diff options
Diffstat (limited to 'arch/blackfin/mach-bf527')
| -rw-r--r-- | arch/blackfin/mach-bf527/Kconfig | 34 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/Makefile | 2 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/boards/cm_bf527.c | 111 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/boards/ezbrd.c | 90 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/boards/ezkit.c | 176 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/dma.c | 2 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/head.S | 146 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/anomaly.h | 10 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/bf527.h | 8 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/bfin_sir.h | 142 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h | 102 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/dma.h | 32 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/gpio.h | 68 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/irq.h | 32 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/mem_init.h | 310 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/mem_map.h | 6 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/ints-priority.c | 16 |
17 files changed, 439 insertions, 848 deletions
diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig index 3cde4beeb214..8438ec6d6679 100644 --- a/arch/blackfin/mach-bf527/Kconfig +++ b/arch/blackfin/mach-bf527/Kconfig @@ -168,29 +168,29 @@ config IRQ_MAC_TX config IRQ_PORTH_INTB int "IRQ_PORTH_INTB" default 11 -config IRQ_TMR0 - int "IRQ_TMR0" - default 12 -config IRQ_TMR1 - int "IRQ_TMR1" +config IRQ_TIMER0 + int "IRQ_TIMER0" + default 8 +config IRQ_TIMER1 + int "IRQ_TIMER1" default 12 -config IRQ_TMR2 - int "IRQ_TMR2" +config IRQ_TIMER2 + int "IRQ_TIMER2" default 12 -config IRQ_TMR3 - int "IRQ_TMR3" +config IRQ_TIMER3 + int "IRQ_TIMER3" default 12 -config IRQ_TMR4 - int "IRQ_TMR4" +config IRQ_TIMER4 + int "IRQ_TIMER4" default 12 -config IRQ_TMR5 - int "IRQ_TMR5" +config IRQ_TIMER5 + int "IRQ_TIMER5" default 12 -config IRQ_TMR6 - int "IRQ_TMR6" +config IRQ_TIMER6 + int "IRQ_TIMER6" default 12 -config IRQ_TMR7 - int "IRQ_TMR7" +config IRQ_TIMER7 + int "IRQ_TIMER7" default 12 config IRQ_PORTG_INTA int "IRQ_PORTG_INTA" diff --git a/arch/blackfin/mach-bf527/Makefile b/arch/blackfin/mach-bf527/Makefile index 4eddb580319c..4a6cdafab8ce 100644 --- a/arch/blackfin/mach-bf527/Makefile +++ b/arch/blackfin/mach-bf527/Makefile @@ -2,6 +2,4 @@ # arch/blackfin/mach-bf527/Makefile # -extra-y := head.o - obj-y := ints-priority.o dma.o diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c index 9ea440bbb13d..a2c3578f4b6c 100644 --- a/arch/blackfin/mach-bf527/boards/cm_bf527.c +++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c @@ -61,51 +61,40 @@ const char bfin_board_name[] = "Bluetechnix CM-BF527"; * Driver needs to know address, irq and flag pin. */ -#define ISP1761_BASE 0x203C0000 -#define ISP1761_IRQ IRQ_PF7 - #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) -static struct resource bfin_isp1761_resources[] = { +#include <linux/usb/isp1760.h> +static struct resource bfin_isp1760_resources[] = { [0] = { - .name = "isp1761-regs", - .start = ISP1761_BASE + 0x00000000, - .end = ISP1761_BASE + 0x000fffff, + .start = 0x203C0000, + .end = 0x203C0000 + 0x000fffff, .flags = IORESOURCE_MEM, }, [1] = { - .start = ISP1761_IRQ, - .end = ISP1761_IRQ, + .start = IRQ_PF7, + .end = IRQ_PF7, .flags = IORESOURCE_IRQ, }, }; -static struct platform_device bfin_isp1761_device = { - .name = "isp1761", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_isp1761_resources), - .resource = bfin_isp1761_resources, +static struct isp1760_platform_data isp1760_priv = { + .is_isp1761 = 0, + .port1_disable = 0, + .bus_width_16 = 1, + .port1_otg = 0, + .analog_oc = 0, + .dack_polarity_high = 0, + .dreq_polarity_high = 0, }; -static struct platform_device *bfin_isp1761_devices[] = { - &bfin_isp1761_device, +static struct platform_device bfin_isp1760_device = { + .name = "isp1760-hcd", + .id = 0, + .dev = { + .platform_data = &isp1760_priv, + }, + .num_resources = ARRAY_SIZE(bfin_isp1760_resources), + .resource = bfin_isp1760_resources, }; - -int __init bfin_isp1761_init(void) -{ - unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices); - - printk(KERN_INFO "%s(): registering device resources\n", __func__); - set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING); - - return platform_add_devices(bfin_isp1761_devices, num_devices); -} - -void __exit bfin_isp1761_exit(void) -{ - platform_device_unregister(&bfin_isp1761_device); -} - -arch_initcall(bfin_isp1761_init); #endif #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) @@ -132,8 +121,8 @@ static struct musb_hdrc_config musb_config = { .dyn_fifo = 0, .soft_con = 1, .dma = 1, - .num_eps = 7, - .dma_channels = 7, + .num_eps = 8, + .dma_channels = 8, .gpio_vrsel = GPIO_PF11, }; @@ -728,30 +717,59 @@ static struct platform_device bfin_uart_device = { #endif #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) -static struct resource bfin_sir_resources[] = { #ifdef CONFIG_BFIN_SIR0 +static struct resource bfin_sir0_resources[] = { { .start = 0xFFC00400, .end = 0xFFC004FF, .flags = IORESOURCE_MEM, }, + { + .start = IRQ_UART0_RX, + .end = IRQ_UART0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART0_RX, + .end = CH_UART0_RX+1, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device bfin_sir0_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir0_resources), + .resource = bfin_sir0_resources, +}; #endif #ifdef CONFIG_BFIN_SIR1 +static struct resource bfin_sir1_resources[] = { { .start = 0xFFC02000, .end = 0xFFC020FF, .flags = IORESOURCE_MEM, }, -#endif + { + .start = IRQ_UART1_RX, + .end = IRQ_UART1_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART1_RX, + .end = CH_UART1_RX+1, + .flags = IORESOURCE_DMA, + }, }; -static struct platform_device bfin_sir_device = { +static struct platform_device bfin_sir1_device = { .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir_resources), - .resource = bfin_sir_resources, + .id = 1, + .num_resources = ARRAY_SIZE(bfin_sir1_resources), + .resource = bfin_sir1_resources, }; #endif +#endif #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) static struct resource bfin_twi0_resource[] = { @@ -885,6 +903,10 @@ static struct platform_device *stamp_devices[] __initdata = { &isp1362_hcd_device, #endif +#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) + &bfin_isp1760_device, +#endif + #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) &musb_device, #endif @@ -918,7 +940,12 @@ static struct platform_device *stamp_devices[] __initdata = { #endif #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) - &bfin_sir_device, +#ifdef CONFIG_BFIN_SIR0 + &bfin_sir0_device, +#endif +#ifdef CONFIG_BFIN_SIR1 + &bfin_sir1_device, +#endif #endif #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c index 36c87b6fbdec..0314bd3355eb 100644 --- a/arch/blackfin/mach-bf527/boards/ezbrd.c +++ b/arch/blackfin/mach-bf527/boards/ezbrd.c @@ -51,7 +51,7 @@ /* * Name the Board for the /proc/cpuinfo */ -const char bfin_board_name[] = "BF526-EZBRD"; +const char bfin_board_name[] = "ADI BF526-EZBRD"; /* * Driver needs to know address, irq and flag pin. @@ -81,8 +81,8 @@ static struct musb_hdrc_config musb_config = { .dyn_fifo = 0, .soft_con = 1, .dma = 1, - .num_eps = 7, - .dma_channels = 7, + .num_eps = 8, + .dma_channels = 8, .gpio_vrsel = GPIO_PG13, }; @@ -288,6 +288,30 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = { }; #endif +#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE) +#include <linux/spi/ad7879.h> +static const struct ad7879_platform_data bfin_ad7879_ts_info = { + .model = 7879, /* Model = AD7879 */ + .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */ + .pressure_max = 10000, + .pressure_min = 0, + .first_conversion_delay = 3, /* wait 512us before do a first conversion */ + .acquisition_time = 1, /* 4us acquisition time per sample */ + .median = 2, /* do 8 measurements */ + .averaging = 1, /* take the average of 4 middle samples */ + .pen_down_acc_interval = 255, /* 9.4 ms */ + .gpio_output = 1, /* configure AUX/VBAT/GPIO as GPIO output */ + .gpio_default = 1, /* During initialization set GPIO = HIGH */ +}; +#endif + +#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) +static struct bfin5xx_spi_chip spi_ad7879_chip_info = { + .enable_dma = 0, + .bits_per_word = 16, +}; +#endif + #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ && defined(CONFIG_SND_SOC_WM8731_SPI) static struct bfin5xx_spi_chip spi_wm8731_chip_info = { @@ -386,6 +410,18 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .controller_data = &spi_ad7877_chip_info, }, #endif +#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) + { + .modalias = "ad7879", + .platform_data = &bfin_ad7879_ts_info, + .irq = IRQ_PG0, + .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, + .controller_data = &spi_ad7879_chip_info, + .mode = SPI_CPHA | SPI_CPOL, + }, +#endif #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ && defined(CONFIG_SND_SOC_WM8731_SPI) { @@ -478,30 +514,59 @@ static struct platform_device bfin_uart_device = { #endif #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) -static struct resource bfin_sir_resources[] = { #ifdef CONFIG_BFIN_SIR0 +static struct resource bfin_sir0_resources[] = { { .start = 0xFFC00400, .end = 0xFFC004FF, .flags = IORESOURCE_MEM, }, + { + .start = IRQ_UART0_RX, + .end = IRQ_UART0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART0_RX, + .end = CH_UART0_RX+1, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device bfin_sir0_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir0_resources), + .resource = bfin_sir0_resources, +}; #endif #ifdef CONFIG_BFIN_SIR1 +static struct resource bfin_sir1_resources[] = { { .start = 0xFFC02000, .end = 0xFFC020FF, .flags = IORESOURCE_MEM, }, -#endif + { + .start = IRQ_UART1_RX, + .end = IRQ_UART1_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART1_RX, + .end = CH_UART1_RX+1, + .flags = IORESOURCE_DMA, + }, }; -static struct platform_device bfin_sir_device = { +static struct platform_device bfin_sir1_device = { .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir_resources), - .resource = bfin_sir_resources, + .id = 1, + .num_resources = ARRAY_SIZE(bfin_sir1_resources), + .resource = bfin_sir1_resources, }; #endif +#endif #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) static struct resource bfin_twi0_resource[] = { @@ -671,7 +736,12 @@ static struct platform_device *stamp_devices[] __initdata = { #endif #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) - &bfin_sir_device, +#ifdef CONFIG_BFIN_SIR0 + &bfin_sir0_device, +#endif +#ifdef CONFIG_BFIN_SIR1 + &bfin_sir1_device, +#endif #endif #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c index 8ee2b744e234..9454fb7b18c3 100644 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/arch/blackfin/mach-bf527/boards/ezkit.c @@ -54,57 +54,46 @@ /* * Name the Board for the /proc/cpuinfo */ -const char bfin_board_name[] = "ADDS-BF527-EZKIT"; +const char bfin_board_name[] = "ADI BF527-EZKIT"; /* * Driver needs to know address, irq and flag pin. */ -#define ISP1761_BASE 0x203C0000 -#define ISP1761_IRQ IRQ_PF7 - #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) -static struct resource bfin_isp1761_resources[] = { +#include <linux/usb/isp1760.h> +static struct resource bfin_isp1760_resources[] = { [0] = { - .name = "isp1761-regs", - .start = ISP1761_BASE + 0x00000000, - .end = ISP1761_BASE + 0x000fffff, + .start = 0x203C0000, + .end = 0x203C0000 + 0x000fffff, .flags = IORESOURCE_MEM, }, [1] = { - .start = ISP1761_IRQ, - .end = ISP1761_IRQ, + .start = IRQ_PF7, + .end = IRQ_PF7, .flags = IORESOURCE_IRQ, }, }; -static struct platform_device bfin_isp1761_device = { - .name = "isp1761", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_isp1761_resources), - .resource = bfin_isp1761_resources, +static struct isp1760_platform_data isp1760_priv = { + .is_isp1761 = 0, + .port1_disable = 0, + .bus_width_16 = 1, + .port1_otg = 0, + .analog_oc = 0, + .dack_polarity_high = 0, + .dreq_polarity_high = 0, }; -static struct platform_device *bfin_isp1761_devices[] = { - &bfin_isp1761_device, +static struct platform_device bfin_isp1760_device = { + .name = "isp1760-hcd", + .id = 0, + .dev = { + .platform_data = &isp1760_priv, + }, + .num_resources = ARRAY_SIZE(bfin_isp1760_resources), + .resource = bfin_isp1760_resources, }; - -int __init bfin_isp1761_init(void) -{ - unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices); - - printk(KERN_INFO "%s(): registering device resources\n", __func__); - set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING); - - return platform_add_devices(bfin_isp1761_devices, num_devices); -} - -void __exit bfin_isp1761_exit(void) -{ - platform_device_unregister(&bfin_isp1761_device); -} - -arch_initcall(bfin_isp1761_init); #endif #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) @@ -131,8 +120,8 @@ static struct musb_hdrc_config musb_config = { .dyn_fifo = 0, .soft_con = 1, .dma = 1, - .num_eps = 7, - .dma_channels = 7, + .num_eps = 8, + .dma_channels = 8, .gpio_vrsel = GPIO_PG13, }; @@ -515,13 +504,6 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = { }; #endif -#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) -static struct bfin5xx_spi_chip spi_mmc_chip_info = { - .enable_dma = 1, - .bits_per_word = 8, -}; -#endif - #if defined(CONFIG_PBX) static struct bfin5xx_spi_chip spi_si3xxx_chip_info = { .ctl_reg = 0x4, /* send zero */ @@ -552,6 +534,30 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = { }; #endif +#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE) +#include <linux/spi/ad7879.h> +static const struct ad7879_platform_data bfin_ad7879_ts_info = { + .model = 7879, /* Model = AD7879 */ + .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */ + .pressure_max = 10000, + .pressure_min = 0, + .first_conversion_delay = 3, /* wait 512us before do a first conversion */ + .acquisition_time = 1, /* 4us acquisition time per sample */ + .median = 2, /* do 8 measurements */ + .averaging = 1, /* take the average of 4 middle samples */ + .pen_down_acc_interval = 255, /* 9.4 ms */ + .gpio_output = 1, /* configure AUX/VBAT/GPIO as GPIO output */ + .gpio_default = 1, /* During initialization set GPIO = HIGH */ +}; +#endif + +#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) +static struct bfin5xx_spi_chip spi_ad7879_chip_info = { + .enable_dma = 0, + .bits_per_word = 16, +}; +#endif + #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ && defined(CONFIG_SND_SOC_WM8731_SPI) static struct bfin5xx_spi_chip spi_wm8731_chip_info = { @@ -613,26 +619,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .controller_data = &ad9960_spi_chip_info, }, #endif -#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) - { - .modalias = "spi_mmc_dummy", - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 0, - .platform_data = NULL, - .controller_data = &spi_mmc_chip_info, - .mode = SPI_MODE_3, - }, - { - .modalias = "spi_mmc", - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = CONFIG_SPI_MMC_CS_CHAN, - .platform_data = NULL, - .controller_data = &spi_mmc_chip_info, - .mode = SPI_MODE_3, - }, -#endif #if defined(CONFIG_PBX) { .modalias = "fxs-spi", @@ -662,6 +648,18 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .controller_data = &spi_ad7877_chip_info, }, #endif +#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) + { + .modalias = "ad7879", + .platform_data = &bfin_ad7879_ts_info, + .irq = IRQ_PF8, + .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 3, + .controller_data = &spi_ad7879_chip_info, + .mode = SPI_CPHA | SPI_CPOL, + }, +#endif #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ && defined(CONFIG_SND_SOC_WM8731_SPI) { @@ -756,30 +754,59 @@ static struct platform_device bfin_uart_device = { #endif #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) -static struct resource bfin_sir_resources[] = { #ifdef CONFIG_BFIN_SIR0 +static struct resource bfin_sir0_resources[] = { { .start = 0xFFC00400, .end = 0xFFC004FF, .flags = IORESOURCE_MEM, }, + { + .start = IRQ_UART0_RX, + .end = IRQ_UART0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART0_RX, + .end = CH_UART0_RX+1, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device bfin_sir0_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir0_resources), + .resource = bfin_sir0_resources, +}; #endif #ifdef CONFIG_BFIN_SIR1 +static struct resource bfin_sir1_resources[] = { { .start = 0xFFC02000, .end = 0xFFC020FF, .flags = IORESOURCE_MEM, }, -#endif + { + .start = IRQ_UART1_RX, + .end = IRQ_UART1_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART1_RX, + .end = CH_UART1_RX+1, + .flags = IORESOURCE_DMA, + }, }; -static struct platform_device bfin_sir_device = { +static struct platform_device bfin_sir1_device = { .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir_resources), - .resource = bfin_sir_resources, + .id = 1, + .num_resources = ARRAY_SIZE(bfin_sir1_resources), + .resource = bfin_sir1_resources, }; #endif +#endif #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) static struct resource bfin_twi0_resource[] = { @@ -944,6 +971,10 @@ static struct platform_device *stamp_devices[] __initdata = { &isp1362_hcd_device, #endif +#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) + &bfin_isp1760_device, +#endif + #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) &musb_device, #endif @@ -985,7 +1016,12 @@ static struct platform_device *stamp_devices[] __initdata = { #endif #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) - &bfin_sir_device, +#ifdef CONFIG_BFIN_SIR0 + &bfin_sir0_device, +#endif +#ifdef CONFIG_BFIN_SIR1 + &bfin_sir1_device, +#endif #endif #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) diff --git a/arch/blackfin/mach-bf527/dma.c b/arch/blackfin/mach-bf527/dma.c index dfd080cda787..231877578243 100644 --- a/arch/blackfin/mach-bf527/dma.c +++ b/arch/blackfin/mach-bf527/dma.c @@ -31,7 +31,7 @@ #include <asm/blackfin.h> #include <asm/dma.h> -struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { +struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { (struct dma_register *) DMA0_NEXT_DESC_PTR, (struct dma_register *) DMA1_NEXT_DESC_PTR, (struct dma_register *) DMA2_NEXT_DESC_PTR, diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S deleted file mode 100644 index 0eb1da85db73..000000000000 --- a/arch/blackfin/mach-bf527/head.S +++ /dev/null @@ -1,146 +0,0 @@ -/* - * File: arch/blackfin/mach-bf527/head.S - * Based on: arch/blackfin/mach-bf533/head.S - * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne - * - * Created: 1998 - * Description: Startup code for Blackfin BF537 - * - * Modified: - * Copyright 2004-2007 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <linux/linkage.h> -#include <linux/init.h> -#include <asm/blackfin.h> -#ifdef CONFIG_BFIN_KERNEL_CLOCK -#include <asm/clocks.h> -#include <mach/mem_init.h> -#endif - -.section .l1.text -#ifdef CONFIG_BFIN_KERNEL_CLOCK -ENTRY(_start_dma_code) - - /* Enable PHY CLK buffer output */ - p0.h = hi(VR_CTL); - p0.l = lo(VR_CTL); - r0.l = w[p0]; - bitset(r0, 14); - w[p0] = r0.l; - ssync; - - p0.h = hi(SIC_IWR0); - p0.l = lo(SIC_IWR0); - r0.l = 0x1; - r0.h = 0x0; - [p0] = r0; - SSYNC; - - /* - * Set PLL_CTL - * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors - * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK - * - [7] = output delay (add 200ps of delay to mem signals) - * - [6] = input delay (add 200ps of input delay to mem signals) - * - [5] = PDWN : 1=All Clocks off - * - [3] = STOPCK : 1=Core Clock off - * - [1] = PLL_OFF : 1=Disable Power to PLL - * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL - * all other bits set to zero - */ - - p0.h = hi(PLL_LOCKCNT); - p0.l = lo(PLL_LOCKCNT); - r0 = 0x300(Z); - w[p0] = r0.l; - ssync; - - P2.H = hi(EBIU_SDGCTL); - P2.L = lo(EBIU_SDGCTL); - R0 = [P2]; - BITSET (R0, 24); - [P2] = R0; - SSYNC; - - r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ - r0 = r0 << 9; /* Shift it over, */ - r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ - r0 = r1 | r0; - r1 = PLL_BYPASS; /* Bypass the PLL? */ - r1 = r1 << 8; /* Shift it over */ - r0 = r1 | r0; /* add them all together */ -#ifdef ANOMALY_05000265 - BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */ -#endif - - p0.h = hi(PLL_CTL); - p0.l = lo(PLL_CTL); /* Load the address */ - cli r2; /* Disable interrupts */ - ssync; - w[p0] = r0.l; /* Set the value */ - idle; /* Wait for the PLL to stablize */ - sti r2; /* Enable interrupts */ - -.Lcheck_again: - p0.h = hi(PLL_STAT); - p0.l = lo(PLL_STAT); - R0 = W[P0](Z); - CC = BITTST(R0,5); - if ! CC jump .Lcheck_again; - - /* Configure SCLK & CCLK Dividers */ - r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); - p0.h = hi(PLL_DIV); - p0.l = lo(PLL_DIV); - w[p0] = r0.l; - ssync; - - p0.l = lo(EBIU_SDRRC); - p0.h = hi(EBIU_SDRRC); - r0 = mem_SDRRC; - w[p0] = r0.l; - ssync; - - P2.H = hi(EBIU_SDGCTL); - P2.L = lo(EBIU_SDGCTL); - R0 = [P2]; - BITCLR (R0, 24); - p0.h = hi(EBIU_SDSTAT); - p0.l = lo(EBIU_SDSTAT); - r2.l = w[p0]; - cc = bittst(r2,3); - if !cc jump .Lskip; - NOP; - BITSET (R0, 23); -.Lskip: - [P2] = R0; - SSYNC; - - R0.L = lo(mem_SDGCTL); - R0.H = hi(mem_SDGCTL); - R1 = [p2]; - R1 = R1 | R0; - [P2] = R1; - SSYNC; - - RTS; -ENDPROC(_start_dma_code) -#endif /* CONFIG_BFIN_KERNEL_CLOCK */ diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h index 62373e61c585..035e8d835058 100644 --- a/arch/blackfin/mach-bf527/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h @@ -28,7 +28,7 @@ /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ -#define ANOMALY_05000119 (1) +#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ @@ -37,8 +37,6 @@ #define ANOMALY_05000265 (1) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (ANOMALY_BF527) /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (__SILICON_REVISION__ < 2) /* Incorrect Access of OTP_STATUS During otp_write() Function */ @@ -153,6 +151,10 @@ #define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ #define ANOMALY_05000432 (ANOMALY_BF526) +/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ +#define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527) +/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ +#define ANOMALY_05000443 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) @@ -168,7 +170,9 @@ #define ANOMALY_05000285 (0) #define ANOMALY_05000307 (0) #define ANOMALY_05000311 (0) +#define ANOMALY_05000312 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000363 (0) +#define ANOMALY_05000412 (0) #endif diff --git a/arch/blackfin/mach-bf527/include/mach/bf527.h b/arch/blackfin/mach-bf527/include/mach/bf527.h index 144f08d3f8ea..3832aab11e9a 100644 --- a/arch/blackfin/mach-bf527/include/mach/bf527.h +++ b/arch/blackfin/mach-bf527/include/mach/bf527.h @@ -110,7 +110,7 @@ #ifdef CONFIG_BF527 #define CPU "BF527" -#define CPUID 0x27e4 +#define CPUID 0x27e0 #endif #ifdef CONFIG_BF526 #define CPU "BF526" @@ -118,7 +118,7 @@ #endif #ifdef CONFIG_BF525 #define CPU "BF525" -#define CPUID 0x27e4 +#define CPUID 0x27e0 #endif #ifdef CONFIG_BF524 #define CPU "BF524" @@ -126,7 +126,7 @@ #endif #ifdef CONFIG_BF523 #define CPU "BF523" -#define CPUID 0x27e4 +#define CPUID 0x27e0 #endif #ifdef CONFIG_BF522 #define CPU "BF522" @@ -134,7 +134,7 @@ #endif #ifndef CPU -#error Unknown CPU type - This kernel doesn't seem to be configured properly +#error "Unknown CPU type - This kernel doesn't seem to be configured properly" #endif #endif /* __MACH_BF527_H__ */ diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_sir.h b/arch/blackfin/mach-bf527/include/mach/bfin_sir.h deleted file mode 100644 index cfd8ad4f1f2c..000000000000 --- a/arch/blackfin/mach-bf527/include/mach/bfin_sir.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Blackfin Infra-red Driver - * - * Copyright 2006-2008 Analog Devices Inc. - * - * Enter bugs at http://blackfin.uclinux.org/ - * - * Licensed under the GPL-2 or later. - * - */ - -#include <linux/serial.h> -#include <asm/dma.h> -#include <asm/portmux.h> - -#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR) -#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL) -#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER) -#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH) -#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR) -#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR) -#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL) - -#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v) -#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v) -#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v) -#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v) -#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v) -#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v) - -#ifdef CONFIG_SIR_BFIN_DMA -struct dma_rx_buf { - char *buf; - int head; - int tail; - }; -#endif /* CONFIG_SIR_BFIN_DMA */ - -struct bfin_sir_port { - unsigned char __iomem *membase; - unsigned int irq; - unsigned int lsr; - unsigned long clk; - struct net_device *dev; -#ifdef CONFIG_SIR_BFIN_DMA - int tx_done; - struct dma_rx_buf rx_dma_buf; - struct timer_list rx_dma_timer; - int rx_dma_nrows; -#endif /* CONFIG_SIR_BFIN_DMA */ - unsigned int tx_dma_channel; - unsigned int rx_dma_channel; -}; - -struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS]; - -struct bfin_sir_port_res { - unsigned long base_addr; - int irq; - unsigned int rx_dma_channel; - unsigned int tx_dma_channel; -}; - -struct bfin_sir_port_res bfin_sir_port_resource[] = { -#ifdef CONFIG_BFIN_SIR0 - { - 0xFFC00400, - IRQ_UART0_RX, - CH_UART0_RX, - CH_UART0_TX, - }, -#endif -#ifdef CONFIG_BFIN_SIR1 - { - 0xFFC02000, - IRQ_UART1_RX, - CH_UART1_RX, - CH_UART1_TX, - }, -#endif -}; - -int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource); - -struct bfin_sir_self { - struct bfin_sir_port *sir_port; - spinlock_t lock; - unsigned int open; - int speed; - int newspeed; - - struct sk_buff *txskb; - struct sk_buff *rxskb; - struct net_device_stats stats; - struct device *dev; - struct irlap_cb *irlap; - struct qos_info qos; - - iobuff_t tx_buff; - iobuff_t rx_buff; - - struct work_struct work; - int mtt; -}; - -static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port) -{ - unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR); - port->lsr |= (lsr & (BI|FE|PE|OE)); - return lsr | port->lsr; -} - -static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port) -{ - port->lsr = 0; - bfin_read16(port->membase + OFFSET_LSR); -} - -#define DRIVER_NAME "bfin_sir" - -static int bfin_sir_hw_init(void) -{ - int ret = -ENODEV; -#ifdef CONFIG_BFIN_SIR0 - ret = peripheral_request(P_UART0_TX, DRIVER_NAME); - if (ret) - return ret; - ret = peripheral_request(P_UART0_RX, DRIVER_NAME); - if (ret) - return ret; -#endif - -#ifdef CONFIG_BFIN_SIR1 - ret = peripheral_request(P_UART1_TX, DRIVER_NAME); - if (ret) - return ret; - ret = peripheral_request(P_UART1_RX, DRIVER_NAME); - if (ret) - return ret; -#endif - return ret; -} diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h index 9a814b9a12b9..1fe76d8e0403 100644 --- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h +++ b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h @@ -31,7 +31,6 @@ #ifndef _CDEF_BF52X_H #define _CDEF_BF52X_H -#include <asm/system.h> #include <asm/blackfin.h> #include "defBF52x_base.h" @@ -43,57 +42,9 @@ /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -/* Writing to PLL_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_PLL_CTL(unsigned int val) -{ - unsigned long flags, iwr0, iwr1; - - if (val == bfin_read_PLL_CTL()) - return; - - local_irq_save(flags); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr0 = bfin_read32(SIC_IWR0); - iwr1 = bfin_read32(SIC_IWR1); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR0, IWR_ENABLE(0)); - bfin_write32(SIC_IWR1, 0); - - bfin_write16(PLL_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR0, iwr0); - bfin_write32(SIC_IWR1, iwr1); - local_irq_restore(flags); -} #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) #define bfin_read_VR_CTL() bfin_read16(VR_CTL) -/* Writing to VR_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_VR_CTL(unsigned int val) -{ - unsigned long flags, iwr0, iwr1; - - if (val == bfin_read_VR_CTL()) - return; - - local_irq_save(flags); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr0 = bfin_read32(SIC_IWR0); - iwr1 = bfin_read32(SIC_IWR1); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR0, IWR_ENABLE(0)); - bfin_write32(SIC_IWR1, 0); - - bfin_write16(VR_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR0, iwr0); - bfin_write32(SIC_IWR1, iwr1); - local_irq_restore(flags); -} #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) @@ -1201,4 +1152,57 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) #define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) +/* These need to be last due to the cdef/linux inter-dependencies */ +#include <asm/irq.h> + +/* Writing to PLL_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_PLL_CTL(unsigned int val) +{ + unsigned long flags, iwr0, iwr1; + + if (val == bfin_read_PLL_CTL()) + return; + + local_irq_save_hw(flags); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr0 = bfin_read32(SIC_IWR0); + iwr1 = bfin_read32(SIC_IWR1); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR0, IWR_ENABLE(0)); + bfin_write32(SIC_IWR1, 0); + + bfin_write16(PLL_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SIC_IWR0, iwr0); + bfin_write32(SIC_IWR1, iwr1); + local_irq_restore_hw(flags); +} + +/* Writing to VR_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_VR_CTL(unsigned int val) +{ + unsigned long flags, iwr0, iwr1; + + if (val == bfin_read_VR_CTL()) + return; + + local_irq_save_hw(flags); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr0 = bfin_read32(SIC_IWR0); + iwr1 = bfin_read32(SIC_IWR1); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR0, IWR_ENABLE(0)); + bfin_write32(SIC_IWR1, 0); + + bfin_write16(VR_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SIC_IWR0, iwr0); + bfin_write32(SIC_IWR1, iwr1); + local_irq_restore_hw(flags); +} + #endif /* _CDEF_BF52X_H */ diff --git a/arch/blackfin/mach-bf527/include/mach/dma.h b/arch/blackfin/mach-bf527/include/mach/dma.h index 49dd693223e8..eb287da101a2 100644 --- a/arch/blackfin/mach-bf527/include/mach/dma.h +++ b/arch/blackfin/mach-bf527/include/mach/dma.h @@ -1,38 +1,14 @@ -/* - * file: include/asm-blackfin/mach-bf527/dma.h - * based on: include/asm-blackfin/mach-bf537/dma.h - * author: Michael Hennerich (michael.hennerich@analog.com) +/* mach/dma.h - arch-specific DMA defines * - * created: - * description: - * system DMA map - * rev: + * Copyright 2004-2008 Analog Devices Inc. * - * modified: - * - * - * bugs: enter bugs at http://blackfin.uclinux.org/ - * - * this program is free software; you can redistribute it and/or modify - * it under the terms of the gnu general public license as published by - * the free software foundation; either version 2, or (at your option) - * any later version. - * - * this program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * merchantability or fitness for a particular purpose. see the - * gnu general public license for more details. - * - * you should have received a copy of the gnu general public license - * along with this program; see the file copying. - * if not, write to the free software foundation, - * 59 temple place - suite 330, boston, ma 02111-1307, usa. + * Licensed under the GPL-2 or later. */ #ifndef _MACH_DMA_H_ #define _MACH_DMA_H_ -#define MAX_BLACKFIN_DMA_CHANNEL 16 +#define MAX_DMA_CHANNELS 16 #define CH_PPI 0 /* PPI receive/transmit or NFC */ #define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */ diff --git a/arch/blackfin/mach-bf527/include/mach/gpio.h b/arch/blackfin/mach-bf527/include/mach/gpio.h new file mode 100644 index 000000000000..06b6eebf0d49 --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/gpio.h @@ -0,0 +1,68 @@ +/* + * File: arch/blackfin/mach-bf527/include/mach/gpio.h + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * Copyright (C) 2008 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + + +#ifndef _MACH_GPIO_H_ +#define _MACH_GPIO_H_ + +#define MAX_BLACKFIN_GPIOS 48 + +#define GPIO_PF0 0 +#define GPIO_PF1 1 +#define GPIO_PF2 2 +#define GPIO_PF3 3 +#define GPIO_PF4 4 +#define GPIO_PF5 5 +#define GPIO_PF6 6 +#define GPIO_PF7 7 +#define GPIO_PF8 8 +#define GPIO_PF9 9 +#define GPIO_PF10 10 +#define GPIO_PF11 11 +#define GPIO_PF12 12 +#define GPIO_PF13 13 +#define GPIO_PF14 14 +#define GPIO_PF15 15 +#define GPIO_PG0 16 +#define GPIO_PG1 17 +#define GPIO_PG2 18 +#define GPIO_PG3 19 +#define GPIO_PG4 20 +#define GPIO_PG5 21 +#define GPIO_PG6 22 +#define GPIO_PG7 23 +#define GPIO_PG8 24 +#define GPIO_PG9 25 +#define GPIO_PG10 26 +#define GPIO_PG11 27 +#define GPIO_PG12 28 +#define GPIO_PG13 29 +#define GPIO_PG14 30 +#define GPIO_PG15 31 +#define GPIO_PH0 32 +#define GPIO_PH1 33 +#define GPIO_PH2 34 +#define GPIO_PH3 35 +#define GPIO_PH4 36 +#define GPIO_PH5 37 +#define GPIO_PH6 38 +#define GPIO_PH7 39 +#define GPIO_PH8 40 +#define GPIO_PH9 41 +#define GPIO_PH10 42 +#define GPIO_PH11 43 +#define GPIO_PH12 44 +#define GPIO_PH13 45 +#define GPIO_PH14 46 +#define GPIO_PH15 47 + +#define PORT_F GPIO_PF0 +#define PORT_G GPIO_PG0 +#define PORT_H GPIO_PH0 + +#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/mach-bf527/include/mach/irq.h b/arch/blackfin/mach-bf527/include/mach/irq.h index 4e2b3f2020e5..8ea660d8151f 100644 --- a/arch/blackfin/mach-bf527/include/mach/irq.h +++ b/arch/blackfin/mach-bf527/include/mach/irq.h @@ -96,14 +96,14 @@ #define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ #define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ #define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */ -#define IRQ_TMR0 BFIN_IRQ(32) /* Timer 0 */ -#define IRQ_TMR1 BFIN_IRQ(33) /* Timer 1 */ -#define IRQ_TMR2 BFIN_IRQ(34) /* Timer 2 */ -#define IRQ_TMR3 BFIN_IRQ(35) /* Timer 3 */ -#define IRQ_TMR4 BFIN_IRQ(36) /* Timer 4 */ -#define IRQ_TMR5 BFIN_IRQ(37) /* Timer 5 */ -#define IRQ_TMR6 BFIN_IRQ(38) /* Timer 6 */ -#define IRQ_TMR7 BFIN_IRQ(39) /* Timer 7 */ +#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */ +#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */ +#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */ +#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */ +#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */ +#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */ +#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */ +#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */ #define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */ #define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */ #define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */ @@ -227,14 +227,14 @@ #define IRQ_PORTH_INTB_POS 28 /* IAR4 BIT FIELDS */ -#define IRQ_TMR0_POS 0 -#define IRQ_TMR1_POS 4 -#define IRQ_TMR2_POS 8 -#define IRQ_TMR3_POS 12 -#define IRQ_TMR4_POS 16 -#define IRQ_TMR5_POS 20 -#define IRQ_TMR6_POS 24 -#define IRQ_TMR7_POS 28 +#define IRQ_TIMER0_POS 0 +#define IRQ_TIMER1_POS 4 +#define IRQ_TIMER2_POS 8 +#define IRQ_TIMER3_POS 12 +#define IRQ_TIMER4_POS 16 +#define IRQ_TIMER5_POS 20 +#define IRQ_TIMER6_POS 24 +#define IRQ_TIMER7_POS 28 /* IAR5 BIT FIELDS */ #define IRQ_PORTG_INTA_POS 0 diff --git a/arch/blackfin/mach-bf527/include/mach/mem_init.h b/arch/blackfin/mach-bf527/include/mach/mem_init.h deleted file mode 100644 index cbe03f4a5698..000000000000 --- a/arch/blackfin/mach-bf527/include/mach/mem_init.h +++ /dev/null @@ -1,310 +0,0 @@ -/* - * File: include/asm-blackfin/mach-bf527/mem_init.h - * Based on: - * Author: - * - * Created: - * Description: - * - * Rev: - * - * Modified: - * Copyright 2004-2007 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75 || CONFIG_MEM_MT48LC32M16A2TG_75) -#if (CONFIG_SCLK_HZ > 119402985) -#define SDRAM_tRP TRP_2 -#define SDRAM_tRP_num 2 -#define SDRAM_tRAS TRAS_7 -#define SDRAM_tRAS_num 7 -#define SDRAM_tRCD TRCD_2 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985) -#define SDRAM_tRP TRP_2 -#define SDRAM_tRP_num 2 -#define SDRAM_tRAS TRAS_6 -#define SDRAM_tRAS_num 6 -#define SDRAM_tRCD TRCD_2 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612) -#define SDRAM_tRP TRP_2 -#define SDRAM_tRP_num 2 -#define SDRAM_tRAS TRAS_5 -#define SDRAM_tRAS_num 5 -#define SDRAM_tRCD TRCD_2 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239) -#define SDRAM_tRP TRP_2 -#define SDRAM_tRP_num 2 -#define SDRAM_tRAS TRAS_4 -#define SDRAM_tRAS_num 4 -#define SDRAM_tRCD TRCD_2 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866) -#define SDRAM_tRP TRP_2 -#define SDRAM_tRP_num 2 -#define SDRAM_tRAS TRAS_3 -#define SDRAM_tRAS_num 3 -#define SDRAM_tRCD TRCD_2 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667) -#define SDRAM_tRP TRP_1 -#define SDRAM_tRP_num 1 -#define SDRAM_tRAS TRAS_4 -#define SDRAM_tRAS_num 3 -#define SDRAM_tRCD TRCD_1 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493) -#define SDRAM_tRP TRP_1 -#define SDRAM_tRP_num 1 -#define SDRAM_tRAS TRAS_3 -#define SDRAM_tRAS_num 3 -#define SDRAM_tRCD TRCD_1 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119) -#define SDRAM_tRP TRP_1 -#define SDRAM_tRP_num 1 -#define SDRAM_tRAS TRAS_2 -#define SDRAM_tRAS_num 2 -#define SDRAM_tRCD TRCD_1 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ <= 29850746) -#define SDRAM_tRP TRP_1 -#define SDRAM_tRP_num 1 -#define SDRAM_tRAS TRAS_1 -#define SDRAM_tRAS_num 1 -#define SDRAM_tRCD TRCD_1 -#define SDRAM_tWR TWR_2 -#endif -#endif - -#if (CONFIG_MEM_MT48LC16M16A2TG_75) - /*SDRAM INFORMATION: */ -#define SDRAM_Tref 64 /* Refresh period in milliseconds */ -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ -#define SDRAM_CL CL_3 -#endif - -#if (CONFIG_MEM_MT48LC16M8A2TG_75) - /*SDRAM INFORMATION: */ -#define SDRAM_Tref 64 /* Refresh period in milliseconds */ -#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ -#define SDRAM_CL CL_3 -#endif - -#if (CONFIG_MEM_MT48LC32M8A2_75) - /*SDRAM INFORMATION: */ -#define SDRAM_Tref 64 /* Refresh period in milliseconds */ -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ -#define SDRAM_CL CL_3 -#endif - -#if (CONFIG_MEM_MT48LC64M4A2FB_7E) - /*SDRAM INFORMATION: */ -#define SDRAM_Tref 64 /* Refresh period in milliseconds */ -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ -#define SDRAM_CL CL_3 -#endif - -#if (CONFIG_MEM_GENERIC_BOARD) - /*SDRAM INFORMATION: Modify this for your board */ -#define SDRAM_Tref 64 /* Refresh period in milliseconds */ -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ -#define SDRAM_CL CL_3 -#endif - -#if (CONFIG_MEM_MT48LC32M16A2TG_75) - /*SDRAM INFORMATION: */ -#define SDRAM_Tref 64 /* Refresh period in milliseconds */ -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ -#define SDRAM_CL CL_3 -#endif - -/* Equation from section 17 (p17-46) of BF533 HRM */ -#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) - -/* Enable SCLK Out */ -#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS) - -#if defined CONFIG_CLKIN_HALF -#define CLKIN_HALF 1 -#else -#define CLKIN_HALF 0 -#endif - -#if defined CONFIG_PLL_BYPASS -#define PLL_BYPASS 1 -#else -#define PLL_BYPASS 0 -#endif - -/***************************************Currently Not Being Used *********************************/ -#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 -#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 -#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ)) -#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 -#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 - -#if (flash_EBIU_AMBCTL_TT > 3) -#define flash_EBIU_AMBCTL0_TT B0TT_4 -#endif -#if (flash_EBIU_AMBCTL_TT == 3) -#define flash_EBIU_AMBCTL0_TT B0TT_3 -#endif -#if (flash_EBIU_AMBCTL_TT == 2) -#define flash_EBIU_AMBCTL0_TT B0TT_2 -#endif -#if (flash_EBIU_AMBCTL_TT < 2) -#define flash_EBIU_AMBCTL0_TT B0TT_1 -#endif - -#if (flash_EBIU_AMBCTL_ST > 3) -#define flash_EBIU_AMBCTL0_ST B0ST_4 -#endif -#if (flash_EBIU_AMBCTL_ST == 3) -#define flash_EBIU_AMBCTL0_ST B0ST_3 -#endif -#if (flash_EBIU_AMBCTL_ST == 2) -#define flash_EBIU_AMBCTL0_ST B0ST_2 -#endif -#if (flash_EBIU_AMBCTL_ST < 2) -#define flash_EBIU_AMBCTL0_ST B0ST_1 -#endif - -#if (flash_EBIU_AMBCTL_HT > 2) -#define flash_EBIU_AMBCTL0_HT B0HT_3 -#endif -#if (flash_EBIU_AMBCTL_HT == 2) -#define flash_EBIU_AMBCTL0_HT B0HT_2 -#endif -#if (flash_EBIU_AMBCTL_HT == 1) -#define flash_EBIU_AMBCTL0_HT B0HT_1 -#endif -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0) -#define flash_EBIU_AMBCTL0_HT B0HT_0 -#endif -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0) -#define flash_EBIU_AMBCTL0_HT B0HT_1 -#endif - -#if (flash_EBIU_AMBCTL_WAT > 14) -#define flash_EBIU_AMBCTL0_WAT B0WAT_15 -#endif -#if (flash_EBIU_AMBCTL_WAT == 14) -#define flash_EBIU_AMBCTL0_WAT B0WAT_14 -#endif -#if (flash_EBIU_AMBCTL_WAT == 13) -#define flash_EBIU_AMBCTL0_WAT B0WAT_13 -#endif -#if (flash_EBIU_AMBCTL_WAT == 12) -#define flash_EBIU_AMBCTL0_WAT B0WAT_12 -#endif -#if (flash_EBIU_AMBCTL_WAT == 11) -#define flash_EBIU_AMBCTL0_WAT B0WAT_11 -#endif -#if (flash_EBIU_AMBCTL_WAT == 10) -#define flash_EBIU_AMBCTL0_WAT B0WAT_10 -#endif -#if (flash_EBIU_AMBCTL_WAT == 9) -#define flash_EBIU_AMBCTL0_WAT B0WAT_9 -#endif -#if (flash_EBIU_AMBCTL_WAT == 8) -#define flash_EBIU_AMBCTL0_WAT B0WAT_8 -#endif -#if (flash_EBIU_AMBCTL_WAT == 7) -#define flash_EBIU_AMBCTL0_WAT B0WAT_7 -#endif -#if (flash_EBIU_AMBCTL_WAT == 6) -#define flash_EBIU_AMBCTL0_WAT B0WAT_6 -#endif -#if (flash_EBIU_AMBCTL_WAT == 5) -#define flash_EBIU_AMBCTL0_WAT B0WAT_5 -#endif -#if (flash_EBIU_AMBCTL_WAT == 4) -#define flash_EBIU_AMBCTL0_WAT B0WAT_4 -#endif -#if (flash_EBIU_AMBCTL_WAT == 3) -#define flash_EBIU_AMBCTL0_WAT B0WAT_3 -#endif -#if (flash_EBIU_AMBCTL_WAT == 2) -#define flash_EBIU_AMBCTL0_WAT B0WAT_2 -#endif -#if (flash_EBIU_AMBCTL_WAT == 1) -#define flash_EBIU_AMBCTL0_WAT B0WAT_1 -#endif - -#if (flash_EBIU_AMBCTL_RAT > 14) -#define flash_EBIU_AMBCTL0_RAT B0RAT_15 -#endif -#if (flash_EBIU_AMBCTL_RAT == 14) -#define flash_EBIU_AMBCTL0_RAT B0RAT_14 -#endif -#if (flash_EBIU_AMBCTL_RAT == 13) -#define flash_EBIU_AMBCTL0_RAT B0RAT_13 -#endif -#if (flash_EBIU_AMBCTL_RAT == 12) -#define flash_EBIU_AMBCTL0_RAT B0RAT_12 -#endif -#if (flash_EBIU_AMBCTL_RAT == 11) -#define flash_EBIU_AMBCTL0_RAT B0RAT_11 -#endif -#if (flash_EBIU_AMBCTL_RAT == 10) -#define flash_EBIU_AMBCTL0_RAT B0RAT_10 -#endif -#if (flash_EBIU_AMBCTL_RAT == 9) -#define flash_EBIU_AMBCTL0_RAT B0RAT_9 -#endif -#if (flash_EBIU_AMBCTL_RAT == 8) -#define flash_EBIU_AMBCTL0_RAT B0RAT_8 -#endif -#if (flash_EBIU_AMBCTL_RAT == 7) -#define flash_EBIU_AMBCTL0_RAT B0RAT_7 -#endif -#if (flash_EBIU_AMBCTL_RAT == 6) -#define flash_EBIU_AMBCTL0_RAT B0RAT_6 -#endif -#if (flash_EBIU_AMBCTL_RAT == 5) -#define flash_EBIU_AMBCTL0_RAT B0RAT_5 -#endif -#if (flash_EBIU_AMBCTL_RAT == 4) -#define flash_EBIU_AMBCTL0_RAT B0RAT_4 -#endif -#if (flash_EBIU_AMBCTL_RAT == 3) -#define flash_EBIU_AMBCTL0_RAT B0RAT_3 -#endif -#if (flash_EBIU_AMBCTL_RAT == 2) -#define flash_EBIU_AMBCTL0_RAT B0RAT_2 -#endif -#if (flash_EBIU_AMBCTL_RAT == 1) -#define flash_EBIU_AMBCTL0_RAT B0RAT_1 -#endif - -#define flash_EBIU_AMBCTL0 \ - (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \ - flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN) diff --git a/arch/blackfin/mach-bf527/include/mach/mem_map.h b/arch/blackfin/mach-bf527/include/mach/mem_map.h index ef46dc991cd4..019e0017ad81 100644 --- a/arch/blackfin/mach-bf527/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf527/include/mach/mem_map.h @@ -99,4 +99,10 @@ #define L1_SCRATCH_START 0xFFB00000 #define L1_SCRATCH_LENGTH 0x1000 +#define GET_PDA_SAFE(preg) \ + preg.l = _cpu_pda; \ + preg.h = _cpu_pda; + +#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) + #endif /* _MEM_MAP_527_H_ */ diff --git a/arch/blackfin/mach-bf527/ints-priority.c b/arch/blackfin/mach-bf527/ints-priority.c index 8a2367403d2b..f8c8acd73e30 100644 --- a/arch/blackfin/mach-bf527/ints-priority.c +++ b/arch/blackfin/mach-bf527/ints-priority.c @@ -69,14 +69,14 @@ void __init program_IAR(void) ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) | ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS)); - bfin_write_SIC_IAR4(((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) | - ((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) | - ((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) | - ((CONFIG_IRQ_TMR3 - 7) << IRQ_TMR3_POS) | - ((CONFIG_IRQ_TMR4 - 7) << IRQ_TMR4_POS) | - ((CONFIG_IRQ_TMR5 - 7) << IRQ_TMR5_POS) | - ((CONFIG_IRQ_TMR6 - 7) << IRQ_TMR6_POS) | - ((CONFIG_IRQ_TMR7 - 7) << IRQ_TMR7_POS)); + bfin_write_SIC_IAR4(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) | + ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) | + ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) | + ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) | + ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) | + ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | + ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) | + ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS)); bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) | ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) | |