diff options
Diffstat (limited to 'arch/mips/boot')
44 files changed, 1210 insertions, 199 deletions
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile index f27cf31b4140..6cc28173bee8 100644 --- a/arch/mips/boot/compressed/Makefile +++ b/arch/mips/boot/compressed/Makefile @@ -38,6 +38,7 @@ KBUILD_AFLAGS := $(KBUILD_AFLAGS) -D__ASSEMBLY__ \ KCOV_INSTRUMENT := n GCOV_PROFILE := n UBSAN_SANITIZE := n +KCSAN_SANITIZE := n # decompressor objects (linked with vmlinuz) vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/string.o $(obj)/bswapsi.o @@ -52,7 +53,7 @@ endif vmlinuzobjs-$(CONFIG_KERNEL_XZ) += $(obj)/ashldi3.o -vmlinuzobjs-$(CONFIG_KERNEL_ZSTD) += $(obj)/bswapdi.o $(obj)/ashldi3.o +vmlinuzobjs-$(CONFIG_KERNEL_ZSTD) += $(obj)/bswapdi.o $(obj)/ashldi3.o $(obj)/clz_ctz.o targets := $(notdir $(vmlinuzobjs-y)) @@ -64,12 +65,12 @@ $(obj)/vmlinux.bin: $(KBUILD_IMAGE) FORCE $(call if_changed,objcopy) tool_$(CONFIG_KERNEL_GZIP) = gzip -tool_$(CONFIG_KERNEL_BZIP2) = bzip2 -tool_$(CONFIG_KERNEL_LZ4) = lz4 -tool_$(CONFIG_KERNEL_LZMA) = lzma -tool_$(CONFIG_KERNEL_LZO) = lzo -tool_$(CONFIG_KERNEL_XZ) = xzkern -tool_$(CONFIG_KERNEL_ZSTD) = zstd22 +tool_$(CONFIG_KERNEL_BZIP2) = bzip2_with_size +tool_$(CONFIG_KERNEL_LZ4) = lz4_with_size +tool_$(CONFIG_KERNEL_LZMA) = lzma_with_size +tool_$(CONFIG_KERNEL_LZO) = lzo_with_size +tool_$(CONFIG_KERNEL_XZ) = xzkern_with_size +tool_$(CONFIG_KERNEL_ZSTD) = zstd22_with_size targets += vmlinux.bin.z @@ -89,6 +90,10 @@ HOSTCFLAGS_calc_vmlinuz_load_addr.o += $(LINUXINCLUDE) # Calculate the load address of the compressed kernel image hostprogs := calc_vmlinuz_load_addr +ifneq (0x0,$(CONFIG_ZBOOT_LOAD_ADDRESS)) +zload-y = $(CONFIG_ZBOOT_LOAD_ADDRESS) +endif + ifneq ($(zload-y),) VMLINUZ_LOAD_ADDRESS := $(zload-y) else diff --git a/arch/mips/boot/compressed/clz_ctz.c b/arch/mips/boot/compressed/clz_ctz.c new file mode 100644 index 000000000000..b4a1b6eb2f8a --- /dev/null +++ b/arch/mips/boot/compressed/clz_ctz.c @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "../../../../lib/clz_ctz.c" diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c index aae1346a509a..c5dd415254d3 100644 --- a/arch/mips/boot/compressed/decompress.c +++ b/arch/mips/boot/compressed/decompress.c @@ -9,6 +9,7 @@ #define DISABLE_BRANCH_PROFILING +#define __NO_FORTIFY #include <linux/types.h> #include <linux/kernel.h> #include <linux/string.h> @@ -26,7 +27,7 @@ unsigned long free_mem_ptr; unsigned long free_mem_end_ptr; /* The linker tells us where the image is. */ -extern unsigned char __image_begin, __image_end; +extern unsigned char __image_begin[], __image_end[]; /* debug interfaces */ #ifdef CONFIG_DEBUG_ZBOOT @@ -91,9 +92,9 @@ void decompress_kernel(unsigned long boot_heap_start) { unsigned long zimage_start, zimage_size; - zimage_start = (unsigned long)(&__image_begin); - zimage_size = (unsigned long)(&__image_end) - - (unsigned long)(&__image_begin); + zimage_start = (unsigned long)(__image_begin); + zimage_size = (unsigned long)(__image_end) - + (unsigned long)(__image_begin); puts("zimage at: "); puthex(zimage_start); @@ -121,7 +122,7 @@ void decompress_kernel(unsigned long boot_heap_start) dtb_size = fdt_totalsize((void *)&__appended_dtb); /* last four bytes is always image size in little endian */ - image_size = get_unaligned_le32((void *)&__image_end - 4); + image_size = get_unaligned_le32((void *)__image_end - 4); /* The device tree's address must be properly aligned */ image_size = ALIGN(image_size, STRUCT_ALIGNMENT); diff --git a/arch/mips/boot/dts/brcm/bcm63268.dtsi b/arch/mips/boot/dts/brcm/bcm63268.dtsi index c3ce49ec675f..8926417a8fbc 100644 --- a/arch/mips/boot/dts/brcm/bcm63268.dtsi +++ b/arch/mips/boot/dts/brcm/bcm63268.dtsi @@ -105,14 +105,20 @@ interrupts = <2>, <3>; }; - wdt: watchdog@1000009c { - compatible = "brcm,bcm7038-wdt"; - reg = <0x1000009c 0xc>; + timer-mfd@10000080 { + compatible = "brcm,bcm7038-twd", "simple-mfd", "syscon"; + reg = <0x10000080 0x30>; + ranges = <0x0 0x10000080 0x30>; - clocks = <&periph_osc>; - clock-names = "refclk"; + wdt: watchdog@1c { + compatible = "brcm,bcm7038-wdt"; + reg = <0x1c 0xc>; - timeout-sec = <30>; + clocks = <&periph_osc>; + clock-names = "refclk"; + + timeout-sec = <30>; + }; }; uart0: serial@10000180 { diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi b/arch/mips/boot/dts/brcm/bcm7425.dtsi index aa0b2d39c902..62588c53d356 100644 --- a/arch/mips/boot/dts/brcm/bcm7425.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi @@ -584,4 +584,34 @@ }; }; }; + + pcie_0: pcie@8b20000 { + status = "disabled"; + compatible = "brcm,bcm7425-pcie"; + + ranges = <0x02000000 0x0 0xd0000000 0xd0000000 0x0 0x08000000 + 0x02000000 0x0 0xd8000000 0xd8000000 0x0 0x08000000 + 0x02000000 0x0 0xe0000000 0xe0000000 0x0 0x08000000 + 0x02000000 0x0 0xe8000000 0xe8000000 0x0 0x08000000>; + + reg = <0x10410000 0x19310>; + aspm-no-l0s; + device_type = "pci"; + msi-controller; + msi-parent = <&pcie_0>; + #address-cells = <0x3>; + #size-cells = <0x2>; + bus-range = <0x0 0xff>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + linux,pci-domain = <0x0>; + + interrupt-parent = <&periph_intc>; + interrupts = <37>, <37>; + interrupt-names = "pcie", "msi"; + #interrupt-cells = <0x1>; + interrupt-map = <0 0 0 1 &periph_intc 0x21 + 0 0 0 1 &periph_intc 0x22 + 0 0 0 1 &periph_intc 0x23 + 0 0 0 1 &periph_intc 0x24>; + }; }; diff --git a/arch/mips/boot/dts/brcm/bcm7435.dtsi b/arch/mips/boot/dts/brcm/bcm7435.dtsi index 8398b7f68bf4..8c001b944c8b 100644 --- a/arch/mips/boot/dts/brcm/bcm7435.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7435.dtsi @@ -599,4 +599,34 @@ }; }; }; + + pcie_0: pcie@8b20000 { + status = "disabled"; + compatible = "brcm,bcm7435-pcie"; + + ranges = <0x02000000 0x0 0xd0000000 0xd0000000 0x0 0x08000000 + 0x02000000 0x0 0xd8000000 0xd8000000 0x0 0x08000000 + 0x02000000 0x0 0xe0000000 0xe0000000 0x0 0x08000000 + 0x02000000 0x0 0xe8000000 0xe8000000 0x0 0x08000000>; + + reg = <0x10410000 0x19310>; + aspm-no-l0s; + device_type = "pci"; + msi-controller; + msi-parent = <&pcie_0>; + #address-cells = <0x3>; + #size-cells = <0x2>; + bus-range = <0x0 0xff>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + linux,pci-domain = <0x0>; + + interrupt-parent = <&periph_intc>; + interrupts = <39>, <39>; + interrupt-names = "pcie", "msi"; + #interrupt-cells = <0x1>; + interrupt-map = <0 0 0 1 &periph_intc 0x23 + 0 0 0 1 &periph_intc 0x24 + 0 0 0 1 &periph_intc 0x25 + 0 0 0 1 &periph_intc 0x26>; + }; }; diff --git a/arch/mips/boot/dts/brcm/bcm97358svmb.dts b/arch/mips/boot/dts/brcm/bcm97358svmb.dts index 522f2c40d6e6..c17fc14d4899 100644 --- a/arch/mips/boot/dts/brcm/bcm97358svmb.dts +++ b/arch/mips/boot/dts/brcm/bcm97358svmb.dts @@ -78,7 +78,7 @@ &qspi { status = "okay"; - m25p80@0 { + flash@0 { compatible = "m25p80"; reg = <0>; spi-max-frequency = <40000000>; diff --git a/arch/mips/boot/dts/brcm/bcm97360svmb.dts b/arch/mips/boot/dts/brcm/bcm97360svmb.dts index 01f215b08dba..c9b76f41e7a6 100644 --- a/arch/mips/boot/dts/brcm/bcm97360svmb.dts +++ b/arch/mips/boot/dts/brcm/bcm97360svmb.dts @@ -81,7 +81,7 @@ &qspi { status = "okay"; - m25p80@0 { + flash@0 { compatible = "m25p80"; reg = <0>; spi-max-frequency = <40000000>; diff --git a/arch/mips/boot/dts/brcm/bcm97425svmb.dts b/arch/mips/boot/dts/brcm/bcm97425svmb.dts index 9efecfe1e05c..289a57b912ef 100644 --- a/arch/mips/boot/dts/brcm/bcm97425svmb.dts +++ b/arch/mips/boot/dts/brcm/bcm97425svmb.dts @@ -116,7 +116,7 @@ &qspi { status = "okay"; - m25p80@0 { + flash@0 { compatible = "m25p80"; reg = <0>; spi-max-frequency = <40000000>; @@ -152,3 +152,12 @@ &waketimer { status = "okay"; }; + +&pcie_0 { + status = "okay"; + /* 1GB Memc0, 1GB Memc1 */ + brcm,scb-sizes = <0 0x40000000 0 0x40000000>; + dma-ranges = <0x43000000 0x00000000 0x00000000 0x00000000 0x0 0x10000000 + 0x43000000 0x00000000 0x10000000 0x20000000 0x0 0x30000000 + 0x43000000 0x00000000 0x40000000 0x90000000 0x0 0x40000000>; +}; diff --git a/arch/mips/boot/dts/brcm/bcm97435svmb.dts b/arch/mips/boot/dts/brcm/bcm97435svmb.dts index b653c6ff74b5..a0cf53e23c07 100644 --- a/arch/mips/boot/dts/brcm/bcm97435svmb.dts +++ b/arch/mips/boot/dts/brcm/bcm97435svmb.dts @@ -128,3 +128,12 @@ &waketimer { status = "okay"; }; + +&pcie_0 { + status = "okay"; + /* 1GB Memc0, 1GB Memc1 */ + brcm,scb-sizes = <0 0x40000000 0 0x40000000>; + dma-ranges = <0x43000000 0x00000000 0x00000000 0x00000000 0x0 0x10000000 + 0x43000000 0x00000000 0x10000000 0x20000000 0x0 0x30000000 + 0x43000000 0x00000000 0x40000000 0x90000000 0x0 0x40000000>; +}; diff --git a/arch/mips/boot/dts/img/pistachio_marduk.dts b/arch/mips/boot/dts/img/pistachio_marduk.dts index a8708783f04b..a8da2f992b1a 100644 --- a/arch/mips/boot/dts/img/pistachio_marduk.dts +++ b/arch/mips/boot/dts/img/pistachio_marduk.dts @@ -59,12 +59,12 @@ keys { compatible = "gpio-keys"; - button@1 { + button-1 { label = "Button 1"; linux,code = <0x101>; /* BTN_1 */ gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; }; - button@2 { + button-2 { label = "Button 2"; linux,code = <0x102>; /* BTN_2 */ gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index b249a4f0f6b6..37c46720c719 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -31,7 +31,7 @@ gpio-keys { compatible = "gpio-keys"; - sw1 { + switch { label = "ci20:sw1"; linux,code = <KEY_F13>; gpios = <&gpd 17 GPIO_ACTIVE_HIGH>; @@ -78,6 +78,20 @@ enable-active-high; }; + hdmi_out: connector { + compatible = "hdmi-connector"; + label = "HDMI OUT"; + type = "a"; + + ddc-en-gpios = <&gpa 25 GPIO_ACTIVE_HIGH>; + + port { + hdmi_con: endpoint { + remote-endpoint = <&dw_hdmi_out>; + }; + }; + }; + ir: ir { compatible = "gpio-ir-receiver"; gpios = <&gpe 3 GPIO_ACTIVE_LOW>; @@ -114,11 +128,12 @@ * precision. */ assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>, - <&cgu JZ4780_CLK_SSIPLL>, <&cgu JZ4780_CLK_SSI>; + <&cgu JZ4780_CLK_SSIPLL>, <&cgu JZ4780_CLK_SSI>, + <&cgu JZ4780_CLK_HDMI>; assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>, <&cgu JZ4780_CLK_MPLL>, <&cgu JZ4780_CLK_SSIPLL>; - assigned-clock-rates = <48000000>, <0>, <54000000>; + assigned-clock-rates = <48000000>, <0>, <54000000>, <0>, <27000000>; }; &tcu { @@ -509,6 +524,12 @@ bias-disable; }; + pins_hdmi_ddc: hdmi_ddc { + function = "hdmi-ddc"; + groups = "hdmi-ddc"; + bias-disable; + }; + pins_nemc: nemc { function = "nemc"; groups = "nemc-data", "nemc-cle-ale", "nemc-rd-we", "nemc-frd-fwe"; @@ -539,3 +560,39 @@ bias-disable; }; }; + +&hdmi { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_hdmi_ddc>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dw_hdmi_in: endpoint { + remote-endpoint = <&lcd_out>; + }; + }; + + port@1 { + reg = <1>; + dw_hdmi_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; +}; + +&lcdc0 { + status = "okay"; + + port { + lcd_out: endpoint { + remote-endpoint = <&dw_hdmi_in>; + }; + }; +}; diff --git a/arch/mips/boot/dts/ingenic/cu1000-neo.dts b/arch/mips/boot/dts/ingenic/cu1000-neo.dts index f98cf029efc3..c89abf94e74f 100644 --- a/arch/mips/boot/dts/ingenic/cu1000-neo.dts +++ b/arch/mips/boot/dts/ingenic/cu1000-neo.dts @@ -31,42 +31,6 @@ }; }; - ssi: spi-gpio { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - num-chipselects = <1>; - - mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>; - miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>; - sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>; - - status = "okay"; - - spi-max-frequency = <50000000>; - - sc16is752: expander@0 { - compatible = "nxp,sc16is752"; - reg = <0>; /* CE0 */ - spi-max-frequency = <4000000>; - - clocks = <&exclk_sc16is752>; - - interrupt-parent = <&gpc>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - - gpio-controller; - #gpio-cells = <2>; - - exclk_sc16is752: sc16is752 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - }; - }; - wlan_pwrseq: msc1-pwrseq { compatible = "mmc-pwrseq-simple"; @@ -90,7 +54,7 @@ &ost { /* 1500 kHz for the system timer and clocksource */ - assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>; + assigned-clocks = <&ost OST_CLK_EVENT_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>; assigned-clock-rates = <1500000>, <1500000>; }; @@ -101,6 +65,39 @@ pinctrl-0 = <&pins_uart2>; }; +&ssi { + status = "okay"; + + num-cs = <2>; + cs-gpios = <0>, <&gpc 20 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_ssi>; + + sc16is752: expander@0 { + compatible = "nxp,sc16is752"; + reg = <0>; /* CE0 */ + + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; + spi-max-frequency = <4000000>; + + clocks = <&exclk_sc16is752>; + + interrupt-parent = <&gpc>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + + exclk_sc16is752: sc16is752 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + }; +}; + &i2c0 { status = "okay"; @@ -192,6 +189,12 @@ bias-pull-up; }; + pins_ssi: ssi { + function = "ssi"; + groups = "ssi-dt-d", "ssi-dr-d", "ssi-clk-d", "ssi-ce0-d"; + bias-disable; + }; + pins_i2c0: i2c0 { function = "i2c0"; groups = "i2c0-data"; diff --git a/arch/mips/boot/dts/ingenic/cu1830-neo.dts b/arch/mips/boot/dts/ingenic/cu1830-neo.dts index cfcb40edb7d9..3c7784983332 100644 --- a/arch/mips/boot/dts/ingenic/cu1830-neo.dts +++ b/arch/mips/boot/dts/ingenic/cu1830-neo.dts @@ -31,42 +31,6 @@ }; }; - ssi0: spi-gpio { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - num-chipselects = <1>; - - mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>; - miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>; - sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>; - - status = "okay"; - - spi-max-frequency = <50000000>; - - sc16is752: expander@0 { - compatible = "nxp,sc16is752"; - reg = <0>; /* CE0 */ - spi-max-frequency = <4000000>; - - clocks = <&exclk_sc16is752>; - - interrupt-parent = <&gpb>; - interrupts = <18 IRQ_TYPE_EDGE_FALLING>; - - gpio-controller; - #gpio-cells = <2>; - - exclk_sc16is752: sc16is752 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - }; - }; - wlan_pwrseq: msc1-pwrseq { compatible = "mmc-pwrseq-simple"; @@ -90,7 +54,7 @@ &ost { /* 1500 kHz for the system timer and clocksource */ - assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>; + assigned-clocks = <&ost OST_CLK_EVENT_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>; assigned-clock-rates = <1500000>, <1500000>; }; @@ -101,6 +65,38 @@ pinctrl-0 = <&pins_uart1>; }; +&ssi0 { + status = "okay"; + + num-cs = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_ssi0>; + + sc16is752: expander@0 { + compatible = "nxp,sc16is752"; + reg = <0>; /* CE0 */ + + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; + spi-max-frequency = <4000000>; + + clocks = <&exclk_sc16is752>; + + interrupt-parent = <&gpb>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + + exclk_sc16is752: sc16is752 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + }; +}; + &i2c0 { status = "okay"; @@ -196,6 +192,12 @@ bias-pull-up; }; + pins_ssi0: ssi0 { + function = "ssi0"; + groups = "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-ce0", "ssi0-ce1"; + bias-disable; + }; + pins_i2c0: i2c0 { function = "i2c0"; groups = "i2c0-data"; diff --git a/arch/mips/boot/dts/ingenic/gcw0.dts b/arch/mips/boot/dts/ingenic/gcw0.dts index 4abb0318416c..5d33f26fd28c 100644 --- a/arch/mips/boot/dts/ingenic/gcw0.dts +++ b/arch/mips/boot/dts/ingenic/gcw0.dts @@ -130,89 +130,86 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - button@0 { + button-0 { label = "D-pad up"; linux,code = <KEY_UP>; linux,can-disable; gpios = <&gpe 21 GPIO_ACTIVE_LOW>; }; - button@1 { + button-1 { label = "D-pad down"; linux,code = <KEY_DOWN>; linux,can-disable; gpios = <&gpe 25 GPIO_ACTIVE_LOW>; }; - button@2 { + button-2 { label = "D-pad left"; linux,code = <KEY_LEFT>; linux,can-disable; gpios = <&gpe 23 GPIO_ACTIVE_LOW>; }; - button@3 { + button-3 { label = "D-pad right"; linux,code = <KEY_RIGHT>; linux,can-disable; gpios = <&gpe 24 GPIO_ACTIVE_LOW>; }; - button@4 { + button-4 { label = "Button A"; linux,code = <KEY_LEFTCTRL>; linux,can-disable; gpios = <&gpe 29 GPIO_ACTIVE_LOW>; }; - button@5 { + button-5 { label = "Button B"; linux,code = <KEY_LEFTALT>; linux,can-disable; gpios = <&gpe 20 GPIO_ACTIVE_LOW>; }; - button@6 { + button-6 { label = "Button Y"; linux,code = <KEY_SPACE>; linux,can-disable; gpios = <&gpe 27 GPIO_ACTIVE_LOW>; }; - button@7 { + button-7 { label = "Button X"; linux,code = <KEY_LEFTSHIFT>; linux,can-disable; gpios = <&gpe 28 GPIO_ACTIVE_LOW>; }; - button@8 { + button-8 { label = "Left shoulder button"; linux,code = <KEY_TAB>; linux,can-disable; gpios = <&gpb 20 GPIO_ACTIVE_LOW>; }; - button@9 { + button-9 { label = "Right shoulder button"; linux,code = <KEY_BACKSPACE>; linux,can-disable; gpios = <&gpe 26 GPIO_ACTIVE_LOW>; }; - button@10 { + button-10 { label = "Start button"; linux,code = <KEY_ENTER>; linux,can-disable; gpios = <&gpb 21 GPIO_ACTIVE_LOW>; }; - button@11 { + button-11 { label = "Select button"; linux,code = <KEY_ESC>; linux,can-disable; @@ -223,7 +220,7 @@ gpios = <&gpd 18 GPIO_ACTIVE_HIGH>; }; - button@12 { + button-12 { label = "Power slider"; linux,code = <KEY_POWER>; linux,can-disable; @@ -231,7 +228,7 @@ wakeup-source; }; - button@13 { + button-13 { label = "Power hold"; linux,code = <KEY_PAUSE>; linux,can-disable; diff --git a/arch/mips/boot/dts/ingenic/jz4725b.dtsi b/arch/mips/boot/dts/ingenic/jz4725b.dtsi index 0c6a5a4266f4..e9e48022f631 100644 --- a/arch/mips/boot/dts/ingenic/jz4725b.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4725b.dtsi @@ -321,7 +321,7 @@ lcd: lcd-controller@13050000 { compatible = "ingenic,jz4725b-lcd"; - reg = <0x13050000 0x1000>; + reg = <0x13050000 0x130>; /* tbc */ interrupt-parent = <&intc>; interrupts = <31>; diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi b/arch/mips/boot/dts/ingenic/jz4740.dtsi index 772542e1f266..7f76cba03a08 100644 --- a/arch/mips/boot/dts/ingenic/jz4740.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi @@ -323,7 +323,7 @@ lcd: lcd-controller@13050000 { compatible = "ingenic,jz4740-lcd"; - reg = <0x13050000 0x1000>; + reg = <0x13050000 0x60>; /* LCDCMD1+4 */ interrupt-parent = <&intc>; interrupts = <30>; diff --git a/arch/mips/boot/dts/ingenic/jz4770.dtsi b/arch/mips/boot/dts/ingenic/jz4770.dtsi index dfe74328ae5d..bda0a3a86ed5 100644 --- a/arch/mips/boot/dts/ingenic/jz4770.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4770.dtsi @@ -399,7 +399,7 @@ lcd: lcd-controller@13050000 { compatible = "ingenic,jz4770-lcd"; - reg = <0x13050000 0x300>; + reg = <0x13050000 0x130>; /* tbc */ interrupt-parent = <&intc>; interrupts = <31>; diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi index b0a4e2e019c3..c182a656d63b 100644 --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi @@ -444,6 +444,46 @@ status = "disabled"; }; + hdmi: hdmi@10180000 { + compatible = "ingenic,jz4780-dw-hdmi"; + reg = <0x10180000 0x8000>; + reg-io-width = <4>; + + clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>; + clock-names = "iahb", "isfr"; + + interrupt-parent = <&intc>; + interrupts = <3>; + + status = "disabled"; + }; + + lcdc0: lcdc0@13050000 { + compatible = "ingenic,jz4780-lcd"; + reg = <0x13050000 0x1800>; + + clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD0PIXCLK>; + clock-names = "lcd", "lcd_pclk"; + + interrupt-parent = <&intc>; + interrupts = <31>; + + status = "disabled"; + }; + + lcdc1: lcdc1@130a0000 { + compatible = "ingenic,jz4780-lcd"; + reg = <0x130a0000 0x1800>; + + clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD1PIXCLK>; + clock-names = "lcd", "lcd_pclk"; + + interrupt-parent = <&intc>; + interrupts = <23>; + + status = "disabled"; + }; + nemc: nemc@13410000 { compatible = "ingenic,jz4780-nemc", "simple-mfd"; reg = <0x13410000 0x10000>; @@ -470,7 +510,7 @@ #address-cells = <1>; #size-cells = <1>; - eth0_addr: eth-mac-addr@0x22 { + eth0_addr: eth-mac-addr@22 { reg = <0x22 0x6>; }; }; @@ -537,7 +577,7 @@ }; otg: usb@13500000 { - compatible = "ingenic,jz4780-otg", "snps,dwc2"; + compatible = "ingenic,jz4780-otg"; reg = <0x13500000 0x40000>; interrupt-parent = <&intc>; diff --git a/arch/mips/boot/dts/ingenic/rs90.dts b/arch/mips/boot/dts/ingenic/rs90.dts index 74fee7f01352..e8df70dd42bf 100644 --- a/arch/mips/boot/dts/ingenic/rs90.dts +++ b/arch/mips/boot/dts/ingenic/rs90.dts @@ -52,53 +52,51 @@ keys@0 { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - key@0 { + key-0 { label = "D-pad up"; linux,code = <KEY_UP>; gpios = <&gpc 10 GPIO_ACTIVE_LOW>; }; - key@1 { + key-1 { label = "D-pad down"; linux,code = <KEY_DOWN>; gpios = <&gpc 11 GPIO_ACTIVE_LOW>; }; - key@2 { + key-2 { label = "D-pad left"; linux,code = <KEY_LEFT>; gpios = <&gpb 31 GPIO_ACTIVE_LOW>; }; - key@3 { + key-3 { label = "D-pad right"; linux,code = <KEY_RIGHT>; gpios = <&gpd 21 GPIO_ACTIVE_LOW>; }; - key@4 { + key-4 { label = "Button A"; linux,code = <KEY_LEFTCTRL>; gpios = <&gpc 31 GPIO_ACTIVE_LOW>; }; - key@5 { + key-5 { label = "Button B"; linux,code = <KEY_LEFTALT>; gpios = <&gpc 30 GPIO_ACTIVE_LOW>; }; - key@6 { + key-6 { label = "Right shoulder button"; linux,code = <KEY_BACKSPACE>; gpios = <&gpc 12 GPIO_ACTIVE_LOW>; debounce-interval = <10>; }; - key@7 { + key-7 { label = "Start button"; linux,code = <KEY_ENTER>; gpios = <&gpd 17 GPIO_ACTIVE_LOW>; diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi index 8bd27edef216..42e69664efd9 100644 --- a/arch/mips/boot/dts/ingenic/x1000.dtsi +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi @@ -111,8 +111,9 @@ clocks = <&cgu X1000_CLK_RTCLK>, <&cgu X1000_CLK_EXCLK>, - <&cgu X1000_CLK_PCLK>; - clock-names = "rtc", "ext", "pclk"; + <&cgu X1000_CLK_PCLK>, + <&cgu X1000_CLK_TCU>; + clock-names = "rtc", "ext", "pclk", "tcu"; interrupt-controller; #interrupt-cells = <1>; @@ -127,6 +128,18 @@ clocks = <&tcu TCU_CLK_WDT>; clock-names = "wdt"; }; + + pwm: pwm@40 { + compatible = "ingenic,x1000-pwm"; + reg = <0x40 0x50>; + + #pwm-cells = <3>; + + clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, + <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>, + <&tcu TCU_CLK_TIMER4>; + clock-names = "timer0", "timer1", "timer2", "timer3", "timer4"; + }; }; rtc: rtc@10003000 { @@ -246,6 +259,25 @@ status = "disabled"; }; + ssi: spi@10043000 { + compatible = "ingenic,x1000-spi"; + reg = <0x10043000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&intc>; + interrupts = <8>; + + clocks = <&cgu X1000_CLK_SSI>; + clock-names = "spi"; + + dmas = <&pdma X1000_DMA_SSI0_RX 0xffffffff>, + <&pdma X1000_DMA_SSI0_TX 0xffffffff>; + dma-names = "rx", "tx"; + + status = "disabled"; + }; + i2c0: i2c-controller@10050000 { compatible = "ingenic,x1000-i2c"; reg = <0x10050000 0x1000>; @@ -291,6 +323,7 @@ pdma: dma-controller@13420000 { compatible = "ingenic,x1000-dma"; reg = <0x13420000 0x400>, <0x13421000 0x40>; + #dma-cells = <2>; interrupt-parent = <&intc>; @@ -366,7 +399,7 @@ }; otg: usb@13500000 { - compatible = "ingenic,x1000-otg", "snps,dwc2"; + compatible = "ingenic,x1000-otg"; reg = <0x13500000 0x40000>; interrupt-parent = <&intc>; diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi index 2595df8671c7..65a5da71c199 100644 --- a/arch/mips/boot/dts/ingenic/x1830.dtsi +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi @@ -104,8 +104,9 @@ clocks = <&cgu X1830_CLK_RTCLK>, <&cgu X1830_CLK_EXCLK>, - <&cgu X1830_CLK_PCLK>; - clock-names = "rtc", "ext", "pclk"; + <&cgu X1830_CLK_PCLK>, + <&cgu X1830_CLK_TCU>; + clock-names = "rtc", "ext", "pclk", "tcu"; interrupt-controller; #interrupt-cells = <1>; @@ -120,6 +121,20 @@ clocks = <&tcu TCU_CLK_WDT>; clock-names = "wdt"; }; + + pwm: pwm@40 { + compatible = "ingenic,x1830-pwm", "ingenic,jz4740-pwm"; + reg = <0x40 0x80>; + + #pwm-cells = <3>; + + clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, + <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>, + <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>, + <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>; + clock-names = "timer0", "timer1", "timer2", "timer3", + "timer4", "timer5", "timer6", "timer7"; + }; }; rtc: rtc@10003000 { @@ -226,6 +241,44 @@ status = "disabled"; }; + ssi0: spi@10043000 { + compatible = "ingenic,x1830-spi", "ingenic,x1000-spi"; + reg = <0x10043000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&intc>; + interrupts = <9>; + + clocks = <&cgu X1830_CLK_SSI0>; + clock-names = "spi"; + + dmas = <&pdma X1830_DMA_SSI0_RX 0xffffffff>, + <&pdma X1830_DMA_SSI0_TX 0xffffffff>; + dma-names = "rx", "tx"; + + status = "disabled"; + }; + + ssi1: spi@10044000 { + compatible = "ingenic,x1830-spi", "ingenic,x1000-spi"; + reg = <0x10044000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&intc>; + interrupts = <8>; + + clocks = <&cgu X1830_CLK_SSI1>; + clock-names = "spi"; + + dmas = <&pdma X1830_DMA_SSI1_RX 0xffffffff>, + <&pdma X1830_DMA_SSI1_TX 0xffffffff>; + dma-names = "rx", "tx"; + + status = "disabled"; + }; + i2c0: i2c-controller@10050000 { compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c"; reg = <0x10050000 0x1000>; @@ -280,6 +333,7 @@ pdma: dma-controller@13420000 { compatible = "ingenic,x1830-dma"; reg = <0x13420000 0x400>, <0x13421000 0x40>; + #dma-cells = <2>; interrupt-parent = <&intc>; @@ -355,7 +409,7 @@ }; otg: usb@13500000 { - compatible = "ingenic,x1830-otg", "snps,dwc2"; + compatible = "ingenic,x1830-otg"; reg = <0x13500000 0x40000>; interrupt-parent = <&intc>; diff --git a/arch/mips/boot/dts/lantiq/Makefile b/arch/mips/boot/dts/lantiq/Makefile index f5dfc06242b9..ae6e3e21ebeb 100644 --- a/arch/mips/boot/dts/lantiq/Makefile +++ b/arch/mips/boot/dts/lantiq/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_DT_EASY50712) += easy50712.dtb +dtb-$(CONFIG_DT_EASY50712) += danube_easy50712.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/mips/boot/dts/lantiq/easy50712.dts b/arch/mips/boot/dts/lantiq/danube_easy50712.dts index 1ce20b7d05cb..1ce20b7d05cb 100644 --- a/arch/mips/boot/dts/lantiq/easy50712.dts +++ b/arch/mips/boot/dts/lantiq/danube_easy50712.dts diff --git a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi index bfc3d3243ee7..8143a61111e3 100644 --- a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi +++ b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi @@ -52,6 +52,11 @@ 0 0x40000000 0 0x40000000 0 0x40000000 0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>; + pm: reset-controller@1fe07000 { + compatible = "loongson,ls2k-pm"; + reg = <0 0x1fe07000 0 0x422>; + }; + liointc0: interrupt-controller@1fe11400 { compatible = "loongson,liointc-2.0"; reg = <0 0x1fe11400 0 0x40>, diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts index d80cd6842b2a..0ea7bc5b5746 100644 --- a/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts +++ b/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts @@ -180,27 +180,27 @@ pins = "GPIO_49"; function = "si"; }; - i2cmux_pins_i: i2cmux-pins-i { + i2cmux_pins_i: i2cmux-pins { pins = "GPIO_17", "GPIO_18", "GPIO_20", "GPIO_21"; function = "twi_scl_m"; output-low; }; - i2cmux_0: i2cmux-0 { + i2cmux_0: i2cmux-0-pins { pins = "GPIO_17"; function = "twi_scl_m"; output-high; }; - i2cmux_1: i2cmux-1 { + i2cmux_1: i2cmux-1-pins { pins = "GPIO_18"; function = "twi_scl_m"; output-high; }; - i2cmux_2: i2cmux-2 { + i2cmux_2: i2cmux-2-pins { pins = "GPIO_20"; function = "twi_scl_m"; output-high; }; - i2cmux_3: i2cmux-3 { + i2cmux_3: i2cmux-3-pins { pins = "GPIO_21"; function = "twi_scl_m"; output-high; diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts index 813c5e16013c..05d8c6a96dc4 100644 --- a/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts +++ b/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts @@ -79,27 +79,27 @@ }; &gpio { - i2cmux_pins_i: i2cmux-pins-i { + i2cmux_pins_i: i2cmux-pins { pins = "GPIO_17", "GPIO_18"; function = "twi_scl_m"; output-low; }; - i2cmux_0: i2cmux-0 { + i2cmux_0: i2cmux-0-pins { pins = "GPIO_17"; function = "twi_scl_m"; output-high; }; - i2cmux_1: i2cmux-1 { + i2cmux_1: i2cmux-1-pins { pins = "GPIO_18"; function = "twi_scl_m"; output-high; }; - i2cmux_2: i2cmux-2 { + i2cmux_2: i2cmux-2-pins { pins = "GPIO_20"; function = "twi_scl_m"; output-high; }; - i2cmux_3: i2cmux-3 { + i2cmux_3: i2cmux-3-pins { pins = "GPIO_21"; function = "twi_scl_m"; output-high; diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts index 27c644f2d17f..cf2cf591a211 100644 --- a/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts +++ b/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts @@ -39,17 +39,17 @@ }; &gpio { - i2cmux_pins_i: i2cmux-pins-i { + i2cmux_pins_i: i2cmux-pins { pins = "GPIO_17", "GPIO_16"; function = "twi_scl_m"; output-low; }; - i2cmux_0: i2cmux-0 { + i2cmux_0: i2cmux-0-pins { pins = "GPIO_17"; function = "twi_scl_m"; output-high; }; - i2cmux_1: i2cmux-1 { + i2cmux_1: i2cmux-1-pins { pins = "GPIO_16"; function = "twi_scl_m"; output-high; diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi index e51db651af13..6bd8a1ad94da 100644 --- a/arch/mips/boot/dts/mscc/ocelot.dtsi +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi @@ -136,13 +136,14 @@ <0x1880000 0x10000>, <0x1040000 0x10000>, <0x1050000 0x10000>, - <0x1060000 0x10000>; + <0x1060000 0x10000>, + <0x1a0 0x1c4>; reg-names = "sys", "rew", "qs", "ptp", "port0", "port1", "port2", "port3", "port4", "port5", "port6", "port7", "port8", "port9", "port10", "qsys", - "ana", "s0", "s1", "s2"; - interrupts = <18 21 22>; - interrupt-names = "ptp_rdy", "xtr", "inj"; + "ana", "s0", "s1", "s2", "fdma"; + interrupts = <18 21 22 16>; + interrupt-names = "ptp_rdy", "xtr", "inj", "fdma"; ethernet-ports { #address-cells = <1>; @@ -225,7 +226,7 @@ function = "uart2"; }; - miim1: miim1 { + miim1_pins: miim1-pins { pins = "GPIO_14", "GPIO_15"; function = "miim"; }; @@ -261,7 +262,7 @@ reg = <0x10700c0 0x24>; interrupts = <15>; pinctrl-names = "default"; - pinctrl-0 = <&miim1>; + pinctrl-0 = <&miim1_pins>; status = "disabled"; }; diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts index bd240690cb37..d348742c233d 100644 --- a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts +++ b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts @@ -22,12 +22,12 @@ }; &gpio { - phy_int_pins: phy_int_pins { + phy_int_pins: phy-int-pins { pins = "GPIO_4"; function = "gpio"; }; - phy_load_save_pins: phy_load_save_pins { + phy_load_save_pins: phy-load-save-pins { pins = "GPIO_10"; function = "ptp2"; }; @@ -40,7 +40,7 @@ &mdio1 { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&miim1>, <&phy_int_pins>, <&phy_load_save_pins>; + pinctrl-0 = <&miim1_pins>, <&phy_int_pins>, <&phy_load_save_pins>; phy7: ethernet-phy@0 { reg = <0>; diff --git a/arch/mips/boot/dts/mscc/serval_common.dtsi b/arch/mips/boot/dts/mscc/serval_common.dtsi index 5b404836db5e..0893de420e27 100644 --- a/arch/mips/boot/dts/mscc/serval_common.dtsi +++ b/arch/mips/boot/dts/mscc/serval_common.dtsi @@ -82,38 +82,38 @@ pins = "GPIO_7"; /* No "default" scl for i2c0 */ function = "twi"; }; - i2cmux_pins_i: i2cmux-pins-i { + i2cmux_pins_i: i2cmux-pins { pins = "GPIO_11", "GPIO_12", "GPIO_18", "GPIO_19", "GPIO_20", "GPIO_21"; function = "twi_scl_m"; output-low; }; - i2cmux_0: i2cmux-0 { + i2cmux_0: i2cmux-0-pins { pins = "GPIO_11"; function = "twi_scl_m"; output-high; }; - i2cmux_1: i2cmux-1 { + i2cmux_1: i2cmux-1-pins { pins = "GPIO_12"; function = "twi_scl_m"; output-high; }; - i2cmux_2: i2cmux-2 { + i2cmux_2: i2cmux-2-pins { pins = "GPIO_18"; function = "twi_scl_m"; output-high; }; - i2cmux_3: i2cmux-3 { + i2cmux_3: i2cmux-3-pins { pins = "GPIO_19"; function = "twi_scl_m"; output-high; }; - i2cmux_4: i2cmux-4 { + i2cmux_4: i2cmux-4-pins { pins = "GPIO_20"; function = "twi_scl_m"; output-high; }; - i2cmux_5: i2cmux-5 { + i2cmux_5: i2cmux-5-pins { pins = "GPIO_21"; function = "twi_scl_m"; output-high; diff --git a/arch/mips/boot/dts/pic32/pic32mzda_sk.dts b/arch/mips/boot/dts/pic32/pic32mzda_sk.dts index d7fa5d55dbf3..ab70637bbec5 100644 --- a/arch/mips/boot/dts/pic32/pic32mzda_sk.dts +++ b/arch/mips/boot/dts/pic32/pic32mzda_sk.dts @@ -52,22 +52,19 @@ pinctrl-0 = <&user_buttons_s0>; pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - button@sw1 { + button-1 { label = "ESC"; linux,code = <1>; gpios = <&gpio1 12 0>; }; - button@sw2 { + button-2 { label = "Home"; linux,code = <102>; gpios = <&gpio1 13 0>; }; - button@sw3 { + button-3 { label = "Menu"; linux,code = <139>; gpios = <&gpio1 14 0>; diff --git a/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts b/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts index 7fccf6357225..f3dff4009ab5 100644 --- a/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts +++ b/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts @@ -23,17 +23,15 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - button@0 { + button-0 { label = "reset"; linux,code = <KEY_RESTART>; gpios = <&gpio 3 GPIO_ACTIVE_LOW>; debounce-interval = <60>; }; - button@1 { + button-1 { label = "qss"; linux,code = <KEY_WPS_BUTTON>; gpios = <&gpio 7 GPIO_ACTIVE_LOW>; diff --git a/arch/mips/boot/dts/qca/ar9331_dpt_module.dts b/arch/mips/boot/dts/qca/ar9331_dpt_module.dts index 7695d326df11..c857cd22f7db 100644 --- a/arch/mips/boot/dts/qca/ar9331_dpt_module.dts +++ b/arch/mips/boot/dts/qca/ar9331_dpt_module.dts @@ -33,10 +33,8 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - button@0 { + button-0 { label = "reset"; linux,code = <KEY_RESTART>; gpios = <&gpio 11 GPIO_ACTIVE_LOW>; diff --git a/arch/mips/boot/dts/qca/ar9331_dragino_ms14.dts b/arch/mips/boot/dts/qca/ar9331_dragino_ms14.dts index d38aa73f1a2e..40e4c5da0e65 100644 --- a/arch/mips/boot/dts/qca/ar9331_dragino_ms14.dts +++ b/arch/mips/boot/dts/qca/ar9331_dragino_ms14.dts @@ -49,16 +49,14 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - button@0 { + button-0 { label = "jumpstart"; linux,code = <KEY_WPS_BUTTON>; gpios = <&gpio 11 GPIO_ACTIVE_LOW>; }; - button@1 { + button-1 { label = "reset"; linux,code = <KEY_RESTART>; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; diff --git a/arch/mips/boot/dts/qca/ar9331_omega.dts b/arch/mips/boot/dts/qca/ar9331_omega.dts index 11778abacf66..ed184d861d5f 100644 --- a/arch/mips/boot/dts/qca/ar9331_omega.dts +++ b/arch/mips/boot/dts/qca/ar9331_omega.dts @@ -31,10 +31,8 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - button@0 { + button-0 { label = "reset"; linux,code = <KEY_RESTART>; gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; diff --git a/arch/mips/boot/dts/qca/ar9331_openembed_som9331_board.dts b/arch/mips/boot/dts/qca/ar9331_openembed_som9331_board.dts index e6622f8e8c2b..dc65ebd60bbc 100644 --- a/arch/mips/boot/dts/qca/ar9331_openembed_som9331_board.dts +++ b/arch/mips/boot/dts/qca/ar9331_openembed_som9331_board.dts @@ -33,10 +33,8 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - button@0 { + button-0 { label = "reset"; linux,code = <KEY_RESTART>; gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; diff --git a/arch/mips/boot/dts/qca/ar9331_tl_mr3020.dts b/arch/mips/boot/dts/qca/ar9331_tl_mr3020.dts index c8290d36cfbe..5f424c2cd781 100644 --- a/arch/mips/boot/dts/qca/ar9331_tl_mr3020.dts +++ b/arch/mips/boot/dts/qca/ar9331_tl_mr3020.dts @@ -49,22 +49,20 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - button@0 { + button-0 { label = "wps"; linux,code = <KEY_WPS_BUTTON>; gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; }; - button@1 { + button-1 { label = "sw1"; linux,code = <BTN_0>; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; }; - button@2 { + button-2 { label = "sw2"; linux,code = <BTN_1>; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; diff --git a/arch/mips/boot/dts/ralink/Makefile b/arch/mips/boot/dts/ralink/Makefile index 6c26dfa0a903..11732b8c8163 100644 --- a/arch/mips/boot/dts/ralink/Makefile +++ b/arch/mips/boot/dts/ralink/Makefile @@ -6,4 +6,8 @@ dtb-$(CONFIG_DTB_MT7620A_EVAL) += mt7620a_eval.dtb dtb-$(CONFIG_DTB_OMEGA2P) += omega2p.dtb dtb-$(CONFIG_DTB_VOCORE2) += vocore2.dtb +dtb-$(CONFIG_SOC_MT7621) += \ + mt7621-gnubee-gb-pc1.dtb \ + mt7621-gnubee-gb-pc2.dtb + obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts b/arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts index 6069b33cf09f..179558161f85 100644 --- a/arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts +++ b/arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts @@ -26,7 +26,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinmux_gpio_gpio>; /* GPIO11 */ - user_btn1 { + button { label = "USER_BTN1"; gpios = <&gpio 11 GPIO_ACTIVE_LOW>; linux,code =<KEY_PROG1> ; @@ -129,7 +129,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinmux_spi_spi>, <&pinmux_spi_cs1_cs>; - m25p80@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <40000000>; diff --git a/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts b/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts new file mode 100644 index 000000000000..0128bd8fa7ed --- /dev/null +++ b/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/dts-v1/; + +#include "mt7621.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + compatible = "gnubee,gb-pc1", "mediatek,mt7621-soc"; + model = "GB-PC1"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x1c000000>, + <0x20000000 0x04000000>; + }; + + chosen { + bootargs = "console=ttyS0,57600"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-reset { + label = "reset"; + gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_RESTART>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power { + label = "green:power"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + system { + label = "green:system"; + gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + linux,default-trigger = "disk-activity"; + }; + }; +}; + +&mmc { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + broken-flash-reset; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x1fb0000>; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&gmac1 { + status = "okay"; + phy-handle = <ðphy4>; +}; + +&mdio { + ethphy4: ethernet-phy@4 { + reg = <4>; + }; +}; + +&switch0 { + ports { + port@0 { + status = "okay"; + label = "ethblack"; + }; + }; +}; diff --git a/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts b/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts new file mode 100644 index 000000000000..7515555388ae --- /dev/null +++ b/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/dts-v1/; + +#include "mt7621.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + compatible = "gnubee,gb-pc2", "mediatek,mt7621-soc"; + model = "GB-PC2"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x1c000000>, + <0x20000000 0x04000000>; + }; + + chosen { + bootargs = "console=ttyS0,57600"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-reset { + label = "reset"; + gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_RESTART>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + ethblack-green { + label = "green:ethblack"; + gpios = <&gpio 3 GPIO_ACTIVE_LOW>; + }; + + ethblue-green { + label = "green:ethblue"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + + ethyellow-green { + label = "green:ethyellow"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + }; + + ethyellow-orange { + label = "orange:ethyellow"; + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + }; + + power { + label = "green:power"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + system { + label = "green:system"; + gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + linux,default-trigger = "disk-activity"; + }; + }; +}; + +&mmc { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + broken-flash-reset; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x1fb0000>; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&gmac1 { + status = "okay"; + phy-handle = <ðphy5>; +}; + +&mdio { + ethphy5: ethernet-phy@5 { + reg = <5>; + phy-mode = "rgmii-rxid"; + }; +}; + +&switch0 { + ports { + port@0 { + status = "okay"; + label = "ethblack"; + }; + + port@4 { + status = "okay"; + label = "ethblue"; + }; + }; +}; diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi new file mode 100644 index 000000000000..f3f4c1f26e01 --- /dev/null +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +#include <dt-bindings/interrupt-controller/mips-gic.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/mt7621-clk.h> +#include <dt-bindings/reset/mt7621-reset.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt7621-soc"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "mips,mips1004Kc"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "mips,mips1004Kc"; + reg = <1>; + }; + }; + + cpuintc: cpuintc { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + mmc_fixed_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "mmc_power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + }; + + mmc_fixed_1v8_io: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "mmc_io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-always-on; + }; + + palmbus: palmbus@1e000000 { + compatible = "palmbus"; + reg = <0x1e000000 0x100000>; + ranges = <0x0 0x1e000000 0x0fffff>; + + #address-cells = <1>; + #size-cells = <1>; + + sysc: syscon@0 { + compatible = "mediatek,mt7621-sysc", "syscon"; + reg = <0x0 0x100>; + #clock-cells = <1>; + #reset-cells = <1>; + ralink,memctl = <&memc>; + clock-output-names = "xtal", "cpu", "bus", + "50m", "125m", "150m", + "250m", "270m"; + }; + + wdt: wdt@100 { + compatible = "mediatek,mt7621-wdt"; + reg = <0x100 0x100>; + }; + + gpio: gpio@600 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "mediatek,mt7621-gpio"; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 95>; + interrupt-controller; + reg = <0x600 0x100>; + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>; + }; + + i2c: i2c@900 { + compatible = "mediatek,mt7621-i2c"; + reg = <0x900 0x100>; + + clocks = <&sysc MT7621_CLK_I2C>; + clock-names = "i2c"; + resets = <&sysc MT7621_RST_I2C>; + reset-names = "i2c"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins>; + }; + + memc: memory-controller@5000 { + compatible = "mediatek,mt7621-memc", "syscon"; + reg = <0x5000 0x1000>; + }; + + serial0: serial@c00 { + compatible = "ns16550a"; + reg = <0xc00 0x100>; + + clocks = <&sysc MT7621_CLK_UART1>; + + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>; + + reg-shift = <2>; + reg-io-width = <4>; + no-loopback-test; + }; + + spi0: spi@b00 { + status = "disabled"; + + compatible = "ralink,mt7621-spi"; + reg = <0xb00 0x100>; + + clocks = <&sysc MT7621_CLK_SPI>; + clock-names = "spi"; + + resets = <&sysc MT7621_RST_SPI>; + reset-names = "spi"; + + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins>; + }; + }; + + pinctrl: pinctrl { + compatible = "ralink,mt7621-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + + spi_pins: spi0-pins { + pinmux { + groups = "spi"; + function = "spi"; + }; + }; + + uart1_pins: uart1-pins { + pinmux { + groups = "uart1"; + function = "uart1"; + }; + }; + + uart2_pins: uart2-pins { + pinmux { + groups = "uart2"; + function = "uart2"; + }; + }; + + uart3_pins: uart3-pins { + pinmux { + groups = "uart3"; + function = "uart3"; + }; + }; + + rgmii1_pins: rgmii1-pins { + pinmux { + groups = "rgmii1"; + function = "rgmii1"; + }; + }; + + rgmii2_pins: rgmii2-pins { + pinmux { + groups = "rgmii2"; + function = "rgmii2"; + }; + }; + + mdio_pins: mdio0-pins { + pinmux { + groups = "mdio"; + function = "mdio"; + }; + }; + + pcie_pins: pcie0-pins { + pinmux { + groups = "pcie"; + function = "gpio"; + }; + }; + + nand_pins: nand0-pins { + spi-pinmux { + groups = "spi"; + function = "nand1"; + }; + + sdhci-pinmux { + groups = "sdhci"; + function = "nand2"; + }; + }; + + sdhci_pins: sdhci0-pins { + pinmux { + groups = "sdhci"; + function = "sdhci"; + }; + }; + }; + + mmc: mmc@1e130000 { + status = "disabled"; + + compatible = "mediatek,mt7620-mmc"; + reg = <0x1e130000 0x4000>; + + bus-width = <4>; + max-frequency = <48000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + vmmc-supply = <&mmc_fixed_3v3>; + vqmmc-supply = <&mmc_fixed_1v8_io>; + disable-wp; + + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&sdhci_pins>; + pinctrl-1 = <&sdhci_pins>; + + clocks = <&sysc MT7621_CLK_SHXC>, + <&sysc MT7621_CLK_50M>; + clock-names = "source", "hclk"; + + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>; + }; + + usb: usb@1e1c0000 { + compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci"; + reg = <0x1e1c0000 0x1000 + 0x1e1d0700 0x0100>; + reg-names = "mac", "ippc"; + + clocks = <&sysc MT7621_CLK_XTAL>; + clock-names = "sys_ck"; + + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>; + }; + + gic: interrupt-controller@1fbc0000 { + compatible = "mti,gic"; + reg = <0x1fbc0000 0x2000>; + + interrupt-controller; + #interrupt-cells = <3>; + + mti,reserved-cpu-vectors = <7>; + + timer { + compatible = "mti,gic-timer"; + interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; + clocks = <&sysc MT7621_CLK_CPU>; + }; + }; + + cpc: cpc@1fbf0000 { + compatible = "mti,mips-cpc"; + reg = <0x1fbf0000 0x8000>; + }; + + cdmm: cdmm@1fbf8000 { + compatible = "mti,mips-cdmm"; + reg = <0x1fbf8000 0x8000>; + }; + + ethernet: ethernet@1e100000 { + compatible = "mediatek,mt7621-eth"; + reg = <0x1e100000 0x10000>; + + clocks = <&sysc MT7621_CLK_FE>, + <&sysc MT7621_CLK_ETH>; + clock-names = "fe", "ethif"; + + #address-cells = <1>; + #size-cells = <0>; + + resets = <&sysc MT7621_RST_FE &sysc MT7621_RST_ETH>; + reset-names = "fe", "eth"; + + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; + + mediatek,ethsys = <&sysc>; + + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + status = "disabled"; + phy-mode = "rgmii"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + switch0: switch@1f { + compatible = "mediatek,mt7621"; + reg = <0x1f>; + mediatek,mcm; + resets = <&sysc MT7621_RST_MCM>; + reset-names = "mcm"; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + status = "disabled"; + reg = <0>; + label = "lan0"; + }; + + port@1 { + status = "disabled"; + reg = <1>; + label = "lan1"; + }; + + port@2 { + status = "disabled"; + reg = <2>; + label = "lan2"; + }; + + port@3 { + status = "disabled"; + reg = <3>; + label = "lan3"; + }; + + port@4 { + status = "disabled"; + reg = <4>; + label = "lan4"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; + }; + + pcie: pcie@1e140000 { + compatible = "mediatek,mt7621-pci"; + reg = <0x1e140000 0x100>, /* host-pci bridge registers */ + <0x1e142000 0x100>, /* pcie port 0 RC control registers */ + <0x1e143000 0x100>, /* pcie port 1 RC control registers */ + <0x1e144000 0x100>; /* pcie port 2 RC control registers */ + #address-cells = <3>; + #size-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + + device_type = "pci"; + + ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */ + <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ + + #interrupt-cells = <1>; + interrupt-map-mask = <0xF800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + + reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; + resets = <&sysc MT7621_RST_PCIE0>; + clocks = <&sysc MT7621_CLK_PCIE0>; + phys = <&pcie0_phy 1>; + phy-names = "pcie-phy0"; + ranges; + }; + + pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; + resets = <&sysc MT7621_RST_PCIE1>; + clocks = <&sysc MT7621_CLK_PCIE1>; + phys = <&pcie0_phy 1>; + phy-names = "pcie-phy1"; + ranges; + }; + + pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; + resets = <&sysc MT7621_RST_PCIE2>; + clocks = <&sysc MT7621_CLK_PCIE2>; + phys = <&pcie2_phy 0>; + phy-names = "pcie-phy2"; + ranges; + }; + }; + + pcie0_phy: pcie-phy@1e149000 { + compatible = "mediatek,mt7621-pci-phy"; + reg = <0x1e149000 0x0700>; + clocks = <&sysc MT7621_CLK_XTAL>; + #phy-cells = <1>; + }; + + pcie2_phy: pcie-phy@1e14a000 { + compatible = "mediatek,mt7621-pci-phy"; + reg = <0x1e14a000 0x0700>; + clocks = <&sysc MT7621_CLK_XTAL>; + #phy-cells = <1>; + }; +}; diff --git a/arch/mips/boot/tools/relocs.c b/arch/mips/boot/tools/relocs.c index 1bf53f3524b3..02fc85f3e8ff 100644 --- a/arch/mips/boot/tools/relocs.c +++ b/arch/mips/boot/tools/relocs.c @@ -351,7 +351,7 @@ static void read_symtabs(FILE *fp) static void read_relocs(FILE *fp) { - static unsigned long base = 0; + static unsigned long base; int i, j; if (!base) { |