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-rw-r--r--arch/mips/cavium-octeon/Makefile3
-rw-r--r--arch/mips/cavium-octeon/Platform11
-rw-r--r--arch/mips/cavium-octeon/cpu.c6
-rw-r--r--arch/mips/cavium-octeon/csrc-octeon.c63
-rw-r--r--arch/mips/cavium-octeon/dma-octeon.c17
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c553
-rw-r--r--arch/mips/cavium-octeon/octeon_boot.h16
-rw-r--r--arch/mips/cavium-octeon/serial.c4
-rw-r--r--arch/mips/cavium-octeon/setup.c48
-rw-r--r--arch/mips/cavium-octeon/smp.c170
10 files changed, 535 insertions, 356 deletions
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 3e9876317e61..19eb0434269f 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -12,7 +12,6 @@
obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
obj-y += dma-octeon.o flash_setup.o
obj-y += octeon-memcpy.o
+obj-y += executive/
obj-$(CONFIG_SMP) += smp.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/cavium-octeon/Platform b/arch/mips/cavium-octeon/Platform
new file mode 100644
index 000000000000..1e43ccf1a792
--- /dev/null
+++ b/arch/mips/cavium-octeon/Platform
@@ -0,0 +1,11 @@
+#
+# Cavium Octeon
+#
+platform-$(CONFIG_CPU_CAVIUM_OCTEON) += cavium-octeon/
+cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += \
+ -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon
+ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
+load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff84100000
+else
+load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff81100000
+endif
diff --git a/arch/mips/cavium-octeon/cpu.c b/arch/mips/cavium-octeon/cpu.c
index b6df5387e855..c664c8cc2b42 100644
--- a/arch/mips/cavium-octeon/cpu.c
+++ b/arch/mips/cavium-octeon/cpu.c
@@ -41,12 +41,8 @@ static int cnmips_cu2_call(struct notifier_block *nfb, unsigned long action,
return NOTIFY_OK; /* Let default notifier send signals */
}
-static struct notifier_block cnmips_cu2_notifier = {
- .notifier_call = cnmips_cu2_call,
-};
-
static int cnmips_cu2_setup(void)
{
- return register_cu2_notifier(&cnmips_cu2_notifier);
+ return cu2_notifier(cnmips_cu2_call, 0);
}
early_initcall(cnmips_cu2_setup);
diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c
index 0bf4bbe04ae2..b6847c8e0ddd 100644
--- a/arch/mips/cavium-octeon/csrc-octeon.c
+++ b/arch/mips/cavium-octeon/csrc-octeon.c
@@ -53,7 +53,6 @@ static struct clocksource clocksource_mips = {
unsigned long long notrace sched_clock(void)
{
/* 64-bit arithmatic can overflow, so use 128-bit. */
-#if (__GNUC__ < 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ <= 3))
u64 t1, t2, t3;
unsigned long long rv;
u64 mult = clocksource_mips.mult;
@@ -73,13 +72,6 @@ unsigned long long notrace sched_clock(void)
: [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift)
: "hi", "lo");
return rv;
-#else
- /* GCC > 4.3 do it the easy way. */
- unsigned int __attribute__((mode(TI))) t;
- t = read_c0_cvmcount();
- t = t * clocksource_mips.mult;
- return (unsigned long long)(t >> clocksource_mips.shift);
-#endif
}
void __init plat_time_init(void)
@@ -88,3 +80,58 @@ void __init plat_time_init(void)
clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
clocksource_register(&clocksource_mips);
}
+
+static u64 octeon_udelay_factor;
+static u64 octeon_ndelay_factor;
+
+void __init octeon_setup_delays(void)
+{
+ octeon_udelay_factor = octeon_get_clock_rate() / 1000000;
+ /*
+ * For __ndelay we divide by 2^16, so the factor is multiplied
+ * by the same amount.
+ */
+ octeon_ndelay_factor = (octeon_udelay_factor * 0x10000ull) / 1000ull;
+
+ preset_lpj = octeon_get_clock_rate() / HZ;
+}
+
+void __udelay(unsigned long us)
+{
+ u64 cur, end, inc;
+
+ cur = read_c0_cvmcount();
+
+ inc = us * octeon_udelay_factor;
+ end = cur + inc;
+
+ while (end > cur)
+ cur = read_c0_cvmcount();
+}
+EXPORT_SYMBOL(__udelay);
+
+void __ndelay(unsigned long ns)
+{
+ u64 cur, end, inc;
+
+ cur = read_c0_cvmcount();
+
+ inc = ((ns * octeon_ndelay_factor) >> 16);
+ end = cur + inc;
+
+ while (end > cur)
+ cur = read_c0_cvmcount();
+}
+EXPORT_SYMBOL(__ndelay);
+
+void __delay(unsigned long loops)
+{
+ u64 cur, end;
+
+ cur = read_c0_cvmcount();
+ end = cur + loops;
+
+ while (end > cur)
+ cur = read_c0_cvmcount();
+}
+EXPORT_SYMBOL(__delay);
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
index be531ec1f206..d22b5a2d64f4 100644
--- a/arch/mips/cavium-octeon/dma-octeon.c
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -99,13 +99,16 @@ dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
panic("dma_map_single: "
"Attempt to map illegal memory address 0x%llx\n",
physical);
- else if ((physical + size >=
- (4ull<<30) - (OCTEON_PCI_BAR1_HOLE_SIZE<<20))
- && physical < (4ull<<30))
- pr_warning("dma_map_single: Warning: "
- "Mapping memory address that might "
- "conflict with devices 0x%llx-0x%llx\n",
- physical, physical+size-1);
+ else if (physical >= CVMX_PCIE_BAR1_PHYS_BASE &&
+ physical + size < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE)) {
+ result = physical - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
+
+ if (((result+size-1) & dma_mask) != result+size-1)
+ panic("dma_map_single: Attempt to map address 0x%llx-0x%llx, which can't be accessed according to the dma mask 0x%llx\n",
+ physical, physical+size-1, dma_mask);
+ goto done;
+ }
+
/* The 2nd 256MB is mapped at 256<<20 instead of 0x410000000 */
if ((physical >= 0x410000000ull) && physical < 0x420000000ull)
result = physical - 0x400000000ull;
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index c424cd158dc6..ce7500cdf5b7 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -3,15 +3,13 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 2004-2008 Cavium Networks
+ * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
*/
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/smp.h>
#include <asm/octeon/octeon.h>
-#include <asm/octeon/cvmx-pexp-defs.h>
-#include <asm/octeon/cvmx-npi-defs.h>
static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock);
static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock);
@@ -41,14 +39,14 @@ static void octeon_irq_core_ack(unsigned int irq)
static void octeon_irq_core_eoi(unsigned int irq)
{
- struct irq_desc *desc = irq_desc + irq;
+ struct irq_desc *desc = irq_to_desc(irq);
unsigned int bit = irq - OCTEON_IRQ_SW0;
/*
* If an IRQ is being processed while we are disabling it the
* handler will attempt to unmask the interrupt after it has
* been disabled.
*/
- if (desc->status & IRQ_DISABLED)
+ if ((unlikely(desc->status & IRQ_DISABLED)))
return;
/*
* We don't need to disable IRQs to make these atomic since
@@ -106,6 +104,29 @@ static struct irq_chip octeon_irq_chip_core = {
static void octeon_irq_ciu0_ack(unsigned int irq)
{
+ switch (irq) {
+ case OCTEON_IRQ_GMX_DRP0:
+ case OCTEON_IRQ_GMX_DRP1:
+ case OCTEON_IRQ_IPD_DRP:
+ case OCTEON_IRQ_KEY_ZERO:
+ case OCTEON_IRQ_TIMER0:
+ case OCTEON_IRQ_TIMER1:
+ case OCTEON_IRQ_TIMER2:
+ case OCTEON_IRQ_TIMER3:
+ {
+ int index = cvmx_get_core_num() * 2;
+ u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
+ /*
+ * CIU timer type interrupts must be acknoleged by
+ * writing a '1' bit to their sum0 bit.
+ */
+ cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
+ break;
+ }
+ default:
+ break;
+ }
+
/*
* In order to avoid any locking accessing the CIU, we
* acknowledge CIU interrupts by disabling all of them. This
@@ -130,8 +151,54 @@ static void octeon_irq_ciu0_eoi(unsigned int irq)
set_c0_status(0x100 << 2);
}
+static int next_coreid_for_irq(struct irq_desc *desc)
+{
+
+#ifdef CONFIG_SMP
+ int coreid;
+ int weight = cpumask_weight(desc->affinity);
+
+ if (weight > 1) {
+ int cpu = smp_processor_id();
+ for (;;) {
+ cpu = cpumask_next(cpu, desc->affinity);
+ if (cpu >= nr_cpu_ids) {
+ cpu = -1;
+ continue;
+ } else if (cpumask_test_cpu(cpu, cpu_online_mask)) {
+ break;
+ }
+ }
+ coreid = octeon_coreid_for_cpu(cpu);
+ } else if (weight == 1) {
+ coreid = octeon_coreid_for_cpu(cpumask_first(desc->affinity));
+ } else {
+ coreid = cvmx_get_core_num();
+ }
+ return coreid;
+#else
+ return cvmx_get_core_num();
+#endif
+}
+
static void octeon_irq_ciu0_enable(unsigned int irq)
{
+ struct irq_desc *desc = irq_to_desc(irq);
+ int coreid = next_coreid_for_irq(desc);
+ unsigned long flags;
+ uint64_t en0;
+ int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
+
+ raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
+ en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
+ en0 |= 1ull << bit;
+ cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
+ cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
+ raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
+}
+
+static void octeon_irq_ciu0_enable_mbox(unsigned int irq)
+{
int coreid = cvmx_get_core_num();
unsigned long flags;
uint64_t en0;
@@ -167,63 +234,76 @@ static void octeon_irq_ciu0_disable(unsigned int irq)
}
/*
- * Enable the irq on the current core for chips that have the EN*_W1{S,C}
- * registers.
+ * Enable the irq on the next core in the affinity set for chips that
+ * have the EN*_W1{S,C} registers.
*/
static void octeon_irq_ciu0_enable_v2(unsigned int irq)
{
- int index = cvmx_get_core_num() * 2;
+ int index;
u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
+ struct irq_desc *desc = irq_to_desc(irq);
- cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
+ if ((desc->status & IRQ_DISABLED) == 0) {
+ index = next_coreid_for_irq(desc) * 2;
+ cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
+ }
}
/*
- * Disable the irq on the current core for chips that have the EN*_W1{S,C}
- * registers.
+ * Enable the irq on the current CPU for chips that
+ * have the EN*_W1{S,C} registers.
*/
-static void octeon_irq_ciu0_ack_v2(unsigned int irq)
+static void octeon_irq_ciu0_enable_mbox_v2(unsigned int irq)
{
- int index = cvmx_get_core_num() * 2;
+ int index;
u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
- cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
+ index = cvmx_get_core_num() * 2;
+ cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
}
/*
- * CIU timer type interrupts must be acknoleged by writing a '1' bit
- * to their sum0 bit.
+ * Disable the irq on the current core for chips that have the EN*_W1{S,C}
+ * registers.
*/
-static void octeon_irq_ciu0_timer_ack(unsigned int irq)
+static void octeon_irq_ciu0_ack_v2(unsigned int irq)
{
int index = cvmx_get_core_num() * 2;
- uint64_t mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
- cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
-}
+ u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
-static void octeon_irq_ciu0_timer_ack_v1(unsigned int irq)
-{
- octeon_irq_ciu0_timer_ack(irq);
- octeon_irq_ciu0_ack(irq);
-}
+ switch (irq) {
+ case OCTEON_IRQ_GMX_DRP0:
+ case OCTEON_IRQ_GMX_DRP1:
+ case OCTEON_IRQ_IPD_DRP:
+ case OCTEON_IRQ_KEY_ZERO:
+ case OCTEON_IRQ_TIMER0:
+ case OCTEON_IRQ_TIMER1:
+ case OCTEON_IRQ_TIMER2:
+ case OCTEON_IRQ_TIMER3:
+ /*
+ * CIU timer type interrupts must be acknoleged by
+ * writing a '1' bit to their sum0 bit.
+ */
+ cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
+ break;
+ default:
+ break;
+ }
-static void octeon_irq_ciu0_timer_ack_v2(unsigned int irq)
-{
- octeon_irq_ciu0_timer_ack(irq);
- octeon_irq_ciu0_ack_v2(irq);
+ cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
}
/*
* Enable the irq on the current core for chips that have the EN*_W1{S,C}
* registers.
*/
-static void octeon_irq_ciu0_eoi_v2(unsigned int irq)
+static void octeon_irq_ciu0_eoi_mbox_v2(unsigned int irq)
{
- struct irq_desc *desc = irq_desc + irq;
+ struct irq_desc *desc = irq_to_desc(irq);
int index = cvmx_get_core_num() * 2;
u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
- if ((desc->status & IRQ_DISABLED) == 0)
+ if (likely((desc->status & IRQ_DISABLED) == 0))
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
}
@@ -246,18 +326,30 @@ static void octeon_irq_ciu0_disable_all_v2(unsigned int irq)
static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest)
{
int cpu;
+ struct irq_desc *desc = irq_to_desc(irq);
+ int enable_one = (desc->status & IRQ_DISABLED) == 0;
unsigned long flags;
int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
+ /*
+ * For non-v2 CIU, we will allow only single CPU affinity.
+ * This removes the need to do locking in the .ack/.eoi
+ * functions.
+ */
+ if (cpumask_weight(dest) != 1)
+ return -EINVAL;
+
raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
for_each_online_cpu(cpu) {
int coreid = octeon_coreid_for_cpu(cpu);
uint64_t en0 =
cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
- if (cpumask_test_cpu(cpu, dest))
+ if (cpumask_test_cpu(cpu, dest) && enable_one) {
+ enable_one = 0;
en0 |= 1ull << bit;
- else
+ } else {
en0 &= ~(1ull << bit);
+ }
cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
}
/*
@@ -279,13 +371,18 @@ static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq,
{
int cpu;
int index;
+ struct irq_desc *desc = irq_to_desc(irq);
+ int enable_one = (desc->status & IRQ_DISABLED) == 0;
u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
+
for_each_online_cpu(cpu) {
index = octeon_coreid_for_cpu(cpu) * 2;
- if (cpumask_test_cpu(cpu, dest))
+ if (cpumask_test_cpu(cpu, dest) && enable_one) {
+ enable_one = 0;
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
- else
+ } else {
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
+ }
}
return 0;
}
@@ -298,8 +395,7 @@ static struct irq_chip octeon_irq_chip_ciu0_v2 = {
.name = "CIU0",
.enable = octeon_irq_ciu0_enable_v2,
.disable = octeon_irq_ciu0_disable_all_v2,
- .ack = octeon_irq_ciu0_ack_v2,
- .eoi = octeon_irq_ciu0_eoi_v2,
+ .eoi = octeon_irq_ciu0_enable_v2,
#ifdef CONFIG_SMP
.set_affinity = octeon_irq_ciu0_set_affinity_v2,
#endif
@@ -309,36 +405,27 @@ static struct irq_chip octeon_irq_chip_ciu0 = {
.name = "CIU0",
.enable = octeon_irq_ciu0_enable,
.disable = octeon_irq_ciu0_disable,
- .ack = octeon_irq_ciu0_ack,
.eoi = octeon_irq_ciu0_eoi,
#ifdef CONFIG_SMP
.set_affinity = octeon_irq_ciu0_set_affinity,
#endif
};
-static struct irq_chip octeon_irq_chip_ciu0_timer_v2 = {
- .name = "CIU0-T",
- .enable = octeon_irq_ciu0_enable_v2,
- .disable = octeon_irq_ciu0_disable_all_v2,
- .ack = octeon_irq_ciu0_timer_ack_v2,
- .eoi = octeon_irq_ciu0_eoi_v2,
-#ifdef CONFIG_SMP
- .set_affinity = octeon_irq_ciu0_set_affinity_v2,
-#endif
+/* The mbox versions don't do any affinity or round-robin. */
+static struct irq_chip octeon_irq_chip_ciu0_mbox_v2 = {
+ .name = "CIU0-M",
+ .enable = octeon_irq_ciu0_enable_mbox_v2,
+ .disable = octeon_irq_ciu0_disable,
+ .eoi = octeon_irq_ciu0_eoi_mbox_v2,
};
-static struct irq_chip octeon_irq_chip_ciu0_timer = {
- .name = "CIU0-T",
- .enable = octeon_irq_ciu0_enable,
+static struct irq_chip octeon_irq_chip_ciu0_mbox = {
+ .name = "CIU0-M",
+ .enable = octeon_irq_ciu0_enable_mbox,
.disable = octeon_irq_ciu0_disable,
- .ack = octeon_irq_ciu0_timer_ack_v1,
.eoi = octeon_irq_ciu0_eoi,
-#ifdef CONFIG_SMP
- .set_affinity = octeon_irq_ciu0_set_affinity,
-#endif
};
-
static void octeon_irq_ciu1_ack(unsigned int irq)
{
/*
@@ -365,10 +452,30 @@ static void octeon_irq_ciu1_eoi(unsigned int irq)
static void octeon_irq_ciu1_enable(unsigned int irq)
{
- int coreid = cvmx_get_core_num();
+ struct irq_desc *desc = irq_to_desc(irq);
+ int coreid = next_coreid_for_irq(desc);
+ unsigned long flags;
+ uint64_t en1;
+ int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
+
+ raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
+ en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
+ en1 |= 1ull << bit;
+ cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
+ cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
+ raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
+}
+
+/*
+ * Watchdog interrupts are special. They are associated with a single
+ * core, so we hardwire the affinity to that core.
+ */
+static void octeon_irq_ciu1_wd_enable(unsigned int irq)
+{
unsigned long flags;
uint64_t en1;
int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
+ int coreid = bit;
raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
@@ -405,36 +512,43 @@ static void octeon_irq_ciu1_disable(unsigned int irq)
*/
static void octeon_irq_ciu1_enable_v2(unsigned int irq)
{
- int index = cvmx_get_core_num() * 2 + 1;
+ int index;
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
+ struct irq_desc *desc = irq_to_desc(irq);
- cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+ if ((desc->status & IRQ_DISABLED) == 0) {
+ index = next_coreid_for_irq(desc) * 2 + 1;
+ cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+ }
}
/*
- * Disable the irq on the current core for chips that have the EN*_W1{S,C}
- * registers.
+ * Watchdog interrupts are special. They are associated with a single
+ * core, so we hardwire the affinity to that core.
*/
-static void octeon_irq_ciu1_ack_v2(unsigned int irq)
+static void octeon_irq_ciu1_wd_enable_v2(unsigned int irq)
{
- int index = cvmx_get_core_num() * 2 + 1;
+ int index;
+ int coreid = irq - OCTEON_IRQ_WDOG0;
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
+ struct irq_desc *desc = irq_to_desc(irq);
- cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
+ if ((desc->status & IRQ_DISABLED) == 0) {
+ index = coreid * 2 + 1;
+ cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+ }
}
/*
- * Enable the irq on the current core for chips that have the EN*_W1{S,C}
+ * Disable the irq on the current core for chips that have the EN*_W1{S,C}
* registers.
*/
-static void octeon_irq_ciu1_eoi_v2(unsigned int irq)
+static void octeon_irq_ciu1_ack_v2(unsigned int irq)
{
- struct irq_desc *desc = irq_desc + irq;
int index = cvmx_get_core_num() * 2 + 1;
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
- if ((desc->status & IRQ_DISABLED) == 0)
- cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+ cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
}
/*
@@ -457,19 +571,30 @@ static int octeon_irq_ciu1_set_affinity(unsigned int irq,
const struct cpumask *dest)
{
int cpu;
+ struct irq_desc *desc = irq_to_desc(irq);
+ int enable_one = (desc->status & IRQ_DISABLED) == 0;
unsigned long flags;
int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
+ /*
+ * For non-v2 CIU, we will allow only single CPU affinity.
+ * This removes the need to do locking in the .ack/.eoi
+ * functions.
+ */
+ if (cpumask_weight(dest) != 1)
+ return -EINVAL;
+
raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
for_each_online_cpu(cpu) {
int coreid = octeon_coreid_for_cpu(cpu);
uint64_t en1 =
- cvmx_read_csr(CVMX_CIU_INTX_EN1
- (coreid * 2 + 1));
- if (cpumask_test_cpu(cpu, dest))
+ cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
+ if (cpumask_test_cpu(cpu, dest) && enable_one) {
+ enable_one = 0;
en1 |= 1ull << bit;
- else
+ } else {
en1 &= ~(1ull << bit);
+ }
cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
}
/*
@@ -491,13 +616,17 @@ static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq,
{
int cpu;
int index;
+ struct irq_desc *desc = irq_to_desc(irq);
+ int enable_one = (desc->status & IRQ_DISABLED) == 0;
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
for_each_online_cpu(cpu) {
index = octeon_coreid_for_cpu(cpu) * 2 + 1;
- if (cpumask_test_cpu(cpu, dest))
+ if (cpumask_test_cpu(cpu, dest) && enable_one) {
+ enable_one = 0;
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
- else
+ } else {
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
+ }
}
return 0;
}
@@ -507,11 +636,10 @@ static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq,
* Newer octeon chips have support for lockless CIU operation.
*/
static struct irq_chip octeon_irq_chip_ciu1_v2 = {
- .name = "CIU0",
+ .name = "CIU1",
.enable = octeon_irq_ciu1_enable_v2,
.disable = octeon_irq_ciu1_disable_all_v2,
- .ack = octeon_irq_ciu1_ack_v2,
- .eoi = octeon_irq_ciu1_eoi_v2,
+ .eoi = octeon_irq_ciu1_enable_v2,
#ifdef CONFIG_SMP
.set_affinity = octeon_irq_ciu1_set_affinity_v2,
#endif
@@ -521,103 +649,36 @@ static struct irq_chip octeon_irq_chip_ciu1 = {
.name = "CIU1",
.enable = octeon_irq_ciu1_enable,
.disable = octeon_irq_ciu1_disable,
- .ack = octeon_irq_ciu1_ack,
.eoi = octeon_irq_ciu1_eoi,
#ifdef CONFIG_SMP
.set_affinity = octeon_irq_ciu1_set_affinity,
#endif
};
-#ifdef CONFIG_PCI_MSI
-
-static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);
-
-static void octeon_irq_msi_ack(unsigned int irq)
-{
- if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
- /* These chips have PCI */
- cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
- 1ull << (irq - OCTEON_IRQ_MSI_BIT0));
- } else {
- /*
- * These chips have PCIe. Thankfully the ACK doesn't
- * need any locking.
- */
- cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
- 1ull << (irq - OCTEON_IRQ_MSI_BIT0));
- }
-}
-
-static void octeon_irq_msi_eoi(unsigned int irq)
-{
- /* Nothing needed */
-}
-
-static void octeon_irq_msi_enable(unsigned int irq)
-{
- if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
- /*
- * Octeon PCI doesn't have the ability to mask/unmask
- * MSI interrupts individually. Instead of
- * masking/unmasking them in groups of 16, we simple
- * assume MSI devices are well behaved. MSI
- * interrupts are always enable and the ACK is assumed
- * to be enough.
- */
- } else {
- /* These chips have PCIe. Note that we only support
- * the first 64 MSI interrupts. Unfortunately all the
- * MSI enables are in the same register. We use
- * MSI0's lock to control access to them all.
- */
- uint64_t en;
- unsigned long flags;
- raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
- en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
- en |= 1ull << (irq - OCTEON_IRQ_MSI_BIT0);
- cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
- cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
- raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
- }
-}
-
-static void octeon_irq_msi_disable(unsigned int irq)
-{
- if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
- /* See comment in enable */
- } else {
- /*
- * These chips have PCIe. Note that we only support
- * the first 64 MSI interrupts. Unfortunately all the
- * MSI enables are in the same register. We use
- * MSI0's lock to control access to them all.
- */
- uint64_t en;
- unsigned long flags;
- raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
- en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
- en &= ~(1ull << (irq - OCTEON_IRQ_MSI_BIT0));
- cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
- cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
- raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
- }
-}
+static struct irq_chip octeon_irq_chip_ciu1_wd_v2 = {
+ .name = "CIU1-W",
+ .enable = octeon_irq_ciu1_wd_enable_v2,
+ .disable = octeon_irq_ciu1_disable_all_v2,
+ .eoi = octeon_irq_ciu1_wd_enable_v2,
+};
-static struct irq_chip octeon_irq_chip_msi = {
- .name = "MSI",
- .enable = octeon_irq_msi_enable,
- .disable = octeon_irq_msi_disable,
- .ack = octeon_irq_msi_ack,
- .eoi = octeon_irq_msi_eoi,
+static struct irq_chip octeon_irq_chip_ciu1_wd = {
+ .name = "CIU1-W",
+ .enable = octeon_irq_ciu1_wd_enable,
+ .disable = octeon_irq_ciu1_disable,
+ .eoi = octeon_irq_ciu1_eoi,
};
-#endif
+
+static void (*octeon_ciu0_ack)(unsigned int);
+static void (*octeon_ciu1_ack)(unsigned int);
void __init arch_init_irq(void)
{
- int irq;
+ unsigned int irq;
struct irq_chip *chip0;
- struct irq_chip *chip0_timer;
+ struct irq_chip *chip0_mbox;
struct irq_chip *chip1;
+ struct irq_chip *chip1_wd;
#ifdef CONFIG_SMP
/* Set the default affinity to the boot cpu. */
@@ -631,13 +692,19 @@ void __init arch_init_irq(void)
if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) {
+ octeon_ciu0_ack = octeon_irq_ciu0_ack_v2;
+ octeon_ciu1_ack = octeon_irq_ciu1_ack_v2;
chip0 = &octeon_irq_chip_ciu0_v2;
- chip0_timer = &octeon_irq_chip_ciu0_timer_v2;
+ chip0_mbox = &octeon_irq_chip_ciu0_mbox_v2;
chip1 = &octeon_irq_chip_ciu1_v2;
+ chip1_wd = &octeon_irq_chip_ciu1_wd_v2;
} else {
+ octeon_ciu0_ack = octeon_irq_ciu0_ack;
+ octeon_ciu1_ack = octeon_irq_ciu1_ack;
chip0 = &octeon_irq_chip_ciu0;
- chip0_timer = &octeon_irq_chip_ciu0_timer;
+ chip0_mbox = &octeon_irq_chip_ciu0_mbox;
chip1 = &octeon_irq_chip_ciu1;
+ chip1_wd = &octeon_irq_chip_ciu1_wd;
}
/* 0 - 15 reserved for i8259 master and slave controller. */
@@ -651,34 +718,23 @@ void __init arch_init_irq(void)
/* 24 - 87 CIU_INT_SUM0 */
for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
switch (irq) {
- case OCTEON_IRQ_GMX_DRP0:
- case OCTEON_IRQ_GMX_DRP1:
- case OCTEON_IRQ_IPD_DRP:
- case OCTEON_IRQ_KEY_ZERO:
- case OCTEON_IRQ_TIMER0:
- case OCTEON_IRQ_TIMER1:
- case OCTEON_IRQ_TIMER2:
- case OCTEON_IRQ_TIMER3:
- set_irq_chip_and_handler(irq, chip0_timer, handle_percpu_irq);
+ case OCTEON_IRQ_MBOX0:
+ case OCTEON_IRQ_MBOX1:
+ set_irq_chip_and_handler(irq, chip0_mbox, handle_percpu_irq);
break;
default:
- set_irq_chip_and_handler(irq, chip0, handle_percpu_irq);
+ set_irq_chip_and_handler(irq, chip0, handle_fasteoi_irq);
break;
}
}
/* 88 - 151 CIU_INT_SUM1 */
- for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) {
- set_irq_chip_and_handler(irq, chip1, handle_percpu_irq);
- }
+ for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_WDOG15; irq++)
+ set_irq_chip_and_handler(irq, chip1_wd, handle_fasteoi_irq);
+
+ for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED151; irq++)
+ set_irq_chip_and_handler(irq, chip1, handle_fasteoi_irq);
-#ifdef CONFIG_PCI_MSI
- /* 152 - 215 PCI/PCIe MSI interrupts */
- for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_BIT63; irq++) {
- set_irq_chip_and_handler(irq, &octeon_irq_chip_msi,
- handle_percpu_irq);
- }
-#endif
set_c0_status(0x300 << 2);
}
@@ -693,6 +749,7 @@ asmlinkage void plat_irq_dispatch(void)
unsigned long cop0_status;
uint64_t ciu_en;
uint64_t ciu_sum;
+ unsigned int irq;
while (1) {
cop0_cause = read_c0_cause();
@@ -704,18 +761,24 @@ asmlinkage void plat_irq_dispatch(void)
ciu_sum = cvmx_read_csr(ciu_sum0_address);
ciu_en = cvmx_read_csr(ciu_en0_address);
ciu_sum &= ciu_en;
- if (likely(ciu_sum))
- do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1);
- else
+ if (likely(ciu_sum)) {
+ irq = fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1;
+ octeon_ciu0_ack(irq);
+ do_IRQ(irq);
+ } else {
spurious_interrupt();
+ }
} else if (unlikely(cop0_cause & STATUSF_IP3)) {
ciu_sum = cvmx_read_csr(ciu_sum1_address);
ciu_en = cvmx_read_csr(ciu_en1_address);
ciu_sum &= ciu_en;
- if (likely(ciu_sum))
- do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1);
- else
+ if (likely(ciu_sum)) {
+ irq = fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1;
+ octeon_ciu1_ack(irq);
+ do_IRQ(irq);
+ } else {
spurious_interrupt();
+ }
} else if (likely(cop0_cause)) {
do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE);
} else {
@@ -725,54 +788,84 @@ asmlinkage void plat_irq_dispatch(void)
}
#ifdef CONFIG_HOTPLUG_CPU
-static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu)
-{
- unsigned int isset;
- int coreid = octeon_coreid_for_cpu(cpu);
- int bit = (irq < OCTEON_IRQ_WDOG0) ?
- irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0;
- if (irq < 64) {
- isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) &
- (1ull << bit)) >> bit;
- } else {
- isset = (cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)) &
- (1ull << bit)) >> bit;
- }
- return isset;
-}
void fixup_irqs(void)
{
- int irq;
+ int irq;
+ struct irq_desc *desc;
+ cpumask_t new_affinity;
+ unsigned long flags;
+ int do_set_affinity;
+ int cpu;
+
+ cpu = smp_processor_id();
for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++)
octeon_irq_core_disable_local(irq);
- for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_GPIO15; irq++) {
- if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
- /* ciu irq migrates to next cpu */
- octeon_irq_chip_ciu0.disable(irq);
- octeon_irq_ciu0_set_affinity(irq, &cpu_online_map);
- }
- }
-
-#if 0
- for (irq = OCTEON_IRQ_MBOX0; irq <= OCTEON_IRQ_MBOX1; irq++)
- octeon_irq_mailbox_mask(irq);
-#endif
- for (irq = OCTEON_IRQ_UART0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
- if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
- /* ciu irq migrates to next cpu */
- octeon_irq_chip_ciu0.disable(irq);
- octeon_irq_ciu0_set_affinity(irq, &cpu_online_map);
- }
- }
+ for (irq = OCTEON_IRQ_WORKQ0; irq < OCTEON_IRQ_LAST; irq++) {
+ desc = irq_to_desc(irq);
+ switch (irq) {
+ case OCTEON_IRQ_MBOX0:
+ case OCTEON_IRQ_MBOX1:
+ /* The eoi function will disable them on this CPU. */
+ desc->chip->eoi(irq);
+ break;
+ case OCTEON_IRQ_WDOG0:
+ case OCTEON_IRQ_WDOG1:
+ case OCTEON_IRQ_WDOG2:
+ case OCTEON_IRQ_WDOG3:
+ case OCTEON_IRQ_WDOG4:
+ case OCTEON_IRQ_WDOG5:
+ case OCTEON_IRQ_WDOG6:
+ case OCTEON_IRQ_WDOG7:
+ case OCTEON_IRQ_WDOG8:
+ case OCTEON_IRQ_WDOG9:
+ case OCTEON_IRQ_WDOG10:
+ case OCTEON_IRQ_WDOG11:
+ case OCTEON_IRQ_WDOG12:
+ case OCTEON_IRQ_WDOG13:
+ case OCTEON_IRQ_WDOG14:
+ case OCTEON_IRQ_WDOG15:
+ /*
+ * These have special per CPU semantics and
+ * are handled in the watchdog driver.
+ */
+ break;
+ default:
+ raw_spin_lock_irqsave(&desc->lock, flags);
+ /*
+ * If this irq has an action, it is in use and
+ * must be migrated if it has affinity to this
+ * cpu.
+ */
+ if (desc->action && cpumask_test_cpu(cpu, desc->affinity)) {
+ if (cpumask_weight(desc->affinity) > 1) {
+ /*
+ * It has multi CPU affinity,
+ * just remove this CPU from
+ * the affinity set.
+ */
+ cpumask_copy(&new_affinity, desc->affinity);
+ cpumask_clear_cpu(cpu, &new_affinity);
+ } else {
+ /*
+ * Otherwise, put it on lowest
+ * numbered online CPU.
+ */
+ cpumask_clear(&new_affinity);
+ cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
+ }
+ do_set_affinity = 1;
+ } else {
+ do_set_affinity = 0;
+ }
+ raw_spin_unlock_irqrestore(&desc->lock, flags);
+
+ if (do_set_affinity)
+ irq_set_affinity(irq, &new_affinity);
- for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED135; irq++) {
- if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
- /* ciu irq migrates to next cpu */
- octeon_irq_chip_ciu1.disable(irq);
- octeon_irq_ciu1_set_affinity(irq, &cpu_online_map);
+ break;
}
}
}
diff --git a/arch/mips/cavium-octeon/octeon_boot.h b/arch/mips/cavium-octeon/octeon_boot.h
index 0f7f84accf9a..428864b2ba41 100644
--- a/arch/mips/cavium-octeon/octeon_boot.h
+++ b/arch/mips/cavium-octeon/octeon_boot.h
@@ -23,14 +23,16 @@
#include <linux/types.h>
struct boot_init_vector {
- uint32_t stack_addr;
- uint32_t code_addr;
+ /* First stage address - in ram instead of flash */
+ uint64_t code_addr;
+ /* Setup code for application, NOT application entry point */
uint32_t app_start_func_addr;
+ /* k0 is used for global data - needs to be passed to other cores */
uint32_t k0_val;
- uint32_t flags;
- uint32_t boot_info_addr;
+ /* Address of boot info block structure */
+ uint64_t boot_info_addr;
+ uint32_t flags; /* flags */
uint32_t pad;
- uint32_t pad2;
};
/* similar to bootloader's linux_app_boot_info but without global data */
@@ -40,7 +42,7 @@ struct linux_app_boot_info {
uint32_t avail_coremask;
uint32_t pci_console_active;
uint32_t icache_prefetch_disable;
- uint32_t InitTLBStart_addr;
+ uint64_t InitTLBStart_addr;
uint32_t start_app_addr;
uint32_t cur_exception_base;
uint32_t no_mark_private_data;
@@ -58,7 +60,7 @@ struct linux_app_boot_info {
#define LINUX_APP_BOOT_BLOCK_NAME "linux-app-boot"
-#define LABI_SIGNATURE 0xAABBCCDD
+#define LABI_SIGNATURE 0xAABBCC01
/* from uboot-headers/octeon_mem_map.h */
#define EXCEPTION_BASE_INCR (4 * 1024)
diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c
index 83eac37a1ff9..638adab02842 100644
--- a/arch/mips/cavium-octeon/serial.c
+++ b/arch/mips/cavium-octeon/serial.c
@@ -18,11 +18,7 @@
#include <asm/octeon/octeon.h>
-#ifdef CONFIG_GDB_CONSOLE
-#define DEBUG_UART 0
-#else
#define DEBUG_UART 1
-#endif
unsigned int octeon_serial_in(struct uart_port *up, int offset)
{
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index d1b5ffaf0281..69197cb6c7ea 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -32,6 +32,7 @@
#include <asm/time.h>
#include <asm/octeon/octeon.h>
+#include <asm/octeon/pci-octeon.h>
#ifdef CONFIG_CAVIUM_DECODE_RSL
extern void cvmx_interrupt_rsl_decode(void);
@@ -578,9 +579,6 @@ void __init prom_init(void)
}
if (strstr(arcs_cmdline, "console=") == NULL) {
-#ifdef CONFIG_GDB_CONSOLE
- strcat(arcs_cmdline, " console=gdb");
-#else
#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
strcat(arcs_cmdline, " console=ttyS0,115200");
#else
@@ -589,7 +587,6 @@ void __init prom_init(void)
else
strcat(arcs_cmdline, " console=ttyS0,115200");
#endif
-#endif
}
if (octeon_is_simulation()) {
@@ -598,13 +595,13 @@ void __init prom_init(void)
* the filesystem. Also specify the calibration delay
* to avoid calculating it every time.
*/
- strcat(arcs_cmdline, " rw root=1f00"
- " lpj=60176 slram=root,0x40000000,+1073741824");
+ strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824");
}
mips_hpt_frequency = octeon_get_clock_rate();
octeon_init_cvmcount();
+ octeon_setup_delays();
_machine_restart = octeon_restart;
_machine_halt = octeon_halt;
@@ -613,6 +610,22 @@ void __init prom_init(void)
register_smp_ops(&octeon_smp_ops);
}
+/* Exclude a single page from the regions obtained in plat_mem_setup. */
+static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
+{
+ if (addr > *mem && addr < *mem + *size) {
+ u64 inc = addr - *mem;
+ add_memory_region(*mem, inc, BOOT_MEM_RAM);
+ *mem += inc;
+ *size -= inc;
+ }
+
+ if (addr == *mem && *size > PAGE_SIZE) {
+ *mem += PAGE_SIZE;
+ *size -= PAGE_SIZE;
+ }
+}
+
void __init plat_mem_setup(void)
{
uint64_t mem_alloc_size;
@@ -663,12 +676,27 @@ void __init plat_mem_setup(void)
CVMX_BOOTMEM_FLAG_NO_LOCKING);
#endif
if (memory >= 0) {
+ u64 size = mem_alloc_size;
+
+ /*
+ * exclude a page at the beginning and end of
+ * the 256MB PCIe 'hole' so the kernel will not
+ * try to allocate multi-page buffers that
+ * span the discontinuity.
+ */
+ memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE,
+ &memory, &size);
+ memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE +
+ CVMX_PCIE_BAR1_PHYS_SIZE,
+ &memory, &size);
+
/*
* This function automatically merges address
* regions next to each other if they are
* received in incrementing order.
*/
- add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
+ if (size)
+ add_memory_region(memory, size, BOOT_MEM_RAM);
total += mem_alloc_size;
} else {
break;
@@ -691,7 +719,10 @@ void __init plat_mem_setup(void)
"cvmx_bootmem_phy_alloc\n");
}
-
+/*
+ * Emit one character to the boot UART. Exported for use by the
+ * watchdog timer.
+ */
int prom_putchar(char c)
{
uint64_t lsrval;
@@ -705,6 +736,7 @@ int prom_putchar(char c)
cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
return 1;
}
+EXPORT_SYMBOL(prom_putchar);
void prom_free_prom_memory(void)
{
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index 6d99b9d8887d..391cefe556b3 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 2004-2008 Cavium Networks
+ * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
*/
#include <linux/cpu.h>
#include <linux/init.h>
@@ -27,7 +27,8 @@ volatile unsigned long octeon_processor_sp;
volatile unsigned long octeon_processor_gp;
#ifdef CONFIG_HOTPLUG_CPU
-static unsigned int InitTLBStart_addr;
+uint64_t octeon_bootloader_entry_addr;
+EXPORT_SYMBOL(octeon_bootloader_entry_addr);
#endif
static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
@@ -80,20 +81,13 @@ static inline void octeon_send_ipi_mask(const struct cpumask *mask,
static void octeon_smp_hotplug_setup(void)
{
#ifdef CONFIG_HOTPLUG_CPU
- uint32_t labi_signature;
-
- labi_signature =
- cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
- LABI_ADDR_IN_BOOTLOADER +
- offsetof(struct linux_app_boot_info,
- labi_signature)));
- if (labi_signature != LABI_SIGNATURE)
- pr_err("The bootloader version on this board is incorrect\n");
- InitTLBStart_addr =
- cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
- LABI_ADDR_IN_BOOTLOADER +
- offsetof(struct linux_app_boot_info,
- InitTLBStart_addr)));
+ struct linux_app_boot_info *labi;
+
+ labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
+ if (labi->labi_signature != LABI_SIGNATURE)
+ panic("The bootloader version on this board is incorrect.");
+
+ octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
#endif
}
@@ -102,24 +96,47 @@ static void octeon_smp_setup(void)
const int coreid = cvmx_get_core_num();
int cpus;
int id;
-
int core_mask = octeon_get_boot_coremask();
+#ifdef CONFIG_HOTPLUG_CPU
+ unsigned int num_cores = cvmx_octeon_num_cores();
+#endif
+
+ /* The present CPUs are initially just the boot cpu (CPU 0). */
+ for (id = 0; id < NR_CPUS; id++) {
+ set_cpu_possible(id, id == 0);
+ set_cpu_present(id, id == 0);
+ }
- cpus_clear(cpu_possible_map);
__cpu_number_map[coreid] = 0;
__cpu_logical_map[0] = coreid;
- cpu_set(0, cpu_possible_map);
+ /* The present CPUs get the lowest CPU numbers. */
cpus = 1;
- for (id = 0; id < 16; id++) {
+ for (id = 0; id < NR_CPUS; id++) {
if ((id != coreid) && (core_mask & (1 << id))) {
- cpu_set(cpus, cpu_possible_map);
+ set_cpu_possible(cpus, true);
+ set_cpu_present(cpus, true);
__cpu_number_map[id] = cpus;
__cpu_logical_map[cpus] = id;
cpus++;
}
}
- cpu_present_map = cpu_possible_map;
+
+#ifdef CONFIG_HOTPLUG_CPU
+ /*
+ * The possible CPUs are all those present on the chip. We
+ * will assign CPU numbers for possible cores as well. Cores
+ * are always consecutively numberd from 0.
+ */
+ for (id = 0; id < num_cores && id < NR_CPUS; id++) {
+ if (!(core_mask & (1 << id))) {
+ set_cpu_possible(cpus, true);
+ __cpu_number_map[id] = cpus;
+ __cpu_logical_map[cpus] = id;
+ cpus++;
+ }
+ }
+#endif
octeon_smp_hotplug_setup();
}
@@ -158,18 +175,21 @@ static void octeon_init_secondary(void)
{
const int coreid = cvmx_get_core_num();
union cvmx_ciu_intx_sum0 interrupt_enable;
+ unsigned int sr;
#ifdef CONFIG_HOTPLUG_CPU
- unsigned int cur_exception_base;
-
- cur_exception_base = cvmx_read64_uint32(
- CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
- LABI_ADDR_IN_BOOTLOADER +
- offsetof(struct linux_app_boot_info,
- cur_exception_base)));
- /* cur_exception_base is incremented in bootloader after setting */
- write_c0_ebase((unsigned int)(cur_exception_base - EXCEPTION_BASE_INCR));
+ struct linux_app_boot_info *labi;
+
+ labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
+
+ if (labi->labi_signature != LABI_SIGNATURE)
+ panic("The bootloader version on this board is incorrect.");
#endif
+
+ sr = set_c0_status(ST0_BEV);
+ write_c0_ebase((u32)ebase);
+ write_c0_status(sr);
+
octeon_check_cpu_bist();
octeon_init_cvmcount();
/*
@@ -276,8 +296,8 @@ static int octeon_cpu_disable(void)
static void octeon_cpu_die(unsigned int cpu)
{
int coreid = cpu_logical_map(cpu);
- uint32_t avail_coremask;
- struct cvmx_bootmem_named_block_desc *block_desc;
+ uint32_t mask, new_mask;
+ const struct cvmx_bootmem_named_block_desc *block_desc;
while (per_cpu(cpu_state, cpu) != CPU_DEAD)
cpu_relax();
@@ -286,52 +306,40 @@ static void octeon_cpu_die(unsigned int cpu)
* This is a bit complicated strategics of getting/settig available
* cores mask, copied from bootloader
*/
+
+ mask = 1 << coreid;
/* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
if (!block_desc) {
- avail_coremask =
- cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
- LABI_ADDR_IN_BOOTLOADER +
- offsetof
- (struct linux_app_boot_info,
- avail_coremask)));
- } else { /* alternative, already initialized */
- avail_coremask =
- cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
- block_desc->base_addr +
- AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
- }
+ struct linux_app_boot_info *labi;
- avail_coremask |= 1 << coreid;
+ labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
- /* Setting avail_coremask for bootoct binary */
- if (!block_desc) {
- cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
- LABI_ADDR_IN_BOOTLOADER +
- offsetof(struct linux_app_boot_info,
- avail_coremask)),
- avail_coremask);
- } else {
- cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
- block_desc->base_addr +
- AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK),
- avail_coremask);
+ labi->avail_coremask |= mask;
+ new_mask = labi->avail_coremask;
+ } else { /* alternative, already initialized */
+ uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
+ AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
+ *p |= mask;
+ new_mask = *p;
}
- pr_info("Reset core %d. Available Coremask = %x\n", coreid,
- avail_coremask);
+ pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
+ mb();
cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
cvmx_write_csr(CVMX_CIU_PP_RST, 0);
}
void play_dead(void)
{
- int coreid = cvmx_get_core_num();
+ int cpu = cpu_number_map(cvmx_get_core_num());
idle_task_exit();
octeon_processor_boot = 0xff;
- per_cpu(cpu_state, coreid) = CPU_DEAD;
+ per_cpu(cpu_state, cpu) = CPU_DEAD;
+
+ mb();
while (1) /* core will be reset here */
;
@@ -344,29 +352,27 @@ static void start_after_reset(void)
kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */
}
-int octeon_update_boot_vector(unsigned int cpu)
+static int octeon_update_boot_vector(unsigned int cpu)
{
int coreid = cpu_logical_map(cpu);
- unsigned int avail_coremask;
- struct cvmx_bootmem_named_block_desc *block_desc;
+ uint32_t avail_coremask;
+ const struct cvmx_bootmem_named_block_desc *block_desc;
struct boot_init_vector *boot_vect =
- (struct boot_init_vector *) cvmx_phys_to_ptr(0x0 +
- BOOTLOADER_BOOT_VECTOR);
+ (struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);
block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
if (!block_desc) {
- avail_coremask =
- cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
- LABI_ADDR_IN_BOOTLOADER +
- offsetof(struct linux_app_boot_info,
- avail_coremask)));
+ struct linux_app_boot_info *labi;
+
+ labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
+
+ avail_coremask = labi->avail_coremask;
+ labi->avail_coremask &= ~(1 << coreid);
} else { /* alternative, already initialized */
- avail_coremask =
- cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
- block_desc->base_addr +
- AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
+ avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED(
+ block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
}
if (!(avail_coremask & (1 << coreid))) {
@@ -377,9 +383,9 @@ int octeon_update_boot_vector(unsigned int cpu)
boot_vect[coreid].app_start_func_addr =
(uint32_t) (unsigned long) start_after_reset;
- boot_vect[coreid].code_addr = InitTLBStart_addr;
+ boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;
- CVMX_SYNC;
+ mb();
cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
@@ -405,17 +411,11 @@ static int __cpuinit octeon_cpu_callback(struct notifier_block *nfb,
return NOTIFY_OK;
}
-static struct notifier_block __cpuinitdata octeon_cpu_notifier = {
- .notifier_call = octeon_cpu_callback,
-};
-
static int __cpuinit register_cavium_notifier(void)
{
- register_hotcpu_notifier(&octeon_cpu_notifier);
-
+ hotcpu_notifier(octeon_cpu_callback, 0);
return 0;
}
-
late_initcall(register_cavium_notifier);
#endif /* CONFIG_HOTPLUG_CPU */
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