diff options
Diffstat (limited to 'arch/mips/mips-boards/generic')
| -rw-r--r-- | arch/mips/mips-boards/generic/init.c | 12 | ||||
| -rw-r--r-- | arch/mips/mips-boards/generic/memory.c | 4 | ||||
| -rw-r--r-- | arch/mips/mips-boards/generic/pci.c | 2 | ||||
| -rw-r--r-- | arch/mips/mips-boards/generic/time.c | 149 |
4 files changed, 31 insertions, 136 deletions
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c index e2c7147fedf7..30f1f54cb68b 100644 --- a/arch/mips/mips-boards/generic/init.c +++ b/arch/mips/mips-boards/generic/init.c @@ -166,15 +166,15 @@ static void __init console_config(void) bits = '8'; if (flow == '\0') flow = 'r'; - sprintf (console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); - strcat (prom_getcmdline(), console_string); + sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); + strcat(prom_getcmdline(), console_string); pr_info("Config serial console:%s\n", console_string); } } #endif #ifdef CONFIG_KGDB -void __init kgdb_config (void) +void __init kgdb_config(void) { extern int (*generic_putDebugChar)(char); extern char (*generic_getDebugChar)(void); @@ -218,7 +218,7 @@ void __init kgdb_config (void) { char *s; for (s = "Please connect GDB to this port\r\n"; *s; ) - generic_putDebugChar (*s++); + generic_putDebugChar(*s++); } /* Breakpoint is invoked after interrupts are initialised */ @@ -226,7 +226,7 @@ void __init kgdb_config (void) } #endif -void __init mips_nmi_setup (void) +void __init mips_nmi_setup(void) { void *base; extern char except_vec_nmi; @@ -238,7 +238,7 @@ void __init mips_nmi_setup (void) flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); } -void __init mips_ejtag_setup (void) +void __init mips_ejtag_setup(void) { void *base; extern char except_vec_ejtag_debug; diff --git a/arch/mips/mips-boards/generic/memory.c b/arch/mips/mips-boards/generic/memory.c index ae39953da2c4..dc272c188233 100644 --- a/arch/mips/mips-boards/generic/memory.c +++ b/arch/mips/mips-boards/generic/memory.c @@ -125,7 +125,7 @@ struct prom_pmemblock * __init prom_getmdesc(void) return &mdesc[0]; } -static int __init prom_memtype_classify (unsigned int type) +static int __init prom_memtype_classify(unsigned int type) { switch (type) { case yamon_free: @@ -158,7 +158,7 @@ void __init prom_meminit(void) long type; unsigned long base, size; - type = prom_memtype_classify (p->type); + type = prom_memtype_classify(p->type); base = p->base; size = p->size; diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c index c9852206890a..b9743190609a 100644 --- a/arch/mips/mips-boards/generic/pci.c +++ b/arch/mips/mips-boards/generic/pci.c @@ -239,5 +239,5 @@ void __init mips_pcibios_init(void) iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ ioport_resource.end = controller->io_resource->end; - register_pci_controller (controller); + register_pci_controller(controller); } diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index d7bff9ca5356..1d00b778ff1e 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -31,6 +31,7 @@ #include <asm/mipsregs.h> #include <asm/mipsmtregs.h> #include <asm/hardirq.h> +#include <asm/i8253.h> #include <asm/irq.h> #include <asm/div64.h> #include <asm/cpu.h> @@ -55,7 +56,6 @@ unsigned long cpu_khz; static int mips_cpu_timer_irq; extern int cp0_perfcount_irq; -extern void smtc_timer_broadcast(void); static void mips_timer_dispatch(void) { @@ -68,108 +68,6 @@ static void mips_perf_dispatch(void) } /* - * Redeclare until I get around mopping the timer code insanity on MIPS. - */ -extern int null_perf_irq(void); - -extern int (*perf_irq)(void); - -/* - * Possibly handle a performance counter interrupt. - * Return true if the timer interrupt should not be checked - */ -static inline int handle_perf_irq (int r2) -{ - /* - * The performance counter overflow interrupt may be shared with the - * timer interrupt (cp0_perfcount_irq < 0). If it is and a - * performance counter has overflowed (perf_irq() == IRQ_HANDLED) - * and we can't reliably determine if a counter interrupt has also - * happened (!r2) then don't check for a timer interrupt. - */ - return (cp0_perfcount_irq < 0) && - perf_irq() == IRQ_HANDLED && - !r2; -} - -irqreturn_t mips_timer_interrupt(int irq, void *dev_id) -{ - int cpu = smp_processor_id(); - -#ifdef CONFIG_MIPS_MT_SMTC - /* - * In an SMTC system, one Count/Compare set exists per VPE. - * Which TC within a VPE gets the interrupt is essentially - * random - we only know that it shouldn't be one with - * IXMT set. Whichever TC gets the interrupt needs to - * send special interprocessor interrupts to the other - * TCs to make sure that they schedule, etc. - * - * That code is specific to the SMTC kernel, not to - * the a particular platform, so it's invoked from - * the general MIPS timer_interrupt routine. - */ - - /* - * We could be here due to timer interrupt, - * perf counter overflow, or both. - */ - (void) handle_perf_irq(1); - - if (read_c0_cause() & (1 << 30)) { - /* - * There are things we only want to do once per tick - * in an "MP" system. One TC of each VPE will take - * the actual timer interrupt. The others will get - * timer broadcast IPIs. We use whoever it is that takes - * the tick on VPE 0 to run the full timer_interrupt(). - */ - if (cpu_data[cpu].vpe_id == 0) { - timer_interrupt(irq, NULL); - } else { - write_c0_compare(read_c0_count() + - (mips_hpt_frequency/HZ)); - local_timer_interrupt(irq, dev_id); - } - smtc_timer_broadcast(); - } -#else /* CONFIG_MIPS_MT_SMTC */ - int r2 = cpu_has_mips_r2; - - if (handle_perf_irq(r2)) - goto out; - - if (r2 && ((read_c0_cause() & (1 << 30)) == 0)) - goto out; - - if (cpu == 0) { - /* - * CPU 0 handles the global timer interrupt job and process - * accounting resets count/compare registers to trigger next - * timer int. - */ - timer_interrupt(irq, NULL); - } else { - /* Everyone else needs to reset the timer int here as - ll_local_timer_interrupt doesn't */ - /* - * FIXME: need to cope with counter underflow. - * More support needs to be added to kernel/time for - * counter/timer interrupts on multiple CPU's - */ - write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ)); - - /* - * Other CPUs should do profiling and process accounting - */ - local_timer_interrupt(irq, dev_id); - } -out: -#endif /* CONFIG_MIPS_MT_SMTC */ - return IRQ_HANDLED; -} - -/* * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect */ static unsigned int __init estimate_cpu_frequency(void) @@ -224,19 +122,19 @@ static unsigned int __init estimate_cpu_frequency(void) return count; } -unsigned long __init mips_rtc_get_time(void) +unsigned long read_persistent_clock(void) { return mc146818_get_cmos_time(); } -void __init mips_time_init(void) +void __init plat_time_init(void) { unsigned int est_freq; /* Set Data mode - binary. */ CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); - est_freq = estimate_cpu_frequency (); + est_freq = estimate_cpu_frequency(); printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, (est_freq%1000000)*100/1000000); @@ -244,38 +142,37 @@ void __init mips_time_init(void) cpu_khz = est_freq / 1000; mips_scroll_message(); +#ifdef CONFIG_I8253 /* Only Malta has a PIT */ + setup_pit_timer(); +#endif } -irqreturn_t mips_perf_interrupt(int irq, void *dev_id) -{ - return perf_irq(); -} +//static irqreturn_t mips_perf_interrupt(int irq, void *dev_id) +//{ +// return perf_irq(); +//} -static struct irqaction perf_irqaction = { - .handler = mips_perf_interrupt, - .flags = IRQF_DISABLED | IRQF_PERCPU, - .name = "performance", -}; +//static struct irqaction perf_irqaction = { +// .handler = mips_perf_interrupt, +// .flags = IRQF_DISABLED | IRQF_PERCPU, +// .name = "performance", +//}; -void __init plat_perf_setup(struct irqaction *irq) +void __init plat_perf_setup(void) { +// struct irqaction *irq = &perf_irqaction; + cp0_perfcount_irq = -1; #ifdef MSC01E_INT_BASE if (cpu_has_veic) { - set_vi_handler (MSC01E_INT_PERFCTR, mips_perf_dispatch); + set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch); cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; } else #endif if (cp0_perfcount_irq >= 0) { if (cpu_has_vint) set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); -#ifdef CONFIG_MIPS_MT_SMTC - setup_irq_smtc(cp0_perfcount_irq, irq, - 0x100 << cp0_perfcount_irq); -#else - setup_irq(cp0_perfcount_irq, irq); -#endif /* CONFIG_MIPS_MT_SMTC */ #ifdef CONFIG_SMP set_irq_handler(cp0_perfcount_irq, handle_percpu_irq); #endif @@ -286,7 +183,7 @@ void __init plat_timer_setup(struct irqaction *irq) { #ifdef MSC01E_INT_BASE if (cpu_has_veic) { - set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch); + set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; } else @@ -297,8 +194,6 @@ void __init plat_timer_setup(struct irqaction *irq) mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; } - /* we are using the cpu counter for timer interrupts */ - irq->handler = mips_timer_interrupt; /* we use our own handler */ #ifdef CONFIG_MIPS_MT_SMTC setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << cp0_compare_irq); #else @@ -308,5 +203,5 @@ void __init plat_timer_setup(struct irqaction *irq) set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); #endif - plat_perf_setup(&perf_irqaction); + plat_perf_setup(); } |