diff options
Diffstat (limited to 'arch/powerpc/boot')
46 files changed, 2814 insertions, 112 deletions
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts b/arch/powerpc/boot/dts/gef_ppc9a.dts index 53a7a6255909..910944edd886 100644 --- a/arch/powerpc/boot/dts/gef_ppc9a.dts +++ b/arch/powerpc/boot/dts/gef_ppc9a.dts @@ -164,9 +164,21 @@ device_type = "soc"; compatible = "fsl,mpc8641-soc", "simple-bus"; ranges = <0x0 0xfef00000 0x00100000>; - reg = <0xfef00000 0x100000>; // CCSRBAR 1M bus-frequency = <33333333>; + mcm-law@0 { + compatible = "fsl,mcm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + mcm@1000 { + compatible = "fsl,mpc8641-mcm", "fsl,mcm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + i2c1: i2c@3000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts index 1569117e5ddc..0f4c9ec2c3a6 100644 --- a/arch/powerpc/boot/dts/gef_sbc310.dts +++ b/arch/powerpc/boot/dts/gef_sbc310.dts @@ -163,9 +163,21 @@ device_type = "soc"; compatible = "simple-bus"; ranges = <0x0 0xfef00000 0x00100000>; - reg = <0xfef00000 0x100000>; // CCSRBAR 1M bus-frequency = <33333333>; + mcm-law@0 { + compatible = "fsl,mcm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + mcm@1000 { + compatible = "fsl,mpc8641-mcm", "fsl,mcm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + i2c1: i2c@3000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts index 6582dbd36da7..217f8aa66725 100644 --- a/arch/powerpc/boot/dts/gef_sbc610.dts +++ b/arch/powerpc/boot/dts/gef_sbc610.dts @@ -128,9 +128,21 @@ device_type = "soc"; compatible = "simple-bus"; ranges = <0x0 0xfef00000 0x00100000>; - reg = <0xfef00000 0x100000>; // CCSRBAR 1M bus-frequency = <33333333>; + mcm-law@0 { + compatible = "fsl,mcm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + mcm@1000 { + compatible = "fsl,mpc8641-mcm", "fsl,mcm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + i2c1: i2c@3000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts index c9cfd374bffb..bdb7fc0fa332 100644 --- a/arch/powerpc/boot/dts/ksi8560.dts +++ b/arch/powerpc/boot/dts/ksi8560.dts @@ -56,6 +56,19 @@ ranges = <0x00000000 0xfdf00000 0x00100000>; bus-frequency = <0>; /* Fixed by bootwrapper */ + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8560-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8540-memory-controller"; reg = <0x2000 0x1000>; diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts index 57c595bf1071..436c9c671dd9 100644 --- a/arch/powerpc/boot/dts/mpc832x_mds.dts +++ b/arch/powerpc/boot/dts/mpc832x_mds.dts @@ -249,6 +249,8 @@ reg = <0xe0100000 0x480>; brg-frequency = <0>; bus-frequency = <198000000>; + fsl,qe-num-riscs = <1>; + fsl,qe-num-snums = <28>; muram@10000 { #address-cells = <1>; @@ -369,7 +371,6 @@ }; pci0: pci@e0008500 { - cell-index = <1>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x11 AD17 */ diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts index 4319bd70a580..9a0952f74b81 100644 --- a/arch/powerpc/boot/dts/mpc832x_rdb.dts +++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts @@ -221,6 +221,8 @@ reg = <0xe0100000 0x480>; brg-frequency = <0>; bus-frequency = <198000000>; + fsl,qe-num-riscs = <1>; + fsl,qe-num-snums = <28>; muram@10000 { #address-cells = <1>; @@ -327,7 +329,6 @@ }; pci0: pci@e0008500 { - cell-index = <1>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x10 AD16 (USB) */ diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts index 1ae38f0ddef8..e3eeaeda9187 100644 --- a/arch/powerpc/boot/dts/mpc8349emitx.dts +++ b/arch/powerpc/boot/dts/mpc8349emitx.dts @@ -278,7 +278,6 @@ }; pci0: pci@e0008500 { - cell-index = <1>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x10 - SATA */ @@ -301,7 +300,6 @@ }; pci1: pci@e0008600 { - cell-index = <2>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x0E - MiniPCI Slot */ diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts index 662abe1fb804..eb732115f016 100644 --- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts +++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts @@ -227,7 +227,6 @@ }; pci0: pci@e0008600 { - cell-index = <2>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x0F - PCI Slot */ diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts index d9f0a2325fa4..a2553a6f9009 100644 --- a/arch/powerpc/boot/dts/mpc834x_mds.dts +++ b/arch/powerpc/boot/dts/mpc834x_mds.dts @@ -286,7 +286,6 @@ }; pci0: pci@e0008500 { - cell-index = <1>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < @@ -348,7 +347,6 @@ }; pci1: pci@e0008600 { - cell-index = <2>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts index 6e34f170fa62..39ff4c829caf 100644 --- a/arch/powerpc/boot/dts/mpc836x_mds.dts +++ b/arch/powerpc/boot/dts/mpc836x_mds.dts @@ -289,6 +289,8 @@ reg = <0xe0100000 0x480>; brg-frequency = <0>; bus-frequency = <396000000>; + fsl,qe-num-riscs = <2>; + fsl,qe-num-snums = <28>; muram@10000 { #address-cells = <1>; @@ -410,7 +412,6 @@ }; pci0: pci@e0008500 { - cell-index = <1>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts b/arch/powerpc/boot/dts/mpc836x_rdk.dts index 37b789510d68..6315d6fcc58a 100644 --- a/arch/powerpc/boot/dts/mpc836x_rdk.dts +++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts @@ -198,6 +198,8 @@ clock-frequency = <0>; bus-frequency = <0>; brg-frequency = <0>; + fsl,qe-num-riscs = <2>; + fsl,qe-num-snums = <28>; muram@10000 { #address-cells = <1>; diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts index 963708017e6c..67bb372c9451 100644 --- a/arch/powerpc/boot/dts/mpc8377_mds.dts +++ b/arch/powerpc/boot/dts/mpc8377_mds.dts @@ -383,7 +383,6 @@ }; pci0: pci@e0008500 { - cell-index = <0>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts index 651ff2f9db2d..a955a577db81 100644 --- a/arch/powerpc/boot/dts/mpc8378_mds.dts +++ b/arch/powerpc/boot/dts/mpc8378_mds.dts @@ -367,7 +367,6 @@ }; pci0: pci@e0008500 { - cell-index = <0>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts index d6f208b8297a..d266ddbfc28d 100644 --- a/arch/powerpc/boot/dts/mpc8379_mds.dts +++ b/arch/powerpc/boot/dts/mpc8379_mds.dts @@ -397,7 +397,6 @@ }; pci0: pci@e0008500 { - cell-index = <0>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts index b31c5041350b..e781ad2f1f8a 100644 --- a/arch/powerpc/boot/dts/mpc8536ds.dts +++ b/arch/powerpc/boot/dts/mpc8536ds.dts @@ -51,9 +51,21 @@ device_type = "soc"; compatible = "simple-bus"; ranges = <0x0 0xffe00000 0x100000>; - reg = <0xffe00000 0x1000>; bus-frequency = <0>; // Filled out by uboot. + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <12>; + }; + + ecm@1000 { + compatible = "fsl,mpc8536-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8536-memory-controller"; reg = <0x2000 0x1000>; @@ -321,7 +333,6 @@ }; pci0: pci@ffe08000 { - cell-index = <0>; compatible = "fsl,mpc8540-pci"; device_type = "pci"; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; @@ -346,7 +357,6 @@ }; pci1: pcie@ffe09000 { - cell-index = <1>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -383,7 +393,6 @@ }; pci2: pcie@ffe0a000 { - cell-index = <2>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -420,7 +429,6 @@ }; pci3: pcie@ffe0b000 { - cell-index = <3>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts index ddd67be10b03..9dc292962a9a 100644 --- a/arch/powerpc/boot/dts/mpc8540ads.dts +++ b/arch/powerpc/boot/dts/mpc8540ads.dts @@ -55,9 +55,21 @@ device_type = "soc"; compatible = "simple-bus"; ranges = <0x0 0xe0000000 0x100000>; - reg = <0xe0000000 0x100000>; // CCSRBAR 1M bus-frequency = <0>; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8540-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,8540-memory-controller"; reg = <0x2000 0x1000>; @@ -258,7 +270,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts index e45097f44fbd..9a3ad311aedf 100644 --- a/arch/powerpc/boot/dts/mpc8541cds.dts +++ b/arch/powerpc/boot/dts/mpc8541cds.dts @@ -55,9 +55,21 @@ device_type = "soc"; compatible = "simple-bus"; ranges = <0x0 0xe0000000 0x100000>; - reg = <0xe0000000 0x1000>; // CCSRBAR 1M bus-frequency = <0>; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8541-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,8541-memory-controller"; reg = <0x2000 0x1000>; @@ -272,7 +284,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; interrupt-map = < @@ -344,7 +355,6 @@ }; pci1: pci@e0009000 { - cell-index = <1>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts index 7c6932be0197..98e94b465662 100644 --- a/arch/powerpc/boot/dts/mpc8544ds.dts +++ b/arch/powerpc/boot/dts/mpc8544ds.dts @@ -57,9 +57,21 @@ compatible = "simple-bus"; ranges = <0x0 0xe0000000 0x100000>; - reg = <0xe0000000 0x1000>; // CCSRBAR 1M bus-frequency = <0>; // Filled out by uboot. + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + ecm@1000 { + compatible = "fsl,mpc8544-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,8544-memory-controller"; reg = <0x2000 0x1000>; @@ -274,7 +286,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; compatible = "fsl,mpc8540-pci"; device_type = "pci"; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; @@ -306,7 +317,6 @@ }; pci1: pcie@e0009000 { - cell-index = <1>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -343,7 +353,6 @@ }; pci2: pcie@e000a000 { - cell-index = <2>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -380,7 +389,6 @@ }; pci3: pcie@e000b000 { - cell-index = <3>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts index 804e90353293..475be1433fe1 100644 --- a/arch/powerpc/boot/dts/mpc8548cds.dts +++ b/arch/powerpc/boot/dts/mpc8548cds.dts @@ -60,9 +60,21 @@ device_type = "soc"; compatible = "simple-bus"; ranges = <0x0 0xe0000000 0x100000>; - reg = <0xe0000000 0x1000>; // CCSRBAR bus-frequency = <0>; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + ecm@1000 { + compatible = "fsl,mpc8548-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,8548-memory-controller"; reg = <0x2000 0x1000>; @@ -328,7 +340,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x4 (PCIX Slot 2) */ @@ -478,7 +489,6 @@ }; pci1: pci@e0009000 { - cell-index = <1>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < @@ -503,7 +513,6 @@ }; pci2: pcie@e000a000 { - cell-index = <2>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts index 9484f0729b10..065b2f093de2 100644 --- a/arch/powerpc/boot/dts/mpc8555cds.dts +++ b/arch/powerpc/boot/dts/mpc8555cds.dts @@ -55,9 +55,21 @@ device_type = "soc"; compatible = "simple-bus"; ranges = <0x0 0xe0000000 0x100000>; - reg = <0xe0000000 0x1000>; // CCSRBAR 1M bus-frequency = <0>; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8555-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,8555-memory-controller"; reg = <0x2000 0x1000>; @@ -272,7 +284,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; interrupt-map = < @@ -344,7 +355,6 @@ }; pci1: pci@e0009000 { - cell-index = <1>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts index cc2acf87d02f..a5bb1ec70a5a 100644 --- a/arch/powerpc/boot/dts/mpc8560ads.dts +++ b/arch/powerpc/boot/dts/mpc8560ads.dts @@ -55,9 +55,21 @@ device_type = "soc"; compatible = "simple-bus"; ranges = <0x0 0xe0000000 0x100000>; - reg = <0xe0000000 0x200>; bus-frequency = <330000000>; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8560-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,8540-memory-controller"; reg = <0x2000 0x1000>; @@ -291,7 +303,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts index 9d52e3b25047..00c2bbda7013 100644 --- a/arch/powerpc/boot/dts/mpc8568mds.dts +++ b/arch/powerpc/boot/dts/mpc8568mds.dts @@ -26,6 +26,7 @@ serial1 = &serial1; pci0 = &pci0; pci1 = &pci1; + rapidio0 = &rio0; }; cpus { @@ -62,9 +63,21 @@ device_type = "soc"; compatible = "simple-bus"; ranges = <0x0 0xe0000000 0x100000>; - reg = <0xe0000000 0x1000>; bus-frequency = <0>; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + ecm@1000 { + compatible = "fsl,mpc8568-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,8568-memory-controller"; reg = <0x2000 0x1000>; @@ -275,6 +288,22 @@ device_type = "open-pic"; }; + msi@41600 { + compatible = "fsl,mpc8568-msi", "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0 + 0xe4 0 + 0xe5 0 + 0xe6 0 + 0xe7 0>; + interrupt-parent = <&mpic>; + }; + par_io@e0100 { reg = <0xe0100 0x100>; device_type = "par_io"; @@ -349,6 +378,8 @@ reg = <0xe0080000 0x480>; brg-frequency = <0>; bus-frequency = <396000000>; + fsl,qe-num-riscs = <2>; + fsl,qe-num-snums = <28>; muram@10000 { #address-cells = <1>; @@ -459,7 +490,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x12 AD18 */ @@ -490,7 +520,6 @@ /* PCI Express */ pci1: pcie@e000a000 { - cell-index = <2>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < @@ -526,4 +555,20 @@ 0x0 0x800000>; }; }; + + rio0: rapidio@e00c00000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "fsl,mpc8568-rapidio", "fsl,rapidio-delta"; + reg = <0xe00c0000 0x20000>; + ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>; + interrupts = <48 2 /* error */ + 49 2 /* bell_outb */ + 50 2 /* bell_inb */ + 53 2 /* msg1_tx */ + 54 2 /* msg1_rx */ + 55 2 /* msg2_tx */ + 56 2 /* msg2_rx */>; + interrupt-parent = <&mpic>; + }; }; diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts new file mode 100644 index 000000000000..39c2927503cf --- /dev/null +++ b/arch/powerpc/boot/dts/mpc8569mds.dts @@ -0,0 +1,583 @@ +/* + * MPC8569E MDS Device Tree Source + * + * Copyright (C) 2009 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + model = "MPC8569EMDS"; + compatible = "fsl,MPC8569EMDS"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + ethernet3 = &enet3; + pci1 = &pci1; + rapidio0 = &rio0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8569@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + next-level-cache = <&L2>; + }; + }; + + memory { + device_type = "memory"; + }; + + localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus"; + reg = <0xe0005000 0x1000>; + interrupts = <19 2>; + interrupt-parent = <&mpic>; + + ranges = <0x0 0x0 0xfe000000 0x02000000 + 0x1 0x0 0xf8000000 0x00008000 + 0x2 0x0 0xf0000000 0x04000000 + 0x3 0x0 0xfc000000 0x00008000 + 0x4 0x0 0xf8008000 0x00008000 + 0x5 0x0 0xf8010000 0x00008000>; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x02000000>; + bank-width = <2>; + device-width = <1>; + }; + + bcsr@1,0 { + compatible = "fsl,mpc8569mds-bcsr"; + reg = <1 0 0x8000>; + }; + + nand@3,0 { + compatible = "fsl,mpc8569-fcm-nand", + "fsl,elbc-fcm-nand"; + reg = <3 0 0x8000>; + }; + + pib@4,0 { + compatible = "fsl,mpc8569mds-pib"; + reg = <4 0 0x8000>; + }; + + pib@5,0 { + compatible = "fsl,mpc8569mds-pib"; + reg = <5 0 0x8000>; + }; + }; + + soc@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,mpc8569-immr", "simple-bus"; + ranges = <0x0 0xe0000000 0x100000>; + bus-frequency = <0>; + + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + ecm@1000 { + compatible = "fsl,mpc8569-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + + memory-controller@2000 { + compatible = "fsl,mpc8569-memory-controller"; + reg = <0x2000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + + rtc@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; + }; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + L2: l2-cache-controller@20000 { + compatible = "fsl,mpc8569-l2-cache-controller"; + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x80000>; // L2, 512K + interrupt-parent = <&mpic>; + interrupts = <16 2>; + }; + + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8569-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8569-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8569-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8569-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + + sdhci@2e000 { + compatible = "fsl,mpc8569-esdhc", "fsl,esdhc"; + reg = <0x2e000 0x1000>; + interrupts = <72 0x8>; + interrupt-parent = <&mpic>; + /* Filled in by U-Boot */ + clock-frequency = <0>; + status = "disabled"; + }; + + crypto@30000 { + compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4", + "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <45 2 58 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0xbfe>; + fsl,descriptor-types-mask = <0x3ab0ebf>; + }; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + }; + + msi@41600 { + compatible = "fsl,mpc8568-msi", "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0 + 0xe4 0 + 0xe5 0 + 0xe6 0 + 0xe7 0>; + interrupt-parent = <&mpic>; + }; + + global-utilities@e0000 { + compatible = "fsl,mpc8569-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + + par_io@e0100 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xe0100 0x100>; + ranges = <0x0 0xe0100 0x100>; + device_type = "par_io"; + num-ports = <7>; + + qe_pio_e: gpio-controller@80 { + #gpio-cells = <2>; + compatible = "fsl,mpc8569-qe-pario-bank", + "fsl,mpc8323-qe-pario-bank"; + reg = <0x80 0x18>; + gpio-controller; + }; + + pio1: ucc_pin@01 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ + 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ + 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/ + 0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */ + 0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */ + 0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */ + 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */ + 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */ + 0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */ + 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */ + 0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */ + 0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */ + 0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */ + 0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */ + 0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */ + }; + + pio2: ucc_pin@02 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ + 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ + 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */ + 0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */ + 0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */ + 0x0 0x10 0x1 0x0 0x1 0x0 /* ENET2_TXD2_SER2_TXD2 */ + 0x0 0x11 0x1 0x0 0x1 0x0 /* ENET2_TXD3_SER2_TXD3 */ + 0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */ + 0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */ + 0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */ + 0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */ + 0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */ + 0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */ + 0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */ + 0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */ + }; + + pio3: ucc_pin@03 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ + 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ + 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/ + 0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */ + 0x0 0x1e 0x1 0x0 0x3 0x0 /* ENET3_TXD1_SER3_TXD1 */ + 0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */ + 0x1 0x0 0x1 0x0 0x3 0x0 /* ENET3_TXD3_SER3_TXD3 */ + 0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */ + 0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */ + 0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */ + 0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */ + 0x1 0x1 0x1 0x0 0x1 0x0 /* ENET3_TX_EN_SER3_RTS_B */ + 0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */ + 0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */ + 0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */ + }; + + pio4: ucc_pin@04 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ + 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ + 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */ + 0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */ + 0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */ + 0x1 0xe 0x1 0x0 0x1 0x0 /* ENET4_TXD2_SER4_TXD2 */ + 0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */ + 0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */ + 0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */ + 0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */ + 0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */ + 0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */ + 0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */ + 0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */ + 0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */ + }; + }; + }; + + qe@e0080000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "qe"; + compatible = "fsl,qe"; + ranges = <0x0 0xe0080000 0x40000>; + reg = <0xe0080000 0x480>; + brg-frequency = <0>; + bus-frequency = <0>; + fsl,qe-num-riscs = <4>; + fsl,qe-num-snums = <46>; + + qeic: interrupt-controller@80 { + interrupt-controller; + compatible = "fsl,qe-ic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x80 0x80>; + interrupts = <46 2 46 2>; //high:30 low:30 + interrupt-parent = <&mpic>; + }; + + spi@4c0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mpc8569-qe-spi", "fsl,spi"; + reg = <0x4c0 0x40>; + cell-index = <0>; + interrupts = <2>; + interrupt-parent = <&qeic>; + gpios = <&qe_pio_e 30 0>; + mode = "cpu-qe"; + + serial-flash@0 { + compatible = "stm,m25p40"; + reg = <0>; + spi-max-frequency = <25000000>; + }; + }; + + spi@500 { + cell-index = <1>; + compatible = "fsl,spi"; + reg = <0x500 0x40>; + interrupts = <1>; + interrupt-parent = <&qeic>; + mode = "cpu"; + }; + + enet0: ucc@2000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk12"; + pio-handle = <&pio1>; + phy-handle = <&qe_phy0>; + phy-connection-type = "rgmii-id"; + }; + + mdio@2120 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2120 0x18>; + compatible = "fsl,ucc-mdio"; + + qe_phy0: ethernet-phy@07 { + interrupt-parent = <&mpic>; + interrupts = <1 1>; + reg = <0x7>; + device_type = "ethernet-phy"; + }; + qe_phy1: ethernet-phy@01 { + interrupt-parent = <&mpic>; + interrupts = <2 1>; + reg = <0x1>; + device_type = "ethernet-phy"; + }; + qe_phy2: ethernet-phy@02 { + interrupt-parent = <&mpic>; + interrupts = <3 1>; + reg = <0x2>; + device_type = "ethernet-phy"; + }; + qe_phy3: ethernet-phy@03 { + interrupt-parent = <&mpic>; + interrupts = <4 1>; + reg = <0x3>; + device_type = "ethernet-phy"; + }; + }; + + enet2: ucc@2200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <3>; + reg = <0x2200 0x200>; + interrupts = <34>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk12"; + pio-handle = <&pio3>; + phy-handle = <&qe_phy2>; + phy-connection-type = "rgmii-id"; + }; + + enet1: ucc@3000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <2>; + reg = <0x3000 0x200>; + interrupts = <33>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk17"; + pio-handle = <&pio2>; + phy-handle = <&qe_phy1>; + phy-connection-type = "rgmii-id"; + }; + + enet3: ucc@3200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <4>; + reg = <0x3200 0x200>; + interrupts = <35>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk17"; + pio-handle = <&pio4>; + phy-handle = <&qe_phy3>; + phy-connection-type = "rgmii-id"; + }; + + muram@10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0x0 0x10000 0x20000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0x0 0x20000>; + }; + }; + + }; + + /* PCI Express */ + pci1: pcie@e000a000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0xe000a000 0x1000>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 0x0 (PEX) */ + 00000 0x0 0x0 0x1 &mpic 0x0 0x1 + 00000 0x0 0x0 0x2 &mpic 0x1 0x1 + 00000 0x0 0x0 0x3 &mpic 0x2 0x1 + 00000 0x0 0x0 0x4 &mpic 0x3 0x1>; + + interrupt-parent = <&mpic>; + interrupts = <26 2>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 + 0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>; + clock-frequency = <33333333>; + pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x2000000 0x0 0xa0000000 + 0x2000000 0x0 0xa0000000 + 0x0 0x10000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x800000>; + }; + }; + + rio0: rapidio@e00c00000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "fsl,mpc8569-rapidio", "fsl,rapidio-delta"; + reg = <0xe00c0000 0x20000>; + ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>; + interrupts = <48 2 /* error */ + 49 2 /* bell_outb */ + 50 2 /* bell_inb */ + 53 2 /* msg1_tx */ + 54 2 /* msg1_rx */ + 55 2 /* msg2_tx */ + 56 2 /* msg2_rx */>; + interrupt-parent = <&mpic>; + }; +}; diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts index 6e79a4169088..cafc1285c140 100644 --- a/arch/powerpc/boot/dts/mpc8572ds.dts +++ b/arch/powerpc/boot/dts/mpc8572ds.dts @@ -182,9 +182,21 @@ device_type = "soc"; compatible = "simple-bus"; ranges = <0x0 0 0xffe00000 0x100000>; - reg = <0 0xffe00000 0 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed bus-frequency = <0>; // Filled out by uboot. + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <12>; + }; + + ecm@1000 { + compatible = "fsl,mpc8572-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8572-memory-controller"; reg = <0x2000 0x1000>; @@ -514,7 +526,6 @@ }; pci0: pcie@ffe08000 { - cell-index = <0>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -724,7 +735,6 @@ }; pci1: pcie@ffe09000 { - cell-index = <1>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -761,7 +771,6 @@ }; pci2: pcie@ffe0a000 { - cell-index = <2>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; diff --git a/arch/powerpc/boot/dts/mpc8572ds_36b.dts b/arch/powerpc/boot/dts/mpc8572ds_36b.dts index dbd81a764742..f6365db3b97d 100644 --- a/arch/powerpc/boot/dts/mpc8572ds_36b.dts +++ b/arch/powerpc/boot/dts/mpc8572ds_36b.dts @@ -182,9 +182,21 @@ device_type = "soc"; compatible = "simple-bus"; ranges = <0x0 0xf 0xffe00000 0x100000>; - reg = <0xf 0xffe00000 0 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed bus-frequency = <0>; // Filled out by uboot. + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <12>; + }; + + ecm@1000 { + compatible = "fsl,mpc8572-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8572-memory-controller"; reg = <0x2000 0x1000>; @@ -514,7 +526,6 @@ }; pci0: pcie@fffe08000 { - cell-index = <0>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -522,7 +533,7 @@ #address-cells = <3>; reg = <0xf 0xffe08000 0 0x1000>; bus-range = <0 255>; - ranges = <0x2000000 0x0 0xc0000000 0xc 0x00000000 0x0 0x20000000 + ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>; clock-frequency = <33333333>; interrupt-parent = <&mpic>; @@ -649,8 +660,8 @@ #size-cells = <2>; #address-cells = <3>; device_type = "pci"; - ranges = <0x2000000 0x0 0xc0000000 - 0x2000000 0x0 0xc0000000 + ranges = <0x2000000 0x0 0xe0000000 + 0x2000000 0x0 0xe0000000 0x0 0x20000000 0x1000000 0x0 0x0 @@ -660,8 +671,8 @@ reg = <0x0 0x0 0x0 0x0 0x0>; #size-cells = <2>; #address-cells = <3>; - ranges = <0x2000000 0x0 0xc0000000 - 0x2000000 0x0 0xc0000000 + ranges = <0x2000000 0x0 0xe0000000 + 0x2000000 0x0 0xe0000000 0x0 0x20000000 0x1000000 0x0 0x0 @@ -724,7 +735,6 @@ }; pci1: pcie@fffe09000 { - cell-index = <1>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -732,7 +742,7 @@ #address-cells = <3>; reg = <0xf 0xffe09000 0 0x1000>; bus-range = <0 255>; - ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000 + ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>; clock-frequency = <33333333>; interrupt-parent = <&mpic>; @@ -750,8 +760,8 @@ #size-cells = <2>; #address-cells = <3>; device_type = "pci"; - ranges = <0x2000000 0x0 0xc0000000 - 0x2000000 0x0 0xc0000000 + ranges = <0x2000000 0x0 0xe0000000 + 0x2000000 0x0 0xe0000000 0x0 0x20000000 0x1000000 0x0 0x0 @@ -761,7 +771,6 @@ }; pci2: pcie@fffe0a000 { - cell-index = <2>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -769,7 +778,7 @@ #address-cells = <3>; reg = <0xf 0xffe0a000 0 0x1000>; bus-range = <0 255>; - ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000 + ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>; clock-frequency = <33333333>; interrupt-parent = <&mpic>; @@ -787,8 +796,8 @@ #size-cells = <2>; #address-cells = <3>; device_type = "pci"; - ranges = <0x2000000 0x0 0xc0000000 - 0x2000000 0x0 0xc0000000 + ranges = <0x2000000 0x0 0xe0000000 + 0x2000000 0x0 0xe0000000 0x0 0x20000000 0x1000000 0x0 0x0 diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts index 2bc0c7189653..5bd1011fde96 100644 --- a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts +++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts @@ -59,9 +59,21 @@ device_type = "soc"; compatible = "simple-bus"; ranges = <0x0 0xffe00000 0x100000>; - reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed bus-frequency = <0>; // Filled out by uboot. + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <12>; + }; + + ecm@1000 { + compatible = "fsl,mpc8572-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8572-memory-controller"; reg = <0x2000 0x1000>; @@ -238,7 +250,6 @@ }; pci0: pcie@ffe08000 { - cell-index = <0>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -448,7 +459,6 @@ }; pci1: pcie@ffe09000 { - cell-index = <1>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts index 159cb3a875f0..0efc3456e297 100644 --- a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts +++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts @@ -58,7 +58,6 @@ device_type = "soc"; compatible = "simple-bus"; ranges = <0x0 0xffe00000 0x100000>; - reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed bus-frequency = <0>; // Filled out by uboot. L2: l2-cache-controller@20000 { @@ -196,7 +195,6 @@ }; pci2: pcie@ffe0a000 { - cell-index = <2>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts index 1bd3ebe11437..cfc2c60d1f5f 100644 --- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts +++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts @@ -112,9 +112,21 @@ device_type = "soc"; compatible = "fsl,mpc8610-immr", "simple-bus"; ranges = <0x0 0xe0000000 0x00100000>; - reg = <0xe0000000 0x1000>; bus-frequency = <0>; + mcm-law@0 { + compatible = "fsl,mcm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + mcm@1000 { + compatible = "fsl,mpc8610-mcm", "fsl,mcm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + i2c@3000 { #address-cells = <1>; #size-cells = <0>; @@ -316,7 +328,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; compatible = "fsl,mpc8610-pci"; device_type = "pci"; #interrupt-cells = <1>; @@ -346,7 +357,6 @@ }; pci1: pcie@e000a000 { - cell-index = <1>; compatible = "fsl,mpc8641-pcie"; device_type = "pci"; #interrupt-cells = <1>; diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts index d72beb192460..848320e4d3c4 100644 --- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts +++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts @@ -114,9 +114,21 @@ device_type = "soc"; compatible = "simple-bus"; ranges = <0x00000000 0xffe00000 0x00100000>; - reg = <0xffe00000 0x00001000>; // CCSRBAR bus-frequency = <0>; + mcm-law@0 { + compatible = "fsl,mcm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + mcm@1000 { + compatible = "fsl,mpc8641-mcm", "fsl,mcm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + i2c@3000 { #address-cells = <1>; #size-cells = <0>; @@ -357,7 +369,6 @@ }; pci0: pcie@ffe08000 { - cell-index = <0>; compatible = "fsl,mpc8641-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -566,7 +577,6 @@ }; pci1: pcie@ffe09000 { - cell-index = <1>; compatible = "fsl,mpc8641-pcie"; device_type = "pci"; #interrupt-cells = <1>; diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts b/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts new file mode 100644 index 000000000000..8be8e701e1d3 --- /dev/null +++ b/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts @@ -0,0 +1,609 @@ +/* + * MPC8641 HPCN Device Tree Source + * + * Copyright 2008-2009 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + model = "MPC8641HPCN"; + compatible = "fsl,mpc8641hpcn"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + ethernet3 = &enet3; + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + pci1 = &pci1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8641@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <32768>; // L1, 32K + i-cache-size = <32768>; // L1, 32K + timebase-frequency = <0>; // 33 MHz, from uboot + bus-frequency = <0>; // From uboot + clock-frequency = <0>; // From uboot + }; + PowerPC,8641@1 { + device_type = "cpu"; + reg = <1>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <32768>; // L1, 32K + i-cache-size = <32768>; // L1, 32K + timebase-frequency = <0>; // 33 MHz, from uboot + bus-frequency = <0>; // From uboot + clock-frequency = <0>; // From uboot + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0 + }; + + localbus@fffe05000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8641-localbus", "simple-bus"; + reg = <0x0f 0xffe05000 0x0 0x1000>; + interrupts = <19 2>; + interrupt-parent = <&mpic>; + + ranges = <0 0 0xf 0xef800000 0x00800000 + 2 0 0xf 0xffdf8000 0x00008000 + 3 0 0xf 0xffdf0000 0x00008000>; + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x00800000>; + bank-width = <2>; + device-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "kernel"; + reg = <0x00000000 0x00300000>; + }; + partition@300000 { + label = "firmware b"; + reg = <0x00300000 0x00100000>; + read-only; + }; + partition@400000 { + label = "fs"; + reg = <0x00400000 0x00300000>; + }; + partition@700000 { + label = "firmware a"; + reg = <0x00700000 0x00100000>; + read-only; + }; + }; + }; + + soc8641@fffe00000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + ranges = <0x00000000 0x0f 0xffe00000 0x00100000>; + bus-frequency = <0>; + + mcm-law@0 { + compatible = "fsl,mcm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + mcm@1000 { + compatible = "fsl,mpc8641-mcm", "fsl,mcm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + + enet0: ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + ranges = <0x0 0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2 30 2 34 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi0>; + phy-handle = <&phy0>; + phy-connection-type = "rgmii-id"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x520 0x20>; + + phy0: ethernet-phy@0 { + interrupt-parent = <&mpic>; + interrupts = <10 1>; + reg = <0>; + device_type = "ethernet-phy"; + }; + phy1: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <10 1>; + reg = <1>; + device_type = "ethernet-phy"; + }; + phy2: ethernet-phy@2 { + interrupt-parent = <&mpic>; + interrupts = <10 1>; + reg = <2>; + device_type = "ethernet-phy"; + }; + phy3: ethernet-phy@3 { + interrupt-parent = <&mpic>; + interrupts = <10 1>; + reg = <3>; + device_type = "ethernet-phy"; + }; + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + enet1: ethernet@25000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <1>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + ranges = <0x0 0x25000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 2 36 2 40 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi1>; + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + enet2: ethernet@26000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <2>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x26000 0x1000>; + ranges = <0x0 0x26000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <31 2 32 2 33 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi2>; + phy-handle = <&phy2>; + phy-connection-type = "rgmii-id"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi2: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + enet3: ethernet@27000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <3>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x27000 0x1000>; + ranges = <0x0 0x27000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <37 2 38 2 39 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi3>; + phy-handle = <&phy3>; + phy-connection-type = "rgmii-id"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi3: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <28 2>; + interrupt-parent = <&mpic>; + }; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + }; + + global-utilities@e0000 { + compatible = "fsl,mpc8641-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + }; + + pci0: pcie@fffe08000 { + cell-index = <0>; + compatible = "fsl,mpc8641-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x0f 0xffe08000 0x0 0x1000>; + bus-range = <0x0 0xff>; + ranges = <0x02000000 0x0 0xe0000000 0x0c 0x00000000 0x0 0x20000000 + 0x01000000 0x0 0x00000000 0x0f 0xffc00000 0x0 0x00010000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <24 2>; + interrupt-map-mask = <0xff00 0 0 7>; + interrupt-map = < + /* IDSEL 0x11 func 0 - PCI slot 1 */ + 0x8800 0 0 1 &mpic 2 1 + 0x8800 0 0 2 &mpic 3 1 + 0x8800 0 0 3 &mpic 4 1 + 0x8800 0 0 4 &mpic 1 1 + + /* IDSEL 0x11 func 1 - PCI slot 1 */ + 0x8900 0 0 1 &mpic 2 1 + 0x8900 0 0 2 &mpic 3 1 + 0x8900 0 0 3 &mpic 4 1 + 0x8900 0 0 4 &mpic 1 1 + + /* IDSEL 0x11 func 2 - PCI slot 1 */ + 0x8a00 0 0 1 &mpic 2 1 + 0x8a00 0 0 2 &mpic 3 1 + 0x8a00 0 0 3 &mpic 4 1 + 0x8a00 0 0 4 &mpic 1 1 + + /* IDSEL 0x11 func 3 - PCI slot 1 */ + 0x8b00 0 0 1 &mpic 2 1 + 0x8b00 0 0 2 &mpic 3 1 + 0x8b00 0 0 3 &mpic 4 1 + 0x8b00 0 0 4 &mpic 1 1 + + /* IDSEL 0x11 func 4 - PCI slot 1 */ + 0x8c00 0 0 1 &mpic 2 1 + 0x8c00 0 0 2 &mpic 3 1 + 0x8c00 0 0 3 &mpic 4 1 + 0x8c00 0 0 4 &mpic 1 1 + + /* IDSEL 0x11 func 5 - PCI slot 1 */ + 0x8d00 0 0 1 &mpic 2 1 + 0x8d00 0 0 2 &mpic 3 1 + 0x8d00 0 0 3 &mpic 4 1 + 0x8d00 0 0 4 &mpic 1 1 + + /* IDSEL 0x11 func 6 - PCI slot 1 */ + 0x8e00 0 0 1 &mpic 2 1 + 0x8e00 0 0 2 &mpic 3 1 + 0x8e00 0 0 3 &mpic 4 1 + 0x8e00 0 0 4 &mpic 1 1 + + /* IDSEL 0x11 func 7 - PCI slot 1 */ + 0x8f00 0 0 1 &mpic 2 1 + 0x8f00 0 0 2 &mpic 3 1 + 0x8f00 0 0 3 &mpic 4 1 + 0x8f00 0 0 4 &mpic 1 1 + + /* IDSEL 0x12 func 0 - PCI slot 2 */ + 0x9000 0 0 1 &mpic 3 1 + 0x9000 0 0 2 &mpic 4 1 + 0x9000 0 0 3 &mpic 1 1 + 0x9000 0 0 4 &mpic 2 1 + + /* IDSEL 0x12 func 1 - PCI slot 2 */ + 0x9100 0 0 1 &mpic 3 1 + 0x9100 0 0 2 &mpic 4 1 + 0x9100 0 0 3 &mpic 1 1 + 0x9100 0 0 4 &mpic 2 1 + + /* IDSEL 0x12 func 2 - PCI slot 2 */ + 0x9200 0 0 1 &mpic 3 1 + 0x9200 0 0 2 &mpic 4 1 + 0x9200 0 0 3 &mpic 1 1 + 0x9200 0 0 4 &mpic 2 1 + + /* IDSEL 0x12 func 3 - PCI slot 2 */ + 0x9300 0 0 1 &mpic 3 1 + 0x9300 0 0 2 &mpic 4 1 + 0x9300 0 0 3 &mpic 1 1 + 0x9300 0 0 4 &mpic 2 1 + + /* IDSEL 0x12 func 4 - PCI slot 2 */ + 0x9400 0 0 1 &mpic 3 1 + 0x9400 0 0 2 &mpic 4 1 + 0x9400 0 0 3 &mpic 1 1 + 0x9400 0 0 4 &mpic 2 1 + + /* IDSEL 0x12 func 5 - PCI slot 2 */ + 0x9500 0 0 1 &mpic 3 1 + 0x9500 0 0 2 &mpic 4 1 + 0x9500 0 0 3 &mpic 1 1 + 0x9500 0 0 4 &mpic 2 1 + + /* IDSEL 0x12 func 6 - PCI slot 2 */ + 0x9600 0 0 1 &mpic 3 1 + 0x9600 0 0 2 &mpic 4 1 + 0x9600 0 0 3 &mpic 1 1 + 0x9600 0 0 4 &mpic 2 1 + + /* IDSEL 0x12 func 7 - PCI slot 2 */ + 0x9700 0 0 1 &mpic 3 1 + 0x9700 0 0 2 &mpic 4 1 + 0x9700 0 0 3 &mpic 1 1 + 0x9700 0 0 4 &mpic 2 1 + + // IDSEL 0x1c USB + 0xe000 0 0 1 &i8259 12 2 + 0xe100 0 0 2 &i8259 9 2 + 0xe200 0 0 3 &i8259 10 2 + 0xe300 0 0 4 &i8259 11 2 + + // IDSEL 0x1d Audio + 0xe800 0 0 1 &i8259 6 2 + + // IDSEL 0x1e Legacy + 0xf000 0 0 1 &i8259 7 2 + 0xf100 0 0 1 &i8259 7 2 + + // IDSEL 0x1f IDE/SATA + 0xf800 0 0 1 &i8259 14 2 + 0xf900 0 0 1 &i8259 5 2 + >; + + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x02000000 0x0 0xe0000000 + 0x02000000 0x0 0xe0000000 + 0x0 0x20000000 + + 0x01000000 0x0 0x00000000 + 0x01000000 0x0 0x00000000 + 0x0 0x00010000>; + uli1575@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + ranges = <0x02000000 0x0 0xe0000000 + 0x02000000 0x0 0xe0000000 + 0x0 0x20000000 + 0x01000000 0x0 0x00000000 + 0x01000000 0x0 0x00000000 + 0x0 0x00010000>; + isa@1e { + device_type = "isa"; + #interrupt-cells = <2>; + #size-cells = <1>; + #address-cells = <2>; + reg = <0xf000 0 0 0 0>; + ranges = <1 0 0x01000000 0 0 + 0x00001000>; + interrupt-parent = <&i8259>; + + i8259: interrupt-controller@20 { + reg = <1 0x20 2 + 1 0xa0 2 + 1 0x4d0 2>; + interrupt-controller; + device_type = "interrupt-controller"; + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "chrp,iic"; + interrupts = <9 2>; + interrupt-parent = <&mpic>; + }; + + i8042@60 { + #size-cells = <0>; + #address-cells = <1>; + reg = <1 0x60 1 1 0x64 1>; + interrupts = <1 3 12 3>; + interrupt-parent = + <&i8259>; + + keyboard@0 { + reg = <0>; + compatible = "pnpPNP,303"; + }; + + mouse@1 { + reg = <1>; + compatible = "pnpPNP,f03"; + }; + }; + + rtc@70 { + compatible = + "pnpPNP,b00"; + reg = <1 0x70 2>; + }; + + gpio@400 { + reg = <1 0x400 0x80>; + }; + }; + }; + }; + + }; + + pci1: pcie@fffe09000 { + cell-index = <1>; + compatible = "fsl,mpc8641-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x0f 0xffe09000 0x0 0x1000>; + bus-range = <0x0 0xff>; + ranges = <0x02000000 0x0 0xe0000000 0x0c 0x20000000 0x0 0x20000000 + 0x01000000 0x0 0x00000000 0x0f 0xffc10000 0x0 0x00010000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <25 2>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0x0000 0 0 1 &mpic 4 1 + 0x0000 0 0 2 &mpic 5 1 + 0x0000 0 0 3 &mpic 6 1 + 0x0000 0 0 4 &mpic 7 1 + >; + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x02000000 0x0 0xe0000000 + 0x02000000 0x0 0xe0000000 + 0x0 0x20000000 + + 0x01000000 0x0 0x00000000 + 0x01000000 0x0 0x00000000 + 0x0 0x00010000>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts new file mode 100644 index 000000000000..11019142813c --- /dev/null +++ b/arch/powerpc/boot/dts/p2020ds.dts @@ -0,0 +1,704 @@ +/* + * P2020 DS Device Tree Source + * + * Copyright 2009 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; +/ { + model = "fsl,P2020"; + compatible = "fsl,P2020DS"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + pci1 = &pci1; + pci2 = &pci2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,P2020@0 { + device_type = "cpu"; + reg = <0x0>; + next-level-cache = <&L2>; + }; + + PowerPC,P2020@1 { + device_type = "cpu"; + reg = <0x1>; + next-level-cache = <&L2>; + }; + }; + + memory { + device_type = "memory"; + }; + + localbus@ffe05000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,elbc", "simple-bus"; + reg = <0 0xffe05000 0 0x1000>; + interrupts = <19 2>; + interrupt-parent = <&mpic>; + + ranges = <0x0 0x0 0x0 0xe8000000 0x08000000 + 0x1 0x0 0x0 0xe0000000 0x08000000 + 0x2 0x0 0x0 0xffa00000 0x00040000 + 0x3 0x0 0x0 0xffdf0000 0x00008000 + 0x4 0x0 0x0 0xffa40000 0x00040000 + 0x5 0x0 0x0 0xffa80000 0x00040000 + 0x6 0x0 0x0 0xffac0000 0x00040000>; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + + ramdisk@0 { + reg = <0x0 0x03000000>; + read-only; + }; + + diagnostic@3000000 { + reg = <0x03000000 0x00e00000>; + read-only; + }; + + dink@3e00000 { + reg = <0x03e00000 0x00200000>; + read-only; + }; + + kernel@4000000 { + reg = <0x04000000 0x00400000>; + read-only; + }; + + jffs2@4400000 { + reg = <0x04400000 0x03b00000>; + }; + + dtb@7f00000 { + reg = <0x07f00000 0x00080000>; + read-only; + }; + + u-boot@7f80000 { + reg = <0x07f80000 0x00080000>; + read-only; + }; + }; + + nand@2,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,elbc-fcm-nand"; + reg = <0x2 0x0 0x40000>; + + u-boot@0 { + reg = <0x0 0x02000000>; + read-only; + }; + + jffs2@2000000 { + reg = <0x02000000 0x10000000>; + }; + + ramdisk@12000000 { + reg = <0x12000000 0x08000000>; + read-only; + }; + + kernel@1a000000 { + reg = <0x1a000000 0x04000000>; + }; + + dtb@1e000000 { + reg = <0x1e000000 0x01000000>; + read-only; + }; + + empty@1f000000 { + reg = <0x1f000000 0x21000000>; + }; + }; + + nand@4,0 { + compatible = "fsl,elbc-fcm-nand"; + reg = <0x4 0x0 0x40000>; + }; + + nand@5,0 { + compatible = "fsl,elbc-fcm-nand"; + reg = <0x5 0x0 0x40000>; + }; + + nand@6,0 { + compatible = "fsl,elbc-fcm-nand"; + reg = <0x6 0x0 0x40000>; + }; + }; + + soc@ffe00000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,p2020-immr", "simple-bus"; + ranges = <0x0 0 0xffe00000 0x100000>; + bus-frequency = <0>; // Filled out by uboot. + + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <12>; + }; + + ecm@1000 { + compatible = "fsl,p2020-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + + memory-controller@2000 { + compatible = "fsl,p2020-memory-controller"; + reg = <0x2000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + spi@7000 { + compatible = "fsl,espi"; + reg = <0x7000 0x1000>; + interrupts = <59 0x2>; + interrupt-parent = <&mpic>; + }; + + dma@c300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,eloplus-dma"; + reg = <0xc300 0x4>; + ranges = <0x0 0xc100 0x200>; + cell-index = <1>; + dma-channel@0 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <76 2>; + }; + dma-channel@80 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <77 2>; + }; + dma-channel@100 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <78 2>; + }; + dma-channel@180 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <79 2>; + }; + }; + + gpio: gpio-controller@f000 { + #gpio-cells = <2>; + compatible = "fsl,mpc8572-gpio"; + reg = <0xf000 0x100>; + interrupts = <47 0x2>; + interrupt-parent = <&mpic>; + gpio-controller; + }; + + L2: l2-cache-controller@20000 { + compatible = "fsl,p2020-l2-cache-controller"; + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x80000>; // L2, 512k + interrupt-parent = <&mpic>; + interrupts = <16 2>; + }; + + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + + usb@22000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl-usb2-dr"; + reg = <0x22000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <28 0x2>; + phy_type = "ulpi"; + }; + + enet0: ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + ranges = <0x0 0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2 30 2 34 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi0>; + phy-handle = <&phy0>; + phy-connection-type = "rgmii-id"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x520 0x20>; + + phy0: ethernet-phy@0 { + interrupt-parent = <&mpic>; + interrupts = <3 1>; + reg = <0x0>; + }; + phy1: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <3 1>; + reg = <0x1>; + }; + phy2: ethernet-phy@2 { + interrupt-parent = <&mpic>; + interrupts = <3 1>; + reg = <0x2>; + }; + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + enet1: ethernet@25000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + ranges = <0x0 0x25000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 2 36 2 40 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi1>; + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + enet2: ethernet@26000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <2>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x26000 0x1000>; + ranges = <0x0 0x26000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <31 2 32 2 33 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi2>; + phy-handle = <&phy2>; + phy-connection-type = "rgmii-id"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi2: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + sdhci@2e000 { + compatible = "fsl,p2020-esdhc", "fsl,esdhc"; + reg = <0x2e000 0x1000>; + interrupts = <72 0x2>; + interrupt-parent = <&mpic>; + /* Filled in by U-Boot */ + clock-frequency = <0>; + }; + + crypto@30000 { + compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4", + "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <45 2 58 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0xbfe>; + fsl,descriptor-types-mask = <0x3ab0ebf>; + }; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + }; + + msi@41600 { + compatible = "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0 + 0xe4 0 + 0xe5 0 + 0xe6 0 + 0xe7 0>; + interrupt-parent = <&mpic>; + }; + + global-utilities@e0000 { //global utilities block + compatible = "fsl,p2020-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + }; + + pci0: pcie@ffe08000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0 0xffe08000 0 0x1000>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <24 2>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0x0 0x0 0x1 &mpic 0x8 0x1 + 0000 0x0 0x0 0x2 &mpic 0x9 0x1 + 0000 0x0 0x0 0x3 &mpic 0xa 0x1 + 0000 0x0 0x0 0x4 &mpic 0xb 0x1 + >; + pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x2000000 0x0 0x80000000 + 0x2000000 0x0 0x80000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x10000>; + }; + }; + + pci1: pcie@ffe09000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0 0xffe09000 0 0x1000>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <25 2>; + interrupt-map-mask = <0xff00 0x0 0x0 0x7>; + interrupt-map = < + + // IDSEL 0x11 func 0 - PCI slot 1 + 0x8800 0x0 0x0 0x1 &i8259 0x9 0x2 + 0x8800 0x0 0x0 0x2 &i8259 0xa 0x2 + + // IDSEL 0x11 func 1 - PCI slot 1 + 0x8900 0x0 0x0 0x1 &i8259 0x9 0x2 + 0x8900 0x0 0x0 0x2 &i8259 0xa 0x2 + + // IDSEL 0x11 func 2 - PCI slot 1 + 0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2 + 0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2 + + // IDSEL 0x11 func 3 - PCI slot 1 + 0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2 + 0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2 + + // IDSEL 0x11 func 4 - PCI slot 1 + 0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2 + 0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2 + + // IDSEL 0x11 func 5 - PCI slot 1 + 0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2 + 0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2 + + // IDSEL 0x11 func 6 - PCI slot 1 + 0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2 + 0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2 + + // IDSEL 0x11 func 7 - PCI slot 1 + 0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2 + 0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2 + + // IDSEL 0x1d Audio + 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2 + + // IDSEL 0x1e Legacy + 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2 + 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2 + + // IDSEL 0x1f IDE/SATA + 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2 + 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2 + >; + + pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x2000000 0x0 0xa0000000 + 0x2000000 0x0 0xa0000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x10000>; + uli1575@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #size-cells = <2>; + #address-cells = <3>; + ranges = <0x2000000 0x0 0xa0000000 + 0x2000000 0x0 0xa0000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x10000>; + isa@1e { + device_type = "isa"; + #interrupt-cells = <2>; + #size-cells = <1>; + #address-cells = <2>; + reg = <0xf000 0x0 0x0 0x0 0x0>; + ranges = <0x1 0x0 0x1000000 0x0 0x0 + 0x1000>; + interrupt-parent = <&i8259>; + + i8259: interrupt-controller@20 { + reg = <0x1 0x20 0x2 + 0x1 0xa0 0x2 + 0x1 0x4d0 0x2>; + interrupt-controller; + device_type = "interrupt-controller"; + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "chrp,iic"; + interrupts = <4 1>; + interrupt-parent = <&mpic>; + }; + + i8042@60 { + #size-cells = <0>; + #address-cells = <1>; + reg = <0x1 0x60 0x1 0x1 0x64 0x1>; + interrupts = <1 3 12 3>; + interrupt-parent = + <&i8259>; + + keyboard@0 { + reg = <0x0>; + compatible = "pnpPNP,303"; + }; + + mouse@1 { + reg = <0x1>; + compatible = "pnpPNP,f03"; + }; + }; + + rtc@70 { + compatible = "pnpPNP,b00"; + reg = <0x1 0x70 0x2>; + }; + + gpio@400 { + reg = <0x1 0x400 0x80>; + }; + }; + }; + }; + + }; + + pci2: pcie@ffe0a000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0 0xffe0a000 0 0x1000>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <26 2>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0x0 0x0 0x1 &mpic 0x0 0x1 + 0000 0x0 0x0 0x2 &mpic 0x1 0x1 + 0000 0x0 0x0 0x3 &mpic 0x2 0x1 + 0000 0x0 0x0 0x4 &mpic 0x3 0x1 + >; + pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x2000000 0x0 0xc0000000 + 0x2000000 0x0 0xc0000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x10000>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts index a36dbbc48694..5fb6f6684b0e 100644 --- a/arch/powerpc/boot/dts/sbc8349.dts +++ b/arch/powerpc/boot/dts/sbc8349.dts @@ -278,7 +278,6 @@ }; pci0: pci@e0008500 { - cell-index = <1>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts index b1f1416ac998..9eefe00ed253 100644 --- a/arch/powerpc/boot/dts/sbc8548.dts +++ b/arch/powerpc/boot/dts/sbc8548.dts @@ -151,10 +151,22 @@ #size-cells = <1>; device_type = "soc"; ranges = <0x00000000 0xe0000000 0x00100000>; - reg = <0xe0000000 0x00001000>; // CCSRBAR bus-frequency = <0>; compatible = "simple-bus"; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + ecm@1000 { + compatible = "fsl,mpc8548-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8548-memory-controller"; reg = <0x2000 0x1000>; @@ -350,7 +362,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x01 (PCI-X slot) @66MHz */ @@ -380,7 +391,6 @@ }; pci2: pcie@e000a000 { - cell-index = <2>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts index c4564b81e473..239d57a55cf4 100644 --- a/arch/powerpc/boot/dts/sbc8560.dts +++ b/arch/powerpc/boot/dts/sbc8560.dts @@ -57,9 +57,21 @@ #size-cells = <1>; device_type = "soc"; ranges = <0x0 0xff700000 0x00100000>; - reg = <0xff700000 0x00100000>; clock-frequency = <0>; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8560-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8560-memory-controller"; reg = <0x2000 0x1000>; @@ -296,7 +308,6 @@ }; pci0: pci@ff708000 { - cell-index = <0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; diff --git a/arch/powerpc/boot/dts/sbc8641d.dts b/arch/powerpc/boot/dts/sbc8641d.dts index e3e914e78caa..ee5538feb455 100644 --- a/arch/powerpc/boot/dts/sbc8641d.dts +++ b/arch/powerpc/boot/dts/sbc8641d.dts @@ -126,9 +126,21 @@ device_type = "soc"; compatible = "simple-bus"; ranges = <0x00000000 0xf8000000 0x00100000>; - reg = <0xf8000000 0x00001000>; // CCSRBAR bus-frequency = <0>; + mcm-law@0 { + compatible = "fsl,mcm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + mcm@1000 { + compatible = "fsl,mpc8641-mcm", "fsl,mcm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + i2c@3000 { #address-cells = <1>; #size-cells = <0>; @@ -371,7 +383,6 @@ }; pci0: pcie@f8008000 { - cell-index = <0>; compatible = "fsl,mpc8641-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -410,7 +421,6 @@ }; pci1: pcie@f8009000 { - cell-index = <1>; compatible = "fsl,mpc8641-pcie"; device_type = "pci"; #interrupt-cells = <1>; diff --git a/arch/powerpc/boot/dts/sequoia.dts b/arch/powerpc/boot/dts/sequoia.dts index 43cc68bd3192..739dd0da2416 100644 --- a/arch/powerpc/boot/dts/sequoia.dts +++ b/arch/powerpc/boot/dts/sequoia.dts @@ -199,6 +199,28 @@ }; }; + ndfc@3,0 { + compatible = "ibm,ndfc"; + reg = <0x00000003 0x00000000 0x00002000>; + ccr = <0x00001000>; + bank-settings = <0x80002222>; + #address-cells = <1>; + #size-cells = <1>; + + nand { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x00084000>; + }; + partition@84000 { + label = "user"; + reg = <0x00000000 0x01f7c000>; + }; + }; + }; }; UART0: serial@ef600300 { diff --git a/arch/powerpc/boot/dts/socrates.dts b/arch/powerpc/boot/dts/socrates.dts index 7a6ae75a1e57..feb4ef6bd144 100644 --- a/arch/powerpc/boot/dts/socrates.dts +++ b/arch/powerpc/boot/dts/socrates.dts @@ -55,10 +55,22 @@ device_type = "soc"; ranges = <0x00000000 0xe0000000 0x00100000>; - reg = <0xe0000000 0x00001000>; // CCSRBAR 1M bus-frequency = <0>; // Filled in by U-Boot compatible = "fsl,mpc8544-immr", "simple-bus"; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + ecm@1000 { + compatible = "fsl,mpc8544-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8544-memory-controller"; reg = <0x2000 0x1000>; @@ -314,7 +326,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; diff --git a/arch/powerpc/boot/dts/stx_gp3_8560.dts b/arch/powerpc/boot/dts/stx_gp3_8560.dts index ea6b15152de3..b670d03fbcd9 100644 --- a/arch/powerpc/boot/dts/stx_gp3_8560.dts +++ b/arch/powerpc/boot/dts/stx_gp3_8560.dts @@ -52,10 +52,22 @@ #size-cells = <1>; device_type = "soc"; ranges = <0 0xfdf00000 0x100000>; - reg = <0xfdf00000 0x1000>; bus-frequency = <0>; compatible = "fsl,mpc8560-immr", "simple-bus"; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8560-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8540-memory-controller"; reg = <0x2000 0x1000>; @@ -251,7 +263,6 @@ }; pci0: pci@fdf08000 { - cell-index = <0>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts index b6f1fc6eb960..71347537b83e 100644 --- a/arch/powerpc/boot/dts/tqm8540.dts +++ b/arch/powerpc/boot/dts/tqm8540.dts @@ -54,10 +54,22 @@ #size-cells = <1>; device_type = "soc"; ranges = <0x0 0xe0000000 0x100000>; - reg = <0xe0000000 0x200>; bus-frequency = <0>; compatible = "fsl,mpc8540-immr", "simple-bus"; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8540-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8540-memory-controller"; reg = <0x2000 0x1000>; @@ -266,7 +278,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts index fa6a3d54a8a5..b30f63753d41 100644 --- a/arch/powerpc/boot/dts/tqm8541.dts +++ b/arch/powerpc/boot/dts/tqm8541.dts @@ -53,10 +53,22 @@ #size-cells = <1>; device_type = "soc"; ranges = <0x0 0xe0000000 0x100000>; - reg = <0xe0000000 0x200>; bus-frequency = <0>; compatible = "fsl,mpc8541-immr", "simple-bus"; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8541-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8540-memory-controller"; reg = <0x2000 0x1000>; @@ -288,7 +300,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts index 00f7ed7a2455..61f25e15fd66 100644 --- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts +++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts @@ -55,10 +55,22 @@ #size-cells = <1>; device_type = "soc"; ranges = <0x0 0xa0000000 0x100000>; - reg = <0xa0000000 0x1000>; // CCSRBAR bus-frequency = <0>; compatible = "fsl,mpc8548-immr", "simple-bus"; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + ecm@1000 { + compatible = "fsl,mpc8548-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8548-memory-controller"; reg = <0x2000 0x1000>; @@ -419,7 +431,6 @@ }; pci0: pci@a0008000 { - cell-index = <0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; @@ -441,7 +452,6 @@ }; pci1: pcie@a000a000 { - cell-index = <2>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x0 (PEX) */ diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts index 673e4a778ac8..025759c7c955 100644 --- a/arch/powerpc/boot/dts/tqm8548.dts +++ b/arch/powerpc/boot/dts/tqm8548.dts @@ -55,10 +55,22 @@ #size-cells = <1>; device_type = "soc"; ranges = <0x0 0xe0000000 0x100000>; - reg = <0xe0000000 0x1000>; // CCSRBAR bus-frequency = <0>; compatible = "fsl,mpc8548-immr", "simple-bus"; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + ecm@1000 { + compatible = "fsl,mpc8548-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8548-memory-controller"; reg = <0x2000 0x1000>; @@ -419,7 +431,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; @@ -441,7 +452,6 @@ }; pci1: pcie@e000a000 { - cell-index = <2>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x0 (PEX) */ diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts index 6a99f1eef7ad..95e287381836 100644 --- a/arch/powerpc/boot/dts/tqm8555.dts +++ b/arch/powerpc/boot/dts/tqm8555.dts @@ -53,10 +53,22 @@ #size-cells = <1>; device_type = "soc"; ranges = <0x0 0xe0000000 0x100000>; - reg = <0xe0000000 0x200>; bus-frequency = <0>; compatible = "fsl,mpc8555-immr", "simple-bus"; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8555-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8540-memory-controller"; reg = <0x2000 0x1000>; @@ -288,7 +300,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts index b6c2d71defd3..ff70580a8f4c 100644 --- a/arch/powerpc/boot/dts/tqm8560.dts +++ b/arch/powerpc/boot/dts/tqm8560.dts @@ -55,10 +55,22 @@ #size-cells = <1>; device_type = "soc"; ranges = <0x0 0xe0000000 0x100000>; - reg = <0xe0000000 0x200>; bus-frequency = <0>; compatible = "fsl,mpc8560-immr", "simple-bus"; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8560-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8540-memory-controller"; reg = <0x2000 0x1000>; @@ -359,7 +371,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; diff --git a/arch/powerpc/boot/dts/virtex440-ml510.dts b/arch/powerpc/boot/dts/virtex440-ml510.dts new file mode 100644 index 000000000000..81a8dc2c6365 --- /dev/null +++ b/arch/powerpc/boot/dts/virtex440-ml510.dts @@ -0,0 +1,465 @@ +/* + * Xilinx ML510 Reference Design support + * + * This DTS file was created for the ml510_bsb1_pcores_ppc440 reference design. + * The reference design contains a bug which prevent PCI DMA from working + * properly. A description of the bug is given in the plbv46_pci section. It + * needs to be fixed by the user until Xilinx updates their reference design. + * + * Copyright 2009, Roderick Colenbrander + */ + +/dts-v1/; +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,ml510-ref-design", "xlnx,virtex440"; + dcr-parent = <&ppc440_0>; + DDR2_SDRAM_DIMM0: memory@0 { + device_type = "memory"; + reg = < 0x0 0x20000000 >; + } ; + alias { + ethernet0 = &Hard_Ethernet_MAC; + serial0 = &RS232_Uart_1; + } ; + chosen { + bootargs = "console=ttyS0 root=/dev/ram"; + linux,stdout-path = "/plb@0/serial@83e00000"; + } ; + cpus { + #address-cells = <1>; + #cpus = <0x1>; + #size-cells = <0>; + ppc440_0: cpu@0 { + #address-cells = <1>; + #size-cells = <1>; + clock-frequency = <300000000>; + compatible = "PowerPC,440", "ibm,ppc440"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + dcr-access-method = "native"; + dcr-controller ; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + model = "PowerPC,440"; + reg = <0>; + timebase-frequency = <300000000>; + xlnx,apu-control = <0x2000>; + xlnx,apu-udi-0 = <0x0>; + xlnx,apu-udi-1 = <0x0>; + xlnx,apu-udi-10 = <0x0>; + xlnx,apu-udi-11 = <0x0>; + xlnx,apu-udi-12 = <0x0>; + xlnx,apu-udi-13 = <0x0>; + xlnx,apu-udi-14 = <0x0>; + xlnx,apu-udi-15 = <0x0>; + xlnx,apu-udi-2 = <0x0>; + xlnx,apu-udi-3 = <0x0>; + xlnx,apu-udi-4 = <0x0>; + xlnx,apu-udi-5 = <0x0>; + xlnx,apu-udi-6 = <0x0>; + xlnx,apu-udi-7 = <0x0>; + xlnx,apu-udi-8 = <0x0>; + xlnx,apu-udi-9 = <0x0>; + xlnx,dcr-autolock-enable = <0x1>; + xlnx,dcu-rd-ld-cache-plb-prio = <0x0>; + xlnx,dcu-rd-noncache-plb-prio = <0x0>; + xlnx,dcu-rd-touch-plb-prio = <0x0>; + xlnx,dcu-rd-urgent-plb-prio = <0x0>; + xlnx,dcu-wr-flush-plb-prio = <0x0>; + xlnx,dcu-wr-store-plb-prio = <0x0>; + xlnx,dcu-wr-urgent-plb-prio = <0x0>; + xlnx,dma0-control = <0x0>; + xlnx,dma0-plb-prio = <0x0>; + xlnx,dma0-rxchannelctrl = <0x1010000>; + xlnx,dma0-rxirqtimer = <0x3ff>; + xlnx,dma0-txchannelctrl = <0x1010000>; + xlnx,dma0-txirqtimer = <0x3ff>; + xlnx,dma1-control = <0x0>; + xlnx,dma1-plb-prio = <0x0>; + xlnx,dma1-rxchannelctrl = <0x1010000>; + xlnx,dma1-rxirqtimer = <0x3ff>; + xlnx,dma1-txchannelctrl = <0x1010000>; + xlnx,dma1-txirqtimer = <0x3ff>; + xlnx,dma2-control = <0x0>; + xlnx,dma2-plb-prio = <0x0>; + xlnx,dma2-rxchannelctrl = <0x1010000>; + xlnx,dma2-rxirqtimer = <0x3ff>; + xlnx,dma2-txchannelctrl = <0x1010000>; + xlnx,dma2-txirqtimer = <0x3ff>; + xlnx,dma3-control = <0x0>; + xlnx,dma3-plb-prio = <0x0>; + xlnx,dma3-rxchannelctrl = <0x1010000>; + xlnx,dma3-rxirqtimer = <0x3ff>; + xlnx,dma3-txchannelctrl = <0x1010000>; + xlnx,dma3-txirqtimer = <0x3ff>; + xlnx,endian-reset = <0x0>; + xlnx,generate-plb-timespecs = <0x1>; + xlnx,icu-rd-fetch-plb-prio = <0x0>; + xlnx,icu-rd-spec-plb-prio = <0x0>; + xlnx,icu-rd-touch-plb-prio = <0x0>; + xlnx,interconnect-imask = <0xffffffff>; + xlnx,mplb-allow-lock-xfer = <0x1>; + xlnx,mplb-arb-mode = <0x0>; + xlnx,mplb-awidth = <0x20>; + xlnx,mplb-counter = <0x500>; + xlnx,mplb-dwidth = <0x80>; + xlnx,mplb-max-burst = <0x8>; + xlnx,mplb-native-dwidth = <0x80>; + xlnx,mplb-p2p = <0x0>; + xlnx,mplb-prio-dcur = <0x2>; + xlnx,mplb-prio-dcuw = <0x3>; + xlnx,mplb-prio-icu = <0x4>; + xlnx,mplb-prio-splb0 = <0x1>; + xlnx,mplb-prio-splb1 = <0x0>; + xlnx,mplb-read-pipe-enable = <0x1>; + xlnx,mplb-sync-tattribute = <0x0>; + xlnx,mplb-wdog-enable = <0x1>; + xlnx,mplb-write-pipe-enable = <0x1>; + xlnx,mplb-write-post-enable = <0x1>; + xlnx,num-dma = <0x0>; + xlnx,pir = <0xf>; + xlnx,ppc440mc-addr-base = <0x0>; + xlnx,ppc440mc-addr-high = <0x1fffffff>; + xlnx,ppc440mc-arb-mode = <0x0>; + xlnx,ppc440mc-bank-conflict-mask = <0x1800000>; + xlnx,ppc440mc-control = <0xf810008f>; + xlnx,ppc440mc-max-burst = <0x8>; + xlnx,ppc440mc-prio-dcur = <0x2>; + xlnx,ppc440mc-prio-dcuw = <0x3>; + xlnx,ppc440mc-prio-icu = <0x4>; + xlnx,ppc440mc-prio-splb0 = <0x1>; + xlnx,ppc440mc-prio-splb1 = <0x0>; + xlnx,ppc440mc-row-conflict-mask = <0x7ffe00>; + xlnx,ppcdm-asyncmode = <0x0>; + xlnx,ppcds-asyncmode = <0x0>; + xlnx,user-reset = <0x0>; + } ; + } ; + plb_v46_0: plb@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,plb-v46-1.03.a", "simple-bus"; + ranges ; + FLASH: flash@fc000000 { + bank-width = <2>; + compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash"; + reg = < 0xfc000000 0x2000000 >; + xlnx,family = "virtex5"; + xlnx,include-datawidth-matching-0 = <0x1>; + xlnx,include-datawidth-matching-1 = <0x0>; + xlnx,include-datawidth-matching-2 = <0x0>; + xlnx,include-datawidth-matching-3 = <0x0>; + xlnx,include-negedge-ioregs = <0x0>; + xlnx,include-plb-ipif = <0x1>; + xlnx,include-wrbuf = <0x1>; + xlnx,max-mem-width = <0x10>; + xlnx,mch-native-dwidth = <0x20>; + xlnx,mch-plb-clk-period-ps = <0x2710>; + xlnx,mch-splb-awidth = <0x20>; + xlnx,mch0-accessbuf-depth = <0x10>; + xlnx,mch0-protocol = <0x0>; + xlnx,mch0-rddatabuf-depth = <0x10>; + xlnx,mch1-accessbuf-depth = <0x10>; + xlnx,mch1-protocol = <0x0>; + xlnx,mch1-rddatabuf-depth = <0x10>; + xlnx,mch2-accessbuf-depth = <0x10>; + xlnx,mch2-protocol = <0x0>; + xlnx,mch2-rddatabuf-depth = <0x10>; + xlnx,mch3-accessbuf-depth = <0x10>; + xlnx,mch3-protocol = <0x0>; + xlnx,mch3-rddatabuf-depth = <0x10>; + xlnx,mem0-width = <0x10>; + xlnx,mem1-width = <0x20>; + xlnx,mem2-width = <0x20>; + xlnx,mem3-width = <0x20>; + xlnx,num-banks-mem = <0x1>; + xlnx,num-channels = <0x2>; + xlnx,priority-mode = <0x0>; + xlnx,synch-mem-0 = <0x0>; + xlnx,synch-mem-1 = <0x0>; + xlnx,synch-mem-2 = <0x0>; + xlnx,synch-mem-3 = <0x0>; + xlnx,synch-pipedelay-0 = <0x2>; + xlnx,synch-pipedelay-1 = <0x2>; + xlnx,synch-pipedelay-2 = <0x2>; + xlnx,synch-pipedelay-3 = <0x2>; + xlnx,tavdv-ps-mem-0 = <0x1adb0>; + xlnx,tavdv-ps-mem-1 = <0x3a98>; + xlnx,tavdv-ps-mem-2 = <0x3a98>; + xlnx,tavdv-ps-mem-3 = <0x3a98>; + xlnx,tcedv-ps-mem-0 = <0x1adb0>; + xlnx,tcedv-ps-mem-1 = <0x3a98>; + xlnx,tcedv-ps-mem-2 = <0x3a98>; + xlnx,tcedv-ps-mem-3 = <0x3a98>; + xlnx,thzce-ps-mem-0 = <0x88b8>; + xlnx,thzce-ps-mem-1 = <0x1b58>; + xlnx,thzce-ps-mem-2 = <0x1b58>; + xlnx,thzce-ps-mem-3 = <0x1b58>; + xlnx,thzoe-ps-mem-0 = <0x1b58>; + xlnx,thzoe-ps-mem-1 = <0x1b58>; + xlnx,thzoe-ps-mem-2 = <0x1b58>; + xlnx,thzoe-ps-mem-3 = <0x1b58>; + xlnx,tlzwe-ps-mem-0 = <0x88b8>; + xlnx,tlzwe-ps-mem-1 = <0x0>; + xlnx,tlzwe-ps-mem-2 = <0x0>; + xlnx,tlzwe-ps-mem-3 = <0x0>; + xlnx,twc-ps-mem-0 = <0x1adb0>; + xlnx,twc-ps-mem-1 = <0x3a98>; + xlnx,twc-ps-mem-2 = <0x3a98>; + xlnx,twc-ps-mem-3 = <0x3a98>; + xlnx,twp-ps-mem-0 = <0x11170>; + xlnx,twp-ps-mem-1 = <0x2ee0>; + xlnx,twp-ps-mem-2 = <0x2ee0>; + xlnx,twp-ps-mem-3 = <0x2ee0>; + xlnx,xcl0-linesize = <0x4>; + xlnx,xcl0-writexfer = <0x1>; + xlnx,xcl1-linesize = <0x4>; + xlnx,xcl1-writexfer = <0x1>; + xlnx,xcl2-linesize = <0x4>; + xlnx,xcl2-writexfer = <0x1>; + xlnx,xcl3-linesize = <0x4>; + xlnx,xcl3-writexfer = <0x1>; + } ; + Hard_Ethernet_MAC: xps-ll-temac@81c00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,compound"; + ethernet@81c00000 { + compatible = "xlnx,xps-ll-temac-1.01.b"; + device_type = "network"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 8 2 >; + llink-connected = <&Hard_Ethernet_MAC_fifo>; + local-mac-address = [ 02 00 00 00 00 00 ]; + reg = < 0x81c00000 0x40 >; + xlnx,bus2core-clk-ratio = <0x1>; + xlnx,phy-type = <0x3>; + xlnx,phyaddr = <0x1>; + xlnx,rxcsum = <0x0>; + xlnx,rxfifo = <0x8000>; + xlnx,temac-type = <0x0>; + xlnx,txcsum = <0x0>; + xlnx,txfifo = <0x8000>; + } ; + } ; + Hard_Ethernet_MAC_fifo: xps-ll-fifo@81a00000 { + compatible = "xlnx,xps-ll-fifo-1.01.a"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 6 2 >; + reg = < 0x81a00000 0x10000 >; + xlnx,family = "virtex5"; + } ; + IIC_EEPROM: i2c@81600000 { + compatible = "xlnx,xps-iic-2.00.a"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 9 2 >; + reg = < 0x81600000 0x10000 >; + xlnx,clk-freq = <0x5f5e100>; + xlnx,family = "virtex5"; + xlnx,gpo-width = <0x1>; + xlnx,iic-freq = <0x186a0>; + xlnx,scl-inertial-delay = <0x5>; + xlnx,sda-inertial-delay = <0x5>; + xlnx,ten-bit-adr = <0x0>; + } ; + LCD_OPTIONAL: gpio@81420000 { + compatible = "xlnx,xps-gpio-1.00.a"; + reg = < 0x81420000 0x10000 >; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,dout-default = <0x0>; + xlnx,dout-default-2 = <0x0>; + xlnx,family = "virtex5"; + xlnx,gpio-width = <0xb>; + xlnx,interrupt-present = <0x0>; + xlnx,is-bidir = <0x1>; + xlnx,is-bidir-2 = <0x1>; + xlnx,is-dual = <0x0>; + xlnx,tri-default = <0xffffffff>; + xlnx,tri-default-2 = <0xffffffff>; + } ; + LEDs_4Bit: gpio@81400000 { + compatible = "xlnx,xps-gpio-1.00.a"; + reg = < 0x81400000 0x10000 >; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,dout-default = <0x0>; + xlnx,dout-default-2 = <0x0>; + xlnx,family = "virtex5"; + xlnx,gpio-width = <0x4>; + xlnx,interrupt-present = <0x0>; + xlnx,is-bidir = <0x1>; + xlnx,is-bidir-2 = <0x1>; + xlnx,is-dual = <0x0>; + xlnx,tri-default = <0xffffffff>; + xlnx,tri-default-2 = <0xffffffff>; + } ; + RS232_Uart_1: serial@83e00000 { + clock-frequency = <100000000>; + compatible = "xlnx,xps-uart16550-2.00.b", "ns16550"; + current-speed = <9600>; + device_type = "serial"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 11 2 >; + reg = < 0x83e00000 0x10000 >; + reg-offset = <0x1003>; + reg-shift = <2>; + xlnx,family = "virtex5"; + xlnx,has-external-rclk = <0x0>; + xlnx,has-external-xin = <0x0>; + xlnx,is-a-16550 = <0x1>; + } ; + SPI_EEPROM: xps-spi@feff8000 { + compatible = "xlnx,xps-spi-2.00.b"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 10 2 >; + reg = < 0xfeff8000 0x80 >; + xlnx,family = "virtex5"; + xlnx,fifo-exist = <0x1>; + xlnx,num-ss-bits = <0x1>; + xlnx,num-transfer-bits = <0x8>; + xlnx,sck-ratio = <0x80>; + } ; + SysACE_CompactFlash: sysace@83600000 { + compatible = "xlnx,xps-sysace-1.00.a"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 7 2 >; + reg = < 0x83600000 0x10000 >; + xlnx,family = "virtex5"; + xlnx,mem-width = <0x10>; + } ; + plbv46_pci_0: plbv46-pci@85e00000 { + #size-cells = <2>; + #address-cells = <3>; + compatible = "xlnx,plbv46-pci-1.03.a"; + device_type = "pci"; + reg = < 0x85e00000 0x10000 >; + + /* + * The default ML510 BSB has C_IPIFBAR2PCIBAR_0 set to + * 0 which means that a read/write to the memory mapped + * i/o region (which starts at 0xa0000000) for pci + * bar 0 on the plb side translates to 0. + * It is important to set this value to 0xa0000000, so + * that inbound and outbound pci transactions work + * properly including DMA. + */ + ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000 + 0x01000000 0 0x00000000 0xf0000000 0 0x00010000>; + + #interrupt-cells = <1>; + interrupt-parent = <&xps_intc_0>; + interrupt-map-mask = <0xff00 0x0 0x0 0x7>; + interrupt-map = < + /* IRQ mapping for pci slots and ALI M1533 + * periperhals. In total there are 5 interrupt + * lines connected to a xps_intc controller. + * Four of them are PCI IRQ A, B, C, D and + * which correspond to respectively xpx_intc + * 5, 4, 3 and 2. The fifth interrupt line is + * connected to the south bridge and this one + * uses irq 1 and is active high instead of + * active low. + * + * The M1533 contains various peripherals + * including AC97 audio, a modem, USB, IDE and + * some power management stuff. The modem + * isn't connected on the ML510 and the power + * management core also isn't used. + */ + + /* IDSEL 0x16 / dev=6, bus=0 / PCI slot 3 */ + 0x3000 0 0 1 &xps_intc_0 3 2 + 0x3000 0 0 2 &xps_intc_0 2 2 + 0x3000 0 0 3 &xps_intc_0 5 2 + 0x3000 0 0 4 &xps_intc_0 4 2 + + /* IDSEL 0x13 / dev=3, bus=1 / PCI slot 4 */ + /* + 0x11800 0 0 1 &xps_intc_0 5 0 2 + 0x11800 0 0 2 &xps_intc_0 4 0 2 + 0x11800 0 0 3 &xps_intc_0 3 0 2 + 0x11800 0 0 4 &xps_intc_0 2 0 2 + */ + + /* According to the datasheet + schematic + * ABCD [FPGA] of slot 5 is mapped to DABC. + * Testing showed that at least A maps to B, + * the mapping of the other pins is a guess + * and for that reason the lines have been + * commented out. + */ + /* IDSEL 0x15 / dev=5, bus=0 / PCI slot 5 */ + 0x2800 0 0 1 &xps_intc_0 4 2 + /* + 0x2800 0 0 2 &xps_intc_0 3 2 + 0x2800 0 0 3 &xps_intc_0 2 2 + 0x2800 0 0 4 &xps_intc_0 5 2 + */ + + /* IDSEL 0x12 / dev=2, bus=1 / PCI slot 6 */ + /* + 0x11000 0 0 1 &xps_intc_0 4 0 2 + 0x11000 0 0 2 &xps_intc_0 3 0 2 + 0x11000 0 0 3 &xps_intc_0 2 0 2 + 0x11000 0 0 4 &xps_intc_0 5 0 2 + */ + + /* IDSEL 0x11 / dev=1, bus=0 / AC97 audio */ + 0x0800 0 0 1 &i8259 7 2 + + /* IDSEL 0x1b / dev=11, bus=0 / IDE */ + 0x5800 0 0 1 &i8259 14 2 + + /* IDSEL 0x1f / dev 15, bus=0 / 2x USB 1.1 */ + 0x7800 0 0 1 &i8259 7 2 + >; + ali_m1533 { + #size-cells = <1>; + #address-cells = <2>; + i8259: interrupt-controller@20 { + reg = <1 0x20 2 + 1 0xa0 2 + 1 0x4d0 2>; + interrupt-controller; + device_type = "interrupt-controller"; + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "chrp,iic"; + + /* south bridge irq is active high */ + interrupts = <1 3>; + interrupt-parent = <&xps_intc_0>; + }; + }; + } ; + xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 { + compatible = "xlnx,xps-bram-if-cntlr-1.00.a"; + reg = < 0xffff0000 0x10000 >; + xlnx,family = "virtex5"; + } ; + xps_intc_0: interrupt-controller@81800000 { + #interrupt-cells = <0x2>; + compatible = "xlnx,xps-intc-1.00.a"; + interrupt-controller ; + reg = < 0x81800000 0x10000 >; + xlnx,num-intr-inputs = <0xc>; + } ; + xps_tft_0: tft@86e00000 { + compatible = "xlnx,xps-tft-1.00.a"; + reg = < 0x86e00000 0x10000 >; + xlnx,dcr-splb-slave-if = <0x1>; + xlnx,default-tft-base-addr = <0x0>; + xlnx,family = "virtex5"; + xlnx,i2c-slave-addr = <0x76>; + xlnx,mplb-awidth = <0x20>; + xlnx,mplb-dwidth = <0x80>; + xlnx,mplb-native-dwidth = <0x40>; + xlnx,mplb-smallest-slave = <0x20>; + xlnx,tft-interface = <0x1>; + } ; + } ; +} ; diff --git a/arch/powerpc/boot/dts/warp.dts b/arch/powerpc/boot/dts/warp.dts index 7e183ff9a317..01bfb56bbe80 100644 --- a/arch/powerpc/boot/dts/warp.dts +++ b/arch/powerpc/boot/dts/warp.dts @@ -1,7 +1,7 @@ /* * Device Tree Source for PIKA Warp * - * Copyright (c) 2008 PIKA Technologies + * Copyright (c) 2008-2009 PIKA Technologies * Sean MacLennan <smaclennan@pikatech.com> * * This file is licensed under the terms of the GNU General Public @@ -158,7 +158,7 @@ partition@0 { label = "splash"; - reg = <0x00000000 0x00020000>; + reg = <0x00000000 0x00010000>; }; partition@300000 { label = "fpga"; @@ -244,28 +244,27 @@ }; GPIO0: gpio@ef600b00 { - compatible = "ibm,gpio-440ep"; + compatible = "ibm,ppc4xx-gpio"; reg = <0xef600b00 0x00000048>; #gpio-cells = <2>; gpio-controller; }; GPIO1: gpio@ef600c00 { - compatible = "ibm,gpio-440ep"; + compatible = "ibm,ppc4xx-gpio"; reg = <0xef600c00 0x00000048>; #gpio-cells = <2>; gpio-controller; + }; - led@31 { - compatible = "linux,gpio-led"; - linux,name = ":green:"; - gpios = <&GPIO1 31 0>; - }; - - led@30 { - compatible = "linux,gpio-led"; - linux,name = ":red:"; - gpios = <&GPIO1 30 0>; + power-leds { + compatible = "gpio-leds"; + green { + gpios = <&GPIO1 0 0>; + default-state = "on"; + }; + red { + gpios = <&GPIO1 1 0>; }; }; |