diff options
Diffstat (limited to 'arch/sh/Kconfig')
| -rw-r--r-- | arch/sh/Kconfig | 28 |
1 files changed, 23 insertions, 5 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 8d50d527c595..e7390dd0283d 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -14,6 +14,7 @@ config SUPERH select HAVE_GENERIC_DMA_COHERENT select HAVE_IOREMAP_PROT if MMU select HAVE_ARCH_TRACEHOOK + select HAVE_DMA_API_DEBUG help The SuperH is a RISC processor targeted for use in embedded systems and consumer electronics; it was also used in the Sega Dreamcast @@ -21,16 +22,17 @@ config SUPERH <http://www.linux-sh.org/>. config SUPERH32 - def_bool !SUPERH64 + def_bool ARCH = "sh" select HAVE_KPROBES select HAVE_KRETPROBES select HAVE_FUNCTION_TRACER select HAVE_FTRACE_MCOUNT_RECORD select HAVE_DYNAMIC_FTRACE select HAVE_ARCH_KGDB + select ARCH_HIBERNATION_POSSIBLE if MMU config SUPERH64 - def_bool y if CPU_SH5 + def_bool ARCH = "sh64" config ARCH_DEFCONFIG string @@ -129,6 +131,9 @@ config ARCH_HAS_ILOG2_U64 config ARCH_NO_VIRT_TO_BUS def_bool y +config ARCH_HAS_DEFAULT_IDLE + def_bool y + config IO_TRAPPED bool @@ -183,6 +188,8 @@ config ARCH_SHMOBILE bool select ARCH_SUSPEND_POSSIBLE +if SUPERH32 + choice prompt "Processor sub-type selection" @@ -404,6 +411,15 @@ config CPU_SUBTYPE_SH7366 select SYS_SUPPORTS_NUMA select SYS_SUPPORTS_CMT +endchoice + +endif + +if SUPERH64 + +choice + prompt "Processor sub-type selection" + # SH-5 Processor Support config CPU_SUBTYPE_SH5_101 @@ -416,6 +432,8 @@ config CPU_SUBTYPE_SH5_103 endchoice +endif + source "arch/sh/mm/Kconfig" source "arch/sh/Kconfig.cpu" @@ -530,7 +548,7 @@ source kernel/Kconfig.hz config KEXEC bool "kexec system call (EXPERIMENTAL)" - depends on SUPERH32 && EXPERIMENTAL + depends on SUPERH32 && EXPERIMENTAL && MMU help kexec is a system call that implements the ability to shutdown your current kernel, and to start another kernel. It is like a reboot @@ -640,10 +658,10 @@ config GUSA_RB depends on GUSA && CPU_SH3 || (CPU_SH4 && !CPU_SH4A) help Enabling this option will allow the kernel to implement some - atomic operations using a software implemention of load-locked/ + atomic operations using a software implementation of load-locked/ store-conditional (LLSC). On machines which do not have hardware LLSC, this should be more efficient than the other alternative of - disabling insterrupts around the atomic sequence. + disabling interrupts around the atomic sequence. endmenu |