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path: root/drivers/clk/nxp/clk-lpc18xx-cgu.c
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Diffstat (limited to 'drivers/clk/nxp/clk-lpc18xx-cgu.c')
-rw-r--r--drivers/clk/nxp/clk-lpc18xx-cgu.c12
1 files changed, 4 insertions, 8 deletions
diff --git a/drivers/clk/nxp/clk-lpc18xx-cgu.c b/drivers/clk/nxp/clk-lpc18xx-cgu.c
index 8b686da5577b..69ebf65081b8 100644
--- a/drivers/clk/nxp/clk-lpc18xx-cgu.c
+++ b/drivers/clk/nxp/clk-lpc18xx-cgu.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Clk driver for NXP LPC18xx/LPC43xx Clock Generation Unit (CGU)
*
* Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/clk-provider.h>
@@ -457,9 +454,8 @@ static unsigned long lpc18xx_pll1_recalc_rate(struct clk_hw *hw,
struct lpc18xx_pll *pll = to_lpc_pll(hw);
u16 msel, nsel, psel;
bool direct, fbsel;
- u32 stat, ctrl;
+ u32 ctrl;
- stat = readl(pll->reg + LPC18XX_CGU_PLL1_STAT);
ctrl = readl(pll->reg + LPC18XX_CGU_PLL1_CTRL);
direct = (ctrl & LPC18XX_PLL1_CTRL_DIRECT) ? true : false;
@@ -523,7 +519,7 @@ static struct lpc18xx_cgu_pll_clk lpc18xx_cgu_src_clk_plls[] = {
LPC1XX_CGU_CLK_PLL(PLL1, pll1_src_ids, pll1_ops),
};
-static void lpc18xx_fill_parent_names(const char **parent, u32 *id, int size)
+static void lpc18xx_fill_parent_names(const char **parent, const u32 *id, int size)
{
int i;
@@ -610,7 +606,7 @@ static void __init lpc18xx_cgu_register_source_clks(struct device_node *np,
if (IS_ERR(clk))
pr_warn("%s: failed to register irc clk\n", __func__);
- /* Register crystal oscillator controlller */
+ /* Register crystal oscillator controller */
parents[0] = of_clk_get_parent_name(np, 0);
clk = clk_register_gate(NULL, clk_src_names[CLK_SRC_OSC], parents[0],
0, base + LPC18XX_CGU_XTAL_OSC_CTRL,