diff options
Diffstat (limited to 'drivers/clk/qcom/camcc-sdm845.c')
| -rw-r--r-- | drivers/clk/qcom/camcc-sdm845.c | 327 |
1 files changed, 172 insertions, 155 deletions
diff --git a/drivers/clk/qcom/camcc-sdm845.c b/drivers/clk/qcom/camcc-sdm845.c index 1b2cefef7431..27d44188a7ab 100644 --- a/drivers/clk/qcom/camcc-sdm845.c +++ b/drivers/clk/qcom/camcc-sdm845.c @@ -23,25 +23,6 @@ enum { P_CAM_CC_PLL1_OUT_EVEN, P_CAM_CC_PLL2_OUT_EVEN, P_CAM_CC_PLL3_OUT_EVEN, - P_CORE_BI_PLL_TEST_SE, -}; - -static const struct parent_map cam_cc_parent_map_0[] = { - { P_BI_TCXO, 0 }, - { P_CAM_CC_PLL2_OUT_EVEN, 1 }, - { P_CAM_CC_PLL1_OUT_EVEN, 2 }, - { P_CAM_CC_PLL3_OUT_EVEN, 5 }, - { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const cam_cc_parent_names_0[] = { - "bi_tcxo", - "cam_cc_pll2_out_even", - "cam_cc_pll1_out_even", - "cam_cc_pll3_out_even", - "cam_cc_pll0_out_even", - "core_bi_pll_test_se", }; static struct clk_alpha_pll cam_cc_pll0 = { @@ -50,7 +31,9 @@ static struct clk_alpha_pll cam_cc_pll0 = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll0", - .parent_names = (const char *[]){ "bi_tcxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", .name = "bi_tcxo", + }, .num_parents = 1, .ops = &clk_alpha_pll_fabia_ops, }, @@ -72,7 +55,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll0_out_even", - .parent_names = (const char *[]){ "cam_cc_pll0" }, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll0.clkr.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, @@ -84,7 +69,9 @@ static struct clk_alpha_pll cam_cc_pll1 = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll1", - .parent_names = (const char *[]){ "bi_tcxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", .name = "bi_tcxo", + }, .num_parents = 1, .ops = &clk_alpha_pll_fabia_ops, }, @@ -100,7 +87,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll1_out_even", - .parent_names = (const char *[]){ "cam_cc_pll1" }, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll1.clkr.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, @@ -112,7 +101,9 @@ static struct clk_alpha_pll cam_cc_pll2 = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll2", - .parent_names = (const char *[]){ "bi_tcxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", .name = "bi_tcxo", + }, .num_parents = 1, .ops = &clk_alpha_pll_fabia_ops, }, @@ -128,7 +119,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll2_out_even", - .parent_names = (const char *[]){ "cam_cc_pll2" }, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll2.clkr.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, @@ -140,7 +133,9 @@ static struct clk_alpha_pll cam_cc_pll3 = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll3", - .parent_names = (const char *[]){ "bi_tcxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", .name = "bi_tcxo", + }, .num_parents = 1, .ops = &clk_alpha_pll_fabia_ops, }, @@ -156,12 +151,30 @@ static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll3_out_even", - .parent_names = (const char *[]){ "cam_cc_pll3" }, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll3.clkr.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; +static const struct parent_map cam_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL2_OUT_EVEN, 1 }, + { P_CAM_CC_PLL1_OUT_EVEN, 2 }, + { P_CAM_CC_PLL3_OUT_EVEN, 5 }, + { P_CAM_CC_PLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_0[] = { + { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, + { .hw = &cam_cc_pll2_out_even.clkr.hw }, + { .hw = &cam_cc_pll1_out_even.clkr.hw }, + { .hw = &cam_cc_pll3_out_even.clkr.hw }, + { .hw = &cam_cc_pll0_out_even.clkr.hw }, +}; + static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), @@ -189,8 +202,8 @@ static struct clk_rcg2 cam_cc_bps_clk_src = { .freq_tbl = ftbl_cam_cc_bps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -212,8 +225,8 @@ static struct clk_rcg2 cam_cc_cci_clk_src = { .freq_tbl = ftbl_cam_cc_cci_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -232,8 +245,8 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cphy_rx_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -253,8 +266,8 @@ static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi0phytimer_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -268,8 +281,8 @@ static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi1phytimer_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -283,8 +296,8 @@ static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi2phytimer_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -298,8 +311,8 @@ static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi3phytimer_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -323,8 +336,8 @@ static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_fast_ahb_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -346,8 +359,8 @@ static struct clk_rcg2 cam_cc_fd_core_clk_src = { .freq_tbl = ftbl_cam_cc_fd_core_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_fd_core_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -369,8 +382,8 @@ static struct clk_rcg2 cam_cc_icp_clk_src = { .freq_tbl = ftbl_cam_cc_icp_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_icp_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -393,8 +406,8 @@ static struct clk_rcg2 cam_cc_ife_0_clk_src = { .freq_tbl = ftbl_cam_cc_ife_0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -416,8 +429,8 @@ static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_csid_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -430,8 +443,8 @@ static struct clk_rcg2 cam_cc_ife_1_clk_src = { .freq_tbl = ftbl_cam_cc_ife_0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -445,8 +458,8 @@ static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_csid_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -459,8 +472,8 @@ static struct clk_rcg2 cam_cc_ife_lite_clk_src = { .freq_tbl = ftbl_cam_cc_ife_0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -474,8 +487,8 @@ static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_csid_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -499,8 +512,8 @@ static struct clk_rcg2 cam_cc_ipe_0_clk_src = { .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -514,8 +527,8 @@ static struct clk_rcg2 cam_cc_ipe_1_clk_src = { .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_1_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -529,8 +542,8 @@ static struct clk_rcg2 cam_cc_jpeg_clk_src = { .freq_tbl = ftbl_cam_cc_bps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_jpeg_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -554,8 +567,8 @@ static struct clk_rcg2 cam_cc_lrme_clk_src = { .freq_tbl = ftbl_cam_cc_lrme_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_lrme_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -577,8 +590,8 @@ static struct clk_rcg2 cam_cc_mclk0_clk_src = { .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk0_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -592,8 +605,8 @@ static struct clk_rcg2 cam_cc_mclk1_clk_src = { .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk1_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -607,8 +620,8 @@ static struct clk_rcg2 cam_cc_mclk2_clk_src = { .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk2_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -622,8 +635,8 @@ static struct clk_rcg2 cam_cc_mclk3_clk_src = { .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk3_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -646,8 +659,8 @@ static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_slow_ahb_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -661,8 +674,8 @@ static struct clk_branch cam_cc_bps_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_ahb_clk", - .parent_names = (const char *[]){ - "cam_cc_slow_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -679,8 +692,8 @@ static struct clk_branch cam_cc_bps_areg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_areg_clk", - .parent_names = (const char *[]){ - "cam_cc_fast_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -710,8 +723,8 @@ static struct clk_branch cam_cc_bps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_clk", - .parent_names = (const char *[]){ - "cam_cc_bps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_bps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -754,8 +767,8 @@ static struct clk_branch cam_cc_cci_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_clk", - .parent_names = (const char *[]){ - "cam_cc_cci_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cci_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -772,8 +785,8 @@ static struct clk_branch cam_cc_cpas_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cpas_ahb_clk", - .parent_names = (const char *[]){ - "cam_cc_slow_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -790,8 +803,8 @@ static struct clk_branch cam_cc_csi0phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi0phytimer_clk", - .parent_names = (const char *[]){ - "cam_cc_csi0phytimer_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi0phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -808,8 +821,8 @@ static struct clk_branch cam_cc_csi1phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi1phytimer_clk", - .parent_names = (const char *[]){ - "cam_cc_csi1phytimer_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi1phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -826,8 +839,8 @@ static struct clk_branch cam_cc_csi2phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi2phytimer_clk", - .parent_names = (const char *[]){ - "cam_cc_csi2phytimer_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi2phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -844,8 +857,8 @@ static struct clk_branch cam_cc_csi3phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi3phytimer_clk", - .parent_names = (const char *[]){ - "cam_cc_csi3phytimer_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi3phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -862,8 +875,8 @@ static struct clk_branch cam_cc_csiphy0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy0_clk", - .parent_names = (const char *[]){ - "cam_cc_cphy_rx_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -880,8 +893,8 @@ static struct clk_branch cam_cc_csiphy1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy1_clk", - .parent_names = (const char *[]){ - "cam_cc_cphy_rx_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -898,8 +911,8 @@ static struct clk_branch cam_cc_csiphy2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy2_clk", - .parent_names = (const char *[]){ - "cam_cc_cphy_rx_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -916,8 +929,8 @@ static struct clk_branch cam_cc_csiphy3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy3_clk", - .parent_names = (const char *[]){ - "cam_cc_cphy_rx_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -934,8 +947,8 @@ static struct clk_branch cam_cc_fd_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_fd_core_clk", - .parent_names = (const char *[]){ - "cam_cc_fd_core_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fd_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -952,8 +965,8 @@ static struct clk_branch cam_cc_fd_core_uar_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_fd_core_uar_clk", - .parent_names = (const char *[]){ - "cam_cc_fd_core_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fd_core_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -995,8 +1008,8 @@ static struct clk_branch cam_cc_icp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_icp_clk", - .parent_names = (const char *[]){ - "cam_cc_icp_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_icp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1052,8 +1065,8 @@ static struct clk_branch cam_cc_ife_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1070,8 +1083,8 @@ static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_cphy_rx_clk", - .parent_names = (const char *[]){ - "cam_cc_cphy_rx_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1088,8 +1101,8 @@ static struct clk_branch cam_cc_ife_0_csid_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_csid_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_0_csid_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1106,8 +1119,8 @@ static struct clk_branch cam_cc_ife_0_dsp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_dsp_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1136,8 +1149,8 @@ static struct clk_branch cam_cc_ife_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1154,8 +1167,8 @@ static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_cphy_rx_clk", - .parent_names = (const char *[]){ - "cam_cc_cphy_rx_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1172,8 +1185,8 @@ static struct clk_branch cam_cc_ife_1_csid_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_csid_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_1_csid_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1190,8 +1203,8 @@ static struct clk_branch cam_cc_ife_1_dsp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_dsp_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1207,8 +1220,8 @@ static struct clk_branch cam_cc_ife_lite_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_lite_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_lite_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1225,8 +1238,8 @@ static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_cphy_rx_clk", - .parent_names = (const char *[]){ - "cam_cc_cphy_rx_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1243,8 +1256,8 @@ static struct clk_branch cam_cc_ife_lite_csid_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_csid_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_lite_csid_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_lite_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1261,8 +1274,8 @@ static struct clk_branch cam_cc_ipe_0_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_ahb_clk", - .parent_names = (const char *[]){ - "cam_cc_slow_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1279,8 +1292,8 @@ static struct clk_branch cam_cc_ipe_0_areg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_areg_clk", - .parent_names = (const char *[]){ - "cam_cc_fast_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1310,8 +1323,8 @@ static struct clk_branch cam_cc_ipe_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_clk", - .parent_names = (const char *[]){ - "cam_cc_ipe_0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ipe_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1328,8 +1341,8 @@ static struct clk_branch cam_cc_ipe_1_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_1_ahb_clk", - .parent_names = (const char *[]){ - "cam_cc_slow_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1346,8 +1359,8 @@ static struct clk_branch cam_cc_ipe_1_areg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_1_areg_clk", - .parent_names = (const char *[]){ - "cam_cc_fast_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1377,8 +1390,8 @@ static struct clk_branch cam_cc_ipe_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_1_clk", - .parent_names = (const char *[]){ - "cam_cc_ipe_1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ipe_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1395,8 +1408,8 @@ static struct clk_branch cam_cc_jpeg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_jpeg_clk", - .parent_names = (const char *[]){ - "cam_cc_jpeg_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_jpeg_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1413,8 +1426,8 @@ static struct clk_branch cam_cc_lrme_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_lrme_clk", - .parent_names = (const char *[]){ - "cam_cc_lrme_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_lrme_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1431,8 +1444,8 @@ static struct clk_branch cam_cc_mclk0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk0_clk", - .parent_names = (const char *[]){ - "cam_cc_mclk0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1449,8 +1462,8 @@ static struct clk_branch cam_cc_mclk1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk1_clk", - .parent_names = (const char *[]){ - "cam_cc_mclk1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1467,8 +1480,8 @@ static struct clk_branch cam_cc_mclk2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk2_clk", - .parent_names = (const char *[]){ - "cam_cc_mclk2_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1485,8 +1498,8 @@ static struct clk_branch cam_cc_mclk3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk3_clk", - .parent_names = (const char *[]){ - "cam_cc_mclk3_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1521,6 +1534,8 @@ static struct clk_branch cam_cc_sys_tmr_clk = { }, }; +static struct gdsc titan_top_gdsc; + static struct gdsc bps_gdsc = { .gdscr = 0x6004, .pd = { @@ -1554,6 +1569,7 @@ static struct gdsc ife_0_gdsc = { .name = "ife_0_gdsc", }, .flags = POLL_CFG_GDSCR, + .parent = &titan_top_gdsc.pd, .pwrsts = PWRSTS_OFF_ON, }; @@ -1563,6 +1579,7 @@ static struct gdsc ife_1_gdsc = { .name = "ife_1_gdsc", }, .flags = POLL_CFG_GDSCR, + .parent = &titan_top_gdsc.pd, .pwrsts = PWRSTS_OFF_ON, }; |