diff options
Diffstat (limited to 'drivers/edac/altera_edac.c')
| -rw-r--r-- | drivers/edac/altera_edac.c | 381 |
1 files changed, 242 insertions, 139 deletions
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c index 3c4929fda9d5..23ef0917483c 100644 --- a/drivers/edac/altera_edac.c +++ b/drivers/edac/altera_edac.c @@ -1,5 +1,5 @@ /* - * Copyright Altera Corporation (C) 2014. All rights reserved. + * Copyright Altera Corporation (C) 2014-2015. All rights reserved. * Copyright 2011-2012 Calxeda, Inc. * * This program is free software; you can redistribute it and/or modify it @@ -28,113 +28,92 @@ #include <linux/types.h> #include <linux/uaccess.h> +#include "altera_edac.h" #include "edac_core.h" #include "edac_module.h" #define EDAC_MOD_STR "altera_edac" #define EDAC_VERSION "1" -/* SDRAM Controller CtrlCfg Register */ -#define CTLCFG_OFST 0x00 - -/* SDRAM Controller CtrlCfg Register Bit Masks */ -#define CTLCFG_ECC_EN 0x400 -#define CTLCFG_ECC_CORR_EN 0x800 -#define CTLCFG_GEN_SB_ERR 0x2000 -#define CTLCFG_GEN_DB_ERR 0x4000 - -#define CTLCFG_ECC_AUTO_EN (CTLCFG_ECC_EN | \ - CTLCFG_ECC_CORR_EN) - -/* SDRAM Controller Address Width Register */ -#define DRAMADDRW_OFST 0x2C - -/* SDRAM Controller Address Widths Field Register */ -#define DRAMADDRW_COLBIT_MASK 0x001F -#define DRAMADDRW_COLBIT_SHIFT 0 -#define DRAMADDRW_ROWBIT_MASK 0x03E0 -#define DRAMADDRW_ROWBIT_SHIFT 5 -#define DRAMADDRW_BANKBIT_MASK 0x1C00 -#define DRAMADDRW_BANKBIT_SHIFT 10 -#define DRAMADDRW_CSBIT_MASK 0xE000 -#define DRAMADDRW_CSBIT_SHIFT 13 - -/* SDRAM Controller Interface Data Width Register */ -#define DRAMIFWIDTH_OFST 0x30 - -/* SDRAM Controller Interface Data Width Defines */ -#define DRAMIFWIDTH_16B_ECC 24 -#define DRAMIFWIDTH_32B_ECC 40 - -/* SDRAM Controller DRAM Status Register */ -#define DRAMSTS_OFST 0x38 - -/* SDRAM Controller DRAM Status Register Bit Masks */ -#define DRAMSTS_SBEERR 0x04 -#define DRAMSTS_DBEERR 0x08 -#define DRAMSTS_CORR_DROP 0x10 - -/* SDRAM Controller DRAM IRQ Register */ -#define DRAMINTR_OFST 0x3C - -/* SDRAM Controller DRAM IRQ Register Bit Masks */ -#define DRAMINTR_INTREN 0x01 -#define DRAMINTR_SBEMASK 0x02 -#define DRAMINTR_DBEMASK 0x04 -#define DRAMINTR_CORRDROPMASK 0x08 -#define DRAMINTR_INTRCLR 0x10 - -/* SDRAM Controller Single Bit Error Count Register */ -#define SBECOUNT_OFST 0x40 - -/* SDRAM Controller Single Bit Error Count Register Bit Masks */ -#define SBECOUNT_MASK 0x0F - -/* SDRAM Controller Double Bit Error Count Register */ -#define DBECOUNT_OFST 0x44 - -/* SDRAM Controller Double Bit Error Count Register Bit Masks */ -#define DBECOUNT_MASK 0x0F - -/* SDRAM Controller ECC Error Address Register */ -#define ERRADDR_OFST 0x48 - -/* SDRAM Controller ECC Error Address Register Bit Masks */ -#define ERRADDR_MASK 0xFFFFFFFF +static const struct altr_sdram_prv_data c5_data = { + .ecc_ctrl_offset = CV_CTLCFG_OFST, + .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN, + .ecc_stat_offset = CV_DRAMSTS_OFST, + .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR, + .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR, + .ecc_saddr_offset = CV_ERRADDR_OFST, + .ecc_daddr_offset = CV_ERRADDR_OFST, + .ecc_cecnt_offset = CV_SBECOUNT_OFST, + .ecc_uecnt_offset = CV_DBECOUNT_OFST, + .ecc_irq_en_offset = CV_DRAMINTR_OFST, + .ecc_irq_en_mask = CV_DRAMINTR_INTREN, + .ecc_irq_clr_offset = CV_DRAMINTR_OFST, + .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN), + .ecc_cnt_rst_offset = CV_DRAMINTR_OFST, + .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR, +#ifdef CONFIG_EDAC_DEBUG + .ce_ue_trgr_offset = CV_CTLCFG_OFST, + .ce_set_mask = CV_CTLCFG_GEN_SB_ERR, + .ue_set_mask = CV_CTLCFG_GEN_DB_ERR, +#endif +}; -/* Altera SDRAM Memory Controller data */ -struct altr_sdram_mc_data { - struct regmap *mc_vbase; +static const struct altr_sdram_prv_data a10_data = { + .ecc_ctrl_offset = A10_ECCCTRL1_OFST, + .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN, + .ecc_stat_offset = A10_INTSTAT_OFST, + .ecc_stat_ce_mask = A10_INTSTAT_SBEERR, + .ecc_stat_ue_mask = A10_INTSTAT_DBEERR, + .ecc_saddr_offset = A10_SERRADDR_OFST, + .ecc_daddr_offset = A10_DERRADDR_OFST, + .ecc_irq_en_offset = A10_ERRINTEN_OFST, + .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK, + .ecc_irq_clr_offset = A10_INTSTAT_OFST, + .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR), + .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST, + .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK, +#ifdef CONFIG_EDAC_DEBUG + .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST, + .ce_set_mask = A10_DIAGINT_TSERRA_MASK, + .ue_set_mask = A10_DIAGINT_TDERRA_MASK, +#endif }; static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id) { struct mem_ctl_info *mci = dev_id; struct altr_sdram_mc_data *drvdata = mci->pvt_info; - u32 status, err_count, err_addr; + const struct altr_sdram_prv_data *priv = drvdata->data; + u32 status, err_count = 1, err_addr; - /* Error Address is shared by both SBE & DBE */ - regmap_read(drvdata->mc_vbase, ERRADDR_OFST, &err_addr); + regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status); - regmap_read(drvdata->mc_vbase, DRAMSTS_OFST, &status); - - if (status & DRAMSTS_DBEERR) { - regmap_read(drvdata->mc_vbase, DBECOUNT_OFST, &err_count); + if (status & priv->ecc_stat_ue_mask) { + regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset, + &err_addr); + if (priv->ecc_uecnt_offset) + regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset, + &err_count); panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n", err_count, err_addr); } - if (status & DRAMSTS_SBEERR) { - regmap_read(drvdata->mc_vbase, SBECOUNT_OFST, &err_count); + if (status & priv->ecc_stat_ce_mask) { + regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset, + &err_addr); + if (priv->ecc_uecnt_offset) + regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset, + &err_count); edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count, err_addr >> PAGE_SHIFT, err_addr & ~PAGE_MASK, 0, 0, 0, -1, mci->ctl_name, ""); - } - - regmap_write(drvdata->mc_vbase, DRAMINTR_OFST, - (DRAMINTR_INTRCLR | DRAMINTR_INTREN)); + /* Clear IRQ to resume */ + regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset, + priv->ecc_irq_clr_mask); - return IRQ_HANDLED; + return IRQ_HANDLED; + } + return IRQ_NONE; } #ifdef CONFIG_EDAC_DEBUG @@ -144,6 +123,7 @@ static ssize_t altr_sdr_mc_err_inject_write(struct file *file, { struct mem_ctl_info *mci = file->private_data; struct altr_sdram_mc_data *drvdata = mci->pvt_info; + const struct altr_sdram_prv_data *priv = drvdata->data; u32 *ptemp; dma_addr_t dma_handle; u32 reg, read_reg; @@ -156,8 +136,9 @@ static ssize_t altr_sdr_mc_err_inject_write(struct file *file, return -ENOMEM; } - regmap_read(drvdata->mc_vbase, CTLCFG_OFST, &read_reg); - read_reg &= ~(CTLCFG_GEN_SB_ERR | CTLCFG_GEN_DB_ERR); + regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset, + &read_reg); + read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask); /* Error are injected by writing a word while the SBE or DBE * bit in the CTLCFG register is set. Reading the word will @@ -166,20 +147,20 @@ static ssize_t altr_sdr_mc_err_inject_write(struct file *file, if (count == 3) { edac_printk(KERN_ALERT, EDAC_MC, "Inject Double bit error\n"); - regmap_write(drvdata->mc_vbase, CTLCFG_OFST, - (read_reg | CTLCFG_GEN_DB_ERR)); + regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, + (read_reg | priv->ue_set_mask)); } else { edac_printk(KERN_ALERT, EDAC_MC, "Inject Single bit error\n"); - regmap_write(drvdata->mc_vbase, CTLCFG_OFST, - (read_reg | CTLCFG_GEN_SB_ERR)); + regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, + (read_reg | priv->ce_set_mask)); } ptemp[0] = 0x5A5A5A5A; ptemp[1] = 0xA5A5A5A5; /* Clear the error injection bits */ - regmap_write(drvdata->mc_vbase, CTLCFG_OFST, read_reg); + regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg); /* Ensure it has been written out */ wmb(); @@ -219,50 +200,106 @@ static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci) {} #endif -/* Get total memory size in bytes */ -static u32 altr_sdram_get_total_mem_size(struct regmap *mc_vbase) +/* Get total memory size from Open Firmware DTB */ +static unsigned long get_total_mem(void) { - u32 size, read_reg, row, bank, col, cs, width; - - if (regmap_read(mc_vbase, DRAMADDRW_OFST, &read_reg) < 0) - return 0; - - if (regmap_read(mc_vbase, DRAMIFWIDTH_OFST, &width) < 0) - return 0; - - col = (read_reg & DRAMADDRW_COLBIT_MASK) >> - DRAMADDRW_COLBIT_SHIFT; - row = (read_reg & DRAMADDRW_ROWBIT_MASK) >> - DRAMADDRW_ROWBIT_SHIFT; - bank = (read_reg & DRAMADDRW_BANKBIT_MASK) >> - DRAMADDRW_BANKBIT_SHIFT; - cs = (read_reg & DRAMADDRW_CSBIT_MASK) >> - DRAMADDRW_CSBIT_SHIFT; - - /* Correct for ECC as its not addressible */ - if (width == DRAMIFWIDTH_32B_ECC) - width = 32; - if (width == DRAMIFWIDTH_16B_ECC) - width = 16; - - /* calculate the SDRAM size base on this info */ - size = 1 << (row + bank + col); - size = size * cs * (width / 8); - return size; + struct device_node *np = NULL; + const unsigned int *reg, *reg_end; + int len, sw, aw; + unsigned long start, size, total_mem = 0; + + for_each_node_by_type(np, "memory") { + aw = of_n_addr_cells(np); + sw = of_n_size_cells(np); + reg = (const unsigned int *)of_get_property(np, "reg", &len); + reg_end = reg + (len / sizeof(u32)); + + total_mem = 0; + do { + start = of_read_number(reg, aw); + reg += aw; + size = of_read_number(reg, sw); + reg += sw; + total_mem += size; + } while (reg < reg_end); + } + edac_dbg(0, "total_mem 0x%lx\n", total_mem); + return total_mem; +} + +static const struct of_device_id altr_sdram_ctrl_of_match[] = { + { .compatible = "altr,sdram-edac", .data = (void *)&c5_data}, + { .compatible = "altr,sdram-edac-a10", .data = (void *)&a10_data}, + {}, +}; +MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match); + +static int a10_init(struct regmap *mc_vbase) +{ + if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST, + A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) { + edac_printk(KERN_ERR, EDAC_MC, + "Error setting SB IRQ mode\n"); + return -ENODEV; + } + + if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) { + edac_printk(KERN_ERR, EDAC_MC, + "Error setting trigger count\n"); + return -ENODEV; + } + + return 0; +} + +static int a10_unmask_irq(struct platform_device *pdev, u32 mask) +{ + void __iomem *sm_base; + int ret = 0; + + if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32), + dev_name(&pdev->dev))) { + edac_printk(KERN_ERR, EDAC_MC, + "Unable to request mem region\n"); + return -EBUSY; + } + + sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32)); + if (!sm_base) { + edac_printk(KERN_ERR, EDAC_MC, + "Unable to ioremap device\n"); + + ret = -ENOMEM; + goto release; + } + + iowrite32(mask, sm_base); + + iounmap(sm_base); + +release: + release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32)); + + return ret; } static int altr_sdram_probe(struct platform_device *pdev) { + const struct of_device_id *id; struct edac_mc_layer layers[2]; struct mem_ctl_info *mci; struct altr_sdram_mc_data *drvdata; + const struct altr_sdram_prv_data *priv; struct regmap *mc_vbase; struct dimm_info *dimm; - u32 read_reg, mem_size; - int irq; - int res = 0; + u32 read_reg; + int irq, irq2, res = 0; + unsigned long mem_size, irqflags = 0; + + id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev); + if (!id) + return -ENODEV; - /* Validate the SDRAM controller has ECC enabled */ /* Grab the register range from the sdr controller in device tree */ mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "altr,sdr-syscon"); @@ -272,25 +309,46 @@ static int altr_sdram_probe(struct platform_device *pdev) return -ENODEV; } - if (regmap_read(mc_vbase, CTLCFG_OFST, &read_reg) || - ((read_reg & CTLCFG_ECC_AUTO_EN) != CTLCFG_ECC_AUTO_EN)) { + /* Check specific dependencies for the module */ + priv = of_match_node(altr_sdram_ctrl_of_match, + pdev->dev.of_node)->data; + + /* Validate the SDRAM controller has ECC enabled */ + if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) || + ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) { edac_printk(KERN_ERR, EDAC_MC, "No ECC/ECC disabled [0x%08X]\n", read_reg); return -ENODEV; } /* Grab memory size from device tree. */ - mem_size = altr_sdram_get_total_mem_size(mc_vbase); + mem_size = get_total_mem(); if (!mem_size) { + edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n"); + return -ENODEV; + } + + /* Ensure the SDRAM Interrupt is disabled */ + if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset, + priv->ecc_irq_en_mask, 0)) { + edac_printk(KERN_ERR, EDAC_MC, + "Error disabling SDRAM ECC IRQ\n"); + return -ENODEV; + } + + /* Toggle to clear the SDRAM Error count */ + if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, + priv->ecc_cnt_rst_mask, + priv->ecc_cnt_rst_mask)) { edac_printk(KERN_ERR, EDAC_MC, - "Unable to calculate memory size\n"); + "Error clearing SDRAM ECC count\n"); return -ENODEV; } - /* Ensure the SDRAM Interrupt is disabled and cleared */ - if (regmap_write(mc_vbase, DRAMINTR_OFST, DRAMINTR_INTRCLR)) { + if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, + priv->ecc_cnt_rst_mask, 0)) { edac_printk(KERN_ERR, EDAC_MC, - "Error clearing SDRAM ECC IRQ\n"); + "Error clearing SDRAM ECC count\n"); return -ENODEV; } @@ -301,6 +359,9 @@ static int altr_sdram_probe(struct platform_device *pdev) return -ENODEV; } + /* Arria10 has a 2nd IRQ */ + irq2 = platform_get_irq(pdev, 1); + layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers[0].size = 1; layers[0].is_virt_csrow = true; @@ -315,9 +376,12 @@ static int altr_sdram_probe(struct platform_device *pdev) mci->pdev = &pdev->dev; drvdata = mci->pvt_info; drvdata->mc_vbase = mc_vbase; + drvdata->data = priv; platform_set_drvdata(pdev, mci); if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { + edac_printk(KERN_ERR, EDAC_MC, + "Unable to get managed device resource\n"); res = -ENOMEM; goto free; } @@ -342,8 +406,32 @@ static int altr_sdram_probe(struct platform_device *pdev) if (res < 0) goto err; + /* Only the Arria10 has separate IRQs */ + if (irq2 > 0) { + /* Arria10 specific initialization */ + res = a10_init(mc_vbase); + if (res < 0) + goto err2; + + res = devm_request_irq(&pdev->dev, irq2, + altr_sdram_mc_err_handler, + IRQF_SHARED, dev_name(&pdev->dev), mci); + if (res < 0) { + edac_mc_printk(mci, KERN_ERR, + "Unable to request irq %d\n", irq2); + res = -ENODEV; + goto err2; + } + + res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK); + if (res < 0) + goto err2; + + irqflags = IRQF_SHARED; + } + res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler, - 0, dev_name(&pdev->dev), mci); + irqflags, dev_name(&pdev->dev), mci); if (res < 0) { edac_mc_printk(mci, KERN_ERR, "Unable to request irq %d\n", irq); @@ -351,8 +439,9 @@ static int altr_sdram_probe(struct platform_device *pdev) goto err2; } - if (regmap_write(drvdata->mc_vbase, DRAMINTR_OFST, - (DRAMINTR_INTRCLR | DRAMINTR_INTREN))) { + /* Infrastructure ready - enable the IRQ */ + if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset, + priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) { edac_mc_printk(mci, KERN_ERR, "Error enabling SDRAM ECC IRQ\n"); res = -ENODEV; @@ -388,17 +477,31 @@ static int altr_sdram_remove(struct platform_device *pdev) return 0; } -static const struct of_device_id altr_sdram_ctrl_of_match[] = { - { .compatible = "altr,sdram-edac", }, - {}, +/* + * If you want to suspend, need to disable EDAC by removing it + * from the device tree or defconfig. + */ +#ifdef CONFIG_PM +static int altr_sdram_prepare(struct device *dev) +{ + pr_err("Suspend not allowed when EDAC is enabled.\n"); + + return -EPERM; +} + +static const struct dev_pm_ops altr_sdram_pm_ops = { + .prepare = altr_sdram_prepare, }; -MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match); +#endif static struct platform_driver altr_sdram_edac_driver = { .probe = altr_sdram_probe, .remove = altr_sdram_remove, .driver = { .name = "altr_sdram_edac", +#ifdef CONFIG_PM + .pm = &altr_sdram_pm_ops, +#endif .of_match_table = altr_sdram_ctrl_of_match, }, }; |