diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc_hw_types.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index a8dc3082e3e1..7bc0be839c9e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -62,6 +62,9 @@ enum dc_plane_addr_type { PLN_ADDR_TYPE_GRAPHICS = 0, PLN_ADDR_TYPE_GRPH_STEREO, PLN_ADDR_TYPE_VIDEO_PROGRESSIVE, +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + PLN_ADDR_TYPE_RGBEA +#endif }; struct dc_plane_address { @@ -84,6 +87,16 @@ struct dc_plane_address { PHYSICAL_ADDRESS_LOC right_meta_addr; union large_integer right_dcc_const_color; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + PHYSICAL_ADDRESS_LOC left_alpha_addr; + PHYSICAL_ADDRESS_LOC left_alpha_meta_addr; + union large_integer left_alpha_dcc_const_color; + + PHYSICAL_ADDRESS_LOC right_alpha_addr; + PHYSICAL_ADDRESS_LOC right_alpha_meta_addr; + union large_integer right_alpha_dcc_const_color; +#endif + } grph_stereo; /*video progressive*/ @@ -96,6 +109,18 @@ struct dc_plane_address { PHYSICAL_ADDRESS_LOC chroma_meta_addr; union large_integer chroma_dcc_const_color; } video_progressive; + +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + struct { + PHYSICAL_ADDRESS_LOC addr; + PHYSICAL_ADDRESS_LOC meta_addr; + union large_integer dcc_const_color; + + PHYSICAL_ADDRESS_LOC alpha_addr; + PHYSICAL_ADDRESS_LOC alpha_meta_addr; + union large_integer alpha_dcc_const_color; + } rgbea; +#endif }; union large_integer page_table_base; @@ -131,9 +156,15 @@ struct dc_plane_dcc_param { int meta_pitch; bool independent_64b_blks; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + uint8_t dcc_ind_blk; +#endif int meta_pitch_c; bool independent_64b_blks_c; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + uint8_t dcc_ind_blk_c; +#endif }; /*Displayable pixel format in fb*/ @@ -169,6 +200,10 @@ enum surface_pixel_format { SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX, SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT, SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT, +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + SURFACE_PIXEL_FORMAT_GRPH_RGBE, + SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA, +#endif SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr = SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, |