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path: root/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
index be49fc7f4abe..ffd0014ec3b5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
@@ -126,7 +126,7 @@ static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock
/* Maximum total throughput with all the slices combined. This is different from how DP spec specifies it.
* Our decoder's total throughput in Pix/s is equal to DISPCLK. This is then shared between slices.
- * The value below is the absolute maximum value. The actual througput may be lower, but it'll always
+ * The value below is the absolute maximum value. The actual throughput may be lower, but it'll always
* be sufficient to process the input pixel rate fed into a single DSC engine.
*/
dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz;