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path: root/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c17
1 files changed, 12 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
index 136a9dc062bc..784a8b6f360d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
@@ -575,11 +575,18 @@ static void dsc_write_to_registers(struct display_stream_compressor *dsc, const
PIC_HEIGHT, reg_vals->pps.pic_height);
// dscc registers
- REG_SET_4(DSCC_CONFIG0, 0,
- ICH_RESET_AT_END_OF_LINE, reg_vals->ich_reset_at_eol,
- NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1,
- ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en,
- NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1);
+ if (dsc20->dsc_mask->ICH_RESET_AT_END_OF_LINE == 0) {
+ REG_SET_3(DSCC_CONFIG0, 0,
+ NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1,
+ ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en,
+ NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1);
+ } else {
+ REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE,
+ reg_vals->ich_reset_at_eol, NUMBER_OF_SLICES_PER_LINE,
+ reg_vals->num_slices_h - 1, ALTERNATE_ICH_ENCODING_EN,
+ reg_vals->alternate_ich_encoding_en, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION,
+ reg_vals->num_slices_v - 1);
+ }
REG_SET(DSCC_CONFIG1, 0,
DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size);