diff options
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_default.h')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_default.h | 6114 |
1 files changed, 6114 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_default.h new file mode 100644 index 000000000000..a86d38f2d03d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_default.h @@ -0,0 +1,6114 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _gc_11_0_0_DEFAULT_HEADER +#define _gc_11_0_0_DEFAULT_HEADER + + +// addressBlock: gc_sdma0_sdma0dec +#define regSDMA0_DEC_START_DEFAULT 0x00000000 +#define regSDMA0_F32_MISC_CNTL_DEFAULT 0x00000000 +#define regSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000 +#define regSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000 +#define regSDMA0_POWER_CNTL_DEFAULT 0x00000000 +#define regSDMA0_CNTL_DEFAULT 0x00002440 +#define regSDMA0_CHICKEN_BITS_DEFAULT 0x0107d186 +#define regSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000545 +#define regSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00000545 +#define regSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000 +#define regSDMA0_RB_RPTR_FETCH_HI_DEFAULT 0x00000000 +#define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000 +#define regSDMA0_IB_OFFSET_FETCH_DEFAULT 0x00000000 +#define regSDMA0_PROGRAM_DEFAULT 0x00000000 +#define regSDMA0_STATUS_REG_DEFAULT 0x46dee557 +#define regSDMA0_STATUS1_REG_DEFAULT 0x000403ff +#define regSDMA0_CNTL1_DEFAULT 0x00000c30 +#define regSDMA0_HBM_PAGE_CONFIG_DEFAULT 0x00000000 +#define regSDMA0_UCODE_CHECKSUM_DEFAULT 0x00000000 +#define regSDMA0_FREEZE_DEFAULT 0x00000000 +#define regSDMA0_PROCESS_QUANTUM0_DEFAULT 0x00000000 +#define regSDMA0_PROCESS_QUANTUM1_DEFAULT 0x00000000 +#define regSDMA0_WATCHDOG_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE_STATUS0_DEFAULT 0x22222222 +#define regSDMA0_EDC_CONFIG_DEFAULT 0x00000004 +#define regSDMA0_BA_THRESHOLD_DEFAULT 0x03ff03ff +#define regSDMA0_ID_DEFAULT 0x00000001 +#define regSDMA0_VERSION_DEFAULT 0x00000600 +#define regSDMA0_EDC_COUNTER_DEFAULT 0x00000000 +#define regSDMA0_EDC_COUNTER_CLEAR_DEFAULT 0x00000000 +#define regSDMA0_STATUS2_REG_DEFAULT 0x00000000 +#define regSDMA0_ATOMIC_CNTL_DEFAULT 0x00000200 +#define regSDMA0_ATOMIC_PREOP_LO_DEFAULT 0x00000000 +#define regSDMA0_ATOMIC_PREOP_HI_DEFAULT 0x00000000 +#define regSDMA0_UTCL1_CNTL_DEFAULT 0x2c000288 +#define regSDMA0_UTCL1_WATERMK_DEFAULT 0x00000000 +#define regSDMA0_UTCL1_TIMEOUT_DEFAULT 0x00000000 +#define regSDMA0_UTCL1_PAGE_DEFAULT 0x010cec00 +#define regSDMA0_UTCL1_RD_STATUS_DEFAULT 0xb90700ff +#define regSDMA0_UTCL1_WR_STATUS_DEFAULT 0xf90780ff +#define regSDMA0_UTCL1_INV0_DEFAULT 0x00000000 +#define regSDMA0_UTCL1_INV1_DEFAULT 0x00000000 +#define regSDMA0_UTCL1_INV2_DEFAULT 0x00000000 +#define regSDMA0_UTCL1_RD_XNACK0_DEFAULT 0x00000000 +#define regSDMA0_UTCL1_RD_XNACK1_DEFAULT 0x00000000 +#define regSDMA0_UTCL1_WR_XNACK0_DEFAULT 0x00000000 +#define regSDMA0_UTCL1_WR_XNACK1_DEFAULT 0x00000000 +#define regSDMA0_RELAX_ORDERING_LUT_DEFAULT 0xc0000806 +#define regSDMA0_CHICKEN_BITS_2_DEFAULT 0x400007c9 +#define regSDMA0_STATUS3_REG_DEFAULT 0x03f00000 +#define regSDMA0_PHYSICAL_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_PHYSICAL_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_GLOBAL_QUANTUM_DEFAULT 0x00000000 +#define regSDMA0_ERROR_LOG_DEFAULT 0x0000000f +#define regSDMA0_PUB_DUMMY_REG0_DEFAULT 0x00000000 +#define regSDMA0_PUB_DUMMY_REG1_DEFAULT 0x00000000 +#define regSDMA0_PUB_DUMMY_REG2_DEFAULT 0x00000000 +#define regSDMA0_PUB_DUMMY_REG3_DEFAULT 0x00000000 +#define regSDMA0_F32_COUNTER_DEFAULT 0x00000000 +#define regSDMA0_CRD_CNTL_DEFAULT 0x18694840 +#define regSDMA0_RLC_CGCG_CTRL_DEFAULT 0x00400000 +#define regSDMA0_AQL_STATUS_DEFAULT 0x00000003 +#define regSDMA0_EA_DBIT_ADDR_DATA_DEFAULT 0x0000270d +#define regSDMA0_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000 +#define regSDMA0_TLBI_GCR_CNTL_DEFAULT 0x40600454 +#define regSDMA0_TILING_CONFIG_DEFAULT 0x00000000 +#define regSDMA0_INT_STATUS_DEFAULT 0x00000000 +#define regSDMA0_HOLE_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_HOLE_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_CLOCK_GATING_STATUS_DEFAULT 0x00000000 +#define regSDMA0_STATUS4_REG_DEFAULT 0x00000001 +#define regSDMA0_SCRATCH_RAM_DATA_DEFAULT 0x00000000 +#define regSDMA0_SCRATCH_RAM_ADDR_DEFAULT 0x00000000 +#define regSDMA0_TIMESTAMP_CNTL_DEFAULT 0x00000000 +#define regSDMA0_STATUS5_REG_DEFAULT 0x00000000 +#define regSDMA0_QUEUE_RESET_REQ_DEFAULT 0x00000000 +#define regSDMA0_STATUS6_REG_DEFAULT 0x00000000 +#define regSDMA0_UCODE1_CHECKSUM_DEFAULT 0x00000000 +#define regSDMA0_CE_CTRL_DEFAULT 0x00000000 +#define regSDMA0_FED_STATUS_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_RB_CNTL_DEFAULT 0x00040800 +#define regSDMA0_QUEUE0_RB_BASE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_RB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_RB_RPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_RB_RPTR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_RB_WPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_RB_WPTR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_IB_CNTL_DEFAULT 0x00000100 +#define regSDMA0_QUEUE0_IB_RPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_IB_OFFSET_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_IB_BASE_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_IB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_IB_SIZE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_SKIP_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regSDMA0_QUEUE0_DOORBELL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_DOORBELL_LOG_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_PREEMPT_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_DUMMY_REG_DEFAULT 0x0000000f +#define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regSDMA0_QUEUE0_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_RB_PREEMPT_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_MIDCMD_DATA0_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_MIDCMD_DATA1_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_MIDCMD_DATA2_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_MIDCMD_DATA3_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_MIDCMD_DATA4_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_MIDCMD_DATA5_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_MIDCMD_DATA6_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_MIDCMD_DATA7_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_MIDCMD_DATA8_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_MIDCMD_DATA9_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_MIDCMD_DATA10_DEFAULT 0x00000000 +#define regSDMA0_QUEUE0_MIDCMD_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_RB_CNTL_DEFAULT 0x00040800 +#define regSDMA0_QUEUE1_RB_BASE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_RB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_RB_RPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_RB_RPTR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_RB_WPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_RB_WPTR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_IB_CNTL_DEFAULT 0x00000100 +#define regSDMA0_QUEUE1_IB_RPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_IB_OFFSET_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_IB_BASE_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_IB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_IB_SIZE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_SKIP_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regSDMA0_QUEUE1_DOORBELL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_DOORBELL_LOG_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_PREEMPT_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_DUMMY_REG_DEFAULT 0x0000000f +#define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regSDMA0_QUEUE1_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_RB_PREEMPT_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_MIDCMD_DATA0_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_MIDCMD_DATA1_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_MIDCMD_DATA2_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_MIDCMD_DATA3_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_MIDCMD_DATA4_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_MIDCMD_DATA5_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_MIDCMD_DATA6_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_MIDCMD_DATA7_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_MIDCMD_DATA8_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_MIDCMD_DATA9_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_MIDCMD_DATA10_DEFAULT 0x00000000 +#define regSDMA0_QUEUE1_MIDCMD_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_RB_CNTL_DEFAULT 0x00040800 +#define regSDMA0_QUEUE2_RB_BASE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_RB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_RB_RPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_RB_RPTR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_RB_WPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_RB_WPTR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_IB_CNTL_DEFAULT 0x00000100 +#define regSDMA0_QUEUE2_IB_RPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_IB_OFFSET_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_IB_BASE_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_IB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_IB_SIZE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_SKIP_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regSDMA0_QUEUE2_DOORBELL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_DOORBELL_LOG_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_PREEMPT_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_DUMMY_REG_DEFAULT 0x0000000f +#define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regSDMA0_QUEUE2_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_RB_PREEMPT_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_MIDCMD_DATA0_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_MIDCMD_DATA1_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_MIDCMD_DATA2_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_MIDCMD_DATA3_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_MIDCMD_DATA4_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_MIDCMD_DATA5_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_MIDCMD_DATA6_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_MIDCMD_DATA7_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_MIDCMD_DATA8_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_MIDCMD_DATA9_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_MIDCMD_DATA10_DEFAULT 0x00000000 +#define regSDMA0_QUEUE2_MIDCMD_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_RB_CNTL_DEFAULT 0x00040800 +#define regSDMA0_QUEUE3_RB_BASE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_RB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_RB_RPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_RB_RPTR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_RB_WPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_RB_WPTR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_IB_CNTL_DEFAULT 0x00000100 +#define regSDMA0_QUEUE3_IB_RPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_IB_OFFSET_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_IB_BASE_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_IB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_IB_SIZE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_SKIP_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regSDMA0_QUEUE3_DOORBELL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_DOORBELL_LOG_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_PREEMPT_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_DUMMY_REG_DEFAULT 0x0000000f +#define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regSDMA0_QUEUE3_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_RB_PREEMPT_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_MIDCMD_DATA0_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_MIDCMD_DATA1_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_MIDCMD_DATA2_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_MIDCMD_DATA3_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_MIDCMD_DATA4_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_MIDCMD_DATA5_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_MIDCMD_DATA6_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_MIDCMD_DATA7_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_MIDCMD_DATA8_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_MIDCMD_DATA9_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_MIDCMD_DATA10_DEFAULT 0x00000000 +#define regSDMA0_QUEUE3_MIDCMD_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_RB_CNTL_DEFAULT 0x00040800 +#define regSDMA0_QUEUE4_RB_BASE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_RB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_RB_RPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_RB_RPTR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_RB_WPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_RB_WPTR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_IB_CNTL_DEFAULT 0x00000100 +#define regSDMA0_QUEUE4_IB_RPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_IB_OFFSET_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_IB_BASE_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_IB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_IB_SIZE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_SKIP_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regSDMA0_QUEUE4_DOORBELL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_DOORBELL_LOG_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_PREEMPT_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_DUMMY_REG_DEFAULT 0x0000000f +#define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regSDMA0_QUEUE4_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_RB_PREEMPT_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_MIDCMD_DATA0_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_MIDCMD_DATA1_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_MIDCMD_DATA2_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_MIDCMD_DATA3_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_MIDCMD_DATA4_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_MIDCMD_DATA5_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_MIDCMD_DATA6_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_MIDCMD_DATA7_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_MIDCMD_DATA8_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_MIDCMD_DATA9_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_MIDCMD_DATA10_DEFAULT 0x00000000 +#define regSDMA0_QUEUE4_MIDCMD_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_RB_CNTL_DEFAULT 0x00040800 +#define regSDMA0_QUEUE5_RB_BASE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_RB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_RB_RPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_RB_RPTR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_RB_WPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_RB_WPTR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_IB_CNTL_DEFAULT 0x00000100 +#define regSDMA0_QUEUE5_IB_RPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_IB_OFFSET_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_IB_BASE_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_IB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_IB_SIZE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_SKIP_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regSDMA0_QUEUE5_DOORBELL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_DOORBELL_LOG_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_PREEMPT_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_DUMMY_REG_DEFAULT 0x0000000f +#define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regSDMA0_QUEUE5_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_RB_PREEMPT_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_MIDCMD_DATA0_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_MIDCMD_DATA1_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_MIDCMD_DATA2_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_MIDCMD_DATA3_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_MIDCMD_DATA4_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_MIDCMD_DATA5_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_MIDCMD_DATA6_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_MIDCMD_DATA7_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_MIDCMD_DATA8_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_MIDCMD_DATA9_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_MIDCMD_DATA10_DEFAULT 0x00000000 +#define regSDMA0_QUEUE5_MIDCMD_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_RB_CNTL_DEFAULT 0x00040800 +#define regSDMA0_QUEUE6_RB_BASE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_RB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_RB_RPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_RB_RPTR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_RB_WPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_RB_WPTR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_IB_CNTL_DEFAULT 0x00000100 +#define regSDMA0_QUEUE6_IB_RPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_IB_OFFSET_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_IB_BASE_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_IB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_IB_SIZE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_SKIP_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regSDMA0_QUEUE6_DOORBELL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_DOORBELL_LOG_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_PREEMPT_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_DUMMY_REG_DEFAULT 0x0000000f +#define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regSDMA0_QUEUE6_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_RB_PREEMPT_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_MIDCMD_DATA0_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_MIDCMD_DATA1_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_MIDCMD_DATA2_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_MIDCMD_DATA3_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_MIDCMD_DATA4_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_MIDCMD_DATA5_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_MIDCMD_DATA6_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_MIDCMD_DATA7_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_MIDCMD_DATA8_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_MIDCMD_DATA9_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_MIDCMD_DATA10_DEFAULT 0x00000000 +#define regSDMA0_QUEUE6_MIDCMD_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_RB_CNTL_DEFAULT 0x00040800 +#define regSDMA0_QUEUE7_RB_BASE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_RB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_RB_RPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_RB_RPTR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_RB_WPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_RB_WPTR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_IB_CNTL_DEFAULT 0x00000100 +#define regSDMA0_QUEUE7_IB_RPTR_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_IB_OFFSET_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_IB_BASE_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_IB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_IB_SIZE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_SKIP_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regSDMA0_QUEUE7_DOORBELL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_DOORBELL_LOG_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_PREEMPT_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_DUMMY_REG_DEFAULT 0x0000000f +#define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regSDMA0_QUEUE7_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_RB_PREEMPT_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_MIDCMD_DATA0_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_MIDCMD_DATA1_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_MIDCMD_DATA2_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_MIDCMD_DATA3_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_MIDCMD_DATA4_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_MIDCMD_DATA5_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_MIDCMD_DATA6_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_MIDCMD_DATA7_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_MIDCMD_DATA8_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_MIDCMD_DATA9_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_MIDCMD_DATA10_DEFAULT 0x00000000 +#define regSDMA0_QUEUE7_MIDCMD_CNTL_DEFAULT 0x00000000 + + +// addressBlock: gc_sdma0_sdma1dec +#define regSDMA1_DEC_START_DEFAULT 0x00000000 +#define regSDMA1_F32_MISC_CNTL_DEFAULT 0x00000000 +#define regSDMA1_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000 +#define regSDMA1_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000 +#define regSDMA1_POWER_CNTL_DEFAULT 0x00000000 +#define regSDMA1_CNTL_DEFAULT 0x00002440 +#define regSDMA1_CHICKEN_BITS_DEFAULT 0x0107d186 +#define regSDMA1_GB_ADDR_CONFIG_DEFAULT 0x00000545 +#define regSDMA1_GB_ADDR_CONFIG_READ_DEFAULT 0x00000545 +#define regSDMA1_RB_RPTR_FETCH_DEFAULT 0x00000000 +#define regSDMA1_RB_RPTR_FETCH_HI_DEFAULT 0x00000000 +#define regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000 +#define regSDMA1_IB_OFFSET_FETCH_DEFAULT 0x00000000 +#define regSDMA1_PROGRAM_DEFAULT 0x00000000 +#define regSDMA1_STATUS_REG_DEFAULT 0x46dee557 +#define regSDMA1_STATUS1_REG_DEFAULT 0x000403ff +#define regSDMA1_CNTL1_DEFAULT 0x00000c30 +#define regSDMA1_HBM_PAGE_CONFIG_DEFAULT 0x00000000 +#define regSDMA1_UCODE_CHECKSUM_DEFAULT 0x00000000 +#define regSDMA1_FREEZE_DEFAULT 0x00000000 +#define regSDMA1_PROCESS_QUANTUM0_DEFAULT 0x00000000 +#define regSDMA1_PROCESS_QUANTUM1_DEFAULT 0x00000000 +#define regSDMA1_WATCHDOG_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE_STATUS0_DEFAULT 0x22222222 +#define regSDMA1_EDC_CONFIG_DEFAULT 0x00000004 +#define regSDMA1_BA_THRESHOLD_DEFAULT 0x03ff03ff +#define regSDMA1_ID_DEFAULT 0x00000001 +#define regSDMA1_VERSION_DEFAULT 0x00000600 +#define regSDMA1_EDC_COUNTER_DEFAULT 0x00000000 +#define regSDMA1_EDC_COUNTER_CLEAR_DEFAULT 0x00000000 +#define regSDMA1_STATUS2_REG_DEFAULT 0x00000000 +#define regSDMA1_ATOMIC_CNTL_DEFAULT 0x00000200 +#define regSDMA1_ATOMIC_PREOP_LO_DEFAULT 0x00000000 +#define regSDMA1_ATOMIC_PREOP_HI_DEFAULT 0x00000000 +#define regSDMA1_UTCL1_CNTL_DEFAULT 0x2c000288 +#define regSDMA1_UTCL1_WATERMK_DEFAULT 0x00000000 +#define regSDMA1_UTCL1_TIMEOUT_DEFAULT 0x00000000 +#define regSDMA1_UTCL1_PAGE_DEFAULT 0x010cec00 +#define regSDMA1_UTCL1_RD_STATUS_DEFAULT 0xb90700ff +#define regSDMA1_UTCL1_WR_STATUS_DEFAULT 0xf90780ff +#define regSDMA1_UTCL1_INV0_DEFAULT 0x00000000 +#define regSDMA1_UTCL1_INV1_DEFAULT 0x00000000 +#define regSDMA1_UTCL1_INV2_DEFAULT 0x00000000 +#define regSDMA1_UTCL1_RD_XNACK0_DEFAULT 0x00000000 +#define regSDMA1_UTCL1_RD_XNACK1_DEFAULT 0x00000000 +#define regSDMA1_UTCL1_WR_XNACK0_DEFAULT 0x00000000 +#define regSDMA1_UTCL1_WR_XNACK1_DEFAULT 0x00000000 +#define regSDMA1_RELAX_ORDERING_LUT_DEFAULT 0xc0000806 +#define regSDMA1_CHICKEN_BITS_2_DEFAULT 0x400007c9 +#define regSDMA1_STATUS3_REG_DEFAULT 0x03f00000 +#define regSDMA1_PHYSICAL_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_PHYSICAL_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_GLOBAL_QUANTUM_DEFAULT 0x00000000 +#define regSDMA1_ERROR_LOG_DEFAULT 0x0000000f +#define regSDMA1_PUB_DUMMY_REG0_DEFAULT 0x00000000 +#define regSDMA1_PUB_DUMMY_REG1_DEFAULT 0x00000000 +#define regSDMA1_PUB_DUMMY_REG2_DEFAULT 0x00000000 +#define regSDMA1_PUB_DUMMY_REG3_DEFAULT 0x00000000 +#define regSDMA1_F32_COUNTER_DEFAULT 0x00000000 +#define regSDMA1_CRD_CNTL_DEFAULT 0x18694840 +#define regSDMA1_RLC_CGCG_CTRL_DEFAULT 0x00400000 +#define regSDMA1_AQL_STATUS_DEFAULT 0x00000003 +#define regSDMA1_EA_DBIT_ADDR_DATA_DEFAULT 0x0000270d +#define regSDMA1_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000 +#define regSDMA1_TLBI_GCR_CNTL_DEFAULT 0x40600454 +#define regSDMA1_TILING_CONFIG_DEFAULT 0x00000000 +#define regSDMA1_INT_STATUS_DEFAULT 0x00000000 +#define regSDMA1_HOLE_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_HOLE_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_CLOCK_GATING_STATUS_DEFAULT 0x00000000 +#define regSDMA1_STATUS4_REG_DEFAULT 0x00000001 +#define regSDMA1_SCRATCH_RAM_DATA_DEFAULT 0x00000000 +#define regSDMA1_SCRATCH_RAM_ADDR_DEFAULT 0x00000000 +#define regSDMA1_TIMESTAMP_CNTL_DEFAULT 0x00000000 +#define regSDMA1_STATUS5_REG_DEFAULT 0x00000000 +#define regSDMA1_QUEUE_RESET_REQ_DEFAULT 0x00000000 +#define regSDMA1_STATUS6_REG_DEFAULT 0x00000000 +#define regSDMA1_UCODE1_CHECKSUM_DEFAULT 0x00000000 +#define regSDMA1_CE_CTRL_DEFAULT 0x00000000 +#define regSDMA1_FED_STATUS_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_RB_CNTL_DEFAULT 0x00040800 +#define regSDMA1_QUEUE0_RB_BASE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_RB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_RB_RPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_RB_RPTR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_RB_WPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_RB_WPTR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_IB_CNTL_DEFAULT 0x00000100 +#define regSDMA1_QUEUE0_IB_RPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_IB_OFFSET_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_IB_BASE_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_IB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_IB_SIZE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_SKIP_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regSDMA1_QUEUE0_DOORBELL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_DOORBELL_LOG_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_PREEMPT_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_DUMMY_REG_DEFAULT 0x0000000f +#define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regSDMA1_QUEUE0_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_RB_PREEMPT_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_MIDCMD_DATA0_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_MIDCMD_DATA1_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_MIDCMD_DATA2_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_MIDCMD_DATA3_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_MIDCMD_DATA4_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_MIDCMD_DATA5_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_MIDCMD_DATA6_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_MIDCMD_DATA7_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_MIDCMD_DATA8_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_MIDCMD_DATA9_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_MIDCMD_DATA10_DEFAULT 0x00000000 +#define regSDMA1_QUEUE0_MIDCMD_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_RB_CNTL_DEFAULT 0x00040800 +#define regSDMA1_QUEUE1_RB_BASE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_RB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_RB_RPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_RB_RPTR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_RB_WPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_RB_WPTR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_IB_CNTL_DEFAULT 0x00000100 +#define regSDMA1_QUEUE1_IB_RPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_IB_OFFSET_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_IB_BASE_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_IB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_IB_SIZE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_SKIP_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regSDMA1_QUEUE1_DOORBELL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_DOORBELL_LOG_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_PREEMPT_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_DUMMY_REG_DEFAULT 0x0000000f +#define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regSDMA1_QUEUE1_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_RB_PREEMPT_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_MIDCMD_DATA0_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_MIDCMD_DATA1_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_MIDCMD_DATA2_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_MIDCMD_DATA3_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_MIDCMD_DATA4_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_MIDCMD_DATA5_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_MIDCMD_DATA6_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_MIDCMD_DATA7_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_MIDCMD_DATA8_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_MIDCMD_DATA9_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_MIDCMD_DATA10_DEFAULT 0x00000000 +#define regSDMA1_QUEUE1_MIDCMD_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_RB_CNTL_DEFAULT 0x00040800 +#define regSDMA1_QUEUE2_RB_BASE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_RB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_RB_RPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_RB_RPTR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_RB_WPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_RB_WPTR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_IB_CNTL_DEFAULT 0x00000100 +#define regSDMA1_QUEUE2_IB_RPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_IB_OFFSET_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_IB_BASE_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_IB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_IB_SIZE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_SKIP_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regSDMA1_QUEUE2_DOORBELL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_DOORBELL_LOG_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_PREEMPT_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_DUMMY_REG_DEFAULT 0x0000000f +#define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regSDMA1_QUEUE2_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_RB_PREEMPT_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_MIDCMD_DATA0_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_MIDCMD_DATA1_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_MIDCMD_DATA2_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_MIDCMD_DATA3_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_MIDCMD_DATA4_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_MIDCMD_DATA5_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_MIDCMD_DATA6_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_MIDCMD_DATA7_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_MIDCMD_DATA8_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_MIDCMD_DATA9_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_MIDCMD_DATA10_DEFAULT 0x00000000 +#define regSDMA1_QUEUE2_MIDCMD_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_RB_CNTL_DEFAULT 0x00040800 +#define regSDMA1_QUEUE3_RB_BASE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_RB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_RB_RPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_RB_RPTR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_RB_WPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_RB_WPTR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_IB_CNTL_DEFAULT 0x00000100 +#define regSDMA1_QUEUE3_IB_RPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_IB_OFFSET_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_IB_BASE_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_IB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_IB_SIZE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_SKIP_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regSDMA1_QUEUE3_DOORBELL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_DOORBELL_LOG_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_PREEMPT_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_DUMMY_REG_DEFAULT 0x0000000f +#define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regSDMA1_QUEUE3_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_RB_PREEMPT_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_MIDCMD_DATA0_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_MIDCMD_DATA1_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_MIDCMD_DATA2_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_MIDCMD_DATA3_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_MIDCMD_DATA4_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_MIDCMD_DATA5_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_MIDCMD_DATA6_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_MIDCMD_DATA7_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_MIDCMD_DATA8_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_MIDCMD_DATA9_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_MIDCMD_DATA10_DEFAULT 0x00000000 +#define regSDMA1_QUEUE3_MIDCMD_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_RB_CNTL_DEFAULT 0x00040800 +#define regSDMA1_QUEUE4_RB_BASE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_RB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_RB_RPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_RB_RPTR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_RB_WPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_RB_WPTR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_IB_CNTL_DEFAULT 0x00000100 +#define regSDMA1_QUEUE4_IB_RPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_IB_OFFSET_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_IB_BASE_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_IB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_IB_SIZE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_SKIP_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regSDMA1_QUEUE4_DOORBELL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_DOORBELL_LOG_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_PREEMPT_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_DUMMY_REG_DEFAULT 0x0000000f +#define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regSDMA1_QUEUE4_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_RB_PREEMPT_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_MIDCMD_DATA0_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_MIDCMD_DATA1_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_MIDCMD_DATA2_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_MIDCMD_DATA3_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_MIDCMD_DATA4_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_MIDCMD_DATA5_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_MIDCMD_DATA6_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_MIDCMD_DATA7_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_MIDCMD_DATA8_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_MIDCMD_DATA9_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_MIDCMD_DATA10_DEFAULT 0x00000000 +#define regSDMA1_QUEUE4_MIDCMD_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_RB_CNTL_DEFAULT 0x00040800 +#define regSDMA1_QUEUE5_RB_BASE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_RB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_RB_RPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_RB_RPTR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_RB_WPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_RB_WPTR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_IB_CNTL_DEFAULT 0x00000100 +#define regSDMA1_QUEUE5_IB_RPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_IB_OFFSET_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_IB_BASE_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_IB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_IB_SIZE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_SKIP_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regSDMA1_QUEUE5_DOORBELL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_DOORBELL_LOG_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_PREEMPT_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_DUMMY_REG_DEFAULT 0x0000000f +#define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regSDMA1_QUEUE5_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_RB_PREEMPT_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_MIDCMD_DATA0_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_MIDCMD_DATA1_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_MIDCMD_DATA2_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_MIDCMD_DATA3_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_MIDCMD_DATA4_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_MIDCMD_DATA5_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_MIDCMD_DATA6_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_MIDCMD_DATA7_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_MIDCMD_DATA8_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_MIDCMD_DATA9_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_MIDCMD_DATA10_DEFAULT 0x00000000 +#define regSDMA1_QUEUE5_MIDCMD_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_RB_CNTL_DEFAULT 0x00040800 +#define regSDMA1_QUEUE6_RB_BASE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_RB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_RB_RPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_RB_RPTR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_RB_WPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_RB_WPTR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_IB_CNTL_DEFAULT 0x00000100 +#define regSDMA1_QUEUE6_IB_RPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_IB_OFFSET_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_IB_BASE_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_IB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_IB_SIZE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_SKIP_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regSDMA1_QUEUE6_DOORBELL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_DOORBELL_LOG_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_PREEMPT_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_DUMMY_REG_DEFAULT 0x0000000f +#define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regSDMA1_QUEUE6_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_RB_PREEMPT_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_MIDCMD_DATA0_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_MIDCMD_DATA1_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_MIDCMD_DATA2_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_MIDCMD_DATA3_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_MIDCMD_DATA4_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_MIDCMD_DATA5_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_MIDCMD_DATA6_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_MIDCMD_DATA7_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_MIDCMD_DATA8_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_MIDCMD_DATA9_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_MIDCMD_DATA10_DEFAULT 0x00000000 +#define regSDMA1_QUEUE6_MIDCMD_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_RB_CNTL_DEFAULT 0x00040800 +#define regSDMA1_QUEUE7_RB_BASE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_RB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_RB_RPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_RB_RPTR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_RB_WPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_RB_WPTR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_IB_CNTL_DEFAULT 0x00000100 +#define regSDMA1_QUEUE7_IB_RPTR_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_IB_OFFSET_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_IB_BASE_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_IB_BASE_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_IB_SIZE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_SKIP_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_CONTEXT_STATUS_DEFAULT 0x00000804 +#define regSDMA1_QUEUE7_DOORBELL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_DOORBELL_LOG_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_CSA_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_CSA_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_SCHEDULE_CNTL_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_PREEMPT_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_DUMMY_REG_DEFAULT 0x0000000f +#define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_RB_AQL_CNTL_DEFAULT 0x00004000 +#define regSDMA1_QUEUE7_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_RB_PREEMPT_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_MIDCMD_DATA0_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_MIDCMD_DATA1_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_MIDCMD_DATA2_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_MIDCMD_DATA3_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_MIDCMD_DATA4_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_MIDCMD_DATA5_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_MIDCMD_DATA6_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_MIDCMD_DATA7_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_MIDCMD_DATA8_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_MIDCMD_DATA9_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_MIDCMD_DATA10_DEFAULT 0x00000000 +#define regSDMA1_QUEUE7_MIDCMD_CNTL_DEFAULT 0x00000000 + + +// addressBlock: gc_grbmdec +#define regGRBM_CNTL_DEFAULT 0x00000018 +#define regGRBM_SKEW_CNTL_DEFAULT 0x00000020 +#define regGRBM_STATUS2_DEFAULT 0x00000000 +#define regGRBM_PWR_CNTL_DEFAULT 0x00000000 +#define regGRBM_STATUS_DEFAULT 0x00000000 +#define regGRBM_STATUS_SE0_DEFAULT 0x00000000 +#define regGRBM_STATUS_SE1_DEFAULT 0x00000000 +#define regGRBM_STATUS3_DEFAULT 0x00000000 +#define regGRBM_SOFT_RESET_DEFAULT 0x00000000 +#define regGRBM_GFX_CLKEN_CNTL_DEFAULT 0x00000402 +#define regGRBM_WAIT_IDLE_CLOCKS_DEFAULT 0x00000030 +#define regGRBM_STATUS_SE2_DEFAULT 0x00000000 +#define regGRBM_STATUS_SE3_DEFAULT 0x00000000 +#define regGRBM_STATUS_SE4_DEFAULT 0x00000000 +#define regGRBM_STATUS_SE5_DEFAULT 0x00000000 +#define regGRBM_READ_ERROR_DEFAULT 0x00000000 +#define regGRBM_READ_ERROR2_DEFAULT 0x00000000 +#define regGRBM_INT_CNTL_DEFAULT 0x00000000 +#define regGRBM_TRAP_OP_DEFAULT 0x00000000 +#define regGRBM_TRAP_ADDR_DEFAULT 0x00000000 +#define regGRBM_TRAP_ADDR_MSK_DEFAULT 0x0003ffff +#define regGRBM_TRAP_WD_DEFAULT 0x00000000 +#define regGRBM_TRAP_WD_MSK_DEFAULT 0xffffffff +#define regGRBM_DSM_BYPASS_DEFAULT 0x00000000 +#define regGRBM_WRITE_ERROR_DEFAULT 0x00000000 +#define regGRBM_CHIP_REVISION_DEFAULT 0x00000000 +#define regGRBM_IH_CREDIT_DEFAULT 0x00010000 +#define regGRBM_PWR_CNTL2_DEFAULT 0x00010000 +#define regGRBM_UTCL2_INVAL_RANGE_START_DEFAULT 0x0000286d +#define regGRBM_UTCL2_INVAL_RANGE_END_DEFAULT 0x000028c6 +#define regGRBM_INVALID_PIPE_DEFAULT 0x00000000 +#define regGRBM_FENCE_RANGE0_DEFAULT 0x00000000 +#define regGRBM_FENCE_RANGE1_DEFAULT 0x00000000 +#define regGRBM_SCRATCH_REG0_DEFAULT 0x00000000 +#define regGRBM_SCRATCH_REG1_DEFAULT 0x00000000 +#define regGRBM_SCRATCH_REG2_DEFAULT 0x00000000 +#define regGRBM_SCRATCH_REG3_DEFAULT 0x00000000 +#define regGRBM_SCRATCH_REG4_DEFAULT 0x00000000 +#define regGRBM_SCRATCH_REG5_DEFAULT 0x00000000 +#define regGRBM_SCRATCH_REG6_DEFAULT 0x00000000 +#define regGRBM_SCRATCH_REG7_DEFAULT 0x00000000 +#define regVIOLATION_DATA_ASYNC_VF_PROG_DEFAULT 0x00000000 + + +// addressBlock: gc_cpdec +#define regCP_CPC_DEBUG_CNTL_DEFAULT 0x00000000 +#define regCP_CPC_DEBUG_DATA_DEFAULT 0x00000000 +#define regCP_CPC_STATUS_DEFAULT 0x00000000 +#define regCP_CPC_BUSY_STAT_DEFAULT 0x00000000 +#define regCP_CPC_STALLED_STAT1_DEFAULT 0x00000000 +#define regCP_CPF_STATUS_DEFAULT 0x00000000 +#define regCP_CPF_BUSY_STAT_DEFAULT 0x00000000 +#define regCP_CPF_STALLED_STAT1_DEFAULT 0x00000000 +#define regCP_CPC_BUSY_STAT2_DEFAULT 0x00000000 +#define regCP_CPC_GRBM_FREE_COUNT_DEFAULT 0x00000008 +#define regCP_CPC_PRIV_VIOLATION_ADDR_DEFAULT 0x00000000 +#define regCP_MEC_ME1_HEADER_DUMP_DEFAULT 0xdef0def0 +#define regCP_MEC_ME2_HEADER_DUMP_DEFAULT 0xdef0def0 +#define regCP_CPC_SCRATCH_INDEX_DEFAULT 0x00000000 +#define regCP_CPC_SCRATCH_DATA_DEFAULT 0x00000000 +#define regCP_CPF_GRBM_FREE_COUNT_DEFAULT 0x00000002 +#define regCP_CPF_BUSY_STAT2_DEFAULT 0x00000000 +#define regCP_CPC_HALT_HYST_COUNT_DEFAULT 0x00000002 +#define regCP_STALLED_STAT3_DEFAULT 0x00000000 +#define regCP_STALLED_STAT1_DEFAULT 0x00000000 +#define regCP_STALLED_STAT2_DEFAULT 0x00000000 +#define regCP_BUSY_STAT_DEFAULT 0x00000000 +#define regCP_STAT_DEFAULT 0x00000000 +#define regCP_ME_HEADER_DUMP_DEFAULT 0xdef0def0 +#define regCP_PFP_HEADER_DUMP_DEFAULT 0xdef0def0 +#define regCP_GRBM_FREE_COUNT_DEFAULT 0x000c0c0c +#define regCP_PFP_INSTR_PNTR_DEFAULT 0x00000000 +#define regCP_ME_INSTR_PNTR_DEFAULT 0x00000000 +#define regCP_MEC1_INSTR_PNTR_DEFAULT 0x00000000 +#define regCP_MEC2_INSTR_PNTR_DEFAULT 0x00000000 +#define regCP_CSF_STAT_DEFAULT 0x00000000 +#define regCP_CNTX_STAT_DEFAULT 0x00000000 +#define regCP_ME_PREEMPTION_DEFAULT 0x00000000 +#define regCP_RB1_RPTR_DEFAULT 0x00000000 +#define regCP_RB0_RPTR_DEFAULT 0x00000000 +#define regCP_RB_RPTR_DEFAULT 0x00000000 +#define regCP_RB_WPTR_DELAY_DEFAULT 0x00000000 +#define regCP_RB_WPTR_POLL_CNTL_DEFAULT 0x00400000 +#define regCP_ROQ1_THRESHOLDS_DEFAULT 0x06008010 +#define regCP_ROQ2_THRESHOLDS_DEFAULT 0x000380a0 +#define regCP_STQ_THRESHOLDS_DEFAULT 0x00804000 +#define regCP_MEQ_THRESHOLDS_DEFAULT 0x00008040 +#define regCP_ROQ_AVAIL_DEFAULT 0x02000080 +#define regCP_STQ_AVAIL_DEFAULT 0x00000000 +#define regCP_ROQ2_AVAIL_DEFAULT 0x00800200 +#define regCP_MEQ_AVAIL_DEFAULT 0x00000200 +#define regCP_CMD_INDEX_DEFAULT 0x00000000 +#define regCP_CMD_DATA_DEFAULT 0x00000000 +#define regCP_ROQ_RB_STAT_DEFAULT 0x00000000 +#define regCP_ROQ_IB1_STAT_DEFAULT 0x01600160 +#define regCP_ROQ_IB2_STAT_DEFAULT 0x05000500 +#define regCP_STQ_STAT_DEFAULT 0x00000000 +#define regCP_STQ_WR_STAT_DEFAULT 0x00000000 +#define regCP_MEQ_STAT_DEFAULT 0x00000000 +#define regCP_ROQ3_THRESHOLDS_DEFAULT 0x00050120 +#define regCP_ROQ_DB_STAT_DEFAULT 0x09000900 +#define regCP_DEBUG_CNTL_DEFAULT 0x00000000 +#define regCP_DEBUG_DATA_DEFAULT 0x00000000 +#define regCP_PRIV_VIOLATION_ADDR_DEFAULT 0x00000000 + + +// addressBlock: gc_padec +#define regVGT_DMA_DATA_FIFO_DEPTH_DEFAULT 0x00000200 +#define regVGT_DMA_REQ_FIFO_DEPTH_DEFAULT 0x00000020 +#define regVGT_DRAW_INIT_FIFO_DEPTH_DEFAULT 0x00000020 +#define regVGT_MC_LAT_CNTL_DEFAULT 0x00000002 +#define regIA_UTCL1_STATUS_2_DEFAULT 0x00000000 +#define regWD_CNTL_STATUS_DEFAULT 0x00000000 +#define regCC_GC_PRIM_CONFIG_DEFAULT 0x000faaa0 +#define regWD_QOS_DEFAULT 0x00000000 +#define regWD_UTCL1_CNTL_DEFAULT 0x00000080 +#define regWD_UTCL1_STATUS_DEFAULT 0x00000000 +#define regIA_UTCL1_CNTL_DEFAULT 0x00000080 +#define regIA_UTCL1_STATUS_DEFAULT 0x00000000 +#define regCC_GC_SA_UNIT_DISABLE_DEFAULT 0x00f00000 +#define regGE_RATE_CNTL_1_DEFAULT 0x10101010 +#define regGE_RATE_CNTL_2_DEFAULT 0x00001010 +#define regVGT_SYS_CONFIG_DEFAULT 0x00000011 +#define regGE_PRIV_CONTROL_DEFAULT 0x000001fe +#define regGE_STATUS_DEFAULT 0x00000000 +#define regVGT_GS_MAX_WAVE_ID_DEFAULT 0x00000bff +#define regGFX_PIPE_CONTROL_DEFAULT 0x00000000 +#define regCC_GC_SHADER_ARRAY_CONFIG_DEFAULT 0xfff00000 +#define regGE2_SE_CNTL_STATUS_DEFAULT 0x00000000 +#define regGE_SPI_IF_SAFE_REG_DEFAULT 0x00020db6 +#define regGE_PA_IF_SAFE_REG_DEFAULT 0x0000dc37 +#define regPA_CL_CNTL_STATUS_DEFAULT 0x00000000 +#define regPA_CL_ENHANCE_DEFAULT 0x00080007 +#define regPA_SU_CNTL_STATUS_DEFAULT 0x00000000 +#define regPA_SC_FIFO_DEPTH_CNTL_DEFAULT 0x00000034 + + +// addressBlock: gc_sqdec +#define regSQ_CONFIG_DEFAULT 0x00180000 +#define regSQC_CONFIG_DEFAULT 0x00028800 +#define regLDS_CONFIG_DEFAULT 0x00000000 +#define regSQ_RANDOM_WAVE_PRI_DEFAULT 0x0000007f +#define regSQG_STATUS_DEFAULT 0x00000000 +#define regSQ_FIFO_SIZES_DEFAULT 0x0000d001 +#define regSQ_DSM_CNTL_DEFAULT 0x00000000 +#define regSQ_DSM_CNTL2_DEFAULT 0x00000000 +#define regSP_CONFIG_DEFAULT 0x00000010 +#define regSQ_ARB_CONFIG_DEFAULT 0x00000030 +#define regSQ_DEBUG_HOST_TRAP_STATUS_DEFAULT 0x00000000 +#define regSQG_GL1H_STATUS_DEFAULT 0x00000000 +#define regSQG_CONFIG_DEFAULT 0x00002000 +#define regSQ_PERF_SNAPSHOT_CTRL_DEFAULT 0x0001fffe +#define regCC_GC_SHADER_RATE_CONFIG_DEFAULT 0x00000000 +#define regSQ_INTERRUPT_AUTO_MASK_DEFAULT 0x00ffffff +#define regSQ_INTERRUPT_MSG_CTRL_DEFAULT 0x00000000 +#define regSQ_WATCH0_ADDR_H_DEFAULT 0x00000000 +#define regSQ_WATCH0_ADDR_L_DEFAULT 0x00000000 +#define regSQ_WATCH0_CNTL_DEFAULT 0x00000000 +#define regSQ_WATCH1_ADDR_H_DEFAULT 0x00000000 +#define regSQ_WATCH1_ADDR_L_DEFAULT 0x00000000 +#define regSQ_WATCH1_CNTL_DEFAULT 0x00000000 +#define regSQ_WATCH2_ADDR_H_DEFAULT 0x00000000 +#define regSQ_WATCH2_ADDR_L_DEFAULT 0x00000000 +#define regSQ_WATCH2_CNTL_DEFAULT 0x00000000 +#define regSQ_WATCH3_ADDR_H_DEFAULT 0x00000000 +#define regSQ_WATCH3_ADDR_L_DEFAULT 0x00000000 +#define regSQ_WATCH3_CNTL_DEFAULT 0x00000000 +#define regSQ_IND_INDEX_DEFAULT 0x00000000 +#define regSQ_IND_DATA_DEFAULT 0x00000000 +#define regSQ_CMD_DEFAULT 0x00000000 + + +// addressBlock: gc_shsdec +#define regSX_DEBUG_1_DEFAULT 0x00000020 +#define regSPI_PS_MAX_WAVE_ID_DEFAULT 0x020000ff +#define regSPI_GFX_CNTL_DEFAULT 0x00000000 +#define regSPI_DSM_CNTL_DEFAULT 0x00000000 +#define regSPI_DSM_CNTL2_DEFAULT 0x00000000 +#define regSPI_EDC_CNT_DEFAULT 0x00000000 +#define regSPI_CONFIG_PS_CU_EN_DEFAULT 0x00000000 +#define regSPI_WF_LIFETIME_CNTL_DEFAULT 0x00000000 +#define regSPI_WF_LIFETIME_LIMIT_0_DEFAULT 0x00000100 +#define regSPI_WF_LIFETIME_LIMIT_1_DEFAULT 0x00000100 +#define regSPI_WF_LIFETIME_LIMIT_2_DEFAULT 0x00000100 +#define regSPI_WF_LIFETIME_LIMIT_3_DEFAULT 0x00000100 +#define regSPI_WF_LIFETIME_LIMIT_4_DEFAULT 0x00000100 +#define regSPI_WF_LIFETIME_LIMIT_5_DEFAULT 0x00000100 +#define regSPI_WF_LIFETIME_STATUS_0_DEFAULT 0x00000000 +#define regSPI_WF_LIFETIME_STATUS_2_DEFAULT 0x00000000 +#define regSPI_WF_LIFETIME_STATUS_4_DEFAULT 0x00000000 +#define regSPI_WF_LIFETIME_STATUS_6_DEFAULT 0x00000000 +#define regSPI_WF_LIFETIME_STATUS_7_DEFAULT 0x00000000 +#define regSPI_WF_LIFETIME_STATUS_9_DEFAULT 0x00000000 +#define regSPI_WF_LIFETIME_STATUS_11_DEFAULT 0x00000000 +#define regSPI_WF_LIFETIME_STATUS_13_DEFAULT 0x00000000 +#define regSPI_WF_LIFETIME_STATUS_14_DEFAULT 0x00000000 +#define regSPI_WF_LIFETIME_STATUS_15_DEFAULT 0x00000000 +#define regSPI_WF_LIFETIME_STATUS_16_DEFAULT 0x00000000 +#define regSPI_WF_LIFETIME_STATUS_17_DEFAULT 0x00000000 +#define regSPI_WF_LIFETIME_STATUS_18_DEFAULT 0x00000000 +#define regSPI_WF_LIFETIME_STATUS_19_DEFAULT 0x00000000 +#define regSPI_WF_LIFETIME_STATUS_20_DEFAULT 0x00000000 +#define regSPI_WF_LIFETIME_STATUS_21_DEFAULT 0x00000000 +#define regSPI_LB_CTR_CTRL_DEFAULT 0x00000000 +#define regSPI_LB_WGP_MASK_DEFAULT 0x0000ffff +#define regSPI_LB_DATA_REG_DEFAULT 0x00000000 +#define regSPI_PG_ENABLE_STATIC_WGP_MASK_DEFAULT 0x0000ffff +#define regSPI_GDS_CREDITS_DEFAULT 0x00004040 +#define regSPI_SX_EXPORT_BUFFER_SIZES_DEFAULT 0x10000160 +#define regSPI_SX_SCOREBOARD_BUFFER_SIZES_DEFAULT 0x00800040 +#define regSPI_CSQ_WF_ACTIVE_STATUS_DEFAULT 0x00000000 +#define regSPI_CSQ_WF_ACTIVE_COUNT_0_DEFAULT 0x00000000 +#define regSPI_CSQ_WF_ACTIVE_COUNT_1_DEFAULT 0x00000000 +#define regSPI_CSQ_WF_ACTIVE_COUNT_2_DEFAULT 0x00000000 +#define regSPI_CSQ_WF_ACTIVE_COUNT_3_DEFAULT 0x00000000 +#define regSPI_LB_DATA_WAVES_DEFAULT 0x00000000 +#define regSPI_P0_TRAP_SCREEN_PSBA_LO_DEFAULT 0x00000000 +#define regSPI_P0_TRAP_SCREEN_PSBA_HI_DEFAULT 0x00000000 +#define regSPI_P0_TRAP_SCREEN_PSMA_LO_DEFAULT 0x00000000 +#define regSPI_P0_TRAP_SCREEN_PSMA_HI_DEFAULT 0x00000000 +#define regSPI_P0_TRAP_SCREEN_GPR_MIN_DEFAULT 0x00000000 +#define regSPI_P1_TRAP_SCREEN_PSBA_LO_DEFAULT 0x00000000 +#define regSPI_P1_TRAP_SCREEN_PSBA_HI_DEFAULT 0x00000000 +#define regSPI_P1_TRAP_SCREEN_PSMA_LO_DEFAULT 0x00000000 +#define regSPI_P1_TRAP_SCREEN_PSMA_HI_DEFAULT 0x00000000 +#define regSPI_P1_TRAP_SCREEN_GPR_MIN_DEFAULT 0x00000000 + + +// addressBlock: gc_tpdec +#define regTD_STATUS_DEFAULT 0x00000000 +#define regTD_DSM_CNTL_DEFAULT 0x00000000 +#define regTD_DSM_CNTL2_DEFAULT 0x00000000 +#define regTD_SCRATCH_DEFAULT 0x00000000 +#define regTA_CNTL_DEFAULT 0xc0040000 +#define regTA_CNTL_AUX_DEFAULT 0x01030000 +#define regTA_CNTL2_DEFAULT 0x00000000 +#define regTA_STATUS_DEFAULT 0x00000000 +#define regTA_SCRATCH_DEFAULT 0x00000000 + + +// addressBlock: gc_gdsdec +#define regGDS_CONFIG_DEFAULT 0x00000000 +#define regGDS_CNTL_STATUS_DEFAULT 0x00000000 +#define regGDS_ENHANCE_DEFAULT 0x00000000 +#define regGDS_PROTECTION_FAULT_DEFAULT 0x00000000 +#define regGDS_VM_PROTECTION_FAULT_DEFAULT 0x00000000 +#define regGDS_EDC_CNT_DEFAULT 0x00000000 +#define regGDS_EDC_GRBM_CNT_DEFAULT 0x00000000 +#define regGDS_EDC_OA_DED_DEFAULT 0x00000000 +#define regGDS_DSM_CNTL_DEFAULT 0x00000000 +#define regGDS_EDC_OA_PHY_CNT_DEFAULT 0x00000000 +#define regGDS_EDC_OA_PIPE_CNT_DEFAULT 0x00000000 +#define regGDS_DSM_CNTL2_DEFAULT 0x00000000 + + +// addressBlock: gc_rbdec +#define regDB_DEBUG_DEFAULT 0x00000000 +#define regDB_DEBUG2_DEFAULT 0x00000420 +#define regDB_DEBUG3_DEFAULT 0x00000000 +#define regDB_DEBUG4_DEFAULT 0x04000000 +#define regDB_ETILE_STUTTER_CONTROL_DEFAULT 0x00000000 +#define regDB_LTILE_STUTTER_CONTROL_DEFAULT 0x00000000 +#define regDB_EQUAD_STUTTER_CONTROL_DEFAULT 0x00000000 +#define regDB_LQUAD_STUTTER_CONTROL_DEFAULT 0x00000000 +#define regDB_CREDIT_LIMIT_DEFAULT 0x00000000 +#define regDB_WATERMARKS_DEFAULT 0x0a040a05 +#define regDB_SUBTILE_CONTROL_DEFAULT 0x00000000 +#define regDB_FREE_CACHELINES_DEFAULT 0x00000000 +#define regDB_FIFO_DEPTH1_DEFAULT 0x00000000 +#define regDB_FIFO_DEPTH2_DEFAULT 0x00000000 +#define regDB_LAST_OF_BURST_CONFIG_DEFAULT 0x00c28210 +#define regDB_RING_CONTROL_DEFAULT 0x00000001 +#define regDB_MEM_ARB_WATERMARKS_DEFAULT 0x04040404 +#define regDB_FIFO_DEPTH3_DEFAULT 0x00000000 +#define regDB_DEBUG6_DEFAULT 0x00100000 +#define regDB_EXCEPTION_CONTROL_DEFAULT 0x00000000 +#define regDB_DEBUG7_DEFAULT 0x00000000 +#define regDB_DEBUG5_DEFAULT 0x00000000 +#define regDB_FGCG_SRAMS_CLK_CTRL_DEFAULT 0x00000000 +#define regDB_FGCG_INTERFACES_CLK_CTRL_DEFAULT 0x00000000 +#define regDB_FIFO_DEPTH4_DEFAULT 0x00000000 +#define regCC_RB_REDUNDANCY_DEFAULT 0x00000000 +#define regCC_RB_BACKEND_DISABLE_DEFAULT 0x00000000 +#define regGB_ADDR_CONFIG_DEFAULT 0x00000545 +#define regGB_BACKEND_MAP_DEFAULT 0x00000000 +#define regGB_GPU_ID_DEFAULT 0x00000000 +#define regCC_RB_DAISY_CHAIN_DEFAULT 0x76543210 +#define regGB_ADDR_CONFIG_READ_DEFAULT 0x00000545 +#define regCB_HW_CONTROL_4_DEFAULT 0x00001814 +#define regCB_HW_CONTROL_3_DEFAULT 0x00000000 +#define regCB_HW_CONTROL_DEFAULT 0x00000140 +#define regCB_HW_CONTROL_1_DEFAULT 0x00000000 +#define regCB_HW_CONTROL_2_DEFAULT 0x00003700 +#define regCB_DCC_CONFIG_DEFAULT 0x00000000 +#define regCB_HW_MEM_ARBITER_RD_DEFAULT 0x00002000 +#define regCB_HW_MEM_ARBITER_WR_DEFAULT 0x00002000 +#define regCB_FGCG_SRAM_OVERRIDE_DEFAULT 0x00000000 +#define regCB_DCC_CONFIG2_DEFAULT 0x00000000 +#define regCHICKEN_BITS_DEFAULT 0x00000000 +#define regCB_CACHE_EVICT_POINTS_DEFAULT 0x0410051a + + +// addressBlock: gc_gceadec2 +#define regGCEA_MISC_DEFAULT 0x0de8bff0 +#define regGCEA_LATENCY_SAMPLING_DEFAULT 0x00000000 +#define regGCEA_MAM_CTRL2_DEFAULT 0x0002ba00 +#define regGCEA_MAM_CTRL_DEFAULT 0x0000d000 +#define regGCEA_EDC_CNT_DEFAULT 0x00000000 +#define regGCEA_EDC_CNT2_DEFAULT 0x00000000 +#define regGCEA_DSM_CNTL_DEFAULT 0x00000000 +#define regGCEA_DSM_CNTLA_DEFAULT 0x00000000 +#define regGCEA_DSM_CNTLB_DEFAULT 0x00000000 +#define regGCEA_DSM_CNTL2_DEFAULT 0x00000000 +#define regGCEA_DSM_CNTL2A_DEFAULT 0x00000000 +#define regGCEA_DSM_CNTL2B_DEFAULT 0x00000000 +#define regGCEA_GL2C_XBR_CREDITS_DEFAULT 0x637f637f +#define regGCEA_GL2C_XBR_MAXBURST_DEFAULT 0x00333333 +#define regGCEA_PROBE_CNTL_DEFAULT 0x00000000 +#define regGCEA_PROBE_MAP_DEFAULT 0x0000aaaa +#define regGCEA_ERR_STATUS_DEFAULT 0x00000300 +#define regGCEA_MISC2_DEFAULT 0x00000000 + + +// addressBlock: gc_spipdec2 +#define regSPI_PQEV_CTRL_DEFAULT 0x00ff1008 +#define regSPI_EXP_THROTTLE_CTRL_DEFAULT 0x08782e2e + + +// addressBlock: gc_gceadec3 +#define regGCEA_RRET_MEM_RESERVE_DEFAULT 0x00000000 +#define regGCEA_EDC_CNT3_DEFAULT 0x00000000 +#define regGCEA_SDP_ENABLE_DEFAULT 0x00000000 + + +// addressBlock: gc_pmmdec +#define regGCR_PIO_CNTL_DEFAULT 0x80000000 +#define regGCR_PIO_DATA_DEFAULT 0x00000000 +#define regPMM_CNTL_DEFAULT 0x00000040 +#define regPMM_STATUS_DEFAULT 0x00000000 + + +// addressBlock: gc_utcl1dec +#define regUTCL1_CTRL_1_DEFAULT 0x00000000 +#define regUTCL1_ALOG_DEFAULT 0x00186482 +#define regUTCL1_STATUS_DEFAULT 0x00000000 + + +// addressBlock: gc_gcvmsharedpfdec +#define regGCMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 +#define regGCMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000 +#define regGCMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000 +#define regGCMC_VM_FB_OFFSET_DEFAULT 0x00000000 +#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 +#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 +#define regGCMC_VM_STEERING_DEFAULT 0x00000001 +#define regGCMC_MEM_POWER_LS_DEFAULT 0x00000208 +#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000 +#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x000fffff +#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START_DEFAULT 0x00000000 +#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END_DEFAULT 0x000fffff +#define regGCMC_VM_APT_CNTL_DEFAULT 0x0000000c +#define regGCMC_VM_LOCAL_FB_ADDRESS_START_DEFAULT 0x00000000 +#define regGCMC_VM_LOCAL_FB_ADDRESS_END_DEFAULT 0x000fffff +#define regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000 +#define regGCUTCL2_ICG_CTRL_DEFAULT 0x00000000 +#define regGCUTCL2_CGTT_BUSY_CTRL_DEFAULT 0x00000001 +#define regGCMC_VM_FB_NOALLOC_CNTL_DEFAULT 0x00000010 +#define regGCUTCL2_HARVEST_BYPASS_GROUPS_DEFAULT 0x00000000 +#define regGCUTCL2_GROUP_RET_FAULT_STATUS_DEFAULT 0x00000000 + + +// addressBlock: gc_gcvml2pfdec +#define regGCVM_L2_CNTL_DEFAULT 0x00080602 +#define regGCVM_L2_CNTL2_DEFAULT 0x00000000 +#define regGCVM_L2_CNTL3_DEFAULT 0x80120007 +#define regGCVM_L2_STATUS_DEFAULT 0x00000000 +#define regGCVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090 +#define regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_CNTL_DEFAULT 0x0000010f +#define regGCVM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc +#define regGCVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000 +#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff +#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff +#define regGCVM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000 +#define regGCVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000 +#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000 +#define regGCVM_L2_CNTL4_DEFAULT 0x000000c1 +#define regGCVM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000 +#define regGCVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000 +#define regGCVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000 +#define regGCVM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000 +#define regGCVM_L2_ICG_CTRL_DEFAULT 0x00000000 +#define regGCVM_L2_CNTL5_DEFAULT 0x00003fe0 +#define regGCVM_L2_GCR_CNTL_DEFAULT 0x00000000 +#define regGCVML2_WALKER_MACRO_THROTTLE_TIME_DEFAULT 0x00000000 +#define regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_DEFAULT 0x00000000 +#define regGCVML2_WALKER_MICRO_THROTTLE_TIME_DEFAULT 0x00000000 +#define regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_DEFAULT 0x00000000 +#define regGCVM_L2_CGTT_BUSY_CTRL_DEFAULT 0x00000001 +#define regGCVM_L2_PTE_CACHE_DUMP_CNTL_DEFAULT 0x00000000 +#define regGCVM_L2_PTE_CACHE_DUMP_READ_DEFAULT 0x00000000 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_DEFAULT 0x00000000 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_DEFAULT 0x00000000 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_DEFAULT 0x00000000 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_DEFAULT 0x00000000 +#define regGCVM_L2_BANK_SELECT_MASKS_DEFAULT 0x00000000 +#define regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_DEFAULT 0x00000000 +#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_DEFAULT 0x00000000 +#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_DEFAULT 0x00000000 +#define regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_DEFAULT 0x00000000 +#define regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_DEFAULT 0x00000000 + + +// addressBlock: gc_gcvmsharedvcdec +#define regGCMC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000 +#define regGCMC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000 +#define regGCMC_VM_AGP_TOP_DEFAULT 0x00000000 +#define regGCMC_VM_AGP_BOT_DEFAULT 0x00000000 +#define regGCMC_VM_AGP_BASE_DEFAULT 0x00000000 +#define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000 +#define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000 +#define regGCMC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000501 + + +// addressBlock: gc_gcvml2vcdec +#define regGCVM_CONTEXT0_CNTL_DEFAULT 0x01fffe00 +#define regGCVM_CONTEXT1_CNTL_DEFAULT 0x01fffe00 +#define regGCVM_CONTEXT2_CNTL_DEFAULT 0x01fffe00 +#define regGCVM_CONTEXT3_CNTL_DEFAULT 0x01fffe00 +#define regGCVM_CONTEXT4_CNTL_DEFAULT 0x01fffe00 +#define regGCVM_CONTEXT5_CNTL_DEFAULT 0x01fffe00 +#define regGCVM_CONTEXT6_CNTL_DEFAULT 0x01fffe00 +#define regGCVM_CONTEXT7_CNTL_DEFAULT 0x01fffe00 +#define regGCVM_CONTEXT8_CNTL_DEFAULT 0x01fffe00 +#define regGCVM_CONTEXT9_CNTL_DEFAULT 0x01fffe00 +#define regGCVM_CONTEXT10_CNTL_DEFAULT 0x01fffe00 +#define regGCVM_CONTEXT11_CNTL_DEFAULT 0x01fffe00 +#define regGCVM_CONTEXT12_CNTL_DEFAULT 0x01fffe00 +#define regGCVM_CONTEXT13_CNTL_DEFAULT 0x01fffe00 +#define regGCVM_CONTEXT14_CNTL_DEFAULT 0x01fffe00 +#define regGCVM_CONTEXT15_CNTL_DEFAULT 0x01fffe00 +#define regGCVM_CONTEXTS_DISABLE_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG0_REQ_DEFAULT 0x02f80000 +#define regGCVM_INVALIDATE_ENG1_REQ_DEFAULT 0x02f80000 +#define regGCVM_INVALIDATE_ENG2_REQ_DEFAULT 0x02f80000 +#define regGCVM_INVALIDATE_ENG3_REQ_DEFAULT 0x02f80000 +#define regGCVM_INVALIDATE_ENG4_REQ_DEFAULT 0x02f80000 +#define regGCVM_INVALIDATE_ENG5_REQ_DEFAULT 0x02f80000 +#define regGCVM_INVALIDATE_ENG6_REQ_DEFAULT 0x02f80000 +#define regGCVM_INVALIDATE_ENG7_REQ_DEFAULT 0x02f80000 +#define regGCVM_INVALIDATE_ENG8_REQ_DEFAULT 0x02f80000 +#define regGCVM_INVALIDATE_ENG9_REQ_DEFAULT 0x02f80000 +#define regGCVM_INVALIDATE_ENG10_REQ_DEFAULT 0x02f80000 +#define regGCVM_INVALIDATE_ENG11_REQ_DEFAULT 0x02f80000 +#define regGCVM_INVALIDATE_ENG12_REQ_DEFAULT 0x02f80000 +#define regGCVM_INVALIDATE_ENG13_REQ_DEFAULT 0x02f80000 +#define regGCVM_INVALIDATE_ENG14_REQ_DEFAULT 0x02f80000 +#define regGCVM_INVALIDATE_ENG15_REQ_DEFAULT 0x02f80000 +#define regGCVM_INVALIDATE_ENG16_REQ_DEFAULT 0x02f80000 +#define regGCVM_INVALIDATE_ENG17_REQ_DEFAULT 0x02f80000 +#define regGCVM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT 0x00001c80 +#define regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT 0x00001c80 +#define regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT 0x00001c80 +#define regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT 0x00001c80 +#define regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT 0x00001c80 +#define regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT 0x00001c80 +#define regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT 0x00001c80 +#define regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT 0x00001c80 +#define regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT 0x00001c80 +#define regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT 0x00001c80 +#define regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT 0x00001c80 +#define regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT 0x00001c80 +#define regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT 0x00001c80 +#define regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT 0x00001c80 +#define regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT 0x00001c80 +#define regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT 0x00001c80 +#define regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT 0x00001c80 + + +// addressBlock: gc_gceadec +#define regGCEA_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0xa9503aaa +#define regGCEA_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0xa9503aaa +#define regGCEA_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0xa9503aaa +#define regGCEA_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0xa9503aaa +#define regGCEA_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000924 +#define regGCEA_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000324 +#define regGCEA_DRAM_RD_LAZY_DEFAULT 0x78000924 +#define regGCEA_DRAM_WR_LAZY_DEFAULT 0x78000924 +#define regGCEA_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 +#define regGCEA_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 +#define regGCEA_DRAM_PAGE_BURST_DEFAULT 0x20082008 +#define regGCEA_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 +#define regGCEA_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 +#define regGCEA_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define regGCEA_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define regGCEA_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 +#define regGCEA_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 +#define regGCEA_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define regGCEA_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define regGCEA_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define regGCEA_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define regGCEA_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define regGCEA_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define regGCEA_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define regGCEA_IO_RD_CLI2GRP_MAP0_DEFAULT 0xa9503aaa +#define regGCEA_IO_RD_CLI2GRP_MAP1_DEFAULT 0xa9503aaa +#define regGCEA_IO_WR_CLI2GRP_MAP0_DEFAULT 0xa9503aaa +#define regGCEA_IO_WR_CLI2GRP_MAP1_DEFAULT 0xa9503aaa +#define regGCEA_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 +#define regGCEA_IO_WR_COMBINE_FLUSH_DEFAULT 0x00017777 +#define regGCEA_IO_GROUP_BURST_DEFAULT 0x1f031f03 +#define regGCEA_IO_RD_PRI_AGE_DEFAULT 0x00db6249 +#define regGCEA_IO_WR_PRI_AGE_DEFAULT 0x00db6249 +#define regGCEA_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define regGCEA_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define regGCEA_IO_RD_PRI_FIXED_DEFAULT 0x00000924 +#define regGCEA_IO_WR_PRI_FIXED_DEFAULT 0x00000924 +#define regGCEA_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 +#define regGCEA_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 +#define regGCEA_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define regGCEA_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define regGCEA_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define regGCEA_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define regGCEA_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define regGCEA_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define regGCEA_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define regGCEA_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define regGCEA_SDP_ARB_FINAL_DEFAULT 0x00007fff +#define regGCEA_SDP_IO_PRIORITY_DEFAULT 0x00000000 +#define regGCEA_SDP_CREDITS_DEFAULT 0x000101bf +#define regGCEA_SDP_TAG_RESERVE0_DEFAULT 0x00000000 +#define regGCEA_SDP_TAG_RESERVE1_DEFAULT 0x00000000 +#define regGCEA_SDP_VCC_RESERVE0_DEFAULT 0x00000000 +#define regGCEA_SDP_VCC_RESERVE1_DEFAULT 0x00000000 + + +// addressBlock: gc_shdec +#define regSPI_SHADER_PGM_RSRC4_PS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_CHKSUM_PS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_RSRC3_PS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_LO_PS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_HI_PS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_RSRC1_PS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_RSRC2_PS_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_0_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_1_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_2_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_3_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_4_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_5_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_6_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_7_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_8_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_9_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_10_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_11_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_12_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_13_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_14_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_15_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_16_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_17_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_18_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_19_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_20_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_21_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_22_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_23_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_24_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_25_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_26_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_27_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_28_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_29_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_30_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_PS_31_DEFAULT 0x00000000 +#define regSPI_SHADER_REQ_CTRL_PS_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_ACCUM_PS_0_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_ACCUM_PS_1_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_ACCUM_PS_2_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_ACCUM_PS_3_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_CHKSUM_GS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_RSRC4_GS_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_ADDR_LO_GS_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_ADDR_HI_GS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_LO_ES_GS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_HI_ES_GS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_RSRC3_GS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_LO_GS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_HI_GS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_RSRC1_GS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_RSRC2_GS_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_0_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_1_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_2_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_3_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_4_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_5_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_6_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_7_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_8_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_9_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_10_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_11_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_12_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_13_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_14_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_15_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_16_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_17_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_18_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_19_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_20_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_21_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_22_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_23_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_24_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_25_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_26_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_27_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_28_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_29_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_30_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_GS_31_DEFAULT 0x00000000 +#define regSPI_SHADER_GS_MESHLET_DIM_DEFAULT 0x00000000 +#define regSPI_SHADER_GS_MESHLET_EXP_ALLOC_DEFAULT 0x00000000 +#define regSPI_SHADER_REQ_CTRL_ESGS_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_ACCUM_ESGS_0_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_ACCUM_ESGS_1_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_ACCUM_ESGS_2_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_ACCUM_ESGS_3_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_LO_ES_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_HI_ES_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_CHKSUM_HS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_RSRC4_HS_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_ADDR_LO_HS_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_ADDR_HI_HS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_LO_LS_HS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_HI_LS_HS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_RSRC3_HS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_LO_HS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_HI_HS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_RSRC1_HS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_RSRC2_HS_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_0_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_1_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_2_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_3_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_4_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_5_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_6_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_7_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_8_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_9_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_10_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_11_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_12_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_13_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_14_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_15_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_16_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_17_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_18_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_19_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_20_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_21_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_22_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_23_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_24_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_25_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_26_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_27_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_28_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_29_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_30_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_DATA_HS_31_DEFAULT 0x00000000 +#define regSPI_SHADER_REQ_CTRL_LSHS_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_ACCUM_LSHS_0_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_ACCUM_LSHS_1_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_ACCUM_LSHS_2_DEFAULT 0x00000000 +#define regSPI_SHADER_USER_ACCUM_LSHS_3_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_LO_LS_DEFAULT 0x00000000 +#define regSPI_SHADER_PGM_HI_LS_DEFAULT 0x00000000 +#define regCOMPUTE_DISPATCH_INITIATOR_DEFAULT 0x00000000 +#define regCOMPUTE_DIM_X_DEFAULT 0x00000000 +#define regCOMPUTE_DIM_Y_DEFAULT 0x00000000 +#define regCOMPUTE_DIM_Z_DEFAULT 0x00000000 +#define regCOMPUTE_START_X_DEFAULT 0x00000000 +#define regCOMPUTE_START_Y_DEFAULT 0x00000000 +#define regCOMPUTE_START_Z_DEFAULT 0x00000000 +#define regCOMPUTE_NUM_THREAD_X_DEFAULT 0x00000000 +#define regCOMPUTE_NUM_THREAD_Y_DEFAULT 0x00000000 +#define regCOMPUTE_NUM_THREAD_Z_DEFAULT 0x00000000 +#define regCOMPUTE_PIPELINESTAT_ENABLE_DEFAULT 0x00000001 +#define regCOMPUTE_PERFCOUNT_ENABLE_DEFAULT 0x00000000 +#define regCOMPUTE_PGM_LO_DEFAULT 0x00000000 +#define regCOMPUTE_PGM_HI_DEFAULT 0x00000000 +#define regCOMPUTE_DISPATCH_PKT_ADDR_LO_DEFAULT 0x00000000 +#define regCOMPUTE_DISPATCH_PKT_ADDR_HI_DEFAULT 0x00000000 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_DEFAULT 0x00000000 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_DEFAULT 0x00000000 +#define regCOMPUTE_PGM_RSRC1_DEFAULT 0x00000000 +#define regCOMPUTE_PGM_RSRC2_DEFAULT 0x00000000 +#define regCOMPUTE_VMID_DEFAULT 0x00000000 +#define regCOMPUTE_RESOURCE_LIMITS_DEFAULT 0x00000000 +#define regCOMPUTE_DESTINATION_EN_SE0_DEFAULT 0x00000000 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE0_DEFAULT 0xffffffff +#define regCOMPUTE_DESTINATION_EN_SE1_DEFAULT 0x00000000 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE1_DEFAULT 0xffffffff +#define regCOMPUTE_TMPRING_SIZE_DEFAULT 0x00000000 +#define regCOMPUTE_DESTINATION_EN_SE2_DEFAULT 0x00000000 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE2_DEFAULT 0xffffffff +#define regCOMPUTE_DESTINATION_EN_SE3_DEFAULT 0x00000000 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE3_DEFAULT 0xffffffff +#define regCOMPUTE_RESTART_X_DEFAULT 0x00000000 +#define regCOMPUTE_RESTART_Y_DEFAULT 0x00000000 +#define regCOMPUTE_RESTART_Z_DEFAULT 0x00000000 +#define regCOMPUTE_THREAD_TRACE_ENABLE_DEFAULT 0x00000000 +#define regCOMPUTE_MISC_RESERVED_DEFAULT 0x00000007 +#define regCOMPUTE_DISPATCH_ID_DEFAULT 0x00000000 +#define regCOMPUTE_THREADGROUP_ID_DEFAULT 0x00000000 +#define regCOMPUTE_REQ_CTRL_DEFAULT 0x00000000 +#define regCOMPUTE_USER_ACCUM_0_DEFAULT 0x00000000 +#define regCOMPUTE_USER_ACCUM_1_DEFAULT 0x00000000 +#define regCOMPUTE_USER_ACCUM_2_DEFAULT 0x00000000 +#define regCOMPUTE_USER_ACCUM_3_DEFAULT 0x00000000 +#define regCOMPUTE_PGM_RSRC3_DEFAULT 0x00000000 +#define regCOMPUTE_DDID_INDEX_DEFAULT 0x00000000 +#define regCOMPUTE_SHADER_CHKSUM_DEFAULT 0x00000000 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE4_DEFAULT 0xffffffff +#define regCOMPUTE_STATIC_THREAD_MGMT_SE5_DEFAULT 0xffffffff +#define regCOMPUTE_STATIC_THREAD_MGMT_SE6_DEFAULT 0xffffffff +#define regCOMPUTE_STATIC_THREAD_MGMT_SE7_DEFAULT 0xffffffff +#define regCOMPUTE_DISPATCH_INTERLEAVE_DEFAULT 0x00000040 +#define regCOMPUTE_RELAUNCH_DEFAULT 0x00000000 +#define regCOMPUTE_WAVE_RESTORE_ADDR_LO_DEFAULT 0x00000000 +#define regCOMPUTE_WAVE_RESTORE_ADDR_HI_DEFAULT 0x00000000 +#define regCOMPUTE_RELAUNCH2_DEFAULT 0x00000000 +#define regCOMPUTE_USER_DATA_0_DEFAULT 0x00000000 +#define regCOMPUTE_USER_DATA_1_DEFAULT 0x00000000 +#define regCOMPUTE_USER_DATA_2_DEFAULT 0x00000000 +#define regCOMPUTE_USER_DATA_3_DEFAULT 0x00000000 +#define regCOMPUTE_USER_DATA_4_DEFAULT 0x00000000 +#define regCOMPUTE_USER_DATA_5_DEFAULT 0x00000000 +#define regCOMPUTE_USER_DATA_6_DEFAULT 0x00000000 +#define regCOMPUTE_USER_DATA_7_DEFAULT 0x00000000 +#define regCOMPUTE_USER_DATA_8_DEFAULT 0x00000000 +#define regCOMPUTE_USER_DATA_9_DEFAULT 0x00000000 +#define regCOMPUTE_USER_DATA_10_DEFAULT 0x00000000 +#define regCOMPUTE_USER_DATA_11_DEFAULT 0x00000000 +#define regCOMPUTE_USER_DATA_12_DEFAULT 0x00000000 +#define regCOMPUTE_USER_DATA_13_DEFAULT 0x00000000 +#define regCOMPUTE_USER_DATA_14_DEFAULT 0x00000000 +#define regCOMPUTE_USER_DATA_15_DEFAULT 0x00000000 +#define regCOMPUTE_DISPATCH_TUNNEL_DEFAULT 0x00000000 +#define regCOMPUTE_DISPATCH_END_DEFAULT 0x00000000 +#define regCOMPUTE_NOWHERE_DEFAULT 0x00000000 +#define regSH_RESERVED_REG0_DEFAULT 0x00000000 +#define regSH_RESERVED_REG1_DEFAULT 0x00000000 + + +// addressBlock: gc_cppdec +#define regCP_CU_MASK_ADDR_LO_DEFAULT 0x00000000 +#define regCP_CU_MASK_ADDR_HI_DEFAULT 0x00000000 +#define regCP_CU_MASK_CNTL_DEFAULT 0x00000000 +#define regCP_EOPQ_WAIT_TIME_DEFAULT 0x0000052c +#define regCP_CPC_MGCG_SYNC_CNTL_DEFAULT 0x00001020 +#define regCPC_INT_INFO_DEFAULT 0x00000000 +#define regCP_VIRT_STATUS_DEFAULT 0x00000000 +#define regCPC_INT_ADDR_DEFAULT 0x00000000 +#define regCPC_INT_PASID_DEFAULT 0x00000000 +#define regCP_GFX_ERROR_DEFAULT 0x00000000 +#define regCPG_UTCL1_CNTL_DEFAULT 0x00000080 +#define regCPC_UTCL1_CNTL_DEFAULT 0x00000080 +#define regCPF_UTCL1_CNTL_DEFAULT 0x00000080 +#define regCP_AQL_SMM_STATUS_DEFAULT 0x00000000 +#define regCP_RB0_BASE_DEFAULT 0xfedcbaef +#define regCP_RB_BASE_DEFAULT 0xfedcbaef +#define regCP_RB0_CNTL_DEFAULT 0x00a00000 +#define regCP_RB_CNTL_DEFAULT 0x00a00000 +#define regCP_RB_RPTR_WR_DEFAULT 0x00000000 +#define regCP_RB0_RPTR_ADDR_DEFAULT 0x00000000 +#define regCP_RB_RPTR_ADDR_DEFAULT 0x00000000 +#define regCP_RB0_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regCP_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regCP_RB0_BUFSZ_MASK_DEFAULT 0x00000000 +#define regCP_RB_BUFSZ_MASK_DEFAULT 0x00000000 +#define regCP_INT_CNTL_DEFAULT 0x00000000 +#define regCP_INT_STATUS_DEFAULT 0x00000000 +#define regCP_DEVICE_ID_DEFAULT 0x00000000 +#define regCP_ME0_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020 +#define regCP_RING_PRIORITY_CNTS_DEFAULT 0x08081020 +#define regCP_ME0_PIPE0_PRIORITY_DEFAULT 0x00000002 +#define regCP_RING0_PRIORITY_DEFAULT 0x00000002 +#define regCP_ME0_PIPE1_PRIORITY_DEFAULT 0x00000002 +#define regCP_RING1_PRIORITY_DEFAULT 0x00000002 +#define regCP_FATAL_ERROR_DEFAULT 0x00000000 +#define regCP_RB_VMID_DEFAULT 0x00000000 +#define regCP_ME0_PIPE0_VMID_DEFAULT 0x00000000 +#define regCP_ME0_PIPE1_VMID_DEFAULT 0x00000000 +#define regCP_RB0_WPTR_DEFAULT 0x00000000 +#define regCP_RB_WPTR_DEFAULT 0x00000000 +#define regCP_RB0_WPTR_HI_DEFAULT 0x00000000 +#define regCP_RB_WPTR_HI_DEFAULT 0x00000000 +#define regCP_RB1_WPTR_DEFAULT 0x00000000 +#define regCP_RB1_WPTR_HI_DEFAULT 0x00000000 +#define regCP_PROCESS_QUANTUM_DEFAULT 0x00000008 +#define regCP_RB_DOORBELL_RANGE_LOWER_DEFAULT 0x00000000 +#define regCP_RB_DOORBELL_RANGE_UPPER_DEFAULT 0x00000108 +#define regCP_MEC_DOORBELL_RANGE_LOWER_DEFAULT 0x00000110 +#define regCP_MEC_DOORBELL_RANGE_UPPER_DEFAULT 0x00000ffc +#define regCPG_UTCL1_ERROR_DEFAULT 0x00000000 +#define regCPC_UTCL1_ERROR_DEFAULT 0x00000000 +#define regCP_RB1_BASE_DEFAULT 0xfedcbadf +#define regCP_RB1_CNTL_DEFAULT 0x00a00000 +#define regCP_RB1_RPTR_ADDR_DEFAULT 0x00000000 +#define regCP_RB1_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regCP_RB1_BUFSZ_MASK_DEFAULT 0x00000000 +#define regCP_INT_CNTL_RING0_DEFAULT 0x00000000 +#define regCP_INT_CNTL_RING1_DEFAULT 0x00000000 +#define regCP_INT_STATUS_RING0_DEFAULT 0x00000000 +#define regCP_INT_STATUS_RING1_DEFAULT 0x00000000 +#define regCP_ME_F32_INTERRUPT_DEFAULT 0x00000000 +#define regCP_PFP_F32_INTERRUPT_DEFAULT 0x00000000 +#define regCP_MEC1_F32_INTERRUPT_DEFAULT 0x00000000 +#define regCP_MEC2_F32_INTERRUPT_DEFAULT 0x00000000 +#define regCP_PWR_CNTL_DEFAULT 0x00000000 +#define regCP_ECC_FIRSTOCCURRENCE_DEFAULT 0x00000000 +#define regCP_ECC_FIRSTOCCURRENCE_RING0_DEFAULT 0x00000000 +#define regCP_ECC_FIRSTOCCURRENCE_RING1_DEFAULT 0x00000000 +#define regGB_EDC_MODE_DEFAULT 0x00000000 +#define regCP_DEBUG_DEFAULT 0x00400000 +#define regCP_CPC_DEBUG_DEFAULT 0x00500000 +#define regCP_PQ_WPTR_POLL_CNTL_DEFAULT 0x00000001 +#define regCP_PQ_WPTR_POLL_CNTL1_DEFAULT 0x00000000 +#define regCP_ME1_PIPE0_INT_CNTL_DEFAULT 0x00000000 +#define regCP_ME1_PIPE1_INT_CNTL_DEFAULT 0x00000000 +#define regCP_ME1_PIPE2_INT_CNTL_DEFAULT 0x00000000 +#define regCP_ME1_PIPE3_INT_CNTL_DEFAULT 0x00000000 +#define regCP_ME2_PIPE0_INT_CNTL_DEFAULT 0x00000000 +#define regCP_ME2_PIPE1_INT_CNTL_DEFAULT 0x00000000 +#define regCP_ME2_PIPE2_INT_CNTL_DEFAULT 0x00000000 +#define regCP_ME2_PIPE3_INT_CNTL_DEFAULT 0x00000000 +#define regCP_ME1_PIPE0_INT_STATUS_DEFAULT 0x00000000 +#define regCP_ME1_PIPE1_INT_STATUS_DEFAULT 0x00000000 +#define regCP_ME1_PIPE2_INT_STATUS_DEFAULT 0x00000000 +#define regCP_ME1_PIPE3_INT_STATUS_DEFAULT 0x00000000 +#define regCP_ME2_PIPE0_INT_STATUS_DEFAULT 0x00000000 +#define regCP_ME2_PIPE1_INT_STATUS_DEFAULT 0x00000000 +#define regCP_ME2_PIPE2_INT_STATUS_DEFAULT 0x00000000 +#define regCP_ME2_PIPE3_INT_STATUS_DEFAULT 0x00000000 +#define regCP_GFX_QUEUE_INDEX_DEFAULT 0x00000000 +#define regCC_GC_EDC_CONFIG_DEFAULT 0x00000000 +#define regCP_ME1_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020 +#define regCP_ME1_PIPE0_PRIORITY_DEFAULT 0x00000002 +#define regCP_ME1_PIPE1_PRIORITY_DEFAULT 0x00000002 +#define regCP_ME1_PIPE2_PRIORITY_DEFAULT 0x00000002 +#define regCP_ME1_PIPE3_PRIORITY_DEFAULT 0x00000002 +#define regCP_ME2_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020 +#define regCP_ME2_PIPE0_PRIORITY_DEFAULT 0x00000002 +#define regCP_ME2_PIPE1_PRIORITY_DEFAULT 0x00000002 +#define regCP_ME2_PIPE2_PRIORITY_DEFAULT 0x00000002 +#define regCP_ME2_PIPE3_PRIORITY_DEFAULT 0x00000002 +#define regCP_PFP_PRGRM_CNTR_START_DEFAULT 0x00000000 +#define regCP_ME_PRGRM_CNTR_START_DEFAULT 0x00000000 +#define regCP_MEC1_PRGRM_CNTR_START_DEFAULT 0x00000000 +#define regCP_MEC2_PRGRM_CNTR_START_DEFAULT 0x00000000 +#define regCP_PFP_INTR_ROUTINE_START_DEFAULT 0x00000002 +#define regCP_ME_INTR_ROUTINE_START_DEFAULT 0x00000002 +#define regCP_MEC1_INTR_ROUTINE_START_DEFAULT 0x00000002 +#define regCP_MEC2_INTR_ROUTINE_START_DEFAULT 0x00000002 +#define regCP_CONTEXT_CNTL_DEFAULT 0x00750075 +#define regCP_MAX_CONTEXT_DEFAULT 0x00000007 +#define regCP_IQ_WAIT_TIME1_DEFAULT 0x40404040 +#define regCP_IQ_WAIT_TIME2_DEFAULT 0x40404040 +#define regCP_RB0_BASE_HI_DEFAULT 0x00000000 +#define regCP_RB1_BASE_HI_DEFAULT 0x00000000 +#define regCP_VMID_RESET_DEFAULT 0x00000000 +#define regCPC_INT_CNTL_DEFAULT 0x00000000 +#define regCPC_INT_STATUS_DEFAULT 0x00000000 +#define regCP_VMID_PREEMPT_DEFAULT 0x00000000 +#define regCPC_INT_CNTX_ID_DEFAULT 0x00000000 +#define regCP_PQ_STATUS_DEFAULT 0x00000000 +#define regCP_PFP_PRGRM_CNTR_START_HI_DEFAULT 0x00000000 +#define regCP_MAX_DRAW_COUNT_DEFAULT 0x00000000 +#define regCP_MEC1_F32_INT_DIS_DEFAULT 0x00000000 +#define regCP_MEC2_F32_INT_DIS_DEFAULT 0x00000000 +#define regCP_VMID_STATUS_DEFAULT 0x00000000 +#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_DEFAULT 0x00000000 +#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_DEFAULT 0x00000000 +#define regCPC_SUSPEND_CTX_SAVE_CONTROL_DEFAULT 0x00000000 +#define regCPC_SUSPEND_CNTL_STACK_OFFSET_DEFAULT 0x00000000 +#define regCPC_SUSPEND_CNTL_STACK_SIZE_DEFAULT 0x00000000 +#define regCPC_SUSPEND_WG_STATE_OFFSET_DEFAULT 0x00000000 +#define regCPC_SUSPEND_CTX_SAVE_SIZE_DEFAULT 0x00000000 +#define regCPC_OS_PIPES_DEFAULT 0x00000000 +#define regCP_SUSPEND_RESUME_REQ_DEFAULT 0x00000000 +#define regCP_SUSPEND_CNTL_DEFAULT 0x00000002 +#define regCP_IQ_WAIT_TIME3_DEFAULT 0x00000040 +#define regCPC_DDID_BASE_ADDR_LO_DEFAULT 0x00000000 +#define regCP_DDID_BASE_ADDR_LO_DEFAULT 0x00000000 +#define regCPC_DDID_BASE_ADDR_HI_DEFAULT 0x00000000 +#define regCP_DDID_BASE_ADDR_HI_DEFAULT 0x00000000 +#define regCPC_DDID_CNTL_DEFAULT 0x00000080 +#define regCP_DDID_CNTL_DEFAULT 0x00000080 +#define regCP_GFX_DDID_INFLIGHT_COUNT_DEFAULT 0x00000000 +#define regCP_GFX_DDID_WPTR_DEFAULT 0x00000000 +#define regCP_GFX_DDID_RPTR_DEFAULT 0x00000000 +#define regCP_GFX_DDID_DELTA_RPT_COUNT_DEFAULT 0x00000000 +#define regCP_GFX_HPD_STATUS0_DEFAULT 0x01000000 +#define regCP_GFX_HPD_CONTROL0_DEFAULT 0x00000001 +#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_DEFAULT 0x00000000 +#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_DEFAULT 0x00000000 +#define regCP_GFX_HPD_OSPRE_FENCE_DATA_LO_DEFAULT 0x00000000 +#define regCP_GFX_HPD_OSPRE_FENCE_DATA_HI_DEFAULT 0x00000000 +#define regCP_GFX_INDEX_MUTEX_DEFAULT 0x00000000 +#define regCP_ME_PRGRM_CNTR_START_HI_DEFAULT 0x00000000 +#define regCP_PFP_INTR_ROUTINE_START_HI_DEFAULT 0x00000002 +#define regCP_ME_INTR_ROUTINE_START_HI_DEFAULT 0x00000002 +#define regCP_GFX_MQD_BASE_ADDR_DEFAULT 0x00000000 +#define regCP_GFX_MQD_BASE_ADDR_HI_DEFAULT 0x00000000 +#define regCP_GFX_HQD_ACTIVE_DEFAULT 0x00000000 +#define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 +#define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 +#define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 +#define regCP_GFX_HQD_BASE_DEFAULT 0xfedcbaef +#define regCP_GFX_HQD_BASE_HI_DEFAULT 0x00000000 +#define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 +#define regCP_GFX_HQD_RPTR_ADDR_DEFAULT 0x00000000 +#define regCP_GFX_HQD_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define regCP_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define regCP_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 +#define regCP_GFX_HQD_OFFSET_DEFAULT 0x00000000 +#define regCP_GFX_HQD_CNTL_DEFAULT 0x00a00000 +#define regCP_GFX_HQD_CSMD_RPTR_DEFAULT 0x00000000 +#define regCP_GFX_HQD_WPTR_DEFAULT 0x00000000 +#define regCP_GFX_HQD_WPTR_HI_DEFAULT 0x00000000 +#define regCP_GFX_HQD_DEQUEUE_REQUEST_DEFAULT 0x00000000 +#define regCP_GFX_HQD_MAPPED_DEFAULT 0x00000000 +#define regCP_GFX_HQD_QUE_MGR_CONTROL_DEFAULT 0x00000000 +#define regCP_GFX_HQD_IQ_TIMER_DEFAULT 0x00000000 +#define regCP_GFX_HQD_HQ_STATUS0_DEFAULT 0x40000000 +#define regCP_GFX_HQD_HQ_CONTROL0_DEFAULT 0x00000000 +#define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 +#define regCP_HQD_GFX_CONTROL_DEFAULT 0x00000000 +#define regCP_HQD_GFX_STATUS_DEFAULT 0x00000000 +#define regCP_DMA_WATCH0_ADDR_LO_DEFAULT 0x00000000 +#define regCP_DMA_WATCH0_ADDR_HI_DEFAULT 0x00000000 +#define regCP_DMA_WATCH0_MASK_DEFAULT 0x00000000 +#define regCP_DMA_WATCH0_CNTL_DEFAULT 0x00000000 +#define regCP_DMA_WATCH1_ADDR_LO_DEFAULT 0x00000000 +#define regCP_DMA_WATCH1_ADDR_HI_DEFAULT 0x00000000 +#define regCP_DMA_WATCH1_MASK_DEFAULT 0x00000000 +#define regCP_DMA_WATCH1_CNTL_DEFAULT 0x00000000 +#define regCP_DMA_WATCH2_ADDR_LO_DEFAULT 0x00000000 +#define regCP_DMA_WATCH2_ADDR_HI_DEFAULT 0x00000000 +#define regCP_DMA_WATCH2_MASK_DEFAULT 0x00000000 +#define regCP_DMA_WATCH2_CNTL_DEFAULT 0x00000000 +#define regCP_DMA_WATCH3_ADDR_LO_DEFAULT 0x00000000 +#define regCP_DMA_WATCH3_ADDR_HI_DEFAULT 0x00000000 +#define regCP_DMA_WATCH3_MASK_DEFAULT 0x00000000 +#define regCP_DMA_WATCH3_CNTL_DEFAULT 0x00000000 +#define regCP_DMA_WATCH_STAT_ADDR_LO_DEFAULT 0x00000000 +#define regCP_DMA_WATCH_STAT_ADDR_HI_DEFAULT 0x00000000 +#define regCP_DMA_WATCH_STAT_DEFAULT 0x00000000 +#define regCP_PFP_JT_STAT_DEFAULT 0x00000000 +#define regCP_MEC_JT_STAT_DEFAULT 0x00000000 +#define regCP_CPC_BUSY_HYSTERESIS_DEFAULT 0x00002020 +#define regCP_CPF_BUSY_HYSTERESIS1_DEFAULT 0x20202020 +#define regCP_CPF_BUSY_HYSTERESIS2_DEFAULT 0x00000020 +#define regCP_CPG_BUSY_HYSTERESIS1_DEFAULT 0x20202020 +#define regCP_CPG_BUSY_HYSTERESIS2_DEFAULT 0x00101020 +#define regCP_RB_DOORBELL_CLEAR_DEFAULT 0x00000000 +#define regCP_RB0_ACTIVE_DEFAULT 0x00000000 +#define regCP_RB_ACTIVE_DEFAULT 0x00000000 +#define regCP_RB1_ACTIVE_DEFAULT 0x00000000 +#define regCP_RB_STATUS_DEFAULT 0x00000000 +#define regCPG_RCIU_CAM_INDEX_DEFAULT 0x00000000 +#define regCPG_RCIU_CAM_DATA_DEFAULT 0x00000000 +#define regCPG_RCIU_CAM_DATA_PHASE0_DEFAULT 0x00000000 +#define regCPG_RCIU_CAM_DATA_PHASE1_DEFAULT 0x00000000 +#define regCPG_RCIU_CAM_DATA_PHASE2_DEFAULT 0x00000000 +#define regCP_GPU_TIMESTAMP_OFFSET_LO_DEFAULT 0x00000000 +#define regCP_GPU_TIMESTAMP_OFFSET_HI_DEFAULT 0x00000000 +#define regCP_SDMA_DMA_DONE_DEFAULT 0x00000000 +#define regCP_PFP_SDMA_CS_DEFAULT 0x00000000 +#define regCP_ME_SDMA_CS_DEFAULT 0x00000000 +#define regCPF_GCR_CNTL_DEFAULT 0x0000c000 +#define regCPG_UTCL1_STATUS_DEFAULT 0x00000000 +#define regCPC_UTCL1_STATUS_DEFAULT 0x00000000 +#define regCPF_UTCL1_STATUS_DEFAULT 0x00000000 +#define regCP_SD_CNTL_DEFAULT 0x0000046f +#define regCP_SOFT_RESET_CNTL_DEFAULT 0x00000000 +#define regCP_CPC_GFX_CNTL_DEFAULT 0x00000000 + + +// addressBlock: gc_spipdec +#define regSPI_ARB_PRIORITY_DEFAULT 0x00000000 +#define regSPI_ARB_CYCLES_0_DEFAULT 0x00000000 +#define regSPI_ARB_CYCLES_1_DEFAULT 0x00000000 +#define regSPI_WCL_PIPE_PERCENT_GFX_DEFAULT 0x07c1f07f +#define regSPI_WCL_PIPE_PERCENT_HP3D_DEFAULT 0x07c1f07f +#define regSPI_WCL_PIPE_PERCENT_CS0_DEFAULT 0x0000007f +#define regSPI_WCL_PIPE_PERCENT_CS1_DEFAULT 0x0000007f +#define regSPI_WCL_PIPE_PERCENT_CS2_DEFAULT 0x0000007f +#define regSPI_WCL_PIPE_PERCENT_CS3_DEFAULT 0x0000007f +#define regSPI_WCL_PIPE_PERCENT_CS4_DEFAULT 0x0000007f +#define regSPI_WCL_PIPE_PERCENT_CS5_DEFAULT 0x0000007f +#define regSPI_WCL_PIPE_PERCENT_CS6_DEFAULT 0x0000007f +#define regSPI_WCL_PIPE_PERCENT_CS7_DEFAULT 0x0000007f +#define regSPI_USER_ACCUM_VMID_CNTL_DEFAULT 0x00000000 +#define regSPI_GDBG_PER_VMID_CNTL_DEFAULT 0x00000000 +#define regSPI_COMPUTE_QUEUE_RESET_DEFAULT 0x00000000 +#define regSPI_COMPUTE_WF_CTX_SAVE_DEFAULT 0x00000000 + + +// addressBlock: gc_cpphqddec +#define regCP_HPD_UTCL1_CNTL_DEFAULT 0x00000000 +#define regCP_HPD_UTCL1_ERROR_DEFAULT 0x00000000 +#define regCP_HPD_UTCL1_ERROR_ADDR_DEFAULT 0x00000000 +#define regCP_MQD_BASE_ADDR_DEFAULT 0x00000000 +#define regCP_MQD_BASE_ADDR_HI_DEFAULT 0x00000000 +#define regCP_HQD_ACTIVE_DEFAULT 0x00000000 +#define regCP_HQD_VMID_DEFAULT 0x00000000 +#define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 +#define regCP_HQD_PIPE_PRIORITY_DEFAULT 0x00000000 +#define regCP_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 +#define regCP_HQD_QUANTUM_DEFAULT 0x00000000 +#define regCP_HQD_PQ_BASE_DEFAULT 0x00000000 +#define regCP_HQD_PQ_BASE_HI_DEFAULT 0x00000000 +#define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR_DEFAULT 0x00000000 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_DEFAULT 0x00000000 +#define regCP_HQD_PQ_WPTR_POLL_ADDR_DEFAULT 0x00000000 +#define regCP_HQD_PQ_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 +#define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 +#define regCP_HQD_IB_BASE_ADDR_DEFAULT 0x00000000 +#define regCP_HQD_IB_BASE_ADDR_HI_DEFAULT 0x00000000 +#define regCP_HQD_IB_RPTR_DEFAULT 0x00000000 +#define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 +#define regCP_HQD_IQ_TIMER_DEFAULT 0x00000000 +#define regCP_HQD_IQ_RPTR_DEFAULT 0x00000000 +#define regCP_HQD_DEQUEUE_REQUEST_DEFAULT 0x00000000 +#define regCP_HQD_DMA_OFFLOAD_DEFAULT 0x00000000 +#define regCP_HQD_OFFLOAD_DEFAULT 0x00000000 +#define regCP_HQD_SEMA_CMD_DEFAULT 0x00000000 +#define regCP_HQD_MSG_TYPE_DEFAULT 0x00000000 +#define regCP_HQD_ATOMIC0_PREOP_LO_DEFAULT 0x00000000 +#define regCP_HQD_ATOMIC0_PREOP_HI_DEFAULT 0x00000000 +#define regCP_HQD_ATOMIC1_PREOP_LO_DEFAULT 0x00000000 +#define regCP_HQD_ATOMIC1_PREOP_HI_DEFAULT 0x00000000 +#define regCP_HQD_HQ_SCHEDULER0_DEFAULT 0x40000000 +#define regCP_HQD_HQ_STATUS0_DEFAULT 0x40000000 +#define regCP_HQD_HQ_CONTROL0_DEFAULT 0x00000000 +#define regCP_HQD_HQ_SCHEDULER1_DEFAULT 0x00000000 +#define regCP_MQD_CONTROL_DEFAULT 0x00000100 +#define regCP_HQD_HQ_STATUS1_DEFAULT 0x00000000 +#define regCP_HQD_HQ_CONTROL1_DEFAULT 0x00000000 +#define regCP_HQD_EOP_BASE_ADDR_DEFAULT 0x00000000 +#define regCP_HQD_EOP_BASE_ADDR_HI_DEFAULT 0x00000000 +#define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 +#define regCP_HQD_EOP_RPTR_DEFAULT 0x40000000 +#define regCP_HQD_EOP_WPTR_DEFAULT 0x00008000 +#define regCP_HQD_EOP_EVENTS_DEFAULT 0x00000000 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_LO_DEFAULT 0x00000000 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_HI_DEFAULT 0x00000000 +#define regCP_HQD_CTX_SAVE_CONTROL_DEFAULT 0x00000000 +#define regCP_HQD_CNTL_STACK_OFFSET_DEFAULT 0x00000000 +#define regCP_HQD_CNTL_STACK_SIZE_DEFAULT 0x00000000 +#define regCP_HQD_WG_STATE_OFFSET_DEFAULT 0x00000000 +#define regCP_HQD_CTX_SAVE_SIZE_DEFAULT 0x00000000 +#define regCP_HQD_GDS_RESOURCE_STATE_DEFAULT 0x00000000 +#define regCP_HQD_ERROR_DEFAULT 0x00000000 +#define regCP_HQD_EOP_WPTR_MEM_DEFAULT 0x00000000 +#define regCP_HQD_AQL_CONTROL_DEFAULT 0x00000000 +#define regCP_HQD_PQ_WPTR_LO_DEFAULT 0x00000000 +#define regCP_HQD_PQ_WPTR_HI_DEFAULT 0x00000000 +#define regCP_HQD_SUSPEND_CNTL_STACK_OFFSET_DEFAULT 0x00000000 +#define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_DEFAULT 0x00000000 +#define regCP_HQD_SUSPEND_WG_STATE_OFFSET_DEFAULT 0x00000000 +#define regCP_HQD_DDID_RPTR_DEFAULT 0x00000000 +#define regCP_HQD_DDID_WPTR_DEFAULT 0x00000000 +#define regCP_HQD_DDID_INFLIGHT_COUNT_DEFAULT 0x00000000 +#define regCP_HQD_DDID_DELTA_RPT_COUNT_DEFAULT 0x00000000 +#define regCP_HQD_DEQUEUE_STATUS_DEFAULT 0x00000000 + + +// addressBlock: gc_tcpdec +#define regTCP_WATCH0_ADDR_H_DEFAULT 0x00000000 +#define regTCP_WATCH0_ADDR_L_DEFAULT 0x00000000 +#define regTCP_WATCH0_CNTL_DEFAULT 0x00000000 +#define regTCP_WATCH1_ADDR_H_DEFAULT 0x00000000 +#define regTCP_WATCH1_ADDR_L_DEFAULT 0x00000000 +#define regTCP_WATCH1_CNTL_DEFAULT 0x00000000 +#define regTCP_WATCH2_ADDR_H_DEFAULT 0x00000000 +#define regTCP_WATCH2_ADDR_L_DEFAULT 0x00000000 +#define regTCP_WATCH2_CNTL_DEFAULT 0x00000000 +#define regTCP_WATCH3_ADDR_H_DEFAULT 0x00000000 +#define regTCP_WATCH3_ADDR_L_DEFAULT 0x00000000 +#define regTCP_WATCH3_CNTL_DEFAULT 0x00000000 + + +// addressBlock: gc_gdspdec +#define regGDS_VMID0_BASE_DEFAULT 0x00000000 +#define regGDS_VMID0_SIZE_DEFAULT 0x00001000 +#define regGDS_VMID1_BASE_DEFAULT 0x00000000 +#define regGDS_VMID1_SIZE_DEFAULT 0x00001000 +#define regGDS_VMID2_BASE_DEFAULT 0x00000000 +#define regGDS_VMID2_SIZE_DEFAULT 0x00001000 +#define regGDS_VMID3_BASE_DEFAULT 0x00000000 +#define regGDS_VMID3_SIZE_DEFAULT 0x00001000 +#define regGDS_VMID4_BASE_DEFAULT 0x00000000 +#define regGDS_VMID4_SIZE_DEFAULT 0x00001000 +#define regGDS_VMID5_BASE_DEFAULT 0x00000000 +#define regGDS_VMID5_SIZE_DEFAULT 0x00001000 +#define regGDS_VMID6_BASE_DEFAULT 0x00000000 +#define regGDS_VMID6_SIZE_DEFAULT 0x00001000 +#define regGDS_VMID7_BASE_DEFAULT 0x00000000 +#define regGDS_VMID7_SIZE_DEFAULT 0x00001000 +#define regGDS_VMID8_BASE_DEFAULT 0x00000000 +#define regGDS_VMID8_SIZE_DEFAULT 0x00001000 +#define regGDS_VMID9_BASE_DEFAULT 0x00000000 +#define regGDS_VMID9_SIZE_DEFAULT 0x00001000 +#define regGDS_VMID10_BASE_DEFAULT 0x00000000 +#define regGDS_VMID10_SIZE_DEFAULT 0x00001000 +#define regGDS_VMID11_BASE_DEFAULT 0x00000000 +#define regGDS_VMID11_SIZE_DEFAULT 0x00001000 +#define regGDS_VMID12_BASE_DEFAULT 0x00000000 +#define regGDS_VMID12_SIZE_DEFAULT 0x00001000 +#define regGDS_VMID13_BASE_DEFAULT 0x00000000 +#define regGDS_VMID13_SIZE_DEFAULT 0x00001000 +#define regGDS_VMID14_BASE_DEFAULT 0x00000000 +#define regGDS_VMID14_SIZE_DEFAULT 0x00001000 +#define regGDS_VMID15_BASE_DEFAULT 0x00000000 +#define regGDS_VMID15_SIZE_DEFAULT 0x00001000 +#define regGDS_GWS_VMID0_DEFAULT 0x00400000 +#define regGDS_GWS_VMID1_DEFAULT 0x00400000 +#define regGDS_GWS_VMID2_DEFAULT 0x00400000 +#define regGDS_GWS_VMID3_DEFAULT 0x00400000 +#define regGDS_GWS_VMID4_DEFAULT 0x00400000 +#define regGDS_GWS_VMID5_DEFAULT 0x00400000 +#define regGDS_GWS_VMID6_DEFAULT 0x00400000 +#define regGDS_GWS_VMID7_DEFAULT 0x00400000 +#define regGDS_GWS_VMID8_DEFAULT 0x00400000 +#define regGDS_GWS_VMID9_DEFAULT 0x00400000 +#define regGDS_GWS_VMID10_DEFAULT 0x00400000 +#define regGDS_GWS_VMID11_DEFAULT 0x00400000 +#define regGDS_GWS_VMID12_DEFAULT 0x00400000 +#define regGDS_GWS_VMID13_DEFAULT 0x00400000 +#define regGDS_GWS_VMID14_DEFAULT 0x00400000 +#define regGDS_GWS_VMID15_DEFAULT 0x00400000 +#define regGDS_OA_VMID0_DEFAULT 0x00000000 +#define regGDS_OA_VMID1_DEFAULT 0x00000000 +#define regGDS_OA_VMID2_DEFAULT 0x00000000 +#define regGDS_OA_VMID3_DEFAULT 0x00000000 +#define regGDS_OA_VMID4_DEFAULT 0x00000000 +#define regGDS_OA_VMID5_DEFAULT 0x00000000 +#define regGDS_OA_VMID6_DEFAULT 0x00000000 +#define regGDS_OA_VMID7_DEFAULT 0x00000000 +#define regGDS_OA_VMID8_DEFAULT 0x00000000 +#define regGDS_OA_VMID9_DEFAULT 0x00000000 +#define regGDS_OA_VMID10_DEFAULT 0x00000000 +#define regGDS_OA_VMID11_DEFAULT 0x00000000 +#define regGDS_OA_VMID12_DEFAULT 0x00000000 +#define regGDS_OA_VMID13_DEFAULT 0x00000000 +#define regGDS_OA_VMID14_DEFAULT 0x00000000 +#define regGDS_OA_VMID15_DEFAULT 0x00000000 +#define regGDS_GWS_RESET0_DEFAULT 0x00000000 +#define regGDS_GWS_RESET1_DEFAULT 0x00000000 +#define regGDS_GWS_RESOURCE_RESET_DEFAULT 0x00000000 +#define regGDS_COMPUTE_MAX_WAVE_ID_DEFAULT 0x00000bff +#define regGDS_OA_RESET_MASK_DEFAULT 0x00000000 +#define regGDS_OA_RESET_DEFAULT 0x00000000 +#define regGDS_CS_CTXSW_STATUS_DEFAULT 0x00000000 +#define regGDS_CS_CTXSW_CNT0_DEFAULT 0x00000000 +#define regGDS_CS_CTXSW_CNT1_DEFAULT 0x00000000 +#define regGDS_CS_CTXSW_CNT2_DEFAULT 0x00000000 +#define regGDS_CS_CTXSW_CNT3_DEFAULT 0x00000000 +#define regGDS_GFX_CTXSW_STATUS_DEFAULT 0x00000000 +#define regGDS_PS_CTXSW_CNT0_DEFAULT 0x00000000 +#define regGDS_PS_CTXSW_CNT1_DEFAULT 0x00000000 +#define regGDS_PS_CTXSW_CNT2_DEFAULT 0x00000000 +#define regGDS_PS_CTXSW_CNT3_DEFAULT 0x00000000 +#define regGDS_PS_CTXSW_IDX_DEFAULT 0x00000000 +#define regGDS_GS_CTXSW_CNT0_DEFAULT 0x00000000 +#define regGDS_GS_CTXSW_CNT1_DEFAULT 0x00000000 +#define regGDS_GS_CTXSW_CNT2_DEFAULT 0x00000000 +#define regGDS_GS_CTXSW_CNT3_DEFAULT 0x00000000 +#define regGDS_MEMORY_CLEAN_DEFAULT 0x00000000 + + +// addressBlock: gc_gfxdec0 +#define regDB_RENDER_CONTROL_DEFAULT 0x00000000 +#define regDB_COUNT_CONTROL_DEFAULT 0x00000000 +#define regDB_DEPTH_VIEW_DEFAULT 0x00000000 +#define regDB_RENDER_OVERRIDE_DEFAULT 0x00000000 +#define regDB_RENDER_OVERRIDE2_DEFAULT 0x00000000 +#define regDB_HTILE_DATA_BASE_DEFAULT 0x00000000 +#define regDB_DEPTH_SIZE_XY_DEFAULT 0x00000000 +#define regDB_DEPTH_BOUNDS_MIN_DEFAULT 0x00000000 +#define regDB_DEPTH_BOUNDS_MAX_DEFAULT 0x00000000 +#define regDB_STENCIL_CLEAR_DEFAULT 0x00000000 +#define regDB_DEPTH_CLEAR_DEFAULT 0x00000000 +#define regPA_SC_SCREEN_SCISSOR_TL_DEFAULT 0x00000000 +#define regPA_SC_SCREEN_SCISSOR_BR_DEFAULT 0x00000000 +#define regDB_RESERVED_REG_2_DEFAULT 0x00000000 +#define regDB_Z_INFO_DEFAULT 0x00000000 +#define regDB_STENCIL_INFO_DEFAULT 0x00000000 +#define regDB_Z_READ_BASE_DEFAULT 0x00000000 +#define regDB_STENCIL_READ_BASE_DEFAULT 0x00000000 +#define regDB_Z_WRITE_BASE_DEFAULT 0x00000000 +#define regDB_STENCIL_WRITE_BASE_DEFAULT 0x00000000 +#define regDB_RESERVED_REG_1_DEFAULT 0x00000000 +#define regDB_RESERVED_REG_3_DEFAULT 0x00000000 +#define regDB_Z_READ_BASE_HI_DEFAULT 0x00000000 +#define regDB_STENCIL_READ_BASE_HI_DEFAULT 0x00000000 +#define regDB_Z_WRITE_BASE_HI_DEFAULT 0x00000000 +#define regDB_STENCIL_WRITE_BASE_HI_DEFAULT 0x00000000 +#define regDB_HTILE_DATA_BASE_HI_DEFAULT 0x00000000 +#define regDB_RMI_L2_CACHE_CONTROL_DEFAULT 0x00000000 +#define regTA_BC_BASE_ADDR_DEFAULT 0x00000000 +#define regTA_BC_BASE_ADDR_HI_DEFAULT 0x00000000 +#define regCOHER_DEST_BASE_HI_0_DEFAULT 0x00000000 +#define regCOHER_DEST_BASE_HI_1_DEFAULT 0x00000000 +#define regCOHER_DEST_BASE_HI_2_DEFAULT 0x00000000 +#define regCOHER_DEST_BASE_HI_3_DEFAULT 0x00000000 +#define regCOHER_DEST_BASE_2_DEFAULT 0x00000000 +#define regCOHER_DEST_BASE_3_DEFAULT 0x00000000 +#define regPA_SC_WINDOW_OFFSET_DEFAULT 0x00000000 +#define regPA_SC_WINDOW_SCISSOR_TL_DEFAULT 0x00000000 +#define regPA_SC_WINDOW_SCISSOR_BR_DEFAULT 0x00000000 +#define regPA_SC_CLIPRECT_RULE_DEFAULT 0x00000000 +#define regPA_SC_CLIPRECT_0_TL_DEFAULT 0x00000000 +#define regPA_SC_CLIPRECT_0_BR_DEFAULT 0x00000000 +#define regPA_SC_CLIPRECT_1_TL_DEFAULT 0x00000000 +#define regPA_SC_CLIPRECT_1_BR_DEFAULT 0x00000000 +#define regPA_SC_CLIPRECT_2_TL_DEFAULT 0x00000000 +#define regPA_SC_CLIPRECT_2_BR_DEFAULT 0x00000000 +#define regPA_SC_CLIPRECT_3_TL_DEFAULT 0x00000000 +#define regPA_SC_CLIPRECT_3_BR_DEFAULT 0x00000000 +#define regPA_SC_EDGERULE_DEFAULT 0x00000000 +#define regPA_SU_HARDWARE_SCREEN_OFFSET_DEFAULT 0x00000000 +#define regCB_TARGET_MASK_DEFAULT 0x00000000 +#define regCB_SHADER_MASK_DEFAULT 0x00000000 +#define regPA_SC_GENERIC_SCISSOR_TL_DEFAULT 0x00000000 +#define regPA_SC_GENERIC_SCISSOR_BR_DEFAULT 0x00000000 +#define regCOHER_DEST_BASE_0_DEFAULT 0x00000000 +#define regCOHER_DEST_BASE_1_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_0_TL_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_0_BR_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_1_TL_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_1_BR_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_2_TL_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_2_BR_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_3_TL_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_3_BR_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_4_TL_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_4_BR_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_5_TL_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_5_BR_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_6_TL_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_6_BR_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_7_TL_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_7_BR_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_8_TL_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_8_BR_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_9_TL_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_9_BR_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_10_TL_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_10_BR_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_11_TL_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_11_BR_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_12_TL_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_12_BR_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_13_TL_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_13_BR_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_14_TL_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_14_BR_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_15_TL_DEFAULT 0x00000000 +#define regPA_SC_VPORT_SCISSOR_15_BR_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMIN_0_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMAX_0_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMIN_1_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMAX_1_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMIN_2_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMAX_2_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMIN_3_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMAX_3_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMIN_4_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMAX_4_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMIN_5_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMAX_5_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMIN_6_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMAX_6_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMIN_7_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMAX_7_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMIN_8_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMAX_8_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMIN_9_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMAX_9_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMIN_10_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMAX_10_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMIN_11_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMAX_11_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMIN_12_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMAX_12_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMIN_13_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMAX_13_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMIN_14_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMAX_14_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMIN_15_DEFAULT 0x00000000 +#define regPA_SC_VPORT_ZMAX_15_DEFAULT 0x00000000 +#define regPA_SC_RASTER_CONFIG_DEFAULT 0x2a00126a +#define regPA_SC_RASTER_CONFIG_1_DEFAULT 0x00000000 +#define regPA_SC_SCREEN_EXTENT_CONTROL_DEFAULT 0x00000000 +#define regPA_SC_TILE_STEERING_OVERRIDE_DEFAULT 0x00000000 +#define regCP_PERFMON_CNTX_CNTL_DEFAULT 0x00000000 +#define regCP_PIPEID_DEFAULT 0x00000000 +#define regCP_RINGID_DEFAULT 0x00000000 +#define regCP_VMID_DEFAULT 0x00000000 +#define regCONTEXT_RESERVED_REG0_DEFAULT 0x00000000 +#define regCONTEXT_RESERVED_REG1_DEFAULT 0x00000000 +#define regPA_SC_VRS_OVERRIDE_CNTL_DEFAULT 0x00000000 +#define regPA_SC_VRS_RATE_FEEDBACK_BASE_DEFAULT 0x00000000 +#define regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT_DEFAULT 0x00000000 +#define regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY_DEFAULT 0x00000000 +#define regPA_SC_VRS_RATE_CACHE_CNTL_DEFAULT 0x00000000 +#define regPA_SC_VRS_RATE_BASE_DEFAULT 0x00000000 +#define regPA_SC_VRS_RATE_BASE_EXT_DEFAULT 0x00000000 +#define regPA_SC_VRS_RATE_SIZE_XY_DEFAULT 0x00000000 +#define regVGT_MULTI_PRIM_IB_RESET_INDX_DEFAULT 0x00000000 +#define regCB_RMI_GL2_CACHE_CONTROL_DEFAULT 0x00000000 +#define regCB_BLEND_RED_DEFAULT 0x00000000 +#define regCB_BLEND_GREEN_DEFAULT 0x00000000 +#define regCB_BLEND_BLUE_DEFAULT 0x00000000 +#define regCB_BLEND_ALPHA_DEFAULT 0x00000000 +#define regCB_FDCC_CONTROL_DEFAULT 0x00000000 +#define regCB_COVERAGE_OUT_CONTROL_DEFAULT 0x00000000 +#define regDB_STENCIL_CONTROL_DEFAULT 0x00000000 +#define regDB_STENCILREFMASK_DEFAULT 0x00000000 +#define regDB_STENCILREFMASK_BF_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XSCALE_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XOFFSET_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YSCALE_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YOFFSET_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZSCALE_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZOFFSET_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XSCALE_1_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XOFFSET_1_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YSCALE_1_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YOFFSET_1_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZSCALE_1_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZOFFSET_1_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XSCALE_2_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XOFFSET_2_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YSCALE_2_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YOFFSET_2_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZSCALE_2_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZOFFSET_2_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XSCALE_3_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XOFFSET_3_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YSCALE_3_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YOFFSET_3_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZSCALE_3_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZOFFSET_3_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XSCALE_4_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XOFFSET_4_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YSCALE_4_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YOFFSET_4_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZSCALE_4_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZOFFSET_4_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XSCALE_5_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XOFFSET_5_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YSCALE_5_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YOFFSET_5_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZSCALE_5_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZOFFSET_5_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XSCALE_6_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XOFFSET_6_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YSCALE_6_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YOFFSET_6_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZSCALE_6_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZOFFSET_6_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XSCALE_7_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XOFFSET_7_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YSCALE_7_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YOFFSET_7_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZSCALE_7_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZOFFSET_7_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XSCALE_8_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XOFFSET_8_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YSCALE_8_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YOFFSET_8_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZSCALE_8_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZOFFSET_8_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XSCALE_9_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XOFFSET_9_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YSCALE_9_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YOFFSET_9_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZSCALE_9_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZOFFSET_9_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XSCALE_10_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XOFFSET_10_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YSCALE_10_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YOFFSET_10_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZSCALE_10_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZOFFSET_10_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XSCALE_11_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XOFFSET_11_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YSCALE_11_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YOFFSET_11_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZSCALE_11_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZOFFSET_11_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XSCALE_12_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XOFFSET_12_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YSCALE_12_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YOFFSET_12_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZSCALE_12_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZOFFSET_12_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XSCALE_13_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XOFFSET_13_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YSCALE_13_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YOFFSET_13_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZSCALE_13_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZOFFSET_13_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XSCALE_14_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XOFFSET_14_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YSCALE_14_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YOFFSET_14_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZSCALE_14_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZOFFSET_14_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XSCALE_15_DEFAULT 0x00000000 +#define regPA_CL_VPORT_XOFFSET_15_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YSCALE_15_DEFAULT 0x00000000 +#define regPA_CL_VPORT_YOFFSET_15_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZSCALE_15_DEFAULT 0x00000000 +#define regPA_CL_VPORT_ZOFFSET_15_DEFAULT 0x00000000 +#define regPA_CL_UCP_0_X_DEFAULT 0x00000000 +#define regPA_CL_UCP_0_Y_DEFAULT 0x00000000 +#define regPA_CL_UCP_0_Z_DEFAULT 0x00000000 +#define regPA_CL_UCP_0_W_DEFAULT 0x00000000 +#define regPA_CL_UCP_1_X_DEFAULT 0x00000000 +#define regPA_CL_UCP_1_Y_DEFAULT 0x00000000 +#define regPA_CL_UCP_1_Z_DEFAULT 0x00000000 +#define regPA_CL_UCP_1_W_DEFAULT 0x00000000 +#define regPA_CL_UCP_2_X_DEFAULT 0x00000000 +#define regPA_CL_UCP_2_Y_DEFAULT 0x00000000 +#define regPA_CL_UCP_2_Z_DEFAULT 0x00000000 +#define regPA_CL_UCP_2_W_DEFAULT 0x00000000 +#define regPA_CL_UCP_3_X_DEFAULT 0x00000000 +#define regPA_CL_UCP_3_Y_DEFAULT 0x00000000 +#define regPA_CL_UCP_3_Z_DEFAULT 0x00000000 +#define regPA_CL_UCP_3_W_DEFAULT 0x00000000 +#define regPA_CL_UCP_4_X_DEFAULT 0x00000000 +#define regPA_CL_UCP_4_Y_DEFAULT 0x00000000 +#define regPA_CL_UCP_4_Z_DEFAULT 0x00000000 +#define regPA_CL_UCP_4_W_DEFAULT 0x00000000 +#define regPA_CL_UCP_5_X_DEFAULT 0x00000000 +#define regPA_CL_UCP_5_Y_DEFAULT 0x00000000 +#define regPA_CL_UCP_5_Z_DEFAULT 0x00000000 +#define regPA_CL_UCP_5_W_DEFAULT 0x00000000 +#define regPA_CL_PROG_NEAR_CLIP_Z_DEFAULT 0x00000000 +#define regPA_RATE_CNTL_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_0_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_1_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_2_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_3_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_4_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_5_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_6_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_7_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_8_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_9_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_10_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_11_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_12_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_13_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_14_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_15_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_16_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_17_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_18_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_19_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_20_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_21_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_22_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_23_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_24_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_25_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_26_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_27_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_28_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_29_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_30_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_CNTL_31_DEFAULT 0x00000000 +#define regSPI_VS_OUT_CONFIG_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_ENA_DEFAULT 0x00000000 +#define regSPI_PS_INPUT_ADDR_DEFAULT 0x00000000 +#define regSPI_INTERP_CONTROL_0_DEFAULT 0x00000000 +#define regSPI_PS_IN_CONTROL_DEFAULT 0x00000000 +#define regSPI_BARYC_CNTL_DEFAULT 0x00000000 +#define regSPI_TMPRING_SIZE_DEFAULT 0x00000000 +#define regSPI_GFX_SCRATCH_BASE_LO_DEFAULT 0x00000000 +#define regSPI_GFX_SCRATCH_BASE_HI_DEFAULT 0x00000000 +#define regSPI_SHADER_IDX_FORMAT_DEFAULT 0x00000000 +#define regSPI_SHADER_POS_FORMAT_DEFAULT 0x00000000 +#define regSPI_SHADER_Z_FORMAT_DEFAULT 0x00000000 +#define regSPI_SHADER_COL_FORMAT_DEFAULT 0x00000000 +#define regSX_PS_DOWNCONVERT_CONTROL_DEFAULT 0x00000000 +#define regSX_PS_DOWNCONVERT_DEFAULT 0x00000000 +#define regSX_BLEND_OPT_EPSILON_DEFAULT 0x00000000 +#define regSX_BLEND_OPT_CONTROL_DEFAULT 0x00000000 +#define regSX_MRT0_BLEND_OPT_DEFAULT 0x00000000 +#define regSX_MRT1_BLEND_OPT_DEFAULT 0x00000000 +#define regSX_MRT2_BLEND_OPT_DEFAULT 0x00000000 +#define regSX_MRT3_BLEND_OPT_DEFAULT 0x00000000 +#define regSX_MRT4_BLEND_OPT_DEFAULT 0x00000000 +#define regSX_MRT5_BLEND_OPT_DEFAULT 0x00000000 +#define regSX_MRT6_BLEND_OPT_DEFAULT 0x00000000 +#define regSX_MRT7_BLEND_OPT_DEFAULT 0x00000000 +#define regCB_BLEND0_CONTROL_DEFAULT 0x00000000 +#define regCB_BLEND1_CONTROL_DEFAULT 0x00000000 +#define regCB_BLEND2_CONTROL_DEFAULT 0x00000000 +#define regCB_BLEND3_CONTROL_DEFAULT 0x00000000 +#define regCB_BLEND4_CONTROL_DEFAULT 0x00000000 +#define regCB_BLEND5_CONTROL_DEFAULT 0x00000000 +#define regCB_BLEND6_CONTROL_DEFAULT 0x00000000 +#define regCB_BLEND7_CONTROL_DEFAULT 0x00000000 +#define regGFX_COPY_STATE_DEFAULT 0x00000000 +#define regPA_CL_POINT_X_RAD_DEFAULT 0x00000000 +#define regPA_CL_POINT_Y_RAD_DEFAULT 0x00000000 +#define regPA_CL_POINT_SIZE_DEFAULT 0x00000000 +#define regPA_CL_POINT_CULL_RAD_DEFAULT 0x00000000 +#define regVGT_DMA_BASE_HI_DEFAULT 0x00000000 +#define regVGT_DMA_BASE_DEFAULT 0x00000000 +#define regVGT_DRAW_INITIATOR_DEFAULT 0x00000000 +#define regVGT_EVENT_ADDRESS_REG_DEFAULT 0x00000000 +#define regGE_MAX_OUTPUT_PER_SUBGROUP_DEFAULT 0x00000000 +#define regDB_DEPTH_CONTROL_DEFAULT 0x00000000 +#define regDB_EQAA_DEFAULT 0x00000000 +#define regCB_COLOR_CONTROL_DEFAULT 0x00000000 +#define regDB_SHADER_CONTROL_DEFAULT 0x00000000 +#define regPA_CL_CLIP_CNTL_DEFAULT 0x00000000 +#define regPA_SU_SC_MODE_CNTL_DEFAULT 0x00000000 +#define regPA_CL_VTE_CNTL_DEFAULT 0x00000000 +#define regPA_CL_VS_OUT_CNTL_DEFAULT 0x00000000 +#define regPA_CL_NANINF_CNTL_DEFAULT 0x00000000 +#define regPA_SU_LINE_STIPPLE_CNTL_DEFAULT 0x00000000 +#define regPA_SU_LINE_STIPPLE_SCALE_DEFAULT 0x00000000 +#define regPA_SU_PRIM_FILTER_CNTL_DEFAULT 0x00000000 +#define regPA_SU_SMALL_PRIM_FILTER_CNTL_DEFAULT 0x00000000 +#define regPA_CL_NGG_CNTL_DEFAULT 0x00000000 +#define regPA_SU_OVER_RASTERIZATION_CNTL_DEFAULT 0x00000000 +#define regPA_STEREO_CNTL_DEFAULT 0x00000000 +#define regPA_STATE_STEREO_X_DEFAULT 0x00000000 +#define regPA_CL_VRS_CNTL_DEFAULT 0x00000000 +#define regPA_SU_POINT_SIZE_DEFAULT 0x00000000 +#define regPA_SU_POINT_MINMAX_DEFAULT 0x00000000 +#define regPA_SU_LINE_CNTL_DEFAULT 0x00000000 +#define regPA_SC_LINE_STIPPLE_DEFAULT 0x00000000 +#define regVGT_HOS_MAX_TESS_LEVEL_DEFAULT 0x00000000 +#define regVGT_HOS_MIN_TESS_LEVEL_DEFAULT 0x00000000 +#define regPA_SC_MODE_CNTL_0_DEFAULT 0x00000000 +#define regPA_SC_MODE_CNTL_1_DEFAULT 0x06000000 +#define regVGT_ENHANCE_DEFAULT 0x00000000 +#define regIA_ENHANCE_DEFAULT 0x00000000 +#define regVGT_DMA_SIZE_DEFAULT 0x00000000 +#define regVGT_DMA_MAX_SIZE_DEFAULT 0x00000000 +#define regVGT_DMA_INDEX_TYPE_DEFAULT 0x00000000 +#define regWD_ENHANCE_DEFAULT 0x00000000 +#define regVGT_PRIMITIVEID_EN_DEFAULT 0x00000000 +#define regVGT_DMA_NUM_INSTANCES_DEFAULT 0x00000000 +#define regVGT_PRIMITIVEID_RESET_DEFAULT 0x00000000 +#define regVGT_EVENT_INITIATOR_DEFAULT 0x00000000 +#define regVGT_DRAW_PAYLOAD_CNTL_DEFAULT 0x00000000 +#define regVGT_ESGS_RING_ITEMSIZE_DEFAULT 0x00000000 +#define regVGT_REUSE_OFF_DEFAULT 0x00000000 +#define regDB_HTILE_SURFACE_DEFAULT 0x00000000 +#define regDB_SRESULTS_COMPARE_STATE0_DEFAULT 0x00000000 +#define regDB_SRESULTS_COMPARE_STATE1_DEFAULT 0x00000000 +#define regDB_PRELOAD_CONTROL_DEFAULT 0x00000000 +#define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_DEFAULT 0x00000000 +#define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_DEFAULT 0x00000000 +#define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_DEFAULT 0x00000000 +#define regVGT_GS_MAX_VERT_OUT_DEFAULT 0x00000000 +#define regGE_NGG_SUBGRP_CNTL_DEFAULT 0x00000000 +#define regVGT_TESS_DISTRIBUTION_DEFAULT 0x00000000 +#define regVGT_SHADER_STAGES_EN_DEFAULT 0x00000000 +#define regVGT_LS_HS_CONFIG_DEFAULT 0x00000000 +#define regVGT_TF_PARAM_DEFAULT 0x00000000 +#define regDB_ALPHA_TO_MASK_DEFAULT 0x00000000 +#define regPA_SU_POLY_OFFSET_DB_FMT_CNTL_DEFAULT 0x00000000 +#define regPA_SU_POLY_OFFSET_CLAMP_DEFAULT 0x00000000 +#define regPA_SU_POLY_OFFSET_FRONT_SCALE_DEFAULT 0x00000000 +#define regPA_SU_POLY_OFFSET_FRONT_OFFSET_DEFAULT 0x00000000 +#define regPA_SU_POLY_OFFSET_BACK_SCALE_DEFAULT 0x00000000 +#define regPA_SU_POLY_OFFSET_BACK_OFFSET_DEFAULT 0x00000000 +#define regVGT_GS_INSTANCE_CNT_DEFAULT 0x00000000 +#define regPA_SC_CENTROID_PRIORITY_0_DEFAULT 0x00000000 +#define regPA_SC_CENTROID_PRIORITY_1_DEFAULT 0x00000000 +#define regPA_SC_LINE_CNTL_DEFAULT 0x00000000 +#define regPA_SC_AA_CONFIG_DEFAULT 0x00000000 +#define regPA_SU_VTX_CNTL_DEFAULT 0x00000000 +#define regPA_CL_GB_VERT_CLIP_ADJ_DEFAULT 0x00000000 +#define regPA_CL_GB_VERT_DISC_ADJ_DEFAULT 0x00000000 +#define regPA_CL_GB_HORZ_CLIP_ADJ_DEFAULT 0x00000000 +#define regPA_CL_GB_HORZ_DISC_ADJ_DEFAULT 0x00000000 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_DEFAULT 0x00000000 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_DEFAULT 0x00000000 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_DEFAULT 0x00000000 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_DEFAULT 0x00000000 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_DEFAULT 0x00000000 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_DEFAULT 0x00000000 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_DEFAULT 0x00000000 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_DEFAULT 0x00000000 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_DEFAULT 0x00000000 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_DEFAULT 0x00000000 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_DEFAULT 0x00000000 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_DEFAULT 0x00000000 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_DEFAULT 0x00000000 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_DEFAULT 0x00000000 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_DEFAULT 0x00000000 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_DEFAULT 0x00000000 +#define regPA_SC_AA_MASK_X0Y0_X1Y0_DEFAULT 0x00000000 +#define regPA_SC_AA_MASK_X0Y1_X1Y1_DEFAULT 0x00000000 +#define regPA_SC_SHADER_CONTROL_DEFAULT 0x00000000 +#define regPA_SC_BINNER_CNTL_0_DEFAULT 0x00000000 +#define regPA_SC_BINNER_CNTL_1_DEFAULT 0x00000000 +#define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_DEFAULT 0x00000000 +#define regPA_SC_NGG_MODE_CNTL_DEFAULT 0x00000000 +#define regPA_SC_BINNER_CNTL_2_DEFAULT 0x00000000 +#define regCB_COLOR0_BASE_DEFAULT 0x00000000 +#define regCB_COLOR0_VIEW_DEFAULT 0x00000000 +#define regCB_COLOR0_INFO_DEFAULT 0x00000000 +#define regCB_COLOR0_ATTRIB_DEFAULT 0x00000000 +#define regCB_COLOR0_FDCC_CONTROL_DEFAULT 0x00000000 +#define regCB_COLOR0_DCC_BASE_DEFAULT 0x00000000 +#define regCB_COLOR1_BASE_DEFAULT 0x00000000 +#define regCB_COLOR1_VIEW_DEFAULT 0x00000000 +#define regCB_COLOR1_INFO_DEFAULT 0x00000000 +#define regCB_COLOR1_ATTRIB_DEFAULT 0x00000000 +#define regCB_COLOR1_FDCC_CONTROL_DEFAULT 0x00000000 +#define regCB_COLOR1_DCC_BASE_DEFAULT 0x00000000 +#define regCB_COLOR2_BASE_DEFAULT 0x00000000 +#define regCB_COLOR2_VIEW_DEFAULT 0x00000000 +#define regCB_COLOR2_INFO_DEFAULT 0x00000000 +#define regCB_COLOR2_ATTRIB_DEFAULT 0x00000000 +#define regCB_COLOR2_FDCC_CONTROL_DEFAULT 0x00000000 +#define regCB_COLOR2_DCC_BASE_DEFAULT 0x00000000 +#define regCB_COLOR3_BASE_DEFAULT 0x00000000 +#define regCB_COLOR3_VIEW_DEFAULT 0x00000000 +#define regCB_COLOR3_INFO_DEFAULT 0x00000000 +#define regCB_COLOR3_ATTRIB_DEFAULT 0x00000000 +#define regCB_COLOR3_FDCC_CONTROL_DEFAULT 0x00000000 +#define regCB_COLOR3_DCC_BASE_DEFAULT 0x00000000 +#define regCB_COLOR4_BASE_DEFAULT 0x00000000 +#define regCB_COLOR4_VIEW_DEFAULT 0x00000000 +#define regCB_COLOR4_INFO_DEFAULT 0x00000000 +#define regCB_COLOR4_ATTRIB_DEFAULT 0x00000000 +#define regCB_COLOR4_FDCC_CONTROL_DEFAULT 0x00000000 +#define regCB_COLOR4_DCC_BASE_DEFAULT 0x00000000 +#define regCB_COLOR5_BASE_DEFAULT 0x00000000 +#define regCB_COLOR5_VIEW_DEFAULT 0x00000000 +#define regCB_COLOR5_INFO_DEFAULT 0x00000000 +#define regCB_COLOR5_ATTRIB_DEFAULT 0x00000000 +#define regCB_COLOR5_FDCC_CONTROL_DEFAULT 0x00000000 +#define regCB_COLOR5_DCC_BASE_DEFAULT 0x00000000 +#define regCB_COLOR6_BASE_DEFAULT 0x00000000 +#define regCB_COLOR6_VIEW_DEFAULT 0x00000000 +#define regCB_COLOR6_INFO_DEFAULT 0x00000000 +#define regCB_COLOR6_ATTRIB_DEFAULT 0x00000000 +#define regCB_COLOR6_FDCC_CONTROL_DEFAULT 0x00000000 +#define regCB_COLOR6_DCC_BASE_DEFAULT 0x00000000 +#define regCB_COLOR7_BASE_DEFAULT 0x00000000 +#define regCB_COLOR7_VIEW_DEFAULT 0x00000000 +#define regCB_COLOR7_INFO_DEFAULT 0x00000000 +#define regCB_COLOR7_ATTRIB_DEFAULT 0x00000000 +#define regCB_COLOR7_FDCC_CONTROL_DEFAULT 0x00000000 +#define regCB_COLOR7_DCC_BASE_DEFAULT 0x00000000 +#define regCB_COLOR0_BASE_EXT_DEFAULT 0x00000000 +#define regCB_COLOR1_BASE_EXT_DEFAULT 0x00000000 +#define regCB_COLOR2_BASE_EXT_DEFAULT 0x00000000 +#define regCB_COLOR3_BASE_EXT_DEFAULT 0x00000000 +#define regCB_COLOR4_BASE_EXT_DEFAULT 0x00000000 +#define regCB_COLOR5_BASE_EXT_DEFAULT 0x00000000 +#define regCB_COLOR6_BASE_EXT_DEFAULT 0x00000000 +#define regCB_COLOR7_BASE_EXT_DEFAULT 0x00000000 +#define regCB_COLOR0_DCC_BASE_EXT_DEFAULT 0x00000000 +#define regCB_COLOR1_DCC_BASE_EXT_DEFAULT 0x00000000 +#define regCB_COLOR2_DCC_BASE_EXT_DEFAULT 0x00000000 +#define regCB_COLOR3_DCC_BASE_EXT_DEFAULT 0x00000000 +#define regCB_COLOR4_DCC_BASE_EXT_DEFAULT 0x00000000 +#define regCB_COLOR5_DCC_BASE_EXT_DEFAULT 0x00000000 +#define regCB_COLOR6_DCC_BASE_EXT_DEFAULT 0x00000000 +#define regCB_COLOR7_DCC_BASE_EXT_DEFAULT 0x00000000 +#define regCB_COLOR0_ATTRIB2_DEFAULT 0x00000000 +#define regCB_COLOR1_ATTRIB2_DEFAULT 0x00000000 +#define regCB_COLOR2_ATTRIB2_DEFAULT 0x00000000 +#define regCB_COLOR3_ATTRIB2_DEFAULT 0x00000000 +#define regCB_COLOR4_ATTRIB2_DEFAULT 0x00000000 +#define regCB_COLOR5_ATTRIB2_DEFAULT 0x00000000 +#define regCB_COLOR6_ATTRIB2_DEFAULT 0x00000000 +#define regCB_COLOR7_ATTRIB2_DEFAULT 0x00000000 +#define regCB_COLOR0_ATTRIB3_DEFAULT 0x00000000 +#define regCB_COLOR1_ATTRIB3_DEFAULT 0x00000000 +#define regCB_COLOR2_ATTRIB3_DEFAULT 0x00000000 +#define regCB_COLOR3_ATTRIB3_DEFAULT 0x00000000 +#define regCB_COLOR4_ATTRIB3_DEFAULT 0x00000000 +#define regCB_COLOR5_ATTRIB3_DEFAULT 0x00000000 +#define regCB_COLOR6_ATTRIB3_DEFAULT 0x00000000 +#define regCB_COLOR7_ATTRIB3_DEFAULT 0x00000000 + + +// addressBlock: gc_pfvf_cpdec +#define regCONFIG_RESERVED_REG0_DEFAULT 0x00000000 +#define regCONFIG_RESERVED_REG1_DEFAULT 0x00000000 +#define regCP_MEC_CNTL_DEFAULT 0x50000000 +#define regCP_ME_CNTL_DEFAULT 0x15000000 + + +// addressBlock: gc_pfvf_grbmdec +#define regGRBM_GFX_CNTL_DEFAULT 0x00000000 +#define regGRBM_NOWHERE_DEFAULT 0x00000000 + + +// addressBlock: gc_pfvf_padec +#define regPA_SC_VRS_SURFACE_CNTL_DEFAULT 0x42000000 +#define regPA_SC_ENHANCE_DEFAULT 0x08000009 +#define regPA_SC_ENHANCE_1_DEFAULT 0x040c2000 +#define regPA_SC_ENHANCE_2_DEFAULT 0x00000820 +#define regPA_SC_ENHANCE_3_DEFAULT 0x00000180 +#define regPA_SC_BINNER_CNTL_OVERRIDE_DEFAULT 0x08000000 +#define regPA_SC_PBB_OVERRIDE_FLAG_DEFAULT 0x00000000 +#define regPA_SC_DSM_CNTL_DEFAULT 0x00000000 +#define regPA_SC_TILE_STEERING_CREST_OVERRIDE_DEFAULT 0x00000000 +#define regPA_SC_FIFO_SIZE_DEFAULT 0x00000000 +#define regPA_SC_IF_FIFO_SIZE_DEFAULT 0x00000000 +#define regPA_SC_PACKER_WAVE_ID_CNTL_DEFAULT 0x00000000 +#define regPA_SC_ATM_CNTL_DEFAULT 0x00000000 +#define regPA_SC_PKR_WAVE_TABLE_CNTL_DEFAULT 0x00000000 +#define regPA_SC_FORCE_EOV_MAX_CNTS_DEFAULT 0x00ffffff +#define regPA_SC_BINNER_EVENT_CNTL_0_DEFAULT 0x842a4c02 +#define regPA_SC_BINNER_EVENT_CNTL_1_DEFAULT 0x82000008 +#define regPA_SC_BINNER_EVENT_CNTL_2_DEFAULT 0x1118aab8 +#define regPA_SC_BINNER_EVENT_CNTL_3_DEFAULT 0xc2400024 +#define regPA_SC_BINNER_TIMEOUT_COUNTER_DEFAULT 0x00000800 +#define regPA_SC_BINNER_PERF_CNTL_0_DEFAULT 0x00000000 +#define regPA_SC_BINNER_PERF_CNTL_1_DEFAULT 0x00000000 +#define regPA_SC_BINNER_PERF_CNTL_2_DEFAULT 0x00000000 +#define regPA_SC_BINNER_PERF_CNTL_3_DEFAULT 0x00000000 +#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000 +#define regPA_SC_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000 +#define regPA_PH_INTERFACE_FIFO_SIZE_DEFAULT 0x00000034 +#define regPA_PH_ENHANCE_DEFAULT 0x00001000 +#define regPA_SC_VRS_SURFACE_CNTL_1_DEFAULT 0x55488100 + + +// addressBlock: gc_pfvfdec_rlc +#define regRLC_SAFE_MODE_DEFAULT 0x00000000 +#define regRLC_SPM_SAMPLE_CNT_DEFAULT 0x00000000 +#define regRLC_SPM_MC_CNTL_DEFAULT 0x00000000 +#define regRLC_SPM_INT_CNTL_DEFAULT 0x00000000 +#define regRLC_SPM_INT_STATUS_DEFAULT 0x00000000 +#define regRLC_SPM_INT_INFO_1_DEFAULT 0x00000000 +#define regRLC_SPM_INT_INFO_2_DEFAULT 0x00ca0000 +#define regRLC_CSIB_ADDR_LO_DEFAULT 0x00000000 +#define regRLC_CSIB_ADDR_HI_DEFAULT 0x00000000 +#define regRLC_CSIB_LENGTH_DEFAULT 0x00000000 +#define regRLC_CP_SCHEDULERS_DEFAULT 0x00003038 +#define regRLC_CP_EOF_INT_DEFAULT 0x00000000 +#define regRLC_CP_EOF_INT_CNT_DEFAULT 0x00000000 +#define regRLC_SPARE_INT_0_DEFAULT 0x00000000 +#define regRLC_SPARE_INT_1_DEFAULT 0x00000000 +#define regRLC_SPARE_INT_2_DEFAULT 0x00000000 +#define regRLC_PACE_SPARE_INT_DEFAULT 0x00000000 +#define regRLC_PACE_SPARE_INT_1_DEFAULT 0x00000000 +#define regRLC_RLCV_SPARE_INT_1_DEFAULT 0x00000000 + + +// addressBlock: gc_pfvf_sqdec +#define regSQ_RUNTIME_CONFIG_DEFAULT 0x00000000 +#define regSQ_DEBUG_STS_GLOBAL_DEFAULT 0x00000000 +#define regSQ_DEBUG_STS_GLOBAL2_DEFAULT 0x00000000 +#define regSH_MEM_BASES_DEFAULT 0x00000000 +#define regSH_MEM_CONFIG_DEFAULT 0x0000c000 +#define regSQ_DEBUG_DEFAULT 0x00000000 +#define regSQ_SHADER_TBA_LO_DEFAULT 0x00000000 +#define regSQ_SHADER_TBA_HI_DEFAULT 0x00000000 +#define regSQ_SHADER_TMA_LO_DEFAULT 0x00000000 +#define regSQ_SHADER_TMA_HI_DEFAULT 0x00000000 + + +// addressBlock: gc_pfonly_cpdec +#define regCP_DEBUG_2_DEFAULT 0x00000000 +#define regCP_FETCHER_SOURCE_DEFAULT 0x00000000 + + +// addressBlock: gc_pfonly_cpphqddec +#define regCP_HPD_MES_ROQ_OFFSETS_DEFAULT 0x00400000 +#define regCP_HPD_ROQ_OFFSETS_DEFAULT 0x00200604 +#define regCP_HPD_STATUS0_DEFAULT 0x01000000 + + +// addressBlock: gc_rmi_rmidec +#define regRMI_GENERAL_CNTL_DEFAULT 0x01e00000 +#define regRMI_GENERAL_CNTL1_DEFAULT 0x00000201 +#define regRMI_GENERAL_STATUS_DEFAULT 0x00000000 +#define regRMI_SUBBLOCK_STATUS0_DEFAULT 0x00000000 +#define regRMI_SUBBLOCK_STATUS1_DEFAULT 0x00000000 +#define regRMI_SUBBLOCK_STATUS2_DEFAULT 0x00000000 +#define regRMI_SUBBLOCK_STATUS3_DEFAULT 0x00000000 +#define regRMI_XBAR_CONFIG_DEFAULT 0x00000000 +#define regRMI_PROBE_POP_LOGIC_CNTL_DEFAULT 0x000300c0 +#define regRMI_UTC_XNACK_N_MISC_CNTL_DEFAULT 0x00000564 +#define regRMI_DEMUX_CNTL_DEFAULT 0x02000200 +#define regRMI_UTCL1_CNTL1_DEFAULT 0x00020000 +#define regRMI_UTCL1_CNTL2_DEFAULT 0x00010000 +#define regRMI_UTC_UNIT_CONFIG_DEFAULT 0x00000000 +#define regRMI_TCIW_FORMATTER0_CNTL_DEFAULT 0x00040000 +#define regRMI_TCIW_FORMATTER1_CNTL_DEFAULT 0x4004001e +#define regRMI_SCOREBOARD_CNTL_DEFAULT 0x001ffe00 +#define regRMI_SCOREBOARD_STATUS0_DEFAULT 0x00000000 +#define regRMI_SCOREBOARD_STATUS1_DEFAULT 0x00000000 +#define regRMI_SCOREBOARD_STATUS2_DEFAULT 0x00000000 +#define regRMI_XBAR_ARBITER_CONFIG_DEFAULT 0x08000000 +#define regRMI_XBAR_ARBITER_CONFIG_1_DEFAULT 0x0000ffff +#define regRMI_CLOCK_CNTRL_DEFAULT 0x00008822 +#define regRMI_UTCL1_STATUS_DEFAULT 0x00000000 +#define regRMI_RB_GLX_CID_MAP_DEFAULT 0xbcaa9987 +#define regRMI_SPARE_DEFAULT 0xffff3100 +#define regRMI_SPARE_1_DEFAULT 0x00000a00 +#define regRMI_SPARE_2_DEFAULT 0x00000000 +#define regCC_RMI_REDUNDANCY_DEFAULT 0x00000010 + + +// addressBlock: gc_pfonly_didtdec +#define regDIDT_INDEX_AUTO_INCR_EN_DEFAULT 0x00000001 +#define regDIDT_EDC_CTRL_DEFAULT 0x00003800 +#define regDIDT_EDC_THROTTLE_CTRL_DEFAULT 0x00000010 +#define regDIDT_EDC_THRESHOLD_DEFAULT 0x00000000 +#define regDIDT_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001 +#define regDIDT_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421 +#define regDIDT_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249 +#define regDIDT_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa +#define regDIDT_EDC_STATUS_DEFAULT 0x00000000 +#define regDIDT_EDC_DYNAMIC_THRESHOLD_RO_DEFAULT 0x00000000 +#define regDIDT_EDC_OVERFLOW_DEFAULT 0x00000000 +#define regDIDT_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000 +#define regDIDT_IND_INDEX_DEFAULT 0x00000000 +#define regDIDT_IND_DATA_DEFAULT 0x00000000 + + +// addressBlock: gc_pfonly_spidec +#define regSPI_GDBG_WAVE_CNTL_DEFAULT 0x00000000 +#define regSPI_GDBG_TRAP_CONFIG_DEFAULT 0x00000000 +#define regSPI_GDBG_WAVE_CNTL3_DEFAULT 0x00000000 +#define regSPI_ARB_CNTL_0_DEFAULT 0x00000000 +#define regSPI_FEATURE_CTRL_DEFAULT 0x000013e0 +#define regSPI_SHADER_RSRC_LIMIT_CTRL_DEFAULT 0x00000000 +#define regSPI_COMPUTE_WF_CTX_SAVE_STATUS_DEFAULT 0x00000000 + + +// addressBlock: gc_pfonly_utcl1dec +#define regUTCL1_CTRL_0_DEFAULT 0x00001168 +#define regUTCL1_UTCL0_INVREQ_DISABLE_DEFAULT 0x00000000 +#define regUTCL1_CTRL_2_DEFAULT 0x0000060f +#define regUTCL1_FIFO_SIZING_DEFAULT 0x00000003 +#define regGCRD_SA0_TARGETS_DISABLE_DEFAULT 0x00000000 +#define regGCRD_SA1_TARGETS_DISABLE_DEFAULT 0x00000000 +#define regGCRD_CREDIT_SAFE_DEFAULT 0x00000044 + + +// addressBlock: gc_pfonly_pmmdec +#define regGCR_GENERAL_CNTL_DEFAULT 0x00f00400 +#define regGCR_CMD_STATUS_DEFAULT 0x00000000 +#define regGCR_SPARE_DEFAULT 0x00482d00 +#define regPMM_CNTL2_DEFAULT 0x60000000 + + +// addressBlock: gc_pfonly_tcpdec +#define regTCP_INVALIDATE_DEFAULT 0x00000000 +#define regTCP_STATUS_DEFAULT 0x00000000 +#define regTCP_CNTL2_DEFAULT 0x0000200a +#define regTCP_DEBUG_INDEX_DEFAULT 0x00000000 +#define regTCP_DEBUG_DATA_DEFAULT 0x00000000 + + +// addressBlock: gc_pfonly_gdsdec +#define regGDS_ENHANCE2_DEFAULT 0x00000000 +#define regGDS_OA_CGPG_RESTORE_DEFAULT 0x00000000 + + +// addressBlock: gc_sedcdec +#define regSEDC_GL1_GL2_OVERRIDES_DEFAULT 0x00002828 + + +// addressBlock: gc_pfonly_gccacdec +#define regGC_CAC_CTRL_1_DEFAULT 0x00000108 +#define regGC_CAC_CTRL_2_DEFAULT 0x00007fc4 +#define regGC_CAC_AGGR_LOWER_DEFAULT 0x00000000 +#define regGC_CAC_AGGR_UPPER_DEFAULT 0x00000000 +#define regSE0_CAC_AGGR_LOWER_DEFAULT 0x00000000 +#define regSE0_CAC_AGGR_UPPER_DEFAULT 0x00000000 +#define regSE1_CAC_AGGR_LOWER_DEFAULT 0x00000000 +#define regSE1_CAC_AGGR_UPPER_DEFAULT 0x00000000 +#define regSE2_CAC_AGGR_LOWER_DEFAULT 0x00000000 +#define regSE2_CAC_AGGR_UPPER_DEFAULT 0x00000000 +#define regSE3_CAC_AGGR_LOWER_DEFAULT 0x00000000 +#define regSE3_CAC_AGGR_UPPER_DEFAULT 0x00000000 +#define regSE4_CAC_AGGR_LOWER_DEFAULT 0x00000000 +#define regSE4_CAC_AGGR_UPPER_DEFAULT 0x00000000 +#define regSE5_CAC_AGGR_LOWER_DEFAULT 0x00000000 +#define regSE5_CAC_AGGR_UPPER_DEFAULT 0x00000000 +#define regGC_CAC_AGGR_GFXCLK_CYCLE_DEFAULT 0x00000000 +#define regSE0_CAC_AGGR_GFXCLK_CYCLE_DEFAULT 0x00000000 +#define regSE1_CAC_AGGR_GFXCLK_CYCLE_DEFAULT 0x00000000 +#define regSE2_CAC_AGGR_GFXCLK_CYCLE_DEFAULT 0x00000000 +#define regSE3_CAC_AGGR_GFXCLK_CYCLE_DEFAULT 0x00000000 +#define regSE4_CAC_AGGR_GFXCLK_CYCLE_DEFAULT 0x00000000 +#define regSE5_CAC_AGGR_GFXCLK_CYCLE_DEFAULT 0x00000000 +#define regGC_EDC_CTRL_DEFAULT 0x00007800 +#define regGC_EDC_THRESHOLD_DEFAULT 0x00000000 +#define regGC_EDC_STRETCH_CTRL_DEFAULT 0x00000000 +#define regGC_EDC_STRETCH_THRESHOLD_DEFAULT 0x00000000 +#define regEDC_HYSTERESIS_CNTL_DEFAULT 0x00018001 +#define regGC_THROTTLE_CTRL_DEFAULT 0x00002040 +#define regGC_THROTTLE_CTRL1_DEFAULT 0x00cc0660 +#define regPCC_STALL_PATTERN_CTRL_DEFAULT 0x07fa0401 +#define regPWRBRK_STALL_PATTERN_CTRL_DEFAULT 0x00fa0401 +#define regPCC_STALL_PATTERN_1_2_DEFAULT 0x00000000 +#define regPCC_STALL_PATTERN_3_4_DEFAULT 0x00000000 +#define regPCC_STALL_PATTERN_5_6_DEFAULT 0x00000000 +#define regPCC_STALL_PATTERN_7_DEFAULT 0x00000000 +#define regPWRBRK_STALL_PATTERN_1_2_DEFAULT 0x00000000 +#define regPWRBRK_STALL_PATTERN_3_4_DEFAULT 0x00000000 +#define regPWRBRK_STALL_PATTERN_5_6_DEFAULT 0x00000000 +#define regPWRBRK_STALL_PATTERN_7_DEFAULT 0x00000000 +#define regDIDT_STALL_PATTERN_CTRL_DEFAULT 0x000000f8 +#define regDIDT_STALL_PATTERN_1_2_DEFAULT 0x00000000 +#define regDIDT_STALL_PATTERN_3_4_DEFAULT 0x00000000 +#define regDIDT_STALL_PATTERN_5_6_DEFAULT 0x00000000 +#define regDIDT_STALL_PATTERN_7_DEFAULT 0x00000000 +#define regPCC_PWRBRK_HYSTERESIS_CTRL_DEFAULT 0x00000000 +#define regEDC_STRETCH_PERF_COUNTER_DEFAULT 0x00000000 +#define regEDC_UNSTRETCH_PERF_COUNTER_DEFAULT 0x00000000 +#define regEDC_STRETCH_NUM_PERF_COUNTER_DEFAULT 0x00000000 +#define regGC_EDC_STATUS_DEFAULT 0x00000000 +#define regGC_EDC_OVERFLOW_DEFAULT 0x00000000 +#define regGC_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000 +#define regGC_THROTTLE_STATUS_DEFAULT 0x00000000 +#define regEDC_PERF_COUNTER_DEFAULT 0x00000000 +#define regPCC_PERF_COUNTER_DEFAULT 0x00000000 +#define regPWRBRK_PERF_COUNTER_DEFAULT 0x00000000 +#define regEDC_HYSTERESIS_STAT_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_CP_0_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_CP_1_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_EA_0_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_EA_1_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_EA_2_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_0_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_1_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_2_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_3_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_4_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_UTCL2_VML2_0_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_UTCL2_VML2_1_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_UTCL2_VML2_2_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_UTCL2_WALKER_0_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_UTCL2_WALKER_1_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_UTCL2_WALKER_2_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_GDS_0_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_GDS_1_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_GDS_2_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_GE_0_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_GE_1_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_GE_2_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_GE_3_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_GE_4_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_GE_5_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_GE_6_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_PMM_0_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_GL2C_0_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_GL2C_1_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_GL2C_2_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_PH_0_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_PH_1_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_PH_2_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_PH_3_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_SDMA_0_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_SDMA_1_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_SDMA_2_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_SDMA_3_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_SDMA_4_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_SDMA_5_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_CHC_0_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_CHC_1_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_GUS_0_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_GUS_1_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_RLC_0_DEFAULT 0x00000000 +#define regGC_CAC_WEIGHT_GRBM_0_DEFAULT 0x00000000 +#define regGC_EDC_CLK_MONITOR_CTRL_DEFAULT 0x00000000 +#define regGC_CAC_IND_INDEX_DEFAULT 0x00000000 +#define regGC_CAC_IND_DATA_DEFAULT 0x00000000 +#define regSE_CAC_CTRL_1_DEFAULT 0x00000108 +#define regSE_CAC_CTRL_2_DEFAULT 0x00000008 +#define regSE_CAC_WEIGHT_TA_0_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_TD_0_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_TD_1_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_TD_2_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_TD_3_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_TD_4_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_TD_5_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_TCP_0_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_TCP_1_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_TCP_2_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_TCP_3_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_SQ_0_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_SQ_1_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_SQ_2_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_SP_0_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_SP_1_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_LDS_0_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_LDS_1_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_LDS_2_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_LDS_3_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_SQC_0_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_SQC_1_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_CU_0_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_BCI_0_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_CB_0_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_CB_1_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_CB_2_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_CB_3_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_CB_4_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_CB_5_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_CB_6_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_CB_7_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_CB_8_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_CB_9_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_CB_10_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_CB_11_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_DB_0_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_DB_1_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_DB_2_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_DB_3_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_DB_4_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_RMI_0_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_RMI_1_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_SX_0_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_SXRB_0_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_UTCL1_0_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_GL1C_0_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_GL1C_1_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_GL1C_2_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_SPI_0_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_SPI_1_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_SPI_2_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_PC_0_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_PA_0_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_PA_1_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_PA_2_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_PA_3_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_SC_0_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_SC_1_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_SC_2_DEFAULT 0x00000000 +#define regSE_CAC_WEIGHT_SC_3_DEFAULT 0x00000000 +#define regSE_CAC_WINDOW_AGGR_VALUE_DEFAULT 0x00000000 +#define regSE_CAC_WINDOW_GFXCLK_CYCLE_DEFAULT 0x00000000 +#define regSE_CAC_IND_INDEX_DEFAULT 0x00000000 +#define regSE_CAC_IND_DATA_DEFAULT 0x00000000 + + +// addressBlock: gc_pfonly2_spidec +#define regSPI_RESOURCE_RESERVE_CU_0_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_CU_1_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_CU_2_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_CU_3_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_CU_4_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_CU_5_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_CU_6_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_CU_7_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_CU_8_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_CU_9_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_CU_10_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_CU_11_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_CU_12_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_CU_13_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_CU_14_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_CU_15_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_EN_CU_0_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_EN_CU_1_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_EN_CU_2_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_EN_CU_3_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_EN_CU_4_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_EN_CU_5_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_EN_CU_6_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_EN_CU_7_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_EN_CU_8_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_EN_CU_9_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_EN_CU_10_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_EN_CU_11_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_EN_CU_12_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_EN_CU_13_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_EN_CU_14_DEFAULT 0x00000000 +#define regSPI_RESOURCE_RESERVE_EN_CU_15_DEFAULT 0x00000000 + + +// addressBlock: gc_gfxudec +#define regCP_EOP_DONE_ADDR_LO_DEFAULT 0x00000000 +#define regCP_EOP_DONE_ADDR_HI_DEFAULT 0x00000000 +#define regCP_EOP_DONE_DATA_LO_DEFAULT 0x00000000 +#define regCP_EOP_DONE_DATA_HI_DEFAULT 0x00000000 +#define regCP_EOP_LAST_FENCE_LO_DEFAULT 0x00000000 +#define regCP_EOP_LAST_FENCE_HI_DEFAULT 0x00000000 +#define regCP_PIPE_STATS_ADDR_LO_DEFAULT 0x00000000 +#define regCP_PIPE_STATS_ADDR_HI_DEFAULT 0x00000000 +#define regCP_VGT_IAVERT_COUNT_LO_DEFAULT 0x00000000 +#define regCP_VGT_IAVERT_COUNT_HI_DEFAULT 0x00000000 +#define regCP_VGT_IAPRIM_COUNT_LO_DEFAULT 0x00000000 +#define regCP_VGT_IAPRIM_COUNT_HI_DEFAULT 0x00000000 +#define regCP_VGT_GSPRIM_COUNT_LO_DEFAULT 0x00000000 +#define regCP_VGT_GSPRIM_COUNT_HI_DEFAULT 0x00000000 +#define regCP_VGT_VSINVOC_COUNT_LO_DEFAULT 0x00000000 +#define regCP_VGT_VSINVOC_COUNT_HI_DEFAULT 0x00000000 +#define regCP_VGT_GSINVOC_COUNT_LO_DEFAULT 0x00000000 +#define regCP_VGT_GSINVOC_COUNT_HI_DEFAULT 0x00000000 +#define regCP_VGT_HSINVOC_COUNT_LO_DEFAULT 0x00000000 +#define regCP_VGT_HSINVOC_COUNT_HI_DEFAULT 0x00000000 +#define regCP_VGT_DSINVOC_COUNT_LO_DEFAULT 0x00000000 +#define regCP_VGT_DSINVOC_COUNT_HI_DEFAULT 0x00000000 +#define regCP_PA_CINVOC_COUNT_LO_DEFAULT 0x00000000 +#define regCP_PA_CINVOC_COUNT_HI_DEFAULT 0x00000000 +#define regCP_PA_CPRIM_COUNT_LO_DEFAULT 0x00000000 +#define regCP_PA_CPRIM_COUNT_HI_DEFAULT 0x00000000 +#define regCP_SC_PSINVOC_COUNT0_LO_DEFAULT 0x00000000 +#define regCP_SC_PSINVOC_COUNT0_HI_DEFAULT 0x00000000 +#define regCP_SC_PSINVOC_COUNT1_LO_DEFAULT 0x00000000 +#define regCP_SC_PSINVOC_COUNT1_HI_DEFAULT 0x00000000 +#define regCP_VGT_CSINVOC_COUNT_LO_DEFAULT 0x00000000 +#define regCP_VGT_CSINVOC_COUNT_HI_DEFAULT 0x00000000 +#define regCP_VGT_ASINVOC_COUNT_LO_DEFAULT 0x00000000 +#define regCP_VGT_ASINVOC_COUNT_HI_DEFAULT 0x00000000 +#define regCP_PIPE_STATS_CONTROL_DEFAULT 0x00000000 +#define regSCRATCH_REG0_DEFAULT 0x00000000 +#define regSCRATCH_REG1_DEFAULT 0x00000000 +#define regSCRATCH_REG2_DEFAULT 0x00000000 +#define regSCRATCH_REG3_DEFAULT 0x00000000 +#define regSCRATCH_REG4_DEFAULT 0x00000000 +#define regSCRATCH_REG5_DEFAULT 0x00000000 +#define regSCRATCH_REG6_DEFAULT 0x00000000 +#define regSCRATCH_REG7_DEFAULT 0x00000000 +#define regSCRATCH_REG_ATOMIC_DEFAULT 0x00000000 +#define regSCRATCH_REG_CMPSWAP_ATOMIC_DEFAULT 0x00000000 +#define regCP_APPEND_DDID_CNT_DEFAULT 0x00000000 +#define regCP_APPEND_DATA_HI_DEFAULT 0x00000000 +#define regCP_APPEND_LAST_CS_FENCE_HI_DEFAULT 0x00000000 +#define regCP_APPEND_LAST_PS_FENCE_HI_DEFAULT 0x00000000 +#define regCP_PFP_ATOMIC_PREOP_LO_DEFAULT 0x00000000 +#define regCP_PFP_ATOMIC_PREOP_HI_DEFAULT 0x00000000 +#define regCP_PFP_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000 +#define regCP_PFP_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000 +#define regCP_PFP_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000 +#define regCP_PFP_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000 +#define regCP_APPEND_ADDR_LO_DEFAULT 0x00000000 +#define regCP_APPEND_ADDR_HI_DEFAULT 0x00000000 +#define regCP_APPEND_DATA_DEFAULT 0x00000000 +#define regCP_APPEND_DATA_LO_DEFAULT 0x00000000 +#define regCP_APPEND_LAST_CS_FENCE_DEFAULT 0x00000000 +#define regCP_APPEND_LAST_CS_FENCE_LO_DEFAULT 0x00000000 +#define regCP_APPEND_LAST_PS_FENCE_DEFAULT 0x00000000 +#define regCP_APPEND_LAST_PS_FENCE_LO_DEFAULT 0x00000000 +#define regCP_ATOMIC_PREOP_LO_DEFAULT 0x00000000 +#define regCP_ME_ATOMIC_PREOP_LO_DEFAULT 0x00000000 +#define regCP_ATOMIC_PREOP_HI_DEFAULT 0x00000000 +#define regCP_ME_ATOMIC_PREOP_HI_DEFAULT 0x00000000 +#define regCP_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000 +#define regCP_ME_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000 +#define regCP_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000 +#define regCP_ME_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000 +#define regCP_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000 +#define regCP_ME_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000 +#define regCP_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000 +#define regCP_ME_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000 +#define regCP_ME_MC_WADDR_LO_DEFAULT 0x00000000 +#define regCP_ME_MC_WADDR_HI_DEFAULT 0x00000000 +#define regCP_ME_MC_WDATA_LO_DEFAULT 0x00000000 +#define regCP_ME_MC_WDATA_HI_DEFAULT 0x00000000 +#define regCP_ME_MC_RADDR_LO_DEFAULT 0x00000000 +#define regCP_ME_MC_RADDR_HI_DEFAULT 0x80000000 +#define regCP_SEM_WAIT_TIMER_DEFAULT 0x00000000 +#define regCP_SIG_SEM_ADDR_LO_DEFAULT 0x00000000 +#define regCP_SIG_SEM_ADDR_HI_DEFAULT 0x00000000 +#define regCP_WAIT_REG_MEM_TIMEOUT_DEFAULT 0x00000000 +#define regCP_WAIT_SEM_ADDR_LO_DEFAULT 0x00000000 +#define regCP_WAIT_SEM_ADDR_HI_DEFAULT 0x00000000 +#define regCP_DMA_PFP_CONTROL_DEFAULT 0x00000000 +#define regCP_DMA_ME_CONTROL_DEFAULT 0x00000000 +#define regCP_DMA_ME_SRC_ADDR_DEFAULT 0x00000000 +#define regCP_DMA_ME_SRC_ADDR_HI_DEFAULT 0x00000000 +#define regCP_DMA_ME_DST_ADDR_DEFAULT 0x00000000 +#define regCP_DMA_ME_DST_ADDR_HI_DEFAULT 0x00000000 +#define regCP_DMA_ME_COMMAND_DEFAULT 0x00000000 +#define regCP_DMA_PFP_SRC_ADDR_DEFAULT 0x00000000 +#define regCP_DMA_PFP_SRC_ADDR_HI_DEFAULT 0x00000000 +#define regCP_DMA_PFP_DST_ADDR_DEFAULT 0x00000000 +#define regCP_DMA_PFP_DST_ADDR_HI_DEFAULT 0x00000000 +#define regCP_DMA_PFP_COMMAND_DEFAULT 0x00000000 +#define regCP_DMA_CNTL_DEFAULT 0x10100020 +#define regCP_DMA_READ_TAGS_DEFAULT 0x00000000 +#define regCP_PFP_IB_CONTROL_DEFAULT 0x00000000 +#define regCP_PFP_LOAD_CONTROL_DEFAULT 0x00000000 +#define regCP_SCRATCH_INDEX_DEFAULT 0x00000000 +#define regCP_SCRATCH_DATA_DEFAULT 0x00000000 +#define regCP_RB_OFFSET_DEFAULT 0x00000000 +#define regCP_IB2_OFFSET_DEFAULT 0x00000000 +#define regCP_IB2_PREAMBLE_BEGIN_DEFAULT 0x00000000 +#define regCP_IB2_PREAMBLE_END_DEFAULT 0x00000000 +#define regCP_DMA_ME_CMD_ADDR_LO_DEFAULT 0x00000000 +#define regCP_DMA_ME_CMD_ADDR_HI_DEFAULT 0x00000000 +#define regCP_DMA_PFP_CMD_ADDR_LO_DEFAULT 0x00000000 +#define regCP_DMA_PFP_CMD_ADDR_HI_DEFAULT 0x00000000 +#define regCP_APPEND_CMD_ADDR_LO_DEFAULT 0x00000000 +#define regCP_APPEND_CMD_ADDR_HI_DEFAULT 0x00000000 +#define regUCONFIG_RESERVED_REG0_DEFAULT 0x00000000 +#define regUCONFIG_RESERVED_REG1_DEFAULT 0x00000000 +#define regCP_PA_MSPRIM_COUNT_LO_DEFAULT 0x00000000 +#define regCP_PA_MSPRIM_COUNT_HI_DEFAULT 0x00000000 +#define regCP_GE_MSINVOC_COUNT_LO_DEFAULT 0x00000000 +#define regCP_GE_MSINVOC_COUNT_HI_DEFAULT 0x00000000 +#define regCP_IB2_CMD_BUFSZ_DEFAULT 0x00000000 +#define regCP_ST_CMD_BUFSZ_DEFAULT 0x00000000 +#define regCP_IB2_BASE_LO_DEFAULT 0x00000000 +#define regCP_IB2_BASE_HI_DEFAULT 0x00000000 +#define regCP_IB2_BUFSZ_DEFAULT 0x00000000 +#define regCP_ST_BASE_LO_DEFAULT 0x00000000 +#define regCP_ST_BASE_HI_DEFAULT 0x00000000 +#define regCP_ST_BUFSZ_DEFAULT 0x00000000 +#define regCP_EOP_DONE_EVENT_CNTL_DEFAULT 0x00000000 +#define regCP_EOP_DONE_DATA_CNTL_DEFAULT 0x00000000 +#define regCP_EOP_DONE_CNTX_ID_DEFAULT 0x00000000 +#define regCP_DB_BASE_LO_DEFAULT 0x00000000 +#define regCP_DB_BASE_HI_DEFAULT 0x00000000 +#define regCP_DB_BUFSZ_DEFAULT 0x00000000 +#define regCP_DB_CMD_BUFSZ_DEFAULT 0x00000000 +#define regCP_PFP_COMPLETION_STATUS_DEFAULT 0x00000000 +#define regCP_PRED_NOT_VISIBLE_DEFAULT 0x00000000 +#define regCP_PFP_METADATA_BASE_ADDR_DEFAULT 0x00000000 +#define regCP_PFP_METADATA_BASE_ADDR_HI_DEFAULT 0x00000000 +#define regCP_DRAW_INDX_INDR_ADDR_DEFAULT 0x00000000 +#define regCP_DRAW_INDX_INDR_ADDR_HI_DEFAULT 0x00000000 +#define regCP_DISPATCH_INDR_ADDR_DEFAULT 0x00000000 +#define regCP_DISPATCH_INDR_ADDR_HI_DEFAULT 0x00000000 +#define regCP_INDEX_BASE_ADDR_DEFAULT 0x00000000 +#define regCP_INDEX_BASE_ADDR_HI_DEFAULT 0x00000000 +#define regCP_INDEX_TYPE_DEFAULT 0x00000000 +#define regCP_GDS_BKUP_ADDR_DEFAULT 0x00000000 +#define regCP_GDS_BKUP_ADDR_HI_DEFAULT 0x00000000 +#define regCP_SAMPLE_STATUS_DEFAULT 0x00000000 +#define regCP_ME_COHER_CNTL_DEFAULT 0x00000000 +#define regCP_ME_COHER_SIZE_DEFAULT 0x00000000 +#define regCP_ME_COHER_SIZE_HI_DEFAULT 0x00000000 +#define regCP_ME_COHER_BASE_DEFAULT 0x00000000 +#define regCP_ME_COHER_BASE_HI_DEFAULT 0x00000000 +#define regCP_ME_COHER_STATUS_DEFAULT 0x00000000 +#define regRLC_GPM_PERF_COUNT_0_DEFAULT 0x00000000 +#define regRLC_GPM_PERF_COUNT_1_DEFAULT 0x00000000 +#define regGRBM_GFX_INDEX_DEFAULT 0xe0000000 +#define regVGT_PRIMITIVE_TYPE_DEFAULT 0x00000000 +#define regVGT_INDEX_TYPE_DEFAULT 0x00000000 +#define regGE_MIN_VTX_INDX_DEFAULT 0x00000000 +#define regGE_INDX_OFFSET_DEFAULT 0x00000000 +#define regGE_MULTI_PRIM_IB_RESET_EN_DEFAULT 0x00000000 +#define regVGT_NUM_INDICES_DEFAULT 0x00000000 +#define regVGT_NUM_INSTANCES_DEFAULT 0x00000000 +#define regVGT_TF_RING_SIZE_DEFAULT 0x00003000 +#define regVGT_HS_OFFCHIP_PARAM_DEFAULT 0x00000000 +#define regVGT_TF_MEMORY_BASE_DEFAULT 0x00000000 +#define regGE_MAX_VTX_INDX_DEFAULT 0x00000000 +#define regVGT_INSTANCE_BASE_ID_DEFAULT 0x00000000 +#define regGE_CNTL_DEFAULT 0x00000000 +#define regGE_USER_VGPR1_DEFAULT 0x00000000 +#define regGE_USER_VGPR2_DEFAULT 0x00000000 +#define regGE_USER_VGPR3_DEFAULT 0x00000000 +#define regGE_STEREO_CNTL_DEFAULT 0x00000000 +#define regGE_PC_ALLOC_DEFAULT 0x00000000 +#define regVGT_TF_MEMORY_BASE_HI_DEFAULT 0x00000000 +#define regGE_USER_VGPR_EN_DEFAULT 0x00000000 +#define regGE_GS_FAST_LAUNCH_WG_DIM_DEFAULT 0x00000000 +#define regGE_GS_FAST_LAUNCH_WG_DIM_1_DEFAULT 0x00000000 +#define regVGT_GS_OUT_PRIM_TYPE_DEFAULT 0x00000000 +#define regPA_SU_LINE_STIPPLE_VALUE_DEFAULT 0x00000000 +#define regPA_SC_LINE_STIPPLE_STATE_DEFAULT 0x00000000 +#define regPA_SC_SCREEN_EXTENT_MIN_0_DEFAULT 0x7fff7fff +#define regPA_SC_SCREEN_EXTENT_MAX_0_DEFAULT 0x80008000 +#define regPA_SC_SCREEN_EXTENT_MIN_1_DEFAULT 0x7fff7fff +#define regPA_SC_SCREEN_EXTENT_MAX_1_DEFAULT 0x80008000 +#define regPA_SC_P3D_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000 +#define regPA_SC_P3D_TRAP_SCREEN_H_DEFAULT 0x00000000 +#define regPA_SC_P3D_TRAP_SCREEN_V_DEFAULT 0x00000000 +#define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000 +#define regPA_SC_P3D_TRAP_SCREEN_COUNT_DEFAULT 0x00000000 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000 +#define regPA_SC_HP3D_TRAP_SCREEN_H_DEFAULT 0x00000000 +#define regPA_SC_HP3D_TRAP_SCREEN_V_DEFAULT 0x00000000 +#define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000 +#define regPA_SC_HP3D_TRAP_SCREEN_COUNT_DEFAULT 0x00000000 +#define regPA_SC_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000 +#define regPA_SC_TRAP_SCREEN_H_DEFAULT 0x00000000 +#define regPA_SC_TRAP_SCREEN_V_DEFAULT 0x00000000 +#define regPA_SC_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000 +#define regPA_SC_TRAP_SCREEN_COUNT_DEFAULT 0x00000000 +#define regSQ_THREAD_TRACE_USERDATA_0_DEFAULT 0x00000000 +#define regSQ_THREAD_TRACE_USERDATA_1_DEFAULT 0x00000000 +#define regSQ_THREAD_TRACE_USERDATA_2_DEFAULT 0x00000000 +#define regSQ_THREAD_TRACE_USERDATA_3_DEFAULT 0x00000000 +#define regSQ_THREAD_TRACE_USERDATA_4_DEFAULT 0x00000000 +#define regSQ_THREAD_TRACE_USERDATA_5_DEFAULT 0x00000000 +#define regSQ_THREAD_TRACE_USERDATA_6_DEFAULT 0x00000000 +#define regSQ_THREAD_TRACE_USERDATA_7_DEFAULT 0x00000000 +#define regSQC_CACHES_DEFAULT 0x00000000 +#define regTA_CS_BC_BASE_ADDR_DEFAULT 0x00000000 +#define regTA_CS_BC_BASE_ADDR_HI_DEFAULT 0x00000000 +#define regDB_OCCLUSION_COUNT0_LOW_DEFAULT 0x00000000 +#define regDB_OCCLUSION_COUNT0_HI_DEFAULT 0x00000000 +#define regDB_OCCLUSION_COUNT1_LOW_DEFAULT 0x00000000 +#define regDB_OCCLUSION_COUNT1_HI_DEFAULT 0x00000000 +#define regDB_OCCLUSION_COUNT2_LOW_DEFAULT 0x00000000 +#define regDB_OCCLUSION_COUNT2_HI_DEFAULT 0x00000000 +#define regDB_OCCLUSION_COUNT3_LOW_DEFAULT 0x00000000 +#define regDB_OCCLUSION_COUNT3_HI_DEFAULT 0x00000000 +#define regGDS_RD_ADDR_DEFAULT 0x00000000 +#define regGDS_RD_DATA_DEFAULT 0x00000000 +#define regGDS_RD_BURST_ADDR_DEFAULT 0x00000000 +#define regGDS_RD_BURST_COUNT_DEFAULT 0x00000000 +#define regGDS_RD_BURST_DATA_DEFAULT 0x00000000 +#define regGDS_WR_ADDR_DEFAULT 0x00000000 +#define regGDS_WR_DATA_DEFAULT 0x00000000 +#define regGDS_WR_BURST_ADDR_DEFAULT 0x00000000 +#define regGDS_WR_BURST_DATA_DEFAULT 0x00000000 +#define regGDS_WRITE_COMPLETE_DEFAULT 0x00000000 +#define regGDS_ATOM_CNTL_DEFAULT 0x00000000 +#define regGDS_ATOM_COMPLETE_DEFAULT 0x00000001 +#define regGDS_ATOM_BASE_DEFAULT 0x00000000 +#define regGDS_ATOM_SIZE_DEFAULT 0x00000000 +#define regGDS_ATOM_OFFSET0_DEFAULT 0x00000000 +#define regGDS_ATOM_OFFSET1_DEFAULT 0x00000000 +#define regGDS_ATOM_DST_DEFAULT 0x00000000 +#define regGDS_ATOM_OP_DEFAULT 0x00000000 +#define regGDS_ATOM_SRC0_DEFAULT 0x00000000 +#define regGDS_ATOM_SRC0_U_DEFAULT 0x00000000 +#define regGDS_ATOM_SRC1_DEFAULT 0x00000000 +#define regGDS_ATOM_SRC1_U_DEFAULT 0x00000000 +#define regGDS_ATOM_READ0_DEFAULT 0x00000000 +#define regGDS_ATOM_READ0_U_DEFAULT 0x00000000 +#define regGDS_ATOM_READ1_DEFAULT 0x00000000 +#define regGDS_ATOM_READ1_U_DEFAULT 0x00000000 +#define regGDS_GWS_RESOURCE_CNTL_DEFAULT 0x00000000 +#define regGDS_GWS_RESOURCE_DEFAULT 0x00000000 +#define regGDS_GWS_RESOURCE_CNT_DEFAULT 0x00000000 +#define regGDS_OA_CNTL_DEFAULT 0x00000000 +#define regGDS_OA_COUNTER_DEFAULT 0x00000000 +#define regGDS_OA_ADDRESS_DEFAULT 0x00000000 +#define regGDS_OA_INCDEC_DEFAULT 0x00000000 +#define regGDS_OA_RING_SIZE_DEFAULT 0x00000000 +#define regGDS_STRMOUT_DWORDS_WRITTEN_0_DEFAULT 0x00000000 +#define regGDS_STRMOUT_DWORDS_WRITTEN_1_DEFAULT 0x00000000 +#define regGDS_STRMOUT_DWORDS_WRITTEN_2_DEFAULT 0x00000000 +#define regGDS_STRMOUT_DWORDS_WRITTEN_3_DEFAULT 0x00000000 +#define regGDS_GS_0_DEFAULT 0x00000000 +#define regGDS_GS_1_DEFAULT 0x00000000 +#define regGDS_GS_2_DEFAULT 0x00000000 +#define regGDS_GS_3_DEFAULT 0x00000000 +#define regGDS_STRMOUT_PRIMS_NEEDED_0_LO_DEFAULT 0x00000000 +#define regGDS_STRMOUT_PRIMS_NEEDED_0_HI_DEFAULT 0x00000000 +#define regGDS_STRMOUT_PRIMS_WRITTEN_0_LO_DEFAULT 0x00000000 +#define regGDS_STRMOUT_PRIMS_WRITTEN_0_HI_DEFAULT 0x00000000 +#define regGDS_STRMOUT_PRIMS_NEEDED_1_LO_DEFAULT 0x00000000 +#define regGDS_STRMOUT_PRIMS_NEEDED_1_HI_DEFAULT 0x00000000 +#define regGDS_STRMOUT_PRIMS_WRITTEN_1_LO_DEFAULT 0x00000000 +#define regGDS_STRMOUT_PRIMS_WRITTEN_1_HI_DEFAULT 0x00000000 +#define regGDS_STRMOUT_PRIMS_NEEDED_2_LO_DEFAULT 0x00000000 +#define regGDS_STRMOUT_PRIMS_NEEDED_2_HI_DEFAULT 0x00000000 +#define regGDS_STRMOUT_PRIMS_WRITTEN_2_LO_DEFAULT 0x00000000 +#define regGDS_STRMOUT_PRIMS_WRITTEN_2_HI_DEFAULT 0x00000000 +#define regGDS_STRMOUT_PRIMS_NEEDED_3_LO_DEFAULT 0x00000000 +#define regGDS_STRMOUT_PRIMS_NEEDED_3_HI_DEFAULT 0x00000000 +#define regGDS_STRMOUT_PRIMS_WRITTEN_3_LO_DEFAULT 0x00000000 +#define regGDS_STRMOUT_PRIMS_WRITTEN_3_HI_DEFAULT 0x00000000 +#define regSPI_CONFIG_CNTL_DEFAULT 0xc062c688 +#define regSPI_CONFIG_CNTL_1_DEFAULT 0x80070000 +#define regSPI_CONFIG_CNTL_2_DEFAULT 0x00010011 +#define regSPI_WAVE_LIMIT_CNTL_DEFAULT 0x00000000 +#define regSPI_GS_THROTTLE_CNTL1_DEFAULT 0x12355123 +#define regSPI_GS_THROTTLE_CNTL2_DEFAULT 0x0001544d +#define regSPI_ATTRIBUTE_RING_BASE_DEFAULT 0x00000000 +#define regSPI_ATTRIBUTE_RING_SIZE_DEFAULT 0x00020000 + + +// addressBlock: gc_cprs64dec +#define regCP_MES_PRGRM_CNTR_START_DEFAULT 0x00000800 +#define regCP_MES_INTR_ROUTINE_START_DEFAULT 0x00000000 +#define regCP_MES_MTVEC_LO_DEFAULT 0x00000000 +#define regCP_MES_INTR_ROUTINE_START_HI_DEFAULT 0x00000000 +#define regCP_MES_MTVEC_HI_DEFAULT 0x00000000 +#define regCP_MES_CNTL_DEFAULT 0x40000000 +#define regCP_MES_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020 +#define regCP_MES_PIPE0_PRIORITY_DEFAULT 0x00000002 +#define regCP_MES_PIPE1_PRIORITY_DEFAULT 0x00000002 +#define regCP_MES_PIPE2_PRIORITY_DEFAULT 0x00000002 +#define regCP_MES_PIPE3_PRIORITY_DEFAULT 0x00000002 +#define regCP_MES_HEADER_DUMP_DEFAULT 0xdef0def0 +#define regCP_MES_MIE_LO_DEFAULT 0x00000000 +#define regCP_MES_MIE_HI_DEFAULT 0x00000000 +#define regCP_MES_INTERRUPT_DEFAULT 0x00000000 +#define regCP_MES_SCRATCH_INDEX_DEFAULT 0x00000000 +#define regCP_MES_SCRATCH_DATA_DEFAULT 0x00000000 +#define regCP_MES_INSTR_PNTR_DEFAULT 0x00000000 +#define regCP_MES_MSCRATCH_HI_DEFAULT 0x00000000 +#define regCP_MES_MSCRATCH_LO_DEFAULT 0x00000000 +#define regCP_MES_MSTATUS_LO_DEFAULT 0x00000000 +#define regCP_MES_MSTATUS_HI_DEFAULT 0x00000000 +#define regCP_MES_MEPC_LO_DEFAULT 0x00000000 +#define regCP_MES_MEPC_HI_DEFAULT 0x00000000 +#define regCP_MES_MCAUSE_LO_DEFAULT 0x00000000 +#define regCP_MES_MCAUSE_HI_DEFAULT 0x00000000 +#define regCP_MES_MBADADDR_LO_DEFAULT 0x00000000 +#define regCP_MES_MBADADDR_HI_DEFAULT 0x00000000 +#define regCP_MES_MIP_LO_DEFAULT 0x00000000 +#define regCP_MES_MIP_HI_DEFAULT 0x00000000 +#define regCP_MES_IC_OP_CNTL_DEFAULT 0x00000000 +#define regCP_MES_MCYCLE_LO_DEFAULT 0x00000000 +#define regCP_MES_MCYCLE_HI_DEFAULT 0x00000000 +#define regCP_MES_MTIME_LO_DEFAULT 0x00000000 +#define regCP_MES_MTIME_HI_DEFAULT 0x00000000 +#define regCP_MES_MINSTRET_LO_DEFAULT 0x00000000 +#define regCP_MES_MINSTRET_HI_DEFAULT 0x00000000 +#define regCP_MES_MISA_LO_DEFAULT 0x00000000 +#define regCP_MES_MISA_HI_DEFAULT 0x00000000 +#define regCP_MES_MVENDORID_LO_DEFAULT 0x00000000 +#define regCP_MES_MVENDORID_HI_DEFAULT 0x00000000 +#define regCP_MES_MARCHID_LO_DEFAULT 0x00000000 +#define regCP_MES_MARCHID_HI_DEFAULT 0x00000000 +#define regCP_MES_MIMPID_LO_DEFAULT 0x00000000 +#define regCP_MES_MIMPID_HI_DEFAULT 0x00000000 +#define regCP_MES_MHARTID_LO_DEFAULT 0x00000000 +#define regCP_MES_MHARTID_HI_DEFAULT 0x00000000 +#define regCP_MES_DC_BASE_CNTL_DEFAULT 0x00000000 +#define regCP_MES_DC_OP_CNTL_DEFAULT 0x00000000 +#define regCP_MES_MTIMECMP_LO_DEFAULT 0x00000000 +#define regCP_MES_MTIMECMP_HI_DEFAULT 0x00000000 +#define regCP_MES_PROCESS_QUANTUM_PIPE0_DEFAULT 0x00000008 +#define regCP_MES_PROCESS_QUANTUM_PIPE1_DEFAULT 0x00000008 +#define regCP_MES_DOORBELL_CONTROL1_DEFAULT 0x00000000 +#define regCP_MES_DOORBELL_CONTROL2_DEFAULT 0x00000000 +#define regCP_MES_DOORBELL_CONTROL3_DEFAULT 0x00000000 +#define regCP_MES_DOORBELL_CONTROL4_DEFAULT 0x00000000 +#define regCP_MES_DOORBELL_CONTROL5_DEFAULT 0x00000000 +#define regCP_MES_DOORBELL_CONTROL6_DEFAULT 0x00000000 +#define regCP_MES_GP0_LO_DEFAULT 0x00000000 +#define regCP_MES_GP0_HI_DEFAULT 0x00000000 +#define regCP_MES_GP1_LO_DEFAULT 0x00002001 +#define regCP_MES_GP1_HI_DEFAULT 0x00000000 +#define regCP_MES_GP2_LO_DEFAULT 0x00000000 +#define regCP_MES_GP2_HI_DEFAULT 0x00000000 +#define regCP_MES_GP3_LO_DEFAULT 0x00000000 +#define regCP_MES_GP3_HI_DEFAULT 0x00000000 +#define regCP_MES_GP4_LO_DEFAULT 0x00000000 +#define regCP_MES_GP4_HI_DEFAULT 0x00000000 +#define regCP_MES_GP5_LO_DEFAULT 0x00000000 +#define regCP_MES_GP5_HI_DEFAULT 0x00000000 +#define regCP_MES_GP6_LO_DEFAULT 0x00000000 +#define regCP_MES_GP6_HI_DEFAULT 0x00000000 +#define regCP_MES_GP7_LO_DEFAULT 0x00000000 +#define regCP_MES_GP7_HI_DEFAULT 0x00000000 +#define regCP_MES_GP8_LO_DEFAULT 0x00000000 +#define regCP_MES_GP8_HI_DEFAULT 0x00000000 +#define regCP_MES_GP9_LO_DEFAULT 0x40000000 +#define regCP_MES_GP9_HI_DEFAULT 0x40000000 +#define regCP_MES_LOCAL_BASE0_LO_DEFAULT 0x00000000 +#define regCP_MES_LOCAL_BASE0_HI_DEFAULT 0x00000000 +#define regCP_MES_LOCAL_MASK0_LO_DEFAULT 0xffff0000 +#define regCP_MES_LOCAL_MASK0_HI_DEFAULT 0x0000ffff +#define regCP_MES_LOCAL_APERTURE_DEFAULT 0x00000007 +#define regCP_MES_LOCAL_INSTR_BASE_LO_DEFAULT 0x00000000 +#define regCP_MES_LOCAL_INSTR_BASE_HI_DEFAULT 0x00000000 +#define regCP_MES_LOCAL_INSTR_MASK_LO_DEFAULT 0x000f0000 +#define regCP_MES_LOCAL_INSTR_MASK_HI_DEFAULT 0x00000000 +#define regCP_MES_LOCAL_INSTR_APERTURE_DEFAULT 0x00000007 +#define regCP_MES_LOCAL_SCRATCH_APERTURE_DEFAULT 0x00000003 +#define regCP_MES_LOCAL_SCRATCH_BASE_LO_DEFAULT 0x00000000 +#define regCP_MES_LOCAL_SCRATCH_BASE_HI_DEFAULT 0x00000000 +#define regCP_MES_PERFCOUNT_CNTL_DEFAULT 0x00000000 +#define regCP_MES_PENDING_INTERRUPT_DEFAULT 0x00000000 +#define regCP_MES_PRGRM_CNTR_START_HI_DEFAULT 0x00000000 +#define regCP_MES_INTERRUPT_DATA_16_DEFAULT 0x00000000 +#define regCP_MES_INTERRUPT_DATA_17_DEFAULT 0x00000000 +#define regCP_MES_INTERRUPT_DATA_18_DEFAULT 0x00000000 +#define regCP_MES_INTERRUPT_DATA_19_DEFAULT 0x00000000 +#define regCP_MES_INTERRUPT_DATA_20_DEFAULT 0x00000000 +#define regCP_MES_INTERRUPT_DATA_21_DEFAULT 0x00000000 +#define regCP_MES_INTERRUPT_DATA_22_DEFAULT 0x00000000 +#define regCP_MES_INTERRUPT_DATA_23_DEFAULT 0x00000000 +#define regCP_MES_INTERRUPT_DATA_24_DEFAULT 0x00000000 +#define regCP_MES_INTERRUPT_DATA_25_DEFAULT 0x00000000 +#define regCP_MES_INTERRUPT_DATA_26_DEFAULT 0x00000000 +#define regCP_MES_INTERRUPT_DATA_27_DEFAULT 0x00000000 +#define regCP_MES_INTERRUPT_DATA_28_DEFAULT 0x00000000 +#define regCP_MES_INTERRUPT_DATA_29_DEFAULT 0x00000000 +#define regCP_MES_INTERRUPT_DATA_30_DEFAULT 0x00000000 +#define regCP_MES_INTERRUPT_DATA_31_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE0_BASE_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE0_MASK_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE0_CNTL_DEFAULT 0x00000010 +#define regCP_MES_DC_APERTURE1_BASE_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE1_MASK_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE1_CNTL_DEFAULT 0x00000011 +#define regCP_MES_DC_APERTURE2_BASE_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE2_MASK_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE2_CNTL_DEFAULT 0x00000012 +#define regCP_MES_DC_APERTURE3_BASE_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE3_MASK_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE3_CNTL_DEFAULT 0x00000013 +#define regCP_MES_DC_APERTURE4_BASE_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE4_MASK_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE4_CNTL_DEFAULT 0x00000014 +#define regCP_MES_DC_APERTURE5_BASE_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE5_MASK_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE5_CNTL_DEFAULT 0x00000015 +#define regCP_MES_DC_APERTURE6_BASE_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE6_MASK_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE6_CNTL_DEFAULT 0x00000016 +#define regCP_MES_DC_APERTURE7_BASE_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE7_MASK_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE7_CNTL_DEFAULT 0x00000017 +#define regCP_MES_DC_APERTURE8_BASE_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE8_MASK_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE8_CNTL_DEFAULT 0x00000018 +#define regCP_MES_DC_APERTURE9_BASE_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE9_MASK_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE9_CNTL_DEFAULT 0x00000019 +#define regCP_MES_DC_APERTURE10_BASE_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE10_MASK_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE10_CNTL_DEFAULT 0x0000001a +#define regCP_MES_DC_APERTURE11_BASE_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE11_MASK_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE11_CNTL_DEFAULT 0x0000001b +#define regCP_MES_DC_APERTURE12_BASE_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE12_MASK_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE12_CNTL_DEFAULT 0x0000001c +#define regCP_MES_DC_APERTURE13_BASE_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE13_MASK_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE13_CNTL_DEFAULT 0x0000001d +#define regCP_MES_DC_APERTURE14_BASE_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE14_MASK_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE14_CNTL_DEFAULT 0x0000001e +#define regCP_MES_DC_APERTURE15_BASE_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE15_MASK_DEFAULT 0x00000000 +#define regCP_MES_DC_APERTURE15_CNTL_DEFAULT 0x0000001f +#define regCP_MEC_RS64_PRGRM_CNTR_START_DEFAULT 0x00000800 +#define regCP_MEC_MTVEC_LO_DEFAULT 0x00000000 +#define regCP_MEC_MTVEC_HI_DEFAULT 0x00000000 +#define regCP_MEC_ISA_CNTL_DEFAULT 0x00000000 +#define regCP_MEC_RS64_CNTL_DEFAULT 0x40000000 +#define regCP_MEC_MIE_LO_DEFAULT 0x00000000 +#define regCP_MEC_MIE_HI_DEFAULT 0x00000000 +#define regCP_MEC_RS64_INTERRUPT_DEFAULT 0x00000000 +#define regCP_MEC_RS64_INSTR_PNTR_DEFAULT 0x00000000 +#define regCP_MEC_MIP_LO_DEFAULT 0x00000000 +#define regCP_MEC_MIP_HI_DEFAULT 0x00000000 +#define regCP_MEC_DC_BASE_CNTL_DEFAULT 0x00000000 +#define regCP_MEC_DC_OP_CNTL_DEFAULT 0x00000000 +#define regCP_MEC_MTIMECMP_LO_DEFAULT 0x00000000 +#define regCP_MEC_MTIMECMP_HI_DEFAULT 0x00000000 +#define regCP_MEC_GP0_LO_DEFAULT 0x00000000 +#define regCP_MEC_GP0_HI_DEFAULT 0x00000000 +#define regCP_MEC_GP1_LO_DEFAULT 0x00002001 +#define regCP_MEC_GP1_HI_DEFAULT 0x00000000 +#define regCP_MEC_GP2_LO_DEFAULT 0x00000000 +#define regCP_MEC_GP2_HI_DEFAULT 0x00000000 +#define regCP_MEC_GP3_LO_DEFAULT 0x00000000 +#define regCP_MEC_GP3_HI_DEFAULT 0x00000000 +#define regCP_MEC_GP4_LO_DEFAULT 0x00000000 +#define regCP_MEC_GP4_HI_DEFAULT 0x00000000 +#define regCP_MEC_GP5_LO_DEFAULT 0x00000000 +#define regCP_MEC_GP5_HI_DEFAULT 0x00000000 +#define regCP_MEC_GP6_LO_DEFAULT 0x00000000 +#define regCP_MEC_GP6_HI_DEFAULT 0x00000000 +#define regCP_MEC_GP7_LO_DEFAULT 0x00000000 +#define regCP_MEC_GP7_HI_DEFAULT 0x00000000 +#define regCP_MEC_GP8_LO_DEFAULT 0x00000000 +#define regCP_MEC_GP8_HI_DEFAULT 0x00000000 +#define regCP_MEC_GP9_LO_DEFAULT 0x40000000 +#define regCP_MEC_GP9_HI_DEFAULT 0x40000000 +#define regCP_MEC_LOCAL_BASE0_LO_DEFAULT 0x00000000 +#define regCP_MEC_LOCAL_BASE0_HI_DEFAULT 0x00000000 +#define regCP_MEC_LOCAL_MASK0_LO_DEFAULT 0xffff0000 +#define regCP_MEC_LOCAL_MASK0_HI_DEFAULT 0x0000ffff +#define regCP_MEC_LOCAL_APERTURE_DEFAULT 0x00000007 +#define regCP_MEC_LOCAL_INSTR_BASE_LO_DEFAULT 0x00000000 +#define regCP_MEC_LOCAL_INSTR_BASE_HI_DEFAULT 0x00000000 +#define regCP_MEC_LOCAL_INSTR_MASK_LO_DEFAULT 0x000f0000 +#define regCP_MEC_LOCAL_INSTR_MASK_HI_DEFAULT 0x00000000 +#define regCP_MEC_LOCAL_INSTR_APERTURE_DEFAULT 0x00000007 +#define regCP_MEC_LOCAL_SCRATCH_APERTURE_DEFAULT 0x00000003 +#define regCP_MEC_LOCAL_SCRATCH_BASE_LO_DEFAULT 0x00000000 +#define regCP_MEC_LOCAL_SCRATCH_BASE_HI_DEFAULT 0x00000000 +#define regCP_MEC_RS64_PERFCOUNT_CNTL_DEFAULT 0x00000000 +#define regCP_MEC_RS64_PENDING_INTERRUPT_DEFAULT 0x00000000 +#define regCP_MEC_RS64_PRGRM_CNTR_START_HI_DEFAULT 0x00000000 +#define regCP_MEC_RS64_INTERRUPT_DATA_16_DEFAULT 0x00000000 +#define regCP_MEC_RS64_INTERRUPT_DATA_17_DEFAULT 0x00000000 +#define regCP_MEC_RS64_INTERRUPT_DATA_18_DEFAULT 0x00000000 +#define regCP_MEC_RS64_INTERRUPT_DATA_19_DEFAULT 0x00000000 +#define regCP_MEC_RS64_INTERRUPT_DATA_20_DEFAULT 0x00000000 +#define regCP_MEC_RS64_INTERRUPT_DATA_21_DEFAULT 0x00000000 +#define regCP_MEC_RS64_INTERRUPT_DATA_22_DEFAULT 0x00000000 +#define regCP_MEC_RS64_INTERRUPT_DATA_23_DEFAULT 0x00000000 +#define regCP_MEC_RS64_INTERRUPT_DATA_24_DEFAULT 0x00000000 +#define regCP_MEC_RS64_INTERRUPT_DATA_25_DEFAULT 0x00000000 +#define regCP_MEC_RS64_INTERRUPT_DATA_26_DEFAULT 0x00000000 +#define regCP_MEC_RS64_INTERRUPT_DATA_27_DEFAULT 0x00000000 +#define regCP_MEC_RS64_INTERRUPT_DATA_28_DEFAULT 0x00000000 +#define regCP_MEC_RS64_INTERRUPT_DATA_29_DEFAULT 0x00000000 +#define regCP_MEC_RS64_INTERRUPT_DATA_30_DEFAULT 0x00000000 +#define regCP_MEC_RS64_INTERRUPT_DATA_31_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE0_BASE_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE0_MASK_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE0_CNTL_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE1_BASE_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE1_MASK_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE1_CNTL_DEFAULT 0x00000001 +#define regCP_MEC_DC_APERTURE2_BASE_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE2_MASK_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE2_CNTL_DEFAULT 0x00000002 +#define regCP_MEC_DC_APERTURE3_BASE_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE3_MASK_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE3_CNTL_DEFAULT 0x00000003 +#define regCP_MEC_DC_APERTURE4_BASE_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE4_MASK_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE4_CNTL_DEFAULT 0x00000004 +#define regCP_MEC_DC_APERTURE5_BASE_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE5_MASK_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE5_CNTL_DEFAULT 0x00000005 +#define regCP_MEC_DC_APERTURE6_BASE_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE6_MASK_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE6_CNTL_DEFAULT 0x00000006 +#define regCP_MEC_DC_APERTURE7_BASE_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE7_MASK_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE7_CNTL_DEFAULT 0x00000007 +#define regCP_MEC_DC_APERTURE8_BASE_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE8_MASK_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE8_CNTL_DEFAULT 0x00000008 +#define regCP_MEC_DC_APERTURE9_BASE_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE9_MASK_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE9_CNTL_DEFAULT 0x00000009 +#define regCP_MEC_DC_APERTURE10_BASE_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE10_MASK_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE10_CNTL_DEFAULT 0x0000000a +#define regCP_MEC_DC_APERTURE11_BASE_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE11_MASK_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE11_CNTL_DEFAULT 0x0000000b +#define regCP_MEC_DC_APERTURE12_BASE_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE12_MASK_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE12_CNTL_DEFAULT 0x0000000c +#define regCP_MEC_DC_APERTURE13_BASE_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE13_MASK_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE13_CNTL_DEFAULT 0x0000000d +#define regCP_MEC_DC_APERTURE14_BASE_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE14_MASK_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE14_CNTL_DEFAULT 0x0000000e +#define regCP_MEC_DC_APERTURE15_BASE_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE15_MASK_DEFAULT 0x00000000 +#define regCP_MEC_DC_APERTURE15_CNTL_DEFAULT 0x0000000f +#define regCP_CPC_IC_OP_CNTL_DEFAULT 0x00000000 +#define regCP_GFX_CNTL_DEFAULT 0x00000000 +#define regCP_GFX_RS64_INTERRUPT0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_INTR_EN0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_INTR_EN1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_BASE_CNTL_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_OP_CNTL_DEFAULT 0x00000000 +#define regCP_GFX_RS64_LOCAL_BASE0_LO_DEFAULT 0x00000000 +#define regCP_GFX_RS64_LOCAL_BASE0_HI_DEFAULT 0x00000000 +#define regCP_GFX_RS64_LOCAL_MASK0_LO_DEFAULT 0xffff0000 +#define regCP_GFX_RS64_LOCAL_MASK0_HI_DEFAULT 0x0000ffff +#define regCP_GFX_RS64_LOCAL_APERTURE_DEFAULT 0x00000007 +#define regCP_GFX_RS64_LOCAL_INSTR_BASE_LO_DEFAULT 0x00000000 +#define regCP_GFX_RS64_LOCAL_INSTR_BASE_HI_DEFAULT 0x00000000 +#define regCP_GFX_RS64_LOCAL_INSTR_MASK_LO_DEFAULT 0x000f0000 +#define regCP_GFX_RS64_LOCAL_INSTR_MASK_HI_DEFAULT 0x00000000 +#define regCP_GFX_RS64_LOCAL_INSTR_APERTURE_DEFAULT 0x00000007 +#define regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE_DEFAULT 0x00000003 +#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO_DEFAULT 0x00000000 +#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI_DEFAULT 0x00000000 +#define regCP_GFX_RS64_PERFCOUNT_CNTL0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_PERFCOUNT_CNTL1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_MIP_LO0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_MIP_LO1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_MIP_HI0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_MIP_HI1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_MTIMECMP_LO0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_MTIMECMP_LO1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_MTIMECMP_HI0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_MTIMECMP_HI1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP0_LO0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP0_LO1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP0_HI0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP0_HI1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP1_LO0_DEFAULT 0x00002001 +#define regCP_GFX_RS64_GP1_LO1_DEFAULT 0x00002001 +#define regCP_GFX_RS64_GP1_HI0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP1_HI1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP2_LO0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP2_LO1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP2_HI0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP2_HI1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP3_LO0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP3_LO1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP3_HI0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP3_HI1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP4_LO0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP4_LO1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP4_HI0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP4_HI1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP5_LO0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP5_LO1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP5_HI0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP5_HI1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP6_LO_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP6_HI_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP7_LO_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP7_HI_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP8_LO_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP8_HI_DEFAULT 0x00000000 +#define regCP_GFX_RS64_GP9_LO_DEFAULT 0x40000000 +#define regCP_GFX_RS64_GP9_HI_DEFAULT 0x40000000 +#define regCP_GFX_RS64_INSTR_PNTR0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_INSTR_PNTR1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_PENDING_INTERRUPT0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_PENDING_INTERRUPT1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE0_BASE0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE0_MASK0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE0_CNTL0_DEFAULT 0x00000010 +#define regCP_GFX_RS64_DC_APERTURE1_BASE0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE1_MASK0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE1_CNTL0_DEFAULT 0x00000011 +#define regCP_GFX_RS64_DC_APERTURE2_BASE0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE2_MASK0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE2_CNTL0_DEFAULT 0x00000012 +#define regCP_GFX_RS64_DC_APERTURE3_BASE0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE3_MASK0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE3_CNTL0_DEFAULT 0x00000013 +#define regCP_GFX_RS64_DC_APERTURE4_BASE0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE4_MASK0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE4_CNTL0_DEFAULT 0x00000014 +#define regCP_GFX_RS64_DC_APERTURE5_BASE0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE5_MASK0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE5_CNTL0_DEFAULT 0x00000015 +#define regCP_GFX_RS64_DC_APERTURE6_BASE0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE6_MASK0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE6_CNTL0_DEFAULT 0x00000016 +#define regCP_GFX_RS64_DC_APERTURE7_BASE0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE7_MASK0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE7_CNTL0_DEFAULT 0x00000017 +#define regCP_GFX_RS64_DC_APERTURE8_BASE0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE8_MASK0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE8_CNTL0_DEFAULT 0x00000018 +#define regCP_GFX_RS64_DC_APERTURE9_BASE0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE9_MASK0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE9_CNTL0_DEFAULT 0x00000019 +#define regCP_GFX_RS64_DC_APERTURE10_BASE0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE10_MASK0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE10_CNTL0_DEFAULT 0x0000001a +#define regCP_GFX_RS64_DC_APERTURE11_BASE0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE11_MASK0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE11_CNTL0_DEFAULT 0x0000001b +#define regCP_GFX_RS64_DC_APERTURE12_BASE0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE12_MASK0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE12_CNTL0_DEFAULT 0x0000001c +#define regCP_GFX_RS64_DC_APERTURE13_BASE0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE13_MASK0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE13_CNTL0_DEFAULT 0x0000001d +#define regCP_GFX_RS64_DC_APERTURE14_BASE0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE14_MASK0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE14_CNTL0_DEFAULT 0x0000001e +#define regCP_GFX_RS64_DC_APERTURE15_BASE0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE15_MASK0_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE15_CNTL0_DEFAULT 0x0000001f +#define regCP_GFX_RS64_DC_APERTURE0_BASE1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE0_MASK1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE0_CNTL1_DEFAULT 0x00000010 +#define regCP_GFX_RS64_DC_APERTURE1_BASE1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE1_MASK1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE1_CNTL1_DEFAULT 0x00000011 +#define regCP_GFX_RS64_DC_APERTURE2_BASE1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE2_MASK1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE2_CNTL1_DEFAULT 0x00000012 +#define regCP_GFX_RS64_DC_APERTURE3_BASE1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE3_MASK1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE3_CNTL1_DEFAULT 0x00000013 +#define regCP_GFX_RS64_DC_APERTURE4_BASE1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE4_MASK1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE4_CNTL1_DEFAULT 0x00000014 +#define regCP_GFX_RS64_DC_APERTURE5_BASE1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE5_MASK1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE5_CNTL1_DEFAULT 0x00000015 +#define regCP_GFX_RS64_DC_APERTURE6_BASE1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE6_MASK1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE6_CNTL1_DEFAULT 0x00000016 +#define regCP_GFX_RS64_DC_APERTURE7_BASE1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE7_MASK1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE7_CNTL1_DEFAULT 0x00000017 +#define regCP_GFX_RS64_DC_APERTURE8_BASE1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE8_MASK1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE8_CNTL1_DEFAULT 0x00000018 +#define regCP_GFX_RS64_DC_APERTURE9_BASE1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE9_MASK1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE9_CNTL1_DEFAULT 0x00000019 +#define regCP_GFX_RS64_DC_APERTURE10_BASE1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE10_MASK1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE10_CNTL1_DEFAULT 0x0000001a +#define regCP_GFX_RS64_DC_APERTURE11_BASE1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE11_MASK1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE11_CNTL1_DEFAULT 0x0000001b +#define regCP_GFX_RS64_DC_APERTURE12_BASE1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE12_MASK1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE12_CNTL1_DEFAULT 0x0000001c +#define regCP_GFX_RS64_DC_APERTURE13_BASE1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE13_MASK1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE13_CNTL1_DEFAULT 0x0000001d +#define regCP_GFX_RS64_DC_APERTURE14_BASE1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE14_MASK1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE14_CNTL1_DEFAULT 0x0000001e +#define regCP_GFX_RS64_DC_APERTURE15_BASE1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE15_MASK1_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_APERTURE15_CNTL1_DEFAULT 0x0000001f +#define regCP_GFX_RS64_INTERRUPT1_DEFAULT 0x00000000 + + +// addressBlock: gc_gusdec +#define regGUS_IO_RD_COMBINE_FLUSH_DEFAULT 0x00000000 +#define regGUS_IO_WR_COMBINE_FLUSH_DEFAULT 0x01000000 +#define regGUS_IO_RD_PRI_AGE_RATE_DEFAULT 0x00000000 +#define regGUS_IO_WR_PRI_AGE_RATE_DEFAULT 0x00000000 +#define regGUS_IO_RD_PRI_AGE_COEFF_DEFAULT 0x0003ffff +#define regGUS_IO_WR_PRI_AGE_COEFF_DEFAULT 0x0003ffff +#define regGUS_IO_RD_PRI_QUEUING_DEFAULT 0x0003ffff +#define regGUS_IO_WR_PRI_QUEUING_DEFAULT 0x0003ffff +#define regGUS_IO_RD_PRI_FIXED_DEFAULT 0x00000000 +#define regGUS_IO_WR_PRI_FIXED_DEFAULT 0x00000000 +#define regGUS_IO_RD_PRI_URGENCY_COEFF_DEFAULT 0x00000000 +#define regGUS_IO_WR_PRI_URGENCY_COEFF_DEFAULT 0x00000000 +#define regGUS_IO_RD_PRI_URGENCY_MODE_DEFAULT 0x00000000 +#define regGUS_IO_WR_PRI_URGENCY_MODE_DEFAULT 0x00000000 +#define regGUS_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x1f1f1f1f +#define regGUS_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x3f3f3f3f +#define regGUS_IO_RD_PRI_QUANT_PRI3_DEFAULT 0x7f7f7f7f +#define regGUS_IO_RD_PRI_QUANT_PRI4_DEFAULT 0xffffffff +#define regGUS_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x1f1f1f1f +#define regGUS_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x3f3f3f3f +#define regGUS_IO_WR_PRI_QUANT_PRI3_DEFAULT 0x7f7f7f7f +#define regGUS_IO_WR_PRI_QUANT_PRI4_DEFAULT 0xffffffff +#define regGUS_IO_RD_PRI_QUANT1_PRI1_DEFAULT 0x00001f1f +#define regGUS_IO_RD_PRI_QUANT1_PRI2_DEFAULT 0x00003f3f +#define regGUS_IO_RD_PRI_QUANT1_PRI3_DEFAULT 0x00007f7f +#define regGUS_IO_RD_PRI_QUANT1_PRI4_DEFAULT 0x0000ffff +#define regGUS_IO_WR_PRI_QUANT1_PRI1_DEFAULT 0x00001f1f +#define regGUS_IO_WR_PRI_QUANT1_PRI2_DEFAULT 0x00003f3f +#define regGUS_IO_WR_PRI_QUANT1_PRI3_DEFAULT 0x00007f7f +#define regGUS_IO_WR_PRI_QUANT1_PRI4_DEFAULT 0x0000ffff +#define regGUS_DRAM_COMBINE_FLUSH_DEFAULT 0x00000000 +#define regGUS_DRAM_COMBINE_RD_WR_EN_DEFAULT 0x00000fff +#define regGUS_DRAM_PRI_AGE_RATE_DEFAULT 0x00001249 +#define regGUS_DRAM_PRI_AGE_COEFF_DEFAULT 0x0003ffff +#define regGUS_DRAM_PRI_QUEUING_DEFAULT 0x0003edb6 +#define regGUS_DRAM_PRI_FIXED_DEFAULT 0x00000000 +#define regGUS_DRAM_PRI_URGENCY_COEFF_DEFAULT 0x00000000 +#define regGUS_DRAM_PRI_URGENCY_MODE_DEFAULT 0x00000000 +#define regGUS_DRAM_PRI_QUANT_PRI1_DEFAULT 0x0f0f0f0f +#define regGUS_DRAM_PRI_QUANT_PRI2_DEFAULT 0x1f1f1f1f +#define regGUS_DRAM_PRI_QUANT_PRI3_DEFAULT 0x3f3f3f3f +#define regGUS_DRAM_PRI_QUANT_PRI4_DEFAULT 0x7f7f7f7f +#define regGUS_DRAM_PRI_QUANT_PRI5_DEFAULT 0xffffffff +#define regGUS_DRAM_PRI_QUANT1_PRI1_DEFAULT 0x00000f0f +#define regGUS_DRAM_PRI_QUANT1_PRI2_DEFAULT 0x00001f1f +#define regGUS_DRAM_PRI_QUANT1_PRI3_DEFAULT 0x00003f3f +#define regGUS_DRAM_PRI_QUANT1_PRI4_DEFAULT 0x00007f7f +#define regGUS_DRAM_PRI_QUANT1_PRI5_DEFAULT 0x0000ffff +#define regGUS_IO_GROUP_BURST_DEFAULT 0x05040504 +#define regGUS_DRAM_GROUP_BURST_DEFAULT 0x00000504 +#define regGUS_SDP_ARB_FINAL_DEFAULT 0x00007fff +#define regGUS_SDP_QOS_VC_PRIORITY_DEFAULT 0x0000a000 +#define regGUS_SDP_CREDITS_DEFAULT 0x000100ff +#define regGUS_SDP_TAG_RESERVE0_DEFAULT 0x07070000 +#define regGUS_SDP_TAG_RESERVE1_DEFAULT 0x00000707 +#define regGUS_SDP_VCC_RESERVE0_DEFAULT 0x02041000 +#define regGUS_SDP_VCC_RESERVE1_DEFAULT 0x00000002 +#define regGUS_SDP_VCD_RESERVE0_DEFAULT 0x02040000 +#define regGUS_SDP_VCD_RESERVE1_DEFAULT 0x00000002 +#define regGUS_SDP_REQ_CNTL_DEFAULT 0x0000001f +#define regGUS_MISC_DEFAULT 0x00003c07 +#define regGUS_LATENCY_SAMPLING_DEFAULT 0x00000000 +#define regGUS_ERR_STATUS_DEFAULT 0x00000300 +#define regGUS_MISC2_DEFAULT 0x0000103e +#define regGUS_SDP_ENABLE_DEFAULT 0x00000000 +#define regGUS_L1_CH0_CMD_IN_DEFAULT 0x00000000 +#define regGUS_L1_CH0_CMD_OUT_DEFAULT 0x00000000 +#define regGUS_L1_CH0_DATA_IN_DEFAULT 0x00000000 +#define regGUS_L1_CH0_DATA_OUT_DEFAULT 0x00000000 +#define regGUS_L1_CH0_DATA_U_IN_DEFAULT 0x00000000 +#define regGUS_L1_CH0_DATA_U_OUT_DEFAULT 0x00000000 +#define regGUS_L1_CH1_CMD_IN_DEFAULT 0x00000000 +#define regGUS_L1_CH1_CMD_OUT_DEFAULT 0x00000000 +#define regGUS_L1_CH1_DATA_IN_DEFAULT 0x00000000 +#define regGUS_L1_CH1_DATA_OUT_DEFAULT 0x00000000 +#define regGUS_L1_CH1_DATA_U_IN_DEFAULT 0x00000000 +#define regGUS_L1_CH1_DATA_U_OUT_DEFAULT 0x00000000 +#define regGUS_L1_SA0_CMD_IN_DEFAULT 0x00000000 +#define regGUS_L1_SA0_CMD_OUT_DEFAULT 0x00000000 +#define regGUS_L1_SA0_DATA_IN_DEFAULT 0x00000000 +#define regGUS_L1_SA0_DATA_OUT_DEFAULT 0x00000000 +#define regGUS_L1_SA0_DATA_U_IN_DEFAULT 0x00000000 +#define regGUS_L1_SA0_DATA_U_OUT_DEFAULT 0x00000000 +#define regGUS_L1_SA1_CMD_IN_DEFAULT 0x00000000 +#define regGUS_L1_SA1_CMD_OUT_DEFAULT 0x00000000 +#define regGUS_L1_SA1_DATA_IN_DEFAULT 0x00000000 +#define regGUS_L1_SA1_DATA_OUT_DEFAULT 0x00000000 +#define regGUS_L1_SA1_DATA_U_IN_DEFAULT 0x00000000 +#define regGUS_L1_SA1_DATA_U_OUT_DEFAULT 0x00000000 +#define regGUS_L1_SA2_CMD_IN_DEFAULT 0x00000000 +#define regGUS_L1_SA2_CMD_OUT_DEFAULT 0x00000000 +#define regGUS_L1_SA2_DATA_IN_DEFAULT 0x00000000 +#define regGUS_L1_SA2_DATA_OUT_DEFAULT 0x00000000 +#define regGUS_L1_SA2_DATA_U_IN_DEFAULT 0x00000000 +#define regGUS_L1_SA2_DATA_U_OUT_DEFAULT 0x00000000 +#define regGUS_L1_SA3_CMD_IN_DEFAULT 0x00000000 +#define regGUS_L1_SA3_CMD_OUT_DEFAULT 0x00000000 +#define regGUS_L1_SA3_DATA_IN_DEFAULT 0x00000000 +#define regGUS_L1_SA3_DATA_OUT_DEFAULT 0x00000000 +#define regGUS_L1_SA3_DATA_U_IN_DEFAULT 0x00000000 +#define regGUS_L1_SA3_DATA_U_OUT_DEFAULT 0x00000000 +#define regGUS_MISC3_DEFAULT 0x00000000 +#define regGUS_WRRSP_FIFO_CNTL_DEFAULT 0x0000000a + + +// addressBlock: gc_gl1dec +#define regGL1_DRAM_BURST_MASK_DEFAULT 0x000000cf +#define regGL1_ARB_STATUS_DEFAULT 0x00000000 +#define regGL1I_GL1R_REP_FGCG_OVERRIDE_DEFAULT 0x00000000 +#define regGL1C_STATUS_DEFAULT 0x80000000 +#define regGL1C_UTCL0_CNTL2_DEFAULT 0x00000010 +#define regGL1C_UTCL0_STATUS_DEFAULT 0x00000000 +#define regGL1C_UTCL0_RETRY_DEFAULT 0x00000040 + + +// addressBlock: gc_chdec +#define regCH_ARB_CTRL_DEFAULT 0x00001e02 +#define regCH_DRAM_BURST_MASK_DEFAULT 0x000000cf +#define regCH_ARB_STATUS_DEFAULT 0x00000000 +#define regCH_DRAM_BURST_CTRL_DEFAULT 0x000001f7 +#define regCHA_CHC_CREDITS_DEFAULT 0x00000000 +#define regCHA_CLIENT_FREE_DELAY_DEFAULT 0x00000000 +#define regCHI_CHR_REP_FGCG_OVERRIDE_DEFAULT 0x00000000 +#define regCH_VC5_ENABLE_DEFAULT 0x00000000 +#define regCHC_CTRL_DEFAULT 0x0000b16f +#define regCHC_STATUS_DEFAULT 0x00000000 +#define regCHCG_CTRL_DEFAULT 0x001830ff +#define regCHCG_STATUS_DEFAULT 0x00000000 + + +// addressBlock: gc_gl2dec +#define regGL2C_CTRL_DEFAULT 0xf37fff7f +#define regGL2C_CTRL2_DEFAULT 0x0402002f +#define regGL2C_ADDR_MATCH_MASK_DEFAULT 0xffffffff +#define regGL2C_ADDR_MATCH_SIZE_DEFAULT 0x00000007 +#define regGL2C_WBINVL2_DEFAULT 0x00000010 +#define regGL2C_SOFT_RESET_DEFAULT 0x00000000 +#define regGL2C_CM_CTRL0_DEFAULT 0x42108421 +#define regGL2C_CM_CTRL1_DEFAULT 0x190f1008 +#define regGL2C_CM_STALL_DEFAULT 0x00000000 +#define regGL2C_CTRL3_DEFAULT 0xc0d41988 +#define regGL2C_LB_CTR_CTRL_DEFAULT 0x00000000 +#define regGL2C_LB_DATA0_DEFAULT 0x00000000 +#define regGL2C_LB_DATA1_DEFAULT 0x00000000 +#define regGL2C_LB_DATA2_DEFAULT 0x00000000 +#define regGL2C_LB_DATA3_DEFAULT 0x00000000 +#define regGL2C_LB_CTR_SEL0_DEFAULT 0x00000000 +#define regGL2C_LB_CTR_SEL1_DEFAULT 0x00000000 +#define regGL2C_CTRL4_DEFAULT 0x04000007 +#define regGL2C_DISCARD_STALL_CTRL_DEFAULT 0x00c800c8 +#define regGL2A_ADDR_MATCH_CTRL_DEFAULT 0x00000000 +#define regGL2A_ADDR_MATCH_MASK_DEFAULT 0xffffffff +#define regGL2A_ADDR_MATCH_SIZE_DEFAULT 0x00000007 +#define regGL2A_PRIORITY_CTRL_DEFAULT 0x00000000 +#define regGL2A_RESP_THROTTLE_CTRL_DEFAULT 0x00000000 + + +// addressBlock: gc_gl1hdec +#define regGL1H_ARB_CTRL_DEFAULT 0x00000000 +#define regGL1H_GL1_CREDITS_DEFAULT 0x00000000 +#define regGL1H_BURST_MASK_DEFAULT 0x000000cf +#define regGL1H_BURST_CTRL_DEFAULT 0x00000007 +#define regGL1H_ARB_STATUS_DEFAULT 0x00000000 + + +// addressBlock: gc_perfddec +#define regCPG_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regCPG_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regCPG_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regCPG_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regCPC_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regCPC_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regCPC_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regCPC_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regCPF_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regCPF_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regCPF_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regCPF_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regCPF_LATENCY_STATS_DATA_DEFAULT 0x00000000 +#define regCPG_LATENCY_STATS_DATA_DEFAULT 0x00000000 +#define regCPC_LATENCY_STATS_DATA_DEFAULT 0x00000000 +#define regGRBM_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regGRBM_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regGRBM_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regGRBM_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regGRBM_SE0_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define regGRBM_SE0_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define regGRBM_SE1_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define regGRBM_SE1_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define regGRBM_SE2_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define regGRBM_SE2_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define regGRBM_SE3_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define regGRBM_SE3_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define regGRBM_SE4_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define regGRBM_SE4_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define regGRBM_SE5_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define regGRBM_SE5_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define regGRBM_SE6_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define regGRBM_SE6_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define regGE1_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regGE1_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regGE1_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regGE1_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regGE1_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regGE1_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regGE1_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regGE1_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regGE2_DIST_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regGE2_DIST_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regGE2_DIST_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regGE2_DIST_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regGE2_DIST_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regGE2_DIST_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regGE2_DIST_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regGE2_DIST_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regGE2_SE_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regGE2_SE_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regGE2_SE_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regGE2_SE_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regGE2_SE_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regGE2_SE_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regGE2_SE_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regGE2_SE_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regPA_SU_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regPA_SU_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regPA_SU_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regPA_SU_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regPA_SU_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regPA_SU_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regPA_SU_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regPA_SU_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regPA_SC_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regPA_SC_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regPA_SC_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regPA_SC_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regPA_SC_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regPA_SC_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regPA_SC_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regPA_SC_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regPA_SC_PERFCOUNTER4_LO_DEFAULT 0x00000000 +#define regPA_SC_PERFCOUNTER4_HI_DEFAULT 0x00000000 +#define regPA_SC_PERFCOUNTER5_LO_DEFAULT 0x00000000 +#define regPA_SC_PERFCOUNTER5_HI_DEFAULT 0x00000000 +#define regPA_SC_PERFCOUNTER6_LO_DEFAULT 0x00000000 +#define regPA_SC_PERFCOUNTER6_HI_DEFAULT 0x00000000 +#define regPA_SC_PERFCOUNTER7_LO_DEFAULT 0x00000000 +#define regPA_SC_PERFCOUNTER7_HI_DEFAULT 0x00000000 +#define regSPI_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regSPI_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regSPI_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regSPI_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regSPI_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regSPI_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regSPI_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regSPI_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regSPI_PERFCOUNTER4_HI_DEFAULT 0x00000000 +#define regSPI_PERFCOUNTER4_LO_DEFAULT 0x00000000 +#define regSPI_PERFCOUNTER5_HI_DEFAULT 0x00000000 +#define regSPI_PERFCOUNTER5_LO_DEFAULT 0x00000000 +#define regPC_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regPC_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regPC_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regPC_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regPC_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regPC_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regPC_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regPC_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regSQ_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regSQ_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regSQ_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regSQ_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regSQ_PERFCOUNTER4_LO_DEFAULT 0x00000000 +#define regSQ_PERFCOUNTER5_LO_DEFAULT 0x00000000 +#define regSQ_PERFCOUNTER6_LO_DEFAULT 0x00000000 +#define regSQ_PERFCOUNTER7_LO_DEFAULT 0x00000000 +#define regSQG_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regSQG_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regSQG_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regSQG_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regSQG_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regSQG_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regSQG_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regSQG_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regSQG_PERFCOUNTER4_LO_DEFAULT 0x00000000 +#define regSQG_PERFCOUNTER4_HI_DEFAULT 0x00000000 +#define regSQG_PERFCOUNTER5_LO_DEFAULT 0x00000000 +#define regSQG_PERFCOUNTER5_HI_DEFAULT 0x00000000 +#define regSQG_PERFCOUNTER6_LO_DEFAULT 0x00000000 +#define regSQG_PERFCOUNTER6_HI_DEFAULT 0x00000000 +#define regSQG_PERFCOUNTER7_LO_DEFAULT 0x00000000 +#define regSQG_PERFCOUNTER7_HI_DEFAULT 0x00000000 +#define regSX_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regSX_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regSX_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regSX_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regSX_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regSX_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regSX_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regSX_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regGCEA_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regGCEA_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regGCEA_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define regGCEA_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define regGDS_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regGDS_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regGDS_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regGDS_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regGDS_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regGDS_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regGDS_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regGDS_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regTA_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regTA_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regTA_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regTA_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regTD_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regTD_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regTD_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regTD_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regTCP_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regTCP_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regTCP_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regTCP_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regTCP_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regTCP_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regTCP_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regTCP_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regTCP_PERFCOUNTER_FILTER_DEFAULT 0x00000000 +#define regTCP_PERFCOUNTER_FILTER2_DEFAULT 0x00000000 +#define regTCP_PERFCOUNTER_FILTER_EN_DEFAULT 0x00000000 +#define regGL2C_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regGL2C_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regGL2C_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regGL2C_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regGL2C_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regGL2C_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regGL2C_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regGL2C_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regGL2A_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regGL2A_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regGL2A_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regGL2A_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regGL2A_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regGL2A_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regGL2A_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regGL2A_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regGL1C_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regGL1C_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regGL1C_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regGL1C_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regGL1C_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regGL1C_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regGL1C_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regGL1C_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regCHC_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regCHC_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regCHC_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regCHC_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regCHC_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regCHC_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regCHC_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regCHC_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regCHCG_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regCHCG_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regCHCG_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regCHCG_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regCHCG_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regCHCG_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regCHCG_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regCHCG_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regCB_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regCB_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regCB_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regCB_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regCB_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regCB_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regCB_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regCB_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regDB_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regDB_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regDB_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regDB_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regDB_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regDB_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regDB_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regDB_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regRLC_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regRLC_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regRLC_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regRLC_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regRMI_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regRMI_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regRMI_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regRMI_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regRMI_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regRMI_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regRMI_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regRMI_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regGCR_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regGCR_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regGCR_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regGCR_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regPA_PH_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regPA_PH_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regPA_PH_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regPA_PH_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regPA_PH_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regPA_PH_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regPA_PH_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regPA_PH_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regPA_PH_PERFCOUNTER4_LO_DEFAULT 0x00000000 +#define regPA_PH_PERFCOUNTER4_HI_DEFAULT 0x00000000 +#define regPA_PH_PERFCOUNTER5_LO_DEFAULT 0x00000000 +#define regPA_PH_PERFCOUNTER5_HI_DEFAULT 0x00000000 +#define regPA_PH_PERFCOUNTER6_LO_DEFAULT 0x00000000 +#define regPA_PH_PERFCOUNTER6_HI_DEFAULT 0x00000000 +#define regPA_PH_PERFCOUNTER7_LO_DEFAULT 0x00000000 +#define regPA_PH_PERFCOUNTER7_HI_DEFAULT 0x00000000 +#define regUTCL1_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regUTCL1_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regUTCL1_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regUTCL1_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regUTCL1_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regUTCL1_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regUTCL1_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regUTCL1_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regGL1A_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regGL1A_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regGL1A_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regGL1A_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regGL1A_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regGL1A_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regGL1A_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regGL1A_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regGL1H_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regGL1H_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regGL1H_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regGL1H_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regGL1H_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regGL1H_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regGL1H_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regGL1H_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regCHA_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regCHA_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regCHA_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regCHA_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define regCHA_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regCHA_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regCHA_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define regCHA_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define regGUS_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define regGUS_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define regGUS_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define regGUS_PERFCOUNTER_HI_DEFAULT 0x00000000 + + +// addressBlock: gc_gcvml2perfddec +#define regGCVML2_PERFCOUNTER2_0_LO_DEFAULT 0x00000000 +#define regGCVML2_PERFCOUNTER2_1_LO_DEFAULT 0x00000000 +#define regGCVML2_PERFCOUNTER2_0_HI_DEFAULT 0x00000000 +#define regGCVML2_PERFCOUNTER2_1_HI_DEFAULT 0x00000000 + + +// addressBlock: gc_gcvml2prdec +#define regGCMC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define regGCMC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define regGCUTCL2_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define regGCUTCL2_PERFCOUNTER_HI_DEFAULT 0x00000000 + + +// addressBlock: gc_sdma0_sdma0perfddec +#define regSDMA0_PERFCNT_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define regSDMA0_PERFCNT_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define regSDMA0_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regSDMA0_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regSDMA0_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regSDMA0_PERFCOUNTER1_HI_DEFAULT 0x00000000 + + +// addressBlock: gc_sdma0_sdma1perfddec +#define regSDMA1_PERFCNT_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define regSDMA1_PERFCNT_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define regSDMA1_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define regSDMA1_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define regSDMA1_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define regSDMA1_PERFCOUNTER1_HI_DEFAULT 0x00000000 + + +// addressBlock: gc_perfsdec +#define regCPG_PERFCOUNTER1_SELECT_DEFAULT 0x000003ff +#define regCPG_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regCPG_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regCPC_PERFCOUNTER1_SELECT_DEFAULT 0x000003ff +#define regCPC_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regCPF_PERFCOUNTER1_SELECT_DEFAULT 0x000003ff +#define regCPF_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regCPF_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regCP_PERFMON_CNTL_DEFAULT 0x00000000 +#define regCPC_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regCPF_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT 0x00000000 +#define regCPG_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT 0x00000000 +#define regCPF_LATENCY_STATS_SELECT_DEFAULT 0x00000000 +#define regCPG_LATENCY_STATS_SELECT_DEFAULT 0x00000000 +#define regCPC_LATENCY_STATS_SELECT_DEFAULT 0x00000000 +#define regCPC_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT 0x00000000 +#define regCP_DRAW_OBJECT_DEFAULT 0x00000000 +#define regCP_DRAW_OBJECT_COUNTER_DEFAULT 0x00000000 +#define regCP_DRAW_WINDOW_MASK_HI_DEFAULT 0x00000000 +#define regCP_DRAW_WINDOW_HI_DEFAULT 0x00000000 +#define regCP_DRAW_WINDOW_LO_DEFAULT 0x00000000 +#define regCP_DRAW_WINDOW_CNTL_DEFAULT 0x00000007 +#define regGRBM_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 +#define regGRBM_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 +#define regGRBM_SE0_PERFCOUNTER_SELECT_DEFAULT 0x00000000 +#define regGRBM_SE1_PERFCOUNTER_SELECT_DEFAULT 0x00000000 +#define regGRBM_SE2_PERFCOUNTER_SELECT_DEFAULT 0x00000000 +#define regGRBM_SE3_PERFCOUNTER_SELECT_DEFAULT 0x00000000 +#define regGRBM_SE4_PERFCOUNTER_SELECT_DEFAULT 0x00000000 +#define regGRBM_SE5_PERFCOUNTER_SELECT_DEFAULT 0x00000000 +#define regGRBM_SE6_PERFCOUNTER_SELECT_DEFAULT 0x00000000 +#define regGRBM_PERFCOUNTER0_SELECT_HI_DEFAULT 0x00000000 +#define regGRBM_PERFCOUNTER1_SELECT_HI_DEFAULT 0x00000000 +#define regGE1_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regGE1_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regGE1_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff +#define regGE1_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff +#define regGE1_PERFCOUNTER2_SELECT_DEFAULT 0x000fffff +#define regGE1_PERFCOUNTER2_SELECT1_DEFAULT 0x000fffff +#define regGE1_PERFCOUNTER3_SELECT_DEFAULT 0x000fffff +#define regGE1_PERFCOUNTER3_SELECT1_DEFAULT 0x000fffff +#define regGE2_DIST_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regGE2_DIST_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regGE2_DIST_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff +#define regGE2_DIST_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff +#define regGE2_DIST_PERFCOUNTER2_SELECT_DEFAULT 0x000fffff +#define regGE2_DIST_PERFCOUNTER2_SELECT1_DEFAULT 0x000fffff +#define regGE2_DIST_PERFCOUNTER3_SELECT_DEFAULT 0x000fffff +#define regGE2_DIST_PERFCOUNTER3_SELECT1_DEFAULT 0x000fffff +#define regGE2_SE_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regGE2_SE_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regGE2_SE_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff +#define regGE2_SE_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff +#define regGE2_SE_PERFCOUNTER2_SELECT_DEFAULT 0x000fffff +#define regGE2_SE_PERFCOUNTER2_SELECT1_DEFAULT 0x000fffff +#define regGE2_SE_PERFCOUNTER3_SELECT_DEFAULT 0x000fffff +#define regGE2_SE_PERFCOUNTER3_SELECT1_DEFAULT 0x000fffff +#define regPA_SU_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regPA_SU_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regPA_SU_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff +#define regPA_SU_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff +#define regPA_SU_PERFCOUNTER2_SELECT_DEFAULT 0x000fffff +#define regPA_SU_PERFCOUNTER2_SELECT1_DEFAULT 0x000fffff +#define regPA_SU_PERFCOUNTER3_SELECT_DEFAULT 0x000fffff +#define regPA_SU_PERFCOUNTER3_SELECT1_DEFAULT 0x000fffff +#define regPA_SC_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regPA_SC_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regPA_SC_PERFCOUNTER1_SELECT_DEFAULT 0x000003ff +#define regPA_SC_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff +#define regPA_SC_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff +#define regPA_SC_PERFCOUNTER4_SELECT_DEFAULT 0x000003ff +#define regPA_SC_PERFCOUNTER5_SELECT_DEFAULT 0x000003ff +#define regPA_SC_PERFCOUNTER6_SELECT_DEFAULT 0x000003ff +#define regPA_SC_PERFCOUNTER7_SELECT_DEFAULT 0x000003ff +#define regSPI_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regSPI_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff +#define regSPI_PERFCOUNTER2_SELECT_DEFAULT 0x000fffff +#define regSPI_PERFCOUNTER3_SELECT_DEFAULT 0x000fffff +#define regSPI_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regSPI_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff +#define regSPI_PERFCOUNTER2_SELECT1_DEFAULT 0x000fffff +#define regSPI_PERFCOUNTER3_SELECT1_DEFAULT 0x000fffff +#define regSPI_PERFCOUNTER4_SELECT_DEFAULT 0x000003ff +#define regSPI_PERFCOUNTER5_SELECT_DEFAULT 0x000003ff +#define regSPI_PERFCOUNTER_BINS_DEFAULT 0xfcb87430 +#define regPC_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regPC_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff +#define regPC_PERFCOUNTER2_SELECT_DEFAULT 0x000fffff +#define regPC_PERFCOUNTER3_SELECT_DEFAULT 0x000fffff +#define regPC_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regPC_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff +#define regPC_PERFCOUNTER2_SELECT1_DEFAULT 0x000fffff +#define regPC_PERFCOUNTER3_SELECT1_DEFAULT 0x000fffff +#define regSQ_PERFCOUNTER0_SELECT_DEFAULT 0x000001ff +#define regSQ_PERFCOUNTER1_SELECT_DEFAULT 0x000001ff +#define regSQ_PERFCOUNTER2_SELECT_DEFAULT 0x000001ff +#define regSQ_PERFCOUNTER3_SELECT_DEFAULT 0x000001ff +#define regSQ_PERFCOUNTER4_SELECT_DEFAULT 0x000001ff +#define regSQ_PERFCOUNTER5_SELECT_DEFAULT 0x000001ff +#define regSQ_PERFCOUNTER6_SELECT_DEFAULT 0x000001ff +#define regSQ_PERFCOUNTER7_SELECT_DEFAULT 0x000001ff +#define regSQ_PERFCOUNTER8_SELECT_DEFAULT 0x000001ff +#define regSQ_PERFCOUNTER9_SELECT_DEFAULT 0x000001ff +#define regSQ_PERFCOUNTER10_SELECT_DEFAULT 0x000001ff +#define regSQ_PERFCOUNTER11_SELECT_DEFAULT 0x000001ff +#define regSQ_PERFCOUNTER12_SELECT_DEFAULT 0x000001ff +#define regSQ_PERFCOUNTER13_SELECT_DEFAULT 0x000001ff +#define regSQ_PERFCOUNTER14_SELECT_DEFAULT 0x000001ff +#define regSQ_PERFCOUNTER15_SELECT_DEFAULT 0x000001ff +#define regSQG_PERFCOUNTER0_SELECT_DEFAULT 0x000001ff +#define regSQG_PERFCOUNTER1_SELECT_DEFAULT 0x000001ff +#define regSQG_PERFCOUNTER2_SELECT_DEFAULT 0x000001ff +#define regSQG_PERFCOUNTER3_SELECT_DEFAULT 0x000001ff +#define regSQG_PERFCOUNTER4_SELECT_DEFAULT 0x000001ff +#define regSQG_PERFCOUNTER5_SELECT_DEFAULT 0x000001ff +#define regSQG_PERFCOUNTER6_SELECT_DEFAULT 0x000001ff +#define regSQG_PERFCOUNTER7_SELECT_DEFAULT 0x000001ff +#define regSQG_PERFCOUNTER_CTRL_DEFAULT 0x00000000 +#define regSQG_PERFCOUNTER_CTRL2_DEFAULT 0x0001fffe +#define regSQG_PERF_SAMPLE_FINISH_DEFAULT 0x00000000 +#define regSQ_PERFCOUNTER_CTRL_DEFAULT 0x00000000 +#define regSQ_PERFCOUNTER_CTRL2_DEFAULT 0x0001fffe +#define regSQ_THREAD_TRACE_BUF0_BASE_DEFAULT 0x00000000 +#define regSQ_THREAD_TRACE_BUF0_SIZE_DEFAULT 0x00000000 +#define regSQ_THREAD_TRACE_BUF1_BASE_DEFAULT 0x00000000 +#define regSQ_THREAD_TRACE_BUF1_SIZE_DEFAULT 0x00000000 +#define regSQ_THREAD_TRACE_CTRL_DEFAULT 0x00400000 +#define regSQ_THREAD_TRACE_MASK_DEFAULT 0x00000000 +#define regSQ_THREAD_TRACE_TOKEN_MASK_DEFAULT 0x00000000 +#define regSQ_THREAD_TRACE_WPTR_DEFAULT 0x00000000 +#define regSQ_THREAD_TRACE_STATUS_DEFAULT 0x00000000 +#define regSQ_THREAD_TRACE_STATUS2_DEFAULT 0x00000000 +#define regSQ_THREAD_TRACE_GFX_DRAW_CNTR_DEFAULT 0x00000000 +#define regSQ_THREAD_TRACE_GFX_MARKER_CNTR_DEFAULT 0x00000000 +#define regSQ_THREAD_TRACE_HP3D_DRAW_CNTR_DEFAULT 0x00000000 +#define regSQ_THREAD_TRACE_HP3D_MARKER_CNTR_DEFAULT 0x00000000 +#define regSQ_THREAD_TRACE_DROPPED_CNTR_DEFAULT 0x00000000 +#define regGCEA_PERFCOUNTER2_SELECT_DEFAULT 0x000fffff +#define regGCEA_PERFCOUNTER2_SELECT1_DEFAULT 0x000fffff +#define regGCEA_PERFCOUNTER2_MODE_DEFAULT 0x00000000 +#define regGCEA_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define regGCEA_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define regGCEA_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define regSX_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regSX_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff +#define regSX_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff +#define regSX_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff +#define regSX_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regSX_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff +#define regGDS_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regGDS_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff +#define regGDS_PERFCOUNTER2_SELECT_DEFAULT 0x000fffff +#define regGDS_PERFCOUNTER3_SELECT_DEFAULT 0x000fffff +#define regGDS_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regGDS_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff +#define regGDS_PERFCOUNTER2_SELECT1_DEFAULT 0x000fffff +#define regGDS_PERFCOUNTER3_SELECT1_DEFAULT 0x000fffff +#define regTA_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regTA_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regTA_PERFCOUNTER1_SELECT_DEFAULT 0x000003ff +#define regTD_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regTD_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regTD_PERFCOUNTER1_SELECT_DEFAULT 0x000003ff +#define regTCP_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regTCP_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regTCP_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff +#define regTCP_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff +#define regTCP_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff +#define regTCP_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff +#define regGL2C_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regGL2C_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regGL2C_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff +#define regGL2C_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff +#define regGL2C_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff +#define regGL2C_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff +#define regGL2A_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regGL2A_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regGL2A_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff +#define regGL2A_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff +#define regGL2A_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff +#define regGL2A_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff +#define regGL1C_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regGL1C_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regGL1C_PERFCOUNTER1_SELECT_DEFAULT 0x000003ff +#define regGL1C_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff +#define regGL1C_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff +#define regCHC_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regCHC_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regCHC_PERFCOUNTER1_SELECT_DEFAULT 0x000003ff +#define regCHC_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff +#define regCHC_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff +#define regCHCG_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regCHCG_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regCHCG_PERFCOUNTER1_SELECT_DEFAULT 0x000003ff +#define regCHCG_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff +#define regCHCG_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff +#define regCB_PERFCOUNTER_FILTER_DEFAULT 0x00000000 +#define regCB_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regCB_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regCB_PERFCOUNTER1_SELECT_DEFAULT 0x000003ff +#define regCB_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff +#define regCB_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff +#define regDB_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regDB_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regDB_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff +#define regDB_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff +#define regDB_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff +#define regDB_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff +#define regRLC_SPM_PERFMON_CNTL_DEFAULT 0x00000000 +#define regRLC_SPM_PERFMON_RING_BASE_LO_DEFAULT 0x00000000 +#define regRLC_SPM_PERFMON_RING_BASE_HI_DEFAULT 0x00000000 +#define regRLC_SPM_PERFMON_RING_SIZE_DEFAULT 0x00000000 +#define regRLC_SPM_RING_WRPTR_DEFAULT 0x00000000 +#define regRLC_SPM_RING_RDPTR_DEFAULT 0x00000000 +#define regRLC_SPM_SEGMENT_THRESHOLD_DEFAULT 0x00000000 +#define regRLC_SPM_PERFMON_SEGMENT_SIZE_DEFAULT 0x00000000 +#define regRLC_SPM_GLOBAL_MUXSEL_ADDR_DEFAULT 0x00000000 +#define regRLC_SPM_GLOBAL_MUXSEL_DATA_DEFAULT 0x00000000 +#define regRLC_SPM_SE_MUXSEL_ADDR_DEFAULT 0x00000000 +#define regRLC_SPM_SE_MUXSEL_DATA_DEFAULT 0x00000000 +#define regRLC_SPM_ACCUM_DATARAM_ADDR_DEFAULT 0x00000000 +#define regRLC_SPM_ACCUM_DATARAM_DATA_DEFAULT 0x00000000 +#define regRLC_SPM_ACCUM_SWA_DATARAM_ADDR_DEFAULT 0x00000000 +#define regRLC_SPM_ACCUM_SWA_DATARAM_DATA_DEFAULT 0x00000000 +#define regRLC_SPM_ACCUM_CTRLRAM_ADDR_DEFAULT 0x00000000 +#define regRLC_SPM_ACCUM_CTRLRAM_DATA_DEFAULT 0x00000000 +#define regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_DEFAULT 0x00000008 +#define regRLC_SPM_ACCUM_STATUS_DEFAULT 0x00184800 +#define regRLC_SPM_ACCUM_CTRL_DEFAULT 0x00000000 +#define regRLC_SPM_ACCUM_MODE_DEFAULT 0x007fe004 +#define regRLC_SPM_ACCUM_THRESHOLD_DEFAULT 0x00000001 +#define regRLC_SPM_ACCUM_SAMPLES_REQUESTED_DEFAULT 0x00000001 +#define regRLC_SPM_ACCUM_DATARAM_WRCOUNT_DEFAULT 0x00000000 +#define regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_DEFAULT 0x0000ffff +#define regRLC_SPM_PAUSE_DEFAULT 0x00000000 +#define regRLC_SPM_STATUS_DEFAULT 0x00000000 +#define regRLC_SPM_GFXCLOCK_LOWCOUNT_DEFAULT 0x00000000 +#define regRLC_SPM_GFXCLOCK_HIGHCOUNT_DEFAULT 0x00000000 +#define regRLC_SPM_MODE_DEFAULT 0x00000000 +#define regRLC_SPM_RSPM_REQ_DATA_LO_DEFAULT 0x00000000 +#define regRLC_SPM_RSPM_REQ_DATA_HI_DEFAULT 0x00000000 +#define regRLC_SPM_RSPM_REQ_OP_DEFAULT 0x00000000 +#define regRLC_SPM_RSPM_RET_DATA_DEFAULT 0x00000000 +#define regRLC_SPM_RSPM_RET_OP_DEFAULT 0x00000000 +#define regRLC_SPM_SE_RSPM_REQ_DATA_LO_DEFAULT 0x00000000 +#define regRLC_SPM_SE_RSPM_REQ_DATA_HI_DEFAULT 0x00000000 +#define regRLC_SPM_SE_RSPM_REQ_OP_DEFAULT 0x00000000 +#define regRLC_SPM_SE_RSPM_RET_DATA_DEFAULT 0x00000000 +#define regRLC_SPM_SE_RSPM_RET_OP_DEFAULT 0x00000000 +#define regRLC_SPM_RSPM_CMD_DEFAULT 0x00000000 +#define regRLC_SPM_RSPM_CMD_ACK_DEFAULT 0x00000000 +#define regRLC_SPM_SPARE_DEFAULT 0x00000000 +#define regRLC_PERFMON_CNTL_DEFAULT 0x00000000 +#define regRLC_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 +#define regRLC_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_PERF_CNT_CNTL_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_PERF_CNT_WR_ADDR_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_PERF_CNT_WR_DATA_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_PERF_CNT_RD_ADDR_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_PERF_CNT_RD_DATA_DEFAULT 0x00000000 +#define regRMI_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regRMI_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regRMI_PERFCOUNTER1_SELECT_DEFAULT 0x000003ff +#define regRMI_PERFCOUNTER2_SELECT_DEFAULT 0x000fffff +#define regRMI_PERFCOUNTER2_SELECT1_DEFAULT 0x000fffff +#define regRMI_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff +#define regRMI_PERF_COUNTER_CNTL_DEFAULT 0x00080240 +#define regGCR_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regGCR_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regGCR_PERFCOUNTER1_SELECT_DEFAULT 0x000003ff +#define regPA_PH_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regPA_PH_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regPA_PH_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff +#define regPA_PH_PERFCOUNTER2_SELECT_DEFAULT 0x000fffff +#define regPA_PH_PERFCOUNTER3_SELECT_DEFAULT 0x000fffff +#define regPA_PH_PERFCOUNTER4_SELECT_DEFAULT 0x000003ff +#define regPA_PH_PERFCOUNTER5_SELECT_DEFAULT 0x000003ff +#define regPA_PH_PERFCOUNTER6_SELECT_DEFAULT 0x000003ff +#define regPA_PH_PERFCOUNTER7_SELECT_DEFAULT 0x000003ff +#define regPA_PH_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff +#define regPA_PH_PERFCOUNTER2_SELECT1_DEFAULT 0x000fffff +#define regPA_PH_PERFCOUNTER3_SELECT1_DEFAULT 0x000fffff +#define regUTCL1_PERFCOUNTER0_SELECT_DEFAULT 0x000003ff +#define regUTCL1_PERFCOUNTER1_SELECT_DEFAULT 0x000003ff +#define regUTCL1_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff +#define regUTCL1_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff +#define regGL1A_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regGL1A_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regGL1A_PERFCOUNTER1_SELECT_DEFAULT 0x000003ff +#define regGL1A_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff +#define regGL1A_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff +#define regGL1H_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regGL1H_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regGL1H_PERFCOUNTER1_SELECT_DEFAULT 0x000003ff +#define regGL1H_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff +#define regGL1H_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff +#define regCHA_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regCHA_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regCHA_PERFCOUNTER1_SELECT_DEFAULT 0x000003ff +#define regCHA_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff +#define regCHA_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff +#define regGUS_PERFCOUNTER2_SELECT_DEFAULT 0x000fffff +#define regGUS_PERFCOUNTER2_SELECT1_DEFAULT 0x000fffff +#define regGUS_PERFCOUNTER2_MODE_DEFAULT 0x00000000 +#define regGUS_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define regGUS_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define regGUS_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 + + +// addressBlock: gc_gcvml2perfsdec +#define regGCVML2_PERFCOUNTER2_0_SELECT_DEFAULT 0x000fffff +#define regGCVML2_PERFCOUNTER2_1_SELECT_DEFAULT 0x000fffff +#define regGCVML2_PERFCOUNTER2_0_SELECT1_DEFAULT 0x000fffff +#define regGCVML2_PERFCOUNTER2_1_SELECT1_DEFAULT 0x000fffff +#define regGCVML2_PERFCOUNTER2_0_MODE_DEFAULT 0x00000000 +#define regGCVML2_PERFCOUNTER2_1_MODE_DEFAULT 0x00000000 + + +// addressBlock: gc_gcvml2pldec +#define regGCMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define regGCMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define regGCMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 +#define regGCMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000 +#define regGCMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000 +#define regGCMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000 +#define regGCMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000 +#define regGCMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000 +#define regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define regGCUTCL2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define regGCUTCL2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define regGCUTCL2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 +#define regGCUTCL2_PERFCOUNTER3_CFG_DEFAULT 0x00000000 +#define regGCUTCL2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 + + +// addressBlock: gc_sdma0_sdma0perfsdec +#define regSDMA0_PERFCNT_PERFCOUNTER0_CFG_DEFAULT 0x0000ffff +#define regSDMA0_PERFCNT_PERFCOUNTER1_CFG_DEFAULT 0x0000ffff +#define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define regSDMA0_PERFCNT_MISC_CNTL_DEFAULT 0x00000000 +#define regSDMA0_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regSDMA0_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regSDMA0_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff +#define regSDMA0_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff + + +// addressBlock: gc_sdma0_sdma1perfsdec +#define regSDMA1_PERFCNT_PERFCOUNTER0_CFG_DEFAULT 0x0000ffff +#define regSDMA1_PERFCNT_PERFCOUNTER1_CFG_DEFAULT 0x0000ffff +#define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define regSDMA1_PERFCNT_MISC_CNTL_DEFAULT 0x00000000 +#define regSDMA1_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define regSDMA1_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define regSDMA1_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff +#define regSDMA1_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff + + +// addressBlock: gc_gfx_imu_gfx_imudec +#define regGFX_IMU_C2PMSG_0_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_1_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_2_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_3_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_4_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_5_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_6_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_7_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_8_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_9_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_10_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_11_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_12_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_13_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_14_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_15_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_16_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_17_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_18_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_19_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_20_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_21_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_22_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_23_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_24_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_25_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_26_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_27_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_28_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_29_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_30_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_31_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_32_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_33_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_34_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_35_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_36_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_37_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_38_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_39_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_40_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_41_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_42_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_43_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_44_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_45_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_46_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_47_DEFAULT 0x00000000 +#define regGFX_IMU_MSG_FLAGS_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_ACCESS_CTRL0_DEFAULT 0x00000000 +#define regGFX_IMU_C2PMSG_ACCESS_CTRL1_DEFAULT 0x00000000 +#define regGFX_IMU_PWRMGT_IRQ_CTRL_DEFAULT 0x00000000 +#define regGFX_IMU_MP1_MUTEX_DEFAULT 0x00000000 +#define regGFX_IMU_RLC_DATA_4_DEFAULT 0x00000000 +#define regGFX_IMU_RLC_DATA_3_DEFAULT 0x00000000 +#define regGFX_IMU_RLC_DATA_2_DEFAULT 0x00000000 +#define regGFX_IMU_RLC_DATA_1_DEFAULT 0x00000000 +#define regGFX_IMU_RLC_DATA_0_DEFAULT 0x00000000 +#define regGFX_IMU_RLC_CMD_DEFAULT 0x00000000 +#define regGFX_IMU_RLC_MUTEX_DEFAULT 0x00000000 +#define regGFX_IMU_RLC_MSG_STATUS_DEFAULT 0x00000000 +#define regRLC_GFX_IMU_DATA_0_DEFAULT 0x00000000 +#define regRLC_GFX_IMU_CMD_DEFAULT 0x00000000 +#define regGFX_IMU_RLC_STATUS_DEFAULT 0x00000000 +#define regGFX_IMU_STATUS_DEFAULT 0x00000000 +#define regGFX_IMU_SOC_DATA_DEFAULT 0x00000000 +#define regGFX_IMU_SOC_ADDR_DEFAULT 0x00000000 +#define regGFX_IMU_SOC_REQ_DEFAULT 0x00000000 +#define regGFX_IMU_VF_CTRL_DEFAULT 0x00000080 +#define regGFX_IMU_TELEMETRY_DEFAULT 0x00003000 +#define regGFX_IMU_TELEMETRY_DATA_DEFAULT 0x00000000 +#define regGFX_IMU_TELEMETRY_TEMPERATURE_DEFAULT 0x00000000 +#define regGFX_IMU_SCRATCH_0_DEFAULT 0x00000000 +#define regGFX_IMU_SCRATCH_1_DEFAULT 0x00000000 +#define regGFX_IMU_SCRATCH_2_DEFAULT 0x00000000 +#define regGFX_IMU_SCRATCH_3_DEFAULT 0x00000000 +#define regGFX_IMU_SCRATCH_4_DEFAULT 0x00000000 +#define regGFX_IMU_SCRATCH_5_DEFAULT 0x00000000 +#define regGFX_IMU_SCRATCH_6_DEFAULT 0x00000000 +#define regGFX_IMU_SCRATCH_7_DEFAULT 0x00000000 +#define regGFX_IMU_SCRATCH_8_DEFAULT 0x00000000 +#define regGFX_IMU_SCRATCH_9_DEFAULT 0x00000000 +#define regGFX_IMU_SCRATCH_10_DEFAULT 0x00000000 +#define regGFX_IMU_SCRATCH_11_DEFAULT 0x00000000 +#define regGFX_IMU_SCRATCH_12_DEFAULT 0x00000000 +#define regGFX_IMU_SCRATCH_13_DEFAULT 0x00000000 +#define regGFX_IMU_SCRATCH_14_DEFAULT 0x00000000 +#define regGFX_IMU_SCRATCH_15_DEFAULT 0x00000000 +#define regGFX_IMU_FW_GTS_LO_DEFAULT 0x00000000 +#define regGFX_IMU_FW_GTS_HI_DEFAULT 0x00000000 +#define regGFX_IMU_GTS_OFFSET_LO_DEFAULT 0x00000000 +#define regGFX_IMU_GTS_OFFSET_HI_DEFAULT 0x00000000 +#define regGFX_IMU_RLC_GTS_OFFSET_LO_DEFAULT 0x00000000 +#define regGFX_IMU_RLC_GTS_OFFSET_HI_DEFAULT 0x00000000 +#define regGFX_IMU_CORE_INT_STATUS_DEFAULT 0x00000000 +#define regGFX_IMU_PIC_INT_MASK_DEFAULT 0x00000000 +#define regGFX_IMU_PIC_INT_LVL_DEFAULT 0x00000000 +#define regGFX_IMU_PIC_INT_EDGE_DEFAULT 0x00000000 +#define regGFX_IMU_PIC_INT_PRI_0_DEFAULT 0x03020100 +#define regGFX_IMU_PIC_INT_PRI_1_DEFAULT 0x07060504 +#define regGFX_IMU_PIC_INT_PRI_2_DEFAULT 0x0b0a0908 +#define regGFX_IMU_PIC_INT_PRI_3_DEFAULT 0x0f0e0d0c +#define regGFX_IMU_PIC_INT_PRI_4_DEFAULT 0x13121110 +#define regGFX_IMU_PIC_INT_PRI_5_DEFAULT 0x17161514 +#define regGFX_IMU_PIC_INT_PRI_6_DEFAULT 0x1b1a1918 +#define regGFX_IMU_PIC_INT_PRI_7_DEFAULT 0x1f1e1d1c +#define regGFX_IMU_PIC_INT_STATUS_DEFAULT 0x00000000 +#define regGFX_IMU_PIC_INTR_DEFAULT 0x00000001 +#define regGFX_IMU_PIC_INTR_ID_DEFAULT 0x00000000 +#define regGFX_IMU_IH_CTRL_1_DEFAULT 0x00000000 +#define regGFX_IMU_IH_CTRL_2_DEFAULT 0x80000000 +#define regGFX_IMU_IH_CTRL_3_DEFAULT 0x00000000 +#define regGFX_IMU_IH_STATUS_DEFAULT 0x00000000 +#define regGFX_IMU_FUSESTRAP_DEFAULT 0x00000000 +#define regGFX_IMU_SMUIO_VIDCHG_CTRL_DEFAULT 0x00000000 +#define regGFX_IMU_GFXCLK_BYPASS_CTRL_DEFAULT 0x00000001 +#define regGFX_IMU_CLK_CTRL_DEFAULT 0x20680013 +#define regGFX_IMU_DOORBELL_CONTROL_DEFAULT 0x00000000 +#define regGFX_IMU_RLC_CG_CTRL_DEFAULT 0x00000000 +#define regGFX_IMU_RLC_THROTTLE_GFX_DEFAULT 0x00000000 +#define regGFX_IMU_RLC_RESET_VECTOR_DEFAULT 0x00000000 +#define regGFX_IMU_RLC_OVERRIDE_DEFAULT 0x00000000 +#define regGFX_IMU_DPM_CONTROL_DEFAULT 0x00000000 +#define regGFX_IMU_DPM_ACC_DEFAULT 0x00000000 +#define regGFX_IMU_DPM_REF_COUNTER_DEFAULT 0x00000000 +#define regGFX_IMU_RLC_RAM_INDEX_DEFAULT 0x00000000 +#define regGFX_IMU_RLC_RAM_ADDR_HIGH_DEFAULT 0x00000000 +#define regGFX_IMU_RLC_RAM_ADDR_LOW_DEFAULT 0x00000000 +#define regGFX_IMU_RLC_RAM_DATA_DEFAULT 0x00000000 +#define regGFX_IMU_FENCE_CTRL_DEFAULT 0x00000002 +#define regGFX_IMU_FENCE_LOG_INIT_DEFAULT 0x00000000 +#define regGFX_IMU_FENCE_LOG_ADDR_DEFAULT 0x00000000 +#define regGFX_IMU_PROGRAM_CTR_DEFAULT 0x00000000 +#define regGFX_IMU_CORE_CTRL_DEFAULT 0x00000009 +#define regGFX_IMU_CORE_STATUS_DEFAULT 0x00000000 +#define regGFX_IMU_PWROKRAW_DEFAULT 0x00000000 +#define regGFX_IMU_PWROK_DEFAULT 0x00000000 +#define regGFX_IMU_GAP_PWROK_DEFAULT 0x00000000 +#define regGFX_IMU_RESETn_DEFAULT 0x00000000 +#define regGFX_IMU_GFX_RESET_CTRL_DEFAULT 0x00000010 +#define regGFX_IMU_AEB_OVERRIDE_DEFAULT 0x00000000 +#define regGFX_IMU_VDCI_RESET_CTRL_DEFAULT 0x0000000e +#define regGFX_IMU_GFX_ISO_CTRL_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER0_CTRL0_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER0_CTRL1_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER0_CMP_AUTOINC_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER0_CMP_INTEN_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER0_CMP0_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER0_CMP1_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER0_CMP3_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER0_VALUE_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER1_CTRL0_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER1_CTRL1_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER1_CMP_AUTOINC_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER1_CMP_INTEN_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER1_CMP0_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER1_CMP1_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER1_CMP3_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER1_VALUE_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER2_CTRL0_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER2_CTRL1_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER2_CMP_AUTOINC_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER2_CMP_INTEN_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER2_CMP0_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER2_CMP1_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER2_CMP3_DEFAULT 0x00000000 +#define regGFX_IMU_TIMER2_VALUE_DEFAULT 0x00000000 +#define regGFX_IMU_FUSE_CTRL_DEFAULT 0x00000000 +#define regGFX_IMU_D_RAM_ADDR_DEFAULT 0x00000000 +#define regGFX_IMU_D_RAM_DATA_DEFAULT 0x00000000 +#define regGFX_IMU_GFX_IH_GASKET_CTRL_DEFAULT 0x00000001 + + +// addressBlock: gc_gdfll_gdfll_dec +#define regGDFLL_EDC_HYSTERESIS_CNTL_DEFAULT 0x00000001 +#define regGDFLL_EDC_HYSTERESIS_STAT_DEFAULT 0x00000000 + + +// addressBlock: gc_gdfll_se_gdfll_dec +#define regGDFLL_SE_EDC_HYSTERESIS_CNTL_DEFAULT 0x00000001 +#define regGDFLL_SE_EDC_HYSTERESIS_STAT_DEFAULT 0x00000000 + + +// addressBlock: gc_grtavfs_grtavfs_dec +#define regGRTAVFS_RTAVFS_REG_ADDR_DEFAULT 0x00000000 +#define regGRTAVFS_RTAVFS_WR_DATA_DEFAULT 0x00000000 +#define regGRTAVFS_GENERAL_0_DEFAULT 0x00000000 +#define regGRTAVFS_RTAVFS_RD_DATA_DEFAULT 0x00000000 +#define regGRTAVFS_RTAVFS_REG_CTRL_DEFAULT 0x00000000 +#define regGRTAVFS_RTAVFS_REG_STATUS_DEFAULT 0x00000000 +#define regGRTAVFS_TARG_FREQ_DEFAULT 0x00000000 +#define regGRTAVFS_TARG_VOLT_DEFAULT 0x00000000 +#define regGRTAVFS_SOFT_RESET_DEFAULT 0x00000001 +#define regGRTAVFS_PSM_CNTL_DEFAULT 0x00000000 +#define regGRTAVFS_CLK_CNTL_DEFAULT 0x00000003 + + +// addressBlock: gc_grtavfsdec +#define regRTAVFS_RTAVFS_REG_ADDR_DEFAULT 0x00000000 +#define regRTAVFS_RTAVFS_WR_DATA_DEFAULT 0x00000000 + + +// addressBlock: gc_grtavfs_se_grtavfs_dec +#define regGRTAVFS_SE_RTAVFS_REG_ADDR_DEFAULT 0x00000000 +#define regGRTAVFS_SE_RTAVFS_WR_DATA_DEFAULT 0x00000000 +#define regGRTAVFS_SE_GENERAL_0_DEFAULT 0x00000000 +#define regGRTAVFS_SE_RTAVFS_RD_DATA_DEFAULT 0x00000000 +#define regGRTAVFS_SE_RTAVFS_REG_CTRL_DEFAULT 0x00000000 +#define regGRTAVFS_SE_RTAVFS_REG_STATUS_DEFAULT 0x00000000 +#define regGRTAVFS_SE_TARG_FREQ_DEFAULT 0x00000000 +#define regGRTAVFS_SE_TARG_VOLT_DEFAULT 0x00000000 +#define regGRTAVFS_SE_SOFT_RESET_DEFAULT 0x00000001 +#define regGRTAVFS_SE_PSM_CNTL_DEFAULT 0x00000000 +#define regGRTAVFS_SE_CLK_CNTL_DEFAULT 0x00000003 + + +// addressBlock: gc_rlcdec +#define regRLC_CNTL_DEFAULT 0x00000001 +#define regRLC_F32_UCODE_VERSION_DEFAULT 0x00000000 +#define regRLC_STAT_DEFAULT 0x00000000 +#define regRLC_REFCLOCK_TIMESTAMP_LSB_DEFAULT 0x00000000 +#define regRLC_REFCLOCK_TIMESTAMP_MSB_DEFAULT 0x00000000 +#define regRLC_GPM_TIMER_INT_0_DEFAULT 0x00000063 +#define regRLC_GPM_TIMER_INT_1_DEFAULT 0x00000063 +#define regRLC_GPM_TIMER_INT_2_DEFAULT 0x00000063 +#define regRLC_GPM_TIMER_INT_3_DEFAULT 0x00000063 +#define regRLC_GPM_TIMER_INT_4_DEFAULT 0x00000063 +#define regRLC_GPM_TIMER_CTRL_DEFAULT 0x00000000 +#define regRLC_GPM_TIMER_STAT_DEFAULT 0x00000000 +#define regRLC_GPM_LEGACY_INT_STAT_DEFAULT 0x00000000 +#define regRLC_GPM_LEGACY_INT_CLEAR_DEFAULT 0x00000000 +#define regRLC_INT_STAT_DEFAULT 0x00000000 +#define regRLC_MGCG_CTRL_DEFAULT 0x00000800 +#define regRLC_JUMP_TABLE_RESTORE_DEFAULT 0x00000000 +#define regRLC_PG_DELAY_2_DEFAULT 0x00000004 +#define regRLC_GPU_CLOCK_COUNT_LSB_DEFAULT 0x00000000 +#define regRLC_GPU_CLOCK_COUNT_MSB_DEFAULT 0x00000000 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_DEFAULT 0x00000000 +#define regRLC_UCODE_CNTL_DEFAULT 0x00000000 +#define regRLC_GPM_THREAD_RESET_DEFAULT 0x00000004 +#define regRLC_GPM_CP_DMA_COMPLETE_T0_DEFAULT 0x00000000 +#define regRLC_GPM_CP_DMA_COMPLETE_T1_DEFAULT 0x00000000 +#define regRLC_GPM_THREAD_INVALIDATE_CACHE_DEFAULT 0x00000004 +#define regRLC_CLK_COUNT_GFXCLK_LSB_DEFAULT 0x00000000 +#define regRLC_CLK_COUNT_GFXCLK_MSB_DEFAULT 0x00000000 +#define regRLC_CLK_COUNT_REFCLK_LSB_DEFAULT 0x00000000 +#define regRLC_CLK_COUNT_REFCLK_MSB_DEFAULT 0x00000000 +#define regRLC_CLK_COUNT_CTRL_DEFAULT 0x00000000 +#define regRLC_CLK_COUNT_STAT_DEFAULT 0x00000000 +#define regRLC_RLCG_DOORBELL_CNTL_DEFAULT 0x00260000 +#define regRLC_RLCG_DOORBELL_STAT_DEFAULT 0x00000000 +#define regRLC_RLCG_DOORBELL_0_DATA_LO_DEFAULT 0x00000000 +#define regRLC_RLCG_DOORBELL_0_DATA_HI_DEFAULT 0x00000000 +#define regRLC_RLCG_DOORBELL_1_DATA_LO_DEFAULT 0x00000000 +#define regRLC_RLCG_DOORBELL_1_DATA_HI_DEFAULT 0x00000000 +#define regRLC_RLCG_DOORBELL_2_DATA_LO_DEFAULT 0x00000000 +#define regRLC_RLCG_DOORBELL_2_DATA_HI_DEFAULT 0x00000000 +#define regRLC_RLCG_DOORBELL_3_DATA_LO_DEFAULT 0x00000000 +#define regRLC_RLCG_DOORBELL_3_DATA_HI_DEFAULT 0x00000000 +#define regRLC_GPU_CLOCK_32_RES_SEL_DEFAULT 0x00000000 +#define regRLC_GPU_CLOCK_32_DEFAULT 0x00000000 +#define regRLC_PG_CNTL_DEFAULT 0x00000000 +#define regRLC_GPM_THREAD_PRIORITY_DEFAULT 0x08080808 +#define regRLC_GPM_THREAD_ENABLE_DEFAULT 0x00000001 +#define regRLC_RLCG_DOORBELL_RANGE_DEFAULT 0x00000000 +#define regRLC_CGTT_MGCG_OVERRIDE_DEFAULT 0x000607ff +#define regRLC_CGCG_CGLS_CTRL_DEFAULT 0x0001003c +#define regRLC_CGCG_RAMP_CTRL_DEFAULT 0x00021711 +#define regRLC_DYN_PG_STATUS_DEFAULT 0xffffffff +#define regRLC_DYN_PG_REQUEST_DEFAULT 0xffffffff +#define regRLC_PG_DELAY_DEFAULT 0x00101010 +#define regRLC_WGP_STATUS_DEFAULT 0x00000000 +#define regRLC_PG_ALWAYS_ON_WGP_MASK_DEFAULT 0x00000003 +#define regRLC_MAX_PG_WGP_DEFAULT 0x00000008 +#define regRLC_AUTO_PG_CTRL_DEFAULT 0x00000000 +#define regRLC_SERDES_RD_INDEX_DEFAULT 0x00000000 +#define regRLC_SERDES_RD_DATA_0_DEFAULT 0x00000000 +#define regRLC_SERDES_RD_DATA_1_DEFAULT 0x00000000 +#define regRLC_SERDES_RD_DATA_2_DEFAULT 0x00000000 +#define regRLC_SERDES_RD_DATA_3_DEFAULT 0x00000000 +#define regRLC_SERDES_MASK_DEFAULT 0x00000000 +#define regRLC_SERDES_CTRL_DEFAULT 0x00000000 +#define regRLC_SERDES_DATA_DEFAULT 0x00000000 +#define regRLC_SERDES_BUSY_DEFAULT 0x00000000 +#define regRLC_GPM_GENERAL_0_DEFAULT 0x00000000 +#define regRLC_GPM_GENERAL_1_DEFAULT 0x00000000 +#define regRLC_GPM_GENERAL_2_DEFAULT 0x00000000 +#define regRLC_GPM_GENERAL_3_DEFAULT 0x00000000 +#define regRLC_GPM_GENERAL_4_DEFAULT 0x00000000 +#define regRLC_GPM_GENERAL_5_DEFAULT 0x00000000 +#define regRLC_GPM_GENERAL_6_DEFAULT 0x00000000 +#define regRLC_GPM_GENERAL_7_DEFAULT 0x00000000 +#define regRLC_STATIC_PG_STATUS_DEFAULT 0xffffffff +#define regRLC_GPM_GENERAL_16_DEFAULT 0x00000000 +#define regRLC_PG_DELAY_3_DEFAULT 0x00000000 +#define regRLC_GPR_REG1_DEFAULT 0x00000000 +#define regRLC_GPR_REG2_DEFAULT 0x00000000 +#define regRLC_GPM_INT_DISABLE_TH0_DEFAULT 0xffffffff +#define regRLC_GPM_LEGACY_INT_DISABLE_DEFAULT 0x0000000f +#define regRLC_GPM_INT_FORCE_TH0_DEFAULT 0x00000000 +#define regRLC_SRM_CNTL_DEFAULT 0x00000002 +#define regRLC_SRM_GPM_COMMAND_STATUS_DEFAULT 0x00000001 +#define regRLC_SRM_INDEX_CNTL_ADDR_0_DEFAULT 0x00000000 +#define regRLC_SRM_INDEX_CNTL_ADDR_1_DEFAULT 0x00000000 +#define regRLC_SRM_INDEX_CNTL_ADDR_2_DEFAULT 0x00000000 +#define regRLC_SRM_INDEX_CNTL_ADDR_3_DEFAULT 0x00000000 +#define regRLC_SRM_INDEX_CNTL_ADDR_4_DEFAULT 0x00000000 +#define regRLC_SRM_INDEX_CNTL_ADDR_5_DEFAULT 0x00000000 +#define regRLC_SRM_INDEX_CNTL_ADDR_6_DEFAULT 0x00000000 +#define regRLC_SRM_INDEX_CNTL_ADDR_7_DEFAULT 0x00000000 +#define regRLC_SRM_INDEX_CNTL_DATA_0_DEFAULT 0x00000000 +#define regRLC_SRM_INDEX_CNTL_DATA_1_DEFAULT 0x00000000 +#define regRLC_SRM_INDEX_CNTL_DATA_2_DEFAULT 0x00000000 +#define regRLC_SRM_INDEX_CNTL_DATA_3_DEFAULT 0x00000000 +#define regRLC_SRM_INDEX_CNTL_DATA_4_DEFAULT 0x00000000 +#define regRLC_SRM_INDEX_CNTL_DATA_5_DEFAULT 0x00000000 +#define regRLC_SRM_INDEX_CNTL_DATA_6_DEFAULT 0x00000000 +#define regRLC_SRM_INDEX_CNTL_DATA_7_DEFAULT 0x00000000 +#define regRLC_SRM_STAT_DEFAULT 0x00000000 +#define regRLC_GPM_GENERAL_8_DEFAULT 0x00000000 +#define regRLC_GPM_GENERAL_9_DEFAULT 0x00000000 +#define regRLC_GPM_GENERAL_10_DEFAULT 0x00000000 +#define regRLC_GPM_GENERAL_11_DEFAULT 0x00000000 +#define regRLC_GPM_GENERAL_12_DEFAULT 0x00000000 +#define regRLC_GPM_UTCL1_CNTL_0_DEFAULT 0x00000080 +#define regRLC_GPM_UTCL1_CNTL_1_DEFAULT 0x00000080 +#define regRLC_GPM_UTCL1_CNTL_2_DEFAULT 0x00000080 +#define regRLC_SPM_UTCL1_CNTL_DEFAULT 0x00000080 +#define regRLC_UTCL1_STATUS_2_DEFAULT 0x00000000 +#define regRLC_SPM_UTCL1_ERROR_1_DEFAULT 0x00000000 +#define regRLC_SPM_UTCL1_ERROR_2_DEFAULT 0x00000000 +#define regRLC_GPM_UTCL1_TH0_ERROR_1_DEFAULT 0x00000000 +#define regRLC_GPM_UTCL1_TH0_ERROR_2_DEFAULT 0x00000000 +#define regRLC_GPM_UTCL1_TH1_ERROR_1_DEFAULT 0x00000000 +#define regRLC_GPM_UTCL1_TH1_ERROR_2_DEFAULT 0x00000000 +#define regRLC_GPM_UTCL1_TH2_ERROR_1_DEFAULT 0x00000000 +#define regRLC_GPM_UTCL1_TH2_ERROR_2_DEFAULT 0x00000000 +#define regRLC_CGCG_CGLS_CTRL_3D_DEFAULT 0x0001003c +#define regRLC_CGCG_RAMP_CTRL_3D_DEFAULT 0x00021711 +#define regRLC_SEMAPHORE_0_DEFAULT 0x00000000 +#define regRLC_SEMAPHORE_1_DEFAULT 0x00000000 +#define regRLC_SEMAPHORE_2_DEFAULT 0x00000000 +#define regRLC_SEMAPHORE_3_DEFAULT 0x00000000 +#define regRLC_PACE_INT_STAT_DEFAULT 0x00000000 +#define regRLC_UTCL1_STATUS_DEFAULT 0x00000000 +#define regRLC_R2I_CNTL_0_DEFAULT 0x00000000 +#define regRLC_R2I_CNTL_1_DEFAULT 0x00000000 +#define regRLC_R2I_CNTL_2_DEFAULT 0x00000000 +#define regRLC_R2I_CNTL_3_DEFAULT 0x00000000 +#define regRLC_GPM_INT_STAT_TH0_DEFAULT 0x00000000 +#define regRLC_GPM_GENERAL_13_DEFAULT 0x00000000 +#define regRLC_GPM_GENERAL_14_DEFAULT 0x00000000 +#define regRLC_GPM_GENERAL_15_DEFAULT 0x00000000 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_1_DEFAULT 0x00000000 +#define regRLC_GPU_CLOCK_COUNT_LSB_2_DEFAULT 0x00000000 +#define regRLC_GPU_CLOCK_COUNT_MSB_2_DEFAULT 0x00000000 +#define regRLC_PACE_INT_DISABLE_DEFAULT 0xffffffff +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_2_DEFAULT 0x00000000 +#define regRLC_RLCV_DOORBELL_RANGE_DEFAULT 0x00000000 +#define regRLC_RLCV_DOORBELL_CNTL_DEFAULT 0x00260000 +#define regRLC_RLCV_DOORBELL_STAT_DEFAULT 0x00000000 +#define regRLC_RLCV_DOORBELL_0_DATA_LO_DEFAULT 0x00000000 +#define regRLC_RLCV_DOORBELL_0_DATA_HI_DEFAULT 0x00000000 +#define regRLC_RLCV_DOORBELL_1_DATA_LO_DEFAULT 0x00000000 +#define regRLC_RLCV_DOORBELL_1_DATA_HI_DEFAULT 0x00000000 +#define regRLC_RLCV_DOORBELL_2_DATA_LO_DEFAULT 0x00000000 +#define regRLC_RLCV_DOORBELL_2_DATA_HI_DEFAULT 0x00000000 +#define regRLC_RLCV_DOORBELL_3_DATA_LO_DEFAULT 0x00000000 +#define regRLC_RLCV_DOORBELL_3_DATA_HI_DEFAULT 0x00000000 +#define regRLC_GPU_CLOCK_COUNT_LSB_1_DEFAULT 0x00000000 +#define regRLC_GPU_CLOCK_COUNT_MSB_1_DEFAULT 0x00000000 +#define regRLC_RLCV_SPARE_INT_DEFAULT 0x00000000 +#define regRLC_PACE_TIMER_INT_0_DEFAULT 0x00000063 +#define regRLC_PACE_TIMER_INT_1_DEFAULT 0x00000063 +#define regRLC_PACE_TIMER_CTRL_DEFAULT 0x00000000 +#define regRLC_SMU_CLK_REQ_DEFAULT 0x00000000 +#define regRLC_CP_STAT_INVAL_STAT_DEFAULT 0x00000000 +#define regRLC_CP_STAT_INVAL_CTRL_DEFAULT 0x00000007 +#define regRLC_SPARE_DEFAULT 0x00000000 +#define regRLC_SPP_CTRL_DEFAULT 0x00000000 +#define regRLC_SPP_SHADER_PROFILE_EN_DEFAULT 0x00000000 +#define regRLC_SPP_SSF_CAPTURE_EN_DEFAULT 0x00000000 +#define regRLC_SPP_SSF_THRESHOLD_0_DEFAULT 0x01100110 +#define regRLC_SPP_SSF_THRESHOLD_1_DEFAULT 0x01100110 +#define regRLC_SPP_SSF_THRESHOLD_2_DEFAULT 0x01100110 +#define regRLC_SPP_INFLIGHT_RD_ADDR_DEFAULT 0x00000000 +#define regRLC_SPP_INFLIGHT_RD_DATA_DEFAULT 0x00000000 +#define regRLC_SPP_PROF_INFO_1_DEFAULT 0x00000000 +#define regRLC_SPP_PROF_INFO_2_DEFAULT 0x00000000 +#define regRLC_SPP_GLOBAL_SH_ID_DEFAULT 0x00000000 +#define regRLC_SPP_GLOBAL_SH_ID_VALID_DEFAULT 0x00000000 +#define regRLC_SPP_STATUS_DEFAULT 0x00000000 +#define regRLC_SPP_PVT_STAT_0_DEFAULT 0x00000000 +#define regRLC_SPP_PVT_STAT_1_DEFAULT 0x00000000 +#define regRLC_SPP_PVT_STAT_2_DEFAULT 0x00000000 +#define regRLC_SPP_PVT_STAT_3_DEFAULT 0x00000000 +#define regRLC_SPP_PVT_LEVEL_MAX_DEFAULT 0x00000000 +#define regRLC_SPP_STALL_STATE_UPDATE_DEFAULT 0x00000000 +#define regRLC_SPP_PBB_INFO_DEFAULT 0x00000000 +#define regRLC_SPP_RESET_DEFAULT 0x00000000 +#define regRLC_RLCP_DOORBELL_RANGE_DEFAULT 0x00000000 +#define regRLC_RLCP_DOORBELL_CNTL_DEFAULT 0x00260000 +#define regRLC_RLCP_DOORBELL_STAT_DEFAULT 0x00000000 +#define regRLC_RLCP_DOORBELL_0_DATA_LO_DEFAULT 0x00000000 +#define regRLC_RLCP_DOORBELL_0_DATA_HI_DEFAULT 0x00000000 +#define regRLC_RLCP_DOORBELL_1_DATA_LO_DEFAULT 0x00000000 +#define regRLC_RLCP_DOORBELL_1_DATA_HI_DEFAULT 0x00000000 +#define regRLC_RLCP_DOORBELL_2_DATA_LO_DEFAULT 0x00000000 +#define regRLC_RLCP_DOORBELL_2_DATA_HI_DEFAULT 0x00000000 +#define regRLC_RLCP_DOORBELL_3_DATA_LO_DEFAULT 0x00000000 +#define regRLC_RLCP_DOORBELL_3_DATA_HI_DEFAULT 0x00000000 +#define regRLC_CAC_MASK_CNTL_DEFAULT 0x000000bf +#define regRLC_POWER_RESIDENCY_CNTR_CTRL_DEFAULT 0x00000000 +#define regRLC_CLK_RESIDENCY_CNTR_CTRL_DEFAULT 0x00000000 +#define regRLC_DS_RESIDENCY_CNTR_CTRL_DEFAULT 0x00000000 +#define regRLC_ULV_RESIDENCY_CNTR_CTRL_DEFAULT 0x00000000 +#define regRLC_PCC_RESIDENCY_CNTR_CTRL_DEFAULT 0x00000000 +#define regRLC_GENERAL_RESIDENCY_CNTR_CTRL_DEFAULT 0x00000000 +#define regRLC_POWER_RESIDENCY_EVENT_CNTR_DEFAULT 0x00000000 +#define regRLC_CLK_RESIDENCY_EVENT_CNTR_DEFAULT 0x00000000 +#define regRLC_DS_RESIDENCY_EVENT_CNTR_DEFAULT 0x00000000 +#define regRLC_ULV_RESIDENCY_EVENT_CNTR_DEFAULT 0x00000000 +#define regRLC_PCC_RESIDENCY_EVENT_CNTR_DEFAULT 0x00000000 +#define regRLC_GENERAL_RESIDENCY_EVENT_CNTR_DEFAULT 0x00000000 +#define regRLC_POWER_RESIDENCY_REF_CNTR_DEFAULT 0x00000000 +#define regRLC_CLK_RESIDENCY_REF_CNTR_DEFAULT 0x00000000 +#define regRLC_DS_RESIDENCY_REF_CNTR_DEFAULT 0x00000000 +#define regRLC_ULV_RESIDENCY_REF_CNTR_DEFAULT 0x00000000 +#define regRLC_PCC_RESIDENCY_REF_CNTR_DEFAULT 0x00000000 +#define regRLC_GENERAL_RESIDENCY_REF_CNTR_DEFAULT 0x00000000 +#define regRLC_GFX_IH_CLIENT_CTRL_DEFAULT 0x00000000 +#define regRLC_GFX_IH_ARBITER_STAT_DEFAULT 0x00000000 +#define regRLC_GFX_IH_CLIENT_SE_STAT_L_DEFAULT 0x00000000 +#define regRLC_GFX_IH_CLIENT_SE_STAT_H_DEFAULT 0x00000000 +#define regRLC_GFX_IH_CLIENT_SDMA_STAT_DEFAULT 0x00000000 +#define regRLC_GFX_IH_CLIENT_OTHER_STAT_DEFAULT 0x00000000 +#define regRLC_SPM_GLOBAL_DELAY_IND_ADDR_DEFAULT 0x00000000 +#define regRLC_SPM_GLOBAL_DELAY_IND_DATA_DEFAULT 0x00000000 +#define regRLC_SPM_SE_DELAY_IND_ADDR_DEFAULT 0x00000000 +#define regRLC_SPM_SE_DELAY_IND_DATA_DEFAULT 0x00000000 +#define regRLC_LX6_CNTL_DEFAULT 0x00000001 +#define regRLC_XT_CORE_STATUS_DEFAULT 0x00000000 +#define regRLC_XT_CORE_INTERRUPT_DEFAULT 0x00000000 +#define regRLC_XT_CORE_FAULT_INFO_DEFAULT 0x00000000 +#define regRLC_XT_CORE_ALT_RESET_VEC_DEFAULT 0x00000000 +#define regRLC_XT_CORE_RESERVED_DEFAULT 0x00000000 +#define regRLC_XT_INT_VEC_FORCE_DEFAULT 0x00000000 +#define regRLC_XT_INT_VEC_CLEAR_DEFAULT 0x00000000 +#define regRLC_XT_INT_VEC_MUX_SEL_DEFAULT 0x00000000 +#define regRLC_XT_INT_VEC_MUX_INT_SEL_DEFAULT 0x00000000 +#define regRLC_GPU_CLOCK_COUNT_SPM_LSB_DEFAULT 0x00000000 +#define regRLC_GPU_CLOCK_COUNT_SPM_MSB_DEFAULT 0x00000000 +#define regRLC_SPM_THREAD_TRACE_CTRL_DEFAULT 0x00000000 +#define regRLC_SPP_CAM_ADDR_DEFAULT 0x00000000 +#define regRLC_SPP_CAM_DATA_DEFAULT 0x00000000 +#define regRLC_SPP_CAM_EXT_ADDR_DEFAULT 0x00000000 +#define regRLC_SPP_CAM_EXT_DATA_DEFAULT 0x00000000 +#define regRLC_XT_DOORBELL_RANGE_DEFAULT 0x00000000 +#define regRLC_XT_DOORBELL_CNTL_DEFAULT 0x00260000 +#define regRLC_XT_DOORBELL_STAT_DEFAULT 0x00000000 +#define regRLC_XT_DOORBELL_0_DATA_LO_DEFAULT 0x00000000 +#define regRLC_XT_DOORBELL_0_DATA_HI_DEFAULT 0x00000000 +#define regRLC_XT_DOORBELL_1_DATA_LO_DEFAULT 0x00000000 +#define regRLC_XT_DOORBELL_1_DATA_HI_DEFAULT 0x00000000 +#define regRLC_XT_DOORBELL_2_DATA_LO_DEFAULT 0x00000000 +#define regRLC_XT_DOORBELL_2_DATA_HI_DEFAULT 0x00000000 +#define regRLC_XT_DOORBELL_3_DATA_LO_DEFAULT 0x00000000 +#define regRLC_XT_DOORBELL_3_DATA_HI_DEFAULT 0x00000000 +#define regRLC_MEM_SLP_CNTL_DEFAULT 0x00020200 +#define regSMU_RLC_RESPONSE_DEFAULT 0x00000000 +#define regRLC_RLCV_SAFE_MODE_DEFAULT 0x00000000 +#define regRLC_SMU_SAFE_MODE_DEFAULT 0x00000000 +#define regRLC_RLCV_COMMAND_DEFAULT 0x00000000 +#define regRLC_SMU_MESSAGE_DEFAULT 0x00000000 +#define regRLC_SMU_MESSAGE_1_DEFAULT 0x00000000 +#define regRLC_SMU_MESSAGE_2_DEFAULT 0x00000000 +#define regRLC_SRM_GPM_COMMAND_DEFAULT 0x00000000 +#define regRLC_SRM_GPM_ABORT_DEFAULT 0x00000000 +#define regRLC_SMU_COMMAND_DEFAULT 0x00000000 +#define regRLC_SMU_ARGUMENT_1_DEFAULT 0x00000000 +#define regRLC_SMU_ARGUMENT_2_DEFAULT 0x00000000 +#define regRLC_SMU_ARGUMENT_3_DEFAULT 0x00000000 +#define regRLC_SMU_ARGUMENT_4_DEFAULT 0x00000000 +#define regRLC_SMU_ARGUMENT_5_DEFAULT 0x00000000 +#define regRLC_IMU_BOOTLOAD_ADDR_HI_DEFAULT 0x00000000 +#define regRLC_IMU_BOOTLOAD_ADDR_LO_DEFAULT 0x00000000 +#define regRLC_IMU_BOOTLOAD_SIZE_DEFAULT 0x00000000 +#define regRLC_IMU_MISC_DEFAULT 0x00000000 +#define regRLC_IMU_RESET_VECTOR_DEFAULT 0x00000000 + + +// addressBlock: gc_rlcsdec +#define regRLC_RLCS_DEC_START_DEFAULT 0x00000000 +#define regRLC_RLCS_DEC_DUMP_ADDR_DEFAULT 0x00000000 +#define regRLC_RLCS_EXCEPTION_REG_1_DEFAULT 0x0003b984 +#define regRLC_RLCS_EXCEPTION_REG_2_DEFAULT 0x0003b984 +#define regRLC_RLCS_EXCEPTION_REG_3_DEFAULT 0x0003b984 +#define regRLC_RLCS_EXCEPTION_REG_4_DEFAULT 0x0003b984 +#define regRLC_RLCS_CGCG_REQUEST_DEFAULT 0x00000003 +#define regRLC_RLCS_CGCG_STATUS_DEFAULT 0x00000024 +#define regRLC_RLCS_SOC_DS_CNTL_DEFAULT 0x00ff00c6 +#define regRLC_RLCS_GFX_DS_CNTL_DEFAULT 0x00ff01c6 +#define regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL_DEFAULT 0x0000007f +#define regRLC_GPM_STAT_DEFAULT 0x00b40016 +#define regRLC_RLCS_GPM_STAT_DEFAULT 0x00b40016 +#define regRLC_RLCS_ABORTED_PD_SEQUENCE_DEFAULT 0x00000000 +#define regRLC_RLCS_DIDT_FORCE_STALL_DEFAULT 0x00000000 +#define regRLC_RLCS_IOV_CMD_STATUS_DEFAULT 0x00000000 +#define regRLC_RLCS_IOV_CNTX_LOC_SIZE_DEFAULT 0x00000000 +#define regRLC_RLCS_IOV_SCH_BLOCK_DEFAULT 0x00000000 +#define regRLC_RLCS_IOV_VM_BUSY_STATUS_DEFAULT 0x00000000 +#define regRLC_RLCS_GPM_STAT_2_DEFAULT 0x00000000 +#define regRLC_RLCS_GRBM_SOFT_RESET_DEFAULT 0x00000001 +#define regRLC_RLCS_PG_CHANGE_STATUS_DEFAULT 0x00000000 +#define regRLC_RLCS_PG_CHANGE_READ_DEFAULT 0x00000000 +#define regRLC_RLCS_IH_SEMAPHORE_DEFAULT 0x00000000 +#define regRLC_RLCS_IH_COOKIE_SEMAPHORE_DEFAULT 0x00000000 +#define regRLC_RLCS_WGP_STATUS_DEFAULT 0x00000000 +#define regRLC_RLCS_WGP_READ_DEFAULT 0x00000000 +#define regRLC_RLCS_CP_INT_CTRL_1_DEFAULT 0x00000000 +#define regRLC_RLCS_CP_INT_CTRL_2_DEFAULT 0x00000000 +#define regRLC_RLCS_CP_INT_INFO_1_DEFAULT 0x00000000 +#define regRLC_RLCS_CP_INT_INFO_2_DEFAULT 0x00000000 +#define regRLC_RLCS_SPM_INT_CTRL_DEFAULT 0x00000000 +#define regRLC_RLCS_SPM_INT_INFO_1_DEFAULT 0x00000000 +#define regRLC_RLCS_SPM_INT_INFO_2_DEFAULT 0x00000000 +#define regRLC_RLCS_DSM_TRIG_DEFAULT 0x00000000 +#define regRLC_RLCS_BOOTLOAD_STATUS_DEFAULT 0x00000000 +#define regRLC_RLCS_POWER_BRAKE_CNTL_DEFAULT 0x00000004 +#define regRLC_RLCS_POWER_BRAKE_CNTL_TH1_DEFAULT 0x00000004 +#define regRLC_RLCS_GRBM_IDLE_BUSY_STAT_DEFAULT 0x00000000 +#define regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_DEFAULT 0x00000000 +#define regRLC_RLCS_CMP_IDLE_CNTL_DEFAULT 0x00000100 +#define regRLC_RLCS_GENERAL_0_DEFAULT 0x00000000 +#define regRLC_RLCS_GENERAL_1_DEFAULT 0x00000000 +#define regRLC_RLCS_GENERAL_2_DEFAULT 0x00000000 +#define regRLC_RLCS_GENERAL_3_DEFAULT 0x00000000 +#define regRLC_RLCS_GENERAL_4_DEFAULT 0x00000000 +#define regRLC_RLCS_GENERAL_5_DEFAULT 0x00000000 +#define regRLC_RLCS_GENERAL_6_DEFAULT 0x00000000 +#define regRLC_RLCS_GENERAL_7_DEFAULT 0x00000000 +#define regRLC_RLCS_GENERAL_8_DEFAULT 0x00000000 +#define regRLC_RLCS_GENERAL_9_DEFAULT 0x00000000 +#define regRLC_RLCS_GENERAL_10_DEFAULT 0x00000000 +#define regRLC_RLCS_GENERAL_11_DEFAULT 0x00000000 +#define regRLC_RLCS_GENERAL_12_DEFAULT 0x00000000 +#define regRLC_RLCS_GENERAL_13_DEFAULT 0x00000000 +#define regRLC_RLCS_GENERAL_14_DEFAULT 0x00000000 +#define regRLC_RLCS_GENERAL_15_DEFAULT 0x00000000 +#define regRLC_RLCS_GENERAL_16_DEFAULT 0x00000000 +#define regRLC_RLCS_AUXILIARY_REG_1_DEFAULT 0x0003b984 +#define regRLC_RLCS_AUXILIARY_REG_2_DEFAULT 0x0003b984 +#define regRLC_RLCS_AUXILIARY_REG_3_DEFAULT 0x0003b984 +#define regRLC_RLCS_AUXILIARY_REG_4_DEFAULT 0x0003b984 +#define regRLC_RLCS_SPM_SQTT_MODE_DEFAULT 0x00000000 +#define regRLC_RLCS_CP_DMA_SRCID_OVER_DEFAULT 0x00000000 +#define regRLC_RLCS_BOOTLOAD_ID_STATUS1_DEFAULT 0x00000000 +#define regRLC_RLCS_BOOTLOAD_ID_STATUS2_DEFAULT 0x00000000 +#define regRLC_RLCS_IMU_VIDCHG_CNTL_DEFAULT 0x00000000 +#define regRLC_RLCS_EDC_INT_CNTL_DEFAULT 0x00000000 +#define regRLC_RLCS_KMD_LOG_CNTL1_DEFAULT 0x00000000 +#define regRLC_RLCS_KMD_LOG_CNTL2_DEFAULT 0x00000000 +#define regRLC_RLCS_GPM_LEGACY_INT_STAT_DEFAULT 0x00000000 +#define regRLC_RLCS_GPM_LEGACY_INT_DISABLE_DEFAULT 0x00000003 +#define regRLC_RLCS_SRM_SRCID_CNTL_DEFAULT 0x00000006 +#define regRLC_RLCS_GCR_DATA_0_DEFAULT 0x00000000 +#define regRLC_RLCS_GCR_DATA_1_DEFAULT 0x00000000 +#define regRLC_RLCS_GCR_DATA_2_DEFAULT 0x00000000 +#define regRLC_RLCS_GCR_DATA_3_DEFAULT 0x00000000 +#define regRLC_RLCS_GCR_STATUS_DEFAULT 0x00000000 +#define regRLC_RLCS_PERFMON_CLK_CNTL_UCODE_DEFAULT 0x00000001 +#define regRLC_RLCS_UTCL2_CNTL_DEFAULT 0x00000018 +#define regRLC_RLCS_IMU_RLC_MSG_DATA0_DEFAULT 0x00000000 +#define regRLC_RLCS_IMU_RLC_MSG_DATA1_DEFAULT 0x00000000 +#define regRLC_RLCS_IMU_RLC_MSG_DATA2_DEFAULT 0x00000000 +#define regRLC_RLCS_IMU_RLC_MSG_DATA3_DEFAULT 0x00000000 +#define regRLC_RLCS_IMU_RLC_MSG_DATA4_DEFAULT 0x00000000 +#define regRLC_RLCS_IMU_RLC_MSG_CONTROL_DEFAULT 0x00000000 +#define regRLC_RLCS_IMU_RLC_MSG_CNTL_DEFAULT 0x00000000 +#define regRLC_RLCS_RLC_IMU_MSG_DATA0_DEFAULT 0x00000000 +#define regRLC_RLCS_RLC_IMU_MSG_CONTROL_DEFAULT 0x00000000 +#define regRLC_RLCS_RLC_IMU_MSG_CNTL_DEFAULT 0x00000000 +#define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0_DEFAULT 0x00000000 +#define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1_DEFAULT 0x00000000 +#define regRLC_RLCS_IMU_RLC_MUTEX_CNTL_DEFAULT 0x00000000 +#define regRLC_RLCS_IMU_RLC_STATUS_DEFAULT 0x00000000 +#define regRLC_RLCS_RLC_IMU_STATUS_DEFAULT 0x00000000 +#define regRLC_RLCS_IMU_RAM_DATA_1_DEFAULT 0x00000000 +#define regRLC_RLCS_IMU_RAM_ADDR_1_LSB_DEFAULT 0x00000000 +#define regRLC_RLCS_IMU_RAM_ADDR_1_MSB_DEFAULT 0x00000000 +#define regRLC_RLCS_IMU_RAM_DATA_0_DEFAULT 0x00000000 +#define regRLC_RLCS_IMU_RAM_ADDR_0_LSB_DEFAULT 0x00000000 +#define regRLC_RLCS_IMU_RAM_ADDR_0_MSB_DEFAULT 0x00000000 +#define regRLC_RLCS_IMU_RAM_CNTL_DEFAULT 0x00000000 +#define regRLC_RLCS_IMU_GFX_DOORBELL_FENCE_DEFAULT 0x00000001 +#define regRLC_RLCS_SDMA_INT_CNTL_1_DEFAULT 0x00000000 +#define regRLC_RLCS_SDMA_INT_CNTL_2_DEFAULT 0x00000000 +#define regRLC_RLCS_SDMA_INT_STAT_DEFAULT 0x00000300 +#define regRLC_RLCS_SDMA_INT_INFO_DEFAULT 0x00000000 +#define regRLC_RLCS_PMM_CGCG_CNTL_DEFAULT 0x00000000 +#define regRLC_RLCS_GFX_MEM_POWER_CTRL_LO_DEFAULT 0x00000000 +#define regRLC_RLCS_GFX_RM_CNTL_DEFAULT 0x00000000 +#define regRLC_RLCS_DEC_END_DEFAULT 0x00000000 + + +// addressBlock: gc_pwrdec +#define regCGTS_TCC_DISABLE_DEFAULT 0x00000000 +#define regCGTT_GS_NGG_CLK_CTRL_DEFAULT 0x00018000 +#define regCGTT_PA_CLK_CTRL_DEFAULT 0x00000000 +#define regCGTT_SC_CLK_CTRL0_DEFAULT 0x00000100 +#define regCGTT_SC_CLK_CTRL1_DEFAULT 0x00000100 +#define regCGTT_SC_CLK_CTRL2_DEFAULT 0x00020100 +#define regCGTT_SQG_CLK_CTRL_DEFAULT 0x00000100 +#define regSQ_ALU_CLK_CTRL_DEFAULT 0x00000000 +#define regSQ_TEX_CLK_CTRL_DEFAULT 0x00000000 +#define regSQ_LDS_CLK_CTRL_DEFAULT 0x00000000 +#define regICG_SP_CLK_CTRL_DEFAULT 0x00000000 +#define regTA_CGTT_CTRL_DEFAULT 0x00000100 +#define regDB_CGTT_CLK_CTRL_0_DEFAULT 0x00000000 +#define regCB_CGTT_SCLK_CTRL_DEFAULT 0x00000100 +#define regCGTT_CP_CLK_CTRL_DEFAULT 0x00000100 +#define regCGTT_CPF_CLK_CTRL_DEFAULT 0x00000100 +#define regCGTT_CPC_CLK_CTRL_DEFAULT 0x00000100 +#define regCGTT_RLC_CLK_CTRL_DEFAULT 0x00000000 +#define regCGTT_SC_CLK_CTRL3_DEFAULT 0x00000000 +#define regCGTT_SC_CLK_CTRL4_DEFAULT 0x00000000 +#define regGCEA_ICG_CTRL_DEFAULT 0x00000000 +#define regGL1I_GL1R_MGCG_OVERRIDE_DEFAULT 0x00000000 +#define regGL1H_ICG_CTRL_DEFAULT 0x00000000 +#define regCHI_CHR_MGCG_OVERRIDE_DEFAULT 0x00000000 +#define regICG_GL1C_CLK_CTRL_DEFAULT 0x00000000 +#define regICG_GL1A_CTRL_DEFAULT 0x00000000 +#define regICG_CHA_CTRL_DEFAULT 0x00000000 +#define regGUS_ICG_CTRL_DEFAULT 0x00000000 +#define regCGTT_PH_CLK_CTRL0_DEFAULT 0x00000100 +#define regCGTT_PH_CLK_CTRL1_DEFAULT 0x00000100 +#define regCGTT_PH_CLK_CTRL2_DEFAULT 0x00000100 +#define regCGTT_PH_CLK_CTRL3_DEFAULT 0x00000100 +#define regGFX_ICG_GL2C_CTRL_DEFAULT 0x00000000 +#define regGFX_ICG_GL2C_CTRL1_DEFAULT 0x00000000 +#define regICG_LDS_CLK_CTRL_DEFAULT 0x00000000 +#define regICG_CHC_CLK_CTRL_DEFAULT 0x00000000 +#define regICG_CHCG_CLK_CTRL_DEFAULT 0x00000000 + + +// addressBlock: gc_cphypdec +#define regCP_HYP_PFP_UCODE_ADDR_DEFAULT 0x00000000 +#define regCP_PFP_UCODE_ADDR_DEFAULT 0x00000000 +#define regCP_HYP_PFP_UCODE_DATA_DEFAULT 0x00000000 +#define regCP_PFP_UCODE_DATA_DEFAULT 0x00000000 +#define regCP_HYP_ME_UCODE_ADDR_DEFAULT 0x00000000 +#define regCP_ME_RAM_RADDR_DEFAULT 0x00000000 +#define regCP_ME_RAM_WADDR_DEFAULT 0x00000000 +#define regCP_HYP_ME_UCODE_DATA_DEFAULT 0x00000000 +#define regCP_ME_RAM_DATA_DEFAULT 0x00000000 +#define regCP_HYP_MEC1_UCODE_ADDR_DEFAULT 0x00000000 +#define regCP_MEC_ME1_UCODE_ADDR_DEFAULT 0x00000000 +#define regCP_HYP_MEC1_UCODE_DATA_DEFAULT 0x00000000 +#define regCP_MEC_ME1_UCODE_DATA_DEFAULT 0x00000000 +#define regCP_HYP_MEC2_UCODE_ADDR_DEFAULT 0x00000000 +#define regCP_MEC_ME2_UCODE_ADDR_DEFAULT 0x00000000 +#define regCP_HYP_MEC2_UCODE_DATA_DEFAULT 0x00000000 +#define regCP_MEC_ME2_UCODE_DATA_DEFAULT 0x00000000 +#define regCP_PFP_IC_BASE_LO_DEFAULT 0x00000000 +#define regCP_PFP_IC_BASE_HI_DEFAULT 0x00000000 +#define regCP_PFP_IC_BASE_CNTL_DEFAULT 0x00000010 +#define regCP_PFP_IC_OP_CNTL_DEFAULT 0x00000000 +#define regCP_ME_IC_BASE_LO_DEFAULT 0x00000000 +#define regCP_ME_IC_BASE_HI_DEFAULT 0x00000000 +#define regCP_ME_IC_BASE_CNTL_DEFAULT 0x00000010 +#define regCP_ME_IC_OP_CNTL_DEFAULT 0x00000000 +#define regCP_CPC_IC_BASE_LO_DEFAULT 0x00000000 +#define regCP_CPC_IC_BASE_HI_DEFAULT 0x00000000 +#define regCP_CPC_IC_BASE_CNTL_DEFAULT 0x00000010 +#define regCP_MES_IC_BASE_LO_DEFAULT 0x00000000 +#define regCP_MES_MIBASE_LO_DEFAULT 0x00000000 +#define regCP_MES_IC_BASE_HI_DEFAULT 0x00000000 +#define regCP_MES_MIBASE_HI_DEFAULT 0x00000000 +#define regCP_MES_IC_BASE_CNTL_DEFAULT 0x00000000 +#define regCP_MES_DC_BASE_LO_DEFAULT 0x00000000 +#define regCP_MES_MDBASE_LO_DEFAULT 0x00000000 +#define regCP_MES_DC_BASE_HI_DEFAULT 0x00000000 +#define regCP_MES_MDBASE_HI_DEFAULT 0x00000000 +#define regCP_MES_MIBOUND_LO_DEFAULT 0x0000ffff +#define regCP_MES_MIBOUND_HI_DEFAULT 0x00000000 +#define regCP_MES_MDBOUND_LO_DEFAULT 0x0000ffff +#define regCP_MES_MDBOUND_HI_DEFAULT 0x0000ffff +#define regCP_GFX_RS64_DC_BASE0_LO_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_BASE1_LO_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_BASE0_HI_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DC_BASE1_HI_DEFAULT 0x00000000 +#define regCP_GFX_RS64_MIBOUND_LO_DEFAULT 0x000fffff +#define regCP_GFX_RS64_MIBOUND_HI_DEFAULT 0x000fffff +#define regCP_MEC_DC_BASE_LO_DEFAULT 0x00000000 +#define regCP_MEC_MDBASE_LO_DEFAULT 0x00000000 +#define regCP_MEC_DC_BASE_HI_DEFAULT 0x00000000 +#define regCP_MEC_MDBASE_HI_DEFAULT 0x00000000 +#define regCP_MEC_MIBOUND_LO_DEFAULT 0x0000ffff +#define regCP_MEC_MIBOUND_HI_DEFAULT 0x00000000 +#define regCP_MEC_MDBOUND_LO_DEFAULT 0x0000ffff +#define regCP_MEC_MDBOUND_HI_DEFAULT 0x0000ffff + + +// addressBlock: gc_hypdec +#define regGFX_PIPE_PRIORITY_DEFAULT 0x00000001 +#define regGRBM_GFX_INDEX_SR_SELECT_DEFAULT 0x00000000 +#define regGRBM_GFX_INDEX_SR_DATA_DEFAULT 0xe0000000 +#define regGRBM_GFX_CNTL_SR_SELECT_DEFAULT 0x00000000 +#define regGRBM_GFX_CNTL_SR_DATA_DEFAULT 0x00000000 +#define regGC_IH_COOKIE_0_PTR_DEFAULT 0x00004300 +#define regGRBM_SE_REMAP_CNTL_DEFAULT 0xeca86420 +#define regRLC_GPU_IOV_VF_ENABLE_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_CFG_REG6_DEFAULT 0x00000000 +#define regRLC_SDMA0_STATUS_DEFAULT 0x00000000 +#define regRLC_SDMA1_STATUS_DEFAULT 0x00000000 +#define regRLC_SDMA2_STATUS_DEFAULT 0x00000000 +#define regRLC_SDMA3_STATUS_DEFAULT 0x00000000 +#define regRLC_SDMA0_BUSY_STATUS_DEFAULT 0x00000000 +#define regRLC_SDMA1_BUSY_STATUS_DEFAULT 0x00000000 +#define regRLC_SDMA2_BUSY_STATUS_DEFAULT 0x00000000 +#define regRLC_SDMA3_BUSY_STATUS_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_CFG_REG8_DEFAULT 0x00000000 +#define regRLC_RLCV_TIMER_INT_0_DEFAULT 0x00000063 +#define regRLC_RLCV_TIMER_INT_1_DEFAULT 0x00000063 +#define regRLC_RLCV_TIMER_CTRL_DEFAULT 0x00000000 +#define regRLC_RLCV_TIMER_STAT_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_DEFAULT 0x7fffffff +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_VF_MASK_DEFAULT 0x7fffffff +#define regRLC_HYP_SEMAPHORE_0_DEFAULT 0x00000000 +#define regRLC_HYP_SEMAPHORE_1_DEFAULT 0x00000000 +#define regRLC_BUSY_CLK_CNTL_DEFAULT 0x00000800 +#define regRLC_CLK_CNTL_DEFAULT 0x00000000 +#define regRLC_PACE_TIMER_STAT_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_SCH_BLOCK_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_CFG_REG1_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_CFG_REG2_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_VM_BUSY_STATUS_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_SCH_0_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_SCH_3_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_SCH_1_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_SCH_2_DEFAULT 0x00000000 +#define regRLC_PACE_INT_FORCE_DEFAULT 0x00000000 +#define regRLC_PACE_INT_CLEAR_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_INT_STAT_DEFAULT 0x00000000 +#define regRLC_IH_COOKIE_DEFAULT 0x00000000 +#define regRLC_IH_COOKIE_CNTL_DEFAULT 0x00000002 +#define regRLC_HYP_RLCG_UCODE_CHKSUM_DEFAULT 0x00000000 +#define regRLC_HYP_RLCP_UCODE_CHKSUM_DEFAULT 0x00000000 +#define regRLC_HYP_RLCV_UCODE_CHKSUM_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_F32_CNTL_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_F32_RESET_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_UCODE_ADDR_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_UCODE_DATA_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_SMU_RESPONSE_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_F32_INVALIDATE_CACHE_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_RLC_RESPONSE_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_INT_DISABLE_DEFAULT 0xffffffff +#define regRLC_GPU_IOV_INT_FORCE_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_SCRATCH_ADDR_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_SCRATCH_DATA_DEFAULT 0x00000000 +#define regRLC_HYP_SEMAPHORE_2_DEFAULT 0x00000000 +#define regRLC_HYP_SEMAPHORE_3_DEFAULT 0x00000000 +#define regRLC_GPM_UCODE_ADDR_DEFAULT 0x00000000 +#define regRLC_GPM_UCODE_DATA_DEFAULT 0x00000000 +#define regRLC_GPM_IRAM_ADDR_DEFAULT 0x00000000 +#define regRLC_GPM_IRAM_DATA_DEFAULT 0x00000000 +#define regRLC_RLCP_IRAM_ADDR_DEFAULT 0x00000000 +#define regRLC_RLCP_IRAM_DATA_DEFAULT 0x00000000 +#define regRLC_RLCV_IRAM_ADDR_DEFAULT 0x00000000 +#define regRLC_RLCV_IRAM_DATA_DEFAULT 0x00000000 +#define regRLC_LX6_DRAM_ADDR_DEFAULT 0x00000000 +#define regRLC_LX6_DRAM_DATA_DEFAULT 0x00000000 +#define regRLC_LX6_IRAM_ADDR_DEFAULT 0x00000000 +#define regRLC_LX6_IRAM_DATA_DEFAULT 0x00000000 +#define regRLC_PACE_UCODE_ADDR_DEFAULT 0x00000000 +#define regRLC_PACE_UCODE_DATA_DEFAULT 0x00000000 +#define regRLC_GPM_SCRATCH_ADDR_DEFAULT 0x00000000 +#define regRLC_GPM_SCRATCH_DATA_DEFAULT 0x00000000 +#define regRLC_SRM_DRAM_ADDR_DEFAULT 0x00000000 +#define regRLC_SRM_DRAM_DATA_DEFAULT 0x00000000 +#define regRLC_SRM_ARAM_ADDR_DEFAULT 0x00000000 +#define regRLC_SRM_ARAM_DATA_DEFAULT 0x00000000 +#define regRLC_PACE_SCRATCH_ADDR_DEFAULT 0x00000000 +#define regRLC_PACE_SCRATCH_DATA_DEFAULT 0x00000000 +#define regRLC_GTS_OFFSET_LSB_DEFAULT 0x00000000 +#define regRLC_GTS_OFFSET_MSB_DEFAULT 0x00000000 +#define regGL2_PIPE_STEER_0_DEFAULT 0x32103210 +#define regGL2_PIPE_STEER_1_DEFAULT 0x32103210 +#define regGL2_PIPE_STEER_2_DEFAULT 0x76547654 +#define regGL2_PIPE_STEER_3_DEFAULT 0x76547654 +#define regGL1_PIPE_STEER_DEFAULT 0x000000e4 +#define regCH_PIPE_STEER_DEFAULT 0x000000e4 +#define regGC_USER_SHADER_ARRAY_CONFIG_DEFAULT 0x00000000 +#define regGC_USER_PRIM_CONFIG_DEFAULT 0x000faaa0 +#define regGC_USER_SA_UNIT_DISABLE_DEFAULT 0x00f00000 +#define regGC_USER_RB_REDUNDANCY_DEFAULT 0x00000000 +#define regGC_USER_RB_BACKEND_DISABLE_DEFAULT 0x00000000 +#define regGC_USER_RMI_REDUNDANCY_DEFAULT 0x00000010 +#define regCGTS_USER_TCC_DISABLE_DEFAULT 0x00000000 +#define regGC_USER_SHADER_RATE_CONFIG_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_SDMA0_STATUS_DEFAULT 0x0000000f +#define regRLC_GPU_IOV_SDMA1_STATUS_DEFAULT 0x0000000f +#define regRLC_GPU_IOV_SDMA2_STATUS_DEFAULT 0x0000000f +#define regRLC_GPU_IOV_SDMA3_STATUS_DEFAULT 0x0000000f +#define regRLC_GPU_IOV_SDMA4_STATUS_DEFAULT 0x0000000f +#define regRLC_GPU_IOV_SDMA5_STATUS_DEFAULT 0x0000000f +#define regRLC_GPU_IOV_SDMA6_STATUS_DEFAULT 0x0000000f +#define regRLC_GPU_IOV_SDMA7_STATUS_DEFAULT 0x0000000f +#define regRLC_GPU_IOV_SDMA0_BUSY_STATUS_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_SDMA1_BUSY_STATUS_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_SDMA2_BUSY_STATUS_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_SDMA3_BUSY_STATUS_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_SDMA4_BUSY_STATUS_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_SDMA5_BUSY_STATUS_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_SDMA6_BUSY_STATUS_DEFAULT 0x00000000 +#define regRLC_GPU_IOV_SDMA7_BUSY_STATUS_DEFAULT 0x00000000 + + +// addressBlock: gc_sdma0_sdma0hypdec +#define regSDMA0_UCODE_ADDR_DEFAULT 0x00000000 +#define regSDMA0_UCODE_DATA_DEFAULT 0x00000000 +#define regSDMA0_UCODE_SELFLOAD_CONTROL_DEFAULT 0x00000223 +#define regSDMA0_BROADCAST_UCODE_ADDR_DEFAULT 0x00000000 +#define regSDMA0_BROADCAST_UCODE_DATA_DEFAULT 0x00000000 +#define regSDMA0_F32_CNTL_DEFAULT 0x08084001 + + +// addressBlock: gc_sdma0_sdma1hypdec +#define regSDMA1_UCODE_ADDR_DEFAULT 0x00000000 +#define regSDMA1_UCODE_DATA_DEFAULT 0x00000000 +#define regSDMA1_UCODE_SELFLOAD_CONTROL_DEFAULT 0x00000223 +#define regSDMA1_BROADCAST_UCODE_ADDR_DEFAULT 0x00000000 +#define regSDMA1_BROADCAST_UCODE_DATA_DEFAULT 0x00000000 +#define regSDMA1_F32_CNTL_DEFAULT 0x08084001 + + +// addressBlock: gc_gcvmsharedhvdec +#define regGCMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000 +#define regGCMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000 +#define regGCMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000 +#define regGCMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000 +#define regGCMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000 +#define regGCMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000 +#define regGCMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000 +#define regGCMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000 +#define regGCMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000 +#define regGCMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000 +#define regGCMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000 +#define regGCMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000 +#define regGCMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000 +#define regGCMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000 +#define regGCMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000 +#define regGCMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000 + + +// addressBlock: gc_pspdec +#define regCP_MES_DM_INDEX_ADDR_DEFAULT 0x00000000 +#define regCP_MES_DM_INDEX_DATA_DEFAULT 0x00000000 +#define regCP_MEC_DM_INDEX_ADDR_DEFAULT 0x00000000 +#define regCP_MEC_DM_INDEX_DATA_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DM_INDEX_ADDR_DEFAULT 0x00000000 +#define regCP_GFX_RS64_DM_INDEX_DATA_DEFAULT 0x00000000 +#define regCPG_PSP_DEBUG_DEFAULT 0x00000000 +#define regCPC_PSP_DEBUG_DEFAULT 0x00000000 +#define regGRBM_SEC_CNTL_DEFAULT 0x00000000 +#define regGRBM_CAM_INDEX_DEFAULT 0x00000000 +#define regGRBM_HYP_CAM_INDEX_DEFAULT 0x00000000 +#define regGRBM_CAM_DATA_DEFAULT 0x00000000 +#define regGRBM_HYP_CAM_DATA_DEFAULT 0x00000000 +#define regGRBM_CAM_DATA_UPPER_DEFAULT 0x00000000 +#define regGRBM_HYP_CAM_DATA_UPPER_DEFAULT 0x00000000 +#define regRLC_FWL_FIRST_VIOL_ADDR_DEFAULT 0x00000000 + + +// addressBlock: gc_gcvml2pspdec +#define regGCUTCL2_TRANSLATION_BYPASS_BY_VMID_DEFAULT 0x00000000 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_LO_4_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_LO_5_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_LO_6_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_LO_7_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_LO_8_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_LO_9_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_LO_10_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_LO_11_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_LO_12_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_LO_13_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_LO_14_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_LO_15_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_HI_4_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_HI_5_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_HI_6_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_HI_7_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_HI_8_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_HI_9_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_HI_10_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_HI_11_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_HI_12_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_HI_13_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_HI_14_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_BASE_HI_15_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_LO_4_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_LO_5_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_LO_6_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_LO_7_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_LO_8_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_LO_9_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_LO_10_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_LO_11_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_LO_12_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_LO_13_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_LO_14_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_LO_15_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_HI_4_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_HI_5_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_HI_6_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_HI_7_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_HI_8_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_HI_9_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_HI_10_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_HI_11_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_HI_12_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_HI_13_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_HI_14_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_RELOC_HI_15_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_LO_4_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_LO_5_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_LO_6_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_LO_7_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_LO_8_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_LO_9_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_LO_10_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_LO_11_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_LO_12_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_LO_13_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_LO_14_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_LO_15_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_HI_4_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_HI_5_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_HI_6_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_HI_7_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_HI_8_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_HI_9_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_HI_10_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_HI_11_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_HI_12_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_HI_13_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_HI_14_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_LEN_HI_15_DEFAULT 0x00000000 +#define regGCMC_VM_MARC_PFVF_MAPPING_0_DEFAULT 0x0001ffff +#define regGCMC_VM_MARC_PFVF_MAPPING_1_DEFAULT 0x0001ffff +#define regGCMC_VM_MARC_PFVF_MAPPING_2_DEFAULT 0x0001ffff +#define regGCMC_VM_MARC_PFVF_MAPPING_3_DEFAULT 0x0001ffff +#define regGCMC_VM_MARC_PFVF_MAPPING_4_DEFAULT 0x0001ffff +#define regGCMC_VM_MARC_PFVF_MAPPING_5_DEFAULT 0x0001ffff +#define regGCMC_VM_MARC_PFVF_MAPPING_6_DEFAULT 0x0001ffff +#define regGCMC_VM_MARC_PFVF_MAPPING_7_DEFAULT 0x0001ffff +#define regGCMC_VM_MARC_PFVF_MAPPING_8_DEFAULT 0x0001ffff +#define regGCMC_VM_MARC_PFVF_MAPPING_9_DEFAULT 0x0001ffff +#define regGCMC_VM_MARC_PFVF_MAPPING_10_DEFAULT 0x0001ffff +#define regGCMC_VM_MARC_PFVF_MAPPING_11_DEFAULT 0x0001ffff +#define regGCMC_VM_MARC_PFVF_MAPPING_12_DEFAULT 0x0001ffff +#define regGCMC_VM_MARC_PFVF_MAPPING_13_DEFAULT 0x0001ffff +#define regGCMC_VM_MARC_PFVF_MAPPING_14_DEFAULT 0x0001ffff +#define regGCMC_VM_MARC_PFVF_MAPPING_15_DEFAULT 0x0001ffff +#define regGCUTC_TRANSLATION_FAULT_CNTL0_DEFAULT 0x00000000 +#define regGCUTC_TRANSLATION_FAULT_CNTL1_DEFAULT 0x00000000 + + +// addressBlock: gc_gfx_imu_gfx_imu_pspdec +#define regGFX_IMU_RLC_BOOTLOADER_ADDR_HI_DEFAULT 0x00000000 +#define regGFX_IMU_RLC_BOOTLOADER_ADDR_LO_DEFAULT 0x00000000 +#define regGFX_IMU_RLC_BOOTLOADER_SIZE_DEFAULT 0x00000000 +#define regGFX_IMU_I_RAM_ADDR_DEFAULT 0x00000000 +#define regGFX_IMU_I_RAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: gccacind +#define ixGC_CAC_ID_DEFAULT 0x00000000 +#define ixGC_CAC_CNTL_DEFAULT 0x000000ff +#define ixGC_CAC_ACC_CP0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CP1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CP2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_EA0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_EA1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_EA2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_EA3_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_EA4_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_EA5_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ROUTER0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ROUTER1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ROUTER2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ROUTER3_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ROUTER4_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ROUTER5_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ROUTER6_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ROUTER7_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ROUTER8_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ROUTER9_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_VML20_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_VML21_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_VML22_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_VML23_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_VML24_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_WALKER0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_WALKER1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_WALKER2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_WALKER3_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_WALKER4_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GDS0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GDS1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GDS2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GDS3_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GDS4_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GE0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GE1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GE2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GE3_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GE4_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GE5_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GE6_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GE7_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GE8_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GE9_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GE10_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GE11_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GE12_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GE13_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GE14_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GE15_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GE16_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GE17_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GE18_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GE19_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GE20_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_PMM0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GL2C0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GL2C1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GL2C2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GL2C3_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GL2C4_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_PH0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_PH1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_PH2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_PH3_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_PH4_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_PH5_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_PH6_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_PH7_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SDMA0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SDMA1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SDMA2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SDMA3_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SDMA4_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SDMA5_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SDMA6_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SDMA7_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SDMA8_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SDMA9_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SDMA10_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SDMA11_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CHC0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CHC1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CHC2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GUS0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GUS1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GUS2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_RLC0_DEFAULT 0x00000000 +#define ixRELEASE_TO_STALL_LUT_1_8_DEFAULT 0x00000000 +#define ixRELEASE_TO_STALL_LUT_9_16_DEFAULT 0x00000000 +#define ixRELEASE_TO_STALL_LUT_17_20_DEFAULT 0x00000000 +#define ixSTALL_TO_RELEASE_LUT_1_4_DEFAULT 0x00000000 +#define ixSTALL_TO_RELEASE_LUT_5_7_DEFAULT 0x00000000 +#define ixSTALL_TO_PWRBRK_LUT_1_4_DEFAULT 0x00000000 +#define ixSTALL_TO_PWRBRK_LUT_5_7_DEFAULT 0x00000000 +#define ixPWRBRK_STALL_TO_RELEASE_LUT_1_4_DEFAULT 0x00000000 +#define ixPWRBRK_STALL_TO_RELEASE_LUT_5_7_DEFAULT 0x00000000 +#define ixPWRBRK_RELEASE_TO_STALL_LUT_1_8_DEFAULT 0x00000000 +#define ixPWRBRK_RELEASE_TO_STALL_LUT_9_16_DEFAULT 0x00000000 +#define ixPWRBRK_RELEASE_TO_STALL_LUT_17_20_DEFAULT 0x00000000 +#define ixFIXED_PATTERN_PERF_COUNTER_1_DEFAULT 0x00000000 +#define ixFIXED_PATTERN_PERF_COUNTER_2_DEFAULT 0x00000000 +#define ixFIXED_PATTERN_PERF_COUNTER_3_DEFAULT 0x00000000 +#define ixFIXED_PATTERN_PERF_COUNTER_4_DEFAULT 0x00000000 +#define ixFIXED_PATTERN_PERF_COUNTER_5_DEFAULT 0x00000000 +#define ixFIXED_PATTERN_PERF_COUNTER_6_DEFAULT 0x00000000 +#define ixFIXED_PATTERN_PERF_COUNTER_7_DEFAULT 0x00000000 +#define ixFIXED_PATTERN_PERF_COUNTER_8_DEFAULT 0x00000000 +#define ixFIXED_PATTERN_PERF_COUNTER_9_DEFAULT 0x00000000 +#define ixFIXED_PATTERN_PERF_COUNTER_10_DEFAULT 0x00000000 +#define ixHW_LUT_UPDATE_STATUS_DEFAULT 0x00000000 + + +// addressBlock: secacind +#define ixSE_CAC_ID_DEFAULT 0x00000000 +#define ixSE_CAC_CNTL_DEFAULT 0x000000ff + + +// addressBlock: grtavfsind +#define ixRTAVFS_REG0_DEFAULT 0x01000000 +#define ixRTAVFS_REG1_DEFAULT 0x01000000 +#define ixRTAVFS_REG2_DEFAULT 0x01000000 +#define ixRTAVFS_REG3_DEFAULT 0x01000000 +#define ixRTAVFS_REG4_DEFAULT 0x01000000 +#define ixRTAVFS_REG5_DEFAULT 0x00000000 +#define ixRTAVFS_REG6_DEFAULT 0x00000000 +#define ixRTAVFS_REG7_DEFAULT 0x00000000 +#define ixRTAVFS_REG8_DEFAULT 0x00000000 +#define ixRTAVFS_REG9_DEFAULT 0x00000000 +#define ixRTAVFS_REG10_DEFAULT 0x00000000 +#define ixRTAVFS_REG11_DEFAULT 0x00000000 +#define ixRTAVFS_REG12_DEFAULT 0x00000000 +#define ixRTAVFS_REG13_DEFAULT 0x00000000 +#define ixRTAVFS_REG14_DEFAULT 0x00000000 +#define ixRTAVFS_REG15_DEFAULT 0x00000000 +#define ixRTAVFS_REG16_DEFAULT 0x00000000 +#define ixRTAVFS_REG17_DEFAULT 0x00000000 +#define ixRTAVFS_REG18_DEFAULT 0x00000000 +#define ixRTAVFS_REG19_DEFAULT 0x00000000 +#define ixRTAVFS_REG20_DEFAULT 0x00000000 +#define ixRTAVFS_REG21_DEFAULT 0x00000000 +#define ixRTAVFS_REG22_DEFAULT 0x00000000 +#define ixRTAVFS_REG23_DEFAULT 0x00000000 +#define ixRTAVFS_REG24_DEFAULT 0x00000000 +#define ixRTAVFS_REG25_DEFAULT 0x00000000 +#define ixRTAVFS_REG26_DEFAULT 0x00000000 +#define ixRTAVFS_REG27_DEFAULT 0x00000000 +#define ixRTAVFS_REG28_DEFAULT 0x00000000 +#define ixRTAVFS_REG29_DEFAULT 0x00000000 +#define ixRTAVFS_REG30_DEFAULT 0x00000000 +#define ixRTAVFS_REG31_DEFAULT 0x00000000 +#define ixRTAVFS_REG32_DEFAULT 0x000000ff +#define ixRTAVFS_REG33_DEFAULT 0x000000ff +#define ixRTAVFS_REG34_DEFAULT 0x000000ff +#define ixRTAVFS_REG35_DEFAULT 0x000000ff +#define ixRTAVFS_REG36_DEFAULT 0x000000ff +#define ixRTAVFS_REG37_DEFAULT 0x000000ff +#define ixRTAVFS_REG38_DEFAULT 0x000000ff +#define ixRTAVFS_REG39_DEFAULT 0x000000ff +#define ixRTAVFS_REG40_DEFAULT 0x000000ff +#define ixRTAVFS_REG41_DEFAULT 0x000000ff +#define ixRTAVFS_REG42_DEFAULT 0x000000ff +#define ixRTAVFS_REG43_DEFAULT 0xcccdbcdd +#define ixRTAVFS_REG44_DEFAULT 0x2587d190 +#define ixRTAVFS_REG45_DEFAULT 0x00000000 +#define ixRTAVFS_REG46_DEFAULT 0x000211cd +#define ixRTAVFS_REG47_DEFAULT 0x000af12c +#define ixRTAVFS_REG48_DEFAULT 0x00000010 +#define ixRTAVFS_REG49_DEFAULT 0x00000000 +#define ixRTAVFS_REG50_DEFAULT 0x00000000 +#define ixRTAVFS_REG51_DEFAULT 0x00000008 +#define ixRTAVFS_REG52_DEFAULT 0x00000000 +#define ixRTAVFS_REG53_DEFAULT 0x00000000 +#define ixRTAVFS_REG54_DEFAULT 0x01000000 +#define ixRTAVFS_REG55_DEFAULT 0x01000000 +#define ixRTAVFS_REG56_DEFAULT 0x01000000 +#define ixRTAVFS_REG57_DEFAULT 0x01000000 +#define ixRTAVFS_REG58_DEFAULT 0x01000000 +#define ixRTAVFS_REG59_DEFAULT 0x01000000 +#define ixRTAVFS_REG60_DEFAULT 0x01000000 +#define ixRTAVFS_REG61_DEFAULT 0x01000000 +#define ixRTAVFS_REG62_DEFAULT 0x01000000 +#define ixRTAVFS_REG63_DEFAULT 0x01000000 +#define ixRTAVFS_REG64_DEFAULT 0x01000000 +#define ixRTAVFS_REG65_DEFAULT 0x01000000 +#define ixRTAVFS_REG66_DEFAULT 0x01000000 +#define ixRTAVFS_REG67_DEFAULT 0x01000000 +#define ixRTAVFS_REG68_DEFAULT 0x01000000 +#define ixRTAVFS_REG69_DEFAULT 0x01000000 +#define ixRTAVFS_REG70_DEFAULT 0x01000000 +#define ixRTAVFS_REG71_DEFAULT 0x01000000 +#define ixRTAVFS_REG72_DEFAULT 0x01000000 +#define ixRTAVFS_REG73_DEFAULT 0x00000100 +#define ixRTAVFS_REG74_DEFAULT 0x00000100 +#define ixRTAVFS_REG75_DEFAULT 0x00000100 +#define ixRTAVFS_REG76_DEFAULT 0x00000100 +#define ixRTAVFS_REG77_DEFAULT 0x00000100 +#define ixRTAVFS_REG78_DEFAULT 0x00000100 +#define ixRTAVFS_REG79_DEFAULT 0x00000100 +#define ixRTAVFS_REG80_DEFAULT 0x01000000 +#define ixRTAVFS_REG81_DEFAULT 0x01000000 +#define ixRTAVFS_REG82_DEFAULT 0x01000000 +#define ixRTAVFS_REG83_DEFAULT 0x01000000 +#define ixRTAVFS_REG84_DEFAULT 0x01000000 +#define ixRTAVFS_REG85_DEFAULT 0x01000000 +#define ixRTAVFS_REG86_DEFAULT 0x01000000 +#define ixRTAVFS_REG87_DEFAULT 0x01000000 +#define ixRTAVFS_REG88_DEFAULT 0x01000000 +#define ixRTAVFS_REG89_DEFAULT 0x01000000 +#define ixRTAVFS_REG90_DEFAULT 0x01000000 +#define ixRTAVFS_REG91_DEFAULT 0x01000000 +#define ixRTAVFS_REG92_DEFAULT 0x01000000 +#define ixRTAVFS_REG93_DEFAULT 0x01000000 +#define ixRTAVFS_REG94_DEFAULT 0x01000000 +#define ixRTAVFS_REG95_DEFAULT 0x01000000 +#define ixRTAVFS_REG96_DEFAULT 0x01000000 +#define ixRTAVFS_REG97_DEFAULT 0x01000000 +#define ixRTAVFS_REG98_DEFAULT 0x01000000 +#define ixRTAVFS_REG99_DEFAULT 0x01000000 +#define ixRTAVFS_REG100_DEFAULT 0x01000000 +#define ixRTAVFS_REG101_DEFAULT 0x01000000 +#define ixRTAVFS_REG102_DEFAULT 0x00000100 +#define ixRTAVFS_REG103_DEFAULT 0x00000100 +#define ixRTAVFS_REG104_DEFAULT 0x00000100 +#define ixRTAVFS_REG105_DEFAULT 0x00000100 +#define ixRTAVFS_REG106_DEFAULT 0x00000100 +#define ixRTAVFS_REG107_DEFAULT 0x00000100 +#define ixRTAVFS_REG108_DEFAULT 0x00000100 +#define ixRTAVFS_REG109_DEFAULT 0x01000000 +#define ixRTAVFS_REG110_DEFAULT 0x01000000 +#define ixRTAVFS_REG111_DEFAULT 0x01000000 +#define ixRTAVFS_REG112_DEFAULT 0x00000100 +#define ixRTAVFS_REG113_DEFAULT 0x00000100 +#define ixRTAVFS_REG114_DEFAULT 0x00000100 +#define ixRTAVFS_REG115_DEFAULT 0x01000000 +#define ixRTAVFS_REG116_DEFAULT 0x01000000 +#define ixRTAVFS_REG117_DEFAULT 0x01000000 +#define ixRTAVFS_REG118_DEFAULT 0x00000000 +#define ixRTAVFS_REG119_DEFAULT 0x00000000 +#define ixRTAVFS_REG120_DEFAULT 0x00000000 +#define ixRTAVFS_REG121_DEFAULT 0x00000000 +#define ixRTAVFS_REG122_DEFAULT 0x00000000 +#define ixRTAVFS_REG123_DEFAULT 0x00000000 +#define ixRTAVFS_REG124_DEFAULT 0x00000000 +#define ixRTAVFS_REG125_DEFAULT 0x00000000 +#define ixRTAVFS_REG126_DEFAULT 0x00000000 +#define ixRTAVFS_REG127_DEFAULT 0x00000000 +#define ixRTAVFS_REG128_DEFAULT 0x00000000 +#define ixRTAVFS_REG129_DEFAULT 0x00000000 +#define ixRTAVFS_REG130_DEFAULT 0x00000000 +#define ixRTAVFS_REG131_DEFAULT 0x00000000 +#define ixRTAVFS_REG132_DEFAULT 0x00000000 +#define ixRTAVFS_REG133_DEFAULT 0x00000000 +#define ixRTAVFS_REG134_DEFAULT 0x00000000 +#define ixRTAVFS_REG135_DEFAULT 0x00000000 +#define ixRTAVFS_REG136_DEFAULT 0x00000000 +#define ixRTAVFS_REG137_DEFAULT 0x00000000 +#define ixRTAVFS_REG138_DEFAULT 0x00000000 +#define ixRTAVFS_REG139_DEFAULT 0x00000000 +#define ixRTAVFS_REG140_DEFAULT 0x00000000 +#define ixRTAVFS_REG141_DEFAULT 0x00000000 +#define ixRTAVFS_REG142_DEFAULT 0x00000000 +#define ixRTAVFS_REG143_DEFAULT 0x00000000 +#define ixRTAVFS_REG144_DEFAULT 0x00000000 +#define ixRTAVFS_REG145_DEFAULT 0x00000000 +#define ixRTAVFS_REG146_DEFAULT 0x00000000 +#define ixRTAVFS_REG147_DEFAULT 0x00000000 +#define ixRTAVFS_REG148_DEFAULT 0x00000000 +#define ixRTAVFS_REG149_DEFAULT 0x00000000 +#define ixRTAVFS_REG150_DEFAULT 0x00000000 +#define ixRTAVFS_REG151_DEFAULT 0x00000000 +#define ixRTAVFS_REG152_DEFAULT 0x00000000 +#define ixRTAVFS_REG153_DEFAULT 0x00000000 +#define ixRTAVFS_REG154_DEFAULT 0x00000000 +#define ixRTAVFS_REG155_DEFAULT 0x00000000 +#define ixRTAVFS_REG156_DEFAULT 0x00000000 +#define ixRTAVFS_REG157_DEFAULT 0x00000000 +#define ixRTAVFS_REG158_DEFAULT 0x00000000 +#define ixRTAVFS_REG159_DEFAULT 0x00000000 +#define ixRTAVFS_REG160_DEFAULT 0x00000000 +#define ixRTAVFS_REG161_DEFAULT 0x00000000 +#define ixRTAVFS_REG162_DEFAULT 0x00000000 +#define ixRTAVFS_REG163_DEFAULT 0x00000000 +#define ixRTAVFS_REG164_DEFAULT 0x00000000 +#define ixRTAVFS_REG165_DEFAULT 0x00000000 +#define ixRTAVFS_REG166_DEFAULT 0x00000000 +#define ixRTAVFS_REG167_DEFAULT 0x00000000 +#define ixRTAVFS_REG168_DEFAULT 0x00000000 +#define ixRTAVFS_REG169_DEFAULT 0x00000000 +#define ixRTAVFS_REG170_DEFAULT 0x00000000 +#define ixRTAVFS_REG171_DEFAULT 0x00000000 +#define ixRTAVFS_REG172_DEFAULT 0x00000000 +#define ixRTAVFS_REG173_DEFAULT 0x00000000 +#define ixRTAVFS_REG174_DEFAULT 0x00000000 +#define ixRTAVFS_REG175_DEFAULT 0x00000000 +#define ixRTAVFS_REG176_DEFAULT 0x00000000 +#define ixRTAVFS_REG177_DEFAULT 0x00000000 +#define ixRTAVFS_REG178_DEFAULT 0x00000000 +#define ixRTAVFS_REG179_DEFAULT 0x00000000 +#define ixRTAVFS_REG180_DEFAULT 0x00000000 +#define ixRTAVFS_REG181_DEFAULT 0x00000000 +#define ixRTAVFS_REG182_DEFAULT 0x00000000 +#define ixRTAVFS_REG183_DEFAULT 0x00000000 +#define ixRTAVFS_REG184_DEFAULT 0x00000000 +#define ixRTAVFS_REG185_DEFAULT 0x00000000 +#define ixRTAVFS_REG186_DEFAULT 0x00000000 +#define ixRTAVFS_REG187_DEFAULT 0x00000000 +#define ixRTAVFS_REG188_DEFAULT 0x00000000 +#define ixRTAVFS_REG189_DEFAULT 0x0007d12c +#define ixRTAVFS_REG190_DEFAULT 0x00000000 +#define ixRTAVFS_REG191_DEFAULT 0x00000000 +#define ixRTAVFS_REG192_DEFAULT 0x00000000 +#define ixRTAVFS_REG193_DEFAULT 0x00000001 +#define ixRTAVFS_REG194_DEFAULT 0x00000000 + + +// addressBlock: sqind +#define ixSQ_DEBUG_STS_LOCAL_DEFAULT 0x00000000 +#define ixSQ_DEBUG_CTRL_LOCAL_DEFAULT 0x00000000 +#define ixSQ_WAVE_ACTIVE_DEFAULT 0x00000000 +#define ixSQ_WAVE_VALID_AND_IDLE_DEFAULT 0x00000000 +#define ixSQ_WAVE_MODE_DEFAULT 0x00000000 +#define ixSQ_WAVE_STATUS_DEFAULT 0x00000000 +#define ixSQ_WAVE_TRAPSTS_DEFAULT 0x00000000 +#define ixSQ_WAVE_GPR_ALLOC_DEFAULT 0x00000000 +#define ixSQ_WAVE_LDS_ALLOC_DEFAULT 0x00000000 +#define ixSQ_WAVE_IB_STS_DEFAULT 0x00000000 +#define ixSQ_WAVE_PC_LO_DEFAULT 0x00000000 +#define ixSQ_WAVE_PC_HI_DEFAULT 0x00000000 +#define ixSQ_WAVE_IB_DBG1_DEFAULT 0x00000000 +#define ixSQ_WAVE_FLUSH_IB_DEFAULT 0x00000000 +#define ixSQ_WAVE_FLAT_SCRATCH_LO_DEFAULT 0x00000000 +#define ixSQ_WAVE_FLAT_SCRATCH_HI_DEFAULT 0x00000000 +#define ixSQ_WAVE_HW_ID1_DEFAULT 0x00000000 +#define ixSQ_WAVE_HW_ID2_DEFAULT 0x00000000 +#define ixSQ_WAVE_POPS_PACKER_DEFAULT 0x00000000 +#define ixSQ_WAVE_SCHED_MODE_DEFAULT 0x00000000 +#define ixSQ_WAVE_IB_STS2_DEFAULT 0x00000000 +#define ixSQ_WAVE_SHADER_CYCLES_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP0_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP1_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP3_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP4_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP5_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP6_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP7_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP8_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP9_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP10_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP11_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP12_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP13_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP14_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP15_DEFAULT 0x00000000 +#define ixSQ_WAVE_M0_DEFAULT 0x00000000 +#define ixSQ_WAVE_EXEC_LO_DEFAULT 0x00000000 +#define ixSQ_WAVE_EXEC_HI_DEFAULT 0x00000000 + + +#endif |