diff options
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h | 11673 |
1 files changed, 11673 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h new file mode 100644 index 000000000000..c92c4b83253f --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h @@ -0,0 +1,11673 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _gc_11_0_0_OFFSET_HEADER +#define _gc_11_0_0_OFFSET_HEADER + + + +// addressBlock: gc_sdma0_sdma0dec +// base address: 0x4980 +#define regSDMA0_DEC_START 0x0000 +#define regSDMA0_DEC_START_BASE_IDX 0 +#define regSDMA0_F32_MISC_CNTL 0x000b +#define regSDMA0_F32_MISC_CNTL_BASE_IDX 0 +#define regSDMA0_GLOBAL_TIMESTAMP_LO 0x000f +#define regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0 +#define regSDMA0_GLOBAL_TIMESTAMP_HI 0x0010 +#define regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0 +#define regSDMA0_POWER_CNTL 0x001a +#define regSDMA0_POWER_CNTL_BASE_IDX 0 +#define regSDMA0_CNTL 0x001c +#define regSDMA0_CNTL_BASE_IDX 0 +#define regSDMA0_CHICKEN_BITS 0x001d +#define regSDMA0_CHICKEN_BITS_BASE_IDX 0 +#define regSDMA0_GB_ADDR_CONFIG 0x001e +#define regSDMA0_GB_ADDR_CONFIG_BASE_IDX 0 +#define regSDMA0_GB_ADDR_CONFIG_READ 0x001f +#define regSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0 +#define regSDMA0_RB_RPTR_FETCH 0x0020 +#define regSDMA0_RB_RPTR_FETCH_BASE_IDX 0 +#define regSDMA0_RB_RPTR_FETCH_HI 0x0021 +#define regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0022 +#define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 +#define regSDMA0_IB_OFFSET_FETCH 0x0023 +#define regSDMA0_IB_OFFSET_FETCH_BASE_IDX 0 +#define regSDMA0_PROGRAM 0x0024 +#define regSDMA0_PROGRAM_BASE_IDX 0 +#define regSDMA0_STATUS_REG 0x0025 +#define regSDMA0_STATUS_REG_BASE_IDX 0 +#define regSDMA0_STATUS1_REG 0x0026 +#define regSDMA0_STATUS1_REG_BASE_IDX 0 +#define regSDMA0_CNTL1 0x0027 +#define regSDMA0_CNTL1_BASE_IDX 0 +#define regSDMA0_HBM_PAGE_CONFIG 0x0028 +#define regSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0 +#define regSDMA0_UCODE_CHECKSUM 0x0029 +#define regSDMA0_UCODE_CHECKSUM_BASE_IDX 0 +#define regSDMA0_FREEZE 0x002b +#define regSDMA0_FREEZE_BASE_IDX 0 +#define regSDMA0_PROCESS_QUANTUM0 0x002c +#define regSDMA0_PROCESS_QUANTUM0_BASE_IDX 0 +#define regSDMA0_PROCESS_QUANTUM1 0x002d +#define regSDMA0_PROCESS_QUANTUM1_BASE_IDX 0 +#define regSDMA0_WATCHDOG_CNTL 0x002e +#define regSDMA0_WATCHDOG_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE_STATUS0 0x002f +#define regSDMA0_QUEUE_STATUS0_BASE_IDX 0 +#define regSDMA0_EDC_CONFIG 0x0032 +#define regSDMA0_EDC_CONFIG_BASE_IDX 0 +#define regSDMA0_BA_THRESHOLD 0x0033 +#define regSDMA0_BA_THRESHOLD_BASE_IDX 0 +#define regSDMA0_ID 0x0034 +#define regSDMA0_ID_BASE_IDX 0 +#define regSDMA0_VERSION 0x0035 +#define regSDMA0_VERSION_BASE_IDX 0 +#define regSDMA0_EDC_COUNTER 0x0036 +#define regSDMA0_EDC_COUNTER_BASE_IDX 0 +#define regSDMA0_EDC_COUNTER_CLEAR 0x0037 +#define regSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0 +#define regSDMA0_STATUS2_REG 0x0038 +#define regSDMA0_STATUS2_REG_BASE_IDX 0 +#define regSDMA0_ATOMIC_CNTL 0x0039 +#define regSDMA0_ATOMIC_CNTL_BASE_IDX 0 +#define regSDMA0_ATOMIC_PREOP_LO 0x003a +#define regSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 +#define regSDMA0_ATOMIC_PREOP_HI 0x003b +#define regSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 +#define regSDMA0_UTCL1_CNTL 0x003c +#define regSDMA0_UTCL1_CNTL_BASE_IDX 0 +#define regSDMA0_UTCL1_WATERMK 0x003d +#define regSDMA0_UTCL1_WATERMK_BASE_IDX 0 +#define regSDMA0_UTCL1_TIMEOUT 0x003e +#define regSDMA0_UTCL1_TIMEOUT_BASE_IDX 0 +#define regSDMA0_UTCL1_PAGE 0x003f +#define regSDMA0_UTCL1_PAGE_BASE_IDX 0 +#define regSDMA0_UTCL1_RD_STATUS 0x0040 +#define regSDMA0_UTCL1_RD_STATUS_BASE_IDX 0 +#define regSDMA0_UTCL1_WR_STATUS 0x0041 +#define regSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 +#define regSDMA0_UTCL1_INV0 0x0042 +#define regSDMA0_UTCL1_INV0_BASE_IDX 0 +#define regSDMA0_UTCL1_INV1 0x0043 +#define regSDMA0_UTCL1_INV1_BASE_IDX 0 +#define regSDMA0_UTCL1_INV2 0x0044 +#define regSDMA0_UTCL1_INV2_BASE_IDX 0 +#define regSDMA0_UTCL1_RD_XNACK0 0x0045 +#define regSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0 +#define regSDMA0_UTCL1_RD_XNACK1 0x0046 +#define regSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0 +#define regSDMA0_UTCL1_WR_XNACK0 0x0047 +#define regSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0 +#define regSDMA0_UTCL1_WR_XNACK1 0x0048 +#define regSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0 +#define regSDMA0_RELAX_ORDERING_LUT 0x004a +#define regSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0 +#define regSDMA0_CHICKEN_BITS_2 0x004b +#define regSDMA0_CHICKEN_BITS_2_BASE_IDX 0 +#define regSDMA0_STATUS3_REG 0x004c +#define regSDMA0_STATUS3_REG_BASE_IDX 0 +#define regSDMA0_PHYSICAL_ADDR_LO 0x004d +#define regSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_PHYSICAL_ADDR_HI 0x004e +#define regSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_GLOBAL_QUANTUM 0x004f +#define regSDMA0_GLOBAL_QUANTUM_BASE_IDX 0 +#define regSDMA0_ERROR_LOG 0x0050 +#define regSDMA0_ERROR_LOG_BASE_IDX 0 +#define regSDMA0_PUB_DUMMY_REG0 0x0051 +#define regSDMA0_PUB_DUMMY_REG0_BASE_IDX 0 +#define regSDMA0_PUB_DUMMY_REG1 0x0052 +#define regSDMA0_PUB_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_PUB_DUMMY_REG2 0x0053 +#define regSDMA0_PUB_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_PUB_DUMMY_REG3 0x0054 +#define regSDMA0_PUB_DUMMY_REG3_BASE_IDX 0 +#define regSDMA0_F32_COUNTER 0x0055 +#define regSDMA0_F32_COUNTER_BASE_IDX 0 +#define regSDMA0_CRD_CNTL 0x005b +#define regSDMA0_CRD_CNTL_BASE_IDX 0 +#define regSDMA0_RLC_CGCG_CTRL 0x005c +#define regSDMA0_RLC_CGCG_CTRL_BASE_IDX 0 +#define regSDMA0_AQL_STATUS 0x005f +#define regSDMA0_AQL_STATUS_BASE_IDX 0 +#define regSDMA0_EA_DBIT_ADDR_DATA 0x0060 +#define regSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0 +#define regSDMA0_EA_DBIT_ADDR_INDEX 0x0061 +#define regSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0 +#define regSDMA0_TLBI_GCR_CNTL 0x0062 +#define regSDMA0_TLBI_GCR_CNTL_BASE_IDX 0 +#define regSDMA0_TILING_CONFIG 0x0063 +#define regSDMA0_TILING_CONFIG_BASE_IDX 0 +#define regSDMA0_INT_STATUS 0x0070 +#define regSDMA0_INT_STATUS_BASE_IDX 0 +#define regSDMA0_HOLE_ADDR_LO 0x0072 +#define regSDMA0_HOLE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_HOLE_ADDR_HI 0x0073 +#define regSDMA0_HOLE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_CLOCK_GATING_STATUS 0x0075 +#define regSDMA0_CLOCK_GATING_STATUS_BASE_IDX 0 +#define regSDMA0_STATUS4_REG 0x0076 +#define regSDMA0_STATUS4_REG_BASE_IDX 0 +#define regSDMA0_SCRATCH_RAM_DATA 0x0077 +#define regSDMA0_SCRATCH_RAM_DATA_BASE_IDX 0 +#define regSDMA0_SCRATCH_RAM_ADDR 0x0078 +#define regSDMA0_SCRATCH_RAM_ADDR_BASE_IDX 0 +#define regSDMA0_TIMESTAMP_CNTL 0x0079 +#define regSDMA0_TIMESTAMP_CNTL_BASE_IDX 0 +#define regSDMA0_STATUS5_REG 0x007a +#define regSDMA0_STATUS5_REG_BASE_IDX 0 +#define regSDMA0_QUEUE_RESET_REQ 0x007b +#define regSDMA0_QUEUE_RESET_REQ_BASE_IDX 0 +#define regSDMA0_STATUS6_REG 0x007c +#define regSDMA0_STATUS6_REG_BASE_IDX 0 +#define regSDMA0_UCODE1_CHECKSUM 0x007d +#define regSDMA0_UCODE1_CHECKSUM_BASE_IDX 0 +#define regSDMA0_CE_CTRL 0x007e +#define regSDMA0_CE_CTRL_BASE_IDX 0 +#define regSDMA0_FED_STATUS 0x007f +#define regSDMA0_FED_STATUS_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_CNTL 0x0080 +#define regSDMA0_QUEUE0_RB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_BASE 0x0081 +#define regSDMA0_QUEUE0_RB_BASE_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_BASE_HI 0x0082 +#define regSDMA0_QUEUE0_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_RPTR 0x0083 +#define regSDMA0_QUEUE0_RB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_RPTR_HI 0x0084 +#define regSDMA0_QUEUE0_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_WPTR 0x0085 +#define regSDMA0_QUEUE0_RB_WPTR_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_WPTR_HI 0x0086 +#define regSDMA0_QUEUE0_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_RPTR_ADDR_HI 0x0088 +#define regSDMA0_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_RPTR_ADDR_LO 0x0089 +#define regSDMA0_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE0_IB_CNTL 0x008a +#define regSDMA0_QUEUE0_IB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE0_IB_RPTR 0x008b +#define regSDMA0_QUEUE0_IB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE0_IB_OFFSET 0x008c +#define regSDMA0_QUEUE0_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE0_IB_BASE_LO 0x008d +#define regSDMA0_QUEUE0_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_QUEUE0_IB_BASE_HI 0x008e +#define regSDMA0_QUEUE0_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE0_IB_SIZE 0x008f +#define regSDMA0_QUEUE0_IB_SIZE_BASE_IDX 0 +#define regSDMA0_QUEUE0_SKIP_CNTL 0x0090 +#define regSDMA0_QUEUE0_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE0_CONTEXT_STATUS 0x0091 +#define regSDMA0_QUEUE0_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_QUEUE0_DOORBELL 0x0092 +#define regSDMA0_QUEUE0_DOORBELL_BASE_IDX 0 +#define regSDMA0_QUEUE0_DOORBELL_LOG 0x00a9 +#define regSDMA0_QUEUE0_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_QUEUE0_DOORBELL_OFFSET 0x00ab +#define regSDMA0_QUEUE0_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE0_CSA_ADDR_LO 0x00ac +#define regSDMA0_QUEUE0_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE0_CSA_ADDR_HI 0x00ad +#define regSDMA0_QUEUE0_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE0_SCHEDULE_CNTL 0x00ae +#define regSDMA0_QUEUE0_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE0_IB_SUB_REMAIN 0x00af +#define regSDMA0_QUEUE0_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_QUEUE0_PREEMPT 0x00b0 +#define regSDMA0_QUEUE0_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE0_DUMMY_REG 0x00b1 +#define regSDMA0_QUEUE0_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_AQL_CNTL 0x00b4 +#define regSDMA0_QUEUE0_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE0_MINOR_PTR_UPDATE 0x00b5 +#define regSDMA0_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_PREEMPT 0x00b6 +#define regSDMA0_QUEUE0_RB_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA0 0x00c0 +#define regSDMA0_QUEUE0_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA1 0x00c1 +#define regSDMA0_QUEUE0_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA2 0x00c2 +#define regSDMA0_QUEUE0_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA3 0x00c3 +#define regSDMA0_QUEUE0_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA4 0x00c4 +#define regSDMA0_QUEUE0_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA5 0x00c5 +#define regSDMA0_QUEUE0_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA6 0x00c6 +#define regSDMA0_QUEUE0_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA7 0x00c7 +#define regSDMA0_QUEUE0_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA8 0x00c8 +#define regSDMA0_QUEUE0_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA9 0x00c9 +#define regSDMA0_QUEUE0_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA10 0x00ca +#define regSDMA0_QUEUE0_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_CNTL 0x00cb +#define regSDMA0_QUEUE0_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_CNTL 0x00d8 +#define regSDMA0_QUEUE1_RB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_BASE 0x00d9 +#define regSDMA0_QUEUE1_RB_BASE_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_BASE_HI 0x00da +#define regSDMA0_QUEUE1_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_RPTR 0x00db +#define regSDMA0_QUEUE1_RB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_RPTR_HI 0x00dc +#define regSDMA0_QUEUE1_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_WPTR 0x00dd +#define regSDMA0_QUEUE1_RB_WPTR_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_WPTR_HI 0x00de +#define regSDMA0_QUEUE1_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_RPTR_ADDR_HI 0x00e0 +#define regSDMA0_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_RPTR_ADDR_LO 0x00e1 +#define regSDMA0_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE1_IB_CNTL 0x00e2 +#define regSDMA0_QUEUE1_IB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE1_IB_RPTR 0x00e3 +#define regSDMA0_QUEUE1_IB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE1_IB_OFFSET 0x00e4 +#define regSDMA0_QUEUE1_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE1_IB_BASE_LO 0x00e5 +#define regSDMA0_QUEUE1_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_QUEUE1_IB_BASE_HI 0x00e6 +#define regSDMA0_QUEUE1_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE1_IB_SIZE 0x00e7 +#define regSDMA0_QUEUE1_IB_SIZE_BASE_IDX 0 +#define regSDMA0_QUEUE1_SKIP_CNTL 0x00e8 +#define regSDMA0_QUEUE1_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE1_CONTEXT_STATUS 0x00e9 +#define regSDMA0_QUEUE1_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_QUEUE1_DOORBELL 0x00ea +#define regSDMA0_QUEUE1_DOORBELL_BASE_IDX 0 +#define regSDMA0_QUEUE1_DOORBELL_LOG 0x0101 +#define regSDMA0_QUEUE1_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_QUEUE1_DOORBELL_OFFSET 0x0103 +#define regSDMA0_QUEUE1_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE1_CSA_ADDR_LO 0x0104 +#define regSDMA0_QUEUE1_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE1_CSA_ADDR_HI 0x0105 +#define regSDMA0_QUEUE1_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE1_SCHEDULE_CNTL 0x0106 +#define regSDMA0_QUEUE1_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE1_IB_SUB_REMAIN 0x0107 +#define regSDMA0_QUEUE1_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_QUEUE1_PREEMPT 0x0108 +#define regSDMA0_QUEUE1_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE1_DUMMY_REG 0x0109 +#define regSDMA0_QUEUE1_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI 0x010a +#define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO 0x010b +#define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_AQL_CNTL 0x010c +#define regSDMA0_QUEUE1_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE1_MINOR_PTR_UPDATE 0x010d +#define regSDMA0_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_PREEMPT 0x010e +#define regSDMA0_QUEUE1_RB_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA0 0x0118 +#define regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA1 0x0119 +#define regSDMA0_QUEUE1_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA2 0x011a +#define regSDMA0_QUEUE1_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA3 0x011b +#define regSDMA0_QUEUE1_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA4 0x011c +#define regSDMA0_QUEUE1_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA5 0x011d +#define regSDMA0_QUEUE1_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA6 0x011e +#define regSDMA0_QUEUE1_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA7 0x011f +#define regSDMA0_QUEUE1_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA8 0x0120 +#define regSDMA0_QUEUE1_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA9 0x0121 +#define regSDMA0_QUEUE1_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA10 0x0122 +#define regSDMA0_QUEUE1_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_CNTL 0x0123 +#define regSDMA0_QUEUE1_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_CNTL 0x0130 +#define regSDMA0_QUEUE2_RB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_BASE 0x0131 +#define regSDMA0_QUEUE2_RB_BASE_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_BASE_HI 0x0132 +#define regSDMA0_QUEUE2_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_RPTR 0x0133 +#define regSDMA0_QUEUE2_RB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_RPTR_HI 0x0134 +#define regSDMA0_QUEUE2_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_WPTR 0x0135 +#define regSDMA0_QUEUE2_RB_WPTR_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_WPTR_HI 0x0136 +#define regSDMA0_QUEUE2_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_RPTR_ADDR_HI 0x0138 +#define regSDMA0_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_RPTR_ADDR_LO 0x0139 +#define regSDMA0_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE2_IB_CNTL 0x013a +#define regSDMA0_QUEUE2_IB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE2_IB_RPTR 0x013b +#define regSDMA0_QUEUE2_IB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE2_IB_OFFSET 0x013c +#define regSDMA0_QUEUE2_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE2_IB_BASE_LO 0x013d +#define regSDMA0_QUEUE2_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_QUEUE2_IB_BASE_HI 0x013e +#define regSDMA0_QUEUE2_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE2_IB_SIZE 0x013f +#define regSDMA0_QUEUE2_IB_SIZE_BASE_IDX 0 +#define regSDMA0_QUEUE2_SKIP_CNTL 0x0140 +#define regSDMA0_QUEUE2_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE2_CONTEXT_STATUS 0x0141 +#define regSDMA0_QUEUE2_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_QUEUE2_DOORBELL 0x0142 +#define regSDMA0_QUEUE2_DOORBELL_BASE_IDX 0 +#define regSDMA0_QUEUE2_DOORBELL_LOG 0x0159 +#define regSDMA0_QUEUE2_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_QUEUE2_DOORBELL_OFFSET 0x015b +#define regSDMA0_QUEUE2_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE2_CSA_ADDR_LO 0x015c +#define regSDMA0_QUEUE2_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE2_CSA_ADDR_HI 0x015d +#define regSDMA0_QUEUE2_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE2_SCHEDULE_CNTL 0x015e +#define regSDMA0_QUEUE2_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE2_IB_SUB_REMAIN 0x015f +#define regSDMA0_QUEUE2_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_QUEUE2_PREEMPT 0x0160 +#define regSDMA0_QUEUE2_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE2_DUMMY_REG 0x0161 +#define regSDMA0_QUEUE2_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI 0x0162 +#define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO 0x0163 +#define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_AQL_CNTL 0x0164 +#define regSDMA0_QUEUE2_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE2_MINOR_PTR_UPDATE 0x0165 +#define regSDMA0_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_PREEMPT 0x0166 +#define regSDMA0_QUEUE2_RB_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA0 0x0170 +#define regSDMA0_QUEUE2_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA1 0x0171 +#define regSDMA0_QUEUE2_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA2 0x0172 +#define regSDMA0_QUEUE2_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA3 0x0173 +#define regSDMA0_QUEUE2_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA4 0x0174 +#define regSDMA0_QUEUE2_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA5 0x0175 +#define regSDMA0_QUEUE2_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA6 0x0176 +#define regSDMA0_QUEUE2_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA7 0x0177 +#define regSDMA0_QUEUE2_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA8 0x0178 +#define regSDMA0_QUEUE2_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA9 0x0179 +#define regSDMA0_QUEUE2_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA10 0x017a +#define regSDMA0_QUEUE2_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_CNTL 0x017b +#define regSDMA0_QUEUE2_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_CNTL 0x0188 +#define regSDMA0_QUEUE3_RB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_BASE 0x0189 +#define regSDMA0_QUEUE3_RB_BASE_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_BASE_HI 0x018a +#define regSDMA0_QUEUE3_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_RPTR 0x018b +#define regSDMA0_QUEUE3_RB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_RPTR_HI 0x018c +#define regSDMA0_QUEUE3_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_WPTR 0x018d +#define regSDMA0_QUEUE3_RB_WPTR_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_WPTR_HI 0x018e +#define regSDMA0_QUEUE3_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_RPTR_ADDR_HI 0x0190 +#define regSDMA0_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_RPTR_ADDR_LO 0x0191 +#define regSDMA0_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE3_IB_CNTL 0x0192 +#define regSDMA0_QUEUE3_IB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE3_IB_RPTR 0x0193 +#define regSDMA0_QUEUE3_IB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE3_IB_OFFSET 0x0194 +#define regSDMA0_QUEUE3_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE3_IB_BASE_LO 0x0195 +#define regSDMA0_QUEUE3_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_QUEUE3_IB_BASE_HI 0x0196 +#define regSDMA0_QUEUE3_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE3_IB_SIZE 0x0197 +#define regSDMA0_QUEUE3_IB_SIZE_BASE_IDX 0 +#define regSDMA0_QUEUE3_SKIP_CNTL 0x0198 +#define regSDMA0_QUEUE3_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE3_CONTEXT_STATUS 0x0199 +#define regSDMA0_QUEUE3_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_QUEUE3_DOORBELL 0x019a +#define regSDMA0_QUEUE3_DOORBELL_BASE_IDX 0 +#define regSDMA0_QUEUE3_DOORBELL_LOG 0x01b1 +#define regSDMA0_QUEUE3_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_QUEUE3_DOORBELL_OFFSET 0x01b3 +#define regSDMA0_QUEUE3_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE3_CSA_ADDR_LO 0x01b4 +#define regSDMA0_QUEUE3_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE3_CSA_ADDR_HI 0x01b5 +#define regSDMA0_QUEUE3_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE3_SCHEDULE_CNTL 0x01b6 +#define regSDMA0_QUEUE3_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE3_IB_SUB_REMAIN 0x01b7 +#define regSDMA0_QUEUE3_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_QUEUE3_PREEMPT 0x01b8 +#define regSDMA0_QUEUE3_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE3_DUMMY_REG 0x01b9 +#define regSDMA0_QUEUE3_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI 0x01ba +#define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO 0x01bb +#define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_AQL_CNTL 0x01bc +#define regSDMA0_QUEUE3_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE3_MINOR_PTR_UPDATE 0x01bd +#define regSDMA0_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_PREEMPT 0x01be +#define regSDMA0_QUEUE3_RB_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA0 0x01c8 +#define regSDMA0_QUEUE3_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA1 0x01c9 +#define regSDMA0_QUEUE3_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA2 0x01ca +#define regSDMA0_QUEUE3_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA3 0x01cb +#define regSDMA0_QUEUE3_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA4 0x01cc +#define regSDMA0_QUEUE3_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA5 0x01cd +#define regSDMA0_QUEUE3_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA6 0x01ce +#define regSDMA0_QUEUE3_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA7 0x01cf +#define regSDMA0_QUEUE3_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA8 0x01d0 +#define regSDMA0_QUEUE3_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA9 0x01d1 +#define regSDMA0_QUEUE3_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA10 0x01d2 +#define regSDMA0_QUEUE3_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_CNTL 0x01d3 +#define regSDMA0_QUEUE3_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_CNTL 0x01e0 +#define regSDMA0_QUEUE4_RB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_BASE 0x01e1 +#define regSDMA0_QUEUE4_RB_BASE_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_BASE_HI 0x01e2 +#define regSDMA0_QUEUE4_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_RPTR 0x01e3 +#define regSDMA0_QUEUE4_RB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_RPTR_HI 0x01e4 +#define regSDMA0_QUEUE4_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_WPTR 0x01e5 +#define regSDMA0_QUEUE4_RB_WPTR_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_WPTR_HI 0x01e6 +#define regSDMA0_QUEUE4_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_RPTR_ADDR_HI 0x01e8 +#define regSDMA0_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_RPTR_ADDR_LO 0x01e9 +#define regSDMA0_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE4_IB_CNTL 0x01ea +#define regSDMA0_QUEUE4_IB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE4_IB_RPTR 0x01eb +#define regSDMA0_QUEUE4_IB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE4_IB_OFFSET 0x01ec +#define regSDMA0_QUEUE4_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE4_IB_BASE_LO 0x01ed +#define regSDMA0_QUEUE4_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_QUEUE4_IB_BASE_HI 0x01ee +#define regSDMA0_QUEUE4_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE4_IB_SIZE 0x01ef +#define regSDMA0_QUEUE4_IB_SIZE_BASE_IDX 0 +#define regSDMA0_QUEUE4_SKIP_CNTL 0x01f0 +#define regSDMA0_QUEUE4_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE4_CONTEXT_STATUS 0x01f1 +#define regSDMA0_QUEUE4_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_QUEUE4_DOORBELL 0x01f2 +#define regSDMA0_QUEUE4_DOORBELL_BASE_IDX 0 +#define regSDMA0_QUEUE4_DOORBELL_LOG 0x0209 +#define regSDMA0_QUEUE4_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_QUEUE4_DOORBELL_OFFSET 0x020b +#define regSDMA0_QUEUE4_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE4_CSA_ADDR_LO 0x020c +#define regSDMA0_QUEUE4_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE4_CSA_ADDR_HI 0x020d +#define regSDMA0_QUEUE4_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE4_SCHEDULE_CNTL 0x020e +#define regSDMA0_QUEUE4_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE4_IB_SUB_REMAIN 0x020f +#define regSDMA0_QUEUE4_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_QUEUE4_PREEMPT 0x0210 +#define regSDMA0_QUEUE4_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE4_DUMMY_REG 0x0211 +#define regSDMA0_QUEUE4_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI 0x0212 +#define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO 0x0213 +#define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_AQL_CNTL 0x0214 +#define regSDMA0_QUEUE4_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE4_MINOR_PTR_UPDATE 0x0215 +#define regSDMA0_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_PREEMPT 0x0216 +#define regSDMA0_QUEUE4_RB_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA0 0x0220 +#define regSDMA0_QUEUE4_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA1 0x0221 +#define regSDMA0_QUEUE4_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA2 0x0222 +#define regSDMA0_QUEUE4_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA3 0x0223 +#define regSDMA0_QUEUE4_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA4 0x0224 +#define regSDMA0_QUEUE4_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA5 0x0225 +#define regSDMA0_QUEUE4_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA6 0x0226 +#define regSDMA0_QUEUE4_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA7 0x0227 +#define regSDMA0_QUEUE4_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA8 0x0228 +#define regSDMA0_QUEUE4_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA9 0x0229 +#define regSDMA0_QUEUE4_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA10 0x022a +#define regSDMA0_QUEUE4_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_CNTL 0x022b +#define regSDMA0_QUEUE4_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_CNTL 0x0238 +#define regSDMA0_QUEUE5_RB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_BASE 0x0239 +#define regSDMA0_QUEUE5_RB_BASE_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_BASE_HI 0x023a +#define regSDMA0_QUEUE5_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_RPTR 0x023b +#define regSDMA0_QUEUE5_RB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_RPTR_HI 0x023c +#define regSDMA0_QUEUE5_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_WPTR 0x023d +#define regSDMA0_QUEUE5_RB_WPTR_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_WPTR_HI 0x023e +#define regSDMA0_QUEUE5_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_RPTR_ADDR_HI 0x0240 +#define regSDMA0_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_RPTR_ADDR_LO 0x0241 +#define regSDMA0_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE5_IB_CNTL 0x0242 +#define regSDMA0_QUEUE5_IB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE5_IB_RPTR 0x0243 +#define regSDMA0_QUEUE5_IB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE5_IB_OFFSET 0x0244 +#define regSDMA0_QUEUE5_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE5_IB_BASE_LO 0x0245 +#define regSDMA0_QUEUE5_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_QUEUE5_IB_BASE_HI 0x0246 +#define regSDMA0_QUEUE5_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE5_IB_SIZE 0x0247 +#define regSDMA0_QUEUE5_IB_SIZE_BASE_IDX 0 +#define regSDMA0_QUEUE5_SKIP_CNTL 0x0248 +#define regSDMA0_QUEUE5_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE5_CONTEXT_STATUS 0x0249 +#define regSDMA0_QUEUE5_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_QUEUE5_DOORBELL 0x024a +#define regSDMA0_QUEUE5_DOORBELL_BASE_IDX 0 +#define regSDMA0_QUEUE5_DOORBELL_LOG 0x0261 +#define regSDMA0_QUEUE5_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_QUEUE5_DOORBELL_OFFSET 0x0263 +#define regSDMA0_QUEUE5_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE5_CSA_ADDR_LO 0x0264 +#define regSDMA0_QUEUE5_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE5_CSA_ADDR_HI 0x0265 +#define regSDMA0_QUEUE5_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE5_SCHEDULE_CNTL 0x0266 +#define regSDMA0_QUEUE5_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE5_IB_SUB_REMAIN 0x0267 +#define regSDMA0_QUEUE5_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_QUEUE5_PREEMPT 0x0268 +#define regSDMA0_QUEUE5_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE5_DUMMY_REG 0x0269 +#define regSDMA0_QUEUE5_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI 0x026a +#define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO 0x026b +#define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_AQL_CNTL 0x026c +#define regSDMA0_QUEUE5_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE5_MINOR_PTR_UPDATE 0x026d +#define regSDMA0_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_PREEMPT 0x026e +#define regSDMA0_QUEUE5_RB_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA0 0x0278 +#define regSDMA0_QUEUE5_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA1 0x0279 +#define regSDMA0_QUEUE5_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA2 0x027a +#define regSDMA0_QUEUE5_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA3 0x027b +#define regSDMA0_QUEUE5_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA4 0x027c +#define regSDMA0_QUEUE5_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA5 0x027d +#define regSDMA0_QUEUE5_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA6 0x027e +#define regSDMA0_QUEUE5_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA7 0x027f +#define regSDMA0_QUEUE5_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA8 0x0280 +#define regSDMA0_QUEUE5_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA9 0x0281 +#define regSDMA0_QUEUE5_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA10 0x0282 +#define regSDMA0_QUEUE5_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_CNTL 0x0283 +#define regSDMA0_QUEUE5_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_CNTL 0x0290 +#define regSDMA0_QUEUE6_RB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_BASE 0x0291 +#define regSDMA0_QUEUE6_RB_BASE_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_BASE_HI 0x0292 +#define regSDMA0_QUEUE6_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_RPTR 0x0293 +#define regSDMA0_QUEUE6_RB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_RPTR_HI 0x0294 +#define regSDMA0_QUEUE6_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_WPTR 0x0295 +#define regSDMA0_QUEUE6_RB_WPTR_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_WPTR_HI 0x0296 +#define regSDMA0_QUEUE6_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_RPTR_ADDR_HI 0x0298 +#define regSDMA0_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_RPTR_ADDR_LO 0x0299 +#define regSDMA0_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE6_IB_CNTL 0x029a +#define regSDMA0_QUEUE6_IB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE6_IB_RPTR 0x029b +#define regSDMA0_QUEUE6_IB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE6_IB_OFFSET 0x029c +#define regSDMA0_QUEUE6_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE6_IB_BASE_LO 0x029d +#define regSDMA0_QUEUE6_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_QUEUE6_IB_BASE_HI 0x029e +#define regSDMA0_QUEUE6_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE6_IB_SIZE 0x029f +#define regSDMA0_QUEUE6_IB_SIZE_BASE_IDX 0 +#define regSDMA0_QUEUE6_SKIP_CNTL 0x02a0 +#define regSDMA0_QUEUE6_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE6_CONTEXT_STATUS 0x02a1 +#define regSDMA0_QUEUE6_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_QUEUE6_DOORBELL 0x02a2 +#define regSDMA0_QUEUE6_DOORBELL_BASE_IDX 0 +#define regSDMA0_QUEUE6_DOORBELL_LOG 0x02b9 +#define regSDMA0_QUEUE6_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_QUEUE6_DOORBELL_OFFSET 0x02bb +#define regSDMA0_QUEUE6_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE6_CSA_ADDR_LO 0x02bc +#define regSDMA0_QUEUE6_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE6_CSA_ADDR_HI 0x02bd +#define regSDMA0_QUEUE6_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE6_SCHEDULE_CNTL 0x02be +#define regSDMA0_QUEUE6_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE6_IB_SUB_REMAIN 0x02bf +#define regSDMA0_QUEUE6_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_QUEUE6_PREEMPT 0x02c0 +#define regSDMA0_QUEUE6_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE6_DUMMY_REG 0x02c1 +#define regSDMA0_QUEUE6_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI 0x02c2 +#define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO 0x02c3 +#define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_AQL_CNTL 0x02c4 +#define regSDMA0_QUEUE6_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE6_MINOR_PTR_UPDATE 0x02c5 +#define regSDMA0_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_PREEMPT 0x02c6 +#define regSDMA0_QUEUE6_RB_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA0 0x02d0 +#define regSDMA0_QUEUE6_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA1 0x02d1 +#define regSDMA0_QUEUE6_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA2 0x02d2 +#define regSDMA0_QUEUE6_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA3 0x02d3 +#define regSDMA0_QUEUE6_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA4 0x02d4 +#define regSDMA0_QUEUE6_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA5 0x02d5 +#define regSDMA0_QUEUE6_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA6 0x02d6 +#define regSDMA0_QUEUE6_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA7 0x02d7 +#define regSDMA0_QUEUE6_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA8 0x02d8 +#define regSDMA0_QUEUE6_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA9 0x02d9 +#define regSDMA0_QUEUE6_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA10 0x02da +#define regSDMA0_QUEUE6_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_CNTL 0x02db +#define regSDMA0_QUEUE6_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_CNTL 0x02e8 +#define regSDMA0_QUEUE7_RB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_BASE 0x02e9 +#define regSDMA0_QUEUE7_RB_BASE_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_BASE_HI 0x02ea +#define regSDMA0_QUEUE7_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_RPTR 0x02eb +#define regSDMA0_QUEUE7_RB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_RPTR_HI 0x02ec +#define regSDMA0_QUEUE7_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_WPTR 0x02ed +#define regSDMA0_QUEUE7_RB_WPTR_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_WPTR_HI 0x02ee +#define regSDMA0_QUEUE7_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_RPTR_ADDR_HI 0x02f0 +#define regSDMA0_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_RPTR_ADDR_LO 0x02f1 +#define regSDMA0_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE7_IB_CNTL 0x02f2 +#define regSDMA0_QUEUE7_IB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE7_IB_RPTR 0x02f3 +#define regSDMA0_QUEUE7_IB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE7_IB_OFFSET 0x02f4 +#define regSDMA0_QUEUE7_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE7_IB_BASE_LO 0x02f5 +#define regSDMA0_QUEUE7_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_QUEUE7_IB_BASE_HI 0x02f6 +#define regSDMA0_QUEUE7_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE7_IB_SIZE 0x02f7 +#define regSDMA0_QUEUE7_IB_SIZE_BASE_IDX 0 +#define regSDMA0_QUEUE7_SKIP_CNTL 0x02f8 +#define regSDMA0_QUEUE7_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE7_CONTEXT_STATUS 0x02f9 +#define regSDMA0_QUEUE7_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_QUEUE7_DOORBELL 0x02fa +#define regSDMA0_QUEUE7_DOORBELL_BASE_IDX 0 +#define regSDMA0_QUEUE7_DOORBELL_LOG 0x0311 +#define regSDMA0_QUEUE7_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_QUEUE7_DOORBELL_OFFSET 0x0313 +#define regSDMA0_QUEUE7_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE7_CSA_ADDR_LO 0x0314 +#define regSDMA0_QUEUE7_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE7_CSA_ADDR_HI 0x0315 +#define regSDMA0_QUEUE7_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE7_SCHEDULE_CNTL 0x0316 +#define regSDMA0_QUEUE7_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE7_IB_SUB_REMAIN 0x0317 +#define regSDMA0_QUEUE7_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_QUEUE7_PREEMPT 0x0318 +#define regSDMA0_QUEUE7_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE7_DUMMY_REG 0x0319 +#define regSDMA0_QUEUE7_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI 0x031a +#define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO 0x031b +#define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_AQL_CNTL 0x031c +#define regSDMA0_QUEUE7_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE7_MINOR_PTR_UPDATE 0x031d +#define regSDMA0_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_PREEMPT 0x031e +#define regSDMA0_QUEUE7_RB_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA0 0x0328 +#define regSDMA0_QUEUE7_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA1 0x0329 +#define regSDMA0_QUEUE7_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA2 0x032a +#define regSDMA0_QUEUE7_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA3 0x032b +#define regSDMA0_QUEUE7_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA4 0x032c +#define regSDMA0_QUEUE7_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA5 0x032d +#define regSDMA0_QUEUE7_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA6 0x032e +#define regSDMA0_QUEUE7_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA7 0x032f +#define regSDMA0_QUEUE7_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA8 0x0330 +#define regSDMA0_QUEUE7_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA9 0x0331 +#define regSDMA0_QUEUE7_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA10 0x0332 +#define regSDMA0_QUEUE7_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_CNTL 0x0333 +#define regSDMA0_QUEUE7_MIDCMD_CNTL_BASE_IDX 0 + + +// addressBlock: gc_sdma0_sdma1dec +// base address: 0x6180 +#define regSDMA1_DEC_START 0x0600 +#define regSDMA1_DEC_START_BASE_IDX 0 +#define regSDMA1_F32_MISC_CNTL 0x060b +#define regSDMA1_F32_MISC_CNTL_BASE_IDX 0 +#define regSDMA1_GLOBAL_TIMESTAMP_LO 0x060f +#define regSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX 0 +#define regSDMA1_GLOBAL_TIMESTAMP_HI 0x0610 +#define regSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX 0 +#define regSDMA1_POWER_CNTL 0x061a +#define regSDMA1_POWER_CNTL_BASE_IDX 0 +#define regSDMA1_CNTL 0x061c +#define regSDMA1_CNTL_BASE_IDX 0 +#define regSDMA1_CHICKEN_BITS 0x061d +#define regSDMA1_CHICKEN_BITS_BASE_IDX 0 +#define regSDMA1_GB_ADDR_CONFIG 0x061e +#define regSDMA1_GB_ADDR_CONFIG_BASE_IDX 0 +#define regSDMA1_GB_ADDR_CONFIG_READ 0x061f +#define regSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0 +#define regSDMA1_RB_RPTR_FETCH 0x0620 +#define regSDMA1_RB_RPTR_FETCH_BASE_IDX 0 +#define regSDMA1_RB_RPTR_FETCH_HI 0x0621 +#define regSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0622 +#define regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 +#define regSDMA1_IB_OFFSET_FETCH 0x0623 +#define regSDMA1_IB_OFFSET_FETCH_BASE_IDX 0 +#define regSDMA1_PROGRAM 0x0624 +#define regSDMA1_PROGRAM_BASE_IDX 0 +#define regSDMA1_STATUS_REG 0x0625 +#define regSDMA1_STATUS_REG_BASE_IDX 0 +#define regSDMA1_STATUS1_REG 0x0626 +#define regSDMA1_STATUS1_REG_BASE_IDX 0 +#define regSDMA1_CNTL1 0x0627 +#define regSDMA1_CNTL1_BASE_IDX 0 +#define regSDMA1_HBM_PAGE_CONFIG 0x0628 +#define regSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0 +#define regSDMA1_UCODE_CHECKSUM 0x0629 +#define regSDMA1_UCODE_CHECKSUM_BASE_IDX 0 +#define regSDMA1_FREEZE 0x062b +#define regSDMA1_FREEZE_BASE_IDX 0 +#define regSDMA1_PROCESS_QUANTUM0 0x062c +#define regSDMA1_PROCESS_QUANTUM0_BASE_IDX 0 +#define regSDMA1_PROCESS_QUANTUM1 0x062d +#define regSDMA1_PROCESS_QUANTUM1_BASE_IDX 0 +#define regSDMA1_WATCHDOG_CNTL 0x062e +#define regSDMA1_WATCHDOG_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE_STATUS0 0x062f +#define regSDMA1_QUEUE_STATUS0_BASE_IDX 0 +#define regSDMA1_EDC_CONFIG 0x0632 +#define regSDMA1_EDC_CONFIG_BASE_IDX 0 +#define regSDMA1_BA_THRESHOLD 0x0633 +#define regSDMA1_BA_THRESHOLD_BASE_IDX 0 +#define regSDMA1_ID 0x0634 +#define regSDMA1_ID_BASE_IDX 0 +#define regSDMA1_VERSION 0x0635 +#define regSDMA1_VERSION_BASE_IDX 0 +#define regSDMA1_EDC_COUNTER 0x0636 +#define regSDMA1_EDC_COUNTER_BASE_IDX 0 +#define regSDMA1_EDC_COUNTER_CLEAR 0x0637 +#define regSDMA1_EDC_COUNTER_CLEAR_BASE_IDX 0 +#define regSDMA1_STATUS2_REG 0x0638 +#define regSDMA1_STATUS2_REG_BASE_IDX 0 +#define regSDMA1_ATOMIC_CNTL 0x0639 +#define regSDMA1_ATOMIC_CNTL_BASE_IDX 0 +#define regSDMA1_ATOMIC_PREOP_LO 0x063a +#define regSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0 +#define regSDMA1_ATOMIC_PREOP_HI 0x063b +#define regSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0 +#define regSDMA1_UTCL1_CNTL 0x063c +#define regSDMA1_UTCL1_CNTL_BASE_IDX 0 +#define regSDMA1_UTCL1_WATERMK 0x063d +#define regSDMA1_UTCL1_WATERMK_BASE_IDX 0 +#define regSDMA1_UTCL1_TIMEOUT 0x063e +#define regSDMA1_UTCL1_TIMEOUT_BASE_IDX 0 +#define regSDMA1_UTCL1_PAGE 0x063f +#define regSDMA1_UTCL1_PAGE_BASE_IDX 0 +#define regSDMA1_UTCL1_RD_STATUS 0x0640 +#define regSDMA1_UTCL1_RD_STATUS_BASE_IDX 0 +#define regSDMA1_UTCL1_WR_STATUS 0x0641 +#define regSDMA1_UTCL1_WR_STATUS_BASE_IDX 0 +#define regSDMA1_UTCL1_INV0 0x0642 +#define regSDMA1_UTCL1_INV0_BASE_IDX 0 +#define regSDMA1_UTCL1_INV1 0x0643 +#define regSDMA1_UTCL1_INV1_BASE_IDX 0 +#define regSDMA1_UTCL1_INV2 0x0644 +#define regSDMA1_UTCL1_INV2_BASE_IDX 0 +#define regSDMA1_UTCL1_RD_XNACK0 0x0645 +#define regSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0 +#define regSDMA1_UTCL1_RD_XNACK1 0x0646 +#define regSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0 +#define regSDMA1_UTCL1_WR_XNACK0 0x0647 +#define regSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0 +#define regSDMA1_UTCL1_WR_XNACK1 0x0648 +#define regSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0 +#define regSDMA1_RELAX_ORDERING_LUT 0x064a +#define regSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0 +#define regSDMA1_CHICKEN_BITS_2 0x064b +#define regSDMA1_CHICKEN_BITS_2_BASE_IDX 0 +#define regSDMA1_STATUS3_REG 0x064c +#define regSDMA1_STATUS3_REG_BASE_IDX 0 +#define regSDMA1_PHYSICAL_ADDR_LO 0x064d +#define regSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_PHYSICAL_ADDR_HI 0x064e +#define regSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_GLOBAL_QUANTUM 0x064f +#define regSDMA1_GLOBAL_QUANTUM_BASE_IDX 0 +#define regSDMA1_ERROR_LOG 0x0650 +#define regSDMA1_ERROR_LOG_BASE_IDX 0 +#define regSDMA1_PUB_DUMMY_REG0 0x0651 +#define regSDMA1_PUB_DUMMY_REG0_BASE_IDX 0 +#define regSDMA1_PUB_DUMMY_REG1 0x0652 +#define regSDMA1_PUB_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_PUB_DUMMY_REG2 0x0653 +#define regSDMA1_PUB_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_PUB_DUMMY_REG3 0x0654 +#define regSDMA1_PUB_DUMMY_REG3_BASE_IDX 0 +#define regSDMA1_F32_COUNTER 0x0655 +#define regSDMA1_F32_COUNTER_BASE_IDX 0 +#define regSDMA1_CRD_CNTL 0x065b +#define regSDMA1_CRD_CNTL_BASE_IDX 0 +#define regSDMA1_RLC_CGCG_CTRL 0x065c +#define regSDMA1_RLC_CGCG_CTRL_BASE_IDX 0 +#define regSDMA1_AQL_STATUS 0x065f +#define regSDMA1_AQL_STATUS_BASE_IDX 0 +#define regSDMA1_EA_DBIT_ADDR_DATA 0x0660 +#define regSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0 +#define regSDMA1_EA_DBIT_ADDR_INDEX 0x0661 +#define regSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0 +#define regSDMA1_TLBI_GCR_CNTL 0x0662 +#define regSDMA1_TLBI_GCR_CNTL_BASE_IDX 0 +#define regSDMA1_TILING_CONFIG 0x0663 +#define regSDMA1_TILING_CONFIG_BASE_IDX 0 +#define regSDMA1_INT_STATUS 0x0670 +#define regSDMA1_INT_STATUS_BASE_IDX 0 +#define regSDMA1_HOLE_ADDR_LO 0x0672 +#define regSDMA1_HOLE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_HOLE_ADDR_HI 0x0673 +#define regSDMA1_HOLE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_CLOCK_GATING_STATUS 0x0675 +#define regSDMA1_CLOCK_GATING_STATUS_BASE_IDX 0 +#define regSDMA1_STATUS4_REG 0x0676 +#define regSDMA1_STATUS4_REG_BASE_IDX 0 +#define regSDMA1_SCRATCH_RAM_DATA 0x0677 +#define regSDMA1_SCRATCH_RAM_DATA_BASE_IDX 0 +#define regSDMA1_SCRATCH_RAM_ADDR 0x0678 +#define regSDMA1_SCRATCH_RAM_ADDR_BASE_IDX 0 +#define regSDMA1_TIMESTAMP_CNTL 0x0679 +#define regSDMA1_TIMESTAMP_CNTL_BASE_IDX 0 +#define regSDMA1_STATUS5_REG 0x067a +#define regSDMA1_STATUS5_REG_BASE_IDX 0 +#define regSDMA1_QUEUE_RESET_REQ 0x067b +#define regSDMA1_QUEUE_RESET_REQ_BASE_IDX 0 +#define regSDMA1_STATUS6_REG 0x067c +#define regSDMA1_STATUS6_REG_BASE_IDX 0 +#define regSDMA1_UCODE1_CHECKSUM 0x067d +#define regSDMA1_UCODE1_CHECKSUM_BASE_IDX 0 +#define regSDMA1_CE_CTRL 0x067e +#define regSDMA1_CE_CTRL_BASE_IDX 0 +#define regSDMA1_FED_STATUS 0x067f +#define regSDMA1_FED_STATUS_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_CNTL 0x0680 +#define regSDMA1_QUEUE0_RB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_BASE 0x0681 +#define regSDMA1_QUEUE0_RB_BASE_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_BASE_HI 0x0682 +#define regSDMA1_QUEUE0_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_RPTR 0x0683 +#define regSDMA1_QUEUE0_RB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_RPTR_HI 0x0684 +#define regSDMA1_QUEUE0_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_WPTR 0x0685 +#define regSDMA1_QUEUE0_RB_WPTR_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_WPTR_HI 0x0686 +#define regSDMA1_QUEUE0_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_RPTR_ADDR_HI 0x0688 +#define regSDMA1_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_RPTR_ADDR_LO 0x0689 +#define regSDMA1_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE0_IB_CNTL 0x068a +#define regSDMA1_QUEUE0_IB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE0_IB_RPTR 0x068b +#define regSDMA1_QUEUE0_IB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE0_IB_OFFSET 0x068c +#define regSDMA1_QUEUE0_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE0_IB_BASE_LO 0x068d +#define regSDMA1_QUEUE0_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_QUEUE0_IB_BASE_HI 0x068e +#define regSDMA1_QUEUE0_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE0_IB_SIZE 0x068f +#define regSDMA1_QUEUE0_IB_SIZE_BASE_IDX 0 +#define regSDMA1_QUEUE0_SKIP_CNTL 0x0690 +#define regSDMA1_QUEUE0_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE0_CONTEXT_STATUS 0x0691 +#define regSDMA1_QUEUE0_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_QUEUE0_DOORBELL 0x0692 +#define regSDMA1_QUEUE0_DOORBELL_BASE_IDX 0 +#define regSDMA1_QUEUE0_DOORBELL_LOG 0x06a9 +#define regSDMA1_QUEUE0_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_QUEUE0_DOORBELL_OFFSET 0x06ab +#define regSDMA1_QUEUE0_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE0_CSA_ADDR_LO 0x06ac +#define regSDMA1_QUEUE0_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE0_CSA_ADDR_HI 0x06ad +#define regSDMA1_QUEUE0_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE0_SCHEDULE_CNTL 0x06ae +#define regSDMA1_QUEUE0_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE0_IB_SUB_REMAIN 0x06af +#define regSDMA1_QUEUE0_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_QUEUE0_PREEMPT 0x06b0 +#define regSDMA1_QUEUE0_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE0_DUMMY_REG 0x06b1 +#define regSDMA1_QUEUE0_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI 0x06b2 +#define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO 0x06b3 +#define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_AQL_CNTL 0x06b4 +#define regSDMA1_QUEUE0_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE0_MINOR_PTR_UPDATE 0x06b5 +#define regSDMA1_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_PREEMPT 0x06b6 +#define regSDMA1_QUEUE0_RB_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA0 0x06c0 +#define regSDMA1_QUEUE0_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA1 0x06c1 +#define regSDMA1_QUEUE0_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA2 0x06c2 +#define regSDMA1_QUEUE0_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA3 0x06c3 +#define regSDMA1_QUEUE0_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA4 0x06c4 +#define regSDMA1_QUEUE0_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA5 0x06c5 +#define regSDMA1_QUEUE0_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA6 0x06c6 +#define regSDMA1_QUEUE0_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA7 0x06c7 +#define regSDMA1_QUEUE0_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA8 0x06c8 +#define regSDMA1_QUEUE0_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA9 0x06c9 +#define regSDMA1_QUEUE0_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA10 0x06ca +#define regSDMA1_QUEUE0_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_CNTL 0x06cb +#define regSDMA1_QUEUE0_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_CNTL 0x06d8 +#define regSDMA1_QUEUE1_RB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_BASE 0x06d9 +#define regSDMA1_QUEUE1_RB_BASE_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_BASE_HI 0x06da +#define regSDMA1_QUEUE1_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_RPTR 0x06db +#define regSDMA1_QUEUE1_RB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_RPTR_HI 0x06dc +#define regSDMA1_QUEUE1_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_WPTR 0x06dd +#define regSDMA1_QUEUE1_RB_WPTR_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_WPTR_HI 0x06de +#define regSDMA1_QUEUE1_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_RPTR_ADDR_HI 0x06e0 +#define regSDMA1_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_RPTR_ADDR_LO 0x06e1 +#define regSDMA1_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE1_IB_CNTL 0x06e2 +#define regSDMA1_QUEUE1_IB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE1_IB_RPTR 0x06e3 +#define regSDMA1_QUEUE1_IB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE1_IB_OFFSET 0x06e4 +#define regSDMA1_QUEUE1_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE1_IB_BASE_LO 0x06e5 +#define regSDMA1_QUEUE1_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_QUEUE1_IB_BASE_HI 0x06e6 +#define regSDMA1_QUEUE1_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE1_IB_SIZE 0x06e7 +#define regSDMA1_QUEUE1_IB_SIZE_BASE_IDX 0 +#define regSDMA1_QUEUE1_SKIP_CNTL 0x06e8 +#define regSDMA1_QUEUE1_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE1_CONTEXT_STATUS 0x06e9 +#define regSDMA1_QUEUE1_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_QUEUE1_DOORBELL 0x06ea +#define regSDMA1_QUEUE1_DOORBELL_BASE_IDX 0 +#define regSDMA1_QUEUE1_DOORBELL_LOG 0x0701 +#define regSDMA1_QUEUE1_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_QUEUE1_DOORBELL_OFFSET 0x0703 +#define regSDMA1_QUEUE1_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE1_CSA_ADDR_LO 0x0704 +#define regSDMA1_QUEUE1_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE1_CSA_ADDR_HI 0x0705 +#define regSDMA1_QUEUE1_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE1_SCHEDULE_CNTL 0x0706 +#define regSDMA1_QUEUE1_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE1_IB_SUB_REMAIN 0x0707 +#define regSDMA1_QUEUE1_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_QUEUE1_PREEMPT 0x0708 +#define regSDMA1_QUEUE1_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE1_DUMMY_REG 0x0709 +#define regSDMA1_QUEUE1_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI 0x070a +#define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO 0x070b +#define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_AQL_CNTL 0x070c +#define regSDMA1_QUEUE1_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE1_MINOR_PTR_UPDATE 0x070d +#define regSDMA1_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_PREEMPT 0x070e +#define regSDMA1_QUEUE1_RB_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA0 0x0718 +#define regSDMA1_QUEUE1_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA1 0x0719 +#define regSDMA1_QUEUE1_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA2 0x071a +#define regSDMA1_QUEUE1_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA3 0x071b +#define regSDMA1_QUEUE1_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA4 0x071c +#define regSDMA1_QUEUE1_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA5 0x071d +#define regSDMA1_QUEUE1_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA6 0x071e +#define regSDMA1_QUEUE1_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA7 0x071f +#define regSDMA1_QUEUE1_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA8 0x0720 +#define regSDMA1_QUEUE1_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA9 0x0721 +#define regSDMA1_QUEUE1_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA10 0x0722 +#define regSDMA1_QUEUE1_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_CNTL 0x0723 +#define regSDMA1_QUEUE1_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_CNTL 0x0730 +#define regSDMA1_QUEUE2_RB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_BASE 0x0731 +#define regSDMA1_QUEUE2_RB_BASE_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_BASE_HI 0x0732 +#define regSDMA1_QUEUE2_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_RPTR 0x0733 +#define regSDMA1_QUEUE2_RB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_RPTR_HI 0x0734 +#define regSDMA1_QUEUE2_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_WPTR 0x0735 +#define regSDMA1_QUEUE2_RB_WPTR_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_WPTR_HI 0x0736 +#define regSDMA1_QUEUE2_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_RPTR_ADDR_HI 0x0738 +#define regSDMA1_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_RPTR_ADDR_LO 0x0739 +#define regSDMA1_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE2_IB_CNTL 0x073a +#define regSDMA1_QUEUE2_IB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE2_IB_RPTR 0x073b +#define regSDMA1_QUEUE2_IB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE2_IB_OFFSET 0x073c +#define regSDMA1_QUEUE2_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE2_IB_BASE_LO 0x073d +#define regSDMA1_QUEUE2_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_QUEUE2_IB_BASE_HI 0x073e +#define regSDMA1_QUEUE2_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE2_IB_SIZE 0x073f +#define regSDMA1_QUEUE2_IB_SIZE_BASE_IDX 0 +#define regSDMA1_QUEUE2_SKIP_CNTL 0x0740 +#define regSDMA1_QUEUE2_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE2_CONTEXT_STATUS 0x0741 +#define regSDMA1_QUEUE2_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_QUEUE2_DOORBELL 0x0742 +#define regSDMA1_QUEUE2_DOORBELL_BASE_IDX 0 +#define regSDMA1_QUEUE2_DOORBELL_LOG 0x0759 +#define regSDMA1_QUEUE2_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_QUEUE2_DOORBELL_OFFSET 0x075b +#define regSDMA1_QUEUE2_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE2_CSA_ADDR_LO 0x075c +#define regSDMA1_QUEUE2_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE2_CSA_ADDR_HI 0x075d +#define regSDMA1_QUEUE2_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE2_SCHEDULE_CNTL 0x075e +#define regSDMA1_QUEUE2_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE2_IB_SUB_REMAIN 0x075f +#define regSDMA1_QUEUE2_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_QUEUE2_PREEMPT 0x0760 +#define regSDMA1_QUEUE2_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE2_DUMMY_REG 0x0761 +#define regSDMA1_QUEUE2_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI 0x0762 +#define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO 0x0763 +#define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_AQL_CNTL 0x0764 +#define regSDMA1_QUEUE2_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE2_MINOR_PTR_UPDATE 0x0765 +#define regSDMA1_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_PREEMPT 0x0766 +#define regSDMA1_QUEUE2_RB_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA0 0x0770 +#define regSDMA1_QUEUE2_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA1 0x0771 +#define regSDMA1_QUEUE2_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA2 0x0772 +#define regSDMA1_QUEUE2_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA3 0x0773 +#define regSDMA1_QUEUE2_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA4 0x0774 +#define regSDMA1_QUEUE2_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA5 0x0775 +#define regSDMA1_QUEUE2_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA6 0x0776 +#define regSDMA1_QUEUE2_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA7 0x0777 +#define regSDMA1_QUEUE2_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA8 0x0778 +#define regSDMA1_QUEUE2_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA9 0x0779 +#define regSDMA1_QUEUE2_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA10 0x077a +#define regSDMA1_QUEUE2_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_CNTL 0x077b +#define regSDMA1_QUEUE2_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_CNTL 0x0788 +#define regSDMA1_QUEUE3_RB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_BASE 0x0789 +#define regSDMA1_QUEUE3_RB_BASE_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_BASE_HI 0x078a +#define regSDMA1_QUEUE3_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_RPTR 0x078b +#define regSDMA1_QUEUE3_RB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_RPTR_HI 0x078c +#define regSDMA1_QUEUE3_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_WPTR 0x078d +#define regSDMA1_QUEUE3_RB_WPTR_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_WPTR_HI 0x078e +#define regSDMA1_QUEUE3_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_RPTR_ADDR_HI 0x0790 +#define regSDMA1_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_RPTR_ADDR_LO 0x0791 +#define regSDMA1_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE3_IB_CNTL 0x0792 +#define regSDMA1_QUEUE3_IB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE3_IB_RPTR 0x0793 +#define regSDMA1_QUEUE3_IB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE3_IB_OFFSET 0x0794 +#define regSDMA1_QUEUE3_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE3_IB_BASE_LO 0x0795 +#define regSDMA1_QUEUE3_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_QUEUE3_IB_BASE_HI 0x0796 +#define regSDMA1_QUEUE3_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE3_IB_SIZE 0x0797 +#define regSDMA1_QUEUE3_IB_SIZE_BASE_IDX 0 +#define regSDMA1_QUEUE3_SKIP_CNTL 0x0798 +#define regSDMA1_QUEUE3_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE3_CONTEXT_STATUS 0x0799 +#define regSDMA1_QUEUE3_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_QUEUE3_DOORBELL 0x079a +#define regSDMA1_QUEUE3_DOORBELL_BASE_IDX 0 +#define regSDMA1_QUEUE3_DOORBELL_LOG 0x07b1 +#define regSDMA1_QUEUE3_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_QUEUE3_DOORBELL_OFFSET 0x07b3 +#define regSDMA1_QUEUE3_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE3_CSA_ADDR_LO 0x07b4 +#define regSDMA1_QUEUE3_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE3_CSA_ADDR_HI 0x07b5 +#define regSDMA1_QUEUE3_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE3_SCHEDULE_CNTL 0x07b6 +#define regSDMA1_QUEUE3_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE3_IB_SUB_REMAIN 0x07b7 +#define regSDMA1_QUEUE3_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_QUEUE3_PREEMPT 0x07b8 +#define regSDMA1_QUEUE3_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE3_DUMMY_REG 0x07b9 +#define regSDMA1_QUEUE3_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI 0x07ba +#define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO 0x07bb +#define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_AQL_CNTL 0x07bc +#define regSDMA1_QUEUE3_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE3_MINOR_PTR_UPDATE 0x07bd +#define regSDMA1_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_PREEMPT 0x07be +#define regSDMA1_QUEUE3_RB_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA0 0x07c8 +#define regSDMA1_QUEUE3_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA1 0x07c9 +#define regSDMA1_QUEUE3_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA2 0x07ca +#define regSDMA1_QUEUE3_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA3 0x07cb +#define regSDMA1_QUEUE3_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA4 0x07cc +#define regSDMA1_QUEUE3_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA5 0x07cd +#define regSDMA1_QUEUE3_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA6 0x07ce +#define regSDMA1_QUEUE3_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA7 0x07cf +#define regSDMA1_QUEUE3_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA8 0x07d0 +#define regSDMA1_QUEUE3_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA9 0x07d1 +#define regSDMA1_QUEUE3_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA10 0x07d2 +#define regSDMA1_QUEUE3_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_CNTL 0x07d3 +#define regSDMA1_QUEUE3_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_CNTL 0x07e0 +#define regSDMA1_QUEUE4_RB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_BASE 0x07e1 +#define regSDMA1_QUEUE4_RB_BASE_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_BASE_HI 0x07e2 +#define regSDMA1_QUEUE4_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_RPTR 0x07e3 +#define regSDMA1_QUEUE4_RB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_RPTR_HI 0x07e4 +#define regSDMA1_QUEUE4_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_WPTR 0x07e5 +#define regSDMA1_QUEUE4_RB_WPTR_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_WPTR_HI 0x07e6 +#define regSDMA1_QUEUE4_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_RPTR_ADDR_HI 0x07e8 +#define regSDMA1_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_RPTR_ADDR_LO 0x07e9 +#define regSDMA1_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE4_IB_CNTL 0x07ea +#define regSDMA1_QUEUE4_IB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE4_IB_RPTR 0x07eb +#define regSDMA1_QUEUE4_IB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE4_IB_OFFSET 0x07ec +#define regSDMA1_QUEUE4_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE4_IB_BASE_LO 0x07ed +#define regSDMA1_QUEUE4_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_QUEUE4_IB_BASE_HI 0x07ee +#define regSDMA1_QUEUE4_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE4_IB_SIZE 0x07ef +#define regSDMA1_QUEUE4_IB_SIZE_BASE_IDX 0 +#define regSDMA1_QUEUE4_SKIP_CNTL 0x07f0 +#define regSDMA1_QUEUE4_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE4_CONTEXT_STATUS 0x07f1 +#define regSDMA1_QUEUE4_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_QUEUE4_DOORBELL 0x07f2 +#define regSDMA1_QUEUE4_DOORBELL_BASE_IDX 0 +#define regSDMA1_QUEUE4_DOORBELL_LOG 0x0809 +#define regSDMA1_QUEUE4_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_QUEUE4_DOORBELL_OFFSET 0x080b +#define regSDMA1_QUEUE4_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE4_CSA_ADDR_LO 0x080c +#define regSDMA1_QUEUE4_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE4_CSA_ADDR_HI 0x080d +#define regSDMA1_QUEUE4_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE4_SCHEDULE_CNTL 0x080e +#define regSDMA1_QUEUE4_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE4_IB_SUB_REMAIN 0x080f +#define regSDMA1_QUEUE4_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_QUEUE4_PREEMPT 0x0810 +#define regSDMA1_QUEUE4_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE4_DUMMY_REG 0x0811 +#define regSDMA1_QUEUE4_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI 0x0812 +#define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO 0x0813 +#define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_AQL_CNTL 0x0814 +#define regSDMA1_QUEUE4_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE4_MINOR_PTR_UPDATE 0x0815 +#define regSDMA1_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_PREEMPT 0x0816 +#define regSDMA1_QUEUE4_RB_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA0 0x0820 +#define regSDMA1_QUEUE4_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA1 0x0821 +#define regSDMA1_QUEUE4_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA2 0x0822 +#define regSDMA1_QUEUE4_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA3 0x0823 +#define regSDMA1_QUEUE4_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA4 0x0824 +#define regSDMA1_QUEUE4_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA5 0x0825 +#define regSDMA1_QUEUE4_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA6 0x0826 +#define regSDMA1_QUEUE4_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA7 0x0827 +#define regSDMA1_QUEUE4_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA8 0x0828 +#define regSDMA1_QUEUE4_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA9 0x0829 +#define regSDMA1_QUEUE4_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA10 0x082a +#define regSDMA1_QUEUE4_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_CNTL 0x082b +#define regSDMA1_QUEUE4_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_CNTL 0x0838 +#define regSDMA1_QUEUE5_RB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_BASE 0x0839 +#define regSDMA1_QUEUE5_RB_BASE_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_BASE_HI 0x083a +#define regSDMA1_QUEUE5_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_RPTR 0x083b +#define regSDMA1_QUEUE5_RB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_RPTR_HI 0x083c +#define regSDMA1_QUEUE5_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_WPTR 0x083d +#define regSDMA1_QUEUE5_RB_WPTR_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_WPTR_HI 0x083e +#define regSDMA1_QUEUE5_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_RPTR_ADDR_HI 0x0840 +#define regSDMA1_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_RPTR_ADDR_LO 0x0841 +#define regSDMA1_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE5_IB_CNTL 0x0842 +#define regSDMA1_QUEUE5_IB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE5_IB_RPTR 0x0843 +#define regSDMA1_QUEUE5_IB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE5_IB_OFFSET 0x0844 +#define regSDMA1_QUEUE5_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE5_IB_BASE_LO 0x0845 +#define regSDMA1_QUEUE5_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_QUEUE5_IB_BASE_HI 0x0846 +#define regSDMA1_QUEUE5_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE5_IB_SIZE 0x0847 +#define regSDMA1_QUEUE5_IB_SIZE_BASE_IDX 0 +#define regSDMA1_QUEUE5_SKIP_CNTL 0x0848 +#define regSDMA1_QUEUE5_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE5_CONTEXT_STATUS 0x0849 +#define regSDMA1_QUEUE5_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_QUEUE5_DOORBELL 0x084a +#define regSDMA1_QUEUE5_DOORBELL_BASE_IDX 0 +#define regSDMA1_QUEUE5_DOORBELL_LOG 0x0861 +#define regSDMA1_QUEUE5_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_QUEUE5_DOORBELL_OFFSET 0x0863 +#define regSDMA1_QUEUE5_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE5_CSA_ADDR_LO 0x0864 +#define regSDMA1_QUEUE5_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE5_CSA_ADDR_HI 0x0865 +#define regSDMA1_QUEUE5_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE5_SCHEDULE_CNTL 0x0866 +#define regSDMA1_QUEUE5_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE5_IB_SUB_REMAIN 0x0867 +#define regSDMA1_QUEUE5_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_QUEUE5_PREEMPT 0x0868 +#define regSDMA1_QUEUE5_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE5_DUMMY_REG 0x0869 +#define regSDMA1_QUEUE5_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI 0x086a +#define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO 0x086b +#define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_AQL_CNTL 0x086c +#define regSDMA1_QUEUE5_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE5_MINOR_PTR_UPDATE 0x086d +#define regSDMA1_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_PREEMPT 0x086e +#define regSDMA1_QUEUE5_RB_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA0 0x0878 +#define regSDMA1_QUEUE5_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA1 0x0879 +#define regSDMA1_QUEUE5_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA2 0x087a +#define regSDMA1_QUEUE5_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA3 0x087b +#define regSDMA1_QUEUE5_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA4 0x087c +#define regSDMA1_QUEUE5_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA5 0x087d +#define regSDMA1_QUEUE5_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA6 0x087e +#define regSDMA1_QUEUE5_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA7 0x087f +#define regSDMA1_QUEUE5_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA8 0x0880 +#define regSDMA1_QUEUE5_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA9 0x0881 +#define regSDMA1_QUEUE5_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA10 0x0882 +#define regSDMA1_QUEUE5_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_CNTL 0x0883 +#define regSDMA1_QUEUE5_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_CNTL 0x0890 +#define regSDMA1_QUEUE6_RB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_BASE 0x0891 +#define regSDMA1_QUEUE6_RB_BASE_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_BASE_HI 0x0892 +#define regSDMA1_QUEUE6_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_RPTR 0x0893 +#define regSDMA1_QUEUE6_RB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_RPTR_HI 0x0894 +#define regSDMA1_QUEUE6_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_WPTR 0x0895 +#define regSDMA1_QUEUE6_RB_WPTR_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_WPTR_HI 0x0896 +#define regSDMA1_QUEUE6_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_RPTR_ADDR_HI 0x0898 +#define regSDMA1_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_RPTR_ADDR_LO 0x0899 +#define regSDMA1_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE6_IB_CNTL 0x089a +#define regSDMA1_QUEUE6_IB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE6_IB_RPTR 0x089b +#define regSDMA1_QUEUE6_IB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE6_IB_OFFSET 0x089c +#define regSDMA1_QUEUE6_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE6_IB_BASE_LO 0x089d +#define regSDMA1_QUEUE6_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_QUEUE6_IB_BASE_HI 0x089e +#define regSDMA1_QUEUE6_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE6_IB_SIZE 0x089f +#define regSDMA1_QUEUE6_IB_SIZE_BASE_IDX 0 +#define regSDMA1_QUEUE6_SKIP_CNTL 0x08a0 +#define regSDMA1_QUEUE6_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE6_CONTEXT_STATUS 0x08a1 +#define regSDMA1_QUEUE6_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_QUEUE6_DOORBELL 0x08a2 +#define regSDMA1_QUEUE6_DOORBELL_BASE_IDX 0 +#define regSDMA1_QUEUE6_DOORBELL_LOG 0x08b9 +#define regSDMA1_QUEUE6_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_QUEUE6_DOORBELL_OFFSET 0x08bb +#define regSDMA1_QUEUE6_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE6_CSA_ADDR_LO 0x08bc +#define regSDMA1_QUEUE6_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE6_CSA_ADDR_HI 0x08bd +#define regSDMA1_QUEUE6_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE6_SCHEDULE_CNTL 0x08be +#define regSDMA1_QUEUE6_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE6_IB_SUB_REMAIN 0x08bf +#define regSDMA1_QUEUE6_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_QUEUE6_PREEMPT 0x08c0 +#define regSDMA1_QUEUE6_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE6_DUMMY_REG 0x08c1 +#define regSDMA1_QUEUE6_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI 0x08c2 +#define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO 0x08c3 +#define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_AQL_CNTL 0x08c4 +#define regSDMA1_QUEUE6_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE6_MINOR_PTR_UPDATE 0x08c5 +#define regSDMA1_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_PREEMPT 0x08c6 +#define regSDMA1_QUEUE6_RB_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA0 0x08d0 +#define regSDMA1_QUEUE6_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA1 0x08d1 +#define regSDMA1_QUEUE6_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA2 0x08d2 +#define regSDMA1_QUEUE6_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA3 0x08d3 +#define regSDMA1_QUEUE6_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA4 0x08d4 +#define regSDMA1_QUEUE6_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA5 0x08d5 +#define regSDMA1_QUEUE6_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA6 0x08d6 +#define regSDMA1_QUEUE6_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA7 0x08d7 +#define regSDMA1_QUEUE6_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA8 0x08d8 +#define regSDMA1_QUEUE6_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA9 0x08d9 +#define regSDMA1_QUEUE6_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA10 0x08da +#define regSDMA1_QUEUE6_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_CNTL 0x08db +#define regSDMA1_QUEUE6_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_CNTL 0x08e8 +#define regSDMA1_QUEUE7_RB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_BASE 0x08e9 +#define regSDMA1_QUEUE7_RB_BASE_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_BASE_HI 0x08ea +#define regSDMA1_QUEUE7_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_RPTR 0x08eb +#define regSDMA1_QUEUE7_RB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_RPTR_HI 0x08ec +#define regSDMA1_QUEUE7_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_WPTR 0x08ed +#define regSDMA1_QUEUE7_RB_WPTR_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_WPTR_HI 0x08ee +#define regSDMA1_QUEUE7_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_RPTR_ADDR_HI 0x08f0 +#define regSDMA1_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_RPTR_ADDR_LO 0x08f1 +#define regSDMA1_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE7_IB_CNTL 0x08f2 +#define regSDMA1_QUEUE7_IB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE7_IB_RPTR 0x08f3 +#define regSDMA1_QUEUE7_IB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE7_IB_OFFSET 0x08f4 +#define regSDMA1_QUEUE7_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE7_IB_BASE_LO 0x08f5 +#define regSDMA1_QUEUE7_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_QUEUE7_IB_BASE_HI 0x08f6 +#define regSDMA1_QUEUE7_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE7_IB_SIZE 0x08f7 +#define regSDMA1_QUEUE7_IB_SIZE_BASE_IDX 0 +#define regSDMA1_QUEUE7_SKIP_CNTL 0x08f8 +#define regSDMA1_QUEUE7_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE7_CONTEXT_STATUS 0x08f9 +#define regSDMA1_QUEUE7_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_QUEUE7_DOORBELL 0x08fa +#define regSDMA1_QUEUE7_DOORBELL_BASE_IDX 0 +#define regSDMA1_QUEUE7_DOORBELL_LOG 0x0911 +#define regSDMA1_QUEUE7_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_QUEUE7_DOORBELL_OFFSET 0x0913 +#define regSDMA1_QUEUE7_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE7_CSA_ADDR_LO 0x0914 +#define regSDMA1_QUEUE7_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE7_CSA_ADDR_HI 0x0915 +#define regSDMA1_QUEUE7_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE7_SCHEDULE_CNTL 0x0916 +#define regSDMA1_QUEUE7_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE7_IB_SUB_REMAIN 0x0917 +#define regSDMA1_QUEUE7_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_QUEUE7_PREEMPT 0x0918 +#define regSDMA1_QUEUE7_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE7_DUMMY_REG 0x0919 +#define regSDMA1_QUEUE7_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI 0x091a +#define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO 0x091b +#define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_AQL_CNTL 0x091c +#define regSDMA1_QUEUE7_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE7_MINOR_PTR_UPDATE 0x091d +#define regSDMA1_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_PREEMPT 0x091e +#define regSDMA1_QUEUE7_RB_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA0 0x0928 +#define regSDMA1_QUEUE7_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA1 0x0929 +#define regSDMA1_QUEUE7_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA2 0x092a +#define regSDMA1_QUEUE7_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA3 0x092b +#define regSDMA1_QUEUE7_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA4 0x092c +#define regSDMA1_QUEUE7_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA5 0x092d +#define regSDMA1_QUEUE7_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA6 0x092e +#define regSDMA1_QUEUE7_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA7 0x092f +#define regSDMA1_QUEUE7_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA8 0x0930 +#define regSDMA1_QUEUE7_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA9 0x0931 +#define regSDMA1_QUEUE7_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA10 0x0932 +#define regSDMA1_QUEUE7_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_CNTL 0x0933 +#define regSDMA1_QUEUE7_MIDCMD_CNTL_BASE_IDX 0 + + +// addressBlock: gc_sdma0_sdma0hypdec +// base address: 0x3e200 +#define regSDMA0_UCODE_ADDR 0x5880 +#define regSDMA0_UCODE_ADDR_BASE_IDX 1 +#define regSDMA0_UCODE_DATA 0x5881 +#define regSDMA0_UCODE_DATA_BASE_IDX 1 +#define regSDMA0_UCODE_SELFLOAD_CONTROL 0x5882 +#define regSDMA0_UCODE_SELFLOAD_CONTROL_BASE_IDX 1 +#define regSDMA0_BROADCAST_UCODE_ADDR 0x5886 +#define regSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX 1 +#define regSDMA0_BROADCAST_UCODE_DATA 0x5887 +#define regSDMA0_BROADCAST_UCODE_DATA_BASE_IDX 1 +#define regSDMA0_F32_CNTL 0x589a +#define regSDMA0_F32_CNTL_BASE_IDX 1 + + +// addressBlock: gc_sdma0_sdma1hypdec +// base address: 0x3e280 +#define regSDMA1_UCODE_ADDR 0x58a0 +#define regSDMA1_UCODE_ADDR_BASE_IDX 1 +#define regSDMA1_UCODE_DATA 0x58a1 +#define regSDMA1_UCODE_DATA_BASE_IDX 1 +#define regSDMA1_UCODE_SELFLOAD_CONTROL 0x58a2 +#define regSDMA1_UCODE_SELFLOAD_CONTROL_BASE_IDX 1 +#define regSDMA1_BROADCAST_UCODE_ADDR 0x58a6 +#define regSDMA1_BROADCAST_UCODE_ADDR_BASE_IDX 1 +#define regSDMA1_BROADCAST_UCODE_DATA 0x58a7 +#define regSDMA1_BROADCAST_UCODE_DATA_BASE_IDX 1 +#define regSDMA1_F32_CNTL 0x58ba +#define regSDMA1_F32_CNTL_BASE_IDX 1 + + +// addressBlock: gc_sdma0_sdma0perfsdec +// base address: 0x37880 +#define regSDMA0_PERFCNT_PERFCOUNTER0_CFG 0x3e20 +#define regSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regSDMA0_PERFCNT_PERFCOUNTER1_CFG 0x3e21 +#define regSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x3e22 +#define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regSDMA0_PERFCNT_MISC_CNTL 0x3e23 +#define regSDMA0_PERFCNT_MISC_CNTL_BASE_IDX 1 +#define regSDMA0_PERFCOUNTER0_SELECT 0x3e24 +#define regSDMA0_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSDMA0_PERFCOUNTER0_SELECT1 0x3e25 +#define regSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regSDMA0_PERFCOUNTER1_SELECT 0x3e26 +#define regSDMA0_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSDMA0_PERFCOUNTER1_SELECT1 0x3e27 +#define regSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX 1 + + +// addressBlock: gc_sdma0_sdma1perfsdec +// base address: 0x378b0 +#define regSDMA1_PERFCNT_PERFCOUNTER0_CFG 0x3e2c +#define regSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regSDMA1_PERFCNT_PERFCOUNTER1_CFG 0x3e2d +#define regSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x3e2e +#define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regSDMA1_PERFCNT_MISC_CNTL 0x3e2f +#define regSDMA1_PERFCNT_MISC_CNTL_BASE_IDX 1 +#define regSDMA1_PERFCOUNTER0_SELECT 0x3e30 +#define regSDMA1_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSDMA1_PERFCOUNTER0_SELECT1 0x3e31 +#define regSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regSDMA1_PERFCOUNTER1_SELECT 0x3e32 +#define regSDMA1_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSDMA1_PERFCOUNTER1_SELECT1 0x3e33 +#define regSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX 1 + + +// addressBlock: gc_sdma0_sdma0perfddec +// base address: 0x35980 +#define regSDMA0_PERFCNT_PERFCOUNTER_LO 0x3660 +#define regSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX 1 +#define regSDMA0_PERFCNT_PERFCOUNTER_HI 0x3661 +#define regSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX 1 +#define regSDMA0_PERFCOUNTER0_LO 0x3662 +#define regSDMA0_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSDMA0_PERFCOUNTER0_HI 0x3663 +#define regSDMA0_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSDMA0_PERFCOUNTER1_LO 0x3664 +#define regSDMA0_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSDMA0_PERFCOUNTER1_HI 0x3665 +#define regSDMA0_PERFCOUNTER1_HI_BASE_IDX 1 + + +// addressBlock: gc_sdma0_sdma1perfddec +// base address: 0x359b0 +#define regSDMA1_PERFCNT_PERFCOUNTER_LO 0x366c +#define regSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX 1 +#define regSDMA1_PERFCNT_PERFCOUNTER_HI 0x366d +#define regSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX 1 +#define regSDMA1_PERFCOUNTER0_LO 0x366e +#define regSDMA1_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSDMA1_PERFCOUNTER0_HI 0x366f +#define regSDMA1_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSDMA1_PERFCOUNTER1_LO 0x3670 +#define regSDMA1_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSDMA1_PERFCOUNTER1_HI 0x3671 +#define regSDMA1_PERFCOUNTER1_HI_BASE_IDX 1 + + +// addressBlock: gc_grbmdec +// base address: 0x8000 +#define regGRBM_CNTL 0x0da0 +#define regGRBM_CNTL_BASE_IDX 0 +#define regGRBM_SKEW_CNTL 0x0da1 +#define regGRBM_SKEW_CNTL_BASE_IDX 0 +#define regGRBM_STATUS2 0x0da2 +#define regGRBM_STATUS2_BASE_IDX 0 +#define regGRBM_PWR_CNTL 0x0da3 +#define regGRBM_PWR_CNTL_BASE_IDX 0 +#define regGRBM_STATUS 0x0da4 +#define regGRBM_STATUS_BASE_IDX 0 +#define regGRBM_STATUS_SE0 0x0da5 +#define regGRBM_STATUS_SE0_BASE_IDX 0 +#define regGRBM_STATUS_SE1 0x0da6 +#define regGRBM_STATUS_SE1_BASE_IDX 0 +#define regGRBM_STATUS3 0x0da7 +#define regGRBM_STATUS3_BASE_IDX 0 +#define regGRBM_SOFT_RESET 0x0da8 +#define regGRBM_SOFT_RESET_BASE_IDX 0 +#define regGRBM_GFX_CLKEN_CNTL 0x0dac +#define regGRBM_GFX_CLKEN_CNTL_BASE_IDX 0 +#define regGRBM_WAIT_IDLE_CLOCKS 0x0dad +#define regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0 +#define regGRBM_STATUS_SE2 0x0dae +#define regGRBM_STATUS_SE2_BASE_IDX 0 +#define regGRBM_STATUS_SE3 0x0daf +#define regGRBM_STATUS_SE3_BASE_IDX 0 +#define regGRBM_STATUS_SE4 0x0db0 +#define regGRBM_STATUS_SE4_BASE_IDX 0 +#define regGRBM_STATUS_SE5 0x0db1 +#define regGRBM_STATUS_SE5_BASE_IDX 0 +#define regGRBM_READ_ERROR 0x0db6 +#define regGRBM_READ_ERROR_BASE_IDX 0 +#define regGRBM_READ_ERROR2 0x0db7 +#define regGRBM_READ_ERROR2_BASE_IDX 0 +#define regGRBM_INT_CNTL 0x0db8 +#define regGRBM_INT_CNTL_BASE_IDX 0 +#define regGRBM_TRAP_OP 0x0db9 +#define regGRBM_TRAP_OP_BASE_IDX 0 +#define regGRBM_TRAP_ADDR 0x0dba +#define regGRBM_TRAP_ADDR_BASE_IDX 0 +#define regGRBM_TRAP_ADDR_MSK 0x0dbb +#define regGRBM_TRAP_ADDR_MSK_BASE_IDX 0 +#define regGRBM_TRAP_WD 0x0dbc +#define regGRBM_TRAP_WD_BASE_IDX 0 +#define regGRBM_TRAP_WD_MSK 0x0dbd +#define regGRBM_TRAP_WD_MSK_BASE_IDX 0 +#define regGRBM_DSM_BYPASS 0x0dbe +#define regGRBM_DSM_BYPASS_BASE_IDX 0 +#define regGRBM_WRITE_ERROR 0x0dbf +#define regGRBM_WRITE_ERROR_BASE_IDX 0 +#define regGRBM_CHIP_REVISION 0x0dc1 +#define regGRBM_CHIP_REVISION_BASE_IDX 0 +#define regGRBM_IH_CREDIT 0x0dc4 +#define regGRBM_IH_CREDIT_BASE_IDX 0 +#define regGRBM_PWR_CNTL2 0x0dc5 +#define regGRBM_PWR_CNTL2_BASE_IDX 0 +#define regGRBM_UTCL2_INVAL_RANGE_START 0x0dc6 +#define regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0 +#define regGRBM_UTCL2_INVAL_RANGE_END 0x0dc7 +#define regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0 +#define regGRBM_INVALID_PIPE 0x0dc9 +#define regGRBM_INVALID_PIPE_BASE_IDX 0 +#define regGRBM_FENCE_RANGE0 0x0dca +#define regGRBM_FENCE_RANGE0_BASE_IDX 0 +#define regGRBM_FENCE_RANGE1 0x0dcb +#define regGRBM_FENCE_RANGE1_BASE_IDX 0 +#define regGRBM_SCRATCH_REG0 0x0de0 +#define regGRBM_SCRATCH_REG0_BASE_IDX 0 +#define regGRBM_SCRATCH_REG1 0x0de1 +#define regGRBM_SCRATCH_REG1_BASE_IDX 0 +#define regGRBM_SCRATCH_REG2 0x0de2 +#define regGRBM_SCRATCH_REG2_BASE_IDX 0 +#define regGRBM_SCRATCH_REG3 0x0de3 +#define regGRBM_SCRATCH_REG3_BASE_IDX 0 +#define regGRBM_SCRATCH_REG4 0x0de4 +#define regGRBM_SCRATCH_REG4_BASE_IDX 0 +#define regGRBM_SCRATCH_REG5 0x0de5 +#define regGRBM_SCRATCH_REG5_BASE_IDX 0 +#define regGRBM_SCRATCH_REG6 0x0de6 +#define regGRBM_SCRATCH_REG6_BASE_IDX 0 +#define regGRBM_SCRATCH_REG7 0x0de7 +#define regGRBM_SCRATCH_REG7_BASE_IDX 0 +#define regVIOLATION_DATA_ASYNC_VF_PROG 0x0df1 +#define regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX 0 + + +// addressBlock: gc_cpdec +// base address: 0x8200 +#define regCP_CPC_DEBUG_CNTL 0x0e20 +#define regCP_CPC_DEBUG_CNTL_BASE_IDX 0 +#define regCP_CPC_DEBUG_DATA 0x0e21 +#define regCP_CPC_DEBUG_DATA_BASE_IDX 0 +#define regCP_CPC_STATUS 0x0e24 +#define regCP_CPC_STATUS_BASE_IDX 0 +#define regCP_CPC_BUSY_STAT 0x0e25 +#define regCP_CPC_BUSY_STAT_BASE_IDX 0 +#define regCP_CPC_STALLED_STAT1 0x0e26 +#define regCP_CPC_STALLED_STAT1_BASE_IDX 0 +#define regCP_CPF_STATUS 0x0e27 +#define regCP_CPF_STATUS_BASE_IDX 0 +#define regCP_CPF_BUSY_STAT 0x0e28 +#define regCP_CPF_BUSY_STAT_BASE_IDX 0 +#define regCP_CPF_STALLED_STAT1 0x0e29 +#define regCP_CPF_STALLED_STAT1_BASE_IDX 0 +#define regCP_CPC_BUSY_STAT2 0x0e2a +#define regCP_CPC_BUSY_STAT2_BASE_IDX 0 +#define regCP_CPC_GRBM_FREE_COUNT 0x0e2b +#define regCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0 +#define regCP_CPC_PRIV_VIOLATION_ADDR 0x0e2c +#define regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX 0 +#define regCP_MEC_ME1_HEADER_DUMP 0x0e2e +#define regCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0 +#define regCP_MEC_ME2_HEADER_DUMP 0x0e2f +#define regCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0 +#define regCP_CPC_SCRATCH_INDEX 0x0e30 +#define regCP_CPC_SCRATCH_INDEX_BASE_IDX 0 +#define regCP_CPC_SCRATCH_DATA 0x0e31 +#define regCP_CPC_SCRATCH_DATA_BASE_IDX 0 +#define regCP_CPF_GRBM_FREE_COUNT 0x0e32 +#define regCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0 +#define regCP_CPF_BUSY_STAT2 0x0e33 +#define regCP_CPF_BUSY_STAT2_BASE_IDX 0 +#define regCP_CPC_HALT_HYST_COUNT 0x0e47 +#define regCP_CPC_HALT_HYST_COUNT_BASE_IDX 0 +#define regCP_STALLED_STAT3 0x0f3c +#define regCP_STALLED_STAT3_BASE_IDX 0 +#define regCP_STALLED_STAT1 0x0f3d +#define regCP_STALLED_STAT1_BASE_IDX 0 +#define regCP_STALLED_STAT2 0x0f3e +#define regCP_STALLED_STAT2_BASE_IDX 0 +#define regCP_BUSY_STAT 0x0f3f +#define regCP_BUSY_STAT_BASE_IDX 0 +#define regCP_STAT 0x0f40 +#define regCP_STAT_BASE_IDX 0 +#define regCP_ME_HEADER_DUMP 0x0f41 +#define regCP_ME_HEADER_DUMP_BASE_IDX 0 +#define regCP_PFP_HEADER_DUMP 0x0f42 +#define regCP_PFP_HEADER_DUMP_BASE_IDX 0 +#define regCP_GRBM_FREE_COUNT 0x0f43 +#define regCP_GRBM_FREE_COUNT_BASE_IDX 0 +#define regCP_PFP_INSTR_PNTR 0x0f45 +#define regCP_PFP_INSTR_PNTR_BASE_IDX 0 +#define regCP_ME_INSTR_PNTR 0x0f46 +#define regCP_ME_INSTR_PNTR_BASE_IDX 0 +#define regCP_MEC1_INSTR_PNTR 0x0f48 +#define regCP_MEC1_INSTR_PNTR_BASE_IDX 0 +#define regCP_MEC2_INSTR_PNTR 0x0f49 +#define regCP_MEC2_INSTR_PNTR_BASE_IDX 0 +#define regCP_CSF_STAT 0x0f54 +#define regCP_CSF_STAT_BASE_IDX 0 +#define regCP_CNTX_STAT 0x0f58 +#define regCP_CNTX_STAT_BASE_IDX 0 +#define regCP_ME_PREEMPTION 0x0f59 +#define regCP_ME_PREEMPTION_BASE_IDX 0 +#define regCP_RB1_RPTR 0x0f5f +#define regCP_RB1_RPTR_BASE_IDX 0 +#define regCP_RB0_RPTR 0x0f60 +#define regCP_RB0_RPTR_BASE_IDX 0 +#define regCP_RB_RPTR 0x0f60 +#define regCP_RB_RPTR_BASE_IDX 0 +#define regCP_RB_WPTR_DELAY 0x0f61 +#define regCP_RB_WPTR_DELAY_BASE_IDX 0 +#define regCP_RB_WPTR_POLL_CNTL 0x0f62 +#define regCP_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regCP_ROQ1_THRESHOLDS 0x0f75 +#define regCP_ROQ1_THRESHOLDS_BASE_IDX 0 +#define regCP_ROQ2_THRESHOLDS 0x0f76 +#define regCP_ROQ2_THRESHOLDS_BASE_IDX 0 +#define regCP_STQ_THRESHOLDS 0x0f77 +#define regCP_STQ_THRESHOLDS_BASE_IDX 0 +#define regCP_MEQ_THRESHOLDS 0x0f79 +#define regCP_MEQ_THRESHOLDS_BASE_IDX 0 +#define regCP_ROQ_AVAIL 0x0f7a +#define regCP_ROQ_AVAIL_BASE_IDX 0 +#define regCP_STQ_AVAIL 0x0f7b +#define regCP_STQ_AVAIL_BASE_IDX 0 +#define regCP_ROQ2_AVAIL 0x0f7c +#define regCP_ROQ2_AVAIL_BASE_IDX 0 +#define regCP_MEQ_AVAIL 0x0f7d +#define regCP_MEQ_AVAIL_BASE_IDX 0 +#define regCP_CMD_INDEX 0x0f7e +#define regCP_CMD_INDEX_BASE_IDX 0 +#define regCP_CMD_DATA 0x0f7f +#define regCP_CMD_DATA_BASE_IDX 0 +#define regCP_ROQ_RB_STAT 0x0f80 +#define regCP_ROQ_RB_STAT_BASE_IDX 0 +#define regCP_ROQ_IB1_STAT 0x0f81 +#define regCP_ROQ_IB1_STAT_BASE_IDX 0 +#define regCP_ROQ_IB2_STAT 0x0f82 +#define regCP_ROQ_IB2_STAT_BASE_IDX 0 +#define regCP_STQ_STAT 0x0f83 +#define regCP_STQ_STAT_BASE_IDX 0 +#define regCP_STQ_WR_STAT 0x0f84 +#define regCP_STQ_WR_STAT_BASE_IDX 0 +#define regCP_MEQ_STAT 0x0f85 +#define regCP_MEQ_STAT_BASE_IDX 0 +#define regCP_ROQ3_THRESHOLDS 0x0f8c +#define regCP_ROQ3_THRESHOLDS_BASE_IDX 0 +#define regCP_ROQ_DB_STAT 0x0f8d +#define regCP_ROQ_DB_STAT_BASE_IDX 0 +#define regCP_DEBUG_CNTL 0x0f98 +#define regCP_DEBUG_CNTL_BASE_IDX 0 +#define regCP_DEBUG_DATA 0x0f99 +#define regCP_DEBUG_DATA_BASE_IDX 0 +#define regCP_PRIV_VIOLATION_ADDR 0x0f9a +#define regCP_PRIV_VIOLATION_ADDR_BASE_IDX 0 + + +// addressBlock: gc_padec +// base address: 0x8800 +#define regVGT_DMA_DATA_FIFO_DEPTH 0x0fcd +#define regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0 +#define regVGT_DMA_REQ_FIFO_DEPTH 0x0fce +#define regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0 +#define regVGT_DRAW_INIT_FIFO_DEPTH 0x0fcf +#define regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0 +#define regVGT_MC_LAT_CNTL 0x0fd6 +#define regVGT_MC_LAT_CNTL_BASE_IDX 0 +#define regIA_UTCL1_STATUS_2 0x0fd7 +#define regIA_UTCL1_STATUS_2_BASE_IDX 0 +#define regWD_CNTL_STATUS 0x0fdf +#define regWD_CNTL_STATUS_BASE_IDX 0 +#define regCC_GC_PRIM_CONFIG 0x0fe0 +#define regCC_GC_PRIM_CONFIG_BASE_IDX 0 +#define regWD_QOS 0x0fe2 +#define regWD_QOS_BASE_IDX 0 +#define regWD_UTCL1_CNTL 0x0fe3 +#define regWD_UTCL1_CNTL_BASE_IDX 0 +#define regWD_UTCL1_STATUS 0x0fe4 +#define regWD_UTCL1_STATUS_BASE_IDX 0 +#define regIA_UTCL1_CNTL 0x0fe6 +#define regIA_UTCL1_CNTL_BASE_IDX 0 +#define regIA_UTCL1_STATUS 0x0fe7 +#define regIA_UTCL1_STATUS_BASE_IDX 0 +#define regCC_GC_SA_UNIT_DISABLE 0x0fe9 +#define regCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 +#define regGE_RATE_CNTL_1 0x0ff4 +#define regGE_RATE_CNTL_1_BASE_IDX 0 +#define regGE_RATE_CNTL_2 0x0ff5 +#define regGE_RATE_CNTL_2_BASE_IDX 0 +#define regVGT_SYS_CONFIG 0x1003 +#define regVGT_SYS_CONFIG_BASE_IDX 0 +#define regGE_PRIV_CONTROL 0x1004 +#define regGE_PRIV_CONTROL_BASE_IDX 0 +#define regGE_STATUS 0x1005 +#define regGE_STATUS_BASE_IDX 0 +#define regVGT_GS_MAX_WAVE_ID 0x1009 +#define regVGT_GS_MAX_WAVE_ID_BASE_IDX 0 +#define regGFX_PIPE_CONTROL 0x100d +#define regGFX_PIPE_CONTROL_BASE_IDX 0 +#define regCC_GC_SHADER_ARRAY_CONFIG 0x100f +#define regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0 +#define regGE2_SE_CNTL_STATUS 0x1011 +#define regGE2_SE_CNTL_STATUS_BASE_IDX 0 +#define regGE_SPI_IF_SAFE_REG 0x1018 +#define regGE_SPI_IF_SAFE_REG_BASE_IDX 0 +#define regGE_PA_IF_SAFE_REG 0x1019 +#define regGE_PA_IF_SAFE_REG_BASE_IDX 0 +#define regPA_CL_CNTL_STATUS 0x1024 +#define regPA_CL_CNTL_STATUS_BASE_IDX 0 +#define regPA_CL_ENHANCE 0x1025 +#define regPA_CL_ENHANCE_BASE_IDX 0 +#define regPA_SU_CNTL_STATUS 0x1034 +#define regPA_SU_CNTL_STATUS_BASE_IDX 0 +#define regPA_SC_FIFO_DEPTH_CNTL 0x1035 +#define regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0 + + +// addressBlock: gc_sqdec +// base address: 0x8c00 +#define regSQ_CONFIG 0x10a0 +#define regSQ_CONFIG_BASE_IDX 0 +#define regSQC_CONFIG 0x10a1 +#define regSQC_CONFIG_BASE_IDX 0 +#define regLDS_CONFIG 0x10a2 +#define regLDS_CONFIG_BASE_IDX 0 +#define regSQ_RANDOM_WAVE_PRI 0x10a3 +#define regSQ_RANDOM_WAVE_PRI_BASE_IDX 0 +#define regSQG_STATUS 0x10a4 +#define regSQG_STATUS_BASE_IDX 0 +#define regSQ_FIFO_SIZES 0x10a5 +#define regSQ_FIFO_SIZES_BASE_IDX 0 +#define regSQ_DSM_CNTL 0x10a6 +#define regSQ_DSM_CNTL_BASE_IDX 0 +#define regSQ_DSM_CNTL2 0x10a7 +#define regSQ_DSM_CNTL2_BASE_IDX 0 +#define regSP_CONFIG 0x10ab +#define regSP_CONFIG_BASE_IDX 0 +#define regSQ_ARB_CONFIG 0x10ac +#define regSQ_ARB_CONFIG_BASE_IDX 0 +#define regSQ_DEBUG_HOST_TRAP_STATUS 0x10b6 +#define regSQ_DEBUG_HOST_TRAP_STATUS_BASE_IDX 0 +#define regSQG_GL1H_STATUS 0x10b9 +#define regSQG_GL1H_STATUS_BASE_IDX 0 +#define regSQG_CONFIG 0x10ba +#define regSQG_CONFIG_BASE_IDX 0 +#define regSQ_PERF_SNAPSHOT_CTRL 0x10bb +#define regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX 0 +#define regCC_GC_SHADER_RATE_CONFIG 0x10bc +#define regCC_GC_SHADER_RATE_CONFIG_BASE_IDX 0 +#define regSQ_INTERRUPT_AUTO_MASK 0x10be +#define regSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0 +#define regSQ_INTERRUPT_MSG_CTRL 0x10bf +#define regSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0 +#define regSQ_WATCH0_ADDR_H 0x10d0 +#define regSQ_WATCH0_ADDR_H_BASE_IDX 0 +#define regSQ_WATCH0_ADDR_L 0x10d1 +#define regSQ_WATCH0_ADDR_L_BASE_IDX 0 +#define regSQ_WATCH0_CNTL 0x10d2 +#define regSQ_WATCH0_CNTL_BASE_IDX 0 +#define regSQ_WATCH1_ADDR_H 0x10d3 +#define regSQ_WATCH1_ADDR_H_BASE_IDX 0 +#define regSQ_WATCH1_ADDR_L 0x10d4 +#define regSQ_WATCH1_ADDR_L_BASE_IDX 0 +#define regSQ_WATCH1_CNTL 0x10d5 +#define regSQ_WATCH1_CNTL_BASE_IDX 0 +#define regSQ_WATCH2_ADDR_H 0x10d6 +#define regSQ_WATCH2_ADDR_H_BASE_IDX 0 +#define regSQ_WATCH2_ADDR_L 0x10d7 +#define regSQ_WATCH2_ADDR_L_BASE_IDX 0 +#define regSQ_WATCH2_CNTL 0x10d8 +#define regSQ_WATCH2_CNTL_BASE_IDX 0 +#define regSQ_WATCH3_ADDR_H 0x10d9 +#define regSQ_WATCH3_ADDR_H_BASE_IDX 0 +#define regSQ_WATCH3_ADDR_L 0x10da +#define regSQ_WATCH3_ADDR_L_BASE_IDX 0 +#define regSQ_WATCH3_CNTL 0x10db +#define regSQ_WATCH3_CNTL_BASE_IDX 0 +#define regSQ_IND_INDEX 0x1118 +#define regSQ_IND_INDEX_BASE_IDX 0 +#define regSQ_IND_DATA 0x1119 +#define regSQ_IND_DATA_BASE_IDX 0 +#define regSQ_CMD 0x111b +#define regSQ_CMD_BASE_IDX 0 + + +// addressBlock: gc_shsdec +// base address: 0x9000 +#define regSX_DEBUG_1 0x11b8 +#define regSX_DEBUG_1_BASE_IDX 0 +#define regSPI_PS_MAX_WAVE_ID 0x11da +#define regSPI_PS_MAX_WAVE_ID_BASE_IDX 0 +#define regSPI_GFX_CNTL 0x11dc +#define regSPI_GFX_CNTL_BASE_IDX 0 +#define regSPI_DSM_CNTL 0x11e3 +#define regSPI_DSM_CNTL_BASE_IDX 0 +#define regSPI_DSM_CNTL2 0x11e4 +#define regSPI_DSM_CNTL2_BASE_IDX 0 +#define regSPI_EDC_CNT 0x11e5 +#define regSPI_EDC_CNT_BASE_IDX 0 +#define regSPI_CONFIG_PS_CU_EN 0x11f2 +#define regSPI_CONFIG_PS_CU_EN_BASE_IDX 0 +#define regSPI_WF_LIFETIME_CNTL 0x124a +#define regSPI_WF_LIFETIME_CNTL_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_0 0x124b +#define regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_1 0x124c +#define regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_2 0x124d +#define regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_3 0x124e +#define regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_4 0x124f +#define regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_5 0x1250 +#define regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_0 0x1255 +#define regSPI_WF_LIFETIME_STATUS_0_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_2 0x1257 +#define regSPI_WF_LIFETIME_STATUS_2_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_4 0x1259 +#define regSPI_WF_LIFETIME_STATUS_4_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_6 0x125b +#define regSPI_WF_LIFETIME_STATUS_6_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_7 0x125c +#define regSPI_WF_LIFETIME_STATUS_7_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_9 0x125e +#define regSPI_WF_LIFETIME_STATUS_9_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_11 0x1260 +#define regSPI_WF_LIFETIME_STATUS_11_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_13 0x1262 +#define regSPI_WF_LIFETIME_STATUS_13_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_14 0x1263 +#define regSPI_WF_LIFETIME_STATUS_14_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_15 0x1264 +#define regSPI_WF_LIFETIME_STATUS_15_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_16 0x1265 +#define regSPI_WF_LIFETIME_STATUS_16_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_17 0x1266 +#define regSPI_WF_LIFETIME_STATUS_17_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_18 0x1267 +#define regSPI_WF_LIFETIME_STATUS_18_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_19 0x1268 +#define regSPI_WF_LIFETIME_STATUS_19_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_20 0x1269 +#define regSPI_WF_LIFETIME_STATUS_20_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_21 0x126b +#define regSPI_WF_LIFETIME_STATUS_21_BASE_IDX 0 +#define regSPI_LB_CTR_CTRL 0x1274 +#define regSPI_LB_CTR_CTRL_BASE_IDX 0 +#define regSPI_LB_WGP_MASK 0x1275 +#define regSPI_LB_WGP_MASK_BASE_IDX 0 +#define regSPI_LB_DATA_REG 0x1276 +#define regSPI_LB_DATA_REG_BASE_IDX 0 +#define regSPI_PG_ENABLE_STATIC_WGP_MASK 0x1277 +#define regSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX 0 +#define regSPI_GDS_CREDITS 0x1278 +#define regSPI_GDS_CREDITS_BASE_IDX 0 +#define regSPI_SX_EXPORT_BUFFER_SIZES 0x1279 +#define regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX 0 +#define regSPI_SX_SCOREBOARD_BUFFER_SIZES 0x127a +#define regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_STATUS 0x127b +#define regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_0 0x127c +#define regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_1 0x127d +#define regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_2 0x127e +#define regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_3 0x127f +#define regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX 0 +#define regSPI_LB_DATA_WAVES 0x1284 +#define regSPI_LB_DATA_WAVES_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSBA_LO 0x128c +#define regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSBA_HI 0x128d +#define regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSMA_LO 0x128e +#define regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSMA_HI 0x128f +#define regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_GPR_MIN 0x1290 +#define regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSBA_LO 0x1291 +#define regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSBA_HI 0x1292 +#define regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSMA_LO 0x1293 +#define regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSMA_HI 0x1294 +#define regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_GPR_MIN 0x1295 +#define regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 + + +// addressBlock: gc_tpdec +// base address: 0x9400 +#define regTD_STATUS 0x12c6 +#define regTD_STATUS_BASE_IDX 0 +#define regTD_DSM_CNTL 0x12cf +#define regTD_DSM_CNTL_BASE_IDX 0 +#define regTD_DSM_CNTL2 0x12d0 +#define regTD_DSM_CNTL2_BASE_IDX 0 +#define regTD_SCRATCH 0x12d3 +#define regTD_SCRATCH_BASE_IDX 0 +#define regTA_CNTL 0x12e1 +#define regTA_CNTL_BASE_IDX 0 +#define regTA_CNTL_AUX 0x12e2 +#define regTA_CNTL_AUX_BASE_IDX 0 +#define regTA_CNTL2 0x12e5 +#define regTA_CNTL2_BASE_IDX 0 +#define regTA_STATUS 0x12e8 +#define regTA_STATUS_BASE_IDX 0 +#define regTA_SCRATCH 0x1304 +#define regTA_SCRATCH_BASE_IDX 0 + + +// addressBlock: gc_gdsdec +// base address: 0x9700 +#define regGDS_CONFIG 0x1360 +#define regGDS_CONFIG_BASE_IDX 0 +#define regGDS_CNTL_STATUS 0x1361 +#define regGDS_CNTL_STATUS_BASE_IDX 0 +#define regGDS_ENHANCE 0x1362 +#define regGDS_ENHANCE_BASE_IDX 0 +#define regGDS_PROTECTION_FAULT 0x1363 +#define regGDS_PROTECTION_FAULT_BASE_IDX 0 +#define regGDS_VM_PROTECTION_FAULT 0x1364 +#define regGDS_VM_PROTECTION_FAULT_BASE_IDX 0 +#define regGDS_EDC_CNT 0x1365 +#define regGDS_EDC_CNT_BASE_IDX 0 +#define regGDS_EDC_GRBM_CNT 0x1366 +#define regGDS_EDC_GRBM_CNT_BASE_IDX 0 +#define regGDS_EDC_OA_DED 0x1367 +#define regGDS_EDC_OA_DED_BASE_IDX 0 +#define regGDS_DSM_CNTL 0x136a +#define regGDS_DSM_CNTL_BASE_IDX 0 +#define regGDS_EDC_OA_PHY_CNT 0x136b +#define regGDS_EDC_OA_PHY_CNT_BASE_IDX 0 +#define regGDS_EDC_OA_PIPE_CNT 0x136c +#define regGDS_EDC_OA_PIPE_CNT_BASE_IDX 0 +#define regGDS_DSM_CNTL2 0x136d +#define regGDS_DSM_CNTL2_BASE_IDX 0 + + +// addressBlock: gc_rbdec +// base address: 0x9800 +#define regDB_DEBUG 0x13ac +#define regDB_DEBUG_BASE_IDX 0 +#define regDB_DEBUG2 0x13ad +#define regDB_DEBUG2_BASE_IDX 0 +#define regDB_DEBUG3 0x13ae +#define regDB_DEBUG3_BASE_IDX 0 +#define regDB_DEBUG4 0x13af +#define regDB_DEBUG4_BASE_IDX 0 +#define regDB_ETILE_STUTTER_CONTROL 0x13b0 +#define regDB_ETILE_STUTTER_CONTROL_BASE_IDX 0 +#define regDB_LTILE_STUTTER_CONTROL 0x13b1 +#define regDB_LTILE_STUTTER_CONTROL_BASE_IDX 0 +#define regDB_EQUAD_STUTTER_CONTROL 0x13b2 +#define regDB_EQUAD_STUTTER_CONTROL_BASE_IDX 0 +#define regDB_LQUAD_STUTTER_CONTROL 0x13b3 +#define regDB_LQUAD_STUTTER_CONTROL_BASE_IDX 0 +#define regDB_CREDIT_LIMIT 0x13b4 +#define regDB_CREDIT_LIMIT_BASE_IDX 0 +#define regDB_WATERMARKS 0x13b5 +#define regDB_WATERMARKS_BASE_IDX 0 +#define regDB_SUBTILE_CONTROL 0x13b6 +#define regDB_SUBTILE_CONTROL_BASE_IDX 0 +#define regDB_FREE_CACHELINES 0x13b7 +#define regDB_FREE_CACHELINES_BASE_IDX 0 +#define regDB_FIFO_DEPTH1 0x13b8 +#define regDB_FIFO_DEPTH1_BASE_IDX 0 +#define regDB_FIFO_DEPTH2 0x13b9 +#define regDB_FIFO_DEPTH2_BASE_IDX 0 +#define regDB_LAST_OF_BURST_CONFIG 0x13ba +#define regDB_LAST_OF_BURST_CONFIG_BASE_IDX 0 +#define regDB_RING_CONTROL 0x13bb +#define regDB_RING_CONTROL_BASE_IDX 0 +#define regDB_MEM_ARB_WATERMARKS 0x13bc +#define regDB_MEM_ARB_WATERMARKS_BASE_IDX 0 +#define regDB_FIFO_DEPTH3 0x13bd +#define regDB_FIFO_DEPTH3_BASE_IDX 0 +#define regDB_DEBUG6 0x13be +#define regDB_DEBUG6_BASE_IDX 0 +#define regDB_EXCEPTION_CONTROL 0x13bf +#define regDB_EXCEPTION_CONTROL_BASE_IDX 0 +#define regDB_DEBUG7 0x13d0 +#define regDB_DEBUG7_BASE_IDX 0 +#define regDB_DEBUG5 0x13d1 +#define regDB_DEBUG5_BASE_IDX 0 +#define regDB_FGCG_SRAMS_CLK_CTRL 0x13d7 +#define regDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX 0 +#define regDB_FGCG_INTERFACES_CLK_CTRL 0x13d8 +#define regDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX 0 +#define regDB_FIFO_DEPTH4 0x13d9 +#define regDB_FIFO_DEPTH4_BASE_IDX 0 +#define regCC_RB_REDUNDANCY 0x13dc +#define regCC_RB_REDUNDANCY_BASE_IDX 0 +#define regCC_RB_BACKEND_DISABLE 0x13dd +#define regCC_RB_BACKEND_DISABLE_BASE_IDX 0 +#define regGB_ADDR_CONFIG 0x13de +#define regGB_ADDR_CONFIG_BASE_IDX 0 +#define regGB_BACKEND_MAP 0x13df +#define regGB_BACKEND_MAP_BASE_IDX 0 +#define regGB_GPU_ID 0x13e0 +#define regGB_GPU_ID_BASE_IDX 0 +#define regCC_RB_DAISY_CHAIN 0x13e1 +#define regCC_RB_DAISY_CHAIN_BASE_IDX 0 +#define regGB_ADDR_CONFIG_READ 0x13e2 +#define regGB_ADDR_CONFIG_READ_BASE_IDX 0 +#define regCB_HW_CONTROL_4 0x1422 +#define regCB_HW_CONTROL_4_BASE_IDX 0 +#define regCB_HW_CONTROL_3 0x1423 +#define regCB_HW_CONTROL_3_BASE_IDX 0 +#define regCB_HW_CONTROL 0x1424 +#define regCB_HW_CONTROL_BASE_IDX 0 +#define regCB_HW_CONTROL_1 0x1425 +#define regCB_HW_CONTROL_1_BASE_IDX 0 +#define regCB_HW_CONTROL_2 0x1426 +#define regCB_HW_CONTROL_2_BASE_IDX 0 +#define regCB_DCC_CONFIG 0x1427 +#define regCB_DCC_CONFIG_BASE_IDX 0 +#define regCB_HW_MEM_ARBITER_RD 0x1428 +#define regCB_HW_MEM_ARBITER_RD_BASE_IDX 0 +#define regCB_HW_MEM_ARBITER_WR 0x1429 +#define regCB_HW_MEM_ARBITER_WR_BASE_IDX 0 +#define regCB_FGCG_SRAM_OVERRIDE 0x142a +#define regCB_FGCG_SRAM_OVERRIDE_BASE_IDX 0 +#define regCB_DCC_CONFIG2 0x142b +#define regCB_DCC_CONFIG2_BASE_IDX 0 +#define regCHICKEN_BITS 0x142d +#define regCHICKEN_BITS_BASE_IDX 0 +#define regCB_CACHE_EVICT_POINTS 0x142e +#define regCB_CACHE_EVICT_POINTS_BASE_IDX 0 + + +// addressBlock: gc_gceadec +// base address: 0xa800 +#define regGCEA_DRAM_RD_CLI2GRP_MAP0 0x17a0 +#define regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regGCEA_DRAM_RD_CLI2GRP_MAP1 0x17a1 +#define regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regGCEA_DRAM_WR_CLI2GRP_MAP0 0x17a2 +#define regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regGCEA_DRAM_WR_CLI2GRP_MAP1 0x17a3 +#define regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regGCEA_DRAM_RD_GRP2VC_MAP 0x17a4 +#define regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 +#define regGCEA_DRAM_WR_GRP2VC_MAP 0x17a5 +#define regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 +#define regGCEA_DRAM_RD_LAZY 0x17a6 +#define regGCEA_DRAM_RD_LAZY_BASE_IDX 0 +#define regGCEA_DRAM_WR_LAZY 0x17a7 +#define regGCEA_DRAM_WR_LAZY_BASE_IDX 0 +#define regGCEA_DRAM_RD_CAM_CNTL 0x17a8 +#define regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX 0 +#define regGCEA_DRAM_WR_CAM_CNTL 0x17a9 +#define regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX 0 +#define regGCEA_DRAM_PAGE_BURST 0x17aa +#define regGCEA_DRAM_PAGE_BURST_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_AGE 0x17ab +#define regGCEA_DRAM_RD_PRI_AGE_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_AGE 0x17ac +#define regGCEA_DRAM_WR_PRI_AGE_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_QUEUING 0x17ad +#define regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_QUEUING 0x17ae +#define regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_FIXED 0x17af +#define regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_FIXED 0x17b0 +#define regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_URGENCY 0x17b1 +#define regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_URGENCY 0x17b2 +#define regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI1 0x17b3 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI2 0x17b4 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI3 0x17b5 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI1 0x17b6 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI2 0x17b7 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI3 0x17b8 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regGCEA_IO_RD_CLI2GRP_MAP0 0x187d +#define regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regGCEA_IO_RD_CLI2GRP_MAP1 0x187e +#define regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regGCEA_IO_WR_CLI2GRP_MAP0 0x187f +#define regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regGCEA_IO_WR_CLI2GRP_MAP1 0x1880 +#define regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regGCEA_IO_RD_COMBINE_FLUSH 0x1881 +#define regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX 0 +#define regGCEA_IO_WR_COMBINE_FLUSH 0x1882 +#define regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX 0 +#define regGCEA_IO_GROUP_BURST 0x1883 +#define regGCEA_IO_GROUP_BURST_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_AGE 0x1884 +#define regGCEA_IO_RD_PRI_AGE_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_AGE 0x1885 +#define regGCEA_IO_WR_PRI_AGE_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_QUEUING 0x1886 +#define regGCEA_IO_RD_PRI_QUEUING_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_QUEUING 0x1887 +#define regGCEA_IO_WR_PRI_QUEUING_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_FIXED 0x1888 +#define regGCEA_IO_RD_PRI_FIXED_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_FIXED 0x1889 +#define regGCEA_IO_WR_PRI_FIXED_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_URGENCY 0x188a +#define regGCEA_IO_RD_PRI_URGENCY_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_URGENCY 0x188b +#define regGCEA_IO_WR_PRI_URGENCY_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_URGENCY_MASKING 0x188c +#define regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_URGENCY_MASKING 0x188d +#define regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_QUANT_PRI1 0x188e +#define regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_QUANT_PRI2 0x188f +#define regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_QUANT_PRI3 0x1890 +#define regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_QUANT_PRI1 0x1891 +#define regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_QUANT_PRI2 0x1892 +#define regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_QUANT_PRI3 0x1893 +#define regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regGCEA_SDP_ARB_FINAL 0x1896 +#define regGCEA_SDP_ARB_FINAL_BASE_IDX 0 +#define regGCEA_SDP_IO_PRIORITY 0x1899 +#define regGCEA_SDP_IO_PRIORITY_BASE_IDX 0 +#define regGCEA_SDP_CREDITS 0x189a +#define regGCEA_SDP_CREDITS_BASE_IDX 0 +#define regGCEA_SDP_TAG_RESERVE0 0x189b +#define regGCEA_SDP_TAG_RESERVE0_BASE_IDX 0 +#define regGCEA_SDP_TAG_RESERVE1 0x189c +#define regGCEA_SDP_TAG_RESERVE1_BASE_IDX 0 +#define regGCEA_SDP_VCC_RESERVE0 0x189d +#define regGCEA_SDP_VCC_RESERVE0_BASE_IDX 0 +#define regGCEA_SDP_VCC_RESERVE1 0x189e +#define regGCEA_SDP_VCC_RESERVE1_BASE_IDX 0 + + +// addressBlock: gc_gceadec2 +// base address: 0x9c00 +#define regGCEA_MISC 0x14a2 +#define regGCEA_MISC_BASE_IDX 0 +#define regGCEA_LATENCY_SAMPLING 0x14a3 +#define regGCEA_LATENCY_SAMPLING_BASE_IDX 0 +#define regGCEA_MAM_CTRL2 0x14a9 +#define regGCEA_MAM_CTRL2_BASE_IDX 0 +#define regGCEA_MAM_CTRL 0x14ab +#define regGCEA_MAM_CTRL_BASE_IDX 0 +#define regGCEA_EDC_CNT 0x14b2 +#define regGCEA_EDC_CNT_BASE_IDX 0 +#define regGCEA_EDC_CNT2 0x14b3 +#define regGCEA_EDC_CNT2_BASE_IDX 0 +#define regGCEA_DSM_CNTL 0x14b4 +#define regGCEA_DSM_CNTL_BASE_IDX 0 +#define regGCEA_DSM_CNTLA 0x14b5 +#define regGCEA_DSM_CNTLA_BASE_IDX 0 +#define regGCEA_DSM_CNTLB 0x14b6 +#define regGCEA_DSM_CNTLB_BASE_IDX 0 +#define regGCEA_DSM_CNTL2 0x14b7 +#define regGCEA_DSM_CNTL2_BASE_IDX 0 +#define regGCEA_DSM_CNTL2A 0x14b8 +#define regGCEA_DSM_CNTL2A_BASE_IDX 0 +#define regGCEA_DSM_CNTL2B 0x14b9 +#define regGCEA_DSM_CNTL2B_BASE_IDX 0 +#define regGCEA_GL2C_XBR_CREDITS 0x14ba +#define regGCEA_GL2C_XBR_CREDITS_BASE_IDX 0 +#define regGCEA_GL2C_XBR_MAXBURST 0x14bb +#define regGCEA_GL2C_XBR_MAXBURST_BASE_IDX 0 +#define regGCEA_PROBE_CNTL 0x14bc +#define regGCEA_PROBE_CNTL_BASE_IDX 0 +#define regGCEA_PROBE_MAP 0x14bd +#define regGCEA_PROBE_MAP_BASE_IDX 0 +#define regGCEA_ERR_STATUS 0x14be +#define regGCEA_ERR_STATUS_BASE_IDX 0 +#define regGCEA_MISC2 0x14bf +#define regGCEA_MISC2_BASE_IDX 0 + + +// addressBlock: gc_gceadec3 +// base address: 0x9dc0 +#define regGCEA_RRET_MEM_RESERVE 0x1518 +#define regGCEA_RRET_MEM_RESERVE_BASE_IDX 0 +#define regGCEA_EDC_CNT3 0x151a +#define regGCEA_EDC_CNT3_BASE_IDX 0 +#define regGCEA_SDP_ENABLE 0x151e +#define regGCEA_SDP_ENABLE_BASE_IDX 0 + + +// addressBlock: gc_spipdec2 +// base address: 0x9c80 +#define regSPI_PQEV_CTRL 0x14c0 +#define regSPI_PQEV_CTRL_BASE_IDX 0 +#define regSPI_EXP_THROTTLE_CTRL 0x14c3 +#define regSPI_EXP_THROTTLE_CTRL_BASE_IDX 0 + + +// addressBlock: gc_rmi_rmidec +// base address: 0x2e200 +#define regRMI_GENERAL_CNTL 0x1880 +#define regRMI_GENERAL_CNTL_BASE_IDX 1 +#define regRMI_GENERAL_CNTL1 0x1881 +#define regRMI_GENERAL_CNTL1_BASE_IDX 1 +#define regRMI_GENERAL_STATUS 0x1882 +#define regRMI_GENERAL_STATUS_BASE_IDX 1 +#define regRMI_SUBBLOCK_STATUS0 0x1883 +#define regRMI_SUBBLOCK_STATUS0_BASE_IDX 1 +#define regRMI_SUBBLOCK_STATUS1 0x1884 +#define regRMI_SUBBLOCK_STATUS1_BASE_IDX 1 +#define regRMI_SUBBLOCK_STATUS2 0x1885 +#define regRMI_SUBBLOCK_STATUS2_BASE_IDX 1 +#define regRMI_SUBBLOCK_STATUS3 0x1886 +#define regRMI_SUBBLOCK_STATUS3_BASE_IDX 1 +#define regRMI_XBAR_CONFIG 0x1887 +#define regRMI_XBAR_CONFIG_BASE_IDX 1 +#define regRMI_PROBE_POP_LOGIC_CNTL 0x1888 +#define regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX 1 +#define regRMI_UTC_XNACK_N_MISC_CNTL 0x1889 +#define regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX 1 +#define regRMI_DEMUX_CNTL 0x188a +#define regRMI_DEMUX_CNTL_BASE_IDX 1 +#define regRMI_UTCL1_CNTL1 0x188b +#define regRMI_UTCL1_CNTL1_BASE_IDX 1 +#define regRMI_UTCL1_CNTL2 0x188c +#define regRMI_UTCL1_CNTL2_BASE_IDX 1 +#define regRMI_UTC_UNIT_CONFIG 0x188d +#define regRMI_UTC_UNIT_CONFIG_BASE_IDX 1 +#define regRMI_TCIW_FORMATTER0_CNTL 0x188e +#define regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX 1 +#define regRMI_TCIW_FORMATTER1_CNTL 0x188f +#define regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX 1 +#define regRMI_SCOREBOARD_CNTL 0x1890 +#define regRMI_SCOREBOARD_CNTL_BASE_IDX 1 +#define regRMI_SCOREBOARD_STATUS0 0x1891 +#define regRMI_SCOREBOARD_STATUS0_BASE_IDX 1 +#define regRMI_SCOREBOARD_STATUS1 0x1892 +#define regRMI_SCOREBOARD_STATUS1_BASE_IDX 1 +#define regRMI_SCOREBOARD_STATUS2 0x1893 +#define regRMI_SCOREBOARD_STATUS2_BASE_IDX 1 +#define regRMI_XBAR_ARBITER_CONFIG 0x1894 +#define regRMI_XBAR_ARBITER_CONFIG_BASE_IDX 1 +#define regRMI_XBAR_ARBITER_CONFIG_1 0x1895 +#define regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX 1 +#define regRMI_CLOCK_CNTRL 0x1896 +#define regRMI_CLOCK_CNTRL_BASE_IDX 1 +#define regRMI_UTCL1_STATUS 0x1897 +#define regRMI_UTCL1_STATUS_BASE_IDX 1 +#define regRMI_RB_GLX_CID_MAP 0x1898 +#define regRMI_RB_GLX_CID_MAP_BASE_IDX 1 +#define regRMI_SPARE 0x189f +#define regRMI_SPARE_BASE_IDX 1 +#define regRMI_SPARE_1 0x18a0 +#define regRMI_SPARE_1_BASE_IDX 1 +#define regRMI_SPARE_2 0x18a1 +#define regRMI_SPARE_2_BASE_IDX 1 +#define regCC_RMI_REDUNDANCY 0x18a2 +#define regCC_RMI_REDUNDANCY_BASE_IDX 1 + + +// addressBlock: gc_pmmdec +// base address: 0x9f80 +#define regGCR_PIO_CNTL 0x1580 +#define regGCR_PIO_CNTL_BASE_IDX 0 +#define regGCR_PIO_DATA 0x1581 +#define regGCR_PIO_DATA_BASE_IDX 0 +#define regPMM_CNTL 0x1582 +#define regPMM_CNTL_BASE_IDX 0 +#define regPMM_STATUS 0x1583 +#define regPMM_STATUS_BASE_IDX 0 + + +// addressBlock: gc_utcl1dec +// base address: 0x9fb0 +#define regUTCL1_CTRL_1 0x158c +#define regUTCL1_CTRL_1_BASE_IDX 0 +#define regUTCL1_ALOG 0x158f +#define regUTCL1_ALOG_BASE_IDX 0 +#define regUTCL1_STATUS 0x1594 +#define regUTCL1_STATUS_BASE_IDX 0 + + +// addressBlock: gc_gcvmsharedpfdec +// base address: 0xa000 +#define regGCMC_VM_NB_TOP_OF_DRAM_SLOT1 0x15a4 +#define regGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 +#define regGCMC_VM_NB_LOWER_TOP_OF_DRAM2 0x15a5 +#define regGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 +#define regGCMC_VM_NB_UPPER_TOP_OF_DRAM2 0x15a6 +#define regGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 +#define regGCMC_VM_FB_OFFSET 0x15a7 +#define regGCMC_VM_FB_OFFSET_BASE_IDX 0 +#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x15a8 +#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 +#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x15a9 +#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 +#define regGCMC_VM_STEERING 0x15aa +#define regGCMC_VM_STEERING_BASE_IDX 0 +#define regGCMC_MEM_POWER_LS 0x15ac +#define regGCMC_MEM_POWER_LS_BASE_IDX 0 +#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x15ad +#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 +#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x15ae +#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 +#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START 0x15af +#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX 0 +#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END 0x15b0 +#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX 0 +#define regGCMC_VM_APT_CNTL 0x15b1 +#define regGCMC_VM_APT_CNTL_BASE_IDX 0 +#define regGCMC_VM_LOCAL_FB_ADDRESS_START 0x15b2 +#define regGCMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX 0 +#define regGCMC_VM_LOCAL_FB_ADDRESS_END 0x15b3 +#define regGCMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX 0 +#define regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 0x15b4 +#define regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX 0 +#define regGCUTCL2_ICG_CTRL 0x15b5 +#define regGCUTCL2_ICG_CTRL_BASE_IDX 0 +#define regGCUTCL2_CGTT_BUSY_CTRL 0x15b7 +#define regGCUTCL2_CGTT_BUSY_CTRL_BASE_IDX 0 +#define regGCMC_VM_FB_NOALLOC_CNTL 0x15b8 +#define regGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX 0 +#define regGCUTCL2_HARVEST_BYPASS_GROUPS 0x15b9 +#define regGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 0 +#define regGCUTCL2_GROUP_RET_FAULT_STATUS 0x15bb +#define regGCUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX 0 + + +// addressBlock: gc_gcvml2pfdec +// base address: 0xa070 +#define regGCVM_L2_CNTL 0x15bc +#define regGCVM_L2_CNTL_BASE_IDX 0 +#define regGCVM_L2_CNTL2 0x15bd +#define regGCVM_L2_CNTL2_BASE_IDX 0 +#define regGCVM_L2_CNTL3 0x15be +#define regGCVM_L2_CNTL3_BASE_IDX 0 +#define regGCVM_L2_STATUS 0x15bf +#define regGCVM_L2_STATUS_BASE_IDX 0 +#define regGCVM_DUMMY_PAGE_FAULT_CNTL 0x15c0 +#define regGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 +#define regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x15c1 +#define regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 +#define regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x15c2 +#define regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_CNTL 0x15c3 +#define regGCVM_INVALIDATE_CNTL_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_CNTL 0x15c4 +#define regGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_CNTL2 0x15c5 +#define regGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL3 0x15c6 +#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL4 0x15c7 +#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_STATUS 0x15c8 +#define regGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_ADDR_LO32 0x15c9 +#define regGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_ADDR_HI32 0x15ca +#define regGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x15cb +#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x15cc +#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x15ce +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x15cf +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x15d0 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x15d1 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x15d2 +#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x15d3 +#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 +#define regGCVM_L2_CNTL4 0x15d4 +#define regGCVM_L2_CNTL4_BASE_IDX 0 +#define regGCVM_L2_MM_GROUP_RT_CLASSES 0x15d5 +#define regGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 +#define regGCVM_L2_BANK_SELECT_RESERVED_CID 0x15d6 +#define regGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 +#define regGCVM_L2_BANK_SELECT_RESERVED_CID2 0x15d7 +#define regGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 +#define regGCVM_L2_CACHE_PARITY_CNTL 0x15d8 +#define regGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 +#define regGCVM_L2_ICG_CTRL 0x15d9 +#define regGCVM_L2_ICG_CTRL_BASE_IDX 0 +#define regGCVM_L2_CNTL5 0x15da +#define regGCVM_L2_CNTL5_BASE_IDX 0 +#define regGCVM_L2_GCR_CNTL 0x15db +#define regGCVM_L2_GCR_CNTL_BASE_IDX 0 +#define regGCVML2_WALKER_MACRO_THROTTLE_TIME 0x15dc +#define regGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX 0 +#define regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT 0x15dd +#define regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0 +#define regGCVML2_WALKER_MICRO_THROTTLE_TIME 0x15de +#define regGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX 0 +#define regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT 0x15df +#define regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0 +#define regGCVM_L2_CGTT_BUSY_CTRL 0x15e0 +#define regGCVM_L2_CGTT_BUSY_CTRL_BASE_IDX 0 +#define regGCVM_L2_PTE_CACHE_DUMP_CNTL 0x15e1 +#define regGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 0 +#define regGCVM_L2_PTE_CACHE_DUMP_READ 0x15e2 +#define regGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x15e5 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x15e6 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x15e7 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x15e8 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 0 +#define regGCVM_L2_BANK_SELECT_MASKS 0x15e9 +#define regGCVM_L2_BANK_SELECT_MASKS_BASE_IDX 0 +#define regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 0x15ea +#define regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX 0 +#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 0x15eb +#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX 0 +#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 0x15ec +#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX 0 +#define regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 0x15ed +#define regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX 0 +#define regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 0x15ee +#define regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 0 + + +// addressBlock: gc_gcvmsharedvcdec +// base address: 0xa360 +#define regGCMC_VM_FB_LOCATION_BASE 0x1678 +#define regGCMC_VM_FB_LOCATION_BASE_BASE_IDX 0 +#define regGCMC_VM_FB_LOCATION_TOP 0x1679 +#define regGCMC_VM_FB_LOCATION_TOP_BASE_IDX 0 +#define regGCMC_VM_AGP_TOP 0x167a +#define regGCMC_VM_AGP_TOP_BASE_IDX 0 +#define regGCMC_VM_AGP_BOT 0x167b +#define regGCMC_VM_AGP_BOT_BASE_IDX 0 +#define regGCMC_VM_AGP_BASE 0x167c +#define regGCMC_VM_AGP_BASE_BASE_IDX 0 +#define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x167d +#define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 +#define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x167e +#define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 +#define regGCMC_VM_MX_L1_TLB_CNTL 0x167f +#define regGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 + + +// addressBlock: gc_gcvml2vcdec +// base address: 0xa3a0 +#define regGCVM_CONTEXT0_CNTL 0x1688 +#define regGCVM_CONTEXT0_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT1_CNTL 0x1689 +#define regGCVM_CONTEXT1_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT2_CNTL 0x168a +#define regGCVM_CONTEXT2_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT3_CNTL 0x168b +#define regGCVM_CONTEXT3_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT4_CNTL 0x168c +#define regGCVM_CONTEXT4_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT5_CNTL 0x168d +#define regGCVM_CONTEXT5_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT6_CNTL 0x168e +#define regGCVM_CONTEXT6_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT7_CNTL 0x168f +#define regGCVM_CONTEXT7_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT8_CNTL 0x1690 +#define regGCVM_CONTEXT8_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT9_CNTL 0x1691 +#define regGCVM_CONTEXT9_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT10_CNTL 0x1692 +#define regGCVM_CONTEXT10_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT11_CNTL 0x1693 +#define regGCVM_CONTEXT11_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT12_CNTL 0x1694 +#define regGCVM_CONTEXT12_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT13_CNTL 0x1695 +#define regGCVM_CONTEXT13_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT14_CNTL 0x1696 +#define regGCVM_CONTEXT14_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT15_CNTL 0x1697 +#define regGCVM_CONTEXT15_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXTS_DISABLE 0x1698 +#define regGCVM_CONTEXTS_DISABLE_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG0_SEM 0x1699 +#define regGCVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG1_SEM 0x169a +#define regGCVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG2_SEM 0x169b +#define regGCVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG3_SEM 0x169c +#define regGCVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG4_SEM 0x169d +#define regGCVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG5_SEM 0x169e +#define regGCVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG6_SEM 0x169f +#define regGCVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG7_SEM 0x16a0 +#define regGCVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG8_SEM 0x16a1 +#define regGCVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG9_SEM 0x16a2 +#define regGCVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG10_SEM 0x16a3 +#define regGCVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG11_SEM 0x16a4 +#define regGCVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG12_SEM 0x16a5 +#define regGCVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG13_SEM 0x16a6 +#define regGCVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG14_SEM 0x16a7 +#define regGCVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG15_SEM 0x16a8 +#define regGCVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG16_SEM 0x16a9 +#define regGCVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG17_SEM 0x16aa +#define regGCVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG0_REQ 0x16ab +#define regGCVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG1_REQ 0x16ac +#define regGCVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG2_REQ 0x16ad +#define regGCVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG3_REQ 0x16ae +#define regGCVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG4_REQ 0x16af +#define regGCVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG5_REQ 0x16b0 +#define regGCVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG6_REQ 0x16b1 +#define regGCVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG7_REQ 0x16b2 +#define regGCVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG8_REQ 0x16b3 +#define regGCVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG9_REQ 0x16b4 +#define regGCVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG10_REQ 0x16b5 +#define regGCVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG11_REQ 0x16b6 +#define regGCVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG12_REQ 0x16b7 +#define regGCVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG13_REQ 0x16b8 +#define regGCVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG14_REQ 0x16b9 +#define regGCVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG15_REQ 0x16ba +#define regGCVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG16_REQ 0x16bb +#define regGCVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG17_REQ 0x16bc +#define regGCVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG0_ACK 0x16bd +#define regGCVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG1_ACK 0x16be +#define regGCVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG2_ACK 0x16bf +#define regGCVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG3_ACK 0x16c0 +#define regGCVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG4_ACK 0x16c1 +#define regGCVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG5_ACK 0x16c2 +#define regGCVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG6_ACK 0x16c3 +#define regGCVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG7_ACK 0x16c4 +#define regGCVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG8_ACK 0x16c5 +#define regGCVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG9_ACK 0x16c6 +#define regGCVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG10_ACK 0x16c7 +#define regGCVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG11_ACK 0x16c8 +#define regGCVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG12_ACK 0x16c9 +#define regGCVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG13_ACK 0x16ca +#define regGCVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG14_ACK 0x16cb +#define regGCVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG15_ACK 0x16cc +#define regGCVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG16_ACK 0x16cd +#define regGCVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG17_ACK 0x16ce +#define regGCVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x16cf +#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x16d0 +#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x16d1 +#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x16d2 +#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x16d3 +#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x16d4 +#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x16d5 +#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x16d6 +#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x16d7 +#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x16d8 +#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x16d9 +#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x16da +#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x16db +#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x16dc +#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x16dd +#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x16de +#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x16df +#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x16e0 +#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x16e1 +#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x16e2 +#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x16e3 +#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x16e4 +#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x16e5 +#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x16e6 +#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x16e7 +#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x16e8 +#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x16e9 +#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x16ea +#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x16eb +#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x16ec +#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x16ed +#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x16ee +#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x16ef +#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x16f0 +#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x16f1 +#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x16f2 +#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x16f3 +#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x16f4 +#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x16f5 +#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x16f6 +#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x16f7 +#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x16f8 +#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x16f9 +#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x16fa +#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x16fb +#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x16fc +#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x16fd +#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x16fe +#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x16ff +#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x1700 +#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x1701 +#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x1702 +#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x1703 +#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x1704 +#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x1705 +#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x1706 +#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x1707 +#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x1708 +#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x1709 +#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x170a +#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x170b +#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x170c +#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x170d +#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x170e +#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x170f +#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x1710 +#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x1711 +#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x1712 +#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x1713 +#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x1714 +#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x1715 +#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x1716 +#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x1717 +#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x1718 +#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x1719 +#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x171a +#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x171b +#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x171c +#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x171d +#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x171e +#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x171f +#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x1720 +#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x1721 +#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x1722 +#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x1723 +#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x1724 +#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x1725 +#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x1726 +#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x1727 +#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x1728 +#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x1729 +#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x172a +#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x172b +#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x172c +#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x172d +#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x172e +#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x172f +#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x1730 +#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x1731 +#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x1732 +#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x1733 +#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x1734 +#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x1735 +#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x1736 +#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x1737 +#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x1738 +#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x1739 +#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x173a +#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x173b +#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x173c +#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x173d +#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x173e +#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x173f +#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x1740 +#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x1741 +#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x1742 +#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x1743 +#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x1744 +#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x1745 +#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x1746 +#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x1747 +#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x1748 +#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x1749 +#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x174a +#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x174b +#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x174c +#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x174d +#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x174e +#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x174f +#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x1750 +#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x1751 +#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x1752 +#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1753 +#define regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1754 +#define regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1755 +#define regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1756 +#define regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1757 +#define regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1758 +#define regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1759 +#define regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175a +#define regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175b +#define regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175c +#define regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175d +#define regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175e +#define regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175f +#define regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1760 +#define regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1761 +#define regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1762 +#define regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1763 +#define regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 + + +// addressBlock: gc_gcvml2perfddec +// base address: 0x35380 +#define regGCVML2_PERFCOUNTER2_0_LO 0x34e0 +#define regGCVML2_PERFCOUNTER2_0_LO_BASE_IDX 1 +#define regGCVML2_PERFCOUNTER2_1_LO 0x34e1 +#define regGCVML2_PERFCOUNTER2_1_LO_BASE_IDX 1 +#define regGCVML2_PERFCOUNTER2_0_HI 0x34e2 +#define regGCVML2_PERFCOUNTER2_0_HI_BASE_IDX 1 +#define regGCVML2_PERFCOUNTER2_1_HI 0x34e3 +#define regGCVML2_PERFCOUNTER2_1_HI_BASE_IDX 1 + + +// addressBlock: gc_gcvml2prdec +// base address: 0x35390 +#define regGCMC_VM_L2_PERFCOUNTER_LO 0x34e4 +#define regGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER_HI 0x34e5 +#define regGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER_LO 0x34e6 +#define regGCUTCL2_PERFCOUNTER_LO_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER_HI 0x34e7 +#define regGCUTCL2_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: gc_gcvml2perfsdec +// base address: 0x37480 +#define regGCVML2_PERFCOUNTER2_0_SELECT 0x3d20 +#define regGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX 1 +#define regGCVML2_PERFCOUNTER2_1_SELECT 0x3d21 +#define regGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX 1 +#define regGCVML2_PERFCOUNTER2_0_SELECT1 0x3d22 +#define regGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX 1 +#define regGCVML2_PERFCOUNTER2_1_SELECT1 0x3d23 +#define regGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX 1 +#define regGCVML2_PERFCOUNTER2_0_MODE 0x3d24 +#define regGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX 1 +#define regGCVML2_PERFCOUNTER2_1_MODE 0x3d25 +#define regGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX 1 + + +// addressBlock: gc_gcvml2pldec +// base address: 0x374c0 +#define regGCMC_VM_L2_PERFCOUNTER0_CFG 0x3d30 +#define regGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER1_CFG 0x3d31 +#define regGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER2_CFG 0x3d32 +#define regGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER3_CFG 0x3d33 +#define regGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER4_CFG 0x3d34 +#define regGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER5_CFG 0x3d35 +#define regGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER6_CFG 0x3d36 +#define regGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER7_CFG 0x3d37 +#define regGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3d38 +#define regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER0_CFG 0x3d39 +#define regGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER1_CFG 0x3d3a +#define regGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER2_CFG 0x3d3b +#define regGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER3_CFG 0x3d3c +#define regGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER_RSLT_CNTL 0x3d3d +#define regGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: gc_gcvmsharedhvdec +// base address: 0x3ea00 +#define regGCMC_VM_FB_SIZE_OFFSET_VF0 0x5a80 +#define regGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF1 0x5a81 +#define regGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF2 0x5a82 +#define regGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF3 0x5a83 +#define regGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF4 0x5a84 +#define regGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF5 0x5a85 +#define regGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF6 0x5a86 +#define regGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF7 0x5a87 +#define regGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF8 0x5a88 +#define regGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF9 0x5a89 +#define regGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF10 0x5a8a +#define regGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF11 0x5a8b +#define regGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF12 0x5a8c +#define regGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF13 0x5a8d +#define regGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF14 0x5a8e +#define regGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF15 0x5a8f +#define regGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 + + +// addressBlock: gc_gcvml2pspdec +// base address: 0x3f900 +#define regGCUTCL2_TRANSLATION_BYPASS_BY_VMID 0x5e41 +#define regGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX 1 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 0x5e44 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_0 0x5e48 +#define regGCMC_VM_MARC_BASE_LO_0_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_1 0x5e49 +#define regGCMC_VM_MARC_BASE_LO_1_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_2 0x5e4a +#define regGCMC_VM_MARC_BASE_LO_2_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_3 0x5e4b +#define regGCMC_VM_MARC_BASE_LO_3_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_4 0x5e4c +#define regGCMC_VM_MARC_BASE_LO_4_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_5 0x5e4d +#define regGCMC_VM_MARC_BASE_LO_5_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_6 0x5e4e +#define regGCMC_VM_MARC_BASE_LO_6_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_7 0x5e4f +#define regGCMC_VM_MARC_BASE_LO_7_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_8 0x5e50 +#define regGCMC_VM_MARC_BASE_LO_8_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_9 0x5e51 +#define regGCMC_VM_MARC_BASE_LO_9_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_10 0x5e52 +#define regGCMC_VM_MARC_BASE_LO_10_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_11 0x5e53 +#define regGCMC_VM_MARC_BASE_LO_11_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_12 0x5e54 +#define regGCMC_VM_MARC_BASE_LO_12_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_13 0x5e55 +#define regGCMC_VM_MARC_BASE_LO_13_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_14 0x5e56 +#define regGCMC_VM_MARC_BASE_LO_14_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_15 0x5e57 +#define regGCMC_VM_MARC_BASE_LO_15_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_0 0x5e58 +#define regGCMC_VM_MARC_BASE_HI_0_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_1 0x5e59 +#define regGCMC_VM_MARC_BASE_HI_1_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_2 0x5e5a +#define regGCMC_VM_MARC_BASE_HI_2_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_3 0x5e5b +#define regGCMC_VM_MARC_BASE_HI_3_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_4 0x5e5c +#define regGCMC_VM_MARC_BASE_HI_4_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_5 0x5e5d +#define regGCMC_VM_MARC_BASE_HI_5_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_6 0x5e5e +#define regGCMC_VM_MARC_BASE_HI_6_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_7 0x5e5f +#define regGCMC_VM_MARC_BASE_HI_7_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_8 0x5e60 +#define regGCMC_VM_MARC_BASE_HI_8_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_9 0x5e61 +#define regGCMC_VM_MARC_BASE_HI_9_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_10 0x5e62 +#define regGCMC_VM_MARC_BASE_HI_10_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_11 0x5e63 +#define regGCMC_VM_MARC_BASE_HI_11_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_12 0x5e64 +#define regGCMC_VM_MARC_BASE_HI_12_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_13 0x5e65 +#define regGCMC_VM_MARC_BASE_HI_13_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_14 0x5e66 +#define regGCMC_VM_MARC_BASE_HI_14_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_15 0x5e67 +#define regGCMC_VM_MARC_BASE_HI_15_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_0 0x5e68 +#define regGCMC_VM_MARC_RELOC_LO_0_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_1 0x5e69 +#define regGCMC_VM_MARC_RELOC_LO_1_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_2 0x5e6a +#define regGCMC_VM_MARC_RELOC_LO_2_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_3 0x5e6b +#define regGCMC_VM_MARC_RELOC_LO_3_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_4 0x5e6c +#define regGCMC_VM_MARC_RELOC_LO_4_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_5 0x5e6d +#define regGCMC_VM_MARC_RELOC_LO_5_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_6 0x5e6e +#define regGCMC_VM_MARC_RELOC_LO_6_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_7 0x5e6f +#define regGCMC_VM_MARC_RELOC_LO_7_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_8 0x5e70 +#define regGCMC_VM_MARC_RELOC_LO_8_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_9 0x5e71 +#define regGCMC_VM_MARC_RELOC_LO_9_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_10 0x5e72 +#define regGCMC_VM_MARC_RELOC_LO_10_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_11 0x5e73 +#define regGCMC_VM_MARC_RELOC_LO_11_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_12 0x5e74 +#define regGCMC_VM_MARC_RELOC_LO_12_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_13 0x5e75 +#define regGCMC_VM_MARC_RELOC_LO_13_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_14 0x5e76 +#define regGCMC_VM_MARC_RELOC_LO_14_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_15 0x5e77 +#define regGCMC_VM_MARC_RELOC_LO_15_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_0 0x5e78 +#define regGCMC_VM_MARC_RELOC_HI_0_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_1 0x5e79 +#define regGCMC_VM_MARC_RELOC_HI_1_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_2 0x5e7a +#define regGCMC_VM_MARC_RELOC_HI_2_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_3 0x5e7b +#define regGCMC_VM_MARC_RELOC_HI_3_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_4 0x5e7c +#define regGCMC_VM_MARC_RELOC_HI_4_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_5 0x5e7d +#define regGCMC_VM_MARC_RELOC_HI_5_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_6 0x5e7e +#define regGCMC_VM_MARC_RELOC_HI_6_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_7 0x5e7f +#define regGCMC_VM_MARC_RELOC_HI_7_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_8 0x5e80 +#define regGCMC_VM_MARC_RELOC_HI_8_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_9 0x5e81 +#define regGCMC_VM_MARC_RELOC_HI_9_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_10 0x5e82 +#define regGCMC_VM_MARC_RELOC_HI_10_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_11 0x5e83 +#define regGCMC_VM_MARC_RELOC_HI_11_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_12 0x5e84 +#define regGCMC_VM_MARC_RELOC_HI_12_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_13 0x5e85 +#define regGCMC_VM_MARC_RELOC_HI_13_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_14 0x5e86 +#define regGCMC_VM_MARC_RELOC_HI_14_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_15 0x5e87 +#define regGCMC_VM_MARC_RELOC_HI_15_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_0 0x5e88 +#define regGCMC_VM_MARC_LEN_LO_0_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_1 0x5e89 +#define regGCMC_VM_MARC_LEN_LO_1_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_2 0x5e8a +#define regGCMC_VM_MARC_LEN_LO_2_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_3 0x5e8b +#define regGCMC_VM_MARC_LEN_LO_3_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_4 0x5e8c +#define regGCMC_VM_MARC_LEN_LO_4_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_5 0x5e8d +#define regGCMC_VM_MARC_LEN_LO_5_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_6 0x5e8e +#define regGCMC_VM_MARC_LEN_LO_6_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_7 0x5e8f +#define regGCMC_VM_MARC_LEN_LO_7_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_8 0x5e90 +#define regGCMC_VM_MARC_LEN_LO_8_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_9 0x5e91 +#define regGCMC_VM_MARC_LEN_LO_9_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_10 0x5e92 +#define regGCMC_VM_MARC_LEN_LO_10_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_11 0x5e93 +#define regGCMC_VM_MARC_LEN_LO_11_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_12 0x5e94 +#define regGCMC_VM_MARC_LEN_LO_12_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_13 0x5e95 +#define regGCMC_VM_MARC_LEN_LO_13_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_14 0x5e96 +#define regGCMC_VM_MARC_LEN_LO_14_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_15 0x5e97 +#define regGCMC_VM_MARC_LEN_LO_15_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_0 0x5e98 +#define regGCMC_VM_MARC_LEN_HI_0_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_1 0x5e99 +#define regGCMC_VM_MARC_LEN_HI_1_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_2 0x5e9a +#define regGCMC_VM_MARC_LEN_HI_2_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_3 0x5e9b +#define regGCMC_VM_MARC_LEN_HI_3_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_4 0x5e9c +#define regGCMC_VM_MARC_LEN_HI_4_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_5 0x5e9d +#define regGCMC_VM_MARC_LEN_HI_5_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_6 0x5e9e +#define regGCMC_VM_MARC_LEN_HI_6_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_7 0x5e9f +#define regGCMC_VM_MARC_LEN_HI_7_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_8 0x5ea0 +#define regGCMC_VM_MARC_LEN_HI_8_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_9 0x5ea1 +#define regGCMC_VM_MARC_LEN_HI_9_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_10 0x5ea2 +#define regGCMC_VM_MARC_LEN_HI_10_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_11 0x5ea3 +#define regGCMC_VM_MARC_LEN_HI_11_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_12 0x5ea4 +#define regGCMC_VM_MARC_LEN_HI_12_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_13 0x5ea5 +#define regGCMC_VM_MARC_LEN_HI_13_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_14 0x5ea6 +#define regGCMC_VM_MARC_LEN_HI_14_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_15 0x5ea7 +#define regGCMC_VM_MARC_LEN_HI_15_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_0 0x5ea8 +#define regGCMC_VM_MARC_PFVF_MAPPING_0_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_1 0x5ea9 +#define regGCMC_VM_MARC_PFVF_MAPPING_1_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_2 0x5eaa +#define regGCMC_VM_MARC_PFVF_MAPPING_2_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_3 0x5eab +#define regGCMC_VM_MARC_PFVF_MAPPING_3_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_4 0x5eac +#define regGCMC_VM_MARC_PFVF_MAPPING_4_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_5 0x5ead +#define regGCMC_VM_MARC_PFVF_MAPPING_5_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_6 0x5eae +#define regGCMC_VM_MARC_PFVF_MAPPING_6_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_7 0x5eaf +#define regGCMC_VM_MARC_PFVF_MAPPING_7_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_8 0x5eb0 +#define regGCMC_VM_MARC_PFVF_MAPPING_8_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_9 0x5eb1 +#define regGCMC_VM_MARC_PFVF_MAPPING_9_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_10 0x5eb2 +#define regGCMC_VM_MARC_PFVF_MAPPING_10_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_11 0x5eb3 +#define regGCMC_VM_MARC_PFVF_MAPPING_11_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_12 0x5eb4 +#define regGCMC_VM_MARC_PFVF_MAPPING_12_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_13 0x5eb5 +#define regGCMC_VM_MARC_PFVF_MAPPING_13_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_14 0x5eb6 +#define regGCMC_VM_MARC_PFVF_MAPPING_14_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_15 0x5eb7 +#define regGCMC_VM_MARC_PFVF_MAPPING_15_BASE_IDX 1 +#define regGCUTC_TRANSLATION_FAULT_CNTL0 0x5eb8 +#define regGCUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX 1 +#define regGCUTC_TRANSLATION_FAULT_CNTL1 0x5eb9 +#define regGCUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX 1 + + +// addressBlock: gc_shdec +// base address: 0xb000 +#define regSPI_SHADER_PGM_RSRC4_PS 0x19a1 +#define regSPI_SHADER_PGM_RSRC4_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_CHKSUM_PS 0x19a6 +#define regSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC3_PS 0x19a7 +#define regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_PS 0x19a8 +#define regSPI_SHADER_PGM_LO_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_PS 0x19a9 +#define regSPI_SHADER_PGM_HI_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC1_PS 0x19aa +#define regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_PS 0x19ab +#define regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_0 0x19ac +#define regSPI_SHADER_USER_DATA_PS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_1 0x19ad +#define regSPI_SHADER_USER_DATA_PS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_2 0x19ae +#define regSPI_SHADER_USER_DATA_PS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_3 0x19af +#define regSPI_SHADER_USER_DATA_PS_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_4 0x19b0 +#define regSPI_SHADER_USER_DATA_PS_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_5 0x19b1 +#define regSPI_SHADER_USER_DATA_PS_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_6 0x19b2 +#define regSPI_SHADER_USER_DATA_PS_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_7 0x19b3 +#define regSPI_SHADER_USER_DATA_PS_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_8 0x19b4 +#define regSPI_SHADER_USER_DATA_PS_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_9 0x19b5 +#define regSPI_SHADER_USER_DATA_PS_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_10 0x19b6 +#define regSPI_SHADER_USER_DATA_PS_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_11 0x19b7 +#define regSPI_SHADER_USER_DATA_PS_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_12 0x19b8 +#define regSPI_SHADER_USER_DATA_PS_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_13 0x19b9 +#define regSPI_SHADER_USER_DATA_PS_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_14 0x19ba +#define regSPI_SHADER_USER_DATA_PS_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_15 0x19bb +#define regSPI_SHADER_USER_DATA_PS_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_16 0x19bc +#define regSPI_SHADER_USER_DATA_PS_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_17 0x19bd +#define regSPI_SHADER_USER_DATA_PS_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_18 0x19be +#define regSPI_SHADER_USER_DATA_PS_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_19 0x19bf +#define regSPI_SHADER_USER_DATA_PS_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_20 0x19c0 +#define regSPI_SHADER_USER_DATA_PS_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_21 0x19c1 +#define regSPI_SHADER_USER_DATA_PS_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_22 0x19c2 +#define regSPI_SHADER_USER_DATA_PS_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_23 0x19c3 +#define regSPI_SHADER_USER_DATA_PS_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_24 0x19c4 +#define regSPI_SHADER_USER_DATA_PS_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_25 0x19c5 +#define regSPI_SHADER_USER_DATA_PS_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_26 0x19c6 +#define regSPI_SHADER_USER_DATA_PS_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_27 0x19c7 +#define regSPI_SHADER_USER_DATA_PS_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_28 0x19c8 +#define regSPI_SHADER_USER_DATA_PS_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_29 0x19c9 +#define regSPI_SHADER_USER_DATA_PS_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_30 0x19ca +#define regSPI_SHADER_USER_DATA_PS_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_31 0x19cb +#define regSPI_SHADER_USER_DATA_PS_31_BASE_IDX 0 +#define regSPI_SHADER_REQ_CTRL_PS 0x19d0 +#define regSPI_SHADER_REQ_CTRL_PS_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_PS_0 0x19d2 +#define regSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_PS_1 0x19d3 +#define regSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_PS_2 0x19d4 +#define regSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_PS_3 0x19d5 +#define regSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX 0 +#define regSPI_SHADER_PGM_CHKSUM_GS 0x1a20 +#define regSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC4_GS 0x1a21 +#define regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_LO_GS 0x1a22 +#define regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_HI_GS 0x1a23 +#define regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_ES_GS 0x1a24 +#define regSPI_SHADER_PGM_LO_ES_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_ES_GS 0x1a25 +#define regSPI_SHADER_PGM_HI_ES_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC3_GS 0x1a27 +#define regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_GS 0x1a28 +#define regSPI_SHADER_PGM_LO_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_GS 0x1a29 +#define regSPI_SHADER_PGM_HI_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC1_GS 0x1a2a +#define regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_GS 0x1a2b +#define regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_0 0x1a2c +#define regSPI_SHADER_USER_DATA_GS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_1 0x1a2d +#define regSPI_SHADER_USER_DATA_GS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_2 0x1a2e +#define regSPI_SHADER_USER_DATA_GS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_3 0x1a2f +#define regSPI_SHADER_USER_DATA_GS_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_4 0x1a30 +#define regSPI_SHADER_USER_DATA_GS_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_5 0x1a31 +#define regSPI_SHADER_USER_DATA_GS_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_6 0x1a32 +#define regSPI_SHADER_USER_DATA_GS_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_7 0x1a33 +#define regSPI_SHADER_USER_DATA_GS_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_8 0x1a34 +#define regSPI_SHADER_USER_DATA_GS_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_9 0x1a35 +#define regSPI_SHADER_USER_DATA_GS_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_10 0x1a36 +#define regSPI_SHADER_USER_DATA_GS_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_11 0x1a37 +#define regSPI_SHADER_USER_DATA_GS_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_12 0x1a38 +#define regSPI_SHADER_USER_DATA_GS_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_13 0x1a39 +#define regSPI_SHADER_USER_DATA_GS_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_14 0x1a3a +#define regSPI_SHADER_USER_DATA_GS_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_15 0x1a3b +#define regSPI_SHADER_USER_DATA_GS_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_16 0x1a3c +#define regSPI_SHADER_USER_DATA_GS_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_17 0x1a3d +#define regSPI_SHADER_USER_DATA_GS_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_18 0x1a3e +#define regSPI_SHADER_USER_DATA_GS_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_19 0x1a3f +#define regSPI_SHADER_USER_DATA_GS_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_20 0x1a40 +#define regSPI_SHADER_USER_DATA_GS_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_21 0x1a41 +#define regSPI_SHADER_USER_DATA_GS_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_22 0x1a42 +#define regSPI_SHADER_USER_DATA_GS_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_23 0x1a43 +#define regSPI_SHADER_USER_DATA_GS_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_24 0x1a44 +#define regSPI_SHADER_USER_DATA_GS_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_25 0x1a45 +#define regSPI_SHADER_USER_DATA_GS_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_26 0x1a46 +#define regSPI_SHADER_USER_DATA_GS_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_27 0x1a47 +#define regSPI_SHADER_USER_DATA_GS_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_28 0x1a48 +#define regSPI_SHADER_USER_DATA_GS_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_29 0x1a49 +#define regSPI_SHADER_USER_DATA_GS_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_30 0x1a4a +#define regSPI_SHADER_USER_DATA_GS_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_31 0x1a4b +#define regSPI_SHADER_USER_DATA_GS_31_BASE_IDX 0 +#define regSPI_SHADER_GS_MESHLET_DIM 0x1a4c +#define regSPI_SHADER_GS_MESHLET_DIM_BASE_IDX 0 +#define regSPI_SHADER_GS_MESHLET_EXP_ALLOC 0x1a4d +#define regSPI_SHADER_GS_MESHLET_EXP_ALLOC_BASE_IDX 0 +#define regSPI_SHADER_REQ_CTRL_ESGS 0x1a50 +#define regSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_ESGS_0 0x1a52 +#define regSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_ESGS_1 0x1a53 +#define regSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_ESGS_2 0x1a54 +#define regSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_ESGS_3 0x1a55 +#define regSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_ES 0x1a68 +#define regSPI_SHADER_PGM_LO_ES_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_ES 0x1a69 +#define regSPI_SHADER_PGM_HI_ES_BASE_IDX 0 +#define regSPI_SHADER_PGM_CHKSUM_HS 0x1aa0 +#define regSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC4_HS 0x1aa1 +#define regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_LO_HS 0x1aa2 +#define regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_HI_HS 0x1aa3 +#define regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_LS_HS 0x1aa4 +#define regSPI_SHADER_PGM_LO_LS_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_LS_HS 0x1aa5 +#define regSPI_SHADER_PGM_HI_LS_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC3_HS 0x1aa7 +#define regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_HS 0x1aa8 +#define regSPI_SHADER_PGM_LO_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_HS 0x1aa9 +#define regSPI_SHADER_PGM_HI_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC1_HS 0x1aaa +#define regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_HS 0x1aab +#define regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_0 0x1aac +#define regSPI_SHADER_USER_DATA_HS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_1 0x1aad +#define regSPI_SHADER_USER_DATA_HS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_2 0x1aae +#define regSPI_SHADER_USER_DATA_HS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_3 0x1aaf +#define regSPI_SHADER_USER_DATA_HS_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_4 0x1ab0 +#define regSPI_SHADER_USER_DATA_HS_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_5 0x1ab1 +#define regSPI_SHADER_USER_DATA_HS_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_6 0x1ab2 +#define regSPI_SHADER_USER_DATA_HS_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_7 0x1ab3 +#define regSPI_SHADER_USER_DATA_HS_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_8 0x1ab4 +#define regSPI_SHADER_USER_DATA_HS_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_9 0x1ab5 +#define regSPI_SHADER_USER_DATA_HS_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_10 0x1ab6 +#define regSPI_SHADER_USER_DATA_HS_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_11 0x1ab7 +#define regSPI_SHADER_USER_DATA_HS_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_12 0x1ab8 +#define regSPI_SHADER_USER_DATA_HS_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_13 0x1ab9 +#define regSPI_SHADER_USER_DATA_HS_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_14 0x1aba +#define regSPI_SHADER_USER_DATA_HS_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_15 0x1abb +#define regSPI_SHADER_USER_DATA_HS_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_16 0x1abc +#define regSPI_SHADER_USER_DATA_HS_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_17 0x1abd +#define regSPI_SHADER_USER_DATA_HS_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_18 0x1abe +#define regSPI_SHADER_USER_DATA_HS_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_19 0x1abf +#define regSPI_SHADER_USER_DATA_HS_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_20 0x1ac0 +#define regSPI_SHADER_USER_DATA_HS_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_21 0x1ac1 +#define regSPI_SHADER_USER_DATA_HS_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_22 0x1ac2 +#define regSPI_SHADER_USER_DATA_HS_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_23 0x1ac3 +#define regSPI_SHADER_USER_DATA_HS_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_24 0x1ac4 +#define regSPI_SHADER_USER_DATA_HS_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_25 0x1ac5 +#define regSPI_SHADER_USER_DATA_HS_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_26 0x1ac6 +#define regSPI_SHADER_USER_DATA_HS_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_27 0x1ac7 +#define regSPI_SHADER_USER_DATA_HS_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_28 0x1ac8 +#define regSPI_SHADER_USER_DATA_HS_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_29 0x1ac9 +#define regSPI_SHADER_USER_DATA_HS_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_30 0x1aca +#define regSPI_SHADER_USER_DATA_HS_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_31 0x1acb +#define regSPI_SHADER_USER_DATA_HS_31_BASE_IDX 0 +#define regSPI_SHADER_REQ_CTRL_LSHS 0x1ad0 +#define regSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_LSHS_0 0x1ad2 +#define regSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_LSHS_1 0x1ad3 +#define regSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_LSHS_2 0x1ad4 +#define regSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_LSHS_3 0x1ad5 +#define regSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_LS 0x1ae8 +#define regSPI_SHADER_PGM_LO_LS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_LS 0x1ae9 +#define regSPI_SHADER_PGM_HI_LS_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_INITIATOR 0x1ba0 +#define regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX 0 +#define regCOMPUTE_DIM_X 0x1ba1 +#define regCOMPUTE_DIM_X_BASE_IDX 0 +#define regCOMPUTE_DIM_Y 0x1ba2 +#define regCOMPUTE_DIM_Y_BASE_IDX 0 +#define regCOMPUTE_DIM_Z 0x1ba3 +#define regCOMPUTE_DIM_Z_BASE_IDX 0 +#define regCOMPUTE_START_X 0x1ba4 +#define regCOMPUTE_START_X_BASE_IDX 0 +#define regCOMPUTE_START_Y 0x1ba5 +#define regCOMPUTE_START_Y_BASE_IDX 0 +#define regCOMPUTE_START_Z 0x1ba6 +#define regCOMPUTE_START_Z_BASE_IDX 0 +#define regCOMPUTE_NUM_THREAD_X 0x1ba7 +#define regCOMPUTE_NUM_THREAD_X_BASE_IDX 0 +#define regCOMPUTE_NUM_THREAD_Y 0x1ba8 +#define regCOMPUTE_NUM_THREAD_Y_BASE_IDX 0 +#define regCOMPUTE_NUM_THREAD_Z 0x1ba9 +#define regCOMPUTE_NUM_THREAD_Z_BASE_IDX 0 +#define regCOMPUTE_PIPELINESTAT_ENABLE 0x1baa +#define regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 0 +#define regCOMPUTE_PERFCOUNT_ENABLE 0x1bab +#define regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX 0 +#define regCOMPUTE_PGM_LO 0x1bac +#define regCOMPUTE_PGM_LO_BASE_IDX 0 +#define regCOMPUTE_PGM_HI 0x1bad +#define regCOMPUTE_PGM_HI_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_PKT_ADDR_LO 0x1bae +#define regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_PKT_ADDR_HI 0x1baf +#define regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x1bb0 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x1bb1 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 0 +#define regCOMPUTE_PGM_RSRC1 0x1bb2 +#define regCOMPUTE_PGM_RSRC1_BASE_IDX 0 +#define regCOMPUTE_PGM_RSRC2 0x1bb3 +#define regCOMPUTE_PGM_RSRC2_BASE_IDX 0 +#define regCOMPUTE_VMID 0x1bb4 +#define regCOMPUTE_VMID_BASE_IDX 0 +#define regCOMPUTE_RESOURCE_LIMITS 0x1bb5 +#define regCOMPUTE_RESOURCE_LIMITS_BASE_IDX 0 +#define regCOMPUTE_DESTINATION_EN_SE0 0x1bb6 +#define regCOMPUTE_DESTINATION_EN_SE0_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE0 0x1bb6 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 0 +#define regCOMPUTE_DESTINATION_EN_SE1 0x1bb7 +#define regCOMPUTE_DESTINATION_EN_SE1_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE1 0x1bb7 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 0 +#define regCOMPUTE_TMPRING_SIZE 0x1bb8 +#define regCOMPUTE_TMPRING_SIZE_BASE_IDX 0 +#define regCOMPUTE_DESTINATION_EN_SE2 0x1bb9 +#define regCOMPUTE_DESTINATION_EN_SE2_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE2 0x1bb9 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0 +#define regCOMPUTE_DESTINATION_EN_SE3 0x1bba +#define regCOMPUTE_DESTINATION_EN_SE3_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE3 0x1bba +#define regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0 +#define regCOMPUTE_RESTART_X 0x1bbb +#define regCOMPUTE_RESTART_X_BASE_IDX 0 +#define regCOMPUTE_RESTART_Y 0x1bbc +#define regCOMPUTE_RESTART_Y_BASE_IDX 0 +#define regCOMPUTE_RESTART_Z 0x1bbd +#define regCOMPUTE_RESTART_Z_BASE_IDX 0 +#define regCOMPUTE_THREAD_TRACE_ENABLE 0x1bbe +#define regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 0 +#define regCOMPUTE_MISC_RESERVED 0x1bbf +#define regCOMPUTE_MISC_RESERVED_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_ID 0x1bc0 +#define regCOMPUTE_DISPATCH_ID_BASE_IDX 0 +#define regCOMPUTE_THREADGROUP_ID 0x1bc1 +#define regCOMPUTE_THREADGROUP_ID_BASE_IDX 0 +#define regCOMPUTE_REQ_CTRL 0x1bc2 +#define regCOMPUTE_REQ_CTRL_BASE_IDX 0 +#define regCOMPUTE_USER_ACCUM_0 0x1bc4 +#define regCOMPUTE_USER_ACCUM_0_BASE_IDX 0 +#define regCOMPUTE_USER_ACCUM_1 0x1bc5 +#define regCOMPUTE_USER_ACCUM_1_BASE_IDX 0 +#define regCOMPUTE_USER_ACCUM_2 0x1bc6 +#define regCOMPUTE_USER_ACCUM_2_BASE_IDX 0 +#define regCOMPUTE_USER_ACCUM_3 0x1bc7 +#define regCOMPUTE_USER_ACCUM_3_BASE_IDX 0 +#define regCOMPUTE_PGM_RSRC3 0x1bc8 +#define regCOMPUTE_PGM_RSRC3_BASE_IDX 0 +#define regCOMPUTE_DDID_INDEX 0x1bc9 +#define regCOMPUTE_DDID_INDEX_BASE_IDX 0 +#define regCOMPUTE_SHADER_CHKSUM 0x1bca +#define regCOMPUTE_SHADER_CHKSUM_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE4 0x1bcb +#define regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE5 0x1bcc +#define regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE6 0x1bcd +#define regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE7 0x1bce +#define regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_INTERLEAVE 0x1bcf +#define regCOMPUTE_DISPATCH_INTERLEAVE_BASE_IDX 0 +#define regCOMPUTE_RELAUNCH 0x1bd0 +#define regCOMPUTE_RELAUNCH_BASE_IDX 0 +#define regCOMPUTE_WAVE_RESTORE_ADDR_LO 0x1bd1 +#define regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 0 +#define regCOMPUTE_WAVE_RESTORE_ADDR_HI 0x1bd2 +#define regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 0 +#define regCOMPUTE_RELAUNCH2 0x1bd3 +#define regCOMPUTE_RELAUNCH2_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_0 0x1be0 +#define regCOMPUTE_USER_DATA_0_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_1 0x1be1 +#define regCOMPUTE_USER_DATA_1_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_2 0x1be2 +#define regCOMPUTE_USER_DATA_2_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_3 0x1be3 +#define regCOMPUTE_USER_DATA_3_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_4 0x1be4 +#define regCOMPUTE_USER_DATA_4_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_5 0x1be5 +#define regCOMPUTE_USER_DATA_5_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_6 0x1be6 +#define regCOMPUTE_USER_DATA_6_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_7 0x1be7 +#define regCOMPUTE_USER_DATA_7_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_8 0x1be8 +#define regCOMPUTE_USER_DATA_8_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_9 0x1be9 +#define regCOMPUTE_USER_DATA_9_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_10 0x1bea +#define regCOMPUTE_USER_DATA_10_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_11 0x1beb +#define regCOMPUTE_USER_DATA_11_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_12 0x1bec +#define regCOMPUTE_USER_DATA_12_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_13 0x1bed +#define regCOMPUTE_USER_DATA_13_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_14 0x1bee +#define regCOMPUTE_USER_DATA_14_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_15 0x1bef +#define regCOMPUTE_USER_DATA_15_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_TUNNEL 0x1c1d +#define regCOMPUTE_DISPATCH_TUNNEL_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_END 0x1c1e +#define regCOMPUTE_DISPATCH_END_BASE_IDX 0 +#define regCOMPUTE_NOWHERE 0x1c1f +#define regCOMPUTE_NOWHERE_BASE_IDX 0 +#define regSH_RESERVED_REG0 0x1c20 +#define regSH_RESERVED_REG0_BASE_IDX 0 +#define regSH_RESERVED_REG1 0x1c21 +#define regSH_RESERVED_REG1_BASE_IDX 0 + + +// addressBlock: gc_cppdec +// base address: 0xc080 +#define regCP_CU_MASK_ADDR_LO 0x1dd2 +#define regCP_CU_MASK_ADDR_LO_BASE_IDX 0 +#define regCP_CU_MASK_ADDR_HI 0x1dd3 +#define regCP_CU_MASK_ADDR_HI_BASE_IDX 0 +#define regCP_CU_MASK_CNTL 0x1dd4 +#define regCP_CU_MASK_CNTL_BASE_IDX 0 +#define regCP_EOPQ_WAIT_TIME 0x1dd5 +#define regCP_EOPQ_WAIT_TIME_BASE_IDX 0 +#define regCP_CPC_MGCG_SYNC_CNTL 0x1dd6 +#define regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0 +#define regCPC_INT_INFO 0x1dd7 +#define regCPC_INT_INFO_BASE_IDX 0 +#define regCP_VIRT_STATUS 0x1dd8 +#define regCP_VIRT_STATUS_BASE_IDX 0 +#define regCPC_INT_ADDR 0x1dd9 +#define regCPC_INT_ADDR_BASE_IDX 0 +#define regCPC_INT_PASID 0x1dda +#define regCPC_INT_PASID_BASE_IDX 0 +#define regCP_GFX_ERROR 0x1ddb +#define regCP_GFX_ERROR_BASE_IDX 0 +#define regCPG_UTCL1_CNTL 0x1ddc +#define regCPG_UTCL1_CNTL_BASE_IDX 0 +#define regCPC_UTCL1_CNTL 0x1ddd +#define regCPC_UTCL1_CNTL_BASE_IDX 0 +#define regCPF_UTCL1_CNTL 0x1dde +#define regCPF_UTCL1_CNTL_BASE_IDX 0 +#define regCP_AQL_SMM_STATUS 0x1ddf +#define regCP_AQL_SMM_STATUS_BASE_IDX 0 +#define regCP_RB0_BASE 0x1de0 +#define regCP_RB0_BASE_BASE_IDX 0 +#define regCP_RB_BASE 0x1de0 +#define regCP_RB_BASE_BASE_IDX 0 +#define regCP_RB0_CNTL 0x1de1 +#define regCP_RB0_CNTL_BASE_IDX 0 +#define regCP_RB_CNTL 0x1de1 +#define regCP_RB_CNTL_BASE_IDX 0 +#define regCP_RB_RPTR_WR 0x1de2 +#define regCP_RB_RPTR_WR_BASE_IDX 0 +#define regCP_RB0_RPTR_ADDR 0x1de3 +#define regCP_RB0_RPTR_ADDR_BASE_IDX 0 +#define regCP_RB_RPTR_ADDR 0x1de3 +#define regCP_RB_RPTR_ADDR_BASE_IDX 0 +#define regCP_RB0_RPTR_ADDR_HI 0x1de4 +#define regCP_RB0_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB_RPTR_ADDR_HI 0x1de4 +#define regCP_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB0_BUFSZ_MASK 0x1de5 +#define regCP_RB0_BUFSZ_MASK_BASE_IDX 0 +#define regCP_RB_BUFSZ_MASK 0x1de5 +#define regCP_RB_BUFSZ_MASK_BASE_IDX 0 +#define regCP_INT_CNTL 0x1de9 +#define regCP_INT_CNTL_BASE_IDX 0 +#define regCP_INT_STATUS 0x1dea +#define regCP_INT_STATUS_BASE_IDX 0 +#define regCP_DEVICE_ID 0x1deb +#define regCP_DEVICE_ID_BASE_IDX 0 +#define regCP_ME0_PIPE_PRIORITY_CNTS 0x1dec +#define regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_RING_PRIORITY_CNTS 0x1dec +#define regCP_RING_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_ME0_PIPE0_PRIORITY 0x1ded +#define regCP_ME0_PIPE0_PRIORITY_BASE_IDX 0 +#define regCP_RING0_PRIORITY 0x1ded +#define regCP_RING0_PRIORITY_BASE_IDX 0 +#define regCP_ME0_PIPE1_PRIORITY 0x1dee +#define regCP_ME0_PIPE1_PRIORITY_BASE_IDX 0 +#define regCP_RING1_PRIORITY 0x1dee +#define regCP_RING1_PRIORITY_BASE_IDX 0 +#define regCP_FATAL_ERROR 0x1df0 +#define regCP_FATAL_ERROR_BASE_IDX 0 +#define regCP_RB_VMID 0x1df1 +#define regCP_RB_VMID_BASE_IDX 0 +#define regCP_ME0_PIPE0_VMID 0x1df2 +#define regCP_ME0_PIPE0_VMID_BASE_IDX 0 +#define regCP_ME0_PIPE1_VMID 0x1df3 +#define regCP_ME0_PIPE1_VMID_BASE_IDX 0 +#define regCP_RB0_WPTR 0x1df4 +#define regCP_RB0_WPTR_BASE_IDX 0 +#define regCP_RB_WPTR 0x1df4 +#define regCP_RB_WPTR_BASE_IDX 0 +#define regCP_RB0_WPTR_HI 0x1df5 +#define regCP_RB0_WPTR_HI_BASE_IDX 0 +#define regCP_RB_WPTR_HI 0x1df5 +#define regCP_RB_WPTR_HI_BASE_IDX 0 +#define regCP_RB1_WPTR 0x1df6 +#define regCP_RB1_WPTR_BASE_IDX 0 +#define regCP_RB1_WPTR_HI 0x1df7 +#define regCP_RB1_WPTR_HI_BASE_IDX 0 +#define regCP_PROCESS_QUANTUM 0x1df9 +#define regCP_PROCESS_QUANTUM_BASE_IDX 0 +#define regCP_RB_DOORBELL_RANGE_LOWER 0x1dfa +#define regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0 +#define regCP_RB_DOORBELL_RANGE_UPPER 0x1dfb +#define regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0 +#define regCP_MEC_DOORBELL_RANGE_LOWER 0x1dfc +#define regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0 +#define regCP_MEC_DOORBELL_RANGE_UPPER 0x1dfd +#define regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0 +#define regCPG_UTCL1_ERROR 0x1dfe +#define regCPG_UTCL1_ERROR_BASE_IDX 0 +#define regCPC_UTCL1_ERROR 0x1dff +#define regCPC_UTCL1_ERROR_BASE_IDX 0 +#define regCP_RB1_BASE 0x1e00 +#define regCP_RB1_BASE_BASE_IDX 0 +#define regCP_RB1_CNTL 0x1e01 +#define regCP_RB1_CNTL_BASE_IDX 0 +#define regCP_RB1_RPTR_ADDR 0x1e02 +#define regCP_RB1_RPTR_ADDR_BASE_IDX 0 +#define regCP_RB1_RPTR_ADDR_HI 0x1e03 +#define regCP_RB1_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB1_BUFSZ_MASK 0x1e04 +#define regCP_RB1_BUFSZ_MASK_BASE_IDX 0 +#define regCP_INT_CNTL_RING0 0x1e0a +#define regCP_INT_CNTL_RING0_BASE_IDX 0 +#define regCP_INT_CNTL_RING1 0x1e0b +#define regCP_INT_CNTL_RING1_BASE_IDX 0 +#define regCP_INT_STATUS_RING0 0x1e0d +#define regCP_INT_STATUS_RING0_BASE_IDX 0 +#define regCP_INT_STATUS_RING1 0x1e0e +#define regCP_INT_STATUS_RING1_BASE_IDX 0 +#define regCP_ME_F32_INTERRUPT 0x1e13 +#define regCP_ME_F32_INTERRUPT_BASE_IDX 0 +#define regCP_PFP_F32_INTERRUPT 0x1e14 +#define regCP_PFP_F32_INTERRUPT_BASE_IDX 0 +#define regCP_MEC1_F32_INTERRUPT 0x1e16 +#define regCP_MEC1_F32_INTERRUPT_BASE_IDX 0 +#define regCP_MEC2_F32_INTERRUPT 0x1e17 +#define regCP_MEC2_F32_INTERRUPT_BASE_IDX 0 +#define regCP_PWR_CNTL 0x1e18 +#define regCP_PWR_CNTL_BASE_IDX 0 +#define regCP_ECC_FIRSTOCCURRENCE 0x1e1a +#define regCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0 +#define regCP_ECC_FIRSTOCCURRENCE_RING0 0x1e1b +#define regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0 +#define regCP_ECC_FIRSTOCCURRENCE_RING1 0x1e1c +#define regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0 +#define regGB_EDC_MODE 0x1e1e +#define regGB_EDC_MODE_BASE_IDX 0 +#define regCP_DEBUG 0x1e1f +#define regCP_DEBUG_BASE_IDX 0 +#define regCP_CPC_DEBUG 0x1e21 +#define regCP_CPC_DEBUG_BASE_IDX 0 +#define regCP_PQ_WPTR_POLL_CNTL 0x1e23 +#define regCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0 +#define regCP_PQ_WPTR_POLL_CNTL1 0x1e24 +#define regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0 +#define regCP_ME1_PIPE0_INT_CNTL 0x1e25 +#define regCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE1_INT_CNTL 0x1e26 +#define regCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE2_INT_CNTL 0x1e27 +#define regCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE3_INT_CNTL 0x1e28 +#define regCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0 +#define regCP_ME2_PIPE0_INT_CNTL 0x1e29 +#define regCP_ME2_PIPE0_INT_CNTL_BASE_IDX 0 +#define regCP_ME2_PIPE1_INT_CNTL 0x1e2a +#define regCP_ME2_PIPE1_INT_CNTL_BASE_IDX 0 +#define regCP_ME2_PIPE2_INT_CNTL 0x1e2b +#define regCP_ME2_PIPE2_INT_CNTL_BASE_IDX 0 +#define regCP_ME2_PIPE3_INT_CNTL 0x1e2c +#define regCP_ME2_PIPE3_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE0_INT_STATUS 0x1e2d +#define regCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0 +#define regCP_ME1_PIPE1_INT_STATUS 0x1e2e +#define regCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0 +#define regCP_ME1_PIPE2_INT_STATUS 0x1e2f +#define regCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0 +#define regCP_ME1_PIPE3_INT_STATUS 0x1e30 +#define regCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0 +#define regCP_ME2_PIPE0_INT_STATUS 0x1e31 +#define regCP_ME2_PIPE0_INT_STATUS_BASE_IDX 0 +#define regCP_ME2_PIPE1_INT_STATUS 0x1e32 +#define regCP_ME2_PIPE1_INT_STATUS_BASE_IDX 0 +#define regCP_ME2_PIPE2_INT_STATUS 0x1e33 +#define regCP_ME2_PIPE2_INT_STATUS_BASE_IDX 0 +#define regCP_ME2_PIPE3_INT_STATUS 0x1e34 +#define regCP_ME2_PIPE3_INT_STATUS_BASE_IDX 0 +#define regCP_GFX_QUEUE_INDEX 0x1e37 +#define regCP_GFX_QUEUE_INDEX_BASE_IDX 0 +#define regCC_GC_EDC_CONFIG 0x1e38 +#define regCC_GC_EDC_CONFIG_BASE_IDX 0 +#define regCP_ME1_PIPE_PRIORITY_CNTS 0x1e39 +#define regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_ME1_PIPE0_PRIORITY 0x1e3a +#define regCP_ME1_PIPE0_PRIORITY_BASE_IDX 0 +#define regCP_ME1_PIPE1_PRIORITY 0x1e3b +#define regCP_ME1_PIPE1_PRIORITY_BASE_IDX 0 +#define regCP_ME1_PIPE2_PRIORITY 0x1e3c +#define regCP_ME1_PIPE2_PRIORITY_BASE_IDX 0 +#define regCP_ME1_PIPE3_PRIORITY 0x1e3d +#define regCP_ME1_PIPE3_PRIORITY_BASE_IDX 0 +#define regCP_ME2_PIPE_PRIORITY_CNTS 0x1e3e +#define regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_ME2_PIPE0_PRIORITY 0x1e3f +#define regCP_ME2_PIPE0_PRIORITY_BASE_IDX 0 +#define regCP_ME2_PIPE1_PRIORITY 0x1e40 +#define regCP_ME2_PIPE1_PRIORITY_BASE_IDX 0 +#define regCP_ME2_PIPE2_PRIORITY 0x1e41 +#define regCP_ME2_PIPE2_PRIORITY_BASE_IDX 0 +#define regCP_ME2_PIPE3_PRIORITY 0x1e42 +#define regCP_ME2_PIPE3_PRIORITY_BASE_IDX 0 +#define regCP_PFP_PRGRM_CNTR_START 0x1e44 +#define regCP_PFP_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_ME_PRGRM_CNTR_START 0x1e45 +#define regCP_ME_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_MEC1_PRGRM_CNTR_START 0x1e46 +#define regCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_MEC2_PRGRM_CNTR_START 0x1e47 +#define regCP_MEC2_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_PFP_INTR_ROUTINE_START 0x1e49 +#define regCP_PFP_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_ME_INTR_ROUTINE_START 0x1e4a +#define regCP_ME_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_MEC1_INTR_ROUTINE_START 0x1e4b +#define regCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_MEC2_INTR_ROUTINE_START 0x1e4c +#define regCP_MEC2_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_CONTEXT_CNTL 0x1e4d +#define regCP_CONTEXT_CNTL_BASE_IDX 0 +#define regCP_MAX_CONTEXT 0x1e4e +#define regCP_MAX_CONTEXT_BASE_IDX 0 +#define regCP_IQ_WAIT_TIME1 0x1e4f +#define regCP_IQ_WAIT_TIME1_BASE_IDX 0 +#define regCP_IQ_WAIT_TIME2 0x1e50 +#define regCP_IQ_WAIT_TIME2_BASE_IDX 0 +#define regCP_RB0_BASE_HI 0x1e51 +#define regCP_RB0_BASE_HI_BASE_IDX 0 +#define regCP_RB1_BASE_HI 0x1e52 +#define regCP_RB1_BASE_HI_BASE_IDX 0 +#define regCP_VMID_RESET 0x1e53 +#define regCP_VMID_RESET_BASE_IDX 0 +#define regCPC_INT_CNTL 0x1e54 +#define regCPC_INT_CNTL_BASE_IDX 0 +#define regCPC_INT_STATUS 0x1e55 +#define regCPC_INT_STATUS_BASE_IDX 0 +#define regCP_VMID_PREEMPT 0x1e56 +#define regCP_VMID_PREEMPT_BASE_IDX 0 +#define regCPC_INT_CNTX_ID 0x1e57 +#define regCPC_INT_CNTX_ID_BASE_IDX 0 +#define regCP_PQ_STATUS 0x1e58 +#define regCP_PQ_STATUS_BASE_IDX 0 +#define regCP_PFP_PRGRM_CNTR_START_HI 0x1e59 +#define regCP_PFP_PRGRM_CNTR_START_HI_BASE_IDX 0 +#define regCP_MAX_DRAW_COUNT 0x1e5c +#define regCP_MAX_DRAW_COUNT_BASE_IDX 0 +#define regCP_MEC1_F32_INT_DIS 0x1e5d +#define regCP_MEC1_F32_INT_DIS_BASE_IDX 0 +#define regCP_MEC2_F32_INT_DIS 0x1e5e +#define regCP_MEC2_F32_INT_DIS_BASE_IDX 0 +#define regCP_VMID_STATUS 0x1e5f +#define regCP_VMID_STATUS_BASE_IDX 0 +#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO 0x1e60 +#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 +#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI 0x1e61 +#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 +#define regCPC_SUSPEND_CTX_SAVE_CONTROL 0x1e62 +#define regCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX 0 +#define regCPC_SUSPEND_CNTL_STACK_OFFSET 0x1e63 +#define regCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX 0 +#define regCPC_SUSPEND_CNTL_STACK_SIZE 0x1e64 +#define regCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX 0 +#define regCPC_SUSPEND_WG_STATE_OFFSET 0x1e65 +#define regCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX 0 +#define regCPC_SUSPEND_CTX_SAVE_SIZE 0x1e66 +#define regCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX 0 +#define regCPC_OS_PIPES 0x1e67 +#define regCPC_OS_PIPES_BASE_IDX 0 +#define regCP_SUSPEND_RESUME_REQ 0x1e68 +#define regCP_SUSPEND_RESUME_REQ_BASE_IDX 0 +#define regCP_SUSPEND_CNTL 0x1e69 +#define regCP_SUSPEND_CNTL_BASE_IDX 0 +#define regCP_IQ_WAIT_TIME3 0x1e6a +#define regCP_IQ_WAIT_TIME3_BASE_IDX 0 +#define regCPC_DDID_BASE_ADDR_LO 0x1e6b +#define regCPC_DDID_BASE_ADDR_LO_BASE_IDX 0 +#define regCP_DDID_BASE_ADDR_LO 0x1e6b +#define regCP_DDID_BASE_ADDR_LO_BASE_IDX 0 +#define regCPC_DDID_BASE_ADDR_HI 0x1e6c +#define regCPC_DDID_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_DDID_BASE_ADDR_HI 0x1e6c +#define regCP_DDID_BASE_ADDR_HI_BASE_IDX 0 +#define regCPC_DDID_CNTL 0x1e6d +#define regCPC_DDID_CNTL_BASE_IDX 0 +#define regCP_DDID_CNTL 0x1e6d +#define regCP_DDID_CNTL_BASE_IDX 0 +#define regCP_GFX_DDID_INFLIGHT_COUNT 0x1e6e +#define regCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX 0 +#define regCP_GFX_DDID_WPTR 0x1e6f +#define regCP_GFX_DDID_WPTR_BASE_IDX 0 +#define regCP_GFX_DDID_RPTR 0x1e70 +#define regCP_GFX_DDID_RPTR_BASE_IDX 0 +#define regCP_GFX_DDID_DELTA_RPT_COUNT 0x1e71 +#define regCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX 0 +#define regCP_GFX_HPD_STATUS0 0x1e72 +#define regCP_GFX_HPD_STATUS0_BASE_IDX 0 +#define regCP_GFX_HPD_CONTROL0 0x1e73 +#define regCP_GFX_HPD_CONTROL0_BASE_IDX 0 +#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO 0x1e74 +#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX 0 +#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI 0x1e75 +#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX 0 +#define regCP_GFX_HPD_OSPRE_FENCE_DATA_LO 0x1e76 +#define regCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX 0 +#define regCP_GFX_HPD_OSPRE_FENCE_DATA_HI 0x1e77 +#define regCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX 0 +#define regCP_GFX_INDEX_MUTEX 0x1e78 +#define regCP_GFX_INDEX_MUTEX_BASE_IDX 0 +#define regCP_ME_PRGRM_CNTR_START_HI 0x1e79 +#define regCP_ME_PRGRM_CNTR_START_HI_BASE_IDX 0 +#define regCP_PFP_INTR_ROUTINE_START_HI 0x1e7a +#define regCP_PFP_INTR_ROUTINE_START_HI_BASE_IDX 0 +#define regCP_ME_INTR_ROUTINE_START_HI 0x1e7b +#define regCP_ME_INTR_ROUTINE_START_HI_BASE_IDX 0 +#define regCP_GFX_MQD_BASE_ADDR 0x1e7e +#define regCP_GFX_MQD_BASE_ADDR_BASE_IDX 0 +#define regCP_GFX_MQD_BASE_ADDR_HI 0x1e7f +#define regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_GFX_HQD_ACTIVE 0x1e80 +#define regCP_GFX_HQD_ACTIVE_BASE_IDX 0 +#define regCP_GFX_HQD_VMID 0x1e81 +#define regCP_GFX_HQD_VMID_BASE_IDX 0 +#define regCP_GFX_HQD_QUEUE_PRIORITY 0x1e84 +#define regCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX 0 +#define regCP_GFX_HQD_QUANTUM 0x1e85 +#define regCP_GFX_HQD_QUANTUM_BASE_IDX 0 +#define regCP_GFX_HQD_BASE 0x1e86 +#define regCP_GFX_HQD_BASE_BASE_IDX 0 +#define regCP_GFX_HQD_BASE_HI 0x1e87 +#define regCP_GFX_HQD_BASE_HI_BASE_IDX 0 +#define regCP_GFX_HQD_RPTR 0x1e88 +#define regCP_GFX_HQD_RPTR_BASE_IDX 0 +#define regCP_GFX_HQD_RPTR_ADDR 0x1e89 +#define regCP_GFX_HQD_RPTR_ADDR_BASE_IDX 0 +#define regCP_GFX_HQD_RPTR_ADDR_HI 0x1e8a +#define regCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB_WPTR_POLL_ADDR_LO 0x1e8b +#define regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regCP_RB_WPTR_POLL_ADDR_HI 0x1e8c +#define regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regCP_RB_DOORBELL_CONTROL 0x1e8d +#define regCP_RB_DOORBELL_CONTROL_BASE_IDX 0 +#define regCP_GFX_HQD_OFFSET 0x1e8e +#define regCP_GFX_HQD_OFFSET_BASE_IDX 0 +#define regCP_GFX_HQD_CNTL 0x1e8f +#define regCP_GFX_HQD_CNTL_BASE_IDX 0 +#define regCP_GFX_HQD_CSMD_RPTR 0x1e90 +#define regCP_GFX_HQD_CSMD_RPTR_BASE_IDX 0 +#define regCP_GFX_HQD_WPTR 0x1e91 +#define regCP_GFX_HQD_WPTR_BASE_IDX 0 +#define regCP_GFX_HQD_WPTR_HI 0x1e92 +#define regCP_GFX_HQD_WPTR_HI_BASE_IDX 0 +#define regCP_GFX_HQD_DEQUEUE_REQUEST 0x1e93 +#define regCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX 0 +#define regCP_GFX_HQD_MAPPED 0x1e94 +#define regCP_GFX_HQD_MAPPED_BASE_IDX 0 +#define regCP_GFX_HQD_QUE_MGR_CONTROL 0x1e95 +#define regCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX 0 +#define regCP_GFX_HQD_IQ_TIMER 0x1e96 +#define regCP_GFX_HQD_IQ_TIMER_BASE_IDX 0 +#define regCP_GFX_HQD_HQ_STATUS0 0x1e98 +#define regCP_GFX_HQD_HQ_STATUS0_BASE_IDX 0 +#define regCP_GFX_HQD_HQ_CONTROL0 0x1e99 +#define regCP_GFX_HQD_HQ_CONTROL0_BASE_IDX 0 +#define regCP_GFX_MQD_CONTROL 0x1e9a +#define regCP_GFX_MQD_CONTROL_BASE_IDX 0 +#define regCP_HQD_GFX_CONTROL 0x1e9f +#define regCP_HQD_GFX_CONTROL_BASE_IDX 0 +#define regCP_HQD_GFX_STATUS 0x1ea0 +#define regCP_HQD_GFX_STATUS_BASE_IDX 0 +#define regCP_DMA_WATCH0_ADDR_LO 0x1ec0 +#define regCP_DMA_WATCH0_ADDR_LO_BASE_IDX 0 +#define regCP_DMA_WATCH0_ADDR_HI 0x1ec1 +#define regCP_DMA_WATCH0_ADDR_HI_BASE_IDX 0 +#define regCP_DMA_WATCH0_MASK 0x1ec2 +#define regCP_DMA_WATCH0_MASK_BASE_IDX 0 +#define regCP_DMA_WATCH0_CNTL 0x1ec3 +#define regCP_DMA_WATCH0_CNTL_BASE_IDX 0 +#define regCP_DMA_WATCH1_ADDR_LO 0x1ec4 +#define regCP_DMA_WATCH1_ADDR_LO_BASE_IDX 0 +#define regCP_DMA_WATCH1_ADDR_HI 0x1ec5 +#define regCP_DMA_WATCH1_ADDR_HI_BASE_IDX 0 +#define regCP_DMA_WATCH1_MASK 0x1ec6 +#define regCP_DMA_WATCH1_MASK_BASE_IDX 0 +#define regCP_DMA_WATCH1_CNTL 0x1ec7 +#define regCP_DMA_WATCH1_CNTL_BASE_IDX 0 +#define regCP_DMA_WATCH2_ADDR_LO 0x1ec8 +#define regCP_DMA_WATCH2_ADDR_LO_BASE_IDX 0 +#define regCP_DMA_WATCH2_ADDR_HI 0x1ec9 +#define regCP_DMA_WATCH2_ADDR_HI_BASE_IDX 0 +#define regCP_DMA_WATCH2_MASK 0x1eca +#define regCP_DMA_WATCH2_MASK_BASE_IDX 0 +#define regCP_DMA_WATCH2_CNTL 0x1ecb +#define regCP_DMA_WATCH2_CNTL_BASE_IDX 0 +#define regCP_DMA_WATCH3_ADDR_LO 0x1ecc +#define regCP_DMA_WATCH3_ADDR_LO_BASE_IDX 0 +#define regCP_DMA_WATCH3_ADDR_HI 0x1ecd +#define regCP_DMA_WATCH3_ADDR_HI_BASE_IDX 0 +#define regCP_DMA_WATCH3_MASK 0x1ece +#define regCP_DMA_WATCH3_MASK_BASE_IDX 0 +#define regCP_DMA_WATCH3_CNTL 0x1ecf +#define regCP_DMA_WATCH3_CNTL_BASE_IDX 0 +#define regCP_DMA_WATCH_STAT_ADDR_LO 0x1ed0 +#define regCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX 0 +#define regCP_DMA_WATCH_STAT_ADDR_HI 0x1ed1 +#define regCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX 0 +#define regCP_DMA_WATCH_STAT 0x1ed2 +#define regCP_DMA_WATCH_STAT_BASE_IDX 0 +#define regCP_PFP_JT_STAT 0x1ed3 +#define regCP_PFP_JT_STAT_BASE_IDX 0 +#define regCP_MEC_JT_STAT 0x1ed5 +#define regCP_MEC_JT_STAT_BASE_IDX 0 +#define regCP_CPC_BUSY_HYSTERESIS 0x1edb +#define regCP_CPC_BUSY_HYSTERESIS_BASE_IDX 0 +#define regCP_CPF_BUSY_HYSTERESIS1 0x1edc +#define regCP_CPF_BUSY_HYSTERESIS1_BASE_IDX 0 +#define regCP_CPF_BUSY_HYSTERESIS2 0x1edd +#define regCP_CPF_BUSY_HYSTERESIS2_BASE_IDX 0 +#define regCP_CPG_BUSY_HYSTERESIS1 0x1ede +#define regCP_CPG_BUSY_HYSTERESIS1_BASE_IDX 0 +#define regCP_CPG_BUSY_HYSTERESIS2 0x1edf +#define regCP_CPG_BUSY_HYSTERESIS2_BASE_IDX 0 +#define regCP_RB_DOORBELL_CLEAR 0x1f28 +#define regCP_RB_DOORBELL_CLEAR_BASE_IDX 0 +#define regCP_RB0_ACTIVE 0x1f40 +#define regCP_RB0_ACTIVE_BASE_IDX 0 +#define regCP_RB_ACTIVE 0x1f40 +#define regCP_RB_ACTIVE_BASE_IDX 0 +#define regCP_RB1_ACTIVE 0x1f41 +#define regCP_RB1_ACTIVE_BASE_IDX 0 +#define regCP_RB_STATUS 0x1f43 +#define regCP_RB_STATUS_BASE_IDX 0 +#define regCPG_RCIU_CAM_INDEX 0x1f44 +#define regCPG_RCIU_CAM_INDEX_BASE_IDX 0 +#define regCPG_RCIU_CAM_DATA 0x1f45 +#define regCPG_RCIU_CAM_DATA_BASE_IDX 0 +#define regCPG_RCIU_CAM_DATA_PHASE0 0x1f45 +#define regCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX 0 +#define regCPG_RCIU_CAM_DATA_PHASE1 0x1f45 +#define regCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX 0 +#define regCPG_RCIU_CAM_DATA_PHASE2 0x1f45 +#define regCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX 0 +#define regCP_GPU_TIMESTAMP_OFFSET_LO 0x1f4c +#define regCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX 0 +#define regCP_GPU_TIMESTAMP_OFFSET_HI 0x1f4d +#define regCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX 0 +#define regCP_SDMA_DMA_DONE 0x1f4e +#define regCP_SDMA_DMA_DONE_BASE_IDX 0 +#define regCP_PFP_SDMA_CS 0x1f4f +#define regCP_PFP_SDMA_CS_BASE_IDX 0 +#define regCP_ME_SDMA_CS 0x1f50 +#define regCP_ME_SDMA_CS_BASE_IDX 0 +#define regCPF_GCR_CNTL 0x1f53 +#define regCPF_GCR_CNTL_BASE_IDX 0 +#define regCPG_UTCL1_STATUS 0x1f54 +#define regCPG_UTCL1_STATUS_BASE_IDX 0 +#define regCPC_UTCL1_STATUS 0x1f55 +#define regCPC_UTCL1_STATUS_BASE_IDX 0 +#define regCPF_UTCL1_STATUS 0x1f56 +#define regCPF_UTCL1_STATUS_BASE_IDX 0 +#define regCP_SD_CNTL 0x1f57 +#define regCP_SD_CNTL_BASE_IDX 0 +#define regCP_SOFT_RESET_CNTL 0x1f59 +#define regCP_SOFT_RESET_CNTL_BASE_IDX 0 +#define regCP_CPC_GFX_CNTL 0x1f5a +#define regCP_CPC_GFX_CNTL_BASE_IDX 0 + + +// addressBlock: gc_spipdec +// base address: 0xc700 +#define regSPI_ARB_PRIORITY 0x1f60 +#define regSPI_ARB_PRIORITY_BASE_IDX 0 +#define regSPI_ARB_CYCLES_0 0x1f61 +#define regSPI_ARB_CYCLES_0_BASE_IDX 0 +#define regSPI_ARB_CYCLES_1 0x1f62 +#define regSPI_ARB_CYCLES_1_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_GFX 0x1f67 +#define regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_HP3D 0x1f68 +#define regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS0 0x1f69 +#define regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS1 0x1f6a +#define regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS2 0x1f6b +#define regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS3 0x1f6c +#define regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS4 0x1f6d +#define regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS5 0x1f6e +#define regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS6 0x1f6f +#define regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS7 0x1f70 +#define regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0 +#define regSPI_USER_ACCUM_VMID_CNTL 0x1f71 +#define regSPI_USER_ACCUM_VMID_CNTL_BASE_IDX 0 +#define regSPI_GDBG_PER_VMID_CNTL 0x1f72 +#define regSPI_GDBG_PER_VMID_CNTL_BASE_IDX 0 +#define regSPI_COMPUTE_QUEUE_RESET 0x1f73 +#define regSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0 +#define regSPI_COMPUTE_WF_CTX_SAVE 0x1f74 +#define regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX 0 + + +// addressBlock: gc_cpphqddec +// base address: 0xc800 +#define regCP_HPD_UTCL1_CNTL 0x1fa3 +#define regCP_HPD_UTCL1_CNTL_BASE_IDX 0 +#define regCP_HPD_UTCL1_ERROR 0x1fa7 +#define regCP_HPD_UTCL1_ERROR_BASE_IDX 0 +#define regCP_HPD_UTCL1_ERROR_ADDR 0x1fa8 +#define regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0 +#define regCP_MQD_BASE_ADDR 0x1fa9 +#define regCP_MQD_BASE_ADDR_BASE_IDX 0 +#define regCP_MQD_BASE_ADDR_HI 0x1faa +#define regCP_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_ACTIVE 0x1fab +#define regCP_HQD_ACTIVE_BASE_IDX 0 +#define regCP_HQD_VMID 0x1fac +#define regCP_HQD_VMID_BASE_IDX 0 +#define regCP_HQD_PERSISTENT_STATE 0x1fad +#define regCP_HQD_PERSISTENT_STATE_BASE_IDX 0 +#define regCP_HQD_PIPE_PRIORITY 0x1fae +#define regCP_HQD_PIPE_PRIORITY_BASE_IDX 0 +#define regCP_HQD_QUEUE_PRIORITY 0x1faf +#define regCP_HQD_QUEUE_PRIORITY_BASE_IDX 0 +#define regCP_HQD_QUANTUM 0x1fb0 +#define regCP_HQD_QUANTUM_BASE_IDX 0 +#define regCP_HQD_PQ_BASE 0x1fb1 +#define regCP_HQD_PQ_BASE_BASE_IDX 0 +#define regCP_HQD_PQ_BASE_HI 0x1fb2 +#define regCP_HQD_PQ_BASE_HI_BASE_IDX 0 +#define regCP_HQD_PQ_RPTR 0x1fb3 +#define regCP_HQD_PQ_RPTR_BASE_IDX 0 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR 0x1fb4 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1fb5 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_POLL_ADDR 0x1fb6 +#define regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1fb7 +#define regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_PQ_DOORBELL_CONTROL 0x1fb8 +#define regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0 +#define regCP_HQD_PQ_CONTROL 0x1fba +#define regCP_HQD_PQ_CONTROL_BASE_IDX 0 +#define regCP_HQD_IB_BASE_ADDR 0x1fbb +#define regCP_HQD_IB_BASE_ADDR_BASE_IDX 0 +#define regCP_HQD_IB_BASE_ADDR_HI 0x1fbc +#define regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_IB_RPTR 0x1fbd +#define regCP_HQD_IB_RPTR_BASE_IDX 0 +#define regCP_HQD_IB_CONTROL 0x1fbe +#define regCP_HQD_IB_CONTROL_BASE_IDX 0 +#define regCP_HQD_IQ_TIMER 0x1fbf +#define regCP_HQD_IQ_TIMER_BASE_IDX 0 +#define regCP_HQD_IQ_RPTR 0x1fc0 +#define regCP_HQD_IQ_RPTR_BASE_IDX 0 +#define regCP_HQD_DEQUEUE_REQUEST 0x1fc1 +#define regCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0 +#define regCP_HQD_DMA_OFFLOAD 0x1fc2 +#define regCP_HQD_DMA_OFFLOAD_BASE_IDX 0 +#define regCP_HQD_OFFLOAD 0x1fc2 +#define regCP_HQD_OFFLOAD_BASE_IDX 0 +#define regCP_HQD_SEMA_CMD 0x1fc3 +#define regCP_HQD_SEMA_CMD_BASE_IDX 0 +#define regCP_HQD_MSG_TYPE 0x1fc4 +#define regCP_HQD_MSG_TYPE_BASE_IDX 0 +#define regCP_HQD_ATOMIC0_PREOP_LO 0x1fc5 +#define regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0 +#define regCP_HQD_ATOMIC0_PREOP_HI 0x1fc6 +#define regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0 +#define regCP_HQD_ATOMIC1_PREOP_LO 0x1fc7 +#define regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0 +#define regCP_HQD_ATOMIC1_PREOP_HI 0x1fc8 +#define regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0 +#define regCP_HQD_HQ_SCHEDULER0 0x1fc9 +#define regCP_HQD_HQ_SCHEDULER0_BASE_IDX 0 +#define regCP_HQD_HQ_STATUS0 0x1fc9 +#define regCP_HQD_HQ_STATUS0_BASE_IDX 0 +#define regCP_HQD_HQ_CONTROL0 0x1fca +#define regCP_HQD_HQ_CONTROL0_BASE_IDX 0 +#define regCP_HQD_HQ_SCHEDULER1 0x1fca +#define regCP_HQD_HQ_SCHEDULER1_BASE_IDX 0 +#define regCP_MQD_CONTROL 0x1fcb +#define regCP_MQD_CONTROL_BASE_IDX 0 +#define regCP_HQD_HQ_STATUS1 0x1fcc +#define regCP_HQD_HQ_STATUS1_BASE_IDX 0 +#define regCP_HQD_HQ_CONTROL1 0x1fcd +#define regCP_HQD_HQ_CONTROL1_BASE_IDX 0 +#define regCP_HQD_EOP_BASE_ADDR 0x1fce +#define regCP_HQD_EOP_BASE_ADDR_BASE_IDX 0 +#define regCP_HQD_EOP_BASE_ADDR_HI 0x1fcf +#define regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_EOP_CONTROL 0x1fd0 +#define regCP_HQD_EOP_CONTROL_BASE_IDX 0 +#define regCP_HQD_EOP_RPTR 0x1fd1 +#define regCP_HQD_EOP_RPTR_BASE_IDX 0 +#define regCP_HQD_EOP_WPTR 0x1fd2 +#define regCP_HQD_EOP_WPTR_BASE_IDX 0 +#define regCP_HQD_EOP_EVENTS 0x1fd3 +#define regCP_HQD_EOP_EVENTS_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x1fd4 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x1fd5 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_CONTROL 0x1fd6 +#define regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0 +#define regCP_HQD_CNTL_STACK_OFFSET 0x1fd7 +#define regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0 +#define regCP_HQD_CNTL_STACK_SIZE 0x1fd8 +#define regCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0 +#define regCP_HQD_WG_STATE_OFFSET 0x1fd9 +#define regCP_HQD_WG_STATE_OFFSET_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_SIZE 0x1fda +#define regCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0 +#define regCP_HQD_GDS_RESOURCE_STATE 0x1fdb +#define regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0 +#define regCP_HQD_ERROR 0x1fdc +#define regCP_HQD_ERROR_BASE_IDX 0 +#define regCP_HQD_EOP_WPTR_MEM 0x1fdd +#define regCP_HQD_EOP_WPTR_MEM_BASE_IDX 0 +#define regCP_HQD_AQL_CONTROL 0x1fde +#define regCP_HQD_AQL_CONTROL_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_LO 0x1fdf +#define regCP_HQD_PQ_WPTR_LO_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_HI 0x1fe0 +#define regCP_HQD_PQ_WPTR_HI_BASE_IDX 0 +#define regCP_HQD_SUSPEND_CNTL_STACK_OFFSET 0x1fe1 +#define regCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX 0 +#define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT 0x1fe2 +#define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX 0 +#define regCP_HQD_SUSPEND_WG_STATE_OFFSET 0x1fe3 +#define regCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX 0 +#define regCP_HQD_DDID_RPTR 0x1fe4 +#define regCP_HQD_DDID_RPTR_BASE_IDX 0 +#define regCP_HQD_DDID_WPTR 0x1fe5 +#define regCP_HQD_DDID_WPTR_BASE_IDX 0 +#define regCP_HQD_DDID_INFLIGHT_COUNT 0x1fe6 +#define regCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX 0 +#define regCP_HQD_DDID_DELTA_RPT_COUNT 0x1fe7 +#define regCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX 0 +#define regCP_HQD_DEQUEUE_STATUS 0x1fe8 +#define regCP_HQD_DEQUEUE_STATUS_BASE_IDX 0 + + +// addressBlock: gc_tcpdec +// base address: 0xca80 +#define regTCP_WATCH0_ADDR_H 0x2048 +#define regTCP_WATCH0_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH0_ADDR_L 0x2049 +#define regTCP_WATCH0_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH0_CNTL 0x204a +#define regTCP_WATCH0_CNTL_BASE_IDX 0 +#define regTCP_WATCH1_ADDR_H 0x204b +#define regTCP_WATCH1_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH1_ADDR_L 0x204c +#define regTCP_WATCH1_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH1_CNTL 0x204d +#define regTCP_WATCH1_CNTL_BASE_IDX 0 +#define regTCP_WATCH2_ADDR_H 0x204e +#define regTCP_WATCH2_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH2_ADDR_L 0x204f +#define regTCP_WATCH2_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH2_CNTL 0x2050 +#define regTCP_WATCH2_CNTL_BASE_IDX 0 +#define regTCP_WATCH3_ADDR_H 0x2051 +#define regTCP_WATCH3_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH3_ADDR_L 0x2052 +#define regTCP_WATCH3_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH3_CNTL 0x2053 +#define regTCP_WATCH3_CNTL_BASE_IDX 0 + + +// addressBlock: gc_gdspdec +// base address: 0xcc00 +#define regGDS_VMID0_BASE 0x20a0 +#define regGDS_VMID0_BASE_BASE_IDX 0 +#define regGDS_VMID0_SIZE 0x20a1 +#define regGDS_VMID0_SIZE_BASE_IDX 0 +#define regGDS_VMID1_BASE 0x20a2 +#define regGDS_VMID1_BASE_BASE_IDX 0 +#define regGDS_VMID1_SIZE 0x20a3 +#define regGDS_VMID1_SIZE_BASE_IDX 0 +#define regGDS_VMID2_BASE 0x20a4 +#define regGDS_VMID2_BASE_BASE_IDX 0 +#define regGDS_VMID2_SIZE 0x20a5 +#define regGDS_VMID2_SIZE_BASE_IDX 0 +#define regGDS_VMID3_BASE 0x20a6 +#define regGDS_VMID3_BASE_BASE_IDX 0 +#define regGDS_VMID3_SIZE 0x20a7 +#define regGDS_VMID3_SIZE_BASE_IDX 0 +#define regGDS_VMID4_BASE 0x20a8 +#define regGDS_VMID4_BASE_BASE_IDX 0 +#define regGDS_VMID4_SIZE 0x20a9 +#define regGDS_VMID4_SIZE_BASE_IDX 0 +#define regGDS_VMID5_BASE 0x20aa +#define regGDS_VMID5_BASE_BASE_IDX 0 +#define regGDS_VMID5_SIZE 0x20ab +#define regGDS_VMID5_SIZE_BASE_IDX 0 +#define regGDS_VMID6_BASE 0x20ac +#define regGDS_VMID6_BASE_BASE_IDX 0 +#define regGDS_VMID6_SIZE 0x20ad +#define regGDS_VMID6_SIZE_BASE_IDX 0 +#define regGDS_VMID7_BASE 0x20ae +#define regGDS_VMID7_BASE_BASE_IDX 0 +#define regGDS_VMID7_SIZE 0x20af +#define regGDS_VMID7_SIZE_BASE_IDX 0 +#define regGDS_VMID8_BASE 0x20b0 +#define regGDS_VMID8_BASE_BASE_IDX 0 +#define regGDS_VMID8_SIZE 0x20b1 +#define regGDS_VMID8_SIZE_BASE_IDX 0 +#define regGDS_VMID9_BASE 0x20b2 +#define regGDS_VMID9_BASE_BASE_IDX 0 +#define regGDS_VMID9_SIZE 0x20b3 +#define regGDS_VMID9_SIZE_BASE_IDX 0 +#define regGDS_VMID10_BASE 0x20b4 +#define regGDS_VMID10_BASE_BASE_IDX 0 +#define regGDS_VMID10_SIZE 0x20b5 +#define regGDS_VMID10_SIZE_BASE_IDX 0 +#define regGDS_VMID11_BASE 0x20b6 +#define regGDS_VMID11_BASE_BASE_IDX 0 +#define regGDS_VMID11_SIZE 0x20b7 +#define regGDS_VMID11_SIZE_BASE_IDX 0 +#define regGDS_VMID12_BASE 0x20b8 +#define regGDS_VMID12_BASE_BASE_IDX 0 +#define regGDS_VMID12_SIZE 0x20b9 +#define regGDS_VMID12_SIZE_BASE_IDX 0 +#define regGDS_VMID13_BASE 0x20ba +#define regGDS_VMID13_BASE_BASE_IDX 0 +#define regGDS_VMID13_SIZE 0x20bb +#define regGDS_VMID13_SIZE_BASE_IDX 0 +#define regGDS_VMID14_BASE 0x20bc +#define regGDS_VMID14_BASE_BASE_IDX 0 +#define regGDS_VMID14_SIZE 0x20bd +#define regGDS_VMID14_SIZE_BASE_IDX 0 +#define regGDS_VMID15_BASE 0x20be +#define regGDS_VMID15_BASE_BASE_IDX 0 +#define regGDS_VMID15_SIZE 0x20bf +#define regGDS_VMID15_SIZE_BASE_IDX 0 +#define regGDS_GWS_VMID0 0x20c0 +#define regGDS_GWS_VMID0_BASE_IDX 0 +#define regGDS_GWS_VMID1 0x20c1 +#define regGDS_GWS_VMID1_BASE_IDX 0 +#define regGDS_GWS_VMID2 0x20c2 +#define regGDS_GWS_VMID2_BASE_IDX 0 +#define regGDS_GWS_VMID3 0x20c3 +#define regGDS_GWS_VMID3_BASE_IDX 0 +#define regGDS_GWS_VMID4 0x20c4 +#define regGDS_GWS_VMID4_BASE_IDX 0 +#define regGDS_GWS_VMID5 0x20c5 +#define regGDS_GWS_VMID5_BASE_IDX 0 +#define regGDS_GWS_VMID6 0x20c6 +#define regGDS_GWS_VMID6_BASE_IDX 0 +#define regGDS_GWS_VMID7 0x20c7 +#define regGDS_GWS_VMID7_BASE_IDX 0 +#define regGDS_GWS_VMID8 0x20c8 +#define regGDS_GWS_VMID8_BASE_IDX 0 +#define regGDS_GWS_VMID9 0x20c9 +#define regGDS_GWS_VMID9_BASE_IDX 0 +#define regGDS_GWS_VMID10 0x20ca +#define regGDS_GWS_VMID10_BASE_IDX 0 +#define regGDS_GWS_VMID11 0x20cb +#define regGDS_GWS_VMID11_BASE_IDX 0 +#define regGDS_GWS_VMID12 0x20cc +#define regGDS_GWS_VMID12_BASE_IDX 0 +#define regGDS_GWS_VMID13 0x20cd +#define regGDS_GWS_VMID13_BASE_IDX 0 +#define regGDS_GWS_VMID14 0x20ce +#define regGDS_GWS_VMID14_BASE_IDX 0 +#define regGDS_GWS_VMID15 0x20cf +#define regGDS_GWS_VMID15_BASE_IDX 0 +#define regGDS_OA_VMID0 0x20d0 +#define regGDS_OA_VMID0_BASE_IDX 0 +#define regGDS_OA_VMID1 0x20d1 +#define regGDS_OA_VMID1_BASE_IDX 0 +#define regGDS_OA_VMID2 0x20d2 +#define regGDS_OA_VMID2_BASE_IDX 0 +#define regGDS_OA_VMID3 0x20d3 +#define regGDS_OA_VMID3_BASE_IDX 0 +#define regGDS_OA_VMID4 0x20d4 +#define regGDS_OA_VMID4_BASE_IDX 0 +#define regGDS_OA_VMID5 0x20d5 +#define regGDS_OA_VMID5_BASE_IDX 0 +#define regGDS_OA_VMID6 0x20d6 +#define regGDS_OA_VMID6_BASE_IDX 0 +#define regGDS_OA_VMID7 0x20d7 +#define regGDS_OA_VMID7_BASE_IDX 0 +#define regGDS_OA_VMID8 0x20d8 +#define regGDS_OA_VMID8_BASE_IDX 0 +#define regGDS_OA_VMID9 0x20d9 +#define regGDS_OA_VMID9_BASE_IDX 0 +#define regGDS_OA_VMID10 0x20da +#define regGDS_OA_VMID10_BASE_IDX 0 +#define regGDS_OA_VMID11 0x20db +#define regGDS_OA_VMID11_BASE_IDX 0 +#define regGDS_OA_VMID12 0x20dc +#define regGDS_OA_VMID12_BASE_IDX 0 +#define regGDS_OA_VMID13 0x20dd +#define regGDS_OA_VMID13_BASE_IDX 0 +#define regGDS_OA_VMID14 0x20de +#define regGDS_OA_VMID14_BASE_IDX 0 +#define regGDS_OA_VMID15 0x20df +#define regGDS_OA_VMID15_BASE_IDX 0 +#define regGDS_GWS_RESET0 0x20e4 +#define regGDS_GWS_RESET0_BASE_IDX 0 +#define regGDS_GWS_RESET1 0x20e5 +#define regGDS_GWS_RESET1_BASE_IDX 0 +#define regGDS_GWS_RESOURCE_RESET 0x20e6 +#define regGDS_GWS_RESOURCE_RESET_BASE_IDX 0 +#define regGDS_COMPUTE_MAX_WAVE_ID 0x20e8 +#define regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 0 +#define regGDS_OA_RESET_MASK 0x20e9 +#define regGDS_OA_RESET_MASK_BASE_IDX 0 +#define regGDS_OA_RESET 0x20ea +#define regGDS_OA_RESET_BASE_IDX 0 +#define regGDS_CS_CTXSW_STATUS 0x20ed +#define regGDS_CS_CTXSW_STATUS_BASE_IDX 0 +#define regGDS_CS_CTXSW_CNT0 0x20ee +#define regGDS_CS_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_CS_CTXSW_CNT1 0x20ef +#define regGDS_CS_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_CS_CTXSW_CNT2 0x20f0 +#define regGDS_CS_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_CS_CTXSW_CNT3 0x20f1 +#define regGDS_CS_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_GFX_CTXSW_STATUS 0x20f2 +#define regGDS_GFX_CTXSW_STATUS_BASE_IDX 0 +#define regGDS_PS_CTXSW_CNT0 0x20f7 +#define regGDS_PS_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_PS_CTXSW_CNT1 0x20f8 +#define regGDS_PS_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_PS_CTXSW_CNT2 0x20f9 +#define regGDS_PS_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_PS_CTXSW_CNT3 0x20fa +#define regGDS_PS_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_PS_CTXSW_IDX 0x20fb +#define regGDS_PS_CTXSW_IDX_BASE_IDX 0 +#define regGDS_GS_CTXSW_CNT0 0x2117 +#define regGDS_GS_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_GS_CTXSW_CNT1 0x2118 +#define regGDS_GS_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_GS_CTXSW_CNT2 0x2119 +#define regGDS_GS_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_GS_CTXSW_CNT3 0x211a +#define regGDS_GS_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_MEMORY_CLEAN 0x211f +#define regGDS_MEMORY_CLEAN_BASE_IDX 0 + + +// addressBlock: gc_gusdec +// base address: 0x33000 +#define regGUS_IO_RD_COMBINE_FLUSH 0x2c00 +#define regGUS_IO_RD_COMBINE_FLUSH_BASE_IDX 1 +#define regGUS_IO_WR_COMBINE_FLUSH 0x2c01 +#define regGUS_IO_WR_COMBINE_FLUSH_BASE_IDX 1 +#define regGUS_IO_RD_PRI_AGE_RATE 0x2c02 +#define regGUS_IO_RD_PRI_AGE_RATE_BASE_IDX 1 +#define regGUS_IO_WR_PRI_AGE_RATE 0x2c03 +#define regGUS_IO_WR_PRI_AGE_RATE_BASE_IDX 1 +#define regGUS_IO_RD_PRI_AGE_COEFF 0x2c04 +#define regGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX 1 +#define regGUS_IO_WR_PRI_AGE_COEFF 0x2c05 +#define regGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX 1 +#define regGUS_IO_RD_PRI_QUEUING 0x2c06 +#define regGUS_IO_RD_PRI_QUEUING_BASE_IDX 1 +#define regGUS_IO_WR_PRI_QUEUING 0x2c07 +#define regGUS_IO_WR_PRI_QUEUING_BASE_IDX 1 +#define regGUS_IO_RD_PRI_FIXED 0x2c08 +#define regGUS_IO_RD_PRI_FIXED_BASE_IDX 1 +#define regGUS_IO_WR_PRI_FIXED 0x2c09 +#define regGUS_IO_WR_PRI_FIXED_BASE_IDX 1 +#define regGUS_IO_RD_PRI_URGENCY_COEFF 0x2c0a +#define regGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX 1 +#define regGUS_IO_WR_PRI_URGENCY_COEFF 0x2c0b +#define regGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX 1 +#define regGUS_IO_RD_PRI_URGENCY_MODE 0x2c0c +#define regGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX 1 +#define regGUS_IO_WR_PRI_URGENCY_MODE 0x2c0d +#define regGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX 1 +#define regGUS_IO_RD_PRI_QUANT_PRI1 0x2c0e +#define regGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define regGUS_IO_RD_PRI_QUANT_PRI2 0x2c0f +#define regGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define regGUS_IO_RD_PRI_QUANT_PRI3 0x2c10 +#define regGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define regGUS_IO_RD_PRI_QUANT_PRI4 0x2c11 +#define regGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX 1 +#define regGUS_IO_WR_PRI_QUANT_PRI1 0x2c12 +#define regGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define regGUS_IO_WR_PRI_QUANT_PRI2 0x2c13 +#define regGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define regGUS_IO_WR_PRI_QUANT_PRI3 0x2c14 +#define regGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define regGUS_IO_WR_PRI_QUANT_PRI4 0x2c15 +#define regGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX 1 +#define regGUS_IO_RD_PRI_QUANT1_PRI1 0x2c16 +#define regGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX 1 +#define regGUS_IO_RD_PRI_QUANT1_PRI2 0x2c17 +#define regGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX 1 +#define regGUS_IO_RD_PRI_QUANT1_PRI3 0x2c18 +#define regGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX 1 +#define regGUS_IO_RD_PRI_QUANT1_PRI4 0x2c19 +#define regGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX 1 +#define regGUS_IO_WR_PRI_QUANT1_PRI1 0x2c1a +#define regGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX 1 +#define regGUS_IO_WR_PRI_QUANT1_PRI2 0x2c1b +#define regGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX 1 +#define regGUS_IO_WR_PRI_QUANT1_PRI3 0x2c1c +#define regGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX 1 +#define regGUS_IO_WR_PRI_QUANT1_PRI4 0x2c1d +#define regGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX 1 +#define regGUS_DRAM_COMBINE_FLUSH 0x2c1e +#define regGUS_DRAM_COMBINE_FLUSH_BASE_IDX 1 +#define regGUS_DRAM_COMBINE_RD_WR_EN 0x2c1f +#define regGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX 1 +#define regGUS_DRAM_PRI_AGE_RATE 0x2c20 +#define regGUS_DRAM_PRI_AGE_RATE_BASE_IDX 1 +#define regGUS_DRAM_PRI_AGE_COEFF 0x2c21 +#define regGUS_DRAM_PRI_AGE_COEFF_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUEUING 0x2c22 +#define regGUS_DRAM_PRI_QUEUING_BASE_IDX 1 +#define regGUS_DRAM_PRI_FIXED 0x2c23 +#define regGUS_DRAM_PRI_FIXED_BASE_IDX 1 +#define regGUS_DRAM_PRI_URGENCY_COEFF 0x2c24 +#define regGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX 1 +#define regGUS_DRAM_PRI_URGENCY_MODE 0x2c25 +#define regGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUANT_PRI1 0x2c26 +#define regGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUANT_PRI2 0x2c27 +#define regGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUANT_PRI3 0x2c28 +#define regGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUANT_PRI4 0x2c29 +#define regGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUANT_PRI5 0x2c2a +#define regGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUANT1_PRI1 0x2c2b +#define regGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUANT1_PRI2 0x2c2c +#define regGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUANT1_PRI3 0x2c2d +#define regGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUANT1_PRI4 0x2c2e +#define regGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUANT1_PRI5 0x2c2f +#define regGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX 1 +#define regGUS_IO_GROUP_BURST 0x2c30 +#define regGUS_IO_GROUP_BURST_BASE_IDX 1 +#define regGUS_DRAM_GROUP_BURST 0x2c31 +#define regGUS_DRAM_GROUP_BURST_BASE_IDX 1 +#define regGUS_SDP_ARB_FINAL 0x2c32 +#define regGUS_SDP_ARB_FINAL_BASE_IDX 1 +#define regGUS_SDP_QOS_VC_PRIORITY 0x2c33 +#define regGUS_SDP_QOS_VC_PRIORITY_BASE_IDX 1 +#define regGUS_SDP_CREDITS 0x2c34 +#define regGUS_SDP_CREDITS_BASE_IDX 1 +#define regGUS_SDP_TAG_RESERVE0 0x2c35 +#define regGUS_SDP_TAG_RESERVE0_BASE_IDX 1 +#define regGUS_SDP_TAG_RESERVE1 0x2c36 +#define regGUS_SDP_TAG_RESERVE1_BASE_IDX 1 +#define regGUS_SDP_VCC_RESERVE0 0x2c37 +#define regGUS_SDP_VCC_RESERVE0_BASE_IDX 1 +#define regGUS_SDP_VCC_RESERVE1 0x2c38 +#define regGUS_SDP_VCC_RESERVE1_BASE_IDX 1 +#define regGUS_SDP_VCD_RESERVE0 0x2c39 +#define regGUS_SDP_VCD_RESERVE0_BASE_IDX 1 +#define regGUS_SDP_VCD_RESERVE1 0x2c3a +#define regGUS_SDP_VCD_RESERVE1_BASE_IDX 1 +#define regGUS_SDP_REQ_CNTL 0x2c3b +#define regGUS_SDP_REQ_CNTL_BASE_IDX 1 +#define regGUS_MISC 0x2c3c +#define regGUS_MISC_BASE_IDX 1 +#define regGUS_LATENCY_SAMPLING 0x2c3d +#define regGUS_LATENCY_SAMPLING_BASE_IDX 1 +#define regGUS_ERR_STATUS 0x2c3e +#define regGUS_ERR_STATUS_BASE_IDX 1 +#define regGUS_MISC2 0x2c3f +#define regGUS_MISC2_BASE_IDX 1 +#define regGUS_SDP_ENABLE 0x2c45 +#define regGUS_SDP_ENABLE_BASE_IDX 1 +#define regGUS_L1_CH0_CMD_IN 0x2c46 +#define regGUS_L1_CH0_CMD_IN_BASE_IDX 1 +#define regGUS_L1_CH0_CMD_OUT 0x2c47 +#define regGUS_L1_CH0_CMD_OUT_BASE_IDX 1 +#define regGUS_L1_CH0_DATA_IN 0x2c48 +#define regGUS_L1_CH0_DATA_IN_BASE_IDX 1 +#define regGUS_L1_CH0_DATA_OUT 0x2c49 +#define regGUS_L1_CH0_DATA_OUT_BASE_IDX 1 +#define regGUS_L1_CH0_DATA_U_IN 0x2c4a +#define regGUS_L1_CH0_DATA_U_IN_BASE_IDX 1 +#define regGUS_L1_CH0_DATA_U_OUT 0x2c4b +#define regGUS_L1_CH0_DATA_U_OUT_BASE_IDX 1 +#define regGUS_L1_CH1_CMD_IN 0x2c4c +#define regGUS_L1_CH1_CMD_IN_BASE_IDX 1 +#define regGUS_L1_CH1_CMD_OUT 0x2c4d +#define regGUS_L1_CH1_CMD_OUT_BASE_IDX 1 +#define regGUS_L1_CH1_DATA_IN 0x2c4e +#define regGUS_L1_CH1_DATA_IN_BASE_IDX 1 +#define regGUS_L1_CH1_DATA_OUT 0x2c4f +#define regGUS_L1_CH1_DATA_OUT_BASE_IDX 1 +#define regGUS_L1_CH1_DATA_U_IN 0x2c50 +#define regGUS_L1_CH1_DATA_U_IN_BASE_IDX 1 +#define regGUS_L1_CH1_DATA_U_OUT 0x2c51 +#define regGUS_L1_CH1_DATA_U_OUT_BASE_IDX 1 +#define regGUS_L1_SA0_CMD_IN 0x2c52 +#define regGUS_L1_SA0_CMD_IN_BASE_IDX 1 +#define regGUS_L1_SA0_CMD_OUT 0x2c53 +#define regGUS_L1_SA0_CMD_OUT_BASE_IDX 1 +#define regGUS_L1_SA0_DATA_IN 0x2c54 +#define regGUS_L1_SA0_DATA_IN_BASE_IDX 1 +#define regGUS_L1_SA0_DATA_OUT 0x2c55 +#define regGUS_L1_SA0_DATA_OUT_BASE_IDX 1 +#define regGUS_L1_SA0_DATA_U_IN 0x2c56 +#define regGUS_L1_SA0_DATA_U_IN_BASE_IDX 1 +#define regGUS_L1_SA0_DATA_U_OUT 0x2c57 +#define regGUS_L1_SA0_DATA_U_OUT_BASE_IDX 1 +#define regGUS_L1_SA1_CMD_IN 0x2c58 +#define regGUS_L1_SA1_CMD_IN_BASE_IDX 1 +#define regGUS_L1_SA1_CMD_OUT 0x2c59 +#define regGUS_L1_SA1_CMD_OUT_BASE_IDX 1 +#define regGUS_L1_SA1_DATA_IN 0x2c5a +#define regGUS_L1_SA1_DATA_IN_BASE_IDX 1 +#define regGUS_L1_SA1_DATA_OUT 0x2c5b +#define regGUS_L1_SA1_DATA_OUT_BASE_IDX 1 +#define regGUS_L1_SA1_DATA_U_IN 0x2c5c +#define regGUS_L1_SA1_DATA_U_IN_BASE_IDX 1 +#define regGUS_L1_SA1_DATA_U_OUT 0x2c5d +#define regGUS_L1_SA1_DATA_U_OUT_BASE_IDX 1 +#define regGUS_L1_SA2_CMD_IN 0x2c5e +#define regGUS_L1_SA2_CMD_IN_BASE_IDX 1 +#define regGUS_L1_SA2_CMD_OUT 0x2c5f +#define regGUS_L1_SA2_CMD_OUT_BASE_IDX 1 +#define regGUS_L1_SA2_DATA_IN 0x2c60 +#define regGUS_L1_SA2_DATA_IN_BASE_IDX 1 +#define regGUS_L1_SA2_DATA_OUT 0x2c61 +#define regGUS_L1_SA2_DATA_OUT_BASE_IDX 1 +#define regGUS_L1_SA2_DATA_U_IN 0x2c62 +#define regGUS_L1_SA2_DATA_U_IN_BASE_IDX 1 +#define regGUS_L1_SA2_DATA_U_OUT 0x2c63 +#define regGUS_L1_SA2_DATA_U_OUT_BASE_IDX 1 +#define regGUS_L1_SA3_CMD_IN 0x2c64 +#define regGUS_L1_SA3_CMD_IN_BASE_IDX 1 +#define regGUS_L1_SA3_CMD_OUT 0x2c65 +#define regGUS_L1_SA3_CMD_OUT_BASE_IDX 1 +#define regGUS_L1_SA3_DATA_IN 0x2c66 +#define regGUS_L1_SA3_DATA_IN_BASE_IDX 1 +#define regGUS_L1_SA3_DATA_OUT 0x2c67 +#define regGUS_L1_SA3_DATA_OUT_BASE_IDX 1 +#define regGUS_L1_SA3_DATA_U_IN 0x2c68 +#define regGUS_L1_SA3_DATA_U_IN_BASE_IDX 1 +#define regGUS_L1_SA3_DATA_U_OUT 0x2c69 +#define regGUS_L1_SA3_DATA_U_OUT_BASE_IDX 1 +#define regGUS_MISC3 0x2c6a +#define regGUS_MISC3_BASE_IDX 1 +#define regGUS_WRRSP_FIFO_CNTL 0x2c6b +#define regGUS_WRRSP_FIFO_CNTL_BASE_IDX 1 + + +// addressBlock: gc_gfxdec0 +// base address: 0x28000 +#define regDB_RENDER_CONTROL 0x0000 +#define regDB_RENDER_CONTROL_BASE_IDX 1 +#define regDB_COUNT_CONTROL 0x0001 +#define regDB_COUNT_CONTROL_BASE_IDX 1 +#define regDB_DEPTH_VIEW 0x0002 +#define regDB_DEPTH_VIEW_BASE_IDX 1 +#define regDB_RENDER_OVERRIDE 0x0003 +#define regDB_RENDER_OVERRIDE_BASE_IDX 1 +#define regDB_RENDER_OVERRIDE2 0x0004 +#define regDB_RENDER_OVERRIDE2_BASE_IDX 1 +#define regDB_HTILE_DATA_BASE 0x0005 +#define regDB_HTILE_DATA_BASE_BASE_IDX 1 +#define regDB_DEPTH_SIZE_XY 0x0007 +#define regDB_DEPTH_SIZE_XY_BASE_IDX 1 +#define regDB_DEPTH_BOUNDS_MIN 0x0008 +#define regDB_DEPTH_BOUNDS_MIN_BASE_IDX 1 +#define regDB_DEPTH_BOUNDS_MAX 0x0009 +#define regDB_DEPTH_BOUNDS_MAX_BASE_IDX 1 +#define regDB_STENCIL_CLEAR 0x000a +#define regDB_STENCIL_CLEAR_BASE_IDX 1 +#define regDB_DEPTH_CLEAR 0x000b +#define regDB_DEPTH_CLEAR_BASE_IDX 1 +#define regPA_SC_SCREEN_SCISSOR_TL 0x000c +#define regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1 +#define regPA_SC_SCREEN_SCISSOR_BR 0x000d +#define regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1 +#define regDB_RESERVED_REG_2 0x000f +#define regDB_RESERVED_REG_2_BASE_IDX 1 +#define regDB_Z_INFO 0x0010 +#define regDB_Z_INFO_BASE_IDX 1 +#define regDB_STENCIL_INFO 0x0011 +#define regDB_STENCIL_INFO_BASE_IDX 1 +#define regDB_Z_READ_BASE 0x0012 +#define regDB_Z_READ_BASE_BASE_IDX 1 +#define regDB_STENCIL_READ_BASE 0x0013 +#define regDB_STENCIL_READ_BASE_BASE_IDX 1 +#define regDB_Z_WRITE_BASE 0x0014 +#define regDB_Z_WRITE_BASE_BASE_IDX 1 +#define regDB_STENCIL_WRITE_BASE 0x0015 +#define regDB_STENCIL_WRITE_BASE_BASE_IDX 1 +#define regDB_RESERVED_REG_1 0x0016 +#define regDB_RESERVED_REG_1_BASE_IDX 1 +#define regDB_RESERVED_REG_3 0x0017 +#define regDB_RESERVED_REG_3_BASE_IDX 1 +#define regDB_Z_READ_BASE_HI 0x001a +#define regDB_Z_READ_BASE_HI_BASE_IDX 1 +#define regDB_STENCIL_READ_BASE_HI 0x001b +#define regDB_STENCIL_READ_BASE_HI_BASE_IDX 1 +#define regDB_Z_WRITE_BASE_HI 0x001c +#define regDB_Z_WRITE_BASE_HI_BASE_IDX 1 +#define regDB_STENCIL_WRITE_BASE_HI 0x001d +#define regDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 +#define regDB_HTILE_DATA_BASE_HI 0x001e +#define regDB_HTILE_DATA_BASE_HI_BASE_IDX 1 +#define regDB_RMI_L2_CACHE_CONTROL 0x001f +#define regDB_RMI_L2_CACHE_CONTROL_BASE_IDX 1 +#define regTA_BC_BASE_ADDR 0x0020 +#define regTA_BC_BASE_ADDR_BASE_IDX 1 +#define regTA_BC_BASE_ADDR_HI 0x0021 +#define regTA_BC_BASE_ADDR_HI_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_0 0x007a +#define regCOHER_DEST_BASE_HI_0_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_1 0x007b +#define regCOHER_DEST_BASE_HI_1_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_2 0x007c +#define regCOHER_DEST_BASE_HI_2_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_3 0x007d +#define regCOHER_DEST_BASE_HI_3_BASE_IDX 1 +#define regCOHER_DEST_BASE_2 0x007e +#define regCOHER_DEST_BASE_2_BASE_IDX 1 +#define regCOHER_DEST_BASE_3 0x007f +#define regCOHER_DEST_BASE_3_BASE_IDX 1 +#define regPA_SC_WINDOW_OFFSET 0x0080 +#define regPA_SC_WINDOW_OFFSET_BASE_IDX 1 +#define regPA_SC_WINDOW_SCISSOR_TL 0x0081 +#define regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1 +#define regPA_SC_WINDOW_SCISSOR_BR 0x0082 +#define regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_RULE 0x0083 +#define regPA_SC_CLIPRECT_RULE_BASE_IDX 1 +#define regPA_SC_CLIPRECT_0_TL 0x0084 +#define regPA_SC_CLIPRECT_0_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_0_BR 0x0085 +#define regPA_SC_CLIPRECT_0_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_1_TL 0x0086 +#define regPA_SC_CLIPRECT_1_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_1_BR 0x0087 +#define regPA_SC_CLIPRECT_1_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_2_TL 0x0088 +#define regPA_SC_CLIPRECT_2_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_2_BR 0x0089 +#define regPA_SC_CLIPRECT_2_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_3_TL 0x008a +#define regPA_SC_CLIPRECT_3_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_3_BR 0x008b +#define regPA_SC_CLIPRECT_3_BR_BASE_IDX 1 +#define regPA_SC_EDGERULE 0x008c +#define regPA_SC_EDGERULE_BASE_IDX 1 +#define regPA_SU_HARDWARE_SCREEN_OFFSET 0x008d +#define regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1 +#define regCB_TARGET_MASK 0x008e +#define regCB_TARGET_MASK_BASE_IDX 1 +#define regCB_SHADER_MASK 0x008f +#define regCB_SHADER_MASK_BASE_IDX 1 +#define regPA_SC_GENERIC_SCISSOR_TL 0x0090 +#define regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1 +#define regPA_SC_GENERIC_SCISSOR_BR 0x0091 +#define regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1 +#define regCOHER_DEST_BASE_0 0x0092 +#define regCOHER_DEST_BASE_0_BASE_IDX 1 +#define regCOHER_DEST_BASE_1 0x0093 +#define regCOHER_DEST_BASE_1_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_0_TL 0x0094 +#define regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_0_BR 0x0095 +#define regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_1_TL 0x0096 +#define regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_1_BR 0x0097 +#define regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_2_TL 0x0098 +#define regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_2_BR 0x0099 +#define regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_3_TL 0x009a +#define regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_3_BR 0x009b +#define regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_4_TL 0x009c +#define regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_4_BR 0x009d +#define regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_5_TL 0x009e +#define regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_5_BR 0x009f +#define regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_6_TL 0x00a0 +#define regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_6_BR 0x00a1 +#define regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_7_TL 0x00a2 +#define regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_7_BR 0x00a3 +#define regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_8_TL 0x00a4 +#define regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_8_BR 0x00a5 +#define regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_9_TL 0x00a6 +#define regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_9_BR 0x00a7 +#define regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_10_TL 0x00a8 +#define regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_10_BR 0x00a9 +#define regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_11_TL 0x00aa +#define regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_11_BR 0x00ab +#define regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_12_TL 0x00ac +#define regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_12_BR 0x00ad +#define regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_13_TL 0x00ae +#define regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_13_BR 0x00af +#define regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_14_TL 0x00b0 +#define regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_14_BR 0x00b1 +#define regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_15_TL 0x00b2 +#define regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_15_BR 0x00b3 +#define regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_0 0x00b4 +#define regPA_SC_VPORT_ZMIN_0_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_0 0x00b5 +#define regPA_SC_VPORT_ZMAX_0_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_1 0x00b6 +#define regPA_SC_VPORT_ZMIN_1_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_1 0x00b7 +#define regPA_SC_VPORT_ZMAX_1_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_2 0x00b8 +#define regPA_SC_VPORT_ZMIN_2_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_2 0x00b9 +#define regPA_SC_VPORT_ZMAX_2_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_3 0x00ba +#define regPA_SC_VPORT_ZMIN_3_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_3 0x00bb +#define regPA_SC_VPORT_ZMAX_3_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_4 0x00bc +#define regPA_SC_VPORT_ZMIN_4_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_4 0x00bd +#define regPA_SC_VPORT_ZMAX_4_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_5 0x00be +#define regPA_SC_VPORT_ZMIN_5_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_5 0x00bf +#define regPA_SC_VPORT_ZMAX_5_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_6 0x00c0 +#define regPA_SC_VPORT_ZMIN_6_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_6 0x00c1 +#define regPA_SC_VPORT_ZMAX_6_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_7 0x00c2 +#define regPA_SC_VPORT_ZMIN_7_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_7 0x00c3 +#define regPA_SC_VPORT_ZMAX_7_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_8 0x00c4 +#define regPA_SC_VPORT_ZMIN_8_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_8 0x00c5 +#define regPA_SC_VPORT_ZMAX_8_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_9 0x00c6 +#define regPA_SC_VPORT_ZMIN_9_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_9 0x00c7 +#define regPA_SC_VPORT_ZMAX_9_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_10 0x00c8 +#define regPA_SC_VPORT_ZMIN_10_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_10 0x00c9 +#define regPA_SC_VPORT_ZMAX_10_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_11 0x00ca +#define regPA_SC_VPORT_ZMIN_11_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_11 0x00cb +#define regPA_SC_VPORT_ZMAX_11_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_12 0x00cc +#define regPA_SC_VPORT_ZMIN_12_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_12 0x00cd +#define regPA_SC_VPORT_ZMAX_12_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_13 0x00ce +#define regPA_SC_VPORT_ZMIN_13_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_13 0x00cf +#define regPA_SC_VPORT_ZMAX_13_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_14 0x00d0 +#define regPA_SC_VPORT_ZMIN_14_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_14 0x00d1 +#define regPA_SC_VPORT_ZMAX_14_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_15 0x00d2 +#define regPA_SC_VPORT_ZMIN_15_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_15 0x00d3 +#define regPA_SC_VPORT_ZMAX_15_BASE_IDX 1 +#define regPA_SC_RASTER_CONFIG 0x00d4 +#define regPA_SC_RASTER_CONFIG_BASE_IDX 1 +#define regPA_SC_RASTER_CONFIG_1 0x00d5 +#define regPA_SC_RASTER_CONFIG_1_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_CONTROL 0x00d6 +#define regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1 +#define regPA_SC_TILE_STEERING_OVERRIDE 0x00d7 +#define regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1 +#define regCP_PERFMON_CNTX_CNTL 0x00d8 +#define regCP_PERFMON_CNTX_CNTL_BASE_IDX 1 +#define regCP_PIPEID 0x00d9 +#define regCP_PIPEID_BASE_IDX 1 +#define regCP_RINGID 0x00d9 +#define regCP_RINGID_BASE_IDX 1 +#define regCP_VMID 0x00da +#define regCP_VMID_BASE_IDX 1 +#define regCONTEXT_RESERVED_REG0 0x00db +#define regCONTEXT_RESERVED_REG0_BASE_IDX 1 +#define regCONTEXT_RESERVED_REG1 0x00dc +#define regCONTEXT_RESERVED_REG1_BASE_IDX 1 +#define regPA_SC_VRS_OVERRIDE_CNTL 0x00f4 +#define regPA_SC_VRS_OVERRIDE_CNTL_BASE_IDX 1 +#define regPA_SC_VRS_RATE_FEEDBACK_BASE 0x00f5 +#define regPA_SC_VRS_RATE_FEEDBACK_BASE_BASE_IDX 1 +#define regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT 0x00f6 +#define regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT_BASE_IDX 1 +#define regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY 0x00f7 +#define regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY_BASE_IDX 1 +#define regPA_SC_VRS_RATE_CACHE_CNTL 0x00f9 +#define regPA_SC_VRS_RATE_CACHE_CNTL_BASE_IDX 1 +#define regPA_SC_VRS_RATE_BASE 0x00fc +#define regPA_SC_VRS_RATE_BASE_BASE_IDX 1 +#define regPA_SC_VRS_RATE_BASE_EXT 0x00fd +#define regPA_SC_VRS_RATE_BASE_EXT_BASE_IDX 1 +#define regPA_SC_VRS_RATE_SIZE_XY 0x00fe +#define regPA_SC_VRS_RATE_SIZE_XY_BASE_IDX 1 +#define regVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 +#define regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 +#define regCB_RMI_GL2_CACHE_CONTROL 0x0104 +#define regCB_RMI_GL2_CACHE_CONTROL_BASE_IDX 1 +#define regCB_BLEND_RED 0x0105 +#define regCB_BLEND_RED_BASE_IDX 1 +#define regCB_BLEND_GREEN 0x0106 +#define regCB_BLEND_GREEN_BASE_IDX 1 +#define regCB_BLEND_BLUE 0x0107 +#define regCB_BLEND_BLUE_BASE_IDX 1 +#define regCB_BLEND_ALPHA 0x0108 +#define regCB_BLEND_ALPHA_BASE_IDX 1 +#define regCB_FDCC_CONTROL 0x0109 +#define regCB_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COVERAGE_OUT_CONTROL 0x010a +#define regCB_COVERAGE_OUT_CONTROL_BASE_IDX 1 +#define regDB_STENCIL_CONTROL 0x010b +#define regDB_STENCIL_CONTROL_BASE_IDX 1 +#define regDB_STENCILREFMASK 0x010c +#define regDB_STENCILREFMASK_BASE_IDX 1 +#define regDB_STENCILREFMASK_BF 0x010d +#define regDB_STENCILREFMASK_BF_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE 0x010f +#define regPA_CL_VPORT_XSCALE_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET 0x0110 +#define regPA_CL_VPORT_XOFFSET_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE 0x0111 +#define regPA_CL_VPORT_YSCALE_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET 0x0112 +#define regPA_CL_VPORT_YOFFSET_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE 0x0113 +#define regPA_CL_VPORT_ZSCALE_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET 0x0114 +#define regPA_CL_VPORT_ZOFFSET_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_1 0x0115 +#define regPA_CL_VPORT_XSCALE_1_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_1 0x0116 +#define regPA_CL_VPORT_XOFFSET_1_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_1 0x0117 +#define regPA_CL_VPORT_YSCALE_1_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_1 0x0118 +#define regPA_CL_VPORT_YOFFSET_1_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_1 0x0119 +#define regPA_CL_VPORT_ZSCALE_1_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_1 0x011a +#define regPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_2 0x011b +#define regPA_CL_VPORT_XSCALE_2_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_2 0x011c +#define regPA_CL_VPORT_XOFFSET_2_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_2 0x011d +#define regPA_CL_VPORT_YSCALE_2_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_2 0x011e +#define regPA_CL_VPORT_YOFFSET_2_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_2 0x011f +#define regPA_CL_VPORT_ZSCALE_2_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_2 0x0120 +#define regPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_3 0x0121 +#define regPA_CL_VPORT_XSCALE_3_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_3 0x0122 +#define regPA_CL_VPORT_XOFFSET_3_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_3 0x0123 +#define regPA_CL_VPORT_YSCALE_3_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_3 0x0124 +#define regPA_CL_VPORT_YOFFSET_3_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_3 0x0125 +#define regPA_CL_VPORT_ZSCALE_3_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_3 0x0126 +#define regPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_4 0x0127 +#define regPA_CL_VPORT_XSCALE_4_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_4 0x0128 +#define regPA_CL_VPORT_XOFFSET_4_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_4 0x0129 +#define regPA_CL_VPORT_YSCALE_4_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_4 0x012a +#define regPA_CL_VPORT_YOFFSET_4_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_4 0x012b +#define regPA_CL_VPORT_ZSCALE_4_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_4 0x012c +#define regPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_5 0x012d +#define regPA_CL_VPORT_XSCALE_5_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_5 0x012e +#define regPA_CL_VPORT_XOFFSET_5_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_5 0x012f +#define regPA_CL_VPORT_YSCALE_5_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_5 0x0130 +#define regPA_CL_VPORT_YOFFSET_5_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_5 0x0131 +#define regPA_CL_VPORT_ZSCALE_5_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_5 0x0132 +#define regPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_6 0x0133 +#define regPA_CL_VPORT_XSCALE_6_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_6 0x0134 +#define regPA_CL_VPORT_XOFFSET_6_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_6 0x0135 +#define regPA_CL_VPORT_YSCALE_6_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_6 0x0136 +#define regPA_CL_VPORT_YOFFSET_6_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_6 0x0137 +#define regPA_CL_VPORT_ZSCALE_6_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_6 0x0138 +#define regPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_7 0x0139 +#define regPA_CL_VPORT_XSCALE_7_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_7 0x013a +#define regPA_CL_VPORT_XOFFSET_7_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_7 0x013b +#define regPA_CL_VPORT_YSCALE_7_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_7 0x013c +#define regPA_CL_VPORT_YOFFSET_7_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_7 0x013d +#define regPA_CL_VPORT_ZSCALE_7_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_7 0x013e +#define regPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_8 0x013f +#define regPA_CL_VPORT_XSCALE_8_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_8 0x0140 +#define regPA_CL_VPORT_XOFFSET_8_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_8 0x0141 +#define regPA_CL_VPORT_YSCALE_8_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_8 0x0142 +#define regPA_CL_VPORT_YOFFSET_8_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_8 0x0143 +#define regPA_CL_VPORT_ZSCALE_8_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_8 0x0144 +#define regPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_9 0x0145 +#define regPA_CL_VPORT_XSCALE_9_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_9 0x0146 +#define regPA_CL_VPORT_XOFFSET_9_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_9 0x0147 +#define regPA_CL_VPORT_YSCALE_9_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_9 0x0148 +#define regPA_CL_VPORT_YOFFSET_9_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_9 0x0149 +#define regPA_CL_VPORT_ZSCALE_9_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_9 0x014a +#define regPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_10 0x014b +#define regPA_CL_VPORT_XSCALE_10_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_10 0x014c +#define regPA_CL_VPORT_XOFFSET_10_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_10 0x014d +#define regPA_CL_VPORT_YSCALE_10_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_10 0x014e +#define regPA_CL_VPORT_YOFFSET_10_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_10 0x014f +#define regPA_CL_VPORT_ZSCALE_10_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_10 0x0150 +#define regPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_11 0x0151 +#define regPA_CL_VPORT_XSCALE_11_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_11 0x0152 +#define regPA_CL_VPORT_XOFFSET_11_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_11 0x0153 +#define regPA_CL_VPORT_YSCALE_11_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_11 0x0154 +#define regPA_CL_VPORT_YOFFSET_11_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_11 0x0155 +#define regPA_CL_VPORT_ZSCALE_11_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_11 0x0156 +#define regPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_12 0x0157 +#define regPA_CL_VPORT_XSCALE_12_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_12 0x0158 +#define regPA_CL_VPORT_XOFFSET_12_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_12 0x0159 +#define regPA_CL_VPORT_YSCALE_12_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_12 0x015a +#define regPA_CL_VPORT_YOFFSET_12_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_12 0x015b +#define regPA_CL_VPORT_ZSCALE_12_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_12 0x015c +#define regPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_13 0x015d +#define regPA_CL_VPORT_XSCALE_13_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_13 0x015e +#define regPA_CL_VPORT_XOFFSET_13_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_13 0x015f +#define regPA_CL_VPORT_YSCALE_13_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_13 0x0160 +#define regPA_CL_VPORT_YOFFSET_13_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_13 0x0161 +#define regPA_CL_VPORT_ZSCALE_13_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_13 0x0162 +#define regPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_14 0x0163 +#define regPA_CL_VPORT_XSCALE_14_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_14 0x0164 +#define regPA_CL_VPORT_XOFFSET_14_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_14 0x0165 +#define regPA_CL_VPORT_YSCALE_14_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_14 0x0166 +#define regPA_CL_VPORT_YOFFSET_14_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_14 0x0167 +#define regPA_CL_VPORT_ZSCALE_14_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_14 0x0168 +#define regPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_15 0x0169 +#define regPA_CL_VPORT_XSCALE_15_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_15 0x016a +#define regPA_CL_VPORT_XOFFSET_15_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_15 0x016b +#define regPA_CL_VPORT_YSCALE_15_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_15 0x016c +#define regPA_CL_VPORT_YOFFSET_15_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_15 0x016d +#define regPA_CL_VPORT_ZSCALE_15_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_15 0x016e +#define regPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1 +#define regPA_CL_UCP_0_X 0x016f +#define regPA_CL_UCP_0_X_BASE_IDX 1 +#define regPA_CL_UCP_0_Y 0x0170 +#define regPA_CL_UCP_0_Y_BASE_IDX 1 +#define regPA_CL_UCP_0_Z 0x0171 +#define regPA_CL_UCP_0_Z_BASE_IDX 1 +#define regPA_CL_UCP_0_W 0x0172 +#define regPA_CL_UCP_0_W_BASE_IDX 1 +#define regPA_CL_UCP_1_X 0x0173 +#define regPA_CL_UCP_1_X_BASE_IDX 1 +#define regPA_CL_UCP_1_Y 0x0174 +#define regPA_CL_UCP_1_Y_BASE_IDX 1 +#define regPA_CL_UCP_1_Z 0x0175 +#define regPA_CL_UCP_1_Z_BASE_IDX 1 +#define regPA_CL_UCP_1_W 0x0176 +#define regPA_CL_UCP_1_W_BASE_IDX 1 +#define regPA_CL_UCP_2_X 0x0177 +#define regPA_CL_UCP_2_X_BASE_IDX 1 +#define regPA_CL_UCP_2_Y 0x0178 +#define regPA_CL_UCP_2_Y_BASE_IDX 1 +#define regPA_CL_UCP_2_Z 0x0179 +#define regPA_CL_UCP_2_Z_BASE_IDX 1 +#define regPA_CL_UCP_2_W 0x017a +#define regPA_CL_UCP_2_W_BASE_IDX 1 +#define regPA_CL_UCP_3_X 0x017b +#define regPA_CL_UCP_3_X_BASE_IDX 1 +#define regPA_CL_UCP_3_Y 0x017c +#define regPA_CL_UCP_3_Y_BASE_IDX 1 +#define regPA_CL_UCP_3_Z 0x017d +#define regPA_CL_UCP_3_Z_BASE_IDX 1 +#define regPA_CL_UCP_3_W 0x017e +#define regPA_CL_UCP_3_W_BASE_IDX 1 +#define regPA_CL_UCP_4_X 0x017f +#define regPA_CL_UCP_4_X_BASE_IDX 1 +#define regPA_CL_UCP_4_Y 0x0180 +#define regPA_CL_UCP_4_Y_BASE_IDX 1 +#define regPA_CL_UCP_4_Z 0x0181 +#define regPA_CL_UCP_4_Z_BASE_IDX 1 +#define regPA_CL_UCP_4_W 0x0182 +#define regPA_CL_UCP_4_W_BASE_IDX 1 +#define regPA_CL_UCP_5_X 0x0183 +#define regPA_CL_UCP_5_X_BASE_IDX 1 +#define regPA_CL_UCP_5_Y 0x0184 +#define regPA_CL_UCP_5_Y_BASE_IDX 1 +#define regPA_CL_UCP_5_Z 0x0185 +#define regPA_CL_UCP_5_Z_BASE_IDX 1 +#define regPA_CL_UCP_5_W 0x0186 +#define regPA_CL_UCP_5_W_BASE_IDX 1 +#define regPA_CL_PROG_NEAR_CLIP_Z 0x0187 +#define regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX 1 +#define regPA_RATE_CNTL 0x0188 +#define regPA_RATE_CNTL_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_0 0x0191 +#define regSPI_PS_INPUT_CNTL_0_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_1 0x0192 +#define regSPI_PS_INPUT_CNTL_1_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_2 0x0193 +#define regSPI_PS_INPUT_CNTL_2_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_3 0x0194 +#define regSPI_PS_INPUT_CNTL_3_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_4 0x0195 +#define regSPI_PS_INPUT_CNTL_4_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_5 0x0196 +#define regSPI_PS_INPUT_CNTL_5_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_6 0x0197 +#define regSPI_PS_INPUT_CNTL_6_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_7 0x0198 +#define regSPI_PS_INPUT_CNTL_7_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_8 0x0199 +#define regSPI_PS_INPUT_CNTL_8_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_9 0x019a +#define regSPI_PS_INPUT_CNTL_9_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_10 0x019b +#define regSPI_PS_INPUT_CNTL_10_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_11 0x019c +#define regSPI_PS_INPUT_CNTL_11_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_12 0x019d +#define regSPI_PS_INPUT_CNTL_12_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_13 0x019e +#define regSPI_PS_INPUT_CNTL_13_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_14 0x019f +#define regSPI_PS_INPUT_CNTL_14_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_15 0x01a0 +#define regSPI_PS_INPUT_CNTL_15_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_16 0x01a1 +#define regSPI_PS_INPUT_CNTL_16_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_17 0x01a2 +#define regSPI_PS_INPUT_CNTL_17_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_18 0x01a3 +#define regSPI_PS_INPUT_CNTL_18_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_19 0x01a4 +#define regSPI_PS_INPUT_CNTL_19_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_20 0x01a5 +#define regSPI_PS_INPUT_CNTL_20_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_21 0x01a6 +#define regSPI_PS_INPUT_CNTL_21_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_22 0x01a7 +#define regSPI_PS_INPUT_CNTL_22_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_23 0x01a8 +#define regSPI_PS_INPUT_CNTL_23_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_24 0x01a9 +#define regSPI_PS_INPUT_CNTL_24_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_25 0x01aa +#define regSPI_PS_INPUT_CNTL_25_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_26 0x01ab +#define regSPI_PS_INPUT_CNTL_26_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_27 0x01ac +#define regSPI_PS_INPUT_CNTL_27_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_28 0x01ad +#define regSPI_PS_INPUT_CNTL_28_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_29 0x01ae +#define regSPI_PS_INPUT_CNTL_29_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_30 0x01af +#define regSPI_PS_INPUT_CNTL_30_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_31 0x01b0 +#define regSPI_PS_INPUT_CNTL_31_BASE_IDX 1 +#define regSPI_VS_OUT_CONFIG 0x01b1 +#define regSPI_VS_OUT_CONFIG_BASE_IDX 1 +#define regSPI_PS_INPUT_ENA 0x01b3 +#define regSPI_PS_INPUT_ENA_BASE_IDX 1 +#define regSPI_PS_INPUT_ADDR 0x01b4 +#define regSPI_PS_INPUT_ADDR_BASE_IDX 1 +#define regSPI_INTERP_CONTROL_0 0x01b5 +#define regSPI_INTERP_CONTROL_0_BASE_IDX 1 +#define regSPI_PS_IN_CONTROL 0x01b6 +#define regSPI_PS_IN_CONTROL_BASE_IDX 1 +#define regSPI_BARYC_CNTL 0x01b8 +#define regSPI_BARYC_CNTL_BASE_IDX 1 +#define regSPI_TMPRING_SIZE 0x01ba +#define regSPI_TMPRING_SIZE_BASE_IDX 1 +#define regSPI_GFX_SCRATCH_BASE_LO 0x01bb +#define regSPI_GFX_SCRATCH_BASE_LO_BASE_IDX 1 +#define regSPI_GFX_SCRATCH_BASE_HI 0x01bc +#define regSPI_GFX_SCRATCH_BASE_HI_BASE_IDX 1 +#define regSPI_SHADER_IDX_FORMAT 0x01c2 +#define regSPI_SHADER_IDX_FORMAT_BASE_IDX 1 +#define regSPI_SHADER_POS_FORMAT 0x01c3 +#define regSPI_SHADER_POS_FORMAT_BASE_IDX 1 +#define regSPI_SHADER_Z_FORMAT 0x01c4 +#define regSPI_SHADER_Z_FORMAT_BASE_IDX 1 +#define regSPI_SHADER_COL_FORMAT 0x01c5 +#define regSPI_SHADER_COL_FORMAT_BASE_IDX 1 +#define regSX_PS_DOWNCONVERT_CONTROL 0x01d4 +#define regSX_PS_DOWNCONVERT_CONTROL_BASE_IDX 1 +#define regSX_PS_DOWNCONVERT 0x01d5 +#define regSX_PS_DOWNCONVERT_BASE_IDX 1 +#define regSX_BLEND_OPT_EPSILON 0x01d6 +#define regSX_BLEND_OPT_EPSILON_BASE_IDX 1 +#define regSX_BLEND_OPT_CONTROL 0x01d7 +#define regSX_BLEND_OPT_CONTROL_BASE_IDX 1 +#define regSX_MRT0_BLEND_OPT 0x01d8 +#define regSX_MRT0_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT1_BLEND_OPT 0x01d9 +#define regSX_MRT1_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT2_BLEND_OPT 0x01da +#define regSX_MRT2_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT3_BLEND_OPT 0x01db +#define regSX_MRT3_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT4_BLEND_OPT 0x01dc +#define regSX_MRT4_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT5_BLEND_OPT 0x01dd +#define regSX_MRT5_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT6_BLEND_OPT 0x01de +#define regSX_MRT6_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT7_BLEND_OPT 0x01df +#define regSX_MRT7_BLEND_OPT_BASE_IDX 1 +#define regCB_BLEND0_CONTROL 0x01e0 +#define regCB_BLEND0_CONTROL_BASE_IDX 1 +#define regCB_BLEND1_CONTROL 0x01e1 +#define regCB_BLEND1_CONTROL_BASE_IDX 1 +#define regCB_BLEND2_CONTROL 0x01e2 +#define regCB_BLEND2_CONTROL_BASE_IDX 1 +#define regCB_BLEND3_CONTROL 0x01e3 +#define regCB_BLEND3_CONTROL_BASE_IDX 1 +#define regCB_BLEND4_CONTROL 0x01e4 +#define regCB_BLEND4_CONTROL_BASE_IDX 1 +#define regCB_BLEND5_CONTROL 0x01e5 +#define regCB_BLEND5_CONTROL_BASE_IDX 1 +#define regCB_BLEND6_CONTROL 0x01e6 +#define regCB_BLEND6_CONTROL_BASE_IDX 1 +#define regCB_BLEND7_CONTROL 0x01e7 +#define regCB_BLEND7_CONTROL_BASE_IDX 1 +#define regGFX_COPY_STATE 0x01f4 +#define regGFX_COPY_STATE_BASE_IDX 1 +#define regPA_CL_POINT_X_RAD 0x01f5 +#define regPA_CL_POINT_X_RAD_BASE_IDX 1 +#define regPA_CL_POINT_Y_RAD 0x01f6 +#define regPA_CL_POINT_Y_RAD_BASE_IDX 1 +#define regPA_CL_POINT_SIZE 0x01f7 +#define regPA_CL_POINT_SIZE_BASE_IDX 1 +#define regPA_CL_POINT_CULL_RAD 0x01f8 +#define regPA_CL_POINT_CULL_RAD_BASE_IDX 1 +#define regVGT_DMA_BASE_HI 0x01f9 +#define regVGT_DMA_BASE_HI_BASE_IDX 1 +#define regVGT_DMA_BASE 0x01fa +#define regVGT_DMA_BASE_BASE_IDX 1 +#define regVGT_DRAW_INITIATOR 0x01fc +#define regVGT_DRAW_INITIATOR_BASE_IDX 1 +#define regVGT_EVENT_ADDRESS_REG 0x01fe +#define regVGT_EVENT_ADDRESS_REG_BASE_IDX 1 +#define regGE_MAX_OUTPUT_PER_SUBGROUP 0x01ff +#define regGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX 1 +#define regDB_DEPTH_CONTROL 0x0200 +#define regDB_DEPTH_CONTROL_BASE_IDX 1 +#define regDB_EQAA 0x0201 +#define regDB_EQAA_BASE_IDX 1 +#define regCB_COLOR_CONTROL 0x0202 +#define regCB_COLOR_CONTROL_BASE_IDX 1 +#define regDB_SHADER_CONTROL 0x0203 +#define regDB_SHADER_CONTROL_BASE_IDX 1 +#define regPA_CL_CLIP_CNTL 0x0204 +#define regPA_CL_CLIP_CNTL_BASE_IDX 1 +#define regPA_SU_SC_MODE_CNTL 0x0205 +#define regPA_SU_SC_MODE_CNTL_BASE_IDX 1 +#define regPA_CL_VTE_CNTL 0x0206 +#define regPA_CL_VTE_CNTL_BASE_IDX 1 +#define regPA_CL_VS_OUT_CNTL 0x0207 +#define regPA_CL_VS_OUT_CNTL_BASE_IDX 1 +#define regPA_CL_NANINF_CNTL 0x0208 +#define regPA_CL_NANINF_CNTL_BASE_IDX 1 +#define regPA_SU_LINE_STIPPLE_CNTL 0x0209 +#define regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX 1 +#define regPA_SU_LINE_STIPPLE_SCALE 0x020a +#define regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX 1 +#define regPA_SU_PRIM_FILTER_CNTL 0x020b +#define regPA_SU_PRIM_FILTER_CNTL_BASE_IDX 1 +#define regPA_SU_SMALL_PRIM_FILTER_CNTL 0x020c +#define regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX 1 +#define regPA_CL_NGG_CNTL 0x020e +#define regPA_CL_NGG_CNTL_BASE_IDX 1 +#define regPA_SU_OVER_RASTERIZATION_CNTL 0x020f +#define regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX 1 +#define regPA_STEREO_CNTL 0x0210 +#define regPA_STEREO_CNTL_BASE_IDX 1 +#define regPA_STATE_STEREO_X 0x0211 +#define regPA_STATE_STEREO_X_BASE_IDX 1 +#define regPA_CL_VRS_CNTL 0x0212 +#define regPA_CL_VRS_CNTL_BASE_IDX 1 +#define regPA_SU_POINT_SIZE 0x0280 +#define regPA_SU_POINT_SIZE_BASE_IDX 1 +#define regPA_SU_POINT_MINMAX 0x0281 +#define regPA_SU_POINT_MINMAX_BASE_IDX 1 +#define regPA_SU_LINE_CNTL 0x0282 +#define regPA_SU_LINE_CNTL_BASE_IDX 1 +#define regPA_SC_LINE_STIPPLE 0x0283 +#define regPA_SC_LINE_STIPPLE_BASE_IDX 1 +#define regVGT_HOS_MAX_TESS_LEVEL 0x0286 +#define regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX 1 +#define regVGT_HOS_MIN_TESS_LEVEL 0x0287 +#define regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX 1 +#define regPA_SC_MODE_CNTL_0 0x0292 +#define regPA_SC_MODE_CNTL_0_BASE_IDX 1 +#define regPA_SC_MODE_CNTL_1 0x0293 +#define regPA_SC_MODE_CNTL_1_BASE_IDX 1 +#define regVGT_ENHANCE 0x0294 +#define regVGT_ENHANCE_BASE_IDX 1 +#define regIA_ENHANCE 0x029c +#define regIA_ENHANCE_BASE_IDX 1 +#define regVGT_DMA_SIZE 0x029d +#define regVGT_DMA_SIZE_BASE_IDX 1 +#define regVGT_DMA_MAX_SIZE 0x029e +#define regVGT_DMA_MAX_SIZE_BASE_IDX 1 +#define regVGT_DMA_INDEX_TYPE 0x029f +#define regVGT_DMA_INDEX_TYPE_BASE_IDX 1 +#define regWD_ENHANCE 0x02a0 +#define regWD_ENHANCE_BASE_IDX 1 +#define regVGT_PRIMITIVEID_EN 0x02a1 +#define regVGT_PRIMITIVEID_EN_BASE_IDX 1 +#define regVGT_DMA_NUM_INSTANCES 0x02a2 +#define regVGT_DMA_NUM_INSTANCES_BASE_IDX 1 +#define regVGT_PRIMITIVEID_RESET 0x02a3 +#define regVGT_PRIMITIVEID_RESET_BASE_IDX 1 +#define regVGT_EVENT_INITIATOR 0x02a4 +#define regVGT_EVENT_INITIATOR_BASE_IDX 1 +#define regVGT_DRAW_PAYLOAD_CNTL 0x02a6 +#define regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 +#define regVGT_ESGS_RING_ITEMSIZE 0x02ab +#define regVGT_ESGS_RING_ITEMSIZE_BASE_IDX 1 +#define regVGT_REUSE_OFF 0x02ad +#define regVGT_REUSE_OFF_BASE_IDX 1 +#define regDB_HTILE_SURFACE 0x02af +#define regDB_HTILE_SURFACE_BASE_IDX 1 +#define regDB_SRESULTS_COMPARE_STATE0 0x02b0 +#define regDB_SRESULTS_COMPARE_STATE0_BASE_IDX 1 +#define regDB_SRESULTS_COMPARE_STATE1 0x02b1 +#define regDB_SRESULTS_COMPARE_STATE1_BASE_IDX 1 +#define regDB_PRELOAD_CONTROL 0x02b2 +#define regDB_PRELOAD_CONTROL_BASE_IDX 1 +#define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x02ca +#define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX 1 +#define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x02cb +#define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX 1 +#define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x02cc +#define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX 1 +#define regVGT_GS_MAX_VERT_OUT 0x02ce +#define regVGT_GS_MAX_VERT_OUT_BASE_IDX 1 +#define regGE_NGG_SUBGRP_CNTL 0x02d3 +#define regGE_NGG_SUBGRP_CNTL_BASE_IDX 1 +#define regVGT_TESS_DISTRIBUTION 0x02d4 +#define regVGT_TESS_DISTRIBUTION_BASE_IDX 1 +#define regVGT_SHADER_STAGES_EN 0x02d5 +#define regVGT_SHADER_STAGES_EN_BASE_IDX 1 +#define regVGT_LS_HS_CONFIG 0x02d6 +#define regVGT_LS_HS_CONFIG_BASE_IDX 1 +#define regVGT_TF_PARAM 0x02db +#define regVGT_TF_PARAM_BASE_IDX 1 +#define regDB_ALPHA_TO_MASK 0x02dc +#define regDB_ALPHA_TO_MASK_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_DB_FMT_CNTL 0x02de +#define regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_CLAMP 0x02df +#define regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_FRONT_SCALE 0x02e0 +#define regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_FRONT_OFFSET 0x02e1 +#define regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_BACK_SCALE 0x02e2 +#define regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_BACK_OFFSET 0x02e3 +#define regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX 1 +#define regVGT_GS_INSTANCE_CNT 0x02e4 +#define regVGT_GS_INSTANCE_CNT_BASE_IDX 1 +#define regPA_SC_CENTROID_PRIORITY_0 0x02f5 +#define regPA_SC_CENTROID_PRIORITY_0_BASE_IDX 1 +#define regPA_SC_CENTROID_PRIORITY_1 0x02f6 +#define regPA_SC_CENTROID_PRIORITY_1_BASE_IDX 1 +#define regPA_SC_LINE_CNTL 0x02f7 +#define regPA_SC_LINE_CNTL_BASE_IDX 1 +#define regPA_SC_AA_CONFIG 0x02f8 +#define regPA_SC_AA_CONFIG_BASE_IDX 1 +#define regPA_SU_VTX_CNTL 0x02f9 +#define regPA_SU_VTX_CNTL_BASE_IDX 1 +#define regPA_CL_GB_VERT_CLIP_ADJ 0x02fa +#define regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX 1 +#define regPA_CL_GB_VERT_DISC_ADJ 0x02fb +#define regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX 1 +#define regPA_CL_GB_HORZ_CLIP_ADJ 0x02fc +#define regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX 1 +#define regPA_CL_GB_HORZ_DISC_ADJ 0x02fd +#define regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x02fe +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x02ff +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x0300 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x0301 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x0302 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x0303 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x0304 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x0305 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x0306 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x0307 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x0308 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x0309 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x030a +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x030b +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x030c +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x030d +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX 1 +#define regPA_SC_AA_MASK_X0Y0_X1Y0 0x030e +#define regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 1 +#define regPA_SC_AA_MASK_X0Y1_X1Y1 0x030f +#define regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 1 +#define regPA_SC_SHADER_CONTROL 0x0310 +#define regPA_SC_SHADER_CONTROL_BASE_IDX 1 +#define regPA_SC_BINNER_CNTL_0 0x0311 +#define regPA_SC_BINNER_CNTL_0_BASE_IDX 1 +#define regPA_SC_BINNER_CNTL_1 0x0312 +#define regPA_SC_BINNER_CNTL_1_BASE_IDX 1 +#define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0x0313 +#define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX 1 +#define regPA_SC_NGG_MODE_CNTL 0x0314 +#define regPA_SC_NGG_MODE_CNTL_BASE_IDX 1 +#define regPA_SC_BINNER_CNTL_2 0x0315 +#define regPA_SC_BINNER_CNTL_2_BASE_IDX 1 +#define regCB_COLOR0_BASE 0x0318 +#define regCB_COLOR0_BASE_BASE_IDX 1 +#define regCB_COLOR0_VIEW 0x031b +#define regCB_COLOR0_VIEW_BASE_IDX 1 +#define regCB_COLOR0_INFO 0x031c +#define regCB_COLOR0_INFO_BASE_IDX 1 +#define regCB_COLOR0_ATTRIB 0x031d +#define regCB_COLOR0_ATTRIB_BASE_IDX 1 +#define regCB_COLOR0_FDCC_CONTROL 0x031e +#define regCB_COLOR0_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR0_DCC_BASE 0x0325 +#define regCB_COLOR0_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR1_BASE 0x0327 +#define regCB_COLOR1_BASE_BASE_IDX 1 +#define regCB_COLOR1_VIEW 0x032a +#define regCB_COLOR1_VIEW_BASE_IDX 1 +#define regCB_COLOR1_INFO 0x032b +#define regCB_COLOR1_INFO_BASE_IDX 1 +#define regCB_COLOR1_ATTRIB 0x032c +#define regCB_COLOR1_ATTRIB_BASE_IDX 1 +#define regCB_COLOR1_FDCC_CONTROL 0x032d +#define regCB_COLOR1_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR1_DCC_BASE 0x0334 +#define regCB_COLOR1_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR2_BASE 0x0336 +#define regCB_COLOR2_BASE_BASE_IDX 1 +#define regCB_COLOR2_VIEW 0x0339 +#define regCB_COLOR2_VIEW_BASE_IDX 1 +#define regCB_COLOR2_INFO 0x033a +#define regCB_COLOR2_INFO_BASE_IDX 1 +#define regCB_COLOR2_ATTRIB 0x033b +#define regCB_COLOR2_ATTRIB_BASE_IDX 1 +#define regCB_COLOR2_FDCC_CONTROL 0x033c +#define regCB_COLOR2_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR2_DCC_BASE 0x0343 +#define regCB_COLOR2_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR3_BASE 0x0345 +#define regCB_COLOR3_BASE_BASE_IDX 1 +#define regCB_COLOR3_VIEW 0x0348 +#define regCB_COLOR3_VIEW_BASE_IDX 1 +#define regCB_COLOR3_INFO 0x0349 +#define regCB_COLOR3_INFO_BASE_IDX 1 +#define regCB_COLOR3_ATTRIB 0x034a +#define regCB_COLOR3_ATTRIB_BASE_IDX 1 +#define regCB_COLOR3_FDCC_CONTROL 0x034b +#define regCB_COLOR3_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR3_DCC_BASE 0x0352 +#define regCB_COLOR3_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR4_BASE 0x0354 +#define regCB_COLOR4_BASE_BASE_IDX 1 +#define regCB_COLOR4_VIEW 0x0357 +#define regCB_COLOR4_VIEW_BASE_IDX 1 +#define regCB_COLOR4_INFO 0x0358 +#define regCB_COLOR4_INFO_BASE_IDX 1 +#define regCB_COLOR4_ATTRIB 0x0359 +#define regCB_COLOR4_ATTRIB_BASE_IDX 1 +#define regCB_COLOR4_FDCC_CONTROL 0x035a +#define regCB_COLOR4_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR4_DCC_BASE 0x0361 +#define regCB_COLOR4_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR5_BASE 0x0363 +#define regCB_COLOR5_BASE_BASE_IDX 1 +#define regCB_COLOR5_VIEW 0x0366 +#define regCB_COLOR5_VIEW_BASE_IDX 1 +#define regCB_COLOR5_INFO 0x0367 +#define regCB_COLOR5_INFO_BASE_IDX 1 +#define regCB_COLOR5_ATTRIB 0x0368 +#define regCB_COLOR5_ATTRIB_BASE_IDX 1 +#define regCB_COLOR5_FDCC_CONTROL 0x0369 +#define regCB_COLOR5_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR5_DCC_BASE 0x0370 +#define regCB_COLOR5_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR6_BASE 0x0372 +#define regCB_COLOR6_BASE_BASE_IDX 1 +#define regCB_COLOR6_VIEW 0x0375 +#define regCB_COLOR6_VIEW_BASE_IDX 1 +#define regCB_COLOR6_INFO 0x0376 +#define regCB_COLOR6_INFO_BASE_IDX 1 +#define regCB_COLOR6_ATTRIB 0x0377 +#define regCB_COLOR6_ATTRIB_BASE_IDX 1 +#define regCB_COLOR6_FDCC_CONTROL 0x0378 +#define regCB_COLOR6_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR6_DCC_BASE 0x037f +#define regCB_COLOR6_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR7_BASE 0x0381 +#define regCB_COLOR7_BASE_BASE_IDX 1 +#define regCB_COLOR7_VIEW 0x0384 +#define regCB_COLOR7_VIEW_BASE_IDX 1 +#define regCB_COLOR7_INFO 0x0385 +#define regCB_COLOR7_INFO_BASE_IDX 1 +#define regCB_COLOR7_ATTRIB 0x0386 +#define regCB_COLOR7_ATTRIB_BASE_IDX 1 +#define regCB_COLOR7_FDCC_CONTROL 0x0387 +#define regCB_COLOR7_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR7_DCC_BASE 0x038e +#define regCB_COLOR7_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR0_BASE_EXT 0x0390 +#define regCB_COLOR0_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR1_BASE_EXT 0x0391 +#define regCB_COLOR1_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR2_BASE_EXT 0x0392 +#define regCB_COLOR2_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR3_BASE_EXT 0x0393 +#define regCB_COLOR3_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR4_BASE_EXT 0x0394 +#define regCB_COLOR4_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR5_BASE_EXT 0x0395 +#define regCB_COLOR5_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR6_BASE_EXT 0x0396 +#define regCB_COLOR6_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR7_BASE_EXT 0x0397 +#define regCB_COLOR7_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR0_DCC_BASE_EXT 0x03a8 +#define regCB_COLOR0_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR1_DCC_BASE_EXT 0x03a9 +#define regCB_COLOR1_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR2_DCC_BASE_EXT 0x03aa +#define regCB_COLOR2_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR3_DCC_BASE_EXT 0x03ab +#define regCB_COLOR3_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR4_DCC_BASE_EXT 0x03ac +#define regCB_COLOR4_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR5_DCC_BASE_EXT 0x03ad +#define regCB_COLOR5_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR6_DCC_BASE_EXT 0x03ae +#define regCB_COLOR6_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR7_DCC_BASE_EXT 0x03af +#define regCB_COLOR7_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR0_ATTRIB2 0x03b0 +#define regCB_COLOR0_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR1_ATTRIB2 0x03b1 +#define regCB_COLOR1_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR2_ATTRIB2 0x03b2 +#define regCB_COLOR2_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR3_ATTRIB2 0x03b3 +#define regCB_COLOR3_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR4_ATTRIB2 0x03b4 +#define regCB_COLOR4_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR5_ATTRIB2 0x03b5 +#define regCB_COLOR5_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR6_ATTRIB2 0x03b6 +#define regCB_COLOR6_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR7_ATTRIB2 0x03b7 +#define regCB_COLOR7_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR0_ATTRIB3 0x03b8 +#define regCB_COLOR0_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR1_ATTRIB3 0x03b9 +#define regCB_COLOR1_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR2_ATTRIB3 0x03ba +#define regCB_COLOR2_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR3_ATTRIB3 0x03bb +#define regCB_COLOR3_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR4_ATTRIB3 0x03bc +#define regCB_COLOR4_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR5_ATTRIB3 0x03bd +#define regCB_COLOR5_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR6_ATTRIB3 0x03be +#define regCB_COLOR6_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR7_ATTRIB3 0x03bf +#define regCB_COLOR7_ATTRIB3_BASE_IDX 1 + + +// addressBlock: gc_pfvf_cpdec +// base address: 0x2a000 +#define regCONFIG_RESERVED_REG0 0x0800 +#define regCONFIG_RESERVED_REG0_BASE_IDX 1 +#define regCONFIG_RESERVED_REG1 0x0801 +#define regCONFIG_RESERVED_REG1_BASE_IDX 1 +#define regCP_MEC_CNTL 0x0802 +#define regCP_MEC_CNTL_BASE_IDX 1 +#define regCP_ME_CNTL 0x0803 +#define regCP_ME_CNTL_BASE_IDX 1 + + +// addressBlock: gc_pfvf_grbmdec +// base address: 0x2a400 +#define regGRBM_GFX_CNTL 0x0900 +#define regGRBM_GFX_CNTL_BASE_IDX 1 +#define regGRBM_NOWHERE 0x0901 +#define regGRBM_NOWHERE_BASE_IDX 1 + + +// addressBlock: gc_pfvf_padec +// base address: 0x2a500 +#define regPA_SC_VRS_SURFACE_CNTL 0x0940 +#define regPA_SC_VRS_SURFACE_CNTL_BASE_IDX 1 +#define regPA_SC_ENHANCE 0x0941 +#define regPA_SC_ENHANCE_BASE_IDX 1 +#define regPA_SC_ENHANCE_1 0x0942 +#define regPA_SC_ENHANCE_1_BASE_IDX 1 +#define regPA_SC_ENHANCE_2 0x0943 +#define regPA_SC_ENHANCE_2_BASE_IDX 1 +#define regPA_SC_ENHANCE_3 0x0944 +#define regPA_SC_ENHANCE_3_BASE_IDX 1 +#define regPA_SC_BINNER_CNTL_OVERRIDE 0x0946 +#define regPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX 1 +#define regPA_SC_PBB_OVERRIDE_FLAG 0x0947 +#define regPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX 1 +#define regPA_SC_DSM_CNTL 0x0948 +#define regPA_SC_DSM_CNTL_BASE_IDX 1 +#define regPA_SC_TILE_STEERING_CREST_OVERRIDE 0x0949 +#define regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 1 +#define regPA_SC_FIFO_SIZE 0x094a +#define regPA_SC_FIFO_SIZE_BASE_IDX 1 +#define regPA_SC_IF_FIFO_SIZE 0x094b +#define regPA_SC_IF_FIFO_SIZE_BASE_IDX 1 +#define regPA_SC_PACKER_WAVE_ID_CNTL 0x094c +#define regPA_SC_PACKER_WAVE_ID_CNTL_BASE_IDX 1 +#define regPA_SC_ATM_CNTL 0x094d +#define regPA_SC_ATM_CNTL_BASE_IDX 1 +#define regPA_SC_PKR_WAVE_TABLE_CNTL 0x094e +#define regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 1 +#define regPA_SC_FORCE_EOV_MAX_CNTS 0x094f +#define regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 1 +#define regPA_SC_BINNER_EVENT_CNTL_0 0x0950 +#define regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 1 +#define regPA_SC_BINNER_EVENT_CNTL_1 0x0951 +#define regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 1 +#define regPA_SC_BINNER_EVENT_CNTL_2 0x0952 +#define regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 1 +#define regPA_SC_BINNER_EVENT_CNTL_3 0x0953 +#define regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 1 +#define regPA_SC_BINNER_TIMEOUT_COUNTER 0x0954 +#define regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 1 +#define regPA_SC_BINNER_PERF_CNTL_0 0x0955 +#define regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 1 +#define regPA_SC_BINNER_PERF_CNTL_1 0x0956 +#define regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 1 +#define regPA_SC_BINNER_PERF_CNTL_2 0x0957 +#define regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 1 +#define regPA_SC_BINNER_PERF_CNTL_3 0x0958 +#define regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x095b +#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x095c +#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_HV_LOCK 0x095d +#define regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 1 +#define regPA_PH_INTERFACE_FIFO_SIZE 0x095e +#define regPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX 1 +#define regPA_PH_ENHANCE 0x095f +#define regPA_PH_ENHANCE_BASE_IDX 1 +#define regPA_SC_VRS_SURFACE_CNTL_1 0x0960 +#define regPA_SC_VRS_SURFACE_CNTL_1_BASE_IDX 1 + + +// addressBlock: gc_pfvf_sqdec +// base address: 0x2a780 +#define regSQ_RUNTIME_CONFIG 0x09e0 +#define regSQ_RUNTIME_CONFIG_BASE_IDX 1 +#define regSQ_DEBUG_STS_GLOBAL 0x09e1 +#define regSQ_DEBUG_STS_GLOBAL_BASE_IDX 1 +#define regSQ_DEBUG_STS_GLOBAL2 0x09e2 +#define regSQ_DEBUG_STS_GLOBAL2_BASE_IDX 1 +#define regSH_MEM_BASES 0x09e3 +#define regSH_MEM_BASES_BASE_IDX 1 +#define regSH_MEM_CONFIG 0x09e4 +#define regSH_MEM_CONFIG_BASE_IDX 1 +#define regSQ_DEBUG 0x09e5 +#define regSQ_DEBUG_BASE_IDX 1 +#define regSQ_SHADER_TBA_LO 0x09e6 +#define regSQ_SHADER_TBA_LO_BASE_IDX 1 +#define regSQ_SHADER_TBA_HI 0x09e7 +#define regSQ_SHADER_TBA_HI_BASE_IDX 1 +#define regSQ_SHADER_TMA_LO 0x09e8 +#define regSQ_SHADER_TMA_LO_BASE_IDX 1 +#define regSQ_SHADER_TMA_HI 0x09e9 +#define regSQ_SHADER_TMA_HI_BASE_IDX 1 + + +// addressBlock: gc_pfonly_cpdec +// base address: 0x2e000 +#define regCP_DEBUG_2 0x1800 +#define regCP_DEBUG_2_BASE_IDX 1 +#define regCP_FETCHER_SOURCE 0x1801 +#define regCP_FETCHER_SOURCE_BASE_IDX 1 + + +// addressBlock: gc_pfonly_cpphqddec +// base address: 0x2e080 +#define regCP_HPD_MES_ROQ_OFFSETS 0x1821 +#define regCP_HPD_MES_ROQ_OFFSETS_BASE_IDX 1 +#define regCP_HPD_ROQ_OFFSETS 0x1821 +#define regCP_HPD_ROQ_OFFSETS_BASE_IDX 1 +#define regCP_HPD_STATUS0 0x1822 +#define regCP_HPD_STATUS0_BASE_IDX 1 + + +// addressBlock: gc_pfonly_didtdec +// base address: 0x2e400 +#define regDIDT_INDEX_AUTO_INCR_EN 0x1900 +#define regDIDT_INDEX_AUTO_INCR_EN_BASE_IDX 1 +#define regDIDT_EDC_CTRL 0x1901 +#define regDIDT_EDC_CTRL_BASE_IDX 1 +#define regDIDT_EDC_THROTTLE_CTRL 0x1902 +#define regDIDT_EDC_THROTTLE_CTRL_BASE_IDX 1 +#define regDIDT_EDC_THRESHOLD 0x1903 +#define regDIDT_EDC_THRESHOLD_BASE_IDX 1 +#define regDIDT_EDC_STALL_PATTERN_1_2 0x1904 +#define regDIDT_EDC_STALL_PATTERN_1_2_BASE_IDX 1 +#define regDIDT_EDC_STALL_PATTERN_3_4 0x1905 +#define regDIDT_EDC_STALL_PATTERN_3_4_BASE_IDX 1 +#define regDIDT_EDC_STALL_PATTERN_5_6 0x1906 +#define regDIDT_EDC_STALL_PATTERN_5_6_BASE_IDX 1 +#define regDIDT_EDC_STALL_PATTERN_7 0x1907 +#define regDIDT_EDC_STALL_PATTERN_7_BASE_IDX 1 +#define regDIDT_EDC_STATUS 0x1908 +#define regDIDT_EDC_STATUS_BASE_IDX 1 +#define regDIDT_EDC_DYNAMIC_THRESHOLD_RO 0x1909 +#define regDIDT_EDC_DYNAMIC_THRESHOLD_RO_BASE_IDX 1 +#define regDIDT_EDC_OVERFLOW 0x190a +#define regDIDT_EDC_OVERFLOW_BASE_IDX 1 +#define regDIDT_EDC_ROLLING_POWER_DELTA 0x190b +#define regDIDT_EDC_ROLLING_POWER_DELTA_BASE_IDX 1 +#define regDIDT_IND_INDEX 0x190c +#define regDIDT_IND_INDEX_BASE_IDX 1 +#define regDIDT_IND_DATA 0x190d +#define regDIDT_IND_DATA_BASE_IDX 1 + + +// addressBlock: gc_pfonly_spidec +// base address: 0x2e500 +#define regSPI_GDBG_WAVE_CNTL 0x1943 +#define regSPI_GDBG_WAVE_CNTL_BASE_IDX 1 +#define regSPI_GDBG_TRAP_CONFIG 0x1944 +#define regSPI_GDBG_TRAP_CONFIG_BASE_IDX 1 +#define regSPI_GDBG_WAVE_CNTL3 0x1945 +#define regSPI_GDBG_WAVE_CNTL3_BASE_IDX 1 +#define regSPI_ARB_CNTL_0 0x1949 +#define regSPI_ARB_CNTL_0_BASE_IDX 1 +#define regSPI_FEATURE_CTRL 0x194a +#define regSPI_FEATURE_CTRL_BASE_IDX 1 +#define regSPI_SHADER_RSRC_LIMIT_CTRL 0x194b +#define regSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX 1 +#define regSPI_COMPUTE_WF_CTX_SAVE_STATUS 0x194e +#define regSPI_COMPUTE_WF_CTX_SAVE_STATUS_BASE_IDX 1 + + +// addressBlock: gc_pfonly_tcpdec +// base address: 0x2e680 +#define regTCP_INVALIDATE 0x19a0 +#define regTCP_INVALIDATE_BASE_IDX 1 +#define regTCP_STATUS 0x19a1 +#define regTCP_STATUS_BASE_IDX 1 +#define regTCP_CNTL2 0x19a3 +#define regTCP_CNTL2_BASE_IDX 1 +#define regTCP_DEBUG_INDEX 0x19a5 +#define regTCP_DEBUG_INDEX_BASE_IDX 1 +#define regTCP_DEBUG_DATA 0x19a6 +#define regTCP_DEBUG_DATA_BASE_IDX 1 + + +// addressBlock: gc_pfonly_gdsdec +// base address: 0x2e6c0 +#define regGDS_ENHANCE2 0x19b0 +#define regGDS_ENHANCE2_BASE_IDX 1 +#define regGDS_OA_CGPG_RESTORE 0x19b1 +#define regGDS_OA_CGPG_RESTORE_BASE_IDX 1 + + +// addressBlock: gc_pfonly_utcl1dec +// base address: 0x2e600 +#define regUTCL1_CTRL_0 0x1980 +#define regUTCL1_CTRL_0_BASE_IDX 1 +#define regUTCL1_UTCL0_INVREQ_DISABLE 0x1984 +#define regUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX 1 +#define regUTCL1_CTRL_2 0x1985 +#define regUTCL1_CTRL_2_BASE_IDX 1 +#define regUTCL1_FIFO_SIZING 0x1986 +#define regUTCL1_FIFO_SIZING_BASE_IDX 1 +#define regGCRD_SA0_TARGETS_DISABLE 0x1987 +#define regGCRD_SA0_TARGETS_DISABLE_BASE_IDX 1 +#define regGCRD_SA1_TARGETS_DISABLE 0x1989 +#define regGCRD_SA1_TARGETS_DISABLE_BASE_IDX 1 +#define regGCRD_CREDIT_SAFE 0x198a +#define regGCRD_CREDIT_SAFE_BASE_IDX 1 + + +// addressBlock: gc_pfonly_pmmdec +// base address: 0x2e640 +#define regGCR_GENERAL_CNTL 0x1990 +#define regGCR_GENERAL_CNTL_BASE_IDX 1 +#define regGCR_CMD_STATUS 0x1992 +#define regGCR_CMD_STATUS_BASE_IDX 1 +#define regGCR_SPARE 0x1993 +#define regGCR_SPARE_BASE_IDX 1 +#define regPMM_CNTL2 0x1999 +#define regPMM_CNTL2_BASE_IDX 1 + + +// addressBlock: gc_sedcdec +// base address: 0x2eb00 +#define regSEDC_GL1_GL2_OVERRIDES 0x1ac0 +#define regSEDC_GL1_GL2_OVERRIDES_BASE_IDX 1 + + +// addressBlock: gc_pfonly_gccacdec +// base address: 0x2eb40 +#define regGC_CAC_CTRL_1 0x1ad0 +#define regGC_CAC_CTRL_1_BASE_IDX 1 +#define regGC_CAC_CTRL_2 0x1ad1 +#define regGC_CAC_CTRL_2_BASE_IDX 1 +#define regGC_CAC_AGGR_LOWER 0x1ad2 +#define regGC_CAC_AGGR_LOWER_BASE_IDX 1 +#define regGC_CAC_AGGR_UPPER 0x1ad3 +#define regGC_CAC_AGGR_UPPER_BASE_IDX 1 +#define regSE0_CAC_AGGR_LOWER 0x1ad4 +#define regSE0_CAC_AGGR_LOWER_BASE_IDX 1 +#define regSE0_CAC_AGGR_UPPER 0x1ad5 +#define regSE0_CAC_AGGR_UPPER_BASE_IDX 1 +#define regSE1_CAC_AGGR_LOWER 0x1ad6 +#define regSE1_CAC_AGGR_LOWER_BASE_IDX 1 +#define regSE1_CAC_AGGR_UPPER 0x1ad7 +#define regSE1_CAC_AGGR_UPPER_BASE_IDX 1 +#define regSE2_CAC_AGGR_LOWER 0x1ad8 +#define regSE2_CAC_AGGR_LOWER_BASE_IDX 1 +#define regSE2_CAC_AGGR_UPPER 0x1ad9 +#define regSE2_CAC_AGGR_UPPER_BASE_IDX 1 +#define regSE3_CAC_AGGR_LOWER 0x1ada +#define regSE3_CAC_AGGR_LOWER_BASE_IDX 1 +#define regSE3_CAC_AGGR_UPPER 0x1adb +#define regSE3_CAC_AGGR_UPPER_BASE_IDX 1 +#define regSE4_CAC_AGGR_LOWER 0x1adc +#define regSE4_CAC_AGGR_LOWER_BASE_IDX 1 +#define regSE4_CAC_AGGR_UPPER 0x1add +#define regSE4_CAC_AGGR_UPPER_BASE_IDX 1 +#define regSE5_CAC_AGGR_LOWER 0x1ade +#define regSE5_CAC_AGGR_LOWER_BASE_IDX 1 +#define regSE5_CAC_AGGR_UPPER 0x1adf +#define regSE5_CAC_AGGR_UPPER_BASE_IDX 1 +#define regGC_CAC_AGGR_GFXCLK_CYCLE 0x1ae4 +#define regGC_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 +#define regSE0_CAC_AGGR_GFXCLK_CYCLE 0x1ae5 +#define regSE0_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 +#define regSE1_CAC_AGGR_GFXCLK_CYCLE 0x1ae6 +#define regSE1_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 +#define regSE2_CAC_AGGR_GFXCLK_CYCLE 0x1ae7 +#define regSE2_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 +#define regSE3_CAC_AGGR_GFXCLK_CYCLE 0x1ae8 +#define regSE3_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 +#define regSE4_CAC_AGGR_GFXCLK_CYCLE 0x1ae9 +#define regSE4_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 +#define regSE5_CAC_AGGR_GFXCLK_CYCLE 0x1aea +#define regSE5_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 +#define regGC_EDC_CTRL 0x1aed +#define regGC_EDC_CTRL_BASE_IDX 1 +#define regGC_EDC_THRESHOLD 0x1aee +#define regGC_EDC_THRESHOLD_BASE_IDX 1 +#define regGC_EDC_STRETCH_CTRL 0x1aef +#define regGC_EDC_STRETCH_CTRL_BASE_IDX 1 +#define regGC_EDC_STRETCH_THRESHOLD 0x1af0 +#define regGC_EDC_STRETCH_THRESHOLD_BASE_IDX 1 +#define regEDC_HYSTERESIS_CNTL 0x1af1 +#define regEDC_HYSTERESIS_CNTL_BASE_IDX 1 +#define regGC_THROTTLE_CTRL 0x1af2 +#define regGC_THROTTLE_CTRL_BASE_IDX 1 +#define regGC_THROTTLE_CTRL1 0x1af3 +#define regGC_THROTTLE_CTRL1_BASE_IDX 1 +#define regPCC_STALL_PATTERN_CTRL 0x1af4 +#define regPCC_STALL_PATTERN_CTRL_BASE_IDX 1 +#define regPWRBRK_STALL_PATTERN_CTRL 0x1af5 +#define regPWRBRK_STALL_PATTERN_CTRL_BASE_IDX 1 +#define regPCC_STALL_PATTERN_1_2 0x1af6 +#define regPCC_STALL_PATTERN_1_2_BASE_IDX 1 +#define regPCC_STALL_PATTERN_3_4 0x1af7 +#define regPCC_STALL_PATTERN_3_4_BASE_IDX 1 +#define regPCC_STALL_PATTERN_5_6 0x1af8 +#define regPCC_STALL_PATTERN_5_6_BASE_IDX 1 +#define regPCC_STALL_PATTERN_7 0x1af9 +#define regPCC_STALL_PATTERN_7_BASE_IDX 1 +#define regPWRBRK_STALL_PATTERN_1_2 0x1afa +#define regPWRBRK_STALL_PATTERN_1_2_BASE_IDX 1 +#define regPWRBRK_STALL_PATTERN_3_4 0x1afb +#define regPWRBRK_STALL_PATTERN_3_4_BASE_IDX 1 +#define regPWRBRK_STALL_PATTERN_5_6 0x1afc +#define regPWRBRK_STALL_PATTERN_5_6_BASE_IDX 1 +#define regPWRBRK_STALL_PATTERN_7 0x1afd +#define regPWRBRK_STALL_PATTERN_7_BASE_IDX 1 +#define regDIDT_STALL_PATTERN_CTRL 0x1afe +#define regDIDT_STALL_PATTERN_CTRL_BASE_IDX 1 +#define regDIDT_STALL_PATTERN_1_2 0x1aff +#define regDIDT_STALL_PATTERN_1_2_BASE_IDX 1 +#define regDIDT_STALL_PATTERN_3_4 0x1b00 +#define regDIDT_STALL_PATTERN_3_4_BASE_IDX 1 +#define regDIDT_STALL_PATTERN_5_6 0x1b01 +#define regDIDT_STALL_PATTERN_5_6_BASE_IDX 1 +#define regDIDT_STALL_PATTERN_7 0x1b02 +#define regDIDT_STALL_PATTERN_7_BASE_IDX 1 +#define regPCC_PWRBRK_HYSTERESIS_CTRL 0x1b03 +#define regPCC_PWRBRK_HYSTERESIS_CTRL_BASE_IDX 1 +#define regEDC_STRETCH_PERF_COUNTER 0x1b04 +#define regEDC_STRETCH_PERF_COUNTER_BASE_IDX 1 +#define regEDC_UNSTRETCH_PERF_COUNTER 0x1b05 +#define regEDC_UNSTRETCH_PERF_COUNTER_BASE_IDX 1 +#define regEDC_STRETCH_NUM_PERF_COUNTER 0x1b06 +#define regEDC_STRETCH_NUM_PERF_COUNTER_BASE_IDX 1 +#define regGC_EDC_STATUS 0x1b07 +#define regGC_EDC_STATUS_BASE_IDX 1 +#define regGC_EDC_OVERFLOW 0x1b08 +#define regGC_EDC_OVERFLOW_BASE_IDX 1 +#define regGC_EDC_ROLLING_POWER_DELTA 0x1b09 +#define regGC_EDC_ROLLING_POWER_DELTA_BASE_IDX 1 +#define regGC_THROTTLE_STATUS 0x1b0a +#define regGC_THROTTLE_STATUS_BASE_IDX 1 +#define regEDC_PERF_COUNTER 0x1b0b +#define regEDC_PERF_COUNTER_BASE_IDX 1 +#define regPCC_PERF_COUNTER 0x1b0c +#define regPCC_PERF_COUNTER_BASE_IDX 1 +#define regPWRBRK_PERF_COUNTER 0x1b0d +#define regPWRBRK_PERF_COUNTER_BASE_IDX 1 +#define regEDC_HYSTERESIS_STAT 0x1b0e +#define regEDC_HYSTERESIS_STAT_BASE_IDX 1 +#define regGC_CAC_WEIGHT_CP_0 0x1b10 +#define regGC_CAC_WEIGHT_CP_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_CP_1 0x1b11 +#define regGC_CAC_WEIGHT_CP_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_EA_0 0x1b12 +#define regGC_CAC_WEIGHT_EA_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_EA_1 0x1b13 +#define regGC_CAC_WEIGHT_EA_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_EA_2 0x1b14 +#define regGC_CAC_WEIGHT_EA_2_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_0 0x1b15 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_1 0x1b16 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_2 0x1b17 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_2_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_3 0x1b18 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_3_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_4 0x1b19 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_4_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_VML2_0 0x1b1a +#define regGC_CAC_WEIGHT_UTCL2_VML2_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_VML2_1 0x1b1b +#define regGC_CAC_WEIGHT_UTCL2_VML2_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_VML2_2 0x1b1c +#define regGC_CAC_WEIGHT_UTCL2_VML2_2_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_WALKER_0 0x1b1d +#define regGC_CAC_WEIGHT_UTCL2_WALKER_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_WALKER_1 0x1b1e +#define regGC_CAC_WEIGHT_UTCL2_WALKER_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_WALKER_2 0x1b1f +#define regGC_CAC_WEIGHT_UTCL2_WALKER_2_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GDS_0 0x1b20 +#define regGC_CAC_WEIGHT_GDS_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GDS_1 0x1b21 +#define regGC_CAC_WEIGHT_GDS_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GDS_2 0x1b22 +#define regGC_CAC_WEIGHT_GDS_2_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GE_0 0x1b23 +#define regGC_CAC_WEIGHT_GE_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GE_1 0x1b24 +#define regGC_CAC_WEIGHT_GE_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GE_2 0x1b25 +#define regGC_CAC_WEIGHT_GE_2_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GE_3 0x1b26 +#define regGC_CAC_WEIGHT_GE_3_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GE_4 0x1b27 +#define regGC_CAC_WEIGHT_GE_4_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GE_5 0x1b28 +#define regGC_CAC_WEIGHT_GE_5_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GE_6 0x1b29 +#define regGC_CAC_WEIGHT_GE_6_BASE_IDX 1 +#define regGC_CAC_WEIGHT_PMM_0 0x1b2e +#define regGC_CAC_WEIGHT_PMM_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GL2C_0 0x1b2f +#define regGC_CAC_WEIGHT_GL2C_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GL2C_1 0x1b30 +#define regGC_CAC_WEIGHT_GL2C_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GL2C_2 0x1b31 +#define regGC_CAC_WEIGHT_GL2C_2_BASE_IDX 1 +#define regGC_CAC_WEIGHT_PH_0 0x1b32 +#define regGC_CAC_WEIGHT_PH_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_PH_1 0x1b33 +#define regGC_CAC_WEIGHT_PH_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_PH_2 0x1b34 +#define regGC_CAC_WEIGHT_PH_2_BASE_IDX 1 +#define regGC_CAC_WEIGHT_PH_3 0x1b35 +#define regGC_CAC_WEIGHT_PH_3_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_0 0x1b36 +#define regGC_CAC_WEIGHT_SDMA_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_1 0x1b37 +#define regGC_CAC_WEIGHT_SDMA_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_2 0x1b38 +#define regGC_CAC_WEIGHT_SDMA_2_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_3 0x1b39 +#define regGC_CAC_WEIGHT_SDMA_3_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_4 0x1b3a +#define regGC_CAC_WEIGHT_SDMA_4_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_5 0x1b3b +#define regGC_CAC_WEIGHT_SDMA_5_BASE_IDX 1 +#define regGC_CAC_WEIGHT_CHC_0 0x1b3c +#define regGC_CAC_WEIGHT_CHC_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_CHC_1 0x1b3d +#define regGC_CAC_WEIGHT_CHC_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GUS_0 0x1b3e +#define regGC_CAC_WEIGHT_GUS_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GUS_1 0x1b3f +#define regGC_CAC_WEIGHT_GUS_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_RLC_0 0x1b40 +#define regGC_CAC_WEIGHT_RLC_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GRBM_0 0x1b44 +#define regGC_CAC_WEIGHT_GRBM_0_BASE_IDX 1 +#define regGC_EDC_CLK_MONITOR_CTRL 0x1b56 +#define regGC_EDC_CLK_MONITOR_CTRL_BASE_IDX 1 +#define regGC_CAC_IND_INDEX 0x1b58 +#define regGC_CAC_IND_INDEX_BASE_IDX 1 +#define regGC_CAC_IND_DATA 0x1b59 +#define regGC_CAC_IND_DATA_BASE_IDX 1 +#define regSE_CAC_CTRL_1 0x1b70 +#define regSE_CAC_CTRL_1_BASE_IDX 1 +#define regSE_CAC_CTRL_2 0x1b71 +#define regSE_CAC_CTRL_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TA_0 0x1b72 +#define regSE_CAC_WEIGHT_TA_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TD_0 0x1b73 +#define regSE_CAC_WEIGHT_TD_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TD_1 0x1b74 +#define regSE_CAC_WEIGHT_TD_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TD_2 0x1b75 +#define regSE_CAC_WEIGHT_TD_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TD_3 0x1b76 +#define regSE_CAC_WEIGHT_TD_3_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TD_4 0x1b77 +#define regSE_CAC_WEIGHT_TD_4_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TD_5 0x1b78 +#define regSE_CAC_WEIGHT_TD_5_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_0 0x1b79 +#define regSE_CAC_WEIGHT_TCP_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_1 0x1b7a +#define regSE_CAC_WEIGHT_TCP_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_2 0x1b7b +#define regSE_CAC_WEIGHT_TCP_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_3 0x1b7c +#define regSE_CAC_WEIGHT_TCP_3_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SQ_0 0x1b7d +#define regSE_CAC_WEIGHT_SQ_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SQ_1 0x1b7e +#define regSE_CAC_WEIGHT_SQ_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SQ_2 0x1b7f +#define regSE_CAC_WEIGHT_SQ_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SP_0 0x1b80 +#define regSE_CAC_WEIGHT_SP_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SP_1 0x1b81 +#define regSE_CAC_WEIGHT_SP_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS_0 0x1b82 +#define regSE_CAC_WEIGHT_LDS_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS_1 0x1b83 +#define regSE_CAC_WEIGHT_LDS_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS_2 0x1b84 +#define regSE_CAC_WEIGHT_LDS_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS_3 0x1b85 +#define regSE_CAC_WEIGHT_LDS_3_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SQC_0 0x1b87 +#define regSE_CAC_WEIGHT_SQC_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SQC_1 0x1b88 +#define regSE_CAC_WEIGHT_SQC_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CU_0 0x1b89 +#define regSE_CAC_WEIGHT_CU_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_BCI_0 0x1b8a +#define regSE_CAC_WEIGHT_BCI_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_0 0x1b8b +#define regSE_CAC_WEIGHT_CB_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_1 0x1b8c +#define regSE_CAC_WEIGHT_CB_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_2 0x1b8d +#define regSE_CAC_WEIGHT_CB_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_3 0x1b8e +#define regSE_CAC_WEIGHT_CB_3_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_4 0x1b8f +#define regSE_CAC_WEIGHT_CB_4_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_5 0x1b90 +#define regSE_CAC_WEIGHT_CB_5_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_6 0x1b91 +#define regSE_CAC_WEIGHT_CB_6_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_7 0x1b92 +#define regSE_CAC_WEIGHT_CB_7_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_8 0x1b93 +#define regSE_CAC_WEIGHT_CB_8_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_9 0x1b94 +#define regSE_CAC_WEIGHT_CB_9_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_10 0x1b95 +#define regSE_CAC_WEIGHT_CB_10_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_11 0x1b96 +#define regSE_CAC_WEIGHT_CB_11_BASE_IDX 1 +#define regSE_CAC_WEIGHT_DB_0 0x1b97 +#define regSE_CAC_WEIGHT_DB_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_DB_1 0x1b98 +#define regSE_CAC_WEIGHT_DB_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_DB_2 0x1b99 +#define regSE_CAC_WEIGHT_DB_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_DB_3 0x1b9a +#define regSE_CAC_WEIGHT_DB_3_BASE_IDX 1 +#define regSE_CAC_WEIGHT_DB_4 0x1b9b +#define regSE_CAC_WEIGHT_DB_4_BASE_IDX 1 +#define regSE_CAC_WEIGHT_RMI_0 0x1b9c +#define regSE_CAC_WEIGHT_RMI_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_RMI_1 0x1b9d +#define regSE_CAC_WEIGHT_RMI_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SX_0 0x1b9e +#define regSE_CAC_WEIGHT_SX_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SXRB_0 0x1b9f +#define regSE_CAC_WEIGHT_SXRB_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_UTCL1_0 0x1ba0 +#define regSE_CAC_WEIGHT_UTCL1_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_GL1C_0 0x1ba1 +#define regSE_CAC_WEIGHT_GL1C_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_GL1C_1 0x1ba2 +#define regSE_CAC_WEIGHT_GL1C_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_GL1C_2 0x1ba3 +#define regSE_CAC_WEIGHT_GL1C_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SPI_0 0x1ba4 +#define regSE_CAC_WEIGHT_SPI_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SPI_1 0x1ba5 +#define regSE_CAC_WEIGHT_SPI_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SPI_2 0x1ba6 +#define regSE_CAC_WEIGHT_SPI_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_PC_0 0x1ba7 +#define regSE_CAC_WEIGHT_PC_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_PA_0 0x1ba8 +#define regSE_CAC_WEIGHT_PA_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_PA_1 0x1ba9 +#define regSE_CAC_WEIGHT_PA_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_PA_2 0x1baa +#define regSE_CAC_WEIGHT_PA_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_PA_3 0x1bab +#define regSE_CAC_WEIGHT_PA_3_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SC_0 0x1bac +#define regSE_CAC_WEIGHT_SC_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SC_1 0x1bad +#define regSE_CAC_WEIGHT_SC_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SC_2 0x1bae +#define regSE_CAC_WEIGHT_SC_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SC_3 0x1baf +#define regSE_CAC_WEIGHT_SC_3_BASE_IDX 1 +#define regSE_CAC_WINDOW_AGGR_VALUE 0x1bb0 +#define regSE_CAC_WINDOW_AGGR_VALUE_BASE_IDX 1 +#define regSE_CAC_WINDOW_GFXCLK_CYCLE 0x1bb1 +#define regSE_CAC_WINDOW_GFXCLK_CYCLE_BASE_IDX 1 +#define regSE_CAC_IND_INDEX 0x1bce +#define regSE_CAC_IND_INDEX_BASE_IDX 1 +#define regSE_CAC_IND_DATA 0x1bcf +#define regSE_CAC_IND_DATA_BASE_IDX 1 + + +// addressBlock: gc_pfonly2_spidec +// base address: 0x2f000 +#define regSPI_RESOURCE_RESERVE_CU_0 0x1c00 +#define regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_1 0x1c01 +#define regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_2 0x1c02 +#define regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_3 0x1c03 +#define regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_4 0x1c04 +#define regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_5 0x1c05 +#define regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_6 0x1c06 +#define regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_7 0x1c07 +#define regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_8 0x1c08 +#define regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_9 0x1c09 +#define regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_10 0x1c0a +#define regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_11 0x1c0b +#define regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_12 0x1c0c +#define regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_13 0x1c0d +#define regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_14 0x1c0e +#define regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_15 0x1c0f +#define regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_0 0x1c10 +#define regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_1 0x1c11 +#define regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_2 0x1c12 +#define regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_3 0x1c13 +#define regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_4 0x1c14 +#define regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_5 0x1c15 +#define regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_6 0x1c16 +#define regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_7 0x1c17 +#define regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_8 0x1c18 +#define regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_9 0x1c19 +#define regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_10 0x1c1a +#define regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_11 0x1c1b +#define regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_12 0x1c1c +#define regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_13 0x1c1d +#define regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_14 0x1c1e +#define regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_15 0x1c1f +#define regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX 1 + + +// addressBlock: gc_gfxudec +// base address: 0x30000 +#define regCP_EOP_DONE_ADDR_LO 0x2000 +#define regCP_EOP_DONE_ADDR_LO_BASE_IDX 1 +#define regCP_EOP_DONE_ADDR_HI 0x2001 +#define regCP_EOP_DONE_ADDR_HI_BASE_IDX 1 +#define regCP_EOP_DONE_DATA_LO 0x2002 +#define regCP_EOP_DONE_DATA_LO_BASE_IDX 1 +#define regCP_EOP_DONE_DATA_HI 0x2003 +#define regCP_EOP_DONE_DATA_HI_BASE_IDX 1 +#define regCP_EOP_LAST_FENCE_LO 0x2004 +#define regCP_EOP_LAST_FENCE_LO_BASE_IDX 1 +#define regCP_EOP_LAST_FENCE_HI 0x2005 +#define regCP_EOP_LAST_FENCE_HI_BASE_IDX 1 +#define regCP_PIPE_STATS_ADDR_LO 0x2018 +#define regCP_PIPE_STATS_ADDR_LO_BASE_IDX 1 +#define regCP_PIPE_STATS_ADDR_HI 0x2019 +#define regCP_PIPE_STATS_ADDR_HI_BASE_IDX 1 +#define regCP_VGT_IAVERT_COUNT_LO 0x201a +#define regCP_VGT_IAVERT_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_IAVERT_COUNT_HI 0x201b +#define regCP_VGT_IAVERT_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_IAPRIM_COUNT_LO 0x201c +#define regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_IAPRIM_COUNT_HI 0x201d +#define regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_GSPRIM_COUNT_LO 0x201e +#define regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_GSPRIM_COUNT_HI 0x201f +#define regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_VSINVOC_COUNT_LO 0x2020 +#define regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_VSINVOC_COUNT_HI 0x2021 +#define regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_GSINVOC_COUNT_LO 0x2022 +#define regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_GSINVOC_COUNT_HI 0x2023 +#define regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_HSINVOC_COUNT_LO 0x2024 +#define regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_HSINVOC_COUNT_HI 0x2025 +#define regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_DSINVOC_COUNT_LO 0x2026 +#define regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_DSINVOC_COUNT_HI 0x2027 +#define regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_PA_CINVOC_COUNT_LO 0x2028 +#define regCP_PA_CINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_PA_CINVOC_COUNT_HI 0x2029 +#define regCP_PA_CINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_PA_CPRIM_COUNT_LO 0x202a +#define regCP_PA_CPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_PA_CPRIM_COUNT_HI 0x202b +#define regCP_PA_CPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT0_LO 0x202c +#define regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT0_HI 0x202d +#define regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT1_LO 0x202e +#define regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT1_HI 0x202f +#define regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX 1 +#define regCP_VGT_CSINVOC_COUNT_LO 0x2030 +#define regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_CSINVOC_COUNT_HI 0x2031 +#define regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_ASINVOC_COUNT_LO 0x2032 +#define regCP_VGT_ASINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_ASINVOC_COUNT_HI 0x2033 +#define regCP_VGT_ASINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_PIPE_STATS_CONTROL 0x203d +#define regCP_PIPE_STATS_CONTROL_BASE_IDX 1 +#define regSCRATCH_REG0 0x2040 +#define regSCRATCH_REG0_BASE_IDX 1 +#define regSCRATCH_REG1 0x2041 +#define regSCRATCH_REG1_BASE_IDX 1 +#define regSCRATCH_REG2 0x2042 +#define regSCRATCH_REG2_BASE_IDX 1 +#define regSCRATCH_REG3 0x2043 +#define regSCRATCH_REG3_BASE_IDX 1 +#define regSCRATCH_REG4 0x2044 +#define regSCRATCH_REG4_BASE_IDX 1 +#define regSCRATCH_REG5 0x2045 +#define regSCRATCH_REG5_BASE_IDX 1 +#define regSCRATCH_REG6 0x2046 +#define regSCRATCH_REG6_BASE_IDX 1 +#define regSCRATCH_REG7 0x2047 +#define regSCRATCH_REG7_BASE_IDX 1 +#define regSCRATCH_REG_ATOMIC 0x2048 +#define regSCRATCH_REG_ATOMIC_BASE_IDX 1 +#define regSCRATCH_REG_CMPSWAP_ATOMIC 0x2048 +#define regSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX 1 +#define regCP_APPEND_DDID_CNT 0x204b +#define regCP_APPEND_DDID_CNT_BASE_IDX 1 +#define regCP_APPEND_DATA_HI 0x204c +#define regCP_APPEND_DATA_HI_BASE_IDX 1 +#define regCP_APPEND_LAST_CS_FENCE_HI 0x204d +#define regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX 1 +#define regCP_APPEND_LAST_PS_FENCE_HI 0x204e +#define regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX 1 +#define regCP_PFP_ATOMIC_PREOP_LO 0x2052 +#define regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX 1 +#define regCP_PFP_ATOMIC_PREOP_HI 0x2053 +#define regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX 1 +#define regCP_PFP_GDS_ATOMIC0_PREOP_LO 0x2054 +#define regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 +#define regCP_PFP_GDS_ATOMIC0_PREOP_HI 0x2055 +#define regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 +#define regCP_PFP_GDS_ATOMIC1_PREOP_LO 0x2056 +#define regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 +#define regCP_PFP_GDS_ATOMIC1_PREOP_HI 0x2057 +#define regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 +#define regCP_APPEND_ADDR_LO 0x2058 +#define regCP_APPEND_ADDR_LO_BASE_IDX 1 +#define regCP_APPEND_ADDR_HI 0x2059 +#define regCP_APPEND_ADDR_HI_BASE_IDX 1 +#define regCP_APPEND_DATA 0x205a +#define regCP_APPEND_DATA_BASE_IDX 1 +#define regCP_APPEND_DATA_LO 0x205a +#define regCP_APPEND_DATA_LO_BASE_IDX 1 +#define regCP_APPEND_LAST_CS_FENCE 0x205b +#define regCP_APPEND_LAST_CS_FENCE_BASE_IDX 1 +#define regCP_APPEND_LAST_CS_FENCE_LO 0x205b +#define regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX 1 +#define regCP_APPEND_LAST_PS_FENCE 0x205c +#define regCP_APPEND_LAST_PS_FENCE_BASE_IDX 1 +#define regCP_APPEND_LAST_PS_FENCE_LO 0x205c +#define regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX 1 +#define regCP_ATOMIC_PREOP_LO 0x205d +#define regCP_ATOMIC_PREOP_LO_BASE_IDX 1 +#define regCP_ME_ATOMIC_PREOP_LO 0x205d +#define regCP_ME_ATOMIC_PREOP_LO_BASE_IDX 1 +#define regCP_ATOMIC_PREOP_HI 0x205e +#define regCP_ATOMIC_PREOP_HI_BASE_IDX 1 +#define regCP_ME_ATOMIC_PREOP_HI 0x205e +#define regCP_ME_ATOMIC_PREOP_HI_BASE_IDX 1 +#define regCP_GDS_ATOMIC0_PREOP_LO 0x205f +#define regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 +#define regCP_ME_GDS_ATOMIC0_PREOP_LO 0x205f +#define regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 +#define regCP_GDS_ATOMIC0_PREOP_HI 0x2060 +#define regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 +#define regCP_ME_GDS_ATOMIC0_PREOP_HI 0x2060 +#define regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 +#define regCP_GDS_ATOMIC1_PREOP_LO 0x2061 +#define regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 +#define regCP_ME_GDS_ATOMIC1_PREOP_LO 0x2061 +#define regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 +#define regCP_GDS_ATOMIC1_PREOP_HI 0x2062 +#define regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 +#define regCP_ME_GDS_ATOMIC1_PREOP_HI 0x2062 +#define regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 +#define regCP_ME_MC_WADDR_LO 0x2069 +#define regCP_ME_MC_WADDR_LO_BASE_IDX 1 +#define regCP_ME_MC_WADDR_HI 0x206a +#define regCP_ME_MC_WADDR_HI_BASE_IDX 1 +#define regCP_ME_MC_WDATA_LO 0x206b +#define regCP_ME_MC_WDATA_LO_BASE_IDX 1 +#define regCP_ME_MC_WDATA_HI 0x206c +#define regCP_ME_MC_WDATA_HI_BASE_IDX 1 +#define regCP_ME_MC_RADDR_LO 0x206d +#define regCP_ME_MC_RADDR_LO_BASE_IDX 1 +#define regCP_ME_MC_RADDR_HI 0x206e +#define regCP_ME_MC_RADDR_HI_BASE_IDX 1 +#define regCP_SEM_WAIT_TIMER 0x206f +#define regCP_SEM_WAIT_TIMER_BASE_IDX 1 +#define regCP_SIG_SEM_ADDR_LO 0x2070 +#define regCP_SIG_SEM_ADDR_LO_BASE_IDX 1 +#define regCP_SIG_SEM_ADDR_HI 0x2071 +#define regCP_SIG_SEM_ADDR_HI_BASE_IDX 1 +#define regCP_WAIT_REG_MEM_TIMEOUT 0x2074 +#define regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX 1 +#define regCP_WAIT_SEM_ADDR_LO 0x2075 +#define regCP_WAIT_SEM_ADDR_LO_BASE_IDX 1 +#define regCP_WAIT_SEM_ADDR_HI 0x2076 +#define regCP_WAIT_SEM_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_PFP_CONTROL 0x2077 +#define regCP_DMA_PFP_CONTROL_BASE_IDX 1 +#define regCP_DMA_ME_CONTROL 0x2078 +#define regCP_DMA_ME_CONTROL_BASE_IDX 1 +#define regCP_DMA_ME_SRC_ADDR 0x2080 +#define regCP_DMA_ME_SRC_ADDR_BASE_IDX 1 +#define regCP_DMA_ME_SRC_ADDR_HI 0x2081 +#define regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_ME_DST_ADDR 0x2082 +#define regCP_DMA_ME_DST_ADDR_BASE_IDX 1 +#define regCP_DMA_ME_DST_ADDR_HI 0x2083 +#define regCP_DMA_ME_DST_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_ME_COMMAND 0x2084 +#define regCP_DMA_ME_COMMAND_BASE_IDX 1 +#define regCP_DMA_PFP_SRC_ADDR 0x2085 +#define regCP_DMA_PFP_SRC_ADDR_BASE_IDX 1 +#define regCP_DMA_PFP_SRC_ADDR_HI 0x2086 +#define regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_PFP_DST_ADDR 0x2087 +#define regCP_DMA_PFP_DST_ADDR_BASE_IDX 1 +#define regCP_DMA_PFP_DST_ADDR_HI 0x2088 +#define regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_PFP_COMMAND 0x2089 +#define regCP_DMA_PFP_COMMAND_BASE_IDX 1 +#define regCP_DMA_CNTL 0x208a +#define regCP_DMA_CNTL_BASE_IDX 1 +#define regCP_DMA_READ_TAGS 0x208b +#define regCP_DMA_READ_TAGS_BASE_IDX 1 +#define regCP_PFP_IB_CONTROL 0x208d +#define regCP_PFP_IB_CONTROL_BASE_IDX 1 +#define regCP_PFP_LOAD_CONTROL 0x208e +#define regCP_PFP_LOAD_CONTROL_BASE_IDX 1 +#define regCP_SCRATCH_INDEX 0x208f +#define regCP_SCRATCH_INDEX_BASE_IDX 1 +#define regCP_SCRATCH_DATA 0x2090 +#define regCP_SCRATCH_DATA_BASE_IDX 1 +#define regCP_RB_OFFSET 0x2091 +#define regCP_RB_OFFSET_BASE_IDX 1 +#define regCP_IB2_OFFSET 0x2093 +#define regCP_IB2_OFFSET_BASE_IDX 1 +#define regCP_IB2_PREAMBLE_BEGIN 0x2096 +#define regCP_IB2_PREAMBLE_BEGIN_BASE_IDX 1 +#define regCP_IB2_PREAMBLE_END 0x2097 +#define regCP_IB2_PREAMBLE_END_BASE_IDX 1 +#define regCP_DMA_ME_CMD_ADDR_LO 0x209c +#define regCP_DMA_ME_CMD_ADDR_LO_BASE_IDX 1 +#define regCP_DMA_ME_CMD_ADDR_HI 0x209d +#define regCP_DMA_ME_CMD_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_PFP_CMD_ADDR_LO 0x209e +#define regCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX 1 +#define regCP_DMA_PFP_CMD_ADDR_HI 0x209f +#define regCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX 1 +#define regCP_APPEND_CMD_ADDR_LO 0x20a0 +#define regCP_APPEND_CMD_ADDR_LO_BASE_IDX 1 +#define regCP_APPEND_CMD_ADDR_HI 0x20a1 +#define regCP_APPEND_CMD_ADDR_HI_BASE_IDX 1 +#define regUCONFIG_RESERVED_REG0 0x20a2 +#define regUCONFIG_RESERVED_REG0_BASE_IDX 1 +#define regUCONFIG_RESERVED_REG1 0x20a3 +#define regUCONFIG_RESERVED_REG1_BASE_IDX 1 +#define regCP_PA_MSPRIM_COUNT_LO 0x20a4 +#define regCP_PA_MSPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_PA_MSPRIM_COUNT_HI 0x20a5 +#define regCP_PA_MSPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_GE_MSINVOC_COUNT_LO 0x20a6 +#define regCP_GE_MSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_GE_MSINVOC_COUNT_HI 0x20a7 +#define regCP_GE_MSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_IB2_CMD_BUFSZ 0x20c1 +#define regCP_IB2_CMD_BUFSZ_BASE_IDX 1 +#define regCP_ST_CMD_BUFSZ 0x20c2 +#define regCP_ST_CMD_BUFSZ_BASE_IDX 1 +#define regCP_IB2_BASE_LO 0x20cf +#define regCP_IB2_BASE_LO_BASE_IDX 1 +#define regCP_IB2_BASE_HI 0x20d0 +#define regCP_IB2_BASE_HI_BASE_IDX 1 +#define regCP_IB2_BUFSZ 0x20d1 +#define regCP_IB2_BUFSZ_BASE_IDX 1 +#define regCP_ST_BASE_LO 0x20d2 +#define regCP_ST_BASE_LO_BASE_IDX 1 +#define regCP_ST_BASE_HI 0x20d3 +#define regCP_ST_BASE_HI_BASE_IDX 1 +#define regCP_ST_BUFSZ 0x20d4 +#define regCP_ST_BUFSZ_BASE_IDX 1 +#define regCP_EOP_DONE_EVENT_CNTL 0x20d5 +#define regCP_EOP_DONE_EVENT_CNTL_BASE_IDX 1 +#define regCP_EOP_DONE_DATA_CNTL 0x20d6 +#define regCP_EOP_DONE_DATA_CNTL_BASE_IDX 1 +#define regCP_EOP_DONE_CNTX_ID 0x20d7 +#define regCP_EOP_DONE_CNTX_ID_BASE_IDX 1 +#define regCP_DB_BASE_LO 0x20d8 +#define regCP_DB_BASE_LO_BASE_IDX 1 +#define regCP_DB_BASE_HI 0x20d9 +#define regCP_DB_BASE_HI_BASE_IDX 1 +#define regCP_DB_BUFSZ 0x20da +#define regCP_DB_BUFSZ_BASE_IDX 1 +#define regCP_DB_CMD_BUFSZ 0x20db +#define regCP_DB_CMD_BUFSZ_BASE_IDX 1 +#define regCP_PFP_COMPLETION_STATUS 0x20ec +#define regCP_PFP_COMPLETION_STATUS_BASE_IDX 1 +#define regCP_PRED_NOT_VISIBLE 0x20ee +#define regCP_PRED_NOT_VISIBLE_BASE_IDX 1 +#define regCP_PFP_METADATA_BASE_ADDR 0x20f0 +#define regCP_PFP_METADATA_BASE_ADDR_BASE_IDX 1 +#define regCP_PFP_METADATA_BASE_ADDR_HI 0x20f1 +#define regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX 1 +#define regCP_DRAW_INDX_INDR_ADDR 0x20f4 +#define regCP_DRAW_INDX_INDR_ADDR_BASE_IDX 1 +#define regCP_DRAW_INDX_INDR_ADDR_HI 0x20f5 +#define regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX 1 +#define regCP_DISPATCH_INDR_ADDR 0x20f6 +#define regCP_DISPATCH_INDR_ADDR_BASE_IDX 1 +#define regCP_DISPATCH_INDR_ADDR_HI 0x20f7 +#define regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX 1 +#define regCP_INDEX_BASE_ADDR 0x20f8 +#define regCP_INDEX_BASE_ADDR_BASE_IDX 1 +#define regCP_INDEX_BASE_ADDR_HI 0x20f9 +#define regCP_INDEX_BASE_ADDR_HI_BASE_IDX 1 +#define regCP_INDEX_TYPE 0x20fa +#define regCP_INDEX_TYPE_BASE_IDX 1 +#define regCP_GDS_BKUP_ADDR 0x20fb +#define regCP_GDS_BKUP_ADDR_BASE_IDX 1 +#define regCP_GDS_BKUP_ADDR_HI 0x20fc +#define regCP_GDS_BKUP_ADDR_HI_BASE_IDX 1 +#define regCP_SAMPLE_STATUS 0x20fd +#define regCP_SAMPLE_STATUS_BASE_IDX 1 +#define regCP_ME_COHER_CNTL 0x20fe +#define regCP_ME_COHER_CNTL_BASE_IDX 1 +#define regCP_ME_COHER_SIZE 0x20ff +#define regCP_ME_COHER_SIZE_BASE_IDX 1 +#define regCP_ME_COHER_SIZE_HI 0x2100 +#define regCP_ME_COHER_SIZE_HI_BASE_IDX 1 +#define regCP_ME_COHER_BASE 0x2101 +#define regCP_ME_COHER_BASE_BASE_IDX 1 +#define regCP_ME_COHER_BASE_HI 0x2102 +#define regCP_ME_COHER_BASE_HI_BASE_IDX 1 +#define regCP_ME_COHER_STATUS 0x2103 +#define regCP_ME_COHER_STATUS_BASE_IDX 1 +#define regRLC_GPM_PERF_COUNT_0 0x2140 +#define regRLC_GPM_PERF_COUNT_0_BASE_IDX 1 +#define regRLC_GPM_PERF_COUNT_1 0x2141 +#define regRLC_GPM_PERF_COUNT_1_BASE_IDX 1 +#define regGRBM_GFX_INDEX 0x2200 +#define regGRBM_GFX_INDEX_BASE_IDX 1 +#define regVGT_PRIMITIVE_TYPE 0x2242 +#define regVGT_PRIMITIVE_TYPE_BASE_IDX 1 +#define regVGT_INDEX_TYPE 0x2243 +#define regVGT_INDEX_TYPE_BASE_IDX 1 +#define regGE_MIN_VTX_INDX 0x2249 +#define regGE_MIN_VTX_INDX_BASE_IDX 1 +#define regGE_INDX_OFFSET 0x224a +#define regGE_INDX_OFFSET_BASE_IDX 1 +#define regGE_MULTI_PRIM_IB_RESET_EN 0x224b +#define regGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1 +#define regVGT_NUM_INDICES 0x224c +#define regVGT_NUM_INDICES_BASE_IDX 1 +#define regVGT_NUM_INSTANCES 0x224d +#define regVGT_NUM_INSTANCES_BASE_IDX 1 +#define regVGT_TF_RING_SIZE 0x224e +#define regVGT_TF_RING_SIZE_BASE_IDX 1 +#define regVGT_HS_OFFCHIP_PARAM 0x224f +#define regVGT_HS_OFFCHIP_PARAM_BASE_IDX 1 +#define regVGT_TF_MEMORY_BASE 0x2250 +#define regVGT_TF_MEMORY_BASE_BASE_IDX 1 +#define regGE_MAX_VTX_INDX 0x2259 +#define regGE_MAX_VTX_INDX_BASE_IDX 1 +#define regVGT_INSTANCE_BASE_ID 0x225a +#define regVGT_INSTANCE_BASE_ID_BASE_IDX 1 +#define regGE_CNTL 0x225b +#define regGE_CNTL_BASE_IDX 1 +#define regGE_USER_VGPR1 0x225c +#define regGE_USER_VGPR1_BASE_IDX 1 +#define regGE_USER_VGPR2 0x225d +#define regGE_USER_VGPR2_BASE_IDX 1 +#define regGE_USER_VGPR3 0x225e +#define regGE_USER_VGPR3_BASE_IDX 1 +#define regGE_STEREO_CNTL 0x225f +#define regGE_STEREO_CNTL_BASE_IDX 1 +#define regGE_PC_ALLOC 0x2260 +#define regGE_PC_ALLOC_BASE_IDX 1 +#define regVGT_TF_MEMORY_BASE_HI 0x2261 +#define regVGT_TF_MEMORY_BASE_HI_BASE_IDX 1 +#define regGE_USER_VGPR_EN 0x2262 +#define regGE_USER_VGPR_EN_BASE_IDX 1 +#define regGE_GS_FAST_LAUNCH_WG_DIM 0x2264 +#define regGE_GS_FAST_LAUNCH_WG_DIM_BASE_IDX 1 +#define regGE_GS_FAST_LAUNCH_WG_DIM_1 0x2265 +#define regGE_GS_FAST_LAUNCH_WG_DIM_1_BASE_IDX 1 +#define regVGT_GS_OUT_PRIM_TYPE 0x2266 +#define regVGT_GS_OUT_PRIM_TYPE_BASE_IDX 1 +#define regPA_SU_LINE_STIPPLE_VALUE 0x2280 +#define regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX 1 +#define regPA_SC_LINE_STIPPLE_STATE 0x2281 +#define regPA_SC_LINE_STIPPLE_STATE_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MIN_0 0x2284 +#define regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MAX_0 0x2285 +#define regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MIN_1 0x2286 +#define regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MAX_1 0x228b +#define regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_HV_EN 0x22a0 +#define regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_H 0x22a1 +#define regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_V 0x22a2 +#define regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0x22a3 +#define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_COUNT 0x22a4 +#define regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_EN 0x22a8 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_H 0x22a9 +#define regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_V 0x22aa +#define regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0x22ab +#define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_COUNT 0x22ac +#define regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_HV_EN 0x22b0 +#define regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_H 0x22b1 +#define regPA_SC_TRAP_SCREEN_H_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_V 0x22b2 +#define regPA_SC_TRAP_SCREEN_V_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_OCCURRENCE 0x22b3 +#define regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_COUNT 0x22b4 +#define regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_0 0x2340 +#define regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_1 0x2341 +#define regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_2 0x2342 +#define regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_3 0x2343 +#define regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_4 0x2344 +#define regSQ_THREAD_TRACE_USERDATA_4_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_5 0x2345 +#define regSQ_THREAD_TRACE_USERDATA_5_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_6 0x2346 +#define regSQ_THREAD_TRACE_USERDATA_6_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_7 0x2347 +#define regSQ_THREAD_TRACE_USERDATA_7_BASE_IDX 1 +#define regSQC_CACHES 0x2348 +#define regSQC_CACHES_BASE_IDX 1 +#define regTA_CS_BC_BASE_ADDR 0x2380 +#define regTA_CS_BC_BASE_ADDR_BASE_IDX 1 +#define regTA_CS_BC_BASE_ADDR_HI 0x2381 +#define regTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT0_LOW 0x23c0 +#define regDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT0_HI 0x23c1 +#define regDB_OCCLUSION_COUNT0_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT1_LOW 0x23c2 +#define regDB_OCCLUSION_COUNT1_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT1_HI 0x23c3 +#define regDB_OCCLUSION_COUNT1_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT2_LOW 0x23c4 +#define regDB_OCCLUSION_COUNT2_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT2_HI 0x23c5 +#define regDB_OCCLUSION_COUNT2_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT3_LOW 0x23c6 +#define regDB_OCCLUSION_COUNT3_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT3_HI 0x23c7 +#define regDB_OCCLUSION_COUNT3_HI_BASE_IDX 1 +#define regGDS_RD_ADDR 0x2400 +#define regGDS_RD_ADDR_BASE_IDX 1 +#define regGDS_RD_DATA 0x2401 +#define regGDS_RD_DATA_BASE_IDX 1 +#define regGDS_RD_BURST_ADDR 0x2402 +#define regGDS_RD_BURST_ADDR_BASE_IDX 1 +#define regGDS_RD_BURST_COUNT 0x2403 +#define regGDS_RD_BURST_COUNT_BASE_IDX 1 +#define regGDS_RD_BURST_DATA 0x2404 +#define regGDS_RD_BURST_DATA_BASE_IDX 1 +#define regGDS_WR_ADDR 0x2405 +#define regGDS_WR_ADDR_BASE_IDX 1 +#define regGDS_WR_DATA 0x2406 +#define regGDS_WR_DATA_BASE_IDX 1 +#define regGDS_WR_BURST_ADDR 0x2407 +#define regGDS_WR_BURST_ADDR_BASE_IDX 1 +#define regGDS_WR_BURST_DATA 0x2408 +#define regGDS_WR_BURST_DATA_BASE_IDX 1 +#define regGDS_WRITE_COMPLETE 0x2409 +#define regGDS_WRITE_COMPLETE_BASE_IDX 1 +#define regGDS_ATOM_CNTL 0x240a +#define regGDS_ATOM_CNTL_BASE_IDX 1 +#define regGDS_ATOM_COMPLETE 0x240b +#define regGDS_ATOM_COMPLETE_BASE_IDX 1 +#define regGDS_ATOM_BASE 0x240c +#define regGDS_ATOM_BASE_BASE_IDX 1 +#define regGDS_ATOM_SIZE 0x240d +#define regGDS_ATOM_SIZE_BASE_IDX 1 +#define regGDS_ATOM_OFFSET0 0x240e +#define regGDS_ATOM_OFFSET0_BASE_IDX 1 +#define regGDS_ATOM_OFFSET1 0x240f +#define regGDS_ATOM_OFFSET1_BASE_IDX 1 +#define regGDS_ATOM_DST 0x2410 +#define regGDS_ATOM_DST_BASE_IDX 1 +#define regGDS_ATOM_OP 0x2411 +#define regGDS_ATOM_OP_BASE_IDX 1 +#define regGDS_ATOM_SRC0 0x2412 +#define regGDS_ATOM_SRC0_BASE_IDX 1 +#define regGDS_ATOM_SRC0_U 0x2413 +#define regGDS_ATOM_SRC0_U_BASE_IDX 1 +#define regGDS_ATOM_SRC1 0x2414 +#define regGDS_ATOM_SRC1_BASE_IDX 1 +#define regGDS_ATOM_SRC1_U 0x2415 +#define regGDS_ATOM_SRC1_U_BASE_IDX 1 +#define regGDS_ATOM_READ0 0x2416 +#define regGDS_ATOM_READ0_BASE_IDX 1 +#define regGDS_ATOM_READ0_U 0x2417 +#define regGDS_ATOM_READ0_U_BASE_IDX 1 +#define regGDS_ATOM_READ1 0x2418 +#define regGDS_ATOM_READ1_BASE_IDX 1 +#define regGDS_ATOM_READ1_U 0x2419 +#define regGDS_ATOM_READ1_U_BASE_IDX 1 +#define regGDS_GWS_RESOURCE_CNTL 0x241a +#define regGDS_GWS_RESOURCE_CNTL_BASE_IDX 1 +#define regGDS_GWS_RESOURCE 0x241b +#define regGDS_GWS_RESOURCE_BASE_IDX 1 +#define regGDS_GWS_RESOURCE_CNT 0x241c +#define regGDS_GWS_RESOURCE_CNT_BASE_IDX 1 +#define regGDS_OA_CNTL 0x241d +#define regGDS_OA_CNTL_BASE_IDX 1 +#define regGDS_OA_COUNTER 0x241e +#define regGDS_OA_COUNTER_BASE_IDX 1 +#define regGDS_OA_ADDRESS 0x241f +#define regGDS_OA_ADDRESS_BASE_IDX 1 +#define regGDS_OA_INCDEC 0x2420 +#define regGDS_OA_INCDEC_BASE_IDX 1 +#define regGDS_OA_RING_SIZE 0x2421 +#define regGDS_OA_RING_SIZE_BASE_IDX 1 +#define regGDS_STRMOUT_DWORDS_WRITTEN_0 0x2422 +#define regGDS_STRMOUT_DWORDS_WRITTEN_0_BASE_IDX 1 +#define regGDS_STRMOUT_DWORDS_WRITTEN_1 0x2423 +#define regGDS_STRMOUT_DWORDS_WRITTEN_1_BASE_IDX 1 +#define regGDS_STRMOUT_DWORDS_WRITTEN_2 0x2424 +#define regGDS_STRMOUT_DWORDS_WRITTEN_2_BASE_IDX 1 +#define regGDS_STRMOUT_DWORDS_WRITTEN_3 0x2425 +#define regGDS_STRMOUT_DWORDS_WRITTEN_3_BASE_IDX 1 +#define regGDS_GS_0 0x2426 +#define regGDS_GS_0_BASE_IDX 1 +#define regGDS_GS_1 0x2427 +#define regGDS_GS_1_BASE_IDX 1 +#define regGDS_GS_2 0x2428 +#define regGDS_GS_2_BASE_IDX 1 +#define regGDS_GS_3 0x2429 +#define regGDS_GS_3_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_NEEDED_0_LO 0x242a +#define regGDS_STRMOUT_PRIMS_NEEDED_0_LO_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_NEEDED_0_HI 0x242b +#define regGDS_STRMOUT_PRIMS_NEEDED_0_HI_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_WRITTEN_0_LO 0x242c +#define regGDS_STRMOUT_PRIMS_WRITTEN_0_LO_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_WRITTEN_0_HI 0x242d +#define regGDS_STRMOUT_PRIMS_WRITTEN_0_HI_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_NEEDED_1_LO 0x242e +#define regGDS_STRMOUT_PRIMS_NEEDED_1_LO_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_NEEDED_1_HI 0x242f +#define regGDS_STRMOUT_PRIMS_NEEDED_1_HI_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_WRITTEN_1_LO 0x2430 +#define regGDS_STRMOUT_PRIMS_WRITTEN_1_LO_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_WRITTEN_1_HI 0x2431 +#define regGDS_STRMOUT_PRIMS_WRITTEN_1_HI_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_NEEDED_2_LO 0x2432 +#define regGDS_STRMOUT_PRIMS_NEEDED_2_LO_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_NEEDED_2_HI 0x2433 +#define regGDS_STRMOUT_PRIMS_NEEDED_2_HI_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_WRITTEN_2_LO 0x2434 +#define regGDS_STRMOUT_PRIMS_WRITTEN_2_LO_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_WRITTEN_2_HI 0x2435 +#define regGDS_STRMOUT_PRIMS_WRITTEN_2_HI_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_NEEDED_3_LO 0x2436 +#define regGDS_STRMOUT_PRIMS_NEEDED_3_LO_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_NEEDED_3_HI 0x2437 +#define regGDS_STRMOUT_PRIMS_NEEDED_3_HI_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_WRITTEN_3_LO 0x2438 +#define regGDS_STRMOUT_PRIMS_WRITTEN_3_LO_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_WRITTEN_3_HI 0x2439 +#define regGDS_STRMOUT_PRIMS_WRITTEN_3_HI_BASE_IDX 1 +#define regSPI_CONFIG_CNTL 0x2440 +#define regSPI_CONFIG_CNTL_BASE_IDX 1 +#define regSPI_CONFIG_CNTL_1 0x2441 +#define regSPI_CONFIG_CNTL_1_BASE_IDX 1 +#define regSPI_CONFIG_CNTL_2 0x2442 +#define regSPI_CONFIG_CNTL_2_BASE_IDX 1 +#define regSPI_WAVE_LIMIT_CNTL 0x2443 +#define regSPI_WAVE_LIMIT_CNTL_BASE_IDX 1 +#define regSPI_GS_THROTTLE_CNTL1 0x2444 +#define regSPI_GS_THROTTLE_CNTL1_BASE_IDX 1 +#define regSPI_GS_THROTTLE_CNTL2 0x2445 +#define regSPI_GS_THROTTLE_CNTL2_BASE_IDX 1 +#define regSPI_ATTRIBUTE_RING_BASE 0x2446 +#define regSPI_ATTRIBUTE_RING_BASE_BASE_IDX 1 +#define regSPI_ATTRIBUTE_RING_SIZE 0x2447 +#define regSPI_ATTRIBUTE_RING_SIZE_BASE_IDX 1 + + +// addressBlock: gc_cprs64dec +// base address: 0x32000 +#define regCP_MES_PRGRM_CNTR_START 0x2800 +#define regCP_MES_PRGRM_CNTR_START_BASE_IDX 1 +#define regCP_MES_INTR_ROUTINE_START 0x2801 +#define regCP_MES_INTR_ROUTINE_START_BASE_IDX 1 +#define regCP_MES_MTVEC_LO 0x2801 +#define regCP_MES_MTVEC_LO_BASE_IDX 1 +#define regCP_MES_INTR_ROUTINE_START_HI 0x2802 +#define regCP_MES_INTR_ROUTINE_START_HI_BASE_IDX 1 +#define regCP_MES_MTVEC_HI 0x2802 +#define regCP_MES_MTVEC_HI_BASE_IDX 1 +#define regCP_MES_CNTL 0x2807 +#define regCP_MES_CNTL_BASE_IDX 1 +#define regCP_MES_PIPE_PRIORITY_CNTS 0x2808 +#define regCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX 1 +#define regCP_MES_PIPE0_PRIORITY 0x2809 +#define regCP_MES_PIPE0_PRIORITY_BASE_IDX 1 +#define regCP_MES_PIPE1_PRIORITY 0x280a +#define regCP_MES_PIPE1_PRIORITY_BASE_IDX 1 +#define regCP_MES_PIPE2_PRIORITY 0x280b +#define regCP_MES_PIPE2_PRIORITY_BASE_IDX 1 +#define regCP_MES_PIPE3_PRIORITY 0x280c +#define regCP_MES_PIPE3_PRIORITY_BASE_IDX 1 +#define regCP_MES_HEADER_DUMP 0x280d +#define regCP_MES_HEADER_DUMP_BASE_IDX 1 +#define regCP_MES_MIE_LO 0x280e +#define regCP_MES_MIE_LO_BASE_IDX 1 +#define regCP_MES_MIE_HI 0x280f +#define regCP_MES_MIE_HI_BASE_IDX 1 +#define regCP_MES_INTERRUPT 0x2810 +#define regCP_MES_INTERRUPT_BASE_IDX 1 +#define regCP_MES_SCRATCH_INDEX 0x2811 +#define regCP_MES_SCRATCH_INDEX_BASE_IDX 1 +#define regCP_MES_SCRATCH_DATA 0x2812 +#define regCP_MES_SCRATCH_DATA_BASE_IDX 1 +#define regCP_MES_INSTR_PNTR 0x2813 +#define regCP_MES_INSTR_PNTR_BASE_IDX 1 +#define regCP_MES_MSCRATCH_HI 0x2814 +#define regCP_MES_MSCRATCH_HI_BASE_IDX 1 +#define regCP_MES_MSCRATCH_LO 0x2815 +#define regCP_MES_MSCRATCH_LO_BASE_IDX 1 +#define regCP_MES_MSTATUS_LO 0x2816 +#define regCP_MES_MSTATUS_LO_BASE_IDX 1 +#define regCP_MES_MSTATUS_HI 0x2817 +#define regCP_MES_MSTATUS_HI_BASE_IDX 1 +#define regCP_MES_MEPC_LO 0x2818 +#define regCP_MES_MEPC_LO_BASE_IDX 1 +#define regCP_MES_MEPC_HI 0x2819 +#define regCP_MES_MEPC_HI_BASE_IDX 1 +#define regCP_MES_MCAUSE_LO 0x281a +#define regCP_MES_MCAUSE_LO_BASE_IDX 1 +#define regCP_MES_MCAUSE_HI 0x281b +#define regCP_MES_MCAUSE_HI_BASE_IDX 1 +#define regCP_MES_MBADADDR_LO 0x281c +#define regCP_MES_MBADADDR_LO_BASE_IDX 1 +#define regCP_MES_MBADADDR_HI 0x281d +#define regCP_MES_MBADADDR_HI_BASE_IDX 1 +#define regCP_MES_MIP_LO 0x281e +#define regCP_MES_MIP_LO_BASE_IDX 1 +#define regCP_MES_MIP_HI 0x281f +#define regCP_MES_MIP_HI_BASE_IDX 1 +#define regCP_MES_IC_OP_CNTL 0x2820 +#define regCP_MES_IC_OP_CNTL_BASE_IDX 1 +#define regCP_MES_MCYCLE_LO 0x2826 +#define regCP_MES_MCYCLE_LO_BASE_IDX 1 +#define regCP_MES_MCYCLE_HI 0x2827 +#define regCP_MES_MCYCLE_HI_BASE_IDX 1 +#define regCP_MES_MTIME_LO 0x2828 +#define regCP_MES_MTIME_LO_BASE_IDX 1 +#define regCP_MES_MTIME_HI 0x2829 +#define regCP_MES_MTIME_HI_BASE_IDX 1 +#define regCP_MES_MINSTRET_LO 0x282a +#define regCP_MES_MINSTRET_LO_BASE_IDX 1 +#define regCP_MES_MINSTRET_HI 0x282b +#define regCP_MES_MINSTRET_HI_BASE_IDX 1 +#define regCP_MES_MISA_LO 0x282c +#define regCP_MES_MISA_LO_BASE_IDX 1 +#define regCP_MES_MISA_HI 0x282d +#define regCP_MES_MISA_HI_BASE_IDX 1 +#define regCP_MES_MVENDORID_LO 0x282e +#define regCP_MES_MVENDORID_LO_BASE_IDX 1 +#define regCP_MES_MVENDORID_HI 0x282f +#define regCP_MES_MVENDORID_HI_BASE_IDX 1 +#define regCP_MES_MARCHID_LO 0x2830 +#define regCP_MES_MARCHID_LO_BASE_IDX 1 +#define regCP_MES_MARCHID_HI 0x2831 +#define regCP_MES_MARCHID_HI_BASE_IDX 1 +#define regCP_MES_MIMPID_LO 0x2832 +#define regCP_MES_MIMPID_LO_BASE_IDX 1 +#define regCP_MES_MIMPID_HI 0x2833 +#define regCP_MES_MIMPID_HI_BASE_IDX 1 +#define regCP_MES_MHARTID_LO 0x2834 +#define regCP_MES_MHARTID_LO_BASE_IDX 1 +#define regCP_MES_MHARTID_HI 0x2835 +#define regCP_MES_MHARTID_HI_BASE_IDX 1 +#define regCP_MES_DC_BASE_CNTL 0x2836 +#define regCP_MES_DC_BASE_CNTL_BASE_IDX 1 +#define regCP_MES_DC_OP_CNTL 0x2837 +#define regCP_MES_DC_OP_CNTL_BASE_IDX 1 +#define regCP_MES_MTIMECMP_LO 0x2838 +#define regCP_MES_MTIMECMP_LO_BASE_IDX 1 +#define regCP_MES_MTIMECMP_HI 0x2839 +#define regCP_MES_MTIMECMP_HI_BASE_IDX 1 +#define regCP_MES_PROCESS_QUANTUM_PIPE0 0x283a +#define regCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX 1 +#define regCP_MES_PROCESS_QUANTUM_PIPE1 0x283b +#define regCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL1 0x283c +#define regCP_MES_DOORBELL_CONTROL1_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL2 0x283d +#define regCP_MES_DOORBELL_CONTROL2_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL3 0x283e +#define regCP_MES_DOORBELL_CONTROL3_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL4 0x283f +#define regCP_MES_DOORBELL_CONTROL4_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL5 0x2840 +#define regCP_MES_DOORBELL_CONTROL5_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL6 0x2841 +#define regCP_MES_DOORBELL_CONTROL6_BASE_IDX 1 +#define regCP_MES_GP0_LO 0x2843 +#define regCP_MES_GP0_LO_BASE_IDX 1 +#define regCP_MES_GP0_HI 0x2844 +#define regCP_MES_GP0_HI_BASE_IDX 1 +#define regCP_MES_GP1_LO 0x2845 +#define regCP_MES_GP1_LO_BASE_IDX 1 +#define regCP_MES_GP1_HI 0x2846 +#define regCP_MES_GP1_HI_BASE_IDX 1 +#define regCP_MES_GP2_LO 0x2847 +#define regCP_MES_GP2_LO_BASE_IDX 1 +#define regCP_MES_GP2_HI 0x2848 +#define regCP_MES_GP2_HI_BASE_IDX 1 +#define regCP_MES_GP3_LO 0x2849 +#define regCP_MES_GP3_LO_BASE_IDX 1 +#define regCP_MES_GP3_HI 0x284a +#define regCP_MES_GP3_HI_BASE_IDX 1 +#define regCP_MES_GP4_LO 0x284b +#define regCP_MES_GP4_LO_BASE_IDX 1 +#define regCP_MES_GP4_HI 0x284c +#define regCP_MES_GP4_HI_BASE_IDX 1 +#define regCP_MES_GP5_LO 0x284d +#define regCP_MES_GP5_LO_BASE_IDX 1 +#define regCP_MES_GP5_HI 0x284e +#define regCP_MES_GP5_HI_BASE_IDX 1 +#define regCP_MES_GP6_LO 0x284f +#define regCP_MES_GP6_LO_BASE_IDX 1 +#define regCP_MES_GP6_HI 0x2850 +#define regCP_MES_GP6_HI_BASE_IDX 1 +#define regCP_MES_GP7_LO 0x2851 +#define regCP_MES_GP7_LO_BASE_IDX 1 +#define regCP_MES_GP7_HI 0x2852 +#define regCP_MES_GP7_HI_BASE_IDX 1 +#define regCP_MES_GP8_LO 0x2853 +#define regCP_MES_GP8_LO_BASE_IDX 1 +#define regCP_MES_GP8_HI 0x2854 +#define regCP_MES_GP8_HI_BASE_IDX 1 +#define regCP_MES_GP9_LO 0x2855 +#define regCP_MES_GP9_LO_BASE_IDX 1 +#define regCP_MES_GP9_HI 0x2856 +#define regCP_MES_GP9_HI_BASE_IDX 1 +#define regCP_MES_LOCAL_BASE0_LO 0x2883 +#define regCP_MES_LOCAL_BASE0_LO_BASE_IDX 1 +#define regCP_MES_LOCAL_BASE0_HI 0x2884 +#define regCP_MES_LOCAL_BASE0_HI_BASE_IDX 1 +#define regCP_MES_LOCAL_MASK0_LO 0x2885 +#define regCP_MES_LOCAL_MASK0_LO_BASE_IDX 1 +#define regCP_MES_LOCAL_MASK0_HI 0x2886 +#define regCP_MES_LOCAL_MASK0_HI_BASE_IDX 1 +#define regCP_MES_LOCAL_APERTURE 0x2887 +#define regCP_MES_LOCAL_APERTURE_BASE_IDX 1 +#define regCP_MES_LOCAL_INSTR_BASE_LO 0x2888 +#define regCP_MES_LOCAL_INSTR_BASE_LO_BASE_IDX 1 +#define regCP_MES_LOCAL_INSTR_BASE_HI 0x2889 +#define regCP_MES_LOCAL_INSTR_BASE_HI_BASE_IDX 1 +#define regCP_MES_LOCAL_INSTR_MASK_LO 0x288a +#define regCP_MES_LOCAL_INSTR_MASK_LO_BASE_IDX 1 +#define regCP_MES_LOCAL_INSTR_MASK_HI 0x288b +#define regCP_MES_LOCAL_INSTR_MASK_HI_BASE_IDX 1 +#define regCP_MES_LOCAL_INSTR_APERTURE 0x288c +#define regCP_MES_LOCAL_INSTR_APERTURE_BASE_IDX 1 +#define regCP_MES_LOCAL_SCRATCH_APERTURE 0x288d +#define regCP_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 +#define regCP_MES_LOCAL_SCRATCH_BASE_LO 0x288e +#define regCP_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 +#define regCP_MES_LOCAL_SCRATCH_BASE_HI 0x288f +#define regCP_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 +#define regCP_MES_PERFCOUNT_CNTL 0x2899 +#define regCP_MES_PERFCOUNT_CNTL_BASE_IDX 1 +#define regCP_MES_PENDING_INTERRUPT 0x289a +#define regCP_MES_PENDING_INTERRUPT_BASE_IDX 1 +#define regCP_MES_PRGRM_CNTR_START_HI 0x289d +#define regCP_MES_PRGRM_CNTR_START_HI_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_16 0x289f +#define regCP_MES_INTERRUPT_DATA_16_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_17 0x28a0 +#define regCP_MES_INTERRUPT_DATA_17_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_18 0x28a1 +#define regCP_MES_INTERRUPT_DATA_18_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_19 0x28a2 +#define regCP_MES_INTERRUPT_DATA_19_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_20 0x28a3 +#define regCP_MES_INTERRUPT_DATA_20_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_21 0x28a4 +#define regCP_MES_INTERRUPT_DATA_21_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_22 0x28a5 +#define regCP_MES_INTERRUPT_DATA_22_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_23 0x28a6 +#define regCP_MES_INTERRUPT_DATA_23_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_24 0x28a7 +#define regCP_MES_INTERRUPT_DATA_24_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_25 0x28a8 +#define regCP_MES_INTERRUPT_DATA_25_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_26 0x28a9 +#define regCP_MES_INTERRUPT_DATA_26_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_27 0x28aa +#define regCP_MES_INTERRUPT_DATA_27_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_28 0x28ab +#define regCP_MES_INTERRUPT_DATA_28_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_29 0x28ac +#define regCP_MES_INTERRUPT_DATA_29_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_30 0x28ad +#define regCP_MES_INTERRUPT_DATA_30_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_31 0x28ae +#define regCP_MES_INTERRUPT_DATA_31_BASE_IDX 1 +#define regCP_MES_DC_APERTURE0_BASE 0x28af +#define regCP_MES_DC_APERTURE0_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE0_MASK 0x28b0 +#define regCP_MES_DC_APERTURE0_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE0_CNTL 0x28b1 +#define regCP_MES_DC_APERTURE0_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE1_BASE 0x28b2 +#define regCP_MES_DC_APERTURE1_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE1_MASK 0x28b3 +#define regCP_MES_DC_APERTURE1_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE1_CNTL 0x28b4 +#define regCP_MES_DC_APERTURE1_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE2_BASE 0x28b5 +#define regCP_MES_DC_APERTURE2_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE2_MASK 0x28b6 +#define regCP_MES_DC_APERTURE2_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE2_CNTL 0x28b7 +#define regCP_MES_DC_APERTURE2_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE3_BASE 0x28b8 +#define regCP_MES_DC_APERTURE3_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE3_MASK 0x28b9 +#define regCP_MES_DC_APERTURE3_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE3_CNTL 0x28ba +#define regCP_MES_DC_APERTURE3_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE4_BASE 0x28bb +#define regCP_MES_DC_APERTURE4_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE4_MASK 0x28bc +#define regCP_MES_DC_APERTURE4_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE4_CNTL 0x28bd +#define regCP_MES_DC_APERTURE4_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE5_BASE 0x28be +#define regCP_MES_DC_APERTURE5_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE5_MASK 0x28bf +#define regCP_MES_DC_APERTURE5_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE5_CNTL 0x28c0 +#define regCP_MES_DC_APERTURE5_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE6_BASE 0x28c1 +#define regCP_MES_DC_APERTURE6_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE6_MASK 0x28c2 +#define regCP_MES_DC_APERTURE6_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE6_CNTL 0x28c3 +#define regCP_MES_DC_APERTURE6_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE7_BASE 0x28c4 +#define regCP_MES_DC_APERTURE7_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE7_MASK 0x28c5 +#define regCP_MES_DC_APERTURE7_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE7_CNTL 0x28c6 +#define regCP_MES_DC_APERTURE7_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE8_BASE 0x28c7 +#define regCP_MES_DC_APERTURE8_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE8_MASK 0x28c8 +#define regCP_MES_DC_APERTURE8_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE8_CNTL 0x28c9 +#define regCP_MES_DC_APERTURE8_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE9_BASE 0x28ca +#define regCP_MES_DC_APERTURE9_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE9_MASK 0x28cb +#define regCP_MES_DC_APERTURE9_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE9_CNTL 0x28cc +#define regCP_MES_DC_APERTURE9_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE10_BASE 0x28cd +#define regCP_MES_DC_APERTURE10_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE10_MASK 0x28ce +#define regCP_MES_DC_APERTURE10_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE10_CNTL 0x28cf +#define regCP_MES_DC_APERTURE10_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE11_BASE 0x28d0 +#define regCP_MES_DC_APERTURE11_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE11_MASK 0x28d1 +#define regCP_MES_DC_APERTURE11_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE11_CNTL 0x28d2 +#define regCP_MES_DC_APERTURE11_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE12_BASE 0x28d3 +#define regCP_MES_DC_APERTURE12_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE12_MASK 0x28d4 +#define regCP_MES_DC_APERTURE12_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE12_CNTL 0x28d5 +#define regCP_MES_DC_APERTURE12_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE13_BASE 0x28d6 +#define regCP_MES_DC_APERTURE13_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE13_MASK 0x28d7 +#define regCP_MES_DC_APERTURE13_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE13_CNTL 0x28d8 +#define regCP_MES_DC_APERTURE13_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE14_BASE 0x28d9 +#define regCP_MES_DC_APERTURE14_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE14_MASK 0x28da +#define regCP_MES_DC_APERTURE14_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE14_CNTL 0x28db +#define regCP_MES_DC_APERTURE14_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE15_BASE 0x28dc +#define regCP_MES_DC_APERTURE15_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE15_MASK 0x28dd +#define regCP_MES_DC_APERTURE15_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE15_CNTL 0x28de +#define regCP_MES_DC_APERTURE15_CNTL_BASE_IDX 1 +#define regCP_MEC_RS64_PRGRM_CNTR_START 0x2900 +#define regCP_MEC_RS64_PRGRM_CNTR_START_BASE_IDX 1 +#define regCP_MEC_MTVEC_LO 0x2901 +#define regCP_MEC_MTVEC_LO_BASE_IDX 1 +#define regCP_MEC_MTVEC_HI 0x2902 +#define regCP_MEC_MTVEC_HI_BASE_IDX 1 +#define regCP_MEC_ISA_CNTL 0x2903 +#define regCP_MEC_ISA_CNTL_BASE_IDX 1 +#define regCP_MEC_RS64_CNTL 0x2904 +#define regCP_MEC_RS64_CNTL_BASE_IDX 1 +#define regCP_MEC_MIE_LO 0x2905 +#define regCP_MEC_MIE_LO_BASE_IDX 1 +#define regCP_MEC_MIE_HI 0x2906 +#define regCP_MEC_MIE_HI_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT 0x2907 +#define regCP_MEC_RS64_INTERRUPT_BASE_IDX 1 +#define regCP_MEC_RS64_INSTR_PNTR 0x2908 +#define regCP_MEC_RS64_INSTR_PNTR_BASE_IDX 1 +#define regCP_MEC_MIP_LO 0x2909 +#define regCP_MEC_MIP_LO_BASE_IDX 1 +#define regCP_MEC_MIP_HI 0x290a +#define regCP_MEC_MIP_HI_BASE_IDX 1 +#define regCP_MEC_DC_BASE_CNTL 0x290b +#define regCP_MEC_DC_BASE_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_OP_CNTL 0x290c +#define regCP_MEC_DC_OP_CNTL_BASE_IDX 1 +#define regCP_MEC_MTIMECMP_LO 0x290d +#define regCP_MEC_MTIMECMP_LO_BASE_IDX 1 +#define regCP_MEC_MTIMECMP_HI 0x290e +#define regCP_MEC_MTIMECMP_HI_BASE_IDX 1 +#define regCP_MEC_GP0_LO 0x2910 +#define regCP_MEC_GP0_LO_BASE_IDX 1 +#define regCP_MEC_GP0_HI 0x2911 +#define regCP_MEC_GP0_HI_BASE_IDX 1 +#define regCP_MEC_GP1_LO 0x2912 +#define regCP_MEC_GP1_LO_BASE_IDX 1 +#define regCP_MEC_GP1_HI 0x2913 +#define regCP_MEC_GP1_HI_BASE_IDX 1 +#define regCP_MEC_GP2_LO 0x2914 +#define regCP_MEC_GP2_LO_BASE_IDX 1 +#define regCP_MEC_GP2_HI 0x2915 +#define regCP_MEC_GP2_HI_BASE_IDX 1 +#define regCP_MEC_GP3_LO 0x2916 +#define regCP_MEC_GP3_LO_BASE_IDX 1 +#define regCP_MEC_GP3_HI 0x2917 +#define regCP_MEC_GP3_HI_BASE_IDX 1 +#define regCP_MEC_GP4_LO 0x2918 +#define regCP_MEC_GP4_LO_BASE_IDX 1 +#define regCP_MEC_GP4_HI 0x2919 +#define regCP_MEC_GP4_HI_BASE_IDX 1 +#define regCP_MEC_GP5_LO 0x291a +#define regCP_MEC_GP5_LO_BASE_IDX 1 +#define regCP_MEC_GP5_HI 0x291b +#define regCP_MEC_GP5_HI_BASE_IDX 1 +#define regCP_MEC_GP6_LO 0x291c +#define regCP_MEC_GP6_LO_BASE_IDX 1 +#define regCP_MEC_GP6_HI 0x291d +#define regCP_MEC_GP6_HI_BASE_IDX 1 +#define regCP_MEC_GP7_LO 0x291e +#define regCP_MEC_GP7_LO_BASE_IDX 1 +#define regCP_MEC_GP7_HI 0x291f +#define regCP_MEC_GP7_HI_BASE_IDX 1 +#define regCP_MEC_GP8_LO 0x2920 +#define regCP_MEC_GP8_LO_BASE_IDX 1 +#define regCP_MEC_GP8_HI 0x2921 +#define regCP_MEC_GP8_HI_BASE_IDX 1 +#define regCP_MEC_GP9_LO 0x2922 +#define regCP_MEC_GP9_LO_BASE_IDX 1 +#define regCP_MEC_GP9_HI 0x2923 +#define regCP_MEC_GP9_HI_BASE_IDX 1 +#define regCP_MEC_LOCAL_BASE0_LO 0x2927 +#define regCP_MEC_LOCAL_BASE0_LO_BASE_IDX 1 +#define regCP_MEC_LOCAL_BASE0_HI 0x2928 +#define regCP_MEC_LOCAL_BASE0_HI_BASE_IDX 1 +#define regCP_MEC_LOCAL_MASK0_LO 0x2929 +#define regCP_MEC_LOCAL_MASK0_LO_BASE_IDX 1 +#define regCP_MEC_LOCAL_MASK0_HI 0x292a +#define regCP_MEC_LOCAL_MASK0_HI_BASE_IDX 1 +#define regCP_MEC_LOCAL_APERTURE 0x292b +#define regCP_MEC_LOCAL_APERTURE_BASE_IDX 1 +#define regCP_MEC_LOCAL_INSTR_BASE_LO 0x292c +#define regCP_MEC_LOCAL_INSTR_BASE_LO_BASE_IDX 1 +#define regCP_MEC_LOCAL_INSTR_BASE_HI 0x292d +#define regCP_MEC_LOCAL_INSTR_BASE_HI_BASE_IDX 1 +#define regCP_MEC_LOCAL_INSTR_MASK_LO 0x292e +#define regCP_MEC_LOCAL_INSTR_MASK_LO_BASE_IDX 1 +#define regCP_MEC_LOCAL_INSTR_MASK_HI 0x292f +#define regCP_MEC_LOCAL_INSTR_MASK_HI_BASE_IDX 1 +#define regCP_MEC_LOCAL_INSTR_APERTURE 0x2930 +#define regCP_MEC_LOCAL_INSTR_APERTURE_BASE_IDX 1 +#define regCP_MEC_LOCAL_SCRATCH_APERTURE 0x2931 +#define regCP_MEC_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 +#define regCP_MEC_LOCAL_SCRATCH_BASE_LO 0x2932 +#define regCP_MEC_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 +#define regCP_MEC_LOCAL_SCRATCH_BASE_HI 0x2933 +#define regCP_MEC_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 +#define regCP_MEC_RS64_PERFCOUNT_CNTL 0x2934 +#define regCP_MEC_RS64_PERFCOUNT_CNTL_BASE_IDX 1 +#define regCP_MEC_RS64_PENDING_INTERRUPT 0x2935 +#define regCP_MEC_RS64_PENDING_INTERRUPT_BASE_IDX 1 +#define regCP_MEC_RS64_PRGRM_CNTR_START_HI 0x2938 +#define regCP_MEC_RS64_PRGRM_CNTR_START_HI_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_16 0x293a +#define regCP_MEC_RS64_INTERRUPT_DATA_16_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_17 0x293b +#define regCP_MEC_RS64_INTERRUPT_DATA_17_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_18 0x293c +#define regCP_MEC_RS64_INTERRUPT_DATA_18_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_19 0x293d +#define regCP_MEC_RS64_INTERRUPT_DATA_19_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_20 0x293e +#define regCP_MEC_RS64_INTERRUPT_DATA_20_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_21 0x293f +#define regCP_MEC_RS64_INTERRUPT_DATA_21_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_22 0x2940 +#define regCP_MEC_RS64_INTERRUPT_DATA_22_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_23 0x2941 +#define regCP_MEC_RS64_INTERRUPT_DATA_23_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_24 0x2942 +#define regCP_MEC_RS64_INTERRUPT_DATA_24_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_25 0x2943 +#define regCP_MEC_RS64_INTERRUPT_DATA_25_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_26 0x2944 +#define regCP_MEC_RS64_INTERRUPT_DATA_26_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_27 0x2945 +#define regCP_MEC_RS64_INTERRUPT_DATA_27_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_28 0x2946 +#define regCP_MEC_RS64_INTERRUPT_DATA_28_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_29 0x2947 +#define regCP_MEC_RS64_INTERRUPT_DATA_29_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_30 0x2948 +#define regCP_MEC_RS64_INTERRUPT_DATA_30_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_31 0x2949 +#define regCP_MEC_RS64_INTERRUPT_DATA_31_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE0_BASE 0x294a +#define regCP_MEC_DC_APERTURE0_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE0_MASK 0x294b +#define regCP_MEC_DC_APERTURE0_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE0_CNTL 0x294c +#define regCP_MEC_DC_APERTURE0_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE1_BASE 0x294d +#define regCP_MEC_DC_APERTURE1_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE1_MASK 0x294e +#define regCP_MEC_DC_APERTURE1_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE1_CNTL 0x294f +#define regCP_MEC_DC_APERTURE1_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE2_BASE 0x2950 +#define regCP_MEC_DC_APERTURE2_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE2_MASK 0x2951 +#define regCP_MEC_DC_APERTURE2_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE2_CNTL 0x2952 +#define regCP_MEC_DC_APERTURE2_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE3_BASE 0x2953 +#define regCP_MEC_DC_APERTURE3_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE3_MASK 0x2954 +#define regCP_MEC_DC_APERTURE3_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE3_CNTL 0x2955 +#define regCP_MEC_DC_APERTURE3_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE4_BASE 0x2956 +#define regCP_MEC_DC_APERTURE4_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE4_MASK 0x2957 +#define regCP_MEC_DC_APERTURE4_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE4_CNTL 0x2958 +#define regCP_MEC_DC_APERTURE4_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE5_BASE 0x2959 +#define regCP_MEC_DC_APERTURE5_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE5_MASK 0x295a +#define regCP_MEC_DC_APERTURE5_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE5_CNTL 0x295b +#define regCP_MEC_DC_APERTURE5_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE6_BASE 0x295c +#define regCP_MEC_DC_APERTURE6_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE6_MASK 0x295d +#define regCP_MEC_DC_APERTURE6_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE6_CNTL 0x295e +#define regCP_MEC_DC_APERTURE6_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE7_BASE 0x295f +#define regCP_MEC_DC_APERTURE7_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE7_MASK 0x2960 +#define regCP_MEC_DC_APERTURE7_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE7_CNTL 0x2961 +#define regCP_MEC_DC_APERTURE7_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE8_BASE 0x2962 +#define regCP_MEC_DC_APERTURE8_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE8_MASK 0x2963 +#define regCP_MEC_DC_APERTURE8_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE8_CNTL 0x2964 +#define regCP_MEC_DC_APERTURE8_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE9_BASE 0x2965 +#define regCP_MEC_DC_APERTURE9_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE9_MASK 0x2966 +#define regCP_MEC_DC_APERTURE9_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE9_CNTL 0x2967 +#define regCP_MEC_DC_APERTURE9_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE10_BASE 0x2968 +#define regCP_MEC_DC_APERTURE10_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE10_MASK 0x2969 +#define regCP_MEC_DC_APERTURE10_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE10_CNTL 0x296a +#define regCP_MEC_DC_APERTURE10_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE11_BASE 0x296b +#define regCP_MEC_DC_APERTURE11_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE11_MASK 0x296c +#define regCP_MEC_DC_APERTURE11_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE11_CNTL 0x296d +#define regCP_MEC_DC_APERTURE11_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE12_BASE 0x296e +#define regCP_MEC_DC_APERTURE12_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE12_MASK 0x296f +#define regCP_MEC_DC_APERTURE12_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE12_CNTL 0x2970 +#define regCP_MEC_DC_APERTURE12_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE13_BASE 0x2971 +#define regCP_MEC_DC_APERTURE13_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE13_MASK 0x2972 +#define regCP_MEC_DC_APERTURE13_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE13_CNTL 0x2973 +#define regCP_MEC_DC_APERTURE13_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE14_BASE 0x2974 +#define regCP_MEC_DC_APERTURE14_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE14_MASK 0x2975 +#define regCP_MEC_DC_APERTURE14_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE14_CNTL 0x2976 +#define regCP_MEC_DC_APERTURE14_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE15_BASE 0x2977 +#define regCP_MEC_DC_APERTURE15_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE15_MASK 0x2978 +#define regCP_MEC_DC_APERTURE15_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE15_CNTL 0x2979 +#define regCP_MEC_DC_APERTURE15_CNTL_BASE_IDX 1 +#define regCP_CPC_IC_OP_CNTL 0x297a +#define regCP_CPC_IC_OP_CNTL_BASE_IDX 1 +#define regCP_GFX_CNTL 0x2a00 +#define regCP_GFX_CNTL_BASE_IDX 1 +#define regCP_GFX_RS64_INTERRUPT0 0x2a01 +#define regCP_GFX_RS64_INTERRUPT0_BASE_IDX 1 +#define regCP_GFX_RS64_INTR_EN0 0x2a02 +#define regCP_GFX_RS64_INTR_EN0_BASE_IDX 1 +#define regCP_GFX_RS64_INTR_EN1 0x2a03 +#define regCP_GFX_RS64_INTR_EN1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_BASE_CNTL 0x2a08 +#define regCP_GFX_RS64_DC_BASE_CNTL_BASE_IDX 1 +#define regCP_GFX_RS64_DC_OP_CNTL 0x2a09 +#define regCP_GFX_RS64_DC_OP_CNTL_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_BASE0_LO 0x2a0a +#define regCP_GFX_RS64_LOCAL_BASE0_LO_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_BASE0_HI 0x2a0b +#define regCP_GFX_RS64_LOCAL_BASE0_HI_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_MASK0_LO 0x2a0c +#define regCP_GFX_RS64_LOCAL_MASK0_LO_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_MASK0_HI 0x2a0d +#define regCP_GFX_RS64_LOCAL_MASK0_HI_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_APERTURE 0x2a0e +#define regCP_GFX_RS64_LOCAL_APERTURE_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_INSTR_BASE_LO 0x2a0f +#define regCP_GFX_RS64_LOCAL_INSTR_BASE_LO_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_INSTR_BASE_HI 0x2a10 +#define regCP_GFX_RS64_LOCAL_INSTR_BASE_HI_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_INSTR_MASK_LO 0x2a11 +#define regCP_GFX_RS64_LOCAL_INSTR_MASK_LO_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_INSTR_MASK_HI 0x2a12 +#define regCP_GFX_RS64_LOCAL_INSTR_MASK_HI_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_INSTR_APERTURE 0x2a13 +#define regCP_GFX_RS64_LOCAL_INSTR_APERTURE_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE 0x2a14 +#define regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO 0x2a15 +#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI 0x2a16 +#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 +#define regCP_GFX_RS64_PERFCOUNT_CNTL0 0x2a1a +#define regCP_GFX_RS64_PERFCOUNT_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_PERFCOUNT_CNTL1 0x2a1b +#define regCP_GFX_RS64_PERFCOUNT_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_MIP_LO0 0x2a1c +#define regCP_GFX_RS64_MIP_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_MIP_LO1 0x2a1d +#define regCP_GFX_RS64_MIP_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_MIP_HI0 0x2a1e +#define regCP_GFX_RS64_MIP_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_MIP_HI1 0x2a1f +#define regCP_GFX_RS64_MIP_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_MTIMECMP_LO0 0x2a20 +#define regCP_GFX_RS64_MTIMECMP_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_MTIMECMP_LO1 0x2a21 +#define regCP_GFX_RS64_MTIMECMP_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_MTIMECMP_HI0 0x2a22 +#define regCP_GFX_RS64_MTIMECMP_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_MTIMECMP_HI1 0x2a23 +#define regCP_GFX_RS64_MTIMECMP_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP0_LO0 0x2a24 +#define regCP_GFX_RS64_GP0_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP0_LO1 0x2a25 +#define regCP_GFX_RS64_GP0_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP0_HI0 0x2a26 +#define regCP_GFX_RS64_GP0_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP0_HI1 0x2a27 +#define regCP_GFX_RS64_GP0_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP1_LO0 0x2a28 +#define regCP_GFX_RS64_GP1_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP1_LO1 0x2a29 +#define regCP_GFX_RS64_GP1_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP1_HI0 0x2a2a +#define regCP_GFX_RS64_GP1_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP1_HI1 0x2a2b +#define regCP_GFX_RS64_GP1_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP2_LO0 0x2a2c +#define regCP_GFX_RS64_GP2_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP2_LO1 0x2a2d +#define regCP_GFX_RS64_GP2_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP2_HI0 0x2a2e +#define regCP_GFX_RS64_GP2_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP2_HI1 0x2a2f +#define regCP_GFX_RS64_GP2_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP3_LO0 0x2a30 +#define regCP_GFX_RS64_GP3_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP3_LO1 0x2a31 +#define regCP_GFX_RS64_GP3_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP3_HI0 0x2a32 +#define regCP_GFX_RS64_GP3_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP3_HI1 0x2a33 +#define regCP_GFX_RS64_GP3_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP4_LO0 0x2a34 +#define regCP_GFX_RS64_GP4_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP4_LO1 0x2a35 +#define regCP_GFX_RS64_GP4_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP4_HI0 0x2a36 +#define regCP_GFX_RS64_GP4_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP4_HI1 0x2a37 +#define regCP_GFX_RS64_GP4_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP5_LO0 0x2a38 +#define regCP_GFX_RS64_GP5_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP5_LO1 0x2a39 +#define regCP_GFX_RS64_GP5_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP5_HI0 0x2a3a +#define regCP_GFX_RS64_GP5_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP5_HI1 0x2a3b +#define regCP_GFX_RS64_GP5_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP6_LO 0x2a3c +#define regCP_GFX_RS64_GP6_LO_BASE_IDX 1 +#define regCP_GFX_RS64_GP6_HI 0x2a3d +#define regCP_GFX_RS64_GP6_HI_BASE_IDX 1 +#define regCP_GFX_RS64_GP7_LO 0x2a3e +#define regCP_GFX_RS64_GP7_LO_BASE_IDX 1 +#define regCP_GFX_RS64_GP7_HI 0x2a3f +#define regCP_GFX_RS64_GP7_HI_BASE_IDX 1 +#define regCP_GFX_RS64_GP8_LO 0x2a40 +#define regCP_GFX_RS64_GP8_LO_BASE_IDX 1 +#define regCP_GFX_RS64_GP8_HI 0x2a41 +#define regCP_GFX_RS64_GP8_HI_BASE_IDX 1 +#define regCP_GFX_RS64_GP9_LO 0x2a42 +#define regCP_GFX_RS64_GP9_LO_BASE_IDX 1 +#define regCP_GFX_RS64_GP9_HI 0x2a43 +#define regCP_GFX_RS64_GP9_HI_BASE_IDX 1 +#define regCP_GFX_RS64_INSTR_PNTR0 0x2a44 +#define regCP_GFX_RS64_INSTR_PNTR0_BASE_IDX 1 +#define regCP_GFX_RS64_INSTR_PNTR1 0x2a45 +#define regCP_GFX_RS64_INSTR_PNTR1_BASE_IDX 1 +#define regCP_GFX_RS64_PENDING_INTERRUPT0 0x2a46 +#define regCP_GFX_RS64_PENDING_INTERRUPT0_BASE_IDX 1 +#define regCP_GFX_RS64_PENDING_INTERRUPT1 0x2a47 +#define regCP_GFX_RS64_PENDING_INTERRUPT1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_BASE0 0x2a49 +#define regCP_GFX_RS64_DC_APERTURE0_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_MASK0 0x2a4a +#define regCP_GFX_RS64_DC_APERTURE0_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_CNTL0 0x2a4b +#define regCP_GFX_RS64_DC_APERTURE0_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_BASE0 0x2a4c +#define regCP_GFX_RS64_DC_APERTURE1_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_MASK0 0x2a4d +#define regCP_GFX_RS64_DC_APERTURE1_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_CNTL0 0x2a4e +#define regCP_GFX_RS64_DC_APERTURE1_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_BASE0 0x2a4f +#define regCP_GFX_RS64_DC_APERTURE2_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_MASK0 0x2a50 +#define regCP_GFX_RS64_DC_APERTURE2_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_CNTL0 0x2a51 +#define regCP_GFX_RS64_DC_APERTURE2_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_BASE0 0x2a52 +#define regCP_GFX_RS64_DC_APERTURE3_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_MASK0 0x2a53 +#define regCP_GFX_RS64_DC_APERTURE3_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_CNTL0 0x2a54 +#define regCP_GFX_RS64_DC_APERTURE3_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_BASE0 0x2a55 +#define regCP_GFX_RS64_DC_APERTURE4_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_MASK0 0x2a56 +#define regCP_GFX_RS64_DC_APERTURE4_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_CNTL0 0x2a57 +#define regCP_GFX_RS64_DC_APERTURE4_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_BASE0 0x2a58 +#define regCP_GFX_RS64_DC_APERTURE5_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_MASK0 0x2a59 +#define regCP_GFX_RS64_DC_APERTURE5_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_CNTL0 0x2a5a +#define regCP_GFX_RS64_DC_APERTURE5_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_BASE0 0x2a5b +#define regCP_GFX_RS64_DC_APERTURE6_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_MASK0 0x2a5c +#define regCP_GFX_RS64_DC_APERTURE6_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_CNTL0 0x2a5d +#define regCP_GFX_RS64_DC_APERTURE6_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_BASE0 0x2a5e +#define regCP_GFX_RS64_DC_APERTURE7_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_MASK0 0x2a5f +#define regCP_GFX_RS64_DC_APERTURE7_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_CNTL0 0x2a60 +#define regCP_GFX_RS64_DC_APERTURE7_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_BASE0 0x2a61 +#define regCP_GFX_RS64_DC_APERTURE8_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_MASK0 0x2a62 +#define regCP_GFX_RS64_DC_APERTURE8_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_CNTL0 0x2a63 +#define regCP_GFX_RS64_DC_APERTURE8_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_BASE0 0x2a64 +#define regCP_GFX_RS64_DC_APERTURE9_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_MASK0 0x2a65 +#define regCP_GFX_RS64_DC_APERTURE9_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_CNTL0 0x2a66 +#define regCP_GFX_RS64_DC_APERTURE9_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_BASE0 0x2a67 +#define regCP_GFX_RS64_DC_APERTURE10_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_MASK0 0x2a68 +#define regCP_GFX_RS64_DC_APERTURE10_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_CNTL0 0x2a69 +#define regCP_GFX_RS64_DC_APERTURE10_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_BASE0 0x2a6a +#define regCP_GFX_RS64_DC_APERTURE11_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_MASK0 0x2a6b +#define regCP_GFX_RS64_DC_APERTURE11_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_CNTL0 0x2a6c +#define regCP_GFX_RS64_DC_APERTURE11_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_BASE0 0x2a6d +#define regCP_GFX_RS64_DC_APERTURE12_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_MASK0 0x2a6e +#define regCP_GFX_RS64_DC_APERTURE12_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_CNTL0 0x2a6f +#define regCP_GFX_RS64_DC_APERTURE12_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_BASE0 0x2a70 +#define regCP_GFX_RS64_DC_APERTURE13_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_MASK0 0x2a71 +#define regCP_GFX_RS64_DC_APERTURE13_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_CNTL0 0x2a72 +#define regCP_GFX_RS64_DC_APERTURE13_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_BASE0 0x2a73 +#define regCP_GFX_RS64_DC_APERTURE14_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_MASK0 0x2a74 +#define regCP_GFX_RS64_DC_APERTURE14_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_CNTL0 0x2a75 +#define regCP_GFX_RS64_DC_APERTURE14_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_BASE0 0x2a76 +#define regCP_GFX_RS64_DC_APERTURE15_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_MASK0 0x2a77 +#define regCP_GFX_RS64_DC_APERTURE15_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_CNTL0 0x2a78 +#define regCP_GFX_RS64_DC_APERTURE15_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_BASE1 0x2a79 +#define regCP_GFX_RS64_DC_APERTURE0_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_MASK1 0x2a7a +#define regCP_GFX_RS64_DC_APERTURE0_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_CNTL1 0x2a7b +#define regCP_GFX_RS64_DC_APERTURE0_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_BASE1 0x2a7c +#define regCP_GFX_RS64_DC_APERTURE1_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_MASK1 0x2a7d +#define regCP_GFX_RS64_DC_APERTURE1_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_CNTL1 0x2a7e +#define regCP_GFX_RS64_DC_APERTURE1_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_BASE1 0x2a7f +#define regCP_GFX_RS64_DC_APERTURE2_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_MASK1 0x2a80 +#define regCP_GFX_RS64_DC_APERTURE2_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_CNTL1 0x2a81 +#define regCP_GFX_RS64_DC_APERTURE2_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_BASE1 0x2a82 +#define regCP_GFX_RS64_DC_APERTURE3_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_MASK1 0x2a83 +#define regCP_GFX_RS64_DC_APERTURE3_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_CNTL1 0x2a84 +#define regCP_GFX_RS64_DC_APERTURE3_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_BASE1 0x2a85 +#define regCP_GFX_RS64_DC_APERTURE4_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_MASK1 0x2a86 +#define regCP_GFX_RS64_DC_APERTURE4_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_CNTL1 0x2a87 +#define regCP_GFX_RS64_DC_APERTURE4_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_BASE1 0x2a88 +#define regCP_GFX_RS64_DC_APERTURE5_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_MASK1 0x2a89 +#define regCP_GFX_RS64_DC_APERTURE5_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_CNTL1 0x2a8a +#define regCP_GFX_RS64_DC_APERTURE5_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_BASE1 0x2a8b +#define regCP_GFX_RS64_DC_APERTURE6_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_MASK1 0x2a8c +#define regCP_GFX_RS64_DC_APERTURE6_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_CNTL1 0x2a8d +#define regCP_GFX_RS64_DC_APERTURE6_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_BASE1 0x2a8e +#define regCP_GFX_RS64_DC_APERTURE7_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_MASK1 0x2a8f +#define regCP_GFX_RS64_DC_APERTURE7_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_CNTL1 0x2a90 +#define regCP_GFX_RS64_DC_APERTURE7_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_BASE1 0x2a91 +#define regCP_GFX_RS64_DC_APERTURE8_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_MASK1 0x2a92 +#define regCP_GFX_RS64_DC_APERTURE8_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_CNTL1 0x2a93 +#define regCP_GFX_RS64_DC_APERTURE8_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_BASE1 0x2a94 +#define regCP_GFX_RS64_DC_APERTURE9_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_MASK1 0x2a95 +#define regCP_GFX_RS64_DC_APERTURE9_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_CNTL1 0x2a96 +#define regCP_GFX_RS64_DC_APERTURE9_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_BASE1 0x2a97 +#define regCP_GFX_RS64_DC_APERTURE10_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_MASK1 0x2a98 +#define regCP_GFX_RS64_DC_APERTURE10_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_CNTL1 0x2a99 +#define regCP_GFX_RS64_DC_APERTURE10_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_BASE1 0x2a9a +#define regCP_GFX_RS64_DC_APERTURE11_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_MASK1 0x2a9b +#define regCP_GFX_RS64_DC_APERTURE11_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_CNTL1 0x2a9c +#define regCP_GFX_RS64_DC_APERTURE11_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_BASE1 0x2a9d +#define regCP_GFX_RS64_DC_APERTURE12_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_MASK1 0x2a9e +#define regCP_GFX_RS64_DC_APERTURE12_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_CNTL1 0x2a9f +#define regCP_GFX_RS64_DC_APERTURE12_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_BASE1 0x2aa0 +#define regCP_GFX_RS64_DC_APERTURE13_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_MASK1 0x2aa1 +#define regCP_GFX_RS64_DC_APERTURE13_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_CNTL1 0x2aa2 +#define regCP_GFX_RS64_DC_APERTURE13_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_BASE1 0x2aa3 +#define regCP_GFX_RS64_DC_APERTURE14_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_MASK1 0x2aa4 +#define regCP_GFX_RS64_DC_APERTURE14_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_CNTL1 0x2aa5 +#define regCP_GFX_RS64_DC_APERTURE14_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_BASE1 0x2aa6 +#define regCP_GFX_RS64_DC_APERTURE15_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_MASK1 0x2aa7 +#define regCP_GFX_RS64_DC_APERTURE15_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_CNTL1 0x2aa8 +#define regCP_GFX_RS64_DC_APERTURE15_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_INTERRUPT1 0x2aac +#define regCP_GFX_RS64_INTERRUPT1_BASE_IDX 1 + + +// addressBlock: gc_gl1dec +// base address: 0x33400 +#define regGL1_DRAM_BURST_MASK 0x2d02 +#define regGL1_DRAM_BURST_MASK_BASE_IDX 1 +#define regGL1_ARB_STATUS 0x2d03 +#define regGL1_ARB_STATUS_BASE_IDX 1 +#define regGL1I_GL1R_REP_FGCG_OVERRIDE 0x2d05 +#define regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX 1 +#define regGL1C_STATUS 0x2d41 +#define regGL1C_STATUS_BASE_IDX 1 +#define regGL1C_UTCL0_CNTL1 0x2d42 +#define regGL1C_UTCL0_CNTL1_BASE_IDX 1 +#define regGL1C_UTCL0_CNTL2 0x2d43 +#define regGL1C_UTCL0_CNTL2_BASE_IDX 1 +#define regGL1C_UTCL0_STATUS 0x2d44 +#define regGL1C_UTCL0_STATUS_BASE_IDX 1 +#define regGL1C_UTCL0_RETRY 0x2d45 +#define regGL1C_UTCL0_RETRY_BASE_IDX 1 + + +// addressBlock: gc_chdec +// base address: 0x33600 +#define regCH_ARB_CTRL 0x2d80 +#define regCH_ARB_CTRL_BASE_IDX 1 +#define regCH_DRAM_BURST_MASK 0x2d82 +#define regCH_DRAM_BURST_MASK_BASE_IDX 1 +#define regCH_ARB_STATUS 0x2d83 +#define regCH_ARB_STATUS_BASE_IDX 1 +#define regCH_DRAM_BURST_CTRL 0x2d84 +#define regCH_DRAM_BURST_CTRL_BASE_IDX 1 +#define regCHA_CHC_CREDITS 0x2d88 +#define regCHA_CHC_CREDITS_BASE_IDX 1 +#define regCHA_CLIENT_FREE_DELAY 0x2d89 +#define regCHA_CLIENT_FREE_DELAY_BASE_IDX 1 +#define regCHI_CHR_REP_FGCG_OVERRIDE 0x2d8c +#define regCHI_CHR_REP_FGCG_OVERRIDE_BASE_IDX 1 +#define regCH_VC5_ENABLE 0x2d94 +#define regCH_VC5_ENABLE_BASE_IDX 1 +#define regCHC_CTRL 0x2dc0 +#define regCHC_CTRL_BASE_IDX 1 +#define regCHC_STATUS 0x2dc1 +#define regCHC_STATUS_BASE_IDX 1 +#define regCHCG_CTRL 0x2dc2 +#define regCHCG_CTRL_BASE_IDX 1 +#define regCHCG_STATUS 0x2dc3 +#define regCHCG_STATUS_BASE_IDX 1 + + +// addressBlock: gc_gl2dec +// base address: 0x33800 +#define regGL2C_CTRL 0x2e00 +#define regGL2C_CTRL_BASE_IDX 1 +#define regGL2C_CTRL2 0x2e01 +#define regGL2C_CTRL2_BASE_IDX 1 +#define regGL2C_ADDR_MATCH_MASK 0x2e03 +#define regGL2C_ADDR_MATCH_MASK_BASE_IDX 1 +#define regGL2C_ADDR_MATCH_SIZE 0x2e04 +#define regGL2C_ADDR_MATCH_SIZE_BASE_IDX 1 +#define regGL2C_WBINVL2 0x2e05 +#define regGL2C_WBINVL2_BASE_IDX 1 +#define regGL2C_SOFT_RESET 0x2e06 +#define regGL2C_SOFT_RESET_BASE_IDX 1 +#define regGL2C_CM_CTRL0 0x2e07 +#define regGL2C_CM_CTRL0_BASE_IDX 1 +#define regGL2C_CM_CTRL1 0x2e08 +#define regGL2C_CM_CTRL1_BASE_IDX 1 +#define regGL2C_CM_STALL 0x2e09 +#define regGL2C_CM_STALL_BASE_IDX 1 +#define regGL2C_CTRL3 0x2e0c +#define regGL2C_CTRL3_BASE_IDX 1 +#define regGL2C_LB_CTR_CTRL 0x2e0d +#define regGL2C_LB_CTR_CTRL_BASE_IDX 1 +#define regGL2C_LB_DATA0 0x2e0e +#define regGL2C_LB_DATA0_BASE_IDX 1 +#define regGL2C_LB_DATA1 0x2e0f +#define regGL2C_LB_DATA1_BASE_IDX 1 +#define regGL2C_LB_DATA2 0x2e10 +#define regGL2C_LB_DATA2_BASE_IDX 1 +#define regGL2C_LB_DATA3 0x2e11 +#define regGL2C_LB_DATA3_BASE_IDX 1 +#define regGL2C_LB_CTR_SEL0 0x2e12 +#define regGL2C_LB_CTR_SEL0_BASE_IDX 1 +#define regGL2C_LB_CTR_SEL1 0x2e13 +#define regGL2C_LB_CTR_SEL1_BASE_IDX 1 +#define regGL2C_CTRL4 0x2e17 +#define regGL2C_CTRL4_BASE_IDX 1 +#define regGL2C_DISCARD_STALL_CTRL 0x2e18 +#define regGL2C_DISCARD_STALL_CTRL_BASE_IDX 1 +#define regGL2A_ADDR_MATCH_CTRL 0x2e20 +#define regGL2A_ADDR_MATCH_CTRL_BASE_IDX 1 +#define regGL2A_ADDR_MATCH_MASK 0x2e21 +#define regGL2A_ADDR_MATCH_MASK_BASE_IDX 1 +#define regGL2A_ADDR_MATCH_SIZE 0x2e22 +#define regGL2A_ADDR_MATCH_SIZE_BASE_IDX 1 +#define regGL2A_PRIORITY_CTRL 0x2e23 +#define regGL2A_PRIORITY_CTRL_BASE_IDX 1 +#define regGL2A_RESP_THROTTLE_CTRL 0x2e2a +#define regGL2A_RESP_THROTTLE_CTRL_BASE_IDX 1 + + +// addressBlock: gc_gl1hdec +// base address: 0x33900 +#define regGL1H_ARB_CTRL 0x2e40 +#define regGL1H_ARB_CTRL_BASE_IDX 1 +#define regGL1H_GL1_CREDITS 0x2e41 +#define regGL1H_GL1_CREDITS_BASE_IDX 1 +#define regGL1H_BURST_MASK 0x2e42 +#define regGL1H_BURST_MASK_BASE_IDX 1 +#define regGL1H_BURST_CTRL 0x2e43 +#define regGL1H_BURST_CTRL_BASE_IDX 1 +#define regGL1H_ARB_STATUS 0x2e44 +#define regGL1H_ARB_STATUS_BASE_IDX 1 + + +// addressBlock: gc_perfddec +// base address: 0x34000 +#define regCPG_PERFCOUNTER1_LO 0x3000 +#define regCPG_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCPG_PERFCOUNTER1_HI 0x3001 +#define regCPG_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_LO 0x3002 +#define regCPG_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_HI 0x3003 +#define regCPG_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCPC_PERFCOUNTER1_LO 0x3004 +#define regCPC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCPC_PERFCOUNTER1_HI 0x3005 +#define regCPC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_LO 0x3006 +#define regCPC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_HI 0x3007 +#define regCPC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCPF_PERFCOUNTER1_LO 0x3008 +#define regCPF_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCPF_PERFCOUNTER1_HI 0x3009 +#define regCPF_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_LO 0x300a +#define regCPF_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_HI 0x300b +#define regCPF_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCPF_LATENCY_STATS_DATA 0x300c +#define regCPF_LATENCY_STATS_DATA_BASE_IDX 1 +#define regCPG_LATENCY_STATS_DATA 0x300d +#define regCPG_LATENCY_STATS_DATA_BASE_IDX 1 +#define regCPC_LATENCY_STATS_DATA 0x300e +#define regCPC_LATENCY_STATS_DATA_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_LO 0x3040 +#define regGRBM_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_HI 0x3041 +#define regGRBM_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_LO 0x3043 +#define regGRBM_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_HI 0x3044 +#define regGRBM_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGRBM_SE0_PERFCOUNTER_LO 0x3045 +#define regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE0_PERFCOUNTER_HI 0x3046 +#define regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX 1 +#define regGRBM_SE1_PERFCOUNTER_LO 0x3047 +#define regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE1_PERFCOUNTER_HI 0x3048 +#define regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX 1 +#define regGRBM_SE2_PERFCOUNTER_LO 0x3049 +#define regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE2_PERFCOUNTER_HI 0x304a +#define regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX 1 +#define regGRBM_SE3_PERFCOUNTER_LO 0x304b +#define regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE3_PERFCOUNTER_HI 0x304c +#define regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX 1 +#define regGRBM_SE4_PERFCOUNTER_LO 0x304d +#define regGRBM_SE4_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE4_PERFCOUNTER_HI 0x304e +#define regGRBM_SE4_PERFCOUNTER_HI_BASE_IDX 1 +#define regGRBM_SE5_PERFCOUNTER_LO 0x304f +#define regGRBM_SE5_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE5_PERFCOUNTER_HI 0x3050 +#define regGRBM_SE5_PERFCOUNTER_HI_BASE_IDX 1 +#define regGRBM_SE6_PERFCOUNTER_LO 0x3051 +#define regGRBM_SE6_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE6_PERFCOUNTER_HI 0x3052 +#define regGRBM_SE6_PERFCOUNTER_HI_BASE_IDX 1 +#define regGE1_PERFCOUNTER0_LO 0x30a4 +#define regGE1_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGE1_PERFCOUNTER0_HI 0x30a5 +#define regGE1_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGE1_PERFCOUNTER1_LO 0x30a6 +#define regGE1_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGE1_PERFCOUNTER1_HI 0x30a7 +#define regGE1_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGE1_PERFCOUNTER2_LO 0x30a8 +#define regGE1_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGE1_PERFCOUNTER2_HI 0x30a9 +#define regGE1_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGE1_PERFCOUNTER3_LO 0x30aa +#define regGE1_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGE1_PERFCOUNTER3_HI 0x30ab +#define regGE1_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER0_LO 0x30ac +#define regGE2_DIST_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER0_HI 0x30ad +#define regGE2_DIST_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER1_LO 0x30ae +#define regGE2_DIST_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER1_HI 0x30af +#define regGE2_DIST_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER2_LO 0x30b0 +#define regGE2_DIST_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER2_HI 0x30b1 +#define regGE2_DIST_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER3_LO 0x30b2 +#define regGE2_DIST_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER3_HI 0x30b3 +#define regGE2_DIST_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER0_LO 0x30b4 +#define regGE2_SE_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER0_HI 0x30b5 +#define regGE2_SE_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER1_LO 0x30b6 +#define regGE2_SE_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER1_HI 0x30b7 +#define regGE2_SE_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER2_LO 0x30b8 +#define regGE2_SE_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER2_HI 0x30b9 +#define regGE2_SE_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER3_LO 0x30ba +#define regGE2_SE_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER3_HI 0x30bb +#define regGE2_SE_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_LO 0x3100 +#define regPA_SU_PERFCOUNTER0_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_HI 0x3101 +#define regPA_SU_PERFCOUNTER0_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_LO 0x3102 +#define regPA_SU_PERFCOUNTER1_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_HI 0x3103 +#define regPA_SU_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_LO 0x3104 +#define regPA_SU_PERFCOUNTER2_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_HI 0x3105 +#define regPA_SU_PERFCOUNTER2_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_LO 0x3106 +#define regPA_SU_PERFCOUNTER3_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_HI 0x3107 +#define regPA_SU_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_LO 0x3140 +#define regPA_SC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_HI 0x3141 +#define regPA_SC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER1_LO 0x3142 +#define regPA_SC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER1_HI 0x3143 +#define regPA_SC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER2_LO 0x3144 +#define regPA_SC_PERFCOUNTER2_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER2_HI 0x3145 +#define regPA_SC_PERFCOUNTER2_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER3_LO 0x3146 +#define regPA_SC_PERFCOUNTER3_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER3_HI 0x3147 +#define regPA_SC_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER4_LO 0x3148 +#define regPA_SC_PERFCOUNTER4_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER4_HI 0x3149 +#define regPA_SC_PERFCOUNTER4_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER5_LO 0x314a +#define regPA_SC_PERFCOUNTER5_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER5_HI 0x314b +#define regPA_SC_PERFCOUNTER5_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER6_LO 0x314c +#define regPA_SC_PERFCOUNTER6_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER6_HI 0x314d +#define regPA_SC_PERFCOUNTER6_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER7_LO 0x314e +#define regPA_SC_PERFCOUNTER7_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER7_HI 0x314f +#define regPA_SC_PERFCOUNTER7_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_HI 0x3180 +#define regSPI_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_LO 0x3181 +#define regSPI_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_HI 0x3182 +#define regSPI_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_LO 0x3183 +#define regSPI_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_HI 0x3184 +#define regSPI_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_LO 0x3185 +#define regSPI_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_HI 0x3186 +#define regSPI_PERFCOUNTER3_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_LO 0x3187 +#define regSPI_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER4_HI 0x3188 +#define regSPI_PERFCOUNTER4_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER4_LO 0x3189 +#define regSPI_PERFCOUNTER4_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER5_HI 0x318a +#define regSPI_PERFCOUNTER5_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER5_LO 0x318b +#define regSPI_PERFCOUNTER5_LO_BASE_IDX 1 +#define regPC_PERFCOUNTER0_HI 0x318c +#define regPC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regPC_PERFCOUNTER0_LO 0x318d +#define regPC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regPC_PERFCOUNTER1_HI 0x318e +#define regPC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPC_PERFCOUNTER1_LO 0x318f +#define regPC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regPC_PERFCOUNTER2_HI 0x3190 +#define regPC_PERFCOUNTER2_HI_BASE_IDX 1 +#define regPC_PERFCOUNTER2_LO 0x3191 +#define regPC_PERFCOUNTER2_LO_BASE_IDX 1 +#define regPC_PERFCOUNTER3_HI 0x3192 +#define regPC_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPC_PERFCOUNTER3_LO 0x3193 +#define regPC_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER0_LO 0x31c0 +#define regSQ_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER1_LO 0x31c2 +#define regSQ_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER2_LO 0x31c4 +#define regSQ_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER3_LO 0x31c6 +#define regSQ_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER4_LO 0x31c8 +#define regSQ_PERFCOUNTER4_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER5_LO 0x31ca +#define regSQ_PERFCOUNTER5_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER6_LO 0x31cc +#define regSQ_PERFCOUNTER6_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER7_LO 0x31ce +#define regSQ_PERFCOUNTER7_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER0_LO 0x31e4 +#define regSQG_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER0_HI 0x31e5 +#define regSQG_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER1_LO 0x31e6 +#define regSQG_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER1_HI 0x31e7 +#define regSQG_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER2_LO 0x31e8 +#define regSQG_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER2_HI 0x31e9 +#define regSQG_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER3_LO 0x31ea +#define regSQG_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER3_HI 0x31eb +#define regSQG_PERFCOUNTER3_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER4_LO 0x31ec +#define regSQG_PERFCOUNTER4_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER4_HI 0x31ed +#define regSQG_PERFCOUNTER4_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER5_LO 0x31ee +#define regSQG_PERFCOUNTER5_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER5_HI 0x31ef +#define regSQG_PERFCOUNTER5_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER6_LO 0x31f0 +#define regSQG_PERFCOUNTER6_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER6_HI 0x31f1 +#define regSQG_PERFCOUNTER6_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER7_LO 0x31f2 +#define regSQG_PERFCOUNTER7_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER7_HI 0x31f3 +#define regSQG_PERFCOUNTER7_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER0_LO 0x3240 +#define regSX_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER0_HI 0x3241 +#define regSX_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER1_LO 0x3242 +#define regSX_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER1_HI 0x3243 +#define regSX_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER2_LO 0x3244 +#define regSX_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER2_HI 0x3245 +#define regSX_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER3_LO 0x3246 +#define regSX_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER3_HI 0x3247 +#define regSX_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGCEA_PERFCOUNTER2_LO 0x3260 +#define regGCEA_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGCEA_PERFCOUNTER2_HI 0x3261 +#define regGCEA_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGCEA_PERFCOUNTER_LO 0x3262 +#define regGCEA_PERFCOUNTER_LO_BASE_IDX 1 +#define regGCEA_PERFCOUNTER_HI 0x3263 +#define regGCEA_PERFCOUNTER_HI_BASE_IDX 1 +#define regGDS_PERFCOUNTER0_LO 0x3280 +#define regGDS_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGDS_PERFCOUNTER0_HI 0x3281 +#define regGDS_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGDS_PERFCOUNTER1_LO 0x3282 +#define regGDS_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGDS_PERFCOUNTER1_HI 0x3283 +#define regGDS_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGDS_PERFCOUNTER2_LO 0x3284 +#define regGDS_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGDS_PERFCOUNTER2_HI 0x3285 +#define regGDS_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGDS_PERFCOUNTER3_LO 0x3286 +#define regGDS_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGDS_PERFCOUNTER3_HI 0x3287 +#define regGDS_PERFCOUNTER3_HI_BASE_IDX 1 +#define regTA_PERFCOUNTER0_LO 0x32c0 +#define regTA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTA_PERFCOUNTER0_HI 0x32c1 +#define regTA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTA_PERFCOUNTER1_LO 0x32c2 +#define regTA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTA_PERFCOUNTER1_HI 0x32c3 +#define regTA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTD_PERFCOUNTER0_LO 0x3300 +#define regTD_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTD_PERFCOUNTER0_HI 0x3301 +#define regTD_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTD_PERFCOUNTER1_LO 0x3302 +#define regTD_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTD_PERFCOUNTER1_HI 0x3303 +#define regTD_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_LO 0x3340 +#define regTCP_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_HI 0x3341 +#define regTCP_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_LO 0x3342 +#define regTCP_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_HI 0x3343 +#define regTCP_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER2_LO 0x3344 +#define regTCP_PERFCOUNTER2_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER2_HI 0x3345 +#define regTCP_PERFCOUNTER2_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER3_LO 0x3346 +#define regTCP_PERFCOUNTER3_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER3_HI 0x3347 +#define regTCP_PERFCOUNTER3_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER_FILTER 0x3348 +#define regTCP_PERFCOUNTER_FILTER_BASE_IDX 1 +#define regTCP_PERFCOUNTER_FILTER2 0x3349 +#define regTCP_PERFCOUNTER_FILTER2_BASE_IDX 1 +#define regTCP_PERFCOUNTER_FILTER_EN 0x334a +#define regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX 1 +#define regGL2C_PERFCOUNTER0_LO 0x3380 +#define regGL2C_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL2C_PERFCOUNTER0_HI 0x3381 +#define regGL2C_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL2C_PERFCOUNTER1_LO 0x3382 +#define regGL2C_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL2C_PERFCOUNTER1_HI 0x3383 +#define regGL2C_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL2C_PERFCOUNTER2_LO 0x3384 +#define regGL2C_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL2C_PERFCOUNTER2_HI 0x3385 +#define regGL2C_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL2C_PERFCOUNTER3_LO 0x3386 +#define regGL2C_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL2C_PERFCOUNTER3_HI 0x3387 +#define regGL2C_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGL2A_PERFCOUNTER0_LO 0x3390 +#define regGL2A_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL2A_PERFCOUNTER0_HI 0x3391 +#define regGL2A_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL2A_PERFCOUNTER1_LO 0x3392 +#define regGL2A_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL2A_PERFCOUNTER1_HI 0x3393 +#define regGL2A_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL2A_PERFCOUNTER2_LO 0x3394 +#define regGL2A_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL2A_PERFCOUNTER2_HI 0x3395 +#define regGL2A_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL2A_PERFCOUNTER3_LO 0x3396 +#define regGL2A_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL2A_PERFCOUNTER3_HI 0x3397 +#define regGL2A_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGL1C_PERFCOUNTER0_LO 0x33a0 +#define regGL1C_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL1C_PERFCOUNTER0_HI 0x33a1 +#define regGL1C_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL1C_PERFCOUNTER1_LO 0x33a2 +#define regGL1C_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL1C_PERFCOUNTER1_HI 0x33a3 +#define regGL1C_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL1C_PERFCOUNTER2_LO 0x33a4 +#define regGL1C_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL1C_PERFCOUNTER2_HI 0x33a5 +#define regGL1C_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL1C_PERFCOUNTER3_LO 0x33a6 +#define regGL1C_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL1C_PERFCOUNTER3_HI 0x33a7 +#define regGL1C_PERFCOUNTER3_HI_BASE_IDX 1 +#define regCHC_PERFCOUNTER0_LO 0x33c0 +#define regCHC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCHC_PERFCOUNTER0_HI 0x33c1 +#define regCHC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCHC_PERFCOUNTER1_LO 0x33c2 +#define regCHC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCHC_PERFCOUNTER1_HI 0x33c3 +#define regCHC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCHC_PERFCOUNTER2_LO 0x33c4 +#define regCHC_PERFCOUNTER2_LO_BASE_IDX 1 +#define regCHC_PERFCOUNTER2_HI 0x33c5 +#define regCHC_PERFCOUNTER2_HI_BASE_IDX 1 +#define regCHC_PERFCOUNTER3_LO 0x33c6 +#define regCHC_PERFCOUNTER3_LO_BASE_IDX 1 +#define regCHC_PERFCOUNTER3_HI 0x33c7 +#define regCHC_PERFCOUNTER3_HI_BASE_IDX 1 +#define regCHCG_PERFCOUNTER0_LO 0x33c8 +#define regCHCG_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCHCG_PERFCOUNTER0_HI 0x33c9 +#define regCHCG_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCHCG_PERFCOUNTER1_LO 0x33ca +#define regCHCG_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCHCG_PERFCOUNTER1_HI 0x33cb +#define regCHCG_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCHCG_PERFCOUNTER2_LO 0x33cc +#define regCHCG_PERFCOUNTER2_LO_BASE_IDX 1 +#define regCHCG_PERFCOUNTER2_HI 0x33cd +#define regCHCG_PERFCOUNTER2_HI_BASE_IDX 1 +#define regCHCG_PERFCOUNTER3_LO 0x33ce +#define regCHCG_PERFCOUNTER3_LO_BASE_IDX 1 +#define regCHCG_PERFCOUNTER3_HI 0x33cf +#define regCHCG_PERFCOUNTER3_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER0_LO 0x3406 +#define regCB_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER0_HI 0x3407 +#define regCB_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER1_LO 0x3408 +#define regCB_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER1_HI 0x3409 +#define regCB_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER2_LO 0x340a +#define regCB_PERFCOUNTER2_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER2_HI 0x340b +#define regCB_PERFCOUNTER2_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER3_LO 0x340c +#define regCB_PERFCOUNTER3_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER3_HI 0x340d +#define regCB_PERFCOUNTER3_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER0_LO 0x3440 +#define regDB_PERFCOUNTER0_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER0_HI 0x3441 +#define regDB_PERFCOUNTER0_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER1_LO 0x3442 +#define regDB_PERFCOUNTER1_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER1_HI 0x3443 +#define regDB_PERFCOUNTER1_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER2_LO 0x3444 +#define regDB_PERFCOUNTER2_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER2_HI 0x3445 +#define regDB_PERFCOUNTER2_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER3_LO 0x3446 +#define regDB_PERFCOUNTER3_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER3_HI 0x3447 +#define regDB_PERFCOUNTER3_HI_BASE_IDX 1 +#define regRLC_PERFCOUNTER0_LO 0x3480 +#define regRLC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regRLC_PERFCOUNTER0_HI 0x3481 +#define regRLC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regRLC_PERFCOUNTER1_LO 0x3482 +#define regRLC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regRLC_PERFCOUNTER1_HI 0x3483 +#define regRLC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_LO 0x34c0 +#define regRMI_PERFCOUNTER0_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_HI 0x34c1 +#define regRMI_PERFCOUNTER0_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER1_LO 0x34c2 +#define regRMI_PERFCOUNTER1_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER1_HI 0x34c3 +#define regRMI_PERFCOUNTER1_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_LO 0x34c4 +#define regRMI_PERFCOUNTER2_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_HI 0x34c5 +#define regRMI_PERFCOUNTER2_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER3_LO 0x34c6 +#define regRMI_PERFCOUNTER3_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER3_HI 0x34c7 +#define regRMI_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGCR_PERFCOUNTER0_LO 0x3520 +#define regGCR_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGCR_PERFCOUNTER0_HI 0x3521 +#define regGCR_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGCR_PERFCOUNTER1_LO 0x3522 +#define regGCR_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGCR_PERFCOUNTER1_HI 0x3523 +#define regGCR_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER0_LO 0x3580 +#define regPA_PH_PERFCOUNTER0_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER0_HI 0x3581 +#define regPA_PH_PERFCOUNTER0_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER1_LO 0x3582 +#define regPA_PH_PERFCOUNTER1_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER1_HI 0x3583 +#define regPA_PH_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER2_LO 0x3584 +#define regPA_PH_PERFCOUNTER2_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER2_HI 0x3585 +#define regPA_PH_PERFCOUNTER2_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER3_LO 0x3586 +#define regPA_PH_PERFCOUNTER3_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER3_HI 0x3587 +#define regPA_PH_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER4_LO 0x3588 +#define regPA_PH_PERFCOUNTER4_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER4_HI 0x3589 +#define regPA_PH_PERFCOUNTER4_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER5_LO 0x358a +#define regPA_PH_PERFCOUNTER5_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER5_HI 0x358b +#define regPA_PH_PERFCOUNTER5_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER6_LO 0x358c +#define regPA_PH_PERFCOUNTER6_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER6_HI 0x358d +#define regPA_PH_PERFCOUNTER6_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER7_LO 0x358e +#define regPA_PH_PERFCOUNTER7_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER7_HI 0x358f +#define regPA_PH_PERFCOUNTER7_HI_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER0_LO 0x35a0 +#define regUTCL1_PERFCOUNTER0_LO_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER0_HI 0x35a1 +#define regUTCL1_PERFCOUNTER0_HI_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER1_LO 0x35a2 +#define regUTCL1_PERFCOUNTER1_LO_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER1_HI 0x35a3 +#define regUTCL1_PERFCOUNTER1_HI_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER2_LO 0x35a4 +#define regUTCL1_PERFCOUNTER2_LO_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER2_HI 0x35a5 +#define regUTCL1_PERFCOUNTER2_HI_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER3_LO 0x35a6 +#define regUTCL1_PERFCOUNTER3_LO_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER3_HI 0x35a7 +#define regUTCL1_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGL1A_PERFCOUNTER0_LO 0x35c0 +#define regGL1A_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL1A_PERFCOUNTER0_HI 0x35c1 +#define regGL1A_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL1A_PERFCOUNTER1_LO 0x35c2 +#define regGL1A_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL1A_PERFCOUNTER1_HI 0x35c3 +#define regGL1A_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL1A_PERFCOUNTER2_LO 0x35c4 +#define regGL1A_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL1A_PERFCOUNTER2_HI 0x35c5 +#define regGL1A_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL1A_PERFCOUNTER3_LO 0x35c6 +#define regGL1A_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL1A_PERFCOUNTER3_HI 0x35c7 +#define regGL1A_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGL1H_PERFCOUNTER0_LO 0x35d0 +#define regGL1H_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL1H_PERFCOUNTER0_HI 0x35d1 +#define regGL1H_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL1H_PERFCOUNTER1_LO 0x35d2 +#define regGL1H_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL1H_PERFCOUNTER1_HI 0x35d3 +#define regGL1H_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL1H_PERFCOUNTER2_LO 0x35d4 +#define regGL1H_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL1H_PERFCOUNTER2_HI 0x35d5 +#define regGL1H_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL1H_PERFCOUNTER3_LO 0x35d6 +#define regGL1H_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL1H_PERFCOUNTER3_HI 0x35d7 +#define regGL1H_PERFCOUNTER3_HI_BASE_IDX 1 +#define regCHA_PERFCOUNTER0_LO 0x3600 +#define regCHA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCHA_PERFCOUNTER0_HI 0x3601 +#define regCHA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCHA_PERFCOUNTER1_LO 0x3602 +#define regCHA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCHA_PERFCOUNTER1_HI 0x3603 +#define regCHA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCHA_PERFCOUNTER2_LO 0x3604 +#define regCHA_PERFCOUNTER2_LO_BASE_IDX 1 +#define regCHA_PERFCOUNTER2_HI 0x3605 +#define regCHA_PERFCOUNTER2_HI_BASE_IDX 1 +#define regCHA_PERFCOUNTER3_LO 0x3606 +#define regCHA_PERFCOUNTER3_LO_BASE_IDX 1 +#define regCHA_PERFCOUNTER3_HI 0x3607 +#define regCHA_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGUS_PERFCOUNTER2_LO 0x3640 +#define regGUS_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGUS_PERFCOUNTER2_HI 0x3641 +#define regGUS_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGUS_PERFCOUNTER_LO 0x3642 +#define regGUS_PERFCOUNTER_LO_BASE_IDX 1 +#define regGUS_PERFCOUNTER_HI 0x3643 +#define regGUS_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: gc_perfsdec +// base address: 0x36000 +#define regCPG_PERFCOUNTER1_SELECT 0x3800 +#define regCPG_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_SELECT1 0x3801 +#define regCPG_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_SELECT 0x3802 +#define regCPG_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCPC_PERFCOUNTER1_SELECT 0x3803 +#define regCPC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_SELECT1 0x3804 +#define regCPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCPF_PERFCOUNTER1_SELECT 0x3805 +#define regCPF_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_SELECT1 0x3806 +#define regCPF_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_SELECT 0x3807 +#define regCPF_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCP_PERFMON_CNTL 0x3808 +#define regCP_PERFMON_CNTL_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_SELECT 0x3809 +#define regCPC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCPF_TC_PERF_COUNTER_WINDOW_SELECT 0x380a +#define regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 +#define regCPG_TC_PERF_COUNTER_WINDOW_SELECT 0x380b +#define regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 +#define regCPF_LATENCY_STATS_SELECT 0x380c +#define regCPF_LATENCY_STATS_SELECT_BASE_IDX 1 +#define regCPG_LATENCY_STATS_SELECT 0x380d +#define regCPG_LATENCY_STATS_SELECT_BASE_IDX 1 +#define regCPC_LATENCY_STATS_SELECT 0x380e +#define regCPC_LATENCY_STATS_SELECT_BASE_IDX 1 +#define regCPC_TC_PERF_COUNTER_WINDOW_SELECT 0x380f +#define regCPC_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 +#define regCP_DRAW_OBJECT 0x3810 +#define regCP_DRAW_OBJECT_BASE_IDX 1 +#define regCP_DRAW_OBJECT_COUNTER 0x3811 +#define regCP_DRAW_OBJECT_COUNTER_BASE_IDX 1 +#define regCP_DRAW_WINDOW_MASK_HI 0x3812 +#define regCP_DRAW_WINDOW_MASK_HI_BASE_IDX 1 +#define regCP_DRAW_WINDOW_HI 0x3813 +#define regCP_DRAW_WINDOW_HI_BASE_IDX 1 +#define regCP_DRAW_WINDOW_LO 0x3814 +#define regCP_DRAW_WINDOW_LO_BASE_IDX 1 +#define regCP_DRAW_WINDOW_CNTL 0x3815 +#define regCP_DRAW_WINDOW_CNTL_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_SELECT 0x3840 +#define regGRBM_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_SELECT 0x3841 +#define regGRBM_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGRBM_SE0_PERFCOUNTER_SELECT 0x3842 +#define regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regGRBM_SE1_PERFCOUNTER_SELECT 0x3843 +#define regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regGRBM_SE2_PERFCOUNTER_SELECT 0x3844 +#define regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regGRBM_SE3_PERFCOUNTER_SELECT 0x3845 +#define regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regGRBM_SE4_PERFCOUNTER_SELECT 0x3846 +#define regGRBM_SE4_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regGRBM_SE5_PERFCOUNTER_SELECT 0x3847 +#define regGRBM_SE5_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regGRBM_SE6_PERFCOUNTER_SELECT 0x3848 +#define regGRBM_SE6_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_SELECT_HI 0x384d +#define regGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_SELECT_HI 0x384e +#define regGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX 1 +#define regGE1_PERFCOUNTER0_SELECT 0x38a4 +#define regGE1_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGE1_PERFCOUNTER0_SELECT1 0x38a5 +#define regGE1_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGE1_PERFCOUNTER1_SELECT 0x38a6 +#define regGE1_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGE1_PERFCOUNTER1_SELECT1 0x38a7 +#define regGE1_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGE1_PERFCOUNTER2_SELECT 0x38a8 +#define regGE1_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGE1_PERFCOUNTER2_SELECT1 0x38a9 +#define regGE1_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGE1_PERFCOUNTER3_SELECT 0x38aa +#define regGE1_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGE1_PERFCOUNTER3_SELECT1 0x38ab +#define regGE1_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER0_SELECT 0x38ac +#define regGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER0_SELECT1 0x38ad +#define regGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER1_SELECT 0x38ae +#define regGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER1_SELECT1 0x38af +#define regGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER2_SELECT 0x38b0 +#define regGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER2_SELECT1 0x38b1 +#define regGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER3_SELECT 0x38b2 +#define regGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER3_SELECT1 0x38b3 +#define regGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER0_SELECT 0x38b4 +#define regGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER0_SELECT1 0x38b5 +#define regGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER1_SELECT 0x38b6 +#define regGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER1_SELECT1 0x38b7 +#define regGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER2_SELECT 0x38b8 +#define regGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER2_SELECT1 0x38b9 +#define regGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER3_SELECT 0x38ba +#define regGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER3_SELECT1 0x38bb +#define regGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_SELECT 0x3900 +#define regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_SELECT1 0x3901 +#define regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_SELECT 0x3902 +#define regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_SELECT1 0x3903 +#define regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_SELECT 0x3904 +#define regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_SELECT1 0x3905 +#define regPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_SELECT 0x3906 +#define regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_SELECT1 0x3907 +#define regPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_SELECT 0x3940 +#define regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_SELECT1 0x3941 +#define regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER1_SELECT 0x3942 +#define regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER2_SELECT 0x3943 +#define regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER3_SELECT 0x3944 +#define regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER4_SELECT 0x3945 +#define regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER5_SELECT 0x3946 +#define regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER6_SELECT 0x3947 +#define regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER7_SELECT 0x3948 +#define regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_SELECT 0x3980 +#define regSPI_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_SELECT 0x3981 +#define regSPI_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_SELECT 0x3982 +#define regSPI_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_SELECT 0x3983 +#define regSPI_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_SELECT1 0x3984 +#define regSPI_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_SELECT1 0x3985 +#define regSPI_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_SELECT1 0x3986 +#define regSPI_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_SELECT1 0x3987 +#define regSPI_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER4_SELECT 0x3988 +#define regSPI_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER5_SELECT 0x3989 +#define regSPI_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER_BINS 0x398a +#define regSPI_PERFCOUNTER_BINS_BASE_IDX 1 +#define regPC_PERFCOUNTER0_SELECT 0x398c +#define regPC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regPC_PERFCOUNTER1_SELECT 0x398d +#define regPC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPC_PERFCOUNTER2_SELECT 0x398e +#define regPC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regPC_PERFCOUNTER3_SELECT 0x398f +#define regPC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regPC_PERFCOUNTER0_SELECT1 0x3990 +#define regPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regPC_PERFCOUNTER1_SELECT1 0x3991 +#define regPC_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regPC_PERFCOUNTER2_SELECT1 0x3992 +#define regPC_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regPC_PERFCOUNTER3_SELECT1 0x3993 +#define regPC_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regSQ_PERFCOUNTER0_SELECT 0x39c0 +#define regSQ_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER1_SELECT 0x39c1 +#define regSQ_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER2_SELECT 0x39c2 +#define regSQ_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER3_SELECT 0x39c3 +#define regSQ_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER4_SELECT 0x39c4 +#define regSQ_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER5_SELECT 0x39c5 +#define regSQ_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER6_SELECT 0x39c6 +#define regSQ_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER7_SELECT 0x39c7 +#define regSQ_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER8_SELECT 0x39c8 +#define regSQ_PERFCOUNTER8_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER9_SELECT 0x39c9 +#define regSQ_PERFCOUNTER9_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER10_SELECT 0x39ca +#define regSQ_PERFCOUNTER10_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER11_SELECT 0x39cb +#define regSQ_PERFCOUNTER11_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER12_SELECT 0x39cc +#define regSQ_PERFCOUNTER12_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER13_SELECT 0x39cd +#define regSQ_PERFCOUNTER13_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER14_SELECT 0x39ce +#define regSQ_PERFCOUNTER14_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER15_SELECT 0x39cf +#define regSQ_PERFCOUNTER15_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER0_SELECT 0x39d0 +#define regSQG_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER1_SELECT 0x39d1 +#define regSQG_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER2_SELECT 0x39d2 +#define regSQG_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER3_SELECT 0x39d3 +#define regSQG_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER4_SELECT 0x39d4 +#define regSQG_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER5_SELECT 0x39d5 +#define regSQG_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER6_SELECT 0x39d6 +#define regSQG_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER7_SELECT 0x39d7 +#define regSQG_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER_CTRL 0x39d8 +#define regSQG_PERFCOUNTER_CTRL_BASE_IDX 1 +#define regSQG_PERFCOUNTER_CTRL2 0x39da +#define regSQG_PERFCOUNTER_CTRL2_BASE_IDX 1 +#define regSQG_PERF_SAMPLE_FINISH 0x39db +#define regSQG_PERF_SAMPLE_FINISH_BASE_IDX 1 +#define regSQ_PERFCOUNTER_CTRL 0x39e0 +#define regSQ_PERFCOUNTER_CTRL_BASE_IDX 1 +#define regSQ_PERFCOUNTER_CTRL2 0x39e2 +#define regSQ_PERFCOUNTER_CTRL2_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BUF0_BASE 0x39e8 +#define regSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BUF0_SIZE 0x39e9 +#define regSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BUF1_BASE 0x39ea +#define regSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BUF1_SIZE 0x39eb +#define regSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX 1 +#define regSQ_THREAD_TRACE_CTRL 0x39ec +#define regSQ_THREAD_TRACE_CTRL_BASE_IDX 1 +#define regSQ_THREAD_TRACE_MASK 0x39ed +#define regSQ_THREAD_TRACE_MASK_BASE_IDX 1 +#define regSQ_THREAD_TRACE_TOKEN_MASK 0x39ee +#define regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX 1 +#define regSQ_THREAD_TRACE_WPTR 0x39ef +#define regSQ_THREAD_TRACE_WPTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_STATUS 0x39f4 +#define regSQ_THREAD_TRACE_STATUS_BASE_IDX 1 +#define regSQ_THREAD_TRACE_STATUS2 0x39f5 +#define regSQ_THREAD_TRACE_STATUS2_BASE_IDX 1 +#define regSQ_THREAD_TRACE_GFX_DRAW_CNTR 0x39f6 +#define regSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_GFX_MARKER_CNTR 0x39f7 +#define regSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_HP3D_DRAW_CNTR 0x39f8 +#define regSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_HP3D_MARKER_CNTR 0x39f9 +#define regSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_DROPPED_CNTR 0x39fa +#define regSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX 1 +#define regGCEA_PERFCOUNTER2_SELECT 0x3a00 +#define regGCEA_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGCEA_PERFCOUNTER2_SELECT1 0x3a01 +#define regGCEA_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGCEA_PERFCOUNTER2_MODE 0x3a02 +#define regGCEA_PERFCOUNTER2_MODE_BASE_IDX 1 +#define regGCEA_PERFCOUNTER0_CFG 0x3a03 +#define regGCEA_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regGCEA_PERFCOUNTER1_CFG 0x3a04 +#define regGCEA_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regGCEA_PERFCOUNTER_RSLT_CNTL 0x3a05 +#define regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regSX_PERFCOUNTER0_SELECT 0x3a40 +#define regSX_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER1_SELECT 0x3a41 +#define regSX_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER2_SELECT 0x3a42 +#define regSX_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER3_SELECT 0x3a43 +#define regSX_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER0_SELECT1 0x3a44 +#define regSX_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regSX_PERFCOUNTER1_SELECT1 0x3a45 +#define regSX_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGDS_PERFCOUNTER0_SELECT 0x3a80 +#define regGDS_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGDS_PERFCOUNTER1_SELECT 0x3a81 +#define regGDS_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGDS_PERFCOUNTER2_SELECT 0x3a82 +#define regGDS_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGDS_PERFCOUNTER3_SELECT 0x3a83 +#define regGDS_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGDS_PERFCOUNTER0_SELECT1 0x3a84 +#define regGDS_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGDS_PERFCOUNTER1_SELECT1 0x3a85 +#define regGDS_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGDS_PERFCOUNTER2_SELECT1 0x3a86 +#define regGDS_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGDS_PERFCOUNTER3_SELECT1 0x3a87 +#define regGDS_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regTA_PERFCOUNTER0_SELECT 0x3ac0 +#define regTA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTA_PERFCOUNTER0_SELECT1 0x3ac1 +#define regTA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTA_PERFCOUNTER1_SELECT 0x3ac2 +#define regTA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTD_PERFCOUNTER0_SELECT 0x3b00 +#define regTD_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTD_PERFCOUNTER0_SELECT1 0x3b01 +#define regTD_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTD_PERFCOUNTER1_SELECT 0x3b02 +#define regTD_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_SELECT 0x3b40 +#define regTCP_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_SELECT1 0x3b41 +#define regTCP_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_SELECT 0x3b42 +#define regTCP_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_SELECT1 0x3b43 +#define regTCP_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regTCP_PERFCOUNTER2_SELECT 0x3b44 +#define regTCP_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER3_SELECT 0x3b45 +#define regTCP_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL2C_PERFCOUNTER0_SELECT 0x3b80 +#define regGL2C_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL2C_PERFCOUNTER0_SELECT1 0x3b81 +#define regGL2C_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL2C_PERFCOUNTER1_SELECT 0x3b82 +#define regGL2C_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL2C_PERFCOUNTER1_SELECT1 0x3b83 +#define regGL2C_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGL2C_PERFCOUNTER2_SELECT 0x3b84 +#define regGL2C_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL2C_PERFCOUNTER3_SELECT 0x3b85 +#define regGL2C_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL2A_PERFCOUNTER0_SELECT 0x3b90 +#define regGL2A_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL2A_PERFCOUNTER0_SELECT1 0x3b91 +#define regGL2A_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL2A_PERFCOUNTER1_SELECT 0x3b92 +#define regGL2A_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL2A_PERFCOUNTER1_SELECT1 0x3b93 +#define regGL2A_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGL2A_PERFCOUNTER2_SELECT 0x3b94 +#define regGL2A_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL2A_PERFCOUNTER3_SELECT 0x3b95 +#define regGL2A_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL1C_PERFCOUNTER0_SELECT 0x3ba0 +#define regGL1C_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL1C_PERFCOUNTER0_SELECT1 0x3ba1 +#define regGL1C_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL1C_PERFCOUNTER1_SELECT 0x3ba2 +#define regGL1C_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL1C_PERFCOUNTER2_SELECT 0x3ba3 +#define regGL1C_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL1C_PERFCOUNTER3_SELECT 0x3ba4 +#define regGL1C_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regCHC_PERFCOUNTER0_SELECT 0x3bc0 +#define regCHC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCHC_PERFCOUNTER0_SELECT1 0x3bc1 +#define regCHC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCHC_PERFCOUNTER1_SELECT 0x3bc2 +#define regCHC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCHC_PERFCOUNTER2_SELECT 0x3bc3 +#define regCHC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regCHC_PERFCOUNTER3_SELECT 0x3bc4 +#define regCHC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regCHCG_PERFCOUNTER0_SELECT 0x3bc6 +#define regCHCG_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCHCG_PERFCOUNTER0_SELECT1 0x3bc7 +#define regCHCG_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCHCG_PERFCOUNTER1_SELECT 0x3bc8 +#define regCHCG_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCHCG_PERFCOUNTER2_SELECT 0x3bc9 +#define regCHCG_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regCHCG_PERFCOUNTER3_SELECT 0x3bca +#define regCHCG_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER_FILTER 0x3c00 +#define regCB_PERFCOUNTER_FILTER_BASE_IDX 1 +#define regCB_PERFCOUNTER0_SELECT 0x3c01 +#define regCB_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER0_SELECT1 0x3c02 +#define regCB_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCB_PERFCOUNTER1_SELECT 0x3c03 +#define regCB_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER2_SELECT 0x3c04 +#define regCB_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER3_SELECT 0x3c05 +#define regCB_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER0_SELECT 0x3c40 +#define regDB_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER0_SELECT1 0x3c41 +#define regDB_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regDB_PERFCOUNTER1_SELECT 0x3c42 +#define regDB_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER1_SELECT1 0x3c43 +#define regDB_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regDB_PERFCOUNTER2_SELECT 0x3c44 +#define regDB_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER3_SELECT 0x3c46 +#define regDB_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regRLC_SPM_PERFMON_CNTL 0x3c80 +#define regRLC_SPM_PERFMON_CNTL_BASE_IDX 1 +#define regRLC_SPM_PERFMON_RING_BASE_LO 0x3c81 +#define regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 1 +#define regRLC_SPM_PERFMON_RING_BASE_HI 0x3c82 +#define regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX 1 +#define regRLC_SPM_PERFMON_RING_SIZE 0x3c83 +#define regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX 1 +#define regRLC_SPM_RING_WRPTR 0x3c84 +#define regRLC_SPM_RING_WRPTR_BASE_IDX 1 +#define regRLC_SPM_RING_RDPTR 0x3c85 +#define regRLC_SPM_RING_RDPTR_BASE_IDX 1 +#define regRLC_SPM_SEGMENT_THRESHOLD 0x3c86 +#define regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX 1 +#define regRLC_SPM_PERFMON_SEGMENT_SIZE 0x3c87 +#define regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_MUXSEL_ADDR 0x3c88 +#define regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_MUXSEL_DATA 0x3c89 +#define regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX 1 +#define regRLC_SPM_SE_MUXSEL_ADDR 0x3c8a +#define regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX 1 +#define regRLC_SPM_SE_MUXSEL_DATA 0x3c8b +#define regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 1 +#define regRLC_SPM_ACCUM_DATARAM_ADDR 0x3c92 +#define regRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX 1 +#define regRLC_SPM_ACCUM_DATARAM_DATA 0x3c93 +#define regRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX 1 +#define regRLC_SPM_ACCUM_SWA_DATARAM_ADDR 0x3c94 +#define regRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX 1 +#define regRLC_SPM_ACCUM_SWA_DATARAM_DATA 0x3c95 +#define regRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX 1 +#define regRLC_SPM_ACCUM_CTRLRAM_ADDR 0x3c96 +#define regRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX 1 +#define regRLC_SPM_ACCUM_CTRLRAM_DATA 0x3c97 +#define regRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX 1 +#define regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET 0x3c98 +#define regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX 1 +#define regRLC_SPM_ACCUM_STATUS 0x3c99 +#define regRLC_SPM_ACCUM_STATUS_BASE_IDX 1 +#define regRLC_SPM_ACCUM_CTRL 0x3c9a +#define regRLC_SPM_ACCUM_CTRL_BASE_IDX 1 +#define regRLC_SPM_ACCUM_MODE 0x3c9b +#define regRLC_SPM_ACCUM_MODE_BASE_IDX 1 +#define regRLC_SPM_ACCUM_THRESHOLD 0x3c9c +#define regRLC_SPM_ACCUM_THRESHOLD_BASE_IDX 1 +#define regRLC_SPM_ACCUM_SAMPLES_REQUESTED 0x3c9d +#define regRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX 1 +#define regRLC_SPM_ACCUM_DATARAM_WRCOUNT 0x3c9e +#define regRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX 1 +#define regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS 0x3c9f +#define regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX 1 +#define regRLC_SPM_PAUSE 0x3ca2 +#define regRLC_SPM_PAUSE_BASE_IDX 1 +#define regRLC_SPM_STATUS 0x3ca3 +#define regRLC_SPM_STATUS_BASE_IDX 1 +#define regRLC_SPM_GFXCLOCK_LOWCOUNT 0x3ca4 +#define regRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX 1 +#define regRLC_SPM_GFXCLOCK_HIGHCOUNT 0x3ca5 +#define regRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX 1 +#define regRLC_SPM_MODE 0x3cad +#define regRLC_SPM_MODE_BASE_IDX 1 +#define regRLC_SPM_RSPM_REQ_DATA_LO 0x3cae +#define regRLC_SPM_RSPM_REQ_DATA_LO_BASE_IDX 1 +#define regRLC_SPM_RSPM_REQ_DATA_HI 0x3caf +#define regRLC_SPM_RSPM_REQ_DATA_HI_BASE_IDX 1 +#define regRLC_SPM_RSPM_REQ_OP 0x3cb0 +#define regRLC_SPM_RSPM_REQ_OP_BASE_IDX 1 +#define regRLC_SPM_RSPM_RET_DATA 0x3cb1 +#define regRLC_SPM_RSPM_RET_DATA_BASE_IDX 1 +#define regRLC_SPM_RSPM_RET_OP 0x3cb2 +#define regRLC_SPM_RSPM_RET_OP_BASE_IDX 1 +#define regRLC_SPM_SE_RSPM_REQ_DATA_LO 0x3cb3 +#define regRLC_SPM_SE_RSPM_REQ_DATA_LO_BASE_IDX 1 +#define regRLC_SPM_SE_RSPM_REQ_DATA_HI 0x3cb4 +#define regRLC_SPM_SE_RSPM_REQ_DATA_HI_BASE_IDX 1 +#define regRLC_SPM_SE_RSPM_REQ_OP 0x3cb5 +#define regRLC_SPM_SE_RSPM_REQ_OP_BASE_IDX 1 +#define regRLC_SPM_SE_RSPM_RET_DATA 0x3cb6 +#define regRLC_SPM_SE_RSPM_RET_DATA_BASE_IDX 1 +#define regRLC_SPM_SE_RSPM_RET_OP 0x3cb7 +#define regRLC_SPM_SE_RSPM_RET_OP_BASE_IDX 1 +#define regRLC_SPM_RSPM_CMD 0x3cb8 +#define regRLC_SPM_RSPM_CMD_BASE_IDX 1 +#define regRLC_SPM_RSPM_CMD_ACK 0x3cb9 +#define regRLC_SPM_RSPM_CMD_ACK_BASE_IDX 1 +#define regRLC_SPM_SPARE 0x3cbf +#define regRLC_SPM_SPARE_BASE_IDX 1 +#define regRLC_PERFMON_CNTL 0x3cc0 +#define regRLC_PERFMON_CNTL_BASE_IDX 1 +#define regRLC_PERFCOUNTER0_SELECT 0x3cc1 +#define regRLC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regRLC_PERFCOUNTER1_SELECT 0x3cc2 +#define regRLC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_CNTL 0x3cc3 +#define regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_WR_ADDR 0x3cc4 +#define regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_WR_DATA 0x3cc5 +#define regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_RD_ADDR 0x3cc6 +#define regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_RD_DATA 0x3cc7 +#define regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_SELECT 0x3d00 +#define regRMI_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_SELECT1 0x3d01 +#define regRMI_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regRMI_PERFCOUNTER1_SELECT 0x3d02 +#define regRMI_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_SELECT 0x3d03 +#define regRMI_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_SELECT1 0x3d04 +#define regRMI_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regRMI_PERFCOUNTER3_SELECT 0x3d05 +#define regRMI_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regRMI_PERF_COUNTER_CNTL 0x3d06 +#define regRMI_PERF_COUNTER_CNTL_BASE_IDX 1 +#define regGCR_PERFCOUNTER0_SELECT 0x3d60 +#define regGCR_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGCR_PERFCOUNTER0_SELECT1 0x3d61 +#define regGCR_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGCR_PERFCOUNTER1_SELECT 0x3d62 +#define regGCR_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER0_SELECT 0x3d80 +#define regPA_PH_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER0_SELECT1 0x3d81 +#define regPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER1_SELECT 0x3d82 +#define regPA_PH_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER2_SELECT 0x3d83 +#define regPA_PH_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER3_SELECT 0x3d84 +#define regPA_PH_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER4_SELECT 0x3d85 +#define regPA_PH_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER5_SELECT 0x3d86 +#define regPA_PH_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER6_SELECT 0x3d87 +#define regPA_PH_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER7_SELECT 0x3d88 +#define regPA_PH_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER1_SELECT1 0x3d90 +#define regPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER2_SELECT1 0x3d91 +#define regPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER3_SELECT1 0x3d92 +#define regPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER0_SELECT 0x3da0 +#define regUTCL1_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER1_SELECT 0x3da1 +#define regUTCL1_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER2_SELECT 0x3da2 +#define regUTCL1_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER3_SELECT 0x3da3 +#define regUTCL1_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL1A_PERFCOUNTER0_SELECT 0x3dc0 +#define regGL1A_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL1A_PERFCOUNTER0_SELECT1 0x3dc1 +#define regGL1A_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL1A_PERFCOUNTER1_SELECT 0x3dc2 +#define regGL1A_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL1A_PERFCOUNTER2_SELECT 0x3dc3 +#define regGL1A_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL1A_PERFCOUNTER3_SELECT 0x3dc4 +#define regGL1A_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL1H_PERFCOUNTER0_SELECT 0x3dd0 +#define regGL1H_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL1H_PERFCOUNTER0_SELECT1 0x3dd1 +#define regGL1H_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL1H_PERFCOUNTER1_SELECT 0x3dd2 +#define regGL1H_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL1H_PERFCOUNTER2_SELECT 0x3dd3 +#define regGL1H_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL1H_PERFCOUNTER3_SELECT 0x3dd4 +#define regGL1H_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regCHA_PERFCOUNTER0_SELECT 0x3de0 +#define regCHA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCHA_PERFCOUNTER0_SELECT1 0x3de1 +#define regCHA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCHA_PERFCOUNTER1_SELECT 0x3de2 +#define regCHA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCHA_PERFCOUNTER2_SELECT 0x3de3 +#define regCHA_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regCHA_PERFCOUNTER3_SELECT 0x3de4 +#define regCHA_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGUS_PERFCOUNTER2_SELECT 0x3e00 +#define regGUS_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGUS_PERFCOUNTER2_SELECT1 0x3e01 +#define regGUS_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGUS_PERFCOUNTER2_MODE 0x3e02 +#define regGUS_PERFCOUNTER2_MODE_BASE_IDX 1 +#define regGUS_PERFCOUNTER0_CFG 0x3e03 +#define regGUS_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regGUS_PERFCOUNTER1_CFG 0x3e04 +#define regGUS_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regGUS_PERFCOUNTER_RSLT_CNTL 0x3e05 +#define regGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: gc_grtavfs_grtavfs_dec +// base address: 0x3ac00 +#define regGRTAVFS_RTAVFS_REG_ADDR 0x4b00 +#define regGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX 1 +#define regGRTAVFS_RTAVFS_WR_DATA 0x4b01 +#define regGRTAVFS_RTAVFS_WR_DATA_BASE_IDX 1 +#define regGRTAVFS_GENERAL_0 0x4b02 +#define regGRTAVFS_GENERAL_0_BASE_IDX 1 +#define regGRTAVFS_RTAVFS_RD_DATA 0x4b03 +#define regGRTAVFS_RTAVFS_RD_DATA_BASE_IDX 1 +#define regGRTAVFS_RTAVFS_REG_CTRL 0x4b04 +#define regGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX 1 +#define regGRTAVFS_RTAVFS_REG_STATUS 0x4b05 +#define regGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX 1 +#define regGRTAVFS_TARG_FREQ 0x4b06 +#define regGRTAVFS_TARG_FREQ_BASE_IDX 1 +#define regGRTAVFS_TARG_VOLT 0x4b07 +#define regGRTAVFS_TARG_VOLT_BASE_IDX 1 +#define regGRTAVFS_SOFT_RESET 0x4b0c +#define regGRTAVFS_SOFT_RESET_BASE_IDX 1 +#define regGRTAVFS_PSM_CNTL 0x4b0d +#define regGRTAVFS_PSM_CNTL_BASE_IDX 1 +#define regGRTAVFS_CLK_CNTL 0x4b0e +#define regGRTAVFS_CLK_CNTL_BASE_IDX 1 + + +// addressBlock: gc_grtavfs_se_grtavfs_dec +// base address: 0x3ad00 +#define regGRTAVFS_SE_RTAVFS_REG_ADDR 0x4b40 +#define regGRTAVFS_SE_RTAVFS_REG_ADDR_BASE_IDX 1 +#define regGRTAVFS_SE_RTAVFS_WR_DATA 0x4b41 +#define regGRTAVFS_SE_RTAVFS_WR_DATA_BASE_IDX 1 +#define regGRTAVFS_SE_GENERAL_0 0x4b42 +#define regGRTAVFS_SE_GENERAL_0_BASE_IDX 1 +#define regGRTAVFS_SE_RTAVFS_RD_DATA 0x4b43 +#define regGRTAVFS_SE_RTAVFS_RD_DATA_BASE_IDX 1 +#define regGRTAVFS_SE_RTAVFS_REG_CTRL 0x4b44 +#define regGRTAVFS_SE_RTAVFS_REG_CTRL_BASE_IDX 1 +#define regGRTAVFS_SE_RTAVFS_REG_STATUS 0x4b45 +#define regGRTAVFS_SE_RTAVFS_REG_STATUS_BASE_IDX 1 +#define regGRTAVFS_SE_TARG_FREQ 0x4b46 +#define regGRTAVFS_SE_TARG_FREQ_BASE_IDX 1 +#define regGRTAVFS_SE_TARG_VOLT 0x4b47 +#define regGRTAVFS_SE_TARG_VOLT_BASE_IDX 1 +#define regGRTAVFS_SE_SOFT_RESET 0x4b4c +#define regGRTAVFS_SE_SOFT_RESET_BASE_IDX 1 +#define regGRTAVFS_SE_PSM_CNTL 0x4b4d +#define regGRTAVFS_SE_PSM_CNTL_BASE_IDX 1 +#define regGRTAVFS_SE_CLK_CNTL 0x4b4e +#define regGRTAVFS_SE_CLK_CNTL_BASE_IDX 1 + + +// addressBlock: gc_grtavfsdec +// base address: 0x3ac00 +#define regRTAVFS_RTAVFS_REG_ADDR 0x4b00 +#define regRTAVFS_RTAVFS_REG_ADDR_BASE_IDX 1 +#define regRTAVFS_RTAVFS_WR_DATA 0x4b01 +#define regRTAVFS_RTAVFS_WR_DATA_BASE_IDX 1 + + +// addressBlock: gc_cphypdec +// base address: 0x3e000 +#define regCP_HYP_PFP_UCODE_ADDR 0x5814 +#define regCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 +#define regCP_PFP_UCODE_ADDR 0x5814 +#define regCP_PFP_UCODE_ADDR_BASE_IDX 1 +#define regCP_HYP_PFP_UCODE_DATA 0x5815 +#define regCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 +#define regCP_PFP_UCODE_DATA 0x5815 +#define regCP_PFP_UCODE_DATA_BASE_IDX 1 +#define regCP_HYP_ME_UCODE_ADDR 0x5816 +#define regCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 +#define regCP_ME_RAM_RADDR 0x5816 +#define regCP_ME_RAM_RADDR_BASE_IDX 1 +#define regCP_ME_RAM_WADDR 0x5816 +#define regCP_ME_RAM_WADDR_BASE_IDX 1 +#define regCP_HYP_ME_UCODE_DATA 0x5817 +#define regCP_HYP_ME_UCODE_DATA_BASE_IDX 1 +#define regCP_ME_RAM_DATA 0x5817 +#define regCP_ME_RAM_DATA_BASE_IDX 1 +#define regCP_HYP_MEC1_UCODE_ADDR 0x581a +#define regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX 1 +#define regCP_MEC_ME1_UCODE_ADDR 0x581a +#define regCP_MEC_ME1_UCODE_ADDR_BASE_IDX 1 +#define regCP_HYP_MEC1_UCODE_DATA 0x581b +#define regCP_HYP_MEC1_UCODE_DATA_BASE_IDX 1 +#define regCP_MEC_ME1_UCODE_DATA 0x581b +#define regCP_MEC_ME1_UCODE_DATA_BASE_IDX 1 +#define regCP_HYP_MEC2_UCODE_ADDR 0x581c +#define regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX 1 +#define regCP_MEC_ME2_UCODE_ADDR 0x581c +#define regCP_MEC_ME2_UCODE_ADDR_BASE_IDX 1 +#define regCP_HYP_MEC2_UCODE_DATA 0x581d +#define regCP_HYP_MEC2_UCODE_DATA_BASE_IDX 1 +#define regCP_MEC_ME2_UCODE_DATA 0x581d +#define regCP_MEC_ME2_UCODE_DATA_BASE_IDX 1 +#define regCP_PFP_IC_BASE_LO 0x5840 +#define regCP_PFP_IC_BASE_LO_BASE_IDX 1 +#define regCP_PFP_IC_BASE_HI 0x5841 +#define regCP_PFP_IC_BASE_HI_BASE_IDX 1 +#define regCP_PFP_IC_BASE_CNTL 0x5842 +#define regCP_PFP_IC_BASE_CNTL_BASE_IDX 1 +#define regCP_PFP_IC_OP_CNTL 0x5843 +#define regCP_PFP_IC_OP_CNTL_BASE_IDX 1 +#define regCP_ME_IC_BASE_LO 0x5844 +#define regCP_ME_IC_BASE_LO_BASE_IDX 1 +#define regCP_ME_IC_BASE_HI 0x5845 +#define regCP_ME_IC_BASE_HI_BASE_IDX 1 +#define regCP_ME_IC_BASE_CNTL 0x5846 +#define regCP_ME_IC_BASE_CNTL_BASE_IDX 1 +#define regCP_ME_IC_OP_CNTL 0x5847 +#define regCP_ME_IC_OP_CNTL_BASE_IDX 1 +#define regCP_CPC_IC_BASE_LO 0x584c +#define regCP_CPC_IC_BASE_LO_BASE_IDX 1 +#define regCP_CPC_IC_BASE_HI 0x584d +#define regCP_CPC_IC_BASE_HI_BASE_IDX 1 +#define regCP_CPC_IC_BASE_CNTL 0x584e +#define regCP_CPC_IC_BASE_CNTL_BASE_IDX 1 +#define regCP_MES_IC_BASE_LO 0x5850 +#define regCP_MES_IC_BASE_LO_BASE_IDX 1 +#define regCP_MES_MIBASE_LO 0x5850 +#define regCP_MES_MIBASE_LO_BASE_IDX 1 +#define regCP_MES_IC_BASE_HI 0x5851 +#define regCP_MES_IC_BASE_HI_BASE_IDX 1 +#define regCP_MES_MIBASE_HI 0x5851 +#define regCP_MES_MIBASE_HI_BASE_IDX 1 +#define regCP_MES_IC_BASE_CNTL 0x5852 +#define regCP_MES_IC_BASE_CNTL_BASE_IDX 1 +#define regCP_MES_DC_BASE_LO 0x5854 +#define regCP_MES_DC_BASE_LO_BASE_IDX 1 +#define regCP_MES_MDBASE_LO 0x5854 +#define regCP_MES_MDBASE_LO_BASE_IDX 1 +#define regCP_MES_DC_BASE_HI 0x5855 +#define regCP_MES_DC_BASE_HI_BASE_IDX 1 +#define regCP_MES_MDBASE_HI 0x5855 +#define regCP_MES_MDBASE_HI_BASE_IDX 1 +#define regCP_MES_MIBOUND_LO 0x585b +#define regCP_MES_MIBOUND_LO_BASE_IDX 1 +#define regCP_MES_MIBOUND_HI 0x585c +#define regCP_MES_MIBOUND_HI_BASE_IDX 1 +#define regCP_MES_MDBOUND_LO 0x585d +#define regCP_MES_MDBOUND_LO_BASE_IDX 1 +#define regCP_MES_MDBOUND_HI 0x585e +#define regCP_MES_MDBOUND_HI_BASE_IDX 1 +#define regCP_GFX_RS64_DC_BASE0_LO 0x5863 +#define regCP_GFX_RS64_DC_BASE0_LO_BASE_IDX 1 +#define regCP_GFX_RS64_DC_BASE1_LO 0x5864 +#define regCP_GFX_RS64_DC_BASE1_LO_BASE_IDX 1 +#define regCP_GFX_RS64_DC_BASE0_HI 0x5865 +#define regCP_GFX_RS64_DC_BASE0_HI_BASE_IDX 1 +#define regCP_GFX_RS64_DC_BASE1_HI 0x5866 +#define regCP_GFX_RS64_DC_BASE1_HI_BASE_IDX 1 +#define regCP_GFX_RS64_MIBOUND_LO 0x586c +#define regCP_GFX_RS64_MIBOUND_LO_BASE_IDX 1 +#define regCP_GFX_RS64_MIBOUND_HI 0x586d +#define regCP_GFX_RS64_MIBOUND_HI_BASE_IDX 1 +#define regCP_MEC_DC_BASE_LO 0x5870 +#define regCP_MEC_DC_BASE_LO_BASE_IDX 1 +#define regCP_MEC_MDBASE_LO 0x5870 +#define regCP_MEC_MDBASE_LO_BASE_IDX 1 +#define regCP_MEC_DC_BASE_HI 0x5871 +#define regCP_MEC_DC_BASE_HI_BASE_IDX 1 +#define regCP_MEC_MDBASE_HI 0x5871 +#define regCP_MEC_MDBASE_HI_BASE_IDX 1 +#define regCP_MEC_MIBOUND_LO 0x5872 +#define regCP_MEC_MIBOUND_LO_BASE_IDX 1 +#define regCP_MEC_MIBOUND_HI 0x5873 +#define regCP_MEC_MIBOUND_HI_BASE_IDX 1 +#define regCP_MEC_MDBOUND_LO 0x5874 +#define regCP_MEC_MDBOUND_LO_BASE_IDX 1 +#define regCP_MEC_MDBOUND_HI 0x5875 +#define regCP_MEC_MDBOUND_HI_BASE_IDX 1 + + +// addressBlock: gc_rlcdec +// base address: 0x3b000 +#define regRLC_CNTL 0x4c00 +#define regRLC_CNTL_BASE_IDX 1 +#define regRLC_F32_UCODE_VERSION 0x4c03 +#define regRLC_F32_UCODE_VERSION_BASE_IDX 1 +#define regRLC_STAT 0x4c04 +#define regRLC_STAT_BASE_IDX 1 +#define regRLC_REFCLOCK_TIMESTAMP_LSB 0x4c0c +#define regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX 1 +#define regRLC_REFCLOCK_TIMESTAMP_MSB 0x4c0d +#define regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_0 0x4c0e +#define regRLC_GPM_TIMER_INT_0_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_1 0x4c0f +#define regRLC_GPM_TIMER_INT_1_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_2 0x4c10 +#define regRLC_GPM_TIMER_INT_2_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_3 0x4c11 +#define regRLC_GPM_TIMER_INT_3_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_4 0x4c12 +#define regRLC_GPM_TIMER_INT_4_BASE_IDX 1 +#define regRLC_GPM_TIMER_CTRL 0x4c13 +#define regRLC_GPM_TIMER_CTRL_BASE_IDX 1 +#define regRLC_GPM_TIMER_STAT 0x4c14 +#define regRLC_GPM_TIMER_STAT_BASE_IDX 1 +#define regRLC_GPM_LEGACY_INT_STAT 0x4c16 +#define regRLC_GPM_LEGACY_INT_STAT_BASE_IDX 1 +#define regRLC_GPM_LEGACY_INT_CLEAR 0x4c17 +#define regRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX 1 +#define regRLC_INT_STAT 0x4c18 +#define regRLC_INT_STAT_BASE_IDX 1 +#define regRLC_MGCG_CTRL 0x4c1a +#define regRLC_MGCG_CTRL_BASE_IDX 1 +#define regRLC_JUMP_TABLE_RESTORE 0x4c1e +#define regRLC_JUMP_TABLE_RESTORE_BASE_IDX 1 +#define regRLC_PG_DELAY_2 0x4c1f +#define regRLC_PG_DELAY_2_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_LSB 0x4c24 +#define regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_MSB 0x4c25 +#define regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX 1 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT 0x4c26 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX 1 +#define regRLC_UCODE_CNTL 0x4c27 +#define regRLC_UCODE_CNTL_BASE_IDX 1 +#define regRLC_GPM_THREAD_RESET 0x4c28 +#define regRLC_GPM_THREAD_RESET_BASE_IDX 1 +#define regRLC_GPM_CP_DMA_COMPLETE_T0 0x4c29 +#define regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX 1 +#define regRLC_GPM_CP_DMA_COMPLETE_T1 0x4c2a +#define regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX 1 +#define regRLC_GPM_THREAD_INVALIDATE_CACHE 0x4c2b +#define regRLC_GPM_THREAD_INVALIDATE_CACHE_BASE_IDX 1 +#define regRLC_CLK_COUNT_GFXCLK_LSB 0x4c30 +#define regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_GFXCLK_MSB 0x4c31 +#define regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_REFCLK_LSB 0x4c32 +#define regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_REFCLK_MSB 0x4c33 +#define regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_CTRL 0x4c34 +#define regRLC_CLK_COUNT_CTRL_BASE_IDX 1 +#define regRLC_CLK_COUNT_STAT 0x4c35 +#define regRLC_CLK_COUNT_STAT_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_CNTL 0x4c36 +#define regRLC_RLCG_DOORBELL_CNTL_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_STAT 0x4c37 +#define regRLC_RLCG_DOORBELL_STAT_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_0_DATA_LO 0x4c38 +#define regRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_0_DATA_HI 0x4c39 +#define regRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_1_DATA_LO 0x4c3a +#define regRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_1_DATA_HI 0x4c3b +#define regRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_2_DATA_LO 0x4c3c +#define regRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_2_DATA_HI 0x4c3d +#define regRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_3_DATA_LO 0x4c3e +#define regRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_3_DATA_HI 0x4c3f +#define regRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX 1 +#define regRLC_GPU_CLOCK_32_RES_SEL 0x4c41 +#define regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1 +#define regRLC_GPU_CLOCK_32 0x4c42 +#define regRLC_GPU_CLOCK_32_BASE_IDX 1 +#define regRLC_PG_CNTL 0x4c43 +#define regRLC_PG_CNTL_BASE_IDX 1 +#define regRLC_GPM_THREAD_PRIORITY 0x4c44 +#define regRLC_GPM_THREAD_PRIORITY_BASE_IDX 1 +#define regRLC_GPM_THREAD_ENABLE 0x4c45 +#define regRLC_GPM_THREAD_ENABLE_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_RANGE 0x4c47 +#define regRLC_RLCG_DOORBELL_RANGE_BASE_IDX 1 +#define regRLC_CGTT_MGCG_OVERRIDE 0x4c48 +#define regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX 1 +#define regRLC_CGCG_CGLS_CTRL 0x4c49 +#define regRLC_CGCG_CGLS_CTRL_BASE_IDX 1 +#define regRLC_CGCG_RAMP_CTRL 0x4c4a +#define regRLC_CGCG_RAMP_CTRL_BASE_IDX 1 +#define regRLC_DYN_PG_STATUS 0x4c4b +#define regRLC_DYN_PG_STATUS_BASE_IDX 1 +#define regRLC_DYN_PG_REQUEST 0x4c4c +#define regRLC_DYN_PG_REQUEST_BASE_IDX 1 +#define regRLC_PG_DELAY 0x4c4d +#define regRLC_PG_DELAY_BASE_IDX 1 +#define regRLC_WGP_STATUS 0x4c4e +#define regRLC_WGP_STATUS_BASE_IDX 1 +#define regRLC_PG_ALWAYS_ON_WGP_MASK 0x4c53 +#define regRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX 1 +#define regRLC_MAX_PG_WGP 0x4c54 +#define regRLC_MAX_PG_WGP_BASE_IDX 1 +#define regRLC_AUTO_PG_CTRL 0x4c55 +#define regRLC_AUTO_PG_CTRL_BASE_IDX 1 +#define regRLC_SERDES_RD_INDEX 0x4c59 +#define regRLC_SERDES_RD_INDEX_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_0 0x4c5a +#define regRLC_SERDES_RD_DATA_0_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_1 0x4c5b +#define regRLC_SERDES_RD_DATA_1_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_2 0x4c5c +#define regRLC_SERDES_RD_DATA_2_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_3 0x4c5d +#define regRLC_SERDES_RD_DATA_3_BASE_IDX 1 +#define regRLC_SERDES_MASK 0x4c5e +#define regRLC_SERDES_MASK_BASE_IDX 1 +#define regRLC_SERDES_CTRL 0x4c5f +#define regRLC_SERDES_CTRL_BASE_IDX 1 +#define regRLC_SERDES_DATA 0x4c60 +#define regRLC_SERDES_DATA_BASE_IDX 1 +#define regRLC_SERDES_BUSY 0x4c61 +#define regRLC_SERDES_BUSY_BASE_IDX 1 +#define regRLC_GPM_GENERAL_0 0x4c63 +#define regRLC_GPM_GENERAL_0_BASE_IDX 1 +#define regRLC_GPM_GENERAL_1 0x4c64 +#define regRLC_GPM_GENERAL_1_BASE_IDX 1 +#define regRLC_GPM_GENERAL_2 0x4c65 +#define regRLC_GPM_GENERAL_2_BASE_IDX 1 +#define regRLC_GPM_GENERAL_3 0x4c66 +#define regRLC_GPM_GENERAL_3_BASE_IDX 1 +#define regRLC_GPM_GENERAL_4 0x4c67 +#define regRLC_GPM_GENERAL_4_BASE_IDX 1 +#define regRLC_GPM_GENERAL_5 0x4c68 +#define regRLC_GPM_GENERAL_5_BASE_IDX 1 +#define regRLC_GPM_GENERAL_6 0x4c69 +#define regRLC_GPM_GENERAL_6_BASE_IDX 1 +#define regRLC_GPM_GENERAL_7 0x4c6a +#define regRLC_GPM_GENERAL_7_BASE_IDX 1 +#define regRLC_STATIC_PG_STATUS 0x4c6e +#define regRLC_STATIC_PG_STATUS_BASE_IDX 1 +#define regRLC_GPM_GENERAL_16 0x4c76 +#define regRLC_GPM_GENERAL_16_BASE_IDX 1 +#define regRLC_PG_DELAY_3 0x4c78 +#define regRLC_PG_DELAY_3_BASE_IDX 1 +#define regRLC_GPR_REG1 0x4c79 +#define regRLC_GPR_REG1_BASE_IDX 1 +#define regRLC_GPR_REG2 0x4c7a +#define regRLC_GPR_REG2_BASE_IDX 1 +#define regRLC_GPM_INT_DISABLE_TH0 0x4c7c +#define regRLC_GPM_INT_DISABLE_TH0_BASE_IDX 1 +#define regRLC_GPM_LEGACY_INT_DISABLE 0x4c7d +#define regRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX 1 +#define regRLC_GPM_INT_FORCE_TH0 0x4c7e +#define regRLC_GPM_INT_FORCE_TH0_BASE_IDX 1 +#define regRLC_SRM_CNTL 0x4c80 +#define regRLC_SRM_CNTL_BASE_IDX 1 +#define regRLC_SRM_GPM_COMMAND_STATUS 0x4c88 +#define regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b +#define regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_1 0x4c8c +#define regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_2 0x4c8d +#define regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_3 0x4c8e +#define regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_4 0x4c8f +#define regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_5 0x4c90 +#define regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_6 0x4c91 +#define regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_7 0x4c92 +#define regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_0 0x4c93 +#define regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_1 0x4c94 +#define regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_2 0x4c95 +#define regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_3 0x4c96 +#define regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_4 0x4c97 +#define regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_5 0x4c98 +#define regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_6 0x4c99 +#define regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_7 0x4c9a +#define regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX 1 +#define regRLC_SRM_STAT 0x4c9b +#define regRLC_SRM_STAT_BASE_IDX 1 +#define regRLC_GPM_GENERAL_8 0x4cad +#define regRLC_GPM_GENERAL_8_BASE_IDX 1 +#define regRLC_GPM_GENERAL_9 0x4cae +#define regRLC_GPM_GENERAL_9_BASE_IDX 1 +#define regRLC_GPM_GENERAL_10 0x4caf +#define regRLC_GPM_GENERAL_10_BASE_IDX 1 +#define regRLC_GPM_GENERAL_11 0x4cb0 +#define regRLC_GPM_GENERAL_11_BASE_IDX 1 +#define regRLC_GPM_GENERAL_12 0x4cb1 +#define regRLC_GPM_GENERAL_12_BASE_IDX 1 +#define regRLC_GPM_UTCL1_CNTL_0 0x4cb2 +#define regRLC_GPM_UTCL1_CNTL_0_BASE_IDX 1 +#define regRLC_GPM_UTCL1_CNTL_1 0x4cb3 +#define regRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1 +#define regRLC_GPM_UTCL1_CNTL_2 0x4cb4 +#define regRLC_GPM_UTCL1_CNTL_2_BASE_IDX 1 +#define regRLC_SPM_UTCL1_CNTL 0x4cb5 +#define regRLC_SPM_UTCL1_CNTL_BASE_IDX 1 +#define regRLC_UTCL1_STATUS_2 0x4cb6 +#define regRLC_UTCL1_STATUS_2_BASE_IDX 1 +#define regRLC_SPM_UTCL1_ERROR_1 0x4cbc +#define regRLC_SPM_UTCL1_ERROR_1_BASE_IDX 1 +#define regRLC_SPM_UTCL1_ERROR_2 0x4cbd +#define regRLC_SPM_UTCL1_ERROR_2_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH0_ERROR_1 0x4cbe +#define regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH0_ERROR_2 0x4cc0 +#define regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH1_ERROR_1 0x4cc1 +#define regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH1_ERROR_2 0x4cc2 +#define regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH2_ERROR_1 0x4cc3 +#define regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH2_ERROR_2 0x4cc4 +#define regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX 1 +#define regRLC_CGCG_CGLS_CTRL_3D 0x4cc5 +#define regRLC_CGCG_CGLS_CTRL_3D_BASE_IDX 1 +#define regRLC_CGCG_RAMP_CTRL_3D 0x4cc6 +#define regRLC_CGCG_RAMP_CTRL_3D_BASE_IDX 1 +#define regRLC_SEMAPHORE_0 0x4cc7 +#define regRLC_SEMAPHORE_0_BASE_IDX 1 +#define regRLC_SEMAPHORE_1 0x4cc8 +#define regRLC_SEMAPHORE_1_BASE_IDX 1 +#define regRLC_SEMAPHORE_2 0x4cc9 +#define regRLC_SEMAPHORE_2_BASE_IDX 1 +#define regRLC_SEMAPHORE_3 0x4cca +#define regRLC_SEMAPHORE_3_BASE_IDX 1 +#define regRLC_PACE_INT_STAT 0x4ccc +#define regRLC_PACE_INT_STAT_BASE_IDX 1 +#define regRLC_UTCL1_STATUS 0x4cd4 +#define regRLC_UTCL1_STATUS_BASE_IDX 1 +#define regRLC_R2I_CNTL_0 0x4cd5 +#define regRLC_R2I_CNTL_0_BASE_IDX 1 +#define regRLC_R2I_CNTL_1 0x4cd6 +#define regRLC_R2I_CNTL_1_BASE_IDX 1 +#define regRLC_R2I_CNTL_2 0x4cd7 +#define regRLC_R2I_CNTL_2_BASE_IDX 1 +#define regRLC_R2I_CNTL_3 0x4cd8 +#define regRLC_R2I_CNTL_3_BASE_IDX 1 +#define regRLC_GPM_INT_STAT_TH0 0x4cdc +#define regRLC_GPM_INT_STAT_TH0_BASE_IDX 1 +#define regRLC_GPM_GENERAL_13 0x4cdd +#define regRLC_GPM_GENERAL_13_BASE_IDX 1 +#define regRLC_GPM_GENERAL_14 0x4cde +#define regRLC_GPM_GENERAL_14_BASE_IDX 1 +#define regRLC_GPM_GENERAL_15 0x4cdf +#define regRLC_GPM_GENERAL_15_BASE_IDX 1 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_1 0x4cea +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_LSB_2 0x4ceb +#define regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_MSB_2 0x4cec +#define regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX 1 +#define regRLC_PACE_INT_DISABLE 0x4ced +#define regRLC_PACE_INT_DISABLE_BASE_IDX 1 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_2 0x4cef +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_RANGE 0x4cf0 +#define regRLC_RLCV_DOORBELL_RANGE_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_CNTL 0x4cf1 +#define regRLC_RLCV_DOORBELL_CNTL_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_STAT 0x4cf2 +#define regRLC_RLCV_DOORBELL_STAT_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_0_DATA_LO 0x4cf3 +#define regRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_0_DATA_HI 0x4cf4 +#define regRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_1_DATA_LO 0x4cf5 +#define regRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_1_DATA_HI 0x4cf6 +#define regRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_2_DATA_LO 0x4cf7 +#define regRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_2_DATA_HI 0x4cf8 +#define regRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_3_DATA_LO 0x4cf9 +#define regRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_3_DATA_HI 0x4cfa +#define regRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_LSB_1 0x4cfb +#define regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_MSB_1 0x4cfc +#define regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX 1 +#define regRLC_RLCV_SPARE_INT 0x4d00 +#define regRLC_RLCV_SPARE_INT_BASE_IDX 1 +#define regRLC_PACE_TIMER_INT_0 0x4d04 +#define regRLC_PACE_TIMER_INT_0_BASE_IDX 1 +#define regRLC_PACE_TIMER_INT_1 0x4d05 +#define regRLC_PACE_TIMER_INT_1_BASE_IDX 1 +#define regRLC_PACE_TIMER_CTRL 0x4d06 +#define regRLC_PACE_TIMER_CTRL_BASE_IDX 1 +#define regRLC_SMU_CLK_REQ 0x4d08 +#define regRLC_SMU_CLK_REQ_BASE_IDX 1 +#define regRLC_CP_STAT_INVAL_STAT 0x4d09 +#define regRLC_CP_STAT_INVAL_STAT_BASE_IDX 1 +#define regRLC_CP_STAT_INVAL_CTRL 0x4d0a +#define regRLC_CP_STAT_INVAL_CTRL_BASE_IDX 1 +#define regRLC_SPARE 0x4d0b +#define regRLC_SPARE_BASE_IDX 1 +#define regRLC_SPP_CTRL 0x4d0c +#define regRLC_SPP_CTRL_BASE_IDX 1 +#define regRLC_SPP_SHADER_PROFILE_EN 0x4d0d +#define regRLC_SPP_SHADER_PROFILE_EN_BASE_IDX 1 +#define regRLC_SPP_SSF_CAPTURE_EN 0x4d0e +#define regRLC_SPP_SSF_CAPTURE_EN_BASE_IDX 1 +#define regRLC_SPP_SSF_THRESHOLD_0 0x4d0f +#define regRLC_SPP_SSF_THRESHOLD_0_BASE_IDX 1 +#define regRLC_SPP_SSF_THRESHOLD_1 0x4d10 +#define regRLC_SPP_SSF_THRESHOLD_1_BASE_IDX 1 +#define regRLC_SPP_SSF_THRESHOLD_2 0x4d11 +#define regRLC_SPP_SSF_THRESHOLD_2_BASE_IDX 1 +#define regRLC_SPP_INFLIGHT_RD_ADDR 0x4d12 +#define regRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX 1 +#define regRLC_SPP_INFLIGHT_RD_DATA 0x4d13 +#define regRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX 1 +#define regRLC_SPP_PROF_INFO_1 0x4d18 +#define regRLC_SPP_PROF_INFO_1_BASE_IDX 1 +#define regRLC_SPP_PROF_INFO_2 0x4d19 +#define regRLC_SPP_PROF_INFO_2_BASE_IDX 1 +#define regRLC_SPP_GLOBAL_SH_ID 0x4d1a +#define regRLC_SPP_GLOBAL_SH_ID_BASE_IDX 1 +#define regRLC_SPP_GLOBAL_SH_ID_VALID 0x4d1b +#define regRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX 1 +#define regRLC_SPP_STATUS 0x4d1c +#define regRLC_SPP_STATUS_BASE_IDX 1 +#define regRLC_SPP_PVT_STAT_0 0x4d1d +#define regRLC_SPP_PVT_STAT_0_BASE_IDX 1 +#define regRLC_SPP_PVT_STAT_1 0x4d1e +#define regRLC_SPP_PVT_STAT_1_BASE_IDX 1 +#define regRLC_SPP_PVT_STAT_2 0x4d1f +#define regRLC_SPP_PVT_STAT_2_BASE_IDX 1 +#define regRLC_SPP_PVT_STAT_3 0x4d20 +#define regRLC_SPP_PVT_STAT_3_BASE_IDX 1 +#define regRLC_SPP_PVT_LEVEL_MAX 0x4d21 +#define regRLC_SPP_PVT_LEVEL_MAX_BASE_IDX 1 +#define regRLC_SPP_STALL_STATE_UPDATE 0x4d22 +#define regRLC_SPP_STALL_STATE_UPDATE_BASE_IDX 1 +#define regRLC_SPP_PBB_INFO 0x4d23 +#define regRLC_SPP_PBB_INFO_BASE_IDX 1 +#define regRLC_SPP_RESET 0x4d24 +#define regRLC_SPP_RESET_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_RANGE 0x4d26 +#define regRLC_RLCP_DOORBELL_RANGE_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_CNTL 0x4d27 +#define regRLC_RLCP_DOORBELL_CNTL_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_STAT 0x4d28 +#define regRLC_RLCP_DOORBELL_STAT_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_0_DATA_LO 0x4d29 +#define regRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_0_DATA_HI 0x4d2a +#define regRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_1_DATA_LO 0x4d2b +#define regRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_1_DATA_HI 0x4d2c +#define regRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_2_DATA_LO 0x4d2d +#define regRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_2_DATA_HI 0x4d2e +#define regRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_3_DATA_LO 0x4d2f +#define regRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_3_DATA_HI 0x4d30 +#define regRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX 1 +#define regRLC_CAC_MASK_CNTL 0x4d45 +#define regRLC_CAC_MASK_CNTL_BASE_IDX 1 +#define regRLC_POWER_RESIDENCY_CNTR_CTRL 0x4d48 +#define regRLC_POWER_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_CLK_RESIDENCY_CNTR_CTRL 0x4d49 +#define regRLC_CLK_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_DS_RESIDENCY_CNTR_CTRL 0x4d4a +#define regRLC_DS_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_ULV_RESIDENCY_CNTR_CTRL 0x4d4b +#define regRLC_ULV_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_PCC_RESIDENCY_CNTR_CTRL 0x4d4c +#define regRLC_PCC_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_GENERAL_RESIDENCY_CNTR_CTRL 0x4d4d +#define regRLC_GENERAL_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_POWER_RESIDENCY_EVENT_CNTR 0x4d50 +#define regRLC_POWER_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_CLK_RESIDENCY_EVENT_CNTR 0x4d51 +#define regRLC_CLK_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_DS_RESIDENCY_EVENT_CNTR 0x4d52 +#define regRLC_DS_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_ULV_RESIDENCY_EVENT_CNTR 0x4d53 +#define regRLC_ULV_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_PCC_RESIDENCY_EVENT_CNTR 0x4d54 +#define regRLC_PCC_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_GENERAL_RESIDENCY_EVENT_CNTR 0x4d55 +#define regRLC_GENERAL_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_POWER_RESIDENCY_REF_CNTR 0x4d58 +#define regRLC_POWER_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_CLK_RESIDENCY_REF_CNTR 0x4d59 +#define regRLC_CLK_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_DS_RESIDENCY_REF_CNTR 0x4d5a +#define regRLC_DS_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_ULV_RESIDENCY_REF_CNTR 0x4d5b +#define regRLC_ULV_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_PCC_RESIDENCY_REF_CNTR 0x4d5c +#define regRLC_PCC_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_GENERAL_RESIDENCY_REF_CNTR 0x4d5d +#define regRLC_GENERAL_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_GFX_IH_CLIENT_CTRL 0x4d5e +#define regRLC_GFX_IH_CLIENT_CTRL_BASE_IDX 1 +#define regRLC_GFX_IH_ARBITER_STAT 0x4d5f +#define regRLC_GFX_IH_ARBITER_STAT_BASE_IDX 1 +#define regRLC_GFX_IH_CLIENT_SE_STAT_L 0x4d60 +#define regRLC_GFX_IH_CLIENT_SE_STAT_L_BASE_IDX 1 +#define regRLC_GFX_IH_CLIENT_SE_STAT_H 0x4d61 +#define regRLC_GFX_IH_CLIENT_SE_STAT_H_BASE_IDX 1 +#define regRLC_GFX_IH_CLIENT_SDMA_STAT 0x4d62 +#define regRLC_GFX_IH_CLIENT_SDMA_STAT_BASE_IDX 1 +#define regRLC_GFX_IH_CLIENT_OTHER_STAT 0x4d63 +#define regRLC_GFX_IH_CLIENT_OTHER_STAT_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_DELAY_IND_ADDR 0x4d64 +#define regRLC_SPM_GLOBAL_DELAY_IND_ADDR_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_DELAY_IND_DATA 0x4d65 +#define regRLC_SPM_GLOBAL_DELAY_IND_DATA_BASE_IDX 1 +#define regRLC_SPM_SE_DELAY_IND_ADDR 0x4d66 +#define regRLC_SPM_SE_DELAY_IND_ADDR_BASE_IDX 1 +#define regRLC_SPM_SE_DELAY_IND_DATA 0x4d67 +#define regRLC_SPM_SE_DELAY_IND_DATA_BASE_IDX 1 +#define regRLC_LX6_CNTL 0x4d80 +#define regRLC_LX6_CNTL_BASE_IDX 1 +#define regRLC_XT_CORE_STATUS 0x4dd4 +#define regRLC_XT_CORE_STATUS_BASE_IDX 1 +#define regRLC_XT_CORE_INTERRUPT 0x4dd5 +#define regRLC_XT_CORE_INTERRUPT_BASE_IDX 1 +#define regRLC_XT_CORE_FAULT_INFO 0x4dd6 +#define regRLC_XT_CORE_FAULT_INFO_BASE_IDX 1 +#define regRLC_XT_CORE_ALT_RESET_VEC 0x4dd7 +#define regRLC_XT_CORE_ALT_RESET_VEC_BASE_IDX 1 +#define regRLC_XT_CORE_RESERVED 0x4dd8 +#define regRLC_XT_CORE_RESERVED_BASE_IDX 1 +#define regRLC_XT_INT_VEC_FORCE 0x4dd9 +#define regRLC_XT_INT_VEC_FORCE_BASE_IDX 1 +#define regRLC_XT_INT_VEC_CLEAR 0x4dda +#define regRLC_XT_INT_VEC_CLEAR_BASE_IDX 1 +#define regRLC_XT_INT_VEC_MUX_SEL 0x4ddb +#define regRLC_XT_INT_VEC_MUX_SEL_BASE_IDX 1 +#define regRLC_XT_INT_VEC_MUX_INT_SEL 0x4ddc +#define regRLC_XT_INT_VEC_MUX_INT_SEL_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_SPM_LSB 0x4de4 +#define regRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_SPM_MSB 0x4de5 +#define regRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX 1 +#define regRLC_SPM_THREAD_TRACE_CTRL 0x4de6 +#define regRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX 1 +#define regRLC_SPP_CAM_ADDR 0x4de8 +#define regRLC_SPP_CAM_ADDR_BASE_IDX 1 +#define regRLC_SPP_CAM_DATA 0x4de9 +#define regRLC_SPP_CAM_DATA_BASE_IDX 1 +#define regRLC_SPP_CAM_EXT_ADDR 0x4dea +#define regRLC_SPP_CAM_EXT_ADDR_BASE_IDX 1 +#define regRLC_SPP_CAM_EXT_DATA 0x4deb +#define regRLC_SPP_CAM_EXT_DATA_BASE_IDX 1 +#define regRLC_XT_DOORBELL_RANGE 0x4df5 +#define regRLC_XT_DOORBELL_RANGE_BASE_IDX 1 +#define regRLC_XT_DOORBELL_CNTL 0x4df6 +#define regRLC_XT_DOORBELL_CNTL_BASE_IDX 1 +#define regRLC_XT_DOORBELL_STAT 0x4df7 +#define regRLC_XT_DOORBELL_STAT_BASE_IDX 1 +#define regRLC_XT_DOORBELL_0_DATA_LO 0x4df8 +#define regRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX 1 +#define regRLC_XT_DOORBELL_0_DATA_HI 0x4df9 +#define regRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX 1 +#define regRLC_XT_DOORBELL_1_DATA_LO 0x4dfa +#define regRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX 1 +#define regRLC_XT_DOORBELL_1_DATA_HI 0x4dfb +#define regRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX 1 +#define regRLC_XT_DOORBELL_2_DATA_LO 0x4dfc +#define regRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX 1 +#define regRLC_XT_DOORBELL_2_DATA_HI 0x4dfd +#define regRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX 1 +#define regRLC_XT_DOORBELL_3_DATA_LO 0x4dfe +#define regRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX 1 +#define regRLC_XT_DOORBELL_3_DATA_HI 0x4dff +#define regRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX 1 +#define regRLC_MEM_SLP_CNTL 0x4e00 +#define regRLC_MEM_SLP_CNTL_BASE_IDX 1 +#define regSMU_RLC_RESPONSE 0x4e01 +#define regSMU_RLC_RESPONSE_BASE_IDX 1 +#define regRLC_RLCV_SAFE_MODE 0x4e02 +#define regRLC_RLCV_SAFE_MODE_BASE_IDX 1 +#define regRLC_SMU_SAFE_MODE 0x4e03 +#define regRLC_SMU_SAFE_MODE_BASE_IDX 1 +#define regRLC_RLCV_COMMAND 0x4e04 +#define regRLC_RLCV_COMMAND_BASE_IDX 1 +#define regRLC_SMU_MESSAGE 0x4e05 +#define regRLC_SMU_MESSAGE_BASE_IDX 1 +#define regRLC_SMU_MESSAGE_1 0x4e06 +#define regRLC_SMU_MESSAGE_1_BASE_IDX 1 +#define regRLC_SMU_MESSAGE_2 0x4e07 +#define regRLC_SMU_MESSAGE_2_BASE_IDX 1 +#define regRLC_SRM_GPM_COMMAND 0x4e08 +#define regRLC_SRM_GPM_COMMAND_BASE_IDX 1 +#define regRLC_SRM_GPM_ABORT 0x4e09 +#define regRLC_SRM_GPM_ABORT_BASE_IDX 1 +#define regRLC_SMU_COMMAND 0x4e0a +#define regRLC_SMU_COMMAND_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_1 0x4e0b +#define regRLC_SMU_ARGUMENT_1_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_2 0x4e0c +#define regRLC_SMU_ARGUMENT_2_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_3 0x4e0d +#define regRLC_SMU_ARGUMENT_3_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_4 0x4e0e +#define regRLC_SMU_ARGUMENT_4_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_5 0x4e0f +#define regRLC_SMU_ARGUMENT_5_BASE_IDX 1 +#define regRLC_IMU_BOOTLOAD_ADDR_HI 0x4e10 +#define regRLC_IMU_BOOTLOAD_ADDR_HI_BASE_IDX 1 +#define regRLC_IMU_BOOTLOAD_ADDR_LO 0x4e11 +#define regRLC_IMU_BOOTLOAD_ADDR_LO_BASE_IDX 1 +#define regRLC_IMU_BOOTLOAD_SIZE 0x4e12 +#define regRLC_IMU_BOOTLOAD_SIZE_BASE_IDX 1 +#define regRLC_IMU_MISC 0x4e16 +#define regRLC_IMU_MISC_BASE_IDX 1 +#define regRLC_IMU_RESET_VECTOR 0x4e17 +#define regRLC_IMU_RESET_VECTOR_BASE_IDX 1 + + +// addressBlock: gc_rlcsdec +// base address: 0x3b980 +#define regRLC_RLCS_DEC_START 0x4e60 +#define regRLC_RLCS_DEC_START_BASE_IDX 1 +#define regRLC_RLCS_DEC_DUMP_ADDR 0x4e61 +#define regRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX 1 +#define regRLC_RLCS_EXCEPTION_REG_1 0x4e62 +#define regRLC_RLCS_EXCEPTION_REG_1_BASE_IDX 1 +#define regRLC_RLCS_EXCEPTION_REG_2 0x4e63 +#define regRLC_RLCS_EXCEPTION_REG_2_BASE_IDX 1 +#define regRLC_RLCS_EXCEPTION_REG_3 0x4e64 +#define regRLC_RLCS_EXCEPTION_REG_3_BASE_IDX 1 +#define regRLC_RLCS_EXCEPTION_REG_4 0x4e65 +#define regRLC_RLCS_EXCEPTION_REG_4_BASE_IDX 1 +#define regRLC_RLCS_CGCG_REQUEST 0x4e66 +#define regRLC_RLCS_CGCG_REQUEST_BASE_IDX 1 +#define regRLC_RLCS_CGCG_STATUS 0x4e67 +#define regRLC_RLCS_CGCG_STATUS_BASE_IDX 1 +#define regRLC_RLCS_SOC_DS_CNTL 0x4e68 +#define regRLC_RLCS_SOC_DS_CNTL_BASE_IDX 1 +#define regRLC_RLCS_GFX_DS_CNTL 0x4e69 +#define regRLC_RLCS_GFX_DS_CNTL_BASE_IDX 1 +#define regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL 0x4e6a +#define regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL_BASE_IDX 1 +#define regRLC_GPM_STAT 0x4e6b +#define regRLC_GPM_STAT_BASE_IDX 1 +#define regRLC_RLCS_GPM_STAT 0x4e6b +#define regRLC_RLCS_GPM_STAT_BASE_IDX 1 +#define regRLC_RLCS_ABORTED_PD_SEQUENCE 0x4e6c +#define regRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX 1 +#define regRLC_RLCS_DIDT_FORCE_STALL 0x4e6d +#define regRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX 1 +#define regRLC_RLCS_IOV_CMD_STATUS 0x4e6e +#define regRLC_RLCS_IOV_CMD_STATUS_BASE_IDX 1 +#define regRLC_RLCS_IOV_CNTX_LOC_SIZE 0x4e6f +#define regRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX 1 +#define regRLC_RLCS_IOV_SCH_BLOCK 0x4e70 +#define regRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX 1 +#define regRLC_RLCS_IOV_VM_BUSY_STATUS 0x4e71 +#define regRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX 1 +#define regRLC_RLCS_GPM_STAT_2 0x4e72 +#define regRLC_RLCS_GPM_STAT_2_BASE_IDX 1 +#define regRLC_RLCS_GRBM_SOFT_RESET 0x4e73 +#define regRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX 1 +#define regRLC_RLCS_PG_CHANGE_STATUS 0x4e74 +#define regRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX 1 +#define regRLC_RLCS_PG_CHANGE_READ 0x4e75 +#define regRLC_RLCS_PG_CHANGE_READ_BASE_IDX 1 +#define regRLC_RLCS_IH_SEMAPHORE 0x4e76 +#define regRLC_RLCS_IH_SEMAPHORE_BASE_IDX 1 +#define regRLC_RLCS_IH_COOKIE_SEMAPHORE 0x4e77 +#define regRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX 1 +#define regRLC_RLCS_WGP_STATUS 0x4e78 +#define regRLC_RLCS_WGP_STATUS_BASE_IDX 1 +#define regRLC_RLCS_WGP_READ 0x4e79 +#define regRLC_RLCS_WGP_READ_BASE_IDX 1 +#define regRLC_RLCS_CP_INT_CTRL_1 0x4e7a +#define regRLC_RLCS_CP_INT_CTRL_1_BASE_IDX 1 +#define regRLC_RLCS_CP_INT_CTRL_2 0x4e7b +#define regRLC_RLCS_CP_INT_CTRL_2_BASE_IDX 1 +#define regRLC_RLCS_CP_INT_INFO_1 0x4e7c +#define regRLC_RLCS_CP_INT_INFO_1_BASE_IDX 1 +#define regRLC_RLCS_CP_INT_INFO_2 0x4e7d +#define regRLC_RLCS_CP_INT_INFO_2_BASE_IDX 1 +#define regRLC_RLCS_SPM_INT_CTRL 0x4e7e +#define regRLC_RLCS_SPM_INT_CTRL_BASE_IDX 1 +#define regRLC_RLCS_SPM_INT_INFO_1 0x4e7f +#define regRLC_RLCS_SPM_INT_INFO_1_BASE_IDX 1 +#define regRLC_RLCS_SPM_INT_INFO_2 0x4e80 +#define regRLC_RLCS_SPM_INT_INFO_2_BASE_IDX 1 +#define regRLC_RLCS_DSM_TRIG 0x4e81 +#define regRLC_RLCS_DSM_TRIG_BASE_IDX 1 +#define regRLC_RLCS_BOOTLOAD_STATUS 0x4e82 +#define regRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX 1 +#define regRLC_RLCS_POWER_BRAKE_CNTL 0x4e83 +#define regRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX 1 +#define regRLC_RLCS_POWER_BRAKE_CNTL_TH1 0x4e84 +#define regRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX 1 +#define regRLC_RLCS_GRBM_IDLE_BUSY_STAT 0x4e85 +#define regRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX 1 +#define regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL 0x4e86 +#define regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX 1 +#define regRLC_RLCS_CMP_IDLE_CNTL 0x4e87 +#define regRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_0 0x4e88 +#define regRLC_RLCS_GENERAL_0_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_1 0x4e89 +#define regRLC_RLCS_GENERAL_1_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_2 0x4e8a +#define regRLC_RLCS_GENERAL_2_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_3 0x4e8b +#define regRLC_RLCS_GENERAL_3_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_4 0x4e8c +#define regRLC_RLCS_GENERAL_4_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_5 0x4e8d +#define regRLC_RLCS_GENERAL_5_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_6 0x4e8e +#define regRLC_RLCS_GENERAL_6_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_7 0x4e8f +#define regRLC_RLCS_GENERAL_7_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_8 0x4e90 +#define regRLC_RLCS_GENERAL_8_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_9 0x4e91 +#define regRLC_RLCS_GENERAL_9_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_10 0x4e92 +#define regRLC_RLCS_GENERAL_10_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_11 0x4e93 +#define regRLC_RLCS_GENERAL_11_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_12 0x4e94 +#define regRLC_RLCS_GENERAL_12_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_13 0x4e95 +#define regRLC_RLCS_GENERAL_13_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_14 0x4e96 +#define regRLC_RLCS_GENERAL_14_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_15 0x4e97 +#define regRLC_RLCS_GENERAL_15_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_16 0x4e98 +#define regRLC_RLCS_GENERAL_16_BASE_IDX 1 +#define regRLC_RLCS_AUXILIARY_REG_1 0x4ec5 +#define regRLC_RLCS_AUXILIARY_REG_1_BASE_IDX 1 +#define regRLC_RLCS_AUXILIARY_REG_2 0x4ec6 +#define regRLC_RLCS_AUXILIARY_REG_2_BASE_IDX 1 +#define regRLC_RLCS_AUXILIARY_REG_3 0x4ec7 +#define regRLC_RLCS_AUXILIARY_REG_3_BASE_IDX 1 +#define regRLC_RLCS_AUXILIARY_REG_4 0x4ec8 +#define regRLC_RLCS_AUXILIARY_REG_4_BASE_IDX 1 +#define regRLC_RLCS_SPM_SQTT_MODE 0x4ec9 +#define regRLC_RLCS_SPM_SQTT_MODE_BASE_IDX 1 +#define regRLC_RLCS_CP_DMA_SRCID_OVER 0x4eca +#define regRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX 1 +#define regRLC_RLCS_BOOTLOAD_ID_STATUS1 0x4ecb +#define regRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX 1 +#define regRLC_RLCS_BOOTLOAD_ID_STATUS2 0x4ecc +#define regRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX 1 +#define regRLC_RLCS_IMU_VIDCHG_CNTL 0x4ecd +#define regRLC_RLCS_IMU_VIDCHG_CNTL_BASE_IDX 1 +#define regRLC_RLCS_EDC_INT_CNTL 0x4ece +#define regRLC_RLCS_EDC_INT_CNTL_BASE_IDX 1 +#define regRLC_RLCS_KMD_LOG_CNTL1 0x4ecf +#define regRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX 1 +#define regRLC_RLCS_KMD_LOG_CNTL2 0x4ed0 +#define regRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX 1 +#define regRLC_RLCS_GPM_LEGACY_INT_STAT 0x4ed1 +#define regRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX 1 +#define regRLC_RLCS_GPM_LEGACY_INT_DISABLE 0x4ed2 +#define regRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX 1 +#define regRLC_RLCS_SRM_SRCID_CNTL 0x4ed3 +#define regRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX 1 +#define regRLC_RLCS_GCR_DATA_0 0x4ed4 +#define regRLC_RLCS_GCR_DATA_0_BASE_IDX 1 +#define regRLC_RLCS_GCR_DATA_1 0x4ed5 +#define regRLC_RLCS_GCR_DATA_1_BASE_IDX 1 +#define regRLC_RLCS_GCR_DATA_2 0x4ed6 +#define regRLC_RLCS_GCR_DATA_2_BASE_IDX 1 +#define regRLC_RLCS_GCR_DATA_3 0x4ed7 +#define regRLC_RLCS_GCR_DATA_3_BASE_IDX 1 +#define regRLC_RLCS_GCR_STATUS 0x4ed8 +#define regRLC_RLCS_GCR_STATUS_BASE_IDX 1 +#define regRLC_RLCS_PERFMON_CLK_CNTL_UCODE 0x4ed9 +#define regRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX 1 +#define regRLC_RLCS_UTCL2_CNTL 0x4eda +#define regRLC_RLCS_UTCL2_CNTL_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_DATA0 0x4edb +#define regRLC_RLCS_IMU_RLC_MSG_DATA0_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_DATA1 0x4edc +#define regRLC_RLCS_IMU_RLC_MSG_DATA1_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_DATA2 0x4edd +#define regRLC_RLCS_IMU_RLC_MSG_DATA2_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_DATA3 0x4ede +#define regRLC_RLCS_IMU_RLC_MSG_DATA3_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_DATA4 0x4edf +#define regRLC_RLCS_IMU_RLC_MSG_DATA4_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_CONTROL 0x4ee0 +#define regRLC_RLCS_IMU_RLC_MSG_CONTROL_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_CNTL 0x4ee1 +#define regRLC_RLCS_IMU_RLC_MSG_CNTL_BASE_IDX 1 +#define regRLC_RLCS_RLC_IMU_MSG_DATA0 0x4ee2 +#define regRLC_RLCS_RLC_IMU_MSG_DATA0_BASE_IDX 1 +#define regRLC_RLCS_RLC_IMU_MSG_CONTROL 0x4ee3 +#define regRLC_RLCS_RLC_IMU_MSG_CONTROL_BASE_IDX 1 +#define regRLC_RLCS_RLC_IMU_MSG_CNTL 0x4ee4 +#define regRLC_RLCS_RLC_IMU_MSG_CNTL_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0 0x4ee5 +#define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1 0x4ee6 +#define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MUTEX_CNTL 0x4ee7 +#define regRLC_RLCS_IMU_RLC_MUTEX_CNTL_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_STATUS 0x4ee8 +#define regRLC_RLCS_IMU_RLC_STATUS_BASE_IDX 1 +#define regRLC_RLCS_RLC_IMU_STATUS 0x4ee9 +#define regRLC_RLCS_RLC_IMU_STATUS_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_DATA_1 0x4eea +#define regRLC_RLCS_IMU_RAM_DATA_1_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_ADDR_1_LSB 0x4eeb +#define regRLC_RLCS_IMU_RAM_ADDR_1_LSB_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_ADDR_1_MSB 0x4eec +#define regRLC_RLCS_IMU_RAM_ADDR_1_MSB_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_DATA_0 0x4eed +#define regRLC_RLCS_IMU_RAM_DATA_0_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_ADDR_0_LSB 0x4eee +#define regRLC_RLCS_IMU_RAM_ADDR_0_LSB_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_ADDR_0_MSB 0x4eef +#define regRLC_RLCS_IMU_RAM_ADDR_0_MSB_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_CNTL 0x4ef0 +#define regRLC_RLCS_IMU_RAM_CNTL_BASE_IDX 1 +#define regRLC_RLCS_IMU_GFX_DOORBELL_FENCE 0x4ef1 +#define regRLC_RLCS_IMU_GFX_DOORBELL_FENCE_BASE_IDX 1 +#define regRLC_RLCS_SDMA_INT_CNTL_1 0x4ef3 +#define regRLC_RLCS_SDMA_INT_CNTL_1_BASE_IDX 1 +#define regRLC_RLCS_SDMA_INT_CNTL_2 0x4ef4 +#define regRLC_RLCS_SDMA_INT_CNTL_2_BASE_IDX 1 +#define regRLC_RLCS_SDMA_INT_STAT 0x4ef5 +#define regRLC_RLCS_SDMA_INT_STAT_BASE_IDX 1 +#define regRLC_RLCS_SDMA_INT_INFO 0x4ef6 +#define regRLC_RLCS_SDMA_INT_INFO_BASE_IDX 1 +#define regRLC_RLCS_PMM_CGCG_CNTL 0x4ef7 +#define regRLC_RLCS_PMM_CGCG_CNTL_BASE_IDX 1 +#define regRLC_RLCS_GFX_MEM_POWER_CTRL_LO 0x4ef8 +#define regRLC_RLCS_GFX_MEM_POWER_CTRL_LO_BASE_IDX 1 +#define regRLC_RLCS_GFX_RM_CNTL 0x4efa +#define regRLC_RLCS_GFX_RM_CNTL_BASE_IDX 1 +#define regRLC_RLCS_DEC_END 0x4fff +#define regRLC_RLCS_DEC_END_BASE_IDX 1 + + +// addressBlock: gc_pfvfdec_rlc +// base address: 0x2a600 +#define regRLC_SAFE_MODE 0x0980 +#define regRLC_SAFE_MODE_BASE_IDX 1 +#define regRLC_SPM_SAMPLE_CNT 0x0981 +#define regRLC_SPM_SAMPLE_CNT_BASE_IDX 1 +#define regRLC_SPM_MC_CNTL 0x0982 +#define regRLC_SPM_MC_CNTL_BASE_IDX 1 +#define regRLC_SPM_INT_CNTL 0x0983 +#define regRLC_SPM_INT_CNTL_BASE_IDX 1 +#define regRLC_SPM_INT_STATUS 0x0984 +#define regRLC_SPM_INT_STATUS_BASE_IDX 1 +#define regRLC_SPM_INT_INFO_1 0x0985 +#define regRLC_SPM_INT_INFO_1_BASE_IDX 1 +#define regRLC_SPM_INT_INFO_2 0x0986 +#define regRLC_SPM_INT_INFO_2_BASE_IDX 1 +#define regRLC_CSIB_ADDR_LO 0x0987 +#define regRLC_CSIB_ADDR_LO_BASE_IDX 1 +#define regRLC_CSIB_ADDR_HI 0x0988 +#define regRLC_CSIB_ADDR_HI_BASE_IDX 1 +#define regRLC_CSIB_LENGTH 0x0989 +#define regRLC_CSIB_LENGTH_BASE_IDX 1 +#define regRLC_CP_SCHEDULERS 0x098a +#define regRLC_CP_SCHEDULERS_BASE_IDX 1 +#define regRLC_CP_EOF_INT 0x098b +#define regRLC_CP_EOF_INT_BASE_IDX 1 +#define regRLC_CP_EOF_INT_CNT 0x098c +#define regRLC_CP_EOF_INT_CNT_BASE_IDX 1 +#define regRLC_SPARE_INT_0 0x098d +#define regRLC_SPARE_INT_0_BASE_IDX 1 +#define regRLC_SPARE_INT_1 0x098e +#define regRLC_SPARE_INT_1_BASE_IDX 1 +#define regRLC_SPARE_INT_2 0x098f +#define regRLC_SPARE_INT_2_BASE_IDX 1 +#define regRLC_PACE_SPARE_INT 0x0990 +#define regRLC_PACE_SPARE_INT_BASE_IDX 1 +#define regRLC_PACE_SPARE_INT_1 0x0991 +#define regRLC_PACE_SPARE_INT_1_BASE_IDX 1 +#define regRLC_RLCV_SPARE_INT_1 0x0992 +#define regRLC_RLCV_SPARE_INT_1_BASE_IDX 1 + + +// addressBlock: gc_pwrdec +// base address: 0x3c000 +#define regCGTS_TCC_DISABLE 0x5006 +#define regCGTS_TCC_DISABLE_BASE_IDX 1 +#define regCGTT_GS_NGG_CLK_CTRL 0x5087 +#define regCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 +#define regCGTT_PA_CLK_CTRL 0x5088 +#define regCGTT_PA_CLK_CTRL_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL0 0x5089 +#define regCGTT_SC_CLK_CTRL0_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL1 0x508a +#define regCGTT_SC_CLK_CTRL1_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL2 0x508b +#define regCGTT_SC_CLK_CTRL2_BASE_IDX 1 +#define regCGTT_SQG_CLK_CTRL 0x508d +#define regCGTT_SQG_CLK_CTRL_BASE_IDX 1 +#define regSQ_ALU_CLK_CTRL 0x508e +#define regSQ_ALU_CLK_CTRL_BASE_IDX 1 +#define regSQ_TEX_CLK_CTRL 0x508f +#define regSQ_TEX_CLK_CTRL_BASE_IDX 1 +#define regSQ_LDS_CLK_CTRL 0x5090 +#define regSQ_LDS_CLK_CTRL_BASE_IDX 1 +#define regICG_SP_CLK_CTRL 0x5093 +#define regICG_SP_CLK_CTRL_BASE_IDX 1 +#define regTA_CGTT_CTRL 0x509d +#define regTA_CGTT_CTRL_BASE_IDX 1 +#define regDB_CGTT_CLK_CTRL_0 0x50a4 +#define regDB_CGTT_CLK_CTRL_0_BASE_IDX 1 +#define regCB_CGTT_SCLK_CTRL 0x50a8 +#define regCB_CGTT_SCLK_CTRL_BASE_IDX 1 +#define regCGTT_CP_CLK_CTRL 0x50b0 +#define regCGTT_CP_CLK_CTRL_BASE_IDX 1 +#define regCGTT_CPF_CLK_CTRL 0x50b1 +#define regCGTT_CPF_CLK_CTRL_BASE_IDX 1 +#define regCGTT_CPC_CLK_CTRL 0x50b2 +#define regCGTT_CPC_CLK_CTRL_BASE_IDX 1 +#define regCGTT_RLC_CLK_CTRL 0x50b5 +#define regCGTT_RLC_CLK_CTRL_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL3 0x50bc +#define regCGTT_SC_CLK_CTRL3_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL4 0x50bd +#define regCGTT_SC_CLK_CTRL4_BASE_IDX 1 +#define regGCEA_ICG_CTRL 0x50c4 +#define regGCEA_ICG_CTRL_BASE_IDX 1 +#define regGL1I_GL1R_MGCG_OVERRIDE 0x50e4 +#define regGL1I_GL1R_MGCG_OVERRIDE_BASE_IDX 1 +#define regGL1H_ICG_CTRL 0x50e8 +#define regGL1H_ICG_CTRL_BASE_IDX 1 +#define regCHI_CHR_MGCG_OVERRIDE 0x50e9 +#define regCHI_CHR_MGCG_OVERRIDE_BASE_IDX 1 +#define regICG_GL1C_CLK_CTRL 0x50ec +#define regICG_GL1C_CLK_CTRL_BASE_IDX 1 +#define regICG_GL1A_CTRL 0x50f0 +#define regICG_GL1A_CTRL_BASE_IDX 1 +#define regICG_CHA_CTRL 0x50f1 +#define regICG_CHA_CTRL_BASE_IDX 1 +#define regGUS_ICG_CTRL 0x50f4 +#define regGUS_ICG_CTRL_BASE_IDX 1 +#define regCGTT_PH_CLK_CTRL0 0x50f8 +#define regCGTT_PH_CLK_CTRL0_BASE_IDX 1 +#define regCGTT_PH_CLK_CTRL1 0x50f9 +#define regCGTT_PH_CLK_CTRL1_BASE_IDX 1 +#define regCGTT_PH_CLK_CTRL2 0x50fa +#define regCGTT_PH_CLK_CTRL2_BASE_IDX 1 +#define regCGTT_PH_CLK_CTRL3 0x50fb +#define regCGTT_PH_CLK_CTRL3_BASE_IDX 1 +#define regGFX_ICG_GL2C_CTRL 0x50fc +#define regGFX_ICG_GL2C_CTRL_BASE_IDX 1 +#define regGFX_ICG_GL2C_CTRL1 0x50fd +#define regGFX_ICG_GL2C_CTRL1_BASE_IDX 1 +#define regICG_LDS_CLK_CTRL 0x5114 +#define regICG_LDS_CLK_CTRL_BASE_IDX 1 +#define regICG_CHC_CLK_CTRL 0x5140 +#define regICG_CHC_CLK_CTRL_BASE_IDX 1 +#define regICG_CHCG_CLK_CTRL 0x5144 +#define regICG_CHCG_CLK_CTRL_BASE_IDX 1 + + +// addressBlock: gc_hypdec +// base address: 0x3e000 +#define regGFX_PIPE_PRIORITY 0x587f +#define regGFX_PIPE_PRIORITY_BASE_IDX 1 +#define regGRBM_GFX_INDEX_SR_SELECT 0x5a00 +#define regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX 1 +#define regGRBM_GFX_INDEX_SR_DATA 0x5a01 +#define regGRBM_GFX_INDEX_SR_DATA_BASE_IDX 1 +#define regGRBM_GFX_CNTL_SR_SELECT 0x5a02 +#define regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX 1 +#define regGRBM_GFX_CNTL_SR_DATA 0x5a03 +#define regGRBM_GFX_CNTL_SR_DATA_BASE_IDX 1 +#define regGC_IH_COOKIE_0_PTR 0x5a07 +#define regGC_IH_COOKIE_0_PTR_BASE_IDX 1 +#define regGRBM_SE_REMAP_CNTL 0x5a08 +#define regGRBM_SE_REMAP_CNTL_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_ENABLE 0x5b00 +#define regRLC_GPU_IOV_VF_ENABLE_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG6 0x5b06 +#define regRLC_GPU_IOV_CFG_REG6_BASE_IDX 1 +#define regRLC_SDMA0_STATUS 0x5b18 +#define regRLC_SDMA0_STATUS_BASE_IDX 1 +#define regRLC_SDMA1_STATUS 0x5b19 +#define regRLC_SDMA1_STATUS_BASE_IDX 1 +#define regRLC_SDMA2_STATUS 0x5b1a +#define regRLC_SDMA2_STATUS_BASE_IDX 1 +#define regRLC_SDMA3_STATUS 0x5b1b +#define regRLC_SDMA3_STATUS_BASE_IDX 1 +#define regRLC_SDMA0_BUSY_STATUS 0x5b1c +#define regRLC_SDMA0_BUSY_STATUS_BASE_IDX 1 +#define regRLC_SDMA1_BUSY_STATUS 0x5b1d +#define regRLC_SDMA1_BUSY_STATUS_BASE_IDX 1 +#define regRLC_SDMA2_BUSY_STATUS 0x5b1e +#define regRLC_SDMA2_BUSY_STATUS_BASE_IDX 1 +#define regRLC_SDMA3_BUSY_STATUS 0x5b1f +#define regRLC_SDMA3_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG8 0x5b20 +#define regRLC_GPU_IOV_CFG_REG8_BASE_IDX 1 +#define regRLC_RLCV_TIMER_INT_0 0x5b25 +#define regRLC_RLCV_TIMER_INT_0_BASE_IDX 1 +#define regRLC_RLCV_TIMER_INT_1 0x5b26 +#define regRLC_RLCV_TIMER_INT_1_BASE_IDX 1 +#define regRLC_RLCV_TIMER_CTRL 0x5b27 +#define regRLC_RLCV_TIMER_CTRL_BASE_IDX 1 +#define regRLC_RLCV_TIMER_STAT 0x5b28 +#define regRLC_RLCV_TIMER_STAT_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS 0x5b2a +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0x5b2b +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0x5b2c +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_MASK 0x5b2d +#define regRLC_GPU_IOV_VF_MASK_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_0 0x5b2e +#define regRLC_HYP_SEMAPHORE_0_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_1 0x5b2f +#define regRLC_HYP_SEMAPHORE_1_BASE_IDX 1 +#define regRLC_BUSY_CLK_CNTL 0x5b30 +#define regRLC_BUSY_CLK_CNTL_BASE_IDX 1 +#define regRLC_CLK_CNTL 0x5b31 +#define regRLC_CLK_CNTL_BASE_IDX 1 +#define regRLC_PACE_TIMER_STAT 0x5b33 +#define regRLC_PACE_TIMER_STAT_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_BLOCK 0x5b34 +#define regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG1 0x5b35 +#define regRLC_GPU_IOV_CFG_REG1_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG2 0x5b36 +#define regRLC_GPU_IOV_CFG_REG2_BASE_IDX 1 +#define regRLC_GPU_IOV_VM_BUSY_STATUS 0x5b37 +#define regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_0 0x5b38 +#define regRLC_GPU_IOV_SCH_0_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_3 0x5b3a +#define regRLC_GPU_IOV_SCH_3_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_1 0x5b3b +#define regRLC_GPU_IOV_SCH_1_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_2 0x5b3c +#define regRLC_GPU_IOV_SCH_2_BASE_IDX 1 +#define regRLC_PACE_INT_FORCE 0x5b3d +#define regRLC_PACE_INT_FORCE_BASE_IDX 1 +#define regRLC_PACE_INT_CLEAR 0x5b3e +#define regRLC_PACE_INT_CLEAR_BASE_IDX 1 +#define regRLC_GPU_IOV_INT_STAT 0x5b3f +#define regRLC_GPU_IOV_INT_STAT_BASE_IDX 1 +#define regRLC_IH_COOKIE 0x5b41 +#define regRLC_IH_COOKIE_BASE_IDX 1 +#define regRLC_IH_COOKIE_CNTL 0x5b42 +#define regRLC_IH_COOKIE_CNTL_BASE_IDX 1 +#define regRLC_HYP_RLCG_UCODE_CHKSUM 0x5b43 +#define regRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX 1 +#define regRLC_HYP_RLCP_UCODE_CHKSUM 0x5b44 +#define regRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX 1 +#define regRLC_HYP_RLCV_UCODE_CHKSUM 0x5b45 +#define regRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX 1 +#define regRLC_GPU_IOV_F32_CNTL 0x5b46 +#define regRLC_GPU_IOV_F32_CNTL_BASE_IDX 1 +#define regRLC_GPU_IOV_F32_RESET 0x5b47 +#define regRLC_GPU_IOV_F32_RESET_BASE_IDX 1 +#define regRLC_GPU_IOV_UCODE_ADDR 0x5b48 +#define regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX 1 +#define regRLC_GPU_IOV_UCODE_DATA 0x5b49 +#define regRLC_GPU_IOV_UCODE_DATA_BASE_IDX 1 +#define regRLC_GPU_IOV_SMU_RESPONSE 0x5b4a +#define regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX 1 +#define regRLC_GPU_IOV_F32_INVALIDATE_CACHE 0x5b4b +#define regRLC_GPU_IOV_F32_INVALIDATE_CACHE_BASE_IDX 1 +#define regRLC_GPU_IOV_RLC_RESPONSE 0x5b4d +#define regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX 1 +#define regRLC_GPU_IOV_INT_DISABLE 0x5b4e +#define regRLC_GPU_IOV_INT_DISABLE_BASE_IDX 1 +#define regRLC_GPU_IOV_INT_FORCE 0x5b4f +#define regRLC_GPU_IOV_INT_FORCE_BASE_IDX 1 +#define regRLC_GPU_IOV_SCRATCH_ADDR 0x5b50 +#define regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX 1 +#define regRLC_GPU_IOV_SCRATCH_DATA 0x5b51 +#define regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_2 0x5b52 +#define regRLC_HYP_SEMAPHORE_2_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_3 0x5b53 +#define regRLC_HYP_SEMAPHORE_3_BASE_IDX 1 +#define regRLC_GPM_UCODE_ADDR 0x5b60 +#define regRLC_GPM_UCODE_ADDR_BASE_IDX 1 +#define regRLC_GPM_UCODE_DATA 0x5b61 +#define regRLC_GPM_UCODE_DATA_BASE_IDX 1 +#define regRLC_GPM_IRAM_ADDR 0x5b62 +#define regRLC_GPM_IRAM_ADDR_BASE_IDX 1 +#define regRLC_GPM_IRAM_DATA 0x5b63 +#define regRLC_GPM_IRAM_DATA_BASE_IDX 1 +#define regRLC_RLCP_IRAM_ADDR 0x5b64 +#define regRLC_RLCP_IRAM_ADDR_BASE_IDX 1 +#define regRLC_RLCP_IRAM_DATA 0x5b65 +#define regRLC_RLCP_IRAM_DATA_BASE_IDX 1 +#define regRLC_RLCV_IRAM_ADDR 0x5b66 +#define regRLC_RLCV_IRAM_ADDR_BASE_IDX 1 +#define regRLC_RLCV_IRAM_DATA 0x5b67 +#define regRLC_RLCV_IRAM_DATA_BASE_IDX 1 +#define regRLC_LX6_DRAM_ADDR 0x5b68 +#define regRLC_LX6_DRAM_ADDR_BASE_IDX 1 +#define regRLC_LX6_DRAM_DATA 0x5b69 +#define regRLC_LX6_DRAM_DATA_BASE_IDX 1 +#define regRLC_LX6_IRAM_ADDR 0x5b6a +#define regRLC_LX6_IRAM_ADDR_BASE_IDX 1 +#define regRLC_LX6_IRAM_DATA 0x5b6b +#define regRLC_LX6_IRAM_DATA_BASE_IDX 1 +#define regRLC_PACE_UCODE_ADDR 0x5b6c +#define regRLC_PACE_UCODE_ADDR_BASE_IDX 1 +#define regRLC_PACE_UCODE_DATA 0x5b6d +#define regRLC_PACE_UCODE_DATA_BASE_IDX 1 +#define regRLC_GPM_SCRATCH_ADDR 0x5b6e +#define regRLC_GPM_SCRATCH_ADDR_BASE_IDX 1 +#define regRLC_GPM_SCRATCH_DATA 0x5b6f +#define regRLC_GPM_SCRATCH_DATA_BASE_IDX 1 +#define regRLC_SRM_DRAM_ADDR 0x5b71 +#define regRLC_SRM_DRAM_ADDR_BASE_IDX 1 +#define regRLC_SRM_DRAM_DATA 0x5b72 +#define regRLC_SRM_DRAM_DATA_BASE_IDX 1 +#define regRLC_SRM_ARAM_ADDR 0x5b73 +#define regRLC_SRM_ARAM_ADDR_BASE_IDX 1 +#define regRLC_SRM_ARAM_DATA 0x5b74 +#define regRLC_SRM_ARAM_DATA_BASE_IDX 1 +#define regRLC_PACE_SCRATCH_ADDR 0x5b77 +#define regRLC_PACE_SCRATCH_ADDR_BASE_IDX 1 +#define regRLC_PACE_SCRATCH_DATA 0x5b78 +#define regRLC_PACE_SCRATCH_DATA_BASE_IDX 1 +#define regRLC_GTS_OFFSET_LSB 0x5b79 +#define regRLC_GTS_OFFSET_LSB_BASE_IDX 1 +#define regRLC_GTS_OFFSET_MSB 0x5b7a +#define regRLC_GTS_OFFSET_MSB_BASE_IDX 1 +#define regGL2_PIPE_STEER_0 0x5b80 +#define regGL2_PIPE_STEER_0_BASE_IDX 1 +#define regGL2_PIPE_STEER_1 0x5b81 +#define regGL2_PIPE_STEER_1_BASE_IDX 1 +#define regGL2_PIPE_STEER_2 0x5b82 +#define regGL2_PIPE_STEER_2_BASE_IDX 1 +#define regGL2_PIPE_STEER_3 0x5b83 +#define regGL2_PIPE_STEER_3_BASE_IDX 1 +#define regGL1_PIPE_STEER 0x5b84 +#define regGL1_PIPE_STEER_BASE_IDX 1 +#define regCH_PIPE_STEER 0x5b88 +#define regCH_PIPE_STEER_BASE_IDX 1 +#define regGC_USER_SHADER_ARRAY_CONFIG 0x5b90 +#define regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 1 +#define regGC_USER_PRIM_CONFIG 0x5b91 +#define regGC_USER_PRIM_CONFIG_BASE_IDX 1 +#define regGC_USER_SA_UNIT_DISABLE 0x5b92 +#define regGC_USER_SA_UNIT_DISABLE_BASE_IDX 1 +#define regGC_USER_RB_REDUNDANCY 0x5b93 +#define regGC_USER_RB_REDUNDANCY_BASE_IDX 1 +#define regGC_USER_RB_BACKEND_DISABLE 0x5b94 +#define regGC_USER_RB_BACKEND_DISABLE_BASE_IDX 1 +#define regGC_USER_RMI_REDUNDANCY 0x5b95 +#define regGC_USER_RMI_REDUNDANCY_BASE_IDX 1 +#define regCGTS_USER_TCC_DISABLE 0x5b96 +#define regCGTS_USER_TCC_DISABLE_BASE_IDX 1 +#define regGC_USER_SHADER_RATE_CONFIG 0x5b97 +#define regGC_USER_SHADER_RATE_CONFIG_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA0_STATUS 0x5bc0 +#define regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA1_STATUS 0x5bc1 +#define regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA2_STATUS 0x5bc2 +#define regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA3_STATUS 0x5bc3 +#define regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA4_STATUS 0x5bc4 +#define regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA5_STATUS 0x5bc5 +#define regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA6_STATUS 0x5bc6 +#define regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA7_STATUS 0x5bc7 +#define regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA0_BUSY_STATUS 0x5bc8 +#define regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA1_BUSY_STATUS 0x5bc9 +#define regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA2_BUSY_STATUS 0x5bca +#define regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA3_BUSY_STATUS 0x5bcb +#define regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA4_BUSY_STATUS 0x5bcc +#define regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA5_BUSY_STATUS 0x5bcd +#define regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA6_BUSY_STATUS 0x5bce +#define regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA7_BUSY_STATUS 0x5bcf +#define regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX 1 + + +// addressBlock: gc_pspdec +// base address: 0x3f000 +#define regCP_MES_DM_INDEX_ADDR 0x5c00 +#define regCP_MES_DM_INDEX_ADDR_BASE_IDX 1 +#define regCP_MES_DM_INDEX_DATA 0x5c01 +#define regCP_MES_DM_INDEX_DATA_BASE_IDX 1 +#define regCP_MEC_DM_INDEX_ADDR 0x5c02 +#define regCP_MEC_DM_INDEX_ADDR_BASE_IDX 1 +#define regCP_MEC_DM_INDEX_DATA 0x5c03 +#define regCP_MEC_DM_INDEX_DATA_BASE_IDX 1 +#define regCP_GFX_RS64_DM_INDEX_ADDR 0x5c04 +#define regCP_GFX_RS64_DM_INDEX_ADDR_BASE_IDX 1 +#define regCP_GFX_RS64_DM_INDEX_DATA 0x5c05 +#define regCP_GFX_RS64_DM_INDEX_DATA_BASE_IDX 1 +#define regCPG_PSP_DEBUG 0x5c10 +#define regCPG_PSP_DEBUG_BASE_IDX 1 +#define regCPC_PSP_DEBUG 0x5c11 +#define regCPC_PSP_DEBUG_BASE_IDX 1 +#define regGRBM_SEC_CNTL 0x5e0d +#define regGRBM_SEC_CNTL_BASE_IDX 1 +#define regGRBM_CAM_INDEX 0x5e10 +#define regGRBM_CAM_INDEX_BASE_IDX 1 +#define regGRBM_HYP_CAM_INDEX 0x5e10 +#define regGRBM_HYP_CAM_INDEX_BASE_IDX 1 +#define regGRBM_CAM_DATA 0x5e11 +#define regGRBM_CAM_DATA_BASE_IDX 1 +#define regGRBM_HYP_CAM_DATA 0x5e11 +#define regGRBM_HYP_CAM_DATA_BASE_IDX 1 +#define regGRBM_CAM_DATA_UPPER 0x5e12 +#define regGRBM_CAM_DATA_UPPER_BASE_IDX 1 +#define regGRBM_HYP_CAM_DATA_UPPER 0x5e12 +#define regGRBM_HYP_CAM_DATA_UPPER_BASE_IDX 1 +#define regRLC_FWL_FIRST_VIOL_ADDR 0x5f26 +#define regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX 1 + + +// addressBlock: gc_gfx_imu_gfx_imudec +// base address: 0x38000 +#define regGFX_IMU_C2PMSG_0 0x4000 +#define regGFX_IMU_C2PMSG_0_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_1 0x4001 +#define regGFX_IMU_C2PMSG_1_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_2 0x4002 +#define regGFX_IMU_C2PMSG_2_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_3 0x4003 +#define regGFX_IMU_C2PMSG_3_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_4 0x4004 +#define regGFX_IMU_C2PMSG_4_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_5 0x4005 +#define regGFX_IMU_C2PMSG_5_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_6 0x4006 +#define regGFX_IMU_C2PMSG_6_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_7 0x4007 +#define regGFX_IMU_C2PMSG_7_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_8 0x4008 +#define regGFX_IMU_C2PMSG_8_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_9 0x4009 +#define regGFX_IMU_C2PMSG_9_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_10 0x400a +#define regGFX_IMU_C2PMSG_10_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_11 0x400b +#define regGFX_IMU_C2PMSG_11_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_12 0x400c +#define regGFX_IMU_C2PMSG_12_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_13 0x400d +#define regGFX_IMU_C2PMSG_13_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_14 0x400e +#define regGFX_IMU_C2PMSG_14_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_15 0x400f +#define regGFX_IMU_C2PMSG_15_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_16 0x4010 +#define regGFX_IMU_C2PMSG_16_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_17 0x4011 +#define regGFX_IMU_C2PMSG_17_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_18 0x4012 +#define regGFX_IMU_C2PMSG_18_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_19 0x4013 +#define regGFX_IMU_C2PMSG_19_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_20 0x4014 +#define regGFX_IMU_C2PMSG_20_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_21 0x4015 +#define regGFX_IMU_C2PMSG_21_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_22 0x4016 +#define regGFX_IMU_C2PMSG_22_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_23 0x4017 +#define regGFX_IMU_C2PMSG_23_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_24 0x4018 +#define regGFX_IMU_C2PMSG_24_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_25 0x4019 +#define regGFX_IMU_C2PMSG_25_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_26 0x401a +#define regGFX_IMU_C2PMSG_26_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_27 0x401b +#define regGFX_IMU_C2PMSG_27_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_28 0x401c +#define regGFX_IMU_C2PMSG_28_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_29 0x401d +#define regGFX_IMU_C2PMSG_29_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_30 0x401e +#define regGFX_IMU_C2PMSG_30_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_31 0x401f +#define regGFX_IMU_C2PMSG_31_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_32 0x4020 +#define regGFX_IMU_C2PMSG_32_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_33 0x4021 +#define regGFX_IMU_C2PMSG_33_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_34 0x4022 +#define regGFX_IMU_C2PMSG_34_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_35 0x4023 +#define regGFX_IMU_C2PMSG_35_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_36 0x4024 +#define regGFX_IMU_C2PMSG_36_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_37 0x4025 +#define regGFX_IMU_C2PMSG_37_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_38 0x4026 +#define regGFX_IMU_C2PMSG_38_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_39 0x4027 +#define regGFX_IMU_C2PMSG_39_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_40 0x4028 +#define regGFX_IMU_C2PMSG_40_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_41 0x4029 +#define regGFX_IMU_C2PMSG_41_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_42 0x402a +#define regGFX_IMU_C2PMSG_42_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_43 0x402b +#define regGFX_IMU_C2PMSG_43_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_44 0x402c +#define regGFX_IMU_C2PMSG_44_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_45 0x402d +#define regGFX_IMU_C2PMSG_45_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_46 0x402e +#define regGFX_IMU_C2PMSG_46_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_47 0x402f +#define regGFX_IMU_C2PMSG_47_BASE_IDX 1 +#define regGFX_IMU_MSG_FLAGS 0x403f +#define regGFX_IMU_MSG_FLAGS_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_ACCESS_CTRL0 0x4040 +#define regGFX_IMU_C2PMSG_ACCESS_CTRL0_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_ACCESS_CTRL1 0x4041 +#define regGFX_IMU_C2PMSG_ACCESS_CTRL1_BASE_IDX 1 +#define regGFX_IMU_PWRMGT_IRQ_CTRL 0x4042 +#define regGFX_IMU_PWRMGT_IRQ_CTRL_BASE_IDX 1 +#define regGFX_IMU_MP1_MUTEX 0x4043 +#define regGFX_IMU_MP1_MUTEX_BASE_IDX 1 +#define regGFX_IMU_RLC_DATA_4 0x4046 +#define regGFX_IMU_RLC_DATA_4_BASE_IDX 1 +#define regGFX_IMU_RLC_DATA_3 0x4047 +#define regGFX_IMU_RLC_DATA_3_BASE_IDX 1 +#define regGFX_IMU_RLC_DATA_2 0x4048 +#define regGFX_IMU_RLC_DATA_2_BASE_IDX 1 +#define regGFX_IMU_RLC_DATA_1 0x4049 +#define regGFX_IMU_RLC_DATA_1_BASE_IDX 1 +#define regGFX_IMU_RLC_DATA_0 0x404a +#define regGFX_IMU_RLC_DATA_0_BASE_IDX 1 +#define regGFX_IMU_RLC_CMD 0x404b +#define regGFX_IMU_RLC_CMD_BASE_IDX 1 +#define regGFX_IMU_RLC_MUTEX 0x404c +#define regGFX_IMU_RLC_MUTEX_BASE_IDX 1 +#define regGFX_IMU_RLC_MSG_STATUS 0x404f +#define regGFX_IMU_RLC_MSG_STATUS_BASE_IDX 1 +#define regRLC_GFX_IMU_DATA_0 0x4052 +#define regRLC_GFX_IMU_DATA_0_BASE_IDX 1 +#define regRLC_GFX_IMU_CMD 0x4053 +#define regRLC_GFX_IMU_CMD_BASE_IDX 1 +#define regGFX_IMU_RLC_STATUS 0x4054 +#define regGFX_IMU_RLC_STATUS_BASE_IDX 1 +#define regGFX_IMU_STATUS 0x4055 +#define regGFX_IMU_STATUS_BASE_IDX 1 +#define regGFX_IMU_SOC_DATA 0x4059 +#define regGFX_IMU_SOC_DATA_BASE_IDX 1 +#define regGFX_IMU_SOC_ADDR 0x405a +#define regGFX_IMU_SOC_ADDR_BASE_IDX 1 +#define regGFX_IMU_SOC_REQ 0x405b +#define regGFX_IMU_SOC_REQ_BASE_IDX 1 +#define regGFX_IMU_VF_CTRL 0x405c +#define regGFX_IMU_VF_CTRL_BASE_IDX 1 +#define regGFX_IMU_TELEMETRY 0x4060 +#define regGFX_IMU_TELEMETRY_BASE_IDX 1 +#define regGFX_IMU_TELEMETRY_DATA 0x4061 +#define regGFX_IMU_TELEMETRY_DATA_BASE_IDX 1 +#define regGFX_IMU_TELEMETRY_TEMPERATURE 0x4062 +#define regGFX_IMU_TELEMETRY_TEMPERATURE_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_0 0x4068 +#define regGFX_IMU_SCRATCH_0_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_1 0x4069 +#define regGFX_IMU_SCRATCH_1_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_2 0x406a +#define regGFX_IMU_SCRATCH_2_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_3 0x406b +#define regGFX_IMU_SCRATCH_3_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_4 0x406c +#define regGFX_IMU_SCRATCH_4_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_5 0x406d +#define regGFX_IMU_SCRATCH_5_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_6 0x406e +#define regGFX_IMU_SCRATCH_6_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_7 0x406f +#define regGFX_IMU_SCRATCH_7_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_8 0x4070 +#define regGFX_IMU_SCRATCH_8_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_9 0x4071 +#define regGFX_IMU_SCRATCH_9_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_10 0x4072 +#define regGFX_IMU_SCRATCH_10_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_11 0x4073 +#define regGFX_IMU_SCRATCH_11_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_12 0x4074 +#define regGFX_IMU_SCRATCH_12_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_13 0x4075 +#define regGFX_IMU_SCRATCH_13_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_14 0x4076 +#define regGFX_IMU_SCRATCH_14_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_15 0x4077 +#define regGFX_IMU_SCRATCH_15_BASE_IDX 1 +#define regGFX_IMU_FW_GTS_LO 0x4078 +#define regGFX_IMU_FW_GTS_LO_BASE_IDX 1 +#define regGFX_IMU_FW_GTS_HI 0x4079 +#define regGFX_IMU_FW_GTS_HI_BASE_IDX 1 +#define regGFX_IMU_GTS_OFFSET_LO 0x407a +#define regGFX_IMU_GTS_OFFSET_LO_BASE_IDX 1 +#define regGFX_IMU_GTS_OFFSET_HI 0x407b +#define regGFX_IMU_GTS_OFFSET_HI_BASE_IDX 1 +#define regGFX_IMU_RLC_GTS_OFFSET_LO 0x407c +#define regGFX_IMU_RLC_GTS_OFFSET_LO_BASE_IDX 1 +#define regGFX_IMU_RLC_GTS_OFFSET_HI 0x407d +#define regGFX_IMU_RLC_GTS_OFFSET_HI_BASE_IDX 1 +#define regGFX_IMU_CORE_INT_STATUS 0x407f +#define regGFX_IMU_CORE_INT_STATUS_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_MASK 0x4080 +#define regGFX_IMU_PIC_INT_MASK_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_LVL 0x4081 +#define regGFX_IMU_PIC_INT_LVL_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_EDGE 0x4082 +#define regGFX_IMU_PIC_INT_EDGE_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_0 0x4083 +#define regGFX_IMU_PIC_INT_PRI_0_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_1 0x4084 +#define regGFX_IMU_PIC_INT_PRI_1_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_2 0x4085 +#define regGFX_IMU_PIC_INT_PRI_2_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_3 0x4086 +#define regGFX_IMU_PIC_INT_PRI_3_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_4 0x4087 +#define regGFX_IMU_PIC_INT_PRI_4_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_5 0x4088 +#define regGFX_IMU_PIC_INT_PRI_5_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_6 0x4089 +#define regGFX_IMU_PIC_INT_PRI_6_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_7 0x408a +#define regGFX_IMU_PIC_INT_PRI_7_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_STATUS 0x408b +#define regGFX_IMU_PIC_INT_STATUS_BASE_IDX 1 +#define regGFX_IMU_PIC_INTR 0x408c +#define regGFX_IMU_PIC_INTR_BASE_IDX 1 +#define regGFX_IMU_PIC_INTR_ID 0x408d +#define regGFX_IMU_PIC_INTR_ID_BASE_IDX 1 +#define regGFX_IMU_IH_CTRL_1 0x4090 +#define regGFX_IMU_IH_CTRL_1_BASE_IDX 1 +#define regGFX_IMU_IH_CTRL_2 0x4091 +#define regGFX_IMU_IH_CTRL_2_BASE_IDX 1 +#define regGFX_IMU_IH_CTRL_3 0x4092 +#define regGFX_IMU_IH_CTRL_3_BASE_IDX 1 +#define regGFX_IMU_IH_STATUS 0x4093 +#define regGFX_IMU_IH_STATUS_BASE_IDX 1 +#define regGFX_IMU_FUSESTRAP 0x4094 +#define regGFX_IMU_SMUIO_VIDCHG_CTRL 0x4098 +#define regGFX_IMU_SMUIO_VIDCHG_CTRL_BASE_IDX 1 +#define regGFX_IMU_GFXCLK_BYPASS_CTRL 0x409c +#define regGFX_IMU_GFXCLK_BYPASS_CTRL_BASE_IDX 1 +#define regGFX_IMU_CLK_CTRL 0x409d +#define regGFX_IMU_CLK_CTRL_BASE_IDX 1 +#define regGFX_IMU_DOORBELL_CONTROL 0x409e +#define regGFX_IMU_DOORBELL_CONTROL_BASE_IDX 1 +#define regGFX_IMU_RLC_CG_CTRL 0x40a0 +#define regGFX_IMU_RLC_CG_CTRL_BASE_IDX 1 +#define regGFX_IMU_RLC_THROTTLE_GFX 0x40a1 +#define regGFX_IMU_RLC_THROTTLE_GFX_BASE_IDX 1 +#define regGFX_IMU_RLC_RESET_VECTOR 0x40a2 +#define regGFX_IMU_RLC_RESET_VECTOR_BASE_IDX 1 +#define regGFX_IMU_RLC_OVERRIDE 0x40a3 +#define regGFX_IMU_RLC_OVERRIDE_BASE_IDX 1 +#define regGFX_IMU_DPM_CONTROL 0x40a8 +#define regGFX_IMU_DPM_CONTROL_BASE_IDX 1 +#define regGFX_IMU_DPM_ACC 0x40a9 +#define regGFX_IMU_DPM_ACC_BASE_IDX 1 +#define regGFX_IMU_DPM_REF_COUNTER 0x40aa +#define regGFX_IMU_DPM_REF_COUNTER_BASE_IDX 1 +#define regGFX_IMU_RLC_RAM_INDEX 0x40ac +#define regGFX_IMU_RLC_RAM_INDEX_BASE_IDX 1 +#define regGFX_IMU_RLC_RAM_ADDR_HIGH 0x40ad +#define regGFX_IMU_RLC_RAM_ADDR_HIGH_BASE_IDX 1 +#define regGFX_IMU_RLC_RAM_ADDR_LOW 0x40ae +#define regGFX_IMU_RLC_RAM_ADDR_LOW_BASE_IDX 1 +#define regGFX_IMU_RLC_RAM_DATA 0x40af +#define regGFX_IMU_RLC_RAM_DATA_BASE_IDX 1 +#define regGFX_IMU_FENCE_CTRL 0x40b0 +#define regGFX_IMU_FENCE_CTRL_BASE_IDX 1 +#define regGFX_IMU_FENCE_LOG_INIT 0x40b1 +#define regGFX_IMU_FENCE_LOG_INIT_BASE_IDX 1 +#define regGFX_IMU_FENCE_LOG_ADDR 0x40b2 +#define regGFX_IMU_FENCE_LOG_ADDR_BASE_IDX 1 +#define regGFX_IMU_PROGRAM_CTR 0x40b5 +#define regGFX_IMU_PROGRAM_CTR_BASE_IDX 1 +#define regGFX_IMU_CORE_CTRL 0x40b6 +#define regGFX_IMU_CORE_CTRL_BASE_IDX 1 +#define regGFX_IMU_CORE_STATUS 0x40b7 +#define regGFX_IMU_CORE_STATUS_BASE_IDX 1 +#define regGFX_IMU_PWROKRAW 0x40b8 +#define regGFX_IMU_PWROKRAW_BASE_IDX 1 +#define regGFX_IMU_PWROK 0x40b9 +#define regGFX_IMU_PWROK_BASE_IDX 1 +#define regGFX_IMU_GAP_PWROK 0x40ba +#define regGFX_IMU_GAP_PWROK_BASE_IDX 1 +#define regGFX_IMU_RESETn 0x40bb +#define regGFX_IMU_RESETn_BASE_IDX 1 +#define regGFX_IMU_GFX_RESET_CTRL 0x40bc +#define regGFX_IMU_GFX_RESET_CTRL_BASE_IDX 1 +#define regGFX_IMU_AEB_OVERRIDE 0x40bd +#define regGFX_IMU_AEB_OVERRIDE_BASE_IDX 1 +#define regGFX_IMU_VDCI_RESET_CTRL 0x40be +#define regGFX_IMU_VDCI_RESET_CTRL_BASE_IDX 1 +#define regGFX_IMU_GFX_ISO_CTRL 0x40bf +#define regGFX_IMU_GFX_ISO_CTRL_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CTRL0 0x40c0 +#define regGFX_IMU_TIMER0_CTRL0_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CTRL1 0x40c1 +#define regGFX_IMU_TIMER0_CTRL1_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CMP_AUTOINC 0x40c2 +#define regGFX_IMU_TIMER0_CMP_AUTOINC_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CMP_INTEN 0x40c3 +#define regGFX_IMU_TIMER0_CMP_INTEN_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CMP0 0x40c4 +#define regGFX_IMU_TIMER0_CMP0_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CMP1 0x40c5 +#define regGFX_IMU_TIMER0_CMP1_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CMP3 0x40c7 +#define regGFX_IMU_TIMER0_CMP3_BASE_IDX 1 +#define regGFX_IMU_TIMER0_VALUE 0x40c8 +#define regGFX_IMU_TIMER0_VALUE_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CTRL0 0x40c9 +#define regGFX_IMU_TIMER1_CTRL0_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CTRL1 0x40ca +#define regGFX_IMU_TIMER1_CTRL1_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CMP_AUTOINC 0x40cb +#define regGFX_IMU_TIMER1_CMP_AUTOINC_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CMP_INTEN 0x40cc +#define regGFX_IMU_TIMER1_CMP_INTEN_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CMP0 0x40cd +#define regGFX_IMU_TIMER1_CMP0_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CMP1 0x40ce +#define regGFX_IMU_TIMER1_CMP1_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CMP3 0x40d0 +#define regGFX_IMU_TIMER1_CMP3_BASE_IDX 1 +#define regGFX_IMU_TIMER1_VALUE 0x40d1 +#define regGFX_IMU_TIMER1_VALUE_BASE_IDX 1 +#define regGFX_IMU_TIMER2_CTRL0 0x40d2 +#define regGFX_IMU_TIMER2_CTRL0_BASE_IDX 1 +#define regGFX_IMU_TIMER2_CTRL1 0x40d3 +#define regGFX_IMU_TIMER2_CTRL1_BASE_IDX 1 +#define regGFX_IMU_TIMER2_CMP_AUTOINC 0x40d4 +#define regGFX_IMU_TIMER2_CMP_AUTOINC_BASE_IDX 1 +#define regGFX_IMU_TIMER2_CMP_INTEN 0x40d5 +#define regGFX_IMU_TIMER2_CMP_INTEN_BASE_IDX 1 +#define regGFX_IMU_TIMER2_CMP0 0x40d6 +#define regGFX_IMU_TIMER2_CMP0_BASE_IDX 1 +#define regGFX_IMU_TIMER2_CMP1 0x40d7 +#define regGFX_IMU_TIMER2_CMP1_BASE_IDX 1 +#define regGFX_IMU_TIMER2_CMP3 0x40d9 +#define regGFX_IMU_TIMER2_CMP3_BASE_IDX 1 +#define regGFX_IMU_TIMER2_VALUE 0x40da +#define regGFX_IMU_TIMER2_VALUE_BASE_IDX 1 +#define regGFX_IMU_FUSE_CTRL 0x40e0 +#define regGFX_IMU_FUSE_CTRL_BASE_IDX 1 +#define regGFX_IMU_D_RAM_ADDR 0x40fc +#define regGFX_IMU_D_RAM_ADDR_BASE_IDX 1 +#define regGFX_IMU_D_RAM_DATA 0x40fd +#define regGFX_IMU_D_RAM_DATA_BASE_IDX 1 +#define regGFX_IMU_GFX_IH_GASKET_CTRL 0x40ff +#define regGFX_IMU_GFX_IH_GASKET_CTRL_BASE_IDX 1 + + +// addressBlock: gc_gfx_imu_gfx_imu_pspdec +// base address: 0x3fe00 +#define regGFX_IMU_RLC_BOOTLOADER_ADDR_HI 0x5f81 +#define regGFX_IMU_RLC_BOOTLOADER_ADDR_HI_BASE_IDX 1 +#define regGFX_IMU_RLC_BOOTLOADER_ADDR_LO 0x5f82 +#define regGFX_IMU_RLC_BOOTLOADER_ADDR_LO_BASE_IDX 1 +#define regGFX_IMU_RLC_BOOTLOADER_SIZE 0x5f83 +#define regGFX_IMU_RLC_BOOTLOADER_SIZE_BASE_IDX 1 +#define regGFX_IMU_I_RAM_ADDR 0x5f90 +#define regGFX_IMU_I_RAM_ADDR_BASE_IDX 1 +#define regGFX_IMU_I_RAM_DATA 0x5f91 +#define regGFX_IMU_I_RAM_DATA_BASE_IDX 1 + + +// addressBlock: gccacind +// base address: 0x0 +#define ixGC_CAC_ID 0x0000 +#define ixGC_CAC_CNTL 0x0001 +#define ixGC_CAC_ACC_CP0 0x0010 +#define ixGC_CAC_ACC_CP1 0x0011 +#define ixGC_CAC_ACC_CP2 0x0012 +#define ixGC_CAC_ACC_EA0 0x0013 +#define ixGC_CAC_ACC_EA1 0x0014 +#define ixGC_CAC_ACC_EA2 0x0015 +#define ixGC_CAC_ACC_EA3 0x0016 +#define ixGC_CAC_ACC_EA4 0x0017 +#define ixGC_CAC_ACC_EA5 0x0018 +#define ixGC_CAC_ACC_UTCL2_ROUTER0 0x0019 +#define ixGC_CAC_ACC_UTCL2_ROUTER1 0x001a +#define ixGC_CAC_ACC_UTCL2_ROUTER2 0x001b +#define ixGC_CAC_ACC_UTCL2_ROUTER3 0x001c +#define ixGC_CAC_ACC_UTCL2_ROUTER4 0x001d +#define ixGC_CAC_ACC_UTCL2_ROUTER5 0x001e +#define ixGC_CAC_ACC_UTCL2_ROUTER6 0x001f +#define ixGC_CAC_ACC_UTCL2_ROUTER7 0x0020 +#define ixGC_CAC_ACC_UTCL2_ROUTER8 0x0021 +#define ixGC_CAC_ACC_UTCL2_ROUTER9 0x0022 +#define ixGC_CAC_ACC_UTCL2_VML20 0x0023 +#define ixGC_CAC_ACC_UTCL2_VML21 0x0024 +#define ixGC_CAC_ACC_UTCL2_VML22 0x0025 +#define ixGC_CAC_ACC_UTCL2_VML23 0x0026 +#define ixGC_CAC_ACC_UTCL2_VML24 0x0027 +#define ixGC_CAC_ACC_UTCL2_WALKER0 0x0028 +#define ixGC_CAC_ACC_UTCL2_WALKER1 0x0029 +#define ixGC_CAC_ACC_UTCL2_WALKER2 0x002a +#define ixGC_CAC_ACC_UTCL2_WALKER3 0x002b +#define ixGC_CAC_ACC_UTCL2_WALKER4 0x002c +#define ixGC_CAC_ACC_GDS0 0x002d +#define ixGC_CAC_ACC_GDS1 0x002e +#define ixGC_CAC_ACC_GDS2 0x002f +#define ixGC_CAC_ACC_GDS3 0x0030 +#define ixGC_CAC_ACC_GDS4 0x0031 +#define ixGC_CAC_ACC_GE0 0x0032 +#define ixGC_CAC_ACC_GE1 0x0033 +#define ixGC_CAC_ACC_GE2 0x0034 +#define ixGC_CAC_ACC_GE3 0x0035 +#define ixGC_CAC_ACC_GE4 0x0036 +#define ixGC_CAC_ACC_GE5 0x0037 +#define ixGC_CAC_ACC_GE6 0x0038 +#define ixGC_CAC_ACC_GE7 0x0039 +#define ixGC_CAC_ACC_GE8 0x003a +#define ixGC_CAC_ACC_GE9 0x003b +#define ixGC_CAC_ACC_GE10 0x003c +#define ixGC_CAC_ACC_GE11 0x003d +#define ixGC_CAC_ACC_GE12 0x003e +#define ixGC_CAC_ACC_GE13 0x003f +#define ixGC_CAC_ACC_GE14 0x0040 +#define ixGC_CAC_ACC_GE15 0x0041 +#define ixGC_CAC_ACC_GE16 0x0042 +#define ixGC_CAC_ACC_GE17 0x0043 +#define ixGC_CAC_ACC_GE18 0x0044 +#define ixGC_CAC_ACC_GE19 0x0045 +#define ixGC_CAC_ACC_GE20 0x0046 +#define ixGC_CAC_ACC_PMM0 0x0047 +#define ixGC_CAC_ACC_GL2C0 0x0048 +#define ixGC_CAC_ACC_GL2C1 0x0049 +#define ixGC_CAC_ACC_GL2C2 0x004a +#define ixGC_CAC_ACC_GL2C3 0x004b +#define ixGC_CAC_ACC_GL2C4 0x004c +#define ixGC_CAC_ACC_PH0 0x004d +#define ixGC_CAC_ACC_PH1 0x004e +#define ixGC_CAC_ACC_PH2 0x004f +#define ixGC_CAC_ACC_PH3 0x0050 +#define ixGC_CAC_ACC_PH4 0x0051 +#define ixGC_CAC_ACC_PH5 0x0052 +#define ixGC_CAC_ACC_PH6 0x0053 +#define ixGC_CAC_ACC_PH7 0x0054 +#define ixGC_CAC_ACC_SDMA0 0x0055 +#define ixGC_CAC_ACC_SDMA1 0x0056 +#define ixGC_CAC_ACC_SDMA2 0x0057 +#define ixGC_CAC_ACC_SDMA3 0x0058 +#define ixGC_CAC_ACC_SDMA4 0x0059 +#define ixGC_CAC_ACC_SDMA5 0x005a +#define ixGC_CAC_ACC_SDMA6 0x005b +#define ixGC_CAC_ACC_SDMA7 0x005c +#define ixGC_CAC_ACC_SDMA8 0x005d +#define ixGC_CAC_ACC_SDMA9 0x005e +#define ixGC_CAC_ACC_SDMA10 0x005f +#define ixGC_CAC_ACC_SDMA11 0x0060 +#define ixGC_CAC_ACC_CHC0 0x0061 +#define ixGC_CAC_ACC_CHC1 0x0062 +#define ixGC_CAC_ACC_CHC2 0x0063 +#define ixGC_CAC_ACC_GUS0 0x0064 +#define ixGC_CAC_ACC_GUS1 0x0065 +#define ixGC_CAC_ACC_GUS2 0x0066 +#define ixGC_CAC_ACC_RLC0 0x0067 +#define ixRELEASE_TO_STALL_LUT_1_8 0x0100 +#define ixRELEASE_TO_STALL_LUT_9_16 0x0101 +#define ixRELEASE_TO_STALL_LUT_17_20 0x0102 +#define ixSTALL_TO_RELEASE_LUT_1_4 0x0103 +#define ixSTALL_TO_RELEASE_LUT_5_7 0x0104 +#define ixSTALL_TO_PWRBRK_LUT_1_4 0x0105 +#define ixSTALL_TO_PWRBRK_LUT_5_7 0x0106 +#define ixPWRBRK_STALL_TO_RELEASE_LUT_1_4 0x0107 +#define ixPWRBRK_STALL_TO_RELEASE_LUT_5_7 0x0108 +#define ixPWRBRK_RELEASE_TO_STALL_LUT_1_8 0x0109 +#define ixPWRBRK_RELEASE_TO_STALL_LUT_9_16 0x010a +#define ixPWRBRK_RELEASE_TO_STALL_LUT_17_20 0x010b +#define ixFIXED_PATTERN_PERF_COUNTER_1 0x010c +#define ixFIXED_PATTERN_PERF_COUNTER_2 0x010d +#define ixFIXED_PATTERN_PERF_COUNTER_3 0x010e +#define ixFIXED_PATTERN_PERF_COUNTER_4 0x010f +#define ixFIXED_PATTERN_PERF_COUNTER_5 0x0110 +#define ixFIXED_PATTERN_PERF_COUNTER_6 0x0111 +#define ixFIXED_PATTERN_PERF_COUNTER_7 0x0112 +#define ixFIXED_PATTERN_PERF_COUNTER_8 0x0113 +#define ixFIXED_PATTERN_PERF_COUNTER_9 0x0114 +#define ixFIXED_PATTERN_PERF_COUNTER_10 0x0115 +#define ixHW_LUT_UPDATE_STATUS 0x0116 + + +// addressBlock: secacind +// base address: 0x0 +#define ixSE_CAC_ID 0x0000 +#define ixSE_CAC_CNTL 0x0001 + + +// addressBlock: grtavfsind +// base address: 0x0 +#define ixRTAVFS_REG0 0x0000 +#define ixRTAVFS_REG1 0x0001 +#define ixRTAVFS_REG2 0x0002 +#define ixRTAVFS_REG3 0x0003 +#define ixRTAVFS_REG4 0x0004 +#define ixRTAVFS_REG5 0x0005 +#define ixRTAVFS_REG6 0x0006 +#define ixRTAVFS_REG7 0x0007 +#define ixRTAVFS_REG8 0x0008 +#define ixRTAVFS_REG9 0x0009 +#define ixRTAVFS_REG10 0x000a +#define ixRTAVFS_REG11 0x000b +#define ixRTAVFS_REG12 0x000c +#define ixRTAVFS_REG13 0x000d +#define ixRTAVFS_REG14 0x000e +#define ixRTAVFS_REG15 0x000f +#define ixRTAVFS_REG16 0x0010 +#define ixRTAVFS_REG17 0x0011 +#define ixRTAVFS_REG18 0x0012 +#define ixRTAVFS_REG19 0x0013 +#define ixRTAVFS_REG20 0x0014 +#define ixRTAVFS_REG21 0x0015 +#define ixRTAVFS_REG22 0x0016 +#define ixRTAVFS_REG23 0x0017 +#define ixRTAVFS_REG24 0x0018 +#define ixRTAVFS_REG25 0x0019 +#define ixRTAVFS_REG26 0x001a +#define ixRTAVFS_REG27 0x001b +#define ixRTAVFS_REG28 0x001c +#define ixRTAVFS_REG29 0x001d +#define ixRTAVFS_REG30 0x001e +#define ixRTAVFS_REG31 0x001f +#define ixRTAVFS_REG32 0x0020 +#define ixRTAVFS_REG33 0x0021 +#define ixRTAVFS_REG34 0x0022 +#define ixRTAVFS_REG35 0x0023 +#define ixRTAVFS_REG36 0x0024 +#define ixRTAVFS_REG37 0x0025 +#define ixRTAVFS_REG38 0x0026 +#define ixRTAVFS_REG39 0x0027 +#define ixRTAVFS_REG40 0x0028 +#define ixRTAVFS_REG41 0x0029 +#define ixRTAVFS_REG42 0x002a +#define ixRTAVFS_REG43 0x002b +#define ixRTAVFS_REG44 0x002c +#define ixRTAVFS_REG45 0x002d +#define ixRTAVFS_REG46 0x002e +#define ixRTAVFS_REG47 0x002f +#define ixRTAVFS_REG48 0x0030 +#define ixRTAVFS_REG49 0x0031 +#define ixRTAVFS_REG50 0x0032 +#define ixRTAVFS_REG51 0x0033 +#define ixRTAVFS_REG52 0x0034 +#define ixRTAVFS_REG53 0x0035 +#define ixRTAVFS_REG54 0x0036 +#define ixRTAVFS_REG55 0x0037 +#define ixRTAVFS_REG56 0x0038 +#define ixRTAVFS_REG57 0x0039 +#define ixRTAVFS_REG58 0x003a +#define ixRTAVFS_REG59 0x003b +#define ixRTAVFS_REG60 0x003c +#define ixRTAVFS_REG61 0x003d +#define ixRTAVFS_REG62 0x003e +#define ixRTAVFS_REG63 0x003f +#define ixRTAVFS_REG64 0x0040 +#define ixRTAVFS_REG65 0x0041 +#define ixRTAVFS_REG66 0x0042 +#define ixRTAVFS_REG67 0x0043 +#define ixRTAVFS_REG68 0x0044 +#define ixRTAVFS_REG69 0x0045 +#define ixRTAVFS_REG70 0x0046 +#define ixRTAVFS_REG71 0x0047 +#define ixRTAVFS_REG72 0x0048 +#define ixRTAVFS_REG73 0x0049 +#define ixRTAVFS_REG74 0x004a +#define ixRTAVFS_REG75 0x004b +#define ixRTAVFS_REG76 0x004c +#define ixRTAVFS_REG77 0x004d +#define ixRTAVFS_REG78 0x004e +#define ixRTAVFS_REG79 0x004f +#define ixRTAVFS_REG80 0x0050 +#define ixRTAVFS_REG81 0x0051 +#define ixRTAVFS_REG82 0x0052 +#define ixRTAVFS_REG83 0x0053 +#define ixRTAVFS_REG84 0x0054 +#define ixRTAVFS_REG85 0x0055 +#define ixRTAVFS_REG86 0x0056 +#define ixRTAVFS_REG87 0x0057 +#define ixRTAVFS_REG88 0x0058 +#define ixRTAVFS_REG89 0x0059 +#define ixRTAVFS_REG90 0x005a +#define ixRTAVFS_REG91 0x005b +#define ixRTAVFS_REG92 0x005c +#define ixRTAVFS_REG93 0x005d +#define ixRTAVFS_REG94 0x005e +#define ixRTAVFS_REG95 0x005f +#define ixRTAVFS_REG96 0x0060 +#define ixRTAVFS_REG97 0x0061 +#define ixRTAVFS_REG98 0x0062 +#define ixRTAVFS_REG99 0x0063 +#define ixRTAVFS_REG100 0x0064 +#define ixRTAVFS_REG101 0x0065 +#define ixRTAVFS_REG102 0x0066 +#define ixRTAVFS_REG103 0x0067 +#define ixRTAVFS_REG104 0x0068 +#define ixRTAVFS_REG105 0x0069 +#define ixRTAVFS_REG106 0x006a +#define ixRTAVFS_REG107 0x006b +#define ixRTAVFS_REG108 0x006c +#define ixRTAVFS_REG109 0x006d +#define ixRTAVFS_REG110 0x006e +#define ixRTAVFS_REG111 0x006f +#define ixRTAVFS_REG112 0x0070 +#define ixRTAVFS_REG113 0x0071 +#define ixRTAVFS_REG114 0x0072 +#define ixRTAVFS_REG115 0x0073 +#define ixRTAVFS_REG116 0x0074 +#define ixRTAVFS_REG117 0x0075 +#define ixRTAVFS_REG118 0x0076 +#define ixRTAVFS_REG119 0x0077 +#define ixRTAVFS_REG120 0x0078 +#define ixRTAVFS_REG121 0x0079 +#define ixRTAVFS_REG122 0x007a +#define ixRTAVFS_REG123 0x007b +#define ixRTAVFS_REG124 0x007c +#define ixRTAVFS_REG125 0x007d +#define ixRTAVFS_REG126 0x007e +#define ixRTAVFS_REG127 0x007f +#define ixRTAVFS_REG128 0x0080 +#define ixRTAVFS_REG129 0x0081 +#define ixRTAVFS_REG130 0x0082 +#define ixRTAVFS_REG131 0x0083 +#define ixRTAVFS_REG132 0x0084 +#define ixRTAVFS_REG133 0x0085 +#define ixRTAVFS_REG134 0x0086 +#define ixRTAVFS_REG135 0x0087 +#define ixRTAVFS_REG136 0x0088 +#define ixRTAVFS_REG137 0x0089 +#define ixRTAVFS_REG138 0x008a +#define ixRTAVFS_REG139 0x008b +#define ixRTAVFS_REG140 0x008c +#define ixRTAVFS_REG141 0x008d +#define ixRTAVFS_REG142 0x008e +#define ixRTAVFS_REG143 0x008f +#define ixRTAVFS_REG144 0x0090 +#define ixRTAVFS_REG145 0x0091 +#define ixRTAVFS_REG146 0x0092 +#define ixRTAVFS_REG147 0x0093 +#define ixRTAVFS_REG148 0x0094 +#define ixRTAVFS_REG149 0x0095 +#define ixRTAVFS_REG150 0x0096 +#define ixRTAVFS_REG151 0x0097 +#define ixRTAVFS_REG152 0x0098 +#define ixRTAVFS_REG153 0x0099 +#define ixRTAVFS_REG154 0x009a +#define ixRTAVFS_REG155 0x009b +#define ixRTAVFS_REG156 0x009c +#define ixRTAVFS_REG157 0x009d +#define ixRTAVFS_REG158 0x009e +#define ixRTAVFS_REG159 0x009f +#define ixRTAVFS_REG160 0x00a0 +#define ixRTAVFS_REG161 0x00a1 +#define ixRTAVFS_REG162 0x00a2 +#define ixRTAVFS_REG163 0x00a3 +#define ixRTAVFS_REG164 0x00a4 +#define ixRTAVFS_REG165 0x00a5 +#define ixRTAVFS_REG166 0x00a6 +#define ixRTAVFS_REG167 0x00a7 +#define ixRTAVFS_REG168 0x00a8 +#define ixRTAVFS_REG169 0x00a9 +#define ixRTAVFS_REG170 0x00aa +#define ixRTAVFS_REG171 0x00ab +#define ixRTAVFS_REG172 0x00ac +#define ixRTAVFS_REG173 0x00ad +#define ixRTAVFS_REG174 0x00ae +#define ixRTAVFS_REG175 0x00af +#define ixRTAVFS_REG176 0x00b0 +#define ixRTAVFS_REG177 0x00b1 +#define ixRTAVFS_REG178 0x00b2 +#define ixRTAVFS_REG179 0x00b3 +#define ixRTAVFS_REG180 0x00b4 +#define ixRTAVFS_REG181 0x00b5 +#define ixRTAVFS_REG182 0x00b6 +#define ixRTAVFS_REG183 0x00b7 +#define ixRTAVFS_REG184 0x00b8 +#define ixRTAVFS_REG185 0x00b9 +#define ixRTAVFS_REG186 0x00ba +#define ixRTAVFS_REG187 0x00bb +#define ixRTAVFS_REG188 0x00bc +#define ixRTAVFS_REG189 0x00bd +#define ixRTAVFS_REG190 0x00be +#define ixRTAVFS_REG191 0x00bf +#define ixRTAVFS_REG192 0x00c0 +#define ixRTAVFS_REG193 0x00c1 +#define ixRTAVFS_REG194 0x00c2 + + +// addressBlock: sqind +// base address: 0x0 +#define ixSQ_DEBUG_STS_LOCAL 0x0008 +#define ixSQ_DEBUG_CTRL_LOCAL 0x0009 +#define ixSQ_WAVE_ACTIVE 0x000a +#define ixSQ_WAVE_VALID_AND_IDLE 0x000b +#define ixSQ_WAVE_MODE 0x0101 +#define ixSQ_WAVE_STATUS 0x0102 +#define ixSQ_WAVE_TRAPSTS 0x0103 +#define ixSQ_WAVE_GPR_ALLOC 0x0105 +#define ixSQ_WAVE_LDS_ALLOC 0x0106 +#define ixSQ_WAVE_IB_STS 0x0107 +#define ixSQ_WAVE_PC_LO 0x0108 +#define ixSQ_WAVE_PC_HI 0x0109 +#define ixSQ_WAVE_IB_DBG1 0x010d +#define ixSQ_WAVE_FLUSH_IB 0x010e +#define ixSQ_WAVE_FLAT_SCRATCH_LO 0x0114 +#define ixSQ_WAVE_FLAT_SCRATCH_HI 0x0115 +#define ixSQ_WAVE_HW_ID1 0x0117 +#define ixSQ_WAVE_HW_ID2 0x0118 +#define ixSQ_WAVE_POPS_PACKER 0x0119 +#define ixSQ_WAVE_SCHED_MODE 0x011a +#define ixSQ_WAVE_IB_STS2 0x011c +#define ixSQ_WAVE_SHADER_CYCLES 0x011d +#define ixSQ_WAVE_TTMP0 0x026c +#define ixSQ_WAVE_TTMP1 0x026d +#define ixSQ_WAVE_TTMP3 0x026f +#define ixSQ_WAVE_TTMP4 0x0270 +#define ixSQ_WAVE_TTMP5 0x0271 +#define ixSQ_WAVE_TTMP6 0x0272 +#define ixSQ_WAVE_TTMP7 0x0273 +#define ixSQ_WAVE_TTMP8 0x0274 +#define ixSQ_WAVE_TTMP9 0x0275 +#define ixSQ_WAVE_TTMP10 0x0276 +#define ixSQ_WAVE_TTMP11 0x0277 +#define ixSQ_WAVE_TTMP12 0x0278 +#define ixSQ_WAVE_TTMP13 0x0279 +#define ixSQ_WAVE_TTMP14 0x027a +#define ixSQ_WAVE_TTMP15 0x027b +#define ixSQ_WAVE_M0 0x027d +#define ixSQ_WAVE_EXEC_LO 0x027e +#define ixSQ_WAVE_EXEC_HI 0x027f + + +#endif |