diff options
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB')
3 files changed, 0 insertions, 13105 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_default.h deleted file mode 100644 index 02989fe9f7bd..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_default.h +++ /dev/null @@ -1,1011 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _mmhub_1_0_DEFAULT_HEADER -#define _mmhub_1_0_DEFAULT_HEADER - - -// addressBlock: mmhub_dagbdec -#define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI10_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI11_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI12_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI13_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI14_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI15_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RD_CNTL_DEFAULT 0x03527df8 -#define mmDAGB0_RD_GMI_CNTL_DEFAULT 0x0000304f -#define mmDAGB0_RD_ADDR_DAGB_DEFAULT 0x00000039 -#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 -#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 -#define mmDAGB0_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 -#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 -#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 -#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 -#define mmDAGB0_RD_VC0_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_VC1_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_VC2_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_VC3_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_VC4_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_VC5_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_VC6_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_VC7_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_CNTL_MISC_DEFAULT 0x01a10408 -#define mmDAGB0_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 -#define mmDAGB0_RDCLI_ASK_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_RDCLI_GO_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_RDCLI_TLB_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_RDCLI_OARB_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_RDCLI_OSD_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI0_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI1_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI2_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI3_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI4_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI5_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI6_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI7_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI8_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI9_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI10_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI11_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI12_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI13_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI14_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI15_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WR_CNTL_DEFAULT 0x03527df8 -#define mmDAGB0_WR_GMI_CNTL_DEFAULT 0x0000304f -#define mmDAGB0_WR_ADDR_DAGB_DEFAULT 0x00000039 -#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 -#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 -#define mmDAGB0_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 -#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 -#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 -#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 -#define mmDAGB0_WR_DATA_DAGB_DEFAULT 0x00000001 -#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 -#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 -#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 -#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 -#define mmDAGB0_WR_VC0_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_VC1_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_VC2_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_VC3_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_VC4_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_VC5_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_VC6_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_VC7_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_CNTL_MISC_DEFAULT 0x01a10408 -#define mmDAGB0_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 -#define mmDAGB0_WR_DATA_CREDIT_DEFAULT 0x5c626870 -#define mmDAGB0_WR_MISC_CREDIT_DEFAULT 0x0078dc88 -#define mmDAGB0_WRCLI_ASK_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI_GO_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI_TLB_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI_OARB_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI_OSD_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_DAGB_DLY_DEFAULT 0x00000000 -#define mmDAGB0_CNTL_MISC_DEFAULT 0xcf7c1ffa -#define mmDAGB0_CNTL_MISC2_DEFAULT 0x00000000 -#define mmDAGB0_FIFO_EMPTY_DEFAULT 0x00ffffff -#define mmDAGB0_FIFO_FULL_DEFAULT 0x00000000 -#define mmDAGB0_WR_CREDITS_FULL_DEFAULT 0x0007ffff -#define mmDAGB0_RD_CREDITS_FULL_DEFAULT 0x0003ffff -#define mmDAGB0_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmDAGB0_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmDAGB0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmDAGB0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmDAGB0_PERFCOUNTER2_CFG_DEFAULT 0x00000000 -#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 -#define mmDAGB0_RESERVE0_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE1_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE2_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE3_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE4_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE5_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE6_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE7_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE8_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE9_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE10_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE11_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE12_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE13_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE14_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE15_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE16_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE17_DEFAULT 0x00000000 -#define mmDAGB1_RDCLI0_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_RDCLI1_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_RDCLI2_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_RDCLI3_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_RDCLI4_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_RDCLI5_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_RDCLI6_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_RDCLI7_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_RDCLI8_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_RDCLI9_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_RDCLI10_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_RDCLI11_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_RDCLI12_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_RDCLI13_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_RDCLI14_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_RDCLI15_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_RD_CNTL_DEFAULT 0x03527df8 -#define mmDAGB1_RD_GMI_CNTL_DEFAULT 0x0000304f -#define mmDAGB1_RD_ADDR_DAGB_DEFAULT 0x00000039 -#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 -#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 -#define mmDAGB1_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 -#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 -#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 -#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 -#define mmDAGB1_RD_VC0_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB1_RD_VC1_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB1_RD_VC2_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB1_RD_VC3_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB1_RD_VC4_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB1_RD_VC5_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB1_RD_VC6_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB1_RD_VC7_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB1_RD_CNTL_MISC_DEFAULT 0x01a10408 -#define mmDAGB1_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 -#define mmDAGB1_RDCLI_ASK_PENDING_DEFAULT 0x00000000 -#define mmDAGB1_RDCLI_GO_PENDING_DEFAULT 0x00000000 -#define mmDAGB1_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 -#define mmDAGB1_RDCLI_TLB_PENDING_DEFAULT 0x00000000 -#define mmDAGB1_RDCLI_OARB_PENDING_DEFAULT 0x00000000 -#define mmDAGB1_RDCLI_OSD_PENDING_DEFAULT 0x00000000 -#define mmDAGB1_WRCLI0_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_WRCLI1_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_WRCLI2_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_WRCLI3_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_WRCLI4_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_WRCLI5_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_WRCLI6_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_WRCLI7_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_WRCLI8_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_WRCLI9_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_WRCLI10_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_WRCLI11_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_WRCLI12_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_WRCLI13_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_WRCLI14_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_WRCLI15_DEFAULT 0xfe5fe0f9 -#define mmDAGB1_WR_CNTL_DEFAULT 0x03527df8 -#define mmDAGB1_WR_GMI_CNTL_DEFAULT 0x0000304f -#define mmDAGB1_WR_ADDR_DAGB_DEFAULT 0x00000039 -#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 -#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 -#define mmDAGB1_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 -#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 -#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 -#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 -#define mmDAGB1_WR_DATA_DAGB_DEFAULT 0x00000001 -#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 -#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 -#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 -#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 -#define mmDAGB1_WR_VC0_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB1_WR_VC1_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB1_WR_VC2_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB1_WR_VC3_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB1_WR_VC4_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB1_WR_VC5_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB1_WR_VC6_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB1_WR_VC7_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB1_WR_CNTL_MISC_DEFAULT 0x01a10408 -#define mmDAGB1_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 -#define mmDAGB1_WR_DATA_CREDIT_DEFAULT 0x5c626870 -#define mmDAGB1_WR_MISC_CREDIT_DEFAULT 0x0078dc88 -#define mmDAGB1_WRCLI_ASK_PENDING_DEFAULT 0x00000000 -#define mmDAGB1_WRCLI_GO_PENDING_DEFAULT 0x00000000 -#define mmDAGB1_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 -#define mmDAGB1_WRCLI_TLB_PENDING_DEFAULT 0x00000000 -#define mmDAGB1_WRCLI_OARB_PENDING_DEFAULT 0x00000000 -#define mmDAGB1_WRCLI_OSD_PENDING_DEFAULT 0x00000000 -#define mmDAGB1_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 -#define mmDAGB1_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 -#define mmDAGB1_DAGB_DLY_DEFAULT 0x00000000 -#define mmDAGB1_CNTL_MISC_DEFAULT 0xcf7c1ffa -#define mmDAGB1_CNTL_MISC2_DEFAULT 0x00000000 -#define mmDAGB1_FIFO_EMPTY_DEFAULT 0x00ffffff -#define mmDAGB1_FIFO_FULL_DEFAULT 0x00000000 -#define mmDAGB1_WR_CREDITS_FULL_DEFAULT 0x0007ffff -#define mmDAGB1_RD_CREDITS_FULL_DEFAULT 0x0003ffff -#define mmDAGB1_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmDAGB1_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmDAGB1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmDAGB1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmDAGB1_PERFCOUNTER2_CFG_DEFAULT 0x00000000 -#define mmDAGB1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 -#define mmDAGB1_RESERVE0_DEFAULT 0x00000000 -#define mmDAGB1_RESERVE1_DEFAULT 0x00000000 -#define mmDAGB1_RESERVE2_DEFAULT 0x00000000 -#define mmDAGB1_RESERVE3_DEFAULT 0x00000000 -#define mmDAGB1_RESERVE4_DEFAULT 0x00000000 -#define mmDAGB1_RESERVE5_DEFAULT 0x00000000 -#define mmDAGB1_RESERVE6_DEFAULT 0x00000000 -#define mmDAGB1_RESERVE7_DEFAULT 0x00000000 -#define mmDAGB1_RESERVE8_DEFAULT 0x00000000 -#define mmDAGB1_RESERVE9_DEFAULT 0x00000000 -#define mmDAGB1_RESERVE10_DEFAULT 0x00000000 -#define mmDAGB1_RESERVE11_DEFAULT 0x00000000 -#define mmDAGB1_RESERVE12_DEFAULT 0x00000000 -#define mmDAGB1_RESERVE13_DEFAULT 0x00000000 -#define mmDAGB1_RESERVE14_DEFAULT 0x00000000 -#define mmDAGB1_RESERVE15_DEFAULT 0x00000000 -#define mmDAGB1_RESERVE16_DEFAULT 0x00000000 -#define mmDAGB1_RESERVE17_DEFAULT 0x00000000 - - -// addressBlock: mmhub_ea_mmeadec -#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 -#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 -#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 -#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 -#define mmMMEA0_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 -#define mmMMEA0_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 -#define mmMMEA0_DRAM_RD_LAZY_DEFAULT 0x00000924 -#define mmMMEA0_DRAM_WR_LAZY_DEFAULT 0x00000924 -#define mmMMEA0_DRAM_RD_CAM_CNTL_DEFAULT 0x06db3333 -#define mmMMEA0_DRAM_WR_CAM_CNTL_DEFAULT 0x06db3333 -#define mmMMEA0_DRAM_PAGE_BURST_DEFAULT 0x20002000 -#define mmMMEA0_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA0_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA0_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA0_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA0_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA0_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA0_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 -#define mmMMEA0_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 -#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA0_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRNORM_HOLE_CNTL_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef -#define mmMMEA0_ADDRDEC_MISC_CFG_DEFAULT 0x3ffff000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 -#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 -#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 -#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 -#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 -#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 -#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 -#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 -#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 -#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 -#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 -#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 -#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 -#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 -#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 -#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 -#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 -#define mmMMEA0_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 -#define mmMMEA0_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 -#define mmMMEA0_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 -#define mmMMEA0_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 -#define mmMMEA0_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 -#define mmMMEA0_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 -#define mmMMEA0_IO_GROUP_BURST_DEFAULT 0x1f031f03 -#define mmMMEA0_IO_RD_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA0_IO_WR_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA0_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA0_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA0_IO_RD_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA0_IO_WR_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA0_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 -#define mmMMEA0_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 -#define mmMMEA0_IO_RD_PRI_URGENCY_MASK_DEFAULT 0xffffffff -#define mmMMEA0_IO_WR_PRI_URGENCY_MASK_DEFAULT 0xffffffff -#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA0_SDP_ARB_DRAM_DEFAULT 0x00102040 -#define mmMMEA0_SDP_ARB_FINAL_DEFAULT 0x00007fff -#define mmMMEA0_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 -#define mmMMEA0_SDP_IO_PRIORITY_DEFAULT 0x00000000 -#define mmMMEA0_SDP_CREDITS_DEFAULT 0x000100bf -#define mmMMEA0_SDP_TAG_RESERVE0_DEFAULT 0x00000000 -#define mmMMEA0_SDP_TAG_RESERVE1_DEFAULT 0x00000000 -#define mmMMEA0_SDP_VCC_RESERVE0_DEFAULT 0x00000000 -#define mmMMEA0_SDP_VCC_RESERVE1_DEFAULT 0x00000000 -#define mmMMEA0_SDP_VCD_RESERVE0_DEFAULT 0x00000000 -#define mmMMEA0_SDP_VCD_RESERVE1_DEFAULT 0x00000000 -#define mmMMEA0_SDP_REQ_CNTL_DEFAULT 0x0000000f -#define mmMMEA0_MISC_DEFAULT 0x00180130 -#define mmMMEA0_LATENCY_SAMPLING_DEFAULT 0x00000000 -#define mmMMEA0_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmMMEA0_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmMMEA0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmMMEA0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 -#define mmMMEA0_EDC_CNT_DEFAULT 0x00000000 -#define mmMMEA0_EDC_CNT2_DEFAULT 0x00000000 -#define mmMMEA0_DSM_CNTL_DEFAULT 0x00000000 -#define mmMMEA0_DSM_CNTLA_DEFAULT 0x00000000 -#define mmMMEA0_DSM_CNTLB_DEFAULT 0x00000000 -#define mmMMEA0_DSM_CNTL2_DEFAULT 0x00000000 -#define mmMMEA0_DSM_CNTL2A_DEFAULT 0x00000000 -#define mmMMEA0_DSM_CNTL2B_DEFAULT 0x00000000 -#define mmMMEA0_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmMMEA0_EDC_MODE_DEFAULT 0x00000000 -#define mmMMEA0_ERR_STATUS_DEFAULT 0x00000000 -#define mmMMEA0_MISC2_DEFAULT 0x00000000 -#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 -#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 -#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 -#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 -#define mmMMEA1_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 -#define mmMMEA1_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 -#define mmMMEA1_DRAM_RD_LAZY_DEFAULT 0x00000924 -#define mmMMEA1_DRAM_WR_LAZY_DEFAULT 0x00000924 -#define mmMMEA1_DRAM_RD_CAM_CNTL_DEFAULT 0x06db3333 -#define mmMMEA1_DRAM_WR_CAM_CNTL_DEFAULT 0x06db3333 -#define mmMMEA1_DRAM_PAGE_BURST_DEFAULT 0x20002000 -#define mmMMEA1_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA1_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA1_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA1_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA1_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA1_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA1_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 -#define mmMMEA1_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 -#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA1_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRNORM_HOLE_CNTL_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef -#define mmMMEA1_ADDRDEC_MISC_CFG_DEFAULT 0x3ffff000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 -#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 -#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 -#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 -#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 -#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 -#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 -#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 -#define mmMMEA1_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 -#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 -#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 -#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 -#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 -#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 -#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 -#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 -#define mmMMEA1_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 -#define mmMMEA1_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 -#define mmMMEA1_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 -#define mmMMEA1_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 -#define mmMMEA1_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 -#define mmMMEA1_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 -#define mmMMEA1_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 -#define mmMMEA1_IO_GROUP_BURST_DEFAULT 0x1f031f03 -#define mmMMEA1_IO_RD_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA1_IO_WR_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA1_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA1_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA1_IO_RD_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA1_IO_WR_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA1_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 -#define mmMMEA1_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 -#define mmMMEA1_IO_RD_PRI_URGENCY_MASK_DEFAULT 0xffffffff -#define mmMMEA1_IO_WR_PRI_URGENCY_MASK_DEFAULT 0xffffffff -#define mmMMEA1_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA1_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA1_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA1_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA1_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA1_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA1_SDP_ARB_DRAM_DEFAULT 0x00102040 -#define mmMMEA1_SDP_ARB_FINAL_DEFAULT 0x00007fff -#define mmMMEA1_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 -#define mmMMEA1_SDP_IO_PRIORITY_DEFAULT 0x00000000 -#define mmMMEA1_SDP_CREDITS_DEFAULT 0x000100bf -#define mmMMEA1_SDP_TAG_RESERVE0_DEFAULT 0x00000000 -#define mmMMEA1_SDP_TAG_RESERVE1_DEFAULT 0x00000000 -#define mmMMEA1_SDP_VCC_RESERVE0_DEFAULT 0x00000000 -#define mmMMEA1_SDP_VCC_RESERVE1_DEFAULT 0x00000000 -#define mmMMEA1_SDP_VCD_RESERVE0_DEFAULT 0x00000000 -#define mmMMEA1_SDP_VCD_RESERVE1_DEFAULT 0x00000000 -#define mmMMEA1_SDP_REQ_CNTL_DEFAULT 0x0000000f -#define mmMMEA1_MISC_DEFAULT 0x00180130 -#define mmMMEA1_LATENCY_SAMPLING_DEFAULT 0x00000000 -#define mmMMEA1_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmMMEA1_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmMMEA1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmMMEA1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmMMEA1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 -#define mmMMEA1_EDC_CNT_DEFAULT 0x00000000 -#define mmMMEA1_EDC_CNT2_DEFAULT 0x00000000 -#define mmMMEA1_DSM_CNTL_DEFAULT 0x00000000 -#define mmMMEA1_DSM_CNTLA_DEFAULT 0x00000000 -#define mmMMEA1_DSM_CNTLB_DEFAULT 0x00000000 -#define mmMMEA1_DSM_CNTL2_DEFAULT 0x00000000 -#define mmMMEA1_DSM_CNTL2A_DEFAULT 0x00000000 -#define mmMMEA1_DSM_CNTL2B_DEFAULT 0x00000000 -#define mmMMEA1_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmMMEA1_EDC_MODE_DEFAULT 0x00000000 -#define mmMMEA1_ERR_STATUS_DEFAULT 0x00000000 -#define mmMMEA1_MISC2_DEFAULT 0x00000000 - - -// addressBlock: mmhub_pctldec -#define mmPCTL_MISC_DEFAULT 0x00000889 -#define mmPCTL_MMHUB_DEEPSLEEP_DEFAULT 0x00000000 -#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_DEFAULT 0x00000000 -#define mmPCTL_PG_IGNORE_DEEPSLEEP_DEFAULT 0x00000000 -#define mmPCTL_PG_DAGB_DEFAULT 0x00000000 -#define mmPCTL0_RENG_RAM_INDEX_DEFAULT 0x00000000 -#define mmPCTL0_RENG_RAM_DATA_DEFAULT 0x00000000 -#define mmPCTL0_RENG_EXECUTE_DEFAULT 0x00000000 -#define mmPCTL0_MISC_DEFAULT 0x00001000 -#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 -#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 -#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 -#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff -#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff -#define mmPCTL1_RENG_RAM_INDEX_DEFAULT 0x00000000 -#define mmPCTL1_RENG_RAM_DATA_DEFAULT 0x00000000 -#define mmPCTL1_RENG_EXECUTE_DEFAULT 0x00000000 -#define mmPCTL1_MISC_DEFAULT 0x00000800 -#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x061f05a0 -#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08590800 -#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 -#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff -#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff -#define mmPCTL2_RENG_RAM_INDEX_DEFAULT 0x00000000 -#define mmPCTL2_RENG_RAM_DATA_DEFAULT 0x00000000 -#define mmPCTL2_RENG_EXECUTE_DEFAULT 0x00000000 -#define mmPCTL2_MISC_DEFAULT 0x00000800 -#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x069f0620 -#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08b3085a -#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 -#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff -#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff - - -// addressBlock: mmhub_l1tlb_vml1dec -#define mmMC_VM_MX_L1_TLB0_STATUS_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB1_STATUS_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB2_STATUS_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB3_STATUS_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB4_STATUS_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB5_STATUS_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB6_STATUS_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB7_STATUS_DEFAULT 0x00000000 - - -// addressBlock: mmhub_l1tlb_vml1pldec -#define mmMC_VM_MX_L1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_PERFCOUNTER2_CFG_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_PERFCOUNTER3_CFG_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 - - -// addressBlock: mmhub_l1tlb_vml1prdec -#define mmMC_VM_MX_L1_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_PERFCOUNTER_HI_DEFAULT 0x00000000 - - -// addressBlock: mmhub_utcl2_atcl2dec -#define mmATC_L2_CNTL_DEFAULT 0x000001c9 -#define mmATC_L2_CNTL2_DEFAULT 0x00000100 -#define mmATC_L2_CACHE_DATA0_DEFAULT 0x00000000 -#define mmATC_L2_CACHE_DATA1_DEFAULT 0x00000000 -#define mmATC_L2_CACHE_DATA2_DEFAULT 0x00000000 -#define mmATC_L2_CNTL3_DEFAULT 0x000001f8 -#define mmATC_L2_STATUS_DEFAULT 0x00000000 -#define mmATC_L2_STATUS2_DEFAULT 0x00000000 -#define mmATC_L2_MISC_CG_DEFAULT 0x00000200 -#define mmATC_L2_MEM_POWER_LS_DEFAULT 0x00000208 -#define mmATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 - - -// addressBlock: mmhub_utcl2_vml2pfdec -#define mmVM_L2_CNTL_DEFAULT 0x00080602 -#define mmVM_L2_CNTL2_DEFAULT 0x00000000 -#define mmVM_L2_CNTL3_DEFAULT 0x80100007 -#define mmVM_L2_STATUS_DEFAULT 0x00000000 -#define mmVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090 -#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc -#define mmVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000 -#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff -#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff -#define mmVM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000 -#define mmVM_L2_CNTL4_DEFAULT 0x000000c1 -#define mmVM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000 -#define mmVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000 -#define mmVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000 -#define mmVM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000 -#define mmVM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 - - -// addressBlock: mmhub_utcl2_vml2vcdec -#define mmVM_CONTEXT0_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT1_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT2_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT3_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT4_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT5_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT6_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT7_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT8_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT9_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT10_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT11_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT12_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT13_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT14_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT15_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXTS_DISABLE_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG0_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG1_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG2_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG3_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG4_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG5_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG6_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG7_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG8_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG9_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG10_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG11_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG12_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG13_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG14_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG15_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG16_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG17_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 - - -// addressBlock: mmhub_utcl2_vml2pldec -#define mmMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 - - -// addressBlock: mmhub_utcl2_vml2prdec -#define mmMC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 - - -// addressBlock: mmhub_utcl2_vmsharedhvdec -#define mmMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000 -#define mmVM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100 -#define mmMC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000 -#define mmVM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000 -#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000 -#define mmUTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080 - - -// addressBlock: mmhub_utcl2_vmsharedpfdec -#define mmMC_VM_NB_MMIOBASE_DEFAULT 0x00000000 -#define mmMC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000 -#define mmMC_VM_NB_PCI_CTRL_DEFAULT 0x00000000 -#define mmMC_VM_NB_PCI_ARB_DEFAULT 0x00000008 -#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 -#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000 -#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000 -#define mmMC_VM_FB_OFFSET_DEFAULT 0x00000000 -#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 -#define mmMC_VM_STEERING_DEFAULT 0x00000001 -#define mmMC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000 -#define mmMC_MEM_POWER_LS_DEFAULT 0x00000208 -#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000 -#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000 -#define mmMC_VM_APT_CNTL_DEFAULT 0x00000000 -#define mmMC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000 -#define mmMC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff -#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000 - - -// addressBlock: mmhub_utcl2_vmsharedvcdec -#define mmMC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000 -#define mmMC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000 -#define mmMC_VM_AGP_TOP_DEFAULT 0x00000000 -#define mmMC_VM_AGP_BOT_DEFAULT 0x00000000 -#define mmMC_VM_AGP_BASE_DEFAULT 0x00000000 -#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000 -#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00002501 - - -// addressBlock: mmhub_utcl2_atcl2pfcntrdec -#define mmATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 - - -// addressBlock: mmhub_utcl2_atcl2pfcntldec -#define mmATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_offset.h deleted file mode 100644 index 352ffae7a7ca..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_offset.h +++ /dev/null @@ -1,1967 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _mmhub_1_0_OFFSET_HEADER -#define _mmhub_1_0_OFFSET_HEADER - - - -// addressBlock: mmhub_dagbdec -// base address: 0x68000 -#define mmDAGB0_RDCLI0 0x0000 -#define mmDAGB0_RDCLI0_BASE_IDX 0 -#define mmDAGB0_RDCLI1 0x0001 -#define mmDAGB0_RDCLI1_BASE_IDX 0 -#define mmDAGB0_RDCLI2 0x0002 -#define mmDAGB0_RDCLI2_BASE_IDX 0 -#define mmDAGB0_RDCLI3 0x0003 -#define mmDAGB0_RDCLI3_BASE_IDX 0 -#define mmDAGB0_RDCLI4 0x0004 -#define mmDAGB0_RDCLI4_BASE_IDX 0 -#define mmDAGB0_RDCLI5 0x0005 -#define mmDAGB0_RDCLI5_BASE_IDX 0 -#define mmDAGB0_RDCLI6 0x0006 -#define mmDAGB0_RDCLI6_BASE_IDX 0 -#define mmDAGB0_RDCLI7 0x0007 -#define mmDAGB0_RDCLI7_BASE_IDX 0 -#define mmDAGB0_RDCLI8 0x0008 -#define mmDAGB0_RDCLI8_BASE_IDX 0 -#define mmDAGB0_RDCLI9 0x0009 -#define mmDAGB0_RDCLI9_BASE_IDX 0 -#define mmDAGB0_RDCLI10 0x000a -#define mmDAGB0_RDCLI10_BASE_IDX 0 -#define mmDAGB0_RDCLI11 0x000b -#define mmDAGB0_RDCLI11_BASE_IDX 0 -#define mmDAGB0_RDCLI12 0x000c -#define mmDAGB0_RDCLI12_BASE_IDX 0 -#define mmDAGB0_RDCLI13 0x000d -#define mmDAGB0_RDCLI13_BASE_IDX 0 -#define mmDAGB0_RDCLI14 0x000e -#define mmDAGB0_RDCLI14_BASE_IDX 0 -#define mmDAGB0_RDCLI15 0x000f -#define mmDAGB0_RDCLI15_BASE_IDX 0 -#define mmDAGB0_RD_CNTL 0x0010 -#define mmDAGB0_RD_CNTL_BASE_IDX 0 -#define mmDAGB0_RD_GMI_CNTL 0x0011 -#define mmDAGB0_RD_GMI_CNTL_BASE_IDX 0 -#define mmDAGB0_RD_ADDR_DAGB 0x0012 -#define mmDAGB0_RD_ADDR_DAGB_BASE_IDX 0 -#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0013 -#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 -#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0014 -#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 -#define mmDAGB0_RD_CGTT_CLK_CTRL 0x0015 -#define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0 -#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0016 -#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 -#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x0017 -#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 -#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0018 -#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 -#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0019 -#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 -#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001a -#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 -#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001b -#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 -#define mmDAGB0_RD_VC0_CNTL 0x001c -#define mmDAGB0_RD_VC0_CNTL_BASE_IDX 0 -#define mmDAGB0_RD_VC1_CNTL 0x001d -#define mmDAGB0_RD_VC1_CNTL_BASE_IDX 0 -#define mmDAGB0_RD_VC2_CNTL 0x001e -#define mmDAGB0_RD_VC2_CNTL_BASE_IDX 0 -#define mmDAGB0_RD_VC3_CNTL 0x001f -#define mmDAGB0_RD_VC3_CNTL_BASE_IDX 0 -#define mmDAGB0_RD_VC4_CNTL 0x0020 -#define mmDAGB0_RD_VC4_CNTL_BASE_IDX 0 -#define mmDAGB0_RD_VC5_CNTL 0x0021 -#define mmDAGB0_RD_VC5_CNTL_BASE_IDX 0 -#define mmDAGB0_RD_VC6_CNTL 0x0022 -#define mmDAGB0_RD_VC6_CNTL_BASE_IDX 0 -#define mmDAGB0_RD_VC7_CNTL 0x0023 -#define mmDAGB0_RD_VC7_CNTL_BASE_IDX 0 -#define mmDAGB0_RD_CNTL_MISC 0x0024 -#define mmDAGB0_RD_CNTL_MISC_BASE_IDX 0 -#define mmDAGB0_RD_TLB_CREDIT 0x0025 -#define mmDAGB0_RD_TLB_CREDIT_BASE_IDX 0 -#define mmDAGB0_RDCLI_ASK_PENDING 0x0026 -#define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0 -#define mmDAGB0_RDCLI_GO_PENDING 0x0027 -#define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX 0 -#define mmDAGB0_RDCLI_GBLSEND_PENDING 0x0028 -#define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0 -#define mmDAGB0_RDCLI_TLB_PENDING 0x0029 -#define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0 -#define mmDAGB0_RDCLI_OARB_PENDING 0x002a -#define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0 -#define mmDAGB0_RDCLI_OSD_PENDING 0x002b -#define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0 -#define mmDAGB0_WRCLI0 0x002c -#define mmDAGB0_WRCLI0_BASE_IDX 0 -#define mmDAGB0_WRCLI1 0x002d -#define mmDAGB0_WRCLI1_BASE_IDX 0 -#define mmDAGB0_WRCLI2 0x002e -#define mmDAGB0_WRCLI2_BASE_IDX 0 -#define mmDAGB0_WRCLI3 0x002f -#define mmDAGB0_WRCLI3_BASE_IDX 0 -#define mmDAGB0_WRCLI4 0x0030 -#define mmDAGB0_WRCLI4_BASE_IDX 0 -#define mmDAGB0_WRCLI5 0x0031 -#define mmDAGB0_WRCLI5_BASE_IDX 0 -#define mmDAGB0_WRCLI6 0x0032 -#define mmDAGB0_WRCLI6_BASE_IDX 0 -#define mmDAGB0_WRCLI7 0x0033 -#define mmDAGB0_WRCLI7_BASE_IDX 0 -#define mmDAGB0_WRCLI8 0x0034 -#define mmDAGB0_WRCLI8_BASE_IDX 0 -#define mmDAGB0_WRCLI9 0x0035 -#define mmDAGB0_WRCLI9_BASE_IDX 0 -#define mmDAGB0_WRCLI10 0x0036 -#define mmDAGB0_WRCLI10_BASE_IDX 0 -#define mmDAGB0_WRCLI11 0x0037 -#define mmDAGB0_WRCLI11_BASE_IDX 0 -#define mmDAGB0_WRCLI12 0x0038 -#define mmDAGB0_WRCLI12_BASE_IDX 0 -#define mmDAGB0_WRCLI13 0x0039 -#define mmDAGB0_WRCLI13_BASE_IDX 0 -#define mmDAGB0_WRCLI14 0x003a -#define mmDAGB0_WRCLI14_BASE_IDX 0 -#define mmDAGB0_WRCLI15 0x003b -#define mmDAGB0_WRCLI15_BASE_IDX 0 -#define mmDAGB0_WR_CNTL 0x003c -#define mmDAGB0_WR_CNTL_BASE_IDX 0 -#define mmDAGB0_WR_GMI_CNTL 0x003d -#define mmDAGB0_WR_GMI_CNTL_BASE_IDX 0 -#define mmDAGB0_WR_ADDR_DAGB 0x003e -#define mmDAGB0_WR_ADDR_DAGB_BASE_IDX 0 -#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x003f -#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 -#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0040 -#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 -#define mmDAGB0_WR_CGTT_CLK_CTRL 0x0041 -#define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0 -#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0042 -#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 -#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x0043 -#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 -#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0044 -#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 -#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0045 -#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 -#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0046 -#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 -#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x0047 -#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 -#define mmDAGB0_WR_DATA_DAGB 0x0048 -#define mmDAGB0_WR_DATA_DAGB_BASE_IDX 0 -#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0049 -#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 -#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x004a -#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 -#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1 0x004b -#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 -#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x004c -#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 -#define mmDAGB0_WR_VC0_CNTL 0x004d -#define mmDAGB0_WR_VC0_CNTL_BASE_IDX 0 -#define mmDAGB0_WR_VC1_CNTL 0x004e -#define mmDAGB0_WR_VC1_CNTL_BASE_IDX 0 -#define mmDAGB0_WR_VC2_CNTL 0x004f -#define mmDAGB0_WR_VC2_CNTL_BASE_IDX 0 -#define mmDAGB0_WR_VC3_CNTL 0x0050 -#define mmDAGB0_WR_VC3_CNTL_BASE_IDX 0 -#define mmDAGB0_WR_VC4_CNTL 0x0051 -#define mmDAGB0_WR_VC4_CNTL_BASE_IDX 0 -#define mmDAGB0_WR_VC5_CNTL 0x0052 -#define mmDAGB0_WR_VC5_CNTL_BASE_IDX 0 -#define mmDAGB0_WR_VC6_CNTL 0x0053 -#define mmDAGB0_WR_VC6_CNTL_BASE_IDX 0 -#define mmDAGB0_WR_VC7_CNTL 0x0054 -#define mmDAGB0_WR_VC7_CNTL_BASE_IDX 0 -#define mmDAGB0_WR_CNTL_MISC 0x0055 -#define mmDAGB0_WR_CNTL_MISC_BASE_IDX 0 -#define mmDAGB0_WR_TLB_CREDIT 0x0056 -#define mmDAGB0_WR_TLB_CREDIT_BASE_IDX 0 -#define mmDAGB0_WR_DATA_CREDIT 0x0057 -#define mmDAGB0_WR_DATA_CREDIT_BASE_IDX 0 -#define mmDAGB0_WR_MISC_CREDIT 0x0058 -#define mmDAGB0_WR_MISC_CREDIT_BASE_IDX 0 -#define mmDAGB0_WRCLI_ASK_PENDING 0x0059 -#define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0 -#define mmDAGB0_WRCLI_GO_PENDING 0x005a -#define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX 0 -#define mmDAGB0_WRCLI_GBLSEND_PENDING 0x005b -#define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0 -#define mmDAGB0_WRCLI_TLB_PENDING 0x005c -#define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0 -#define mmDAGB0_WRCLI_OARB_PENDING 0x005d -#define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0 -#define mmDAGB0_WRCLI_OSD_PENDING 0x005e -#define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0 -#define mmDAGB0_WRCLI_DBUS_ASK_PENDING 0x005f -#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 -#define mmDAGB0_WRCLI_DBUS_GO_PENDING 0x0060 -#define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 -#define mmDAGB0_DAGB_DLY 0x0061 -#define mmDAGB0_DAGB_DLY_BASE_IDX 0 -#define mmDAGB0_CNTL_MISC 0x0062 -#define mmDAGB0_CNTL_MISC_BASE_IDX 0 -#define mmDAGB0_CNTL_MISC2 0x0063 -#define mmDAGB0_CNTL_MISC2_BASE_IDX 0 -#define mmDAGB0_FIFO_EMPTY 0x0064 -#define mmDAGB0_FIFO_EMPTY_BASE_IDX 0 -#define mmDAGB0_FIFO_FULL 0x0065 -#define mmDAGB0_FIFO_FULL_BASE_IDX 0 -#define mmDAGB0_WR_CREDITS_FULL 0x0066 -#define mmDAGB0_WR_CREDITS_FULL_BASE_IDX 0 -#define mmDAGB0_RD_CREDITS_FULL 0x0067 -#define mmDAGB0_RD_CREDITS_FULL_BASE_IDX 0 -#define mmDAGB0_PERFCOUNTER_LO 0x0068 -#define mmDAGB0_PERFCOUNTER_LO_BASE_IDX 0 -#define mmDAGB0_PERFCOUNTER_HI 0x0069 -#define mmDAGB0_PERFCOUNTER_HI_BASE_IDX 0 -#define mmDAGB0_PERFCOUNTER0_CFG 0x006a -#define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0 -#define mmDAGB0_PERFCOUNTER1_CFG 0x006b -#define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0 -#define mmDAGB0_PERFCOUNTER2_CFG 0x006c -#define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0 -#define mmDAGB0_PERFCOUNTER_RSLT_CNTL 0x006d -#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 -#define mmDAGB0_RESERVE0 0x006e -#define mmDAGB0_RESERVE0_BASE_IDX 0 -#define mmDAGB0_RESERVE1 0x006f -#define mmDAGB0_RESERVE1_BASE_IDX 0 -#define mmDAGB0_RESERVE2 0x0070 -#define mmDAGB0_RESERVE2_BASE_IDX 0 -#define mmDAGB0_RESERVE3 0x0071 -#define mmDAGB0_RESERVE3_BASE_IDX 0 -#define mmDAGB0_RESERVE4 0x0072 -#define mmDAGB0_RESERVE4_BASE_IDX 0 -#define mmDAGB0_RESERVE5 0x0073 -#define mmDAGB0_RESERVE5_BASE_IDX 0 -#define mmDAGB0_RESERVE6 0x0074 -#define mmDAGB0_RESERVE6_BASE_IDX 0 -#define mmDAGB0_RESERVE7 0x0075 -#define mmDAGB0_RESERVE7_BASE_IDX 0 -#define mmDAGB0_RESERVE8 0x0076 -#define mmDAGB0_RESERVE8_BASE_IDX 0 -#define mmDAGB0_RESERVE9 0x0077 -#define mmDAGB0_RESERVE9_BASE_IDX 0 -#define mmDAGB0_RESERVE10 0x0078 -#define mmDAGB0_RESERVE10_BASE_IDX 0 -#define mmDAGB0_RESERVE11 0x0079 -#define mmDAGB0_RESERVE11_BASE_IDX 0 -#define mmDAGB0_RESERVE12 0x007a -#define mmDAGB0_RESERVE12_BASE_IDX 0 -#define mmDAGB0_RESERVE13 0x007b -#define mmDAGB0_RESERVE13_BASE_IDX 0 -#define mmDAGB0_RESERVE14 0x007c -#define mmDAGB0_RESERVE14_BASE_IDX 0 -#define mmDAGB0_RESERVE15 0x007d -#define mmDAGB0_RESERVE15_BASE_IDX 0 -#define mmDAGB0_RESERVE16 0x007e -#define mmDAGB0_RESERVE16_BASE_IDX 0 -#define mmDAGB0_RESERVE17 0x007f -#define mmDAGB0_RESERVE17_BASE_IDX 0 -#define mmDAGB1_RDCLI0 0x0080 -#define mmDAGB1_RDCLI0_BASE_IDX 0 -#define mmDAGB1_RDCLI1 0x0081 -#define mmDAGB1_RDCLI1_BASE_IDX 0 -#define mmDAGB1_RDCLI2 0x0082 -#define mmDAGB1_RDCLI2_BASE_IDX 0 -#define mmDAGB1_RDCLI3 0x0083 -#define mmDAGB1_RDCLI3_BASE_IDX 0 -#define mmDAGB1_RDCLI4 0x0084 -#define mmDAGB1_RDCLI4_BASE_IDX 0 -#define mmDAGB1_RDCLI5 0x0085 -#define mmDAGB1_RDCLI5_BASE_IDX 0 -#define mmDAGB1_RDCLI6 0x0086 -#define mmDAGB1_RDCLI6_BASE_IDX 0 -#define mmDAGB1_RDCLI7 0x0087 -#define mmDAGB1_RDCLI7_BASE_IDX 0 -#define mmDAGB1_RDCLI8 0x0088 -#define mmDAGB1_RDCLI8_BASE_IDX 0 -#define mmDAGB1_RDCLI9 0x0089 -#define mmDAGB1_RDCLI9_BASE_IDX 0 -#define mmDAGB1_RDCLI10 0x008a -#define mmDAGB1_RDCLI10_BASE_IDX 0 -#define mmDAGB1_RDCLI11 0x008b -#define mmDAGB1_RDCLI11_BASE_IDX 0 -#define mmDAGB1_RDCLI12 0x008c -#define mmDAGB1_RDCLI12_BASE_IDX 0 -#define mmDAGB1_RDCLI13 0x008d -#define mmDAGB1_RDCLI13_BASE_IDX 0 -#define mmDAGB1_RDCLI14 0x008e -#define mmDAGB1_RDCLI14_BASE_IDX 0 -#define mmDAGB1_RDCLI15 0x008f -#define mmDAGB1_RDCLI15_BASE_IDX 0 -#define mmDAGB1_RD_CNTL 0x0090 -#define mmDAGB1_RD_CNTL_BASE_IDX 0 -#define mmDAGB1_RD_GMI_CNTL 0x0091 -#define mmDAGB1_RD_GMI_CNTL_BASE_IDX 0 -#define mmDAGB1_RD_ADDR_DAGB 0x0092 -#define mmDAGB1_RD_ADDR_DAGB_BASE_IDX 0 -#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST 0x0093 -#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 -#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 0x0094 -#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 -#define mmDAGB1_RD_CGTT_CLK_CTRL 0x0095 -#define mmDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 0 -#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x0096 -#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 -#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL 0x0097 -#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 -#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x0098 -#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 -#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x0099 -#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 -#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x009a -#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 -#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x009b -#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 -#define mmDAGB1_RD_VC0_CNTL 0x009c -#define mmDAGB1_RD_VC0_CNTL_BASE_IDX 0 -#define mmDAGB1_RD_VC1_CNTL 0x009d -#define mmDAGB1_RD_VC1_CNTL_BASE_IDX 0 -#define mmDAGB1_RD_VC2_CNTL 0x009e -#define mmDAGB1_RD_VC2_CNTL_BASE_IDX 0 -#define mmDAGB1_RD_VC3_CNTL 0x009f -#define mmDAGB1_RD_VC3_CNTL_BASE_IDX 0 -#define mmDAGB1_RD_VC4_CNTL 0x00a0 -#define mmDAGB1_RD_VC4_CNTL_BASE_IDX 0 -#define mmDAGB1_RD_VC5_CNTL 0x00a1 -#define mmDAGB1_RD_VC5_CNTL_BASE_IDX 0 -#define mmDAGB1_RD_VC6_CNTL 0x00a2 -#define mmDAGB1_RD_VC6_CNTL_BASE_IDX 0 -#define mmDAGB1_RD_VC7_CNTL 0x00a3 -#define mmDAGB1_RD_VC7_CNTL_BASE_IDX 0 -#define mmDAGB1_RD_CNTL_MISC 0x00a4 -#define mmDAGB1_RD_CNTL_MISC_BASE_IDX 0 -#define mmDAGB1_RD_TLB_CREDIT 0x00a5 -#define mmDAGB1_RD_TLB_CREDIT_BASE_IDX 0 -#define mmDAGB1_RDCLI_ASK_PENDING 0x00a6 -#define mmDAGB1_RDCLI_ASK_PENDING_BASE_IDX 0 -#define mmDAGB1_RDCLI_GO_PENDING 0x00a7 -#define mmDAGB1_RDCLI_GO_PENDING_BASE_IDX 0 -#define mmDAGB1_RDCLI_GBLSEND_PENDING 0x00a8 -#define mmDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 0 -#define mmDAGB1_RDCLI_TLB_PENDING 0x00a9 -#define mmDAGB1_RDCLI_TLB_PENDING_BASE_IDX 0 -#define mmDAGB1_RDCLI_OARB_PENDING 0x00aa -#define mmDAGB1_RDCLI_OARB_PENDING_BASE_IDX 0 -#define mmDAGB1_RDCLI_OSD_PENDING 0x00ab -#define mmDAGB1_RDCLI_OSD_PENDING_BASE_IDX 0 -#define mmDAGB1_WRCLI0 0x00ac -#define mmDAGB1_WRCLI0_BASE_IDX 0 -#define mmDAGB1_WRCLI1 0x00ad -#define mmDAGB1_WRCLI1_BASE_IDX 0 -#define mmDAGB1_WRCLI2 0x00ae -#define mmDAGB1_WRCLI2_BASE_IDX 0 -#define mmDAGB1_WRCLI3 0x00af -#define mmDAGB1_WRCLI3_BASE_IDX 0 -#define mmDAGB1_WRCLI4 0x00b0 -#define mmDAGB1_WRCLI4_BASE_IDX 0 -#define mmDAGB1_WRCLI5 0x00b1 -#define mmDAGB1_WRCLI5_BASE_IDX 0 -#define mmDAGB1_WRCLI6 0x00b2 -#define mmDAGB1_WRCLI6_BASE_IDX 0 -#define mmDAGB1_WRCLI7 0x00b3 -#define mmDAGB1_WRCLI7_BASE_IDX 0 -#define mmDAGB1_WRCLI8 0x00b4 -#define mmDAGB1_WRCLI8_BASE_IDX 0 -#define mmDAGB1_WRCLI9 0x00b5 -#define mmDAGB1_WRCLI9_BASE_IDX 0 -#define mmDAGB1_WRCLI10 0x00b6 -#define mmDAGB1_WRCLI10_BASE_IDX 0 -#define mmDAGB1_WRCLI11 0x00b7 -#define mmDAGB1_WRCLI11_BASE_IDX 0 -#define mmDAGB1_WRCLI12 0x00b8 -#define mmDAGB1_WRCLI12_BASE_IDX 0 -#define mmDAGB1_WRCLI13 0x00b9 -#define mmDAGB1_WRCLI13_BASE_IDX 0 -#define mmDAGB1_WRCLI14 0x00ba -#define mmDAGB1_WRCLI14_BASE_IDX 0 -#define mmDAGB1_WRCLI15 0x00bb -#define mmDAGB1_WRCLI15_BASE_IDX 0 -#define mmDAGB1_WR_CNTL 0x00bc -#define mmDAGB1_WR_CNTL_BASE_IDX 0 -#define mmDAGB1_WR_GMI_CNTL 0x00bd -#define mmDAGB1_WR_GMI_CNTL_BASE_IDX 0 -#define mmDAGB1_WR_ADDR_DAGB 0x00be -#define mmDAGB1_WR_ADDR_DAGB_BASE_IDX 0 -#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST 0x00bf -#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 -#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 0x00c0 -#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 -#define mmDAGB1_WR_CGTT_CLK_CTRL 0x00c1 -#define mmDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX 0 -#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0x00c2 -#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 -#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL 0x00c3 -#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 -#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0 0x00c4 -#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 -#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0x00c5 -#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 -#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1 0x00c6 -#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 -#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 0x00c7 -#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 -#define mmDAGB1_WR_DATA_DAGB 0x00c8 -#define mmDAGB1_WR_DATA_DAGB_BASE_IDX 0 -#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0 0x00c9 -#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 -#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0 0x00ca -#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 -#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1 0x00cb -#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 -#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1 0x00cc -#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 -#define mmDAGB1_WR_VC0_CNTL 0x00cd -#define mmDAGB1_WR_VC0_CNTL_BASE_IDX 0 -#define mmDAGB1_WR_VC1_CNTL 0x00ce -#define mmDAGB1_WR_VC1_CNTL_BASE_IDX 0 -#define mmDAGB1_WR_VC2_CNTL 0x00cf -#define mmDAGB1_WR_VC2_CNTL_BASE_IDX 0 -#define mmDAGB1_WR_VC3_CNTL 0x00d0 -#define mmDAGB1_WR_VC3_CNTL_BASE_IDX 0 -#define mmDAGB1_WR_VC4_CNTL 0x00d1 -#define mmDAGB1_WR_VC4_CNTL_BASE_IDX 0 -#define mmDAGB1_WR_VC5_CNTL 0x00d2 -#define mmDAGB1_WR_VC5_CNTL_BASE_IDX 0 -#define mmDAGB1_WR_VC6_CNTL 0x00d3 -#define mmDAGB1_WR_VC6_CNTL_BASE_IDX 0 -#define mmDAGB1_WR_VC7_CNTL 0x00d4 -#define mmDAGB1_WR_VC7_CNTL_BASE_IDX 0 -#define mmDAGB1_WR_CNTL_MISC 0x00d5 -#define mmDAGB1_WR_CNTL_MISC_BASE_IDX 0 -#define mmDAGB1_WR_TLB_CREDIT 0x00d6 -#define mmDAGB1_WR_TLB_CREDIT_BASE_IDX 0 -#define mmDAGB1_WR_DATA_CREDIT 0x00d7 -#define mmDAGB1_WR_DATA_CREDIT_BASE_IDX 0 -#define mmDAGB1_WR_MISC_CREDIT 0x00d8 -#define mmDAGB1_WR_MISC_CREDIT_BASE_IDX 0 -#define mmDAGB1_WRCLI_ASK_PENDING 0x00d9 -#define mmDAGB1_WRCLI_ASK_PENDING_BASE_IDX 0 -#define mmDAGB1_WRCLI_GO_PENDING 0x00da -#define mmDAGB1_WRCLI_GO_PENDING_BASE_IDX 0 -#define mmDAGB1_WRCLI_GBLSEND_PENDING 0x00db -#define mmDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX 0 -#define mmDAGB1_WRCLI_TLB_PENDING 0x00dc -#define mmDAGB1_WRCLI_TLB_PENDING_BASE_IDX 0 -#define mmDAGB1_WRCLI_OARB_PENDING 0x00dd -#define mmDAGB1_WRCLI_OARB_PENDING_BASE_IDX 0 -#define mmDAGB1_WRCLI_OSD_PENDING 0x00de -#define mmDAGB1_WRCLI_OSD_PENDING_BASE_IDX 0 -#define mmDAGB1_WRCLI_DBUS_ASK_PENDING 0x00df -#define mmDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 -#define mmDAGB1_WRCLI_DBUS_GO_PENDING 0x00e0 -#define mmDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 -#define mmDAGB1_DAGB_DLY 0x00e1 -#define mmDAGB1_DAGB_DLY_BASE_IDX 0 -#define mmDAGB1_CNTL_MISC 0x00e2 -#define mmDAGB1_CNTL_MISC_BASE_IDX 0 -#define mmDAGB1_CNTL_MISC2 0x00e3 -#define mmDAGB1_CNTL_MISC2_BASE_IDX 0 -#define mmDAGB1_FIFO_EMPTY 0x00e4 -#define mmDAGB1_FIFO_EMPTY_BASE_IDX 0 -#define mmDAGB1_FIFO_FULL 0x00e5 -#define mmDAGB1_FIFO_FULL_BASE_IDX 0 -#define mmDAGB1_WR_CREDITS_FULL 0x00e6 -#define mmDAGB1_WR_CREDITS_FULL_BASE_IDX 0 -#define mmDAGB1_RD_CREDITS_FULL 0x00e7 -#define mmDAGB1_RD_CREDITS_FULL_BASE_IDX 0 -#define mmDAGB1_PERFCOUNTER_LO 0x00e8 -#define mmDAGB1_PERFCOUNTER_LO_BASE_IDX 0 -#define mmDAGB1_PERFCOUNTER_HI 0x00e9 -#define mmDAGB1_PERFCOUNTER_HI_BASE_IDX 0 -#define mmDAGB1_PERFCOUNTER0_CFG 0x00ea -#define mmDAGB1_PERFCOUNTER0_CFG_BASE_IDX 0 -#define mmDAGB1_PERFCOUNTER1_CFG 0x00eb -#define mmDAGB1_PERFCOUNTER1_CFG_BASE_IDX 0 -#define mmDAGB1_PERFCOUNTER2_CFG 0x00ec -#define mmDAGB1_PERFCOUNTER2_CFG_BASE_IDX 0 -#define mmDAGB1_PERFCOUNTER_RSLT_CNTL 0x00ed -#define mmDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 -#define mmDAGB1_RESERVE0 0x00ee -#define mmDAGB1_RESERVE0_BASE_IDX 0 -#define mmDAGB1_RESERVE1 0x00ef -#define mmDAGB1_RESERVE1_BASE_IDX 0 -#define mmDAGB1_RESERVE2 0x00f0 -#define mmDAGB1_RESERVE2_BASE_IDX 0 -#define mmDAGB1_RESERVE3 0x00f1 -#define mmDAGB1_RESERVE3_BASE_IDX 0 -#define mmDAGB1_RESERVE4 0x00f2 -#define mmDAGB1_RESERVE4_BASE_IDX 0 -#define mmDAGB1_RESERVE5 0x00f3 -#define mmDAGB1_RESERVE5_BASE_IDX 0 -#define mmDAGB1_RESERVE6 0x00f4 -#define mmDAGB1_RESERVE6_BASE_IDX 0 -#define mmDAGB1_RESERVE7 0x00f5 -#define mmDAGB1_RESERVE7_BASE_IDX 0 -#define mmDAGB1_RESERVE8 0x00f6 -#define mmDAGB1_RESERVE8_BASE_IDX 0 -#define mmDAGB1_RESERVE9 0x00f7 -#define mmDAGB1_RESERVE9_BASE_IDX 0 -#define mmDAGB1_RESERVE10 0x00f8 -#define mmDAGB1_RESERVE10_BASE_IDX 0 -#define mmDAGB1_RESERVE11 0x00f9 -#define mmDAGB1_RESERVE11_BASE_IDX 0 -#define mmDAGB1_RESERVE12 0x00fa -#define mmDAGB1_RESERVE12_BASE_IDX 0 -#define mmDAGB1_RESERVE13 0x00fb -#define mmDAGB1_RESERVE13_BASE_IDX 0 -#define mmDAGB1_RESERVE14 0x00fc -#define mmDAGB1_RESERVE14_BASE_IDX 0 -#define mmDAGB1_RESERVE15 0x00fd -#define mmDAGB1_RESERVE15_BASE_IDX 0 -#define mmDAGB1_RESERVE16 0x00fe -#define mmDAGB1_RESERVE16_BASE_IDX 0 -#define mmDAGB1_RESERVE17 0x00ff -#define mmDAGB1_RESERVE17_BASE_IDX 0 - - -// addressBlock: mmhub_ea_mmeadec -// base address: 0x68400 -#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0100 -#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 -#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0101 -#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 -#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0102 -#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 -#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0103 -#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 -#define mmMMEA0_DRAM_RD_GRP2VC_MAP 0x0104 -#define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 -#define mmMMEA0_DRAM_WR_GRP2VC_MAP 0x0105 -#define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 -#define mmMMEA0_DRAM_RD_LAZY 0x0106 -#define mmMMEA0_DRAM_RD_LAZY_BASE_IDX 0 -#define mmMMEA0_DRAM_WR_LAZY 0x0107 -#define mmMMEA0_DRAM_WR_LAZY_BASE_IDX 0 -#define mmMMEA0_DRAM_RD_CAM_CNTL 0x0108 -#define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 0 -#define mmMMEA0_DRAM_WR_CAM_CNTL 0x0109 -#define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 0 -#define mmMMEA0_DRAM_PAGE_BURST 0x010a -#define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX 0 -#define mmMMEA0_DRAM_RD_PRI_AGE 0x010b -#define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 0 -#define mmMMEA0_DRAM_WR_PRI_AGE 0x010c -#define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 0 -#define mmMMEA0_DRAM_RD_PRI_QUEUING 0x010d -#define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 0 -#define mmMMEA0_DRAM_WR_PRI_QUEUING 0x010e -#define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 0 -#define mmMMEA0_DRAM_RD_PRI_FIXED 0x010f -#define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 0 -#define mmMMEA0_DRAM_WR_PRI_FIXED 0x0110 -#define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 0 -#define mmMMEA0_DRAM_RD_PRI_URGENCY 0x0111 -#define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 0 -#define mmMMEA0_DRAM_WR_PRI_URGENCY 0x0112 -#define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 0 -#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0113 -#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 -#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0114 -#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 -#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0115 -#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 -#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0116 -#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 -#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0117 -#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 -#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0118 -#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 -#define mmMMEA0_ADDRNORM_BASE_ADDR0 0x0132 -#define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 0 -#define mmMMEA0_ADDRNORM_LIMIT_ADDR0 0x0133 -#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 -#define mmMMEA0_ADDRNORM_BASE_ADDR1 0x0134 -#define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 0 -#define mmMMEA0_ADDRNORM_LIMIT_ADDR1 0x0135 -#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 -#define mmMMEA0_ADDRNORM_OFFSET_ADDR1 0x0136 -#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 -#define mmMMEA0_ADDRNORM_HOLE_CNTL 0x0141 -#define mmMMEA0_ADDRNORM_HOLE_CNTL_BASE_IDX 0 -#define mmMMEA0_ADDRDEC_BANK_CFG 0x0142 -#define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 0 -#define mmMMEA0_ADDRDEC_MISC_CFG 0x0143 -#define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 0 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 0x0144 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 0x0145 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 0x0146 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 0x0147 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 0x0148 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC 0x0149 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 0x014a -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 0x014b -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 0x014c -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0 -#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x014d -#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x0158 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x0159 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x015a -#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x015b -#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x015c -#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x015d -#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x015e -#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x015f -#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x0160 -#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x0161 -#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x0162 -#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x0163 -#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x0164 -#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x0165 -#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x0166 -#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x0167 -#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x0168 -#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x0169 -#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x016a -#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x016b -#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_RM_SEL_CS01 0x016c -#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_RM_SEL_CS23 0x016d -#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01 0x016e -#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 -#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23 0x016f -#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x0170 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x0171 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x0172 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x0173 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x0174 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x0175 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x0176 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x0177 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x0178 -#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x0179 -#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x017a -#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x017b -#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x017c -#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x017d -#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x017e -#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x017f -#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x0180 -#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x0181 -#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x0182 -#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x0183 -#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_RM_SEL_CS01 0x0184 -#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_RM_SEL_CS23 0x0185 -#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01 0x0186 -#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 -#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23 0x0187 -#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 -#define mmMMEA0_IO_RD_CLI2GRP_MAP0 0x01d0 -#define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 -#define mmMMEA0_IO_RD_CLI2GRP_MAP1 0x01d1 -#define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 -#define mmMMEA0_IO_WR_CLI2GRP_MAP0 0x01d2 -#define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 -#define mmMMEA0_IO_WR_CLI2GRP_MAP1 0x01d3 -#define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 -#define mmMMEA0_IO_RD_COMBINE_FLUSH 0x01d4 -#define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 0 -#define mmMMEA0_IO_WR_COMBINE_FLUSH 0x01d5 -#define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 0 -#define mmMMEA0_IO_GROUP_BURST 0x01d6 -#define mmMMEA0_IO_GROUP_BURST_BASE_IDX 0 -#define mmMMEA0_IO_RD_PRI_AGE 0x01d7 -#define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX 0 -#define mmMMEA0_IO_WR_PRI_AGE 0x01d8 -#define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX 0 -#define mmMMEA0_IO_RD_PRI_QUEUING 0x01d9 -#define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 0 -#define mmMMEA0_IO_WR_PRI_QUEUING 0x01da -#define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 0 -#define mmMMEA0_IO_RD_PRI_FIXED 0x01db -#define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX 0 -#define mmMMEA0_IO_WR_PRI_FIXED 0x01dc -#define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX 0 -#define mmMMEA0_IO_RD_PRI_URGENCY 0x01dd -#define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 0 -#define mmMMEA0_IO_WR_PRI_URGENCY 0x01de -#define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 0 -#define mmMMEA0_IO_RD_PRI_URGENCY_MASK 0x01df -#define mmMMEA0_IO_RD_PRI_URGENCY_MASK_BASE_IDX 0 -#define mmMMEA0_IO_WR_PRI_URGENCY_MASK 0x01e0 -#define mmMMEA0_IO_WR_PRI_URGENCY_MASK_BASE_IDX 0 -#define mmMMEA0_IO_RD_PRI_QUANT_PRI1 0x01e1 -#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 -#define mmMMEA0_IO_RD_PRI_QUANT_PRI2 0x01e2 -#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 -#define mmMMEA0_IO_RD_PRI_QUANT_PRI3 0x01e3 -#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 -#define mmMMEA0_IO_WR_PRI_QUANT_PRI1 0x01e4 -#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 -#define mmMMEA0_IO_WR_PRI_QUANT_PRI2 0x01e5 -#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 -#define mmMMEA0_IO_WR_PRI_QUANT_PRI3 0x01e6 -#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 -#define mmMMEA0_SDP_ARB_DRAM 0x01e7 -#define mmMMEA0_SDP_ARB_DRAM_BASE_IDX 0 -#define mmMMEA0_SDP_ARB_FINAL 0x01e9 -#define mmMMEA0_SDP_ARB_FINAL_BASE_IDX 0 -#define mmMMEA0_SDP_DRAM_PRIORITY 0x01ea -#define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 0 -#define mmMMEA0_SDP_IO_PRIORITY 0x01ec -#define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX 0 -#define mmMMEA0_SDP_CREDITS 0x01ed -#define mmMMEA0_SDP_CREDITS_BASE_IDX 0 -#define mmMMEA0_SDP_TAG_RESERVE0 0x01ee -#define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX 0 -#define mmMMEA0_SDP_TAG_RESERVE1 0x01ef -#define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX 0 -#define mmMMEA0_SDP_VCC_RESERVE0 0x01f0 -#define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX 0 -#define mmMMEA0_SDP_VCC_RESERVE1 0x01f1 -#define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX 0 -#define mmMMEA0_SDP_VCD_RESERVE0 0x01f2 -#define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX 0 -#define mmMMEA0_SDP_VCD_RESERVE1 0x01f3 -#define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX 0 -#define mmMMEA0_SDP_REQ_CNTL 0x01f4 -#define mmMMEA0_SDP_REQ_CNTL_BASE_IDX 0 -#define mmMMEA0_MISC 0x01f5 -#define mmMMEA0_MISC_BASE_IDX 0 -#define mmMMEA0_LATENCY_SAMPLING 0x01f6 -#define mmMMEA0_LATENCY_SAMPLING_BASE_IDX 0 -#define mmMMEA0_PERFCOUNTER_LO 0x01f7 -#define mmMMEA0_PERFCOUNTER_LO_BASE_IDX 0 -#define mmMMEA0_PERFCOUNTER_HI 0x01f8 -#define mmMMEA0_PERFCOUNTER_HI_BASE_IDX 0 -#define mmMMEA0_PERFCOUNTER0_CFG 0x01f9 -#define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX 0 -#define mmMMEA0_PERFCOUNTER1_CFG 0x01fa -#define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX 0 -#define mmMMEA0_PERFCOUNTER_RSLT_CNTL 0x01fb -#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 -#define mmMMEA0_EDC_CNT 0x0201 -#define mmMMEA0_EDC_CNT_BASE_IDX 0 -#define mmMMEA0_EDC_CNT2 0x0202 -#define mmMMEA0_EDC_CNT2_BASE_IDX 0 -#define mmMMEA0_DSM_CNTL 0x0203 -#define mmMMEA0_DSM_CNTL_BASE_IDX 0 -#define mmMMEA0_DSM_CNTLA 0x0204 -#define mmMMEA0_DSM_CNTLA_BASE_IDX 0 -#define mmMMEA0_DSM_CNTLB 0x0205 -#define mmMMEA0_DSM_CNTLB_BASE_IDX 0 -#define mmMMEA0_DSM_CNTL2 0x0206 -#define mmMMEA0_DSM_CNTL2_BASE_IDX 0 -#define mmMMEA0_DSM_CNTL2A 0x0207 -#define mmMMEA0_DSM_CNTL2A_BASE_IDX 0 -#define mmMMEA0_DSM_CNTL2B 0x0208 -#define mmMMEA0_DSM_CNTL2B_BASE_IDX 0 -#define mmMMEA0_CGTT_CLK_CTRL 0x020a -#define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX 0 -#define mmMMEA0_EDC_MODE 0x020b -#define mmMMEA0_EDC_MODE_BASE_IDX 0 -#define mmMMEA0_ERR_STATUS 0x020c -#define mmMMEA0_ERR_STATUS_BASE_IDX 0 -#define mmMMEA0_MISC2 0x020d -#define mmMMEA0_MISC2_BASE_IDX 0 -#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0 0x0240 -#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 -#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1 0x0241 -#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 -#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0 0x0242 -#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 -#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1 0x0243 -#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 -#define mmMMEA1_DRAM_RD_GRP2VC_MAP 0x0244 -#define mmMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 -#define mmMMEA1_DRAM_WR_GRP2VC_MAP 0x0245 -#define mmMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 -#define mmMMEA1_DRAM_RD_LAZY 0x0246 -#define mmMMEA1_DRAM_RD_LAZY_BASE_IDX 0 -#define mmMMEA1_DRAM_WR_LAZY 0x0247 -#define mmMMEA1_DRAM_WR_LAZY_BASE_IDX 0 -#define mmMMEA1_DRAM_RD_CAM_CNTL 0x0248 -#define mmMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX 0 -#define mmMMEA1_DRAM_WR_CAM_CNTL 0x0249 -#define mmMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX 0 -#define mmMMEA1_DRAM_PAGE_BURST 0x024a -#define mmMMEA1_DRAM_PAGE_BURST_BASE_IDX 0 -#define mmMMEA1_DRAM_RD_PRI_AGE 0x024b -#define mmMMEA1_DRAM_RD_PRI_AGE_BASE_IDX 0 -#define mmMMEA1_DRAM_WR_PRI_AGE 0x024c -#define mmMMEA1_DRAM_WR_PRI_AGE_BASE_IDX 0 -#define mmMMEA1_DRAM_RD_PRI_QUEUING 0x024d -#define mmMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX 0 -#define mmMMEA1_DRAM_WR_PRI_QUEUING 0x024e -#define mmMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX 0 -#define mmMMEA1_DRAM_RD_PRI_FIXED 0x024f -#define mmMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX 0 -#define mmMMEA1_DRAM_WR_PRI_FIXED 0x0250 -#define mmMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX 0 -#define mmMMEA1_DRAM_RD_PRI_URGENCY 0x0251 -#define mmMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX 0 -#define mmMMEA1_DRAM_WR_PRI_URGENCY 0x0252 -#define mmMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX 0 -#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1 0x0253 -#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 -#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2 0x0254 -#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 -#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3 0x0255 -#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 -#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1 0x0256 -#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 -#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2 0x0257 -#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 -#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3 0x0258 -#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 -#define mmMMEA1_ADDRNORM_BASE_ADDR0 0x0272 -#define mmMMEA1_ADDRNORM_BASE_ADDR0_BASE_IDX 0 -#define mmMMEA1_ADDRNORM_LIMIT_ADDR0 0x0273 -#define mmMMEA1_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 -#define mmMMEA1_ADDRNORM_BASE_ADDR1 0x0274 -#define mmMMEA1_ADDRNORM_BASE_ADDR1_BASE_IDX 0 -#define mmMMEA1_ADDRNORM_LIMIT_ADDR1 0x0275 -#define mmMMEA1_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 -#define mmMMEA1_ADDRNORM_OFFSET_ADDR1 0x0276 -#define mmMMEA1_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 -#define mmMMEA1_ADDRNORM_HOLE_CNTL 0x0281 -#define mmMMEA1_ADDRNORM_HOLE_CNTL_BASE_IDX 0 -#define mmMMEA1_ADDRDEC_BANK_CFG 0x0282 -#define mmMMEA1_ADDRDEC_BANK_CFG_BASE_IDX 0 -#define mmMMEA1_ADDRDEC_MISC_CFG 0x0283 -#define mmMMEA1_ADDRDEC_MISC_CFG_BASE_IDX 0 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 0x0284 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 0x0285 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 0x0286 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 0x0287 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 0x0288 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC 0x0289 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2 0x028a -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0 0x028b -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1 0x028c -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0 -#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE 0x028d -#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0 0x0298 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1 0x0299 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2 0x029a -#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3 0x029b -#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 0x029c -#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 0x029d -#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 0x029e -#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 0x029f -#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01 0x02a0 -#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23 0x02a1 -#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 0x02a2 -#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 0x02a3 -#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01 0x02a4 -#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23 0x02a5 -#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01 0x02a6 -#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23 0x02a7 -#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01 0x02a8 -#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23 0x02a9 -#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01 0x02aa -#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23 0x02ab -#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_RM_SEL_CS01 0x02ac -#define mmMMEA1_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_RM_SEL_CS23 0x02ad -#define mmMMEA1_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01 0x02ae -#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 -#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23 0x02af -#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0 0x02b0 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1 0x02b1 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2 0x02b2 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3 0x02b3 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 0x02b4 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 0x02b5 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 0x02b6 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 0x02b7 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01 0x02b8 -#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23 0x02b9 -#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 0x02ba -#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 0x02bb -#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01 0x02bc -#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23 0x02bd -#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01 0x02be -#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23 0x02bf -#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01 0x02c0 -#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23 0x02c1 -#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01 0x02c2 -#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23 0x02c3 -#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_RM_SEL_CS01 0x02c4 -#define mmMMEA1_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_RM_SEL_CS23 0x02c5 -#define mmMMEA1_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01 0x02c6 -#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 -#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23 0x02c7 -#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 -#define mmMMEA1_IO_RD_CLI2GRP_MAP0 0x0310 -#define mmMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 -#define mmMMEA1_IO_RD_CLI2GRP_MAP1 0x0311 -#define mmMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 -#define mmMMEA1_IO_WR_CLI2GRP_MAP0 0x0312 -#define mmMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 -#define mmMMEA1_IO_WR_CLI2GRP_MAP1 0x0313 -#define mmMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 -#define mmMMEA1_IO_RD_COMBINE_FLUSH 0x0314 -#define mmMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX 0 -#define mmMMEA1_IO_WR_COMBINE_FLUSH 0x0315 -#define mmMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX 0 -#define mmMMEA1_IO_GROUP_BURST 0x0316 -#define mmMMEA1_IO_GROUP_BURST_BASE_IDX 0 -#define mmMMEA1_IO_RD_PRI_AGE 0x0317 -#define mmMMEA1_IO_RD_PRI_AGE_BASE_IDX 0 -#define mmMMEA1_IO_WR_PRI_AGE 0x0318 -#define mmMMEA1_IO_WR_PRI_AGE_BASE_IDX 0 -#define mmMMEA1_IO_RD_PRI_QUEUING 0x0319 -#define mmMMEA1_IO_RD_PRI_QUEUING_BASE_IDX 0 -#define mmMMEA1_IO_WR_PRI_QUEUING 0x031a -#define mmMMEA1_IO_WR_PRI_QUEUING_BASE_IDX 0 -#define mmMMEA1_IO_RD_PRI_FIXED 0x031b -#define mmMMEA1_IO_RD_PRI_FIXED_BASE_IDX 0 -#define mmMMEA1_IO_WR_PRI_FIXED 0x031c -#define mmMMEA1_IO_WR_PRI_FIXED_BASE_IDX 0 -#define mmMMEA1_IO_RD_PRI_URGENCY 0x031d -#define mmMMEA1_IO_RD_PRI_URGENCY_BASE_IDX 0 -#define mmMMEA1_IO_WR_PRI_URGENCY 0x031e -#define mmMMEA1_IO_WR_PRI_URGENCY_BASE_IDX 0 -#define mmMMEA1_IO_RD_PRI_URGENCY_MASK 0x031f -#define mmMMEA1_IO_RD_PRI_URGENCY_MASK_BASE_IDX 0 -#define mmMMEA1_IO_WR_PRI_URGENCY_MASK 0x0320 -#define mmMMEA1_IO_WR_PRI_URGENCY_MASK_BASE_IDX 0 -#define mmMMEA1_IO_RD_PRI_QUANT_PRI1 0x0321 -#define mmMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 -#define mmMMEA1_IO_RD_PRI_QUANT_PRI2 0x0322 -#define mmMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 -#define mmMMEA1_IO_RD_PRI_QUANT_PRI3 0x0323 -#define mmMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 -#define mmMMEA1_IO_WR_PRI_QUANT_PRI1 0x0324 -#define mmMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 -#define mmMMEA1_IO_WR_PRI_QUANT_PRI2 0x0325 -#define mmMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 -#define mmMMEA1_IO_WR_PRI_QUANT_PRI3 0x0326 -#define mmMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 -#define mmMMEA1_SDP_ARB_DRAM 0x0327 -#define mmMMEA1_SDP_ARB_DRAM_BASE_IDX 0 -#define mmMMEA1_SDP_ARB_FINAL 0x0329 -#define mmMMEA1_SDP_ARB_FINAL_BASE_IDX 0 -#define mmMMEA1_SDP_DRAM_PRIORITY 0x032a -#define mmMMEA1_SDP_DRAM_PRIORITY_BASE_IDX 0 -#define mmMMEA1_SDP_IO_PRIORITY 0x032c -#define mmMMEA1_SDP_IO_PRIORITY_BASE_IDX 0 -#define mmMMEA1_SDP_CREDITS 0x032d -#define mmMMEA1_SDP_CREDITS_BASE_IDX 0 -#define mmMMEA1_SDP_TAG_RESERVE0 0x032e -#define mmMMEA1_SDP_TAG_RESERVE0_BASE_IDX 0 -#define mmMMEA1_SDP_TAG_RESERVE1 0x032f -#define mmMMEA1_SDP_TAG_RESERVE1_BASE_IDX 0 -#define mmMMEA1_SDP_VCC_RESERVE0 0x0330 -#define mmMMEA1_SDP_VCC_RESERVE0_BASE_IDX 0 -#define mmMMEA1_SDP_VCC_RESERVE1 0x0331 -#define mmMMEA1_SDP_VCC_RESERVE1_BASE_IDX 0 -#define mmMMEA1_SDP_VCD_RESERVE0 0x0332 -#define mmMMEA1_SDP_VCD_RESERVE0_BASE_IDX 0 -#define mmMMEA1_SDP_VCD_RESERVE1 0x0333 -#define mmMMEA1_SDP_VCD_RESERVE1_BASE_IDX 0 -#define mmMMEA1_SDP_REQ_CNTL 0x0334 -#define mmMMEA1_SDP_REQ_CNTL_BASE_IDX 0 -#define mmMMEA1_MISC 0x0335 -#define mmMMEA1_MISC_BASE_IDX 0 -#define mmMMEA1_LATENCY_SAMPLING 0x0336 -#define mmMMEA1_LATENCY_SAMPLING_BASE_IDX 0 -#define mmMMEA1_PERFCOUNTER_LO 0x0337 -#define mmMMEA1_PERFCOUNTER_LO_BASE_IDX 0 -#define mmMMEA1_PERFCOUNTER_HI 0x0338 -#define mmMMEA1_PERFCOUNTER_HI_BASE_IDX 0 -#define mmMMEA1_PERFCOUNTER0_CFG 0x0339 -#define mmMMEA1_PERFCOUNTER0_CFG_BASE_IDX 0 -#define mmMMEA1_PERFCOUNTER1_CFG 0x033a -#define mmMMEA1_PERFCOUNTER1_CFG_BASE_IDX 0 -#define mmMMEA1_PERFCOUNTER_RSLT_CNTL 0x033b -#define mmMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 -#define mmMMEA1_EDC_CNT 0x0341 -#define mmMMEA1_EDC_CNT_BASE_IDX 0 -#define mmMMEA1_EDC_CNT2 0x0342 -#define mmMMEA1_EDC_CNT2_BASE_IDX 0 -#define mmMMEA1_DSM_CNTL 0x0343 -#define mmMMEA1_DSM_CNTL_BASE_IDX 0 -#define mmMMEA1_DSM_CNTLA 0x0344 -#define mmMMEA1_DSM_CNTLA_BASE_IDX 0 -#define mmMMEA1_DSM_CNTLB 0x0345 -#define mmMMEA1_DSM_CNTLB_BASE_IDX 0 -#define mmMMEA1_DSM_CNTL2 0x0346 -#define mmMMEA1_DSM_CNTL2_BASE_IDX 0 -#define mmMMEA1_DSM_CNTL2A 0x0347 -#define mmMMEA1_DSM_CNTL2A_BASE_IDX 0 -#define mmMMEA1_DSM_CNTL2B 0x0348 -#define mmMMEA1_DSM_CNTL2B_BASE_IDX 0 -#define mmMMEA1_CGTT_CLK_CTRL 0x034a -#define mmMMEA1_CGTT_CLK_CTRL_BASE_IDX 0 -#define mmMMEA1_EDC_MODE 0x034b -#define mmMMEA1_EDC_MODE_BASE_IDX 0 -#define mmMMEA1_ERR_STATUS 0x034c -#define mmMMEA1_ERR_STATUS_BASE_IDX 0 -#define mmMMEA1_MISC2 0x034d -#define mmMMEA1_MISC2_BASE_IDX 0 - - -// addressBlock: mmhub_pctldec -// base address: 0x68e00 -#define mmPCTL_MISC 0x0380 -#define mmPCTL_MISC_BASE_IDX 0 -#define mmPCTL_MMHUB_DEEPSLEEP 0x0381 -#define mmPCTL_MMHUB_DEEPSLEEP_BASE_IDX 0 -#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0382 -#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 0 -#define mmPCTL_PG_IGNORE_DEEPSLEEP 0x0383 -#define mmPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 0 -#define mmPCTL_PG_DAGB 0x0384 -#define mmPCTL_PG_DAGB_BASE_IDX 0 -#define mmPCTL0_RENG_RAM_INDEX 0x0385 -#define mmPCTL0_RENG_RAM_INDEX_BASE_IDX 0 -#define mmPCTL0_RENG_RAM_DATA 0x0386 -#define mmPCTL0_RENG_RAM_DATA_BASE_IDX 0 -#define mmPCTL0_RENG_EXECUTE 0x0387 -#define mmPCTL0_RENG_EXECUTE_BASE_IDX 0 -#define mmPCTL0_MISC 0x0388 -#define mmPCTL0_MISC_BASE_IDX 0 -#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0 0x0389 -#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 -#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1 0x038a -#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 -#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2 0x038b -#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 -#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET 0x038c -#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 -#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x038d -#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 -#define mmPCTL1_RENG_RAM_INDEX 0x038e -#define mmPCTL1_RENG_RAM_INDEX_BASE_IDX 0 -#define mmPCTL1_RENG_RAM_DATA 0x038f -#define mmPCTL1_RENG_RAM_DATA_BASE_IDX 0 -#define mmPCTL1_RENG_EXECUTE 0x0390 -#define mmPCTL1_RENG_EXECUTE_BASE_IDX 0 -#define mmPCTL1_MISC 0x0391 -#define mmPCTL1_MISC_BASE_IDX 0 -#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0 0x0392 -#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 -#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1 0x0393 -#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 -#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2 0x0394 -#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 -#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET 0x0395 -#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 -#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0396 -#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 -#define mmPCTL2_RENG_RAM_INDEX 0x0397 -#define mmPCTL2_RENG_RAM_INDEX_BASE_IDX 0 -#define mmPCTL2_RENG_RAM_DATA 0x0398 -#define mmPCTL2_RENG_RAM_DATA_BASE_IDX 0 -#define mmPCTL2_RENG_EXECUTE 0x0399 -#define mmPCTL2_RENG_EXECUTE_BASE_IDX 0 -#define mmPCTL2_MISC 0x039a -#define mmPCTL2_MISC_BASE_IDX 0 -#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0 0x039b -#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 -#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1 0x039c -#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 -#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2 0x039d -#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 -#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET 0x039e -#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 -#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x039f -#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 - - -// addressBlock: mmhub_l1tlb_vml1dec -// base address: 0x69600 -#define mmMC_VM_MX_L1_TLB0_STATUS 0x0588 -#define mmMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 0 -#define mmMC_VM_MX_L1_TLB1_STATUS 0x0589 -#define mmMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 0 -#define mmMC_VM_MX_L1_TLB2_STATUS 0x058a -#define mmMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 0 -#define mmMC_VM_MX_L1_TLB3_STATUS 0x058b -#define mmMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 0 -#define mmMC_VM_MX_L1_TLB4_STATUS 0x058c -#define mmMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 0 -#define mmMC_VM_MX_L1_TLB5_STATUS 0x058d -#define mmMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 0 -#define mmMC_VM_MX_L1_TLB6_STATUS 0x058e -#define mmMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 0 -#define mmMC_VM_MX_L1_TLB7_STATUS 0x058f -#define mmMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 0 - - -// addressBlock: mmhub_l1tlb_vml1pldec -// base address: 0x69650 -#define mmMC_VM_MX_L1_PERFCOUNTER0_CFG 0x0594 -#define mmMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 0 -#define mmMC_VM_MX_L1_PERFCOUNTER1_CFG 0x0595 -#define mmMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 0 -#define mmMC_VM_MX_L1_PERFCOUNTER2_CFG 0x0596 -#define mmMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 0 -#define mmMC_VM_MX_L1_PERFCOUNTER3_CFG 0x0597 -#define mmMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 0 -#define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x0598 -#define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 - - -// addressBlock: mmhub_l1tlb_vml1prdec -// base address: 0x69670 -#define mmMC_VM_MX_L1_PERFCOUNTER_LO 0x059c -#define mmMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 0 -#define mmMC_VM_MX_L1_PERFCOUNTER_HI 0x059d -#define mmMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 0 - - -// addressBlock: mmhub_utcl2_atcl2dec -// base address: 0x69900 -#define mmATC_L2_CNTL 0x0640 -#define mmATC_L2_CNTL_BASE_IDX 0 -#define mmATC_L2_CNTL2 0x0641 -#define mmATC_L2_CNTL2_BASE_IDX 0 -#define mmATC_L2_CACHE_DATA0 0x0644 -#define mmATC_L2_CACHE_DATA0_BASE_IDX 0 -#define mmATC_L2_CACHE_DATA1 0x0645 -#define mmATC_L2_CACHE_DATA1_BASE_IDX 0 -#define mmATC_L2_CACHE_DATA2 0x0646 -#define mmATC_L2_CACHE_DATA2_BASE_IDX 0 -#define mmATC_L2_CNTL3 0x0647 -#define mmATC_L2_CNTL3_BASE_IDX 0 -#define mmATC_L2_STATUS 0x0648 -#define mmATC_L2_STATUS_BASE_IDX 0 -#define mmATC_L2_STATUS2 0x0649 -#define mmATC_L2_STATUS2_BASE_IDX 0 -#define mmATC_L2_MISC_CG 0x064a -#define mmATC_L2_MISC_CG_BASE_IDX 0 -#define mmATC_L2_MEM_POWER_LS 0x064b -#define mmATC_L2_MEM_POWER_LS_BASE_IDX 0 -#define mmATC_L2_CGTT_CLK_CTRL 0x064c -#define mmATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 - - -// addressBlock: mmhub_utcl2_vml2pfdec -// base address: 0x69a00 -#define mmVM_L2_CNTL 0x0680 -#define mmVM_L2_CNTL_BASE_IDX 0 -#define mmVM_L2_CNTL2 0x0681 -#define mmVM_L2_CNTL2_BASE_IDX 0 -#define mmVM_L2_CNTL3 0x0682 -#define mmVM_L2_CNTL3_BASE_IDX 0 -#define mmVM_L2_STATUS 0x0683 -#define mmVM_L2_STATUS_BASE_IDX 0 -#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x0684 -#define mmVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 -#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0685 -#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 -#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0686 -#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 -#define mmVM_L2_PROTECTION_FAULT_CNTL 0x0687 -#define mmVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 -#define mmVM_L2_PROTECTION_FAULT_CNTL2 0x0688 -#define mmVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 -#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0689 -#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 -#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4 0x068a -#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 -#define mmVM_L2_PROTECTION_FAULT_STATUS 0x068b -#define mmVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 -#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32 0x068c -#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 -#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32 0x068d -#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 -#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x068e -#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 -#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x068f -#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0691 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0692 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0693 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0694 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 -#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0695 -#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 -#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0696 -#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 -#define mmVM_L2_CNTL4 0x0697 -#define mmVM_L2_CNTL4_BASE_IDX 0 -#define mmVM_L2_MM_GROUP_RT_CLASSES 0x0698 -#define mmVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 -#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x0699 -#define mmVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 -#define mmVM_L2_BANK_SELECT_RESERVED_CID2 0x069a -#define mmVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 -#define mmVM_L2_CACHE_PARITY_CNTL 0x069b -#define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 -#define mmVM_L2_CGTT_CLK_CTRL 0x069e -#define mmVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 - - -// addressBlock: mmhub_utcl2_vml2vcdec -// base address: 0x69b00 -#define mmVM_CONTEXT0_CNTL 0x06c0 -#define mmVM_CONTEXT0_CNTL_BASE_IDX 0 -#define mmVM_CONTEXT1_CNTL 0x06c1 -#define mmVM_CONTEXT1_CNTL_BASE_IDX 0 -#define mmVM_CONTEXT2_CNTL 0x06c2 -#define mmVM_CONTEXT2_CNTL_BASE_IDX 0 -#define mmVM_CONTEXT3_CNTL 0x06c3 -#define mmVM_CONTEXT3_CNTL_BASE_IDX 0 -#define mmVM_CONTEXT4_CNTL 0x06c4 -#define mmVM_CONTEXT4_CNTL_BASE_IDX 0 -#define mmVM_CONTEXT5_CNTL 0x06c5 -#define mmVM_CONTEXT5_CNTL_BASE_IDX 0 -#define mmVM_CONTEXT6_CNTL 0x06c6 -#define mmVM_CONTEXT6_CNTL_BASE_IDX 0 -#define mmVM_CONTEXT7_CNTL 0x06c7 -#define mmVM_CONTEXT7_CNTL_BASE_IDX 0 -#define mmVM_CONTEXT8_CNTL 0x06c8 -#define mmVM_CONTEXT8_CNTL_BASE_IDX 0 -#define mmVM_CONTEXT9_CNTL 0x06c9 -#define mmVM_CONTEXT9_CNTL_BASE_IDX 0 -#define mmVM_CONTEXT10_CNTL 0x06ca -#define mmVM_CONTEXT10_CNTL_BASE_IDX 0 -#define mmVM_CONTEXT11_CNTL 0x06cb -#define mmVM_CONTEXT11_CNTL_BASE_IDX 0 -#define mmVM_CONTEXT12_CNTL 0x06cc -#define mmVM_CONTEXT12_CNTL_BASE_IDX 0 -#define mmVM_CONTEXT13_CNTL 0x06cd -#define mmVM_CONTEXT13_CNTL_BASE_IDX 0 -#define mmVM_CONTEXT14_CNTL 0x06ce -#define mmVM_CONTEXT14_CNTL_BASE_IDX 0 -#define mmVM_CONTEXT15_CNTL 0x06cf -#define mmVM_CONTEXT15_CNTL_BASE_IDX 0 -#define mmVM_CONTEXTS_DISABLE 0x06d0 -#define mmVM_CONTEXTS_DISABLE_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG0_SEM 0x06d1 -#define mmVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG1_SEM 0x06d2 -#define mmVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG2_SEM 0x06d3 -#define mmVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG3_SEM 0x06d4 -#define mmVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG4_SEM 0x06d5 -#define mmVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG5_SEM 0x06d6 -#define mmVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG6_SEM 0x06d7 -#define mmVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG7_SEM 0x06d8 -#define mmVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG8_SEM 0x06d9 -#define mmVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG9_SEM 0x06da -#define mmVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG10_SEM 0x06db -#define mmVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG11_SEM 0x06dc -#define mmVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG12_SEM 0x06dd -#define mmVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG13_SEM 0x06de -#define mmVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG14_SEM 0x06df -#define mmVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG15_SEM 0x06e0 -#define mmVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG16_SEM 0x06e1 -#define mmVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG17_SEM 0x06e2 -#define mmVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG0_REQ 0x06e3 -#define mmVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG1_REQ 0x06e4 -#define mmVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG2_REQ 0x06e5 -#define mmVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG3_REQ 0x06e6 -#define mmVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG4_REQ 0x06e7 -#define mmVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG5_REQ 0x06e8 -#define mmVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG6_REQ 0x06e9 -#define mmVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG7_REQ 0x06ea -#define mmVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG8_REQ 0x06eb -#define mmVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG9_REQ 0x06ec -#define mmVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG10_REQ 0x06ed -#define mmVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG11_REQ 0x06ee -#define mmVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG12_REQ 0x06ef -#define mmVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG13_REQ 0x06f0 -#define mmVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG14_REQ 0x06f1 -#define mmVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG15_REQ 0x06f2 -#define mmVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG16_REQ 0x06f3 -#define mmVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG17_REQ 0x06f4 -#define mmVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG0_ACK 0x06f5 -#define mmVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG1_ACK 0x06f6 -#define mmVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG2_ACK 0x06f7 -#define mmVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG3_ACK 0x06f8 -#define mmVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG4_ACK 0x06f9 -#define mmVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG5_ACK 0x06fa -#define mmVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG6_ACK 0x06fb -#define mmVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG7_ACK 0x06fc -#define mmVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG8_ACK 0x06fd -#define mmVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG9_ACK 0x06fe -#define mmVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG10_ACK 0x06ff -#define mmVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG11_ACK 0x0700 -#define mmVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG12_ACK 0x0701 -#define mmVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG13_ACK 0x0702 -#define mmVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG14_ACK 0x0703 -#define mmVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG15_ACK 0x0704 -#define mmVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG16_ACK 0x0705 -#define mmVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG17_ACK 0x0706 -#define mmVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0707 -#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0708 -#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0709 -#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x070a -#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x070b -#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x070c -#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x070d -#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x070e -#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x070f -#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0710 -#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0711 -#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0712 -#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0713 -#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0714 -#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0715 -#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0716 -#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0717 -#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0718 -#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0719 -#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x071a -#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x071b -#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x071c -#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x071d -#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x071e -#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x071f -#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0720 -#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0721 -#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0722 -#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0723 -#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0724 -#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0725 -#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0726 -#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0727 -#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0728 -#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0729 -#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x072a -#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x072b -#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x072c -#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x072d -#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x072e -#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x072f -#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0730 -#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0731 -#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0732 -#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0733 -#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0734 -#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0735 -#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0736 -#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0737 -#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0738 -#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0739 -#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x073a -#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x073b -#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x073c -#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x073d -#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x073e -#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x073f -#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0740 -#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0741 -#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0742 -#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0743 -#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0744 -#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0745 -#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0746 -#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0747 -#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0748 -#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0749 -#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x074a -#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x074b -#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x074c -#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x074d -#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x074e -#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x074f -#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0750 -#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0751 -#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0752 -#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0753 -#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0754 -#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0755 -#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0756 -#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0757 -#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0758 -#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0759 -#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x075a -#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x075b -#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x075c -#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x075d -#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x075e -#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x075f -#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0760 -#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0761 -#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0762 -#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0763 -#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0764 -#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0765 -#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0766 -#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0767 -#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0768 -#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0769 -#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x076a -#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x076b -#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x076c -#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x076d -#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x076e -#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x076f -#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0770 -#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0771 -#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0772 -#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0773 -#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0774 -#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0775 -#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0776 -#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0777 -#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0778 -#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0779 -#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x077a -#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x077b -#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x077c -#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x077d -#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x077e -#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x077f -#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0780 -#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0781 -#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0782 -#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0783 -#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0784 -#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0785 -#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0786 -#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0787 -#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0788 -#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0789 -#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x078a -#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 - - -// addressBlock: mmhub_utcl2_vml2pldec -// base address: 0x69e90 -#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x07a4 -#define mmMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 0 -#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x07a5 -#define mmMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 0 -#define mmMC_VM_L2_PERFCOUNTER2_CFG 0x07a6 -#define mmMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 0 -#define mmMC_VM_L2_PERFCOUNTER3_CFG 0x07a7 -#define mmMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 0 -#define mmMC_VM_L2_PERFCOUNTER4_CFG 0x07a8 -#define mmMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 0 -#define mmMC_VM_L2_PERFCOUNTER5_CFG 0x07a9 -#define mmMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0 -#define mmMC_VM_L2_PERFCOUNTER6_CFG 0x07aa -#define mmMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 0 -#define mmMC_VM_L2_PERFCOUNTER7_CFG 0x07ab -#define mmMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 0 -#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x07ac -#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 - - -// addressBlock: mmhub_utcl2_vml2prdec -// base address: 0x69ee0 -#define mmMC_VM_L2_PERFCOUNTER_LO 0x07b8 -#define mmMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 0 -#define mmMC_VM_L2_PERFCOUNTER_HI 0x07b9 -#define mmMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 0 - - -// addressBlock: mmhub_utcl2_vmsharedhvdec -// base address: 0x69f30 -#define mmMC_VM_FB_SIZE_OFFSET_VF0 0x07cc -#define mmMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 0 -#define mmMC_VM_FB_SIZE_OFFSET_VF1 0x07cd -#define mmMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 0 -#define mmMC_VM_FB_SIZE_OFFSET_VF2 0x07ce -#define mmMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 0 -#define mmMC_VM_FB_SIZE_OFFSET_VF3 0x07cf -#define mmMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 0 -#define mmMC_VM_FB_SIZE_OFFSET_VF4 0x07d0 -#define mmMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 0 -#define mmMC_VM_FB_SIZE_OFFSET_VF5 0x07d1 -#define mmMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 0 -#define mmMC_VM_FB_SIZE_OFFSET_VF6 0x07d2 -#define mmMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 0 -#define mmMC_VM_FB_SIZE_OFFSET_VF7 0x07d3 -#define mmMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 0 -#define mmMC_VM_FB_SIZE_OFFSET_VF8 0x07d4 -#define mmMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 0 -#define mmMC_VM_FB_SIZE_OFFSET_VF9 0x07d5 -#define mmMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 0 -#define mmMC_VM_FB_SIZE_OFFSET_VF10 0x07d6 -#define mmMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 0 -#define mmMC_VM_FB_SIZE_OFFSET_VF11 0x07d7 -#define mmMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 0 -#define mmMC_VM_FB_SIZE_OFFSET_VF12 0x07d8 -#define mmMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 0 -#define mmMC_VM_FB_SIZE_OFFSET_VF13 0x07d9 -#define mmMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 0 -#define mmMC_VM_FB_SIZE_OFFSET_VF14 0x07da -#define mmMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 0 -#define mmMC_VM_FB_SIZE_OFFSET_VF15 0x07db -#define mmMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 0 -#define mmVM_IOMMU_MMIO_CNTRL_1 0x07dc -#define mmVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 0 -#define mmMC_VM_MARC_BASE_LO_0 0x07dd -#define mmMC_VM_MARC_BASE_LO_0_BASE_IDX 0 -#define mmMC_VM_MARC_BASE_LO_1 0x07de -#define mmMC_VM_MARC_BASE_LO_1_BASE_IDX 0 -#define mmMC_VM_MARC_BASE_LO_2 0x07df -#define mmMC_VM_MARC_BASE_LO_2_BASE_IDX 0 -#define mmMC_VM_MARC_BASE_LO_3 0x07e0 -#define mmMC_VM_MARC_BASE_LO_3_BASE_IDX 0 -#define mmMC_VM_MARC_BASE_HI_0 0x07e1 -#define mmMC_VM_MARC_BASE_HI_0_BASE_IDX 0 -#define mmMC_VM_MARC_BASE_HI_1 0x07e2 -#define mmMC_VM_MARC_BASE_HI_1_BASE_IDX 0 -#define mmMC_VM_MARC_BASE_HI_2 0x07e3 -#define mmMC_VM_MARC_BASE_HI_2_BASE_IDX 0 -#define mmMC_VM_MARC_BASE_HI_3 0x07e4 -#define mmMC_VM_MARC_BASE_HI_3_BASE_IDX 0 -#define mmMC_VM_MARC_RELOC_LO_0 0x07e5 -#define mmMC_VM_MARC_RELOC_LO_0_BASE_IDX 0 -#define mmMC_VM_MARC_RELOC_LO_1 0x07e6 -#define mmMC_VM_MARC_RELOC_LO_1_BASE_IDX 0 -#define mmMC_VM_MARC_RELOC_LO_2 0x07e7 -#define mmMC_VM_MARC_RELOC_LO_2_BASE_IDX 0 -#define mmMC_VM_MARC_RELOC_LO_3 0x07e8 -#define mmMC_VM_MARC_RELOC_LO_3_BASE_IDX 0 -#define mmMC_VM_MARC_RELOC_HI_0 0x07e9 -#define mmMC_VM_MARC_RELOC_HI_0_BASE_IDX 0 -#define mmMC_VM_MARC_RELOC_HI_1 0x07ea -#define mmMC_VM_MARC_RELOC_HI_1_BASE_IDX 0 -#define mmMC_VM_MARC_RELOC_HI_2 0x07eb -#define mmMC_VM_MARC_RELOC_HI_2_BASE_IDX 0 -#define mmMC_VM_MARC_RELOC_HI_3 0x07ec -#define mmMC_VM_MARC_RELOC_HI_3_BASE_IDX 0 -#define mmMC_VM_MARC_LEN_LO_0 0x07ed -#define mmMC_VM_MARC_LEN_LO_0_BASE_IDX 0 -#define mmMC_VM_MARC_LEN_LO_1 0x07ee -#define mmMC_VM_MARC_LEN_LO_1_BASE_IDX 0 -#define mmMC_VM_MARC_LEN_LO_2 0x07ef -#define mmMC_VM_MARC_LEN_LO_2_BASE_IDX 0 -#define mmMC_VM_MARC_LEN_LO_3 0x07f0 -#define mmMC_VM_MARC_LEN_LO_3_BASE_IDX 0 -#define mmMC_VM_MARC_LEN_HI_0 0x07f1 -#define mmMC_VM_MARC_LEN_HI_0_BASE_IDX 0 -#define mmMC_VM_MARC_LEN_HI_1 0x07f2 -#define mmMC_VM_MARC_LEN_HI_1_BASE_IDX 0 -#define mmMC_VM_MARC_LEN_HI_2 0x07f3 -#define mmMC_VM_MARC_LEN_HI_2_BASE_IDX 0 -#define mmMC_VM_MARC_LEN_HI_3 0x07f4 -#define mmMC_VM_MARC_LEN_HI_3_BASE_IDX 0 -#define mmVM_IOMMU_CONTROL_REGISTER 0x07f5 -#define mmVM_IOMMU_CONTROL_REGISTER_BASE_IDX 0 -#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x07f6 -#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 0 -#define mmVM_PCIE_ATS_CNTL 0x07f7 -#define mmVM_PCIE_ATS_CNTL_BASE_IDX 0 -#define mmVM_PCIE_ATS_CNTL_VF_0 0x07f8 -#define mmVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 0 -#define mmVM_PCIE_ATS_CNTL_VF_1 0x07f9 -#define mmVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 0 -#define mmVM_PCIE_ATS_CNTL_VF_2 0x07fa -#define mmVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 0 -#define mmVM_PCIE_ATS_CNTL_VF_3 0x07fb -#define mmVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 0 -#define mmVM_PCIE_ATS_CNTL_VF_4 0x07fc -#define mmVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 0 -#define mmVM_PCIE_ATS_CNTL_VF_5 0x07fd -#define mmVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 0 -#define mmVM_PCIE_ATS_CNTL_VF_6 0x07fe -#define mmVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 0 -#define mmVM_PCIE_ATS_CNTL_VF_7 0x07ff -#define mmVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 0 -#define mmVM_PCIE_ATS_CNTL_VF_8 0x0800 -#define mmVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 0 -#define mmVM_PCIE_ATS_CNTL_VF_9 0x0801 -#define mmVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 0 -#define mmVM_PCIE_ATS_CNTL_VF_10 0x0802 -#define mmVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 0 -#define mmVM_PCIE_ATS_CNTL_VF_11 0x0803 -#define mmVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 0 -#define mmVM_PCIE_ATS_CNTL_VF_12 0x0804 -#define mmVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 0 -#define mmVM_PCIE_ATS_CNTL_VF_13 0x0805 -#define mmVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 0 -#define mmVM_PCIE_ATS_CNTL_VF_14 0x0806 -#define mmVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 0 -#define mmVM_PCIE_ATS_CNTL_VF_15 0x0807 -#define mmVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 0 -#define mmUTCL2_CGTT_CLK_CTRL 0x0808 -#define mmUTCL2_CGTT_CLK_CTRL_BASE_IDX 0 - - -// addressBlock: mmhub_utcl2_vmsharedpfdec -// base address: 0x6a040 -#define mmMC_VM_NB_MMIOBASE 0x0810 -#define mmMC_VM_NB_MMIOBASE_BASE_IDX 0 -#define mmMC_VM_NB_MMIOLIMIT 0x0811 -#define mmMC_VM_NB_MMIOLIMIT_BASE_IDX 0 -#define mmMC_VM_NB_PCI_CTRL 0x0812 -#define mmMC_VM_NB_PCI_CTRL_BASE_IDX 0 -#define mmMC_VM_NB_PCI_ARB 0x0813 -#define mmMC_VM_NB_PCI_ARB_BASE_IDX 0 -#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0814 -#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 -#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0815 -#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 -#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0x0816 -#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 -#define mmMC_VM_FB_OFFSET 0x0817 -#define mmMC_VM_FB_OFFSET_BASE_IDX 0 -#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0818 -#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 -#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0819 -#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 -#define mmMC_VM_STEERING 0x081a -#define mmMC_VM_STEERING_BASE_IDX 0 -#define mmMC_SHARED_VIRT_RESET_REQ 0x081b -#define mmMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 -#define mmMC_MEM_POWER_LS 0x081c -#define mmMC_MEM_POWER_LS_BASE_IDX 0 -#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x081d -#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 -#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x081e -#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 -#define mmMC_VM_APT_CNTL 0x081f -#define mmMC_VM_APT_CNTL_BASE_IDX 0 -#define mmMC_VM_LOCAL_HBM_ADDRESS_START 0x0820 -#define mmMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0 -#define mmMC_VM_LOCAL_HBM_ADDRESS_END 0x0821 -#define mmMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0 -#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0822 -#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0 - - -// addressBlock: mmhub_utcl2_vmsharedvcdec -// base address: 0x6a0b0 -#define mmMC_VM_FB_LOCATION_BASE 0x082c -#define mmMC_VM_FB_LOCATION_BASE_BASE_IDX 0 -#define mmMC_VM_FB_LOCATION_TOP 0x082d -#define mmMC_VM_FB_LOCATION_TOP_BASE_IDX 0 -#define mmMC_VM_AGP_TOP 0x082e -#define mmMC_VM_AGP_TOP_BASE_IDX 0 -#define mmMC_VM_AGP_BOT 0x082f -#define mmMC_VM_AGP_BOT_BASE_IDX 0 -#define mmMC_VM_AGP_BASE 0x0830 -#define mmMC_VM_AGP_BASE_BASE_IDX 0 -#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0831 -#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 -#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0832 -#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 -#define mmMC_VM_MX_L1_TLB_CNTL 0x0833 -#define mmMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 - - -// addressBlock: mmhub_utcl2_atcl2pfcntrdec -// base address: 0x6a100 -#define mmATC_L2_PERFCOUNTER_LO 0x0840 -#define mmATC_L2_PERFCOUNTER_LO_BASE_IDX 0 -#define mmATC_L2_PERFCOUNTER_HI 0x0841 -#define mmATC_L2_PERFCOUNTER_HI_BASE_IDX 0 - - -// addressBlock: mmhub_utcl2_atcl2pfcntldec -// base address: 0x6a120 -#define mmATC_L2_PERFCOUNTER0_CFG 0x0848 -#define mmATC_L2_PERFCOUNTER0_CFG_BASE_IDX 0 -#define mmATC_L2_PERFCOUNTER1_CFG 0x0849 -#define mmATC_L2_PERFCOUNTER1_CFG_BASE_IDX 0 -#define mmATC_L2_PERFCOUNTER_RSLT_CNTL 0x084a -#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h deleted file mode 100644 index 34278ef2aa1b..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h +++ /dev/null @@ -1,10127 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _mmhub_1_0_SH_MASK_HEADER -#define _mmhub_1_0_SH_MASK_HEADER - - -// addressBlock: mmhub_dagbdec -//DAGB0_RDCLI0 -#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 -#define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 -#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd -#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 -#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a -#define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L -#define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L -#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L -#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L -#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L -//DAGB0_RDCLI1 -#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 -#define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 -#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd -#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 -#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a -#define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L -#define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L -#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L -#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L -#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L -//DAGB0_RDCLI2 -#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 -#define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 -#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd -#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 -#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a -#define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L -#define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L -#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L -#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L -#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L -//DAGB0_RDCLI3 -#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 -#define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 -#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd -#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 -#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a -#define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L -#define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L -#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L -#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L -#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L -//DAGB0_RDCLI4 -#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 -#define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 -#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd -#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 -#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a -#define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L -#define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L -#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L -#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L -#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L -//DAGB0_RDCLI5 -#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 -#define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 -#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd -#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 -#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a -#define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L -#define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L -#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L -#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L -#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L -//DAGB0_RDCLI6 -#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 -#define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 -#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd -#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 -#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a -#define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L -#define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L -#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L -#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L -#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L -//DAGB0_RDCLI7 -#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 -#define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 -#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd -#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 -#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a -#define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L -#define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L -#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L -#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L -#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L -//DAGB0_RDCLI8 -#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 -#define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 -#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd -#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 -#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a -#define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L -#define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L -#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L -#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L -#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L -//DAGB0_RDCLI9 -#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 -#define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 -#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd -#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 -#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a -#define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L -#define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L -#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L -#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L -#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L -//DAGB0_RDCLI10 -#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 -#define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 -#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd -#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 -#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a -#define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L -#define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L -#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L -#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L -#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L -//DAGB0_RDCLI11 -#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 -#define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 -#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd -#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 -#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a -#define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L -#define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L -#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L -#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L -#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L -//DAGB0_RDCLI12 -#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 -#define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 -#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd -#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 -#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a -#define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L -#define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L -#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L -#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L -#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L -//DAGB0_RDCLI13 -#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 -#define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 -#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd -#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 -#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a -#define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L -#define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L -#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L -#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L -#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L -//DAGB0_RDCLI14 -#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 -#define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 -#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd -#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 -#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a -#define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L -#define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L -#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L -#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L -#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L -//DAGB0_RDCLI15 -#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 -#define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 -#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd -#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 -#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a -#define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L -#define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L -#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L -#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L -#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L -//DAGB0_RD_CNTL -#define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0 -#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 -#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa -#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 -#define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11 -#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 -#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 -#define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL -#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L -#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L -#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L -#define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L -#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L -#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L -//DAGB0_RD_GMI_CNTL -#define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 -#define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6 -#define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 -#define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd -#define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL -#define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L -#define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L -#define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L -//DAGB0_RD_ADDR_DAGB -#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 -#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 -#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 -#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 -#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L -#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L -#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L -#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L -//DAGB0_RD_OUTPUT_DAGB_MAX_BURST -#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 -#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 -#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 -#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc -#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 -#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 -#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 -#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c -#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL -#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L -#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L -#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L -#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L -#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L -#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L -#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L -//DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER -#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 -#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 -#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 -#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc -#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 -#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 -#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 -#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c -#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL -#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L -#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L -#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L -#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L -#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L -#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L -#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L -//DAGB0_RD_CGTT_CLK_CTRL -#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 -#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b -#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c -#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d -#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e -#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f -#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L -#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L -#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L -#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L -#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L -#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L -//DAGB0_L1TLB_RD_CGTT_CLK_CTRL -#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 -#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b -#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c -#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d -#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e -#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f -#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L -#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L -#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L -#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L -#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L -#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L -//DAGB0_ATCVM_RD_CGTT_CLK_CTRL -#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 -#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b -#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c -#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d -#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e -#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f -#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L -#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L -#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L -#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L -#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L -#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L -//DAGB0_RD_ADDR_DAGB_MAX_BURST0 -#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 -#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 -#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 -#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc -#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 -#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 -#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 -#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c -#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL -#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L -#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L -#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L -#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L -#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L -#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L -#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L -//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L -//DAGB0_RD_ADDR_DAGB_MAX_BURST1 -#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 -#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 -#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 -#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc -#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 -#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 -#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 -#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c -#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL -#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L -#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L -#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L -#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L -#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L -#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L -#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L -//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L -#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L -//DAGB0_RD_VC0_CNTL -#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc -#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB0_RD_VC1_CNTL -#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc -#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB0_RD_VC2_CNTL -#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc -#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB0_RD_VC3_CNTL -#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc -#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB0_RD_VC4_CNTL -#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc -#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB0_RD_VC5_CNTL -#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc -#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB0_RD_VC6_CNTL -#define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc -#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB0_RD_VC7_CNTL -#define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc -#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB0_RD_CNTL_MISC -#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 -#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 -#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd -#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 -#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 -#define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 -#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL -#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L -#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L -#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L -#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L -#define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L -//DAGB0_RD_TLB_CREDIT -#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 -#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 -#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa -#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf -#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 -#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 -#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL -#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L -#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L -#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L -#define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L -#define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L -//DAGB0_RDCLI_ASK_PENDING -#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 -#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB0_RDCLI_GO_PENDING -#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 -#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB0_RDCLI_GBLSEND_PENDING -#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 -#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB0_RDCLI_TLB_PENDING -#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 -#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB0_RDCLI_OARB_PENDING -#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 -#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB0_RDCLI_OSD_PENDING -#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 -#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB0_WRCLI0 -#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 -#define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 -#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd -#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 -#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a -#define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L -#define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L -#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L -#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L -#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L -//DAGB0_WRCLI1 -#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 -#define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 -#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd -#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 -#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a -#define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L -#define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L -#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L -#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L -#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L -//DAGB0_WRCLI2 -#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 -#define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 -#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd -#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 -#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a -#define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L -#define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L -#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L -#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L -#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L -//DAGB0_WRCLI3 -#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 -#define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 -#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd -#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 -#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a -#define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L -#define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L -#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L -#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L -#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L -//DAGB0_WRCLI4 -#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 -#define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 -#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd -#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 -#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a -#define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L -#define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L -#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L -#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L -#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L -//DAGB0_WRCLI5 -#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 -#define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 -#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd -#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 -#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a -#define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L -#define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L -#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L -#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L -#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L -//DAGB0_WRCLI6 -#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 -#define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 -#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd -#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 -#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a -#define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L -#define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L -#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L -#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L -#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L -//DAGB0_WRCLI7 -#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 -#define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 -#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd -#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 -#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a -#define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L -#define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L -#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L -#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L -#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L -//DAGB0_WRCLI8 -#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 -#define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 -#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd -#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 -#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a -#define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L -#define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L -#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L -#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L -#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L -//DAGB0_WRCLI9 -#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 -#define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 -#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd -#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 -#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a -#define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L -#define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L -#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L -#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L -#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L -//DAGB0_WRCLI10 -#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 -#define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 -#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd -#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 -#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a -#define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L -#define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L -#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L -#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L -#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L -//DAGB0_WRCLI11 -#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 -#define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 -#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd -#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 -#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a -#define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L -#define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L -#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L -#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L -#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L -//DAGB0_WRCLI12 -#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 -#define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 -#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd -#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 -#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a -#define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L -#define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L -#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L -#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L -#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L -//DAGB0_WRCLI13 -#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 -#define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 -#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd -#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 -#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a -#define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L -#define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L -#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L -#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L -#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L -//DAGB0_WRCLI14 -#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 -#define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 -#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd -#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 -#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a -#define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L -#define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L -#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L -#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L -#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L -//DAGB0_WRCLI15 -#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 -#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 -#define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 -#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd -#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 -#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a -#define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L -#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L -#define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L -#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L -#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L -#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L -//DAGB0_WR_CNTL -#define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0 -#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 -#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa -#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 -#define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11 -#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 -#define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 -#define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL -#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L -#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L -#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L -#define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L -#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L -#define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L -//DAGB0_WR_GMI_CNTL -#define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 -#define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6 -#define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 -#define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd -#define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL -#define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L -#define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L -#define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L -//DAGB0_WR_ADDR_DAGB -#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 -#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 -#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 -#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 -#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L -#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L -#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L -#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L -//DAGB0_WR_OUTPUT_DAGB_MAX_BURST -#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 -#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 -#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 -#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc -#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 -#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 -#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 -#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c -#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL -#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L -#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L -#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L -#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L -#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L -#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L -#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L -//DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER -#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 -#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 -#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 -#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc -#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 -#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 -#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 -#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c -#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL -#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L -#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L -#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L -#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L -#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L -#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L -#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L -//DAGB0_WR_CGTT_CLK_CTRL -#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 -#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b -#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c -#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d -#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e -#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f -#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L -#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L -#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L -#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L -#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L -#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L -//DAGB0_L1TLB_WR_CGTT_CLK_CTRL -#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 -#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b -#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c -#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d -#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e -#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f -#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L -#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L -#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L -#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L -#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L -#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L -//DAGB0_ATCVM_WR_CGTT_CLK_CTRL -#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 -#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b -#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c -#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d -#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e -#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f -#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L -#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L -#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L -#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L -#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L -#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L -//DAGB0_WR_ADDR_DAGB_MAX_BURST0 -#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 -#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 -#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 -#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc -#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 -#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 -#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 -#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c -#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL -#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L -#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L -#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L -#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L -#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L -#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L -#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L -//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L -//DAGB0_WR_ADDR_DAGB_MAX_BURST1 -#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 -#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 -#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 -#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc -#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 -#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 -#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 -#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c -#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL -#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L -#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L -#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L -#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L -#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L -#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L -#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L -//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L -#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L -//DAGB0_WR_DATA_DAGB -#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 -#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 -#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 -#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 -#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L -#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L -#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L -#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L -//DAGB0_WR_DATA_DAGB_MAX_BURST0 -#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 -#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 -#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 -#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc -#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 -#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 -#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 -#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c -#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL -#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L -#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L -#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L -#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L -#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L -#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L -#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L -//DAGB0_WR_DATA_DAGB_LAZY_TIMER0 -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L -//DAGB0_WR_DATA_DAGB_MAX_BURST1 -#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 -#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 -#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 -#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc -#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 -#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 -#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 -#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c -#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL -#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L -#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L -#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L -#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L -#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L -#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L -#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L -//DAGB0_WR_DATA_DAGB_LAZY_TIMER1 -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L -#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L -//DAGB0_WR_VC0_CNTL -#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc -#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB0_WR_VC1_CNTL -#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc -#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB0_WR_VC2_CNTL -#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc -#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB0_WR_VC3_CNTL -#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc -#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB0_WR_VC4_CNTL -#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc -#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB0_WR_VC5_CNTL -#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc -#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB0_WR_VC6_CNTL -#define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc -#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB0_WR_VC7_CNTL -#define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc -#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB0_WR_CNTL_MISC -#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 -#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 -#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd -#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 -#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 -#define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 -#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL -#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L -#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L -#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L -#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L -#define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L -//DAGB0_WR_TLB_CREDIT -#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 -#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 -#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa -#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf -#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 -#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 -#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL -#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L -#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L -#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L -#define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L -#define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L -//DAGB0_WR_DATA_CREDIT -#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 -#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 -#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 -#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 -#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL -#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L -#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L -#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L -//DAGB0_WR_MISC_CREDIT -#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 -#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 -#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 -#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 -#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL -#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L -#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L -#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L -//DAGB0_WRCLI_ASK_PENDING -#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 -#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB0_WRCLI_GO_PENDING -#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 -#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB0_WRCLI_GBLSEND_PENDING -#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 -#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB0_WRCLI_TLB_PENDING -#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 -#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB0_WRCLI_OARB_PENDING -#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 -#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB0_WRCLI_OSD_PENDING -#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 -#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB0_WRCLI_DBUS_ASK_PENDING -#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 -#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB0_WRCLI_DBUS_GO_PENDING -#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 -#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB0_DAGB_DLY -#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 -#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 -#define DAGB0_DAGB_DLY__POS__SHIFT 0x10 -#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL -#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L -#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L -//DAGB0_CNTL_MISC -#define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 -#define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 -#define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 -#define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 -#define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc -#define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf -#define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 -#define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 -#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 -#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e -#define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L -#define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L -#define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L -#define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L -#define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L -#define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L -#define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L -#define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L -#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L -#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L -//DAGB0_CNTL_MISC2 -#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 -#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 -#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 -#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 -#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 -#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 -#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 -#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 -#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 -#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 -#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa -#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L -#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L -#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L -#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L -#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L -#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L -#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L -#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L -#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L -#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L -#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L -//DAGB0_FIFO_EMPTY -#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 -#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL -//DAGB0_FIFO_FULL -#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 -#define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL -//DAGB0_WR_CREDITS_FULL -#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 -#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL -//DAGB0_RD_CREDITS_FULL -#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 -#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL -//DAGB0_PERFCOUNTER_LO -#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 -#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL -//DAGB0_PERFCOUNTER_HI -#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 -#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 -#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL -#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L -//DAGB0_PERFCOUNTER0_CFG -#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 -#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 -#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 -#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c -#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d -#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL -#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L -#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L -//DAGB0_PERFCOUNTER1_CFG -#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 -#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 -#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 -#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c -#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d -#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL -#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L -#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L -//DAGB0_PERFCOUNTER2_CFG -#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 -#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 -#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 -#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c -#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d -#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL -#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L -#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L -#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L -//DAGB0_PERFCOUNTER_RSLT_CNTL -#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 -#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 -#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 -#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 -#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 -#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a -#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL -#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L -#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L -#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L -//DAGB0_RESERVE0 -#define DAGB0_RESERVE0__RESERVE__SHIFT 0x0 -#define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL -//DAGB0_RESERVE1 -#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 -#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL -//DAGB0_RESERVE2 -#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 -#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL -//DAGB0_RESERVE3 -#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 -#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL -//DAGB0_RESERVE4 -#define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 -#define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL -//DAGB0_RESERVE5 -#define DAGB0_RESERVE5__RESERVE__SHIFT 0x0 -#define DAGB0_RESERVE5__RESERVE_MASK 0xFFFFFFFFL -//DAGB0_RESERVE6 -#define DAGB0_RESERVE6__RESERVE__SHIFT 0x0 -#define DAGB0_RESERVE6__RESERVE_MASK 0xFFFFFFFFL -//DAGB0_RESERVE7 -#define DAGB0_RESERVE7__RESERVE__SHIFT 0x0 -#define DAGB0_RESERVE7__RESERVE_MASK 0xFFFFFFFFL -//DAGB0_RESERVE8 -#define DAGB0_RESERVE8__RESERVE__SHIFT 0x0 -#define DAGB0_RESERVE8__RESERVE_MASK 0xFFFFFFFFL -//DAGB0_RESERVE9 -#define DAGB0_RESERVE9__RESERVE__SHIFT 0x0 -#define DAGB0_RESERVE9__RESERVE_MASK 0xFFFFFFFFL -//DAGB0_RESERVE10 -#define DAGB0_RESERVE10__RESERVE__SHIFT 0x0 -#define DAGB0_RESERVE10__RESERVE_MASK 0xFFFFFFFFL -//DAGB0_RESERVE11 -#define DAGB0_RESERVE11__RESERVE__SHIFT 0x0 -#define DAGB0_RESERVE11__RESERVE_MASK 0xFFFFFFFFL -//DAGB0_RESERVE12 -#define DAGB0_RESERVE12__RESERVE__SHIFT 0x0 -#define DAGB0_RESERVE12__RESERVE_MASK 0xFFFFFFFFL -//DAGB0_RESERVE13 -#define DAGB0_RESERVE13__RESERVE__SHIFT 0x0 -#define DAGB0_RESERVE13__RESERVE_MASK 0xFFFFFFFFL -//DAGB0_RESERVE14 -#define DAGB0_RESERVE14__RESERVE__SHIFT 0x0 -#define DAGB0_RESERVE14__RESERVE_MASK 0xFFFFFFFFL -//DAGB0_RESERVE15 -#define DAGB0_RESERVE15__RESERVE__SHIFT 0x0 -#define DAGB0_RESERVE15__RESERVE_MASK 0xFFFFFFFFL -//DAGB0_RESERVE16 -#define DAGB0_RESERVE16__RESERVE__SHIFT 0x0 -#define DAGB0_RESERVE16__RESERVE_MASK 0xFFFFFFFFL -//DAGB0_RESERVE17 -#define DAGB0_RESERVE17__RESERVE__SHIFT 0x0 -#define DAGB0_RESERVE17__RESERVE_MASK 0xFFFFFFFFL -//DAGB1_RDCLI0 -#define DAGB1_RDCLI0__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_RDCLI0__URG_HIGH__SHIFT 0x4 -#define DAGB1_RDCLI0__URG_LOW__SHIFT 0x8 -#define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_RDCLI0__MAX_BW__SHIFT 0xd -#define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_RDCLI0__MIN_BW__SHIFT 0x16 -#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_RDCLI0__MAX_OSD__SHIFT 0x1a -#define DAGB1_RDCLI0__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_RDCLI0__URG_HIGH_MASK 0x000000F0L -#define DAGB1_RDCLI0__URG_LOW_MASK 0x00000F00L -#define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_RDCLI0__MAX_BW_MASK 0x001FE000L -#define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_RDCLI0__MIN_BW_MASK 0x01C00000L -#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_RDCLI0__MAX_OSD_MASK 0xFC000000L -//DAGB1_RDCLI1 -#define DAGB1_RDCLI1__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_RDCLI1__URG_HIGH__SHIFT 0x4 -#define DAGB1_RDCLI1__URG_LOW__SHIFT 0x8 -#define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_RDCLI1__MAX_BW__SHIFT 0xd -#define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_RDCLI1__MIN_BW__SHIFT 0x16 -#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_RDCLI1__MAX_OSD__SHIFT 0x1a -#define DAGB1_RDCLI1__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_RDCLI1__URG_HIGH_MASK 0x000000F0L -#define DAGB1_RDCLI1__URG_LOW_MASK 0x00000F00L -#define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_RDCLI1__MAX_BW_MASK 0x001FE000L -#define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_RDCLI1__MIN_BW_MASK 0x01C00000L -#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_RDCLI1__MAX_OSD_MASK 0xFC000000L -//DAGB1_RDCLI2 -#define DAGB1_RDCLI2__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_RDCLI2__URG_HIGH__SHIFT 0x4 -#define DAGB1_RDCLI2__URG_LOW__SHIFT 0x8 -#define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_RDCLI2__MAX_BW__SHIFT 0xd -#define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_RDCLI2__MIN_BW__SHIFT 0x16 -#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_RDCLI2__MAX_OSD__SHIFT 0x1a -#define DAGB1_RDCLI2__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_RDCLI2__URG_HIGH_MASK 0x000000F0L -#define DAGB1_RDCLI2__URG_LOW_MASK 0x00000F00L -#define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_RDCLI2__MAX_BW_MASK 0x001FE000L -#define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_RDCLI2__MIN_BW_MASK 0x01C00000L -#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_RDCLI2__MAX_OSD_MASK 0xFC000000L -//DAGB1_RDCLI3 -#define DAGB1_RDCLI3__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_RDCLI3__URG_HIGH__SHIFT 0x4 -#define DAGB1_RDCLI3__URG_LOW__SHIFT 0x8 -#define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_RDCLI3__MAX_BW__SHIFT 0xd -#define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_RDCLI3__MIN_BW__SHIFT 0x16 -#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_RDCLI3__MAX_OSD__SHIFT 0x1a -#define DAGB1_RDCLI3__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_RDCLI3__URG_HIGH_MASK 0x000000F0L -#define DAGB1_RDCLI3__URG_LOW_MASK 0x00000F00L -#define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_RDCLI3__MAX_BW_MASK 0x001FE000L -#define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_RDCLI3__MIN_BW_MASK 0x01C00000L -#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_RDCLI3__MAX_OSD_MASK 0xFC000000L -//DAGB1_RDCLI4 -#define DAGB1_RDCLI4__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_RDCLI4__URG_HIGH__SHIFT 0x4 -#define DAGB1_RDCLI4__URG_LOW__SHIFT 0x8 -#define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_RDCLI4__MAX_BW__SHIFT 0xd -#define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_RDCLI4__MIN_BW__SHIFT 0x16 -#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_RDCLI4__MAX_OSD__SHIFT 0x1a -#define DAGB1_RDCLI4__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_RDCLI4__URG_HIGH_MASK 0x000000F0L -#define DAGB1_RDCLI4__URG_LOW_MASK 0x00000F00L -#define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_RDCLI4__MAX_BW_MASK 0x001FE000L -#define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_RDCLI4__MIN_BW_MASK 0x01C00000L -#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_RDCLI4__MAX_OSD_MASK 0xFC000000L -//DAGB1_RDCLI5 -#define DAGB1_RDCLI5__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_RDCLI5__URG_HIGH__SHIFT 0x4 -#define DAGB1_RDCLI5__URG_LOW__SHIFT 0x8 -#define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_RDCLI5__MAX_BW__SHIFT 0xd -#define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_RDCLI5__MIN_BW__SHIFT 0x16 -#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_RDCLI5__MAX_OSD__SHIFT 0x1a -#define DAGB1_RDCLI5__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_RDCLI5__URG_HIGH_MASK 0x000000F0L -#define DAGB1_RDCLI5__URG_LOW_MASK 0x00000F00L -#define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_RDCLI5__MAX_BW_MASK 0x001FE000L -#define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_RDCLI5__MIN_BW_MASK 0x01C00000L -#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_RDCLI5__MAX_OSD_MASK 0xFC000000L -//DAGB1_RDCLI6 -#define DAGB1_RDCLI6__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_RDCLI6__URG_HIGH__SHIFT 0x4 -#define DAGB1_RDCLI6__URG_LOW__SHIFT 0x8 -#define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_RDCLI6__MAX_BW__SHIFT 0xd -#define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_RDCLI6__MIN_BW__SHIFT 0x16 -#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_RDCLI6__MAX_OSD__SHIFT 0x1a -#define DAGB1_RDCLI6__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_RDCLI6__URG_HIGH_MASK 0x000000F0L -#define DAGB1_RDCLI6__URG_LOW_MASK 0x00000F00L -#define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_RDCLI6__MAX_BW_MASK 0x001FE000L -#define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_RDCLI6__MIN_BW_MASK 0x01C00000L -#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_RDCLI6__MAX_OSD_MASK 0xFC000000L -//DAGB1_RDCLI7 -#define DAGB1_RDCLI7__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_RDCLI7__URG_HIGH__SHIFT 0x4 -#define DAGB1_RDCLI7__URG_LOW__SHIFT 0x8 -#define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_RDCLI7__MAX_BW__SHIFT 0xd -#define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_RDCLI7__MIN_BW__SHIFT 0x16 -#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_RDCLI7__MAX_OSD__SHIFT 0x1a -#define DAGB1_RDCLI7__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_RDCLI7__URG_HIGH_MASK 0x000000F0L -#define DAGB1_RDCLI7__URG_LOW_MASK 0x00000F00L -#define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_RDCLI7__MAX_BW_MASK 0x001FE000L -#define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_RDCLI7__MIN_BW_MASK 0x01C00000L -#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_RDCLI7__MAX_OSD_MASK 0xFC000000L -//DAGB1_RDCLI8 -#define DAGB1_RDCLI8__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_RDCLI8__URG_HIGH__SHIFT 0x4 -#define DAGB1_RDCLI8__URG_LOW__SHIFT 0x8 -#define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_RDCLI8__MAX_BW__SHIFT 0xd -#define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_RDCLI8__MIN_BW__SHIFT 0x16 -#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_RDCLI8__MAX_OSD__SHIFT 0x1a -#define DAGB1_RDCLI8__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_RDCLI8__URG_HIGH_MASK 0x000000F0L -#define DAGB1_RDCLI8__URG_LOW_MASK 0x00000F00L -#define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_RDCLI8__MAX_BW_MASK 0x001FE000L -#define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_RDCLI8__MIN_BW_MASK 0x01C00000L -#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_RDCLI8__MAX_OSD_MASK 0xFC000000L -//DAGB1_RDCLI9 -#define DAGB1_RDCLI9__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_RDCLI9__URG_HIGH__SHIFT 0x4 -#define DAGB1_RDCLI9__URG_LOW__SHIFT 0x8 -#define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_RDCLI9__MAX_BW__SHIFT 0xd -#define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_RDCLI9__MIN_BW__SHIFT 0x16 -#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_RDCLI9__MAX_OSD__SHIFT 0x1a -#define DAGB1_RDCLI9__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_RDCLI9__URG_HIGH_MASK 0x000000F0L -#define DAGB1_RDCLI9__URG_LOW_MASK 0x00000F00L -#define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_RDCLI9__MAX_BW_MASK 0x001FE000L -#define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_RDCLI9__MIN_BW_MASK 0x01C00000L -#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_RDCLI9__MAX_OSD_MASK 0xFC000000L -//DAGB1_RDCLI10 -#define DAGB1_RDCLI10__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_RDCLI10__URG_HIGH__SHIFT 0x4 -#define DAGB1_RDCLI10__URG_LOW__SHIFT 0x8 -#define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_RDCLI10__MAX_BW__SHIFT 0xd -#define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_RDCLI10__MIN_BW__SHIFT 0x16 -#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_RDCLI10__MAX_OSD__SHIFT 0x1a -#define DAGB1_RDCLI10__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_RDCLI10__URG_HIGH_MASK 0x000000F0L -#define DAGB1_RDCLI10__URG_LOW_MASK 0x00000F00L -#define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_RDCLI10__MAX_BW_MASK 0x001FE000L -#define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_RDCLI10__MIN_BW_MASK 0x01C00000L -#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_RDCLI10__MAX_OSD_MASK 0xFC000000L -//DAGB1_RDCLI11 -#define DAGB1_RDCLI11__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_RDCLI11__URG_HIGH__SHIFT 0x4 -#define DAGB1_RDCLI11__URG_LOW__SHIFT 0x8 -#define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_RDCLI11__MAX_BW__SHIFT 0xd -#define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_RDCLI11__MIN_BW__SHIFT 0x16 -#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_RDCLI11__MAX_OSD__SHIFT 0x1a -#define DAGB1_RDCLI11__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_RDCLI11__URG_HIGH_MASK 0x000000F0L -#define DAGB1_RDCLI11__URG_LOW_MASK 0x00000F00L -#define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_RDCLI11__MAX_BW_MASK 0x001FE000L -#define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_RDCLI11__MIN_BW_MASK 0x01C00000L -#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_RDCLI11__MAX_OSD_MASK 0xFC000000L -//DAGB1_RDCLI12 -#define DAGB1_RDCLI12__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_RDCLI12__URG_HIGH__SHIFT 0x4 -#define DAGB1_RDCLI12__URG_LOW__SHIFT 0x8 -#define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_RDCLI12__MAX_BW__SHIFT 0xd -#define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_RDCLI12__MIN_BW__SHIFT 0x16 -#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_RDCLI12__MAX_OSD__SHIFT 0x1a -#define DAGB1_RDCLI12__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_RDCLI12__URG_HIGH_MASK 0x000000F0L -#define DAGB1_RDCLI12__URG_LOW_MASK 0x00000F00L -#define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_RDCLI12__MAX_BW_MASK 0x001FE000L -#define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_RDCLI12__MIN_BW_MASK 0x01C00000L -#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_RDCLI12__MAX_OSD_MASK 0xFC000000L -//DAGB1_RDCLI13 -#define DAGB1_RDCLI13__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_RDCLI13__URG_HIGH__SHIFT 0x4 -#define DAGB1_RDCLI13__URG_LOW__SHIFT 0x8 -#define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_RDCLI13__MAX_BW__SHIFT 0xd -#define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_RDCLI13__MIN_BW__SHIFT 0x16 -#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_RDCLI13__MAX_OSD__SHIFT 0x1a -#define DAGB1_RDCLI13__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_RDCLI13__URG_HIGH_MASK 0x000000F0L -#define DAGB1_RDCLI13__URG_LOW_MASK 0x00000F00L -#define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_RDCLI13__MAX_BW_MASK 0x001FE000L -#define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_RDCLI13__MIN_BW_MASK 0x01C00000L -#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_RDCLI13__MAX_OSD_MASK 0xFC000000L -//DAGB1_RDCLI14 -#define DAGB1_RDCLI14__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_RDCLI14__URG_HIGH__SHIFT 0x4 -#define DAGB1_RDCLI14__URG_LOW__SHIFT 0x8 -#define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_RDCLI14__MAX_BW__SHIFT 0xd -#define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_RDCLI14__MIN_BW__SHIFT 0x16 -#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_RDCLI14__MAX_OSD__SHIFT 0x1a -#define DAGB1_RDCLI14__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_RDCLI14__URG_HIGH_MASK 0x000000F0L -#define DAGB1_RDCLI14__URG_LOW_MASK 0x00000F00L -#define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_RDCLI14__MAX_BW_MASK 0x001FE000L -#define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_RDCLI14__MIN_BW_MASK 0x01C00000L -#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_RDCLI14__MAX_OSD_MASK 0xFC000000L -//DAGB1_RDCLI15 -#define DAGB1_RDCLI15__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_RDCLI15__URG_HIGH__SHIFT 0x4 -#define DAGB1_RDCLI15__URG_LOW__SHIFT 0x8 -#define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_RDCLI15__MAX_BW__SHIFT 0xd -#define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_RDCLI15__MIN_BW__SHIFT 0x16 -#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_RDCLI15__MAX_OSD__SHIFT 0x1a -#define DAGB1_RDCLI15__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_RDCLI15__URG_HIGH_MASK 0x000000F0L -#define DAGB1_RDCLI15__URG_LOW_MASK 0x00000F00L -#define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_RDCLI15__MAX_BW_MASK 0x001FE000L -#define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_RDCLI15__MIN_BW_MASK 0x01C00000L -#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_RDCLI15__MAX_OSD_MASK 0xFC000000L -//DAGB1_RD_CNTL -#define DAGB1_RD_CNTL__SCLK_FREQ__SHIFT 0x0 -#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 -#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa -#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 -#define DAGB1_RD_CNTL__IO_LEVEL__SHIFT 0x11 -#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 -#define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 -#define DAGB1_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL -#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L -#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L -#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L -#define DAGB1_RD_CNTL__IO_LEVEL_MASK 0x000E0000L -#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L -#define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L -//DAGB1_RD_GMI_CNTL -#define DAGB1_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 -#define DAGB1_RD_GMI_CNTL__LEVEL__SHIFT 0x6 -#define DAGB1_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 -#define DAGB1_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd -#define DAGB1_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL -#define DAGB1_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L -#define DAGB1_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L -#define DAGB1_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L -//DAGB1_RD_ADDR_DAGB -#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 -#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 -#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 -#define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 -#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L -#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L -#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L -#define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L -//DAGB1_RD_OUTPUT_DAGB_MAX_BURST -#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 -#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 -#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 -#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc -#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 -#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 -#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 -#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c -#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL -#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L -#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L -#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L -#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L -#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L -#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L -#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L -//DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER -#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 -#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 -#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 -#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc -#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 -#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 -#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 -#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c -#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL -#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L -#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L -#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L -#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L -#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L -#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L -#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L -//DAGB1_RD_CGTT_CLK_CTRL -#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 -#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b -#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c -#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d -#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e -#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f -#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L -#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L -#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L -#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L -#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L -#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L -//DAGB1_L1TLB_RD_CGTT_CLK_CTRL -#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 -#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b -#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c -#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d -#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e -#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f -#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L -#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L -#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L -#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L -#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L -#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L -//DAGB1_ATCVM_RD_CGTT_CLK_CTRL -#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 -#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b -#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c -#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d -#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e -#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f -#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L -#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L -#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L -#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L -#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L -#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L -//DAGB1_RD_ADDR_DAGB_MAX_BURST0 -#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 -#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 -#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 -#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc -#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 -#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 -#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 -#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c -#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL -#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L -#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L -#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L -#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L -#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L -#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L -#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L -//DAGB1_RD_ADDR_DAGB_LAZY_TIMER0 -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L -//DAGB1_RD_ADDR_DAGB_MAX_BURST1 -#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 -#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 -#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 -#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc -#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 -#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 -#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 -#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c -#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL -#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L -#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L -#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L -#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L -#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L -#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L -#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L -//DAGB1_RD_ADDR_DAGB_LAZY_TIMER1 -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L -#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L -//DAGB1_RD_VC0_CNTL -#define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB1_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT 0xc -#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB1_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB1_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB1_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB1_RD_VC1_CNTL -#define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB1_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT 0xc -#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB1_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB1_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB1_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB1_RD_VC2_CNTL -#define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB1_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT 0xc -#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB1_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB1_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB1_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB1_RD_VC3_CNTL -#define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB1_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT 0xc -#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB1_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB1_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB1_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB1_RD_VC4_CNTL -#define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB1_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT 0xc -#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB1_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB1_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB1_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB1_RD_VC5_CNTL -#define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB1_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT 0xc -#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB1_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB1_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB1_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB1_RD_VC6_CNTL -#define DAGB1_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB1_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB1_RD_VC6_CNTL__MAX_BW__SHIFT 0xc -#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB1_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB1_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB1_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB1_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB1_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB1_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB1_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB1_RD_VC7_CNTL -#define DAGB1_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB1_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB1_RD_VC7_CNTL__MAX_BW__SHIFT 0xc -#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB1_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB1_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB1_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB1_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB1_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB1_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB1_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB1_RD_CNTL_MISC -#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 -#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 -#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd -#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 -#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 -#define DAGB1_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 -#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL -#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L -#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L -#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L -#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L -#define DAGB1_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L -//DAGB1_RD_TLB_CREDIT -#define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT 0x0 -#define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT 0x5 -#define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa -#define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT 0xf -#define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT 0x14 -#define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT 0x19 -#define DAGB1_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL -#define DAGB1_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L -#define DAGB1_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L -#define DAGB1_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L -#define DAGB1_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L -#define DAGB1_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L -//DAGB1_RDCLI_ASK_PENDING -#define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 -#define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB1_RDCLI_GO_PENDING -#define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 -#define DAGB1_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB1_RDCLI_GBLSEND_PENDING -#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 -#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB1_RDCLI_TLB_PENDING -#define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 -#define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB1_RDCLI_OARB_PENDING -#define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 -#define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB1_RDCLI_OSD_PENDING -#define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 -#define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB1_WRCLI0 -#define DAGB1_WRCLI0__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_WRCLI0__URG_HIGH__SHIFT 0x4 -#define DAGB1_WRCLI0__URG_LOW__SHIFT 0x8 -#define DAGB1_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_WRCLI0__MAX_BW__SHIFT 0xd -#define DAGB1_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_WRCLI0__MIN_BW__SHIFT 0x16 -#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_WRCLI0__MAX_OSD__SHIFT 0x1a -#define DAGB1_WRCLI0__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_WRCLI0__URG_HIGH_MASK 0x000000F0L -#define DAGB1_WRCLI0__URG_LOW_MASK 0x00000F00L -#define DAGB1_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_WRCLI0__MAX_BW_MASK 0x001FE000L -#define DAGB1_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_WRCLI0__MIN_BW_MASK 0x01C00000L -#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_WRCLI0__MAX_OSD_MASK 0xFC000000L -//DAGB1_WRCLI1 -#define DAGB1_WRCLI1__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_WRCLI1__URG_HIGH__SHIFT 0x4 -#define DAGB1_WRCLI1__URG_LOW__SHIFT 0x8 -#define DAGB1_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_WRCLI1__MAX_BW__SHIFT 0xd -#define DAGB1_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_WRCLI1__MIN_BW__SHIFT 0x16 -#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_WRCLI1__MAX_OSD__SHIFT 0x1a -#define DAGB1_WRCLI1__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_WRCLI1__URG_HIGH_MASK 0x000000F0L -#define DAGB1_WRCLI1__URG_LOW_MASK 0x00000F00L -#define DAGB1_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_WRCLI1__MAX_BW_MASK 0x001FE000L -#define DAGB1_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_WRCLI1__MIN_BW_MASK 0x01C00000L -#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_WRCLI1__MAX_OSD_MASK 0xFC000000L -//DAGB1_WRCLI2 -#define DAGB1_WRCLI2__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_WRCLI2__URG_HIGH__SHIFT 0x4 -#define DAGB1_WRCLI2__URG_LOW__SHIFT 0x8 -#define DAGB1_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_WRCLI2__MAX_BW__SHIFT 0xd -#define DAGB1_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_WRCLI2__MIN_BW__SHIFT 0x16 -#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_WRCLI2__MAX_OSD__SHIFT 0x1a -#define DAGB1_WRCLI2__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_WRCLI2__URG_HIGH_MASK 0x000000F0L -#define DAGB1_WRCLI2__URG_LOW_MASK 0x00000F00L -#define DAGB1_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_WRCLI2__MAX_BW_MASK 0x001FE000L -#define DAGB1_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_WRCLI2__MIN_BW_MASK 0x01C00000L -#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_WRCLI2__MAX_OSD_MASK 0xFC000000L -//DAGB1_WRCLI3 -#define DAGB1_WRCLI3__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_WRCLI3__URG_HIGH__SHIFT 0x4 -#define DAGB1_WRCLI3__URG_LOW__SHIFT 0x8 -#define DAGB1_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_WRCLI3__MAX_BW__SHIFT 0xd -#define DAGB1_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_WRCLI3__MIN_BW__SHIFT 0x16 -#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_WRCLI3__MAX_OSD__SHIFT 0x1a -#define DAGB1_WRCLI3__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_WRCLI3__URG_HIGH_MASK 0x000000F0L -#define DAGB1_WRCLI3__URG_LOW_MASK 0x00000F00L -#define DAGB1_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_WRCLI3__MAX_BW_MASK 0x001FE000L -#define DAGB1_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_WRCLI3__MIN_BW_MASK 0x01C00000L -#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_WRCLI3__MAX_OSD_MASK 0xFC000000L -//DAGB1_WRCLI4 -#define DAGB1_WRCLI4__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_WRCLI4__URG_HIGH__SHIFT 0x4 -#define DAGB1_WRCLI4__URG_LOW__SHIFT 0x8 -#define DAGB1_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_WRCLI4__MAX_BW__SHIFT 0xd -#define DAGB1_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_WRCLI4__MIN_BW__SHIFT 0x16 -#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_WRCLI4__MAX_OSD__SHIFT 0x1a -#define DAGB1_WRCLI4__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_WRCLI4__URG_HIGH_MASK 0x000000F0L -#define DAGB1_WRCLI4__URG_LOW_MASK 0x00000F00L -#define DAGB1_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_WRCLI4__MAX_BW_MASK 0x001FE000L -#define DAGB1_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_WRCLI4__MIN_BW_MASK 0x01C00000L -#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_WRCLI4__MAX_OSD_MASK 0xFC000000L -//DAGB1_WRCLI5 -#define DAGB1_WRCLI5__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_WRCLI5__URG_HIGH__SHIFT 0x4 -#define DAGB1_WRCLI5__URG_LOW__SHIFT 0x8 -#define DAGB1_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_WRCLI5__MAX_BW__SHIFT 0xd -#define DAGB1_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_WRCLI5__MIN_BW__SHIFT 0x16 -#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_WRCLI5__MAX_OSD__SHIFT 0x1a -#define DAGB1_WRCLI5__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_WRCLI5__URG_HIGH_MASK 0x000000F0L -#define DAGB1_WRCLI5__URG_LOW_MASK 0x00000F00L -#define DAGB1_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_WRCLI5__MAX_BW_MASK 0x001FE000L -#define DAGB1_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_WRCLI5__MIN_BW_MASK 0x01C00000L -#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_WRCLI5__MAX_OSD_MASK 0xFC000000L -//DAGB1_WRCLI6 -#define DAGB1_WRCLI6__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_WRCLI6__URG_HIGH__SHIFT 0x4 -#define DAGB1_WRCLI6__URG_LOW__SHIFT 0x8 -#define DAGB1_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_WRCLI6__MAX_BW__SHIFT 0xd -#define DAGB1_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_WRCLI6__MIN_BW__SHIFT 0x16 -#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_WRCLI6__MAX_OSD__SHIFT 0x1a -#define DAGB1_WRCLI6__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_WRCLI6__URG_HIGH_MASK 0x000000F0L -#define DAGB1_WRCLI6__URG_LOW_MASK 0x00000F00L -#define DAGB1_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_WRCLI6__MAX_BW_MASK 0x001FE000L -#define DAGB1_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_WRCLI6__MIN_BW_MASK 0x01C00000L -#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_WRCLI6__MAX_OSD_MASK 0xFC000000L -//DAGB1_WRCLI7 -#define DAGB1_WRCLI7__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_WRCLI7__URG_HIGH__SHIFT 0x4 -#define DAGB1_WRCLI7__URG_LOW__SHIFT 0x8 -#define DAGB1_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_WRCLI7__MAX_BW__SHIFT 0xd -#define DAGB1_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_WRCLI7__MIN_BW__SHIFT 0x16 -#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_WRCLI7__MAX_OSD__SHIFT 0x1a -#define DAGB1_WRCLI7__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_WRCLI7__URG_HIGH_MASK 0x000000F0L -#define DAGB1_WRCLI7__URG_LOW_MASK 0x00000F00L -#define DAGB1_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_WRCLI7__MAX_BW_MASK 0x001FE000L -#define DAGB1_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_WRCLI7__MIN_BW_MASK 0x01C00000L -#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_WRCLI7__MAX_OSD_MASK 0xFC000000L -//DAGB1_WRCLI8 -#define DAGB1_WRCLI8__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_WRCLI8__URG_HIGH__SHIFT 0x4 -#define DAGB1_WRCLI8__URG_LOW__SHIFT 0x8 -#define DAGB1_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_WRCLI8__MAX_BW__SHIFT 0xd -#define DAGB1_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_WRCLI8__MIN_BW__SHIFT 0x16 -#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_WRCLI8__MAX_OSD__SHIFT 0x1a -#define DAGB1_WRCLI8__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_WRCLI8__URG_HIGH_MASK 0x000000F0L -#define DAGB1_WRCLI8__URG_LOW_MASK 0x00000F00L -#define DAGB1_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_WRCLI8__MAX_BW_MASK 0x001FE000L -#define DAGB1_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_WRCLI8__MIN_BW_MASK 0x01C00000L -#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_WRCLI8__MAX_OSD_MASK 0xFC000000L -//DAGB1_WRCLI9 -#define DAGB1_WRCLI9__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_WRCLI9__URG_HIGH__SHIFT 0x4 -#define DAGB1_WRCLI9__URG_LOW__SHIFT 0x8 -#define DAGB1_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_WRCLI9__MAX_BW__SHIFT 0xd -#define DAGB1_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_WRCLI9__MIN_BW__SHIFT 0x16 -#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_WRCLI9__MAX_OSD__SHIFT 0x1a -#define DAGB1_WRCLI9__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_WRCLI9__URG_HIGH_MASK 0x000000F0L -#define DAGB1_WRCLI9__URG_LOW_MASK 0x00000F00L -#define DAGB1_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_WRCLI9__MAX_BW_MASK 0x001FE000L -#define DAGB1_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_WRCLI9__MIN_BW_MASK 0x01C00000L -#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_WRCLI9__MAX_OSD_MASK 0xFC000000L -//DAGB1_WRCLI10 -#define DAGB1_WRCLI10__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_WRCLI10__URG_HIGH__SHIFT 0x4 -#define DAGB1_WRCLI10__URG_LOW__SHIFT 0x8 -#define DAGB1_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_WRCLI10__MAX_BW__SHIFT 0xd -#define DAGB1_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_WRCLI10__MIN_BW__SHIFT 0x16 -#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_WRCLI10__MAX_OSD__SHIFT 0x1a -#define DAGB1_WRCLI10__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_WRCLI10__URG_HIGH_MASK 0x000000F0L -#define DAGB1_WRCLI10__URG_LOW_MASK 0x00000F00L -#define DAGB1_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_WRCLI10__MAX_BW_MASK 0x001FE000L -#define DAGB1_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_WRCLI10__MIN_BW_MASK 0x01C00000L -#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_WRCLI10__MAX_OSD_MASK 0xFC000000L -//DAGB1_WRCLI11 -#define DAGB1_WRCLI11__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_WRCLI11__URG_HIGH__SHIFT 0x4 -#define DAGB1_WRCLI11__URG_LOW__SHIFT 0x8 -#define DAGB1_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_WRCLI11__MAX_BW__SHIFT 0xd -#define DAGB1_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_WRCLI11__MIN_BW__SHIFT 0x16 -#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_WRCLI11__MAX_OSD__SHIFT 0x1a -#define DAGB1_WRCLI11__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_WRCLI11__URG_HIGH_MASK 0x000000F0L -#define DAGB1_WRCLI11__URG_LOW_MASK 0x00000F00L -#define DAGB1_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_WRCLI11__MAX_BW_MASK 0x001FE000L -#define DAGB1_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_WRCLI11__MIN_BW_MASK 0x01C00000L -#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_WRCLI11__MAX_OSD_MASK 0xFC000000L -//DAGB1_WRCLI12 -#define DAGB1_WRCLI12__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_WRCLI12__URG_HIGH__SHIFT 0x4 -#define DAGB1_WRCLI12__URG_LOW__SHIFT 0x8 -#define DAGB1_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_WRCLI12__MAX_BW__SHIFT 0xd -#define DAGB1_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_WRCLI12__MIN_BW__SHIFT 0x16 -#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_WRCLI12__MAX_OSD__SHIFT 0x1a -#define DAGB1_WRCLI12__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_WRCLI12__URG_HIGH_MASK 0x000000F0L -#define DAGB1_WRCLI12__URG_LOW_MASK 0x00000F00L -#define DAGB1_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_WRCLI12__MAX_BW_MASK 0x001FE000L -#define DAGB1_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_WRCLI12__MIN_BW_MASK 0x01C00000L -#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_WRCLI12__MAX_OSD_MASK 0xFC000000L -//DAGB1_WRCLI13 -#define DAGB1_WRCLI13__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_WRCLI13__URG_HIGH__SHIFT 0x4 -#define DAGB1_WRCLI13__URG_LOW__SHIFT 0x8 -#define DAGB1_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_WRCLI13__MAX_BW__SHIFT 0xd -#define DAGB1_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_WRCLI13__MIN_BW__SHIFT 0x16 -#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_WRCLI13__MAX_OSD__SHIFT 0x1a -#define DAGB1_WRCLI13__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_WRCLI13__URG_HIGH_MASK 0x000000F0L -#define DAGB1_WRCLI13__URG_LOW_MASK 0x00000F00L -#define DAGB1_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_WRCLI13__MAX_BW_MASK 0x001FE000L -#define DAGB1_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_WRCLI13__MIN_BW_MASK 0x01C00000L -#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_WRCLI13__MAX_OSD_MASK 0xFC000000L -//DAGB1_WRCLI14 -#define DAGB1_WRCLI14__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_WRCLI14__URG_HIGH__SHIFT 0x4 -#define DAGB1_WRCLI14__URG_LOW__SHIFT 0x8 -#define DAGB1_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_WRCLI14__MAX_BW__SHIFT 0xd -#define DAGB1_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_WRCLI14__MIN_BW__SHIFT 0x16 -#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_WRCLI14__MAX_OSD__SHIFT 0x1a -#define DAGB1_WRCLI14__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_WRCLI14__URG_HIGH_MASK 0x000000F0L -#define DAGB1_WRCLI14__URG_LOW_MASK 0x00000F00L -#define DAGB1_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_WRCLI14__MAX_BW_MASK 0x001FE000L -#define DAGB1_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_WRCLI14__MIN_BW_MASK 0x01C00000L -#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_WRCLI14__MAX_OSD_MASK 0xFC000000L -//DAGB1_WRCLI15 -#define DAGB1_WRCLI15__VIRT_CHAN__SHIFT 0x0 -#define DAGB1_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 -#define DAGB1_WRCLI15__URG_HIGH__SHIFT 0x4 -#define DAGB1_WRCLI15__URG_LOW__SHIFT 0x8 -#define DAGB1_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc -#define DAGB1_WRCLI15__MAX_BW__SHIFT 0xd -#define DAGB1_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 -#define DAGB1_WRCLI15__MIN_BW__SHIFT 0x16 -#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 -#define DAGB1_WRCLI15__MAX_OSD__SHIFT 0x1a -#define DAGB1_WRCLI15__VIRT_CHAN_MASK 0x00000007L -#define DAGB1_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L -#define DAGB1_WRCLI15__URG_HIGH_MASK 0x000000F0L -#define DAGB1_WRCLI15__URG_LOW_MASK 0x00000F00L -#define DAGB1_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L -#define DAGB1_WRCLI15__MAX_BW_MASK 0x001FE000L -#define DAGB1_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L -#define DAGB1_WRCLI15__MIN_BW_MASK 0x01C00000L -#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L -#define DAGB1_WRCLI15__MAX_OSD_MASK 0xFC000000L -//DAGB1_WR_CNTL -#define DAGB1_WR_CNTL__SCLK_FREQ__SHIFT 0x0 -#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 -#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa -#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 -#define DAGB1_WR_CNTL__IO_LEVEL__SHIFT 0x11 -#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 -#define DAGB1_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 -#define DAGB1_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL -#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L -#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L -#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L -#define DAGB1_WR_CNTL__IO_LEVEL_MASK 0x000E0000L -#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L -#define DAGB1_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L -//DAGB1_WR_GMI_CNTL -#define DAGB1_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 -#define DAGB1_WR_GMI_CNTL__LEVEL__SHIFT 0x6 -#define DAGB1_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 -#define DAGB1_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd -#define DAGB1_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL -#define DAGB1_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L -#define DAGB1_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L -#define DAGB1_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L -//DAGB1_WR_ADDR_DAGB -#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 -#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 -#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 -#define DAGB1_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 -#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L -#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L -#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L -#define DAGB1_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L -//DAGB1_WR_OUTPUT_DAGB_MAX_BURST -#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 -#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 -#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 -#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc -#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 -#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 -#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 -#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c -#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL -#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L -#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L -#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L -#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L -#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L -#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L -#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L -//DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER -#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 -#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 -#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 -#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc -#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 -#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 -#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 -#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c -#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL -#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L -#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L -#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L -#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L -#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L -#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L -#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L -//DAGB1_WR_CGTT_CLK_CTRL -#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 -#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b -#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c -#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d -#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e -#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f -#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L -#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L -#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L -#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L -#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L -#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L -//DAGB1_L1TLB_WR_CGTT_CLK_CTRL -#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 -#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b -#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c -#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d -#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e -#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f -#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L -#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L -#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L -#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L -#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L -#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L -//DAGB1_ATCVM_WR_CGTT_CLK_CTRL -#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 -#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b -#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c -#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d -#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e -#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f -#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L -#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L -#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L -#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L -#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L -#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L -//DAGB1_WR_ADDR_DAGB_MAX_BURST0 -#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 -#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 -#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 -#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc -#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 -#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 -#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 -#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c -#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL -#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L -#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L -#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L -#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L -#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L -#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L -#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L -//DAGB1_WR_ADDR_DAGB_LAZY_TIMER0 -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L -//DAGB1_WR_ADDR_DAGB_MAX_BURST1 -#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 -#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 -#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 -#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc -#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 -#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 -#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 -#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c -#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL -#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L -#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L -#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L -#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L -#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L -#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L -#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L -//DAGB1_WR_ADDR_DAGB_LAZY_TIMER1 -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L -#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L -//DAGB1_WR_DATA_DAGB -#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 -#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 -#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 -#define DAGB1_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 -#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L -#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L -#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L -#define DAGB1_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L -//DAGB1_WR_DATA_DAGB_MAX_BURST0 -#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 -#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 -#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 -#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc -#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 -#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 -#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 -#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c -#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL -#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L -#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L -#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L -#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L -#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L -#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L -#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L -//DAGB1_WR_DATA_DAGB_LAZY_TIMER0 -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L -//DAGB1_WR_DATA_DAGB_MAX_BURST1 -#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 -#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 -#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 -#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc -#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 -#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 -#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 -#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c -#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL -#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L -#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L -#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L -#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L -#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L -#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L -#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L -//DAGB1_WR_DATA_DAGB_LAZY_TIMER1 -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L -#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L -//DAGB1_WR_VC0_CNTL -#define DAGB1_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB1_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB1_WR_VC0_CNTL__MAX_BW__SHIFT 0xc -#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB1_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB1_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB1_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB1_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB1_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB1_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB1_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB1_WR_VC1_CNTL -#define DAGB1_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB1_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB1_WR_VC1_CNTL__MAX_BW__SHIFT 0xc -#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB1_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB1_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB1_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB1_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB1_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB1_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB1_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB1_WR_VC2_CNTL -#define DAGB1_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB1_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB1_WR_VC2_CNTL__MAX_BW__SHIFT 0xc -#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB1_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB1_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB1_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB1_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB1_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB1_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB1_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB1_WR_VC3_CNTL -#define DAGB1_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB1_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB1_WR_VC3_CNTL__MAX_BW__SHIFT 0xc -#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB1_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB1_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB1_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB1_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB1_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB1_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB1_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB1_WR_VC4_CNTL -#define DAGB1_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB1_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB1_WR_VC4_CNTL__MAX_BW__SHIFT 0xc -#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB1_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB1_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB1_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB1_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB1_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB1_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB1_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB1_WR_VC5_CNTL -#define DAGB1_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB1_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB1_WR_VC5_CNTL__MAX_BW__SHIFT 0xc -#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB1_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB1_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB1_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB1_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB1_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB1_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB1_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB1_WR_VC6_CNTL -#define DAGB1_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB1_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB1_WR_VC6_CNTL__MAX_BW__SHIFT 0xc -#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB1_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB1_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB1_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB1_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB1_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB1_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB1_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB1_WR_VC7_CNTL -#define DAGB1_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 -#define DAGB1_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 -#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb -#define DAGB1_WR_VC7_CNTL__MAX_BW__SHIFT 0xc -#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 -#define DAGB1_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 -#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 -#define DAGB1_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 -#define DAGB1_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL -#define DAGB1_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L -#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L -#define DAGB1_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L -#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L -#define DAGB1_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L -#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L -#define DAGB1_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L -//DAGB1_WR_CNTL_MISC -#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 -#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 -#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd -#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 -#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 -#define DAGB1_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 -#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL -#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L -#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L -#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L -#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L -#define DAGB1_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L -//DAGB1_WR_TLB_CREDIT -#define DAGB1_WR_TLB_CREDIT__TLB0__SHIFT 0x0 -#define DAGB1_WR_TLB_CREDIT__TLB1__SHIFT 0x5 -#define DAGB1_WR_TLB_CREDIT__TLB2__SHIFT 0xa -#define DAGB1_WR_TLB_CREDIT__TLB3__SHIFT 0xf -#define DAGB1_WR_TLB_CREDIT__TLB4__SHIFT 0x14 -#define DAGB1_WR_TLB_CREDIT__TLB5__SHIFT 0x19 -#define DAGB1_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL -#define DAGB1_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L -#define DAGB1_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L -#define DAGB1_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L -#define DAGB1_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L -#define DAGB1_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L -//DAGB1_WR_DATA_CREDIT -#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 -#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 -#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 -#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 -#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL -#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L -#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L -#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L -//DAGB1_WR_MISC_CREDIT -#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 -#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 -#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 -#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 -#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL -#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L -#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L -#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L -//DAGB1_WRCLI_ASK_PENDING -#define DAGB1_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 -#define DAGB1_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB1_WRCLI_GO_PENDING -#define DAGB1_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 -#define DAGB1_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB1_WRCLI_GBLSEND_PENDING -#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 -#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB1_WRCLI_TLB_PENDING -#define DAGB1_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 -#define DAGB1_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB1_WRCLI_OARB_PENDING -#define DAGB1_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 -#define DAGB1_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB1_WRCLI_OSD_PENDING -#define DAGB1_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 -#define DAGB1_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB1_WRCLI_DBUS_ASK_PENDING -#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 -#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB1_WRCLI_DBUS_GO_PENDING -#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 -#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL -//DAGB1_DAGB_DLY -#define DAGB1_DAGB_DLY__DLY__SHIFT 0x0 -#define DAGB1_DAGB_DLY__CLI__SHIFT 0x8 -#define DAGB1_DAGB_DLY__POS__SHIFT 0x10 -#define DAGB1_DAGB_DLY__DLY_MASK 0x000000FFL -#define DAGB1_DAGB_DLY__CLI_MASK 0x0000FF00L -#define DAGB1_DAGB_DLY__POS_MASK 0x000F0000L -//DAGB1_CNTL_MISC -#define DAGB1_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 -#define DAGB1_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 -#define DAGB1_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 -#define DAGB1_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 -#define DAGB1_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc -#define DAGB1_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf -#define DAGB1_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 -#define DAGB1_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 -#define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 -#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e -#define DAGB1_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L -#define DAGB1_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L -#define DAGB1_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L -#define DAGB1_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L -#define DAGB1_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L -#define DAGB1_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L -#define DAGB1_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L -#define DAGB1_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L -#define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L -#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L -//DAGB1_CNTL_MISC2 -#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 -#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 -#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 -#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 -#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 -#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 -#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 -#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 -#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 -#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 -#define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0xa -#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L -#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L -#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L -#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L -#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L -#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L -#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L -#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L -#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L -#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L -#define DAGB1_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L -//DAGB1_FIFO_EMPTY -#define DAGB1_FIFO_EMPTY__EMPTY__SHIFT 0x0 -#define DAGB1_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL -//DAGB1_FIFO_FULL -#define DAGB1_FIFO_FULL__FULL__SHIFT 0x0 -#define DAGB1_FIFO_FULL__FULL_MASK 0x007FFFFFL -//DAGB1_WR_CREDITS_FULL -#define DAGB1_WR_CREDITS_FULL__FULL__SHIFT 0x0 -#define DAGB1_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL -//DAGB1_RD_CREDITS_FULL -#define DAGB1_RD_CREDITS_FULL__FULL__SHIFT 0x0 -#define DAGB1_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL -//DAGB1_PERFCOUNTER_LO -#define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 -#define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL -//DAGB1_PERFCOUNTER_HI -#define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 -#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 -#define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL -#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L -//DAGB1_PERFCOUNTER0_CFG -#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 -#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 -#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 -#define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c -#define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d -#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL -#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L -#define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L -//DAGB1_PERFCOUNTER1_CFG -#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 -#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 -#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 -#define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c -#define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d -#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL -#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L -#define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L -//DAGB1_PERFCOUNTER2_CFG -#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 -#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 -#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 -#define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c -#define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d -#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL -#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L -#define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L -#define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L -//DAGB1_PERFCOUNTER_RSLT_CNTL -#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 -#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 -#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 -#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 -#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 -#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a -#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL -#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L -#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L -#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L -//DAGB1_RESERVE0 -#define DAGB1_RESERVE0__RESERVE__SHIFT 0x0 -#define DAGB1_RESERVE0__RESERVE_MASK 0xFFFFFFFFL -//DAGB1_RESERVE1 -#define DAGB1_RESERVE1__RESERVE__SHIFT 0x0 -#define DAGB1_RESERVE1__RESERVE_MASK 0xFFFFFFFFL -//DAGB1_RESERVE2 -#define DAGB1_RESERVE2__RESERVE__SHIFT 0x0 -#define DAGB1_RESERVE2__RESERVE_MASK 0xFFFFFFFFL -//DAGB1_RESERVE3 -#define DAGB1_RESERVE3__RESERVE__SHIFT 0x0 -#define DAGB1_RESERVE3__RESERVE_MASK 0xFFFFFFFFL -//DAGB1_RESERVE4 -#define DAGB1_RESERVE4__RESERVE__SHIFT 0x0 -#define DAGB1_RESERVE4__RESERVE_MASK 0xFFFFFFFFL -//DAGB1_RESERVE5 -#define DAGB1_RESERVE5__RESERVE__SHIFT 0x0 -#define DAGB1_RESERVE5__RESERVE_MASK 0xFFFFFFFFL -//DAGB1_RESERVE6 -#define DAGB1_RESERVE6__RESERVE__SHIFT 0x0 -#define DAGB1_RESERVE6__RESERVE_MASK 0xFFFFFFFFL -//DAGB1_RESERVE7 -#define DAGB1_RESERVE7__RESERVE__SHIFT 0x0 -#define DAGB1_RESERVE7__RESERVE_MASK 0xFFFFFFFFL -//DAGB1_RESERVE8 -#define DAGB1_RESERVE8__RESERVE__SHIFT 0x0 -#define DAGB1_RESERVE8__RESERVE_MASK 0xFFFFFFFFL -//DAGB1_RESERVE9 -#define DAGB1_RESERVE9__RESERVE__SHIFT 0x0 -#define DAGB1_RESERVE9__RESERVE_MASK 0xFFFFFFFFL -//DAGB1_RESERVE10 -#define DAGB1_RESERVE10__RESERVE__SHIFT 0x0 -#define DAGB1_RESERVE10__RESERVE_MASK 0xFFFFFFFFL -//DAGB1_RESERVE11 -#define DAGB1_RESERVE11__RESERVE__SHIFT 0x0 -#define DAGB1_RESERVE11__RESERVE_MASK 0xFFFFFFFFL -//DAGB1_RESERVE12 -#define DAGB1_RESERVE12__RESERVE__SHIFT 0x0 -#define DAGB1_RESERVE12__RESERVE_MASK 0xFFFFFFFFL -//DAGB1_RESERVE13 -#define DAGB1_RESERVE13__RESERVE__SHIFT 0x0 -#define DAGB1_RESERVE13__RESERVE_MASK 0xFFFFFFFFL -//DAGB1_RESERVE14 -#define DAGB1_RESERVE14__RESERVE__SHIFT 0x0 -#define DAGB1_RESERVE14__RESERVE_MASK 0xFFFFFFFFL -//DAGB1_RESERVE15 -#define DAGB1_RESERVE15__RESERVE__SHIFT 0x0 -#define DAGB1_RESERVE15__RESERVE_MASK 0xFFFFFFFFL -//DAGB1_RESERVE16 -#define DAGB1_RESERVE16__RESERVE__SHIFT 0x0 -#define DAGB1_RESERVE16__RESERVE_MASK 0xFFFFFFFFL -//DAGB1_RESERVE17 -#define DAGB1_RESERVE17__RESERVE__SHIFT 0x0 -#define DAGB1_RESERVE17__RESERVE_MASK 0xFFFFFFFFL - - -// addressBlock: mmhub_ea_mmeadec -//MMEA0_DRAM_RD_CLI2GRP_MAP0 -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L -#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L -//MMEA0_DRAM_RD_CLI2GRP_MAP1 -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L -#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L -//MMEA0_DRAM_WR_CLI2GRP_MAP0 -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L -#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L -//MMEA0_DRAM_WR_CLI2GRP_MAP1 -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L -#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L -//MMEA0_DRAM_RD_GRP2VC_MAP -#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 -#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 -#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 -#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 -#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L -#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L -#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L -#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L -//MMEA0_DRAM_WR_GRP2VC_MAP -#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 -#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 -#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 -#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 -#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L -#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L -#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L -#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L -//MMEA0_DRAM_RD_LAZY -#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 -#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 -#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 -#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 -#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L -#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L -#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L -#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L -//MMEA0_DRAM_WR_LAZY -#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 -#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 -#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 -#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 -#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L -#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L -#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L -#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L -//MMEA0_DRAM_RD_CAM_CNTL -#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 -#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 -#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 -#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc -#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 -#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 -#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 -#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 -#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL -#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L -#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L -#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L -#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L -#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L -#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L -#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L -//MMEA0_DRAM_WR_CAM_CNTL -#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 -#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 -#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 -#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc -#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 -#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 -#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 -#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 -#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL -#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L -#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L -#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L -#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L -#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L -#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L -#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L -//MMEA0_DRAM_PAGE_BURST -#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 -#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 -#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 -#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 -#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL -#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L -#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L -#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L -//MMEA0_DRAM_RD_PRI_AGE -#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 -#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 -#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 -#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 -#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc -#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf -#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 -#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 -#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L -#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L -#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L -#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L -#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L -#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L -#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L -#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L -//MMEA0_DRAM_WR_PRI_AGE -#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 -#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 -#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 -#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 -#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc -#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf -#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 -#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 -#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L -#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L -#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L -#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L -#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L -#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L -#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L -#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L -//MMEA0_DRAM_RD_PRI_QUEUING -#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 -#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 -#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 -#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 -#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L -#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L -#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L -#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L -//MMEA0_DRAM_WR_PRI_QUEUING -#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 -#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 -#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 -#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 -#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L -#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L -#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L -#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L -//MMEA0_DRAM_RD_PRI_FIXED -#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 -#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 -#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 -#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 -#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L -#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L -#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L -#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L -//MMEA0_DRAM_WR_PRI_FIXED -#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 -#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 -#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 -#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 -#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L -#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L -#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L -#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L -//MMEA0_DRAM_RD_PRI_URGENCY -#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 -#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 -#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 -#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 -#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc -#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd -#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe -#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf -#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L -#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L -#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L -#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L -#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L -#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L -#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L -#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L -//MMEA0_DRAM_WR_PRI_URGENCY -#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 -#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 -#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 -#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 -#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc -#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd -#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe -#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf -#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L -#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L -#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L -#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L -#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L -#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L -#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L -#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L -//MMEA0_DRAM_RD_PRI_QUANT_PRI1 -#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA0_DRAM_RD_PRI_QUANT_PRI2 -#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA0_DRAM_RD_PRI_QUANT_PRI3 -#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA0_DRAM_WR_PRI_QUANT_PRI1 -#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA0_DRAM_WR_PRI_QUANT_PRI2 -#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA0_DRAM_WR_PRI_QUANT_PRI3 -#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA0_ADDRNORM_BASE_ADDR0 -#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 -#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 -#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4 -#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8 -#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc -#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L -#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L -#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L -#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L -#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L -//MMEA0_ADDRNORM_LIMIT_ADDR0 -#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 -#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 -#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa -#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc -#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL -#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L -#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L -#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L -//MMEA0_ADDRNORM_BASE_ADDR1 -#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 -#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 -#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4 -#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8 -#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc -#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L -#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L -#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L -#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L -#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L -//MMEA0_ADDRNORM_LIMIT_ADDR1 -#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 -#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 -#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa -#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc -#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL -#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L -#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L -#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L -//MMEA0_ADDRNORM_OFFSET_ADDR1 -#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 -#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 -#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L -#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L -//MMEA0_ADDRNORM_HOLE_CNTL -#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 -#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 -#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L -#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L -//MMEA0_ADDRDEC_BANK_CFG -#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 -#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 -#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa -#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd -#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 -#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 -#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL -#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L -#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L -#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L -#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L -#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L -//MMEA0_ADDRDEC_MISC_CFG -#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 -#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 -#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 -#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 -#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 -#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 -#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 -#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc -#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10 -#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14 -#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16 -#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18 -#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b -#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L -#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L -#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L -#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L -#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L -#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L -#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L -#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L -#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L -#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L -#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L -#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L -#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L -//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L -//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L -//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L -//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L -//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL -#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L -//MMEA0_ADDRDECDRAM_ADDR_HASH_PC -#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe -#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL -#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L -//MMEA0_ADDRDECDRAM_ADDR_HASH_PC2 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL -//MMEA0_ADDRDECDRAM_ADDR_HASH_CS0 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL -//MMEA0_ADDRDECDRAM_ADDR_HASH_CS1 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 -#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL -//MMEA0_ADDRDECDRAM_HARVEST_ENABLE -#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 -#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 -#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 -#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 -#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L -#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L -#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L -#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L -//MMEA0_ADDRDEC0_BASE_ADDR_CS0 -#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 -#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC0_BASE_ADDR_CS1 -#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 -#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC0_BASE_ADDR_CS2 -#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 -#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC0_BASE_ADDR_CS3 -#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 -#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC0_BASE_ADDR_SECCS0 -#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 -#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC0_BASE_ADDR_SECCS1 -#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 -#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC0_BASE_ADDR_SECCS2 -#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 -#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC0_BASE_ADDR_SECCS3 -#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 -#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC0_ADDR_MASK_CS01 -#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 -#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC0_ADDR_MASK_CS23 -#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 -#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC0_ADDR_MASK_SECCS01 -#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 -#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC0_ADDR_MASK_SECCS23 -#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 -#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC0_ADDR_CFG_CS01 -#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 -#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 -#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 -#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc -#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 -#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 -#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL -#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L -#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L -#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L -#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L -#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L -//MMEA0_ADDRDEC0_ADDR_CFG_CS23 -#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 -#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 -#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 -#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc -#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 -#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 -#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL -#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L -#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L -#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L -#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L -#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L -//MMEA0_ADDRDEC0_ADDR_SEL_CS01 -#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 -#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 -#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 -#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc -#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 -#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 -#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c -#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL -#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L -#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L -#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L -#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L -#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L -#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L -//MMEA0_ADDRDEC0_ADDR_SEL_CS23 -#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 -#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 -#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 -#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc -#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 -#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 -#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c -#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL -#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L -#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L -#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L -#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L -#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L -#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L -//MMEA0_ADDRDEC0_COL_SEL_LO_CS01 -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L -//MMEA0_ADDRDEC0_COL_SEL_LO_CS23 -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L -#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L -//MMEA0_ADDRDEC0_COL_SEL_HI_CS01 -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L -//MMEA0_ADDRDEC0_COL_SEL_HI_CS23 -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L -#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L -//MMEA0_ADDRDEC0_RM_SEL_CS01 -#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 -#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 -#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 -#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc -#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL -#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L -#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L -#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L -#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//MMEA0_ADDRDEC0_RM_SEL_CS23 -#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 -#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 -#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 -#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc -#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL -#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L -#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L -#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L -#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//MMEA0_ADDRDEC0_RM_SEL_SECCS01 -#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 -#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 -#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 -#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc -#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL -#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L -#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L -#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L -#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//MMEA0_ADDRDEC0_RM_SEL_SECCS23 -#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 -#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 -#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 -#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc -#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL -#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L -#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L -#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L -#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//MMEA0_ADDRDEC1_BASE_ADDR_CS0 -#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 -#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC1_BASE_ADDR_CS1 -#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 -#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC1_BASE_ADDR_CS2 -#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 -#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC1_BASE_ADDR_CS3 -#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 -#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC1_BASE_ADDR_SECCS0 -#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 -#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC1_BASE_ADDR_SECCS1 -#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 -#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC1_BASE_ADDR_SECCS2 -#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 -#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC1_BASE_ADDR_SECCS3 -#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 -#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 -#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L -#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC1_ADDR_MASK_CS01 -#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 -#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC1_ADDR_MASK_CS23 -#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 -#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC1_ADDR_MASK_SECCS01 -#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 -#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC1_ADDR_MASK_SECCS23 -#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 -#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL -//MMEA0_ADDRDEC1_ADDR_CFG_CS01 -#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 -#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 -#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 -#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc -#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 -#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 -#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL -#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L -#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L -#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L -#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L -#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L -//MMEA0_ADDRDEC1_ADDR_CFG_CS23 -#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 -#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 -#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 -#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc -#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 -#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 -#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL -#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L -#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L -#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L -#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L -#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L -//MMEA0_ADDRDEC1_ADDR_SEL_CS01 -#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 -#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 -#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 -#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc -#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 -#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 -#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c -#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL -#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L -#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L -#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L -#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L -#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L -#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L -//MMEA0_ADDRDEC1_ADDR_SEL_CS23 -#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 -#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 -#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 -#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc -#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 -#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 -#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c -#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL -#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L -#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L -#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L -#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L -#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L -#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L -//MMEA0_ADDRDEC1_COL_SEL_LO_CS01 -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L -//MMEA0_ADDRDEC1_COL_SEL_LO_CS23 -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L -#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L -//MMEA0_ADDRDEC1_COL_SEL_HI_CS01 -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L -//MMEA0_ADDRDEC1_COL_SEL_HI_CS23 -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L -#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L -//MMEA0_ADDRDEC1_RM_SEL_CS01 -#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 -#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 -#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 -#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc -#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL -#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L -#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L -#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L -#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//MMEA0_ADDRDEC1_RM_SEL_CS23 -#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 -#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 -#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 -#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc -#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL -#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L -#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L -#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L -#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//MMEA0_ADDRDEC1_RM_SEL_SECCS01 -#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 -#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 -#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 -#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc -#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL -#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L -#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L -#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L -#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//MMEA0_ADDRDEC1_RM_SEL_SECCS23 -#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 -#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 -#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 -#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc -#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL -#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L -#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L -#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L -#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//MMEA0_IO_RD_CLI2GRP_MAP0 -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L -#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L -//MMEA0_IO_RD_CLI2GRP_MAP1 -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L -#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L -//MMEA0_IO_WR_CLI2GRP_MAP0 -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L -#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L -//MMEA0_IO_WR_CLI2GRP_MAP1 -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L -#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L -//MMEA0_IO_RD_COMBINE_FLUSH -#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 -#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 -#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 -#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc -#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL -#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L -#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L -#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L -//MMEA0_IO_WR_COMBINE_FLUSH -#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 -#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 -#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 -#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc -#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL -#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L -#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L -#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L -//MMEA0_IO_GROUP_BURST -#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 -#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 -#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 -#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 -#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL -#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L -#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L -#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L -//MMEA0_IO_RD_PRI_AGE -#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 -#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 -#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 -#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 -#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc -#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf -#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 -#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 -#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L -#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L -#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L -#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L -#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L -#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L -#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L -#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L -//MMEA0_IO_WR_PRI_AGE -#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 -#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 -#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 -#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 -#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc -#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf -#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 -#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 -#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L -#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L -#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L -#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L -#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L -#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L -#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L -#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L -//MMEA0_IO_RD_PRI_QUEUING -#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 -#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 -#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 -#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 -#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L -#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L -#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L -#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L -//MMEA0_IO_WR_PRI_QUEUING -#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 -#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 -#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 -#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 -#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L -#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L -#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L -#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L -//MMEA0_IO_RD_PRI_FIXED -#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 -#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 -#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 -#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 -#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L -#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L -#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L -#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L -//MMEA0_IO_WR_PRI_FIXED -#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 -#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 -#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 -#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 -#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L -#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L -#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L -#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L -//MMEA0_IO_RD_PRI_URGENCY -#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 -#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 -#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 -#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 -#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc -#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd -#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe -#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf -#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L -#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L -#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L -#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L -#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L -#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L -#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L -#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L -//MMEA0_IO_WR_PRI_URGENCY -#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 -#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 -#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 -#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 -#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc -#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd -#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe -#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf -#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L -#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L -#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L -#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L -#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L -#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L -#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L -#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L -//MMEA0_IO_RD_PRI_URGENCY_MASK -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L -#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L -//MMEA0_IO_WR_PRI_URGENCY_MASK -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L -#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L -//MMEA0_IO_RD_PRI_QUANT_PRI1 -#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA0_IO_RD_PRI_QUANT_PRI2 -#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA0_IO_RD_PRI_QUANT_PRI3 -#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA0_IO_WR_PRI_QUANT_PRI1 -#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA0_IO_WR_PRI_QUANT_PRI2 -#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA0_IO_WR_PRI_QUANT_PRI3 -#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA0_SDP_ARB_DRAM -#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 -#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 -#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 -#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 -#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 -#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 -#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 -#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL -#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L -#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L -#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L -#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L -#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L -#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L -//MMEA0_SDP_ARB_FINAL -#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 -#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 -#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa -#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf -#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 -#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 -#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 -#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 -#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 -#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 -#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 -#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 -#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 -#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a -#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL -#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L -#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L -#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L -#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L -#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L -#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L -#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L -#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L -#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L -#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L -#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L -#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L -#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L -//MMEA0_SDP_DRAM_PRIORITY -#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 -#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 -#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 -#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc -#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 -#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 -#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 -#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c -#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL -#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L -#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L -#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L -#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L -#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L -#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L -#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L -//MMEA0_SDP_IO_PRIORITY -#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 -#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 -#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 -#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc -#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 -#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 -#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 -#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c -#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL -#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L -#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L -#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L -#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L -#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L -#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L -#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L -//MMEA0_SDP_CREDITS -#define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 -#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 -#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 -#define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL -#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L -#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L -//MMEA0_SDP_TAG_RESERVE0 -#define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 -#define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 -#define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 -#define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 -#define MMEA0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL -#define MMEA0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L -#define MMEA0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L -#define MMEA0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L -//MMEA0_SDP_TAG_RESERVE1 -#define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 -#define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 -#define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 -#define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 -#define MMEA0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL -#define MMEA0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L -#define MMEA0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L -#define MMEA0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L -//MMEA0_SDP_VCC_RESERVE0 -#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 -#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 -#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc -#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 -#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 -#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL -#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L -#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L -#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L -#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L -//MMEA0_SDP_VCC_RESERVE1 -#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 -#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 -#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc -#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f -#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL -#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L -#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L -#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L -//MMEA0_SDP_VCD_RESERVE0 -#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 -#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 -#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc -#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 -#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 -#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL -#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L -#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L -#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L -#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L -//MMEA0_SDP_VCD_RESERVE1 -#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 -#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 -#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc -#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f -#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL -#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L -#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L -#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L -//MMEA0_SDP_REQ_CNTL -#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 -#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 -#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 -#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 -#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 -#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L -#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L -#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L -#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L -#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L -//MMEA0_MISC -#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 -#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 -#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 -#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 -#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 -#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 -#define MMEA0_MISC__RRET_SWAP_MODE__SHIFT 0x6 -#define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x7 -#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x8 -#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xa -#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xc -#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xe -#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x13 -#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x14 -#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x15 -#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x16 -#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x17 -#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x18 -#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L -#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L -#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L -#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L -#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L -#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L -#define MMEA0_MISC__RRET_SWAP_MODE_MASK 0x00000040L -#define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000080L -#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000300L -#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00000C00L -#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00003000L -#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x0007C000L -#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x00080000L -#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x00100000L -#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x00200000L -#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x00400000L -#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x00800000L -#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x01000000L -//MMEA0_LATENCY_SAMPLING -#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 -#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 -#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 -#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 -#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 -#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 -#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 -#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 -#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 -#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 -#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa -#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb -#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc -#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd -#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe -#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 -#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L -#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L -#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L -#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L -#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L -#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L -#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L -#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L -#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L -#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L -#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L -#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L -#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L -#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L -#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L -#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L -//MMEA0_PERFCOUNTER_LO -#define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 -#define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL -//MMEA0_PERFCOUNTER_HI -#define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 -#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 -#define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL -#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L -//MMEA0_PERFCOUNTER0_CFG -#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 -#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 -#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 -#define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c -#define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d -#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL -#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L -#define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L -//MMEA0_PERFCOUNTER1_CFG -#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 -#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 -#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 -#define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c -#define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d -#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL -#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L -#define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L -//MMEA0_PERFCOUNTER_RSLT_CNTL -#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 -#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 -#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 -#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 -#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 -#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a -#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL -#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L -#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L -#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L -//MMEA0_EDC_CNT -#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 -#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 -#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 -#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 -#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 -#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa -#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc -#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe -#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 -#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 -#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 -#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 -#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 -#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a -#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c -#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L -#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL -#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L -#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L -#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L -#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L -#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L -#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L -#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L -#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L -#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L -#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L -#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L -#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L -#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L -//MMEA0_EDC_CNT2 -#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 -#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 -#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 -#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 -#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 -#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa -#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc -#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe -#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L -#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL -#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L -#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L -#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L -#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L -#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L -#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L -//MMEA0_DSM_CNTL -#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 -#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 -#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 -#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 -#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 -#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 -#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 -#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb -#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc -#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe -#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf -#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 -#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 -#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 -#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 -#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 -#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L -#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L -#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L -#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L -#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L -#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L -#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L -#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L -#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L -//MMEA0_DSM_CNTLA -#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 -#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 -#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 -#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 -#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 -#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 -#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 -#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb -#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc -#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe -#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf -#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 -#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 -#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 -#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L -#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L -#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L -#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L -#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L -#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L -#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L -//MMEA0_DSM_CNTLB -//MMEA0_DSM_CNTL2 -#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 -#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 -#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 -#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb -#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc -#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe -#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf -#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 -#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 -#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 -#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 -#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 -#define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a -#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L -#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L -#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L -#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L -#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L -#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L -#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L -#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L -#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L -#define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L -//MMEA0_DSM_CNTL2A -#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 -#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 -#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 -#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb -#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc -#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe -#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf -#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 -#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 -#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 -#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L -#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L -#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L -#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L -#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L -#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L -#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L -//MMEA0_DSM_CNTL2B -//MMEA0_CGTT_CLK_CTRL -#define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 -#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b -#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c -#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d -#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e -#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f -#define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L -#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L -#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L -#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L -#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L -#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L -//MMEA0_EDC_MODE -#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 -#define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11 -#define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14 -#define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d -#define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f -#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L -#define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L -#define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L -#define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L -#define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L -//MMEA0_ERR_STATUS -#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 -#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 -#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0x8 -#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0x9 -#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xa -#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL -#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L -#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000100L -#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000200L -#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00000400L -//MMEA0_MISC2 -#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 -#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 -#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 -#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 -#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L -#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L -#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL -#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L -//MMEA1_DRAM_RD_CLI2GRP_MAP0 -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L -#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L -//MMEA1_DRAM_RD_CLI2GRP_MAP1 -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L -#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L -//MMEA1_DRAM_WR_CLI2GRP_MAP0 -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L -#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L -//MMEA1_DRAM_WR_CLI2GRP_MAP1 -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L -#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L -//MMEA1_DRAM_RD_GRP2VC_MAP -#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 -#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 -#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 -#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 -#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L -#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L -#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L -#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L -//MMEA1_DRAM_WR_GRP2VC_MAP -#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 -#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 -#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 -#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 -#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L -#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L -#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L -#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L -//MMEA1_DRAM_RD_LAZY -#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 -#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 -#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 -#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 -#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L -#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L -#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L -#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L -//MMEA1_DRAM_WR_LAZY -#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 -#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 -#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 -#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 -#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L -#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L -#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L -#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L -//MMEA1_DRAM_RD_CAM_CNTL -#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 -#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 -#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 -#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc -#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 -#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 -#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 -#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 -#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL -#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L -#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L -#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L -#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L -#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L -#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L -#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L -//MMEA1_DRAM_WR_CAM_CNTL -#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 -#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 -#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 -#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc -#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 -#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 -#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 -#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 -#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL -#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L -#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L -#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L -#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L -#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L -#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L -#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L -//MMEA1_DRAM_PAGE_BURST -#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 -#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 -#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 -#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 -#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL -#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L -#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L -#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L -//MMEA1_DRAM_RD_PRI_AGE -#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 -#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 -#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 -#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 -#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc -#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf -#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 -#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 -#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L -#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L -#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L -#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L -#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L -#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L -#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L -#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L -//MMEA1_DRAM_WR_PRI_AGE -#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 -#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 -#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 -#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 -#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc -#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf -#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 -#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 -#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L -#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L -#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L -#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L -#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L -#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L -#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L -#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L -//MMEA1_DRAM_RD_PRI_QUEUING -#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 -#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 -#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 -#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 -#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L -#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L -#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L -#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L -//MMEA1_DRAM_WR_PRI_QUEUING -#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 -#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 -#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 -#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 -#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L -#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L -#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L -#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L -//MMEA1_DRAM_RD_PRI_FIXED -#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 -#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 -#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 -#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 -#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L -#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L -#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L -#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L -//MMEA1_DRAM_WR_PRI_FIXED -#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 -#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 -#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 -#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 -#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L -#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L -#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L -#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L -//MMEA1_DRAM_RD_PRI_URGENCY -#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 -#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 -#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 -#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 -#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc -#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd -#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe -#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf -#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L -#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L -#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L -#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L -#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L -#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L -#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L -#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L -//MMEA1_DRAM_WR_PRI_URGENCY -#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 -#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 -#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 -#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 -#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc -#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd -#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe -#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf -#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L -#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L -#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L -#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L -#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L -#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L -#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L -#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L -//MMEA1_DRAM_RD_PRI_QUANT_PRI1 -#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA1_DRAM_RD_PRI_QUANT_PRI2 -#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA1_DRAM_RD_PRI_QUANT_PRI3 -#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA1_DRAM_WR_PRI_QUANT_PRI1 -#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA1_DRAM_WR_PRI_QUANT_PRI2 -#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA1_DRAM_WR_PRI_QUANT_PRI3 -#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA1_ADDRNORM_BASE_ADDR0 -#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 -#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 -#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4 -#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8 -#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc -#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L -#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L -#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L -#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L -#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L -//MMEA1_ADDRNORM_LIMIT_ADDR0 -#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 -#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 -#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa -#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc -#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL -#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L -#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L -#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L -//MMEA1_ADDRNORM_BASE_ADDR1 -#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 -#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 -#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4 -#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8 -#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc -#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L -#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L -#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L -#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L -#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L -//MMEA1_ADDRNORM_LIMIT_ADDR1 -#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 -#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 -#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa -#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc -#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL -#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L -#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L -#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L -//MMEA1_ADDRNORM_OFFSET_ADDR1 -#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 -#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 -#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L -#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L -//MMEA1_ADDRNORM_HOLE_CNTL -#define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 -#define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 -#define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L -#define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L -//MMEA1_ADDRDEC_BANK_CFG -#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 -#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 -#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa -#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd -#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 -#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 -#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL -#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L -#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L -#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L -#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L -#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L -//MMEA1_ADDRDEC_MISC_CFG -#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 -#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 -#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 -#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 -#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 -#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 -#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 -#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc -#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10 -#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14 -#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16 -#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18 -#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b -#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L -#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L -#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L -#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L -#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L -#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L -#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L -#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L -#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L -#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L -#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L -#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L -#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L -//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L -//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L -//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L -//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L -//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL -#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L -//MMEA1_ADDRDECDRAM_ADDR_HASH_PC -#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe -#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL -#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L -//MMEA1_ADDRDECDRAM_ADDR_HASH_PC2 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL -//MMEA1_ADDRDECDRAM_ADDR_HASH_CS0 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL -//MMEA1_ADDRDECDRAM_ADDR_HASH_CS1 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 -#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL -//MMEA1_ADDRDECDRAM_HARVEST_ENABLE -#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 -#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 -#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 -#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 -#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L -#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L -#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L -#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L -//MMEA1_ADDRDEC0_BASE_ADDR_CS0 -#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 -#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC0_BASE_ADDR_CS1 -#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 -#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC0_BASE_ADDR_CS2 -#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 -#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC0_BASE_ADDR_CS3 -#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 -#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC0_BASE_ADDR_SECCS0 -#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 -#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC0_BASE_ADDR_SECCS1 -#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 -#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC0_BASE_ADDR_SECCS2 -#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 -#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC0_BASE_ADDR_SECCS3 -#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 -#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC0_ADDR_MASK_CS01 -#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 -#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC0_ADDR_MASK_CS23 -#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 -#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC0_ADDR_MASK_SECCS01 -#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 -#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC0_ADDR_MASK_SECCS23 -#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 -#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC0_ADDR_CFG_CS01 -#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 -#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 -#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 -#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc -#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 -#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 -#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL -#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L -#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L -#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L -#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L -#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L -//MMEA1_ADDRDEC0_ADDR_CFG_CS23 -#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 -#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 -#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 -#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc -#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 -#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 -#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL -#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L -#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L -#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L -#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L -#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L -//MMEA1_ADDRDEC0_ADDR_SEL_CS01 -#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 -#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 -#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 -#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc -#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 -#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 -#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c -#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL -#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L -#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L -#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L -#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L -#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L -#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L -//MMEA1_ADDRDEC0_ADDR_SEL_CS23 -#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 -#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 -#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 -#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc -#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 -#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 -#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c -#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL -#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L -#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L -#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L -#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L -#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L -#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L -//MMEA1_ADDRDEC0_COL_SEL_LO_CS01 -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L -//MMEA1_ADDRDEC0_COL_SEL_LO_CS23 -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L -#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L -//MMEA1_ADDRDEC0_COL_SEL_HI_CS01 -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L -//MMEA1_ADDRDEC0_COL_SEL_HI_CS23 -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L -#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L -//MMEA1_ADDRDEC0_RM_SEL_CS01 -#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 -#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 -#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 -#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc -#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL -#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L -#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L -#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L -#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//MMEA1_ADDRDEC0_RM_SEL_CS23 -#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 -#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 -#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 -#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc -#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL -#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L -#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L -#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L -#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//MMEA1_ADDRDEC0_RM_SEL_SECCS01 -#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 -#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 -#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 -#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc -#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL -#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L -#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L -#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L -#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//MMEA1_ADDRDEC0_RM_SEL_SECCS23 -#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 -#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 -#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 -#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc -#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL -#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L -#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L -#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L -#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//MMEA1_ADDRDEC1_BASE_ADDR_CS0 -#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 -#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC1_BASE_ADDR_CS1 -#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 -#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC1_BASE_ADDR_CS2 -#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 -#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC1_BASE_ADDR_CS3 -#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 -#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC1_BASE_ADDR_SECCS0 -#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 -#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC1_BASE_ADDR_SECCS1 -#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 -#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC1_BASE_ADDR_SECCS2 -#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 -#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC1_BASE_ADDR_SECCS3 -#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 -#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 -#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L -#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC1_ADDR_MASK_CS01 -#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 -#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC1_ADDR_MASK_CS23 -#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 -#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC1_ADDR_MASK_SECCS01 -#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 -#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC1_ADDR_MASK_SECCS23 -#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 -#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL -//MMEA1_ADDRDEC1_ADDR_CFG_CS01 -#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 -#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 -#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 -#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc -#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 -#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 -#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL -#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L -#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L -#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L -#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L -#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L -//MMEA1_ADDRDEC1_ADDR_CFG_CS23 -#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 -#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 -#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 -#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc -#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 -#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 -#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL -#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L -#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L -#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L -#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L -#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L -//MMEA1_ADDRDEC1_ADDR_SEL_CS01 -#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 -#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 -#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 -#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc -#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 -#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 -#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c -#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL -#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L -#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L -#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L -#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L -#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L -#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L -//MMEA1_ADDRDEC1_ADDR_SEL_CS23 -#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 -#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 -#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 -#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc -#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 -#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 -#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c -#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL -#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L -#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L -#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L -#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L -#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L -#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L -//MMEA1_ADDRDEC1_COL_SEL_LO_CS01 -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L -//MMEA1_ADDRDEC1_COL_SEL_LO_CS23 -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L -#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L -//MMEA1_ADDRDEC1_COL_SEL_HI_CS01 -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L -//MMEA1_ADDRDEC1_COL_SEL_HI_CS23 -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L -#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L -//MMEA1_ADDRDEC1_RM_SEL_CS01 -#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 -#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 -#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 -#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc -#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL -#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L -#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L -#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L -#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//MMEA1_ADDRDEC1_RM_SEL_CS23 -#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 -#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 -#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 -#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc -#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL -#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L -#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L -#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L -#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//MMEA1_ADDRDEC1_RM_SEL_SECCS01 -#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 -#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 -#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 -#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc -#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL -#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L -#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L -#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L -#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//MMEA1_ADDRDEC1_RM_SEL_SECCS23 -#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 -#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 -#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 -#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc -#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL -#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L -#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L -#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L -#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//MMEA1_IO_RD_CLI2GRP_MAP0 -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L -#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L -//MMEA1_IO_RD_CLI2GRP_MAP1 -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L -#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L -//MMEA1_IO_WR_CLI2GRP_MAP0 -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L -#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L -//MMEA1_IO_WR_CLI2GRP_MAP1 -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L -#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L -//MMEA1_IO_RD_COMBINE_FLUSH -#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 -#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 -#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 -#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc -#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL -#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L -#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L -#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L -//MMEA1_IO_WR_COMBINE_FLUSH -#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 -#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 -#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 -#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc -#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL -#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L -#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L -#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L -//MMEA1_IO_GROUP_BURST -#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 -#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 -#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 -#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 -#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL -#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L -#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L -#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L -//MMEA1_IO_RD_PRI_AGE -#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 -#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 -#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 -#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 -#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc -#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf -#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 -#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 -#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L -#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L -#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L -#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L -#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L -#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L -#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L -#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L -//MMEA1_IO_WR_PRI_AGE -#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 -#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 -#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 -#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 -#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc -#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf -#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 -#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 -#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L -#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L -#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L -#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L -#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L -#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L -#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L -#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L -//MMEA1_IO_RD_PRI_QUEUING -#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 -#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 -#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 -#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 -#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L -#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L -#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L -#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L -//MMEA1_IO_WR_PRI_QUEUING -#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 -#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 -#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 -#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 -#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L -#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L -#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L -#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L -//MMEA1_IO_RD_PRI_FIXED -#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 -#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 -#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 -#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 -#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L -#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L -#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L -#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L -//MMEA1_IO_WR_PRI_FIXED -#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 -#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 -#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 -#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 -#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L -#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L -#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L -#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L -//MMEA1_IO_RD_PRI_URGENCY -#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 -#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 -#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 -#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 -#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc -#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd -#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe -#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf -#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L -#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L -#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L -#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L -#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L -#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L -#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L -#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L -//MMEA1_IO_WR_PRI_URGENCY -#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 -#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 -#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 -#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 -#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc -#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd -#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe -#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf -#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L -#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L -#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L -#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L -#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L -#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L -#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L -#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L -//MMEA1_IO_RD_PRI_URGENCY_MASK -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L -#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L -//MMEA1_IO_WR_PRI_URGENCY_MASK -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L -#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L -//MMEA1_IO_RD_PRI_QUANT_PRI1 -#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA1_IO_RD_PRI_QUANT_PRI2 -#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA1_IO_RD_PRI_QUANT_PRI3 -#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA1_IO_WR_PRI_QUANT_PRI1 -#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA1_IO_WR_PRI_QUANT_PRI2 -#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA1_IO_WR_PRI_QUANT_PRI3 -#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 -#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 -#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 -#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 -#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL -#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L -//MMEA1_SDP_ARB_DRAM -#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 -#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 -#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 -#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 -#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 -#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 -#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 -#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL -#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L -#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L -#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L -#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L -#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L -#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L -//MMEA1_SDP_ARB_FINAL -#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 -#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 -#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa -#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf -#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 -#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 -#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 -#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 -#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 -#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 -#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 -#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 -#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 -#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a -#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL -#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L -#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L -#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L -#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L -#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L -#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L -#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L -#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L -#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L -#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L -#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L -#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L -#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L -//MMEA1_SDP_DRAM_PRIORITY -#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 -#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 -#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 -#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc -#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 -#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 -#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 -#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c -#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL -#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L -#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L -#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L -#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L -#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L -#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L -#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L -//MMEA1_SDP_IO_PRIORITY -#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 -#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 -#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 -#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc -#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 -#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 -#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 -#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c -#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL -#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L -#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L -#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L -#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L -#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L -#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L -#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L -//MMEA1_SDP_CREDITS -#define MMEA1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 -#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 -#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 -#define MMEA1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL -#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L -#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L -//MMEA1_SDP_TAG_RESERVE0 -#define MMEA1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 -#define MMEA1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 -#define MMEA1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 -#define MMEA1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 -#define MMEA1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL -#define MMEA1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L -#define MMEA1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L -#define MMEA1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L -//MMEA1_SDP_TAG_RESERVE1 -#define MMEA1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 -#define MMEA1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 -#define MMEA1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 -#define MMEA1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 -#define MMEA1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL -#define MMEA1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L -#define MMEA1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L -#define MMEA1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L -//MMEA1_SDP_VCC_RESERVE0 -#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 -#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 -#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc -#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 -#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 -#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL -#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L -#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L -#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L -#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L -//MMEA1_SDP_VCC_RESERVE1 -#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 -#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 -#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc -#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f -#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL -#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L -#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L -#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L -//MMEA1_SDP_VCD_RESERVE0 -#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 -#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 -#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc -#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 -#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 -#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL -#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L -#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L -#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L -#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L -//MMEA1_SDP_VCD_RESERVE1 -#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 -#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 -#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc -#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f -#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL -#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L -#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L -#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L -//MMEA1_SDP_REQ_CNTL -#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 -#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 -#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 -#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 -#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 -#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L -#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L -#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L -#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L -#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L -//MMEA1_MISC -#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 -#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 -#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 -#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 -#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 -#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 -#define MMEA1_MISC__RRET_SWAP_MODE__SHIFT 0x6 -#define MMEA1_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x7 -#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x8 -#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xa -#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xc -#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xe -#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x13 -#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x14 -#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x15 -#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x16 -#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x17 -#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x18 -#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L -#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L -#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L -#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L -#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L -#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L -#define MMEA1_MISC__RRET_SWAP_MODE_MASK 0x00000040L -#define MMEA1_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000080L -#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000300L -#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00000C00L -#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00003000L -#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x0007C000L -#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x00080000L -#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x00100000L -#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x00200000L -#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x00400000L -#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x00800000L -#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x01000000L -//MMEA1_LATENCY_SAMPLING -#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 -#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 -#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 -#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 -#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 -#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 -#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 -#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 -#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 -#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 -#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa -#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb -#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc -#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd -#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe -#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 -#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L -#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L -#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L -#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L -#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L -#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L -#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L -#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L -#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L -#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L -#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L -#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L -#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L -#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L -#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L -#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L -//MMEA1_PERFCOUNTER_LO -#define MMEA1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 -#define MMEA1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL -//MMEA1_PERFCOUNTER_HI -#define MMEA1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 -#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 -#define MMEA1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL -#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L -//MMEA1_PERFCOUNTER0_CFG -#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 -#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 -#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 -#define MMEA1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c -#define MMEA1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d -#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL -#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L -#define MMEA1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define MMEA1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L -//MMEA1_PERFCOUNTER1_CFG -#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 -#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 -#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 -#define MMEA1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c -#define MMEA1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d -#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL -#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L -#define MMEA1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define MMEA1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L -//MMEA1_PERFCOUNTER_RSLT_CNTL -#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 -#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 -#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 -#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 -#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 -#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a -#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL -#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L -#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L -#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L -//MMEA1_EDC_CNT -#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 -#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 -#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 -#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 -#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 -#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa -#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc -#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe -#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 -#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 -#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 -#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 -#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 -#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a -#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c -#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L -#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL -#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L -#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L -#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L -#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L -#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L -#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L -#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L -#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L -#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L -#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L -#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L -#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L -#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L -//MMEA1_EDC_CNT2 -#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 -#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 -#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 -#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 -#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 -#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa -#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc -#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe -#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L -#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL -#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L -#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L -#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L -#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L -#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L -#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L -//MMEA1_DSM_CNTL -#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 -#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 -#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 -#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 -#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 -#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 -#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 -#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb -#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc -#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe -#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf -#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 -#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 -#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 -#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 -#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 -#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L -#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L -#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L -#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L -#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L -#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L -#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L -#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L -#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L -//MMEA1_DSM_CNTLA -#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 -#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 -#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 -#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 -#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 -#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 -#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 -#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb -#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc -#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe -#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf -#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 -#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 -#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 -#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L -#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L -#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L -#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L -#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L -#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L -#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L -//MMEA1_DSM_CNTLB -//MMEA1_DSM_CNTL2 -#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 -#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 -#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 -#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb -#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc -#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe -#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf -#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 -#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 -#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 -#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 -#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 -#define MMEA1_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a -#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L -#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L -#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L -#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L -#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L -#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L -#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L -#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L -#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L -#define MMEA1_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L -//MMEA1_DSM_CNTL2A -#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 -#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 -#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 -#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb -#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc -#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe -#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf -#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 -#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 -#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 -#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L -#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L -#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L -#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L -#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L -#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L -#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L -//MMEA1_DSM_CNTL2B -//MMEA1_CGTT_CLK_CTRL -#define MMEA1_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 -#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b -#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c -#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d -#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e -#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f -#define MMEA1_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L -#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L -#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L -#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L -#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L -#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L -//MMEA1_EDC_MODE -#define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 -#define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11 -#define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14 -#define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d -#define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f -#define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L -#define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L -#define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L -#define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L -#define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L -//MMEA1_ERR_STATUS -#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 -#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 -#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0x8 -#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0x9 -#define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xa -#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL -#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L -#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000100L -#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000200L -#define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00000400L -//MMEA1_MISC2 -#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 -#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 -#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 -#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 -#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L -#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L -#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL -#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L - - -// addressBlock: mmhub_pctldec -//PCTL_MISC -#define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x0 -#define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x3 -#define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0x6 -#define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0xb -#define PCTL_MISC__IGNORE_EA0_SDP_ACK__SHIFT 0xc -#define PCTL_MISC__IGNORE_EA1_SDP_ACK__SHIFT 0xd -#define PCTL_MISC__PGFSM_CMD_STATUS__SHIFT 0xe -#define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x00000007L -#define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00000038L -#define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x000007C0L -#define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00000800L -#define PCTL_MISC__IGNORE_EA0_SDP_ACK_MASK 0x00001000L -#define PCTL_MISC__IGNORE_EA1_SDP_ACK_MASK 0x00002000L -#define PCTL_MISC__PGFSM_CMD_STATUS_MASK 0x0000C000L -//PCTL_MMHUB_DEEPSLEEP -#define PCTL_MMHUB_DEEPSLEEP__DS0__SHIFT 0x0 -#define PCTL_MMHUB_DEEPSLEEP__DS1__SHIFT 0x1 -#define PCTL_MMHUB_DEEPSLEEP__DS2__SHIFT 0x2 -#define PCTL_MMHUB_DEEPSLEEP__DS3__SHIFT 0x3 -#define PCTL_MMHUB_DEEPSLEEP__DS4__SHIFT 0x4 -#define PCTL_MMHUB_DEEPSLEEP__DS5__SHIFT 0x5 -#define PCTL_MMHUB_DEEPSLEEP__DS6__SHIFT 0x6 -#define PCTL_MMHUB_DEEPSLEEP__DS7__SHIFT 0x7 -#define PCTL_MMHUB_DEEPSLEEP__DS8__SHIFT 0x8 -#define PCTL_MMHUB_DEEPSLEEP__DS9__SHIFT 0x9 -#define PCTL_MMHUB_DEEPSLEEP__DS10__SHIFT 0xa -#define PCTL_MMHUB_DEEPSLEEP__DS11__SHIFT 0xb -#define PCTL_MMHUB_DEEPSLEEP__DS12__SHIFT 0xc -#define PCTL_MMHUB_DEEPSLEEP__DS13__SHIFT 0xd -#define PCTL_MMHUB_DEEPSLEEP__DS14__SHIFT 0xe -#define PCTL_MMHUB_DEEPSLEEP__DS15__SHIFT 0xf -#define PCTL_MMHUB_DEEPSLEEP__DS16__SHIFT 0x10 -#define PCTL_MMHUB_DEEPSLEEP__SETCLEAR__SHIFT 0x1f -#define PCTL_MMHUB_DEEPSLEEP__DS0_MASK 0x00000001L -#define PCTL_MMHUB_DEEPSLEEP__DS1_MASK 0x00000002L -#define PCTL_MMHUB_DEEPSLEEP__DS2_MASK 0x00000004L -#define PCTL_MMHUB_DEEPSLEEP__DS3_MASK 0x00000008L -#define PCTL_MMHUB_DEEPSLEEP__DS4_MASK 0x00000010L -#define PCTL_MMHUB_DEEPSLEEP__DS5_MASK 0x00000020L -#define PCTL_MMHUB_DEEPSLEEP__DS6_MASK 0x00000040L -#define PCTL_MMHUB_DEEPSLEEP__DS7_MASK 0x00000080L -#define PCTL_MMHUB_DEEPSLEEP__DS8_MASK 0x00000100L -#define PCTL_MMHUB_DEEPSLEEP__DS9_MASK 0x00000200L -#define PCTL_MMHUB_DEEPSLEEP__DS10_MASK 0x00000400L -#define PCTL_MMHUB_DEEPSLEEP__DS11_MASK 0x00000800L -#define PCTL_MMHUB_DEEPSLEEP__DS12_MASK 0x00001000L -#define PCTL_MMHUB_DEEPSLEEP__DS13_MASK 0x00002000L -#define PCTL_MMHUB_DEEPSLEEP__DS14_MASK 0x00004000L -#define PCTL_MMHUB_DEEPSLEEP__DS15_MASK 0x00008000L -#define PCTL_MMHUB_DEEPSLEEP__DS16_MASK 0x00010000L -#define PCTL_MMHUB_DEEPSLEEP__SETCLEAR_MASK 0x80000000L -//PCTL_MMHUB_DEEPSLEEP_OVERRIDE -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L -#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L -//PCTL_PG_IGNORE_DEEPSLEEP -#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x0 -#define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x1 -#define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x2 -#define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x3 -#define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x4 -#define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x5 -#define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x6 -#define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x7 -#define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x8 -#define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x9 -#define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0xa -#define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xb -#define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xc -#define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xd -#define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xe -#define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xf -#define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0x10 -#define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x11 -#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00000001L -#define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000002L -#define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000004L -#define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000008L -#define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000010L -#define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000020L -#define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000040L -#define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000080L -#define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000100L -#define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000200L -#define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000400L -#define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000800L -#define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00001000L -#define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00002000L -#define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00004000L -#define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00008000L -#define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00010000L -#define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00020000L -//PCTL_PG_DAGB -#define PCTL_PG_DAGB__DS0__SHIFT 0x0 -#define PCTL_PG_DAGB__DS1__SHIFT 0x1 -#define PCTL_PG_DAGB__DS2__SHIFT 0x2 -#define PCTL_PG_DAGB__DS3__SHIFT 0x3 -#define PCTL_PG_DAGB__DS4__SHIFT 0x4 -#define PCTL_PG_DAGB__DS5__SHIFT 0x5 -#define PCTL_PG_DAGB__DS6__SHIFT 0x6 -#define PCTL_PG_DAGB__DS7__SHIFT 0x7 -#define PCTL_PG_DAGB__DS8__SHIFT 0x8 -#define PCTL_PG_DAGB__DS9__SHIFT 0x9 -#define PCTL_PG_DAGB__DS10__SHIFT 0xa -#define PCTL_PG_DAGB__DS11__SHIFT 0xb -#define PCTL_PG_DAGB__DS12__SHIFT 0xc -#define PCTL_PG_DAGB__DS13__SHIFT 0xd -#define PCTL_PG_DAGB__DS14__SHIFT 0xe -#define PCTL_PG_DAGB__DS15__SHIFT 0xf -#define PCTL_PG_DAGB__DS16__SHIFT 0x10 -#define PCTL_PG_DAGB__DS0_MASK 0x00000001L -#define PCTL_PG_DAGB__DS1_MASK 0x00000002L -#define PCTL_PG_DAGB__DS2_MASK 0x00000004L -#define PCTL_PG_DAGB__DS3_MASK 0x00000008L -#define PCTL_PG_DAGB__DS4_MASK 0x00000010L -#define PCTL_PG_DAGB__DS5_MASK 0x00000020L -#define PCTL_PG_DAGB__DS6_MASK 0x00000040L -#define PCTL_PG_DAGB__DS7_MASK 0x00000080L -#define PCTL_PG_DAGB__DS8_MASK 0x00000100L -#define PCTL_PG_DAGB__DS9_MASK 0x00000200L -#define PCTL_PG_DAGB__DS10_MASK 0x00000400L -#define PCTL_PG_DAGB__DS11_MASK 0x00000800L -#define PCTL_PG_DAGB__DS12_MASK 0x00001000L -#define PCTL_PG_DAGB__DS13_MASK 0x00002000L -#define PCTL_PG_DAGB__DS14_MASK 0x00004000L -#define PCTL_PG_DAGB__DS15_MASK 0x00008000L -#define PCTL_PG_DAGB__DS16_MASK 0x00010000L -//PCTL0_RENG_RAM_INDEX -#define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 -#define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL -//PCTL0_RENG_RAM_DATA -#define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 -#define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL -//PCTL0_RENG_EXECUTE -#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 -#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 -#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 -#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 -#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xe -#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x19 -#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L -#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L -#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L -#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00003FF8L -#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x01FFC000L -#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x02000000L -//PCTL0_MISC -#define PCTL0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb -#define PCTL0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc -#define PCTL0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf -#define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 -#define PCTL0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L -#define PCTL0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L -#define PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L -#define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L -//PCTL0_STCTRL_REGISTER_SAVE_RANGE0 -#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 -#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 -#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL -#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L -//PCTL0_STCTRL_REGISTER_SAVE_RANGE1 -#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 -#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 -#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL -#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L -//PCTL0_STCTRL_REGISTER_SAVE_RANGE2 -#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 -#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 -#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL -#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L -//PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET -#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 -#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 -#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL -#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L -//PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 -#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 -#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 -#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL -#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L -//PCTL1_RENG_RAM_INDEX -#define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 -#define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL -//PCTL1_RENG_RAM_DATA -#define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 -#define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL -//PCTL1_RENG_EXECUTE -#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 -#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 -#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 -#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 -#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd -#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x17 -#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L -#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L -#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L -#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FF8L -#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x007FE000L -#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00800000L -//PCTL1_MISC -#define PCTL1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa -#define PCTL1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb -#define PCTL1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe -#define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf -#define PCTL1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 -#define PCTL1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L -#define PCTL1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L -#define PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L -#define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L -#define PCTL1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L -//PCTL1_STCTRL_REGISTER_SAVE_RANGE0 -#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 -#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 -#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL -#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L -//PCTL1_STCTRL_REGISTER_SAVE_RANGE1 -#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 -#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 -#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL -#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L -//PCTL1_STCTRL_REGISTER_SAVE_RANGE2 -#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 -#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 -#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL -#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L -//PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET -#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 -#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 -#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL -#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L -//PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 -#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 -#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 -#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL -#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L -//PCTL2_RENG_RAM_INDEX -#define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 -#define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL -//PCTL2_RENG_RAM_DATA -#define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 -#define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL -//PCTL2_RENG_EXECUTE -#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 -#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 -#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 -#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 -#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd -#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x17 -#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L -#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L -#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L -#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FF8L -#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x007FE000L -#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00800000L -//PCTL2_MISC -#define PCTL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa -#define PCTL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb -#define PCTL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe -#define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf -#define PCTL2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 -#define PCTL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L -#define PCTL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L -#define PCTL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L -#define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L -#define PCTL2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L -//PCTL2_STCTRL_REGISTER_SAVE_RANGE0 -#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 -#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 -#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL -#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L -//PCTL2_STCTRL_REGISTER_SAVE_RANGE1 -#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 -#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 -#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL -#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L -//PCTL2_STCTRL_REGISTER_SAVE_RANGE2 -#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 -#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 -#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL -#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L -//PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET -#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 -#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 -#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL -#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L -//PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 -#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 -#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 -#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL -#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L - - -// addressBlock: mmhub_l1tlb_vml1dec -//MC_VM_MX_L1_TLB0_STATUS -#define MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 -#define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 -#define MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L -#define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L -//MC_VM_MX_L1_TLB1_STATUS -#define MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 -#define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 -#define MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L -#define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L -//MC_VM_MX_L1_TLB2_STATUS -#define MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 -#define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 -#define MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L -#define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L -//MC_VM_MX_L1_TLB3_STATUS -#define MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 -#define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 -#define MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L -#define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L -//MC_VM_MX_L1_TLB4_STATUS -#define MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 -#define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 -#define MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L -#define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L -//MC_VM_MX_L1_TLB5_STATUS -#define MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 -#define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 -#define MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L -#define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L -//MC_VM_MX_L1_TLB6_STATUS -#define MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 -#define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 -#define MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L -#define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L -//MC_VM_MX_L1_TLB7_STATUS -#define MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 -#define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 -#define MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L -#define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L - - -// addressBlock: mmhub_l1tlb_vml1pldec -//MC_VM_MX_L1_PERFCOUNTER0_CFG -#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L -//MC_VM_MX_L1_PERFCOUNTER1_CFG -#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L -//MC_VM_MX_L1_PERFCOUNTER2_CFG -#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L -//MC_VM_MX_L1_PERFCOUNTER3_CFG -#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L -//MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL -#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 -#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 -#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 -#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 -#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 -#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a -#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL -#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L -#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L -#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L - - -// addressBlock: mmhub_l1tlb_vml1prdec -//MC_VM_MX_L1_PERFCOUNTER_LO -#define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 -#define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL -//MC_VM_MX_L1_PERFCOUNTER_HI -#define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 -#define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 -#define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL -#define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L - - -// addressBlock: mmhub_utcl2_atcl2dec -//ATC_L2_CNTL -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 -#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8 -#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L -#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L -#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L -//ATC_L2_CNTL2 -#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 -#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 -#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 -#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 -#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc -#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf -#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL -#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L -#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L -#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L -#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L -#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L -//ATC_L2_CACHE_DATA0 -#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 -#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 -#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 -#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 -#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L -#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L -#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL -#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L -//ATC_L2_CACHE_DATA1 -#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 -#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL -//ATC_L2_CACHE_DATA2 -#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 -#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL -//ATC_L2_CNTL3 -#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0 -#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3 -#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L -#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L -//ATC_L2_STATUS -#define ATC_L2_STATUS__BUSY__SHIFT 0x0 -#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 -#define ATC_L2_STATUS__BUSY_MASK 0x00000001L -#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL -//ATC_L2_STATUS2 -#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 -#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 -#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL -#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L -//ATC_L2_MISC_CG -#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 -#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 -#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 -#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L -#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L -#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L -//ATC_L2_MEM_POWER_LS -#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 -#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 -#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL -#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L -//ATC_L2_CGTT_CLK_CTRL -#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf -#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 -#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 -#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L -#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L -#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L - - -// addressBlock: mmhub_utcl2_vml2pfdec -//VM_L2_CNTL -#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 -#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 -#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 -#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 -#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 -#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 -#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa -#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb -#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc -#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf -#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 -#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 -#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 -#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a -#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L -#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L -#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL -#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L -#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L -#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L -#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L -#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L -#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L -#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L -#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L -#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L -#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L -#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L -//VM_L2_CNTL2 -#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 -#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 -#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 -#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 -#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 -#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a -#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c -#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L -#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L -#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L -#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L -#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L -#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L -#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L -//VM_L2_CNTL3 -#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 -#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 -#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 -#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf -#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 -#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 -#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 -#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c -#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d -#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e -#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f -#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL -#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L -#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L -#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L -#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L -#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L -#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L -#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L -#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L -#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L -#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L -//VM_L2_STATUS -#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 -#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 -#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 -#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 -#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 -#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 -#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 -#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L -#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL -#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L -#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L -#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L -#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L -#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L -//VM_DUMMY_PAGE_FAULT_CNTL -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL -//VM_DUMMY_PAGE_FAULT_ADDR_LO32 -#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 -#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL -//VM_DUMMY_PAGE_FAULT_ADDR_HI32 -#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 -#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL -//VM_L2_PROTECTION_FAULT_CNTL -#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 -#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 -#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 -#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 -#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 -#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 -#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 -#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 -#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 -#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb -#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd -#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d -#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e -#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f -#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L -#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L -#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L -#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L -#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L -#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L -#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L -#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L -#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L -#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L -#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L -#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L -#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L -#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L -#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L -//VM_L2_PROTECTION_FAULT_CNTL2 -#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 -#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 -#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 -#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 -#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL -#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L -#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L -#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L -#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L -//VM_L2_PROTECTION_FAULT_MM_CNTL3 -#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL -//VM_L2_PROTECTION_FAULT_MM_CNTL4 -#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL -//VM_L2_PROTECTION_FAULT_STATUS -#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 -#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 -#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 -#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 -#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 -#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 -#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 -#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 -#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 -#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L -#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL -#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L -#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L -#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L -#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L -#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L -#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L -#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L -#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L -//VM_L2_PROTECTION_FAULT_ADDR_LO32 -#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL -//VM_L2_PROTECTION_FAULT_ADDR_HI32 -#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL -//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 -#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL -//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 -#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL -//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 -#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 -#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL -//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 -#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 -#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL -//VM_L2_CNTL4 -#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 -#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 -#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 -#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 -#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 -#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c -#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL -#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L -#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L -#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L -#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L -#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L -//VM_L2_MM_GROUP_RT_CLASSES -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L -//VM_L2_BANK_SELECT_RESERVED_CID -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa -#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L -#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L -//VM_L2_BANK_SELECT_RESERVED_CID2 -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa -#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L -#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L -//VM_L2_CACHE_PARITY_CNTL -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L -//VM_L2_CGTT_CLK_CTRL -#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf -#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 -#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 -#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L -#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L -#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L - - -// addressBlock: mmhub_utcl2_vml2vcdec -//VM_CONTEXT0_CNTL -#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT1_CNTL -#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT2_CNTL -#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT3_CNTL -#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT4_CNTL -#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT5_CNTL -#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT6_CNTL -#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT7_CNTL -#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT8_CNTL -#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT9_CNTL -#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT10_CNTL -#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT11_CNTL -#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT12_CNTL -#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT13_CNTL -#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT14_CNTL -#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT15_CNTL -#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXTS_DISABLE -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L -//VM_INVALIDATE_ENG0_SEM -#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG1_SEM -#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG2_SEM -#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG3_SEM -#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG4_SEM -#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG5_SEM -#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG6_SEM -#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG7_SEM -#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG8_SEM -#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG9_SEM -#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG10_SEM -#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG11_SEM -#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG12_SEM -#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG13_SEM -#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG14_SEM -#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG15_SEM -#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG16_SEM -#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG17_SEM -#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG0_REQ -#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG1_REQ -#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG2_REQ -#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG3_REQ -#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG4_REQ -#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG5_REQ -#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG6_REQ -#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG7_REQ -#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG8_REQ -#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG9_REQ -#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG10_REQ -#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG11_REQ -#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG12_REQ -#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG13_REQ -#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG14_REQ -#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG15_REQ -#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG16_REQ -#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG17_REQ -#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG0_ACK -#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG1_ACK -#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG2_ACK -#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG3_ACK -#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG4_ACK -#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG5_ACK -#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG6_ACK -#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG7_ACK -#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG8_ACK -#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG9_ACK -#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG10_ACK -#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG11_ACK -#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG12_ACK -#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG13_ACK -#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG14_ACK -#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG15_ACK -#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG16_ACK -#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG17_ACK -#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL - - -// addressBlock: mmhub_utcl2_vml2pldec -//MC_VM_L2_PERFCOUNTER0_CFG -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER1_CFG -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER2_CFG -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER3_CFG -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER4_CFG -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER5_CFG -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER6_CFG -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER7_CFG -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER_RSLT_CNTL -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L - - -// addressBlock: mmhub_utcl2_vml2prdec -//MC_VM_L2_PERFCOUNTER_LO -#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL -//MC_VM_L2_PERFCOUNTER_HI -#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 -#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL -#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L - - -// addressBlock: mmhub_utcl2_vmsharedhvdec -//MC_VM_FB_SIZE_OFFSET_VF0 -#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF1 -#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF2 -#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF3 -#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF4 -#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF5 -#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF6 -#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF7 -#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF8 -#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF9 -#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF10 -#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF11 -#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF12 -#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF13 -#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF14 -#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF15 -#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L -//VM_IOMMU_MMIO_CNTRL_1 -#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 -#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L -//MC_VM_MARC_BASE_LO_0 -#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc -#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L -//MC_VM_MARC_BASE_LO_1 -#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc -#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L -//MC_VM_MARC_BASE_LO_2 -#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc -#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L -//MC_VM_MARC_BASE_LO_3 -#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc -#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L -//MC_VM_MARC_BASE_HI_0 -#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 -#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL -//MC_VM_MARC_BASE_HI_1 -#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 -#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL -//MC_VM_MARC_BASE_HI_2 -#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 -#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL -//MC_VM_MARC_BASE_HI_3 -#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 -#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL -//MC_VM_MARC_RELOC_LO_0 -#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 -#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 -#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc -#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L -#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L -#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L -//MC_VM_MARC_RELOC_LO_1 -#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 -#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 -#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc -#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L -#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L -#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L -//MC_VM_MARC_RELOC_LO_2 -#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 -#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 -#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc -#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L -#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L -#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L -//MC_VM_MARC_RELOC_LO_3 -#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 -#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 -#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc -#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L -#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L -#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L -//MC_VM_MARC_RELOC_HI_0 -#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 -#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL -//MC_VM_MARC_RELOC_HI_1 -#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 -#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL -//MC_VM_MARC_RELOC_HI_2 -#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 -#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL -//MC_VM_MARC_RELOC_HI_3 -#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 -#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL -//MC_VM_MARC_LEN_LO_0 -#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc -#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L -//MC_VM_MARC_LEN_LO_1 -#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc -#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L -//MC_VM_MARC_LEN_LO_2 -#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc -#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L -//MC_VM_MARC_LEN_LO_3 -#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc -#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L -//MC_VM_MARC_LEN_HI_0 -#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 -#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL -//MC_VM_MARC_LEN_HI_1 -#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 -#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL -//MC_VM_MARC_LEN_HI_2 -#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 -#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL -//MC_VM_MARC_LEN_HI_3 -#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 -#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL -//VM_IOMMU_CONTROL_REGISTER -#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 -#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L -//VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER -#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd -#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L -//VM_PCIE_ATS_CNTL -#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 -#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L -#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_0 -#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_1 -#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_2 -#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_3 -#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_4 -#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_5 -#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_6 -#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_7 -#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_8 -#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_9 -#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_10 -#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_11 -#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_12 -#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_13 -#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_14 -#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_15 -#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L -//UTCL2_CGTT_CLK_CTRL -#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc -#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf -#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 -#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 -#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L -#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L -#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L -#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L - - -// addressBlock: mmhub_utcl2_vmsharedpfdec -//MC_VM_NB_MMIOBASE -#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 -#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL -//MC_VM_NB_MMIOLIMIT -#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 -#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL -//MC_VM_NB_PCI_CTRL -#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 -#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L -//MC_VM_NB_PCI_ARB -#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 -#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L -//MC_VM_NB_TOP_OF_DRAM_SLOT1 -#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 -#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L -//MC_VM_NB_LOWER_TOP_OF_DRAM2 -#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 -#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 -#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L -#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L -//MC_VM_NB_UPPER_TOP_OF_DRAM2 -#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 -#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL -//MC_VM_FB_OFFSET -#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 -#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL -//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB -#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 -#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL -//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB -#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 -#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL -//MC_VM_STEERING -#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 -#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L -//MC_SHARED_VIRT_RESET_REQ -#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 -#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f -#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL -#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L -//MC_MEM_POWER_LS -#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 -#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 -#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL -#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L -//MC_VM_CACHEABLE_DRAM_ADDRESS_START -#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 -#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL -//MC_VM_CACHEABLE_DRAM_ADDRESS_END -#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 -#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL -//MC_VM_APT_CNTL -#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 -#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 -#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L -#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L -//MC_VM_LOCAL_HBM_ADDRESS_START -#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 -#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL -//MC_VM_LOCAL_HBM_ADDRESS_END -#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 -#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL -//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL -#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 -#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L - - -// addressBlock: mmhub_utcl2_vmsharedvcdec -//MC_VM_FB_LOCATION_BASE -#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 -#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL -//MC_VM_FB_LOCATION_TOP -#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 -#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL -//MC_VM_AGP_TOP -#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 -#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL -//MC_VM_AGP_BOT -#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 -#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL -//MC_VM_AGP_BASE -#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 -#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL -//MC_VM_SYSTEM_APERTURE_LOW_ADDR -#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 -#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL -//MC_VM_SYSTEM_APERTURE_HIGH_ADDR -#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 -#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL -//MC_VM_MX_L1_TLB_CNTL -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 -#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 -#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 -#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 -#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb -#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L -#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L -#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L -#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L -#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L -#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L - - -// addressBlock: mmhub_utcl2_atcl2pfcntrdec -//ATC_L2_PERFCOUNTER_LO -#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 -#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL -//ATC_L2_PERFCOUNTER_HI -#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 -#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 -#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL -#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L - - -// addressBlock: mmhub_utcl2_atcl2pfcntldec -//ATC_L2_PERFCOUNTER0_CFG -#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 -#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 -#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 -#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c -#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d -#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL -#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L -#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L -//ATC_L2_PERFCOUNTER1_CFG -#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 -#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 -#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 -#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c -#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d -#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL -#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L -#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L -//ATC_L2_PERFCOUNTER_RSLT_CNTL -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L - -#endif |