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path: root/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
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Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h')
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h114
1 files changed, 55 insertions, 59 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 6b3b451a8018..6a42331aba8a 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -26,11 +26,12 @@
#include "amdgpu_smu.h"
#define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
-#define SMU11_DRIVER_IF_VERSION_VG20 0x13
-#define SMU11_DRIVER_IF_VERSION_ARCT 0x14
+#define SMU11_DRIVER_IF_VERSION_ARCT 0x17
#define SMU11_DRIVER_IF_VERSION_NV10 0x36
#define SMU11_DRIVER_IF_VERSION_NV12 0x33
#define SMU11_DRIVER_IF_VERSION_NV14 0x36
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x34
+#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x3
/* MP Apertures */
#define MP0_Public 0x03800000
@@ -48,22 +49,12 @@
#define SMU11_TOOL_SIZE 0x19000
+#define MAX_DPM_LEVELS 16
#define MAX_PCIE_CONF 2
-#define CLK_MAP(clk, index) \
- [SMU_##clk] = {1, (index)}
-
-#define FEA_MAP(fea) \
- [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT}
-
-#define TAB_MAP(tab) \
- [SMU_TABLE_##tab] = {1, TABLE_##tab}
-
-#define PWR_MAP(tab) \
- [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab}
-
-#define WORKLOAD_MAP(profile, workload) \
- [profile] = {1, (workload)}
+#define CTF_OFFSET_EDGE 5
+#define CTF_OFFSET_HOTSPOT 5
+#define CTF_OFFSET_MEM 5
static const struct smu_temperature_range smu11_thermal_policy[] =
{
@@ -71,11 +62,6 @@ static const struct smu_temperature_range smu11_thermal_policy[] =
{ 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
};
-struct smu_11_0_cmn2aisc_mapping {
- int valid_mapping;
- int map_to;
-};
-
struct smu_11_0_max_sustainable_clocks {
uint32_t display_clock;
uint32_t phy_clock;
@@ -85,9 +71,17 @@ struct smu_11_0_max_sustainable_clocks {
uint32_t soc_clock;
};
+struct smu_11_0_dpm_clk_level {
+ bool enabled;
+ uint32_t value;
+};
+
struct smu_11_0_dpm_table {
- uint32_t min; /* MHz */
- uint32_t max; /* MHz */
+ uint32_t min; /* MHz */
+ uint32_t max; /* MHz */
+ uint32_t count;
+ bool is_fine_grained;
+ struct smu_11_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS];
};
struct smu_11_0_pcie_table {
@@ -101,7 +95,9 @@ struct smu_11_0_dpm_tables {
struct smu_11_0_dpm_table uclk_table;
struct smu_11_0_dpm_table eclk_table;
struct smu_11_0_dpm_table vclk_table;
+ struct smu_11_0_dpm_table vclk1_table;
struct smu_11_0_dpm_table dclk_table;
+ struct smu_11_0_dpm_table dclk1_table;
struct smu_11_0_dpm_table dcef_table;
struct smu_11_0_dpm_table pixel_table;
struct smu_11_0_dpm_table display_table;
@@ -138,8 +134,12 @@ enum smu_v11_0_baco_seq {
BACO_SEQ_COUNT,
};
+#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
+
int smu_v11_0_init_microcode(struct smu_context *smu);
+void smu_v11_0_fini_microcode(struct smu_context *smu);
+
int smu_v11_0_load_microcode(struct smu_context *smu);
int smu_v11_0_init_smc_tables(struct smu_context *smu);
@@ -156,20 +156,8 @@ int smu_v11_0_setup_pptable(struct smu_context *smu);
int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu);
-int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu);
-
-int smu_v11_0_check_pptable(struct smu_context *smu);
-
-int smu_v11_0_parse_pptable(struct smu_context *smu);
-
-int smu_v11_0_populate_smc_pptable(struct smu_context *smu);
-
int smu_v11_0_check_fw_version(struct smu_context *smu);
-int smu_v11_0_write_pptable(struct smu_context *smu);
-
-int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu);
-
int smu_v11_0_set_driver_table_location(struct smu_context *smu);
int smu_v11_0_set_tool_table_location(struct smu_context *smu);
@@ -179,38 +167,26 @@ int smu_v11_0_notify_memory_pool_location(struct smu_context *smu);
int smu_v11_0_system_features_control(struct smu_context *smu,
bool en);
-int
-smu_v11_0_send_msg_with_param(struct smu_context *smu,
- enum smu_message_type msg,
- uint32_t param,
- uint32_t *read_arg);
-
int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count);
int smu_v11_0_set_allowed_mask(struct smu_context *smu);
-int smu_v11_0_get_enabled_mask(struct smu_context *smu,
- uint32_t *feature_mask, uint32_t num);
-
int smu_v11_0_notify_display_change(struct smu_context *smu);
-int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n);
+int smu_v11_0_get_current_power_limit(struct smu_context *smu,
+ uint32_t *power_limit);
-int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
- enum smu_clk_type clk_id,
- uint32_t *value);
+int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n);
int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu);
-int smu_v11_0_start_thermal_control(struct smu_context *smu);
+int smu_v11_0_enable_thermal_alert(struct smu_context *smu);
-int smu_v11_0_stop_thermal_control(struct smu_context *smu);
+int smu_v11_0_disable_thermal_alert(struct smu_context *smu);
-int smu_v11_0_read_sensor(struct smu_context *smu,
- enum amd_pp_sensors sensor,
- void *data, uint32_t *size);
+int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value);
-int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
+int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
int
smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
@@ -251,17 +227,18 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
int smu_v11_0_baco_enter(struct smu_context *smu);
int smu_v11_0_baco_exit(struct smu_context *smu);
+int smu_v11_0_mode1_reset(struct smu_context *smu);
+
int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t *min, uint32_t *max);
int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t min, uint32_t max);
-int smu_v11_0_override_pcie_parameters(struct smu_context *smu);
-
-int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, size_t overdrive_table_size);
-
-uint32_t smu_v11_0_get_max_power_limit(struct smu_context *smu);
+int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ uint32_t min,
+ uint32_t max);
int smu_v11_0_set_performance_level(struct smu_context *smu,
enum amd_dpm_forced_level level);
@@ -269,4 +246,23 @@ int smu_v11_0_set_performance_level(struct smu_context *smu,
int smu_v11_0_set_power_source(struct smu_context *smu,
enum smu_power_src_type power_src);
+int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ uint16_t level,
+ uint32_t *value);
+
+int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ uint32_t *value);
+
+int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ struct smu_11_0_dpm_table *single_dpm_table);
+
+int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ uint32_t *min_value,
+ uint32_t *max_value);
+
+#endif
#endif
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.