diff options
Diffstat (limited to 'drivers/gpu/drm/bridge/tc358767.c')
| -rw-r--r-- | drivers/gpu/drm/bridge/tc358767.c | 683 |
1 files changed, 402 insertions, 281 deletions
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 13ade28a36a8..cebc8e620820 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -15,6 +15,7 @@ * Author: Rob Clark <robdclark@gmail.com> */ +#include <linux/bitfield.h> #include <linux/clk.h> #include <linux/device.h> #include <linux/gpio/consumer.h> @@ -47,6 +48,7 @@ /* Video Path */ #define VPCTRL0 0x0450 +#define VSDELAY GENMASK(31, 20) #define OPXLFMT_RGB666 (0 << 8) #define OPXLFMT_RGB888 (1 << 8) #define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */ @@ -54,9 +56,17 @@ #define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */ #define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */ #define HTIM01 0x0454 +#define HPW GENMASK(8, 0) +#define HBPR GENMASK(24, 16) #define HTIM02 0x0458 +#define HDISPR GENMASK(10, 0) +#define HFPR GENMASK(24, 16) #define VTIM01 0x045c +#define VSPR GENMASK(7, 0) +#define VBPR GENMASK(23, 16) #define VTIM02 0x0460 +#define VFPR GENMASK(23, 16) +#define VDISPR GENMASK(10, 0) #define VFUEN0 0x0464 #define VFUEN BIT(0) /* Video Frame Timing Upload */ @@ -70,6 +80,13 @@ #define DP0_VIDSRC_DSI_RX (1 << 0) #define DP0_VIDSRC_DPI_RX (2 << 0) #define DP0_VIDSRC_COLOR_BAR (3 << 0) +#define SYSRSTENB 0x050c +#define ENBI2C (1 << 0) +#define ENBLCD0 (1 << 2) +#define ENBBM (1 << 3) +#define ENBDSIRX (1 << 4) +#define ENBREG (1 << 5) +#define ENBHDCP (1 << 8) #define GPIOM 0x0540 #define GPIOC 0x0544 #define GPIOO 0x0548 @@ -99,19 +116,35 @@ /* Main Channel */ #define DP0_SECSAMPLE 0x0640 #define DP0_VIDSYNCDELAY 0x0644 +#define VID_SYNC_DLY GENMASK(15, 0) +#define THRESH_DLY GENMASK(31, 16) + #define DP0_TOTALVAL 0x0648 +#define H_TOTAL GENMASK(15, 0) +#define V_TOTAL GENMASK(31, 16) #define DP0_STARTVAL 0x064c +#define H_START GENMASK(15, 0) +#define V_START GENMASK(31, 16) #define DP0_ACTIVEVAL 0x0650 +#define H_ACT GENMASK(15, 0) +#define V_ACT GENMASK(31, 16) + #define DP0_SYNCVAL 0x0654 +#define VS_WIDTH GENMASK(30, 16) +#define HS_WIDTH GENMASK(14, 0) #define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15) #define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31) #define DP0_MISC 0x0658 #define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */ +#define MAX_TU_SYMBOL GENMASK(28, 23) +#define TU_SIZE GENMASK(21, 16) #define BPC_6 (0 << 5) #define BPC_8 (1 << 5) /* AUX channel */ #define DP0_AUXCFG0 0x0660 +#define DP0_AUXCFG0_BSIZE GENMASK(11, 8) +#define DP0_AUXCFG0_ADDR_ONLY BIT(4) #define DP0_AUXCFG1 0x0664 #define AUX_RX_FILTER_EN BIT(16) @@ -119,10 +152,10 @@ #define DP0_AUXWDATA(i) (0x066c + (i) * 4) #define DP0_AUXRDATA(i) (0x067c + (i) * 4) #define DP0_AUXSTATUS 0x068c -#define AUX_STATUS_MASK 0xf0 -#define AUX_STATUS_SHIFT 4 -#define AUX_TIMEOUT BIT(1) -#define AUX_BUSY BIT(0) +#define AUX_BYTES GENMASK(15, 8) +#define AUX_STATUS GENMASK(7, 4) +#define AUX_TIMEOUT BIT(1) +#define AUX_BUSY BIT(0) #define DP0_AUXI2CADR 0x0698 /* Link Training */ @@ -183,6 +216,12 @@ /* Test & Debug */ #define TSTCTL 0x0a00 +#define COLOR_R GENMASK(31, 24) +#define COLOR_G GENMASK(23, 16) +#define COLOR_B GENMASK(15, 8) +#define ENI2CFILTER BIT(4) +#define COLOR_BAR_MODE GENMASK(1, 0) +#define COLOR_BAR_MODE_BARS 2 #define PLL_DBG 0x0a04 static bool tc_test_pattern; @@ -241,137 +280,131 @@ static inline struct tc_data *connector_to_tc(struct drm_connector *c) return container_of(c, struct tc_data, connector); } -/* Simple macros to avoid repeated error checks */ -#define tc_write(reg, var) \ - do { \ - ret = regmap_write(tc->regmap, reg, var); \ - if (ret) \ - goto err; \ - } while (0) -#define tc_read(reg, var) \ - do { \ - ret = regmap_read(tc->regmap, reg, var); \ - if (ret) \ - goto err; \ - } while (0) - -static inline int tc_poll_timeout(struct regmap *map, unsigned int addr, +static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr, unsigned int cond_mask, unsigned int cond_value, unsigned long sleep_us, u64 timeout_us) { - ktime_t timeout = ktime_add_us(ktime_get(), timeout_us); unsigned int val; - int ret; - for (;;) { - ret = regmap_read(map, addr, &val); - if (ret) - break; - if ((val & cond_mask) == cond_value) - break; - if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) { - ret = regmap_read(map, addr, &val); - break; - } - if (sleep_us) - usleep_range((sleep_us >> 2) + 1, sleep_us); - } - return ret ?: (((val & cond_mask) == cond_value) ? 0 : -ETIMEDOUT); + return regmap_read_poll_timeout(tc->regmap, addr, val, + (val & cond_mask) == cond_value, + sleep_us, timeout_us); } -static int tc_aux_wait_busy(struct tc_data *tc, unsigned int timeout_ms) +static int tc_aux_wait_busy(struct tc_data *tc) { - return tc_poll_timeout(tc->regmap, DP0_AUXSTATUS, AUX_BUSY, 0, - 1000, 1000 * timeout_ms); + return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 1000, 100000); } -static int tc_aux_get_status(struct tc_data *tc, u8 *reply) +static int tc_aux_write_data(struct tc_data *tc, const void *data, + size_t size) { - int ret; - u32 value; + u32 auxwdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)] = { 0 }; + int ret, count = ALIGN(size, sizeof(u32)); - ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &value); - if (ret < 0) + memcpy(auxwdata, data, size); + + ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count); + if (ret) return ret; - if (value & AUX_BUSY) { - dev_err(tc->dev, "aux busy!\n"); - return -EBUSY; - } + return size; +} - if (value & AUX_TIMEOUT) { - dev_err(tc->dev, "aux access timeout!\n"); - return -ETIMEDOUT; - } +static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size) +{ + u32 auxrdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)]; + int ret, count = ALIGN(size, sizeof(u32)); - *reply = (value & AUX_STATUS_MASK) >> AUX_STATUS_SHIFT; - return 0; + ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count); + if (ret) + return ret; + + memcpy(data, auxrdata, size); + + return size; +} + +static u32 tc_auxcfg0(struct drm_dp_aux_msg *msg, size_t size) +{ + u32 auxcfg0 = msg->request; + + if (size) + auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1); + else + auxcfg0 |= DP0_AUXCFG0_ADDR_ONLY; + + return auxcfg0; } static ssize_t tc_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) { struct tc_data *tc = aux_to_tc(aux); - size_t size = min_t(size_t, 8, msg->size); + size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size); u8 request = msg->request & ~DP_AUX_I2C_MOT; - u8 *buf = msg->buffer; - u32 tmp = 0; - int i = 0; + u32 auxstatus; int ret; - if (size == 0) - return 0; - - ret = tc_aux_wait_busy(tc, 100); + ret = tc_aux_wait_busy(tc); if (ret) - goto err; + return ret; - if (request == DP_AUX_I2C_WRITE || request == DP_AUX_NATIVE_WRITE) { - /* Store data */ - while (i < size) { - if (request == DP_AUX_NATIVE_WRITE) - tmp = tmp | (buf[i] << (8 * (i & 0x3))); - else - tmp = (tmp << 8) | buf[i]; - i++; - if (((i % 4) == 0) || (i == size)) { - tc_write(DP0_AUXWDATA((i - 1) >> 2), tmp); - tmp = 0; - } + switch (request) { + case DP_AUX_NATIVE_READ: + case DP_AUX_I2C_READ: + break; + case DP_AUX_NATIVE_WRITE: + case DP_AUX_I2C_WRITE: + if (size) { + ret = tc_aux_write_data(tc, msg->buffer, size); + if (ret < 0) + return ret; } - } else if (request != DP_AUX_I2C_READ && - request != DP_AUX_NATIVE_READ) { + break; + default: return -EINVAL; } /* Store address */ - tc_write(DP0_AUXADDR, msg->address); + ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address); + if (ret) + return ret; /* Start transfer */ - tc_write(DP0_AUXCFG0, ((size - 1) << 8) | request); + ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size)); + if (ret) + return ret; - ret = tc_aux_wait_busy(tc, 100); + ret = tc_aux_wait_busy(tc); if (ret) - goto err; + return ret; - ret = tc_aux_get_status(tc, &msg->reply); + ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus); if (ret) - goto err; + return ret; - if (request == DP_AUX_I2C_READ || request == DP_AUX_NATIVE_READ) { - /* Read data */ - while (i < size) { - if ((i % 4) == 0) - tc_read(DP0_AUXRDATA(i >> 2), &tmp); - buf[i] = tmp & 0xff; - tmp = tmp >> 8; - i++; - } + if (auxstatus & AUX_TIMEOUT) + return -ETIMEDOUT; + /* + * For some reason address-only DP_AUX_I2C_WRITE (MOT), still + * reports 1 byte transferred in its status. To deal we that + * we ignore aux_bytes field if we know that this was an + * address-only transfer + */ + if (size) + size = FIELD_GET(AUX_BYTES, auxstatus); + msg->reply = FIELD_GET(AUX_STATUS, auxstatus); + + switch (request) { + case DP_AUX_NATIVE_READ: + case DP_AUX_I2C_READ: + if (size) + return tc_aux_read_data(tc, msg->buffer, size); + break; } return size; -err: - return ret; } static const char * const training_pattern1_errors[] = { @@ -411,10 +444,18 @@ static u32 tc_srcctrl(struct tc_data *tc) return reg; } -static void tc_wait_pll_lock(struct tc_data *tc) +static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl) { + int ret; + + ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN); + if (ret) + return ret; + /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */ usleep_range(3000, 6000); + + return 0; } static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) @@ -428,6 +469,7 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) int ext_div[] = {1, 2, 3, 5, 7}; int best_pixelclock = 0; int vco_hi = 0; + u32 pxl_pllparam; dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock, refclk); @@ -497,24 +539,23 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) best_mul = 0; /* Power up PLL and switch to bypass */ - tc_write(PXL_PLLCTRL, PLLBYP | PLLEN); - - tc_write(PXL_PLLPARAM, - (vco_hi << 24) | /* For PLL VCO >= 300 MHz = 1 */ - (ext_div[best_pre] << 20) | /* External Pre-divider */ - (ext_div[best_post] << 16) | /* External Post-divider */ - IN_SEL_REFCLK | /* Use RefClk as PLL input */ - (best_div << 8) | /* Divider for PLL RefClk */ - (best_mul << 0)); /* Multiplier for PLL */ + ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN); + if (ret) + return ret; - /* Force PLL parameter update and disable bypass */ - tc_write(PXL_PLLCTRL, PLLUPDATE | PLLEN); + pxl_pllparam = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */ + pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */ + pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */ + pxl_pllparam |= IN_SEL_REFCLK; /* Use RefClk as PLL input */ + pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */ + pxl_pllparam |= best_mul; /* Multiplier for PLL */ - tc_wait_pll_lock(tc); + ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam); + if (ret) + return ret; - return 0; -err: - return ret; + /* Force PLL parameter update and disable bypass */ + return tc_pllupdate(tc, PXL_PLLCTRL); } static int tc_pxl_pll_dis(struct tc_data *tc) @@ -525,7 +566,6 @@ static int tc_pxl_pll_dis(struct tc_data *tc) static int tc_stream_clock_calc(struct tc_data *tc) { - int ret; /* * If the Stream clock and Link Symbol clock are * asynchronous with each other, the value of M changes over @@ -541,56 +581,63 @@ static int tc_stream_clock_calc(struct tc_data *tc) * M/N = f_STRMCLK / f_LSCLK * */ - tc_write(DP0_VIDMNGEN1, 32768); - - return 0; -err: - return ret; + return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768); } -static int tc_aux_link_setup(struct tc_data *tc) +static int tc_set_syspllparam(struct tc_data *tc) { unsigned long rate; - u32 value; - int ret; + u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2; rate = clk_get_rate(tc->refclk); switch (rate) { case 38400000: - value = REF_FREQ_38M4; + pllparam |= REF_FREQ_38M4; break; case 26000000: - value = REF_FREQ_26M; + pllparam |= REF_FREQ_26M; break; case 19200000: - value = REF_FREQ_19M2; + pllparam |= REF_FREQ_19M2; break; case 13000000: - value = REF_FREQ_13M; + pllparam |= REF_FREQ_13M; break; default: dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate); return -EINVAL; } - /* Setup DP-PHY / PLL */ - value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2; - tc_write(SYS_PLLPARAM, value); + return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam); +} + +static int tc_aux_link_setup(struct tc_data *tc) +{ + int ret; + u32 dp0_auxcfg1; - tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | PHY_A0_EN); + /* Setup DP-PHY / PLL */ + ret = tc_set_syspllparam(tc); + if (ret) + goto err; + ret = regmap_write(tc->regmap, DP_PHY_CTRL, + BGREN | PWR_SW_EN | PHY_A0_EN); + if (ret) + goto err; /* * Initially PLLs are in bypass. Force PLL parameter update, * disable PLL bypass, enable PLL */ - tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN); - tc_wait_pll_lock(tc); + ret = tc_pllupdate(tc, DP0_PLLCTRL); + if (ret) + goto err; - tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN); - tc_wait_pll_lock(tc); + ret = tc_pllupdate(tc, DP1_PLLCTRL); + if (ret) + goto err; - ret = tc_poll_timeout(tc->regmap, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, - 1000); + ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 1000); if (ret == -ETIMEDOUT) { dev_err(tc->dev, "Timeout waiting for PHY to become ready"); return ret; @@ -599,9 +646,13 @@ static int tc_aux_link_setup(struct tc_data *tc) } /* Setup AUX link */ - tc_write(DP0_AUXCFG1, AUX_RX_FILTER_EN | - (0x06 << 8) | /* Aux Bit Period Calculator Threshold */ - (0x3f << 0)); /* Aux Response Timeout Timer */ + dp0_auxcfg1 = AUX_RX_FILTER_EN; + dp0_auxcfg1 |= 0x06 << 8; /* Aux Bit Period Calculator Threshold */ + dp0_auxcfg1 |= 0x3f << 0; /* Aux Response Timeout Timer */ + + ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1); + if (ret) + goto err; return 0; err: @@ -612,8 +663,7 @@ err: static int tc_get_display_props(struct tc_data *tc) { int ret; - /* temp buffer */ - u8 tmp[8]; + u8 reg; /* Read DP Rx Link Capability */ ret = drm_dp_link_probe(&tc->aux, &tc->link.base); @@ -629,21 +679,21 @@ static int tc_get_display_props(struct tc_data *tc) tc->link.base.num_lanes = 2; } - ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, tmp); + ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, ®); if (ret < 0) goto err_dpcd_read; - tc->link.spread = tmp[0] & DP_MAX_DOWNSPREAD_0_5; + tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5; - ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, tmp); + ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, ®); if (ret < 0) goto err_dpcd_read; tc->link.scrambler_dis = false; /* read assr */ - ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, tmp); + ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, ®); if (ret < 0) goto err_dpcd_read; - tc->link.assr = tmp[0] & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; + tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n", tc->link.base.revision >> 4, tc->link.base.revision & 0x0f, @@ -677,6 +727,7 @@ static int tc_set_video_mode(struct tc_data *tc, int upper_margin = mode->vtotal - mode->vsync_end; int lower_margin = mode->vsync_start - mode->vdisplay; int vsync_len = mode->vsync_end - mode->vsync_start; + u32 dp0_syncval; /* * Recommended maximum number of symbols transferred in a transfer unit: @@ -701,156 +752,193 @@ static int tc_set_video_mode(struct tc_data *tc, * assume we do not need any delay when DPI is a source of * sync signals */ - tc_write(VPCTRL0, (0 << 20) /* VSDELAY */ | - OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED); - tc_write(HTIM01, (ALIGN(left_margin, 2) << 16) | /* H back porch */ - (ALIGN(hsync_len, 2) << 0)); /* Hsync */ - tc_write(HTIM02, (ALIGN(right_margin, 2) << 16) | /* H front porch */ - (ALIGN(mode->hdisplay, 2) << 0)); /* width */ - tc_write(VTIM01, (upper_margin << 16) | /* V back porch */ - (vsync_len << 0)); /* Vsync */ - tc_write(VTIM02, (lower_margin << 16) | /* V front porch */ - (mode->vdisplay << 0)); /* height */ - tc_write(VFUEN0, VFUEN); /* update settings */ + ret = regmap_write(tc->regmap, VPCTRL0, + FIELD_PREP(VSDELAY, 0) | + OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED); + if (ret) + return ret; + + ret = regmap_write(tc->regmap, HTIM01, + FIELD_PREP(HBPR, ALIGN(left_margin, 2)) | + FIELD_PREP(HPW, ALIGN(hsync_len, 2))); + if (ret) + return ret; + + ret = regmap_write(tc->regmap, HTIM02, + FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) | + FIELD_PREP(HFPR, ALIGN(right_margin, 2))); + if (ret) + return ret; + + ret = regmap_write(tc->regmap, VTIM01, + FIELD_PREP(VBPR, upper_margin) | + FIELD_PREP(VSPR, vsync_len)); + if (ret) + return ret; + + ret = regmap_write(tc->regmap, VTIM02, + FIELD_PREP(VFPR, lower_margin) | + FIELD_PREP(VDISPR, mode->vdisplay)); + if (ret) + return ret; + + ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */ + if (ret) + return ret; /* Test pattern settings */ - tc_write(TSTCTL, - (120 << 24) | /* Red Color component value */ - (20 << 16) | /* Green Color component value */ - (99 << 8) | /* Blue Color component value */ - (1 << 4) | /* Enable I2C Filter */ - (2 << 0) | /* Color bar Mode */ - 0); + ret = regmap_write(tc->regmap, TSTCTL, + FIELD_PREP(COLOR_R, 120) | + FIELD_PREP(COLOR_G, 20) | + FIELD_PREP(COLOR_B, 99) | + ENI2CFILTER | + FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS)); + if (ret) + return ret; /* DP Main Stream Attributes */ vid_sync_dly = hsync_len + left_margin + mode->hdisplay; - tc_write(DP0_VIDSYNCDELAY, - (max_tu_symbol << 16) | /* thresh_dly */ - (vid_sync_dly << 0)); + ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY, + FIELD_PREP(THRESH_DLY, max_tu_symbol) | + FIELD_PREP(VID_SYNC_DLY, vid_sync_dly)); - tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal)); + ret = regmap_write(tc->regmap, DP0_TOTALVAL, + FIELD_PREP(H_TOTAL, mode->htotal) | + FIELD_PREP(V_TOTAL, mode->vtotal)); + if (ret) + return ret; - tc_write(DP0_STARTVAL, - ((upper_margin + vsync_len) << 16) | - ((left_margin + hsync_len) << 0)); + ret = regmap_write(tc->regmap, DP0_STARTVAL, + FIELD_PREP(H_START, left_margin + hsync_len) | + FIELD_PREP(V_START, upper_margin + vsync_len)); + if (ret) + return ret; + + ret = regmap_write(tc->regmap, DP0_ACTIVEVAL, + FIELD_PREP(V_ACT, mode->vdisplay) | + FIELD_PREP(H_ACT, mode->hdisplay)); + if (ret) + return ret; - tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay)); + dp0_syncval = FIELD_PREP(VS_WIDTH, vsync_len) | + FIELD_PREP(HS_WIDTH, hsync_len); - tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0) | - ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? SYNCVAL_HS_POL_ACTIVE_LOW : 0) | - ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? SYNCVAL_VS_POL_ACTIVE_LOW : 0)); + if (mode->flags & DRM_MODE_FLAG_NVSYNC) + dp0_syncval |= SYNCVAL_VS_POL_ACTIVE_LOW; - tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW | - DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888); + if (mode->flags & DRM_MODE_FLAG_NHSYNC) + dp0_syncval |= SYNCVAL_HS_POL_ACTIVE_LOW; - tc_write(DP0_MISC, (max_tu_symbol << 23) | (TU_SIZE_RECOMMENDED << 16) | + ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval); + if (ret) + return ret; + + ret = regmap_write(tc->regmap, DPIPXLFMT, + VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW | + DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | + DPI_BPP_RGB888); + if (ret) + return ret; + + ret = regmap_write(tc->regmap, DP0_MISC, + FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) | + FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) | BPC_8); + if (ret) + return ret; return 0; -err: - return ret; } static int tc_wait_link_training(struct tc_data *tc) { - u32 timeout = 1000; u32 value; int ret; - do { - udelay(1); - tc_read(DP0_LTSTAT, &value); - } while ((!(value & LT_LOOPDONE)) && (--timeout)); - - if (timeout == 0) { + ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE, + LT_LOOPDONE, 1, 1000); + if (ret) { dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n"); - return -ETIMEDOUT; + return ret; } - return (value >> 8) & 0x7; + ret = regmap_read(tc->regmap, DP0_LTSTAT, &value); + if (ret) + return ret; -err: - return ret; + return (value >> 8) & 0x7; } static int tc_main_link_enable(struct tc_data *tc) { struct drm_dp_aux *aux = &tc->aux; struct device *dev = tc->dev; - unsigned int rate; u32 dp_phy_ctrl; - int timeout; u32 value; int ret; - u8 tmp[8]; + u8 tmp[DP_LINK_STATUS_SIZE]; dev_dbg(tc->dev, "link enable\n"); - tc_read(DP0CTL, &value); - if (WARN_ON(value & DP_EN)) - tc_write(DP0CTL, 0); + ret = regmap_read(tc->regmap, DP0CTL, &value); + if (ret) + return ret; + + if (WARN_ON(value & DP_EN)) { + ret = regmap_write(tc->regmap, DP0CTL, 0); + if (ret) + return ret; + } - tc_write(DP0_SRCCTRL, tc_srcctrl(tc)); + ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc)); + if (ret) + return ret; /* SSCG and BW27 on DP1 must be set to the same as on DP0 */ - tc_write(DP1_SRCCTRL, + ret = regmap_write(tc->regmap, DP1_SRCCTRL, (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) | ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0)); + if (ret) + return ret; - rate = clk_get_rate(tc->refclk); - switch (rate) { - case 38400000: - value = REF_FREQ_38M4; - break; - case 26000000: - value = REF_FREQ_26M; - break; - case 19200000: - value = REF_FREQ_19M2; - break; - case 13000000: - value = REF_FREQ_13M; - break; - default: - return -EINVAL; - } - value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2; - tc_write(SYS_PLLPARAM, value); + ret = tc_set_syspllparam(tc); + if (ret) + return ret; /* Setup Main Link */ dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN; if (tc->link.base.num_lanes == 2) dp_phy_ctrl |= PHY_2LANE; - tc_write(DP_PHY_CTRL, dp_phy_ctrl); + + ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); + if (ret) + return ret; /* PLL setup */ - tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN); - tc_wait_pll_lock(tc); + ret = tc_pllupdate(tc, DP0_PLLCTRL); + if (ret) + return ret; - tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN); - tc_wait_pll_lock(tc); + ret = tc_pllupdate(tc, DP1_PLLCTRL); + if (ret) + return ret; /* Reset/Enable Main Links */ dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST; - tc_write(DP_PHY_CTRL, dp_phy_ctrl); + ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); usleep_range(100, 200); dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST); - tc_write(DP_PHY_CTRL, dp_phy_ctrl); - - timeout = 1000; - do { - tc_read(DP_PHY_CTRL, &value); - udelay(1); - } while ((!(value & PHY_RDY)) && (--timeout)); + ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); - if (timeout == 0) { + ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 1000); + if (ret) { dev_err(dev, "timeout waiting for phy become ready"); - return -ETIMEDOUT; + return ret; } /* Set misc: 8 bits per color */ ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8); if (ret) - goto err; + return ret; /* * ASSR mode @@ -903,53 +991,71 @@ static int tc_main_link_enable(struct tc_data *tc) /* Clock-Recovery */ /* Set DPCD 0x102 for Training Pattern 1 */ - tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | - DP_TRAINING_PATTERN_1); + ret = regmap_write(tc->regmap, DP0_SNKLTCTRL, + DP_LINK_SCRAMBLING_DISABLE | + DP_TRAINING_PATTERN_1); + if (ret) + return ret; - tc_write(DP0_LTLOOPCTRL, - (15 << 28) | /* Defer Iteration Count */ - (15 << 24) | /* Loop Iteration Count */ - (0xd << 0)); /* Loop Timer Delay */ + ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL, + (15 << 28) | /* Defer Iteration Count */ + (15 << 24) | /* Loop Iteration Count */ + (0xd << 0)); /* Loop Timer Delay */ + if (ret) + return ret; - tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | - DP0_SRCCTRL_AUTOCORRECT | DP0_SRCCTRL_TP1); + ret = regmap_write(tc->regmap, DP0_SRCCTRL, + tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | + DP0_SRCCTRL_AUTOCORRECT | + DP0_SRCCTRL_TP1); + if (ret) + return ret; /* Enable DP0 to start Link Training */ - tc_write(DP0CTL, - ((tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ? EF_EN : 0) | - DP_EN); + ret = regmap_write(tc->regmap, DP0CTL, + ((tc->link.base.capabilities & + DP_LINK_CAP_ENHANCED_FRAMING) ? EF_EN : 0) | + DP_EN); + if (ret) + return ret; /* wait */ + ret = tc_wait_link_training(tc); if (ret < 0) - goto err; + return ret; if (ret) { dev_err(tc->dev, "Link training phase 1 failed: %s\n", training_pattern1_errors[ret]); - ret = -ENODEV; - goto err; + return -ENODEV; } /* Channel Equalization */ /* Set DPCD 0x102 for Training Pattern 2 */ - tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | - DP_TRAINING_PATTERN_2); + ret = regmap_write(tc->regmap, DP0_SNKLTCTRL, + DP_LINK_SCRAMBLING_DISABLE | + DP_TRAINING_PATTERN_2); + if (ret) + return ret; - tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | - DP0_SRCCTRL_AUTOCORRECT | DP0_SRCCTRL_TP2); + ret = regmap_write(tc->regmap, DP0_SRCCTRL, + tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | + DP0_SRCCTRL_AUTOCORRECT | + DP0_SRCCTRL_TP2); + if (ret) + return ret; /* wait */ ret = tc_wait_link_training(tc); if (ret < 0) - goto err; + return ret; if (ret) { dev_err(tc->dev, "Link training phase 2 failed: %s\n", training_pattern2_errors[ret]); - ret = -ENODEV; - goto err; + return -ENODEV; } /* @@ -962,7 +1068,10 @@ static int tc_main_link_enable(struct tc_data *tc) */ /* Clear Training Pattern, set AutoCorrect Mode = 1 */ - tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_AUTOCORRECT); + ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) | + DP0_SRCCTRL_AUTOCORRECT); + if (ret) + return ret; /* Clear DPCD 0x102 */ /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */ @@ -1006,7 +1115,7 @@ static int tc_main_link_enable(struct tc_data *tc) dev_err(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[3]); dev_err(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n", tmp[4]); dev_err(dev, "0x0207 ADJUST_REQUEST_LANE2_3: 0x%02x\n", tmp[5]); - goto err; + return ret; } return 0; @@ -1015,7 +1124,6 @@ err_dpcd_read: return ret; err_dpcd_write: dev_err(tc->dev, "Failed to write DPCD: %d\n", ret); -err: return ret; } @@ -1025,12 +1133,11 @@ static int tc_main_link_disable(struct tc_data *tc) dev_dbg(tc->dev, "link disable\n"); - tc_write(DP0_SRCCTRL, 0); - tc_write(DP0CTL, 0); + ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0); + if (ret) + return ret; - return 0; -err: - return ret; + return regmap_write(tc->regmap, DP0CTL, 0); } static int tc_stream_enable(struct tc_data *tc) @@ -1045,7 +1152,7 @@ static int tc_stream_enable(struct tc_data *tc) ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), 1000 * tc->mode.clock); if (ret) - goto err; + return ret; } ret = tc_set_video_mode(tc, &tc->mode); @@ -1060,7 +1167,9 @@ static int tc_stream_enable(struct tc_data *tc) value = VID_MN_GEN | DP_EN; if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) value |= EF_EN; - tc_write(DP0CTL, value); + ret = regmap_write(tc->regmap, DP0CTL, value); + if (ret) + return ret; /* * VID_EN assertion should be delayed by at least N * LSCLK * cycles from the time VID_MN_GEN is enabled in order to @@ -1070,36 +1179,35 @@ static int tc_stream_enable(struct tc_data *tc) */ usleep_range(500, 1000); value |= VID_EN; - tc_write(DP0CTL, value); + ret = regmap_write(tc->regmap, DP0CTL, value); + if (ret) + return ret; /* Set input interface */ value = DP0_AUDSRC_NO_INPUT; if (tc_test_pattern) value |= DP0_VIDSRC_COLOR_BAR; else value |= DP0_VIDSRC_DPI_RX; - tc_write(SYSCTRL, value); + ret = regmap_write(tc->regmap, SYSCTRL, value); + if (ret) + return ret; return 0; -err: - return ret; } static int tc_stream_disable(struct tc_data *tc) { int ret; - u32 val; dev_dbg(tc->dev, "disable video stream\n"); - tc_read(DP0CTL, &val); - val &= ~VID_EN; - tc_write(DP0CTL, val); + ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0); + if (ret) + return ret; tc_pxl_pll_dis(tc); return 0; -err: - return ret; } static void tc_bridge_pre_enable(struct drm_bridge *bridge) @@ -1204,7 +1312,7 @@ static int tc_connector_get_modes(struct drm_connector *connector) { struct tc_data *tc = connector_to_tc(connector); struct edid *edid; - unsigned int count; + int count; int ret; ret = tc_get_display_props(tc); @@ -1213,11 +1321,9 @@ static int tc_connector_get_modes(struct drm_connector *connector) return 0; } - if (tc->panel && tc->panel->funcs && tc->panel->funcs->get_modes) { - count = tc->panel->funcs->get_modes(tc->panel); - if (count > 0) - return count; - } + count = drm_panel_get_modes(tc->panel); + if (count > 0) + return count; edid = drm_get_edid(connector, &tc->aux.ddc); @@ -1251,7 +1357,9 @@ static enum drm_connector_status tc_connector_detect(struct drm_connector *conne return connector_status_unknown; } - tc_read(GPIOI, &val); + ret = regmap_read(tc->regmap, GPIOI, &val); + if (ret) + return connector_status_unknown; conn = val & BIT(tc->hpd_pin); @@ -1259,9 +1367,6 @@ static enum drm_connector_status tc_connector_detect(struct drm_connector *conne return connector_status_connected; else return connector_status_disconnected; - -err: - return connector_status_unknown; } static const struct drm_connector_funcs tc_connector_funcs = { @@ -1497,6 +1602,22 @@ static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id) tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */ + if (!tc->reset_gpio) { + /* + * If the reset pin isn't present, do a software reset. It isn't + * as thorough as the hardware reset, as we can't reset the I2C + * communication block for obvious reasons, but it's getting the + * chip into a defined state. + */ + regmap_update_bits(tc->regmap, SYSRSTENB, + ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP, + 0); + regmap_update_bits(tc->regmap, SYSRSTENB, + ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP, + ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP); + usleep_range(5000, 10000); + } + if (tc->hpd_pin >= 0) { u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT; u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin); |