diff options
Diffstat (limited to 'drivers/gpu/drm/msm/disp')
55 files changed, 816 insertions, 4899 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c index 879c13fe74e0..e45c69044935 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c @@ -319,10 +319,8 @@ static int dpu_debugfs_core_irq_show(struct seq_file *s, void *v) unsigned long irq_flags; int i, irq_count, enable_count, cb_count; - if (!irq_obj || !irq_obj->enable_counts || !irq_obj->irq_cb_tbl) { - DPU_ERROR("invalid parameters\n"); + if (WARN_ON(!irq_obj->enable_counts || !irq_obj->irq_cb_tbl)) return 0; - } for (i = 0; i < irq_obj->total_irqs; i++) { spin_lock_irqsave(&irq_obj->cb_lock, irq_flags); @@ -343,31 +341,11 @@ static int dpu_debugfs_core_irq_show(struct seq_file *s, void *v) DEFINE_DPU_DEBUGFS_SEQ_FOPS(dpu_debugfs_core_irq); -int dpu_debugfs_core_irq_init(struct dpu_kms *dpu_kms, - struct dentry *parent) -{ - dpu_kms->irq_obj.debugfs_file = debugfs_create_file("core_irq", 0600, - parent, &dpu_kms->irq_obj, - &dpu_debugfs_core_irq_fops); - - return 0; -} - -void dpu_debugfs_core_irq_destroy(struct dpu_kms *dpu_kms) -{ - debugfs_remove(dpu_kms->irq_obj.debugfs_file); - dpu_kms->irq_obj.debugfs_file = NULL; -} - -#else -int dpu_debugfs_core_irq_init(struct dpu_kms *dpu_kms, +void dpu_debugfs_core_irq_init(struct dpu_kms *dpu_kms, struct dentry *parent) { - return 0; -} - -void dpu_debugfs_core_irq_destroy(struct dpu_kms *dpu_kms) -{ + debugfs_create_file("core_irq", 0600, parent, &dpu_kms->irq_obj, + &dpu_debugfs_core_irq_fops); } #endif @@ -376,10 +354,7 @@ void dpu_core_irq_preinstall(struct dpu_kms *dpu_kms) struct msm_drm_private *priv; int i; - if (!dpu_kms) { - DPU_ERROR("invalid dpu_kms\n"); - return; - } else if (!dpu_kms->dev) { + if (!dpu_kms->dev) { DPU_ERROR("invalid drm device\n"); return; } else if (!dpu_kms->dev->dev_private) { @@ -410,20 +385,12 @@ void dpu_core_irq_preinstall(struct dpu_kms *dpu_kms) } } -int dpu_core_irq_postinstall(struct dpu_kms *dpu_kms) -{ - return 0; -} - void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms) { struct msm_drm_private *priv; int i; - if (!dpu_kms) { - DPU_ERROR("invalid dpu_kms\n"); - return; - } else if (!dpu_kms->dev) { + if (!dpu_kms->dev) { DPU_ERROR("invalid drm device\n"); return; } else if (!dpu_kms->dev->dev_private) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h index 5e98bba46af5..e9015a2b23fe 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h @@ -24,13 +24,6 @@ void dpu_core_irq_preinstall(struct dpu_kms *dpu_kms); /** - * dpu_core_irq_postinstall - perform post-installation of core IRQ handler - * @dpu_kms: DPU handle - * @return: 0 if success; error code otherwise - */ -int dpu_core_irq_postinstall(struct dpu_kms *dpu_kms); - -/** * dpu_core_irq_uninstall - uninstall core IRQ handler * @dpu_kms: DPU handle * @return: none @@ -139,15 +132,8 @@ int dpu_core_irq_unregister_callback( * dpu_debugfs_core_irq_init - register core irq debugfs * @dpu_kms: pointer to kms * @parent: debugfs directory root - * @Return: 0 on success */ -int dpu_debugfs_core_irq_init(struct dpu_kms *dpu_kms, +void dpu_debugfs_core_irq_init(struct dpu_kms *dpu_kms, struct dentry *parent); -/** - * dpu_debugfs_core_irq_destroy - deregister core irq debugfs - * @dpu_kms: pointer to kms - */ -void dpu_debugfs_core_irq_destroy(struct dpu_kms *dpu_kms); - #endif /* __DPU_CORE_IRQ_H__ */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 41c5191f9056..9f20f397f77d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -24,8 +24,6 @@ #include "dpu_crtc.h" #include "dpu_core_perf.h" -#define DPU_PERF_MODE_STRING_SIZE 128 - /** * enum dpu_perf_mode - performance tuning mode * @DPU_PERF_MODE_NORMAL: performance controlled by user mode client @@ -57,31 +55,20 @@ static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc) return to_dpu_kms(priv->kms); } -static bool _dpu_core_perf_crtc_is_power_on(struct drm_crtc *crtc) -{ - return dpu_crtc_is_enabled(crtc); -} - static bool _dpu_core_video_mode_intf_connected(struct drm_crtc *crtc) { struct drm_crtc *tmp_crtc; - bool intf_connected = false; - - if (!crtc) - goto end; drm_for_each_crtc(tmp_crtc, crtc->dev) { if ((dpu_crtc_get_intf_mode(tmp_crtc) == INTF_MODE_VIDEO) && - _dpu_core_perf_crtc_is_power_on(tmp_crtc)) { + tmp_crtc->enabled) { DPU_DEBUG("video interface connected crtc:%d\n", tmp_crtc->base.id); - intf_connected = true; - goto end; + return true; } } -end: - return intf_connected; + return false; } static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms, @@ -101,20 +88,20 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms, memset(perf, 0, sizeof(struct dpu_core_perf_params)); if (!dpu_cstate->bw_control) { - for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) { + for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { perf->bw_ctl[i] = kms->catalog->perf.max_bw_high * 1000ULL; perf->max_per_pipe_ib[i] = perf->bw_ctl[i]; } perf->core_clk_rate = kms->perf.max_core_clk_rate; } else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) { - for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) { + for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { perf->bw_ctl[i] = 0; perf->max_per_pipe_ib[i] = 0; } perf->core_clk_rate = 0; } else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED) { - for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) { + for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { perf->bw_ctl[i] = kms->perf.fix_core_ab_vote; perf->max_per_pipe_ib[i] = kms->perf.fix_core_ib_vote; } @@ -124,12 +111,12 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms, DPU_DEBUG( "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu llcc_ib=%llu llcc_ab=%llu mem_ib=%llu mem_ab=%llu\n", crtc->base.id, perf->core_clk_rate, - perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_MNOC], - perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MNOC], - perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_LLCC], - perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC], - perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_EBI], - perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI]); + perf->max_per_pipe_ib[DPU_CORE_PERF_DATA_BUS_ID_MNOC], + perf->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_MNOC], + perf->max_per_pipe_ib[DPU_CORE_PERF_DATA_BUS_ID_LLCC], + perf->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_LLCC], + perf->max_per_pipe_ib[DPU_CORE_PERF_DATA_BUS_ID_EBI], + perf->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_EBI]); } int dpu_core_perf_crtc_check(struct drm_crtc *crtc, @@ -164,13 +151,13 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, /* obtain new values */ _dpu_core_perf_calc_crtc(kms, crtc, state, &dpu_cstate->new_perf); - for (i = DPU_POWER_HANDLE_DBUS_ID_MNOC; - i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) { + for (i = DPU_CORE_PERF_DATA_BUS_ID_MNOC; + i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { bw_sum_of_intfs = dpu_cstate->new_perf.bw_ctl[i]; curr_client_type = dpu_crtc_get_client_type(crtc); drm_for_each_crtc(tmp_crtc, crtc->dev) { - if (_dpu_core_perf_crtc_is_power_on(tmp_crtc) && + if (tmp_crtc->enabled && (dpu_crtc_get_client_type(tmp_crtc) == curr_client_type) && (tmp_crtc != crtc)) { @@ -229,7 +216,7 @@ static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms, int ret = 0; drm_for_each_crtc(tmp_crtc, crtc->dev) { - if (_dpu_core_perf_crtc_is_power_on(tmp_crtc) && + if (tmp_crtc->enabled && curr_client_type == dpu_crtc_get_client_type(tmp_crtc)) { dpu_cstate = to_dpu_crtc_state(tmp_crtc->state); @@ -286,7 +273,7 @@ void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc) */ if (dpu_crtc_get_intf_mode(crtc) == INTF_MODE_CMD) drm_for_each_crtc(tmp_crtc, crtc->dev) { - if (_dpu_core_perf_crtc_is_power_on(tmp_crtc) && + if (tmp_crtc->enabled && dpu_crtc_get_intf_mode(tmp_crtc) == INTF_MODE_VIDEO) return; @@ -296,7 +283,7 @@ void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc) if (kms->perf.enable_bw_release) { trace_dpu_cmd_release_bw(crtc->base.id); DPU_DEBUG("Release BW crtc=%d\n", crtc->base.id); - for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) { + for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { dpu_crtc->cur_perf.bw_ctl[i] = 0; _dpu_core_perf_crtc_update_bus(kms, crtc, i); } @@ -321,7 +308,7 @@ static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms) struct dpu_crtc_state *dpu_cstate; drm_for_each_crtc(crtc, kms->dev) { - if (_dpu_core_perf_crtc_is_power_on(crtc)) { + if (crtc->enabled) { dpu_cstate = to_dpu_crtc_state(crtc->state); clk_rate = max(dpu_cstate->new_perf.core_clk_rate, clk_rate); @@ -372,8 +359,8 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, old = &dpu_crtc->cur_perf; new = &dpu_cstate->new_perf; - if (_dpu_core_perf_crtc_is_power_on(crtc) && !stop_req) { - for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) { + if (crtc->enabled && !stop_req) { + for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { /* * cases for bus bandwidth update. * 1. new bandwidth vote - "ab or ib vote" is higher @@ -415,13 +402,13 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, update_clk = 1; } trace_dpu_perf_crtc_update(crtc->base.id, - new->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MNOC], - new->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC], - new->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI], + new->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_MNOC], + new->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_LLCC], + new->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_EBI], new->core_clk_rate, stop_req, update_bus, update_clk); - for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) { + for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { if (update_bus & BIT(i)) { ret = _dpu_core_perf_crtc_update_bus(kms, crtc, i); if (ret) { @@ -462,24 +449,14 @@ static ssize_t _dpu_core_perf_mode_write(struct file *file, struct dpu_core_perf *perf = file->private_data; struct dpu_perf_cfg *cfg = &perf->catalog->perf; u32 perf_mode = 0; - char buf[10]; - - if (!perf) - return -ENODEV; - - if (count >= sizeof(buf)) - return -EFAULT; - - if (copy_from_user(buf, user_buf, count)) - return -EFAULT; - - buf[count] = 0; /* end of string */ + int ret; - if (kstrtouint(buf, 0, &perf_mode)) - return -EFAULT; + ret = kstrtouint_from_user(user_buf, count, 0, &perf_mode); + if (ret) + return ret; if (perf_mode >= DPU_PERF_MODE_MAX) - return -EFAULT; + return -EINVAL; if (perf_mode == DPU_PERF_MODE_FIXED) { DRM_INFO("fix performance mode\n"); @@ -504,29 +481,16 @@ static ssize_t _dpu_core_perf_mode_read(struct file *file, char __user *buff, size_t count, loff_t *ppos) { struct dpu_core_perf *perf = file->private_data; - int len = 0; - char buf[DPU_PERF_MODE_STRING_SIZE] = {'\0'}; - - if (!perf) - return -ENODEV; + int len; + char buf[128]; - if (*ppos) - return 0; /* the end */ - - len = snprintf(buf, sizeof(buf), + len = scnprintf(buf, sizeof(buf), "mode %d min_mdp_clk %llu min_bus_vote %llu\n", perf->perf_tune.mode, perf->perf_tune.min_core_clk, perf->perf_tune.min_bus_vote); - if (len < 0 || len >= sizeof(buf)) - return 0; - - if ((count < sizeof(buf)) || copy_to_user(buff, buf, len)) - return -EFAULT; - - *ppos += len; /* increase offset */ - return len; + return simple_read_from_buffer(buff, count, ppos, buf, len); } static const struct file_operations dpu_core_perf_mode_fops = { @@ -535,70 +499,43 @@ static const struct file_operations dpu_core_perf_mode_fops = { .write = _dpu_core_perf_mode_write, }; -static void dpu_core_perf_debugfs_destroy(struct dpu_core_perf *perf) -{ - debugfs_remove_recursive(perf->debugfs_root); - perf->debugfs_root = NULL; -} - -int dpu_core_perf_debugfs_init(struct dpu_core_perf *perf, - struct dentry *parent) +int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent) { + struct dpu_core_perf *perf = &dpu_kms->perf; struct dpu_mdss_cfg *catalog = perf->catalog; - struct msm_drm_private *priv; - struct dpu_kms *dpu_kms; - - priv = perf->dev->dev_private; - if (!priv || !priv->kms) { - DPU_ERROR("invalid KMS reference\n"); - return -EINVAL; - } + struct dentry *entry; - dpu_kms = to_dpu_kms(priv->kms); - - perf->debugfs_root = debugfs_create_dir("core_perf", parent); - if (!perf->debugfs_root) { - DPU_ERROR("failed to create core perf debugfs\n"); + entry = debugfs_create_dir("core_perf", parent); + if (IS_ERR_OR_NULL(entry)) return -EINVAL; - } - debugfs_create_u64("max_core_clk_rate", 0600, perf->debugfs_root, + debugfs_create_u64("max_core_clk_rate", 0600, entry, &perf->max_core_clk_rate); - debugfs_create_u64("core_clk_rate", 0600, perf->debugfs_root, + debugfs_create_u64("core_clk_rate", 0600, entry, &perf->core_clk_rate); - debugfs_create_u32("enable_bw_release", 0600, perf->debugfs_root, + debugfs_create_u32("enable_bw_release", 0600, entry, (u32 *)&perf->enable_bw_release); - debugfs_create_u32("threshold_low", 0600, perf->debugfs_root, + debugfs_create_u32("threshold_low", 0600, entry, (u32 *)&catalog->perf.max_bw_low); - debugfs_create_u32("threshold_high", 0600, perf->debugfs_root, + debugfs_create_u32("threshold_high", 0600, entry, (u32 *)&catalog->perf.max_bw_high); - debugfs_create_u32("min_core_ib", 0600, perf->debugfs_root, + debugfs_create_u32("min_core_ib", 0600, entry, (u32 *)&catalog->perf.min_core_ib); - debugfs_create_u32("min_llcc_ib", 0600, perf->debugfs_root, + debugfs_create_u32("min_llcc_ib", 0600, entry, (u32 *)&catalog->perf.min_llcc_ib); - debugfs_create_u32("min_dram_ib", 0600, perf->debugfs_root, + debugfs_create_u32("min_dram_ib", 0600, entry, (u32 *)&catalog->perf.min_dram_ib); - debugfs_create_file("perf_mode", 0600, perf->debugfs_root, + debugfs_create_file("perf_mode", 0600, entry, (u32 *)perf, &dpu_core_perf_mode_fops); - debugfs_create_u64("fix_core_clk_rate", 0600, perf->debugfs_root, + debugfs_create_u64("fix_core_clk_rate", 0600, entry, &perf->fix_core_clk_rate); - debugfs_create_u64("fix_core_ib_vote", 0600, perf->debugfs_root, + debugfs_create_u64("fix_core_ib_vote", 0600, entry, &perf->fix_core_ib_vote); - debugfs_create_u64("fix_core_ab_vote", 0600, perf->debugfs_root, + debugfs_create_u64("fix_core_ab_vote", 0600, entry, &perf->fix_core_ab_vote); return 0; } -#else -static void dpu_core_perf_debugfs_destroy(struct dpu_core_perf *perf) -{ -} - -int dpu_core_perf_debugfs_init(struct dpu_core_perf *perf, - struct dentry *parent) -{ - return 0; -} #endif void dpu_core_perf_destroy(struct dpu_core_perf *perf) @@ -608,10 +545,8 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf) return; } - dpu_core_perf_debugfs_destroy(perf); perf->max_core_clk_rate = 0; perf->core_clk = NULL; - perf->phandle = NULL; perf->catalog = NULL; perf->dev = NULL; } @@ -619,12 +554,10 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf) int dpu_core_perf_init(struct dpu_core_perf *perf, struct drm_device *dev, struct dpu_mdss_cfg *catalog, - struct dpu_power_handle *phandle, struct dss_clk *core_clk) { perf->dev = dev; perf->catalog = catalog; - perf->phandle = phandle; perf->core_clk = core_clk; perf->max_core_clk_rate = core_clk->max_rate; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h index fbcbe0c7527a..37f518815eb7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h @@ -19,19 +19,31 @@ #include <drm/drm_crtc.h> #include "dpu_hw_catalog.h" -#include "dpu_power_handle.h" #define DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE 412500000 /** + * enum dpu_core_perf_data_bus_id - data bus identifier + * @DPU_CORE_PERF_DATA_BUS_ID_MNOC: DPU/MNOC data bus + * @DPU_CORE_PERF_DATA_BUS_ID_LLCC: MNOC/LLCC data bus + * @DPU_CORE_PERF_DATA_BUS_ID_EBI: LLCC/EBI data bus + */ +enum dpu_core_perf_data_bus_id { + DPU_CORE_PERF_DATA_BUS_ID_MNOC, + DPU_CORE_PERF_DATA_BUS_ID_LLCC, + DPU_CORE_PERF_DATA_BUS_ID_EBI, + DPU_CORE_PERF_DATA_BUS_ID_MAX, +}; + +/** * struct dpu_core_perf_params - definition of performance parameters * @max_per_pipe_ib: maximum instantaneous bandwidth request * @bw_ctl: arbitrated bandwidth request * @core_clk_rate: core clock rate request */ struct dpu_core_perf_params { - u64 max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_MAX]; - u64 bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MAX]; + u64 max_per_pipe_ib[DPU_CORE_PERF_DATA_BUS_ID_MAX]; + u64 bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_MAX]; u64 core_clk_rate; }; @@ -52,7 +64,6 @@ struct dpu_core_perf_tune { * @dev: Pointer to drm device * @debugfs_root: top level debug folder * @catalog: Pointer to catalog configuration - * @phandle: Pointer to power handler * @core_clk: Pointer to core clock structure * @core_clk_rate: current core clock rate * @max_core_clk_rate: maximum allowable core clock rate @@ -66,7 +77,6 @@ struct dpu_core_perf { struct drm_device *dev; struct dentry *debugfs_root; struct dpu_mdss_cfg *catalog; - struct dpu_power_handle *phandle; struct dss_clk *core_clk; u64 core_clk_rate; u64 max_core_clk_rate; @@ -113,21 +123,20 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf); * @perf: Pointer to core performance context * @dev: Pointer to drm device * @catalog: Pointer to catalog - * @phandle: Pointer to power handle * @core_clk: pointer to core clock */ int dpu_core_perf_init(struct dpu_core_perf *perf, struct drm_device *dev, struct dpu_mdss_cfg *catalog, - struct dpu_power_handle *phandle, struct dss_clk *core_clk); +struct dpu_kms; + /** * dpu_core_perf_debugfs_init - initialize debugfs for core performance context - * @perf: Pointer to core performance context + * @dpu_kms: Pointer to the dpu_kms struct * @debugfs_parent: Pointer to parent debugfs */ -int dpu_core_perf_debugfs_init(struct dpu_core_perf *perf, - struct dentry *parent); +int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent); #endif /* _DPU_CORE_PERF_H_ */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index ca169f013a14..9be7c355debd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -33,7 +33,6 @@ #include "dpu_plane.h" #include "dpu_encoder.h" #include "dpu_vbif.h" -#include "dpu_power_handle.h" #include "dpu_core_perf.h" #include "dpu_trace.h" @@ -47,13 +46,7 @@ #define LEFT_MIXER 0 #define RIGHT_MIXER 1 -static inline int _dpu_crtc_get_mixer_width(struct dpu_crtc_state *cstate, - struct drm_display_mode *mode) -{ - return mode->hdisplay / cstate->num_mixers; -} - -static inline struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc) +static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc) { struct msm_drm_private *priv = crtc->dev->dev_private; @@ -69,10 +62,7 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc) if (!crtc) return; - dpu_crtc->phandle = NULL; - drm_crtc_cleanup(crtc); - mutex_destroy(&dpu_crtc->crtc_lock); kfree(dpu_crtc); } @@ -287,16 +277,17 @@ enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc) return INTF_MODE_NONE; } - drm_for_each_encoder(encoder, crtc->dev) - if (encoder->crtc == crtc) - return dpu_encoder_get_intf_mode(encoder); + WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); + + /* TODO: Returns the first INTF_MODE, could there be multiple values? */ + drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) + return dpu_encoder_get_intf_mode(encoder); return INTF_MODE_NONE; } -static void dpu_crtc_vblank_cb(void *data) +void dpu_crtc_vblank_callback(struct drm_crtc *crtc) { - struct drm_crtc *crtc = (struct drm_crtc *)data; struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); /* keep statistics on vblank callback - with auto reset via debugfs */ @@ -309,6 +300,19 @@ static void dpu_crtc_vblank_cb(void *data) trace_dpu_crtc_vblank_cb(DRMID(crtc)); } +static void dpu_crtc_release_bw_unlocked(struct drm_crtc *crtc) +{ + int ret = 0; + struct drm_modeset_acquire_ctx ctx; + + DRM_MODESET_LOCK_ALL_BEGIN(crtc->dev, ctx, 0, ret); + dpu_core_perf_crtc_release_bw(crtc); + DRM_MODESET_LOCK_ALL_END(ctx, ret); + if (ret) + DRM_ERROR("Failed to acquire modeset locks to release bw, %d\n", + ret); +} + static void dpu_crtc_frame_event_work(struct kthread_work *work) { struct dpu_crtc_frame_event *fevent = container_of(work, @@ -338,7 +342,7 @@ static void dpu_crtc_frame_event_work(struct kthread_work *work) /* release bandwidth and other resources */ trace_dpu_crtc_frame_event_done(DRMID(crtc), fevent->event); - dpu_core_perf_crtc_release_bw(crtc); + dpu_crtc_release_bw_unlocked(crtc); } else { trace_dpu_crtc_frame_event_more_pending(DRMID(crtc), fevent->event); @@ -473,28 +477,21 @@ static void _dpu_crtc_setup_mixer_for_encoder( static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc) { - struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); struct drm_encoder *enc; - mutex_lock(&dpu_crtc->crtc_lock); - /* Check for mixers on all encoders attached to this crtc */ - list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) { - if (enc->crtc != crtc) - continue; + WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); + /* Check for mixers on all encoders attached to this crtc */ + drm_for_each_encoder_mask(enc, crtc->dev, crtc->state->encoder_mask) _dpu_crtc_setup_mixer_for_encoder(crtc, enc); - } - - mutex_unlock(&dpu_crtc->crtc_lock); } static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc, struct drm_crtc_state *state) { - struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); struct dpu_crtc_state *cstate = to_dpu_crtc_state(state); struct drm_display_mode *adj_mode = &state->adjusted_mode; - u32 crtc_split_width = _dpu_crtc_get_mixer_width(cstate, adj_mode); + u32 crtc_split_width = adj_mode->hdisplay / cstate->num_mixers; int i; for (i = 0; i < cstate->num_mixers; i++) { @@ -502,7 +499,7 @@ static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc, r->x1 = crtc_split_width * i; r->y1 = 0; r->x2 = r->x1 + crtc_split_width; - r->y2 = dpu_crtc_get_mixer_height(dpu_crtc, cstate, adj_mode); + r->y2 = adj_mode->vdisplay; trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i, r); } @@ -552,13 +549,9 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, spin_unlock_irqrestore(&dev->event_lock, flags); } - list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { - if (encoder->crtc != crtc) - continue; - - /* encoder will trigger pending mask now */ + /* encoder will trigger pending mask now */ + drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) dpu_encoder_trigger_kickoff_pending(encoder); - } /* * If no mixers have been allocated in dpu_crtc_atomic_check(), @@ -702,10 +695,9 @@ static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc) return rc; } -void dpu_crtc_commit_kickoff(struct drm_crtc *crtc) +void dpu_crtc_commit_kickoff(struct drm_crtc *crtc, bool async) { struct drm_encoder *encoder; - struct drm_device *dev = crtc->dev; struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); @@ -721,127 +713,59 @@ void dpu_crtc_commit_kickoff(struct drm_crtc *crtc) DPU_ATRACE_BEGIN("crtc_commit"); - list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + /* + * Encoder will flush/start now, unless it has a tx pending. If so, it + * may delay and flush at an irq event (e.g. ppdone) + */ + drm_for_each_encoder_mask(encoder, crtc->dev, + crtc->state->encoder_mask) { struct dpu_encoder_kickoff_params params = { 0 }; - - if (encoder->crtc != crtc) - continue; - - /* - * Encoder will flush/start now, unless it has a tx pending. - * If so, it may delay and flush at an irq event (e.g. ppdone) - */ - dpu_encoder_prepare_for_kickoff(encoder, ¶ms); + dpu_encoder_prepare_for_kickoff(encoder, ¶ms, async); } - /* wait for frame_event_done completion */ - DPU_ATRACE_BEGIN("wait_for_frame_done_event"); - ret = _dpu_crtc_wait_for_frame_done(crtc); - DPU_ATRACE_END("wait_for_frame_done_event"); - if (ret) { - DPU_ERROR("crtc%d wait for frame done failed;frame_pending%d\n", - crtc->base.id, - atomic_read(&dpu_crtc->frame_pending)); - goto end; - } - if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) { - /* acquire bandwidth and other resources */ - DPU_DEBUG("crtc%d first commit\n", crtc->base.id); - } else - DPU_DEBUG("crtc%d commit\n", crtc->base.id); + if (!async) { + /* wait for frame_event_done completion */ + DPU_ATRACE_BEGIN("wait_for_frame_done_event"); + ret = _dpu_crtc_wait_for_frame_done(crtc); + DPU_ATRACE_END("wait_for_frame_done_event"); + if (ret) { + DPU_ERROR("crtc%d wait for frame done failed;frame_pending%d\n", + crtc->base.id, + atomic_read(&dpu_crtc->frame_pending)); + goto end; + } + + if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) { + /* acquire bandwidth and other resources */ + DPU_DEBUG("crtc%d first commit\n", crtc->base.id); + } else + DPU_DEBUG("crtc%d commit\n", crtc->base.id); - dpu_crtc->play_count++; + dpu_crtc->play_count++; + } dpu_vbif_clear_errors(dpu_kms); - list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { - if (encoder->crtc != crtc) - continue; - - dpu_encoder_kickoff(encoder); - } + drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) + dpu_encoder_kickoff(encoder, async); end: - reinit_completion(&dpu_crtc->frame_done_comp); + if (!async) + reinit_completion(&dpu_crtc->frame_done_comp); DPU_ATRACE_END("crtc_commit"); } -/** - * _dpu_crtc_vblank_enable_no_lock - update power resource and vblank request - * @dpu_crtc: Pointer to dpu crtc structure - * @enable: Whether to enable/disable vblanks - */ -static void _dpu_crtc_vblank_enable_no_lock( - struct dpu_crtc *dpu_crtc, bool enable) -{ - struct drm_crtc *crtc = &dpu_crtc->base; - struct drm_device *dev = crtc->dev; - struct drm_encoder *enc; - - if (enable) { - /* drop lock since power crtc cb may try to re-acquire lock */ - mutex_unlock(&dpu_crtc->crtc_lock); - pm_runtime_get_sync(dev->dev); - mutex_lock(&dpu_crtc->crtc_lock); - - list_for_each_entry(enc, &dev->mode_config.encoder_list, head) { - if (enc->crtc != crtc) - continue; - - trace_dpu_crtc_vblank_enable(DRMID(&dpu_crtc->base), - DRMID(enc), enable, - dpu_crtc); - - dpu_encoder_register_vblank_callback(enc, - dpu_crtc_vblank_cb, (void *)crtc); - } - } else { - list_for_each_entry(enc, &dev->mode_config.encoder_list, head) { - if (enc->crtc != crtc) - continue; - - trace_dpu_crtc_vblank_enable(DRMID(&dpu_crtc->base), - DRMID(enc), enable, - dpu_crtc); - - dpu_encoder_register_vblank_callback(enc, NULL, NULL); - } - - /* drop lock since power crtc cb may try to re-acquire lock */ - mutex_unlock(&dpu_crtc->crtc_lock); - pm_runtime_put_sync(dev->dev); - mutex_lock(&dpu_crtc->crtc_lock); - } -} - -/** - * _dpu_crtc_set_suspend - notify crtc of suspend enable/disable - * @crtc: Pointer to drm crtc object - * @enable: true to enable suspend, false to indicate resume - */ -static void _dpu_crtc_set_suspend(struct drm_crtc *crtc, bool enable) +static void dpu_crtc_reset(struct drm_crtc *crtc) { - struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); - - DRM_DEBUG_KMS("crtc%d suspend = %d\n", crtc->base.id, enable); - - mutex_lock(&dpu_crtc->crtc_lock); + struct dpu_crtc_state *cstate; - /* - * If the vblank is enabled, release a power reference on suspend - * and take it back during resume (if it is still enabled). - */ - trace_dpu_crtc_set_suspend(DRMID(&dpu_crtc->base), enable, dpu_crtc); - if (dpu_crtc->suspend == enable) - DPU_DEBUG("crtc%d suspend already set to %d, ignoring update\n", - crtc->base.id, enable); - else if (dpu_crtc->enabled && dpu_crtc->vblank_requested) { - _dpu_crtc_vblank_enable_no_lock(dpu_crtc, !enable); - } + if (crtc->state) + dpu_crtc_destroy_state(crtc, crtc->state); - dpu_crtc->suspend = enable; - mutex_unlock(&dpu_crtc->crtc_lock); + crtc->state = kzalloc(sizeof(*cstate), GFP_KERNEL); + if (crtc->state) + crtc->state->crtc = crtc; } /** @@ -873,65 +797,8 @@ static struct drm_crtc_state *dpu_crtc_duplicate_state(struct drm_crtc *crtc) return &cstate->base; } -/** - * dpu_crtc_reset - reset hook for CRTCs - * Resets the atomic state for @crtc by freeing the state pointer (which might - * be NULL, e.g. at driver load time) and allocating a new empty state object. - * @crtc: Pointer to drm crtc structure - */ -static void dpu_crtc_reset(struct drm_crtc *crtc) -{ - struct dpu_crtc *dpu_crtc; - struct dpu_crtc_state *cstate; - - if (!crtc) { - DPU_ERROR("invalid crtc\n"); - return; - } - - /* revert suspend actions, if necessary */ - if (dpu_kms_is_suspend_state(crtc->dev)) - _dpu_crtc_set_suspend(crtc, false); - - /* remove previous state, if present */ - if (crtc->state) { - dpu_crtc_destroy_state(crtc, crtc->state); - crtc->state = 0; - } - - dpu_crtc = to_dpu_crtc(crtc); - cstate = kzalloc(sizeof(*cstate), GFP_KERNEL); - if (!cstate) { - DPU_ERROR("failed to allocate state\n"); - return; - } - - cstate->base.crtc = crtc; - crtc->state = &cstate->base; -} - -static void dpu_crtc_handle_power_event(u32 event_type, void *arg) -{ - struct drm_crtc *crtc = arg; - struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); - struct drm_encoder *encoder; - - mutex_lock(&dpu_crtc->crtc_lock); - - trace_dpu_crtc_handle_power_event(DRMID(crtc), event_type); - - /* restore encoder; crtc will be programmed during commit */ - drm_for_each_encoder(encoder, crtc->dev) { - if (encoder->crtc != crtc) - continue; - - dpu_encoder_virt_restore(encoder); - } - - mutex_unlock(&dpu_crtc->crtc_lock); -} - -static void dpu_crtc_disable(struct drm_crtc *crtc) +static void dpu_crtc_disable(struct drm_crtc *crtc, + struct drm_crtc_state *old_crtc_state) { struct dpu_crtc *dpu_crtc; struct dpu_crtc_state *cstate; @@ -951,13 +818,12 @@ static void dpu_crtc_disable(struct drm_crtc *crtc) DRM_DEBUG_KMS("crtc%d\n", crtc->base.id); - if (dpu_kms_is_suspend_state(crtc->dev)) - _dpu_crtc_set_suspend(crtc, true); - /* Disable/save vblank irq handling */ drm_crtc_vblank_off(crtc); - mutex_lock(&dpu_crtc->crtc_lock); + drm_for_each_encoder_mask(encoder, crtc->dev, + old_crtc_state->encoder_mask) + dpu_encoder_assign_crtc(encoder, NULL); /* wait for frame_event_done completion */ if (_dpu_crtc_wait_for_frame_done(crtc)) @@ -966,10 +832,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc) atomic_read(&dpu_crtc->frame_pending)); trace_dpu_crtc_disable(DRMID(crtc), false, dpu_crtc); - if (dpu_crtc->enabled && !dpu_crtc->suspend && - dpu_crtc->vblank_requested) { - _dpu_crtc_vblank_enable_no_lock(dpu_crtc, false); - } dpu_crtc->enabled = false; if (atomic_read(&dpu_crtc->frame_pending)) { @@ -981,15 +843,8 @@ static void dpu_crtc_disable(struct drm_crtc *crtc) dpu_core_perf_crtc_update(crtc, 0, true); - drm_for_each_encoder(encoder, crtc->dev) { - if (encoder->crtc != crtc) - continue; + drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) dpu_encoder_register_frame_event_callback(encoder, NULL, NULL); - } - - if (dpu_crtc->power_event) - dpu_power_handle_unregister_event(dpu_crtc->phandle, - dpu_crtc->power_event); memset(cstate->mixers, 0, sizeof(cstate->mixers)); cstate->num_mixers = 0; @@ -998,14 +853,14 @@ static void dpu_crtc_disable(struct drm_crtc *crtc) cstate->bw_control = false; cstate->bw_split_vote = false; - mutex_unlock(&dpu_crtc->crtc_lock); - if (crtc->state->event && !crtc->state->active) { spin_lock_irqsave(&crtc->dev->event_lock, flags); drm_crtc_send_vblank_event(crtc, crtc->state->event); crtc->state->event = NULL; spin_unlock_irqrestore(&crtc->dev->event_lock, flags); } + + pm_runtime_put_sync(crtc->dev->dev); } static void dpu_crtc_enable(struct drm_crtc *crtc, @@ -1021,33 +876,23 @@ static void dpu_crtc_enable(struct drm_crtc *crtc, } priv = crtc->dev->dev_private; + pm_runtime_get_sync(crtc->dev->dev); + DRM_DEBUG_KMS("crtc%d\n", crtc->base.id); dpu_crtc = to_dpu_crtc(crtc); - drm_for_each_encoder(encoder, crtc->dev) { - if (encoder->crtc != crtc) - continue; + drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) dpu_encoder_register_frame_event_callback(encoder, dpu_crtc_frame_event_cb, (void *)crtc); - } - mutex_lock(&dpu_crtc->crtc_lock); trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc); - if (!dpu_crtc->enabled && !dpu_crtc->suspend && - dpu_crtc->vblank_requested) { - _dpu_crtc_vblank_enable_no_lock(dpu_crtc, true); - } dpu_crtc->enabled = true; - mutex_unlock(&dpu_crtc->crtc_lock); + drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) + dpu_encoder_assign_crtc(encoder, crtc); /* Enable/restore vblank irq handling */ drm_crtc_vblank_on(crtc); - - dpu_crtc->power_event = dpu_power_handle_register_event( - dpu_crtc->phandle, DPU_POWER_EVENT_ENABLE, - dpu_crtc_handle_power_event, crtc, dpu_crtc->name); - } struct plane_state { @@ -1101,7 +946,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, memset(pipe_staged, 0, sizeof(pipe_staged)); - mixer_width = _dpu_crtc_get_mixer_width(cstate, mode); + mixer_width = mode->hdisplay / cstate->num_mixers; _dpu_crtc_setup_lm_bounds(crtc, state); @@ -1289,21 +1134,32 @@ end: int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) { - struct dpu_crtc *dpu_crtc; - - if (!crtc) { - DPU_ERROR("invalid crtc\n"); - return -EINVAL; - } - dpu_crtc = to_dpu_crtc(crtc); + struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); + struct drm_encoder *enc; - mutex_lock(&dpu_crtc->crtc_lock); trace_dpu_crtc_vblank(DRMID(&dpu_crtc->base), en, dpu_crtc); - if (dpu_crtc->enabled && !dpu_crtc->suspend) { - _dpu_crtc_vblank_enable_no_lock(dpu_crtc, en); + + /* + * Normally we would iterate through encoder_mask in crtc state to find + * attached encoders. In this case, we might be disabling vblank _after_ + * encoder_mask has been cleared. + * + * Instead, we "assign" a crtc to the encoder in enable and clear it in + * disable (which is also after encoder_mask is cleared). So instead of + * using encoder mask, we'll ask the encoder to toggle itself iff it's + * currently assigned to our crtc. + * + * Note also that this function cannot be called while crtc is disabled + * since we use drm_crtc_vblank_on/off. So we don't need to worry + * about the assigned crtcs being inconsistent with the current state + * (which means no need to worry about modeset locks). + */ + list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) { + trace_dpu_crtc_vblank_enable(DRMID(crtc), DRMID(enc), en, + dpu_crtc); + + dpu_encoder_toggle_vblank_for_crtc(enc, crtc, en); } - dpu_crtc->vblank_requested = en; - mutex_unlock(&dpu_crtc->crtc_lock); return 0; } @@ -1324,18 +1180,14 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data) int i, out_width; - if (!s || !s->private) - return -EINVAL; - dpu_crtc = s->private; crtc = &dpu_crtc->base; drm_modeset_lock_all(crtc->dev); cstate = to_dpu_crtc_state(crtc->state); - mutex_lock(&dpu_crtc->crtc_lock); mode = &crtc->state->adjusted_mode; - out_width = _dpu_crtc_get_mixer_width(cstate, mode); + out_width = mode->hdisplay / cstate->num_mixers; seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id, mode->hdisplay, mode->vdisplay); @@ -1420,9 +1272,6 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data) dpu_crtc->vblank_cb_time = ktime_set(0, 0); } - seq_printf(s, "vblank_enable:%d\n", dpu_crtc->vblank_requested); - - mutex_unlock(&dpu_crtc->crtc_lock); drm_modeset_unlock_all(crtc->dev); return 0; @@ -1456,13 +1305,11 @@ static int dpu_crtc_debugfs_state_show(struct seq_file *s, void *v) seq_printf(s, "intf_mode: %d\n", dpu_crtc_get_intf_mode(crtc)); seq_printf(s, "core_clk_rate: %llu\n", dpu_crtc->cur_perf.core_clk_rate); - for (i = DPU_POWER_HANDLE_DBUS_ID_MNOC; - i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) { - seq_printf(s, "bw_ctl[%s]: %llu\n", - dpu_power_handle_get_dbus_name(i), + for (i = DPU_CORE_PERF_DATA_BUS_ID_MNOC; + i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { + seq_printf(s, "bw_ctl[%d]: %llu\n", i, dpu_crtc->cur_perf.bw_ctl[i]); - seq_printf(s, "max_per_pipe_ib[%s]: %llu\n", - dpu_power_handle_get_dbus_name(i), + seq_printf(s, "max_per_pipe_ib[%d]: %llu\n", i, dpu_crtc->cur_perf.max_per_pipe_ib[i]); } @@ -1472,8 +1319,7 @@ DEFINE_DPU_DEBUGFS_SEQ_FOPS(dpu_crtc_debugfs_state); static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc) { - struct dpu_crtc *dpu_crtc; - struct dpu_kms *dpu_kms; + struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); static const struct file_operations debugfs_status_fops = { .open = _dpu_debugfs_status_open, @@ -1482,12 +1328,6 @@ static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc) .release = single_release, }; - if (!crtc) - return -EINVAL; - dpu_crtc = to_dpu_crtc(crtc); - - dpu_kms = _dpu_crtc_get_kms(crtc); - dpu_crtc->debugfs_root = debugfs_create_dir(dpu_crtc->name, crtc->dev->primary->debugfs_root); if (!dpu_crtc->debugfs_root) @@ -1504,25 +1344,11 @@ static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc) return 0; } - -static void _dpu_crtc_destroy_debugfs(struct drm_crtc *crtc) -{ - struct dpu_crtc *dpu_crtc; - - if (!crtc) - return; - dpu_crtc = to_dpu_crtc(crtc); - debugfs_remove_recursive(dpu_crtc->debugfs_root); -} #else static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc) { return 0; } - -static void _dpu_crtc_destroy_debugfs(struct drm_crtc *crtc) -{ -} #endif /* CONFIG_DEBUG_FS */ static int dpu_crtc_late_register(struct drm_crtc *crtc) @@ -1532,7 +1358,9 @@ static int dpu_crtc_late_register(struct drm_crtc *crtc) static void dpu_crtc_early_unregister(struct drm_crtc *crtc) { - _dpu_crtc_destroy_debugfs(crtc); + struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); + + debugfs_remove_recursive(dpu_crtc->debugfs_root); } static const struct drm_crtc_funcs dpu_crtc_funcs = { @@ -1547,7 +1375,7 @@ static const struct drm_crtc_funcs dpu_crtc_funcs = { }; static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = { - .disable = dpu_crtc_disable, + .atomic_disable = dpu_crtc_disable, .atomic_enable = dpu_crtc_enable, .atomic_check = dpu_crtc_atomic_check, .atomic_begin = dpu_crtc_atomic_begin, @@ -1574,7 +1402,6 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, crtc = &dpu_crtc->base; crtc->dev = dev; - mutex_init(&dpu_crtc->crtc_lock); spin_lock_init(&dpu_crtc->spin_lock); atomic_set(&dpu_crtc->frame_pending, 0); @@ -1601,8 +1428,6 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, /* initialize event handling */ spin_lock_init(&dpu_crtc->event_lock); - dpu_crtc->phandle = &kms->phandle; - DPU_DEBUG("%s: successfully initialized crtc\n", dpu_crtc->name); return crtc; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h index 3723b4830335..dbfb38a1986c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -132,8 +132,6 @@ struct dpu_crtc_frame_event { * @vblank_cb_count : count of vblank callback since last reset * @play_count : frame count between crtc enable and disable * @vblank_cb_time : ktime at vblank count reset - * @vblank_requested : whether the user has requested vblank events - * @suspend : whether or not a suspend operation is in progress * @enabled : whether the DPU CRTC is currently enabled. updated in the * commit-thread, not state-swap time which is earlier, so * safe to make decisions on during VBLANK on/off work @@ -142,7 +140,6 @@ struct dpu_crtc_frame_event { * @dirty_list : list of color processing features are dirty * @ad_dirty: list containing ad properties that are dirty * @ad_active: list containing ad properties that are active - * @crtc_lock : crtc lock around create, destroy and access. * @frame_pending : Whether or not an update is pending * @frame_events : static allocation of in-flight frame events * @frame_event_list : available frame event list @@ -152,7 +149,6 @@ struct dpu_crtc_frame_event { * @event_worker : Event worker queue * @event_lock : Spinlock around event handling code * @phandle: Pointer to power handler - * @power_event : registered power event handle * @cur_perf : current performance committed to clock/bandwidth driver */ struct dpu_crtc { @@ -168,8 +164,6 @@ struct dpu_crtc { u32 vblank_cb_count; u64 play_count; ktime_t vblank_cb_time; - bool vblank_requested; - bool suspend; bool enabled; struct list_head feature_list; @@ -178,8 +172,6 @@ struct dpu_crtc { struct list_head ad_dirty; struct list_head ad_active; - struct mutex crtc_lock; - atomic_t frame_pending; struct dpu_crtc_frame_event frame_events[DPU_CRTC_FRAME_EVENT_SIZE]; struct list_head frame_event_list; @@ -189,9 +181,6 @@ struct dpu_crtc { /* for handling internal event thread */ spinlock_t event_lock; - struct dpu_power_handle *phandle; - struct dpu_power_event *power_event; - struct dpu_core_perf_params cur_perf; struct dpu_crtc_smmu_state_data smmu_state; @@ -238,41 +227,12 @@ struct dpu_crtc_state { container_of(x, struct dpu_crtc_state, base) /** - * dpu_crtc_state_is_stereo - Is crtc virtualized with two mixers? - * @cstate: Pointer to dpu crtc state - * @Return: true - has two mixers, false - has one mixer - */ -static inline bool dpu_crtc_state_is_stereo(struct dpu_crtc_state *cstate) -{ - return cstate->num_mixers == CRTC_DUAL_MIXERS; -} - -/** - * dpu_crtc_get_mixer_height - get the mixer height - * Mixer height will be same as panel height - */ -static inline int dpu_crtc_get_mixer_height(struct dpu_crtc *dpu_crtc, - struct dpu_crtc_state *cstate, struct drm_display_mode *mode) -{ - if (!dpu_crtc || !cstate || !mode) - return 0; - - return mode->vdisplay; -} - -/** * dpu_crtc_frame_pending - retun the number of pending frames * @crtc: Pointer to drm crtc object */ static inline int dpu_crtc_frame_pending(struct drm_crtc *crtc) { - struct dpu_crtc *dpu_crtc; - - if (!crtc) - return -EINVAL; - - dpu_crtc = to_dpu_crtc(crtc); - return atomic_read(&dpu_crtc->frame_pending); + return crtc ? atomic_read(&to_dpu_crtc(crtc)->frame_pending) : -EINVAL; } /** @@ -283,10 +243,17 @@ static inline int dpu_crtc_frame_pending(struct drm_crtc *crtc) int dpu_crtc_vblank(struct drm_crtc *crtc, bool en); /** + * dpu_crtc_vblank_callback - called on vblank irq, issues completion events + * @crtc: Pointer to drm crtc object + */ +void dpu_crtc_vblank_callback(struct drm_crtc *crtc); + +/** * dpu_crtc_commit_kickoff - trigger kickoff of the commit for this crtc * @crtc: Pointer to drm crtc object + * @async: true if the commit is asynchronous, false otherwise */ -void dpu_crtc_commit_kickoff(struct drm_crtc *crtc); +void dpu_crtc_commit_kickoff(struct drm_crtc *crtc, bool async); /** * dpu_crtc_complete_commit - callback signalling completion of current commit @@ -329,22 +296,7 @@ enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc); static inline enum dpu_crtc_client_type dpu_crtc_get_client_type( struct drm_crtc *crtc) { - struct dpu_crtc_state *cstate = - crtc ? to_dpu_crtc_state(crtc->state) : NULL; - - if (!cstate) - return NRT_CLIENT; - - return RT_CLIENT; -} - -/** - * dpu_crtc_is_enabled - check if dpu crtc is enabled or not - * @crtc: Pointer to crtc - */ -static inline bool dpu_crtc_is_enabled(struct drm_crtc *crtc) -{ - return crtc ? crtc->enabled : false; + return crtc && crtc->state ? RT_CLIENT : NRT_CLIENT; } #endif /* _DPU_CRTC_H_ */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.c deleted file mode 100644 index ae2aee7ed9e1..000000000000 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.c +++ /dev/null @@ -1,2393 +0,0 @@ -/* Copyright (c) 2009-2018, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ - -#include <linux/delay.h> -#include <linux/spinlock.h> -#include <linux/ktime.h> -#include <linux/debugfs.h> -#include <linux/uaccess.h> -#include <linux/dma-buf.h> -#include <linux/slab.h> -#include <linux/list_sort.h> -#include <linux/pm_runtime.h> - -#include "dpu_dbg.h" -#include "disp/dpu1/dpu_hw_catalog.h" - - -#define DEFAULT_DBGBUS_DPU DPU_DBG_DUMP_IN_MEM -#define DEFAULT_DBGBUS_VBIFRT DPU_DBG_DUMP_IN_MEM -#define REG_BASE_NAME_LEN 80 - -#define DBGBUS_FLAGS_DSPP BIT(0) -#define DBGBUS_DSPP_STATUS 0x34C - -#define DBGBUS_NAME_DPU "dpu" -#define DBGBUS_NAME_VBIF_RT "vbif_rt" - -/* offsets from dpu top address for the debug buses */ -#define DBGBUS_SSPP0 0x188 -#define DBGBUS_AXI_INTF 0x194 -#define DBGBUS_SSPP1 0x298 -#define DBGBUS_DSPP 0x348 -#define DBGBUS_PERIPH 0x418 - -#define TEST_MASK(id, tp) ((id << 4) | (tp << 1) | BIT(0)) - -/* following offsets are with respect to MDP VBIF base for DBG BUS access */ -#define MMSS_VBIF_CLKON 0x4 -#define MMSS_VBIF_TEST_BUS_OUT_CTRL 0x210 -#define MMSS_VBIF_TEST_BUS_OUT 0x230 - -/* Vbif error info */ -#define MMSS_VBIF_PND_ERR 0x190 -#define MMSS_VBIF_SRC_ERR 0x194 -#define MMSS_VBIF_XIN_HALT_CTRL1 0x204 -#define MMSS_VBIF_ERR_INFO 0X1a0 -#define MMSS_VBIF_ERR_INFO_1 0x1a4 -#define MMSS_VBIF_CLIENT_NUM 14 - -/** - * struct dpu_dbg_reg_base - register region base. - * may sub-ranges: sub-ranges are used for dumping - * or may not have sub-ranges: dumping is base -> max_offset - * @reg_base_head: head of this node - * @name: register base name - * @base: base pointer - * @off: cached offset of region for manual register dumping - * @cnt: cached range of region for manual register dumping - * @max_offset: length of region - * @buf: buffer used for manual register dumping - * @buf_len: buffer length used for manual register dumping - * @cb: callback for external dump function, null if not defined - * @cb_ptr: private pointer to callback function - */ -struct dpu_dbg_reg_base { - struct list_head reg_base_head; - char name[REG_BASE_NAME_LEN]; - void __iomem *base; - size_t off; - size_t cnt; - size_t max_offset; - char *buf; - size_t buf_len; - void (*cb)(void *ptr); - void *cb_ptr; -}; - -struct dpu_debug_bus_entry { - u32 wr_addr; - u32 block_id; - u32 test_id; - void (*analyzer)(void __iomem *mem_base, - struct dpu_debug_bus_entry *entry, u32 val); -}; - -struct vbif_debug_bus_entry { - u32 disable_bus_addr; - u32 block_bus_addr; - u32 bit_offset; - u32 block_cnt; - u32 test_pnt_start; - u32 test_pnt_cnt; -}; - -struct dpu_dbg_debug_bus_common { - char *name; - u32 enable_mask; - bool include_in_deferred_work; - u32 flags; - u32 entries_size; - u32 *dumped_content; -}; - -struct dpu_dbg_dpu_debug_bus { - struct dpu_dbg_debug_bus_common cmn; - struct dpu_debug_bus_entry *entries; - u32 top_blk_off; -}; - -struct dpu_dbg_vbif_debug_bus { - struct dpu_dbg_debug_bus_common cmn; - struct vbif_debug_bus_entry *entries; -}; - -/** - * struct dpu_dbg_base - global dpu debug base structure - * @reg_base_list: list of register dumping regions - * @dev: device pointer - * @dump_work: work struct for deferring register dump work to separate thread - * @dbgbus_dpu: debug bus structure for the dpu - * @dbgbus_vbif_rt: debug bus structure for the realtime vbif - */ -static struct dpu_dbg_base { - struct list_head reg_base_list; - struct device *dev; - - struct work_struct dump_work; - - struct dpu_dbg_dpu_debug_bus dbgbus_dpu; - struct dpu_dbg_vbif_debug_bus dbgbus_vbif_rt; -} dpu_dbg_base; - -static void _dpu_debug_bus_xbar_dump(void __iomem *mem_base, - struct dpu_debug_bus_entry *entry, u32 val) -{ - dev_err(dpu_dbg_base.dev, "xbar 0x%x %d %d 0x%x\n", - entry->wr_addr, entry->block_id, entry->test_id, val); -} - -static void _dpu_debug_bus_lm_dump(void __iomem *mem_base, - struct dpu_debug_bus_entry *entry, u32 val) -{ - if (!(val & 0xFFF000)) - return; - - dev_err(dpu_dbg_base.dev, "lm 0x%x %d %d 0x%x\n", - entry->wr_addr, entry->block_id, entry->test_id, val); -} - -static void _dpu_debug_bus_ppb0_dump(void __iomem *mem_base, - struct dpu_debug_bus_entry *entry, u32 val) -{ - if (!(val & BIT(15))) - return; - - dev_err(dpu_dbg_base.dev, "ppb0 0x%x %d %d 0x%x\n", - entry->wr_addr, entry->block_id, entry->test_id, val); -} - -static void _dpu_debug_bus_ppb1_dump(void __iomem *mem_base, - struct dpu_debug_bus_entry *entry, u32 val) -{ - if (!(val & BIT(15))) - return; - - dev_err(dpu_dbg_base.dev, "ppb1 0x%x %d %d 0x%x\n", - entry->wr_addr, entry->block_id, entry->test_id, val); -} - -static struct dpu_debug_bus_entry dbg_bus_dpu_8998[] = { - - /* Unpack 0 sspp 0*/ - { DBGBUS_SSPP0, 50, 2 }, - { DBGBUS_SSPP0, 60, 2 }, - { DBGBUS_SSPP0, 70, 2 }, - { DBGBUS_SSPP0, 85, 2 }, - - /* Upack 0 sspp 1*/ - { DBGBUS_SSPP1, 50, 2 }, - { DBGBUS_SSPP1, 60, 2 }, - { DBGBUS_SSPP1, 70, 2 }, - { DBGBUS_SSPP1, 85, 2 }, - - /* scheduler */ - { DBGBUS_DSPP, 130, 0 }, - { DBGBUS_DSPP, 130, 1 }, - { DBGBUS_DSPP, 130, 2 }, - { DBGBUS_DSPP, 130, 3 }, - { DBGBUS_DSPP, 130, 4 }, - { DBGBUS_DSPP, 130, 5 }, - - /* qseed */ - { DBGBUS_SSPP0, 6, 0}, - { DBGBUS_SSPP0, 6, 1}, - { DBGBUS_SSPP0, 26, 0}, - { DBGBUS_SSPP0, 26, 1}, - { DBGBUS_SSPP1, 6, 0}, - { DBGBUS_SSPP1, 6, 1}, - { DBGBUS_SSPP1, 26, 0}, - { DBGBUS_SSPP1, 26, 1}, - - /* scale */ - { DBGBUS_SSPP0, 16, 0}, - { DBGBUS_SSPP0, 16, 1}, - { DBGBUS_SSPP0, 36, 0}, - { DBGBUS_SSPP0, 36, 1}, - { DBGBUS_SSPP1, 16, 0}, - { DBGBUS_SSPP1, 16, 1}, - { DBGBUS_SSPP1, 36, 0}, - { DBGBUS_SSPP1, 36, 1}, - - /* fetch sspp0 */ - - /* vig 0 */ - { DBGBUS_SSPP0, 0, 0 }, - { DBGBUS_SSPP0, 0, 1 }, - { DBGBUS_SSPP0, 0, 2 }, - { DBGBUS_SSPP0, 0, 3 }, - { DBGBUS_SSPP0, 0, 4 }, - { DBGBUS_SSPP0, 0, 5 }, - { DBGBUS_SSPP0, 0, 6 }, - { DBGBUS_SSPP0, 0, 7 }, - - { DBGBUS_SSPP0, 1, 0 }, - { DBGBUS_SSPP0, 1, 1 }, - { DBGBUS_SSPP0, 1, 2 }, - { DBGBUS_SSPP0, 1, 3 }, - { DBGBUS_SSPP0, 1, 4 }, - { DBGBUS_SSPP0, 1, 5 }, - { DBGBUS_SSPP0, 1, 6 }, - { DBGBUS_SSPP0, 1, 7 }, - - { DBGBUS_SSPP0, 2, 0 }, - { DBGBUS_SSPP0, 2, 1 }, - { DBGBUS_SSPP0, 2, 2 }, - { DBGBUS_SSPP0, 2, 3 }, - { DBGBUS_SSPP0, 2, 4 }, - { DBGBUS_SSPP0, 2, 5 }, - { DBGBUS_SSPP0, 2, 6 }, - { DBGBUS_SSPP0, 2, 7 }, - - { DBGBUS_SSPP0, 4, 0 }, - { DBGBUS_SSPP0, 4, 1 }, - { DBGBUS_SSPP0, 4, 2 }, - { DBGBUS_SSPP0, 4, 3 }, - { DBGBUS_SSPP0, 4, 4 }, - { DBGBUS_SSPP0, 4, 5 }, - { DBGBUS_SSPP0, 4, 6 }, - { DBGBUS_SSPP0, 4, 7 }, - - { DBGBUS_SSPP0, 5, 0 }, - { DBGBUS_SSPP0, 5, 1 }, - { DBGBUS_SSPP0, 5, 2 }, - { DBGBUS_SSPP0, 5, 3 }, - { DBGBUS_SSPP0, 5, 4 }, - { DBGBUS_SSPP0, 5, 5 }, - { DBGBUS_SSPP0, 5, 6 }, - { DBGBUS_SSPP0, 5, 7 }, - - /* vig 2 */ - { DBGBUS_SSPP0, 20, 0 }, - { DBGBUS_SSPP0, 20, 1 }, - { DBGBUS_SSPP0, 20, 2 }, - { DBGBUS_SSPP0, 20, 3 }, - { DBGBUS_SSPP0, 20, 4 }, - { DBGBUS_SSPP0, 20, 5 }, - { DBGBUS_SSPP0, 20, 6 }, - { DBGBUS_SSPP0, 20, 7 }, - - { DBGBUS_SSPP0, 21, 0 }, - { DBGBUS_SSPP0, 21, 1 }, - { DBGBUS_SSPP0, 21, 2 }, - { DBGBUS_SSPP0, 21, 3 }, - { DBGBUS_SSPP0, 21, 4 }, - { DBGBUS_SSPP0, 21, 5 }, - { DBGBUS_SSPP0, 21, 6 }, - { DBGBUS_SSPP0, 21, 7 }, - - { DBGBUS_SSPP0, 22, 0 }, - { DBGBUS_SSPP0, 22, 1 }, - { DBGBUS_SSPP0, 22, 2 }, - { DBGBUS_SSPP0, 22, 3 }, - { DBGBUS_SSPP0, 22, 4 }, - { DBGBUS_SSPP0, 22, 5 }, - { DBGBUS_SSPP0, 22, 6 }, - { DBGBUS_SSPP0, 22, 7 }, - - { DBGBUS_SSPP0, 24, 0 }, - { DBGBUS_SSPP0, 24, 1 }, - { DBGBUS_SSPP0, 24, 2 }, - { DBGBUS_SSPP0, 24, 3 }, - { DBGBUS_SSPP0, 24, 4 }, - { DBGBUS_SSPP0, 24, 5 }, - { DBGBUS_SSPP0, 24, 6 }, - { DBGBUS_SSPP0, 24, 7 }, - - { DBGBUS_SSPP0, 25, 0 }, - { DBGBUS_SSPP0, 25, 1 }, - { DBGBUS_SSPP0, 25, 2 }, - { DBGBUS_SSPP0, 25, 3 }, - { DBGBUS_SSPP0, 25, 4 }, - { DBGBUS_SSPP0, 25, 5 }, - { DBGBUS_SSPP0, 25, 6 }, - { DBGBUS_SSPP0, 25, 7 }, - - /* dma 2 */ - { DBGBUS_SSPP0, 30, 0 }, - { DBGBUS_SSPP0, 30, 1 }, - { DBGBUS_SSPP0, 30, 2 }, - { DBGBUS_SSPP0, 30, 3 }, - { DBGBUS_SSPP0, 30, 4 }, - { DBGBUS_SSPP0, 30, 5 }, - { DBGBUS_SSPP0, 30, 6 }, - { DBGBUS_SSPP0, 30, 7 }, - - { DBGBUS_SSPP0, 31, 0 }, - { DBGBUS_SSPP0, 31, 1 }, - { DBGBUS_SSPP0, 31, 2 }, - { DBGBUS_SSPP0, 31, 3 }, - { DBGBUS_SSPP0, 31, 4 }, - { DBGBUS_SSPP0, 31, 5 }, - { DBGBUS_SSPP0, 31, 6 }, - { DBGBUS_SSPP0, 31, 7 }, - - { DBGBUS_SSPP0, 32, 0 }, - { DBGBUS_SSPP0, 32, 1 }, - { DBGBUS_SSPP0, 32, 2 }, - { DBGBUS_SSPP0, 32, 3 }, - { DBGBUS_SSPP0, 32, 4 }, - { DBGBUS_SSPP0, 32, 5 }, - { DBGBUS_SSPP0, 32, 6 }, - { DBGBUS_SSPP0, 32, 7 }, - - { DBGBUS_SSPP0, 33, 0 }, - { DBGBUS_SSPP0, 33, 1 }, - { DBGBUS_SSPP0, 33, 2 }, - { DBGBUS_SSPP0, 33, 3 }, - { DBGBUS_SSPP0, 33, 4 }, - { DBGBUS_SSPP0, 33, 5 }, - { DBGBUS_SSPP0, 33, 6 }, - { DBGBUS_SSPP0, 33, 7 }, - - { DBGBUS_SSPP0, 34, 0 }, - { DBGBUS_SSPP0, 34, 1 }, - { DBGBUS_SSPP0, 34, 2 }, - { DBGBUS_SSPP0, 34, 3 }, - { DBGBUS_SSPP0, 34, 4 }, - { DBGBUS_SSPP0, 34, 5 }, - { DBGBUS_SSPP0, 34, 6 }, - { DBGBUS_SSPP0, 34, 7 }, - - { DBGBUS_SSPP0, 35, 0 }, - { DBGBUS_SSPP0, 35, 1 }, - { DBGBUS_SSPP0, 35, 2 }, - { DBGBUS_SSPP0, 35, 3 }, - - /* dma 0 */ - { DBGBUS_SSPP0, 40, 0 }, - { DBGBUS_SSPP0, 40, 1 }, - { DBGBUS_SSPP0, 40, 2 }, - { DBGBUS_SSPP0, 40, 3 }, - { DBGBUS_SSPP0, 40, 4 }, - { DBGBUS_SSPP0, 40, 5 }, - { DBGBUS_SSPP0, 40, 6 }, - { DBGBUS_SSPP0, 40, 7 }, - - { DBGBUS_SSPP0, 41, 0 }, - { DBGBUS_SSPP0, 41, 1 }, - { DBGBUS_SSPP0, 41, 2 }, - { DBGBUS_SSPP0, 41, 3 }, - { DBGBUS_SSPP0, 41, 4 }, - { DBGBUS_SSPP0, 41, 5 }, - { DBGBUS_SSPP0, 41, 6 }, - { DBGBUS_SSPP0, 41, 7 }, - - { DBGBUS_SSPP0, 42, 0 }, - { DBGBUS_SSPP0, 42, 1 }, - { DBGBUS_SSPP0, 42, 2 }, - { DBGBUS_SSPP0, 42, 3 }, - { DBGBUS_SSPP0, 42, 4 }, - { DBGBUS_SSPP0, 42, 5 }, - { DBGBUS_SSPP0, 42, 6 }, - { DBGBUS_SSPP0, 42, 7 }, - - { DBGBUS_SSPP0, 44, 0 }, - { DBGBUS_SSPP0, 44, 1 }, - { DBGBUS_SSPP0, 44, 2 }, - { DBGBUS_SSPP0, 44, 3 }, - { DBGBUS_SSPP0, 44, 4 }, - { DBGBUS_SSPP0, 44, 5 }, - { DBGBUS_SSPP0, 44, 6 }, - { DBGBUS_SSPP0, 44, 7 }, - - { DBGBUS_SSPP0, 45, 0 }, - { DBGBUS_SSPP0, 45, 1 }, - { DBGBUS_SSPP0, 45, 2 }, - { DBGBUS_SSPP0, 45, 3 }, - { DBGBUS_SSPP0, 45, 4 }, - { DBGBUS_SSPP0, 45, 5 }, - { DBGBUS_SSPP0, 45, 6 }, - { DBGBUS_SSPP0, 45, 7 }, - - /* fetch sspp1 */ - /* vig 1 */ - { DBGBUS_SSPP1, 0, 0 }, - { DBGBUS_SSPP1, 0, 1 }, - { DBGBUS_SSPP1, 0, 2 }, - { DBGBUS_SSPP1, 0, 3 }, - { DBGBUS_SSPP1, 0, 4 }, - { DBGBUS_SSPP1, 0, 5 }, - { DBGBUS_SSPP1, 0, 6 }, - { DBGBUS_SSPP1, 0, 7 }, - - { DBGBUS_SSPP1, 1, 0 }, - { DBGBUS_SSPP1, 1, 1 }, - { DBGBUS_SSPP1, 1, 2 }, - { DBGBUS_SSPP1, 1, 3 }, - { DBGBUS_SSPP1, 1, 4 }, - { DBGBUS_SSPP1, 1, 5 }, - { DBGBUS_SSPP1, 1, 6 }, - { DBGBUS_SSPP1, 1, 7 }, - - { DBGBUS_SSPP1, 2, 0 }, - { DBGBUS_SSPP1, 2, 1 }, - { DBGBUS_SSPP1, 2, 2 }, - { DBGBUS_SSPP1, 2, 3 }, - { DBGBUS_SSPP1, 2, 4 }, - { DBGBUS_SSPP1, 2, 5 }, - { DBGBUS_SSPP1, 2, 6 }, - { DBGBUS_SSPP1, 2, 7 }, - - { DBGBUS_SSPP1, 4, 0 }, - { DBGBUS_SSPP1, 4, 1 }, - { DBGBUS_SSPP1, 4, 2 }, - { DBGBUS_SSPP1, 4, 3 }, - { DBGBUS_SSPP1, 4, 4 }, - { DBGBUS_SSPP1, 4, 5 }, - { DBGBUS_SSPP1, 4, 6 }, - { DBGBUS_SSPP1, 4, 7 }, - - { DBGBUS_SSPP1, 5, 0 }, - { DBGBUS_SSPP1, 5, 1 }, - { DBGBUS_SSPP1, 5, 2 }, - { DBGBUS_SSPP1, 5, 3 }, - { DBGBUS_SSPP1, 5, 4 }, - { DBGBUS_SSPP1, 5, 5 }, - { DBGBUS_SSPP1, 5, 6 }, - { DBGBUS_SSPP1, 5, 7 }, - - /* vig 3 */ - { DBGBUS_SSPP1, 20, 0 }, - { DBGBUS_SSPP1, 20, 1 }, - { DBGBUS_SSPP1, 20, 2 }, - { DBGBUS_SSPP1, 20, 3 }, - { DBGBUS_SSPP1, 20, 4 }, - { DBGBUS_SSPP1, 20, 5 }, - { DBGBUS_SSPP1, 20, 6 }, - { DBGBUS_SSPP1, 20, 7 }, - - { DBGBUS_SSPP1, 21, 0 }, - { DBGBUS_SSPP1, 21, 1 }, - { DBGBUS_SSPP1, 21, 2 }, - { DBGBUS_SSPP1, 21, 3 }, - { DBGBUS_SSPP1, 21, 4 }, - { DBGBUS_SSPP1, 21, 5 }, - { DBGBUS_SSPP1, 21, 6 }, - { DBGBUS_SSPP1, 21, 7 }, - - { DBGBUS_SSPP1, 22, 0 }, - { DBGBUS_SSPP1, 22, 1 }, - { DBGBUS_SSPP1, 22, 2 }, - { DBGBUS_SSPP1, 22, 3 }, - { DBGBUS_SSPP1, 22, 4 }, - { DBGBUS_SSPP1, 22, 5 }, - { DBGBUS_SSPP1, 22, 6 }, - { DBGBUS_SSPP1, 22, 7 }, - - { DBGBUS_SSPP1, 24, 0 }, - { DBGBUS_SSPP1, 24, 1 }, - { DBGBUS_SSPP1, 24, 2 }, - { DBGBUS_SSPP1, 24, 3 }, - { DBGBUS_SSPP1, 24, 4 }, - { DBGBUS_SSPP1, 24, 5 }, - { DBGBUS_SSPP1, 24, 6 }, - { DBGBUS_SSPP1, 24, 7 }, - - { DBGBUS_SSPP1, 25, 0 }, - { DBGBUS_SSPP1, 25, 1 }, - { DBGBUS_SSPP1, 25, 2 }, - { DBGBUS_SSPP1, 25, 3 }, - { DBGBUS_SSPP1, 25, 4 }, - { DBGBUS_SSPP1, 25, 5 }, - { DBGBUS_SSPP1, 25, 6 }, - { DBGBUS_SSPP1, 25, 7 }, - - /* dma 3 */ - { DBGBUS_SSPP1, 30, 0 }, - { DBGBUS_SSPP1, 30, 1 }, - { DBGBUS_SSPP1, 30, 2 }, - { DBGBUS_SSPP1, 30, 3 }, - { DBGBUS_SSPP1, 30, 4 }, - { DBGBUS_SSPP1, 30, 5 }, - { DBGBUS_SSPP1, 30, 6 }, - { DBGBUS_SSPP1, 30, 7 }, - - { DBGBUS_SSPP1, 31, 0 }, - { DBGBUS_SSPP1, 31, 1 }, - { DBGBUS_SSPP1, 31, 2 }, - { DBGBUS_SSPP1, 31, 3 }, - { DBGBUS_SSPP1, 31, 4 }, - { DBGBUS_SSPP1, 31, 5 }, - { DBGBUS_SSPP1, 31, 6 }, - { DBGBUS_SSPP1, 31, 7 }, - - { DBGBUS_SSPP1, 32, 0 }, - { DBGBUS_SSPP1, 32, 1 }, - { DBGBUS_SSPP1, 32, 2 }, - { DBGBUS_SSPP1, 32, 3 }, - { DBGBUS_SSPP1, 32, 4 }, - { DBGBUS_SSPP1, 32, 5 }, - { DBGBUS_SSPP1, 32, 6 }, - { DBGBUS_SSPP1, 32, 7 }, - - { DBGBUS_SSPP1, 33, 0 }, - { DBGBUS_SSPP1, 33, 1 }, - { DBGBUS_SSPP1, 33, 2 }, - { DBGBUS_SSPP1, 33, 3 }, - { DBGBUS_SSPP1, 33, 4 }, - { DBGBUS_SSPP1, 33, 5 }, - { DBGBUS_SSPP1, 33, 6 }, - { DBGBUS_SSPP1, 33, 7 }, - - { DBGBUS_SSPP1, 34, 0 }, - { DBGBUS_SSPP1, 34, 1 }, - { DBGBUS_SSPP1, 34, 2 }, - { DBGBUS_SSPP1, 34, 3 }, - { DBGBUS_SSPP1, 34, 4 }, - { DBGBUS_SSPP1, 34, 5 }, - { DBGBUS_SSPP1, 34, 6 }, - { DBGBUS_SSPP1, 34, 7 }, - - { DBGBUS_SSPP1, 35, 0 }, - { DBGBUS_SSPP1, 35, 1 }, - { DBGBUS_SSPP1, 35, 2 }, - - /* dma 1 */ - { DBGBUS_SSPP1, 40, 0 }, - { DBGBUS_SSPP1, 40, 1 }, - { DBGBUS_SSPP1, 40, 2 }, - { DBGBUS_SSPP1, 40, 3 }, - { DBGBUS_SSPP1, 40, 4 }, - { DBGBUS_SSPP1, 40, 5 }, - { DBGBUS_SSPP1, 40, 6 }, - { DBGBUS_SSPP1, 40, 7 }, - - { DBGBUS_SSPP1, 41, 0 }, - { DBGBUS_SSPP1, 41, 1 }, - { DBGBUS_SSPP1, 41, 2 }, - { DBGBUS_SSPP1, 41, 3 }, - { DBGBUS_SSPP1, 41, 4 }, - { DBGBUS_SSPP1, 41, 5 }, - { DBGBUS_SSPP1, 41, 6 }, - { DBGBUS_SSPP1, 41, 7 }, - - { DBGBUS_SSPP1, 42, 0 }, - { DBGBUS_SSPP1, 42, 1 }, - { DBGBUS_SSPP1, 42, 2 }, - { DBGBUS_SSPP1, 42, 3 }, - { DBGBUS_SSPP1, 42, 4 }, - { DBGBUS_SSPP1, 42, 5 }, - { DBGBUS_SSPP1, 42, 6 }, - { DBGBUS_SSPP1, 42, 7 }, - - { DBGBUS_SSPP1, 44, 0 }, - { DBGBUS_SSPP1, 44, 1 }, - { DBGBUS_SSPP1, 44, 2 }, - { DBGBUS_SSPP1, 44, 3 }, - { DBGBUS_SSPP1, 44, 4 }, - { DBGBUS_SSPP1, 44, 5 }, - { DBGBUS_SSPP1, 44, 6 }, - { DBGBUS_SSPP1, 44, 7 }, - - { DBGBUS_SSPP1, 45, 0 }, - { DBGBUS_SSPP1, 45, 1 }, - { DBGBUS_SSPP1, 45, 2 }, - { DBGBUS_SSPP1, 45, 3 }, - { DBGBUS_SSPP1, 45, 4 }, - { DBGBUS_SSPP1, 45, 5 }, - { DBGBUS_SSPP1, 45, 6 }, - { DBGBUS_SSPP1, 45, 7 }, - - /* cursor 1 */ - { DBGBUS_SSPP1, 80, 0 }, - { DBGBUS_SSPP1, 80, 1 }, - { DBGBUS_SSPP1, 80, 2 }, - { DBGBUS_SSPP1, 80, 3 }, - { DBGBUS_SSPP1, 80, 4 }, - { DBGBUS_SSPP1, 80, 5 }, - { DBGBUS_SSPP1, 80, 6 }, - { DBGBUS_SSPP1, 80, 7 }, - - { DBGBUS_SSPP1, 81, 0 }, - { DBGBUS_SSPP1, 81, 1 }, - { DBGBUS_SSPP1, 81, 2 }, - { DBGBUS_SSPP1, 81, 3 }, - { DBGBUS_SSPP1, 81, 4 }, - { DBGBUS_SSPP1, 81, 5 }, - { DBGBUS_SSPP1, 81, 6 }, - { DBGBUS_SSPP1, 81, 7 }, - - { DBGBUS_SSPP1, 82, 0 }, - { DBGBUS_SSPP1, 82, 1 }, - { DBGBUS_SSPP1, 82, 2 }, - { DBGBUS_SSPP1, 82, 3 }, - { DBGBUS_SSPP1, 82, 4 }, - { DBGBUS_SSPP1, 82, 5 }, - { DBGBUS_SSPP1, 82, 6 }, - { DBGBUS_SSPP1, 82, 7 }, - - { DBGBUS_SSPP1, 83, 0 }, - { DBGBUS_SSPP1, 83, 1 }, - { DBGBUS_SSPP1, 83, 2 }, - { DBGBUS_SSPP1, 83, 3 }, - { DBGBUS_SSPP1, 83, 4 }, - { DBGBUS_SSPP1, 83, 5 }, - { DBGBUS_SSPP1, 83, 6 }, - { DBGBUS_SSPP1, 83, 7 }, - - { DBGBUS_SSPP1, 84, 0 }, - { DBGBUS_SSPP1, 84, 1 }, - { DBGBUS_SSPP1, 84, 2 }, - { DBGBUS_SSPP1, 84, 3 }, - { DBGBUS_SSPP1, 84, 4 }, - { DBGBUS_SSPP1, 84, 5 }, - { DBGBUS_SSPP1, 84, 6 }, - { DBGBUS_SSPP1, 84, 7 }, - - /* dspp */ - { DBGBUS_DSPP, 13, 0 }, - { DBGBUS_DSPP, 19, 0 }, - { DBGBUS_DSPP, 14, 0 }, - { DBGBUS_DSPP, 14, 1 }, - { DBGBUS_DSPP, 14, 3 }, - { DBGBUS_DSPP, 20, 0 }, - { DBGBUS_DSPP, 20, 1 }, - { DBGBUS_DSPP, 20, 3 }, - - /* ppb_0 */ - { DBGBUS_DSPP, 31, 0, _dpu_debug_bus_ppb0_dump }, - { DBGBUS_DSPP, 33, 0, _dpu_debug_bus_ppb0_dump }, - { DBGBUS_DSPP, 35, 0, _dpu_debug_bus_ppb0_dump }, - { DBGBUS_DSPP, 42, 0, _dpu_debug_bus_ppb0_dump }, - - /* ppb_1 */ - { DBGBUS_DSPP, 32, 0, _dpu_debug_bus_ppb1_dump }, - { DBGBUS_DSPP, 34, 0, _dpu_debug_bus_ppb1_dump }, - { DBGBUS_DSPP, 36, 0, _dpu_debug_bus_ppb1_dump }, - { DBGBUS_DSPP, 43, 0, _dpu_debug_bus_ppb1_dump }, - - /* lm_lut */ - { DBGBUS_DSPP, 109, 0 }, - { DBGBUS_DSPP, 105, 0 }, - { DBGBUS_DSPP, 103, 0 }, - - /* tear-check */ - { DBGBUS_PERIPH, 63, 0 }, - { DBGBUS_PERIPH, 64, 0 }, - { DBGBUS_PERIPH, 65, 0 }, - { DBGBUS_PERIPH, 73, 0 }, - { DBGBUS_PERIPH, 74, 0 }, - - /* crossbar */ - { DBGBUS_DSPP, 0, 0, _dpu_debug_bus_xbar_dump }, - - /* rotator */ - { DBGBUS_DSPP, 9, 0}, - - /* blend */ - /* LM0 */ - { DBGBUS_DSPP, 63, 0}, - { DBGBUS_DSPP, 63, 1}, - { DBGBUS_DSPP, 63, 2}, - { DBGBUS_DSPP, 63, 3}, - { DBGBUS_DSPP, 63, 4}, - { DBGBUS_DSPP, 63, 5}, - { DBGBUS_DSPP, 63, 6}, - { DBGBUS_DSPP, 63, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 64, 0}, - { DBGBUS_DSPP, 64, 1}, - { DBGBUS_DSPP, 64, 2}, - { DBGBUS_DSPP, 64, 3}, - { DBGBUS_DSPP, 64, 4}, - { DBGBUS_DSPP, 64, 5}, - { DBGBUS_DSPP, 64, 6}, - { DBGBUS_DSPP, 64, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 65, 0}, - { DBGBUS_DSPP, 65, 1}, - { DBGBUS_DSPP, 65, 2}, - { DBGBUS_DSPP, 65, 3}, - { DBGBUS_DSPP, 65, 4}, - { DBGBUS_DSPP, 65, 5}, - { DBGBUS_DSPP, 65, 6}, - { DBGBUS_DSPP, 65, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 66, 0}, - { DBGBUS_DSPP, 66, 1}, - { DBGBUS_DSPP, 66, 2}, - { DBGBUS_DSPP, 66, 3}, - { DBGBUS_DSPP, 66, 4}, - { DBGBUS_DSPP, 66, 5}, - { DBGBUS_DSPP, 66, 6}, - { DBGBUS_DSPP, 66, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 67, 0}, - { DBGBUS_DSPP, 67, 1}, - { DBGBUS_DSPP, 67, 2}, - { DBGBUS_DSPP, 67, 3}, - { DBGBUS_DSPP, 67, 4}, - { DBGBUS_DSPP, 67, 5}, - { DBGBUS_DSPP, 67, 6}, - { DBGBUS_DSPP, 67, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 68, 0}, - { DBGBUS_DSPP, 68, 1}, - { DBGBUS_DSPP, 68, 2}, - { DBGBUS_DSPP, 68, 3}, - { DBGBUS_DSPP, 68, 4}, - { DBGBUS_DSPP, 68, 5}, - { DBGBUS_DSPP, 68, 6}, - { DBGBUS_DSPP, 68, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 69, 0}, - { DBGBUS_DSPP, 69, 1}, - { DBGBUS_DSPP, 69, 2}, - { DBGBUS_DSPP, 69, 3}, - { DBGBUS_DSPP, 69, 4}, - { DBGBUS_DSPP, 69, 5}, - { DBGBUS_DSPP, 69, 6}, - { DBGBUS_DSPP, 69, 7, _dpu_debug_bus_lm_dump }, - - /* LM1 */ - { DBGBUS_DSPP, 70, 0}, - { DBGBUS_DSPP, 70, 1}, - { DBGBUS_DSPP, 70, 2}, - { DBGBUS_DSPP, 70, 3}, - { DBGBUS_DSPP, 70, 4}, - { DBGBUS_DSPP, 70, 5}, - { DBGBUS_DSPP, 70, 6}, - { DBGBUS_DSPP, 70, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 71, 0}, - { DBGBUS_DSPP, 71, 1}, - { DBGBUS_DSPP, 71, 2}, - { DBGBUS_DSPP, 71, 3}, - { DBGBUS_DSPP, 71, 4}, - { DBGBUS_DSPP, 71, 5}, - { DBGBUS_DSPP, 71, 6}, - { DBGBUS_DSPP, 71, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 72, 0}, - { DBGBUS_DSPP, 72, 1}, - { DBGBUS_DSPP, 72, 2}, - { DBGBUS_DSPP, 72, 3}, - { DBGBUS_DSPP, 72, 4}, - { DBGBUS_DSPP, 72, 5}, - { DBGBUS_DSPP, 72, 6}, - { DBGBUS_DSPP, 72, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 73, 0}, - { DBGBUS_DSPP, 73, 1}, - { DBGBUS_DSPP, 73, 2}, - { DBGBUS_DSPP, 73, 3}, - { DBGBUS_DSPP, 73, 4}, - { DBGBUS_DSPP, 73, 5}, - { DBGBUS_DSPP, 73, 6}, - { DBGBUS_DSPP, 73, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 74, 0}, - { DBGBUS_DSPP, 74, 1}, - { DBGBUS_DSPP, 74, 2}, - { DBGBUS_DSPP, 74, 3}, - { DBGBUS_DSPP, 74, 4}, - { DBGBUS_DSPP, 74, 5}, - { DBGBUS_DSPP, 74, 6}, - { DBGBUS_DSPP, 74, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 75, 0}, - { DBGBUS_DSPP, 75, 1}, - { DBGBUS_DSPP, 75, 2}, - { DBGBUS_DSPP, 75, 3}, - { DBGBUS_DSPP, 75, 4}, - { DBGBUS_DSPP, 75, 5}, - { DBGBUS_DSPP, 75, 6}, - { DBGBUS_DSPP, 75, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 76, 0}, - { DBGBUS_DSPP, 76, 1}, - { DBGBUS_DSPP, 76, 2}, - { DBGBUS_DSPP, 76, 3}, - { DBGBUS_DSPP, 76, 4}, - { DBGBUS_DSPP, 76, 5}, - { DBGBUS_DSPP, 76, 6}, - { DBGBUS_DSPP, 76, 7, _dpu_debug_bus_lm_dump }, - - /* LM2 */ - { DBGBUS_DSPP, 77, 0}, - { DBGBUS_DSPP, 77, 1}, - { DBGBUS_DSPP, 77, 2}, - { DBGBUS_DSPP, 77, 3}, - { DBGBUS_DSPP, 77, 4}, - { DBGBUS_DSPP, 77, 5}, - { DBGBUS_DSPP, 77, 6}, - { DBGBUS_DSPP, 77, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 78, 0}, - { DBGBUS_DSPP, 78, 1}, - { DBGBUS_DSPP, 78, 2}, - { DBGBUS_DSPP, 78, 3}, - { DBGBUS_DSPP, 78, 4}, - { DBGBUS_DSPP, 78, 5}, - { DBGBUS_DSPP, 78, 6}, - { DBGBUS_DSPP, 78, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 79, 0}, - { DBGBUS_DSPP, 79, 1}, - { DBGBUS_DSPP, 79, 2}, - { DBGBUS_DSPP, 79, 3}, - { DBGBUS_DSPP, 79, 4}, - { DBGBUS_DSPP, 79, 5}, - { DBGBUS_DSPP, 79, 6}, - { DBGBUS_DSPP, 79, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 80, 0}, - { DBGBUS_DSPP, 80, 1}, - { DBGBUS_DSPP, 80, 2}, - { DBGBUS_DSPP, 80, 3}, - { DBGBUS_DSPP, 80, 4}, - { DBGBUS_DSPP, 80, 5}, - { DBGBUS_DSPP, 80, 6}, - { DBGBUS_DSPP, 80, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 81, 0}, - { DBGBUS_DSPP, 81, 1}, - { DBGBUS_DSPP, 81, 2}, - { DBGBUS_DSPP, 81, 3}, - { DBGBUS_DSPP, 81, 4}, - { DBGBUS_DSPP, 81, 5}, - { DBGBUS_DSPP, 81, 6}, - { DBGBUS_DSPP, 81, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 82, 0}, - { DBGBUS_DSPP, 82, 1}, - { DBGBUS_DSPP, 82, 2}, - { DBGBUS_DSPP, 82, 3}, - { DBGBUS_DSPP, 82, 4}, - { DBGBUS_DSPP, 82, 5}, - { DBGBUS_DSPP, 82, 6}, - { DBGBUS_DSPP, 82, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 83, 0}, - { DBGBUS_DSPP, 83, 1}, - { DBGBUS_DSPP, 83, 2}, - { DBGBUS_DSPP, 83, 3}, - { DBGBUS_DSPP, 83, 4}, - { DBGBUS_DSPP, 83, 5}, - { DBGBUS_DSPP, 83, 6}, - { DBGBUS_DSPP, 83, 7, _dpu_debug_bus_lm_dump }, - - /* csc */ - { DBGBUS_SSPP0, 7, 0}, - { DBGBUS_SSPP0, 7, 1}, - { DBGBUS_SSPP0, 27, 0}, - { DBGBUS_SSPP0, 27, 1}, - { DBGBUS_SSPP1, 7, 0}, - { DBGBUS_SSPP1, 7, 1}, - { DBGBUS_SSPP1, 27, 0}, - { DBGBUS_SSPP1, 27, 1}, - - /* pcc */ - { DBGBUS_SSPP0, 3, 3}, - { DBGBUS_SSPP0, 23, 3}, - { DBGBUS_SSPP0, 33, 3}, - { DBGBUS_SSPP0, 43, 3}, - { DBGBUS_SSPP1, 3, 3}, - { DBGBUS_SSPP1, 23, 3}, - { DBGBUS_SSPP1, 33, 3}, - { DBGBUS_SSPP1, 43, 3}, - - /* spa */ - { DBGBUS_SSPP0, 8, 0}, - { DBGBUS_SSPP0, 28, 0}, - { DBGBUS_SSPP1, 8, 0}, - { DBGBUS_SSPP1, 28, 0}, - { DBGBUS_DSPP, 13, 0}, - { DBGBUS_DSPP, 19, 0}, - - /* igc */ - { DBGBUS_SSPP0, 9, 0}, - { DBGBUS_SSPP0, 9, 1}, - { DBGBUS_SSPP0, 9, 3}, - { DBGBUS_SSPP0, 29, 0}, - { DBGBUS_SSPP0, 29, 1}, - { DBGBUS_SSPP0, 29, 3}, - { DBGBUS_SSPP0, 17, 0}, - { DBGBUS_SSPP0, 17, 1}, - { DBGBUS_SSPP0, 17, 3}, - { DBGBUS_SSPP0, 37, 0}, - { DBGBUS_SSPP0, 37, 1}, - { DBGBUS_SSPP0, 37, 3}, - { DBGBUS_SSPP0, 46, 0}, - { DBGBUS_SSPP0, 46, 1}, - { DBGBUS_SSPP0, 46, 3}, - - { DBGBUS_SSPP1, 9, 0}, - { DBGBUS_SSPP1, 9, 1}, - { DBGBUS_SSPP1, 9, 3}, - { DBGBUS_SSPP1, 29, 0}, - { DBGBUS_SSPP1, 29, 1}, - { DBGBUS_SSPP1, 29, 3}, - { DBGBUS_SSPP1, 17, 0}, - { DBGBUS_SSPP1, 17, 1}, - { DBGBUS_SSPP1, 17, 3}, - { DBGBUS_SSPP1, 37, 0}, - { DBGBUS_SSPP1, 37, 1}, - { DBGBUS_SSPP1, 37, 3}, - { DBGBUS_SSPP1, 46, 0}, - { DBGBUS_SSPP1, 46, 1}, - { DBGBUS_SSPP1, 46, 3}, - - { DBGBUS_DSPP, 14, 0}, - { DBGBUS_DSPP, 14, 1}, - { DBGBUS_DSPP, 14, 3}, - { DBGBUS_DSPP, 20, 0}, - { DBGBUS_DSPP, 20, 1}, - { DBGBUS_DSPP, 20, 3}, - - { DBGBUS_PERIPH, 60, 0}, -}; - -static struct dpu_debug_bus_entry dbg_bus_dpu_sdm845[] = { - - /* Unpack 0 sspp 0*/ - { DBGBUS_SSPP0, 50, 2 }, - { DBGBUS_SSPP0, 60, 2 }, - { DBGBUS_SSPP0, 70, 2 }, - - /* Upack 0 sspp 1*/ - { DBGBUS_SSPP1, 50, 2 }, - { DBGBUS_SSPP1, 60, 2 }, - { DBGBUS_SSPP1, 70, 2 }, - - /* scheduler */ - { DBGBUS_DSPP, 130, 0 }, - { DBGBUS_DSPP, 130, 1 }, - { DBGBUS_DSPP, 130, 2 }, - { DBGBUS_DSPP, 130, 3 }, - { DBGBUS_DSPP, 130, 4 }, - { DBGBUS_DSPP, 130, 5 }, - - /* qseed */ - { DBGBUS_SSPP0, 6, 0}, - { DBGBUS_SSPP0, 6, 1}, - { DBGBUS_SSPP0, 26, 0}, - { DBGBUS_SSPP0, 26, 1}, - { DBGBUS_SSPP1, 6, 0}, - { DBGBUS_SSPP1, 6, 1}, - { DBGBUS_SSPP1, 26, 0}, - { DBGBUS_SSPP1, 26, 1}, - - /* scale */ - { DBGBUS_SSPP0, 16, 0}, - { DBGBUS_SSPP0, 16, 1}, - { DBGBUS_SSPP0, 36, 0}, - { DBGBUS_SSPP0, 36, 1}, - { DBGBUS_SSPP1, 16, 0}, - { DBGBUS_SSPP1, 16, 1}, - { DBGBUS_SSPP1, 36, 0}, - { DBGBUS_SSPP1, 36, 1}, - - /* fetch sspp0 */ - - /* vig 0 */ - { DBGBUS_SSPP0, 0, 0 }, - { DBGBUS_SSPP0, 0, 1 }, - { DBGBUS_SSPP0, 0, 2 }, - { DBGBUS_SSPP0, 0, 3 }, - { DBGBUS_SSPP0, 0, 4 }, - { DBGBUS_SSPP0, 0, 5 }, - { DBGBUS_SSPP0, 0, 6 }, - { DBGBUS_SSPP0, 0, 7 }, - - { DBGBUS_SSPP0, 1, 0 }, - { DBGBUS_SSPP0, 1, 1 }, - { DBGBUS_SSPP0, 1, 2 }, - { DBGBUS_SSPP0, 1, 3 }, - { DBGBUS_SSPP0, 1, 4 }, - { DBGBUS_SSPP0, 1, 5 }, - { DBGBUS_SSPP0, 1, 6 }, - { DBGBUS_SSPP0, 1, 7 }, - - { DBGBUS_SSPP0, 2, 0 }, - { DBGBUS_SSPP0, 2, 1 }, - { DBGBUS_SSPP0, 2, 2 }, - { DBGBUS_SSPP0, 2, 3 }, - { DBGBUS_SSPP0, 2, 4 }, - { DBGBUS_SSPP0, 2, 5 }, - { DBGBUS_SSPP0, 2, 6 }, - { DBGBUS_SSPP0, 2, 7 }, - - { DBGBUS_SSPP0, 4, 0 }, - { DBGBUS_SSPP0, 4, 1 }, - { DBGBUS_SSPP0, 4, 2 }, - { DBGBUS_SSPP0, 4, 3 }, - { DBGBUS_SSPP0, 4, 4 }, - { DBGBUS_SSPP0, 4, 5 }, - { DBGBUS_SSPP0, 4, 6 }, - { DBGBUS_SSPP0, 4, 7 }, - - { DBGBUS_SSPP0, 5, 0 }, - { DBGBUS_SSPP0, 5, 1 }, - { DBGBUS_SSPP0, 5, 2 }, - { DBGBUS_SSPP0, 5, 3 }, - { DBGBUS_SSPP0, 5, 4 }, - { DBGBUS_SSPP0, 5, 5 }, - { DBGBUS_SSPP0, 5, 6 }, - { DBGBUS_SSPP0, 5, 7 }, - - /* vig 2 */ - { DBGBUS_SSPP0, 20, 0 }, - { DBGBUS_SSPP0, 20, 1 }, - { DBGBUS_SSPP0, 20, 2 }, - { DBGBUS_SSPP0, 20, 3 }, - { DBGBUS_SSPP0, 20, 4 }, - { DBGBUS_SSPP0, 20, 5 }, - { DBGBUS_SSPP0, 20, 6 }, - { DBGBUS_SSPP0, 20, 7 }, - - { DBGBUS_SSPP0, 21, 0 }, - { DBGBUS_SSPP0, 21, 1 }, - { DBGBUS_SSPP0, 21, 2 }, - { DBGBUS_SSPP0, 21, 3 }, - { DBGBUS_SSPP0, 21, 4 }, - { DBGBUS_SSPP0, 21, 5 }, - { DBGBUS_SSPP0, 21, 6 }, - { DBGBUS_SSPP0, 21, 7 }, - - { DBGBUS_SSPP0, 22, 0 }, - { DBGBUS_SSPP0, 22, 1 }, - { DBGBUS_SSPP0, 22, 2 }, - { DBGBUS_SSPP0, 22, 3 }, - { DBGBUS_SSPP0, 22, 4 }, - { DBGBUS_SSPP0, 22, 5 }, - { DBGBUS_SSPP0, 22, 6 }, - { DBGBUS_SSPP0, 22, 7 }, - - { DBGBUS_SSPP0, 24, 0 }, - { DBGBUS_SSPP0, 24, 1 }, - { DBGBUS_SSPP0, 24, 2 }, - { DBGBUS_SSPP0, 24, 3 }, - { DBGBUS_SSPP0, 24, 4 }, - { DBGBUS_SSPP0, 24, 5 }, - { DBGBUS_SSPP0, 24, 6 }, - { DBGBUS_SSPP0, 24, 7 }, - - { DBGBUS_SSPP0, 25, 0 }, - { DBGBUS_SSPP0, 25, 1 }, - { DBGBUS_SSPP0, 25, 2 }, - { DBGBUS_SSPP0, 25, 3 }, - { DBGBUS_SSPP0, 25, 4 }, - { DBGBUS_SSPP0, 25, 5 }, - { DBGBUS_SSPP0, 25, 6 }, - { DBGBUS_SSPP0, 25, 7 }, - - /* dma 2 */ - { DBGBUS_SSPP0, 30, 0 }, - { DBGBUS_SSPP0, 30, 1 }, - { DBGBUS_SSPP0, 30, 2 }, - { DBGBUS_SSPP0, 30, 3 }, - { DBGBUS_SSPP0, 30, 4 }, - { DBGBUS_SSPP0, 30, 5 }, - { DBGBUS_SSPP0, 30, 6 }, - { DBGBUS_SSPP0, 30, 7 }, - - { DBGBUS_SSPP0, 31, 0 }, - { DBGBUS_SSPP0, 31, 1 }, - { DBGBUS_SSPP0, 31, 2 }, - { DBGBUS_SSPP0, 31, 3 }, - { DBGBUS_SSPP0, 31, 4 }, - { DBGBUS_SSPP0, 31, 5 }, - { DBGBUS_SSPP0, 31, 6 }, - { DBGBUS_SSPP0, 31, 7 }, - - { DBGBUS_SSPP0, 32, 0 }, - { DBGBUS_SSPP0, 32, 1 }, - { DBGBUS_SSPP0, 32, 2 }, - { DBGBUS_SSPP0, 32, 3 }, - { DBGBUS_SSPP0, 32, 4 }, - { DBGBUS_SSPP0, 32, 5 }, - { DBGBUS_SSPP0, 32, 6 }, - { DBGBUS_SSPP0, 32, 7 }, - - { DBGBUS_SSPP0, 33, 0 }, - { DBGBUS_SSPP0, 33, 1 }, - { DBGBUS_SSPP0, 33, 2 }, - { DBGBUS_SSPP0, 33, 3 }, - { DBGBUS_SSPP0, 33, 4 }, - { DBGBUS_SSPP0, 33, 5 }, - { DBGBUS_SSPP0, 33, 6 }, - { DBGBUS_SSPP0, 33, 7 }, - - { DBGBUS_SSPP0, 34, 0 }, - { DBGBUS_SSPP0, 34, 1 }, - { DBGBUS_SSPP0, 34, 2 }, - { DBGBUS_SSPP0, 34, 3 }, - { DBGBUS_SSPP0, 34, 4 }, - { DBGBUS_SSPP0, 34, 5 }, - { DBGBUS_SSPP0, 34, 6 }, - { DBGBUS_SSPP0, 34, 7 }, - - { DBGBUS_SSPP0, 35, 0 }, - { DBGBUS_SSPP0, 35, 1 }, - { DBGBUS_SSPP0, 35, 2 }, - { DBGBUS_SSPP0, 35, 3 }, - - /* dma 0 */ - { DBGBUS_SSPP0, 40, 0 }, - { DBGBUS_SSPP0, 40, 1 }, - { DBGBUS_SSPP0, 40, 2 }, - { DBGBUS_SSPP0, 40, 3 }, - { DBGBUS_SSPP0, 40, 4 }, - { DBGBUS_SSPP0, 40, 5 }, - { DBGBUS_SSPP0, 40, 6 }, - { DBGBUS_SSPP0, 40, 7 }, - - { DBGBUS_SSPP0, 41, 0 }, - { DBGBUS_SSPP0, 41, 1 }, - { DBGBUS_SSPP0, 41, 2 }, - { DBGBUS_SSPP0, 41, 3 }, - { DBGBUS_SSPP0, 41, 4 }, - { DBGBUS_SSPP0, 41, 5 }, - { DBGBUS_SSPP0, 41, 6 }, - { DBGBUS_SSPP0, 41, 7 }, - - { DBGBUS_SSPP0, 42, 0 }, - { DBGBUS_SSPP0, 42, 1 }, - { DBGBUS_SSPP0, 42, 2 }, - { DBGBUS_SSPP0, 42, 3 }, - { DBGBUS_SSPP0, 42, 4 }, - { DBGBUS_SSPP0, 42, 5 }, - { DBGBUS_SSPP0, 42, 6 }, - { DBGBUS_SSPP0, 42, 7 }, - - { DBGBUS_SSPP0, 44, 0 }, - { DBGBUS_SSPP0, 44, 1 }, - { DBGBUS_SSPP0, 44, 2 }, - { DBGBUS_SSPP0, 44, 3 }, - { DBGBUS_SSPP0, 44, 4 }, - { DBGBUS_SSPP0, 44, 5 }, - { DBGBUS_SSPP0, 44, 6 }, - { DBGBUS_SSPP0, 44, 7 }, - - { DBGBUS_SSPP0, 45, 0 }, - { DBGBUS_SSPP0, 45, 1 }, - { DBGBUS_SSPP0, 45, 2 }, - { DBGBUS_SSPP0, 45, 3 }, - { DBGBUS_SSPP0, 45, 4 }, - { DBGBUS_SSPP0, 45, 5 }, - { DBGBUS_SSPP0, 45, 6 }, - { DBGBUS_SSPP0, 45, 7 }, - - /* fetch sspp1 */ - /* vig 1 */ - { DBGBUS_SSPP1, 0, 0 }, - { DBGBUS_SSPP1, 0, 1 }, - { DBGBUS_SSPP1, 0, 2 }, - { DBGBUS_SSPP1, 0, 3 }, - { DBGBUS_SSPP1, 0, 4 }, - { DBGBUS_SSPP1, 0, 5 }, - { DBGBUS_SSPP1, 0, 6 }, - { DBGBUS_SSPP1, 0, 7 }, - - { DBGBUS_SSPP1, 1, 0 }, - { DBGBUS_SSPP1, 1, 1 }, - { DBGBUS_SSPP1, 1, 2 }, - { DBGBUS_SSPP1, 1, 3 }, - { DBGBUS_SSPP1, 1, 4 }, - { DBGBUS_SSPP1, 1, 5 }, - { DBGBUS_SSPP1, 1, 6 }, - { DBGBUS_SSPP1, 1, 7 }, - - { DBGBUS_SSPP1, 2, 0 }, - { DBGBUS_SSPP1, 2, 1 }, - { DBGBUS_SSPP1, 2, 2 }, - { DBGBUS_SSPP1, 2, 3 }, - { DBGBUS_SSPP1, 2, 4 }, - { DBGBUS_SSPP1, 2, 5 }, - { DBGBUS_SSPP1, 2, 6 }, - { DBGBUS_SSPP1, 2, 7 }, - - { DBGBUS_SSPP1, 4, 0 }, - { DBGBUS_SSPP1, 4, 1 }, - { DBGBUS_SSPP1, 4, 2 }, - { DBGBUS_SSPP1, 4, 3 }, - { DBGBUS_SSPP1, 4, 4 }, - { DBGBUS_SSPP1, 4, 5 }, - { DBGBUS_SSPP1, 4, 6 }, - { DBGBUS_SSPP1, 4, 7 }, - - { DBGBUS_SSPP1, 5, 0 }, - { DBGBUS_SSPP1, 5, 1 }, - { DBGBUS_SSPP1, 5, 2 }, - { DBGBUS_SSPP1, 5, 3 }, - { DBGBUS_SSPP1, 5, 4 }, - { DBGBUS_SSPP1, 5, 5 }, - { DBGBUS_SSPP1, 5, 6 }, - { DBGBUS_SSPP1, 5, 7 }, - - /* vig 3 */ - { DBGBUS_SSPP1, 20, 0 }, - { DBGBUS_SSPP1, 20, 1 }, - { DBGBUS_SSPP1, 20, 2 }, - { DBGBUS_SSPP1, 20, 3 }, - { DBGBUS_SSPP1, 20, 4 }, - { DBGBUS_SSPP1, 20, 5 }, - { DBGBUS_SSPP1, 20, 6 }, - { DBGBUS_SSPP1, 20, 7 }, - - { DBGBUS_SSPP1, 21, 0 }, - { DBGBUS_SSPP1, 21, 1 }, - { DBGBUS_SSPP1, 21, 2 }, - { DBGBUS_SSPP1, 21, 3 }, - { DBGBUS_SSPP1, 21, 4 }, - { DBGBUS_SSPP1, 21, 5 }, - { DBGBUS_SSPP1, 21, 6 }, - { DBGBUS_SSPP1, 21, 7 }, - - { DBGBUS_SSPP1, 22, 0 }, - { DBGBUS_SSPP1, 22, 1 }, - { DBGBUS_SSPP1, 22, 2 }, - { DBGBUS_SSPP1, 22, 3 }, - { DBGBUS_SSPP1, 22, 4 }, - { DBGBUS_SSPP1, 22, 5 }, - { DBGBUS_SSPP1, 22, 6 }, - { DBGBUS_SSPP1, 22, 7 }, - - { DBGBUS_SSPP1, 24, 0 }, - { DBGBUS_SSPP1, 24, 1 }, - { DBGBUS_SSPP1, 24, 2 }, - { DBGBUS_SSPP1, 24, 3 }, - { DBGBUS_SSPP1, 24, 4 }, - { DBGBUS_SSPP1, 24, 5 }, - { DBGBUS_SSPP1, 24, 6 }, - { DBGBUS_SSPP1, 24, 7 }, - - { DBGBUS_SSPP1, 25, 0 }, - { DBGBUS_SSPP1, 25, 1 }, - { DBGBUS_SSPP1, 25, 2 }, - { DBGBUS_SSPP1, 25, 3 }, - { DBGBUS_SSPP1, 25, 4 }, - { DBGBUS_SSPP1, 25, 5 }, - { DBGBUS_SSPP1, 25, 6 }, - { DBGBUS_SSPP1, 25, 7 }, - - /* dma 3 */ - { DBGBUS_SSPP1, 30, 0 }, - { DBGBUS_SSPP1, 30, 1 }, - { DBGBUS_SSPP1, 30, 2 }, - { DBGBUS_SSPP1, 30, 3 }, - { DBGBUS_SSPP1, 30, 4 }, - { DBGBUS_SSPP1, 30, 5 }, - { DBGBUS_SSPP1, 30, 6 }, - { DBGBUS_SSPP1, 30, 7 }, - - { DBGBUS_SSPP1, 31, 0 }, - { DBGBUS_SSPP1, 31, 1 }, - { DBGBUS_SSPP1, 31, 2 }, - { DBGBUS_SSPP1, 31, 3 }, - { DBGBUS_SSPP1, 31, 4 }, - { DBGBUS_SSPP1, 31, 5 }, - { DBGBUS_SSPP1, 31, 6 }, - { DBGBUS_SSPP1, 31, 7 }, - - { DBGBUS_SSPP1, 32, 0 }, - { DBGBUS_SSPP1, 32, 1 }, - { DBGBUS_SSPP1, 32, 2 }, - { DBGBUS_SSPP1, 32, 3 }, - { DBGBUS_SSPP1, 32, 4 }, - { DBGBUS_SSPP1, 32, 5 }, - { DBGBUS_SSPP1, 32, 6 }, - { DBGBUS_SSPP1, 32, 7 }, - - { DBGBUS_SSPP1, 33, 0 }, - { DBGBUS_SSPP1, 33, 1 }, - { DBGBUS_SSPP1, 33, 2 }, - { DBGBUS_SSPP1, 33, 3 }, - { DBGBUS_SSPP1, 33, 4 }, - { DBGBUS_SSPP1, 33, 5 }, - { DBGBUS_SSPP1, 33, 6 }, - { DBGBUS_SSPP1, 33, 7 }, - - { DBGBUS_SSPP1, 34, 0 }, - { DBGBUS_SSPP1, 34, 1 }, - { DBGBUS_SSPP1, 34, 2 }, - { DBGBUS_SSPP1, 34, 3 }, - { DBGBUS_SSPP1, 34, 4 }, - { DBGBUS_SSPP1, 34, 5 }, - { DBGBUS_SSPP1, 34, 6 }, - { DBGBUS_SSPP1, 34, 7 }, - - { DBGBUS_SSPP1, 35, 0 }, - { DBGBUS_SSPP1, 35, 1 }, - { DBGBUS_SSPP1, 35, 2 }, - - /* dma 1 */ - { DBGBUS_SSPP1, 40, 0 }, - { DBGBUS_SSPP1, 40, 1 }, - { DBGBUS_SSPP1, 40, 2 }, - { DBGBUS_SSPP1, 40, 3 }, - { DBGBUS_SSPP1, 40, 4 }, - { DBGBUS_SSPP1, 40, 5 }, - { DBGBUS_SSPP1, 40, 6 }, - { DBGBUS_SSPP1, 40, 7 }, - - { DBGBUS_SSPP1, 41, 0 }, - { DBGBUS_SSPP1, 41, 1 }, - { DBGBUS_SSPP1, 41, 2 }, - { DBGBUS_SSPP1, 41, 3 }, - { DBGBUS_SSPP1, 41, 4 }, - { DBGBUS_SSPP1, 41, 5 }, - { DBGBUS_SSPP1, 41, 6 }, - { DBGBUS_SSPP1, 41, 7 }, - - { DBGBUS_SSPP1, 42, 0 }, - { DBGBUS_SSPP1, 42, 1 }, - { DBGBUS_SSPP1, 42, 2 }, - { DBGBUS_SSPP1, 42, 3 }, - { DBGBUS_SSPP1, 42, 4 }, - { DBGBUS_SSPP1, 42, 5 }, - { DBGBUS_SSPP1, 42, 6 }, - { DBGBUS_SSPP1, 42, 7 }, - - { DBGBUS_SSPP1, 44, 0 }, - { DBGBUS_SSPP1, 44, 1 }, - { DBGBUS_SSPP1, 44, 2 }, - { DBGBUS_SSPP1, 44, 3 }, - { DBGBUS_SSPP1, 44, 4 }, - { DBGBUS_SSPP1, 44, 5 }, - { DBGBUS_SSPP1, 44, 6 }, - { DBGBUS_SSPP1, 44, 7 }, - - { DBGBUS_SSPP1, 45, 0 }, - { DBGBUS_SSPP1, 45, 1 }, - { DBGBUS_SSPP1, 45, 2 }, - { DBGBUS_SSPP1, 45, 3 }, - { DBGBUS_SSPP1, 45, 4 }, - { DBGBUS_SSPP1, 45, 5 }, - { DBGBUS_SSPP1, 45, 6 }, - { DBGBUS_SSPP1, 45, 7 }, - - /* dspp */ - { DBGBUS_DSPP, 13, 0 }, - { DBGBUS_DSPP, 19, 0 }, - { DBGBUS_DSPP, 14, 0 }, - { DBGBUS_DSPP, 14, 1 }, - { DBGBUS_DSPP, 14, 3 }, - { DBGBUS_DSPP, 20, 0 }, - { DBGBUS_DSPP, 20, 1 }, - { DBGBUS_DSPP, 20, 3 }, - - /* ppb_0 */ - { DBGBUS_DSPP, 31, 0, _dpu_debug_bus_ppb0_dump }, - { DBGBUS_DSPP, 33, 0, _dpu_debug_bus_ppb0_dump }, - { DBGBUS_DSPP, 35, 0, _dpu_debug_bus_ppb0_dump }, - { DBGBUS_DSPP, 42, 0, _dpu_debug_bus_ppb0_dump }, - - /* ppb_1 */ - { DBGBUS_DSPP, 32, 0, _dpu_debug_bus_ppb1_dump }, - { DBGBUS_DSPP, 34, 0, _dpu_debug_bus_ppb1_dump }, - { DBGBUS_DSPP, 36, 0, _dpu_debug_bus_ppb1_dump }, - { DBGBUS_DSPP, 43, 0, _dpu_debug_bus_ppb1_dump }, - - /* lm_lut */ - { DBGBUS_DSPP, 109, 0 }, - { DBGBUS_DSPP, 105, 0 }, - { DBGBUS_DSPP, 103, 0 }, - - /* crossbar */ - { DBGBUS_DSPP, 0, 0, _dpu_debug_bus_xbar_dump }, - - /* rotator */ - { DBGBUS_DSPP, 9, 0}, - - /* blend */ - /* LM0 */ - { DBGBUS_DSPP, 63, 1}, - { DBGBUS_DSPP, 63, 2}, - { DBGBUS_DSPP, 63, 3}, - { DBGBUS_DSPP, 63, 4}, - { DBGBUS_DSPP, 63, 5}, - { DBGBUS_DSPP, 63, 6}, - { DBGBUS_DSPP, 63, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 64, 1}, - { DBGBUS_DSPP, 64, 2}, - { DBGBUS_DSPP, 64, 3}, - { DBGBUS_DSPP, 64, 4}, - { DBGBUS_DSPP, 64, 5}, - { DBGBUS_DSPP, 64, 6}, - { DBGBUS_DSPP, 64, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 65, 1}, - { DBGBUS_DSPP, 65, 2}, - { DBGBUS_DSPP, 65, 3}, - { DBGBUS_DSPP, 65, 4}, - { DBGBUS_DSPP, 65, 5}, - { DBGBUS_DSPP, 65, 6}, - { DBGBUS_DSPP, 65, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 66, 1}, - { DBGBUS_DSPP, 66, 2}, - { DBGBUS_DSPP, 66, 3}, - { DBGBUS_DSPP, 66, 4}, - { DBGBUS_DSPP, 66, 5}, - { DBGBUS_DSPP, 66, 6}, - { DBGBUS_DSPP, 66, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 67, 1}, - { DBGBUS_DSPP, 67, 2}, - { DBGBUS_DSPP, 67, 3}, - { DBGBUS_DSPP, 67, 4}, - { DBGBUS_DSPP, 67, 5}, - { DBGBUS_DSPP, 67, 6}, - { DBGBUS_DSPP, 67, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 68, 1}, - { DBGBUS_DSPP, 68, 2}, - { DBGBUS_DSPP, 68, 3}, - { DBGBUS_DSPP, 68, 4}, - { DBGBUS_DSPP, 68, 5}, - { DBGBUS_DSPP, 68, 6}, - { DBGBUS_DSPP, 68, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 69, 1}, - { DBGBUS_DSPP, 69, 2}, - { DBGBUS_DSPP, 69, 3}, - { DBGBUS_DSPP, 69, 4}, - { DBGBUS_DSPP, 69, 5}, - { DBGBUS_DSPP, 69, 6}, - { DBGBUS_DSPP, 69, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 84, 1}, - { DBGBUS_DSPP, 84, 2}, - { DBGBUS_DSPP, 84, 3}, - { DBGBUS_DSPP, 84, 4}, - { DBGBUS_DSPP, 84, 5}, - { DBGBUS_DSPP, 84, 6}, - { DBGBUS_DSPP, 84, 7, _dpu_debug_bus_lm_dump }, - - - { DBGBUS_DSPP, 85, 1}, - { DBGBUS_DSPP, 85, 2}, - { DBGBUS_DSPP, 85, 3}, - { DBGBUS_DSPP, 85, 4}, - { DBGBUS_DSPP, 85, 5}, - { DBGBUS_DSPP, 85, 6}, - { DBGBUS_DSPP, 85, 7, _dpu_debug_bus_lm_dump }, - - - { DBGBUS_DSPP, 86, 1}, - { DBGBUS_DSPP, 86, 2}, - { DBGBUS_DSPP, 86, 3}, - { DBGBUS_DSPP, 86, 4}, - { DBGBUS_DSPP, 86, 5}, - { DBGBUS_DSPP, 86, 6}, - { DBGBUS_DSPP, 86, 7, _dpu_debug_bus_lm_dump }, - - - { DBGBUS_DSPP, 87, 1}, - { DBGBUS_DSPP, 87, 2}, - { DBGBUS_DSPP, 87, 3}, - { DBGBUS_DSPP, 87, 4}, - { DBGBUS_DSPP, 87, 5}, - { DBGBUS_DSPP, 87, 6}, - { DBGBUS_DSPP, 87, 7, _dpu_debug_bus_lm_dump }, - - /* LM1 */ - { DBGBUS_DSPP, 70, 1}, - { DBGBUS_DSPP, 70, 2}, - { DBGBUS_DSPP, 70, 3}, - { DBGBUS_DSPP, 70, 4}, - { DBGBUS_DSPP, 70, 5}, - { DBGBUS_DSPP, 70, 6}, - { DBGBUS_DSPP, 70, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 71, 1}, - { DBGBUS_DSPP, 71, 2}, - { DBGBUS_DSPP, 71, 3}, - { DBGBUS_DSPP, 71, 4}, - { DBGBUS_DSPP, 71, 5}, - { DBGBUS_DSPP, 71, 6}, - { DBGBUS_DSPP, 71, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 72, 1}, - { DBGBUS_DSPP, 72, 2}, - { DBGBUS_DSPP, 72, 3}, - { DBGBUS_DSPP, 72, 4}, - { DBGBUS_DSPP, 72, 5}, - { DBGBUS_DSPP, 72, 6}, - { DBGBUS_DSPP, 72, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 73, 1}, - { DBGBUS_DSPP, 73, 2}, - { DBGBUS_DSPP, 73, 3}, - { DBGBUS_DSPP, 73, 4}, - { DBGBUS_DSPP, 73, 5}, - { DBGBUS_DSPP, 73, 6}, - { DBGBUS_DSPP, 73, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 74, 1}, - { DBGBUS_DSPP, 74, 2}, - { DBGBUS_DSPP, 74, 3}, - { DBGBUS_DSPP, 74, 4}, - { DBGBUS_DSPP, 74, 5}, - { DBGBUS_DSPP, 74, 6}, - { DBGBUS_DSPP, 74, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 75, 1}, - { DBGBUS_DSPP, 75, 2}, - { DBGBUS_DSPP, 75, 3}, - { DBGBUS_DSPP, 75, 4}, - { DBGBUS_DSPP, 75, 5}, - { DBGBUS_DSPP, 75, 6}, - { DBGBUS_DSPP, 75, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 76, 1}, - { DBGBUS_DSPP, 76, 2}, - { DBGBUS_DSPP, 76, 3}, - { DBGBUS_DSPP, 76, 4}, - { DBGBUS_DSPP, 76, 5}, - { DBGBUS_DSPP, 76, 6}, - { DBGBUS_DSPP, 76, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 88, 1}, - { DBGBUS_DSPP, 88, 2}, - { DBGBUS_DSPP, 88, 3}, - { DBGBUS_DSPP, 88, 4}, - { DBGBUS_DSPP, 88, 5}, - { DBGBUS_DSPP, 88, 6}, - { DBGBUS_DSPP, 88, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 89, 1}, - { DBGBUS_DSPP, 89, 2}, - { DBGBUS_DSPP, 89, 3}, - { DBGBUS_DSPP, 89, 4}, - { DBGBUS_DSPP, 89, 5}, - { DBGBUS_DSPP, 89, 6}, - { DBGBUS_DSPP, 89, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 90, 1}, - { DBGBUS_DSPP, 90, 2}, - { DBGBUS_DSPP, 90, 3}, - { DBGBUS_DSPP, 90, 4}, - { DBGBUS_DSPP, 90, 5}, - { DBGBUS_DSPP, 90, 6}, - { DBGBUS_DSPP, 90, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 91, 1}, - { DBGBUS_DSPP, 91, 2}, - { DBGBUS_DSPP, 91, 3}, - { DBGBUS_DSPP, 91, 4}, - { DBGBUS_DSPP, 91, 5}, - { DBGBUS_DSPP, 91, 6}, - { DBGBUS_DSPP, 91, 7, _dpu_debug_bus_lm_dump }, - - /* LM2 */ - { DBGBUS_DSPP, 77, 0}, - { DBGBUS_DSPP, 77, 1}, - { DBGBUS_DSPP, 77, 2}, - { DBGBUS_DSPP, 77, 3}, - { DBGBUS_DSPP, 77, 4}, - { DBGBUS_DSPP, 77, 5}, - { DBGBUS_DSPP, 77, 6}, - { DBGBUS_DSPP, 77, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 78, 0}, - { DBGBUS_DSPP, 78, 1}, - { DBGBUS_DSPP, 78, 2}, - { DBGBUS_DSPP, 78, 3}, - { DBGBUS_DSPP, 78, 4}, - { DBGBUS_DSPP, 78, 5}, - { DBGBUS_DSPP, 78, 6}, - { DBGBUS_DSPP, 78, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 79, 0}, - { DBGBUS_DSPP, 79, 1}, - { DBGBUS_DSPP, 79, 2}, - { DBGBUS_DSPP, 79, 3}, - { DBGBUS_DSPP, 79, 4}, - { DBGBUS_DSPP, 79, 5}, - { DBGBUS_DSPP, 79, 6}, - { DBGBUS_DSPP, 79, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 80, 0}, - { DBGBUS_DSPP, 80, 1}, - { DBGBUS_DSPP, 80, 2}, - { DBGBUS_DSPP, 80, 3}, - { DBGBUS_DSPP, 80, 4}, - { DBGBUS_DSPP, 80, 5}, - { DBGBUS_DSPP, 80, 6}, - { DBGBUS_DSPP, 80, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 81, 0}, - { DBGBUS_DSPP, 81, 1}, - { DBGBUS_DSPP, 81, 2}, - { DBGBUS_DSPP, 81, 3}, - { DBGBUS_DSPP, 81, 4}, - { DBGBUS_DSPP, 81, 5}, - { DBGBUS_DSPP, 81, 6}, - { DBGBUS_DSPP, 81, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 82, 0}, - { DBGBUS_DSPP, 82, 1}, - { DBGBUS_DSPP, 82, 2}, - { DBGBUS_DSPP, 82, 3}, - { DBGBUS_DSPP, 82, 4}, - { DBGBUS_DSPP, 82, 5}, - { DBGBUS_DSPP, 82, 6}, - { DBGBUS_DSPP, 82, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 83, 0}, - { DBGBUS_DSPP, 83, 1}, - { DBGBUS_DSPP, 83, 2}, - { DBGBUS_DSPP, 83, 3}, - { DBGBUS_DSPP, 83, 4}, - { DBGBUS_DSPP, 83, 5}, - { DBGBUS_DSPP, 83, 6}, - { DBGBUS_DSPP, 83, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 92, 1}, - { DBGBUS_DSPP, 92, 2}, - { DBGBUS_DSPP, 92, 3}, - { DBGBUS_DSPP, 92, 4}, - { DBGBUS_DSPP, 92, 5}, - { DBGBUS_DSPP, 92, 6}, - { DBGBUS_DSPP, 92, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 93, 1}, - { DBGBUS_DSPP, 93, 2}, - { DBGBUS_DSPP, 93, 3}, - { DBGBUS_DSPP, 93, 4}, - { DBGBUS_DSPP, 93, 5}, - { DBGBUS_DSPP, 93, 6}, - { DBGBUS_DSPP, 93, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 94, 1}, - { DBGBUS_DSPP, 94, 2}, - { DBGBUS_DSPP, 94, 3}, - { DBGBUS_DSPP, 94, 4}, - { DBGBUS_DSPP, 94, 5}, - { DBGBUS_DSPP, 94, 6}, - { DBGBUS_DSPP, 94, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 95, 1}, - { DBGBUS_DSPP, 95, 2}, - { DBGBUS_DSPP, 95, 3}, - { DBGBUS_DSPP, 95, 4}, - { DBGBUS_DSPP, 95, 5}, - { DBGBUS_DSPP, 95, 6}, - { DBGBUS_DSPP, 95, 7, _dpu_debug_bus_lm_dump }, - - /* LM5 */ - { DBGBUS_DSPP, 110, 1}, - { DBGBUS_DSPP, 110, 2}, - { DBGBUS_DSPP, 110, 3}, - { DBGBUS_DSPP, 110, 4}, - { DBGBUS_DSPP, 110, 5}, - { DBGBUS_DSPP, 110, 6}, - { DBGBUS_DSPP, 110, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 111, 1}, - { DBGBUS_DSPP, 111, 2}, - { DBGBUS_DSPP, 111, 3}, - { DBGBUS_DSPP, 111, 4}, - { DBGBUS_DSPP, 111, 5}, - { DBGBUS_DSPP, 111, 6}, - { DBGBUS_DSPP, 111, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 112, 1}, - { DBGBUS_DSPP, 112, 2}, - { DBGBUS_DSPP, 112, 3}, - { DBGBUS_DSPP, 112, 4}, - { DBGBUS_DSPP, 112, 5}, - { DBGBUS_DSPP, 112, 6}, - { DBGBUS_DSPP, 112, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 113, 1}, - { DBGBUS_DSPP, 113, 2}, - { DBGBUS_DSPP, 113, 3}, - { DBGBUS_DSPP, 113, 4}, - { DBGBUS_DSPP, 113, 5}, - { DBGBUS_DSPP, 113, 6}, - { DBGBUS_DSPP, 113, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 114, 1}, - { DBGBUS_DSPP, 114, 2}, - { DBGBUS_DSPP, 114, 3}, - { DBGBUS_DSPP, 114, 4}, - { DBGBUS_DSPP, 114, 5}, - { DBGBUS_DSPP, 114, 6}, - { DBGBUS_DSPP, 114, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 115, 1}, - { DBGBUS_DSPP, 115, 2}, - { DBGBUS_DSPP, 115, 3}, - { DBGBUS_DSPP, 115, 4}, - { DBGBUS_DSPP, 115, 5}, - { DBGBUS_DSPP, 115, 6}, - { DBGBUS_DSPP, 115, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 116, 1}, - { DBGBUS_DSPP, 116, 2}, - { DBGBUS_DSPP, 116, 3}, - { DBGBUS_DSPP, 116, 4}, - { DBGBUS_DSPP, 116, 5}, - { DBGBUS_DSPP, 116, 6}, - { DBGBUS_DSPP, 116, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 117, 1}, - { DBGBUS_DSPP, 117, 2}, - { DBGBUS_DSPP, 117, 3}, - { DBGBUS_DSPP, 117, 4}, - { DBGBUS_DSPP, 117, 5}, - { DBGBUS_DSPP, 117, 6}, - { DBGBUS_DSPP, 117, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 118, 1}, - { DBGBUS_DSPP, 118, 2}, - { DBGBUS_DSPP, 118, 3}, - { DBGBUS_DSPP, 118, 4}, - { DBGBUS_DSPP, 118, 5}, - { DBGBUS_DSPP, 118, 6}, - { DBGBUS_DSPP, 118, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 119, 1}, - { DBGBUS_DSPP, 119, 2}, - { DBGBUS_DSPP, 119, 3}, - { DBGBUS_DSPP, 119, 4}, - { DBGBUS_DSPP, 119, 5}, - { DBGBUS_DSPP, 119, 6}, - { DBGBUS_DSPP, 119, 7, _dpu_debug_bus_lm_dump }, - - { DBGBUS_DSPP, 120, 1}, - { DBGBUS_DSPP, 120, 2}, - { DBGBUS_DSPP, 120, 3}, - { DBGBUS_DSPP, 120, 4}, - { DBGBUS_DSPP, 120, 5}, - { DBGBUS_DSPP, 120, 6}, - { DBGBUS_DSPP, 120, 7, _dpu_debug_bus_lm_dump }, - - /* csc */ - { DBGBUS_SSPP0, 7, 0}, - { DBGBUS_SSPP0, 7, 1}, - { DBGBUS_SSPP0, 27, 0}, - { DBGBUS_SSPP0, 27, 1}, - { DBGBUS_SSPP1, 7, 0}, - { DBGBUS_SSPP1, 7, 1}, - { DBGBUS_SSPP1, 27, 0}, - { DBGBUS_SSPP1, 27, 1}, - - /* pcc */ - { DBGBUS_SSPP0, 3, 3}, - { DBGBUS_SSPP0, 23, 3}, - { DBGBUS_SSPP0, 33, 3}, - { DBGBUS_SSPP0, 43, 3}, - { DBGBUS_SSPP1, 3, 3}, - { DBGBUS_SSPP1, 23, 3}, - { DBGBUS_SSPP1, 33, 3}, - { DBGBUS_SSPP1, 43, 3}, - - /* spa */ - { DBGBUS_SSPP0, 8, 0}, - { DBGBUS_SSPP0, 28, 0}, - { DBGBUS_SSPP1, 8, 0}, - { DBGBUS_SSPP1, 28, 0}, - { DBGBUS_DSPP, 13, 0}, - { DBGBUS_DSPP, 19, 0}, - - /* igc */ - { DBGBUS_SSPP0, 17, 0}, - { DBGBUS_SSPP0, 17, 1}, - { DBGBUS_SSPP0, 17, 3}, - { DBGBUS_SSPP0, 37, 0}, - { DBGBUS_SSPP0, 37, 1}, - { DBGBUS_SSPP0, 37, 3}, - { DBGBUS_SSPP0, 46, 0}, - { DBGBUS_SSPP0, 46, 1}, - { DBGBUS_SSPP0, 46, 3}, - - { DBGBUS_SSPP1, 17, 0}, - { DBGBUS_SSPP1, 17, 1}, - { DBGBUS_SSPP1, 17, 3}, - { DBGBUS_SSPP1, 37, 0}, - { DBGBUS_SSPP1, 37, 1}, - { DBGBUS_SSPP1, 37, 3}, - { DBGBUS_SSPP1, 46, 0}, - { DBGBUS_SSPP1, 46, 1}, - { DBGBUS_SSPP1, 46, 3}, - - { DBGBUS_DSPP, 14, 0}, - { DBGBUS_DSPP, 14, 1}, - { DBGBUS_DSPP, 14, 3}, - { DBGBUS_DSPP, 20, 0}, - { DBGBUS_DSPP, 20, 1}, - { DBGBUS_DSPP, 20, 3}, - - /* intf0-3 */ - { DBGBUS_PERIPH, 0, 0}, - { DBGBUS_PERIPH, 1, 0}, - { DBGBUS_PERIPH, 2, 0}, - { DBGBUS_PERIPH, 3, 0}, - - /* te counter wrapper */ - { DBGBUS_PERIPH, 60, 0}, - - /* dsc0 */ - { DBGBUS_PERIPH, 47, 0}, - { DBGBUS_PERIPH, 47, 1}, - { DBGBUS_PERIPH, 47, 2}, - { DBGBUS_PERIPH, 47, 3}, - { DBGBUS_PERIPH, 47, 4}, - { DBGBUS_PERIPH, 47, 5}, - { DBGBUS_PERIPH, 47, 6}, - { DBGBUS_PERIPH, 47, 7}, - - /* dsc1 */ - { DBGBUS_PERIPH, 48, 0}, - { DBGBUS_PERIPH, 48, 1}, - { DBGBUS_PERIPH, 48, 2}, - { DBGBUS_PERIPH, 48, 3}, - { DBGBUS_PERIPH, 48, 4}, - { DBGBUS_PERIPH, 48, 5}, - { DBGBUS_PERIPH, 48, 6}, - { DBGBUS_PERIPH, 48, 7}, - - /* dsc2 */ - { DBGBUS_PERIPH, 51, 0}, - { DBGBUS_PERIPH, 51, 1}, - { DBGBUS_PERIPH, 51, 2}, - { DBGBUS_PERIPH, 51, 3}, - { DBGBUS_PERIPH, 51, 4}, - { DBGBUS_PERIPH, 51, 5}, - { DBGBUS_PERIPH, 51, 6}, - { DBGBUS_PERIPH, 51, 7}, - - /* dsc3 */ - { DBGBUS_PERIPH, 52, 0}, - { DBGBUS_PERIPH, 52, 1}, - { DBGBUS_PERIPH, 52, 2}, - { DBGBUS_PERIPH, 52, 3}, - { DBGBUS_PERIPH, 52, 4}, - { DBGBUS_PERIPH, 52, 5}, - { DBGBUS_PERIPH, 52, 6}, - { DBGBUS_PERIPH, 52, 7}, - - /* tear-check */ - { DBGBUS_PERIPH, 63, 0 }, - { DBGBUS_PERIPH, 64, 0 }, - { DBGBUS_PERIPH, 65, 0 }, - { DBGBUS_PERIPH, 73, 0 }, - { DBGBUS_PERIPH, 74, 0 }, - - /* cdwn */ - { DBGBUS_PERIPH, 80, 0}, - { DBGBUS_PERIPH, 80, 1}, - { DBGBUS_PERIPH, 80, 2}, - - { DBGBUS_PERIPH, 81, 0}, - { DBGBUS_PERIPH, 81, 1}, - { DBGBUS_PERIPH, 81, 2}, - - { DBGBUS_PERIPH, 82, 0}, - { DBGBUS_PERIPH, 82, 1}, - { DBGBUS_PERIPH, 82, 2}, - { DBGBUS_PERIPH, 82, 3}, - { DBGBUS_PERIPH, 82, 4}, - { DBGBUS_PERIPH, 82, 5}, - { DBGBUS_PERIPH, 82, 6}, - { DBGBUS_PERIPH, 82, 7}, - - /* hdmi */ - { DBGBUS_PERIPH, 68, 0}, - { DBGBUS_PERIPH, 68, 1}, - { DBGBUS_PERIPH, 68, 2}, - { DBGBUS_PERIPH, 68, 3}, - { DBGBUS_PERIPH, 68, 4}, - { DBGBUS_PERIPH, 68, 5}, - - /* edp */ - { DBGBUS_PERIPH, 69, 0}, - { DBGBUS_PERIPH, 69, 1}, - { DBGBUS_PERIPH, 69, 2}, - { DBGBUS_PERIPH, 69, 3}, - { DBGBUS_PERIPH, 69, 4}, - { DBGBUS_PERIPH, 69, 5}, - - /* dsi0 */ - { DBGBUS_PERIPH, 70, 0}, - { DBGBUS_PERIPH, 70, 1}, - { DBGBUS_PERIPH, 70, 2}, - { DBGBUS_PERIPH, 70, 3}, - { DBGBUS_PERIPH, 70, 4}, - { DBGBUS_PERIPH, 70, 5}, - - /* dsi1 */ - { DBGBUS_PERIPH, 71, 0}, - { DBGBUS_PERIPH, 71, 1}, - { DBGBUS_PERIPH, 71, 2}, - { DBGBUS_PERIPH, 71, 3}, - { DBGBUS_PERIPH, 71, 4}, - { DBGBUS_PERIPH, 71, 5}, -}; - -static struct vbif_debug_bus_entry vbif_dbg_bus_msm8998[] = { - {0x214, 0x21c, 16, 2, 0x0, 0xd}, /* arb clients */ - {0x214, 0x21c, 16, 2, 0x80, 0xc0}, /* arb clients */ - {0x214, 0x21c, 16, 2, 0x100, 0x140}, /* arb clients */ - {0x214, 0x21c, 0, 16, 0x0, 0xf}, /* xin blocks - axi side */ - {0x214, 0x21c, 0, 16, 0x80, 0xa4}, /* xin blocks - axi side */ - {0x214, 0x21c, 0, 15, 0x100, 0x124}, /* xin blocks - axi side */ - {0x21c, 0x214, 0, 14, 0, 0xc}, /* xin blocks - clock side */ -}; - -/** - * _dpu_dbg_enable_power - use callback to turn power on for hw register access - * @enable: whether to turn power on or off - */ -static inline void _dpu_dbg_enable_power(int enable) -{ - if (enable) - pm_runtime_get_sync(dpu_dbg_base.dev); - else - pm_runtime_put_sync(dpu_dbg_base.dev); -} - -static void _dpu_dbg_dump_dpu_dbg_bus(struct dpu_dbg_dpu_debug_bus *bus) -{ - bool in_log, in_mem; - u32 **dump_mem = NULL; - u32 *dump_addr = NULL; - u32 status = 0; - struct dpu_debug_bus_entry *head; - phys_addr_t phys = 0; - int list_size; - int i; - u32 offset; - void __iomem *mem_base = NULL; - struct dpu_dbg_reg_base *reg_base; - - if (!bus || !bus->cmn.entries_size) - return; - - list_for_each_entry(reg_base, &dpu_dbg_base.reg_base_list, - reg_base_head) - if (strlen(reg_base->name) && - !strcmp(reg_base->name, bus->cmn.name)) - mem_base = reg_base->base + bus->top_blk_off; - - if (!mem_base) { - pr_err("unable to find mem_base for %s\n", bus->cmn.name); - return; - } - - dump_mem = &bus->cmn.dumped_content; - - /* will keep in memory 4 entries of 4 bytes each */ - list_size = (bus->cmn.entries_size * 4 * 4); - - in_log = (bus->cmn.enable_mask & DPU_DBG_DUMP_IN_LOG); - in_mem = (bus->cmn.enable_mask & DPU_DBG_DUMP_IN_MEM); - - if (!in_log && !in_mem) - return; - - dev_info(dpu_dbg_base.dev, "======== start %s dump =========\n", - bus->cmn.name); - - if (in_mem) { - if (!(*dump_mem)) - *dump_mem = dma_alloc_coherent(dpu_dbg_base.dev, - list_size, &phys, GFP_KERNEL); - - if (*dump_mem) { - dump_addr = *dump_mem; - dev_info(dpu_dbg_base.dev, - "%s: start_addr:0x%pK len:0x%x\n", - __func__, dump_addr, list_size); - } else { - in_mem = false; - pr_err("dump_mem: allocation fails\n"); - } - } - - _dpu_dbg_enable_power(true); - for (i = 0; i < bus->cmn.entries_size; i++) { - head = bus->entries + i; - writel_relaxed(TEST_MASK(head->block_id, head->test_id), - mem_base + head->wr_addr); - wmb(); /* make sure test bits were written */ - - if (bus->cmn.flags & DBGBUS_FLAGS_DSPP) { - offset = DBGBUS_DSPP_STATUS; - /* keep DSPP test point enabled */ - if (head->wr_addr != DBGBUS_DSPP) - writel_relaxed(0xF, mem_base + DBGBUS_DSPP); - } else { - offset = head->wr_addr + 0x4; - } - - status = readl_relaxed(mem_base + offset); - - if (in_log) - dev_info(dpu_dbg_base.dev, - "waddr=0x%x blk=%d tst=%d val=0x%x\n", - head->wr_addr, head->block_id, - head->test_id, status); - - if (dump_addr && in_mem) { - dump_addr[i*4] = head->wr_addr; - dump_addr[i*4 + 1] = head->block_id; - dump_addr[i*4 + 2] = head->test_id; - dump_addr[i*4 + 3] = status; - } - - if (head->analyzer) - head->analyzer(mem_base, head, status); - - /* Disable debug bus once we are done */ - writel_relaxed(0, mem_base + head->wr_addr); - if (bus->cmn.flags & DBGBUS_FLAGS_DSPP && - head->wr_addr != DBGBUS_DSPP) - writel_relaxed(0x0, mem_base + DBGBUS_DSPP); - } - _dpu_dbg_enable_power(false); - - dev_info(dpu_dbg_base.dev, "======== end %s dump =========\n", - bus->cmn.name); -} - -static void _dpu_dbg_dump_vbif_debug_bus_entry( - struct vbif_debug_bus_entry *head, void __iomem *mem_base, - u32 *dump_addr, bool in_log) -{ - int i, j; - u32 val; - - if (!dump_addr && !in_log) - return; - - for (i = 0; i < head->block_cnt; i++) { - writel_relaxed(1 << (i + head->bit_offset), - mem_base + head->block_bus_addr); - /* make sure that current bus blcok enable */ - wmb(); - for (j = head->test_pnt_start; j < head->test_pnt_cnt; j++) { - writel_relaxed(j, mem_base + head->block_bus_addr + 4); - /* make sure that test point is enabled */ - wmb(); - val = readl_relaxed(mem_base + MMSS_VBIF_TEST_BUS_OUT); - if (dump_addr) { - *dump_addr++ = head->block_bus_addr; - *dump_addr++ = i; - *dump_addr++ = j; - *dump_addr++ = val; - } - if (in_log) - dev_info(dpu_dbg_base.dev, - "testpoint:%x arb/xin id=%d index=%d val=0x%x\n", - head->block_bus_addr, i, j, val); - } - } -} - -static void _dpu_dbg_dump_vbif_dbg_bus(struct dpu_dbg_vbif_debug_bus *bus) -{ - bool in_log, in_mem; - u32 **dump_mem = NULL; - u32 *dump_addr = NULL; - u32 value, d0, d1; - unsigned long reg, reg1, reg2; - struct vbif_debug_bus_entry *head; - phys_addr_t phys = 0; - int i, list_size = 0; - void __iomem *mem_base = NULL; - struct vbif_debug_bus_entry *dbg_bus; - u32 bus_size; - struct dpu_dbg_reg_base *reg_base; - - if (!bus || !bus->cmn.entries_size) - return; - - list_for_each_entry(reg_base, &dpu_dbg_base.reg_base_list, - reg_base_head) - if (strlen(reg_base->name) && - !strcmp(reg_base->name, bus->cmn.name)) - mem_base = reg_base->base; - - if (!mem_base) { - pr_err("unable to find mem_base for %s\n", bus->cmn.name); - return; - } - - dbg_bus = bus->entries; - bus_size = bus->cmn.entries_size; - list_size = bus->cmn.entries_size; - dump_mem = &bus->cmn.dumped_content; - - dev_info(dpu_dbg_base.dev, "======== start %s dump =========\n", - bus->cmn.name); - - if (!dump_mem || !dbg_bus || !bus_size || !list_size) - return; - - /* allocate memory for each test point */ - for (i = 0; i < bus_size; i++) { - head = dbg_bus + i; - list_size += (head->block_cnt * head->test_pnt_cnt); - } - - /* 4 bytes * 4 entries for each test point*/ - list_size *= 16; - - in_log = (bus->cmn.enable_mask & DPU_DBG_DUMP_IN_LOG); - in_mem = (bus->cmn.enable_mask & DPU_DBG_DUMP_IN_MEM); - - if (!in_log && !in_mem) - return; - - if (in_mem) { - if (!(*dump_mem)) - *dump_mem = dma_alloc_coherent(dpu_dbg_base.dev, - list_size, &phys, GFP_KERNEL); - - if (*dump_mem) { - dump_addr = *dump_mem; - dev_info(dpu_dbg_base.dev, - "%s: start_addr:0x%pK len:0x%x\n", - __func__, dump_addr, list_size); - } else { - in_mem = false; - pr_err("dump_mem: allocation fails\n"); - } - } - - _dpu_dbg_enable_power(true); - - value = readl_relaxed(mem_base + MMSS_VBIF_CLKON); - writel_relaxed(value | BIT(1), mem_base + MMSS_VBIF_CLKON); - - /* make sure that vbif core is on */ - wmb(); - - /** - * Extract VBIF error info based on XIN halt and error status. - * If the XIN client is not in HALT state, or an error is detected, - * then retrieve the VBIF error info for it. - */ - reg = readl_relaxed(mem_base + MMSS_VBIF_XIN_HALT_CTRL1); - reg1 = readl_relaxed(mem_base + MMSS_VBIF_PND_ERR); - reg2 = readl_relaxed(mem_base + MMSS_VBIF_SRC_ERR); - dev_err(dpu_dbg_base.dev, - "XIN HALT:0x%lX, PND ERR:0x%lX, SRC ERR:0x%lX\n", - reg, reg1, reg2); - reg >>= 16; - reg &= ~(reg1 | reg2); - for (i = 0; i < MMSS_VBIF_CLIENT_NUM; i++) { - if (!test_bit(0, ®)) { - writel_relaxed(i, mem_base + MMSS_VBIF_ERR_INFO); - /* make sure reg write goes through */ - wmb(); - - d0 = readl_relaxed(mem_base + MMSS_VBIF_ERR_INFO); - d1 = readl_relaxed(mem_base + MMSS_VBIF_ERR_INFO_1); - - dev_err(dpu_dbg_base.dev, - "Client:%d, errinfo=0x%X, errinfo1=0x%X\n", - i, d0, d1); - } - reg >>= 1; - } - - for (i = 0; i < bus_size; i++) { - head = dbg_bus + i; - - writel_relaxed(0, mem_base + head->disable_bus_addr); - writel_relaxed(BIT(0), mem_base + MMSS_VBIF_TEST_BUS_OUT_CTRL); - /* make sure that other bus is off */ - wmb(); - - _dpu_dbg_dump_vbif_debug_bus_entry(head, mem_base, dump_addr, - in_log); - if (dump_addr) - dump_addr += (head->block_cnt * head->test_pnt_cnt * 4); - } - - _dpu_dbg_enable_power(false); - - dev_info(dpu_dbg_base.dev, "======== end %s dump =========\n", - bus->cmn.name); -} - -/** - * _dpu_dump_array - dump array of register bases - * @name: string indicating origin of dump - * @dump_dbgbus_dpu: whether to dump the dpu debug bus - * @dump_dbgbus_vbif_rt: whether to dump the vbif rt debug bus - */ -static void _dpu_dump_array(const char *name, bool dump_dbgbus_dpu, - bool dump_dbgbus_vbif_rt) -{ - if (dump_dbgbus_dpu) - _dpu_dbg_dump_dpu_dbg_bus(&dpu_dbg_base.dbgbus_dpu); - - if (dump_dbgbus_vbif_rt) - _dpu_dbg_dump_vbif_dbg_bus(&dpu_dbg_base.dbgbus_vbif_rt); -} - -/** - * _dpu_dump_work - deferred dump work function - * @work: work structure - */ -static void _dpu_dump_work(struct work_struct *work) -{ - _dpu_dump_array("dpudump_workitem", - dpu_dbg_base.dbgbus_dpu.cmn.include_in_deferred_work, - dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work); -} - -void dpu_dbg_dump(bool queue_work, const char *name, bool dump_dbgbus_dpu, - bool dump_dbgbus_vbif_rt) -{ - if (queue_work && work_pending(&dpu_dbg_base.dump_work)) - return; - - if (!queue_work) { - _dpu_dump_array(name, dump_dbgbus_dpu, dump_dbgbus_vbif_rt); - return; - } - - /* schedule work to dump later */ - dpu_dbg_base.dbgbus_dpu.cmn.include_in_deferred_work = dump_dbgbus_dpu; - dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work = - dump_dbgbus_vbif_rt; - schedule_work(&dpu_dbg_base.dump_work); -} - -/* - * dpu_dbg_debugfs_open - debugfs open handler for debug dump - * @inode: debugfs inode - * @file: file handle - */ -static int dpu_dbg_debugfs_open(struct inode *inode, struct file *file) -{ - /* non-seekable */ - file->f_mode &= ~(FMODE_LSEEK | FMODE_PREAD | FMODE_PWRITE); - file->private_data = inode->i_private; - return 0; -} - -/** - * dpu_dbg_dump_write - debugfs write handler for debug dump - * @file: file handler - * @user_buf: user buffer content from debugfs - * @count: size of user buffer - * @ppos: position offset of user buffer - */ -static ssize_t dpu_dbg_dump_write(struct file *file, - const char __user *user_buf, size_t count, loff_t *ppos) -{ - _dpu_dump_array("dump_debugfs", true, true); - return count; -} - -static const struct file_operations dpu_dbg_dump_fops = { - .open = dpu_dbg_debugfs_open, - .write = dpu_dbg_dump_write, -}; - -int dpu_dbg_debugfs_register(struct dentry *debugfs_root) -{ - static struct dpu_dbg_base *dbg = &dpu_dbg_base; - char debug_name[80] = ""; - - if (!debugfs_root) - return -EINVAL; - - debugfs_create_file("dump", 0600, debugfs_root, NULL, - &dpu_dbg_dump_fops); - - if (dbg->dbgbus_dpu.entries) { - dbg->dbgbus_dpu.cmn.name = DBGBUS_NAME_DPU; - snprintf(debug_name, sizeof(debug_name), "%s_dbgbus", - dbg->dbgbus_dpu.cmn.name); - dbg->dbgbus_dpu.cmn.enable_mask = DEFAULT_DBGBUS_DPU; - debugfs_create_u32(debug_name, 0600, debugfs_root, - &dbg->dbgbus_dpu.cmn.enable_mask); - } - - if (dbg->dbgbus_vbif_rt.entries) { - dbg->dbgbus_vbif_rt.cmn.name = DBGBUS_NAME_VBIF_RT; - snprintf(debug_name, sizeof(debug_name), "%s_dbgbus", - dbg->dbgbus_vbif_rt.cmn.name); - dbg->dbgbus_vbif_rt.cmn.enable_mask = DEFAULT_DBGBUS_VBIFRT; - debugfs_create_u32(debug_name, 0600, debugfs_root, - &dbg->dbgbus_vbif_rt.cmn.enable_mask); - } - - return 0; -} - -static void _dpu_dbg_debugfs_destroy(void) -{ -} - -void dpu_dbg_init_dbg_buses(u32 hwversion) -{ - static struct dpu_dbg_base *dbg = &dpu_dbg_base; - - memset(&dbg->dbgbus_dpu, 0, sizeof(dbg->dbgbus_dpu)); - memset(&dbg->dbgbus_vbif_rt, 0, sizeof(dbg->dbgbus_vbif_rt)); - - if (IS_MSM8998_TARGET(hwversion)) { - dbg->dbgbus_dpu.entries = dbg_bus_dpu_8998; - dbg->dbgbus_dpu.cmn.entries_size = ARRAY_SIZE(dbg_bus_dpu_8998); - dbg->dbgbus_dpu.cmn.flags = DBGBUS_FLAGS_DSPP; - - dbg->dbgbus_vbif_rt.entries = vbif_dbg_bus_msm8998; - dbg->dbgbus_vbif_rt.cmn.entries_size = - ARRAY_SIZE(vbif_dbg_bus_msm8998); - } else if (IS_SDM845_TARGET(hwversion) || IS_SDM670_TARGET(hwversion)) { - dbg->dbgbus_dpu.entries = dbg_bus_dpu_sdm845; - dbg->dbgbus_dpu.cmn.entries_size = - ARRAY_SIZE(dbg_bus_dpu_sdm845); - dbg->dbgbus_dpu.cmn.flags = DBGBUS_FLAGS_DSPP; - - /* vbif is unchanged vs 8998 */ - dbg->dbgbus_vbif_rt.entries = vbif_dbg_bus_msm8998; - dbg->dbgbus_vbif_rt.cmn.entries_size = - ARRAY_SIZE(vbif_dbg_bus_msm8998); - } else { - pr_err("unsupported chipset id %X\n", hwversion); - } -} - -int dpu_dbg_init(struct device *dev) -{ - if (!dev) { - pr_err("invalid params\n"); - return -EINVAL; - } - - INIT_LIST_HEAD(&dpu_dbg_base.reg_base_list); - dpu_dbg_base.dev = dev; - - INIT_WORK(&dpu_dbg_base.dump_work, _dpu_dump_work); - - return 0; -} - -/** - * dpu_dbg_destroy - destroy dpu debug facilities - */ -void dpu_dbg_destroy(void) -{ - _dpu_dbg_debugfs_destroy(); -} - -void dpu_dbg_set_dpu_top_offset(u32 blk_off) -{ - dpu_dbg_base.dbgbus_dpu.top_blk_off = blk_off; -} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h deleted file mode 100644 index 1e6fa945f98b..000000000000 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h +++ /dev/null @@ -1,103 +0,0 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef DPU_DBG_H_ -#define DPU_DBG_H_ - -#include <stdarg.h> -#include <linux/debugfs.h> -#include <linux/list.h> - -enum dpu_dbg_dump_flag { - DPU_DBG_DUMP_IN_LOG = BIT(0), - DPU_DBG_DUMP_IN_MEM = BIT(1), -}; - -#if defined(CONFIG_DEBUG_FS) - -/** - * dpu_dbg_init_dbg_buses - initialize debug bus dumping support for the chipset - * @hwversion: Chipset revision - */ -void dpu_dbg_init_dbg_buses(u32 hwversion); - -/** - * dpu_dbg_init - initialize global dpu debug facilities: regdump - * @dev: device handle - * Returns: 0 or -ERROR - */ -int dpu_dbg_init(struct device *dev); - -/** - * dpu_dbg_debugfs_register - register entries at the given debugfs dir - * @debugfs_root: debugfs root in which to create dpu debug entries - * Returns: 0 or -ERROR - */ -int dpu_dbg_debugfs_register(struct dentry *debugfs_root); - -/** - * dpu_dbg_destroy - destroy the global dpu debug facilities - * Returns: none - */ -void dpu_dbg_destroy(void); - -/** - * dpu_dbg_dump - trigger dumping of all dpu_dbg facilities - * @queue_work: whether to queue the dumping work to the work_struct - * @name: string indicating origin of dump - * @dump_dbgbus: dump the dpu debug bus - * @dump_vbif_rt: dump the vbif rt bus - * Returns: none - */ -void dpu_dbg_dump(bool queue_work, const char *name, bool dump_dbgbus_dpu, - bool dump_dbgbus_vbif_rt); - -/** - * dpu_dbg_set_dpu_top_offset - set the target specific offset from mdss base - * address of the top registers. Used for accessing debug bus controls. - * @blk_off: offset from mdss base of the top block - */ -void dpu_dbg_set_dpu_top_offset(u32 blk_off); - -#else - -static inline void dpu_dbg_init_dbg_buses(u32 hwversion) -{ -} - -static inline int dpu_dbg_init(struct device *dev) -{ - return 0; -} - -static inline int dpu_dbg_debugfs_register(struct dentry *debugfs_root) -{ - return 0; -} - -static inline void dpu_dbg_destroy(void) -{ -} - -static inline void dpu_dbg_dump(bool queue_work, const char *name, - bool dump_dbgbus_dpu, bool dump_dbgbus_vbif_rt) -{ -} - -static inline void dpu_dbg_set_dpu_top_offset(u32 blk_off) -{ -} - -#endif /* defined(CONFIG_DEBUG_FS) */ - - -#endif /* DPU_DBG_H_ */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index d31d8281424e..36158b7d99cd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -130,8 +130,9 @@ enum dpu_enc_rc_states { * Virtual encoder defers as much as possible to the physical encoders. * Virtual encoder registers itself with the DRM Framework as the encoder. * @base: drm_encoder base class for registration with DRM - * @enc_spin_lock: Virtual-Encoder-Wide Spin Lock for IRQ purposes + * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes * @bus_scaling_client: Client handle to the bus scaling interface + * @enabled: True if the encoder is active, protected by enc_lock * @num_phys_encs: Actual number of physical encoders contained. * @phys_encs: Container of physical encoders managed. * @cur_master: Pointer to the current master in this mode. Optimization @@ -141,15 +142,17 @@ enum dpu_enc_rc_states { * @intfs_swapped Whether or not the phys_enc interfaces have been swapped * for partial update right-only cases, such as pingpong * split where virtual pingpong does not generate IRQs - * @crtc_vblank_cb: Callback into the upper layer / CRTC for - * notification of the VBLANK - * @crtc_vblank_cb_data: Data from upper layer for VBLANK notification + * @crtc: Pointer to the currently assigned crtc. Normally you + * would use crtc->state->encoder_mask to determine the + * link between encoder/crtc. However in this case we need + * to track crtc in the disable() hook which is called + * _after_ encoder_mask is cleared. * @crtc_kickoff_cb: Callback into CRTC that will flush & start * all CTL paths * @crtc_kickoff_cb_data: Opaque user data given to crtc_kickoff_cb * @debugfs_root: Debug file system root file node - * @enc_lock: Lock around physical encoder create/destroy and - access. + * @enc_lock: Lock around physical encoder + * create/destroy/enable/disable * @frame_busy_mask: Bitmask tracking which phys_enc we are still * busy processing current command. * Bit0 = phys_encs[0] etc. @@ -175,6 +178,8 @@ struct dpu_encoder_virt { spinlock_t enc_spinlock; uint32_t bus_scaling_client; + bool enabled; + unsigned int num_phys_encs; struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; struct dpu_encoder_phys *cur_master; @@ -183,8 +188,7 @@ struct dpu_encoder_virt { bool intfs_swapped; - void (*crtc_vblank_cb)(void *); - void *crtc_vblank_cb_data; + struct drm_crtc *crtc; struct dentry *debugfs_root; struct mutex enc_lock; @@ -210,39 +214,6 @@ struct dpu_encoder_virt { }; #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base) -static inline int _dpu_encoder_power_enable(struct dpu_encoder_virt *dpu_enc, - bool enable) -{ - struct drm_encoder *drm_enc; - struct msm_drm_private *priv; - struct dpu_kms *dpu_kms; - - if (!dpu_enc) { - DPU_ERROR("invalid dpu enc\n"); - return -EINVAL; - } - - drm_enc = &dpu_enc->base; - if (!drm_enc->dev || !drm_enc->dev->dev_private) { - DPU_ERROR("drm device invalid\n"); - return -EINVAL; - } - - priv = drm_enc->dev->dev_private; - if (!priv->kms) { - DPU_ERROR("invalid kms\n"); - return -EINVAL; - } - - dpu_kms = to_dpu_kms(priv->kms); - - if (enable) - pm_runtime_get_sync(&dpu_kms->pdev->dev); - else - pm_runtime_put_sync(&dpu_kms->pdev->dev); - - return 0; -} void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, enum dpu_intr_idx intr_idx) @@ -1117,28 +1088,24 @@ static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc) _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info); } -void dpu_encoder_virt_restore(struct drm_encoder *drm_enc) +void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc) { - struct dpu_encoder_virt *dpu_enc = NULL; - int i; - - if (!drm_enc) { - DPU_ERROR("invalid encoder\n"); - return; - } - dpu_enc = to_dpu_encoder_virt(drm_enc); + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); - for (i = 0; i < dpu_enc->num_phys_encs; i++) { - struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; + mutex_lock(&dpu_enc->enc_lock); - if (phys && (phys != dpu_enc->cur_master) && phys->ops.restore) - phys->ops.restore(phys); - } + if (!dpu_enc->enabled) + goto out; + if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore) + dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave); if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore) dpu_enc->cur_master->ops.restore(dpu_enc->cur_master); _dpu_encoder_virt_enable_helper(drm_enc); + +out: + mutex_unlock(&dpu_enc->enc_lock); } static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc) @@ -1152,6 +1119,8 @@ static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc) return; } dpu_enc = to_dpu_encoder_virt(drm_enc); + + mutex_lock(&dpu_enc->enc_lock); cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay, @@ -1168,10 +1137,15 @@ static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc) if (ret) { DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n", ret); - return; + goto out; } _dpu_encoder_virt_enable_helper(drm_enc); + + dpu_enc->enabled = true; + +out: + mutex_unlock(&dpu_enc->enc_lock); } static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) @@ -1193,11 +1167,14 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) return; } - mode = &drm_enc->crtc->state->adjusted_mode; - dpu_enc = to_dpu_encoder_virt(drm_enc); DPU_DEBUG_ENC(dpu_enc, "\n"); + mutex_lock(&dpu_enc->enc_lock); + dpu_enc->enabled = false; + + mode = &drm_enc->crtc->state->adjusted_mode; + priv = drm_enc->dev->dev_private; dpu_kms = to_dpu_kms(priv->kms); @@ -1231,6 +1208,8 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n"); dpu_rm_release(&dpu_kms->rm, drm_enc); + + mutex_unlock(&dpu_enc->enc_lock); } static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog, @@ -1261,8 +1240,8 @@ static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc, dpu_enc = to_dpu_encoder_virt(drm_enc); spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); - if (dpu_enc->crtc_vblank_cb) - dpu_enc->crtc_vblank_cb(dpu_enc->crtc_vblank_cb_data); + if (dpu_enc->crtc) + dpu_crtc_vblank_callback(dpu_enc->crtc); spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); atomic_inc(&phy_enc->vsync_cnt); @@ -1282,25 +1261,32 @@ static void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, DPU_ATRACE_END("encoder_underrun_callback"); } -void dpu_encoder_register_vblank_callback(struct drm_encoder *drm_enc, - void (*vbl_cb)(void *), void *vbl_data) +void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc) { struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); unsigned long lock_flags; - bool enable; - int i; - enable = vbl_cb ? true : false; + spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); + /* crtc should always be cleared before re-assigning */ + WARN_ON(crtc && dpu_enc->crtc); + dpu_enc->crtc = crtc; + spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); +} + +void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc, + struct drm_crtc *crtc, bool enable) +{ + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); + unsigned long lock_flags; + int i; - if (!drm_enc) { - DPU_ERROR("invalid encoder\n"); - return; - } trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable); spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); - dpu_enc->crtc_vblank_cb = vbl_cb; - dpu_enc->crtc_vblank_cb_data = vbl_data; + if (dpu_enc->crtc != crtc) { + spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); + return; + } spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); for (i = 0; i < dpu_enc->num_phys_encs; i++) { @@ -1405,8 +1391,9 @@ static void dpu_encoder_off_work(struct kthread_work *work) * phys: Pointer to physical encoder structure * extra_flush_bits: Additional bit mask to include in flush trigger */ -static inline void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, - struct dpu_encoder_phys *phys, uint32_t extra_flush_bits) +static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, + struct dpu_encoder_phys *phys, uint32_t extra_flush_bits, + bool async) { struct dpu_hw_ctl *ctl; int pending_kickoff_cnt; @@ -1429,7 +1416,10 @@ static inline void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, return; } - pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys); + if (!async) + pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys); + else + pending_kickoff_cnt = atomic_read(&phys->pending_kickoff_cnt); if (extra_flush_bits && ctl->ops.update_pending_flush) ctl->ops.update_pending_flush(ctl, extra_flush_bits); @@ -1448,7 +1438,7 @@ static inline void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, * _dpu_encoder_trigger_start - trigger start for a physical encoder * phys: Pointer to physical encoder structure */ -static inline void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys) +static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys) { if (!phys) { DPU_ERROR("invalid argument(s)\n"); @@ -1505,7 +1495,7 @@ static int dpu_encoder_helper_wait_event_timeout( return rc; } -void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) +static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) { struct dpu_encoder_virt *dpu_enc; struct dpu_hw_ctl *ctl; @@ -1525,10 +1515,8 @@ void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) ctl->idx); rc = ctl->ops.reset(ctl); - if (rc) { + if (rc) DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx); - dpu_dbg_dump(false, __func__, true, true); - } phys_enc->enable_state = DPU_ENC_ENABLED; } @@ -1542,7 +1530,8 @@ void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) * a time. * dpu_enc: Pointer to virtual encoder structure */ -static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc) +static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc, + bool async) { struct dpu_hw_ctl *ctl; uint32_t i, pending_flush; @@ -1573,7 +1562,8 @@ static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc) set_bit(i, dpu_enc->frame_busy_mask); if (!phys->ops.needs_single_flush || !phys->ops.needs_single_flush(phys)) - _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0); + _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0, + async); else if (ctl->ops.get_pending_flush) pending_flush |= ctl->ops.get_pending_flush(ctl); } @@ -1583,7 +1573,7 @@ static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc) _dpu_encoder_trigger_flush( &dpu_enc->base, dpu_enc->cur_master, - pending_flush); + pending_flush, async); } _dpu_encoder_trigger_start(dpu_enc->cur_master); @@ -1767,7 +1757,7 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work) } void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc, - struct dpu_encoder_kickoff_params *params) + struct dpu_encoder_kickoff_params *params, bool async) { struct dpu_encoder_virt *dpu_enc; struct dpu_encoder_phys *phys; @@ -1801,14 +1791,12 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc, if (needs_hw_reset) { trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc)); for (i = 0; i < dpu_enc->num_phys_encs; i++) { - phys = dpu_enc->phys_encs[i]; - if (phys && phys->ops.hw_reset) - phys->ops.hw_reset(phys); + dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]); } } } -void dpu_encoder_kickoff(struct drm_encoder *drm_enc) +void dpu_encoder_kickoff(struct drm_encoder *drm_enc, bool async) { struct dpu_encoder_virt *dpu_enc; struct dpu_encoder_phys *phys; @@ -1831,7 +1819,7 @@ void dpu_encoder_kickoff(struct drm_encoder *drm_enc) ((atomic_read(&dpu_enc->frame_done_timeout) * HZ) / 1000)); /* All phys encs are ready to go, trigger the kickoff */ - _dpu_encoder_kickoff_phys(dpu_enc); + _dpu_encoder_kickoff_phys(dpu_enc, async); /* allow phys encs to handle any post-kickoff business */ for (i = 0; i < dpu_enc->num_phys_encs; i++) { @@ -1873,14 +1861,9 @@ void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc) #ifdef CONFIG_DEBUG_FS static int _dpu_encoder_status_show(struct seq_file *s, void *data) { - struct dpu_encoder_virt *dpu_enc; + struct dpu_encoder_virt *dpu_enc = s->private; int i; - if (!s || !s->private) - return -EINVAL; - - dpu_enc = s->private; - mutex_lock(&dpu_enc->enc_lock); for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; @@ -1918,7 +1901,7 @@ static int _dpu_encoder_debugfs_status_open(struct inode *inode, static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc) { - struct dpu_encoder_virt *dpu_enc; + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); struct msm_drm_private *priv; struct dpu_kms *dpu_kms; int i; @@ -1932,12 +1915,11 @@ static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc) char name[DPU_NAME_SIZE]; - if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) { + if (!drm_enc->dev || !drm_enc->dev->dev_private) { DPU_ERROR("invalid encoder or kms\n"); return -EINVAL; } - dpu_enc = to_dpu_encoder_virt(drm_enc); priv = drm_enc->dev->dev_private; dpu_kms = to_dpu_kms(priv->kms); @@ -1962,26 +1944,11 @@ static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc) return 0; } - -static void _dpu_encoder_destroy_debugfs(struct drm_encoder *drm_enc) -{ - struct dpu_encoder_virt *dpu_enc; - - if (!drm_enc) - return; - - dpu_enc = to_dpu_encoder_virt(drm_enc); - debugfs_remove_recursive(dpu_enc->debugfs_root); -} #else static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc) { return 0; } - -static void _dpu_encoder_destroy_debugfs(struct drm_encoder *drm_enc) -{ -} #endif static int dpu_encoder_late_register(struct drm_encoder *encoder) @@ -1991,7 +1958,9 @@ static int dpu_encoder_late_register(struct drm_encoder *encoder) static void dpu_encoder_early_unregister(struct drm_encoder *encoder) { - _dpu_encoder_destroy_debugfs(encoder); + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder); + + debugfs_remove_recursive(dpu_enc->debugfs_root); } static int dpu_encoder_virt_add_phys_encs( @@ -2266,6 +2235,8 @@ struct drm_encoder *dpu_encoder_init(struct drm_device *dev, drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs); + dpu_enc->enabled = false; + return &dpu_enc->base; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index 9dbf38f446d9..3f5dafe00580 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -55,14 +55,22 @@ void dpu_encoder_get_hw_resources(struct drm_encoder *encoder, struct dpu_encoder_hw_resources *hw_res); /** - * dpu_encoder_register_vblank_callback - provide callback to encoder that - * will be called on the next vblank. + * dpu_encoder_assign_crtc - Link the encoder to the crtc it's assigned to * @encoder: encoder pointer - * @cb: callback pointer, provide NULL to deregister and disable IRQs - * @data: user data provided to callback + * @crtc: crtc pointer + */ +void dpu_encoder_assign_crtc(struct drm_encoder *encoder, + struct drm_crtc *crtc); + +/** + * dpu_encoder_toggle_vblank_for_crtc - Toggles vblank interrupts on or off if + * the encoder is assigned to the given crtc + * @encoder: encoder pointer + * @crtc: crtc pointer + * @enable: true if vblank should be enabled */ -void dpu_encoder_register_vblank_callback(struct drm_encoder *encoder, - void (*cb)(void *), void *data); +void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *encoder, + struct drm_crtc *crtc, bool enable); /** * dpu_encoder_register_frame_event_callback - provide callback to encoder that @@ -81,9 +89,10 @@ void dpu_encoder_register_frame_event_callback(struct drm_encoder *encoder, * Delayed: Block until next trigger can be issued. * @encoder: encoder pointer * @params: kickoff time parameters + * @async: true if this is an asynchronous commit */ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *encoder, - struct dpu_encoder_kickoff_params *params); + struct dpu_encoder_kickoff_params *params, bool async); /** * dpu_encoder_trigger_kickoff_pending - Clear the flush bits from previous @@ -96,8 +105,9 @@ void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *encoder); * dpu_encoder_kickoff - trigger a double buffer flip of the ctl path * (i.e. ctl flush and start) immediately. * @encoder: encoder pointer + * @async: true if this is an asynchronous commit */ -void dpu_encoder_kickoff(struct drm_encoder *encoder); +void dpu_encoder_kickoff(struct drm_encoder *encoder, bool async); /** * dpu_encoder_wait_for_event - Waits for encoder events @@ -126,10 +136,10 @@ int dpu_encoder_wait_for_event(struct drm_encoder *drm_encoder, enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder); /** - * dpu_encoder_virt_restore - restore the encoder configs + * dpu_encoder_virt_runtime_resume - pm runtime resume the encoder configs * @encoder: encoder pointer */ -void dpu_encoder_virt_restore(struct drm_encoder *encoder); +void dpu_encoder_virt_runtime_resume(struct drm_encoder *encoder); /** * dpu_encoder_init - initialize virtual encoder object diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index 964efcc757a4..44e6f8b68e70 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -114,8 +114,6 @@ struct dpu_encoder_virt_ops { * @handle_post_kickoff: Do any work necessary post-kickoff work * @trigger_start: Process start event on physical encoder * @needs_single_flush: Whether encoder slaves need to be flushed - * @hw_reset: Issue HW recovery such as CTL reset and clear - * DPU_ENC_ERR_NEEDS_HW_RESET state * @irq_control: Handler to enable/disable all the encoder IRQs * @prepare_idle_pc: phys encoder can update the vsync_enable status * on idle power collapse prepare @@ -151,7 +149,6 @@ struct dpu_encoder_phys_ops { void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc); void (*trigger_start)(struct dpu_encoder_phys *phys_enc); bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc); - void (*hw_reset)(struct dpu_encoder_phys *phys_enc); void (*irq_control)(struct dpu_encoder_phys *phys, bool enable); void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc); void (*restore)(struct dpu_encoder_phys *phys); @@ -342,15 +339,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( */ void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc); -/** - * dpu_encoder_helper_hw_reset - issue ctl hw reset - * This helper function may be optionally specified by physical - * encoders if they require ctl hw reset. If state is currently - * DPU_ENC_ERR_NEEDS_HW_RESET, it is set back to DPU_ENC_ENABLED. - * @phys_enc: Pointer to physical encoder structure - */ -void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc); - static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( struct dpu_encoder_phys *phys_enc) { @@ -362,7 +350,7 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state); if (phys_enc->split_role == ENC_ROLE_SOLO && - dpu_crtc_state_is_stereo(dpu_cstate)) + dpu_cstate->num_mixers == CRTC_DUAL_MIXERS) return BLEND_3D_H_ROW_INT; return BLEND_3D_NONE; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index b2d7f0ded24c..99ab5ca9bed3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -44,14 +44,7 @@ #define DPU_ENC_WR_PTR_START_TIMEOUT_US 20000 -static inline int _dpu_encoder_phys_cmd_get_idle_timeout( - struct dpu_encoder_phys_cmd *cmd_enc) -{ - return KICKOFF_TIMEOUT_MS; -} - -static inline bool dpu_encoder_phys_cmd_is_master( - struct dpu_encoder_phys *phys_enc) +static bool dpu_encoder_phys_cmd_is_master(struct dpu_encoder_phys *phys_enc) { return (phys_enc->split_role != ENC_ROLE_SLAVE) ? true : false; } @@ -243,7 +236,6 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( atomic_read(&phys_enc->pending_kickoff_cnt)); dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR); - dpu_dbg_dump(false, __func__, true, true); } atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0); @@ -496,14 +488,11 @@ static void dpu_encoder_phys_cmd_enable_helper( _dpu_encoder_phys_cmd_pingpong_config(phys_enc); if (!dpu_encoder_phys_cmd_is_master(phys_enc)) - goto skip_flush; + return; ctl = phys_enc->hw_ctl; ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->intf_idx); ctl->ops.update_pending_flush(ctl, flush_mask); - -skip_flush: - return; } static void dpu_encoder_phys_cmd_enable(struct dpu_encoder_phys *phys_enc) @@ -727,7 +716,7 @@ static int dpu_encoder_phys_cmd_wait_for_vblank( wait_info.wq = &cmd_enc->pending_vblank_wq; wait_info.atomic_cnt = &cmd_enc->pending_vblank_cnt; - wait_info.timeout_ms = _dpu_encoder_phys_cmd_get_idle_timeout(cmd_enc); + wait_info.timeout_ms = KICKOFF_TIMEOUT_MS; atomic_inc(&cmd_enc->pending_vblank_cnt); @@ -776,7 +765,6 @@ static void dpu_encoder_phys_cmd_init_ops( ops->wait_for_vblank = dpu_encoder_phys_cmd_wait_for_vblank; ops->trigger_start = dpu_encoder_phys_cmd_trigger_start; ops->needs_single_flush = dpu_encoder_phys_cmd_needs_single_flush; - ops->hw_reset = dpu_encoder_helper_hw_reset; ops->irq_control = dpu_encoder_phys_cmd_irq_control; ops->restore = dpu_encoder_phys_cmd_enable_helper; ops->prepare_idle_pc = dpu_encoder_phys_cmd_prepare_idle_pc; @@ -798,7 +786,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( if (!cmd_enc) { ret = -ENOMEM; DPU_ERROR("failed to allocate\n"); - goto fail; + return ERR_PTR(ret); } phys_enc = &cmd_enc->base; phys_enc->hw_mdptop = p->dpu_kms->hw_mdp; @@ -856,6 +844,5 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( return phys_enc; -fail: return ERR_PTR(ret); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 84de385a9f62..acdab5b0db18 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -110,7 +110,7 @@ static void drm_mode_to_intf_timing_params( */ } -static inline u32 get_horizontal_total(const struct intf_timing_params *timing) +static u32 get_horizontal_total(const struct intf_timing_params *timing) { u32 active = timing->xres; u32 inactive = @@ -119,7 +119,7 @@ static inline u32 get_horizontal_total(const struct intf_timing_params *timing) return active + inactive; } -static inline u32 get_vertical_total(const struct intf_timing_params *timing) +static u32 get_vertical_total(const struct intf_timing_params *timing) { u32 active = timing->yres; u32 inactive = @@ -331,7 +331,7 @@ static void dpu_encoder_phys_vid_vblank_irq(void *arg, int irq_idx) if (hw_ctl && hw_ctl->ops.get_flush_register) flush_register = hw_ctl->ops.get_flush_register(hw_ctl); - if (flush_register == 0) + if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl))) new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); @@ -613,7 +613,6 @@ static void dpu_encoder_phys_vid_prepare_for_kickoff( DPU_ERROR_VIDENC(vid_enc, "ctl %d reset failure: %d\n", ctl->idx, rc); dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC); - dpu_dbg_dump(false, __func__, true, true); } } @@ -766,7 +765,6 @@ static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff; ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff; ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush; - ops->hw_reset = dpu_encoder_helper_hw_reset; ops->get_line_count = dpu_encoder_phys_vid_get_line_count; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index d743e7ca6a3c..0874f0a53bf9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -921,7 +921,7 @@ static int _dpu_format_populate_addrs_ubwc( + layout->plane_size[2] + layout->plane_size[3]; if (!meta) - goto done; + return 0; /* configure Y metadata plane */ layout->plane_addr[2] = base_addr; @@ -952,12 +952,11 @@ static int _dpu_format_populate_addrs_ubwc( layout->plane_addr[1] = 0; if (!meta) - goto done; + return 0; layout->plane_addr[2] = base_addr; layout->plane_addr[3] = 0; } -done: return 0; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c index 58d29e43faef..92f1c4241b9a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c @@ -30,16 +30,10 @@ static LIST_HEAD(dpu_hw_blk_list); * @type: hw block type - enum dpu_hw_blk_type * @id: instance id of the hw block * @ops: Pointer to block operations - * return: 0 if success; error code otherwise */ -int dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id, +void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id, struct dpu_hw_blk_ops *ops) { - if (!hw_blk) { - pr_err("invalid parameters\n"); - return -EINVAL; - } - INIT_LIST_HEAD(&hw_blk->list); hw_blk->type = type; hw_blk->id = id; @@ -51,8 +45,6 @@ int dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id, mutex_lock(&dpu_hw_blk_lock); list_add(&hw_blk->list, &dpu_hw_blk_list); mutex_unlock(&dpu_hw_blk_lock); - - return 0; } /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h index 0f4ca8af1ec5..1934c2f7e8fa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h @@ -44,7 +44,7 @@ struct dpu_hw_blk { struct dpu_hw_blk_ops ops; }; -int dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id, +void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id, struct dpu_hw_blk_ops *ops); void dpu_hw_blk_destroy(struct dpu_hw_blk *hw_blk); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index dc060e7358e4..144358a3d0fb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -736,13 +736,4 @@ struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev); */ void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg); -/** - * dpu_hw_sspp_multirect_enabled - check multirect enabled for the sspp - * @cfg: pointer to sspp cfg - */ -static inline bool dpu_hw_sspp_multirect_enabled(const struct dpu_sspp_cfg *cfg) -{ - return test_bit(DPU_SSPP_SMART_DMA_V1, &cfg->features) || - test_bit(DPU_SSPP_SMART_DMA_V2, &cfg->features); -} #endif /* _DPU_HW_CATALOG_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index eec1051f2afc..1068b4b7940f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -13,8 +13,8 @@ #include <linux/delay.h> #include "dpu_hwio.h" #include "dpu_hw_ctl.h" -#include "dpu_dbg.h" #include "dpu_kms.h" +#include "dpu_trace.h" #define CTL_LAYER(lm) \ (((lm) == LM_5) ? (0x024) : (((lm) - LM_0) * 0x004)) @@ -72,24 +72,39 @@ static int _mixer_stages(const struct dpu_lm_cfg *mixer, int count, return stages; } +static inline u32 dpu_hw_ctl_get_flush_register(struct dpu_hw_ctl *ctx) +{ + struct dpu_hw_blk_reg_map *c = &ctx->hw; + + return DPU_REG_READ(c, CTL_FLUSH); +} + static inline void dpu_hw_ctl_trigger_start(struct dpu_hw_ctl *ctx) { + trace_dpu_hw_ctl_trigger_start(ctx->pending_flush_mask, + dpu_hw_ctl_get_flush_register(ctx)); DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1); } static inline void dpu_hw_ctl_trigger_pending(struct dpu_hw_ctl *ctx) { + trace_dpu_hw_ctl_trigger_prepare(ctx->pending_flush_mask, + dpu_hw_ctl_get_flush_register(ctx)); DPU_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1); } static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx) { + trace_dpu_hw_ctl_clear_pending_flush(ctx->pending_flush_mask, + dpu_hw_ctl_get_flush_register(ctx)); ctx->pending_flush_mask = 0x0; } static inline void dpu_hw_ctl_update_pending_flush(struct dpu_hw_ctl *ctx, u32 flushbits) { + trace_dpu_hw_ctl_update_pending_flush(flushbits, + ctx->pending_flush_mask); ctx->pending_flush_mask |= flushbits; } @@ -103,18 +118,12 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx) static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx) { - + trace_dpu_hw_ctl_trigger_pending_flush(ctx->pending_flush_mask, + dpu_hw_ctl_get_flush_register(ctx)); DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask); } -static inline u32 dpu_hw_ctl_get_flush_register(struct dpu_hw_ctl *ctx) -{ - struct dpu_hw_blk_reg_map *c = &ctx->hw; - - return DPU_REG_READ(c, CTL_FLUSH); -} - -static inline uint32_t dpu_hw_ctl_get_bitmask_sspp(struct dpu_hw_ctl *ctx, +static uint32_t dpu_hw_ctl_get_bitmask_sspp(struct dpu_hw_ctl *ctx, enum dpu_sspp sspp) { uint32_t flushbits = 0; @@ -169,7 +178,7 @@ static inline uint32_t dpu_hw_ctl_get_bitmask_sspp(struct dpu_hw_ctl *ctx, return flushbits; } -static inline uint32_t dpu_hw_ctl_get_bitmask_mixer(struct dpu_hw_ctl *ctx, +static uint32_t dpu_hw_ctl_get_bitmask_mixer(struct dpu_hw_ctl *ctx, enum dpu_lm lm) { uint32_t flushbits = 0; @@ -202,7 +211,7 @@ static inline uint32_t dpu_hw_ctl_get_bitmask_mixer(struct dpu_hw_ctl *ctx, return flushbits; } -static inline int dpu_hw_ctl_get_bitmask_intf(struct dpu_hw_ctl *ctx, +static int dpu_hw_ctl_get_bitmask_intf(struct dpu_hw_ctl *ctx, u32 *flushbits, enum dpu_intf intf) { switch (intf) { @@ -474,10 +483,7 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, ops->get_bitmask_intf = dpu_hw_ctl_get_bitmask_intf; }; -static struct dpu_hw_blk_ops dpu_hw_ops = { - .start = NULL, - .stop = NULL, -}; +static struct dpu_hw_blk_ops dpu_hw_ops; struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, void __iomem *addr, @@ -485,7 +491,6 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, { struct dpu_hw_ctl *c; struct dpu_ctl_cfg *cfg; - int rc; c = kzalloc(sizeof(*c), GFP_KERNEL); if (!c) @@ -504,18 +509,9 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, c->mixer_count = m->mixer_count; c->mixer_hw_caps = m->mixer; - rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_CTL, idx, &dpu_hw_ops); - if (rc) { - DPU_ERROR("failed to init hw blk %d\n", rc); - goto blk_init_error; - } + dpu_hw_blk_init(&c->base, DPU_HW_BLK_CTL, idx, &dpu_hw_ops); return c; - -blk_init_error: - kzfree(c); - - return ERR_PTR(rc); } void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 9c6bba0ac7c3..f6a83daa385b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -13,7 +13,6 @@ #include "dpu_hwio.h" #include "dpu_hw_catalog.h" #include "dpu_hw_intf.h" -#include "dpu_dbg.h" #include "dpu_kms.h" #define INTF_TIMING_ENGINE_EN 0x000 @@ -265,10 +264,7 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, ops->get_line_count = dpu_hw_intf_get_line_count; } -static struct dpu_hw_blk_ops dpu_hw_ops = { - .start = NULL, - .stop = NULL, -}; +static struct dpu_hw_blk_ops dpu_hw_ops; struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, void __iomem *addr, @@ -276,7 +272,6 @@ struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, { struct dpu_hw_intf *c; struct dpu_intf_cfg *cfg; - int rc; c = kzalloc(sizeof(*c), GFP_KERNEL); if (!c) @@ -297,18 +292,9 @@ struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, c->mdss = m; _setup_intf_ops(&c->ops, c->cap->features); - rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx, &dpu_hw_ops); - if (rc) { - DPU_ERROR("failed to init hw blk %d\n", rc); - goto blk_init_error; - } + dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx, &dpu_hw_ops); return c; - -blk_init_error: - kzfree(c); - - return ERR_PTR(rc); } void dpu_hw_intf_destroy(struct dpu_hw_intf *intf) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h index 3b77df460dea..a2b0dbc23058 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -92,16 +92,6 @@ struct dpu_hw_intf { }; /** - * to_dpu_hw_intf - convert base object dpu_hw_base to container - * @hw: Pointer to base hardware block - * return: Pointer to hardware block container - */ -static inline struct dpu_hw_intf *to_dpu_hw_intf(struct dpu_hw_blk *hw) -{ - return container_of(hw, struct dpu_hw_intf, base); -} - -/** * dpu_hw_intf_init(): Initializes the intf driver for the passed * interface idx. * @idx: interface index for which driver object is required diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index acb8dc8acaa5..018df2c3b7ed 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -15,7 +15,6 @@ #include "dpu_hwio.h" #include "dpu_hw_lm.h" #include "dpu_hw_mdss.h" -#include "dpu_dbg.h" #include "dpu_kms.h" #define LM_OP_MODE 0x00 @@ -64,16 +63,10 @@ static struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer, static inline int _stage_offset(struct dpu_hw_mixer *ctx, enum dpu_stage stage) { const struct dpu_lm_sub_blks *sblk = ctx->cap->sblk; - int rc; + if (stage != DPU_STAGE_BASE && stage <= sblk->maxblendstages) + return sblk->blendstage_base[stage - DPU_STAGE_0]; - if (stage == DPU_STAGE_BASE) - rc = -EINVAL; - else if (stage <= sblk->maxblendstages) - rc = sblk->blendstage_base[stage - DPU_STAGE_0]; - else - rc = -EINVAL; - - return rc; + return -EINVAL; } static void dpu_hw_lm_setup_out(struct dpu_hw_mixer *ctx, @@ -163,11 +156,6 @@ static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx, DPU_REG_WRITE(c, LM_OP_MODE, op_mode); } -static void dpu_hw_lm_gc(struct dpu_hw_mixer *mixer, - void *cfg) -{ -} - static void _setup_mixer_ops(struct dpu_mdss_cfg *m, struct dpu_hw_lm_ops *ops, unsigned long features) @@ -179,13 +167,9 @@ static void _setup_mixer_ops(struct dpu_mdss_cfg *m, ops->setup_blend_config = dpu_hw_lm_setup_blend_config; ops->setup_alpha_out = dpu_hw_lm_setup_color3; ops->setup_border_color = dpu_hw_lm_setup_border_color; - ops->setup_gc = dpu_hw_lm_gc; }; -static struct dpu_hw_blk_ops dpu_hw_ops = { - .start = NULL, - .stop = NULL, -}; +static struct dpu_hw_blk_ops dpu_hw_ops; struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, void __iomem *addr, @@ -193,7 +177,6 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, { struct dpu_hw_mixer *c; struct dpu_lm_cfg *cfg; - int rc; c = kzalloc(sizeof(*c), GFP_KERNEL); if (!c) @@ -210,18 +193,9 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, c->cap = cfg; _setup_mixer_ops(m, &c->ops, c->cap->features); - rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx, &dpu_hw_ops); - if (rc) { - DPU_ERROR("failed to init hw blk %d\n", rc); - goto blk_init_error; - } + dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx, &dpu_hw_ops); return c; - -blk_init_error: - kzfree(c); - - return ERR_PTR(rc); } void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h index 5b036aca8340..6aee839a6a23 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h @@ -61,11 +61,6 @@ struct dpu_hw_lm_ops { void (*setup_border_color)(struct dpu_hw_mixer *ctx, struct dpu_mdss_color *color, u8 border_en); - /** - * setup_gc : enable/disable gamma correction feature - */ - void (*setup_gc)(struct dpu_hw_mixer *mixer, - void *cfg); }; struct dpu_hw_mixer { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c index cc3a623903f4..3bdf47ed1845 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -16,7 +16,6 @@ #include "dpu_hwio.h" #include "dpu_hw_catalog.h" #include "dpu_hw_pingpong.h" -#include "dpu_dbg.h" #include "dpu_kms.h" #include "dpu_trace.h" @@ -177,7 +176,7 @@ static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp) height = DPU_REG_READ(c, PP_SYNC_CONFIG_HEIGHT) & 0xFFFF; if (height < init) - goto line_count_exit; + return line; line = DPU_REG_READ(c, PP_INT_COUNT_VAL) & 0xFFFF; @@ -186,7 +185,6 @@ static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp) else line -= init; -line_count_exit: return line; } @@ -201,10 +199,7 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong_ops *ops, ops->get_line_count = dpu_hw_pp_get_line_count; }; -static struct dpu_hw_blk_ops dpu_hw_ops = { - .start = NULL, - .stop = NULL, -}; +static struct dpu_hw_blk_ops dpu_hw_ops; struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, void __iomem *addr, @@ -212,7 +207,6 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, { struct dpu_hw_pingpong *c; struct dpu_pingpong_cfg *cfg; - int rc; c = kzalloc(sizeof(*c), GFP_KERNEL); if (!c) @@ -228,18 +222,9 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, c->caps = cfg; _setup_pingpong_ops(&c->ops, c->caps); - rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_PINGPONG, idx, &dpu_hw_ops); - if (rc) { - DPU_ERROR("failed to init hw blk %d\n", rc); - goto blk_init_error; - } + dpu_hw_blk_init(&c->base, DPU_HW_BLK_PINGPONG, idx, &dpu_hw_ops); return c; - -blk_init_error: - kzfree(c); - - return ERR_PTR(rc); } void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h index 3caccd7d6a3e..0e02e43cee14 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h @@ -105,16 +105,6 @@ struct dpu_hw_pingpong { }; /** - * dpu_hw_pingpong - convert base object dpu_hw_base to container - * @hw: Pointer to base hardware block - * return: Pointer to hardware block container - */ -static inline struct dpu_hw_pingpong *to_dpu_hw_pingpong(struct dpu_hw_blk *hw) -{ - return container_of(hw, struct dpu_hw_pingpong, base); -} - -/** * dpu_hw_pingpong_init - initializes the pingpong driver for the passed * pingpong idx. * @idx: Pingpong index for which driver object is required diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index c25b52a6b219..e9132bf5166b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -14,7 +14,6 @@ #include "dpu_hw_catalog.h" #include "dpu_hw_lm.h" #include "dpu_hw_sspp.h" -#include "dpu_dbg.h" #include "dpu_kms.h" #define DPU_FETCH_CONFIG_RESET_VALUE 0x00000087 @@ -141,7 +140,7 @@ /* traffic shaper clock in Hz */ #define TS_CLK 19200000 -static inline int _sspp_subblk_offset(struct dpu_hw_pipe *ctx, +static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx, int s_id, u32 *idx) { @@ -662,7 +661,8 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c, test_bit(DPU_SSPP_CSC_10BIT, &features)) c->ops.setup_csc = dpu_hw_sspp_setup_csc; - if (dpu_hw_sspp_multirect_enabled(c->cap)) + if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) || + test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features)) c->ops.setup_multirect = dpu_hw_sspp_setup_multirect; if (test_bit(DPU_SSPP_SCALER_QSEED3, &features)) { @@ -697,10 +697,7 @@ static struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp, return ERR_PTR(-ENOMEM); } -static struct dpu_hw_blk_ops dpu_hw_ops = { - .start = NULL, - .stop = NULL, -}; +static struct dpu_hw_blk_ops dpu_hw_ops; struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, void __iomem *addr, struct dpu_mdss_cfg *catalog, @@ -708,7 +705,6 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, { struct dpu_hw_pipe *hw_pipe; struct dpu_sspp_cfg *cfg; - int rc; if (!addr || !catalog) return ERR_PTR(-EINVAL); @@ -730,18 +726,9 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, hw_pipe->cap = cfg; _setup_layer_ops(hw_pipe, hw_pipe->cap->features); - rc = dpu_hw_blk_init(&hw_pipe->base, DPU_HW_BLK_SSPP, idx, &dpu_hw_ops); - if (rc) { - DPU_ERROR("failed to init hw blk %d\n", rc); - goto blk_init_error; - } + dpu_hw_blk_init(&hw_pipe->base, DPU_HW_BLK_SSPP, idx, &dpu_hw_ops); return hw_pipe; - -blk_init_error: - kzfree(hw_pipe); - - return ERR_PTR(rc); } void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 4d81e5f5ce1b..119b4e1c16be 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -392,16 +392,6 @@ struct dpu_hw_pipe { }; /** - * dpu_hw_pipe - convert base object dpu_hw_base to container - * @hw: Pointer to base hardware block - * return: Pointer to hardware block container - */ -static inline struct dpu_hw_pipe *to_dpu_hw_pipe(struct dpu_hw_blk *hw) -{ - return container_of(hw, struct dpu_hw_pipe, base); -} - -/** * dpu_hw_sspp_init - initializes the sspp hw driver object. * Should be called once before accessing every pipe. * @idx: Pipe index for which driver object is required diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c index b8781256e21b..a041597bb849 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -13,7 +13,6 @@ #include "dpu_hwio.h" #include "dpu_hw_catalog.h" #include "dpu_hw_top.h" -#include "dpu_dbg.h" #include "dpu_kms.h" #define SSPP_SPARE 0x28 @@ -322,10 +321,7 @@ static const struct dpu_mdp_cfg *_top_offset(enum dpu_mdp mdp, return ERR_PTR(-EINVAL); } -static struct dpu_hw_blk_ops dpu_hw_ops = { - .start = NULL, - .stop = NULL, -}; +static struct dpu_hw_blk_ops dpu_hw_ops; struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx, void __iomem *addr, @@ -333,7 +329,6 @@ struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx, { struct dpu_hw_mdp *mdp; const struct dpu_mdp_cfg *cfg; - int rc; if (!addr || !m) return ERR_PTR(-EINVAL); @@ -355,20 +350,9 @@ struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx, mdp->caps = cfg; _setup_mdp_ops(&mdp->ops, mdp->caps->features); - rc = dpu_hw_blk_init(&mdp->base, DPU_HW_BLK_TOP, idx, &dpu_hw_ops); - if (rc) { - DPU_ERROR("failed to init hw blk %d\n", rc); - goto blk_init_error; - } - - dpu_dbg_set_dpu_top_offset(mdp->hw.blk_off); + dpu_hw_blk_init(&mdp->base, DPU_HW_BLK_TOP, idx, &dpu_hw_ops); return mdp; - -blk_init_error: - kzfree(mdp); - - return ERR_PTR(rc); } void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h index 192e338f20bb..aa21fd834398 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h @@ -161,16 +161,6 @@ struct dpu_hw_mdp { }; /** - * to_dpu_hw_mdp - convert base object dpu_hw_base to container - * @hw: Pointer to base hardware block - * return: Pointer to hardware block container - */ -static inline struct dpu_hw_mdp *to_dpu_hw_mdp(struct dpu_hw_blk *hw) -{ - return container_of(hw, struct dpu_hw_mdp, base); -} - -/** * dpu_hw_mdptop_init - initializes the top driver for the passed idx * @idx: Interface index for which driver object is required * @addr: Mapped register io address of MDP diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c index d43905525f92..38bfd222ed72 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c @@ -13,7 +13,6 @@ #include "dpu_hwio.h" #include "dpu_hw_catalog.h" #include "dpu_hw_vbif.h" -#include "dpu_dbg.h" #define VBIF_VERSION 0x0000 #define VBIF_CLK_FORCE_CTRL0 0x0008 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c index b557687b1964..78833c2c27f8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c @@ -16,6 +16,8 @@ #include <linux/err.h> #include <linux/delay.h> +#include <drm/drm_print.h> + #include "dpu_io_util.h" void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk) @@ -164,7 +166,7 @@ int msm_dss_parse_clock(struct platform_device *pdev, "clock-names", i, &clock_name); if (rc) { - dev_err(&pdev->dev, "Failed to get clock name for %d\n", + DRM_DEV_ERROR(&pdev->dev, "Failed to get clock name for %d\n", i); break; } @@ -176,13 +178,13 @@ int msm_dss_parse_clock(struct platform_device *pdev, rc = msm_dss_get_clk(&pdev->dev, mp->clk_config, num_clk); if (rc) { - dev_err(&pdev->dev, "Failed to get clock refs %d\n", rc); + DRM_DEV_ERROR(&pdev->dev, "Failed to get clock refs %d\n", rc); goto err; } rc = of_clk_set_defaults(pdev->dev.of_node, false); if (rc) { - dev_err(&pdev->dev, "Failed to set clock defaults %d\n", rc); + DRM_DEV_ERROR(&pdev->dev, "Failed to set clock defaults %d\n", rc); goto err; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c deleted file mode 100644 index d5e6ce0140cf..000000000000 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c +++ /dev/null @@ -1,66 +0,0 @@ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ - -#include <linux/irqdomain.h> -#include <linux/irq.h> -#include <linux/kthread.h> - -#include "dpu_irq.h" -#include "dpu_core_irq.h" - -irqreturn_t dpu_irq(struct msm_kms *kms) -{ - struct dpu_kms *dpu_kms = to_dpu_kms(kms); - - return dpu_core_irq(dpu_kms); -} - -void dpu_irq_preinstall(struct msm_kms *kms) -{ - struct dpu_kms *dpu_kms = to_dpu_kms(kms); - - if (!dpu_kms->dev || !dpu_kms->dev->dev) { - pr_err("invalid device handles\n"); - return; - } - - dpu_core_irq_preinstall(dpu_kms); -} - -int dpu_irq_postinstall(struct msm_kms *kms) -{ - struct dpu_kms *dpu_kms = to_dpu_kms(kms); - int rc; - - if (!kms) { - DPU_ERROR("invalid parameters\n"); - return -EINVAL; - } - - rc = dpu_core_irq_postinstall(dpu_kms); - - return rc; -} - -void dpu_irq_uninstall(struct msm_kms *kms) -{ - struct dpu_kms *dpu_kms = to_dpu_kms(kms); - - if (!kms) { - DPU_ERROR("invalid parameters\n"); - return; - } - - dpu_core_irq_uninstall(dpu_kms); -} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_irq.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_irq.h deleted file mode 100644 index 3e147f7176e2..000000000000 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_irq.h +++ /dev/null @@ -1,59 +0,0 @@ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __DPU_IRQ_H__ -#define __DPU_IRQ_H__ - -#include <linux/kernel.h> -#include <linux/irqdomain.h> - -#include "msm_kms.h" - -/** - * dpu_irq_controller - define MDSS level interrupt controller context - * @enabled_mask: enable status of MDSS level interrupt - * @domain: interrupt domain of this controller - */ -struct dpu_irq_controller { - unsigned long enabled_mask; - struct irq_domain *domain; -}; - -/** - * dpu_irq_preinstall - perform pre-installation of MDSS IRQ handler - * @kms: pointer to kms context - * @return: none - */ -void dpu_irq_preinstall(struct msm_kms *kms); - -/** - * dpu_irq_postinstall - perform post-installation of MDSS IRQ handler - * @kms: pointer to kms context - * @return: 0 if success; error code otherwise - */ -int dpu_irq_postinstall(struct msm_kms *kms); - -/** - * dpu_irq_uninstall - uninstall MDSS IRQ handler - * @drm_dev: pointer to kms context - * @return: none - */ -void dpu_irq_uninstall(struct msm_kms *kms); - -/** - * dpu_irq - MDSS level IRQ handler - * @kms: pointer to kms context - * @return: interrupt handling status - */ -irqreturn_t dpu_irq(struct msm_kms *kms); - -#endif /* __DPU_IRQ_H__ */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 0a683e65a9f3..4d67b3c96702 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -81,7 +81,7 @@ static int _dpu_danger_signal_status(struct seq_file *s, struct dpu_danger_safe_status status; int i; - if (!kms || !kms->dev || !kms->dev->dev_private || !kms->hw_mdp) { + if (!kms->dev || !kms->dev->dev_private || !kms->hw_mdp) { DPU_ERROR("invalid arg(s)\n"); return 0; } @@ -138,46 +138,29 @@ static int dpu_debugfs_safe_stats_show(struct seq_file *s, void *v) } DEFINE_DPU_DEBUGFS_SEQ_FOPS(dpu_debugfs_safe_stats); -static void dpu_debugfs_danger_destroy(struct dpu_kms *dpu_kms) -{ - debugfs_remove_recursive(dpu_kms->debugfs_danger); - dpu_kms->debugfs_danger = NULL; -} - -static int dpu_debugfs_danger_init(struct dpu_kms *dpu_kms, +static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms, struct dentry *parent) { - dpu_kms->debugfs_danger = debugfs_create_dir("danger", - parent); - if (!dpu_kms->debugfs_danger) { - DPU_ERROR("failed to create danger debugfs\n"); - return -EINVAL; - } + struct dentry *entry = debugfs_create_dir("danger", parent); + if (IS_ERR_OR_NULL(entry)) + return; - debugfs_create_file("danger_status", 0600, dpu_kms->debugfs_danger, + debugfs_create_file("danger_status", 0600, entry, dpu_kms, &dpu_debugfs_danger_stats_fops); - debugfs_create_file("safe_status", 0600, dpu_kms->debugfs_danger, + debugfs_create_file("safe_status", 0600, entry, dpu_kms, &dpu_debugfs_safe_stats_fops); - - return 0; } static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data) { - struct dpu_debugfs_regset32 *regset; - struct dpu_kms *dpu_kms; + struct dpu_debugfs_regset32 *regset = s->private; + struct dpu_kms *dpu_kms = regset->dpu_kms; struct drm_device *dev; struct msm_drm_private *priv; void __iomem *base; uint32_t i, addr; - if (!s || !s->private) - return 0; - - regset = s->private; - - dpu_kms = regset->dpu_kms; - if (!dpu_kms || !dpu_kms->mmio) + if (!dpu_kms->mmio) return 0; dev = dpu_kms->dev; @@ -250,57 +233,24 @@ void *dpu_debugfs_create_regset32(const char *name, umode_t mode, static int _dpu_debugfs_init(struct dpu_kms *dpu_kms) { - void *p; - int rc; - - p = dpu_hw_util_get_log_mask_ptr(); + void *p = dpu_hw_util_get_log_mask_ptr(); + struct dentry *entry; - if (!dpu_kms || !p) + if (!p) return -EINVAL; - dpu_kms->debugfs_root = debugfs_create_dir("debug", - dpu_kms->dev->primary->debugfs_root); - if (IS_ERR_OR_NULL(dpu_kms->debugfs_root)) { - DRM_ERROR("debugfs create_dir failed %ld\n", - PTR_ERR(dpu_kms->debugfs_root)); - return PTR_ERR(dpu_kms->debugfs_root); - } - - rc = dpu_dbg_debugfs_register(dpu_kms->debugfs_root); - if (rc) { - DRM_ERROR("failed to reg dpu dbg debugfs: %d\n", rc); - return rc; - } + entry = debugfs_create_dir("debug", dpu_kms->dev->primary->debugfs_root); + if (IS_ERR_OR_NULL(entry)) + return -ENODEV; /* allow root to be NULL */ - debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, dpu_kms->debugfs_root, p); - - (void) dpu_debugfs_danger_init(dpu_kms, dpu_kms->debugfs_root); - (void) dpu_debugfs_vbif_init(dpu_kms, dpu_kms->debugfs_root); - (void) dpu_debugfs_core_irq_init(dpu_kms, dpu_kms->debugfs_root); - - rc = dpu_core_perf_debugfs_init(&dpu_kms->perf, dpu_kms->debugfs_root); - if (rc) { - DPU_ERROR("failed to init perf %d\n", rc); - return rc; - } + debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, entry, p); - return 0; -} + dpu_debugfs_danger_init(dpu_kms, entry); + dpu_debugfs_vbif_init(dpu_kms, entry); + dpu_debugfs_core_irq_init(dpu_kms, entry); -static void _dpu_debugfs_destroy(struct dpu_kms *dpu_kms) -{ - /* don't need to NULL check debugfs_root */ - if (dpu_kms) { - dpu_debugfs_vbif_destroy(dpu_kms); - dpu_debugfs_danger_destroy(dpu_kms); - dpu_debugfs_core_irq_destroy(dpu_kms); - debugfs_remove_recursive(dpu_kms->debugfs_root); - } -} -#else -static void _dpu_debugfs_destroy(struct dpu_kms *dpu_kms) -{ + return dpu_core_perf_debugfs_init(dpu_kms, entry); } #endif @@ -320,7 +270,10 @@ static void dpu_kms_prepare_commit(struct msm_kms *kms, struct dpu_kms *dpu_kms; struct msm_drm_private *priv; struct drm_device *dev; + struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; struct drm_encoder *encoder; + int i; if (!kms) return; @@ -332,9 +285,13 @@ static void dpu_kms_prepare_commit(struct msm_kms *kms, priv = dev->dev_private; pm_runtime_get_sync(&dpu_kms->pdev->dev); - list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) - if (encoder->crtc != NULL) + /* Call prepare_commit for all affected encoders */ + for_each_new_crtc_in_state(state, crtc, crtc_state, i) { + drm_for_each_encoder_mask(encoder, crtc->dev, + crtc_state->encoder_mask) { dpu_encoder_prepare_commit(encoder); + } + } } /* @@ -344,15 +301,20 @@ static void dpu_kms_prepare_commit(struct msm_kms *kms, void dpu_kms_encoder_enable(struct drm_encoder *encoder) { const struct drm_encoder_helper_funcs *funcs = encoder->helper_private; - struct drm_crtc *crtc = encoder->crtc; + struct drm_device *dev = encoder->dev; + struct drm_crtc *crtc; /* Forward this enable call to the commit hook */ if (funcs && funcs->commit) funcs->commit(encoder); - if (crtc && crtc->state->active) { + WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); + drm_for_each_crtc(crtc, dev) { + if (!(crtc->state->encoder_mask & drm_encoder_mask(encoder))) + continue; + trace_dpu_kms_enc_enable(DRMID(crtc)); - dpu_crtc_commit_kickoff(crtc); + dpu_crtc_commit_kickoff(crtc, false); } } @@ -369,7 +331,8 @@ static void dpu_kms_commit(struct msm_kms *kms, struct drm_atomic_state *state) if (crtc->state->active) { trace_dpu_kms_commit(DRMID(crtc)); - dpu_crtc_commit_kickoff(crtc); + dpu_crtc_commit_kickoff(crtc, + state->legacy_cursor_update); } } } @@ -613,22 +576,7 @@ fail: #ifdef CONFIG_DEBUG_FS static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) { - struct dpu_kms *dpu_kms = to_dpu_kms(kms); - struct drm_device *dev; - int rc; - - if (!dpu_kms || !dpu_kms->dev || !dpu_kms->dev->dev) { - DPU_ERROR("invalid dpu_kms\n"); - return -EINVAL; - } - - dev = dpu_kms->dev; - - rc = _dpu_debugfs_init(dpu_kms); - if (rc) - DPU_ERROR("dpu_debugfs init failed: %d\n", rc); - - return rc; + return _dpu_debugfs_init(to_dpu_kms(kms)); } #endif @@ -651,12 +599,7 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms) dpu_hw_intr_destroy(dpu_kms->hw_intr); dpu_kms->hw_intr = NULL; - if (dpu_kms->power_event) - dpu_power_handle_unregister_event( - &dpu_kms->phandle, dpu_kms->power_event); - /* safe to call these more than once during shutdown */ - _dpu_debugfs_destroy(dpu_kms); _dpu_kms_mmu_destroy(dpu_kms); if (dpu_kms->catalog) { @@ -676,11 +619,6 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms) dpu_hw_catalog_deinit(dpu_kms->catalog); dpu_kms->catalog = NULL; - if (dpu_kms->core_client) - dpu_power_client_destroy(&dpu_kms->phandle, - dpu_kms->core_client); - dpu_kms->core_client = NULL; - if (dpu_kms->vbif[VBIF_NRT]) devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_NRT]); dpu_kms->vbif[VBIF_NRT] = NULL; @@ -705,131 +643,9 @@ static void dpu_kms_destroy(struct msm_kms *kms) dpu_kms = to_dpu_kms(kms); - dpu_dbg_destroy(); _dpu_kms_hw_destroy(dpu_kms); } -static int dpu_kms_pm_suspend(struct device *dev) -{ - struct drm_device *ddev; - struct drm_modeset_acquire_ctx ctx; - struct drm_atomic_state *state; - struct dpu_kms *dpu_kms; - int ret = 0, num_crtcs = 0; - - if (!dev) - return -EINVAL; - - ddev = dev_get_drvdata(dev); - if (!ddev || !ddev_to_msm_kms(ddev)) - return -EINVAL; - - dpu_kms = to_dpu_kms(ddev_to_msm_kms(ddev)); - - /* disable hot-plug polling */ - drm_kms_helper_poll_disable(ddev); - - /* acquire modeset lock(s) */ - drm_modeset_acquire_init(&ctx, 0); - -retry: - DPU_ATRACE_BEGIN("kms_pm_suspend"); - - ret = drm_modeset_lock_all_ctx(ddev, &ctx); - if (ret) - goto unlock; - - /* save current state for resume */ - if (dpu_kms->suspend_state) - drm_atomic_state_put(dpu_kms->suspend_state); - dpu_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx); - if (IS_ERR_OR_NULL(dpu_kms->suspend_state)) { - DRM_ERROR("failed to back up suspend state\n"); - dpu_kms->suspend_state = NULL; - goto unlock; - } - - /* create atomic state to disable all CRTCs */ - state = drm_atomic_state_alloc(ddev); - if (IS_ERR_OR_NULL(state)) { - DRM_ERROR("failed to allocate crtc disable state\n"); - goto unlock; - } - - state->acquire_ctx = &ctx; - - /* check for nothing to do */ - if (num_crtcs == 0) { - DRM_DEBUG("all crtcs are already in the off state\n"); - drm_atomic_state_put(state); - goto suspended; - } - - /* commit the "disable all" state */ - ret = drm_atomic_commit(state); - if (ret < 0) { - DRM_ERROR("failed to disable crtcs, %d\n", ret); - drm_atomic_state_put(state); - goto unlock; - } - -suspended: - dpu_kms->suspend_block = true; - -unlock: - if (ret == -EDEADLK) { - drm_modeset_backoff(&ctx); - goto retry; - } - drm_modeset_drop_locks(&ctx); - drm_modeset_acquire_fini(&ctx); - - DPU_ATRACE_END("kms_pm_suspend"); - return 0; -} - -static int dpu_kms_pm_resume(struct device *dev) -{ - struct drm_device *ddev; - struct dpu_kms *dpu_kms; - int ret; - - if (!dev) - return -EINVAL; - - ddev = dev_get_drvdata(dev); - if (!ddev || !ddev_to_msm_kms(ddev)) - return -EINVAL; - - dpu_kms = to_dpu_kms(ddev_to_msm_kms(ddev)); - - DPU_ATRACE_BEGIN("kms_pm_resume"); - - drm_mode_config_reset(ddev); - - drm_modeset_lock_all(ddev); - - dpu_kms->suspend_block = false; - - if (dpu_kms->suspend_state) { - dpu_kms->suspend_state->acquire_ctx = - ddev->mode_config.acquire_ctx; - ret = drm_atomic_commit(dpu_kms->suspend_state); - if (ret < 0) { - DRM_ERROR("failed to restore state, %d\n", ret); - drm_atomic_state_put(dpu_kms->suspend_state); - } - dpu_kms->suspend_state = NULL; - } - drm_modeset_unlock_all(ddev); - - /* enable hot-plug polling */ - drm_kms_helper_poll_enable(ddev); - - DPU_ATRACE_END("kms_pm_resume"); - return 0; -} - static void _dpu_kms_set_encoder_mode(struct msm_kms *kms, struct drm_encoder *encoder, bool cmd_mode) @@ -858,10 +674,30 @@ static void _dpu_kms_set_encoder_mode(struct msm_kms *kms, encoder->base.id, rc); } +static irqreturn_t dpu_irq(struct msm_kms *kms) +{ + struct dpu_kms *dpu_kms = to_dpu_kms(kms); + + return dpu_core_irq(dpu_kms); +} + +static void dpu_irq_preinstall(struct msm_kms *kms) +{ + struct dpu_kms *dpu_kms = to_dpu_kms(kms); + + dpu_core_irq_preinstall(dpu_kms); +} + +static void dpu_irq_uninstall(struct msm_kms *kms) +{ + struct dpu_kms *dpu_kms = to_dpu_kms(kms); + + dpu_core_irq_uninstall(dpu_kms); +} + static const struct msm_kms_funcs kms_funcs = { .hw_init = dpu_kms_hw_init, .irq_preinstall = dpu_irq_preinstall, - .irq_postinstall = dpu_irq_postinstall, .irq_uninstall = dpu_irq_uninstall, .irq = dpu_irq, .prepare_commit = dpu_kms_prepare_commit, @@ -873,8 +709,6 @@ static const struct msm_kms_funcs kms_funcs = { .check_modified_format = dpu_format_check_modified_format, .get_format = dpu_get_msm_format, .round_pixclk = dpu_kms_round_pixclk, - .pm_suspend = dpu_kms_pm_suspend, - .pm_resume = dpu_kms_pm_resume, .destroy = dpu_kms_destroy, .set_encoder_mode = _dpu_kms_set_encoder_mode, #ifdef CONFIG_DEBUG_FS @@ -882,12 +716,6 @@ static const struct msm_kms_funcs kms_funcs = { #endif }; -/* the caller api needs to turn on clock before calling it */ -static inline void _dpu_kms_core_hw_rev_init(struct dpu_kms *dpu_kms) -{ - dpu_kms->core_rev = readl_relaxed(dpu_kms->mmio + 0x0); -} - static int _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms) { struct msm_mmu *mmu; @@ -911,6 +739,9 @@ static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms) if (!domain) return 0; + domain->geometry.aperture_start = 0x1000; + domain->geometry.aperture_end = 0xffffffff; + aspace = msm_gem_address_space_create(dpu_kms->dev->dev, domain, "dpu1"); if (IS_ERR(aspace)) { @@ -960,16 +791,6 @@ u64 dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name) return clk_get_rate(clk->clk); } -static void dpu_kms_handle_power_event(u32 event_type, void *usr) -{ - struct dpu_kms *dpu_kms = usr; - - if (!dpu_kms) - return; - - dpu_vbif_init_memtypes(dpu_kms); -} - static int dpu_kms_hw_init(struct msm_kms *kms) { struct dpu_kms *dpu_kms; @@ -979,26 +800,20 @@ static int dpu_kms_hw_init(struct msm_kms *kms) if (!kms) { DPU_ERROR("invalid kms\n"); - goto end; + return rc; } dpu_kms = to_dpu_kms(kms); dev = dpu_kms->dev; if (!dev) { DPU_ERROR("invalid device\n"); - goto end; - } - - rc = dpu_dbg_init(&dpu_kms->pdev->dev); - if (rc) { - DRM_ERROR("failed to init dpu dbg: %d\n", rc); - goto end; + return rc; } priv = dev->dev_private; if (!priv) { DPU_ERROR("invalid private data\n"); - goto dbg_destroy; + return rc; } dpu_kms->mmio = msm_ioremap(dpu_kms->pdev, "mdp", "mdp"); @@ -1036,20 +851,9 @@ static int dpu_kms_hw_init(struct msm_kms *kms) dpu_kms->reg_dma_len = dpu_iomap_size(dpu_kms->pdev, "regdma"); } - dpu_kms->core_client = dpu_power_client_create(&dpu_kms->phandle, - "core"); - if (IS_ERR_OR_NULL(dpu_kms->core_client)) { - rc = PTR_ERR(dpu_kms->core_client); - if (!dpu_kms->core_client) - rc = -EINVAL; - DPU_ERROR("dpu power client create failed: %d\n", rc); - dpu_kms->core_client = NULL; - goto error; - } - pm_runtime_get_sync(&dpu_kms->pdev->dev); - _dpu_kms_core_hw_rev_init(dpu_kms); + dpu_kms->core_rev = readl_relaxed(dpu_kms->mmio + 0x0); pr_info("dpu hardware revision:0x%x\n", dpu_kms->core_rev); @@ -1063,8 +867,6 @@ static int dpu_kms_hw_init(struct msm_kms *kms) goto power_error; } - dpu_dbg_init_dbg_buses(dpu_kms->core_rev); - /* * Now we need to read the HW catalog and initialize resources such as * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc @@ -1110,7 +912,6 @@ static int dpu_kms_hw_init(struct msm_kms *kms) } rc = dpu_core_perf_init(&dpu_kms->perf, dev, dpu_kms->catalog, - &dpu_kms->phandle, _dpu_kms_get_clk(dpu_kms, "core")); if (rc) { DPU_ERROR("failed to init perf %d\n", rc); @@ -1151,13 +952,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms) */ dev->mode_config.allow_fb_modifiers = true; - /* - * Handle (re)initializations during power enable - */ - dpu_kms_handle_power_event(DPU_POWER_EVENT_ENABLE, dpu_kms); - dpu_kms->power_event = dpu_power_handle_register_event( - &dpu_kms->phandle, DPU_POWER_EVENT_ENABLE, - dpu_kms_handle_power_event, dpu_kms, "kms"); + dpu_vbif_init_memtypes(dpu_kms); pm_runtime_put_sync(&dpu_kms->pdev->dev); @@ -1171,9 +966,7 @@ power_error: pm_runtime_put_sync(&dpu_kms->pdev->dev); error: _dpu_kms_hw_destroy(dpu_kms); -dbg_destroy: - dpu_dbg_destroy(); -end: + return rc; } @@ -1221,8 +1014,6 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) return ret; } - dpu_power_resource_init(pdev, &dpu_kms->phandle); - platform_set_drvdata(pdev, dpu_kms); msm_kms_init(&dpu_kms->base, &kms_funcs); @@ -1242,7 +1033,6 @@ static void dpu_unbind(struct device *dev, struct device *master, void *data) struct dpu_kms *dpu_kms = platform_get_drvdata(pdev); struct dss_module_power *mp = &dpu_kms->mp; - dpu_power_resource_deinit(pdev, &dpu_kms->phandle); msm_dss_put_clk(mp->clk_config, mp->num_clk); devm_kfree(&pdev->dev, mp->clk_config); mp->num_clk = 0; @@ -1278,19 +1068,13 @@ static int __maybe_unused dpu_runtime_suspend(struct device *dev) ddev = dpu_kms->dev; if (!ddev) { DPU_ERROR("invalid drm_device\n"); - goto exit; + return rc; } - rc = dpu_power_resource_enable(&dpu_kms->phandle, - dpu_kms->core_client, false); - if (rc) - DPU_ERROR("resource disable failed: %d\n", rc); - rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false); if (rc) DPU_ERROR("clock disable failed rc:%d\n", rc); -exit: return rc; } @@ -1299,27 +1083,27 @@ static int __maybe_unused dpu_runtime_resume(struct device *dev) int rc = -1; struct platform_device *pdev = to_platform_device(dev); struct dpu_kms *dpu_kms = platform_get_drvdata(pdev); + struct drm_encoder *encoder; struct drm_device *ddev; struct dss_module_power *mp = &dpu_kms->mp; ddev = dpu_kms->dev; if (!ddev) { DPU_ERROR("invalid drm_device\n"); - goto exit; + return rc; } rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true); if (rc) { DPU_ERROR("clock enable failed rc:%d\n", rc); - goto exit; + return rc; } - rc = dpu_power_resource_enable(&dpu_kms->phandle, - dpu_kms->core_client, true); - if (rc) - DPU_ERROR("resource enable failed: %d\n", rc); + dpu_vbif_init_memtypes(dpu_kms); + + drm_for_each_encoder(encoder, ddev) + dpu_encoder_virt_runtime_resume(encoder); -exit: return rc; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index 66d466628e2b..ac75cfc267f4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -23,15 +23,13 @@ #include "msm_kms.h" #include "msm_mmu.h" #include "msm_gem.h" -#include "dpu_dbg.h" #include "dpu_hw_catalog.h" #include "dpu_hw_ctl.h" #include "dpu_hw_lm.h" #include "dpu_hw_interrupts.h" #include "dpu_hw_top.h" +#include "dpu_io_util.h" #include "dpu_rm.h" -#include "dpu_power_handle.h" -#include "dpu_irq.h" #include "dpu_core_perf.h" #define DRMID(x) ((x) ? (x)->base.id : -1) @@ -104,7 +102,6 @@ struct dpu_irq { atomic_t *enable_counts; atomic_t *irq_counts; spinlock_t cb_lock; - struct dentry *debugfs_file; }; struct dpu_kms { @@ -113,15 +110,6 @@ struct dpu_kms { int core_rev; struct dpu_mdss_cfg *catalog; - struct dpu_power_handle phandle; - struct dpu_power_client *core_client; - struct dpu_power_event *power_event; - - /* directory entry for debugfs */ - struct dentry *debugfs_root; - struct dentry *debugfs_danger; - struct dentry *debugfs_vbif; - /* io/register spaces: */ void __iomem *mmio, *vbif[VBIF_MAX], *reg_dma; unsigned long mmio_len, vbif_len[VBIF_MAX], reg_dma_len; @@ -135,10 +123,6 @@ struct dpu_kms { struct dpu_core_perf perf; - /* saved atomic state during system suspend */ - struct drm_atomic_state *suspend_state; - bool suspend_block; - struct dpu_rm rm; bool rm_init; @@ -164,33 +148,6 @@ struct vsync_info { ((struct msm_drm_private *)((D)->dev_private))->kms : NULL) /** - * dpu_kms_is_suspend_state - whether or not the system is pm suspended - * @dev: Pointer to drm device - * Return: Suspend status - */ -static inline bool dpu_kms_is_suspend_state(struct drm_device *dev) -{ - if (!ddev_to_msm_kms(dev)) - return false; - - return to_dpu_kms(ddev_to_msm_kms(dev))->suspend_state != NULL; -} - -/** - * dpu_kms_is_suspend_blocked - whether or not commits are blocked due to pm - * suspend status - * @dev: Pointer to drm device - * Return: True if commits should be rejected due to pm suspend - */ -static inline bool dpu_kms_is_suspend_blocked(struct drm_device *dev) -{ - if (!dpu_kms_is_suspend_state(dev)) - return false; - - return to_dpu_kms(ddev_to_msm_kms(dev))->suspend_block; -} - -/** * Debugfs functions - extra helper functions for debugfs support * * Main debugfs documentation is located at, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c index 2235ef8129f4..cb307a2abf06 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c @@ -9,6 +9,11 @@ #define HW_INTR_STATUS 0x0010 +struct dpu_irq_controller { + unsigned long enabled_mask; + struct irq_domain *domain; +}; + struct dpu_mdss { struct msm_mdss base; void __iomem *mmio; @@ -115,13 +120,12 @@ static int _dpu_mdss_irq_domain_add(struct dpu_mdss *dpu_mdss) return 0; } -static int _dpu_mdss_irq_domain_fini(struct dpu_mdss *dpu_mdss) +static void _dpu_mdss_irq_domain_fini(struct dpu_mdss *dpu_mdss) { if (dpu_mdss->irq_controller.domain) { irq_domain_remove(dpu_mdss->irq_controller.domain); dpu_mdss->irq_controller.domain = NULL; } - return 0; } static int dpu_mdss_enable(struct msm_mdss *mdss) { @@ -156,18 +160,16 @@ static void dpu_mdss_destroy(struct drm_device *dev) struct dpu_mdss *dpu_mdss = to_dpu_mdss(priv->mdss); struct dss_module_power *mp = &dpu_mdss->mp; + pm_runtime_suspend(dev->dev); + pm_runtime_disable(dev->dev); _dpu_mdss_irq_domain_fini(dpu_mdss); - free_irq(platform_get_irq(pdev, 0), dpu_mdss); - msm_dss_put_clk(mp->clk_config, mp->num_clk); devm_kfree(&pdev->dev, mp->clk_config); if (dpu_mdss->mmio) devm_iounmap(&pdev->dev, dpu_mdss->mmio); dpu_mdss->mmio = NULL; - - pm_runtime_disable(dev->dev); priv->mdss = NULL; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index f549daf30fe6..fd75870eb17f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -137,7 +137,7 @@ static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) * @src_wdith: width of source buffer * Return: fill level corresponding to the source buffer/format or 0 if error */ -static inline int _dpu_plane_calc_fill_level(struct drm_plane *plane, +static int _dpu_plane_calc_fill_level(struct drm_plane *plane, const struct dpu_format *fmt, u32 src_width) { struct dpu_plane *pdpu, *tmp; @@ -430,24 +430,14 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane) dpu_vbif_set_qos_remap(dpu_kms, &qos_params); } -/** - * _dpu_plane_get_aspace: gets the address space - */ -static inline struct msm_gem_address_space *_dpu_plane_get_aspace( - struct dpu_plane *pdpu) -{ - struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); - - return kms->base.aspace; -} - -static inline void _dpu_plane_set_scanout(struct drm_plane *plane, +static void _dpu_plane_set_scanout(struct drm_plane *plane, struct dpu_plane_state *pstate, struct dpu_hw_pipe_cfg *pipe_cfg, struct drm_framebuffer *fb) { struct dpu_plane *pdpu = to_dpu_plane(plane); - struct msm_gem_address_space *aspace = _dpu_plane_get_aspace(pdpu); + struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); + struct msm_gem_address_space *aspace = kms->base.aspace; int ret; ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout); @@ -525,7 +515,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, scale_cfg->enable = 1; } -static inline void _dpu_plane_setup_csc(struct dpu_plane *pdpu) +static void _dpu_plane_setup_csc(struct dpu_plane *pdpu) { static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = { { @@ -801,7 +791,7 @@ static int dpu_plane_prepare_fb(struct drm_plane *plane, struct drm_gem_object *obj; struct msm_gem_object *msm_obj; struct dma_fence *fence; - struct msm_gem_address_space *aspace = _dpu_plane_get_aspace(pdpu); + struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); int ret; if (!new_state->fb) @@ -810,7 +800,7 @@ static int dpu_plane_prepare_fb(struct drm_plane *plane, DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id); /* cache aspace */ - pstate->aspace = aspace; + pstate->aspace = kms->base.aspace; /* * TODO: Need to sort out the msm_framebuffer_prepare() call below so @@ -1179,8 +1169,6 @@ static void dpu_plane_destroy(struct drm_plane *plane) mutex_destroy(&pdpu->lock); - drm_plane_helper_disable(plane, NULL); - /* this will destroy the states as well */ drm_plane_cleanup(plane); @@ -1193,19 +1181,8 @@ static void dpu_plane_destroy(struct drm_plane *plane) static void dpu_plane_destroy_state(struct drm_plane *plane, struct drm_plane_state *state) { - struct dpu_plane_state *pstate; - - if (!plane || !state) { - DPU_ERROR("invalid arg(s), plane %d state %d\n", - plane != 0, state != 0); - return; - } - - pstate = to_dpu_plane_state(state); - __drm_atomic_helper_plane_destroy_state(state); - - kfree(pstate); + kfree(to_dpu_plane_state(state)); } static struct drm_plane_state * @@ -1275,26 +1252,12 @@ static ssize_t _dpu_plane_danger_read(struct file *file, char __user *buff, size_t count, loff_t *ppos) { struct dpu_kms *kms = file->private_data; - struct dpu_mdss_cfg *cfg = kms->catalog; - int len = 0; - char buf[40] = {'\0'}; - - if (!cfg) - return -ENODEV; - - if (*ppos) - return 0; /* the end */ + int len; + char buf[40]; - len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl); - if (len < 0 || len >= sizeof(buf)) - return 0; - - if ((count < sizeof(buf)) || copy_to_user(buff, buf, len)) - return -EFAULT; + len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl); - *ppos += len; /* increase offset */ - - return len; + return simple_read_from_buffer(buff, count, ppos, buf, len); } static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable) @@ -1324,23 +1287,12 @@ static ssize_t _dpu_plane_danger_write(struct file *file, const char __user *user_buf, size_t count, loff_t *ppos) { struct dpu_kms *kms = file->private_data; - struct dpu_mdss_cfg *cfg = kms->catalog; int disable_panic; - char buf[10]; - - if (!cfg) - return -EFAULT; - - if (count >= sizeof(buf)) - return -EFAULT; - - if (copy_from_user(buf, user_buf, count)) - return -EFAULT; - - buf[count] = 0; /* end of string */ + int ret; - if (kstrtoint(buf, 0, &disable_panic)) - return -EFAULT; + ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic); + if (ret) + return ret; if (disable_panic) { /* Disable panic signal for all active pipes */ @@ -1365,33 +1317,10 @@ static const struct file_operations dpu_plane_danger_enable = { static int _dpu_plane_init_debugfs(struct drm_plane *plane) { - struct dpu_plane *pdpu; - struct dpu_kms *kms; - struct msm_drm_private *priv; - const struct dpu_sspp_sub_blks *sblk = 0; - const struct dpu_sspp_cfg *cfg = 0; - - if (!plane || !plane->dev) { - DPU_ERROR("invalid arguments\n"); - return -EINVAL; - } - - priv = plane->dev->dev_private; - if (!priv || !priv->kms) { - DPU_ERROR("invalid KMS reference\n"); - return -EINVAL; - } - - kms = to_dpu_kms(priv->kms); - pdpu = to_dpu_plane(plane); - - if (pdpu && pdpu->pipe_hw) - cfg = pdpu->pipe_hw->cap; - if (cfg) - sblk = cfg->sblk; - - if (!sblk) - return 0; + struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_kms *kms = _dpu_plane_get_kms(plane); + const struct dpu_sspp_cfg *cfg = pdpu->pipe_hw->cap; + const struct dpu_sspp_sub_blks *sblk = cfg->sblk; /* create overall sub-directory for the pipe */ pdpu->debugfs_root = @@ -1462,25 +1391,11 @@ static int _dpu_plane_init_debugfs(struct drm_plane *plane) return 0; } - -static void _dpu_plane_destroy_debugfs(struct drm_plane *plane) -{ - struct dpu_plane *pdpu; - - if (!plane) - return; - pdpu = to_dpu_plane(plane); - - debugfs_remove_recursive(pdpu->debugfs_root); -} #else static int _dpu_plane_init_debugfs(struct drm_plane *plane) { return 0; } -static void _dpu_plane_destroy_debugfs(struct drm_plane *plane) -{ -} #endif static int dpu_plane_late_register(struct drm_plane *plane) @@ -1490,7 +1405,9 @@ static int dpu_plane_late_register(struct drm_plane *plane) static void dpu_plane_early_unregister(struct drm_plane *plane) { - _dpu_plane_destroy_debugfs(plane); + struct dpu_plane *pdpu = to_dpu_plane(plane); + + debugfs_remove_recursive(pdpu->debugfs_root); } static const struct drm_plane_funcs dpu_plane_funcs = { @@ -1539,7 +1456,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, if (!pdpu) { DPU_ERROR("[%u]failed to allocate local plane struct\n", pipe); ret = -ENOMEM; - goto exit; + return ERR_PTR(ret); } /* cache local stuff for later */ @@ -1625,6 +1542,5 @@ clean_sspp: dpu_hw_sspp_destroy(pdpu->pipe_hw); clean_plane: kfree(pdpu); -exit: return ERR_PTR(ret); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c deleted file mode 100644 index fc14116789f2..000000000000 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c +++ /dev/null @@ -1,240 +0,0 @@ -/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#define pr_fmt(fmt) "[drm:%s:%d]: " fmt, __func__, __LINE__ - -#include <linux/kernel.h> -#include <linux/of.h> -#include <linux/string.h> -#include <linux/of_address.h> -#include <linux/slab.h> -#include <linux/mutex.h> -#include <linux/of_platform.h> - -#include "dpu_power_handle.h" -#include "dpu_trace.h" - -static const char *data_bus_name[DPU_POWER_HANDLE_DBUS_ID_MAX] = { - [DPU_POWER_HANDLE_DBUS_ID_MNOC] = "qcom,dpu-data-bus", - [DPU_POWER_HANDLE_DBUS_ID_LLCC] = "qcom,dpu-llcc-bus", - [DPU_POWER_HANDLE_DBUS_ID_EBI] = "qcom,dpu-ebi-bus", -}; - -const char *dpu_power_handle_get_dbus_name(u32 bus_id) -{ - if (bus_id < DPU_POWER_HANDLE_DBUS_ID_MAX) - return data_bus_name[bus_id]; - - return NULL; -} - -static void dpu_power_event_trigger_locked(struct dpu_power_handle *phandle, - u32 event_type) -{ - struct dpu_power_event *event; - - list_for_each_entry(event, &phandle->event_list, list) { - if (event->event_type & event_type) - event->cb_fnc(event_type, event->usr); - } -} - -struct dpu_power_client *dpu_power_client_create( - struct dpu_power_handle *phandle, char *client_name) -{ - struct dpu_power_client *client; - static u32 id; - - if (!client_name || !phandle) { - pr_err("client name is null or invalid power data\n"); - return ERR_PTR(-EINVAL); - } - - client = kzalloc(sizeof(struct dpu_power_client), GFP_KERNEL); - if (!client) - return ERR_PTR(-ENOMEM); - - mutex_lock(&phandle->phandle_lock); - strlcpy(client->name, client_name, MAX_CLIENT_NAME_LEN); - client->usecase_ndx = VOTE_INDEX_DISABLE; - client->id = id; - client->active = true; - pr_debug("client %s created:%pK id :%d\n", client_name, - client, id); - id++; - list_add(&client->list, &phandle->power_client_clist); - mutex_unlock(&phandle->phandle_lock); - - return client; -} - -void dpu_power_client_destroy(struct dpu_power_handle *phandle, - struct dpu_power_client *client) -{ - if (!client || !phandle) { - pr_err("reg bus vote: invalid client handle\n"); - } else if (!client->active) { - pr_err("dpu power deinit already done\n"); - kfree(client); - } else { - pr_debug("bus vote client %s destroyed:%pK id:%u\n", - client->name, client, client->id); - mutex_lock(&phandle->phandle_lock); - list_del_init(&client->list); - mutex_unlock(&phandle->phandle_lock); - kfree(client); - } -} - -void dpu_power_resource_init(struct platform_device *pdev, - struct dpu_power_handle *phandle) -{ - phandle->dev = &pdev->dev; - - INIT_LIST_HEAD(&phandle->power_client_clist); - INIT_LIST_HEAD(&phandle->event_list); - - mutex_init(&phandle->phandle_lock); -} - -void dpu_power_resource_deinit(struct platform_device *pdev, - struct dpu_power_handle *phandle) -{ - struct dpu_power_client *curr_client, *next_client; - struct dpu_power_event *curr_event, *next_event; - - if (!phandle || !pdev) { - pr_err("invalid input param\n"); - return; - } - - mutex_lock(&phandle->phandle_lock); - list_for_each_entry_safe(curr_client, next_client, - &phandle->power_client_clist, list) { - pr_err("client:%s-%d still registered with refcount:%d\n", - curr_client->name, curr_client->id, - curr_client->refcount); - curr_client->active = false; - list_del(&curr_client->list); - } - - list_for_each_entry_safe(curr_event, next_event, - &phandle->event_list, list) { - pr_err("event:%d, client:%s still registered\n", - curr_event->event_type, - curr_event->client_name); - curr_event->active = false; - list_del(&curr_event->list); - } - mutex_unlock(&phandle->phandle_lock); -} - -int dpu_power_resource_enable(struct dpu_power_handle *phandle, - struct dpu_power_client *pclient, bool enable) -{ - bool changed = false; - u32 max_usecase_ndx = VOTE_INDEX_DISABLE, prev_usecase_ndx; - struct dpu_power_client *client; - u32 event_type; - - if (!phandle || !pclient) { - pr_err("invalid input argument\n"); - return -EINVAL; - } - - mutex_lock(&phandle->phandle_lock); - if (enable) - pclient->refcount++; - else if (pclient->refcount) - pclient->refcount--; - - if (pclient->refcount) - pclient->usecase_ndx = VOTE_INDEX_LOW; - else - pclient->usecase_ndx = VOTE_INDEX_DISABLE; - - list_for_each_entry(client, &phandle->power_client_clist, list) { - if (client->usecase_ndx < VOTE_INDEX_MAX && - client->usecase_ndx > max_usecase_ndx) - max_usecase_ndx = client->usecase_ndx; - } - - if (phandle->current_usecase_ndx != max_usecase_ndx) { - changed = true; - prev_usecase_ndx = phandle->current_usecase_ndx; - phandle->current_usecase_ndx = max_usecase_ndx; - } - - pr_debug("%pS: changed=%d current idx=%d request client %s id:%u enable:%d refcount:%d\n", - __builtin_return_address(0), changed, max_usecase_ndx, - pclient->name, pclient->id, enable, pclient->refcount); - - if (!changed) - goto end; - - event_type = enable ? DPU_POWER_EVENT_ENABLE : DPU_POWER_EVENT_DISABLE; - - dpu_power_event_trigger_locked(phandle, event_type); -end: - mutex_unlock(&phandle->phandle_lock); - return 0; -} - -struct dpu_power_event *dpu_power_handle_register_event( - struct dpu_power_handle *phandle, - u32 event_type, void (*cb_fnc)(u32 event_type, void *usr), - void *usr, char *client_name) -{ - struct dpu_power_event *event; - - if (!phandle) { - pr_err("invalid power handle\n"); - return ERR_PTR(-EINVAL); - } else if (!cb_fnc || !event_type) { - pr_err("no callback fnc or event type\n"); - return ERR_PTR(-EINVAL); - } - - event = kzalloc(sizeof(struct dpu_power_event), GFP_KERNEL); - if (!event) - return ERR_PTR(-ENOMEM); - - event->event_type = event_type; - event->cb_fnc = cb_fnc; - event->usr = usr; - strlcpy(event->client_name, client_name, MAX_CLIENT_NAME_LEN); - event->active = true; - - mutex_lock(&phandle->phandle_lock); - list_add(&event->list, &phandle->event_list); - mutex_unlock(&phandle->phandle_lock); - - return event; -} - -void dpu_power_handle_unregister_event( - struct dpu_power_handle *phandle, - struct dpu_power_event *event) -{ - if (!phandle || !event) { - pr_err("invalid phandle or event\n"); - } else if (!event->active) { - pr_err("power handle deinit already done\n"); - kfree(event); - } else { - mutex_lock(&phandle->phandle_lock); - list_del_init(&event->list); - mutex_unlock(&phandle->phandle_lock); - kfree(event); - } -} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h deleted file mode 100644 index a65b7a297f21..000000000000 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h +++ /dev/null @@ -1,217 +0,0 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _DPU_POWER_HANDLE_H_ -#define _DPU_POWER_HANDLE_H_ - -#define MAX_CLIENT_NAME_LEN 128 - -#define DPU_POWER_HANDLE_ENABLE_BUS_AB_QUOTA 0 -#define DPU_POWER_HANDLE_DISABLE_BUS_AB_QUOTA 0 -#define DPU_POWER_HANDLE_ENABLE_BUS_IB_QUOTA 1600000000 -#define DPU_POWER_HANDLE_DISABLE_BUS_IB_QUOTA 0 - -#include "dpu_io_util.h" - -/* events will be triggered on power handler enable/disable */ -#define DPU_POWER_EVENT_DISABLE BIT(0) -#define DPU_POWER_EVENT_ENABLE BIT(1) - -/** - * mdss_bus_vote_type: register bus vote type - * VOTE_INDEX_DISABLE: removes the client vote - * VOTE_INDEX_LOW: keeps the lowest vote for register bus - * VOTE_INDEX_MAX: invalid - */ -enum mdss_bus_vote_type { - VOTE_INDEX_DISABLE, - VOTE_INDEX_LOW, - VOTE_INDEX_MAX, -}; - -/** - * enum dpu_power_handle_data_bus_client - type of axi bus clients - * @DPU_POWER_HANDLE_DATA_BUS_CLIENT_RT: core real-time bus client - * @DPU_POWER_HANDLE_DATA_BUS_CLIENT_NRT: core non-real-time bus client - * @DPU_POWER_HANDLE_DATA_BUS_CLIENT_MAX: maximum number of bus client type - */ -enum dpu_power_handle_data_bus_client { - DPU_POWER_HANDLE_DATA_BUS_CLIENT_RT, - DPU_POWER_HANDLE_DATA_BUS_CLIENT_NRT, - DPU_POWER_HANDLE_DATA_BUS_CLIENT_MAX -}; - -/** - * enum DPU_POWER_HANDLE_DBUS_ID - data bus identifier - * @DPU_POWER_HANDLE_DBUS_ID_MNOC: DPU/MNOC data bus - * @DPU_POWER_HANDLE_DBUS_ID_LLCC: MNOC/LLCC data bus - * @DPU_POWER_HANDLE_DBUS_ID_EBI: LLCC/EBI data bus - */ -enum DPU_POWER_HANDLE_DBUS_ID { - DPU_POWER_HANDLE_DBUS_ID_MNOC, - DPU_POWER_HANDLE_DBUS_ID_LLCC, - DPU_POWER_HANDLE_DBUS_ID_EBI, - DPU_POWER_HANDLE_DBUS_ID_MAX, -}; - -/** - * struct dpu_power_client: stores the power client for dpu driver - * @name: name of the client - * @usecase_ndx: current regs bus vote type - * @refcount: current refcount if multiple modules are using same - * same client for enable/disable. Power module will - * aggregate the refcount and vote accordingly for this - * client. - * @id: assigned during create. helps for debugging. - * @list: list to attach power handle master list - * @ab: arbitrated bandwidth for each bus client - * @ib: instantaneous bandwidth for each bus client - * @active: inidcates the state of dpu power handle - */ -struct dpu_power_client { - char name[MAX_CLIENT_NAME_LEN]; - short usecase_ndx; - short refcount; - u32 id; - struct list_head list; - u64 ab[DPU_POWER_HANDLE_DATA_BUS_CLIENT_MAX]; - u64 ib[DPU_POWER_HANDLE_DATA_BUS_CLIENT_MAX]; - bool active; -}; - -/* - * struct dpu_power_event - local event registration structure - * @client_name: name of the client registering - * @cb_fnc: pointer to desired callback function - * @usr: user pointer to pass to callback event trigger - * @event: refer to DPU_POWER_HANDLE_EVENT_* - * @list: list to attach event master list - * @active: indicates the state of dpu power handle - */ -struct dpu_power_event { - char client_name[MAX_CLIENT_NAME_LEN]; - void (*cb_fnc)(u32 event_type, void *usr); - void *usr; - u32 event_type; - struct list_head list; - bool active; -}; - -/** - * struct dpu_power_handle: power handle main struct - * @client_clist: master list to store all clients - * @phandle_lock: lock to synchronize the enable/disable - * @dev: pointer to device structure - * @usecase_ndx: current usecase index - * @event_list: current power handle event list - */ -struct dpu_power_handle { - struct list_head power_client_clist; - struct mutex phandle_lock; - struct device *dev; - u32 current_usecase_ndx; - struct list_head event_list; -}; - -/** - * dpu_power_resource_init() - initializes the dpu power handle - * @pdev: platform device to search the power resources - * @pdata: power handle to store the power resources - */ -void dpu_power_resource_init(struct platform_device *pdev, - struct dpu_power_handle *pdata); - -/** - * dpu_power_resource_deinit() - release the dpu power handle - * @pdev: platform device for power resources - * @pdata: power handle containing the resources - * - * Return: error code. - */ -void dpu_power_resource_deinit(struct platform_device *pdev, - struct dpu_power_handle *pdata); - -/** - * dpu_power_client_create() - create the client on power handle - * @pdata: power handle containing the resources - * @client_name: new client name for registration - * - * Return: error code. - */ -struct dpu_power_client *dpu_power_client_create(struct dpu_power_handle *pdata, - char *client_name); - -/** - * dpu_power_client_destroy() - destroy the client on power handle - * @pdata: power handle containing the resources - * @client_name: new client name for registration - * - * Return: none - */ -void dpu_power_client_destroy(struct dpu_power_handle *phandle, - struct dpu_power_client *client); - -/** - * dpu_power_resource_enable() - enable/disable the power resources - * @pdata: power handle containing the resources - * @client: client information to enable/disable its vote - * @enable: boolean request for enable/disable - * - * Return: error code. - */ -int dpu_power_resource_enable(struct dpu_power_handle *pdata, - struct dpu_power_client *pclient, bool enable); - -/** - * dpu_power_data_bus_bandwidth_ctrl() - control data bus bandwidth enable - * @phandle: power handle containing the resources - * @client: client information to bandwidth control - * @enable: true to enable bandwidth for data base - * - * Return: none - */ -void dpu_power_data_bus_bandwidth_ctrl(struct dpu_power_handle *phandle, - struct dpu_power_client *pclient, int enable); - -/** - * dpu_power_handle_register_event - register a callback function for an event. - * Clients can register for multiple events with a single register. - * Any block with access to phandle can register for the event - * notification. - * @phandle: power handle containing the resources - * @event_type: event type to register; refer DPU_POWER_HANDLE_EVENT_* - * @cb_fnc: pointer to desired callback function - * @usr: user pointer to pass to callback on event trigger - * - * Return: event pointer if success, or error code otherwise - */ -struct dpu_power_event *dpu_power_handle_register_event( - struct dpu_power_handle *phandle, - u32 event_type, void (*cb_fnc)(u32 event_type, void *usr), - void *usr, char *client_name); -/** - * dpu_power_handle_unregister_event - unregister callback for event(s) - * @phandle: power handle containing the resources - * @event: event pointer returned after power handle register - */ -void dpu_power_handle_unregister_event(struct dpu_power_handle *phandle, - struct dpu_power_event *event); - -/** - * dpu_power_handle_get_dbus_name - get name of given data bus identifier - * @bus_id: data bus identifier - * Return: Pointer to name string if success; NULL otherwise - */ -const char *dpu_power_handle_get_dbus_name(u32 bus_id); - -#endif /* _DPU_POWER_HANDLE_H_ */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h index e12c4cefb742..c78b521ceda1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h @@ -99,27 +99,6 @@ TRACE_EVENT(dpu_perf_set_ot, __entry->vbif_idx) ) -TRACE_EVENT(dpu_perf_update_bus, - TP_PROTO(int client, unsigned long long ab_quota, - unsigned long long ib_quota), - TP_ARGS(client, ab_quota, ib_quota), - TP_STRUCT__entry( - __field(int, client) - __field(u64, ab_quota) - __field(u64, ib_quota) - ), - TP_fast_assign( - __entry->client = client; - __entry->ab_quota = ab_quota; - __entry->ib_quota = ib_quota; - ), - TP_printk("Request client:%d ab=%llu ib=%llu", - __entry->client, - __entry->ab_quota, - __entry->ib_quota) -) - - TRACE_EVENT(dpu_cmd_release_bw, TP_PROTO(u32 crtc_id), TP_ARGS(crtc_id), @@ -319,6 +298,10 @@ DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_wait_for_commit_done, TP_PROTO(uint32_t drm_id), TP_ARGS(drm_id) ); +DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_runtime_resume, + TP_PROTO(uint32_t drm_id), + TP_ARGS(drm_id) +); TRACE_EVENT(dpu_enc_enable, TP_PROTO(uint32_t drm_id, int hdisplay, int vdisplay), @@ -539,10 +522,6 @@ DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_cb, TP_PROTO(uint32_t drm_id, u32 event), TP_ARGS(drm_id, event) ); -DEFINE_EVENT(dpu_id_event_template, dpu_crtc_handle_power_event, - TP_PROTO(uint32_t drm_id, u32 event), - TP_ARGS(drm_id, event) -); DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_done, TP_PROTO(uint32_t drm_id, u32 event), TP_ARGS(drm_id, event) @@ -749,24 +728,17 @@ TRACE_EVENT(dpu_crtc_vblank_enable, __field( uint32_t, enc_id ) __field( bool, enable ) __field( bool, enabled ) - __field( bool, suspend ) - __field( bool, vblank_requested ) ), TP_fast_assign( __entry->drm_id = drm_id; __entry->enc_id = enc_id; __entry->enable = enable; __entry->enabled = crtc->enabled; - __entry->suspend = crtc->suspend; - __entry->vblank_requested = crtc->vblank_requested; ), - TP_printk("id:%u encoder:%u enable:%s state{enabled:%s suspend:%s " - "vblank_req:%s}", + TP_printk("id:%u encoder:%u enable:%s state{enabled:%s}", __entry->drm_id, __entry->enc_id, __entry->enable ? "true" : "false", - __entry->enabled ? "true" : "false", - __entry->suspend ? "true" : "false", - __entry->vblank_requested ? "true" : "false") + __entry->enabled ? "true" : "false") ); DECLARE_EVENT_CLASS(dpu_crtc_enable_template, @@ -776,25 +748,15 @@ DECLARE_EVENT_CLASS(dpu_crtc_enable_template, __field( uint32_t, drm_id ) __field( bool, enable ) __field( bool, enabled ) - __field( bool, suspend ) - __field( bool, vblank_requested ) ), TP_fast_assign( __entry->drm_id = drm_id; __entry->enable = enable; __entry->enabled = crtc->enabled; - __entry->suspend = crtc->suspend; - __entry->vblank_requested = crtc->vblank_requested; ), - TP_printk("id:%u enable:%s state{enabled:%s suspend:%s vblank_req:%s}", + TP_printk("id:%u enable:%s state{enabled:%s}", __entry->drm_id, __entry->enable ? "true" : "false", - __entry->enabled ? "true" : "false", - __entry->suspend ? "true" : "false", - __entry->vblank_requested ? "true" : "false") -); -DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_set_suspend, - TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), - TP_ARGS(drm_id, enable, crtc) + __entry->enabled ? "true" : "false") ); DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_enable, TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), @@ -1004,6 +966,53 @@ TRACE_EVENT(dpu_core_perf_update_clk, __entry->stop_req ? "true" : "false", __entry->clk_rate) ); +TRACE_EVENT(dpu_hw_ctl_update_pending_flush, + TP_PROTO(u32 new_bits, u32 pending_mask), + TP_ARGS(new_bits, pending_mask), + TP_STRUCT__entry( + __field( u32, new_bits ) + __field( u32, pending_mask ) + ), + TP_fast_assign( + __entry->new_bits = new_bits; + __entry->pending_mask = pending_mask; + ), + TP_printk("new=%x existing=%x", __entry->new_bits, + __entry->pending_mask) +); + +DECLARE_EVENT_CLASS(dpu_hw_ctl_pending_flush_template, + TP_PROTO(u32 pending_mask, u32 ctl_flush), + TP_ARGS(pending_mask, ctl_flush), + TP_STRUCT__entry( + __field( u32, pending_mask ) + __field( u32, ctl_flush ) + ), + TP_fast_assign( + __entry->pending_mask = pending_mask; + __entry->ctl_flush = ctl_flush; + ), + TP_printk("pending_mask=%x CTL_FLUSH=%x", __entry->pending_mask, + __entry->ctl_flush) +); +DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_clear_pending_flush, + TP_PROTO(u32 pending_mask, u32 ctl_flush), + TP_ARGS(pending_mask, ctl_flush) +); +DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, + dpu_hw_ctl_trigger_pending_flush, + TP_PROTO(u32 pending_mask, u32 ctl_flush), + TP_ARGS(pending_mask, ctl_flush) +); +DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_prepare, + TP_PROTO(u32 pending_mask, u32 ctl_flush), + TP_ARGS(pending_mask, ctl_flush) +); +DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_start, + TP_PROTO(u32 pending_mask, u32 ctl_flush), + TP_ARGS(pending_mask, ctl_flush) +); + #define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0) #define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1) #define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c index 295528292296..ef753ea9c499 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c @@ -191,7 +191,7 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms, ot_lim = _dpu_vbif_get_ot_limit(vbif, params) & 0xFF; if (ot_lim == 0) - goto exit; + return; trace_dpu_perf_set_ot(params->num, params->xin_id, ot_lim, params->vbif_idx); @@ -210,8 +210,6 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms, if (forced_on) mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, false); -exit: - return; } void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, @@ -312,31 +310,25 @@ void dpu_vbif_init_memtypes(struct dpu_kms *dpu_kms) } #ifdef CONFIG_DEBUG_FS -void dpu_debugfs_vbif_destroy(struct dpu_kms *dpu_kms) -{ - debugfs_remove_recursive(dpu_kms->debugfs_vbif); - dpu_kms->debugfs_vbif = NULL; -} -int dpu_debugfs_vbif_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root) +void dpu_debugfs_vbif_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root) { char vbif_name[32]; - struct dentry *debugfs_vbif; + struct dentry *entry, *debugfs_vbif; int i, j; - dpu_kms->debugfs_vbif = debugfs_create_dir("vbif", debugfs_root); - if (!dpu_kms->debugfs_vbif) { - DPU_ERROR("failed to create vbif debugfs\n"); - return -EINVAL; - } + entry = debugfs_create_dir("vbif", debugfs_root); + if (IS_ERR_OR_NULL(entry)) + return; for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { struct dpu_vbif_cfg *vbif = &dpu_kms->catalog->vbif[i]; snprintf(vbif_name, sizeof(vbif_name), "%d", vbif->id); - debugfs_vbif = debugfs_create_dir(vbif_name, - dpu_kms->debugfs_vbif); + debugfs_vbif = debugfs_create_dir(vbif_name, entry); + if (IS_ERR_OR_NULL(debugfs_vbif)) + continue; debugfs_create_u32("features", 0600, debugfs_vbif, (u32 *)&vbif->features); @@ -378,7 +370,5 @@ int dpu_debugfs_vbif_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root) (u32 *)&cfg->ot_limit); } } - - return 0; } #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h index f17af52dbbd5..6356876d7a66 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h @@ -78,17 +78,6 @@ void dpu_vbif_clear_errors(struct dpu_kms *dpu_kms); */ void dpu_vbif_init_memtypes(struct dpu_kms *dpu_kms); -#ifdef CONFIG_DEBUG_FS -int dpu_debugfs_vbif_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root); -void dpu_debugfs_vbif_destroy(struct dpu_kms *dpu_kms); -#else -static inline int dpu_debugfs_vbif_init(struct dpu_kms *dpu_kms, - struct dentry *debugfs_root) -{ - return 0; -} -static inline void dpu_debugfs_vbif_destroy(struct dpu_kms *dpu_kms) -{ -} -#endif +void dpu_debugfs_vbif_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root); + #endif /* __DPU_VBIF_H__ */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/msm_media_info.h b/drivers/gpu/drm/msm/disp/dpu1/msm_media_info.h index 4f12e5c534c8..9fc9dbde8a27 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/msm_media_info.h +++ b/drivers/gpu/drm/msm/disp/dpu1/msm_media_info.h @@ -813,18 +813,6 @@ enum color_fmts { #define COLOR_FMT_P010_UBWC COLOR_FMT_P010_UBWC #define COLOR_FMT_P010 COLOR_FMT_P010 -static inline unsigned int VENUS_EXTRADATA_SIZE(int width, int height) -{ - (void)height; - (void)width; - - /* - * In the future, calculate the size based on the w/h but just - * hardcode it for now since 16K satisfies all current usecases. - */ - return 16 * 1024; -} - /* * Function arguments: * @color_fmt @@ -832,38 +820,32 @@ static inline unsigned int VENUS_EXTRADATA_SIZE(int width, int height) * Progressive: width * Interlaced: width */ -static inline unsigned int VENUS_Y_STRIDE(int color_fmt, int width) +static unsigned int VENUS_Y_STRIDE(int color_fmt, int width) { - unsigned int alignment, stride = 0; + unsigned int stride = 0; if (!width) - goto invalid_input; + return 0; switch (color_fmt) { case COLOR_FMT_NV21: case COLOR_FMT_NV12: case COLOR_FMT_NV12_MVTB: case COLOR_FMT_NV12_UBWC: - alignment = 128; - stride = MSM_MEDIA_ALIGN(width, alignment); + stride = MSM_MEDIA_ALIGN(width, 128); break; case COLOR_FMT_NV12_BPP10_UBWC: - alignment = 256; stride = MSM_MEDIA_ALIGN(width, 192); - stride = MSM_MEDIA_ALIGN(stride * 4/3, alignment); + stride = MSM_MEDIA_ALIGN(stride * 4 / 3, 256); break; case COLOR_FMT_P010_UBWC: - alignment = 256; - stride = MSM_MEDIA_ALIGN(width * 2, alignment); + stride = MSM_MEDIA_ALIGN(width * 2, 256); break; case COLOR_FMT_P010: - alignment = 128; - stride = MSM_MEDIA_ALIGN(width*2, alignment); - break; - default: + stride = MSM_MEDIA_ALIGN(width * 2, 128); break; } -invalid_input: + return stride; } @@ -874,38 +856,32 @@ invalid_input: * Progressive: width * Interlaced: width */ -static inline unsigned int VENUS_UV_STRIDE(int color_fmt, int width) +static unsigned int VENUS_UV_STRIDE(int color_fmt, int width) { - unsigned int alignment, stride = 0; + unsigned int stride = 0; if (!width) - goto invalid_input; + return 0; switch (color_fmt) { case COLOR_FMT_NV21: case COLOR_FMT_NV12: case COLOR_FMT_NV12_MVTB: case COLOR_FMT_NV12_UBWC: - alignment = 128; - stride = MSM_MEDIA_ALIGN(width, alignment); + stride = MSM_MEDIA_ALIGN(width, 128); break; case COLOR_FMT_NV12_BPP10_UBWC: - alignment = 256; stride = MSM_MEDIA_ALIGN(width, 192); - stride = MSM_MEDIA_ALIGN(stride * 4/3, alignment); + stride = MSM_MEDIA_ALIGN(stride * 4 / 3, 256); break; case COLOR_FMT_P010_UBWC: - alignment = 256; - stride = MSM_MEDIA_ALIGN(width * 2, alignment); + stride = MSM_MEDIA_ALIGN(width * 2, 256); break; case COLOR_FMT_P010: - alignment = 128; - stride = MSM_MEDIA_ALIGN(width*2, alignment); - break; - default: + stride = MSM_MEDIA_ALIGN(width * 2, 128); break; } -invalid_input: + return stride; } @@ -916,12 +892,12 @@ invalid_input: * Progressive: height * Interlaced: (height+1)>>1 */ -static inline unsigned int VENUS_Y_SCANLINES(int color_fmt, int height) +static unsigned int VENUS_Y_SCANLINES(int color_fmt, int height) { - unsigned int alignment, sclines = 0; + unsigned int sclines = 0; if (!height) - goto invalid_input; + return 0; switch (color_fmt) { case COLOR_FMT_NV21: @@ -929,17 +905,14 @@ static inline unsigned int VENUS_Y_SCANLINES(int color_fmt, int height) case COLOR_FMT_NV12_MVTB: case COLOR_FMT_NV12_UBWC: case COLOR_FMT_P010: - alignment = 32; + sclines = MSM_MEDIA_ALIGN(height, 32); break; case COLOR_FMT_NV12_BPP10_UBWC: case COLOR_FMT_P010_UBWC: - alignment = 16; + sclines = MSM_MEDIA_ALIGN(height, 16); break; - default: - return 0; } - sclines = MSM_MEDIA_ALIGN(height, alignment); -invalid_input: + return sclines; } @@ -950,12 +923,12 @@ invalid_input: * Progressive: height * Interlaced: (height+1)>>1 */ -static inline unsigned int VENUS_UV_SCANLINES(int color_fmt, int height) +static unsigned int VENUS_UV_SCANLINES(int color_fmt, int height) { - unsigned int alignment, sclines = 0; + unsigned int sclines = 0; if (!height) - goto invalid_input; + return 0; switch (color_fmt) { case COLOR_FMT_NV21: @@ -964,18 +937,13 @@ static inline unsigned int VENUS_UV_SCANLINES(int color_fmt, int height) case COLOR_FMT_NV12_BPP10_UBWC: case COLOR_FMT_P010_UBWC: case COLOR_FMT_P010: - alignment = 16; + sclines = MSM_MEDIA_ALIGN((height + 1) >> 1, 16); break; case COLOR_FMT_NV12_UBWC: - alignment = 32; + sclines = MSM_MEDIA_ALIGN((height + 1) >> 1, 32); break; - default: - goto invalid_input; } - sclines = MSM_MEDIA_ALIGN((height+1)>>1, alignment); - -invalid_input: return sclines; } @@ -986,12 +954,12 @@ invalid_input: * Progressive: width * Interlaced: width */ -static inline unsigned int VENUS_Y_META_STRIDE(int color_fmt, int width) +static unsigned int VENUS_Y_META_STRIDE(int color_fmt, int width) { - int y_tile_width = 0, y_meta_stride = 0; + int y_tile_width = 0, y_meta_stride; if (!width) - goto invalid_input; + return 0; switch (color_fmt) { case COLOR_FMT_NV12_UBWC: @@ -1002,14 +970,11 @@ static inline unsigned int VENUS_Y_META_STRIDE(int color_fmt, int width) y_tile_width = 48; break; default: - goto invalid_input; + return 0; } y_meta_stride = MSM_MEDIA_ROUNDUP(width, y_tile_width); - y_meta_stride = MSM_MEDIA_ALIGN(y_meta_stride, 64); - -invalid_input: - return y_meta_stride; + return MSM_MEDIA_ALIGN(y_meta_stride, 64); } /* @@ -1019,12 +984,12 @@ invalid_input: * Progressive: height * Interlaced: (height+1)>>1 */ -static inline unsigned int VENUS_Y_META_SCANLINES(int color_fmt, int height) +static unsigned int VENUS_Y_META_SCANLINES(int color_fmt, int height) { - int y_tile_height = 0, y_meta_scanlines = 0; + int y_tile_height = 0, y_meta_scanlines; if (!height) - goto invalid_input; + return 0; switch (color_fmt) { case COLOR_FMT_NV12_UBWC: @@ -1035,14 +1000,11 @@ static inline unsigned int VENUS_Y_META_SCANLINES(int color_fmt, int height) y_tile_height = 4; break; default: - goto invalid_input; + return 0; } y_meta_scanlines = MSM_MEDIA_ROUNDUP(height, y_tile_height); - y_meta_scanlines = MSM_MEDIA_ALIGN(y_meta_scanlines, 16); - -invalid_input: - return y_meta_scanlines; + return MSM_MEDIA_ALIGN(y_meta_scanlines, 16); } /* @@ -1052,12 +1014,12 @@ invalid_input: * Progressive: width * Interlaced: width */ -static inline unsigned int VENUS_UV_META_STRIDE(int color_fmt, int width) +static unsigned int VENUS_UV_META_STRIDE(int color_fmt, int width) { - int uv_tile_width = 0, uv_meta_stride = 0; + int uv_tile_width = 0, uv_meta_stride; if (!width) - goto invalid_input; + return 0; switch (color_fmt) { case COLOR_FMT_NV12_UBWC: @@ -1068,14 +1030,11 @@ static inline unsigned int VENUS_UV_META_STRIDE(int color_fmt, int width) uv_tile_width = 24; break; default: - goto invalid_input; + return 0; } uv_meta_stride = MSM_MEDIA_ROUNDUP((width+1)>>1, uv_tile_width); - uv_meta_stride = MSM_MEDIA_ALIGN(uv_meta_stride, 64); - -invalid_input: - return uv_meta_stride; + return MSM_MEDIA_ALIGN(uv_meta_stride, 64); } /* @@ -1085,12 +1044,12 @@ invalid_input: * Progressive: height * Interlaced: (height+1)>>1 */ -static inline unsigned int VENUS_UV_META_SCANLINES(int color_fmt, int height) +static unsigned int VENUS_UV_META_SCANLINES(int color_fmt, int height) { - int uv_tile_height = 0, uv_meta_scanlines = 0; + int uv_tile_height = 0, uv_meta_scanlines; if (!height) - goto invalid_input; + return 0; switch (color_fmt) { case COLOR_FMT_NV12_UBWC: @@ -1101,22 +1060,19 @@ static inline unsigned int VENUS_UV_META_SCANLINES(int color_fmt, int height) uv_tile_height = 4; break; default: - goto invalid_input; + return 0; } uv_meta_scanlines = MSM_MEDIA_ROUNDUP((height+1)>>1, uv_tile_height); - uv_meta_scanlines = MSM_MEDIA_ALIGN(uv_meta_scanlines, 16); - -invalid_input: - return uv_meta_scanlines; + return MSM_MEDIA_ALIGN(uv_meta_scanlines, 16); } -static inline unsigned int VENUS_RGB_STRIDE(int color_fmt, int width) +static unsigned int VENUS_RGB_STRIDE(int color_fmt, int width) { - unsigned int alignment = 0, stride = 0, bpp = 4; + unsigned int alignment = 0, bpp = 4; if (!width) - goto invalid_input; + return 0; switch (color_fmt) { case COLOR_FMT_RGBA8888: @@ -1131,21 +1087,18 @@ static inline unsigned int VENUS_RGB_STRIDE(int color_fmt, int width) alignment = 256; break; default: - goto invalid_input; + return 0; } - stride = MSM_MEDIA_ALIGN(width * bpp, alignment); - -invalid_input: - return stride; + return MSM_MEDIA_ALIGN(width * bpp, alignment); } -static inline unsigned int VENUS_RGB_SCANLINES(int color_fmt, int height) +static unsigned int VENUS_RGB_SCANLINES(int color_fmt, int height) { - unsigned int alignment = 0, scanlines = 0; + unsigned int alignment = 0; if (!height) - goto invalid_input; + return 0; switch (color_fmt) { case COLOR_FMT_RGBA8888: @@ -1157,220 +1110,46 @@ static inline unsigned int VENUS_RGB_SCANLINES(int color_fmt, int height) alignment = 16; break; default: - goto invalid_input; + return 0; } - scanlines = MSM_MEDIA_ALIGN(height, alignment); - -invalid_input: - return scanlines; + return MSM_MEDIA_ALIGN(height, alignment); } -static inline unsigned int VENUS_RGB_META_STRIDE(int color_fmt, int width) +static unsigned int VENUS_RGB_META_STRIDE(int color_fmt, int width) { - int rgb_tile_width = 0, rgb_meta_stride = 0; + int rgb_meta_stride; if (!width) - goto invalid_input; + return 0; switch (color_fmt) { case COLOR_FMT_RGBA8888_UBWC: case COLOR_FMT_RGBA1010102_UBWC: case COLOR_FMT_RGB565_UBWC: - rgb_tile_width = 16; - break; - default: - goto invalid_input; + rgb_meta_stride = MSM_MEDIA_ROUNDUP(width, 16); + return MSM_MEDIA_ALIGN(rgb_meta_stride, 64); } - rgb_meta_stride = MSM_MEDIA_ROUNDUP(width, rgb_tile_width); - rgb_meta_stride = MSM_MEDIA_ALIGN(rgb_meta_stride, 64); - -invalid_input: - return rgb_meta_stride; + return 0; } -static inline unsigned int VENUS_RGB_META_SCANLINES(int color_fmt, int height) +static unsigned int VENUS_RGB_META_SCANLINES(int color_fmt, int height) { - int rgb_tile_height = 0, rgb_meta_scanlines = 0; + int rgb_meta_scanlines; if (!height) - goto invalid_input; + return 0; switch (color_fmt) { case COLOR_FMT_RGBA8888_UBWC: case COLOR_FMT_RGBA1010102_UBWC: case COLOR_FMT_RGB565_UBWC: - rgb_tile_height = 4; - break; - default: - goto invalid_input; + rgb_meta_scanlines = MSM_MEDIA_ROUNDUP(height, 4); + return MSM_MEDIA_ALIGN(rgb_meta_scanlines, 16); } - rgb_meta_scanlines = MSM_MEDIA_ROUNDUP(height, rgb_tile_height); - rgb_meta_scanlines = MSM_MEDIA_ALIGN(rgb_meta_scanlines, 16); - -invalid_input: - return rgb_meta_scanlines; -} - -/* - * Function arguments: - * @color_fmt - * @width - * Progressive: width - * Interlaced: width - * @height - * Progressive: height - * Interlaced: height - */ -static inline unsigned int VENUS_BUFFER_SIZE( - int color_fmt, int width, int height) -{ - const unsigned int extra_size = VENUS_EXTRADATA_SIZE(width, height); - unsigned int uv_alignment = 0, size = 0; - unsigned int y_plane, uv_plane, y_stride, - uv_stride, y_sclines, uv_sclines; - unsigned int y_ubwc_plane = 0, uv_ubwc_plane = 0; - unsigned int y_meta_stride = 0, y_meta_scanlines = 0; - unsigned int uv_meta_stride = 0, uv_meta_scanlines = 0; - unsigned int y_meta_plane = 0, uv_meta_plane = 0; - unsigned int rgb_stride = 0, rgb_scanlines = 0; - unsigned int rgb_plane = 0, rgb_ubwc_plane = 0, rgb_meta_plane = 0; - unsigned int rgb_meta_stride = 0, rgb_meta_scanlines = 0; - - if (!width || !height) - goto invalid_input; - - y_stride = VENUS_Y_STRIDE(color_fmt, width); - uv_stride = VENUS_UV_STRIDE(color_fmt, width); - y_sclines = VENUS_Y_SCANLINES(color_fmt, height); - uv_sclines = VENUS_UV_SCANLINES(color_fmt, height); - rgb_stride = VENUS_RGB_STRIDE(color_fmt, width); - rgb_scanlines = VENUS_RGB_SCANLINES(color_fmt, height); - - switch (color_fmt) { - case COLOR_FMT_NV21: - case COLOR_FMT_NV12: - case COLOR_FMT_P010: - uv_alignment = 4096; - y_plane = y_stride * y_sclines; - uv_plane = uv_stride * uv_sclines + uv_alignment; - size = y_plane + uv_plane + - MSM_MEDIA_MAX(extra_size, 8 * y_stride); - size = MSM_MEDIA_ALIGN(size, 4096); - break; - case COLOR_FMT_NV12_MVTB: - uv_alignment = 4096; - y_plane = y_stride * y_sclines; - uv_plane = uv_stride * uv_sclines + uv_alignment; - size = y_plane + uv_plane; - size = 2 * size + extra_size; - size = MSM_MEDIA_ALIGN(size, 4096); - break; - case COLOR_FMT_NV12_UBWC: - y_sclines = VENUS_Y_SCANLINES(color_fmt, (height+1)>>1); - y_ubwc_plane = MSM_MEDIA_ALIGN(y_stride * y_sclines, 4096); - uv_sclines = VENUS_UV_SCANLINES(color_fmt, (height+1)>>1); - uv_ubwc_plane = MSM_MEDIA_ALIGN(uv_stride * uv_sclines, 4096); - y_meta_stride = VENUS_Y_META_STRIDE(color_fmt, width); - y_meta_scanlines = - VENUS_Y_META_SCANLINES(color_fmt, (height+1)>>1); - y_meta_plane = MSM_MEDIA_ALIGN( - y_meta_stride * y_meta_scanlines, 4096); - uv_meta_stride = VENUS_UV_META_STRIDE(color_fmt, width); - uv_meta_scanlines = - VENUS_UV_META_SCANLINES(color_fmt, (height+1)>>1); - uv_meta_plane = MSM_MEDIA_ALIGN(uv_meta_stride * - uv_meta_scanlines, 4096); - - size = (y_ubwc_plane + uv_ubwc_plane + y_meta_plane + - uv_meta_plane)*2 + - MSM_MEDIA_MAX(extra_size + 8192, 48 * y_stride); - size = MSM_MEDIA_ALIGN(size, 4096); - break; - case COLOR_FMT_NV12_BPP10_UBWC: - y_ubwc_plane = MSM_MEDIA_ALIGN(y_stride * y_sclines, 4096); - uv_ubwc_plane = MSM_MEDIA_ALIGN(uv_stride * uv_sclines, 4096); - y_meta_stride = VENUS_Y_META_STRIDE(color_fmt, width); - y_meta_scanlines = VENUS_Y_META_SCANLINES(color_fmt, height); - y_meta_plane = MSM_MEDIA_ALIGN( - y_meta_stride * y_meta_scanlines, 4096); - uv_meta_stride = VENUS_UV_META_STRIDE(color_fmt, width); - uv_meta_scanlines = VENUS_UV_META_SCANLINES(color_fmt, height); - uv_meta_plane = MSM_MEDIA_ALIGN(uv_meta_stride * - uv_meta_scanlines, 4096); - - size = y_ubwc_plane + uv_ubwc_plane + y_meta_plane + - uv_meta_plane + - MSM_MEDIA_MAX(extra_size + 8192, 48 * y_stride); - size = MSM_MEDIA_ALIGN(size, 4096); - break; - case COLOR_FMT_P010_UBWC: - y_ubwc_plane = MSM_MEDIA_ALIGN(y_stride * y_sclines, 4096); - uv_ubwc_plane = MSM_MEDIA_ALIGN(uv_stride * uv_sclines, 4096); - y_meta_stride = VENUS_Y_META_STRIDE(color_fmt, width); - y_meta_scanlines = VENUS_Y_META_SCANLINES(color_fmt, height); - y_meta_plane = MSM_MEDIA_ALIGN( - y_meta_stride * y_meta_scanlines, 4096); - uv_meta_stride = VENUS_UV_META_STRIDE(color_fmt, width); - uv_meta_scanlines = VENUS_UV_META_SCANLINES(color_fmt, height); - uv_meta_plane = MSM_MEDIA_ALIGN(uv_meta_stride * - uv_meta_scanlines, 4096); - - size = y_ubwc_plane + uv_ubwc_plane + y_meta_plane + - uv_meta_plane; - size = MSM_MEDIA_ALIGN(size, 4096); - break; - case COLOR_FMT_RGBA8888: - rgb_plane = MSM_MEDIA_ALIGN(rgb_stride * rgb_scanlines, 4096); - size = rgb_plane; - size = MSM_MEDIA_ALIGN(size, 4096); - break; - case COLOR_FMT_RGBA8888_UBWC: - case COLOR_FMT_RGBA1010102_UBWC: - case COLOR_FMT_RGB565_UBWC: - rgb_ubwc_plane = MSM_MEDIA_ALIGN(rgb_stride * rgb_scanlines, - 4096); - rgb_meta_stride = VENUS_RGB_META_STRIDE(color_fmt, width); - rgb_meta_scanlines = VENUS_RGB_META_SCANLINES(color_fmt, - height); - rgb_meta_plane = MSM_MEDIA_ALIGN(rgb_meta_stride * - rgb_meta_scanlines, 4096); - size = rgb_ubwc_plane + rgb_meta_plane; - size = MSM_MEDIA_ALIGN(size, 4096); - break; - default: - break; - } -invalid_input: - return size; -} - -static inline unsigned int VENUS_VIEW2_OFFSET( - int color_fmt, int width, int height) -{ - unsigned int offset = 0; - unsigned int y_plane, uv_plane, y_stride, - uv_stride, y_sclines, uv_sclines; - if (!width || !height) - goto invalid_input; - - y_stride = VENUS_Y_STRIDE(color_fmt, width); - uv_stride = VENUS_UV_STRIDE(color_fmt, width); - y_sclines = VENUS_Y_SCANLINES(color_fmt, height); - uv_sclines = VENUS_UV_SCANLINES(color_fmt, height); - switch (color_fmt) { - case COLOR_FMT_NV12_MVTB: - y_plane = y_stride * y_sclines; - uv_plane = uv_stride * uv_sclines; - offset = y_plane + uv_plane; - break; - default: - break; - } -invalid_input: - return offset; + return 0; } #endif diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c index 457c29dba4a1..8f2359dc87b4 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c @@ -128,7 +128,7 @@ static void unref_cursor_worker(struct drm_flip_work *work, void *val) struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base); struct msm_kms *kms = &mdp4_kms->base.base; - msm_gem_put_iova(val, kms->aspace); + msm_gem_unpin_iova(val, kms->aspace); drm_gem_object_put_unlocked(val); } @@ -384,7 +384,7 @@ static void update_cursor(struct drm_crtc *crtc) if (next_bo) { /* take a obj ref + iova ref when we start scanning out: */ drm_gem_object_get(next_bo); - msm_gem_get_iova(next_bo, kms->aspace, &iova); + msm_gem_get_and_pin_iova(next_bo, kms->aspace, &iova); /* enable cursor: */ mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma), @@ -429,7 +429,7 @@ static int mdp4_crtc_cursor_set(struct drm_crtc *crtc, int ret; if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) { - dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height); + DRM_DEV_ERROR(dev->dev, "bad cursor size: %dx%d\n", width, height); return -EINVAL; } @@ -442,7 +442,7 @@ static int mdp4_crtc_cursor_set(struct drm_crtc *crtc, } if (cursor_bo) { - ret = msm_gem_get_iova(cursor_bo, kms->aspace, &iova); + ret = msm_gem_get_and_pin_iova(cursor_bo, kms->aspace, &iova); if (ret) goto fail; } else { diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c index ba8e587f734b..a8fd14d4846b 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c @@ -45,7 +45,7 @@ static void bs_init(struct mdp4_dtv_encoder *mdp4_dtv_encoder) struct lcdc_platform_data *dtv_pdata = mdp4_find_pdata("dtv.0"); if (!dtv_pdata) { - dev_err(dev->dev, "could not find dtv pdata\n"); + DRM_DEV_ERROR(dev->dev, "could not find dtv pdata\n"); return; } @@ -209,16 +209,16 @@ static void mdp4_dtv_encoder_enable(struct drm_encoder *encoder) ret = clk_set_rate(mdp4_dtv_encoder->mdp_clk, pc); if (ret) - dev_err(dev->dev, "failed to set mdp_clk to %lu: %d\n", + DRM_DEV_ERROR(dev->dev, "failed to set mdp_clk to %lu: %d\n", pc, ret); ret = clk_prepare_enable(mdp4_dtv_encoder->mdp_clk); if (ret) - dev_err(dev->dev, "failed to enabled mdp_clk: %d\n", ret); + DRM_DEV_ERROR(dev->dev, "failed to enabled mdp_clk: %d\n", ret); ret = clk_prepare_enable(mdp4_dtv_encoder->hdmi_clk); if (ret) - dev_err(dev->dev, "failed to enable hdmi_clk: %d\n", ret); + DRM_DEV_ERROR(dev->dev, "failed to enable hdmi_clk: %d\n", ret); mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 1); @@ -258,14 +258,14 @@ struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev) mdp4_dtv_encoder->hdmi_clk = devm_clk_get(dev->dev, "hdmi_clk"); if (IS_ERR(mdp4_dtv_encoder->hdmi_clk)) { - dev_err(dev->dev, "failed to get hdmi_clk\n"); + DRM_DEV_ERROR(dev->dev, "failed to get hdmi_clk\n"); ret = PTR_ERR(mdp4_dtv_encoder->hdmi_clk); goto fail; } mdp4_dtv_encoder->mdp_clk = devm_clk_get(dev->dev, "tv_clk"); if (IS_ERR(mdp4_dtv_encoder->mdp_clk)) { - dev_err(dev->dev, "failed to get tv_clk\n"); + DRM_DEV_ERROR(dev->dev, "failed to get tv_clk\n"); ret = PTR_ERR(mdp4_dtv_encoder->mdp_clk); goto fail; } diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c index 44d1cda56974..e437aa806f7b 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c @@ -43,7 +43,7 @@ static int mdp4_hw_init(struct msm_kms *kms) DBG("found MDP4 version v%d.%d", major, minor); if (major != 4) { - dev_err(dev->dev, "unexpected MDP version: v%d.%d\n", + DRM_DEV_ERROR(dev->dev, "unexpected MDP version: v%d.%d\n", major, minor); ret = -ENXIO; goto out; @@ -165,7 +165,7 @@ static void mdp4_destroy(struct msm_kms *kms) struct msm_gem_address_space *aspace = kms->aspace; if (mdp4_kms->blank_cursor_iova) - msm_gem_put_iova(mdp4_kms->blank_cursor_bo, kms->aspace); + msm_gem_unpin_iova(mdp4_kms->blank_cursor_bo, kms->aspace); drm_gem_object_put_unlocked(mdp4_kms->blank_cursor_bo); if (aspace) { @@ -206,7 +206,8 @@ int mdp4_disable(struct mdp4_kms *mdp4_kms) clk_disable_unprepare(mdp4_kms->clk); if (mdp4_kms->pclk) clk_disable_unprepare(mdp4_kms->pclk); - clk_disable_unprepare(mdp4_kms->lut_clk); + if (mdp4_kms->lut_clk) + clk_disable_unprepare(mdp4_kms->lut_clk); if (mdp4_kms->axi_clk) clk_disable_unprepare(mdp4_kms->axi_clk); @@ -220,7 +221,8 @@ int mdp4_enable(struct mdp4_kms *mdp4_kms) clk_prepare_enable(mdp4_kms->clk); if (mdp4_kms->pclk) clk_prepare_enable(mdp4_kms->pclk); - clk_prepare_enable(mdp4_kms->lut_clk); + if (mdp4_kms->lut_clk) + clk_prepare_enable(mdp4_kms->lut_clk); if (mdp4_kms->axi_clk) clk_prepare_enable(mdp4_kms->axi_clk); @@ -251,7 +253,7 @@ static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms, encoder = mdp4_lcdc_encoder_init(dev, panel_node); if (IS_ERR(encoder)) { - dev_err(dev->dev, "failed to construct LCDC encoder\n"); + DRM_DEV_ERROR(dev->dev, "failed to construct LCDC encoder\n"); return PTR_ERR(encoder); } @@ -260,7 +262,7 @@ static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms, connector = mdp4_lvds_connector_init(dev, panel_node, encoder); if (IS_ERR(connector)) { - dev_err(dev->dev, "failed to initialize LVDS connector\n"); + DRM_DEV_ERROR(dev->dev, "failed to initialize LVDS connector\n"); return PTR_ERR(connector); } @@ -271,7 +273,7 @@ static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms, case DRM_MODE_ENCODER_TMDS: encoder = mdp4_dtv_encoder_init(dev); if (IS_ERR(encoder)) { - dev_err(dev->dev, "failed to construct DTV encoder\n"); + DRM_DEV_ERROR(dev->dev, "failed to construct DTV encoder\n"); return PTR_ERR(encoder); } @@ -282,7 +284,7 @@ static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms, /* Construct bridge/connector for HDMI: */ ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder); if (ret) { - dev_err(dev->dev, "failed to initialize HDMI: %d\n", ret); + DRM_DEV_ERROR(dev->dev, "failed to initialize HDMI: %d\n", ret); return ret; } } @@ -300,7 +302,7 @@ static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms, encoder = mdp4_dsi_encoder_init(dev); if (IS_ERR(encoder)) { ret = PTR_ERR(encoder); - dev_err(dev->dev, + DRM_DEV_ERROR(dev->dev, "failed to construct DSI encoder: %d\n", ret); return ret; } @@ -311,14 +313,14 @@ static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms, ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder); if (ret) { - dev_err(dev->dev, "failed to initialize DSI: %d\n", + DRM_DEV_ERROR(dev->dev, "failed to initialize DSI: %d\n", ret); return ret; } break; default: - dev_err(dev->dev, "Invalid or unsupported interface\n"); + DRM_DEV_ERROR(dev->dev, "Invalid or unsupported interface\n"); return -EINVAL; } @@ -354,7 +356,7 @@ static int modeset_init(struct mdp4_kms *mdp4_kms) for (i = 0; i < ARRAY_SIZE(vg_planes); i++) { plane = mdp4_plane_init(dev, vg_planes[i], false); if (IS_ERR(plane)) { - dev_err(dev->dev, + DRM_DEV_ERROR(dev->dev, "failed to construct plane for VG%d\n", i + 1); ret = PTR_ERR(plane); goto fail; @@ -365,7 +367,7 @@ static int modeset_init(struct mdp4_kms *mdp4_kms) for (i = 0; i < ARRAY_SIZE(mdp4_crtcs); i++) { plane = mdp4_plane_init(dev, rgb_planes[i], true); if (IS_ERR(plane)) { - dev_err(dev->dev, + DRM_DEV_ERROR(dev->dev, "failed to construct plane for RGB%d\n", i + 1); ret = PTR_ERR(plane); goto fail; @@ -374,7 +376,7 @@ static int modeset_init(struct mdp4_kms *mdp4_kms) crtc = mdp4_crtc_init(dev, plane, priv->num_crtcs, i, mdp4_crtcs[i]); if (IS_ERR(crtc)) { - dev_err(dev->dev, "failed to construct crtc for %s\n", + DRM_DEV_ERROR(dev->dev, "failed to construct crtc for %s\n", mdp4_crtc_names[i]); ret = PTR_ERR(crtc); goto fail; @@ -396,7 +398,7 @@ static int modeset_init(struct mdp4_kms *mdp4_kms) for (i = 0; i < ARRAY_SIZE(mdp4_intfs); i++) { ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]); if (ret) { - dev_err(dev->dev, "failed to initialize intf: %d, %d\n", + DRM_DEV_ERROR(dev->dev, "failed to initialize intf: %d, %d\n", i, ret); goto fail; } @@ -419,7 +421,7 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev) mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL); if (!mdp4_kms) { - dev_err(dev->dev, "failed to allocate kms\n"); + DRM_DEV_ERROR(dev->dev, "failed to allocate kms\n"); ret = -ENOMEM; goto fail; } @@ -439,7 +441,7 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev) irq = platform_get_irq(pdev, 0); if (irq < 0) { ret = irq; - dev_err(dev->dev, "failed to get irq: %d\n", ret); + DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret); goto fail; } @@ -456,14 +458,14 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev) if (mdp4_kms->vdd) { ret = regulator_enable(mdp4_kms->vdd); if (ret) { - dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret); + DRM_DEV_ERROR(dev->dev, "failed to enable regulator vdd: %d\n", ret); goto fail; } } mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk"); if (IS_ERR(mdp4_kms->clk)) { - dev_err(dev->dev, "failed to get core_clk\n"); + DRM_DEV_ERROR(dev->dev, "failed to get core_clk\n"); ret = PTR_ERR(mdp4_kms->clk); goto fail; } @@ -472,23 +474,25 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev) if (IS_ERR(mdp4_kms->pclk)) mdp4_kms->pclk = NULL; - // XXX if (rev >= MDP_REV_42) { ??? - mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk"); - if (IS_ERR(mdp4_kms->lut_clk)) { - dev_err(dev->dev, "failed to get lut_clk\n"); - ret = PTR_ERR(mdp4_kms->lut_clk); - goto fail; + if (mdp4_kms->rev >= 2) { + mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk"); + if (IS_ERR(mdp4_kms->lut_clk)) { + DRM_DEV_ERROR(dev->dev, "failed to get lut_clk\n"); + ret = PTR_ERR(mdp4_kms->lut_clk); + goto fail; + } } mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk"); if (IS_ERR(mdp4_kms->axi_clk)) { - dev_err(dev->dev, "failed to get axi_clk\n"); + DRM_DEV_ERROR(dev->dev, "failed to get axi_clk\n"); ret = PTR_ERR(mdp4_kms->axi_clk); goto fail; } clk_set_rate(mdp4_kms->clk, config->max_clk); - clk_set_rate(mdp4_kms->lut_clk, config->max_clk); + if (mdp4_kms->lut_clk) + clk_set_rate(mdp4_kms->lut_clk, config->max_clk); pm_runtime_enable(dev->dev); mdp4_kms->rpm_enabled = true; @@ -519,29 +523,29 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev) if (ret) goto fail; } else { - dev_info(dev->dev, "no iommu, fallback to phys " + DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys " "contig buffers for scanout\n"); aspace = NULL; } ret = modeset_init(mdp4_kms); if (ret) { - dev_err(dev->dev, "modeset_init failed: %d\n", ret); + DRM_DEV_ERROR(dev->dev, "modeset_init failed: %d\n", ret); goto fail; } - mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC); + mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC | MSM_BO_SCANOUT); if (IS_ERR(mdp4_kms->blank_cursor_bo)) { ret = PTR_ERR(mdp4_kms->blank_cursor_bo); - dev_err(dev->dev, "could not allocate blank-cursor bo: %d\n", ret); + DRM_DEV_ERROR(dev->dev, "could not allocate blank-cursor bo: %d\n", ret); mdp4_kms->blank_cursor_bo = NULL; goto fail; } - ret = msm_gem_get_iova(mdp4_kms->blank_cursor_bo, kms->aspace, + ret = msm_gem_get_and_pin_iova(mdp4_kms->blank_cursor_bo, kms->aspace, &mdp4_kms->blank_cursor_iova); if (ret) { - dev_err(dev->dev, "could not pin blank-cursor bo: %d\n", ret); + DRM_DEV_ERROR(dev->dev, "could not pin blank-cursor bo: %d\n", ret); goto fail; } diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c index 2bfb39082f54..c9e34501a89e 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c @@ -47,7 +47,7 @@ static void bs_init(struct mdp4_lcdc_encoder *mdp4_lcdc_encoder) struct lcdc_platform_data *lcdc_pdata = mdp4_find_pdata("lvds.0"); if (!lcdc_pdata) { - dev_err(dev->dev, "could not find lvds pdata\n"); + DRM_DEV_ERROR(dev->dev, "could not find lvds pdata\n"); return; } @@ -224,7 +224,7 @@ static void setup_phy(struct drm_encoder *encoder) break; default: - dev_err(dev->dev, "unknown bpp: %d\n", bpp); + DRM_DEV_ERROR(dev->dev, "unknown bpp: %d\n", bpp); return; } @@ -241,7 +241,7 @@ static void setup_phy(struct drm_encoder *encoder) MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN; break; default: - dev_err(dev->dev, "unknown # of channels: %d\n", nchan); + DRM_DEV_ERROR(dev->dev, "unknown # of channels: %d\n", nchan); return; } @@ -361,7 +361,7 @@ static void mdp4_lcdc_encoder_disable(struct drm_encoder *encoder) for (i = 0; i < ARRAY_SIZE(mdp4_lcdc_encoder->regs); i++) { ret = regulator_disable(mdp4_lcdc_encoder->regs[i]); if (ret) - dev_err(dev->dev, "failed to disable regulator: %d\n", ret); + DRM_DEV_ERROR(dev->dev, "failed to disable regulator: %d\n", ret); } bs_set(mdp4_lcdc_encoder, 0); @@ -377,20 +377,25 @@ static void mdp4_lcdc_encoder_enable(struct drm_encoder *encoder) unsigned long pc = mdp4_lcdc_encoder->pixclock; struct mdp4_kms *mdp4_kms = get_kms(encoder); struct drm_panel *panel; + uint32_t config; int i, ret; if (WARN_ON(mdp4_lcdc_encoder->enabled)) return; /* TODO: hard-coded for 18bpp: */ - mdp4_crtc_set_config(encoder->crtc, - MDP4_DMA_CONFIG_R_BPC(BPC6) | - MDP4_DMA_CONFIG_G_BPC(BPC6) | - MDP4_DMA_CONFIG_B_BPC(BPC6) | - MDP4_DMA_CONFIG_PACK_ALIGN_MSB | - MDP4_DMA_CONFIG_PACK(0x21) | - MDP4_DMA_CONFIG_DEFLKR_EN | - MDP4_DMA_CONFIG_DITHER_EN); + config = + MDP4_DMA_CONFIG_R_BPC(BPC6) | + MDP4_DMA_CONFIG_G_BPC(BPC6) | + MDP4_DMA_CONFIG_B_BPC(BPC6) | + MDP4_DMA_CONFIG_PACK(0x21) | + MDP4_DMA_CONFIG_DEFLKR_EN | + MDP4_DMA_CONFIG_DITHER_EN; + + if (!of_property_read_bool(dev->dev->of_node, "qcom,lcdc-align-lsb")) + config |= MDP4_DMA_CONFIG_PACK_ALIGN_MSB; + + mdp4_crtc_set_config(encoder->crtc, config); mdp4_crtc_set_intf(encoder->crtc, INTF_LCDC_DTV, 0); bs_set(mdp4_lcdc_encoder, 1); @@ -398,16 +403,16 @@ static void mdp4_lcdc_encoder_enable(struct drm_encoder *encoder) for (i = 0; i < ARRAY_SIZE(mdp4_lcdc_encoder->regs); i++) { ret = regulator_enable(mdp4_lcdc_encoder->regs[i]); if (ret) - dev_err(dev->dev, "failed to enable regulator: %d\n", ret); + DRM_DEV_ERROR(dev->dev, "failed to enable regulator: %d\n", ret); } DBG("setting lcdc_clk=%lu", pc); ret = clk_set_rate(mdp4_lcdc_encoder->lcdc_clk, pc); if (ret) - dev_err(dev->dev, "failed to configure lcdc_clk: %d\n", ret); + DRM_DEV_ERROR(dev->dev, "failed to configure lcdc_clk: %d\n", ret); ret = clk_prepare_enable(mdp4_lcdc_encoder->lcdc_clk); if (ret) - dev_err(dev->dev, "failed to enable lcdc_clk: %d\n", ret); + DRM_DEV_ERROR(dev->dev, "failed to enable lcdc_clk: %d\n", ret); panel = of_drm_find_panel(mdp4_lcdc_encoder->panel_node); if (!IS_ERR(panel)) { @@ -461,7 +466,7 @@ struct drm_encoder *mdp4_lcdc_encoder_init(struct drm_device *dev, /* TODO: do we need different pll in other cases? */ mdp4_lcdc_encoder->lcdc_clk = mpd4_lvds_pll_init(dev); if (IS_ERR(mdp4_lcdc_encoder->lcdc_clk)) { - dev_err(dev->dev, "failed to get lvds_clk\n"); + DRM_DEV_ERROR(dev->dev, "failed to get lvds_clk\n"); ret = PTR_ERR(mdp4_lcdc_encoder->lcdc_clk); goto fail; } @@ -470,7 +475,7 @@ struct drm_encoder *mdp4_lcdc_encoder_init(struct drm_device *dev, reg = devm_regulator_get(dev->dev, "lvds-vccs-3p3v"); if (IS_ERR(reg)) { ret = PTR_ERR(reg); - dev_err(dev->dev, "failed to get lvds-vccs-3p3v: %d\n", ret); + DRM_DEV_ERROR(dev->dev, "failed to get lvds-vccs-3p3v: %d\n", ret); goto fail; } mdp4_lcdc_encoder->regs[0] = reg; @@ -478,7 +483,7 @@ struct drm_encoder *mdp4_lcdc_encoder_init(struct drm_device *dev, reg = devm_regulator_get(dev->dev, "lvds-pll-vdda"); if (IS_ERR(reg)) { ret = PTR_ERR(reg); - dev_err(dev->dev, "failed to get lvds-pll-vdda: %d\n", ret); + DRM_DEV_ERROR(dev->dev, "failed to get lvds-pll-vdda: %d\n", ret); goto fail; } mdp4_lcdc_encoder->regs[1] = reg; @@ -486,7 +491,7 @@ struct drm_encoder *mdp4_lcdc_encoder_init(struct drm_device *dev, reg = devm_regulator_get(dev->dev, "lvds-vdda"); if (IS_ERR(reg)) { ret = PTR_ERR(reg); - dev_err(dev->dev, "failed to get lvds-vdda: %d\n", ret); + DRM_DEV_ERROR(dev->dev, "failed to get lvds-vdda: %d\n", ret); goto fail; } mdp4_lcdc_encoder->regs[2] = reg; diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c index 79ff653d8081..005066f7154d 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c @@ -68,7 +68,6 @@ static void mdp4_plane_destroy(struct drm_plane *plane) { struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane); - drm_plane_helper_disable(plane, NULL); drm_plane_cleanup(plane); kfree(mdp4_plane); @@ -235,22 +234,22 @@ static int mdp4_plane_mode_set(struct drm_plane *plane, format = to_mdp_format(msm_framebuffer_format(fb)); if (src_w > (crtc_w * DOWN_SCALE_MAX)) { - dev_err(dev->dev, "Width down scaling exceeds limits!\n"); + DRM_DEV_ERROR(dev->dev, "Width down scaling exceeds limits!\n"); return -ERANGE; } if (src_h > (crtc_h * DOWN_SCALE_MAX)) { - dev_err(dev->dev, "Height down scaling exceeds limits!\n"); + DRM_DEV_ERROR(dev->dev, "Height down scaling exceeds limits!\n"); return -ERANGE; } if (crtc_w > (src_w * UP_SCALE_MAX)) { - dev_err(dev->dev, "Width up scaling exceeds limits!\n"); + DRM_DEV_ERROR(dev->dev, "Width up scaling exceeds limits!\n"); return -ERANGE; } if (crtc_h > (src_h * UP_SCALE_MAX)) { - dev_err(dev->dev, "Height up scaling exceeds limits!\n"); + DRM_DEV_ERROR(dev->dev, "Height up scaling exceeds limits!\n"); return -ERANGE; } diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c index 824067d2d427..ea8f7d7daf7f 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c @@ -553,6 +553,91 @@ const struct mdp5_cfg_hw msm8x96_config = { .max_clk = 412500000, }; +const struct mdp5_cfg_hw msm8917_config = { + .name = "msm8917", + .mdp = { + .count = 1, + .caps = MDP_CAP_CDM, + }, + .ctl = { + .count = 3, + .base = { 0x01000, 0x01200, 0x01400 }, + .flush_hw_mask = 0xffffffff, + }, + .pipe_vig = { + .count = 1, + .base = { 0x04000 }, + .caps = MDP_PIPE_CAP_HFLIP | + MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_SCALE | + MDP_PIPE_CAP_CSC | + MDP_PIPE_CAP_DECIMATION | + MDP_PIPE_CAP_SW_PIX_EXT | + 0, + }, + .pipe_rgb = { + .count = 2, + .base = { 0x14000, 0x16000 }, + .caps = MDP_PIPE_CAP_HFLIP | + MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_DECIMATION | + MDP_PIPE_CAP_SW_PIX_EXT | + 0, + }, + .pipe_dma = { + .count = 1, + .base = { 0x24000 }, + .caps = MDP_PIPE_CAP_HFLIP | + MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_SW_PIX_EXT | + 0, + }, + .pipe_cursor = { + .count = 1, + .base = { 0x34000 }, + .caps = MDP_PIPE_CAP_HFLIP | + MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_SW_PIX_EXT | + MDP_PIPE_CAP_CURSOR | + 0, + }, + + .lm = { + .count = 2, + .base = { 0x44000, 0x45000 }, + .instances = { + { .id = 0, .pp = 0, .dspp = 0, + .caps = MDP_LM_CAP_DISPLAY, }, + { .id = 1, .pp = -1, .dspp = -1, + .caps = MDP_LM_CAP_WB }, + }, + .nb_stages = 8, + .max_width = 2048, + .max_height = 0xFFFF, + }, + .dspp = { + .count = 1, + .base = { 0x54000 }, + + }, + .pp = { + .count = 1, + .base = { 0x70000 }, + }, + .cdm = { + .count = 1, + .base = { 0x79200 }, + }, + .intf = { + .base = { 0x6a000, 0x6a800 }, + .connect = { + [0] = INTF_DISABLED, + [1] = INTF_DSI, + }, + }, + .max_clk = 320000000, +}; + static const struct mdp5_cfg_handler cfg_handlers[] = { { .revision = 0, .config = { .hw = &msm8x74v1_config } }, { .revision = 2, .config = { .hw = &msm8x74v2_config } }, @@ -560,6 +645,7 @@ static const struct mdp5_cfg_handler cfg_handlers[] = { { .revision = 6, .config = { .hw = &msm8x16_config } }, { .revision = 9, .config = { .hw = &msm8x94_config } }, { .revision = 7, .config = { .hw = &msm8x96_config } }, + { .revision = 15, .config = { .hw = &msm8917_config } }, }; static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev); @@ -600,7 +686,7 @@ struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms, } if (major != 1) { - dev_err(dev->dev, "unexpected MDP major version: v%d.%d\n", + DRM_DEV_ERROR(dev->dev, "unexpected MDP major version: v%d.%d\n", major, minor); ret = -ENXIO; goto fail; @@ -615,7 +701,7 @@ struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms, break; } if (unlikely(!mdp5_cfg)) { - dev_err(dev->dev, "unexpected MDP minor revision: v%d.%d\n", + DRM_DEV_ERROR(dev->dev, "unexpected MDP minor revision: v%d.%d\n", major, minor); ret = -ENXIO; goto fail; diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c index d6f79dc755b4..c1962f29ec7d 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c @@ -55,20 +55,20 @@ static int pingpong_tearcheck_setup(struct drm_encoder *encoder, int pp_id = mixer->pp; if (IS_ERR_OR_NULL(mdp5_kms->vsync_clk)) { - dev_err(dev, "vsync_clk is not initialized\n"); + DRM_DEV_ERROR(dev, "vsync_clk is not initialized\n"); return -EINVAL; } total_lines_x100 = mode->vtotal * mode->vrefresh; if (!total_lines_x100) { - dev_err(dev, "%s: vtotal(%d) or vrefresh(%d) is 0\n", + DRM_DEV_ERROR(dev, "%s: vtotal(%d) or vrefresh(%d) is 0\n", __func__, mode->vtotal, mode->vrefresh); return -EINVAL; } vsync_clk_speed = clk_round_rate(mdp5_kms->vsync_clk, VSYNC_CLK_RATE); if (vsync_clk_speed <= 0) { - dev_err(dev, "vsync_clk round rate failed %ld\n", + DRM_DEV_ERROR(dev, "vsync_clk round rate failed %ld\n", vsync_clk_speed); return -EINVAL; } @@ -102,13 +102,13 @@ static int pingpong_tearcheck_enable(struct drm_encoder *encoder) ret = clk_set_rate(mdp5_kms->vsync_clk, clk_round_rate(mdp5_kms->vsync_clk, VSYNC_CLK_RATE)); if (ret) { - dev_err(encoder->dev->dev, + DRM_DEV_ERROR(encoder->dev->dev, "vsync_clk clk_set_rate failed, %d\n", ret); return ret; } ret = clk_prepare_enable(mdp5_kms->vsync_clk); if (ret) { - dev_err(encoder->dev->dev, + DRM_DEV_ERROR(encoder->dev->dev, "vsync_clk clk_prepare_enable failed, %d\n", ret); return ret; } diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c index b1da9ce54379..c5fde1a4191a 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c @@ -173,7 +173,7 @@ static void unref_cursor_worker(struct drm_flip_work *work, void *val) struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base); struct msm_kms *kms = &mdp5_kms->base.base; - msm_gem_put_iova(val, kms->aspace); + msm_gem_unpin_iova(val, kms->aspace); drm_gem_object_put_unlocked(val); } @@ -662,7 +662,7 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, ret = mdp5_crtc_setup_pipeline(crtc, state, need_right_mixer); if (ret) { - dev_err(dev->dev, "couldn't assign mixers %d\n", ret); + DRM_DEV_ERROR(dev->dev, "couldn't assign mixers %d\n", ret); return ret; } @@ -679,7 +679,7 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, * and that we don't have conflicting mixer stages: */ if ((cnt + start - 1) >= hw_cfg->lm.nb_stages) { - dev_err(dev->dev, "too many planes! cnt=%d, start stage=%d\n", + DRM_DEV_ERROR(dev->dev, "too many planes! cnt=%d, start stage=%d\n", cnt, start); return -EINVAL; } @@ -879,7 +879,7 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, } if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) { - dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height); + DRM_DEV_ERROR(dev->dev, "bad cursor size: %dx%d\n", width, height); return -EINVAL; } @@ -903,7 +903,7 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, if (!cursor_bo) return -ENOENT; - ret = msm_gem_get_iova(cursor_bo, kms->aspace, + ret = msm_gem_get_and_pin_iova(cursor_bo, kms->aspace, &mdp5_crtc->cursor.iova); if (ret) return -EINVAL; @@ -924,7 +924,7 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, set_cursor: ret = mdp5_ctl_set_cursor(ctl, pipeline, 0, cursor_enable); if (ret) { - dev_err(dev->dev, "failed to %sable cursor: %d\n", + DRM_DEV_ERROR(dev->dev, "failed to %sable cursor: %d\n", cursor_enable ? "en" : "dis", ret); goto end; } diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c index f93d5681267c..65a871f9f0d9 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c @@ -262,13 +262,13 @@ int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline, struct mdp5_hw_mixer *mixer = pipeline->mixer; if (unlikely(WARN_ON(!mixer))) { - dev_err(ctl_mgr->dev->dev, "CTL %d cannot find LM", + DRM_DEV_ERROR(ctl_mgr->dev->dev, "CTL %d cannot find LM", ctl->id); return -EINVAL; } if (pipeline->r_mixer) { - dev_err(ctl_mgr->dev->dev, "unsupported configuration"); + DRM_DEV_ERROR(ctl_mgr->dev->dev, "unsupported configuration"); return -EINVAL; } @@ -604,10 +604,10 @@ int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable) mdp5_write(mdp5_kms, REG_MDP5_SPARE_0, 0); return 0; } else if ((ctlx->pair != NULL) || (ctly->pair != NULL)) { - dev_err(ctl_mgr->dev->dev, "CTLs already paired\n"); + DRM_DEV_ERROR(ctl_mgr->dev->dev, "CTLs already paired\n"); return -EINVAL; } else if (!(ctlx->status & ctly->status & CTL_STAT_BOOKED)) { - dev_err(ctl_mgr->dev->dev, "Only pair booked CTLs\n"); + DRM_DEV_ERROR(ctl_mgr->dev->dev, "Only pair booked CTLs\n"); return -EINVAL; } @@ -652,7 +652,7 @@ struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctl_mgr, if ((ctl_mgr->ctls[c].status & checkm) == match) goto found; - dev_err(ctl_mgr->dev->dev, "No more CTL available!"); + DRM_DEV_ERROR(ctl_mgr->dev->dev, "No more CTL available!"); goto unlock; found: @@ -698,13 +698,13 @@ struct mdp5_ctl_manager *mdp5_ctlm_init(struct drm_device *dev, ctl_mgr = kzalloc(sizeof(*ctl_mgr), GFP_KERNEL); if (!ctl_mgr) { - dev_err(dev->dev, "failed to allocate CTL manager\n"); + DRM_DEV_ERROR(dev->dev, "failed to allocate CTL manager\n"); ret = -ENOMEM; goto fail; } if (unlikely(WARN_ON(ctl_cfg->count > MAX_CTL))) { - dev_err(dev->dev, "Increase static pool size to at least %d\n", + DRM_DEV_ERROR(dev->dev, "Increase static pool size to at least %d\n", ctl_cfg->count); ret = -ENOSPC; goto fail; @@ -723,7 +723,7 @@ struct mdp5_ctl_manager *mdp5_ctlm_init(struct drm_device *dev, struct mdp5_ctl *ctl = &ctl_mgr->ctls[c]; if (WARN_ON(!ctl_cfg->base[c])) { - dev_err(dev->dev, "CTL_%d: base is null!\n", c); + DRM_DEV_ERROR(dev->dev, "CTL_%d: base is null!\n", c); ret = -EINVAL; spin_unlock_irqrestore(&ctl_mgr->pool_lock, flags); goto fail; diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c index bddd625ab91b..d27e35a217bd 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c @@ -264,7 +264,7 @@ static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) minor->debugfs_root, minor); if (ret) { - dev_err(dev->dev, "could not install mdp5_debugfs_list\n"); + DRM_DEV_ERROR(dev->dev, "could not install mdp5_debugfs_list\n"); return ret; } @@ -337,7 +337,7 @@ static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms, encoder = mdp5_encoder_init(dev, intf, ctl); if (IS_ERR(encoder)) { - dev_err(dev->dev, "failed to construct encoder\n"); + DRM_DEV_ERROR(dev->dev, "failed to construct encoder\n"); return encoder; } @@ -418,7 +418,7 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_kms, int dsi_id = get_dsi_id_from_intf(hw_cfg, intf->num); if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) { - dev_err(dev->dev, "failed to find dsi from intf %d\n", + DRM_DEV_ERROR(dev->dev, "failed to find dsi from intf %d\n", intf->num); ret = -EINVAL; break; @@ -443,7 +443,7 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_kms, break; } default: - dev_err(dev->dev, "unknown intf: %d\n", intf->type); + DRM_DEV_ERROR(dev->dev, "unknown intf: %d\n", intf->type); ret = -EINVAL; break; } @@ -500,7 +500,7 @@ static int modeset_init(struct mdp5_kms *mdp5_kms) plane = mdp5_plane_init(dev, type); if (IS_ERR(plane)) { ret = PTR_ERR(plane); - dev_err(dev->dev, "failed to construct plane %d (%d)\n", i, ret); + DRM_DEV_ERROR(dev->dev, "failed to construct plane %d (%d)\n", i, ret); goto fail; } priv->planes[priv->num_planes++] = plane; @@ -517,7 +517,7 @@ static int modeset_init(struct mdp5_kms *mdp5_kms) crtc = mdp5_crtc_init(dev, primary[i], cursor[i], i); if (IS_ERR(crtc)) { ret = PTR_ERR(crtc); - dev_err(dev->dev, "failed to construct crtc %d (%d)\n", i, ret); + DRM_DEV_ERROR(dev->dev, "failed to construct crtc %d (%d)\n", i, ret); goto fail; } priv->crtcs[priv->num_crtcs++] = crtc; @@ -552,7 +552,7 @@ static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms, *major = FIELD(version, MDP5_HW_VERSION_MAJOR); *minor = FIELD(version, MDP5_HW_VERSION_MINOR); - dev_info(dev, "MDP5 version v%d.%d", *major, *minor); + DRM_DEV_INFO(dev, "MDP5 version v%d.%d", *major, *minor); } static int get_clk(struct platform_device *pdev, struct clk **clkp, @@ -561,7 +561,7 @@ static int get_clk(struct platform_device *pdev, struct clk **clkp, struct device *dev = &pdev->dev; struct clk *clk = msm_clk_get(pdev, name); if (IS_ERR(clk) && mandatory) { - dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk)); + DRM_DEV_ERROR(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk)); return PTR_ERR(clk); } if (IS_ERR(clk)) @@ -688,7 +688,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) irq = irq_of_parse_and_map(pdev->dev.of_node, 0); if (irq < 0) { ret = irq; - dev_err(&pdev->dev, "failed to get irq: %d\n", ret); + DRM_DEV_ERROR(&pdev->dev, "failed to get irq: %d\n", ret); goto fail; } @@ -724,12 +724,12 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports, ARRAY_SIZE(iommu_ports)); if (ret) { - dev_err(&pdev->dev, "failed to attach iommu: %d\n", + DRM_DEV_ERROR(&pdev->dev, "failed to attach iommu: %d\n", ret); goto fail; } } else { - dev_info(&pdev->dev, + DRM_DEV_INFO(&pdev->dev, "no iommu, fallback to phys contig buffers for scanout\n"); aspace = NULL; } @@ -738,7 +738,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) ret = modeset_init(mdp5_kms); if (ret) { - dev_err(&pdev->dev, "modeset_init failed: %d\n", ret); + DRM_DEV_ERROR(&pdev->dev, "modeset_init failed: %d\n", ret); goto fail; } @@ -795,7 +795,7 @@ static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt, hwpipe = mdp5_pipe_init(pipes[i], offsets[i], caps); if (IS_ERR(hwpipe)) { ret = PTR_ERR(hwpipe); - dev_err(dev->dev, "failed to construct pipe for %s (%d)\n", + DRM_DEV_ERROR(dev->dev, "failed to construct pipe for %s (%d)\n", pipe2name(pipes[i]), ret); return ret; } @@ -867,7 +867,7 @@ static int hwmixer_init(struct mdp5_kms *mdp5_kms) mixer = mdp5_mixer_init(&hw_cfg->lm.instances[i]); if (IS_ERR(mixer)) { ret = PTR_ERR(mixer); - dev_err(dev->dev, "failed to construct LM%d (%d)\n", + DRM_DEV_ERROR(dev->dev, "failed to construct LM%d (%d)\n", i, ret); return ret; } @@ -897,7 +897,7 @@ static int interface_init(struct mdp5_kms *mdp5_kms) intf = kzalloc(sizeof(*intf), GFP_KERNEL); if (!intf) { - dev_err(dev->dev, "failed to construct INTF%d\n", i); + DRM_DEV_ERROR(dev->dev, "failed to construct INTF%d\n", i); return -ENOMEM; } diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c index 1cc4e57f0226..889c2940692c 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c @@ -132,7 +132,7 @@ static int mdss_irq_domain_init(struct mdp5_mdss *mdp5_mdss) d = irq_domain_add_linear(dev->of_node, 32, &mdss_hw_irqdomain_ops, mdp5_mdss); if (!d) { - dev_err(dev, "mdss irq domain add failed\n"); + DRM_DEV_ERROR(dev, "mdss irq domain add failed\n"); return -ENXIO; } @@ -246,7 +246,7 @@ int mdp5_mdss_init(struct drm_device *dev) ret = msm_mdss_get_clocks(mdp5_mdss); if (ret) { - dev_err(dev->dev, "failed to get clocks: %d\n", ret); + DRM_DEV_ERROR(dev->dev, "failed to get clocks: %d\n", ret); goto fail; } @@ -259,7 +259,7 @@ int mdp5_mdss_init(struct drm_device *dev) ret = regulator_enable(mdp5_mdss->vdd); if (ret) { - dev_err(dev->dev, "failed to enable regulator vdd: %d\n", + DRM_DEV_ERROR(dev->dev, "failed to enable regulator vdd: %d\n", ret); goto fail; } @@ -267,13 +267,13 @@ int mdp5_mdss_init(struct drm_device *dev) ret = devm_request_irq(dev->dev, platform_get_irq(pdev, 0), mdss_irq, 0, "mdss_isr", mdp5_mdss); if (ret) { - dev_err(dev->dev, "failed to init irq: %d\n", ret); + DRM_DEV_ERROR(dev->dev, "failed to init irq: %d\n", ret); goto fail_irq; } ret = mdss_irq_domain_init(mdp5_mdss); if (ret) { - dev_err(dev->dev, "failed to init sub-block irqs: %d\n", ret); + DRM_DEV_ERROR(dev->dev, "failed to init sub-block irqs: %d\n", ret); goto fail_irq; } diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c index 7f42c3e68a53..be13140967b4 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c @@ -46,7 +46,6 @@ static void mdp5_plane_destroy(struct drm_plane *plane) { struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); - drm_plane_helper_disable(plane, NULL); drm_plane_cleanup(plane); kfree(mdp5_plane); @@ -126,7 +125,7 @@ static int mdp5_plane_atomic_set_property(struct drm_plane *plane, SET_PROPERTY(zpos, ZPOS, uint8_t); - dev_err(dev->dev, "Invalid property\n"); + DRM_DEV_ERROR(dev->dev, "Invalid property\n"); ret = -EINVAL; done: return ret; @@ -154,7 +153,7 @@ static int mdp5_plane_atomic_get_property(struct drm_plane *plane, GET_PROPERTY(zpos, ZPOS, uint8_t); - dev_err(dev->dev, "Invalid property\n"); + DRM_DEV_ERROR(dev->dev, "Invalid property\n"); ret = -EINVAL; done: return ret; @@ -659,7 +658,7 @@ static int calc_scalex_steps(struct drm_plane *plane, ret = calc_phase_step(src, dest, &phasex_step); if (ret) { - dev_err(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret); + DRM_DEV_ERROR(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret); return ret; } @@ -684,7 +683,7 @@ static int calc_scaley_steps(struct drm_plane *plane, ret = calc_phase_step(src, dest, &phasey_step); if (ret) { - dev_err(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret); + DRM_DEV_ERROR(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret); return ret; } diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c index 96c2b828dba4..7cebcb2b3a37 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c @@ -88,7 +88,7 @@ static int smp_request_block(struct mdp5_smp *smp, avail = cnt - bitmap_weight(state->state, cnt); if (nblks > avail) { - dev_err(smp->dev->dev, "out of blks (req=%d > avail=%d)\n", + DRM_DEV_ERROR(smp->dev->dev, "out of blks (req=%d > avail=%d)\n", nblks, avail); return -ENOSPC; } @@ -188,7 +188,7 @@ int mdp5_smp_assign(struct mdp5_smp *smp, struct mdp5_smp_state *state, DBG("%s[%d]: request %d SMP blocks", pipe2name(pipe), i, n); ret = smp_request_block(smp, state, cid, n); if (ret) { - dev_err(dev->dev, "Cannot allocate %d SMP blocks: %d\n", + DRM_DEV_ERROR(dev->dev, "Cannot allocate %d SMP blocks: %d\n", n, ret); return ret; } |