diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/subdev')
93 files changed, 6686 insertions, 2852 deletions
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/base.c b/drivers/gpu/drm/nouveau/core/subdev/bar/base.c index 73b1ed20c8d5..b1adc69efd88 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bar/base.c +++ b/drivers/gpu/drm/nouveau/core/subdev/bar/base.c @@ -38,10 +38,12 @@ struct nouveau_barobj { static int nouveau_barobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *mem, u32 size, + struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) { + struct nouveau_device *device = nv_device(parent); struct nouveau_bar *bar = (void *)engine; + struct nouveau_mem *mem = data; struct nouveau_barobj *barobj; int ret; @@ -54,7 +56,13 @@ nouveau_barobj_ctor(struct nouveau_object *parent, if (ret) return ret; - barobj->iomem = bar->iomem + (u32)barobj->vma.offset; + barobj->iomem = ioremap(nv_device_resource_start(device, 3) + + (u32)barobj->vma.offset, mem->size << 12); + if (!barobj->iomem) { + nv_warn(bar, "PRAMIN ioremap failed\n"); + return -ENOMEM; + } + return 0; } @@ -63,8 +71,11 @@ nouveau_barobj_dtor(struct nouveau_object *object) { struct nouveau_bar *bar = (void *)object->engine; struct nouveau_barobj *barobj = (void *)object; - if (barobj->vma.node) + if (barobj->vma.node) { + if (barobj->iomem) + iounmap(barobj->iomem); bar->unmap(bar, &barobj->vma); + } nouveau_object_destroy(&barobj->base); } @@ -99,8 +110,12 @@ nouveau_bar_alloc(struct nouveau_bar *bar, struct nouveau_object *parent, struct nouveau_mem *mem, struct nouveau_object **pobject) { struct nouveau_object *engine = nv_object(bar); - return nouveau_object_ctor(parent, engine, &nouveau_barobj_oclass, - mem, 0, pobject); + struct nouveau_object *gpuobj; + int ret = nouveau_object_ctor(parent, engine, &nouveau_barobj_oclass, + mem, 0, &gpuobj); + if (ret == 0) + *pobject = gpuobj; + return ret; } int @@ -108,7 +123,6 @@ nouveau_bar_create_(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, int length, void **pobject) { - struct nouveau_device *device = nv_device(parent); struct nouveau_bar *bar; int ret; @@ -118,18 +132,12 @@ nouveau_bar_create_(struct nouveau_object *parent, if (ret) return ret; - if (nv_device_resource_len(device, 3) != 0) - bar->iomem = ioremap(nv_device_resource_start(device, 3), - nv_device_resource_len(device, 3)); - return 0; } void nouveau_bar_destroy(struct nouveau_bar *bar) { - if (bar->iomem) - iounmap(bar->iomem); nouveau_subdev_destroy(&bar->base); } diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/gk20a.c b/drivers/gpu/drm/nouveau/core/subdev/bar/gk20a.c new file mode 100644 index 000000000000..bf877af9d3bd --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/bar/gk20a.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include <subdev/bar.h> + +#include "priv.h" + +int +gk20a_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nouveau_bar *bar; + int ret; + + ret = nvc0_bar_ctor(parent, engine, oclass, data, size, pobject); + if (ret) + return ret; + + bar = (struct nouveau_bar *)*pobject; + bar->iomap_uncached = true; + + return 0; +} + +struct nouveau_oclass +gk20a_bar_oclass = { + .handle = NV_SUBDEV(BAR, 0xea), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = gk20a_bar_ctor, + .dtor = nvc0_bar_dtor, + .init = nvc0_bar_init, + .fini = _nouveau_bar_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c index ca8139b9ab27..05a278bab247 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c @@ -133,7 +133,7 @@ nvc0_bar_init_vm(struct nvc0_bar_priv *priv, struct nvc0_bar_priv_vm *bar_vm, return 0; } -static int +int nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) @@ -169,7 +169,7 @@ nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -static void +void nvc0_bar_dtor(struct nouveau_object *object) { struct nvc0_bar_priv *priv = (void *)object; @@ -188,7 +188,7 @@ nvc0_bar_dtor(struct nouveau_object *object) nouveau_bar_destroy(&priv->base); } -static int +int nvc0_bar_init(struct nouveau_object *object) { struct nvc0_bar_priv *priv = (void *)object; @@ -200,7 +200,6 @@ nvc0_bar_init(struct nouveau_object *object) nv_mask(priv, 0x000200, 0x00000100, 0x00000000); nv_mask(priv, 0x000200, 0x00000100, 0x00000100); - nv_mask(priv, 0x100c80, 0x00000001, 0x00000000); nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12); if (priv->bar[0].mem) diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/priv.h b/drivers/gpu/drm/nouveau/core/subdev/bar/priv.h index ffad8f337ead..3ee8b1476d00 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bar/priv.h +++ b/drivers/gpu/drm/nouveau/core/subdev/bar/priv.h @@ -23,4 +23,10 @@ int nouveau_bar_alloc(struct nouveau_bar *, struct nouveau_object *, void nv84_bar_flush(struct nouveau_bar *); +int nvc0_bar_ctor(struct nouveau_object *, struct nouveau_object *, + struct nouveau_oclass *, void *, u32, + struct nouveau_object **); +void nvc0_bar_dtor(struct nouveau_object *); +int nvc0_bar_init(struct nouveau_object *); + #endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/M0205.c b/drivers/gpu/drm/nouveau/core/subdev/bios/M0205.c new file mode 100644 index 000000000000..ac9617c5fc2a --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/bios/M0205.c @@ -0,0 +1,136 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include <subdev/bios.h> +#include <subdev/bios/bit.h> +#include <subdev/bios/M0205.h> + +u32 +nvbios_M0205Te(struct nouveau_bios *bios, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz) +{ + struct bit_entry bit_M; + u32 data = 0x00000000; + + if (!bit_entry(bios, 'M', &bit_M)) { + if (bit_M.version == 2 && bit_M.length > 0x08) + data = nv_ro32(bios, bit_M.offset + 0x05); + if (data) { + *ver = nv_ro08(bios, data + 0x00); + switch (*ver) { + case 0x10: + *hdr = nv_ro08(bios, data + 0x01); + *len = nv_ro08(bios, data + 0x02); + *ssz = nv_ro08(bios, data + 0x03); + *snr = nv_ro08(bios, data + 0x04); + *cnt = nv_ro08(bios, data + 0x05); + return data; + default: + break; + } + } + } + + return 0x00000000; +} + +u32 +nvbios_M0205Tp(struct nouveau_bios *bios, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz, + struct nvbios_M0205T *info) +{ + u32 data = nvbios_M0205Te(bios, ver, hdr, cnt, len, snr, ssz); + memset(info, 0x00, sizeof(*info)); + switch (!!data * *ver) { + case 0x10: + info->freq = nv_ro16(bios, data + 0x06); + break; + default: + break; + } + return data; +} + +u32 +nvbios_M0205Ee(struct nouveau_bios *bios, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +{ + u8 snr, ssz; + u32 data = nvbios_M0205Te(bios, ver, hdr, cnt, len, &snr, &ssz); + if (data && idx < *cnt) { + data = data + *hdr + idx * (*len + (snr * ssz)); + *hdr = *len; + *cnt = snr; + *len = ssz; + return data; + } + return 0x00000000; +} + +u32 +nvbios_M0205Ep(struct nouveau_bios *bios, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, + struct nvbios_M0205E *info) +{ + u32 data = nvbios_M0205Ee(bios, idx, ver, hdr, cnt, len); + memset(info, 0x00, sizeof(*info)); + switch (!!data * *ver) { + case 0x10: + info->type = nv_ro08(bios, data + 0x00) & 0x0f; + return data; + default: + break; + } + return 0x00000000; +} + +u32 +nvbios_M0205Se(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr) +{ + + u8 cnt, len; + u32 data = nvbios_M0205Ee(bios, ent, ver, hdr, &cnt, &len); + if (data && idx < cnt) { + data = data + *hdr + idx * len; + *hdr = len; + return data; + } + return 0x00000000; +} + +u32 +nvbios_M0205Sp(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr, + struct nvbios_M0205S *info) +{ + u32 data = nvbios_M0205Se(bios, ent, idx, ver, hdr); + memset(info, 0x00, sizeof(*info)); + switch (!!data * *ver) { + case 0x10: + info->data = nv_ro08(bios, data + 0x00); + return data; + default: + break; + } + return 0x00000000; +} diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/M0209.c b/drivers/gpu/drm/nouveau/core/subdev/bios/M0209.c new file mode 100644 index 000000000000..b142a510e89f --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/bios/M0209.c @@ -0,0 +1,137 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include <subdev/bios.h> +#include <subdev/bios/bit.h> +#include <subdev/bios/M0209.h> + +u32 +nvbios_M0209Te(struct nouveau_bios *bios, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz) +{ + struct bit_entry bit_M; + u32 data = 0x00000000; + + if (!bit_entry(bios, 'M', &bit_M)) { + if (bit_M.version == 2 && bit_M.length > 0x0c) + data = nv_ro32(bios, bit_M.offset + 0x09); + if (data) { + *ver = nv_ro08(bios, data + 0x00); + switch (*ver) { + case 0x10: + *hdr = nv_ro08(bios, data + 0x01); + *len = nv_ro08(bios, data + 0x02); + *ssz = nv_ro08(bios, data + 0x03); + *snr = 1; + *cnt = nv_ro08(bios, data + 0x04); + return data; + default: + break; + } + } + } + + return 0x00000000; +} + +u32 +nvbios_M0209Ee(struct nouveau_bios *bios, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +{ + u8 snr, ssz; + u32 data = nvbios_M0209Te(bios, ver, hdr, cnt, len, &snr, &ssz); + if (data && idx < *cnt) { + data = data + *hdr + idx * (*len + (snr * ssz)); + *hdr = *len; + *cnt = snr; + *len = ssz; + return data; + } + return 0x00000000; +} + +u32 +nvbios_M0209Ep(struct nouveau_bios *bios, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, + struct nvbios_M0209E *info) +{ + u32 data = nvbios_M0209Ee(bios, idx, ver, hdr, cnt, len); + memset(info, 0x00, sizeof(*info)); + switch (!!data * *ver) { + case 0x10: + info->v00_40 = (nv_ro08(bios, data + 0x00) & 0x40) >> 6; + info->bits = nv_ro08(bios, data + 0x00) & 0x3f; + info->modulo = nv_ro08(bios, data + 0x01); + info->v02_40 = (nv_ro08(bios, data + 0x02) & 0x40) >> 6; + info->v02_07 = nv_ro08(bios, data + 0x02) & 0x07; + info->v03 = nv_ro08(bios, data + 0x03); + return data; + default: + break; + } + return 0x00000000; +} + +u32 +nvbios_M0209Se(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr) +{ + + u8 cnt, len; + u32 data = nvbios_M0209Ee(bios, ent, ver, hdr, &cnt, &len); + if (data && idx < cnt) { + data = data + *hdr + idx * len; + *hdr = len; + return data; + } + return 0x00000000; +} + +u32 +nvbios_M0209Sp(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr, + struct nvbios_M0209S *info) +{ + struct nvbios_M0209E M0209E; + u8 cnt, len; + u32 data = nvbios_M0209Ep(bios, ent, ver, hdr, &cnt, &len, &M0209E); + if (data) { + u32 i, data = nvbios_M0209Se(bios, ent, idx, ver, hdr); + memset(info, 0x00, sizeof(*info)); + switch (!!data * *ver) { + case 0x10: + for (i = 0; i < ARRAY_SIZE(info->data); i++) { + u32 bits = (i % M0209E.modulo) * M0209E.bits; + u32 mask = (1ULL << M0209E.bits) - 1; + u16 off = bits / 8; + u8 mod = bits % 8; + info->data[i] = nv_ro32(bios, data + off); + info->data[i] = info->data[i] >> mod; + info->data[i] = info->data[i] & mask; + } + return data; + default: + break; + } + } + return 0x00000000; +} diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c b/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c index 88606bfaf847..bd8d348385b3 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c +++ b/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c @@ -124,6 +124,7 @@ dcb_outp_parse(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len, struct dcb_output *outp) { u16 dcb = dcb_outp(bios, idx, ver, len); + memset(outp, 0x00, sizeof(*outp)); if (dcb) { if (*ver >= 0x20) { u32 conn = nv_ro32(bios, dcb + 0x00); diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/fan.c b/drivers/gpu/drm/nouveau/core/subdev/bios/fan.c new file mode 100644 index 000000000000..e419892240f5 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/bios/fan.c @@ -0,0 +1,93 @@ +/* + * Copyright 2014 Martin Peres + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Martin Peres + */ + +#include <subdev/bios.h> +#include <subdev/bios/bit.h> +#include <subdev/bios/fan.h> + +u16 +nvbios_fan_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +{ + struct bit_entry bit_P; + u16 fan = 0x0000; + + if (!bit_entry(bios, 'P', &bit_P)) { + if (bit_P.version == 2 && bit_P.length >= 0x5a) + fan = nv_ro16(bios, bit_P.offset + 0x58); + + if (fan) { + *ver = nv_ro08(bios, fan + 0); + switch (*ver) { + case 0x10: + *hdr = nv_ro08(bios, fan + 1); + *len = nv_ro08(bios, fan + 2); + *cnt = nv_ro08(bios, fan + 3); + return fan; + default: + break; + } + } + } + + return 0x0000; +} + +u16 +nvbios_fan_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr, + u8 *cnt, u8 *len) +{ + u16 data = nvbios_fan_table(bios, ver, hdr, cnt, len); + if (data && idx < *cnt) + return data + *hdr + (idx * (*len)); + return 0x0000; +} + +u16 +nvbios_fan_parse(struct nouveau_bios *bios, struct nvbios_therm_fan *fan) +{ + u8 ver, hdr, cnt, len; + + u16 data = nvbios_fan_entry(bios, 0, &ver, &hdr, &cnt, &len); + if (data) { + u8 type = nv_ro08(bios, data + 0x00); + switch (type) { + case 0: + fan->type = NVBIOS_THERM_FAN_TOGGLE; + break; + case 1: + case 2: + /* TODO: Understand the difference between the two! */ + fan->type = NVBIOS_THERM_FAN_PWM; + break; + default: + fan->type = NVBIOS_THERM_FAN_UNK; + } + + fan->min_duty = nv_ro08(bios, data + 0x02); + fan->max_duty = nv_ro08(bios, data + 0x03); + + fan->pwm_freq = nv_ro32(bios, data + 0x0b) & 0xffffff; + } + return data; +} diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c b/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c index 1811b2cb0472..585e69331ccc 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c +++ b/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c @@ -75,31 +75,39 @@ nvbios_rammapEe(struct nouveau_bios *bios, int idx, } u32 -nvbios_rammapEm(struct nouveau_bios *bios, u16 khz, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len) -{ - int idx = 0; - u32 data; - while ((data = nvbios_rammapEe(bios, idx++, ver, hdr, cnt, len))) { - if (khz >= nv_ro16(bios, data + 0x00) && - khz <= nv_ro16(bios, data + 0x02)) - break; - } - return data; -} - -u32 -nvbios_rammapEp(struct nouveau_bios *bios, u16 khz, +nvbios_rammapEp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *p) { - u32 data = nvbios_rammapEm(bios, khz, ver, hdr, cnt, len); + u32 data = nvbios_rammapEe(bios, idx, ver, hdr, cnt, len), temp; memset(p, 0x00, sizeof(*p)); + p->rammap_ver = *ver; + p->rammap_hdr = *hdr; switch (!!data * *ver) { + case 0x10: + p->rammap_min = nv_ro16(bios, data + 0x00); + p->rammap_max = nv_ro16(bios, data + 0x02); + p->rammap_10_04_02 = (nv_ro08(bios, data + 0x04) & 0x02) >> 1; + p->rammap_10_04_08 = (nv_ro08(bios, data + 0x04) & 0x08) >> 3; + break; case 0x11: + p->rammap_min = nv_ro16(bios, data + 0x00); + p->rammap_max = nv_ro16(bios, data + 0x02); p->rammap_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0; p->rammap_11_08_0c = (nv_ro08(bios, data + 0x08) & 0x0c) >> 2; p->rammap_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4; + temp = nv_ro32(bios, data + 0x09); + p->rammap_11_09_01ff = (temp & 0x000001ff) >> 0; + p->rammap_11_0a_03fe = (temp & 0x0003fe00) >> 9; + p->rammap_11_0a_0400 = (temp & 0x00040000) >> 18; + p->rammap_11_0a_0800 = (temp & 0x00080000) >> 19; + p->rammap_11_0b_01f0 = (temp & 0x01f00000) >> 20; + p->rammap_11_0b_0200 = (temp & 0x02000000) >> 25; + p->rammap_11_0b_0400 = (temp & 0x04000000) >> 26; + p->rammap_11_0b_0800 = (temp & 0x08000000) >> 27; + p->rammap_11_0d = nv_ro08(bios, data + 0x0d); + p->rammap_11_0e = nv_ro08(bios, data + 0x0e); + p->rammap_11_0f = nv_ro08(bios, data + 0x0f); p->rammap_11_11_0c = (nv_ro08(bios, data + 0x11) & 0x0c) >> 2; break; default: @@ -110,6 +118,20 @@ nvbios_rammapEp(struct nouveau_bios *bios, u16 khz, } u32 +nvbios_rammapEm(struct nouveau_bios *bios, u16 mhz, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, + struct nvbios_ramcfg *info) +{ + int idx = 0; + u32 data; + while ((data = nvbios_rammapEp(bios, idx++, ver, hdr, cnt, len, info))) { + if (mhz >= info->rammap_min && mhz <= info->rammap_max) + break; + } + return data; +} + +u32 nvbios_rammapSe(struct nouveau_bios *bios, u32 data, u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, u8 *ver, u8 *hdr) @@ -129,8 +151,28 @@ nvbios_rammapSp(struct nouveau_bios *bios, u32 data, u8 *ver, u8 *hdr, struct nvbios_ramcfg *p) { data = nvbios_rammapSe(bios, data, ever, ehdr, ecnt, elen, idx, ver, hdr); + p->ramcfg_ver = *ver; + p->ramcfg_hdr = *hdr; switch (!!data * *ver) { + case 0x10: + p->ramcfg_timing = nv_ro08(bios, data + 0x01); + p->ramcfg_10_02_01 = (nv_ro08(bios, data + 0x02) & 0x01) >> 0; + p->ramcfg_10_02_02 = (nv_ro08(bios, data + 0x02) & 0x02) >> 1; + p->ramcfg_10_02_04 = (nv_ro08(bios, data + 0x02) & 0x04) >> 2; + p->ramcfg_10_02_08 = (nv_ro08(bios, data + 0x02) & 0x08) >> 3; + p->ramcfg_10_02_10 = (nv_ro08(bios, data + 0x02) & 0x10) >> 4; + p->ramcfg_10_02_20 = (nv_ro08(bios, data + 0x02) & 0x20) >> 5; + p->ramcfg_10_02_40 = (nv_ro08(bios, data + 0x02) & 0x40) >> 6; + p->ramcfg_10_03_0f = (nv_ro08(bios, data + 0x03) & 0x0f) >> 0; + p->ramcfg_10_05 = (nv_ro08(bios, data + 0x05) & 0xff) >> 0; + p->ramcfg_10_06 = (nv_ro08(bios, data + 0x06) & 0xff) >> 0; + p->ramcfg_10_07 = (nv_ro08(bios, data + 0x07) & 0xff) >> 0; + p->ramcfg_10_08 = (nv_ro08(bios, data + 0x08) & 0xff) >> 0; + p->ramcfg_10_09_0f = (nv_ro08(bios, data + 0x09) & 0x0f) >> 0; + p->ramcfg_10_09_f0 = (nv_ro08(bios, data + 0x09) & 0xf0) >> 4; + break; case 0x11: + p->ramcfg_timing = nv_ro08(bios, data + 0x00); p->ramcfg_11_01_01 = (nv_ro08(bios, data + 0x01) & 0x01) >> 0; p->ramcfg_11_01_02 = (nv_ro08(bios, data + 0x01) & 0x02) >> 1; p->ramcfg_11_01_04 = (nv_ro08(bios, data + 0x01) & 0x04) >> 2; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c b/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c index 350d44ab2ba2..46d955eb51eb 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c +++ b/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c @@ -89,7 +89,15 @@ nvbios_timingEp(struct nouveau_bios *bios, int idx, struct nvbios_ramcfg *p) { u16 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp; + p->timing_ver = *ver; + p->timing_hdr = *hdr; switch (!!data * *ver) { + case 0x10: + p->timing_10_WR = nv_ro08(bios, data + 0x00); + p->timing_10_CL = nv_ro08(bios, data + 0x02); + p->timing_10_ODT = nv_ro08(bios, data + 0x0e) & 0x07; + p->timing_10_CWL = nv_ro08(bios, data + 0x13); + break; case 0x20: p->timing[0] = nv_ro32(bios, data + 0x00); p->timing[1] = nv_ro32(bios, data + 0x04); diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c b/drivers/gpu/drm/nouveau/core/subdev/clock/base.c index 22351f594d2a..e51b72d47129 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/base.c @@ -90,16 +90,20 @@ nouveau_cstate_prog(struct nouveau_clock *clk, cstate = &pstate->base; } - ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, +1); - if (ret && ret != -ENODEV) { - nv_error(clk, "failed to raise fan speed: %d\n", ret); - return ret; + if (ptherm) { + ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, +1); + if (ret && ret != -ENODEV) { + nv_error(clk, "failed to raise fan speed: %d\n", ret); + return ret; + } } - ret = volt->set_id(volt, cstate->voltage, +1); - if (ret && ret != -ENODEV) { - nv_error(clk, "failed to raise voltage: %d\n", ret); - return ret; + if (volt) { + ret = volt->set_id(volt, cstate->voltage, +1); + if (ret && ret != -ENODEV) { + nv_error(clk, "failed to raise voltage: %d\n", ret); + return ret; + } } ret = clk->calc(clk, cstate); @@ -108,13 +112,17 @@ nouveau_cstate_prog(struct nouveau_clock *clk, clk->tidy(clk); } - ret = volt->set_id(volt, cstate->voltage, -1); - if (ret && ret != -ENODEV) - nv_error(clk, "failed to lower voltage: %d\n", ret); + if (volt) { + ret = volt->set_id(volt, cstate->voltage, -1); + if (ret && ret != -ENODEV) + nv_error(clk, "failed to lower voltage: %d\n", ret); + } - ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, -1); - if (ret && ret != -ENODEV) - nv_error(clk, "failed to lower fan speed: %d\n", ret); + if (ptherm) { + ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, -1); + if (ret && ret != -ENODEV) + nv_error(clk, "failed to lower fan speed: %d\n", ret); + } return 0; } @@ -194,16 +202,23 @@ nouveau_pstate_prog(struct nouveau_clock *clk, int pstatei) return nouveau_cstate_prog(clk, pstate, 0); } -static int -nouveau_pstate_calc(struct nouveau_clock *clk) +static void +nouveau_pstate_work(struct work_struct *work) { - int pstate, ret = 0; + struct nouveau_clock *clk = container_of(work, typeof(*clk), work); + int pstate; - nv_trace(clk, "P %d U %d A %d T %d D %d\n", clk->pstate, - clk->ustate, clk->astate, clk->tstate, clk->dstate); + if (!atomic_xchg(&clk->waiting, 0)) + return; + clk->pwrsrc = power_supply_is_system_supplied(); - if (clk->state_nr && clk->ustate != -1) { - pstate = (clk->ustate < 0) ? clk->astate : clk->ustate; + nv_trace(clk, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n", + clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc, + clk->astate, clk->tstate, clk->dstate); + + pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc; + if (clk->state_nr && pstate != -1) { + pstate = (pstate < 0) ? clk->astate : pstate; pstate = min(pstate, clk->state_nr - 1 - clk->tstate); pstate = max(pstate, clk->dstate); } else { @@ -211,9 +226,26 @@ nouveau_pstate_calc(struct nouveau_clock *clk) } nv_trace(clk, "-> %d\n", pstate); - if (pstate != clk->pstate) - ret = nouveau_pstate_prog(clk, pstate); - return ret; + if (pstate != clk->pstate) { + int ret = nouveau_pstate_prog(clk, pstate); + if (ret) { + nv_error(clk, "error setting pstate %d: %d\n", + pstate, ret); + } + } + + wake_up_all(&clk->wait); + nvkm_notify_get(&clk->pwrsrc_ntfy); +} + +static int +nouveau_pstate_calc(struct nouveau_clock *clk, bool wait) +{ + atomic_set(&clk->waiting, 1); + schedule_work(&clk->work); + if (wait) + wait_event(clk->wait, !atomic_read(&clk->waiting)); + return 0; } static void @@ -361,17 +393,40 @@ nouveau_clock_ustate_update(struct nouveau_clock *clk, int req) req = i; } - clk->ustate = req; - return 0; + return req + 2; +} + +static int +nouveau_clock_nstate(struct nouveau_clock *clk, const char *mode, int arglen) +{ + int ret = 1; + + if (strncasecmpz(mode, "disabled", arglen)) { + char save = mode[arglen]; + long v; + + ((char *)mode)[arglen] = '\0'; + if (!kstrtol(mode, 0, &v)) { + ret = nouveau_clock_ustate_update(clk, v); + if (ret < 0) + ret = 1; + } + ((char *)mode)[arglen] = save; + } + + return ret - 2; } int -nouveau_clock_ustate(struct nouveau_clock *clk, int req) +nouveau_clock_ustate(struct nouveau_clock *clk, int req, int pwr) { int ret = nouveau_clock_ustate_update(clk, req); - if (ret) - return ret; - return nouveau_pstate_calc(clk); + if (ret >= 0) { + if (ret -= 2, pwr) clk->ustate_ac = ret; + else clk->ustate_dc = ret; + return nouveau_pstate_calc(clk, true); + } + return ret; } int @@ -381,7 +436,7 @@ nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel) if ( rel) clk->astate += rel; clk->astate = min(clk->astate, clk->state_nr - 1); clk->astate = max(clk->astate, 0); - return nouveau_pstate_calc(clk); + return nouveau_pstate_calc(clk, true); } int @@ -391,7 +446,7 @@ nouveau_clock_tstate(struct nouveau_clock *clk, int req, int rel) if ( rel) clk->tstate += rel; clk->tstate = min(clk->tstate, 0); clk->tstate = max(clk->tstate, -(clk->state_nr - 1)); - return nouveau_pstate_calc(clk); + return nouveau_pstate_calc(clk, true); } int @@ -401,12 +456,30 @@ nouveau_clock_dstate(struct nouveau_clock *clk, int req, int rel) if ( rel) clk->dstate += rel; clk->dstate = min(clk->dstate, clk->state_nr - 1); clk->dstate = max(clk->dstate, 0); - return nouveau_pstate_calc(clk); + return nouveau_pstate_calc(clk, true); +} + +static int +nouveau_clock_pwrsrc(struct nvkm_notify *notify) +{ + struct nouveau_clock *clk = + container_of(notify, typeof(*clk), pwrsrc_ntfy); + nouveau_pstate_calc(clk, false); + return NVKM_NOTIFY_DROP; } /****************************************************************************** * subdev base class implementation *****************************************************************************/ + +int +_nouveau_clock_fini(struct nouveau_object *object, bool suspend) +{ + struct nouveau_clock *clk = (void *)object; + nvkm_notify_put(&clk->pwrsrc_ntfy); + return nouveau_subdev_fini(&clk->base, suspend); +} + int _nouveau_clock_init(struct nouveau_object *object) { @@ -414,6 +487,10 @@ _nouveau_clock_init(struct nouveau_object *object) struct nouveau_clocks *clock = clk->domains; int ret; + ret = nouveau_subdev_init(&clk->base); + if (ret) + return ret; + memset(&clk->bstate, 0x00, sizeof(clk->bstate)); INIT_LIST_HEAD(&clk->bstate.list); clk->bstate.pstate = 0xff; @@ -434,7 +511,7 @@ _nouveau_clock_init(struct nouveau_object *object) clk->tstate = 0; clk->dstate = 0; clk->pstate = -1; - nouveau_pstate_calc(clk); + nouveau_pstate_calc(clk, true); return 0; } @@ -444,6 +521,8 @@ _nouveau_clock_dtor(struct nouveau_object *object) struct nouveau_clock *clk = (void *)object; struct nouveau_pstate *pstate, *temp; + nvkm_notify_fini(&clk->pwrsrc_ntfy); + list_for_each_entry_safe(pstate, temp, &clk->states, head) { nouveau_pstate_del(pstate); } @@ -456,6 +535,7 @@ nouveau_clock_create_(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, struct nouveau_clocks *clocks, + struct nouveau_pstate *pstates, int nb_pstates, bool allow_reclock, int length, void **object) { @@ -472,29 +552,46 @@ nouveau_clock_create_(struct nouveau_object *parent, INIT_LIST_HEAD(&clk->states); clk->domains = clocks; - clk->ustate = -1; + clk->ustate_ac = -1; + clk->ustate_dc = -1; + + INIT_WORK(&clk->work, nouveau_pstate_work); + init_waitqueue_head(&clk->wait); + atomic_set(&clk->waiting, 0); - idx = 0; - do { - ret = nouveau_pstate_new(clk, idx++); - } while (ret == 0); + /* If no pstates are provided, try and fetch them from the BIOS */ + if (!pstates) { + idx = 0; + do { + ret = nouveau_pstate_new(clk, idx++); + } while (ret == 0); + } else { + for (idx = 0; idx < nb_pstates; idx++) + list_add_tail(&pstates[idx].head, &clk->states); + clk->state_nr = nb_pstates; + } clk->allow_reclock = allow_reclock; + ret = nvkm_notify_init(NULL, &device->event, nouveau_clock_pwrsrc, true, + NULL, 0, 0, &clk->pwrsrc_ntfy); + if (ret) + return ret; + mode = nouveau_stropt(device->cfgopt, "NvClkMode", &arglen); if (mode) { - if (!strncasecmpz(mode, "disabled", arglen)) { - clk->ustate = -1; - } else { - char save = mode[arglen]; - long v; - - ((char *)mode)[arglen] = '\0'; - if (!kstrtol(mode, 0, &v)) - nouveau_clock_ustate_update(clk, v); - ((char *)mode)[arglen] = save; - } + clk->ustate_ac = nouveau_clock_nstate(clk, mode, arglen); + clk->ustate_dc = nouveau_clock_nstate(clk, mode, arglen); } + mode = nouveau_stropt(device->cfgopt, "NvClkModeAC", &arglen); + if (mode) + clk->ustate_ac = nouveau_clock_nstate(clk, mode, arglen); + + mode = nouveau_stropt(device->cfgopt, "NvClkModeDC", &arglen); + if (mode) + clk->ustate_dc = nouveau_clock_nstate(clk, mode, arglen); + + return 0; } diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c b/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c new file mode 100644 index 000000000000..425a8d5e9129 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c @@ -0,0 +1,665 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c + * + */ + +#define MHZ (1000 * 1000) + +#define MASK(w) ((1 << w) - 1) + +#define SYS_GPCPLL_CFG_BASE 0x00137000 +#define GPC_BCASE_GPCPLL_CFG_BASE 0x00132800 + +#define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0) +#define GPCPLL_CFG_ENABLE BIT(0) +#define GPCPLL_CFG_IDDQ BIT(1) +#define GPCPLL_CFG_LOCK_DET_OFF BIT(4) +#define GPCPLL_CFG_LOCK BIT(17) + +#define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4) +#define GPCPLL_COEFF_M_SHIFT 0 +#define GPCPLL_COEFF_M_WIDTH 8 +#define GPCPLL_COEFF_N_SHIFT 8 +#define GPCPLL_COEFF_N_WIDTH 8 +#define GPCPLL_COEFF_P_SHIFT 16 +#define GPCPLL_COEFF_P_WIDTH 6 + +#define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc) +#define GPCPLL_CFG2_SETUP2_SHIFT 16 +#define GPCPLL_CFG2_PLL_STEPA_SHIFT 24 + +#define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18) +#define GPCPLL_CFG3_PLL_STEPB_SHIFT 16 + +#define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c) +#define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT 0 +#define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 8 +#define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT 16 +#define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 22 +#define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 31 + +#define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100) +#define SEL_VCO_GPC2CLK_OUT_SHIFT 0 + +#define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250) +#define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 1 +#define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31 +#define GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define GPC2CLK_OUT_VCODIV_WIDTH 6 +#define GPC2CLK_OUT_VCODIV_SHIFT 8 +#define GPC2CLK_OUT_VCODIV1 0 +#define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \ + GPC2CLK_OUT_VCODIV_SHIFT) +#define GPC2CLK_OUT_BYPDIV_WIDTH 6 +#define GPC2CLK_OUT_BYPDIV_SHIFT 0 +#define GPC2CLK_OUT_BYPDIV31 0x3c +#define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \ + GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\ + | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\ + | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT)) +#define GPC2CLK_OUT_INIT_VAL ((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \ + GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \ + | (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \ + | (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT)) + +#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG (GPC_BCASE_GPCPLL_CFG_BASE + 0xa0) +#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 24 +#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \ + (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT) + +#include <subdev/clock.h> +#include <subdev/timer.h> + +#ifdef __KERNEL__ +#include <nouveau_platform.h> +#endif + +static const u8 pl_to_div[] = { +/* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ +/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32, +}; + +/* All frequencies in Mhz */ +struct gk20a_clk_pllg_params { + u32 min_vco, max_vco; + u32 min_u, max_u; + u32 min_m, max_m; + u32 min_n, max_n; + u32 min_pl, max_pl; +}; + +static const struct gk20a_clk_pllg_params gk20a_pllg_params = { + .min_vco = 1000, .max_vco = 1700, + .min_u = 12, .max_u = 38, + .min_m = 1, .max_m = 255, + .min_n = 8, .max_n = 255, + .min_pl = 1, .max_pl = 32, +}; + +struct gk20a_clock_priv { + struct nouveau_clock base; + const struct gk20a_clk_pllg_params *params; + u32 m, n, pl; + u32 parent_rate; +}; +#define to_gk20a_clock(base) container_of(base, struct gk20a_clock_priv, base) + +static void +gk20a_pllg_read_mnp(struct gk20a_clock_priv *priv) +{ + u32 val; + + val = nv_rd32(priv, GPCPLL_COEFF); + priv->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); + priv->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); + priv->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); +} + +static u32 +gk20a_pllg_calc_rate(struct gk20a_clock_priv *priv) +{ + u32 rate; + u32 divider; + + rate = priv->parent_rate * priv->n; + divider = priv->m * pl_to_div[priv->pl]; + do_div(rate, divider); + + return rate / 2; +} + +static int +gk20a_pllg_calc_mnp(struct gk20a_clock_priv *priv, unsigned long rate) +{ + u32 target_clk_f, ref_clk_f, target_freq; + u32 min_vco_f, max_vco_f; + u32 low_pl, high_pl, best_pl; + u32 target_vco_f, vco_f; + u32 best_m, best_n; + u32 u_f; + u32 m, n, n2; + u32 delta, lwv, best_delta = ~0; + u32 pl; + + target_clk_f = rate * 2 / MHZ; + ref_clk_f = priv->parent_rate / MHZ; + + max_vco_f = priv->params->max_vco; + min_vco_f = priv->params->min_vco; + best_m = priv->params->max_m; + best_n = priv->params->min_n; + best_pl = priv->params->min_pl; + + target_vco_f = target_clk_f + target_clk_f / 50; + if (max_vco_f < target_vco_f) + max_vco_f = target_vco_f; + + /* min_pl <= high_pl <= max_pl */ + high_pl = (max_vco_f + target_vco_f - 1) / target_vco_f; + high_pl = min(high_pl, priv->params->max_pl); + high_pl = max(high_pl, priv->params->min_pl); + + /* min_pl <= low_pl <= max_pl */ + low_pl = min_vco_f / target_vco_f; + low_pl = min(low_pl, priv->params->max_pl); + low_pl = max(low_pl, priv->params->min_pl); + + /* Find Indices of high_pl and low_pl */ + for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) { + if (pl_to_div[pl] >= low_pl) { + low_pl = pl; + break; + } + } + for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) { + if (pl_to_div[pl] >= high_pl) { + high_pl = pl; + break; + } + } + + nv_debug(priv, "low_PL %d(div%d), high_PL %d(div%d)", low_pl, + pl_to_div[low_pl], high_pl, pl_to_div[high_pl]); + + /* Select lowest possible VCO */ + for (pl = low_pl; pl <= high_pl; pl++) { + target_vco_f = target_clk_f * pl_to_div[pl]; + for (m = priv->params->min_m; m <= priv->params->max_m; m++) { + u_f = ref_clk_f / m; + + if (u_f < priv->params->min_u) + break; + if (u_f > priv->params->max_u) + continue; + + n = (target_vco_f * m) / ref_clk_f; + n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f; + + if (n > priv->params->max_n) + break; + + for (; n <= n2; n++) { + if (n < priv->params->min_n) + continue; + if (n > priv->params->max_n) + break; + + vco_f = ref_clk_f * n / m; + + if (vco_f >= min_vco_f && vco_f <= max_vco_f) { + lwv = (vco_f + (pl_to_div[pl] / 2)) + / pl_to_div[pl]; + delta = abs(lwv - target_clk_f); + + if (delta < best_delta) { + best_delta = delta; + best_m = m; + best_n = n; + best_pl = pl; + + if (best_delta == 0) + goto found_match; + } + } + } + } + } + +found_match: + WARN_ON(best_delta == ~0); + + if (best_delta != 0) + nv_debug(priv, "no best match for target @ %dMHz on gpc_pll", + target_clk_f); + + priv->m = best_m; + priv->n = best_n; + priv->pl = best_pl; + + target_freq = gk20a_pllg_calc_rate(priv) / MHZ; + + nv_debug(priv, "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n", + target_freq, priv->m, priv->n, priv->pl, pl_to_div[priv->pl]); + + return 0; +} + +static int +gk20a_pllg_slide(struct gk20a_clock_priv *priv, u32 n) +{ + u32 val; + int ramp_timeout; + + /* get old coefficients */ + val = nv_rd32(priv, GPCPLL_COEFF); + /* do nothing if NDIV is the same */ + if (n == ((val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH))) + return 0; + + /* setup */ + nv_mask(priv, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT, + 0x2b << GPCPLL_CFG2_PLL_STEPA_SHIFT); + nv_mask(priv, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT, + 0xb << GPCPLL_CFG3_PLL_STEPB_SHIFT); + + /* pll slowdown mode */ + nv_mask(priv, GPCPLL_NDIV_SLOWDOWN, + BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT), + BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT)); + + /* new ndiv ready for ramp */ + val = nv_rd32(priv, GPCPLL_COEFF); + val &= ~(MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT); + val |= (n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT; + udelay(1); + nv_wr32(priv, GPCPLL_COEFF, val); + + /* dynamic ramp to new ndiv */ + val = nv_rd32(priv, GPCPLL_NDIV_SLOWDOWN); + val |= 0x1 << GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT; + udelay(1); + nv_wr32(priv, GPCPLL_NDIV_SLOWDOWN, val); + + for (ramp_timeout = 500; ramp_timeout > 0; ramp_timeout--) { + udelay(1); + val = nv_rd32(priv, GPC_BCAST_NDIV_SLOWDOWN_DEBUG); + if (val & GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK) + break; + } + + /* exit slowdown mode */ + nv_mask(priv, GPCPLL_NDIV_SLOWDOWN, + BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT) | + BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 0); + nv_rd32(priv, GPCPLL_NDIV_SLOWDOWN); + + if (ramp_timeout <= 0) { + nv_error(priv, "gpcpll dynamic ramp timeout\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static void +_gk20a_pllg_enable(struct gk20a_clock_priv *priv) +{ + nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE); + nv_rd32(priv, GPCPLL_CFG); +} + +static void +_gk20a_pllg_disable(struct gk20a_clock_priv *priv) +{ + nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0); + nv_rd32(priv, GPCPLL_CFG); +} + +static int +_gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv, bool allow_slide) +{ + u32 val, cfg; + u32 m_old, pl_old, n_lo; + + /* get old coefficients */ + val = nv_rd32(priv, GPCPLL_COEFF); + m_old = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); + pl_old = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); + + /* do NDIV slide if there is no change in M and PL */ + cfg = nv_rd32(priv, GPCPLL_CFG); + if (allow_slide && priv->m == m_old && priv->pl == pl_old && + (cfg & GPCPLL_CFG_ENABLE)) { + return gk20a_pllg_slide(priv, priv->n); + } + + /* slide down to NDIV_LO */ + n_lo = DIV_ROUND_UP(m_old * priv->params->min_vco, + priv->parent_rate / MHZ); + if (allow_slide && (cfg & GPCPLL_CFG_ENABLE)) { + int ret = gk20a_pllg_slide(priv, n_lo); + + if (ret) + return ret; + } + + /* split FO-to-bypass jump in halfs by setting out divider 1:2 */ + nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK, + 0x2 << GPC2CLK_OUT_VCODIV_SHIFT); + + /* put PLL in bypass before programming it */ + val = nv_rd32(priv, SEL_VCO); + val &= ~(BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); + udelay(2); + nv_wr32(priv, SEL_VCO, val); + + /* get out from IDDQ */ + val = nv_rd32(priv, GPCPLL_CFG); + if (val & GPCPLL_CFG_IDDQ) { + val &= ~GPCPLL_CFG_IDDQ; + nv_wr32(priv, GPCPLL_CFG, val); + nv_rd32(priv, GPCPLL_CFG); + udelay(2); + } + + _gk20a_pllg_disable(priv); + + nv_debug(priv, "%s: m=%d n=%d pl=%d\n", __func__, priv->m, priv->n, + priv->pl); + + n_lo = DIV_ROUND_UP(priv->m * priv->params->min_vco, + priv->parent_rate / MHZ); + val = priv->m << GPCPLL_COEFF_M_SHIFT; + val |= (allow_slide ? n_lo : priv->n) << GPCPLL_COEFF_N_SHIFT; + val |= priv->pl << GPCPLL_COEFF_P_SHIFT; + nv_wr32(priv, GPCPLL_COEFF, val); + + _gk20a_pllg_enable(priv); + + val = nv_rd32(priv, GPCPLL_CFG); + if (val & GPCPLL_CFG_LOCK_DET_OFF) { + val &= ~GPCPLL_CFG_LOCK_DET_OFF; + nv_wr32(priv, GPCPLL_CFG, val); + } + + if (!nouveau_timer_wait_eq(priv, 300000, GPCPLL_CFG, GPCPLL_CFG_LOCK, + GPCPLL_CFG_LOCK)) { + nv_error(priv, "%s: timeout waiting for pllg lock\n", __func__); + return -ETIMEDOUT; + } + + /* switch to VCO mode */ + nv_mask(priv, SEL_VCO, 0, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); + + /* restore out divider 1:1 */ + val = nv_rd32(priv, GPC2CLK_OUT); + val &= ~GPC2CLK_OUT_VCODIV_MASK; + udelay(2); + nv_wr32(priv, GPC2CLK_OUT, val); + + /* slide up to new NDIV */ + return allow_slide ? gk20a_pllg_slide(priv, priv->n) : 0; +} + +static int +gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv) +{ + int err; + + err = _gk20a_pllg_program_mnp(priv, true); + if (err) + err = _gk20a_pllg_program_mnp(priv, false); + + return err; +} + +static void +gk20a_pllg_disable(struct gk20a_clock_priv *priv) +{ + u32 val; + + /* slide to VCO min */ + val = nv_rd32(priv, GPCPLL_CFG); + if (val & GPCPLL_CFG_ENABLE) { + u32 coeff, m, n_lo; + + coeff = nv_rd32(priv, GPCPLL_COEFF); + m = (coeff >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); + n_lo = DIV_ROUND_UP(m * priv->params->min_vco, + priv->parent_rate / MHZ); + gk20a_pllg_slide(priv, n_lo); + } + + /* put PLL in bypass before disabling it */ + nv_mask(priv, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); + + _gk20a_pllg_disable(priv); +} + +#define GK20A_CLK_GPC_MDIV 1000 + +static struct nouveau_clocks +gk20a_domains[] = { + { nv_clk_src_crystal, 0xff }, + { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV }, + { nv_clk_src_max } +}; + +static struct nouveau_pstate +gk20a_pstates[] = { + { + .base = { + .domain[nv_clk_src_gpc] = 72000, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 108000, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 180000, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 252000, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 324000, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 396000, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 468000, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 540000, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 612000, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 648000, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 684000, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 708000, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 756000, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 804000, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 852000, + }, + }, +}; + +static int +gk20a_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) +{ + struct gk20a_clock_priv *priv = (void *)clk; + + switch (src) { + case nv_clk_src_crystal: + return nv_device(clk)->crystal; + case nv_clk_src_gpc: + gk20a_pllg_read_mnp(priv); + return gk20a_pllg_calc_rate(priv) / GK20A_CLK_GPC_MDIV; + default: + nv_error(clk, "invalid clock source %d\n", src); + return -EINVAL; + } +} + +static int +gk20a_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) +{ + struct gk20a_clock_priv *priv = (void *)clk; + + return gk20a_pllg_calc_mnp(priv, cstate->domain[nv_clk_src_gpc] * + GK20A_CLK_GPC_MDIV); +} + +static int +gk20a_clock_prog(struct nouveau_clock *clk) +{ + struct gk20a_clock_priv *priv = (void *)clk; + + return gk20a_pllg_program_mnp(priv); +} + +static void +gk20a_clock_tidy(struct nouveau_clock *clk) +{ +} + +static int +gk20a_clock_fini(struct nouveau_object *object, bool suspend) +{ + struct gk20a_clock_priv *priv = (void *)object; + int ret; + + ret = nouveau_clock_fini(&priv->base, false); + + gk20a_pllg_disable(priv); + + return ret; +} + +static int +gk20a_clock_init(struct nouveau_object *object) +{ + struct gk20a_clock_priv *priv = (void *)object; + int ret; + + nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL); + + ret = nouveau_clock_init(&priv->base); + if (ret) + return ret; + + ret = gk20a_clock_prog(&priv->base); + if (ret) { + nv_error(priv, "cannot initialize clock\n"); + return ret; + } + + return 0; +} + +static int +gk20a_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct gk20a_clock_priv *priv; + struct nouveau_platform_device *plat; + int ret; + int i; + + /* Finish initializing the pstates */ + for (i = 0; i < ARRAY_SIZE(gk20a_pstates); i++) { + INIT_LIST_HEAD(&gk20a_pstates[i].list); + gk20a_pstates[i].pstate = i + 1; + } + + ret = nouveau_clock_create(parent, engine, oclass, gk20a_domains, + gk20a_pstates, ARRAY_SIZE(gk20a_pstates), true, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + priv->params = &gk20a_pllg_params; + + plat = nv_device_to_platform(nv_device(parent)); + priv->parent_rate = clk_get_rate(plat->gpu->clk); + nv_info(priv, "parent clock rate: %d Mhz\n", priv->parent_rate / MHZ); + + priv->base.read = gk20a_clock_read; + priv->base.calc = gk20a_clock_calc; + priv->base.prog = gk20a_clock_prog; + priv->base.tidy = gk20a_clock_tidy; + + return 0; +} + +struct nouveau_oclass +gk20a_clock_oclass = { + .handle = NV_SUBDEV(CLOCK, 0xea), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = gk20a_clock_ctor, + .dtor = _nouveau_subdev_dtor, + .init = gk20a_clock_init, + .fini = gk20a_clock_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c index eb2d4425a49e..4c48232686be 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c @@ -82,8 +82,8 @@ nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nv04_clock_priv *priv; int ret; - ret = nouveau_clock_create(parent, engine, oclass, nv04_domain, false, - &priv); + ret = nouveau_clock_create(parent, engine, oclass, nv04_domain, NULL, 0, + false, &priv); *pobject = nv_object(priv); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c index 8a9e16839791..08368fe97029 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c @@ -213,8 +213,8 @@ nv40_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nv40_clock_priv *priv; int ret; - ret = nouveau_clock_create(parent, engine, oclass, nv40_domain, true, - &priv); + ret = nouveau_clock_create(parent, engine, oclass, nv40_domain, NULL, 0, + true, &priv); *pobject = nv_object(priv); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c index 8c132772ba9e..5070ebc260f8 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c @@ -507,7 +507,7 @@ nv50_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, int ret; ret = nouveau_clock_create(parent, engine, oclass, pclass->domains, - false, &priv); + NULL, 0, false, &priv); *pobject = nv_object(priv); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c index 9fb58354a80b..094551d8ad9b 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c @@ -20,8 +20,10 @@ * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Ben Skeggs + * Roy Spliet */ +#include <engine/fifo.h> #include <subdev/bios.h> #include <subdev/bios/pll.h> #include <subdev/timer.h> @@ -42,9 +44,17 @@ static u32 read_vco(struct nva3_clock_priv *priv, int clk) { u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4)); - if ((sctl & 0x00000030) != 0x00000030) + + switch (sctl & 0x00000030) { + case 0x00000000: + return nv_device(priv)->crystal; + case 0x00000020: return read_pll(priv, 0x41, 0x00e820); - return read_pll(priv, 0x42, 0x00e8a0); + case 0x00000030: + return read_pll(priv, 0x42, 0x00e8a0); + default: + return 0; + } } static u32 @@ -66,14 +76,25 @@ read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en) if (!ignore_en && !(sctl & 0x00000100)) return 0; + /* out_alt */ + if (sctl & 0x00000400) + return 108000; + + /* vco_out */ switch (sctl & 0x00003000) { case 0x00000000: - return nv_device(priv)->crystal; + if (!(sctl & 0x00000200)) + return nv_device(priv)->crystal; + return 0; case 0x00002000: if (sctl & 0x00000040) return 108000; return 100000; case 0x00003000: + /* vco_enable */ + if (!(sctl & 0x00000001)) + return 0; + sclk = read_vco(priv, clk); sdiv = ((sctl & 0x003f0000) >> 16) + 2; return (sclk * 2) / sdiv; @@ -95,7 +116,9 @@ read_pll(struct nva3_clock_priv *priv, int clk, u32 pll) N = (coef & 0x0000ff00) >> 8; P = (coef & 0x003f0000) >> 16; - /* no post-divider on these.. */ + /* no post-divider on these.. + * XXX: it looks more like two post-"dividers" that + * cross each other out in the default RPLL config */ if ((pll & 0x00ff00) == 0x00e800) P = 1; @@ -114,13 +137,13 @@ static int nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) { struct nva3_clock_priv *priv = (void *)clk; + u32 hsrc; switch (src) { case nv_clk_src_crystal: return nv_device(priv)->crystal; - case nv_clk_src_href: - return 100000; case nv_clk_src_core: + case nv_clk_src_core_intm: return read_pll(priv, 0x00, 0x4200); case nv_clk_src_shader: return read_pll(priv, 0x01, 0x4220); @@ -132,24 +155,33 @@ nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) return read_clk(priv, 0x21, false); case nv_clk_src_daemon: return read_clk(priv, 0x25, false); + case nv_clk_src_host: + hsrc = (nv_rd32(priv, 0xc040) & 0x30000000) >> 28; + switch (hsrc) { + case 0: + return read_clk(priv, 0x1d, false); + case 2: + case 3: + return 277000; + default: + nv_error(clk, "unknown HOST clock source %d\n", hsrc); + return -EINVAL; + } default: nv_error(clk, "invalid clock source %d\n", src); return -EINVAL; } + + return 0; } int -nva3_clock_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz, +nva3_clk_info(struct nouveau_clock *clock, int clk, u32 khz, struct nva3_clock_info *info) { - struct nouveau_bios *bios = nouveau_bios(clock); struct nva3_clock_priv *priv = (void *)clock; - struct nvbios_pll limits; - u32 oclk, sclk, sdiv; - int P, N, M, diff; - int ret; + u32 oclk, sclk, sdiv, diff; - info->pll = 0; info->clk = 0; switch (khz) { @@ -164,43 +196,69 @@ nva3_clock_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz, return khz; default: sclk = read_vco(priv, clk); - sdiv = min((sclk * 2) / (khz - 2999), (u32)65); - /* if the clock has a PLL attached, and we can get a within - * [-2, 3) MHz of a divider, we'll disable the PLL and use - * the divider instead. - * - * divider can go as low as 2, limited here because NVIDIA + sdiv = min((sclk * 2) / khz, (u32)65); + oclk = (sclk * 2) / sdiv; + diff = ((khz + 3000) - oclk); + + /* When imprecise, play it safe and aim for a clock lower than + * desired rather than higher */ + if (diff < 0) { + sdiv++; + oclk = (sclk * 2) / sdiv; + } + + /* divider can go as low as 2, limited here because NVIDIA * and the VBIOS on my NVA8 seem to prefer using the PLL * for 810MHz - is there a good reason? - */ + * XXX: PLLs with refclk 810MHz? */ if (sdiv > 4) { - oclk = (sclk * 2) / sdiv; - diff = khz - oclk; - if (!pll || (diff >= -2000 && diff < 3000)) { - info->clk = (((sdiv - 2) << 16) | 0x00003100); - return oclk; - } + info->clk = (((sdiv - 2) << 16) | 0x00003100); + return oclk; } - if (!pll) - return -ERANGE; break; } + return -ERANGE; +} + +int +nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz, + struct nva3_clock_info *info) +{ + struct nouveau_bios *bios = nouveau_bios(clock); + struct nva3_clock_priv *priv = (void *)clock; + struct nvbios_pll limits; + int P, N, M, diff; + int ret; + + info->pll = 0; + + /* If we can get a within [-2, 3) MHz of a divider, we'll disable the + * PLL and use the divider instead. */ + ret = nva3_clk_info(clock, clk, khz, info); + diff = khz - ret; + if (!pll || (diff >= -2000 && diff < 3000)) { + goto out; + } + + /* Try with PLL */ ret = nvbios_pll_parse(bios, pll, &limits); if (ret) return ret; - limits.refclk = read_clk(priv, clk - 0x10, true); - if (!limits.refclk) + ret = nva3_clk_info(clock, clk - 0x10, limits.refclk, info); + if (ret != limits.refclk) return -EINVAL; ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P); if (ret >= 0) { - info->clk = nv_rd32(priv, 0x4120 + (clk * 4)); info->pll = (P << 16) | (N << 8) | M; } +out: + info->fb_delay = max(((khz + 7566) / 15133), (u32) 18); + return ret ? ret : -ERANGE; } @@ -208,13 +266,76 @@ static int calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate, int clk, u32 pll, int idx) { - int ret = nva3_clock_info(&priv->base, clk, pll, cstate->domain[idx], + int ret = nva3_pll_info(&priv->base, clk, pll, cstate->domain[idx], &priv->eng[idx]); if (ret >= 0) return 0; return ret; } +static int +calc_host(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate) +{ + int ret = 0; + u32 kHz = cstate->domain[nv_clk_src_host]; + struct nva3_clock_info *info = &priv->eng[nv_clk_src_host]; + + if (kHz == 277000) { + info->clk = 0; + info->host_out = NVA3_HOST_277; + return 0; + } + + info->host_out = NVA3_HOST_CLK; + + ret = nva3_clk_info(&priv->base, 0x1d, kHz, info); + if (ret >= 0) + return 0; + return ret; +} + +int +nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags) +{ + struct nouveau_fifo *pfifo = nouveau_fifo(clk); + + /* halt and idle execution engines */ + nv_mask(clk, 0x020060, 0x00070000, 0x00000000); + nv_mask(clk, 0x002504, 0x00000001, 0x00000001); + /* Wait until the interrupt handler is finished */ + if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000)) + return -EBUSY; + + if (pfifo) + pfifo->pause(pfifo, flags); + + if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010)) + return -EIO; + if (!nv_wait(clk, 0x00251c, 0x0000003f, 0x0000003f)) + return -EIO; + + return 0; +} + +void +nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags) +{ + struct nouveau_fifo *pfifo = nouveau_fifo(clk); + + if (pfifo && flags) + pfifo->start(pfifo, flags); + + nv_mask(clk, 0x002504, 0x00000001, 0x00000000); + nv_mask(clk, 0x020060, 0x00070000, 0x00040000); +} + +static void +disable_clk_src(struct nva3_clock_priv *priv, u32 src) +{ + nv_mask(priv, src, 0x00000100, 0x00000000); + nv_mask(priv, src, 0x00000001, 0x00000000); +} + static void prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx) { @@ -223,24 +344,35 @@ prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx) const u32 src1 = 0x004160 + (clk * 4); const u32 ctrl = pll + 0; const u32 coef = pll + 4; + u32 bypass; if (info->pll) { - nv_mask(priv, src0, 0x00000101, 0x00000101); + /* Always start from a non-PLL clock */ + bypass = nv_rd32(priv, ctrl) & 0x00000008; + if (!bypass) { + nv_mask(priv, src1, 0x00000101, 0x00000101); + nv_mask(priv, ctrl, 0x00000008, 0x00000008); + udelay(20); + } + + nv_mask(priv, src0, 0x003f3141, 0x00000101 | info->clk); nv_wr32(priv, coef, info->pll); nv_mask(priv, ctrl, 0x00000015, 0x00000015); nv_mask(priv, ctrl, 0x00000010, 0x00000000); - nv_wait(priv, ctrl, 0x00020000, 0x00020000); + if (!nv_wait(priv, ctrl, 0x00020000, 0x00020000)) { + nv_mask(priv, ctrl, 0x00000010, 0x00000010); + nv_mask(priv, src0, 0x00000101, 0x00000000); + return; + } nv_mask(priv, ctrl, 0x00000010, 0x00000010); nv_mask(priv, ctrl, 0x00000008, 0x00000000); - nv_mask(priv, src1, 0x00000100, 0x00000000); - nv_mask(priv, src1, 0x00000001, 0x00000000); + disable_clk_src(priv, src1); } else { nv_mask(priv, src1, 0x003f3141, 0x00000101 | info->clk); nv_mask(priv, ctrl, 0x00000018, 0x00000018); udelay(20); nv_mask(priv, ctrl, 0x00000001, 0x00000000); - nv_mask(priv, src0, 0x00000100, 0x00000000); - nv_mask(priv, src0, 0x00000001, 0x00000000); + disable_clk_src(priv, src0); } } @@ -251,18 +383,72 @@ prog_clk(struct nva3_clock_priv *priv, int clk, int idx) nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk); } +static void +prog_host(struct nva3_clock_priv *priv) +{ + struct nva3_clock_info *info = &priv->eng[nv_clk_src_host]; + u32 hsrc = (nv_rd32(priv, 0xc040)); + + switch (info->host_out) { + case NVA3_HOST_277: + if ((hsrc & 0x30000000) == 0) { + nv_wr32(priv, 0xc040, hsrc | 0x20000000); + disable_clk_src(priv, 0x4194); + } + break; + case NVA3_HOST_CLK: + prog_clk(priv, 0x1d, nv_clk_src_host); + if ((hsrc & 0x30000000) >= 0x20000000) { + nv_wr32(priv, 0xc040, hsrc & ~0x30000000); + } + break; + default: + break; + } + + /* This seems to be a clock gating factor on idle, always set to 64 */ + nv_wr32(priv, 0xc044, 0x3e); +} + +static void +prog_core(struct nva3_clock_priv *priv, int idx) +{ + struct nva3_clock_info *info = &priv->eng[idx]; + u32 fb_delay = nv_rd32(priv, 0x10002c); + + if (fb_delay < info->fb_delay) + nv_wr32(priv, 0x10002c, info->fb_delay); + + prog_pll(priv, 0x00, 0x004200, idx); + + if (fb_delay > info->fb_delay) + nv_wr32(priv, 0x10002c, info->fb_delay); +} + static int nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) { struct nva3_clock_priv *priv = (void *)clk; + struct nva3_clock_info *core = &priv->eng[nv_clk_src_core]; int ret; if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) || (ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) || (ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) || - (ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec))) + (ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)) || + (ret = calc_host(priv, cstate))) return ret; + /* XXX: Should be reading the highest bit in the VBIOS clock to decide + * whether to use a PLL or not... but using a PLL defeats the purpose */ + if (core->pll) { + ret = nva3_clk_info(clk, 0x10, + cstate->domain[nv_clk_src_core_intm], + &priv->eng[nv_clk_src_core_intm]); + if (ret < 0) + return ret; + } + return 0; } @@ -270,11 +456,31 @@ static int nva3_clock_prog(struct nouveau_clock *clk) { struct nva3_clock_priv *priv = (void *)clk; - prog_pll(priv, 0x00, 0x004200, nv_clk_src_core); + struct nva3_clock_info *core = &priv->eng[nv_clk_src_core]; + int ret = 0; + unsigned long flags; + unsigned long *f = &flags; + + ret = nva3_clock_pre(clk, f); + if (ret) + goto out; + + if (core->pll) + prog_core(priv, nv_clk_src_core_intm); + + prog_core(priv, nv_clk_src_core); prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader); prog_clk(priv, 0x20, nv_clk_src_disp); prog_clk(priv, 0x21, nv_clk_src_vdec); - return 0; + prog_host(priv); + +out: + if (ret == -EBUSY) + f = NULL; + + nva3_clock_post(clk, f); + + return ret; } static void @@ -284,13 +490,14 @@ nva3_clock_tidy(struct nouveau_clock *clk) static struct nouveau_clocks nva3_domain[] = { - { nv_clk_src_crystal, 0xff }, - { nv_clk_src_href , 0xff }, - { nv_clk_src_core , 0x00, 0, "core", 1000 }, - { nv_clk_src_shader , 0x01, 0, "shader", 1000 }, - { nv_clk_src_mem , 0x02, 0, "memory", 1000 }, - { nv_clk_src_vdec , 0x03 }, - { nv_clk_src_disp , 0x04 }, + { nv_clk_src_crystal , 0xff }, + { nv_clk_src_core , 0x00, 0, "core", 1000 }, + { nv_clk_src_shader , 0x01, 0, "shader", 1000 }, + { nv_clk_src_mem , 0x02, 0, "memory", 1000 }, + { nv_clk_src_vdec , 0x03 }, + { nv_clk_src_disp , 0x04 }, + { nv_clk_src_host , 0x05 }, + { nv_clk_src_core_intm, 0x06 }, { nv_clk_src_max } }; @@ -302,8 +509,8 @@ nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nva3_clock_priv *priv; int ret; - ret = nouveau_clock_create(parent, engine, oclass, nva3_domain, false, - &priv); + ret = nouveau_clock_create(parent, engine, oclass, nva3_domain, NULL, 0, + false, &priv); *pobject = nv_object(priv); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h index 6229a509b42e..a45a1038b12f 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h @@ -6,9 +6,15 @@ struct nva3_clock_info { u32 clk; u32 pll; + enum { + NVA3_HOST_277, + NVA3_HOST_CLK, + } host_out; + u32 fb_delay; }; -int nva3_clock_info(struct nouveau_clock *, int, u32, u32, +int nva3_pll_info(struct nouveau_clock *, int, u32, u32, struct nva3_clock_info *); - +int nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags); +void nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags); #endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c index 6a65fc9e9663..54aeab8005a0 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c @@ -28,6 +28,7 @@ #include <subdev/timer.h> #include <subdev/clock.h> +#include "nva3.h" #include "pll.h" struct nvaa_clock_priv { @@ -299,25 +300,14 @@ static int nvaa_clock_prog(struct nouveau_clock *clk) { struct nvaa_clock_priv *priv = (void *)clk; - struct nouveau_fifo *pfifo = nouveau_fifo(clk); + u32 pllmask = 0, mast; unsigned long flags; - u32 pllmask = 0, mast, ptherm_gate; - int ret = -EBUSY; - - /* halt and idle execution engines */ - ptherm_gate = nv_mask(clk, 0x020060, 0x00070000, 0x00000000); - nv_mask(clk, 0x002504, 0x00000001, 0x00000001); - /* Wait until the interrupt handler is finished */ - if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000)) - goto resume; - - if (pfifo) - pfifo->pause(pfifo, &flags); + unsigned long *f = &flags; + int ret = 0; - if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010)) - goto resume; - if (!nv_wait(clk, 0x00251c, 0x0000003f, 0x0000003f)) - goto resume; + ret = nva3_clock_pre(clk, f); + if (ret) + goto out; /* First switch to safe clocks: href */ mast = nv_mask(clk, 0xc054, 0x03400e70, 0x03400640); @@ -375,15 +365,8 @@ nvaa_clock_prog(struct nouveau_clock *clk) } nv_wr32(clk, 0xc054, mast); - ret = 0; resume: - if (pfifo) - pfifo->start(pfifo, &flags); - - nv_mask(clk, 0x002504, 0x00000001, 0x00000000); - nv_wr32(clk, 0x020060, ptherm_gate); - /* Disable some PLLs and dividers when unused */ if (priv->csrc != nv_clk_src_core) { nv_wr32(clk, 0x4040, 0x00000000); @@ -395,6 +378,12 @@ resume: nv_mask(clk, 0x4020, 0x80000000, 0x00000000); } +out: + if (ret == -EBUSY) + f = NULL; + + nva3_clock_post(clk, f); + return ret; } @@ -421,8 +410,8 @@ nvaa_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nvaa_clock_priv *priv; int ret; - ret = nouveau_clock_create(parent, engine, oclass, nvaa_domains, true, - &priv); + ret = nouveau_clock_create(parent, engine, oclass, nvaa_domains, NULL, + 0, true, &priv); *pobject = nv_object(priv); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c index dbf8517f54da..1234abaab2db 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c @@ -437,8 +437,8 @@ nvc0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nvc0_clock_priv *priv; int ret; - ret = nouveau_clock_create(parent, engine, oclass, nvc0_domain, false, - &priv); + ret = nouveau_clock_create(parent, engine, oclass, nvc0_domain, NULL, 0, + false, &priv); *pobject = nv_object(priv); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c index 0e62a3240144..7eccad57512e 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c @@ -475,8 +475,8 @@ nve0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nve0_clock_priv *priv; int ret; - ret = nouveau_clock_create(parent, engine, oclass, nve0_domain, true, - &priv); + ret = nouveau_clock_create(parent, engine, oclass, nve0_domain, NULL, 0, + true, &priv); *pobject = nv_object(priv); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h index 4fe49cf4c99a..6103484fea72 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h +++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h @@ -26,22 +26,8 @@ #include <core/device.h> -#define NV04_PFB_BOOT_0 0x00100000 -# define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003 -# define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000 -# define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001 -# define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002 -# define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003 -# define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004 -# define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028 -# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000 -# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008 -# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK 0x00000010 -# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT 0x00000018 -# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT 0x00000020 -# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 0x00000028 -# define NV04_PFB_BOOT_0_UMA_ENABLE 0x00000100 -# define NV04_PFB_BOOT_0_UMA_SIZE 0x0000f000 +#include <subdev/fb/regsnv04.h> + #define NV04_PFB_DEBUG_0 0x00100080 # define NV04_PFB_DEBUG_0_PAGE_MODE 0x00000001 # define NV04_PFB_DEBUG_0_REFRESH_OFF 0x00000010 diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c b/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c index 66fe959b4f74..7fbbe05d5c60 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c @@ -40,7 +40,7 @@ nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts) int WL, CL, WR, at[2], dt, ds; int rq = ram->freq < 1000000; /* XXX */ - switch (ram->ramcfg.version) { + switch (ram->next->bios.ramcfg_ver) { case 0x11: pd = ram->next->bios.ramcfg_11_01_80; lf = ram->next->bios.ramcfg_11_01_40; @@ -54,7 +54,7 @@ nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts) return -ENOSYS; } - switch (ram->timing.version) { + switch (ram->next->bios.timing_ver) { case 0x20: WL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; CL = (ram->next->bios.timing[1] & 0x0000001f); diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gk20a.c b/drivers/gpu/drm/nouveau/core/subdev/fb/gk20a.c index a16024a74771..fde42e4d1b56 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/gk20a.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/gk20a.c @@ -27,6 +27,20 @@ struct gk20a_fb_priv { }; static int +gk20a_fb_init(struct nouveau_object *object) +{ + struct gk20a_fb_priv *priv = (void *)object; + int ret; + + ret = nouveau_fb_init(&priv->base); + if (ret) + return ret; + + nv_mask(priv, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */ + return 0; +} + +static int gk20a_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) @@ -48,7 +62,7 @@ gk20a_fb_oclass = &(struct nouveau_fb_impl) { .base.ofuncs = &(struct nouveau_ofuncs) { .ctor = gk20a_fb_ctor, .dtor = _nouveau_fb_dtor, - .init = _nouveau_fb_init, + .init = gk20a_fb_init, .fini = _nouveau_fb_fini, }, .memtype = nvc0_fb_memtype_valid, diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c index f003c1b1893f..2209ade63339 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c @@ -45,7 +45,7 @@ nv20_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / pfb->ram->parts, 0x40); - if (!nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) { + if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */ else tile->zcomp = 0x04000000; /* Z24S8 */ tile->zcomp |= tile->tag->offset; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c index f34f4223210b..e2a66c355c50 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c @@ -32,7 +32,7 @@ nv25_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / pfb->ram->parts, 0x40); - if (!nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) { + if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ else tile->zcomp = 0x00200000; /* Z24S8 */ tile->zcomp |= tile->tag->offset; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c index 69093f7151f0..cbec402ba5b9 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c @@ -51,7 +51,7 @@ nv30_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / pfb->ram->parts, 0x40); - if (!nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) { + if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (flags & 2) tile->zcomp |= 0x01000000; /* Z16 */ else tile->zcomp |= 0x02000000; /* Z24S8 */ tile->zcomp |= ((tile->tag->offset ) >> 6); diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c index 161b06e8fc3f..b2cf8c69fb2e 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c @@ -32,7 +32,7 @@ nv35_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / pfb->ram->parts, 0x40); - if (!nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) { + if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ else tile->zcomp |= 0x08000000; /* Z24S8 */ tile->zcomp |= ((tile->tag->offset ) >> 6); diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c index 2dd3d0aab6bb..b4cdae2a3b2f 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c @@ -32,7 +32,7 @@ nv36_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / pfb->ram->parts, 0x40); - if (!nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) { + if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ else tile->zcomp |= 0x20000000; /* Z24S8 */ tile->zcomp |= ((tile->tag->offset ) >> 6); diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c index 95a115ab0c86..52814258c212 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c @@ -33,7 +33,7 @@ nv40_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, u32 tiles = DIV_ROUND_UP(size, 0x80); u32 tags = round_up(tiles / pfb->ram->parts, 0x100); if ( (flags & 2) && - !nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) { + !nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ tile->zcomp |= ((tile->tag->offset ) >> 8); tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c index 1fc55c1e91a1..4150b0d10af8 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c @@ -250,9 +250,11 @@ nv50_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO); if (priv->r100c08_page) { - priv->r100c08 = nv_device_map_page(device, priv->r100c08_page); - if (!priv->r100c08) - nv_warn(priv, "failed 0x100c08 page map\n"); + priv->r100c08 = dma_map_page(nv_device_base(device), + priv->r100c08_page, 0, PAGE_SIZE, + DMA_BIDIRECTIONAL); + if (dma_mapping_error(nv_device_base(device), priv->r100c08)) + return -EFAULT; } else { nv_warn(priv, "failed 0x100c08 page alloc\n"); } @@ -268,7 +270,8 @@ nv50_fb_dtor(struct nouveau_object *object) struct nv50_fb_priv *priv = (void *)object; if (priv->r100c08_page) { - nv_device_unmap_page(device, priv->r100c08); + dma_unmap_page(nv_device_base(device), priv->r100c08, PAGE_SIZE, + DMA_BIDIRECTIONAL); __free_page(priv->r100c08_page); } diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c index 0670ae33ee45..32f28dc73ef2 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c @@ -60,6 +60,7 @@ nvc0_fb_init(struct nouveau_object *object) if (priv->r100c10_page) nv_wr32(priv, 0x100c10, priv->r100c10 >> 8); + nv_mask(priv, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */ return 0; } @@ -70,7 +71,8 @@ nvc0_fb_dtor(struct nouveau_object *object) struct nvc0_fb_priv *priv = (void *)object; if (priv->r100c10_page) { - nv_device_unmap_page(device, priv->r100c10); + dma_unmap_page(nv_device_base(device), priv->r100c10, PAGE_SIZE, + DMA_BIDIRECTIONAL); __free_page(priv->r100c10_page); } @@ -93,8 +95,10 @@ nvc0_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->r100c10_page = alloc_page(GFP_KERNEL | __GFP_ZERO); if (priv->r100c10_page) { - priv->r100c10 = nv_device_map_page(device, priv->r100c10_page); - if (!priv->r100c10) + priv->r100c10 = dma_map_page(nv_device_base(device), + priv->r100c10_page, 0, PAGE_SIZE, + DMA_BIDIRECTIONAL); + if (dma_mapping_error(nv_device_base(device), priv->r100c10)) return -EFAULT; } diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h b/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h index 82273f832e42..60322e906dd4 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h @@ -35,6 +35,7 @@ extern struct nouveau_oclass nve0_ram_oclass; extern struct nouveau_oclass gk20a_ram_oclass; extern struct nouveau_oclass gm107_ram_oclass; +int nouveau_sddr2_calc(struct nouveau_ram *ram); int nouveau_sddr3_calc(struct nouveau_ram *ram); int nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts); diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h b/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h index 2af9cfd2c60f..d1fbbe4b00a2 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h @@ -12,16 +12,32 @@ struct ramfuc { struct ramfuc_reg { int sequence; bool force; - u32 addr[2]; + u32 addr; + u32 stride; /* in bytes */ + u32 mask; u32 data; }; static inline struct ramfuc_reg +ramfuc_stride(u32 addr, u32 stride, u32 mask) +{ + return (struct ramfuc_reg) { + .sequence = 0, + .addr = addr, + .stride = stride, + .mask = mask, + .data = 0xdeadbeef, + }; +} + +static inline struct ramfuc_reg ramfuc_reg2(u32 addr1, u32 addr2) { return (struct ramfuc_reg) { .sequence = 0, - .addr = { addr1, addr2 }, + .addr = addr1, + .stride = addr2 - addr1, + .mask = 0x3, .data = 0xdeadbeef, }; } @@ -29,7 +45,13 @@ ramfuc_reg2(u32 addr1, u32 addr2) static noinline struct ramfuc_reg ramfuc_reg(u32 addr) { - return ramfuc_reg2(addr, addr); + return (struct ramfuc_reg) { + .sequence = 0, + .addr = addr, + .stride = 0, + .mask = 0x1, + .data = 0xdeadbeef, + }; } static inline int @@ -62,18 +84,25 @@ static inline u32 ramfuc_rd32(struct ramfuc *ram, struct ramfuc_reg *reg) { if (reg->sequence != ram->sequence) - reg->data = nv_rd32(ram->pfb, reg->addr[0]); + reg->data = nv_rd32(ram->pfb, reg->addr); return reg->data; } static inline void ramfuc_wr32(struct ramfuc *ram, struct ramfuc_reg *reg, u32 data) { + unsigned int mask, off = 0; + reg->sequence = ram->sequence; reg->data = data; - if (reg->addr[0] != reg->addr[1]) - nouveau_memx_wr32(ram->memx, reg->addr[1], reg->data); - nouveau_memx_wr32(ram->memx, reg->addr[0], reg->data); + + for (mask = reg->mask; mask > 0; mask = (mask & ~1) >> 1) { + if (mask & 1) { + nouveau_memx_wr32(ram->memx, reg->addr+off, reg->data); + } + + off += reg->stride; + } } static inline void @@ -105,14 +134,35 @@ ramfuc_nsec(struct ramfuc *ram, u32 nsec) nouveau_memx_nsec(ram->memx, nsec); } -#define ram_init(s,p) ramfuc_init(&(s)->base, (p)) -#define ram_exec(s,e) ramfuc_exec(&(s)->base, (e)) -#define ram_have(s,r) ((s)->r_##r.addr[0] != 0x000000) -#define ram_rd32(s,r) ramfuc_rd32(&(s)->base, &(s)->r_##r) -#define ram_wr32(s,r,d) ramfuc_wr32(&(s)->base, &(s)->r_##r, (d)) -#define ram_nuke(s,r) ramfuc_nuke(&(s)->base, &(s)->r_##r) -#define ram_mask(s,r,m,d) ramfuc_mask(&(s)->base, &(s)->r_##r, (m), (d)) -#define ram_wait(s,r,m,d,n) ramfuc_wait(&(s)->base, (r), (m), (d), (n)) -#define ram_nsec(s,n) ramfuc_nsec(&(s)->base, (n)) +static inline void +ramfuc_wait_vblank(struct ramfuc *ram) +{ + nouveau_memx_wait_vblank(ram->memx); +} + +static inline void +ramfuc_block(struct ramfuc *ram) +{ + nouveau_memx_block(ram->memx); +} + +static inline void +ramfuc_unblock(struct ramfuc *ram) +{ + nouveau_memx_unblock(ram->memx); +} + +#define ram_init(s,p) ramfuc_init(&(s)->base, (p)) +#define ram_exec(s,e) ramfuc_exec(&(s)->base, (e)) +#define ram_have(s,r) ((s)->r_##r.addr != 0x000000) +#define ram_rd32(s,r) ramfuc_rd32(&(s)->base, &(s)->r_##r) +#define ram_wr32(s,r,d) ramfuc_wr32(&(s)->base, &(s)->r_##r, (d)) +#define ram_nuke(s,r) ramfuc_nuke(&(s)->base, &(s)->r_##r) +#define ram_mask(s,r,m,d) ramfuc_mask(&(s)->base, &(s)->r_##r, (m), (d)) +#define ram_wait(s,r,m,d,n) ramfuc_wait(&(s)->base, (r), (m), (d), (n)) +#define ram_nsec(s,n) ramfuc_nsec(&(s)->base, (n)) +#define ram_wait_vblank(s) ramfuc_wait_vblank(&(s)->base) +#define ram_block(s) ramfuc_block(&(s)->base) +#define ram_unblock(s) ramfuc_unblock(&(s)->base) #endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv04.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv04.c index e781080d3327..1972268d1410 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv04.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv04.c @@ -22,22 +22,7 @@ * Authors: Ben Skeggs */ -#define NV04_PFB_BOOT_0 0x00100000 -# define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003 -# define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000 -# define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001 -# define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002 -# define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003 -# define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004 -# define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028 -# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000 -# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008 -# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK 0x00000010 -# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT 0x00000018 -# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT 0x00000020 -# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 0x00000028 -# define NV04_PFB_BOOT_0_UMA_ENABLE 0x00000100 -# define NV04_PFB_BOOT_0_UMA_SIZE 0x0000f000 +#include <subdev/fb/regsnv04.h> #include "priv.h" diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c index e5d12c24cc43..64a983c96625 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c @@ -280,7 +280,7 @@ nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, if (align == 16) { int n = (max >> 4) * comp; - ret = nouveau_mm_head(tags, 1, n, n, 1, &mem->tag); + ret = nouveau_mm_head(tags, 0, 1, n, n, 1, &mem->tag); if (ret) mem->tag = NULL; } @@ -296,9 +296,9 @@ nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, type = nv50_fb_memtype[type]; do { if (back) - ret = nouveau_mm_tail(heap, type, max, min, align, &r); + ret = nouveau_mm_tail(heap, 0, type, max, min, align, &r); else - ret = nouveau_mm_head(heap, type, max, min, align, &r); + ret = nouveau_mm_head(heap, 0, type, max, min, align, &r); if (ret) { mutex_unlock(&pfb->base.mutex); pfb->ram->put(pfb, &mem); @@ -319,27 +319,22 @@ nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, static u32 nv50_fb_vram_rblock(struct nouveau_fb *pfb, struct nouveau_ram *ram) { - int i, parts, colbits, rowbitsa, rowbitsb, banks; + int colbits, rowbitsa, rowbitsb, banks; u64 rowsize, predicted; - u32 r0, r4, rt, ru, rblock_size; + u32 r0, r4, rt, rblock_size; r0 = nv_rd32(pfb, 0x100200); r4 = nv_rd32(pfb, 0x100204); rt = nv_rd32(pfb, 0x100250); - ru = nv_rd32(pfb, 0x001540); - nv_debug(pfb, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, ru); - - for (i = 0, parts = 0; i < 8; i++) { - if (ru & (0x00010000 << i)) - parts++; - } + nv_debug(pfb, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, + nv_rd32(pfb, 0x001540)); colbits = (r4 & 0x0000f000) >> 12; rowbitsa = ((r4 & 0x000f0000) >> 16) + 8; rowbitsb = ((r4 & 0x00f00000) >> 20) + 8; banks = 1 << (((r4 & 0x03000000) >> 24) + 2); - rowsize = parts * banks * (1 << colbits) * 8; + rowsize = ram->parts * banks * (1 << colbits) * 8; predicted = rowsize << rowbitsa; if (r0 & 0x00000004) predicted += rowsize << rowbitsb; @@ -376,6 +371,9 @@ nv50_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, ram->size = nv_rd32(pfb, 0x10020c); ram->size = (ram->size & 0xffffff00) | ((ram->size & 0x000000ff) << 32); + ram->part_mask = (nv_rd32(pfb, 0x001540) & 0x00ff0000) >> 16; + ram->parts = hweight8(ram->part_mask); + switch (nv_rd32(pfb, 0x100714) & 0x00000007) { case 0: ram->type = NV_MEM_TYPE_DDR1; break; case 1: diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c index 8076fb195dd5..3601deca0bd5 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c @@ -79,20 +79,27 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) struct nva3_ram *ram = (void *)pfb->ram; struct nva3_ramfuc *fuc = &ram->fuc; struct nva3_clock_info mclk; - u8 ver, cnt, len, strap; + struct nouveau_ram_data *next; + u8 ver, hdr, cnt, len, strap; u32 data; - struct { - u32 data; - u8 size; - } rammap, ramcfg, timing; u32 r004018, r100760, ctrl; u32 unk714, unk718, unk71c; - int ret; + int ret, i; + + next = &ram->base.target; + next->freq = freq; + ram->base.next = next; /* lookup memory config data relevant to the target frequency */ - rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size, - &cnt, &ramcfg.size); - if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) { + i = 0; + while ((data = nvbios_rammapEp(bios, i++, &ver, &hdr, &cnt, &len, + &next->bios))) { + if (freq / 1000 >= next->bios.rammap_min && + freq / 1000 <= next->bios.rammap_max) + break; + } + + if (!data || ver != 0x10 || hdr < 0x0e) { nv_error(pfb, "invalid/missing rammap entry\n"); return -EINVAL; } @@ -104,26 +111,25 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) return -EINVAL; } - ramcfg.data = rammap.data + rammap.size + (strap * ramcfg.size); - if (!ramcfg.data || ver != 0x10 || ramcfg.size < 0x0e) { + data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, strap, + &ver, &hdr, &next->bios); + if (!data || ver != 0x10 || hdr < 0x0e) { nv_error(pfb, "invalid/missing ramcfg entry\n"); return -EINVAL; } /* lookup memory timings, if bios says they're present */ - strap = nv_ro08(bios, ramcfg.data + 0x01); - if (strap != 0xff) { - timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size, - &cnt, &len); - if (!timing.data || ver != 0x10 || timing.size < 0x19) { + if (next->bios.ramcfg_timing != 0xff) { + data = nvbios_timingEp(bios, next->bios.ramcfg_timing, + &ver, &hdr, &cnt, &len, + &next->bios); + if (!data || ver != 0x10 || hdr < 0x19) { nv_error(pfb, "invalid/missing timing entry\n"); return -EINVAL; } - } else { - timing.data = 0; } - ret = nva3_clock_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk); + ret = nva3_pll_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk); if (ret < 0) { nv_error(pfb, "failed mclk calculation\n"); return ret; @@ -163,17 +169,17 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) ram_mask(fuc, 0x004168, 0x003f3141, ctrl); } - if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x10)) { + if (next->bios.ramcfg_10_02_10) { ram_mask(fuc, 0x111104, 0x00000600, 0x00000000); } else { ram_mask(fuc, 0x111100, 0x40000000, 0x40000000); ram_mask(fuc, 0x111104, 0x00000180, 0x00000000); } - if (!(nv_ro08(bios, rammap.data + 0x04) & 0x02)) + if (!next->bios.rammap_10_04_02) ram_mask(fuc, 0x100200, 0x00000800, 0x00000000); ram_wr32(fuc, 0x611200, 0x00003300); - if (!(nv_ro08(bios, ramcfg.data + 0x02) & 0x10)) + if (!next->bios.ramcfg_10_02_10) ram_wr32(fuc, 0x111100, 0x4c020000); /*XXX*/ ram_wr32(fuc, 0x1002d4, 0x00000001); @@ -202,17 +208,16 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) ram_wr32(fuc, 0x004018, 0x0000d000 | r004018); } - if ( (nv_ro08(bios, rammap.data + 0x04) & 0x08)) { - u32 unk5a0 = (nv_ro16(bios, ramcfg.data + 0x05) << 8) | - nv_ro08(bios, ramcfg.data + 0x05); - u32 unk5a4 = (nv_ro16(bios, ramcfg.data + 0x07)); - u32 unk804 = (nv_ro08(bios, ramcfg.data + 0x09) & 0xf0) << 16 | - (nv_ro08(bios, ramcfg.data + 0x03) & 0x0f) << 16 | - (nv_ro08(bios, ramcfg.data + 0x09) & 0x0f) | - 0x80000000; - ram_wr32(fuc, 0x1005a0, unk5a0); - ram_wr32(fuc, 0x1005a4, unk5a4); - ram_wr32(fuc, 0x10f804, unk804); + if (next->bios.rammap_10_04_08) { + ram_wr32(fuc, 0x1005a0, next->bios.ramcfg_10_06 << 16 | + next->bios.ramcfg_10_05 << 8 | + next->bios.ramcfg_10_05); + ram_wr32(fuc, 0x1005a4, next->bios.ramcfg_10_08 << 8 | + next->bios.ramcfg_10_07); + ram_wr32(fuc, 0x10f804, next->bios.ramcfg_10_09_f0 << 20 | + next->bios.ramcfg_10_03_0f << 16 | + next->bios.ramcfg_10_09_0f | + 0x80000000); ram_mask(fuc, 0x10053c, 0x00001000, 0x00000000); } else { ram_mask(fuc, 0x10053c, 0x00001000, 0x00001000); @@ -250,27 +255,26 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) ram_mask(fuc, 0x100220[0], 0x00000000, 0x00000000); ram_mask(fuc, 0x100220[8], 0x00000000, 0x00000000); - data = (nv_ro08(bios, ramcfg.data + 0x02) & 0x08) ? 0x00000000 : 0x00001000; - ram_mask(fuc, 0x100200, 0x00001000, data); + ram_mask(fuc, 0x100200, 0x00001000, !next->bios.ramcfg_10_02_08 << 12); unk714 = ram_rd32(fuc, 0x100714) & ~0xf0000010; unk718 = ram_rd32(fuc, 0x100718) & ~0x00000100; unk71c = ram_rd32(fuc, 0x10071c) & ~0x00000100; - if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x20)) + if (next->bios.ramcfg_10_02_20) unk714 |= 0xf0000000; - if (!(nv_ro08(bios, ramcfg.data + 0x02) & 0x04)) + if (!next->bios.ramcfg_10_02_04) unk714 |= 0x00000010; ram_wr32(fuc, 0x100714, unk714); - if (nv_ro08(bios, ramcfg.data + 0x02) & 0x01) + if (next->bios.ramcfg_10_02_01) unk71c |= 0x00000100; ram_wr32(fuc, 0x10071c, unk71c); - if (nv_ro08(bios, ramcfg.data + 0x02) & 0x02) + if (next->bios.ramcfg_10_02_02) unk718 |= 0x00000100; ram_wr32(fuc, 0x100718, unk718); - if (nv_ro08(bios, ramcfg.data + 0x02) & 0x10) + if (next->bios.ramcfg_10_02_10) ram_wr32(fuc, 0x111100, 0x48000000); /*XXX*/ ram_mask(fuc, mr[0], 0x100, 0x100); @@ -282,9 +286,9 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) ram_nsec(fuc, 12000); ram_wr32(fuc, 0x611200, 0x00003330); - if ( (nv_ro08(bios, rammap.data + 0x04) & 0x02)) + if (next->bios.rammap_10_04_02) ram_mask(fuc, 0x100200, 0x00000800, 0x00000800); - if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x10)) { + if (next->bios.ramcfg_10_02_10) { ram_mask(fuc, 0x111104, 0x00000180, 0x00000180); ram_mask(fuc, 0x111100, 0x40000000, 0x00000000); } else { @@ -404,11 +408,11 @@ nva3_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ram->fuc.r_0x100714 = ramfuc_reg(0x100714); ram->fuc.r_0x100718 = ramfuc_reg(0x100718); ram->fuc.r_0x10071c = ramfuc_reg(0x10071c); - ram->fuc.r_0x100760 = ramfuc_reg(0x100760); - ram->fuc.r_0x1007a0 = ramfuc_reg(0x1007a0); - ram->fuc.r_0x1007e0 = ramfuc_reg(0x1007e0); + ram->fuc.r_0x100760 = ramfuc_stride(0x100760, 4, ram->base.part_mask); + ram->fuc.r_0x1007a0 = ramfuc_stride(0x1007a0, 4, ram->base.part_mask); + ram->fuc.r_0x1007e0 = ramfuc_stride(0x1007e0, 4, ram->base.part_mask); ram->fuc.r_0x10f804 = ramfuc_reg(0x10f804); - ram->fuc.r_0x1110e0 = ramfuc_reg(0x1110e0); + ram->fuc.r_0x1110e0 = ramfuc_stride(0x1110e0, 4, ram->base.part_mask); ram->fuc.r_0x111100 = ramfuc_reg(0x111100); ram->fuc.r_0x111104 = ramfuc_reg(0x111104); ram->fuc.r_0x611200 = ramfuc_reg(0x611200); diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c index 5a6a5027f749..735cb9580abe 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c @@ -26,7 +26,7 @@ #include <subdev/bios/pll.h> #include <subdev/bios/rammap.h> #include <subdev/bios/timing.h> -#include <subdev/ltcg.h> +#include <subdev/ltc.h> #include <subdev/clock.h> #include <subdev/clock/pll.h> @@ -133,6 +133,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) struct nouveau_bios *bios = nouveau_bios(pfb); struct nvc0_ram *ram = (void *)pfb->ram; struct nvc0_ramfuc *fuc = &ram->fuc; + struct nvbios_ramcfg cfg; u8 ver, cnt, len, strap; struct { u32 data; @@ -145,7 +146,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) /* lookup memory config data relevant to the target frequency */ rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size, - &cnt, &ramcfg.size); + &cnt, &ramcfg.size, &cfg); if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) { nv_error(pfb, "invalid/missing rammap entry\n"); return -EINVAL; @@ -425,7 +426,7 @@ extern const u8 nvc0_pte_storage_type_map[256]; void nvc0_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) { - struct nouveau_ltcg *ltcg = nouveau_ltcg(pfb); + struct nouveau_ltc *ltc = nouveau_ltc(pfb); struct nouveau_mem *mem = *pmem; *pmem = NULL; @@ -434,7 +435,7 @@ nvc0_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) mutex_lock(&pfb->base.mutex); if (mem->tag) - ltcg->tags_free(ltcg, &mem->tag); + ltc->tags_free(ltc, &mem->tag); __nv50_ram_put(pfb, mem); mutex_unlock(&pfb->base.mutex); @@ -468,12 +469,12 @@ nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, mutex_lock(&pfb->base.mutex); if (comp) { - struct nouveau_ltcg *ltcg = nouveau_ltcg(pfb); + struct nouveau_ltc *ltc = nouveau_ltc(pfb); /* compression only works with lpages */ if (align == (1 << (17 - 12))) { int n = size >> 5; - ltcg->tags_alloc(ltcg, n, &mem->tag); + ltc->tags_alloc(ltc, n, &mem->tag); } if (unlikely(!mem->tag)) @@ -483,9 +484,9 @@ nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, do { if (back) - ret = nouveau_mm_tail(mm, 1, size, ncmin, align, &r); + ret = nouveau_mm_tail(mm, 0, 1, size, ncmin, align, &r); else - ret = nouveau_mm_head(mm, 1, size, ncmin, align, &r); + ret = nouveau_mm_head(mm, 0, 1, size, ncmin, align, &r); if (ret) { mutex_unlock(&pfb->base.mutex); pfb->ram->put(pfb, &mem); @@ -554,15 +555,15 @@ nvc0_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, } else { /* otherwise, address lowest common amount from 0GiB */ ret = nouveau_mm_init(&pfb->vram, rsvd_head, - (bsize << 8) * parts, 1); + (bsize << 8) * parts - rsvd_head, 1); if (ret) return ret; /* and the rest starting from (8GiB + common_size) */ offset = (0x0200000000ULL >> 12) + (bsize << 8); - length = (ram->size >> 12) - (bsize << 8) - rsvd_tail; + length = (ram->size >> 12) - ((bsize * parts) << 8) - rsvd_tail; - ret = nouveau_mm_init(&pfb->vram, offset, length, 0); + ret = nouveau_mm_init(&pfb->vram, offset, length, 1); if (ret) nouveau_mm_fini(&pfb->vram); } diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c index c5b46e302319..6bae474abb44 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c @@ -29,6 +29,8 @@ #include <subdev/bios/init.h> #include <subdev/bios/rammap.h> #include <subdev/bios/timing.h> +#include <subdev/bios/M0205.h> +#include <subdev/bios/M0209.h> #include <subdev/clock.h> #include <subdev/clock/pll.h> @@ -41,14 +43,6 @@ #include "ramfuc.h" -/* binary driver only executes this path if the condition (a) is true - * for any configuration (combination of rammap+ramcfg+timing) that - * can be reached on a given card. for now, we will execute the branch - * unconditionally in the hope that a "false everywhere" in the bios - * tables doesn't actually mean "don't touch this". - */ -#define NOTE00(a) 1 - struct nve0_ramfuc { struct ramfuc base; @@ -134,10 +128,12 @@ struct nve0_ram { struct nouveau_ram base; struct nve0_ramfuc fuc; + struct list_head cfg; u32 parts; u32 pmask; u32 pnuts; + struct nvbios_ramcfg diff; int from; int mode; int N1, fN1, M1, P1; @@ -241,7 +237,7 @@ nve0_ram_nuts(struct nve0_ram *ram, struct ramfuc_reg *reg, { struct nve0_fb_priv *priv = (void *)nouveau_fb(ram); struct ramfuc *fuc = &ram->fuc.base; - u32 addr = 0x110000 + (reg->addr[0] & 0xfff); + u32 addr = 0x110000 + (reg->addr & 0xfff); u32 mask = _mask | _copy; u32 data = (_data & _mask) | (reg->data & _copy); u32 i; @@ -268,6 +264,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) u32 mask, data; ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); + ram_block(fuc); ram_wr32(fuc, 0x62c000, 0x0f0f0000); /* MR1: turn termination on early, for some reason.. */ @@ -478,7 +475,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]); data = mask = 0x00000000; - if (NOTE00(ramcfg_08_20)) { + if (ram->diff.ramcfg_11_08_20) { if (next->bios.ramcfg_11_08_20) data |= 0x01000000; mask |= 0x01000000; @@ -486,11 +483,11 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) ram_mask(fuc, 0x10f200, mask, data); data = mask = 0x00000000; - if (NOTE00(ramcfg_02_03 != 0)) { + if (ram->diff.ramcfg_11_02_03) { data |= next->bios.ramcfg_11_02_03 << 8; mask |= 0x00000300; } - if (NOTE00(ramcfg_01_10)) { + if (ram->diff.ramcfg_11_01_10) { if (next->bios.ramcfg_11_01_10) data |= 0x70000000; mask |= 0x70000000; @@ -498,11 +495,11 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) ram_mask(fuc, 0x10f604, mask, data); data = mask = 0x00000000; - if (NOTE00(timing_30_07 != 0)) { + if (ram->diff.timing_20_30_07) { data |= next->bios.timing_20_30_07 << 28; mask |= 0x70000000; } - if (NOTE00(ramcfg_01_01)) { + if (ram->diff.ramcfg_11_01_01) { if (next->bios.ramcfg_11_01_01) data |= 0x00000100; mask |= 0x00000100; @@ -510,11 +507,11 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) ram_mask(fuc, 0x10f614, mask, data); data = mask = 0x00000000; - if (NOTE00(timing_30_07 != 0)) { + if (ram->diff.timing_20_30_07) { data |= next->bios.timing_20_30_07 << 28; mask |= 0x70000000; } - if (NOTE00(ramcfg_01_02)) { + if (ram->diff.ramcfg_11_01_02) { if (next->bios.ramcfg_11_01_02) data |= 0x00000100; mask |= 0x00000100; @@ -548,11 +545,11 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f); data = mask = 0x00000000; - if (NOTE00(ramcfg_02_03 != 0)) { + if (ram->diff.ramcfg_11_02_03) { data |= next->bios.ramcfg_11_02_03; mask |= 0x00000003; } - if (NOTE00(ramcfg_01_10)) { + if (ram->diff.ramcfg_11_01_10) { if (next->bios.ramcfg_11_01_10) data |= 0x00000004; mask |= 0x00000004; @@ -666,6 +663,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) if (next->bios.ramcfg_11_07_02) nve0_ram_train(fuc, 0x80020000, 0x01000000); + ram_unblock(fuc); ram_wr32(fuc, 0x62c000, 0x0f0f0f00); if (next->bios.rammap_11_08_01) @@ -695,6 +693,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) u32 mask, data; ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); + ram_block(fuc); ram_wr32(fuc, 0x62c000, 0x0f0f0000); if (vc == 1 && ram_have(fuc, gpio2E)) { @@ -917,6 +916,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); ram_nsec(fuc, 1000); + ram_unblock(fuc); ram_wr32(fuc, 0x62c000, 0x0f0f0f00); if (next->bios.rammap_11_08_01) @@ -932,58 +932,24 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) ******************************************************************************/ static int -nve0_ram_calc_data(struct nouveau_fb *pfb, u32 freq, +nve0_ram_calc_data(struct nouveau_fb *pfb, u32 khz, struct nouveau_ram_data *data) { - struct nouveau_bios *bios = nouveau_bios(pfb); struct nve0_ram *ram = (void *)pfb->ram; - u8 strap, cnt, len; - - /* lookup memory config data relevant to the target frequency */ - ram->base.rammap.data = nvbios_rammapEp(bios, freq / 1000, - &ram->base.rammap.version, - &ram->base.rammap.size, - &cnt, &len, &data->bios); - if (!ram->base.rammap.data || ram->base.rammap.version != 0x11 || - ram->base.rammap.size < 0x09) { - nv_error(pfb, "invalid/missing rammap entry\n"); - return -EINVAL; - } - - /* locate specific data set for the attached memory */ - strap = nvbios_ramcfg_index(nv_subdev(pfb)); - ram->base.ramcfg.data = nvbios_rammapSp(bios, ram->base.rammap.data, - ram->base.rammap.version, - ram->base.rammap.size, - cnt, len, strap, - &ram->base.ramcfg.version, - &ram->base.ramcfg.size, - &data->bios); - if (!ram->base.ramcfg.data || ram->base.ramcfg.version != 0x11 || - ram->base.ramcfg.size < 0x08) { - nv_error(pfb, "invalid/missing ramcfg entry\n"); - return -EINVAL; - } - - /* lookup memory timings, if bios says they're present */ - strap = nv_ro08(bios, ram->base.ramcfg.data + 0x00); - if (strap != 0xff) { - ram->base.timing.data = - nvbios_timingEp(bios, strap, &ram->base.timing.version, - &ram->base.timing.size, &cnt, &len, - &data->bios); - if (!ram->base.timing.data || - ram->base.timing.version != 0x20 || - ram->base.timing.size < 0x33) { - nv_error(pfb, "invalid/missing timing entry\n"); - return -EINVAL; + struct nouveau_ram_data *cfg; + u32 mhz = khz / 1000; + + list_for_each_entry(cfg, &ram->cfg, head) { + if (mhz >= cfg->bios.rammap_min && + mhz <= cfg->bios.rammap_max) { + *data = *cfg; + data->freq = khz; + return 0; } - } else { - ram->base.timing.data = 0; } - data->freq = freq; - return 0; + nv_error(ram, "ramcfg data for %dMHz not found\n", mhz); + return -EINVAL; } static int @@ -1106,13 +1072,99 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) return nve0_ram_calc_xits(pfb, ram->base.next); } +static void +nve0_ram_prog_0(struct nouveau_fb *pfb, u32 freq) +{ + struct nve0_ram *ram = (void *)pfb->ram; + struct nouveau_ram_data *cfg; + u32 mhz = freq / 1000; + u32 mask, data; + + list_for_each_entry(cfg, &ram->cfg, head) { + if (mhz >= cfg->bios.rammap_min && + mhz <= cfg->bios.rammap_max) + break; + } + + if (&cfg->head == &ram->cfg) + return; + + if (mask = 0, data = 0, ram->diff.rammap_11_0a_03fe) { + data |= cfg->bios.rammap_11_0a_03fe << 12; + mask |= 0x001ff000; + } + if (ram->diff.rammap_11_09_01ff) { + data |= cfg->bios.rammap_11_09_01ff; + mask |= 0x000001ff; + } + nv_mask(pfb, 0x10f468, mask, data); + + if (mask = 0, data = 0, ram->diff.rammap_11_0a_0400) { + data |= cfg->bios.rammap_11_0a_0400; + mask |= 0x00000001; + } + nv_mask(pfb, 0x10f420, mask, data); + + if (mask = 0, data = 0, ram->diff.rammap_11_0a_0800) { + data |= cfg->bios.rammap_11_0a_0800; + mask |= 0x00000001; + } + nv_mask(pfb, 0x10f430, mask, data); + + if (mask = 0, data = 0, ram->diff.rammap_11_0b_01f0) { + data |= cfg->bios.rammap_11_0b_01f0; + mask |= 0x0000001f; + } + nv_mask(pfb, 0x10f400, mask, data); + + if (mask = 0, data = 0, ram->diff.rammap_11_0b_0200) { + data |= cfg->bios.rammap_11_0b_0200 << 9; + mask |= 0x00000200; + } + nv_mask(pfb, 0x10f410, mask, data); + + if (mask = 0, data = 0, ram->diff.rammap_11_0d) { + data |= cfg->bios.rammap_11_0d << 16; + mask |= 0x00ff0000; + } + if (ram->diff.rammap_11_0f) { + data |= cfg->bios.rammap_11_0f << 8; + mask |= 0x0000ff00; + } + nv_mask(pfb, 0x10f440, mask, data); + + if (mask = 0, data = 0, ram->diff.rammap_11_0e) { + data |= cfg->bios.rammap_11_0e << 8; + mask |= 0x0000ff00; + } + if (ram->diff.rammap_11_0b_0800) { + data |= cfg->bios.rammap_11_0b_0800 << 7; + mask |= 0x00000080; + } + if (ram->diff.rammap_11_0b_0400) { + data |= cfg->bios.rammap_11_0b_0400 << 5; + mask |= 0x00000020; + } + nv_mask(pfb, 0x10f444, mask, data); +} + static int nve0_ram_prog(struct nouveau_fb *pfb) { struct nouveau_device *device = nv_device(pfb); struct nve0_ram *ram = (void *)pfb->ram; struct nve0_ramfuc *fuc = &ram->fuc; - ram_exec(fuc, nouveau_boolopt(device->cfgopt, "NvMemExec", true)); + struct nouveau_ram_data *next = ram->base.next; + + if (!nouveau_boolopt(device->cfgopt, "NvMemExec", true)) { + ram_exec(fuc, false); + return (ram->base.next == &ram->base.xition); + } + + nve0_ram_prog_0(pfb, 1000); + ram_exec(fuc, true); + nve0_ram_prog_0(pfb, next->freq); + return (ram->base.next == &ram->base.xition); } @@ -1125,24 +1177,147 @@ nve0_ram_tidy(struct nouveau_fb *pfb) ram_exec(fuc, false); } +struct nve0_ram_train { + u16 mask; + struct nvbios_M0209S remap; + struct nvbios_M0209S type00; + struct nvbios_M0209S type01; + struct nvbios_M0209S type04; + struct nvbios_M0209S type06; + struct nvbios_M0209S type07; + struct nvbios_M0209S type08; + struct nvbios_M0209S type09; +}; + +static int +nve0_ram_train_type(struct nouveau_fb *pfb, int i, u8 ramcfg, + struct nve0_ram_train *train) +{ + struct nouveau_bios *bios = nouveau_bios(pfb); + struct nvbios_M0205E M0205E; + struct nvbios_M0205S M0205S; + struct nvbios_M0209E M0209E; + struct nvbios_M0209S *remap = &train->remap; + struct nvbios_M0209S *value; + u8 ver, hdr, cnt, len; + u32 data; + + /* determine type of data for this index */ + if (!(data = nvbios_M0205Ep(bios, i, &ver, &hdr, &cnt, &len, &M0205E))) + return -ENOENT; + + switch (M0205E.type) { + case 0x00: value = &train->type00; break; + case 0x01: value = &train->type01; break; + case 0x04: value = &train->type04; break; + case 0x06: value = &train->type06; break; + case 0x07: value = &train->type07; break; + case 0x08: value = &train->type08; break; + case 0x09: value = &train->type09; break; + default: + return 0; + } + + /* training data index determined by ramcfg strap */ + if (!(data = nvbios_M0205Sp(bios, i, ramcfg, &ver, &hdr, &M0205S))) + return -EINVAL; + i = M0205S.data; + + /* training data format information */ + if (!(data = nvbios_M0209Ep(bios, i, &ver, &hdr, &cnt, &len, &M0209E))) + return -EINVAL; + + /* ... and the raw data */ + if (!(data = nvbios_M0209Sp(bios, i, 0, &ver, &hdr, value))) + return -EINVAL; + + if (M0209E.v02_07 == 2) { + /* of course! why wouldn't we have a pointer to another entry + * in the same table, and use the first one as an array of + * remap indices... + */ + if (!(data = nvbios_M0209Sp(bios, M0209E.v03, 0, &ver, &hdr, + remap))) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(value->data); i++) + value->data[i] = remap->data[value->data[i]]; + } else + if (M0209E.v02_07 != 1) + return -EINVAL; + + train->mask |= 1 << M0205E.type; + return 0; +} + +static int +nve0_ram_train_init_0(struct nouveau_fb *pfb, struct nve0_ram_train *train) +{ + int i, j; + + if ((train->mask & 0x03d3) != 0x03d3) { + nv_warn(pfb, "missing link training data\n"); + return -EINVAL; + } + + for (i = 0; i < 0x30; i++) { + for (j = 0; j < 8; j += 4) { + nv_wr32(pfb, 0x10f968 + j, 0x00000000 | (i << 8)); + nv_wr32(pfb, 0x10f920 + j, 0x00000000 | + train->type08.data[i] << 4 | + train->type06.data[i]); + nv_wr32(pfb, 0x10f918 + j, train->type00.data[i]); + nv_wr32(pfb, 0x10f920 + j, 0x00000100 | + train->type09.data[i] << 4 | + train->type07.data[i]); + nv_wr32(pfb, 0x10f918 + j, train->type01.data[i]); + } + } + + for (j = 0; j < 8; j += 4) { + for (i = 0; i < 0x100; i++) { + nv_wr32(pfb, 0x10f968 + j, i); + nv_wr32(pfb, 0x10f900 + j, train->type04.data[i]); + } + } + + return 0; +} + +static int +nve0_ram_train_init(struct nouveau_fb *pfb) +{ + u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb)); + struct nve0_ram_train *train; + int ret = -ENOMEM, i; + + if ((train = kzalloc(sizeof(*train), GFP_KERNEL))) { + for (i = 0; i < 0x100; i++) { + ret = nve0_ram_train_type(pfb, i, ramcfg, train); + if (ret && ret != -ENOENT) + break; + } + } + + switch (pfb->ram->type) { + case NV_MEM_TYPE_GDDR5: + ret = nve0_ram_train_init_0(pfb, train); + break; + default: + ret = 0; + break; + } + + kfree(train); + return ret; +} + int nve0_ram_init(struct nouveau_object *object) { struct nouveau_fb *pfb = (void *)object->parent; struct nve0_ram *ram = (void *)object; struct nouveau_bios *bios = nouveau_bios(pfb); - static const u8 train0[] = { - 0x00, 0xff, 0xff, 0x00, 0xff, 0x00, - 0x00, 0xff, 0xff, 0x00, 0xff, 0x00, - }; - static const u32 train1[] = { - 0x00000000, 0xffffffff, - 0x55555555, 0xaaaaaaaa, - 0x33333333, 0xcccccccc, - 0xf0f0f0f0, 0x0f0f0f0f, - 0x00ff00ff, 0xff00ff00, - 0x0000ffff, 0xffff0000, - }; u8 ver, hdr, cnt, len, snr, ssz; u32 data, save; int ret, i; @@ -1168,51 +1343,107 @@ nve0_ram_init(struct nouveau_object *object) cnt = nv_ro08(bios, data + 0x14); /* guess at count */ data = nv_ro32(bios, data + 0x10); /* guess u32... */ - save = nv_rd32(pfb, 0x10f65c); - for (i = 0; i < cnt; i++) { - nv_mask(pfb, 0x10f65c, 0x000000f0, i << 4); - nvbios_exec(&(struct nvbios_init) { - .subdev = nv_subdev(pfb), - .bios = bios, - .offset = nv_ro32(bios, data), /* guess u32 */ - .execute = 1, - }); - data += 4; - } - nv_wr32(pfb, 0x10f65c, save); + save = nv_rd32(pfb, 0x10f65c) & 0x000000f0; + for (i = 0; i < cnt; i++, data += 4) { + if (i != save >> 4) { + nv_mask(pfb, 0x10f65c, 0x000000f0, i << 4); + nvbios_exec(&(struct nvbios_init) { + .subdev = nv_subdev(pfb), + .bios = bios, + .offset = nv_ro32(bios, data), + .execute = 1, + }); + } + } + nv_mask(pfb, 0x10f65c, 0x000000f0, save); nv_mask(pfb, 0x10f584, 0x11000000, 0x00000000); + nv_wr32(pfb, 0x10ecc0, 0xffffffff); + nv_mask(pfb, 0x10f160, 0x00000010, 0x00000010); - switch (ram->base.type) { - case NV_MEM_TYPE_GDDR5: - for (i = 0; i < 0x30; i++) { - nv_wr32(pfb, 0x10f968, 0x00000000 | (i << 8)); - nv_wr32(pfb, 0x10f920, 0x00000000 | train0[i % 12]); - nv_wr32(pfb, 0x10f918, train1[i % 12]); - nv_wr32(pfb, 0x10f920, 0x00000100 | train0[i % 12]); - nv_wr32(pfb, 0x10f918, train1[i % 12]); - - nv_wr32(pfb, 0x10f96c, 0x00000000 | (i << 8)); - nv_wr32(pfb, 0x10f924, 0x00000000 | train0[i % 12]); - nv_wr32(pfb, 0x10f91c, train1[i % 12]); - nv_wr32(pfb, 0x10f924, 0x00000100 | train0[i % 12]); - nv_wr32(pfb, 0x10f91c, train1[i % 12]); - } + return nve0_ram_train_init(pfb); +} - for (i = 0; i < 0x100; i++) { - nv_wr32(pfb, 0x10f968, i); - nv_wr32(pfb, 0x10f900, train1[2 + (i & 1)]); - } +static int +nve0_ram_ctor_data(struct nve0_ram *ram, u8 ramcfg, int i) +{ + struct nouveau_fb *pfb = (void *)nv_object(ram)->parent; + struct nouveau_bios *bios = nouveau_bios(pfb); + struct nouveau_ram_data *cfg; + struct nvbios_ramcfg *d = &ram->diff; + struct nvbios_ramcfg *p, *n; + u8 ver, hdr, cnt, len; + u32 data; + int ret; - for (i = 0; i < 0x100; i++) { - nv_wr32(pfb, 0x10f96c, i); - nv_wr32(pfb, 0x10f900, train1[2 + (i & 1)]); - } - break; - default: - break; + if (!(cfg = kmalloc(sizeof(*cfg), GFP_KERNEL))) + return -ENOMEM; + p = &list_last_entry(&ram->cfg, typeof(*cfg), head)->bios; + n = &cfg->bios; + + /* memory config data for a range of target frequencies */ + data = nvbios_rammapEp(bios, i, &ver, &hdr, &cnt, &len, &cfg->bios); + if (ret = -ENOENT, !data) + goto done; + if (ret = -ENOSYS, ver != 0x11 || hdr < 0x12) + goto done; + + /* ... and a portion specific to the attached memory */ + data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, ramcfg, + &ver, &hdr, &cfg->bios); + if (ret = -EINVAL, !data) + goto done; + if (ret = -ENOSYS, ver != 0x11 || hdr < 0x0a) + goto done; + + /* lookup memory timings, if bios says they're present */ + if (cfg->bios.ramcfg_timing != 0xff) { + data = nvbios_timingEp(bios, cfg->bios.ramcfg_timing, + &ver, &hdr, &cnt, &len, + &cfg->bios); + if (ret = -EINVAL, !data) + goto done; + if (ret = -ENOSYS, ver != 0x20 || hdr < 0x33) + goto done; } - return 0; + list_add_tail(&cfg->head, &ram->cfg); + if (ret = 0, i == 0) + goto done; + + d->rammap_11_0a_03fe |= p->rammap_11_0a_03fe != n->rammap_11_0a_03fe; + d->rammap_11_09_01ff |= p->rammap_11_09_01ff != n->rammap_11_09_01ff; + d->rammap_11_0a_0400 |= p->rammap_11_0a_0400 != n->rammap_11_0a_0400; + d->rammap_11_0a_0800 |= p->rammap_11_0a_0800 != n->rammap_11_0a_0800; + d->rammap_11_0b_01f0 |= p->rammap_11_0b_01f0 != n->rammap_11_0b_01f0; + d->rammap_11_0b_0200 |= p->rammap_11_0b_0200 != n->rammap_11_0b_0200; + d->rammap_11_0d |= p->rammap_11_0d != n->rammap_11_0d; + d->rammap_11_0f |= p->rammap_11_0f != n->rammap_11_0f; + d->rammap_11_0e |= p->rammap_11_0e != n->rammap_11_0e; + d->rammap_11_0b_0800 |= p->rammap_11_0b_0800 != n->rammap_11_0b_0800; + d->rammap_11_0b_0400 |= p->rammap_11_0b_0400 != n->rammap_11_0b_0400; + d->ramcfg_11_01_01 |= p->ramcfg_11_01_01 != n->ramcfg_11_01_01; + d->ramcfg_11_01_02 |= p->ramcfg_11_01_02 != n->ramcfg_11_01_02; + d->ramcfg_11_01_10 |= p->ramcfg_11_01_10 != n->ramcfg_11_01_10; + d->ramcfg_11_02_03 |= p->ramcfg_11_02_03 != n->ramcfg_11_02_03; + d->ramcfg_11_08_20 |= p->ramcfg_11_08_20 != n->ramcfg_11_08_20; + d->timing_20_30_07 |= p->timing_20_30_07 != n->timing_20_30_07; +done: + if (ret) + kfree(cfg); + return ret; +} + +static void +nve0_ram_dtor(struct nouveau_object *object) +{ + struct nve0_ram *ram = (void *)object; + struct nouveau_ram_data *cfg, *tmp; + + list_for_each_entry_safe(cfg, tmp, &ram->cfg, head) { + kfree(cfg); + } + + nouveau_ram_destroy(&ram->base); } static int @@ -1226,6 +1457,7 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct dcb_gpio_func func; struct nve0_ram *ram; int ret, i; + u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb)); u32 tmp; ret = nvc0_ram_create(parent, engine, oclass, 0x022554, &ram); @@ -1233,6 +1465,8 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, if (ret) return ret; + INIT_LIST_HEAD(&ram->cfg); + switch (ram->base.type) { case NV_MEM_TYPE_DDR3: case NV_MEM_TYPE_GDDR5: @@ -1264,7 +1498,26 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } } - // parse bios data for both pll's + /* parse bios data for all rammap table entries up-front, and + * build information on whether certain fields differ between + * any of the entries. + * + * the binary driver appears to completely ignore some fields + * when all entries contain the same value. at first, it was + * hoped that these were mere optimisations and the bios init + * tables had configured as per the values here, but there is + * evidence now to suggest that this isn't the case and we do + * need to treat this condition as a "don't touch" indicator. + */ + for (i = 0; !ret; i++) { + ret = nve0_ram_ctor_data(ram, ramcfg, i); + if (ret && ret != -ENOENT) { + nv_error(pfb, "failed to parse ramcfg data\n"); + return ret; + } + } + + /* parse bios data for both pll's */ ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll); if (ret) { nv_error(pfb, "mclk refpll data not found\n"); @@ -1277,6 +1530,7 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return ret; } + /* lookup memory voltage gpios */ ret = gpio->find(gpio, 0, 0x18, DCB_GPIO_UNUSED, &func); if (ret == 0) { ram->fuc.r_gpioMV = ramfuc_reg(0x00d610 + (func.line * 0x04)); @@ -1385,7 +1639,7 @@ nve0_ram_oclass = { .handle = 0, .ofuncs = &(struct nouveau_ofuncs) { .ctor = nve0_ram_ctor, - .dtor = _nouveau_ram_dtor, + .dtor = nve0_ram_dtor, .init = nve0_ram_init, .fini = _nouveau_ram_fini, } diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c b/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c new file mode 100644 index 000000000000..bb1eb8f3e639 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c @@ -0,0 +1,94 @@ +/* + * Copyright 2014 Roy Spliet + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Roy Spliet <rspliet@eclipso.eu> + * Ben Skeggs + */ + +#include "priv.h" + +struct ramxlat { + int id; + u8 enc; +}; + +static inline int +ramxlat(const struct ramxlat *xlat, int id) +{ + while (xlat->id >= 0) { + if (xlat->id == id) + return xlat->enc; + xlat++; + } + return -EINVAL; +} + +static const struct ramxlat +ramddr2_cl[] = { + { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, + /* The following are available in some, but not all DDR2 docs */ + { 7, 7 }, + { -1 } +}; + +static const struct ramxlat +ramddr2_wr[] = { + { 2, 1 }, { 3, 2 }, { 4, 3 }, { 5, 4 }, { 6, 5 }, + /* The following are available in some, but not all DDR2 docs */ + { 7, 6 }, + { -1 } +}; + +int +nouveau_sddr2_calc(struct nouveau_ram *ram) +{ + int CL, WR, DLL = 0, ODT = 0; + + switch (ram->next->bios.timing_ver) { + case 0x10: + CL = ram->next->bios.timing_10_CL; + WR = ram->next->bios.timing_10_WR; + DLL = !ram->next->bios.ramcfg_10_02_40; + ODT = ram->next->bios.timing_10_ODT & 3; + break; + case 0x20: + CL = (ram->next->bios.timing[1] & 0x0000001f); + WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; + break; + default: + return -ENOSYS; + } + + CL = ramxlat(ramddr2_cl, CL); + WR = ramxlat(ramddr2_wr, WR); + if (CL < 0 || WR < 0) + return -EINVAL; + + ram->mr[0] &= ~0xf70; + ram->mr[0] |= (WR & 0x07) << 9; + ram->mr[0] |= (CL & 0x07) << 4; + + ram->mr[1] &= ~0x045; + ram->mr[1] |= (ODT & 0x1) << 2; + ram->mr[1] |= (ODT & 0x2) << 5; + ram->mr[1] |= !DLL; + return 0; +} diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c b/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c index ebd4cd9c35d9..83949b11833a 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c @@ -20,9 +20,9 @@ * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Ben Skeggs <bskeggs@redhat.com> + * Roy Spliet <rspliet@eclipso.eu> */ -#include <subdev/bios.h> #include "priv.h" struct ramxlat { @@ -69,31 +69,52 @@ ramddr3_cwl[] = { int nouveau_sddr3_calc(struct nouveau_ram *ram) { - struct nouveau_bios *bios = nouveau_bios(ram); - int WL, CL, WR; + int CWL, CL, WR, DLL = 0, ODT = 0; - switch (!!ram->timing.data * ram->timing.version) { + switch (ram->next->bios.timing_ver) { + case 0x10: + if (ram->next->bios.timing_hdr < 0x17) { + /* XXX: NV50: Get CWL from the timing register */ + return -ENOSYS; + } + CWL = ram->next->bios.timing_10_CWL; + CL = ram->next->bios.timing_10_CL; + WR = ram->next->bios.timing_10_WR; + DLL = !ram->next->bios.ramcfg_10_02_40; + ODT = ram->next->bios.timing_10_ODT; + break; case 0x20: - WL = (nv_ro16(bios, ram->timing.data + 0x04) & 0x0f80) >> 7; - CL = nv_ro08(bios, ram->timing.data + 0x04) & 0x1f; - WR = nv_ro08(bios, ram->timing.data + 0x0a) & 0x7f; + CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; + CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; + WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; + /* XXX: Get these values from the VBIOS instead */ + DLL = !(ram->mr[1] & 0x1); + ODT = (ram->mr[1] & 0x004) >> 2 | + (ram->mr[1] & 0x040) >> 5 | + (ram->mr[1] & 0x200) >> 7; break; default: return -ENOSYS; } - WL = ramxlat(ramddr3_cwl, WL); - CL = ramxlat(ramddr3_cl, CL); - WR = ramxlat(ramddr3_wr, WR); - if (WL < 0 || CL < 0 || WR < 0) + CWL = ramxlat(ramddr3_cwl, CWL); + CL = ramxlat(ramddr3_cl, CL); + WR = ramxlat(ramddr3_wr, WR); + if (CL < 0 || CWL < 0 || WR < 0) return -EINVAL; - ram->mr[0] &= ~0xe74; + ram->mr[0] &= ~0xf74; ram->mr[0] |= (WR & 0x07) << 9; ram->mr[0] |= (CL & 0x0e) << 3; ram->mr[0] |= (CL & 0x01) << 2; + ram->mr[1] &= ~0x245; + ram->mr[1] |= (ODT & 0x1) << 2; + ram->mr[1] |= (ODT & 0x2) << 5; + ram->mr[1] |= (ODT & 0x4) << 7; + ram->mr[1] |= !DLL; + ram->mr[2] &= ~0x038; - ram->mr[2] |= (WL & 0x07) << 3; + ram->mr[2] |= (CWL & 0x07) << 3; return 0; } diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/base.c b/drivers/gpu/drm/nouveau/core/subdev/fuse/base.c new file mode 100644 index 000000000000..9e8e92127715 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/fuse/base.c @@ -0,0 +1,54 @@ +/* + * Copyright 2014 Martin Peres + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Martin Peres + */ + +#include <subdev/fuse.h> + +int +_nouveau_fuse_init(struct nouveau_object *object) +{ + struct nouveau_fuse *fuse = (void *)object; + return nouveau_subdev_init(&fuse->base); +} + +void +_nouveau_fuse_dtor(struct nouveau_object *object) +{ + struct nouveau_fuse *fuse = (void *)object; + nouveau_subdev_destroy(&fuse->base); +} + +int +nouveau_fuse_create_(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, int length, void **pobject) +{ + struct nouveau_fuse *fuse; + int ret; + + ret = nouveau_subdev_create_(parent, engine, oclass, 0, "FUSE", + "fuse", length, pobject); + fuse = *pobject; + + return ret; +} diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/g80.c b/drivers/gpu/drm/nouveau/core/subdev/fuse/g80.c new file mode 100644 index 000000000000..a374ade485be --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/fuse/g80.c @@ -0,0 +1,81 @@ +/* + * Copyright 2014 Martin Peres + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Martin Peres + */ + +#include "priv.h" + +struct g80_fuse_priv { + struct nouveau_fuse base; + + spinlock_t fuse_enable_lock; +}; + +static u32 +g80_fuse_rd32(struct nouveau_object *object, u64 addr) +{ + struct g80_fuse_priv *priv = (void *)object; + unsigned long flags; + u32 fuse_enable, val; + + spin_lock_irqsave(&priv->fuse_enable_lock, flags); + + /* racy if another part of nouveau start writing to this reg */ + fuse_enable = nv_mask(priv, 0x1084, 0x800, 0x800); + val = nv_rd32(priv, 0x21000 + addr); + nv_wr32(priv, 0x1084, fuse_enable); + + spin_unlock_irqrestore(&priv->fuse_enable_lock, flags); + + return val; +} + + +static int +g80_fuse_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct g80_fuse_priv *priv; + int ret; + + ret = nouveau_fuse_create(parent, engine, oclass, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + spin_lock_init(&priv->fuse_enable_lock); + + return 0; +} + +struct nouveau_oclass +g80_fuse_oclass = { + .handle = NV_SUBDEV(FUSE, 0x50), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = g80_fuse_ctor, + .dtor = _nouveau_fuse_dtor, + .init = _nouveau_fuse_init, + .fini = _nouveau_fuse_fini, + .rd32 = g80_fuse_rd32, + }, +}; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/gf100.c b/drivers/gpu/drm/nouveau/core/subdev/fuse/gf100.c new file mode 100644 index 000000000000..5ed03f54b3d4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/fuse/gf100.c @@ -0,0 +1,83 @@ +/* + * Copyright 2014 Martin Peres + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Martin Peres + */ + +#include "priv.h" + +struct gf100_fuse_priv { + struct nouveau_fuse base; + + spinlock_t fuse_enable_lock; +}; + +static u32 +gf100_fuse_rd32(struct nouveau_object *object, u64 addr) +{ + struct gf100_fuse_priv *priv = (void *)object; + unsigned long flags; + u32 fuse_enable, unk, val; + + spin_lock_irqsave(&priv->fuse_enable_lock, flags); + + /* racy if another part of nouveau start writing to these regs */ + fuse_enable = nv_mask(priv, 0x22400, 0x800, 0x800); + unk = nv_mask(priv, 0x21000, 0x1, 0x1); + val = nv_rd32(priv, 0x21100 + addr); + nv_wr32(priv, 0x21000, unk); + nv_wr32(priv, 0x22400, fuse_enable); + + spin_unlock_irqrestore(&priv->fuse_enable_lock, flags); + + return val; +} + + +static int +gf100_fuse_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct gf100_fuse_priv *priv; + int ret; + + ret = nouveau_fuse_create(parent, engine, oclass, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + spin_lock_init(&priv->fuse_enable_lock); + + return 0; +} + +struct nouveau_oclass +gf100_fuse_oclass = { + .handle = NV_SUBDEV(FUSE, 0xC0), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = gf100_fuse_ctor, + .dtor = _nouveau_fuse_dtor, + .init = _nouveau_fuse_init, + .fini = _nouveau_fuse_fini, + .rd32 = gf100_fuse_rd32, + }, +}; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/gm107.c b/drivers/gpu/drm/nouveau/core/subdev/fuse/gm107.c new file mode 100644 index 000000000000..4f1a636c6538 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/fuse/gm107.c @@ -0,0 +1,66 @@ +/* + * Copyright 2014 Martin Peres + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Martin Peres + */ + +#include "priv.h" + +struct gm107_fuse_priv { + struct nouveau_fuse base; +}; + +static u32 +gm107_fuse_rd32(struct nouveau_object *object, u64 addr) +{ + struct gf100_fuse_priv *priv = (void *)object; + + return nv_rd32(priv, 0x21100 + addr); +} + + +static int +gm107_fuse_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct gm107_fuse_priv *priv; + int ret; + + ret = nouveau_fuse_create(parent, engine, oclass, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + return 0; +} + +struct nouveau_oclass +gm107_fuse_oclass = { + .handle = NV_SUBDEV(FUSE, 0x117), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = gm107_fuse_ctor, + .dtor = _nouveau_fuse_dtor, + .init = _nouveau_fuse_init, + .fini = _nouveau_fuse_fini, + .rd32 = gm107_fuse_rd32, + }, +}; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/priv.h b/drivers/gpu/drm/nouveau/core/subdev/fuse/priv.h new file mode 100644 index 000000000000..d2085411a5cb --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/fuse/priv.h @@ -0,0 +1,9 @@ +#ifndef __NVKM_FUSE_PRIV_H__ +#define __NVKM_FUSE_PRIV_H__ + +#include <subdev/fuse.h> + +int _nouveau_fuse_init(struct nouveau_object *object); +void _nouveau_fuse_dtor(struct nouveau_object *object); + +#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/base.c b/drivers/gpu/drm/nouveau/core/subdev/gpio/base.c index 45e0202f3151..7ad99b763f4c 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/gpio/base.c +++ b/drivers/gpu/drm/nouveau/core/subdev/gpio/base.c @@ -106,39 +106,60 @@ nouveau_gpio_get(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line) } static void -nouveau_gpio_intr_disable(struct nouveau_event *event, int type, int index) +nouveau_gpio_intr_fini(struct nvkm_event *event, int type, int index) { - struct nouveau_gpio *gpio = nouveau_gpio(event->priv); + struct nouveau_gpio *gpio = container_of(event, typeof(*gpio), event); const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass; impl->intr_mask(gpio, type, 1 << index, 0); } static void -nouveau_gpio_intr_enable(struct nouveau_event *event, int type, int index) +nouveau_gpio_intr_init(struct nvkm_event *event, int type, int index) { - struct nouveau_gpio *gpio = nouveau_gpio(event->priv); + struct nouveau_gpio *gpio = container_of(event, typeof(*gpio), event); const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass; impl->intr_mask(gpio, type, 1 << index, 1 << index); } +static int +nouveau_gpio_intr_ctor(struct nouveau_object *object, void *data, u32 size, + struct nvkm_notify *notify) +{ + struct nvkm_gpio_ntfy_req *req = data; + if (!WARN_ON(size != sizeof(*req))) { + notify->size = sizeof(struct nvkm_gpio_ntfy_rep); + notify->types = req->mask; + notify->index = req->line; + return 0; + } + return -EINVAL; +} + static void nouveau_gpio_intr(struct nouveau_subdev *subdev) { struct nouveau_gpio *gpio = nouveau_gpio(subdev); const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass; - u32 hi, lo, e, i; + u32 hi, lo, i; impl->intr_stat(gpio, &hi, &lo); - for (i = 0; e = 0, (hi | lo) && i < impl->lines; i++) { - if (hi & (1 << i)) - e |= NVKM_GPIO_HI; - if (lo & (1 << i)) - e |= NVKM_GPIO_LO; - nouveau_event_trigger(gpio->events, e, i); + for (i = 0; (hi | lo) && i < impl->lines; i++) { + struct nvkm_gpio_ntfy_rep rep = { + .mask = (NVKM_GPIO_HI * !!(hi & (1 << i))) | + (NVKM_GPIO_LO * !!(lo & (1 << i))), + }; + nvkm_event_send(&gpio->event, rep.mask, i, &rep, sizeof(rep)); } } +static const struct nvkm_event_func +nouveau_gpio_intr_func = { + .ctor = nouveau_gpio_intr_ctor, + .init = nouveau_gpio_intr_init, + .fini = nouveau_gpio_intr_fini, +}; + int _nouveau_gpio_fini(struct nouveau_object *object, bool suspend) { @@ -183,7 +204,7 @@ void _nouveau_gpio_dtor(struct nouveau_object *object) { struct nouveau_gpio *gpio = (void *)object; - nouveau_event_destroy(&gpio->events); + nvkm_event_fini(&gpio->event); nouveau_subdev_destroy(&gpio->base); } @@ -208,13 +229,11 @@ nouveau_gpio_create_(struct nouveau_object *parent, gpio->get = nouveau_gpio_get; gpio->reset = impl->reset; - ret = nouveau_event_create(2, impl->lines, &gpio->events); + ret = nvkm_event_init(&nouveau_gpio_intr_func, 2, impl->lines, + &gpio->event); if (ret) return ret; - gpio->events->priv = gpio; - gpio->events->enable = nouveau_gpio_intr_enable; - gpio->events->disable = nouveau_gpio_intr_disable; nv_subdev(gpio)->intr = nouveau_gpio_intr; return 0; } diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv92.c b/drivers/gpu/drm/nouveau/core/subdev/gpio/nv94.c index 252083d376f5..cae404ccadac 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv92.c +++ b/drivers/gpu/drm/nouveau/core/subdev/gpio/nv94.c @@ -25,7 +25,7 @@ #include "priv.h" void -nv92_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo) +nv94_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo) { u32 intr0 = nv_rd32(gpio, 0x00e054); u32 intr1 = nv_rd32(gpio, 0x00e074); @@ -38,7 +38,7 @@ nv92_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo) } void -nv92_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data) +nv94_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data) { u32 inte0 = nv_rd32(gpio, 0x00e050); u32 inte1 = nv_rd32(gpio, 0x00e070); @@ -57,8 +57,8 @@ nv92_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data) } struct nouveau_oclass * -nv92_gpio_oclass = &(struct nouveau_gpio_impl) { - .base.handle = NV_SUBDEV(GPIO, 0x92), +nv94_gpio_oclass = &(struct nouveau_gpio_impl) { + .base.handle = NV_SUBDEV(GPIO, 0x94), .base.ofuncs = &(struct nouveau_ofuncs) { .ctor = _nouveau_gpio_ctor, .dtor = _nouveau_gpio_dtor, @@ -66,8 +66,8 @@ nv92_gpio_oclass = &(struct nouveau_gpio_impl) { .fini = _nouveau_gpio_fini, }, .lines = 32, - .intr_stat = nv92_gpio_intr_stat, - .intr_mask = nv92_gpio_intr_mask, + .intr_stat = nv94_gpio_intr_stat, + .intr_mask = nv94_gpio_intr_mask, .drive = nv50_gpio_drive, .sense = nv50_gpio_sense, .reset = nv50_gpio_reset, diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c b/drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c index a4682b0956ad..480d6d2af770 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c @@ -77,8 +77,8 @@ nvd0_gpio_oclass = &(struct nouveau_gpio_impl) { .fini = _nouveau_gpio_fini, }, .lines = 32, - .intr_stat = nv92_gpio_intr_stat, - .intr_mask = nv92_gpio_intr_mask, + .intr_stat = nv94_gpio_intr_stat, + .intr_mask = nv94_gpio_intr_mask, .drive = nvd0_gpio_drive, .sense = nvd0_gpio_sense, .reset = nvd0_gpio_reset, diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h b/drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h index e1724dfc86ae..bff98b86e2b5 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h +++ b/drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h @@ -56,8 +56,8 @@ void nv50_gpio_reset(struct nouveau_gpio *, u8); int nv50_gpio_drive(struct nouveau_gpio *, int, int, int); int nv50_gpio_sense(struct nouveau_gpio *, int); -void nv92_gpio_intr_stat(struct nouveau_gpio *, u32 *, u32 *); -void nv92_gpio_intr_mask(struct nouveau_gpio *, u32, u32, u32); +void nv94_gpio_intr_stat(struct nouveau_gpio *, u32 *, u32 *); +void nv94_gpio_intr_mask(struct nouveau_gpio *, u32, u32, u32); void nvd0_gpio_reset(struct nouveau_gpio *, u8); int nvd0_gpio_drive(struct nouveau_gpio *, int, int, int); diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c index 09ba2cc851cf..2b1bf545e488 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c +++ b/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c @@ -23,6 +23,7 @@ */ #include <core/option.h> +#include <core/object.h> #include <core/event.h> #include <subdev/bios.h> @@ -326,9 +327,9 @@ nouveau_i2c_identify(struct nouveau_i2c *i2c, int index, const char *what, } static void -nouveau_i2c_intr_disable(struct nouveau_event *event, int type, int index) +nouveau_i2c_intr_fini(struct nvkm_event *event, int type, int index) { - struct nouveau_i2c *i2c = nouveau_i2c(event->priv); + struct nouveau_i2c *i2c = container_of(event, typeof(*i2c), event); struct nouveau_i2c_port *port = i2c->find(i2c, index); const struct nouveau_i2c_impl *impl = (void *)nv_object(i2c)->oclass; if (port && port->aux >= 0) @@ -336,15 +337,29 @@ nouveau_i2c_intr_disable(struct nouveau_event *event, int type, int index) } static void -nouveau_i2c_intr_enable(struct nouveau_event *event, int type, int index) +nouveau_i2c_intr_init(struct nvkm_event *event, int type, int index) { - struct nouveau_i2c *i2c = nouveau_i2c(event->priv); + struct nouveau_i2c *i2c = container_of(event, typeof(*i2c), event); struct nouveau_i2c_port *port = i2c->find(i2c, index); const struct nouveau_i2c_impl *impl = (void *)nv_object(i2c)->oclass; if (port && port->aux >= 0) impl->aux_mask(i2c, type, 1 << port->aux, 1 << port->aux); } +static int +nouveau_i2c_intr_ctor(struct nouveau_object *object, void *data, u32 size, + struct nvkm_notify *notify) +{ + struct nvkm_i2c_ntfy_req *req = data; + if (!WARN_ON(size != sizeof(*req))) { + notify->size = sizeof(struct nvkm_i2c_ntfy_rep); + notify->types = req->mask; + notify->index = req->port; + return 0; + } + return -EINVAL; +} + static void nouveau_i2c_intr(struct nouveau_subdev *subdev) { @@ -364,13 +379,26 @@ nouveau_i2c_intr(struct nouveau_subdev *subdev) if (lo & (1 << port->aux)) e |= NVKM_I2C_UNPLUG; if (rq & (1 << port->aux)) e |= NVKM_I2C_IRQ; if (tx & (1 << port->aux)) e |= NVKM_I2C_DONE; - - nouveau_event_trigger(i2c->ntfy, e, port->index); + if (e) { + struct nvkm_i2c_ntfy_rep rep = { + .mask = e, + }; + nvkm_event_send(&i2c->event, rep.mask, + port->index, &rep, + sizeof(rep)); + } } } } } +static const struct nvkm_event_func +nouveau_i2c_intr_func = { + .ctor = nouveau_i2c_intr_ctor, + .init = nouveau_i2c_intr_init, + .fini = nouveau_i2c_intr_fini, +}; + int _nouveau_i2c_fini(struct nouveau_object *object, bool suspend) { @@ -431,7 +459,7 @@ _nouveau_i2c_dtor(struct nouveau_object *object) struct nouveau_i2c *i2c = (void *)object; struct nouveau_i2c_port *port, *temp; - nouveau_event_destroy(&i2c->ntfy); + nvkm_event_fini(&i2c->event); list_for_each_entry_safe(port, temp, &i2c->ports, head) { nouveau_object_ref(NULL, (struct nouveau_object **)&port); @@ -547,13 +575,10 @@ nouveau_i2c_create_(struct nouveau_object *parent, } } - ret = nouveau_event_create(4, index, &i2c->ntfy); + ret = nvkm_event_init(&nouveau_i2c_intr_func, 4, index, &i2c->event); if (ret) return ret; - i2c->ntfy->priv = i2c; - i2c->ntfy->enable = nouveau_i2c_intr_enable; - i2c->ntfy->disable = nouveau_i2c_intr_disable; return 0; } diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c index 7b64befee48f..e8b1401c59c0 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c +++ b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c @@ -69,7 +69,7 @@ nv04_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, if (ret) return ret; - ret = nouveau_mm_head(&priv->heap, 1, args->size, args->size, + ret = nouveau_mm_head(&priv->heap, 0, 1, args->size, args->size, args->align, &node->mem); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/base.c b/drivers/gpu/drm/nouveau/core/subdev/ltc/base.c new file mode 100644 index 000000000000..7fa331516f84 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/ltc/base.c @@ -0,0 +1,126 @@ +/* + * Copyright 2014 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ + +#include "priv.h" + +static int +nvkm_ltc_tags_alloc(struct nouveau_ltc *ltc, u32 n, + struct nouveau_mm_node **pnode) +{ + struct nvkm_ltc_priv *priv = (void *)ltc; + int ret; + + ret = nouveau_mm_head(&priv->tags, 0, 1, n, n, 1, pnode); + if (ret) + *pnode = NULL; + + return ret; +} + +static void +nvkm_ltc_tags_free(struct nouveau_ltc *ltc, struct nouveau_mm_node **pnode) +{ + struct nvkm_ltc_priv *priv = (void *)ltc; + nouveau_mm_free(&priv->tags, pnode); +} + +static void +nvkm_ltc_tags_clear(struct nouveau_ltc *ltc, u32 first, u32 count) +{ + const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc); + struct nvkm_ltc_priv *priv = (void *)ltc; + const u32 limit = first + count - 1; + + BUG_ON((first > limit) || (limit >= priv->num_tags)); + + impl->cbc_clear(priv, first, limit); + impl->cbc_wait(priv); +} + +static int +nvkm_ltc_zbc_color_get(struct nouveau_ltc *ltc, int index, const u32 color[4]) +{ + const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc); + struct nvkm_ltc_priv *priv = (void *)ltc; + memcpy(priv->zbc_color[index], color, sizeof(priv->zbc_color[index])); + impl->zbc_clear_color(priv, index, color); + return index; +} + +static int +nvkm_ltc_zbc_depth_get(struct nouveau_ltc *ltc, int index, const u32 depth) +{ + const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc); + struct nvkm_ltc_priv *priv = (void *)ltc; + priv->zbc_depth[index] = depth; + impl->zbc_clear_depth(priv, index, depth); + return index; +} + +int +_nvkm_ltc_init(struct nouveau_object *object) +{ + const struct nvkm_ltc_impl *impl = (void *)nv_oclass(object); + struct nvkm_ltc_priv *priv = (void *)object; + int ret, i; + + ret = nouveau_subdev_init(&priv->base.base); + if (ret) + return ret; + + for (i = priv->base.zbc_min; i <= priv->base.zbc_max; i++) { + impl->zbc_clear_color(priv, i, priv->zbc_color[i]); + impl->zbc_clear_depth(priv, i, priv->zbc_depth[i]); + } + + return 0; +} + +int +nvkm_ltc_create_(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, int length, void **pobject) +{ + const struct nvkm_ltc_impl *impl = (void *)oclass; + struct nvkm_ltc_priv *priv; + int ret; + + ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PLTCG", + "l2c", length, pobject); + priv = *pobject; + if (ret) + return ret; + + memset(priv->zbc_color, 0x00, sizeof(priv->zbc_color)); + memset(priv->zbc_depth, 0x00, sizeof(priv->zbc_depth)); + + priv->base.base.intr = impl->intr; + priv->base.tags_alloc = nvkm_ltc_tags_alloc; + priv->base.tags_free = nvkm_ltc_tags_free; + priv->base.tags_clear = nvkm_ltc_tags_clear; + priv->base.zbc_min = 1; /* reserve 0 for disabled */ + priv->base.zbc_max = min(impl->zbc, NOUVEAU_LTC_MAX_ZBC_CNT) - 1; + priv->base.zbc_color_get = nvkm_ltc_zbc_color_get; + priv->base.zbc_depth_get = nvkm_ltc_zbc_depth_get; + return 0; +} diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltcg/gf100.c b/drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c index f2f3338a967a..2db0977284f8 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/ltcg/gf100.c +++ b/drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c @@ -25,86 +25,126 @@ #include <subdev/fb.h> #include <subdev/timer.h> -#include "gf100.h" +#include "priv.h" + +void +gf100_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit) +{ + nv_wr32(priv, 0x17e8cc, start); + nv_wr32(priv, 0x17e8d0, limit); + nv_wr32(priv, 0x17e8c8, 0x00000004); +} + +void +gf100_ltc_cbc_wait(struct nvkm_ltc_priv *priv) +{ + int c, s; + for (c = 0; c < priv->ltc_nr; c++) { + for (s = 0; s < priv->lts_nr; s++) + nv_wait(priv, 0x1410c8 + c * 0x2000 + s * 0x400, ~0, 0); + } +} + +void +gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *priv, int i, const u32 color[4]) +{ + nv_mask(priv, 0x17ea44, 0x0000000f, i); + nv_wr32(priv, 0x17ea48, color[0]); + nv_wr32(priv, 0x17ea4c, color[1]); + nv_wr32(priv, 0x17ea50, color[2]); + nv_wr32(priv, 0x17ea54, color[3]); +} + +void +gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *priv, int i, const u32 depth) +{ + nv_mask(priv, 0x17ea44, 0x0000000f, i); + nv_wr32(priv, 0x17ea58, depth); +} + +static const struct nouveau_bitfield +gf100_ltc_lts_intr_name[] = { + { 0x00000001, "IDLE_ERROR_IQ" }, + { 0x00000002, "IDLE_ERROR_CBC" }, + { 0x00000004, "IDLE_ERROR_TSTG" }, + { 0x00000008, "IDLE_ERROR_DSTG" }, + { 0x00000010, "EVICTED_CB" }, + { 0x00000020, "ILLEGAL_COMPSTAT" }, + { 0x00000040, "BLOCKLINEAR_CB" }, + { 0x00000100, "ECC_SEC_ERROR" }, + { 0x00000200, "ECC_DED_ERROR" }, + { 0x00000400, "DEBUG" }, + { 0x00000800, "ATOMIC_TO_Z" }, + { 0x00001000, "ILLEGAL_ATOMIC" }, + { 0x00002000, "BLKACTIVITY_ERR" }, + {} +}; static void -gf100_ltcg_lts_isr(struct gf100_ltcg_priv *priv, int ltc, int lts) +gf100_ltc_lts_intr(struct nvkm_ltc_priv *priv, int ltc, int lts) { u32 base = 0x141000 + (ltc * 0x2000) + (lts * 0x400); - u32 stat = nv_rd32(priv, base + 0x020); + u32 intr = nv_rd32(priv, base + 0x020); + u32 stat = intr & 0x0000ffff; if (stat) { - nv_info(priv, "LTC%d_LTS%d: 0x%08x\n", ltc, lts, stat); - nv_wr32(priv, base + 0x020, stat); + nv_info(priv, "LTC%d_LTS%d:", ltc, lts); + nouveau_bitfield_print(gf100_ltc_lts_intr_name, stat); + pr_cont("\n"); } + + nv_wr32(priv, base + 0x020, intr); } -static void -gf100_ltcg_intr(struct nouveau_subdev *subdev) +void +gf100_ltc_intr(struct nouveau_subdev *subdev) { - struct gf100_ltcg_priv *priv = (void *)subdev; + struct nvkm_ltc_priv *priv = (void *)subdev; u32 mask; mask = nv_rd32(priv, 0x00017c); while (mask) { u32 lts, ltc = __ffs(mask); for (lts = 0; lts < priv->lts_nr; lts++) - gf100_ltcg_lts_isr(priv, ltc, lts); + gf100_ltc_lts_intr(priv, ltc, lts); mask &= ~(1 << ltc); } - - /* we do something horribly wrong and upset PMFB a lot, so mask off - * interrupts from it after the first one until it's fixed - */ - nv_mask(priv, 0x000640, 0x02000000, 0x00000000); } -int -gf100_ltcg_tags_alloc(struct nouveau_ltcg *ltcg, u32 n, - struct nouveau_mm_node **pnode) +static int +gf100_ltc_init(struct nouveau_object *object) { - struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg; + struct nvkm_ltc_priv *priv = (void *)object; + u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001); int ret; - ret = nouveau_mm_head(&priv->tags, 1, n, n, 1, pnode); + ret = nvkm_ltc_init(priv); if (ret) - *pnode = NULL; + return ret; - return ret; + nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */ + nv_wr32(priv, 0x17e8d8, priv->ltc_nr); + nv_wr32(priv, 0x17e8d4, priv->tag_base); + nv_mask(priv, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); + return 0; } void -gf100_ltcg_tags_free(struct nouveau_ltcg *ltcg, struct nouveau_mm_node **pnode) -{ - struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg; - - nouveau_mm_free(&priv->tags, pnode); -} - -static void -gf100_ltcg_tags_clear(struct nouveau_ltcg *ltcg, u32 first, u32 count) +gf100_ltc_dtor(struct nouveau_object *object) { - struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg; - u32 last = first + count - 1; - int p, i; + struct nouveau_fb *pfb = nouveau_fb(object); + struct nvkm_ltc_priv *priv = (void *)object; - BUG_ON((first > last) || (last >= priv->num_tags)); - - nv_wr32(priv, 0x17e8cc, first); - nv_wr32(priv, 0x17e8d0, last); - nv_wr32(priv, 0x17e8c8, 0x4); /* trigger clear */ + nouveau_mm_fini(&priv->tags); + nouveau_mm_free(&pfb->vram, &priv->tag_ram); - /* wait until it's finished with clearing */ - for (p = 0; p < priv->ltc_nr; ++p) { - for (i = 0; i < priv->lts_nr; ++i) - nv_wait(priv, 0x1410c8 + p * 0x2000 + i * 0x400, ~0, 0); - } + nvkm_ltc_destroy(priv); } /* TODO: Figure out tag memory details and drop the over-cautious allocation. */ int -gf100_ltcg_init_tag_ram(struct nouveau_fb *pfb, struct gf100_ltcg_priv *priv) +gf100_ltc_init_tag_ram(struct nouveau_fb *pfb, struct nvkm_ltc_priv *priv) { u32 tag_size, tag_margin, tag_align; int ret; @@ -130,34 +170,34 @@ gf100_ltcg_init_tag_ram(struct nouveau_fb *pfb, struct gf100_ltcg_priv *priv) tag_size += tag_align; tag_size = (tag_size + 0xfff) >> 12; /* round up */ - ret = nouveau_mm_tail(&pfb->vram, 1, tag_size, tag_size, 1, + ret = nouveau_mm_tail(&pfb->vram, 1, 1, tag_size, tag_size, 1, &priv->tag_ram); if (ret) { priv->num_tags = 0; } else { - u64 tag_base = (priv->tag_ram->offset << 12) + tag_margin; + u64 tag_base = ((u64)priv->tag_ram->offset << 12) + tag_margin; tag_base += tag_align - 1; ret = do_div(tag_base, tag_align); priv->tag_base = tag_base; } - ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1); + ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1); return ret; } -static int -gf100_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +int +gf100_ltc_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) { - struct gf100_ltcg_priv *priv; struct nouveau_fb *pfb = nouveau_fb(parent); + struct nvkm_ltc_priv *priv; u32 parts, mask; int ret, i; - ret = nouveau_ltcg_create(parent, engine, oclass, &priv); + ret = nvkm_ltc_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -170,57 +210,27 @@ gf100_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } priv->lts_nr = nv_rd32(priv, 0x17e8dc) >> 28; - ret = gf100_ltcg_init_tag_ram(pfb, priv); - if (ret) - return ret; - - priv->base.tags_alloc = gf100_ltcg_tags_alloc; - priv->base.tags_free = gf100_ltcg_tags_free; - priv->base.tags_clear = gf100_ltcg_tags_clear; - - nv_subdev(priv)->intr = gf100_ltcg_intr; - return 0; -} - -void -gf100_ltcg_dtor(struct nouveau_object *object) -{ - struct nouveau_ltcg *ltcg = (struct nouveau_ltcg *)object; - struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg; - struct nouveau_fb *pfb = nouveau_fb(ltcg->base.base.parent); - - nouveau_mm_fini(&priv->tags); - nouveau_mm_free(&pfb->vram, &priv->tag_ram); - - nouveau_ltcg_destroy(ltcg); -} - -static int -gf100_ltcg_init(struct nouveau_object *object) -{ - struct nouveau_ltcg *ltcg = (struct nouveau_ltcg *)object; - struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg; - int ret; - - ret = nouveau_ltcg_init(ltcg); + ret = gf100_ltc_init_tag_ram(pfb, priv); if (ret) return ret; - nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */ - nv_wr32(priv, 0x17e8d8, priv->ltc_nr); - if (nv_device(ltcg)->card_type >= NV_E0) - nv_wr32(priv, 0x17e000, priv->ltc_nr); - nv_wr32(priv, 0x17e8d4, priv->tag_base); + nv_subdev(priv)->intr = gf100_ltc_intr; return 0; } struct nouveau_oclass * -gf100_ltcg_oclass = &(struct nouveau_oclass) { - .handle = NV_SUBDEV(LTCG, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = gf100_ltcg_ctor, - .dtor = gf100_ltcg_dtor, - .init = gf100_ltcg_init, - .fini = _nouveau_ltcg_fini, +gf100_ltc_oclass = &(struct nvkm_ltc_impl) { + .base.handle = NV_SUBDEV(LTC, 0xc0), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = gf100_ltc_ctor, + .dtor = gf100_ltc_dtor, + .init = gf100_ltc_init, + .fini = _nvkm_ltc_fini, }, -}; + .intr = gf100_ltc_intr, + .cbc_clear = gf100_ltc_cbc_clear, + .cbc_wait = gf100_ltc_cbc_wait, + .zbc = 16, + .zbc_clear_color = gf100_ltc_zbc_clear_color, + .zbc_clear_depth = gf100_ltc_zbc_clear_depth, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/gk104.c b/drivers/gpu/drm/nouveau/core/subdev/ltc/gk104.c new file mode 100644 index 000000000000..b39b5d0eb8f9 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/ltc/gk104.c @@ -0,0 +1,60 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "priv.h" + +static int +gk104_ltc_init(struct nouveau_object *object) +{ + struct nvkm_ltc_priv *priv = (void *)object; + u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001); + int ret; + + ret = nvkm_ltc_init(priv); + if (ret) + return ret; + + nv_wr32(priv, 0x17e8d8, priv->ltc_nr); + nv_wr32(priv, 0x17e000, priv->ltc_nr); + nv_wr32(priv, 0x17e8d4, priv->tag_base); + nv_mask(priv, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); + return 0; +} + +struct nouveau_oclass * +gk104_ltc_oclass = &(struct nvkm_ltc_impl) { + .base.handle = NV_SUBDEV(LTC, 0xe4), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = gf100_ltc_ctor, + .dtor = gf100_ltc_dtor, + .init = gk104_ltc_init, + .fini = _nvkm_ltc_fini, + }, + .intr = gf100_ltc_intr, + .cbc_clear = gf100_ltc_cbc_clear, + .cbc_wait = gf100_ltc_cbc_wait, + .zbc = 16, + .zbc_clear_color = gf100_ltc_zbc_clear_color, + .zbc_clear_depth = gf100_ltc_zbc_clear_depth, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltcg/gm107.c b/drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c index e79d0e81de40..89fc4238f50c 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/ltcg/gm107.c +++ b/drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c @@ -25,10 +25,45 @@ #include <subdev/fb.h> #include <subdev/timer.h> -#include "gf100.h" +#include "priv.h" static void -gm107_ltcg_lts_isr(struct gf100_ltcg_priv *priv, int ltc, int lts) +gm107_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit) +{ + nv_wr32(priv, 0x17e270, start); + nv_wr32(priv, 0x17e274, limit); + nv_wr32(priv, 0x17e26c, 0x00000004); +} + +static void +gm107_ltc_cbc_wait(struct nvkm_ltc_priv *priv) +{ + int c, s; + for (c = 0; c < priv->ltc_nr; c++) { + for (s = 0; s < priv->lts_nr; s++) + nv_wait(priv, 0x14046c + c * 0x2000 + s * 0x200, ~0, 0); + } +} + +static void +gm107_ltc_zbc_clear_color(struct nvkm_ltc_priv *priv, int i, const u32 color[4]) +{ + nv_mask(priv, 0x17e338, 0x0000000f, i); + nv_wr32(priv, 0x17e33c, color[0]); + nv_wr32(priv, 0x17e340, color[1]); + nv_wr32(priv, 0x17e344, color[2]); + nv_wr32(priv, 0x17e348, color[3]); +} + +static void +gm107_ltc_zbc_clear_depth(struct nvkm_ltc_priv *priv, int i, const u32 depth) +{ + nv_mask(priv, 0x17e338, 0x0000000f, i); + nv_wr32(priv, 0x17e34c, depth); +} + +static void +gm107_ltc_lts_isr(struct nvkm_ltc_priv *priv, int ltc, int lts) { u32 base = 0x140000 + (ltc * 0x2000) + (lts * 0x400); u32 stat = nv_rd32(priv, base + 0x00c); @@ -40,56 +75,48 @@ gm107_ltcg_lts_isr(struct gf100_ltcg_priv *priv, int ltc, int lts) } static void -gm107_ltcg_intr(struct nouveau_subdev *subdev) +gm107_ltc_intr(struct nouveau_subdev *subdev) { - struct gf100_ltcg_priv *priv = (void *)subdev; + struct nvkm_ltc_priv *priv = (void *)subdev; u32 mask; mask = nv_rd32(priv, 0x00017c); while (mask) { u32 lts, ltc = __ffs(mask); for (lts = 0; lts < priv->lts_nr; lts++) - gm107_ltcg_lts_isr(priv, ltc, lts); + gm107_ltc_lts_isr(priv, ltc, lts); mask &= ~(1 << ltc); } - - /* we do something horribly wrong and upset PMFB a lot, so mask off - * interrupts from it after the first one until it's fixed - */ - nv_mask(priv, 0x000640, 0x02000000, 0x00000000); } -static void -gm107_ltcg_tags_clear(struct nouveau_ltcg *ltcg, u32 first, u32 count) +static int +gm107_ltc_init(struct nouveau_object *object) { - struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg; - u32 last = first + count - 1; - int p, i; - - BUG_ON((first > last) || (last >= priv->num_tags)); + struct nvkm_ltc_priv *priv = (void *)object; + u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001); + int ret; - nv_wr32(priv, 0x17e270, first); - nv_wr32(priv, 0x17e274, last); - nv_wr32(priv, 0x17e26c, 0x4); /* trigger clear */ + ret = nvkm_ltc_init(priv); + if (ret) + return ret; - /* wait until it's finished with clearing */ - for (p = 0; p < priv->ltc_nr; ++p) { - for (i = 0; i < priv->lts_nr; ++i) - nv_wait(priv, 0x14046c + p * 0x2000 + i * 0x200, ~0, 0); - } + nv_wr32(priv, 0x17e27c, priv->ltc_nr); + nv_wr32(priv, 0x17e278, priv->tag_base); + nv_mask(priv, 0x17e264, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); + return 0; } static int -gm107_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +gm107_ltc_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) { - struct gf100_ltcg_priv *priv; struct nouveau_fb *pfb = nouveau_fb(parent); + struct nvkm_ltc_priv *priv; u32 parts, mask; int ret, i; - ret = nouveau_ltcg_create(parent, engine, oclass, &priv); + ret = nvkm_ltc_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -102,41 +129,26 @@ gm107_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } priv->lts_nr = nv_rd32(priv, 0x17e280) >> 28; - ret = gf100_ltcg_init_tag_ram(pfb, priv); - if (ret) - return ret; - - priv->base.tags_alloc = gf100_ltcg_tags_alloc; - priv->base.tags_free = gf100_ltcg_tags_free; - priv->base.tags_clear = gm107_ltcg_tags_clear; - - nv_subdev(priv)->intr = gm107_ltcg_intr; - return 0; -} - -static int -gm107_ltcg_init(struct nouveau_object *object) -{ - struct nouveau_ltcg *ltcg = (struct nouveau_ltcg *)object; - struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg; - int ret; - - ret = nouveau_ltcg_init(ltcg); + ret = gf100_ltc_init_tag_ram(pfb, priv); if (ret) return ret; - nv_wr32(priv, 0x17e27c, priv->ltc_nr); - nv_wr32(priv, 0x17e278, priv->tag_base); return 0; } struct nouveau_oclass * -gm107_ltcg_oclass = &(struct nouveau_oclass) { - .handle = NV_SUBDEV(LTCG, 0xff), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = gm107_ltcg_ctor, - .dtor = gf100_ltcg_dtor, - .init = gm107_ltcg_init, - .fini = _nouveau_ltcg_fini, +gm107_ltc_oclass = &(struct nvkm_ltc_impl) { + .base.handle = NV_SUBDEV(LTC, 0xff), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = gm107_ltc_ctor, + .dtor = gf100_ltc_dtor, + .init = gm107_ltc_init, + .fini = _nvkm_ltc_fini, }, -}; + .intr = gm107_ltc_intr, + .cbc_clear = gm107_ltc_cbc_clear, + .cbc_wait = gm107_ltc_cbc_wait, + .zbc = 16, + .zbc_clear_color = gm107_ltc_zbc_clear_color, + .zbc_clear_depth = gm107_ltc_zbc_clear_depth, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h b/drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h new file mode 100644 index 000000000000..41f179d93da6 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h @@ -0,0 +1,71 @@ +#ifndef __NVKM_LTC_PRIV_H__ +#define __NVKM_LTC_PRIV_H__ + +#include <subdev/ltc.h> +#include <subdev/fb.h> + +#include <core/enum.h> + +struct nvkm_ltc_priv { + struct nouveau_ltc base; + u32 ltc_nr; + u32 lts_nr; + + u32 num_tags; + u32 tag_base; + struct nouveau_mm tags; + struct nouveau_mm_node *tag_ram; + + u32 zbc_color[NOUVEAU_LTC_MAX_ZBC_CNT][4]; + u32 zbc_depth[NOUVEAU_LTC_MAX_ZBC_CNT]; +}; + +#define nvkm_ltc_create(p,e,o,d) \ + nvkm_ltc_create_((p), (e), (o), sizeof(**d), (void **)d) +#define nvkm_ltc_destroy(p) ({ \ + struct nvkm_ltc_priv *_priv = (p); \ + _nvkm_ltc_dtor(nv_object(_priv)); \ +}) +#define nvkm_ltc_init(p) ({ \ + struct nvkm_ltc_priv *_priv = (p); \ + _nvkm_ltc_init(nv_object(_priv)); \ +}) +#define nvkm_ltc_fini(p,s) ({ \ + struct nvkm_ltc_priv *_priv = (p); \ + _nvkm_ltc_fini(nv_object(_priv), (s)); \ +}) + +int nvkm_ltc_create_(struct nouveau_object *, struct nouveau_object *, + struct nouveau_oclass *, int, void **); + +#define _nvkm_ltc_dtor _nouveau_subdev_dtor +int _nvkm_ltc_init(struct nouveau_object *); +#define _nvkm_ltc_fini _nouveau_subdev_fini + +int gf100_ltc_ctor(struct nouveau_object *, struct nouveau_object *, + struct nouveau_oclass *, void *, u32, + struct nouveau_object **); +void gf100_ltc_dtor(struct nouveau_object *); +int gf100_ltc_init_tag_ram(struct nouveau_fb *, struct nvkm_ltc_priv *); +int gf100_ltc_tags_alloc(struct nouveau_ltc *, u32, struct nouveau_mm_node **); +void gf100_ltc_tags_free(struct nouveau_ltc *, struct nouveau_mm_node **); + +struct nvkm_ltc_impl { + struct nouveau_oclass base; + void (*intr)(struct nouveau_subdev *); + + void (*cbc_clear)(struct nvkm_ltc_priv *, u32 start, u32 limit); + void (*cbc_wait)(struct nvkm_ltc_priv *); + + int zbc; + void (*zbc_clear_color)(struct nvkm_ltc_priv *, int, const u32[4]); + void (*zbc_clear_depth)(struct nvkm_ltc_priv *, int, const u32); +}; + +void gf100_ltc_intr(struct nouveau_subdev *); +void gf100_ltc_cbc_clear(struct nvkm_ltc_priv *, u32, u32); +void gf100_ltc_cbc_wait(struct nvkm_ltc_priv *); +void gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *, int, const u32[4]); +void gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *, int, const u32); + +#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltcg/gf100.h b/drivers/gpu/drm/nouveau/core/subdev/ltcg/gf100.h deleted file mode 100644 index 87b10b8412ea..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/ltcg/gf100.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef __NVKM_LTCG_PRIV_GF100_H__ -#define __NVKM_LTCG_PRIV_GF100_H__ - -#include <subdev/ltcg.h> - -struct gf100_ltcg_priv { - struct nouveau_ltcg base; - u32 ltc_nr; - u32 lts_nr; - u32 num_tags; - u32 tag_base; - struct nouveau_mm tags; - struct nouveau_mm_node *tag_ram; -}; - -void gf100_ltcg_dtor(struct nouveau_object *); -int gf100_ltcg_init_tag_ram(struct nouveau_fb *, struct gf100_ltcg_priv *); -int gf100_ltcg_tags_alloc(struct nouveau_ltcg *, u32, struct nouveau_mm_node **); -void gf100_ltcg_tags_free(struct nouveau_ltcg *, struct nouveau_mm_node **); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/base.c b/drivers/gpu/drm/nouveau/core/subdev/mc/base.c index 8a5555192fa5..ca7cee3a314a 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/base.c +++ b/drivers/gpu/drm/nouveau/core/subdev/mc/base.c @@ -22,9 +22,17 @@ * Authors: Ben Skeggs */ -#include <subdev/mc.h> +#include "priv.h" #include <core/option.h> +static inline void +nouveau_mc_unk260(struct nouveau_mc *pmc, u32 data) +{ + const struct nouveau_mc_oclass *impl = (void *)nv_oclass(pmc); + if (impl->unk260) + impl->unk260(pmc, data); +} + static inline u32 nouveau_mc_intr_mask(struct nouveau_mc *pmc) { @@ -114,6 +122,8 @@ nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine, if (ret) return ret; + pmc->unk260 = nouveau_mc_unk260; + if (nv_device_is_pci(device)) switch (device->pdev->device & 0x0ff0) { case 0x00f0: diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/gk20a.c b/drivers/gpu/drm/nouveau/core/subdev/mc/gk20a.c new file mode 100644 index 000000000000..b8d6cb435d0a --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/mc/gk20a.c @@ -0,0 +1,38 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "nv04.h" + +struct nouveau_oclass * +gk20a_mc_oclass = &(struct nouveau_mc_oclass) { + .base.handle = NV_SUBDEV(MC, 0xea), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv04_mc_ctor, + .dtor = _nouveau_mc_dtor, + .init = nv50_mc_init, + .fini = _nouveau_mc_fini, + }, + .intr = nvc0_mc_intr, + .msi_rearm = nv40_mc_msi_rearm, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h index 81a408e7d034..4d9ea46c47c2 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h +++ b/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h @@ -1,7 +1,7 @@ #ifndef __NVKM_MC_NV04_H__ #define __NVKM_MC_NV04_H__ -#include <subdev/mc.h> +#include "priv.h" struct nv04_mc_priv { struct nouveau_mc base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c index f9c6a678b47d..15d41dc176ff 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c @@ -41,7 +41,7 @@ nvc0_mc_intr[] = { { 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */ { 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */ { 0x01000000, NVDEV_SUBDEV_PWR }, - { 0x02000000, NVDEV_SUBDEV_LTCG }, + { 0x02000000, NVDEV_SUBDEV_LTC }, { 0x08000000, NVDEV_SUBDEV_FB }, { 0x10000000, NVDEV_SUBDEV_BUS }, { 0x40000000, NVDEV_SUBDEV_IBUS }, @@ -56,6 +56,12 @@ nvc0_mc_msi_rearm(struct nouveau_mc *pmc) nv_wr32(priv, 0x088704, 0x00000000); } +void +nvc0_mc_unk260(struct nouveau_mc *pmc, u32 data) +{ + nv_wr32(pmc, 0x000260, data); +} + struct nouveau_oclass * nvc0_mc_oclass = &(struct nouveau_mc_oclass) { .base.handle = NV_SUBDEV(MC, 0xc0), @@ -67,4 +73,5 @@ nvc0_mc_oclass = &(struct nouveau_mc_oclass) { }, .intr = nvc0_mc_intr, .msi_rearm = nvc0_mc_msi_rearm, + .unk260 = nvc0_mc_unk260, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc3.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nvc3.c index 837e545aeb9f..68b5f61aadb5 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc3.c +++ b/drivers/gpu/drm/nouveau/core/subdev/mc/nvc3.c @@ -35,4 +35,5 @@ nvc3_mc_oclass = &(struct nouveau_mc_oclass) { }, .intr = nvc0_mc_intr, .msi_rearm = nv40_mc_msi_rearm, + .unk260 = nvc0_mc_unk260, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/priv.h b/drivers/gpu/drm/nouveau/core/subdev/mc/priv.h new file mode 100644 index 000000000000..911e66392587 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/mc/priv.h @@ -0,0 +1,38 @@ +#ifndef __NVKM_MC_PRIV_H__ +#define __NVKM_MC_PRIV_H__ + +#include <subdev/mc.h> + +#define nouveau_mc_create(p,e,o,d) \ + nouveau_mc_create_((p), (e), (o), sizeof(**d), (void **)d) +#define nouveau_mc_destroy(p) ({ \ + struct nouveau_mc *pmc = (p); _nouveau_mc_dtor(nv_object(pmc)); \ +}) +#define nouveau_mc_init(p) ({ \ + struct nouveau_mc *pmc = (p); _nouveau_mc_init(nv_object(pmc)); \ +}) +#define nouveau_mc_fini(p,s) ({ \ + struct nouveau_mc *pmc = (p); _nouveau_mc_fini(nv_object(pmc), (s)); \ +}) + +int nouveau_mc_create_(struct nouveau_object *, struct nouveau_object *, + struct nouveau_oclass *, int, void **); +void _nouveau_mc_dtor(struct nouveau_object *); +int _nouveau_mc_init(struct nouveau_object *); +int _nouveau_mc_fini(struct nouveau_object *, bool); + +struct nouveau_mc_intr { + u32 stat; + u32 unit; +}; + +struct nouveau_mc_oclass { + struct nouveau_oclass base; + const struct nouveau_mc_intr *intr; + void (*msi_rearm)(struct nouveau_mc *); + void (*unk260)(struct nouveau_mc *, u32); +}; + +void nvc0_mc_unk260(struct nouveau_mc *, u32); + +#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c index d4fd3bc9c66f..0ab55f27ec45 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c @@ -22,9 +22,18 @@ * Authors: Ben Skeggs */ -#include <subdev/pwr.h> #include <subdev/timer.h> +#include "priv.h" + +static void +nouveau_pwr_pgob(struct nouveau_pwr *ppwr, bool enable) +{ + const struct nvkm_pwr_impl *impl = (void *)nv_oclass(ppwr); + if (impl->pgob) + impl->pgob(ppwr, enable); +} + static int nouveau_pwr_send(struct nouveau_pwr *ppwr, u32 reply[2], u32 process, u32 message, u32 data0, u32 data1) @@ -177,6 +186,7 @@ _nouveau_pwr_fini(struct nouveau_object *object, bool suspend) int _nouveau_pwr_init(struct nouveau_object *object) { + const struct nvkm_pwr_impl *impl = (void *)object->oclass; struct nouveau_pwr *ppwr = (void *)object; int ret, i; @@ -186,24 +196,27 @@ _nouveau_pwr_init(struct nouveau_object *object) nv_subdev(ppwr)->intr = nouveau_pwr_intr; ppwr->message = nouveau_pwr_send; + ppwr->pgob = nouveau_pwr_pgob; /* prevent previous ucode from running, wait for idle, reset */ nv_wr32(ppwr, 0x10a014, 0x0000ffff); /* INTR_EN_CLR = ALL */ nv_wait(ppwr, 0x10a04c, 0xffffffff, 0x00000000); nv_mask(ppwr, 0x000200, 0x00002000, 0x00000000); nv_mask(ppwr, 0x000200, 0x00002000, 0x00002000); + nv_rd32(ppwr, 0x000200); + nv_wait(ppwr, 0x10a10c, 0x00000006, 0x00000000); /* upload data segment */ nv_wr32(ppwr, 0x10a1c0, 0x01000000); - for (i = 0; i < ppwr->data.size / 4; i++) - nv_wr32(ppwr, 0x10a1c4, ppwr->data.data[i]); + for (i = 0; i < impl->data.size / 4; i++) + nv_wr32(ppwr, 0x10a1c4, impl->data.data[i]); /* upload code segment */ nv_wr32(ppwr, 0x10a180, 0x01000000); - for (i = 0; i < ppwr->code.size / 4; i++) { + for (i = 0; i < impl->code.size / 4; i++) { if ((i & 0x3f) == 0) nv_wr32(ppwr, 0x10a188, i >> 6); - nv_wr32(ppwr, 0x10a184, ppwr->code.data[i]); + nv_wr32(ppwr, 0x10a184, impl->code.data[i]); } /* start it running */ @@ -245,3 +258,15 @@ nouveau_pwr_create_(struct nouveau_object *parent, init_waitqueue_head(&ppwr->recv.wait); return 0; } + +int +_nouveau_pwr_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nouveau_pwr *ppwr; + int ret = nouveau_pwr_create(parent, engine, oclass, &ppwr); + *pobject = nv_object(ppwr); + return ret; +} diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/arith.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/arith.fuc new file mode 100644 index 000000000000..214a6d9e088d --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/arith.fuc @@ -0,0 +1,94 @@ +/* + * Copyright 2014 Martin Peres <martin.peres@free.fr> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the folloing conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Martin Peres + */ + +/****************************************************************************** + * arith data segment + *****************************************************************************/ +#ifdef INCLUDE_PROC +#endif + +#ifdef INCLUDE_DATA +#endif + +/****************************************************************************** + * arith code segment + *****************************************************************************/ +#ifdef INCLUDE_CODE + +// does a 32x32 -> 64 multiplication +// +// A * B = A_lo * B_lo +// + ( A_hi * B_lo ) << 16 +// + ( A_lo * B_hi ) << 16 +// + ( A_hi * B_hi ) << 32 +// +// $r15 - current +// $r14 - A +// $r13 - B +// $r12 - mul_lo (return) +// $r11 - mul_hi (return) +// $r0 - zero +mulu32_32_64: + push $r1 // A_hi + push $r2 // B_hi + push $r3 // tmp0 + push $r4 // tmp1 + + shr b32 $r1 $r14 16 + shr b32 $r2 $r13 16 + + clear b32 $r12 + clear b32 $r11 + + // A_lo * B_lo + mulu $r12 $r14 $r13 + + // ( A_hi * B_lo ) << 16 + mulu $r3 $r1 $r13 // tmp0 = A_hi * B_lo + mov b32 $r4 $r3 + and $r3 0xffff // tmp0 = tmp0_lo + shl b32 $r3 16 + shr b32 $r4 16 // tmp1 = tmp0_hi + add b32 $r12 $r3 + adc b32 $r11 $r4 + + // ( A_lo * B_hi ) << 16 + mulu $r3 $r14 $r2 // tmp0 = A_lo * B_hi + mov b32 $r4 $r3 + and $r3 0xffff // tmp0 = tmp0_lo + shl b32 $r3 16 + shr b32 $r4 16 // tmp1 = tmp0_hi + add b32 $r12 $r3 + adc b32 $r11 $r4 + + // ( A_hi * B_hi ) << 32 + mulu $r3 $r1 $r2 // tmp0 = A_hi * B_hi + add b32 $r11 $r3 + + pop $r4 + pop $r3 + pop $r2 + pop $r1 + ret +#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc index 8f29badd785f..5cf5be63cbef 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc @@ -98,12 +98,16 @@ wr32: // $r14 - ns // $r0 - zero nsec: + push $r9 + push $r8 nv_iord($r8, NV_PPWR_TIMER_LOW) nsec_loop: nv_iord($r9, NV_PPWR_TIMER_LOW) sub b32 $r9 $r8 cmp b32 $r9 $r14 bra l #nsec_loop + pop $r8 + pop $r9 ret // busy-wait for a period of time @@ -115,6 +119,8 @@ nsec: // $r11 - timeout (ns) // $r0 - zero wait: + push $r9 + push $r8 nv_iord($r8, NV_PPWR_TIMER_LOW) wait_loop: nv_rd32($r10, $r14) @@ -126,6 +132,8 @@ wait: cmp b32 $r9 $r11 bra l #wait_loop wait_done: + pop $r8 + pop $r9 ret // $r15 - current (kern) @@ -242,12 +250,89 @@ intr: bclr $flags $p0 iret -// request the current process be sent a message after a timeout expires +// calculate the number of ticks in the specified nanoseconds delay +// +// $r15 - current +// $r14 - ns +// $r14 - ticks (return) +// $r0 - zero +ticks_from_ns: + push $r12 + push $r11 + + /* try not losing precision (multiply then divide) */ + imm32($r13, HW_TICKS_PER_US) + call #mulu32_32_64 + + /* use an immeditate, it's ok because HW_TICKS_PER_US < 16 bits */ + div $r12 $r12 1000 + + /* check if there wasn't any overflow */ + cmpu b32 $r11 0 + bra e #ticks_from_ns_quit + + /* let's divide then multiply, too bad for the precision! */ + div $r14 $r14 1000 + imm32($r13, HW_TICKS_PER_US) + call #mulu32_32_64 + + /* this cannot overflow as long as HW_TICKS_PER_US < 1000 */ + +ticks_from_ns_quit: + mov b32 $r14 $r12 + pop $r11 + pop $r12 + ret + +// calculate the number of ticks in the specified microsecond delay +// +// $r15 - current +// $r14 - us +// $r14 - ticks (return) +// $r0 - zero +ticks_from_us: + push $r12 + push $r11 + + /* simply multiply $us by HW_TICKS_PER_US */ + imm32($r13, HW_TICKS_PER_US) + call #mulu32_32_64 + mov b32 $r14 $r12 + + /* check if there wasn't any overflow */ + cmpu b32 $r11 0 + bra e #ticks_from_us_quit + + /* Overflow! */ + clear b32 $r14 + +ticks_from_us_quit: + pop $r11 + pop $r12 + ret + +// calculate the number of ticks in the specified microsecond delay // // $r15 - current // $r14 - ticks +// $r14 - us (return) +// $r0 - zero +ticks_to_us: + /* simply divide $ticks by HW_TICKS_PER_US */ + imm32($r13, HW_TICKS_PER_US) + div $r14 $r14 $r13 + + ret + +// request the current process be sent a message after a timeout expires +// +// $r15 - current +// $r14 - ticks (make sure it is < 2^31 to avoid any possible overflow) // $r0 - zero timer: + push $r9 + push $r8 + // interrupts off to prevent racing with timer isr bclr $flags ie0 @@ -255,13 +340,22 @@ timer: ld b32 $r8 D[$r15 + #proc_time] cmp b32 $r8 0 bra g #timer_done - st b32 D[$r15 + #proc_time] $r14 - // halt watchdog timer temporarily and check for a pending - // interrupt. if there's one already pending, we can just - // bail since the timer isr will queue the next soonest - // right after it's done + // halt watchdog timer temporarily + clear b32 $r8 nv_iowr(NV_PPWR_WATCHDOG_ENABLE, $r8) + + // find out how much time elapsed since the last update + // of the watchdog and add this time to the wanted ticks + nv_iord($r8, NV_PPWR_WATCHDOG_TIME) + ld b32 $r9 D[$r0 + #time_prev] + sub b32 $r9 $r8 + add b32 $r14 $r9 + st b32 D[$r15 + #proc_time] $r14 + + // check for a pending interrupt. if there's one already + // pending, we can just bail since the timer isr will + // queue the next soonest right after it's done nv_iord($r8, NV_PPWR_INTR) and $r8 NV_PPWR_INTR_WATCHDOG bra nz #timer_enable @@ -272,10 +366,10 @@ timer: cmp b32 $r14 $r0 bra e #timer_reset cmp b32 $r14 $r8 - bra l #timer_done - timer_reset: - nv_iowr(NV_PPWR_WATCHDOG_TIME, $r14) - st b32 D[$r0 + #time_prev] $r14 + bra g #timer_enable + timer_reset: + nv_iowr(NV_PPWR_WATCHDOG_TIME, $r14) + st b32 D[$r0 + #time_prev] $r14 // re-enable the watchdog timer timer_enable: @@ -285,6 +379,9 @@ timer: // interrupts back on timer_done: bset $flags ie0 + + pop $r8 + pop $r9 ret // send message to another process @@ -371,6 +468,9 @@ send: // $r14 - process // $r0 - zero recv: + push $r9 + push $r8 + ld b32 $r8 D[$r14 + #proc_qget] ld b32 $r9 D[$r14 + #proc_qput] bclr $flags $p1 @@ -403,6 +503,8 @@ recv: bset $flags $p1 pop $r15 recv_done: + pop $r8 + pop $r9 ret init: diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc index e2a63ac5422b..96fc984dafdc 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc @@ -242,7 +242,7 @@ */ push reg /* */ pop $r13 /* */ pop $r14 /* -*/ call(wr32) /* +*/ call(wr32) #else #define nv_wr32(addr,reg) /* */ sethi $r0 0x14000000 /* @@ -250,3 +250,23 @@ */ st b32 D[$r0] reg /* */ clear b32 $r0 #endif + +#define st(size, addr, reg) /* +*/ movw $r0 addr /* +*/ st size D[$r0] reg /* +*/ clear b32 $r0 + +#define ld(size, reg, addr) /* +*/ movw $r0 addr /* +*/ ld size reg D[$r0] /* +*/ clear b32 $r0 + +// does a 64+64 -> 64 unsigned addition (C = A + B) +#define addu64(reg_a_c_hi, reg_a_c_lo, b_hi, b_lo) /* +*/ add b32 reg_a_c_lo b_lo /* +*/ adc b32 reg_a_c_hi b_hi + +// does a 64+64 -> 64 substraction (C = A - B) +#define subu64(reg_a_c_hi, reg_a_c_lo, b_hi, b_lo) /* +*/ sub b32 reg_a_c_lo b_lo /* +*/ sbb b32 reg_a_c_hi b_hi diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc index d43741eccb11..e89789a53b80 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc @@ -43,17 +43,23 @@ process(PROC_MEMX, #memx_init, #memx_recv) */ .b32 func memx_func_head: -handler(ENTER , 0x0001, 0x0000, #memx_func_enter) +handler(ENTER , 0x0000, 0x0000, #memx_func_enter) memx_func_next: handler(LEAVE , 0x0000, 0x0000, #memx_func_leave) handler(WR32 , 0x0000, 0x0002, #memx_func_wr32) handler(WAIT , 0x0004, 0x0000, #memx_func_wait) handler(DELAY , 0x0001, 0x0000, #memx_func_delay) +handler(VBLANK, 0x0001, 0x0000, #memx_func_wait_vblank) memx_func_tail: .equ #memx_func_size #memx_func_next - #memx_func_head .equ #memx_func_num (#memx_func_tail - #memx_func_head) / #memx_func_size +memx_ts_start: +.b32 0 +memx_ts_end: +.b32 0 + memx_data_head: .skip 0x0800 memx_data_tail: @@ -67,19 +73,44 @@ memx_data_tail: // // $r15 - current (memx) // $r4 - packet length -// +00: bitmask of heads to wait for vblank on // $r3 - opcode desciption // $r0 - zero memx_func_enter: +#if NVKM_PPWR_CHIPSET == GT215 + movw $r8 0x1610 + nv_rd32($r7, $r8) + imm32($r6, 0xfffffffc) + and $r7 $r6 + movw $r6 0x2 + or $r7 $r6 + nv_wr32($r8, $r7) +#else + movw $r6 0x001620 + imm32($r7, ~0x00000aa2); + nv_rd32($r8, $r6) + and $r8 $r7 + nv_wr32($r6, $r8) + + imm32($r7, ~0x00000001) + nv_rd32($r8, $r6) + and $r8 $r7 + nv_wr32($r6, $r8) + + movw $r6 0x0026f0 + nv_rd32($r8, $r6) + and $r8 $r7 + nv_wr32($r6, $r8) +#endif + mov $r6 NV_PPWR_OUTPUT_SET_FB_PAUSE nv_iowr(NV_PPWR_OUTPUT_SET, $r6) memx_func_enter_wait: nv_iord($r6, NV_PPWR_OUTPUT) and $r6 NV_PPWR_OUTPUT_FB_PAUSE bra z #memx_func_enter_wait - //XXX: TODO - ld b32 $r6 D[$r1 + 0x00] - add b32 $r1 0x04 + + nv_iord($r6, NV_PPWR_TIMER_LOW) + st b32 D[$r0 + #memx_ts_start] $r6 ret // description @@ -89,14 +120,93 @@ memx_func_enter: // $r3 - opcode desciption // $r0 - zero memx_func_leave: + nv_iord($r6, NV_PPWR_TIMER_LOW) + st b32 D[$r0 + #memx_ts_end] $r6 + mov $r6 NV_PPWR_OUTPUT_CLR_FB_PAUSE nv_iowr(NV_PPWR_OUTPUT_CLR, $r6) memx_func_leave_wait: nv_iord($r6, NV_PPWR_OUTPUT) and $r6 NV_PPWR_OUTPUT_FB_PAUSE bra nz #memx_func_leave_wait + +#if NVKM_PPWR_CHIPSET == GT215 + movw $r8 0x1610 + nv_rd32($r7, $r8) + imm32($r6, 0xffffffcc) + and $r7 $r6 + nv_wr32($r8, $r7) +#else + movw $r6 0x0026f0 + imm32($r7, 0x00000001) + nv_rd32($r8, $r6) + or $r8 $r7 + nv_wr32($r6, $r8) + + movw $r6 0x001620 + nv_rd32($r8, $r6) + or $r8 $r7 + nv_wr32($r6, $r8) + + imm32($r7, 0x00000aa2); + nv_rd32($r8, $r6) + or $r8 $r7 + nv_wr32($r6, $r8) +#endif + ret + +#if NVKM_PPWR_CHIPSET < GF119 +// description +// +// $r15 - current (memx) +// $r4 - packet length +// +00: head to wait for vblank on +// $r3 - opcode desciption +// $r0 - zero +memx_func_wait_vblank: + ld b32 $r6 D[$r1 + 0x00] + cmp b32 $r6 0x0 + bra z #memx_func_wait_vblank_head0 + cmp b32 $r6 0x1 + bra z #memx_func_wait_vblank_head1 + bra #memx_func_wait_vblank_fini + + memx_func_wait_vblank_head1: + movw $r7 0x20 + bra #memx_func_wait_vblank_0 + + memx_func_wait_vblank_head0: + movw $r7 0x8 + + memx_func_wait_vblank_0: + nv_iord($r6, NV_PPWR_INPUT) + and $r6 $r7 + bra nz #memx_func_wait_vblank_0 + + memx_func_wait_vblank_1: + nv_iord($r6, NV_PPWR_INPUT) + and $r6 $r7 + bra z #memx_func_wait_vblank_1 + + memx_func_wait_vblank_fini: + add b32 $r1 0x4 + ret + +#else + +// XXX: currently no-op +// +// $r15 - current (memx) +// $r4 - packet length +// +00: head to wait for vblank on +// $r3 - opcode desciption +// $r0 - zero +memx_func_wait_vblank: + add b32 $r1 0x4 ret +#endif + // description // // $r15 - current (memx) @@ -160,14 +270,17 @@ memx_exec: push $r13 mov b32 $r1 $r12 mov b32 $r2 $r11 + memx_exec_next: - // fetch the packet header, and locate opcode info + // fetch the packet header ld b32 $r3 D[$r1] add b32 $r1 4 - shr b32 $r4 $r3 16 - mulu $r3 #memx_func_size + extr $r4 $r3 16:31 + extr $r3 $r3 0:15 // execute the opcode handler + sub b32 $r3 1 + mulu $r3 #memx_func_size ld b32 $r5 D[$r3 + #memx_func_head + #memx_func] call $r5 @@ -176,6 +289,10 @@ memx_exec: bra l #memx_exec_next // send completion reply + ld b32 $r11 D[$r0 + #memx_ts_start] + ld b32 $r12 D[$r0 + #memx_ts_end] + sub b32 $r12 $r11 + nv_iord($r11, NV_PPWR_INPUT) pop $r13 pop $r14 call(send) diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc index 17a8a383d91a..b439519ec866 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc @@ -23,6 +23,7 @@ */ #define NVKM_PPWR_CHIPSET GK208 +#define HW_TICKS_PER_US 324 #define NVKM_FALCON_PC24 #define NVKM_FALCON_UNSHIFTED_IO @@ -34,6 +35,7 @@ .section #nv108_pwr_data #define INCLUDE_PROC #include "kernel.fuc" +#include "arith.fuc" #include "host.fuc" #include "memx.fuc" #include "perf.fuc" @@ -44,6 +46,7 @@ #define INCLUDE_DATA #include "kernel.fuc" +#include "arith.fuc" #include "host.fuc" #include "memx.fuc" #include "perf.fuc" @@ -56,6 +59,7 @@ .section #nv108_pwr_code #define INCLUDE_CODE #include "kernel.fuc" +#include "arith.fuc" #include "host.fuc" #include "memx.fuc" #include "perf.fuc" diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h index 39a5dc150a05..4d278a96b2bb 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h @@ -24,8 +24,8 @@ uint32_t nv108_pwr_data[] = { 0x00000000, /* 0x0058: proc_list_head */ 0x54534f48, - 0x00000379, - 0x0000032a, + 0x00000453, + 0x00000404, 0x00000000, 0x00000000, 0x00000000, @@ -46,8 +46,8 @@ uint32_t nv108_pwr_data[] = { 0x00000000, 0x00000000, 0x584d454d, - 0x0000046f, - 0x00000461, + 0x0000061c, + 0x0000060e, 0x00000000, 0x00000000, 0x00000000, @@ -68,8 +68,8 @@ uint32_t nv108_pwr_data[] = { 0x00000000, 0x00000000, 0x46524550, - 0x00000473, - 0x00000471, + 0x00000620, + 0x0000061e, 0x00000000, 0x00000000, 0x00000000, @@ -90,8 +90,8 @@ uint32_t nv108_pwr_data[] = { 0x00000000, 0x00000000, 0x5f433249, - 0x00000877, - 0x0000071e, + 0x00000a24, + 0x000008cb, 0x00000000, 0x00000000, 0x00000000, @@ -112,8 +112,8 @@ uint32_t nv108_pwr_data[] = { 0x00000000, 0x00000000, 0x54534554, - 0x00000898, - 0x00000879, + 0x00000a45, + 0x00000a26, 0x00000000, 0x00000000, 0x00000000, @@ -134,8 +134,8 @@ uint32_t nv108_pwr_data[] = { 0x00000000, 0x00000000, 0x454c4449, - 0x000008a3, - 0x000008a1, + 0x00000a50, + 0x00000a4e, 0x00000000, 0x00000000, 0x00000000, @@ -227,24 +227,31 @@ uint32_t nv108_pwr_data[] = { 0x00000000, 0x00000000, /* 0x0370: memx_func_head */ - 0x00010000, - 0x00000000, - 0x000003a9, -/* 0x037c: memx_func_next */ 0x00000001, 0x00000000, - 0x000003c7, + 0x00000483, +/* 0x037c: memx_func_next */ 0x00000002, + 0x00000000, + 0x00000500, + 0x00000003, 0x00000002, - 0x000003df, - 0x00040003, + 0x00000580, + 0x00040004, + 0x00000000, + 0x0000059d, + 0x00010005, + 0x00000000, + 0x000005b7, + 0x00010006, + 0x00000000, + 0x0000057b, +/* 0x03b8: memx_func_tail */ +/* 0x03b8: memx_ts_start */ 0x00000000, - 0x00000407, - 0x00010004, +/* 0x03bc: memx_ts_end */ 0x00000000, - 0x00000421, -/* 0x03ac: memx_func_tail */ -/* 0x03ac: memx_data_head */ +/* 0x03c0: memx_data_head */ 0x00000000, 0x00000000, 0x00000000, @@ -757,8 +764,8 @@ uint32_t nv108_pwr_data[] = { 0x00000000, 0x00000000, 0x00000000, -/* 0x0bac: memx_data_tail */ -/* 0x0bac: i2c_scl_map */ +/* 0x0bc0: memx_data_tail */ +/* 0x0bc0: i2c_scl_map */ 0x00000400, 0x00000800, 0x00001000, @@ -769,7 +776,7 @@ uint32_t nv108_pwr_data[] = { 0x00020000, 0x00040000, 0x00080000, -/* 0x0bd4: i2c_sda_map */ +/* 0x0be8: i2c_sda_map */ 0x00100000, 0x00200000, 0x00400000, @@ -781,10 +788,69 @@ uint32_t nv108_pwr_data[] = { 0x10000000, 0x20000000, 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, }; uint32_t nv108_pwr_code[] = { - 0x02910ef5, + 0x031c0ef5, /* 0x0004: rd32 */ 0xf607a040, 0x04bd000e, @@ -812,15 +878,18 @@ uint32_t nv108_pwr_code[] = { 0x7000d4f1, 0xf8f61bf4, /* 0x005d: nsec */ - 0xcf2c0800, -/* 0x0062: nsec_loop */ + 0xf990f900, + 0xcf2c0880, +/* 0x0066: nsec_loop */ 0x2c090088, 0xbb0099cf, 0x9ea60298, - 0xf8f61ef4, -/* 0x0071: wait */ - 0xcf2c0800, -/* 0x0076: wait_loop */ + 0xfcf61ef4, + 0xf890fc80, +/* 0x0079: wait */ + 0xf990f900, + 0xcf2c0880, +/* 0x0082: wait_loop */ 0xeeb20088, 0x0000047e, 0xadfddab2, @@ -828,28 +897,29 @@ uint32_t nv108_pwr_code[] = { 0x2c09100b, 0xbb0099cf, 0x9ba60298, -/* 0x0093: wait_done */ - 0xf8e61ef4, -/* 0x0095: intr_watchdog */ +/* 0x009f: wait_done */ + 0xfce61ef4, + 0xf890fc80, +/* 0x00a5: intr_watchdog */ 0x03e99800, 0xf40096b0, 0x0a98280b, 0x029abb9a, 0x0d0e1cf4, - 0x01de7e01, + 0x02617e01, 0xf494bd00, -/* 0x00b2: intr_watchdog_next_time */ +/* 0x00c2: intr_watchdog_next_time */ 0x0a98140e, 0x00a6b09b, 0xa6080bf4, 0x061cf49a, -/* 0x00c0: intr_watchdog_next_time_set */ -/* 0x00c3: intr_watchdog_next_proc */ +/* 0x00d0: intr_watchdog_next_time_set */ +/* 0x00d3: intr_watchdog_next_proc */ 0xb59b09b5, 0xe0b603e9, 0x68e6b158, 0xc81bf402, -/* 0x00d2: intr */ +/* 0x00e2: intr */ 0x00f900f8, 0x80f904bd, 0xa0f990f9, @@ -865,13 +935,13 @@ uint32_t nv108_pwr_code[] = { 0xc40088cf, 0x0bf40289, 0x9b00b51f, - 0x957e580e, + 0xa57e580e, 0x09980000, 0x0096b09b, 0x000d0bf4, 0x0009f634, 0x09b504bd, -/* 0x0125: intr_skip_watchdog */ +/* 0x0135: intr_skip_watchdog */ 0x0089e49a, 0x360bf408, 0xcf068849, @@ -881,20 +951,20 @@ uint32_t nv108_pwr_code[] = { 0xc0f900cc, 0xf14f484e, 0x0d5453e3, - 0x023f7e00, + 0x02c27e00, 0x40c0fc00, 0x0cf604c0, -/* 0x0157: intr_subintr_skip_fifo */ +/* 0x0167: intr_subintr_skip_fifo */ 0x4004bd00, 0x09f60688, -/* 0x015f: intr_skip_subintr */ +/* 0x016f: intr_skip_subintr */ 0xc404bd00, 0x0bf42089, 0xbfa4f107, -/* 0x0169: intr_skip_pause */ +/* 0x0179: intr_skip_pause */ 0x4089c4ff, 0xf1070bf4, -/* 0x0173: intr_skip_user0 */ +/* 0x0183: intr_skip_user0 */ 0x00ffbfa4, 0x0008f604, 0x80fc04bd, @@ -904,551 +974,682 @@ uint32_t nv108_pwr_code[] = { 0xfca0fcb0, 0xfc80fc90, 0x0032f400, -/* 0x0196: timer */ - 0x32f401f8, - 0x03f89810, - 0xf40086b0, - 0xfeb53a1c, - 0xf6380003, +/* 0x01a6: ticks_from_ns */ + 0xc0f901f8, + 0xd7f1b0f9, + 0xd3f00144, + 0x7721f500, + 0xe8ccec03, + 0x00b4b003, + 0xec120bf4, + 0xf103e8ee, + 0xf00144d7, + 0x21f500d3, +/* 0x01ce: ticks_from_ns_quit */ + 0xceb20377, + 0xc0fcb0fc, +/* 0x01d6: ticks_from_us */ + 0xc0f900f8, + 0xd7f1b0f9, + 0xd3f00144, + 0x7721f500, + 0xb0ceb203, + 0x0bf400b4, +/* 0x01ef: ticks_from_us_quit */ + 0xfce4bd05, + 0xf8c0fcb0, +/* 0x01f5: ticks_to_us */ + 0x44d7f100, + 0x00d3f001, + 0xf8ecedff, +/* 0x0201: timer */ + 0xf990f900, + 0x1032f480, + 0xb003f898, + 0x1cf40086, + 0x0084bd4a, + 0x0008f638, + 0x340804bd, + 0x980088cf, + 0x98bb9a09, + 0x00e9bb02, + 0x0803feb5, + 0x0088cf08, + 0xf40284f0, + 0x34081c1b, + 0xa60088cf, + 0x080bf4e0, + 0x1cf4e8a6, +/* 0x0245: timer_reset */ + 0xf634000d, + 0x04bd000e, +/* 0x024f: timer_enable */ + 0x089a0eb5, + 0xf6380001, 0x04bd0008, - 0x88cf0808, - 0x0284f000, - 0x081c1bf4, - 0x0088cf34, - 0x0bf4e0a6, - 0xf4e8a608, -/* 0x01c6: timer_reset */ - 0x3400161e, - 0xbd000ef6, - 0x9a0eb504, -/* 0x01d0: timer_enable */ - 0x38000108, - 0xbd0008f6, -/* 0x01d9: timer_done */ - 0x1031f404, -/* 0x01de: send_proc */ - 0x80f900f8, - 0xe89890f9, - 0x04e99805, - 0xa60486f0, - 0x2a0bf489, - 0x940398c4, - 0x80b60488, - 0x008ebb18, - 0xb500fa98, - 0x8db5008a, - 0x028cb501, - 0xb6038bb5, - 0x94f00190, - 0x04e9b507, -/* 0x0217: send_done */ - 0xfc0231f4, - 0xf880fc90, -/* 0x021d: find */ - 0x0880f900, - 0x0131f458, -/* 0x0224: find_loop */ - 0xa6008a98, - 0x100bf4ae, - 0xb15880b6, - 0xf4026886, - 0x32f4f11b, -/* 0x0239: find_done */ - 0xfc8eb201, -/* 0x023f: send */ - 0x7e00f880, - 0xf400021d, - 0x00f89b01, -/* 0x0248: recv */ - 0x9805e898, - 0x32f404e9, - 0xf489a601, - 0x89c43c0b, - 0x0180b603, - 0xb50784f0, - 0xea9805e8, - 0xfef0f902, - 0xf0f9018f, - 0x9994efb2, - 0x00e9bb04, - 0x9818e0b6, - 0xec9803eb, - 0x01ed9802, - 0xf900ee98, - 0xfef0fca5, - 0x31f400f8, -/* 0x028f: recv_done */ - 0xf8f0fc01, -/* 0x0291: init */ - 0x01084100, - 0xe70011cf, - 0xb6010911, - 0x14fe0814, - 0x00e04100, - 0x000013f0, - 0x0001f61c, - 0xff0104bd, - 0x01f61400, - 0x0104bd00, - 0x0015f102, - 0xf6100008, - 0x04bd0001, - 0xf000d241, - 0x10fe0013, - 0x1031f400, - 0x38000101, +/* 0x0258: timer_done */ + 0xfc1031f4, + 0xf890fc80, +/* 0x0261: send_proc */ + 0xf980f900, + 0x05e89890, + 0xf004e998, + 0x89a60486, + 0xc42a0bf4, + 0x88940398, + 0x1880b604, + 0x98008ebb, + 0x8ab500fa, + 0x018db500, + 0xb5028cb5, + 0x90b6038b, + 0x0794f001, + 0xf404e9b5, +/* 0x029a: send_done */ + 0x90fc0231, + 0x00f880fc, +/* 0x02a0: find */ + 0x580880f9, +/* 0x02a7: find_loop */ + 0x980131f4, + 0xaea6008a, + 0xb6100bf4, + 0x86b15880, + 0x1bf40268, + 0x0132f4f1, +/* 0x02bc: find_done */ + 0x80fc8eb2, +/* 0x02c2: send */ + 0xa07e00f8, + 0x01f40002, +/* 0x02cb: recv */ + 0xf900f89b, + 0x9880f990, + 0xe99805e8, + 0x0132f404, + 0x0bf489a6, + 0x0389c43c, + 0xf00180b6, + 0xe8b50784, + 0x02ea9805, + 0x8ffef0f9, + 0xb2f0f901, + 0x049994ef, + 0xb600e9bb, + 0xeb9818e0, + 0x02ec9803, + 0x9801ed98, + 0xa5f900ee, + 0xf8fef0fc, + 0x0131f400, +/* 0x0316: recv_done */ + 0x80fcf0fc, + 0x00f890fc, +/* 0x031c: init */ + 0xcf010841, + 0x11e70011, + 0x14b60109, + 0x0014fe08, + 0xf000e041, + 0x1c000013, 0xbd0001f6, -/* 0x02db: init_proc */ - 0x98580f04, - 0x16b001f1, - 0xfa0bf400, - 0xf0b615f9, - 0xf20ef458, -/* 0x02ec: host_send */ - 0xcf04b041, - 0xa0420011, - 0x0022cf04, - 0x0bf412a6, - 0x071ec42e, - 0xb704ee94, - 0x980270e0, - 0xec9803eb, - 0x01ed9802, - 0x7e00ee98, - 0xb600023f, - 0x1ec40110, - 0x04b0400f, - 0xbd000ef6, - 0xc70ef404, -/* 0x0328: host_send_done */ -/* 0x032a: host_recv */ - 0x494100f8, - 0x5413f14e, - 0xf4e1a652, -/* 0x0336: host_recv_wait */ - 0xcc41b90b, - 0x0011cf04, - 0xcf04c842, - 0x16f00022, - 0xf412a608, - 0x23c4ef0b, - 0x0434b607, - 0x02f030b7, - 0xb5033bb5, - 0x3db5023c, - 0x003eb501, - 0xf00120b6, - 0xc8400f24, - 0x0002f604, - 0x400204bd, - 0x02f60000, - 0xf804bd00, -/* 0x0379: host_init */ - 0x00804100, - 0xf11014b6, - 0x40027015, - 0x01f604d0, + 0x00ff0104, + 0x0001f614, + 0x020104bd, + 0x080015f1, + 0x01f61000, 0x4104bd00, + 0x13f000e2, + 0x0010fe00, + 0x011031f4, + 0xf6380001, + 0x04bd0001, +/* 0x0366: init_proc */ + 0xf198580f, + 0x0016b001, + 0xf9fa0bf4, + 0x58f0b615, +/* 0x0377: mulu32_32_64 */ + 0xf9f20ef4, + 0xf920f910, + 0x9540f930, + 0xd29510e1, + 0xbdc4bd10, + 0xc0edffb4, + 0xb2301dff, + 0xff34f134, + 0x1034b6ff, + 0xbb1045b6, + 0xb4bb00c3, + 0x30e2ff01, + 0x34f134b2, + 0x34b6ffff, + 0x1045b610, + 0xbb00c3bb, + 0x12ff01b4, + 0x00b3bb30, + 0x30fc40fc, + 0x10fc20fc, +/* 0x03c6: host_send */ + 0xb04100f8, + 0x0011cf04, + 0xcf04a042, + 0x12a60022, + 0xc42e0bf4, + 0xee94071e, + 0x70e0b704, + 0x03eb9802, + 0x9802ec98, + 0xee9801ed, + 0x02c27e00, + 0x0110b600, + 0x400f1ec4, + 0x0ef604b0, + 0xf404bd00, +/* 0x0402: host_send_done */ + 0x00f8c70e, +/* 0x0404: host_recv */ + 0xf14e4941, + 0xa6525413, + 0xb90bf4e1, +/* 0x0410: host_recv_wait */ + 0xcf04cc41, + 0xc8420011, + 0x0022cf04, + 0xa60816f0, + 0xef0bf412, + 0xb60723c4, + 0x30b70434, + 0x3bb502f0, + 0x023cb503, + 0xb5013db5, + 0x20b6003e, + 0x0f24f001, + 0xf604c840, + 0x04bd0002, + 0x00004002, + 0xbd0002f6, +/* 0x0453: host_init */ + 0x4100f804, 0x14b60080, - 0xf015f110, - 0x04dc4002, + 0x7015f110, + 0x04d04002, + 0xbd0001f6, + 0x00804104, + 0xf11014b6, + 0x4002f015, + 0x01f604dc, + 0x0104bd00, + 0x04c44001, 0xbd0001f6, - 0x40010104, - 0x01f604c4, - 0xf804bd00, -/* 0x03a9: memx_func_enter */ - 0x40040600, - 0x06f607e0, -/* 0x03b3: memx_func_enter_wait */ - 0x4604bd00, - 0x66cf07c0, - 0x0464f000, - 0x98f70bf4, - 0x10b60016, -/* 0x03c7: memx_func_leave */ - 0x0600f804, - 0x07e44004, - 0xbd0006f6, -/* 0x03d1: memx_func_leave_wait */ - 0x07c04604, - 0xf00066cf, - 0x1bf40464, -/* 0x03df: memx_func_wr32 */ - 0x9800f8f7, - 0x15980016, - 0x0810b601, - 0x50f960f9, +/* 0x0483: memx_func_enter */ + 0xf100f804, + 0xf1162067, + 0xf1f55d77, + 0xb2ffff73, + 0x00047e6e, + 0xfdd8b200, + 0x60f90487, + 0xd0fc80f9, + 0x2e7ee0fc, + 0x77f10000, + 0x73f1fffe, + 0x6eb2ffff, + 0x0000047e, + 0x87fdd8b2, + 0xf960f904, + 0xfcd0fc80, + 0x002e7ee0, + 0xf067f100, + 0x7e6eb226, + 0xb2000004, + 0x0487fdd8, + 0x80f960f9, 0xe0fcd0fc, 0x00002e7e, - 0x140003f1, - 0xa00506fd, - 0xb604bd05, - 0x1bf40242, -/* 0x0407: memx_func_wait */ - 0x0800f8dd, - 0x0088cf2c, - 0x98001e98, - 0x1c98011d, - 0x031b9802, - 0x7e1010b6, - 0xf8000071, -/* 0x0421: memx_func_delay */ - 0x001e9800, - 0x7e0410b6, - 0xf800005d, -/* 0x042d: memx_exec */ - 0xf9e0f900, - 0xb2c1b2d0, -/* 0x0435: memx_exec_next */ - 0x001398b2, - 0x950410b6, - 0x30f01034, - 0xde35980c, - 0x12a655f9, - 0xfced1ef4, + 0xe0400406, + 0x0006f607, +/* 0x04ea: memx_func_enter_wait */ + 0xc04604bd, + 0x0066cf07, + 0xf40464f0, + 0x2c06f70b, + 0xb50066cf, + 0x00f8ee06, +/* 0x0500: memx_func_leave */ + 0x66cf2c06, + 0xef06b500, + 0xe4400406, + 0x0006f607, +/* 0x0512: memx_func_leave_wait */ + 0xc04604bd, + 0x0066cf07, + 0xf40464f0, + 0x67f1f71b, + 0x77f126f0, + 0x73f00001, + 0x7e6eb200, + 0xb2000004, + 0x0587fdd8, + 0x80f960f9, + 0xe0fcd0fc, + 0x00002e7e, + 0x162067f1, + 0x047e6eb2, + 0xd8b20000, + 0xf90587fd, + 0xfc80f960, 0x7ee0fcd0, - 0xf800023f, -/* 0x0455: memx_info */ - 0x03ac4c00, - 0x7e08004b, - 0xf800023f, -/* 0x0461: memx_recv */ - 0x01d6b000, - 0xb0c90bf4, - 0x0bf400d6, -/* 0x046f: memx_init */ - 0xf800f8eb, -/* 0x0471: perf_recv */ -/* 0x0473: perf_init */ - 0xf800f800, -/* 0x0475: i2c_drive_scl */ - 0x0036b000, - 0x400d0bf4, - 0x01f607e0, - 0xf804bd00, -/* 0x0485: i2c_drive_scl_lo */ - 0x07e44000, - 0xbd0001f6, -/* 0x048f: i2c_drive_sda */ - 0xb000f804, - 0x0bf40036, - 0x07e0400d, - 0xbd0002f6, -/* 0x049f: i2c_drive_sda_lo */ - 0x4000f804, - 0x02f607e4, - 0xf804bd00, -/* 0x04a9: i2c_sense_scl */ - 0x0132f400, - 0xcf07c443, - 0x31fd0033, - 0x060bf404, -/* 0x04bb: i2c_sense_scl_done */ - 0xf80131f4, -/* 0x04bd: i2c_sense_sda */ - 0x0132f400, - 0xcf07c443, - 0x32fd0033, - 0x060bf404, -/* 0x04cf: i2c_sense_sda_done */ - 0xf80131f4, -/* 0x04d1: i2c_raise_scl */ - 0x4440f900, - 0x01030898, - 0x0004757e, -/* 0x04dc: i2c_raise_scl_wait */ - 0x7e03e84e, - 0x7e00005d, - 0xf40004a9, - 0x42b60901, - 0xef1bf401, -/* 0x04f0: i2c_raise_scl_done */ - 0x00f840fc, -/* 0x04f4: i2c_start */ - 0x0004a97e, - 0x7e0d11f4, - 0xf40004bd, - 0x0ef40611, -/* 0x0505: i2c_start_rep */ - 0x7e00032e, - 0x03000475, - 0x048f7e01, - 0x0076bb00, - 0xf90465b6, - 0x04659450, - 0xbd0256bb, - 0x0475fd50, - 0xd17e50fc, - 0x64b60004, - 0x1d11f404, -/* 0x0530: i2c_start_send */ - 0x8f7e0003, - 0x884e0004, - 0x005d7e13, - 0x7e000300, - 0x4e000475, - 0x5d7e1388, -/* 0x054a: i2c_start_out */ - 0x00f80000, -/* 0x054c: i2c_stop */ - 0x757e0003, - 0x00030004, - 0x00048f7e, - 0x7e03e84e, - 0x0300005d, - 0x04757e01, - 0x13884e00, + 0xf100002e, + 0xf00aa277, + 0x6eb20073, + 0x0000047e, + 0x87fdd8b2, + 0xf960f905, + 0xfcd0fc80, + 0x002e7ee0, +/* 0x057b: memx_func_wait_vblank */ + 0xb600f800, + 0x00f80410, +/* 0x0580: memx_func_wr32 */ + 0x98001698, + 0x10b60115, + 0xf960f908, + 0xfcd0fc50, + 0x002e7ee0, + 0x0242b600, + 0xf8e81bf4, +/* 0x059d: memx_func_wait */ + 0xcf2c0800, + 0x1e980088, + 0x011d9800, + 0x98021c98, + 0x10b6031b, + 0x00797e10, +/* 0x05b7: memx_func_delay */ + 0x9800f800, + 0x10b6001e, + 0x005d7e04, +/* 0x05c3: memx_exec */ + 0xf900f800, + 0xb2d0f9e0, +/* 0x05cb: memx_exec_next */ + 0x98b2b2c1, + 0x10b60013, + 0xf034e704, + 0xe033e701, + 0x0132b601, + 0x980c30f0, + 0x55f9de35, + 0x1ef412a6, + 0xee0b98e5, + 0xbbef0c98, + 0xc44b02cb, + 0x00bbcf07, + 0xe0fcd0fc, + 0x0002c27e, +/* 0x0602: memx_info */ + 0xc04c00f8, + 0x08004b03, + 0x0002c27e, +/* 0x060e: memx_recv */ + 0xd6b000f8, + 0xb20bf401, + 0xf400d6b0, + 0x00f8eb0b, +/* 0x061c: memx_init */ +/* 0x061e: perf_recv */ + 0x00f800f8, +/* 0x0620: perf_init */ +/* 0x0622: i2c_drive_scl */ + 0x36b000f8, + 0x0d0bf400, + 0xf607e040, + 0x04bd0001, +/* 0x0632: i2c_drive_scl_lo */ + 0xe44000f8, + 0x0001f607, + 0x00f804bd, +/* 0x063c: i2c_drive_sda */ + 0xf40036b0, + 0xe0400d0b, + 0x0002f607, + 0x00f804bd, +/* 0x064c: i2c_drive_sda_lo */ + 0xf607e440, + 0x04bd0002, +/* 0x0656: i2c_sense_scl */ + 0x32f400f8, + 0x07c44301, + 0xfd0033cf, + 0x0bf40431, + 0x0131f406, +/* 0x0668: i2c_sense_scl_done */ +/* 0x066a: i2c_sense_sda */ + 0x32f400f8, + 0x07c44301, + 0xfd0033cf, + 0x0bf40432, + 0x0131f406, +/* 0x067c: i2c_sense_sda_done */ +/* 0x067e: i2c_raise_scl */ + 0x40f900f8, + 0x03089844, + 0x06227e01, +/* 0x0689: i2c_raise_scl_wait */ + 0x03e84e00, 0x00005d7e, - 0x8f7e0103, - 0x884e0004, - 0x005d7e13, -/* 0x057b: i2c_bitw */ - 0x7e00f800, - 0x4e00048f, - 0x5d7e03e8, - 0x76bb0000, + 0x0006567e, + 0xb60901f4, + 0x1bf40142, +/* 0x069d: i2c_raise_scl_done */ + 0xf840fcef, +/* 0x06a1: i2c_start */ + 0x06567e00, + 0x0d11f400, + 0x00066a7e, + 0xf40611f4, +/* 0x06b2: i2c_start_rep */ + 0x00032e0e, + 0x0006227e, + 0x3c7e0103, + 0x76bb0006, 0x0465b600, 0x659450f9, 0x0256bb04, 0x75fd50bd, 0x7e50fc04, - 0xb60004d1, + 0xb600067e, 0x11f40464, - 0x13884e17, - 0x00005d7e, - 0x757e0003, - 0x884e0004, - 0x005d7e13, -/* 0x05b9: i2c_bitw_out */ -/* 0x05bb: i2c_bitr */ - 0x0300f800, - 0x048f7e01, +/* 0x06dd: i2c_start_send */ + 0x7e00031d, + 0x4e00063c, + 0x5d7e1388, + 0x00030000, + 0x0006227e, + 0x7e13884e, +/* 0x06f7: i2c_start_out */ + 0xf800005d, +/* 0x06f9: i2c_stop */ + 0x7e000300, + 0x03000622, + 0x063c7e00, 0x03e84e00, 0x00005d7e, - 0xb60076bb, - 0x50f90465, - 0xbb046594, - 0x50bd0256, - 0xfc0475fd, - 0x04d17e50, - 0x0464b600, - 0x7e1a11f4, - 0x030004bd, - 0x04757e00, - 0x13884e00, - 0x00005d7e, - 0xf4013cf0, -/* 0x05fe: i2c_bitr_done */ - 0x00f80131, -/* 0x0600: i2c_get_byte */ - 0x08040005, -/* 0x0604: i2c_get_byte_next */ - 0xbb0154b6, + 0x227e0103, + 0x884e0006, + 0x005d7e13, + 0x7e010300, + 0x4e00063c, + 0x5d7e1388, + 0x00f80000, +/* 0x0728: i2c_bitw */ + 0x00063c7e, + 0x7e03e84e, + 0xbb00005d, 0x65b60076, 0x9450f904, 0x56bb0465, 0xfd50bd02, 0x50fc0475, - 0x0005bb7e, + 0x00067e7e, 0xf40464b6, - 0x53fd2a11, - 0x0142b605, - 0x03d81bf4, - 0x0076bb01, + 0x884e1711, + 0x005d7e13, + 0x7e000300, + 0x4e000622, + 0x5d7e1388, +/* 0x0766: i2c_bitw_out */ + 0x00f80000, +/* 0x0768: i2c_bitr */ + 0x3c7e0103, + 0xe84e0006, + 0x005d7e03, + 0x0076bb00, 0xf90465b6, 0x04659450, 0xbd0256bb, 0x0475fd50, - 0x7b7e50fc, - 0x64b60005, -/* 0x064d: i2c_get_byte_done */ -/* 0x064f: i2c_put_byte */ - 0x0400f804, -/* 0x0651: i2c_put_byte_next */ - 0x0142b608, - 0xbb3854ff, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x00057b7e, - 0xf40464b6, - 0x46b03411, - 0xd81bf400, + 0x7e7e50fc, + 0x64b60006, + 0x1a11f404, + 0x00066a7e, + 0x227e0003, + 0x884e0006, + 0x005d7e13, + 0x013cf000, +/* 0x07ab: i2c_bitr_done */ + 0xf80131f4, +/* 0x07ad: i2c_get_byte */ + 0x04000500, +/* 0x07b1: i2c_get_byte_next */ + 0x0154b608, 0xb60076bb, 0x50f90465, 0xbb046594, 0x50bd0256, 0xfc0475fd, - 0x05bb7e50, + 0x07687e50, 0x0464b600, - 0xbb0f11f4, - 0x36b00076, - 0x061bf401, -/* 0x06a7: i2c_put_byte_done */ - 0xf80132f4, -/* 0x06a9: i2c_addr */ - 0x0076bb00, - 0xf90465b6, - 0x04659450, - 0xbd0256bb, - 0x0475fd50, - 0xf47e50fc, - 0x64b60004, - 0x2911f404, - 0x012ec3e7, - 0xfd0134b6, - 0x76bb0553, + 0xfd2a11f4, + 0x42b60553, + 0xd81bf401, + 0x76bb0103, 0x0465b600, 0x659450f9, 0x0256bb04, 0x75fd50bd, 0x7e50fc04, - 0xb600064f, -/* 0x06ee: i2c_addr_done */ + 0xb6000728, +/* 0x07fa: i2c_get_byte_done */ 0x00f80464, -/* 0x06f0: i2c_acquire_addr */ - 0xb6f8cec7, - 0xe0b705e4, - 0x00f8d014, -/* 0x06fc: i2c_acquire */ - 0x0006f07e, - 0x0000047e, - 0x7e03d9f0, - 0xf800002e, -/* 0x070d: i2c_release */ - 0x06f07e00, - 0x00047e00, - 0x03daf000, - 0x00002e7e, -/* 0x071e: i2c_recv */ - 0x32f400f8, - 0xf8c1c701, - 0xb00214b6, - 0x1ff52816, - 0x13b80137, - 0x98000bd4, - 0x13b80032, - 0x98000bac, - 0x31f40031, - 0xf9d0f902, - 0xf1d0f9e0, - 0xf1000067, - 0x92100063, - 0x76bb0167, - 0x0465b600, - 0x659450f9, - 0x0256bb04, - 0x75fd50bd, - 0x7e50fc04, - 0xb60006fc, - 0xd0fc0464, - 0xf500d6b0, - 0x0500b01b, - 0x0076bb00, - 0xf90465b6, - 0x04659450, - 0xbd0256bb, - 0x0475fd50, - 0xa97e50fc, - 0x64b60006, - 0xcc11f504, - 0xe0c5c700, +/* 0x07fc: i2c_put_byte */ +/* 0x07fe: i2c_put_byte_next */ + 0x42b60804, + 0x3854ff01, 0xb60076bb, 0x50f90465, 0xbb046594, 0x50bd0256, 0xfc0475fd, - 0x064f7e50, + 0x07287e50, 0x0464b600, - 0x00a911f5, - 0x76bb0105, + 0xb03411f4, + 0x1bf40046, + 0x0076bbd8, + 0xf90465b6, + 0x04659450, + 0xbd0256bb, + 0x0475fd50, + 0x687e50fc, + 0x64b60007, + 0x0f11f404, + 0xb00076bb, + 0x1bf40136, + 0x0132f406, +/* 0x0854: i2c_put_byte_done */ +/* 0x0856: i2c_addr */ + 0x76bb00f8, 0x0465b600, 0x659450f9, 0x0256bb04, 0x75fd50bd, 0x7e50fc04, - 0xb60006a9, - 0x11f50464, - 0x76bb0087, + 0xb60006a1, + 0x11f40464, + 0x2ec3e729, + 0x0134b601, + 0xbb0553fd, + 0x65b60076, + 0x9450f904, + 0x56bb0465, + 0xfd50bd02, + 0x50fc0475, + 0x0007fc7e, +/* 0x089b: i2c_addr_done */ + 0xf80464b6, +/* 0x089d: i2c_acquire_addr */ + 0xf8cec700, + 0xb705e4b6, + 0xf8d014e0, +/* 0x08a9: i2c_acquire */ + 0x089d7e00, + 0x00047e00, + 0x03d9f000, + 0x00002e7e, +/* 0x08ba: i2c_release */ + 0x9d7e00f8, + 0x047e0008, + 0xdaf00000, + 0x002e7e03, +/* 0x08cb: i2c_recv */ + 0xf400f800, + 0xc1c70132, + 0x0214b6f8, + 0xf52816b0, + 0xb801371f, + 0x000be813, + 0xb8003298, + 0x000bc013, + 0xf4003198, + 0xd0f90231, + 0xd0f9e0f9, + 0x000067f1, + 0x100063f1, + 0xbb016792, + 0x65b60076, + 0x9450f904, + 0x56bb0465, + 0xfd50bd02, + 0x50fc0475, + 0x0008a97e, + 0xfc0464b6, + 0x00d6b0d0, + 0x00b01bf5, + 0x76bb0005, 0x0465b600, 0x659450f9, 0x0256bb04, 0x75fd50bd, 0x7e50fc04, - 0xb6000600, - 0x11f40464, - 0xe05bcb67, - 0xb60076bb, - 0x50f90465, - 0xbb046594, - 0x50bd0256, - 0xfc0475fd, - 0x054c7e50, - 0x0464b600, - 0x74bd5bb2, -/* 0x0823: i2c_recv_not_rd08 */ - 0xb0410ef4, - 0x1bf401d6, - 0x7e00053b, - 0xf40006a9, - 0xc5c73211, - 0x064f7ee0, - 0x2811f400, - 0xa97e0005, - 0x11f40006, - 0xe0b5c71f, - 0x00064f7e, - 0x7e1511f4, - 0xbd00054c, - 0x08c5c774, - 0xf4091bf4, - 0x0ef40232, -/* 0x0861: i2c_recv_not_wr08 */ -/* 0x0861: i2c_recv_done */ - 0xf8cec703, - 0x00070d7e, - 0xd0fce0fc, - 0xb20912f4, - 0x023f7e7c, -/* 0x0875: i2c_recv_exit */ -/* 0x0877: i2c_init */ - 0xf800f800, -/* 0x0879: test_recv */ - 0x04584100, - 0xb60011cf, - 0x58400110, - 0x0001f604, - 0xe7f104bd, - 0xe3f1d900, - 0x967e134f, - 0x00f80001, -/* 0x0898: test_init */ - 0x7e08004e, - 0xf8000196, -/* 0x08a1: idle_recv */ -/* 0x08a3: idle */ - 0xf400f800, - 0x54410031, + 0xb6000856, + 0x11f50464, + 0xc5c700cc, + 0x0076bbe0, + 0xf90465b6, + 0x04659450, + 0xbd0256bb, + 0x0475fd50, + 0xfc7e50fc, + 0x64b60007, + 0xa911f504, + 0xbb010500, + 0x65b60076, + 0x9450f904, + 0x56bb0465, + 0xfd50bd02, + 0x50fc0475, + 0x0008567e, + 0xf50464b6, + 0xbb008711, + 0x65b60076, + 0x9450f904, + 0x56bb0465, + 0xfd50bd02, + 0x50fc0475, + 0x0007ad7e, + 0xf40464b6, + 0x5bcb6711, + 0x0076bbe0, + 0xf90465b6, + 0x04659450, + 0xbd0256bb, + 0x0475fd50, + 0xf97e50fc, + 0x64b60006, + 0xbd5bb204, + 0x410ef474, +/* 0x09d0: i2c_recv_not_rd08 */ + 0xf401d6b0, + 0x00053b1b, + 0x0008567e, + 0xc73211f4, + 0xfc7ee0c5, + 0x11f40007, + 0x7e000528, + 0xf4000856, + 0xb5c71f11, + 0x07fc7ee0, + 0x1511f400, + 0x0006f97e, + 0xc5c774bd, + 0x091bf408, + 0xf40232f4, +/* 0x0a0e: i2c_recv_not_wr08 */ +/* 0x0a0e: i2c_recv_done */ + 0xcec7030e, + 0x08ba7ef8, + 0xfce0fc00, + 0x0912f4d0, + 0xc27e7cb2, +/* 0x0a22: i2c_recv_exit */ + 0x00f80002, +/* 0x0a24: i2c_init */ +/* 0x0a26: test_recv */ + 0x584100f8, 0x0011cf04, 0x400110b6, - 0x01f60454, -/* 0x08b7: idle_loop */ - 0x0104bd00, - 0x0232f458, -/* 0x08bc: idle_proc */ -/* 0x08bc: idle_proc_exec */ - 0x1eb210f9, - 0x0002487e, - 0x11f410fc, - 0x0231f409, -/* 0x08cf: idle_proc_next */ - 0xb6f00ef4, - 0x1fa65810, - 0xf4e81bf4, - 0x28f4e002, - 0xc60ef400, + 0x01f60458, + 0xf104bd00, + 0xf1d900e7, + 0x7e134fe3, + 0xf8000201, +/* 0x0a45: test_init */ + 0x08004e00, + 0x0002017e, +/* 0x0a4e: idle_recv */ + 0x00f800f8, +/* 0x0a50: idle */ + 0x410031f4, + 0x11cf0454, + 0x0110b600, + 0xf6045440, + 0x04bd0001, +/* 0x0a64: idle_loop */ + 0x32f45801, +/* 0x0a69: idle_proc */ +/* 0x0a69: idle_proc_exec */ + 0xb210f902, + 0x02cb7e1e, + 0xf410fc00, + 0x31f40911, + 0xf00ef402, +/* 0x0a7c: idle_proc_next */ + 0xa65810b6, + 0xe81bf41f, + 0xf4e002f4, + 0x0ef40028, + 0x000000c6, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc index 6744fcc06151..daa06c1c655e 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc @@ -23,6 +23,7 @@ */ #define NVKM_PPWR_CHIPSET GT215 +#define HW_TICKS_PER_US 203 // should be 202.5 //#define NVKM_FALCON_PC24 //#define NVKM_FALCON_UNSHIFTED_IO @@ -34,6 +35,7 @@ .section #nva3_pwr_data #define INCLUDE_PROC #include "kernel.fuc" +#include "arith.fuc" #include "host.fuc" #include "memx.fuc" #include "perf.fuc" @@ -44,6 +46,7 @@ #define INCLUDE_DATA #include "kernel.fuc" +#include "arith.fuc" #include "host.fuc" #include "memx.fuc" #include "perf.fuc" @@ -56,6 +59,7 @@ .section #nva3_pwr_code #define INCLUDE_CODE #include "kernel.fuc" +#include "arith.fuc" #include "host.fuc" #include "memx.fuc" #include "perf.fuc" diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h index 254205cd5166..64e97baabc3c 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h @@ -24,8 +24,8 @@ uint32_t nva3_pwr_data[] = { 0x00000000, /* 0x0058: proc_list_head */ 0x54534f48, - 0x00000430, - 0x000003cd, + 0x00000512, + 0x000004af, 0x00000000, 0x00000000, 0x00000000, @@ -46,8 +46,8 @@ uint32_t nva3_pwr_data[] = { 0x00000000, 0x00000000, 0x584d454d, - 0x0000054e, - 0x00000540, + 0x000006e0, + 0x000006d2, 0x00000000, 0x00000000, 0x00000000, @@ -68,8 +68,8 @@ uint32_t nva3_pwr_data[] = { 0x00000000, 0x00000000, 0x46524550, - 0x00000552, - 0x00000550, + 0x000006e4, + 0x000006e2, 0x00000000, 0x00000000, 0x00000000, @@ -90,8 +90,8 @@ uint32_t nva3_pwr_data[] = { 0x00000000, 0x00000000, 0x5f433249, - 0x00000982, - 0x00000825, + 0x00000b14, + 0x000009b7, 0x00000000, 0x00000000, 0x00000000, @@ -112,8 +112,8 @@ uint32_t nva3_pwr_data[] = { 0x00000000, 0x00000000, 0x54534554, - 0x000009ab, - 0x00000984, + 0x00000b3d, + 0x00000b16, 0x00000000, 0x00000000, 0x00000000, @@ -134,8 +134,8 @@ uint32_t nva3_pwr_data[] = { 0x00000000, 0x00000000, 0x454c4449, - 0x000009b7, - 0x000009b5, + 0x00000b49, + 0x00000b47, 0x00000000, 0x00000000, 0x00000000, @@ -227,27 +227,31 @@ uint32_t nva3_pwr_data[] = { 0x00000000, 0x00000000, /* 0x0370: memx_func_head */ - 0x00010000, - 0x00000000, - 0x0000046f, -/* 0x037c: memx_func_next */ 0x00000001, 0x00000000, - 0x00000496, + 0x00000551, +/* 0x037c: memx_func_next */ 0x00000002, + 0x00000000, + 0x000005a8, + 0x00000003, 0x00000002, - 0x000004b7, - 0x00040003, + 0x0000063a, + 0x00040004, 0x00000000, - 0x000004df, - 0x00010004, + 0x00000656, + 0x00010005, 0x00000000, - 0x000004fc, -/* 0x03ac: memx_func_tail */ -/* 0x03ac: memx_data_head */ + 0x00000673, + 0x00010006, 0x00000000, + 0x000005f8, +/* 0x03b8: memx_func_tail */ +/* 0x03b8: memx_ts_start */ 0x00000000, +/* 0x03bc: memx_ts_end */ 0x00000000, +/* 0x03c0: memx_data_head */ 0x00000000, 0x00000000, 0x00000000, @@ -757,8 +761,11 @@ uint32_t nva3_pwr_data[] = { 0x00000000, 0x00000000, 0x00000000, -/* 0x0bac: memx_data_tail */ -/* 0x0bac: i2c_scl_map */ + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0bc0: memx_data_tail */ +/* 0x0bc0: i2c_scl_map */ 0x00001000, 0x00004000, 0x00010000, @@ -769,7 +776,7 @@ uint32_t nva3_pwr_data[] = { 0x01000000, 0x04000000, 0x10000000, -/* 0x0bd4: i2c_sda_map */ +/* 0x0be8: i2c_sda_map */ 0x00002000, 0x00008000, 0x00020000, @@ -780,7 +787,7 @@ uint32_t nva3_pwr_data[] = { 0x02000000, 0x08000000, 0x20000000, -/* 0x0bfc: i2c_ctrl */ +/* 0x0c10: i2c_ctrl */ 0x0000e138, 0x0000e150, 0x0000e168, @@ -841,15 +848,10 @@ uint32_t nva3_pwr_data[] = { 0x00000000, 0x00000000, 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, }; uint32_t nva3_pwr_code[] = { - 0x030d0ef5, + 0x039e0ef5, /* 0x0004: rd32 */ 0x07a007f1, 0xd00604b6, @@ -885,19 +887,22 @@ uint32_t nva3_pwr_code[] = { 0xd4f100dd, 0x1bf47000, /* 0x007f: nsec */ - 0xf000f8f2, + 0xf900f8f2, + 0xf080f990, 0x84b62c87, 0x0088cf06, -/* 0x0088: nsec_loop */ +/* 0x008c: nsec_loop */ 0xb62c97f0, 0x99cf0694, 0x0298bb00, 0xf4069eb8, - 0x00f8f11e, -/* 0x009c: wait */ + 0x80fcf11e, + 0x00f890fc, +/* 0x00a4: wait */ + 0x80f990f9, 0xb62c87f0, 0x88cf0684, -/* 0x00a5: wait_loop */ +/* 0x00b1: wait_loop */ 0x02eeb900, 0xb90421f4, 0xadfd02da, @@ -907,28 +912,29 @@ uint32_t nva3_pwr_code[] = { 0x0099cf06, 0xb80298bb, 0x1ef4069b, -/* 0x00c9: wait_done */ -/* 0x00cb: intr_watchdog */ - 0x9800f8df, +/* 0x00d5: wait_done */ + 0xfc80fcdf, +/* 0x00db: intr_watchdog */ + 0x9800f890, 0x96b003e9, 0x2a0bf400, 0xbb9a0a98, 0x1cf4029a, 0x01d7f00f, - 0x025421f5, + 0x02dd21f5, 0x0ef494bd, -/* 0x00e9: intr_watchdog_next_time */ +/* 0x00f9: intr_watchdog_next_time */ 0x9b0a9815, 0xf400a6b0, 0x9ab8090b, 0x061cf406, -/* 0x00f8: intr_watchdog_next_time_set */ -/* 0x00fb: intr_watchdog_next_proc */ +/* 0x0108: intr_watchdog_next_time_set */ +/* 0x010b: intr_watchdog_next_proc */ 0x809b0980, 0xe0b603e9, 0x68e6b158, 0xc61bf402, -/* 0x010a: intr */ +/* 0x011a: intr */ 0x00f900f8, 0x80f904bd, 0xa0f990f9, @@ -948,13 +954,13 @@ uint32_t nva3_pwr_code[] = { 0xf40289c4, 0x0080230b, 0x58e7f09b, - 0x98cb21f4, + 0x98db21f4, 0x96b09b09, 0x110bf400, 0xb63407f0, 0x09d00604, 0x8004bd00, -/* 0x016e: intr_skip_watchdog */ +/* 0x017e: intr_skip_watchdog */ 0x89e49a09, 0x0bf40800, 0x8897f148, @@ -967,22 +973,22 @@ uint32_t nva3_pwr_code[] = { 0x48e7f1c0, 0x53e3f14f, 0x00d7f054, - 0x02b921f5, + 0x034221f5, 0x07f1c0fc, 0x04b604c0, 0x000cd006, -/* 0x01ae: intr_subintr_skip_fifo */ +/* 0x01be: intr_subintr_skip_fifo */ 0x07f104bd, 0x04b60688, 0x0009d006, -/* 0x01ba: intr_skip_subintr */ +/* 0x01ca: intr_skip_subintr */ 0x89c404bd, 0x070bf420, 0xffbfa4f1, -/* 0x01c4: intr_skip_pause */ +/* 0x01d4: intr_skip_pause */ 0xf44089c4, 0xa4f1070b, -/* 0x01ce: intr_skip_user0 */ +/* 0x01de: intr_skip_user0 */ 0x07f0ffbf, 0x0604b604, 0xbd0008d0, @@ -993,597 +999,733 @@ uint32_t nva3_pwr_code[] = { 0x90fca0fc, 0x00fc80fc, 0xf80032f4, -/* 0x01f5: timer */ - 0x1032f401, - 0xb003f898, - 0x1cf40086, - 0x03fe8051, +/* 0x0205: ticks_from_ns */ + 0xf9c0f901, + 0xcbd7f1b0, + 0x00d3f000, + 0x041321f5, + 0x03e8ccec, + 0xf400b4b0, + 0xeeec120b, + 0xd7f103e8, + 0xd3f000cb, + 0x1321f500, +/* 0x022d: ticks_from_ns_quit */ + 0x02ceb904, + 0xc0fcb0fc, +/* 0x0236: ticks_from_us */ + 0xc0f900f8, + 0xd7f1b0f9, + 0xd3f000cb, + 0x1321f500, + 0x02ceb904, + 0xf400b4b0, + 0xe4bd050b, +/* 0x0250: ticks_from_us_quit */ + 0xc0fcb0fc, +/* 0x0256: ticks_to_us */ + 0xd7f100f8, + 0xd3f000cb, + 0xecedff00, +/* 0x0262: timer */ + 0x90f900f8, + 0x32f480f9, + 0x03f89810, + 0xf40086b0, + 0x84bd651c, 0xb63807f0, 0x08d00604, 0xf004bd00, - 0x84b60887, + 0x84b63487, 0x0088cf06, - 0xf40284f0, - 0x87f0261b, - 0x0684b634, - 0xb80088cf, - 0x0bf406e0, - 0x06e8b809, -/* 0x0233: timer_reset */ - 0xf01f1ef4, - 0x04b63407, - 0x000ed006, - 0x0e8004bd, -/* 0x0241: timer_enable */ - 0x0187f09a, + 0xbb9a0998, + 0xe9bb0298, + 0x03fe8000, + 0xb60887f0, + 0x88cf0684, + 0x0284f000, + 0xf0261bf4, + 0x84b63487, + 0x0088cf06, + 0xf406e0b8, + 0xe8b8090b, + 0x111cf406, +/* 0x02b8: timer_reset */ + 0xb63407f0, + 0x0ed00604, + 0x8004bd00, +/* 0x02c6: timer_enable */ + 0x87f09a0e, + 0x3807f001, + 0xd00604b6, + 0x04bd0008, +/* 0x02d4: timer_done */ + 0xfc1031f4, + 0xf890fc80, +/* 0x02dd: send_proc */ + 0xf980f900, + 0x05e89890, + 0xf004e998, + 0x89b80486, + 0x2a0bf406, + 0x940398c4, + 0x80b60488, + 0x008ebb18, + 0x8000fa98, + 0x8d80008a, + 0x028c8001, + 0xb6038b80, + 0x94f00190, + 0x04e98007, +/* 0x0317: send_done */ + 0xfc0231f4, + 0xf880fc90, +/* 0x031d: find */ + 0xf080f900, + 0x31f45887, +/* 0x0325: find_loop */ + 0x008a9801, + 0xf406aeb8, + 0x80b6100b, + 0x6886b158, + 0xf01bf402, +/* 0x033b: find_done */ + 0xb90132f4, + 0x80fc028e, +/* 0x0342: send */ + 0x21f500f8, + 0x01f4031d, +/* 0x034b: recv */ + 0xf900f897, + 0x9880f990, + 0xe99805e8, + 0x0132f404, + 0xf40689b8, + 0x89c43d0b, + 0x0180b603, + 0x800784f0, + 0xea9805e8, + 0xfef0f902, + 0xf0f9018f, + 0x9402efb9, + 0xe9bb0499, + 0x18e0b600, + 0x9803eb98, + 0xed9802ec, + 0x00ee9801, + 0xf0fca5f9, + 0xf400f8fe, + 0xf0fc0131, +/* 0x0398: recv_done */ + 0x90fc80fc, +/* 0x039e: init */ + 0x17f100f8, + 0x14b60108, + 0x0011cf06, + 0x010911e7, + 0xfe0814b6, + 0x17f10014, + 0x13f000e0, + 0x1c07f000, + 0xd00604b6, + 0x04bd0001, + 0xf0ff17f0, + 0x04b61407, + 0x0001d006, + 0x17f004bd, + 0x0015f102, + 0x1007f008, + 0xd00604b6, + 0x04bd0001, + 0x011a17f1, + 0xfe0013f0, + 0x31f40010, + 0x0117f010, 0xb63807f0, - 0x08d00604, -/* 0x024f: timer_done */ - 0xf404bd00, - 0x00f81031, -/* 0x0254: send_proc */ - 0x90f980f9, - 0x9805e898, - 0x86f004e9, - 0x0689b804, - 0xc42a0bf4, - 0x88940398, - 0x1880b604, - 0x98008ebb, - 0x8a8000fa, - 0x018d8000, - 0x80028c80, - 0x90b6038b, - 0x0794f001, - 0xf404e980, -/* 0x028e: send_done */ - 0x90fc0231, - 0x00f880fc, -/* 0x0294: find */ - 0x87f080f9, - 0x0131f458, -/* 0x029c: find_loop */ - 0xb8008a98, - 0x0bf406ae, - 0x5880b610, - 0x026886b1, - 0xf4f01bf4, -/* 0x02b2: find_done */ - 0x8eb90132, - 0xf880fc02, -/* 0x02b9: send */ - 0x9421f500, - 0x9701f402, -/* 0x02c2: recv */ - 0xe89800f8, - 0x04e99805, - 0xb80132f4, - 0x0bf40689, - 0x0389c43d, - 0xf00180b6, - 0xe8800784, - 0x02ea9805, - 0x8ffef0f9, - 0xb9f0f901, - 0x999402ef, - 0x00e9bb04, - 0x9818e0b6, - 0xec9803eb, - 0x01ed9802, - 0xf900ee98, - 0xfef0fca5, - 0x31f400f8, -/* 0x030b: recv_done */ - 0xf8f0fc01, -/* 0x030d: init */ - 0x0817f100, - 0x0614b601, - 0xe70011cf, - 0xb6010911, - 0x14fe0814, - 0xe017f100, - 0x0013f000, - 0xb61c07f0, 0x01d00604, 0xf004bd00, - 0x07f0ff17, - 0x0604b614, - 0xbd0001d0, - 0x0217f004, - 0x080015f1, - 0xb61007f0, - 0x01d00604, - 0xf104bd00, - 0xf0010a17, - 0x10fe0013, - 0x1031f400, - 0xf00117f0, - 0x04b63807, - 0x0001d006, - 0xf7f004bd, -/* 0x0371: init_proc */ - 0x01f19858, - 0xf40016b0, - 0x15f9fa0b, - 0xf458f0b6, -/* 0x0382: host_send */ - 0x17f1f20e, - 0x14b604b0, - 0x0011cf06, - 0x04a027f1, - 0xcf0624b6, - 0x12b80022, - 0x320bf406, - 0x94071ec4, - 0xe0b704ee, - 0xeb980270, - 0x02ec9803, - 0x9801ed98, - 0x21f500ee, - 0x10b602b9, - 0x0f1ec401, - 0x04b007f1, - 0xd00604b6, - 0x04bd000e, -/* 0x03cb: host_send_done */ - 0xf8ba0ef4, -/* 0x03cd: host_recv */ - 0x4917f100, - 0x5413f14e, - 0x06e1b852, -/* 0x03db: host_recv_wait */ - 0xf1aa0bf4, - 0xb604cc17, - 0x11cf0614, - 0xc827f100, - 0x0624b604, - 0xf00022cf, - 0x12b80816, - 0xe60bf406, - 0xb60723c4, - 0x30b70434, - 0x3b8002f0, - 0x023c8003, - 0x80013d80, - 0x20b6003e, - 0x0f24f001, - 0x04c807f1, +/* 0x0402: init_proc */ + 0xf19858f7, + 0x0016b001, + 0xf9fa0bf4, + 0x58f0b615, +/* 0x0413: mulu32_32_64 */ + 0xf9f20ef4, + 0xf920f910, + 0x9540f930, + 0xd29510e1, + 0xbdc4bd10, + 0xc0edffb4, + 0xb9301dff, + 0x34f10234, + 0x34b6ffff, + 0x1045b610, + 0xbb00c3bb, + 0xe2ff01b4, + 0x0234b930, + 0xffff34f1, + 0xb61034b6, + 0xc3bb1045, + 0x01b4bb00, + 0xbb3012ff, + 0x40fc00b3, + 0x20fc30fc, + 0x00f810fc, +/* 0x0464: host_send */ + 0x04b017f1, + 0xcf0614b6, + 0x27f10011, + 0x24b604a0, + 0x0022cf06, + 0xf40612b8, + 0x1ec4320b, + 0x04ee9407, + 0x0270e0b7, + 0x9803eb98, + 0xed9802ec, + 0x00ee9801, + 0x034221f5, + 0xc40110b6, + 0x07f10f1e, + 0x04b604b0, + 0x000ed006, + 0x0ef404bd, +/* 0x04ad: host_send_done */ +/* 0x04af: host_recv */ + 0xf100f8ba, + 0xf14e4917, + 0xb8525413, + 0x0bf406e1, +/* 0x04bd: host_recv_wait */ + 0xcc17f1aa, + 0x0614b604, + 0xf10011cf, + 0xb604c827, + 0x22cf0624, + 0x0816f000, + 0xf40612b8, + 0x23c4e60b, + 0x0434b607, + 0x02f030b7, + 0x80033b80, + 0x3d80023c, + 0x003e8001, + 0xf00120b6, + 0x07f10f24, + 0x04b604c8, + 0x0002d006, + 0x27f004bd, + 0x0007f040, 0xd00604b6, 0x04bd0002, - 0xf04027f0, - 0x04b60007, - 0x0002d006, - 0x00f804bd, -/* 0x0430: host_init */ - 0x008017f1, - 0xf11014b6, - 0xf1027015, - 0xb604d007, - 0x01d00604, - 0xf104bd00, - 0xb6008017, - 0x15f11014, - 0x07f102f0, - 0x04b604dc, - 0x0001d006, - 0x17f004bd, - 0xc407f101, +/* 0x0512: host_init */ + 0x17f100f8, + 0x14b60080, + 0x7015f110, + 0xd007f102, 0x0604b604, 0xbd0001d0, -/* 0x046f: memx_func_enter */ - 0xf000f804, + 0x8017f104, + 0x1014b600, + 0x02f015f1, + 0x04dc07f1, + 0xd00604b6, + 0x04bd0001, + 0xf10117f0, + 0xb604c407, + 0x01d00604, + 0xf804bd00, +/* 0x0551: memx_func_enter */ + 0x1087f100, + 0x028eb916, + 0xb90421f4, + 0x67f102d7, + 0x63f1fffc, + 0x76fdffff, + 0x0267f104, + 0x0576fd00, + 0x70f980f9, + 0xe0fcd0fc, + 0xf03f21f4, 0x07f10467, 0x04b607e0, 0x0006d006, -/* 0x047e: memx_func_enter_wait */ +/* 0x058a: memx_func_enter_wait */ 0x67f104bd, 0x64b607c0, 0x0066cf06, 0xf40464f0, - 0x1698f30b, - 0x0410b600, -/* 0x0496: memx_func_leave */ - 0x67f000f8, - 0xe407f104, - 0x0604b607, - 0xbd0006d0, -/* 0x04a5: memx_func_leave_wait */ - 0xc067f104, + 0x67f0f30b, + 0x0664b62c, + 0x800066cf, + 0x00f8ee06, +/* 0x05a8: memx_func_leave */ + 0xb62c67f0, + 0x66cf0664, + 0xef068000, + 0xf10467f0, + 0xb607e407, + 0x06d00604, +/* 0x05c3: memx_func_leave_wait */ + 0xf104bd00, + 0xb607c067, + 0x66cf0664, + 0x0464f000, + 0xf1f31bf4, + 0xb9161087, + 0x21f4028e, + 0x02d7b904, + 0xffcc67f1, + 0xffff63f1, + 0xf90476fd, + 0xfc70f980, + 0xf4e0fcd0, + 0x00f83f21, +/* 0x05f8: memx_func_wait_vblank */ + 0xb0001698, + 0x0bf40066, + 0x0166b013, + 0xf4060bf4, +/* 0x060a: memx_func_wait_vblank_head1 */ + 0x77f12e0e, + 0x0ef40020, +/* 0x0611: memx_func_wait_vblank_head0 */ + 0x0877f107, +/* 0x0615: memx_func_wait_vblank_0 */ + 0xc467f100, 0x0664b607, - 0xf00066cf, - 0x1bf40464, -/* 0x04b7: memx_func_wr32 */ - 0x9800f8f3, - 0x15980016, - 0x0810b601, - 0x50f960f9, - 0xe0fcd0fc, - 0xf13f21f4, - 0xfd140003, - 0x05800506, - 0xb604bd00, - 0x1bf40242, -/* 0x04df: memx_func_wait */ - 0xf000f8dd, - 0x84b62c87, - 0x0088cf06, - 0x98001e98, - 0x1c98011d, - 0x031b9802, - 0xf41010b6, - 0x00f89c21, -/* 0x04fc: memx_func_delay */ - 0xb6001e98, - 0x21f40410, -/* 0x0507: memx_exec */ - 0xf900f87f, - 0xb9d0f9e0, - 0xb2b902c1, -/* 0x0511: memx_exec_next */ - 0x00139802, - 0x950410b6, - 0x30f01034, - 0xde35980c, - 0x12b855f9, - 0xec1ef406, - 0xe0fcd0fc, - 0x02b921f5, -/* 0x0532: memx_info */ - 0xc7f100f8, - 0xb7f103ac, - 0x21f50800, - 0x00f802b9, -/* 0x0540: memx_recv */ - 0xf401d6b0, - 0xd6b0c40b, - 0xe90bf400, -/* 0x054e: memx_init */ - 0x00f800f8, -/* 0x0550: perf_recv */ -/* 0x0552: perf_init */ + 0xfd0066cf, + 0x1bf40467, +/* 0x0625: memx_func_wait_vblank_1 */ + 0xc467f1f3, + 0x0664b607, + 0xfd0066cf, + 0x0bf40467, +/* 0x0635: memx_func_wait_vblank_fini */ + 0x0410b6f3, +/* 0x063a: memx_func_wr32 */ + 0x169800f8, + 0x01159800, + 0xf90810b6, + 0xfc50f960, + 0xf4e0fcd0, + 0x42b63f21, + 0xe91bf402, +/* 0x0656: memx_func_wait */ + 0x87f000f8, + 0x0684b62c, + 0x980088cf, + 0x1d98001e, + 0x021c9801, + 0xb6031b98, + 0x21f41010, +/* 0x0673: memx_func_delay */ + 0x9800f8a4, + 0x10b6001e, + 0x7f21f404, +/* 0x067e: memx_exec */ + 0xe0f900f8, + 0xc1b9d0f9, + 0x02b2b902, +/* 0x0688: memx_exec_next */ + 0xb6001398, + 0x34e70410, + 0x33e701f0, + 0x32b601e0, + 0x0c30f001, + 0xf9de3598, + 0x0612b855, + 0x98e41ef4, + 0x0c98ee0b, + 0x02cbbbef, + 0x07c4b7f1, + 0xcf06b4b6, + 0xd0fc00bb, + 0x21f5e0fc, + 0x00f80342, +/* 0x06c4: memx_info */ + 0x03c0c7f1, + 0x0800b7f1, + 0x034221f5, +/* 0x06d2: memx_recv */ + 0xd6b000f8, + 0xa90bf401, + 0xf400d6b0, + 0x00f8e90b, +/* 0x06e0: memx_init */ +/* 0x06e2: perf_recv */ 0x00f800f8, -/* 0x0554: i2c_drive_scl */ - 0xf40036b0, - 0x07f1110b, - 0x04b607e0, - 0x0001d006, - 0x00f804bd, -/* 0x0568: i2c_drive_scl_lo */ - 0x07e407f1, - 0xd00604b6, - 0x04bd0001, -/* 0x0576: i2c_drive_sda */ +/* 0x06e4: perf_init */ +/* 0x06e6: i2c_drive_scl */ 0x36b000f8, 0x110bf400, 0x07e007f1, 0xd00604b6, - 0x04bd0002, -/* 0x058a: i2c_drive_sda_lo */ + 0x04bd0001, +/* 0x06fa: i2c_drive_scl_lo */ 0x07f100f8, 0x04b607e4, + 0x0001d006, + 0x00f804bd, +/* 0x0708: i2c_drive_sda */ + 0xf40036b0, + 0x07f1110b, + 0x04b607e0, 0x0002d006, 0x00f804bd, -/* 0x0598: i2c_sense_scl */ - 0xf10132f4, - 0xb607c437, - 0x33cf0634, - 0x0431fd00, - 0xf4060bf4, -/* 0x05ae: i2c_sense_scl_done */ - 0x00f80131, -/* 0x05b0: i2c_sense_sda */ - 0xf10132f4, - 0xb607c437, - 0x33cf0634, - 0x0432fd00, - 0xf4060bf4, -/* 0x05c6: i2c_sense_sda_done */ - 0x00f80131, -/* 0x05c8: i2c_raise_scl */ - 0x47f140f9, - 0x37f00898, - 0x5421f501, -/* 0x05d5: i2c_raise_scl_wait */ - 0xe8e7f105, - 0x7f21f403, - 0x059821f5, - 0xb60901f4, - 0x1bf40142, -/* 0x05e9: i2c_raise_scl_done */ - 0xf840fcef, -/* 0x05ed: i2c_start */ - 0x9821f500, - 0x0d11f405, - 0x05b021f5, - 0xf40611f4, -/* 0x05fe: i2c_start_rep */ - 0x37f0300e, - 0x5421f500, - 0x0137f005, - 0x057621f5, - 0xb60076bb, - 0x50f90465, - 0xbb046594, - 0x50bd0256, - 0xfc0475fd, - 0xc821f550, - 0x0464b605, -/* 0x062b: i2c_start_send */ - 0xf01f11f4, +/* 0x071c: i2c_drive_sda_lo */ + 0x07e407f1, + 0xd00604b6, + 0x04bd0002, +/* 0x072a: i2c_sense_scl */ + 0x32f400f8, + 0xc437f101, + 0x0634b607, + 0xfd0033cf, + 0x0bf40431, + 0x0131f406, +/* 0x0740: i2c_sense_scl_done */ +/* 0x0742: i2c_sense_sda */ + 0x32f400f8, + 0xc437f101, + 0x0634b607, + 0xfd0033cf, + 0x0bf40432, + 0x0131f406, +/* 0x0758: i2c_sense_sda_done */ +/* 0x075a: i2c_raise_scl */ + 0x40f900f8, + 0x089847f1, + 0xf50137f0, +/* 0x0767: i2c_raise_scl_wait */ + 0xf106e621, + 0xf403e8e7, + 0x21f57f21, + 0x01f4072a, + 0x0142b609, +/* 0x077b: i2c_raise_scl_done */ + 0xfcef1bf4, +/* 0x077f: i2c_start */ + 0xf500f840, + 0xf4072a21, + 0x21f50d11, + 0x11f40742, + 0x300ef406, +/* 0x0790: i2c_start_rep */ + 0xf50037f0, + 0xf006e621, + 0x21f50137, + 0x76bb0708, + 0x0465b600, + 0x659450f9, + 0x0256bb04, + 0x75fd50bd, + 0xf550fc04, + 0xb6075a21, + 0x11f40464, +/* 0x07bd: i2c_start_send */ + 0x0037f01f, + 0x070821f5, + 0x1388e7f1, + 0xf07f21f4, 0x21f50037, - 0xe7f10576, + 0xe7f106e6, 0x21f41388, - 0x0037f07f, - 0x055421f5, - 0x1388e7f1, -/* 0x0647: i2c_start_out */ - 0xf87f21f4, -/* 0x0649: i2c_stop */ - 0x0037f000, - 0x055421f5, - 0xf50037f0, - 0xf1057621, - 0xf403e8e7, - 0x37f07f21, - 0x5421f501, - 0x88e7f105, - 0x7f21f413, +/* 0x07d9: i2c_start_out */ +/* 0x07db: i2c_stop */ + 0xf000f87f, + 0x21f50037, + 0x37f006e6, + 0x0821f500, + 0xe8e7f107, + 0x7f21f403, 0xf50137f0, - 0xf1057621, + 0xf106e621, 0xf41388e7, - 0x00f87f21, -/* 0x067c: i2c_bitw */ - 0x057621f5, - 0x03e8e7f1, - 0xbb7f21f4, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x05c821f5, - 0xf40464b6, - 0xe7f11811, - 0x21f41388, - 0x0037f07f, - 0x055421f5, - 0x1388e7f1, -/* 0x06bb: i2c_bitw_out */ - 0xf87f21f4, -/* 0x06bd: i2c_bitr */ - 0x0137f000, - 0x057621f5, - 0x03e8e7f1, - 0xbb7f21f4, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x05c821f5, - 0xf40464b6, - 0x21f51b11, - 0x37f005b0, - 0x5421f500, - 0x88e7f105, + 0x37f07f21, + 0x0821f501, + 0x88e7f107, 0x7f21f413, - 0xf4013cf0, -/* 0x0702: i2c_bitr_done */ - 0x00f80131, -/* 0x0704: i2c_get_byte */ - 0xf00057f0, -/* 0x070a: i2c_get_byte_next */ - 0x54b60847, - 0x0076bb01, +/* 0x080e: i2c_bitw */ + 0x21f500f8, + 0xe7f10708, + 0x21f403e8, + 0x0076bb7f, 0xf90465b6, 0x04659450, 0xbd0256bb, 0x0475fd50, 0x21f550fc, - 0x64b606bd, - 0x2b11f404, - 0xb60553fd, - 0x1bf40142, - 0x0137f0d8, - 0xb60076bb, - 0x50f90465, - 0xbb046594, - 0x50bd0256, - 0xfc0475fd, - 0x7c21f550, - 0x0464b606, -/* 0x0754: i2c_get_byte_done */ -/* 0x0756: i2c_put_byte */ - 0x47f000f8, -/* 0x0759: i2c_put_byte_next */ - 0x0142b608, - 0xbb3854ff, + 0x64b6075a, + 0x1811f404, + 0x1388e7f1, + 0xf07f21f4, + 0x21f50037, + 0xe7f106e6, + 0x21f41388, +/* 0x084d: i2c_bitw_out */ +/* 0x084f: i2c_bitr */ + 0xf000f87f, + 0x21f50137, + 0xe7f10708, + 0x21f403e8, + 0x0076bb7f, + 0xf90465b6, + 0x04659450, + 0xbd0256bb, + 0x0475fd50, + 0x21f550fc, + 0x64b6075a, + 0x1b11f404, + 0x074221f5, + 0xf50037f0, + 0xf106e621, + 0xf41388e7, + 0x3cf07f21, + 0x0131f401, +/* 0x0894: i2c_bitr_done */ +/* 0x0896: i2c_get_byte */ + 0x57f000f8, + 0x0847f000, +/* 0x089c: i2c_get_byte_next */ + 0xbb0154b6, 0x65b60076, 0x9450f904, 0x56bb0465, 0xfd50bd02, 0x50fc0475, - 0x067c21f5, + 0x084f21f5, 0xf40464b6, - 0x46b03411, - 0xd81bf400, - 0xb60076bb, - 0x50f90465, - 0xbb046594, - 0x50bd0256, - 0xfc0475fd, - 0xbd21f550, - 0x0464b606, - 0xbb0f11f4, - 0x36b00076, - 0x061bf401, -/* 0x07af: i2c_put_byte_done */ - 0xf80132f4, -/* 0x07b1: i2c_addr */ - 0x0076bb00, + 0x53fd2b11, + 0x0142b605, + 0xf0d81bf4, + 0x76bb0137, + 0x0465b600, + 0x659450f9, + 0x0256bb04, + 0x75fd50bd, + 0xf550fc04, + 0xb6080e21, +/* 0x08e6: i2c_get_byte_done */ + 0x00f80464, +/* 0x08e8: i2c_put_byte */ +/* 0x08eb: i2c_put_byte_next */ + 0xb60847f0, + 0x54ff0142, + 0x0076bb38, 0xf90465b6, 0x04659450, 0xbd0256bb, 0x0475fd50, 0x21f550fc, - 0x64b605ed, - 0x2911f404, - 0x012ec3e7, - 0xfd0134b6, - 0x76bb0553, + 0x64b6080e, + 0x3411f404, + 0xf40046b0, + 0x76bbd81b, 0x0465b600, 0x659450f9, 0x0256bb04, 0x75fd50bd, 0xf550fc04, - 0xb6075621, -/* 0x07f6: i2c_addr_done */ - 0x00f80464, -/* 0x07f8: i2c_acquire_addr */ - 0xb6f8cec7, - 0xe0b702e4, - 0xee980bfc, -/* 0x0807: i2c_acquire */ - 0xf500f800, - 0xf407f821, - 0xd9f00421, - 0x3f21f403, -/* 0x0816: i2c_release */ - 0x21f500f8, - 0x21f407f8, - 0x03daf004, - 0xf83f21f4, -/* 0x0825: i2c_recv */ - 0x0132f400, - 0xb6f8c1c7, - 0x16b00214, - 0x3a1ff528, - 0xd413a001, - 0x0032980b, - 0x0bac13a0, - 0xf4003198, - 0xd0f90231, - 0xd0f9e0f9, - 0x000067f1, - 0x100063f1, - 0xbb016792, + 0xb6084f21, + 0x11f40464, + 0x0076bb0f, + 0xf40136b0, + 0x32f4061b, +/* 0x0941: i2c_put_byte_done */ +/* 0x0943: i2c_addr */ + 0xbb00f801, 0x65b60076, 0x9450f904, 0x56bb0465, 0xfd50bd02, 0x50fc0475, - 0x080721f5, - 0xfc0464b6, - 0x00d6b0d0, - 0x00b31bf5, - 0xbb0057f0, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x07b121f5, - 0xf50464b6, - 0xc700d011, - 0x76bbe0c5, - 0x0465b600, - 0x659450f9, - 0x0256bb04, - 0x75fd50bd, - 0xf550fc04, - 0xb6075621, - 0x11f50464, - 0x57f000ad, + 0x077f21f5, + 0xf40464b6, + 0xc3e72911, + 0x34b6012e, + 0x0553fd01, + 0xb60076bb, + 0x50f90465, + 0xbb046594, + 0x50bd0256, + 0xfc0475fd, + 0xe821f550, + 0x0464b608, +/* 0x0988: i2c_addr_done */ +/* 0x098a: i2c_acquire_addr */ + 0xcec700f8, + 0x02e4b6f8, + 0x0c10e0b7, + 0xf800ee98, +/* 0x0999: i2c_acquire */ + 0x8a21f500, + 0x0421f409, + 0xf403d9f0, + 0x00f83f21, +/* 0x09a8: i2c_release */ + 0x098a21f5, + 0xf00421f4, + 0x21f403da, +/* 0x09b7: i2c_recv */ + 0xf400f83f, + 0xc1c70132, + 0x0214b6f8, + 0xf52816b0, + 0xa0013a1f, + 0x980be813, + 0x13a00032, + 0x31980bc0, + 0x0231f400, + 0xe0f9d0f9, + 0x67f1d0f9, + 0x63f10000, + 0x67921000, 0x0076bb01, 0xf90465b6, 0x04659450, 0xbd0256bb, 0x0475fd50, 0x21f550fc, - 0x64b607b1, - 0x8a11f504, + 0x64b60999, + 0xb0d0fc04, + 0x1bf500d6, + 0x57f000b3, 0x0076bb00, 0xf90465b6, 0x04659450, 0xbd0256bb, 0x0475fd50, 0x21f550fc, - 0x64b60704, - 0x6a11f404, - 0xbbe05bcb, + 0x64b60943, + 0xd011f504, + 0xe0c5c700, + 0xb60076bb, + 0x50f90465, + 0xbb046594, + 0x50bd0256, + 0xfc0475fd, + 0xe821f550, + 0x0464b608, + 0x00ad11f5, + 0xbb0157f0, 0x65b60076, 0x9450f904, 0x56bb0465, 0xfd50bd02, 0x50fc0475, - 0x064921f5, - 0xb90464b6, - 0x74bd025b, -/* 0x092b: i2c_recv_not_rd08 */ - 0xb0430ef4, - 0x1bf401d6, - 0x0057f03d, - 0x07b121f5, - 0xc73311f4, - 0x21f5e0c5, - 0x11f40756, - 0x0057f029, - 0x07b121f5, - 0xc71f11f4, - 0x21f5e0b5, - 0x11f40756, - 0x4921f515, - 0xc774bd06, - 0x1bf408c5, - 0x0232f409, -/* 0x096b: i2c_recv_not_wr08 */ -/* 0x096b: i2c_recv_done */ - 0xc7030ef4, - 0x21f5f8ce, - 0xe0fc0816, - 0x12f4d0fc, - 0x027cb90a, - 0x02b921f5, -/* 0x0980: i2c_recv_exit */ -/* 0x0982: i2c_init */ - 0x00f800f8, -/* 0x0984: test_recv */ - 0x05d817f1, + 0x094321f5, + 0xf50464b6, + 0xbb008a11, + 0x65b60076, + 0x9450f904, + 0x56bb0465, + 0xfd50bd02, + 0x50fc0475, + 0x089621f5, + 0xf40464b6, + 0x5bcb6a11, + 0x0076bbe0, + 0xf90465b6, + 0x04659450, + 0xbd0256bb, + 0x0475fd50, + 0x21f550fc, + 0x64b607db, + 0x025bb904, + 0x0ef474bd, +/* 0x0abd: i2c_recv_not_rd08 */ + 0x01d6b043, + 0xf03d1bf4, + 0x21f50057, + 0x11f40943, + 0xe0c5c733, + 0x08e821f5, + 0xf02911f4, + 0x21f50057, + 0x11f40943, + 0xe0b5c71f, + 0x08e821f5, + 0xf51511f4, + 0xbd07db21, + 0x08c5c774, + 0xf4091bf4, + 0x0ef40232, +/* 0x0afd: i2c_recv_not_wr08 */ +/* 0x0afd: i2c_recv_done */ + 0xf8cec703, + 0x09a821f5, + 0xd0fce0fc, + 0xb90a12f4, + 0x21f5027c, +/* 0x0b12: i2c_recv_exit */ + 0x00f80342, +/* 0x0b14: i2c_init */ +/* 0x0b16: test_recv */ + 0x17f100f8, + 0x14b605d8, + 0x0011cf06, + 0xf10110b6, + 0xb605d807, + 0x01d00604, + 0xf104bd00, + 0xf1d900e7, + 0xf5134fe3, + 0xf8026221, +/* 0x0b3d: test_init */ + 0x00e7f100, + 0x6221f508, +/* 0x0b47: idle_recv */ + 0xf800f802, +/* 0x0b49: idle */ + 0x0031f400, + 0x05d417f1, 0xcf0614b6, 0x10b60011, - 0xd807f101, + 0xd407f101, 0x0604b605, 0xbd0001d0, - 0x00e7f104, - 0x4fe3f1d9, - 0xf521f513, -/* 0x09ab: test_init */ - 0xf100f801, - 0xf50800e7, - 0xf801f521, -/* 0x09b5: idle_recv */ -/* 0x09b7: idle */ - 0xf400f800, - 0x17f10031, - 0x14b605d4, - 0x0011cf06, - 0xf10110b6, - 0xb605d407, - 0x01d00604, -/* 0x09d3: idle_loop */ - 0xf004bd00, - 0x32f45817, -/* 0x09d9: idle_proc */ -/* 0x09d9: idle_proc_exec */ - 0xb910f902, - 0x21f5021e, - 0x10fc02c2, - 0xf40911f4, - 0x0ef40231, -/* 0x09ed: idle_proc_next */ - 0x5810b6ef, - 0xf4061fb8, - 0x02f4e61b, - 0x0028f4dd, - 0x00bb0ef4, +/* 0x0b65: idle_loop */ + 0x5817f004, +/* 0x0b6b: idle_proc */ +/* 0x0b6b: idle_proc_exec */ + 0xf90232f4, + 0x021eb910, + 0x034b21f5, + 0x11f410fc, + 0x0231f409, +/* 0x0b7f: idle_proc_next */ + 0xb6ef0ef4, + 0x1fb85810, + 0xe61bf406, + 0xf4dd02f4, + 0x0ef40028, + 0x000000bb, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc index 48f79434a449..21bf8cc7618f 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc @@ -23,6 +23,7 @@ */ #define NVKM_PPWR_CHIPSET GF100 +#define HW_TICKS_PER_US 203 // should be 202.5 //#define NVKM_FALCON_PC24 //#define NVKM_FALCON_UNSHIFTED_IO @@ -34,6 +35,7 @@ .section #nvc0_pwr_data #define INCLUDE_PROC #include "kernel.fuc" +#include "arith.fuc" #include "host.fuc" #include "memx.fuc" #include "perf.fuc" @@ -44,6 +46,7 @@ #define INCLUDE_DATA #include "kernel.fuc" +#include "arith.fuc" #include "host.fuc" #include "memx.fuc" #include "perf.fuc" @@ -56,6 +59,7 @@ .section #nvc0_pwr_code #define INCLUDE_CODE #include "kernel.fuc" +#include "arith.fuc" #include "host.fuc" #include "memx.fuc" #include "perf.fuc" diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h index 7ac87405d01b..ca30fa4011b5 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h @@ -24,8 +24,8 @@ uint32_t nvc0_pwr_data[] = { 0x00000000, /* 0x0058: proc_list_head */ 0x54534f48, - 0x00000430, - 0x000003cd, + 0x00000512, + 0x000004af, 0x00000000, 0x00000000, 0x00000000, @@ -46,8 +46,8 @@ uint32_t nvc0_pwr_data[] = { 0x00000000, 0x00000000, 0x584d454d, - 0x0000054e, - 0x00000540, + 0x0000074b, + 0x0000073d, 0x00000000, 0x00000000, 0x00000000, @@ -68,8 +68,8 @@ uint32_t nvc0_pwr_data[] = { 0x00000000, 0x00000000, 0x46524550, - 0x00000552, - 0x00000550, + 0x0000074f, + 0x0000074d, 0x00000000, 0x00000000, 0x00000000, @@ -90,8 +90,8 @@ uint32_t nvc0_pwr_data[] = { 0x00000000, 0x00000000, 0x5f433249, - 0x00000982, - 0x00000825, + 0x00000b7f, + 0x00000a22, 0x00000000, 0x00000000, 0x00000000, @@ -112,8 +112,8 @@ uint32_t nvc0_pwr_data[] = { 0x00000000, 0x00000000, 0x54534554, - 0x000009ab, - 0x00000984, + 0x00000ba8, + 0x00000b81, 0x00000000, 0x00000000, 0x00000000, @@ -134,8 +134,8 @@ uint32_t nvc0_pwr_data[] = { 0x00000000, 0x00000000, 0x454c4449, - 0x000009b7, - 0x000009b5, + 0x00000bb4, + 0x00000bb2, 0x00000000, 0x00000000, 0x00000000, @@ -227,25 +227,31 @@ uint32_t nvc0_pwr_data[] = { 0x00000000, 0x00000000, /* 0x0370: memx_func_head */ - 0x00010000, - 0x00000000, - 0x0000046f, -/* 0x037c: memx_func_next */ 0x00000001, 0x00000000, - 0x00000496, + 0x00000551, +/* 0x037c: memx_func_next */ 0x00000002, + 0x00000000, + 0x000005db, + 0x00000003, 0x00000002, - 0x000004b7, - 0x00040003, + 0x000006a5, + 0x00040004, + 0x00000000, + 0x000006c1, + 0x00010005, + 0x00000000, + 0x000006de, + 0x00010006, 0x00000000, - 0x000004df, - 0x00010004, + 0x00000663, +/* 0x03b8: memx_func_tail */ +/* 0x03b8: memx_ts_start */ 0x00000000, - 0x000004fc, -/* 0x03ac: memx_func_tail */ -/* 0x03ac: memx_data_head */ +/* 0x03bc: memx_ts_end */ 0x00000000, +/* 0x03c0: memx_data_head */ 0x00000000, 0x00000000, 0x00000000, @@ -757,8 +763,9 @@ uint32_t nvc0_pwr_data[] = { 0x00000000, 0x00000000, 0x00000000, -/* 0x0bac: memx_data_tail */ -/* 0x0bac: i2c_scl_map */ + 0x00000000, +/* 0x0bc0: memx_data_tail */ +/* 0x0bc0: i2c_scl_map */ 0x00001000, 0x00004000, 0x00010000, @@ -769,7 +776,7 @@ uint32_t nvc0_pwr_data[] = { 0x01000000, 0x04000000, 0x10000000, -/* 0x0bd4: i2c_sda_map */ +/* 0x0be8: i2c_sda_map */ 0x00002000, 0x00008000, 0x00020000, @@ -780,7 +787,7 @@ uint32_t nvc0_pwr_data[] = { 0x02000000, 0x08000000, 0x20000000, -/* 0x0bfc: i2c_ctrl */ +/* 0x0c10: i2c_ctrl */ 0x0000e138, 0x0000e150, 0x0000e168, @@ -841,15 +848,10 @@ uint32_t nvc0_pwr_data[] = { 0x00000000, 0x00000000, 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, }; uint32_t nvc0_pwr_code[] = { - 0x030d0ef5, + 0x039e0ef5, /* 0x0004: rd32 */ 0x07a007f1, 0xd00604b6, @@ -885,19 +887,22 @@ uint32_t nvc0_pwr_code[] = { 0xd4f100dd, 0x1bf47000, /* 0x007f: nsec */ - 0xf000f8f2, + 0xf900f8f2, + 0xf080f990, 0x84b62c87, 0x0088cf06, -/* 0x0088: nsec_loop */ +/* 0x008c: nsec_loop */ 0xb62c97f0, 0x99cf0694, 0x0298bb00, 0xf4069eb8, - 0x00f8f11e, -/* 0x009c: wait */ + 0x80fcf11e, + 0x00f890fc, +/* 0x00a4: wait */ + 0x80f990f9, 0xb62c87f0, 0x88cf0684, -/* 0x00a5: wait_loop */ +/* 0x00b1: wait_loop */ 0x02eeb900, 0xb90421f4, 0xadfd02da, @@ -907,28 +912,29 @@ uint32_t nvc0_pwr_code[] = { 0x0099cf06, 0xb80298bb, 0x1ef4069b, -/* 0x00c9: wait_done */ -/* 0x00cb: intr_watchdog */ - 0x9800f8df, +/* 0x00d5: wait_done */ + 0xfc80fcdf, +/* 0x00db: intr_watchdog */ + 0x9800f890, 0x96b003e9, 0x2a0bf400, 0xbb9a0a98, 0x1cf4029a, 0x01d7f00f, - 0x025421f5, + 0x02dd21f5, 0x0ef494bd, -/* 0x00e9: intr_watchdog_next_time */ +/* 0x00f9: intr_watchdog_next_time */ 0x9b0a9815, 0xf400a6b0, 0x9ab8090b, 0x061cf406, -/* 0x00f8: intr_watchdog_next_time_set */ -/* 0x00fb: intr_watchdog_next_proc */ +/* 0x0108: intr_watchdog_next_time_set */ +/* 0x010b: intr_watchdog_next_proc */ 0x809b0980, 0xe0b603e9, 0x68e6b158, 0xc61bf402, -/* 0x010a: intr */ +/* 0x011a: intr */ 0x00f900f8, 0x80f904bd, 0xa0f990f9, @@ -948,13 +954,13 @@ uint32_t nvc0_pwr_code[] = { 0xf40289c4, 0x0080230b, 0x58e7f09b, - 0x98cb21f4, + 0x98db21f4, 0x96b09b09, 0x110bf400, 0xb63407f0, 0x09d00604, 0x8004bd00, -/* 0x016e: intr_skip_watchdog */ +/* 0x017e: intr_skip_watchdog */ 0x89e49a09, 0x0bf40800, 0x8897f148, @@ -967,22 +973,22 @@ uint32_t nvc0_pwr_code[] = { 0x48e7f1c0, 0x53e3f14f, 0x00d7f054, - 0x02b921f5, + 0x034221f5, 0x07f1c0fc, 0x04b604c0, 0x000cd006, -/* 0x01ae: intr_subintr_skip_fifo */ +/* 0x01be: intr_subintr_skip_fifo */ 0x07f104bd, 0x04b60688, 0x0009d006, -/* 0x01ba: intr_skip_subintr */ +/* 0x01ca: intr_skip_subintr */ 0x89c404bd, 0x070bf420, 0xffbfa4f1, -/* 0x01c4: intr_skip_pause */ +/* 0x01d4: intr_skip_pause */ 0xf44089c4, 0xa4f1070b, -/* 0x01ce: intr_skip_user0 */ +/* 0x01de: intr_skip_user0 */ 0x07f0ffbf, 0x0604b604, 0xbd0008d0, @@ -993,597 +999,733 @@ uint32_t nvc0_pwr_code[] = { 0x90fca0fc, 0x00fc80fc, 0xf80032f4, -/* 0x01f5: timer */ - 0x1032f401, - 0xb003f898, - 0x1cf40086, - 0x03fe8051, +/* 0x0205: ticks_from_ns */ + 0xf9c0f901, + 0xcbd7f1b0, + 0x00d3f000, + 0x041321f5, + 0x03e8ccec, + 0xf400b4b0, + 0xeeec120b, + 0xd7f103e8, + 0xd3f000cb, + 0x1321f500, +/* 0x022d: ticks_from_ns_quit */ + 0x02ceb904, + 0xc0fcb0fc, +/* 0x0236: ticks_from_us */ + 0xc0f900f8, + 0xd7f1b0f9, + 0xd3f000cb, + 0x1321f500, + 0x02ceb904, + 0xf400b4b0, + 0xe4bd050b, +/* 0x0250: ticks_from_us_quit */ + 0xc0fcb0fc, +/* 0x0256: ticks_to_us */ + 0xd7f100f8, + 0xd3f000cb, + 0xecedff00, +/* 0x0262: timer */ + 0x90f900f8, + 0x32f480f9, + 0x03f89810, + 0xf40086b0, + 0x84bd651c, 0xb63807f0, 0x08d00604, 0xf004bd00, - 0x84b60887, + 0x84b63487, 0x0088cf06, - 0xf40284f0, - 0x87f0261b, - 0x0684b634, - 0xb80088cf, - 0x0bf406e0, - 0x06e8b809, -/* 0x0233: timer_reset */ - 0xf01f1ef4, - 0x04b63407, - 0x000ed006, - 0x0e8004bd, -/* 0x0241: timer_enable */ - 0x0187f09a, + 0xbb9a0998, + 0xe9bb0298, + 0x03fe8000, + 0xb60887f0, + 0x88cf0684, + 0x0284f000, + 0xf0261bf4, + 0x84b63487, + 0x0088cf06, + 0xf406e0b8, + 0xe8b8090b, + 0x111cf406, +/* 0x02b8: timer_reset */ + 0xb63407f0, + 0x0ed00604, + 0x8004bd00, +/* 0x02c6: timer_enable */ + 0x87f09a0e, + 0x3807f001, + 0xd00604b6, + 0x04bd0008, +/* 0x02d4: timer_done */ + 0xfc1031f4, + 0xf890fc80, +/* 0x02dd: send_proc */ + 0xf980f900, + 0x05e89890, + 0xf004e998, + 0x89b80486, + 0x2a0bf406, + 0x940398c4, + 0x80b60488, + 0x008ebb18, + 0x8000fa98, + 0x8d80008a, + 0x028c8001, + 0xb6038b80, + 0x94f00190, + 0x04e98007, +/* 0x0317: send_done */ + 0xfc0231f4, + 0xf880fc90, +/* 0x031d: find */ + 0xf080f900, + 0x31f45887, +/* 0x0325: find_loop */ + 0x008a9801, + 0xf406aeb8, + 0x80b6100b, + 0x6886b158, + 0xf01bf402, +/* 0x033b: find_done */ + 0xb90132f4, + 0x80fc028e, +/* 0x0342: send */ + 0x21f500f8, + 0x01f4031d, +/* 0x034b: recv */ + 0xf900f897, + 0x9880f990, + 0xe99805e8, + 0x0132f404, + 0xf40689b8, + 0x89c43d0b, + 0x0180b603, + 0x800784f0, + 0xea9805e8, + 0xfef0f902, + 0xf0f9018f, + 0x9402efb9, + 0xe9bb0499, + 0x18e0b600, + 0x9803eb98, + 0xed9802ec, + 0x00ee9801, + 0xf0fca5f9, + 0xf400f8fe, + 0xf0fc0131, +/* 0x0398: recv_done */ + 0x90fc80fc, +/* 0x039e: init */ + 0x17f100f8, + 0x14b60108, + 0x0011cf06, + 0x010911e7, + 0xfe0814b6, + 0x17f10014, + 0x13f000e0, + 0x1c07f000, + 0xd00604b6, + 0x04bd0001, + 0xf0ff17f0, + 0x04b61407, + 0x0001d006, + 0x17f004bd, + 0x0015f102, + 0x1007f008, + 0xd00604b6, + 0x04bd0001, + 0x011a17f1, + 0xfe0013f0, + 0x31f40010, + 0x0117f010, 0xb63807f0, - 0x08d00604, -/* 0x024f: timer_done */ - 0xf404bd00, - 0x00f81031, -/* 0x0254: send_proc */ - 0x90f980f9, - 0x9805e898, - 0x86f004e9, - 0x0689b804, - 0xc42a0bf4, - 0x88940398, - 0x1880b604, - 0x98008ebb, - 0x8a8000fa, - 0x018d8000, - 0x80028c80, - 0x90b6038b, - 0x0794f001, - 0xf404e980, -/* 0x028e: send_done */ - 0x90fc0231, - 0x00f880fc, -/* 0x0294: find */ - 0x87f080f9, - 0x0131f458, -/* 0x029c: find_loop */ - 0xb8008a98, - 0x0bf406ae, - 0x5880b610, - 0x026886b1, - 0xf4f01bf4, -/* 0x02b2: find_done */ - 0x8eb90132, - 0xf880fc02, -/* 0x02b9: send */ - 0x9421f500, - 0x9701f402, -/* 0x02c2: recv */ - 0xe89800f8, - 0x04e99805, - 0xb80132f4, - 0x0bf40689, - 0x0389c43d, - 0xf00180b6, - 0xe8800784, - 0x02ea9805, - 0x8ffef0f9, - 0xb9f0f901, - 0x999402ef, - 0x00e9bb04, - 0x9818e0b6, - 0xec9803eb, - 0x01ed9802, - 0xf900ee98, - 0xfef0fca5, - 0x31f400f8, -/* 0x030b: recv_done */ - 0xf8f0fc01, -/* 0x030d: init */ - 0x0817f100, - 0x0614b601, - 0xe70011cf, - 0xb6010911, - 0x14fe0814, - 0xe017f100, - 0x0013f000, - 0xb61c07f0, 0x01d00604, 0xf004bd00, - 0x07f0ff17, - 0x0604b614, - 0xbd0001d0, - 0x0217f004, - 0x080015f1, - 0xb61007f0, - 0x01d00604, - 0xf104bd00, - 0xf0010a17, - 0x10fe0013, - 0x1031f400, - 0xf00117f0, - 0x04b63807, - 0x0001d006, - 0xf7f004bd, -/* 0x0371: init_proc */ - 0x01f19858, - 0xf40016b0, - 0x15f9fa0b, - 0xf458f0b6, -/* 0x0382: host_send */ - 0x17f1f20e, - 0x14b604b0, - 0x0011cf06, - 0x04a027f1, - 0xcf0624b6, - 0x12b80022, - 0x320bf406, - 0x94071ec4, - 0xe0b704ee, - 0xeb980270, - 0x02ec9803, - 0x9801ed98, - 0x21f500ee, - 0x10b602b9, - 0x0f1ec401, - 0x04b007f1, - 0xd00604b6, - 0x04bd000e, -/* 0x03cb: host_send_done */ - 0xf8ba0ef4, -/* 0x03cd: host_recv */ - 0x4917f100, - 0x5413f14e, - 0x06e1b852, -/* 0x03db: host_recv_wait */ - 0xf1aa0bf4, - 0xb604cc17, - 0x11cf0614, - 0xc827f100, - 0x0624b604, - 0xf00022cf, - 0x12b80816, - 0xe60bf406, - 0xb60723c4, - 0x30b70434, - 0x3b8002f0, - 0x023c8003, - 0x80013d80, - 0x20b6003e, - 0x0f24f001, - 0x04c807f1, +/* 0x0402: init_proc */ + 0xf19858f7, + 0x0016b001, + 0xf9fa0bf4, + 0x58f0b615, +/* 0x0413: mulu32_32_64 */ + 0xf9f20ef4, + 0xf920f910, + 0x9540f930, + 0xd29510e1, + 0xbdc4bd10, + 0xc0edffb4, + 0xb9301dff, + 0x34f10234, + 0x34b6ffff, + 0x1045b610, + 0xbb00c3bb, + 0xe2ff01b4, + 0x0234b930, + 0xffff34f1, + 0xb61034b6, + 0xc3bb1045, + 0x01b4bb00, + 0xbb3012ff, + 0x40fc00b3, + 0x20fc30fc, + 0x00f810fc, +/* 0x0464: host_send */ + 0x04b017f1, + 0xcf0614b6, + 0x27f10011, + 0x24b604a0, + 0x0022cf06, + 0xf40612b8, + 0x1ec4320b, + 0x04ee9407, + 0x0270e0b7, + 0x9803eb98, + 0xed9802ec, + 0x00ee9801, + 0x034221f5, + 0xc40110b6, + 0x07f10f1e, + 0x04b604b0, + 0x000ed006, + 0x0ef404bd, +/* 0x04ad: host_send_done */ +/* 0x04af: host_recv */ + 0xf100f8ba, + 0xf14e4917, + 0xb8525413, + 0x0bf406e1, +/* 0x04bd: host_recv_wait */ + 0xcc17f1aa, + 0x0614b604, + 0xf10011cf, + 0xb604c827, + 0x22cf0624, + 0x0816f000, + 0xf40612b8, + 0x23c4e60b, + 0x0434b607, + 0x02f030b7, + 0x80033b80, + 0x3d80023c, + 0x003e8001, + 0xf00120b6, + 0x07f10f24, + 0x04b604c8, + 0x0002d006, + 0x27f004bd, + 0x0007f040, 0xd00604b6, 0x04bd0002, - 0xf04027f0, - 0x04b60007, - 0x0002d006, - 0x00f804bd, -/* 0x0430: host_init */ - 0x008017f1, - 0xf11014b6, - 0xf1027015, - 0xb604d007, - 0x01d00604, - 0xf104bd00, - 0xb6008017, - 0x15f11014, - 0x07f102f0, - 0x04b604dc, - 0x0001d006, - 0x17f004bd, - 0xc407f101, +/* 0x0512: host_init */ + 0x17f100f8, + 0x14b60080, + 0x7015f110, + 0xd007f102, 0x0604b604, 0xbd0001d0, -/* 0x046f: memx_func_enter */ - 0xf000f804, + 0x8017f104, + 0x1014b600, + 0x02f015f1, + 0x04dc07f1, + 0xd00604b6, + 0x04bd0001, + 0xf10117f0, + 0xb604c407, + 0x01d00604, + 0xf804bd00, +/* 0x0551: memx_func_enter */ + 0x2067f100, + 0x5d77f116, + 0xff73f1f5, + 0x026eb9ff, + 0xb90421f4, + 0x87fd02d8, + 0xf960f904, + 0xfcd0fc80, + 0x3f21f4e0, + 0xfffe77f1, + 0xffff73f1, + 0xf4026eb9, + 0xd8b90421, + 0x0487fd02, + 0x80f960f9, + 0xe0fcd0fc, + 0xf13f21f4, + 0xb926f067, + 0x21f4026e, + 0x02d8b904, + 0xf90487fd, + 0xfc80f960, + 0xf4e0fcd0, + 0x67f03f21, + 0xe007f104, + 0x0604b607, + 0xbd0006d0, +/* 0x05bd: memx_func_enter_wait */ + 0xc067f104, + 0x0664b607, + 0xf00066cf, + 0x0bf40464, + 0x2c67f0f3, + 0xcf0664b6, + 0x06800066, +/* 0x05db: memx_func_leave */ + 0xf000f8ee, + 0x64b62c67, + 0x0066cf06, + 0xf0ef0680, 0x07f10467, - 0x04b607e0, + 0x04b607e4, 0x0006d006, -/* 0x047e: memx_func_enter_wait */ +/* 0x05f6: memx_func_leave_wait */ 0x67f104bd, 0x64b607c0, 0x0066cf06, 0xf40464f0, - 0x1698f30b, - 0x0410b600, -/* 0x0496: memx_func_leave */ - 0x67f000f8, - 0xe407f104, - 0x0604b607, - 0xbd0006d0, -/* 0x04a5: memx_func_leave_wait */ - 0xc067f104, - 0x0664b607, - 0xf00066cf, - 0x1bf40464, -/* 0x04b7: memx_func_wr32 */ - 0x9800f8f3, - 0x15980016, - 0x0810b601, - 0x50f960f9, + 0x67f1f31b, + 0x77f126f0, + 0x73f00001, + 0x026eb900, + 0xb90421f4, + 0x87fd02d8, + 0xf960f905, + 0xfcd0fc80, + 0x3f21f4e0, + 0x162067f1, + 0xf4026eb9, + 0xd8b90421, + 0x0587fd02, + 0x80f960f9, 0xe0fcd0fc, 0xf13f21f4, - 0xfd140003, - 0x05800506, - 0xb604bd00, - 0x1bf40242, -/* 0x04df: memx_func_wait */ - 0xf000f8dd, - 0x84b62c87, - 0x0088cf06, - 0x98001e98, - 0x1c98011d, - 0x031b9802, - 0xf41010b6, - 0x00f89c21, -/* 0x04fc: memx_func_delay */ - 0xb6001e98, - 0x21f40410, -/* 0x0507: memx_exec */ - 0xf900f87f, - 0xb9d0f9e0, - 0xb2b902c1, -/* 0x0511: memx_exec_next */ - 0x00139802, - 0x950410b6, - 0x30f01034, - 0xde35980c, - 0x12b855f9, - 0xec1ef406, - 0xe0fcd0fc, - 0x02b921f5, -/* 0x0532: memx_info */ - 0xc7f100f8, - 0xb7f103ac, - 0x21f50800, - 0x00f802b9, -/* 0x0540: memx_recv */ - 0xf401d6b0, - 0xd6b0c40b, - 0xe90bf400, -/* 0x054e: memx_init */ - 0x00f800f8, -/* 0x0550: perf_recv */ -/* 0x0552: perf_init */ - 0x00f800f8, -/* 0x0554: i2c_drive_scl */ - 0xf40036b0, - 0x07f1110b, - 0x04b607e0, - 0x0001d006, - 0x00f804bd, -/* 0x0568: i2c_drive_scl_lo */ - 0x07e407f1, - 0xd00604b6, - 0x04bd0001, -/* 0x0576: i2c_drive_sda */ - 0x36b000f8, - 0x110bf400, - 0x07e007f1, - 0xd00604b6, - 0x04bd0002, -/* 0x058a: i2c_drive_sda_lo */ - 0x07f100f8, - 0x04b607e4, - 0x0002d006, - 0x00f804bd, -/* 0x0598: i2c_sense_scl */ - 0xf10132f4, - 0xb607c437, - 0x33cf0634, - 0x0431fd00, - 0xf4060bf4, -/* 0x05ae: i2c_sense_scl_done */ - 0x00f80131, -/* 0x05b0: i2c_sense_sda */ - 0xf10132f4, - 0xb607c437, - 0x33cf0634, - 0x0432fd00, - 0xf4060bf4, -/* 0x05c6: i2c_sense_sda_done */ - 0x00f80131, -/* 0x05c8: i2c_raise_scl */ - 0x47f140f9, - 0x37f00898, - 0x5421f501, -/* 0x05d5: i2c_raise_scl_wait */ - 0xe8e7f105, - 0x7f21f403, - 0x059821f5, - 0xb60901f4, - 0x1bf40142, -/* 0x05e9: i2c_raise_scl_done */ - 0xf840fcef, -/* 0x05ed: i2c_start */ - 0x9821f500, - 0x0d11f405, - 0x05b021f5, - 0xf40611f4, -/* 0x05fe: i2c_start_rep */ - 0x37f0300e, - 0x5421f500, - 0x0137f005, - 0x057621f5, - 0xb60076bb, - 0x50f90465, - 0xbb046594, - 0x50bd0256, - 0xfc0475fd, - 0xc821f550, - 0x0464b605, -/* 0x062b: i2c_start_send */ - 0xf01f11f4, - 0x21f50037, - 0xe7f10576, - 0x21f41388, - 0x0037f07f, - 0x055421f5, - 0x1388e7f1, -/* 0x0647: i2c_start_out */ + 0xf00aa277, + 0x6eb90073, + 0x0421f402, + 0xfd02d8b9, + 0x60f90587, + 0xd0fc80f9, + 0x21f4e0fc, +/* 0x0663: memx_func_wait_vblank */ + 0x9800f83f, + 0x66b00016, + 0x130bf400, + 0xf40166b0, + 0x0ef4060b, +/* 0x0675: memx_func_wait_vblank_head1 */ + 0x2077f12e, + 0x070ef400, +/* 0x067c: memx_func_wait_vblank_head0 */ + 0x000877f1, +/* 0x0680: memx_func_wait_vblank_0 */ + 0x07c467f1, + 0xcf0664b6, + 0x67fd0066, + 0xf31bf404, +/* 0x0690: memx_func_wait_vblank_1 */ + 0x07c467f1, + 0xcf0664b6, + 0x67fd0066, + 0xf30bf404, +/* 0x06a0: memx_func_wait_vblank_fini */ + 0xf80410b6, +/* 0x06a5: memx_func_wr32 */ + 0x00169800, + 0xb6011598, + 0x60f90810, + 0xd0fc50f9, + 0x21f4e0fc, + 0x0242b63f, + 0xf8e91bf4, +/* 0x06c1: memx_func_wait */ + 0x2c87f000, + 0xcf0684b6, + 0x1e980088, + 0x011d9800, + 0x98021c98, + 0x10b6031b, + 0xa421f410, +/* 0x06de: memx_func_delay */ + 0x1e9800f8, + 0x0410b600, 0xf87f21f4, -/* 0x0649: i2c_stop */ - 0x0037f000, - 0x055421f5, +/* 0x06e9: memx_exec */ + 0xf9e0f900, + 0x02c1b9d0, +/* 0x06f3: memx_exec_next */ + 0x9802b2b9, + 0x10b60013, + 0xf034e704, + 0xe033e701, + 0x0132b601, + 0x980c30f0, + 0x55f9de35, + 0xf40612b8, + 0x0b98e41e, + 0xef0c98ee, + 0xf102cbbb, + 0xb607c4b7, + 0xbbcf06b4, + 0xfcd0fc00, + 0x4221f5e0, +/* 0x072f: memx_info */ + 0xf100f803, + 0xf103c0c7, + 0xf50800b7, + 0xf8034221, +/* 0x073d: memx_recv */ + 0x01d6b000, + 0xb0a90bf4, + 0x0bf400d6, +/* 0x074b: memx_init */ + 0xf800f8e9, +/* 0x074d: perf_recv */ +/* 0x074f: perf_init */ + 0xf800f800, +/* 0x0751: i2c_drive_scl */ + 0x0036b000, + 0xf1110bf4, + 0xb607e007, + 0x01d00604, + 0xf804bd00, +/* 0x0765: i2c_drive_scl_lo */ + 0xe407f100, + 0x0604b607, + 0xbd0001d0, +/* 0x0773: i2c_drive_sda */ + 0xb000f804, + 0x0bf40036, + 0xe007f111, + 0x0604b607, + 0xbd0002d0, +/* 0x0787: i2c_drive_sda_lo */ + 0xf100f804, + 0xb607e407, + 0x02d00604, + 0xf804bd00, +/* 0x0795: i2c_sense_scl */ + 0x0132f400, + 0x07c437f1, + 0xcf0634b6, + 0x31fd0033, + 0x060bf404, +/* 0x07ab: i2c_sense_scl_done */ + 0xf80131f4, +/* 0x07ad: i2c_sense_sda */ + 0x0132f400, + 0x07c437f1, + 0xcf0634b6, + 0x32fd0033, + 0x060bf404, +/* 0x07c3: i2c_sense_sda_done */ + 0xf80131f4, +/* 0x07c5: i2c_raise_scl */ + 0xf140f900, + 0xf0089847, + 0x21f50137, +/* 0x07d2: i2c_raise_scl_wait */ + 0xe7f10751, + 0x21f403e8, + 0x9521f57f, + 0x0901f407, + 0xf40142b6, +/* 0x07e6: i2c_raise_scl_done */ + 0x40fcef1b, +/* 0x07ea: i2c_start */ + 0x21f500f8, + 0x11f40795, + 0xad21f50d, + 0x0611f407, +/* 0x07fb: i2c_start_rep */ + 0xf0300ef4, + 0x21f50037, + 0x37f00751, + 0x7321f501, + 0x0076bb07, + 0xf90465b6, + 0x04659450, + 0xbd0256bb, + 0x0475fd50, + 0x21f550fc, + 0x64b607c5, + 0x1f11f404, +/* 0x0828: i2c_start_send */ 0xf50037f0, - 0xf1057621, - 0xf403e8e7, + 0xf1077321, + 0xf41388e7, 0x37f07f21, - 0x5421f501, - 0x88e7f105, + 0x5121f500, + 0x88e7f107, 0x7f21f413, - 0xf50137f0, - 0xf1057621, - 0xf41388e7, - 0x00f87f21, -/* 0x067c: i2c_bitw */ - 0x057621f5, +/* 0x0844: i2c_start_out */ +/* 0x0846: i2c_stop */ + 0x37f000f8, + 0x5121f500, + 0x0037f007, + 0x077321f5, 0x03e8e7f1, - 0xbb7f21f4, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x05c821f5, - 0xf40464b6, - 0xe7f11811, + 0xf07f21f4, + 0x21f50137, + 0xe7f10751, 0x21f41388, - 0x0037f07f, - 0x055421f5, + 0x0137f07f, + 0x077321f5, 0x1388e7f1, -/* 0x06bb: i2c_bitw_out */ 0xf87f21f4, -/* 0x06bd: i2c_bitr */ - 0x0137f000, - 0x057621f5, - 0x03e8e7f1, - 0xbb7f21f4, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x05c821f5, - 0xf40464b6, - 0x21f51b11, - 0x37f005b0, - 0x5421f500, - 0x88e7f105, +/* 0x0879: i2c_bitw */ + 0x7321f500, + 0xe8e7f107, + 0x7f21f403, + 0xb60076bb, + 0x50f90465, + 0xbb046594, + 0x50bd0256, + 0xfc0475fd, + 0xc521f550, + 0x0464b607, + 0xf11811f4, + 0xf41388e7, + 0x37f07f21, + 0x5121f500, + 0x88e7f107, 0x7f21f413, - 0xf4013cf0, -/* 0x0702: i2c_bitr_done */ - 0x00f80131, -/* 0x0704: i2c_get_byte */ - 0xf00057f0, -/* 0x070a: i2c_get_byte_next */ - 0x54b60847, +/* 0x08b8: i2c_bitw_out */ +/* 0x08ba: i2c_bitr */ + 0x37f000f8, + 0x7321f501, + 0xe8e7f107, + 0x7f21f403, + 0xb60076bb, + 0x50f90465, + 0xbb046594, + 0x50bd0256, + 0xfc0475fd, + 0xc521f550, + 0x0464b607, + 0xf51b11f4, + 0xf007ad21, + 0x21f50037, + 0xe7f10751, + 0x21f41388, + 0x013cf07f, +/* 0x08ff: i2c_bitr_done */ + 0xf80131f4, +/* 0x0901: i2c_get_byte */ + 0x0057f000, +/* 0x0907: i2c_get_byte_next */ + 0xb60847f0, + 0x76bb0154, + 0x0465b600, + 0x659450f9, + 0x0256bb04, + 0x75fd50bd, + 0xf550fc04, + 0xb608ba21, + 0x11f40464, + 0x0553fd2b, + 0xf40142b6, + 0x37f0d81b, 0x0076bb01, 0xf90465b6, 0x04659450, 0xbd0256bb, 0x0475fd50, 0x21f550fc, - 0x64b606bd, - 0x2b11f404, - 0xb60553fd, - 0x1bf40142, - 0x0137f0d8, - 0xb60076bb, - 0x50f90465, - 0xbb046594, - 0x50bd0256, - 0xfc0475fd, - 0x7c21f550, - 0x0464b606, -/* 0x0754: i2c_get_byte_done */ -/* 0x0756: i2c_put_byte */ - 0x47f000f8, -/* 0x0759: i2c_put_byte_next */ - 0x0142b608, - 0xbb3854ff, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x067c21f5, - 0xf40464b6, - 0x46b03411, - 0xd81bf400, + 0x64b60879, +/* 0x0951: i2c_get_byte_done */ +/* 0x0953: i2c_put_byte */ + 0xf000f804, +/* 0x0956: i2c_put_byte_next */ + 0x42b60847, + 0x3854ff01, 0xb60076bb, 0x50f90465, 0xbb046594, 0x50bd0256, 0xfc0475fd, - 0xbd21f550, - 0x0464b606, - 0xbb0f11f4, - 0x36b00076, - 0x061bf401, -/* 0x07af: i2c_put_byte_done */ - 0xf80132f4, -/* 0x07b1: i2c_addr */ - 0x0076bb00, + 0x7921f550, + 0x0464b608, + 0xb03411f4, + 0x1bf40046, + 0x0076bbd8, 0xf90465b6, 0x04659450, 0xbd0256bb, 0x0475fd50, 0x21f550fc, - 0x64b605ed, - 0x2911f404, - 0x012ec3e7, - 0xfd0134b6, - 0x76bb0553, + 0x64b608ba, + 0x0f11f404, + 0xb00076bb, + 0x1bf40136, + 0x0132f406, +/* 0x09ac: i2c_put_byte_done */ +/* 0x09ae: i2c_addr */ + 0x76bb00f8, 0x0465b600, 0x659450f9, 0x0256bb04, 0x75fd50bd, 0xf550fc04, - 0xb6075621, -/* 0x07f6: i2c_addr_done */ - 0x00f80464, -/* 0x07f8: i2c_acquire_addr */ - 0xb6f8cec7, - 0xe0b702e4, - 0xee980bfc, -/* 0x0807: i2c_acquire */ - 0xf500f800, - 0xf407f821, - 0xd9f00421, - 0x3f21f403, -/* 0x0816: i2c_release */ - 0x21f500f8, - 0x21f407f8, - 0x03daf004, - 0xf83f21f4, -/* 0x0825: i2c_recv */ - 0x0132f400, - 0xb6f8c1c7, - 0x16b00214, - 0x3a1ff528, - 0xd413a001, - 0x0032980b, - 0x0bac13a0, - 0xf4003198, - 0xd0f90231, - 0xd0f9e0f9, - 0x000067f1, - 0x100063f1, - 0xbb016792, + 0xb607ea21, + 0x11f40464, + 0x2ec3e729, + 0x0134b601, + 0xbb0553fd, 0x65b60076, 0x9450f904, 0x56bb0465, 0xfd50bd02, 0x50fc0475, - 0x080721f5, - 0xfc0464b6, - 0x00d6b0d0, - 0x00b31bf5, - 0xbb0057f0, + 0x095321f5, +/* 0x09f3: i2c_addr_done */ + 0xf80464b6, +/* 0x09f5: i2c_acquire_addr */ + 0xf8cec700, + 0xb702e4b6, + 0x980c10e0, + 0x00f800ee, +/* 0x0a04: i2c_acquire */ + 0x09f521f5, + 0xf00421f4, + 0x21f403d9, +/* 0x0a13: i2c_release */ + 0xf500f83f, + 0xf409f521, + 0xdaf00421, + 0x3f21f403, +/* 0x0a22: i2c_recv */ + 0x32f400f8, + 0xf8c1c701, + 0xb00214b6, + 0x1ff52816, + 0x13a0013a, + 0x32980be8, + 0xc013a000, + 0x0031980b, + 0xf90231f4, + 0xf9e0f9d0, + 0x0067f1d0, + 0x0063f100, + 0x01679210, + 0xb60076bb, + 0x50f90465, + 0xbb046594, + 0x50bd0256, + 0xfc0475fd, + 0x0421f550, + 0x0464b60a, + 0xd6b0d0fc, + 0xb31bf500, + 0x0057f000, + 0xb60076bb, + 0x50f90465, + 0xbb046594, + 0x50bd0256, + 0xfc0475fd, + 0xae21f550, + 0x0464b609, + 0x00d011f5, + 0xbbe0c5c7, 0x65b60076, 0x9450f904, 0x56bb0465, 0xfd50bd02, 0x50fc0475, - 0x07b121f5, + 0x095321f5, 0xf50464b6, - 0xc700d011, - 0x76bbe0c5, + 0xf000ad11, + 0x76bb0157, 0x0465b600, 0x659450f9, 0x0256bb04, 0x75fd50bd, 0xf550fc04, - 0xb6075621, + 0xb609ae21, 0x11f50464, - 0x57f000ad, - 0x0076bb01, - 0xf90465b6, - 0x04659450, - 0xbd0256bb, - 0x0475fd50, - 0x21f550fc, - 0x64b607b1, - 0x8a11f504, - 0x0076bb00, - 0xf90465b6, - 0x04659450, - 0xbd0256bb, - 0x0475fd50, - 0x21f550fc, - 0x64b60704, - 0x6a11f404, - 0xbbe05bcb, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x064921f5, - 0xb90464b6, - 0x74bd025b, -/* 0x092b: i2c_recv_not_rd08 */ - 0xb0430ef4, - 0x1bf401d6, - 0x0057f03d, - 0x07b121f5, - 0xc73311f4, - 0x21f5e0c5, - 0x11f40756, - 0x0057f029, - 0x07b121f5, - 0xc71f11f4, - 0x21f5e0b5, - 0x11f40756, - 0x4921f515, - 0xc774bd06, - 0x1bf408c5, - 0x0232f409, -/* 0x096b: i2c_recv_not_wr08 */ -/* 0x096b: i2c_recv_done */ - 0xc7030ef4, - 0x21f5f8ce, - 0xe0fc0816, - 0x12f4d0fc, - 0x027cb90a, - 0x02b921f5, -/* 0x0980: i2c_recv_exit */ -/* 0x0982: i2c_init */ + 0x76bb008a, + 0x0465b600, + 0x659450f9, + 0x0256bb04, + 0x75fd50bd, + 0xf550fc04, + 0xb6090121, + 0x11f40464, + 0xe05bcb6a, + 0xb60076bb, + 0x50f90465, + 0xbb046594, + 0x50bd0256, + 0xfc0475fd, + 0x4621f550, + 0x0464b608, + 0xbd025bb9, + 0x430ef474, +/* 0x0b28: i2c_recv_not_rd08 */ + 0xf401d6b0, + 0x57f03d1b, + 0xae21f500, + 0x3311f409, + 0xf5e0c5c7, + 0xf4095321, + 0x57f02911, + 0xae21f500, + 0x1f11f409, + 0xf5e0b5c7, + 0xf4095321, + 0x21f51511, + 0x74bd0846, + 0xf408c5c7, + 0x32f4091b, + 0x030ef402, +/* 0x0b68: i2c_recv_not_wr08 */ +/* 0x0b68: i2c_recv_done */ + 0xf5f8cec7, + 0xfc0a1321, + 0xf4d0fce0, + 0x7cb90a12, + 0x4221f502, +/* 0x0b7d: i2c_recv_exit */ +/* 0x0b7f: i2c_init */ + 0xf800f803, +/* 0x0b81: test_recv */ + 0xd817f100, + 0x0614b605, + 0xb60011cf, + 0x07f10110, + 0x04b605d8, + 0x0001d006, + 0xe7f104bd, + 0xe3f1d900, + 0x21f5134f, + 0x00f80262, +/* 0x0ba8: test_init */ + 0x0800e7f1, + 0x026221f5, +/* 0x0bb2: idle_recv */ 0x00f800f8, -/* 0x0984: test_recv */ - 0x05d817f1, - 0xcf0614b6, - 0x10b60011, - 0xd807f101, - 0x0604b605, - 0xbd0001d0, - 0x00e7f104, - 0x4fe3f1d9, - 0xf521f513, -/* 0x09ab: test_init */ - 0xf100f801, - 0xf50800e7, - 0xf801f521, -/* 0x09b5: idle_recv */ -/* 0x09b7: idle */ - 0xf400f800, - 0x17f10031, - 0x14b605d4, - 0x0011cf06, - 0xf10110b6, - 0xb605d407, - 0x01d00604, -/* 0x09d3: idle_loop */ - 0xf004bd00, - 0x32f45817, -/* 0x09d9: idle_proc */ -/* 0x09d9: idle_proc_exec */ - 0xb910f902, - 0x21f5021e, - 0x10fc02c2, - 0xf40911f4, - 0x0ef40231, -/* 0x09ed: idle_proc_next */ - 0x5810b6ef, - 0xf4061fb8, - 0x02f4e61b, - 0x0028f4dd, - 0x00bb0ef4, +/* 0x0bb4: idle */ + 0xf10031f4, + 0xb605d417, + 0x11cf0614, + 0x0110b600, + 0x05d407f1, + 0xd00604b6, + 0x04bd0001, +/* 0x0bd0: idle_loop */ + 0xf45817f0, +/* 0x0bd6: idle_proc */ +/* 0x0bd6: idle_proc_exec */ + 0x10f90232, + 0xf5021eb9, + 0xfc034b21, + 0x0911f410, + 0xf40231f4, +/* 0x0bea: idle_proc_next */ + 0x10b6ef0e, + 0x061fb858, + 0xf4e61bf4, + 0x28f4dd02, + 0xbb0ef400, + 0x00000000, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc index 8a89dfe41ce1..b85443261569 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc @@ -23,6 +23,7 @@ */ #define NVKM_PPWR_CHIPSET GF119 +#define HW_TICKS_PER_US 324 //#define NVKM_FALCON_PC24 #define NVKM_FALCON_UNSHIFTED_IO @@ -34,6 +35,7 @@ .section #nvd0_pwr_data #define INCLUDE_PROC #include "kernel.fuc" +#include "arith.fuc" #include "host.fuc" #include "memx.fuc" #include "perf.fuc" @@ -44,6 +46,7 @@ #define INCLUDE_DATA #include "kernel.fuc" +#include "arith.fuc" #include "host.fuc" #include "memx.fuc" #include "perf.fuc" @@ -56,6 +59,7 @@ .section #nvd0_pwr_code #define INCLUDE_CODE #include "kernel.fuc" +#include "arith.fuc" #include "host.fuc" #include "memx.fuc" #include "perf.fuc" diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h index cd9ff1a73284..12d86f72ad10 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h @@ -24,8 +24,8 @@ uint32_t nvd0_pwr_data[] = { 0x00000000, /* 0x0058: proc_list_head */ 0x54534f48, - 0x000003be, - 0x00000367, + 0x0000049d, + 0x00000446, 0x00000000, 0x00000000, 0x00000000, @@ -46,8 +46,8 @@ uint32_t nvd0_pwr_data[] = { 0x00000000, 0x00000000, 0x584d454d, - 0x000004c4, - 0x000004b6, + 0x00000678, + 0x0000066a, 0x00000000, 0x00000000, 0x00000000, @@ -68,8 +68,8 @@ uint32_t nvd0_pwr_data[] = { 0x00000000, 0x00000000, 0x46524550, - 0x000004c8, - 0x000004c6, + 0x0000067c, + 0x0000067a, 0x00000000, 0x00000000, 0x00000000, @@ -90,8 +90,8 @@ uint32_t nvd0_pwr_data[] = { 0x00000000, 0x00000000, 0x5f433249, - 0x000008e3, - 0x00000786, + 0x00000a97, + 0x0000093a, 0x00000000, 0x00000000, 0x00000000, @@ -112,8 +112,8 @@ uint32_t nvd0_pwr_data[] = { 0x00000000, 0x00000000, 0x54534554, - 0x00000906, - 0x000008e5, + 0x00000aba, + 0x00000a99, 0x00000000, 0x00000000, 0x00000000, @@ -134,8 +134,8 @@ uint32_t nvd0_pwr_data[] = { 0x00000000, 0x00000000, 0x454c4449, - 0x00000912, - 0x00000910, + 0x00000ac6, + 0x00000ac4, 0x00000000, 0x00000000, 0x00000000, @@ -227,24 +227,31 @@ uint32_t nvd0_pwr_data[] = { 0x00000000, 0x00000000, /* 0x0370: memx_func_head */ - 0x00010000, - 0x00000000, - 0x000003f4, -/* 0x037c: memx_func_next */ 0x00000001, 0x00000000, - 0x00000415, + 0x000004d3, +/* 0x037c: memx_func_next */ 0x00000002, + 0x00000000, + 0x00000554, + 0x00000003, 0x00000002, - 0x00000430, - 0x00040003, + 0x000005d8, + 0x00040004, + 0x00000000, + 0x000005f4, + 0x00010005, + 0x00000000, + 0x0000060e, + 0x00010006, + 0x00000000, + 0x000005d3, +/* 0x03b8: memx_func_tail */ +/* 0x03b8: memx_ts_start */ 0x00000000, - 0x00000458, - 0x00010004, +/* 0x03bc: memx_ts_end */ 0x00000000, - 0x00000472, -/* 0x03ac: memx_func_tail */ -/* 0x03ac: memx_data_head */ +/* 0x03c0: memx_data_head */ 0x00000000, 0x00000000, 0x00000000, @@ -757,8 +764,8 @@ uint32_t nvd0_pwr_data[] = { 0x00000000, 0x00000000, 0x00000000, -/* 0x0bac: memx_data_tail */ -/* 0x0bac: i2c_scl_map */ +/* 0x0bc0: memx_data_tail */ +/* 0x0bc0: i2c_scl_map */ 0x00000400, 0x00000800, 0x00001000, @@ -769,7 +776,7 @@ uint32_t nvd0_pwr_data[] = { 0x00020000, 0x00040000, 0x00080000, -/* 0x0bd4: i2c_sda_map */ +/* 0x0be8: i2c_sda_map */ 0x00100000, 0x00200000, 0x00400000, @@ -781,10 +788,69 @@ uint32_t nvd0_pwr_data[] = { 0x10000000, 0x20000000, 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, }; uint32_t nvd0_pwr_code[] = { - 0x02bf0ef5, + 0x034d0ef5, /* 0x0004: rd32 */ 0x07a007f1, 0xbd000ed0, @@ -814,17 +880,20 @@ uint32_t nvd0_pwr_code[] = { 0xd4f100dd, 0x1bf47000, /* 0x0067: nsec */ - 0xf000f8f5, + 0xf900f8f5, + 0xf080f990, 0x88cf2c87, -/* 0x006d: nsec_loop */ +/* 0x0071: nsec_loop */ 0x2c97f000, 0xbb0099cf, 0x9eb80298, 0xf41ef406, -/* 0x007e: wait */ - 0x87f000f8, + 0x90fc80fc, +/* 0x0086: wait */ + 0x90f900f8, + 0x87f080f9, 0x0088cf2c, -/* 0x0084: wait_loop */ +/* 0x0090: wait_loop */ 0xf402eeb9, 0xdab90421, 0x04adfd02, @@ -833,28 +902,29 @@ uint32_t nvd0_pwr_code[] = { 0x0099cf2c, 0xb80298bb, 0x1ef4069b, -/* 0x00a5: wait_done */ -/* 0x00a7: intr_watchdog */ - 0x9800f8e2, +/* 0x00b1: wait_done */ + 0xfc80fce2, +/* 0x00b7: intr_watchdog */ + 0x9800f890, 0x96b003e9, 0x2a0bf400, 0xbb9a0a98, 0x1cf4029a, 0x01d7f00f, - 0x020621f5, + 0x028c21f5, 0x0ef494bd, -/* 0x00c5: intr_watchdog_next_time */ +/* 0x00d5: intr_watchdog_next_time */ 0x9b0a9815, 0xf400a6b0, 0x9ab8090b, 0x061cf406, -/* 0x00d4: intr_watchdog_next_time_set */ -/* 0x00d7: intr_watchdog_next_proc */ +/* 0x00e4: intr_watchdog_next_time_set */ +/* 0x00e7: intr_watchdog_next_proc */ 0x809b0980, 0xe0b603e9, 0x68e6b158, 0xc61bf402, -/* 0x00e6: intr */ +/* 0x00f6: intr */ 0x00f900f8, 0x80f904bd, 0xa0f990f9, @@ -872,12 +942,12 @@ uint32_t nvd0_pwr_code[] = { 0x0bf40289, 0x9b008020, 0xf458e7f0, - 0x0998a721, + 0x0998b721, 0x0096b09b, 0xf00e0bf4, 0x09d03407, 0x8004bd00, -/* 0x013e: intr_skip_watchdog */ +/* 0x014e: intr_skip_watchdog */ 0x89e49a09, 0x0bf40800, 0x8897f13c, @@ -889,20 +959,20 @@ uint32_t nvd0_pwr_code[] = { 0xf14f48e7, 0xf05453e3, 0x21f500d7, - 0xc0fc026b, + 0xc0fc02f1, 0x04c007f1, 0xbd000cd0, -/* 0x0175: intr_subintr_skip_fifo */ +/* 0x0185: intr_subintr_skip_fifo */ 0x8807f104, 0x0009d006, -/* 0x017e: intr_skip_subintr */ +/* 0x018e: intr_skip_subintr */ 0x89c404bd, 0x070bf420, 0xffbfa4f1, -/* 0x0188: intr_skip_pause */ +/* 0x0198: intr_skip_pause */ 0xf44089c4, 0xa4f1070b, -/* 0x0192: intr_skip_user0 */ +/* 0x01a2: intr_skip_user0 */ 0x07f0ffbf, 0x0008d004, 0x80fc04bd, @@ -912,324 +982,436 @@ uint32_t nvd0_pwr_code[] = { 0xfca0fcb0, 0xfc80fc90, 0x0032f400, -/* 0x01b6: timer */ - 0x32f401f8, - 0x03f89810, - 0xf40086b0, - 0xfe80421c, - 0x3807f003, +/* 0x01c6: ticks_from_ns */ + 0xc0f901f8, + 0xd7f1b0f9, + 0xd3f00144, + 0xb321f500, + 0xe8ccec03, + 0x00b4b003, + 0xec120bf4, + 0xf103e8ee, + 0xf00144d7, + 0x21f500d3, +/* 0x01ee: ticks_from_ns_quit */ + 0xceb903b3, + 0xfcb0fc02, +/* 0x01f7: ticks_from_us */ + 0xf900f8c0, + 0xf1b0f9c0, + 0xf00144d7, + 0x21f500d3, + 0xceb903b3, + 0x00b4b002, + 0xbd050bf4, +/* 0x0211: ticks_from_us_quit */ + 0xfcb0fce4, +/* 0x0217: ticks_to_us */ + 0xf100f8c0, + 0xf00144d7, + 0xedff00d3, +/* 0x0223: timer */ + 0xf900f8ec, + 0xf480f990, + 0xf8981032, + 0x0086b003, + 0xbd531cf4, + 0x3807f084, 0xbd0008d0, - 0x0887f004, - 0xf00088cf, - 0x1bf40284, - 0x3487f020, - 0xb80088cf, - 0x0bf406e0, - 0x06e8b809, -/* 0x01eb: timer_reset */ - 0xf0191ef4, - 0x0ed03407, - 0x8004bd00, -/* 0x01f6: timer_enable */ - 0x87f09a0e, - 0x3807f001, - 0xbd0008d0, -/* 0x0201: timer_done */ - 0x1031f404, -/* 0x0206: send_proc */ - 0x80f900f8, - 0xe89890f9, + 0x3487f004, + 0x980088cf, + 0x98bb9a09, + 0x00e9bb02, + 0xf003fe80, + 0x88cf0887, + 0x0284f000, + 0xf0201bf4, + 0x88cf3487, + 0x06e0b800, + 0xb8090bf4, + 0x1cf406e8, +/* 0x026d: timer_reset */ + 0x3407f00e, + 0xbd000ed0, + 0x9a0e8004, +/* 0x0278: timer_enable */ + 0xf00187f0, + 0x08d03807, +/* 0x0283: timer_done */ + 0xf404bd00, + 0x80fc1031, + 0x00f890fc, +/* 0x028c: send_proc */ + 0x90f980f9, + 0x9805e898, + 0x86f004e9, + 0x0689b804, + 0xc42a0bf4, + 0x88940398, + 0x1880b604, + 0x98008ebb, + 0x8a8000fa, + 0x018d8000, + 0x80028c80, + 0x90b6038b, + 0x0794f001, + 0xf404e980, +/* 0x02c6: send_done */ + 0x90fc0231, + 0x00f880fc, +/* 0x02cc: find */ + 0x87f080f9, + 0x0131f458, +/* 0x02d4: find_loop */ + 0xb8008a98, + 0x0bf406ae, + 0x5880b610, + 0x026886b1, + 0xf4f01bf4, +/* 0x02ea: find_done */ + 0x8eb90132, + 0xf880fc02, +/* 0x02f1: send */ + 0xcc21f500, + 0x9701f402, +/* 0x02fa: recv */ + 0x90f900f8, + 0xe89880f9, 0x04e99805, - 0xb80486f0, + 0xb80132f4, 0x0bf40689, - 0x0398c42a, - 0xb6048894, - 0x8ebb1880, - 0x00fa9800, - 0x80008a80, - 0x8c80018d, - 0x038b8002, - 0xf00190b6, - 0xe9800794, - 0x0231f404, -/* 0x0240: send_done */ - 0x80fc90fc, -/* 0x0246: find */ - 0x80f900f8, - 0xf45887f0, -/* 0x024e: find_loop */ - 0x8a980131, - 0x06aeb800, - 0xb6100bf4, - 0x86b15880, - 0x1bf40268, - 0x0132f4f0, -/* 0x0264: find_done */ - 0xfc028eb9, -/* 0x026b: send */ - 0xf500f880, - 0xf4024621, - 0x00f89701, -/* 0x0274: recv */ - 0x9805e898, - 0x32f404e9, - 0x0689b801, - 0xc43d0bf4, - 0x80b60389, - 0x0784f001, - 0x9805e880, - 0xf0f902ea, - 0xf9018ffe, - 0x02efb9f0, - 0xbb049994, - 0xe0b600e9, - 0x03eb9818, - 0x9802ec98, - 0xee9801ed, - 0xfca5f900, - 0x00f8fef0, - 0xfc0131f4, -/* 0x02bd: recv_done */ -/* 0x02bf: init */ - 0xf100f8f0, - 0xcf010817, - 0x11e70011, - 0x14b60109, - 0x0014fe08, - 0x00e017f1, - 0xf00013f0, - 0x01d01c07, - 0xf004bd00, - 0x07f0ff17, - 0x0001d014, - 0x17f004bd, - 0x0015f102, - 0x1007f008, - 0xbd0001d0, - 0xe617f104, - 0x0013f000, - 0xf40010fe, - 0x17f01031, - 0x3807f001, - 0xbd0001d0, - 0x58f7f004, -/* 0x0314: init_proc */ - 0xb001f198, - 0x0bf40016, - 0xb615f9fa, - 0x0ef458f0, -/* 0x0325: host_send */ - 0xb017f1f2, - 0x0011cf04, - 0x04a027f1, - 0xb80022cf, - 0x0bf40612, - 0x071ec42f, - 0xb704ee94, - 0x980270e0, + 0x0389c43d, + 0xf00180b6, + 0xe8800784, + 0x02ea9805, + 0x8ffef0f9, + 0xb9f0f901, + 0x999402ef, + 0x00e9bb04, + 0x9818e0b6, 0xec9803eb, 0x01ed9802, - 0xf500ee98, - 0xb6026b21, - 0x1ec40110, - 0xb007f10f, - 0x000ed004, - 0x0ef404bd, -/* 0x0365: host_send_done */ -/* 0x0367: host_recv */ - 0xf100f8c3, - 0xf14e4917, - 0xb8525413, - 0x0bf406e1, -/* 0x0375: host_recv_wait */ - 0xcc17f1b3, - 0x0011cf04, - 0x04c827f1, - 0xf00022cf, - 0x12b80816, - 0xec0bf406, - 0xb60723c4, - 0x30b70434, - 0x3b8002f0, - 0x023c8003, - 0x80013d80, - 0x20b6003e, - 0x0f24f001, - 0x04c807f1, - 0xbd0002d0, - 0x4027f004, - 0xd00007f0, - 0x04bd0002, -/* 0x03be: host_init */ + 0xf900ee98, + 0xfef0fca5, + 0x31f400f8, +/* 0x0347: recv_done */ + 0xfcf0fc01, + 0xf890fc80, +/* 0x034d: init */ + 0x0817f100, + 0x0011cf01, + 0x010911e7, + 0xfe0814b6, + 0x17f10014, + 0x13f000e0, + 0x1c07f000, + 0xbd0001d0, + 0xff17f004, + 0xd01407f0, + 0x04bd0001, + 0xf10217f0, + 0xf0080015, + 0x01d01007, + 0xf104bd00, + 0xf000f617, + 0x10fe0013, + 0x1031f400, + 0xf00117f0, + 0x01d03807, + 0xf004bd00, +/* 0x03a2: init_proc */ + 0xf19858f7, + 0x0016b001, + 0xf9fa0bf4, + 0x58f0b615, +/* 0x03b3: mulu32_32_64 */ + 0xf9f20ef4, + 0xf920f910, + 0x9540f930, + 0xd29510e1, + 0xbdc4bd10, + 0xc0edffb4, + 0xb9301dff, + 0x34f10234, + 0x34b6ffff, + 0x1045b610, + 0xbb00c3bb, + 0xe2ff01b4, + 0x0234b930, + 0xffff34f1, + 0xb61034b6, + 0xc3bb1045, + 0x01b4bb00, + 0xbb3012ff, + 0x40fc00b3, + 0x20fc30fc, + 0x00f810fc, +/* 0x0404: host_send */ + 0x04b017f1, + 0xf10011cf, + 0xcf04a027, + 0x12b80022, + 0x2f0bf406, + 0x94071ec4, + 0xe0b704ee, + 0xeb980270, + 0x02ec9803, + 0x9801ed98, + 0x21f500ee, + 0x10b602f1, + 0x0f1ec401, + 0x04b007f1, + 0xbd000ed0, + 0xc30ef404, +/* 0x0444: host_send_done */ +/* 0x0446: host_recv */ 0x17f100f8, - 0x14b60080, - 0x7015f110, - 0xd007f102, - 0x0001d004, - 0x17f104bd, - 0x14b60080, - 0xf015f110, - 0xdc07f102, - 0x0001d004, - 0x17f004bd, - 0xc407f101, - 0x0001d004, - 0x00f804bd, -/* 0x03f4: memx_func_enter */ + 0x13f14e49, + 0xe1b85254, + 0xb30bf406, +/* 0x0454: host_recv_wait */ + 0x04cc17f1, + 0xf10011cf, + 0xcf04c827, + 0x16f00022, + 0x0612b808, + 0xc4ec0bf4, + 0x34b60723, + 0xf030b704, + 0x033b8002, + 0x80023c80, + 0x3e80013d, + 0x0120b600, + 0xf10f24f0, + 0xd004c807, + 0x04bd0002, + 0xf04027f0, + 0x02d00007, + 0xf804bd00, +/* 0x049d: host_init */ + 0x8017f100, + 0x1014b600, + 0x027015f1, + 0x04d007f1, + 0xbd0001d0, + 0x8017f104, + 0x1014b600, + 0x02f015f1, + 0x04dc07f1, + 0xbd0001d0, + 0x0117f004, + 0x04c407f1, + 0xbd0001d0, +/* 0x04d3: memx_func_enter */ + 0xf100f804, + 0xf1162067, + 0xf1f55d77, + 0xb9ffff73, + 0x21f4026e, + 0x02d8b904, + 0xf90487fd, + 0xfc80f960, + 0xf4e0fcd0, + 0x77f13321, + 0x73f1fffe, + 0x6eb9ffff, + 0x0421f402, + 0xfd02d8b9, + 0x60f90487, + 0xd0fc80f9, + 0x21f4e0fc, + 0xf067f133, + 0x026eb926, + 0xb90421f4, + 0x87fd02d8, + 0xf960f904, + 0xfcd0fc80, + 0x3321f4e0, 0xf10467f0, 0xd007e007, 0x04bd0006, -/* 0x0400: memx_func_enter_wait */ +/* 0x053c: memx_func_enter_wait */ 0x07c067f1, 0xf00066cf, 0x0bf40464, - 0x001698f6, - 0xf80410b6, -/* 0x0415: memx_func_leave */ - 0x0467f000, + 0x2c67f0f6, + 0x800066cf, + 0x00f8ee06, +/* 0x0554: memx_func_leave */ + 0xcf2c67f0, + 0x06800066, + 0x0467f0ef, 0x07e407f1, 0xbd0006d0, -/* 0x0421: memx_func_leave_wait */ +/* 0x0569: memx_func_leave_wait */ 0xc067f104, 0x0066cf07, 0xf40464f0, - 0x00f8f61b, -/* 0x0430: memx_func_wr32 */ + 0x67f1f61b, + 0x77f126f0, + 0x73f00001, + 0x026eb900, + 0xb90421f4, + 0x87fd02d8, + 0xf960f905, + 0xfcd0fc80, + 0x3321f4e0, + 0x162067f1, + 0xf4026eb9, + 0xd8b90421, + 0x0587fd02, + 0x80f960f9, + 0xe0fcd0fc, + 0xf13321f4, + 0xf00aa277, + 0x6eb90073, + 0x0421f402, + 0xfd02d8b9, + 0x60f90587, + 0xd0fc80f9, + 0x21f4e0fc, +/* 0x05d3: memx_func_wait_vblank */ + 0xb600f833, + 0x00f80410, +/* 0x05d8: memx_func_wr32 */ 0x98001698, 0x10b60115, 0xf960f908, 0xfcd0fc50, 0x3321f4e0, - 0x140003f1, - 0x800506fd, - 0x04bd0005, 0xf40242b6, - 0x00f8dd1b, -/* 0x0458: memx_func_wait */ + 0x00f8e91b, +/* 0x05f4: memx_func_wait */ 0xcf2c87f0, 0x1e980088, 0x011d9800, 0x98021c98, 0x10b6031b, - 0x7e21f410, -/* 0x0472: memx_func_delay */ + 0x8621f410, +/* 0x060e: memx_func_delay */ 0x1e9800f8, 0x0410b600, 0xf86721f4, -/* 0x047d: memx_exec */ +/* 0x0619: memx_exec */ 0xf9e0f900, 0x02c1b9d0, -/* 0x0487: memx_exec_next */ +/* 0x0623: memx_exec_next */ 0x9802b2b9, 0x10b60013, - 0x10349504, + 0xf034e704, + 0xe033e701, + 0x0132b601, 0x980c30f0, 0x55f9de35, 0xf40612b8, - 0xd0fcec1e, + 0x0b98e41e, + 0xef0c98ee, + 0xf102cbbb, + 0xcf07c4b7, + 0xd0fc00bb, 0x21f5e0fc, - 0x00f8026b, -/* 0x04a8: memx_info */ - 0x03acc7f1, + 0x00f802f1, +/* 0x065c: memx_info */ + 0x03c0c7f1, 0x0800b7f1, - 0x026b21f5, -/* 0x04b6: memx_recv */ + 0x02f121f5, +/* 0x066a: memx_recv */ 0xd6b000f8, - 0xc40bf401, + 0xac0bf401, 0xf400d6b0, 0x00f8e90b, -/* 0x04c4: memx_init */ -/* 0x04c6: perf_recv */ +/* 0x0678: memx_init */ +/* 0x067a: perf_recv */ 0x00f800f8, -/* 0x04c8: perf_init */ -/* 0x04ca: i2c_drive_scl */ +/* 0x067c: perf_init */ +/* 0x067e: i2c_drive_scl */ 0x36b000f8, 0x0e0bf400, 0x07e007f1, 0xbd0001d0, -/* 0x04db: i2c_drive_scl_lo */ +/* 0x068f: i2c_drive_scl_lo */ 0xf100f804, 0xd007e407, 0x04bd0001, -/* 0x04e6: i2c_drive_sda */ +/* 0x069a: i2c_drive_sda */ 0x36b000f8, 0x0e0bf400, 0x07e007f1, 0xbd0002d0, -/* 0x04f7: i2c_drive_sda_lo */ +/* 0x06ab: i2c_drive_sda_lo */ 0xf100f804, 0xd007e407, 0x04bd0002, -/* 0x0502: i2c_sense_scl */ +/* 0x06b6: i2c_sense_scl */ 0x32f400f8, 0xc437f101, 0x0033cf07, 0xf40431fd, 0x31f4060b, -/* 0x0515: i2c_sense_scl_done */ -/* 0x0517: i2c_sense_sda */ +/* 0x06c9: i2c_sense_scl_done */ +/* 0x06cb: i2c_sense_sda */ 0xf400f801, 0x37f10132, 0x33cf07c4, 0x0432fd00, 0xf4060bf4, -/* 0x052a: i2c_sense_sda_done */ +/* 0x06de: i2c_sense_sda_done */ 0x00f80131, -/* 0x052c: i2c_raise_scl */ +/* 0x06e0: i2c_raise_scl */ 0x47f140f9, 0x37f00898, - 0xca21f501, -/* 0x0539: i2c_raise_scl_wait */ - 0xe8e7f104, + 0x7e21f501, +/* 0x06ed: i2c_raise_scl_wait */ + 0xe8e7f106, 0x6721f403, - 0x050221f5, + 0x06b621f5, 0xb60901f4, 0x1bf40142, -/* 0x054d: i2c_raise_scl_done */ +/* 0x0701: i2c_raise_scl_done */ 0xf840fcef, -/* 0x0551: i2c_start */ - 0x0221f500, - 0x0d11f405, - 0x051721f5, +/* 0x0705: i2c_start */ + 0xb621f500, + 0x0d11f406, + 0x06cb21f5, 0xf40611f4, -/* 0x0562: i2c_start_rep */ +/* 0x0716: i2c_start_rep */ 0x37f0300e, - 0xca21f500, - 0x0137f004, - 0x04e621f5, + 0x7e21f500, + 0x0137f006, + 0x069a21f5, 0xb60076bb, 0x50f90465, 0xbb046594, 0x50bd0256, 0xfc0475fd, - 0x2c21f550, - 0x0464b605, -/* 0x058f: i2c_start_send */ + 0xe021f550, + 0x0464b606, +/* 0x0743: i2c_start_send */ 0xf01f11f4, 0x21f50037, - 0xe7f104e6, + 0xe7f1069a, 0x21f41388, 0x0037f067, - 0x04ca21f5, + 0x067e21f5, 0x1388e7f1, -/* 0x05ab: i2c_start_out */ +/* 0x075f: i2c_start_out */ 0xf86721f4, -/* 0x05ad: i2c_stop */ +/* 0x0761: i2c_stop */ 0x0037f000, - 0x04ca21f5, + 0x067e21f5, 0xf50037f0, - 0xf104e621, + 0xf1069a21, 0xf403e8e7, 0x37f06721, - 0xca21f501, - 0x88e7f104, + 0x7e21f501, + 0x88e7f106, 0x6721f413, 0xf50137f0, - 0xf104e621, + 0xf1069a21, 0xf41388e7, 0x00f86721, -/* 0x05e0: i2c_bitw */ - 0x04e621f5, +/* 0x0794: i2c_bitw */ + 0x069a21f5, 0x03e8e7f1, 0xbb6721f4, 0x65b60076, @@ -1237,18 +1419,18 @@ uint32_t nvd0_pwr_code[] = { 0x56bb0465, 0xfd50bd02, 0x50fc0475, - 0x052c21f5, + 0x06e021f5, 0xf40464b6, 0xe7f11811, 0x21f41388, 0x0037f067, - 0x04ca21f5, + 0x067e21f5, 0x1388e7f1, -/* 0x061f: i2c_bitw_out */ +/* 0x07d3: i2c_bitw_out */ 0xf86721f4, -/* 0x0621: i2c_bitr */ +/* 0x07d5: i2c_bitr */ 0x0137f000, - 0x04e621f5, + 0x069a21f5, 0x03e8e7f1, 0xbb6721f4, 0x65b60076, @@ -1256,19 +1438,19 @@ uint32_t nvd0_pwr_code[] = { 0x56bb0465, 0xfd50bd02, 0x50fc0475, - 0x052c21f5, + 0x06e021f5, 0xf40464b6, 0x21f51b11, - 0x37f00517, - 0xca21f500, - 0x88e7f104, + 0x37f006cb, + 0x7e21f500, + 0x88e7f106, 0x6721f413, 0xf4013cf0, -/* 0x0666: i2c_bitr_done */ +/* 0x081a: i2c_bitr_done */ 0x00f80131, -/* 0x0668: i2c_get_byte */ +/* 0x081c: i2c_get_byte */ 0xf00057f0, -/* 0x066e: i2c_get_byte_next */ +/* 0x0822: i2c_get_byte_next */ 0x54b60847, 0x0076bb01, 0xf90465b6, @@ -1276,7 +1458,7 @@ uint32_t nvd0_pwr_code[] = { 0xbd0256bb, 0x0475fd50, 0x21f550fc, - 0x64b60621, + 0x64b607d5, 0x2b11f404, 0xb60553fd, 0x1bf40142, @@ -1286,12 +1468,12 @@ uint32_t nvd0_pwr_code[] = { 0xbb046594, 0x50bd0256, 0xfc0475fd, - 0xe021f550, - 0x0464b605, -/* 0x06b8: i2c_get_byte_done */ -/* 0x06ba: i2c_put_byte */ + 0x9421f550, + 0x0464b607, +/* 0x086c: i2c_get_byte_done */ +/* 0x086e: i2c_put_byte */ 0x47f000f8, -/* 0x06bd: i2c_put_byte_next */ +/* 0x0871: i2c_put_byte_next */ 0x0142b608, 0xbb3854ff, 0x65b60076, @@ -1299,7 +1481,7 @@ uint32_t nvd0_pwr_code[] = { 0x56bb0465, 0xfd50bd02, 0x50fc0475, - 0x05e021f5, + 0x079421f5, 0xf40464b6, 0x46b03411, 0xd81bf400, @@ -1308,21 +1490,21 @@ uint32_t nvd0_pwr_code[] = { 0xbb046594, 0x50bd0256, 0xfc0475fd, - 0x2121f550, - 0x0464b606, + 0xd521f550, + 0x0464b607, 0xbb0f11f4, 0x36b00076, 0x061bf401, -/* 0x0713: i2c_put_byte_done */ +/* 0x08c7: i2c_put_byte_done */ 0xf80132f4, -/* 0x0715: i2c_addr */ +/* 0x08c9: i2c_addr */ 0x0076bb00, 0xf90465b6, 0x04659450, 0xbd0256bb, 0x0475fd50, 0x21f550fc, - 0x64b60551, + 0x64b60705, 0x2911f404, 0x012ec3e7, 0xfd0134b6, @@ -1332,30 +1514,30 @@ uint32_t nvd0_pwr_code[] = { 0x0256bb04, 0x75fd50bd, 0xf550fc04, - 0xb606ba21, -/* 0x075a: i2c_addr_done */ + 0xb6086e21, +/* 0x090e: i2c_addr_done */ 0x00f80464, -/* 0x075c: i2c_acquire_addr */ +/* 0x0910: i2c_acquire_addr */ 0xb6f8cec7, 0xe0b705e4, 0x00f8d014, -/* 0x0768: i2c_acquire */ - 0x075c21f5, +/* 0x091c: i2c_acquire */ + 0x091021f5, 0xf00421f4, 0x21f403d9, -/* 0x0777: i2c_release */ +/* 0x092b: i2c_release */ 0xf500f833, - 0xf4075c21, + 0xf4091021, 0xdaf00421, 0x3321f403, -/* 0x0786: i2c_recv */ +/* 0x093a: i2c_recv */ 0x32f400f8, 0xf8c1c701, 0xb00214b6, 0x1ff52816, 0x13a0013a, - 0x32980bd4, - 0xac13a000, + 0x32980be8, + 0xc013a000, 0x0031980b, 0xf90231f4, 0xf9e0f9d0, @@ -1367,8 +1549,8 @@ uint32_t nvd0_pwr_code[] = { 0xbb046594, 0x50bd0256, 0xfc0475fd, - 0x6821f550, - 0x0464b607, + 0x1c21f550, + 0x0464b609, 0xd6b0d0fc, 0xb31bf500, 0x0057f000, @@ -1377,8 +1559,8 @@ uint32_t nvd0_pwr_code[] = { 0xbb046594, 0x50bd0256, 0xfc0475fd, - 0x1521f550, - 0x0464b607, + 0xc921f550, + 0x0464b608, 0x00d011f5, 0xbbe0c5c7, 0x65b60076, @@ -1386,7 +1568,7 @@ uint32_t nvd0_pwr_code[] = { 0x56bb0465, 0xfd50bd02, 0x50fc0475, - 0x06ba21f5, + 0x086e21f5, 0xf50464b6, 0xf000ad11, 0x76bb0157, @@ -1395,7 +1577,7 @@ uint32_t nvd0_pwr_code[] = { 0x0256bb04, 0x75fd50bd, 0xf550fc04, - 0xb6071521, + 0xb608c921, 0x11f50464, 0x76bb008a, 0x0465b600, @@ -1403,7 +1585,7 @@ uint32_t nvd0_pwr_code[] = { 0x0256bb04, 0x75fd50bd, 0xf550fc04, - 0xb6066821, + 0xb6081c21, 0x11f40464, 0xe05bcb6a, 0xb60076bb, @@ -1411,38 +1593,38 @@ uint32_t nvd0_pwr_code[] = { 0xbb046594, 0x50bd0256, 0xfc0475fd, - 0xad21f550, - 0x0464b605, + 0x6121f550, + 0x0464b607, 0xbd025bb9, 0x430ef474, -/* 0x088c: i2c_recv_not_rd08 */ +/* 0x0a40: i2c_recv_not_rd08 */ 0xf401d6b0, 0x57f03d1b, - 0x1521f500, - 0x3311f407, + 0xc921f500, + 0x3311f408, 0xf5e0c5c7, - 0xf406ba21, + 0xf4086e21, 0x57f02911, - 0x1521f500, - 0x1f11f407, + 0xc921f500, + 0x1f11f408, 0xf5e0b5c7, - 0xf406ba21, + 0xf4086e21, 0x21f51511, - 0x74bd05ad, + 0x74bd0761, 0xf408c5c7, 0x32f4091b, 0x030ef402, -/* 0x08cc: i2c_recv_not_wr08 */ -/* 0x08cc: i2c_recv_done */ +/* 0x0a80: i2c_recv_not_wr08 */ +/* 0x0a80: i2c_recv_done */ 0xf5f8cec7, - 0xfc077721, + 0xfc092b21, 0xf4d0fce0, 0x7cb90a12, - 0x6b21f502, -/* 0x08e1: i2c_recv_exit */ -/* 0x08e3: i2c_init */ + 0xf121f502, +/* 0x0a95: i2c_recv_exit */ +/* 0x0a97: i2c_init */ 0xf800f802, -/* 0x08e5: test_recv */ +/* 0x0a99: test_recv */ 0xd817f100, 0x0011cf05, 0xf10110b6, @@ -1450,29 +1632,29 @@ uint32_t nvd0_pwr_code[] = { 0x04bd0001, 0xd900e7f1, 0x134fe3f1, - 0x01b621f5, -/* 0x0906: test_init */ + 0x022321f5, +/* 0x0aba: test_init */ 0xe7f100f8, 0x21f50800, - 0x00f801b6, -/* 0x0910: idle_recv */ -/* 0x0912: idle */ + 0x00f80223, +/* 0x0ac4: idle_recv */ +/* 0x0ac6: idle */ 0x31f400f8, 0xd417f100, 0x0011cf05, 0xf10110b6, 0xd005d407, 0x04bd0001, -/* 0x0928: idle_loop */ +/* 0x0adc: idle_loop */ 0xf45817f0, -/* 0x092e: idle_proc */ -/* 0x092e: idle_proc_exec */ +/* 0x0ae2: idle_proc */ +/* 0x0ae2: idle_proc_exec */ 0x10f90232, 0xf5021eb9, - 0xfc027421, + 0xfc02fa21, 0x0911f410, 0xf40231f4, -/* 0x0942: idle_proc_next */ +/* 0x0af6: idle_proc_next */ 0x10b6ef0e, 0x061fb858, 0xf4e61bf4, @@ -1521,4 +1703,23 @@ uint32_t nvd0_pwr_code[] = { 0x00000000, 0x00000000, 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h index 574acfa44c8c..522e3079f824 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h @@ -19,11 +19,12 @@ #define MEMX_MSG_EXEC 1 /* MEMX: script opcode definitions */ -#define MEMX_ENTER 0 -#define MEMX_LEAVE 1 -#define MEMX_WR32 2 -#define MEMX_WAIT 3 -#define MEMX_DELAY 4 +#define MEMX_ENTER 1 +#define MEMX_LEAVE 2 +#define MEMX_WR32 3 +#define MEMX_WAIT 4 +#define MEMX_DELAY 5 +#define MEMX_VBLANK 6 /* I2C_: message identifiers */ #define I2C__MSG_RD08 0 diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/gk104.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/gk104.c new file mode 100644 index 000000000000..d76612999b9f --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/gk104.c @@ -0,0 +1,69 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "priv.h" + +#define nvd0_pwr_code gk104_pwr_code +#define nvd0_pwr_data gk104_pwr_data +#include "fuc/nvd0.fuc.h" + +static void +gk104_pwr_pgob(struct nouveau_pwr *ppwr, bool enable) +{ + nv_mask(ppwr, 0x000200, 0x00001000, 0x00000000); + nv_rd32(ppwr, 0x000200); + nv_mask(ppwr, 0x000200, 0x08000000, 0x08000000); + msleep(50); + + nv_mask(ppwr, 0x10a78c, 0x00000002, 0x00000002); + nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000001); + nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000000); + + nv_mask(ppwr, 0x020004, 0xc0000000, enable ? 0xc0000000 : 0x40000000); + msleep(50); + + nv_mask(ppwr, 0x10a78c, 0x00000002, 0x00000000); + nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000001); + nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000000); + + nv_mask(ppwr, 0x000200, 0x08000000, 0x00000000); + nv_mask(ppwr, 0x000200, 0x00001000, 0x00001000); + nv_rd32(ppwr, 0x000200); +} + +struct nouveau_oclass * +gk104_pwr_oclass = &(struct nvkm_pwr_impl) { + .base.handle = NV_SUBDEV(PWR, 0xe4), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = _nouveau_pwr_ctor, + .dtor = _nouveau_pwr_dtor, + .init = _nouveau_pwr_init, + .fini = _nouveau_pwr_fini, + }, + .code.data = gk104_pwr_code, + .code.size = sizeof(gk104_pwr_code), + .data.data = gk104_pwr_data, + .data.size = sizeof(gk104_pwr_data), + .pgob = gk104_pwr_pgob, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c index 03de3107d29f..65eaa2546cad 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c @@ -1,8 +1,7 @@ #ifndef __NVKM_PWR_MEMX_H__ #define __NVKM_PWR_MEMX_H__ -#include <subdev/pwr.h> -#include <subdev/pwr/fuc/os.h> +#include "priv.h" struct nouveau_memx { struct nouveau_pwr *ppwr; @@ -21,10 +20,11 @@ memx_out(struct nouveau_memx *memx) struct nouveau_pwr *ppwr = memx->ppwr; int i; - if (memx->c.size) { + if (memx->c.mthd) { nv_wr32(ppwr, 0x10a1c4, (memx->c.size << 16) | memx->c.mthd); for (i = 0; i < memx->c.size; i++) nv_wr32(ppwr, 0x10a1c4, memx->c.data[i]); + memx->c.mthd = 0; memx->c.size = 0; } } @@ -33,7 +33,7 @@ static void memx_cmd(struct nouveau_memx *memx, u32 mthd, u32 size, u32 data[]) { if ((memx->c.size + size >= ARRAY_SIZE(memx->c.data)) || - (memx->c.size && memx->c.mthd != mthd)) + (memx->c.mthd && memx->c.mthd != mthd)) memx_out(memx); memcpy(&memx->c.data[memx->c.size], data, size * sizeof(data[0])); memx->c.size += size; @@ -63,8 +63,7 @@ nouveau_memx_init(struct nouveau_pwr *ppwr, struct nouveau_memx **pmemx) nv_wr32(ppwr, 0x10a580, 0x00000003); } while (nv_rd32(ppwr, 0x10a580) != 0x00000003); nv_wr32(ppwr, 0x10a1c0, 0x01000000 | memx->base); - nv_wr32(ppwr, 0x10a1c4, 0x00010000 | MEMX_ENTER); - nv_wr32(ppwr, 0x10a1c4, 0x00000000); + return 0; } @@ -79,7 +78,6 @@ nouveau_memx_fini(struct nouveau_memx **pmemx, bool exec) memx_out(memx); /* release data segment access */ - nv_wr32(ppwr, 0x10a1c4, 0x00000000 | MEMX_LEAVE); finish = nv_rd32(ppwr, 0x10a1c0) & 0x00ffffff; nv_wr32(ppwr, 0x10a580, 0x00000000); @@ -89,6 +87,8 @@ nouveau_memx_fini(struct nouveau_memx **pmemx, bool exec) memx->base, finish); } + nv_debug(memx->ppwr, "Exec took %uns, PPWR_IN %08x\n", + reply[0], reply[1]); kfree(memx); return 0; } @@ -118,4 +118,51 @@ nouveau_memx_nsec(struct nouveau_memx *memx, u32 nsec) memx_out(memx); /* fuc can't handle multiple */ } +void +nouveau_memx_wait_vblank(struct nouveau_memx *memx) +{ + struct nouveau_pwr *ppwr = memx->ppwr; + u32 heads, x, y, px = 0; + int i, head_sync; + + if (nv_device(ppwr)->chipset < 0xd0) { + heads = nv_rd32(ppwr, 0x610050); + for (i = 0; i < 2; i++) { + /* Heuristic: sync to head with biggest resolution */ + if (heads & (2 << (i << 3))) { + x = nv_rd32(ppwr, 0x610b40 + (0x540 * i)); + y = (x & 0xffff0000) >> 16; + x &= 0x0000ffff; + if ((x * y) > px) { + px = (x * y); + head_sync = i; + } + } + } + } + + if (px == 0) { + nv_debug(memx->ppwr, "WAIT VBLANK !NO ACTIVE HEAD\n"); + return; + } + + nv_debug(memx->ppwr, "WAIT VBLANK HEAD%d\n", head_sync); + memx_cmd(memx, MEMX_VBLANK, 1, (u32[]){ head_sync }); + memx_out(memx); /* fuc can't handle multiple */ +} + +void +nouveau_memx_block(struct nouveau_memx *memx) +{ + nv_debug(memx->ppwr, " HOST BLOCKED\n"); + memx_cmd(memx, MEMX_ENTER, 0, NULL); +} + +void +nouveau_memx_unblock(struct nouveau_memx *memx) +{ + nv_debug(memx->ppwr, " HOST UNBLOCKED\n"); + memx_cmd(memx, MEMX_LEAVE, 0, NULL); +} + #endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c index 52c85414866a..04ff7c3c34e9 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c @@ -22,41 +22,20 @@ * Authors: Ben Skeggs */ -#include <subdev/pwr.h> - +#include "priv.h" #include "fuc/nv108.fuc.h" -struct nv108_pwr_priv { - struct nouveau_pwr base; -}; - -static int -nv108_pwr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv108_pwr_priv *priv; - int ret; - - ret = nouveau_pwr_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - priv->base.code.data = nv108_pwr_code; - priv->base.code.size = sizeof(nv108_pwr_code); - priv->base.data.data = nv108_pwr_data; - priv->base.data.size = sizeof(nv108_pwr_data); - return 0; -} - -struct nouveau_oclass -nv108_pwr_oclass = { - .handle = NV_SUBDEV(PWR, 0x00), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv108_pwr_ctor, +struct nouveau_oclass * +nv108_pwr_oclass = &(struct nvkm_pwr_impl) { + .base.handle = NV_SUBDEV(PWR, 0x00), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = _nouveau_pwr_ctor, .dtor = _nouveau_pwr_dtor, .init = _nouveau_pwr_init, .fini = _nouveau_pwr_fini, }, -}; + .code.data = nv108_pwr_code, + .code.size = sizeof(nv108_pwr_code), + .data.data = nv108_pwr_data, + .data.size = sizeof(nv108_pwr_data), +}.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c index c132b7ca9747..998d53076b8b 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c @@ -22,50 +22,29 @@ * Authors: Ben Skeggs */ -#include <subdev/pwr.h> - +#include "priv.h" #include "fuc/nva3.fuc.h" -struct nva3_pwr_priv { - struct nouveau_pwr base; -}; - static int nva3_pwr_init(struct nouveau_object *object) { - struct nva3_pwr_priv *priv = (void *)object; - nv_mask(priv, 0x022210, 0x00000001, 0x00000000); - nv_mask(priv, 0x022210, 0x00000001, 0x00000001); - return nouveau_pwr_init(&priv->base); -} - -static int -nva3_pwr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nva3_pwr_priv *priv; - int ret; - - ret = nouveau_pwr_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - priv->base.code.data = nva3_pwr_code; - priv->base.code.size = sizeof(nva3_pwr_code); - priv->base.data.data = nva3_pwr_data; - priv->base.data.size = sizeof(nva3_pwr_data); - return 0; + struct nouveau_pwr *ppwr = (void *)object; + nv_mask(ppwr, 0x022210, 0x00000001, 0x00000000); + nv_mask(ppwr, 0x022210, 0x00000001, 0x00000001); + return nouveau_pwr_init(ppwr); } -struct nouveau_oclass -nva3_pwr_oclass = { - .handle = NV_SUBDEV(PWR, 0xa3), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nva3_pwr_ctor, +struct nouveau_oclass * +nva3_pwr_oclass = &(struct nvkm_pwr_impl) { + .base.handle = NV_SUBDEV(PWR, 0xa3), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = _nouveau_pwr_ctor, .dtor = _nouveau_pwr_dtor, .init = nva3_pwr_init, .fini = _nouveau_pwr_fini, }, -}; + .code.data = nva3_pwr_code, + .code.size = sizeof(nva3_pwr_code), + .data.data = nva3_pwr_data, + .data.size = sizeof(nva3_pwr_data), +}.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c index 495f6857428d..9a773e66efa4 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c @@ -22,41 +22,20 @@ * Authors: Ben Skeggs */ -#include <subdev/pwr.h> - +#include "priv.h" #include "fuc/nvc0.fuc.h" -struct nvc0_pwr_priv { - struct nouveau_pwr base; -}; - -static int -nvc0_pwr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nvc0_pwr_priv *priv; - int ret; - - ret = nouveau_pwr_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - priv->base.code.data = nvc0_pwr_code; - priv->base.code.size = sizeof(nvc0_pwr_code); - priv->base.data.data = nvc0_pwr_data; - priv->base.data.size = sizeof(nvc0_pwr_data); - return 0; -} - -struct nouveau_oclass -nvc0_pwr_oclass = { - .handle = NV_SUBDEV(PWR, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_pwr_ctor, +struct nouveau_oclass * +nvc0_pwr_oclass = &(struct nvkm_pwr_impl) { + .base.handle = NV_SUBDEV(PWR, 0xc0), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = _nouveau_pwr_ctor, .dtor = _nouveau_pwr_dtor, .init = _nouveau_pwr_init, .fini = _nouveau_pwr_fini, }, -}; + .code.data = nvc0_pwr_code, + .code.size = sizeof(nvc0_pwr_code), + .data.data = nvc0_pwr_data, + .data.size = sizeof(nvc0_pwr_data), +}.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c index 043aa142fe82..2b29be5d08ac 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c @@ -22,41 +22,20 @@ * Authors: Ben Skeggs */ -#include <subdev/pwr.h> - +#include "priv.h" #include "fuc/nvd0.fuc.h" -struct nvd0_pwr_priv { - struct nouveau_pwr base; -}; - -static int -nvd0_pwr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nvd0_pwr_priv *priv; - int ret; - - ret = nouveau_pwr_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - priv->base.code.data = nvd0_pwr_code; - priv->base.code.size = sizeof(nvd0_pwr_code); - priv->base.data.data = nvd0_pwr_data; - priv->base.data.size = sizeof(nvd0_pwr_data); - return 0; -} - -struct nouveau_oclass -nvd0_pwr_oclass = { - .handle = NV_SUBDEV(PWR, 0xd0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvd0_pwr_ctor, +struct nouveau_oclass * +nvd0_pwr_oclass = &(struct nvkm_pwr_impl) { + .base.handle = NV_SUBDEV(PWR, 0xd0), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = _nouveau_pwr_ctor, .dtor = _nouveau_pwr_dtor, .init = _nouveau_pwr_init, .fini = _nouveau_pwr_fini, }, -}; + .code.data = nvd0_pwr_code, + .code.size = sizeof(nvd0_pwr_code), + .data.data = nvd0_pwr_data, + .data.size = sizeof(nvd0_pwr_data), +}.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h new file mode 100644 index 000000000000..3814a341db32 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h @@ -0,0 +1,44 @@ +#ifndef __NVKM_PWR_PRIV_H__ +#define __NVKM_PWR_PRIV_H__ + +#include <subdev/pwr.h> +#include <subdev/pwr/fuc/os.h> + +#define nouveau_pwr_create(p, e, o, d) \ + nouveau_pwr_create_((p), (e), (o), sizeof(**d), (void **)d) +#define nouveau_pwr_destroy(p) \ + nouveau_subdev_destroy(&(p)->base) +#define nouveau_pwr_init(p) ({ \ + struct nouveau_pwr *_ppwr = (p); \ + _nouveau_pwr_init(nv_object(_ppwr)); \ +}) +#define nouveau_pwr_fini(p,s) ({ \ + struct nouveau_pwr *_ppwr = (p); \ + _nouveau_pwr_fini(nv_object(_ppwr), (s)); \ +}) + +int nouveau_pwr_create_(struct nouveau_object *, struct nouveau_object *, + struct nouveau_oclass *, int, void **); + +int _nouveau_pwr_ctor(struct nouveau_object *, struct nouveau_object *, + struct nouveau_oclass *, void *, u32, + struct nouveau_object **); +#define _nouveau_pwr_dtor _nouveau_subdev_dtor +int _nouveau_pwr_init(struct nouveau_object *); +int _nouveau_pwr_fini(struct nouveau_object *, bool); + +struct nvkm_pwr_impl { + struct nouveau_oclass base; + struct { + u32 *data; + u32 size; + } code; + struct { + u32 *data; + u32 size; + } data; + + void (*pgob)(struct nouveau_pwr *, bool); +}; + +#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/fan.c b/drivers/gpu/drm/nouveau/core/subdev/therm/fan.c index 016990a8252c..3656d605168f 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/therm/fan.c +++ b/drivers/gpu/drm/nouveau/core/subdev/therm/fan.c @@ -31,6 +31,8 @@ #include <subdev/gpio.h> #include <subdev/timer.h> +#include <subdev/bios/fan.h> + static int nouveau_fan_update(struct nouveau_fan *fan, bool immediate, int target) { @@ -275,8 +277,11 @@ nouveau_therm_fan_ctor(struct nouveau_therm *therm) /* other random init... */ nouveau_therm_fan_set_defaults(therm); nvbios_perf_fan_parse(bios, &priv->fan->perf); - if (nvbios_therm_fan_parse(bios, &priv->fan->bios)) - nv_error(therm, "parsing the thermal table failed\n"); + if (!nvbios_fan_parse(bios, &priv->fan->bios)) { + nv_debug(therm, "parsing the fan table failed\n"); + if (nvbios_therm_fan_parse(bios, &priv->fan->bios)) + nv_error(therm, "parsing both fan tables failed\n"); + } nouveau_therm_fan_safety_checks(therm); return 0; } diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/fanpwm.c b/drivers/gpu/drm/nouveau/core/subdev/therm/fanpwm.c index 9a5c07340263..c629d7f2a6a4 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/therm/fanpwm.c +++ b/drivers/gpu/drm/nouveau/core/subdev/therm/fanpwm.c @@ -25,6 +25,8 @@ #include <core/option.h> #include <subdev/gpio.h> +#include <subdev/bios.h> +#include <subdev/bios/fan.h> #include "priv.h" @@ -86,11 +88,15 @@ nouveau_fanpwm_create(struct nouveau_therm *therm, struct dcb_gpio_func *func) { struct nouveau_device *device = nv_device(therm); struct nouveau_therm_priv *tpriv = (void *)therm; + struct nouveau_bios *bios = nouveau_bios(therm); struct nouveau_fanpwm_priv *priv; + struct nvbios_therm_fan fan; u32 divs, duty; + nvbios_fan_parse(bios, &fan); + if (!nouveau_boolopt(device->cfgopt, "NvFanPWM", func->param) || - !therm->pwm_ctrl || + !therm->pwm_ctrl || fan.type == NVBIOS_THERM_FAN_TOGGLE || therm->pwm_get(therm, func->line, &divs, &duty) == -ENODEV) return -ENODEV; diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/gm107.c b/drivers/gpu/drm/nouveau/core/subdev/therm/gm107.c new file mode 100644 index 000000000000..668cf3322285 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/therm/gm107.c @@ -0,0 +1,93 @@ +/* + * Copyright 2014 Martin Peres + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Martin Peres + */ + +#include "priv.h" + +struct gm107_therm_priv { + struct nouveau_therm_priv base; +}; + +static int +gm107_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable) +{ + /* nothing to do, it seems hardwired */ + return 0; +} + +static int +gm107_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty) +{ + *divs = nv_rd32(therm, 0x10eb20) & 0x1fff; + *duty = nv_rd32(therm, 0x10eb24) & 0x1fff; + return 0; +} + +static int +gm107_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty) +{ + nv_mask(therm, 0x10eb10, 0x1fff, divs); /* keep the high bits */ + nv_wr32(therm, 0x10eb14, duty | 0x80000000); + return 0; +} + +static int +gm107_fan_pwm_clock(struct nouveau_therm *therm, int line) +{ + return nv_device(therm)->crystal * 1000; +} + +static int +gm107_therm_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct gm107_therm_priv *priv; + int ret; + + ret = nouveau_therm_create(parent, engine, oclass, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + priv->base.base.pwm_ctrl = gm107_fan_pwm_ctrl; + priv->base.base.pwm_get = gm107_fan_pwm_get; + priv->base.base.pwm_set = gm107_fan_pwm_set; + priv->base.base.pwm_clock = gm107_fan_pwm_clock; + priv->base.base.temp_get = nv84_temp_get; + priv->base.base.fan_sense = nva3_therm_fan_sense; + priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling; + return nouveau_therm_preinit(&priv->base.base); +} + +struct nouveau_oclass +gm107_therm_oclass = { + .handle = NV_SUBDEV(THERM, 0x117), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = gm107_therm_ctor, + .dtor = _nouveau_therm_dtor, + .init = nvd0_therm_init, + .fini = nv84_therm_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nv84.c b/drivers/gpu/drm/nouveau/core/subdev/therm/nv84.c index 1d15c52fad0c..14e2e09bfc24 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/therm/nv84.c +++ b/drivers/gpu/drm/nouveau/core/subdev/therm/nv84.c @@ -24,6 +24,7 @@ */ #include "priv.h" +#include <subdev/fuse.h> struct nv84_therm_priv { struct nouveau_therm_priv base; @@ -32,7 +33,25 @@ struct nv84_therm_priv { int nv84_temp_get(struct nouveau_therm *therm) { - return nv_rd32(therm, 0x20400); + struct nouveau_fuse *fuse = nouveau_fuse(therm); + + if (nv_ro32(fuse, 0x1a8) == 1) + return nv_rd32(therm, 0x20400); + else + return -ENODEV; +} + +void +nv84_sensor_setup(struct nouveau_therm *therm) +{ + struct nouveau_fuse *fuse = nouveau_fuse(therm); + + /* enable temperature reading for cards with insane defaults */ + if (nv_ro32(fuse, 0x1a8) == 1) { + nv_mask(therm, 0x20008, 0x80008000, 0x80000000); + nv_mask(therm, 0x2000c, 0x80000003, 0x00000000); + mdelay(20); /* wait for the temperature to stabilize */ + } } static void @@ -171,6 +190,21 @@ nv84_therm_intr(struct nouveau_subdev *subdev) } static int +nv84_therm_init(struct nouveau_object *object) +{ + struct nv84_therm_priv *priv = (void *)object; + int ret; + + ret = nouveau_therm_init(&priv->base.base); + if (ret) + return ret; + + nv84_sensor_setup(&priv->base.base); + + return 0; +} + +static int nv84_therm_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, @@ -228,7 +262,7 @@ nv84_therm_oclass = { .ofuncs = &(struct nouveau_ofuncs) { .ctor = nv84_therm_ctor, .dtor = _nouveau_therm_dtor, - .init = _nouveau_therm_init, + .init = nv84_therm_init, .fini = nv84_therm_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/therm/nva3.c index 0478b2e3fb1d..7893357a7e9f 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/therm/nva3.c +++ b/drivers/gpu/drm/nouveau/core/subdev/therm/nva3.c @@ -51,6 +51,8 @@ nva3_therm_init(struct nouveau_object *object) if (ret) return ret; + nv84_sensor_setup(&priv->base.base); + /* enable fan tach, count revolutions per-second */ nv_mask(priv, 0x00e720, 0x00000003, 0x00000002); if (tach->func != DCB_GPIO_UNUSED) { diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c b/drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c index bbf117be572f..b70f7cc649b8 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c @@ -114,7 +114,7 @@ nvd0_fan_pwm_clock(struct nouveau_therm *therm, int line) return nv_device(therm)->crystal * 1000 / 10; } -static int +int nvd0_therm_init(struct nouveau_object *object) { struct nvd0_therm_priv *priv = (void *)object; @@ -150,6 +150,8 @@ nvd0_therm_ctor(struct nouveau_object *parent, if (ret) return ret; + nv84_sensor_setup(&priv->base.base); + priv->base.base.pwm_ctrl = nvd0_fan_pwm_ctrl; priv->base.base.pwm_get = nvd0_fan_pwm_get; priv->base.base.pwm_set = nvd0_fan_pwm_set; diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/priv.h b/drivers/gpu/drm/nouveau/core/subdev/therm/priv.h index 916fca5c7816..7dba8c281a0b 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/therm/priv.h +++ b/drivers/gpu/drm/nouveau/core/subdev/therm/priv.h @@ -145,10 +145,13 @@ int nv50_fan_pwm_get(struct nouveau_therm *, int, u32 *, u32 *); int nv50_fan_pwm_set(struct nouveau_therm *, int, u32, u32); int nv50_fan_pwm_clock(struct nouveau_therm *, int); int nv84_temp_get(struct nouveau_therm *therm); +void nv84_sensor_setup(struct nouveau_therm *therm); int nv84_therm_fini(struct nouveau_object *object, bool suspend); int nva3_therm_fan_sense(struct nouveau_therm *); +int nvd0_therm_init(struct nouveau_object *object); + int nouveau_fanpwm_create(struct nouveau_therm *, struct dcb_gpio_func *); int nouveau_fantog_create(struct nouveau_therm *, struct dcb_gpio_func *); int nouveau_fannil_create(struct nouveau_therm *); diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c b/drivers/gpu/drm/nouveau/core/subdev/vm/base.c index 7dd680ff2f6f..f75a683bd47a 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c +++ b/drivers/gpu/drm/nouveau/core/subdev/vm/base.c @@ -296,7 +296,7 @@ nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift, int ret; mutex_lock(&nv_subdev(vmm)->mutex); - ret = nouveau_mm_head(&vm->mm, page_shift, msize, msize, align, + ret = nouveau_mm_head(&vm->mm, 0, page_shift, msize, msize, align, &vma->node); if (unlikely(ret != 0)) { mutex_unlock(&nv_subdev(vmm)->mutex); diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c index 668cf964e4a9..2d0988755530 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c @@ -28,7 +28,7 @@ #include <subdev/timer.h> #include <subdev/fb.h> #include <subdev/vm.h> -#include <subdev/ltcg.h> +#include <subdev/ltc.h> #include <subdev/bar.h> struct nvc0_vmmgr_priv { @@ -116,12 +116,12 @@ nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, pte <<= 3; if (mem->tag) { - struct nouveau_ltcg *ltcg = - nouveau_ltcg(vma->vm->vmm->base.base.parent); + struct nouveau_ltc *ltc = + nouveau_ltc(vma->vm->vmm->base.base.parent); u32 tag = mem->tag->offset + (delta >> 17); phys |= (u64)tag << (32 + 12); next |= (u64)1 << (32 + 12); - ltcg->tags_clear(ltcg, tag, cnt); + ltc->tags_clear(ltc, tag, cnt); } while (cnt--) { |