diff options
Diffstat (limited to 'drivers/iio/adc/xilinx-xadc-core.c')
-rw-r--r-- | drivers/iio/adc/xilinx-xadc-core.c | 554 |
1 files changed, 340 insertions, 214 deletions
diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c index ec227b358cd6..292f2892d223 100644 --- a/drivers/iio/adc/xilinx-xadc-core.c +++ b/drivers/iio/adc/xilinx-xadc-core.c @@ -3,7 +3,7 @@ * Xilinx XADC driver * * Copyright 2013-2014 Analog Devices Inc. - * Author: Lars-Peter Clauen <lars@metafoo.de> + * Author: Lars-Peter Clausen <lars@metafoo.de> * * Documentation for the parts can be found at: * - XADC hardmacro: Xilinx UG480 @@ -17,9 +17,11 @@ #include <linux/interrupt.h> #include <linux/io.h> #include <linux/kernel.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of.h> +#include <linux/overflow.h> #include <linux/platform_device.h> +#include <linux/property.h> #include <linux/slab.h> #include <linux/sysfs.h> @@ -92,7 +94,12 @@ static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500; #define XADC_AXI_REG_GIER 0x5c #define XADC_AXI_REG_IPISR 0x60 #define XADC_AXI_REG_IPIER 0x68 -#define XADC_AXI_ADC_REG_OFFSET 0x200 + +/* 7 Series */ +#define XADC_7S_AXI_ADC_REG_OFFSET 0x200 + +/* UltraScale */ +#define XADC_US_AXI_ADC_REG_OFFSET 0x400 #define XADC_AXI_RESET_MAGIC 0xa #define XADC_AXI_GIER_ENABLE BIT(31) @@ -101,6 +108,17 @@ static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500; #define XADC_AXI_INT_ALARM_MASK 0x3c0f #define XADC_FLAGS_BUFFERED BIT(0) +#define XADC_FLAGS_IRQ_OPTIONAL BIT(1) + +/* + * The XADC hardware supports a samplerate of up to 1MSPS. Unfortunately it does + * not have a hardware FIFO. Which means an interrupt is generated for each + * conversion sequence. At 1MSPS sample rate the CPU in ZYNQ7000 is completely + * overloaded by the interrupts that it soft-lockups. For this reason the driver + * limits the maximum samplerate 150kSPS. At this rate the CPU is fairly busy, + * but still responsive. + */ +#define XADC_MAX_SAMPLERATE 150000 static void xadc_write_reg(struct xadc *xadc, unsigned int reg, uint32_t val) @@ -437,6 +455,12 @@ static const struct xadc_ops xadc_zynq_ops = { .get_dclk_rate = xadc_zynq_get_dclk_rate, .interrupt_handler = xadc_zynq_interrupt_handler, .update_alarm = xadc_zynq_update_alarm, + .type = XADC_TYPE_S7, +}; + +static const unsigned int xadc_axi_reg_offsets[] = { + [XADC_TYPE_S7] = XADC_7S_AXI_ADC_REG_OFFSET, + [XADC_TYPE_US] = XADC_US_AXI_ADC_REG_OFFSET, }; static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg, @@ -444,7 +468,8 @@ static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg, { uint32_t val32; - xadc_read_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, &val32); + xadc_read_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4, + &val32); *val = val32 & 0xffff; return 0; @@ -453,7 +478,8 @@ static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg, static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg, uint16_t val) { - xadc_write_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, val); + xadc_write_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4, + val); return 0; } @@ -531,14 +557,26 @@ static unsigned long xadc_axi_get_dclk(struct xadc *xadc) return clk_get_rate(xadc->clk); } -static const struct xadc_ops xadc_axi_ops = { +static const struct xadc_ops xadc_7s_axi_ops = { .read = xadc_axi_read_adc_reg, .write = xadc_axi_write_adc_reg, .setup = xadc_axi_setup, .get_dclk_rate = xadc_axi_get_dclk, .update_alarm = xadc_axi_update_alarm, .interrupt_handler = xadc_axi_interrupt_handler, - .flags = XADC_FLAGS_BUFFERED, + .flags = XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL, + .type = XADC_TYPE_S7, +}; + +static const struct xadc_ops xadc_us_axi_ops = { + .read = xadc_axi_read_adc_reg, + .write = xadc_axi_write_adc_reg, + .setup = xadc_axi_setup, + .get_dclk_rate = xadc_axi_get_dclk, + .update_alarm = xadc_axi_update_alarm, + .interrupt_handler = xadc_axi_interrupt_handler, + .flags = XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL, + .type = XADC_TYPE_US, }; static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg, @@ -575,15 +613,22 @@ static int xadc_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *mask) { struct xadc *xadc = iio_priv(indio_dev); - unsigned int n; + size_t new_size, n; + void *data; n = bitmap_weight(mask, indio_dev->masklength); - kfree(xadc->data); - xadc->data = kcalloc(n, sizeof(*xadc->data), GFP_KERNEL); - if (!xadc->data) + if (check_mul_overflow(n, sizeof(*xadc->data), &new_size)) return -ENOMEM; + data = devm_krealloc(indio_dev->dev.parent, xadc->data, + new_size, GFP_KERNEL); + if (!data) + return -ENOMEM; + + memset(data, 0, new_size); + xadc->data = data; + return 0; } @@ -653,7 +698,7 @@ static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state) mutex_lock(&xadc->mutex); if (state) { - /* Only one of the two triggers can be active at the a time. */ + /* Only one of the two triggers can be active at a time. */ if (xadc->trigger != NULL) { ret = -EBUSY; goto err_out; @@ -674,7 +719,7 @@ static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state) spin_lock_irqsave(&xadc->lock, flags); xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val); - xadc_write_reg(xadc, XADC_AXI_REG_IPISR, val & XADC_AXI_INT_EOS); + xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS); if (state) val |= XADC_AXI_INT_EOS; else @@ -695,40 +740,46 @@ static const struct iio_trigger_ops xadc_trigger_ops = { static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev, const char *name) { + struct device *dev = indio_dev->dev.parent; struct iio_trigger *trig; int ret; - trig = iio_trigger_alloc("%s%d-%s", indio_dev->name, - indio_dev->id, name); + trig = devm_iio_trigger_alloc(dev, "%s%d-%s", indio_dev->name, + iio_device_id(indio_dev), name); if (trig == NULL) return ERR_PTR(-ENOMEM); - trig->dev.parent = indio_dev->dev.parent; trig->ops = &xadc_trigger_ops; iio_trigger_set_drvdata(trig, iio_priv(indio_dev)); - ret = iio_trigger_register(trig); + ret = devm_iio_trigger_register(dev, trig); if (ret) - goto error_free_trig; + return ERR_PTR(ret); return trig; - -error_free_trig: - iio_trigger_free(trig); - return ERR_PTR(ret); } static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode) { uint16_t val; + /* + * As per datasheet the power-down bits are don't care in the + * UltraScale, but as per reality setting the power-down bit for the + * non-existing ADC-B powers down the main ADC, so just return and don't + * do anything. + */ + if (xadc->ops->type == XADC_TYPE_US) + return 0; + + /* Powerdown the ADC-B when it is not needed. */ switch (seq_mode) { case XADC_CONF1_SEQ_SIMULTANEOUS: case XADC_CONF1_SEQ_INDEPENDENT: - val = XADC_CONF2_PD_ADC_B; + val = 0; break; default: - val = 0; + val = XADC_CONF2_PD_ADC_B; break; } @@ -740,6 +791,10 @@ static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode) { unsigned int aux_scan_mode = scan_mode >> 16; + /* UltraScale has only one ADC and supports only continuous mode */ + if (xadc->ops->type == XADC_TYPE_US) + return XADC_CONF1_SEQ_CONTINUOUS; + if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL) return XADC_CONF1_SEQ_SIMULTANEOUS; @@ -797,6 +852,16 @@ static int xadc_preenable(struct iio_dev *indio_dev) if (ret) goto err; + /* + * In simultaneous mode the upper and lower aux channels are samples at + * the same time. In this mode the upper 8 bits in the sequencer + * register are don't care and the lower 8 bits control two channels + * each. As such we must set the bit if either the channel in the lower + * group or the upper group is enabled. + */ + if (seq_mode == XADC_CONF1_SEQ_SIMULTANEOUS) + scan_mask = ((scan_mask >> 8) | scan_mask) & 0xff0000; + ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16); if (ret) goto err; @@ -818,16 +883,31 @@ err: static const struct iio_buffer_setup_ops xadc_buffer_ops = { .preenable = &xadc_preenable, - .postenable = &iio_triggered_buffer_postenable, - .predisable = &iio_triggered_buffer_predisable, .postdisable = &xadc_postdisable, }; +static int xadc_read_samplerate(struct xadc *xadc) +{ + unsigned int div; + uint16_t val16; + int ret; + + ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16); + if (ret) + return ret; + + div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET; + if (div < 2) + div = 2; + + return xadc_get_dclk_rate(xadc) / div / 26; +} + static int xadc_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long info) { struct xadc *xadc = iio_priv(indio_dev); - unsigned int div; + unsigned int bits = chan->scan_type.realbits; uint16_t val16; int ret; @@ -839,17 +919,17 @@ static int xadc_read_raw(struct iio_dev *indio_dev, if (ret < 0) return ret; - val16 >>= 4; + val16 >>= chan->scan_type.shift; if (chan->scan_type.sign == 'u') *val = val16; else - *val = sign_extend32(val16, 11); + *val = sign_extend32(val16, bits - 1); return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: switch (chan->type) { case IIO_VOLTAGE: - /* V = (val * 3.0) / 4096 */ + /* V = (val * 3.0) / 2**bits */ switch (chan->address) { case XADC_REG_VCCINT: case XADC_REG_VCCAUX: @@ -865,56 +945,46 @@ static int xadc_read_raw(struct iio_dev *indio_dev, *val = 1000; break; } - *val2 = 12; + *val2 = bits; return IIO_VAL_FRACTIONAL_LOG2; case IIO_TEMP: - /* Temp in C = (val * 503.975) / 4096 - 273.15 */ + /* Temp in C = (val * 503.975) / 2**bits - 273.15 */ *val = 503975; - *val2 = 12; + *val2 = bits; return IIO_VAL_FRACTIONAL_LOG2; default: return -EINVAL; } case IIO_CHAN_INFO_OFFSET: /* Only the temperature channel has an offset */ - *val = -((273150 << 12) / 503975); + *val = -((273150 << bits) / 503975); return IIO_VAL_INT; case IIO_CHAN_INFO_SAMP_FREQ: - ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16); - if (ret) + ret = xadc_read_samplerate(xadc); + if (ret < 0) return ret; - div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET; - if (div < 2) - div = 2; - - *val = xadc_get_dclk_rate(xadc) / div / 26; - + *val = ret; return IIO_VAL_INT; default: return -EINVAL; } } -static int xadc_write_raw(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, int val, int val2, long info) +static int xadc_write_samplerate(struct xadc *xadc, int val) { - struct xadc *xadc = iio_priv(indio_dev); unsigned long clk_rate = xadc_get_dclk_rate(xadc); unsigned int div; if (!clk_rate) return -EINVAL; - if (info != IIO_CHAN_INFO_SAMP_FREQ) - return -EINVAL; - if (val <= 0) return -EINVAL; /* Max. 150 kSPS */ - if (val > 150000) - val = 150000; + if (val > XADC_MAX_SAMPLERATE) + val = XADC_MAX_SAMPLERATE; val *= 26; @@ -927,7 +997,7 @@ static int xadc_write_raw(struct iio_dev *indio_dev, * limit. */ div = clk_rate / val; - if (clk_rate / div / 26 > 150000) + if (clk_rate / div / 26 > XADC_MAX_SAMPLERATE) div++; if (div < 2) div = 2; @@ -938,6 +1008,17 @@ static int xadc_write_raw(struct iio_dev *indio_dev, div << XADC_CONF2_DIV_OFFSET); } +static int xadc_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int val, int val2, long info) +{ + struct xadc *xadc = iio_priv(indio_dev); + + if (info != IIO_CHAN_INFO_SAMP_FREQ) + return -EINVAL; + + return xadc_write_samplerate(xadc, val); +} + static const struct iio_event_spec xadc_temp_events[] = { { .type = IIO_EV_TYPE_THRESH, @@ -965,7 +1046,7 @@ static const struct iio_event_spec xadc_voltage_events[] = { }, }; -#define XADC_CHAN_TEMP(_chan, _scan_index, _addr) { \ +#define XADC_CHAN_TEMP(_chan, _scan_index, _addr, _bits) { \ .type = IIO_TEMP, \ .indexed = 1, \ .channel = (_chan), \ @@ -979,14 +1060,14 @@ static const struct iio_event_spec xadc_voltage_events[] = { .scan_index = (_scan_index), \ .scan_type = { \ .sign = 'u', \ - .realbits = 12, \ + .realbits = (_bits), \ .storagebits = 16, \ - .shift = 4, \ + .shift = 16 - (_bits), \ .endianness = IIO_CPU, \ }, \ } -#define XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) { \ +#define XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, _bits, _ext, _alarm) { \ .type = IIO_VOLTAGE, \ .indexed = 1, \ .channel = (_chan), \ @@ -999,41 +1080,82 @@ static const struct iio_event_spec xadc_voltage_events[] = { .scan_index = (_scan_index), \ .scan_type = { \ .sign = ((_addr) == XADC_REG_VREFN) ? 's' : 'u', \ - .realbits = 12, \ + .realbits = (_bits), \ .storagebits = 16, \ - .shift = 4, \ + .shift = 16 - (_bits), \ .endianness = IIO_CPU, \ }, \ .extend_name = _ext, \ } -static const struct iio_chan_spec xadc_channels[] = { - XADC_CHAN_TEMP(0, 8, XADC_REG_TEMP), - XADC_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true), - XADC_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true), - XADC_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true), - XADC_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpint", true), - XADC_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpaux", true), - XADC_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccoddr", true), - XADC_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false), - XADC_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false), - XADC_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false), - XADC_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false), - XADC_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false), - XADC_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false), - XADC_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false), - XADC_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false), - XADC_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false), - XADC_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false), - XADC_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false), - XADC_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false), - XADC_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false), - XADC_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false), - XADC_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false), - XADC_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false), - XADC_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false), - XADC_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false), - XADC_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false), +/* 7 Series */ +#define XADC_7S_CHAN_TEMP(_chan, _scan_index, _addr) \ + XADC_CHAN_TEMP(_chan, _scan_index, _addr, 12) +#define XADC_7S_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \ + XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 12, _ext, _alarm) + +static const struct iio_chan_spec xadc_7s_channels[] = { + XADC_7S_CHAN_TEMP(0, 8, XADC_REG_TEMP), + XADC_7S_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true), + XADC_7S_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true), + XADC_7S_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true), + XADC_7S_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpint", true), + XADC_7S_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpaux", true), + XADC_7S_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccoddr", true), + XADC_7S_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false), + XADC_7S_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false), + XADC_7S_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false), + XADC_7S_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false), + XADC_7S_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false), + XADC_7S_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false), + XADC_7S_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false), + XADC_7S_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false), + XADC_7S_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false), + XADC_7S_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false), + XADC_7S_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false), + XADC_7S_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false), + XADC_7S_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false), + XADC_7S_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false), + XADC_7S_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false), + XADC_7S_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false), + XADC_7S_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false), + XADC_7S_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false), + XADC_7S_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false), +}; + +/* UltraScale */ +#define XADC_US_CHAN_TEMP(_chan, _scan_index, _addr) \ + XADC_CHAN_TEMP(_chan, _scan_index, _addr, 10) +#define XADC_US_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \ + XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 10, _ext, _alarm) + +static const struct iio_chan_spec xadc_us_channels[] = { + XADC_US_CHAN_TEMP(0, 8, XADC_REG_TEMP), + XADC_US_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true), + XADC_US_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true), + XADC_US_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true), + XADC_US_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpsintlp", true), + XADC_US_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpsintfp", true), + XADC_US_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccpsaux", true), + XADC_US_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false), + XADC_US_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false), + XADC_US_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false), + XADC_US_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false), + XADC_US_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false), + XADC_US_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false), + XADC_US_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false), + XADC_US_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false), + XADC_US_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false), + XADC_US_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false), + XADC_US_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false), + XADC_US_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false), + XADC_US_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false), + XADC_US_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false), + XADC_US_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false), + XADC_US_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false), + XADC_US_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false), + XADC_US_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false), + XADC_US_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false), }; static const struct iio_info xadc_info = { @@ -1047,27 +1169,38 @@ static const struct iio_info xadc_info = { }; static const struct of_device_id xadc_of_match_table[] = { - { .compatible = "xlnx,zynq-xadc-1.00.a", (void *)&xadc_zynq_ops }, - { .compatible = "xlnx,axi-xadc-1.00.a", (void *)&xadc_axi_ops }, + { + .compatible = "xlnx,zynq-xadc-1.00.a", + .data = &xadc_zynq_ops + }, { + .compatible = "xlnx,axi-xadc-1.00.a", + .data = &xadc_7s_axi_ops + }, { + .compatible = "xlnx,system-management-wiz-1.3", + .data = &xadc_us_axi_ops + }, { }, }; MODULE_DEVICE_TABLE(of, xadc_of_match_table); -static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np, - unsigned int *conf) +static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq) { + struct device *dev = indio_dev->dev.parent; struct xadc *xadc = iio_priv(indio_dev); + const struct iio_chan_spec *channel_templates; struct iio_chan_spec *channels, *chan; - struct device_node *chan_node, *child; + struct fwnode_handle *chan_node, *child; + unsigned int max_channels; unsigned int num_channels; const char *external_mux; u32 ext_mux_chan; u32 reg; int ret; + int i; *conf = 0; - ret = of_property_read_string(np, "xlnx,external-mux", &external_mux); + ret = device_property_read_string(dev, "xlnx,external-mux", &external_mux); if (ret < 0 || strcasecmp(external_mux, "none") == 0) xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE; else if (strcasecmp(external_mux, "single") == 0) @@ -1078,8 +1211,7 @@ static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np, return -EINVAL; if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) { - ret = of_property_read_u32(np, "xlnx,external-mux-channel", - &ext_mux_chan); + ret = device_property_read_u32(dev, "xlnx,external-mux-channel", &ext_mux_chan); if (ret < 0) return ret; @@ -1099,45 +1231,59 @@ static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np, *conf |= XADC_CONF0_MUX | XADC_CONF0_CHAN(ext_mux_chan); } - - channels = kmemdup(xadc_channels, sizeof(xadc_channels), GFP_KERNEL); + if (xadc->ops->type == XADC_TYPE_S7) { + channel_templates = xadc_7s_channels; + max_channels = ARRAY_SIZE(xadc_7s_channels); + } else { + channel_templates = xadc_us_channels; + max_channels = ARRAY_SIZE(xadc_us_channels); + } + channels = devm_kmemdup(dev, channel_templates, + sizeof(channels[0]) * max_channels, GFP_KERNEL); if (!channels) return -ENOMEM; num_channels = 9; chan = &channels[9]; - chan_node = of_get_child_by_name(np, "xlnx,channels"); - if (chan_node) { - for_each_child_of_node(chan_node, child) { - if (num_channels >= ARRAY_SIZE(xadc_channels)) { - of_node_put(child); - break; - } + chan_node = device_get_named_child_node(dev, "xlnx,channels"); + fwnode_for_each_child_node(chan_node, child) { + if (num_channels >= max_channels) { + fwnode_handle_put(child); + break; + } - ret = of_property_read_u32(child, "reg", ®); - if (ret || reg > 16) - continue; + ret = fwnode_property_read_u32(child, "reg", ®); + if (ret || reg > 16) + continue; - if (of_property_read_bool(child, "xlnx,bipolar")) - chan->scan_type.sign = 's'; + if (fwnode_property_read_bool(child, "xlnx,bipolar")) + chan->scan_type.sign = 's'; - if (reg == 0) { - chan->scan_index = 11; - chan->address = XADC_REG_VPVN; - } else { - chan->scan_index = 15 + reg; - chan->address = XADC_REG_VAUX(reg - 1); - } - num_channels++; - chan++; + if (reg == 0) { + chan->scan_index = 11; + chan->address = XADC_REG_VPVN; + } else { + chan->scan_index = 15 + reg; + chan->address = XADC_REG_VAUX(reg - 1); + } + num_channels++; + chan++; + } + fwnode_handle_put(chan_node); + + /* No IRQ => no events */ + if (irq <= 0) { + for (i = 0; i < num_channels; i++) { + channels[i].event_spec = NULL; + channels[i].num_event_specs = 0; } } - of_node_put(chan_node); indio_dev->num_channels = num_channels; - indio_dev->channels = krealloc(channels, sizeof(*channels) * - num_channels, GFP_KERNEL); + indio_dev->channels = devm_krealloc(dev, channels, + sizeof(*channels) * num_channels, + GFP_KERNEL); /* If we can't resize the channels array, just use the original */ if (!indio_dev->channels) indio_dev->channels = channels; @@ -1145,9 +1291,22 @@ static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np, return 0; } +static const char * const xadc_type_names[] = { + [XADC_TYPE_S7] = "xadc", + [XADC_TYPE_US] = "xilinx-system-monitor", +}; + +static void xadc_cancel_delayed_work(void *data) +{ + struct delayed_work *work = data; + + cancel_delayed_work_sync(work); +} + static int xadc_probe(struct platform_device *pdev) { - const struct of_device_id *id; + struct device *dev = &pdev->dev; + const struct xadc_ops *ops; struct iio_dev *indio_dev; unsigned int bipolar_mask; unsigned int conf0; @@ -1156,24 +1315,21 @@ static int xadc_probe(struct platform_device *pdev) int irq; int i; - if (!pdev->dev.of_node) - return -ENODEV; - - id = of_match_node(xadc_of_match_table, pdev->dev.of_node); - if (!id) + ops = device_get_match_data(dev); + if (!ops) return -EINVAL; - irq = platform_get_irq(pdev, 0); - if (irq <= 0) - return -ENXIO; + irq = platform_get_irq_optional(pdev, 0); + if (irq < 0 && + (irq != -ENXIO || !(ops->flags & XADC_FLAGS_IRQ_OPTIONAL))) + return irq; - indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*xadc)); + indio_dev = devm_iio_device_alloc(dev, sizeof(*xadc)); if (!indio_dev) return -ENOMEM; xadc = iio_priv(indio_dev); - xadc->ops = id->data; - xadc->irq = irq; + xadc->ops = ops; init_completion(&xadc->completion); mutex_init(&xadc->mutex); spin_lock_init(&xadc->lock); @@ -1183,54 +1339,69 @@ static int xadc_probe(struct platform_device *pdev) if (IS_ERR(xadc->base)) return PTR_ERR(xadc->base); - indio_dev->dev.parent = &pdev->dev; - indio_dev->dev.of_node = pdev->dev.of_node; - indio_dev->name = "xadc"; + indio_dev->name = xadc_type_names[xadc->ops->type]; indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->info = &xadc_info; - ret = xadc_parse_dt(indio_dev, pdev->dev.of_node, &conf0); + ret = xadc_parse_dt(indio_dev, &conf0, irq); if (ret) - goto err_device_free; + return ret; if (xadc->ops->flags & XADC_FLAGS_BUFFERED) { - ret = iio_triggered_buffer_setup(indio_dev, - &iio_pollfunc_store_time, &xadc_trigger_handler, - &xadc_buffer_ops); + ret = devm_iio_triggered_buffer_setup(dev, indio_dev, + &iio_pollfunc_store_time, + &xadc_trigger_handler, + &xadc_buffer_ops); if (ret) - goto err_device_free; + return ret; - xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst"); - if (IS_ERR(xadc->convst_trigger)) { - ret = PTR_ERR(xadc->convst_trigger); - goto err_triggered_buffer_cleanup; - } - xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev, - "samplerate"); - if (IS_ERR(xadc->samplerate_trigger)) { - ret = PTR_ERR(xadc->samplerate_trigger); - goto err_free_convst_trigger; + if (irq > 0) { + xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst"); + if (IS_ERR(xadc->convst_trigger)) + return PTR_ERR(xadc->convst_trigger); + + xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev, + "samplerate"); + if (IS_ERR(xadc->samplerate_trigger)) + return PTR_ERR(xadc->samplerate_trigger); } } - xadc->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(xadc->clk)) { - ret = PTR_ERR(xadc->clk); - goto err_free_samplerate_trigger; + xadc->clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(xadc->clk)) + return PTR_ERR(xadc->clk); + + /* + * Make sure not to exceed the maximum samplerate since otherwise the + * resulting interrupt storm will soft-lock the system. + */ + if (xadc->ops->flags & XADC_FLAGS_BUFFERED) { + ret = xadc_read_samplerate(xadc); + if (ret < 0) + return ret; + + if (ret > XADC_MAX_SAMPLERATE) { + ret = xadc_write_samplerate(xadc, XADC_MAX_SAMPLERATE); + if (ret < 0) + return ret; + } } - ret = clk_prepare_enable(xadc->clk); - if (ret) - goto err_free_samplerate_trigger; + if (irq > 0) { + ret = devm_request_irq(dev, irq, xadc->ops->interrupt_handler, + 0, dev_name(dev), indio_dev); + if (ret) + return ret; - ret = request_irq(xadc->irq, xadc->ops->interrupt_handler, 0, - dev_name(&pdev->dev), indio_dev); - if (ret) - goto err_clk_disable_unprepare; + ret = devm_add_action_or_reset(dev, xadc_cancel_delayed_work, + &xadc->zynq_unmask_work); + if (ret) + return ret; + } - ret = xadc->ops->setup(pdev, indio_dev, xadc->irq); + ret = xadc->ops->setup(pdev, indio_dev, irq); if (ret) - goto err_free_irq; + return ret; for (i = 0; i < 16; i++) xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i), @@ -1238,7 +1409,7 @@ static int xadc_probe(struct platform_device *pdev) ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0); if (ret) - goto err_free_irq; + return ret; bipolar_mask = 0; for (i = 0; i < indio_dev->num_channels; i++) { @@ -1248,17 +1419,18 @@ static int xadc_probe(struct platform_device *pdev) ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(0), bipolar_mask); if (ret) - goto err_free_irq; + return ret; + ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1), bipolar_mask >> 16); if (ret) - goto err_free_irq; + return ret; /* Disable all alarms */ ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_ALARM_MASK, XADC_CONF1_ALARM_MASK); if (ret) - goto err_free_irq; + return ret; /* Set thresholds to min/max */ for (i = 0; i < 16; i++) { @@ -1273,63 +1445,17 @@ static int xadc_probe(struct platform_device *pdev) ret = xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(i), xadc->threshold[i]); if (ret) - goto err_free_irq; + return ret; } /* Go to non-buffered mode */ xadc_postdisable(indio_dev); - ret = iio_device_register(indio_dev); - if (ret) - goto err_free_irq; - - platform_set_drvdata(pdev, indio_dev); - - return 0; - -err_free_irq: - free_irq(xadc->irq, indio_dev); - cancel_delayed_work_sync(&xadc->zynq_unmask_work); -err_clk_disable_unprepare: - clk_disable_unprepare(xadc->clk); -err_free_samplerate_trigger: - if (xadc->ops->flags & XADC_FLAGS_BUFFERED) - iio_trigger_free(xadc->samplerate_trigger); -err_free_convst_trigger: - if (xadc->ops->flags & XADC_FLAGS_BUFFERED) - iio_trigger_free(xadc->convst_trigger); -err_triggered_buffer_cleanup: - if (xadc->ops->flags & XADC_FLAGS_BUFFERED) - iio_triggered_buffer_cleanup(indio_dev); -err_device_free: - kfree(indio_dev->channels); - - return ret; -} - -static int xadc_remove(struct platform_device *pdev) -{ - struct iio_dev *indio_dev = platform_get_drvdata(pdev); - struct xadc *xadc = iio_priv(indio_dev); - - iio_device_unregister(indio_dev); - if (xadc->ops->flags & XADC_FLAGS_BUFFERED) { - iio_trigger_free(xadc->samplerate_trigger); - iio_trigger_free(xadc->convst_trigger); - iio_triggered_buffer_cleanup(indio_dev); - } - free_irq(xadc->irq, indio_dev); - cancel_delayed_work_sync(&xadc->zynq_unmask_work); - clk_disable_unprepare(xadc->clk); - kfree(xadc->data); - kfree(indio_dev->channels); - - return 0; + return devm_iio_device_register(dev, indio_dev); } static struct platform_driver xadc_driver = { .probe = xadc_probe, - .remove = xadc_remove, .driver = { .name = "xadc", .of_match_table = xadc_of_match_table, |