diff options
Diffstat (limited to 'drivers/media/platform/s5p-mfc')
-rw-r--r-- | drivers/media/platform/s5p-mfc/s5p_mfc.c | 83 | ||||
-rw-r--r-- | drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v5.c | 1 | ||||
-rw-r--r-- | drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c | 1 | ||||
-rw-r--r-- | drivers/media/platform/s5p-mfc/s5p_mfc_common.h | 6 | ||||
-rw-r--r-- | drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c | 27 | ||||
-rw-r--r-- | drivers/media/platform/s5p-mfc/s5p_mfc_debug.h | 6 | ||||
-rw-r--r-- | drivers/media/platform/s5p-mfc/s5p_mfc_dec.c | 54 | ||||
-rw-r--r-- | drivers/media/platform/s5p-mfc/s5p_mfc_enc.c | 67 | ||||
-rw-r--r-- | drivers/media/platform/s5p-mfc/s5p_mfc_opr.c | 4 | ||||
-rw-r--r-- | drivers/media/platform/s5p-mfc/s5p_mfc_opr.h | 488 | ||||
-rw-r--r-- | drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c | 31 | ||||
-rw-r--r-- | drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c | 491 | ||||
-rw-r--r-- | drivers/media/platform/s5p-mfc/s5p_mfc_pm.c | 2 |
13 files changed, 614 insertions, 647 deletions
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c index d35b0418ab37..165bc86c5962 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c @@ -37,8 +37,8 @@ #define S5P_MFC_DEC_NAME "s5p-mfc-dec" #define S5P_MFC_ENC_NAME "s5p-mfc-enc" -int debug; -module_param(debug, int, S_IRUGO | S_IWUSR); +int mfc_debug_level; +module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages"); /* Helper functions for interrupt processing */ @@ -150,10 +150,10 @@ static void s5p_mfc_watchdog_worker(struct work_struct *work) if (!ctx) continue; ctx->state = MFCINST_ERROR; - s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue, - &ctx->vq_dst); - s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue, - &ctx->vq_src); + s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue, + &ctx->dst_queue, &ctx->vq_dst); + s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue, + &ctx->src_queue, &ctx->vq_src); clear_work_bit(ctx); wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0); } @@ -264,7 +264,12 @@ static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err) unsigned int frame_type; dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev); - frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_disp_frame_type, ctx); + if (IS_MFCV6_PLUS(dev)) + frame_type = s5p_mfc_hw_call(dev->mfc_ops, + get_disp_frame_type, ctx); + else + frame_type = s5p_mfc_hw_call(dev->mfc_ops, + get_dec_frame_type, dev); /* If frame is same as previous then skip and do not dequeue */ if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) { @@ -327,12 +332,12 @@ static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx, if (res_change == S5P_FIMV_RES_INCREASE || res_change == S5P_FIMV_RES_DECREASE) { ctx->state = MFCINST_RES_CHANGE_INIT; - s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); wake_up_ctx(ctx, reason, err); if (test_and_clear_bit(0, &dev->hw_lock) == 0) BUG(); s5p_mfc_clock_off(); - s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); return; } if (ctx->dpb_flush_flag) @@ -400,7 +405,7 @@ leave_handle_frame: if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING) || ctx->dst_queue_cnt < ctx->pb_count) clear_work_bit(ctx); - s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); wake_up_ctx(ctx, reason, err); if (test_and_clear_bit(0, &dev->hw_lock) == 0) BUG(); @@ -409,7 +414,7 @@ leave_handle_frame: if (test_bit(0, &dev->enter_suspend)) wake_up_dev(dev, reason, err); else - s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); } /* Error handling for interrupt */ @@ -435,10 +440,10 @@ static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev, ctx->state = MFCINST_ERROR; /* Mark all dst buffers as having an error */ spin_lock_irqsave(&dev->irqlock, flags); - s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, + s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue, &ctx->dst_queue, &ctx->vq_dst); /* Mark all src buffers as having an error */ - s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, + s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue, &ctx->src_queue, &ctx->vq_src); spin_unlock_irqrestore(&dev->irqlock, flags); wake_up_ctx(ctx, reason, err); @@ -452,7 +457,7 @@ static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev, } if (test_and_clear_bit(0, &dev->hw_lock) == 0) BUG(); - s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); s5p_mfc_clock_off(); wake_up_dev(dev, reason, err); return; @@ -476,7 +481,7 @@ static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx, ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height, dev); - s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx); + s5p_mfc_hw_call_void(dev->mfc_ops, dec_calc_dpb_size, ctx); ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count, dev); @@ -503,12 +508,12 @@ static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx, ctx->head_processed = 1; } } - s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); clear_work_bit(ctx); if (test_and_clear_bit(0, &dev->hw_lock) == 0) BUG(); s5p_mfc_clock_off(); - s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); wake_up_ctx(ctx, reason, err); } @@ -523,7 +528,7 @@ static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx, if (ctx == NULL) return; dev = ctx->dev; - s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); ctx->int_type = reason; ctx->int_err = err; ctx->int_cond = 1; @@ -550,7 +555,7 @@ static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx, s5p_mfc_clock_off(); wake_up(&ctx->queue); - s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); } else { if (test_and_clear_bit(0, &dev->hw_lock) == 0) BUG(); @@ -591,7 +596,7 @@ static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx, s5p_mfc_clock_off(); wake_up(&ctx->queue); - s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); } /* Interrupt processing */ @@ -628,12 +633,12 @@ static irqreturn_t s5p_mfc_irq(int irq, void *priv) if (ctx->c_ops->post_frame_start) { if (ctx->c_ops->post_frame_start(ctx)) mfc_err("post_frame_start() failed\n"); - s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); wake_up_ctx(ctx, reason, err); if (test_and_clear_bit(0, &dev->hw_lock) == 0) BUG(); s5p_mfc_clock_off(); - s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); } else { s5p_mfc_handle_frame(ctx, reason, err); } @@ -663,7 +668,7 @@ static irqreturn_t s5p_mfc_irq(int irq, void *priv) case S5P_MFC_R2H_CMD_WAKEUP_RET: if (ctx) clear_work_bit(ctx); - s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); wake_up_dev(dev, reason, err); clear_bit(0, &dev->hw_lock); clear_bit(0, &dev->enter_suspend); @@ -685,12 +690,12 @@ static irqreturn_t s5p_mfc_irq(int irq, void *priv) default: mfc_debug(2, "Unknown int reason\n"); - s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); } mfc_debug_leave(); return IRQ_HANDLED; irq_cleanup_hw: - s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); ctx->int_type = reason; ctx->int_err = err; ctx->int_cond = 1; @@ -699,7 +704,7 @@ irq_cleanup_hw: s5p_mfc_clock_off(); - s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); mfc_debug(2, "Exit via irq_cleanup_hw\n"); return IRQ_HANDLED; } @@ -1311,11 +1316,9 @@ static int s5p_mfc_runtime_resume(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); - int pre_power; if (!m_dev->alloc_ctx) return 0; - pre_power = atomic_read(&m_dev->pm.power); atomic_set(&m_dev->pm.power, 1); return 0; } @@ -1328,20 +1331,20 @@ static const struct dev_pm_ops s5p_mfc_pm_ops = { NULL) }; -struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = { +static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = { .h264_ctx = MFC_H264_CTX_BUF_SIZE, .non_h264_ctx = MFC_CTX_BUF_SIZE, .dsc = DESC_BUF_SIZE, .shm = SHARED_BUF_SIZE, }; -struct s5p_mfc_buf_size buf_size_v5 = { +static struct s5p_mfc_buf_size buf_size_v5 = { .fw = MAX_FW_SIZE, .cpb = MAX_CPB_SIZE, .priv = &mfc_buf_size_v5, }; -struct s5p_mfc_buf_align mfc_buf_align_v5 = { +static struct s5p_mfc_buf_align mfc_buf_align_v5 = { .base = MFC_BASE_ALIGN_ORDER, }; @@ -1354,7 +1357,7 @@ static struct s5p_mfc_variant mfc_drvdata_v5 = { .fw_name[0] = "s5p-mfc.fw", }; -struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = { +static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = { .dev_ctx = MFC_CTX_BUF_SIZE_V6, .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6, .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6, @@ -1362,13 +1365,13 @@ struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = { .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6, }; -struct s5p_mfc_buf_size buf_size_v6 = { +static struct s5p_mfc_buf_size buf_size_v6 = { .fw = MAX_FW_SIZE_V6, .cpb = MAX_CPB_SIZE_V6, .priv = &mfc_buf_size_v6, }; -struct s5p_mfc_buf_align mfc_buf_align_v6 = { +static struct s5p_mfc_buf_align mfc_buf_align_v6 = { .base = 0, }; @@ -1386,7 +1389,7 @@ static struct s5p_mfc_variant mfc_drvdata_v6 = { .fw_name[1] = "s5p-mfc-v6-v2.fw", }; -struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = { +static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = { .dev_ctx = MFC_CTX_BUF_SIZE_V7, .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7, .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7, @@ -1394,13 +1397,13 @@ struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = { .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7, }; -struct s5p_mfc_buf_size buf_size_v7 = { +static struct s5p_mfc_buf_size buf_size_v7 = { .fw = MAX_FW_SIZE_V7, .cpb = MAX_CPB_SIZE_V7, .priv = &mfc_buf_size_v7, }; -struct s5p_mfc_buf_align mfc_buf_align_v7 = { +static struct s5p_mfc_buf_align mfc_buf_align_v7 = { .base = 0, }; @@ -1413,7 +1416,7 @@ static struct s5p_mfc_variant mfc_drvdata_v7 = { .fw_name[0] = "s5p-mfc-v7.fw", }; -struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = { +static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = { .dev_ctx = MFC_CTX_BUF_SIZE_V8, .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V8, .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V8, @@ -1421,13 +1424,13 @@ struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = { .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V8, }; -struct s5p_mfc_buf_size buf_size_v8 = { +static struct s5p_mfc_buf_size buf_size_v8 = { .fw = MAX_FW_SIZE_V8, .cpb = MAX_CPB_SIZE_V8, .priv = &mfc_buf_size_v8, }; -struct s5p_mfc_buf_align mfc_buf_align_v8 = { +static struct s5p_mfc_buf_align mfc_buf_align_v8 = { .base = 0, }; diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v5.c b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v5.c index 9a6efd6c1329..8c4739ca16d6 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v5.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v5.c @@ -14,6 +14,7 @@ #include "s5p_mfc_cmd.h" #include "s5p_mfc_common.h" #include "s5p_mfc_debug.h" +#include "s5p_mfc_cmd_v5.h" /* This function is used to send a command to the MFC */ static int s5p_mfc_cmd_host2risc_v5(struct s5p_mfc_dev *dev, int cmd, diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c index ec1a5947ed7d..f17609669b96 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c @@ -16,6 +16,7 @@ #include "s5p_mfc_debug.h" #include "s5p_mfc_intr.h" #include "s5p_mfc_opr.h" +#include "s5p_mfc_cmd_v6.h" static int s5p_mfc_cmd_host2risc_v6(struct s5p_mfc_dev *dev, int cmd, struct s5p_mfc_cmd_args *args) diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h index 01816ffb384b..3e41ca1293ed 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h @@ -698,6 +698,12 @@ struct mfc_control { #define s5p_mfc_hw_call(f, op, args...) \ ((f && f->op) ? f->op(args) : -ENODEV) +#define s5p_mfc_hw_call_void(f, op, args...) \ +do { \ + if (f && f->op) \ + f->op(args); \ +} while (0) + #define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh) #define ctrl_to_ctx(__ctrl) \ container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler) diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c index ca9f78922832..0c885a8a0e9f 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c @@ -21,6 +21,7 @@ #include "s5p_mfc_intr.h" #include "s5p_mfc_opr.h" #include "s5p_mfc_pm.h" +#include "s5p_mfc_ctrl.h" /* Allocate memory for firmware */ int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev) @@ -188,12 +189,12 @@ static inline void s5p_mfc_init_memctrl(struct s5p_mfc_dev *dev) { if (IS_MFCV6_PLUS(dev)) { mfc_write(dev, dev->bank1, S5P_FIMV_RISC_BASE_ADDRESS_V6); - mfc_debug(2, "Base Address : %08x\n", dev->bank1); + mfc_debug(2, "Base Address : %pad\n", &dev->bank1); } else { mfc_write(dev, dev->bank1, S5P_FIMV_MC_DRAMBASE_ADR_A); mfc_write(dev, dev->bank2, S5P_FIMV_MC_DRAMBASE_ADR_B); - mfc_debug(2, "Bank1: %08x, Bank2: %08x\n", - dev->bank1, dev->bank2); + mfc_debug(2, "Bank1: %pad, Bank2: %pad\n", + &dev->bank1, &dev->bank2); } } @@ -257,9 +258,9 @@ int s5p_mfc_init_hw(struct s5p_mfc_dev *dev) s5p_mfc_clock_off(); return ret; } - mfc_debug(2, "Ok, now will write a command to init the system\n"); + mfc_debug(2, "Ok, now will wait for completion of hardware init\n"); if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SYS_INIT_RET)) { - mfc_err("Failed to load firmware\n"); + mfc_err("Failed to init hardware\n"); s5p_mfc_reset(dev); s5p_mfc_clock_off(); return -EIO; @@ -293,7 +294,7 @@ void s5p_mfc_deinit_hw(struct s5p_mfc_dev *dev) s5p_mfc_clock_on(); s5p_mfc_reset(dev); - s5p_mfc_hw_call(dev->mfc_ops, release_dev_context_buffer, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, release_dev_context_buffer, dev); s5p_mfc_clock_off(); } @@ -396,7 +397,7 @@ int s5p_mfc_open_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx) set_work_bit_irqsave(ctx); s5p_mfc_clean_ctx_int_flags(ctx); - s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); if (s5p_mfc_wait_for_done_ctx(ctx, S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET, 0)) { /* Error or timeout */ @@ -410,9 +411,9 @@ int s5p_mfc_open_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx) err_free_desc_buf: if (ctx->type == MFCINST_DECODER) - s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, ctx); + s5p_mfc_hw_call_void(dev->mfc_ops, release_dec_desc_buffer, ctx); err_free_inst_buf: - s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx); + s5p_mfc_hw_call_void(dev->mfc_ops, release_instance_buffer, ctx); err: return ret; } @@ -422,17 +423,17 @@ void s5p_mfc_close_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx) ctx->state = MFCINST_RETURN_INST; set_work_bit_irqsave(ctx); s5p_mfc_clean_ctx_int_flags(ctx); - s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); /* Wait until instance is returned or timeout occurred */ if (s5p_mfc_wait_for_done_ctx(ctx, S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0)) mfc_err("Err returning instance\n"); /* Free resources */ - s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx); - s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx); + s5p_mfc_hw_call_void(dev->mfc_ops, release_codec_buffers, ctx); + s5p_mfc_hw_call_void(dev->mfc_ops, release_instance_buffer, ctx); if (ctx->type == MFCINST_DECODER) - s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, ctx); + s5p_mfc_hw_call_void(dev->mfc_ops, release_dec_desc_buffer, ctx); ctx->inst_no = MFC_NO_INSTANCE_SET; ctx->state = MFCINST_FREE; diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_debug.h b/drivers/media/platform/s5p-mfc/s5p_mfc_debug.h index 8e608f5aa0d7..5936923c631c 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_debug.h +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_debug.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/samsung/mfc5/s5p_mfc_debug.h + * drivers/media/platform/s5p-mfc/s5p_mfc_debug.h * * Header file for Samsung MFC (Multi Function Codec - FIMV) driver * This file contains debug macros @@ -18,11 +18,11 @@ #define DEBUG #ifdef DEBUG -extern int debug; +extern int mfc_debug_level; #define mfc_debug(level, fmt, args...) \ do { \ - if (debug >= level) \ + if (mfc_debug_level >= level) \ printk(KERN_DEBUG "%s:%d: " fmt, \ __func__, __LINE__, ##args); \ } while (0) diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c index 9103258b7df3..a98fe023deaf 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c @@ -283,17 +283,13 @@ static int vidioc_querycap(struct file *file, void *priv, /* Enumerate format */ static int vidioc_enum_fmt(struct file *file, struct v4l2_fmtdesc *f, - bool mplane, bool out) + bool out) { struct s5p_mfc_dev *dev = video_drvdata(file); struct s5p_mfc_fmt *fmt; int i, j = 0; for (i = 0; i < ARRAY_SIZE(formats); ++i) { - if (mplane && formats[i].num_planes == 1) - continue; - else if (!mplane && formats[i].num_planes > 1) - continue; if (out && formats[i].type != MFC_FMT_DEC) continue; else if (!out && formats[i].type != MFC_FMT_RAW) @@ -313,28 +309,16 @@ static int vidioc_enum_fmt(struct file *file, struct v4l2_fmtdesc *f, return 0; } -static int vidioc_enum_fmt_vid_cap(struct file *file, void *pirv, - struct v4l2_fmtdesc *f) -{ - return vidioc_enum_fmt(file, f, false, false); -} - static int vidioc_enum_fmt_vid_cap_mplane(struct file *file, void *pirv, struct v4l2_fmtdesc *f) { - return vidioc_enum_fmt(file, f, true, false); -} - -static int vidioc_enum_fmt_vid_out(struct file *file, void *priv, - struct v4l2_fmtdesc *f) -{ - return vidioc_enum_fmt(file, f, false, true); + return vidioc_enum_fmt(file, f, false); } static int vidioc_enum_fmt_vid_out_mplane(struct file *file, void *priv, struct v4l2_fmtdesc *f) { - return vidioc_enum_fmt(file, f, true, true); + return vidioc_enum_fmt(file, f, true); } /* Get format */ @@ -543,7 +527,7 @@ static int reqbufs_capture(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx, ret = vb2_reqbufs(&ctx->vq_dst, reqbufs); if (ret) goto out; - s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx); + s5p_mfc_hw_call_void(dev->mfc_ops, release_codec_buffers, ctx); ctx->dst_bufs_cnt = 0; } else if (ctx->capture_state == QUEUE_FREE) { WARN_ON(ctx->dst_bufs_cnt != 0); @@ -571,7 +555,7 @@ static int reqbufs_capture(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx, if (s5p_mfc_ctx_ready(ctx)) set_work_bit_irqsave(ctx); - s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); s5p_mfc_wait_for_done_ctx(ctx, S5P_MFC_R2H_CMD_INIT_BUFFERS_RET, 0); } else { @@ -823,8 +807,8 @@ static int vidioc_g_crop(struct file *file, void *priv, return 0; } -int vidioc_decoder_cmd(struct file *file, void *priv, - struct v4l2_decoder_cmd *cmd) +static int vidioc_decoder_cmd(struct file *file, void *priv, + struct v4l2_decoder_cmd *cmd) { struct s5p_mfc_ctx *ctx = fh_to_ctx(priv); struct s5p_mfc_dev *dev = ctx->dev; @@ -846,7 +830,7 @@ int vidioc_decoder_cmd(struct file *file, void *priv, if (s5p_mfc_ctx_ready(ctx)) set_work_bit_irqsave(ctx); spin_unlock_irqrestore(&dev->irqlock, flags); - s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); } else { mfc_err("EOS: marking last buffer of stream"); buf = list_entry(ctx->src_queue.prev, @@ -881,9 +865,7 @@ static int vidioc_subscribe_event(struct v4l2_fh *fh, /* v4l2_ioctl_ops */ static const struct v4l2_ioctl_ops s5p_mfc_dec_ioctl_ops = { .vidioc_querycap = vidioc_querycap, - .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, .vidioc_enum_fmt_vid_cap_mplane = vidioc_enum_fmt_vid_cap_mplane, - .vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out, .vidioc_enum_fmt_vid_out_mplane = vidioc_enum_fmt_vid_out_mplane, .vidioc_g_fmt_vid_cap_mplane = vidioc_g_fmt, .vidioc_g_fmt_vid_out_mplane = vidioc_g_fmt, @@ -990,7 +972,7 @@ static int s5p_mfc_buf_init(struct vb2_buffer *vb) if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { if (ctx->capture_state == QUEUE_BUFS_MMAPED) return 0; - for (i = 0; i <= ctx->src_fmt->num_planes ; i++) { + for (i = 0; i < ctx->dst_fmt->num_planes; i++) { if (IS_ERR_OR_NULL(ERR_PTR( vb2_dma_contig_plane_dma_addr(vb, i)))) { mfc_err("Plane mem not allocated\n"); @@ -1044,7 +1026,7 @@ static int s5p_mfc_start_streaming(struct vb2_queue *q, unsigned int count) /* If context is ready then dev = work->data;schedule it to run */ if (s5p_mfc_ctx_ready(ctx)) set_work_bit_irqsave(ctx); - s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); return 0; } @@ -1065,8 +1047,8 @@ static void s5p_mfc_stop_streaming(struct vb2_queue *q) } if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { spin_lock_irqsave(&dev->irqlock, flags); - s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue, - &ctx->vq_dst); + s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue, + &ctx->dst_queue, &ctx->vq_dst); INIT_LIST_HEAD(&ctx->dst_queue); ctx->dst_queue_cnt = 0; ctx->dpb_flush_flag = 1; @@ -1076,7 +1058,7 @@ static void s5p_mfc_stop_streaming(struct vb2_queue *q) ctx->state = MFCINST_FLUSH; set_work_bit_irqsave(ctx); s5p_mfc_clean_ctx_int_flags(ctx); - s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); if (s5p_mfc_wait_for_done_ctx(ctx, S5P_MFC_R2H_CMD_DPB_FLUSH_RET, 0)) mfc_err("Err flushing buffers\n"); @@ -1084,8 +1066,8 @@ static void s5p_mfc_stop_streaming(struct vb2_queue *q) } if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { spin_lock_irqsave(&dev->irqlock, flags); - s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue, - &ctx->vq_src); + s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue, + &ctx->src_queue, &ctx->vq_src); INIT_LIST_HEAD(&ctx->src_queue); ctx->src_queue_cnt = 0; spin_unlock_irqrestore(&dev->irqlock, flags); @@ -1124,7 +1106,7 @@ static void s5p_mfc_buf_queue(struct vb2_buffer *vb) } if (s5p_mfc_ctx_ready(ctx)) set_work_bit_irqsave(ctx); - s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); } static struct vb2_ops s5p_mfc_dec_qops = { @@ -1220,7 +1202,7 @@ void s5p_mfc_dec_init(struct s5p_mfc_ctx *ctx) else f.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_NV12MT; ctx->dst_fmt = find_format(&f, MFC_FMT_RAW); - mfc_debug(2, "Default src_fmt is %x, dest_fmt is %x\n", - (unsigned int)ctx->src_fmt, (unsigned int)ctx->dst_fmt); + mfc_debug(2, "Default src_fmt is %p, dest_fmt is %p\n", + ctx->src_fmt, ctx->dst_fmt); } diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c index d26b2484ca10..a904a1c7bb21 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c @@ -739,14 +739,11 @@ static int s5p_mfc_ctx_ready(struct s5p_mfc_ctx *ctx) static void cleanup_ref_queue(struct s5p_mfc_ctx *ctx) { struct s5p_mfc_buf *mb_entry; - unsigned long mb_y_addr, mb_c_addr; /* move buffers in ref queue to src queue */ while (!list_empty(&ctx->ref_queue)) { mb_entry = list_entry((&ctx->ref_queue)->next, struct s5p_mfc_buf, list); - mb_y_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 0); - mb_c_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 1); list_del(&mb_entry->list); ctx->ref_queue_cnt--; list_add_tail(&mb_entry->list, &ctx->src_queue); @@ -770,7 +767,7 @@ static int enc_pre_seq_start(struct s5p_mfc_ctx *ctx) dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list); dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0); dst_size = vb2_plane_size(dst_mb->b, 0); - s5p_mfc_hw_call(dev->mfc_ops, set_enc_stream_buffer, ctx, dst_addr, + s5p_mfc_hw_call_void(dev->mfc_ops, set_enc_stream_buffer, ctx, dst_addr, dst_size); spin_unlock_irqrestore(&dev->irqlock, flags); return 0; @@ -803,7 +800,7 @@ static int enc_post_seq_start(struct s5p_mfc_ctx *ctx) ctx->state = MFCINST_RUNNING; if (s5p_mfc_ctx_ready(ctx)) set_work_bit_irqsave(ctx); - s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); } else { enc_pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_enc_dpb_count, dev); @@ -828,15 +825,15 @@ static int enc_pre_frame_start(struct s5p_mfc_ctx *ctx) src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); src_y_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 0); src_c_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 1); - s5p_mfc_hw_call(dev->mfc_ops, set_enc_frame_buffer, ctx, src_y_addr, - src_c_addr); + s5p_mfc_hw_call_void(dev->mfc_ops, set_enc_frame_buffer, ctx, + src_y_addr, src_c_addr); spin_unlock_irqrestore(&dev->irqlock, flags); spin_lock_irqsave(&dev->irqlock, flags); dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list); dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0); dst_size = vb2_plane_size(dst_mb->b, 0); - s5p_mfc_hw_call(dev->mfc_ops, set_enc_stream_buffer, ctx, dst_addr, + s5p_mfc_hw_call_void(dev->mfc_ops, set_enc_stream_buffer, ctx, dst_addr, dst_size); spin_unlock_irqrestore(&dev->irqlock, flags); @@ -861,7 +858,7 @@ static int enc_post_frame_start(struct s5p_mfc_ctx *ctx) mfc_read(dev, S5P_FIMV_ENC_SI_PIC_CNT)); spin_lock_irqsave(&dev->irqlock, flags); if (slice_type >= 0) { - s5p_mfc_hw_call(dev->mfc_ops, get_enc_frame_buffer, ctx, + s5p_mfc_hw_call_void(dev->mfc_ops, get_enc_frame_buffer, ctx, &enc_y_addr, &enc_c_addr); list_for_each_entry(mb_entry, &ctx->src_queue, list) { mb_y_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 0); @@ -954,17 +951,13 @@ static int vidioc_querycap(struct file *file, void *priv, } static int vidioc_enum_fmt(struct file *file, struct v4l2_fmtdesc *f, - bool mplane, bool out) + bool out) { struct s5p_mfc_dev *dev = video_drvdata(file); struct s5p_mfc_fmt *fmt; int i, j = 0; for (i = 0; i < ARRAY_SIZE(formats); ++i) { - if (mplane && formats[i].num_planes == 1) - continue; - else if (!mplane && formats[i].num_planes > 1) - continue; if (out && formats[i].type != MFC_FMT_RAW) continue; else if (!out && formats[i].type != MFC_FMT_ENC) @@ -984,28 +977,16 @@ static int vidioc_enum_fmt(struct file *file, struct v4l2_fmtdesc *f, return -EINVAL; } -static int vidioc_enum_fmt_vid_cap(struct file *file, void *pirv, - struct v4l2_fmtdesc *f) -{ - return vidioc_enum_fmt(file, f, false, false); -} - static int vidioc_enum_fmt_vid_cap_mplane(struct file *file, void *pirv, struct v4l2_fmtdesc *f) { - return vidioc_enum_fmt(file, f, true, false); -} - -static int vidioc_enum_fmt_vid_out(struct file *file, void *prov, - struct v4l2_fmtdesc *f) -{ - return vidioc_enum_fmt(file, f, false, true); + return vidioc_enum_fmt(file, f, false); } static int vidioc_enum_fmt_vid_out_mplane(struct file *file, void *prov, struct v4l2_fmtdesc *f) { - return vidioc_enum_fmt(file, f, true, true); + return vidioc_enum_fmt(file, f, true); } static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f) @@ -1127,7 +1108,7 @@ static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f) pix_fmt_mp->width, pix_fmt_mp->height, ctx->img_width, ctx->img_height); - s5p_mfc_hw_call(dev->mfc_ops, enc_calc_src_size, ctx); + s5p_mfc_hw_call_void(dev->mfc_ops, enc_calc_src_size, ctx); pix_fmt_mp->plane_fmt[0].sizeimage = ctx->luma_size; pix_fmt_mp->plane_fmt[0].bytesperline = ctx->buf_width; pix_fmt_mp->plane_fmt[1].sizeimage = ctx->chroma_size; @@ -1681,8 +1662,8 @@ static int vidioc_g_parm(struct file *file, void *priv, return 0; } -int vidioc_encoder_cmd(struct file *file, void *priv, - struct v4l2_encoder_cmd *cmd) +static int vidioc_encoder_cmd(struct file *file, void *priv, + struct v4l2_encoder_cmd *cmd) { struct s5p_mfc_ctx *ctx = fh_to_ctx(priv); struct s5p_mfc_dev *dev = ctx->dev; @@ -1704,7 +1685,7 @@ int vidioc_encoder_cmd(struct file *file, void *priv, if (s5p_mfc_ctx_ready(ctx)) set_work_bit_irqsave(ctx); spin_unlock_irqrestore(&dev->irqlock, flags); - s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); } else { mfc_debug(2, "EOS: marking last buffer of stream\n"); buf = list_entry(ctx->src_queue.prev, @@ -1736,9 +1717,7 @@ static int vidioc_subscribe_event(struct v4l2_fh *fh, static const struct v4l2_ioctl_ops s5p_mfc_enc_ioctl_ops = { .vidioc_querycap = vidioc_querycap, - .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, .vidioc_enum_fmt_vid_cap_mplane = vidioc_enum_fmt_vid_cap_mplane, - .vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out, .vidioc_enum_fmt_vid_out_mplane = vidioc_enum_fmt_vid_out_mplane, .vidioc_g_fmt_vid_cap_mplane = vidioc_g_fmt, .vidioc_g_fmt_vid_out_mplane = vidioc_g_fmt, @@ -1771,13 +1750,13 @@ static int check_vb_with_fmt(struct s5p_mfc_fmt *fmt, struct vb2_buffer *vb) return -EINVAL; } for (i = 0; i < fmt->num_planes; i++) { - if (!vb2_dma_contig_plane_dma_addr(vb, i)) { + dma_addr_t dma = vb2_dma_contig_plane_dma_addr(vb, i); + if (!dma) { mfc_err("failed to get plane cookie\n"); return -EINVAL; } - mfc_debug(2, "index: %d, plane[%d] cookie: 0x%08zx\n", - vb->v4l2_buf.index, i, - vb2_dma_contig_plane_dma_addr(vb, i)); + mfc_debug(2, "index: %d, plane[%d] cookie: %pad\n", + vb->v4l2_buf.index, i, &dma); } return 0; } @@ -1897,7 +1876,7 @@ static int s5p_mfc_buf_prepare(struct vb2_buffer *vb) ret = check_vb_with_fmt(ctx->dst_fmt, vb); if (ret < 0) return ret; - mfc_debug(2, "plane size: %ld, dst size: %d\n", + mfc_debug(2, "plane size: %ld, dst size: %zu\n", vb2_plane_size(vb, 0), ctx->enc_dst_buf_size); if (vb2_plane_size(vb, 0) < ctx->enc_dst_buf_size) { mfc_err("plane size is too small for capture\n"); @@ -1948,7 +1927,7 @@ static int s5p_mfc_start_streaming(struct vb2_queue *q, unsigned int count) /* If context is ready then dev = work->data;schedule it to run */ if (s5p_mfc_ctx_ready(ctx)) set_work_bit_irqsave(ctx); - s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); return 0; } @@ -1969,14 +1948,14 @@ static void s5p_mfc_stop_streaming(struct vb2_queue *q) ctx->state = MFCINST_FINISHED; spin_lock_irqsave(&dev->irqlock, flags); if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { - s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue, - &ctx->vq_dst); + s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue, + &ctx->dst_queue, &ctx->vq_dst); INIT_LIST_HEAD(&ctx->dst_queue); ctx->dst_queue_cnt = 0; } if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { cleanup_ref_queue(ctx); - s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue, + s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue, &ctx->src_queue, &ctx->vq_src); INIT_LIST_HEAD(&ctx->src_queue); ctx->src_queue_cnt = 0; @@ -2017,7 +1996,7 @@ static void s5p_mfc_buf_queue(struct vb2_buffer *vb) } if (s5p_mfc_ctx_ready(ctx)) set_work_bit_irqsave(ctx); - s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); + s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); } static struct vb2_ops s5p_mfc_enc_qops = { diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.c index c9a227428e6a..00a1d8b2a8c2 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.c @@ -41,7 +41,7 @@ int s5p_mfc_alloc_priv_buf(struct device *dev, struct s5p_mfc_priv_buf *b) { - mfc_debug(3, "Allocating priv: %d\n", b->size); + mfc_debug(3, "Allocating priv: %zu\n", b->size); b->virt = dma_alloc_coherent(dev, b->size, &b->dma, GFP_KERNEL); @@ -50,7 +50,7 @@ int s5p_mfc_alloc_priv_buf(struct device *dev, return -ENOMEM; } - mfc_debug(3, "Allocated addr %p %08x\n", b->virt, b->dma); + mfc_debug(3, "Allocated addr %p %pad\n", b->virt, &b->dma); return 0; } diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h index 7a7ad32ee608..de2b8c69daa5 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h @@ -20,254 +20,254 @@ struct s5p_mfc_regs { /* codec common registers */ - void *risc_on; - void *risc2host_int; - void *host2risc_int; - void *risc_base_address; - void *mfc_reset; - void *host2risc_command; - void *risc2host_command; - void *mfc_bus_reset_ctrl; - void *firmware_version; - void *instance_id; - void *codec_type; - void *context_mem_addr; - void *context_mem_size; - void *pixel_format; - void *metadata_enable; - void *mfc_version; - void *dbg_info_enable; - void *dbg_buffer_addr; - void *dbg_buffer_size; - void *hed_control; - void *mfc_timeout_value; - void *hed_shared_mem_addr; - void *dis_shared_mem_addr;/* only v7 */ - void *ret_instance_id; - void *error_code; - void *dbg_buffer_output_size; - void *metadata_status; - void *metadata_addr_mb_info; - void *metadata_size_mb_info; - void *dbg_info_stage_counter; + volatile void __iomem *risc_on; + volatile void __iomem *risc2host_int; + volatile void __iomem *host2risc_int; + volatile void __iomem *risc_base_address; + volatile void __iomem *mfc_reset; + volatile void __iomem *host2risc_command; + volatile void __iomem *risc2host_command; + volatile void __iomem *mfc_bus_reset_ctrl; + volatile void __iomem *firmware_version; + volatile void __iomem *instance_id; + volatile void __iomem *codec_type; + volatile void __iomem *context_mem_addr; + volatile void __iomem *context_mem_size; + volatile void __iomem *pixel_format; + volatile void __iomem *metadata_enable; + volatile void __iomem *mfc_version; + volatile void __iomem *dbg_info_enable; + volatile void __iomem *dbg_buffer_addr; + volatile void __iomem *dbg_buffer_size; + volatile void __iomem *hed_control; + volatile void __iomem *mfc_timeout_value; + volatile void __iomem *hed_shared_mem_addr; + volatile void __iomem *dis_shared_mem_addr;/* only v7 */ + volatile void __iomem *ret_instance_id; + volatile void __iomem *error_code; + volatile void __iomem *dbg_buffer_output_size; + volatile void __iomem *metadata_status; + volatile void __iomem *metadata_addr_mb_info; + volatile void __iomem *metadata_size_mb_info; + volatile void __iomem *dbg_info_stage_counter; /* decoder registers */ - void *d_crc_ctrl; - void *d_dec_options; - void *d_display_delay; - void *d_set_frame_width; - void *d_set_frame_height; - void *d_sei_enable; - void *d_min_num_dpb; - void *d_min_first_plane_dpb_size; - void *d_min_second_plane_dpb_size; - void *d_min_third_plane_dpb_size;/* only v8 */ - void *d_min_num_mv; - void *d_mvc_num_views; - void *d_min_num_dis;/* only v7 */ - void *d_min_first_dis_size;/* only v7 */ - void *d_min_second_dis_size;/* only v7 */ - void *d_min_third_dis_size;/* only v7 */ - void *d_post_filter_luma_dpb0;/* v7 and v8 */ - void *d_post_filter_luma_dpb1;/* v7 and v8 */ - void *d_post_filter_luma_dpb2;/* only v7 */ - void *d_post_filter_chroma_dpb0;/* v7 and v8 */ - void *d_post_filter_chroma_dpb1;/* v7 and v8 */ - void *d_post_filter_chroma_dpb2;/* only v7 */ - void *d_num_dpb; - void *d_num_mv; - void *d_init_buffer_options; - void *d_first_plane_dpb_stride_size;/* only v8 */ - void *d_second_plane_dpb_stride_size;/* only v8 */ - void *d_third_plane_dpb_stride_size;/* only v8 */ - void *d_first_plane_dpb_size; - void *d_second_plane_dpb_size; - void *d_third_plane_dpb_size;/* only v8 */ - void *d_mv_buffer_size; - void *d_first_plane_dpb; - void *d_second_plane_dpb; - void *d_third_plane_dpb; - void *d_mv_buffer; - void *d_scratch_buffer_addr; - void *d_scratch_buffer_size; - void *d_metadata_buffer_addr; - void *d_metadata_buffer_size; - void *d_nal_start_options;/* v7 and v8 */ - void *d_cpb_buffer_addr; - void *d_cpb_buffer_size; - void *d_available_dpb_flag_upper; - void *d_available_dpb_flag_lower; - void *d_cpb_buffer_offset; - void *d_slice_if_enable; - void *d_picture_tag; - void *d_stream_data_size; - void *d_dynamic_dpb_flag_upper;/* v7 and v8 */ - void *d_dynamic_dpb_flag_lower;/* v7 and v8 */ - void *d_display_frame_width; - void *d_display_frame_height; - void *d_display_status; - void *d_display_first_plane_addr; - void *d_display_second_plane_addr; - void *d_display_third_plane_addr;/* only v8 */ - void *d_display_frame_type; - void *d_display_crop_info1; - void *d_display_crop_info2; - void *d_display_picture_profile; - void *d_display_luma_crc;/* v7 and v8 */ - void *d_display_chroma0_crc;/* v7 and v8 */ - void *d_display_chroma1_crc;/* only v8 */ - void *d_display_luma_crc_top;/* only v6 */ - void *d_display_chroma_crc_top;/* only v6 */ - void *d_display_luma_crc_bot;/* only v6 */ - void *d_display_chroma_crc_bot;/* only v6 */ - void *d_display_aspect_ratio; - void *d_display_extended_ar; - void *d_decoded_frame_width; - void *d_decoded_frame_height; - void *d_decoded_status; - void *d_decoded_first_plane_addr; - void *d_decoded_second_plane_addr; - void *d_decoded_third_plane_addr;/* only v8 */ - void *d_decoded_frame_type; - void *d_decoded_crop_info1; - void *d_decoded_crop_info2; - void *d_decoded_picture_profile; - void *d_decoded_nal_size; - void *d_decoded_luma_crc; - void *d_decoded_chroma0_crc; - void *d_decoded_chroma1_crc;/* only v8 */ - void *d_ret_picture_tag_top; - void *d_ret_picture_tag_bot; - void *d_ret_picture_time_top; - void *d_ret_picture_time_bot; - void *d_chroma_format; - void *d_vc1_info;/* v7 and v8 */ - void *d_mpeg4_info; - void *d_h264_info; - void *d_metadata_addr_concealed_mb; - void *d_metadata_size_concealed_mb; - void *d_metadata_addr_vc1_param; - void *d_metadata_size_vc1_param; - void *d_metadata_addr_sei_nal; - void *d_metadata_size_sei_nal; - void *d_metadata_addr_vui; - void *d_metadata_size_vui; - void *d_metadata_addr_mvcvui;/* v7 and v8 */ - void *d_metadata_size_mvcvui;/* v7 and v8 */ - void *d_mvc_view_id; - void *d_frame_pack_sei_avail; - void *d_frame_pack_arrgment_id; - void *d_frame_pack_sei_info; - void *d_frame_pack_grid_pos; - void *d_display_recovery_sei_info;/* v7 and v8 */ - void *d_decoded_recovery_sei_info;/* v7 and v8 */ - void *d_display_first_addr;/* only v7 */ - void *d_display_second_addr;/* only v7 */ - void *d_display_third_addr;/* only v7 */ - void *d_decoded_first_addr;/* only v7 */ - void *d_decoded_second_addr;/* only v7 */ - void *d_decoded_third_addr;/* only v7 */ - void *d_used_dpb_flag_upper;/* v7 and v8 */ - void *d_used_dpb_flag_lower;/* v7 and v8 */ + volatile void __iomem *d_crc_ctrl; + volatile void __iomem *d_dec_options; + volatile void __iomem *d_display_delay; + volatile void __iomem *d_set_frame_width; + volatile void __iomem *d_set_frame_height; + volatile void __iomem *d_sei_enable; + volatile void __iomem *d_min_num_dpb; + volatile void __iomem *d_min_first_plane_dpb_size; + volatile void __iomem *d_min_second_plane_dpb_size; + volatile void __iomem *d_min_third_plane_dpb_size;/* only v8 */ + volatile void __iomem *d_min_num_mv; + volatile void __iomem *d_mvc_num_views; + volatile void __iomem *d_min_num_dis;/* only v7 */ + volatile void __iomem *d_min_first_dis_size;/* only v7 */ + volatile void __iomem *d_min_second_dis_size;/* only v7 */ + volatile void __iomem *d_min_third_dis_size;/* only v7 */ + volatile void __iomem *d_post_filter_luma_dpb0;/* v7 and v8 */ + volatile void __iomem *d_post_filter_luma_dpb1;/* v7 and v8 */ + volatile void __iomem *d_post_filter_luma_dpb2;/* only v7 */ + volatile void __iomem *d_post_filter_chroma_dpb0;/* v7 and v8 */ + volatile void __iomem *d_post_filter_chroma_dpb1;/* v7 and v8 */ + volatile void __iomem *d_post_filter_chroma_dpb2;/* only v7 */ + volatile void __iomem *d_num_dpb; + volatile void __iomem *d_num_mv; + volatile void __iomem *d_init_buffer_options; + volatile void __iomem *d_first_plane_dpb_stride_size;/* only v8 */ + volatile void __iomem *d_second_plane_dpb_stride_size;/* only v8 */ + volatile void __iomem *d_third_plane_dpb_stride_size;/* only v8 */ + volatile void __iomem *d_first_plane_dpb_size; + volatile void __iomem *d_second_plane_dpb_size; + volatile void __iomem *d_third_plane_dpb_size;/* only v8 */ + volatile void __iomem *d_mv_buffer_size; + volatile void __iomem *d_first_plane_dpb; + volatile void __iomem *d_second_plane_dpb; + volatile void __iomem *d_third_plane_dpb; + volatile void __iomem *d_mv_buffer; + volatile void __iomem *d_scratch_buffer_addr; + volatile void __iomem *d_scratch_buffer_size; + volatile void __iomem *d_metadata_buffer_addr; + volatile void __iomem *d_metadata_buffer_size; + volatile void __iomem *d_nal_start_options;/* v7 and v8 */ + volatile void __iomem *d_cpb_buffer_addr; + volatile void __iomem *d_cpb_buffer_size; + volatile void __iomem *d_available_dpb_flag_upper; + volatile void __iomem *d_available_dpb_flag_lower; + volatile void __iomem *d_cpb_buffer_offset; + volatile void __iomem *d_slice_if_enable; + volatile void __iomem *d_picture_tag; + volatile void __iomem *d_stream_data_size; + volatile void __iomem *d_dynamic_dpb_flag_upper;/* v7 and v8 */ + volatile void __iomem *d_dynamic_dpb_flag_lower;/* v7 and v8 */ + volatile void __iomem *d_display_frame_width; + volatile void __iomem *d_display_frame_height; + volatile void __iomem *d_display_status; + volatile void __iomem *d_display_first_plane_addr; + volatile void __iomem *d_display_second_plane_addr; + volatile void __iomem *d_display_third_plane_addr;/* only v8 */ + volatile void __iomem *d_display_frame_type; + volatile void __iomem *d_display_crop_info1; + volatile void __iomem *d_display_crop_info2; + volatile void __iomem *d_display_picture_profile; + volatile void __iomem *d_display_luma_crc;/* v7 and v8 */ + volatile void __iomem *d_display_chroma0_crc;/* v7 and v8 */ + volatile void __iomem *d_display_chroma1_crc;/* only v8 */ + volatile void __iomem *d_display_luma_crc_top;/* only v6 */ + volatile void __iomem *d_display_chroma_crc_top;/* only v6 */ + volatile void __iomem *d_display_luma_crc_bot;/* only v6 */ + volatile void __iomem *d_display_chroma_crc_bot;/* only v6 */ + volatile void __iomem *d_display_aspect_ratio; + volatile void __iomem *d_display_extended_ar; + volatile void __iomem *d_decoded_frame_width; + volatile void __iomem *d_decoded_frame_height; + volatile void __iomem *d_decoded_status; + volatile void __iomem *d_decoded_first_plane_addr; + volatile void __iomem *d_decoded_second_plane_addr; + volatile void __iomem *d_decoded_third_plane_addr;/* only v8 */ + volatile void __iomem *d_decoded_frame_type; + volatile void __iomem *d_decoded_crop_info1; + volatile void __iomem *d_decoded_crop_info2; + volatile void __iomem *d_decoded_picture_profile; + volatile void __iomem *d_decoded_nal_size; + volatile void __iomem *d_decoded_luma_crc; + volatile void __iomem *d_decoded_chroma0_crc; + volatile void __iomem *d_decoded_chroma1_crc;/* only v8 */ + volatile void __iomem *d_ret_picture_tag_top; + volatile void __iomem *d_ret_picture_tag_bot; + volatile void __iomem *d_ret_picture_time_top; + volatile void __iomem *d_ret_picture_time_bot; + volatile void __iomem *d_chroma_format; + volatile void __iomem *d_vc1_info;/* v7 and v8 */ + volatile void __iomem *d_mpeg4_info; + volatile void __iomem *d_h264_info; + volatile void __iomem *d_metadata_addr_concealed_mb; + volatile void __iomem *d_metadata_size_concealed_mb; + volatile void __iomem *d_metadata_addr_vc1_param; + volatile void __iomem *d_metadata_size_vc1_param; + volatile void __iomem *d_metadata_addr_sei_nal; + volatile void __iomem *d_metadata_size_sei_nal; + volatile void __iomem *d_metadata_addr_vui; + volatile void __iomem *d_metadata_size_vui; + volatile void __iomem *d_metadata_addr_mvcvui;/* v7 and v8 */ + volatile void __iomem *d_metadata_size_mvcvui;/* v7 and v8 */ + volatile void __iomem *d_mvc_view_id; + volatile void __iomem *d_frame_pack_sei_avail; + volatile void __iomem *d_frame_pack_arrgment_id; + volatile void __iomem *d_frame_pack_sei_info; + volatile void __iomem *d_frame_pack_grid_pos; + volatile void __iomem *d_display_recovery_sei_info;/* v7 and v8 */ + volatile void __iomem *d_decoded_recovery_sei_info;/* v7 and v8 */ + volatile void __iomem *d_display_first_addr;/* only v7 */ + volatile void __iomem *d_display_second_addr;/* only v7 */ + volatile void __iomem *d_display_third_addr;/* only v7 */ + volatile void __iomem *d_decoded_first_addr;/* only v7 */ + volatile void __iomem *d_decoded_second_addr;/* only v7 */ + volatile void __iomem *d_decoded_third_addr;/* only v7 */ + volatile void __iomem *d_used_dpb_flag_upper;/* v7 and v8 */ + volatile void __iomem *d_used_dpb_flag_lower;/* v7 and v8 */ /* encoder registers */ - void *e_frame_width; - void *e_frame_height; - void *e_cropped_frame_width; - void *e_cropped_frame_height; - void *e_frame_crop_offset; - void *e_enc_options; - void *e_picture_profile; - void *e_vbv_buffer_size; - void *e_vbv_init_delay; - void *e_fixed_picture_qp; - void *e_rc_config; - void *e_rc_qp_bound; - void *e_rc_qp_bound_pb;/* v7 and v8 */ - void *e_rc_mode; - void *e_mb_rc_config; - void *e_padding_ctrl; - void *e_air_threshold; - void *e_mv_hor_range; - void *e_mv_ver_range; - void *e_num_dpb; - void *e_luma_dpb; - void *e_chroma_dpb; - void *e_me_buffer; - void *e_scratch_buffer_addr; - void *e_scratch_buffer_size; - void *e_tmv_buffer0; - void *e_tmv_buffer1; - void *e_ir_buffer_addr;/* v7 and v8 */ - void *e_source_first_plane_addr; - void *e_source_second_plane_addr; - void *e_source_third_plane_addr;/* v7 and v8 */ - void *e_source_first_plane_stride;/* v7 and v8 */ - void *e_source_second_plane_stride;/* v7 and v8 */ - void *e_source_third_plane_stride;/* v7 and v8 */ - void *e_stream_buffer_addr; - void *e_stream_buffer_size; - void *e_roi_buffer_addr; - void *e_param_change; - void *e_ir_size; - void *e_gop_config; - void *e_mslice_mode; - void *e_mslice_size_mb; - void *e_mslice_size_bits; - void *e_frame_insertion; - void *e_rc_frame_rate; - void *e_rc_bit_rate; - void *e_rc_roi_ctrl; - void *e_picture_tag; - void *e_bit_count_enable; - void *e_max_bit_count; - void *e_min_bit_count; - void *e_metadata_buffer_addr; - void *e_metadata_buffer_size; - void *e_encoded_source_first_plane_addr; - void *e_encoded_source_second_plane_addr; - void *e_encoded_source_third_plane_addr;/* v7 and v8 */ - void *e_stream_size; - void *e_slice_type; - void *e_picture_count; - void *e_ret_picture_tag; - void *e_stream_buffer_write_pointer; /* only v6 */ - void *e_recon_luma_dpb_addr; - void *e_recon_chroma_dpb_addr; - void *e_metadata_addr_enc_slice; - void *e_metadata_size_enc_slice; - void *e_mpeg4_options; - void *e_mpeg4_hec_period; - void *e_aspect_ratio; - void *e_extended_sar; - void *e_h264_options; - void *e_h264_options_2;/* v7 and v8 */ - void *e_h264_lf_alpha_offset; - void *e_h264_lf_beta_offset; - void *e_h264_i_period; - void *e_h264_fmo_slice_grp_map_type; - void *e_h264_fmo_num_slice_grp_minus1; - void *e_h264_fmo_slice_grp_change_dir; - void *e_h264_fmo_slice_grp_change_rate_minus1; - void *e_h264_fmo_run_length_minus1_0; - void *e_h264_aso_slice_order_0; - void *e_h264_chroma_qp_offset; - void *e_h264_num_t_layer; - void *e_h264_hierarchical_qp_layer0; - void *e_h264_frame_packing_sei_info; - void *e_h264_nal_control;/* v7 and v8 */ - void *e_mvc_frame_qp_view1; - void *e_mvc_rc_bit_rate_view1; - void *e_mvc_rc_qbound_view1; - void *e_mvc_rc_mode_view1; - void *e_mvc_inter_view_prediction_on; - void *e_vp8_options;/* v7 and v8 */ - void *e_vp8_filter_options;/* v7 and v8 */ - void *e_vp8_golden_frame_option;/* v7 and v8 */ - void *e_vp8_num_t_layer;/* v7 and v8 */ - void *e_vp8_hierarchical_qp_layer0;/* v7 and v8 */ - void *e_vp8_hierarchical_qp_layer1;/* v7 and v8 */ - void *e_vp8_hierarchical_qp_layer2;/* v7 and v8 */ + volatile void __iomem *e_frame_width; + volatile void __iomem *e_frame_height; + volatile void __iomem *e_cropped_frame_width; + volatile void __iomem *e_cropped_frame_height; + volatile void __iomem *e_frame_crop_offset; + volatile void __iomem *e_enc_options; + volatile void __iomem *e_picture_profile; + volatile void __iomem *e_vbv_buffer_size; + volatile void __iomem *e_vbv_init_delay; + volatile void __iomem *e_fixed_picture_qp; + volatile void __iomem *e_rc_config; + volatile void __iomem *e_rc_qp_bound; + volatile void __iomem *e_rc_qp_bound_pb;/* v7 and v8 */ + volatile void __iomem *e_rc_mode; + volatile void __iomem *e_mb_rc_config; + volatile void __iomem *e_padding_ctrl; + volatile void __iomem *e_air_threshold; + volatile void __iomem *e_mv_hor_range; + volatile void __iomem *e_mv_ver_range; + volatile void __iomem *e_num_dpb; + volatile void __iomem *e_luma_dpb; + volatile void __iomem *e_chroma_dpb; + volatile void __iomem *e_me_buffer; + volatile void __iomem *e_scratch_buffer_addr; + volatile void __iomem *e_scratch_buffer_size; + volatile void __iomem *e_tmv_buffer0; + volatile void __iomem *e_tmv_buffer1; + volatile void __iomem *e_ir_buffer_addr;/* v7 and v8 */ + volatile void __iomem *e_source_first_plane_addr; + volatile void __iomem *e_source_second_plane_addr; + volatile void __iomem *e_source_third_plane_addr;/* v7 and v8 */ + volatile void __iomem *e_source_first_plane_stride;/* v7 and v8 */ + volatile void __iomem *e_source_second_plane_stride;/* v7 and v8 */ + volatile void __iomem *e_source_third_plane_stride;/* v7 and v8 */ + volatile void __iomem *e_stream_buffer_addr; + volatile void __iomem *e_stream_buffer_size; + volatile void __iomem *e_roi_buffer_addr; + volatile void __iomem *e_param_change; + volatile void __iomem *e_ir_size; + volatile void __iomem *e_gop_config; + volatile void __iomem *e_mslice_mode; + volatile void __iomem *e_mslice_size_mb; + volatile void __iomem *e_mslice_size_bits; + volatile void __iomem *e_frame_insertion; + volatile void __iomem *e_rc_frame_rate; + volatile void __iomem *e_rc_bit_rate; + volatile void __iomem *e_rc_roi_ctrl; + volatile void __iomem *e_picture_tag; + volatile void __iomem *e_bit_count_enable; + volatile void __iomem *e_max_bit_count; + volatile void __iomem *e_min_bit_count; + volatile void __iomem *e_metadata_buffer_addr; + volatile void __iomem *e_metadata_buffer_size; + volatile void __iomem *e_encoded_source_first_plane_addr; + volatile void __iomem *e_encoded_source_second_plane_addr; + volatile void __iomem *e_encoded_source_third_plane_addr;/* v7 and v8 */ + volatile void __iomem *e_stream_size; + volatile void __iomem *e_slice_type; + volatile void __iomem *e_picture_count; + volatile void __iomem *e_ret_picture_tag; + volatile void __iomem *e_stream_buffer_write_pointer; /* only v6 */ + volatile void __iomem *e_recon_luma_dpb_addr; + volatile void __iomem *e_recon_chroma_dpb_addr; + volatile void __iomem *e_metadata_addr_enc_slice; + volatile void __iomem *e_metadata_size_enc_slice; + volatile void __iomem *e_mpeg4_options; + volatile void __iomem *e_mpeg4_hec_period; + volatile void __iomem *e_aspect_ratio; + volatile void __iomem *e_extended_sar; + volatile void __iomem *e_h264_options; + volatile void __iomem *e_h264_options_2;/* v7 and v8 */ + volatile void __iomem *e_h264_lf_alpha_offset; + volatile void __iomem *e_h264_lf_beta_offset; + volatile void __iomem *e_h264_i_period; + volatile void __iomem *e_h264_fmo_slice_grp_map_type; + volatile void __iomem *e_h264_fmo_num_slice_grp_minus1; + volatile void __iomem *e_h264_fmo_slice_grp_change_dir; + volatile void __iomem *e_h264_fmo_slice_grp_change_rate_minus1; + volatile void __iomem *e_h264_fmo_run_length_minus1_0; + volatile void __iomem *e_h264_aso_slice_order_0; + volatile void __iomem *e_h264_chroma_qp_offset; + volatile void __iomem *e_h264_num_t_layer; + volatile void __iomem *e_h264_hierarchical_qp_layer0; + volatile void __iomem *e_h264_frame_packing_sei_info; + volatile void __iomem *e_h264_nal_control;/* v7 and v8 */ + volatile void __iomem *e_mvc_frame_qp_view1; + volatile void __iomem *e_mvc_rc_bit_rate_view1; + volatile void __iomem *e_mvc_rc_qbound_view1; + volatile void __iomem *e_mvc_rc_mode_view1; + volatile void __iomem *e_mvc_inter_view_prediction_on; + volatile void __iomem *e_vp8_options;/* v7 and v8 */ + volatile void __iomem *e_vp8_filter_options;/* v7 and v8 */ + volatile void __iomem *e_vp8_golden_frame_option;/* v7 and v8 */ + volatile void __iomem *e_vp8_num_t_layer;/* v7 and v8 */ + volatile void __iomem *e_vp8_hierarchical_qp_layer0;/* v7 and v8 */ + volatile void __iomem *e_vp8_hierarchical_qp_layer1;/* v7 and v8 */ + volatile void __iomem *e_vp8_hierarchical_qp_layer2;/* v7 and v8 */ }; struct s5p_mfc_hw_ops { diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c index 58ec7bb26ebc..7cf07963187d 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c @@ -228,6 +228,7 @@ static int s5p_mfc_alloc_instance_buffer_v5(struct s5p_mfc_ctx *ctx) ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->shm); if (ret) { mfc_err("Failed to allocate shared memory buffer\n"); + s5p_mfc_release_priv_buf(dev->mem_dev_l, &ctx->ctx); return ret; } @@ -262,7 +263,7 @@ static void s5p_mfc_release_dev_context_buffer_v5(struct s5p_mfc_dev *dev) static void s5p_mfc_write_info_v5(struct s5p_mfc_ctx *ctx, unsigned int data, unsigned int ofs) { - writel(data, (ctx->shm.virt + ofs)); + writel(data, (volatile void __iomem *)(ctx->shm.virt + ofs)); wmb(); } @@ -270,7 +271,7 @@ static unsigned int s5p_mfc_read_info_v5(struct s5p_mfc_ctx *ctx, unsigned int ofs) { rmb(); - return readl(ctx->shm.virt + ofs); + return readl((volatile void __iomem *)(ctx->shm.virt + ofs)); } static void s5p_mfc_dec_calc_dpb_size_v5(struct s5p_mfc_ctx *ctx) @@ -377,7 +378,7 @@ static int s5p_mfc_set_dec_stream_buffer_v5(struct s5p_mfc_ctx *ctx, /* Set decoding frame buffer */ static int s5p_mfc_set_dec_frame_buffer_v5(struct s5p_mfc_ctx *ctx) { - unsigned int frame_size, i; + unsigned int frame_size_lu, i; unsigned int frame_size_ch, frame_size_mv; struct s5p_mfc_dev *dev = ctx->dev; unsigned int dpb; @@ -465,23 +466,23 @@ static int s5p_mfc_set_dec_frame_buffer_v5(struct s5p_mfc_ctx *ctx) ctx->codec_mode); return -EINVAL; } - frame_size = ctx->luma_size; + frame_size_lu = ctx->luma_size; frame_size_ch = ctx->chroma_size; frame_size_mv = ctx->mv_size; - mfc_debug(2, "Frm size: %d ch: %d mv: %d\n", frame_size, frame_size_ch, + mfc_debug(2, "Frm size: %d ch: %d mv: %d\n", frame_size_lu, frame_size_ch, frame_size_mv); for (i = 0; i < ctx->total_dpb_count; i++) { /* Bank2 */ - mfc_debug(2, "Luma %d: %x\n", i, + mfc_debug(2, "Luma %d: %zx\n", i, ctx->dst_bufs[i].cookie.raw.luma); mfc_write(dev, OFFSETB(ctx->dst_bufs[i].cookie.raw.luma), S5P_FIMV_DEC_LUMA_ADR + i * 4); - mfc_debug(2, "\tChroma %d: %x\n", i, + mfc_debug(2, "\tChroma %d: %zx\n", i, ctx->dst_bufs[i].cookie.raw.chroma); mfc_write(dev, OFFSETA(ctx->dst_bufs[i].cookie.raw.chroma), S5P_FIMV_DEC_CHROMA_ADR + i * 4); if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC) { - mfc_debug(2, "\tBuf2: %x, size: %d\n", + mfc_debug(2, "\tBuf2: %zx, size: %d\n", buf_addr2, buf_size2); mfc_write(dev, OFFSETB(buf_addr2), S5P_FIMV_H264_MV_ADR + i * 4); @@ -489,14 +490,14 @@ static int s5p_mfc_set_dec_frame_buffer_v5(struct s5p_mfc_ctx *ctx) buf_size2 -= frame_size_mv; } } - mfc_debug(2, "Buf1: %u, buf_size1: %d\n", buf_addr1, buf_size1); + mfc_debug(2, "Buf1: %zu, buf_size1: %d\n", buf_addr1, buf_size1); mfc_debug(2, "Buf 1/2 size after: %d/%d (frames %d)\n", buf_size1, buf_size2, ctx->total_dpb_count); if (buf_size1 < 0 || buf_size2 < 0) { mfc_debug(2, "Not enough memory has been allocated\n"); return -ENOMEM; } - s5p_mfc_write_info_v5(ctx, frame_size, ALLOC_LUMA_DPB_SIZE); + s5p_mfc_write_info_v5(ctx, frame_size_lu, ALLOC_LUMA_DPB_SIZE); s5p_mfc_write_info_v5(ctx, frame_size_ch, ALLOC_CHROMA_DPB_SIZE); if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC) s5p_mfc_write_info_v5(ctx, frame_size_mv, ALLOC_MV_SIZE); @@ -566,7 +567,7 @@ static int s5p_mfc_set_enc_ref_buffer_v5(struct s5p_mfc_ctx *ctx) enc_ref_c_size = ALIGN(guard_width * guard_height, S5P_FIMV_NV12MT_SALIGN); } - mfc_debug(2, "buf_size1: %d, buf_size2: %d\n", buf_size1, buf_size2); + mfc_debug(2, "buf_size1: %zu, buf_size2: %zu\n", buf_size1, buf_size2); switch (ctx->codec_mode) { case S5P_MFC_CODEC_H264_ENC: for (i = 0; i < 2; i++) { @@ -605,7 +606,7 @@ static int s5p_mfc_set_enc_ref_buffer_v5(struct s5p_mfc_ctx *ctx) S5P_FIMV_H264_NBOR_INFO_ADR); buf_addr1 += S5P_FIMV_ENC_NBORINFO_SIZE; buf_size1 -= S5P_FIMV_ENC_NBORINFO_SIZE; - mfc_debug(2, "buf_size1: %d, buf_size2: %d\n", + mfc_debug(2, "buf_size1: %zu, buf_size2: %zu\n", buf_size1, buf_size2); break; case S5P_MFC_CODEC_MPEG4_ENC: @@ -636,7 +637,7 @@ static int s5p_mfc_set_enc_ref_buffer_v5(struct s5p_mfc_ctx *ctx) S5P_FIMV_MPEG4_ACDC_COEF_ADR); buf_addr1 += S5P_FIMV_ENC_ACDCCOEF_SIZE; buf_size1 -= S5P_FIMV_ENC_ACDCCOEF_SIZE; - mfc_debug(2, "buf_size1: %d, buf_size2: %d\n", + mfc_debug(2, "buf_size1: %zu, buf_size2: %zu\n", buf_size1, buf_size2); break; case S5P_MFC_CODEC_H263_ENC: @@ -662,7 +663,7 @@ static int s5p_mfc_set_enc_ref_buffer_v5(struct s5p_mfc_ctx *ctx) mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_ACDC_COEF_ADR); buf_addr1 += S5P_FIMV_ENC_ACDCCOEF_SIZE; buf_size1 -= S5P_FIMV_ENC_ACDCCOEF_SIZE; - mfc_debug(2, "buf_size1: %d, buf_size2: %d\n", + mfc_debug(2, "buf_size1: %zu, buf_size2: %zu\n", buf_size1, buf_size2); break; default: @@ -1186,7 +1187,6 @@ static int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx, int last_frame) struct s5p_mfc_dev *dev = ctx->dev; struct s5p_mfc_buf *temp_vb; unsigned long flags; - unsigned int index; if (ctx->state == MFCINST_FINISHING) { last_frame = MFC_DEC_LAST_FRAME; @@ -1211,7 +1211,6 @@ static int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx, int last_frame) vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), ctx->consumed_stream, temp_vb->b->v4l2_planes[0].bytesused); spin_unlock_irqrestore(&dev->irqlock, flags); - index = temp_vb->b->v4l2_buf.index; dev->curr_ctx = ctx->num; s5p_mfc_clean_ctx_int_flags(ctx); if (temp_vb->b->v4l2_planes[0].bytesused == 0) { diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c index c1c12f8d8f68..8798b14bacce 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c @@ -43,11 +43,6 @@ } while (0) #endif /* S5P_MFC_DEBUG_REGWRITE */ -#define READL(reg) \ - (WARN_ON_ONCE(!(reg)) ? 0 : readl(reg)) -#define WRITEL(data, reg) \ - (WARN_ON_ONCE(!(reg)) ? 0 : writel((data), (reg))) - #define IS_MFCV6_V2(dev) (!IS_MFCV7_PLUS(dev) && dev->fw_ver == MFC_FW_V2) /* Allocate temporary buffers for decoding */ @@ -105,7 +100,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) mb_width, mb_height), S5P_FIMV_ME_BUFFER_ALIGN_V6); - mfc_debug(2, "recon luma size: %d chroma size: %d\n", + mfc_debug(2, "recon luma size: %zu chroma size: %zu\n", ctx->luma_dpb_size, ctx->chroma_dpb_size); } else { return -EINVAL; @@ -416,10 +411,10 @@ static int s5p_mfc_set_dec_stream_buffer_v6(struct s5p_mfc_ctx *ctx, mfc_debug(2, "inst_no: %d, buf_addr: 0x%08x,\n" "buf_size: 0x%08x (%d)\n", ctx->inst_no, buf_addr, strm_size, strm_size); - WRITEL(strm_size, mfc_regs->d_stream_data_size); - WRITEL(buf_addr, mfc_regs->d_cpb_buffer_addr); - WRITEL(buf_size->cpb, mfc_regs->d_cpb_buffer_size); - WRITEL(start_num_byte, mfc_regs->d_cpb_buffer_offset); + writel(strm_size, mfc_regs->d_stream_data_size); + writel(buf_addr, mfc_regs->d_cpb_buffer_addr); + writel(buf_size->cpb, mfc_regs->d_cpb_buffer_size); + writel(start_num_byte, mfc_regs->d_cpb_buffer_offset); mfc_debug_leave(); return 0; @@ -443,17 +438,17 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx) mfc_debug(2, "Total DPB COUNT: %d\n", ctx->total_dpb_count); mfc_debug(2, "Setting display delay to %d\n", ctx->display_delay); - WRITEL(ctx->total_dpb_count, mfc_regs->d_num_dpb); - WRITEL(ctx->luma_size, mfc_regs->d_first_plane_dpb_size); - WRITEL(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size); + writel(ctx->total_dpb_count, mfc_regs->d_num_dpb); + writel(ctx->luma_size, mfc_regs->d_first_plane_dpb_size); + writel(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size); - WRITEL(buf_addr1, mfc_regs->d_scratch_buffer_addr); - WRITEL(ctx->scratch_buf_size, mfc_regs->d_scratch_buffer_size); + writel(buf_addr1, mfc_regs->d_scratch_buffer_addr); + writel(ctx->scratch_buf_size, mfc_regs->d_scratch_buffer_size); if (IS_MFCV8(dev)) { - WRITEL(ctx->img_width, + writel(ctx->img_width, mfc_regs->d_first_plane_dpb_stride_size); - WRITEL(ctx->img_width, + writel(ctx->img_width, mfc_regs->d_second_plane_dpb_stride_size); } @@ -462,8 +457,8 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx) if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC || ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC){ - WRITEL(ctx->mv_size, mfc_regs->d_mv_buffer_size); - WRITEL(ctx->mv_count, mfc_regs->d_num_mv); + writel(ctx->mv_size, mfc_regs->d_mv_buffer_size); + writel(ctx->mv_count, mfc_regs->d_num_mv); } frame_size = ctx->luma_size; @@ -474,13 +469,13 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx) for (i = 0; i < ctx->total_dpb_count; i++) { /* Bank2 */ - mfc_debug(2, "Luma %d: %x\n", i, + mfc_debug(2, "Luma %d: %zx\n", i, ctx->dst_bufs[i].cookie.raw.luma); - WRITEL(ctx->dst_bufs[i].cookie.raw.luma, + writel(ctx->dst_bufs[i].cookie.raw.luma, mfc_regs->d_first_plane_dpb + i * 4); - mfc_debug(2, "\tChroma %d: %x\n", i, + mfc_debug(2, "\tChroma %d: %zx\n", i, ctx->dst_bufs[i].cookie.raw.chroma); - WRITEL(ctx->dst_bufs[i].cookie.raw.chroma, + writel(ctx->dst_bufs[i].cookie.raw.chroma, mfc_regs->d_second_plane_dpb + i * 4); } if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || @@ -492,23 +487,23 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx) align_gap = buf_addr1 - align_gap; buf_size1 -= align_gap; - mfc_debug(2, "\tBuf1: %x, size: %d\n", + mfc_debug(2, "\tBuf1: %zx, size: %d\n", buf_addr1, buf_size1); - WRITEL(buf_addr1, mfc_regs->d_mv_buffer + i * 4); + writel(buf_addr1, mfc_regs->d_mv_buffer + i * 4); buf_addr1 += frame_size_mv; buf_size1 -= frame_size_mv; } } - mfc_debug(2, "Buf1: %u, buf_size1: %d (frames %d)\n", + mfc_debug(2, "Buf1: %zu, buf_size1: %d (frames %d)\n", buf_addr1, buf_size1, ctx->total_dpb_count); if (buf_size1 < 0) { mfc_debug(2, "Not enough memory has been allocated.\n"); return -ENOMEM; } - WRITEL(ctx->inst_no, mfc_regs->instance_id); - s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, + writel(ctx->inst_no, mfc_regs->instance_id); + s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev, S5P_FIMV_CH_INIT_BUFS_V6, NULL); mfc_debug(2, "After setting buffers.\n"); @@ -522,8 +517,8 @@ static int s5p_mfc_set_enc_stream_buffer_v6(struct s5p_mfc_ctx *ctx, struct s5p_mfc_dev *dev = ctx->dev; const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; - WRITEL(addr, mfc_regs->e_stream_buffer_addr); /* 16B align */ - WRITEL(size, mfc_regs->e_stream_buffer_size); + writel(addr, mfc_regs->e_stream_buffer_addr); /* 16B align */ + writel(size, mfc_regs->e_stream_buffer_size); mfc_debug(2, "stream buf addr: 0x%08lx, size: 0x%d\n", addr, size); @@ -537,8 +532,8 @@ static void s5p_mfc_set_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx, struct s5p_mfc_dev *dev = ctx->dev; const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; - WRITEL(y_addr, mfc_regs->e_source_first_plane_addr); - WRITEL(c_addr, mfc_regs->e_source_second_plane_addr); + writel(y_addr, mfc_regs->e_source_first_plane_addr); + writel(c_addr, mfc_regs->e_source_second_plane_addr); mfc_debug(2, "enc src y buf addr: 0x%08lx\n", y_addr); mfc_debug(2, "enc src c buf addr: 0x%08lx\n", c_addr); @@ -551,11 +546,11 @@ static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx, const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; unsigned long enc_recon_y_addr, enc_recon_c_addr; - *y_addr = READL(mfc_regs->e_encoded_source_first_plane_addr); - *c_addr = READL(mfc_regs->e_encoded_source_second_plane_addr); + *y_addr = readl(mfc_regs->e_encoded_source_first_plane_addr); + *c_addr = readl(mfc_regs->e_encoded_source_second_plane_addr); - enc_recon_y_addr = READL(mfc_regs->e_recon_luma_dpb_addr); - enc_recon_c_addr = READL(mfc_regs->e_recon_chroma_dpb_addr); + enc_recon_y_addr = readl(mfc_regs->e_recon_luma_dpb_addr); + enc_recon_c_addr = readl(mfc_regs->e_recon_chroma_dpb_addr); mfc_debug(2, "recon y addr: 0x%08lx\n", enc_recon_y_addr); mfc_debug(2, "recon c addr: 0x%08lx\n", enc_recon_c_addr); @@ -577,36 +572,36 @@ static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx) mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1); for (i = 0; i < ctx->pb_count; i++) { - WRITEL(buf_addr1, mfc_regs->e_luma_dpb + (4 * i)); + writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i)); buf_addr1 += ctx->luma_dpb_size; - WRITEL(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i)); + writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i)); buf_addr1 += ctx->chroma_dpb_size; - WRITEL(buf_addr1, mfc_regs->e_me_buffer + (4 * i)); + writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i)); buf_addr1 += ctx->me_buffer_size; buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size + ctx->me_buffer_size); } - WRITEL(buf_addr1, mfc_regs->e_scratch_buffer_addr); - WRITEL(ctx->scratch_buf_size, mfc_regs->e_scratch_buffer_size); + writel(buf_addr1, mfc_regs->e_scratch_buffer_addr); + writel(ctx->scratch_buf_size, mfc_regs->e_scratch_buffer_size); buf_addr1 += ctx->scratch_buf_size; buf_size1 -= ctx->scratch_buf_size; - WRITEL(buf_addr1, mfc_regs->e_tmv_buffer0); + writel(buf_addr1, mfc_regs->e_tmv_buffer0); buf_addr1 += ctx->tmv_buffer_size >> 1; - WRITEL(buf_addr1, mfc_regs->e_tmv_buffer1); + writel(buf_addr1, mfc_regs->e_tmv_buffer1); buf_addr1 += ctx->tmv_buffer_size >> 1; buf_size1 -= ctx->tmv_buffer_size; - mfc_debug(2, "Buf1: %u, buf_size1: %d (ref frames %d)\n", + mfc_debug(2, "Buf1: %zu, buf_size1: %d (ref frames %d)\n", buf_addr1, buf_size1, ctx->pb_count); if (buf_size1 < 0) { mfc_debug(2, "Not enough memory has been allocated.\n"); return -ENOMEM; } - WRITEL(ctx->inst_no, mfc_regs->instance_id); - s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, + writel(ctx->inst_no, mfc_regs->instance_id); + s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev, S5P_FIMV_CH_INIT_BUFS_V6, NULL); mfc_debug_leave(); @@ -621,15 +616,15 @@ static int s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx) /* multi-slice control */ /* multi-slice MB number or bit size */ - WRITEL(ctx->slice_mode, mfc_regs->e_mslice_mode); + writel(ctx->slice_mode, mfc_regs->e_mslice_mode); if (ctx->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) { - WRITEL(ctx->slice_size.mb, mfc_regs->e_mslice_size_mb); + writel(ctx->slice_size.mb, mfc_regs->e_mslice_size_mb); } else if (ctx->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) { - WRITEL(ctx->slice_size.bits, mfc_regs->e_mslice_size_bits); + writel(ctx->slice_size.bits, mfc_regs->e_mslice_size_bits); } else { - WRITEL(0x0, mfc_regs->e_mslice_size_mb); - WRITEL(0x0, mfc_regs->e_mslice_size_bits); + writel(0x0, mfc_regs->e_mslice_size_mb); + writel(0x0, mfc_regs->e_mslice_size_bits); } return 0; @@ -645,21 +640,21 @@ static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx) mfc_debug_enter(); /* width */ - WRITEL(ctx->img_width, mfc_regs->e_frame_width); /* 16 align */ + writel(ctx->img_width, mfc_regs->e_frame_width); /* 16 align */ /* height */ - WRITEL(ctx->img_height, mfc_regs->e_frame_height); /* 16 align */ + writel(ctx->img_height, mfc_regs->e_frame_height); /* 16 align */ /* cropped width */ - WRITEL(ctx->img_width, mfc_regs->e_cropped_frame_width); + writel(ctx->img_width, mfc_regs->e_cropped_frame_width); /* cropped height */ - WRITEL(ctx->img_height, mfc_regs->e_cropped_frame_height); + writel(ctx->img_height, mfc_regs->e_cropped_frame_height); /* cropped offset */ - WRITEL(0x0, mfc_regs->e_frame_crop_offset); + writel(0x0, mfc_regs->e_frame_crop_offset); /* pictype : IDR period */ reg = 0; reg |= p->gop_size & 0xFFFF; - WRITEL(reg, mfc_regs->e_gop_config); + writel(reg, mfc_regs->e_gop_config); /* multi-slice control */ /* multi-slice MB number or bit size */ @@ -667,65 +662,65 @@ static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx) reg = 0; if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) { reg |= (0x1 << 3); - WRITEL(reg, mfc_regs->e_enc_options); + writel(reg, mfc_regs->e_enc_options); ctx->slice_size.mb = p->slice_mb; } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) { reg |= (0x1 << 3); - WRITEL(reg, mfc_regs->e_enc_options); + writel(reg, mfc_regs->e_enc_options); ctx->slice_size.bits = p->slice_bit; } else { reg &= ~(0x1 << 3); - WRITEL(reg, mfc_regs->e_enc_options); + writel(reg, mfc_regs->e_enc_options); } s5p_mfc_set_slice_mode(ctx); /* cyclic intra refresh */ - WRITEL(p->intra_refresh_mb, mfc_regs->e_ir_size); - reg = READL(mfc_regs->e_enc_options); + writel(p->intra_refresh_mb, mfc_regs->e_ir_size); + reg = readl(mfc_regs->e_enc_options); if (p->intra_refresh_mb == 0) reg &= ~(0x1 << 4); else reg |= (0x1 << 4); - WRITEL(reg, mfc_regs->e_enc_options); + writel(reg, mfc_regs->e_enc_options); /* 'NON_REFERENCE_STORE_ENABLE' for debugging */ - reg = READL(mfc_regs->e_enc_options); + reg = readl(mfc_regs->e_enc_options); reg &= ~(0x1 << 9); - WRITEL(reg, mfc_regs->e_enc_options); + writel(reg, mfc_regs->e_enc_options); /* memory structure cur. frame */ if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) { /* 0: Linear, 1: 2D tiled*/ - reg = READL(mfc_regs->e_enc_options); + reg = readl(mfc_regs->e_enc_options); reg &= ~(0x1 << 7); - WRITEL(reg, mfc_regs->e_enc_options); + writel(reg, mfc_regs->e_enc_options); /* 0: NV12(CbCr), 1: NV21(CrCb) */ - WRITEL(0x0, mfc_regs->pixel_format); + writel(0x0, mfc_regs->pixel_format); } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV21M) { /* 0: Linear, 1: 2D tiled*/ - reg = READL(mfc_regs->e_enc_options); + reg = readl(mfc_regs->e_enc_options); reg &= ~(0x1 << 7); - WRITEL(reg, mfc_regs->e_enc_options); + writel(reg, mfc_regs->e_enc_options); /* 0: NV12(CbCr), 1: NV21(CrCb) */ - WRITEL(0x1, mfc_regs->pixel_format); + writel(0x1, mfc_regs->pixel_format); } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) { /* 0: Linear, 1: 2D tiled*/ - reg = READL(mfc_regs->e_enc_options); + reg = readl(mfc_regs->e_enc_options); reg |= (0x1 << 7); - WRITEL(reg, mfc_regs->e_enc_options); + writel(reg, mfc_regs->e_enc_options); /* 0: NV12(CbCr), 1: NV21(CrCb) */ - WRITEL(0x0, mfc_regs->pixel_format); + writel(0x0, mfc_regs->pixel_format); } /* memory structure recon. frame */ /* 0: Linear, 1: 2D tiled */ - reg = READL(mfc_regs->e_enc_options); + reg = readl(mfc_regs->e_enc_options); reg |= (0x1 << 8); - WRITEL(reg, mfc_regs->e_enc_options); + writel(reg, mfc_regs->e_enc_options); /* padding control & value */ - WRITEL(0x0, mfc_regs->e_padding_ctrl); + writel(0x0, mfc_regs->e_padding_ctrl); if (p->pad) { reg = 0; /** enable */ @@ -736,64 +731,64 @@ static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx) reg |= ((p->pad_cb & 0xFF) << 8); /** y value */ reg |= p->pad_luma & 0xFF; - WRITEL(reg, mfc_regs->e_padding_ctrl); + writel(reg, mfc_regs->e_padding_ctrl); } /* rate control config. */ reg = 0; /* frame-level rate control */ reg |= ((p->rc_frame & 0x1) << 9); - WRITEL(reg, mfc_regs->e_rc_config); + writel(reg, mfc_regs->e_rc_config); /* bit rate */ if (p->rc_frame) - WRITEL(p->rc_bitrate, + writel(p->rc_bitrate, mfc_regs->e_rc_bit_rate); else - WRITEL(1, mfc_regs->e_rc_bit_rate); + writel(1, mfc_regs->e_rc_bit_rate); /* reaction coefficient */ if (p->rc_frame) { if (p->rc_reaction_coeff < TIGHT_CBR_MAX) /* tight CBR */ - WRITEL(1, mfc_regs->e_rc_mode); + writel(1, mfc_regs->e_rc_mode); else /* loose CBR */ - WRITEL(2, mfc_regs->e_rc_mode); + writel(2, mfc_regs->e_rc_mode); } /* seq header ctrl */ - reg = READL(mfc_regs->e_enc_options); + reg = readl(mfc_regs->e_enc_options); reg &= ~(0x1 << 2); reg |= ((p->seq_hdr_mode & 0x1) << 2); /* frame skip mode */ reg &= ~(0x3); reg |= (p->frame_skip_mode & 0x3); - WRITEL(reg, mfc_regs->e_enc_options); + writel(reg, mfc_regs->e_enc_options); /* 'DROP_CONTROL_ENABLE', disable */ - reg = READL(mfc_regs->e_rc_config); + reg = readl(mfc_regs->e_rc_config); reg &= ~(0x1 << 10); - WRITEL(reg, mfc_regs->e_rc_config); + writel(reg, mfc_regs->e_rc_config); /* setting for MV range [16, 256] */ reg = (p->mv_h_range & S5P_FIMV_E_MV_RANGE_V6_MASK); - WRITEL(reg, mfc_regs->e_mv_hor_range); + writel(reg, mfc_regs->e_mv_hor_range); reg = (p->mv_v_range & S5P_FIMV_E_MV_RANGE_V6_MASK); - WRITEL(reg, mfc_regs->e_mv_ver_range); + writel(reg, mfc_regs->e_mv_ver_range); - WRITEL(0x0, mfc_regs->e_frame_insertion); - WRITEL(0x0, mfc_regs->e_roi_buffer_addr); - WRITEL(0x0, mfc_regs->e_param_change); - WRITEL(0x0, mfc_regs->e_rc_roi_ctrl); - WRITEL(0x0, mfc_regs->e_picture_tag); + writel(0x0, mfc_regs->e_frame_insertion); + writel(0x0, mfc_regs->e_roi_buffer_addr); + writel(0x0, mfc_regs->e_param_change); + writel(0x0, mfc_regs->e_rc_roi_ctrl); + writel(0x0, mfc_regs->e_picture_tag); - WRITEL(0x0, mfc_regs->e_bit_count_enable); - WRITEL(0x0, mfc_regs->e_max_bit_count); - WRITEL(0x0, mfc_regs->e_min_bit_count); + writel(0x0, mfc_regs->e_bit_count_enable); + writel(0x0, mfc_regs->e_max_bit_count); + writel(0x0, mfc_regs->e_min_bit_count); - WRITEL(0x0, mfc_regs->e_metadata_buffer_addr); - WRITEL(0x0, mfc_regs->e_metadata_buffer_size); + writel(0x0, mfc_regs->e_metadata_buffer_addr); + writel(0x0, mfc_regs->e_metadata_buffer_size); mfc_debug_leave(); @@ -814,10 +809,10 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) s5p_mfc_set_enc_params(ctx); /* pictype : number of B */ - reg = READL(mfc_regs->e_gop_config); + reg = readl(mfc_regs->e_gop_config); reg &= ~(0x3 << 16); reg |= ((p->num_b_frame & 0x3) << 16); - WRITEL(reg, mfc_regs->e_gop_config); + writel(reg, mfc_regs->e_gop_config); /* profile & level */ reg = 0; @@ -825,19 +820,19 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) reg |= ((p_h264->level & 0xFF) << 8); /** profile - 0 ~ 3 */ reg |= p_h264->profile & 0x3F; - WRITEL(reg, mfc_regs->e_picture_profile); + writel(reg, mfc_regs->e_picture_profile); /* rate control config. */ - reg = READL(mfc_regs->e_rc_config); + reg = readl(mfc_regs->e_rc_config); /** macroblock level rate control */ reg &= ~(0x1 << 8); reg |= ((p->rc_mb & 0x1) << 8); - WRITEL(reg, mfc_regs->e_rc_config); + writel(reg, mfc_regs->e_rc_config); /** frame QP */ reg &= ~(0x3F); reg |= p_h264->rc_frame_qp & 0x3F; - WRITEL(reg, mfc_regs->e_rc_config); + writel(reg, mfc_regs->e_rc_config); /* max & min value of QP */ reg = 0; @@ -845,16 +840,16 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) reg |= ((p_h264->rc_max_qp & 0x3F) << 8); /** min QP */ reg |= p_h264->rc_min_qp & 0x3F; - WRITEL(reg, mfc_regs->e_rc_qp_bound); + writel(reg, mfc_regs->e_rc_qp_bound); /* other QPs */ - WRITEL(0x0, mfc_regs->e_fixed_picture_qp); + writel(0x0, mfc_regs->e_fixed_picture_qp); if (!p->rc_frame && !p->rc_mb) { reg = 0; reg |= ((p_h264->rc_b_frame_qp & 0x3F) << 16); reg |= ((p_h264->rc_p_frame_qp & 0x3F) << 8); reg |= p_h264->rc_frame_qp & 0x3F; - WRITEL(reg, mfc_regs->e_fixed_picture_qp); + writel(reg, mfc_regs->e_fixed_picture_qp); } /* frame rate */ @@ -862,38 +857,38 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) reg = 0; reg |= ((p->rc_framerate_num & 0xFFFF) << 16); reg |= p->rc_framerate_denom & 0xFFFF; - WRITEL(reg, mfc_regs->e_rc_frame_rate); + writel(reg, mfc_regs->e_rc_frame_rate); } /* vbv buffer size */ if (p->frame_skip_mode == V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { - WRITEL(p_h264->cpb_size & 0xFFFF, + writel(p_h264->cpb_size & 0xFFFF, mfc_regs->e_vbv_buffer_size); if (p->rc_frame) - WRITEL(p->vbv_delay, mfc_regs->e_vbv_init_delay); + writel(p->vbv_delay, mfc_regs->e_vbv_init_delay); } /* interlace */ reg = 0; reg |= ((p_h264->interlace & 0x1) << 3); - WRITEL(reg, mfc_regs->e_h264_options); + writel(reg, mfc_regs->e_h264_options); /* height */ if (p_h264->interlace) { - WRITEL(ctx->img_height >> 1, + writel(ctx->img_height >> 1, mfc_regs->e_frame_height); /* 32 align */ /* cropped height */ - WRITEL(ctx->img_height >> 1, + writel(ctx->img_height >> 1, mfc_regs->e_cropped_frame_height); } /* loop filter ctrl */ - reg = READL(mfc_regs->e_h264_options); + reg = readl(mfc_regs->e_h264_options); reg &= ~(0x3 << 1); reg |= ((p_h264->loop_filter_mode & 0x3) << 1); - WRITEL(reg, mfc_regs->e_h264_options); + writel(reg, mfc_regs->e_h264_options); /* loopfilter alpha offset */ if (p_h264->loop_filter_alpha < 0) { @@ -903,7 +898,7 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) reg = 0x00; reg |= (p_h264->loop_filter_alpha & 0xF); } - WRITEL(reg, mfc_regs->e_h264_lf_alpha_offset); + writel(reg, mfc_regs->e_h264_lf_alpha_offset); /* loopfilter beta offset */ if (p_h264->loop_filter_beta < 0) { @@ -913,28 +908,28 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) reg = 0x00; reg |= (p_h264->loop_filter_beta & 0xF); } - WRITEL(reg, mfc_regs->e_h264_lf_beta_offset); + writel(reg, mfc_regs->e_h264_lf_beta_offset); /* entropy coding mode */ - reg = READL(mfc_regs->e_h264_options); + reg = readl(mfc_regs->e_h264_options); reg &= ~(0x1); reg |= p_h264->entropy_mode & 0x1; - WRITEL(reg, mfc_regs->e_h264_options); + writel(reg, mfc_regs->e_h264_options); /* number of ref. picture */ - reg = READL(mfc_regs->e_h264_options); + reg = readl(mfc_regs->e_h264_options); reg &= ~(0x1 << 7); reg |= (((p_h264->num_ref_pic_4p - 1) & 0x1) << 7); - WRITEL(reg, mfc_regs->e_h264_options); + writel(reg, mfc_regs->e_h264_options); /* 8x8 transform enable */ - reg = READL(mfc_regs->e_h264_options); + reg = readl(mfc_regs->e_h264_options); reg &= ~(0x3 << 12); reg |= ((p_h264->_8x8_transform & 0x3) << 12); - WRITEL(reg, mfc_regs->e_h264_options); + writel(reg, mfc_regs->e_h264_options); /* macroblock adaptive scaling features */ - WRITEL(0x0, mfc_regs->e_mb_rc_config); + writel(0x0, mfc_regs->e_mb_rc_config); if (p->rc_mb) { reg = 0; /** dark region */ @@ -945,95 +940,95 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) reg |= ((p_h264->rc_mb_static & 0x1) << 1); /** high activity region */ reg |= p_h264->rc_mb_activity & 0x1; - WRITEL(reg, mfc_regs->e_mb_rc_config); + writel(reg, mfc_regs->e_mb_rc_config); } /* aspect ratio VUI */ - READL(mfc_regs->e_h264_options); + readl(mfc_regs->e_h264_options); reg &= ~(0x1 << 5); reg |= ((p_h264->vui_sar & 0x1) << 5); - WRITEL(reg, mfc_regs->e_h264_options); + writel(reg, mfc_regs->e_h264_options); - WRITEL(0x0, mfc_regs->e_aspect_ratio); - WRITEL(0x0, mfc_regs->e_extended_sar); + writel(0x0, mfc_regs->e_aspect_ratio); + writel(0x0, mfc_regs->e_extended_sar); if (p_h264->vui_sar) { /* aspect ration IDC */ reg = 0; reg |= p_h264->vui_sar_idc & 0xFF; - WRITEL(reg, mfc_regs->e_aspect_ratio); + writel(reg, mfc_regs->e_aspect_ratio); if (p_h264->vui_sar_idc == 0xFF) { /* extended SAR */ reg = 0; reg |= (p_h264->vui_ext_sar_width & 0xFFFF) << 16; reg |= p_h264->vui_ext_sar_height & 0xFFFF; - WRITEL(reg, mfc_regs->e_extended_sar); + writel(reg, mfc_regs->e_extended_sar); } } /* intra picture period for H.264 open GOP */ /* control */ - READL(mfc_regs->e_h264_options); + readl(mfc_regs->e_h264_options); reg &= ~(0x1 << 4); reg |= ((p_h264->open_gop & 0x1) << 4); - WRITEL(reg, mfc_regs->e_h264_options); + writel(reg, mfc_regs->e_h264_options); /* value */ - WRITEL(0x0, mfc_regs->e_h264_i_period); + writel(0x0, mfc_regs->e_h264_i_period); if (p_h264->open_gop) { reg = 0; reg |= p_h264->open_gop_size & 0xFFFF; - WRITEL(reg, mfc_regs->e_h264_i_period); + writel(reg, mfc_regs->e_h264_i_period); } /* 'WEIGHTED_BI_PREDICTION' for B is disable */ - READL(mfc_regs->e_h264_options); + readl(mfc_regs->e_h264_options); reg &= ~(0x3 << 9); - WRITEL(reg, mfc_regs->e_h264_options); + writel(reg, mfc_regs->e_h264_options); /* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */ - READL(mfc_regs->e_h264_options); + readl(mfc_regs->e_h264_options); reg &= ~(0x1 << 14); - WRITEL(reg, mfc_regs->e_h264_options); + writel(reg, mfc_regs->e_h264_options); /* ASO */ - READL(mfc_regs->e_h264_options); + readl(mfc_regs->e_h264_options); reg &= ~(0x1 << 6); reg |= ((p_h264->aso & 0x1) << 6); - WRITEL(reg, mfc_regs->e_h264_options); + writel(reg, mfc_regs->e_h264_options); /* hier qp enable */ - READL(mfc_regs->e_h264_options); + readl(mfc_regs->e_h264_options); reg &= ~(0x1 << 8); reg |= ((p_h264->open_gop & 0x1) << 8); - WRITEL(reg, mfc_regs->e_h264_options); + writel(reg, mfc_regs->e_h264_options); reg = 0; if (p_h264->hier_qp && p_h264->hier_qp_layer) { reg |= (p_h264->hier_qp_type & 0x1) << 0x3; reg |= p_h264->hier_qp_layer & 0x7; - WRITEL(reg, mfc_regs->e_h264_num_t_layer); + writel(reg, mfc_regs->e_h264_num_t_layer); /* QP value for each layer */ for (i = 0; i < p_h264->hier_qp_layer && i < ARRAY_SIZE(p_h264->hier_qp_layer_qp); i++) { - WRITEL(p_h264->hier_qp_layer_qp[i], + writel(p_h264->hier_qp_layer_qp[i], mfc_regs->e_h264_hierarchical_qp_layer0 + i * 4); } } /* number of coding layer should be zero when hierarchical is disable */ - WRITEL(reg, mfc_regs->e_h264_num_t_layer); + writel(reg, mfc_regs->e_h264_num_t_layer); /* frame packing SEI generation */ - READL(mfc_regs->e_h264_options); + readl(mfc_regs->e_h264_options); reg &= ~(0x1 << 25); reg |= ((p_h264->sei_frame_packing & 0x1) << 25); - WRITEL(reg, mfc_regs->e_h264_options); + writel(reg, mfc_regs->e_h264_options); if (p_h264->sei_frame_packing) { reg = 0; /** current frame0 flag */ reg |= ((p_h264->sei_fp_curr_frame_0 & 0x1) << 2); /** arrangement type */ reg |= p_h264->sei_fp_arrangement_type & 0x3; - WRITEL(reg, mfc_regs->e_h264_frame_packing_sei_info); + writel(reg, mfc_regs->e_h264_frame_packing_sei_info); } if (p_h264->fmo) { @@ -1042,7 +1037,7 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) if (p_h264->fmo_slice_grp > 4) p_h264->fmo_slice_grp = 4; for (i = 0; i < (p_h264->fmo_slice_grp & 0xF); i++) - WRITEL(p_h264->fmo_run_len[i] - 1, + writel(p_h264->fmo_run_len[i] - 1, mfc_regs->e_h264_fmo_run_length_minus1_0 + i * 4); break; @@ -1054,10 +1049,10 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN: if (p_h264->fmo_slice_grp > 2) p_h264->fmo_slice_grp = 2; - WRITEL(p_h264->fmo_chg_dir & 0x1, + writel(p_h264->fmo_chg_dir & 0x1, mfc_regs->e_h264_fmo_slice_grp_change_dir); /* the valid range is 0 ~ number of macroblocks -1 */ - WRITEL(p_h264->fmo_chg_rate, + writel(p_h264->fmo_chg_rate, mfc_regs->e_h264_fmo_slice_grp_change_rate_minus1); break; default: @@ -1068,12 +1063,12 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) break; } - WRITEL(p_h264->fmo_map_type, + writel(p_h264->fmo_map_type, mfc_regs->e_h264_fmo_slice_grp_map_type); - WRITEL(p_h264->fmo_slice_grp - 1, + writel(p_h264->fmo_slice_grp - 1, mfc_regs->e_h264_fmo_num_slice_grp_minus1); } else { - WRITEL(0, mfc_regs->e_h264_fmo_num_slice_grp_minus1); + writel(0, mfc_regs->e_h264_fmo_num_slice_grp_minus1); } mfc_debug_leave(); @@ -1094,10 +1089,10 @@ static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx) s5p_mfc_set_enc_params(ctx); /* pictype : number of B */ - reg = READL(mfc_regs->e_gop_config); + reg = readl(mfc_regs->e_gop_config); reg &= ~(0x3 << 16); reg |= ((p->num_b_frame & 0x3) << 16); - WRITEL(reg, mfc_regs->e_gop_config); + writel(reg, mfc_regs->e_gop_config); /* profile & level */ reg = 0; @@ -1105,19 +1100,19 @@ static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx) reg |= ((p_mpeg4->level & 0xFF) << 8); /** profile - 0 ~ 1 */ reg |= p_mpeg4->profile & 0x3F; - WRITEL(reg, mfc_regs->e_picture_profile); + writel(reg, mfc_regs->e_picture_profile); /* rate control config. */ - reg = READL(mfc_regs->e_rc_config); + reg = readl(mfc_regs->e_rc_config); /** macroblock level rate control */ reg &= ~(0x1 << 8); reg |= ((p->rc_mb & 0x1) << 8); - WRITEL(reg, mfc_regs->e_rc_config); + writel(reg, mfc_regs->e_rc_config); /** frame QP */ reg &= ~(0x3F); reg |= p_mpeg4->rc_frame_qp & 0x3F; - WRITEL(reg, mfc_regs->e_rc_config); + writel(reg, mfc_regs->e_rc_config); /* max & min value of QP */ reg = 0; @@ -1125,16 +1120,16 @@ static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx) reg |= ((p_mpeg4->rc_max_qp & 0x3F) << 8); /** min QP */ reg |= p_mpeg4->rc_min_qp & 0x3F; - WRITEL(reg, mfc_regs->e_rc_qp_bound); + writel(reg, mfc_regs->e_rc_qp_bound); /* other QPs */ - WRITEL(0x0, mfc_regs->e_fixed_picture_qp); + writel(0x0, mfc_regs->e_fixed_picture_qp); if (!p->rc_frame && !p->rc_mb) { reg = 0; reg |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 16); reg |= ((p_mpeg4->rc_p_frame_qp & 0x3F) << 8); reg |= p_mpeg4->rc_frame_qp & 0x3F; - WRITEL(reg, mfc_regs->e_fixed_picture_qp); + writel(reg, mfc_regs->e_fixed_picture_qp); } /* frame rate */ @@ -1142,21 +1137,21 @@ static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx) reg = 0; reg |= ((p->rc_framerate_num & 0xFFFF) << 16); reg |= p->rc_framerate_denom & 0xFFFF; - WRITEL(reg, mfc_regs->e_rc_frame_rate); + writel(reg, mfc_regs->e_rc_frame_rate); } /* vbv buffer size */ if (p->frame_skip_mode == V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { - WRITEL(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size); + writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size); if (p->rc_frame) - WRITEL(p->vbv_delay, mfc_regs->e_vbv_init_delay); + writel(p->vbv_delay, mfc_regs->e_vbv_init_delay); } /* Disable HEC */ - WRITEL(0x0, mfc_regs->e_mpeg4_options); - WRITEL(0x0, mfc_regs->e_mpeg4_hec_period); + writel(0x0, mfc_regs->e_mpeg4_options); + writel(0x0, mfc_regs->e_mpeg4_hec_period); mfc_debug_leave(); @@ -1179,19 +1174,19 @@ static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx) reg = 0; /** profile */ reg |= (0x1 << 4); - WRITEL(reg, mfc_regs->e_picture_profile); + writel(reg, mfc_regs->e_picture_profile); /* rate control config. */ - reg = READL(mfc_regs->e_rc_config); + reg = readl(mfc_regs->e_rc_config); /** macroblock level rate control */ reg &= ~(0x1 << 8); reg |= ((p->rc_mb & 0x1) << 8); - WRITEL(reg, mfc_regs->e_rc_config); + writel(reg, mfc_regs->e_rc_config); /** frame QP */ reg &= ~(0x3F); reg |= p_h263->rc_frame_qp & 0x3F; - WRITEL(reg, mfc_regs->e_rc_config); + writel(reg, mfc_regs->e_rc_config); /* max & min value of QP */ reg = 0; @@ -1199,16 +1194,16 @@ static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx) reg |= ((p_h263->rc_max_qp & 0x3F) << 8); /** min QP */ reg |= p_h263->rc_min_qp & 0x3F; - WRITEL(reg, mfc_regs->e_rc_qp_bound); + writel(reg, mfc_regs->e_rc_qp_bound); /* other QPs */ - WRITEL(0x0, mfc_regs->e_fixed_picture_qp); + writel(0x0, mfc_regs->e_fixed_picture_qp); if (!p->rc_frame && !p->rc_mb) { reg = 0; reg |= ((p_h263->rc_b_frame_qp & 0x3F) << 16); reg |= ((p_h263->rc_p_frame_qp & 0x3F) << 8); reg |= p_h263->rc_frame_qp & 0x3F; - WRITEL(reg, mfc_regs->e_fixed_picture_qp); + writel(reg, mfc_regs->e_fixed_picture_qp); } /* frame rate */ @@ -1216,16 +1211,16 @@ static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx) reg = 0; reg |= ((p->rc_framerate_num & 0xFFFF) << 16); reg |= p->rc_framerate_denom & 0xFFFF; - WRITEL(reg, mfc_regs->e_rc_frame_rate); + writel(reg, mfc_regs->e_rc_frame_rate); } /* vbv buffer size */ if (p->frame_skip_mode == V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { - WRITEL(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size); + writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size); if (p->rc_frame) - WRITEL(p->vbv_delay, mfc_regs->e_vbv_init_delay); + writel(p->vbv_delay, mfc_regs->e_vbv_init_delay); } mfc_debug_leave(); @@ -1247,57 +1242,57 @@ static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx) s5p_mfc_set_enc_params(ctx); /* pictype : number of B */ - reg = READL(mfc_regs->e_gop_config); + reg = readl(mfc_regs->e_gop_config); reg &= ~(0x3 << 16); reg |= ((p->num_b_frame & 0x3) << 16); - WRITEL(reg, mfc_regs->e_gop_config); + writel(reg, mfc_regs->e_gop_config); /* profile - 0 ~ 3 */ reg = p_vp8->profile & 0x3; - WRITEL(reg, mfc_regs->e_picture_profile); + writel(reg, mfc_regs->e_picture_profile); /* rate control config. */ - reg = READL(mfc_regs->e_rc_config); + reg = readl(mfc_regs->e_rc_config); /** macroblock level rate control */ reg &= ~(0x1 << 8); reg |= ((p->rc_mb & 0x1) << 8); - WRITEL(reg, mfc_regs->e_rc_config); + writel(reg, mfc_regs->e_rc_config); /* frame rate */ if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) { reg = 0; reg |= ((p->rc_framerate_num & 0xFFFF) << 16); reg |= p->rc_framerate_denom & 0xFFFF; - WRITEL(reg, mfc_regs->e_rc_frame_rate); + writel(reg, mfc_regs->e_rc_frame_rate); } /* frame QP */ reg &= ~(0x7F); reg |= p_vp8->rc_frame_qp & 0x7F; - WRITEL(reg, mfc_regs->e_rc_config); + writel(reg, mfc_regs->e_rc_config); /* other QPs */ - WRITEL(0x0, mfc_regs->e_fixed_picture_qp); + writel(0x0, mfc_regs->e_fixed_picture_qp); if (!p->rc_frame && !p->rc_mb) { reg = 0; reg |= ((p_vp8->rc_p_frame_qp & 0x7F) << 8); reg |= p_vp8->rc_frame_qp & 0x7F; - WRITEL(reg, mfc_regs->e_fixed_picture_qp); + writel(reg, mfc_regs->e_fixed_picture_qp); } /* max QP */ reg = ((p_vp8->rc_max_qp & 0x7F) << 8); /* min QP */ reg |= p_vp8->rc_min_qp & 0x7F; - WRITEL(reg, mfc_regs->e_rc_qp_bound); + writel(reg, mfc_regs->e_rc_qp_bound); /* vbv buffer size */ if (p->frame_skip_mode == V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { - WRITEL(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size); + writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size); if (p->rc_frame) - WRITEL(p->vbv_delay, mfc_regs->e_vbv_init_delay); + writel(p->vbv_delay, mfc_regs->e_vbv_init_delay); } /* VP8 specific params */ @@ -1319,7 +1314,7 @@ static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx) } reg |= (val & 0xF) << 3; reg |= (p_vp8->num_ref & 0x2); - WRITEL(reg, mfc_regs->e_vp8_options); + writel(reg, mfc_regs->e_vp8_options); mfc_debug_leave(); @@ -1338,9 +1333,9 @@ static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx) mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no, S5P_FIMV_CH_SEQ_HEADER_V6); mfc_debug(2, "BUFs: %08x %08x %08x\n", - READL(mfc_regs->d_cpb_buffer_addr), - READL(mfc_regs->d_cpb_buffer_addr), - READL(mfc_regs->d_cpb_buffer_addr)); + readl(mfc_regs->d_cpb_buffer_addr), + readl(mfc_regs->d_cpb_buffer_addr), + readl(mfc_regs->d_cpb_buffer_addr)); /* FMO_ASO_CTRL - 0: Enable, 1: Disable */ reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6); @@ -1351,11 +1346,11 @@ static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx) * set to negative value. */ if (ctx->display_delay >= 0) { reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6); - WRITEL(ctx->display_delay, mfc_regs->d_display_delay); + writel(ctx->display_delay, mfc_regs->d_display_delay); } if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev)) { - WRITEL(reg, mfc_regs->d_dec_options); + writel(reg, mfc_regs->d_dec_options); reg = 0; } @@ -1370,22 +1365,22 @@ static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx) reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6); if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev)) - WRITEL(reg, mfc_regs->d_init_buffer_options); + writel(reg, mfc_regs->d_init_buffer_options); else - WRITEL(reg, mfc_regs->d_dec_options); + writel(reg, mfc_regs->d_dec_options); /* 0: NV12(CbCr), 1: NV21(CrCb) */ if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M) - WRITEL(0x1, mfc_regs->pixel_format); + writel(0x1, mfc_regs->pixel_format); else - WRITEL(0x0, mfc_regs->pixel_format); + writel(0x0, mfc_regs->pixel_format); /* sei parse */ - WRITEL(ctx->sei_fp_parse & 0x1, mfc_regs->d_sei_enable); + writel(ctx->sei_fp_parse & 0x1, mfc_regs->d_sei_enable); - WRITEL(ctx->inst_no, mfc_regs->instance_id); - s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, + writel(ctx->inst_no, mfc_regs->instance_id); + s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev, S5P_FIMV_CH_SEQ_HEADER_V6, NULL); mfc_debug_leave(); @@ -1400,8 +1395,8 @@ static inline void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush) if (flush) { dev->curr_ctx = ctx->num; s5p_mfc_clean_ctx_int_flags(ctx); - WRITEL(ctx->inst_no, mfc_regs->instance_id); - s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, + writel(ctx->inst_no, mfc_regs->instance_id); + s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev, S5P_FIMV_H2R_CMD_FLUSH_V6, NULL); } } @@ -1413,19 +1408,19 @@ static int s5p_mfc_decode_one_frame_v6(struct s5p_mfc_ctx *ctx, struct s5p_mfc_dev *dev = ctx->dev; const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; - WRITEL(ctx->dec_dst_flag, mfc_regs->d_available_dpb_flag_lower); - WRITEL(ctx->slice_interface & 0x1, mfc_regs->d_slice_if_enable); + writel(ctx->dec_dst_flag, mfc_regs->d_available_dpb_flag_lower); + writel(ctx->slice_interface & 0x1, mfc_regs->d_slice_if_enable); - WRITEL(ctx->inst_no, mfc_regs->instance_id); + writel(ctx->inst_no, mfc_regs->instance_id); /* Issue different commands to instance basing on whether it * is the last frame or not. */ switch (last_frame) { case 0: - s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, + s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev, S5P_FIMV_CH_FRAME_START_V6, NULL); break; case 1: - s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, + s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev, S5P_FIMV_CH_LAST_FRAME_V6, NULL); break; default: @@ -1458,12 +1453,12 @@ static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx) /* Set stride lengths for v7 & above */ if (IS_MFCV7_PLUS(dev)) { - WRITEL(ctx->img_width, mfc_regs->e_source_first_plane_stride); - WRITEL(ctx->img_width, mfc_regs->e_source_second_plane_stride); + writel(ctx->img_width, mfc_regs->e_source_first_plane_stride); + writel(ctx->img_width, mfc_regs->e_source_second_plane_stride); } - WRITEL(ctx->inst_no, mfc_regs->instance_id); - s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, + writel(ctx->inst_no, mfc_regs->instance_id); + s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev, S5P_FIMV_CH_SEQ_HEADER_V6, NULL); return 0; @@ -1479,7 +1474,7 @@ static int s5p_mfc_h264_set_aso_slice_order_v6(struct s5p_mfc_ctx *ctx) if (p_h264->aso) { for (i = 0; i < ARRAY_SIZE(p_h264->aso_slice_order); i++) { - WRITEL(p_h264->aso_slice_order[i], + writel(p_h264->aso_slice_order[i], mfc_regs->e_h264_aso_slice_order_0 + i * 4); } } @@ -1501,8 +1496,8 @@ static int s5p_mfc_encode_one_frame_v6(struct s5p_mfc_ctx *ctx) s5p_mfc_set_slice_mode(ctx); - WRITEL(ctx->inst_no, mfc_regs->instance_id); - s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, + writel(ctx->inst_no, mfc_regs->instance_id); + s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev, S5P_FIMV_CH_FRAME_START_V6, NULL); mfc_debug(2, "--\n"); @@ -1877,15 +1872,15 @@ static void s5p_mfc_cleanup_queue_v6(struct list_head *lh, struct vb2_queue *vq) static void s5p_mfc_clear_int_flags_v6(struct s5p_mfc_dev *dev) { const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; - WRITEL(0, mfc_regs->risc2host_command); - WRITEL(0, mfc_regs->risc2host_int); + writel(0, mfc_regs->risc2host_command); + writel(0, mfc_regs->risc2host_int); } static void s5p_mfc_write_info_v6(struct s5p_mfc_ctx *ctx, unsigned int data, unsigned int ofs) { s5p_mfc_clock_on(); - WRITEL(data, (void *)ofs); + writel(data, (volatile void __iomem *)((unsigned long)ofs)); s5p_mfc_clock_off(); } @@ -1895,7 +1890,7 @@ s5p_mfc_read_info_v6(struct s5p_mfc_ctx *ctx, unsigned int ofs) int ret; s5p_mfc_clock_on(); - ret = READL((void *)ofs); + ret = readl((volatile void __iomem *)((unsigned long)ofs)); s5p_mfc_clock_off(); return ret; @@ -1903,51 +1898,51 @@ s5p_mfc_read_info_v6(struct s5p_mfc_ctx *ctx, unsigned int ofs) static int s5p_mfc_get_dspl_y_adr_v6(struct s5p_mfc_dev *dev) { - return READL(dev->mfc_regs->d_display_first_plane_addr); + return readl(dev->mfc_regs->d_display_first_plane_addr); } static int s5p_mfc_get_dec_y_adr_v6(struct s5p_mfc_dev *dev) { - return READL(dev->mfc_regs->d_decoded_first_plane_addr); + return readl(dev->mfc_regs->d_decoded_first_plane_addr); } static int s5p_mfc_get_dspl_status_v6(struct s5p_mfc_dev *dev) { - return READL(dev->mfc_regs->d_display_status); + return readl(dev->mfc_regs->d_display_status); } static int s5p_mfc_get_dec_status_v6(struct s5p_mfc_dev *dev) { - return READL(dev->mfc_regs->d_decoded_status); + return readl(dev->mfc_regs->d_decoded_status); } static int s5p_mfc_get_dec_frame_type_v6(struct s5p_mfc_dev *dev) { - return READL(dev->mfc_regs->d_decoded_frame_type) & + return readl(dev->mfc_regs->d_decoded_frame_type) & S5P_FIMV_DECODE_FRAME_MASK_V6; } static int s5p_mfc_get_disp_frame_type_v6(struct s5p_mfc_ctx *ctx) { struct s5p_mfc_dev *dev = ctx->dev; - return READL(dev->mfc_regs->d_display_frame_type) & + return readl(dev->mfc_regs->d_display_frame_type) & S5P_FIMV_DECODE_FRAME_MASK_V6; } static int s5p_mfc_get_consumed_stream_v6(struct s5p_mfc_dev *dev) { - return READL(dev->mfc_regs->d_decoded_nal_size); + return readl(dev->mfc_regs->d_decoded_nal_size); } static int s5p_mfc_get_int_reason_v6(struct s5p_mfc_dev *dev) { - return READL(dev->mfc_regs->risc2host_command) & + return readl(dev->mfc_regs->risc2host_command) & S5P_FIMV_RISC2HOST_CMD_MASK; } static int s5p_mfc_get_int_err_v6(struct s5p_mfc_dev *dev) { - return READL(dev->mfc_regs->error_code); + return readl(dev->mfc_regs->error_code); } static int s5p_mfc_err_dec_v6(unsigned int err) @@ -1962,87 +1957,87 @@ static int s5p_mfc_err_dspl_v6(unsigned int err) static int s5p_mfc_get_img_width_v6(struct s5p_mfc_dev *dev) { - return READL(dev->mfc_regs->d_display_frame_width); + return readl(dev->mfc_regs->d_display_frame_width); } static int s5p_mfc_get_img_height_v6(struct s5p_mfc_dev *dev) { - return READL(dev->mfc_regs->d_display_frame_height); + return readl(dev->mfc_regs->d_display_frame_height); } static int s5p_mfc_get_dpb_count_v6(struct s5p_mfc_dev *dev) { - return READL(dev->mfc_regs->d_min_num_dpb); + return readl(dev->mfc_regs->d_min_num_dpb); } static int s5p_mfc_get_mv_count_v6(struct s5p_mfc_dev *dev) { - return READL(dev->mfc_regs->d_min_num_mv); + return readl(dev->mfc_regs->d_min_num_mv); } static int s5p_mfc_get_inst_no_v6(struct s5p_mfc_dev *dev) { - return READL(dev->mfc_regs->ret_instance_id); + return readl(dev->mfc_regs->ret_instance_id); } static int s5p_mfc_get_enc_dpb_count_v6(struct s5p_mfc_dev *dev) { - return READL(dev->mfc_regs->e_num_dpb); + return readl(dev->mfc_regs->e_num_dpb); } static int s5p_mfc_get_enc_strm_size_v6(struct s5p_mfc_dev *dev) { - return READL(dev->mfc_regs->e_stream_size); + return readl(dev->mfc_regs->e_stream_size); } static int s5p_mfc_get_enc_slice_type_v6(struct s5p_mfc_dev *dev) { - return READL(dev->mfc_regs->e_slice_type); + return readl(dev->mfc_regs->e_slice_type); } static int s5p_mfc_get_enc_pic_count_v6(struct s5p_mfc_dev *dev) { - return READL(dev->mfc_regs->e_picture_count); + return readl(dev->mfc_regs->e_picture_count); } static int s5p_mfc_get_sei_avail_status_v6(struct s5p_mfc_ctx *ctx) { struct s5p_mfc_dev *dev = ctx->dev; - return READL(dev->mfc_regs->d_frame_pack_sei_avail); + return readl(dev->mfc_regs->d_frame_pack_sei_avail); } static int s5p_mfc_get_mvc_num_views_v6(struct s5p_mfc_dev *dev) { - return READL(dev->mfc_regs->d_mvc_num_views); + return readl(dev->mfc_regs->d_mvc_num_views); } static int s5p_mfc_get_mvc_view_id_v6(struct s5p_mfc_dev *dev) { - return READL(dev->mfc_regs->d_mvc_view_id); + return readl(dev->mfc_regs->d_mvc_view_id); } static unsigned int s5p_mfc_get_pic_type_top_v6(struct s5p_mfc_ctx *ctx) { return s5p_mfc_read_info_v6(ctx, - (unsigned int) ctx->dev->mfc_regs->d_ret_picture_tag_top); + (__force unsigned long) ctx->dev->mfc_regs->d_ret_picture_tag_top); } static unsigned int s5p_mfc_get_pic_type_bot_v6(struct s5p_mfc_ctx *ctx) { return s5p_mfc_read_info_v6(ctx, - (unsigned int) ctx->dev->mfc_regs->d_ret_picture_tag_bot); + (__force unsigned long) ctx->dev->mfc_regs->d_ret_picture_tag_bot); } static unsigned int s5p_mfc_get_crop_info_h_v6(struct s5p_mfc_ctx *ctx) { return s5p_mfc_read_info_v6(ctx, - (unsigned int) ctx->dev->mfc_regs->d_display_crop_info1); + (__force unsigned long) ctx->dev->mfc_regs->d_display_crop_info1); } static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx) { return s5p_mfc_read_info_v6(ctx, - (unsigned int) ctx->dev->mfc_regs->d_display_crop_info2); + (__force unsigned long) ctx->dev->mfc_regs->d_display_crop_info2); } static struct s5p_mfc_regs mfc_regs; diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_pm.c b/drivers/media/platform/s5p-mfc/s5p_mfc_pm.c index b6a8be97a96c..826c48945bf5 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_pm.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_pm.c @@ -21,7 +21,7 @@ #include "s5p_mfc_pm.h" #define MFC_GATE_CLK_NAME "mfc" -#define MFC_SCLK_NAME "sclk-mfc" +#define MFC_SCLK_NAME "sclk_mfc" #define MFC_SCLK_RATE (200 * 1000000) #define CLK_DEBUG |