diff options
Diffstat (limited to 'drivers/net/ethernet/aquantia/atlantic')
37 files changed, 3912 insertions, 451 deletions
diff --git a/drivers/net/ethernet/aquantia/atlantic/Makefile b/drivers/net/ethernet/aquantia/atlantic/Makefile index 8b555665a33a..130a105d03f3 100644 --- a/drivers/net/ethernet/aquantia/atlantic/Makefile +++ b/drivers/net/ethernet/aquantia/atlantic/Makefile @@ -25,6 +25,10 @@ atlantic-objs := aq_main.o \ hw_atl/hw_atl_utils.o \ hw_atl/hw_atl_utils_fw2x.o \ hw_atl/hw_atl_llh.o \ + hw_atl2/hw_atl2.o \ + hw_atl2/hw_atl2_utils.o \ + hw_atl2/hw_atl2_utils_fw.o \ + hw_atl2/hw_atl2_llh.o \ macsec/macsec_api.o atlantic-$(CONFIG_MACSEC) += aq_macsec.o diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_cfg.h b/drivers/net/ethernet/aquantia/atlantic/aq_cfg.h index 7560f5506e55..52b9833fda99 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_cfg.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_cfg.h @@ -80,8 +80,8 @@ #define AQ_CFG_LOCK_TRYS 100U -#define AQ_CFG_DRV_AUTHOR "aQuantia" -#define AQ_CFG_DRV_DESC "aQuantia Corporation(R) Network Driver" +#define AQ_CFG_DRV_AUTHOR "Marvell" +#define AQ_CFG_DRV_DESC "Marvell (Aquantia) Corporation(R) Network Driver" #define AQ_CFG_DRV_NAME "atlantic" #endif /* AQ_CFG_H */ diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_common.h b/drivers/net/ethernet/aquantia/atlantic/aq_common.h index c8c402b013bb..52ad9433cabc 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_common.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_common.h @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* - * aQuantia Corporation Network Driver - * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved +/* Atlantic Network Driver + * + * Copyright (C) 2014-2019 aQuantia Corporation + * Copyright (C) 2019-2020 Marvell International Ltd. */ /* File aq_common.h: Basic includes for all files in project. */ @@ -37,22 +38,31 @@ #define AQ_DEVICE_ID_AQC111S 0x91B1 #define AQ_DEVICE_ID_AQC112S 0x92B1 -#define HW_ATL_NIC_NAME "aQuantia AQtion 10Gbit Network Adapter" +#define AQ_DEVICE_ID_AQC113DEV 0x00C0 +#define AQ_DEVICE_ID_AQC113CS 0x94C0 +#define AQ_DEVICE_ID_AQC114CS 0x93C0 +#define AQ_DEVICE_ID_AQC113 0x04C0 +#define AQ_DEVICE_ID_AQC113C 0x14C0 +#define AQ_DEVICE_ID_AQC115C 0x12C0 + +#define HW_ATL_NIC_NAME "Marvell (aQuantia) AQtion 10Gbit Network Adapter" #define AQ_HWREV_ANY 0 #define AQ_HWREV_1 1 #define AQ_HWREV_2 2 -#define AQ_NIC_RATE_10G BIT(0) -#define AQ_NIC_RATE_5G BIT(1) -#define AQ_NIC_RATE_5GSR BIT(2) -#define AQ_NIC_RATE_2GS BIT(3) -#define AQ_NIC_RATE_1G BIT(4) -#define AQ_NIC_RATE_100M BIT(5) - -#define AQ_NIC_RATE_EEE_10G BIT(6) -#define AQ_NIC_RATE_EEE_5G BIT(7) -#define AQ_NIC_RATE_EEE_2GS BIT(8) -#define AQ_NIC_RATE_EEE_1G BIT(9) +#define AQ_NIC_RATE_10G BIT(0) +#define AQ_NIC_RATE_5G BIT(1) +#define AQ_NIC_RATE_5GSR BIT(2) +#define AQ_NIC_RATE_2G5 BIT(3) +#define AQ_NIC_RATE_1G BIT(4) +#define AQ_NIC_RATE_100M BIT(5) +#define AQ_NIC_RATE_10M BIT(6) + +#define AQ_NIC_RATE_EEE_10G BIT(7) +#define AQ_NIC_RATE_EEE_5G BIT(8) +#define AQ_NIC_RATE_EEE_2G5 BIT(9) +#define AQ_NIC_RATE_EEE_1G BIT(10) +#define AQ_NIC_RATE_EEE_100M BIT(11) #endif /* AQ_COMMON_H */ diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c b/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c index 7241cf92b43a..743d3b13b39d 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c @@ -88,13 +88,13 @@ static const char aq_ethtool_stat_names[][ETH_GSTRING_LEN] = { "InDroppedDma", }; -static const char aq_ethtool_queue_stat_names[][ETH_GSTRING_LEN] = { - "Queue[%d] InPackets", - "Queue[%d] OutPackets", - "Queue[%d] Restarts", - "Queue[%d] InJumboPackets", - "Queue[%d] InLroPackets", - "Queue[%d] InErrors", +static const char * const aq_ethtool_queue_stat_names[] = { + "%sQueue[%d] InPackets", + "%sQueue[%d] OutPackets", + "%sQueue[%d] Restarts", + "%sQueue[%d] InJumboPackets", + "%sQueue[%d] InLroPackets", + "%sQueue[%d] InErrors", }; #if IS_ENABLED(CONFIG_MACSEC) @@ -166,7 +166,8 @@ static u32 aq_ethtool_n_stats(struct net_device *ndev) struct aq_nic_s *nic = netdev_priv(ndev); struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(nic); u32 n_stats = ARRAY_SIZE(aq_ethtool_stat_names) + - ARRAY_SIZE(aq_ethtool_queue_stat_names) * cfg->vecs; + ARRAY_SIZE(aq_ethtool_queue_stat_names) * cfg->vecs * + cfg->tcs; #if IS_ENABLED(CONFIG_MACSEC) if (nic->macsec_cfg) { @@ -223,7 +224,7 @@ static void aq_ethtool_get_drvinfo(struct net_device *ndev, static void aq_ethtool_get_strings(struct net_device *ndev, u32 stringset, u8 *data) { - struct aq_nic_s *aq_nic = netdev_priv(ndev); + struct aq_nic_s *nic = netdev_priv(ndev); struct aq_nic_cfg_s *cfg; u8 *p = data; int i, si; @@ -231,24 +232,35 @@ static void aq_ethtool_get_strings(struct net_device *ndev, int sa; #endif - cfg = aq_nic_get_cfg(aq_nic); + cfg = aq_nic_get_cfg(nic); switch (stringset) { - case ETH_SS_STATS: + case ETH_SS_STATS: { + const int stat_cnt = ARRAY_SIZE(aq_ethtool_queue_stat_names); + char tc_string[8]; + int tc; + + memset(tc_string, 0, sizeof(tc_string)); memcpy(p, aq_ethtool_stat_names, sizeof(aq_ethtool_stat_names)); p = p + sizeof(aq_ethtool_stat_names); - for (i = 0; i < cfg->vecs; i++) { - for (si = 0; - si < ARRAY_SIZE(aq_ethtool_queue_stat_names); - si++) { - snprintf(p, ETH_GSTRING_LEN, - aq_ethtool_queue_stat_names[si], i); - p += ETH_GSTRING_LEN; + + for (tc = 0; tc < cfg->tcs; tc++) { + if (cfg->is_qos) + snprintf(tc_string, 8, "TC%d ", tc); + + for (i = 0; i < cfg->vecs; i++) { + for (si = 0; si < stat_cnt; si++) { + snprintf(p, ETH_GSTRING_LEN, + aq_ethtool_queue_stat_names[si], + tc_string, + AQ_NIC_CFG_TCVEC2RING(cfg, tc, i)); + p += ETH_GSTRING_LEN; + } } } #if IS_ENABLED(CONFIG_MACSEC) - if (!aq_nic->macsec_cfg) + if (!nic->macsec_cfg) break; memcpy(p, aq_macsec_stat_names, sizeof(aq_macsec_stat_names)); @@ -256,7 +268,7 @@ static void aq_ethtool_get_strings(struct net_device *ndev, for (i = 0; i < AQ_MACSEC_MAX_SC; i++) { struct aq_macsec_txsc *aq_txsc; - if (!(test_bit(i, &aq_nic->macsec_cfg->txsc_idx_busy))) + if (!(test_bit(i, &nic->macsec_cfg->txsc_idx_busy))) continue; for (si = 0; @@ -266,7 +278,7 @@ static void aq_ethtool_get_strings(struct net_device *ndev, aq_macsec_txsc_stat_names[si], i); p += ETH_GSTRING_LEN; } - aq_txsc = &aq_nic->macsec_cfg->aq_txsc[i]; + aq_txsc = &nic->macsec_cfg->aq_txsc[i]; for (sa = 0; sa < MACSEC_NUM_AN; sa++) { if (!(test_bit(sa, &aq_txsc->tx_sa_idx_busy))) continue; @@ -283,10 +295,10 @@ static void aq_ethtool_get_strings(struct net_device *ndev, for (i = 0; i < AQ_MACSEC_MAX_SC; i++) { struct aq_macsec_rxsc *aq_rxsc; - if (!(test_bit(i, &aq_nic->macsec_cfg->rxsc_idx_busy))) + if (!(test_bit(i, &nic->macsec_cfg->rxsc_idx_busy))) continue; - aq_rxsc = &aq_nic->macsec_cfg->aq_rxsc[i]; + aq_rxsc = &nic->macsec_cfg->aq_rxsc[i]; for (sa = 0; sa < MACSEC_NUM_AN; sa++) { if (!(test_bit(sa, &aq_rxsc->rx_sa_idx_busy))) continue; @@ -302,6 +314,7 @@ static void aq_ethtool_get_strings(struct net_device *ndev, } #endif break; + } case ETH_SS_PRIV_FLAGS: memcpy(p, aq_ethtool_priv_flag_names, sizeof(aq_ethtool_priv_flag_names)); @@ -605,12 +618,15 @@ static enum hw_atl_fw2x_rate eee_mask_to_ethtool_mask(u32 speed) if (speed & AQ_NIC_RATE_EEE_10G) rate |= SUPPORTED_10000baseT_Full; - if (speed & AQ_NIC_RATE_EEE_2GS) + if (speed & AQ_NIC_RATE_EEE_2G5) rate |= SUPPORTED_2500baseX_Full; if (speed & AQ_NIC_RATE_EEE_1G) rate |= SUPPORTED_1000baseT_Full; + if (speed & AQ_NIC_RATE_EEE_100M) + rate |= SUPPORTED_100baseT_Full; + return rate; } @@ -777,8 +793,6 @@ static int aq_set_ringparam(struct net_device *ndev, dev_close(ndev); } - aq_nic_free_vectors(aq_nic); - cfg->rxds = max(ring->rx_pending, hw_caps->rxds_min); cfg->rxds = min(cfg->rxds, hw_caps->rxds_max); cfg->rxds = ALIGN(cfg->rxds, AQ_HW_RXD_MULTIPLE); @@ -787,15 +801,10 @@ static int aq_set_ringparam(struct net_device *ndev, cfg->txds = min(cfg->txds, hw_caps->txds_max); cfg->txds = ALIGN(cfg->txds, AQ_HW_TXD_MULTIPLE); - for (aq_nic->aq_vecs = 0; aq_nic->aq_vecs < cfg->vecs; - aq_nic->aq_vecs++) { - aq_nic->aq_vec[aq_nic->aq_vecs] = - aq_vec_alloc(aq_nic, aq_nic->aq_vecs, cfg); - if (unlikely(!aq_nic->aq_vec[aq_nic->aq_vecs])) { - err = -ENOMEM; - goto err_exit; - } - } + err = aq_nic_realloc_vectors(aq_nic); + if (err) + goto err_exit; + if (ndev_running) err = dev_open(ndev, NULL); diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_filters.c b/drivers/net/ethernet/aquantia/atlantic/aq_filters.c index 03ff92bc4a7f..1bc4d33a0ce5 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_filters.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_filters.c @@ -153,6 +153,8 @@ aq_check_approve_fvlan(struct aq_nic_s *aq_nic, struct aq_hw_rx_fltrs_s *rx_fltrs, struct ethtool_rx_flow_spec *fsp) { + struct aq_nic_cfg_s *cfg = &aq_nic->aq_nic_cfg; + if (fsp->location < AQ_RX_FIRST_LOC_FVLANID || fsp->location > AQ_RX_LAST_LOC_FVLANID) { netdev_err(aq_nic->ndev, @@ -170,10 +172,10 @@ aq_check_approve_fvlan(struct aq_nic_s *aq_nic, return -EINVAL; } - if (fsp->ring_cookie > aq_nic->aq_nic_cfg.num_rss_queues) { + if (fsp->ring_cookie > cfg->num_rss_queues * cfg->tcs) { netdev_err(aq_nic->ndev, "ethtool: queue number must be in range [0, %d]", - aq_nic->aq_nic_cfg.num_rss_queues - 1); + cfg->num_rss_queues * cfg->tcs - 1); return -EINVAL; } return 0; @@ -262,6 +264,7 @@ static bool __must_check aq_rule_is_not_correct(struct aq_nic_s *aq_nic, struct ethtool_rx_flow_spec *fsp) { + struct aq_nic_cfg_s *cfg = &aq_nic->aq_nic_cfg; bool rule_is_not_correct = false; if (!aq_nic) { @@ -274,11 +277,11 @@ aq_rule_is_not_correct(struct aq_nic_s *aq_nic, } else if (aq_check_filter(aq_nic, fsp)) { rule_is_not_correct = true; } else if (fsp->ring_cookie != RX_CLS_FLOW_DISC) { - if (fsp->ring_cookie >= aq_nic->aq_nic_cfg.num_rss_queues) { + if (fsp->ring_cookie >= cfg->num_rss_queues * cfg->tcs) { netdev_err(aq_nic->ndev, "ethtool: The specified action is invalid.\n" "Maximum allowable value action is %u.\n", - aq_nic->aq_nic_cfg.num_rss_queues - 1); + cfg->num_rss_queues * cfg->tcs - 1); rule_is_not_correct = true; } } diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h index 7d71bc7dc500..ed5b465bc664 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h @@ -18,6 +18,12 @@ #define AQ_HW_MAC_COUNTER_HZ 312500000ll #define AQ_HW_PHY_COUNTER_HZ 160000000ll +enum aq_tc_mode { + AQ_TC_MODE_INVALID = -1, + AQ_TC_MODE_8TCS, + AQ_TC_MODE_4TCS, +}; + #define AQ_RX_FIRST_LOC_FVLANID 0U #define AQ_RX_LAST_LOC_FVLANID 15U #define AQ_RX_FIRST_LOC_FETHERT 16U @@ -29,6 +35,9 @@ (AQ_RX_LAST_LOC_FVLANID - AQ_RX_FIRST_LOC_FVLANID + 1U) #define AQ_RX_QUEUE_NOT_ASSIGNED 0xFFU +/* Used for rate to Mbps conversion */ +#define AQ_MBPS_DIVISOR 125000 /* 1000000 / 8 */ + /* NIC H/W capabilities */ struct aq_hw_caps_s { u64 hw_features; @@ -46,7 +55,7 @@ struct aq_hw_caps_s { u32 mac_regs_count; u32 hw_alive_check_addr; u8 msix_irqs; - u8 tcs; + u8 tcs_max; u8 rxd_alignment; u8 rxd_size; u8 txd_alignment; @@ -55,6 +64,7 @@ struct aq_hw_caps_s { u8 rx_rings; bool flow_control; bool is_64_dma; + u32 priv_data_len; }; struct aq_hw_link_status_s { @@ -117,8 +127,11 @@ struct aq_stats_s { #define AQ_HW_TXD_MULTIPLE 8U #define AQ_HW_RXD_MULTIPLE 8U +#define AQ_HW_QUEUES_MAX 32U #define AQ_HW_MULTICAST_ADDRESS_MAX 32U +#define AQ_HW_PTP_TC 2U + #define AQ_HW_LED_BLINK 0x2U #define AQ_HW_LED_DEFAULT 0x0U @@ -136,6 +149,19 @@ enum aq_priv_flags { BIT(AQ_HW_LOOPBACK_PHYINT_SYS) |\ BIT(AQ_HW_LOOPBACK_PHYEXT_SYS)) +#define ATL_HW_CHIP_MIPS 0x00000001U +#define ATL_HW_CHIP_TPO2 0x00000002U +#define ATL_HW_CHIP_RPF2 0x00000004U +#define ATL_HW_CHIP_MPI_AQ 0x00000010U +#define ATL_HW_CHIP_ATLANTIC 0x00800000U +#define ATL_HW_CHIP_REVISION_A0 0x01000000U +#define ATL_HW_CHIP_REVISION_B0 0x02000000U +#define ATL_HW_CHIP_REVISION_B1 0x04000000U +#define ATL_HW_CHIP_ANTIGUA 0x08000000U + +#define ATL_HW_IS_CHIP_FEATURE(_HW_, _F_) (!!(ATL_HW_CHIP_##_F_ & \ + (_HW_)->chip_features)) + struct aq_hw_s { atomic_t flags; u8 rbl_enabled:1; @@ -159,6 +185,7 @@ struct aq_hw_s { struct hw_atl_utils_fw_rpc rpc; s64 ptp_clk_offset; u16 phy_id; + void *priv; }; struct aq_ring_s; @@ -182,6 +209,11 @@ struct aq_hw_ops { int (*hw_set_mac_address)(struct aq_hw_s *self, u8 *mac_addr); + int (*hw_soft_reset)(struct aq_hw_s *self); + + int (*hw_prepare)(struct aq_hw_s *self, + const struct aq_fw_ops **fw_ops); + int (*hw_reset)(struct aq_hw_s *self); int (*hw_init)(struct aq_hw_s *self, u8 *mac_addr); @@ -248,21 +280,19 @@ struct aq_hw_ops { int (*hw_rss_hash_set)(struct aq_hw_s *self, struct aq_rss_parameters *rss_params); + int (*hw_tc_rate_limit_set)(struct aq_hw_s *self); + int (*hw_get_regs)(struct aq_hw_s *self, const struct aq_hw_caps_s *aq_hw_caps, u32 *regs_buff); struct aq_stats_s *(*hw_get_hw_stats)(struct aq_hw_s *self); - int (*hw_get_fw_version)(struct aq_hw_s *self, u32 *fw_version); + u32 (*hw_get_fw_version)(struct aq_hw_s *self); int (*hw_set_offload)(struct aq_hw_s *self, struct aq_nic_cfg_s *aq_nic_cfg); - int (*hw_tx_tc_mode_get)(struct aq_hw_s *self, u32 *tc_mode); - - int (*hw_rx_tc_mode_get)(struct aq_hw_s *self, u32 *tc_mode); - int (*hw_ring_hwts_rx_fill)(struct aq_hw_s *self, struct aq_ring_s *aq_ring); diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c index 7dbf49adcea6..342c5179f846 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c @@ -79,3 +79,29 @@ int aq_hw_err_from_flags(struct aq_hw_s *hw) err_exit: return err; } + +int aq_hw_num_tcs(struct aq_hw_s *hw) +{ + switch (hw->aq_nic_cfg->tc_mode) { + case AQ_TC_MODE_8TCS: + return 8; + case AQ_TC_MODE_4TCS: + return 4; + default: + break; + } + + return 1; +} + +int aq_hw_q_per_tc(struct aq_hw_s *hw) +{ + switch (hw->aq_nic_cfg->tc_mode) { + case AQ_TC_MODE_8TCS: + return 4; + case AQ_TC_MODE_4TCS: + return 8; + default: + return 4; + } +} diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h index 9ef82d487e01..32aa5f2fb840 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h @@ -34,5 +34,7 @@ u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg); void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value); u64 aq_hw_read_reg64(struct aq_hw_s *hw, u32 reg); int aq_hw_err_from_flags(struct aq_hw_s *hw); +int aq_hw_num_tcs(struct aq_hw_s *hw); +int aq_hw_q_per_tc(struct aq_hw_s *hw); #endif /* AQ_HW_UTILS_H */ diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_macsec.c b/drivers/net/ethernet/aquantia/atlantic/aq_macsec.c index 0b3e234a54aa..4a6dfac857ca 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_macsec.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_macsec.c @@ -401,7 +401,7 @@ static u32 aq_sc_idx_max(const enum aq_macsec_sc_sa sc_sa) break; default: break; - }; + } return result; } @@ -417,7 +417,7 @@ static u32 aq_to_hw_sc_idx(const u32 sc_idx, const enum aq_macsec_sc_sa sc_sa) return sc_idx; default: WARN_ONCE(true, "Invalid sc_sa"); - }; + } return sc_idx; } @@ -478,7 +478,7 @@ static int aq_mdo_add_secy(struct macsec_context *ctx) set_bit(txsc_idx, &cfg->txsc_idx_busy); - return 0; + return ret; } static int aq_mdo_upd_secy(struct macsec_context *ctx) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_main.c b/drivers/net/ethernet/aquantia/atlantic/aq_main.c index 9fcab646cbd5..8a1da044e908 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_main.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_main.c @@ -12,11 +12,13 @@ #include "aq_ethtool.h" #include "aq_ptp.h" #include "aq_filters.h" +#include "aq_hw_utils.h" #include <linux/netdevice.h> #include <linux/module.h> #include <linux/ip.h> #include <linux/udp.h> +#include <net/pkt_cls.h> MODULE_LICENSE("GPL v2"); MODULE_AUTHOR(AQ_CFG_DRV_AUTHOR); @@ -38,7 +40,7 @@ struct net_device *aq_ndev_alloc(void) struct net_device *ndev = NULL; struct aq_nic_s *aq_nic = NULL; - ndev = alloc_etherdev_mq(sizeof(struct aq_nic_s), AQ_CFG_VECS_MAX); + ndev = alloc_etherdev_mq(sizeof(struct aq_nic_s), AQ_HW_QUEUES_MAX); if (!ndev) return NULL; @@ -330,6 +332,73 @@ static int aq_ndo_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, return 0; } +static int aq_validate_mqprio_opt(struct aq_nic_s *self, + struct tc_mqprio_qopt_offload *mqprio, + const unsigned int num_tc) +{ + const bool has_min_rate = !!(mqprio->flags & TC_MQPRIO_F_MIN_RATE); + struct aq_nic_cfg_s *aq_nic_cfg = aq_nic_get_cfg(self); + const unsigned int tcs_max = min_t(u8, aq_nic_cfg->aq_hw_caps->tcs_max, + AQ_CFG_TCS_MAX); + + if (num_tc > tcs_max) { + netdev_err(self->ndev, "Too many TCs requested\n"); + return -EOPNOTSUPP; + } + + if (num_tc != 0 && !is_power_of_2(num_tc)) { + netdev_err(self->ndev, "TC count should be power of 2\n"); + return -EOPNOTSUPP; + } + + if (has_min_rate && !ATL_HW_IS_CHIP_FEATURE(self->aq_hw, ANTIGUA)) { + netdev_err(self->ndev, "Min tx rate is not supported\n"); + return -EOPNOTSUPP; + } + + return 0; +} + +static int aq_ndo_setup_tc(struct net_device *dev, enum tc_setup_type type, + void *type_data) +{ + struct tc_mqprio_qopt_offload *mqprio = type_data; + struct aq_nic_s *aq_nic = netdev_priv(dev); + bool has_min_rate; + bool has_max_rate; + int err; + int i; + + if (type != TC_SETUP_QDISC_MQPRIO) + return -EOPNOTSUPP; + + has_min_rate = !!(mqprio->flags & TC_MQPRIO_F_MIN_RATE); + has_max_rate = !!(mqprio->flags & TC_MQPRIO_F_MAX_RATE); + + err = aq_validate_mqprio_opt(aq_nic, mqprio, mqprio->qopt.num_tc); + if (err) + return err; + + for (i = 0; i < mqprio->qopt.num_tc; i++) { + if (has_max_rate) { + u64 max_rate = mqprio->max_rate[i]; + + do_div(max_rate, AQ_MBPS_DIVISOR); + aq_nic_setup_tc_max_rate(aq_nic, i, (u32)max_rate); + } + + if (has_min_rate) { + u64 min_rate = mqprio->min_rate[i]; + + do_div(min_rate, AQ_MBPS_DIVISOR); + aq_nic_setup_tc_min_rate(aq_nic, i, (u32)min_rate); + } + } + + return aq_nic_setup_tc_mqprio(aq_nic, mqprio->qopt.num_tc, + mqprio->qopt.prio_tc_map); +} + static const struct net_device_ops aq_ndev_ops = { .ndo_open = aq_ndev_open, .ndo_stop = aq_ndev_close, @@ -341,6 +410,7 @@ static const struct net_device_ops aq_ndev_ops = { .ndo_do_ioctl = aq_ndev_ioctl, .ndo_vlan_rx_add_vid = aq_ndo_vlan_rx_add_vid, .ndo_vlan_rx_kill_vid = aq_ndo_vlan_rx_kill_vid, + .ndo_setup_tc = aq_ndo_setup_tc, }; static int __init aq_ndev_init_module(void) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c index a369705a786a..4435c6374f7e 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only -/* - * aQuantia Corporation Network Driver - * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved +/* Atlantic Network Driver + * + * Copyright (C) 2014-2019 aQuantia Corporation + * Copyright (C) 2019-2020 Marvell International Ltd. */ /* File aq_nic.c: Definition of common code for NIC. */ @@ -25,6 +26,7 @@ #include <linux/ip.h> #include <linux/tcp.h> #include <net/ip.h> +#include <net/pkt_cls.h> static unsigned int aq_itr = AQ_CFG_INTERRUPT_MODERATION_AUTO; module_param_named(aq_itr, aq_itr, uint, 0644); @@ -63,10 +65,38 @@ static void aq_nic_rss_init(struct aq_nic_s *self, unsigned int num_rss_queues) rss_params->indirection_table[i] = i & (num_rss_queues - 1); } +/* Recalculate the number of vectors */ +static void aq_nic_cfg_update_num_vecs(struct aq_nic_s *self) +{ + struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg; + + cfg->vecs = min(cfg->aq_hw_caps->vecs, AQ_CFG_VECS_DEF); + cfg->vecs = min(cfg->vecs, num_online_cpus()); + if (self->irqvecs > AQ_HW_SERVICE_IRQS) + cfg->vecs = min(cfg->vecs, self->irqvecs - AQ_HW_SERVICE_IRQS); + /* cfg->vecs should be power of 2 for RSS */ + cfg->vecs = rounddown_pow_of_two(cfg->vecs); + + if (ATL_HW_IS_CHIP_FEATURE(self->aq_hw, ANTIGUA)) { + if (cfg->tcs > 2) + cfg->vecs = min(cfg->vecs, 4U); + } + + if (cfg->vecs <= 4) + cfg->tc_mode = AQ_TC_MODE_8TCS; + else + cfg->tc_mode = AQ_TC_MODE_4TCS; + + /*rss rings */ + cfg->num_rss_queues = min(cfg->vecs, AQ_CFG_NUM_RSS_QUEUES_DEF); + aq_nic_rss_init(self, cfg->num_rss_queues); +} + /* Checks hw_caps and 'corrects' aq_nic_cfg in runtime */ void aq_nic_cfg_start(struct aq_nic_s *self) { struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg; + int i; cfg->tcs = AQ_CFG_TCS_DEF; @@ -78,7 +108,6 @@ void aq_nic_cfg_start(struct aq_nic_s *self) cfg->rxpageorder = AQ_CFG_RX_PAGEORDER; cfg->is_rss = AQ_CFG_IS_RSS_DEF; - cfg->num_rss_queues = AQ_CFG_NUM_RSS_QUEUES_DEF; cfg->aq_rss.base_cpu_number = AQ_CFG_RSS_BASE_CPU_NUM_DEF; cfg->fc.req = AQ_CFG_FC_MODE; cfg->wol = AQ_CFG_WOL_MODES; @@ -88,29 +117,13 @@ void aq_nic_cfg_start(struct aq_nic_s *self) cfg->is_autoneg = AQ_CFG_IS_AUTONEG_DEF; cfg->is_lro = AQ_CFG_IS_LRO_DEF; + cfg->is_ptp = true; /*descriptors */ cfg->rxds = min(cfg->aq_hw_caps->rxds_max, AQ_CFG_RXDS_DEF); cfg->txds = min(cfg->aq_hw_caps->txds_max, AQ_CFG_TXDS_DEF); - /*rss rings */ - cfg->vecs = min(cfg->aq_hw_caps->vecs, AQ_CFG_VECS_DEF); - cfg->vecs = min(cfg->vecs, num_online_cpus()); - if (self->irqvecs > AQ_HW_SERVICE_IRQS) - cfg->vecs = min(cfg->vecs, self->irqvecs - AQ_HW_SERVICE_IRQS); - /* cfg->vecs should be power of 2 for RSS */ - if (cfg->vecs >= 8U) - cfg->vecs = 8U; - else if (cfg->vecs >= 4U) - cfg->vecs = 4U; - else if (cfg->vecs >= 2U) - cfg->vecs = 2U; - else - cfg->vecs = 1U; - - cfg->num_rss_queues = min(cfg->vecs, AQ_CFG_NUM_RSS_QUEUES_DEF); - - aq_nic_rss_init(self, cfg->num_rss_queues); + aq_nic_cfg_update_num_vecs(self); cfg->irq_type = aq_pci_func_get_irq_type(self); @@ -135,6 +148,9 @@ void aq_nic_cfg_start(struct aq_nic_s *self) cfg->is_vlan_rx_strip = !!(cfg->features & NETIF_F_HW_VLAN_CTAG_RX); cfg->is_vlan_tx_insert = !!(cfg->features & NETIF_F_HW_VLAN_CTAG_TX); cfg->is_vlan_force_promisc = true; + + for (i = 0; i < sizeof(cfg->prio_tc_map); i++) + cfg->prio_tc_map[i] = cfg->tcs * i / 8; } static int aq_nic_update_link_status(struct aq_nic_s *self) @@ -180,6 +196,9 @@ static int aq_nic_update_link_status(struct aq_nic_s *self) #if IS_ENABLED(CONFIG_MACSEC) aq_macsec_enable(self); #endif + if (self->aq_hw_ops->hw_tc_rate_limit_set) + self->aq_hw_ops->hw_tc_rate_limit_set(self->aq_hw); + netif_tx_wake_all_queues(self->ndev); } if (netif_carrier_ok(self->ndev) && !self->link_status.mbps) { @@ -257,6 +276,28 @@ static void aq_nic_polling_timer_cb(struct timer_list *t) AQ_CFG_POLLING_TIMER_INTERVAL); } +static int aq_nic_hw_prepare(struct aq_nic_s *self) +{ + int err = 0; + + err = self->aq_hw_ops->hw_soft_reset(self->aq_hw); + if (err) + goto exit; + + err = self->aq_hw_ops->hw_prepare(self->aq_hw, &self->aq_fw_ops); + +exit: + return err; +} + +static bool aq_nic_is_valid_ether_addr(const u8 *addr) +{ + /* Some engineering samples of Aquantia NICs are provisioned with a + * partially populated MAC, which is still invalid. + */ + return !(addr[0] == 0 && addr[1] == 0 && addr[2] == 0); +} + int aq_nic_ndev_register(struct aq_nic_s *self) { int err = 0; @@ -266,7 +307,7 @@ int aq_nic_ndev_register(struct aq_nic_s *self) goto err_exit; } - err = hw_atl_utils_initfw(self->aq_hw, &self->aq_fw_ops); + err = aq_nic_hw_prepare(self); if (err) goto err_exit; @@ -281,6 +322,12 @@ int aq_nic_ndev_register(struct aq_nic_s *self) if (err) goto err_exit; + if (!is_valid_ether_addr(self->ndev->dev_addr) || + !aq_nic_is_valid_ether_addr(self->ndev->dev_addr)) { + netdev_warn(self->ndev, "MAC is invalid, will use random."); + eth_hw_addr_random(self->ndev); + } + #if defined(AQ_CFG_MAC_ADDR_PERMANENT) { static u8 mac_addr_permanent[] = AQ_CFG_MAC_ADDR_PERMANENT; @@ -364,26 +411,35 @@ int aq_nic_init(struct aq_nic_s *self) if (err < 0) goto err_exit; - if (self->aq_nic_cfg.aq_hw_caps->media_type == AQ_HW_MEDIA_TYPE_TP) { + if (ATL_HW_IS_CHIP_FEATURE(self->aq_hw, ATLANTIC) && + self->aq_nic_cfg.aq_hw_caps->media_type == AQ_HW_MEDIA_TYPE_TP) { self->aq_hw->phy_id = HW_ATL_PHY_ID_MAX; err = aq_phy_init(self->aq_hw); } - for (i = 0U, aq_vec = self->aq_vec[0]; - self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) + for (i = 0U; i < self->aq_vecs; i++) { + aq_vec = self->aq_vec[i]; + err = aq_vec_ring_alloc(aq_vec, self, i, + aq_nic_get_cfg(self)); + if (err) + goto err_exit; + aq_vec_init(aq_vec, self->aq_hw_ops, self->aq_hw); + } - err = aq_ptp_init(self, self->irqvecs - 1); - if (err < 0) - goto err_exit; + if (aq_nic_get_cfg(self)->is_ptp) { + err = aq_ptp_init(self, self->irqvecs - 1); + if (err < 0) + goto err_exit; - err = aq_ptp_ring_alloc(self); - if (err < 0) - goto err_exit; + err = aq_ptp_ring_alloc(self); + if (err < 0) + goto err_exit; - err = aq_ptp_ring_init(self); - if (err < 0) - goto err_exit; + err = aq_ptp_ring_init(self); + if (err < 0) + goto err_exit; + } netif_carrier_off(self->ndev); @@ -394,9 +450,12 @@ err_exit: int aq_nic_start(struct aq_nic_s *self) { struct aq_vec_s *aq_vec = NULL; + struct aq_nic_cfg_s *cfg; unsigned int i = 0U; int err = 0; + cfg = aq_nic_get_cfg(self); + err = self->aq_hw_ops->hw_multicast_list_set(self->aq_hw, self->mc_list.ar, self->mc_list.count); @@ -434,7 +493,7 @@ int aq_nic_start(struct aq_nic_s *self) timer_setup(&self->service_timer, aq_nic_service_timer_cb, 0); aq_nic_service_timer_cb(&self->service_timer); - if (self->aq_nic_cfg.is_polling) { + if (cfg->is_polling) { timer_setup(&self->polling_timer, aq_nic_polling_timer_cb, 0); mod_timer(&self->polling_timer, jiffies + AQ_CFG_POLLING_TIMER_INTERVAL); @@ -452,16 +511,16 @@ int aq_nic_start(struct aq_nic_s *self) if (err < 0) goto err_exit; - if (self->aq_nic_cfg.link_irq_vec) { + if (cfg->link_irq_vec) { int irqvec = pci_irq_vector(self->pdev, - self->aq_nic_cfg.link_irq_vec); + cfg->link_irq_vec); err = request_threaded_irq(irqvec, NULL, aq_linkstate_threaded_isr, IRQF_SHARED | IRQF_ONESHOT, self->ndev->name, self); if (err < 0) goto err_exit; - self->msix_entry_mask |= (1 << self->aq_nic_cfg.link_irq_vec); + self->msix_entry_mask |= (1 << cfg->link_irq_vec); } err = self->aq_hw_ops->hw_irq_enable(self->aq_hw, @@ -470,14 +529,21 @@ int aq_nic_start(struct aq_nic_s *self) goto err_exit; } - err = netif_set_real_num_tx_queues(self->ndev, self->aq_vecs); + err = netif_set_real_num_tx_queues(self->ndev, + self->aq_vecs * cfg->tcs); if (err < 0) goto err_exit; - err = netif_set_real_num_rx_queues(self->ndev, self->aq_vecs); + err = netif_set_real_num_rx_queues(self->ndev, + self->aq_vecs * cfg->tcs); if (err < 0) goto err_exit; + for (i = 0; i < cfg->tcs; i++) { + u16 offset = self->aq_vecs * i; + + netdev_set_tc_queue(self->ndev, i, self->aq_vecs, offset); + } netif_tx_start_all_queues(self->ndev); err_exit: @@ -488,6 +554,8 @@ unsigned int aq_nic_map_skb(struct aq_nic_s *self, struct sk_buff *skb, struct aq_ring_s *ring) { unsigned int nr_frags = skb_shinfo(skb)->nr_frags; + struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(self); + struct device *dev = aq_nic_get_dev(self); struct aq_ring_buff_s *first = NULL; u8 ipver = ip_hdr(skb)->version; struct aq_ring_buff_s *dx_buff; @@ -529,7 +597,7 @@ unsigned int aq_nic_map_skb(struct aq_nic_s *self, struct sk_buff *skb, need_context_tag = true; } - if (self->aq_nic_cfg.is_vlan_tx_insert && skb_vlan_tag_present(skb)) { + if (cfg->is_vlan_tx_insert && skb_vlan_tag_present(skb)) { dx_buff->vlan_tx_tag = skb_vlan_tag_get(skb); dx_buff->len_pkt = skb->len; dx_buff->is_vlan = 1U; @@ -544,12 +612,12 @@ unsigned int aq_nic_map_skb(struct aq_nic_s *self, struct sk_buff *skb, } dx_buff->len = skb_headlen(skb); - dx_buff->pa = dma_map_single(aq_nic_get_dev(self), + dx_buff->pa = dma_map_single(dev, skb->data, dx_buff->len, DMA_TO_DEVICE); - if (unlikely(dma_mapping_error(aq_nic_get_dev(self), dx_buff->pa))) { + if (unlikely(dma_mapping_error(dev, dx_buff->pa))) { ret = 0; goto exit; } @@ -581,13 +649,13 @@ unsigned int aq_nic_map_skb(struct aq_nic_s *self, struct sk_buff *skb, else buff_size = frag_len; - frag_pa = skb_frag_dma_map(aq_nic_get_dev(self), + frag_pa = skb_frag_dma_map(dev, frag, buff_offset, buff_size, DMA_TO_DEVICE); - if (unlikely(dma_mapping_error(aq_nic_get_dev(self), + if (unlikely(dma_mapping_error(dev, frag_pa))) goto mapping_error; @@ -621,12 +689,12 @@ mapping_error: if (!(dx_buff->is_gso_tcp || dx_buff->is_gso_udp) && !dx_buff->is_vlan && dx_buff->pa) { if (unlikely(dx_buff->is_sop)) { - dma_unmap_single(aq_nic_get_dev(self), + dma_unmap_single(dev, dx_buff->pa, dx_buff->len, DMA_TO_DEVICE); } else { - dma_unmap_page(aq_nic_get_dev(self), + dma_unmap_page(dev, dx_buff->pa, dx_buff->len, DMA_TO_DEVICE); @@ -640,15 +708,16 @@ exit: int aq_nic_xmit(struct aq_nic_s *self, struct sk_buff *skb) { - unsigned int vec = skb->queue_mapping % self->aq_nic_cfg.vecs; + struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(self); + unsigned int vec = skb->queue_mapping % cfg->vecs; + unsigned int tc = skb->queue_mapping / cfg->vecs; struct aq_ring_s *ring = NULL; unsigned int frags = 0U; int err = NETDEV_TX_OK; - unsigned int tc = 0U; frags = skb_shinfo(skb)->nr_frags + 1; - ring = self->aq_ring_tx[AQ_NIC_TCVEC2RING(self, tc, vec)]; + ring = self->aq_ring_tx[AQ_NIC_CFG_TCVEC2RING(cfg, tc, vec)]; if (frags > AQ_CFG_SKB_FRAGS_MAX) { dev_kfree_skb_any(skb); @@ -657,13 +726,14 @@ int aq_nic_xmit(struct aq_nic_s *self, struct sk_buff *skb) aq_ring_update_queue_state(ring); - if (self->aq_nic_cfg.priv_flags & BIT(AQ_HW_LOOPBACK_DMA_NET)) { + if (cfg->priv_flags & BIT(AQ_HW_LOOPBACK_DMA_NET)) { err = NETDEV_TX_BUSY; goto err_exit; } /* Above status update may stop the queue. Check this. */ - if (__netif_subqueue_stopped(self->ndev, ring->idx)) { + if (__netif_subqueue_stopped(self->ndev, + AQ_NIC_RING2QMAP(self, ring->idx))) { err = NETDEV_TX_BUSY; goto err_exit; } @@ -764,6 +834,9 @@ int aq_nic_get_regs(struct aq_nic_s *self, struct ethtool_regs *regs, void *p) u32 *regs_buff = p; int err = 0; + if (unlikely(!self->aq_hw_ops->hw_get_regs)) + return -EOPNOTSUPP; + regs->version = 1; err = self->aq_hw_ops->hw_get_regs(self->aq_hw, @@ -778,6 +851,9 @@ err_exit: int aq_nic_get_regs_count(struct aq_nic_s *self) { + if (unlikely(!self->aq_hw_ops->hw_get_regs)) + return 0; + return self->aq_nic_cfg.aq_hw_caps->mac_regs_count; } @@ -787,6 +863,7 @@ u64 *aq_nic_get_stats(struct aq_nic_s *self, u64 *data) struct aq_stats_s *stats; unsigned int count = 0U; unsigned int i = 0U; + unsigned int tc; if (self->aq_fw_ops->update_stats) { mutex_lock(&self->fwreq_mutex); @@ -825,10 +902,13 @@ u64 *aq_nic_get_stats(struct aq_nic_s *self, u64 *data) data += i; - for (i = 0U, aq_vec = self->aq_vec[0]; - aq_vec && self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) { - data += count; - aq_vec_get_sw_stats(aq_vec, data, &count); + for (tc = 0U; tc < self->aq_nic_cfg.tcs; tc++) { + for (i = 0U, aq_vec = self->aq_vec[0]; + aq_vec && self->aq_vecs > i; + ++i, aq_vec = self->aq_vec[i]) { + data += count; + aq_vec_get_sw_stats(aq_vec, tc, data, &count); + } } data += count; @@ -873,7 +953,7 @@ void aq_nic_get_link_ksettings(struct aq_nic_s *self, ethtool_link_ksettings_add_link_mode(cmd, supported, 5000baseT_Full); - if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_2GS) + if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_2G5) ethtool_link_ksettings_add_link_mode(cmd, supported, 2500baseT_Full); @@ -885,6 +965,10 @@ void aq_nic_get_link_ksettings(struct aq_nic_s *self, ethtool_link_ksettings_add_link_mode(cmd, supported, 100baseT_Full); + if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_10M) + ethtool_link_ksettings_add_link_mode(cmd, supported, + 10baseT_Full); + if (self->aq_nic_cfg.aq_hw_caps->flow_control) { ethtool_link_ksettings_add_link_mode(cmd, supported, Pause); @@ -912,7 +996,7 @@ void aq_nic_get_link_ksettings(struct aq_nic_s *self, ethtool_link_ksettings_add_link_mode(cmd, advertising, 5000baseT_Full); - if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_2GS) + if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_2G5) ethtool_link_ksettings_add_link_mode(cmd, advertising, 2500baseT_Full); @@ -924,6 +1008,10 @@ void aq_nic_get_link_ksettings(struct aq_nic_s *self, ethtool_link_ksettings_add_link_mode(cmd, advertising, 100baseT_Full); + if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_10M) + ethtool_link_ksettings_add_link_mode(cmd, advertising, + 10baseT_Full); + if (self->aq_nic_cfg.fc.cur & AQ_NIC_FC_RX) ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause); @@ -954,6 +1042,10 @@ int aq_nic_set_link_ksettings(struct aq_nic_s *self, speed = cmd->base.speed; switch (speed) { + case SPEED_10: + rate = AQ_NIC_RATE_10M; + break; + case SPEED_100: rate = AQ_NIC_RATE_100M; break; @@ -963,7 +1055,7 @@ int aq_nic_set_link_ksettings(struct aq_nic_s *self, break; case SPEED_2500: - rate = AQ_NIC_RATE_2GS; + rate = AQ_NIC_RATE_2G5; break; case SPEED_5000: @@ -1006,11 +1098,7 @@ struct aq_nic_cfg_s *aq_nic_get_cfg(struct aq_nic_s *self) u32 aq_nic_get_fw_version(struct aq_nic_s *self) { - u32 fw_version = 0U; - - self->aq_hw_ops->hw_get_fw_version(self->aq_hw, &fw_version); - - return fw_version; + return self->aq_hw_ops->hw_get_fw_version(self->aq_hw); } int aq_nic_set_loopback(struct aq_nic_s *self) @@ -1101,9 +1189,11 @@ void aq_nic_deinit(struct aq_nic_s *self, bool link_down) if (!self) goto err_exit; - for (i = 0U, aq_vec = self->aq_vec[0]; - self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) + for (i = 0U; i < self->aq_vecs; i++) { + aq_vec = self->aq_vec[i]; aq_vec_deinit(aq_vec); + aq_vec_ring_free(aq_vec); + } aq_ptp_unregister(self); aq_ptp_ring_deinit(self); @@ -1136,6 +1226,22 @@ void aq_nic_free_vectors(struct aq_nic_s *self) err_exit:; } +int aq_nic_realloc_vectors(struct aq_nic_s *self) +{ + struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(self); + + aq_nic_free_vectors(self); + + for (self->aq_vecs = 0; self->aq_vecs < cfg->vecs; self->aq_vecs++) { + self->aq_vec[self->aq_vecs] = aq_vec_alloc(self, self->aq_vecs, + cfg); + if (unlikely(!self->aq_vec[self->aq_vecs])) + return -ENOMEM; + } + + return 0; +} + void aq_nic_shutdown(struct aq_nic_s *self) { int err = 0; @@ -1201,3 +1307,98 @@ void aq_nic_release_filter(struct aq_nic_s *self, enum aq_rx_filter_type type, break; } } + +int aq_nic_setup_tc_mqprio(struct aq_nic_s *self, u32 tcs, u8 *prio_tc_map) +{ + struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg; + const unsigned int prev_vecs = cfg->vecs; + bool ndev_running; + int err = 0; + int i; + + /* if already the same configuration or + * disable request (tcs is 0) and we already is disabled + */ + if (tcs == cfg->tcs || (tcs == 0 && !cfg->is_qos)) + return 0; + + ndev_running = netif_running(self->ndev); + if (ndev_running) + dev_close(self->ndev); + + cfg->tcs = tcs; + if (cfg->tcs == 0) + cfg->tcs = 1; + if (prio_tc_map) + memcpy(cfg->prio_tc_map, prio_tc_map, sizeof(cfg->prio_tc_map)); + else + for (i = 0; i < sizeof(cfg->prio_tc_map); i++) + cfg->prio_tc_map[i] = cfg->tcs * i / 8; + + cfg->is_qos = (tcs != 0 ? true : false); + cfg->is_ptp = (cfg->tcs <= AQ_HW_PTP_TC); + if (!cfg->is_ptp) + netdev_warn(self->ndev, "%s\n", + "PTP is auto disabled due to requested TC count."); + + netdev_set_num_tc(self->ndev, cfg->tcs); + + /* Changing the number of TCs might change the number of vectors */ + aq_nic_cfg_update_num_vecs(self); + if (prev_vecs != cfg->vecs) { + err = aq_nic_realloc_vectors(self); + if (err) + goto err_exit; + } + + if (ndev_running) + err = dev_open(self->ndev, NULL); + +err_exit: + return err; +} + +int aq_nic_setup_tc_max_rate(struct aq_nic_s *self, const unsigned int tc, + const u32 max_rate) +{ + struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg; + + if (tc >= AQ_CFG_TCS_MAX) + return -EINVAL; + + if (max_rate && max_rate < 10) { + netdev_warn(self->ndev, + "Setting %s to the minimum usable value of %dMbps.\n", + "max rate", 10); + cfg->tc_max_rate[tc] = 10; + } else { + cfg->tc_max_rate[tc] = max_rate; + } + + return 0; +} + +int aq_nic_setup_tc_min_rate(struct aq_nic_s *self, const unsigned int tc, + const u32 min_rate) +{ + struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg; + + if (tc >= AQ_CFG_TCS_MAX) + return -EINVAL; + + if (min_rate) + set_bit(tc, &cfg->tc_min_rate_msk); + else + clear_bit(tc, &cfg->tc_min_rate_msk); + + if (min_rate && min_rate < 20) { + netdev_warn(self->ndev, + "Setting %s to the minimum usable value of %dMbps.\n", + "min rate", 20); + cfg->tc_min_rate[tc] = 20; + } else { + cfg->tc_min_rate[tc] = min_rate; + } + + return 0; +} diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic.h b/drivers/net/ethernet/aquantia/atlantic/aq_nic.h index 0663b8d0220d..2ab003065e62 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_nic.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic.h @@ -59,8 +59,15 @@ struct aq_nic_cfg_s { bool is_polling; bool is_rss; bool is_lro; + bool is_qos; + bool is_ptp; + enum aq_tc_mode tc_mode; u32 priv_flags; u8 tcs; + u8 prio_tc_map[8]; + u32 tc_max_rate[AQ_CFG_TCS_MAX]; + unsigned long tc_min_rate_msk; + u32 tc_min_rate[AQ_CFG_TCS_MAX]; struct aq_rss_parameters aq_rss; u32 eee_speeds; }; @@ -77,8 +84,16 @@ struct aq_nic_cfg_s { #define AQ_NIC_WOL_MODES (WAKE_MAGIC |\ WAKE_PHY) -#define AQ_NIC_TCVEC2RING(_NIC_, _TC_, _VEC_) \ - ((_TC_) * AQ_CFG_TCS_MAX + (_VEC_)) +#define AQ_NIC_CFG_RING_PER_TC(_NIC_CFG_) \ + (((_NIC_CFG_)->tc_mode == AQ_TC_MODE_4TCS) ? 8 : 4) + +#define AQ_NIC_CFG_TCVEC2RING(_NIC_CFG_, _TC_, _VEC_) \ + ((_TC_) * AQ_NIC_CFG_RING_PER_TC(_NIC_CFG_) + (_VEC_)) + +#define AQ_NIC_RING2QMAP(_NIC_, _ID_) \ + ((_ID_) / AQ_NIC_CFG_RING_PER_TC(&(_NIC_)->aq_nic_cfg) * \ + (_NIC_)->aq_vecs + \ + ((_ID_) % AQ_NIC_CFG_RING_PER_TC(&(_NIC_)->aq_nic_cfg))) struct aq_hw_rx_fl2 { struct aq_rx_filter_vlan aq_vlans[AQ_VLAN_MAX_FILTERS]; @@ -104,7 +119,7 @@ struct aq_nic_s { atomic_t flags; u32 msg_enable; struct aq_vec_s *aq_vec[AQ_CFG_VECS_MAX]; - struct aq_ring_s *aq_ring_tx[AQ_CFG_VECS_MAX * AQ_CFG_TCS_MAX]; + struct aq_ring_s *aq_ring_tx[AQ_HW_QUEUES_MAX]; struct aq_hw_s *aq_hw; struct net_device *ndev; unsigned int aq_vecs; @@ -164,6 +179,7 @@ void aq_nic_deinit(struct aq_nic_s *self, bool link_down); void aq_nic_set_power(struct aq_nic_s *self); void aq_nic_free_hot_resources(struct aq_nic_s *self); void aq_nic_free_vectors(struct aq_nic_s *self); +int aq_nic_realloc_vectors(struct aq_nic_s *self); int aq_nic_set_mtu(struct aq_nic_s *self, int new_mtu); int aq_nic_set_mac(struct aq_nic_s *self, struct net_device *ndev); int aq_nic_set_packet_filter(struct aq_nic_s *self, unsigned int flags); @@ -181,4 +197,9 @@ void aq_nic_shutdown(struct aq_nic_s *self); u8 aq_nic_reserve_filter(struct aq_nic_s *self, enum aq_rx_filter_type type); void aq_nic_release_filter(struct aq_nic_s *self, enum aq_rx_filter_type type, u32 location); +int aq_nic_setup_tc_mqprio(struct aq_nic_s *self, u32 tcs, u8 *prio_tc_map); +int aq_nic_setup_tc_max_rate(struct aq_nic_s *self, const unsigned int tc, + const u32 max_rate); +int aq_nic_setup_tc_min_rate(struct aq_nic_s *self, const unsigned int tc, + const u32 min_rate); #endif /* AQ_NIC_H */ diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c b/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c index 8a70ffe1d326..41c0f560f95b 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c @@ -16,6 +16,7 @@ #include "aq_pci_func.h" #include "hw_atl/hw_atl_a0.h" #include "hw_atl/hw_atl_b0.h" +#include "hw_atl2/hw_atl2.h" #include "aq_filters.h" #include "aq_drvinfo.h" #include "aq_macsec.h" @@ -41,6 +42,13 @@ static const struct pci_device_id aq_pci_tbl[] = { { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC111S), }, { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC112S), }, + { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC113DEV), }, + { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC113CS), }, + { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC114CS), }, + { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC113), }, + { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC113C), }, + { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC115C), }, + {} }; @@ -70,6 +78,13 @@ static const struct aq_board_revision_s hw_atl_boards[] = { { AQ_DEVICE_ID_AQC109S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc109s, }, { AQ_DEVICE_ID_AQC111S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc111s, }, { AQ_DEVICE_ID_AQC112S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc112s, }, + + { AQ_DEVICE_ID_AQC113DEV, AQ_HWREV_ANY, &hw_atl2_ops, &hw_atl2_caps_aqc113, }, + { AQ_DEVICE_ID_AQC113, AQ_HWREV_ANY, &hw_atl2_ops, &hw_atl2_caps_aqc113, }, + { AQ_DEVICE_ID_AQC113CS, AQ_HWREV_ANY, &hw_atl2_ops, &hw_atl2_caps_aqc113, }, + { AQ_DEVICE_ID_AQC114CS, AQ_HWREV_ANY, &hw_atl2_ops, &hw_atl2_caps_aqc113, }, + { AQ_DEVICE_ID_AQC113C, AQ_HWREV_ANY, &hw_atl2_ops, &hw_atl2_caps_aqc113, }, + { AQ_DEVICE_ID_AQC115C, AQ_HWREV_ANY, &hw_atl2_ops, &hw_atl2_caps_aqc113, }, }; MODULE_DEVICE_TABLE(pci, aq_pci_tbl); @@ -104,10 +119,8 @@ int aq_pci_func_init(struct pci_dev *pdev) int err; err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); - if (!err) { + if (!err) err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); - - } if (err) { err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); if (!err) @@ -237,6 +250,15 @@ static int aq_pci_probe(struct pci_dev *pdev, goto err_ioremap; } self->aq_hw->aq_nic_cfg = aq_nic_get_cfg(self); + if (self->aq_hw->aq_nic_cfg->aq_hw_caps->priv_data_len) { + int len = self->aq_hw->aq_nic_cfg->aq_hw_caps->priv_data_len; + + self->aq_hw->priv = kzalloc(len, GFP_KERNEL); + if (!self->aq_hw->priv) { + err = -ENOMEM; + goto err_free_aq_hw; + } + } for (bar = 0; bar < 4; ++bar) { if (IORESOURCE_MEM & pci_resource_flags(pdev, bar)) { @@ -245,19 +267,19 @@ static int aq_pci_probe(struct pci_dev *pdev, mmio_pa = pci_resource_start(pdev, bar); if (mmio_pa == 0U) { err = -EIO; - goto err_free_aq_hw; + goto err_free_aq_hw_priv; } reg_sz = pci_resource_len(pdev, bar); if ((reg_sz <= 24 /*ATL_REGS_SIZE*/)) { err = -EIO; - goto err_free_aq_hw; + goto err_free_aq_hw_priv; } self->aq_hw->mmio = ioremap(mmio_pa, reg_sz); if (!self->aq_hw->mmio) { err = -EIO; - goto err_free_aq_hw; + goto err_free_aq_hw_priv; } break; } @@ -265,7 +287,7 @@ static int aq_pci_probe(struct pci_dev *pdev, if (bar == 4) { err = -EIO; - goto err_free_aq_hw; + goto err_free_aq_hw_priv; } numvecs = min((u8)AQ_CFG_VECS_DEF, @@ -305,6 +327,8 @@ err_register: aq_pci_free_irq_vectors(self); err_hwinit: iounmap(self->aq_hw->mmio); +err_free_aq_hw_priv: + kfree(self->aq_hw->priv); err_free_aq_hw: kfree(self->aq_hw); err_ioremap: @@ -332,6 +356,7 @@ static void aq_pci_remove(struct pci_dev *pdev) aq_nic_free_vectors(self); aq_pci_free_irq_vectors(self); iounmap(self->aq_hw->mmio); + kfree(self->aq_hw->priv); kfree(self->aq_hw); pci_release_regions(pdev); free_netdev(self->ndev); @@ -406,6 +431,9 @@ static int atl_resume_common(struct device *dev, bool deep) netif_tx_start_all_queues(nic->ndev); err_exit: + if (ret < 0) + aq_nic_deinit(nic, true); + rtnl_unlock(); return ret; diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ptp.c b/drivers/net/ethernet/aquantia/atlantic/aq_ptp.c index 58e8c641e8b3..599ced261b2a 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_ptp.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_ptp.c @@ -945,26 +945,29 @@ void aq_ptp_ring_deinit(struct aq_nic_s *aq_nic) #define PTP_4TC_RING_IDX 16 #define PTP_HWST_RING_IDX 31 +/* Index must be 8 (8 TCs) or 16 (4 TCs). + * It depends on Traffic Class mode. + */ +static unsigned int ptp_ring_idx(const enum aq_tc_mode tc_mode) +{ + if (tc_mode == AQ_TC_MODE_8TCS) + return PTP_8TC_RING_IDX; + + return PTP_4TC_RING_IDX; +} + int aq_ptp_ring_alloc(struct aq_nic_s *aq_nic) { struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp; unsigned int tx_ring_idx, rx_ring_idx; struct aq_ring_s *hwts; - u32 tx_tc_mode, rx_tc_mode; struct aq_ring_s *ring; int err; if (!aq_ptp) return 0; - /* Index must to be 8 (8 TCs) or 16 (4 TCs). - * It depends from Traffic Class mode. - */ - aq_nic->aq_hw_ops->hw_tx_tc_mode_get(aq_nic->aq_hw, &tx_tc_mode); - if (tx_tc_mode == 0) - tx_ring_idx = PTP_8TC_RING_IDX; - else - tx_ring_idx = PTP_4TC_RING_IDX; + tx_ring_idx = ptp_ring_idx(aq_nic->aq_nic_cfg.tc_mode); ring = aq_ring_tx_alloc(&aq_ptp->ptp_tx, aq_nic, tx_ring_idx, &aq_nic->aq_nic_cfg); @@ -973,11 +976,7 @@ int aq_ptp_ring_alloc(struct aq_nic_s *aq_nic) goto err_exit; } - aq_nic->aq_hw_ops->hw_rx_tc_mode_get(aq_nic->aq_hw, &rx_tc_mode); - if (rx_tc_mode == 0) - rx_ring_idx = PTP_8TC_RING_IDX; - else - rx_ring_idx = PTP_4TC_RING_IDX; + rx_ring_idx = ptp_ring_idx(aq_nic->aq_nic_cfg.tc_mode); ring = aq_ring_rx_alloc(&aq_ptp->ptp_rx, aq_nic, rx_ring_idx, &aq_nic->aq_nic_cfg); diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ring.c b/drivers/net/ethernet/aquantia/atlantic/aq_ring.c index bae95a618560..68fdb3994088 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_ring.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_ring.c @@ -232,8 +232,11 @@ void aq_ring_queue_wake(struct aq_ring_s *ring) { struct net_device *ndev = aq_nic_get_ndev(ring->aq_nic); - if (__netif_subqueue_stopped(ndev, ring->idx)) { - netif_wake_subqueue(ndev, ring->idx); + if (__netif_subqueue_stopped(ndev, + AQ_NIC_RING2QMAP(ring->aq_nic, + ring->idx))) { + netif_wake_subqueue(ndev, + AQ_NIC_RING2QMAP(ring->aq_nic, ring->idx)); ring->stats.tx.queue_restarts++; } } @@ -242,8 +245,11 @@ void aq_ring_queue_stop(struct aq_ring_s *ring) { struct net_device *ndev = aq_nic_get_ndev(ring->aq_nic); - if (!__netif_subqueue_stopped(ndev, ring->idx)) - netif_stop_subqueue(ndev, ring->idx); + if (!__netif_subqueue_stopped(ndev, + AQ_NIC_RING2QMAP(ring->aq_nic, + ring->idx))) + netif_stop_subqueue(ndev, + AQ_NIC_RING2QMAP(ring->aq_nic, ring->idx)); } bool aq_ring_tx_clean(struct aq_ring_s *self) @@ -466,7 +472,10 @@ int aq_ring_rx_clean(struct aq_ring_s *self, buff->is_hash_l4 ? PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_NONE); /* Send all PTP traffic to 0 queue */ - skb_record_rx_queue(skb, is_ptp_ring ? 0 : self->idx); + skb_record_rx_queue(skb, + is_ptp_ring ? 0 + : AQ_NIC_RING2QMAP(self->aq_nic, + self->idx)); ++self->stats.rx.packets; self->stats.rx.bytes += skb->len; diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_vec.c b/drivers/net/ethernet/aquantia/atlantic/aq_vec.c index f40a427970dc..d1d43c8ce400 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_vec.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_vec.c @@ -103,16 +103,11 @@ err_exit: struct aq_vec_s *aq_vec_alloc(struct aq_nic_s *aq_nic, unsigned int idx, struct aq_nic_cfg_s *aq_nic_cfg) { - struct aq_ring_s *ring = NULL; struct aq_vec_s *self = NULL; - unsigned int i = 0U; - int err = 0; self = kzalloc(sizeof(*self), GFP_KERNEL); - if (!self) { - err = -ENOMEM; + if (!self) goto err_exit; - } self->aq_nic = aq_nic; self->aq_ring_param.vec_idx = idx; @@ -128,10 +123,20 @@ struct aq_vec_s *aq_vec_alloc(struct aq_nic_s *aq_nic, unsigned int idx, netif_napi_add(aq_nic_get_ndev(aq_nic), &self->napi, aq_vec_poll, AQ_CFG_NAPI_WEIGHT); +err_exit: + return self; +} + +int aq_vec_ring_alloc(struct aq_vec_s *self, struct aq_nic_s *aq_nic, + unsigned int idx, struct aq_nic_cfg_s *aq_nic_cfg) +{ + struct aq_ring_s *ring = NULL; + unsigned int i = 0U; + int err = 0; + for (i = 0; i < aq_nic_cfg->tcs; ++i) { - unsigned int idx_ring = AQ_NIC_TCVEC2RING(self->nic, - self->tx_rings, - self->aq_ring_param.vec_idx); + const unsigned int idx_ring = AQ_NIC_CFG_TCVEC2RING(aq_nic_cfg, + i, idx); ring = aq_ring_tx_alloc(&self->ring[i][AQ_VEC_TX_ID], aq_nic, idx_ring, aq_nic_cfg); @@ -156,11 +161,11 @@ struct aq_vec_s *aq_vec_alloc(struct aq_nic_s *aq_nic, unsigned int idx, err_exit: if (err < 0) { - aq_vec_free(self); + aq_vec_ring_free(self); self = NULL; } - return self; + return err; } int aq_vec_init(struct aq_vec_s *self, const struct aq_hw_ops *aq_hw_ops, @@ -270,6 +275,18 @@ err_exit:; void aq_vec_free(struct aq_vec_s *self) { + if (!self) + goto err_exit; + + netif_napi_del(&self->napi); + + kfree(self); + +err_exit:; +} + +void aq_vec_ring_free(struct aq_vec_s *self) +{ struct aq_ring_s *ring = NULL; unsigned int i = 0U; @@ -279,13 +296,12 @@ void aq_vec_free(struct aq_vec_s *self) for (i = 0U, ring = self->ring[0]; self->tx_rings > i; ++i, ring = self->ring[i]) { aq_ring_free(&ring[AQ_VEC_TX_ID]); - aq_ring_free(&ring[AQ_VEC_RX_ID]); + if (i < self->rx_rings) + aq_ring_free(&ring[AQ_VEC_RX_ID]); } - netif_napi_del(&self->napi); - - kfree(self); - + self->tx_rings = 0; + self->rx_rings = 0; err_exit:; } @@ -333,16 +349,14 @@ cpumask_t *aq_vec_get_affinity_mask(struct aq_vec_s *self) return &self->aq_ring_param.affinity_mask; } -void aq_vec_add_stats(struct aq_vec_s *self, - struct aq_ring_stats_rx_s *stats_rx, - struct aq_ring_stats_tx_s *stats_tx) +static void aq_vec_add_stats(struct aq_vec_s *self, + const unsigned int tc, + struct aq_ring_stats_rx_s *stats_rx, + struct aq_ring_stats_tx_s *stats_tx) { - struct aq_ring_s *ring = NULL; - unsigned int r = 0U; + struct aq_ring_s *ring = self->ring[tc]; - for (r = 0U, ring = self->ring[0]; - self->tx_rings > r; ++r, ring = self->ring[r]) { - struct aq_ring_stats_tx_s *tx = &ring[AQ_VEC_TX_ID].stats.tx; + if (tc < self->rx_rings) { struct aq_ring_stats_rx_s *rx = &ring[AQ_VEC_RX_ID].stats.rx; stats_rx->packets += rx->packets; @@ -353,6 +367,10 @@ void aq_vec_add_stats(struct aq_vec_s *self, stats_rx->pg_losts += rx->pg_losts; stats_rx->pg_flips += rx->pg_flips; stats_rx->pg_reuses += rx->pg_reuses; + } + + if (tc < self->tx_rings) { + struct aq_ring_stats_tx_s *tx = &ring[AQ_VEC_TX_ID].stats.tx; stats_tx->packets += tx->packets; stats_tx->bytes += tx->bytes; @@ -361,7 +379,8 @@ void aq_vec_add_stats(struct aq_vec_s *self, } } -int aq_vec_get_sw_stats(struct aq_vec_s *self, u64 *data, unsigned int *p_count) +int aq_vec_get_sw_stats(struct aq_vec_s *self, const unsigned int tc, u64 *data, + unsigned int *p_count) { struct aq_ring_stats_rx_s stats_rx; struct aq_ring_stats_tx_s stats_tx; @@ -369,7 +388,8 @@ int aq_vec_get_sw_stats(struct aq_vec_s *self, u64 *data, unsigned int *p_count) memset(&stats_rx, 0U, sizeof(struct aq_ring_stats_rx_s)); memset(&stats_tx, 0U, sizeof(struct aq_ring_stats_tx_s)); - aq_vec_add_stats(self, &stats_rx, &stats_tx); + + aq_vec_add_stats(self, tc, &stats_rx, &stats_tx); /* This data should mimic aq_ethtool_queue_stat_names structure */ diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_vec.h b/drivers/net/ethernet/aquantia/atlantic/aq_vec.h index 0fe8e0904c7f..541af85e6510 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_vec.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_vec.h @@ -25,17 +25,17 @@ irqreturn_t aq_vec_isr(int irq, void *private); irqreturn_t aq_vec_isr_legacy(int irq, void *private); struct aq_vec_s *aq_vec_alloc(struct aq_nic_s *aq_nic, unsigned int idx, struct aq_nic_cfg_s *aq_nic_cfg); +int aq_vec_ring_alloc(struct aq_vec_s *self, struct aq_nic_s *aq_nic, + unsigned int idx, struct aq_nic_cfg_s *aq_nic_cfg); int aq_vec_init(struct aq_vec_s *self, const struct aq_hw_ops *aq_hw_ops, struct aq_hw_s *aq_hw); void aq_vec_deinit(struct aq_vec_s *self); void aq_vec_free(struct aq_vec_s *self); +void aq_vec_ring_free(struct aq_vec_s *self); int aq_vec_start(struct aq_vec_s *self); void aq_vec_stop(struct aq_vec_s *self); cpumask_t *aq_vec_get_affinity_mask(struct aq_vec_s *self); -int aq_vec_get_sw_stats(struct aq_vec_s *self, u64 *data, +int aq_vec_get_sw_stats(struct aq_vec_s *self, const unsigned int tc, u64 *data, unsigned int *p_count); -void aq_vec_add_stats(struct aq_vec_s *self, - struct aq_ring_stats_rx_s *stats_rx, - struct aq_ring_stats_tx_s *stats_tx); #endif /* AQ_VEC_H */ diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c index 9b1062b8af64..a312864969af 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only -/* - * aQuantia Corporation Network Driver - * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved +/* Atlantic Network Driver + * + * Copyright (C) 2014-2019 aQuantia Corporation + * Copyright (C) 2019-2020 Marvell International Ltd. */ /* File hw_atl_a0.c: Definition of Atlantic hardware specific functions. */ @@ -20,7 +21,7 @@ .msix_irqs = 4U, \ .irq_mask = ~0U, \ .vecs = HW_ATL_A0_RSS_MAX, \ - .tcs = HW_ATL_A0_TC_MAX, \ + .tcs_max = HW_ATL_A0_TC_MAX, \ .rxd_alignment = 1U, \ .rxd_size = HW_ATL_A0_RXD_SIZE, \ .rxds_max = HW_ATL_A0_MAX_RXD, \ @@ -47,7 +48,7 @@ const struct aq_hw_caps_s hw_atl_a0_caps_aqc100 = { DEFAULT_A0_BOARD_BASIC_CAPABILITIES, .media_type = AQ_HW_MEDIA_TYPE_FIBRE, .link_speed_msk = AQ_NIC_RATE_5G | - AQ_NIC_RATE_2GS | + AQ_NIC_RATE_2G5 | AQ_NIC_RATE_1G | AQ_NIC_RATE_100M, }; @@ -57,7 +58,7 @@ const struct aq_hw_caps_s hw_atl_a0_caps_aqc107 = { .media_type = AQ_HW_MEDIA_TYPE_TP, .link_speed_msk = AQ_NIC_RATE_10G | AQ_NIC_RATE_5G | - AQ_NIC_RATE_2GS | + AQ_NIC_RATE_2G5 | AQ_NIC_RATE_1G | AQ_NIC_RATE_100M, }; @@ -66,7 +67,7 @@ const struct aq_hw_caps_s hw_atl_a0_caps_aqc108 = { DEFAULT_A0_BOARD_BASIC_CAPABILITIES, .media_type = AQ_HW_MEDIA_TYPE_TP, .link_speed_msk = AQ_NIC_RATE_5G | - AQ_NIC_RATE_2GS | + AQ_NIC_RATE_2G5 | AQ_NIC_RATE_1G | AQ_NIC_RATE_100M, }; @@ -74,7 +75,7 @@ const struct aq_hw_caps_s hw_atl_a0_caps_aqc108 = { const struct aq_hw_caps_s hw_atl_a0_caps_aqc109 = { DEFAULT_A0_BOARD_BASIC_CAPABILITIES, .media_type = AQ_HW_MEDIA_TYPE_TP, - .link_speed_msk = AQ_NIC_RATE_2GS | + .link_speed_msk = AQ_NIC_RATE_2G5 | AQ_NIC_RATE_1G | AQ_NIC_RATE_100M, }; @@ -135,10 +136,10 @@ static int hw_atl_a0_hw_qos_set(struct aq_hw_s *self) hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U); hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U); - hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U); - hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U); - hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U); - hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U); + hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0U, 0xFFF); + hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0U, 0x64); + hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0U, 0x50); + hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0U, 0x1E); /* Tx buf size */ buff_size = HW_ATL_A0_TXBUF_MAX; @@ -267,8 +268,7 @@ static int hw_atl_a0_hw_init_tx_path(struct aq_hw_s *self) hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U); /* misc */ - aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ? - 0x00010000U : 0x00000000U); + aq_hw_write_reg(self, 0x00007040U, 0x00000000U); hw_atl_tdm_tx_dca_en_set(self, 0U); hw_atl_tdm_tx_dca_mode_set(self, 0U); @@ -886,6 +886,8 @@ static int hw_atl_a0_hw_ring_rx_stop(struct aq_hw_s *self, } const struct aq_hw_ops hw_atl_ops_a0 = { + .hw_soft_reset = hw_atl_utils_soft_reset, + .hw_prepare = hw_atl_utils_initfw, .hw_set_mac_address = hw_atl_a0_hw_mac_addr_set, .hw_init = hw_atl_a0_hw_init, .hw_reset = hw_atl_a0_hw_reset, diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c index d20d91cdece8..14d79f70cad7 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only -/* - * aQuantia Corporation Network Driver - * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved +/* Atlantic Network Driver + * + * Copyright (C) 2014-2019 aQuantia Corporation + * Copyright (C) 2019-2020 Marvell International Ltd. */ /* File hw_atl_b0.c: Definition of Atlantic hardware specific functions. */ @@ -22,7 +23,7 @@ .msix_irqs = 8U, \ .irq_mask = ~0U, \ .vecs = HW_ATL_B0_RSS_MAX, \ - .tcs = HW_ATL_B0_TC_MAX, \ + .tcs_max = HW_ATL_B0_TC_MAX, \ .rxd_alignment = 1U, \ .rxd_size = HW_ATL_B0_RXD_SIZE, \ .rxds_max = HW_ATL_B0_MAX_RXD, \ @@ -45,7 +46,8 @@ NETIF_F_HW_VLAN_CTAG_RX | \ NETIF_F_HW_VLAN_CTAG_TX | \ NETIF_F_GSO_UDP_L4 | \ - NETIF_F_GSO_PARTIAL, \ + NETIF_F_GSO_PARTIAL | \ + NETIF_F_HW_TC, \ .hw_priv_flags = IFF_UNICAST_FLT, \ .flow_control = true, \ .mtu = HW_ATL_B0_MTU_JUMBO, \ @@ -59,7 +61,7 @@ const struct aq_hw_caps_s hw_atl_b0_caps_aqc100 = { .media_type = AQ_HW_MEDIA_TYPE_FIBRE, .link_speed_msk = AQ_NIC_RATE_10G | AQ_NIC_RATE_5G | - AQ_NIC_RATE_2GS | + AQ_NIC_RATE_2G5 | AQ_NIC_RATE_1G | AQ_NIC_RATE_100M, }; @@ -69,7 +71,7 @@ const struct aq_hw_caps_s hw_atl_b0_caps_aqc107 = { .media_type = AQ_HW_MEDIA_TYPE_TP, .link_speed_msk = AQ_NIC_RATE_10G | AQ_NIC_RATE_5G | - AQ_NIC_RATE_2GS | + AQ_NIC_RATE_2G5 | AQ_NIC_RATE_1G | AQ_NIC_RATE_100M, }; @@ -78,7 +80,7 @@ const struct aq_hw_caps_s hw_atl_b0_caps_aqc108 = { DEFAULT_B0_BOARD_BASIC_CAPABILITIES, .media_type = AQ_HW_MEDIA_TYPE_TP, .link_speed_msk = AQ_NIC_RATE_5G | - AQ_NIC_RATE_2GS | + AQ_NIC_RATE_2G5 | AQ_NIC_RATE_1G | AQ_NIC_RATE_100M, }; @@ -86,7 +88,7 @@ const struct aq_hw_caps_s hw_atl_b0_caps_aqc108 = { const struct aq_hw_caps_s hw_atl_b0_caps_aqc109 = { DEFAULT_B0_BOARD_BASIC_CAPABILITIES, .media_type = AQ_HW_MEDIA_TYPE_TP, - .link_speed_msk = AQ_NIC_RATE_2GS | + .link_speed_msk = AQ_NIC_RATE_2G5 | AQ_NIC_RATE_1G | AQ_NIC_RATE_100M, }; @@ -113,12 +115,34 @@ static int hw_atl_b0_set_fc(struct aq_hw_s *self, u32 fc, u32 tc) return 0; } +static int hw_atl_b0_tc_ptp_set(struct aq_hw_s *self) +{ + /* Init TC2 for PTP_TX */ + hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, HW_ATL_B0_PTP_TXBUF_SIZE, + AQ_HW_PTP_TC); + + /* Init TC2 for PTP_RX */ + hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, HW_ATL_B0_PTP_RXBUF_SIZE, + AQ_HW_PTP_TC); + /* No flow control for PTP */ + hw_atl_rpb_rx_xoff_en_per_tc_set(self, 0U, AQ_HW_PTP_TC); + + return aq_hw_err_from_flags(self); +} + static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self) { - unsigned int i_priority = 0U; - u32 buff_size = 0U; + struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; + u32 tx_buff_size = HW_ATL_B0_TXBUF_MAX; + u32 rx_buff_size = HW_ATL_B0_RXBUF_MAX; + unsigned int prio = 0U; u32 tc = 0U; + if (cfg->is_ptp) { + tx_buff_size -= HW_ATL_B0_PTP_TXBUF_SIZE; + rx_buff_size -= HW_ATL_B0_PTP_RXBUF_SIZE; + } + /* TPS Descriptor rate init */ hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U); hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA); @@ -126,69 +150,45 @@ static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self) /* TPS VM init */ hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U); - /* TPS TC credits init */ - hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U); - hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U); - - tc = 0; - - /* TX Packet Scheduler Data TC0 */ - hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, tc); - hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, tc); - hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, tc); - hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, tc); - - /* Tx buf size TC0 */ - buff_size = HW_ATL_B0_TXBUF_MAX - HW_ATL_B0_PTP_TXBUF_SIZE; - - hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc); - hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self, - (buff_size * - (1024 / 32U) * 66U) / - 100U, tc); - hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self, - (buff_size * - (1024 / 32U) * 50U) / - 100U, tc); - /* Init TC2 for PTP_TX */ - tc = 2; + tx_buff_size /= cfg->tcs; + rx_buff_size /= cfg->tcs; + for (tc = 0; tc < cfg->tcs; tc++) { + u32 threshold = 0U; - hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, HW_ATL_B0_PTP_TXBUF_SIZE, - tc); + /* Tx buf size TC0 */ + hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, tx_buff_size, tc); - /* QoS Rx buf size per TC */ - tc = 0; - buff_size = HW_ATL_B0_RXBUF_MAX - HW_ATL_B0_PTP_RXBUF_SIZE; + threshold = (tx_buff_size * (1024 / 32U) * 66U) / 100U; + hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self, threshold, tc); - hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc); - hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self, - (buff_size * - (1024U / 32U) * 66U) / - 100U, tc); - hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self, - (buff_size * - (1024U / 32U) * 50U) / - 100U, tc); + threshold = (tx_buff_size * (1024 / 32U) * 50U) / 100U; + hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self, threshold, tc); - hw_atl_b0_set_fc(self, self->aq_nic_cfg->fc.req, tc); + /* QoS Rx buf size per TC */ + hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, rx_buff_size, tc); - /* Init TC2 for PTP_RX */ - tc = 2; + threshold = (rx_buff_size * (1024U / 32U) * 66U) / 100U; + hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self, threshold, tc); - hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, HW_ATL_B0_PTP_RXBUF_SIZE, - tc); - /* No flow control for PTP */ - hw_atl_rpb_rx_xoff_en_per_tc_set(self, 0U, tc); + threshold = (rx_buff_size * (1024U / 32U) * 50U) / 100U; + hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self, threshold, tc); + + hw_atl_b0_set_fc(self, self->aq_nic_cfg->fc.req, tc); + } + + if (cfg->is_ptp) + hw_atl_b0_tc_ptp_set(self); /* QoS 802.1p priority -> TC mapping */ - for (i_priority = 8U; i_priority--;) - hw_atl_rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U); + for (prio = 0; prio < 8; ++prio) + hw_atl_rpf_rpb_user_priority_tc_map_set(self, prio, + cfg->prio_tc_map[prio]); return aq_hw_err_from_flags(self); } -static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self, - struct aq_rss_parameters *rss_params) +int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self, + struct aq_rss_parameters *rss_params) { struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; unsigned int addr = 0U; @@ -251,9 +251,10 @@ err_exit: return err; } -static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self, - struct aq_nic_cfg_s *aq_nic_cfg) +int hw_atl_b0_hw_offload_set(struct aq_hw_s *self, + struct aq_nic_cfg_s *aq_nic_cfg) { + u64 rxcsum = !!(aq_nic_cfg->features & NETIF_F_RXCSUM); unsigned int i; /* TX checksums offloads*/ @@ -261,10 +262,8 @@ static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self, hw_atl_tpo_tcp_udp_crc_offload_en_set(self, 1); /* RX checksums offloads*/ - hw_atl_rpo_ipv4header_crc_offload_en_set(self, !!(aq_nic_cfg->features & - NETIF_F_RXCSUM)); - hw_atl_rpo_tcp_udp_crc_offload_en_set(self, !!(aq_nic_cfg->features & - NETIF_F_RXCSUM)); + hw_atl_rpo_ipv4header_crc_offload_en_set(self, rxcsum); + hw_atl_rpo_tcp_udp_crc_offload_en_set(self, rxcsum); /* LSO offloads*/ hw_atl_tdm_large_send_offload_en_set(self, 0xFFFFFFFFU); @@ -272,7 +271,7 @@ static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self, /* Outer VLAN tag offload */ hw_atl_rpo_outer_vlan_tag_mode_set(self, 1U); -/* LRO offloads */ + /* LRO offloads */ { unsigned int val = (8U < HW_ATL_B0_LRO_RXD_MAX) ? 0x3U : ((4U < HW_ATL_B0_LRO_RXD_MAX) ? 0x2U : @@ -311,10 +310,124 @@ static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self, return aq_hw_err_from_flags(self); } +static int hw_atl_b0_hw_init_tx_tc_rate_limit(struct aq_hw_s *self) +{ + static const u32 max_weight = BIT(HW_ATL_TPS_DATA_TCTWEIGHT_WIDTH) - 1; + /* Scale factor is based on the number of bits in fractional portion */ + static const u32 scale = BIT(HW_ATL_TPS_DESC_RATE_Y_WIDTH); + static const u32 frac_msk = HW_ATL_TPS_DESC_RATE_Y_MSK >> + HW_ATL_TPS_DESC_RATE_Y_SHIFT; + const u32 link_speed = self->aq_link_status.mbps; + struct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg; + unsigned long num_min_rated_tcs = 0; + u32 tc_weight[AQ_CFG_TCS_MAX]; + u32 fixed_max_credit; + u8 min_rate_msk = 0; + u32 sum_weight = 0; + int tc; + + /* By default max_credit is based upon MTU (in unit of 64b) */ + fixed_max_credit = nic_cfg->aq_hw_caps->mtu / 64; + + if (link_speed) { + min_rate_msk = nic_cfg->tc_min_rate_msk & + (BIT(nic_cfg->tcs) - 1); + num_min_rated_tcs = hweight8(min_rate_msk); + } + + /* First, calculate weights where min_rate is specified */ + if (num_min_rated_tcs) { + for (tc = 0; tc != nic_cfg->tcs; tc++) { + if (!nic_cfg->tc_min_rate[tc]) { + tc_weight[tc] = 0; + continue; + } + + tc_weight[tc] = (-1L + link_speed + + nic_cfg->tc_min_rate[tc] * + max_weight) / + link_speed; + tc_weight[tc] = min(tc_weight[tc], max_weight); + sum_weight += tc_weight[tc]; + } + } + + /* WSP, if min_rate is set for at least one TC. + * RR otherwise. + */ + hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, min_rate_msk ? 1U : 0U); + /* Data TC Arbiter takes precedence over Descriptor TC Arbiter, + * leave Descriptor TC Arbiter as RR. + */ + hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U); + + hw_atl_tps_tx_desc_rate_mode_set(self, nic_cfg->is_qos ? 1U : 0U); + + for (tc = 0; tc != nic_cfg->tcs; tc++) { + const u32 en = (nic_cfg->tc_max_rate[tc] != 0) ? 1U : 0U; + const u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0); + u32 weight, max_credit; + + hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, tc, + fixed_max_credit); + hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, tc, 0x1E); + + if (num_min_rated_tcs) { + weight = tc_weight[tc]; + + if (!weight && sum_weight < max_weight) + weight = (max_weight - sum_weight) / + (nic_cfg->tcs - num_min_rated_tcs); + else if (!weight) + weight = 0x64; + + max_credit = max(8 * weight, fixed_max_credit); + } else { + weight = 0x64; + max_credit = 0xFFF; + } + + hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, tc, weight); + hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, tc, + max_credit); + + hw_atl_tps_tx_desc_rate_en_set(self, desc, en); + + if (en) { + /* Nominal rate is always 10G */ + const u32 rate = 10000U * scale / + nic_cfg->tc_max_rate[tc]; + const u32 rate_int = rate >> + HW_ATL_TPS_DESC_RATE_Y_WIDTH; + const u32 rate_frac = rate & frac_msk; + + hw_atl_tps_tx_desc_rate_x_set(self, desc, rate_int); + hw_atl_tps_tx_desc_rate_y_set(self, desc, rate_frac); + } else { + /* A value of 1 indicates the queue is not + * rate controlled. + */ + hw_atl_tps_tx_desc_rate_x_set(self, desc, 1U); + hw_atl_tps_tx_desc_rate_y_set(self, desc, 0U); + } + } + for (tc = nic_cfg->tcs; tc != AQ_CFG_TCS_MAX; tc++) { + const u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0); + + hw_atl_tps_tx_desc_rate_en_set(self, desc, 0U); + hw_atl_tps_tx_desc_rate_x_set(self, desc, 1U); + hw_atl_tps_tx_desc_rate_y_set(self, desc, 0U); + } + + return aq_hw_err_from_flags(self); +} + static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self) { + struct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg; + /* Tx TC/Queue number config */ - hw_atl_rpb_tps_tx_tc_mode_set(self, 1U); + hw_atl_tpb_tps_tx_tc_mode_set(self, nic_cfg->tc_mode); hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U); hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U); @@ -324,7 +437,7 @@ static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self) hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U); /* misc */ - aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ? + aq_hw_write_reg(self, 0x00007040U, ATL_HW_IS_CHIP_FEATURE(self, TPO2) ? 0x00010000U : 0x00000000U); hw_atl_tdm_tx_dca_en_set(self, 0U); hw_atl_tdm_tx_dca_mode_set(self, 0U); @@ -334,20 +447,32 @@ static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self) return aq_hw_err_from_flags(self); } +void hw_atl_b0_hw_init_rx_rss_ctrl1(struct aq_hw_s *self) +{ + struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; + u32 rss_ctrl1 = HW_ATL_RSS_DISABLED; + + if (cfg->is_rss) + rss_ctrl1 = (cfg->tc_mode == AQ_TC_MODE_8TCS) ? + HW_ATL_RSS_ENABLED_8TCS_2INDEX_BITS : + HW_ATL_RSS_ENABLED_4TCS_3INDEX_BITS; + + hw_atl_reg_rx_flr_rss_control1set(self, rss_ctrl1); +} + static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self) { struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; int i; /* Rx TC/RSS number config */ - hw_atl_rpb_rpf_rx_traf_class_mode_set(self, 1U); + hw_atl_rpb_rpf_rx_traf_class_mode_set(self, cfg->tc_mode); /* Rx flow control */ hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U); /* RSS Ring selection */ - hw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ? - 0xB3333333U : 0x00000000U); + hw_atl_b0_hw_init_rx_rss_ctrl1(self); /* Multicast filters */ for (i = HW_ATL_B0_MAC_MAX; i--;) { @@ -372,8 +497,8 @@ static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self) hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U); /* misc */ - aq_hw_write_reg(self, 0x00005040U, - IS_CHIP_FEATURE(RPF2) ? 0x000F0000U : 0x00000000U); + aq_hw_write_reg(self, 0x00005040U, ATL_HW_IS_CHIP_FEATURE(self, RPF2) ? + 0x000F0000U : 0x00000000U); hw_atl_rpfl2broadcast_flr_act_set(self, 1U); hw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U)); @@ -384,7 +509,7 @@ static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self) return aq_hw_err_from_flags(self); } -static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr) +int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr) { unsigned int h = 0U; unsigned int l = 0U; @@ -479,23 +604,21 @@ err_exit: return err; } -static int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self, - struct aq_ring_s *ring) +int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self, struct aq_ring_s *ring) { hw_atl_tdm_tx_desc_en_set(self, 1, ring->idx); return aq_hw_err_from_flags(self); } -static int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self, - struct aq_ring_s *ring) +int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self, struct aq_ring_s *ring) { hw_atl_rdm_rx_desc_en_set(self, 1, ring->idx); return aq_hw_err_from_flags(self); } -static int hw_atl_b0_hw_start(struct aq_hw_s *self) +int hw_atl_b0_hw_start(struct aq_hw_s *self) { hw_atl_tpb_tx_buff_en_set(self, 1); hw_atl_rpb_rx_buff_en_set(self, 1); @@ -511,9 +634,8 @@ static int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self, return 0; } -static int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s *self, - struct aq_ring_s *ring, - unsigned int frags) +int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s *self, struct aq_ring_s *ring, + unsigned int frags) { struct aq_ring_buff_s *buff = NULL; struct hw_atl_txd_s *txd = NULL; @@ -600,9 +722,8 @@ static int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s *self, return aq_hw_err_from_flags(self); } -static int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self, - struct aq_ring_s *aq_ring, - struct aq_ring_param_s *aq_ring_param) +int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self, struct aq_ring_s *aq_ring, + struct aq_ring_param_s *aq_ring_param) { u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32); u32 vlan_rx_stripping = self->aq_nic_cfg->is_vlan_rx_strip; @@ -643,9 +764,8 @@ static int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self, return aq_hw_err_from_flags(self); } -static int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self, - struct aq_ring_s *aq_ring, - struct aq_ring_param_s *aq_ring_param) +int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self, struct aq_ring_s *aq_ring, + struct aq_ring_param_s *aq_ring_param) { u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32); u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa; @@ -673,9 +793,8 @@ static int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self, return aq_hw_err_from_flags(self); } -static int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s *self, - struct aq_ring_s *ring, - unsigned int sw_tail_old) +int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s *self, struct aq_ring_s *ring, + unsigned int sw_tail_old) { for (; sw_tail_old != ring->sw_tail; sw_tail_old = aq_ring_next_dx(ring, sw_tail_old)) { @@ -734,8 +853,8 @@ static int hw_atl_b0_hw_ring_hwts_rx_receive(struct aq_hw_s *self, return aq_hw_err_from_flags(self); } -static int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self, - struct aq_ring_s *ring) +int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self, + struct aq_ring_s *ring) { unsigned int hw_head_; int err = 0; @@ -753,8 +872,7 @@ err_exit: return err; } -static int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s *self, - struct aq_ring_s *ring) +int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s *self, struct aq_ring_s *ring) { for (; ring->hw_head != ring->sw_tail; ring->hw_head = aq_ring_next_dx(ring, ring->hw_head)) { @@ -854,14 +972,14 @@ static int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s *self, return aq_hw_err_from_flags(self); } -static int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask) +int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask) { hw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask)); return aq_hw_err_from_flags(self); } -static int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask) +int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask) { hw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask)); hw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask)); @@ -871,7 +989,7 @@ static int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask) return aq_hw_err_from_flags(self); } -static int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask) +int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask) { *mask = hw_atl_itr_irq_statuslsw_get(self); @@ -880,8 +998,8 @@ static int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask) #define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U) -static int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s *self, - unsigned int packet_filter) +int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s *self, + unsigned int packet_filter) { struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; unsigned int i = 0U; @@ -1071,34 +1189,20 @@ err_exit: return err; } -static int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self, - struct aq_ring_s *ring) +int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self, struct aq_ring_s *ring) { hw_atl_tdm_tx_desc_en_set(self, 0U, ring->idx); return aq_hw_err_from_flags(self); } -static int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self, - struct aq_ring_s *ring) +int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self, struct aq_ring_s *ring) { hw_atl_rdm_rx_desc_en_set(self, 0U, ring->idx); return aq_hw_err_from_flags(self); } -static int hw_atl_b0_tx_tc_mode_get(struct aq_hw_s *self, u32 *tc_mode) -{ - *tc_mode = hw_atl_rpb_tps_tx_tc_mode_get(self); - return aq_hw_err_from_flags(self); -} - -static int hw_atl_b0_rx_tc_mode_get(struct aq_hw_s *self, u32 *tc_mode) -{ - *tc_mode = hw_atl_rpb_rpf_rx_traf_class_mode_get(self); - return aq_hw_err_from_flags(self); -} - #define get_ptp_ts_val_u64(self, indx) \ ((u64)(hw_atl_pcs_ptp_clock_get(self, indx) & 0xffff)) @@ -1478,6 +1582,8 @@ static int hw_atl_b0_set_loopback(struct aq_hw_s *self, u32 mode, bool enable) } const struct aq_hw_ops hw_atl_ops_b0 = { + .hw_soft_reset = hw_atl_utils_soft_reset, + .hw_prepare = hw_atl_utils_initfw, .hw_set_mac_address = hw_atl_b0_hw_mac_addr_set, .hw_init = hw_atl_b0_hw_init, .hw_reset = hw_atl_b0_hw_reset, @@ -1510,13 +1616,11 @@ const struct aq_hw_ops hw_atl_ops_b0 = { .hw_interrupt_moderation_set = hw_atl_b0_hw_interrupt_moderation_set, .hw_rss_set = hw_atl_b0_hw_rss_set, .hw_rss_hash_set = hw_atl_b0_hw_rss_hash_set, + .hw_tc_rate_limit_set = hw_atl_b0_hw_init_tx_tc_rate_limit, .hw_get_regs = hw_atl_utils_hw_get_regs, .hw_get_hw_stats = hw_atl_utils_get_hw_stats, .hw_get_fw_version = hw_atl_utils_get_fw_version, - .hw_tx_tc_mode_get = hw_atl_b0_tx_tc_mode_get, - .hw_rx_tc_mode_get = hw_atl_b0_rx_tc_mode_get, - .hw_ring_hwts_rx_fill = hw_atl_b0_hw_ring_hwts_rx_fill, .hw_ring_hwts_rx_receive = hw_atl_b0_hw_ring_hwts_rx_receive, diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h index 09af1683034b..30f468f2084d 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* - * aQuantia Corporation Network Driver - * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved +/* Atlantic Network Driver + * + * Copyright (C) 2014-2019 aQuantia Corporation + * Copyright (C) 2019-2020 Marvell International Ltd. */ /* File hw_atl_b0.h: Declaration of abstract interface for Atlantic hardware @@ -33,4 +34,41 @@ extern const struct aq_hw_ops hw_atl_ops_b0; #define hw_atl_ops_b1 hw_atl_ops_b0 +int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self, + struct aq_rss_parameters *rss_params); +int hw_atl_b0_hw_offload_set(struct aq_hw_s *self, + struct aq_nic_cfg_s *aq_nic_cfg); + +int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self, struct aq_ring_s *ring); +int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self, struct aq_ring_s *ring); + +int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self, struct aq_ring_s *aq_ring, + struct aq_ring_param_s *aq_ring_param); +int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s *self, struct aq_ring_s *ring, + unsigned int sw_tail_old); +int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s *self, struct aq_ring_s *ring); + +int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self, struct aq_ring_s *aq_ring, + struct aq_ring_param_s *aq_ring_param); +int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s *self, struct aq_ring_s *ring, + unsigned int frags); +int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self, + struct aq_ring_s *ring); + +int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self, struct aq_ring_s *ring); +int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self, struct aq_ring_s *ring); + +void hw_atl_b0_hw_init_rx_rss_ctrl1(struct aq_hw_s *self); + +int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr); + +int hw_atl_b0_hw_start(struct aq_hw_s *self); + +int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask); +int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask); +int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask); + +int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s *self, + unsigned int packet_filter); + #endif /* HW_ATL_B0_H */ diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h index 7ab23a1751d3..cf460d61a45e 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h @@ -75,7 +75,7 @@ #define HW_ATL_B0_RSS_HASHKEY_BITS 320U #define HW_ATL_B0_TCRSS_4_8 1 -#define HW_ATL_B0_TC_MAX 1U +#define HW_ATL_B0_TC_MAX 8U #define HW_ATL_B0_RSS_MAX 8U #define HW_ATL_B0_LRO_RXD_MAX 16U @@ -151,6 +151,10 @@ #define HW_ATL_B0_MAX_RXD 8184U #define HW_ATL_B0_MAX_TXD 8184U +#define HW_ATL_RSS_DISABLED 0x00000000U +#define HW_ATL_RSS_ENABLED_8TCS_2INDEX_BITS 0xA2222222U +#define HW_ATL_RSS_ENABLED_4TCS_3INDEX_BITS 0x80003333U + /* HW layer capabilities */ #endif /* HW_ATL_B0_INTERNAL_H */ diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c index d1f68fc16291..3c8e8047ea1e 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c @@ -693,6 +693,13 @@ void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw, HW_ATL_RPFL2MC_ENF_SHIFT, l2multicast_flr_en); } +u32 hw_atl_rpfl2promiscuous_mode_en_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPFL2PROMIS_MODE_ADR, + HW_ATL_RPFL2PROMIS_MODE_MSK, + HW_ATL_RPFL2PROMIS_MODE_SHIFT); +} + void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw, u32 l2promiscuous_mode_en) { @@ -747,7 +754,7 @@ void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw, } void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw, - u32 user_priority_tc_map, u32 tc) + u32 user_priority, u32 tc) { /* register address for bitfield rx_tc_up{t}[2:0] */ static u32 rpf_rpb_rx_tc_upt_adr[8] = { @@ -766,10 +773,9 @@ void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw, 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U }; - aq_hw_write_reg_bit(aq_hw, rpf_rpb_rx_tc_upt_adr[tc], - rpf_rpb_rx_tc_upt_msk[tc], - rpf_rpb_rx_tc_upt_shft[tc], - user_priority_tc_map); + aq_hw_write_reg_bit(aq_hw, rpf_rpb_rx_tc_upt_adr[user_priority], + rpf_rpb_rx_tc_upt_msk[user_priority], + rpf_rpb_rx_tc_upt_shft[user_priority], tc); } void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr) @@ -867,6 +873,13 @@ void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw, vlan_prom_mode_en); } +u32 hw_atl_rpf_vlan_prom_mode_en_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_VL_PROMIS_MODE_ADR, + HW_ATL_RPF_VL_PROMIS_MODE_MSK, + HW_ATL_RPF_VL_PROMIS_MODE_SHIFT); +} + void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw, u32 vlan_acc_untagged_packets) { @@ -1304,14 +1317,14 @@ void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en) HW_ATL_TPB_TX_BUF_EN_SHIFT, tx_buff_en); } -u32 hw_atl_rpb_tps_tx_tc_mode_get(struct aq_hw_s *aq_hw) +u32 hw_atl_tpb_tps_tx_tc_mode_get(struct aq_hw_s *aq_hw) { return aq_hw_read_reg_bit(aq_hw, HW_ATL_TPB_TX_TC_MODE_ADDR, HW_ATL_TPB_TX_TC_MODE_MSK, HW_ATL_TPB_TX_TC_MODE_SHIFT); } -void hw_atl_rpb_tps_tx_tc_mode_set(struct aq_hw_s *aq_hw, +void hw_atl_tpb_tps_tx_tc_mode_set(struct aq_hw_s *aq_hw, u32 tx_traf_class_mode) { aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_TC_MODE_ADDR, @@ -1450,8 +1463,8 @@ void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw, } void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw, - u32 max_credit, - u32 tc) + const u32 tc, + const u32 max_credit) { aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc), HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK, @@ -1460,13 +1473,13 @@ void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw, } void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw, - u32 tx_pkt_shed_desc_tc_weight, - u32 tc) + const u32 tc, + const u32 weight) { aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc), HW_ATL_TPS_DESC_TCTWEIGHT_MSK, HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT, - tx_pkt_shed_desc_tc_weight); + weight); } void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw, @@ -1479,8 +1492,8 @@ void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw, } void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw, - u32 max_credit, - u32 tc) + const u32 tc, + const u32 max_credit) { aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc), HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK, @@ -1489,13 +1502,49 @@ void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw, } void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw, - u32 tx_pkt_shed_tc_data_weight, - u32 tc) + const u32 tc, + const u32 weight) { aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc), HW_ATL_TPS_DATA_TCTWEIGHT_MSK, HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT, - tx_pkt_shed_tc_data_weight); + weight); +} + +void hw_atl_tps_tx_desc_rate_mode_set(struct aq_hw_s *aq_hw, + const u32 rate_mode) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_TX_DESC_RATE_MODE_ADR, + HW_ATL_TPS_TX_DESC_RATE_MODE_MSK, + HW_ATL_TPS_TX_DESC_RATE_MODE_SHIFT, + rate_mode); +} + +void hw_atl_tps_tx_desc_rate_en_set(struct aq_hw_s *aq_hw, const u32 desc, + const u32 enable) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_EN_ADR(desc), + HW_ATL_TPS_DESC_RATE_EN_MSK, + HW_ATL_TPS_DESC_RATE_EN_SHIFT, + enable); +} + +void hw_atl_tps_tx_desc_rate_x_set(struct aq_hw_s *aq_hw, const u32 desc, + const u32 rate_int) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_X_ADR(desc), + HW_ATL_TPS_DESC_RATE_X_MSK, + HW_ATL_TPS_DESC_RATE_X_SHIFT, + rate_int); +} + +void hw_atl_tps_tx_desc_rate_y_set(struct aq_hw_s *aq_hw, const u32 desc, + const u32 rate_frac) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_Y_ADR(desc), + HW_ATL_TPS_DESC_RATE_Y_MSK, + HW_ATL_TPS_DESC_RATE_Y_SHIFT, + rate_frac); } /* tx */ diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h index 62992b23c0e8..61a6f70c51cd 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h @@ -349,6 +349,9 @@ void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw, u32 l2multicast_flr_en, u32 filter); +/* get l2 promiscuous mode enable */ +u32 hw_atl_rpfl2promiscuous_mode_en_get(struct aq_hw_s *aq_hw); + /* set l2 promiscuous mode enable */ void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw, u32 l2promiscuous_mode_en); @@ -420,6 +423,9 @@ void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht); void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw, u32 vlan_prom_mode_en); +/* Get VLAN promiscuous mode enable */ +u32 hw_atl_rpf_vlan_prom_mode_en_get(struct aq_hw_s *aq_hw); + /* Set VLAN untagged action */ void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw, u32 vlan_untagged_act); @@ -610,11 +616,11 @@ void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw, /* tpb */ /* set TX Traffic Class Mode */ -void hw_atl_rpb_tps_tx_tc_mode_set(struct aq_hw_s *aq_hw, +void hw_atl_tpb_tps_tx_tc_mode_set(struct aq_hw_s *aq_hw, u32 tx_traf_class_mode); /* get TX Traffic Class Mode */ -u32 hw_atl_rpb_tps_tx_tc_mode_get(struct aq_hw_s *aq_hw); +u32 hw_atl_tpb_tps_tx_tc_mode_get(struct aq_hw_s *aq_hw); /* set tx buffer enable */ void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en); @@ -682,13 +688,13 @@ void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw, /* set tx packet scheduler descriptor tc max credit */ void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw, - u32 max_credit, - u32 tc); + const u32 tc, + const u32 max_credit); /* set tx packet scheduler descriptor tc weight */ void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw, - u32 tx_pkt_shed_desc_tc_weight, - u32 tc); + const u32 tc, + const u32 weight); /* set tx packet scheduler descriptor vm arbitration mode */ void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw, @@ -696,13 +702,29 @@ void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw, /* set tx packet scheduler tc data max credit */ void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw, - u32 max_credit, - u32 tc); + const u32 tc, + const u32 max_credit); /* set tx packet scheduler tc data weight */ void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw, - u32 tx_pkt_shed_tc_data_weight, - u32 tc); + const u32 tc, + const u32 weight); + +/* set tx descriptor rate mode */ +void hw_atl_tps_tx_desc_rate_mode_set(struct aq_hw_s *aq_hw, + const u32 rate_mode); + +/* set tx packet scheduler descriptor rate enable */ +void hw_atl_tps_tx_desc_rate_en_set(struct aq_hw_s *aq_hw, const u32 desc, + const u32 enable); + +/* set tx packet scheduler descriptor rate integral value */ +void hw_atl_tps_tx_desc_rate_x_set(struct aq_hw_s *aq_hw, const u32 desc, + const u32 rate_int); + +/* set tx packet scheduler descriptor rate fractional value */ +void hw_atl_tps_tx_desc_rate_y_set(struct aq_hw_s *aq_hw, const u32 desc, + const u32 rate_frac); /* tx */ diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h index 18de2f7b8959..06220792daf1 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h @@ -2038,6 +2038,42 @@ /* default value of bitfield lso_tcp_flag_mid[b:0] */ #define HW_ATL_THM_LSO_TCP_FLAG_MID_DEFAULT 0x0 +/* tx tx_tc_mode bitfield definitions + * preprocessor definitions for the bitfield "tx_tc_mode". + * port="pif_tpb_tx_tc_mode_i,pif_tps_tx_tc_mode_i" + */ + +/* register address for bitfield tx_tc_mode */ +#define HW_ATL_TPB_TX_TC_MODE_ADDR 0x00007900 +/* bitmask for bitfield tx_tc_mode */ +#define HW_ATL_TPB_TX_TC_MODE_MSK 0x00000100 +/* inverted bitmask for bitfield tx_tc_mode */ +#define HW_ATL_TPB_TX_TC_MODE_MSKN 0xFFFFFEFF +/* lower bit position of bitfield tx_tc_mode */ +#define HW_ATL_TPB_TX_TC_MODE_SHIFT 8 +/* width of bitfield tx_tc_mode */ +#define HW_ATL_TPB_TX_TC_MODE_WIDTH 1 +/* default value of bitfield tx_tc_mode */ +#define HW_ATL_TPB_TX_TC_MODE_DEFAULT 0x0 + +/* tx tx_desc_rate_mode bitfield definitions + * preprocessor definitions for the bitfield "tx_desc_rate_mode". + * port="pif_tps_desc_rate_mode_i" + */ + +/* register address for bitfield tx_desc_rate_mode */ +#define HW_ATL_TPS_TX_DESC_RATE_MODE_ADR 0x00007900 +/* bitmask for bitfield tx_desc_rate_mode */ +#define HW_ATL_TPS_TX_DESC_RATE_MODE_MSK 0x00000080 +/* inverted bitmask for bitfield tx_desc_rate_mode */ +#define HW_ATL_TPS_TX_DESC_RATE_MODE_MSKN 0xFFFFFF7F +/* lower bit position of bitfield tx_desc_rate_mode */ +#define HW_ATL_TPS_TX_DESC_RATE_MODE_SHIFT 7 +/* width of bitfield tx_desc_rate_mode */ +#define HW_ATL_TPS_TX_DESC_RATE_MODE_WIDTH 1 +/* default value of bitfield tx_desc_rate_mode */ +#define HW_ATL_TPS_TX_DESC_RATE_MODE_DEFAULT 0x0 + /* tx tx_buf_en bitfield definitions * preprocessor definitions for the bitfield "tx_buf_en". * port="pif_tpb_tx_buf_en_i" @@ -2056,19 +2092,6 @@ /* default value of bitfield tx_buf_en */ #define HW_ATL_TPB_TX_BUF_EN_DEFAULT 0x0 -/* register address for bitfield tx_tc_mode */ -#define HW_ATL_TPB_TX_TC_MODE_ADDR 0x00007900 -/* bitmask for bitfield tx_tc_mode */ -#define HW_ATL_TPB_TX_TC_MODE_MSK 0x00000100 -/* inverted bitmask for bitfield tx_tc_mode */ -#define HW_ATL_TPB_TX_TC_MODE_MSKN 0xFFFFFEFF -/* lower bit position of bitfield tx_tc_mode */ -#define HW_ATL_TPB_TX_TC_MODE_SHIFT 8 -/* width of bitfield tx_tc_mode */ -#define HW_ATL_TPB_TX_TC_MODE_WIDTH 1 -/* default value of bitfield tx_tc_mode */ -#define HW_ATL_TPB_TX_TC_MODE_DEFAULT 0x0 - /* tx tx{b}_hi_thresh[c:0] bitfield definitions * preprocessor definitions for the bitfield "tx{b}_hi_thresh[c:0]". * parameter: buffer {b} | stride size 0x10 | range [0, 7] @@ -2270,6 +2293,58 @@ /* default value of bitfield data_tc_arb_mode */ #define HW_ATL_TPS_DATA_TC_ARB_MODE_DEFAULT 0x0 +/* tx desc{r}_rate_en bitfield definitions + * preprocessor definitions for the bitfield "desc{r}_rate_en". + * port="pif_tps_desc_rate_en_i[0]" + */ + +/* register address for bitfield desc{r}_rate_en */ +#define HW_ATL_TPS_DESC_RATE_EN_ADR(desc) (0x00007408 + (desc) * 0x10) +/* bitmask for bitfield desc{r}_rate_en */ +#define HW_ATL_TPS_DESC_RATE_EN_MSK 0x80000000 +/* inverted bitmask for bitfield desc{r}_rate_en */ +#define HW_ATL_TPS_DESC_RATE_EN_MSKN 0x7FFFFFFF +/* lower bit position of bitfield desc{r}_rate_en */ +#define HW_ATL_TPS_DESC_RATE_EN_SHIFT 31 +/* width of bitfield desc{r}_rate_en */ +#define HW_ATL_TPS_DESC_RATE_EN_WIDTH 1 +/* default value of bitfield desc{r}_rate_en */ +#define HW_ATL_TPS_DESC_RATE_EN_DEFAULT 0x0 + +/* tx desc{r}_rate_x bitfield definitions + * preprocessor definitions for the bitfield "desc{r}_rate_x". + * port="pif_tps_desc0_rate_x" + */ +/* register address for bitfield desc{r}_rate_x */ +#define HW_ATL_TPS_DESC_RATE_X_ADR(desc) (0x00007408 + (desc) * 0x10) +/* bitmask for bitfield desc{r}_rate_x */ +#define HW_ATL_TPS_DESC_RATE_X_MSK 0x03FF0000 +/* inverted bitmask for bitfield desc{r}_rate_x */ +#define HW_ATL_TPS_DESC_RATE_X_MSKN 0xFC00FFFF +/* lower bit position of bitfield desc{r}_rate_x */ +#define HW_ATL_TPS_DESC_RATE_X_SHIFT 16 +/* width of bitfield desc{r}_rate_x */ +#define HW_ATL_TPS_DESC_RATE_X_WIDTH 10 +/* default value of bitfield desc{r}_rate_x */ +#define HW_ATL_TPS_DESC_RATE_X_DEFAULT 0x0 + +/* tx desc{r}_rate_y bitfield definitions + * preprocessor definitions for the bitfield "desc{r}_rate_y". + * port="pif_tps_desc0_rate_y" + */ +/* register address for bitfield desc{r}_rate_y */ +#define HW_ATL_TPS_DESC_RATE_Y_ADR(desc) (0x00007408 + (desc) * 0x10) +/* bitmask for bitfield desc{r}_rate_y */ +#define HW_ATL_TPS_DESC_RATE_Y_MSK 0x00003FFF +/* inverted bitmask for bitfield desc{r}_rate_y */ +#define HW_ATL_TPS_DESC_RATE_Y_MSKN 0xFFFFC000 +/* lower bit position of bitfield desc{r}_rate_y */ +#define HW_ATL_TPS_DESC_RATE_Y_SHIFT 0 +/* width of bitfield desc{r}_rate_y */ +#define HW_ATL_TPS_DESC_RATE_Y_WIDTH 14 +/* default value of bitfield desc{r}_rate_y */ +#define HW_ATL_TPS_DESC_RATE_Y_DEFAULT 0x0 + /* tx desc_rate_ta_rst bitfield definitions * preprocessor definitions for the bitfield "desc_rate_ta_rst". * port="pif_tps_desc_rate_ta_rst_i" diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c index 354705f9bc49..73c0f41df8d8 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only -/* - * aQuantia Corporation Network Driver - * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved +/* Atlantic Network Driver + * + * Copyright (C) 2014-2019 aQuantia Corporation + * Copyright (C) 2019-2020 Marvell International Ltd. */ /* File hw_atl_utils.c: Definition of common functions for Atlantic hardware @@ -53,7 +54,6 @@ enum mcp_area { MCP_AREA_SETTINGS = 0x20000000, }; -static int hw_atl_utils_ver_match(u32 ver_expected, u32 ver_actual); static int hw_atl_utils_mpi_set_state(struct aq_hw_s *self, enum hal_atl_utils_fw_state_e state); static u32 hw_atl_utils_get_mpi_mbox_tid(struct aq_hw_s *self); @@ -67,14 +67,10 @@ int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops) { int err = 0; - err = hw_atl_utils_soft_reset(self); - if (err) - return err; - hw_atl_utils_hw_chip_features_init(self, &self->chip_features); - hw_atl_utils_get_fw_version(self, &self->fw_ver_actual); + self->fw_ver_actual = hw_atl_utils_get_fw_version(self); if (hw_atl_utils_ver_match(HW_ATL_FW_VER_1X, self->fw_ver_actual) == 0) { @@ -313,7 +309,7 @@ int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a, for (++cnt; --cnt && !err;) { aq_hw_write_reg(self, HW_ATL_MIF_CMD, 0x00008000U); - if (IS_CHIP_FEATURE(REVISION_B1)) + if (ATL_HW_IS_CHIP_FEATURE(self, REVISION_B1)) err = readx_poll_timeout_atomic(hw_atl_utils_mif_addr_get, self, val, val != a, 1U, 1000U); @@ -409,7 +405,7 @@ static int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 addr, u32 *p, if (err < 0) goto err_exit; - if (IS_CHIP_FEATURE(REVISION_B1)) + if (ATL_HW_IS_CHIP_FEATURE(self, REVISION_B1)) err = hw_atl_utils_write_b1_mbox(self, addr, p, cnt, area); else err = hw_atl_utils_write_b0_mbox(self, addr, p, cnt); @@ -438,7 +434,7 @@ int hw_atl_write_fwsettings_dwords(struct aq_hw_s *self, u32 offset, u32 *p, p, cnt, MCP_AREA_SETTINGS); } -static int hw_atl_utils_ver_match(u32 ver_expected, u32 ver_actual) +int hw_atl_utils_ver_match(u32 ver_expected, u32 ver_actual) { const u32 dw_major_mask = 0xff000000U; const u32 dw_minor_mask = 0x00ffffffU; @@ -501,7 +497,7 @@ int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size) struct aq_hw_atl_utils_fw_rpc_tid_s sw; int err = 0; - if (!IS_CHIP_FEATURE(MIPS)) { + if (!ATL_HW_IS_CHIP_FEATURE(self, MIPS)) { err = -1; goto err_exit; } @@ -607,7 +603,7 @@ void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self, if (err < 0) goto err_exit; - if (IS_CHIP_FEATURE(REVISION_A0)) { + if (ATL_HW_IS_CHIP_FEATURE(self, REVISION_A0)) { unsigned int mtu = self->aq_nic_cfg ? self->aq_nic_cfg->mtu : 1514U; pmbox->stats.ubrc = pmbox->stats.uprc * mtu; @@ -692,7 +688,7 @@ int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self) link_status->mbps = 5000U; break; - case HAL_ATLANTIC_RATE_2GS: + case HAL_ATLANTIC_RATE_2G5: link_status->mbps = 2500U; break; @@ -806,22 +802,24 @@ void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p) u32 mif_rev = val & 0xFFU; u32 chip_features = 0U; + chip_features |= ATL_HW_CHIP_ATLANTIC; + if ((0xFU & mif_rev) == 1U) { - chip_features |= HAL_ATLANTIC_UTILS_CHIP_REVISION_A0 | - HAL_ATLANTIC_UTILS_CHIP_MPI_AQ | - HAL_ATLANTIC_UTILS_CHIP_MIPS; + chip_features |= ATL_HW_CHIP_REVISION_A0 | + ATL_HW_CHIP_MPI_AQ | + ATL_HW_CHIP_MIPS; } else if ((0xFU & mif_rev) == 2U) { - chip_features |= HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 | - HAL_ATLANTIC_UTILS_CHIP_MPI_AQ | - HAL_ATLANTIC_UTILS_CHIP_MIPS | - HAL_ATLANTIC_UTILS_CHIP_TPO2 | - HAL_ATLANTIC_UTILS_CHIP_RPF2; + chip_features |= ATL_HW_CHIP_REVISION_B0 | + ATL_HW_CHIP_MPI_AQ | + ATL_HW_CHIP_MIPS | + ATL_HW_CHIP_TPO2 | + ATL_HW_CHIP_RPF2; } else if ((0xFU & mif_rev) == 0xAU) { - chip_features |= HAL_ATLANTIC_UTILS_CHIP_REVISION_B1 | - HAL_ATLANTIC_UTILS_CHIP_MPI_AQ | - HAL_ATLANTIC_UTILS_CHIP_MIPS | - HAL_ATLANTIC_UTILS_CHIP_TPO2 | - HAL_ATLANTIC_UTILS_CHIP_RPF2; + chip_features |= ATL_HW_CHIP_REVISION_B1 | + ATL_HW_CHIP_MPI_AQ | + ATL_HW_CHIP_MIPS | + ATL_HW_CHIP_TPO2 | + ATL_HW_CHIP_RPF2; } *p = chip_features; @@ -919,11 +917,9 @@ int hw_atl_utils_hw_get_regs(struct aq_hw_s *self, return 0; } -int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version) +u32 hw_atl_utils_get_fw_version(struct aq_hw_s *self) { - *fw_version = aq_hw_read_reg(self, 0x18U); - - return 0; + return aq_hw_read_reg(self, HW_ATL_MPI_FW_VERSION); } static int aq_fw1x_set_wake_magic(struct aq_hw_s *self, bool wol_enabled, diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h index b15513914636..0b4b54fc1de0 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* - * aQuantia Corporation Network Driver - * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved +/* Atlantic Network Driver + * + * Copyright (C) 2014-2019 aQuantia Corporation + * Copyright (C) 2019-2020 Marvell International Ltd. */ /* File hw_atl_utils.h: Declaration of common functions for Atlantic hardware @@ -360,6 +361,8 @@ struct aq_rx_filter_vlan { u8 queue; }; +#define HW_ATL_VLAN_MAX_FILTERS 16U + struct aq_rx_filter_l2 { s8 queue; u8 location; @@ -406,17 +409,6 @@ enum hw_atl_rx_ctrl_registers_l3l4 { #define HW_ATL_GET_REG_LOCATION_FL3L4(location) \ ((location) - AQ_RX_FIRST_LOC_FL3L4) -#define HAL_ATLANTIC_UTILS_CHIP_MIPS 0x00000001U -#define HAL_ATLANTIC_UTILS_CHIP_TPO2 0x00000002U -#define HAL_ATLANTIC_UTILS_CHIP_RPF2 0x00000004U -#define HAL_ATLANTIC_UTILS_CHIP_MPI_AQ 0x00000010U -#define HAL_ATLANTIC_UTILS_CHIP_REVISION_A0 0x01000000U -#define HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 0x02000000U -#define HAL_ATLANTIC_UTILS_CHIP_REVISION_B1 0x04000000U - -#define IS_CHIP_FEATURE(_F_) (HAL_ATLANTIC_UTILS_CHIP_##_F_ & \ - self->chip_features) - enum hal_atl_utils_fw_state_e { MPI_DEINIT = 0, MPI_RESET = 1, @@ -427,7 +419,7 @@ enum hal_atl_utils_fw_state_e { #define HAL_ATLANTIC_RATE_10G BIT(0) #define HAL_ATLANTIC_RATE_5G BIT(1) #define HAL_ATLANTIC_RATE_5GSR BIT(2) -#define HAL_ATLANTIC_RATE_2GS BIT(3) +#define HAL_ATLANTIC_RATE_2G5 BIT(3) #define HAL_ATLANTIC_RATE_1G BIT(4) #define HAL_ATLANTIC_RATE_100M BIT(5) #define HAL_ATLANTIC_RATE_INVALID BIT(6) @@ -622,7 +614,7 @@ int hw_atl_utils_hw_set_power(struct aq_hw_s *self, int hw_atl_utils_hw_deinit(struct aq_hw_s *self); -int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version); +u32 hw_atl_utils_get_fw_version(struct aq_hw_s *self); int hw_atl_utils_update_stats(struct aq_hw_s *self); @@ -643,6 +635,8 @@ int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size); int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self, struct hw_atl_utils_fw_rpc **rpc); +int hw_atl_utils_ver_match(u32 ver_expected, u32 ver_actual); + extern const struct aq_fw_ops aq_fw_1x_ops; extern const struct aq_fw_ops aq_fw_2x_ops; diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c index 1ad10cc14918..eeedd8c90067 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only -/* - * aQuantia Corporation Network Driver - * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved +/* Atlantic Network Driver + * + * Copyright (C) 2014-2019 aQuantia Corporation + * Copyright (C) 2019-2020 Marvell International Ltd. */ /* File hw_atl_utils_fw2x.c: Definition of firmware 2.x functions for @@ -134,7 +135,7 @@ static enum hw_atl_fw2x_rate link_speed_mask_2fw2x_ratemask(u32 speed) if (speed & AQ_NIC_RATE_5GSR) rate |= FW2X_RATE_5G; - if (speed & AQ_NIC_RATE_2GS) + if (speed & AQ_NIC_RATE_2G5) rate |= FW2X_RATE_2G5; if (speed & AQ_NIC_RATE_1G) @@ -155,7 +156,7 @@ static u32 fw2x_to_eee_mask(u32 speed) if (speed & HW_ATL_FW2X_CAP_EEE_5G_MASK) rate |= AQ_NIC_RATE_EEE_5G; if (speed & HW_ATL_FW2X_CAP_EEE_2G5_MASK) - rate |= AQ_NIC_RATE_EEE_2GS; + rate |= AQ_NIC_RATE_EEE_2G5; if (speed & HW_ATL_FW2X_CAP_EEE_1G_MASK) rate |= AQ_NIC_RATE_EEE_1G; @@ -170,7 +171,7 @@ static u32 eee_mask_to_fw2x(u32 speed) rate |= HW_ATL_FW2X_CAP_EEE_10G_MASK; if (speed & AQ_NIC_RATE_EEE_5G) rate |= HW_ATL_FW2X_CAP_EEE_5G_MASK; - if (speed & AQ_NIC_RATE_EEE_2GS) + if (speed & AQ_NIC_RATE_EEE_2G5) rate |= HW_ATL_FW2X_CAP_EEE_2G5_MASK; if (speed & AQ_NIC_RATE_EEE_1G) rate |= HW_ATL_FW2X_CAP_EEE_1G_MASK; @@ -282,8 +283,6 @@ static int aq_fw2x_get_mac_permanent(struct aq_hw_s *self, u8 *mac) u32 efuse_addr = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_EFUSE_ADDR); u32 mac_addr[2] = { 0 }; int err = 0; - u32 h = 0U; - u32 l = 0U; if (efuse_addr != 0) { err = hw_atl_utils_fw_downld_dwords(self, @@ -298,26 +297,6 @@ static int aq_fw2x_get_mac_permanent(struct aq_hw_s *self, u8 *mac) ether_addr_copy(mac, (u8 *)mac_addr); - if ((mac[0] & 0x01U) || ((mac[0] | mac[1] | mac[2]) == 0x00U)) { - unsigned int rnd = 0; - - get_random_bytes(&rnd, sizeof(unsigned int)); - - l = 0xE3000000U | (0xFFFFU & rnd) | (0x00 << 16); - h = 0x8001300EU; - - mac[5] = (u8)(0xFFU & l); - l >>= 8; - mac[4] = (u8)(0xFFU & l); - l >>= 8; - mac[3] = (u8)(0xFFU & l); - l >>= 8; - mac[2] = (u8)(0xFFU & l); - mac[1] = (u8)(0xFFU & h); - h >>= 8; - mac[0] = (u8)(0xFFU & h); - } - return err; } diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c new file mode 100644 index 000000000000..8df9d4ef36f0 --- /dev/null +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c @@ -0,0 +1,841 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Atlantic Network Driver + * Copyright (C) 2020 Marvell International Ltd. + */ + +#include "aq_hw.h" +#include "aq_hw_utils.h" +#include "aq_ring.h" +#include "aq_nic.h" +#include "hw_atl/hw_atl_b0.h" +#include "hw_atl/hw_atl_utils.h" +#include "hw_atl/hw_atl_llh.h" +#include "hw_atl/hw_atl_llh_internal.h" +#include "hw_atl2_utils.h" +#include "hw_atl2_llh.h" +#include "hw_atl2_internal.h" +#include "hw_atl2_llh_internal.h" + +static int hw_atl2_act_rslvr_table_set(struct aq_hw_s *self, u8 location, + u32 tag, u32 mask, u32 action); + +#define DEFAULT_BOARD_BASIC_CAPABILITIES \ + .is_64_dma = true, \ + .msix_irqs = 8U, \ + .irq_mask = ~0U, \ + .vecs = HW_ATL2_RSS_MAX, \ + .tcs_max = HW_ATL2_TC_MAX, \ + .rxd_alignment = 1U, \ + .rxd_size = HW_ATL2_RXD_SIZE, \ + .rxds_max = HW_ATL2_MAX_RXD, \ + .rxds_min = HW_ATL2_MIN_RXD, \ + .txd_alignment = 1U, \ + .txd_size = HW_ATL2_TXD_SIZE, \ + .txds_max = HW_ATL2_MAX_TXD, \ + .txds_min = HW_ATL2_MIN_TXD, \ + .txhwb_alignment = 4096U, \ + .tx_rings = HW_ATL2_TX_RINGS, \ + .rx_rings = HW_ATL2_RX_RINGS, \ + .hw_features = NETIF_F_HW_CSUM | \ + NETIF_F_RXCSUM | \ + NETIF_F_RXHASH | \ + NETIF_F_SG | \ + NETIF_F_TSO | \ + NETIF_F_TSO6 | \ + NETIF_F_LRO | \ + NETIF_F_NTUPLE | \ + NETIF_F_HW_VLAN_CTAG_FILTER | \ + NETIF_F_HW_VLAN_CTAG_RX | \ + NETIF_F_HW_VLAN_CTAG_TX | \ + NETIF_F_GSO_UDP_L4 | \ + NETIF_F_GSO_PARTIAL | \ + NETIF_F_HW_TC, \ + .hw_priv_flags = IFF_UNICAST_FLT, \ + .flow_control = true, \ + .mtu = HW_ATL2_MTU_JUMBO, \ + .mac_regs_count = 72, \ + .hw_alive_check_addr = 0x10U, \ + .priv_data_len = sizeof(struct hw_atl2_priv) + +const struct aq_hw_caps_s hw_atl2_caps_aqc113 = { + DEFAULT_BOARD_BASIC_CAPABILITIES, + .media_type = AQ_HW_MEDIA_TYPE_TP, + .link_speed_msk = AQ_NIC_RATE_10G | + AQ_NIC_RATE_5G | + AQ_NIC_RATE_2G5 | + AQ_NIC_RATE_1G | + AQ_NIC_RATE_100M | + AQ_NIC_RATE_10M, +}; + +static u32 hw_atl2_sem_act_rslvr_get(struct aq_hw_s *self) +{ + return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL2_FW_SM_ACT_RSLVR); +} + +static int hw_atl2_hw_reset(struct aq_hw_s *self) +{ + struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv; + int err; + + err = hw_atl2_utils_soft_reset(self); + if (err) + return err; + + memset(priv, 0, sizeof(*priv)); + + self->aq_fw_ops->set_state(self, MPI_RESET); + + err = aq_hw_err_from_flags(self); + + return err; +} + +static int hw_atl2_hw_queue_to_tc_map_set(struct aq_hw_s *self) +{ + struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; + unsigned int tcs, q_per_tc; + unsigned int tc, q; + u32 rx_map = 0; + u32 tx_map = 0; + + hw_atl2_tpb_tx_tc_q_rand_map_en_set(self, 1U); + + switch (cfg->tc_mode) { + case AQ_TC_MODE_8TCS: + tcs = 8; + q_per_tc = 4; + break; + case AQ_TC_MODE_4TCS: + tcs = 4; + q_per_tc = 8; + break; + default: + return -EINVAL; + } + + for (tc = 0; tc != tcs; tc++) { + unsigned int tc_q_offset = tc * q_per_tc; + + for (q = tc_q_offset; q != tc_q_offset + q_per_tc; q++) { + rx_map |= tc << HW_ATL2_RX_Q_TC_MAP_SHIFT(q); + if (HW_ATL2_RX_Q_TC_MAP_ADR(q) != + HW_ATL2_RX_Q_TC_MAP_ADR(q + 1)) { + aq_hw_write_reg(self, + HW_ATL2_RX_Q_TC_MAP_ADR(q), + rx_map); + rx_map = 0; + } + + tx_map |= tc << HW_ATL2_TX_Q_TC_MAP_SHIFT(q); + if (HW_ATL2_TX_Q_TC_MAP_ADR(q) != + HW_ATL2_TX_Q_TC_MAP_ADR(q + 1)) { + aq_hw_write_reg(self, + HW_ATL2_TX_Q_TC_MAP_ADR(q), + tx_map); + tx_map = 0; + } + } + } + + return aq_hw_err_from_flags(self); +} + +static int hw_atl2_hw_qos_set(struct aq_hw_s *self) +{ + struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; + u32 tx_buff_size = HW_ATL2_TXBUF_MAX; + u32 rx_buff_size = HW_ATL2_RXBUF_MAX; + unsigned int prio = 0U; + u32 tc = 0U; + + /* TPS Descriptor rate init */ + hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U); + hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA); + + /* TPS VM init */ + hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U); + + tx_buff_size /= cfg->tcs; + rx_buff_size /= cfg->tcs; + for (tc = 0; tc < cfg->tcs; tc++) { + u32 threshold = 0U; + + /* Tx buf size TC0 */ + hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, tx_buff_size, tc); + + threshold = (tx_buff_size * (1024 / 32U) * 66U) / 100U; + hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self, threshold, tc); + + threshold = (tx_buff_size * (1024 / 32U) * 50U) / 100U; + hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self, threshold, tc); + + /* QoS Rx buf size per TC */ + hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, rx_buff_size, tc); + + threshold = (rx_buff_size * (1024U / 32U) * 66U) / 100U; + hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self, threshold, tc); + + threshold = (rx_buff_size * (1024U / 32U) * 50U) / 100U; + hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self, threshold, tc); + } + + /* QoS 802.1p priority -> TC mapping */ + for (prio = 0; prio < 8; ++prio) + hw_atl_rpf_rpb_user_priority_tc_map_set(self, prio, + cfg->prio_tc_map[prio]); + + /* ATL2 Apply ring to TC mapping */ + hw_atl2_hw_queue_to_tc_map_set(self); + + return aq_hw_err_from_flags(self); +} + +static int hw_atl2_hw_rss_set(struct aq_hw_s *self, + struct aq_rss_parameters *rss_params) +{ + u8 *indirection_table = rss_params->indirection_table; + const u32 num_tcs = aq_hw_num_tcs(self); + u32 rpf_redir2_enable; + int tc; + int i; + + rpf_redir2_enable = num_tcs > 4 ? 1 : 0; + + hw_atl2_rpf_redirection_table2_select_set(self, rpf_redir2_enable); + + for (i = HW_ATL2_RSS_REDIRECTION_MAX; i--;) { + for (tc = 0; tc != num_tcs; tc++) { + hw_atl2_new_rpf_rss_redir_set(self, tc, i, + tc * + aq_hw_q_per_tc(self) + + indirection_table[i]); + } + } + + return aq_hw_err_from_flags(self); +} + +static int hw_atl2_hw_init_tx_tc_rate_limit(struct aq_hw_s *self) +{ + static const u32 max_weight = BIT(HW_ATL2_TPS_DATA_TCTWEIGHT_WIDTH) - 1; + /* Scale factor is based on the number of bits in fractional portion */ + static const u32 scale = BIT(HW_ATL_TPS_DESC_RATE_Y_WIDTH); + static const u32 frac_msk = HW_ATL_TPS_DESC_RATE_Y_MSK >> + HW_ATL_TPS_DESC_RATE_Y_SHIFT; + const u32 link_speed = self->aq_link_status.mbps; + struct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg; + unsigned long num_min_rated_tcs = 0; + u32 tc_weight[AQ_CFG_TCS_MAX]; + u32 fixed_max_credit_4b; + u32 fixed_max_credit; + u8 min_rate_msk = 0; + u32 sum_weight = 0; + int tc; + + /* By default max_credit is based upon MTU (in unit of 64b) */ + fixed_max_credit = nic_cfg->aq_hw_caps->mtu / 64; + /* in unit of 4b */ + fixed_max_credit_4b = nic_cfg->aq_hw_caps->mtu / 4; + + if (link_speed) { + min_rate_msk = nic_cfg->tc_min_rate_msk & + (BIT(nic_cfg->tcs) - 1); + num_min_rated_tcs = hweight8(min_rate_msk); + } + + /* First, calculate weights where min_rate is specified */ + if (num_min_rated_tcs) { + for (tc = 0; tc != nic_cfg->tcs; tc++) { + if (!nic_cfg->tc_min_rate[tc]) { + tc_weight[tc] = 0; + continue; + } + + tc_weight[tc] = (-1L + link_speed + + nic_cfg->tc_min_rate[tc] * + max_weight) / + link_speed; + tc_weight[tc] = min(tc_weight[tc], max_weight); + sum_weight += tc_weight[tc]; + } + } + + /* WSP, if min_rate is set for at least one TC. + * RR otherwise. + */ + hw_atl2_tps_tx_pkt_shed_data_arb_mode_set(self, min_rate_msk ? 1U : 0U); + /* Data TC Arbiter takes precedence over Descriptor TC Arbiter, + * leave Descriptor TC Arbiter as RR. + */ + hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U); + + hw_atl_tps_tx_desc_rate_mode_set(self, nic_cfg->is_qos ? 1U : 0U); + + for (tc = 0; tc != nic_cfg->tcs; tc++) { + const u32 en = (nic_cfg->tc_max_rate[tc] != 0) ? 1U : 0U; + const u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0); + u32 weight, max_credit; + + hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, tc, + fixed_max_credit); + hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, tc, 0x1E); + + if (num_min_rated_tcs) { + weight = tc_weight[tc]; + + if (!weight && sum_weight < max_weight) + weight = (max_weight - sum_weight) / + (nic_cfg->tcs - num_min_rated_tcs); + else if (!weight) + weight = 0x640; + + max_credit = max(2 * weight, fixed_max_credit_4b); + } else { + weight = 0x640; + max_credit = 0xFFF0; + } + + hw_atl2_tps_tx_pkt_shed_tc_data_weight_set(self, tc, weight); + hw_atl2_tps_tx_pkt_shed_tc_data_max_credit_set(self, tc, + max_credit); + + hw_atl_tps_tx_desc_rate_en_set(self, desc, en); + + if (en) { + /* Nominal rate is always 10G */ + const u32 rate = 10000U * scale / + nic_cfg->tc_max_rate[tc]; + const u32 rate_int = rate >> + HW_ATL_TPS_DESC_RATE_Y_WIDTH; + const u32 rate_frac = rate & frac_msk; + + hw_atl_tps_tx_desc_rate_x_set(self, desc, rate_int); + hw_atl_tps_tx_desc_rate_y_set(self, desc, rate_frac); + } else { + /* A value of 1 indicates the queue is not + * rate controlled. + */ + hw_atl_tps_tx_desc_rate_x_set(self, desc, 1U); + hw_atl_tps_tx_desc_rate_y_set(self, desc, 0U); + } + } + for (tc = nic_cfg->tcs; tc != AQ_CFG_TCS_MAX; tc++) { + const u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0); + + hw_atl_tps_tx_desc_rate_en_set(self, desc, 0U); + hw_atl_tps_tx_desc_rate_x_set(self, desc, 1U); + hw_atl_tps_tx_desc_rate_y_set(self, desc, 0U); + } + + return aq_hw_err_from_flags(self); +} + +static int hw_atl2_hw_init_tx_path(struct aq_hw_s *self) +{ + struct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg; + + /* Tx TC/RSS number config */ + hw_atl_tpb_tps_tx_tc_mode_set(self, nic_cfg->tc_mode); + + hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U); + hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U); + hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU); + + /* Tx interrupts */ + hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U); + + /* misc */ + hw_atl_tdm_tx_dca_en_set(self, 0U); + hw_atl_tdm_tx_dca_mode_set(self, 0U); + + hw_atl_tpb_tx_path_scp_ins_en_set(self, 1U); + + hw_atl2_tpb_tx_buf_clk_gate_en_set(self, 0U); + + return aq_hw_err_from_flags(self); +} + +static void hw_atl2_hw_init_new_rx_filters(struct aq_hw_s *self) +{ + struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv; + u8 *prio_tc_map = self->aq_nic_cfg->prio_tc_map; + u16 action; + u8 index; + int i; + + /* Action Resolver Table (ART) is used by RPF to decide which action + * to take with a packet based upon input tag and tag mask, where: + * - input tag is a combination of 3-bit VLan Prio (PTP) and + * 29-bit concatenation of all tags from filter block; + * - tag mask is a mask used for matching against input tag. + * The input_tag is compared with the all the Requested_tags in the + * Record table to find a match. Action field of the selected matched + * REC entry is used for further processing. If multiple entries match, + * the lowest REC entry, Action field will be selected. + */ + hw_atl2_rpf_act_rslvr_section_en_set(self, 0xFFFF); + hw_atl2_rpfl2_uc_flr_tag_set(self, HW_ATL2_RPF_TAG_BASE_UC, + HW_ATL2_MAC_UC); + hw_atl2_rpfl2_bc_flr_tag_set(self, HW_ATL2_RPF_TAG_BASE_UC); + + /* FW reserves the beginning of ART, thus all driver entries must + * start from the offset specified in FW caps. + */ + index = priv->art_base_index + HW_ATL2_RPF_L2_PROMISC_OFF_INDEX; + hw_atl2_act_rslvr_table_set(self, index, 0, + HW_ATL2_RPF_TAG_UC_MASK | + HW_ATL2_RPF_TAG_ALLMC_MASK, + HW_ATL2_ACTION_DROP); + + index = priv->art_base_index + HW_ATL2_RPF_VLAN_PROMISC_OFF_INDEX; + hw_atl2_act_rslvr_table_set(self, index, 0, + HW_ATL2_RPF_TAG_VLAN_MASK | + HW_ATL2_RPF_TAG_UNTAG_MASK, + HW_ATL2_ACTION_DROP); + + /* Configure ART to map given VLan Prio (PCP) to the TC index for + * RSS redirection table. + */ + for (i = 0; i < 8; i++) { + action = HW_ATL2_ACTION_ASSIGN_TC(prio_tc_map[i]); + + index = priv->art_base_index + HW_ATL2_RPF_PCP_TO_TC_INDEX + i; + hw_atl2_act_rslvr_table_set(self, index, + i << HW_ATL2_RPF_TAG_PCP_OFFSET, + HW_ATL2_RPF_TAG_PCP_MASK, action); + } +} + +static void hw_atl2_hw_new_rx_filter_vlan_promisc(struct aq_hw_s *self, + bool promisc) +{ + u16 off_action = (!promisc && + !hw_atl_rpfl2promiscuous_mode_en_get(self)) ? + HW_ATL2_ACTION_DROP : HW_ATL2_ACTION_DISABLE; + struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv; + u8 index; + + index = priv->art_base_index + HW_ATL2_RPF_VLAN_PROMISC_OFF_INDEX; + hw_atl2_act_rslvr_table_set(self, index, 0, + HW_ATL2_RPF_TAG_VLAN_MASK | + HW_ATL2_RPF_TAG_UNTAG_MASK, off_action); +} + +static void hw_atl2_hw_new_rx_filter_promisc(struct aq_hw_s *self, bool promisc) +{ + u16 off_action = promisc ? HW_ATL2_ACTION_DISABLE : HW_ATL2_ACTION_DROP; + struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv; + bool vlan_promisc_enable; + u8 index; + + index = priv->art_base_index + HW_ATL2_RPF_L2_PROMISC_OFF_INDEX; + hw_atl2_act_rslvr_table_set(self, index, 0, + HW_ATL2_RPF_TAG_UC_MASK | + HW_ATL2_RPF_TAG_ALLMC_MASK, + off_action); + + /* turn VLAN promisc mode too */ + vlan_promisc_enable = hw_atl_rpf_vlan_prom_mode_en_get(self); + hw_atl2_hw_new_rx_filter_vlan_promisc(self, promisc | + vlan_promisc_enable); +} + +static int hw_atl2_act_rslvr_table_set(struct aq_hw_s *self, u8 location, + u32 tag, u32 mask, u32 action) +{ + u32 val; + int err; + + err = readx_poll_timeout_atomic(hw_atl2_sem_act_rslvr_get, + self, val, val == 1, + 1, 10000U); + if (err) + return err; + + hw_atl2_rpf_act_rslvr_record_set(self, location, tag, mask, + action); + + hw_atl_reg_glb_cpu_sem_set(self, 1, HW_ATL2_FW_SM_ACT_RSLVR); + + return err; +} + +static int hw_atl2_hw_init_rx_path(struct aq_hw_s *self) +{ + struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; + int i; + + /* Rx TC/RSS number config */ + hw_atl_rpb_rpf_rx_traf_class_mode_set(self, cfg->tc_mode); + + /* Rx flow control */ + hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U); + + hw_atl2_rpf_rss_hash_type_set(self, HW_ATL2_RPF_RSS_HASH_TYPE_ALL); + + /* RSS Ring selection */ + hw_atl_b0_hw_init_rx_rss_ctrl1(self); + + /* Multicast filters */ + for (i = HW_ATL2_MAC_MAX; i--;) { + hw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i); + hw_atl_rpfl2unicast_flr_act_set(self, 1U, i); + } + + hw_atl_reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U); + hw_atl_reg_rx_flr_mcst_flr_set(self, HW_ATL_MCAST_FLT_ANY_TO_HOST, 0U); + + /* Vlan filters */ + hw_atl_rpf_vlan_outer_etht_set(self, ETH_P_8021AD); + hw_atl_rpf_vlan_inner_etht_set(self, ETH_P_8021Q); + + hw_atl_rpf_vlan_prom_mode_en_set(self, 1); + + /* Always accept untagged packets */ + hw_atl_rpf_vlan_accept_untagged_packets_set(self, 1U); + hw_atl_rpf_vlan_untagged_act_set(self, 1U); + + hw_atl2_hw_init_new_rx_filters(self); + + /* Rx Interrupts */ + hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U); + + hw_atl_rpfl2broadcast_flr_act_set(self, 1U); + hw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U)); + + hw_atl_rdm_rx_dca_en_set(self, 0U); + hw_atl_rdm_rx_dca_mode_set(self, 0U); + + return aq_hw_err_from_flags(self); +} + +static int hw_atl2_hw_init(struct aq_hw_s *self, u8 *mac_addr) +{ + static u32 aq_hw_atl2_igcr_table_[4][2] = { + [AQ_HW_IRQ_INVALID] = { 0x20000000U, 0x20000000U }, + [AQ_HW_IRQ_LEGACY] = { 0x20000080U, 0x20000080U }, + [AQ_HW_IRQ_MSI] = { 0x20000021U, 0x20000025U }, + [AQ_HW_IRQ_MSIX] = { 0x20000022U, 0x20000026U }, + }; + + struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv; + struct aq_nic_cfg_s *aq_nic_cfg = self->aq_nic_cfg; + u8 base_index, count; + int err; + + err = hw_atl2_utils_get_action_resolve_table_caps(self, &base_index, + &count); + if (err) + return err; + + priv->art_base_index = 8 * base_index; + + hw_atl2_init_launchtime(self); + + hw_atl2_hw_init_tx_path(self); + hw_atl2_hw_init_rx_path(self); + + hw_atl_b0_hw_mac_addr_set(self, mac_addr); + + self->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk); + self->aq_fw_ops->set_state(self, MPI_INIT); + + hw_atl2_hw_qos_set(self); + hw_atl2_hw_rss_set(self, &aq_nic_cfg->aq_rss); + hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss); + + hw_atl2_rpf_new_enable_set(self, 1); + + /* Reset link status and read out initial hardware counters */ + self->aq_link_status.mbps = 0; + self->aq_fw_ops->update_stats(self); + + err = aq_hw_err_from_flags(self); + if (err < 0) + goto err_exit; + + /* Interrupts */ + hw_atl_reg_irq_glb_ctl_set(self, + aq_hw_atl2_igcr_table_[aq_nic_cfg->irq_type] + [(aq_nic_cfg->vecs > 1U) ? + 1 : 0]); + + hw_atl_itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask); + + /* Interrupts */ + hw_atl_reg_gen_irq_map_set(self, + ((HW_ATL2_ERR_INT << 0x18) | + (1U << 0x1F)) | + ((HW_ATL2_ERR_INT << 0x10) | + (1U << 0x17)), 0U); + + hw_atl_b0_hw_offload_set(self, aq_nic_cfg); + +err_exit: + return err; +} + +static int hw_atl2_hw_ring_rx_init(struct aq_hw_s *self, + struct aq_ring_s *aq_ring, + struct aq_ring_param_s *aq_ring_param) +{ + return hw_atl_b0_hw_ring_rx_init(self, aq_ring, aq_ring_param); +} + +static int hw_atl2_hw_ring_tx_init(struct aq_hw_s *self, + struct aq_ring_s *aq_ring, + struct aq_ring_param_s *aq_ring_param) +{ + return hw_atl_b0_hw_ring_tx_init(self, aq_ring, aq_ring_param); +} + +#define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U) + +static int hw_atl2_hw_packet_filter_set(struct aq_hw_s *self, + unsigned int packet_filter) +{ + hw_atl2_hw_new_rx_filter_promisc(self, IS_FILTER_ENABLED(IFF_PROMISC)); + + return hw_atl_b0_hw_packet_filter_set(self, packet_filter); +} + +#undef IS_FILTER_ENABLED + +static int hw_atl2_hw_multicast_list_set(struct aq_hw_s *self, + u8 ar_mac + [AQ_HW_MULTICAST_ADDRESS_MAX] + [ETH_ALEN], + u32 count) +{ + struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; + int err = 0; + + if (count > (HW_ATL2_MAC_MAX - HW_ATL2_MAC_MIN)) { + err = -EBADRQC; + goto err_exit; + } + for (cfg->mc_list_count = 0U; + cfg->mc_list_count < count; + ++cfg->mc_list_count) { + u32 i = cfg->mc_list_count; + u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]); + u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) | + (ar_mac[i][4] << 8) | ar_mac[i][5]; + + hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL2_MAC_MIN + i); + + hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, + HW_ATL2_MAC_MIN + i); + + hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, + HW_ATL2_MAC_MIN + i); + + hw_atl2_rpfl2_uc_flr_tag_set(self, 1, HW_ATL2_MAC_MIN + i); + + hw_atl_rpfl2_uc_flr_en_set(self, (cfg->is_mc_list_enabled), + HW_ATL2_MAC_MIN + i); + } + + err = aq_hw_err_from_flags(self); + +err_exit: + return err; +} + +static int hw_atl2_hw_interrupt_moderation_set(struct aq_hw_s *self) +{ + unsigned int i = 0U; + u32 itr_tx = 2U; + u32 itr_rx = 2U; + + switch (self->aq_nic_cfg->itr) { + case AQ_CFG_INTERRUPT_MODERATION_ON: + case AQ_CFG_INTERRUPT_MODERATION_AUTO: + hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 0U); + hw_atl_tdm_tdm_intr_moder_en_set(self, 1U); + hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 0U); + hw_atl_rdm_rdm_intr_moder_en_set(self, 1U); + + if (self->aq_nic_cfg->itr == AQ_CFG_INTERRUPT_MODERATION_ON) { + /* HW timers are in 2us units */ + int tx_max_timer = self->aq_nic_cfg->tx_itr / 2; + int tx_min_timer = tx_max_timer / 2; + + int rx_max_timer = self->aq_nic_cfg->rx_itr / 2; + int rx_min_timer = rx_max_timer / 2; + + tx_max_timer = min(HW_ATL2_INTR_MODER_MAX, + tx_max_timer); + tx_min_timer = min(HW_ATL2_INTR_MODER_MIN, + tx_min_timer); + rx_max_timer = min(HW_ATL2_INTR_MODER_MAX, + rx_max_timer); + rx_min_timer = min(HW_ATL2_INTR_MODER_MIN, + rx_min_timer); + + itr_tx |= tx_min_timer << 0x8U; + itr_tx |= tx_max_timer << 0x10U; + itr_rx |= rx_min_timer << 0x8U; + itr_rx |= rx_max_timer << 0x10U; + } else { + static unsigned int hw_atl2_timers_table_tx_[][2] = { + {0xfU, 0xffU}, /* 10Gbit */ + {0xfU, 0x1ffU}, /* 5Gbit */ + {0xfU, 0x1ffU}, /* 5Gbit 5GS */ + {0xfU, 0x1ffU}, /* 2.5Gbit */ + {0xfU, 0x1ffU}, /* 1Gbit */ + {0xfU, 0x1ffU}, /* 100Mbit */ + }; + static unsigned int hw_atl2_timers_table_rx_[][2] = { + {0x6U, 0x38U},/* 10Gbit */ + {0xCU, 0x70U},/* 5Gbit */ + {0xCU, 0x70U},/* 5Gbit 5GS */ + {0x18U, 0xE0U},/* 2.5Gbit */ + {0x30U, 0x80U},/* 1Gbit */ + {0x4U, 0x50U},/* 100Mbit */ + }; + unsigned int mbps = self->aq_link_status.mbps; + unsigned int speed_index; + + speed_index = hw_atl_utils_mbps_2_speed_index(mbps); + + /* Update user visible ITR settings */ + self->aq_nic_cfg->tx_itr = hw_atl2_timers_table_tx_ + [speed_index][1] * 2; + self->aq_nic_cfg->rx_itr = hw_atl2_timers_table_rx_ + [speed_index][1] * 2; + + itr_tx |= hw_atl2_timers_table_tx_ + [speed_index][0] << 0x8U; + itr_tx |= hw_atl2_timers_table_tx_ + [speed_index][1] << 0x10U; + + itr_rx |= hw_atl2_timers_table_rx_ + [speed_index][0] << 0x8U; + itr_rx |= hw_atl2_timers_table_rx_ + [speed_index][1] << 0x10U; + } + break; + case AQ_CFG_INTERRUPT_MODERATION_OFF: + hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U); + hw_atl_tdm_tdm_intr_moder_en_set(self, 0U); + hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U); + hw_atl_rdm_rdm_intr_moder_en_set(self, 0U); + itr_tx = 0U; + itr_rx = 0U; + break; + } + + for (i = HW_ATL2_RINGS_MAX; i--;) { + hw_atl2_reg_tx_intr_moder_ctrl_set(self, itr_tx, i); + hw_atl_reg_rx_intr_moder_ctrl_set(self, itr_rx, i); + } + + return aq_hw_err_from_flags(self); +} + +static int hw_atl2_hw_stop(struct aq_hw_s *self) +{ + hw_atl_b0_hw_irq_disable(self, HW_ATL2_INT_MASK); + + return 0; +} + +static struct aq_stats_s *hw_atl2_utils_get_hw_stats(struct aq_hw_s *self) +{ + return &self->curr_stats; +} + +static int hw_atl2_hw_vlan_set(struct aq_hw_s *self, + struct aq_rx_filter_vlan *aq_vlans) +{ + struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv; + u32 queue; + u8 index; + int i; + + hw_atl_rpf_vlan_prom_mode_en_set(self, 1U); + + for (i = 0; i < HW_ATL_VLAN_MAX_FILTERS; i++) { + queue = HW_ATL2_ACTION_ASSIGN_QUEUE(aq_vlans[i].queue); + + hw_atl_rpf_vlan_flr_en_set(self, 0U, i); + hw_atl_rpf_vlan_rxq_en_flr_set(self, 0U, i); + index = priv->art_base_index + HW_ATL2_RPF_VLAN_USER_INDEX + i; + hw_atl2_act_rslvr_table_set(self, index, 0, 0, + HW_ATL2_ACTION_DISABLE); + if (aq_vlans[i].enable) { + hw_atl_rpf_vlan_id_flr_set(self, + aq_vlans[i].vlan_id, i); + hw_atl_rpf_vlan_flr_act_set(self, 1U, i); + hw_atl_rpf_vlan_flr_en_set(self, 1U, i); + + if (aq_vlans[i].queue != 0xFF) { + hw_atl_rpf_vlan_rxq_flr_set(self, + aq_vlans[i].queue, + i); + hw_atl_rpf_vlan_rxq_en_flr_set(self, 1U, i); + + hw_atl2_rpf_vlan_flr_tag_set(self, i + 2, i); + + index = priv->art_base_index + + HW_ATL2_RPF_VLAN_USER_INDEX + i; + hw_atl2_act_rslvr_table_set(self, index, + (i + 2) << HW_ATL2_RPF_TAG_VLAN_OFFSET, + HW_ATL2_RPF_TAG_VLAN_MASK, queue); + } else { + hw_atl2_rpf_vlan_flr_tag_set(self, 1, i); + } + } + } + + return aq_hw_err_from_flags(self); +} + +static int hw_atl2_hw_vlan_ctrl(struct aq_hw_s *self, bool enable) +{ + /* set promisc in case of disabing the vlan filter */ + hw_atl_rpf_vlan_prom_mode_en_set(self, !enable); + hw_atl2_hw_new_rx_filter_vlan_promisc(self, !enable); + + return aq_hw_err_from_flags(self); +} + +const struct aq_hw_ops hw_atl2_ops = { + .hw_soft_reset = hw_atl2_utils_soft_reset, + .hw_prepare = hw_atl2_utils_initfw, + .hw_set_mac_address = hw_atl_b0_hw_mac_addr_set, + .hw_init = hw_atl2_hw_init, + .hw_reset = hw_atl2_hw_reset, + .hw_start = hw_atl_b0_hw_start, + .hw_ring_tx_start = hw_atl_b0_hw_ring_tx_start, + .hw_ring_tx_stop = hw_atl_b0_hw_ring_tx_stop, + .hw_ring_rx_start = hw_atl_b0_hw_ring_rx_start, + .hw_ring_rx_stop = hw_atl_b0_hw_ring_rx_stop, + .hw_stop = hw_atl2_hw_stop, + + .hw_ring_tx_xmit = hw_atl_b0_hw_ring_tx_xmit, + .hw_ring_tx_head_update = hw_atl_b0_hw_ring_tx_head_update, + + .hw_ring_rx_receive = hw_atl_b0_hw_ring_rx_receive, + .hw_ring_rx_fill = hw_atl_b0_hw_ring_rx_fill, + + .hw_irq_enable = hw_atl_b0_hw_irq_enable, + .hw_irq_disable = hw_atl_b0_hw_irq_disable, + .hw_irq_read = hw_atl_b0_hw_irq_read, + + .hw_ring_rx_init = hw_atl2_hw_ring_rx_init, + .hw_ring_tx_init = hw_atl2_hw_ring_tx_init, + .hw_packet_filter_set = hw_atl2_hw_packet_filter_set, + .hw_filter_vlan_set = hw_atl2_hw_vlan_set, + .hw_filter_vlan_ctrl = hw_atl2_hw_vlan_ctrl, + .hw_multicast_list_set = hw_atl2_hw_multicast_list_set, + .hw_interrupt_moderation_set = hw_atl2_hw_interrupt_moderation_set, + .hw_rss_set = hw_atl2_hw_rss_set, + .hw_rss_hash_set = hw_atl_b0_hw_rss_hash_set, + .hw_tc_rate_limit_set = hw_atl2_hw_init_tx_tc_rate_limit, + .hw_get_hw_stats = hw_atl2_utils_get_hw_stats, + .hw_get_fw_version = hw_atl2_utils_get_fw_version, + .hw_set_offload = hw_atl_b0_hw_offload_set, +}; diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.h new file mode 100644 index 000000000000..de8723f1c28a --- /dev/null +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Atlantic Network Driver + * Copyright (C) 2020 Marvell International Ltd. + */ + +#ifndef HW_ATL2_H +#define HW_ATL2_H + +#include "aq_common.h" + +extern const struct aq_hw_caps_s hw_atl2_caps_aqc113; +extern const struct aq_hw_ops hw_atl2_ops; + +#endif /* HW_ATL2_H */ diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h new file mode 100644 index 000000000000..5a89bb8722f9 --- /dev/null +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Atlantic Network Driver + * Copyright (C) 2020 Marvell International Ltd. + */ + +#ifndef HW_ATL2_INTERNAL_H +#define HW_ATL2_INTERNAL_H + +#include "hw_atl2_utils.h" + +#define HW_ATL2_MTU_JUMBO 16352U +#define HW_ATL2_MTU 1514U + +#define HW_ATL2_TX_RINGS 4U +#define HW_ATL2_RX_RINGS 4U + +#define HW_ATL2_RINGS_MAX 32U +#define HW_ATL2_TXD_SIZE (16U) +#define HW_ATL2_RXD_SIZE (16U) + +#define HW_ATL2_MAC_UC 0U +#define HW_ATL2_MAC_MIN 1U +#define HW_ATL2_MAC_MAX 38U + +/* interrupts */ +#define HW_ATL2_ERR_INT 8U +#define HW_ATL2_INT_MASK (0xFFFFFFFFU) + +#define HW_ATL2_TXBUF_MAX 128U +#define HW_ATL2_RXBUF_MAX 192U + +#define HW_ATL2_RSS_REDIRECTION_MAX 64U + +#define HW_ATL2_TC_MAX 8U +#define HW_ATL2_RSS_MAX 8U + +#define HW_ATL2_INTR_MODER_MAX 0x1FF +#define HW_ATL2_INTR_MODER_MIN 0xFF + +#define HW_ATL2_MIN_RXD \ + (ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_RXD_MULTIPLE)) +#define HW_ATL2_MIN_TXD \ + (ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_TXD_MULTIPLE)) + +#define HW_ATL2_MAX_RXD 8184U +#define HW_ATL2_MAX_TXD 8184U + +#define HW_ATL2_FW_SM_ACT_RSLVR 0x3U + +#define HW_ATL2_RPF_TAG_UC_OFFSET 0x0 +#define HW_ATL2_RPF_TAG_ALLMC_OFFSET 0x6 +#define HW_ATL2_RPF_TAG_ET_OFFSET 0x7 +#define HW_ATL2_RPF_TAG_VLAN_OFFSET 0xA +#define HW_ATL2_RPF_TAG_UNTAG_OFFSET 0xE +#define HW_ATL2_RPF_TAG_L3_V4_OFFSET 0xF +#define HW_ATL2_RPF_TAG_L3_V6_OFFSET 0x12 +#define HW_ATL2_RPF_TAG_L4_OFFSET 0x15 +#define HW_ATL2_RPF_TAG_L4_FLEX_OFFSET 0x18 +#define HW_ATL2_RPF_TAG_FLEX_OFFSET 0x1B +#define HW_ATL2_RPF_TAG_PCP_OFFSET 0x1D + +#define HW_ATL2_RPF_TAG_UC_MASK (0x0000003F << HW_ATL2_RPF_TAG_UC_OFFSET) +#define HW_ATL2_RPF_TAG_ALLMC_MASK (0x00000001 << HW_ATL2_RPF_TAG_ALLMC_OFFSET) +#define HW_ATL2_RPF_TAG_UNTAG_MASK (0x00000001 << HW_ATL2_RPF_TAG_UNTAG_OFFSET) +#define HW_ATL2_RPF_TAG_VLAN_MASK (0x0000000F << HW_ATL2_RPF_TAG_VLAN_OFFSET) +#define HW_ATL2_RPF_TAG_ET_MASK (0x00000007 << HW_ATL2_RPF_TAG_ET_OFFSET) +#define HW_ATL2_RPF_TAG_L3_V4_MASK (0x00000007 << HW_ATL2_RPF_TAG_L3_V4_OFFSET) +#define HW_ATL2_RPF_TAG_L3_V6_MASK (0x00000007 << HW_ATL2_RPF_TAG_L3_V6_OFFSET) +#define HW_ATL2_RPF_TAG_L4_MASK (0x00000007 << HW_ATL2_RPF_TAG_L4_OFFSET) +#define HW_ATL2_RPF_TAG_PCP_MASK (0x00000007 << HW_ATL2_RPF_TAG_PCP_OFFSET) + +#define HW_ATL2_RPF_TAG_BASE_UC BIT(HW_ATL2_RPF_TAG_UC_OFFSET) +#define HW_ATL2_RPF_TAG_BASE_ALLMC BIT(HW_ATL2_RPF_TAG_ALLMC_OFFSET) +#define HW_ATL2_RPF_TAG_BASE_UNTAG BIT(HW_ATL2_RPF_TAG_UNTAG_OFFSET) +#define HW_ATL2_RPF_TAG_BASE_VLAN BIT(HW_ATL2_RPF_TAG_VLAN_OFFSET) + +enum HW_ATL2_RPF_ART_INDEX { + HW_ATL2_RPF_L2_PROMISC_OFF_INDEX, + HW_ATL2_RPF_VLAN_PROMISC_OFF_INDEX, + HW_ATL2_RPF_L3L4_USER_INDEX = 8, + HW_ATL2_RPF_ET_PCP_USER_INDEX = HW_ATL2_RPF_L3L4_USER_INDEX + 16, + HW_ATL2_RPF_VLAN_USER_INDEX = HW_ATL2_RPF_ET_PCP_USER_INDEX + 16, + HW_ATL2_RPF_PCP_TO_TC_INDEX = HW_ATL2_RPF_VLAN_USER_INDEX + + HW_ATL_VLAN_MAX_FILTERS, +}; + +#define HW_ATL2_ACTION(ACTION, RSS, INDEX, VALID) \ + ((((ACTION) & 0x3U) << 8) | \ + (((RSS) & 0x1U) << 7) | \ + (((INDEX) & 0x3FU) << 2) | \ + (((VALID) & 0x1U) << 0)) + +#define HW_ATL2_ACTION_DROP HW_ATL2_ACTION(0, 0, 0, 1) +#define HW_ATL2_ACTION_DISABLE HW_ATL2_ACTION(0, 0, 0, 0) +#define HW_ATL2_ACTION_ASSIGN_QUEUE(QUEUE) HW_ATL2_ACTION(1, 0, (QUEUE), 1) +#define HW_ATL2_ACTION_ASSIGN_TC(TC) HW_ATL2_ACTION(1, 1, (TC), 1) + +enum HW_ATL2_RPF_RSS_HASH_TYPE { + HW_ATL2_RPF_RSS_HASH_TYPE_NONE = 0, + HW_ATL2_RPF_RSS_HASH_TYPE_IPV4 = BIT(0), + HW_ATL2_RPF_RSS_HASH_TYPE_IPV4_TCP = BIT(1), + HW_ATL2_RPF_RSS_HASH_TYPE_IPV4_UDP = BIT(2), + HW_ATL2_RPF_RSS_HASH_TYPE_IPV6 = BIT(3), + HW_ATL2_RPF_RSS_HASH_TYPE_IPV6_TCP = BIT(4), + HW_ATL2_RPF_RSS_HASH_TYPE_IPV6_UDP = BIT(5), + HW_ATL2_RPF_RSS_HASH_TYPE_IPV6_EX = BIT(6), + HW_ATL2_RPF_RSS_HASH_TYPE_IPV6_EX_TCP = BIT(7), + HW_ATL2_RPF_RSS_HASH_TYPE_IPV6_EX_UDP = BIT(8), + HW_ATL2_RPF_RSS_HASH_TYPE_ALL = HW_ATL2_RPF_RSS_HASH_TYPE_IPV4 | + HW_ATL2_RPF_RSS_HASH_TYPE_IPV4_TCP | + HW_ATL2_RPF_RSS_HASH_TYPE_IPV4_UDP | + HW_ATL2_RPF_RSS_HASH_TYPE_IPV6 | + HW_ATL2_RPF_RSS_HASH_TYPE_IPV6_TCP | + HW_ATL2_RPF_RSS_HASH_TYPE_IPV6_UDP | + HW_ATL2_RPF_RSS_HASH_TYPE_IPV6_EX | + HW_ATL2_RPF_RSS_HASH_TYPE_IPV6_EX_TCP | + HW_ATL2_RPF_RSS_HASH_TYPE_IPV6_EX_UDP, +}; + +#define HW_ATL_MCAST_FLT_ANY_TO_HOST 0x00010FFFU + +struct hw_atl2_priv { + struct statistics_s last_stats; + unsigned int art_base_index; +}; + +#endif /* HW_ATL2_INTERNAL_H */ diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.c new file mode 100644 index 000000000000..cd954b11d24a --- /dev/null +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.c @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Atlantic Network Driver + * Copyright (C) 2020 Marvell International Ltd. + */ + +#include "hw_atl2_llh.h" +#include "hw_atl2_llh_internal.h" +#include "aq_hw_utils.h" + +void hw_atl2_rpf_redirection_table2_select_set(struct aq_hw_s *aq_hw, + u32 select) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_ADR, + HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_MSK, + HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_SHIFT, select); +} + +void hw_atl2_rpf_rss_hash_type_set(struct aq_hw_s *aq_hw, u32 rss_hash_type) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_ADR, + HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_MSK, + HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_SHIFT, + rss_hash_type); +} + +/* rpf */ + +void hw_atl2_rpf_new_enable_set(struct aq_hw_s *aq_hw, u32 enable) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_NEW_EN_ADR, + HW_ATL2_RPF_NEW_EN_MSK, + HW_ATL2_RPF_NEW_EN_SHIFT, + enable); +} + +void hw_atl2_rpfl2_uc_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag, u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPFL2UC_TAG_ADR(filter), + HW_ATL2_RPFL2UC_TAG_MSK, + HW_ATL2_RPFL2UC_TAG_SHIFT, + tag); +} + +void hw_atl2_rpfl2_bc_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_L2_BC_TAG_ADR, + HW_ATL2_RPF_L2_BC_TAG_MSK, + HW_ATL2_RPF_L2_BC_TAG_SHIFT, + tag); +} + +void hw_atl2_new_rpf_rss_redir_set(struct aq_hw_s *aq_hw, u32 tc, u32 index, + u32 queue) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_RSS_REDIR_ADR(tc, index), + HW_ATL2_RPF_RSS_REDIR_MSK(tc), + HW_ATL2_RPF_RSS_REDIR_SHIFT(tc), + queue); +} + +void hw_atl2_rpf_vlan_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag, u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_VL_TAG_ADR(filter), + HW_ATL2_RPF_VL_TAG_MSK, + HW_ATL2_RPF_VL_TAG_SHIFT, + tag); +} + +/* TX */ + +void hw_atl2_tpb_tx_tc_q_rand_map_en_set(struct aq_hw_s *aq_hw, + const u32 tc_q_rand_map_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_ADR, + HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_MSK, + HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_SHIFT, + tc_q_rand_map_en); +} + +void hw_atl2_tpb_tx_buf_clk_gate_en_set(struct aq_hw_s *aq_hw, u32 clk_gate_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_ADR, + HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_MSK, + HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_SHIFT, + clk_gate_en); +} + +void hw_atl2_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, + u32 tx_intr_moderation_ctl, + u32 queue) +{ + aq_hw_write_reg(aq_hw, HW_ATL2_TX_INTR_MODERATION_CTL_ADR(queue), + tx_intr_moderation_ctl); +} + +void hw_atl2_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw, + const u32 data_arb_mode) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPS_DATA_TC_ARB_MODE_ADR, + HW_ATL2_TPS_DATA_TC_ARB_MODE_MSK, + HW_ATL2_TPS_DATA_TC_ARB_MODE_SHIFT, + data_arb_mode); +} + +void hw_atl2_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw, + const u32 tc, + const u32 max_credit) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPS_DATA_TCTCREDIT_MAX_ADR(tc), + HW_ATL2_TPS_DATA_TCTCREDIT_MAX_MSK, + HW_ATL2_TPS_DATA_TCTCREDIT_MAX_SHIFT, + max_credit); +} + +void hw_atl2_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw, + const u32 tc, + const u32 weight) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPS_DATA_TCTWEIGHT_ADR(tc), + HW_ATL2_TPS_DATA_TCTWEIGHT_MSK, + HW_ATL2_TPS_DATA_TCTWEIGHT_SHIFT, + weight); +} + +u32 hw_atl2_get_hw_version(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL2_FPGA_VER_ADR); +} + +void hw_atl2_init_launchtime(struct aq_hw_s *aq_hw) +{ + u32 hw_ver = hw_atl2_get_hw_version(aq_hw); + + aq_hw_write_reg_bit(aq_hw, HW_ATL2_LT_CTRL_ADR, + HW_ATL2_LT_CTRL_CLK_RATIO_MSK, + HW_ATL2_LT_CTRL_CLK_RATIO_SHIFT, + hw_ver < HW_ATL2_FPGA_VER_U32(1, 0, 0, 0) ? + HW_ATL2_LT_CTRL_CLK_RATIO_FULL_SPEED : + hw_ver >= HW_ATL2_FPGA_VER_U32(1, 0, 85, 2) ? + HW_ATL2_LT_CTRL_CLK_RATIO_HALF_SPEED : + HW_ATL2_LT_CTRL_CLK_RATIO_QUATER_SPEED); +} + +/* set action resolver record */ +void hw_atl2_rpf_act_rslvr_record_set(struct aq_hw_s *aq_hw, u8 location, + u32 tag, u32 mask, u32 action) +{ + aq_hw_write_reg(aq_hw, + HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_ADR(location), + tag); + aq_hw_write_reg(aq_hw, + HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_ADR(location), + mask); + aq_hw_write_reg(aq_hw, + HW_ATL2_RPF_ACT_RSLVR_ACTN_ADR(location), + action); +} + +void hw_atl2_rpf_act_rslvr_section_en_set(struct aq_hw_s *aq_hw, u32 sections) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_REC_TAB_EN_ADR, + HW_ATL2_RPF_REC_TAB_EN_MSK, + HW_ATL2_RPF_REC_TAB_EN_SHIFT, + sections); +} + +void hw_atl2_mif_shared_buf_get(struct aq_hw_s *aq_hw, int offset, u32 *data, + int len) +{ + int j = 0; + int i; + + for (i = offset; i < offset + len; i++, j++) + data[j] = aq_hw_read_reg(aq_hw, + HW_ATL2_MIF_SHARED_BUFFER_IN_ADR(i)); +} + +void hw_atl2_mif_shared_buf_write(struct aq_hw_s *aq_hw, int offset, u32 *data, + int len) +{ + int j = 0; + int i; + + for (i = offset; i < offset + len; i++, j++) + aq_hw_write_reg(aq_hw, HW_ATL2_MIF_SHARED_BUFFER_IN_ADR(i), + data[j]); +} + +void hw_atl2_mif_shared_buf_read(struct aq_hw_s *aq_hw, int offset, u32 *data, + int len) +{ + int j = 0; + int i; + + for (i = offset; i < offset + len; i++, j++) + data[j] = aq_hw_read_reg(aq_hw, + HW_ATL2_MIF_SHARED_BUFFER_OUT_ADR(i)); +} + +void hw_atl2_mif_host_finished_write_set(struct aq_hw_s *aq_hw, u32 finish) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_MIF_HOST_FINISHED_WRITE_ADR, + HW_ATL2_MIF_HOST_FINISHED_WRITE_MSK, + HW_ATL2_MIF_HOST_FINISHED_WRITE_SHIFT, + finish); +} + +u32 hw_atl2_mif_mcp_finished_read_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL2_MIF_MCP_FINISHED_READ_ADR, + HW_ATL2_MIF_MCP_FINISHED_READ_MSK, + HW_ATL2_MIF_MCP_FINISHED_READ_SHIFT); +} + +u32 hw_atl2_mif_mcp_boot_reg_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL2_MIF_BOOT_REG_ADR); +} + +void hw_atl2_mif_mcp_boot_reg_set(struct aq_hw_s *aq_hw, u32 val) +{ + return aq_hw_write_reg(aq_hw, HW_ATL2_MIF_BOOT_REG_ADR, val); +} + +u32 hw_atl2_mif_host_req_int_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL2_MCP_HOST_REQ_INT_ADR); +} + +void hw_atl2_mif_host_req_int_clr(struct aq_hw_s *aq_hw, u32 val) +{ + return aq_hw_write_reg(aq_hw, HW_ATL2_MCP_HOST_REQ_INT_CLR_ADR, + val); +} diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.h new file mode 100644 index 000000000000..98c7a4621297 --- /dev/null +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Atlantic Network Driver + * Copyright (C) 2020 Marvell International Ltd. + */ + +#ifndef HW_ATL2_LLH_H +#define HW_ATL2_LLH_H + +#include <linux/types.h> + +struct aq_hw_s; + +/* Set TX Interrupt Moderation Control Register */ +void hw_atl2_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, + u32 tx_intr_moderation_ctl, + u32 queue); + +/* Set Redirection Table 2 Select */ +void hw_atl2_rpf_redirection_table2_select_set(struct aq_hw_s *aq_hw, + u32 select); + +/** Set RSS HASH type */ +void hw_atl2_rpf_rss_hash_type_set(struct aq_hw_s *aq_hw, u32 rss_hash_type); + +/* set new RPF enable */ +void hw_atl2_rpf_new_enable_set(struct aq_hw_s *aq_hw, u32 enable); + +/* set l2 unicast filter tag */ +void hw_atl2_rpfl2_uc_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag, u32 filter); + +/* set l2 broadcast filter tag */ +void hw_atl2_rpfl2_bc_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag); + +/* set new rss redirection table */ +void hw_atl2_new_rpf_rss_redir_set(struct aq_hw_s *aq_hw, u32 tc, u32 index, + u32 queue); + +/* Set VLAN filter tag */ +void hw_atl2_rpf_vlan_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag, u32 filter); + +/* set tx random TC-queue mapping enable bit */ +void hw_atl2_tpb_tx_tc_q_rand_map_en_set(struct aq_hw_s *aq_hw, + const u32 tc_q_rand_map_en); + +/* set tx buffer clock gate enable */ +void hw_atl2_tpb_tx_buf_clk_gate_en_set(struct aq_hw_s *aq_hw, u32 clk_gate_en); + +void hw_atl2_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw, + const u32 data_arb_mode); + +/* set tx packet scheduler tc data max credit */ +void hw_atl2_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw, + const u32 tc, + const u32 max_credit); + +/* set tx packet scheduler tc data weight */ +void hw_atl2_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw, + const u32 tc, + const u32 weight); + +u32 hw_atl2_get_hw_version(struct aq_hw_s *aq_hw); + +void hw_atl2_init_launchtime(struct aq_hw_s *aq_hw); + +/* set action resolver record */ +void hw_atl2_rpf_act_rslvr_record_set(struct aq_hw_s *aq_hw, u8 location, + u32 tag, u32 mask, u32 action); + +/* set enable action resolver section */ +void hw_atl2_rpf_act_rslvr_section_en_set(struct aq_hw_s *aq_hw, u32 sections); + +/* get data from firmware shared input buffer */ +void hw_atl2_mif_shared_buf_get(struct aq_hw_s *aq_hw, int offset, u32 *data, + int len); + +/* set data into firmware shared input buffer */ +void hw_atl2_mif_shared_buf_write(struct aq_hw_s *aq_hw, int offset, u32 *data, + int len); + +/* get data from firmware shared output buffer */ +void hw_atl2_mif_shared_buf_read(struct aq_hw_s *aq_hw, int offset, u32 *data, + int len); + +/* set host finished write shared buffer indication */ +void hw_atl2_mif_host_finished_write_set(struct aq_hw_s *aq_hw, u32 finish); + +/* get mcp finished read shared buffer indication */ +u32 hw_atl2_mif_mcp_finished_read_get(struct aq_hw_s *aq_hw); + +/* get mcp boot register */ +u32 hw_atl2_mif_mcp_boot_reg_get(struct aq_hw_s *aq_hw); + +/* set mcp boot register */ +void hw_atl2_mif_mcp_boot_reg_set(struct aq_hw_s *aq_hw, u32 val); + +/* get host interrupt request */ +u32 hw_atl2_mif_host_req_int_get(struct aq_hw_s *aq_hw); + +/* clear host interrupt request */ +void hw_atl2_mif_host_req_int_clr(struct aq_hw_s *aq_hw, u32 val); + +#endif /* HW_ATL2_LLH_H */ diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh_internal.h new file mode 100644 index 000000000000..e34c5cda061e --- /dev/null +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh_internal.h @@ -0,0 +1,391 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Atlantic Network Driver + * Copyright (C) 2020 Marvell International Ltd. + */ + +#ifndef HW_ATL2_LLH_INTERNAL_H +#define HW_ATL2_LLH_INTERNAL_H + +/* RX pif_rpf_redir_2_en_i Bitfield Definitions + * PORT="pif_rpf_redir_2_en_i" + */ +#define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_ADR 0x000054C8 +#define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_MSK 0x00001000 +#define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_MSKN 0xFFFFEFFF +#define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_SHIFT 12 +#define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_WIDTH 1 +#define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_DEFAULT 0x0 + +/* RX pif_rpf_rss_hash_type_i Bitfield Definitions + */ +#define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_ADR 0x000054C8 +#define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_MSK 0x000001FF +#define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_MSKN 0xFFFFFE00 +#define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_SHIFT 0 +#define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_WIDTH 9 + +/* rx rpf_new_rpf_en bitfield definitions + * preprocessor definitions for the bitfield "rpf_new_rpf_en_i". + * port="pif_rpf_new_rpf_en_i + */ + +/* register address for bitfield rpf_new_rpf_en */ +#define HW_ATL2_RPF_NEW_EN_ADR 0x00005104 +/* bitmask for bitfield rpf_new_rpf_en */ +#define HW_ATL2_RPF_NEW_EN_MSK 0x00000800 +/* inverted bitmask for bitfield rpf_new_rpf_en */ +#define HW_ATL2_RPF_NEW_EN_MSKN 0xfffff7ff +/* lower bit position of bitfield rpf_new_rpf_en */ +#define HW_ATL2_RPF_NEW_EN_SHIFT 11 +/* width of bitfield rpf_new_rpf_en */ +#define HW_ATL2_RPF_NEW_EN_WIDTH 1 +/* default value of bitfield rpf_new_rpf_en */ +#define HW_ATL2_RPF_NEW_EN_DEFAULT 0x0 + +/* rx l2_uc_req_tag0{f}[5:0] bitfield definitions + * preprocessor definitions for the bitfield "l2_uc_req_tag0{f}[7:0]". + * parameter: filter {f} | stride size 0x8 | range [0, 37] + * port="pif_rpf_l2_uc_req_tag0[5:0]" + */ + +/* register address for bitfield l2_uc_req_tag0{f}[2:0] */ +#define HW_ATL2_RPFL2UC_TAG_ADR(filter) (0x00005114 + (filter) * 0x8) +/* bitmask for bitfield l2_uc_req_tag0{f}[2:0] */ +#define HW_ATL2_RPFL2UC_TAG_MSK 0x0FC00000 +/* inverted bitmask for bitfield l2_uc_req_tag0{f}[2:0] */ +#define HW_ATL2_RPFL2UC_TAG_MSKN 0xF03FFFFF +/* lower bit position of bitfield l2_uc_req_tag0{f}[2:0] */ +#define HW_ATL2_RPFL2UC_TAG_SHIFT 22 +/* width of bitfield l2_uc_req_tag0{f}[2:0] */ +#define HW_ATL2_RPFL2UC_TAG_WIDTH 6 +/* default value of bitfield l2_uc_req_tag0{f}[2:0] */ +#define HW_ATL2_RPFL2UC_TAG_DEFAULT 0x0 + +/* rpf_l2_bc_req_tag[5:0] bitfield definitions + * preprocessor definitions for the bitfield "rpf_l2_bc_req_tag[5:0]". + * port="pifrpf_l2_bc_req_tag_i[5:0]" + */ + +/* register address for bitfield rpf_l2_bc_req_tag */ +#define HW_ATL2_RPF_L2_BC_TAG_ADR 0x000050F0 +/* bitmask for bitfield rpf_l2_bc_req_tag */ +#define HW_ATL2_RPF_L2_BC_TAG_MSK 0x0000003F +/* inverted bitmask for bitfield rpf_l2_bc_req_tag */ +#define HW_ATL2_RPF_L2_BC_TAG_MSKN 0xffffffc0 +/* lower bit position of bitfield rpf_l2_bc_req_tag */ +#define HW_ATL2_RPF_L2_BC_TAG_SHIFT 0 +/* width of bitfield rpf_l2_bc_req_tag */ +#define HW_ATL2_RPF_L2_BC_TAG_WIDTH 6 +/* default value of bitfield rpf_l2_bc_req_tag */ +#define HW_ATL2_RPF_L2_BC_TAG_DEFAULT 0x0 + +/* rx rpf_rss_red1_data_[4:0] bitfield definitions + * preprocessor definitions for the bitfield "rpf_rss_red1_data[4:0]". + * port="pif_rpf_rss_red1_data_i[4:0]" + */ + +/* register address for bitfield rpf_rss_red1_data[4:0] */ +#define HW_ATL2_RPF_RSS_REDIR_ADR(TC, INDEX) (0x00006200 + \ + (0x100 * !!((TC) > 3)) + (INDEX) * 4) +/* bitmask for bitfield rpf_rss_red1_data[4:0] */ +#define HW_ATL2_RPF_RSS_REDIR_MSK(TC) (0x00000001F << (5 * ((TC) % 4))) +/* lower bit position of bitfield rpf_rss_red1_data[4:0] */ +#define HW_ATL2_RPF_RSS_REDIR_SHIFT(TC) (5 * ((TC) % 4)) +/* width of bitfield rpf_rss_red1_data[4:0] */ +#define HW_ATL2_RPF_RSS_REDIR_WIDTH 5 +/* default value of bitfield rpf_rss_red1_data[4:0] */ +#define HW_ATL2_RPF_RSS_REDIR_DEFAULT 0x0 + +/* rx vlan_req_tag0{f}[3:0] bitfield definitions + * preprocessor definitions for the bitfield "vlan_req_tag0{f}[3:0]". + * parameter: filter {f} | stride size 0x4 | range [0, 15] + * port="pif_rpf_vlan_req_tag0[3:0]" + */ + +/* register address for bitfield vlan_req_tag0{f}[3:0] */ +#define HW_ATL2_RPF_VL_TAG_ADR(filter) (0x00005290 + (filter) * 0x4) +/* bitmask for bitfield vlan_req_tag0{f}[3:0] */ +#define HW_ATL2_RPF_VL_TAG_MSK 0x0000F000 +/* inverted bitmask for bitfield vlan_req_tag0{f}[3:0] */ +#define HW_ATL2_RPF_VL_TAG_MSKN 0xFFFF0FFF +/* lower bit position of bitfield vlan_req_tag0{f}[3:0] */ +#define HW_ATL2_RPF_VL_TAG_SHIFT 12 +/* width of bitfield vlan_req_tag0{f}[3:0] */ +#define HW_ATL2_RPF_VL_TAG_WIDTH 4 +/* default value of bitfield vlan_req_tag0{f}[3:0] */ +#define HW_ATL2_RPF_VL_TAG_DEFAULT 0x0 + +/* RX rx_q{Q}_tc_map[2:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "rx_q{Q}_tc_map[2:0]". + * Parameter: Queue {Q} | bit-level stride | range [0, 31] + * PORT="pif_rx_q0_tc_map_i[2:0]" + */ + +/* Register address for bitfield rx_q{Q}_tc_map[2:0] */ +#define HW_ATL2_RX_Q_TC_MAP_ADR(queue) \ + (((queue) < 32) ? 0x00005900 + ((queue) / 8) * 4 : 0) +/* Lower bit position of bitfield rx_q{Q}_tc_map[2:0] */ +#define HW_ATL2_RX_Q_TC_MAP_SHIFT(queue) \ + (((queue) < 32) ? ((queue) * 4) % 32 : 0) +/* Width of bitfield rx_q{Q}_tc_map[2:0] */ +#define HW_ATL2_RX_Q_TC_MAP_WIDTH 3 +/* Default value of bitfield rx_q{Q}_tc_map[2:0] */ +#define HW_ATL2_RX_Q_TC_MAP_DEFAULT 0x0 + +/* tx tx_tc_q_rand_map_en bitfield definitions + * preprocessor definitions for the bitfield "tx_tc_q_rand_map_en". + * port="pif_tpb_tx_tc_q_rand_map_en_i" + */ + +/* register address for bitfield tx_tc_q_rand_map_en */ +#define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_ADR 0x00007900 +/* bitmask for bitfield tx_tc_q_rand_map_en */ +#define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_MSK 0x00000200 +/* inverted bitmask for bitfield tx_tc_q_rand_map_en */ +#define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_MSKN 0xFFFFFDFF +/* lower bit position of bitfield tx_tc_q_rand_map_en */ +#define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_SHIFT 9 +/* width of bitfield tx_tc_q_rand_map_en */ +#define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_WIDTH 1 +/* default value of bitfield tx_tc_q_rand_map_en */ +#define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_DEFAULT 0x0 + +/* tx tx_buffer_clk_gate_en bitfield definitions + * preprocessor definitions for the bitfield "tx_buffer_clk_gate_en". + * port="pif_tpb_tx_buffer_clk_gate_en_i" + */ + +/* register address for bitfield tx_buffer_clk_gate_en */ +#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_ADR 0x00007900 +/* bitmask for bitfield tx_buffer_clk_gate_en */ +#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_MSK 0x00000020 +/* inverted bitmask for bitfield tx_buffer_clk_gate_en */ +#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_MSKN 0xffffffdf +/* lower bit position of bitfield tx_buffer_clk_gate_en */ +#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_SHIFT 5 +/* width of bitfield tx_buffer_clk_gate_en */ +#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_WIDTH 1 +/* default value of bitfield tx_buffer_clk_gate_en */ +#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_DEFAULT 0x0 + +/* tx tx_q_tc_map{q} bitfield definitions + * preprocessor definitions for the bitfield "tx_q_tc_map{q}". + * parameter: queue {q} | bit-level stride | range [0, 31] + * port="pif_tpb_tx_q_tc_map0_i[2:0]" + */ + +/* register address for bitfield tx_q_tc_map{q} */ +#define HW_ATL2_TX_Q_TC_MAP_ADR(queue) \ + (((queue) < 32) ? 0x0000799C + ((queue) / 4) * 4 : 0) +/* lower bit position of bitfield tx_q_tc_map{q} */ +#define HW_ATL2_TX_Q_TC_MAP_SHIFT(queue) \ + (((queue) < 32) ? ((queue) * 8) % 32 : 0) +/* width of bitfield tx_q_tc_map{q} */ +#define HW_ATL2_TX_Q_TC_MAP_WIDTH 3 +/* default value of bitfield tx_q_tc_map{q} */ +#define HW_ATL2_TX_Q_TC_MAP_DEFAULT 0x0 + +/* tx data_tc_arb_mode bitfield definitions + * preprocessor definitions for the bitfield "data_tc_arb_mode". + * port="pif_tps_data_tc_arb_mode_i" + */ + +/* register address for bitfield data_tc_arb_mode */ +#define HW_ATL2_TPS_DATA_TC_ARB_MODE_ADR 0x00007100 +/* bitmask for bitfield data_tc_arb_mode */ +#define HW_ATL2_TPS_DATA_TC_ARB_MODE_MSK 0x00000003 +/* inverted bitmask for bitfield data_tc_arb_mode */ +#define HW_ATL2_TPS_DATA_TC_ARB_MODE_MSKN 0xfffffffc +/* lower bit position of bitfield data_tc_arb_mode */ +#define HW_ATL2_TPS_DATA_TC_ARB_MODE_SHIFT 0 +/* width of bitfield data_tc_arb_mode */ +#define HW_ATL2_TPS_DATA_TC_ARB_MODE_WIDTH 2 +/* default value of bitfield data_tc_arb_mode */ +#define HW_ATL2_TPS_DATA_TC_ARB_MODE_DEFAULT 0x0 + +/* tx data_tc{t}_credit_max[f:0] bitfield definitions + * preprocessor definitions for the bitfield "data_tc{t}_credit_max[f:0]". + * parameter: tc {t} | stride size 0x4 | range [0, 7] + * port="pif_tps_data_tc0_credit_max_i[15:0]" + */ + +/* register address for bitfield data_tc{t}_credit_max[f:0] */ +#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_ADR(tc) (0x00007110 + (tc) * 0x4) +/* bitmask for bitfield data_tc{t}_credit_max[f:0] */ +#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_MSK 0xffff0000 +/* inverted bitmask for bitfield data_tc{t}_credit_max[f:0] */ +#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_MSKN 0x0000ffff +/* lower bit position of bitfield data_tc{t}_credit_max[f:0] */ +#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_SHIFT 16 +/* width of bitfield data_tc{t}_credit_max[f:0] */ +#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_WIDTH 16 +/* default value of bitfield data_tc{t}_credit_max[f:0] */ +#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_DEFAULT 0x0 + +/* tx data_tc{t}_weight[e:0] bitfield definitions + * preprocessor definitions for the bitfield "data_tc{t}_weight[e:0]". + * parameter: tc {t} | stride size 0x4 | range [0, 7] + * port="pif_tps_data_tc0_weight_i[14:0]" + */ + +/* register address for bitfield data_tc{t}_weight[e:0] */ +#define HW_ATL2_TPS_DATA_TCTWEIGHT_ADR(tc) (0x00007110 + (tc) * 0x4) +/* bitmask for bitfield data_tc{t}_weight[e:0] */ +#define HW_ATL2_TPS_DATA_TCTWEIGHT_MSK 0x00007fff +/* inverted bitmask for bitfield data_tc{t}_weight[e:0] */ +#define HW_ATL2_TPS_DATA_TCTWEIGHT_MSKN 0xffff8000 +/* lower bit position of bitfield data_tc{t}_weight[e:0] */ +#define HW_ATL2_TPS_DATA_TCTWEIGHT_SHIFT 0 +/* width of bitfield data_tc{t}_weight[e:0] */ +#define HW_ATL2_TPS_DATA_TCTWEIGHT_WIDTH 15 +/* default value of bitfield data_tc{t}_weight[e:0] */ +#define HW_ATL2_TPS_DATA_TCTWEIGHT_DEFAULT 0x0 + +/* tx interrupt moderation control register definitions + * Preprocessor definitions for TX Interrupt Moderation Control Register + * Base Address: 0x00007c28 + * Parameter: queue {Q} | stride size 0x4 | range [0, 31] + */ + +#define HW_ATL2_TX_INTR_MODERATION_CTL_ADR(queue) (0x00007c28u + (queue) * 0x40) + +/* Launch time control register */ +#define HW_ATL2_LT_CTRL_ADR 0x00007a1c + +#define HW_ATL2_LT_CTRL_AVB_LEN_CMP_TRSHLD_MSK 0xFFFF0000 +#define HW_ATL2_LT_CTRL_AVB_LEN_CMP_TRSHLD_SHIFT 16 + +#define HW_ATL2_LT_CTRL_CLK_RATIO_MSK 0x0000FF00 +#define HW_ATL2_LT_CTRL_CLK_RATIO_SHIFT 8 +#define HW_ATL2_LT_CTRL_CLK_RATIO_QUATER_SPEED 4 +#define HW_ATL2_LT_CTRL_CLK_RATIO_HALF_SPEED 2 +#define HW_ATL2_LT_CTRL_CLK_RATIO_FULL_SPEED 1 + +#define HW_ATL2_LT_CTRL_25G_MODE_SUPPORT_MSK 0x00000008 +#define HW_ATL2_LT_CTRL_25G_MODE_SUPPORT_SHIFT 3 + +#define HW_ATL2_LT_CTRL_LINK_SPEED_MSK 0x00000007 +#define HW_ATL2_LT_CTRL_LINK_SPEED_SHIFT 0 + +/* FPGA VER register */ +#define HW_ATL2_FPGA_VER_ADR 0x000000f4 +#define HW_ATL2_FPGA_VER_U32(mj, mi, bl, rv) \ + ((((mj) & 0xff) << 24) | \ + (((mi) & 0xff) << 16) | \ + (((bl) & 0xff) << 8) | \ + (((rv) & 0xff) << 0)) + +/* ahb_mem_addr{f}[31:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "ahb_mem_addr{f}[31:0]". + * Parameter: filter {f} | stride size 0x10 | range [0, 127] + * PORT="ahb_mem_addr{f}[31:0]" + */ + +/* Register address for bitfield ahb_mem_addr{f}[31:0] */ +#define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_ADR(filter) \ + (0x00014000u + (filter) * 0x10) +/* Bitmask for bitfield ahb_mem_addr{f}[31:0] */ +#define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_MSK 0xFFFFFFFFu +/* Inverted bitmask for bitfield ahb_mem_addr{f}[31:0] */ +#define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_MSKN 0x00000000u +/* Lower bit position of bitfield ahb_mem_addr{f}[31:0] */ +#define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_SHIFT 0 +/* Width of bitfield ahb_mem_addr{f}[31:0] */ +#define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_WIDTH 31 +/* Default value of bitfield ahb_mem_addr{f}[31:0] */ +#define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_DEFAULT 0x0 + +/* Register address for bitfield ahb_mem_addr{f}[31:0] */ +#define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_ADR(filter) \ + (0x00014004u + (filter) * 0x10) +/* Bitmask for bitfield ahb_mem_addr{f}[31:0] */ +#define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_MSK 0xFFFFFFFFu +/* Inverted bitmask for bitfield ahb_mem_addr{f}[31:0] */ +#define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_MSKN 0x00000000u +/* Lower bit position of bitfield ahb_mem_addr{f}[31:0] */ +#define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_SHIFT 0 +/* Width of bitfield ahb_mem_addr{f}[31:0] */ +#define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_WIDTH 31 +/* Default value of bitfield ahb_mem_addr{f}[31:0] */ +#define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_DEFAULT 0x0 + +/* Register address for bitfield ahb_mem_addr{f}[31:0] */ +#define HW_ATL2_RPF_ACT_RSLVR_ACTN_ADR(filter) \ + (0x00014008u + (filter) * 0x10) +/* Bitmask for bitfield ahb_mem_addr{f}[31:0] */ +#define HW_ATL2_RPF_ACT_RSLVR_ACTN_MSK 0x000007FFu +/* Inverted bitmask for bitfield ahb_mem_addr{f}[31:0] */ +#define HW_ATL2_RPF_ACT_RSLVR_ACTN_MSKN 0xFFFFF800u +/* Lower bit position of bitfield ahb_mem_addr{f}[31:0] */ +#define HW_ATL2_RPF_ACT_RSLVR_ACTN_SHIFT 0 +/* Width of bitfield ahb_mem_addr{f}[31:0] */ +#define HW_ATL2_RPF_ACT_RSLVR_ACTN_WIDTH 10 +/* Default value of bitfield ahb_mem_addr{f}[31:0] */ +#define HW_ATL2_RPF_ACT_RSLVR_ACTN_DEFAULT 0x0 + +/* rpf_rec_tab_en[15:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "rpf_rec_tab_en[15:0]". + * PORT="pif_rpf_rec_tab_en[15:0]" + */ +/* Register address for bitfield rpf_rec_tab_en[15:0] */ +#define HW_ATL2_RPF_REC_TAB_EN_ADR 0x00006ff0u +/* Bitmask for bitfield rpf_rec_tab_en[15:0] */ +#define HW_ATL2_RPF_REC_TAB_EN_MSK 0x0000FFFFu +/* Inverted bitmask for bitfield rpf_rec_tab_en[15:0] */ +#define HW_ATL2_RPF_REC_TAB_EN_MSKN 0xFFFF0000u +/* Lower bit position of bitfield rpf_rec_tab_en[15:0] */ +#define HW_ATL2_RPF_REC_TAB_EN_SHIFT 0 +/* Width of bitfield rpf_rec_tab_en[15:0] */ +#define HW_ATL2_RPF_REC_TAB_EN_WIDTH 16 +/* Default value of bitfield rpf_rec_tab_en[15:0] */ +#define HW_ATL2_RPF_REC_TAB_EN_DEFAULT 0x0 + +/* Register address for firmware shared input buffer */ +#define HW_ATL2_MIF_SHARED_BUFFER_IN_ADR(dword) (0x00012000U + (dword) * 0x4U) +/* Register address for firmware shared output buffer */ +#define HW_ATL2_MIF_SHARED_BUFFER_OUT_ADR(dword) (0x00013000U + (dword) * 0x4U) + +/* pif_host_finished_buf_wr_i Bitfield Definitions + * Preprocessor definitions for the bitfield "pif_host_finished_buf_wr_i". + * PORT="pif_host_finished_buf_wr_i" + */ +/* Register address for bitfield rpif_host_finished_buf_wr_i */ +#define HW_ATL2_MIF_HOST_FINISHED_WRITE_ADR 0x00000e00u +/* Bitmask for bitfield pif_host_finished_buf_wr_i */ +#define HW_ATL2_MIF_HOST_FINISHED_WRITE_MSK 0x00000001u +/* Inverted bitmask for bitfield pif_host_finished_buf_wr_i */ +#define HW_ATL2_MIF_HOST_FINISHED_WRITE_MSKN 0xFFFFFFFEu +/* Lower bit position of bitfield pif_host_finished_buf_wr_i */ +#define HW_ATL2_MIF_HOST_FINISHED_WRITE_SHIFT 0 +/* Width of bitfield pif_host_finished_buf_wr_i */ +#define HW_ATL2_MIF_HOST_FINISHED_WRITE_WIDTH 1 +/* Default value of bitfield pif_host_finished_buf_wr_i */ +#define HW_ATL2_MIF_HOST_FINISHED_WRITE_DEFAULT 0x0 + +/* pif_mcp_finished_buf_rd_i Bitfield Definitions + * Preprocessor definitions for the bitfield "pif_mcp_finished_buf_rd_i". + * PORT="pif_mcp_finished_buf_rd_i" + */ +/* Register address for bitfield pif_mcp_finished_buf_rd_i */ +#define HW_ATL2_MIF_MCP_FINISHED_READ_ADR 0x00000e04u +/* Bitmask for bitfield pif_mcp_finished_buf_rd_i */ +#define HW_ATL2_MIF_MCP_FINISHED_READ_MSK 0x00000001u +/* Inverted bitmask for bitfield pif_mcp_finished_buf_rd_i */ +#define HW_ATL2_MIF_MCP_FINISHED_READ_MSKN 0xFFFFFFFEu +/* Lower bit position of bitfield pif_mcp_finished_buf_rd_i */ +#define HW_ATL2_MIF_MCP_FINISHED_READ_SHIFT 0 +/* Width of bitfield pif_mcp_finished_buf_rd_i */ +#define HW_ATL2_MIF_MCP_FINISHED_READ_WIDTH 1 +/* Default value of bitfield pif_mcp_finished_buf_rd_i */ +#define HW_ATL2_MIF_MCP_FINISHED_READ_DEFAULT 0x0 + +/* Register address for bitfield pif_mcp_boot_reg */ +#define HW_ATL2_MIF_BOOT_REG_ADR 0x00003040u + +#define HW_ATL2_MCP_HOST_REQ_INT_READY BIT(0) + +#define HW_ATL2_MCP_HOST_REQ_INT_ADR 0x00000F00u +#define HW_ATL2_MCP_HOST_REQ_INT_SET_ADR 0x00000F04u +#define HW_ATL2_MCP_HOST_REQ_INT_CLR_ADR 0x00000F08u + +#endif /* HW_ATL2_LLH_INTERNAL_H */ diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.c new file mode 100644 index 000000000000..f3766780e975 --- /dev/null +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.c @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Atlantic Network Driver + * Copyright (C) 2020 Marvell International Ltd. + */ + +#include <linux/iopoll.h> + +#include "aq_hw_utils.h" +#include "hw_atl/hw_atl_utils.h" +#include "hw_atl2_utils.h" +#include "hw_atl2_llh.h" +#include "hw_atl2_llh_internal.h" + +#define HW_ATL2_FW_VER_1X 0x01000000U + +#define AQ_A2_BOOT_STARTED BIT(0x18) +#define AQ_A2_CRASH_INIT BIT(0x1B) +#define AQ_A2_BOOT_CODE_FAILED BIT(0x1C) +#define AQ_A2_FW_INIT_FAILED BIT(0x1D) +#define AQ_A2_FW_INIT_COMP_SUCCESS BIT(0x1F) + +#define AQ_A2_FW_BOOT_FAILED_MASK (AQ_A2_CRASH_INIT | \ + AQ_A2_BOOT_CODE_FAILED | \ + AQ_A2_FW_INIT_FAILED) +#define AQ_A2_FW_BOOT_COMPLETE_MASK (AQ_A2_FW_BOOT_FAILED_MASK | \ + AQ_A2_FW_INIT_COMP_SUCCESS) + +#define AQ_A2_FW_BOOT_REQ_REBOOT BIT(0x0) +#define AQ_A2_FW_BOOT_REQ_HOST_BOOT BIT(0x8) +#define AQ_A2_FW_BOOT_REQ_MAC_FAST_BOOT BIT(0xA) +#define AQ_A2_FW_BOOT_REQ_PHY_FAST_BOOT BIT(0xB) + +int hw_atl2_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops) +{ + int err; + + self->fw_ver_actual = hw_atl2_utils_get_fw_version(self); + + if (hw_atl_utils_ver_match(HW_ATL2_FW_VER_1X, + self->fw_ver_actual) == 0) { + *fw_ops = &aq_a2_fw_ops; + } else { + aq_pr_err("Bad FW version detected: %x, but continue\n", + self->fw_ver_actual); + *fw_ops = &aq_a2_fw_ops; + } + aq_pr_trace("Detect ATL2FW %x\n", self->fw_ver_actual); + self->aq_fw_ops = *fw_ops; + err = self->aq_fw_ops->init(self); + + self->chip_features |= ATL_HW_CHIP_ANTIGUA; + + return err; +} + +static bool hw_atl2_mcp_boot_complete(struct aq_hw_s *self) +{ + u32 rbl_status; + + rbl_status = hw_atl2_mif_mcp_boot_reg_get(self); + if (rbl_status & AQ_A2_FW_BOOT_COMPLETE_MASK) + return true; + + /* Host boot requested */ + if (hw_atl2_mif_host_req_int_get(self) & HW_ATL2_MCP_HOST_REQ_INT_READY) + return true; + + return false; +} + +int hw_atl2_utils_soft_reset(struct aq_hw_s *self) +{ + bool rbl_complete = false; + u32 rbl_status = 0; + u32 rbl_request; + int err; + + hw_atl2_mif_host_req_int_clr(self, 0x01); + rbl_request = AQ_A2_FW_BOOT_REQ_REBOOT; +#ifdef AQ_CFG_FAST_START + rbl_request |= AQ_A2_FW_BOOT_REQ_MAC_FAST_BOOT; +#endif + hw_atl2_mif_mcp_boot_reg_set(self, rbl_request); + + /* Wait for RBL boot */ + err = readx_poll_timeout_atomic(hw_atl2_mif_mcp_boot_reg_get, self, + rbl_status, + ((rbl_status & AQ_A2_BOOT_STARTED) && + (rbl_status != 0xFFFFFFFFu)), + 10, 200000); + if (err) { + aq_pr_err("Boot code hanged"); + goto err_exit; + } + + err = readx_poll_timeout_atomic(hw_atl2_mcp_boot_complete, self, + rbl_complete, + rbl_complete, + 10, 2000000); + + if (err) { + aq_pr_err("FW Restart timed out"); + goto err_exit; + } + + rbl_status = hw_atl2_mif_mcp_boot_reg_get(self); + + if (rbl_status & AQ_A2_FW_BOOT_FAILED_MASK) { + err = -EIO; + aq_pr_err("FW Restart failed"); + goto err_exit; + } + + if (hw_atl2_mif_host_req_int_get(self) & + HW_ATL2_MCP_HOST_REQ_INT_READY) { + err = -EIO; + aq_pr_err("No FW detected. Dynamic FW load not implemented"); + goto err_exit; + } + + if (self->aq_fw_ops) { + err = self->aq_fw_ops->init(self); + if (err) { + aq_pr_err("FW Init failed"); + goto err_exit; + } + } + +err_exit: + return err; +} diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.h new file mode 100644 index 000000000000..b66fa346581c --- /dev/null +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.h @@ -0,0 +1,606 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Atlantic Network Driver + * Copyright (C) 2020 Marvell International Ltd. + */ + +#ifndef HW_ATL2_UTILS_H +#define HW_ATL2_UTILS_H + +#include "aq_hw.h" + +/* F W A P I */ + +struct link_options_s { + u8 link_up:1; + u8 link_renegotiate:1; + u8 minimal_link_speed:1; + u8 internal_loopback:1; + u8 external_loopback:1; + u8 rate_10M_hd:1; + u8 rate_100M_hd:1; + u8 rate_1G_hd:1; + + u8 rate_10M:1; + u8 rate_100M:1; + u8 rate_1G:1; + u8 rate_2P5G:1; + u8 rate_N2P5G:1; + u8 rate_5G:1; + u8 rate_N5G:1; + u8 rate_10G:1; + + u8 eee_100M:1; + u8 eee_1G:1; + u8 eee_2P5G:1; + u8 eee_5G:1; + u8 eee_10G:1; + u8 rsvd3:3; + + u8 pause_rx:1; + u8 pause_tx:1; + u8 rsvd4:1; + u8 downshift:1; + u8 downshift_retry:4; +}; + +struct link_control_s { + u8 mode:4; + u8 disable_crc_corruption:1; + u8 discard_short_frames:1; + u8 flow_control_mode:1; + u8 disable_length_check:1; + + u8 discard_errored_frames:1; + u8 control_frame_enable:1; + u8 enable_tx_padding:1; + u8 enable_crc_forwarding:1; + u8 enable_frame_padding_removal_rx: 1; + u8 promiscuous_mode: 1; + u8 rsvd:2; + + u16 rsvd2; +}; + +struct thermal_shutdown_s { + u8 enable:1; + u8 warning_enable:1; + u8 rsvd:6; + + u8 shutdown_temperature; + u8 cold_temperature; + u8 warning_temperature; +}; + +struct mac_address_s { + u8 mac_address[6]; +}; + +struct mac_address_aligned_s { + struct mac_address_s aligned; + u16 rsvd; +}; + +struct sleep_proxy_s { + struct wake_on_lan_s { + u8 wake_on_magic_packet:1; + u8 wake_on_pattern:1; + u8 wake_on_link_up:1; + u8 wake_on_link_down:1; + u8 wake_on_ping:1; + u8 wake_on_timer:1; + u8 rsvd:2; + + u8 rsvd2; + u16 rsvd3; + + u32 link_up_timeout; + u32 link_down_timeout; + u32 timer; + } wake_on_lan; + + struct { + u32 mask[4]; + u32 crc32; + } wake_up_pattern[8]; + + struct __packed { + u8 arp_responder:1; + u8 echo_responder:1; + u8 igmp_client:1; + u8 echo_truncate:1; + u8 address_guard:1; + u8 ignore_fragmented:1; + u8 rsvd:2; + + u16 echo_max_len; + u8 rsvd2; + } ipv4_offload; + + u32 ipv4_offload_addr[8]; + u32 reserved[8]; + + struct __packed { + u8 ns_responder:1; + u8 echo_responder:1; + u8 mld_client:1; + u8 echo_truncate:1; + u8 address_guard:1; + u8 rsvd:3; + + u16 echo_max_len; + u8 rsvd2; + } ipv6_offload; + + u32 ipv6_offload_addr[16][4]; + + struct { + u16 port[16]; + } tcp_port_offload; + + struct { + u16 port[16]; + } udp_port_offload; + + struct { + u32 retry_count; + u32 retry_interval; + } ka4_offload; + + struct { + u32 timeout; + u16 local_port; + u16 remote_port; + u8 remote_mac_addr[6]; + u16 rsvd; + u32 rsvd2; + u32 rsvd3; + u16 rsvd4; + u16 win_size; + u32 seq_num; + u32 ack_num; + u32 local_ip; + u32 remote_ip; + } ka4_connection[16]; + + struct { + u32 retry_count; + u32 retry_interval; + } ka6_offload; + + struct { + u32 timeout; + u16 local_port; + u16 remote_port; + u8 remote_mac_addr[6]; + u16 rsvd; + u32 rsvd2; + u32 rsvd3; + u16 rsvd4; + u16 win_size; + u32 seq_num; + u32 ack_num; + u32 local_ip[4]; + u32 remote_ip[4]; + } ka6_connection[16]; + + struct { + u32 rr_count; + u32 rr_buf_len; + u32 idx_offset; + u32 rr__offset; + } mdns_offload; +}; + +struct pause_quanta_s { + u16 quanta_10M; + u16 threshold_10M; + u16 quanta_100M; + u16 threshold_100M; + u16 quanta_1G; + u16 threshold_1G; + u16 quanta_2P5G; + u16 threshold_2P5G; + u16 quanta_5G; + u16 threshold_5G; + u16 quanta_10G; + u16 threshold_10G; +}; + +struct data_buffer_status_s { + u32 data_offset; + u32 data_length; +}; + +struct device_caps_s { + u8 finite_flashless:1; + u8 cable_diag:1; + u8 ncsi:1; + u8 avb:1; + u8 rsvd:4; + + u8 rsvd2; + u16 rsvd3; + u32 rsvd4; +}; + +struct version_s { + struct bundle_version_t { + u8 major; + u8 minor; + u16 build; + } bundle; + struct mac_version_t { + u8 major; + u8 minor; + u16 build; + } mac; + struct phy_version_t { + u8 major; + u8 minor; + u16 build; + } phy; + u32 rsvd; +}; + +struct link_status_s { + u8 link_state:4; + u8 link_rate:4; + + u8 pause_tx:1; + u8 pause_rx:1; + u8 eee:1; + u8 duplex:1; + u8 rsvd:4; + + u16 rsvd2; +}; + +struct wol_status_s { + u8 wake_count; + u8 wake_reason; + + u16 wake_up_packet_length :12; + u16 wake_up_pattern_number :3; + u16 rsvd:1; + + u32 wake_up_packet[379]; +}; + +struct mac_health_monitor_s { + u8 mac_ready:1; + u8 mac_fault:1; + u8 mac_flashless_finished:1; + u8 rsvd:5; + + u8 mac_temperature; + u16 mac_heart_beat; + u16 mac_fault_code; + u16 rsvd2; +}; + +struct phy_health_monitor_s { + u8 phy_ready:1; + u8 phy_fault:1; + u8 phy_hot_warning:1; + u8 rsvd:5; + + u8 phy_temperature; + u16 phy_heart_beat; + u16 phy_fault_code; + u16 rsvd2; +}; + +struct device_link_caps_s { + u8 rsvd:3; + u8 internal_loopback:1; + u8 external_loopback:1; + u8 rate_10M_hd:1; + u8 rate_100M_hd:1; + u8 rate_1G_hd:1; + + u8 rate_10M:1; + u8 rate_100M:1; + u8 rate_1G:1; + u8 rate_2P5G:1; + u8 rate_N2P5G:1; + u8 rate_5G:1; + u8 rate_N5G:1; + u8 rate_10G:1; + + u8 rsvd3:1; + u8 eee_100M:1; + u8 eee_1G:1; + u8 eee_2P5G:1; + u8 rsvd4:1; + u8 eee_5G:1; + u8 rsvd5:1; + u8 eee_10G:1; + + u8 pause_rx:1; + u8 pause_tx:1; + u8 pfc:1; + u8 downshift:1; + u8 downshift_retry:4; +}; + +struct sleep_proxy_caps_s { + u8 ipv4_offload:1; + u8 ipv6_offload:1; + u8 tcp_port_offload:1; + u8 udp_port_offload:1; + u8 ka4_offload:1; + u8 ka6_offload:1; + u8 mdns_offload:1; + u8 wake_on_ping:1; + + u8 wake_on_magic_packet:1; + u8 wake_on_pattern:1; + u8 wake_on_timer:1; + u8 wake_on_link:1; + u8 wake_patterns_count:4; + + u8 ipv4_count; + u8 ipv6_count; + + u8 tcp_port_offload_count; + u8 udp_port_offload_count; + + u8 tcp4_ka_count; + u8 tcp6_ka_count; + + u8 igmp_offload:1; + u8 mld_offload:1; + u8 rsvd:6; + + u8 rsvd2; + u16 rsvd3; +}; + +struct lkp_link_caps_s { + u8 rsvd:5; + u8 rate_10M_hd:1; + u8 rate_100M_hd:1; + u8 rate_1G_hd:1; + + u8 rate_10M:1; + u8 rate_100M:1; + u8 rate_1G:1; + u8 rate_2P5G:1; + u8 rate_N2P5G:1; + u8 rate_5G:1; + u8 rate_N5G:1; + u8 rate_10G:1; + + u8 rsvd2:1; + u8 eee_100M:1; + u8 eee_1G:1; + u8 eee_2P5G:1; + u8 rsvd3:1; + u8 eee_5G:1; + u8 rsvd4:1; + u8 eee_10G:1; + + u8 pause_rx:1; + u8 pause_tx:1; + u8 rsvd5:6; +}; + +struct core_dump_s { + u32 reg0; + u32 reg1; + u32 reg2; + + u32 hi; + u32 lo; + + u32 regs[32]; +}; + +struct trace_s { + u32 sync_counter; + u32 mem_buffer[0x1ff]; +}; + +struct cable_diag_control_s { + u8 toggle :1; + u8 rsvd:7; + + u8 wait_timeout_sec; + u16 rsvd2; +}; + +struct cable_diag_lane_data_s { + u8 result_code; + u8 dist; + u8 far_dist; + u8 rsvd; +}; + +struct cable_diag_status_s { + struct cable_diag_lane_data_s lane_data[4]; + u8 transact_id; + u8 status:4; + u8 rsvd:4; + u16 rsvd2; +}; + +struct statistics_s { + struct { + u32 link_up; + u32 link_down; + } link; + + struct { + u64 tx_unicast_octets; + u64 tx_multicast_octets; + u64 tx_broadcast_octets; + u64 rx_unicast_octets; + u64 rx_multicast_octets; + u64 rx_broadcast_octets; + + u32 tx_unicast_frames; + u32 tx_multicast_frames; + u32 tx_broadcast_frames; + u32 tx_errors; + + u32 rx_unicast_frames; + u32 rx_multicast_frames; + u32 rx_broadcast_frames; + u32 rx_dropped_frames; + u32 rx_error_frames; + + u32 tx_good_frames; + u32 rx_good_frames; + u32 reserve_fw_gap; + } msm; + u32 main_loop_cycles; + u32 reserve_fw_gap; +}; + +struct filter_caps_s { + u8 l2_filters_base_index:6; + u8 flexible_filter_mask:2; + u8 l2_filter_count; + u8 ethertype_filter_base_index; + u8 ethertype_filter_count; + + u8 vlan_filter_base_index; + u8 vlan_filter_count; + u8 l3_ip4_filter_base_index:4; + u8 l3_ip4_filter_count:4; + u8 l3_ip6_filter_base_index:4; + u8 l3_ip6_filter_count:4; + + u8 l4_filter_base_index:4; + u8 l4_filter_count:4; + u8 l4_flex_filter_base_index:4; + u8 l4_flex_filter_count:4; + u8 rslv_tbl_base_index; + u8 rslv_tbl_count; +}; + +struct request_policy_s { + struct { + u8 all:1; + u8 mcast:1; + u8 rx_queue_tc_index:5; + u8 queue_or_tc:1; + } promisc; + + struct { + u8 accept:1; + u8 rsvd:1; + u8 rx_queue_tc_index:5; + u8 queue_or_tc:1; + } bcast; + + struct { + u8 accept:1; + u8 rsvd:1; + u8 rx_queue_tc_index:5; + u8 queue_or_tc:1; + } mcast; + + u8 rsvd:8; +}; + +struct fw_interface_in { + u32 mtu; + u32 rsvd1; + struct mac_address_aligned_s mac_address; + struct link_control_s link_control; + u32 rsvd2; + struct link_options_s link_options; + u32 rsvd3; + struct thermal_shutdown_s thermal_shutdown; + u32 rsvd4; + struct sleep_proxy_s sleep_proxy; + u32 rsvd5; + struct pause_quanta_s pause_quanta[8]; + struct cable_diag_control_s cable_diag_control; + u32 rsvd6; + struct data_buffer_status_s data_buffer_status; + u32 rsvd7; + struct request_policy_s request_policy; +}; + +struct transaction_counter_s { + u16 transaction_cnt_a; + u16 transaction_cnt_b; +}; + +struct management_status_s { + struct mac_address_s mac_address; + u16 vlan; + + struct{ + u32 enable : 1; + u32 rsvd:31; + } flags; + + u32 rsvd1; + u32 rsvd2; + u32 rsvd3; + u32 rsvd4; + u32 rsvd5; +}; + +struct fw_interface_out { + struct transaction_counter_s transaction_id; + struct version_s version; + struct link_status_s link_status; + struct wol_status_s wol_status; + u32 rsvd; + u32 rsvd2; + struct mac_health_monitor_s mac_health_monitor; + u32 rsvd3; + u32 rsvd4; + struct phy_health_monitor_s phy_health_monitor; + u32 rsvd5; + u32 rsvd6; + struct cable_diag_status_s cable_diag_status; + u32 rsvd7; + struct device_link_caps_s device_link_caps; + u32 rsvd8; + struct sleep_proxy_caps_s sleep_proxy_caps; + u32 rsvd9; + struct lkp_link_caps_s lkp_link_caps; + u32 rsvd10; + struct core_dump_s core_dump; + u32 rsvd11; + struct statistics_s stats; + u32 rsvd12; + struct filter_caps_s filter_caps; + struct device_caps_s device_caps; + u32 rsvd13; + struct management_status_s management_status; + u32 reserve[21]; + struct trace_s trace; +}; + +#define AQ_A2_FW_LINK_RATE_INVALID 0 +#define AQ_A2_FW_LINK_RATE_10M 1 +#define AQ_A2_FW_LINK_RATE_100M 2 +#define AQ_A2_FW_LINK_RATE_1G 3 +#define AQ_A2_FW_LINK_RATE_2G5 4 +#define AQ_A2_FW_LINK_RATE_5G 5 +#define AQ_A2_FW_LINK_RATE_10G 6 + +#define AQ_HOST_MODE_INVALID 0U +#define AQ_HOST_MODE_ACTIVE 1U +#define AQ_HOST_MODE_SLEEP_PROXY 2U +#define AQ_HOST_MODE_LOW_POWER 3U +#define AQ_HOST_MODE_SHUTDOWN 4U + +int hw_atl2_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops); + +int hw_atl2_utils_soft_reset(struct aq_hw_s *self); + +u32 hw_atl2_utils_get_fw_version(struct aq_hw_s *self); + +int hw_atl2_utils_get_action_resolve_table_caps(struct aq_hw_s *self, + u8 *base_index, u8 *count); + +extern const struct aq_fw_ops aq_a2_fw_ops; + +#endif /* HW_ATL2_UTILS_H */ diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils_fw.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils_fw.c new file mode 100644 index 000000000000..0ffc33bd67d0 --- /dev/null +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils_fw.c @@ -0,0 +1,320 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Atlantic Network Driver + * Copyright (C) 2020 Marvell International Ltd. + */ + +#include <linux/iopoll.h> + +#include "aq_hw.h" +#include "aq_hw_utils.h" +#include "hw_atl/hw_atl_llh.h" +#include "hw_atl2_utils.h" +#include "hw_atl2_llh.h" +#include "hw_atl2_internal.h" + +#define AQ_A2_FW_READ_TRY_MAX 1000 + +#define hw_atl2_shared_buffer_write(HW, ITEM, VARIABLE) \ + hw_atl2_mif_shared_buf_write(HW,\ + (offsetof(struct fw_interface_in, ITEM) / sizeof(u32)),\ + (u32 *)&(VARIABLE), sizeof(VARIABLE) / sizeof(u32)) + +#define hw_atl2_shared_buffer_get(HW, ITEM, VARIABLE) \ + hw_atl2_mif_shared_buf_get(HW, \ + (offsetof(struct fw_interface_in, ITEM) / sizeof(u32)),\ + (u32 *)&(VARIABLE), \ + sizeof(VARIABLE) / sizeof(u32)) + +/* This should never be used on non atomic fields, + * treat any > u32 read as non atomic. + */ +#define hw_atl2_shared_buffer_read(HW, ITEM, VARIABLE) \ +{\ + BUILD_BUG_ON_MSG((offsetof(struct fw_interface_out, ITEM) % \ + sizeof(u32)) != 0,\ + "Non aligned read " # ITEM);\ + BUILD_BUG_ON_MSG(sizeof(VARIABLE) > sizeof(u32),\ + "Non atomic read " # ITEM);\ + hw_atl2_mif_shared_buf_read(HW, \ + (offsetof(struct fw_interface_out, ITEM) / sizeof(u32)),\ + (u32 *)&(VARIABLE), sizeof(VARIABLE) / sizeof(u32));\ +} + +#define hw_atl2_shared_buffer_read_safe(HW, ITEM, DATA) \ + hw_atl2_shared_buffer_read_block((HW), \ + (offsetof(struct fw_interface_out, ITEM) / sizeof(u32)),\ + sizeof(((struct fw_interface_out *)0)->ITEM) / sizeof(u32),\ + (DATA)) + +static int hw_atl2_shared_buffer_read_block(struct aq_hw_s *self, + u32 offset, u32 dwords, void *data) +{ + struct transaction_counter_s tid1, tid2; + int cnt = 0; + + do { + do { + hw_atl2_shared_buffer_read(self, transaction_id, tid1); + cnt++; + if (cnt > AQ_A2_FW_READ_TRY_MAX) + return -ETIME; + if (tid1.transaction_cnt_a != tid1.transaction_cnt_b) + udelay(1); + } while (tid1.transaction_cnt_a != tid1.transaction_cnt_b); + + hw_atl2_mif_shared_buf_read(self, offset, (u32 *)data, dwords); + + hw_atl2_shared_buffer_read(self, transaction_id, tid2); + + cnt++; + if (cnt > AQ_A2_FW_READ_TRY_MAX) + return -ETIME; + } while (tid2.transaction_cnt_a != tid2.transaction_cnt_b || + tid1.transaction_cnt_a != tid2.transaction_cnt_a); + + return 0; +} + +static inline int hw_atl2_shared_buffer_finish_ack(struct aq_hw_s *self) +{ + u32 val; + int err; + + hw_atl2_mif_host_finished_write_set(self, 1U); + err = readx_poll_timeout_atomic(hw_atl2_mif_mcp_finished_read_get, + self, val, val == 0U, + 100, 100000U); + WARN(err, "hw_atl2_shared_buffer_finish_ack"); + + return err; +} + +static int aq_a2_fw_init(struct aq_hw_s *self) +{ + struct link_control_s link_control; + u32 mtu; + u32 val; + int err; + + hw_atl2_shared_buffer_get(self, link_control, link_control); + link_control.mode = AQ_HOST_MODE_ACTIVE; + hw_atl2_shared_buffer_write(self, link_control, link_control); + + hw_atl2_shared_buffer_get(self, mtu, mtu); + mtu = HW_ATL2_MTU_JUMBO; + hw_atl2_shared_buffer_write(self, mtu, mtu); + + hw_atl2_mif_host_finished_write_set(self, 1U); + err = readx_poll_timeout_atomic(hw_atl2_mif_mcp_finished_read_get, + self, val, val == 0U, + 100, 5000000U); + WARN(err, "hw_atl2_shared_buffer_finish_ack"); + + return err; +} + +static int aq_a2_fw_deinit(struct aq_hw_s *self) +{ + struct link_control_s link_control; + + hw_atl2_shared_buffer_get(self, link_control, link_control); + link_control.mode = AQ_HOST_MODE_SHUTDOWN; + hw_atl2_shared_buffer_write(self, link_control, link_control); + + return hw_atl2_shared_buffer_finish_ack(self); +} + +static void a2_link_speed_mask2fw(u32 speed, + struct link_options_s *link_options) +{ + link_options->rate_10G = !!(speed & AQ_NIC_RATE_10G); + link_options->rate_5G = !!(speed & AQ_NIC_RATE_5G); + link_options->rate_N5G = !!(speed & AQ_NIC_RATE_5GSR); + link_options->rate_2P5G = !!(speed & AQ_NIC_RATE_2G5); + link_options->rate_N2P5G = link_options->rate_2P5G; + link_options->rate_1G = !!(speed & AQ_NIC_RATE_1G); + link_options->rate_100M = !!(speed & AQ_NIC_RATE_100M); + link_options->rate_10M = !!(speed & AQ_NIC_RATE_10M); +} + +static int aq_a2_fw_set_link_speed(struct aq_hw_s *self, u32 speed) +{ + struct link_options_s link_options; + + hw_atl2_shared_buffer_get(self, link_options, link_options); + link_options.link_up = 1U; + a2_link_speed_mask2fw(speed, &link_options); + hw_atl2_shared_buffer_write(self, link_options, link_options); + + return hw_atl2_shared_buffer_finish_ack(self); +} + +static int aq_a2_fw_set_state(struct aq_hw_s *self, + enum hal_atl_utils_fw_state_e state) +{ + struct link_options_s link_options; + + hw_atl2_shared_buffer_get(self, link_options, link_options); + + switch (state) { + case MPI_INIT: + link_options.link_up = 1U; + break; + case MPI_DEINIT: + link_options.link_up = 0U; + break; + case MPI_RESET: + case MPI_POWER: + /* No actions */ + break; + } + + hw_atl2_shared_buffer_write(self, link_options, link_options); + + return hw_atl2_shared_buffer_finish_ack(self); +} + +static int aq_a2_fw_update_link_status(struct aq_hw_s *self) +{ + struct link_status_s link_status; + + hw_atl2_shared_buffer_read(self, link_status, link_status); + + switch (link_status.link_rate) { + case AQ_A2_FW_LINK_RATE_10G: + self->aq_link_status.mbps = 10000; + break; + case AQ_A2_FW_LINK_RATE_5G: + self->aq_link_status.mbps = 5000; + break; + case AQ_A2_FW_LINK_RATE_2G5: + self->aq_link_status.mbps = 2500; + break; + case AQ_A2_FW_LINK_RATE_1G: + self->aq_link_status.mbps = 1000; + break; + case AQ_A2_FW_LINK_RATE_100M: + self->aq_link_status.mbps = 100; + break; + case AQ_A2_FW_LINK_RATE_10M: + self->aq_link_status.mbps = 10; + break; + default: + self->aq_link_status.mbps = 0; + } + + return 0; +} + +static int aq_a2_fw_get_mac_permanent(struct aq_hw_s *self, u8 *mac) +{ + struct mac_address_aligned_s mac_address; + + hw_atl2_shared_buffer_get(self, mac_address, mac_address); + ether_addr_copy(mac, (u8 *)mac_address.aligned.mac_address); + + return 0; +} + +static int aq_a2_fw_update_stats(struct aq_hw_s *self) +{ + struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv; + struct statistics_s stats; + + hw_atl2_shared_buffer_read_safe(self, stats, &stats); + +#define AQ_SDELTA(_N_, _F_) (self->curr_stats._N_ += \ + stats.msm._F_ - priv->last_stats.msm._F_) + + if (self->aq_link_status.mbps) { + AQ_SDELTA(uprc, rx_unicast_frames); + AQ_SDELTA(mprc, rx_multicast_frames); + AQ_SDELTA(bprc, rx_broadcast_frames); + AQ_SDELTA(erpr, rx_error_frames); + + AQ_SDELTA(uptc, tx_unicast_frames); + AQ_SDELTA(mptc, tx_multicast_frames); + AQ_SDELTA(bptc, tx_broadcast_frames); + AQ_SDELTA(erpt, tx_errors); + + AQ_SDELTA(ubrc, rx_unicast_octets); + AQ_SDELTA(ubtc, tx_unicast_octets); + AQ_SDELTA(mbrc, rx_multicast_octets); + AQ_SDELTA(mbtc, tx_multicast_octets); + AQ_SDELTA(bbrc, rx_broadcast_octets); + AQ_SDELTA(bbtc, tx_broadcast_octets); + } +#undef AQ_SDELTA + self->curr_stats.dma_pkt_rc = + hw_atl_stats_rx_dma_good_pkt_counter_get(self); + self->curr_stats.dma_pkt_tc = + hw_atl_stats_tx_dma_good_pkt_counter_get(self); + self->curr_stats.dma_oct_rc = + hw_atl_stats_rx_dma_good_octet_counter_get(self); + self->curr_stats.dma_oct_tc = + hw_atl_stats_tx_dma_good_octet_counter_get(self); + self->curr_stats.dpc = hw_atl_rpb_rx_dma_drop_pkt_cnt_get(self); + + memcpy(&priv->last_stats, &stats, sizeof(stats)); + + return 0; +} + +static int aq_a2_fw_renegotiate(struct aq_hw_s *self) +{ + struct link_options_s link_options; + int err; + + hw_atl2_shared_buffer_get(self, link_options, link_options); + link_options.link_renegotiate = 1U; + hw_atl2_shared_buffer_write(self, link_options, link_options); + + err = hw_atl2_shared_buffer_finish_ack(self); + + /* We should put renegotiate status back to zero + * after command completes + */ + link_options.link_renegotiate = 0U; + hw_atl2_shared_buffer_write(self, link_options, link_options); + + return err; +} + +u32 hw_atl2_utils_get_fw_version(struct aq_hw_s *self) +{ + struct version_s version; + + hw_atl2_shared_buffer_read_safe(self, version, &version); + + /* A2 FW version is stored in reverse order */ + return version.mac.major << 24 | + version.mac.minor << 16 | + version.mac.build; +} + +int hw_atl2_utils_get_action_resolve_table_caps(struct aq_hw_s *self, + u8 *base_index, u8 *count) +{ + struct filter_caps_s filter_caps; + int err; + + err = hw_atl2_shared_buffer_read_safe(self, filter_caps, &filter_caps); + if (err) + return err; + + *base_index = filter_caps.rslv_tbl_base_index; + *count = filter_caps.rslv_tbl_count; + return 0; +} + +const struct aq_fw_ops aq_a2_fw_ops = { + .init = aq_a2_fw_init, + .deinit = aq_a2_fw_deinit, + .reset = NULL, + .renegotiate = aq_a2_fw_renegotiate, + .get_mac_permanent = aq_a2_fw_get_mac_permanent, + .set_link_speed = aq_a2_fw_set_link_speed, + .set_state = aq_a2_fw_set_state, + .update_link_status = aq_a2_fw_update_link_status, + .update_stats = aq_a2_fw_update_stats, +}; diff --git a/drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c b/drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c index fbe9d88b13c7..36c7cf05630a 100644 --- a/drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c +++ b/drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c @@ -846,8 +846,7 @@ static int get_ingress_sakey_record(struct aq_hw_s *hw, rec->key[7] = packed_record[14]; rec->key[7] |= packed_record[15] << 16; - rec->key_len = (rec->key_len & 0xFFFFFFFC) | - (packed_record[16] & 0x3); + rec->key_len = packed_record[16] & 0x3; return 0; } @@ -1158,6 +1157,7 @@ static int set_egress_ctlf_record(struct aq_hw_s *hw, packed_record[0] = rec->sa_da[0] & 0xFFFF; packed_record[1] = (rec->sa_da[0] >> 16) & 0xFFFF; + packed_record[2] = rec->sa_da[1] & 0xFFFF; packed_record[3] = rec->eth_type & 0xFFFF; @@ -1552,7 +1552,7 @@ static int set_egress_sc_record(struct aq_hw_s *hw, packed_record[5] |= (rec->sak_len & 0x3) << 4; - packed_record[7] |= (rec->valid & 0x1) << 15; + packed_record[7] = (rec->valid & 0x1) << 15; return set_raw_egress_record(hw, packed_record, 8, 2, ROWOFFSET_EGRESSSCRECORD + table_index); |