diff options
Diffstat (limited to 'drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h')
| -rw-r--r-- | drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h | 104 |
1 files changed, 89 insertions, 15 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h index a43dea259b12..4e9215bce4ad 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h @@ -284,12 +284,12 @@ #define CCM_REG_GR_ARB_TYPE 0xd015c /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed; that the Store channel priority is - the compliment to 4 of the rest priorities - Aggregation channel; Load + the complement to 4 of the rest priorities - Aggregation channel; Load (FIC0) channel and Load (FIC1). */ #define CCM_REG_GR_LD0_PR 0xd0164 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed; that the Store channel priority is - the compliment to 4 of the rest priorities - Aggregation channel; Load + the complement to 4 of the rest priorities - Aggregation channel; Load (FIC0) channel and Load (FIC1). */ #define CCM_REG_GR_LD1_PR 0xd0168 /* [RW 2] General flags index. */ @@ -2212,7 +2212,7 @@ * MAC DA 2. The reset default is set to mask out all parameters. */ #define NIG_REG_P0_LLH_PTP_PARAM_MASK 0x187a0 -/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set +/* [RW 14] Mask register for the rules used in detecting PTP packets. Set * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; @@ -2381,7 +2381,7 @@ * MAC DA 2. The reset default is set to mask out all parameters. */ #define NIG_REG_P1_LLH_PTP_PARAM_MASK 0x187c8 -/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set +/* [RW 14] Mask register for the rules used in detecting PTP packets. Set * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; @@ -2493,7 +2493,7 @@ * MAC DA 2. The reset default is set to mask out all parameters. */ #define NIG_REG_P0_TLLH_PTP_PARAM_MASK 0x187f0 -/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set +/* [RW 14] Mask register for the rules used in detecting PTP packets. Set * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; @@ -2529,7 +2529,7 @@ * MAC DA 2. The reset default is set to mask out all parameters. */ #define NIG_REG_P1_TLLH_PTP_PARAM_MASK 0x187f8 -/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set +/* [RW 14] Mask register for the rules used in detecting PTP packets. Set * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; @@ -4489,11 +4489,11 @@ #define TCM_REG_GR_ARB_TYPE 0x50114 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed that the Store channel is the - compliment of the other 3 groups. */ + complement of the other 3 groups. */ #define TCM_REG_GR_LD0_PR 0x5011c /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed that the Store channel is the - compliment of the other 3 groups. */ + complement of the other 3 groups. */ #define TCM_REG_GR_LD1_PR 0x50120 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are @@ -5020,11 +5020,11 @@ #define UCM_REG_GR_ARB_TYPE 0xe0144 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed that the Store channel group is - compliment to the others. */ + complement to the others. */ #define UCM_REG_GR_LD0_PR 0xe014c /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed that the Store channel group is - compliment to the others. */ + complement to the others. */ #define UCM_REG_GR_LD1_PR 0xe0150 /* [RW 2] The queue index for invalidate counter flag decision. */ #define UCM_REG_INV_CFLG_Q 0xe00e4 @@ -5523,11 +5523,11 @@ #define XCM_REG_GR_ARB_TYPE 0x2020c /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed that the Channel group is the - compliment of the other 3 groups. */ + complement of the other 3 groups. */ #define XCM_REG_GR_LD0_PR 0x20214 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed that the Channel group is the - compliment of the other 3 groups. */ + complement of the other 3 groups. */ #define XCM_REG_GR_LD1_PR 0x20218 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are @@ -6218,7 +6218,7 @@ #define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2) #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12) #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28) -#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1<<31) +#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1U<<31) #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29) #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30) #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15) @@ -7639,6 +7639,82 @@ Theotherbitsarereservedandshouldbezero*/ (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7)) #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80) +/* IdleChk registers */ +#define PXP_REG_HST_VF_DISABLED_ERROR_VALID 0x1030bc +#define PXP_REG_HST_VF_DISABLED_ERROR_DATA 0x1030b8 +#define PXP_REG_HST_PER_VIOLATION_VALID 0x1030e0 +#define PXP_REG_HST_INCORRECT_ACCESS_VALID 0x1030cc +#define PXP2_REG_RD_CPL_ERR_DETAILS 0x120778 +#define PXP2_REG_RD_CPL_ERR_DETAILS2 0x12077c +#define PXP2_REG_RQ_GARB 0x120748 +#define PBF_REG_DISABLE_NEW_TASK_PROC_Q0 0x15c1bc +#define PBF_REG_DISABLE_NEW_TASK_PROC_Q1 0x15c1c0 +#define PBF_REG_DISABLE_NEW_TASK_PROC_Q2 0x15c1c4 +#define PBF_REG_DISABLE_NEW_TASK_PROC_Q3 0x15c1c8 +#define PBF_REG_DISABLE_NEW_TASK_PROC_Q4 0x15c1cc +#define PBF_REG_DISABLE_NEW_TASK_PROC_Q5 0x15c1d0 +#define PBF_REG_CREDIT_Q2 0x140344 +#define PBF_REG_CREDIT_Q3 0x140348 +#define PBF_REG_CREDIT_Q4 0x14034c +#define PBF_REG_CREDIT_Q5 0x140350 +#define PBF_REG_INIT_CRD_Q2 0x15c238 +#define PBF_REG_INIT_CRD_Q3 0x15c23c +#define PBF_REG_INIT_CRD_Q4 0x15c240 +#define PBF_REG_INIT_CRD_Q5 0x15c244 +#define PBF_REG_TASK_CNT_Q0 0x140374 +#define PBF_REG_TASK_CNT_Q1 0x140378 +#define PBF_REG_TASK_CNT_Q2 0x14037c +#define PBF_REG_TASK_CNT_Q3 0x140380 +#define PBF_REG_TASK_CNT_Q4 0x140384 +#define PBF_REG_TASK_CNT_Q5 0x140388 +#define PBF_REG_TASK_CNT_LB_Q 0x140370 +#define QM_REG_BYTECRD0 0x16e6fc +#define QM_REG_BYTECRD1 0x16e700 +#define QM_REG_BYTECRD2 0x16e704 +#define QM_REG_BYTECRD3 0x16e7ac +#define QM_REG_BYTECRD4 0x16e7b0 +#define QM_REG_BYTECRD5 0x16e7b4 +#define QM_REG_BYTECRD6 0x16e7b8 +#define QM_REG_BYTECRDCMDQ_0 0x16e6e8 +#define QM_REG_BYTECRDERRREG 0x16e708 +#define MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID 0xa714 +#define QM_REG_VOQCREDIT_2 0x1682d8 +#define QM_REG_VOQCREDIT_3 0x1682dc +#define QM_REG_VOQCREDIT_5 0x1682e4 +#define QM_REG_VOQCREDIT_6 0x1682e8 +#define QM_REG_VOQINITCREDIT_3 0x16806c +#define QM_REG_VOQINITCREDIT_6 0x168078 +#define QM_REG_FWVOQ0TOHWVOQ 0x16e7bc +#define QM_REG_FWVOQ1TOHWVOQ 0x16e7c0 +#define QM_REG_FWVOQ2TOHWVOQ 0x16e7c4 +#define QM_REG_FWVOQ3TOHWVOQ 0x16e7c8 +#define QM_REG_FWVOQ4TOHWVOQ 0x16e7cc +#define QM_REG_FWVOQ5TOHWVOQ 0x16e7d0 +#define QM_REG_FWVOQ6TOHWVOQ 0x16e7d4 +#define QM_REG_FWVOQ7TOHWVOQ 0x16e7d8 +#define NIG_REG_INGRESS_EOP_PORT0_EMPTY 0x104ec +#define NIG_REG_INGRESS_EOP_PORT1_EMPTY 0x104f8 +#define NIG_REG_INGRESS_RMP0_DSCR_EMPTY 0x10530 +#define NIG_REG_INGRESS_RMP1_DSCR_EMPTY 0x10538 +#define NIG_REG_INGRESS_LB_PBF_DELAY_EMPTY 0x10508 +#define NIG_REG_EGRESS_MNG0_FIFO_EMPTY 0x10460 +#define NIG_REG_EGRESS_MNG1_FIFO_EMPTY 0x10474 +#define NIG_REG_EGRESS_DEBUG_FIFO_EMPTY 0x10418 +#define NIG_REG_EGRESS_DELAY0_EMPTY 0x10420 +#define NIG_REG_EGRESS_DELAY1_EMPTY 0x10428 +#define NIG_REG_LLH0_FIFO_EMPTY 0x10548 +#define NIG_REG_LLH1_FIFO_EMPTY 0x10558 +#define NIG_REG_P0_TX_MNG_HOST_FIFO_EMPTY 0x182a8 +#define NIG_REG_P0_TLLH_FIFO_EMPTY 0x18308 +#define NIG_REG_P0_HBUF_DSCR_EMPTY 0x18318 +#define NIG_REG_P1_HBUF_DSCR_EMPTY 0x18348 +#define NIG_REG_P0_RX_MACFIFO_EMPTY 0x18570 +#define NIG_REG_P0_TX_MACFIFO_EMPTY 0x18578 +#define NIG_REG_EGRESS_DELAY2_EMPTY 0x1862c +#define NIG_REG_EGRESS_DELAY3_EMPTY 0x18630 +#define NIG_REG_EGRESS_DELAY4_EMPTY 0x18634 +#define NIG_REG_EGRESS_DELAY5_EMPTY 0x18638 + /****************************************************************************** * Description: * Calculates crc 8 on a word value: polynomial 0-1-2-8 @@ -7697,6 +7773,4 @@ static inline u8 calc_crc8(u32 data, u8 crc) return crc_res; } - - #endif /* BNX2X_REG_H */ |