diff options
Diffstat (limited to 'drivers/net/ethernet/pensando/ionic/ionic_if.h')
| -rw-r--r-- | drivers/net/ethernet/pensando/ionic/ionic_if.h | 1452 |
1 files changed, 982 insertions, 470 deletions
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_if.h b/drivers/net/ethernet/pensando/ionic/ionic_if.h index 54547d53b0f2..4a90f611c611 100644 --- a/drivers/net/ethernet/pensando/ionic/ionic_if.h +++ b/drivers/net/ethernet/pensando/ionic/ionic_if.h @@ -1,17 +1,15 @@ -/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB OR BSD-2-Clause */ -/* Copyright (c) 2017-2019 Pensando Systems, Inc. All rights reserved. */ +/* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */ +/* Copyright (c) 2017-2020 Pensando Systems, Inc. All rights reserved. */ #ifndef _IONIC_IF_H_ #define _IONIC_IF_H_ -#pragma pack(push, 1) - #define IONIC_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */ #define IONIC_DEV_INFO_VERSION 1 #define IONIC_IFNAMSIZ 16 /** - * Commands + * enum ionic_cmd_opcode - Device commands */ enum ionic_cmd_opcode { IONIC_CMD_NOP = 0, @@ -36,12 +34,14 @@ enum ionic_cmd_opcode { IONIC_CMD_LIF_RESET = 22, IONIC_CMD_LIF_GETATTR = 23, IONIC_CMD_LIF_SETATTR = 24, + IONIC_CMD_LIF_SETPHC = 25, IONIC_CMD_RX_MODE_SET = 30, IONIC_CMD_RX_FILTER_ADD = 31, IONIC_CMD_RX_FILTER_DEL = 32, /* Queue commands */ + IONIC_CMD_Q_IDENTIFY = 39, IONIC_CMD_Q_INIT = 40, IONIC_CMD_Q_CONTROL = 41, @@ -59,14 +59,19 @@ enum ionic_cmd_opcode { IONIC_CMD_QOS_CLASS_IDENTIFY = 240, IONIC_CMD_QOS_CLASS_INIT = 241, IONIC_CMD_QOS_CLASS_RESET = 242, + IONIC_CMD_QOS_CLASS_UPDATE = 243, + IONIC_CMD_QOS_CLEAR_STATS = 244, + IONIC_CMD_QOS_RESET = 245, /* Firmware commands */ - IONIC_CMD_FW_DOWNLOAD = 254, - IONIC_CMD_FW_CONTROL = 255, + IONIC_CMD_FW_DOWNLOAD = 252, + IONIC_CMD_FW_CONTROL = 253, + IONIC_CMD_FW_DOWNLOAD_V1 = 254, + IONIC_CMD_FW_CONTROL_V1 = 255, }; /** - * Command Return codes + * enum ionic_status_code - Device command return codes */ enum ionic_status_code { IONIC_RC_SUCCESS = 0, /* Success */ @@ -90,8 +95,9 @@ enum ionic_status_code { IONIC_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */ IONIC_RC_ENOSUPP = 19, /* Operation not supported */ IONIC_RC_ERROR = 29, /* Generic error */ - IONIC_RC_ERDMA = 30, /* Generic RDMA error */ + IONIC_RC_EVFID = 31, /* VF ID does not exist */ + IONIC_RC_EBAD_FW = 32, /* FW file is invalid or corrupted */ }; enum ionic_notifyq_opcode { @@ -99,10 +105,11 @@ enum ionic_notifyq_opcode { IONIC_EVENT_RESET = 2, IONIC_EVENT_HEARTBEAT = 3, IONIC_EVENT_LOG = 4, + IONIC_EVENT_XCVR = 5, }; /** - * struct cmd - General admin command format + * struct ionic_admin_cmd - General admin command format * @opcode: Opcode for the command * @lif_index: LIF index * @cmd_data: Opcode-specific command bytes @@ -116,12 +123,11 @@ struct ionic_admin_cmd { /** * struct ionic_admin_comp - General admin command completion format - * @status: The status of the command (enum status_code) - * @comp_index: The index in the descriptor ring for which this - * is the completion. - * @cmd_data: Command-specific bytes. - * @color: Color bit. (Always 0 for commands issued to the - * Device Cmd Registers.) + * @status: Status of the command (enum ionic_status_code) + * @comp_index: Index in the descriptor ring for which this is the completion + * @cmd_data: Command-specific bytes + * @color: Color bit (Always 0 for commands issued to the + * Device Cmd Registers) */ struct ionic_admin_comp { u8 status; @@ -148,7 +154,7 @@ struct ionic_nop_cmd { /** * struct ionic_nop_comp - NOP command completion - * @status: The status of the command (enum status_code) + * @status: Status of the command (enum ionic_status_code) */ struct ionic_nop_comp { u8 status; @@ -158,7 +164,7 @@ struct ionic_nop_comp { /** * struct ionic_dev_init_cmd - Device init command * @opcode: opcode - * @type: device type + * @type: Device type */ struct ionic_dev_init_cmd { u8 opcode; @@ -167,8 +173,8 @@ struct ionic_dev_init_cmd { }; /** - * struct init_comp - Device init command completion - * @status: The status of the command (enum status_code) + * struct ionic_dev_init_comp - Device init command completion + * @status: Status of the command (enum ionic_status_code) */ struct ionic_dev_init_comp { u8 status; @@ -185,8 +191,8 @@ struct ionic_dev_reset_cmd { }; /** - * struct reset_comp - Reset command completion - * @status: The status of the command (enum status_code) + * struct ionic_dev_reset_comp - Reset command completion + * @status: Status of the command (enum ionic_status_code) */ struct ionic_dev_reset_comp { u8 status; @@ -207,8 +213,8 @@ struct ionic_dev_identify_cmd { }; /** - * struct dev_identify_comp - Driver/device identify command completion - * @status: The status of the command (enum status_code) + * struct ionic_dev_identify_comp - Driver/device identify command completion + * @status: Status of the command (enum ionic_status_code) * @ver: Version of identify returned by device */ struct ionic_dev_identify_comp { @@ -227,8 +233,8 @@ enum ionic_os_type { }; /** - * union drv_identity - driver identity information - * @os_type: OS type (see enum os_type) + * union ionic_drv_identity - driver identity information + * @os_type: OS type (see enum ionic_os_type) * @os_dist: OS distribution, numeric format * @os_dist_str: OS distribution, string format * @kernel_ver: Kernel version, numeric format @@ -244,26 +250,29 @@ union ionic_drv_identity { char kernel_ver_str[32]; char driver_ver_str[32]; }; - __le32 words[512]; + __le32 words[478]; }; /** - * union dev_identity - device identity information + * union ionic_dev_identity - device identity information * @version: Version of device identify * @type: Identify type (0 for now) * @nports: Number of ports provisioned * @nlifs: Number of LIFs provisioned * @nintrs: Number of interrupts provisioned * @ndbpgs_per_lif: Number of doorbell pages per LIF - * @intr_coal_mult: Interrupt coalescing multiplication factor. + * @intr_coal_mult: Interrupt coalescing multiplication factor * Scale user-supplied interrupt coalescing * value in usecs to device units using: * device units = usecs * mult / div - * @intr_coal_div: Interrupt coalescing division factor. + * @intr_coal_div: Interrupt coalescing division factor * Scale user-supplied interrupt coalescing * value in usecs to device units using: * device units = usecs * mult / div - * + * @eq_count: Number of shared event queues + * @hwstamp_mask: Bitmask for subtraction of hardware tick values. + * @hwstamp_mult: Hardware tick to nanosecond multiplier. + * @hwstamp_shift: Hardware tick to nanosecond divisor (power of two). */ union ionic_dev_identity { struct { @@ -277,8 +286,12 @@ union ionic_dev_identity { __le32 ndbpgs_per_lif; __le32 intr_coal_mult; __le32 intr_coal_div; + __le32 eq_count; + __le64 hwstamp_mask; + __le32 hwstamp_mult; + __le32 hwstamp_shift; }; - __le32 words[512]; + __le32 words[478]; }; enum ionic_lif_type { @@ -288,10 +301,10 @@ enum ionic_lif_type { }; /** - * struct ionic_lif_identify_cmd - lif identify command + * struct ionic_lif_identify_cmd - LIF identify command * @opcode: opcode - * @type: lif type (enum lif_type) - * @ver: version of identify returned by device + * @type: LIF type (enum ionic_lif_type) + * @ver: Version of identify returned by device */ struct ionic_lif_identify_cmd { u8 opcode; @@ -301,9 +314,9 @@ struct ionic_lif_identify_cmd { }; /** - * struct ionic_lif_identify_comp - lif identify command completion - * @status: status of the command (enum status_code) - * @ver: version of identify returned by device + * struct ionic_lif_identify_comp - LIF identify command completion + * @status: Status of the command (enum ionic_status_code) + * @ver: Version of identify returned by device */ struct ionic_lif_identify_comp { u8 status; @@ -311,13 +324,24 @@ struct ionic_lif_identify_comp { u8 rsvd2[14]; }; +/** + * enum ionic_lif_capability - LIF capabilities + * @IONIC_LIF_CAP_ETH: LIF supports Ethernet + * @IONIC_LIF_CAP_RDMA: LIF supports RDMA + */ enum ionic_lif_capability { IONIC_LIF_CAP_ETH = BIT(0), IONIC_LIF_CAP_RDMA = BIT(1), }; /** - * Logical Queue Types + * enum ionic_logical_qtype - Logical Queue Types + * @IONIC_QTYPE_ADMINQ: Administrative Queue + * @IONIC_QTYPE_NOTIFYQ: Notify Queue + * @IONIC_QTYPE_RXQ: Receive Queue + * @IONIC_QTYPE_TXQ: Transmit Queue + * @IONIC_QTYPE_EQ: Event Queue + * @IONIC_QTYPE_MAX: Max queue type supported */ enum ionic_logical_qtype { IONIC_QTYPE_ADMINQ = 0, @@ -329,10 +353,72 @@ enum ionic_logical_qtype { }; /** - * struct ionic_lif_logical_qtype - Descriptor of logical to hardware queue type. - * @qtype: Hardware Queue Type. - * @qid_count: Number of Queue IDs of the logical type. - * @qid_base: Minimum Queue ID of the logical type. + * enum ionic_q_feature - Common Features for most queue types + * + * Common features use bits 0-15. Per-queue-type features use higher bits. + * + * @IONIC_QIDENT_F_CQ: Queue has completion ring + * @IONIC_QIDENT_F_SG: Queue has scatter/gather ring + * @IONIC_QIDENT_F_EQ: Queue can use event queue + * @IONIC_QIDENT_F_CMB: Queue is in cmb bar + * @IONIC_Q_F_2X_DESC: Double main descriptor size + * @IONIC_Q_F_2X_CQ_DESC: Double cq descriptor size + * @IONIC_Q_F_2X_SG_DESC: Double sg descriptor size + * @IONIC_Q_F_4X_DESC: Quadruple main descriptor size + * @IONIC_Q_F_4X_CQ_DESC: Quadruple cq descriptor size + * @IONIC_Q_F_4X_SG_DESC: Quadruple sg descriptor size + */ +enum ionic_q_feature { + IONIC_QIDENT_F_CQ = BIT_ULL(0), + IONIC_QIDENT_F_SG = BIT_ULL(1), + IONIC_QIDENT_F_EQ = BIT_ULL(2), + IONIC_QIDENT_F_CMB = BIT_ULL(3), + IONIC_Q_F_2X_DESC = BIT_ULL(4), + IONIC_Q_F_2X_CQ_DESC = BIT_ULL(5), + IONIC_Q_F_2X_SG_DESC = BIT_ULL(6), + IONIC_Q_F_4X_DESC = BIT_ULL(7), + IONIC_Q_F_4X_CQ_DESC = BIT_ULL(8), + IONIC_Q_F_4X_SG_DESC = BIT_ULL(9), +}; + +/** + * enum ionic_rxq_feature - RXQ-specific Features + * + * Per-queue-type features use bits 16 and higher. + * + * @IONIC_RXQ_F_HWSTAMP: Queue supports Hardware Timestamping + */ +enum ionic_rxq_feature { + IONIC_RXQ_F_HWSTAMP = BIT_ULL(16), +}; + +/** + * enum ionic_txq_feature - TXQ-specific Features + * + * Per-queue-type features use bits 16 and higher. + * + * @IONIC_TXQ_F_HWSTAMP: Queue supports Hardware Timestamping + */ +enum ionic_txq_feature { + IONIC_TXQ_F_HWSTAMP = BIT(16), +}; + +/** + * struct ionic_hwstamp_bits - Hardware timestamp decoding bits + * @IONIC_HWSTAMP_INVALID: Invalid hardware timestamp value + * @IONIC_HWSTAMP_CQ_NEGOFFSET: Timestamp field negative offset + * from the base cq descriptor. + */ +enum ionic_hwstamp_bits { + IONIC_HWSTAMP_INVALID = ~0ull, + IONIC_HWSTAMP_CQ_NEGOFFSET = 8, +}; + +/** + * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type + * @qtype: Hardware Queue Type + * @qid_count: Number of Queue IDs of the logical type + * @qid_base: Minimum Queue ID of the logical type */ struct ionic_lif_logical_qtype { u8 qtype; @@ -341,20 +427,27 @@ struct ionic_lif_logical_qtype { __le32 qid_base; }; +/** + * enum ionic_lif_state - LIF state + * @IONIC_LIF_DISABLE: LIF disabled + * @IONIC_LIF_ENABLE: LIF enabled + * @IONIC_LIF_QUIESCE: LIF Quiesced + */ enum ionic_lif_state { - IONIC_LIF_DISABLE = 0, + IONIC_LIF_QUIESCE = 0, IONIC_LIF_ENABLE = 1, - IONIC_LIF_HANG_RESET = 2, + IONIC_LIF_DISABLE = 2, }; /** - * LIF configuration - * @state: lif state (enum lif_state) - * @name: lif name - * @mtu: mtu - * @mac: station mac address - * @features: features (enum ionic_eth_hw_features) - * @queue_count: queue counts per queue-type + * union ionic_lif_config - LIF configuration + * @state: LIF state (enum ionic_lif_state) + * @name: LIF name + * @mtu: MTU + * @mac: Station MAC address + * @vlan: Default Vlan ID + * @features: Features (enum ionic_eth_hw_features) + * @queue_count: Queue counts per queue-type */ union ionic_lif_config { struct { @@ -363,45 +456,46 @@ union ionic_lif_config { char name[IONIC_IFNAMSIZ]; __le32 mtu; u8 mac[6]; - u8 rsvd2[2]; + __le16 vlan; __le64 features; __le32 queue_count[IONIC_QTYPE_MAX]; - }; + } __packed; __le32 words[64]; }; /** - * struct ionic_lif_identity - lif identity information (type-specific) + * struct ionic_lif_identity - LIF identity information (type-specific) * - * @capabilities LIF capabilities + * @capabilities: LIF capabilities * - * Ethernet: - * @version: Ethernet identify structure version. - * @features: Ethernet features supported on this lif type. - * @max_ucast_filters: Number of perfect unicast addresses supported. - * @max_mcast_filters: Number of perfect multicast addresses supported. - * @min_frame_size: Minimum size of frames to be sent - * @max_frame_size: Maximim size of frames to be sent - * @config: LIF config struct with features, mtu, mac, q counts + * @eth: Ethernet identify structure + * @version: Ethernet identify structure version + * @max_ucast_filters: Number of perfect unicast addresses supported + * @max_mcast_filters: Number of perfect multicast addresses supported + * @min_frame_size: Minimum size of frames to be sent + * @max_frame_size: Maximum size of frames to be sent + * @hwstamp_tx_modes: Bitmask of BIT_ULL(enum ionic_txstamp_mode) + * @hwstamp_rx_filters: Bitmask of enum ionic_pkt_class + * @config: LIF config struct with features, mtu, mac, q counts * - * RDMA: - * @version: RDMA version of opcodes and queue descriptors. - * @qp_opcodes: Number of rdma queue pair opcodes supported. - * @admin_opcodes: Number of rdma admin opcodes supported. - * @npts_per_lif: Page table size per lif - * @nmrs_per_lif: Number of memory regions per lif - * @nahs_per_lif: Number of address handles per lif - * @max_stride: Max work request stride. - * @cl_stride: Cache line stride. - * @pte_stride: Page table entry stride. - * @rrq_stride: Remote RQ work request stride. - * @rsq_stride: Remote SQ work request stride. + * @rdma: RDMA identify structure + * @version: RDMA version of opcodes and queue descriptors + * @qp_opcodes: Number of RDMA queue pair opcodes supported + * @admin_opcodes: Number of RDMA admin opcodes supported + * @npts_per_lif: Page table size per LIF + * @nmrs_per_lif: Number of memory regions per LIF + * @nahs_per_lif: Number of address handles per LIF + * @max_stride: Max work request stride + * @cl_stride: Cache line stride + * @pte_stride: Page table entry stride + * @rrq_stride: Remote RQ work request stride + * @rsq_stride: Remote SQ work request stride * @dcqcn_profiles: Number of DCQCN profiles - * @aq_qtype: RDMA Admin Qtype. - * @sq_qtype: RDMA Send Qtype. - * @rq_qtype: RDMA Receive Qtype. - * @cq_qtype: RDMA Completion Qtype. - * @eq_qtype: RDMA Event Qtype. + * @aq_qtype: RDMA Admin Qtype + * @sq_qtype: RDMA Send Qtype + * @rq_qtype: RDMA Receive Qtype + * @cq_qtype: RDMA Completion Qtype + * @eq_qtype: RDMA Event Qtype */ union ionic_lif_identity { struct { @@ -415,9 +509,12 @@ union ionic_lif_identity { __le16 rss_ind_tbl_sz; __le32 min_frame_size; __le32 max_frame_size; - u8 rsvd2[106]; + u8 rsvd2[2]; + __le64 hwstamp_tx_modes; + __le64 hwstamp_rx_filters; + u8 rsvd3[88]; union ionic_lif_config config; - } eth; + } __packed eth; struct { u8 version; @@ -439,17 +536,17 @@ union ionic_lif_identity { struct ionic_lif_logical_qtype rq_qtype; struct ionic_lif_logical_qtype cq_qtype; struct ionic_lif_logical_qtype eq_qtype; - } rdma; - }; - __le32 words[512]; + } __packed rdma; + } __packed; + __le32 words[478]; }; /** * struct ionic_lif_init_cmd - LIF init command - * @opcode: opcode - * @type: LIF type (enum lif_type) + * @opcode: Opcode + * @type: LIF type (enum ionic_lif_type) * @index: LIF index - * @info_pa: destination address for lif info (struct ionic_lif_info) + * @info_pa: Destination address for LIF info (struct ionic_lif_info) */ struct ionic_lif_init_cmd { u8 opcode; @@ -462,7 +559,8 @@ struct ionic_lif_init_cmd { /** * struct ionic_lif_init_comp - LIF init command completion - * @status: The status of the command (enum status_code) + * @status: Status of the command (enum ionic_status_code) + * @hw_index: Hardware index of the initialized LIF */ struct ionic_lif_init_comp { u8 status; @@ -472,13 +570,69 @@ struct ionic_lif_init_comp { }; /** + * struct ionic_q_identify_cmd - queue identify command + * @opcode: opcode + * @lif_type: LIF type (enum ionic_lif_type) + * @type: Logical queue type (enum ionic_logical_qtype) + * @ver: Highest queue type version that the driver supports + */ +struct ionic_q_identify_cmd { + u8 opcode; + u8 rsvd; + __le16 lif_type; + u8 type; + u8 ver; + u8 rsvd2[58]; +}; + +/** + * struct ionic_q_identify_comp - queue identify command completion + * @status: Status of the command (enum ionic_status_code) + * @comp_index: Index in the descriptor ring for which this is the completion + * @ver: Queue type version that can be used with FW + */ +struct ionic_q_identify_comp { + u8 status; + u8 rsvd; + __le16 comp_index; + u8 ver; + u8 rsvd2[11]; +}; + +/** + * union ionic_q_identity - queue identity information + * @version: Queue type version that can be used with FW + * @supported: Bitfield of queue versions, first bit = ver 0 + * @features: Queue features (enum ionic_q_feature, etc) + * @desc_sz: Descriptor size + * @comp_sz: Completion descriptor size + * @sg_desc_sz: Scatter/Gather descriptor size + * @max_sg_elems: Maximum number of Scatter/Gather elements + * @sg_desc_stride: Number of Scatter/Gather elements per descriptor + */ +union ionic_q_identity { + struct { + u8 version; + u8 supported; + u8 rsvd[6]; + __le64 features; + __le16 desc_sz; + __le16 comp_sz; + __le16 sg_desc_sz; + __le16 max_sg_elems; + __le16 sg_desc_stride; + }; + __le32 words[478]; +}; + +/** * struct ionic_q_init_cmd - Queue init command * @opcode: opcode * @type: Logical queue type - * @ver: Queue version (defines opcode/descriptor scope) + * @ver: Queue type version * @lif_index: LIF index - * @index: (lif, qtype) relative admin queue index - * @intr_index: Interrupt control register index + * @index: (LIF, qtype) relative admin queue index + * @intr_index: Interrupt control register index, or Event queue index * @pid: Process ID * @flags: * IRQ: Interrupt requested on completion @@ -496,12 +650,12 @@ struct ionic_lif_init_comp { * descriptors. Values of ring_size <2 and >16 are * reserved. * EQ: Enable the Event Queue - * @cos: Class of service for this queue. + * @cos: Class of service for this queue * @ring_size: Queue ring size, encoded as a log2(size) * @ring_base: Queue ring base address * @cq_ring_base: Completion queue ring base address * @sg_ring_base: Scatter/Gather ring base address - * @eq_index: Event queue index + * @features: Mask of queue features to enable, if not in the flags above. */ struct ionic_q_init_cmd { u8 opcode; @@ -518,29 +672,28 @@ struct ionic_q_init_cmd { #define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */ #define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */ #define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */ -#define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */ +#define IONIC_QINIT_F_CMB 0x10 /* Enable cmb-based queue */ +#define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */ u8 cos; u8 ring_size; __le64 ring_base; __le64 cq_ring_base; __le64 sg_ring_base; - __le32 eq_index; - u8 rsvd2[16]; -}; + u8 rsvd2[12]; + __le64 features; +} __packed; /** * struct ionic_q_init_comp - Queue init command completion - * @status: The status of the command (enum status_code) - * @ver: Queue version (defines opcode/descriptor scope) - * @comp_index: The index in the descriptor ring for which this - * is the completion. + * @status: Status of the command (enum ionic_status_code) + * @comp_index: Index in the descriptor ring for which this is the completion * @hw_index: Hardware Queue ID * @hw_type: Hardware Queue type * @color: Color */ struct ionic_q_init_comp { u8 status; - u8 ver; + u8 rsvd; __le16 comp_index; __le32 hw_index; u8 hw_type; @@ -561,10 +714,9 @@ enum ionic_txq_desc_opcode { /** * struct ionic_txq_desc - Ethernet Tx queue descriptor format - * @opcode: Tx operation, see TXQ_DESC_OPCODE_*: + * @cmd: Tx operation, see IONIC_TXQ_DESC_OPCODE_*: * * IONIC_TXQ_DESC_OPCODE_CSUM_NONE: - * * Non-offload send. No segmentation, * fragmentation or checksum calc/insertion is * performed by device; packet is prepared @@ -572,7 +724,6 @@ enum ionic_txq_desc_opcode { * no further manipulation from device. * * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL: - * * Offload 16-bit L4 checksum * calculation/insertion. The device will * calculate the L4 checksum value and @@ -581,14 +732,16 @@ enum ionic_txq_desc_opcode { * is calculated starting at @csum_start bytes * into the packet to the end of the packet. * The checksum insertion position is given - * in @csum_offset. This feature is only - * applicable to protocols such as TCP, UDP - * and ICMP where a standard (i.e. the - * 'IP-style' checksum) one's complement - * 16-bit checksum is used, using an IP - * pseudo-header to seed the calculation. - * Software will preload the L4 checksum - * field with the IP pseudo-header checksum. + * in @csum_offset, which is the offset from + * @csum_start to the checksum field in the L4 + * header. This feature is only applicable to + * protocols such as TCP, UDP and ICMP where a + * standard (i.e. the 'IP-style' checksum) + * one's complement 16-bit checksum is used, + * using an IP pseudo-header to seed the + * calculation. Software will preload the L4 + * checksum field with the IP pseudo-header + * checksum. * * For tunnel encapsulation, @csum_start and * @csum_offset refer to the inner L4 @@ -604,16 +757,14 @@ enum ionic_txq_desc_opcode { * for more info). * * IONIC_TXQ_DESC_OPCODE_CSUM_HW: - * * Offload 16-bit checksum computation to hardware. * If @csum_l3 is set then the packet's L3 checksum is - * updated. Similarly, if @csum_l4 is set the the L4 + * updated. Similarly, if @csum_l4 is set the L4 * checksum is updated. If @encap is set then encap header * checksums are also updated. * * IONIC_TXQ_DESC_OPCODE_TSO: - * - * Device preforms TCP segmentation offload + * Device performs TCP segmentation offload * (TSO). @hdr_len is the number of bytes * to the end of TCP header (the offset to * the TCP payload). @mss is the desired @@ -639,40 +790,41 @@ enum ionic_txq_desc_opcode { * clear CWR in remaining segments. * @flags: * vlan: - * Insert an L2 VLAN header using @vlan_tci. + * Insert an L2 VLAN header using @vlan_tci * encap: - * Calculate encap header checksum. + * Calculate encap header checksum * csum_l3: - * Compute L3 header checksum. + * Compute L3 header checksum * csum_l4: - * Compute L4 header checksum. + * Compute L4 header checksum * tso_sot: * TSO start * tso_eot: * TSO end * @num_sg_elems: Number of scatter-gather elements in SG * descriptor - * @addr: First data buffer's DMA address. - * (Subsequent data buffers are on txq_sg_desc). + * @addr: First data buffer's DMA address + * (Subsequent data buffers are on txq_sg_desc) * @len: First data buffer's length, in bytes * @vlan_tci: VLAN tag to insert in the packet (if requested * by @V-bit). Includes .1p and .1q tags * @hdr_len: Length of packet headers, including - * encapsulating outer header, if applicable. - * Valid for opcodes TXQ_DESC_OPCODE_CALC_CSUM and - * TXQ_DESC_OPCODE_TSO. Should be set to zero for + * encapsulating outer header, if applicable + * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and + * IONIC_TXQ_DESC_OPCODE_TSO. Should be set to zero for * all other modes. For - * TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length + * IONIC_TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length * of headers up to inner-most L4 header. For - * TXQ_DESC_OPCODE_TSO, @hdr_len is up to + * IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to * inner-most L4 payload, so inclusive of * inner-most L4 header. - * @mss: Desired MSS value for TSO. Only applicable for - * TXQ_DESC_OPCODE_TSO. - * @csum_start: Offset into inner-most L3 header of checksum - * @csum_offset: Offset into inner-most L4 header of checksum + * @mss: Desired MSS value for TSO; only applicable for + * IONIC_TXQ_DESC_OPCODE_TSO + * @csum_start: Offset from packet to first byte checked in L4 checksum + * @csum_offset: Offset from csum_start to L4 checksum field */ - +struct ionic_txq_desc { + __le64 cmd; #define IONIC_TXQ_DESC_OPCODE_MASK 0xf #define IONIC_TXQ_DESC_OPCODE_SHIFT 4 #define IONIC_TXQ_DESC_FLAGS_MASK 0xf @@ -694,8 +846,6 @@ enum ionic_txq_desc_opcode { #define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4 #define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8 -struct ionic_txq_desc { - __le64 cmd; __le16 len; union { __le16 vlan_tci; @@ -735,28 +885,38 @@ static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags, *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK; }; -#define IONIC_TX_MAX_SG_ELEMS 8 -#define IONIC_RX_MAX_SG_ELEMS 8 - /** - * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list + * struct ionic_txq_sg_elem - Transmit scatter-gather (SG) descriptor element * @addr: DMA address of SG element data buffer * @len: Length of SG element data buffer, in bytes */ +struct ionic_txq_sg_elem { + __le64 addr; + __le16 len; + __le16 rsvd[3]; +}; + +/** + * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list + * @elems: Scatter-gather elements + */ struct ionic_txq_sg_desc { - struct ionic_txq_sg_elem { - __le64 addr; - __le16 len; - __le16 rsvd[3]; - } elems[IONIC_TX_MAX_SG_ELEMS]; +#define IONIC_TX_MAX_SG_ELEMS 8 +#define IONIC_TX_SG_DESC_STRIDE 8 + struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS]; +}; + +struct ionic_txq_sg_desc_v1 { +#define IONIC_TX_MAX_SG_ELEMS_V1 15 +#define IONIC_TX_SG_DESC_STRIDE_V1 16 + struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1]; }; /** * struct ionic_txq_comp - Ethernet transmit queue completion descriptor - * @status: The status of the command (enum status_code) - * @comp_index: The index in the descriptor ring for which this - * is the completion. - * @color: Color bit. + * @status: Status of the command (enum ionic_status_code) + * @comp_index: Index in the descriptor ring for which this is the completion + * @color: Color bit */ struct ionic_txq_comp { u8 status; @@ -773,16 +933,15 @@ enum ionic_rxq_desc_opcode { /** * struct ionic_rxq_desc - Ethernet Rx queue descriptor format - * @opcode: Rx operation, see RXQ_DESC_OPCODE_*: - * - * RXQ_DESC_OPCODE_SIMPLE: + * @opcode: Rx operation, see IONIC_RXQ_DESC_OPCODE_*: * + * IONIC_RXQ_DESC_OPCODE_SIMPLE: * Receive full packet into data buffer * starting at @addr. Results of * receive, including actual bytes received, * are recorded in Rx completion descriptor. * - * @len: Data buffer's length, in bytes. + * @len: Data buffer's length, in bytes * @addr: Data buffer's DMA address */ struct ionic_rxq_desc { @@ -793,26 +952,33 @@ struct ionic_rxq_desc { }; /** - * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list + * struct ionic_rxq_sg_elem - Receive scatter-gather (SG) descriptor element * @addr: DMA address of SG element data buffer * @len: Length of SG element data buffer, in bytes */ +struct ionic_rxq_sg_elem { + __le64 addr; + __le16 len; + __le16 rsvd[3]; +}; + +/** + * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list + * @elems: Scatter-gather elements + */ struct ionic_rxq_sg_desc { - struct ionic_rxq_sg_elem { - __le64 addr; - __le16 len; - __le16 rsvd[3]; - } elems[IONIC_RX_MAX_SG_ELEMS]; +#define IONIC_RX_MAX_SG_ELEMS 8 +#define IONIC_RX_SG_DESC_STRIDE 8 + struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE]; }; /** * struct ionic_rxq_comp - Ethernet receive queue completion descriptor - * @status: The status of the command (enum status_code) + * @status: Status of the command (enum ionic_status_code) * @num_sg_elems: Number of SG elements used by this descriptor - * @comp_index: The index in the descriptor ring for which this - * is the completion. + * @comp_index: Index in the descriptor ring for which this is the completion * @rss_hash: 32-bit RSS hash - * @csum: 16-bit sum of the packet's L2 payload. + * @csum: 16-bit sum of the packet's L2 payload * If the packet's L2 payload is odd length, an extra * zero-value byte is included in the @csum calculation but * not included in @len. @@ -820,33 +986,51 @@ struct ionic_rxq_sg_desc { * set. Includes .1p and .1q tags. * @len: Received packet length, in bytes. Excludes FCS. * @csum_calc L2 payload checksum is computed or not - * @csum_tcp_ok: The TCP checksum calculated by the device - * matched the checksum in the receive packet's - * TCP header - * @csum_tcp_bad: The TCP checksum calculated by the device did - * not match the checksum in the receive packet's - * TCP header. - * @csum_udp_ok: The UDP checksum calculated by the device - * matched the checksum in the receive packet's - * UDP header - * @csum_udp_bad: The UDP checksum calculated by the device did - * not match the checksum in the receive packet's - * UDP header. - * @csum_ip_ok: The IPv4 checksum calculated by the device - * matched the checksum in the receive packet's - * first IPv4 header. If the receive packet - * contains both a tunnel IPv4 header and a - * transport IPv4 header, the device validates the - * checksum for the both IPv4 headers. - * @csum_ip_bad: The IPv4 checksum calculated by the device did - * not match the checksum in the receive packet's - * first IPv4 header. If the receive packet - * contains both a tunnel IPv4 header and a - * transport IPv4 header, the device validates the - * checksum for both IP headers. - * @VLAN: VLAN header was stripped and placed in @vlan_tci. - * @pkt_type: Packet type - * @color: Color bit. + * @csum_flags: See IONIC_RXQ_COMP_CSUM_F_*: + * + * IONIC_RXQ_COMP_CSUM_F_TCP_OK: + * The TCP checksum calculated by the device + * matched the checksum in the receive packet's + * TCP header. + * + * IONIC_RXQ_COMP_CSUM_F_TCP_BAD: + * The TCP checksum calculated by the device did + * not match the checksum in the receive packet's + * TCP header. + * + * IONIC_RXQ_COMP_CSUM_F_UDP_OK: + * The UDP checksum calculated by the device + * matched the checksum in the receive packet's + * UDP header + * + * IONIC_RXQ_COMP_CSUM_F_UDP_BAD: + * The UDP checksum calculated by the device did + * not match the checksum in the receive packet's + * UDP header. + * + * IONIC_RXQ_COMP_CSUM_F_IP_OK: + * The IPv4 checksum calculated by the device + * matched the checksum in the receive packet's + * first IPv4 header. If the receive packet + * contains both a tunnel IPv4 header and a + * transport IPv4 header, the device validates the + * checksum for the both IPv4 headers. + * + * IONIC_RXQ_COMP_CSUM_F_IP_BAD: + * The IPv4 checksum calculated by the device did + * not match the checksum in the receive packet's + * first IPv4 header. If the receive packet + * contains both a tunnel IPv4 header and a + * transport IPv4 header, the device validates the + * checksum for both IP headers. + * + * IONIC_RXQ_COMP_CSUM_F_VLAN: + * The VLAN header was stripped and placed in @vlan_tci. + * + * IONIC_RXQ_COMP_CSUM_F_CALC: + * The checksum was calculated by the device. + * + * @pkt_type_color: Packet type and color bit; see IONIC_RXQ_COMP_PKT_TYPE_MASK */ struct ionic_rxq_comp { u8 status; @@ -870,13 +1054,21 @@ struct ionic_rxq_comp { }; enum ionic_pkt_type { - IONIC_PKT_TYPE_NON_IP = 0x000, - IONIC_PKT_TYPE_IPV4 = 0x001, - IONIC_PKT_TYPE_IPV4_TCP = 0x003, - IONIC_PKT_TYPE_IPV4_UDP = 0x005, - IONIC_PKT_TYPE_IPV6 = 0x008, - IONIC_PKT_TYPE_IPV6_TCP = 0x018, - IONIC_PKT_TYPE_IPV6_UDP = 0x028, + IONIC_PKT_TYPE_NON_IP = 0x00, + IONIC_PKT_TYPE_IPV4 = 0x01, + IONIC_PKT_TYPE_IPV4_TCP = 0x03, + IONIC_PKT_TYPE_IPV4_UDP = 0x05, + IONIC_PKT_TYPE_IPV6 = 0x08, + IONIC_PKT_TYPE_IPV6_TCP = 0x18, + IONIC_PKT_TYPE_IPV6_UDP = 0x28, + /* below types are only used if encap offloads are enabled on lif */ + IONIC_PKT_TYPE_ENCAP_NON_IP = 0x40, + IONIC_PKT_TYPE_ENCAP_IPV4 = 0x41, + IONIC_PKT_TYPE_ENCAP_IPV4_TCP = 0x43, + IONIC_PKT_TYPE_ENCAP_IPV4_UDP = 0x45, + IONIC_PKT_TYPE_ENCAP_IPV6 = 0x48, + IONIC_PKT_TYPE_ENCAP_IPV6_TCP = 0x58, + IONIC_PKT_TYPE_ENCAP_IPV6_UDP = 0x68, }; enum ionic_eth_hw_features { @@ -893,10 +1085,70 @@ enum ionic_eth_hw_features { IONIC_ETH_HW_TSO_ECN = BIT(10), IONIC_ETH_HW_TSO_GRE = BIT(11), IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12), - IONIC_ETH_HW_TSO_IPXIP4 = BIT(13), - IONIC_ETH_HW_TSO_IPXIP6 = BIT(14), + IONIC_ETH_HW_TSO_IPXIP4 = BIT(13), + IONIC_ETH_HW_TSO_IPXIP6 = BIT(14), IONIC_ETH_HW_TSO_UDP = BIT(15), IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16), + IONIC_ETH_HW_RX_CSUM_GENEVE = BIT(17), + IONIC_ETH_HW_TX_CSUM_GENEVE = BIT(18), + IONIC_ETH_HW_TSO_GENEVE = BIT(19), + IONIC_ETH_HW_TIMESTAMP = BIT(20), +}; + +/** + * enum ionic_pkt_class - Packet classification mask. + * + * Used with rx steering filter, packets indicated by the mask can be steered + * toward a specific receive queue. + * + * @IONIC_PKT_CLS_NTP_ALL: All NTP packets. + * @IONIC_PKT_CLS_PTP1_SYNC: PTPv1 sync + * @IONIC_PKT_CLS_PTP1_DREQ: PTPv1 delay-request + * @IONIC_PKT_CLS_PTP1_ALL: PTPv1 all packets + * @IONIC_PKT_CLS_PTP2_L4_SYNC: PTPv2-UDP sync + * @IONIC_PKT_CLS_PTP2_L4_DREQ: PTPv2-UDP delay-request + * @IONIC_PKT_CLS_PTP2_L4_ALL: PTPv2-UDP all packets + * @IONIC_PKT_CLS_PTP2_L2_SYNC: PTPv2-ETH sync + * @IONIC_PKT_CLS_PTP2_L2_DREQ: PTPv2-ETH delay-request + * @IONIC_PKT_CLS_PTP2_L2_ALL: PTPv2-ETH all packets + * @IONIC_PKT_CLS_PTP2_SYNC: PTPv2 sync + * @IONIC_PKT_CLS_PTP2_DREQ: PTPv2 delay-request + * @IONIC_PKT_CLS_PTP2_ALL: PTPv2 all packets + * @IONIC_PKT_CLS_PTP_SYNC: PTP sync + * @IONIC_PKT_CLS_PTP_DREQ: PTP delay-request + * @IONIC_PKT_CLS_PTP_ALL: PTP all packets + */ +enum ionic_pkt_class { + IONIC_PKT_CLS_NTP_ALL = BIT(0), + + IONIC_PKT_CLS_PTP1_SYNC = BIT(1), + IONIC_PKT_CLS_PTP1_DREQ = BIT(2), + IONIC_PKT_CLS_PTP1_ALL = BIT(3) | + IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP1_DREQ, + + IONIC_PKT_CLS_PTP2_L4_SYNC = BIT(4), + IONIC_PKT_CLS_PTP2_L4_DREQ = BIT(5), + IONIC_PKT_CLS_PTP2_L4_ALL = BIT(6) | + IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L4_DREQ, + + IONIC_PKT_CLS_PTP2_L2_SYNC = BIT(7), + IONIC_PKT_CLS_PTP2_L2_DREQ = BIT(8), + IONIC_PKT_CLS_PTP2_L2_ALL = BIT(9) | + IONIC_PKT_CLS_PTP2_L2_SYNC | IONIC_PKT_CLS_PTP2_L2_DREQ, + + IONIC_PKT_CLS_PTP2_SYNC = + IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L2_SYNC, + IONIC_PKT_CLS_PTP2_DREQ = + IONIC_PKT_CLS_PTP2_L4_DREQ | IONIC_PKT_CLS_PTP2_L2_DREQ, + IONIC_PKT_CLS_PTP2_ALL = + IONIC_PKT_CLS_PTP2_L4_ALL | IONIC_PKT_CLS_PTP2_L2_ALL, + + IONIC_PKT_CLS_PTP_SYNC = + IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP2_SYNC, + IONIC_PKT_CLS_PTP_DREQ = + IONIC_PKT_CLS_PTP1_DREQ | IONIC_PKT_CLS_PTP2_DREQ, + IONIC_PKT_CLS_PTP_ALL = + IONIC_PKT_CLS_PTP1_ALL | IONIC_PKT_CLS_PTP2_ALL, }; /** @@ -905,7 +1157,7 @@ enum ionic_eth_hw_features { * @type: Queue type * @lif_index: LIF index * @index: Queue index - * @oper: Operation (enum q_control_oper) + * @oper: Operation (enum ionic_q_control_oper) */ struct ionic_q_control_cmd { u8 opcode; @@ -925,7 +1177,10 @@ enum q_control_oper { }; /** - * Physical connection type + * enum ionic_phy_type - Physical connection type + * @IONIC_PHY_TYPE_NONE: No PHY installed + * @IONIC_PHY_TYPE_COPPER: Copper PHY + * @IONIC_PHY_TYPE_FIBER: Fiber PHY */ enum ionic_phy_type { IONIC_PHY_TYPE_NONE = 0, @@ -934,18 +1189,23 @@ enum ionic_phy_type { }; /** - * Transceiver status + * enum ionic_xcvr_state - Transceiver status + * @IONIC_XCVR_STATE_REMOVED: Transceiver removed + * @IONIC_XCVR_STATE_INSERTED: Transceiver inserted + * @IONIC_XCVR_STATE_PENDING: Transceiver pending + * @IONIC_XCVR_STATE_SPROM_READ: Transceiver data read + * @IONIC_XCVR_STATE_SPROM_READ_ERR: Transceiver data read error */ enum ionic_xcvr_state { IONIC_XCVR_STATE_REMOVED = 0, IONIC_XCVR_STATE_INSERTED = 1, IONIC_XCVR_STATE_PENDING = 2, IONIC_XCVR_STATE_SPROM_READ = 3, - IONIC_XCVR_STATE_SPROM_READ_ERR = 4, + IONIC_XCVR_STATE_SPROM_READ_ERR = 4, }; /** - * Supported link modes + * enum ionic_xcvr_pid - Supported link modes */ enum ionic_xcvr_pid { IONIC_XCVR_PID_UNKNOWN = 0, @@ -979,67 +1239,88 @@ enum ionic_xcvr_pid { IONIC_XCVR_PID_SFP_10GBASE_CU = 68, IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69, IONIC_XCVR_PID_QSFP_100G_PSM4 = 70, + IONIC_XCVR_PID_SFP_25GBASE_ACC = 71, + IONIC_XCVR_PID_SFP_10GBASE_T = 72, + IONIC_XCVR_PID_SFP_1000BASE_T = 73, }; /** - * Port types + * enum ionic_port_type - Port types + * @IONIC_PORT_TYPE_NONE: Port type not configured + * @IONIC_PORT_TYPE_ETH: Port carries ethernet traffic (inband) + * @IONIC_PORT_TYPE_MGMT: Port carries mgmt traffic (out-of-band) */ enum ionic_port_type { - IONIC_PORT_TYPE_NONE = 0, /* port type not configured */ - IONIC_PORT_TYPE_ETH = 1, /* port carries ethernet traffic (inband) */ - IONIC_PORT_TYPE_MGMT = 2, /* port carries mgmt traffic (out-of-band) */ + IONIC_PORT_TYPE_NONE = 0, + IONIC_PORT_TYPE_ETH = 1, + IONIC_PORT_TYPE_MGMT = 2, }; /** - * Port config state + * enum ionic_port_admin_state - Port config state + * @IONIC_PORT_ADMIN_STATE_NONE: Port admin state not configured + * @IONIC_PORT_ADMIN_STATE_DOWN: Port admin disabled + * @IONIC_PORT_ADMIN_STATE_UP: Port admin enabled */ enum ionic_port_admin_state { - IONIC_PORT_ADMIN_STATE_NONE = 0, /* port admin state not configured */ - IONIC_PORT_ADMIN_STATE_DOWN = 1, /* port is admin disabled */ - IONIC_PORT_ADMIN_STATE_UP = 2, /* port is admin enabled */ + IONIC_PORT_ADMIN_STATE_NONE = 0, + IONIC_PORT_ADMIN_STATE_DOWN = 1, + IONIC_PORT_ADMIN_STATE_UP = 2, }; /** - * Port operational status + * enum ionic_port_oper_status - Port operational status + * @IONIC_PORT_OPER_STATUS_NONE: Port disabled + * @IONIC_PORT_OPER_STATUS_UP: Port link status up + * @IONIC_PORT_OPER_STATUS_DOWN: Port link status down */ enum ionic_port_oper_status { - IONIC_PORT_OPER_STATUS_NONE = 0, /* port is disabled */ - IONIC_PORT_OPER_STATUS_UP = 1, /* port is linked up */ - IONIC_PORT_OPER_STATUS_DOWN = 2, /* port link status is down */ + IONIC_PORT_OPER_STATUS_NONE = 0, + IONIC_PORT_OPER_STATUS_UP = 1, + IONIC_PORT_OPER_STATUS_DOWN = 2, }; /** - * Ethernet Forward error correction (fec) modes + * enum ionic_port_fec_type - Ethernet Forward error correction (FEC) modes + * @IONIC_PORT_FEC_TYPE_NONE: FEC Disabled + * @IONIC_PORT_FEC_TYPE_FC: FireCode FEC + * @IONIC_PORT_FEC_TYPE_RS: ReedSolomon FEC */ enum ionic_port_fec_type { - IONIC_PORT_FEC_TYPE_NONE = 0, /* Disabled */ - IONIC_PORT_FEC_TYPE_FC = 1, /* FireCode */ - IONIC_PORT_FEC_TYPE_RS = 2, /* ReedSolomon */ + IONIC_PORT_FEC_TYPE_NONE = 0, + IONIC_PORT_FEC_TYPE_FC = 1, + IONIC_PORT_FEC_TYPE_RS = 2, }; /** - * Ethernet pause (flow control) modes + * enum ionic_port_pause_type - Ethernet pause (flow control) modes + * @IONIC_PORT_PAUSE_TYPE_NONE: Disable Pause + * @IONIC_PORT_PAUSE_TYPE_LINK: Link level pause + * @IONIC_PORT_PAUSE_TYPE_PFC: Priority-Flow Control */ enum ionic_port_pause_type { - IONIC_PORT_PAUSE_TYPE_NONE = 0, /* Disable Pause */ - IONIC_PORT_PAUSE_TYPE_LINK = 1, /* Link level pause */ - IONIC_PORT_PAUSE_TYPE_PFC = 2, /* Priority-Flow control */ + IONIC_PORT_PAUSE_TYPE_NONE = 0, + IONIC_PORT_PAUSE_TYPE_LINK = 1, + IONIC_PORT_PAUSE_TYPE_PFC = 2, }; /** - * Loopback modes + * enum ionic_port_loopback_mode - Loopback modes + * @IONIC_PORT_LOOPBACK_MODE_NONE: Disable loopback + * @IONIC_PORT_LOOPBACK_MODE_MAC: MAC loopback + * @IONIC_PORT_LOOPBACK_MODE_PHY: PHY/SerDes loopback */ enum ionic_port_loopback_mode { - IONIC_PORT_LOOPBACK_MODE_NONE = 0, /* Disable loopback */ - IONIC_PORT_LOOPBACK_MODE_MAC = 1, /* MAC loopback */ - IONIC_PORT_LOOPBACK_MODE_PHY = 2, /* PHY/Serdes loopback */ + IONIC_PORT_LOOPBACK_MODE_NONE = 0, + IONIC_PORT_LOOPBACK_MODE_MAC = 1, + IONIC_PORT_LOOPBACK_MODE_PHY = 2, }; /** - * Transceiver Status information + * struct ionic_xcvr_status - Transceiver Status information * @state: Transceiver status (enum ionic_xcvr_state) * @phy: Physical connection type (enum ionic_phy_type) - * @pid: Transceiver link mode (enum pid) + * @pid: Transceiver link mode (enum ionic_xcvr_pid) * @sprom: Transceiver sprom contents */ struct ionic_xcvr_status { @@ -1050,10 +1331,10 @@ struct ionic_xcvr_status { }; /** - * Port configuration + * union ionic_port_config - Port configuration * @speed: port speed (in Mbps) * @mtu: mtu - * @state: port admin state (enum port_admin_state) + * @state: port admin state (enum ionic_port_admin_state) * @an_enable: autoneg enable * @fec_type: fec type (enum ionic_port_fec_type) * @pause_type: pause type (enum ionic_port_pause_type) @@ -1083,19 +1364,23 @@ union ionic_port_config { }; /** - * Port Status information + * struct ionic_port_status - Port Status information * @status: link status (enum ionic_port_oper_status) * @id: port id * @speed: link speed (in Mbps) - * @xcvr: tranceiver status + * @link_down_count: number of times link went from up to down + * @fec_type: fec type (enum ionic_port_fec_type) + * @xcvr: transceiver status */ struct ionic_port_status { __le32 id; __le32 speed; u8 status; - u8 rsvd[51]; + __le16 link_down_count; + u8 fec_type; + u8 rsvd[48]; struct ionic_xcvr_status xcvr; -}; +} __packed; /** * struct ionic_port_identify_cmd - Port identify command @@ -1112,7 +1397,7 @@ struct ionic_port_identify_cmd { /** * struct ionic_port_identify_comp - Port identify command completion - * @status: The status of the command (enum status_code) + * @status: Status of the command (enum ionic_status_code) * @ver: Version of identify returned by device */ struct ionic_port_identify_comp { @@ -1137,7 +1422,7 @@ struct ionic_port_init_cmd { /** * struct ionic_port_init_comp - Port initialization command completion - * @status: The status of the command (enum status_code) + * @status: Status of the command (enum ionic_status_code) */ struct ionic_port_init_comp { u8 status; @@ -1157,7 +1442,7 @@ struct ionic_port_reset_cmd { /** * struct ionic_port_reset_comp - Port reset command completion - * @status: The status of the command (enum status_code) + * @status: Status of the command (enum ionic_status_code) */ struct ionic_port_reset_comp { u8 status; @@ -1165,15 +1450,37 @@ struct ionic_port_reset_comp { }; /** - * enum stats_ctl_cmd - List of commands for stats control + * enum ionic_stats_ctl_cmd - List of commands for stats control + * @IONIC_STATS_CTL_RESET: Reset statistics */ enum ionic_stats_ctl_cmd { IONIC_STATS_CTL_RESET = 0, }; +/** + * enum ionic_txstamp_mode - List of TX Timestamping Modes + * @IONIC_TXSTAMP_OFF: Disable TX hardware timetamping. + * @IONIC_TXSTAMP_ON: Enable local TX hardware timetamping. + * @IONIC_TXSTAMP_ONESTEP_SYNC: Modify TX PTP Sync packets. + * @IONIC_TXSTAMP_ONESTEP_P2P: Modify TX PTP Sync and PDelayResp. + */ +enum ionic_txstamp_mode { + IONIC_TXSTAMP_OFF = 0, + IONIC_TXSTAMP_ON = 1, + IONIC_TXSTAMP_ONESTEP_SYNC = 2, + IONIC_TXSTAMP_ONESTEP_P2P = 3, +}; /** * enum ionic_port_attr - List of device attributes + * @IONIC_PORT_ATTR_STATE: Port state attribute + * @IONIC_PORT_ATTR_SPEED: Port speed attribute + * @IONIC_PORT_ATTR_MTU: Port MTU attribute + * @IONIC_PORT_ATTR_AUTONEG: Port autonegotiation attribute + * @IONIC_PORT_ATTR_FEC: Port FEC attribute + * @IONIC_PORT_ATTR_PAUSE: Port pause attribute + * @IONIC_PORT_ATTR_LOOPBACK: Port loopback attribute + * @IONIC_PORT_ATTR_STATS_CTRL: Port statistics control attribute */ enum ionic_port_attr { IONIC_PORT_ATTR_STATE = 0, @@ -1188,9 +1495,17 @@ enum ionic_port_attr { /** * struct ionic_port_setattr_cmd - Set port attributes on the NIC - * @opcode: Opcode - * @index: port index - * @attr: Attribute type (enum ionic_port_attr) + * @opcode: Opcode + * @index: Port index + * @attr: Attribute type (enum ionic_port_attr) + * @state: Port state + * @speed: Port speed + * @mtu: Port MTU + * @an_enable: Port autonegotiation setting + * @fec_type: Port FEC type setting + * @pause_type: Port pause type setting + * @loopback_mode: Port loopback mode + * @stats_ctl: Port stats setting */ struct ionic_port_setattr_cmd { u8 opcode; @@ -1205,14 +1520,14 @@ struct ionic_port_setattr_cmd { u8 fec_type; u8 pause_type; u8 loopback_mode; - u8 stats_ctl; + u8 stats_ctl; u8 rsvd2[60]; }; }; /** * struct ionic_port_setattr_comp - Port set attr command completion - * @status: The status of the command (enum status_code) + * @status: Status of the command (enum ionic_status_code) * @color: Color bit */ struct ionic_port_setattr_comp { @@ -1236,8 +1551,15 @@ struct ionic_port_getattr_cmd { /** * struct ionic_port_getattr_comp - Port get attr command completion - * @status: The status of the command (enum status_code) - * @color: Color bit + * @status: Status of the command (enum ionic_status_code) + * @state: Port state + * @speed: Port speed + * @mtu: Port MTU + * @an_enable: Port autonegotiation setting + * @fec_type: Port FEC type setting + * @pause_type: Port pause type setting + * @loopback_mode: Port loopback mode + * @color: Color bit */ struct ionic_port_getattr_comp { u8 status; @@ -1251,17 +1573,17 @@ struct ionic_port_getattr_comp { u8 pause_type; u8 loopback_mode; u8 rsvd2[11]; - }; + } __packed; u8 color; }; /** - * struct ionic_lif_status - Lif status register + * struct ionic_lif_status - LIF status register * @eid: most recent NotifyQ event id - * @port_num: port the lif is connected to + * @port_num: port the LIF is connected to * @link_status: port status (enum ionic_port_oper_status) * @link_speed: speed of link in Mbps - * @link_down_count: number of times link status changes + * @link_down_count: number of times link went from up to down */ struct ionic_lif_status { __le64 eid; @@ -1295,6 +1617,9 @@ enum ionic_dev_state { /** * enum ionic_dev_attr - List of device attributes + * @IONIC_DEV_ATTR_STATE: Device state attribute + * @IONIC_DEV_ATTR_NAME: Device name attribute + * @IONIC_DEV_ATTR_FEATURES: Device feature attributes */ enum ionic_dev_attr { IONIC_DEV_ATTR_STATE = 0, @@ -1319,12 +1644,12 @@ struct ionic_dev_setattr_cmd { char name[IONIC_IFNAMSIZ]; __le64 features; u8 rsvd2[60]; - }; + } __packed; }; /** * struct ionic_dev_setattr_comp - Device set attr command completion - * @status: The status of the command (enum status_code) + * @status: Status of the command (enum ionic_status_code) * @features: Device features * @color: Color bit */ @@ -1334,7 +1659,7 @@ struct ionic_dev_setattr_comp { union { __le64 features; u8 rsvd2[11]; - }; + } __packed; u8 color; }; @@ -1351,7 +1676,7 @@ struct ionic_dev_getattr_cmd { /** * struct ionic_dev_setattr_comp - Device set attr command completion - * @status: The status of the command (enum status_code) + * @status: Status of the command (enum ionic_status_code) * @features: Device features * @color: Color bit */ @@ -1361,7 +1686,7 @@ struct ionic_dev_getattr_comp { union { __le64 features; u8 rsvd2[11]; - }; + } __packed; u8 color; }; @@ -1381,6 +1706,14 @@ enum ionic_rss_hash_types { /** * enum ionic_lif_attr - List of LIF attributes + * @IONIC_LIF_ATTR_STATE: LIF state attribute + * @IONIC_LIF_ATTR_NAME: LIF name attribute + * @IONIC_LIF_ATTR_MTU: LIF MTU attribute + * @IONIC_LIF_ATTR_MAC: LIF MAC attribute + * @IONIC_LIF_ATTR_FEATURES: LIF features attribute + * @IONIC_LIF_ATTR_RSS: LIF RSS attribute + * @IONIC_LIF_ATTR_STATS_CTRL: LIF statistics control attribute + * @IONIC_LIF_ATTR_TXSTAMP: LIF TX timestamping mode */ enum ionic_lif_attr { IONIC_LIF_ATTR_STATE = 0, @@ -1390,23 +1723,25 @@ enum ionic_lif_attr { IONIC_LIF_ATTR_FEATURES = 4, IONIC_LIF_ATTR_RSS = 5, IONIC_LIF_ATTR_STATS_CTRL = 6, + IONIC_LIF_ATTR_TXSTAMP = 7, }; /** * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC * @opcode: Opcode - * @type: Attribute type (enum ionic_lif_attr) + * @attr: Attribute type (enum ionic_lif_attr) * @index: LIF index - * @state: lif state (enum lif_state) + * @state: LIF state (enum ionic_lif_state) * @name: The netdev name string, 0 terminated * @mtu: Mtu * @mac: Station mac * @features: Features (enum ionic_eth_hw_features) * @rss: RSS properties - * @types: The hash types to enable (see rss_hash_types). - * @key: The hash secret key. - * @addr: Address for the indirection table shared memory. - * @stats_ctl: stats control commands (enum stats_ctl_cmd) + * @types: The hash types to enable (see rss_hash_types) + * @key: The hash secret key + * @addr: Address for the indirection table shared memory + * @stats_ctl: stats control commands (enum ionic_stats_ctl_cmd) + * @txstamp: TX Timestamping Mode (enum ionic_txstamp_mode) */ struct ionic_lif_setattr_cmd { u8 opcode; @@ -1424,16 +1759,16 @@ struct ionic_lif_setattr_cmd { u8 rsvd[6]; __le64 addr; } rss; - u8 stats_ctl; + u8 stats_ctl; + __le16 txstamp_mode; u8 rsvd[60]; - }; + } __packed; }; /** * struct ionic_lif_setattr_comp - LIF set attr command completion - * @status: The status of the command (enum status_code) - * @comp_index: The index in the descriptor ring for which this - * is the completion. + * @status: Status of the command (enum ionic_status_code) + * @comp_index: Index in the descriptor ring for which this is the completion * @features: features (enum ionic_eth_hw_features) * @color: Color bit */ @@ -1444,7 +1779,7 @@ struct ionic_lif_setattr_comp { union { __le64 features; u8 rsvd2[11]; - }; + } __packed; u8 color; }; @@ -1463,14 +1798,14 @@ struct ionic_lif_getattr_cmd { /** * struct ionic_lif_getattr_comp - LIF get attr command completion - * @status: The status of the command (enum status_code) - * @comp_index: The index in the descriptor ring for which this - * is the completion. - * @state: lif state (enum lif_state) + * @status: Status of the command (enum ionic_status_code) + * @comp_index: Index in the descriptor ring for which this is the completion + * @state: LIF state (enum ionic_lif_state) * @name: The netdev name string, 0 terminated * @mtu: Mtu * @mac: Station mac * @features: Features (enum ionic_eth_hw_features) + * @txstamp: TX Timestamping Mode (enum ionic_txstamp_mode) * @color: Color bit */ struct ionic_lif_getattr_comp { @@ -1482,17 +1817,42 @@ struct ionic_lif_getattr_comp { __le32 mtu; u8 mac[6]; __le64 features; + __le16 txstamp_mode; u8 rsvd2[11]; - }; + } __packed; u8 color; }; +/** + * struct ionic_lif_setphc_cmd - Set LIF PTP Hardware Clock + * @opcode: Opcode + * @lif_index: LIF index + * @tick: Hardware stamp tick of an instant in time. + * @nsec: Nanosecond stamp of the same instant. + * @frac: Fractional nanoseconds at the same instant. + * @mult: Cycle to nanosecond multiplier. + * @shift: Cycle to nanosecond divisor (power of two). + */ +struct ionic_lif_setphc_cmd { + u8 opcode; + u8 rsvd1; + __le16 lif_index; + u8 rsvd2[4]; + __le64 tick; + __le64 nsec; + __le64 frac; + __le32 mult; + __le32 shift; + u8 rsvd3[24]; +}; + enum ionic_rx_mode { - IONIC_RX_MODE_F_UNICAST = BIT(0), - IONIC_RX_MODE_F_MULTICAST = BIT(1), - IONIC_RX_MODE_F_BROADCAST = BIT(2), - IONIC_RX_MODE_F_PROMISC = BIT(3), - IONIC_RX_MODE_F_ALLMULTI = BIT(4), + IONIC_RX_MODE_F_UNICAST = BIT(0), + IONIC_RX_MODE_F_MULTICAST = BIT(1), + IONIC_RX_MODE_F_BROADCAST = BIT(2), + IONIC_RX_MODE_F_PROMISC = BIT(3), + IONIC_RX_MODE_F_ALLMULTI = BIT(4), + IONIC_RX_MODE_F_RDMA_SNIFFER = BIT(5), }; /** @@ -1500,11 +1860,12 @@ enum ionic_rx_mode { * @opcode: opcode * @lif_index: LIF index * @rx_mode: Rx mode flags: - * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets. - * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets. - * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets. - * IONIC_RX_MODE_F_PROMISC: Accept any packets. - * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets. + * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets + * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets + * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets + * IONIC_RX_MODE_F_PROMISC: Accept any packets + * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets + * IONIC_RX_MODE_F_RDMA_SNIFFER: Sniff RDMA packets */ struct ionic_rx_mode_set_cmd { u8 opcode; @@ -1517,9 +1878,10 @@ struct ionic_rx_mode_set_cmd { typedef struct ionic_admin_comp ionic_rx_mode_set_comp; enum ionic_rx_filter_match_type { - IONIC_RX_FILTER_MATCH_VLAN = 0, - IONIC_RX_FILTER_MATCH_MAC, - IONIC_RX_FILTER_MATCH_MAC_VLAN, + IONIC_RX_FILTER_MATCH_VLAN = 0x0, + IONIC_RX_FILTER_MATCH_MAC = 0x1, + IONIC_RX_FILTER_MATCH_MAC_VLAN = 0x2, + IONIC_RX_FILTER_STEER_PKTCLASS = 0x10, }; /** @@ -1528,9 +1890,15 @@ enum ionic_rx_filter_match_type { * @qtype: Queue type * @lif_index: LIF index * @qid: Queue ID - * @match: Rx filter match type. (See IONIC_RX_FILTER_MATCH_xxx) - * @vlan: VLAN ID - * @addr: MAC address (network-byte order) + * @match: Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx) + * @vlan: VLAN filter + * @vlan: VLAN ID + * @mac: MAC filter + * @addr: MAC address (network-byte order) + * @mac_vlan: MACVLAN filter + * @vlan: VLAN ID + * @addr: MAC address (network-byte order) + * @pkt_class: Packet classification filter */ struct ionic_rx_filter_add_cmd { u8 opcode; @@ -1549,17 +1917,17 @@ struct ionic_rx_filter_add_cmd { __le16 vlan; u8 addr[6]; } mac_vlan; + __le64 pkt_class; u8 rsvd[54]; - }; + } __packed; }; /** * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion - * @status: The status of the command (enum status_code) - * @comp_index: The index in the descriptor ring for which this - * is the completion. + * @status: Status of the command (enum ionic_status_code) + * @comp_index: Index in the descriptor ring for which this is the completion * @filter_id: Filter ID - * @color: Color bit. + * @color: Color bit */ struct ionic_rx_filter_add_comp { u8 status; @@ -1586,63 +1954,6 @@ struct ionic_rx_filter_del_cmd { typedef struct ionic_admin_comp ionic_rx_filter_del_comp; -/** - * struct ionic_qos_identify_cmd - QoS identify command - * @opcode: opcode - * @ver: Highest version of identify supported by driver - * - */ -struct ionic_qos_identify_cmd { - u8 opcode; - u8 ver; - u8 rsvd[62]; -}; - -/** - * struct ionic_qos_identify_comp - QoS identify command completion - * @status: The status of the command (enum status_code) - * @ver: Version of identify returned by device - */ -struct ionic_qos_identify_comp { - u8 status; - u8 ver; - u8 rsvd[14]; -}; - -#define IONIC_QOS_CLASS_MAX 7 -#define IONIC_QOS_CLASS_NAME_SZ 32 -#define IONIC_QOS_DSCP_MAX_VALUES 64 - -/** - * enum ionic_qos_class - */ -enum ionic_qos_class { - IONIC_QOS_CLASS_DEFAULT = 0, - IONIC_QOS_CLASS_USER_DEFINED_1 = 1, - IONIC_QOS_CLASS_USER_DEFINED_2 = 2, - IONIC_QOS_CLASS_USER_DEFINED_3 = 3, - IONIC_QOS_CLASS_USER_DEFINED_4 = 4, - IONIC_QOS_CLASS_USER_DEFINED_5 = 5, - IONIC_QOS_CLASS_USER_DEFINED_6 = 6, -}; - -/** - * enum ionic_qos_class_type - Traffic classification criteria - */ -enum ionic_qos_class_type { - IONIC_QOS_CLASS_TYPE_NONE = 0, - IONIC_QOS_CLASS_TYPE_PCP = 1, /* Dot1Q pcp */ - IONIC_QOS_CLASS_TYPE_DSCP = 2, /* IP dscp */ -}; - -/** - * enum ionic_qos_sched_type - Qos class scheduling type - */ -enum ionic_qos_sched_type { - IONIC_QOS_SCHED_TYPE_STRICT = 0, /* Strict priority */ - IONIC_QOS_SCHED_TYPE_DWRR = 1, /* Deficit weighted round-robin */ -}; - enum ionic_vf_attr { IONIC_VF_ATTR_SPOOFCHK = 1, IONIC_VF_ATTR_TRUST = 2, @@ -1654,26 +1965,29 @@ enum ionic_vf_attr { }; /** - * VF link status + * enum ionic_vf_link_status - Virtual Function link status + * @IONIC_VF_LINK_STATUS_AUTO: Use link state of the uplink + * @IONIC_VF_LINK_STATUS_UP: Link always up + * @IONIC_VF_LINK_STATUS_DOWN: Link always down */ enum ionic_vf_link_status { - IONIC_VF_LINK_STATUS_AUTO = 0, /* link state of the uplink */ - IONIC_VF_LINK_STATUS_UP = 1, /* link is always up */ - IONIC_VF_LINK_STATUS_DOWN = 2, /* link is always down */ + IONIC_VF_LINK_STATUS_AUTO = 0, + IONIC_VF_LINK_STATUS_UP = 1, + IONIC_VF_LINK_STATUS_DOWN = 2, }; /** * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC * @opcode: Opcode - * @index: VF index * @attr: Attribute type (enum ionic_vf_attr) - * macaddr mac address - * vlanid vlan ID - * maxrate max Tx rate in Mbps - * spoofchk enable address spoof checking - * trust enable VF trust - * linkstate set link up or down - * stats_pa set DMA address for VF stats + * @vf_index: VF index + * @macaddr: mac address + * @vlanid: vlan ID + * @maxrate: max Tx rate in Mbps + * @spoofchk: enable address spoof checking + * @trust: enable VF trust + * @linkstate: set link up or down + * @stats_pa: set DMA address for VF stats */ struct ionic_vf_setattr_cmd { u8 opcode; @@ -1688,7 +2002,7 @@ struct ionic_vf_setattr_cmd { u8 linkstate; __le64 stats_pa; u8 pad[60]; - }; + } __packed; }; struct ionic_vf_setattr_comp { @@ -1703,8 +2017,8 @@ struct ionic_vf_setattr_comp { /** * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC * @opcode: Opcode - * @index: VF index * @attr: Attribute type (enum ionic_vf_attr) + * @vf_index: VF index */ struct ionic_vf_getattr_cmd { u8 opcode; @@ -1726,27 +2040,96 @@ struct ionic_vf_getattr_comp { u8 linkstate; __le64 stats_pa; u8 pad[11]; - }; + } __packed; u8 color; }; /** - * union ionic_qos_config - Qos configuration structure + * struct ionic_qos_identify_cmd - QoS identify command + * @opcode: opcode + * @ver: Highest version of identify supported by driver + * + */ +struct ionic_qos_identify_cmd { + u8 opcode; + u8 ver; + u8 rsvd[62]; +}; + +/** + * struct ionic_qos_identify_comp - QoS identify command completion + * @status: Status of the command (enum ionic_status_code) + * @ver: Version of identify returned by device + */ +struct ionic_qos_identify_comp { + u8 status; + u8 ver; + u8 rsvd[14]; +}; + +#define IONIC_QOS_TC_MAX 8 +#define IONIC_QOS_ALL_TC 0xFF +/* Capri max supported, should be renamed. */ +#define IONIC_QOS_CLASS_MAX 7 +#define IONIC_QOS_PCP_MAX 8 +#define IONIC_QOS_CLASS_NAME_SZ 32 +#define IONIC_QOS_DSCP_MAX 64 +#define IONIC_QOS_ALL_PCP 0xFF +#define IONIC_DSCP_BLOCK_SIZE 8 + +/** + * enum ionic_qos_class + */ +enum ionic_qos_class { + IONIC_QOS_CLASS_DEFAULT = 0, + IONIC_QOS_CLASS_USER_DEFINED_1 = 1, + IONIC_QOS_CLASS_USER_DEFINED_2 = 2, + IONIC_QOS_CLASS_USER_DEFINED_3 = 3, + IONIC_QOS_CLASS_USER_DEFINED_4 = 4, + IONIC_QOS_CLASS_USER_DEFINED_5 = 5, + IONIC_QOS_CLASS_USER_DEFINED_6 = 6, +}; + +/** + * enum ionic_qos_class_type - Traffic classification criteria + * @IONIC_QOS_CLASS_TYPE_NONE: No QoS + * @IONIC_QOS_CLASS_TYPE_PCP: Dot1Q PCP + * @IONIC_QOS_CLASS_TYPE_DSCP: IP DSCP + */ +enum ionic_qos_class_type { + IONIC_QOS_CLASS_TYPE_NONE = 0, + IONIC_QOS_CLASS_TYPE_PCP = 1, + IONIC_QOS_CLASS_TYPE_DSCP = 2, +}; + +/** + * enum ionic_qos_sched_type - QoS class scheduling type + * @IONIC_QOS_SCHED_TYPE_STRICT: Strict priority + * @IONIC_QOS_SCHED_TYPE_DWRR: Deficit weighted round-robin + */ +enum ionic_qos_sched_type { + IONIC_QOS_SCHED_TYPE_STRICT = 0, + IONIC_QOS_SCHED_TYPE_DWRR = 1, +}; + +/** + * union ionic_qos_config - QoS configuration structure * @flags: Configuration flags * IONIC_QOS_CONFIG_F_ENABLE enable - * IONIC_QOS_CONFIG_F_DROP drop/nodrop + * IONIC_QOS_CONFIG_F_NO_DROP drop/nodrop * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite - * @sched_type: Qos class scheduling type (enum ionic_qos_sched_type) - * @class_type: Qos class type (enum ionic_qos_class_type) - * @pause_type: Qos pause type (enum ionic_qos_pause_type) - * @name: Qos class name + * IONIC_QOS_CONFIG_F_NON_DISRUPTIVE Non-disruptive TC update + * @sched_type: QoS class scheduling type (enum ionic_qos_sched_type) + * @class_type: QoS class type (enum ionic_qos_class_type) + * @pause_type: QoS pause type (enum ionic_qos_pause_type) + * @name: QoS class name * @mtu: MTU of the class - * @pfc_dot1q_pcp: Pcp value for pause frames (valid iff F_NODROP) - * @dwrr_weight: Qos class scheduling weight + * @pfc_cos: Priority-Flow Control class of service + * @dwrr_weight: QoS class scheduling weight * @strict_rlmt: Rate limit for strict priority scheduling - * @rw_dot1q_pcp: Rewrite dot1q pcp to this value (valid iff F_RW_DOT1Q_PCP) - * @rw_ip_dscp: Rewrite ip dscp to this value (valid iff F_RW_IP_DSCP) + * @rw_dot1q_pcp: Rewrite dot1q pcp to value (valid iff F_RW_DOT1Q_PCP) + * @rw_ip_dscp: Rewrite ip dscp to value (valid iff F_RW_IP_DSCP) * @dot1q_pcp: Dot1q pcp value * @ndscp: Number of valid dscp values in the ip_dscp field * @ip_dscp: IP dscp values @@ -1754,9 +2137,12 @@ struct ionic_vf_getattr_comp { union ionic_qos_config { struct { #define IONIC_QOS_CONFIG_F_ENABLE BIT(0) -#define IONIC_QOS_CONFIG_F_DROP BIT(1) +#define IONIC_QOS_CONFIG_F_NO_DROP BIT(1) +/* Used to rewrite PCP or DSCP value. */ #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2) #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3) +/* Non-disruptive TC update */ +#define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE BIT(4) u8 flags; u8 sched_type; u8 class_type; @@ -1771,6 +2157,7 @@ union ionic_qos_config { __le64 strict_rlmt; }; /* marking */ + /* Used to rewrite PCP or DSCP value. */ union { u8 rw_dot1q_pcp; u8 rw_ip_dscp; @@ -1780,7 +2167,7 @@ union ionic_qos_config { u8 dot1q_pcp; struct { u8 ndscp; - u8 ip_dscp[IONIC_QOS_DSCP_MAX_VALUES]; + u8 ip_dscp[IONIC_QOS_DSCP_MAX]; }; }; }; @@ -1799,15 +2186,15 @@ union ionic_qos_identity { u8 version; u8 type; u8 rsvd[62]; - union ionic_qos_config config[IONIC_QOS_CLASS_MAX]; + union ionic_qos_config config[IONIC_QOS_CLASS_MAX]; }; - __le32 words[512]; + __le32 words[478]; }; /** - * struct qos_init_cmd - QoS config init command + * struct ionic_qos_init_cmd - QoS config init command * @opcode: Opcode - * @group: Qos class id + * @group: QoS class id * @info_pa: destination address for qos info */ struct ionic_qos_init_cmd { @@ -1821,8 +2208,9 @@ struct ionic_qos_init_cmd { typedef struct ionic_admin_comp ionic_qos_init_comp; /** - * struct ionic_qos_reset_cmd - Qos config reset command + * struct ionic_qos_reset_cmd - QoS config reset command * @opcode: Opcode + * @group: QoS class id */ struct ionic_qos_reset_cmd { u8 opcode; @@ -1830,6 +2218,16 @@ struct ionic_qos_reset_cmd { u8 rsvd[62]; }; +/** + * struct ionic_qos_clear_port_stats_cmd - Qos config reset command + * @opcode: Opcode + */ +struct ionic_qos_clear_stats_cmd { + u8 opcode; + u8 group_bitmap; + u8 rsvd[62]; +}; + typedef struct ionic_admin_comp ionic_qos_reset_comp; /** @@ -1849,10 +2247,25 @@ struct ionic_fw_download_cmd { typedef struct ionic_admin_comp ionic_fw_download_comp; +/** + * enum ionic_fw_control_oper - FW control operations + * @IONIC_FW_RESET: Reset firmware + * @IONIC_FW_INSTALL: Install firmware + * @IONIC_FW_ACTIVATE: Activate firmware + * @IONIC_FW_INSTALL_ASYNC: Install firmware asynchronously + * @IONIC_FW_INSTALL_STATUS: Firmware installation status + * @IONIC_FW_ACTIVATE_ASYNC: Activate firmware asynchronously + * @IONIC_FW_ACTIVATE_STATUS: Firmware activate status + */ enum ionic_fw_control_oper { - IONIC_FW_RESET = 0, /* Reset firmware */ - IONIC_FW_INSTALL = 1, /* Install firmware */ - IONIC_FW_ACTIVATE = 2, /* Activate firmware */ + IONIC_FW_RESET = 0, + IONIC_FW_INSTALL = 1, + IONIC_FW_ACTIVATE = 2, + IONIC_FW_INSTALL_ASYNC = 3, + IONIC_FW_INSTALL_STATUS = 4, + IONIC_FW_ACTIVATE_ASYNC = 5, + IONIC_FW_ACTIVATE_STATUS = 6, + IONIC_FW_UPDATE_CLEANUP = 7, }; /** @@ -1871,8 +2284,10 @@ struct ionic_fw_control_cmd { /** * struct ionic_fw_control_comp - Firmware control copletion - * @opcode: opcode - * @slot: slot where the firmware was installed + * @status: Status of the command (enum ionic_status_code) + * @comp_index: Index in the descriptor ring for which this is the completion + * @slot: Slot where the firmware was installed + * @color: Color bit */ struct ionic_fw_control_comp { u8 status; @@ -1890,11 +2305,11 @@ struct ionic_fw_control_comp { /** * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd * @opcode: opcode - * @lif_index: lif index + * @lif_index: LIF index * - * There is no rdma specific dev command completion struct. Completion uses + * There is no RDMA specific dev command completion struct. Completion uses * the common struct ionic_admin_comp. Only the status is indicated. - * Nonzero status means the LIF does not support rdma. + * Nonzero status means the LIF does not support RDMA. **/ struct ionic_rdma_reset_cmd { u8 opcode; @@ -1906,30 +2321,29 @@ struct ionic_rdma_reset_cmd { /** * struct ionic_rdma_queue_cmd - Create RDMA Queue command * @opcode: opcode, 52, 53 - * @lif_index lif index - * @qid_ver: (qid | (rdma version << 24)) + * @lif_index: LIF index + * @qid_ver: (qid | (RDMA version << 24)) * @cid: intr, eq_id, or cq_id * @dbid: doorbell page id * @depth_log2: log base two of queue depth * @stride_log2: log base two of queue stride * @dma_addr: address of the queue memory - * @xxx_table_index: temporary, but should not need pgtbl for contig. queues. * - * The same command struct is used to create an rdma event queue, completion - * queue, or rdma admin queue. The cid is an interrupt number for an event + * The same command struct is used to create an RDMA event queue, completion + * queue, or RDMA admin queue. The cid is an interrupt number for an event * queue, an event queue id for a completion queue, or a completion queue id - * for an rdma admin queue. + * for an RDMA admin queue. * * The queue created via a dev command must be contiguous in dma space. * * The dev commands are intended only to be used during driver initialization, - * to create queues supporting the rdma admin queue. Other queues, and other - * types of rdma resources like memory regions, will be created and registered - * via the rdma admin queue, and will support a more complete interface + * to create queues supporting the RDMA admin queue. Other queues, and other + * types of RDMA resources like memory regions, will be created and registered + * via the RDMA admin queue, and will support a more complete interface * providing scatter gather lists for larger, scattered queue buffers and * memory registration. * - * There is no rdma specific dev command completion struct. Completion uses + * There is no RDMA specific dev command completion struct. Completion uses * the common struct ionic_admin_comp. Only the status is indicated. **/ struct ionic_rdma_queue_cmd { @@ -1942,8 +2356,7 @@ struct ionic_rdma_queue_cmd { u8 depth_log2; u8 stride_log2; __le64 dma_addr; - u8 rsvd2[36]; - __le32 xxx_table_index; + u8 rsvd2[40]; }; /****************************************************************** @@ -1951,7 +2364,7 @@ struct ionic_rdma_queue_cmd { ******************************************************************/ /** - * struct ionic_notifyq_event + * struct ionic_notifyq_event - Generic event reporting structure * @eid: event number * @ecode: event code * @data: unspecified data about the event @@ -1966,10 +2379,10 @@ struct ionic_notifyq_event { }; /** - * struct ionic_link_change_event + * struct ionic_link_change_event - Link change event notification * @eid: event number - * @ecode: event code = EVENT_OPCODE_LINK_CHANGE - * @link_status: link up or down, with error bits (enum port_status) + * @ecode: event code = IONIC_EVENT_LINK_CHANGE + * @link_status: link up/down, with error bits (enum ionic_port_status) * @link_speed: speed of the network link * * Sent when the network link state changes between UP and DOWN @@ -1983,9 +2396,9 @@ struct ionic_link_change_event { }; /** - * struct ionic_reset_event + * struct ionic_reset_event - Reset event notification * @eid: event number - * @ecode: event code = EVENT_OPCODE_RESET + * @ecode: event code = IONIC_EVENT_RESET * @reset_code: reset type * @state: 0=pending, 1=complete, 2=error * @@ -2001,11 +2414,9 @@ struct ionic_reset_event { }; /** - * struct ionic_heartbeat_event + * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health * @eid: event number - * @ecode: event code = EVENT_OPCODE_HEARTBEAT - * - * Sent periodically by the NIC to indicate continued health + * @ecode: event code = IONIC_EVENT_HEARTBEAT */ struct ionic_heartbeat_event { __le64 eid; @@ -2014,12 +2425,10 @@ struct ionic_heartbeat_event { }; /** - * struct ionic_log_event + * struct ionic_log_event - Sent to notify the driver of an internal error * @eid: event number - * @ecode: event code = EVENT_OPCODE_LOG + * @ecode: event code = IONIC_EVENT_LOG * @data: log data - * - * Sent to notify the driver of an internal error. */ struct ionic_log_event { __le64 eid; @@ -2028,7 +2437,18 @@ struct ionic_log_event { }; /** - * struct ionic_port_stats + * struct ionic_xcvr_event - Transceiver change event + * @eid: event number + * @ecode: event code = IONIC_EVENT_XCVR + */ +struct ionic_xcvr_event { + __le64 eid; + __le16 ecode; + u8 rsvd[54]; +}; + +/** + * struct ionic_port_stats - Port statistics structure */ struct ionic_port_stats { __le64 frames_rx_ok; @@ -2133,34 +2553,85 @@ struct ionic_mgmt_port_stats { __le64 frames_rx_multicast; __le64 frames_rx_broadcast; __le64 frames_rx_pause; - __le64 frames_rx_bad_length0; - __le64 frames_rx_undersized1; - __le64 frames_rx_oversized2; - __le64 frames_rx_fragments3; - __le64 frames_rx_jabber4; - __le64 frames_rx_64b5; - __le64 frames_rx_65b_127b6; - __le64 frames_rx_128b_255b7; - __le64 frames_rx_256b_511b8; - __le64 frames_rx_512b_1023b9; - __le64 frames_rx_1024b_1518b0; - __le64 frames_rx_gt_1518b1; - __le64 frames_rx_fifo_full2; - __le64 frames_tx_ok3; - __le64 frames_tx_all4; - __le64 frames_tx_bad5; - __le64 octets_tx_ok6; - __le64 octets_tx_total7; - __le64 frames_tx_unicast8; - __le64 frames_tx_multicast9; - __le64 frames_tx_broadcast0; - __le64 frames_tx_pause1; + __le64 frames_rx_bad_length; + __le64 frames_rx_undersized; + __le64 frames_rx_oversized; + __le64 frames_rx_fragments; + __le64 frames_rx_jabber; + __le64 frames_rx_64b; + __le64 frames_rx_65b_127b; + __le64 frames_rx_128b_255b; + __le64 frames_rx_256b_511b; + __le64 frames_rx_512b_1023b; + __le64 frames_rx_1024b_1518b; + __le64 frames_rx_gt_1518b; + __le64 frames_rx_fifo_full; + __le64 frames_tx_ok; + __le64 frames_tx_all; + __le64 frames_tx_bad; + __le64 octets_tx_ok; + __le64 octets_tx_total; + __le64 frames_tx_unicast; + __le64 frames_tx_multicast; + __le64 frames_tx_broadcast; + __le64 frames_tx_pause; +}; + +enum ionic_pb_buffer_drop_stats { + IONIC_BUFFER_INTRINSIC_DROP = 0, + IONIC_BUFFER_DISCARDED, + IONIC_BUFFER_ADMITTED, + IONIC_BUFFER_OUT_OF_CELLS_DROP, + IONIC_BUFFER_OUT_OF_CELLS_DROP_2, + IONIC_BUFFER_OUT_OF_CREDIT_DROP, + IONIC_BUFFER_TRUNCATION_DROP, + IONIC_BUFFER_PORT_DISABLED_DROP, + IONIC_BUFFER_COPY_TO_CPU_TAIL_DROP, + IONIC_BUFFER_SPAN_TAIL_DROP, + IONIC_BUFFER_MIN_SIZE_VIOLATION_DROP, + IONIC_BUFFER_ENQUEUE_ERROR_DROP, + IONIC_BUFFER_INVALID_PORT_DROP, + IONIC_BUFFER_INVALID_OUTPUT_QUEUE_DROP, + IONIC_BUFFER_DROP_MAX, +}; + +enum ionic_oflow_drop_stats { + IONIC_OFLOW_OCCUPANCY_DROP, + IONIC_OFLOW_EMERGENCY_STOP_DROP, + IONIC_OFLOW_WRITE_BUFFER_ACK_FILL_UP_DROP, + IONIC_OFLOW_WRITE_BUFFER_ACK_FULL_DROP, + IONIC_OFLOW_WRITE_BUFFER_FULL_DROP, + IONIC_OFLOW_CONTROL_FIFO_FULL_DROP, + IONIC_OFLOW_DROP_MAX, +}; + +/** + * struct port_pb_stats - packet buffers system stats + * uses ionic_pb_buffer_drop_stats for drop_counts[] + */ +struct ionic_port_pb_stats { + __le64 sop_count_in; + __le64 eop_count_in; + __le64 sop_count_out; + __le64 eop_count_out; + __le64 drop_counts[IONIC_BUFFER_DROP_MAX]; + __le64 input_queue_buffer_occupancy[IONIC_QOS_TC_MAX]; + __le64 input_queue_port_monitor[IONIC_QOS_TC_MAX]; + __le64 output_queue_port_monitor[IONIC_QOS_TC_MAX]; + __le64 oflow_drop_counts[IONIC_OFLOW_DROP_MAX]; + __le64 input_queue_good_pkts_in[IONIC_QOS_TC_MAX]; + __le64 input_queue_good_pkts_out[IONIC_QOS_TC_MAX]; + __le64 input_queue_err_pkts_in[IONIC_QOS_TC_MAX]; + __le64 input_queue_fifo_depth[IONIC_QOS_TC_MAX]; + __le64 input_queue_max_fifo_depth[IONIC_QOS_TC_MAX]; + __le64 input_queue_peak_occupancy[IONIC_QOS_TC_MAX]; + __le64 output_queue_buffer_occupancy[IONIC_QOS_TC_MAX]; }; /** * struct ionic_port_identity - port identity structure * @version: identity structure version - * @type: type of port (enum port_type) + * @type: type of port (enum ionic_port_type) * @num_lanes: number of lanes for the port * @autoneg: autoneg supported * @min_frame_size: minimum frame size supported @@ -2186,22 +2657,31 @@ union ionic_port_identity { u8 rsvd2[44]; union ionic_port_config config; }; - __le32 words[512]; + __le32 words[478]; }; /** * struct ionic_port_info - port info structure - * @port_status: port status - * @port_stats: port stats + * @config: Port configuration data + * @status: Port status data + * @stats: Port statistics data + * @mgmt_stats: Port management statistics data + * @port_pb_drop_stats: uplink pb drop stats */ struct ionic_port_info { union ionic_port_config config; struct ionic_port_status status; - struct ionic_port_stats stats; + union { + struct ionic_port_stats stats; + struct ionic_mgmt_port_stats mgmt_stats; + }; + /* room for pb_stats to start at 2k offset */ + u8 rsvd[760]; + struct ionic_port_pb_stats pb_stats; }; /** - * struct ionic_lif_stats + * struct ionic_lif_stats - LIF statistics structure */ struct ionic_lif_stats { /* RX */ @@ -2254,7 +2734,7 @@ struct ionic_lif_stats { __le64 tx_queue_error; __le64 tx_desc_fetch_error; __le64 tx_desc_data_error; - __le64 rsvd9; + __le64 tx_queue_empty; __le64 rsvd10; __le64 rsvd11; __le64 rsvd12; @@ -2355,7 +2835,10 @@ struct ionic_lif_stats { }; /** - * struct ionic_lif_info - lif info structure + * struct ionic_lif_info - LIF info structure + * @config: LIF configuration structure + * @status: LIF status structure + * @stats: LIF statistics structure */ struct ionic_lif_info { union ionic_lif_config config; @@ -2390,8 +2873,14 @@ union ionic_dev_cmd { struct ionic_qos_identify_cmd qos_identify; struct ionic_qos_init_cmd qos_init; struct ionic_qos_reset_cmd qos_reset; + struct ionic_qos_clear_stats_cmd qos_clear_stats; + struct ionic_q_identify_cmd q_identify; struct ionic_q_init_cmd q_init; + struct ionic_q_control_cmd q_control; + + struct ionic_fw_download_cmd fw_download; + struct ionic_fw_control_cmd fw_control; }; union ionic_dev_cmd_comp { @@ -2423,19 +2912,36 @@ union ionic_dev_cmd_comp { ionic_qos_init_comp qos_init; ionic_qos_reset_comp qos_reset; + struct ionic_q_identify_comp q_identify; struct ionic_q_init_comp q_init; + + ionic_fw_download_comp fw_download; + struct ionic_fw_control_comp fw_control; +}; + +/** + * struct ionic_hwstamp_regs - Hardware current timestamp registers + * @tick_low: Low 32 bits of hardware timestamp + * @tick_high: High 32 bits of hardware timestamp + */ +struct ionic_hwstamp_regs { + u32 tick_low; + u32 tick_high; }; /** - * union dev_info - Device info register format (read-only) - * @signature: Signature value of 0x44455649 ('DEVI'). - * @version: Current version of info. - * @asic_type: Asic type. - * @asic_rev: Asic revision. - * @fw_status: Firmware status. - * @fw_heartbeat: Firmware heartbeat counter. - * @serial_num: Serial number. - * @fw_version: Firmware version. + * union ionic_dev_info_regs - Device info register format (read-only) + * @signature: Signature value of 0x44455649 ('DEVI') + * @version: Current version of info + * @asic_type: Asic type + * @asic_rev: Asic revision + * @fw_status: Firmware status + * bit 0 - 1 = fw running + * bit 4-7 - 4 bit generation number, changes on fw restart + * @fw_heartbeat: Firmware heartbeat counter + * @serial_num: Serial number + * @fw_version: Firmware version + * @hwstamp_regs: Hardware current timestamp registers */ union ionic_dev_info_regs { #define IONIC_DEVINFO_FWVERS_BUFLEN 32 @@ -2445,21 +2951,24 @@ union ionic_dev_info_regs { u8 version; u8 asic_type; u8 asic_rev; -#define IONIC_FW_STS_F_RUNNING 0x1 +#define IONIC_FW_STS_F_RUNNING 0x01 +#define IONIC_FW_STS_F_GENERATION 0xF0 u8 fw_status; u32 fw_heartbeat; char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN]; char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN]; + u8 rsvd_pad1024[948]; + struct ionic_hwstamp_regs hwstamp; }; u32 words[512]; }; /** * union ionic_dev_cmd_regs - Device command register format (read-write) - * @doorbell: Device Cmd Doorbell, write-only. + * @doorbell: Device Cmd Doorbell, write-only * Write a 1 to signal device to process cmd, * poll done for completion. - * @done: Done indicator, bit 0 == 1 when command is complete. + * @done: Done indicator, bit 0 == 1 when command is complete * @cmd: Opcode-specific command bytes * @comp: Opcode-specific response bytes * @data: Opcode-specific side-data @@ -2472,12 +2981,12 @@ union ionic_dev_cmd_regs { union ionic_dev_cmd_comp comp; u8 rsvd[48]; u32 data[478]; - }; + } __packed; u32 words[512]; }; /** - * union ionic_dev_regs - Device register format in for bar 0 page 0 + * union ionic_dev_regs - Device register format for bar 0 page 0 * @info: Device info registers * @devcmd: Device command registers */ @@ -2485,17 +2994,19 @@ union ionic_dev_regs { struct { union ionic_dev_info_regs info; union ionic_dev_cmd_regs devcmd; - }; + } __packed; __le32 words[1024]; }; union ionic_adminq_cmd { struct ionic_admin_cmd cmd; struct ionic_nop_cmd nop; + struct ionic_q_identify_cmd q_identify; struct ionic_q_init_cmd q_init; struct ionic_q_control_cmd q_control; struct ionic_lif_setattr_cmd lif_setattr; struct ionic_lif_getattr_cmd lif_getattr; + struct ionic_lif_setphc_cmd lif_setphc; struct ionic_rx_mode_set_cmd rx_mode_set; struct ionic_rx_filter_add_cmd rx_filter_add; struct ionic_rx_filter_del_cmd rx_filter_del; @@ -2508,9 +3019,11 @@ union ionic_adminq_cmd { union ionic_adminq_comp { struct ionic_admin_comp comp; struct ionic_nop_comp nop; + struct ionic_q_identify_comp q_identify; struct ionic_q_init_comp q_init; struct ionic_lif_setattr_comp lif_setattr; struct ionic_lif_getattr_comp lif_getattr; + struct ionic_admin_comp lif_setphc; struct ionic_rx_filter_add_comp rx_filter_add; struct ionic_fw_control_comp fw_control; }; @@ -2533,14 +3046,14 @@ union ionic_adminq_comp { /** * struct ionic_doorbell - Doorbell register layout * @p_index: Producer index - * @ring: Selects the specific ring of the queue to update. + * @ring: Selects the specific ring of the queue to update * Type-specific meaning: - * ring=0: Default producer/consumer queue. + * ring=0: Default producer/consumer queue * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs * send events to EQs when armed. EQs send * interrupts when armed. - * @qid: The queue id selects the queue destination for the - * producer index and flags. + * @qid_lo: Queue destination for the producer index and flags (low bits) + * @qid_hi: Queue destination for the producer index and flags (high bits) */ struct ionic_doorbell { __le16 p_index; @@ -2573,8 +3086,7 @@ struct ionic_identity { union ionic_lif_identity lif; union ionic_port_identity port; union ionic_qos_identity qos; + union ionic_q_identity txq; }; -#pragma pack(pop) - #endif /* _IONIC_IF_H_ */ |