diff options
Diffstat (limited to 'drivers/phy/ti/phy-j721e-wiz.c')
| -rw-r--r-- | drivers/phy/ti/phy-j721e-wiz.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index cc2ab5152f07..20af142580ad 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -24,6 +24,11 @@ #include <linux/regmap.h> #include <linux/reset-controller.h> +#define REF_CLK_19_2MHZ 19200000 +#define REF_CLK_25MHZ 25000000 +#define REF_CLK_100MHZ 100000000 +#define REF_CLK_156_25MHZ 156250000 + /* SCM offsets */ #define SERDES_SUP_CTRL 0x4400 @@ -1053,6 +1058,25 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node) else regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); + switch (wiz->type) { + case AM64_WIZ_10G: + case J7200_WIZ_10G: + switch (rate) { + case REF_CLK_100MHZ: + regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x2); + break; + case REF_CLK_156_25MHZ: + regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x3); + break; + default: + regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0); + break; + } + break; + default: + break; + } + if (wiz->data->pma_cmn_refclk1_int_mode) { clk = devm_clk_get(dev, "core_ref1_clk"); if (IS_ERR(clk)) { |