38 files changed, 0 insertions, 106926 deletions

diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
deleted file mode 100644
index cf0e0dc42b84..000000000000
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ /dev/null
@@ -1,197 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Renesas SH and SH Mobile PINCTRL drivers
-#
-
-config PINCTRL_SH_PFC
-	bool "Renesas SoC pin control support" if COMPILE_TEST && !(ARCH_RENESAS || SUPERH)
-	default y if ARCH_RENESAS || SUPERH
-	select PINMUX
-	select PINCONF
-	select GENERIC_PINCONF
-	select PINCTRL_PFC_EMEV2 if ARCH_EMEV2
-	select PINCTRL_PFC_R8A73A4 if ARCH_R8A73A4
-	select PINCTRL_PFC_R8A7740 if ARCH_R8A7740
-	select PINCTRL_PFC_R8A7743 if ARCH_R8A7743
-	select PINCTRL_PFC_R8A7744 if ARCH_R8A7744
-	select PINCTRL_PFC_R8A7745 if ARCH_R8A7745
-	select PINCTRL_PFC_R8A77470 if ARCH_R8A77470
-	select PINCTRL_PFC_R8A774A1 if ARCH_R8A774A1
-	select PINCTRL_PFC_R8A774B1 if ARCH_R8A774B1
-	select PINCTRL_PFC_R8A774C0 if ARCH_R8A774C0
-	select PINCTRL_PFC_R8A7778 if ARCH_R8A7778
-	select PINCTRL_PFC_R8A7779 if ARCH_R8A7779
-	select PINCTRL_PFC_R8A7790 if ARCH_R8A7790
-	select PINCTRL_PFC_R8A7791 if ARCH_R8A7791
-	select PINCTRL_PFC_R8A7792 if ARCH_R8A7792
-	select PINCTRL_PFC_R8A7793 if ARCH_R8A7793
-	select PINCTRL_PFC_R8A7794 if ARCH_R8A7794
-	select PINCTRL_PFC_R8A77950 if ARCH_R8A77950 || ARCH_R8A7795
-	select PINCTRL_PFC_R8A77951 if ARCH_R8A77951 || ARCH_R8A7795
-	select PINCTRL_PFC_R8A77960 if ARCH_R8A77960
-	select PINCTRL_PFC_R8A77961 if ARCH_R8A77961
-	select PINCTRL_PFC_R8A77965 if ARCH_R8A77965
-	select PINCTRL_PFC_R8A77970 if ARCH_R8A77970
-	select PINCTRL_PFC_R8A77980 if ARCH_R8A77980
-	select PINCTRL_PFC_R8A77990 if ARCH_R8A77990
-	select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
-	select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
-	select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
-	select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
-	select PINCTRL_PFC_SH73A0 if ARCH_SH73A0
-	select PINCTRL_PFC_SH7720 if CPU_SUBTYPE_SH7720
-	select PINCTRL_PFC_SH7722 if CPU_SUBTYPE_SH7722
-	select PINCTRL_PFC_SH7723 if CPU_SUBTYPE_SH7723
-	select PINCTRL_PFC_SH7724 if CPU_SUBTYPE_SH7724
-	select PINCTRL_PFC_SH7734 if CPU_SUBTYPE_SH7734
-	select PINCTRL_PFC_SH7757 if CPU_SUBTYPE_SH7757
-	select PINCTRL_PFC_SH7785 if CPU_SUBTYPE_SH7785
-	select PINCTRL_PFC_SH7786 if CPU_SUBTYPE_SH7786
-	select PINCTRL_PFC_SHX3 if CPU_SUBTYPE_SHX3
-	help
-	  This enables pin control drivers for Renesas SuperH and ARM platforms
-
-config PINCTRL_SH_PFC_GPIO
-	select GPIOLIB
-	bool
-	help
-	  This enables pin control and GPIO drivers for SH/SH Mobile platforms
-
-config PINCTRL_SH_FUNC_GPIO
-	select PINCTRL_SH_PFC_GPIO
-	bool
-	help
-	  This enables legacy function GPIOs for SH platforms
-
-config PINCTRL_PFC_EMEV2
-	bool "Emma Mobile AV2 pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A73A4
-	bool "R-Mobile APE6 pin control support" if COMPILE_TEST
-	select PINCTRL_SH_PFC_GPIO
-
-config PINCTRL_PFC_R8A7740
-	bool "R-Mobile A1 pin control support" if COMPILE_TEST
-	select PINCTRL_SH_PFC_GPIO
-
-config PINCTRL_PFC_R8A7743
-	bool "RZ/G1M pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A7744
-	bool "RZ/G1N pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A7745
-	bool "RZ/G1E pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A77470
-	bool "RZ/G1C pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A774A1
-	bool "RZ/G2M pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A774B1
-	bool "RZ/G2N pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A774C0
-	bool "RZ/G2E pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A7778
-	bool "R-Car M1A pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A7779
-	bool "R-Car H1 pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A7790
-	bool "R-Car H2 pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A7791
-	bool "R-Car M2-W pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A7792
-	bool "R-Car V2H pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A7793
-	bool "R-Car M2-N pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A7794
-	bool "R-Car E2 pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A77950
-	bool "R-Car H3 ES1.x pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A77951
-	bool "R-Car H3 ES2.0+ pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A77960
-	bool "R-Car M3-W pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A77961
-	bool "R-Car M3-W+ pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A77965
-	bool "R-Car M3-N pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A77970
-	bool "R-Car V3M pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A77980
-	bool "R-Car V3H pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A77990
-	bool "R-Car E3 pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_R8A77995
-	bool "R-Car D3 pin control support" if COMPILE_TEST
-
-config PINCTRL_PFC_SH7203
-	bool "SH7203 pin control support" if COMPILE_TEST
-	select PINCTRL_SH_FUNC_GPIO
-
-config PINCTRL_PFC_SH7264
-	bool "SH7264 pin control support" if COMPILE_TEST
-	select PINCTRL_SH_FUNC_GPIO
-
-config PINCTRL_PFC_SH7269
-	bool "SH7269 pin control support" if COMPILE_TEST
-	select PINCTRL_SH_FUNC_GPIO
-
-config PINCTRL_PFC_SH73A0
-	bool "SH-Mobile AG5 pin control support" if COMPILE_TEST
-	select PINCTRL_SH_PFC_GPIO
-	select REGULATOR
-
-config PINCTRL_PFC_SH7720
-	bool "SH7720 pin control support" if COMPILE_TEST
-	select PINCTRL_SH_FUNC_GPIO
-
-config PINCTRL_PFC_SH7722
-	bool "SH7722 pin control support" if COMPILE_TEST
-	select PINCTRL_SH_FUNC_GPIO
-
-config PINCTRL_PFC_SH7723
-	bool "SH-Mobile R2 pin control support" if COMPILE_TEST
-	select PINCTRL_SH_FUNC_GPIO
-
-config PINCTRL_PFC_SH7724
-	bool "SH-Mobile R2R pin control support" if COMPILE_TEST
-	select PINCTRL_SH_FUNC_GPIO
-
-config PINCTRL_PFC_SH7734
-	bool "SH7734 pin control support" if COMPILE_TEST
-	select PINCTRL_SH_FUNC_GPIO
-
-config PINCTRL_PFC_SH7757
-	bool "SH7757 pin control support" if COMPILE_TEST
-	select PINCTRL_SH_FUNC_GPIO
-
-config PINCTRL_PFC_SH7785
-	bool "SH7785 pin control support" if COMPILE_TEST
-	select PINCTRL_SH_FUNC_GPIO
-
-config PINCTRL_PFC_SH7786
-	bool "SH7786 pin control support" if COMPILE_TEST
-	select PINCTRL_SH_FUNC_GPIO
-
-config PINCTRL_PFC_SHX3
-	bool "SH-X3 pin control support" if COMPILE_TEST
-	select PINCTRL_SH_FUNC_GPIO
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
deleted file mode 100644
index 9ebe321d24c4..000000000000
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ /dev/null
@@ -1,57 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_PINCTRL_SH_PFC)	+= core.o pinctrl.o
-obj-$(CONFIG_PINCTRL_SH_PFC_GPIO)	+= gpio.o
-obj-$(CONFIG_PINCTRL_PFC_EMEV2)	+= pfc-emev2.o
-obj-$(CONFIG_PINCTRL_PFC_R8A73A4)	+= pfc-r8a73a4.o
-obj-$(CONFIG_PINCTRL_PFC_R8A7740)	+= pfc-r8a7740.o
-obj-$(CONFIG_PINCTRL_PFC_R8A7743)	+= pfc-r8a7791.o
-obj-$(CONFIG_PINCTRL_PFC_R8A7744)	+= pfc-r8a7791.o
-obj-$(CONFIG_PINCTRL_PFC_R8A7745)	+= pfc-r8a7794.o
-obj-$(CONFIG_PINCTRL_PFC_R8A77470)	+= pfc-r8a77470.o
-obj-$(CONFIG_PINCTRL_PFC_R8A774A1)	+= pfc-r8a7796.o
-obj-$(CONFIG_PINCTRL_PFC_R8A774B1)	+= pfc-r8a77965.o
-obj-$(CONFIG_PINCTRL_PFC_R8A774C0)	+= pfc-r8a77990.o
-obj-$(CONFIG_PINCTRL_PFC_R8A7778)	+= pfc-r8a7778.o
-obj-$(CONFIG_PINCTRL_PFC_R8A7779)	+= pfc-r8a7779.o
-obj-$(CONFIG_PINCTRL_PFC_R8A7790)	+= pfc-r8a7790.o
-obj-$(CONFIG_PINCTRL_PFC_R8A7791)	+= pfc-r8a7791.o
-obj-$(CONFIG_PINCTRL_PFC_R8A7792)	+= pfc-r8a7792.o
-obj-$(CONFIG_PINCTRL_PFC_R8A7793)	+= pfc-r8a7791.o
-obj-$(CONFIG_PINCTRL_PFC_R8A7794)	+= pfc-r8a7794.o
-obj-$(CONFIG_PINCTRL_PFC_R8A77950)	+= pfc-r8a77950.o
-obj-$(CONFIG_PINCTRL_PFC_R8A77951)	+= pfc-r8a77951.o
-obj-$(CONFIG_PINCTRL_PFC_R8A77960)	+= pfc-r8a7796.o
-obj-$(CONFIG_PINCTRL_PFC_R8A77961)	+= pfc-r8a7796.o
-obj-$(CONFIG_PINCTRL_PFC_R8A77965)	+= pfc-r8a77965.o
-obj-$(CONFIG_PINCTRL_PFC_R8A77970)	+= pfc-r8a77970.o
-obj-$(CONFIG_PINCTRL_PFC_R8A77980)	+= pfc-r8a77980.o
-obj-$(CONFIG_PINCTRL_PFC_R8A77990)	+= pfc-r8a77990.o
-obj-$(CONFIG_PINCTRL_PFC_R8A77995)	+= pfc-r8a77995.o
-obj-$(CONFIG_PINCTRL_PFC_SH7203)	+= pfc-sh7203.o
-obj-$(CONFIG_PINCTRL_PFC_SH7264)	+= pfc-sh7264.o
-obj-$(CONFIG_PINCTRL_PFC_SH7269)	+= pfc-sh7269.o
-obj-$(CONFIG_PINCTRL_PFC_SH73A0)	+= pfc-sh73a0.o
-obj-$(CONFIG_PINCTRL_PFC_SH7720)	+= pfc-sh7720.o
-obj-$(CONFIG_PINCTRL_PFC_SH7722)	+= pfc-sh7722.o
-obj-$(CONFIG_PINCTRL_PFC_SH7723)	+= pfc-sh7723.o
-obj-$(CONFIG_PINCTRL_PFC_SH7724)	+= pfc-sh7724.o
-obj-$(CONFIG_PINCTRL_PFC_SH7734)	+= pfc-sh7734.o
-obj-$(CONFIG_PINCTRL_PFC_SH7757)	+= pfc-sh7757.o
-obj-$(CONFIG_PINCTRL_PFC_SH7785)	+= pfc-sh7785.o
-obj-$(CONFIG_PINCTRL_PFC_SH7786)	+= pfc-sh7786.o
-obj-$(CONFIG_PINCTRL_PFC_SHX3)		+= pfc-shx3.o
-
-ifeq ($(CONFIG_COMPILE_TEST),y)
-CFLAGS_pfc-sh7203.o	+= -I$(srctree)/arch/sh/include/cpu-sh2a
-CFLAGS_pfc-sh7264.o	+= -I$(srctree)/arch/sh/include/cpu-sh2a
-CFLAGS_pfc-sh7269.o	+= -I$(srctree)/arch/sh/include/cpu-sh2a
-CFLAGS_pfc-sh7720.o	+= -I$(srctree)/arch/sh/include/cpu-sh3
-CFLAGS_pfc-sh7722.o	+= -I$(srctree)/arch/sh/include/cpu-sh4
-CFLAGS_pfc-sh7723.o	+= -I$(srctree)/arch/sh/include/cpu-sh4
-CFLAGS_pfc-sh7724.o	+= -I$(srctree)/arch/sh/include/cpu-sh4
-CFLAGS_pfc-sh7734.o	+= -I$(srctree)/arch/sh/include/cpu-sh4
-CFLAGS_pfc-sh7757.o	+= -I$(srctree)/arch/sh/include/cpu-sh4
-CFLAGS_pfc-sh7785.o	+= -I$(srctree)/arch/sh/include/cpu-sh4
-CFLAGS_pfc-sh7786.o	+= -I$(srctree)/arch/sh/include/cpu-sh4
-CFLAGS_pfc-shx3.o	+= -I$(srctree)/arch/sh/include/cpu-sh4
-endif
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
deleted file mode 100644
index 82209116955b..000000000000
--- a/drivers/pinctrl/sh-pfc/core.c
+++ /dev/null
@@ -1,1054 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Pin Control and GPIO driver for SuperH Pin Function Controller.
- *
- * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
- *
- * Copyright (C) 2008 Magnus Damm
- * Copyright (C) 2009 - 2012 Paul Mundt
- */
-
-#define DRV_NAME "sh-pfc"
-
-#include <linux/bitops.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/platform_device.h>
-#include <linux/psci.h>
-#include <linux/slab.h>
-#include <linux/sys_soc.h>
-
-#include "core.h"
-
-static int sh_pfc_map_resources(struct sh_pfc *pfc,
-				struct platform_device *pdev)
-{
-	struct sh_pfc_window *windows;
-	unsigned int *irqs = NULL;
-	unsigned int num_windows;
-	struct resource *res;
-	unsigned int i;
-	int num_irqs;
-
-	/* Count the MEM and IRQ resources. */
-	for (num_windows = 0;; num_windows++) {
-		res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
-		if (!res)
-			break;
-	}
-	if (num_windows == 0)
-		return -EINVAL;
-
-	num_irqs = platform_irq_count(pdev);
-	if (num_irqs < 0)
-		return num_irqs;
-
-	/* Allocate memory windows and IRQs arrays. */
-	windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows),
-			       GFP_KERNEL);
-	if (windows == NULL)
-		return -ENOMEM;
-
-	pfc->num_windows = num_windows;
-	pfc->windows = windows;
-
-	if (num_irqs) {
-		irqs = devm_kcalloc(pfc->dev, num_irqs, sizeof(*irqs),
-				    GFP_KERNEL);
-		if (irqs == NULL)
-			return -ENOMEM;
-
-		pfc->num_irqs = num_irqs;
-		pfc->irqs = irqs;
-	}
-
-	/* Fill them. */
-	for (i = 0; i < num_windows; i++) {
-		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
-		windows->phys = res->start;
-		windows->size = resource_size(res);
-		windows->virt = devm_ioremap_resource(pfc->dev, res);
-		if (IS_ERR(windows->virt))
-			return -ENOMEM;
-		windows++;
-	}
-	for (i = 0; i < num_irqs; i++)
-		*irqs++ = platform_get_irq(pdev, i);
-
-	return 0;
-}
-
-static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
-{
-	struct sh_pfc_window *window;
-	phys_addr_t address = reg;
-	unsigned int i;
-
-	/* scan through physical windows and convert address */
-	for (i = 0; i < pfc->num_windows; i++) {
-		window = pfc->windows + i;
-
-		if (address < window->phys)
-			continue;
-
-		if (address >= (window->phys + window->size))
-			continue;
-
-		return window->virt + (address - window->phys);
-	}
-
-	BUG();
-	return NULL;
-}
-
-int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
-{
-	unsigned int offset;
-	unsigned int i;
-
-	for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
-		const struct sh_pfc_pin_range *range = &pfc->ranges[i];
-
-		if (pin <= range->end)
-			return pin >= range->start
-			     ? offset + pin - range->start : -1;
-
-		offset += range->end - range->start + 1;
-	}
-
-	return -EINVAL;
-}
-
-static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
-{
-	if (enum_id < r->begin)
-		return 0;
-
-	if (enum_id > r->end)
-		return 0;
-
-	return 1;
-}
-
-u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
-{
-	switch (reg_width) {
-	case 8:
-		return ioread8(mapped_reg);
-	case 16:
-		return ioread16(mapped_reg);
-	case 32:
-		return ioread32(mapped_reg);
-	}
-
-	BUG();
-	return 0;
-}
-
-void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
-			  u32 data)
-{
-	switch (reg_width) {
-	case 8:
-		iowrite8(data, mapped_reg);
-		return;
-	case 16:
-		iowrite16(data, mapped_reg);
-		return;
-	case 32:
-		iowrite32(data, mapped_reg);
-		return;
-	}
-
-	BUG();
-}
-
-u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
-{
-	return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
-}
-
-void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
-{
-	if (pfc->info->unlock_reg)
-		sh_pfc_write_raw_reg(
-			sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
-			~data);
-
-	sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
-}
-
-static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
-				     const struct pinmux_cfg_reg *crp,
-				     unsigned int in_pos,
-				     void __iomem **mapped_regp, u32 *maskp,
-				     unsigned int *posp)
-{
-	unsigned int k;
-
-	*mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
-
-	if (crp->field_width) {
-		*maskp = (1 << crp->field_width) - 1;
-		*posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
-	} else {
-		*maskp = (1 << crp->var_field_width[in_pos]) - 1;
-		*posp = crp->reg_width;
-		for (k = 0; k <= in_pos; k++)
-			*posp -= crp->var_field_width[k];
-	}
-}
-
-static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
-				    const struct pinmux_cfg_reg *crp,
-				    unsigned int field, u32 value)
-{
-	void __iomem *mapped_reg;
-	unsigned int pos;
-	u32 mask, data;
-
-	sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
-
-	dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
-		"r_width = %u, f_width = %u\n",
-		crp->reg, value, field, crp->reg_width, hweight32(mask));
-
-	mask = ~(mask << pos);
-	value = value << pos;
-
-	data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
-	data &= mask;
-	data |= value;
-
-	if (pfc->info->unlock_reg)
-		sh_pfc_write_raw_reg(
-			sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
-			~data);
-
-	sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
-}
-
-static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
-				 const struct pinmux_cfg_reg **crp,
-				 unsigned int *fieldp, u32 *valuep)
-{
-	unsigned int k = 0;
-
-	while (1) {
-		const struct pinmux_cfg_reg *config_reg =
-			pfc->info->cfg_regs + k;
-		unsigned int r_width = config_reg->reg_width;
-		unsigned int f_width = config_reg->field_width;
-		unsigned int curr_width;
-		unsigned int bit_pos;
-		unsigned int pos = 0;
-		unsigned int m = 0;
-
-		if (!r_width)
-			break;
-
-		for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
-			u32 ncomb;
-			u32 n;
-
-			if (f_width)
-				curr_width = f_width;
-			else
-				curr_width = config_reg->var_field_width[m];
-
-			ncomb = 1 << curr_width;
-			for (n = 0; n < ncomb; n++) {
-				if (config_reg->enum_ids[pos + n] == enum_id) {
-					*crp = config_reg;
-					*fieldp = m;
-					*valuep = n;
-					return 0;
-				}
-			}
-			pos += ncomb;
-			m++;
-		}
-		k++;
-	}
-
-	return -EINVAL;
-}
-
-static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
-			      u16 *enum_idp)
-{
-	const u16 *data = pfc->info->pinmux_data;
-	unsigned int k;
-
-	if (pos) {
-		*enum_idp = data[pos + 1];
-		return pos + 1;
-	}
-
-	for (k = 0; k < pfc->info->pinmux_data_size; k++) {
-		if (data[k] == mark) {
-			*enum_idp = data[k + 1];
-			return k + 1;
-		}
-	}
-
-	dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
-		mark);
-	return -EINVAL;
-}
-
-int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
-{
-	const struct pinmux_range *range;
-	int pos = 0;
-
-	switch (pinmux_type) {
-	case PINMUX_TYPE_GPIO:
-	case PINMUX_TYPE_FUNCTION:
-		range = NULL;
-		break;
-
-	case PINMUX_TYPE_OUTPUT:
-		range = &pfc->info->output;
-		break;
-
-	case PINMUX_TYPE_INPUT:
-		range = &pfc->info->input;
-		break;
-
-	default:
-		return -EINVAL;
-	}
-
-	/* Iterate over all the configuration fields we need to update. */
-	while (1) {
-		const struct pinmux_cfg_reg *cr;
-		unsigned int field;
-		u16 enum_id;
-		u32 value;
-		int in_range;
-		int ret;
-
-		pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
-		if (pos < 0)
-			return pos;
-
-		if (!enum_id)
-			break;
-
-		/* Check if the configuration field selects a function. If it
-		 * doesn't, skip the field if it's not applicable to the
-		 * requested pinmux type.
-		 */
-		in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
-		if (!in_range) {
-			if (pinmux_type == PINMUX_TYPE_FUNCTION) {
-				/* Functions are allowed to modify all
-				 * fields.
-				 */
-				in_range = 1;
-			} else if (pinmux_type != PINMUX_TYPE_GPIO) {
-				/* Input/output types can only modify fields
-				 * that correspond to their respective ranges.
-				 */
-				in_range = sh_pfc_enum_in_range(enum_id, range);
-
-				/*
-				 * special case pass through for fixed
-				 * input-only or output-only pins without
-				 * function enum register association.
-				 */
-				if (in_range && enum_id == range->force)
-					continue;
-			}
-			/* GPIOs are only allowed to modify function fields. */
-		}
-
-		if (!in_range)
-			continue;
-
-		ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
-		if (ret < 0)
-			return ret;
-
-		sh_pfc_write_config_reg(pfc, cr, field, value);
-	}
-
-	return 0;
-}
-
-const struct pinmux_bias_reg *
-sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
-		       unsigned int *bit)
-{
-	unsigned int i, j;
-
-	for (i = 0; pfc->info->bias_regs[i].puen; i++) {
-		for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
-			if (pfc->info->bias_regs[i].pins[j] == pin) {
-				*bit = j;
-				return &pfc->info->bias_regs[i];
-			}
-		}
-	}
-
-	WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
-
-	return NULL;
-}
-
-static int sh_pfc_init_ranges(struct sh_pfc *pfc)
-{
-	struct sh_pfc_pin_range *range;
-	unsigned int nr_ranges;
-	unsigned int i;
-
-	if (pfc->info->pins[0].pin == (u16)-1) {
-		/* Pin number -1 denotes that the SoC doesn't report pin numbers
-		 * in its pin arrays yet. Consider the pin numbers range as
-		 * continuous and allocate a single range.
-		 */
-		pfc->nr_ranges = 1;
-		pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
-					   GFP_KERNEL);
-		if (pfc->ranges == NULL)
-			return -ENOMEM;
-
-		pfc->ranges->start = 0;
-		pfc->ranges->end = pfc->info->nr_pins - 1;
-		pfc->nr_gpio_pins = pfc->info->nr_pins;
-
-		return 0;
-	}
-
-	/* Count, allocate and fill the ranges. The PFC SoC data pins array must
-	 * be sorted by pin numbers, and pins without a GPIO port must come
-	 * last.
-	 */
-	for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
-		if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
-			nr_ranges++;
-	}
-
-	pfc->nr_ranges = nr_ranges;
-	pfc->ranges = devm_kcalloc(pfc->dev, nr_ranges, sizeof(*pfc->ranges),
-				   GFP_KERNEL);
-	if (pfc->ranges == NULL)
-		return -ENOMEM;
-
-	range = pfc->ranges;
-	range->start = pfc->info->pins[0].pin;
-
-	for (i = 1; i < pfc->info->nr_pins; ++i) {
-		if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
-			continue;
-
-		range->end = pfc->info->pins[i-1].pin;
-		if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
-			pfc->nr_gpio_pins = range->end + 1;
-
-		range++;
-		range->start = pfc->info->pins[i].pin;
-	}
-
-	range->end = pfc->info->pins[i-1].pin;
-	if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
-		pfc->nr_gpio_pins = range->end + 1;
-
-	return 0;
-}
-
-#ifdef CONFIG_OF
-static const struct of_device_id sh_pfc_of_table[] = {
-#ifdef CONFIG_PINCTRL_PFC_EMEV2
-	{
-		.compatible = "renesas,pfc-emev2",
-		.data = &emev2_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A73A4
-	{
-		.compatible = "renesas,pfc-r8a73a4",
-		.data = &r8a73a4_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A7740
-	{
-		.compatible = "renesas,pfc-r8a7740",
-		.data = &r8a7740_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A7743
-	{
-		.compatible = "renesas,pfc-r8a7743",
-		.data = &r8a7743_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A7744
-	{
-		.compatible = "renesas,pfc-r8a7744",
-		.data = &r8a7744_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A7745
-	{
-		.compatible = "renesas,pfc-r8a7745",
-		.data = &r8a7745_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A77470
-	{
-		.compatible = "renesas,pfc-r8a77470",
-		.data = &r8a77470_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A774A1
-	{
-		.compatible = "renesas,pfc-r8a774a1",
-		.data = &r8a774a1_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A774B1
-	{
-		.compatible = "renesas,pfc-r8a774b1",
-		.data = &r8a774b1_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A774C0
-	{
-		.compatible = "renesas,pfc-r8a774c0",
-		.data = &r8a774c0_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A7778
-	{
-		.compatible = "renesas,pfc-r8a7778",
-		.data = &r8a7778_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A7779
-	{
-		.compatible = "renesas,pfc-r8a7779",
-		.data = &r8a7779_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A7790
-	{
-		.compatible = "renesas,pfc-r8a7790",
-		.data = &r8a7790_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A7791
-	{
-		.compatible = "renesas,pfc-r8a7791",
-		.data = &r8a7791_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A7792
-	{
-		.compatible = "renesas,pfc-r8a7792",
-		.data = &r8a7792_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A7793
-	{
-		.compatible = "renesas,pfc-r8a7793",
-		.data = &r8a7793_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A7794
-	{
-		.compatible = "renesas,pfc-r8a7794",
-		.data = &r8a7794_pinmux_info,
-	},
-#endif
-/* Both r8a7795 entries must be present to make sanity checks work */
-#ifdef CONFIG_PINCTRL_PFC_R8A77950
-	{
-		.compatible = "renesas,pfc-r8a7795",
-		.data = &r8a77950_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A77951
-	{
-		.compatible = "renesas,pfc-r8a7795",
-		.data = &r8a77951_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A77960
-	{
-		.compatible = "renesas,pfc-r8a7796",
-		.data = &r8a77960_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A77961
-	{
-		.compatible = "renesas,pfc-r8a77961",
-		.data = &r8a77961_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A77965
-	{
-		.compatible = "renesas,pfc-r8a77965",
-		.data = &r8a77965_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A77970
-	{
-		.compatible = "renesas,pfc-r8a77970",
-		.data = &r8a77970_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A77980
-	{
-		.compatible = "renesas,pfc-r8a77980",
-		.data = &r8a77980_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A77990
-	{
-		.compatible = "renesas,pfc-r8a77990",
-		.data = &r8a77990_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A77995
-	{
-		.compatible = "renesas,pfc-r8a77995",
-		.data = &r8a77995_pinmux_info,
-	},
-#endif
-#ifdef CONFIG_PINCTRL_PFC_SH73A0
-	{
-		.compatible = "renesas,pfc-sh73a0",
-		.data = &sh73a0_pinmux_info,
-	},
-#endif
-	{ },
-};
-#endif
-
-#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
-static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
-{
-}
-
-static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
-{
-	pfc->saved_regs[idx] = sh_pfc_read(pfc, reg);
-}
-
-static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
-{
-	sh_pfc_write(pfc, reg, pfc->saved_regs[idx]);
-}
-
-static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
-	void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx))
-{
-	unsigned int i, n = 0;
-
-	if (pfc->info->cfg_regs)
-		for (i = 0; pfc->info->cfg_regs[i].reg; i++)
-			do_reg(pfc, pfc->info->cfg_regs[i].reg, n++);
-
-	if (pfc->info->drive_regs)
-		for (i = 0; pfc->info->drive_regs[i].reg; i++)
-			do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
-
-	if (pfc->info->bias_regs)
-		for (i = 0; pfc->info->bias_regs[i].puen; i++) {
-			do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
-			if (pfc->info->bias_regs[i].pud)
-				do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
-		}
-
-	if (pfc->info->ioctrl_regs)
-		for (i = 0; pfc->info->ioctrl_regs[i].reg; i++)
-			do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++);
-
-	return n;
-}
-
-static int sh_pfc_suspend_init(struct sh_pfc *pfc)
-{
-	unsigned int n;
-
-	/* This is the best we can do to check for the presence of PSCI */
-	if (!psci_ops.cpu_suspend)
-		return 0;
-
-	n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg);
-	if (!n)
-		return 0;
-
-	pfc->saved_regs = devm_kmalloc_array(pfc->dev, n,
-					     sizeof(*pfc->saved_regs),
-					     GFP_KERNEL);
-	if (!pfc->saved_regs)
-		return -ENOMEM;
-
-	dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n);
-	return 0;
-}
-
-static int sh_pfc_suspend_noirq(struct device *dev)
-{
-	struct sh_pfc *pfc = dev_get_drvdata(dev);
-
-	if (pfc->saved_regs)
-		sh_pfc_walk_regs(pfc, sh_pfc_save_reg);
-	return 0;
-}
-
-static int sh_pfc_resume_noirq(struct device *dev)
-{
-	struct sh_pfc *pfc = dev_get_drvdata(dev);
-
-	if (pfc->saved_regs)
-		sh_pfc_walk_regs(pfc, sh_pfc_restore_reg);
-	return 0;
-}
-
-static const struct dev_pm_ops sh_pfc_pm  = {
-	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq)
-};
-#define DEV_PM_OPS	&sh_pfc_pm
-#else
-static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
-#define DEV_PM_OPS	NULL
-#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
-
-#ifdef DEBUG
-static bool __init is0s(const u16 *enum_ids, unsigned int n)
-{
-	unsigned int i;
-
-	for (i = 0; i < n; i++)
-		if (enum_ids[i])
-			return false;
-
-	return true;
-}
-
-static unsigned int sh_pfc_errors __initdata = 0;
-static unsigned int sh_pfc_warnings __initdata = 0;
-
-static void __init sh_pfc_check_cfg_reg(const char *drvname,
-					const struct pinmux_cfg_reg *cfg_reg)
-{
-	unsigned int i, n, rw, fw;
-
-	if (cfg_reg->field_width) {
-		/* Checked at build time */
-		return;
-	}
-
-	for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) {
-		if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw)) {
-			pr_warn("%s: reg 0x%x: reserved field [%u:%u] can be split to reduce table size\n",
-				drvname, cfg_reg->reg, rw, rw + fw - 1);
-			sh_pfc_warnings++;
-		}
-		n += 1 << fw;
-		rw += fw;
-	}
-
-	if (rw != cfg_reg->reg_width) {
-		pr_err("%s: reg 0x%x: var_field_width declares %u instead of %u bits\n",
-		       drvname, cfg_reg->reg, rw, cfg_reg->reg_width);
-		sh_pfc_errors++;
-	}
-
-	if (n != cfg_reg->nr_enum_ids) {
-		pr_err("%s: reg 0x%x: enum_ids[] has %u instead of %u values\n",
-		       drvname, cfg_reg->reg, cfg_reg->nr_enum_ids, n);
-		sh_pfc_errors++;
-	}
-}
-
-static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
-{
-	const struct sh_pfc_function *func;
-	const char *drvname = info->name;
-	unsigned int *refcnts;
-	unsigned int i, j, k;
-
-	pr_info("Checking %s\n", drvname);
-
-	/* Check pins */
-	for (i = 0; i < info->nr_pins; i++) {
-		for (j = 0; j < i; j++) {
-			if (!strcmp(info->pins[i].name, info->pins[j].name)) {
-				pr_err("%s: pin %s/%s: name conflict\n",
-				       drvname, info->pins[i].name,
-				       info->pins[j].name);
-				sh_pfc_errors++;
-			}
-
-			if (info->pins[i].pin != (u16)-1 &&
-			    info->pins[i].pin == info->pins[j].pin) {
-				pr_err("%s: pin %s/%s: pin %u conflict\n",
-				       drvname, info->pins[i].name,
-				       info->pins[j].name, info->pins[i].pin);
-				sh_pfc_errors++;
-			}
-
-			if (info->pins[i].enum_id &&
-			    info->pins[i].enum_id == info->pins[j].enum_id) {
-				pr_err("%s: pin %s/%s: enum_id %u conflict\n",
-				       drvname, info->pins[i].name,
-				       info->pins[j].name,
-				       info->pins[i].enum_id);
-				sh_pfc_errors++;
-			}
-		}
-	}
-
-	/* Check groups and functions */
-	refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);
-	if (!refcnts)
-		return;
-
-	for (i = 0; i < info->nr_functions; i++) {
-		func = &info->functions[i];
-		if (!func->name) {
-			pr_err("%s: empty function %u\n", drvname, i);
-			sh_pfc_errors++;
-			continue;
-		}
-		for (j = 0; j < func->nr_groups; j++) {
-			for (k = 0; k < info->nr_groups; k++) {
-				if (info->groups[k].name &&
-				    !strcmp(func->groups[j],
-					    info->groups[k].name)) {
-					refcnts[k]++;
-					break;
-				}
-			}
-
-			if (k == info->nr_groups) {
-				pr_err("%s: function %s: group %s not found\n",
-				       drvname, func->name, func->groups[j]);
-				sh_pfc_errors++;
-			}
-		}
-	}
-
-	for (i = 0; i < info->nr_groups; i++) {
-		if (!info->groups[i].name) {
-			pr_err("%s: empty group %u\n", drvname, i);
-			sh_pfc_errors++;
-			continue;
-		}
-		if (!refcnts[i]) {
-			pr_err("%s: orphan group %s\n", drvname,
-			       info->groups[i].name);
-			sh_pfc_errors++;
-		} else if (refcnts[i] > 1) {
-			pr_warn("%s: group %s referenced by %u functions\n",
-				drvname, info->groups[i].name, refcnts[i]);
-			sh_pfc_warnings++;
-		}
-	}
-
-	kfree(refcnts);
-
-	/* Check config register descriptions */
-	for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++)
-		sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
-}
-
-static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
-{
-	unsigned int i;
-
-	pr_warn("Checking builtin pinmux tables\n");
-
-	for (i = 0; pdrv->id_table[i].name[0]; i++)
-		sh_pfc_check_info((void *)pdrv->id_table[i].driver_data);
-
-#ifdef CONFIG_OF
-	for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++)
-		sh_pfc_check_info(pdrv->driver.of_match_table[i].data);
-#endif
-
-	pr_warn("Detected %u errors and %u warnings\n", sh_pfc_errors,
-		sh_pfc_warnings);
-}
-
-#else /* !DEBUG */
-static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
-#endif /* !DEBUG */
-
-#ifdef CONFIG_OF
-static const void *sh_pfc_quirk_match(void)
-{
-#if defined(CONFIG_PINCTRL_PFC_R8A77950) || \
-    defined(CONFIG_PINCTRL_PFC_R8A77951)
-	const struct soc_device_attribute *match;
-	static const struct soc_device_attribute quirks[] = {
-		{
-			.soc_id = "r8a7795", .revision = "ES1.*",
-			.data = &r8a77950_pinmux_info,
-		},
-		{
-			.soc_id = "r8a7795",
-			.data = &r8a77951_pinmux_info,
-		},
-
-		{ /* sentinel */ }
-	};
-
-	match = soc_device_match(quirks);
-	if (match)
-		return match->data ?: ERR_PTR(-ENODEV);
-#endif /* CONFIG_PINCTRL_PFC_R8A77950 || CONFIG_PINCTRL_PFC_R8A77951 */
-
-	return NULL;
-}
-#endif /* CONFIG_OF */
-
-static int sh_pfc_probe(struct platform_device *pdev)
-{
-	const struct sh_pfc_soc_info *info;
-	struct sh_pfc *pfc;
-	int ret;
-
-#ifdef CONFIG_OF
-	if (pdev->dev.of_node) {
-		info = sh_pfc_quirk_match();
-		if (IS_ERR(info))
-			return PTR_ERR(info);
-
-		if (!info)
-			info = of_device_get_match_data(&pdev->dev);
-	} else
-#endif
-		info = (const void *)platform_get_device_id(pdev)->driver_data;
-
-	pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
-	if (pfc == NULL)
-		return -ENOMEM;
-
-	pfc->info = info;
-	pfc->dev = &pdev->dev;
-
-	ret = sh_pfc_map_resources(pfc, pdev);
-	if (unlikely(ret < 0))
-		return ret;
-
-	spin_lock_init(&pfc->lock);
-
-	if (info->ops && info->ops->init) {
-		ret = info->ops->init(pfc);
-		if (ret < 0)
-			return ret;
-
-		/* .init() may have overridden pfc->info */
-		info = pfc->info;
-	}
-
-	ret = sh_pfc_suspend_init(pfc);
-	if (ret)
-		return ret;
-
-	/* Enable dummy states for those platforms without pinctrl support */
-	if (!of_have_populated_dt())
-		pinctrl_provide_dummies();
-
-	ret = sh_pfc_init_ranges(pfc);
-	if (ret < 0)
-		return ret;
-
-	/*
-	 * Initialize pinctrl bindings first
-	 */
-	ret = sh_pfc_register_pinctrl(pfc);
-	if (unlikely(ret != 0))
-		return ret;
-
-#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
-	/*
-	 * Then the GPIO chip
-	 */
-	ret = sh_pfc_register_gpiochip(pfc);
-	if (unlikely(ret != 0)) {
-		/*
-		 * If the GPIO chip fails to come up we still leave the
-		 * PFC state as it is, given that there are already
-		 * extant users of it that have succeeded by this point.
-		 */
-		dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
-	}
-#endif
-
-	platform_set_drvdata(pdev, pfc);
-
-	dev_info(pfc->dev, "%s support registered\n", info->name);
-
-	return 0;
-}
-
-static const struct platform_device_id sh_pfc_id_table[] = {
-#ifdef CONFIG_PINCTRL_PFC_SH7203
-	{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
-#endif
-#ifdef CONFIG_PINCTRL_PFC_SH7264
-	{ "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
-#endif
-#ifdef CONFIG_PINCTRL_PFC_SH7269
-	{ "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
-#endif
-#ifdef CONFIG_PINCTRL_PFC_SH7720
-	{ "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
-#endif
-#ifdef CONFIG_PINCTRL_PFC_SH7722
-	{ "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
-#endif
-#ifdef CONFIG_PINCTRL_PFC_SH7723
-	{ "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
-#endif
-#ifdef CONFIG_PINCTRL_PFC_SH7724
-	{ "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
-#endif
-#ifdef CONFIG_PINCTRL_PFC_SH7734
-	{ "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
-#endif
-#ifdef CONFIG_PINCTRL_PFC_SH7757
-	{ "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
-#endif
-#ifdef CONFIG_PINCTRL_PFC_SH7785
-	{ "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
-#endif
-#ifdef CONFIG_PINCTRL_PFC_SH7786
-	{ "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
-#endif
-#ifdef CONFIG_PINCTRL_PFC_SHX3
-	{ "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
-#endif
-	{ },
-};
-
-static struct platform_driver sh_pfc_driver = {
-	.probe		= sh_pfc_probe,
-	.id_table	= sh_pfc_id_table,
-	.driver		= {
-		.name	= DRV_NAME,
-		.of_match_table = of_match_ptr(sh_pfc_of_table),
-		.pm     = DEV_PM_OPS,
-	},
-};
-
-static int __init sh_pfc_init(void)
-{
-	sh_pfc_check_driver(&sh_pfc_driver);
-	return platform_driver_register(&sh_pfc_driver);
-}
-postcore_initcall(sh_pfc_init);
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
deleted file mode 100644
index b5b1d163e98a..000000000000
--- a/drivers/pinctrl/sh-pfc/core.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * SuperH Pin Function Controller support.
- *
- * Copyright (C) 2012  Renesas Solutions Corp.
- */
-#ifndef __SH_PFC_CORE_H__
-#define __SH_PFC_CORE_H__
-
-#include <linux/types.h>
-
-#include "sh_pfc.h"
-
-struct sh_pfc_pin_range {
-	u16 start;
-	u16 end;
-};
-
-int sh_pfc_register_gpiochip(struct sh_pfc *pfc);
-
-int sh_pfc_register_pinctrl(struct sh_pfc *pfc);
-
-u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width);
-void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
-			  u32 data);
-u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg);
-void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data);
-
-int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
-int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
-
-const struct pinmux_bias_reg *
-sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
-		       unsigned int *bit);
-
-#endif /* __SH_PFC_CORE_H__ */
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
deleted file mode 100644
index 8213e118aa40..000000000000
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ /dev/null
@@ -1,397 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * SuperH Pin Function Controller GPIO driver.
- *
- * Copyright (C) 2008 Magnus Damm
- * Copyright (C) 2009 - 2012 Paul Mundt
- */
-
-#include <linux/device.h>
-#include <linux/gpio/driver.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-
-#include "core.h"
-
-struct sh_pfc_gpio_data_reg {
-	const struct pinmux_data_reg *info;
-	u32 shadow;
-};
-
-struct sh_pfc_gpio_pin {
-	u8 dbit;
-	u8 dreg;
-};
-
-struct sh_pfc_chip {
-	struct sh_pfc			*pfc;
-	struct gpio_chip		gpio_chip;
-
-	struct sh_pfc_window		*mem;
-	struct sh_pfc_gpio_data_reg	*regs;
-	struct sh_pfc_gpio_pin		*pins;
-};
-
-static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
-{
-	struct sh_pfc_chip *chip = gpiochip_get_data(gc);
-	return chip->pfc;
-}
-
-static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset,
-			      struct sh_pfc_gpio_data_reg **reg,
-			      unsigned int *bit)
-{
-	int idx = sh_pfc_get_pin_index(chip->pfc, offset);
-	struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
-
-	*reg = &chip->regs[gpio_pin->dreg];
-	*bit = gpio_pin->dbit;
-}
-
-static u32 gpio_read_data_reg(struct sh_pfc_chip *chip,
-			      const struct pinmux_data_reg *dreg)
-{
-	phys_addr_t address = dreg->reg;
-	void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
-
-	return sh_pfc_read_raw_reg(mem, dreg->reg_width);
-}
-
-static void gpio_write_data_reg(struct sh_pfc_chip *chip,
-				const struct pinmux_data_reg *dreg, u32 value)
-{
-	phys_addr_t address = dreg->reg;
-	void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
-
-	sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
-}
-
-static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx)
-{
-	struct sh_pfc *pfc = chip->pfc;
-	struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
-	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
-	const struct pinmux_data_reg *dreg;
-	unsigned int bit;
-	unsigned int i;
-
-	for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
-		for (bit = 0; bit < dreg->reg_width; bit++) {
-			if (dreg->enum_ids[bit] == pin->enum_id) {
-				gpio_pin->dreg = i;
-				gpio_pin->dbit = bit;
-				return;
-			}
-		}
-	}
-
-	BUG();
-}
-
-static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
-{
-	struct sh_pfc *pfc = chip->pfc;
-	const struct pinmux_data_reg *dreg;
-	unsigned int i;
-
-	/* Count the number of data registers, allocate memory and initialize
-	 * them.
-	 */
-	for (i = 0; pfc->info->data_regs[i].reg_width; ++i)
-		;
-
-	chip->regs = devm_kcalloc(pfc->dev, i, sizeof(*chip->regs),
-				  GFP_KERNEL);
-	if (chip->regs == NULL)
-		return -ENOMEM;
-
-	for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
-		chip->regs[i].info = dreg;
-		chip->regs[i].shadow = gpio_read_data_reg(chip, dreg);
-	}
-
-	for (i = 0; i < pfc->info->nr_pins; i++) {
-		if (pfc->info->pins[i].enum_id == 0)
-			continue;
-
-		gpio_setup_data_reg(chip, i);
-	}
-
-	return 0;
-}
-
-/* -----------------------------------------------------------------------------
- * Pin GPIOs
- */
-
-static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
-{
-	struct sh_pfc *pfc = gpio_to_pfc(gc);
-	int idx = sh_pfc_get_pin_index(pfc, offset);
-
-	if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
-		return -EINVAL;
-
-	return pinctrl_gpio_request(offset);
-}
-
-static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
-{
-	return pinctrl_gpio_free(offset);
-}
-
-static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
-			       int value)
-{
-	struct sh_pfc_gpio_data_reg *reg;
-	unsigned int bit;
-	unsigned int pos;
-
-	gpio_get_data_reg(chip, offset, &reg, &bit);
-
-	pos = reg->info->reg_width - (bit + 1);
-
-	if (value)
-		reg->shadow |= BIT(pos);
-	else
-		reg->shadow &= ~BIT(pos);
-
-	gpio_write_data_reg(chip, reg->info, reg->shadow);
-}
-
-static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
-{
-	return pinctrl_gpio_direction_input(offset);
-}
-
-static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
-				    int value)
-{
-	gpio_pin_set_value(gpiochip_get_data(gc), offset, value);
-
-	return pinctrl_gpio_direction_output(offset);
-}
-
-static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
-{
-	struct sh_pfc_chip *chip = gpiochip_get_data(gc);
-	struct sh_pfc_gpio_data_reg *reg;
-	unsigned int bit;
-	unsigned int pos;
-
-	gpio_get_data_reg(chip, offset, &reg, &bit);
-
-	pos = reg->info->reg_width - (bit + 1);
-
-	return (gpio_read_data_reg(chip, reg->info) >> pos) & 1;
-}
-
-static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
-{
-	gpio_pin_set_value(gpiochip_get_data(gc), offset, value);
-}
-
-static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
-{
-	struct sh_pfc *pfc = gpio_to_pfc(gc);
-	unsigned int i, k;
-
-	for (i = 0; i < pfc->info->gpio_irq_size; i++) {
-		const short *gpios = pfc->info->gpio_irq[i].gpios;
-
-		for (k = 0; gpios[k] >= 0; k++) {
-			if (gpios[k] == offset)
-				goto found;
-		}
-	}
-
-	return 0;
-
-found:
-	return pfc->irqs[i];
-}
-
-static int gpio_pin_setup(struct sh_pfc_chip *chip)
-{
-	struct sh_pfc *pfc = chip->pfc;
-	struct gpio_chip *gc = &chip->gpio_chip;
-	int ret;
-
-	chip->pins = devm_kcalloc(pfc->dev,
-				  pfc->info->nr_pins, sizeof(*chip->pins),
-				  GFP_KERNEL);
-	if (chip->pins == NULL)
-		return -ENOMEM;
-
-	ret = gpio_setup_data_regs(chip);
-	if (ret < 0)
-		return ret;
-
-	gc->request = gpio_pin_request;
-	gc->free = gpio_pin_free;
-	gc->direction_input = gpio_pin_direction_input;
-	gc->get = gpio_pin_get;
-	gc->direction_output = gpio_pin_direction_output;
-	gc->set = gpio_pin_set;
-	gc->to_irq = gpio_pin_to_irq;
-
-	gc->label = pfc->info->name;
-	gc->parent = pfc->dev;
-	gc->owner = THIS_MODULE;
-	gc->base = 0;
-	gc->ngpio = pfc->nr_gpio_pins;
-
-	return 0;
-}
-
-/* -----------------------------------------------------------------------------
- * Function GPIOs
- */
-
-#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
-static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
-{
-	struct sh_pfc *pfc = gpio_to_pfc(gc);
-	unsigned int mark = pfc->info->func_gpios[offset].enum_id;
-	unsigned long flags;
-	int ret;
-
-	dev_notice_once(pfc->dev,
-			"Use of GPIO API for function requests is deprecated, convert to pinctrl\n");
-
-	if (mark == 0)
-		return -EINVAL;
-
-	spin_lock_irqsave(&pfc->lock, flags);
-	ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION);
-	spin_unlock_irqrestore(&pfc->lock, flags);
-
-	return ret;
-}
-
-static int gpio_function_setup(struct sh_pfc_chip *chip)
-{
-	struct sh_pfc *pfc = chip->pfc;
-	struct gpio_chip *gc = &chip->gpio_chip;
-
-	gc->request = gpio_function_request;
-
-	gc->label = pfc->info->name;
-	gc->owner = THIS_MODULE;
-	gc->base = pfc->nr_gpio_pins;
-	gc->ngpio = pfc->info->nr_func_gpios;
-
-	return 0;
-}
-#endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
-
-/* -----------------------------------------------------------------------------
- * Register/unregister
- */
-
-static struct sh_pfc_chip *
-sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
-		    struct sh_pfc_window *mem)
-{
-	struct sh_pfc_chip *chip;
-	int ret;
-
-	chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL);
-	if (unlikely(!chip))
-		return ERR_PTR(-ENOMEM);
-
-	chip->mem = mem;
-	chip->pfc = pfc;
-
-	ret = setup(chip);
-	if (ret < 0)
-		return ERR_PTR(ret);
-
-	ret = devm_gpiochip_add_data(pfc->dev, &chip->gpio_chip, chip);
-	if (unlikely(ret < 0))
-		return ERR_PTR(ret);
-
-	dev_info(pfc->dev, "%s handling gpio %u -> %u\n",
-		 chip->gpio_chip.label, chip->gpio_chip.base,
-		 chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);
-
-	return chip;
-}
-
-int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
-{
-	struct sh_pfc_chip *chip;
-	phys_addr_t address;
-	unsigned int i;
-
-	if (pfc->info->data_regs == NULL)
-		return 0;
-
-	/* Find the memory window that contain the GPIO registers. Boards that
-	 * register a separate GPIO device will not supply a memory resource
-	 * that covers the data registers. In that case don't try to handle
-	 * GPIOs.
-	 */
-	address = pfc->info->data_regs[0].reg;
-	for (i = 0; i < pfc->num_windows; ++i) {
-		struct sh_pfc_window *window = &pfc->windows[i];
-
-		if (address >= window->phys &&
-		    address < window->phys + window->size)
-			break;
-	}
-
-	if (i == pfc->num_windows)
-		return 0;
-
-	/* If we have IRQ resources make sure their number is correct. */
-	if (pfc->num_irqs != pfc->info->gpio_irq_size) {
-		dev_err(pfc->dev, "invalid number of IRQ resources\n");
-		return -EINVAL;
-	}
-
-	/* Register the real GPIOs chip. */
-	chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->windows[i]);
-	if (IS_ERR(chip))
-		return PTR_ERR(chip);
-
-	pfc->gpio = chip;
-
-	if (IS_ENABLED(CONFIG_OF) && pfc->dev->of_node)
-		return 0;
-
-#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
-	/*
-	 * Register the GPIO to pin mappings. As pins with GPIO ports
-	 * must come first in the ranges, skip the pins without GPIO
-	 * ports by stopping at the first range that contains such a
-	 * pin.
-	 */
-	for (i = 0; i < pfc->nr_ranges; ++i) {
-		const struct sh_pfc_pin_range *range = &pfc->ranges[i];
-		int ret;
-
-		if (range->start >= pfc->nr_gpio_pins)
-			break;
-
-		ret = gpiochip_add_pin_range(&chip->gpio_chip,
-			dev_name(pfc->dev), range->start, range->start,
-			range->end - range->start + 1);
-		if (ret < 0)
-			return ret;
-	}
-
-	/* Register the function GPIOs chip. */
-	if (pfc->info->nr_func_gpios) {
-		chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
-		if (IS_ERR(chip))
-			return PTR_ERR(chip);
-	}
-#endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
-
-	return 0;
-}
diff --git a/drivers/pinctrl/sh-pfc/pfc-emev2.c b/drivers/pinctrl/sh-pfc/pfc-emev2.c
deleted file mode 100644
index 6c66fc335d2f..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-emev2.c
+++ /dev/null
@@ -1,1737 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Pin Function Controller Support
- *
- * Copyright (C) 2015 Niklas Söderlund
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-
-#include "sh_pfc.h"
-
-#define CPU_ALL_PORT(fn, pfx, sfx)					\
-	PORT_10(0,  fn, pfx, sfx),	PORT_90(0,  fn, pfx, sfx),	\
-	PORT_10(100, fn, pfx##10, sfx),	PORT_10(110, fn, pfx##11, sfx),	\
-	PORT_10(120, fn, pfx##12, sfx),	PORT_10(130, fn, pfx##13, sfx),	\
-	PORT_10(140, fn, pfx##14, sfx), PORT_1(150, fn, pfx##150, sfx), \
-	PORT_1(151, fn, pfx##151, sfx), PORT_1(152, fn, pfx##152, sfx), \
-	PORT_1(153, fn, pfx##153, sfx), PORT_1(154, fn, pfx##154, sfx), \
-	PORT_1(155, fn, pfx##155, sfx), PORT_1(156, fn, pfx##156, sfx), \
-	PORT_1(157, fn, pfx##157, sfx), PORT_1(158, fn, pfx##158, sfx)
-
-#define CPU_ALL_NOGP(fn)		\
-	PIN_NOGP(LCD3_B2, "B15", fn),	\
-	PIN_NOGP(LCD3_B3, "C15", fn),	\
-	PIN_NOGP(LCD3_B4, "D15", fn),	\
-	PIN_NOGP(LCD3_B5, "B14", fn),	\
-	PIN_NOGP(LCD3_B6, "C14", fn),	\
-	PIN_NOGP(LCD3_B7, "D14", fn),	\
-	PIN_NOGP(LCD3_G2, "B17", fn),	\
-	PIN_NOGP(LCD3_G3, "C17", fn),	\
-	PIN_NOGP(LCD3_G4, "D17", fn),	\
-	PIN_NOGP(LCD3_G5, "B16", fn),	\
-	PIN_NOGP(LCD3_G6, "C16", fn),	\
-	PIN_NOGP(LCD3_G7, "D16", fn)
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	PORT_ALL(DATA),
-	PINMUX_DATA_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	PORT_ALL(FN),
-
-	/* GPSR0 */
-	FN_LCD3_1_0_PORT18, FN_LCD3_1_0_PORT20, FN_LCD3_1_0_PORT21,
-	FN_LCD3_1_0_PORT22, FN_LCD3_1_0_PORT23,
-	FN_JT_SEL, FN_ERR_RST_REQB, FN_REF_CLKO, FN_EXT_CLKI, FN_LCD3_PXCLKB,
-
-	/* GPSR1 */
-	FN_LCD3_9_8_PORT38, FN_LCD3_9_8_PORT39, FN_LCD3_11_10_PORT40,
-	FN_LCD3_11_10_PORT41, FN_LCD3_11_10_PORT42, FN_LCD3_11_10_PORT43,
-	FN_IIC_1_0_PORT46, FN_IIC_1_0_PORT47,
-	FN_LCD3_R0, FN_LCD3_R1, FN_LCD3_R2, FN_LCD3_R3, FN_LCD3_R4, FN_LCD3_R5,
-	FN_IIC0_SCL, FN_IIC0_SDA, FN_SD_CKI, FN_SDI0_CKO, FN_SDI0_CKI,
-	FN_SDI0_CMD, FN_SDI0_DATA0, FN_SDI0_DATA1, FN_SDI0_DATA2,
-	FN_SDI0_DATA3, FN_SDI0_DATA4, FN_SDI0_DATA5, FN_SDI0_DATA6,
-	FN_SDI0_DATA7, FN_SDI1_CKO, FN_SDI1_CKI, FN_SDI1_CMD,
-
-	/* GPSR2 */
-	FN_AB_1_0_PORT71, FN_AB_1_0_PORT72, FN_AB_1_0_PORT73,
-	FN_AB_1_0_PORT74, FN_AB_1_0_PORT75, FN_AB_1_0_PORT76,
-	FN_AB_1_0_PORT77, FN_AB_1_0_PORT78, FN_AB_1_0_PORT79,
-	FN_AB_1_0_PORT80, FN_AB_1_0_PORT81, FN_AB_1_0_PORT82,
-	FN_AB_1_0_PORT83, FN_AB_1_0_PORT84, FN_AB_3_2_PORT85,
-	FN_AB_3_2_PORT86, FN_AB_3_2_PORT87, FN_AB_3_2_PORT88,
-	FN_AB_5_4_PORT89, FN_AB_5_4_PORT90, FN_AB_7_6_PORT91,
-	FN_AB_7_6_PORT92, FN_AB_1_0_PORT93, FN_AB_1_0_PORT94,
-	FN_AB_1_0_PORT95,
-	FN_SDI1_DATA0, FN_SDI1_DATA1, FN_SDI1_DATA2, FN_SDI1_DATA3,
-	FN_AB_CLK, FN_AB_CSB0, FN_AB_CSB1,
-
-	/* GPSR3 */
-	FN_AB_13_12_PORT104, FN_AB_13_12_PORT103, FN_AB_11_10_PORT102,
-	FN_AB_11_10_PORT101, FN_AB_11_10_PORT100, FN_AB_9_8_PORT99,
-	FN_AB_9_8_PORT98, FN_AB_9_8_PORT97,
-	FN_USI_1_0_PORT109, FN_USI_1_0_PORT110, FN_USI_1_0_PORT111,
-	FN_USI_1_0_PORT112, FN_USI_3_2_PORT113, FN_USI_3_2_PORT114,
-	FN_USI_5_4_PORT115, FN_USI_5_4_PORT116, FN_USI_5_4_PORT117,
-	FN_USI_5_4_PORT118, FN_USI_7_6_PORT119, FN_USI_9_8_PORT120,
-	FN_USI_9_8_PORT121,
-	FN_AB_A20, FN_USI0_CS1, FN_USI0_CS2, FN_USI1_DI,
-	FN_USI1_DO,
-	FN_NTSC_CLK, FN_NTSC_DATA0, FN_NTSC_DATA1, FN_NTSC_DATA2,
-	FN_NTSC_DATA3, FN_NTSC_DATA4,
-
-	/* GPRS4 */
-	FN_HSI_1_0_PORT143, FN_HSI_1_0_PORT144, FN_HSI_1_0_PORT145,
-	FN_HSI_1_0_PORT146, FN_HSI_1_0_PORT147, FN_HSI_1_0_PORT148,
-	FN_HSI_1_0_PORT149, FN_HSI_1_0_PORT150,
-	FN_UART_1_0_PORT157, FN_UART_1_0_PORT158,
-	FN_NTSC_DATA5, FN_NTSC_DATA6, FN_NTSC_DATA7, FN_CAM_CLKO,
-	FN_CAM_CLKI, FN_CAM_VS, FN_CAM_HS, FN_CAM_YUV0,
-	FN_CAM_YUV1, FN_CAM_YUV2, FN_CAM_YUV3, FN_CAM_YUV4,
-	FN_CAM_YUV5, FN_CAM_YUV6, FN_CAM_YUV7,
-	FN_JT_TDO, FN_JT_TDOEN, FN_LOWPWR, FN_USB_VBUS, FN_UART1_RX,
-	FN_UART1_TX,
-
-	/* CHG_PINSEL_LCD3 */
-	FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01,
-	FN_SEL_LCD3_9_8_00, FN_SEL_LCD3_9_8_10,
-	FN_SEL_LCD3_11_10_00, FN_SEL_LCD3_11_10_01, FN_SEL_LCD3_11_10_10,
-
-	/* CHG_PINSEL_IIC */
-	FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01,
-
-	/* CHG_PINSEL_AB */
-	FN_SEL_AB_1_0_00, FN_SEL_AB_1_0_10, FN_SEL_AB_3_2_00,
-	FN_SEL_AB_3_2_01, FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11,
-	FN_SEL_AB_5_4_00, FN_SEL_AB_5_4_01, FN_SEL_AB_5_4_10,
-	FN_SEL_AB_5_4_11, FN_SEL_AB_7_6_00, FN_SEL_AB_7_6_01,
-	FN_SEL_AB_7_6_10,
-	FN_SEL_AB_9_8_00, FN_SEL_AB_9_8_01, FN_SEL_AB_9_8_10,
-	FN_SEL_AB_11_10_00, FN_SEL_AB_11_10_10,
-	FN_SEL_AB_13_12_00, FN_SEL_AB_13_12_10,
-
-	/* CHG_PINSEL_USI */
-	FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01,
-	FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01,
-	FN_SEL_USI_5_4_00, FN_SEL_USI_5_4_01,
-	FN_SEL_USI_7_6_00, FN_SEL_USI_7_6_01,
-	FN_SEL_USI_9_8_00, FN_SEL_USI_9_8_01,
-
-	/* CHG_PINSEL_HSI */
-	FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01,
-
-	/* CHG_PINSEL_UART */
-	FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01,
-
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-
-	/* GPSR0 */
-	JT_SEL_MARK, ERR_RST_REQB_MARK, REF_CLKO_MARK, EXT_CLKI_MARK,
-	LCD3_PXCLKB_MARK, SD_CKI_MARK,
-
-	/* GPSR1 */
-	LCD3_R0_MARK, LCD3_R1_MARK, LCD3_R2_MARK, LCD3_R3_MARK, LCD3_R4_MARK,
-	LCD3_R5_MARK, IIC0_SCL_MARK, IIC0_SDA_MARK, SDI0_CKO_MARK,
-	SDI0_CKI_MARK, SDI0_CMD_MARK, SDI0_DATA0_MARK, SDI0_DATA1_MARK,
-	SDI0_DATA2_MARK, SDI0_DATA3_MARK, SDI0_DATA4_MARK, SDI0_DATA5_MARK,
-	SDI0_DATA6_MARK, SDI0_DATA7_MARK, SDI1_CKO_MARK, SDI1_CKI_MARK,
-	SDI1_CMD_MARK,
-
-	/* GPSR2 */
-	SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK,
-	AB_CLK_MARK, AB_CSB0_MARK, AB_CSB1_MARK,
-
-	/* GPSR3 */
-	AB_A20_MARK, USI0_CS1_MARK, USI0_CS2_MARK, USI1_DI_MARK,
-	USI1_DO_MARK,
-	NTSC_CLK_MARK, NTSC_DATA0_MARK, NTSC_DATA1_MARK, NTSC_DATA2_MARK,
-	NTSC_DATA3_MARK, NTSC_DATA4_MARK,
-
-	/* GPSR3 */
-	NTSC_DATA5_MARK, NTSC_DATA6_MARK, NTSC_DATA7_MARK, CAM_CLKO_MARK,
-	CAM_CLKI_MARK, CAM_VS_MARK, CAM_HS_MARK, CAM_YUV0_MARK,
-	CAM_YUV1_MARK, CAM_YUV2_MARK, CAM_YUV3_MARK, CAM_YUV4_MARK,
-	CAM_YUV5_MARK, CAM_YUV6_MARK, CAM_YUV7_MARK,
-	JT_TDO_MARK, JT_TDOEN_MARK, USB_VBUS_MARK, LOWPWR_MARK,
-	UART1_RX_MARK, UART1_TX_MARK,
-
-	/* CHG_PINSEL_LCD3 */
-	LCD3_PXCLK_MARK, LCD3_CLK_I_MARK, LCD3_HS_MARK, LCD3_VS_MARK,
-	LCD3_DE_MARK, LCD3_R6_MARK, LCD3_R7_MARK, LCD3_G0_MARK, LCD3_G1_MARK,
-	LCD3_G2_MARK, LCD3_G3_MARK, LCD3_G4_MARK, LCD3_G5_MARK, LCD3_G6_MARK,
-	LCD3_G7_MARK, LCD3_B0_MARK, LCD3_B1_MARK, LCD3_B2_MARK, LCD3_B3_MARK,
-	LCD3_B4_MARK, LCD3_B5_MARK, LCD3_B6_MARK, LCD3_B7_MARK,
-	YUV3_CLK_O_MARK, YUV3_CLK_I_MARK, YUV3_HS_MARK, YUV3_VS_MARK,
-	YUV3_DE_MARK, YUV3_D0_MARK, YUV3_D1_MARK, YUV3_D2_MARK, YUV3_D3_MARK,
-	YUV3_D4_MARK, YUV3_D5_MARK, YUV3_D6_MARK, YUV3_D7_MARK, YUV3_D8_MARK,
-	YUV3_D9_MARK, YUV3_D10_MARK, YUV3_D11_MARK, YUV3_D12_MARK,
-	YUV3_D13_MARK, YUV3_D14_MARK, YUV3_D15_MARK,
-	TP33_CLK_MARK, TP33_CTRL_MARK, TP33_DATA0_MARK, TP33_DATA1_MARK,
-	TP33_DATA2_MARK, TP33_DATA3_MARK, TP33_DATA4_MARK, TP33_DATA5_MARK,
-	TP33_DATA6_MARK, TP33_DATA7_MARK, TP33_DATA8_MARK, TP33_DATA9_MARK,
-	TP33_DATA10_MARK, TP33_DATA11_MARK, TP33_DATA12_MARK, TP33_DATA13_MARK,
-	TP33_DATA14_MARK, TP33_DATA15_MARK,
-
-	/* CHG_PINSEL_IIC */
-	IIC1_SCL_MARK, IIC1_SDA_MARK, UART3_RX_MARK, UART3_TX_MARK,
-
-	/* CHG_PINSEL_AB */
-	AB_CSB2_MARK, AB_CSB3_MARK, AB_RDB_MARK, AB_WRB_MARK,
-	AB_WAIT_MARK, AB_ADV_MARK, AB_AD0_MARK, AB_AD1_MARK,
-	AB_AD2_MARK, AB_AD3_MARK, AB_AD4_MARK, AB_AD5_MARK,
-	AB_AD6_MARK, AB_AD7_MARK, AB_AD8_MARK, AB_AD9_MARK,
-	AB_AD10_MARK, AB_AD11_MARK, AB_AD12_MARK, AB_AD13_MARK,
-	AB_AD14_MARK, AB_AD15_MARK, AB_A17_MARK, AB_A18_MARK,
-	AB_A19_MARK, AB_A21_MARK, AB_A22_MARK, AB_A23_MARK,
-	AB_A24_MARK, AB_A25_MARK, AB_A26_MARK, AB_A27_MARK,
-	AB_A28_MARK, AB_BEN0_MARK, AB_BEN1_MARK,
-	DTV_BCLK_A_MARK, DTV_PSYNC_A_MARK, DTV_VALID_A_MARK,
-	DTV_DATA_A_MARK,
-	SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK,
-	SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK,
-	SDI2_DATA3_MARK,
-	CF_CSB0_MARK, CF_CSB1_MARK, CF_IORDB_MARK,
-	CF_IOWRB_MARK, CF_IORDY_MARK, CF_RESET_MARK,
-	CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
-	CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
-	CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK,
-	CF_D12_MARK, CF_D13_MARK, CF_D14_MARK, CF_D15_MARK,
-	CF_A00_MARK, CF_A01_MARK, CF_A02_MARK,
-	CF_INTRQ_MARK, CF_INPACKB_MARK, CF_CDB1_MARK, CF_CDB2_MARK,
-	USI5_CLK_A_MARK, USI5_DI_A_MARK, USI5_DO_A_MARK,
-	USI5_CS0_A_MARK, USI5_CS1_A_MARK, USI5_CS2_A_MARK,
-
-	/* CHG_PINSEL_USI */
-	USI0_CS3_MARK, USI0_CS4_MARK, USI0_CS5_MARK,
-	USI0_CS6_MARK,
-	USI2_CLK_MARK, USI2_DI_MARK, USI2_DO_MARK,
-	USI2_CS0_MARK, USI2_CS1_MARK, USI2_CS2_MARK,
-	USI3_CLK_MARK, USI3_DI_MARK, USI3_DO_MARK,
-	USI3_CS0_MARK,
-	USI4_CLK_MARK, USI4_DI_MARK, USI4_DO_MARK,
-	USI4_CS0_MARK, USI4_CS1_MARK,
-	PWM0_MARK, PWM1_MARK,
-	DTV_BCLK_B_MARK, DTV_PSYNC_B_MARK, DTV_VALID_B_MARK,
-	DTV_DATA_B_MARK,
-
-	/* CHG_PINSEL_HSI */
-	USI5_CLK_B_MARK, USI5_DO_B_MARK, USI5_CS0_B_MARK, USI5_CS1_B_MARK,
-	USI5_CS2_B_MARK, USI5_CS3_B_MARK, USI5_CS4_B_MARK, USI5_DI_B_MARK,
-
-	/* CHG_PINSEL_UART */
-	UART1_CTSB_MARK, UART1_RTSB_MARK,
-	UART2_RX_MARK, UART2_TX_MARK,
-
-	PINMUX_MARK_END,
-};
-
-/*
- * Pins not associated with a GPIO port.
- */
-enum {
-	PORT_ASSIGN_LAST(),
-	NOGP_ALL(),
-};
-
-/* Expand to a list of sh_pfc_pin entries (named PORT#).
- * NOTE: No config are recorded since the driver do not handle pinconf. */
-#define __PIN_CFG(pn, pfx, sfx)  SH_PFC_PIN_CFG(pfx, 0)
-#define PINMUX_EMEV_GPIO_ALL()	  CPU_ALL_PORT(__PIN_CFG, , unused)
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	PINMUX_EMEV_GPIO_ALL(),
-	PINMUX_NOGP_ALL(),
-};
-
-/* Expand to a list of name_DATA, name_FN marks */
-#define __PORT_DATA(pn, pfx, sfx)  PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN)
-#define PINMUX_EMEV_DATA_ALL()	  CPU_ALL_PORT(__PORT_DATA, , unused)
-
-static const u16 pinmux_data[] = {
-	PINMUX_EMEV_DATA_ALL(), /* PINMUX_DATA(PORTN_DATA, PORTN_FN), */
-
-	/* GPSR0 */
-	/* V9 */
-	PINMUX_SINGLE(JT_SEL),
-	/* U9 */
-	PINMUX_SINGLE(ERR_RST_REQB),
-	/* V8 */
-	PINMUX_SINGLE(REF_CLKO),
-	/* U8 */
-	PINMUX_SINGLE(EXT_CLKI),
-	/* B22*/
-	PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, LCD3_PXCLK, SEL_LCD3_1_0_00),
-	PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, YUV3_CLK_O, SEL_LCD3_1_0_01),
-	/* C21 */
-	PINMUX_SINGLE(LCD3_PXCLKB),
-	/* A21 */
-	PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, LCD3_CLK_I, SEL_LCD3_1_0_00),
-	PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, YUV3_CLK_I, SEL_LCD3_1_0_01),
-	/* B21 */
-	PINMUX_IPSR_NOFN(LCD3_1_0_PORT21, LCD3_HS, SEL_LCD3_1_0_00),
-	PINMUX_IPSR_NOFN(LCD3_1_0_PORT21, YUV3_HS, SEL_LCD3_1_0_01),
-	/* C20 */
-	PINMUX_IPSR_NOFN(LCD3_1_0_PORT22, LCD3_VS, SEL_LCD3_1_0_00),
-	PINMUX_IPSR_NOFN(LCD3_1_0_PORT22, YUV3_VS, SEL_LCD3_1_0_01),
-	/* D19 */
-	PINMUX_IPSR_NOFN(LCD3_1_0_PORT23, LCD3_DE, SEL_LCD3_1_0_00),
-	PINMUX_IPSR_NOFN(LCD3_1_0_PORT23, YUV3_DE, SEL_LCD3_1_0_01),
-
-	/* GPSR1 */
-	/* A20 */
-	PINMUX_SINGLE(LCD3_R0),
-	/* B20 */
-	PINMUX_SINGLE(LCD3_R1),
-	/* A19 */
-	PINMUX_SINGLE(LCD3_R2),
-	/* B19 */
-	PINMUX_SINGLE(LCD3_R3),
-	/* C19 */
-	PINMUX_SINGLE(LCD3_R4),
-	/* B18 */
-	PINMUX_SINGLE(LCD3_R5),
-	/* C18 */
-	PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, LCD3_R6, SEL_LCD3_9_8_00),
-	PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, TP33_CLK, SEL_LCD3_9_8_10),
-	/* D18 */
-	PINMUX_IPSR_NOFN(LCD3_9_8_PORT39, LCD3_R7, SEL_LCD3_9_8_00),
-	PINMUX_IPSR_NOFN(LCD3_9_8_PORT39, TP33_CTRL, SEL_LCD3_9_8_10),
-	/* A18 */
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, LCD3_G0, SEL_LCD3_11_10_00),
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, YUV3_D0, SEL_LCD3_11_10_01),
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, TP33_DATA0, SEL_LCD3_11_10_10),
-	/* A17 */
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, LCD3_G1, SEL_LCD3_11_10_00),
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, YUV3_D1, SEL_LCD3_11_10_01),
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, TP33_DATA1, SEL_LCD3_11_10_10),
-	/* B17 */
-	PINMUX_DATA(LCD3_G2_MARK, FN_SEL_LCD3_11_10_00),
-	PINMUX_DATA(YUV3_D2_MARK, FN_SEL_LCD3_11_10_01),
-	PINMUX_DATA(TP33_DATA2_MARK, FN_SEL_LCD3_11_10_10),
-	/* C17 */
-	PINMUX_DATA(LCD3_G3_MARK, FN_SEL_LCD3_11_10_00),
-	PINMUX_DATA(YUV3_D3_MARK, FN_SEL_LCD3_11_10_01),
-	PINMUX_DATA(TP33_DATA3_MARK, FN_SEL_LCD3_11_10_10),
-	/* D17 */
-	PINMUX_DATA(LCD3_G4_MARK, FN_SEL_LCD3_11_10_00),
-	PINMUX_DATA(YUV3_D4_MARK, FN_SEL_LCD3_11_10_01),
-	PINMUX_DATA(TP33_DATA4_MARK, FN_SEL_LCD3_11_10_10),
-	/* B16 */
-	PINMUX_DATA(LCD3_G5_MARK, FN_SEL_LCD3_11_10_00),
-	PINMUX_DATA(YUV3_D5_MARK, FN_SEL_LCD3_11_10_01),
-	PINMUX_DATA(TP33_DATA5_MARK, FN_SEL_LCD3_11_10_10),
-	/* C16 */
-	PINMUX_DATA(LCD3_G6_MARK, FN_SEL_LCD3_11_10_00),
-	PINMUX_DATA(YUV3_D6_MARK, FN_SEL_LCD3_11_10_01),
-	PINMUX_DATA(TP33_DATA6_MARK, FN_SEL_LCD3_11_10_10),
-	/* D16 */
-	PINMUX_DATA(LCD3_G7_MARK, FN_SEL_LCD3_11_10_00),
-	PINMUX_DATA(YUV3_D7_MARK, FN_SEL_LCD3_11_10_01),
-	PINMUX_DATA(TP33_DATA7_MARK, FN_SEL_LCD3_11_10_10),
-	/* A16 */
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, LCD3_B0, SEL_LCD3_11_10_00),
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, YUV3_D8, SEL_LCD3_11_10_01),
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, TP33_DATA8, SEL_LCD3_11_10_10),
-	/* A15 */
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B1, SEL_LCD3_11_10_00),
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D9, SEL_LCD3_11_10_01),
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA9, SEL_LCD3_11_10_10),
-	/* B15 */
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B2, SEL_LCD3_11_10_00),
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D10, SEL_LCD3_11_10_01),
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA10, SEL_LCD3_11_10_10),
-	/* C15 */
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B3, SEL_LCD3_11_10_00),
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D11, SEL_LCD3_11_10_01),
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA11, SEL_LCD3_11_10_10),
-	/* D15 */
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B4, SEL_LCD3_11_10_00),
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D12, SEL_LCD3_11_10_01),
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA12, SEL_LCD3_11_10_10),
-	/* B14 */
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B5, SEL_LCD3_11_10_00),
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D13, SEL_LCD3_11_10_01),
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA13, SEL_LCD3_11_10_10),
-	/* C14 */
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B6, SEL_LCD3_11_10_00),
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D14, SEL_LCD3_11_10_01),
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA14, SEL_LCD3_11_10_10),
-	/* D14 */
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B7, SEL_LCD3_11_10_00),
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D15, SEL_LCD3_11_10_01),
-	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA15, SEL_LCD3_11_10_10),
-	/* AA9 */
-	PINMUX_SINGLE(IIC0_SCL),
-	/* AA8 */
-	PINMUX_SINGLE(IIC0_SDA),
-	/* Y9 */
-	PINMUX_IPSR_NOFN(IIC_1_0_PORT46, IIC1_SCL, SEL_IIC_1_0_00),
-	PINMUX_IPSR_NOFN(IIC_1_0_PORT46, UART3_RX, SEL_IIC_1_0_01),
-	/* Y8 */
-	PINMUX_IPSR_NOFN(IIC_1_0_PORT47, IIC1_SDA, SEL_IIC_1_0_00),
-	PINMUX_IPSR_NOFN(IIC_1_0_PORT47, UART3_TX, SEL_IIC_1_0_01),
-	/* AC19 */
-	PINMUX_SINGLE(SD_CKI),
-	/* AB18 */
-	PINMUX_SINGLE(SDI0_CKO),
-	/* AC18 */
-	PINMUX_SINGLE(SDI0_CKI),
-	/* Y12 */
-	PINMUX_SINGLE(SDI0_CMD),
-	/* AA13 */
-	PINMUX_SINGLE(SDI0_DATA0),
-	/* Y13 */
-	PINMUX_SINGLE(SDI0_DATA1),
-	/* AA14 */
-	PINMUX_SINGLE(SDI0_DATA2),
-	/* Y14 */
-	PINMUX_SINGLE(SDI0_DATA3),
-	/* AA15 */
-	PINMUX_SINGLE(SDI0_DATA4),
-	/* Y15 */
-	PINMUX_SINGLE(SDI0_DATA5),
-	/* AA16 */
-	PINMUX_SINGLE(SDI0_DATA6),
-	/* Y16 */
-	PINMUX_SINGLE(SDI0_DATA7),
-	/* AB22 */
-	PINMUX_SINGLE(SDI1_CKO),
-	/* AA23 */
-	PINMUX_SINGLE(SDI1_CKI),
-	/* AC21 */
-	PINMUX_SINGLE(SDI1_CMD),
-
-	/* GPSR2 */
-	/* AB21 */
-	PINMUX_SINGLE(SDI1_DATA0),
-	/* AB20 */
-	PINMUX_SINGLE(SDI1_DATA1),
-	/* AB19 */
-	PINMUX_SINGLE(SDI1_DATA2),
-	/* AA19 */
-	PINMUX_SINGLE(SDI1_DATA3),
-	/* J23 */
-	PINMUX_SINGLE(AB_CLK),
-	/* D21 */
-	PINMUX_SINGLE(AB_CSB0),
-	/* E21 */
-	PINMUX_SINGLE(AB_CSB1),
-	/* F20 */
-	PINMUX_IPSR_NOFN(AB_1_0_PORT71, AB_CSB2, SEL_AB_1_0_00),
-	PINMUX_IPSR_NOFN(AB_1_0_PORT71, CF_CSB0, SEL_AB_1_0_10),
-	/* G20 */
-	PINMUX_IPSR_NOFN(AB_1_0_PORT72, AB_CSB3, SEL_AB_1_0_00),
-	PINMUX_IPSR_NOFN(AB_1_0_PORT72, CF_CSB1, SEL_AB_1_0_10),
-	/* J20 */
-	PINMUX_IPSR_NOFN(AB_1_0_PORT73, AB_RDB, SEL_AB_1_0_00),
-	PINMUX_IPSR_NOFN(AB_1_0_PORT73, CF_IORDB, SEL_AB_1_0_10),
-	/* H20 */
-	PINMUX_IPSR_NOFN(AB_1_0_PORT74, AB_WRB, SEL_AB_1_0_00),
-	PINMUX_IPSR_NOFN(AB_1_0_PORT74, CF_IOWRB, SEL_AB_1_0_10),
-	/* L20 */
-	PINMUX_IPSR_NOFN(AB_1_0_PORT75, AB_WAIT, SEL_AB_1_0_00),
-	PINMUX_IPSR_NOFN(AB_1_0_PORT75, CF_IORDY, SEL_AB_1_0_10),
-	/* K20 */
-	PINMUX_IPSR_NOFN(AB_1_0_PORT76, AB_ADV, SEL_AB_1_0_00),
-	PINMUX_IPSR_NOFN(AB_1_0_PORT76, CF_RESET, SEL_AB_1_0_10),
-	/* C23 */
-	PINMUX_IPSR_NOFN(AB_1_0_PORT77, AB_AD0, SEL_AB_1_0_00),
-	PINMUX_IPSR_NOFN(AB_1_0_PORT77, CF_D00, SEL_AB_1_0_10),
-	/* C22 */
-	PINMUX_IPSR_NOFN(AB_1_0_PORT78, AB_AD1, SEL_AB_1_0_00),
-	PINMUX_IPSR_NOFN(AB_1_0_PORT78, CF_D01, SEL_AB_1_0_10),
-	/* D23 */
-	PINMUX_IPSR_NOFN(AB_1_0_PORT79, AB_AD2, SEL_AB_1_0_00),
-	PINMUX_IPSR_NOFN(AB_1_0_PORT79, CF_D02, SEL_AB_1_0_10),
-	/* D22 */
-	PINMUX_IPSR_NOFN(AB_1_0_PORT80, AB_AD3, SEL_AB_1_0_00),
-	PINMUX_IPSR_NOFN(AB_1_0_PORT80, CF_D03, SEL_AB_1_0_10),
-	/* E23 */
-	PINMUX_IPSR_NOFN(AB_1_0_PORT81, AB_AD4, SEL_AB_1_0_00),
-	PINMUX_IPSR_NOFN(AB_1_0_PORT81, CF_D04, SEL_AB_1_0_10),
-	/* E22 */
-	PINMUX_IPSR_NOFN(AB_1_0_PORT82, AB_AD5, SEL_AB_1_0_00),
-	PINMUX_IPSR_NOFN(AB_1_0_PORT82, CF_D05, SEL_AB_1_0_10),
-	/* F23 */
-	PINMUX_IPSR_NOFN(AB_1_0_PORT83, AB_AD6, SEL_AB_1_0_00),
-	PINMUX_IPSR_NOFN(AB_1_0_PORT83, CF_D06, SEL_AB_1_0_10),
-	/* F22 */
-	PINMUX_IPSR_NOFN(AB_1_0_PORT84, AB_AD7, SEL_AB_1_0_00),
-	PINMUX_IPSR_NOFN(AB_1_0_PORT84, CF_D07, SEL_AB_1_0_10),
-	/* F21 */
-	PINMUX_IPSR_NOFN(AB_3_2_PORT85, AB_AD8, SEL_AB_3_2_00),
-	PINMUX_IPSR_NOFN(AB_3_2_PORT85, DTV_BCLK_A, SEL_AB_3_2_01),
-	PINMUX_IPSR_NOFN(AB_3_2_PORT85, CF_D08, SEL_AB_3_2_10),
-	PINMUX_IPSR_NOFN(AB_3_2_PORT85, USI5_CLK_A, SEL_AB_3_2_11),
-	/* G23 */
-	PINMUX_IPSR_NOFN(AB_3_2_PORT86, AB_AD9, SEL_AB_3_2_00),
-	PINMUX_IPSR_NOFN(AB_3_2_PORT86, DTV_PSYNC_A, SEL_AB_3_2_01),
-	PINMUX_IPSR_NOFN(AB_3_2_PORT86, CF_D09, SEL_AB_3_2_10),
-	PINMUX_IPSR_NOFN(AB_3_2_PORT86, USI5_DI_A, SEL_AB_3_2_11),
-	/* G22 */
-	PINMUX_IPSR_NOFN(AB_3_2_PORT87, AB_AD10, SEL_AB_3_2_00),
-	PINMUX_IPSR_NOFN(AB_3_2_PORT87, DTV_VALID_A, SEL_AB_3_2_01),
-	PINMUX_IPSR_NOFN(AB_3_2_PORT87, CF_D10, SEL_AB_3_2_10),
-	PINMUX_IPSR_NOFN(AB_3_2_PORT87, USI5_DO_A, SEL_AB_3_2_11),
-	/* G21 */
-	PINMUX_IPSR_NOFN(AB_3_2_PORT88, AB_AD11, SEL_AB_3_2_00),
-	PINMUX_IPSR_NOFN(AB_3_2_PORT88, DTV_DATA_A, SEL_AB_3_2_01),
-	PINMUX_IPSR_NOFN(AB_3_2_PORT88, CF_D11, SEL_AB_3_2_10),
-	PINMUX_IPSR_NOFN(AB_3_2_PORT88, USI5_CS0_A, SEL_AB_3_2_11),
-	/* H23 */
-	PINMUX_IPSR_NOFN(AB_5_4_PORT89, AB_AD12, SEL_AB_5_4_00),
-	PINMUX_IPSR_NOFN(AB_5_4_PORT89, SDI2_DATA0, SEL_AB_5_4_01),
-	PINMUX_IPSR_NOFN(AB_5_4_PORT89, CF_D12, SEL_AB_5_4_10),
-	PINMUX_IPSR_NOFN(AB_5_4_PORT89, USI5_CS1_A, SEL_AB_5_4_11),
-	/* H22 */
-	PINMUX_IPSR_NOFN(AB_5_4_PORT90, AB_AD13, SEL_AB_5_4_00),
-	PINMUX_IPSR_NOFN(AB_5_4_PORT90, SDI2_DATA1, SEL_AB_5_4_01),
-	PINMUX_IPSR_NOFN(AB_5_4_PORT90, CF_D13, SEL_AB_5_4_10),
-	PINMUX_IPSR_NOFN(AB_5_4_PORT90, USI5_CS2_A, SEL_AB_5_4_11),
-	/* H21 */
-	PINMUX_IPSR_NOFN(AB_7_6_PORT91, AB_AD14, SEL_AB_7_6_00),
-	PINMUX_IPSR_NOFN(AB_7_6_PORT91, SDI2_DATA2, SEL_AB_7_6_01),
-	PINMUX_IPSR_NOFN(AB_7_6_PORT91, CF_D14, SEL_AB_7_6_10),
-	/* J22 */
-	PINMUX_IPSR_NOFN(AB_7_6_PORT92, AB_AD15, SEL_AB_7_6_00),
-	PINMUX_IPSR_NOFN(AB_7_6_PORT92, SDI2_DATA3, SEL_AB_7_6_01),
-	PINMUX_IPSR_NOFN(AB_7_6_PORT92, CF_D15, SEL_AB_7_6_10),
-	/* J21 */
-	PINMUX_IPSR_NOFN(AB_1_0_PORT93, AB_A17, SEL_AB_1_0_00),
-	PINMUX_IPSR_NOFN(AB_1_0_PORT93, CF_A00, SEL_AB_1_0_10),
-	/* K21 */
-	PINMUX_IPSR_NOFN(AB_1_0_PORT94, AB_A18, SEL_AB_1_0_00),
-	PINMUX_IPSR_NOFN(AB_1_0_PORT94, CF_A01, SEL_AB_1_0_10),
-	/* L21 */
-	PINMUX_IPSR_NOFN(AB_1_0_PORT95, AB_A19, SEL_AB_1_0_00),
-	PINMUX_IPSR_NOFN(AB_1_0_PORT95, CF_A02, SEL_AB_1_0_10),
-
-	/* GPSR3 */
-	/* M21 */
-	PINMUX_SINGLE(AB_A20),
-	/* N21 */
-	PINMUX_IPSR_NOFN(AB_9_8_PORT97, AB_A21, SEL_AB_9_8_00),
-	PINMUX_IPSR_NOFN(AB_9_8_PORT97, SDI2_CKO, SEL_AB_9_8_01),
-	PINMUX_IPSR_NOFN(AB_9_8_PORT97, CF_INTRQ, SEL_AB_9_8_10),
-	/* M20 */
-	PINMUX_IPSR_NOFN(AB_9_8_PORT98, AB_A22, SEL_AB_9_8_00),
-	PINMUX_IPSR_NOFN(AB_9_8_PORT98, SDI2_CKI, SEL_AB_9_8_01),
-	/* N20 */
-	PINMUX_IPSR_NOFN(AB_9_8_PORT99, AB_A23, SEL_AB_9_8_00),
-	PINMUX_IPSR_NOFN(AB_9_8_PORT99, SDI2_CMD, SEL_AB_9_8_01),
-	/* L18 */
-	PINMUX_IPSR_NOFN(AB_11_10_PORT100, AB_A24, SEL_AB_11_10_00),
-	PINMUX_IPSR_NOFN(AB_11_10_PORT100, CF_INPACKB, SEL_AB_11_10_10),
-	/* M18 */
-	PINMUX_IPSR_NOFN(AB_11_10_PORT101, AB_A25, SEL_AB_11_10_00),
-	PINMUX_IPSR_NOFN(AB_11_10_PORT101, CF_CDB1, SEL_AB_11_10_10),
-	/* N18 */
-	PINMUX_IPSR_NOFN(AB_11_10_PORT102, AB_A26, SEL_AB_11_10_00),
-	PINMUX_IPSR_NOFN(AB_11_10_PORT102, CF_CDB2, SEL_AB_11_10_10),
-	/* L17 */
-	PINMUX_IPSR_NOFN(AB_13_12_PORT103, AB_A27, SEL_AB_13_12_00),
-	PINMUX_IPSR_NOFN(AB_13_12_PORT103, AB_BEN0, SEL_AB_13_12_10),
-	/* M17 */
-	PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_A28, SEL_AB_13_12_00),
-	PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_BEN1, SEL_AB_13_12_10),
-	/* B8 */
-	PINMUX_SINGLE(USI0_CS1),
-	/* B9 */
-	PINMUX_SINGLE(USI0_CS2),
-	/* C10 */
-	PINMUX_SINGLE(USI1_DI),
-	/* D10 */
-	PINMUX_SINGLE(USI1_DO),
-	/* AB5 */
-	PINMUX_IPSR_NOFN(USI_1_0_PORT109, USI2_CLK, SEL_USI_1_0_00),
-	PINMUX_IPSR_NOFN(USI_1_0_PORT109, DTV_BCLK_B, SEL_USI_1_0_01),
-	/* AA6 */
-	PINMUX_IPSR_NOFN(USI_1_0_PORT110, USI2_DI, SEL_USI_1_0_00),
-	PINMUX_IPSR_NOFN(USI_1_0_PORT110, DTV_PSYNC_B, SEL_USI_1_0_01),
-	/* AA5 */
-	PINMUX_IPSR_NOFN(USI_1_0_PORT111, USI2_DO, SEL_USI_1_0_00),
-	PINMUX_IPSR_NOFN(USI_1_0_PORT111, DTV_VALID_B, SEL_USI_1_0_01),
-	/* Y7 */
-	PINMUX_IPSR_NOFN(USI_1_0_PORT112, USI2_CS0, SEL_USI_1_0_00),
-	PINMUX_IPSR_NOFN(USI_1_0_PORT112, DTV_DATA_B, SEL_USI_1_0_01),
-	/* AA7 */
-	PINMUX_IPSR_NOFN(USI_3_2_PORT113, USI2_CS1, SEL_USI_3_2_00),
-	PINMUX_IPSR_NOFN(USI_3_2_PORT113, USI4_CS0, SEL_USI_3_2_01),
-	/* Y6 */
-	PINMUX_IPSR_NOFN(USI_3_2_PORT114, USI2_CS2, SEL_USI_3_2_00),
-	PINMUX_IPSR_NOFN(USI_3_2_PORT114, USI4_CS1, SEL_USI_3_2_01),
-	/* AC5 */
-	PINMUX_IPSR_NOFN(USI_5_4_PORT115, USI3_CLK, SEL_USI_5_4_00),
-	PINMUX_IPSR_NOFN(USI_5_4_PORT115, USI0_CS3, SEL_USI_5_4_01),
-	/* AC4 */
-	PINMUX_IPSR_NOFN(USI_5_4_PORT116, USI3_DI, SEL_USI_5_4_00),
-	PINMUX_IPSR_NOFN(USI_5_4_PORT116, USI0_CS4, SEL_USI_5_4_01),
-	/* AC3 */
-	PINMUX_IPSR_NOFN(USI_5_4_PORT117, USI3_DO, SEL_USI_5_4_00),
-	PINMUX_IPSR_NOFN(USI_5_4_PORT117, USI0_CS5, SEL_USI_5_4_01),
-	/* AB4 */
-	PINMUX_IPSR_NOFN(USI_5_4_PORT118, USI3_CS0, SEL_USI_5_4_00),
-	PINMUX_IPSR_NOFN(USI_5_4_PORT118, USI0_CS6, SEL_USI_5_4_01),
-	/* AB3 */
-	PINMUX_IPSR_NOFN(USI_7_6_PORT119, USI4_CLK, SEL_USI_7_6_01),
-	/* AA4 */
-	PINMUX_IPSR_NOFN(USI_9_8_PORT120, PWM0, SEL_USI_9_8_00),
-	PINMUX_IPSR_NOFN(USI_9_8_PORT120, USI4_DI, SEL_USI_9_8_01),
-	/* Y5 */
-	PINMUX_IPSR_NOFN(USI_9_8_PORT121, PWM1, SEL_USI_9_8_00),
-	PINMUX_IPSR_NOFN(USI_9_8_PORT121, USI4_DO, SEL_USI_9_8_01),
-	/* V20 */
-	PINMUX_SINGLE(NTSC_CLK),
-	/* P20 */
-	PINMUX_SINGLE(NTSC_DATA0),
-	/* P18 */
-	PINMUX_SINGLE(NTSC_DATA1),
-	/* R20 */
-	PINMUX_SINGLE(NTSC_DATA2),
-	/* R18 */
-	PINMUX_SINGLE(NTSC_DATA3),
-	/* T20 */
-	PINMUX_SINGLE(NTSC_DATA4),
-
-	/* GPRS3 */
-	/* T18 */
-	PINMUX_SINGLE(NTSC_DATA5),
-	/* U20 */
-	PINMUX_SINGLE(NTSC_DATA6),
-	/* U18 */
-	PINMUX_SINGLE(NTSC_DATA7),
-	/* W23 */
-	PINMUX_SINGLE(CAM_CLKO),
-	/* Y23 */
-	PINMUX_SINGLE(CAM_CLKI),
-	/* W22 */
-	PINMUX_SINGLE(CAM_VS),
-	/* V21 */
-	PINMUX_SINGLE(CAM_HS),
-	/* T21 */
-	PINMUX_SINGLE(CAM_YUV0),
-	/* T22 */
-	PINMUX_SINGLE(CAM_YUV1),
-	/* T23 */
-	PINMUX_SINGLE(CAM_YUV2),
-	/* U21 */
-	PINMUX_SINGLE(CAM_YUV3),
-	/* U22 */
-	PINMUX_SINGLE(CAM_YUV4),
-	/* U23 */
-	PINMUX_SINGLE(CAM_YUV5),
-	/* V22 */
-	PINMUX_SINGLE(CAM_YUV6),
-	/* V23 */
-	PINMUX_SINGLE(CAM_YUV7),
-	/* K22 */
-	PINMUX_IPSR_NOFN(HSI_1_0_PORT143, USI5_CLK_B, SEL_HSI_1_0_01),
-	/* K23 */
-	PINMUX_IPSR_NOFN(HSI_1_0_PORT144, USI5_DO_B, SEL_HSI_1_0_01),
-	/* L23 */
-	PINMUX_IPSR_NOFN(HSI_1_0_PORT145, USI5_CS0_B, SEL_HSI_1_0_01),
-	/* L22 */
-	PINMUX_IPSR_NOFN(HSI_1_0_PORT146, USI5_CS1_B, SEL_HSI_1_0_01),
-	/* N22 */
-	PINMUX_IPSR_NOFN(HSI_1_0_PORT147, USI5_CS2_B, SEL_HSI_1_0_01),
-	/* N23 */
-	PINMUX_IPSR_NOFN(HSI_1_0_PORT148, USI5_CS3_B, SEL_HSI_1_0_01),
-	/* M23 */
-	PINMUX_IPSR_NOFN(HSI_1_0_PORT149, USI5_CS4_B, SEL_HSI_1_0_01),
-	/* M22 */
-	PINMUX_IPSR_NOFN(HSI_1_0_PORT150, USI5_DI_B, SEL_HSI_1_0_01),
-	/* D13 */
-	PINMUX_SINGLE(JT_TDO),
-	/* F13 */
-	PINMUX_SINGLE(JT_TDOEN),
-	/* AA12 */
-	PINMUX_SINGLE(USB_VBUS),
-	/* A12 */
-	PINMUX_SINGLE(LOWPWR),
-	/* Y11 */
-	PINMUX_SINGLE(UART1_RX),
-	/* Y10 */
-	PINMUX_SINGLE(UART1_TX),
-	/* AA10 */
-	PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART1_CTSB, SEL_UART_1_0_00),
-	PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART2_RX, SEL_UART_1_0_01),
-	/* AB10 */
-	PINMUX_IPSR_NOFN(UART_1_0_PORT158, UART1_RTSB, SEL_UART_1_0_00),
-	PINMUX_IPSR_NOFN(UART_1_0_PORT158, UART2_TX, SEL_UART_1_0_01),
-};
-
-
-#define EMEV_MUX_PIN(name, pin, mark) \
-	static const unsigned int name##_pins[] = { pin }; \
-	static const unsigned int name##_mux[] = { mark##_MARK }
-
-/* = [ System ] =========== */
-EMEV_MUX_PIN(err_rst_reqb, 3, ERR_RST_REQB);
-EMEV_MUX_PIN(ref_clko, 4, REF_CLKO);
-EMEV_MUX_PIN(ext_clki, 5, EXT_CLKI);
-EMEV_MUX_PIN(lowpwr, 154, LOWPWR);
-
-/* = [ External Memory] === */
-static const unsigned int ab_main_pins[] = {
-	/* AB_RDB, AB_WRB */
-	73, 74,
-	/* AB_AD[0:15] */
-	77, 78, 79, 80,
-	81, 82, 83, 84,
-	85, 86, 87, 88,
-	89, 90, 91, 92,
-};
-static const unsigned int ab_main_mux[] = {
-	AB_RDB_MARK, AB_WRB_MARK,
-	AB_AD0_MARK, AB_AD1_MARK, AB_AD2_MARK, AB_AD3_MARK,
-	AB_AD4_MARK, AB_AD5_MARK, AB_AD6_MARK, AB_AD7_MARK,
-	AB_AD8_MARK, AB_AD9_MARK, AB_AD10_MARK, AB_AD11_MARK,
-	AB_AD12_MARK, AB_AD13_MARK, AB_AD14_MARK, AB_AD15_MARK,
-};
-
-EMEV_MUX_PIN(ab_clk, 68, AB_CLK);
-EMEV_MUX_PIN(ab_csb0, 69, AB_CSB0);
-EMEV_MUX_PIN(ab_csb1, 70, AB_CSB1);
-EMEV_MUX_PIN(ab_csb2, 71, AB_CSB2);
-EMEV_MUX_PIN(ab_csb3, 72, AB_CSB3);
-EMEV_MUX_PIN(ab_wait, 75, AB_WAIT);
-EMEV_MUX_PIN(ab_adv, 76, AB_ADV);
-EMEV_MUX_PIN(ab_a17, 93, AB_A17);
-EMEV_MUX_PIN(ab_a18, 94, AB_A18);
-EMEV_MUX_PIN(ab_a19, 95, AB_A19);
-EMEV_MUX_PIN(ab_a20, 96, AB_A20);
-EMEV_MUX_PIN(ab_a21, 97, AB_A21);
-EMEV_MUX_PIN(ab_a22, 98, AB_A22);
-EMEV_MUX_PIN(ab_a23, 99, AB_A23);
-EMEV_MUX_PIN(ab_a24, 100, AB_A24);
-EMEV_MUX_PIN(ab_a25, 101, AB_A25);
-EMEV_MUX_PIN(ab_a26, 102, AB_A26);
-EMEV_MUX_PIN(ab_a27, 103, AB_A27);
-EMEV_MUX_PIN(ab_a28, 104, AB_A28);
-EMEV_MUX_PIN(ab_ben0, 103, AB_BEN0);
-EMEV_MUX_PIN(ab_ben1, 104, AB_BEN1);
-
-/* = [ CAM ] ============== */
-EMEV_MUX_PIN(cam_clko, 131, CAM_CLKO);
-static const unsigned int cam_pins[] = {
-	/* CLKI, VS, HS */
-	132, 133, 134,
-	/* CAM_YUV[0:7] */
-	135, 136, 137, 138,
-	139, 140, 141, 142,
-};
-static const unsigned int cam_mux[] = {
-	CAM_CLKI_MARK, CAM_VS_MARK, CAM_HS_MARK,
-	CAM_YUV0_MARK, CAM_YUV1_MARK, CAM_YUV2_MARK, CAM_YUV3_MARK,
-	CAM_YUV4_MARK, CAM_YUV5_MARK, CAM_YUV6_MARK, CAM_YUV7_MARK,
-};
-
-/* = [ CF ] -============== */
-static const unsigned int cf_ctrl_pins[] = {
-	/* CSB0, CSB1, IORDB, IOWRB, IORDY, RESET,
-	 * A00, A01, A02, INTRQ, INPACKB, CDB1, CDB2 */
-	71, 72, 73, 74,
-	75, 76, 93, 94,
-	95, 97, 100, 101,
-	102,
-};
-static const unsigned int cf_ctrl_mux[] = {
-	CF_CSB0_MARK, CF_CSB1_MARK, CF_IORDB_MARK, CF_IOWRB_MARK,
-	CF_IORDY_MARK, CF_RESET_MARK, CF_A00_MARK, CF_A01_MARK,
-	CF_A02_MARK, CF_INTRQ_MARK, CF_INPACKB_MARK, CF_CDB1_MARK,
-	CF_CDB2_MARK,
-};
-
-static const unsigned int cf_data8_pins[] = {
-	/* CF_D[0:7] */
-	77, 78, 79, 80,
-	81, 82, 83, 84,
-};
-static const unsigned int cf_data8_mux[] = {
-	CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
-	CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
-};
-static const unsigned int cf_data16_pins[] = {
-	/* CF_D[0:15] */
-	77, 78, 79, 80,
-	81, 82, 83, 84,
-	85, 86, 87, 88,
-	89, 90, 91, 92,
-};
-static const unsigned int cf_data16_mux[] = {
-	CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
-	CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
-	CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK,
-	CF_D12_MARK, CF_D13_MARK, CF_D14_MARK, CF_D15_MARK,
-};
-
-/* = [ DTV ] ============== */
-static const unsigned int dtv_a_pins[] = {
-	/* BCLK, PSYNC, VALID, DATA */
-	85, 86, 87, 88,
-};
-static const unsigned int dtv_a_mux[] = {
-	DTV_BCLK_A_MARK, DTV_PSYNC_A_MARK, DTV_VALID_A_MARK, DTV_DATA_A_MARK,
-};
-
-static const unsigned int dtv_b_pins[] = {
-	/* BCLK, PSYNC, VALID, DATA */
-	109, 110, 111, 112,
-};
-static const unsigned int dtv_b_mux[] = {
-	DTV_BCLK_B_MARK, DTV_PSYNC_B_MARK, DTV_VALID_B_MARK, DTV_DATA_B_MARK,
-};
-
-/* = [ IIC0 ] ============= */
-static const unsigned int iic0_pins[] = {
-	/* SCL, SDA */
-	44, 45,
-};
-static const unsigned int iic0_mux[] = {
-	IIC0_SCL_MARK, IIC0_SDA_MARK,
-};
-
-/* = [ IIC1 ] ============= */
-static const unsigned int iic1_pins[] = {
-	/* SCL, SDA */
-	46, 47,
-};
-static const unsigned int iic1_mux[] = {
-	IIC1_SCL_MARK, IIC1_SDA_MARK,
-};
-
-/* = [ JTAG ] ============= */
-static const unsigned int jtag_pins[] = {
-	/* SEL, TDO, TDOEN */
-	2, 151, 152,
-};
-static const unsigned int jtag_mux[] = {
-	JT_SEL_MARK, JT_TDO_MARK, JT_TDOEN_MARK,
-};
-
-/* = [ LCD/YUV ] ========== */
-EMEV_MUX_PIN(lcd3_pxclk, 18, LCD3_PXCLK);
-EMEV_MUX_PIN(lcd3_pxclkb, 19, LCD3_PXCLKB);
-EMEV_MUX_PIN(lcd3_clk_i, 20, LCD3_CLK_I);
-
-static const unsigned int lcd3_sync_pins[] = {
-	/* HS, VS, DE */
-	21, 22, 23,
-};
-static const unsigned int lcd3_sync_mux[] = {
-	LCD3_HS_MARK, LCD3_VS_MARK, LCD3_DE_MARK,
-};
-
-static const unsigned int lcd3_rgb888_pins[] = {
-	/* R[0:7], G[0:7], B[0:7] */
-	32, 33, 34, 35,
-	36, 37, 38, 39,
-	40, 41, PIN_LCD3_G2, PIN_LCD3_G3,
-	PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7,
-	42, 43, PIN_LCD3_B2, PIN_LCD3_B3,
-	PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7
-};
-static const unsigned int lcd3_rgb888_mux[] = {
-	LCD3_R0_MARK, LCD3_R1_MARK, LCD3_R2_MARK, LCD3_R3_MARK,
-	LCD3_R4_MARK, LCD3_R5_MARK, LCD3_R6_MARK, LCD3_R7_MARK,
-	LCD3_G0_MARK, LCD3_G1_MARK, LCD3_G2_MARK, LCD3_G3_MARK,
-	LCD3_G4_MARK, LCD3_G5_MARK, LCD3_G6_MARK, LCD3_G7_MARK,
-	LCD3_B0_MARK, LCD3_B1_MARK, LCD3_B2_MARK, LCD3_B3_MARK,
-	LCD3_B4_MARK, LCD3_B5_MARK, LCD3_B6_MARK, LCD3_B7_MARK,
-};
-
-EMEV_MUX_PIN(yuv3_clk_i, 20, YUV3_CLK_I);
-static const unsigned int yuv3_pins[] = {
-	/* CLK_O, HS, VS, DE */
-	18, 21, 22, 23,
-	/* YUV3_D[0:15] */
-	40, 41, PIN_LCD3_G2, PIN_LCD3_G3,
-	PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7,
-	42, 43, PIN_LCD3_B2, PIN_LCD3_B3,
-	PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7,
-};
-static const unsigned int yuv3_mux[] = {
-	YUV3_CLK_O_MARK, YUV3_HS_MARK, YUV3_VS_MARK, YUV3_DE_MARK,
-	YUV3_D0_MARK, YUV3_D1_MARK, YUV3_D2_MARK, YUV3_D3_MARK,
-	YUV3_D4_MARK, YUV3_D5_MARK, YUV3_D6_MARK, YUV3_D7_MARK,
-	YUV3_D8_MARK, YUV3_D9_MARK, YUV3_D10_MARK, YUV3_D11_MARK,
-	YUV3_D12_MARK, YUV3_D13_MARK, YUV3_D14_MARK, YUV3_D15_MARK,
-};
-
-/* = [ NTSC ] ============= */
-EMEV_MUX_PIN(ntsc_clk, 122, NTSC_CLK);
-static const unsigned int ntsc_data_pins[] = {
-	/* NTSC_DATA[0:7] */
-	123, 124, 125, 126,
-	127, 128, 129, 130,
-};
-static const unsigned int ntsc_data_mux[] = {
-	NTSC_DATA0_MARK, NTSC_DATA1_MARK, NTSC_DATA2_MARK, NTSC_DATA3_MARK,
-	NTSC_DATA4_MARK, NTSC_DATA5_MARK, NTSC_DATA6_MARK, NTSC_DATA7_MARK,
-};
-
-/* = [ PWM0 ] ============= */
-EMEV_MUX_PIN(pwm0, 120, PWM0);
-
-/* = [ PWM1 ] ============= */
-EMEV_MUX_PIN(pwm1, 121, PWM1);
-
-/* = [ SD ] =============== */
-EMEV_MUX_PIN(sd_cki, 48, SD_CKI);
-
-/* = [ SDIO0 ] ============ */
-static const unsigned int sdi0_ctrl_pins[] = {
-	/* CKO, CKI, CMD */
-	50, 51, 52,
-};
-static const unsigned int sdi0_ctrl_mux[] = {
-	SDI0_CKO_MARK, SDI0_CKI_MARK, SDI0_CMD_MARK,
-};
-
-static const unsigned int sdi0_data1_pins[] = {
-	/* SDI0_DATA[0] */
-	53,
-};
-static const unsigned int sdi0_data1_mux[] = {
-	SDI0_DATA0_MARK,
-};
-static const unsigned int sdi0_data4_pins[] = {
-	/* SDI0_DATA[0:3] */
-	53, 54, 55, 56,
-};
-static const unsigned int sdi0_data4_mux[] = {
-	SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK,
-};
-static const unsigned int sdi0_data8_pins[] = {
-	/* SDI0_DATA[0:7] */
-	53, 54, 55, 56,
-	57, 58, 59, 60
-};
-static const unsigned int sdi0_data8_mux[] = {
-	SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK,
-	SDI0_DATA4_MARK, SDI0_DATA5_MARK, SDI0_DATA6_MARK, SDI0_DATA7_MARK,
-};
-
-/* = [ SDIO1 ] ============ */
-static const unsigned int sdi1_ctrl_pins[] = {
-	/* CKO, CKI, CMD */
-	61, 62, 63,
-};
-static const unsigned int sdi1_ctrl_mux[] = {
-	SDI1_CKO_MARK, SDI1_CKI_MARK, SDI1_CMD_MARK,
-};
-
-static const unsigned int sdi1_data1_pins[] = {
-	/* SDI1_DATA[0] */
-	64,
-};
-static const unsigned int sdi1_data1_mux[] = {
-	SDI1_DATA0_MARK,
-};
-static const unsigned int sdi1_data4_pins[] = {
-	/* SDI1_DATA[0:3] */
-	64, 65, 66, 67,
-};
-static const unsigned int sdi1_data4_mux[] = {
-	SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK,
-};
-
-/* = [ SDIO2 ] ============ */
-static const unsigned int sdi2_ctrl_pins[] = {
-	/* CKO, CKI, CMD */
-	97, 98, 99,
-};
-static const unsigned int sdi2_ctrl_mux[] = {
-	SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK,
-};
-
-static const unsigned int sdi2_data1_pins[] = {
-	/* SDI2_DATA[0] */
-	89,
-};
-static const unsigned int sdi2_data1_mux[] = {
-	SDI2_DATA0_MARK,
-};
-static const unsigned int sdi2_data4_pins[] = {
-	/* SDI2_DATA[0:3] */
-	89, 90, 91, 92,
-};
-static const unsigned int sdi2_data4_mux[] = {
-	SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK, SDI2_DATA3_MARK,
-};
-
-/* = [ TP33 ] ============= */
-static const unsigned int tp33_pins[] = {
-	/* CLK, CTRL */
-	38, 39,
-	/* TP33_DATA[0:15] */
-	40, 41, PIN_LCD3_G2, PIN_LCD3_G3,
-	PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7,
-	42, 43, PIN_LCD3_B2, PIN_LCD3_B3,
-	PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7,
-};
-static const unsigned int tp33_mux[] = {
-	TP33_CLK_MARK, TP33_CTRL_MARK,
-	TP33_DATA0_MARK, TP33_DATA1_MARK, TP33_DATA2_MARK, TP33_DATA3_MARK,
-	TP33_DATA4_MARK, TP33_DATA5_MARK, TP33_DATA6_MARK, TP33_DATA7_MARK,
-	TP33_DATA8_MARK, TP33_DATA9_MARK, TP33_DATA10_MARK, TP33_DATA11_MARK,
-	TP33_DATA12_MARK, TP33_DATA13_MARK, TP33_DATA14_MARK, TP33_DATA15_MARK,
-};
-
-/* = [ UART1 ] ============ */
-static const unsigned int uart1_data_pins[] = {
-	/* RX, TX */
-	155, 156,
-};
-static const unsigned int uart1_data_mux[] = {
-	UART1_RX_MARK, UART1_TX_MARK,
-};
-
-static const unsigned int uart1_ctrl_pins[] = {
-	/* CTSB, RTSB */
-	157, 158,
-};
-static const unsigned int uart1_ctrl_mux[] = {
-	UART1_CTSB_MARK, UART1_RTSB_MARK,
-};
-
-/* = [ UART2 ] ============ */
-static const unsigned int uart2_data_pins[] = {
-	/* RX, TX */
-	157, 158,
-};
-static const unsigned int uart2_data_mux[] = {
-	UART2_RX_MARK, UART2_TX_MARK,
-};
-
-/* = [ UART3 ] ============ */
-static const unsigned int uart3_data_pins[] = {
-	/* RX, TX */
-	46, 47,
-};
-static const unsigned int uart3_data_mux[] = {
-	UART3_RX_MARK, UART3_TX_MARK,
-};
-
-/* = [ USB ] ============== */
-EMEV_MUX_PIN(usb_vbus, 153, USB_VBUS);
-
-/* = [ USI0 ] ============== */
-EMEV_MUX_PIN(usi0_cs1, 105, USI0_CS1);
-EMEV_MUX_PIN(usi0_cs2, 106, USI0_CS2);
-EMEV_MUX_PIN(usi0_cs3, 115, USI0_CS3);
-EMEV_MUX_PIN(usi0_cs4, 116, USI0_CS4);
-EMEV_MUX_PIN(usi0_cs5, 117, USI0_CS5);
-EMEV_MUX_PIN(usi0_cs6, 118, USI0_CS6);
-
-/* = [ USI1 ] ============== */
-static const unsigned int usi1_pins[] = {
-	/* DI, DO*/
-	107, 108,
-};
-static const unsigned int usi1_mux[] = {
-	USI1_DI_MARK, USI1_DO_MARK,
-};
-
-/* = [ USI2 ] ============== */
-static const unsigned int usi2_pins[] = {
-	/* CLK, DI, DO*/
-	109, 110, 111,
-};
-static const unsigned int usi2_mux[] = {
-	USI2_CLK_MARK, USI2_DI_MARK, USI2_DO_MARK,
-};
-EMEV_MUX_PIN(usi2_cs0, 112, USI2_CS0);
-EMEV_MUX_PIN(usi2_cs1, 113, USI2_CS1);
-EMEV_MUX_PIN(usi2_cs2, 114, USI2_CS2);
-
-/* = [ USI3 ] ============== */
-static const unsigned int usi3_pins[] = {
-	/* CLK, DI, DO*/
-	115, 116, 117,
-};
-static const unsigned int usi3_mux[] = {
-	USI3_CLK_MARK, USI3_DI_MARK, USI3_DO_MARK,
-};
-EMEV_MUX_PIN(usi3_cs0, 118, USI3_CS0);
-
-/* = [ USI4 ] ============== */
-static const unsigned int usi4_pins[] = {
-	/* CLK, DI, DO*/
-	119, 120, 121,
-};
-static const unsigned int usi4_mux[] = {
-	USI4_CLK_MARK, USI4_DI_MARK, USI4_DO_MARK,
-};
-EMEV_MUX_PIN(usi4_cs0, 113, USI4_CS0);
-EMEV_MUX_PIN(usi4_cs1, 114, USI4_CS1);
-
-/* = [ USI5 ] ============== */
-static const unsigned int usi5_a_pins[] = {
-	/* CLK, DI, DO*/
-	85, 86, 87,
-};
-static const unsigned int usi5_a_mux[] = {
-	USI5_CLK_A_MARK, USI5_DI_A_MARK, USI5_DO_A_MARK,
-};
-EMEV_MUX_PIN(usi5_cs0_a, 88, USI5_CS0_A);
-EMEV_MUX_PIN(usi5_cs1_a, 89, USI5_CS1_A);
-EMEV_MUX_PIN(usi5_cs2_a, 90, USI5_CS2_A);
-
-static const unsigned int usi5_b_pins[] = {
-	/* CLK, DI, DO*/
-	143, 144, 150,
-};
-static const unsigned int usi5_b_mux[] = {
-	USI5_CLK_B_MARK, USI5_DI_B_MARK, USI5_DO_B_MARK,
-};
-EMEV_MUX_PIN(usi5_cs0_b, 145, USI5_CS0_B);
-EMEV_MUX_PIN(usi5_cs1_b, 146, USI5_CS1_B);
-EMEV_MUX_PIN(usi5_cs2_b, 147, USI5_CS2_B);
-EMEV_MUX_PIN(usi5_cs3_b, 148, USI5_CS3_B);
-EMEV_MUX_PIN(usi5_cs4_b, 149, USI5_CS4_B);
-
-static const struct sh_pfc_pin_group pinmux_groups[] = {
-	SH_PFC_PIN_GROUP(err_rst_reqb),
-	SH_PFC_PIN_GROUP(ref_clko),
-	SH_PFC_PIN_GROUP(ext_clki),
-	SH_PFC_PIN_GROUP(lowpwr),
-
-	SH_PFC_PIN_GROUP(ab_main),
-	SH_PFC_PIN_GROUP(ab_clk),
-	SH_PFC_PIN_GROUP(ab_csb0),
-	SH_PFC_PIN_GROUP(ab_csb1),
-	SH_PFC_PIN_GROUP(ab_csb2),
-	SH_PFC_PIN_GROUP(ab_csb3),
-	SH_PFC_PIN_GROUP(ab_wait),
-	SH_PFC_PIN_GROUP(ab_adv),
-	SH_PFC_PIN_GROUP(ab_a17),
-	SH_PFC_PIN_GROUP(ab_a18),
-	SH_PFC_PIN_GROUP(ab_a19),
-	SH_PFC_PIN_GROUP(ab_a20),
-	SH_PFC_PIN_GROUP(ab_a21),
-	SH_PFC_PIN_GROUP(ab_a22),
-	SH_PFC_PIN_GROUP(ab_a23),
-	SH_PFC_PIN_GROUP(ab_a24),
-	SH_PFC_PIN_GROUP(ab_a25),
-	SH_PFC_PIN_GROUP(ab_a26),
-	SH_PFC_PIN_GROUP(ab_a27),
-	SH_PFC_PIN_GROUP(ab_a28),
-	SH_PFC_PIN_GROUP(ab_ben0),
-	SH_PFC_PIN_GROUP(ab_ben1),
-
-	SH_PFC_PIN_GROUP(cam_clko),
-	SH_PFC_PIN_GROUP(cam),
-
-	SH_PFC_PIN_GROUP(cf_ctrl),
-	SH_PFC_PIN_GROUP(cf_data8),
-	SH_PFC_PIN_GROUP(cf_data16),
-
-	SH_PFC_PIN_GROUP(dtv_a),
-	SH_PFC_PIN_GROUP(dtv_b),
-
-	SH_PFC_PIN_GROUP(iic0),
-
-	SH_PFC_PIN_GROUP(iic1),
-
-	SH_PFC_PIN_GROUP(jtag),
-
-	SH_PFC_PIN_GROUP(lcd3_pxclk),
-	SH_PFC_PIN_GROUP(lcd3_pxclkb),
-	SH_PFC_PIN_GROUP(lcd3_clk_i),
-	SH_PFC_PIN_GROUP(lcd3_sync),
-	SH_PFC_PIN_GROUP(lcd3_rgb888),
-	SH_PFC_PIN_GROUP(yuv3_clk_i),
-	SH_PFC_PIN_GROUP(yuv3),
-
-	SH_PFC_PIN_GROUP(ntsc_clk),
-	SH_PFC_PIN_GROUP(ntsc_data),
-
-	SH_PFC_PIN_GROUP(pwm0),
-
-	SH_PFC_PIN_GROUP(pwm1),
-
-	SH_PFC_PIN_GROUP(sd_cki),
-
-	SH_PFC_PIN_GROUP(sdi0_ctrl),
-	SH_PFC_PIN_GROUP(sdi0_data1),
-	SH_PFC_PIN_GROUP(sdi0_data4),
-	SH_PFC_PIN_GROUP(sdi0_data8),
-
-	SH_PFC_PIN_GROUP(sdi1_ctrl),
-	SH_PFC_PIN_GROUP(sdi1_data1),
-	SH_PFC_PIN_GROUP(sdi1_data4),
-
-	SH_PFC_PIN_GROUP(sdi2_ctrl),
-	SH_PFC_PIN_GROUP(sdi2_data1),
-	SH_PFC_PIN_GROUP(sdi2_data4),
-
-	SH_PFC_PIN_GROUP(tp33),
-
-	SH_PFC_PIN_GROUP(uart1_data),
-	SH_PFC_PIN_GROUP(uart1_ctrl),
-
-	SH_PFC_PIN_GROUP(uart2_data),
-
-	SH_PFC_PIN_GROUP(uart3_data),
-
-	SH_PFC_PIN_GROUP(usb_vbus),
-
-	SH_PFC_PIN_GROUP(usi0_cs1),
-	SH_PFC_PIN_GROUP(usi0_cs2),
-	SH_PFC_PIN_GROUP(usi0_cs3),
-	SH_PFC_PIN_GROUP(usi0_cs4),
-	SH_PFC_PIN_GROUP(usi0_cs5),
-	SH_PFC_PIN_GROUP(usi0_cs6),
-
-	SH_PFC_PIN_GROUP(usi1),
-
-	SH_PFC_PIN_GROUP(usi2),
-	SH_PFC_PIN_GROUP(usi2_cs0),
-	SH_PFC_PIN_GROUP(usi2_cs1),
-	SH_PFC_PIN_GROUP(usi2_cs2),
-
-	SH_PFC_PIN_GROUP(usi3),
-	SH_PFC_PIN_GROUP(usi3_cs0),
-
-	SH_PFC_PIN_GROUP(usi4),
-	SH_PFC_PIN_GROUP(usi4_cs0),
-	SH_PFC_PIN_GROUP(usi4_cs1),
-
-	SH_PFC_PIN_GROUP(usi5_a),
-	SH_PFC_PIN_GROUP(usi5_cs0_a),
-	SH_PFC_PIN_GROUP(usi5_cs1_a),
-	SH_PFC_PIN_GROUP(usi5_cs2_a),
-	SH_PFC_PIN_GROUP(usi5_b),
-	SH_PFC_PIN_GROUP(usi5_cs0_b),
-	SH_PFC_PIN_GROUP(usi5_cs1_b),
-	SH_PFC_PIN_GROUP(usi5_cs2_b),
-	SH_PFC_PIN_GROUP(usi5_cs3_b),
-	SH_PFC_PIN_GROUP(usi5_cs4_b),
-};
-
-static const char * const ab_groups[] = {
-	"ab_main",
-	"ab_clk",
-	"ab_csb0",
-	"ab_csb1",
-	"ab_csb2",
-	"ab_csb3",
-	"ab_wait",
-	"ab_adv",
-	"ab_a17",
-	"ab_a18",
-	"ab_a19",
-	"ab_a20",
-	"ab_a21",
-	"ab_a22",
-	"ab_a23",
-	"ab_a24",
-	"ab_a25",
-	"ab_a26",
-	"ab_a27",
-	"ab_a28",
-	"ab_ben0",
-	"ab_ben1",
-};
-
-static const char * const cam_groups[] = {
-	"cam_clko",
-	"cam",
-};
-
-static const char * const cf_groups[] = {
-	"cf_ctrl",
-	"cf_data8",
-	"cf_data16",
-};
-
-static const char * const dtv_groups[] = {
-	"dtv_a",
-	"dtv_b",
-};
-
-static const char * const err_rst_reqb_groups[] = {
-	"err_rst_reqb",
-};
-
-static const char * const ext_clki_groups[] = {
-	"ext_clki",
-};
-
-static const char * const iic0_groups[] = {
-	"iic0",
-};
-
-static const char * const iic1_groups[] = {
-	"iic1",
-};
-
-static const char * const jtag_groups[] = {
-	"jtag",
-};
-
-static const char * const lcd_groups[] = {
-	"lcd3_pxclk",
-	"lcd3_pxclkb",
-	"lcd3_clk_i",
-	"lcd3_sync",
-	"lcd3_rgb888",
-	"yuv3_clk_i",
-	"yuv3",
-};
-
-static const char * const lowpwr_groups[] = {
-	"lowpwr",
-};
-
-static const char * const ntsc_groups[] = {
-	"ntsc_clk",
-	"ntsc_data",
-};
-
-static const char * const pwm0_groups[] = {
-	"pwm0",
-};
-
-static const char * const pwm1_groups[] = {
-	"pwm1",
-};
-
-static const char * const ref_clko_groups[] = {
-	"ref_clko",
-};
-
-static const char * const sd_groups[] = {
-	"sd_cki",
-};
-
-static const char * const sdi0_groups[] = {
-	"sdi0_ctrl",
-	"sdi0_data1",
-	"sdi0_data4",
-	"sdi0_data8",
-};
-
-static const char * const sdi1_groups[] = {
-	"sdi1_ctrl",
-	"sdi1_data1",
-	"sdi1_data4",
-};
-
-static const char * const sdi2_groups[] = {
-	"sdi2_ctrl",
-	"sdi2_data1",
-	"sdi2_data4",
-};
-
-static const char * const tp33_groups[] = {
-	"tp33",
-};
-
-static const char * const uart1_groups[] = {
-	"uart1_data",
-	"uart1_ctrl",
-};
-
-static const char * const uart2_groups[] = {
-	"uart2_data",
-};
-
-static const char * const uart3_groups[] = {
-	"uart3_data",
-};
-
-static const char * const usb_groups[] = {
-	"usb_vbus",
-};
-
-static const char * const usi0_groups[] = {
-	"usi0_cs1",
-	"usi0_cs2",
-	"usi0_cs3",
-	"usi0_cs4",
-	"usi0_cs5",
-	"usi0_cs6",
-};
-
-static const char * const usi1_groups[] = {
-	"usi1",
-};
-
-static const char * const usi2_groups[] = {
-	"usi2",
-	"usi2_cs0",
-	"usi2_cs1",
-	"usi2_cs2",
-};
-
-static const char * const usi3_groups[] = {
-	"usi3",
-	"usi3_cs0",
-};
-
-static const char * const usi4_groups[] = {
-	"usi4",
-	"usi4_cs0",
-	"usi4_cs1",
-};
-
-static const char * const usi5_groups[] = {
-	"usi5_a",
-	"usi5_cs0_a",
-	"usi5_cs1_a",
-	"usi5_cs2_a",
-	"usi5_b",
-	"usi5_cs0_b",
-	"usi5_cs1_b",
-	"usi5_cs2_b",
-	"usi5_cs3_b",
-	"usi5_cs4_b",
-};
-
-static const struct sh_pfc_function pinmux_functions[] = {
-	SH_PFC_FUNCTION(ab),
-	SH_PFC_FUNCTION(cam),
-	SH_PFC_FUNCTION(cf),
-	SH_PFC_FUNCTION(dtv),
-	SH_PFC_FUNCTION(err_rst_reqb),
-	SH_PFC_FUNCTION(ext_clki),
-	SH_PFC_FUNCTION(iic0),
-	SH_PFC_FUNCTION(iic1),
-	SH_PFC_FUNCTION(jtag),
-	SH_PFC_FUNCTION(lcd),
-	SH_PFC_FUNCTION(lowpwr),
-	SH_PFC_FUNCTION(ntsc),
-	SH_PFC_FUNCTION(pwm0),
-	SH_PFC_FUNCTION(pwm1),
-	SH_PFC_FUNCTION(ref_clko),
-	SH_PFC_FUNCTION(sd),
-	SH_PFC_FUNCTION(sdi0),
-	SH_PFC_FUNCTION(sdi1),
-	SH_PFC_FUNCTION(sdi2),
-	SH_PFC_FUNCTION(tp33),
-	SH_PFC_FUNCTION(uart1),
-	SH_PFC_FUNCTION(uart2),
-	SH_PFC_FUNCTION(uart3),
-	SH_PFC_FUNCTION(usb),
-	SH_PFC_FUNCTION(usi0),
-	SH_PFC_FUNCTION(usi1),
-	SH_PFC_FUNCTION(usi2),
-	SH_PFC_FUNCTION(usi3),
-	SH_PFC_FUNCTION(usi4),
-	SH_PFC_FUNCTION(usi5),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	{ PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1, GROUP(
-		0, PORT31_FN,				/* PIN: J18  */
-		0, PORT30_FN,				/* PIN: H18  */
-		0, PORT29_FN,				/* PIN: G18  */
-		0, PORT28_FN,				/* PIN: F18  */
-		0, PORT27_FN,				/* PIN: F17  */
-		0, PORT26_FN,				/* PIN: F16  */
-		0, PORT25_FN,				/* PIN: E20  */
-		0, PORT24_FN,				/* PIN: D20  */
-		FN_LCD3_1_0_PORT23, PORT23_FN,		/* PIN: D19  */
-		FN_LCD3_1_0_PORT22, PORT22_FN,		/* PIN: C20  */
-		FN_LCD3_1_0_PORT21, PORT21_FN,		/* PIN: B21  */
-		FN_LCD3_1_0_PORT20, PORT20_FN,		/* PIN: A21  */
-		FN_LCD3_PXCLKB, PORT19_FN,		/* PIN: C21  */
-		FN_LCD3_1_0_PORT18, PORT18_FN,		/* PIN: B22  */
-		0, PORT17_FN,				/* PIN: W20  */
-		0, PORT16_FN,				/* PIN: W21  */
-		0, PORT15_FN,				/* PIN: Y19  */
-		0, PORT14_FN,				/* PIN: Y20  */
-		0, PORT13_FN,				/* PIN: Y21  */
-		0, PORT12_FN,				/* PIN: AA20 */
-		0, PORT11_FN,				/* PIN: AA21 */
-		0, PORT10_FN,				/* PIN: AA22 */
-		0, PORT9_FN,				/* PIN: V15  */
-		0, PORT8_FN,				/* PIN: V16  */
-		0, PORT7_FN,				/* PIN: V17  */
-		0, PORT6_FN,				/* PIN: V18  */
-		FN_EXT_CLKI, PORT5_FN,			/* PIN: U8   */
-		FN_REF_CLKO, PORT4_FN,			/* PIN: V8   */
-		FN_ERR_RST_REQB, PORT3_FN,		/* PIN: U9   */
-		FN_JT_SEL, PORT2_FN,			/* PIN: V9   */
-		0, PORT1_FN,				/* PIN: U10  */
-		0, PORT0_FN,				/* PIN: V10  */
-		))
-	},
-	{ PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1, GROUP(
-		FN_SDI1_CMD, PORT63_FN,			/* PIN: AC21 */
-		FN_SDI1_CKI, PORT62_FN,			/* PIN: AA23 */
-		FN_SDI1_CKO, PORT61_FN,			/* PIN: AB22 */
-		FN_SDI0_DATA7, PORT60_FN,		/* PIN: Y16  */
-		FN_SDI0_DATA6, PORT59_FN,		/* PIN: AA16 */
-		FN_SDI0_DATA5, PORT58_FN,		/* PIN: Y15  */
-		FN_SDI0_DATA4, PORT57_FN,		/* PIN: AA15 */
-		FN_SDI0_DATA3, PORT56_FN,		/* PIN: Y14  */
-		FN_SDI0_DATA2, PORT55_FN,		/* PIN: AA14 */
-		FN_SDI0_DATA1, PORT54_FN,		/* PIN: Y13  */
-		FN_SDI0_DATA0, PORT53_FN,		/* PIN: AA13 */
-		FN_SDI0_CMD, PORT52_FN,			/* PIN: Y12  */
-		FN_SDI0_CKI, PORT51_FN,			/* PIN: AC18 */
-		FN_SDI0_CKO, PORT50_FN,			/* PIN: AB18 */
-		0, PORT49_FN,				/* PIN: AB16 */
-		FN_SD_CKI, PORT48_FN,			/* PIN: AC19 */
-		FN_IIC_1_0_PORT47, PORT47_FN,		/* PIN: Y8   */
-		FN_IIC_1_0_PORT46, PORT46_FN,		/* PIN: Y9   */
-		FN_IIC0_SDA, PORT45_FN,			/* PIN: AA8  */
-		FN_IIC0_SCL, PORT44_FN,			/* PIN: AA9  */
-		FN_LCD3_11_10_PORT43, PORT43_FN,	/* PIN: A15  */
-		FN_LCD3_11_10_PORT42, PORT42_FN,	/* PIN: A16  */
-		FN_LCD3_11_10_PORT41, PORT41_FN,	/* PIN: A17  */
-		FN_LCD3_11_10_PORT40, PORT40_FN,	/* PIN: A18  */
-		FN_LCD3_9_8_PORT39, PORT39_FN,		/* PIN: D18  */
-		FN_LCD3_9_8_PORT38, PORT38_FN,		/* PIN: C18  */
-		FN_LCD3_R5, PORT37_FN,			/* PIN: B18  */
-		FN_LCD3_R4, PORT36_FN,			/* PIN: C19  */
-		FN_LCD3_R3, PORT35_FN,			/* PIN: B19  */
-		FN_LCD3_R2, PORT34_FN,			/* PIN: A19  */
-		FN_LCD3_R1, PORT33_FN,			/* PIN: B20  */
-		FN_LCD3_R0, PORT32_FN,			/* PIN: A20  */
-		))
-	},
-	{ PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1, GROUP(
-		FN_AB_1_0_PORT95, PORT95_FN,		/* PIN: L21  */
-		FN_AB_1_0_PORT94, PORT94_FN,		/* PIN: K21  */
-		FN_AB_1_0_PORT93, PORT93_FN,		/* PIN: J21  */
-		FN_AB_7_6_PORT92, PORT92_FN,		/* PIN: J22  */
-		FN_AB_7_6_PORT91, PORT91_FN,		/* PIN: H21  */
-		FN_AB_5_4_PORT90, PORT90_FN,		/* PIN: H22  */
-		FN_AB_5_4_PORT89, PORT89_FN,		/* PIN: H23  */
-		FN_AB_3_2_PORT88, PORT88_FN,		/* PIN: G21  */
-		FN_AB_3_2_PORT87, PORT87_FN,		/* PIN: G22  */
-		FN_AB_3_2_PORT86, PORT86_FN,		/* PIN: G23  */
-		FN_AB_3_2_PORT85, PORT85_FN,		/* PIN: F21  */
-		FN_AB_1_0_PORT84, PORT84_FN,		/* PIN: F22  */
-		FN_AB_1_0_PORT83, PORT83_FN,		/* PIN: F23  */
-		FN_AB_1_0_PORT82, PORT82_FN,		/* PIN: E22  */
-		FN_AB_1_0_PORT81, PORT81_FN,		/* PIN: E23  */
-		FN_AB_1_0_PORT80, PORT80_FN,		/* PIN: D22  */
-		FN_AB_1_0_PORT79, PORT79_FN,		/* PIN: D23  */
-		FN_AB_1_0_PORT78, PORT78_FN,		/* PIN: C22  */
-		FN_AB_1_0_PORT77, PORT77_FN,		/* PIN: C23  */
-		FN_AB_1_0_PORT76, PORT76_FN,		/* PIN: K20  */
-		FN_AB_1_0_PORT75, PORT75_FN,		/* PIN: L20  */
-		FN_AB_1_0_PORT74, PORT74_FN,		/* PIN: H20  */
-		FN_AB_1_0_PORT73, PORT73_FN,		/* PIN: J20  */
-		FN_AB_1_0_PORT72, PORT72_FN,		/* PIN: G20  */
-		FN_AB_1_0_PORT71, PORT71_FN,		/* PIN: F20  */
-		FN_AB_CSB1, PORT70_FN,			/* PIN: E21  */
-		FN_AB_CSB0, PORT69_FN,			/* PIN: D21  */
-		FN_AB_CLK, PORT68_FN,			/* PIN: J23  */
-		FN_SDI1_DATA3, PORT67_FN,		/* PIN: AA19 */
-		FN_SDI1_DATA2, PORT66_FN,		/* PIN: AB19 */
-		FN_SDI1_DATA1, PORT65_FN,		/* PIN: AB20 */
-		FN_SDI1_DATA0, PORT64_FN,		/* PIN: AB21 */
-		))
-	},
-	{ PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1, GROUP(
-		FN_NTSC_DATA4, PORT127_FN,		/* PIN: T20  */
-		FN_NTSC_DATA3, PORT126_FN,		/* PIN: R18  */
-		FN_NTSC_DATA2, PORT125_FN,		/* PIN: R20  */
-		FN_NTSC_DATA1, PORT124_FN,		/* PIN: P18  */
-		FN_NTSC_DATA0, PORT123_FN,		/* PIN: P20  */
-		FN_NTSC_CLK, PORT122_FN,		/* PIN: V20  */
-		FN_USI_9_8_PORT121, PORT121_FN,		/* PIN: Y5   */
-		FN_USI_9_8_PORT120, PORT120_FN,		/* PIN: AA4  */
-		FN_USI_7_6_PORT119, PORT119_FN,		/* PIN: AB3  */
-		FN_USI_5_4_PORT118, PORT118_FN,		/* PIN: AB4  */
-		FN_USI_5_4_PORT117, PORT117_FN,		/* PIN: AC3  */
-		FN_USI_5_4_PORT116, PORT116_FN,		/* PIN: AC4  */
-		FN_USI_5_4_PORT115, PORT115_FN,		/* PIN: AC5  */
-		FN_USI_3_2_PORT114, PORT114_FN,		/* PIN: Y6   */
-		FN_USI_3_2_PORT113, PORT113_FN,		/* PIN: AA7  */
-		FN_USI_1_0_PORT112, PORT112_FN,		/* PIN: Y7   */
-		FN_USI_1_0_PORT111, PORT111_FN,		/* PIN: AA5  */
-		FN_USI_1_0_PORT110, PORT110_FN,		/* PIN: AA6  */
-		FN_USI_1_0_PORT109, PORT109_FN,		/* PIN: AB5  */
-		FN_USI1_DO, PORT108_FN,			/* PIN: D10  */
-		FN_USI1_DI, PORT107_FN,			/* PIN: C10  */
-		FN_USI0_CS2, PORT106_FN,		/* PIN: B9   */
-		FN_USI0_CS1, PORT105_FN,		/* PIN: B8   */
-		FN_AB_13_12_PORT104, PORT104_FN,	/* PIN: M17  */
-		FN_AB_13_12_PORT103, PORT103_FN,	/* PIN: L17  */
-		FN_AB_11_10_PORT102, PORT102_FN,	/* PIN: N18  */
-		FN_AB_11_10_PORT101, PORT101_FN,	/* PIN: M18  */
-		FN_AB_11_10_PORT100, PORT100_FN,	/* PIN: L18  */
-		FN_AB_9_8_PORT99, PORT99_FN,		/* PIN: N20  */
-		FN_AB_9_8_PORT98, PORT98_FN,		/* PIN: M20  */
-		FN_AB_9_8_PORT97, PORT97_FN,		/* PIN: N21  */
-		FN_AB_A20, PORT96_FN,			/* PIN: M21  */
-		))
-	},
-	{ PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1, GROUP(
-		0, 0,
-		FN_UART_1_0_PORT158, PORT158_FN,	/* PIN: AB10 */
-		FN_UART_1_0_PORT157, PORT157_FN,	/* PIN: AA10 */
-		FN_UART1_TX, PORT156_FN,		/* PIN: Y10  */
-		FN_UART1_RX, PORT155_FN,		/* PIN: Y11  */
-		FN_LOWPWR, PORT154_FN,			/* PIN: A12  */
-		FN_USB_VBUS, PORT153_FN,		/* PIN: AA12 */
-		FN_JT_TDOEN, PORT152_FN,		/* PIN: F13  */
-		FN_JT_TDO, PORT151_FN,			/* PIN: D13  */
-		FN_HSI_1_0_PORT150, PORT150_FN,		/* PIN: M22  */
-		FN_HSI_1_0_PORT149, PORT149_FN,		/* PIN: M23  */
-		FN_HSI_1_0_PORT148, PORT148_FN,		/* PIN: N23  */
-		FN_HSI_1_0_PORT147, PORT147_FN,		/* PIN: N22  */
-		FN_HSI_1_0_PORT146, PORT146_FN,		/* PIN: L22  */
-		FN_HSI_1_0_PORT145, PORT145_FN,		/* PIN: L23  */
-		FN_HSI_1_0_PORT144, PORT144_FN,		/* PIN: K23  */
-		FN_HSI_1_0_PORT143, PORT143_FN,		/* PIN: K22  */
-		FN_CAM_YUV7, PORT142_FN,		/* PIN: V23  */
-		FN_CAM_YUV6, PORT141_FN,		/* PIN: V22  */
-		FN_CAM_YUV5, PORT140_FN,		/* PIN: U23  */
-		FN_CAM_YUV4, PORT139_FN,		/* PIN: U22  */
-		FN_CAM_YUV3, PORT138_FN,		/* PIN: U21  */
-		FN_CAM_YUV2, PORT137_FN,		/* PIN: T23  */
-		FN_CAM_YUV1, PORT136_FN,		/* PIN: T22  */
-		FN_CAM_YUV0, PORT135_FN,		/* PIN: T21  */
-		FN_CAM_HS, PORT134_FN,			/* PIN: V21  */
-		FN_CAM_VS, PORT133_FN,			/* PIN: W22  */
-		FN_CAM_CLKI, PORT132_FN,		/* PIN: Y23  */
-		FN_CAM_CLKO, PORT131_FN,		/* PIN: W23  */
-		FN_NTSC_DATA7, PORT130_FN,		/* PIN: U18  */
-		FN_NTSC_DATA6, PORT129_FN,		/* PIN: U20  */
-		FN_NTSC_DATA5, PORT128_FN,		/* PIN: T18  */
-		))
-	},
-	{ PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32,
-			     GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-				   1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
-				   2, 2),
-			     GROUP(
-		/* 31 - 12 */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* 11 - 10 */
-		FN_SEL_LCD3_11_10_00, FN_SEL_LCD3_11_10_01,
-		FN_SEL_LCD3_11_10_10, 0,
-		/* 9 - 8 */
-		FN_SEL_LCD3_9_8_00, 0, FN_SEL_LCD3_9_8_10, 0,
-		/* 7 - 2 */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* 1 - 0 */
-		FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01, 0, 0,
-		))
-	},
-	{ PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32,
-			     GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-				   1, 1, 1, 1, 1, 1, 2),
-			     GROUP(
-		/* 31 - 2 */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* 1 - 0 */
-		FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01, 0, 0,
-		))
-	},
-	{ PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32,
-			     GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-				   1, 1, 1, 1, 1, 1, 2),
-			     GROUP(
-		/* 31 - 2 */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* 1 - 0 */
-		FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01, 0, 0,
-		))
-	},
-	{ PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32,
-			     GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-				   1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2),
-			     GROUP(
-		/* 31 - 14 */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0,
-		/* 13 - 12 */
-		FN_SEL_AB_13_12_00, 0, FN_SEL_AB_13_12_10, 0,
-		/* 11 - 10 */
-		FN_SEL_AB_11_10_00, 0, FN_SEL_AB_11_10_10, 0,
-		/* 9 - 8 */
-		FN_SEL_AB_9_8_00, FN_SEL_AB_9_8_01, FN_SEL_AB_9_8_10, 0,
-		/* 7 - 6 */
-		FN_SEL_AB_7_6_00, FN_SEL_AB_7_6_01, FN_SEL_AB_7_6_10, 0,
-		/* 5 - 4 */
-		FN_SEL_AB_5_4_00, FN_SEL_AB_5_4_01,
-		FN_SEL_AB_5_4_10, FN_SEL_AB_5_4_11,
-		/* 3 - 2 */
-		FN_SEL_AB_3_2_00, FN_SEL_AB_3_2_01,
-		FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11,
-		/* 1 - 0 */
-		FN_SEL_AB_1_0_00, 0, FN_SEL_AB_1_0_10, 0,
-		))
-	},
-	{ PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32,
-			     GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
-				   2, 2, 2),
-			     GROUP(
-		/* 31 - 10 */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* 9 - 8 */
-		FN_SEL_USI_9_8_00, FN_SEL_USI_9_8_01, 0, 0,
-		/* 7 - 6 */
-		FN_SEL_USI_7_6_00, FN_SEL_USI_7_6_01, 0, 0,
-		/* 5 - 4 */
-		FN_SEL_USI_5_4_00, FN_SEL_USI_5_4_01, 0, 0,
-		/* 3 - 2 */
-		FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01, 0, 0,
-		/* 1 - 0 */
-		FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01, 0, 0,
-		))
-	},
-	{ PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32,
-			     GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-				   1, 1, 1, 1, 1, 1, 2),
-			     GROUP(
-		/* 31 - 2 */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* 1 - 0 */
-		FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, 0, 0,
-		))
-	},
-	{ },
-};
-
-const struct sh_pfc_soc_info emev2_pinmux_info = {
-	.name		= "emev2_pfc",
-
-	.function	= { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins		= pinmux_pins,
-	.nr_pins	= ARRAY_SIZE(pinmux_pins),
-	.groups		= pinmux_groups,
-	.nr_groups	= ARRAY_SIZE(pinmux_groups),
-	.functions	= pinmux_functions,
-	.nr_functions	= ARRAY_SIZE(pinmux_functions),
-
-	.cfg_regs	= pinmux_config_regs,
-
-	.pinmux_data	= pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
deleted file mode 100644
index b21f5afe610f..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ /dev/null
@@ -1,2731 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2012-2013  Renesas Solutions Corp.
- * Copyright (C) 2013  Magnus Damm
- * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
- */
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/pinctrl/pinconf-generic.h>
-
-#include "sh_pfc.h"
-
-#define CPU_ALL_PORT(fn, pfx, sfx)					\
-	/*  Port0 - Port30 */						\
-	PORT_10(0, fn, pfx, sfx),					\
-	PORT_10(10, fn, pfx##1, sfx),					\
-	PORT_10(20, fn, pfx##2, sfx),					\
-	PORT_1(30, fn, pfx##30, sfx),					\
-	/* Port32 - Port40 */						\
-	PORT_1(32, fn, pfx##32, sfx),	PORT_1(33, fn, pfx##33, sfx),	\
-	PORT_1(34, fn, pfx##34, sfx),	PORT_1(35, fn, pfx##35, sfx),	\
-	PORT_1(36, fn, pfx##36, sfx),	PORT_1(37, fn, pfx##37, sfx),	\
-	PORT_1(38, fn, pfx##38, sfx),	PORT_1(39, fn, pfx##39, sfx),	\
-	PORT_1(40, fn, pfx##40, sfx),					\
-	/* Port64  - Port85 */						\
-	PORT_1(64, fn, pfx##64, sfx),	PORT_1(65, fn, pfx##65, sfx),	\
-	PORT_1(66, fn, pfx##66, sfx),	PORT_1(67, fn, pfx##67, sfx),	\
-	PORT_1(68, fn, pfx##68, sfx),	PORT_1(69, fn, pfx##69, sfx),	\
-	PORT_10(70, fn, pfx##7, sfx),					\
-	PORT_1(80, fn, pfx##80, sfx),	PORT_1(81, fn, pfx##81, sfx),	\
-	PORT_1(82, fn, pfx##82, sfx),	PORT_1(83, fn, pfx##83, sfx),	\
-	PORT_1(84, fn, pfx##84, sfx),	PORT_1(85, fn, pfx##85, sfx),	\
-	/* Port96  - Port126 */						\
-	PORT_1(96, fn, pfx##96, sfx),	PORT_1(97, fn, pfx##97, sfx),	\
-	PORT_1(98, fn, pfx##98, sfx),	PORT_1(99, fn, pfx##99, sfx),	\
-	PORT_10(100, fn, pfx##10, sfx),					\
-	PORT_10(110, fn, pfx##11, sfx),					\
-	PORT_1(120, fn, pfx##120, sfx),	PORT_1(121, fn, pfx##121, sfx),	\
-	PORT_1(122, fn, pfx##122, sfx),	PORT_1(123, fn, pfx##123, sfx),	\
-	PORT_1(124, fn, pfx##124, sfx),	PORT_1(125, fn, pfx##125, sfx),	\
-	PORT_1(126, fn, pfx##126, sfx),					\
-	/* Port128 - Port134 */						\
-	PORT_1(128, fn, pfx##128, sfx),	PORT_1(129, fn, pfx##129, sfx),	\
-	PORT_1(130, fn, pfx##130, sfx),	PORT_1(131, fn, pfx##131, sfx),	\
-	PORT_1(132, fn, pfx##132, sfx),	PORT_1(133, fn, pfx##133, sfx),	\
-	PORT_1(134, fn, pfx##134, sfx),					\
-	/* Port160 - Port178 */						\
-	PORT_10(160, fn, pfx##16, sfx),					\
-	PORT_1(170, fn, pfx##170, sfx),	PORT_1(171, fn, pfx##171, sfx),	\
-	PORT_1(172, fn, pfx##172, sfx),	PORT_1(173, fn, pfx##173, sfx),	\
-	PORT_1(174, fn, pfx##174, sfx),	PORT_1(175, fn, pfx##175, sfx),	\
-	PORT_1(176, fn, pfx##176, sfx),	PORT_1(177, fn, pfx##177, sfx),	\
-	PORT_1(178, fn, pfx##178, sfx),					\
-	/* Port192 - Port222 */						\
-	PORT_1(192, fn, pfx##192, sfx),	PORT_1(193, fn, pfx##193, sfx),	\
-	PORT_1(194, fn, pfx##194, sfx),	PORT_1(195, fn, pfx##195, sfx),	\
-	PORT_1(196, fn, pfx##196, sfx),	PORT_1(197, fn, pfx##197, sfx),	\
-	PORT_1(198, fn, pfx##198, sfx),	PORT_1(199, fn, pfx##199, sfx),	\
-	PORT_10(200, fn, pfx##20, sfx),					\
-	PORT_10(210, fn, pfx##21, sfx),					\
-	PORT_1(220, fn, pfx##220, sfx),	PORT_1(221, fn, pfx##221, sfx),	\
-	PORT_1(222, fn, pfx##222, sfx),					\
-	/* Port224 - Port250 */						\
-	PORT_1(224, fn, pfx##224, sfx),	PORT_1(225, fn, pfx##225, sfx),	\
-	PORT_1(226, fn, pfx##226, sfx),	PORT_1(227, fn, pfx##227, sfx),	\
-	PORT_1(228, fn, pfx##228, sfx),	PORT_1(229, fn, pfx##229, sfx),	\
-	PORT_10(230, fn, pfx##23, sfx),					\
-	PORT_10(240, fn, pfx##24, sfx),					\
-	PORT_1(250, fn, pfx##250, sfx),					\
-	/* Port256 - Port283 */						\
-	PORT_1(256, fn, pfx##256, sfx),	PORT_1(257, fn, pfx##257, sfx),	\
-	PORT_1(258, fn, pfx##258, sfx),	PORT_1(259, fn, pfx##259, sfx),	\
-	PORT_10(260, fn, pfx##26, sfx),					\
-	PORT_10(270, fn, pfx##27, sfx),					\
-	PORT_1(280, fn, pfx##280, sfx),	PORT_1(281, fn, pfx##281, sfx),	\
-	PORT_1(282, fn, pfx##282, sfx),	PORT_1(283, fn, pfx##283, sfx),	\
-	/* Port288 - Port308 */						\
-	PORT_1(288, fn, pfx##288, sfx),	PORT_1(289, fn, pfx##289, sfx),	\
-	PORT_10(290, fn, pfx##29, sfx),					\
-	PORT_1(300, fn, pfx##300, sfx),	PORT_1(301, fn, pfx##301, sfx),	\
-	PORT_1(302, fn, pfx##302, sfx),	PORT_1(303, fn, pfx##303, sfx),	\
-	PORT_1(304, fn, pfx##304, sfx),	PORT_1(305, fn, pfx##305, sfx),	\
-	PORT_1(306, fn, pfx##306, sfx),	PORT_1(307, fn, pfx##307, sfx),	\
-	PORT_1(308, fn, pfx##308, sfx),					\
-	/* Port320 - Port329 */						\
-	PORT_10(320, fn, pfx##32, sfx)
-
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	/* PORT0_DATA -> PORT329_DATA */
-	PINMUX_DATA_BEGIN,
-	PORT_ALL(DATA),
-	PINMUX_DATA_END,
-
-	/* PORT0_IN -> PORT329_IN */
-	PINMUX_INPUT_BEGIN,
-	PORT_ALL(IN),
-	PINMUX_INPUT_END,
-
-	/* PORT0_OUT -> PORT329_OUT */
-	PINMUX_OUTPUT_BEGIN,
-	PORT_ALL(OUT),
-	PINMUX_OUTPUT_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT329_FN_IN */
-	PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT329_FN_OUT */
-	PORT_ALL(FN0), /* PORT0_FN0 -> PORT329_FN0 */
-	PORT_ALL(FN1), /* PORT0_FN1 -> PORT329_FN1 */
-	PORT_ALL(FN2), /* PORT0_FN2 -> PORT329_FN2 */
-	PORT_ALL(FN3), /* PORT0_FN3 -> PORT329_FN3 */
-	PORT_ALL(FN4), /* PORT0_FN4 -> PORT329_FN4 */
-	PORT_ALL(FN5), /* PORT0_FN5 -> PORT329_FN5 */
-	PORT_ALL(FN6), /* PORT0_FN6 -> PORT329_FN6 */
-	PORT_ALL(FN7), /* PORT0_FN7 -> PORT329_FN7 */
-
-	MSEL1CR_31_0, MSEL1CR_31_1,
-	MSEL1CR_27_0, MSEL1CR_27_1,
-	MSEL1CR_25_0, MSEL1CR_25_1,
-	MSEL1CR_24_0, MSEL1CR_24_1,
-	MSEL1CR_22_0, MSEL1CR_22_1,
-	MSEL1CR_21_0, MSEL1CR_21_1,
-	MSEL1CR_20_0, MSEL1CR_20_1,
-	MSEL1CR_19_0, MSEL1CR_19_1,
-	MSEL1CR_18_0, MSEL1CR_18_1,
-	MSEL1CR_17_0, MSEL1CR_17_1,
-	MSEL1CR_16_0, MSEL1CR_16_1,
-	MSEL1CR_15_0, MSEL1CR_15_1,
-	MSEL1CR_14_0, MSEL1CR_14_1,
-	MSEL1CR_13_0, MSEL1CR_13_1,
-	MSEL1CR_12_0, MSEL1CR_12_1,
-	MSEL1CR_11_0, MSEL1CR_11_1,
-	MSEL1CR_10_0, MSEL1CR_10_1,
-	MSEL1CR_09_0, MSEL1CR_09_1,
-	MSEL1CR_08_0, MSEL1CR_08_1,
-	MSEL1CR_07_0, MSEL1CR_07_1,
-	MSEL1CR_06_0, MSEL1CR_06_1,
-	MSEL1CR_05_0, MSEL1CR_05_1,
-	MSEL1CR_04_0, MSEL1CR_04_1,
-	MSEL1CR_03_0, MSEL1CR_03_1,
-	MSEL1CR_02_0, MSEL1CR_02_1,
-	MSEL1CR_01_0, MSEL1CR_01_1,
-	MSEL1CR_00_0, MSEL1CR_00_1,
-
-	MSEL3CR_31_0, MSEL3CR_31_1,
-	MSEL3CR_28_0, MSEL3CR_28_1,
-	MSEL3CR_27_0, MSEL3CR_27_1,
-	MSEL3CR_26_0, MSEL3CR_26_1,
-	MSEL3CR_23_0, MSEL3CR_23_1,
-	MSEL3CR_22_0, MSEL3CR_22_1,
-	MSEL3CR_21_0, MSEL3CR_21_1,
-	MSEL3CR_20_0, MSEL3CR_20_1,
-	MSEL3CR_19_0, MSEL3CR_19_1,
-	MSEL3CR_18_0, MSEL3CR_18_1,
-	MSEL3CR_17_0, MSEL3CR_17_1,
-	MSEL3CR_16_0, MSEL3CR_16_1,
-	MSEL3CR_15_0, MSEL3CR_15_1,
-	MSEL3CR_12_0, MSEL3CR_12_1,
-	MSEL3CR_11_0, MSEL3CR_11_1,
-	MSEL3CR_10_0, MSEL3CR_10_1,
-	MSEL3CR_09_0, MSEL3CR_09_1,
-	MSEL3CR_06_0, MSEL3CR_06_1,
-	MSEL3CR_03_0, MSEL3CR_03_1,
-	MSEL3CR_01_0, MSEL3CR_01_1,
-	MSEL3CR_00_0, MSEL3CR_00_1,
-
-	MSEL4CR_30_0, MSEL4CR_30_1,
-	MSEL4CR_29_0, MSEL4CR_29_1,
-	MSEL4CR_28_0, MSEL4CR_28_1,
-	MSEL4CR_27_0, MSEL4CR_27_1,
-	MSEL4CR_26_0, MSEL4CR_26_1,
-	MSEL4CR_25_0, MSEL4CR_25_1,
-	MSEL4CR_24_0, MSEL4CR_24_1,
-	MSEL4CR_23_0, MSEL4CR_23_1,
-	MSEL4CR_22_0, MSEL4CR_22_1,
-	MSEL4CR_21_0, MSEL4CR_21_1,
-	MSEL4CR_20_0, MSEL4CR_20_1,
-	MSEL4CR_19_0, MSEL4CR_19_1,
-	MSEL4CR_18_0, MSEL4CR_18_1,
-	MSEL4CR_17_0, MSEL4CR_17_1,
-	MSEL4CR_16_0, MSEL4CR_16_1,
-	MSEL4CR_15_0, MSEL4CR_15_1,
-	MSEL4CR_14_0, MSEL4CR_14_1,
-	MSEL4CR_13_0, MSEL4CR_13_1,
-	MSEL4CR_12_0, MSEL4CR_12_1,
-	MSEL4CR_11_0, MSEL4CR_11_1,
-	MSEL4CR_10_0, MSEL4CR_10_1,
-	MSEL4CR_09_0, MSEL4CR_09_1,
-	MSEL4CR_07_0, MSEL4CR_07_1,
-	MSEL4CR_04_0, MSEL4CR_04_1,
-	MSEL4CR_01_0, MSEL4CR_01_1,
-
-	MSEL5CR_31_0, MSEL5CR_31_1,
-	MSEL5CR_30_0, MSEL5CR_30_1,
-	MSEL5CR_29_0, MSEL5CR_29_1,
-	MSEL5CR_28_0, MSEL5CR_28_1,
-	MSEL5CR_27_0, MSEL5CR_27_1,
-	MSEL5CR_26_0, MSEL5CR_26_1,
-	MSEL5CR_25_0, MSEL5CR_25_1,
-	MSEL5CR_24_0, MSEL5CR_24_1,
-	MSEL5CR_23_0, MSEL5CR_23_1,
-	MSEL5CR_22_0, MSEL5CR_22_1,
-	MSEL5CR_21_0, MSEL5CR_21_1,
-	MSEL5CR_20_0, MSEL5CR_20_1,
-	MSEL5CR_19_0, MSEL5CR_19_1,
-	MSEL5CR_18_0, MSEL5CR_18_1,
-	MSEL5CR_17_0, MSEL5CR_17_1,
-	MSEL5CR_16_0, MSEL5CR_16_1,
-	MSEL5CR_15_0, MSEL5CR_15_1,
-	MSEL5CR_14_0, MSEL5CR_14_1,
-	MSEL5CR_13_0, MSEL5CR_13_1,
-	MSEL5CR_12_0, MSEL5CR_12_1,
-	MSEL5CR_11_0, MSEL5CR_11_1,
-	MSEL5CR_10_0, MSEL5CR_10_1,
-	MSEL5CR_09_0, MSEL5CR_09_1,
-	MSEL5CR_08_0, MSEL5CR_08_1,
-	MSEL5CR_07_0, MSEL5CR_07_1,
-	MSEL5CR_06_0, MSEL5CR_06_1,
-
-	MSEL8CR_16_0, MSEL8CR_16_1,
-	MSEL8CR_01_0, MSEL8CR_01_1,
-	MSEL8CR_00_0, MSEL8CR_00_1,
-
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-
-
-#define F1(a)	a##_MARK
-#define F2(a)	a##_MARK
-#define F3(a)	a##_MARK
-#define F4(a)	a##_MARK
-#define F5(a)	a##_MARK
-#define F6(a)	a##_MARK
-#define F7(a)	a##_MARK
-#define IRQ(a)	IRQ##a##_MARK
-
-	F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */
-	F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1),
-	F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2),
-	F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3),
-	F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4),
-	F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5),
-	F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6),
-	F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7),
-	F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8),
-	F1(LCDD9), F3(PDM1_OUTDATA_9), F7(DU0_DG1), IRQ(9),
-	F1(LCDD10), F3(FSICCK), F7(DU0_DG2), IRQ(10), /* Port10 */
-	F1(LCDD11), F3(FSICISLD), F7(DU0_DG3), IRQ(11),
-	F1(LCDD12), F3(FSICOMC), F7(DU0_DG4), IRQ(12),
-	F1(LCDD13), F3(FSICOLR), F4(FSICILR), F7(DU0_DG5), IRQ(13),
-	F1(LCDD14), F3(FSICOBT), F4(FSICIBT), F7(DU0_DG6), IRQ(14),
-	F1(LCDD15), F3(FSICOSLD), F7(DU0_DG7), IRQ(15),
-	F1(LCDD16), F4(TPU1TO1), F7(DU0_DB0),
-	F1(LCDD17), F4(SF_IRQ_00), F7(DU0_DB1),
-	F1(LCDD18), F4(SF_IRQ_01), F7(DU0_DB2),
-	F1(LCDD19), F3(SCIFB3_RTS_19), F7(DU0_DB3),
-	F1(LCDD20), F3(SCIFB3_CTS_20), F7(DU0_DB4), /* Port20 */
-	F1(LCDD21), F3(SCIFB3_TXD_21), F7(DU0_DB5),
-	F1(LCDD22), F3(SCIFB3_RXD_22), F7(DU0_DB6),
-	F1(LCDD23), F3(SCIFB3_SCK_23), F7(DU0_DB7),
-	F1(LCDHSYN), F2(LCDCS), F3(SCIFB1_RTS_24),
-	F7(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
-	F1(LCDVSYN), F3(SCIFB1_CTS_25), F7(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
-	F1(LCDDCK), F2(LCDWR), F3(SCIFB1_TXD_26), F7(DU0_DOTCLKIN),
-	F1(LCDDISP), F2(LCDRS), F3(SCIFB1_RXD_27), F7(DU0_DOTCLKOUT),
-	F1(LCDRD_N), F3(SCIFB1_SCK_28), F7(DU0_DOTCLKOUTB),
-	F1(LCDLCLK), F4(SF_IRQ_02), F7(DU0_DISP_CSYNC_N_DE),
-	F1(LCDDON), F4(SF_IRQ_03), F7(DU0_ODDF_N_CLAMP), /* Port30 */
-
-	F1(SCIFA0_RTS), F5(SIM0_DET), F7(CSCIF0_RTS), /* Port32 */
-	F1(SCIFA0_CTS), F5(SIM1_DET), F7(CSCIF0_CTS),
-	F1(SCIFA0_SCK), F5(SIM0_PWRON), F7(CSCIF0_SCK),
-	F1(SCIFA1_RTS), F7(CSCIF1_RTS),
-	F1(SCIFA1_CTS), F7(CSCIF1_CTS),
-	F1(SCIFA1_SCK), F7(CSCIF1_SCK),
-	F1(SCIFB0_RTS), F3(TPU0TO1), F4(SCIFB3_RTS_38), F7(CHSCIF0_HRTS),
-	F1(SCIFB0_CTS), F3(TPU0TO2), F4(SCIFB3_CTS_39), F7(CHSCIF0_HCTS),
-	F1(SCIFB0_SCK), F3(TPU0TO3), F4(SCIFB3_SCK_40),
-	F7(CHSCIF0_HSCK), /* Port40 */
-
-	F1(PDM0_DATA), /* Port64 */
-	F1(PDM1_DATA),
-	F1(HSI_RX_WAKE), F2(SCIFB2_CTS_66), F3(MSIOF3_SYNC), F5(GenIO4),
-	IRQ(40),
-	F1(HSI_RX_READY), F2(SCIFB1_TXD_67), F5(GIO_OUT3_67), F7(CHSCIF1_HTX),
-	F1(HSI_RX_FLAG), F2(SCIFB2_TXD_68), F3(MSIOF3_TXD), F5(GIO_OUT4_68),
-	F1(HSI_RX_DATA), F2(SCIFB2_RXD_69), F3(MSIOF3_RXD), F5(GIO_OUT5_69),
-	F1(HSI_TX_FLAG), F2(SCIFB1_RTS_70), F5(GIO_OUT1_70), F6(HSIC_TSTCLK0),
-	F7(CHSCIF1_HRTS), /* Port70 */
-	F1(HSI_TX_DATA), F2(SCIFB1_CTS_71), F5(GIO_OUT2_71), F6(HSIC_TSTCLK1),
-	F7(CHSCIF1_HCTS),
-	F1(HSI_TX_WAKE), F2(SCIFB1_RXD_72), F5(GenIO8), F7(CHSCIF1_HRX),
-	F1(HSI_TX_READY), F2(SCIFB2_RTS_73), F3(MSIOF3_SCK), F5(GIO_OUT0_73),
-	F1(IRDA_OUT), F1(IRDA_IN), F1(IRDA_FIRSEL), F1(TPU0TO0),
-	F1(DIGRFEN), F1(GPS_TIMESTAMP), F1(TXP), /* Port80 */
-	F1(TXP2), F1(COEX_0), F1(COEX_1), IRQ(19), IRQ(18), /* Port85 */
-
-	F1(KEYIN0), /* Port96 */
-	F1(KEYIN1), F1(KEYIN2), F1(KEYIN3), F1(KEYIN4), /* Port100 */
-	F1(KEYIN5), F1(KEYIN6), IRQ(41), F1(KEYIN7), IRQ(42),
-	F2(KEYOUT0), F2(KEYOUT1), F2(KEYOUT2), F2(KEYOUT3),
-	F2(KEYOUT4), F2(KEYOUT5), IRQ(43), F2(KEYOUT6), IRQ(44), /* Port110 */
-	F2(KEYOUT7), F5(RFANAEN), IRQ(45),
-	F1(KEYIN8), F2(KEYOUT8), F4(SF_IRQ_04), IRQ(46),
-	F1(KEYIN9), F2(KEYOUT9), F4(SF_IRQ_05), IRQ(47),
-	F1(KEYIN10), F2(KEYOUT10), F4(SF_IRQ_06), IRQ(48),
-	F1(KEYIN11), F2(KEYOUT11), F4(SF_IRQ_07), IRQ(49),
-	F1(SCIFA0_TXD), F7(CSCIF0_TX), F1(SCIFA0_RXD), F7(CSCIF0_RX),
-	F1(SCIFA1_TXD), F7(CSCIF1_TX), F1(SCIFA1_RXD), F7(CSCIF1_RX),
-	F3(SF_PORT_1_120), F4(SCIFB3_RXD_120), F7(DU0_CDE), /* Port120 */
-	F3(SF_PORT_0_121), F4(SCIFB3_TXD_121),
-	F1(SCIFB0_TXD), F7(CHSCIF0_HTX),
-	F1(SCIFB0_RXD), F7(CHSCIF0_HRX), F3(ISP_STROBE_124),
-	F1(STP_ISD_0), F2(PDM4_CLK_125), F3(MSIOF2_TXD), F5(SIM0_VOLTSEL0),
-	F1(TS_SDEN), F2(MSIOF7_SYNC), F3(STP_ISEN_1),
-	F1(STP_ISEN_0), F2(PDM1_OUTDATA_128), F3(MSIOF2_SYNC),
-	F5(SIM1_VOLTSEL1), F1(TS_SPSYNC), F2(MSIOF7_RXD), F3(STP_ISSYNC_1),
-	F1(STP_ISSYNC_0), F2(PDM4_DATA_130), F3(MSIOF2_RXD),
-	F5(SIM0_VOLTSEL1), /* Port130 */
-	F1(STP_OPWM_0), F5(SIM1_PWRON), F1(TS_SCK), F2(MSIOF7_SCK),
-	F3(STP_ISCLK_1), F1(STP_ISCLK_0), F2(PDM1_OUTCLK_133), F3(MSIOF2_SCK),
-	F5(SIM1_VOLTSEL0), F1(TS_SDAT), F2(MSIOF7_TXD), F3(STP_ISD_1),
-	IRQ(20), /* Port160 */
-	IRQ(21), IRQ(22), IRQ(23),
-	F1(MMCD0_0), F1(MMCD0_1), F1(MMCD0_2), F1(MMCD0_3),
-	F1(MMCD0_4), F1(MMCD0_5), F1(MMCD0_6), /* Port170 */
-	F1(MMCD0_7), F1(MMCCMD0), F1(MMCCLK0), F1(MMCRST),
-	IRQ(24), IRQ(25), IRQ(26), IRQ(27),
-	F1(A10), F2(MMCD1_7), IRQ(31), /* Port192 */
-	F1(A9), F2(MMCD1_6), IRQ(32),
-	F1(A8), F2(MMCD1_5), IRQ(33),
-	F1(A7), F2(MMCD1_4), IRQ(34),
-	F1(A6), F2(MMCD1_3), IRQ(35),
-	F1(A5), F2(MMCD1_2), IRQ(36),
-	F1(A4), F2(MMCD1_1), IRQ(37),
-	F1(A3), F2(MMCD1_0), IRQ(38),
-	F1(A2), F2(MMCCMD1), IRQ(39), /* Port200 */
-	F1(A1),
-	F1(A0), F2(BS),
-	F1(CKO), F2(MMCCLK1),
-	F1(CS0_N), F5(SIM0_GPO1),
-	F1(CS2_N), F5(SIM0_GPO2),
-	F1(CS4_N), F2(VIO_VD), F5(SIM1_GPO0),
-	F1(D15), F5(GIO_OUT15),
-	F1(D14), F5(GIO_OUT14),
-	F1(D13), F5(GIO_OUT13),
-	F1(D12), F5(GIO_OUT12), /* Port210 */
-	F1(D11), F5(WGM_TXP2),
-	F1(D10), F5(WGM_GPS_TIMEM_ASK_RFCLK),
-	F1(D9), F2(VIO_D9), F5(GIO_OUT9),
-	F1(D8), F2(VIO_D8), F5(GIO_OUT8),
-	F1(D7), F2(VIO_D7), F5(GIO_OUT7),
-	F1(D6), F2(VIO_D6), F5(GIO_OUT6),
-	F1(D5), F2(VIO_D5), F5(GIO_OUT5_217),
-	F1(D4), F2(VIO_D4), F5(GIO_OUT4_218),
-	F1(D3), F2(VIO_D3), F5(GIO_OUT3_219),
-	F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */
-	F1(D1), F2(VIO_D1), F5(GIO_OUT1_221),
-	F1(D0), F2(VIO_D0), F5(GIO_OUT0_222),
-	F1(RDWR_224), F2(VIO_HD), F5(SIM1_GPO2),
-	F1(RD_N), F1(WAIT_N), F2(VIO_CLK), F5(SIM1_GPO1),
-	F1(WE0_N), F2(RDWR_227),
-	F1(WE1_N), F5(SIM0_GPO0),
-	F1(PWMO), F2(VIO_CKO1_229),
-	F1(SLIM_CLK), F2(VIO_CKO4_230), /* Port230 */
-	F1(SLIM_DATA), F2(VIO_CKO5_231), F2(VIO_CKO2_232), F4(SF_PORT_0_232),
-	F2(VIO_CKO3_233), F4(SF_PORT_1_233),
-	F1(FSIACK), F2(PDM3_CLK_234), F3(ISP_IRIS1_234),
-	F1(FSIAISLD), F2(PDM3_DATA_235),
-	F1(FSIAOMC), F2(PDM0_OUTCLK_236), F3(ISP_IRIS0_236),
-	F1(FSIAOLR), F2(FSIAILR), F1(FSIAOBT), F2(FSIAIBT),
-	F1(FSIAOSLD), F2(PDM0_OUTDATA_239),
-	F1(FSIBISLD), /* Port240 */
-	F1(FSIBOLR), F2(FSIBILR), F1(FSIBOMC), F3(ISP_SHUTTER1_242),
-	F1(FSIBOBT), F2(FSIBIBT), F1(FSIBOSLD), F2(FSIASPDIF),
-	F1(FSIBCK), F3(ISP_SHUTTER0_245),
-	F1(ISP_IRIS1_246), F1(ISP_IRIS0_247), F1(ISP_SHUTTER1_248),
-	F1(ISP_SHUTTER0_249), F1(ISP_STROBE_250), /* Port250 */
-	F1(MSIOF0_SYNC), F1(MSIOF0_RXD), F1(MSIOF0_SCK), F1(MSIOF0_SS2),
-	F3(VIO_CKO3_259), F1(MSIOF0_TXD), /* Port260 */
-	F2(SCIFB1_SCK_261), F7(CHSCIF1_HSCK), F2(SCIFB2_SCK_262),
-	F1(MSIOF1_SS2), F4(MSIOF5_SS2), F1(MSIOF1_TXD), F4(MSIOF5_TXD),
-	F1(MSIOF1_RXD), F4(MSIOF5_RXD), F1(MSIOF1_SS1), F4(MSIOF5_SS1),
-	F1(MSIOF0_SS1), F1(MSIOF1_SCK), F4(MSIOF5_SCK),
-	F1(MSIOF1_SYNC), F4(MSIOF5_SYNC),
-	F1(MSIOF2_SS1), F3(VIO_CKO5_270), /* Port270 */
-	F1(MSIOF2_SS2), F3(VIO_CKO2_271), F1(MSIOF3_SS2), F3(VIO_CKO1_272),
-	F1(MSIOF3_SS1), F3(VIO_CKO4_273), F1(MSIOF4_SS2), F4(TPU1TO0),
-	F1(IC_DP), F1(SIM0_RST), F1(IC_DM), F1(SIM0_BSICOMP),
-	F1(SIM0_CLK), F1(SIM0_IO), /* Port280 */
-	F1(SIM1_IO), F2(PDM2_DATA_281), F1(SIM1_CLK), F2(PDM2_CLK_282),
-	F1(SIM1_RST), F1(SDHID1_0), F3(STMDATA0_2),
-	F1(SDHID1_1), F3(STMDATA1_2), IRQ(51), /* Port290 */
-	F1(SDHID1_2), F3(STMDATA2_2), F1(SDHID1_3), F3(STMDATA3_2),
-	F1(SDHICLK1), F3(STMCLK_2), F1(SDHICMD1), F3(STMSIDI_2),
-	F1(SDHID2_0), F2(MSIOF4_TXD), F3(SCIFB2_TXD_295), F4(MSIOF6_TXD),
-	F1(SDHID2_1), F4(MSIOF6_SS2), IRQ(52),
-	F1(SDHID2_2), F2(MSIOF4_RXD), F3(SCIFB2_RXD_297), F4(MSIOF6_RXD),
-	F1(SDHID2_3), F2(MSIOF4_SYNC), F3(SCIFB2_CTS_298), F4(MSIOF6_SYNC),
-	F1(SDHICLK2), F2(MSIOF4_SCK), F3(SCIFB2_SCK_299), F4(MSIOF6_SCK),
-	F1(SDHICMD2), F2(MSIOF4_SS1), F3(SCIFB2_RTS_300),
-	F4(MSIOF6_SS1), /* Port300 */
-	F1(SDHICD0), IRQ(50), F1(SDHID0_0), F3(STMDATA0_1),
-	F1(SDHID0_1), F3(STMDATA1_1), F1(SDHID0_2), F3(STMDATA2_1),
-	F1(SDHID0_3), F3(STMDATA3_1), F1(SDHICMD0), F3(STMSIDI_1),
-	F1(SDHIWP0), F1(SDHICLK0), F3(STMCLK_1), IRQ(16), /* Port320 */
-	IRQ(17), IRQ(28), IRQ(29), IRQ(30), IRQ(53), IRQ(54),
-	IRQ(55), IRQ(56), IRQ(57),
-	PINMUX_MARK_END,
-};
-
-static const u16 pinmux_data[] = {
-	/* specify valid pin states for each pin in GPIO mode */
-	PINMUX_DATA_ALL(),
-
-	/* Port0 */
-	PINMUX_DATA(LCDD0_MARK,		PORT0_FN1),
-	PINMUX_DATA(PDM2_CLK_0_MARK,	PORT0_FN3),
-	PINMUX_DATA(DU0_DR0_MARK,	PORT0_FN7),
-	PINMUX_DATA(IRQ0_MARK,		PORT0_FN0),
-
-	/* Port1 */
-	PINMUX_DATA(LCDD1_MARK,		PORT1_FN1),
-	PINMUX_DATA(PDM2_DATA_1_MARK,	PORT1_FN3,	MSEL3CR_12_0),
-	PINMUX_DATA(DU0_DR19_MARK,	PORT1_FN7),
-	PINMUX_DATA(IRQ1_MARK,		PORT1_FN0),
-
-	/* Port2 */
-	PINMUX_DATA(LCDD2_MARK,		PORT2_FN1),
-	PINMUX_DATA(PDM3_CLK_2_MARK,	PORT2_FN3),
-	PINMUX_DATA(DU0_DR2_MARK,	PORT2_FN7),
-	PINMUX_DATA(IRQ2_MARK,		PORT2_FN0),
-
-	/* Port3 */
-	PINMUX_DATA(LCDD3_MARK,		PORT3_FN1),
-	PINMUX_DATA(PDM3_DATA_3_MARK,	PORT3_FN3,	MSEL3CR_12_0),
-	PINMUX_DATA(DU0_DR3_MARK,	PORT3_FN7),
-	PINMUX_DATA(IRQ3_MARK,		PORT3_FN0),
-
-	/* Port4 */
-	PINMUX_DATA(LCDD4_MARK,		PORT4_FN1),
-	PINMUX_DATA(PDM4_CLK_4_MARK,	PORT4_FN3),
-	PINMUX_DATA(DU0_DR4_MARK,	PORT4_FN7),
-	PINMUX_DATA(IRQ4_MARK,		PORT4_FN0),
-
-	/* Port5 */
-	PINMUX_DATA(LCDD5_MARK,		PORT5_FN1),
-	PINMUX_DATA(PDM4_DATA_5_MARK,	PORT5_FN3,	MSEL3CR_12_0),
-	PINMUX_DATA(DU0_DR5_MARK,	PORT5_FN7),
-	PINMUX_DATA(IRQ5_MARK,		PORT5_FN0),
-
-	/* Port6 */
-	PINMUX_DATA(LCDD6_MARK,		PORT6_FN1),
-	PINMUX_DATA(PDM0_OUTCLK_6_MARK,	PORT6_FN3),
-	PINMUX_DATA(DU0_DR6_MARK,	PORT6_FN7),
-	PINMUX_DATA(IRQ6_MARK,		PORT6_FN0),
-
-	/* Port7 */
-	PINMUX_DATA(LCDD7_MARK,			PORT7_FN1),
-	PINMUX_DATA(PDM0_OUTDATA_7_MARK,	PORT7_FN3),
-	PINMUX_DATA(DU0_DR7_MARK,		PORT7_FN7),
-	PINMUX_DATA(IRQ7_MARK,			PORT7_FN0),
-
-	/* Port8 */
-	PINMUX_DATA(LCDD8_MARK,		PORT8_FN1),
-	PINMUX_DATA(PDM1_OUTCLK_8_MARK,	PORT8_FN3),
-	PINMUX_DATA(DU0_DG0_MARK,	PORT8_FN7),
-	PINMUX_DATA(IRQ8_MARK,		PORT8_FN0),
-
-	/* Port9 */
-	PINMUX_DATA(LCDD9_MARK,		PORT9_FN1),
-	PINMUX_DATA(PDM1_OUTDATA_9_MARK, PORT9_FN3),
-	PINMUX_DATA(DU0_DG1_MARK,	PORT9_FN7),
-	PINMUX_DATA(IRQ9_MARK,		PORT9_FN0),
-
-	/* Port10 */
-	PINMUX_DATA(LCDD10_MARK,		PORT10_FN1),
-	PINMUX_DATA(FSICCK_MARK,		PORT10_FN3),
-	PINMUX_DATA(DU0_DG2_MARK,		PORT10_FN7),
-	PINMUX_DATA(IRQ10_MARK,			PORT10_FN0),
-
-	/* Port11 */
-	PINMUX_DATA(LCDD11_MARK,		PORT11_FN1),
-	PINMUX_DATA(FSICISLD_MARK,		PORT11_FN3),
-	PINMUX_DATA(DU0_DG3_MARK,		PORT11_FN7),
-	PINMUX_DATA(IRQ11_MARK,			PORT11_FN0),
-
-	/* Port12 */
-	PINMUX_DATA(LCDD12_MARK,		PORT12_FN1),
-	PINMUX_DATA(FSICOMC_MARK,		PORT12_FN3),
-	PINMUX_DATA(DU0_DG4_MARK,		PORT12_FN7),
-	PINMUX_DATA(IRQ12_MARK,			PORT12_FN0),
-
-	/* Port13 */
-	PINMUX_DATA(LCDD13_MARK,		PORT13_FN1),
-	PINMUX_DATA(FSICOLR_MARK,		PORT13_FN3),
-	PINMUX_DATA(FSICILR_MARK,		PORT13_FN4),
-	PINMUX_DATA(DU0_DG5_MARK,		PORT13_FN7),
-	PINMUX_DATA(IRQ13_MARK,			PORT13_FN0),
-
-	/* Port14 */
-	PINMUX_DATA(LCDD14_MARK,		PORT14_FN1),
-	PINMUX_DATA(FSICOBT_MARK,		PORT14_FN3),
-	PINMUX_DATA(FSICIBT_MARK,		PORT14_FN4),
-	PINMUX_DATA(DU0_DG6_MARK,		PORT14_FN7),
-	PINMUX_DATA(IRQ14_MARK,			PORT14_FN0),
-
-	/* Port15 */
-	PINMUX_DATA(LCDD15_MARK,		PORT15_FN1),
-	PINMUX_DATA(FSICOSLD_MARK,		PORT15_FN3),
-	PINMUX_DATA(DU0_DG7_MARK,		PORT15_FN7),
-	PINMUX_DATA(IRQ15_MARK,			PORT15_FN0),
-
-	/* Port16 */
-	PINMUX_DATA(LCDD16_MARK,		PORT16_FN1),
-	PINMUX_DATA(TPU1TO1_MARK,		PORT16_FN4),
-	PINMUX_DATA(DU0_DB0_MARK,		PORT16_FN7),
-
-	/* Port17 */
-	PINMUX_DATA(LCDD17_MARK,		PORT17_FN1),
-	PINMUX_DATA(SF_IRQ_00_MARK,		PORT17_FN4),
-	PINMUX_DATA(DU0_DB1_MARK,		PORT17_FN7),
-
-	/* Port18 */
-	PINMUX_DATA(LCDD18_MARK,		PORT18_FN1),
-	PINMUX_DATA(SF_IRQ_01_MARK,		PORT18_FN4),
-	PINMUX_DATA(DU0_DB2_MARK,		PORT18_FN7),
-
-	/* Port19 */
-	PINMUX_DATA(LCDD19_MARK,		PORT19_FN1),
-	PINMUX_DATA(SCIFB3_RTS_19_MARK,		PORT19_FN3),
-	PINMUX_DATA(DU0_DB3_MARK,		PORT19_FN7),
-
-	/* Port20 */
-	PINMUX_DATA(LCDD20_MARK,		PORT20_FN1),
-	PINMUX_DATA(SCIFB3_CTS_20_MARK,		PORT20_FN3,	MSEL3CR_09_0),
-	PINMUX_DATA(DU0_DB4_MARK,		PORT20_FN7),
-
-	/* Port21 */
-	PINMUX_DATA(LCDD21_MARK,		PORT21_FN1),
-	PINMUX_DATA(SCIFB3_TXD_21_MARK,		PORT21_FN3,	MSEL3CR_09_0),
-	PINMUX_DATA(DU0_DB5_MARK,		PORT21_FN7),
-
-	/* Port22 */
-	PINMUX_DATA(LCDD22_MARK,		PORT22_FN1),
-	PINMUX_DATA(SCIFB3_RXD_22_MARK,		PORT22_FN3,	MSEL3CR_09_0),
-	PINMUX_DATA(DU0_DB6_MARK,		PORT22_FN7),
-
-	/* Port23 */
-	PINMUX_DATA(LCDD23_MARK,		PORT23_FN1),
-	PINMUX_DATA(SCIFB3_SCK_23_MARK,		PORT23_FN3),
-	PINMUX_DATA(DU0_DB7_MARK,		PORT23_FN7),
-
-	/* Port24 */
-	PINMUX_DATA(LCDHSYN_MARK,			PORT24_FN1),
-	PINMUX_DATA(LCDCS_MARK,				PORT24_FN2),
-	PINMUX_DATA(SCIFB1_RTS_24_MARK,			PORT24_FN3),
-	PINMUX_DATA(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK,	PORT24_FN7),
-
-	/* Port25 */
-	PINMUX_DATA(LCDVSYN_MARK,			PORT25_FN1),
-	PINMUX_DATA(SCIFB1_CTS_25_MARK, PORT25_FN3, MSEL3CR_11_0),
-	PINMUX_DATA(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK,	PORT25_FN7),
-
-	/* Port26 */
-	PINMUX_DATA(LCDDCK_MARK,		PORT26_FN1),
-	PINMUX_DATA(LCDWR_MARK,			PORT26_FN2),
-	PINMUX_DATA(SCIFB1_TXD_26_MARK,		PORT26_FN3,	MSEL3CR_11_0),
-	PINMUX_DATA(DU0_DOTCLKIN_MARK,		PORT26_FN7),
-
-	/* Port27 */
-	PINMUX_DATA(LCDDISP_MARK,		PORT27_FN1),
-	PINMUX_DATA(LCDRS_MARK,			PORT27_FN2),
-	PINMUX_DATA(SCIFB1_RXD_27_MARK,		PORT27_FN3,	MSEL3CR_11_0),
-	PINMUX_DATA(DU0_DOTCLKOUT_MARK,		PORT27_FN7),
-
-	/* Port28 */
-	PINMUX_DATA(LCDRD_N_MARK,		PORT28_FN1),
-	PINMUX_DATA(SCIFB1_SCK_28_MARK,		PORT28_FN3),
-	PINMUX_DATA(DU0_DOTCLKOUTB_MARK,	PORT28_FN7),
-
-	/* Port29 */
-	PINMUX_DATA(LCDLCLK_MARK,		PORT29_FN1),
-	PINMUX_DATA(SF_IRQ_02_MARK,		PORT29_FN4),
-	PINMUX_DATA(DU0_DISP_CSYNC_N_DE_MARK,	PORT29_FN7),
-
-	/* Port30 */
-	PINMUX_DATA(LCDDON_MARK,		PORT30_FN1),
-	PINMUX_DATA(SF_IRQ_03_MARK,		PORT30_FN4),
-	PINMUX_DATA(DU0_ODDF_N_CLAMP_MARK,	PORT30_FN7),
-
-	/* Port32 */
-	PINMUX_DATA(SCIFA0_RTS_MARK,		PORT32_FN1),
-	PINMUX_DATA(SIM0_DET_MARK,		PORT32_FN5),
-	PINMUX_DATA(CSCIF0_RTS_MARK,		PORT32_FN7),
-
-	/* Port33 */
-	PINMUX_DATA(SCIFA0_CTS_MARK,		PORT33_FN1),
-	PINMUX_DATA(SIM1_DET_MARK,		PORT33_FN5),
-	PINMUX_DATA(CSCIF0_CTS_MARK,		PORT33_FN7),
-
-	/* Port34 */
-	PINMUX_DATA(SCIFA0_SCK_MARK,		PORT34_FN1),
-	PINMUX_DATA(SIM0_PWRON_MARK,		PORT34_FN5),
-	PINMUX_DATA(CSCIF0_SCK_MARK,		PORT34_FN7),
-
-	/* Port35 */
-	PINMUX_DATA(SCIFA1_RTS_MARK,		PORT35_FN1),
-	PINMUX_DATA(CSCIF1_RTS_MARK,		PORT35_FN7),
-
-	/* Port36 */
-	PINMUX_DATA(SCIFA1_CTS_MARK,		PORT36_FN1),
-	PINMUX_DATA(CSCIF1_CTS_MARK,		PORT36_FN7),
-
-	/* Port37 */
-	PINMUX_DATA(SCIFA1_SCK_MARK,		PORT37_FN1),
-	PINMUX_DATA(CSCIF1_SCK_MARK,		PORT37_FN7),
-
-	/* Port38 */
-	PINMUX_DATA(SCIFB0_RTS_MARK,		PORT38_FN1),
-	PINMUX_DATA(TPU0TO1_MARK,		PORT38_FN3),
-	PINMUX_DATA(SCIFB3_RTS_38_MARK,		PORT38_FN4),
-	PINMUX_DATA(CHSCIF0_HRTS_MARK,		PORT38_FN7),
-
-	/* Port39 */
-	PINMUX_DATA(SCIFB0_CTS_MARK,		PORT39_FN1),
-	PINMUX_DATA(TPU0TO2_MARK,		PORT39_FN3),
-	PINMUX_DATA(SCIFB3_CTS_39_MARK,		PORT39_FN4,	MSEL3CR_09_1),
-	PINMUX_DATA(CHSCIF0_HCTS_MARK,		PORT39_FN7),
-
-	/* Port40 */
-	PINMUX_DATA(SCIFB0_SCK_MARK,		PORT40_FN1),
-	PINMUX_DATA(TPU0TO3_MARK,		PORT40_FN3),
-	PINMUX_DATA(SCIFB3_SCK_40_MARK,		PORT40_FN4),
-	PINMUX_DATA(CHSCIF0_HSCK_MARK,		PORT40_FN7),
-
-	/* Port64 */
-	PINMUX_DATA(PDM0_DATA_MARK,		PORT64_FN1),
-
-	/* Port65 */
-	PINMUX_DATA(PDM1_DATA_MARK,		PORT65_FN1),
-
-	/* Port66 */
-	PINMUX_DATA(HSI_RX_WAKE_MARK,		PORT66_FN1),
-	PINMUX_DATA(SCIFB2_CTS_66_MARK,		PORT66_FN2,	MSEL3CR_10_0),
-	PINMUX_DATA(MSIOF3_SYNC_MARK,		PORT66_FN3),
-	PINMUX_DATA(GenIO4_MARK,		PORT66_FN5),
-	PINMUX_DATA(IRQ40_MARK,			PORT66_FN0),
-
-	/* Port67 */
-	PINMUX_DATA(HSI_RX_READY_MARK,		PORT67_FN1),
-	PINMUX_DATA(SCIFB1_TXD_67_MARK,		PORT67_FN2,	MSEL3CR_11_1),
-	PINMUX_DATA(GIO_OUT3_67_MARK,		PORT67_FN5),
-	PINMUX_DATA(CHSCIF1_HTX_MARK,		PORT67_FN7),
-
-	/* Port68 */
-	PINMUX_DATA(HSI_RX_FLAG_MARK,		PORT68_FN1),
-	PINMUX_DATA(SCIFB2_TXD_68_MARK,		PORT68_FN2,	MSEL3CR_10_0),
-	PINMUX_DATA(MSIOF3_TXD_MARK,		PORT68_FN3),
-	PINMUX_DATA(GIO_OUT4_68_MARK,		PORT68_FN5),
-
-	/* Port69 */
-	PINMUX_DATA(HSI_RX_DATA_MARK,		PORT69_FN1),
-	PINMUX_DATA(SCIFB2_RXD_69_MARK,		PORT69_FN2,	MSEL3CR_10_0),
-	PINMUX_DATA(MSIOF3_RXD_MARK,		PORT69_FN3),
-	PINMUX_DATA(GIO_OUT5_69_MARK,		PORT69_FN5),
-
-	/* Port70 */
-	PINMUX_DATA(HSI_TX_FLAG_MARK,		PORT70_FN1),
-	PINMUX_DATA(SCIFB1_RTS_70_MARK,		PORT70_FN2),
-	PINMUX_DATA(GIO_OUT1_70_MARK,		PORT70_FN5),
-	PINMUX_DATA(HSIC_TSTCLK0_MARK,		PORT70_FN6),
-	PINMUX_DATA(CHSCIF1_HRTS_MARK,		PORT70_FN7),
-
-	/* Port71 */
-	PINMUX_DATA(HSI_TX_DATA_MARK,		PORT71_FN1),
-	PINMUX_DATA(SCIFB1_CTS_71_MARK,		PORT71_FN2,	MSEL3CR_11_1),
-	PINMUX_DATA(GIO_OUT2_71_MARK,		PORT71_FN5),
-	PINMUX_DATA(HSIC_TSTCLK1_MARK,		PORT71_FN6),
-	PINMUX_DATA(CHSCIF1_HCTS_MARK,		PORT71_FN7),
-
-	/* Port72 */
-	PINMUX_DATA(HSI_TX_WAKE_MARK,		PORT72_FN1),
-	PINMUX_DATA(SCIFB1_RXD_72_MARK,		PORT72_FN2,	MSEL3CR_11_1),
-	PINMUX_DATA(GenIO8_MARK,		PORT72_FN5),
-	PINMUX_DATA(CHSCIF1_HRX_MARK,		PORT72_FN7),
-
-	/* Port73 */
-	PINMUX_DATA(HSI_TX_READY_MARK,		PORT73_FN1),
-	PINMUX_DATA(SCIFB2_RTS_73_MARK,		PORT73_FN2),
-	PINMUX_DATA(MSIOF3_SCK_MARK,		PORT73_FN3),
-	PINMUX_DATA(GIO_OUT0_73_MARK,		PORT73_FN5),
-
-	/* Port74 - Port85 */
-	PINMUX_DATA(IRDA_OUT_MARK,		PORT74_FN1),
-	PINMUX_DATA(IRDA_IN_MARK,		PORT75_FN1),
-	PINMUX_DATA(IRDA_FIRSEL_MARK,		PORT76_FN1),
-	PINMUX_DATA(TPU0TO0_MARK,		PORT77_FN1),
-	PINMUX_DATA(DIGRFEN_MARK,		PORT78_FN1),
-	PINMUX_DATA(GPS_TIMESTAMP_MARK,		PORT79_FN1),
-	PINMUX_DATA(TXP_MARK,			PORT80_FN1),
-	PINMUX_DATA(TXP2_MARK,			PORT81_FN1),
-	PINMUX_DATA(COEX_0_MARK,		PORT82_FN1),
-	PINMUX_DATA(COEX_1_MARK,		PORT83_FN1),
-	PINMUX_DATA(IRQ19_MARK,			PORT84_FN0),
-	PINMUX_DATA(IRQ18_MARK,			PORT85_FN0),
-
-	/* Port96 - Port101 */
-	PINMUX_DATA(KEYIN0_MARK,		PORT96_FN1),
-	PINMUX_DATA(KEYIN1_MARK,		PORT97_FN1),
-	PINMUX_DATA(KEYIN2_MARK,		PORT98_FN1),
-	PINMUX_DATA(KEYIN3_MARK,		PORT99_FN1),
-	PINMUX_DATA(KEYIN4_MARK,		PORT100_FN1),
-	PINMUX_DATA(KEYIN5_MARK,		PORT101_FN1),
-
-	/* Port102 */
-	PINMUX_DATA(KEYIN6_MARK,		PORT102_FN1),
-	PINMUX_DATA(IRQ41_MARK,			PORT102_FN0),
-
-	/* Port103 */
-	PINMUX_DATA(KEYIN7_MARK,		PORT103_FN1),
-	PINMUX_DATA(IRQ42_MARK,			PORT103_FN0),
-
-	/* Port104 - Port108 */
-	PINMUX_DATA(KEYOUT0_MARK,		PORT104_FN2),
-	PINMUX_DATA(KEYOUT1_MARK,		PORT105_FN2),
-	PINMUX_DATA(KEYOUT2_MARK,		PORT106_FN2),
-	PINMUX_DATA(KEYOUT3_MARK,		PORT107_FN2),
-	PINMUX_DATA(KEYOUT4_MARK,		PORT108_FN2),
-
-	/* Port109 */
-	PINMUX_DATA(KEYOUT5_MARK,		PORT109_FN2),
-	PINMUX_DATA(IRQ43_MARK,			PORT109_FN0),
-
-	/* Port110 */
-	PINMUX_DATA(KEYOUT6_MARK,		PORT110_FN2),
-	PINMUX_DATA(IRQ44_MARK,			PORT110_FN0),
-
-	/* Port111 */
-	PINMUX_DATA(KEYOUT7_MARK,		PORT111_FN2),
-	PINMUX_DATA(RFANAEN_MARK,		PORT111_FN5),
-	PINMUX_DATA(IRQ45_MARK,			PORT111_FN0),
-
-	/* Port112 */
-	PINMUX_DATA(KEYIN8_MARK,		PORT112_FN1),
-	PINMUX_DATA(KEYOUT8_MARK,		PORT112_FN2),
-	PINMUX_DATA(SF_IRQ_04_MARK,		PORT112_FN4),
-	PINMUX_DATA(IRQ46_MARK,			PORT112_FN0),
-
-	/* Port113 */
-	PINMUX_DATA(KEYIN9_MARK,		PORT113_FN1),
-	PINMUX_DATA(KEYOUT9_MARK,		PORT113_FN2),
-	PINMUX_DATA(SF_IRQ_05_MARK,		PORT113_FN4),
-	PINMUX_DATA(IRQ47_MARK,			PORT113_FN0),
-
-	/* Port114 */
-	PINMUX_DATA(KEYIN10_MARK,		PORT114_FN1),
-	PINMUX_DATA(KEYOUT10_MARK,		PORT114_FN2),
-	PINMUX_DATA(SF_IRQ_06_MARK,		PORT114_FN4),
-	PINMUX_DATA(IRQ48_MARK,			PORT114_FN0),
-
-	/* Port115 */
-	PINMUX_DATA(KEYIN11_MARK,		PORT115_FN1),
-	PINMUX_DATA(KEYOUT11_MARK,		PORT115_FN2),
-	PINMUX_DATA(SF_IRQ_07_MARK,		PORT115_FN4),
-	PINMUX_DATA(IRQ49_MARK,			PORT115_FN0),
-
-	/* Port116 */
-	PINMUX_DATA(SCIFA0_TXD_MARK,		PORT116_FN1),
-	PINMUX_DATA(CSCIF0_TX_MARK,		PORT116_FN7),
-
-	/* Port117 */
-	PINMUX_DATA(SCIFA0_RXD_MARK,		PORT117_FN1),
-	PINMUX_DATA(CSCIF0_RX_MARK,		PORT117_FN7),
-
-	/* Port118 */
-	PINMUX_DATA(SCIFA1_TXD_MARK,		PORT118_FN1),
-	PINMUX_DATA(CSCIF1_TX_MARK,		PORT118_FN7),
-
-	/* Port119 */
-	PINMUX_DATA(SCIFA1_RXD_MARK,		PORT119_FN1),
-	PINMUX_DATA(CSCIF1_RX_MARK,		PORT119_FN7),
-
-	/* Port120 */
-	PINMUX_DATA(SF_PORT_1_120_MARK,		PORT120_FN3),
-	PINMUX_DATA(SCIFB3_RXD_120_MARK,	PORT120_FN4,	MSEL3CR_09_1),
-	PINMUX_DATA(DU0_CDE_MARK,		PORT120_FN7),
-
-	/* Port121 */
-	PINMUX_DATA(SF_PORT_0_121_MARK,		PORT121_FN3),
-	PINMUX_DATA(SCIFB3_TXD_121_MARK,	PORT121_FN4,	MSEL3CR_09_1),
-
-	/* Port122 */
-	PINMUX_DATA(SCIFB0_TXD_MARK,		PORT122_FN1),
-	PINMUX_DATA(CHSCIF0_HTX_MARK,		PORT122_FN7),
-
-	/* Port123 */
-	PINMUX_DATA(SCIFB0_RXD_MARK,		PORT123_FN1),
-	PINMUX_DATA(CHSCIF0_HRX_MARK,		PORT123_FN7),
-
-	/* Port124 */
-	PINMUX_DATA(ISP_STROBE_124_MARK,	PORT124_FN3),
-
-	/* Port125 */
-	PINMUX_DATA(STP_ISD_0_MARK,		PORT125_FN1),
-	PINMUX_DATA(PDM4_CLK_125_MARK,		PORT125_FN2),
-	PINMUX_DATA(MSIOF2_TXD_MARK,		PORT125_FN3),
-	PINMUX_DATA(SIM0_VOLTSEL0_MARK,		PORT125_FN5),
-
-	/* Port126 */
-	PINMUX_DATA(TS_SDEN_MARK,		PORT126_FN1),
-	PINMUX_DATA(MSIOF7_SYNC_MARK,		PORT126_FN2),
-	PINMUX_DATA(STP_ISEN_1_MARK,		PORT126_FN3),
-
-	/* Port128 */
-	PINMUX_DATA(STP_ISEN_0_MARK,		PORT128_FN1),
-	PINMUX_DATA(PDM1_OUTDATA_128_MARK,	PORT128_FN2),
-	PINMUX_DATA(MSIOF2_SYNC_MARK,		PORT128_FN3),
-	PINMUX_DATA(SIM1_VOLTSEL1_MARK,		PORT128_FN5),
-
-	/* Port129 */
-	PINMUX_DATA(TS_SPSYNC_MARK,		PORT129_FN1),
-	PINMUX_DATA(MSIOF7_RXD_MARK,		PORT129_FN2),
-	PINMUX_DATA(STP_ISSYNC_1_MARK,		PORT129_FN3),
-
-	/* Port130 */
-	PINMUX_DATA(STP_ISSYNC_0_MARK,		PORT130_FN1),
-	PINMUX_DATA(PDM4_DATA_130_MARK,		PORT130_FN2,	MSEL3CR_12_1),
-	PINMUX_DATA(MSIOF2_RXD_MARK,		PORT130_FN3),
-	PINMUX_DATA(SIM0_VOLTSEL1_MARK,		PORT130_FN5),
-
-	/* Port131 */
-	PINMUX_DATA(STP_OPWM_0_MARK,		PORT131_FN1),
-	PINMUX_DATA(SIM1_PWRON_MARK,		PORT131_FN5),
-
-	/* Port132 */
-	PINMUX_DATA(TS_SCK_MARK,		PORT132_FN1),
-	PINMUX_DATA(MSIOF7_SCK_MARK,		PORT132_FN2),
-	PINMUX_DATA(STP_ISCLK_1_MARK,		PORT132_FN3),
-
-	/* Port133 */
-	PINMUX_DATA(STP_ISCLK_0_MARK,		PORT133_FN1),
-	PINMUX_DATA(PDM1_OUTCLK_133_MARK,	PORT133_FN2),
-	PINMUX_DATA(MSIOF2_SCK_MARK,		PORT133_FN3),
-	PINMUX_DATA(SIM1_VOLTSEL0_MARK,		PORT133_FN5),
-
-	/* Port134 */
-	PINMUX_DATA(TS_SDAT_MARK,		PORT134_FN1),
-	PINMUX_DATA(MSIOF7_TXD_MARK,		PORT134_FN2),
-	PINMUX_DATA(STP_ISD_1_MARK,		PORT134_FN3),
-
-	/* Port160 - Port178 */
-	PINMUX_DATA(IRQ20_MARK,			PORT160_FN0),
-	PINMUX_DATA(IRQ21_MARK,			PORT161_FN0),
-	PINMUX_DATA(IRQ22_MARK,			PORT162_FN0),
-	PINMUX_DATA(IRQ23_MARK,			PORT163_FN0),
-	PINMUX_DATA(MMCD0_0_MARK,		PORT164_FN1),
-	PINMUX_DATA(MMCD0_1_MARK,		PORT165_FN1),
-	PINMUX_DATA(MMCD0_2_MARK,		PORT166_FN1),
-	PINMUX_DATA(MMCD0_3_MARK,		PORT167_FN1),
-	PINMUX_DATA(MMCD0_4_MARK,		PORT168_FN1),
-	PINMUX_DATA(MMCD0_5_MARK,		PORT169_FN1),
-	PINMUX_DATA(MMCD0_6_MARK,		PORT170_FN1),
-	PINMUX_DATA(MMCD0_7_MARK,		PORT171_FN1),
-	PINMUX_DATA(MMCCMD0_MARK,		PORT172_FN1),
-	PINMUX_DATA(MMCCLK0_MARK,		PORT173_FN1),
-	PINMUX_DATA(MMCRST_MARK,		PORT174_FN1),
-	PINMUX_DATA(IRQ24_MARK,			PORT175_FN0),
-	PINMUX_DATA(IRQ25_MARK,			PORT176_FN0),
-	PINMUX_DATA(IRQ26_MARK,			PORT177_FN0),
-	PINMUX_DATA(IRQ27_MARK,			PORT178_FN0),
-
-	/* Port192 - Port200 FN1 */
-	PINMUX_DATA(A10_MARK,		PORT192_FN1),
-	PINMUX_DATA(A9_MARK,		PORT193_FN1),
-	PINMUX_DATA(A8_MARK,		PORT194_FN1),
-	PINMUX_DATA(A7_MARK,		PORT195_FN1),
-	PINMUX_DATA(A6_MARK,		PORT196_FN1),
-	PINMUX_DATA(A5_MARK,		PORT197_FN1),
-	PINMUX_DATA(A4_MARK,		PORT198_FN1),
-	PINMUX_DATA(A3_MARK,		PORT199_FN1),
-	PINMUX_DATA(A2_MARK,		PORT200_FN1),
-
-	/* Port192 - Port200 FN2 */
-	PINMUX_DATA(MMCD1_7_MARK,		PORT192_FN2),
-	PINMUX_DATA(MMCD1_6_MARK,		PORT193_FN2),
-	PINMUX_DATA(MMCD1_5_MARK,		PORT194_FN2),
-	PINMUX_DATA(MMCD1_4_MARK,		PORT195_FN2),
-	PINMUX_DATA(MMCD1_3_MARK,		PORT196_FN2),
-	PINMUX_DATA(MMCD1_2_MARK,		PORT197_FN2),
-	PINMUX_DATA(MMCD1_1_MARK,		PORT198_FN2),
-	PINMUX_DATA(MMCD1_0_MARK,		PORT199_FN2),
-	PINMUX_DATA(MMCCMD1_MARK,		PORT200_FN2),
-
-	/* Port192 - Port200 IRQ */
-	PINMUX_DATA(IRQ31_MARK,			PORT192_FN0),
-	PINMUX_DATA(IRQ32_MARK,			PORT193_FN0),
-	PINMUX_DATA(IRQ33_MARK,			PORT194_FN0),
-	PINMUX_DATA(IRQ34_MARK,			PORT195_FN0),
-	PINMUX_DATA(IRQ35_MARK,			PORT196_FN0),
-	PINMUX_DATA(IRQ36_MARK,			PORT197_FN0),
-	PINMUX_DATA(IRQ37_MARK,			PORT198_FN0),
-	PINMUX_DATA(IRQ38_MARK,			PORT199_FN0),
-	PINMUX_DATA(IRQ39_MARK,			PORT200_FN0),
-
-	/* Port201 */
-	PINMUX_DATA(A1_MARK,		PORT201_FN1),
-
-	/* Port202 */
-	PINMUX_DATA(A0_MARK,		PORT202_FN1),
-	PINMUX_DATA(BS_MARK,		PORT202_FN2),
-
-	/* Port203 */
-	PINMUX_DATA(CKO_MARK,		PORT203_FN1),
-	PINMUX_DATA(MMCCLK1_MARK,	PORT203_FN2),
-
-	/* Port204 */
-	PINMUX_DATA(CS0_N_MARK,		PORT204_FN1),
-	PINMUX_DATA(SIM0_GPO1_MARK,	PORT204_FN5),
-
-	/* Port205 */
-	PINMUX_DATA(CS2_N_MARK,		PORT205_FN1),
-	PINMUX_DATA(SIM0_GPO2_MARK,	PORT205_FN5),
-
-	/* Port206 */
-	PINMUX_DATA(CS4_N_MARK,		PORT206_FN1),
-	PINMUX_DATA(VIO_VD_MARK,	PORT206_FN2),
-	PINMUX_DATA(SIM1_GPO0_MARK,	PORT206_FN5),
-
-	/* Port207 - Port212 FN1 */
-	PINMUX_DATA(D15_MARK,		PORT207_FN1),
-	PINMUX_DATA(D14_MARK,		PORT208_FN1),
-	PINMUX_DATA(D13_MARK,		PORT209_FN1),
-	PINMUX_DATA(D12_MARK,		PORT210_FN1),
-	PINMUX_DATA(D11_MARK,		PORT211_FN1),
-	PINMUX_DATA(D10_MARK,		PORT212_FN1),
-
-	/* Port207 - Port212 FN5 */
-	PINMUX_DATA(GIO_OUT15_MARK,			PORT207_FN5),
-	PINMUX_DATA(GIO_OUT14_MARK,			PORT208_FN5),
-	PINMUX_DATA(GIO_OUT13_MARK,			PORT209_FN5),
-	PINMUX_DATA(GIO_OUT12_MARK,			PORT210_FN5),
-	PINMUX_DATA(WGM_TXP2_MARK,			PORT211_FN5),
-	PINMUX_DATA(WGM_GPS_TIMEM_ASK_RFCLK_MARK,	PORT212_FN5),
-
-	/* Port213 - Port222 FN1 */
-	PINMUX_DATA(D9_MARK,		PORT213_FN1),
-	PINMUX_DATA(D8_MARK,		PORT214_FN1),
-	PINMUX_DATA(D7_MARK,		PORT215_FN1),
-	PINMUX_DATA(D6_MARK,		PORT216_FN1),
-	PINMUX_DATA(D5_MARK,		PORT217_FN1),
-	PINMUX_DATA(D4_MARK,		PORT218_FN1),
-	PINMUX_DATA(D3_MARK,		PORT219_FN1),
-	PINMUX_DATA(D2_MARK,		PORT220_FN1),
-	PINMUX_DATA(D1_MARK,		PORT221_FN1),
-	PINMUX_DATA(D0_MARK,		PORT222_FN1),
-
-	/* Port213 - Port222 FN2 */
-	PINMUX_DATA(VIO_D9_MARK,	PORT213_FN2),
-	PINMUX_DATA(VIO_D8_MARK,	PORT214_FN2),
-	PINMUX_DATA(VIO_D7_MARK,	PORT215_FN2),
-	PINMUX_DATA(VIO_D6_MARK,	PORT216_FN2),
-	PINMUX_DATA(VIO_D5_MARK,	PORT217_FN2),
-	PINMUX_DATA(VIO_D4_MARK,	PORT218_FN2),
-	PINMUX_DATA(VIO_D3_MARK,	PORT219_FN2),
-	PINMUX_DATA(VIO_D2_MARK,	PORT220_FN2),
-	PINMUX_DATA(VIO_D1_MARK,	PORT221_FN2),
-	PINMUX_DATA(VIO_D0_MARK,	PORT222_FN2),
-
-	/* Port213 - Port222 FN5 */
-	PINMUX_DATA(GIO_OUT9_MARK,	PORT213_FN5),
-	PINMUX_DATA(GIO_OUT8_MARK,	PORT214_FN5),
-	PINMUX_DATA(GIO_OUT7_MARK,	PORT215_FN5),
-	PINMUX_DATA(GIO_OUT6_MARK,	PORT216_FN5),
-	PINMUX_DATA(GIO_OUT5_217_MARK,	PORT217_FN5),
-	PINMUX_DATA(GIO_OUT4_218_MARK,	PORT218_FN5),
-	PINMUX_DATA(GIO_OUT3_219_MARK,	PORT219_FN5),
-	PINMUX_DATA(GIO_OUT2_220_MARK,	PORT220_FN5),
-	PINMUX_DATA(GIO_OUT1_221_MARK,	PORT221_FN5),
-	PINMUX_DATA(GIO_OUT0_222_MARK,	PORT222_FN5),
-
-	/* Port224 */
-	PINMUX_DATA(RDWR_224_MARK,	PORT224_FN1),
-	PINMUX_DATA(VIO_HD_MARK,	PORT224_FN2),
-	PINMUX_DATA(SIM1_GPO2_MARK,	PORT224_FN5),
-
-	/* Port225 */
-	PINMUX_DATA(RD_N_MARK,		PORT225_FN1),
-
-	/* Port226 */
-	PINMUX_DATA(WAIT_N_MARK,	PORT226_FN1),
-	PINMUX_DATA(VIO_CLK_MARK,	PORT226_FN2),
-	PINMUX_DATA(SIM1_GPO1_MARK,	PORT226_FN5),
-
-	/* Port227 */
-	PINMUX_DATA(WE0_N_MARK,		PORT227_FN1),
-	PINMUX_DATA(RDWR_227_MARK,	PORT227_FN2),
-
-	/* Port228 */
-	PINMUX_DATA(WE1_N_MARK,		PORT228_FN1),
-	PINMUX_DATA(SIM0_GPO0_MARK,	PORT228_FN5),
-
-	/* Port229 */
-	PINMUX_DATA(PWMO_MARK,		PORT229_FN1),
-	PINMUX_DATA(VIO_CKO1_229_MARK,	PORT229_FN2),
-
-	/* Port230 */
-	PINMUX_DATA(SLIM_CLK_MARK,	PORT230_FN1),
-	PINMUX_DATA(VIO_CKO4_230_MARK,	PORT230_FN2),
-
-	/* Port231 */
-	PINMUX_DATA(SLIM_DATA_MARK,	PORT231_FN1),
-	PINMUX_DATA(VIO_CKO5_231_MARK,	PORT231_FN2),
-
-	/* Port232 */
-	PINMUX_DATA(VIO_CKO2_232_MARK,	PORT232_FN2),
-	PINMUX_DATA(SF_PORT_0_232_MARK,	PORT232_FN4),
-
-	/* Port233 */
-	PINMUX_DATA(VIO_CKO3_233_MARK,	PORT233_FN2),
-	PINMUX_DATA(SF_PORT_1_233_MARK,	PORT233_FN4),
-
-	/* Port234 */
-	PINMUX_DATA(FSIACK_MARK,	PORT234_FN1),
-	PINMUX_DATA(PDM3_CLK_234_MARK,	PORT234_FN2),
-	PINMUX_DATA(ISP_IRIS1_234_MARK,	PORT234_FN3),
-
-	/* Port235 */
-	PINMUX_DATA(FSIAISLD_MARK,	PORT235_FN1),
-	PINMUX_DATA(PDM3_DATA_235_MARK,	PORT235_FN2,	MSEL3CR_12_1),
-
-	/* Port236 */
-	PINMUX_DATA(FSIAOMC_MARK,		PORT236_FN1),
-	PINMUX_DATA(PDM0_OUTCLK_236_MARK,	PORT236_FN2),
-	PINMUX_DATA(ISP_IRIS0_236_MARK,		PORT236_FN3),
-
-	/* Port237 */
-	PINMUX_DATA(FSIAOLR_MARK,	PORT237_FN1),
-	PINMUX_DATA(FSIAILR_MARK,	PORT237_FN2),
-
-	/* Port238 */
-	PINMUX_DATA(FSIAOBT_MARK,	PORT238_FN1),
-	PINMUX_DATA(FSIAIBT_MARK,	PORT238_FN2),
-
-	/* Port239 */
-	PINMUX_DATA(FSIAOSLD_MARK,		PORT239_FN1),
-	PINMUX_DATA(PDM0_OUTDATA_239_MARK,	PORT239_FN2),
-
-	/* Port240 */
-	PINMUX_DATA(FSIBISLD_MARK,	PORT240_FN1),
-
-	/* Port241 */
-	PINMUX_DATA(FSIBOLR_MARK,	PORT241_FN1),
-	PINMUX_DATA(FSIBILR_MARK,	PORT241_FN2),
-
-	/* Port242 */
-	PINMUX_DATA(FSIBOMC_MARK,		PORT242_FN1),
-	PINMUX_DATA(ISP_SHUTTER1_242_MARK,	PORT242_FN3),
-
-	/* Port243 */
-	PINMUX_DATA(FSIBOBT_MARK,	PORT243_FN1),
-	PINMUX_DATA(FSIBIBT_MARK,	PORT243_FN2),
-
-	/* Port244 */
-	PINMUX_DATA(FSIBOSLD_MARK,	PORT244_FN1),
-	PINMUX_DATA(FSIASPDIF_MARK,	PORT244_FN2),
-
-	/* Port245 */
-	PINMUX_DATA(FSIBCK_MARK,		PORT245_FN1),
-	PINMUX_DATA(ISP_SHUTTER0_245_MARK,	PORT245_FN3),
-
-	/* Port246 - Port250 FN1 */
-	PINMUX_DATA(ISP_IRIS1_246_MARK,		PORT246_FN1),
-	PINMUX_DATA(ISP_IRIS0_247_MARK,		PORT247_FN1),
-	PINMUX_DATA(ISP_SHUTTER1_248_MARK,	PORT248_FN1),
-	PINMUX_DATA(ISP_SHUTTER0_249_MARK,	PORT249_FN1),
-	PINMUX_DATA(ISP_STROBE_250_MARK,	PORT250_FN1),
-
-	/* Port256 - Port258 */
-	PINMUX_DATA(MSIOF0_SYNC_MARK,		PORT256_FN1),
-	PINMUX_DATA(MSIOF0_RXD_MARK,		PORT257_FN1),
-	PINMUX_DATA(MSIOF0_SCK_MARK,		PORT258_FN1),
-
-	/* Port259 */
-	PINMUX_DATA(MSIOF0_SS2_MARK,		PORT259_FN1),
-	PINMUX_DATA(VIO_CKO3_259_MARK,		PORT259_FN3),
-
-	/* Port260 */
-	PINMUX_DATA(MSIOF0_TXD_MARK,		PORT260_FN1),
-
-	/* Port261 */
-	PINMUX_DATA(SCIFB1_SCK_261_MARK,	PORT261_FN2),
-	PINMUX_DATA(CHSCIF1_HSCK_MARK,		PORT261_FN7),
-
-	/* Port262 */
-	PINMUX_DATA(SCIFB2_SCK_262_MARK,	PORT262_FN2),
-
-	/* Port263 - Port266 FN1 */
-	PINMUX_DATA(MSIOF1_SS2_MARK,		PORT263_FN1),
-	PINMUX_DATA(MSIOF1_TXD_MARK,		PORT264_FN1),
-	PINMUX_DATA(MSIOF1_RXD_MARK,		PORT265_FN1),
-	PINMUX_DATA(MSIOF1_SS1_MARK,		PORT266_FN1),
-
-	/* Port263 - Port266 FN4 */
-	PINMUX_DATA(MSIOF5_SS2_MARK,		PORT263_FN4),
-	PINMUX_DATA(MSIOF5_TXD_MARK,		PORT264_FN4),
-	PINMUX_DATA(MSIOF5_RXD_MARK,		PORT265_FN4),
-	PINMUX_DATA(MSIOF5_SS1_MARK,		PORT266_FN4),
-
-	/* Port267 */
-	PINMUX_DATA(MSIOF0_SS1_MARK,		PORT267_FN1),
-
-	/* Port268 */
-	PINMUX_DATA(MSIOF1_SCK_MARK,		PORT268_FN1),
-	PINMUX_DATA(MSIOF5_SCK_MARK,		PORT268_FN4),
-
-	/* Port269 */
-	PINMUX_DATA(MSIOF1_SYNC_MARK,		PORT269_FN1),
-	PINMUX_DATA(MSIOF5_SYNC_MARK,		PORT269_FN4),
-
-	/* Port270 - Port273 FN1 */
-	PINMUX_DATA(MSIOF2_SS1_MARK,		PORT270_FN1),
-	PINMUX_DATA(MSIOF2_SS2_MARK,		PORT271_FN1),
-	PINMUX_DATA(MSIOF3_SS2_MARK,		PORT272_FN1),
-	PINMUX_DATA(MSIOF3_SS1_MARK,		PORT273_FN1),
-
-	/* Port270 - Port273 FN3 */
-	PINMUX_DATA(VIO_CKO5_270_MARK,		PORT270_FN3),
-	PINMUX_DATA(VIO_CKO2_271_MARK,		PORT271_FN3),
-	PINMUX_DATA(VIO_CKO1_272_MARK,		PORT272_FN3),
-	PINMUX_DATA(VIO_CKO4_273_MARK,		PORT273_FN3),
-
-	/* Port274 */
-	PINMUX_DATA(MSIOF4_SS2_MARK,		PORT274_FN1),
-	PINMUX_DATA(TPU1TO0_MARK,		PORT274_FN4),
-
-	/* Port275 - Port280 */
-	PINMUX_DATA(IC_DP_MARK,			PORT275_FN1),
-	PINMUX_DATA(SIM0_RST_MARK,		PORT276_FN1),
-	PINMUX_DATA(IC_DM_MARK,			PORT277_FN1),
-	PINMUX_DATA(SIM0_BSICOMP_MARK,		PORT278_FN1),
-	PINMUX_DATA(SIM0_CLK_MARK,		PORT279_FN1),
-	PINMUX_DATA(SIM0_IO_MARK,		PORT280_FN1),
-
-	/* Port281 */
-	PINMUX_DATA(SIM1_IO_MARK,		PORT281_FN1),
-	PINMUX_DATA(PDM2_DATA_281_MARK,		PORT281_FN2,	MSEL3CR_12_1),
-
-	/* Port282 */
-	PINMUX_DATA(SIM1_CLK_MARK,		PORT282_FN1),
-	PINMUX_DATA(PDM2_CLK_282_MARK,		PORT282_FN2),
-
-	/* Port283 */
-	PINMUX_DATA(SIM1_RST_MARK,		PORT283_FN1),
-
-	/* Port289 */
-	PINMUX_DATA(SDHID1_0_MARK,		PORT289_FN1),
-	PINMUX_DATA(STMDATA0_2_MARK,		PORT289_FN3),
-
-	/* Port290 */
-	PINMUX_DATA(SDHID1_1_MARK,		PORT290_FN1),
-	PINMUX_DATA(STMDATA1_2_MARK,		PORT290_FN3),
-	PINMUX_DATA(IRQ51_MARK,			PORT290_FN0),
-
-	/* Port291 - Port294 FN1 */
-	PINMUX_DATA(SDHID1_2_MARK,		PORT291_FN1),
-	PINMUX_DATA(SDHID1_3_MARK,		PORT292_FN1),
-	PINMUX_DATA(SDHICLK1_MARK,		PORT293_FN1),
-	PINMUX_DATA(SDHICMD1_MARK,		PORT294_FN1),
-
-	/* Port291 - Port294 FN3 */
-	PINMUX_DATA(STMDATA2_2_MARK,		PORT291_FN3),
-	PINMUX_DATA(STMDATA3_2_MARK,		PORT292_FN3),
-	PINMUX_DATA(STMCLK_2_MARK,		PORT293_FN3),
-	PINMUX_DATA(STMSIDI_2_MARK,		PORT294_FN3),
-
-	/* Port295 */
-	PINMUX_DATA(SDHID2_0_MARK,		PORT295_FN1),
-	PINMUX_DATA(MSIOF4_TXD_MARK,		PORT295_FN2),
-	PINMUX_DATA(SCIFB2_TXD_295_MARK,	PORT295_FN3,	MSEL3CR_10_1),
-	PINMUX_DATA(MSIOF6_TXD_MARK,		PORT295_FN4),
-
-	/* Port296 */
-	PINMUX_DATA(SDHID2_1_MARK,		PORT296_FN1),
-	PINMUX_DATA(MSIOF6_SS2_MARK,		PORT296_FN4),
-	PINMUX_DATA(IRQ52_MARK,			PORT296_FN0),
-
-	/* Port297 - Port300 FN1 */
-	PINMUX_DATA(SDHID2_2_MARK,		PORT297_FN1),
-	PINMUX_DATA(SDHID2_3_MARK,		PORT298_FN1),
-	PINMUX_DATA(SDHICLK2_MARK,		PORT299_FN1),
-	PINMUX_DATA(SDHICMD2_MARK,		PORT300_FN1),
-
-	/* Port297 - Port300 FN2 */
-	PINMUX_DATA(MSIOF4_RXD_MARK,		PORT297_FN2),
-	PINMUX_DATA(MSIOF4_SYNC_MARK,		PORT298_FN2),
-	PINMUX_DATA(MSIOF4_SCK_MARK,		PORT299_FN2),
-	PINMUX_DATA(MSIOF4_SS1_MARK,		PORT300_FN2),
-
-	/* Port297 - Port300 FN3 */
-	PINMUX_DATA(SCIFB2_RXD_297_MARK,	PORT297_FN3,	MSEL3CR_10_1),
-	PINMUX_DATA(SCIFB2_CTS_298_MARK,	PORT298_FN3,	MSEL3CR_10_1),
-	PINMUX_DATA(SCIFB2_SCK_299_MARK,	PORT299_FN3),
-	PINMUX_DATA(SCIFB2_RTS_300_MARK,	PORT300_FN3),
-
-	/* Port297 - Port300 FN4 */
-	PINMUX_DATA(MSIOF6_RXD_MARK,		PORT297_FN4),
-	PINMUX_DATA(MSIOF6_SYNC_MARK,		PORT298_FN4),
-	PINMUX_DATA(MSIOF6_SCK_MARK,		PORT299_FN4),
-	PINMUX_DATA(MSIOF6_SS1_MARK,		PORT300_FN4),
-
-	/* Port301 */
-	PINMUX_DATA(SDHICD0_MARK,		PORT301_FN1),
-	PINMUX_DATA(IRQ50_MARK,			PORT301_FN0),
-
-	/* Port302 - Port306 FN1 */
-	PINMUX_DATA(SDHID0_0_MARK,		PORT302_FN1),
-	PINMUX_DATA(SDHID0_1_MARK,		PORT303_FN1),
-	PINMUX_DATA(SDHID0_2_MARK,		PORT304_FN1),
-	PINMUX_DATA(SDHID0_3_MARK,		PORT305_FN1),
-	PINMUX_DATA(SDHICMD0_MARK,		PORT306_FN1),
-
-	/* Port302 - Port306 FN3 */
-	PINMUX_DATA(STMDATA0_1_MARK,		PORT302_FN3),
-	PINMUX_DATA(STMDATA1_1_MARK,		PORT303_FN3),
-	PINMUX_DATA(STMDATA2_1_MARK,		PORT304_FN3),
-	PINMUX_DATA(STMDATA3_1_MARK,		PORT305_FN3),
-	PINMUX_DATA(STMSIDI_1_MARK,		PORT306_FN3),
-
-	/* Port307 */
-	PINMUX_DATA(SDHIWP0_MARK,		PORT307_FN1),
-
-	/* Port308 */
-	PINMUX_DATA(SDHICLK0_MARK,		PORT308_FN1),
-	PINMUX_DATA(STMCLK_1_MARK,		PORT308_FN3),
-
-	/* Port320 - Port329 */
-	PINMUX_DATA(IRQ16_MARK,			PORT320_FN0),
-	PINMUX_DATA(IRQ17_MARK,			PORT321_FN0),
-	PINMUX_DATA(IRQ28_MARK,			PORT322_FN0),
-	PINMUX_DATA(IRQ29_MARK,			PORT323_FN0),
-	PINMUX_DATA(IRQ30_MARK,			PORT324_FN0),
-	PINMUX_DATA(IRQ53_MARK,			PORT325_FN0),
-	PINMUX_DATA(IRQ54_MARK,			PORT326_FN0),
-	PINMUX_DATA(IRQ55_MARK,			PORT327_FN0),
-	PINMUX_DATA(IRQ56_MARK,			PORT328_FN0),
-	PINMUX_DATA(IRQ57_MARK,			PORT329_FN0),
-};
-
-#define __O	(SH_PFC_PIN_CFG_OUTPUT)
-#define __IO	(SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
-#define __PUD	(SH_PFC_PIN_CFG_PULL_UP_DOWN)
-
-#define R8A73A4_PIN_IO_PU_PD(pin)       SH_PFC_PIN_CFG(pin, __IO | __PUD)
-#define R8A73A4_PIN_O(pin)              SH_PFC_PIN_CFG(pin, __O)
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
-	R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
-	R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
-	R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7),
-	R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9),
-	R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11),
-	R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13),
-	R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15),
-	R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17),
-	R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19),
-	R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21),
-	R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23),
-	R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25),
-	R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27),
-	R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29),
-	R8A73A4_PIN_IO_PU_PD(30),
-	R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33),
-	R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35),
-	R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37),
-	R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39),
-	R8A73A4_PIN_IO_PU_PD(40),
-	R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65),
-	R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67),
-	R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69),
-	R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71),
-	R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73),
-	R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75),
-	R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77),
-	R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79),
-	R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81),
-	R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83),
-	R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85),
-	R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97),
-	R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99),
-	R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101),
-	R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103),
-	R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105),
-	R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107),
-	R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109),
-	R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111),
-	R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113),
-	R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115),
-	R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117),
-	R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119),
-	R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121),
-	R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123),
-	R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125),
-	R8A73A4_PIN_IO_PU_PD(126),
-	R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129),
-	R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131),
-	R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133),
-	R8A73A4_PIN_IO_PU_PD(134),
-	R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161),
-	R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163),
-	R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165),
-	R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167),
-	R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169),
-	R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171),
-	R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173),
-	R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175),
-	R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177),
-	R8A73A4_PIN_IO_PU_PD(178),
-	R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193),
-	R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195),
-	R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197),
-	R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199),
-	R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201),
-	R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203),
-	R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205),
-	R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207),
-	R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209),
-	R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211),
-	R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213),
-	R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215),
-	R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217),
-	R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219),
-	R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221),
-	R8A73A4_PIN_IO_PU_PD(222),
-	R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225),
-	R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227),
-	R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229),
-	R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231),
-	R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233),
-	R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235),
-	R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237),
-	R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239),
-	R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241),
-	R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243),
-	R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245),
-	R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247),
-	R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249),
-	R8A73A4_PIN_IO_PU_PD(250),
-	R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257),
-	R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259),
-	R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261),
-	R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263),
-	R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265),
-	R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267),
-	R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269),
-	R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271),
-	R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273),
-	R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275),
-	R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277),
-	R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279),
-	R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281),
-	R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283),
-	R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289),
-	R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291),
-	R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293),
-	R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295),
-	R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297),
-	R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299),
-	R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301),
-	R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303),
-	R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305),
-	R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307),
-	R8A73A4_PIN_IO_PU_PD(308),
-	R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321),
-	R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323),
-	R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325),
-	R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327),
-	R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
-};
-
-/* - IRQC ------------------------------------------------------------------- */
-#define IRQC_PINS_MUX(pin, irq_mark)				\
-static const unsigned int irqc_irq##irq_mark##_pins[] = {	\
-	pin,							\
-};								\
-static const unsigned int irqc_irq##irq_mark##_mux[] = {	\
-	IRQ##irq_mark##_MARK,					\
-}
-IRQC_PINS_MUX(0, 0);
-IRQC_PINS_MUX(1, 1);
-IRQC_PINS_MUX(2, 2);
-IRQC_PINS_MUX(3, 3);
-IRQC_PINS_MUX(4, 4);
-IRQC_PINS_MUX(5, 5);
-IRQC_PINS_MUX(6, 6);
-IRQC_PINS_MUX(7, 7);
-IRQC_PINS_MUX(8, 8);
-IRQC_PINS_MUX(9, 9);
-IRQC_PINS_MUX(10, 10);
-IRQC_PINS_MUX(11, 11);
-IRQC_PINS_MUX(12, 12);
-IRQC_PINS_MUX(13, 13);
-IRQC_PINS_MUX(14, 14);
-IRQC_PINS_MUX(15, 15);
-IRQC_PINS_MUX(66, 40);
-IRQC_PINS_MUX(84, 19);
-IRQC_PINS_MUX(85, 18);
-IRQC_PINS_MUX(102, 41);
-IRQC_PINS_MUX(103, 42);
-IRQC_PINS_MUX(109, 43);
-IRQC_PINS_MUX(110, 44);
-IRQC_PINS_MUX(111, 45);
-IRQC_PINS_MUX(112, 46);
-IRQC_PINS_MUX(113, 47);
-IRQC_PINS_MUX(114, 48);
-IRQC_PINS_MUX(115, 49);
-IRQC_PINS_MUX(160, 20);
-IRQC_PINS_MUX(161, 21);
-IRQC_PINS_MUX(162, 22);
-IRQC_PINS_MUX(163, 23);
-IRQC_PINS_MUX(175, 24);
-IRQC_PINS_MUX(176, 25);
-IRQC_PINS_MUX(177, 26);
-IRQC_PINS_MUX(178, 27);
-IRQC_PINS_MUX(192, 31);
-IRQC_PINS_MUX(193, 32);
-IRQC_PINS_MUX(194, 33);
-IRQC_PINS_MUX(195, 34);
-IRQC_PINS_MUX(196, 35);
-IRQC_PINS_MUX(197, 36);
-IRQC_PINS_MUX(198, 37);
-IRQC_PINS_MUX(199, 38);
-IRQC_PINS_MUX(200, 39);
-IRQC_PINS_MUX(290, 51);
-IRQC_PINS_MUX(296, 52);
-IRQC_PINS_MUX(301, 50);
-IRQC_PINS_MUX(320, 16);
-IRQC_PINS_MUX(321, 17);
-IRQC_PINS_MUX(322, 28);
-IRQC_PINS_MUX(323, 29);
-IRQC_PINS_MUX(324, 30);
-IRQC_PINS_MUX(325, 53);
-IRQC_PINS_MUX(326, 54);
-IRQC_PINS_MUX(327, 55);
-IRQC_PINS_MUX(328, 56);
-IRQC_PINS_MUX(329, 57);
-/* - MMCIF0 ----------------------------------------------------------------- */
-static const unsigned int mmc0_data1_pins[] = {
-	/* D[0] */
-	164,
-};
-static const unsigned int mmc0_data1_mux[] = {
-	MMCD0_0_MARK,
-};
-static const unsigned int mmc0_data4_pins[] = {
-	/* D[0:3] */
-	164, 165, 166, 167,
-};
-static const unsigned int mmc0_data4_mux[] = {
-	MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
-};
-static const unsigned int mmc0_data8_pins[] = {
-	/* D[0:7] */
-	164, 165, 166, 167, 168, 169, 170, 171,
-};
-static const unsigned int mmc0_data8_mux[] = {
-	MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
-	MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
-};
-static const unsigned int mmc0_ctrl_pins[] = {
-	/* CMD, CLK */
-	172, 173,
-};
-static const unsigned int mmc0_ctrl_mux[] = {
-	MMCCMD0_MARK, MMCCLK0_MARK,
-};
-/* - MMCIF1 ----------------------------------------------------------------- */
-static const unsigned int mmc1_data1_pins[] = {
-	/* D[0] */
-	199,
-};
-static const unsigned int mmc1_data1_mux[] = {
-	MMCD1_0_MARK,
-};
-static const unsigned int mmc1_data4_pins[] = {
-	/* D[0:3] */
-	199, 198, 197, 196,
-};
-static const unsigned int mmc1_data4_mux[] = {
-	MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
-};
-static const unsigned int mmc1_data8_pins[] = {
-	/* D[0:7] */
-	199, 198, 197, 196, 195, 194, 193, 192,
-};
-static const unsigned int mmc1_data8_mux[] = {
-	MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
-	MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
-};
-static const unsigned int mmc1_ctrl_pins[] = {
-	/* CMD, CLK */
-	200, 203,
-};
-static const unsigned int mmc1_ctrl_mux[] = {
-	MMCCMD1_MARK, MMCCLK1_MARK,
-};
-/* - SCIFA0 ----------------------------------------------------------------- */
-static const unsigned int scifa0_data_pins[] = {
-	/* SCIFA0_RXD, SCIFA0_TXD */
-	117, 116,
-};
-static const unsigned int scifa0_data_mux[] = {
-	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
-};
-static const unsigned int scifa0_clk_pins[] = {
-	/* SCIFA0_SCK */
-	34,
-};
-static const unsigned int scifa0_clk_mux[] = {
-	SCIFA0_SCK_MARK,
-};
-static const unsigned int scifa0_ctrl_pins[] = {
-	/* SCIFA0_RTS, SCIFA0_CTS */
-	32, 33,
-};
-static const unsigned int scifa0_ctrl_mux[] = {
-	SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
-};
-/* - SCIFA1 ----------------------------------------------------------------- */
-static const unsigned int scifa1_data_pins[] = {
-	/* SCIFA1_RXD, SCIFA1_TXD */
-	119, 118,
-};
-static const unsigned int scifa1_data_mux[] = {
-	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
-};
-static const unsigned int scifa1_clk_pins[] = {
-	/* SCIFA1_SCK */
-	37,
-};
-static const unsigned int scifa1_clk_mux[] = {
-	SCIFA1_SCK_MARK,
-};
-static const unsigned int scifa1_ctrl_pins[] = {
-	/* SCIFA1_RTS, SCIFA1_CTS */
-	35, 36,
-};
-static const unsigned int scifa1_ctrl_mux[] = {
-	SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
-};
-/* - SCIFB0 ----------------------------------------------------------------- */
-static const unsigned int scifb0_data_pins[] = {
-	/* SCIFB0_RXD, SCIFB0_TXD */
-	123, 122,
-};
-static const unsigned int scifb0_data_mux[] = {
-	SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
-};
-static const unsigned int scifb0_clk_pins[] = {
-	/* SCIFB0_SCK */
-	40,
-};
-static const unsigned int scifb0_clk_mux[] = {
-	SCIFB0_SCK_MARK,
-};
-static const unsigned int scifb0_ctrl_pins[] = {
-	/* SCIFB0_RTS, SCIFB0_CTS */
-	38, 39,
-};
-static const unsigned int scifb0_ctrl_mux[] = {
-	SCIFB0_RTS_MARK, SCIFB0_CTS_MARK,
-};
-/* - SCIFB1 ----------------------------------------------------------------- */
-static const unsigned int scifb1_data_pins[] = {
-	/* SCIFB1_RXD, SCIFB1_TXD */
-	27, 26,
-};
-static const unsigned int scifb1_data_mux[] = {
-	SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK,
-};
-static const unsigned int scifb1_clk_pins[] = {
-	/* SCIFB1_SCK */
-	28,
-};
-static const unsigned int scifb1_clk_mux[] = {
-	SCIFB1_SCK_28_MARK,
-};
-static const unsigned int scifb1_ctrl_pins[] = {
-	/* SCIFB1_RTS, SCIFB1_CTS */
-	24, 25,
-};
-static const unsigned int scifb1_ctrl_mux[] = {
-	SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK,
-};
-static const unsigned int scifb1_data_b_pins[] = {
-	/* SCIFB1_RXD, SCIFB1_TXD */
-	72, 67,
-};
-static const unsigned int scifb1_data_b_mux[] = {
-	SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK,
-};
-static const unsigned int scifb1_clk_b_pins[] = {
-	/* SCIFB1_SCK */
-	261,
-};
-static const unsigned int scifb1_clk_b_mux[] = {
-	SCIFB1_SCK_261_MARK,
-};
-static const unsigned int scifb1_ctrl_b_pins[] = {
-	/* SCIFB1_RTS, SCIFB1_CTS */
-	70, 71,
-};
-static const unsigned int scifb1_ctrl_b_mux[] = {
-	SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK,
-};
-/* - SCIFB2 ----------------------------------------------------------------- */
-static const unsigned int scifb2_data_pins[] = {
-	/* SCIFB2_RXD, SCIFB2_TXD */
-	69, 68,
-};
-static const unsigned int scifb2_data_mux[] = {
-	SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK,
-};
-static const unsigned int scifb2_clk_pins[] = {
-	/* SCIFB2_SCK */
-	262,
-};
-static const unsigned int scifb2_clk_mux[] = {
-	SCIFB2_SCK_262_MARK,
-};
-static const unsigned int scifb2_ctrl_pins[] = {
-	/* SCIFB2_RTS, SCIFB2_CTS */
-	73, 66,
-};
-static const unsigned int scifb2_ctrl_mux[] = {
-	SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK,
-};
-static const unsigned int scifb2_data_b_pins[] = {
-	/* SCIFB2_RXD, SCIFB2_TXD */
-	297, 295,
-};
-static const unsigned int scifb2_data_b_mux[] = {
-	SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK,
-};
-static const unsigned int scifb2_clk_b_pins[] = {
-	/* SCIFB2_SCK */
-	299,
-};
-static const unsigned int scifb2_clk_b_mux[] = {
-	SCIFB2_SCK_299_MARK,
-};
-static const unsigned int scifb2_ctrl_b_pins[] = {
-	/* SCIFB2_RTS, SCIFB2_CTS */
-	300, 298,
-};
-static const unsigned int scifb2_ctrl_b_mux[] = {
-	SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK,
-};
-/* - SCIFB3 ----------------------------------------------------------------- */
-static const unsigned int scifb3_data_pins[] = {
-	/* SCIFB3_RXD, SCIFB3_TXD */
-	22, 21,
-};
-static const unsigned int scifb3_data_mux[] = {
-	SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK,
-};
-static const unsigned int scifb3_clk_pins[] = {
-	/* SCIFB3_SCK */
-	23,
-};
-static const unsigned int scifb3_clk_mux[] = {
-	SCIFB3_SCK_23_MARK,
-};
-static const unsigned int scifb3_ctrl_pins[] = {
-	/* SCIFB3_RTS, SCIFB3_CTS */
-	19, 20,
-};
-static const unsigned int scifb3_ctrl_mux[] = {
-	SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK,
-};
-static const unsigned int scifb3_data_b_pins[] = {
-	/* SCIFB3_RXD, SCIFB3_TXD */
-	120, 121,
-};
-static const unsigned int scifb3_data_b_mux[] = {
-	SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK,
-};
-static const unsigned int scifb3_clk_b_pins[] = {
-	/* SCIFB3_SCK */
-	40,
-};
-static const unsigned int scifb3_clk_b_mux[] = {
-	SCIFB3_SCK_40_MARK,
-};
-static const unsigned int scifb3_ctrl_b_pins[] = {
-	/* SCIFB3_RTS, SCIFB3_CTS */
-	38, 39,
-};
-static const unsigned int scifb3_ctrl_b_mux[] = {
-	SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
-};
-/* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
-	/* D0 */
-	302,
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SDHID0_0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
-	/* D[0:3] */
-	302, 303, 304, 305,
-};
-static const unsigned int sdhi0_data4_mux[] = {
-	SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
-};
-static const unsigned int sdhi0_ctrl_pins[] = {
-	/* CLK, CMD */
-	308, 306,
-};
-static const unsigned int sdhi0_ctrl_mux[] = {
-	SDHICLK0_MARK, SDHICMD0_MARK,
-};
-static const unsigned int sdhi0_cd_pins[] = {
-	/* CD */
-	301,
-};
-static const unsigned int sdhi0_cd_mux[] = {
-	SDHICD0_MARK,
-};
-static const unsigned int sdhi0_wp_pins[] = {
-	/* WP */
-	307,
-};
-static const unsigned int sdhi0_wp_mux[] = {
-	SDHIWP0_MARK,
-};
-/* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
-	/* D0 */
-	289,
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	SDHID1_0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
-	/* D[0:3] */
-	289, 290, 291, 292,
-};
-static const unsigned int sdhi1_data4_mux[] = {
-	SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
-};
-static const unsigned int sdhi1_ctrl_pins[] = {
-	/* CLK, CMD */
-	293, 294,
-};
-static const unsigned int sdhi1_ctrl_mux[] = {
-	SDHICLK1_MARK, SDHICMD1_MARK,
-};
-/* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
-	/* D0 */
-	295,
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SDHID2_0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
-	/* D[0:3] */
-	295, 296, 297, 298,
-};
-static const unsigned int sdhi2_data4_mux[] = {
-	SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
-};
-static const unsigned int sdhi2_ctrl_pins[] = {
-	/* CLK, CMD */
-	299, 300,
-};
-static const unsigned int sdhi2_ctrl_mux[] = {
-	SDHICLK2_MARK, SDHICMD2_MARK,
-};
-
-static const struct sh_pfc_pin_group pinmux_groups[] = {
-	SH_PFC_PIN_GROUP(irqc_irq0),
-	SH_PFC_PIN_GROUP(irqc_irq1),
-	SH_PFC_PIN_GROUP(irqc_irq2),
-	SH_PFC_PIN_GROUP(irqc_irq3),
-	SH_PFC_PIN_GROUP(irqc_irq4),
-	SH_PFC_PIN_GROUP(irqc_irq5),
-	SH_PFC_PIN_GROUP(irqc_irq6),
-	SH_PFC_PIN_GROUP(irqc_irq7),
-	SH_PFC_PIN_GROUP(irqc_irq8),
-	SH_PFC_PIN_GROUP(irqc_irq9),
-	SH_PFC_PIN_GROUP(irqc_irq10),
-	SH_PFC_PIN_GROUP(irqc_irq11),
-	SH_PFC_PIN_GROUP(irqc_irq12),
-	SH_PFC_PIN_GROUP(irqc_irq13),
-	SH_PFC_PIN_GROUP(irqc_irq14),
-	SH_PFC_PIN_GROUP(irqc_irq15),
-	SH_PFC_PIN_GROUP(irqc_irq16),
-	SH_PFC_PIN_GROUP(irqc_irq17),
-	SH_PFC_PIN_GROUP(irqc_irq18),
-	SH_PFC_PIN_GROUP(irqc_irq19),
-	SH_PFC_PIN_GROUP(irqc_irq20),
-	SH_PFC_PIN_GROUP(irqc_irq21),
-	SH_PFC_PIN_GROUP(irqc_irq22),
-	SH_PFC_PIN_GROUP(irqc_irq23),
-	SH_PFC_PIN_GROUP(irqc_irq24),
-	SH_PFC_PIN_GROUP(irqc_irq25),
-	SH_PFC_PIN_GROUP(irqc_irq26),
-	SH_PFC_PIN_GROUP(irqc_irq27),
-	SH_PFC_PIN_GROUP(irqc_irq28),
-	SH_PFC_PIN_GROUP(irqc_irq29),
-	SH_PFC_PIN_GROUP(irqc_irq30),
-	SH_PFC_PIN_GROUP(irqc_irq31),
-	SH_PFC_PIN_GROUP(irqc_irq32),
-	SH_PFC_PIN_GROUP(irqc_irq33),
-	SH_PFC_PIN_GROUP(irqc_irq34),
-	SH_PFC_PIN_GROUP(irqc_irq35),
-	SH_PFC_PIN_GROUP(irqc_irq36),
-	SH_PFC_PIN_GROUP(irqc_irq37),
-	SH_PFC_PIN_GROUP(irqc_irq38),
-	SH_PFC_PIN_GROUP(irqc_irq39),
-	SH_PFC_PIN_GROUP(irqc_irq40),
-	SH_PFC_PIN_GROUP(irqc_irq41),
-	SH_PFC_PIN_GROUP(irqc_irq42),
-	SH_PFC_PIN_GROUP(irqc_irq43),
-	SH_PFC_PIN_GROUP(irqc_irq44),
-	SH_PFC_PIN_GROUP(irqc_irq45),
-	SH_PFC_PIN_GROUP(irqc_irq46),
-	SH_PFC_PIN_GROUP(irqc_irq47),
-	SH_PFC_PIN_GROUP(irqc_irq48),
-	SH_PFC_PIN_GROUP(irqc_irq49),
-	SH_PFC_PIN_GROUP(irqc_irq50),
-	SH_PFC_PIN_GROUP(irqc_irq51),
-	SH_PFC_PIN_GROUP(irqc_irq52),
-	SH_PFC_PIN_GROUP(irqc_irq53),
-	SH_PFC_PIN_GROUP(irqc_irq54),
-	SH_PFC_PIN_GROUP(irqc_irq55),
-	SH_PFC_PIN_GROUP(irqc_irq56),
-	SH_PFC_PIN_GROUP(irqc_irq57),
-	SH_PFC_PIN_GROUP(mmc0_data1),
-	SH_PFC_PIN_GROUP(mmc0_data4),
-	SH_PFC_PIN_GROUP(mmc0_data8),
-	SH_PFC_PIN_GROUP(mmc0_ctrl),
-	SH_PFC_PIN_GROUP(mmc1_data1),
-	SH_PFC_PIN_GROUP(mmc1_data4),
-	SH_PFC_PIN_GROUP(mmc1_data8),
-	SH_PFC_PIN_GROUP(mmc1_ctrl),
-	SH_PFC_PIN_GROUP(scifa0_data),
-	SH_PFC_PIN_GROUP(scifa0_clk),
-	SH_PFC_PIN_GROUP(scifa0_ctrl),
-	SH_PFC_PIN_GROUP(scifa1_data),
-	SH_PFC_PIN_GROUP(scifa1_clk),
-	SH_PFC_PIN_GROUP(scifa1_ctrl),
-	SH_PFC_PIN_GROUP(scifb0_data),
-	SH_PFC_PIN_GROUP(scifb0_clk),
-	SH_PFC_PIN_GROUP(scifb0_ctrl),
-	SH_PFC_PIN_GROUP(scifb1_data),
-	SH_PFC_PIN_GROUP(scifb1_clk),
-	SH_PFC_PIN_GROUP(scifb1_ctrl),
-	SH_PFC_PIN_GROUP(scifb1_data_b),
-	SH_PFC_PIN_GROUP(scifb1_clk_b),
-	SH_PFC_PIN_GROUP(scifb1_ctrl_b),
-	SH_PFC_PIN_GROUP(scifb2_data),
-	SH_PFC_PIN_GROUP(scifb2_clk),
-	SH_PFC_PIN_GROUP(scifb2_ctrl),
-	SH_PFC_PIN_GROUP(scifb2_data_b),
-	SH_PFC_PIN_GROUP(scifb2_clk_b),
-	SH_PFC_PIN_GROUP(scifb2_ctrl_b),
-	SH_PFC_PIN_GROUP(scifb3_data),
-	SH_PFC_PIN_GROUP(scifb3_clk),
-	SH_PFC_PIN_GROUP(scifb3_ctrl),
-	SH_PFC_PIN_GROUP(scifb3_data_b),
-	SH_PFC_PIN_GROUP(scifb3_clk_b),
-	SH_PFC_PIN_GROUP(scifb3_ctrl_b),
-	SH_PFC_PIN_GROUP(sdhi0_data1),
-	SH_PFC_PIN_GROUP(sdhi0_data4),
-	SH_PFC_PIN_GROUP(sdhi0_ctrl),
-	SH_PFC_PIN_GROUP(sdhi0_cd),
-	SH_PFC_PIN_GROUP(sdhi0_wp),
-	SH_PFC_PIN_GROUP(sdhi1_data1),
-	SH_PFC_PIN_GROUP(sdhi1_data4),
-	SH_PFC_PIN_GROUP(sdhi1_ctrl),
-	SH_PFC_PIN_GROUP(sdhi2_data1),
-	SH_PFC_PIN_GROUP(sdhi2_data4),
-	SH_PFC_PIN_GROUP(sdhi2_ctrl),
-};
-
-static const char * const irqc_groups[] = {
-	"irqc_irq0",
-	"irqc_irq1",
-	"irqc_irq2",
-	"irqc_irq3",
-	"irqc_irq4",
-	"irqc_irq5",
-	"irqc_irq6",
-	"irqc_irq7",
-	"irqc_irq8",
-	"irqc_irq9",
-	"irqc_irq10",
-	"irqc_irq11",
-	"irqc_irq12",
-	"irqc_irq13",
-	"irqc_irq14",
-	"irqc_irq15",
-	"irqc_irq16",
-	"irqc_irq17",
-	"irqc_irq18",
-	"irqc_irq19",
-	"irqc_irq20",
-	"irqc_irq21",
-	"irqc_irq22",
-	"irqc_irq23",
-	"irqc_irq24",
-	"irqc_irq25",
-	"irqc_irq26",
-	"irqc_irq27",
-	"irqc_irq28",
-	"irqc_irq29",
-	"irqc_irq30",
-	"irqc_irq31",
-	"irqc_irq32",
-	"irqc_irq33",
-	"irqc_irq34",
-	"irqc_irq35",
-	"irqc_irq36",
-	"irqc_irq37",
-	"irqc_irq38",
-	"irqc_irq39",
-	"irqc_irq40",
-	"irqc_irq41",
-	"irqc_irq42",
-	"irqc_irq43",
-	"irqc_irq44",
-	"irqc_irq45",
-	"irqc_irq46",
-	"irqc_irq47",
-	"irqc_irq48",
-	"irqc_irq49",
-	"irqc_irq50",
-	"irqc_irq51",
-	"irqc_irq52",
-	"irqc_irq53",
-	"irqc_irq54",
-	"irqc_irq55",
-	"irqc_irq56",
-	"irqc_irq57",
-};
-
-static const char * const mmc0_groups[] = {
-	"mmc0_data1",
-	"mmc0_data4",
-	"mmc0_data8",
-	"mmc0_ctrl",
-};
-
-static const char * const mmc1_groups[] = {
-	"mmc1_data1",
-	"mmc1_data4",
-	"mmc1_data8",
-	"mmc1_ctrl",
-};
-
-static const char * const scifa0_groups[] = {
-	"scifa0_data",
-	"scifa0_clk",
-	"scifa0_ctrl",
-};
-
-static const char * const scifa1_groups[] = {
-	"scifa1_data",
-	"scifa1_clk",
-	"scifa1_ctrl",
-};
-
-static const char * const scifb0_groups[] = {
-	"scifb0_data",
-	"scifb0_clk",
-	"scifb0_ctrl",
-};
-
-static const char * const scifb1_groups[] = {
-	"scifb1_data",
-	"scifb1_clk",
-	"scifb1_ctrl",
-	"scifb1_data_b",
-	"scifb1_clk_b",
-	"scifb1_ctrl_b",
-};
-
-static const char * const scifb2_groups[] = {
-	"scifb2_data",
-	"scifb2_clk",
-	"scifb2_ctrl",
-	"scifb2_data_b",
-	"scifb2_clk_b",
-	"scifb2_ctrl_b",
-};
-
-static const char * const scifb3_groups[] = {
-	"scifb3_data",
-	"scifb3_clk",
-	"scifb3_ctrl",
-	"scifb3_data_b",
-	"scifb3_clk_b",
-	"scifb3_ctrl_b",
-};
-
-static const char * const sdhi0_groups[] = {
-	"sdhi0_data1",
-	"sdhi0_data4",
-	"sdhi0_ctrl",
-	"sdhi0_cd",
-	"sdhi0_wp",
-};
-
-static const char * const sdhi1_groups[] = {
-	"sdhi1_data1",
-	"sdhi1_data4",
-	"sdhi1_ctrl",
-};
-
-static const char * const sdhi2_groups[] = {
-	"sdhi2_data1",
-	"sdhi2_data4",
-	"sdhi2_ctrl",
-};
-
-static const struct sh_pfc_function pinmux_functions[] = {
-	SH_PFC_FUNCTION(irqc),
-	SH_PFC_FUNCTION(mmc0),
-	SH_PFC_FUNCTION(mmc1),
-	SH_PFC_FUNCTION(scifa0),
-	SH_PFC_FUNCTION(scifa1),
-	SH_PFC_FUNCTION(scifb0),
-	SH_PFC_FUNCTION(scifb1),
-	SH_PFC_FUNCTION(scifb2),
-	SH_PFC_FUNCTION(scifb3),
-	SH_PFC_FUNCTION(sdhi0),
-	SH_PFC_FUNCTION(sdhi1),
-	SH_PFC_FUNCTION(sdhi2),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	PORTCR(0, 0xe6050000),
-	PORTCR(1, 0xe6050001),
-	PORTCR(2, 0xe6050002),
-	PORTCR(3, 0xe6050003),
-	PORTCR(4, 0xe6050004),
-	PORTCR(5, 0xe6050005),
-	PORTCR(6, 0xe6050006),
-	PORTCR(7, 0xe6050007),
-	PORTCR(8, 0xe6050008),
-	PORTCR(9, 0xe6050009),
-	PORTCR(10, 0xe605000A),
-	PORTCR(11, 0xe605000B),
-	PORTCR(12, 0xe605000C),
-	PORTCR(13, 0xe605000D),
-	PORTCR(14, 0xe605000E),
-	PORTCR(15, 0xe605000F),
-	PORTCR(16, 0xe6050010),
-	PORTCR(17, 0xe6050011),
-	PORTCR(18, 0xe6050012),
-	PORTCR(19, 0xe6050013),
-	PORTCR(20, 0xe6050014),
-	PORTCR(21, 0xe6050015),
-	PORTCR(22, 0xe6050016),
-	PORTCR(23, 0xe6050017),
-	PORTCR(24, 0xe6050018),
-	PORTCR(25, 0xe6050019),
-	PORTCR(26, 0xe605001A),
-	PORTCR(27, 0xe605001B),
-	PORTCR(28, 0xe605001C),
-	PORTCR(29, 0xe605001D),
-	PORTCR(30, 0xe605001E),
-	PORTCR(32, 0xe6051020),
-	PORTCR(33, 0xe6051021),
-	PORTCR(34, 0xe6051022),
-	PORTCR(35, 0xe6051023),
-	PORTCR(36, 0xe6051024),
-	PORTCR(37, 0xe6051025),
-	PORTCR(38, 0xe6051026),
-	PORTCR(39, 0xe6051027),
-	PORTCR(40, 0xe6051028),
-	PORTCR(64, 0xe6050040),
-	PORTCR(65, 0xe6050041),
-	PORTCR(66, 0xe6050042),
-	PORTCR(67, 0xe6050043),
-	PORTCR(68, 0xe6050044),
-	PORTCR(69, 0xe6050045),
-	PORTCR(70, 0xe6050046),
-	PORTCR(71, 0xe6050047),
-	PORTCR(72, 0xe6050048),
-	PORTCR(73, 0xe6050049),
-	PORTCR(74, 0xe605004A),
-	PORTCR(75, 0xe605004B),
-	PORTCR(76, 0xe605004C),
-	PORTCR(77, 0xe605004D),
-	PORTCR(78, 0xe605004E),
-	PORTCR(79, 0xe605004F),
-	PORTCR(80, 0xe6050050),
-	PORTCR(81, 0xe6050051),
-	PORTCR(82, 0xe6050052),
-	PORTCR(83, 0xe6050053),
-	PORTCR(84, 0xe6050054),
-	PORTCR(85, 0xe6050055),
-	PORTCR(96, 0xe6051060),
-	PORTCR(97, 0xe6051061),
-	PORTCR(98, 0xe6051062),
-	PORTCR(99, 0xe6051063),
-	PORTCR(100, 0xe6051064),
-	PORTCR(101, 0xe6051065),
-	PORTCR(102, 0xe6051066),
-	PORTCR(103, 0xe6051067),
-	PORTCR(104, 0xe6051068),
-	PORTCR(105, 0xe6051069),
-	PORTCR(106, 0xe605106A),
-	PORTCR(107, 0xe605106B),
-	PORTCR(108, 0xe605106C),
-	PORTCR(109, 0xe605106D),
-	PORTCR(110, 0xe605106E),
-	PORTCR(111, 0xe605106F),
-	PORTCR(112, 0xe6051070),
-	PORTCR(113, 0xe6051071),
-	PORTCR(114, 0xe6051072),
-	PORTCR(115, 0xe6051073),
-	PORTCR(116, 0xe6051074),
-	PORTCR(117, 0xe6051075),
-	PORTCR(118, 0xe6051076),
-	PORTCR(119, 0xe6051077),
-	PORTCR(120, 0xe6051078),
-	PORTCR(121, 0xe6051079),
-	PORTCR(122, 0xe605107A),
-	PORTCR(123, 0xe605107B),
-	PORTCR(124, 0xe605107C),
-	PORTCR(125, 0xe605107D),
-	PORTCR(126, 0xe605107E),
-	PORTCR(128, 0xe6051080),
-	PORTCR(129, 0xe6051081),
-	PORTCR(130, 0xe6051082),
-	PORTCR(131, 0xe6051083),
-	PORTCR(132, 0xe6051084),
-	PORTCR(133, 0xe6051085),
-	PORTCR(134, 0xe6051086),
-	PORTCR(160, 0xe60520A0),
-	PORTCR(161, 0xe60520A1),
-	PORTCR(162, 0xe60520A2),
-	PORTCR(163, 0xe60520A3),
-	PORTCR(164, 0xe60520A4),
-	PORTCR(165, 0xe60520A5),
-	PORTCR(166, 0xe60520A6),
-	PORTCR(167, 0xe60520A7),
-	PORTCR(168, 0xe60520A8),
-	PORTCR(169, 0xe60520A9),
-	PORTCR(170, 0xe60520AA),
-	PORTCR(171, 0xe60520AB),
-	PORTCR(172, 0xe60520AC),
-	PORTCR(173, 0xe60520AD),
-	PORTCR(174, 0xe60520AE),
-	PORTCR(175, 0xe60520AF),
-	PORTCR(176, 0xe60520B0),
-	PORTCR(177, 0xe60520B1),
-	PORTCR(178, 0xe60520B2),
-	PORTCR(192, 0xe60520C0),
-	PORTCR(193, 0xe60520C1),
-	PORTCR(194, 0xe60520C2),
-	PORTCR(195, 0xe60520C3),
-	PORTCR(196, 0xe60520C4),
-	PORTCR(197, 0xe60520C5),
-	PORTCR(198, 0xe60520C6),
-	PORTCR(199, 0xe60520C7),
-	PORTCR(200, 0xe60520C8),
-	PORTCR(201, 0xe60520C9),
-	PORTCR(202, 0xe60520CA),
-	PORTCR(203, 0xe60520CB),
-	PORTCR(204, 0xe60520CC),
-	PORTCR(205, 0xe60520CD),
-	PORTCR(206, 0xe60520CE),
-	PORTCR(207, 0xe60520CF),
-	PORTCR(208, 0xe60520D0),
-	PORTCR(209, 0xe60520D1),
-	PORTCR(210, 0xe60520D2),
-	PORTCR(211, 0xe60520D3),
-	PORTCR(212, 0xe60520D4),
-	PORTCR(213, 0xe60520D5),
-	PORTCR(214, 0xe60520D6),
-	PORTCR(215, 0xe60520D7),
-	PORTCR(216, 0xe60520D8),
-	PORTCR(217, 0xe60520D9),
-	PORTCR(218, 0xe60520DA),
-	PORTCR(219, 0xe60520DB),
-	PORTCR(220, 0xe60520DC),
-	PORTCR(221, 0xe60520DD),
-	PORTCR(222, 0xe60520DE),
-	PORTCR(224, 0xe60520E0),
-	PORTCR(225, 0xe60520E1),
-	PORTCR(226, 0xe60520E2),
-	PORTCR(227, 0xe60520E3),
-	PORTCR(228, 0xe60520E4),
-	PORTCR(229, 0xe60520E5),
-	PORTCR(230, 0xe60520e6),
-	PORTCR(231, 0xe60520E7),
-	PORTCR(232, 0xe60520E8),
-	PORTCR(233, 0xe60520E9),
-	PORTCR(234, 0xe60520EA),
-	PORTCR(235, 0xe60520EB),
-	PORTCR(236, 0xe60520EC),
-	PORTCR(237, 0xe60520ED),
-	PORTCR(238, 0xe60520EE),
-	PORTCR(239, 0xe60520EF),
-	PORTCR(240, 0xe60520F0),
-	PORTCR(241, 0xe60520F1),
-	PORTCR(242, 0xe60520F2),
-	PORTCR(243, 0xe60520F3),
-	PORTCR(244, 0xe60520F4),
-	PORTCR(245, 0xe60520F5),
-	PORTCR(246, 0xe60520F6),
-	PORTCR(247, 0xe60520F7),
-	PORTCR(248, 0xe60520F8),
-	PORTCR(249, 0xe60520F9),
-	PORTCR(250, 0xe60520FA),
-	PORTCR(256, 0xe6052100),
-	PORTCR(257, 0xe6052101),
-	PORTCR(258, 0xe6052102),
-	PORTCR(259, 0xe6052103),
-	PORTCR(260, 0xe6052104),
-	PORTCR(261, 0xe6052105),
-	PORTCR(262, 0xe6052106),
-	PORTCR(263, 0xe6052107),
-	PORTCR(264, 0xe6052108),
-	PORTCR(265, 0xe6052109),
-	PORTCR(266, 0xe605210A),
-	PORTCR(267, 0xe605210B),
-	PORTCR(268, 0xe605210C),
-	PORTCR(269, 0xe605210D),
-	PORTCR(270, 0xe605210E),
-	PORTCR(271, 0xe605210F),
-	PORTCR(272, 0xe6052110),
-	PORTCR(273, 0xe6052111),
-	PORTCR(274, 0xe6052112),
-	PORTCR(275, 0xe6052113),
-	PORTCR(276, 0xe6052114),
-	PORTCR(277, 0xe6052115),
-	PORTCR(278, 0xe6052116),
-	PORTCR(279, 0xe6052117),
-	PORTCR(280, 0xe6052118),
-	PORTCR(281, 0xe6052119),
-	PORTCR(282, 0xe605211A),
-	PORTCR(283, 0xe605211B),
-	PORTCR(288, 0xe6053120),
-	PORTCR(289, 0xe6053121),
-	PORTCR(290, 0xe6053122),
-	PORTCR(291, 0xe6053123),
-	PORTCR(292, 0xe6053124),
-	PORTCR(293, 0xe6053125),
-	PORTCR(294, 0xe6053126),
-	PORTCR(295, 0xe6053127),
-	PORTCR(296, 0xe6053128),
-	PORTCR(297, 0xe6053129),
-	PORTCR(298, 0xe605312A),
-	PORTCR(299, 0xe605312B),
-	PORTCR(300, 0xe605312C),
-	PORTCR(301, 0xe605312D),
-	PORTCR(302, 0xe605312E),
-	PORTCR(303, 0xe605312F),
-	PORTCR(304, 0xe6053130),
-	PORTCR(305, 0xe6053131),
-	PORTCR(306, 0xe6053132),
-	PORTCR(307, 0xe6053133),
-	PORTCR(308, 0xe6053134),
-	PORTCR(320, 0xe6053140),
-	PORTCR(321, 0xe6053141),
-	PORTCR(322, 0xe6053142),
-	PORTCR(323, 0xe6053143),
-	PORTCR(324, 0xe6053144),
-	PORTCR(325, 0xe6053145),
-	PORTCR(326, 0xe6053146),
-	PORTCR(327, 0xe6053147),
-	PORTCR(328, 0xe6053148),
-	PORTCR(329, 0xe6053149),
-
-	{ PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1, GROUP(
-			MSEL1CR_31_0, MSEL1CR_31_1,
-			0, 0,
-			0, 0,
-			0, 0,
-			MSEL1CR_27_0, MSEL1CR_27_1,
-			0, 0,
-			MSEL1CR_25_0, MSEL1CR_25_1,
-			MSEL1CR_24_0, MSEL1CR_24_1,
-			0, 0,
-			MSEL1CR_22_0, MSEL1CR_22_1,
-			MSEL1CR_21_0, MSEL1CR_21_1,
-			MSEL1CR_20_0, MSEL1CR_20_1,
-			MSEL1CR_19_0, MSEL1CR_19_1,
-			MSEL1CR_18_0, MSEL1CR_18_1,
-			MSEL1CR_17_0, MSEL1CR_17_1,
-			MSEL1CR_16_0, MSEL1CR_16_1,
-			MSEL1CR_15_0, MSEL1CR_15_1,
-			MSEL1CR_14_0, MSEL1CR_14_1,
-			MSEL1CR_13_0, MSEL1CR_13_1,
-			MSEL1CR_12_0, MSEL1CR_12_1,
-			MSEL1CR_11_0, MSEL1CR_11_1,
-			MSEL1CR_10_0, MSEL1CR_10_1,
-			MSEL1CR_09_0, MSEL1CR_09_1,
-			MSEL1CR_08_0, MSEL1CR_08_1,
-			MSEL1CR_07_0, MSEL1CR_07_1,
-			MSEL1CR_06_0, MSEL1CR_06_1,
-			MSEL1CR_05_0, MSEL1CR_05_1,
-			MSEL1CR_04_0, MSEL1CR_04_1,
-			MSEL1CR_03_0, MSEL1CR_03_1,
-			MSEL1CR_02_0, MSEL1CR_02_1,
-			MSEL1CR_01_0, MSEL1CR_01_1,
-			MSEL1CR_00_0, MSEL1CR_00_1,
-		))
-	},
-	{ PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1, GROUP(
-			MSEL3CR_31_0, MSEL3CR_31_1,
-			0, 0,
-			0, 0,
-			MSEL3CR_28_0, MSEL3CR_28_1,
-			MSEL3CR_27_0, MSEL3CR_27_1,
-			MSEL3CR_26_0, MSEL3CR_26_1,
-			0, 0,
-			0, 0,
-			MSEL3CR_23_0, MSEL3CR_23_1,
-			MSEL3CR_22_0, MSEL3CR_22_1,
-			MSEL3CR_21_0, MSEL3CR_21_1,
-			MSEL3CR_20_0, MSEL3CR_20_1,
-			MSEL3CR_19_0, MSEL3CR_19_1,
-			MSEL3CR_18_0, MSEL3CR_18_1,
-			MSEL3CR_17_0, MSEL3CR_17_1,
-			MSEL3CR_16_0, MSEL3CR_16_1,
-			MSEL3CR_15_0, MSEL3CR_15_1,
-			0, 0,
-			0, 0,
-			MSEL3CR_12_0, MSEL3CR_12_1,
-			MSEL3CR_11_0, MSEL3CR_11_1,
-			MSEL3CR_10_0, MSEL3CR_10_1,
-			MSEL3CR_09_0, MSEL3CR_09_1,
-			0, 0,
-			0, 0,
-			MSEL3CR_06_0, MSEL3CR_06_1,
-			0, 0,
-			0, 0,
-			MSEL3CR_03_0, MSEL3CR_03_1,
-			0, 0,
-			MSEL3CR_01_0, MSEL3CR_01_1,
-			MSEL3CR_00_0, MSEL3CR_00_1,
-			))
-	},
-	{ PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1, GROUP(
-			0, 0,
-			MSEL4CR_30_0, MSEL4CR_30_1,
-			MSEL4CR_29_0, MSEL4CR_29_1,
-			MSEL4CR_28_0, MSEL4CR_28_1,
-			MSEL4CR_27_0, MSEL4CR_27_1,
-			MSEL4CR_26_0, MSEL4CR_26_1,
-			MSEL4CR_25_0, MSEL4CR_25_1,
-			MSEL4CR_24_0, MSEL4CR_24_1,
-			MSEL4CR_23_0, MSEL4CR_23_1,
-			MSEL4CR_22_0, MSEL4CR_22_1,
-			MSEL4CR_21_0, MSEL4CR_21_1,
-			MSEL4CR_20_0, MSEL4CR_20_1,
-			MSEL4CR_19_0, MSEL4CR_19_1,
-			MSEL4CR_18_0, MSEL4CR_18_1,
-			MSEL4CR_17_0, MSEL4CR_17_1,
-			MSEL4CR_16_0, MSEL4CR_16_1,
-			MSEL4CR_15_0, MSEL4CR_15_1,
-			MSEL4CR_14_0, MSEL4CR_14_1,
-			MSEL4CR_13_0, MSEL4CR_13_1,
-			MSEL4CR_12_0, MSEL4CR_12_1,
-			MSEL4CR_11_0, MSEL4CR_11_1,
-			MSEL4CR_10_0, MSEL4CR_10_1,
-			MSEL4CR_09_0, MSEL4CR_09_1,
-			0, 0,
-			MSEL4CR_07_0, MSEL4CR_07_1,
-			0, 0,
-			0, 0,
-			MSEL4CR_04_0, MSEL4CR_04_1,
-			0, 0,
-			0, 0,
-			MSEL4CR_01_0, MSEL4CR_01_1,
-			0, 0,
-		))
-	},
-	{ PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1, GROUP(
-			MSEL5CR_31_0, MSEL5CR_31_1,
-			MSEL5CR_30_0, MSEL5CR_30_1,
-			MSEL5CR_29_0, MSEL5CR_29_1,
-			MSEL5CR_28_0, MSEL5CR_28_1,
-			MSEL5CR_27_0, MSEL5CR_27_1,
-			MSEL5CR_26_0, MSEL5CR_26_1,
-			MSEL5CR_25_0, MSEL5CR_25_1,
-			MSEL5CR_24_0, MSEL5CR_24_1,
-			MSEL5CR_23_0, MSEL5CR_23_1,
-			MSEL5CR_22_0, MSEL5CR_22_1,
-			MSEL5CR_21_0, MSEL5CR_21_1,
-			MSEL5CR_20_0, MSEL5CR_20_1,
-			MSEL5CR_19_0, MSEL5CR_19_1,
-			MSEL5CR_18_0, MSEL5CR_18_1,
-			MSEL5CR_17_0, MSEL5CR_17_1,
-			MSEL5CR_16_0, MSEL5CR_16_1,
-			MSEL5CR_15_0, MSEL5CR_15_1,
-			MSEL5CR_14_0, MSEL5CR_14_1,
-			MSEL5CR_13_0, MSEL5CR_13_1,
-			MSEL5CR_12_0, MSEL5CR_12_1,
-			MSEL5CR_11_0, MSEL5CR_11_1,
-			MSEL5CR_10_0, MSEL5CR_10_1,
-			MSEL5CR_09_0, MSEL5CR_09_1,
-			MSEL5CR_08_0, MSEL5CR_08_1,
-			MSEL5CR_07_0, MSEL5CR_07_1,
-			MSEL5CR_06_0, MSEL5CR_06_1,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-		))
-	},
-	{ PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1, GROUP(
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			MSEL8CR_16_0, MSEL8CR_16_1,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			MSEL8CR_01_0, MSEL8CR_01_1,
-			MSEL8CR_00_0, MSEL8CR_00_1,
-		))
-	},
-	{ },
-};
-
-static const struct pinmux_data_reg pinmux_data_regs[] = {
-
-	{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32, GROUP(
-			0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
-			PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
-			PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
-			PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
-			PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
-			PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
-			PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
-			PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
-		))
-	},
-	{ PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32, GROUP(
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, 0, 0, PORT40_DATA,
-			PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
-			PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
-		))
-	},
-	{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32, GROUP(
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, 0, PORT85_DATA, PORT84_DATA,
-			PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
-			PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
-			PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
-			PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
-			PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
-		))
-	},
-	{ PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32, GROUP(
-			0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
-			PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
-			PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
-			PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
-			PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
-			PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
-			PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
-			PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
-		))
-	},
-	{ PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32, GROUP(
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
-			PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
-		))
-	},
-	{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32, GROUP(
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, PORT178_DATA, PORT177_DATA, PORT176_DATA,
-			PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
-			PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
-			PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
-			PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
-		))
-	},
-	{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32, GROUP(
-			0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
-			PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
-			PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
-			PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
-			PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
-			PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
-			PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
-			PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
-		))
-	},
-	{ PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32, GROUP(
-			0, 0, 0, 0,
-			0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
-			PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
-			PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
-			PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
-			PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
-			PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
-			PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
-		))
-	},
-	{ PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32, GROUP(
-			0, 0, 0, 0,
-			PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
-			PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
-			PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
-			PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
-			PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
-			PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
-			PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
-		))
-	},
-	{ PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32, GROUP(
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, 0, 0, PORT308_DATA,
-			PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
-			PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
-			PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
-			PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
-			PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
-		))
-	},
-	{ PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32, GROUP(
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, 0, PORT329_DATA, PORT328_DATA,
-			PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
-			PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
-		))
-	},
-	{ },
-};
-
-static const struct pinmux_irq pinmux_irqs[] = {
-	PINMUX_IRQ(0),		/* IRQ0 */
-	PINMUX_IRQ(1),		/* IRQ1 */
-	PINMUX_IRQ(2),		/* IRQ2 */
-	PINMUX_IRQ(3),		/* IRQ3 */
-	PINMUX_IRQ(4),		/* IRQ4 */
-	PINMUX_IRQ(5),		/* IRQ5 */
-	PINMUX_IRQ(6),		/* IRQ6 */
-	PINMUX_IRQ(7),		/* IRQ7 */
-	PINMUX_IRQ(8),		/* IRQ8 */
-	PINMUX_IRQ(9),		/* IRQ9 */
-	PINMUX_IRQ(10),		/* IRQ10 */
-	PINMUX_IRQ(11),		/* IRQ11 */
-	PINMUX_IRQ(12),		/* IRQ12 */
-	PINMUX_IRQ(13),		/* IRQ13 */
-	PINMUX_IRQ(14),		/* IRQ14 */
-	PINMUX_IRQ(15),		/* IRQ15 */
-	PINMUX_IRQ(320),	/* IRQ16 */
-	PINMUX_IRQ(321),	/* IRQ17 */
-	PINMUX_IRQ(85),		/* IRQ18 */
-	PINMUX_IRQ(84),		/* IRQ19 */
-	PINMUX_IRQ(160),	/* IRQ20 */
-	PINMUX_IRQ(161),	/* IRQ21 */
-	PINMUX_IRQ(162),	/* IRQ22 */
-	PINMUX_IRQ(163),	/* IRQ23 */
-	PINMUX_IRQ(175),	/* IRQ24 */
-	PINMUX_IRQ(176),	/* IRQ25 */
-	PINMUX_IRQ(177),	/* IRQ26 */
-	PINMUX_IRQ(178),	/* IRQ27 */
-	PINMUX_IRQ(322),	/* IRQ28 */
-	PINMUX_IRQ(323),	/* IRQ29 */
-	PINMUX_IRQ(324),	/* IRQ30 */
-	PINMUX_IRQ(192),	/* IRQ31 */
-	PINMUX_IRQ(193),	/* IRQ32 */
-	PINMUX_IRQ(194),	/* IRQ33 */
-	PINMUX_IRQ(195),	/* IRQ34 */
-	PINMUX_IRQ(196),	/* IRQ35 */
-	PINMUX_IRQ(197),	/* IRQ36 */
-	PINMUX_IRQ(198),	/* IRQ37 */
-	PINMUX_IRQ(199),	/* IRQ38 */
-	PINMUX_IRQ(200),	/* IRQ39 */
-	PINMUX_IRQ(66),		/* IRQ40 */
-	PINMUX_IRQ(102),	/* IRQ41 */
-	PINMUX_IRQ(103),	/* IRQ42 */
-	PINMUX_IRQ(109),	/* IRQ43 */
-	PINMUX_IRQ(110),	/* IRQ44 */
-	PINMUX_IRQ(111),	/* IRQ45 */
-	PINMUX_IRQ(112),	/* IRQ46 */
-	PINMUX_IRQ(113),	/* IRQ47 */
-	PINMUX_IRQ(114),	/* IRQ48 */
-	PINMUX_IRQ(115),	/* IRQ49 */
-	PINMUX_IRQ(301),	/* IRQ50 */
-	PINMUX_IRQ(290),	/* IRQ51 */
-	PINMUX_IRQ(296),	/* IRQ52 */
-	PINMUX_IRQ(325),	/* IRQ53 */
-	PINMUX_IRQ(326),	/* IRQ54 */
-	PINMUX_IRQ(327),	/* IRQ55 */
-	PINMUX_IRQ(328),	/* IRQ56 */
-	PINMUX_IRQ(329),	/* IRQ57 */
-};
-
-#define PORTCR_PULMD_OFF (0 << 6)
-#define PORTCR_PULMD_DOWN (2 << 6)
-#define PORTCR_PULMD_UP (3 << 6)
-#define PORTCR_PULMD_MASK (3 << 6)
-
-static const unsigned int r8a73a4_portcr_offsets[] = {
-	0x00000000, 0x00001000, 0x00000000, 0x00001000,
-	0x00001000, 0x00002000, 0x00002000, 0x00002000,
-	0x00002000, 0x00003000, 0x00003000,
-};
-
-static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
-					    unsigned int pin)
-{
-	void __iomem *addr;
-
-	addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
-
-	switch (ioread8(addr) & PORTCR_PULMD_MASK) {
-	case PORTCR_PULMD_UP:
-		return PIN_CONFIG_BIAS_PULL_UP;
-	case PORTCR_PULMD_DOWN:
-		return PIN_CONFIG_BIAS_PULL_DOWN;
-	case PORTCR_PULMD_OFF:
-	default:
-		return PIN_CONFIG_BIAS_DISABLE;
-	}
-}
-
-static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
-				   unsigned int bias)
-{
-	void __iomem *addr;
-	u32 value;
-
-	addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
-	value = ioread8(addr) & ~PORTCR_PULMD_MASK;
-
-	switch (bias) {
-	case PIN_CONFIG_BIAS_PULL_UP:
-		value |= PORTCR_PULMD_UP;
-		break;
-	case PIN_CONFIG_BIAS_PULL_DOWN:
-		value |= PORTCR_PULMD_DOWN;
-		break;
-	}
-
-	iowrite8(value, addr);
-}
-
-static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = {
-	.get_bias = r8a73a4_pinmux_get_bias,
-	.set_bias = r8a73a4_pinmux_set_bias,
-};
-
-const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
-	.name		= "r8a73a4_pfc",
-	.ops		= &r8a73a4_pfc_ops,
-
-	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-
-	.groups = pinmux_groups,
-	.nr_groups = ARRAY_SIZE(pinmux_groups),
-	.functions = pinmux_functions,
-	.nr_functions = ARRAY_SIZE(pinmux_functions),
-
-	.cfg_regs = pinmux_config_regs,
-	.data_regs = pinmux_data_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-
-	.gpio_irq = pinmux_irqs,
-	.gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
deleted file mode 100644
index fdf1b0f09f57..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ /dev/null
@@ -1,3769 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * R8A7740 processor support
- *
- * Copyright (C) 2011  Renesas Solutions Corp.
- * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
- */
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/pinctrl/pinconf-generic.h>
-
-#include "sh_pfc.h"
-
-#define CPU_ALL_PORT(fn, pfx, sfx)					\
-	PORT_10(0,  fn, pfx, sfx),	PORT_90(0,   fn, pfx, sfx),	\
-	PORT_10(100, fn, pfx##10, sfx),	PORT_90(100, fn, pfx##1, sfx),	\
-	PORT_10(200, fn, pfx##20, sfx),					\
-	PORT_1(210, fn, pfx##210, sfx),	PORT_1(211, fn, pfx##211, sfx)
-
-#define IRQC_PIN_MUX(irq, pin)						\
-static const unsigned int intc_irq##irq##_pins[] = {			\
-	pin,								\
-};									\
-static const unsigned int intc_irq##irq##_mux[] = {			\
-	IRQ##irq##_MARK,						\
-}
-
-#define IRQC_PINS_MUX(irq, idx, pin)					\
-static const unsigned int intc_irq##irq##_##idx##_pins[] = {		\
-	pin,								\
-};									\
-static const unsigned int intc_irq##irq##_##idx##_mux[] = {		\
-	IRQ##irq##_PORT##pin##_MARK,					\
-}
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	/* PORT0_DATA -> PORT211_DATA */
-	PINMUX_DATA_BEGIN,
-	PORT_ALL(DATA),
-	PINMUX_DATA_END,
-
-	/* PORT0_IN -> PORT211_IN */
-	PINMUX_INPUT_BEGIN,
-	PORT_ALL(IN),
-	PINMUX_INPUT_END,
-
-	/* PORT0_OUT -> PORT211_OUT */
-	PINMUX_OUTPUT_BEGIN,
-	PORT_ALL(OUT),
-	PINMUX_OUTPUT_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	PORT_ALL(FN_IN),	/* PORT0_FN_IN -> PORT211_FN_IN */
-	PORT_ALL(FN_OUT),	/* PORT0_FN_OUT -> PORT211_FN_OUT */
-	PORT_ALL(FN0),		/* PORT0_FN0 -> PORT211_FN0 */
-	PORT_ALL(FN1),		/* PORT0_FN1 -> PORT211_FN1 */
-	PORT_ALL(FN2),		/* PORT0_FN2 -> PORT211_FN2 */
-	PORT_ALL(FN3),		/* PORT0_FN3 -> PORT211_FN3 */
-	PORT_ALL(FN4),		/* PORT0_FN4 -> PORT211_FN4 */
-	PORT_ALL(FN5),		/* PORT0_FN5 -> PORT211_FN5 */
-	PORT_ALL(FN6),		/* PORT0_FN6 -> PORT211_FN6 */
-	PORT_ALL(FN7),		/* PORT0_FN7 -> PORT211_FN7 */
-
-	MSEL1CR_31_0,	MSEL1CR_31_1,
-	MSEL1CR_30_0,	MSEL1CR_30_1,
-	MSEL1CR_29_0,	MSEL1CR_29_1,
-	MSEL1CR_28_0,	MSEL1CR_28_1,
-	MSEL1CR_27_0,	MSEL1CR_27_1,
-	MSEL1CR_26_0,	MSEL1CR_26_1,
-	MSEL1CR_16_0,	MSEL1CR_16_1,
-	MSEL1CR_15_0,	MSEL1CR_15_1,
-	MSEL1CR_14_0,	MSEL1CR_14_1,
-	MSEL1CR_13_0,	MSEL1CR_13_1,
-	MSEL1CR_12_0,	MSEL1CR_12_1,
-	MSEL1CR_9_0,	MSEL1CR_9_1,
-	MSEL1CR_7_0,	MSEL1CR_7_1,
-	MSEL1CR_6_0,	MSEL1CR_6_1,
-	MSEL1CR_5_0,	MSEL1CR_5_1,
-	MSEL1CR_4_0,	MSEL1CR_4_1,
-	MSEL1CR_3_0,	MSEL1CR_3_1,
-	MSEL1CR_2_0,	MSEL1CR_2_1,
-	MSEL1CR_0_0,	MSEL1CR_0_1,
-
-	MSEL3CR_15_0,	MSEL3CR_15_1, /* Trace / Debug ? */
-	MSEL3CR_6_0,	MSEL3CR_6_1,
-
-	MSEL4CR_19_0,	MSEL4CR_19_1,
-	MSEL4CR_18_0,	MSEL4CR_18_1,
-	MSEL4CR_15_0,	MSEL4CR_15_1,
-	MSEL4CR_10_0,	MSEL4CR_10_1,
-	MSEL4CR_6_0,	MSEL4CR_6_1,
-	MSEL4CR_4_0,	MSEL4CR_4_1,
-	MSEL4CR_1_0,	MSEL4CR_1_1,
-
-	MSEL5CR_31_0,	MSEL5CR_31_1, /* irq/fiq output */
-	MSEL5CR_30_0,	MSEL5CR_30_1,
-	MSEL5CR_29_0,	MSEL5CR_29_1,
-	MSEL5CR_27_0,	MSEL5CR_27_1,
-	MSEL5CR_25_0,	MSEL5CR_25_1,
-	MSEL5CR_23_0,	MSEL5CR_23_1,
-	MSEL5CR_21_0,	MSEL5CR_21_1,
-	MSEL5CR_19_0,	MSEL5CR_19_1,
-	MSEL5CR_17_0,	MSEL5CR_17_1,
-	MSEL5CR_15_0,	MSEL5CR_15_1,
-	MSEL5CR_14_0,	MSEL5CR_14_1,
-	MSEL5CR_13_0,	MSEL5CR_13_1,
-	MSEL5CR_12_0,	MSEL5CR_12_1,
-	MSEL5CR_11_0,	MSEL5CR_11_1,
-	MSEL5CR_10_0,	MSEL5CR_10_1,
-	MSEL5CR_8_0,	MSEL5CR_8_1,
-	MSEL5CR_7_0,	MSEL5CR_7_1,
-	MSEL5CR_6_0,	MSEL5CR_6_1,
-	MSEL5CR_5_0,	MSEL5CR_5_1,
-	MSEL5CR_4_0,	MSEL5CR_4_1,
-	MSEL5CR_3_0,	MSEL5CR_3_1,
-	MSEL5CR_2_0,	MSEL5CR_2_1,
-	MSEL5CR_0_0,	MSEL5CR_0_1,
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-
-	/* IRQ */
-	IRQ0_PORT2_MARK,	IRQ0_PORT13_MARK,
-	IRQ1_MARK,
-	IRQ2_PORT11_MARK,	IRQ2_PORT12_MARK,
-	IRQ3_PORT10_MARK,	IRQ3_PORT14_MARK,
-	IRQ4_PORT15_MARK,	IRQ4_PORT172_MARK,
-	IRQ5_PORT0_MARK,	IRQ5_PORT1_MARK,
-	IRQ6_PORT121_MARK,	IRQ6_PORT173_MARK,
-	IRQ7_PORT120_MARK,	IRQ7_PORT209_MARK,
-	IRQ8_MARK,
-	IRQ9_PORT118_MARK,	IRQ9_PORT210_MARK,
-	IRQ10_MARK,
-	IRQ11_MARK,
-	IRQ12_PORT42_MARK,	IRQ12_PORT97_MARK,
-	IRQ13_PORT64_MARK,	IRQ13_PORT98_MARK,
-	IRQ14_PORT63_MARK,	IRQ14_PORT99_MARK,
-	IRQ15_PORT62_MARK,	IRQ15_PORT100_MARK,
-	IRQ16_PORT68_MARK,	IRQ16_PORT211_MARK,
-	IRQ17_MARK,
-	IRQ18_MARK,
-	IRQ19_MARK,
-	IRQ20_MARK,
-	IRQ21_MARK,
-	IRQ22_MARK,
-	IRQ23_MARK,
-	IRQ24_MARK,
-	IRQ25_MARK,
-	IRQ26_PORT58_MARK,	IRQ26_PORT81_MARK,
-	IRQ27_PORT57_MARK,	IRQ27_PORT168_MARK,
-	IRQ28_PORT56_MARK,	IRQ28_PORT169_MARK,
-	IRQ29_PORT50_MARK,	IRQ29_PORT170_MARK,
-	IRQ30_PORT49_MARK,	IRQ30_PORT171_MARK,
-	IRQ31_PORT41_MARK,	IRQ31_PORT167_MARK,
-
-	/* Function */
-
-	/* DBGT */
-	DBGMDT2_MARK,	DBGMDT1_MARK,	DBGMDT0_MARK,
-	DBGMD10_MARK,	DBGMD11_MARK,	DBGMD20_MARK,
-	DBGMD21_MARK,
-
-	/* FSI-A */
-	FSIAISLD_PORT0_MARK,	/* FSIAISLD Port 0/5 */
-	FSIAISLD_PORT5_MARK,
-	FSIASPDIF_PORT9_MARK,	/* FSIASPDIF Port 9/18 */
-	FSIASPDIF_PORT18_MARK,
-	FSIAOSLD1_MARK,	FSIAOSLD2_MARK,	FSIAOLR_MARK,
-	FSIAOBT_MARK,	FSIAOSLD_MARK,	FSIAOMC_MARK,
-	FSIACK_MARK,	FSIAILR_MARK,	FSIAIBT_MARK,
-
-	/* FSI-B */
-	FSIBCK_MARK,
-
-	/* FMSI */
-	FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
-	FMSISLD_PORT6_MARK,
-	FMSIILR_MARK,	FMSIIBT_MARK,	FMSIOLR_MARK,	FMSIOBT_MARK,
-	FMSICK_MARK,	FMSOILR_MARK,	FMSOIBT_MARK,	FMSOOLR_MARK,
-	FMSOOBT_MARK,	FMSOSLD_MARK,	FMSOCK_MARK,
-
-	/* SCIFA0 */
-	SCIFA0_SCK_MARK,	SCIFA0_CTS_MARK,	SCIFA0_RTS_MARK,
-	SCIFA0_RXD_MARK,	SCIFA0_TXD_MARK,
-
-	/* SCIFA1 */
-	SCIFA1_CTS_MARK,	SCIFA1_SCK_MARK,	SCIFA1_RXD_MARK,
-	SCIFA1_TXD_MARK,	SCIFA1_RTS_MARK,
-
-	/* SCIFA2 */
-	SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
-	SCIFA2_SCK_PORT199_MARK,
-	SCIFA2_RXD_MARK,	SCIFA2_TXD_MARK,
-	SCIFA2_CTS_MARK,	SCIFA2_RTS_MARK,
-
-	/* SCIFA3 */
-	SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
-	SCIFA3_SCK_PORT116_MARK,
-	SCIFA3_CTS_PORT117_MARK,
-	SCIFA3_RXD_PORT174_MARK,
-	SCIFA3_TXD_PORT175_MARK,
-
-	SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
-	SCIFA3_SCK_PORT158_MARK,
-	SCIFA3_CTS_PORT162_MARK,
-	SCIFA3_RXD_PORT159_MARK,
-	SCIFA3_TXD_PORT160_MARK,
-
-	/* SCIFA4 */
-	SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
-	SCIFA4_TXD_PORT13_MARK,
-
-	SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
-	SCIFA4_TXD_PORT203_MARK,
-
-	SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
-	SCIFA4_TXD_PORT93_MARK,
-
-	SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
-	SCIFA4_SCK_PORT205_MARK,
-
-	/* SCIFA5 */
-	SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
-	SCIFA5_RXD_PORT10_MARK,
-
-	SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
-	SCIFA5_TXD_PORT208_MARK,
-
-	SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
-	SCIFA5_RXD_PORT92_MARK,
-
-	SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
-	SCIFA5_SCK_PORT206_MARK,
-
-	/* SCIFA6 */
-	SCIFA6_SCK_MARK,	SCIFA6_RXD_MARK,	SCIFA6_TXD_MARK,
-
-	/* SCIFA7 */
-	SCIFA7_TXD_MARK,	SCIFA7_RXD_MARK,
-
-	/* SCIFB */
-	SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
-	SCIFB_RXD_PORT191_MARK,
-	SCIFB_TXD_PORT192_MARK,
-	SCIFB_RTS_PORT186_MARK,
-	SCIFB_CTS_PORT187_MARK,
-
-	SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
-	SCIFB_RXD_PORT3_MARK,
-	SCIFB_TXD_PORT4_MARK,
-	SCIFB_RTS_PORT172_MARK,
-	SCIFB_CTS_PORT173_MARK,
-
-	/* LCD0 */
-	LCD0_D0_MARK,	LCD0_D1_MARK,	LCD0_D2_MARK,	LCD0_D3_MARK,
-	LCD0_D4_MARK,	LCD0_D5_MARK,	LCD0_D6_MARK,	LCD0_D7_MARK,
-	LCD0_D8_MARK,	LCD0_D9_MARK,	LCD0_D10_MARK,	LCD0_D11_MARK,
-	LCD0_D12_MARK,	LCD0_D13_MARK,	LCD0_D14_MARK,	LCD0_D15_MARK,
-	LCD0_D16_MARK,	LCD0_D17_MARK,
-	LCD0_DON_MARK,	LCD0_VCPWC_MARK,	LCD0_VEPWC_MARK,
-	LCD0_DCK_MARK,	LCD0_VSYN_MARK,	/* for RGB */
-	LCD0_HSYN_MARK,	LCD0_DISP_MARK,	/* for RGB */
-	LCD0_WR_MARK,	LCD0_RD_MARK,	/* for SYS */
-	LCD0_CS_MARK,	LCD0_RS_MARK,	/* for SYS */
-
-	LCD0_D21_PORT158_MARK,	LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
-	LCD0_D22_PORT160_MARK,	LCD0_D20_PORT161_MARK,
-	LCD0_D19_PORT162_MARK,	LCD0_D18_PORT163_MARK,
-	LCD0_LCLK_PORT165_MARK,
-
-	LCD0_D18_PORT40_MARK,	LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
-	LCD0_D23_PORT1_MARK,	LCD0_D21_PORT2_MARK,
-	LCD0_D20_PORT3_MARK,	LCD0_D19_PORT4_MARK,
-	LCD0_LCLK_PORT102_MARK,
-
-	/* LCD1 */
-	LCD1_D0_MARK,	LCD1_D1_MARK,	LCD1_D2_MARK,	LCD1_D3_MARK,
-	LCD1_D4_MARK,	LCD1_D5_MARK,	LCD1_D6_MARK,	LCD1_D7_MARK,
-	LCD1_D8_MARK,	LCD1_D9_MARK,	LCD1_D10_MARK,	LCD1_D11_MARK,
-	LCD1_D12_MARK,	LCD1_D13_MARK,	LCD1_D14_MARK,	LCD1_D15_MARK,
-	LCD1_D16_MARK,	LCD1_D17_MARK,	LCD1_D18_MARK,	LCD1_D19_MARK,
-	LCD1_D20_MARK,	LCD1_D21_MARK,	LCD1_D22_MARK,	LCD1_D23_MARK,
-	LCD1_DON_MARK,	LCD1_VCPWC_MARK,
-	LCD1_LCLK_MARK,	LCD1_VEPWC_MARK,
-
-	LCD1_DCK_MARK,	LCD1_VSYN_MARK,	/* for RGB */
-	LCD1_HSYN_MARK,	LCD1_DISP_MARK,	/* for RGB */
-	LCD1_RS_MARK,	LCD1_CS_MARK,	/* for SYS */
-	LCD1_RD_MARK,	LCD1_WR_MARK,	/* for SYS */
-
-	/* RSPI */
-	RSPI_SSL0_A_MARK,	RSPI_SSL1_A_MARK,	RSPI_SSL2_A_MARK,
-	RSPI_SSL3_A_MARK,	RSPI_CK_A_MARK,		RSPI_MOSI_A_MARK,
-	RSPI_MISO_A_MARK,
-
-	/* VIO CKO */
-	VIO_CKO1_MARK, /* needs fixup */
-	VIO_CKO2_MARK,
-	VIO_CKO_1_MARK,
-	VIO_CKO_MARK,
-
-	/* VIO0 */
-	VIO0_D0_MARK,	VIO0_D1_MARK,	VIO0_D2_MARK,	VIO0_D3_MARK,
-	VIO0_D4_MARK,	VIO0_D5_MARK,	VIO0_D6_MARK,	VIO0_D7_MARK,
-	VIO0_D8_MARK,	VIO0_D9_MARK,	VIO0_D10_MARK,	VIO0_D11_MARK,
-	VIO0_D12_MARK,	VIO0_VD_MARK,	VIO0_HD_MARK,	VIO0_CLK_MARK,
-	VIO0_FIELD_MARK,
-
-	VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
-	VIO0_D14_PORT25_MARK,
-	VIO0_D15_PORT24_MARK,
-
-	VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
-	VIO0_D14_PORT95_MARK,
-	VIO0_D15_PORT96_MARK,
-
-	/* VIO1 */
-	VIO1_D0_MARK,	VIO1_D1_MARK,	VIO1_D2_MARK,	VIO1_D3_MARK,
-	VIO1_D4_MARK,	VIO1_D5_MARK,	VIO1_D6_MARK,	VIO1_D7_MARK,
-	VIO1_VD_MARK,	VIO1_HD_MARK,	VIO1_CLK_MARK,	VIO1_FIELD_MARK,
-
-	/* TPU0 */
-	TPU0TO0_MARK,	TPU0TO1_MARK,	TPU0TO3_MARK,
-	TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
-	TPU0TO2_PORT202_MARK,
-
-	/* SSP1 0 */
-	STP0_IPD0_MARK,	STP0_IPD1_MARK,	STP0_IPD2_MARK,	STP0_IPD3_MARK,
-	STP0_IPD4_MARK,	STP0_IPD5_MARK,	STP0_IPD6_MARK,	STP0_IPD7_MARK,
-	STP0_IPEN_MARK,	STP0_IPCLK_MARK,	STP0_IPSYNC_MARK,
-
-	/* SSP1 1 */
-	STP1_IPD1_MARK,	STP1_IPD2_MARK,	STP1_IPD3_MARK,	STP1_IPD4_MARK,
-	STP1_IPD5_MARK,	STP1_IPD6_MARK,	STP1_IPD7_MARK,	STP1_IPCLK_MARK,
-	STP1_IPSYNC_MARK,
-
-	STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
-	STP1_IPEN_PORT187_MARK,
-
-	STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
-	STP1_IPEN_PORT193_MARK,
-
-	/* SIM */
-	SIM_RST_MARK,	SIM_CLK_MARK,
-	SIM_D_PORT22_MARK, /* SIM_D  Port 22/199 */
-	SIM_D_PORT199_MARK,
-
-	/* SDHI0 */
-	SDHI0_D0_MARK,	SDHI0_D1_MARK,	SDHI0_D2_MARK,	SDHI0_D3_MARK,
-	SDHI0_CD_MARK,	SDHI0_WP_MARK,	SDHI0_CMD_MARK,	SDHI0_CLK_MARK,
-
-	/* SDHI1 */
-	SDHI1_D0_MARK,	SDHI1_D1_MARK,	SDHI1_D2_MARK,	SDHI1_D3_MARK,
-	SDHI1_CD_MARK,	SDHI1_WP_MARK,	SDHI1_CMD_MARK,	SDHI1_CLK_MARK,
-
-	/* SDHI2 */
-	SDHI2_D0_MARK,	SDHI2_D1_MARK,	SDHI2_D2_MARK,	SDHI2_D3_MARK,
-	SDHI2_CLK_MARK,	SDHI2_CMD_MARK,
-
-	SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
-	SDHI2_WP_PORT25_MARK,
-
-	SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
-	SDHI2_CD_PORT202_MARK,
-
-	/* MSIOF2 */
-	MSIOF2_TXD_MARK,	MSIOF2_RXD_MARK,	MSIOF2_TSCK_MARK,
-	MSIOF2_SS2_MARK,	MSIOF2_TSYNC_MARK,	MSIOF2_SS1_MARK,
-	MSIOF2_MCK1_MARK,	MSIOF2_MCK0_MARK,	MSIOF2_RSYNC_MARK,
-	MSIOF2_RSCK_MARK,
-
-	/* KEYSC */
-	KEYIN4_MARK,	KEYIN5_MARK,	KEYIN6_MARK,	KEYIN7_MARK,
-	KEYOUT0_MARK,	KEYOUT1_MARK,	KEYOUT2_MARK,	KEYOUT3_MARK,
-	KEYOUT4_MARK,	KEYOUT5_MARK,	KEYOUT6_MARK,	KEYOUT7_MARK,
-
-	KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
-	KEYIN1_PORT44_MARK,
-	KEYIN2_PORT45_MARK,
-	KEYIN3_PORT46_MARK,
-
-	KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
-	KEYIN1_PORT57_MARK,
-	KEYIN2_PORT56_MARK,
-	KEYIN3_PORT55_MARK,
-
-	/* VOU */
-	DV_D0_MARK,	DV_D1_MARK,	DV_D2_MARK,	DV_D3_MARK,
-	DV_D4_MARK,	DV_D5_MARK,	DV_D6_MARK,	DV_D7_MARK,
-	DV_D8_MARK,	DV_D9_MARK,	DV_D10_MARK,	DV_D11_MARK,
-	DV_D12_MARK,	DV_D13_MARK,	DV_D14_MARK,	DV_D15_MARK,
-	DV_CLK_MARK,	DV_VSYNC_MARK,	DV_HSYNC_MARK,
-
-	/* MEMC */
-	MEMC_AD0_MARK,	MEMC_AD1_MARK,	MEMC_AD2_MARK,	MEMC_AD3_MARK,
-	MEMC_AD4_MARK,	MEMC_AD5_MARK,	MEMC_AD6_MARK,	MEMC_AD7_MARK,
-	MEMC_AD8_MARK,	MEMC_AD9_MARK,	MEMC_AD10_MARK,	MEMC_AD11_MARK,
-	MEMC_AD12_MARK,	MEMC_AD13_MARK,	MEMC_AD14_MARK,	MEMC_AD15_MARK,
-	MEMC_CS0_MARK,	MEMC_INT_MARK,	MEMC_NWE_MARK,	MEMC_NOE_MARK,
-
-	MEMC_CS1_MARK, /* MSEL4CR_6_0 */
-	MEMC_ADV_MARK,
-	MEMC_WAIT_MARK,
-	MEMC_BUSCLK_MARK,
-
-	MEMC_A1_MARK, /* MSEL4CR_6_1 */
-	MEMC_DREQ0_MARK,
-	MEMC_DREQ1_MARK,
-	MEMC_A0_MARK,
-
-	/* MMC */
-	MMC0_D0_PORT68_MARK,	MMC0_D1_PORT69_MARK,	MMC0_D2_PORT70_MARK,
-	MMC0_D3_PORT71_MARK,	MMC0_D4_PORT72_MARK,	MMC0_D5_PORT73_MARK,
-	MMC0_D6_PORT74_MARK,	MMC0_D7_PORT75_MARK,	MMC0_CLK_PORT66_MARK,
-	MMC0_CMD_PORT67_MARK,	/* MSEL4CR_15_0 */
-
-	MMC1_D0_PORT149_MARK,	MMC1_D1_PORT148_MARK,	MMC1_D2_PORT147_MARK,
-	MMC1_D3_PORT146_MARK,	MMC1_D4_PORT145_MARK,	MMC1_D5_PORT144_MARK,
-	MMC1_D6_PORT143_MARK,	MMC1_D7_PORT142_MARK,	MMC1_CLK_PORT103_MARK,
-	MMC1_CMD_PORT104_MARK,	/* MSEL4CR_15_1 */
-
-	/* MSIOF0 */
-	MSIOF0_SS1_MARK,	MSIOF0_SS2_MARK,	MSIOF0_RXD_MARK,
-	MSIOF0_TXD_MARK,	MSIOF0_MCK0_MARK,	MSIOF0_MCK1_MARK,
-	MSIOF0_RSYNC_MARK,	MSIOF0_RSCK_MARK,	MSIOF0_TSCK_MARK,
-	MSIOF0_TSYNC_MARK,
-
-	/* MSIOF1 */
-	MSIOF1_RSCK_MARK,	MSIOF1_RSYNC_MARK,
-	MSIOF1_MCK0_MARK,	MSIOF1_MCK1_MARK,
-
-	MSIOF1_SS2_PORT116_MARK,	MSIOF1_SS1_PORT117_MARK,
-	MSIOF1_RXD_PORT118_MARK,	MSIOF1_TXD_PORT119_MARK,
-	MSIOF1_TSYNC_PORT120_MARK,
-	MSIOF1_TSCK_PORT121_MARK,	/* MSEL4CR_10_0 */
-
-	MSIOF1_SS1_PORT67_MARK,		MSIOF1_TSCK_PORT72_MARK,
-	MSIOF1_TSYNC_PORT73_MARK,	MSIOF1_TXD_PORT74_MARK,
-	MSIOF1_RXD_PORT75_MARK,
-	MSIOF1_SS2_PORT202_MARK,	/* MSEL4CR_10_1 */
-
-	/* GPIO */
-	GPO0_MARK,	GPI0_MARK,	GPO1_MARK,	GPI1_MARK,
-
-	/* USB0 */
-	USB0_OCI_MARK,	USB0_PPON_MARK,	VBUS_MARK,
-
-	/* USB1 */
-	USB1_OCI_MARK,	USB1_PPON_MARK,
-
-	/* BBIF1 */
-	BBIF1_RXD_MARK,		BBIF1_TXD_MARK,		BBIF1_TSYNC_MARK,
-	BBIF1_TSCK_MARK,	BBIF1_RSCK_MARK,	BBIF1_RSYNC_MARK,
-	BBIF1_FLOW_MARK,	BBIF1_RX_FLOW_N_MARK,
-
-	/* BBIF2 */
-	BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
-	BBIF2_RXD2_PORT60_MARK,
-	BBIF2_TSYNC2_PORT6_MARK,
-	BBIF2_TSCK2_PORT59_MARK,
-
-	BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
-	BBIF2_TXD2_PORT183_MARK,
-	BBIF2_TSCK2_PORT89_MARK,
-	BBIF2_TSYNC2_PORT184_MARK,
-
-	/* BSC / FLCTL / PCMCIA */
-	CS0_MARK,	CS2_MARK,	CS4_MARK,
-	CS5B_MARK,	CS6A_MARK,
-	CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
-	CS5A_PORT19_MARK,
-	IOIS16_MARK, /* ? */
-
-	A0_MARK,	A1_MARK,	A2_MARK,	A3_MARK,
-	A4_FOE_MARK,	/* share with FLCTL */
-	A5_FCDE_MARK,	/* share with FLCTL */
-	A6_MARK,	A7_MARK,	A8_MARK,	A9_MARK,
-	A10_MARK,	A11_MARK,	A12_MARK,	A13_MARK,
-	A14_MARK,	A15_MARK,	A16_MARK,	A17_MARK,
-	A18_MARK,	A19_MARK,	A20_MARK,	A21_MARK,
-	A22_MARK,	A23_MARK,	A24_MARK,	A25_MARK,
-	A26_MARK,
-
-	D0_NAF0_MARK,	D1_NAF1_MARK,	D2_NAF2_MARK,	/* share with FLCTL */
-	D3_NAF3_MARK,	D4_NAF4_MARK,	D5_NAF5_MARK,	/* share with FLCTL */
-	D6_NAF6_MARK,	D7_NAF7_MARK,	D8_NAF8_MARK,	/* share with FLCTL */
-	D9_NAF9_MARK,	D10_NAF10_MARK,	D11_NAF11_MARK,	/* share with FLCTL */
-	D12_NAF12_MARK,	D13_NAF13_MARK,	D14_NAF14_MARK,	/* share with FLCTL */
-	D15_NAF15_MARK,					/* share with FLCTL */
-	D16_MARK,	D17_MARK,	D18_MARK,	D19_MARK,
-	D20_MARK,	D21_MARK,	D22_MARK,	D23_MARK,
-	D24_MARK,	D25_MARK,	D26_MARK,	D27_MARK,
-	D28_MARK,	D29_MARK,	D30_MARK,	D31_MARK,
-
-	WE0_FWE_MARK,	/* share with FLCTL */
-	WE1_MARK,
-	WE2_ICIORD_MARK,	/* share with PCMCIA */
-	WE3_ICIOWR_MARK,	/* share with PCMCIA */
-	CKO_MARK,	BS_MARK,	RDWR_MARK,
-	RD_FSC_MARK,	/* share with FLCTL */
-	WAIT_PORT177_MARK, /* WAIT Port 90/177 */
-	WAIT_PORT90_MARK,
-
-	FCE0_MARK,	FCE1_MARK,	FRB_MARK, /* FLCTL */
-
-	/* IRDA */
-	IRDA_FIRSEL_MARK,	IRDA_IN_MARK,	IRDA_OUT_MARK,
-
-	/* ATAPI */
-	IDE_D0_MARK,	IDE_D1_MARK,	IDE_D2_MARK,	IDE_D3_MARK,
-	IDE_D4_MARK,	IDE_D5_MARK,	IDE_D6_MARK,	IDE_D7_MARK,
-	IDE_D8_MARK,	IDE_D9_MARK,	IDE_D10_MARK,	IDE_D11_MARK,
-	IDE_D12_MARK,	IDE_D13_MARK,	IDE_D14_MARK,	IDE_D15_MARK,
-	IDE_A0_MARK,	IDE_A1_MARK,	IDE_A2_MARK,	IDE_CS0_MARK,
-	IDE_CS1_MARK,	IDE_IOWR_MARK,	IDE_IORD_MARK,	IDE_IORDY_MARK,
-	IDE_INT_MARK,		IDE_RST_MARK,		IDE_DIRECTION_MARK,
-	IDE_EXBUF_ENB_MARK,	IDE_IODACK_MARK,	IDE_IODREQ_MARK,
-
-	/* RMII */
-	RMII_CRS_DV_MARK,	RMII_RX_ER_MARK,	RMII_RXD0_MARK,
-	RMII_RXD1_MARK,		RMII_TX_EN_MARK,	RMII_TXD0_MARK,
-	RMII_MDC_MARK,		RMII_TXD1_MARK,		RMII_MDIO_MARK,
-	RMII_REF50CK_MARK,	/* for RMII */
-	RMII_REF125CK_MARK,	/* for GMII */
-
-	/* GEther */
-	ET_TX_CLK_MARK,	ET_TX_EN_MARK,	ET_ETXD0_MARK,	ET_ETXD1_MARK,
-	ET_ETXD2_MARK,	ET_ETXD3_MARK,
-	ET_ETXD4_MARK,	ET_ETXD5_MARK, /* for GEther */
-	ET_ETXD6_MARK,	ET_ETXD7_MARK, /* for GEther */
-	ET_COL_MARK,	ET_TX_ER_MARK,	ET_RX_CLK_MARK,	ET_RX_DV_MARK,
-	ET_ERXD0_MARK,	ET_ERXD1_MARK,	ET_ERXD2_MARK,	ET_ERXD3_MARK,
-	ET_ERXD4_MARK,	ET_ERXD5_MARK, /* for GEther */
-	ET_ERXD6_MARK,	ET_ERXD7_MARK, /* for GEther */
-	ET_RX_ER_MARK,	ET_CRS_MARK,		ET_MDC_MARK,	ET_MDIO_MARK,
-	ET_LINK_MARK,	ET_PHY_INT_MARK,	ET_WOL_MARK,	ET_GTX_CLK_MARK,
-
-	/* DMA0 */
-	DREQ0_MARK,	DACK0_MARK,
-
-	/* DMA1 */
-	DREQ1_MARK,	DACK1_MARK,
-
-	/* SYSC */
-	RESETOUTS_MARK,		RESETP_PULLUP_MARK,	RESETP_PLAIN_MARK,
-
-	/* IRREM */
-	IROUT_MARK,
-
-	/* SDENC */
-	SDENC_CPG_MARK,		SDENC_DV_CLKI_MARK,
-
-	/* HDMI */
-	HDMI_HPD_MARK, HDMI_CEC_MARK,
-
-	/* DEBUG */
-	EDEBGREQ_PULLUP_MARK,	/* for JTAG */
-	EDEBGREQ_PULLDOWN_MARK,
-
-	TRACEAUD_FROM_VIO_MARK,	/* for TRACE/AUD */
-	TRACEAUD_FROM_LCDC0_MARK,
-	TRACEAUD_FROM_MEMC_MARK,
-
-	PINMUX_MARK_END,
-};
-
-static const u16 pinmux_data[] = {
-	PINMUX_DATA_ALL(),
-
-	/* Port0 */
-	PINMUX_DATA(DBGMDT2_MARK,		PORT0_FN1),
-	PINMUX_DATA(FSIAISLD_PORT0_MARK,	PORT0_FN2,	MSEL5CR_3_0),
-	PINMUX_DATA(FSIAOSLD1_MARK,		PORT0_FN3),
-	PINMUX_DATA(LCD0_D22_PORT0_MARK,	PORT0_FN4,	MSEL5CR_6_0),
-	PINMUX_DATA(SCIFA7_RXD_MARK,		PORT0_FN6),
-	PINMUX_DATA(LCD1_D4_MARK,		PORT0_FN7),
-	PINMUX_DATA(IRQ5_PORT0_MARK,		PORT0_FN0,	MSEL1CR_5_0),
-
-	/* Port1 */
-	PINMUX_DATA(DBGMDT1_MARK,		PORT1_FN1),
-	PINMUX_DATA(FMSISLD_PORT1_MARK,		PORT1_FN2,	MSEL5CR_5_0),
-	PINMUX_DATA(FSIAOSLD2_MARK,		PORT1_FN3),
-	PINMUX_DATA(LCD0_D23_PORT1_MARK,	PORT1_FN4,	MSEL5CR_6_0),
-	PINMUX_DATA(SCIFA7_TXD_MARK,		PORT1_FN6),
-	PINMUX_DATA(LCD1_D3_MARK,		PORT1_FN7),
-	PINMUX_DATA(IRQ5_PORT1_MARK,		PORT1_FN0,	MSEL1CR_5_1),
-
-	/* Port2 */
-	PINMUX_DATA(DBGMDT0_MARK,		PORT2_FN1),
-	PINMUX_DATA(SCIFB_SCK_PORT2_MARK,	PORT2_FN2,	MSEL5CR_17_1),
-	PINMUX_DATA(LCD0_D21_PORT2_MARK,	PORT2_FN4,	MSEL5CR_6_0),
-	PINMUX_DATA(LCD1_D2_MARK,		PORT2_FN7),
-	PINMUX_DATA(IRQ0_PORT2_MARK,		PORT2_FN0,	MSEL1CR_0_1),
-
-	/* Port3 */
-	PINMUX_DATA(DBGMD21_MARK,		PORT3_FN1),
-	PINMUX_DATA(SCIFB_RXD_PORT3_MARK,	PORT3_FN2,	MSEL5CR_17_1),
-	PINMUX_DATA(LCD0_D20_PORT3_MARK,	PORT3_FN4,	MSEL5CR_6_0),
-	PINMUX_DATA(LCD1_D1_MARK,		PORT3_FN7),
-
-	/* Port4 */
-	PINMUX_DATA(DBGMD20_MARK,		PORT4_FN1),
-	PINMUX_DATA(SCIFB_TXD_PORT4_MARK,	PORT4_FN2,	MSEL5CR_17_1),
-	PINMUX_DATA(LCD0_D19_PORT4_MARK,	PORT4_FN4,	MSEL5CR_6_0),
-	PINMUX_DATA(LCD1_D0_MARK,		PORT4_FN7),
-
-	/* Port5 */
-	PINMUX_DATA(DBGMD11_MARK,		PORT5_FN1),
-	PINMUX_DATA(BBIF2_TXD2_PORT5_MARK,	PORT5_FN2,	MSEL5CR_0_0),
-	PINMUX_DATA(FSIAISLD_PORT5_MARK,	PORT5_FN4,	MSEL5CR_3_1),
-	PINMUX_DATA(RSPI_SSL0_A_MARK,		PORT5_FN6),
-	PINMUX_DATA(LCD1_VCPWC_MARK,		PORT5_FN7),
-
-	/* Port6 */
-	PINMUX_DATA(DBGMD10_MARK,		PORT6_FN1),
-	PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK,	PORT6_FN2,	MSEL5CR_0_0),
-	PINMUX_DATA(FMSISLD_PORT6_MARK,		PORT6_FN4,	MSEL5CR_5_1),
-	PINMUX_DATA(RSPI_SSL1_A_MARK,		PORT6_FN6),
-	PINMUX_DATA(LCD1_VEPWC_MARK,		PORT6_FN7),
-
-	/* Port7 */
-	PINMUX_DATA(FSIAOLR_MARK,		PORT7_FN1),
-
-	/* Port8 */
-	PINMUX_DATA(FSIAOBT_MARK,		PORT8_FN1),
-
-	/* Port9 */
-	PINMUX_DATA(FSIAOSLD_MARK,		PORT9_FN1),
-	PINMUX_DATA(FSIASPDIF_PORT9_MARK,	PORT9_FN2,	MSEL5CR_4_0),
-
-	/* Port10 */
-	PINMUX_DATA(FSIAOMC_MARK,		PORT10_FN1),
-	PINMUX_DATA(SCIFA5_RXD_PORT10_MARK,	PORT10_FN3,	MSEL5CR_14_0,	MSEL5CR_15_0),
-	PINMUX_DATA(IRQ3_PORT10_MARK,		PORT10_FN0,	MSEL1CR_3_0),
-
-	/* Port11 */
-	PINMUX_DATA(FSIACK_MARK,		PORT11_FN1),
-	PINMUX_DATA(FSIBCK_MARK,		PORT11_FN2),
-	PINMUX_DATA(IRQ2_PORT11_MARK,		PORT11_FN0,	MSEL1CR_2_0),
-
-	/* Port12 */
-	PINMUX_DATA(FSIAILR_MARK,		PORT12_FN1),
-	PINMUX_DATA(SCIFA4_RXD_PORT12_MARK,	PORT12_FN2,	MSEL5CR_12_0,	MSEL5CR_11_0),
-	PINMUX_DATA(LCD1_RS_MARK,		PORT12_FN6),
-	PINMUX_DATA(LCD1_DISP_MARK,		PORT12_FN7),
-	PINMUX_DATA(IRQ2_PORT12_MARK,		PORT12_FN0,	MSEL1CR_2_1),
-
-	/* Port13 */
-	PINMUX_DATA(FSIAIBT_MARK,		PORT13_FN1),
-	PINMUX_DATA(SCIFA4_TXD_PORT13_MARK,	PORT13_FN2,	MSEL5CR_12_0,	MSEL5CR_11_0),
-	PINMUX_DATA(LCD1_RD_MARK,		PORT13_FN7),
-	PINMUX_DATA(IRQ0_PORT13_MARK,		PORT13_FN0,	MSEL1CR_0_0),
-
-	/* Port14 */
-	PINMUX_DATA(FMSOILR_MARK,		PORT14_FN1),
-	PINMUX_DATA(FMSIILR_MARK,		PORT14_FN2),
-	PINMUX_DATA(VIO_CKO1_MARK,		PORT14_FN3),
-	PINMUX_DATA(LCD1_D23_MARK,		PORT14_FN7),
-	PINMUX_DATA(IRQ3_PORT14_MARK,		PORT14_FN0,	MSEL1CR_3_1),
-
-	/* Port15 */
-	PINMUX_DATA(FMSOIBT_MARK,		PORT15_FN1),
-	PINMUX_DATA(FMSIIBT_MARK,		PORT15_FN2),
-	PINMUX_DATA(VIO_CKO2_MARK,		PORT15_FN3),
-	PINMUX_DATA(LCD1_D22_MARK,		PORT15_FN7),
-	PINMUX_DATA(IRQ4_PORT15_MARK,		PORT15_FN0,	MSEL1CR_4_0),
-
-	/* Port16 */
-	PINMUX_DATA(FMSOOLR_MARK,		PORT16_FN1),
-	PINMUX_DATA(FMSIOLR_MARK,		PORT16_FN2),
-
-	/* Port17 */
-	PINMUX_DATA(FMSOOBT_MARK,		PORT17_FN1),
-	PINMUX_DATA(FMSIOBT_MARK,		PORT17_FN2),
-
-	/* Port18 */
-	PINMUX_DATA(FMSOSLD_MARK,		PORT18_FN1),
-	PINMUX_DATA(FSIASPDIF_PORT18_MARK,	PORT18_FN2,	MSEL5CR_4_1),
-
-	/* Port19 */
-	PINMUX_DATA(FMSICK_MARK,		PORT19_FN1),
-	PINMUX_DATA(CS5A_PORT19_MARK,		PORT19_FN7,	MSEL5CR_2_1),
-	PINMUX_DATA(IRQ10_MARK,			PORT19_FN0),
-
-	/* Port20 */
-	PINMUX_DATA(FMSOCK_MARK,		PORT20_FN1),
-	PINMUX_DATA(SCIFA5_TXD_PORT20_MARK,	PORT20_FN3,	MSEL5CR_15_0,	MSEL5CR_14_0),
-	PINMUX_DATA(IRQ1_MARK,			PORT20_FN0),
-
-	/* Port21 */
-	PINMUX_DATA(SCIFA1_CTS_MARK,		PORT21_FN1),
-	PINMUX_DATA(SCIFA4_SCK_PORT21_MARK,	PORT21_FN2,	MSEL5CR_10_0),
-	PINMUX_DATA(TPU0TO1_MARK,		PORT21_FN4),
-	PINMUX_DATA(VIO1_FIELD_MARK,		PORT21_FN5),
-	PINMUX_DATA(STP0_IPD5_MARK,		PORT21_FN6),
-	PINMUX_DATA(LCD1_D10_MARK,		PORT21_FN7),
-
-	/* Port22 */
-	PINMUX_DATA(SCIFA2_SCK_PORT22_MARK,	PORT22_FN1,	MSEL5CR_7_0),
-	PINMUX_DATA(SIM_D_PORT22_MARK,		PORT22_FN4,	MSEL5CR_21_0),
-	PINMUX_DATA(VIO0_D13_PORT22_MARK,	PORT22_FN7,	MSEL5CR_27_1),
-
-	/* Port23 */
-	PINMUX_DATA(SCIFA1_RTS_MARK,		PORT23_FN1),
-	PINMUX_DATA(SCIFA5_SCK_PORT23_MARK,	PORT23_FN3,	MSEL5CR_13_0),
-	PINMUX_DATA(TPU0TO0_MARK,		PORT23_FN4),
-	PINMUX_DATA(VIO_CKO_1_MARK,		PORT23_FN5),
-	PINMUX_DATA(STP0_IPD2_MARK,		PORT23_FN6),
-	PINMUX_DATA(LCD1_D7_MARK,		PORT23_FN7),
-
-	/* Port24 */
-	PINMUX_DATA(VIO0_D15_PORT24_MARK,	PORT24_FN1,	MSEL5CR_27_0),
-	PINMUX_DATA(VIO1_D7_MARK,		PORT24_FN5),
-	PINMUX_DATA(SCIFA6_SCK_MARK,		PORT24_FN6),
-	PINMUX_DATA(SDHI2_CD_PORT24_MARK,	PORT24_FN7,	MSEL5CR_19_0),
-
-	/* Port25 */
-	PINMUX_DATA(VIO0_D14_PORT25_MARK,	PORT25_FN1,	MSEL5CR_27_0),
-	PINMUX_DATA(VIO1_D6_MARK,		PORT25_FN5),
-	PINMUX_DATA(SCIFA6_RXD_MARK,		PORT25_FN6),
-	PINMUX_DATA(SDHI2_WP_PORT25_MARK,	PORT25_FN7,	MSEL5CR_19_0),
-
-	/* Port26 */
-	PINMUX_DATA(VIO0_D13_PORT26_MARK,	PORT26_FN1,	MSEL5CR_27_0),
-	PINMUX_DATA(VIO1_D5_MARK,		PORT26_FN5),
-	PINMUX_DATA(SCIFA6_TXD_MARK,		PORT26_FN6),
-
-	/* Port27 - Port39 Function */
-	PINMUX_DATA(VIO0_D7_MARK,		PORT27_FN1),
-	PINMUX_DATA(VIO0_D6_MARK,		PORT28_FN1),
-	PINMUX_DATA(VIO0_D5_MARK,		PORT29_FN1),
-	PINMUX_DATA(VIO0_D4_MARK,		PORT30_FN1),
-	PINMUX_DATA(VIO0_D3_MARK,		PORT31_FN1),
-	PINMUX_DATA(VIO0_D2_MARK,		PORT32_FN1),
-	PINMUX_DATA(VIO0_D1_MARK,		PORT33_FN1),
-	PINMUX_DATA(VIO0_D0_MARK,		PORT34_FN1),
-	PINMUX_DATA(VIO0_CLK_MARK,		PORT35_FN1),
-	PINMUX_DATA(VIO_CKO_MARK,		PORT36_FN1),
-	PINMUX_DATA(VIO0_HD_MARK,		PORT37_FN1),
-	PINMUX_DATA(VIO0_FIELD_MARK,		PORT38_FN1),
-	PINMUX_DATA(VIO0_VD_MARK,		PORT39_FN1),
-
-	/* Port38 IRQ */
-	PINMUX_DATA(IRQ25_MARK,			PORT38_FN0),
-
-	/* Port40 */
-	PINMUX_DATA(LCD0_D18_PORT40_MARK,	PORT40_FN4,	MSEL5CR_6_0),
-	PINMUX_DATA(RSPI_CK_A_MARK,		PORT40_FN6),
-	PINMUX_DATA(LCD1_LCLK_MARK,		PORT40_FN7),
-
-	/* Port41 */
-	PINMUX_DATA(LCD0_D17_MARK,		PORT41_FN1),
-	PINMUX_DATA(MSIOF2_SS1_MARK,		PORT41_FN2),
-	PINMUX_DATA(IRQ31_PORT41_MARK,		PORT41_FN0,	MSEL1CR_31_1),
-
-	/* Port42 */
-	PINMUX_DATA(LCD0_D16_MARK,		PORT42_FN1),
-	PINMUX_DATA(MSIOF2_MCK1_MARK,		PORT42_FN2),
-	PINMUX_DATA(IRQ12_PORT42_MARK,		PORT42_FN0,	MSEL1CR_12_1),
-
-	/* Port43 */
-	PINMUX_DATA(LCD0_D15_MARK,		PORT43_FN1),
-	PINMUX_DATA(MSIOF2_MCK0_MARK,		PORT43_FN2),
-	PINMUX_DATA(KEYIN0_PORT43_MARK,		PORT43_FN3,	MSEL4CR_18_0),
-	PINMUX_DATA(DV_D15_MARK,		PORT43_FN6),
-
-	/* Port44 */
-	PINMUX_DATA(LCD0_D14_MARK,		PORT44_FN1),
-	PINMUX_DATA(MSIOF2_RSYNC_MARK,		PORT44_FN2),
-	PINMUX_DATA(KEYIN1_PORT44_MARK,		PORT44_FN3,	MSEL4CR_18_0),
-	PINMUX_DATA(DV_D14_MARK,		PORT44_FN6),
-
-	/* Port45 */
-	PINMUX_DATA(LCD0_D13_MARK,		PORT45_FN1),
-	PINMUX_DATA(MSIOF2_RSCK_MARK,		PORT45_FN2),
-	PINMUX_DATA(KEYIN2_PORT45_MARK,		PORT45_FN3,	MSEL4CR_18_0),
-	PINMUX_DATA(DV_D13_MARK,		PORT45_FN6),
-
-	/* Port46 */
-	PINMUX_DATA(LCD0_D12_MARK,		PORT46_FN1),
-	PINMUX_DATA(KEYIN3_PORT46_MARK,		PORT46_FN3,	MSEL4CR_18_0),
-	PINMUX_DATA(DV_D12_MARK,		PORT46_FN6),
-
-	/* Port47 */
-	PINMUX_DATA(LCD0_D11_MARK,		PORT47_FN1),
-	PINMUX_DATA(KEYIN4_MARK,		PORT47_FN3),
-	PINMUX_DATA(DV_D11_MARK,		PORT47_FN6),
-
-	/* Port48 */
-	PINMUX_DATA(LCD0_D10_MARK,		PORT48_FN1),
-	PINMUX_DATA(KEYIN5_MARK,		PORT48_FN3),
-	PINMUX_DATA(DV_D10_MARK,		PORT48_FN6),
-
-	/* Port49 */
-	PINMUX_DATA(LCD0_D9_MARK,		PORT49_FN1),
-	PINMUX_DATA(KEYIN6_MARK,		PORT49_FN3),
-	PINMUX_DATA(DV_D9_MARK,			PORT49_FN6),
-	PINMUX_DATA(IRQ30_PORT49_MARK,		PORT49_FN0,	MSEL1CR_30_1),
-
-	/* Port50 */
-	PINMUX_DATA(LCD0_D8_MARK,		PORT50_FN1),
-	PINMUX_DATA(KEYIN7_MARK,		PORT50_FN3),
-	PINMUX_DATA(DV_D8_MARK,			PORT50_FN6),
-	PINMUX_DATA(IRQ29_PORT50_MARK,		PORT50_FN0,	MSEL1CR_29_1),
-
-	/* Port51 */
-	PINMUX_DATA(LCD0_D7_MARK,		PORT51_FN1),
-	PINMUX_DATA(KEYOUT0_MARK,		PORT51_FN3),
-	PINMUX_DATA(DV_D7_MARK,			PORT51_FN6),
-
-	/* Port52 */
-	PINMUX_DATA(LCD0_D6_MARK,		PORT52_FN1),
-	PINMUX_DATA(KEYOUT1_MARK,		PORT52_FN3),
-	PINMUX_DATA(DV_D6_MARK,			PORT52_FN6),
-
-	/* Port53 */
-	PINMUX_DATA(LCD0_D5_MARK,		PORT53_FN1),
-	PINMUX_DATA(KEYOUT2_MARK,		PORT53_FN3),
-	PINMUX_DATA(DV_D5_MARK,			PORT53_FN6),
-
-	/* Port54 */
-	PINMUX_DATA(LCD0_D4_MARK,		PORT54_FN1),
-	PINMUX_DATA(KEYOUT3_MARK,		PORT54_FN3),
-	PINMUX_DATA(DV_D4_MARK,			PORT54_FN6),
-
-	/* Port55 */
-	PINMUX_DATA(LCD0_D3_MARK,		PORT55_FN1),
-	PINMUX_DATA(KEYOUT4_MARK,		PORT55_FN3),
-	PINMUX_DATA(KEYIN3_PORT55_MARK,		PORT55_FN4,	MSEL4CR_18_1),
-	PINMUX_DATA(DV_D3_MARK,			PORT55_FN6),
-
-	/* Port56 */
-	PINMUX_DATA(LCD0_D2_MARK,		PORT56_FN1),
-	PINMUX_DATA(KEYOUT5_MARK,		PORT56_FN3),
-	PINMUX_DATA(KEYIN2_PORT56_MARK,		PORT56_FN4,	MSEL4CR_18_1),
-	PINMUX_DATA(DV_D2_MARK,			PORT56_FN6),
-	PINMUX_DATA(IRQ28_PORT56_MARK,		PORT56_FN0,	MSEL1CR_28_1),
-
-	/* Port57 */
-	PINMUX_DATA(LCD0_D1_MARK,		PORT57_FN1),
-	PINMUX_DATA(KEYOUT6_MARK,		PORT57_FN3),
-	PINMUX_DATA(KEYIN1_PORT57_MARK,		PORT57_FN4,	MSEL4CR_18_1),
-	PINMUX_DATA(DV_D1_MARK,			PORT57_FN6),
-	PINMUX_DATA(IRQ27_PORT57_MARK,		PORT57_FN0,	MSEL1CR_27_1),
-
-	/* Port58 */
-	PINMUX_DATA(LCD0_D0_MARK,		PORT58_FN1,	MSEL3CR_6_0),
-	PINMUX_DATA(KEYOUT7_MARK,		PORT58_FN3),
-	PINMUX_DATA(KEYIN0_PORT58_MARK,		PORT58_FN4,	MSEL4CR_18_1),
-	PINMUX_DATA(DV_D0_MARK,			PORT58_FN6),
-	PINMUX_DATA(IRQ26_PORT58_MARK,		PORT58_FN0,	MSEL1CR_26_1),
-
-	/* Port59 */
-	PINMUX_DATA(LCD0_VCPWC_MARK,		PORT59_FN1),
-	PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK,	PORT59_FN2,	MSEL5CR_0_0),
-	PINMUX_DATA(RSPI_MOSI_A_MARK,		PORT59_FN6),
-
-	/* Port60 */
-	PINMUX_DATA(LCD0_VEPWC_MARK,		PORT60_FN1),
-	PINMUX_DATA(BBIF2_RXD2_PORT60_MARK,	PORT60_FN2,	MSEL5CR_0_0),
-	PINMUX_DATA(RSPI_MISO_A_MARK,		PORT60_FN6),
-
-	/* Port61 */
-	PINMUX_DATA(LCD0_DON_MARK,		PORT61_FN1),
-	PINMUX_DATA(MSIOF2_TXD_MARK,		PORT61_FN2),
-
-	/* Port62 */
-	PINMUX_DATA(LCD0_DCK_MARK,		PORT62_FN1),
-	PINMUX_DATA(LCD0_WR_MARK,		PORT62_FN4),
-	PINMUX_DATA(DV_CLK_MARK,		PORT62_FN6),
-	PINMUX_DATA(IRQ15_PORT62_MARK,		PORT62_FN0,	MSEL1CR_15_1),
-
-	/* Port63 */
-	PINMUX_DATA(LCD0_VSYN_MARK,		PORT63_FN1),
-	PINMUX_DATA(DV_VSYNC_MARK,		PORT63_FN6),
-	PINMUX_DATA(IRQ14_PORT63_MARK,		PORT63_FN0,	MSEL1CR_14_1),
-
-	/* Port64 */
-	PINMUX_DATA(LCD0_HSYN_MARK,		PORT64_FN1),
-	PINMUX_DATA(LCD0_CS_MARK,		PORT64_FN4),
-	PINMUX_DATA(DV_HSYNC_MARK,		PORT64_FN6),
-	PINMUX_DATA(IRQ13_PORT64_MARK,		PORT64_FN0,	MSEL1CR_13_1),
-
-	/* Port65 */
-	PINMUX_DATA(LCD0_DISP_MARK,		PORT65_FN1),
-	PINMUX_DATA(MSIOF2_TSCK_MARK,		PORT65_FN2),
-	PINMUX_DATA(LCD0_RS_MARK,		PORT65_FN4),
-
-	/* Port66 */
-	PINMUX_DATA(MEMC_INT_MARK,		PORT66_FN1),
-	PINMUX_DATA(TPU0TO2_PORT66_MARK,	PORT66_FN3,	MSEL5CR_25_0),
-	PINMUX_DATA(MMC0_CLK_PORT66_MARK,	PORT66_FN4,	MSEL4CR_15_0),
-	PINMUX_DATA(SDHI1_CLK_MARK,		PORT66_FN6),
-
-	/* Port67 - Port73 Function1 */
-	PINMUX_DATA(MEMC_CS0_MARK,		PORT67_FN1),
-	PINMUX_DATA(MEMC_AD8_MARK,		PORT68_FN1),
-	PINMUX_DATA(MEMC_AD9_MARK,		PORT69_FN1),
-	PINMUX_DATA(MEMC_AD10_MARK,		PORT70_FN1),
-	PINMUX_DATA(MEMC_AD11_MARK,		PORT71_FN1),
-	PINMUX_DATA(MEMC_AD12_MARK,		PORT72_FN1),
-	PINMUX_DATA(MEMC_AD13_MARK,		PORT73_FN1),
-
-	/* Port67 - Port73 Function2 */
-	PINMUX_DATA(MSIOF1_SS1_PORT67_MARK,	PORT67_FN2,	MSEL4CR_10_1),
-	PINMUX_DATA(MSIOF1_RSCK_MARK,		PORT68_FN2),
-	PINMUX_DATA(MSIOF1_RSYNC_MARK,		PORT69_FN2),
-	PINMUX_DATA(MSIOF1_MCK0_MARK,		PORT70_FN2),
-	PINMUX_DATA(MSIOF1_MCK1_MARK,		PORT71_FN2),
-	PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK,	PORT72_FN2,	MSEL4CR_10_1),
-	PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK,	PORT73_FN2,	MSEL4CR_10_1),
-
-	/* Port67 - Port73 Function4 */
-	PINMUX_DATA(MMC0_CMD_PORT67_MARK,	PORT67_FN4,	MSEL4CR_15_0),
-	PINMUX_DATA(MMC0_D0_PORT68_MARK,	PORT68_FN4,	MSEL4CR_15_0),
-	PINMUX_DATA(MMC0_D1_PORT69_MARK,	PORT69_FN4,	MSEL4CR_15_0),
-	PINMUX_DATA(MMC0_D2_PORT70_MARK,	PORT70_FN4,	MSEL4CR_15_0),
-	PINMUX_DATA(MMC0_D3_PORT71_MARK,	PORT71_FN4,	MSEL4CR_15_0),
-	PINMUX_DATA(MMC0_D4_PORT72_MARK,	PORT72_FN4,	MSEL4CR_15_0),
-	PINMUX_DATA(MMC0_D5_PORT73_MARK,	PORT73_FN4,	MSEL4CR_15_0),
-
-	/* Port67 - Port73 Function6 */
-	PINMUX_DATA(SDHI1_CMD_MARK,		PORT67_FN6),
-	PINMUX_DATA(SDHI1_D0_MARK,		PORT68_FN6),
-	PINMUX_DATA(SDHI1_D1_MARK,		PORT69_FN6),
-	PINMUX_DATA(SDHI1_D2_MARK,		PORT70_FN6),
-	PINMUX_DATA(SDHI1_D3_MARK,		PORT71_FN6),
-	PINMUX_DATA(SDHI1_CD_MARK,		PORT72_FN6),
-	PINMUX_DATA(SDHI1_WP_MARK,		PORT73_FN6),
-
-	/* Port67 - Port71 IRQ */
-	PINMUX_DATA(IRQ20_MARK,			PORT67_FN0),
-	PINMUX_DATA(IRQ16_PORT68_MARK,		PORT68_FN0,	MSEL1CR_16_0),
-	PINMUX_DATA(IRQ17_MARK,			PORT69_FN0),
-	PINMUX_DATA(IRQ18_MARK,			PORT70_FN0),
-	PINMUX_DATA(IRQ19_MARK,			PORT71_FN0),
-
-	/* Port74 */
-	PINMUX_DATA(MEMC_AD14_MARK,		PORT74_FN1),
-	PINMUX_DATA(MSIOF1_TXD_PORT74_MARK,	PORT74_FN2,	MSEL4CR_10_1),
-	PINMUX_DATA(MMC0_D6_PORT74_MARK,	PORT74_FN4,	MSEL4CR_15_0),
-	PINMUX_DATA(STP1_IPD7_MARK,		PORT74_FN6),
-	PINMUX_DATA(LCD1_D21_MARK,		PORT74_FN7),
-
-	/* Port75 */
-	PINMUX_DATA(MEMC_AD15_MARK,		PORT75_FN1),
-	PINMUX_DATA(MSIOF1_RXD_PORT75_MARK,	PORT75_FN2,	MSEL4CR_10_1),
-	PINMUX_DATA(MMC0_D7_PORT75_MARK,	PORT75_FN4,	MSEL4CR_15_0),
-	PINMUX_DATA(STP1_IPD6_MARK,		PORT75_FN6),
-	PINMUX_DATA(LCD1_D20_MARK,		PORT75_FN7),
-
-	/* Port76 - Port80 Function */
-	PINMUX_DATA(SDHI0_CMD_MARK,		PORT76_FN1),
-	PINMUX_DATA(SDHI0_D0_MARK,		PORT77_FN1),
-	PINMUX_DATA(SDHI0_D1_MARK,		PORT78_FN1),
-	PINMUX_DATA(SDHI0_D2_MARK,		PORT79_FN1),
-	PINMUX_DATA(SDHI0_D3_MARK,		PORT80_FN1),
-
-	/* Port81 */
-	PINMUX_DATA(SDHI0_CD_MARK,		PORT81_FN1),
-	PINMUX_DATA(IRQ26_PORT81_MARK,		PORT81_FN0,	MSEL1CR_26_0),
-
-	/* Port82 - Port88 Function */
-	PINMUX_DATA(SDHI0_CLK_MARK,		PORT82_FN1),
-	PINMUX_DATA(SDHI0_WP_MARK,		PORT83_FN1),
-	PINMUX_DATA(RESETOUTS_MARK,		PORT84_FN1),
-	PINMUX_DATA(USB0_PPON_MARK,		PORT85_FN1),
-	PINMUX_DATA(USB0_OCI_MARK,		PORT86_FN1),
-	PINMUX_DATA(USB1_PPON_MARK,		PORT87_FN1),
-	PINMUX_DATA(USB1_OCI_MARK,		PORT88_FN1),
-
-	/* Port89 */
-	PINMUX_DATA(DREQ0_MARK,			PORT89_FN1),
-	PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK,	PORT89_FN2,	MSEL5CR_0_1),
-	PINMUX_DATA(RSPI_SSL3_A_MARK,		PORT89_FN6),
-
-	/* Port90 */
-	PINMUX_DATA(DACK0_MARK,			PORT90_FN1),
-	PINMUX_DATA(BBIF2_RXD2_PORT90_MARK,	PORT90_FN2,	MSEL5CR_0_1),
-	PINMUX_DATA(RSPI_SSL2_A_MARK,		PORT90_FN6),
-	PINMUX_DATA(WAIT_PORT90_MARK,		PORT90_FN7,	MSEL5CR_2_1),
-
-	/* Port91 */
-	PINMUX_DATA(MEMC_AD0_MARK,		PORT91_FN1),
-	PINMUX_DATA(BBIF1_RXD_MARK,		PORT91_FN2),
-	PINMUX_DATA(SCIFA5_TXD_PORT91_MARK,	PORT91_FN3,	MSEL5CR_15_1,	MSEL5CR_14_0),
-	PINMUX_DATA(LCD1_D5_MARK,		PORT91_FN7),
-
-	/* Port92 */
-	PINMUX_DATA(MEMC_AD1_MARK,		PORT92_FN1),
-	PINMUX_DATA(BBIF1_TSYNC_MARK,		PORT92_FN2),
-	PINMUX_DATA(SCIFA5_RXD_PORT92_MARK,	PORT92_FN3,	MSEL5CR_15_1,	MSEL5CR_14_0),
-	PINMUX_DATA(STP0_IPD1_MARK,		PORT92_FN6),
-	PINMUX_DATA(LCD1_D6_MARK,		PORT92_FN7),
-
-	/* Port93 */
-	PINMUX_DATA(MEMC_AD2_MARK,		PORT93_FN1),
-	PINMUX_DATA(BBIF1_TSCK_MARK,		PORT93_FN2),
-	PINMUX_DATA(SCIFA4_TXD_PORT93_MARK,	PORT93_FN3,	MSEL5CR_12_1,	MSEL5CR_11_0),
-	PINMUX_DATA(STP0_IPD3_MARK,		PORT93_FN6),
-	PINMUX_DATA(LCD1_D8_MARK,		PORT93_FN7),
-
-	/* Port94 */
-	PINMUX_DATA(MEMC_AD3_MARK,		PORT94_FN1),
-	PINMUX_DATA(BBIF1_TXD_MARK,		PORT94_FN2),
-	PINMUX_DATA(SCIFA4_RXD_PORT94_MARK,	PORT94_FN3,	MSEL5CR_12_1,	MSEL5CR_11_0),
-	PINMUX_DATA(STP0_IPD4_MARK,		PORT94_FN6),
-	PINMUX_DATA(LCD1_D9_MARK,		PORT94_FN7),
-
-	/* Port95 */
-	PINMUX_DATA(MEMC_CS1_MARK,		PORT95_FN1,	MSEL4CR_6_0),
-	PINMUX_DATA(MEMC_A1_MARK,		PORT95_FN1,	MSEL4CR_6_1),
-
-	PINMUX_DATA(SCIFA2_CTS_MARK,		PORT95_FN2),
-	PINMUX_DATA(SIM_RST_MARK,		PORT95_FN4),
-	PINMUX_DATA(VIO0_D14_PORT95_MARK,	PORT95_FN7,	MSEL5CR_27_1),
-	PINMUX_DATA(IRQ22_MARK,			PORT95_FN0),
-
-	/* Port96 */
-	PINMUX_DATA(MEMC_ADV_MARK,		PORT96_FN1,	MSEL4CR_6_0),
-	PINMUX_DATA(MEMC_DREQ0_MARK,		PORT96_FN1,	MSEL4CR_6_1),
-
-	PINMUX_DATA(SCIFA2_RTS_MARK,		PORT96_FN2),
-	PINMUX_DATA(SIM_CLK_MARK,		PORT96_FN4),
-	PINMUX_DATA(VIO0_D15_PORT96_MARK,	PORT96_FN7,	MSEL5CR_27_1),
-	PINMUX_DATA(IRQ23_MARK,			PORT96_FN0),
-
-	/* Port97 */
-	PINMUX_DATA(MEMC_AD4_MARK,		PORT97_FN1),
-	PINMUX_DATA(BBIF1_RSCK_MARK,		PORT97_FN2),
-	PINMUX_DATA(LCD1_CS_MARK,		PORT97_FN6),
-	PINMUX_DATA(LCD1_HSYN_MARK,		PORT97_FN7),
-	PINMUX_DATA(IRQ12_PORT97_MARK,		PORT97_FN0,	MSEL1CR_12_0),
-
-	/* Port98 */
-	PINMUX_DATA(MEMC_AD5_MARK,		PORT98_FN1),
-	PINMUX_DATA(BBIF1_RSYNC_MARK,		PORT98_FN2),
-	PINMUX_DATA(LCD1_VSYN_MARK,		PORT98_FN7),
-	PINMUX_DATA(IRQ13_PORT98_MARK,		PORT98_FN0,	MSEL1CR_13_0),
-
-	/* Port99 */
-	PINMUX_DATA(MEMC_AD6_MARK,		PORT99_FN1),
-	PINMUX_DATA(BBIF1_FLOW_MARK,		PORT99_FN2),
-	PINMUX_DATA(LCD1_WR_MARK,		PORT99_FN6),
-	PINMUX_DATA(LCD1_DCK_MARK,		PORT99_FN7),
-	PINMUX_DATA(IRQ14_PORT99_MARK,		PORT99_FN0,	MSEL1CR_14_0),
-
-	/* Port100 */
-	PINMUX_DATA(MEMC_AD7_MARK,		PORT100_FN1),
-	PINMUX_DATA(BBIF1_RX_FLOW_N_MARK,	PORT100_FN2),
-	PINMUX_DATA(LCD1_DON_MARK,		PORT100_FN7),
-	PINMUX_DATA(IRQ15_PORT100_MARK,		PORT100_FN0,	MSEL1CR_15_0),
-
-	/* Port101 */
-	PINMUX_DATA(FCE0_MARK,			PORT101_FN1),
-
-	/* Port102 */
-	PINMUX_DATA(FRB_MARK,			PORT102_FN1),
-	PINMUX_DATA(LCD0_LCLK_PORT102_MARK,	PORT102_FN4,	MSEL5CR_6_0),
-
-	/* Port103 */
-	PINMUX_DATA(CS5B_MARK,			PORT103_FN1),
-	PINMUX_DATA(FCE1_MARK,			PORT103_FN2),
-	PINMUX_DATA(MMC1_CLK_PORT103_MARK,	PORT103_FN3,	MSEL4CR_15_1),
-
-	/* Port104 */
-	PINMUX_DATA(CS6A_MARK,			PORT104_FN1),
-	PINMUX_DATA(MMC1_CMD_PORT104_MARK,	PORT104_FN3,	MSEL4CR_15_1),
-	PINMUX_DATA(IRQ11_MARK,			PORT104_FN0),
-
-	/* Port105 */
-	PINMUX_DATA(CS5A_PORT105_MARK,		PORT105_FN1,	MSEL5CR_2_0),
-	PINMUX_DATA(SCIFA3_RTS_PORT105_MARK,	PORT105_FN4,	MSEL5CR_8_0),
-
-	/* Port106 */
-	PINMUX_DATA(IOIS16_MARK,		PORT106_FN1),
-	PINMUX_DATA(IDE_EXBUF_ENB_MARK,		PORT106_FN6),
-
-	/* Port107 - Port115 Function */
-	PINMUX_DATA(WE3_ICIOWR_MARK,		PORT107_FN1),
-	PINMUX_DATA(WE2_ICIORD_MARK,		PORT108_FN1),
-	PINMUX_DATA(CS0_MARK,			PORT109_FN1),
-	PINMUX_DATA(CS2_MARK,			PORT110_FN1),
-	PINMUX_DATA(CS4_MARK,			PORT111_FN1),
-	PINMUX_DATA(WE1_MARK,			PORT112_FN1),
-	PINMUX_DATA(WE0_FWE_MARK,		PORT113_FN1),
-	PINMUX_DATA(RDWR_MARK,			PORT114_FN1),
-	PINMUX_DATA(RD_FSC_MARK,		PORT115_FN1),
-
-	/* Port116 */
-	PINMUX_DATA(A25_MARK,			PORT116_FN1),
-	PINMUX_DATA(MSIOF0_SS2_MARK,		PORT116_FN2),
-	PINMUX_DATA(MSIOF1_SS2_PORT116_MARK,	PORT116_FN3,	MSEL4CR_10_0),
-	PINMUX_DATA(SCIFA3_SCK_PORT116_MARK,	PORT116_FN4,	MSEL5CR_8_0),
-	PINMUX_DATA(GPO1_MARK,			PORT116_FN5),
-
-	/* Port117 */
-	PINMUX_DATA(A24_MARK,			PORT117_FN1),
-	PINMUX_DATA(MSIOF0_SS1_MARK,		PORT117_FN2),
-	PINMUX_DATA(MSIOF1_SS1_PORT117_MARK,	PORT117_FN3,	MSEL4CR_10_0),
-	PINMUX_DATA(SCIFA3_CTS_PORT117_MARK,	PORT117_FN4,	MSEL5CR_8_0),
-	PINMUX_DATA(GPO0_MARK,			PORT117_FN5),
-
-	/* Port118 */
-	PINMUX_DATA(A23_MARK,			PORT118_FN1),
-	PINMUX_DATA(MSIOF0_MCK1_MARK,		PORT118_FN2),
-	PINMUX_DATA(MSIOF1_RXD_PORT118_MARK,	PORT118_FN3,	MSEL4CR_10_0),
-	PINMUX_DATA(GPI1_MARK,			PORT118_FN5),
-	PINMUX_DATA(IRQ9_PORT118_MARK,		PORT118_FN0,	MSEL1CR_9_0),
-
-	/* Port119 */
-	PINMUX_DATA(A22_MARK,			PORT119_FN1),
-	PINMUX_DATA(MSIOF0_MCK0_MARK,		PORT119_FN2),
-	PINMUX_DATA(MSIOF1_TXD_PORT119_MARK,	PORT119_FN3,	MSEL4CR_10_0),
-	PINMUX_DATA(GPI0_MARK,			PORT119_FN5),
-	PINMUX_DATA(IRQ8_MARK,			PORT119_FN0),
-
-	/* Port120 */
-	PINMUX_DATA(A21_MARK,			PORT120_FN1),
-	PINMUX_DATA(MSIOF0_RSYNC_MARK,		PORT120_FN2),
-	PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK,	PORT120_FN3,	MSEL4CR_10_0),
-	PINMUX_DATA(IRQ7_PORT120_MARK,		PORT120_FN0,	MSEL1CR_7_1),
-
-	/* Port121 */
-	PINMUX_DATA(A20_MARK,			PORT121_FN1),
-	PINMUX_DATA(MSIOF0_RSCK_MARK,		PORT121_FN2),
-	PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK,	PORT121_FN3,	MSEL4CR_10_0),
-	PINMUX_DATA(IRQ6_PORT121_MARK,		PORT121_FN0,	MSEL1CR_6_0),
-
-	/* Port122 */
-	PINMUX_DATA(A19_MARK,			PORT122_FN1),
-	PINMUX_DATA(MSIOF0_RXD_MARK,		PORT122_FN2),
-
-	/* Port123 */
-	PINMUX_DATA(A18_MARK,			PORT123_FN1),
-	PINMUX_DATA(MSIOF0_TSCK_MARK,		PORT123_FN2),
-
-	/* Port124 */
-	PINMUX_DATA(A17_MARK,			PORT124_FN1),
-	PINMUX_DATA(MSIOF0_TSYNC_MARK,		PORT124_FN2),
-
-	/* Port125 - Port141 Function */
-	PINMUX_DATA(A16_MARK,			PORT125_FN1),
-	PINMUX_DATA(A15_MARK,			PORT126_FN1),
-	PINMUX_DATA(A14_MARK,			PORT127_FN1),
-	PINMUX_DATA(A13_MARK,			PORT128_FN1),
-	PINMUX_DATA(A12_MARK,			PORT129_FN1),
-	PINMUX_DATA(A11_MARK,			PORT130_FN1),
-	PINMUX_DATA(A10_MARK,			PORT131_FN1),
-	PINMUX_DATA(A9_MARK,			PORT132_FN1),
-	PINMUX_DATA(A8_MARK,			PORT133_FN1),
-	PINMUX_DATA(A7_MARK,			PORT134_FN1),
-	PINMUX_DATA(A6_MARK,			PORT135_FN1),
-	PINMUX_DATA(A5_FCDE_MARK,		PORT136_FN1),
-	PINMUX_DATA(A4_FOE_MARK,		PORT137_FN1),
-	PINMUX_DATA(A3_MARK,			PORT138_FN1),
-	PINMUX_DATA(A2_MARK,			PORT139_FN1),
-	PINMUX_DATA(A1_MARK,			PORT140_FN1),
-	PINMUX_DATA(CKO_MARK,			PORT141_FN1),
-
-	/* Port142 - Port157 Function1 */
-	PINMUX_DATA(D15_NAF15_MARK,		PORT142_FN1),
-	PINMUX_DATA(D14_NAF14_MARK,		PORT143_FN1),
-	PINMUX_DATA(D13_NAF13_MARK,		PORT144_FN1),
-	PINMUX_DATA(D12_NAF12_MARK,		PORT145_FN1),
-	PINMUX_DATA(D11_NAF11_MARK,		PORT146_FN1),
-	PINMUX_DATA(D10_NAF10_MARK,		PORT147_FN1),
-	PINMUX_DATA(D9_NAF9_MARK,		PORT148_FN1),
-	PINMUX_DATA(D8_NAF8_MARK,		PORT149_FN1),
-	PINMUX_DATA(D7_NAF7_MARK,		PORT150_FN1),
-	PINMUX_DATA(D6_NAF6_MARK,		PORT151_FN1),
-	PINMUX_DATA(D5_NAF5_MARK,		PORT152_FN1),
-	PINMUX_DATA(D4_NAF4_MARK,		PORT153_FN1),
-	PINMUX_DATA(D3_NAF3_MARK,		PORT154_FN1),
-	PINMUX_DATA(D2_NAF2_MARK,		PORT155_FN1),
-	PINMUX_DATA(D1_NAF1_MARK,		PORT156_FN1),
-	PINMUX_DATA(D0_NAF0_MARK,		PORT157_FN1),
-
-	/* Port142 - Port149 Function3 */
-	PINMUX_DATA(MMC1_D7_PORT142_MARK,	PORT142_FN3,	MSEL4CR_15_1),
-	PINMUX_DATA(MMC1_D6_PORT143_MARK,	PORT143_FN3,	MSEL4CR_15_1),
-	PINMUX_DATA(MMC1_D5_PORT144_MARK,	PORT144_FN3,	MSEL4CR_15_1),
-	PINMUX_DATA(MMC1_D4_PORT145_MARK,	PORT145_FN3,	MSEL4CR_15_1),
-	PINMUX_DATA(MMC1_D3_PORT146_MARK,	PORT146_FN3,	MSEL4CR_15_1),
-	PINMUX_DATA(MMC1_D2_PORT147_MARK,	PORT147_FN3,	MSEL4CR_15_1),
-	PINMUX_DATA(MMC1_D1_PORT148_MARK,	PORT148_FN3,	MSEL4CR_15_1),
-	PINMUX_DATA(MMC1_D0_PORT149_MARK,	PORT149_FN3,	MSEL4CR_15_1),
-
-	/* Port158 */
-	PINMUX_DATA(D31_MARK,			PORT158_FN1),
-	PINMUX_DATA(SCIFA3_SCK_PORT158_MARK,	PORT158_FN2,	MSEL5CR_8_1),
-	PINMUX_DATA(RMII_REF125CK_MARK,		PORT158_FN3),
-	PINMUX_DATA(LCD0_D21_PORT158_MARK,	PORT158_FN4,	MSEL5CR_6_1),
-	PINMUX_DATA(IRDA_FIRSEL_MARK,		PORT158_FN5),
-	PINMUX_DATA(IDE_D15_MARK,		PORT158_FN6),
-
-	/* Port159 */
-	PINMUX_DATA(D30_MARK,			PORT159_FN1),
-	PINMUX_DATA(SCIFA3_RXD_PORT159_MARK,	PORT159_FN2,	MSEL5CR_8_1),
-	PINMUX_DATA(RMII_REF50CK_MARK,		PORT159_FN3),
-	PINMUX_DATA(LCD0_D23_PORT159_MARK,	PORT159_FN4,	MSEL5CR_6_1),
-	PINMUX_DATA(IDE_D14_MARK,		PORT159_FN6),
-
-	/* Port160 */
-	PINMUX_DATA(D29_MARK,			PORT160_FN1),
-	PINMUX_DATA(SCIFA3_TXD_PORT160_MARK,	PORT160_FN2,	MSEL5CR_8_1),
-	PINMUX_DATA(LCD0_D22_PORT160_MARK,	PORT160_FN4,	MSEL5CR_6_1),
-	PINMUX_DATA(VIO1_HD_MARK,		PORT160_FN5),
-	PINMUX_DATA(IDE_D13_MARK,		PORT160_FN6),
-
-	/* Port161 */
-	PINMUX_DATA(D28_MARK,			PORT161_FN1),
-	PINMUX_DATA(SCIFA3_RTS_PORT161_MARK,	PORT161_FN2,	MSEL5CR_8_1),
-	PINMUX_DATA(ET_RX_DV_MARK,		PORT161_FN3),
-	PINMUX_DATA(LCD0_D20_PORT161_MARK,	PORT161_FN4,	MSEL5CR_6_1),
-	PINMUX_DATA(IRDA_IN_MARK,		PORT161_FN5),
-	PINMUX_DATA(IDE_D12_MARK,		PORT161_FN6),
-
-	/* Port162 */
-	PINMUX_DATA(D27_MARK,			PORT162_FN1),
-	PINMUX_DATA(SCIFA3_CTS_PORT162_MARK,	PORT162_FN2,	MSEL5CR_8_1),
-	PINMUX_DATA(LCD0_D19_PORT162_MARK,	PORT162_FN4,	MSEL5CR_6_1),
-	PINMUX_DATA(IRDA_OUT_MARK,		PORT162_FN5),
-	PINMUX_DATA(IDE_D11_MARK,		PORT162_FN6),
-
-	/* Port163 */
-	PINMUX_DATA(D26_MARK,			PORT163_FN1),
-	PINMUX_DATA(MSIOF2_SS2_MARK,		PORT163_FN2),
-	PINMUX_DATA(ET_COL_MARK,		PORT163_FN3),
-	PINMUX_DATA(LCD0_D18_PORT163_MARK,	PORT163_FN4,	MSEL5CR_6_1),
-	PINMUX_DATA(IROUT_MARK,			PORT163_FN5),
-	PINMUX_DATA(IDE_D10_MARK,		PORT163_FN6),
-
-	/* Port164 */
-	PINMUX_DATA(D25_MARK,			PORT164_FN1),
-	PINMUX_DATA(MSIOF2_TSYNC_MARK,		PORT164_FN2),
-	PINMUX_DATA(ET_PHY_INT_MARK,		PORT164_FN3),
-	PINMUX_DATA(LCD0_RD_MARK,		PORT164_FN4),
-	PINMUX_DATA(IDE_D9_MARK,		PORT164_FN6),
-
-	/* Port165 */
-	PINMUX_DATA(D24_MARK,			PORT165_FN1),
-	PINMUX_DATA(MSIOF2_RXD_MARK,		PORT165_FN2),
-	PINMUX_DATA(LCD0_LCLK_PORT165_MARK,	PORT165_FN4,	MSEL5CR_6_1),
-	PINMUX_DATA(IDE_D8_MARK,		PORT165_FN6),
-
-	/* Port166 - Port171 Function1 */
-	PINMUX_DATA(D21_MARK,			PORT166_FN1),
-	PINMUX_DATA(D20_MARK,			PORT167_FN1),
-	PINMUX_DATA(D19_MARK,			PORT168_FN1),
-	PINMUX_DATA(D18_MARK,			PORT169_FN1),
-	PINMUX_DATA(D17_MARK,			PORT170_FN1),
-	PINMUX_DATA(D16_MARK,			PORT171_FN1),
-
-	/* Port166 - Port171 Function3 */
-	PINMUX_DATA(ET_ETXD5_MARK,		PORT166_FN3),
-	PINMUX_DATA(ET_ETXD4_MARK,		PORT167_FN3),
-	PINMUX_DATA(ET_ETXD3_MARK,		PORT168_FN3),
-	PINMUX_DATA(ET_ETXD2_MARK,		PORT169_FN3),
-	PINMUX_DATA(ET_ETXD1_MARK,		PORT170_FN3),
-	PINMUX_DATA(ET_ETXD0_MARK,		PORT171_FN3),
-
-	/* Port166 - Port171 Function6 */
-	PINMUX_DATA(IDE_D5_MARK,		PORT166_FN6),
-	PINMUX_DATA(IDE_D4_MARK,		PORT167_FN6),
-	PINMUX_DATA(IDE_D3_MARK,		PORT168_FN6),
-	PINMUX_DATA(IDE_D2_MARK,		PORT169_FN6),
-	PINMUX_DATA(IDE_D1_MARK,		PORT170_FN6),
-	PINMUX_DATA(IDE_D0_MARK,		PORT171_FN6),
-
-	/* Port167 - Port171 IRQ */
-	PINMUX_DATA(IRQ31_PORT167_MARK,		PORT167_FN0,	MSEL1CR_31_0),
-	PINMUX_DATA(IRQ27_PORT168_MARK,		PORT168_FN0,	MSEL1CR_27_0),
-	PINMUX_DATA(IRQ28_PORT169_MARK,		PORT169_FN0,	MSEL1CR_28_0),
-	PINMUX_DATA(IRQ29_PORT170_MARK,		PORT170_FN0,	MSEL1CR_29_0),
-	PINMUX_DATA(IRQ30_PORT171_MARK,		PORT171_FN0,	MSEL1CR_30_0),
-
-	/* Port172 */
-	PINMUX_DATA(D23_MARK,			PORT172_FN1),
-	PINMUX_DATA(SCIFB_RTS_PORT172_MARK,	PORT172_FN2,	MSEL5CR_17_1),
-	PINMUX_DATA(ET_ETXD7_MARK,		PORT172_FN3),
-	PINMUX_DATA(IDE_D7_MARK,		PORT172_FN6),
-	PINMUX_DATA(IRQ4_PORT172_MARK,		PORT172_FN0,	MSEL1CR_4_1),
-
-	/* Port173 */
-	PINMUX_DATA(D22_MARK,			PORT173_FN1),
-	PINMUX_DATA(SCIFB_CTS_PORT173_MARK,	PORT173_FN2,	MSEL5CR_17_1),
-	PINMUX_DATA(ET_ETXD6_MARK,		PORT173_FN3),
-	PINMUX_DATA(IDE_D6_MARK,		PORT173_FN6),
-	PINMUX_DATA(IRQ6_PORT173_MARK,		PORT173_FN0,	MSEL1CR_6_1),
-
-	/* Port174 */
-	PINMUX_DATA(A26_MARK,			PORT174_FN1),
-	PINMUX_DATA(MSIOF0_TXD_MARK,		PORT174_FN2),
-	PINMUX_DATA(ET_RX_CLK_MARK,		PORT174_FN3),
-	PINMUX_DATA(SCIFA3_RXD_PORT174_MARK,	PORT174_FN4,	MSEL5CR_8_0),
-
-	/* Port175 */
-	PINMUX_DATA(A0_MARK,			PORT175_FN1),
-	PINMUX_DATA(BS_MARK,			PORT175_FN2),
-	PINMUX_DATA(ET_WOL_MARK,		PORT175_FN3),
-	PINMUX_DATA(SCIFA3_TXD_PORT175_MARK,	PORT175_FN4,	MSEL5CR_8_0),
-
-	/* Port176 */
-	PINMUX_DATA(ET_GTX_CLK_MARK,		PORT176_FN3),
-
-	/* Port177 */
-	PINMUX_DATA(WAIT_PORT177_MARK,		PORT177_FN1,	MSEL5CR_2_0),
-	PINMUX_DATA(ET_LINK_MARK,		PORT177_FN3),
-	PINMUX_DATA(IDE_IOWR_MARK,		PORT177_FN6),
-	PINMUX_DATA(SDHI2_WP_PORT177_MARK,	PORT177_FN7,	MSEL5CR_19_1),
-
-	/* Port178 */
-	PINMUX_DATA(VIO0_D12_MARK,		PORT178_FN1),
-	PINMUX_DATA(VIO1_D4_MARK,		PORT178_FN5),
-	PINMUX_DATA(IDE_IORD_MARK,		PORT178_FN6),
-
-	/* Port179 */
-	PINMUX_DATA(VIO0_D11_MARK,		PORT179_FN1),
-	PINMUX_DATA(VIO1_D3_MARK,		PORT179_FN5),
-	PINMUX_DATA(IDE_IORDY_MARK,		PORT179_FN6),
-
-	/* Port180 */
-	PINMUX_DATA(VIO0_D10_MARK,		PORT180_FN1),
-	PINMUX_DATA(TPU0TO3_MARK,		PORT180_FN4),
-	PINMUX_DATA(VIO1_D2_MARK,		PORT180_FN5),
-	PINMUX_DATA(IDE_INT_MARK,		PORT180_FN6),
-	PINMUX_DATA(IRQ24_MARK,			PORT180_FN0),
-
-	/* Port181 */
-	PINMUX_DATA(VIO0_D9_MARK,		PORT181_FN1),
-	PINMUX_DATA(VIO1_D1_MARK,		PORT181_FN5),
-	PINMUX_DATA(IDE_RST_MARK,		PORT181_FN6),
-
-	/* Port182 */
-	PINMUX_DATA(VIO0_D8_MARK,		PORT182_FN1),
-	PINMUX_DATA(VIO1_D0_MARK,		PORT182_FN5),
-	PINMUX_DATA(IDE_DIRECTION_MARK,		PORT182_FN6),
-
-	/* Port183 */
-	PINMUX_DATA(DREQ1_MARK,			PORT183_FN1),
-	PINMUX_DATA(BBIF2_TXD2_PORT183_MARK,	PORT183_FN2,	MSEL5CR_0_1),
-	PINMUX_DATA(ET_TX_EN_MARK,		PORT183_FN3),
-
-	/* Port184 */
-	PINMUX_DATA(DACK1_MARK,			PORT184_FN1),
-	PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK,	PORT184_FN2,	MSEL5CR_0_1),
-	PINMUX_DATA(ET_TX_CLK_MARK,		PORT184_FN3),
-
-	/* Port185 - Port192 Function1 */
-	PINMUX_DATA(SCIFA1_SCK_MARK,		PORT185_FN1),
-	PINMUX_DATA(SCIFB_RTS_PORT186_MARK,	PORT186_FN1,	MSEL5CR_17_0),
-	PINMUX_DATA(SCIFB_CTS_PORT187_MARK,	PORT187_FN1,	MSEL5CR_17_0),
-	PINMUX_DATA(SCIFA0_SCK_MARK,		PORT188_FN1),
-	PINMUX_DATA(SCIFB_SCK_PORT190_MARK,	PORT190_FN1,	MSEL5CR_17_0),
-	PINMUX_DATA(SCIFB_RXD_PORT191_MARK,	PORT191_FN1,	MSEL5CR_17_0),
-	PINMUX_DATA(SCIFB_TXD_PORT192_MARK,	PORT192_FN1,	MSEL5CR_17_0),
-
-	/* Port185 - Port192 Function3 */
-	PINMUX_DATA(ET_ERXD0_MARK,		PORT185_FN3),
-	PINMUX_DATA(ET_ERXD1_MARK,		PORT186_FN3),
-	PINMUX_DATA(ET_ERXD2_MARK,		PORT187_FN3),
-	PINMUX_DATA(ET_ERXD3_MARK,		PORT188_FN3),
-	PINMUX_DATA(ET_ERXD4_MARK,		PORT189_FN3),
-	PINMUX_DATA(ET_ERXD5_MARK,		PORT190_FN3),
-	PINMUX_DATA(ET_ERXD6_MARK,		PORT191_FN3),
-	PINMUX_DATA(ET_ERXD7_MARK,		PORT192_FN3),
-
-	/* Port185 - Port192 Function6 */
-	PINMUX_DATA(STP1_IPCLK_MARK,		PORT185_FN6),
-	PINMUX_DATA(STP1_IPD0_PORT186_MARK,	PORT186_FN6,	MSEL5CR_23_0),
-	PINMUX_DATA(STP1_IPEN_PORT187_MARK,	PORT187_FN6,	MSEL5CR_23_0),
-	PINMUX_DATA(STP1_IPSYNC_MARK,		PORT188_FN6),
-	PINMUX_DATA(STP0_IPCLK_MARK,		PORT189_FN6),
-	PINMUX_DATA(STP0_IPD0_MARK,		PORT190_FN6),
-	PINMUX_DATA(STP0_IPEN_MARK,		PORT191_FN6),
-	PINMUX_DATA(STP0_IPSYNC_MARK,		PORT192_FN6),
-
-	/* Port193 */
-	PINMUX_DATA(SCIFA0_CTS_MARK,		PORT193_FN1),
-	PINMUX_DATA(RMII_CRS_DV_MARK,		PORT193_FN3),
-	PINMUX_DATA(STP1_IPEN_PORT193_MARK,	PORT193_FN6,	MSEL5CR_23_1), /* ? */
-	PINMUX_DATA(LCD1_D17_MARK,		PORT193_FN7),
-
-	/* Port194 */
-	PINMUX_DATA(SCIFA0_RTS_MARK,		PORT194_FN1),
-	PINMUX_DATA(RMII_RX_ER_MARK,		PORT194_FN3),
-	PINMUX_DATA(STP1_IPD0_PORT194_MARK,	PORT194_FN6,	MSEL5CR_23_1), /* ? */
-	PINMUX_DATA(LCD1_D16_MARK,		PORT194_FN7),
-
-	/* Port195 */
-	PINMUX_DATA(SCIFA1_RXD_MARK,		PORT195_FN1),
-	PINMUX_DATA(RMII_RXD0_MARK,		PORT195_FN3),
-	PINMUX_DATA(STP1_IPD3_MARK,		PORT195_FN6),
-	PINMUX_DATA(LCD1_D15_MARK,		PORT195_FN7),
-
-	/* Port196 */
-	PINMUX_DATA(SCIFA1_TXD_MARK,		PORT196_FN1),
-	PINMUX_DATA(RMII_RXD1_MARK,		PORT196_FN3),
-	PINMUX_DATA(STP1_IPD2_MARK,		PORT196_FN6),
-	PINMUX_DATA(LCD1_D14_MARK,		PORT196_FN7),
-
-	/* Port197 */
-	PINMUX_DATA(SCIFA0_RXD_MARK,		PORT197_FN1),
-	PINMUX_DATA(VIO1_CLK_MARK,		PORT197_FN5),
-	PINMUX_DATA(STP1_IPD5_MARK,		PORT197_FN6),
-	PINMUX_DATA(LCD1_D19_MARK,		PORT197_FN7),
-
-	/* Port198 */
-	PINMUX_DATA(SCIFA0_TXD_MARK,		PORT198_FN1),
-	PINMUX_DATA(VIO1_VD_MARK,		PORT198_FN5),
-	PINMUX_DATA(STP1_IPD4_MARK,		PORT198_FN6),
-	PINMUX_DATA(LCD1_D18_MARK,		PORT198_FN7),
-
-	/* Port199 */
-	PINMUX_DATA(MEMC_NWE_MARK,		PORT199_FN1),
-	PINMUX_DATA(SCIFA2_SCK_PORT199_MARK,	PORT199_FN2,	MSEL5CR_7_1),
-	PINMUX_DATA(RMII_TX_EN_MARK,		PORT199_FN3),
-	PINMUX_DATA(SIM_D_PORT199_MARK,		PORT199_FN4,	MSEL5CR_21_1),
-	PINMUX_DATA(STP1_IPD1_MARK,		PORT199_FN6),
-	PINMUX_DATA(LCD1_D13_MARK,		PORT199_FN7),
-
-	/* Port200 */
-	PINMUX_DATA(MEMC_NOE_MARK,		PORT200_FN1),
-	PINMUX_DATA(SCIFA2_RXD_MARK,		PORT200_FN2),
-	PINMUX_DATA(RMII_TXD0_MARK,		PORT200_FN3),
-	PINMUX_DATA(STP0_IPD7_MARK,		PORT200_FN6),
-	PINMUX_DATA(LCD1_D12_MARK,		PORT200_FN7),
-
-	/* Port201 */
-	PINMUX_DATA(MEMC_WAIT_MARK,		PORT201_FN1,	MSEL4CR_6_0),
-	PINMUX_DATA(MEMC_DREQ1_MARK,		PORT201_FN1,	MSEL4CR_6_1),
-
-	PINMUX_DATA(SCIFA2_TXD_MARK,		PORT201_FN2),
-	PINMUX_DATA(RMII_TXD1_MARK,		PORT201_FN3),
-	PINMUX_DATA(STP0_IPD6_MARK,		PORT201_FN6),
-	PINMUX_DATA(LCD1_D11_MARK,		PORT201_FN7),
-
-	/* Port202 */
-	PINMUX_DATA(MEMC_BUSCLK_MARK,		PORT202_FN1,	MSEL4CR_6_0),
-	PINMUX_DATA(MEMC_A0_MARK,		PORT202_FN1,	MSEL4CR_6_1),
-
-	PINMUX_DATA(MSIOF1_SS2_PORT202_MARK,	PORT202_FN2,	MSEL4CR_10_1),
-	PINMUX_DATA(RMII_MDC_MARK,		PORT202_FN3),
-	PINMUX_DATA(TPU0TO2_PORT202_MARK,	PORT202_FN4,	MSEL5CR_25_1),
-	PINMUX_DATA(IDE_CS0_MARK,		PORT202_FN6),
-	PINMUX_DATA(SDHI2_CD_PORT202_MARK,	PORT202_FN7,	MSEL5CR_19_1),
-	PINMUX_DATA(IRQ21_MARK,			PORT202_FN0),
-
-	/* Port203 - Port208 Function1 */
-	PINMUX_DATA(SDHI2_CLK_MARK,		PORT203_FN1),
-	PINMUX_DATA(SDHI2_CMD_MARK,		PORT204_FN1),
-	PINMUX_DATA(SDHI2_D0_MARK,		PORT205_FN1),
-	PINMUX_DATA(SDHI2_D1_MARK,		PORT206_FN1),
-	PINMUX_DATA(SDHI2_D2_MARK,		PORT207_FN1),
-	PINMUX_DATA(SDHI2_D3_MARK,		PORT208_FN1),
-
-	/* Port203 - Port208 Function3 */
-	PINMUX_DATA(ET_TX_ER_MARK,		PORT203_FN3),
-	PINMUX_DATA(ET_RX_ER_MARK,		PORT204_FN3),
-	PINMUX_DATA(ET_CRS_MARK,		PORT205_FN3),
-	PINMUX_DATA(ET_MDC_MARK,		PORT206_FN3),
-	PINMUX_DATA(ET_MDIO_MARK,		PORT207_FN3),
-	PINMUX_DATA(RMII_MDIO_MARK,		PORT208_FN3),
-
-	/* Port203 - Port208 Function6 */
-	PINMUX_DATA(IDE_A2_MARK,		PORT203_FN6),
-	PINMUX_DATA(IDE_A1_MARK,		PORT204_FN6),
-	PINMUX_DATA(IDE_A0_MARK,		PORT205_FN6),
-	PINMUX_DATA(IDE_IODACK_MARK,		PORT206_FN6),
-	PINMUX_DATA(IDE_IODREQ_MARK,		PORT207_FN6),
-	PINMUX_DATA(IDE_CS1_MARK,		PORT208_FN6),
-
-	/* Port203 - Port208 Function7 */
-	PINMUX_DATA(SCIFA4_TXD_PORT203_MARK,	PORT203_FN7,	MSEL5CR_12_0,	MSEL5CR_11_1),
-	PINMUX_DATA(SCIFA4_RXD_PORT204_MARK,	PORT204_FN7,	MSEL5CR_12_0,	MSEL5CR_11_1),
-	PINMUX_DATA(SCIFA4_SCK_PORT205_MARK,	PORT205_FN7,	MSEL5CR_10_1),
-	PINMUX_DATA(SCIFA5_SCK_PORT206_MARK,	PORT206_FN7,	MSEL5CR_13_1),
-	PINMUX_DATA(SCIFA5_RXD_PORT207_MARK,	PORT207_FN7,	MSEL5CR_15_0,	MSEL5CR_14_1),
-	PINMUX_DATA(SCIFA5_TXD_PORT208_MARK,	PORT208_FN7,	MSEL5CR_15_0,	MSEL5CR_14_1),
-
-	/* Port209 */
-	PINMUX_DATA(VBUS_MARK,			PORT209_FN1),
-	PINMUX_DATA(IRQ7_PORT209_MARK,		PORT209_FN0,	MSEL1CR_7_0),
-
-	/* Port210 */
-	PINMUX_DATA(IRQ9_PORT210_MARK,		PORT210_FN0,	MSEL1CR_9_1),
-	PINMUX_DATA(HDMI_HPD_MARK,		PORT210_FN1),
-
-	/* Port211 */
-	PINMUX_DATA(IRQ16_PORT211_MARK,		PORT211_FN0,	MSEL1CR_16_1),
-	PINMUX_DATA(HDMI_CEC_MARK,		PORT211_FN1),
-
-	/* SDENC */
-	PINMUX_DATA(SDENC_CPG_MARK,				MSEL4CR_19_0),
-	PINMUX_DATA(SDENC_DV_CLKI_MARK,				MSEL4CR_19_1),
-
-	/* SYSC */
-	PINMUX_DATA(RESETP_PULLUP_MARK,				MSEL4CR_4_0),
-	PINMUX_DATA(RESETP_PLAIN_MARK,				MSEL4CR_4_1),
-
-	/* DEBUG */
-	PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK,			MSEL4CR_1_0),
-	PINMUX_DATA(EDEBGREQ_PULLUP_MARK,			MSEL4CR_1_1),
-
-	PINMUX_DATA(TRACEAUD_FROM_VIO_MARK,			MSEL5CR_30_0,	MSEL5CR_29_0),
-	PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK,			MSEL5CR_30_0,	MSEL5CR_29_1),
-	PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK,			MSEL5CR_30_1,	MSEL5CR_29_0),
-};
-
-#define __I		(SH_PFC_PIN_CFG_INPUT)
-#define __O		(SH_PFC_PIN_CFG_OUTPUT)
-#define __IO		(SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
-#define __PD		(SH_PFC_PIN_CFG_PULL_DOWN)
-#define __PU		(SH_PFC_PIN_CFG_PULL_UP)
-#define __PUD		(SH_PFC_PIN_CFG_PULL_UP_DOWN)
-
-#define R8A7740_PIN_I_PD(pin)		SH_PFC_PIN_CFG(pin, __I | __PD)
-#define R8A7740_PIN_I_PU(pin)		SH_PFC_PIN_CFG(pin, __I | __PU)
-#define R8A7740_PIN_I_PU_PD(pin)	SH_PFC_PIN_CFG(pin, __I | __PUD)
-#define R8A7740_PIN_IO(pin)		SH_PFC_PIN_CFG(pin, __IO)
-#define R8A7740_PIN_IO_PD(pin)		SH_PFC_PIN_CFG(pin, __IO | __PD)
-#define R8A7740_PIN_IO_PU(pin)		SH_PFC_PIN_CFG(pin, __IO | __PU)
-#define R8A7740_PIN_IO_PU_PD(pin)	SH_PFC_PIN_CFG(pin, __IO | __PUD)
-#define R8A7740_PIN_O(pin)		SH_PFC_PIN_CFG(pin, __O)
-#define R8A7740_PIN_O_PU_PD(pin)	SH_PFC_PIN_CFG(pin, __O | __PUD)
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	/* Table 56-1 (I/O and Pull U/D) */
-	R8A7740_PIN_IO_PD(0),		R8A7740_PIN_IO_PD(1),
-	R8A7740_PIN_IO_PD(2),		R8A7740_PIN_IO_PD(3),
-	R8A7740_PIN_IO_PD(4),		R8A7740_PIN_IO_PD(5),
-	R8A7740_PIN_IO_PD(6),		R8A7740_PIN_IO(7),
-	R8A7740_PIN_IO(8),		R8A7740_PIN_IO(9),
-	R8A7740_PIN_IO_PD(10),		R8A7740_PIN_IO_PD(11),
-	R8A7740_PIN_IO_PD(12),		R8A7740_PIN_IO_PU_PD(13),
-	R8A7740_PIN_IO_PD(14),		R8A7740_PIN_IO_PD(15),
-	R8A7740_PIN_IO_PD(16),		R8A7740_PIN_IO_PD(17),
-	R8A7740_PIN_IO(18),		R8A7740_PIN_IO_PU(19),
-	R8A7740_PIN_IO_PU_PD(20),	R8A7740_PIN_IO_PD(21),
-	R8A7740_PIN_IO_PU_PD(22),	R8A7740_PIN_IO(23),
-	R8A7740_PIN_IO_PU(24),		R8A7740_PIN_IO_PU(25),
-	R8A7740_PIN_IO_PU(26),		R8A7740_PIN_IO_PU(27),
-	R8A7740_PIN_IO_PU(28),		R8A7740_PIN_IO_PU(29),
-	R8A7740_PIN_IO_PU(30),		R8A7740_PIN_IO_PD(31),
-	R8A7740_PIN_IO_PD(32),		R8A7740_PIN_IO_PD(33),
-	R8A7740_PIN_IO_PD(34),		R8A7740_PIN_IO_PU(35),
-	R8A7740_PIN_IO_PU(36),		R8A7740_PIN_IO_PD(37),
-	R8A7740_PIN_IO_PU(38),		R8A7740_PIN_IO_PD(39),
-	R8A7740_PIN_IO_PU_PD(40),	R8A7740_PIN_IO_PD(41),
-	R8A7740_PIN_IO_PD(42),		R8A7740_PIN_IO_PU_PD(43),
-	R8A7740_PIN_IO_PU_PD(44),	R8A7740_PIN_IO_PU_PD(45),
-	R8A7740_PIN_IO_PU_PD(46),	R8A7740_PIN_IO_PU_PD(47),
-	R8A7740_PIN_IO_PU_PD(48),	R8A7740_PIN_IO_PU_PD(49),
-	R8A7740_PIN_IO_PU_PD(50),	R8A7740_PIN_IO_PD(51),
-	R8A7740_PIN_IO_PD(52),		R8A7740_PIN_IO_PD(53),
-	R8A7740_PIN_IO_PD(54),		R8A7740_PIN_IO_PU_PD(55),
-	R8A7740_PIN_IO_PU_PD(56),	R8A7740_PIN_IO_PU_PD(57),
-	R8A7740_PIN_IO_PU_PD(58),	R8A7740_PIN_IO_PU_PD(59),
-	R8A7740_PIN_IO_PU_PD(60),	R8A7740_PIN_IO_PD(61),
-	R8A7740_PIN_IO_PD(62),		R8A7740_PIN_IO_PD(63),
-	R8A7740_PIN_IO_PD(64),		R8A7740_PIN_IO_PD(65),
-	R8A7740_PIN_IO_PU_PD(66),	R8A7740_PIN_IO_PU_PD(67),
-	R8A7740_PIN_IO_PU_PD(68),	R8A7740_PIN_IO_PU_PD(69),
-	R8A7740_PIN_IO_PU_PD(70),	R8A7740_PIN_IO_PU_PD(71),
-	R8A7740_PIN_IO_PU_PD(72),	R8A7740_PIN_IO_PU_PD(73),
-	R8A7740_PIN_IO_PU_PD(74),	R8A7740_PIN_IO_PU_PD(75),
-	R8A7740_PIN_IO_PU_PD(76),	R8A7740_PIN_IO_PU_PD(77),
-	R8A7740_PIN_IO_PU_PD(78),	R8A7740_PIN_IO_PU_PD(79),
-	R8A7740_PIN_IO_PU_PD(80),	R8A7740_PIN_IO_PU_PD(81),
-	R8A7740_PIN_IO(82),		R8A7740_PIN_IO_PU_PD(83),
-	R8A7740_PIN_IO(84),		R8A7740_PIN_IO_PD(85),
-	R8A7740_PIN_IO_PD(86),		R8A7740_PIN_IO_PD(87),
-	R8A7740_PIN_IO_PD(88),		R8A7740_PIN_IO_PD(89),
-	R8A7740_PIN_IO_PD(90),		R8A7740_PIN_IO_PU_PD(91),
-	R8A7740_PIN_IO_PU_PD(92),	R8A7740_PIN_IO_PU_PD(93),
-	R8A7740_PIN_IO_PU_PD(94),	R8A7740_PIN_IO_PU_PD(95),
-	R8A7740_PIN_IO_PU_PD(96),	R8A7740_PIN_IO_PU_PD(97),
-	R8A7740_PIN_IO_PU_PD(98),	R8A7740_PIN_IO_PU_PD(99),
-	R8A7740_PIN_IO_PU_PD(100),	R8A7740_PIN_IO(101),
-	R8A7740_PIN_IO_PU(102),		R8A7740_PIN_IO_PU_PD(103),
-	R8A7740_PIN_IO_PU(104),		R8A7740_PIN_IO_PU(105),
-	R8A7740_PIN_IO_PU_PD(106),	R8A7740_PIN_IO(107),
-	R8A7740_PIN_IO(108),		R8A7740_PIN_IO(109),
-	R8A7740_PIN_IO(110),		R8A7740_PIN_IO(111),
-	R8A7740_PIN_IO(112),		R8A7740_PIN_IO(113),
-	R8A7740_PIN_IO_PU_PD(114),	R8A7740_PIN_IO(115),
-	R8A7740_PIN_IO_PD(116),		R8A7740_PIN_IO_PD(117),
-	R8A7740_PIN_IO_PD(118),		R8A7740_PIN_IO_PD(119),
-	R8A7740_PIN_IO_PD(120),		R8A7740_PIN_IO_PD(121),
-	R8A7740_PIN_IO_PD(122),		R8A7740_PIN_IO_PD(123),
-	R8A7740_PIN_IO_PD(124),		R8A7740_PIN_IO(125),
-	R8A7740_PIN_IO(126),		R8A7740_PIN_IO(127),
-	R8A7740_PIN_IO(128),		R8A7740_PIN_IO(129),
-	R8A7740_PIN_IO(130),		R8A7740_PIN_IO(131),
-	R8A7740_PIN_IO(132),		R8A7740_PIN_IO(133),
-	R8A7740_PIN_IO(134),		R8A7740_PIN_IO(135),
-	R8A7740_PIN_IO(136),		R8A7740_PIN_IO(137),
-	R8A7740_PIN_IO(138),		R8A7740_PIN_IO(139),
-	R8A7740_PIN_IO(140),		R8A7740_PIN_IO(141),
-	R8A7740_PIN_IO_PU(142),		R8A7740_PIN_IO_PU(143),
-	R8A7740_PIN_IO_PU(144),		R8A7740_PIN_IO_PU(145),
-	R8A7740_PIN_IO_PU(146),		R8A7740_PIN_IO_PU(147),
-	R8A7740_PIN_IO_PU(148),		R8A7740_PIN_IO_PU(149),
-	R8A7740_PIN_IO_PU(150),		R8A7740_PIN_IO_PU(151),
-	R8A7740_PIN_IO_PU(152),		R8A7740_PIN_IO_PU(153),
-	R8A7740_PIN_IO_PU(154),		R8A7740_PIN_IO_PU(155),
-	R8A7740_PIN_IO_PU(156),		R8A7740_PIN_IO_PU(157),
-	R8A7740_PIN_IO_PD(158),		R8A7740_PIN_IO_PD(159),
-	R8A7740_PIN_IO_PU_PD(160),	R8A7740_PIN_IO_PD(161),
-	R8A7740_PIN_IO_PD(162),		R8A7740_PIN_IO_PD(163),
-	R8A7740_PIN_IO_PD(164),		R8A7740_PIN_IO_PD(165),
-	R8A7740_PIN_IO_PU(166),		R8A7740_PIN_IO_PU(167),
-	R8A7740_PIN_IO_PU(168),		R8A7740_PIN_IO_PU(169),
-	R8A7740_PIN_IO_PU(170),		R8A7740_PIN_IO_PU(171),
-	R8A7740_PIN_IO_PD(172),		R8A7740_PIN_IO_PD(173),
-	R8A7740_PIN_IO_PD(174),		R8A7740_PIN_IO_PD(175),
-	R8A7740_PIN_IO_PU(176),		R8A7740_PIN_IO_PU_PD(177),
-	R8A7740_PIN_IO_PU(178),		R8A7740_PIN_IO_PD(179),
-	R8A7740_PIN_IO_PD(180),		R8A7740_PIN_IO_PU(181),
-	R8A7740_PIN_IO_PU(182),		R8A7740_PIN_IO(183),
-	R8A7740_PIN_IO_PD(184),		R8A7740_PIN_IO_PD(185),
-	R8A7740_PIN_IO_PD(186),		R8A7740_PIN_IO_PD(187),
-	R8A7740_PIN_IO_PD(188),		R8A7740_PIN_IO_PD(189),
-	R8A7740_PIN_IO_PD(190),		R8A7740_PIN_IO_PD(191),
-	R8A7740_PIN_IO_PD(192),		R8A7740_PIN_IO_PU_PD(193),
-	R8A7740_PIN_IO_PU_PD(194),	R8A7740_PIN_IO_PD(195),
-	R8A7740_PIN_IO_PU_PD(196),	R8A7740_PIN_IO_PD(197),
-	R8A7740_PIN_IO_PU_PD(198),	R8A7740_PIN_IO_PU_PD(199),
-	R8A7740_PIN_IO_PU_PD(200),	R8A7740_PIN_IO_PU(201),
-	R8A7740_PIN_IO_PU_PD(202),	R8A7740_PIN_IO(203),
-	R8A7740_PIN_IO_PU_PD(204),	R8A7740_PIN_IO_PU_PD(205),
-	R8A7740_PIN_IO_PU_PD(206),	R8A7740_PIN_IO_PU_PD(207),
-	R8A7740_PIN_IO_PU_PD(208),	R8A7740_PIN_IO_PD(209),
-	R8A7740_PIN_IO_PD(210),		R8A7740_PIN_IO_PD(211),
-};
-
-/* - BSC -------------------------------------------------------------------- */
-static const unsigned int bsc_data8_pins[] = {
-	/* D[0:7] */
-	157, 156, 155, 154, 153, 152, 151, 150,
-};
-static const unsigned int bsc_data8_mux[] = {
-	D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
-	D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
-};
-static const unsigned int bsc_data16_pins[] = {
-	/* D[0:15] */
-	157, 156, 155, 154, 153, 152, 151, 150,
-	149, 148, 147, 146, 145, 144, 143, 142,
-};
-static const unsigned int bsc_data16_mux[] = {
-	D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
-	D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
-	D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
-	D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
-};
-static const unsigned int bsc_data32_pins[] = {
-	/* D[0:31] */
-	157, 156, 155, 154, 153, 152, 151, 150,
-	149, 148, 147, 146, 145, 144, 143, 142,
-	171, 170, 169, 168, 167, 166, 173, 172,
-	165, 164, 163, 162, 161, 160, 159, 158,
-};
-static const unsigned int bsc_data32_mux[] = {
-	D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
-	D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
-	D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
-	D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
-	D16_MARK, D17_MARK, D18_MARK, D19_MARK,
-	D20_MARK, D21_MARK, D22_MARK, D23_MARK,
-	D24_MARK, D25_MARK, D26_MARK, D27_MARK,
-	D28_MARK, D29_MARK, D30_MARK, D31_MARK,
-};
-static const unsigned int bsc_cs0_pins[] = {
-	/* CS */
-	109,
-};
-static const unsigned int bsc_cs0_mux[] = {
-	CS0_MARK,
-};
-static const unsigned int bsc_cs2_pins[] = {
-	/* CS */
-	110,
-};
-static const unsigned int bsc_cs2_mux[] = {
-	CS2_MARK,
-};
-static const unsigned int bsc_cs4_pins[] = {
-	/* CS */
-	111,
-};
-static const unsigned int bsc_cs4_mux[] = {
-	CS4_MARK,
-};
-static const unsigned int bsc_cs5a_0_pins[] = {
-	/* CS */
-	105,
-};
-static const unsigned int bsc_cs5a_0_mux[] = {
-	CS5A_PORT105_MARK,
-};
-static const unsigned int bsc_cs5a_1_pins[] = {
-	/* CS */
-	19,
-};
-static const unsigned int bsc_cs5a_1_mux[] = {
-	CS5A_PORT19_MARK,
-};
-static const unsigned int bsc_cs5b_pins[] = {
-	/* CS */
-	103,
-};
-static const unsigned int bsc_cs5b_mux[] = {
-	CS5B_MARK,
-};
-static const unsigned int bsc_cs6a_pins[] = {
-	/* CS */
-	104,
-};
-static const unsigned int bsc_cs6a_mux[] = {
-	CS6A_MARK,
-};
-static const unsigned int bsc_rd_we8_pins[] = {
-	/* RD, WE[0] */
-	115, 113,
-};
-static const unsigned int bsc_rd_we8_mux[] = {
-	RD_FSC_MARK, WE0_FWE_MARK,
-};
-static const unsigned int bsc_rd_we16_pins[] = {
-	/* RD, WE[0:1] */
-	115, 113, 112,
-};
-static const unsigned int bsc_rd_we16_mux[] = {
-	RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
-};
-static const unsigned int bsc_rd_we32_pins[] = {
-	/* RD, WE[0:3] */
-	115, 113, 112, 108, 107,
-};
-static const unsigned int bsc_rd_we32_mux[] = {
-	RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
-};
-static const unsigned int bsc_bs_pins[] = {
-	/* BS */
-	175,
-};
-static const unsigned int bsc_bs_mux[] = {
-	BS_MARK,
-};
-static const unsigned int bsc_rdwr_pins[] = {
-	/* RDWR */
-	114,
-};
-static const unsigned int bsc_rdwr_mux[] = {
-	RDWR_MARK,
-};
-/* - CEU0 ------------------------------------------------------------------- */
-static const unsigned int ceu0_data_0_7_pins[] = {
-	/* D[0:7] */
-	34, 33, 32, 31, 30, 29, 28, 27,
-};
-static const unsigned int ceu0_data_0_7_mux[] = {
-	VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
-	VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
-};
-static const unsigned int ceu0_data_8_15_0_pins[] = {
-	/* D[8:15] */
-	182, 181, 180, 179, 178, 26, 25, 24,
-};
-static const unsigned int ceu0_data_8_15_0_mux[] = {
-	VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
-	VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK,
-	VIO0_D15_PORT24_MARK,
-};
-static const unsigned int ceu0_data_8_15_1_pins[] = {
-	/* D[8:15] */
-	182, 181, 180, 179, 178, 22, 95, 96,
-};
-static const unsigned int ceu0_data_8_15_1_mux[] = {
-	VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
-	VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK,
-	VIO0_D15_PORT96_MARK,
-};
-static const unsigned int ceu0_clk_0_pins[] = {
-	/* CKO */
-	36,
-};
-static const unsigned int ceu0_clk_0_mux[] = {
-	VIO_CKO_MARK,
-};
-static const unsigned int ceu0_clk_1_pins[] = {
-	/* CKO */
-	14,
-};
-static const unsigned int ceu0_clk_1_mux[] = {
-	VIO_CKO1_MARK,
-};
-static const unsigned int ceu0_clk_2_pins[] = {
-	/* CKO */
-	15,
-};
-static const unsigned int ceu0_clk_2_mux[] = {
-	VIO_CKO2_MARK,
-};
-static const unsigned int ceu0_sync_pins[] = {
-	/* CLK, VD, HD */
-	35, 39, 37,
-};
-static const unsigned int ceu0_sync_mux[] = {
-	VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK,
-};
-static const unsigned int ceu0_field_pins[] = {
-	/* FIELD */
-	38,
-};
-static const unsigned int ceu0_field_mux[] = {
-	VIO0_FIELD_MARK,
-};
-/* - CEU1 ------------------------------------------------------------------- */
-static const unsigned int ceu1_data_pins[] = {
-	/* D[0:7] */
-	182, 181, 180, 179, 178, 26, 25, 24,
-};
-static const unsigned int ceu1_data_mux[] = {
-	VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
-	VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
-};
-static const unsigned int ceu1_clk_pins[] = {
-	/* CKO */
-	23,
-};
-static const unsigned int ceu1_clk_mux[] = {
-	VIO_CKO_1_MARK,
-};
-static const unsigned int ceu1_sync_pins[] = {
-	/* CLK, VD, HD */
-	197, 198, 160,
-};
-static const unsigned int ceu1_sync_mux[] = {
-	VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK,
-};
-static const unsigned int ceu1_field_pins[] = {
-	/* FIELD */
-	21,
-};
-static const unsigned int ceu1_field_mux[] = {
-	VIO1_FIELD_MARK,
-};
-/* - FSIA ------------------------------------------------------------------- */
-static const unsigned int fsia_mclk_in_pins[] = {
-	/* CK */
-	11,
-};
-static const unsigned int fsia_mclk_in_mux[] = {
-	FSIACK_MARK,
-};
-static const unsigned int fsia_mclk_out_pins[] = {
-	/* OMC */
-	10,
-};
-static const unsigned int fsia_mclk_out_mux[] = {
-	FSIAOMC_MARK,
-};
-static const unsigned int fsia_sclk_in_pins[] = {
-	/* ILR, IBT */
-	12, 13,
-};
-static const unsigned int fsia_sclk_in_mux[] = {
-	FSIAILR_MARK, FSIAIBT_MARK,
-};
-static const unsigned int fsia_sclk_out_pins[] = {
-	/* OLR, OBT */
-	7, 8,
-};
-static const unsigned int fsia_sclk_out_mux[] = {
-	FSIAOLR_MARK, FSIAOBT_MARK,
-};
-static const unsigned int fsia_data_in_0_pins[] = {
-	/* ISLD */
-	0,
-};
-static const unsigned int fsia_data_in_0_mux[] = {
-	FSIAISLD_PORT0_MARK,
-};
-static const unsigned int fsia_data_in_1_pins[] = {
-	/* ISLD */
-	5,
-};
-static const unsigned int fsia_data_in_1_mux[] = {
-	FSIAISLD_PORT5_MARK,
-};
-static const unsigned int fsia_data_out_0_pins[] = {
-	/* OSLD */
-	9,
-};
-static const unsigned int fsia_data_out_0_mux[] = {
-	FSIAOSLD_MARK,
-};
-static const unsigned int fsia_data_out_1_pins[] = {
-	/* OSLD */
-	0,
-};
-static const unsigned int fsia_data_out_1_mux[] = {
-	FSIAOSLD1_MARK,
-};
-static const unsigned int fsia_data_out_2_pins[] = {
-	/* OSLD */
-	1,
-};
-static const unsigned int fsia_data_out_2_mux[] = {
-	FSIAOSLD2_MARK,
-};
-static const unsigned int fsia_spdif_0_pins[] = {
-	/* SPDIF */
-	9,
-};
-static const unsigned int fsia_spdif_0_mux[] = {
-	FSIASPDIF_PORT9_MARK,
-};
-static const unsigned int fsia_spdif_1_pins[] = {
-	/* SPDIF */
-	18,
-};
-static const unsigned int fsia_spdif_1_mux[] = {
-	FSIASPDIF_PORT18_MARK,
-};
-/* - FSIB ------------------------------------------------------------------- */
-static const unsigned int fsib_mclk_in_pins[] = {
-	/* CK */
-	11,
-};
-static const unsigned int fsib_mclk_in_mux[] = {
-	FSIBCK_MARK,
-};
-/* - GETHER ----------------------------------------------------------------- */
-static const unsigned int gether_rmii_pins[] = {
-	/* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
-	195, 196, 194, 193, 200, 201, 199, 159, 202, 208,
-};
-static const unsigned int gether_rmii_mux[] = {
-	RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK,
-	RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK,
-	RMII_MDC_MARK, RMII_MDIO_MARK,
-};
-static const unsigned int gether_mii_pins[] = {
-	/* RXD[0:3], RX_CLK, RX_DV, RX_ER
-	 * TXD[0:3], TX_CLK, TX_EN, TX_ER
-	 * CRS, COL, MDC, MDIO,
-	 */
-	185, 186, 187, 188, 174, 161, 204,
-	171, 170, 169, 168, 184, 183, 203,
-	205, 163, 206, 207,
-};
-static const unsigned int gether_mii_mux[] = {
-	ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
-	ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
-	ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
-	ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
-	ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
-};
-static const unsigned int gether_gmii_pins[] = {
-	/* RXD[0:7], RX_CLK, RX_DV, RX_ER
-	 * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER
-	 * CRS, COL, MDC, MDIO, REF125CK_MARK,
-	 */
-	185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
-	171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
-	205, 163, 206, 207, 158,
-};
-static const unsigned int gether_gmii_mux[] = {
-	ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
-	ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK,
-	ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
-	ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
-	ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK,
-	ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
-	ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
-	RMII_REF125CK_MARK,
-};
-static const unsigned int gether_int_pins[] = {
-	/* PHY_INT */
-	164,
-};
-static const unsigned int gether_int_mux[] = {
-	ET_PHY_INT_MARK,
-};
-static const unsigned int gether_link_pins[] = {
-	/* LINK */
-	177,
-};
-static const unsigned int gether_link_mux[] = {
-	ET_LINK_MARK,
-};
-static const unsigned int gether_wol_pins[] = {
-	/* WOL */
-	175,
-};
-static const unsigned int gether_wol_mux[] = {
-	ET_WOL_MARK,
-};
-/* - HDMI ------------------------------------------------------------------- */
-static const unsigned int hdmi_pins[] = {
-	/* HPD, CEC */
-	210, 211,
-};
-static const unsigned int hdmi_mux[] = {
-	HDMI_HPD_MARK, HDMI_CEC_MARK,
-};
-/* - INTC ------------------------------------------------------------------- */
-IRQC_PINS_MUX(0, 0, 2);
-IRQC_PINS_MUX(0, 1, 13);
-IRQC_PIN_MUX(1, 20);
-IRQC_PINS_MUX(2, 0, 11);
-IRQC_PINS_MUX(2, 1, 12);
-IRQC_PINS_MUX(3, 0, 10);
-IRQC_PINS_MUX(3, 1, 14);
-IRQC_PINS_MUX(4, 0, 15);
-IRQC_PINS_MUX(4, 1, 172);
-IRQC_PINS_MUX(5, 0, 0);
-IRQC_PINS_MUX(5, 1, 1);
-IRQC_PINS_MUX(6, 0, 121);
-IRQC_PINS_MUX(6, 1, 173);
-IRQC_PINS_MUX(7, 0, 120);
-IRQC_PINS_MUX(7, 1, 209);
-IRQC_PIN_MUX(8, 119);
-IRQC_PINS_MUX(9, 0, 118);
-IRQC_PINS_MUX(9, 1, 210);
-IRQC_PIN_MUX(10, 19);
-IRQC_PIN_MUX(11, 104);
-IRQC_PINS_MUX(12, 0, 42);
-IRQC_PINS_MUX(12, 1, 97);
-IRQC_PINS_MUX(13, 0, 64);
-IRQC_PINS_MUX(13, 1, 98);
-IRQC_PINS_MUX(14, 0, 63);
-IRQC_PINS_MUX(14, 1, 99);
-IRQC_PINS_MUX(15, 0, 62);
-IRQC_PINS_MUX(15, 1, 100);
-IRQC_PINS_MUX(16, 0, 68);
-IRQC_PINS_MUX(16, 1, 211);
-IRQC_PIN_MUX(17, 69);
-IRQC_PIN_MUX(18, 70);
-IRQC_PIN_MUX(19, 71);
-IRQC_PIN_MUX(20, 67);
-IRQC_PIN_MUX(21, 202);
-IRQC_PIN_MUX(22, 95);
-IRQC_PIN_MUX(23, 96);
-IRQC_PIN_MUX(24, 180);
-IRQC_PIN_MUX(25, 38);
-IRQC_PINS_MUX(26, 0, 58);
-IRQC_PINS_MUX(26, 1, 81);
-IRQC_PINS_MUX(27, 0, 57);
-IRQC_PINS_MUX(27, 1, 168);
-IRQC_PINS_MUX(28, 0, 56);
-IRQC_PINS_MUX(28, 1, 169);
-IRQC_PINS_MUX(29, 0, 50);
-IRQC_PINS_MUX(29, 1, 170);
-IRQC_PINS_MUX(30, 0, 49);
-IRQC_PINS_MUX(30, 1, 171);
-IRQC_PINS_MUX(31, 0, 41);
-IRQC_PINS_MUX(31, 1, 167);
-
-/* - LCD0 ------------------------------------------------------------------- */
-static const unsigned int lcd0_data8_pins[] = {
-	/* D[0:7] */
-	58, 57, 56, 55, 54, 53, 52, 51,
-};
-static const unsigned int lcd0_data8_mux[] = {
-	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
-	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
-};
-static const unsigned int lcd0_data9_pins[] = {
-	/* D[0:8] */
-	58, 57, 56, 55, 54, 53, 52, 51,
-	50,
-};
-static const unsigned int lcd0_data9_mux[] = {
-	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
-	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
-	LCD0_D8_MARK,
-};
-static const unsigned int lcd0_data12_pins[] = {
-	/* D[0:11] */
-	58, 57, 56, 55, 54, 53, 52, 51,
-	50, 49, 48, 47,
-};
-static const unsigned int lcd0_data12_mux[] = {
-	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
-	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
-	LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
-};
-static const unsigned int lcd0_data16_pins[] = {
-	/* D[0:15] */
-	58, 57, 56, 55, 54, 53, 52, 51,
-	50, 49, 48, 47, 46, 45, 44, 43,
-};
-static const unsigned int lcd0_data16_mux[] = {
-	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
-	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
-	LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
-	LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
-};
-static const unsigned int lcd0_data18_pins[] = {
-	/* D[0:17] */
-	58, 57, 56, 55, 54, 53, 52, 51,
-	50, 49, 48, 47, 46, 45, 44, 43,
-	42, 41,
-};
-static const unsigned int lcd0_data18_mux[] = {
-	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
-	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
-	LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
-	LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
-	LCD0_D16_MARK, LCD0_D17_MARK,
-};
-static const unsigned int lcd0_data24_0_pins[] = {
-	/* D[0:23] */
-	58, 57, 56, 55, 54, 53, 52, 51,
-	50, 49, 48, 47, 46, 45, 44, 43,
-	42, 41, 40, 4, 3, 2, 0, 1,
-};
-static const unsigned int lcd0_data24_0_mux[] = {
-	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
-	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
-	LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
-	LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
-	LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
-	LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
-	LCD0_D23_PORT1_MARK,
-};
-static const unsigned int lcd0_data24_1_pins[] = {
-	/* D[0:23] */
-	58, 57, 56, 55, 54, 53, 52, 51,
-	50, 49, 48, 47, 46, 45, 44, 43,
-	42, 41, 163, 162, 161, 158, 160, 159,
-};
-static const unsigned int lcd0_data24_1_mux[] = {
-	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
-	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
-	LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
-	LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
-	LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
-	LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
-	LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
-};
-static const unsigned int lcd0_display_pins[] = {
-	/* DON, VCPWC, VEPWC */
-	61, 59, 60,
-};
-static const unsigned int lcd0_display_mux[] = {
-	LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
-};
-static const unsigned int lcd0_lclk_0_pins[] = {
-	/* LCLK */
-	102,
-};
-static const unsigned int lcd0_lclk_0_mux[] = {
-	LCD0_LCLK_PORT102_MARK,
-};
-static const unsigned int lcd0_lclk_1_pins[] = {
-	/* LCLK */
-	165,
-};
-static const unsigned int lcd0_lclk_1_mux[] = {
-	LCD0_LCLK_PORT165_MARK,
-};
-static const unsigned int lcd0_sync_pins[] = {
-	/* VSYN, HSYN, DCK, DISP */
-	63, 64, 62, 65,
-};
-static const unsigned int lcd0_sync_mux[] = {
-	LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
-};
-static const unsigned int lcd0_sys_pins[] = {
-	/* CS, WR, RD, RS */
-	64, 62, 164, 65,
-};
-static const unsigned int lcd0_sys_mux[] = {
-	LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
-};
-/* - LCD1 ------------------------------------------------------------------- */
-static const unsigned int lcd1_data8_pins[] = {
-	/* D[0:7] */
-	4, 3, 2, 1, 0, 91, 92, 23,
-};
-static const unsigned int lcd1_data8_mux[] = {
-	LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
-	LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
-};
-static const unsigned int lcd1_data9_pins[] = {
-	/* D[0:8] */
-	4, 3, 2, 1, 0, 91, 92, 23,
-	93,
-};
-static const unsigned int lcd1_data9_mux[] = {
-	LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
-	LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
-	LCD1_D8_MARK,
-};
-static const unsigned int lcd1_data12_pins[] = {
-	/* D[0:11] */
-	4, 3, 2, 1, 0, 91, 92, 23,
-	93, 94, 21, 201,
-};
-static const unsigned int lcd1_data12_mux[] = {
-	LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
-	LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
-	LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
-};
-static const unsigned int lcd1_data16_pins[] = {
-	/* D[0:15] */
-	4, 3, 2, 1, 0, 91, 92, 23,
-	93, 94, 21, 201, 200, 199, 196, 195,
-};
-static const unsigned int lcd1_data16_mux[] = {
-	LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
-	LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
-	LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
-	LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
-};
-static const unsigned int lcd1_data18_pins[] = {
-	/* D[0:17] */
-	4, 3, 2, 1, 0, 91, 92, 23,
-	93, 94, 21, 201, 200, 199, 196, 195,
-	194, 193,
-};
-static const unsigned int lcd1_data18_mux[] = {
-	LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
-	LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
-	LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
-	LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
-	LCD1_D16_MARK, LCD1_D17_MARK,
-};
-static const unsigned int lcd1_data24_pins[] = {
-	/* D[0:23] */
-	4, 3, 2, 1, 0, 91, 92, 23,
-	93, 94, 21, 201, 200, 199, 196, 195,
-	194, 193, 198, 197, 75, 74, 15, 14,
-};
-static const unsigned int lcd1_data24_mux[] = {
-	LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
-	LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
-	LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
-	LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
-	LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
-	LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
-};
-static const unsigned int lcd1_display_pins[] = {
-	/* DON, VCPWC, VEPWC */
-	100, 5, 6,
-};
-static const unsigned int lcd1_display_mux[] = {
-	LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
-};
-static const unsigned int lcd1_lclk_pins[] = {
-	/* LCLK */
-	40,
-};
-static const unsigned int lcd1_lclk_mux[] = {
-	LCD1_LCLK_MARK,
-};
-static const unsigned int lcd1_sync_pins[] = {
-	/* VSYN, HSYN, DCK, DISP */
-	98, 97, 99, 12,
-};
-static const unsigned int lcd1_sync_mux[] = {
-	LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
-};
-static const unsigned int lcd1_sys_pins[] = {
-	/* CS, WR, RD, RS */
-	97, 99, 13, 12,
-};
-static const unsigned int lcd1_sys_mux[] = {
-	LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
-};
-/* - MMCIF ------------------------------------------------------------------ */
-static const unsigned int mmc0_data1_0_pins[] = {
-	/* D[0] */
-	68,
-};
-static const unsigned int mmc0_data1_0_mux[] = {
-	MMC0_D0_PORT68_MARK,
-};
-static const unsigned int mmc0_data4_0_pins[] = {
-	/* D[0:3] */
-	68, 69, 70, 71,
-};
-static const unsigned int mmc0_data4_0_mux[] = {
-	MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
-};
-static const unsigned int mmc0_data8_0_pins[] = {
-	/* D[0:7] */
-	68, 69, 70, 71, 72, 73, 74, 75,
-};
-static const unsigned int mmc0_data8_0_mux[] = {
-	MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
-	MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
-};
-static const unsigned int mmc0_ctrl_0_pins[] = {
-	/* CMD, CLK */
-	67, 66,
-};
-static const unsigned int mmc0_ctrl_0_mux[] = {
-	MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
-};
-
-static const unsigned int mmc0_data1_1_pins[] = {
-	/* D[0] */
-	149,
-};
-static const unsigned int mmc0_data1_1_mux[] = {
-	MMC1_D0_PORT149_MARK,
-};
-static const unsigned int mmc0_data4_1_pins[] = {
-	/* D[0:3] */
-	149, 148, 147, 146,
-};
-static const unsigned int mmc0_data4_1_mux[] = {
-	MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
-};
-static const unsigned int mmc0_data8_1_pins[] = {
-	/* D[0:7] */
-	149, 148, 147, 146, 145, 144, 143, 142,
-};
-static const unsigned int mmc0_data8_1_mux[] = {
-	MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
-	MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
-};
-static const unsigned int mmc0_ctrl_1_pins[] = {
-	/* CMD, CLK */
-	104, 103,
-};
-static const unsigned int mmc0_ctrl_1_mux[] = {
-	MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
-};
-/* - SCIFA0 ----------------------------------------------------------------- */
-static const unsigned int scifa0_data_pins[] = {
-	/* RXD, TXD */
-	197, 198,
-};
-static const unsigned int scifa0_data_mux[] = {
-	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
-};
-static const unsigned int scifa0_clk_pins[] = {
-	/* SCK */
-	188,
-};
-static const unsigned int scifa0_clk_mux[] = {
-	SCIFA0_SCK_MARK,
-};
-static const unsigned int scifa0_ctrl_pins[] = {
-	/* RTS, CTS */
-	194, 193,
-};
-static const unsigned int scifa0_ctrl_mux[] = {
-	SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
-};
-/* - SCIFA1 ----------------------------------------------------------------- */
-static const unsigned int scifa1_data_pins[] = {
-	/* RXD, TXD */
-	195, 196,
-};
-static const unsigned int scifa1_data_mux[] = {
-	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
-};
-static const unsigned int scifa1_clk_pins[] = {
-	/* SCK */
-	185,
-};
-static const unsigned int scifa1_clk_mux[] = {
-	SCIFA1_SCK_MARK,
-};
-static const unsigned int scifa1_ctrl_pins[] = {
-	/* RTS, CTS */
-	23, 21,
-};
-static const unsigned int scifa1_ctrl_mux[] = {
-	SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
-};
-/* - SCIFA2 ----------------------------------------------------------------- */
-static const unsigned int scifa2_data_pins[] = {
-	/* RXD, TXD */
-	200, 201,
-};
-static const unsigned int scifa2_data_mux[] = {
-	SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
-};
-static const unsigned int scifa2_clk_0_pins[] = {
-	/* SCK */
-	22,
-};
-static const unsigned int scifa2_clk_0_mux[] = {
-	SCIFA2_SCK_PORT22_MARK,
-};
-static const unsigned int scifa2_clk_1_pins[] = {
-	/* SCK */
-	199,
-};
-static const unsigned int scifa2_clk_1_mux[] = {
-	SCIFA2_SCK_PORT199_MARK,
-};
-static const unsigned int scifa2_ctrl_pins[] = {
-	/* RTS, CTS */
-	96, 95,
-};
-static const unsigned int scifa2_ctrl_mux[] = {
-	SCIFA2_RTS_MARK, SCIFA2_CTS_MARK,
-};
-/* - SCIFA3 ----------------------------------------------------------------- */
-static const unsigned int scifa3_data_0_pins[] = {
-	/* RXD, TXD */
-	174, 175,
-};
-static const unsigned int scifa3_data_0_mux[] = {
-	SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK,
-};
-static const unsigned int scifa3_clk_0_pins[] = {
-	/* SCK */
-	116,
-};
-static const unsigned int scifa3_clk_0_mux[] = {
-	SCIFA3_SCK_PORT116_MARK,
-};
-static const unsigned int scifa3_ctrl_0_pins[] = {
-	/* RTS, CTS */
-	105, 117,
-};
-static const unsigned int scifa3_ctrl_0_mux[] = {
-	SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK,
-};
-static const unsigned int scifa3_data_1_pins[] = {
-	/* RXD, TXD */
-	159, 160,
-};
-static const unsigned int scifa3_data_1_mux[] = {
-	SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK,
-};
-static const unsigned int scifa3_clk_1_pins[] = {
-	/* SCK */
-	158,
-};
-static const unsigned int scifa3_clk_1_mux[] = {
-	SCIFA3_SCK_PORT158_MARK,
-};
-static const unsigned int scifa3_ctrl_1_pins[] = {
-	/* RTS, CTS */
-	161, 162,
-};
-static const unsigned int scifa3_ctrl_1_mux[] = {
-	SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK,
-};
-/* - SCIFA4 ----------------------------------------------------------------- */
-static const unsigned int scifa4_data_0_pins[] = {
-	/* RXD, TXD */
-	12, 13,
-};
-static const unsigned int scifa4_data_0_mux[] = {
-	SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK,
-};
-static const unsigned int scifa4_data_1_pins[] = {
-	/* RXD, TXD */
-	204, 203,
-};
-static const unsigned int scifa4_data_1_mux[] = {
-	SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK,
-};
-static const unsigned int scifa4_data_2_pins[] = {
-	/* RXD, TXD */
-	94, 93,
-};
-static const unsigned int scifa4_data_2_mux[] = {
-	SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK,
-};
-static const unsigned int scifa4_clk_0_pins[] = {
-	/* SCK */
-	21,
-};
-static const unsigned int scifa4_clk_0_mux[] = {
-	SCIFA4_SCK_PORT21_MARK,
-};
-static const unsigned int scifa4_clk_1_pins[] = {
-	/* SCK */
-	205,
-};
-static const unsigned int scifa4_clk_1_mux[] = {
-	SCIFA4_SCK_PORT205_MARK,
-};
-/* - SCIFA5 ----------------------------------------------------------------- */
-static const unsigned int scifa5_data_0_pins[] = {
-	/* RXD, TXD */
-	10, 20,
-};
-static const unsigned int scifa5_data_0_mux[] = {
-	SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK,
-};
-static const unsigned int scifa5_data_1_pins[] = {
-	/* RXD, TXD */
-	207, 208,
-};
-static const unsigned int scifa5_data_1_mux[] = {
-	SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK,
-};
-static const unsigned int scifa5_data_2_pins[] = {
-	/* RXD, TXD */
-	92, 91,
-};
-static const unsigned int scifa5_data_2_mux[] = {
-	SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK,
-};
-static const unsigned int scifa5_clk_0_pins[] = {
-	/* SCK */
-	23,
-};
-static const unsigned int scifa5_clk_0_mux[] = {
-	SCIFA5_SCK_PORT23_MARK,
-};
-static const unsigned int scifa5_clk_1_pins[] = {
-	/* SCK */
-	206,
-};
-static const unsigned int scifa5_clk_1_mux[] = {
-	SCIFA5_SCK_PORT206_MARK,
-};
-/* - SCIFA6 ----------------------------------------------------------------- */
-static const unsigned int scifa6_data_pins[] = {
-	/* RXD, TXD */
-	25, 26,
-};
-static const unsigned int scifa6_data_mux[] = {
-	SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
-};
-static const unsigned int scifa6_clk_pins[] = {
-	/* SCK */
-	24,
-};
-static const unsigned int scifa6_clk_mux[] = {
-	SCIFA6_SCK_MARK,
-};
-/* - SCIFA7 ----------------------------------------------------------------- */
-static const unsigned int scifa7_data_pins[] = {
-	/* RXD, TXD */
-	0, 1,
-};
-static const unsigned int scifa7_data_mux[] = {
-	SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
-};
-/* - SCIFB ------------------------------------------------------------------ */
-static const unsigned int scifb_data_0_pins[] = {
-	/* RXD, TXD */
-	191, 192,
-};
-static const unsigned int scifb_data_0_mux[] = {
-	SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK,
-};
-static const unsigned int scifb_clk_0_pins[] = {
-	/* SCK */
-	190,
-};
-static const unsigned int scifb_clk_0_mux[] = {
-	SCIFB_SCK_PORT190_MARK,
-};
-static const unsigned int scifb_ctrl_0_pins[] = {
-	/* RTS, CTS */
-	186, 187,
-};
-static const unsigned int scifb_ctrl_0_mux[] = {
-	SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK,
-};
-static const unsigned int scifb_data_1_pins[] = {
-	/* RXD, TXD */
-	3, 4,
-};
-static const unsigned int scifb_data_1_mux[] = {
-	SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK,
-};
-static const unsigned int scifb_clk_1_pins[] = {
-	/* SCK */
-	2,
-};
-static const unsigned int scifb_clk_1_mux[] = {
-	SCIFB_SCK_PORT2_MARK,
-};
-static const unsigned int scifb_ctrl_1_pins[] = {
-	/* RTS, CTS */
-	172, 173,
-};
-static const unsigned int scifb_ctrl_1_mux[] = {
-	SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
-};
-/* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
-	/* D0 */
-	77,
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SDHI0_D0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
-	/* D[0:3] */
-	77, 78, 79, 80,
-};
-static const unsigned int sdhi0_data4_mux[] = {
-	SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
-};
-static const unsigned int sdhi0_ctrl_pins[] = {
-	/* CMD, CLK */
-	76, 82,
-};
-static const unsigned int sdhi0_ctrl_mux[] = {
-	SDHI0_CMD_MARK, SDHI0_CLK_MARK,
-};
-static const unsigned int sdhi0_cd_pins[] = {
-	/* CD */
-	81,
-};
-static const unsigned int sdhi0_cd_mux[] = {
-	SDHI0_CD_MARK,
-};
-static const unsigned int sdhi0_wp_pins[] = {
-	/* WP */
-	83,
-};
-static const unsigned int sdhi0_wp_mux[] = {
-	SDHI0_WP_MARK,
-};
-/* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
-	/* D0 */
-	68,
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	SDHI1_D0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
-	/* D[0:3] */
-	68, 69, 70, 71,
-};
-static const unsigned int sdhi1_data4_mux[] = {
-	SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
-};
-static const unsigned int sdhi1_ctrl_pins[] = {
-	/* CMD, CLK */
-	67, 66,
-};
-static const unsigned int sdhi1_ctrl_mux[] = {
-	SDHI1_CMD_MARK, SDHI1_CLK_MARK,
-};
-static const unsigned int sdhi1_cd_pins[] = {
-	/* CD */
-	72,
-};
-static const unsigned int sdhi1_cd_mux[] = {
-	SDHI1_CD_MARK,
-};
-static const unsigned int sdhi1_wp_pins[] = {
-	/* WP */
-	73,
-};
-static const unsigned int sdhi1_wp_mux[] = {
-	SDHI1_WP_MARK,
-};
-/* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
-	/* D0 */
-	205,
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SDHI2_D0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
-	/* D[0:3] */
-	205, 206, 207, 208,
-};
-static const unsigned int sdhi2_data4_mux[] = {
-	SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
-};
-static const unsigned int sdhi2_ctrl_pins[] = {
-	/* CMD, CLK */
-	204, 203,
-};
-static const unsigned int sdhi2_ctrl_mux[] = {
-	SDHI2_CMD_MARK, SDHI2_CLK_MARK,
-};
-static const unsigned int sdhi2_cd_0_pins[] = {
-	/* CD */
-	202,
-};
-static const unsigned int sdhi2_cd_0_mux[] = {
-	SDHI2_CD_PORT202_MARK,
-};
-static const unsigned int sdhi2_wp_0_pins[] = {
-	/* WP */
-	177,
-};
-static const unsigned int sdhi2_wp_0_mux[] = {
-	SDHI2_WP_PORT177_MARK,
-};
-static const unsigned int sdhi2_cd_1_pins[] = {
-	/* CD */
-	24,
-};
-static const unsigned int sdhi2_cd_1_mux[] = {
-	SDHI2_CD_PORT24_MARK,
-};
-static const unsigned int sdhi2_wp_1_pins[] = {
-	/* WP */
-	25,
-};
-static const unsigned int sdhi2_wp_1_mux[] = {
-	SDHI2_WP_PORT25_MARK,
-};
-/* - TPU0 ------------------------------------------------------------------- */
-static const unsigned int tpu0_to0_pins[] = {
-	/* TO */
-	23,
-};
-static const unsigned int tpu0_to0_mux[] = {
-	TPU0TO0_MARK,
-};
-static const unsigned int tpu0_to1_pins[] = {
-	/* TO */
-	21,
-};
-static const unsigned int tpu0_to1_mux[] = {
-	TPU0TO1_MARK,
-};
-static const unsigned int tpu0_to2_0_pins[] = {
-	/* TO */
-	66,
-};
-static const unsigned int tpu0_to2_0_mux[] = {
-	TPU0TO2_PORT66_MARK,
-};
-static const unsigned int tpu0_to2_1_pins[] = {
-	/* TO */
-	202,
-};
-static const unsigned int tpu0_to2_1_mux[] = {
-	TPU0TO2_PORT202_MARK,
-};
-static const unsigned int tpu0_to3_pins[] = {
-	/* TO */
-	180,
-};
-static const unsigned int tpu0_to3_mux[] = {
-	TPU0TO3_MARK,
-};
-
-static const struct sh_pfc_pin_group pinmux_groups[] = {
-	SH_PFC_PIN_GROUP(bsc_data8),
-	SH_PFC_PIN_GROUP(bsc_data16),
-	SH_PFC_PIN_GROUP(bsc_data32),
-	SH_PFC_PIN_GROUP(bsc_cs0),
-	SH_PFC_PIN_GROUP(bsc_cs2),
-	SH_PFC_PIN_GROUP(bsc_cs4),
-	SH_PFC_PIN_GROUP(bsc_cs5a_0),
-	SH_PFC_PIN_GROUP(bsc_cs5a_1),
-	SH_PFC_PIN_GROUP(bsc_cs5b),
-	SH_PFC_PIN_GROUP(bsc_cs6a),
-	SH_PFC_PIN_GROUP(bsc_rd_we8),
-	SH_PFC_PIN_GROUP(bsc_rd_we16),
-	SH_PFC_PIN_GROUP(bsc_rd_we32),
-	SH_PFC_PIN_GROUP(bsc_bs),
-	SH_PFC_PIN_GROUP(bsc_rdwr),
-	SH_PFC_PIN_GROUP(ceu0_data_0_7),
-	SH_PFC_PIN_GROUP(ceu0_data_8_15_0),
-	SH_PFC_PIN_GROUP(ceu0_data_8_15_1),
-	SH_PFC_PIN_GROUP(ceu0_clk_0),
-	SH_PFC_PIN_GROUP(ceu0_clk_1),
-	SH_PFC_PIN_GROUP(ceu0_clk_2),
-	SH_PFC_PIN_GROUP(ceu0_sync),
-	SH_PFC_PIN_GROUP(ceu0_field),
-	SH_PFC_PIN_GROUP(ceu1_data),
-	SH_PFC_PIN_GROUP(ceu1_clk),
-	SH_PFC_PIN_GROUP(ceu1_sync),
-	SH_PFC_PIN_GROUP(ceu1_field),
-	SH_PFC_PIN_GROUP(fsia_mclk_in),
-	SH_PFC_PIN_GROUP(fsia_mclk_out),
-	SH_PFC_PIN_GROUP(fsia_sclk_in),
-	SH_PFC_PIN_GROUP(fsia_sclk_out),
-	SH_PFC_PIN_GROUP(fsia_data_in_0),
-	SH_PFC_PIN_GROUP(fsia_data_in_1),
-	SH_PFC_PIN_GROUP(fsia_data_out_0),
-	SH_PFC_PIN_GROUP(fsia_data_out_1),
-	SH_PFC_PIN_GROUP(fsia_data_out_2),
-	SH_PFC_PIN_GROUP(fsia_spdif_0),
-	SH_PFC_PIN_GROUP(fsia_spdif_1),
-	SH_PFC_PIN_GROUP(fsib_mclk_in),
-	SH_PFC_PIN_GROUP(gether_rmii),
-	SH_PFC_PIN_GROUP(gether_mii),
-	SH_PFC_PIN_GROUP(gether_gmii),
-	SH_PFC_PIN_GROUP(gether_int),
-	SH_PFC_PIN_GROUP(gether_link),
-	SH_PFC_PIN_GROUP(gether_wol),
-	SH_PFC_PIN_GROUP(hdmi),
-	SH_PFC_PIN_GROUP(intc_irq0_0),
-	SH_PFC_PIN_GROUP(intc_irq0_1),
-	SH_PFC_PIN_GROUP(intc_irq1),
-	SH_PFC_PIN_GROUP(intc_irq2_0),
-	SH_PFC_PIN_GROUP(intc_irq2_1),
-	SH_PFC_PIN_GROUP(intc_irq3_0),
-	SH_PFC_PIN_GROUP(intc_irq3_1),
-	SH_PFC_PIN_GROUP(intc_irq4_0),
-	SH_PFC_PIN_GROUP(intc_irq4_1),
-	SH_PFC_PIN_GROUP(intc_irq5_0),
-	SH_PFC_PIN_GROUP(intc_irq5_1),
-	SH_PFC_PIN_GROUP(intc_irq6_0),
-	SH_PFC_PIN_GROUP(intc_irq6_1),
-	SH_PFC_PIN_GROUP(intc_irq7_0),
-	SH_PFC_PIN_GROUP(intc_irq7_1),
-	SH_PFC_PIN_GROUP(intc_irq8),
-	SH_PFC_PIN_GROUP(intc_irq9_0),
-	SH_PFC_PIN_GROUP(intc_irq9_1),
-	SH_PFC_PIN_GROUP(intc_irq10),
-	SH_PFC_PIN_GROUP(intc_irq11),
-	SH_PFC_PIN_GROUP(intc_irq12_0),
-	SH_PFC_PIN_GROUP(intc_irq12_1),
-	SH_PFC_PIN_GROUP(intc_irq13_0),
-	SH_PFC_PIN_GROUP(intc_irq13_1),
-	SH_PFC_PIN_GROUP(intc_irq14_0),
-	SH_PFC_PIN_GROUP(intc_irq14_1),
-	SH_PFC_PIN_GROUP(intc_irq15_0),
-	SH_PFC_PIN_GROUP(intc_irq15_1),
-	SH_PFC_PIN_GROUP(intc_irq16_0),
-	SH_PFC_PIN_GROUP(intc_irq16_1),
-	SH_PFC_PIN_GROUP(intc_irq17),
-	SH_PFC_PIN_GROUP(intc_irq18),
-	SH_PFC_PIN_GROUP(intc_irq19),
-	SH_PFC_PIN_GROUP(intc_irq20),
-	SH_PFC_PIN_GROUP(intc_irq21),
-	SH_PFC_PIN_GROUP(intc_irq22),
-	SH_PFC_PIN_GROUP(intc_irq23),
-	SH_PFC_PIN_GROUP(intc_irq24),
-	SH_PFC_PIN_GROUP(intc_irq25),
-	SH_PFC_PIN_GROUP(intc_irq26_0),
-	SH_PFC_PIN_GROUP(intc_irq26_1),
-	SH_PFC_PIN_GROUP(intc_irq27_0),
-	SH_PFC_PIN_GROUP(intc_irq27_1),
-	SH_PFC_PIN_GROUP(intc_irq28_0),
-	SH_PFC_PIN_GROUP(intc_irq28_1),
-	SH_PFC_PIN_GROUP(intc_irq29_0),
-	SH_PFC_PIN_GROUP(intc_irq29_1),
-	SH_PFC_PIN_GROUP(intc_irq30_0),
-	SH_PFC_PIN_GROUP(intc_irq30_1),
-	SH_PFC_PIN_GROUP(intc_irq31_0),
-	SH_PFC_PIN_GROUP(intc_irq31_1),
-	SH_PFC_PIN_GROUP(lcd0_data8),
-	SH_PFC_PIN_GROUP(lcd0_data9),
-	SH_PFC_PIN_GROUP(lcd0_data12),
-	SH_PFC_PIN_GROUP(lcd0_data16),
-	SH_PFC_PIN_GROUP(lcd0_data18),
-	SH_PFC_PIN_GROUP(lcd0_data24_0),
-	SH_PFC_PIN_GROUP(lcd0_data24_1),
-	SH_PFC_PIN_GROUP(lcd0_display),
-	SH_PFC_PIN_GROUP(lcd0_lclk_0),
-	SH_PFC_PIN_GROUP(lcd0_lclk_1),
-	SH_PFC_PIN_GROUP(lcd0_sync),
-	SH_PFC_PIN_GROUP(lcd0_sys),
-	SH_PFC_PIN_GROUP(lcd1_data8),
-	SH_PFC_PIN_GROUP(lcd1_data9),
-	SH_PFC_PIN_GROUP(lcd1_data12),
-	SH_PFC_PIN_GROUP(lcd1_data16),
-	SH_PFC_PIN_GROUP(lcd1_data18),
-	SH_PFC_PIN_GROUP(lcd1_data24),
-	SH_PFC_PIN_GROUP(lcd1_display),
-	SH_PFC_PIN_GROUP(lcd1_lclk),
-	SH_PFC_PIN_GROUP(lcd1_sync),
-	SH_PFC_PIN_GROUP(lcd1_sys),
-	SH_PFC_PIN_GROUP(mmc0_data1_0),
-	SH_PFC_PIN_GROUP(mmc0_data4_0),
-	SH_PFC_PIN_GROUP(mmc0_data8_0),
-	SH_PFC_PIN_GROUP(mmc0_ctrl_0),
-	SH_PFC_PIN_GROUP(mmc0_data1_1),
-	SH_PFC_PIN_GROUP(mmc0_data4_1),
-	SH_PFC_PIN_GROUP(mmc0_data8_1),
-	SH_PFC_PIN_GROUP(mmc0_ctrl_1),
-	SH_PFC_PIN_GROUP(scifa0_data),
-	SH_PFC_PIN_GROUP(scifa0_clk),
-	SH_PFC_PIN_GROUP(scifa0_ctrl),
-	SH_PFC_PIN_GROUP(scifa1_data),
-	SH_PFC_PIN_GROUP(scifa1_clk),
-	SH_PFC_PIN_GROUP(scifa1_ctrl),
-	SH_PFC_PIN_GROUP(scifa2_data),
-	SH_PFC_PIN_GROUP(scifa2_clk_0),
-	SH_PFC_PIN_GROUP(scifa2_clk_1),
-	SH_PFC_PIN_GROUP(scifa2_ctrl),
-	SH_PFC_PIN_GROUP(scifa3_data_0),
-	SH_PFC_PIN_GROUP(scifa3_clk_0),
-	SH_PFC_PIN_GROUP(scifa3_ctrl_0),
-	SH_PFC_PIN_GROUP(scifa3_data_1),
-	SH_PFC_PIN_GROUP(scifa3_clk_1),
-	SH_PFC_PIN_GROUP(scifa3_ctrl_1),
-	SH_PFC_PIN_GROUP(scifa4_data_0),
-	SH_PFC_PIN_GROUP(scifa4_data_1),
-	SH_PFC_PIN_GROUP(scifa4_data_2),
-	SH_PFC_PIN_GROUP(scifa4_clk_0),
-	SH_PFC_PIN_GROUP(scifa4_clk_1),
-	SH_PFC_PIN_GROUP(scifa5_data_0),
-	SH_PFC_PIN_GROUP(scifa5_data_1),
-	SH_PFC_PIN_GROUP(scifa5_data_2),
-	SH_PFC_PIN_GROUP(scifa5_clk_0),
-	SH_PFC_PIN_GROUP(scifa5_clk_1),
-	SH_PFC_PIN_GROUP(scifa6_data),
-	SH_PFC_PIN_GROUP(scifa6_clk),
-	SH_PFC_PIN_GROUP(scifa7_data),
-	SH_PFC_PIN_GROUP(scifb_data_0),
-	SH_PFC_PIN_GROUP(scifb_clk_0),
-	SH_PFC_PIN_GROUP(scifb_ctrl_0),
-	SH_PFC_PIN_GROUP(scifb_data_1),
-	SH_PFC_PIN_GROUP(scifb_clk_1),
-	SH_PFC_PIN_GROUP(scifb_ctrl_1),
-	SH_PFC_PIN_GROUP(sdhi0_data1),
-	SH_PFC_PIN_GROUP(sdhi0_data4),
-	SH_PFC_PIN_GROUP(sdhi0_ctrl),
-	SH_PFC_PIN_GROUP(sdhi0_cd),
-	SH_PFC_PIN_GROUP(sdhi0_wp),
-	SH_PFC_PIN_GROUP(sdhi1_data1),
-	SH_PFC_PIN_GROUP(sdhi1_data4),
-	SH_PFC_PIN_GROUP(sdhi1_ctrl),
-	SH_PFC_PIN_GROUP(sdhi1_cd),
-	SH_PFC_PIN_GROUP(sdhi1_wp),
-	SH_PFC_PIN_GROUP(sdhi2_data1),
-	SH_PFC_PIN_GROUP(sdhi2_data4),
-	SH_PFC_PIN_GROUP(sdhi2_ctrl),
-	SH_PFC_PIN_GROUP(sdhi2_cd_0),
-	SH_PFC_PIN_GROUP(sdhi2_wp_0),
-	SH_PFC_PIN_GROUP(sdhi2_cd_1),
-	SH_PFC_PIN_GROUP(sdhi2_wp_1),
-	SH_PFC_PIN_GROUP(tpu0_to0),
-	SH_PFC_PIN_GROUP(tpu0_to1),
-	SH_PFC_PIN_GROUP(tpu0_to2_0),
-	SH_PFC_PIN_GROUP(tpu0_to2_1),
-	SH_PFC_PIN_GROUP(tpu0_to3),
-};
-
-static const char * const bsc_groups[] = {
-	"bsc_data8",
-	"bsc_data16",
-	"bsc_data32",
-	"bsc_cs0",
-	"bsc_cs2",
-	"bsc_cs4",
-	"bsc_cs5a_0",
-	"bsc_cs5a_1",
-	"bsc_cs5b",
-	"bsc_cs6a",
-	"bsc_rd_we8",
-	"bsc_rd_we16",
-	"bsc_rd_we32",
-	"bsc_bs",
-	"bsc_rdwr",
-};
-
-static const char * const ceu0_groups[] = {
-	"ceu0_data_0_7",
-	"ceu0_data_8_15_0",
-	"ceu0_data_8_15_1",
-	"ceu0_clk_0",
-	"ceu0_clk_1",
-	"ceu0_clk_2",
-	"ceu0_sync",
-	"ceu0_field",
-};
-
-static const char * const ceu1_groups[] = {
-	"ceu1_data",
-	"ceu1_clk",
-	"ceu1_sync",
-	"ceu1_field",
-};
-
-static const char * const fsia_groups[] = {
-	"fsia_mclk_in",
-	"fsia_mclk_out",
-	"fsia_sclk_in",
-	"fsia_sclk_out",
-	"fsia_data_in_0",
-	"fsia_data_in_1",
-	"fsia_data_out_0",
-	"fsia_data_out_1",
-	"fsia_data_out_2",
-	"fsia_spdif_0",
-	"fsia_spdif_1",
-};
-
-static const char * const fsib_groups[] = {
-	"fsib_mclk_in",
-};
-
-static const char * const gether_groups[] = {
-	"gether_rmii",
-	"gether_mii",
-	"gether_gmii",
-	"gether_int",
-	"gether_link",
-	"gether_wol",
-};
-
-static const char * const hdmi_groups[] = {
-	"hdmi",
-};
-
-static const char * const intc_groups[] = {
-	"intc_irq0_0",
-	"intc_irq0_1",
-	"intc_irq1",
-	"intc_irq2_0",
-	"intc_irq2_1",
-	"intc_irq3_0",
-	"intc_irq3_1",
-	"intc_irq4_0",
-	"intc_irq4_1",
-	"intc_irq5_0",
-	"intc_irq5_1",
-	"intc_irq6_0",
-	"intc_irq6_1",
-	"intc_irq7_0",
-	"intc_irq7_1",
-	"intc_irq8",
-	"intc_irq9_0",
-	"intc_irq9_1",
-	"intc_irq10",
-	"intc_irq11",
-	"intc_irq12_0",
-	"intc_irq12_1",
-	"intc_irq13_0",
-	"intc_irq13_1",
-	"intc_irq14_0",
-	"intc_irq14_1",
-	"intc_irq15_0",
-	"intc_irq15_1",
-	"intc_irq16_0",
-	"intc_irq16_1",
-	"intc_irq17",
-	"intc_irq18",
-	"intc_irq19",
-	"intc_irq20",
-	"intc_irq21",
-	"intc_irq22",
-	"intc_irq23",
-	"intc_irq24",
-	"intc_irq25",
-	"intc_irq26_0",
-	"intc_irq26_1",
-	"intc_irq27_0",
-	"intc_irq27_1",
-	"intc_irq28_0",
-	"intc_irq28_1",
-	"intc_irq29_0",
-	"intc_irq29_1",
-	"intc_irq30_0",
-	"intc_irq30_1",
-	"intc_irq31_0",
-	"intc_irq31_1",
-};
-
-static const char * const lcd0_groups[] = {
-	"lcd0_data8",
-	"lcd0_data9",
-	"lcd0_data12",
-	"lcd0_data16",
-	"lcd0_data18",
-	"lcd0_data24_0",
-	"lcd0_data24_1",
-	"lcd0_display",
-	"lcd0_lclk_0",
-	"lcd0_lclk_1",
-	"lcd0_sync",
-	"lcd0_sys",
-};
-
-static const char * const lcd1_groups[] = {
-	"lcd1_data8",
-	"lcd1_data9",
-	"lcd1_data12",
-	"lcd1_data16",
-	"lcd1_data18",
-	"lcd1_data24",
-	"lcd1_display",
-	"lcd1_lclk",
-	"lcd1_sync",
-	"lcd1_sys",
-};
-
-static const char * const mmc0_groups[] = {
-	"mmc0_data1_0",
-	"mmc0_data4_0",
-	"mmc0_data8_0",
-	"mmc0_ctrl_0",
-	"mmc0_data1_1",
-	"mmc0_data4_1",
-	"mmc0_data8_1",
-	"mmc0_ctrl_1",
-};
-
-static const char * const scifa0_groups[] = {
-	"scifa0_data",
-	"scifa0_clk",
-	"scifa0_ctrl",
-};
-
-static const char * const scifa1_groups[] = {
-	"scifa1_data",
-	"scifa1_clk",
-	"scifa1_ctrl",
-};
-
-static const char * const scifa2_groups[] = {
-	"scifa2_data",
-	"scifa2_clk_0",
-	"scifa2_clk_1",
-	"scifa2_ctrl",
-};
-
-static const char * const scifa3_groups[] = {
-	"scifa3_data_0",
-	"scifa3_clk_0",
-	"scifa3_ctrl_0",
-	"scifa3_data_1",
-	"scifa3_clk_1",
-	"scifa3_ctrl_1",
-};
-
-static const char * const scifa4_groups[] = {
-	"scifa4_data_0",
-	"scifa4_data_1",
-	"scifa4_data_2",
-	"scifa4_clk_0",
-	"scifa4_clk_1",
-};
-
-static const char * const scifa5_groups[] = {
-	"scifa5_data_0",
-	"scifa5_data_1",
-	"scifa5_data_2",
-	"scifa5_clk_0",
-	"scifa5_clk_1",
-};
-
-static const char * const scifa6_groups[] = {
-	"scifa6_data",
-	"scifa6_clk",
-};
-
-static const char * const scifa7_groups[] = {
-	"scifa7_data",
-};
-
-static const char * const scifb_groups[] = {
-	"scifb_data_0",
-	"scifb_clk_0",
-	"scifb_ctrl_0",
-	"scifb_data_1",
-	"scifb_clk_1",
-	"scifb_ctrl_1",
-};
-
-static const char * const sdhi0_groups[] = {
-	"sdhi0_data1",
-	"sdhi0_data4",
-	"sdhi0_ctrl",
-	"sdhi0_cd",
-	"sdhi0_wp",
-};
-
-static const char * const sdhi1_groups[] = {
-	"sdhi1_data1",
-	"sdhi1_data4",
-	"sdhi1_ctrl",
-	"sdhi1_cd",
-	"sdhi1_wp",
-};
-
-static const char * const sdhi2_groups[] = {
-	"sdhi2_data1",
-	"sdhi2_data4",
-	"sdhi2_ctrl",
-	"sdhi2_cd_0",
-	"sdhi2_wp_0",
-	"sdhi2_cd_1",
-	"sdhi2_wp_1",
-};
-
-static const char * const tpu0_groups[] = {
-	"tpu0_to0",
-	"tpu0_to1",
-	"tpu0_to2_0",
-	"tpu0_to2_1",
-	"tpu0_to3",
-};
-
-static const struct sh_pfc_function pinmux_functions[] = {
-	SH_PFC_FUNCTION(bsc),
-	SH_PFC_FUNCTION(ceu0),
-	SH_PFC_FUNCTION(ceu1),
-	SH_PFC_FUNCTION(fsia),
-	SH_PFC_FUNCTION(fsib),
-	SH_PFC_FUNCTION(gether),
-	SH_PFC_FUNCTION(hdmi),
-	SH_PFC_FUNCTION(intc),
-	SH_PFC_FUNCTION(lcd0),
-	SH_PFC_FUNCTION(lcd1),
-	SH_PFC_FUNCTION(mmc0),
-	SH_PFC_FUNCTION(scifa0),
-	SH_PFC_FUNCTION(scifa1),
-	SH_PFC_FUNCTION(scifa2),
-	SH_PFC_FUNCTION(scifa3),
-	SH_PFC_FUNCTION(scifa4),
-	SH_PFC_FUNCTION(scifa5),
-	SH_PFC_FUNCTION(scifa6),
-	SH_PFC_FUNCTION(scifa7),
-	SH_PFC_FUNCTION(scifb),
-	SH_PFC_FUNCTION(sdhi0),
-	SH_PFC_FUNCTION(sdhi1),
-	SH_PFC_FUNCTION(sdhi2),
-	SH_PFC_FUNCTION(tpu0),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	PORTCR(0,	0xe6050000), /* PORT0CR */
-	PORTCR(1,	0xe6050001), /* PORT1CR */
-	PORTCR(2,	0xe6050002), /* PORT2CR */
-	PORTCR(3,	0xe6050003), /* PORT3CR */
-	PORTCR(4,	0xe6050004), /* PORT4CR */
-	PORTCR(5,	0xe6050005), /* PORT5CR */
-	PORTCR(6,	0xe6050006), /* PORT6CR */
-	PORTCR(7,	0xe6050007), /* PORT7CR */
-	PORTCR(8,	0xe6050008), /* PORT8CR */
-	PORTCR(9,	0xe6050009), /* PORT9CR */
-	PORTCR(10,	0xe605000a), /* PORT10CR */
-	PORTCR(11,	0xe605000b), /* PORT11CR */
-	PORTCR(12,	0xe605000c), /* PORT12CR */
-	PORTCR(13,	0xe605000d), /* PORT13CR */
-	PORTCR(14,	0xe605000e), /* PORT14CR */
-	PORTCR(15,	0xe605000f), /* PORT15CR */
-	PORTCR(16,	0xe6050010), /* PORT16CR */
-	PORTCR(17,	0xe6050011), /* PORT17CR */
-	PORTCR(18,	0xe6050012), /* PORT18CR */
-	PORTCR(19,	0xe6050013), /* PORT19CR */
-	PORTCR(20,	0xe6050014), /* PORT20CR */
-	PORTCR(21,	0xe6050015), /* PORT21CR */
-	PORTCR(22,	0xe6050016), /* PORT22CR */
-	PORTCR(23,	0xe6050017), /* PORT23CR */
-	PORTCR(24,	0xe6050018), /* PORT24CR */
-	PORTCR(25,	0xe6050019), /* PORT25CR */
-	PORTCR(26,	0xe605001a), /* PORT26CR */
-	PORTCR(27,	0xe605001b), /* PORT27CR */
-	PORTCR(28,	0xe605001c), /* PORT28CR */
-	PORTCR(29,	0xe605001d), /* PORT29CR */
-	PORTCR(30,	0xe605001e), /* PORT30CR */
-	PORTCR(31,	0xe605001f), /* PORT31CR */
-	PORTCR(32,	0xe6050020), /* PORT32CR */
-	PORTCR(33,	0xe6050021), /* PORT33CR */
-	PORTCR(34,	0xe6050022), /* PORT34CR */
-	PORTCR(35,	0xe6050023), /* PORT35CR */
-	PORTCR(36,	0xe6050024), /* PORT36CR */
-	PORTCR(37,	0xe6050025), /* PORT37CR */
-	PORTCR(38,	0xe6050026), /* PORT38CR */
-	PORTCR(39,	0xe6050027), /* PORT39CR */
-	PORTCR(40,	0xe6050028), /* PORT40CR */
-	PORTCR(41,	0xe6050029), /* PORT41CR */
-	PORTCR(42,	0xe605002a), /* PORT42CR */
-	PORTCR(43,	0xe605002b), /* PORT43CR */
-	PORTCR(44,	0xe605002c), /* PORT44CR */
-	PORTCR(45,	0xe605002d), /* PORT45CR */
-	PORTCR(46,	0xe605002e), /* PORT46CR */
-	PORTCR(47,	0xe605002f), /* PORT47CR */
-	PORTCR(48,	0xe6050030), /* PORT48CR */
-	PORTCR(49,	0xe6050031), /* PORT49CR */
-	PORTCR(50,	0xe6050032), /* PORT50CR */
-	PORTCR(51,	0xe6050033), /* PORT51CR */
-	PORTCR(52,	0xe6050034), /* PORT52CR */
-	PORTCR(53,	0xe6050035), /* PORT53CR */
-	PORTCR(54,	0xe6050036), /* PORT54CR */
-	PORTCR(55,	0xe6050037), /* PORT55CR */
-	PORTCR(56,	0xe6050038), /* PORT56CR */
-	PORTCR(57,	0xe6050039), /* PORT57CR */
-	PORTCR(58,	0xe605003a), /* PORT58CR */
-	PORTCR(59,	0xe605003b), /* PORT59CR */
-	PORTCR(60,	0xe605003c), /* PORT60CR */
-	PORTCR(61,	0xe605003d), /* PORT61CR */
-	PORTCR(62,	0xe605003e), /* PORT62CR */
-	PORTCR(63,	0xe605003f), /* PORT63CR */
-	PORTCR(64,	0xe6050040), /* PORT64CR */
-	PORTCR(65,	0xe6050041), /* PORT65CR */
-	PORTCR(66,	0xe6050042), /* PORT66CR */
-	PORTCR(67,	0xe6050043), /* PORT67CR */
-	PORTCR(68,	0xe6050044), /* PORT68CR */
-	PORTCR(69,	0xe6050045), /* PORT69CR */
-	PORTCR(70,	0xe6050046), /* PORT70CR */
-	PORTCR(71,	0xe6050047), /* PORT71CR */
-	PORTCR(72,	0xe6050048), /* PORT72CR */
-	PORTCR(73,	0xe6050049), /* PORT73CR */
-	PORTCR(74,	0xe605004a), /* PORT74CR */
-	PORTCR(75,	0xe605004b), /* PORT75CR */
-	PORTCR(76,	0xe605004c), /* PORT76CR */
-	PORTCR(77,	0xe605004d), /* PORT77CR */
-	PORTCR(78,	0xe605004e), /* PORT78CR */
-	PORTCR(79,	0xe605004f), /* PORT79CR */
-	PORTCR(80,	0xe6050050), /* PORT80CR */
-	PORTCR(81,	0xe6050051), /* PORT81CR */
-	PORTCR(82,	0xe6050052), /* PORT82CR */
-	PORTCR(83,	0xe6050053), /* PORT83CR */
-
-	PORTCR(84,	0xe6051054), /* PORT84CR */
-	PORTCR(85,	0xe6051055), /* PORT85CR */
-	PORTCR(86,	0xe6051056), /* PORT86CR */
-	PORTCR(87,	0xe6051057), /* PORT87CR */
-	PORTCR(88,	0xe6051058), /* PORT88CR */
-	PORTCR(89,	0xe6051059), /* PORT89CR */
-	PORTCR(90,	0xe605105a), /* PORT90CR */
-	PORTCR(91,	0xe605105b), /* PORT91CR */
-	PORTCR(92,	0xe605105c), /* PORT92CR */
-	PORTCR(93,	0xe605105d), /* PORT93CR */
-	PORTCR(94,	0xe605105e), /* PORT94CR */
-	PORTCR(95,	0xe605105f), /* PORT95CR */
-	PORTCR(96,	0xe6051060), /* PORT96CR */
-	PORTCR(97,	0xe6051061), /* PORT97CR */
-	PORTCR(98,	0xe6051062), /* PORT98CR */
-	PORTCR(99,	0xe6051063), /* PORT99CR */
-	PORTCR(100,	0xe6051064), /* PORT100CR */
-	PORTCR(101,	0xe6051065), /* PORT101CR */
-	PORTCR(102,	0xe6051066), /* PORT102CR */
-	PORTCR(103,	0xe6051067), /* PORT103CR */
-	PORTCR(104,	0xe6051068), /* PORT104CR */
-	PORTCR(105,	0xe6051069), /* PORT105CR */
-	PORTCR(106,	0xe605106a), /* PORT106CR */
-	PORTCR(107,	0xe605106b), /* PORT107CR */
-	PORTCR(108,	0xe605106c), /* PORT108CR */
-	PORTCR(109,	0xe605106d), /* PORT109CR */
-	PORTCR(110,	0xe605106e), /* PORT110CR */
-	PORTCR(111,	0xe605106f), /* PORT111CR */
-	PORTCR(112,	0xe6051070), /* PORT112CR */
-	PORTCR(113,	0xe6051071), /* PORT113CR */
-	PORTCR(114,	0xe6051072), /* PORT114CR */
-
-	PORTCR(115,	0xe6052073), /* PORT115CR */
-	PORTCR(116,	0xe6052074), /* PORT116CR */
-	PORTCR(117,	0xe6052075), /* PORT117CR */
-	PORTCR(118,	0xe6052076), /* PORT118CR */
-	PORTCR(119,	0xe6052077), /* PORT119CR */
-	PORTCR(120,	0xe6052078), /* PORT120CR */
-	PORTCR(121,	0xe6052079), /* PORT121CR */
-	PORTCR(122,	0xe605207a), /* PORT122CR */
-	PORTCR(123,	0xe605207b), /* PORT123CR */
-	PORTCR(124,	0xe605207c), /* PORT124CR */
-	PORTCR(125,	0xe605207d), /* PORT125CR */
-	PORTCR(126,	0xe605207e), /* PORT126CR */
-	PORTCR(127,	0xe605207f), /* PORT127CR */
-	PORTCR(128,	0xe6052080), /* PORT128CR */
-	PORTCR(129,	0xe6052081), /* PORT129CR */
-	PORTCR(130,	0xe6052082), /* PORT130CR */
-	PORTCR(131,	0xe6052083), /* PORT131CR */
-	PORTCR(132,	0xe6052084), /* PORT132CR */
-	PORTCR(133,	0xe6052085), /* PORT133CR */
-	PORTCR(134,	0xe6052086), /* PORT134CR */
-	PORTCR(135,	0xe6052087), /* PORT135CR */
-	PORTCR(136,	0xe6052088), /* PORT136CR */
-	PORTCR(137,	0xe6052089), /* PORT137CR */
-	PORTCR(138,	0xe605208a), /* PORT138CR */
-	PORTCR(139,	0xe605208b), /* PORT139CR */
-	PORTCR(140,	0xe605208c), /* PORT140CR */
-	PORTCR(141,	0xe605208d), /* PORT141CR */
-	PORTCR(142,	0xe605208e), /* PORT142CR */
-	PORTCR(143,	0xe605208f), /* PORT143CR */
-	PORTCR(144,	0xe6052090), /* PORT144CR */
-	PORTCR(145,	0xe6052091), /* PORT145CR */
-	PORTCR(146,	0xe6052092), /* PORT146CR */
-	PORTCR(147,	0xe6052093), /* PORT147CR */
-	PORTCR(148,	0xe6052094), /* PORT148CR */
-	PORTCR(149,	0xe6052095), /* PORT149CR */
-	PORTCR(150,	0xe6052096), /* PORT150CR */
-	PORTCR(151,	0xe6052097), /* PORT151CR */
-	PORTCR(152,	0xe6052098), /* PORT152CR */
-	PORTCR(153,	0xe6052099), /* PORT153CR */
-	PORTCR(154,	0xe605209a), /* PORT154CR */
-	PORTCR(155,	0xe605209b), /* PORT155CR */
-	PORTCR(156,	0xe605209c), /* PORT156CR */
-	PORTCR(157,	0xe605209d), /* PORT157CR */
-	PORTCR(158,	0xe605209e), /* PORT158CR */
-	PORTCR(159,	0xe605209f), /* PORT159CR */
-	PORTCR(160,	0xe60520a0), /* PORT160CR */
-	PORTCR(161,	0xe60520a1), /* PORT161CR */
-	PORTCR(162,	0xe60520a2), /* PORT162CR */
-	PORTCR(163,	0xe60520a3), /* PORT163CR */
-	PORTCR(164,	0xe60520a4), /* PORT164CR */
-	PORTCR(165,	0xe60520a5), /* PORT165CR */
-	PORTCR(166,	0xe60520a6), /* PORT166CR */
-	PORTCR(167,	0xe60520a7), /* PORT167CR */
-	PORTCR(168,	0xe60520a8), /* PORT168CR */
-	PORTCR(169,	0xe60520a9), /* PORT169CR */
-	PORTCR(170,	0xe60520aa), /* PORT170CR */
-	PORTCR(171,	0xe60520ab), /* PORT171CR */
-	PORTCR(172,	0xe60520ac), /* PORT172CR */
-	PORTCR(173,	0xe60520ad), /* PORT173CR */
-	PORTCR(174,	0xe60520ae), /* PORT174CR */
-	PORTCR(175,	0xe60520af), /* PORT175CR */
-	PORTCR(176,	0xe60520b0), /* PORT176CR */
-	PORTCR(177,	0xe60520b1), /* PORT177CR */
-	PORTCR(178,	0xe60520b2), /* PORT178CR */
-	PORTCR(179,	0xe60520b3), /* PORT179CR */
-	PORTCR(180,	0xe60520b4), /* PORT180CR */
-	PORTCR(181,	0xe60520b5), /* PORT181CR */
-	PORTCR(182,	0xe60520b6), /* PORT182CR */
-	PORTCR(183,	0xe60520b7), /* PORT183CR */
-	PORTCR(184,	0xe60520b8), /* PORT184CR */
-	PORTCR(185,	0xe60520b9), /* PORT185CR */
-	PORTCR(186,	0xe60520ba), /* PORT186CR */
-	PORTCR(187,	0xe60520bb), /* PORT187CR */
-	PORTCR(188,	0xe60520bc), /* PORT188CR */
-	PORTCR(189,	0xe60520bd), /* PORT189CR */
-	PORTCR(190,	0xe60520be), /* PORT190CR */
-	PORTCR(191,	0xe60520bf), /* PORT191CR */
-	PORTCR(192,	0xe60520c0), /* PORT192CR */
-	PORTCR(193,	0xe60520c1), /* PORT193CR */
-	PORTCR(194,	0xe60520c2), /* PORT194CR */
-	PORTCR(195,	0xe60520c3), /* PORT195CR */
-	PORTCR(196,	0xe60520c4), /* PORT196CR */
-	PORTCR(197,	0xe60520c5), /* PORT197CR */
-	PORTCR(198,	0xe60520c6), /* PORT198CR */
-	PORTCR(199,	0xe60520c7), /* PORT199CR */
-	PORTCR(200,	0xe60520c8), /* PORT200CR */
-	PORTCR(201,	0xe60520c9), /* PORT201CR */
-	PORTCR(202,	0xe60520ca), /* PORT202CR */
-	PORTCR(203,	0xe60520cb), /* PORT203CR */
-	PORTCR(204,	0xe60520cc), /* PORT204CR */
-	PORTCR(205,	0xe60520cd), /* PORT205CR */
-	PORTCR(206,	0xe60520ce), /* PORT206CR */
-	PORTCR(207,	0xe60520cf), /* PORT207CR */
-	PORTCR(208,	0xe60520d0), /* PORT208CR */
-	PORTCR(209,	0xe60520d1), /* PORT209CR */
-
-	PORTCR(210,	0xe60530d2), /* PORT210CR */
-	PORTCR(211,	0xe60530d3), /* PORT211CR */
-
-	{ PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1, GROUP(
-			MSEL1CR_31_0,	MSEL1CR_31_1,
-			MSEL1CR_30_0,	MSEL1CR_30_1,
-			MSEL1CR_29_0,	MSEL1CR_29_1,
-			MSEL1CR_28_0,	MSEL1CR_28_1,
-			MSEL1CR_27_0,	MSEL1CR_27_1,
-			MSEL1CR_26_0,	MSEL1CR_26_1,
-			0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-			0, 0, 0, 0, 0, 0, 0, 0,
-			MSEL1CR_16_0,	MSEL1CR_16_1,
-			MSEL1CR_15_0,	MSEL1CR_15_1,
-			MSEL1CR_14_0,	MSEL1CR_14_1,
-			MSEL1CR_13_0,	MSEL1CR_13_1,
-			MSEL1CR_12_0,	MSEL1CR_12_1,
-			0, 0, 0, 0,
-			MSEL1CR_9_0,	MSEL1CR_9_1,
-			0, 0,
-			MSEL1CR_7_0,	MSEL1CR_7_1,
-			MSEL1CR_6_0,	MSEL1CR_6_1,
-			MSEL1CR_5_0,	MSEL1CR_5_1,
-			MSEL1CR_4_0,	MSEL1CR_4_1,
-			MSEL1CR_3_0,	MSEL1CR_3_1,
-			MSEL1CR_2_0,	MSEL1CR_2_1,
-			0, 0,
-			MSEL1CR_0_0,	MSEL1CR_0_1,
-		))
-	},
-	{ PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1, GROUP(
-			0, 0, 0, 0, 0, 0, 0, 0,
-			0, 0, 0, 0, 0, 0, 0, 0,
-			0, 0, 0, 0, 0, 0, 0, 0,
-			0, 0, 0, 0, 0, 0, 0, 0,
-			MSEL3CR_15_0,	MSEL3CR_15_1,
-			0, 0, 0, 0, 0, 0, 0, 0,
-			0, 0, 0, 0, 0, 0, 0, 0,
-			MSEL3CR_6_0,	MSEL3CR_6_1,
-			0, 0, 0, 0, 0, 0, 0, 0,
-			0, 0, 0, 0,
-			))
-	},
-	{ PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1, GROUP(
-			0, 0, 0, 0, 0, 0, 0, 0,
-			0, 0, 0, 0, 0, 0, 0, 0,
-			0, 0, 0, 0, 0, 0, 0, 0,
-			MSEL4CR_19_0,	MSEL4CR_19_1,
-			MSEL4CR_18_0,	MSEL4CR_18_1,
-			0, 0, 0, 0,
-			MSEL4CR_15_0,	MSEL4CR_15_1,
-			0, 0, 0, 0, 0, 0, 0, 0,
-			MSEL4CR_10_0,	MSEL4CR_10_1,
-			0, 0, 0, 0, 0, 0,
-			MSEL4CR_6_0,	MSEL4CR_6_1,
-			0, 0,
-			MSEL4CR_4_0,	MSEL4CR_4_1,
-			0, 0, 0, 0,
-			MSEL4CR_1_0,	MSEL4CR_1_1,
-			0, 0,
-		))
-	},
-	{ PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1, GROUP(
-			MSEL5CR_31_0,	MSEL5CR_31_1,
-			MSEL5CR_30_0,	MSEL5CR_30_1,
-			MSEL5CR_29_0,	MSEL5CR_29_1,
-			0, 0,
-			MSEL5CR_27_0,	MSEL5CR_27_1,
-			0, 0,
-			MSEL5CR_25_0,	MSEL5CR_25_1,
-			0, 0,
-			MSEL5CR_23_0,	MSEL5CR_23_1,
-			0, 0,
-			MSEL5CR_21_0,	MSEL5CR_21_1,
-			0, 0,
-			MSEL5CR_19_0,	MSEL5CR_19_1,
-			0, 0,
-			MSEL5CR_17_0,	MSEL5CR_17_1,
-			0, 0,
-			MSEL5CR_15_0,	MSEL5CR_15_1,
-			MSEL5CR_14_0,	MSEL5CR_14_1,
-			MSEL5CR_13_0,	MSEL5CR_13_1,
-			MSEL5CR_12_0,	MSEL5CR_12_1,
-			MSEL5CR_11_0,	MSEL5CR_11_1,
-			MSEL5CR_10_0,	MSEL5CR_10_1,
-			0, 0,
-			MSEL5CR_8_0,	MSEL5CR_8_1,
-			MSEL5CR_7_0,	MSEL5CR_7_1,
-			MSEL5CR_6_0,	MSEL5CR_6_1,
-			MSEL5CR_5_0,	MSEL5CR_5_1,
-			MSEL5CR_4_0,	MSEL5CR_4_1,
-			MSEL5CR_3_0,	MSEL5CR_3_1,
-			MSEL5CR_2_0,	MSEL5CR_2_1,
-			0, 0,
-			MSEL5CR_0_0,	MSEL5CR_0_1,
-		))
-	},
-	{ },
-};
-
-static const struct pinmux_data_reg pinmux_data_regs[] = {
-	{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32, GROUP(
-		PORT31_DATA,	PORT30_DATA,	PORT29_DATA,	PORT28_DATA,
-		PORT27_DATA,	PORT26_DATA,	PORT25_DATA,	PORT24_DATA,
-		PORT23_DATA,	PORT22_DATA,	PORT21_DATA,	PORT20_DATA,
-		PORT19_DATA,	PORT18_DATA,	PORT17_DATA,	PORT16_DATA,
-		PORT15_DATA,	PORT14_DATA,	PORT13_DATA,	PORT12_DATA,
-		PORT11_DATA,	PORT10_DATA,	PORT9_DATA,	PORT8_DATA,
-		PORT7_DATA,	PORT6_DATA,	PORT5_DATA,	PORT4_DATA,
-		PORT3_DATA,	PORT2_DATA,	PORT1_DATA,	PORT0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32, GROUP(
-		PORT63_DATA,	PORT62_DATA,	PORT61_DATA,	PORT60_DATA,
-		PORT59_DATA,	PORT58_DATA,	PORT57_DATA,	PORT56_DATA,
-		PORT55_DATA,	PORT54_DATA,	PORT53_DATA,	PORT52_DATA,
-		PORT51_DATA,	PORT50_DATA,	PORT49_DATA,	PORT48_DATA,
-		PORT47_DATA,	PORT46_DATA,	PORT45_DATA,	PORT44_DATA,
-		PORT43_DATA,	PORT42_DATA,	PORT41_DATA,	PORT40_DATA,
-		PORT39_DATA,	PORT38_DATA,	PORT37_DATA,	PORT36_DATA,
-		PORT35_DATA,	PORT34_DATA,	PORT33_DATA,	PORT32_DATA ))
-	},
-	{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PORT83_DATA,	PORT82_DATA,	PORT81_DATA,	PORT80_DATA,
-		PORT79_DATA,	PORT78_DATA,	PORT77_DATA,	PORT76_DATA,
-		PORT75_DATA,	PORT74_DATA,	PORT73_DATA,	PORT72_DATA,
-		PORT71_DATA,	PORT70_DATA,	PORT69_DATA,	PORT68_DATA,
-		PORT67_DATA,	PORT66_DATA,	PORT65_DATA,	PORT64_DATA ))
-	},
-	{ PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32, GROUP(
-		PORT95_DATA,	PORT94_DATA,	PORT93_DATA,	PORT92_DATA,
-		PORT91_DATA,	PORT90_DATA,	PORT89_DATA,	PORT88_DATA,
-		PORT87_DATA,	PORT86_DATA,	PORT85_DATA,	PORT84_DATA,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0 ))
-	},
-	{ PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0,		PORT114_DATA,	PORT113_DATA,	PORT112_DATA,
-		PORT111_DATA,	PORT110_DATA,	PORT109_DATA,	PORT108_DATA,
-		PORT107_DATA,	PORT106_DATA,	PORT105_DATA,	PORT104_DATA,
-		PORT103_DATA,	PORT102_DATA,	PORT101_DATA,	PORT100_DATA,
-		PORT99_DATA,	PORT98_DATA,	PORT97_DATA,	PORT96_DATA ))
-	},
-	{ PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32, GROUP(
-		PORT127_DATA,	PORT126_DATA,	PORT125_DATA,	PORT124_DATA,
-		PORT123_DATA,	PORT122_DATA,	PORT121_DATA,	PORT120_DATA,
-		PORT119_DATA,	PORT118_DATA,	PORT117_DATA,	PORT116_DATA,
-		PORT115_DATA,	0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0 ))
-	},
-	{ PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32, GROUP(
-		PORT159_DATA,	PORT158_DATA,	PORT157_DATA,	PORT156_DATA,
-		PORT155_DATA,	PORT154_DATA,	PORT153_DATA,	PORT152_DATA,
-		PORT151_DATA,	PORT150_DATA,	PORT149_DATA,	PORT148_DATA,
-		PORT147_DATA,	PORT146_DATA,	PORT145_DATA,	PORT144_DATA,
-		PORT143_DATA,	PORT142_DATA,	PORT141_DATA,	PORT140_DATA,
-		PORT139_DATA,	PORT138_DATA,	PORT137_DATA,	PORT136_DATA,
-		PORT135_DATA,	PORT134_DATA,	PORT133_DATA,	PORT132_DATA,
-		PORT131_DATA,	PORT130_DATA,	PORT129_DATA,	PORT128_DATA ))
-	},
-	{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32, GROUP(
-		PORT191_DATA,	PORT190_DATA,	PORT189_DATA,	PORT188_DATA,
-		PORT187_DATA,	PORT186_DATA,	PORT185_DATA,	PORT184_DATA,
-		PORT183_DATA,	PORT182_DATA,	PORT181_DATA,	PORT180_DATA,
-		PORT179_DATA,	PORT178_DATA,	PORT177_DATA,	PORT176_DATA,
-		PORT175_DATA,	PORT174_DATA,	PORT173_DATA,	PORT172_DATA,
-		PORT171_DATA,	PORT170_DATA,	PORT169_DATA,	PORT168_DATA,
-		PORT167_DATA,	PORT166_DATA,	PORT165_DATA,	PORT164_DATA,
-		PORT163_DATA,	PORT162_DATA,	PORT161_DATA,	PORT160_DATA ))
-	},
-	{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0,				PORT209_DATA,	PORT208_DATA,
-		PORT207_DATA,	PORT206_DATA,	PORT205_DATA,	PORT204_DATA,
-		PORT203_DATA,	PORT202_DATA,	PORT201_DATA,	PORT200_DATA,
-		PORT199_DATA,	PORT198_DATA,	PORT197_DATA,	PORT196_DATA,
-		PORT195_DATA,	PORT194_DATA,	PORT193_DATA,	PORT192_DATA ))
-	},
-	{ PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PORT211_DATA,	PORT210_DATA, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0 ))
-	},
-	{ },
-};
-
-static const struct pinmux_irq pinmux_irqs[] = {
-	PINMUX_IRQ(2,   13),	/* IRQ0A */
-	PINMUX_IRQ(20),		/* IRQ1A */
-	PINMUX_IRQ(11,  12),	/* IRQ2A */
-	PINMUX_IRQ(10,  14),	/* IRQ3A */
-	PINMUX_IRQ(15,  172),	/* IRQ4A */
-	PINMUX_IRQ(0,   1),	/* IRQ5A */
-	PINMUX_IRQ(121, 173),	/* IRQ6A */
-	PINMUX_IRQ(120, 209),	/* IRQ7A */
-	PINMUX_IRQ(119),	/* IRQ8A */
-	PINMUX_IRQ(118, 210),	/* IRQ9A */
-	PINMUX_IRQ(19),		/* IRQ10A */
-	PINMUX_IRQ(104),	/* IRQ11A */
-	PINMUX_IRQ(42,  97),	/* IRQ12A */
-	PINMUX_IRQ(64,  98),	/* IRQ13A */
-	PINMUX_IRQ(63,  99),	/* IRQ14A */
-	PINMUX_IRQ(62,  100),	/* IRQ15A */
-	PINMUX_IRQ(68,  211),	/* IRQ16A */
-	PINMUX_IRQ(69),		/* IRQ17A */
-	PINMUX_IRQ(70),		/* IRQ18A */
-	PINMUX_IRQ(71),		/* IRQ19A */
-	PINMUX_IRQ(67),		/* IRQ20A */
-	PINMUX_IRQ(202),	/* IRQ21A */
-	PINMUX_IRQ(95),		/* IRQ22A */
-	PINMUX_IRQ(96),		/* IRQ23A */
-	PINMUX_IRQ(180),	/* IRQ24A */
-	PINMUX_IRQ(38),		/* IRQ25A */
-	PINMUX_IRQ(58,  81),	/* IRQ26A */
-	PINMUX_IRQ(57,  168),	/* IRQ27A */
-	PINMUX_IRQ(56,  169),	/* IRQ28A */
-	PINMUX_IRQ(50,  170),	/* IRQ29A */
-	PINMUX_IRQ(49,  171),	/* IRQ30A */
-	PINMUX_IRQ(41,  167),	/* IRQ31A */
-};
-
-#define PORTnCR_PULMD_OFF	(0 << 6)
-#define PORTnCR_PULMD_DOWN	(2 << 6)
-#define PORTnCR_PULMD_UP	(3 << 6)
-#define PORTnCR_PULMD_MASK	(3 << 6)
-
-struct r8a7740_portcr_group {
-	unsigned int end_pin;
-	unsigned int offset;
-};
-
-static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
-	{ 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
-};
-
-static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
-{
-	unsigned int i;
-
-	for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) {
-		const struct r8a7740_portcr_group *group =
-			&r8a7740_portcr_offsets[i];
-
-		if (pin <= group->end_pin)
-			return pfc->windows->virt + group->offset + pin;
-	}
-
-	return NULL;
-}
-
-static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
-{
-	void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
-	u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
-
-	switch (value) {
-	case PORTnCR_PULMD_UP:
-		return PIN_CONFIG_BIAS_PULL_UP;
-	case PORTnCR_PULMD_DOWN:
-		return PIN_CONFIG_BIAS_PULL_DOWN;
-	case PORTnCR_PULMD_OFF:
-	default:
-		return PIN_CONFIG_BIAS_DISABLE;
-	}
-}
-
-static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
-				   unsigned int bias)
-{
-	void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
-	u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
-
-	switch (bias) {
-	case PIN_CONFIG_BIAS_PULL_UP:
-		value |= PORTnCR_PULMD_UP;
-		break;
-	case PIN_CONFIG_BIAS_PULL_DOWN:
-		value |= PORTnCR_PULMD_DOWN;
-		break;
-	}
-
-	iowrite8(value, addr);
-}
-
-static const struct sh_pfc_soc_operations r8a7740_pfc_ops = {
-	.get_bias = r8a7740_pinmux_get_bias,
-	.set_bias = r8a7740_pinmux_set_bias,
-};
-
-const struct sh_pfc_soc_info r8a7740_pinmux_info = {
-	.name		= "r8a7740_pfc",
-	.ops		= &r8a7740_pfc_ops,
-
-	.input		= { PINMUX_INPUT_BEGIN,
-			    PINMUX_INPUT_END },
-	.output		= { PINMUX_OUTPUT_BEGIN,
-			    PINMUX_OUTPUT_END },
-	.function	= { PINMUX_FUNCTION_BEGIN,
-			    PINMUX_FUNCTION_END },
-
-	.pins		= pinmux_pins,
-	.nr_pins	= ARRAY_SIZE(pinmux_pins),
-	.groups		= pinmux_groups,
-	.nr_groups	= ARRAY_SIZE(pinmux_groups),
-	.functions	= pinmux_functions,
-	.nr_functions	= ARRAY_SIZE(pinmux_functions),
-
-	.cfg_regs	= pinmux_config_regs,
-	.data_regs	= pinmux_data_regs,
-
-	.pinmux_data	= pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-
-	.gpio_irq	= pinmux_irqs,
-	.gpio_irq_size	= ARRAY_SIZE(pinmux_irqs),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
deleted file mode 100644
index b3b116da1bb0..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
+++ /dev/null
@@ -1,3447 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * R8A77470 processor support - PFC hardware block.
- *
- * Copyright (C) 2018 Renesas Electronics Corp.
- */
-
-#include <linux/errno.h>
-#include <linux/kernel.h>
-
-#include "sh_pfc.h"
-
-#define CPU_ALL_GP(fn, sfx)						\
-	PORT_GP_4(0, fn, sfx),						\
-	PORT_GP_1(0, 4, fn, sfx),					\
-	PORT_GP_CFG_1(0,  5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(0,  6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(0,  7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(0,  8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(0,  9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_1(0, 11, fn, sfx),					\
-	PORT_GP_1(0, 12, fn, sfx),					\
-	PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_23(1, fn, sfx),						\
-	PORT_GP_32(2, fn, sfx),						\
-	PORT_GP_17(3, fn, sfx),						\
-	PORT_GP_1(3, 27, fn, sfx),					\
-	PORT_GP_1(3, 28, fn, sfx),					\
-	PORT_GP_1(3, 29, fn, sfx),					\
-	PORT_GP_14(4, fn, sfx),						\
-	PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_1(4, 20, fn, sfx),					\
-	PORT_GP_1(4, 21, fn, sfx),					\
-	PORT_GP_1(4, 22, fn, sfx),					\
-	PORT_GP_1(4, 23, fn, sfx),					\
-	PORT_GP_1(4, 24, fn, sfx),					\
-	PORT_GP_1(4, 25, fn, sfx),					\
-	PORT_GP_32(5, fn, sfx)
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	GP_ALL(DATA),
-	PINMUX_DATA_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	GP_ALL(FN),
-
-	/* GPSR0 */
-	FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, FN_CLKOUT,
-	FN_IP0_3_0, FN_IP0_7_4, FN_IP0_11_8, FN_IP0_15_12, FN_IP0_19_16,
-	FN_IP0_23_20, FN_IP0_27_24, FN_IP0_31_28, FN_MMC0_CLK_SDHI1_CLK,
-	FN_MMC0_CMD_SDHI1_CMD, FN_MMC0_D0_SDHI1_D0, FN_MMC0_D1_SDHI1_D1,
-	FN_MMC0_D2_SDHI1_D2, FN_MMC0_D3_SDHI1_D3, FN_IP1_3_0,
-	FN_IP1_7_4, FN_MMC0_D6, FN_MMC0_D7,
-
-	/* GPSR1 */
-	FN_IP1_11_8, FN_IP1_15_12, FN_IP1_19_16, FN_IP1_23_20, FN_IP1_27_24,
-	FN_IP1_31_28, FN_IP2_3_0, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
-	FN_IP2_19_16, FN_IP2_23_20, FN_IP2_27_24, FN_IP2_31_28, FN_IP3_3_0,
-	FN_IP3_7_4, FN_IP3_11_8, FN_IP3_15_12, FN_IP3_19_16, FN_IP3_23_20,
-	FN_IP3_27_24, FN_IP3_31_28, FN_IP4_3_0,
-
-	/* GPSR2 */
-	FN_IP4_7_4, FN_IP4_11_8, FN_IP4_15_12, FN_IP4_19_16, FN_IP4_23_20,
-	FN_IP4_27_24, FN_IP4_31_28, FN_IP5_3_0, FN_IP5_7_4, FN_IP5_11_8,
-	FN_IP5_15_12, FN_IP5_19_16, FN_IP5_23_20, FN_IP5_27_24, FN_IP5_31_28,
-	FN_IP6_3_0, FN_IP6_7_4, FN_IP6_11_8, FN_IP6_15_12, FN_IP6_19_16,
-	FN_IP6_23_20, FN_IP6_27_24, FN_IP6_31_28, FN_IP7_3_0, FN_IP7_7_4,
-	FN_IP7_11_8, FN_IP7_15_12, FN_IP7_19_16, FN_IP7_23_20, FN_IP7_27_24,
-	FN_IP7_31_28, FN_IP8_3_0,
-
-	/* GPSR3 */
-	FN_IP8_7_4, FN_IP8_11_8, FN_IP8_15_12, FN_IP8_19_16, FN_IP8_23_20,
-	FN_IP8_27_24, FN_IP8_31_28, FN_IP9_3_0, FN_IP9_7_4, FN_IP9_11_8,
-	FN_IP9_15_12, FN_IP9_19_16, FN_IP9_23_20, FN_IP9_27_24, FN_IP9_31_28,
-	FN_IP10_3_0, FN_IP10_7_4, FN_IP10_11_8, FN_IP10_15_12, FN_IP10_19_16,
-
-	/* GPSR4 */
-	FN_IP10_23_20, FN_IP10_27_24, FN_IP10_31_28, FN_IP11_3_0, FN_IP11_7_4,
-	FN_IP11_11_8, FN_IP11_15_12, FN_IP11_19_16, FN_IP11_23_20,
-	FN_IP11_27_24, FN_IP11_31_28, FN_IP12_3_0, FN_IP12_7_4, FN_IP12_11_8,
-	FN_IP12_15_12, FN_IP12_19_16, FN_IP12_23_20, FN_IP12_27_24,
-	FN_IP12_31_28, FN_IP13_3_0, FN_IP13_7_4, FN_IP13_11_8, FN_IP13_15_12,
-	FN_IP13_19_16, FN_IP13_23_20, FN_IP13_27_24,
-
-	/* GPSR5 */
-	FN_IP13_31_28, FN_IP14_3_0, FN_IP14_7_4, FN_IP14_11_8, FN_IP14_15_12,
-	FN_IP14_19_16, FN_IP14_23_20, FN_IP14_27_24, FN_IP14_31_28,
-	FN_IP15_3_0, FN_IP15_7_4, FN_IP15_11_8, FN_IP15_15_12, FN_IP15_19_16,
-	FN_IP15_23_20, FN_IP15_27_24, FN_IP15_31_28, FN_IP16_3_0, FN_IP16_7_4,
-	FN_IP16_11_8, FN_IP16_15_12, FN_IP16_19_16, FN_IP16_23_20,
-	FN_IP16_27_24, FN_IP16_31_28, FN_IP17_3_0, FN_IP17_7_4, FN_IP17_11_8,
-	FN_IP17_15_12, FN_IP17_19_16, FN_IP17_23_20, FN_IP17_27_24,
-
-	/* IPSR0 */
-	FN_SD0_CLK, FN_SSI_SCK1_C, FN_RX3_C,
-	FN_SD0_CMD, FN_SSI_WS1_C, FN_TX3_C,
-	FN_SD0_DAT0, FN_SSI_SDATA1_C, FN_RX4_E,
-	FN_SD0_DAT1, FN_SSI_SCK0129_B, FN_TX4_E,
-	FN_SD0_DAT2, FN_SSI_WS0129_B, FN_RX5_E,
-	FN_SD0_DAT3, FN_SSI_SDATA0_B, FN_TX5_E,
-	FN_SD0_CD, FN_CAN0_RX_A,
-	FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A,
-
-	/* IPSR1 */
-	FN_MMC0_D4, FN_SD1_CD,
-	FN_MMC0_D5, FN_SD1_WP,
-	FN_D0, FN_SCL3_B, FN_RX5_B, FN_IRQ4, FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B,
-	FN_D1, FN_SDA3_B, FN_TX5_B, FN_MSIOF2_TXD_C, FN_SSI_WS5_B,
-	FN_D2, FN_RX4_B, FN_SCL0_D, FN_PWM1_C, FN_MSIOF2_SCK_C, FN_SSI_SCK5_B,
-	FN_D3, FN_TX4_B, FN_SDA0_D, FN_PWM0_A, FN_MSIOF2_SYNC_C,
-	FN_D4, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C,
-	FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B,
-
-	/* IPSR2 */
-	FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C,
-	FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
-	FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C,
-	FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D,
-	FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B,
-	FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B,
-	FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, FN_CAN_CLK_C,
-	FN_D13,	FN_MSIOF2_SYNC_A, FN_RX4_C,
-
-	/* IPSR3 */
-	FN_D14, FN_MSIOF2_SS1, FN_TX4_C, FN_CAN1_RX_B, FN_AVB_AVTP_CAPTURE_A,
-	FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, FN_CAN1_TX_B, FN_IRQ2, FN_AVB_AVTP_MATCH_A,
-	FN_QSPI0_SPCLK, FN_WE0_N,
-	FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N,
-	FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N,
-	FN_QSPI0_IO2, FN_CS0_N,
-	FN_QSPI0_IO3, FN_RD_N,
-	FN_QSPI0_SSL, FN_WE1_N,
-
-	/* IPSR4 */
-	FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A,
-	FN_DU0_DR0, FN_RX5_C, FN_SCL2_D, FN_A0,
-	FN_DU0_DR1, FN_TX5_C, FN_SDA2_D, FN_A1,
-	FN_DU0_DR2, FN_RX0_D, FN_SCL0_E, FN_A2,
-	FN_DU0_DR3, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, FN_A3,
-	FN_DU0_DR4, FN_RX1_D, FN_A4,
-	FN_DU0_DR5, FN_TX1_D, FN_PWM1_B, FN_A5,
-	FN_DU0_DR6, FN_RX2_C, FN_A6,
-
-	/* IPSR5 */
-	FN_DU0_DR7, FN_TX2_C, FN_PWM2_B, FN_A7,
-	FN_DU0_DG0, FN_RX3_B, FN_SCL3_D, FN_A8,
-	FN_DU0_DG1, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, FN_A9,
-	FN_DU0_DG2, FN_RX4_D, FN_A10,
-	FN_DU0_DG3, FN_TX4_D, FN_PWM4_B, FN_A11,
-	FN_DU0_DG4, FN_HRX0_A, FN_A12,
-	FN_DU0_DG5, FN_HTX0_A, FN_PWM5_B, FN_A13,
-	FN_DU0_DG6, FN_HRX1_C, FN_A14,
-
-	/* IPSR6 */
-	FN_DU0_DG7, FN_HTX1_C, FN_PWM6_B, FN_A15,
-	FN_DU0_DB0, FN_SCL4_D, FN_CAN0_RX_C, FN_A16,
-	FN_DU0_DB1, FN_SDA4_D, FN_CAN0_TX_C, FN_A17,
-	FN_DU0_DB2, FN_HCTS0_N, FN_A18,
-	FN_DU0_DB3, FN_HRTS0_N, FN_A19,
-	FN_DU0_DB4, FN_HCTS1_N_C, FN_A20,
-	FN_DU0_DB5, FN_HRTS1_N_C, FN_A21,
-	FN_DU0_DB6, FN_A22,
-
-	/* IPSR7 */
-	FN_DU0_DB7, FN_A23,
-	FN_DU0_DOTCLKIN, FN_A24,
-	FN_DU0_DOTCLKOUT0, FN_A25,
-	FN_DU0_DOTCLKOUT1, FN_MSIOF2_RXD_B, FN_CS1_N_A26,
-	FN_DU0_EXHSYNC_DU0_HSYNC, FN_MSIOF2_TXD_B, FN_DREQ0_N,
-	FN_DU0_EXVSYNC_DU0_VSYNC, FN_MSIOF2_SYNC_B, FN_DACK0,
-	FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_MSIOF2_SCK_B, FN_DRACK0,
-	FN_DU0_DISP, FN_CAN1_RX_C,
-
-	/* IPSR8 */
-	FN_DU0_CDE, FN_CAN1_TX_C,
-	FN_VI1_CLK, FN_AVB_RX_CLK, FN_ETH_REF_CLK,
-	FN_VI1_DATA0, FN_AVB_RX_DV, FN_ETH_CRS_DV,
-	FN_VI1_DATA1, FN_AVB_RXD0, FN_ETH_RXD0,
-	FN_VI1_DATA2, FN_AVB_RXD1, FN_ETH_RXD1,
-	FN_VI1_DATA3, FN_AVB_RXD2, FN_ETH_MDIO,
-	FN_VI1_DATA4, FN_AVB_RXD3, FN_ETH_RX_ER,
-	FN_VI1_DATA5, FN_AVB_RXD4, FN_ETH_LINK,
-
-	/* IPSR9 */
-	FN_VI1_DATA6, FN_AVB_RXD5, FN_ETH_TXD1,
-	FN_VI1_DATA7, FN_AVB_RXD6, FN_ETH_TX_EN,
-	FN_VI1_CLKENB, FN_SCL3_A, FN_AVB_RXD7, FN_ETH_MAGIC,
-	FN_VI1_FIELD, FN_SDA3_A, FN_AVB_RX_ER, FN_ETH_TXD0,
-	FN_VI1_HSYNC_N,	FN_RX0_B, FN_SCL0_C, FN_AVB_GTXREFCLK, FN_ETH_MDC,
-	FN_VI1_VSYNC_N,	FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_CLK,
-	FN_VI1_DATA8, FN_SCL2_B, FN_AVB_TX_EN,
-	FN_VI1_DATA9, FN_SDA2_B, FN_AVB_TXD0,
-
-	/* IPSR10 */
-	FN_VI1_DATA10, FN_CAN0_RX_B, FN_AVB_TXD1,
-	FN_VI1_DATA11, FN_CAN0_TX_B, FN_AVB_TXD2,
-	FN_AVB_TXD3, FN_AUDIO_CLKA_B, FN_SSI_SCK1_D, FN_RX5_F, FN_MSIOF0_RXD_B,
-	FN_AVB_TXD4, FN_AUDIO_CLKB_B, FN_SSI_WS1_D, FN_TX5_F, FN_MSIOF0_TXD_B,
-	FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, FN_SSI_SDATA1_D, FN_MSIOF0_SCK_B,
-	FN_SCL0_A, FN_RX0_C, FN_PWM5_A,	FN_TCLK1_B, FN_AVB_TXD6, FN_CAN1_RX_D, FN_MSIOF0_SYNC_B,
-	FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK, FN_CAN1_TX_D, FN_DVC_MUTE,
-	FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, FN_SSI_SCK6_B, FN_VI0_G0,
-
-	/* IPSR11 */
-	FN_SDA1_A, FN_TX4_A, FN_DU1_DR1, FN_SSI_WS6_B, FN_VI0_G1,
-	FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2,
-	FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3,
-	FN_MSIOF0_SCK_A, FN_IRQ0, FN_DU1_DR4, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4,
-	FN_MSIOF0_SYNC_A, FN_PWM1_A, FN_DU1_DR5, FN_QSPI1_IO2, FN_SSI_SDATA7_B,
-	FN_MSIOF0_SS1_A, FN_DU1_DR6, FN_QSPI1_IO3, FN_SSI_SDATA8_B,
-	FN_MSIOF0_SS2_A, FN_DU1_DR7, FN_QSPI1_SSL,
-	FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A,
-
-	/* IPSR12 */
-	FN_HTX1_A, FN_SDA4_A, FN_DU1_DG1, FN_TX0_A,
-	FN_HCTS1_N_A, FN_PWM2_A, FN_DU1_DG2, FN_REMOCON_B,
-	FN_HRTS1_N_A, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1,
-	FN_SD2_CLK, FN_HSCK1, FN_DU1_DG4, FN_SSI_SCK1_B,
-	FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5, FN_SSI_SCK2_B, FN_PWM3_A,
-	FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6, FN_SSI_SDATA1_B,
-	FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B,
-	FN_SD2_DAT2, FN_RX2_A, FN_DU1_DB0, FN_SSI_SDATA2_B,
-
-	/* IPSR13 */
-	FN_SD2_DAT3, FN_TX2_A, FN_DU1_DB1, FN_SSI_WS9_B,
-	FN_SD2_CD, FN_SCIF2_SCK_A, FN_DU1_DB2, FN_SSI_SCK9_B,
-	FN_SD2_WP, FN_SCIF3_SCK, FN_DU1_DB3, FN_SSI_SDATA9_B,
-	FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4, FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B,
-	FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B,
-	FN_SCL2_A, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C, FN_SSI_SCK4_B,
-	FN_SDA2_A, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
-	FN_SSI_SCK5_A, FN_DU1_DOTCLKOUT1,
-
-	/* IPSR14 */
-	FN_SSI_WS5_A, FN_SCL3_C, FN_DU1_DOTCLKIN,
-	FN_SSI_SDATA5_A, FN_SDA3_C, FN_DU1_DOTCLKOUT0,
-	FN_SSI_SCK6_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
-	FN_SSI_WS6_A, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC,
-	FN_SSI_SDATA6_A, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC,
-	FN_SSI_SCK78_A, FN_SDA4_E, FN_DU1_DISP,
-	FN_SSI_WS78_A, FN_SCL4_E, FN_DU1_CDE,
-	FN_SSI_SDATA7_A, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_VI0_G5,
-
-	/* IPSR15 */
-	FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, FN_VI0_G6,
-	FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, FN_VI0_G7,
-	FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, FN_VI0_R0,
-	FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, FN_DACK1, FN_VI0_R1,
-	FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, FN_CAN1_RX_A, FN_DREQ1_N, FN_VI0_R2,
-	FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, FN_CAN1_TX_A, FN_DREQ2_N, FN_VI0_R3,
-	FN_SSI_SCK4_A, FN_AVB_MAGIC, FN_VI0_R4,
-	FN_SSI_WS4_A, FN_AVB_PHY_INT, FN_VI0_R5,
-
-	/* IPSR16 */
-	FN_SSI_SDATA4_A, FN_AVB_CRS, FN_VI0_R6,
-	FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A, FN_DACK2, FN_VI0_CLK, FN_AVB_COL,
-	FN_SSI_SDATA8_A, FN_RX1_B, FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE_B,	FN_VI0_R7,
-	FN_SSI_WS1_A, FN_TX1_B, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0,
-	FN_SSI_SDATA1_A, FN_HRX1_B, FN_VI0_DATA1_VI0_B1,
-	FN_SSI_SCK2_A, FN_HTX1_B, FN_AVB_TXD7, FN_VI0_DATA2_VI0_B2,
-	FN_SSI_WS2_A, FN_HCTS1_N_B, FN_AVB_TX_ER, FN_VI0_DATA3_VI0_B3,
-	FN_SSI_SDATA2_A, FN_HRTS1_N_B, FN_VI0_DATA4_VI0_B4,
-
-	/* IPSR17 */
-	FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, FN_EX_WAIT1, FN_VI0_DATA5_VI0_B5,
-	FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, FN_VI0_DATA6_VI0_B6,
-	FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, FN_VI0_DATA7_VI0_B7,
-	FN_AUDIO_CLKA_A, FN_SCL0_B, FN_VI0_CLKENB,
-	FN_AUDIO_CLKB_A, FN_SDA0_B, FN_VI0_FIELD,
-	FN_AUDIO_CLKC_A, FN_SCL4_B, FN_VI0_HSYNC_N,
-	FN_AUDIO_CLKOUT_A, FN_SDA4_B, FN_VI0_VSYNC_N,
-
-	/* MOD_SEL0 */
-	FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3,
-	FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
-	FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
-	FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
-	FN_SEL_I2C04_0, FN_SEL_I2C04_1,	FN_SEL_I2C04_2, FN_SEL_I2C04_3, FN_SEL_I2C04_4,
-	FN_SEL_I2C03_0,	FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, FN_SEL_I2C03_4,
-	FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
-	FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4,
-	FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, FN_SEL_I2C00_4,
-	FN_SEL_AVB_0, FN_SEL_AVB_1,
-
-	/* MOD_SEL1 */
-	FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
-	FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,	FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, FN_SEL_SCIF5_4, FN_SEL_SCIF5_5,
-	FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,	FN_SEL_SCIF4_4,
-	FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
-	FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
-	FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1,
-	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,	FN_SEL_SCIF1_3,
-	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,	FN_SEL_SCIF0_3,
-	FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2,
-	FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
-	FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1,
-	FN_SEL_RCN_0, FN_SEL_RCN_1,
-	FN_SEL_TMU2_0, FN_SEL_TMU2_1,
-	FN_SEL_TMU1_0, FN_SEL_TMU1_1,
-	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
-	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
-
-	/* MOD_SEL2 */
-	FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2,
-	FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2,
-	FN_SEL_SSI9_0, FN_SEL_SSI9_1,
-	FN_SEL_SSI8_0, FN_SEL_SSI8_1,
-	FN_SEL_SSI7_0, FN_SEL_SSI7_1,
-	FN_SEL_SSI6_0, FN_SEL_SSI6_1,
-	FN_SEL_SSI5_0, FN_SEL_SSI5_1,
-	FN_SEL_SSI4_0, FN_SEL_SSI4_1,
-	FN_SEL_SSI2_0, FN_SEL_SSI2_1,
-	FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3,
-	FN_SEL_SSI0_0, FN_SEL_SSI0_1,
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-
-	USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
-	CLKOUT_MARK, MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
-	MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
-	MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, MMC0_D6_MARK,
-	MMC0_D7_MARK,
-
-	/* IPSR0 */
-	SD0_CLK_MARK, SSI_SCK1_C_MARK, RX3_C_MARK,
-	SD0_CMD_MARK, SSI_WS1_C_MARK, TX3_C_MARK,
-	SD0_DAT0_MARK, SSI_SDATA1_C_MARK, RX4_E_MARK,
-	SD0_DAT1_MARK, SSI_SCK0129_B_MARK, TX4_E_MARK,
-	SD0_DAT2_MARK, SSI_WS0129_B_MARK, RX5_E_MARK,
-	SD0_DAT3_MARK, SSI_SDATA0_B_MARK, TX5_E_MARK,
-	SD0_CD_MARK, CAN0_RX_A_MARK,
-	SD0_WP_MARK, IRQ7_MARK,	CAN0_TX_A_MARK,
-
-	/* IPSR1 */
-	MMC0_D4_MARK, SD1_CD_MARK,
-	MMC0_D5_MARK, SD1_WP_MARK,
-	D0_MARK, SCL3_B_MARK, RX5_B_MARK, IRQ4_MARK, MSIOF2_RXD_C_MARK,	SSI_SDATA5_B_MARK,
-	D1_MARK, SDA3_B_MARK, TX5_B_MARK, MSIOF2_TXD_C_MARK, SSI_WS5_B_MARK,
-	D2_MARK, RX4_B_MARK, SCL0_D_MARK, PWM1_C_MARK, MSIOF2_SCK_C_MARK, SSI_SCK5_B_MARK,
-	D3_MARK, TX4_B_MARK, SDA0_D_MARK, PWM0_A_MARK, MSIOF2_SYNC_C_MARK,
-	D4_MARK, IRQ3_MARK, TCLK1_A_MARK, PWM6_C_MARK,
-	D5_MARK, HRX2_MARK, SCL1_B_MARK, PWM2_C_MARK, TCLK2_B_MARK,
-
-	/* IPSR2 */
-	D6_MARK, HTX2_MARK, SDA1_B_MARK, PWM4_C_MARK,
-	D7_MARK, HSCK2_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
-	D8_MARK, HCTS2_N_MARK, RX1_C_MARK, SCL1_D_MARK,	PWM3_C_MARK,
-	D9_MARK, HRTS2_N_MARK, TX1_C_MARK, SDA1_D_MARK,
-	D10_MARK, MSIOF2_RXD_A_MARK, HRX0_B_MARK,
-	D11_MARK, MSIOF2_TXD_A_MARK, HTX0_B_MARK,
-	D12_MARK, MSIOF2_SCK_A_MARK, HSCK0_MARK, CAN_CLK_C_MARK,
-	D13_MARK, MSIOF2_SYNC_A_MARK, RX4_C_MARK,
-
-	/* IPSR3 */
-	D14_MARK, MSIOF2_SS1_MARK, TX4_C_MARK, CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_A_MARK,
-	D15_MARK, MSIOF2_SS2_MARK, PWM4_A_MARK, CAN1_TX_B_MARK, IRQ2_MARK, AVB_AVTP_MATCH_A_MARK,
-	QSPI0_SPCLK_MARK, WE0_N_MARK,
-	QSPI0_MOSI_QSPI0_IO0_MARK, BS_N_MARK,
-	QSPI0_MISO_QSPI0_IO1_MARK, RD_WR_N_MARK,
-	QSPI0_IO2_MARK, CS0_N_MARK,
-	QSPI0_IO3_MARK, RD_N_MARK,
-	QSPI0_SSL_MARK, WE1_N_MARK,
-
-	/* IPSR4 */
-	EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_A_MARK,
-	DU0_DR0_MARK, RX5_C_MARK, SCL2_D_MARK, A0_MARK,
-	DU0_DR1_MARK, TX5_C_MARK, SDA2_D_MARK, A1_MARK,
-	DU0_DR2_MARK, RX0_D_MARK, SCL0_E_MARK, A2_MARK,
-	DU0_DR3_MARK, TX0_D_MARK, SDA0_E_MARK, PWM0_B_MARK, A3_MARK,
-	DU0_DR4_MARK, RX1_D_MARK, A4_MARK,
-	DU0_DR5_MARK, TX1_D_MARK, PWM1_B_MARK, A5_MARK,
-	DU0_DR6_MARK, RX2_C_MARK, A6_MARK,
-
-	/* IPSR5 */
-	DU0_DR7_MARK, TX2_C_MARK, PWM2_B_MARK, A7_MARK,
-	DU0_DG0_MARK, RX3_B_MARK, SCL3_D_MARK, A8_MARK,
-	DU0_DG1_MARK, TX3_B_MARK, SDA3_D_MARK, PWM3_B_MARK, A9_MARK,
-	DU0_DG2_MARK, RX4_D_MARK, A10_MARK,
-	DU0_DG3_MARK, TX4_D_MARK, PWM4_B_MARK, A11_MARK,
-	DU0_DG4_MARK, HRX0_A_MARK, A12_MARK,
-	DU0_DG5_MARK, HTX0_A_MARK, PWM5_B_MARK, A13_MARK,
-	DU0_DG6_MARK, HRX1_C_MARK, A14_MARK,
-
-	/* IPSR6 */
-	DU0_DG7_MARK, HTX1_C_MARK, PWM6_B_MARK, A15_MARK,
-	DU0_DB0_MARK, SCL4_D_MARK, CAN0_RX_C_MARK, A16_MARK,
-	DU0_DB1_MARK, SDA4_D_MARK, CAN0_TX_C_MARK, A17_MARK,
-	DU0_DB2_MARK, HCTS0_N_MARK, A18_MARK,
-	DU0_DB3_MARK, HRTS0_N_MARK, A19_MARK,
-	DU0_DB4_MARK, HCTS1_N_C_MARK, A20_MARK,
-	DU0_DB5_MARK, HRTS1_N_C_MARK, A21_MARK,
-	DU0_DB6_MARK, A22_MARK,
-
-	/* IPSR7 */
-	DU0_DB7_MARK, A23_MARK,
-	DU0_DOTCLKIN_MARK, A24_MARK,
-	DU0_DOTCLKOUT0_MARK, A25_MARK,
-	DU0_DOTCLKOUT1_MARK, MSIOF2_RXD_B_MARK, CS1_N_A26_MARK,
-	DU0_EXHSYNC_DU0_HSYNC_MARK, MSIOF2_TXD_B_MARK, DREQ0_N_MARK,
-	DU0_EXVSYNC_DU0_VSYNC_MARK, MSIOF2_SYNC_B_MARK, DACK0_MARK,
-	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, MSIOF2_SCK_B_MARK, DRACK0_MARK,
-	DU0_DISP_MARK, CAN1_RX_C_MARK,
-
-	/* IPSR8 */
-	DU0_CDE_MARK, CAN1_TX_C_MARK,
-	VI1_CLK_MARK, AVB_RX_CLK_MARK, ETH_REF_CLK_MARK,
-	VI1_DATA0_MARK, AVB_RX_DV_MARK, ETH_CRS_DV_MARK,
-	VI1_DATA1_MARK, AVB_RXD0_MARK, ETH_RXD0_MARK,
-	VI1_DATA2_MARK, AVB_RXD1_MARK, ETH_RXD1_MARK,
-	VI1_DATA3_MARK, AVB_RXD2_MARK, ETH_MDIO_MARK,
-	VI1_DATA4_MARK, AVB_RXD3_MARK, ETH_RX_ER_MARK,
-	VI1_DATA5_MARK, AVB_RXD4_MARK, ETH_LINK_MARK,
-
-	/* IPSR9 */
-	VI1_DATA6_MARK, AVB_RXD5_MARK, ETH_TXD1_MARK,
-	VI1_DATA7_MARK,	AVB_RXD6_MARK, ETH_TX_EN_MARK,
-	VI1_CLKENB_MARK, SCL3_A_MARK, AVB_RXD7_MARK, ETH_MAGIC_MARK,
-	VI1_FIELD_MARK, SDA3_A_MARK, AVB_RX_ER_MARK, ETH_TXD0_MARK,
-	VI1_HSYNC_N_MARK, RX0_B_MARK, SCL0_C_MARK, AVB_GTXREFCLK_MARK, ETH_MDC_MARK,
-	VI1_VSYNC_N_MARK, TX0_B_MARK, SDA0_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_CLK_MARK,
-	VI1_DATA8_MARK, SCL2_B_MARK, AVB_TX_EN_MARK,
-	VI1_DATA9_MARK, SDA2_B_MARK, AVB_TXD0_MARK,
-
-	/* IPSR10 */
-	VI1_DATA10_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK,
-	VI1_DATA11_MARK, CAN0_TX_B_MARK, AVB_TXD2_MARK,
-	AVB_TXD3_MARK, AUDIO_CLKA_B_MARK, SSI_SCK1_D_MARK, RX5_F_MARK, MSIOF0_RXD_B_MARK,
-	AVB_TXD4_MARK, AUDIO_CLKB_B_MARK, SSI_WS1_D_MARK, TX5_F_MARK, MSIOF0_TXD_B_MARK,
-	AVB_TXD5_MARK, SCIF_CLK_B_MARK, AUDIO_CLKC_B_MARK, SSI_SDATA1_D_MARK, MSIOF0_SCK_B_MARK,
-	SCL0_A_MARK, RX0_C_MARK, PWM5_A_MARK, TCLK1_B_MARK, AVB_TXD6_MARK, CAN1_RX_D_MARK, MSIOF0_SYNC_B_MARK,
-	SDA0_A_MARK, TX0_C_MARK, IRQ5_MARK, CAN_CLK_A_MARK, AVB_GTX_CLK_MARK, CAN1_TX_D_MARK, DVC_MUTE_MARK,
-	SCL1_A_MARK, RX4_A_MARK, PWM5_D_MARK, DU1_DR0_MARK, SSI_SCK6_B_MARK, VI0_G0_MARK,
-
-	/* IPSR11 */
-	SDA1_A_MARK, TX4_A_MARK, DU1_DR1_MARK, SSI_WS6_B_MARK, VI0_G1_MARK,
-	MSIOF0_RXD_A_MARK, RX5_A_MARK, SCL2_C_MARK, DU1_DR2_MARK, QSPI1_MOSI_QSPI1_IO0_MARK, SSI_SDATA6_B_MARK, VI0_G2_MARK,
-	MSIOF0_TXD_A_MARK, TX5_A_MARK, SDA2_C_MARK, DU1_DR3_MARK, QSPI1_MISO_QSPI1_IO1_MARK, SSI_WS78_B_MARK, VI0_G3_MARK,
-	MSIOF0_SCK_A_MARK, IRQ0_MARK, DU1_DR4_MARK, QSPI1_SPCLK_MARK, SSI_SCK78_B_MARK, VI0_G4_MARK,
-	MSIOF0_SYNC_A_MARK, PWM1_A_MARK, DU1_DR5_MARK, QSPI1_IO2_MARK, SSI_SDATA7_B_MARK,
-	MSIOF0_SS1_A_MARK, DU1_DR6_MARK, QSPI1_IO3_MARK, SSI_SDATA8_B_MARK,
-	MSIOF0_SS2_A_MARK, DU1_DR7_MARK, QSPI1_SSL_MARK,
-	HRX1_A_MARK, SCL4_A_MARK, PWM6_A_MARK, DU1_DG0_MARK, RX0_A_MARK,
-
-	/* IPSR12 */
-	HTX1_A_MARK, SDA4_A_MARK, DU1_DG1_MARK, TX0_A_MARK,
-	HCTS1_N_A_MARK, PWM2_A_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
-	HRTS1_N_A_MARK, DU1_DG3_MARK, SSI_WS1_B_MARK, IRQ1_MARK,
-	SD2_CLK_MARK, HSCK1_MARK, DU1_DG4_MARK, SSI_SCK1_B_MARK,
-	SD2_CMD_MARK, SCIF1_SCK_A_MARK, TCLK2_A_MARK, DU1_DG5_MARK, SSI_SCK2_B_MARK, PWM3_A_MARK,
-	SD2_DAT0_MARK, RX1_A_MARK, SCL1_E_MARK, DU1_DG6_MARK, SSI_SDATA1_B_MARK,
-	SD2_DAT1_MARK, TX1_A_MARK, SDA1_E_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
-	SD2_DAT2_MARK, RX2_A_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
-
-	/* IPSR13 */
-	SD2_DAT3_MARK, TX2_A_MARK, DU1_DB1_MARK, SSI_WS9_B_MARK,
-	SD2_CD_MARK, SCIF2_SCK_A_MARK, DU1_DB2_MARK, SSI_SCK9_B_MARK,
-	SD2_WP_MARK, SCIF3_SCK_MARK, DU1_DB3_MARK, SSI_SDATA9_B_MARK,
-	RX3_A_MARK, SCL1_C_MARK, MSIOF1_RXD_B_MARK, DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SDATA4_B_MARK,
-	TX3_A_MARK, SDA1_C_MARK, MSIOF1_TXD_B_MARK, DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
-	SCL2_A_MARK, MSIOF1_SCK_B_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK, SSI_SCK4_B_MARK,
-	SDA2_A_MARK, MSIOF1_SYNC_B_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
-	SSI_SCK5_A_MARK, DU1_DOTCLKOUT1_MARK,
-
-	/* IPSR14 */
-	SSI_WS5_A_MARK, SCL3_C_MARK, DU1_DOTCLKIN_MARK,
-	SSI_SDATA5_A_MARK, SDA3_C_MARK, DU1_DOTCLKOUT0_MARK,
-	SSI_SCK6_A_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
-	SSI_WS6_A_MARK, SCL4_C_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
-	SSI_SDATA6_A_MARK, SDA4_C_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK,
-	SSI_SCK78_A_MARK, SDA4_E_MARK, DU1_DISP_MARK,
-	SSI_WS78_A_MARK, SCL4_E_MARK, DU1_CDE_MARK,
-	SSI_SDATA7_A_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, VI0_G5_MARK,
-
-	/* IPSR15 */
-	SSI_SCK0129_A_MARK, MSIOF1_RXD_A_MARK, RX5_D_MARK, VI0_G6_MARK,
-	SSI_WS0129_A_MARK, MSIOF1_TXD_A_MARK, TX5_D_MARK, VI0_G7_MARK,
-	SSI_SDATA0_A_MARK, MSIOF1_SYNC_A_MARK, PWM0_C_MARK, VI0_R0_MARK,
-	SSI_SCK34_MARK, MSIOF1_SCK_A_MARK, AVB_MDC_MARK, DACK1_MARK, VI0_R1_MARK,
-	SSI_WS34_MARK, MSIOF1_SS1_A_MARK, AVB_MDIO_MARK, CAN1_RX_A_MARK, DREQ1_N_MARK, VI0_R2_MARK,
-	SSI_SDATA3_MARK, MSIOF1_SS2_A_MARK, AVB_LINK_MARK, CAN1_TX_A_MARK, DREQ2_N_MARK, VI0_R3_MARK,
-	SSI_SCK4_A_MARK, AVB_MAGIC_MARK, VI0_R4_MARK,
-	SSI_WS4_A_MARK, AVB_PHY_INT_MARK, VI0_R5_MARK,
-
-	/* IPSR16 */
-	SSI_SDATA4_A_MARK, AVB_CRS_MARK, VI0_R6_MARK,
-	SSI_SCK1_A_MARK, SCIF1_SCK_B_MARK, PWM1_D_MARK, IRQ9_MARK, REMOCON_A_MARK, DACK2_MARK, VI0_CLK_MARK, AVB_COL_MARK,
-	SSI_SDATA8_A_MARK, RX1_B_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_B_MARK, VI0_R7_MARK,
-	SSI_WS1_A_MARK,	TX1_B_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_B_MARK, VI0_DATA0_VI0_B0_MARK,
-	SSI_SDATA1_A_MARK, HRX1_B_MARK, VI0_DATA1_VI0_B1_MARK,
-	SSI_SCK2_A_MARK, HTX1_B_MARK, AVB_TXD7_MARK, VI0_DATA2_VI0_B2_MARK,
-	SSI_WS2_A_MARK, HCTS1_N_B_MARK, AVB_TX_ER_MARK, VI0_DATA3_VI0_B3_MARK,
-	SSI_SDATA2_A_MARK, HRTS1_N_B_MARK, VI0_DATA4_VI0_B4_MARK,
-
-	/* IPSR17 */
-	SSI_SCK9_A_MARK, RX2_B_MARK, SCL3_E_MARK, EX_WAIT1_MARK, VI0_DATA5_VI0_B5_MARK,
-	SSI_WS9_A_MARK, TX2_B_MARK, SDA3_E_MARK, VI0_DATA6_VI0_B6_MARK,
-	SSI_SDATA9_A_MARK, SCIF2_SCK_B_MARK, PWM2_D_MARK, VI0_DATA7_VI0_B7_MARK,
-	AUDIO_CLKA_A_MARK, SCL0_B_MARK, VI0_CLKENB_MARK,
-	AUDIO_CLKB_A_MARK, SDA0_B_MARK,	VI0_FIELD_MARK,
-	AUDIO_CLKC_A_MARK, SCL4_B_MARK, VI0_HSYNC_N_MARK,
-	AUDIO_CLKOUT_A_MARK, SDA4_B_MARK, VI0_VSYNC_N_MARK,
-
-	PINMUX_MARK_END,
-};
-
-static const u16 pinmux_data[] = {
-	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
-
-	PINMUX_SINGLE(USB0_PWEN),
-	PINMUX_SINGLE(USB0_OVC),
-	PINMUX_SINGLE(USB1_PWEN),
-	PINMUX_SINGLE(USB1_OVC),
-	PINMUX_SINGLE(CLKOUT),
-	PINMUX_SINGLE(MMC0_CLK_SDHI1_CLK),
-	PINMUX_SINGLE(MMC0_CMD_SDHI1_CMD),
-	PINMUX_SINGLE(MMC0_D0_SDHI1_D0),
-	PINMUX_SINGLE(MMC0_D1_SDHI1_D1),
-	PINMUX_SINGLE(MMC0_D2_SDHI1_D2),
-	PINMUX_SINGLE(MMC0_D3_SDHI1_D3),
-	PINMUX_SINGLE(MMC0_D6),
-	PINMUX_SINGLE(MMC0_D7),
-
-	/* IPSR0 */
-	PINMUX_IPSR_GPSR(IP0_3_0, SD0_CLK),
-	PINMUX_IPSR_MSEL(IP0_3_0, SSI_SCK1_C, SEL_SSI1_2),
-	PINMUX_IPSR_MSEL(IP0_3_0, RX3_C, SEL_SCIF3_2),
-	PINMUX_IPSR_GPSR(IP0_7_4, SD0_CMD),
-	PINMUX_IPSR_MSEL(IP0_7_4, SSI_WS1_C, SEL_SSI1_2),
-	PINMUX_IPSR_MSEL(IP0_7_4, TX3_C, SEL_SCIF3_2),
-	PINMUX_IPSR_GPSR(IP0_11_8, SD0_DAT0),
-	PINMUX_IPSR_MSEL(IP0_11_8, SSI_SDATA1_C, SEL_SSI1_2),
-	PINMUX_IPSR_MSEL(IP0_11_8, RX4_E, SEL_SCIF4_4),
-	PINMUX_IPSR_GPSR(IP0_15_12, SD0_DAT1),
-	PINMUX_IPSR_MSEL(IP0_15_12, SSI_SCK0129_B, SEL_SSI0_1),
-	PINMUX_IPSR_MSEL(IP0_15_12, TX4_E, SEL_SCIF4_4),
-	PINMUX_IPSR_GPSR(IP0_19_16, SD0_DAT2),
-	PINMUX_IPSR_MSEL(IP0_19_16, SSI_WS0129_B, SEL_SSI0_1),
-	PINMUX_IPSR_MSEL(IP0_19_16, RX5_E, SEL_SCIF5_4),
-	PINMUX_IPSR_GPSR(IP0_23_20, SD0_DAT3),
-	PINMUX_IPSR_MSEL(IP0_23_20, SSI_SDATA0_B, SEL_SSI0_1),
-	PINMUX_IPSR_MSEL(IP0_23_20, TX5_E, SEL_SCIF5_4),
-	PINMUX_IPSR_GPSR(IP0_27_24, SD0_CD),
-	PINMUX_IPSR_MSEL(IP0_27_24, CAN0_RX_A, SEL_CAN0_0),
-	PINMUX_IPSR_GPSR(IP0_31_28, SD0_WP),
-	PINMUX_IPSR_GPSR(IP0_31_28, IRQ7),
-	PINMUX_IPSR_MSEL(IP0_31_28, CAN0_TX_A, SEL_CAN0_0),
-
-	/* IPSR1 */
-	PINMUX_IPSR_GPSR(IP1_3_0, MMC0_D4),
-	PINMUX_IPSR_GPSR(IP1_3_0, SD1_CD),
-	PINMUX_IPSR_GPSR(IP1_7_4, MMC0_D5),
-	PINMUX_IPSR_GPSR(IP1_7_4, SD1_WP),
-	PINMUX_IPSR_GPSR(IP1_11_8, D0),
-	PINMUX_IPSR_MSEL(IP1_11_8, SCL3_B, SEL_I2C03_1),
-	PINMUX_IPSR_MSEL(IP1_11_8, RX5_B, SEL_SCIF5_1),
-	PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
-	PINMUX_IPSR_MSEL(IP1_11_8, MSIOF2_RXD_C, SEL_MSIOF2_2),
-	PINMUX_IPSR_MSEL(IP1_11_8, SSI_SDATA5_B, SEL_SSI5_1),
-	PINMUX_IPSR_GPSR(IP1_15_12, D1),
-	PINMUX_IPSR_MSEL(IP1_15_12, SDA3_B, SEL_I2C03_1),
-	PINMUX_IPSR_MSEL(IP1_15_12, TX5_B, SEL_SCIF5_1),
-	PINMUX_IPSR_MSEL(IP1_15_12, MSIOF2_TXD_C, SEL_MSIOF2_2),
-	PINMUX_IPSR_MSEL(IP1_15_12, SSI_WS5_B, SEL_SSI5_1),
-	PINMUX_IPSR_GPSR(IP1_19_16, D2),
-	PINMUX_IPSR_MSEL(IP1_19_16, RX4_B, SEL_SCIF4_1),
-	PINMUX_IPSR_MSEL(IP1_19_16, SCL0_D, SEL_I2C00_3),
-	PINMUX_IPSR_GPSR(IP1_19_16, PWM1_C),
-	PINMUX_IPSR_MSEL(IP1_19_16, MSIOF2_SCK_C, SEL_MSIOF2_2),
-	PINMUX_IPSR_MSEL(IP1_19_16, SSI_SCK5_B, SEL_SSI5_1),
-	PINMUX_IPSR_GPSR(IP1_23_20, D3),
-	PINMUX_IPSR_MSEL(IP1_23_20, TX4_B, SEL_SCIF4_1),
-	PINMUX_IPSR_MSEL(IP1_23_20, SDA0_D, SEL_I2C00_3),
-	PINMUX_IPSR_GPSR(IP1_23_20, PWM0_A),
-	PINMUX_IPSR_MSEL(IP1_23_20, MSIOF2_SYNC_C, SEL_MSIOF2_2),
-	PINMUX_IPSR_GPSR(IP1_27_24, D4),
-	PINMUX_IPSR_GPSR(IP1_27_24, IRQ3),
-	PINMUX_IPSR_MSEL(IP1_27_24, TCLK1_A, SEL_TMU1_0),
-	PINMUX_IPSR_GPSR(IP1_27_24, PWM6_C),
-	PINMUX_IPSR_GPSR(IP1_31_28, D5),
-	PINMUX_IPSR_GPSR(IP1_31_28, HRX2),
-	PINMUX_IPSR_MSEL(IP1_31_28, SCL1_B, SEL_I2C01_1),
-	PINMUX_IPSR_GPSR(IP1_31_28, PWM2_C),
-	PINMUX_IPSR_MSEL(IP1_31_28, TCLK2_B, SEL_TMU2_1),
-
-	/* IPSR2 */
-	PINMUX_IPSR_GPSR(IP2_3_0, D6),
-	PINMUX_IPSR_GPSR(IP2_3_0, HTX2),
-	PINMUX_IPSR_MSEL(IP2_3_0, SDA1_B, SEL_I2C01_1),
-	PINMUX_IPSR_GPSR(IP2_3_0, PWM4_C),
-	PINMUX_IPSR_GPSR(IP2_7_4, D7),
-	PINMUX_IPSR_GPSR(IP2_7_4, HSCK2),
-	PINMUX_IPSR_MSEL(IP2_7_4, SCIF1_SCK_C, SEL_SCIF1_2),
-	PINMUX_IPSR_GPSR(IP2_7_4, IRQ6),
-	PINMUX_IPSR_GPSR(IP2_7_4, PWM5_C),
-	PINMUX_IPSR_GPSR(IP2_11_8, D8),
-	PINMUX_IPSR_GPSR(IP2_11_8, HCTS2_N),
-	PINMUX_IPSR_MSEL(IP2_11_8, RX1_C, SEL_SCIF1_2),
-	PINMUX_IPSR_MSEL(IP2_11_8, SCL1_D, SEL_I2C01_3),
-	PINMUX_IPSR_GPSR(IP2_11_8, PWM3_C),
-	PINMUX_IPSR_GPSR(IP2_15_12, D9),
-	PINMUX_IPSR_GPSR(IP2_15_12, HRTS2_N),
-	PINMUX_IPSR_MSEL(IP2_15_12, TX1_C, SEL_SCIF1_2),
-	PINMUX_IPSR_MSEL(IP2_15_12, SDA1_D, SEL_I2C01_3),
-	PINMUX_IPSR_GPSR(IP2_19_16, D10),
-	PINMUX_IPSR_MSEL(IP2_19_16, MSIOF2_RXD_A, SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP2_19_16, HRX0_B, SEL_HSCIF0_1),
-	PINMUX_IPSR_GPSR(IP2_23_20, D11),
-	PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_TXD_A, SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP2_23_20, HTX0_B, SEL_HSCIF0_1),
-	PINMUX_IPSR_GPSR(IP2_27_24, D12),
-	PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SCK_A, SEL_MSIOF2_0),
-	PINMUX_IPSR_GPSR(IP2_27_24, HSCK0),
-	PINMUX_IPSR_MSEL(IP2_27_24, CAN_CLK_C, SEL_CANCLK_2),
-	PINMUX_IPSR_GPSR(IP2_31_28, D13),
-	PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP2_31_28, RX4_C, SEL_SCIF4_2),
-
-	/* IPSR3 */
-	PINMUX_IPSR_GPSR(IP3_3_0, D14),
-	PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SS1),
-	PINMUX_IPSR_MSEL(IP3_3_0, TX4_C, SEL_SCIF4_2),
-	PINMUX_IPSR_MSEL(IP3_3_0, CAN1_RX_B, SEL_CAN1_1),
-	PINMUX_IPSR_MSEL(IP3_3_0, AVB_AVTP_CAPTURE_A, SEL_AVB_0),
-	PINMUX_IPSR_GPSR(IP3_7_4, D15),
-	PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_SS2),
-	PINMUX_IPSR_GPSR(IP3_7_4, PWM4_A),
-	PINMUX_IPSR_MSEL(IP3_7_4, CAN1_TX_B, SEL_CAN1_1),
-	PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
-	PINMUX_IPSR_MSEL(IP3_7_4, AVB_AVTP_MATCH_A, SEL_AVB_0),
-	PINMUX_IPSR_GPSR(IP3_11_8, QSPI0_SPCLK),
-	PINMUX_IPSR_GPSR(IP3_11_8, WE0_N),
-	PINMUX_IPSR_GPSR(IP3_15_12, QSPI0_MOSI_QSPI0_IO0),
-	PINMUX_IPSR_GPSR(IP3_15_12, BS_N),
-	PINMUX_IPSR_GPSR(IP3_19_16, QSPI0_MISO_QSPI0_IO1),
-	PINMUX_IPSR_GPSR(IP3_19_16, RD_WR_N),
-	PINMUX_IPSR_GPSR(IP3_23_20, QSPI0_IO2),
-	PINMUX_IPSR_GPSR(IP3_23_20, CS0_N),
-	PINMUX_IPSR_GPSR(IP3_27_24, QSPI0_IO3),
-	PINMUX_IPSR_GPSR(IP3_27_24, RD_N),
-	PINMUX_IPSR_GPSR(IP3_31_28, QSPI0_SSL),
-	PINMUX_IPSR_GPSR(IP3_31_28, WE1_N),
-
-	/* IPSR4 */
-	PINMUX_IPSR_GPSR(IP4_3_0, EX_WAIT0),
-	PINMUX_IPSR_MSEL(IP4_3_0, CAN_CLK_B, SEL_CANCLK_1),
-	PINMUX_IPSR_MSEL(IP4_3_0, SCIF_CLK_A, SEL_SCIFCLK_0),
-	PINMUX_IPSR_GPSR(IP4_7_4, DU0_DR0),
-	PINMUX_IPSR_MSEL(IP4_7_4, RX5_C, SEL_SCIF5_2),
-	PINMUX_IPSR_MSEL(IP4_7_4, SCL2_D, SEL_I2C02_3),
-	PINMUX_IPSR_GPSR(IP4_7_4, A0),
-	PINMUX_IPSR_GPSR(IP4_11_8, DU0_DR1),
-	PINMUX_IPSR_MSEL(IP4_11_8, TX5_C, SEL_SCIF5_2),
-	PINMUX_IPSR_MSEL(IP4_11_8, SDA2_D, SEL_I2C02_3),
-	PINMUX_IPSR_GPSR(IP4_11_8, A1),
-	PINMUX_IPSR_GPSR(IP4_15_12, DU0_DR2),
-	PINMUX_IPSR_MSEL(IP4_15_12, RX0_D, SEL_SCIF0_3),
-	PINMUX_IPSR_MSEL(IP4_15_12, SCL0_E, SEL_I2C00_4),
-	PINMUX_IPSR_GPSR(IP4_15_12, A2),
-	PINMUX_IPSR_GPSR(IP4_19_16, DU0_DR3),
-	PINMUX_IPSR_MSEL(IP4_19_16, TX0_D, SEL_SCIF0_3),
-	PINMUX_IPSR_MSEL(IP4_19_16, SDA0_E, SEL_I2C00_4),
-	PINMUX_IPSR_GPSR(IP4_19_16, PWM0_B),
-	PINMUX_IPSR_GPSR(IP4_19_16, A3),
-	PINMUX_IPSR_GPSR(IP4_23_20, DU0_DR4),
-	PINMUX_IPSR_MSEL(IP4_23_20, RX1_D, SEL_SCIF1_3),
-	PINMUX_IPSR_GPSR(IP4_23_20, A4),
-	PINMUX_IPSR_GPSR(IP4_27_24, DU0_DR5),
-	PINMUX_IPSR_MSEL(IP4_27_24, TX1_D, SEL_SCIF1_3),
-	PINMUX_IPSR_GPSR(IP4_27_24, PWM1_B),
-	PINMUX_IPSR_GPSR(IP4_27_24, A5),
-	PINMUX_IPSR_GPSR(IP4_31_28, DU0_DR6),
-	PINMUX_IPSR_MSEL(IP4_31_28, RX2_C, SEL_SCIF2_2),
-	PINMUX_IPSR_GPSR(IP4_31_28, A6),
-
-	/* IPSR5 */
-	PINMUX_IPSR_GPSR(IP5_3_0, DU0_DR7),
-	PINMUX_IPSR_MSEL(IP5_3_0, TX2_C, SEL_SCIF2_2),
-	PINMUX_IPSR_GPSR(IP5_3_0, PWM2_B),
-	PINMUX_IPSR_GPSR(IP5_3_0, A7),
-	PINMUX_IPSR_GPSR(IP5_7_4, DU0_DG0),
-	PINMUX_IPSR_MSEL(IP5_7_4, RX3_B, SEL_SCIF3_1),
-	PINMUX_IPSR_MSEL(IP5_7_4, SCL3_D, SEL_I2C03_3),
-	PINMUX_IPSR_GPSR(IP5_7_4, A8),
-	PINMUX_IPSR_GPSR(IP5_11_8, DU0_DG1),
-	PINMUX_IPSR_MSEL(IP5_11_8, TX3_B, SEL_SCIF3_1),
-	PINMUX_IPSR_MSEL(IP5_11_8, SDA3_D, SEL_I2C03_3),
-	PINMUX_IPSR_GPSR(IP5_11_8, PWM3_B),
-	PINMUX_IPSR_GPSR(IP5_11_8, A9),
-	PINMUX_IPSR_GPSR(IP5_15_12, DU0_DG2),
-	PINMUX_IPSR_MSEL(IP5_15_12, RX4_D, SEL_SCIF4_3),
-	PINMUX_IPSR_GPSR(IP5_15_12, A10),
-	PINMUX_IPSR_GPSR(IP5_19_16, DU0_DG3),
-	PINMUX_IPSR_MSEL(IP5_19_16, TX4_D, SEL_SCIF4_3),
-	PINMUX_IPSR_GPSR(IP5_19_16, PWM4_B),
-	PINMUX_IPSR_GPSR(IP5_19_16, A11),
-	PINMUX_IPSR_GPSR(IP5_23_20, DU0_DG4),
-	PINMUX_IPSR_MSEL(IP5_23_20, HRX0_A, SEL_HSCIF0_0),
-	PINMUX_IPSR_GPSR(IP5_23_20, A12),
-	PINMUX_IPSR_GPSR(IP5_27_24, DU0_DG5),
-	PINMUX_IPSR_MSEL(IP5_27_24, HTX0_A, SEL_HSCIF0_0),
-	PINMUX_IPSR_GPSR(IP5_27_24, PWM5_B),
-	PINMUX_IPSR_GPSR(IP5_27_24, A13),
-	PINMUX_IPSR_GPSR(IP5_31_28, DU0_DG6),
-	PINMUX_IPSR_MSEL(IP5_31_28, HRX1_C, SEL_HSCIF1_2),
-	PINMUX_IPSR_GPSR(IP5_31_28, A14),
-
-	/* IPSR6 */
-	PINMUX_IPSR_GPSR(IP6_3_0, DU0_DG7),
-	PINMUX_IPSR_MSEL(IP6_3_0, HTX1_C, SEL_HSCIF1_2),
-	PINMUX_IPSR_GPSR(IP6_3_0, PWM6_B),
-	PINMUX_IPSR_GPSR(IP6_3_0, A15),
-	PINMUX_IPSR_GPSR(IP6_7_4, DU0_DB0),
-	PINMUX_IPSR_MSEL(IP6_7_4, SCL4_D, SEL_I2C04_3),
-	PINMUX_IPSR_MSEL(IP6_7_4, CAN0_RX_C, SEL_CAN0_2),
-	PINMUX_IPSR_GPSR(IP6_7_4, A16),
-	PINMUX_IPSR_GPSR(IP6_11_8, DU0_DB1),
-	PINMUX_IPSR_MSEL(IP6_11_8, SDA4_D, SEL_I2C04_3),
-	PINMUX_IPSR_MSEL(IP6_11_8, CAN0_TX_C, SEL_CAN0_2),
-	PINMUX_IPSR_GPSR(IP6_11_8, A17),
-	PINMUX_IPSR_GPSR(IP6_15_12, DU0_DB2),
-	PINMUX_IPSR_GPSR(IP6_15_12, HCTS0_N),
-	PINMUX_IPSR_GPSR(IP6_15_12, A18),
-	PINMUX_IPSR_GPSR(IP6_19_16, DU0_DB3),
-	PINMUX_IPSR_GPSR(IP6_19_16, HRTS0_N),
-	PINMUX_IPSR_GPSR(IP6_19_16, A19),
-	PINMUX_IPSR_GPSR(IP6_23_20, DU0_DB4),
-	PINMUX_IPSR_MSEL(IP6_23_20, HCTS1_N_C, SEL_HSCIF1_2),
-	PINMUX_IPSR_GPSR(IP6_23_20, A20),
-	PINMUX_IPSR_GPSR(IP6_27_24, DU0_DB5),
-	PINMUX_IPSR_MSEL(IP6_27_24, HRTS1_N_C, SEL_HSCIF1_2),
-	PINMUX_IPSR_GPSR(IP6_27_24, A21),
-	PINMUX_IPSR_GPSR(IP6_31_28, DU0_DB6),
-	PINMUX_IPSR_GPSR(IP6_31_28, A22),
-
-	/* IPSR7 */
-	PINMUX_IPSR_GPSR(IP7_3_0, DU0_DB7),
-	PINMUX_IPSR_GPSR(IP7_3_0, A23),
-	PINMUX_IPSR_GPSR(IP7_7_4, DU0_DOTCLKIN),
-	PINMUX_IPSR_GPSR(IP7_7_4, A24),
-	PINMUX_IPSR_GPSR(IP7_11_8, DU0_DOTCLKOUT0),
-	PINMUX_IPSR_GPSR(IP7_11_8, A25),
-	PINMUX_IPSR_GPSR(IP7_15_12, DU0_DOTCLKOUT1),
-	PINMUX_IPSR_MSEL(IP7_15_12, MSIOF2_RXD_B, SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP7_15_12, CS1_N_A26),
-	PINMUX_IPSR_GPSR(IP7_19_16, DU0_EXHSYNC_DU0_HSYNC),
-	PINMUX_IPSR_MSEL(IP7_19_16, MSIOF2_TXD_B, SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP7_19_16, DREQ0_N),
-	PINMUX_IPSR_GPSR(IP7_23_20, DU0_EXVSYNC_DU0_VSYNC),
-	PINMUX_IPSR_MSEL(IP7_23_20, MSIOF2_SYNC_B, SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP7_23_20, DACK0),
-	PINMUX_IPSR_GPSR(IP7_27_24, DU0_EXODDF_DU0_ODDF_DISP_CDE),
-	PINMUX_IPSR_MSEL(IP7_27_24, MSIOF2_SCK_B, SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP7_27_24, DRACK0),
-	PINMUX_IPSR_GPSR(IP7_31_28, DU0_DISP),
-	PINMUX_IPSR_MSEL(IP7_31_28, CAN1_RX_C, SEL_CAN1_2),
-
-	/* IPSR8 */
-	PINMUX_IPSR_GPSR(IP8_3_0, DU0_CDE),
-	PINMUX_IPSR_MSEL(IP8_3_0, CAN1_TX_C, SEL_CAN1_2),
-	PINMUX_IPSR_GPSR(IP8_7_4, VI1_CLK),
-	PINMUX_IPSR_GPSR(IP8_7_4, AVB_RX_CLK),
-	PINMUX_IPSR_GPSR(IP8_7_4, ETH_REF_CLK),
-	PINMUX_IPSR_GPSR(IP8_11_8, VI1_DATA0),
-	PINMUX_IPSR_GPSR(IP8_11_8, AVB_RX_DV),
-	PINMUX_IPSR_GPSR(IP8_11_8, ETH_CRS_DV),
-	PINMUX_IPSR_GPSR(IP8_15_12, VI1_DATA1),
-	PINMUX_IPSR_GPSR(IP8_15_12, AVB_RXD0),
-	PINMUX_IPSR_GPSR(IP8_15_12, ETH_RXD0),
-	PINMUX_IPSR_GPSR(IP8_19_16, VI1_DATA2),
-	PINMUX_IPSR_GPSR(IP8_19_16, AVB_RXD1),
-	PINMUX_IPSR_GPSR(IP8_19_16, ETH_RXD1),
-	PINMUX_IPSR_GPSR(IP8_23_20, VI1_DATA3),
-	PINMUX_IPSR_GPSR(IP8_23_20, AVB_RXD2),
-	PINMUX_IPSR_GPSR(IP8_23_20, ETH_MDIO),
-	PINMUX_IPSR_GPSR(IP8_27_24, VI1_DATA4),
-	PINMUX_IPSR_GPSR(IP8_27_24, AVB_RXD3),
-	PINMUX_IPSR_GPSR(IP8_27_24, ETH_RX_ER),
-	PINMUX_IPSR_GPSR(IP8_31_28, VI1_DATA5),
-	PINMUX_IPSR_GPSR(IP8_31_28, AVB_RXD4),
-	PINMUX_IPSR_GPSR(IP8_31_28, ETH_LINK),
-
-	/* IPSR9 */
-	PINMUX_IPSR_GPSR(IP9_3_0, VI1_DATA6),
-	PINMUX_IPSR_GPSR(IP9_3_0, AVB_RXD5),
-	PINMUX_IPSR_GPSR(IP9_3_0, ETH_TXD1),
-	PINMUX_IPSR_GPSR(IP9_7_4, VI1_DATA7),
-	PINMUX_IPSR_GPSR(IP9_7_4, AVB_RXD6),
-	PINMUX_IPSR_GPSR(IP9_7_4, ETH_TX_EN),
-	PINMUX_IPSR_GPSR(IP9_11_8, VI1_CLKENB),
-	PINMUX_IPSR_MSEL(IP9_11_8, SCL3_A, SEL_I2C03_0),
-	PINMUX_IPSR_GPSR(IP9_11_8, AVB_RXD7),
-	PINMUX_IPSR_GPSR(IP9_11_8, ETH_MAGIC),
-	PINMUX_IPSR_GPSR(IP9_15_12, VI1_FIELD),
-	PINMUX_IPSR_MSEL(IP9_15_12, SDA3_A, SEL_I2C03_0),
-	PINMUX_IPSR_GPSR(IP9_15_12, AVB_RX_ER),
-	PINMUX_IPSR_GPSR(IP9_15_12, ETH_TXD0),
-	PINMUX_IPSR_GPSR(IP9_19_16, VI1_HSYNC_N),
-	PINMUX_IPSR_MSEL(IP9_19_16, RX0_B, SEL_SCIF0_1),
-	PINMUX_IPSR_MSEL(IP9_19_16, SCL0_C, SEL_I2C00_2),
-	PINMUX_IPSR_GPSR(IP9_19_16, AVB_GTXREFCLK),
-	PINMUX_IPSR_GPSR(IP9_19_16, ETH_MDC),
-	PINMUX_IPSR_GPSR(IP9_23_20, VI1_VSYNC_N),
-	PINMUX_IPSR_MSEL(IP9_23_20, TX0_B, SEL_SCIF0_1),
-	PINMUX_IPSR_MSEL(IP9_23_20, SDA0_C, SEL_I2C00_2),
-	PINMUX_IPSR_GPSR(IP9_23_20, AUDIO_CLKOUT_B),
-	PINMUX_IPSR_GPSR(IP9_23_20, AVB_TX_CLK),
-	PINMUX_IPSR_GPSR(IP9_27_24, VI1_DATA8),
-	PINMUX_IPSR_MSEL(IP9_27_24, SCL2_B, SEL_I2C02_1),
-	PINMUX_IPSR_GPSR(IP9_27_24, AVB_TX_EN),
-	PINMUX_IPSR_GPSR(IP9_31_28, VI1_DATA9),
-	PINMUX_IPSR_MSEL(IP9_31_28, SDA2_B, SEL_I2C02_1),
-	PINMUX_IPSR_GPSR(IP9_31_28, AVB_TXD0),
-
-	/* IPSR10 */
-	PINMUX_IPSR_GPSR(IP10_3_0, VI1_DATA10),
-	PINMUX_IPSR_MSEL(IP10_3_0, CAN0_RX_B, SEL_CAN0_1),
-	PINMUX_IPSR_GPSR(IP10_3_0, AVB_TXD1),
-	PINMUX_IPSR_GPSR(IP10_7_4, VI1_DATA11),
-	PINMUX_IPSR_MSEL(IP10_7_4, CAN0_TX_B, SEL_CAN0_1),
-	PINMUX_IPSR_GPSR(IP10_7_4, AVB_TXD2),
-	PINMUX_IPSR_GPSR(IP10_11_8, AVB_TXD3),
-	PINMUX_IPSR_MSEL(IP10_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
-	PINMUX_IPSR_MSEL(IP10_11_8, SSI_SCK1_D, SEL_SSI1_3),
-	PINMUX_IPSR_MSEL(IP10_11_8, RX5_F, SEL_SCIF5_5),
-	PINMUX_IPSR_MSEL(IP10_11_8, MSIOF0_RXD_B, SEL_MSIOF0_1),
-	PINMUX_IPSR_GPSR(IP10_15_12, AVB_TXD4),
-	PINMUX_IPSR_MSEL(IP10_15_12, AUDIO_CLKB_B, SEL_ADGB_1),
-	PINMUX_IPSR_MSEL(IP10_15_12, SSI_WS1_D, SEL_SSI1_3),
-	PINMUX_IPSR_MSEL(IP10_15_12, TX5_F, SEL_SCIF5_5),
-	PINMUX_IPSR_MSEL(IP10_15_12, MSIOF0_TXD_B, SEL_MSIOF0_1),
-	PINMUX_IPSR_GPSR(IP10_19_16, AVB_TXD5),
-	PINMUX_IPSR_MSEL(IP10_19_16, SCIF_CLK_B, SEL_SCIFCLK_1),
-	PINMUX_IPSR_MSEL(IP10_19_16, AUDIO_CLKC_B, SEL_ADGC_1),
-	PINMUX_IPSR_MSEL(IP10_19_16, SSI_SDATA1_D, SEL_SSI1_3),
-	PINMUX_IPSR_MSEL(IP10_19_16, MSIOF0_SCK_B, SEL_MSIOF0_1),
-	PINMUX_IPSR_MSEL(IP10_23_20, SCL0_A, SEL_I2C00_0),
-	PINMUX_IPSR_MSEL(IP10_23_20, RX0_C, SEL_SCIF0_2),
-	PINMUX_IPSR_GPSR(IP10_23_20, PWM5_A),
-	PINMUX_IPSR_MSEL(IP10_23_20, TCLK1_B, SEL_TMU1_1),
-	PINMUX_IPSR_GPSR(IP10_23_20, AVB_TXD6),
-	PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_D, SEL_CAN1_3),
-	PINMUX_IPSR_MSEL(IP10_23_20, MSIOF0_SYNC_B, SEL_MSIOF0_1),
-	PINMUX_IPSR_MSEL(IP10_27_24, SDA0_A, SEL_I2C00_0),
-	PINMUX_IPSR_MSEL(IP10_27_24, TX0_C, SEL_SCIF0_2),
-	PINMUX_IPSR_GPSR(IP10_27_24, IRQ5),
-	PINMUX_IPSR_MSEL(IP10_27_24, CAN_CLK_A, SEL_CANCLK_0),
-	PINMUX_IPSR_GPSR(IP10_27_24, AVB_GTX_CLK),
-	PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_D, SEL_CAN1_3),
-	PINMUX_IPSR_GPSR(IP10_27_24, DVC_MUTE),
-	PINMUX_IPSR_MSEL(IP10_31_28, SCL1_A, SEL_I2C01_0),
-	PINMUX_IPSR_MSEL(IP10_31_28, RX4_A, SEL_SCIF4_0),
-	PINMUX_IPSR_GPSR(IP10_31_28, PWM5_D),
-	PINMUX_IPSR_GPSR(IP10_31_28, DU1_DR0),
-	PINMUX_IPSR_MSEL(IP10_31_28, SSI_SCK6_B, SEL_SSI6_1),
-	PINMUX_IPSR_GPSR(IP10_31_28, VI0_G0),
-
-	/* IPSR11 */
-	PINMUX_IPSR_MSEL(IP11_3_0, SDA1_A, SEL_I2C01_0),
-	PINMUX_IPSR_MSEL(IP11_3_0, TX4_A, SEL_SCIF4_0),
-	PINMUX_IPSR_GPSR(IP11_3_0, DU1_DR1),
-	PINMUX_IPSR_MSEL(IP11_3_0, SSI_WS6_B, SEL_SSI6_1),
-	PINMUX_IPSR_GPSR(IP11_3_0, VI0_G1),
-	PINMUX_IPSR_MSEL(IP11_7_4, MSIOF0_RXD_A, SEL_MSIOF0_0),
-	PINMUX_IPSR_MSEL(IP11_7_4, RX5_A, SEL_SCIF5_0),
-	PINMUX_IPSR_MSEL(IP11_7_4, SCL2_C, SEL_I2C02_2),
-	PINMUX_IPSR_GPSR(IP11_7_4, DU1_DR2),
-	PINMUX_IPSR_GPSR(IP11_7_4, QSPI1_MOSI_QSPI1_IO0),
-	PINMUX_IPSR_MSEL(IP11_7_4, SSI_SDATA6_B, SEL_SSI6_1),
-	PINMUX_IPSR_GPSR(IP11_7_4, VI0_G2),
-	PINMUX_IPSR_MSEL(IP11_11_8, MSIOF0_TXD_A, SEL_MSIOF0_0),
-	PINMUX_IPSR_MSEL(IP11_11_8, TX5_A, SEL_SCIF5_0),
-	PINMUX_IPSR_MSEL(IP11_11_8, SDA2_C, SEL_I2C02_2),
-	PINMUX_IPSR_GPSR(IP11_11_8, DU1_DR3),
-	PINMUX_IPSR_GPSR(IP11_11_8, QSPI1_MISO_QSPI1_IO1),
-	PINMUX_IPSR_MSEL(IP11_11_8, SSI_WS78_B, SEL_SSI7_1),
-	PINMUX_IPSR_GPSR(IP11_11_8, VI0_G3),
-	PINMUX_IPSR_MSEL(IP11_15_12, MSIOF0_SCK_A, SEL_MSIOF0_0),
-	PINMUX_IPSR_GPSR(IP11_15_12, IRQ0),
-	PINMUX_IPSR_GPSR(IP11_15_12, DU1_DR4),
-	PINMUX_IPSR_GPSR(IP11_15_12, QSPI1_SPCLK),
-	PINMUX_IPSR_MSEL(IP11_15_12, SSI_SCK78_B, SEL_SSI7_1),
-	PINMUX_IPSR_GPSR(IP11_15_12, VI0_G4),
-	PINMUX_IPSR_MSEL(IP11_19_16, MSIOF0_SYNC_A, SEL_MSIOF0_0),
-	PINMUX_IPSR_GPSR(IP11_19_16, PWM1_A),
-	PINMUX_IPSR_GPSR(IP11_19_16, DU1_DR5),
-	PINMUX_IPSR_GPSR(IP11_19_16, QSPI1_IO2),
-	PINMUX_IPSR_MSEL(IP11_19_16, SSI_SDATA7_B, SEL_SSI7_1),
-	PINMUX_IPSR_MSEL(IP11_23_20, MSIOF0_SS1_A, SEL_MSIOF0_0),
-	PINMUX_IPSR_GPSR(IP11_23_20, DU1_DR6),
-	PINMUX_IPSR_GPSR(IP11_23_20, QSPI1_IO3),
-	PINMUX_IPSR_MSEL(IP11_23_20, SSI_SDATA8_B, SEL_SSI8_1),
-	PINMUX_IPSR_MSEL(IP11_27_24, MSIOF0_SS2_A, SEL_MSIOF0_0),
-	PINMUX_IPSR_GPSR(IP11_27_24, DU1_DR7),
-	PINMUX_IPSR_GPSR(IP11_27_24, QSPI1_SSL),
-	PINMUX_IPSR_MSEL(IP11_31_28, HRX1_A, SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP11_31_28, SCL4_A, SEL_I2C04_0),
-	PINMUX_IPSR_GPSR(IP11_31_28, PWM6_A),
-	PINMUX_IPSR_GPSR(IP11_31_28, DU1_DG0),
-	PINMUX_IPSR_MSEL(IP11_31_28, RX0_A, SEL_SCIF0_0),
-
-	/* IPSR12 */
-	PINMUX_IPSR_MSEL(IP12_3_0, HTX1_A, SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_3_0, SDA4_A, SEL_I2C04_0),
-	PINMUX_IPSR_GPSR(IP12_3_0, DU1_DG1),
-	PINMUX_IPSR_MSEL(IP12_3_0, TX0_A, SEL_SCIF0_0),
-	PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_A, SEL_HSCIF1_0),
-	PINMUX_IPSR_GPSR(IP12_7_4, PWM2_A),
-	PINMUX_IPSR_GPSR(IP12_7_4, DU1_DG2),
-	PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_B, SEL_RCN_1),
-	PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_A, SEL_HSCIF1_0),
-	PINMUX_IPSR_GPSR(IP12_11_8, DU1_DG3),
-	PINMUX_IPSR_MSEL(IP12_11_8, SSI_WS1_B, SEL_SSI1_1),
-	PINMUX_IPSR_GPSR(IP12_11_8, IRQ1),
-	PINMUX_IPSR_GPSR(IP12_15_12, SD2_CLK),
-	PINMUX_IPSR_GPSR(IP12_15_12, HSCK1),
-	PINMUX_IPSR_GPSR(IP12_15_12, DU1_DG4),
-	PINMUX_IPSR_MSEL(IP12_15_12, SSI_SCK1_B, SEL_SSI1_1),
-	PINMUX_IPSR_GPSR(IP12_19_16, SD2_CMD),
-	PINMUX_IPSR_MSEL(IP12_19_16, SCIF1_SCK_A, SEL_SCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_19_16, TCLK2_A, SEL_TMU2_0),
-	PINMUX_IPSR_GPSR(IP12_19_16, DU1_DG5),
-	PINMUX_IPSR_MSEL(IP12_19_16, SSI_SCK2_B, SEL_SSI2_1),
-	PINMUX_IPSR_GPSR(IP12_19_16, PWM3_A),
-	PINMUX_IPSR_GPSR(IP12_23_20, SD2_DAT0),
-	PINMUX_IPSR_MSEL(IP12_23_20, RX1_A, SEL_SCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_23_20, SCL1_E, SEL_I2C01_4),
-	PINMUX_IPSR_GPSR(IP12_23_20, DU1_DG6),
-	PINMUX_IPSR_MSEL(IP12_23_20, SSI_SDATA1_B, SEL_SSI1_1),
-	PINMUX_IPSR_GPSR(IP12_27_24, SD2_DAT1),
-	PINMUX_IPSR_MSEL(IP12_27_24, TX1_A, SEL_SCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_27_24, SDA1_E, SEL_I2C01_4),
-	PINMUX_IPSR_GPSR(IP12_27_24, DU1_DG7),
-	PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS2_B, SEL_SSI2_1),
-	PINMUX_IPSR_GPSR(IP12_31_28, SD2_DAT2),
-	PINMUX_IPSR_MSEL(IP12_31_28, RX2_A, SEL_SCIF2_0),
-	PINMUX_IPSR_GPSR(IP12_31_28, DU1_DB0),
-	PINMUX_IPSR_MSEL(IP12_31_28, SSI_SDATA2_B, SEL_SSI2_1),
-
-	/* IPSR13 */
-	PINMUX_IPSR_GPSR(IP13_3_0, SD2_DAT3),
-	PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
-	PINMUX_IPSR_GPSR(IP13_3_0, DU1_DB1),
-	PINMUX_IPSR_MSEL(IP13_3_0, SSI_WS9_B, SEL_SSI9_1),
-	PINMUX_IPSR_GPSR(IP13_7_4, SD2_CD),
-	PINMUX_IPSR_MSEL(IP13_7_4, SCIF2_SCK_A, SEL_SCIF2_CLK_0),
-	PINMUX_IPSR_GPSR(IP13_7_4, DU1_DB2),
-	PINMUX_IPSR_MSEL(IP13_7_4, SSI_SCK9_B, SEL_SSI9_1),
-	PINMUX_IPSR_GPSR(IP13_11_8, SD2_WP),
-	PINMUX_IPSR_GPSR(IP13_11_8, SCIF3_SCK),
-	PINMUX_IPSR_GPSR(IP13_11_8, DU1_DB3),
-	PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA9_B, SEL_SSI9_1),
-	PINMUX_IPSR_MSEL(IP13_15_12, RX3_A, SEL_SCIF3_0),
-	PINMUX_IPSR_MSEL(IP13_15_12, SCL1_C, SEL_I2C01_2),
-	PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_B, SEL_MSIOF1_1),
-	PINMUX_IPSR_GPSR(IP13_15_12, DU1_DB4),
-	PINMUX_IPSR_MSEL(IP13_15_12, AUDIO_CLKA_C, SEL_ADGA_2),
-	PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA4_B, SEL_SSI4_1),
-	PINMUX_IPSR_MSEL(IP13_19_16, TX3_A, SEL_SCIF3_0),
-	PINMUX_IPSR_MSEL(IP13_19_16, SDA1_C, SEL_I2C01_2),
-	PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_B, SEL_MSIOF1_1),
-	PINMUX_IPSR_GPSR(IP13_19_16, DU1_DB5),
-	PINMUX_IPSR_MSEL(IP13_19_16, AUDIO_CLKB_C, SEL_ADGB_2),
-	PINMUX_IPSR_MSEL(IP13_19_16, SSI_WS4_B, SEL_SSI4_1),
-	PINMUX_IPSR_MSEL(IP13_23_20, SCL2_A, SEL_I2C02_0),
-	PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SCK_B, SEL_MSIOF1_1),
-	PINMUX_IPSR_GPSR(IP13_23_20, DU1_DB6),
-	PINMUX_IPSR_MSEL(IP13_23_20, AUDIO_CLKC_C, SEL_ADGC_2),
-	PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK4_B, SEL_SSI4_1),
-	PINMUX_IPSR_MSEL(IP13_27_24, SDA2_A, SEL_I2C02_0),
-	PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SYNC_B, SEL_MSIOF1_1),
-	PINMUX_IPSR_GPSR(IP13_27_24, DU1_DB7),
-	PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT_C),
-	PINMUX_IPSR_MSEL(IP13_31_28, SSI_SCK5_A, SEL_SSI5_0),
-	PINMUX_IPSR_GPSR(IP13_31_28, DU1_DOTCLKOUT1),
-
-	/* IPSR14 */
-	PINMUX_IPSR_MSEL(IP14_3_0, SSI_WS5_A, SEL_SSI5_0),
-	PINMUX_IPSR_MSEL(IP14_3_0, SCL3_C, SEL_I2C03_2),
-	PINMUX_IPSR_GPSR(IP14_3_0, DU1_DOTCLKIN),
-	PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA5_A, SEL_SSI5_0),
-	PINMUX_IPSR_MSEL(IP14_7_4, SDA3_C, SEL_I2C03_2),
-	PINMUX_IPSR_GPSR(IP14_7_4, DU1_DOTCLKOUT0),
-	PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK6_A, SEL_SSI6_0),
-	PINMUX_IPSR_GPSR(IP14_11_8, DU1_EXODDF_DU1_ODDF_DISP_CDE),
-	PINMUX_IPSR_MSEL(IP14_15_12, SSI_WS6_A, SEL_SSI6_0),
-	PINMUX_IPSR_MSEL(IP14_15_12, SCL4_C, SEL_I2C04_2),
-	PINMUX_IPSR_GPSR(IP14_15_12, DU1_EXHSYNC_DU1_HSYNC),
-	PINMUX_IPSR_MSEL(IP14_19_16, SSI_SDATA6_A, SEL_SSI6_0),
-	PINMUX_IPSR_MSEL(IP14_19_16, SDA4_C, SEL_I2C04_2),
-	PINMUX_IPSR_GPSR(IP14_19_16, DU1_EXVSYNC_DU1_VSYNC),
-	PINMUX_IPSR_MSEL(IP14_23_20, SSI_SCK78_A, SEL_SSI7_0),
-	PINMUX_IPSR_MSEL(IP14_23_20, SDA4_E, SEL_I2C04_4),
-	PINMUX_IPSR_GPSR(IP14_23_20, DU1_DISP),
-	PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS78_A, SEL_SSI7_0),
-	PINMUX_IPSR_MSEL(IP14_27_24, SCL4_E, SEL_I2C04_4),
-	PINMUX_IPSR_GPSR(IP14_27_24, DU1_CDE),
-	PINMUX_IPSR_MSEL(IP14_31_28, SSI_SDATA7_A, SEL_SSI7_0),
-	PINMUX_IPSR_GPSR(IP14_31_28, IRQ8),
-	PINMUX_IPSR_MSEL(IP14_31_28, AUDIO_CLKA_D, SEL_ADGA_3),
-	PINMUX_IPSR_MSEL(IP14_31_28, CAN_CLK_D, SEL_CANCLK_3),
-	PINMUX_IPSR_GPSR(IP14_31_28, VI0_G5),
-
-	/* IPSR15 */
-	PINMUX_IPSR_MSEL(IP15_3_0, SSI_SCK0129_A, SEL_SSI0_0),
-	PINMUX_IPSR_MSEL(IP15_3_0, MSIOF1_RXD_A, SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP15_3_0, RX5_D, SEL_SCIF5_3),
-	PINMUX_IPSR_GPSR(IP15_3_0, VI0_G6),
-	PINMUX_IPSR_MSEL(IP15_7_4, SSI_WS0129_A, SEL_SSI0_0),
-	PINMUX_IPSR_MSEL(IP15_7_4, MSIOF1_TXD_A, SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP15_7_4, TX5_D, SEL_SCIF5_3),
-	PINMUX_IPSR_GPSR(IP15_7_4, VI0_G7),
-	PINMUX_IPSR_MSEL(IP15_11_8, SSI_SDATA0_A, SEL_SSI0_0),
-	PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SYNC_A, SEL_MSIOF1_0),
-	PINMUX_IPSR_GPSR(IP15_11_8, PWM0_C),
-	PINMUX_IPSR_GPSR(IP15_11_8, VI0_R0),
-	PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK34),
-	PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_A, SEL_MSIOF1_0),
-	PINMUX_IPSR_GPSR(IP15_15_12, AVB_MDC),
-	PINMUX_IPSR_GPSR(IP15_15_12, DACK1),
-	PINMUX_IPSR_GPSR(IP15_15_12, VI0_R1),
-	PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS34),
-	PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SS1_A, SEL_MSIOF1_0),
-	PINMUX_IPSR_GPSR(IP15_19_16, AVB_MDIO),
-	PINMUX_IPSR_MSEL(IP15_19_16, CAN1_RX_A, SEL_CAN1_0),
-	PINMUX_IPSR_GPSR(IP15_19_16, DREQ1_N),
-	PINMUX_IPSR_GPSR(IP15_19_16, VI0_R2),
-	PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA3),
-	PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SS2_A, SEL_MSIOF1_0),
-	PINMUX_IPSR_GPSR(IP15_23_20, AVB_LINK),
-	PINMUX_IPSR_MSEL(IP15_23_20, CAN1_TX_A, SEL_CAN1_0),
-	PINMUX_IPSR_GPSR(IP15_23_20, DREQ2_N),
-	PINMUX_IPSR_GPSR(IP15_23_20, VI0_R3),
-	PINMUX_IPSR_MSEL(IP15_27_24, SSI_SCK4_A, SEL_SSI4_0),
-	PINMUX_IPSR_GPSR(IP15_27_24, AVB_MAGIC),
-	PINMUX_IPSR_GPSR(IP15_27_24, VI0_R4),
-	PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS4_A, SEL_SSI4_0),
-	PINMUX_IPSR_GPSR(IP15_31_28, AVB_PHY_INT),
-	PINMUX_IPSR_GPSR(IP15_31_28, VI0_R5),
-
-	/* IPSR16 */
-	PINMUX_IPSR_MSEL(IP16_3_0, SSI_SDATA4_A, SEL_SSI4_0),
-	PINMUX_IPSR_GPSR(IP16_3_0, AVB_CRS),
-	PINMUX_IPSR_GPSR(IP16_3_0, VI0_R6),
-	PINMUX_IPSR_MSEL(IP16_7_4, SSI_SCK1_A, SEL_SSI1_0),
-	PINMUX_IPSR_MSEL(IP16_7_4, SCIF1_SCK_B, SEL_SCIF1_1),
-	PINMUX_IPSR_GPSR(IP16_7_4, PWM1_D),
-	PINMUX_IPSR_GPSR(IP16_7_4, IRQ9),
-	PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_RCN_0),
-	PINMUX_IPSR_GPSR(IP16_7_4, DACK2),
-	PINMUX_IPSR_GPSR(IP16_7_4, VI0_CLK),
-	PINMUX_IPSR_GPSR(IP16_7_4, AVB_COL),
-	PINMUX_IPSR_MSEL(IP16_11_8, SSI_SDATA8_A, SEL_SSI8_0),
-	PINMUX_IPSR_MSEL(IP16_11_8, RX1_B, SEL_SCIF1_1),
-	PINMUX_IPSR_MSEL(IP16_11_8, CAN0_RX_D, SEL_CAN0_3),
-	PINMUX_IPSR_MSEL(IP16_11_8, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
-	PINMUX_IPSR_GPSR(IP16_11_8, VI0_R7),
-	PINMUX_IPSR_MSEL(IP16_15_12, SSI_WS1_A, SEL_SSI1_0),
-	PINMUX_IPSR_MSEL(IP16_15_12, TX1_B, SEL_SCIF1_1),
-	PINMUX_IPSR_MSEL(IP16_15_12, CAN0_TX_D, SEL_CAN0_3),
-	PINMUX_IPSR_MSEL(IP16_15_12, AVB_AVTP_MATCH_B, SEL_AVB_1),
-	PINMUX_IPSR_GPSR(IP16_15_12, VI0_DATA0_VI0_B0),
-	PINMUX_IPSR_MSEL(IP16_19_16, SSI_SDATA1_A, SEL_SSI1_0),
-	PINMUX_IPSR_MSEL(IP16_19_16, HRX1_B, SEL_HSCIF1_1),
-	PINMUX_IPSR_GPSR(IP16_19_16, VI0_DATA1_VI0_B1),
-	PINMUX_IPSR_MSEL(IP16_23_20, SSI_SCK2_A, SEL_SSI2_0),
-	PINMUX_IPSR_MSEL(IP16_23_20, HTX1_B, SEL_HSCIF1_1),
-	PINMUX_IPSR_GPSR(IP16_23_20, AVB_TXD7),
-	PINMUX_IPSR_GPSR(IP16_23_20, VI0_DATA2_VI0_B2),
-	PINMUX_IPSR_MSEL(IP16_27_24, SSI_WS2_A, SEL_SSI2_0),
-	PINMUX_IPSR_MSEL(IP16_27_24, HCTS1_N_B, SEL_HSCIF1_1),
-	PINMUX_IPSR_GPSR(IP16_27_24, AVB_TX_ER),
-	PINMUX_IPSR_GPSR(IP16_27_24, VI0_DATA3_VI0_B3),
-	PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA2_A, SEL_SSI2_0),
-	PINMUX_IPSR_MSEL(IP16_31_28, HRTS1_N_B, SEL_HSCIF1_1),
-	PINMUX_IPSR_GPSR(IP16_31_28, VI0_DATA4_VI0_B4),
-
-	/* IPSR17 */
-	PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_A, SEL_SSI9_0),
-	PINMUX_IPSR_MSEL(IP17_3_0, RX2_B, SEL_SCIF2_1),
-	PINMUX_IPSR_MSEL(IP17_3_0, SCL3_E, SEL_I2C03_4),
-	PINMUX_IPSR_GPSR(IP17_3_0, EX_WAIT1),
-	PINMUX_IPSR_GPSR(IP17_3_0, VI0_DATA5_VI0_B5),
-	PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_A, SEL_SSI9_0),
-	PINMUX_IPSR_MSEL(IP17_7_4, TX2_B, SEL_SCIF2_1),
-	PINMUX_IPSR_MSEL(IP17_7_4, SDA3_E, SEL_I2C03_4),
-	PINMUX_IPSR_GPSR(IP17_7_4, VI0_DATA6_VI0_B6),
-	PINMUX_IPSR_MSEL(IP17_11_8, SSI_SDATA9_A, SEL_SSI9_0),
-	PINMUX_IPSR_GPSR(IP17_11_8, SCIF2_SCK_B),
-	PINMUX_IPSR_GPSR(IP17_11_8, PWM2_D),
-	PINMUX_IPSR_GPSR(IP17_11_8, VI0_DATA7_VI0_B7),
-	PINMUX_IPSR_MSEL(IP17_15_12, AUDIO_CLKA_A, SEL_ADGA_0),
-	PINMUX_IPSR_MSEL(IP17_15_12, SCL0_B, SEL_I2C00_1),
-	PINMUX_IPSR_GPSR(IP17_15_12, VI0_CLKENB),
-	PINMUX_IPSR_MSEL(IP17_19_16, AUDIO_CLKB_A, SEL_ADGB_0),
-	PINMUX_IPSR_MSEL(IP17_19_16, SDA0_B, SEL_I2C00_1),
-	PINMUX_IPSR_GPSR(IP17_19_16, VI0_FIELD),
-	PINMUX_IPSR_MSEL(IP17_23_20, AUDIO_CLKC_A, SEL_ADGC_0),
-	PINMUX_IPSR_MSEL(IP17_23_20, SCL4_B, SEL_I2C04_1),
-	PINMUX_IPSR_GPSR(IP17_23_20, VI0_HSYNC_N),
-	PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_A),
-	PINMUX_IPSR_MSEL(IP17_27_24, SDA4_B, SEL_I2C04_1),
-	PINMUX_IPSR_GPSR(IP17_27_24, VI0_VSYNC_N),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	PINMUX_GPIO_GP_ALL(),
-};
-
-/* - AVB -------------------------------------------------------------------- */
-static const unsigned int avb_col_pins[] = {
-	RCAR_GP_PIN(5, 18),
-};
-static const unsigned int avb_col_mux[] = {
-	AVB_COL_MARK,
-};
-static const unsigned int avb_crs_pins[] = {
-	RCAR_GP_PIN(5, 17),
-};
-static const unsigned int avb_crs_mux[] = {
-	AVB_CRS_MARK,
-};
-static const unsigned int avb_link_pins[] = {
-	RCAR_GP_PIN(5, 14),
-};
-static const unsigned int avb_link_mux[] = {
-	AVB_LINK_MARK,
-};
-static const unsigned int avb_magic_pins[] = {
-	RCAR_GP_PIN(5, 15),
-};
-static const unsigned int avb_magic_mux[] = {
-	AVB_MAGIC_MARK,
-};
-static const unsigned int avb_phy_int_pins[] = {
-	RCAR_GP_PIN(5, 16),
-};
-static const unsigned int avb_phy_int_mux[] = {
-	AVB_PHY_INT_MARK,
-};
-static const unsigned int avb_mdio_pins[] = {
-	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
-};
-static const unsigned int avb_mdio_mux[] = {
-	AVB_MDC_MARK, AVB_MDIO_MARK,
-};
-static const unsigned int avb_mii_tx_rx_pins[] = {
-	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
-	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 13),
-
-	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
-	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 1),
-	RCAR_GP_PIN(3, 10),
-};
-static const unsigned int avb_mii_tx_rx_mux[] = {
-	AVB_TX_CLK_MARK, AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
-	AVB_TXD3_MARK, AVB_TX_EN_MARK,
-
-	AVB_RX_CLK_MARK, AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
-	AVB_RXD3_MARK, AVB_RX_DV_MARK, AVB_RX_ER_MARK,
-};
-static const unsigned int avb_mii_tx_er_pins[] = {
-	RCAR_GP_PIN(5, 23),
-};
-static const unsigned int avb_mii_tx_er_mux[] = {
-	AVB_TX_ER_MARK,
-};
-static const unsigned int avb_gmii_tx_rx_pins[] = {
-	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
-	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
-	RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
-	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(3, 13),
-	RCAR_GP_PIN(5, 23),
-
-	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
-	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
-	RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 10),
-};
-static const unsigned int avb_gmii_tx_rx_mux[] = {
-	AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, AVB_TX_CLK_MARK, AVB_TXD0_MARK,
-	AVB_TXD1_MARK, AVB_TXD2_MARK, AVB_TXD3_MARK, AVB_TXD4_MARK,
-	AVB_TXD5_MARK, AVB_TXD6_MARK, AVB_TXD7_MARK, AVB_TX_EN_MARK,
-	AVB_TX_ER_MARK,
-
-	AVB_RX_CLK_MARK, AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
-	AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, AVB_RXD6_MARK,
-	AVB_RXD7_MARK, AVB_RX_DV_MARK, AVB_RX_ER_MARK,
-};
-static const unsigned int avb_avtp_match_a_pins[] = {
-	RCAR_GP_PIN(1, 15),
-};
-static const unsigned int avb_avtp_match_a_mux[] = {
-	AVB_AVTP_MATCH_A_MARK,
-};
-static const unsigned int avb_avtp_capture_a_pins[] = {
-	RCAR_GP_PIN(1, 14),
-};
-static const unsigned int avb_avtp_capture_a_mux[] = {
-	AVB_AVTP_CAPTURE_A_MARK,
-};
-static const unsigned int avb_avtp_match_b_pins[] = {
-	RCAR_GP_PIN(5, 20),
-};
-static const unsigned int avb_avtp_match_b_mux[] = {
-	AVB_AVTP_MATCH_B_MARK,
-};
-static const unsigned int avb_avtp_capture_b_pins[] = {
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int avb_avtp_capture_b_mux[] = {
-	AVB_AVTP_CAPTURE_B_MARK,
-};
-/* - DU --------------------------------------------------------------------- */
-static const unsigned int du0_rgb666_pins[] = {
-	/* R[7:2], G[7:2], B[7:2] */
-	RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 5),
-	RCAR_GP_PIN(2, 4),  RCAR_GP_PIN(2, 3),  RCAR_GP_PIN(2, 2),
-	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
-	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
-	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
-	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
-};
-static const unsigned int du0_rgb666_mux[] = {
-	DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
-	DU0_DR3_MARK, DU0_DR2_MARK,
-	DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
-	DU0_DG3_MARK, DU0_DG2_MARK,
-	DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
-	DU0_DB3_MARK, DU0_DB2_MARK,
-};
-static const unsigned int du0_rgb888_pins[] = {
-	/* R[7:0], G[7:0], B[7:0] */
-	RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 5),
-	RCAR_GP_PIN(2, 4),  RCAR_GP_PIN(2, 3),  RCAR_GP_PIN(2, 2),
-	RCAR_GP_PIN(2, 1),  RCAR_GP_PIN(2, 0),
-	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
-	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
-	RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 8),
-	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
-	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
-	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
-};
-static const unsigned int du0_rgb888_mux[] = {
-	DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
-	DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
-	DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
-	DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
-	DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
-	DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
-};
-static const unsigned int du0_clk0_out_pins[] = {
-	/* DOTCLKOUT0 */
-	RCAR_GP_PIN(2, 25),
-};
-static const unsigned int du0_clk0_out_mux[] = {
-	DU0_DOTCLKOUT0_MARK
-};
-static const unsigned int du0_clk1_out_pins[] = {
-	/* DOTCLKOUT1 */
-	RCAR_GP_PIN(2, 26),
-};
-static const unsigned int du0_clk1_out_mux[] = {
-	DU0_DOTCLKOUT1_MARK
-};
-static const unsigned int du0_clk_in_pins[] = {
-	/* CLKIN */
-	RCAR_GP_PIN(2, 24),
-};
-static const unsigned int du0_clk_in_mux[] = {
-	DU0_DOTCLKIN_MARK
-};
-static const unsigned int du0_sync_pins[] = {
-	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
-	RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27),
-};
-static const unsigned int du0_sync_mux[] = {
-	DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK
-};
-static const unsigned int du0_oddf_pins[] = {
-	/* EXODDF/ODDF/DISP/CDE */
-	RCAR_GP_PIN(2, 29),
-};
-static const unsigned int du0_oddf_mux[] = {
-	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
-};
-static const unsigned int du0_cde_pins[] = {
-	/* CDE */
-	RCAR_GP_PIN(2, 31),
-};
-static const unsigned int du0_cde_mux[] = {
-	DU0_CDE_MARK,
-};
-static const unsigned int du0_disp_pins[] = {
-	/* DISP */
-	RCAR_GP_PIN(2, 30),
-};
-static const unsigned int du0_disp_mux[] = {
-	DU0_DISP_MARK
-};
-static const unsigned int du1_rgb666_pins[] = {
-	/* R[7:2], G[7:2], B[7:2] */
-	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 8),  RCAR_GP_PIN(4, 7),
-	RCAR_GP_PIN(4, 6),  RCAR_GP_PIN(4, 5),  RCAR_GP_PIN(4, 4),
-	RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
-	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
-	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
-	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
-};
-static const unsigned int du1_rgb666_mux[] = {
-	DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
-	DU1_DR3_MARK, DU1_DR2_MARK,
-	DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
-	DU1_DG3_MARK, DU1_DG2_MARK,
-	DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
-	DU1_DB3_MARK, DU1_DB2_MARK,
-};
-static const unsigned int du1_rgb888_pins[] = {
-	/* R[7:0], G[7:0], B[7:0] */
-	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 8),  RCAR_GP_PIN(4, 7),
-	RCAR_GP_PIN(4, 6),  RCAR_GP_PIN(4, 5),  RCAR_GP_PIN(4, 4),
-	RCAR_GP_PIN(4, 3),  RCAR_GP_PIN(4, 2),
-	RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
-	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
-	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
-	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
-	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
-	RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
-};
-static const unsigned int du1_rgb888_mux[] = {
-	DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
-	DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
-	DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
-	DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
-	DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
-	DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
-};
-static const unsigned int du1_clk0_out_pins[] = {
-	/* DOTCLKOUT0 */
-	RCAR_GP_PIN(5, 2),
-};
-static const unsigned int du1_clk0_out_mux[] = {
-	DU1_DOTCLKOUT0_MARK
-};
-static const unsigned int du1_clk1_out_pins[] = {
-	/* DOTCLKOUT1 */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int du1_clk1_out_mux[] = {
-	DU1_DOTCLKOUT1_MARK
-};
-static const unsigned int du1_clk_in_pins[] = {
-	/* DOTCLKIN */
-	RCAR_GP_PIN(5, 1),
-};
-static const unsigned int du1_clk_in_mux[] = {
-	DU1_DOTCLKIN_MARK
-};
-static const unsigned int du1_sync_pins[] = {
-	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
-	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 4),
-};
-static const unsigned int du1_sync_mux[] = {
-	DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
-};
-static const unsigned int du1_oddf_pins[] = {
-	/* EXODDF/ODDF/DISP/CDE */
-	RCAR_GP_PIN(5, 3),
-};
-static const unsigned int du1_oddf_mux[] = {
-	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
-};
-static const unsigned int du1_cde_pins[] = {
-	/* CDE */
-	RCAR_GP_PIN(5, 7),
-};
-static const unsigned int du1_cde_mux[] = {
-	DU1_CDE_MARK
-};
-static const unsigned int du1_disp_pins[] = {
-	/* DISP */
-	RCAR_GP_PIN(5, 6),
-};
-static const unsigned int du1_disp_mux[] = {
-	DU1_DISP_MARK
-};
-/* - I2C0 ------------------------------------------------------------------- */
-static const unsigned int i2c0_a_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
-};
-static const unsigned int i2c0_a_mux[] = {
-	SCL0_A_MARK, SDA0_A_MARK,
-};
-static const unsigned int i2c0_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
-};
-static const unsigned int i2c0_b_mux[] = {
-	SCL0_B_MARK, SDA0_B_MARK,
-};
-static const unsigned int i2c0_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
-};
-static const unsigned int i2c0_c_mux[] = {
-	SCL0_C_MARK, SDA0_C_MARK,
-};
-static const unsigned int i2c0_d_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-};
-static const unsigned int i2c0_d_mux[] = {
-	SCL0_D_MARK, SDA0_D_MARK,
-};
-static const unsigned int i2c0_e_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-};
-static const unsigned int i2c0_e_mux[] = {
-	SCL0_E_MARK, SDA0_E_MARK,
-};
-/* - I2C1 ------------------------------------------------------------------- */
-static const unsigned int i2c1_a_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
-};
-static const unsigned int i2c1_a_mux[] = {
-	SCL1_A_MARK, SDA1_A_MARK,
-};
-static const unsigned int i2c1_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
-};
-static const unsigned int i2c1_b_mux[] = {
-	SCL1_B_MARK, SDA1_B_MARK,
-};
-static const unsigned int i2c1_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
-};
-static const unsigned int i2c1_c_mux[] = {
-	SCL1_C_MARK, SDA1_C_MARK,
-};
-static const unsigned int i2c1_d_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
-};
-static const unsigned int i2c1_d_mux[] = {
-	SCL1_D_MARK, SDA1_D_MARK,
-};
-static const unsigned int i2c1_e_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
-};
-static const unsigned int i2c1_e_mux[] = {
-	SCL1_E_MARK, SDA1_E_MARK,
-};
-/* - I2C2 ------------------------------------------------------------------- */
-static const unsigned int i2c2_a_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
-};
-static const unsigned int i2c2_a_mux[] = {
-	SCL2_A_MARK, SDA2_A_MARK,
-};
-static const unsigned int i2c2_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
-};
-static const unsigned int i2c2_b_mux[] = {
-	SCL2_B_MARK, SDA2_B_MARK,
-};
-static const unsigned int i2c2_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-};
-static const unsigned int i2c2_c_mux[] = {
-	SCL2_C_MARK, SDA2_C_MARK,
-};
-static const unsigned int i2c2_d_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-};
-static const unsigned int i2c2_d_mux[] = {
-	SCL2_D_MARK, SDA2_D_MARK,
-};
-/* - I2C3 ------------------------------------------------------------------- */
-static const unsigned int i2c3_a_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
-};
-static const unsigned int i2c3_a_mux[] = {
-	SCL3_A_MARK, SDA3_A_MARK,
-};
-static const unsigned int i2c3_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-};
-static const unsigned int i2c3_b_mux[] = {
-	SCL3_B_MARK, SDA3_B_MARK,
-};
-static const unsigned int i2c3_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-};
-static const unsigned int i2c3_c_mux[] = {
-	SCL3_C_MARK, SDA3_C_MARK,
-};
-static const unsigned int i2c3_d_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
-};
-static const unsigned int i2c3_d_mux[] = {
-	SCL3_D_MARK, SDA3_D_MARK,
-};
-static const unsigned int i2c3_e_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26),
-};
-static const unsigned int i2c3_e_mux[] = {
-	SCL3_E_MARK, SDA3_E_MARK,
-};
-/* - I2C4 ------------------------------------------------------------------- */
-static const unsigned int i2c4_a_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
-};
-static const unsigned int i2c4_a_mux[] = {
-	SCL4_A_MARK, SDA4_A_MARK,
-};
-static const unsigned int i2c4_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 31),
-};
-static const unsigned int i2c4_b_mux[] = {
-	SCL4_B_MARK, SDA4_B_MARK,
-};
-static const unsigned int i2c4_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
-};
-static const unsigned int i2c4_c_mux[] = {
-	SCL4_C_MARK, SDA4_C_MARK,
-};
-static const unsigned int i2c4_d_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
-};
-static const unsigned int i2c4_d_mux[] = {
-	SCL4_D_MARK, SDA4_D_MARK,
-};
-static const unsigned int i2c4_e_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 6),
-};
-static const unsigned int i2c4_e_mux[] = {
-	SCL4_E_MARK, SDA4_E_MARK,
-};
-/* - MMC -------------------------------------------------------------------- */
-static const unsigned int mmc_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(0, 15),
-};
-static const unsigned int mmc_data1_mux[] = {
-	MMC0_D0_SDHI1_D0_MARK,
-};
-static const unsigned int mmc_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
-	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
-};
-static const unsigned int mmc_data4_mux[] = {
-	MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
-	MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
-};
-static const unsigned int mmc_data8_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
-	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
-	RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
-	RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
-};
-static const unsigned int mmc_data8_mux[] = {
-	MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
-	MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
-	MMC0_D4_MARK, MMC0_D5_MARK,
-	MMC0_D6_MARK, MMC0_D7_MARK,
-};
-static const unsigned int mmc_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
-};
-static const unsigned int mmc_ctrl_mux[] = {
-	MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
-};
-/* - QSPI ------------------------------------------------------------------- */
-static const unsigned int qspi0_ctrl_pins[] = {
-	/* SPCLK, SSL */
-	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 21),
-};
-static const unsigned int qspi0_ctrl_mux[] = {
-	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
-};
-static const unsigned int qspi0_data2_pins[] = {
-	/* MOSI_IO0, MISO_IO1 */
-	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
-};
-static const unsigned int qspi0_data2_mux[] = {
-	QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
-};
-static const unsigned int qspi0_data4_pins[] = {
-	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
-	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
-	RCAR_GP_PIN(1, 20),
-};
-static const unsigned int qspi0_data4_mux[] = {
-	QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
-	QSPI0_IO2_MARK, QSPI0_IO3_MARK,
-};
-static const unsigned int qspi1_ctrl_pins[] = {
-	/* SPCLK, SSL */
-	RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 9),
-};
-static const unsigned int qspi1_ctrl_mux[] = {
-	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
-};
-static const unsigned int qspi1_data2_pins[] = {
-	/* MOSI_IO0, MISO_IO1 */
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-};
-static const unsigned int qspi1_data2_mux[] = {
-	QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
-};
-static const unsigned int qspi1_data4_pins[] = {
-	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
-	RCAR_GP_PIN(4, 8),
-};
-static const unsigned int qspi1_data4_mux[] = {
-	QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
-	QSPI1_IO2_MARK, QSPI1_IO3_MARK,
-};
-/* - SCIF0 ------------------------------------------------------------------ */
-static const unsigned int scif0_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
-};
-static const unsigned int scif0_data_a_mux[] = {
-	RX0_A_MARK, TX0_A_MARK,
-};
-static const unsigned int scif0_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
-};
-static const unsigned int scif0_data_b_mux[] = {
-	RX0_B_MARK, TX0_B_MARK,
-};
-static const unsigned int scif0_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
-};
-static const unsigned int scif0_data_c_mux[] = {
-	RX0_C_MARK, TX0_C_MARK,
-};
-static const unsigned int scif0_data_d_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-};
-static const unsigned int scif0_data_d_mux[] = {
-	RX0_D_MARK, TX0_D_MARK,
-};
-/* - SCIF1 ------------------------------------------------------------------ */
-static const unsigned int scif1_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
-};
-static const unsigned int scif1_data_a_mux[] = {
-	RX1_A_MARK, TX1_A_MARK,
-};
-static const unsigned int scif1_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 15),
-};
-static const unsigned int scif1_clk_a_mux[] = {
-	SCIF1_SCK_A_MARK,
-};
-static const unsigned int scif1_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
-};
-static const unsigned int scif1_data_b_mux[] = {
-	RX1_B_MARK, TX1_B_MARK,
-};
-static const unsigned int scif1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 18),
-};
-static const unsigned int scif1_clk_b_mux[] = {
-	SCIF1_SCK_B_MARK,
-};
-static const unsigned int scif1_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
-};
-static const unsigned int scif1_data_c_mux[] = {
-	RX1_C_MARK, TX1_C_MARK,
-};
-static const unsigned int scif1_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 7),
-};
-static const unsigned int scif1_clk_c_mux[] = {
-	SCIF1_SCK_C_MARK,
-};
-static const unsigned int scif1_data_d_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-};
-static const unsigned int scif1_data_d_mux[] = {
-	RX1_D_MARK, TX1_D_MARK,
-};
-/* - SCIF2 ------------------------------------------------------------------ */
-static const unsigned int scif2_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
-};
-static const unsigned int scif2_data_a_mux[] = {
-	RX2_A_MARK, TX2_A_MARK,
-};
-static const unsigned int scif2_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 20),
-};
-static const unsigned int scif2_clk_a_mux[] = {
-	SCIF2_SCK_A_MARK,
-};
-static const unsigned int scif2_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26),
-};
-static const unsigned int scif2_data_b_mux[] = {
-	RX2_B_MARK, TX2_B_MARK,
-};
-static const unsigned int scif2_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 27),
-};
-static const unsigned int scif2_clk_b_mux[] = {
-	SCIF2_SCK_B_MARK,
-};
-static const unsigned int scif2_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-};
-static const unsigned int scif2_data_c_mux[] = {
-	RX2_C_MARK, TX2_C_MARK,
-};
-/* - SCIF3 ------------------------------------------------------------------ */
-static const unsigned int scif3_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
-};
-static const unsigned int scif3_data_a_mux[] = {
-	RX3_A_MARK, TX3_A_MARK,
-};
-static const unsigned int scif3_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 21),
-};
-static const unsigned int scif3_clk_mux[] = {
-	SCIF3_SCK_MARK,
-};
-static const unsigned int scif3_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
-};
-static const unsigned int scif3_data_b_mux[] = {
-	RX3_B_MARK, TX3_B_MARK,
-};
-static const unsigned int scif3_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
-};
-static const unsigned int scif3_data_c_mux[] = {
-	RX3_C_MARK, TX3_C_MARK,
-};
-/* - SCIF4 ------------------------------------------------------------------ */
-static const unsigned int scif4_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
-};
-static const unsigned int scif4_data_a_mux[] = {
-	RX4_A_MARK, TX4_A_MARK,
-};
-static const unsigned int scif4_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-};
-static const unsigned int scif4_data_b_mux[] = {
-	RX4_B_MARK, TX4_B_MARK,
-};
-static const unsigned int scif4_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
-};
-static const unsigned int scif4_data_c_mux[] = {
-	RX4_C_MARK, TX4_C_MARK,
-};
-static const unsigned int scif4_data_d_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
-};
-static const unsigned int scif4_data_d_mux[] = {
-	RX4_D_MARK, TX4_D_MARK,
-};
-static const unsigned int scif4_data_e_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
-};
-static const unsigned int scif4_data_e_mux[] = {
-	RX4_E_MARK, TX4_E_MARK,
-};
-/* - SCIF5 ------------------------------------------------------------------ */
-static const unsigned int scif5_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-};
-static const unsigned int scif5_data_a_mux[] = {
-	RX5_A_MARK, TX5_A_MARK,
-};
-static const unsigned int scif5_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-};
-static const unsigned int scif5_data_b_mux[] = {
-	RX5_B_MARK, TX5_B_MARK,
-};
-static const unsigned int scif5_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-};
-static const unsigned int scif5_data_c_mux[] = {
-	RX5_C_MARK, TX5_C_MARK,
-};
-static const unsigned int scif5_data_d_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
-};
-static const unsigned int scif5_data_d_mux[] = {
-	RX5_D_MARK, TX5_D_MARK,
-};
-static const unsigned int scif5_data_e_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
-};
-static const unsigned int scif5_data_e_mux[] = {
-	RX5_E_MARK, TX5_E_MARK,
-};
-static const unsigned int scif5_data_f_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
-};
-static const unsigned int scif5_data_f_mux[] = {
-	RX5_F_MARK, TX5_F_MARK,
-};
-/* - SCIF Clock ------------------------------------------------------------- */
-static const unsigned int scif_clk_a_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(1, 22),
-};
-static const unsigned int scif_clk_a_mux[] = {
-	SCIF_CLK_A_MARK,
-};
-static const unsigned int scif_clk_b_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(3, 29),
-};
-static const unsigned int scif_clk_b_mux[] = {
-	SCIF_CLK_B_MARK,
-};
-/* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(0, 7),
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SD0_DAT0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
-	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
-};
-static const unsigned int sdhi0_data4_mux[] = {
-	SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
-};
-static const unsigned int sdhi0_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
-};
-static const unsigned int sdhi0_ctrl_mux[] = {
-	SD0_CLK_MARK, SD0_CMD_MARK,
-};
-static const unsigned int sdhi0_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(0, 11),
-};
-static const unsigned int sdhi0_cd_mux[] = {
-	SD0_CD_MARK,
-};
-static const unsigned int sdhi0_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(0, 12),
-};
-static const unsigned int sdhi0_wp_mux[] = {
-	SD0_WP_MARK,
-};
-/* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(0, 15),
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	MMC0_D0_SDHI1_D0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
-	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
-};
-static const unsigned int sdhi1_data4_mux[] = {
-	MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
-	MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
-};
-static const unsigned int sdhi1_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
-};
-static const unsigned int sdhi1_ctrl_mux[] = {
-	MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
-};
-static const unsigned int sdhi1_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(0, 19),
-};
-static const unsigned int sdhi1_cd_mux[] = {
-	SD1_CD_MARK,
-};
-static const unsigned int sdhi1_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(0, 20),
-};
-static const unsigned int sdhi1_wp_mux[] = {
-	SD1_WP_MARK,
-};
-/* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(4, 16),
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SD2_DAT0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
-	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
-};
-static const unsigned int sdhi2_data4_mux[] = {
-	SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
-};
-static const unsigned int sdhi2_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
-};
-static const unsigned int sdhi2_ctrl_mux[] = {
-	SD2_CLK_MARK, SD2_CMD_MARK,
-};
-static const unsigned int sdhi2_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(4, 20),
-};
-static const unsigned int sdhi2_cd_mux[] = {
-	SD2_CD_MARK,
-};
-static const unsigned int sdhi2_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(4, 21),
-};
-static const unsigned int sdhi2_wp_mux[] = {
-	SD2_WP_MARK,
-};
-/* - USB0 ------------------------------------------------------------------- */
-static const unsigned int usb0_pins[] = {
-	RCAR_GP_PIN(0, 0), /* PWEN */
-	RCAR_GP_PIN(0, 1), /* OVC */
-};
-static const unsigned int usb0_mux[] = {
-	USB0_PWEN_MARK,
-	USB0_OVC_MARK,
-};
-/* - USB1 ------------------------------------------------------------------- */
-static const unsigned int usb1_pins[] = {
-	RCAR_GP_PIN(0, 2), /* PWEN */
-	RCAR_GP_PIN(0, 3), /* OVC */
-};
-static const unsigned int usb1_mux[] = {
-	USB1_PWEN_MARK,
-	USB1_OVC_MARK,
-};
-/* - VIN0 ------------------------------------------------------------------- */
-static const union vin_data vin0_data_pins = {
-	.data24 = {
-		/* B */
-		RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
-		RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
-		RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
-		RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
-		/* G */
-		RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
-		RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-		RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
-		RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
-		/* R */
-		RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
-		RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
-		RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
-		RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
-	},
-};
-static const union vin_data vin0_data_mux = {
-	.data24 = {
-		/* B */
-		VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
-		VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
-		VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
-		VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
-		/* G */
-		VI0_G0_MARK, VI0_G1_MARK,
-		VI0_G2_MARK, VI0_G3_MARK,
-		VI0_G4_MARK, VI0_G5_MARK,
-		VI0_G6_MARK, VI0_G7_MARK,
-		/* R */
-		VI0_R0_MARK, VI0_R1_MARK,
-		VI0_R2_MARK, VI0_R3_MARK,
-		VI0_R4_MARK, VI0_R5_MARK,
-		VI0_R6_MARK, VI0_R7_MARK,
-	},
-};
-static const unsigned int vin0_data18_pins[] = {
-	/* B */
-	RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
-	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
-	RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
-	/* G */
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-	RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
-	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
-	/* R */
-	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
-	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
-	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
-};
-static const unsigned int vin0_data18_mux[] = {
-	/* B */
-	VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
-	VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
-	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
-	/* G */
-	VI0_G2_MARK, VI0_G3_MARK,
-	VI0_G4_MARK, VI0_G5_MARK,
-	VI0_G6_MARK, VI0_G7_MARK,
-	/* R */
-	VI0_R2_MARK, VI0_R3_MARK,
-	VI0_R4_MARK, VI0_R5_MARK,
-	VI0_R6_MARK, VI0_R7_MARK,
-};
-static const unsigned int vin0_sync_pins[] = {
-	RCAR_GP_PIN(5, 30), /* HSYNC */
-	RCAR_GP_PIN(5, 31), /* VSYNC */
-};
-static const unsigned int vin0_sync_mux[] = {
-	VI0_HSYNC_N_MARK,
-	VI0_VSYNC_N_MARK,
-};
-static const unsigned int vin0_field_pins[] = {
-	RCAR_GP_PIN(5, 29),
-};
-static const unsigned int vin0_field_mux[] = {
-	VI0_FIELD_MARK,
-};
-static const unsigned int vin0_clkenb_pins[] = {
-	RCAR_GP_PIN(5, 28),
-};
-static const unsigned int vin0_clkenb_mux[] = {
-	VI0_CLKENB_MARK,
-};
-static const unsigned int vin0_clk_pins[] = {
-	RCAR_GP_PIN(5, 18),
-};
-static const unsigned int vin0_clk_mux[] = {
-	VI0_CLK_MARK,
-};
-/* - VIN1 ------------------------------------------------------------------- */
-static const union vin_data vin1_data_pins = {
-	.data12 = {
-		RCAR_GP_PIN(3,  1), RCAR_GP_PIN(3, 2),
-		RCAR_GP_PIN(3,  3), RCAR_GP_PIN(3, 4),
-		RCAR_GP_PIN(3,  5), RCAR_GP_PIN(3, 6),
-		RCAR_GP_PIN(3,  7), RCAR_GP_PIN(3, 8),
-		RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
-		RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
-	},
-};
-static const union vin_data vin1_data_mux = {
-	.data12 = {
-		VI1_DATA0_MARK, VI1_DATA1_MARK,
-		VI1_DATA2_MARK, VI1_DATA3_MARK,
-		VI1_DATA4_MARK, VI1_DATA5_MARK,
-		VI1_DATA6_MARK, VI1_DATA7_MARK,
-		VI1_DATA8_MARK, VI1_DATA9_MARK,
-		VI1_DATA10_MARK, VI1_DATA11_MARK,
-	},
-};
-static const unsigned int vin1_sync_pins[] = {
-	RCAR_GP_PIN(3, 11), /* HSYNC */
-	RCAR_GP_PIN(3, 12), /* VSYNC */
-};
-static const unsigned int vin1_sync_mux[] = {
-	VI1_HSYNC_N_MARK,
-	VI1_VSYNC_N_MARK,
-};
-static const unsigned int vin1_field_pins[] = {
-	RCAR_GP_PIN(3, 10),
-};
-static const unsigned int vin1_field_mux[] = {
-	VI1_FIELD_MARK,
-};
-static const unsigned int vin1_clkenb_pins[] = {
-	RCAR_GP_PIN(3, 9),
-};
-static const unsigned int vin1_clkenb_mux[] = {
-	VI1_CLKENB_MARK,
-};
-static const unsigned int vin1_clk_pins[] = {
-	RCAR_GP_PIN(3, 0),
-};
-static const unsigned int vin1_clk_mux[] = {
-	VI1_CLK_MARK,
-};
-
-static const struct sh_pfc_pin_group pinmux_groups[] = {
-	SH_PFC_PIN_GROUP(avb_col),
-	SH_PFC_PIN_GROUP(avb_crs),
-	SH_PFC_PIN_GROUP(avb_link),
-	SH_PFC_PIN_GROUP(avb_magic),
-	SH_PFC_PIN_GROUP(avb_phy_int),
-	SH_PFC_PIN_GROUP(avb_mdio),
-	SH_PFC_PIN_GROUP(avb_mii_tx_rx),
-	SH_PFC_PIN_GROUP(avb_mii_tx_er),
-	SH_PFC_PIN_GROUP(avb_gmii_tx_rx),
-	SH_PFC_PIN_GROUP(avb_avtp_match_a),
-	SH_PFC_PIN_GROUP(avb_avtp_capture_a),
-	SH_PFC_PIN_GROUP(avb_avtp_match_b),
-	SH_PFC_PIN_GROUP(avb_avtp_capture_b),
-	SH_PFC_PIN_GROUP(du0_rgb666),
-	SH_PFC_PIN_GROUP(du0_rgb888),
-	SH_PFC_PIN_GROUP(du0_clk0_out),
-	SH_PFC_PIN_GROUP(du0_clk1_out),
-	SH_PFC_PIN_GROUP(du0_clk_in),
-	SH_PFC_PIN_GROUP(du0_sync),
-	SH_PFC_PIN_GROUP(du0_oddf),
-	SH_PFC_PIN_GROUP(du0_cde),
-	SH_PFC_PIN_GROUP(du0_disp),
-	SH_PFC_PIN_GROUP(du1_rgb666),
-	SH_PFC_PIN_GROUP(du1_rgb888),
-	SH_PFC_PIN_GROUP(du1_clk0_out),
-	SH_PFC_PIN_GROUP(du1_clk1_out),
-	SH_PFC_PIN_GROUP(du1_clk_in),
-	SH_PFC_PIN_GROUP(du1_sync),
-	SH_PFC_PIN_GROUP(du1_oddf),
-	SH_PFC_PIN_GROUP(du1_cde),
-	SH_PFC_PIN_GROUP(du1_disp),
-	SH_PFC_PIN_GROUP(i2c0_a),
-	SH_PFC_PIN_GROUP(i2c0_b),
-	SH_PFC_PIN_GROUP(i2c0_c),
-	SH_PFC_PIN_GROUP(i2c0_d),
-	SH_PFC_PIN_GROUP(i2c0_e),
-	SH_PFC_PIN_GROUP(i2c1_a),
-	SH_PFC_PIN_GROUP(i2c1_b),
-	SH_PFC_PIN_GROUP(i2c1_c),
-	SH_PFC_PIN_GROUP(i2c1_d),
-	SH_PFC_PIN_GROUP(i2c1_e),
-	SH_PFC_PIN_GROUP(i2c2_a),
-	SH_PFC_PIN_GROUP(i2c2_b),
-	SH_PFC_PIN_GROUP(i2c2_c),
-	SH_PFC_PIN_GROUP(i2c2_d),
-	SH_PFC_PIN_GROUP(i2c3_a),
-	SH_PFC_PIN_GROUP(i2c3_b),
-	SH_PFC_PIN_GROUP(i2c3_c),
-	SH_PFC_PIN_GROUP(i2c3_d),
-	SH_PFC_PIN_GROUP(i2c3_e),
-	SH_PFC_PIN_GROUP(i2c4_a),
-	SH_PFC_PIN_GROUP(i2c4_b),
-	SH_PFC_PIN_GROUP(i2c4_c),
-	SH_PFC_PIN_GROUP(i2c4_d),
-	SH_PFC_PIN_GROUP(i2c4_e),
-	SH_PFC_PIN_GROUP(mmc_data1),
-	SH_PFC_PIN_GROUP(mmc_data4),
-	SH_PFC_PIN_GROUP(mmc_data8),
-	SH_PFC_PIN_GROUP(mmc_ctrl),
-	SH_PFC_PIN_GROUP(qspi0_ctrl),
-	SH_PFC_PIN_GROUP(qspi0_data2),
-	SH_PFC_PIN_GROUP(qspi0_data4),
-	SH_PFC_PIN_GROUP(qspi1_ctrl),
-	SH_PFC_PIN_GROUP(qspi1_data2),
-	SH_PFC_PIN_GROUP(qspi1_data4),
-	SH_PFC_PIN_GROUP(scif0_data_a),
-	SH_PFC_PIN_GROUP(scif0_data_b),
-	SH_PFC_PIN_GROUP(scif0_data_c),
-	SH_PFC_PIN_GROUP(scif0_data_d),
-	SH_PFC_PIN_GROUP(scif1_data_a),
-	SH_PFC_PIN_GROUP(scif1_clk_a),
-	SH_PFC_PIN_GROUP(scif1_data_b),
-	SH_PFC_PIN_GROUP(scif1_clk_b),
-	SH_PFC_PIN_GROUP(scif1_data_c),
-	SH_PFC_PIN_GROUP(scif1_clk_c),
-	SH_PFC_PIN_GROUP(scif1_data_d),
-	SH_PFC_PIN_GROUP(scif2_data_a),
-	SH_PFC_PIN_GROUP(scif2_clk_a),
-	SH_PFC_PIN_GROUP(scif2_data_b),
-	SH_PFC_PIN_GROUP(scif2_clk_b),
-	SH_PFC_PIN_GROUP(scif2_data_c),
-	SH_PFC_PIN_GROUP(scif3_data_a),
-	SH_PFC_PIN_GROUP(scif3_clk),
-	SH_PFC_PIN_GROUP(scif3_data_b),
-	SH_PFC_PIN_GROUP(scif3_data_c),
-	SH_PFC_PIN_GROUP(scif4_data_a),
-	SH_PFC_PIN_GROUP(scif4_data_b),
-	SH_PFC_PIN_GROUP(scif4_data_c),
-	SH_PFC_PIN_GROUP(scif4_data_d),
-	SH_PFC_PIN_GROUP(scif4_data_e),
-	SH_PFC_PIN_GROUP(scif5_data_a),
-	SH_PFC_PIN_GROUP(scif5_data_b),
-	SH_PFC_PIN_GROUP(scif5_data_c),
-	SH_PFC_PIN_GROUP(scif5_data_d),
-	SH_PFC_PIN_GROUP(scif5_data_e),
-	SH_PFC_PIN_GROUP(scif5_data_f),
-	SH_PFC_PIN_GROUP(scif_clk_a),
-	SH_PFC_PIN_GROUP(scif_clk_b),
-	SH_PFC_PIN_GROUP(sdhi0_data1),
-	SH_PFC_PIN_GROUP(sdhi0_data4),
-	SH_PFC_PIN_GROUP(sdhi0_ctrl),
-	SH_PFC_PIN_GROUP(sdhi0_cd),
-	SH_PFC_PIN_GROUP(sdhi0_wp),
-	SH_PFC_PIN_GROUP(sdhi1_data1),
-	SH_PFC_PIN_GROUP(sdhi1_data4),
-	SH_PFC_PIN_GROUP(sdhi1_ctrl),
-	SH_PFC_PIN_GROUP(sdhi1_cd),
-	SH_PFC_PIN_GROUP(sdhi1_wp),
-	SH_PFC_PIN_GROUP(sdhi2_data1),
-	SH_PFC_PIN_GROUP(sdhi2_data4),
-	SH_PFC_PIN_GROUP(sdhi2_ctrl),
-	SH_PFC_PIN_GROUP(sdhi2_cd),
-	SH_PFC_PIN_GROUP(sdhi2_wp),
-	SH_PFC_PIN_GROUP(usb0),
-	SH_PFC_PIN_GROUP(usb1),
-	VIN_DATA_PIN_GROUP(vin0_data, 24),
-	VIN_DATA_PIN_GROUP(vin0_data, 20),
-	SH_PFC_PIN_GROUP(vin0_data18),
-	VIN_DATA_PIN_GROUP(vin0_data, 16),
-	VIN_DATA_PIN_GROUP(vin0_data, 12),
-	VIN_DATA_PIN_GROUP(vin0_data, 10),
-	VIN_DATA_PIN_GROUP(vin0_data, 8),
-	SH_PFC_PIN_GROUP(vin0_sync),
-	SH_PFC_PIN_GROUP(vin0_field),
-	SH_PFC_PIN_GROUP(vin0_clkenb),
-	SH_PFC_PIN_GROUP(vin0_clk),
-	VIN_DATA_PIN_GROUP(vin1_data, 12),
-	VIN_DATA_PIN_GROUP(vin1_data, 10),
-	VIN_DATA_PIN_GROUP(vin1_data, 8),
-	SH_PFC_PIN_GROUP(vin1_sync),
-	SH_PFC_PIN_GROUP(vin1_field),
-	SH_PFC_PIN_GROUP(vin1_clkenb),
-	SH_PFC_PIN_GROUP(vin1_clk),
-};
-
-static const char * const avb_groups[] = {
-	"avb_col",
-	"avb_crs",
-	"avb_link",
-	"avb_magic",
-	"avb_phy_int",
-	"avb_mdio",
-	"avb_mii_tx_rx",
-	"avb_mii_tx_er",
-	"avb_gmii_tx_rx",
-	"avb_avtp_match_a",
-	"avb_avtp_capture_a",
-	"avb_avtp_match_b",
-	"avb_avtp_capture_b",
-};
-
-static const char * const du0_groups[] = {
-	"du0_rgb666",
-	"du0_rgb888",
-	"du0_clk0_out",
-	"du0_clk1_out",
-	"du0_clk_in",
-	"du0_sync",
-	"du0_oddf",
-	"du0_cde",
-	"du0_disp",
-};
-
-static const char * const du1_groups[] = {
-	"du1_rgb666",
-	"du1_rgb888",
-	"du1_clk0_out",
-	"du1_clk1_out",
-	"du1_clk_in",
-	"du1_sync",
-	"du1_oddf",
-	"du1_cde",
-	"du1_disp",
-};
-
-static const char * const i2c0_groups[] = {
-	"i2c0_a",
-	"i2c0_b",
-	"i2c0_c",
-	"i2c0_d",
-	"i2c0_e",
-};
-
-static const char * const i2c1_groups[] = {
-	"i2c1_a",
-	"i2c1_b",
-	"i2c1_c",
-	"i2c1_d",
-	"i2c1_e",
-};
-
-static const char * const i2c2_groups[] = {
-	"i2c2_a",
-	"i2c2_b",
-	"i2c2_c",
-	"i2c2_d",
-};
-
-static const char * const i2c3_groups[] = {
-	"i2c3_a",
-	"i2c3_b",
-	"i2c3_c",
-	"i2c3_d",
-	"i2c3_e",
-};
-
-static const char * const i2c4_groups[] = {
-	"i2c4_a",
-	"i2c4_b",
-	"i2c4_c",
-	"i2c4_d",
-	"i2c4_e",
-};
-
-static const char * const mmc_groups[] = {
-	"mmc_data1",
-	"mmc_data4",
-	"mmc_data8",
-	"mmc_ctrl",
-};
-
-static const char * const qspi0_groups[] = {
-	"qspi0_ctrl",
-	"qspi0_data2",
-	"qspi0_data4",
-};
-
-static const char * const qspi1_groups[] = {
-	"qspi1_ctrl",
-	"qspi1_data2",
-	"qspi1_data4",
-};
-
-static const char * const scif0_groups[] = {
-	"scif0_data_a",
-	"scif0_data_b",
-	"scif0_data_c",
-	"scif0_data_d",
-};
-
-static const char * const scif1_groups[] = {
-	"scif1_data_a",
-	"scif1_clk_a",
-	"scif1_data_b",
-	"scif1_clk_b",
-	"scif1_data_c",
-	"scif1_clk_c",
-	"scif1_data_d",
-};
-
-static const char * const scif2_groups[] = {
-	"scif2_data_a",
-	"scif2_clk_a",
-	"scif2_data_b",
-	"scif2_clk_b",
-	"scif2_data_c",
-};
-
-static const char * const scif3_groups[] = {
-	"scif3_data_a",
-	"scif3_clk",
-	"scif3_data_b",
-	"scif3_data_c",
-};
-
-static const char * const scif4_groups[] = {
-	"scif4_data_a",
-	"scif4_data_b",
-	"scif4_data_c",
-	"scif4_data_d",
-	"scif4_data_e",
-};
-
-static const char * const scif5_groups[] = {
-	"scif5_data_a",
-	"scif5_data_b",
-	"scif5_data_c",
-	"scif5_data_d",
-	"scif5_data_e",
-	"scif5_data_f",
-};
-
-static const char * const scif_clk_groups[] = {
-	"scif_clk_a",
-	"scif_clk_b",
-};
-
-static const char * const sdhi0_groups[] = {
-	"sdhi0_data1",
-	"sdhi0_data4",
-	"sdhi0_ctrl",
-	"sdhi0_cd",
-	"sdhi0_wp",
-};
-
-static const char * const sdhi1_groups[] = {
-	"sdhi1_data1",
-	"sdhi1_data4",
-	"sdhi1_ctrl",
-	"sdhi1_cd",
-	"sdhi1_wp",
-};
-
-static const char * const sdhi2_groups[] = {
-	"sdhi2_data1",
-	"sdhi2_data4",
-	"sdhi2_ctrl",
-	"sdhi2_cd",
-	"sdhi2_wp",
-};
-
-static const char * const usb0_groups[] = {
-	"usb0",
-};
-
-static const char * const usb1_groups[] = {
-	"usb1",
-};
-
-static const char * const vin0_groups[] = {
-	"vin0_data24",
-	"vin0_data20",
-	"vin0_data18",
-	"vin0_data16",
-	"vin0_data12",
-	"vin0_data10",
-	"vin0_data8",
-	"vin0_sync",
-	"vin0_field",
-	"vin0_clkenb",
-	"vin0_clk",
-};
-
-static const char * const vin1_groups[] = {
-	"vin1_data12",
-	"vin1_data10",
-	"vin1_data8",
-	"vin1_sync",
-	"vin1_field",
-	"vin1_clkenb",
-	"vin1_clk",
-};
-
-static const struct sh_pfc_function pinmux_functions[] = {
-	SH_PFC_FUNCTION(avb),
-	SH_PFC_FUNCTION(du0),
-	SH_PFC_FUNCTION(du1),
-	SH_PFC_FUNCTION(i2c0),
-	SH_PFC_FUNCTION(i2c1),
-	SH_PFC_FUNCTION(i2c2),
-	SH_PFC_FUNCTION(i2c3),
-	SH_PFC_FUNCTION(i2c4),
-	SH_PFC_FUNCTION(mmc),
-	SH_PFC_FUNCTION(qspi0),
-	SH_PFC_FUNCTION(qspi1),
-	SH_PFC_FUNCTION(scif0),
-	SH_PFC_FUNCTION(scif1),
-	SH_PFC_FUNCTION(scif2),
-	SH_PFC_FUNCTION(scif3),
-	SH_PFC_FUNCTION(scif4),
-	SH_PFC_FUNCTION(scif5),
-	SH_PFC_FUNCTION(scif_clk),
-	SH_PFC_FUNCTION(sdhi0),
-	SH_PFC_FUNCTION(sdhi1),
-	SH_PFC_FUNCTION(sdhi2),
-	SH_PFC_FUNCTION(usb0),
-	SH_PFC_FUNCTION(usb1),
-	SH_PFC_FUNCTION(vin0),
-	SH_PFC_FUNCTION(vin1),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_0_22_FN, FN_MMC0_D7,
-		GP_0_21_FN, FN_MMC0_D6,
-		GP_0_20_FN, FN_IP1_7_4,
-		GP_0_19_FN, FN_IP1_3_0,
-		GP_0_18_FN, FN_MMC0_D3_SDHI1_D3,
-		GP_0_17_FN, FN_MMC0_D2_SDHI1_D2,
-		GP_0_16_FN, FN_MMC0_D1_SDHI1_D1,
-		GP_0_15_FN, FN_MMC0_D0_SDHI1_D0,
-		GP_0_14_FN, FN_MMC0_CMD_SDHI1_CMD,
-		GP_0_13_FN, FN_MMC0_CLK_SDHI1_CLK,
-		GP_0_12_FN, FN_IP0_31_28,
-		GP_0_11_FN, FN_IP0_27_24,
-		GP_0_10_FN, FN_IP0_23_20,
-		GP_0_9_FN, FN_IP0_19_16,
-		GP_0_8_FN, FN_IP0_15_12,
-		GP_0_7_FN, FN_IP0_11_8,
-		GP_0_6_FN, FN_IP0_7_4,
-		GP_0_5_FN, FN_IP0_3_0,
-		GP_0_4_FN, FN_CLKOUT,
-		GP_0_3_FN, FN_USB1_OVC,
-		GP_0_2_FN, FN_USB1_PWEN,
-		GP_0_1_FN, FN_USB0_OVC,
-		GP_0_0_FN, FN_USB0_PWEN, ))
-	},
-	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_1_22_FN, FN_IP4_3_0,
-		GP_1_21_FN, FN_IP3_31_28,
-		GP_1_20_FN, FN_IP3_27_24,
-		GP_1_19_FN, FN_IP3_23_20,
-		GP_1_18_FN, FN_IP3_19_16,
-		GP_1_17_FN, FN_IP3_15_12,
-		GP_1_16_FN, FN_IP3_11_8,
-		GP_1_15_FN, FN_IP3_7_4,
-		GP_1_14_FN, FN_IP3_3_0,
-		GP_1_13_FN, FN_IP2_31_28,
-		GP_1_12_FN, FN_IP2_27_24,
-		GP_1_11_FN, FN_IP2_23_20,
-		GP_1_10_FN, FN_IP2_19_16,
-		GP_1_9_FN, FN_IP2_15_12,
-		GP_1_8_FN, FN_IP2_11_8,
-		GP_1_7_FN, FN_IP2_7_4,
-		GP_1_6_FN, FN_IP2_3_0,
-		GP_1_5_FN, FN_IP1_31_28,
-		GP_1_4_FN, FN_IP1_27_24,
-		GP_1_3_FN, FN_IP1_23_20,
-		GP_1_2_FN, FN_IP1_19_16,
-		GP_1_1_FN, FN_IP1_15_12,
-		GP_1_0_FN, FN_IP1_11_8, ))
-	},
-	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
-		GP_2_31_FN, FN_IP8_3_0,
-		GP_2_30_FN, FN_IP7_31_28,
-		GP_2_29_FN, FN_IP7_27_24,
-		GP_2_28_FN, FN_IP7_23_20,
-		GP_2_27_FN, FN_IP7_19_16,
-		GP_2_26_FN, FN_IP7_15_12,
-		GP_2_25_FN, FN_IP7_11_8,
-		GP_2_24_FN, FN_IP7_7_4,
-		GP_2_23_FN, FN_IP7_3_0,
-		GP_2_22_FN, FN_IP6_31_28,
-		GP_2_21_FN, FN_IP6_27_24,
-		GP_2_20_FN, FN_IP6_23_20,
-		GP_2_19_FN, FN_IP6_19_16,
-		GP_2_18_FN, FN_IP6_15_12,
-		GP_2_17_FN, FN_IP6_11_8,
-		GP_2_16_FN, FN_IP6_7_4,
-		GP_2_15_FN, FN_IP6_3_0,
-		GP_2_14_FN, FN_IP5_31_28,
-		GP_2_13_FN, FN_IP5_27_24,
-		GP_2_12_FN, FN_IP5_23_20,
-		GP_2_11_FN, FN_IP5_19_16,
-		GP_2_10_FN, FN_IP5_15_12,
-		GP_2_9_FN, FN_IP5_11_8,
-		GP_2_8_FN, FN_IP5_7_4,
-		GP_2_7_FN, FN_IP5_3_0,
-		GP_2_6_FN, FN_IP4_31_28,
-		GP_2_5_FN, FN_IP4_27_24,
-		GP_2_4_FN, FN_IP4_23_20,
-		GP_2_3_FN, FN_IP4_19_16,
-		GP_2_2_FN, FN_IP4_15_12,
-		GP_2_1_FN, FN_IP4_11_8,
-		GP_2_0_FN, FN_IP4_7_4, ))
-	},
-	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		GP_3_29_FN, FN_IP10_19_16,
-		GP_3_28_FN, FN_IP10_15_12,
-		GP_3_27_FN, FN_IP10_11_8,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_3_16_FN, FN_IP10_7_4,
-		GP_3_15_FN, FN_IP10_3_0,
-		GP_3_14_FN, FN_IP9_31_28,
-		GP_3_13_FN, FN_IP9_27_24,
-		GP_3_12_FN, FN_IP9_23_20,
-		GP_3_11_FN, FN_IP9_19_16,
-		GP_3_10_FN, FN_IP9_15_12,
-		GP_3_9_FN, FN_IP9_11_8,
-		GP_3_8_FN, FN_IP9_7_4,
-		GP_3_7_FN, FN_IP9_3_0,
-		GP_3_6_FN, FN_IP8_31_28,
-		GP_3_5_FN, FN_IP8_27_24,
-		GP_3_4_FN, FN_IP8_23_20,
-		GP_3_3_FN, FN_IP8_19_16,
-		GP_3_2_FN, FN_IP8_15_12,
-		GP_3_1_FN, FN_IP8_11_8,
-		GP_3_0_FN, FN_IP8_7_4, ))
-	},
-	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_4_25_FN, FN_IP13_27_24,
-		GP_4_24_FN, FN_IP13_23_20,
-		GP_4_23_FN, FN_IP13_19_16,
-		GP_4_22_FN, FN_IP13_15_12,
-		GP_4_21_FN, FN_IP13_11_8,
-		GP_4_20_FN, FN_IP13_7_4,
-		GP_4_19_FN, FN_IP13_3_0,
-		GP_4_18_FN, FN_IP12_31_28,
-		GP_4_17_FN, FN_IP12_27_24,
-		GP_4_16_FN, FN_IP12_23_20,
-		GP_4_15_FN, FN_IP12_19_16,
-		GP_4_14_FN, FN_IP12_15_12,
-		GP_4_13_FN, FN_IP12_11_8,
-		GP_4_12_FN, FN_IP12_7_4,
-		GP_4_11_FN, FN_IP12_3_0,
-		GP_4_10_FN, FN_IP11_31_28,
-		GP_4_9_FN, FN_IP11_27_24,
-		GP_4_8_FN, FN_IP11_23_20,
-		GP_4_7_FN, FN_IP11_19_16,
-		GP_4_6_FN, FN_IP11_15_12,
-		GP_4_5_FN, FN_IP11_11_8,
-		GP_4_4_FN, FN_IP11_7_4,
-		GP_4_3_FN, FN_IP11_3_0,
-		GP_4_2_FN, FN_IP10_31_28,
-		GP_4_1_FN, FN_IP10_27_24,
-		GP_4_0_FN, FN_IP10_23_20, ))
-	},
-	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
-		GP_5_31_FN, FN_IP17_27_24,
-		GP_5_30_FN, FN_IP17_23_20,
-		GP_5_29_FN, FN_IP17_19_16,
-		GP_5_28_FN, FN_IP17_15_12,
-		GP_5_27_FN, FN_IP17_11_8,
-		GP_5_26_FN, FN_IP17_7_4,
-		GP_5_25_FN, FN_IP17_3_0,
-		GP_5_24_FN, FN_IP16_31_28,
-		GP_5_23_FN, FN_IP16_27_24,
-		GP_5_22_FN, FN_IP16_23_20,
-		GP_5_21_FN, FN_IP16_19_16,
-		GP_5_20_FN, FN_IP16_15_12,
-		GP_5_19_FN, FN_IP16_11_8,
-		GP_5_18_FN, FN_IP16_7_4,
-		GP_5_17_FN, FN_IP16_3_0,
-		GP_5_16_FN, FN_IP15_31_28,
-		GP_5_15_FN, FN_IP15_27_24,
-		GP_5_14_FN, FN_IP15_23_20,
-		GP_5_13_FN, FN_IP15_19_16,
-		GP_5_12_FN, FN_IP15_15_12,
-		GP_5_11_FN, FN_IP15_11_8,
-		GP_5_10_FN, FN_IP15_7_4,
-		GP_5_9_FN, FN_IP15_3_0,
-		GP_5_8_FN, FN_IP14_31_28,
-		GP_5_7_FN, FN_IP14_27_24,
-		GP_5_6_FN, FN_IP14_23_20,
-		GP_5_5_FN, FN_IP14_19_16,
-		GP_5_4_FN, FN_IP14_15_12,
-		GP_5_3_FN, FN_IP14_11_8,
-		GP_5_2_FN, FN_IP14_7_4,
-		GP_5_1_FN, FN_IP14_3_0,
-		GP_5_0_FN, FN_IP13_31_28, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
-			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
-			     GROUP(
-		/* IP0_31_28 [4] */
-		FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP0_27_24 [4] */
-		FN_SD0_CD, 0, FN_CAN0_RX_A, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP0_23_20 [4] */
-		FN_SD0_DAT3, 0, 0, FN_SSI_SDATA0_B, FN_TX5_E, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP0_19_16 [4] */
-		FN_SD0_DAT2, 0, 0, FN_SSI_WS0129_B, FN_RX5_E, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP0_15_12 [4] */
-		FN_SD0_DAT1, 0, 0, FN_SSI_SCK0129_B, FN_TX4_E, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP0_11_8 [4] */
-		FN_SD0_DAT0, 0, 0, FN_SSI_SDATA1_C, FN_RX4_E, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP0_7_4 [4] */
-		FN_SD0_CMD, 0, 0, FN_SSI_WS1_C, FN_TX3_C, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP0_3_0 [4] */
-		FN_SD0_CLK, 0, 0, FN_SSI_SCK1_C, FN_RX3_C, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
-			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
-			     GROUP(
-		/* IP1_31_28 [4] */
-		FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP1_27_24 [4] */
-		FN_D4, 0, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP1_23_20 [4] */
-		FN_D3, 0, FN_TX4_B, FN_SDA0_D, FN_PWM0_A,
-		FN_MSIOF2_SYNC_C, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP1_19_16 [4] */
-		FN_D2, 0, FN_RX4_B, FN_SCL0_D, FN_PWM1_C,
-		FN_MSIOF2_SCK_C, FN_SSI_SCK5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP1_15_12 [4] */
-		FN_D1, 0, FN_SDA3_B, FN_TX5_B, 0, FN_MSIOF2_TXD_C,
-		FN_SSI_WS5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP1_11_8 [4] */
-		FN_D0, 0, FN_SCL3_B, FN_RX5_B, FN_IRQ4,
-		FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP1_7_4 [4] */
-		FN_MMC0_D5, FN_SD1_WP, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP1_3_0 [4] */
-		FN_MMC0_D4, FN_SD1_CD, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
-			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
-			     GROUP(
-		/* IP2_31_28 [4] */
-		FN_D13, FN_MSIOF2_SYNC_A, 0, FN_RX4_C, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0,
-		/* IP2_27_24 [4] */
-		FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, 0, FN_CAN_CLK_C,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP2_23_20 [4] */
-		FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0,
-		/* IP2_19_16 [4] */
-		FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0,
-		/* IP2_15_12 [4] */
-		FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP2_11_8 [4] */
-		FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP2_7_4 [4] */
-		FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP2_3_0 [4] */
-		FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
-			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
-			     GROUP(
-		/* IP3_31_28 [4] */
-		FN_QSPI0_SSL, FN_WE1_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0,
-		/* IP3_27_24 [4] */
-		FN_QSPI0_IO3, FN_RD_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0,
-		/* IP3_23_20 [4] */
-		FN_QSPI0_IO2, FN_CS0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0,
-		/* IP3_19_16 [4] */
-		FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0,
-		/* IP3_15_12 [4] */
-		FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0,
-		/* IP3_11_8 [4] */
-		FN_QSPI0_SPCLK, FN_WE0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0,
-		/* IP3_7_4 [4] */
-		FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, 0, FN_CAN1_TX_B, FN_IRQ2,
-		FN_AVB_AVTP_MATCH_A, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP3_3_0 [4] */
-		FN_D14, FN_MSIOF2_SS1, 0, FN_TX4_C, FN_CAN1_RX_B,
-		0, FN_AVB_AVTP_CAPTURE_A,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
-			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
-			     GROUP(
-		/* IP4_31_28 [4] */
-		FN_DU0_DR6, 0, FN_RX2_C, 0, 0, 0, FN_A6, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP4_27_24 [4] */
-		FN_DU0_DR5, 0, FN_TX1_D, 0, FN_PWM1_B, 0, FN_A5, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP4_23_20 [4] */
-		FN_DU0_DR4, 0, FN_RX1_D, 0, 0, 0, FN_A4, 0, 0, 0, 0,
-		0, 0, 0, 0, 0,
-		/* IP4_19_16 [4] */
-		FN_DU0_DR3, 0, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, 0,
-		FN_A3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP4_15_12 [4] */
-		FN_DU0_DR2, 0, FN_RX0_D, FN_SCL0_E, 0, 0, FN_A2, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP4_11_8 [4] */
-		FN_DU0_DR1, 0, FN_TX5_C, FN_SDA2_D, 0, 0, FN_A1, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP4_7_4 [4] */
-		FN_DU0_DR0, 0, FN_RX5_C, FN_SCL2_D, 0, 0, FN_A0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP4_3_0 [4] */
-		FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
-			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
-			     GROUP(
-		/* IP5_31_28 [4] */
-		FN_DU0_DG6, 0, FN_HRX1_C, 0, 0, 0, FN_A14,  0, 0, 0,
-		0, 0, 0, 0, 0, 0,
-		/* IP5_27_24 [4] */
-		FN_DU0_DG5, 0, FN_HTX0_A, 0, FN_PWM5_B, 0, FN_A13,
-		0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP5_23_20 [4] */
-		FN_DU0_DG4, 0, FN_HRX0_A, 0, 0, 0, FN_A12, 0, 0, 0,
-		0, 0, 0, 0, 0, 0,
-		/* IP5_19_16 [4] */
-		FN_DU0_DG3, 0, FN_TX4_D, 0, FN_PWM4_B, 0, FN_A11, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP5_15_12 [4] */
-		FN_DU0_DG2, 0, FN_RX4_D, 0, 0, 0, FN_A10, 0, 0, 0,
-		0, 0, 0, 0, 0, 0,
-		/* IP5_11_8 [4] */
-		FN_DU0_DG1, 0, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, 0,
-		FN_A9, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP5_7_4 [4] */
-		FN_DU0_DG0, 0, FN_RX3_B, FN_SCL3_D, 0, 0, FN_A8, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP5_3_0 [4] */
-		FN_DU0_DR7, 0, FN_TX2_C, 0, FN_PWM2_B, 0, FN_A7, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
-			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
-			     GROUP(
-		/* IP6_31_28 [4] */
-		FN_DU0_DB6, 0, 0, 0, 0, 0, FN_A22, 0, 0,
-		0, 0, 0, 0, 0, 0, 0,
-		/* IP6_27_24 [4] */
-		FN_DU0_DB5, 0, FN_HRTS1_N_C, 0, 0, 0,
-		FN_A21, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP6_23_20 [4] */
-		FN_DU0_DB4, 0, FN_HCTS1_N_C, 0, 0, 0,
-		FN_A20, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP6_19_16 [4] */
-		FN_DU0_DB3, 0, FN_HRTS0_N, 0, 0, 0, FN_A19, 0, 0, 0,
-		0, 0, 0, 0, 0, 0,
-		/* IP6_15_12 [4] */
-		FN_DU0_DB2, 0, FN_HCTS0_N, 0, 0, 0, FN_A18, 0, 0, 0,
-		0, 0, 0, 0, 0, 0,
-		/* IP6_11_8 [4] */
-		FN_DU0_DB1, 0, 0, FN_SDA4_D, FN_CAN0_TX_C, 0, FN_A17,
-		0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP6_7_4 [4] */
-		FN_DU0_DB0, 0, 0, FN_SCL4_D, FN_CAN0_RX_C, 0, FN_A16,
-		0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP6_3_0 [4] */
-		FN_DU0_DG7, 0, FN_HTX1_C, 0,  FN_PWM6_B, 0, FN_A15,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
-			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
-			     GROUP(
-		/* IP7_31_28 [4] */
-		FN_DU0_DISP, 0, 0, 0, FN_CAN1_RX_C, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0,
-		/* IP7_27_24 [4] */
-		FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0, FN_MSIOF2_SCK_B,
-		0, 0, 0, FN_DRACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP7_23_20 [4] */
-		FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_MSIOF2_SYNC_B, 0,
-		0, 0, FN_DACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP7_19_16 [4] */
-		FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_MSIOF2_TXD_B, 0,
-		0, 0, FN_DREQ0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP7_15_12 [4] */
-		FN_DU0_DOTCLKOUT1, 0, FN_MSIOF2_RXD_B, 0, 0, 0,
-		FN_CS1_N_A26, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP7_11_8 [4] */
-		FN_DU0_DOTCLKOUT0, 0, 0, 0, 0, 0, FN_A25, 0, 0, 0, 0,
-		0, 0, 0, 0, 0,
-		/* IP7_7_4 [4] */
-		FN_DU0_DOTCLKIN, 0, 0, 0, 0, 0, FN_A24, 0, 0, 0,
-		0, 0, 0, 0, 0, 0,
-		/* IP7_3_0 [4] */
-		FN_DU0_DB7, 0, 0, 0, 0, 0, FN_A23, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32,
-			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
-			     GROUP(
-		/* IP8_31_28 [4] */
-		FN_VI1_DATA5, 0, 0, 0, FN_AVB_RXD4, FN_ETH_LINK, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0,
-		/* IP8_27_24 [4] */
-		FN_VI1_DATA4, 0, 0, 0, FN_AVB_RXD3, FN_ETH_RX_ER, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0,
-		/* IP8_23_20 [4] */
-		FN_VI1_DATA3, 0, 0, 0, FN_AVB_RXD2, FN_ETH_MDIO, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0,
-		/* IP8_19_16 [4] */
-		FN_VI1_DATA2, 0, 0, 0, FN_AVB_RXD1, FN_ETH_RXD1, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0,
-		/* IP8_15_12 [4] */
-		FN_VI1_DATA1, 0, 0, 0, FN_AVB_RXD0, FN_ETH_RXD0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0,
-		/* IP8_11_8 [4] */
-		FN_VI1_DATA0, 0, 0, 0, FN_AVB_RX_DV, FN_ETH_CRS_DV, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0,
-		/* IP8_7_4 [4] */
-		FN_VI1_CLK, 0, 0, 0, FN_AVB_RX_CLK, FN_ETH_REF_CLK, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0,
-		/* IP8_3_0 [4] */
-		FN_DU0_CDE, 0, 0, 0, FN_CAN1_TX_C, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32,
-			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
-			     GROUP(
-		/* IP9_31_28 [4] */
-		FN_VI1_DATA9, 0, 0, FN_SDA2_B, FN_AVB_TXD0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0,
-		/* IP9_27_24 [4] */
-		FN_VI1_DATA8, 0, 0, FN_SCL2_B, FN_AVB_TX_EN, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0,
-		/* IP9_23_20 [4] */
-		FN_VI1_VSYNC_N, FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B,
-		FN_AVB_TX_CLK, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP9_19_16 [4] */
-		FN_VI1_HSYNC_N, FN_RX0_B, FN_SCL0_C, 0, FN_AVB_GTXREFCLK,
-		FN_ETH_MDC, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP9_15_12 [4] */
-		FN_VI1_FIELD, FN_SDA3_A, 0, 0, FN_AVB_RX_ER, FN_ETH_TXD0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP9_11_8 [4] */
-		FN_VI1_CLKENB, FN_SCL3_A, 0, 0, FN_AVB_RXD7, FN_ETH_MAGIC, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP9_7_4 [4] */
-		FN_VI1_DATA7, 0, 0, 0, FN_AVB_RXD6, FN_ETH_TX_EN, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0,
-		/* IP9_3_0 [4] */
-		FN_VI1_DATA6, 0, 0, 0, FN_AVB_RXD5, FN_ETH_TXD1, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060068, 32,
-			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
-			     GROUP(
-		/* IP10_31_28 [4] */
-		FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, 0, 0,
-		FN_SSI_SCK6_B, FN_VI0_G0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP10_27_24 [4] */
-		FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK,
-		FN_CAN1_TX_D, FN_DVC_MUTE, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP10_23_20 [4] */
-		FN_SCL0_A, FN_RX0_C, FN_PWM5_A, FN_TCLK1_B, FN_AVB_TXD6,
-		FN_CAN1_RX_D, FN_MSIOF0_SYNC_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP10_19_16 [4] */
-		FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, 0,
-		FN_SSI_SDATA1_D, 0, FN_MSIOF0_SCK_B, 0, 0, 0, 0, 0, 0, 0,
-		0, 0,
-		/* IP10_15_12 [4] */
-		FN_AVB_TXD4, 0, FN_AUDIO_CLKB_B, 0, FN_SSI_WS1_D, FN_TX5_F,
-		FN_MSIOF0_TXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP10_11_8 [4] */
-		FN_AVB_TXD3, 0, FN_AUDIO_CLKA_B, 0, FN_SSI_SCK1_D, FN_RX5_F,
-		FN_MSIOF0_RXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP10_7_4 [4] */
-		FN_VI1_DATA11, 0, 0, FN_CAN0_TX_B, FN_AVB_TXD2, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0,
-		/* IP10_3_0 [4] */
-		FN_VI1_DATA10, 0, 0, FN_CAN0_RX_B, FN_AVB_TXD1, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606006C, 32,
-			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
-			     GROUP(
-		/* IP11_31_28 [4] */
-		FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP11_27_24 [4] */
-		FN_MSIOF0_SS2_A, 0, 0, FN_DU1_DR7, 0,
-		FN_QSPI1_SSL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP11_23_20 [4] */
-		FN_MSIOF0_SS1_A, 0, 0, FN_DU1_DR6, 0,
-		FN_QSPI1_IO3, FN_SSI_SDATA8_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP11_19_16 [4] */
-		FN_MSIOF0_SYNC_A, FN_PWM1_A, 0, FN_DU1_DR5,
-		0, FN_QSPI1_IO2, FN_SSI_SDATA7_B, 0, 0, 0, 0, 0,
-		0, 0, 0, 0,
-		/* IP11_15_12 [4] */
-		FN_MSIOF0_SCK_A, FN_IRQ0, 0, FN_DU1_DR4,
-		0, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP11_11_8 [4] */
-		FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, 0,
-		FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP11_7_4 [4] */
-		FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, 0,
-		FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP11_3_0 [4] */
-		FN_SDA1_A, FN_TX4_A, 0, FN_DU1_DR1, 0, 0, FN_SSI_WS6_B,
-		FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060070, 32,
-			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
-			     GROUP(
-		/* IP12_31_28 [4] */
-		FN_SD2_DAT2, FN_RX2_A, 0, FN_DU1_DB0, FN_SSI_SDATA2_B, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP12_27_24 [4] */
-		FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP12_23_20 [4] */
-		FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6,
-		FN_SSI_SDATA1_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP12_19_16 [4] */
-		FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5,
-		FN_SSI_SCK2_B, FN_PWM3_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP12_15_12 [4] */
-		FN_SD2_CLK, FN_HSCK1, 0, FN_DU1_DG4, FN_SSI_SCK1_B, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP12_11_8 [4] */
-		FN_HRTS1_N_A, 0, 0, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP12_7_4 [4] */
-		FN_HCTS1_N_A, FN_PWM2_A, 0, FN_DU1_DG2, FN_REMOCON_B,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP12_3_0 [4] */
-		FN_HTX1_A, FN_SDA4_A, 0, FN_DU1_DG1, FN_TX0_A, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060074, 32,
-			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
-			     GROUP(
-		/* IP13_31_28 [4] */
-		FN_SSI_SCK5_A, 0, 0, FN_DU1_DOTCLKOUT1, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0,
-		/* IP13_27_24 [4] */
-		FN_SDA2_A, 0, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP13_23_20 [4] */
-		FN_SCL2_A, 0, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C,
-		FN_SSI_SCK4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP13_19_16 [4] */
-		FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5,
-		FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP13_15_12 [4] */
-		FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4,
-		FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0,
-		/* IP13_11_8 [4] */
-		FN_SD2_WP, FN_SCIF3_SCK, 0, FN_DU1_DB3, FN_SSI_SDATA9_B, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP13_7_4 [4] */
-		FN_SD2_CD, FN_SCIF2_SCK_A, 0, FN_DU1_DB2, FN_SSI_SCK9_B, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP13_3_0 [4] */
-		FN_SD2_DAT3, FN_TX2_A, 0, FN_DU1_DB1, FN_SSI_WS9_B, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060078, 32,
-			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
-			     GROUP(
-		/* IP14_31_28 [4] */
-		FN_SSI_SDATA7_A, 0, 0, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
-		FN_VI0_G5, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP14_27_24 [4] */
-		FN_SSI_WS78_A, 0, FN_SCL4_E, FN_DU1_CDE, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0,
-		/* IP14_23_20 [4] */
-		FN_SSI_SCK78_A, 0, FN_SDA4_E, FN_DU1_DISP, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0,
-		/* IP14_19_16 [4] */
-		FN_SSI_SDATA6_A, 0, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP14_15_12 [4] */
-		FN_SSI_WS6_A, 0, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP14_11_8 [4] */
-		FN_SSI_SCK6_A, 0, 0, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP14_7_4 [4] */
-		FN_SSI_SDATA5_A, 0, FN_SDA3_C, FN_DU1_DOTCLKOUT0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP14_3_0 [4] */
-		FN_SSI_WS5_A, 0, FN_SCL3_C, FN_DU1_DOTCLKIN, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606007C, 32,
-			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
-			     GROUP(
-		/* IP15_31_28 [4] */
-		FN_SSI_WS4_A, 0, FN_AVB_PHY_INT, 0, 0, 0, FN_VI0_R5, 0, 0, 0,
-		0, 0, 0, 0, 0, 0,
-		/* IP15_27_24 [4] */
-		FN_SSI_SCK4_A, 0, FN_AVB_MAGIC, 0, 0, 0, FN_VI0_R4, 0, 0, 0,
-		0, 0, 0, 0, 0, 0,
-		/* IP15_23_20 [4] */
-		FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, 0, FN_CAN1_TX_A,
-		FN_DREQ2_N, FN_VI0_R3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP15_19_16 [4] */
-		FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, 0, FN_CAN1_RX_A,
-		FN_DREQ1_N, FN_VI0_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP15_15_12 [4] */
-		FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, 0, 0, FN_DACK1,
-		FN_VI0_R1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP15_11_8 [4] */
-		FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, 0, 0, 0,
-		FN_VI0_R0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP15_7_4 [4] */
-		FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, 0, 0, 0,
-		FN_VI0_G7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP15_3_0 [4] */
-		FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, 0, 0, 0,
-		FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060080, 32,
-			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
-			     GROUP(
-		/* IP16_31_28 [4] */
-		FN_SSI_SDATA2_A, FN_HRTS1_N_B, 0, 0, 0, 0,
-		FN_VI0_DATA4_VI0_B4, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP16_27_24 [4] */
-		FN_SSI_WS2_A, FN_HCTS1_N_B, 0, 0, 0, FN_AVB_TX_ER,
-		FN_VI0_DATA3_VI0_B3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP16_23_20 [4] */
-		FN_SSI_SCK2_A, FN_HTX1_B, 0, 0, 0, FN_AVB_TXD7,
-		FN_VI0_DATA2_VI0_B2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP16_19_16 [4] */
-		FN_SSI_SDATA1_A, FN_HRX1_B, 0, 0, 0, 0, FN_VI0_DATA1_VI0_B1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP16_15_12 [4] */
-		FN_SSI_WS1_A, FN_TX1_B, 0, 0, FN_CAN0_TX_D,
-		FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0,
-		/* IP16_11_8 [4] */
-		FN_SSI_SDATA8_A, FN_RX1_B, 0, 0, FN_CAN0_RX_D,
-		FN_AVB_AVTP_CAPTURE_B, FN_VI0_R7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP16_7_4 [4] */
-		FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A,
-		FN_DACK2, FN_VI0_CLK, FN_AVB_COL, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP16_3_0 [4] */
-		FN_SSI_SDATA4_A, 0, FN_AVB_CRS, 0, 0, 0, FN_VI0_R6, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32,
-			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
-			     GROUP(
-		/* IP17_31_28 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP17_27_24 [4] */
-		FN_AUDIO_CLKOUT_A, FN_SDA4_B, 0, 0, 0, 0,
-		FN_VI0_VSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP17_23_20 [4] */
-		FN_AUDIO_CLKC_A, FN_SCL4_B, 0, 0, 0, 0,
-		FN_VI0_HSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP17_19_16 [4] */
-		FN_AUDIO_CLKB_A, FN_SDA0_B, 0, 0, 0, 0,
-		FN_VI0_FIELD, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP17_15_12 [4] */
-		FN_AUDIO_CLKA_A, FN_SCL0_B, 0, 0, 0, 0,
-		FN_VI0_CLKENB, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP17_11_8 [4] */
-		FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, 0, 0, 0,
-		FN_VI0_DATA7_VI0_B7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP17_7_4 [4] */
-		FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, 0, 0, 0,
-		FN_VI0_DATA6_VI0_B6, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP17_3_0 [4] */
-		FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, 0, 0, FN_EX_WAIT1,
-		FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32,
-			     GROUP(1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 2, 1,
-				   3, 3, 1, 2, 3, 3, 1),
-			     GROUP(
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* SEL_ADGA [2] */
-		FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* SEL_CANCLK [2] */
-		FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
-		FN_SEL_CANCLK_3,
-		/* SEL_CAN1 [2] */
-		FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
-		/* SEL_CAN0 [2] */
-		FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
-		/* RESERVED [1] */
-		0, 0,
-		/* SEL_I2C04 [3] */
-		FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
-		FN_SEL_I2C04_4, 0, 0, 0,
-		/* SEL_I2C03 [3] */
-		FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
-		FN_SEL_I2C03_4, 0, 0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* SEL_I2C02 [2] */
-		FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
-		/* SEL_I2C01 [3] */
-		FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
-		FN_SEL_I2C01_4, 0, 0, 0,
-		/* SEL_I2C00 [3] */
-		FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
-		FN_SEL_I2C00_4, 0, 0, 0,
-		/* SEL_AVB [1] */
-		FN_SEL_AVB_0, FN_SEL_AVB_1, ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32,
-			     GROUP(1, 3, 3, 2, 2, 1, 2, 2, 2, 1, 1, 1,
-				   1, 1, 2, 1, 1, 2, 2, 1),
-			     GROUP(
-		/* SEL_SCIFCLK [1] */
-		FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
-		/* SEL_SCIF5 [3] */
-		FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
-		FN_SEL_SCIF5_4, FN_SEL_SCIF5_5, 0, 0,
-		/* SEL_SCIF4 [3] */
-		FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
-		FN_SEL_SCIF4_4, 0, 0, 0,
-		/* SEL_SCIF3 [2] */
-		FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, 0,
-		/* SEL_SCIF2 [2] */
-		FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
-		/* SEL_SCIF2_CLK [1] */
-		FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1,
-		/* SEL_SCIF1 [2] */
-		FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
-		/* SEL_SCIF0 [2] */
-		FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
-		/* SEL_MSIOF2 [2] */
-		FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* SEL_MSIOF1 [1] */
-		FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
-		/* RESERVED [1] */
-		0, 0,
-		/* SEL_MSIOF0 [1] */
-		FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1,
-		/* SEL_RCN [1] */
-		FN_SEL_RCN_0, FN_SEL_RCN_1,
-		/* RESERVED [2] */
-		0, 0, 0, 0,
-		/* SEL_TMU2 [1] */
-		FN_SEL_TMU2_0, FN_SEL_TMU2_1,
-		/* SEL_TMU1 [1] */
-		FN_SEL_TMU1_0, FN_SEL_TMU1_1,
-		/* RESERVED [2] */
-		0, 0, 0, 0,
-		/* SEL_HSCIF1 [2] */
-		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 0,
-		/* SEL_HSCIF0 [1] */
-		FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32,
-			     GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
-				   2, 2, 2, 2, 2, 2, 2, 2, 2),
-			     GROUP(
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* SEL_ADGB [2] */
-		FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2, 0,
-		/* SEL_ADGC [2] */
-		FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2, 0,
-		/* SEL_SSI9 [2] */
-		FN_SEL_SSI9_0, FN_SEL_SSI9_1, 0, 0,
-		/* SEL_SSI8 [2] */
-		FN_SEL_SSI8_0, FN_SEL_SSI8_1, 0, 0,
-		/* SEL_SSI7 [2] */
-		FN_SEL_SSI7_0, FN_SEL_SSI7_1, 0, 0,
-		/* SEL_SSI6 [2] */
-		FN_SEL_SSI6_0, FN_SEL_SSI6_1, 0, 0,
-		/* SEL_SSI5 [2] */
-		FN_SEL_SSI5_0, FN_SEL_SSI5_1, 0, 0,
-		/* SEL_SSI4 [2] */
-		FN_SEL_SSI4_0, FN_SEL_SSI4_1, 0, 0,
-		/* SEL_SSI2 [2] */
-		FN_SEL_SSI2_0, FN_SEL_SSI2_1, 0, 0,
-		/* SEL_SSI1 [2] */
-		FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3,
-		/* SEL_SSI0 [2] */
-		FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, ))
-	},
-	{ },
-};
-
-static int r8a77470_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
-				   u32 *pocctrl)
-{
-	int bit = -EINVAL;
-
-	*pocctrl = 0xe60600b0;
-
-	if (pin >= RCAR_GP_PIN(0, 5) && pin <= RCAR_GP_PIN(0, 10))
-		bit = 0;
-
-	if (pin >= RCAR_GP_PIN(0, 13) && pin <= RCAR_GP_PIN(0, 22))
-		bit = 2;
-
-	if (pin >= RCAR_GP_PIN(4, 14) && pin <= RCAR_GP_PIN(4, 19))
-		bit = 1;
-
-	return bit;
-}
-
-static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = {
-	.pin_to_pocctrl = r8a77470_pin_to_pocctrl,
-};
-
-#ifdef CONFIG_PINCTRL_PFC_R8A77470
-const struct sh_pfc_soc_info r8a77470_pinmux_info = {
-	.name = "r8a77470_pfc",
-	.ops = &r8a77470_pinmux_ops,
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups,
-	.nr_groups = ARRAY_SIZE(pinmux_groups),
-	.functions = pinmux_functions,
-	.nr_functions = ARRAY_SIZE(pinmux_functions),
-
-	.cfg_regs = pinmux_config_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
-#endif
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
deleted file mode 100644
index a9875038ed9b..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ /dev/null
@@ -1,3185 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * r8a7778 processor support - PFC hardware block
- *
- * Copyright (C) 2013  Renesas Solutions Corp.
- * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
- * Copyright (C) 2013  Cogent Embedded, Inc.
- * Copyright (C) 2015  Ulrich Hecht
- *
- * based on
- * Copyright (C) 2011  Renesas Solutions Corp.
- * Copyright (C) 2011  Magnus Damm
- */
-
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/pinctrl/pinconf-generic.h>
-
-#include "core.h"
-#include "sh_pfc.h"
-
-#define PORT_GP_PUP_1(bank, pin, fn, sfx)	\
-	PORT_GP_CFG_1(bank, pin, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
-
-#define CPU_ALL_GP(fn, sfx)		\
-	PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
-	PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
-	PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
-	PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
-	PORT_GP_CFG_27(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
-
-#define CPU_ALL_NOGP(fn)		\
-	PIN_NOGP(CLKOUT, "B25", fn),	\
-	PIN_NOGP(CS0, "A20", fn),	\
-	PIN_NOGP(CS1_A26, "C20", fn)
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	GP_ALL(DATA), /* GP_0_0_DATA -> GP_4_26_DATA */
-	PINMUX_DATA_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	GP_ALL(FN), /* GP_0_0_FN -> GP_4_26_FN */
-
-	/* GPSR0 */
-	FN_IP0_1_0,	FN_PENC0,	FN_PENC1,	FN_IP0_4_2,
-	FN_IP0_7_5,	FN_IP0_11_8,	FN_IP0_14_12,	FN_A1,
-	FN_A2,		FN_A3,		FN_IP0_15,	FN_IP0_16,
-	FN_IP0_17,	FN_IP0_18,	FN_IP0_19,	FN_IP0_20,
-	FN_IP0_21,	FN_IP0_22,	FN_IP0_23,	FN_IP0_24,
-	FN_IP0_25,	FN_IP0_26,	FN_IP0_27,	FN_IP0_28,
-	FN_IP0_29,	FN_IP0_30,	FN_IP1_0,	FN_IP1_1,
-	FN_IP1_4_2,	FN_IP1_7_5,	FN_IP1_10_8,	FN_IP1_14_11,
-
-	/* GPSR1 */
-	FN_IP1_23_21,	FN_WE0,		FN_IP1_24,	FN_IP1_27_25,
-	FN_IP1_29_28,	FN_IP2_2_0,	FN_IP2_5_3,	FN_IP2_8_6,
-	FN_IP2_11_9,	FN_IP2_13_12,	FN_IP2_16_14,	FN_IP2_17,
-	FN_IP2_30,	FN_IP2_31,	FN_IP3_1_0,	FN_IP3_4_2,
-	FN_IP3_7_5,	FN_IP3_9_8,	FN_IP3_12_10,	FN_IP3_15_13,
-	FN_IP3_18_16,	FN_IP3_20_19,	FN_IP3_23_21,	FN_IP3_26_24,
-	FN_IP3_27,	FN_IP3_28,	FN_IP3_29,	FN_IP3_30,
-	FN_IP3_31,	FN_IP4_0,	FN_IP4_3_1,	FN_IP4_6_4,
-
-	/* GPSR2 */
-	FN_IP4_7,	FN_IP4_8,	FN_IP4_10_9,	FN_IP4_12_11,
-	FN_IP4_14_13,	FN_IP4_16_15,	FN_IP4_20_17,	FN_IP4_24_21,
-	FN_IP4_26_25,	FN_IP4_28_27,	FN_IP4_30_29,	FN_IP5_1_0,
-	FN_IP5_3_2,	FN_IP5_5_4,	FN_IP5_6,	FN_IP5_7,
-	FN_IP5_9_8,	FN_IP5_11_10,	FN_IP5_12,	FN_IP5_14_13,
-	FN_IP5_17_15,	FN_IP5_20_18,	FN_AUDIO_CLKA,	FN_AUDIO_CLKB,
-	FN_IP5_22_21,	FN_IP5_25_23,	FN_IP5_28_26,	FN_IP5_30_29,
-	FN_IP6_1_0,	FN_IP6_4_2,	FN_IP6_6_5,	FN_IP6_7,
-
-	/* GPSR3 */
-	FN_IP6_8,	FN_IP6_9,	FN_SSI_SCK34,	FN_IP6_10,
-	FN_IP6_12_11,	FN_IP6_13,	FN_IP6_15_14,	FN_IP6_16,
-	FN_IP6_18_17,	FN_IP6_20_19,	FN_IP6_21,	FN_IP6_23_22,
-	FN_IP6_25_24,	FN_IP6_27_26,	FN_IP6_29_28,	FN_IP6_31_30,
-	FN_IP7_1_0,	FN_IP7_3_2,	FN_IP7_5_4,	FN_IP7_8_6,
-	FN_IP7_11_9,	FN_IP7_14_12,	FN_IP7_17_15,	FN_IP7_20_18,
-	FN_IP7_21,	FN_IP7_24_22,	FN_IP7_28_25,	FN_IP7_31_29,
-	FN_IP8_2_0,	FN_IP8_5_3,	FN_IP8_8_6,	FN_IP8_10_9,
-
-	/* GPSR4 */
-	FN_IP8_13_11,	FN_IP8_15_14,	FN_IP8_18_16,	FN_IP8_21_19,
-	FN_IP8_23_22,	FN_IP8_26_24,	FN_IP8_29_27,	FN_IP9_2_0,
-	FN_IP9_5_3,	FN_IP9_8_6,	FN_IP9_11_9,	FN_IP9_14_12,
-	FN_IP9_17_15,	FN_IP9_20_18,	FN_IP9_23_21,	FN_IP9_26_24,
-	FN_IP9_29_27,	FN_IP10_2_0,	FN_IP10_5_3,	FN_IP10_8_6,
-	FN_IP10_12_9,	FN_IP10_15_13,	FN_IP10_18_16,	FN_IP10_21_19,
-	FN_IP10_24_22,	FN_AVS1,	FN_AVS2,
-
-	/* IPSR0 */
-	FN_PRESETOUT,	FN_PWM1,	FN_AUDATA0,	FN_ARM_TRACEDATA_0,
-	FN_GPSCLK_C,	FN_USB_OVC0,	FN_TX2_E,	FN_SDA2_B,
-	FN_AUDATA1,	FN_ARM_TRACEDATA_1,		FN_GPSIN_C,
-	FN_USB_OVC1,	FN_RX2_E,	FN_SCL2_B,	FN_SD1_DAT2_A,
-	FN_MMC_D2,	FN_BS,		FN_ATADIR0_A,	FN_SDSELF_A,
-	FN_PWM4_B,	FN_SD1_DAT3_A,	FN_MMC_D3,	FN_A0,
-	FN_ATAG0_A,	FN_REMOCON_B,	FN_A4,		FN_A5,
-	FN_A6,		FN_A7,		FN_A8,		FN_A9,
-	FN_A10,		FN_A11,		FN_A12,		FN_A13,
-	FN_A14,		FN_A15,		FN_A16,		FN_A17,
-	FN_A18,		FN_A19,
-
-	/* IPSR1 */
-	FN_A20,		FN_HSPI_CS1_B,	FN_A21,		FN_HSPI_CLK1_B,
-	FN_A22,		FN_HRTS0_B,	FN_RX2_B,	FN_DREQ2_A,
-	FN_A23,		FN_HTX0_B,	FN_TX2_B,	FN_DACK2_A,
-	FN_TS_SDEN0_A,	FN_SD1_CD_A,	FN_MMC_D6,	FN_A24,
-	FN_DREQ1_A,	FN_HRX0_B,	FN_TS_SPSYNC0_A,
-	FN_SD1_WP_A,	FN_MMC_D7,	FN_A25,	FN_DACK1_A,
-	FN_HCTS0_B,	FN_RX3_C,	FN_TS_SDAT0_A,	FN_CLKOUT,
-	FN_HSPI_TX1_B,	FN_PWM0_B,	FN_CS0,		FN_HSPI_RX1_B,
-	FN_SSI_SCK1_B,	FN_ATAG0_B,	FN_CS1_A26,	FN_SDA2_A,
-	FN_SCK2_B,	FN_MMC_D5,	FN_ATADIR0_B,	FN_RD_WR,
-	FN_WE1,		FN_ATAWR0_B,	FN_SSI_WS1_B,	FN_EX_CS0,
-	FN_SCL2_A,	FN_TX3_C,	FN_TS_SCK0_A,	FN_EX_CS1,
-	FN_MMC_D4,
-
-	/* IPSR2 */
-	FN_SD1_CLK_A,	FN_MMC_CLK,	FN_ATACS00,	FN_EX_CS2,
-	FN_SD1_CMD_A,	FN_MMC_CMD,	FN_ATACS10,	FN_EX_CS3,
-	FN_SD1_DAT0_A,	FN_MMC_D0,	FN_ATARD0,	FN_EX_CS4,
-	FN_EX_WAIT1_A,	FN_SD1_DAT1_A,	FN_MMC_D1,	FN_ATAWR0_A,
-	FN_EX_CS5,	FN_EX_WAIT2_A,	FN_DREQ0_A,	FN_RX3_A,
-	FN_DACK0,	FN_TX3_A,	FN_DRACK0,	FN_EX_WAIT0,
-	FN_PWM0_C,	FN_D0,		FN_D1,		FN_D2,
-	FN_D3,		FN_D4,		FN_D5,		FN_D6,
-	FN_D7,		FN_D8,		FN_D9,		FN_D10,
-	FN_D11,		FN_RD_WR_B,	FN_IRQ0,	FN_MLB_CLK,
-	FN_IRQ1_A,
-
-	/* IPSR3 */
-	FN_MLB_SIG,	FN_RX5_B,	FN_SDA3_A,	FN_IRQ2_A,
-	FN_MLB_DAT,	FN_TX5_B,	FN_SCL3_A,	FN_IRQ3_A,
-	FN_SDSELF_B,	FN_SD1_CMD_B,	FN_SCIF_CLK,	FN_AUDIO_CLKOUT_B,
-	FN_CAN_CLK_B,	FN_SDA3_B,	FN_SD1_CLK_B,	FN_HTX0_A,
-	FN_TX0_A,	FN_SD1_DAT0_B,	FN_HRX0_A,	FN_RX0_A,
-	FN_SD1_DAT1_B,	FN_HSCK0,	FN_SCK0,	FN_SCL3_B,
-	FN_SD1_DAT2_B,	FN_HCTS0_A,	FN_CTS0,	FN_SD1_DAT3_B,
-	FN_HRTS0_A,	FN_RTS0,	FN_SSI_SCK4,	FN_DU0_DR0,
-	FN_LCDOUT0,	FN_AUDATA2,	FN_ARM_TRACEDATA_2,
-	FN_SDA3_C,	FN_ADICHS1,	FN_TS_SDEN0_B,	FN_SSI_WS4,
-	FN_DU0_DR1,	FN_LCDOUT1,	FN_AUDATA3,	FN_ARM_TRACEDATA_3,
-	FN_SCL3_C,	FN_ADICHS2,	FN_TS_SPSYNC0_B,
-	FN_DU0_DR2,	FN_LCDOUT2,	FN_DU0_DR3,	FN_LCDOUT3,
-	FN_DU0_DR4,	FN_LCDOUT4,	FN_DU0_DR5,	FN_LCDOUT5,
-	FN_DU0_DR6,	FN_LCDOUT6,
-
-	/* IPSR4 */
-	FN_DU0_DR7,	FN_LCDOUT7,	FN_DU0_DG0,	FN_LCDOUT8,
-	FN_AUDATA4,	FN_ARM_TRACEDATA_4,		FN_TX1_D,
-	FN_CAN0_TX_A,	FN_ADICHS0,	FN_DU0_DG1,	FN_LCDOUT9,
-	FN_AUDATA5,	FN_ARM_TRACEDATA_5,		FN_RX1_D,
-	FN_CAN0_RX_A,	FN_ADIDATA,	FN_DU0_DG2,	FN_LCDOUT10,
-	FN_DU0_DG3,	FN_LCDOUT11,	FN_DU0_DG4,	FN_LCDOUT12,
-	FN_RX0_B,	FN_DU0_DG5,	FN_LCDOUT13,	FN_TX0_B,
-	FN_DU0_DG6,	FN_LCDOUT14,	FN_RX4_A,	FN_DU0_DG7,
-	FN_LCDOUT15,	FN_TX4_A,	FN_SSI_SCK2_B,	FN_VI0_R0_B,
-	FN_DU0_DB0,	FN_LCDOUT16,	FN_AUDATA6,	FN_ARM_TRACEDATA_6,
-	FN_GPSCLK_A,	FN_PWM0_A,	FN_ADICLK,	FN_TS_SDAT0_B,
-	FN_AUDIO_CLKC,	FN_VI0_R1_B,	FN_DU0_DB1,	FN_LCDOUT17,
-	FN_AUDATA7,	FN_ARM_TRACEDATA_7,		FN_GPSIN_A,
-	FN_ADICS_SAMP,	FN_TS_SCK0_B,	FN_VI0_R2_B,	FN_DU0_DB2,
-	FN_LCDOUT18,	FN_VI0_R3_B,	FN_DU0_DB3,	FN_LCDOUT19,
-	FN_VI0_R4_B,	FN_DU0_DB4,	FN_LCDOUT20,
-
-	/* IPSR5 */
-	FN_VI0_R5_B,	FN_DU0_DB5,	FN_LCDOUT21,	FN_VI1_DATA10_B,
-	FN_DU0_DB6,	FN_LCDOUT22,	FN_VI1_DATA11_B,
-	FN_DU0_DB7,	FN_LCDOUT23,	FN_DU0_DOTCLKIN,
-	FN_QSTVA_QVS,	FN_DU0_DOTCLKO_UT0,		FN_QCLK,
-	FN_DU0_DOTCLKO_UT1,		FN_QSTVB_QVE,	FN_AUDIO_CLKOUT_A,
-	FN_REMOCON_C,	FN_SSI_WS2_B,	FN_DU0_EXHSYNC_DU0_HSYNC,
-	FN_QSTH_QHS,	FN_DU0_EXVSYNC_DU0_VSYNC,	FN_QSTB_QHE,
-	FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,
-	FN_QCPV_QDE,	FN_FMCLK_D,	FN_SSI_SCK1_A,	FN_DU0_DISP,
-	FN_QPOLA,	FN_AUDCK,	FN_ARM_TRACECLK,
-	FN_BPFCLK_D,	FN_SSI_WS1_A,	FN_DU0_CDE,	FN_QPOLB,
-	FN_AUDSYNC,	FN_ARM_TRACECTL,		FN_FMIN_D,
-	FN_SD1_CD_B,	FN_SSI_SCK78,	FN_HSPI_RX0_B,	FN_TX1_B,
-	FN_SD1_WP_B,	FN_SSI_WS78,	FN_HSPI_CLK0_B,	FN_RX1_B,
-	FN_CAN_CLK_D,	FN_SSI_SDATA8,	FN_SSI_SCK2_A,	FN_HSPI_CS0_B,
-	FN_TX2_A,	FN_CAN0_TX_B,	FN_SSI_SDATA7,	FN_HSPI_TX0_B,
-	FN_RX2_A,	FN_CAN0_RX_B,
-
-	/* IPSR6 */
-	FN_SSI_SCK6,	FN_HSPI_RX2_A,	FN_FMCLK_B,	FN_CAN1_TX_B,
-	FN_SSI_WS6,	FN_HSPI_CLK2_A,	FN_BPFCLK_B,	FN_CAN1_RX_B,
-	FN_SSI_SDATA6,	FN_HSPI_TX2_A,	FN_FMIN_B,	FN_SSI_SCK5,
-	FN_RX4_C,	FN_SSI_WS5,	FN_TX4_C,	FN_SSI_SDATA5,
-	FN_RX0_D,	FN_SSI_WS34,	FN_ARM_TRACEDATA_8,
-	FN_SSI_SDATA4,	FN_SSI_WS2_A,	FN_ARM_TRACEDATA_9,
-	FN_SSI_SDATA3,	FN_ARM_TRACEDATA_10,
-	FN_SSI_SCK012,	FN_ARM_TRACEDATA_11,
-	FN_TX0_D,	FN_SSI_WS012,	FN_ARM_TRACEDATA_12,
-	FN_SSI_SDATA2,	FN_HSPI_CS2_A,	FN_ARM_TRACEDATA_13,
-	FN_SDA1_A,	FN_SSI_SDATA1,	FN_ARM_TRACEDATA_14,
-	FN_SCL1_A,	FN_SCK2_A,	FN_SSI_SDATA0,
-	FN_ARM_TRACEDATA_15,
-	FN_SD0_CLK,	FN_SUB_TDO,	FN_SD0_CMD,	FN_SUB_TRST,
-	FN_SD0_DAT0,	FN_SUB_TMS,	FN_SD0_DAT1,	FN_SUB_TCK,
-	FN_SD0_DAT2,	FN_SUB_TDI,
-
-	/* IPSR7 */
-	FN_SD0_DAT3,	FN_IRQ1_B,	FN_SD0_CD,	FN_TX5_A,
-	FN_SD0_WP,	FN_RX5_A,	FN_VI1_CLKENB,	FN_HSPI_CLK0_A,
-	FN_HTX1_A,	FN_RTS1_C,	FN_VI1_FIELD,	FN_HSPI_CS0_A,
-	FN_HRX1_A,	FN_SCK1_C,	FN_VI1_HSYNC,	FN_HSPI_RX0_A,
-	FN_HRTS1_A,	FN_FMCLK_A,	FN_RX1_C,	FN_VI1_VSYNC,
-	FN_HSPI_TX0,	FN_HCTS1_A,	FN_BPFCLK_A,	FN_TX1_C,
-	FN_TCLK0,	FN_HSCK1_A,	FN_FMIN_A,	FN_IRQ2_C,
-	FN_CTS1_C,	FN_SPEEDIN,	FN_VI0_CLK,	FN_CAN_CLK_A,
-	FN_VI0_CLKENB,	FN_SD2_DAT2_B,	FN_VI1_DATA0,	FN_DU1_DG6,
-	FN_HSPI_RX1_A,	FN_RX4_B,	FN_VI0_FIELD,	FN_SD2_DAT3_B,
-	FN_VI0_R3_C,	FN_VI1_DATA1,	FN_DU1_DG7,	FN_HSPI_CLK1_A,
-	FN_TX4_B,	FN_VI0_HSYNC,	FN_SD2_CD_B,	FN_VI1_DATA2,
-	FN_DU1_DR2,	FN_HSPI_CS1_A,	FN_RX3_B,
-
-	/* IPSR8 */
-	FN_VI0_VSYNC,	FN_SD2_WP_B,	FN_VI1_DATA3,	FN_DU1_DR3,
-	FN_HSPI_TX1_A,	FN_TX3_B,	FN_VI0_DATA0_VI0_B0,
-	FN_DU1_DG2,	FN_IRQ2_B,	FN_RX3_D,	FN_VI0_DATA1_VI0_B1,
-	FN_DU1_DG3,	FN_IRQ3_B,	FN_TX3_D,	FN_VI0_DATA2_VI0_B2,
-	FN_DU1_DG4,	FN_RX0_C,	FN_VI0_DATA3_VI0_B3,
-	FN_DU1_DG5,	FN_TX1_A,	FN_TX0_C,	FN_VI0_DATA4_VI0_B4,
-	FN_DU1_DB2,	FN_RX1_A,	FN_VI0_DATA5_VI0_B5,
-	FN_DU1_DB3,	FN_SCK1_A,	FN_PWM4,	FN_HSCK1_B,
-	FN_VI0_DATA6_VI0_G0,		FN_DU1_DB4,	FN_CTS1_A,
-	FN_PWM5,	FN_VI0_DATA7_VI0_G1,		FN_DU1_DB5,
-	FN_RTS1_A,	FN_VI0_G2,	FN_SD2_CLK_B,	FN_VI1_DATA4,
-	FN_DU1_DR4,	FN_HTX1_B,	FN_VI0_G3,	FN_SD2_CMD_B,
-	FN_VI1_DATA5,	FN_DU1_DR5,	FN_HRX1_B,
-
-	/* IPSR9 */
-	FN_VI0_G4,	FN_SD2_DAT0_B,	FN_VI1_DATA6,	FN_DU1_DR6,
-	FN_HRTS1_B,	FN_VI0_G5,	FN_SD2_DAT1_B,	FN_VI1_DATA7,
-	FN_DU1_DR7,	FN_HCTS1_B,	FN_VI0_R0_A,	FN_VI1_CLK,
-	FN_ETH_REF_CLK,	FN_DU1_DOTCLKIN,		FN_VI0_R1_A,
-	FN_VI1_DATA8,	FN_DU1_DB6,	FN_ETH_TXD0,	FN_PWM2,
-	FN_TCLK1,	FN_VI0_R2_A,	FN_VI1_DATA9,	FN_DU1_DB7,
-	FN_ETH_TXD1,	FN_PWM3,	FN_VI0_R3_A,	FN_ETH_CRS_DV,
-	FN_IECLK,	FN_SCK2_C,	FN_VI0_R4_A,	FN_ETH_TX_EN,
-	FN_IETX,	FN_TX2_C,	FN_VI0_R5_A,	FN_ETH_RX_ER,
-	FN_FMCLK_C,	FN_IERX,	FN_RX2_C,	FN_VI1_DATA10_A,
-	FN_DU1_DOTCLKOUT,		FN_ETH_RXD0,	FN_BPFCLK_C,
-	FN_TX2_D,	FN_SDA2_C,	FN_VI1_DATA11_A,
-	FN_DU1_EXHSYNC_DU1_HSYNC,	FN_ETH_RXD1,	FN_FMIN_C,
-	FN_RX2_D,	FN_SCL2_C,
-
-	/* IPSR10 */
-	FN_SD2_CLK_A,	FN_DU1_EXVSYNC_DU1_VSYNC,	FN_ATARD1,
-	FN_ETH_MDC,	FN_SDA1_B,	FN_SD2_CMD_A,
-	FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,		FN_ATAWR1,
-	FN_ETH_MDIO,	FN_SCL1_B,	FN_SD2_DAT0_A,	FN_DU1_DISP,
-	FN_ATACS01,	FN_DREQ1_B,	FN_ETH_LINK,	FN_CAN1_RX_A,
-	FN_SD2_DAT1_A,	FN_DU1_CDE,	FN_ATACS11,	FN_DACK1_B,
-	FN_ETH_MAGIC,	FN_CAN1_TX_A,	FN_PWM6,	FN_SD2_DAT2_A,
-	FN_VI1_DATA12,	FN_DREQ2_B,	FN_ATADIR1,	FN_HSPI_CLK2_B,
-	FN_GPSCLK_B,	FN_SD2_DAT3_A,	FN_VI1_DATA13,	FN_DACK2_B,
-	FN_ATAG1,	FN_HSPI_CS2_B,	FN_GPSIN_B,	FN_SD2_CD_A,
-	FN_VI1_DATA14,	FN_EX_WAIT1_B,	FN_DREQ0_B,	FN_HSPI_RX2_B,
-	FN_REMOCON_A,	FN_SD2_WP_A,	FN_VI1_DATA15,	FN_EX_WAIT2_B,
-	FN_DACK0_B,	FN_HSPI_TX2_B,	FN_CAN_CLK_C,
-
-	/* SEL */
-	FN_SEL_SCIF5_A,	FN_SEL_SCIF5_B,
-	FN_SEL_SCIF4_A,	FN_SEL_SCIF4_B,	FN_SEL_SCIF4_C,
-	FN_SEL_SCIF3_A,	FN_SEL_SCIF3_B,	FN_SEL_SCIF3_C,	FN_SEL_SCIF3_D,
-	FN_SEL_SCIF2_A,	FN_SEL_SCIF2_B,	FN_SEL_SCIF2_C,	FN_SEL_SCIF2_D,	FN_SEL_SCIF2_E,
-	FN_SEL_SCIF1_A,	FN_SEL_SCIF1_B,	FN_SEL_SCIF1_C,	FN_SEL_SCIF1_D,
-	FN_SEL_SCIF0_A,	FN_SEL_SCIF0_B,	FN_SEL_SCIF0_C,	FN_SEL_SCIF0_D,
-	FN_SEL_SSI2_A,	FN_SEL_SSI2_B,
-	FN_SEL_SSI1_A,	FN_SEL_SSI1_B,
-	FN_SEL_VI1_A,	FN_SEL_VI1_B,
-	FN_SEL_VI0_A,	FN_SEL_VI0_B,	FN_SEL_VI0_C,	FN_SEL_VI0_D,
-	FN_SEL_SD2_A,	FN_SEL_SD2_B,
-	FN_SEL_SD1_A,	FN_SEL_SD1_B,
-	FN_SEL_IRQ3_A,	FN_SEL_IRQ3_B,
-	FN_SEL_IRQ2_A,	FN_SEL_IRQ2_B,	FN_SEL_IRQ2_C,
-	FN_SEL_IRQ1_A,	FN_SEL_IRQ1_B,
-	FN_SEL_DREQ2_A,	FN_SEL_DREQ2_B,
-	FN_SEL_DREQ1_A,	FN_SEL_DREQ1_B,
-	FN_SEL_DREQ0_A,	FN_SEL_DREQ0_B,
-	FN_SEL_WAIT2_A,	FN_SEL_WAIT2_B,
-	FN_SEL_WAIT1_A,	FN_SEL_WAIT1_B,
-	FN_SEL_CAN1_A,	FN_SEL_CAN1_B,
-	FN_SEL_CAN0_A,	FN_SEL_CAN0_B,
-	FN_SEL_CANCLK_A,	FN_SEL_CANCLK_B,
-	FN_SEL_CANCLK_C,	FN_SEL_CANCLK_D,
-	FN_SEL_HSCIF1_A,	FN_SEL_HSCIF1_B,
-	FN_SEL_HSCIF0_A,	FN_SEL_HSCIF0_B,
-	FN_SEL_REMOCON_A,	FN_SEL_REMOCON_B,	FN_SEL_REMOCON_C,
-	FN_SEL_FM_A,	FN_SEL_FM_B,	FN_SEL_FM_C,	FN_SEL_FM_D,
-	FN_SEL_GPS_A,	FN_SEL_GPS_B,	FN_SEL_GPS_C,
-	FN_SEL_TSIF0_A,	FN_SEL_TSIF0_B,
-	FN_SEL_HSPI2_A,	FN_SEL_HSPI2_B,
-	FN_SEL_HSPI1_A,	FN_SEL_HSPI1_B,
-	FN_SEL_HSPI0_A,	FN_SEL_HSPI0_B,
-	FN_SEL_I2C3_A,	FN_SEL_I2C3_B,	FN_SEL_I2C3_C,
-	FN_SEL_I2C2_A,	FN_SEL_I2C2_B,	FN_SEL_I2C2_C,
-	FN_SEL_I2C1_A,	FN_SEL_I2C1_B,
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-
-	/* GPSR0 */
-	PENC0_MARK,	PENC1_MARK,	A1_MARK,	A2_MARK,	A3_MARK,
-
-	/* GPSR1 */
-	WE0_MARK,
-
-	/* GPSR2 */
-	AUDIO_CLKA_MARK,
-	AUDIO_CLKB_MARK,
-
-	/* GPSR3 */
-	SSI_SCK34_MARK,
-
-	/* GPSR4 */
-	AVS1_MARK,
-	AVS2_MARK,
-
-	VI0_R0_C_MARK,		/* see sel_vi0 */
-	VI0_R1_C_MARK,		/* see sel_vi0 */
-	VI0_R2_C_MARK,		/* see sel_vi0 */
-	/* VI0_R3_C_MARK, */
-	VI0_R4_C_MARK,		/* see sel_vi0 */
-	VI0_R5_C_MARK,		/* see sel_vi0 */
-
-	VI0_R0_D_MARK,		/* see sel_vi0 */
-	VI0_R1_D_MARK,		/* see sel_vi0 */
-	VI0_R2_D_MARK,		/* see sel_vi0 */
-	VI0_R3_D_MARK,		/* see sel_vi0 */
-	VI0_R4_D_MARK,		/* see sel_vi0 */
-	VI0_R5_D_MARK,		/* see sel_vi0 */
-
-	/* IPSR0 */
-	PRESETOUT_MARK,	PWM1_MARK,	AUDATA0_MARK,
-	ARM_TRACEDATA_0_MARK,		GPSCLK_C_MARK,	USB_OVC0_MARK,
-	TX2_E_MARK,	SDA2_B_MARK,	AUDATA1_MARK,	ARM_TRACEDATA_1_MARK,
-	GPSIN_C_MARK,	USB_OVC1_MARK,	RX2_E_MARK,	SCL2_B_MARK,
-	SD1_DAT2_A_MARK,		MMC_D2_MARK,	BS_MARK,
-	ATADIR0_A_MARK,	SDSELF_A_MARK,	PWM4_B_MARK,	SD1_DAT3_A_MARK,
-	MMC_D3_MARK,	A0_MARK,	ATAG0_A_MARK,	REMOCON_B_MARK,
-	A4_MARK,	A5_MARK,	A6_MARK,	A7_MARK,
-	A8_MARK,	A9_MARK,	A10_MARK,	A11_MARK,
-	A12_MARK,	A13_MARK,	A14_MARK,	A15_MARK,
-	A16_MARK,	A17_MARK,	A18_MARK,	A19_MARK,
-
-	/* IPSR1 */
-	A20_MARK,	HSPI_CS1_B_MARK,		A21_MARK,
-	HSPI_CLK1_B_MARK,		A22_MARK,	HRTS0_B_MARK,
-	RX2_B_MARK,	DREQ2_A_MARK,	A23_MARK,	HTX0_B_MARK,
-	TX2_B_MARK,	DACK2_A_MARK,	TS_SDEN0_A_MARK,
-	SD1_CD_A_MARK,	MMC_D6_MARK,	A24_MARK,	DREQ1_A_MARK,
-	HRX0_B_MARK,	TS_SPSYNC0_A_MARK,		SD1_WP_A_MARK,
-	MMC_D7_MARK,	A25_MARK,	DACK1_A_MARK,	HCTS0_B_MARK,
-	RX3_C_MARK,	TS_SDAT0_A_MARK,		CLKOUT_MARK,
-	HSPI_TX1_B_MARK,		PWM0_B_MARK,	CS0_MARK,
-	HSPI_RX1_B_MARK,		SSI_SCK1_B_MARK,
-	ATAG0_B_MARK,	CS1_A26_MARK,	SDA2_A_MARK,	SCK2_B_MARK,
-	MMC_D5_MARK,	ATADIR0_B_MARK,	RD_WR_MARK,	WE1_MARK,
-	ATAWR0_B_MARK,	SSI_WS1_B_MARK,	EX_CS0_MARK,	SCL2_A_MARK,
-	TX3_C_MARK,	TS_SCK0_A_MARK,	EX_CS1_MARK,	MMC_D4_MARK,
-
-	/* IPSR2 */
-	SD1_CLK_A_MARK,	MMC_CLK_MARK,	ATACS00_MARK,	EX_CS2_MARK,
-	SD1_CMD_A_MARK,	MMC_CMD_MARK,	ATACS10_MARK,	EX_CS3_MARK,
-	SD1_DAT0_A_MARK,		MMC_D0_MARK,	ATARD0_MARK,
-	EX_CS4_MARK,	EX_WAIT1_A_MARK,		SD1_DAT1_A_MARK,
-	MMC_D1_MARK,	ATAWR0_A_MARK,	EX_CS5_MARK,	EX_WAIT2_A_MARK,
-	DREQ0_A_MARK,	RX3_A_MARK,	DACK0_MARK,	TX3_A_MARK,
-	DRACK0_MARK,	EX_WAIT0_MARK,	PWM0_C_MARK,	D0_MARK,
-	D1_MARK,	D2_MARK,	D3_MARK,	D4_MARK,
-	D5_MARK,	D6_MARK,	D7_MARK,	D8_MARK,
-	D9_MARK,	D10_MARK,	D11_MARK,	RD_WR_B_MARK,
-	IRQ0_MARK,	MLB_CLK_MARK,	IRQ1_A_MARK,
-
-	/* IPSR3 */
-	MLB_SIG_MARK,	RX5_B_MARK,	SDA3_A_MARK,	IRQ2_A_MARK,
-	MLB_DAT_MARK,	TX5_B_MARK,	SCL3_A_MARK,	IRQ3_A_MARK,
-	SDSELF_B_MARK,	SD1_CMD_B_MARK,	SCIF_CLK_MARK,	AUDIO_CLKOUT_B_MARK,
-	CAN_CLK_B_MARK,	SDA3_B_MARK,	SD1_CLK_B_MARK,	HTX0_A_MARK,
-	TX0_A_MARK,	SD1_DAT0_B_MARK,		HRX0_A_MARK,
-	RX0_A_MARK,	SD1_DAT1_B_MARK,		HSCK0_MARK,
-	SCK0_MARK,	SCL3_B_MARK,	SD1_DAT2_B_MARK,
-	HCTS0_A_MARK,	CTS0_MARK,	SD1_DAT3_B_MARK,
-	HRTS0_A_MARK,	RTS0_MARK,	SSI_SCK4_MARK,
-	DU0_DR0_MARK,	LCDOUT0_MARK,	AUDATA2_MARK,	ARM_TRACEDATA_2_MARK,
-	SDA3_C_MARK,	ADICHS1_MARK,	TS_SDEN0_B_MARK,
-	SSI_WS4_MARK,	DU0_DR1_MARK,	LCDOUT1_MARK,	AUDATA3_MARK,
-	ARM_TRACEDATA_3_MARK,		SCL3_C_MARK,	ADICHS2_MARK,
-	TS_SPSYNC0_B_MARK,		DU0_DR2_MARK,	LCDOUT2_MARK,
-	DU0_DR3_MARK,	LCDOUT3_MARK,	DU0_DR4_MARK,	LCDOUT4_MARK,
-	DU0_DR5_MARK,	LCDOUT5_MARK,	DU0_DR6_MARK,	LCDOUT6_MARK,
-
-	/* IPSR4 */
-	DU0_DR7_MARK,	LCDOUT7_MARK,	DU0_DG0_MARK,	LCDOUT8_MARK,
-	AUDATA4_MARK,	ARM_TRACEDATA_4_MARK,
-	TX1_D_MARK,	CAN0_TX_A_MARK,	ADICHS0_MARK,	DU0_DG1_MARK,
-	LCDOUT9_MARK,	AUDATA5_MARK,	ARM_TRACEDATA_5_MARK,
-	RX1_D_MARK,	CAN0_RX_A_MARK,	ADIDATA_MARK,	DU0_DG2_MARK,
-	LCDOUT10_MARK,	DU0_DG3_MARK,	LCDOUT11_MARK,	DU0_DG4_MARK,
-	LCDOUT12_MARK,	RX0_B_MARK,	DU0_DG5_MARK,	LCDOUT13_MARK,
-	TX0_B_MARK,	DU0_DG6_MARK,	LCDOUT14_MARK,	RX4_A_MARK,
-	DU0_DG7_MARK,	LCDOUT15_MARK,	TX4_A_MARK,	SSI_SCK2_B_MARK,
-	VI0_R0_B_MARK,	DU0_DB0_MARK,	LCDOUT16_MARK,	AUDATA6_MARK,
-	ARM_TRACEDATA_6_MARK,		GPSCLK_A_MARK,	PWM0_A_MARK,
-	ADICLK_MARK,	TS_SDAT0_B_MARK,		AUDIO_CLKC_MARK,
-	VI0_R1_B_MARK,	DU0_DB1_MARK,	LCDOUT17_MARK,	AUDATA7_MARK,
-	ARM_TRACEDATA_7_MARK,		GPSIN_A_MARK,	ADICS_SAMP_MARK,
-	TS_SCK0_B_MARK,	VI0_R2_B_MARK,	DU0_DB2_MARK,	LCDOUT18_MARK,
-	VI0_R3_B_MARK,	DU0_DB3_MARK,	LCDOUT19_MARK,	VI0_R4_B_MARK,
-	DU0_DB4_MARK,	LCDOUT20_MARK,
-
-	/* IPSR5 */
-	VI0_R5_B_MARK,	DU0_DB5_MARK,	LCDOUT21_MARK,	VI1_DATA10_B_MARK,
-	DU0_DB6_MARK,	LCDOUT22_MARK,	VI1_DATA11_B_MARK,
-	DU0_DB7_MARK,	LCDOUT23_MARK,	DU0_DOTCLKIN_MARK,
-	QSTVA_QVS_MARK,	DU0_DOTCLKO_UT0_MARK,
-	QCLK_MARK,	DU0_DOTCLKO_UT1_MARK,		QSTVB_QVE_MARK,
-	AUDIO_CLKOUT_A_MARK,		REMOCON_C_MARK,	SSI_WS2_B_MARK,
-	DU0_EXHSYNC_DU0_HSYNC_MARK,	QSTH_QHS_MARK,
-	DU0_EXVSYNC_DU0_VSYNC_MARK,	QSTB_QHE_MARK,
-	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
-	QCPV_QDE_MARK,	FMCLK_D_MARK,	SSI_SCK1_A_MARK,
-	DU0_DISP_MARK,	QPOLA_MARK,	AUDCK_MARK,	ARM_TRACECLK_MARK,
-	BPFCLK_D_MARK,	SSI_WS1_A_MARK,	DU0_CDE_MARK,	QPOLB_MARK,
-	AUDSYNC_MARK,	ARM_TRACECTL_MARK,		FMIN_D_MARK,
-	SD1_CD_B_MARK,	SSI_SCK78_MARK,	HSPI_RX0_B_MARK,
-	TX1_B_MARK,	SD1_WP_B_MARK,	SSI_WS78_MARK,	HSPI_CLK0_B_MARK,
-	RX1_B_MARK,	CAN_CLK_D_MARK,	SSI_SDATA8_MARK,
-	SSI_SCK2_A_MARK,		HSPI_CS0_B_MARK,
-	TX2_A_MARK,	CAN0_TX_B_MARK,	SSI_SDATA7_MARK,
-	HSPI_TX0_B_MARK,		RX2_A_MARK,	CAN0_RX_B_MARK,
-
-	/* IPSR6 */
-	SSI_SCK6_MARK,	HSPI_RX2_A_MARK,		FMCLK_B_MARK,
-	CAN1_TX_B_MARK,	SSI_WS6_MARK,	HSPI_CLK2_A_MARK,
-	BPFCLK_B_MARK,	CAN1_RX_B_MARK,	SSI_SDATA6_MARK,
-	HSPI_TX2_A_MARK,		FMIN_B_MARK,	SSI_SCK5_MARK,
-	RX4_C_MARK,	SSI_WS5_MARK,	TX4_C_MARK,	SSI_SDATA5_MARK,
-	RX0_D_MARK,	SSI_WS34_MARK,	ARM_TRACEDATA_8_MARK,
-	SSI_SDATA4_MARK,		SSI_WS2_A_MARK,	ARM_TRACEDATA_9_MARK,
-	SSI_SDATA3_MARK,		ARM_TRACEDATA_10_MARK,
-	SSI_SCK012_MARK,		ARM_TRACEDATA_11_MARK,
-	TX0_D_MARK,	SSI_WS012_MARK,	ARM_TRACEDATA_12_MARK,
-	SSI_SDATA2_MARK,		HSPI_CS2_A_MARK,
-	ARM_TRACEDATA_13_MARK,		SDA1_A_MARK,	SSI_SDATA1_MARK,
-	ARM_TRACEDATA_14_MARK,		SCL1_A_MARK,	SCK2_A_MARK,
-	SSI_SDATA0_MARK,		ARM_TRACEDATA_15_MARK,
-	SD0_CLK_MARK,	SUB_TDO_MARK,	SD0_CMD_MARK,	SUB_TRST_MARK,
-	SD0_DAT0_MARK,	SUB_TMS_MARK,	SD0_DAT1_MARK,	SUB_TCK_MARK,
-	SD0_DAT2_MARK,	SUB_TDI_MARK,
-
-	/* IPSR7 */
-	SD0_DAT3_MARK,	IRQ1_B_MARK,	SD0_CD_MARK,	TX5_A_MARK,
-	SD0_WP_MARK,	RX5_A_MARK,	VI1_CLKENB_MARK,
-	HSPI_CLK0_A_MARK,	HTX1_A_MARK,	RTS1_C_MARK,	VI1_FIELD_MARK,
-	HSPI_CS0_A_MARK,	HRX1_A_MARK,	SCK1_C_MARK,	VI1_HSYNC_MARK,
-	HSPI_RX0_A_MARK,	HRTS1_A_MARK,	FMCLK_A_MARK,	RX1_C_MARK,
-	VI1_VSYNC_MARK,	HSPI_TX0_MARK,	HCTS1_A_MARK,	BPFCLK_A_MARK,
-	TX1_C_MARK,	TCLK0_MARK,	HSCK1_A_MARK,	FMIN_A_MARK,
-	IRQ2_C_MARK,	CTS1_C_MARK,	SPEEDIN_MARK,	VI0_CLK_MARK,
-	CAN_CLK_A_MARK,	VI0_CLKENB_MARK,		SD2_DAT2_B_MARK,
-	VI1_DATA0_MARK,	DU1_DG6_MARK,	HSPI_RX1_A_MARK,
-	RX4_B_MARK,	VI0_FIELD_MARK,	SD2_DAT3_B_MARK,
-	VI0_R3_C_MARK,	VI1_DATA1_MARK,	DU1_DG7_MARK,	HSPI_CLK1_A_MARK,
-	TX4_B_MARK,	VI0_HSYNC_MARK,	SD2_CD_B_MARK,	VI1_DATA2_MARK,
-	DU1_DR2_MARK,	HSPI_CS1_A_MARK,		RX3_B_MARK,
-
-	/* IPSR8 */
-	VI0_VSYNC_MARK,	SD2_WP_B_MARK,	VI1_DATA3_MARK,	DU1_DR3_MARK,
-	HSPI_TX1_A_MARK,		TX3_B_MARK,	VI0_DATA0_VI0_B0_MARK,
-	DU1_DG2_MARK,	IRQ2_B_MARK,	RX3_D_MARK,	VI0_DATA1_VI0_B1_MARK,
-	DU1_DG3_MARK,	IRQ3_B_MARK,	TX3_D_MARK,	VI0_DATA2_VI0_B2_MARK,
-	DU1_DG4_MARK,	RX0_C_MARK,	VI0_DATA3_VI0_B3_MARK,
-	DU1_DG5_MARK,	TX1_A_MARK,	TX0_C_MARK,	VI0_DATA4_VI0_B4_MARK,
-	DU1_DB2_MARK,	RX1_A_MARK,	VI0_DATA5_VI0_B5_MARK,
-	DU1_DB3_MARK,	SCK1_A_MARK,	PWM4_MARK,	HSCK1_B_MARK,
-	VI0_DATA6_VI0_G0_MARK,		DU1_DB4_MARK,	CTS1_A_MARK,
-	PWM5_MARK,	VI0_DATA7_VI0_G1_MARK,		DU1_DB5_MARK,
-	RTS1_A_MARK,	VI0_G2_MARK,	SD2_CLK_B_MARK,	VI1_DATA4_MARK,
-	DU1_DR4_MARK,	HTX1_B_MARK,	VI0_G3_MARK,	SD2_CMD_B_MARK,
-	VI1_DATA5_MARK,	DU1_DR5_MARK,	HRX1_B_MARK,
-
-	/* IPSR9 */
-	VI0_G4_MARK,	SD2_DAT0_B_MARK,		VI1_DATA6_MARK,
-	DU1_DR6_MARK,	HRTS1_B_MARK,	VI0_G5_MARK,	SD2_DAT1_B_MARK,
-	VI1_DATA7_MARK,	DU1_DR7_MARK,	HCTS1_B_MARK,	VI0_R0_A_MARK,
-	VI1_CLK_MARK,	ETH_REF_CLK_MARK,		DU1_DOTCLKIN_MARK,
-	VI0_R1_A_MARK,	VI1_DATA8_MARK,	DU1_DB6_MARK,	ETH_TXD0_MARK,
-	PWM2_MARK,	TCLK1_MARK,	VI0_R2_A_MARK,	VI1_DATA9_MARK,
-	DU1_DB7_MARK,	ETH_TXD1_MARK,	PWM3_MARK,	VI0_R3_A_MARK,
-	ETH_CRS_DV_MARK,		IECLK_MARK,	SCK2_C_MARK,
-	VI0_R4_A_MARK,			ETH_TX_EN_MARK,	IETX_MARK,
-	TX2_C_MARK,	VI0_R5_A_MARK,	ETH_RX_ER_MARK,	FMCLK_C_MARK,
-	IERX_MARK,	RX2_C_MARK,	VI1_DATA10_A_MARK,
-	DU1_DOTCLKOUT_MARK,		ETH_RXD0_MARK,
-	BPFCLK_C_MARK,	TX2_D_MARK,	SDA2_C_MARK,	VI1_DATA11_A_MARK,
-	DU1_EXHSYNC_DU1_HSYNC_MARK,	ETH_RXD1_MARK,	FMIN_C_MARK,
-	RX2_D_MARK,	SCL2_C_MARK,
-
-	/* IPSR10 */
-	SD2_CLK_A_MARK,	DU1_EXVSYNC_DU1_VSYNC_MARK,	ATARD1_MARK,
-	ETH_MDC_MARK,	SDA1_B_MARK,	SD2_CMD_A_MARK,
-	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,		ATAWR1_MARK,
-	ETH_MDIO_MARK,	SCL1_B_MARK,	SD2_DAT0_A_MARK,
-	DU1_DISP_MARK,	ATACS01_MARK,	DREQ1_B_MARK,	ETH_LINK_MARK,
-	CAN1_RX_A_MARK,	SD2_DAT1_A_MARK,		DU1_CDE_MARK,
-	ATACS11_MARK,	DACK1_B_MARK,	ETH_MAGIC_MARK,	CAN1_TX_A_MARK,
-	PWM6_MARK,	SD2_DAT2_A_MARK,		VI1_DATA12_MARK,
-	DREQ2_B_MARK,	ATADIR1_MARK,	HSPI_CLK2_B_MARK,
-	GPSCLK_B_MARK,	SD2_DAT3_A_MARK,		VI1_DATA13_MARK,
-	DACK2_B_MARK,	ATAG1_MARK,	HSPI_CS2_B_MARK,
-	GPSIN_B_MARK,	SD2_CD_A_MARK,	VI1_DATA14_MARK,
-	EX_WAIT1_B_MARK,		DREQ0_B_MARK,	HSPI_RX2_B_MARK,
-	REMOCON_A_MARK,	SD2_WP_A_MARK,	VI1_DATA15_MARK,
-	EX_WAIT2_B_MARK,		DACK0_B_MARK,
-	HSPI_TX2_B_MARK,		CAN_CLK_C_MARK,
-
-	PINMUX_MARK_END,
-};
-
-static const u16 pinmux_data[] = {
-	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
-
-	PINMUX_SINGLE(PENC0),
-	PINMUX_SINGLE(PENC1),
-	PINMUX_SINGLE(A1),
-	PINMUX_SINGLE(A2),
-	PINMUX_SINGLE(A3),
-	PINMUX_SINGLE(WE0),
-	PINMUX_SINGLE(AUDIO_CLKA),
-	PINMUX_SINGLE(AUDIO_CLKB),
-	PINMUX_SINGLE(SSI_SCK34),
-	PINMUX_SINGLE(AVS1),
-	PINMUX_SINGLE(AVS2),
-
-	/* IPSR0 */
-	PINMUX_IPSR_GPSR(IP0_1_0,	PRESETOUT),
-	PINMUX_IPSR_GPSR(IP0_1_0,	PWM1),
-
-	PINMUX_IPSR_GPSR(IP0_4_2,	AUDATA0),
-	PINMUX_IPSR_GPSR(IP0_4_2,	ARM_TRACEDATA_0),
-	PINMUX_IPSR_MSEL(IP0_4_2,	GPSCLK_C,	SEL_GPS_C),
-	PINMUX_IPSR_GPSR(IP0_4_2,	USB_OVC0),
-	PINMUX_IPSR_GPSR(IP0_4_2,	TX2_E),
-	PINMUX_IPSR_MSEL(IP0_4_2,	SDA2_B,		SEL_I2C2_B),
-
-	PINMUX_IPSR_GPSR(IP0_7_5,	AUDATA1),
-	PINMUX_IPSR_GPSR(IP0_7_5,	ARM_TRACEDATA_1),
-	PINMUX_IPSR_MSEL(IP0_7_5,	GPSIN_C,	SEL_GPS_C),
-	PINMUX_IPSR_GPSR(IP0_7_5,	USB_OVC1),
-	PINMUX_IPSR_MSEL(IP0_7_5,	RX2_E,		SEL_SCIF2_E),
-	PINMUX_IPSR_MSEL(IP0_7_5,	SCL2_B,		SEL_I2C2_B),
-
-	PINMUX_IPSR_MSEL(IP0_11_8,	SD1_DAT2_A,	SEL_SD1_A),
-	PINMUX_IPSR_GPSR(IP0_11_8,	MMC_D2),
-	PINMUX_IPSR_GPSR(IP0_11_8,	BS),
-	PINMUX_IPSR_GPSR(IP0_11_8,	ATADIR0_A),
-	PINMUX_IPSR_GPSR(IP0_11_8,	SDSELF_A),
-	PINMUX_IPSR_GPSR(IP0_11_8,	PWM4_B),
-
-	PINMUX_IPSR_MSEL(IP0_14_12,	SD1_DAT3_A,	SEL_SD1_A),
-	PINMUX_IPSR_GPSR(IP0_14_12,	MMC_D3),
-	PINMUX_IPSR_GPSR(IP0_14_12,	A0),
-	PINMUX_IPSR_GPSR(IP0_14_12,	ATAG0_A),
-	PINMUX_IPSR_MSEL(IP0_14_12,	REMOCON_B,	SEL_REMOCON_B),
-
-	PINMUX_IPSR_GPSR(IP0_15,	A4),
-	PINMUX_IPSR_GPSR(IP0_16,	A5),
-	PINMUX_IPSR_GPSR(IP0_17,	A6),
-	PINMUX_IPSR_GPSR(IP0_18,	A7),
-	PINMUX_IPSR_GPSR(IP0_19,	A8),
-	PINMUX_IPSR_GPSR(IP0_20,	A9),
-	PINMUX_IPSR_GPSR(IP0_21,	A10),
-	PINMUX_IPSR_GPSR(IP0_22,	A11),
-	PINMUX_IPSR_GPSR(IP0_23,	A12),
-	PINMUX_IPSR_GPSR(IP0_24,	A13),
-	PINMUX_IPSR_GPSR(IP0_25,	A14),
-	PINMUX_IPSR_GPSR(IP0_26,	A15),
-	PINMUX_IPSR_GPSR(IP0_27,	A16),
-	PINMUX_IPSR_GPSR(IP0_28,	A17),
-	PINMUX_IPSR_GPSR(IP0_29,	A18),
-	PINMUX_IPSR_GPSR(IP0_30,	A19),
-
-	/* IPSR1 */
-	PINMUX_IPSR_GPSR(IP1_0,		A20),
-	PINMUX_IPSR_MSEL(IP1_0,		HSPI_CS1_B,	SEL_HSPI1_B),
-
-	PINMUX_IPSR_GPSR(IP1_1,		A21),
-	PINMUX_IPSR_MSEL(IP1_1,		HSPI_CLK1_B,	SEL_HSPI1_B),
-
-	PINMUX_IPSR_GPSR(IP1_4_2,	A22),
-	PINMUX_IPSR_MSEL(IP1_4_2,	HRTS0_B,	SEL_HSCIF0_B),
-	PINMUX_IPSR_MSEL(IP1_4_2,	RX2_B,		SEL_SCIF2_B),
-	PINMUX_IPSR_MSEL(IP1_4_2,	DREQ2_A,	SEL_DREQ2_A),
-
-	PINMUX_IPSR_GPSR(IP1_7_5,	A23),
-	PINMUX_IPSR_GPSR(IP1_7_5,	HTX0_B),
-	PINMUX_IPSR_GPSR(IP1_7_5,	TX2_B),
-	PINMUX_IPSR_GPSR(IP1_7_5,	DACK2_A),
-	PINMUX_IPSR_MSEL(IP1_7_5,	TS_SDEN0_A,	SEL_TSIF0_A),
-
-	PINMUX_IPSR_MSEL(IP1_10_8,	SD1_CD_A,	SEL_SD1_A),
-	PINMUX_IPSR_GPSR(IP1_10_8,	MMC_D6),
-	PINMUX_IPSR_GPSR(IP1_10_8,	A24),
-	PINMUX_IPSR_MSEL(IP1_10_8,	DREQ1_A,	SEL_DREQ1_A),
-	PINMUX_IPSR_MSEL(IP1_10_8,	HRX0_B,		SEL_HSCIF0_B),
-	PINMUX_IPSR_MSEL(IP1_10_8,	TS_SPSYNC0_A,	SEL_TSIF0_A),
-
-	PINMUX_IPSR_MSEL(IP1_14_11,	SD1_WP_A,	SEL_SD1_A),
-	PINMUX_IPSR_GPSR(IP1_14_11,	MMC_D7),
-	PINMUX_IPSR_GPSR(IP1_14_11,	A25),
-	PINMUX_IPSR_GPSR(IP1_14_11,	DACK1_A),
-	PINMUX_IPSR_MSEL(IP1_14_11,	HCTS0_B,	SEL_HSCIF0_B),
-	PINMUX_IPSR_MSEL(IP1_14_11,	RX3_C,		SEL_SCIF3_C),
-	PINMUX_IPSR_MSEL(IP1_14_11,	TS_SDAT0_A,	SEL_TSIF0_A),
-
-	PINMUX_IPSR_NOGP(IP1_16_15,	CLKOUT),
-	PINMUX_IPSR_NOGP(IP1_16_15,	HSPI_TX1_B),
-	PINMUX_IPSR_NOGP(IP1_16_15,	PWM0_B),
-
-	PINMUX_IPSR_NOGP(IP1_17,	CS0),
-	PINMUX_IPSR_NOGM(IP1_17,	HSPI_RX1_B,	SEL_HSPI1_B),
-
-	PINMUX_IPSR_NOGM(IP1_20_18,	SSI_SCK1_B,	SEL_SSI1_B),
-	PINMUX_IPSR_NOGP(IP1_20_18,	ATAG0_B),
-	PINMUX_IPSR_NOGP(IP1_20_18,	CS1_A26),
-	PINMUX_IPSR_NOGM(IP1_20_18,	SDA2_A,		SEL_I2C2_A),
-	PINMUX_IPSR_NOGM(IP1_20_18,	SCK2_B,		SEL_SCIF2_B),
-
-	PINMUX_IPSR_GPSR(IP1_23_21,	MMC_D5),
-	PINMUX_IPSR_GPSR(IP1_23_21,	ATADIR0_B),
-	PINMUX_IPSR_GPSR(IP1_23_21,	RD_WR),
-
-	PINMUX_IPSR_GPSR(IP1_24,	WE1),
-	PINMUX_IPSR_GPSR(IP1_24,	ATAWR0_B),
-
-	PINMUX_IPSR_MSEL(IP1_27_25,	SSI_WS1_B,	SEL_SSI1_B),
-	PINMUX_IPSR_GPSR(IP1_27_25,	EX_CS0),
-	PINMUX_IPSR_MSEL(IP1_27_25,	SCL2_A,		SEL_I2C2_A),
-	PINMUX_IPSR_GPSR(IP1_27_25,	TX3_C),
-	PINMUX_IPSR_MSEL(IP1_27_25,	TS_SCK0_A,	SEL_TSIF0_A),
-
-	PINMUX_IPSR_GPSR(IP1_29_28,	EX_CS1),
-	PINMUX_IPSR_GPSR(IP1_29_28,	MMC_D4),
-
-	/* IPSR2 */
-	PINMUX_IPSR_GPSR(IP2_2_0,	SD1_CLK_A),
-	PINMUX_IPSR_GPSR(IP2_2_0,	MMC_CLK),
-	PINMUX_IPSR_GPSR(IP2_2_0,	ATACS00),
-	PINMUX_IPSR_GPSR(IP2_2_0,	EX_CS2),
-
-	PINMUX_IPSR_MSEL(IP2_5_3,	SD1_CMD_A,	SEL_SD1_A),
-	PINMUX_IPSR_GPSR(IP2_5_3,	MMC_CMD),
-	PINMUX_IPSR_GPSR(IP2_5_3,	ATACS10),
-	PINMUX_IPSR_GPSR(IP2_5_3,	EX_CS3),
-
-	PINMUX_IPSR_MSEL(IP2_8_6,	SD1_DAT0_A,	SEL_SD1_A),
-	PINMUX_IPSR_GPSR(IP2_8_6,	MMC_D0),
-	PINMUX_IPSR_GPSR(IP2_8_6,	ATARD0),
-	PINMUX_IPSR_GPSR(IP2_8_6,	EX_CS4),
-	PINMUX_IPSR_MSEL(IP2_8_6,	EX_WAIT1_A,	SEL_WAIT1_A),
-
-	PINMUX_IPSR_MSEL(IP2_11_9,	SD1_DAT1_A,	SEL_SD1_A),
-	PINMUX_IPSR_GPSR(IP2_11_9,	MMC_D1),
-	PINMUX_IPSR_GPSR(IP2_11_9,	ATAWR0_A),
-	PINMUX_IPSR_GPSR(IP2_11_9,	EX_CS5),
-	PINMUX_IPSR_MSEL(IP2_11_9,	EX_WAIT2_A,	SEL_WAIT2_A),
-
-	PINMUX_IPSR_MSEL(IP2_13_12,	DREQ0_A,	SEL_DREQ0_A),
-	PINMUX_IPSR_MSEL(IP2_13_12,	RX3_A,		SEL_SCIF3_A),
-
-	PINMUX_IPSR_GPSR(IP2_16_14,	DACK0),
-	PINMUX_IPSR_GPSR(IP2_16_14,	TX3_A),
-	PINMUX_IPSR_GPSR(IP2_16_14,	DRACK0),
-
-	PINMUX_IPSR_GPSR(IP2_17,	EX_WAIT0),
-	PINMUX_IPSR_GPSR(IP2_17,	PWM0_C),
-
-	PINMUX_IPSR_NOGP(IP2_18,	D0),
-	PINMUX_IPSR_NOGP(IP2_19,	D1),
-	PINMUX_IPSR_NOGP(IP2_20,	D2),
-	PINMUX_IPSR_NOGP(IP2_21,	D3),
-	PINMUX_IPSR_NOGP(IP2_22,	D4),
-	PINMUX_IPSR_NOGP(IP2_23,	D5),
-	PINMUX_IPSR_NOGP(IP2_24,	D6),
-	PINMUX_IPSR_NOGP(IP2_25,	D7),
-	PINMUX_IPSR_NOGP(IP2_26,	D8),
-	PINMUX_IPSR_NOGP(IP2_27,	D9),
-	PINMUX_IPSR_NOGP(IP2_28,	D10),
-	PINMUX_IPSR_NOGP(IP2_29,	D11),
-
-	PINMUX_IPSR_GPSR(IP2_30,	RD_WR_B),
-	PINMUX_IPSR_GPSR(IP2_30,	IRQ0),
-
-	PINMUX_IPSR_GPSR(IP2_31,	MLB_CLK),
-	PINMUX_IPSR_MSEL(IP2_31,	IRQ1_A,		SEL_IRQ1_A),
-
-	/* IPSR3 */
-	PINMUX_IPSR_GPSR(IP3_1_0,	MLB_SIG),
-	PINMUX_IPSR_MSEL(IP3_1_0,	RX5_B,		SEL_SCIF5_B),
-	PINMUX_IPSR_MSEL(IP3_1_0,	SDA3_A,		SEL_I2C3_A),
-	PINMUX_IPSR_MSEL(IP3_1_0,	IRQ2_A,		SEL_IRQ2_A),
-
-	PINMUX_IPSR_GPSR(IP3_4_2,	MLB_DAT),
-	PINMUX_IPSR_GPSR(IP3_4_2,	TX5_B),
-	PINMUX_IPSR_MSEL(IP3_4_2,	SCL3_A,		SEL_I2C3_A),
-	PINMUX_IPSR_MSEL(IP3_4_2,	IRQ3_A,		SEL_IRQ3_A),
-	PINMUX_IPSR_GPSR(IP3_4_2,	SDSELF_B),
-
-	PINMUX_IPSR_MSEL(IP3_7_5,	SD1_CMD_B,	SEL_SD1_B),
-	PINMUX_IPSR_GPSR(IP3_7_5,	SCIF_CLK),
-	PINMUX_IPSR_GPSR(IP3_7_5,	AUDIO_CLKOUT_B),
-	PINMUX_IPSR_MSEL(IP3_7_5,	CAN_CLK_B,	SEL_CANCLK_B),
-	PINMUX_IPSR_MSEL(IP3_7_5,	SDA3_B,		SEL_I2C3_B),
-
-	PINMUX_IPSR_GPSR(IP3_9_8,	SD1_CLK_B),
-	PINMUX_IPSR_GPSR(IP3_9_8,	HTX0_A),
-	PINMUX_IPSR_GPSR(IP3_9_8,	TX0_A),
-
-	PINMUX_IPSR_MSEL(IP3_12_10,	SD1_DAT0_B,	SEL_SD1_B),
-	PINMUX_IPSR_MSEL(IP3_12_10,	HRX0_A,		SEL_HSCIF0_A),
-	PINMUX_IPSR_MSEL(IP3_12_10,	RX0_A,		SEL_SCIF0_A),
-
-	PINMUX_IPSR_MSEL(IP3_15_13,	SD1_DAT1_B,	SEL_SD1_B),
-	PINMUX_IPSR_MSEL(IP3_15_13,	HSCK0,		SEL_HSCIF0_A),
-	PINMUX_IPSR_GPSR(IP3_15_13,	SCK0),
-	PINMUX_IPSR_MSEL(IP3_15_13,	SCL3_B,		SEL_I2C3_B),
-
-	PINMUX_IPSR_MSEL(IP3_18_16,	SD1_DAT2_B,	SEL_SD1_B),
-	PINMUX_IPSR_MSEL(IP3_18_16,	HCTS0_A,	SEL_HSCIF0_A),
-	PINMUX_IPSR_GPSR(IP3_18_16,	CTS0),
-
-	PINMUX_IPSR_MSEL(IP3_20_19,	SD1_DAT3_B,	SEL_SD1_B),
-	PINMUX_IPSR_MSEL(IP3_20_19,	HRTS0_A,	SEL_HSCIF0_A),
-	PINMUX_IPSR_GPSR(IP3_20_19,	RTS0),
-
-	PINMUX_IPSR_GPSR(IP3_23_21,	SSI_SCK4),
-	PINMUX_IPSR_GPSR(IP3_23_21,	DU0_DR0),
-	PINMUX_IPSR_GPSR(IP3_23_21,	LCDOUT0),
-	PINMUX_IPSR_GPSR(IP3_23_21,	AUDATA2),
-	PINMUX_IPSR_GPSR(IP3_23_21,	ARM_TRACEDATA_2),
-	PINMUX_IPSR_MSEL(IP3_23_21,	SDA3_C,		SEL_I2C3_C),
-	PINMUX_IPSR_GPSR(IP3_23_21,	ADICHS1),
-	PINMUX_IPSR_MSEL(IP3_23_21,	TS_SDEN0_B,	SEL_TSIF0_B),
-
-	PINMUX_IPSR_GPSR(IP3_26_24,	SSI_WS4),
-	PINMUX_IPSR_GPSR(IP3_26_24,	DU0_DR1),
-	PINMUX_IPSR_GPSR(IP3_26_24,	LCDOUT1),
-	PINMUX_IPSR_GPSR(IP3_26_24,	AUDATA3),
-	PINMUX_IPSR_GPSR(IP3_26_24,	ARM_TRACEDATA_3),
-	PINMUX_IPSR_MSEL(IP3_26_24,	SCL3_C,		SEL_I2C3_C),
-	PINMUX_IPSR_GPSR(IP3_26_24,	ADICHS2),
-	PINMUX_IPSR_MSEL(IP3_26_24,	TS_SPSYNC0_B,	SEL_TSIF0_B),
-
-	PINMUX_IPSR_GPSR(IP3_27,	DU0_DR2),
-	PINMUX_IPSR_GPSR(IP3_27,	LCDOUT2),
-
-	PINMUX_IPSR_GPSR(IP3_28,	DU0_DR3),
-	PINMUX_IPSR_GPSR(IP3_28,	LCDOUT3),
-
-	PINMUX_IPSR_GPSR(IP3_29,	DU0_DR4),
-	PINMUX_IPSR_GPSR(IP3_29,	LCDOUT4),
-
-	PINMUX_IPSR_GPSR(IP3_30,	DU0_DR5),
-	PINMUX_IPSR_GPSR(IP3_30,	LCDOUT5),
-
-	PINMUX_IPSR_GPSR(IP3_31,	DU0_DR6),
-	PINMUX_IPSR_GPSR(IP3_31,	LCDOUT6),
-
-	/* IPSR4 */
-	PINMUX_IPSR_GPSR(IP4_0,		DU0_DR7),
-	PINMUX_IPSR_GPSR(IP4_0,		LCDOUT7),
-
-	PINMUX_IPSR_GPSR(IP4_3_1,	DU0_DG0),
-	PINMUX_IPSR_GPSR(IP4_3_1,	LCDOUT8),
-	PINMUX_IPSR_GPSR(IP4_3_1,	AUDATA4),
-	PINMUX_IPSR_GPSR(IP4_3_1,	ARM_TRACEDATA_4),
-	PINMUX_IPSR_GPSR(IP4_3_1,	TX1_D),
-	PINMUX_IPSR_GPSR(IP4_3_1,	CAN0_TX_A),
-	PINMUX_IPSR_GPSR(IP4_3_1,	ADICHS0),
-
-	PINMUX_IPSR_GPSR(IP4_6_4,	DU0_DG1),
-	PINMUX_IPSR_GPSR(IP4_6_4,	LCDOUT9),
-	PINMUX_IPSR_GPSR(IP4_6_4,	AUDATA5),
-	PINMUX_IPSR_GPSR(IP4_6_4,	ARM_TRACEDATA_5),
-	PINMUX_IPSR_MSEL(IP4_6_4,	RX1_D,		SEL_SCIF1_D),
-	PINMUX_IPSR_MSEL(IP4_6_4,	CAN0_RX_A,	SEL_CAN0_A),
-	PINMUX_IPSR_GPSR(IP4_6_4,	ADIDATA),
-
-	PINMUX_IPSR_GPSR(IP4_7,		DU0_DG2),
-	PINMUX_IPSR_GPSR(IP4_7,		LCDOUT10),
-
-	PINMUX_IPSR_GPSR(IP4_8,		DU0_DG3),
-	PINMUX_IPSR_GPSR(IP4_8,		LCDOUT11),
-
-	PINMUX_IPSR_GPSR(IP4_10_9,	DU0_DG4),
-	PINMUX_IPSR_GPSR(IP4_10_9,	LCDOUT12),
-	PINMUX_IPSR_MSEL(IP4_10_9,	RX0_B,		SEL_SCIF0_B),
-
-	PINMUX_IPSR_GPSR(IP4_12_11,	DU0_DG5),
-	PINMUX_IPSR_GPSR(IP4_12_11,	LCDOUT13),
-	PINMUX_IPSR_GPSR(IP4_12_11,	TX0_B),
-
-	PINMUX_IPSR_GPSR(IP4_14_13,	DU0_DG6),
-	PINMUX_IPSR_GPSR(IP4_14_13,	LCDOUT14),
-	PINMUX_IPSR_MSEL(IP4_14_13,	RX4_A,		SEL_SCIF4_A),
-
-	PINMUX_IPSR_GPSR(IP4_16_15,	DU0_DG7),
-	PINMUX_IPSR_GPSR(IP4_16_15,	LCDOUT15),
-	PINMUX_IPSR_GPSR(IP4_16_15,	TX4_A),
-
-	PINMUX_IPSR_MSEL(IP4_20_17,	SSI_SCK2_B,	SEL_SSI2_B),
-	PINMUX_DATA(VI0_R0_B_MARK,	FN_IP4_20_17,	FN_VI0_R0_B,	FN_SEL_VI0_B), /* see sel_vi0 */
-	PINMUX_DATA(VI0_R0_D_MARK,	FN_IP4_20_17,	FN_VI0_R0_B,	FN_SEL_VI0_D), /* see sel_vi0 */
-	PINMUX_IPSR_GPSR(IP4_20_17,	DU0_DB0),
-	PINMUX_IPSR_GPSR(IP4_20_17,	LCDOUT16),
-	PINMUX_IPSR_GPSR(IP4_20_17,	AUDATA6),
-	PINMUX_IPSR_GPSR(IP4_20_17,	ARM_TRACEDATA_6),
-	PINMUX_IPSR_MSEL(IP4_20_17,	GPSCLK_A,	SEL_GPS_A),
-	PINMUX_IPSR_GPSR(IP4_20_17,	PWM0_A),
-	PINMUX_IPSR_GPSR(IP4_20_17,	ADICLK),
-	PINMUX_IPSR_MSEL(IP4_20_17,	TS_SDAT0_B,	SEL_TSIF0_B),
-
-	PINMUX_IPSR_GPSR(IP4_24_21,	AUDIO_CLKC),
-	PINMUX_DATA(VI0_R1_B_MARK,	FN_IP4_24_21,	FN_VI0_R1_B,	FN_SEL_VI0_B), /* see sel_vi0 */
-	PINMUX_DATA(VI0_R1_D_MARK,	FN_IP4_24_21,	FN_VI0_R1_B,	FN_SEL_VI0_D), /* see sel_vi0 */
-	PINMUX_IPSR_GPSR(IP4_24_21,	DU0_DB1),
-	PINMUX_IPSR_GPSR(IP4_24_21,	LCDOUT17),
-	PINMUX_IPSR_GPSR(IP4_24_21,	AUDATA7),
-	PINMUX_IPSR_GPSR(IP4_24_21,	ARM_TRACEDATA_7),
-	PINMUX_IPSR_MSEL(IP4_24_21,	GPSIN_A,	SEL_GPS_A),
-	PINMUX_IPSR_GPSR(IP4_24_21,	ADICS_SAMP),
-	PINMUX_IPSR_MSEL(IP4_24_21,	TS_SCK0_B,	SEL_TSIF0_B),
-
-	PINMUX_DATA(VI0_R2_B_MARK,	FN_IP4_26_25,	FN_VI0_R2_B,	FN_SEL_VI0_B), /* see sel_vi0 */
-	PINMUX_DATA(VI0_R2_D_MARK,	FN_IP4_26_25,	FN_VI0_R2_B,	FN_SEL_VI0_D), /* see sel_vi0 */
-	PINMUX_IPSR_GPSR(IP4_26_25,	DU0_DB2),
-	PINMUX_IPSR_GPSR(IP4_26_25,	LCDOUT18),
-
-	PINMUX_IPSR_MSEL(IP4_28_27,	VI0_R3_B,	SEL_VI0_B),
-	PINMUX_IPSR_GPSR(IP4_28_27,	DU0_DB3),
-	PINMUX_IPSR_GPSR(IP4_28_27,	LCDOUT19),
-
-	PINMUX_DATA(VI0_R4_B_MARK,	FN_IP4_30_29,	FN_VI0_R4_B,	FN_SEL_VI0_B), /* see sel_vi0 */
-	PINMUX_DATA(VI0_R4_D_MARK,	FN_IP4_30_29,	FN_VI0_R4_B,	FN_SEL_VI0_D), /* see sel_vi0 */
-	PINMUX_IPSR_GPSR(IP4_30_29,	DU0_DB4),
-	PINMUX_IPSR_GPSR(IP4_30_29,	LCDOUT20),
-
-	/* IPSR5 */
-	PINMUX_DATA(VI0_R5_B_MARK,	FN_IP5_1_0,	FN_VI0_R5_B,	FN_SEL_VI0_B), /* see sel_vi0 */
-	PINMUX_DATA(VI0_R5_D_MARK,	FN_IP5_1_0,	FN_VI0_R5_B,	FN_SEL_VI0_D), /* see sel_vi0 */
-	PINMUX_IPSR_GPSR(IP5_1_0,	DU0_DB5),
-	PINMUX_IPSR_GPSR(IP5_1_0,	LCDOUT21),
-
-	PINMUX_IPSR_MSEL(IP5_3_2,	VI1_DATA10_B,	SEL_VI1_B),
-	PINMUX_IPSR_GPSR(IP5_3_2,	DU0_DB6),
-	PINMUX_IPSR_GPSR(IP5_3_2,	LCDOUT22),
-
-	PINMUX_IPSR_MSEL(IP5_5_4,	VI1_DATA11_B,	SEL_VI1_B),
-	PINMUX_IPSR_GPSR(IP5_5_4,	DU0_DB7),
-	PINMUX_IPSR_GPSR(IP5_5_4,	LCDOUT23),
-
-	PINMUX_IPSR_GPSR(IP5_6,		DU0_DOTCLKIN),
-	PINMUX_IPSR_GPSR(IP5_6,		QSTVA_QVS),
-
-	PINMUX_IPSR_GPSR(IP5_7,		DU0_DOTCLKO_UT0),
-	PINMUX_IPSR_GPSR(IP5_7,		QCLK),
-
-	PINMUX_IPSR_GPSR(IP5_9_8,	DU0_DOTCLKO_UT1),
-	PINMUX_IPSR_GPSR(IP5_9_8,	QSTVB_QVE),
-	PINMUX_IPSR_GPSR(IP5_9_8,	AUDIO_CLKOUT_A),
-	PINMUX_IPSR_MSEL(IP5_9_8,	REMOCON_C,	SEL_REMOCON_C),
-
-	PINMUX_IPSR_MSEL(IP5_11_10,	SSI_WS2_B,	SEL_SSI2_B),
-	PINMUX_IPSR_GPSR(IP5_11_10,	DU0_EXHSYNC_DU0_HSYNC),
-	PINMUX_IPSR_GPSR(IP5_11_10,	QSTH_QHS),
-
-	PINMUX_IPSR_GPSR(IP5_12,	DU0_EXVSYNC_DU0_VSYNC),
-	PINMUX_IPSR_GPSR(IP5_12,	QSTB_QHE),
-
-	PINMUX_IPSR_GPSR(IP5_14_13,	DU0_EXODDF_DU0_ODDF_DISP_CDE),
-	PINMUX_IPSR_GPSR(IP5_14_13,	QCPV_QDE),
-	PINMUX_IPSR_MSEL(IP5_14_13,	FMCLK_D,	SEL_FM_D),
-
-	PINMUX_IPSR_MSEL(IP5_17_15,	SSI_SCK1_A,	SEL_SSI1_A),
-	PINMUX_IPSR_GPSR(IP5_17_15,	DU0_DISP),
-	PINMUX_IPSR_GPSR(IP5_17_15,	QPOLA),
-	PINMUX_IPSR_GPSR(IP5_17_15,	AUDCK),
-	PINMUX_IPSR_GPSR(IP5_17_15,	ARM_TRACECLK),
-	PINMUX_IPSR_GPSR(IP5_17_15,	BPFCLK_D),
-
-	PINMUX_IPSR_MSEL(IP5_20_18,	SSI_WS1_A,	SEL_SSI1_A),
-	PINMUX_IPSR_GPSR(IP5_20_18,	DU0_CDE),
-	PINMUX_IPSR_GPSR(IP5_20_18,	QPOLB),
-	PINMUX_IPSR_GPSR(IP5_20_18,	AUDSYNC),
-	PINMUX_IPSR_GPSR(IP5_20_18,	ARM_TRACECTL),
-	PINMUX_IPSR_MSEL(IP5_20_18,	FMIN_D,		SEL_FM_D),
-
-	PINMUX_IPSR_MSEL(IP5_22_21,	SD1_CD_B,	SEL_SD1_B),
-	PINMUX_IPSR_GPSR(IP5_22_21,	SSI_SCK78),
-	PINMUX_IPSR_MSEL(IP5_22_21,	HSPI_RX0_B,	SEL_HSPI0_B),
-	PINMUX_IPSR_GPSR(IP5_22_21,	TX1_B),
-
-	PINMUX_IPSR_MSEL(IP5_25_23,	SD1_WP_B,	SEL_SD1_B),
-	PINMUX_IPSR_GPSR(IP5_25_23,	SSI_WS78),
-	PINMUX_IPSR_MSEL(IP5_25_23,	HSPI_CLK0_B,	SEL_HSPI0_B),
-	PINMUX_IPSR_MSEL(IP5_25_23,	RX1_B,		SEL_SCIF1_B),
-	PINMUX_IPSR_MSEL(IP5_25_23,	CAN_CLK_D,	SEL_CANCLK_D),
-
-	PINMUX_IPSR_GPSR(IP5_28_26,	SSI_SDATA8),
-	PINMUX_IPSR_MSEL(IP5_28_26,	SSI_SCK2_A,	SEL_SSI2_A),
-	PINMUX_IPSR_MSEL(IP5_28_26,	HSPI_CS0_B,	SEL_HSPI0_B),
-	PINMUX_IPSR_GPSR(IP5_28_26,	TX2_A),
-	PINMUX_IPSR_GPSR(IP5_28_26,	CAN0_TX_B),
-
-	PINMUX_IPSR_GPSR(IP5_30_29,	SSI_SDATA7),
-	PINMUX_IPSR_GPSR(IP5_30_29,	HSPI_TX0_B),
-	PINMUX_IPSR_MSEL(IP5_30_29,	RX2_A,		SEL_SCIF2_A),
-	PINMUX_IPSR_MSEL(IP5_30_29,	CAN0_RX_B,	SEL_CAN0_B),
-
-	/* IPSR6 */
-	PINMUX_IPSR_GPSR(IP6_1_0,	SSI_SCK6),
-	PINMUX_IPSR_MSEL(IP6_1_0,	HSPI_RX2_A,	SEL_HSPI2_A),
-	PINMUX_IPSR_MSEL(IP6_1_0,	FMCLK_B,	SEL_FM_B),
-	PINMUX_IPSR_GPSR(IP6_1_0,	CAN1_TX_B),
-
-	PINMUX_IPSR_GPSR(IP6_4_2,	SSI_WS6),
-	PINMUX_IPSR_MSEL(IP6_4_2,	HSPI_CLK2_A,	SEL_HSPI2_A),
-	PINMUX_IPSR_GPSR(IP6_4_2,	BPFCLK_B),
-	PINMUX_IPSR_MSEL(IP6_4_2,	CAN1_RX_B,	SEL_CAN1_B),
-
-	PINMUX_IPSR_GPSR(IP6_6_5,	SSI_SDATA6),
-	PINMUX_IPSR_GPSR(IP6_6_5,	HSPI_TX2_A),
-	PINMUX_IPSR_MSEL(IP6_6_5,	FMIN_B,		SEL_FM_B),
-
-	PINMUX_IPSR_GPSR(IP6_7,		SSI_SCK5),
-	PINMUX_IPSR_MSEL(IP6_7,		RX4_C,		SEL_SCIF4_C),
-
-	PINMUX_IPSR_GPSR(IP6_8,		SSI_WS5),
-	PINMUX_IPSR_GPSR(IP6_8,		TX4_C),
-
-	PINMUX_IPSR_GPSR(IP6_9,		SSI_SDATA5),
-	PINMUX_IPSR_MSEL(IP6_9,		RX0_D,		SEL_SCIF0_D),
-
-	PINMUX_IPSR_GPSR(IP6_10,	SSI_WS34),
-	PINMUX_IPSR_GPSR(IP6_10,	ARM_TRACEDATA_8),
-
-	PINMUX_IPSR_GPSR(IP6_12_11,	SSI_SDATA4),
-	PINMUX_IPSR_MSEL(IP6_12_11,	SSI_WS2_A,	SEL_SSI2_A),
-	PINMUX_IPSR_GPSR(IP6_12_11,	ARM_TRACEDATA_9),
-
-	PINMUX_IPSR_GPSR(IP6_13,	SSI_SDATA3),
-	PINMUX_IPSR_GPSR(IP6_13,	ARM_TRACEDATA_10),
-
-	PINMUX_IPSR_GPSR(IP6_15_14,	SSI_SCK012),
-	PINMUX_IPSR_GPSR(IP6_15_14,	ARM_TRACEDATA_11),
-	PINMUX_IPSR_GPSR(IP6_15_14,	TX0_D),
-
-	PINMUX_IPSR_GPSR(IP6_16,	SSI_WS012),
-	PINMUX_IPSR_GPSR(IP6_16,	ARM_TRACEDATA_12),
-
-	PINMUX_IPSR_GPSR(IP6_18_17,	SSI_SDATA2),
-	PINMUX_IPSR_MSEL(IP6_18_17,	HSPI_CS2_A,	SEL_HSPI2_A),
-	PINMUX_IPSR_GPSR(IP6_18_17,	ARM_TRACEDATA_13),
-	PINMUX_IPSR_MSEL(IP6_18_17,	SDA1_A,		SEL_I2C1_A),
-
-	PINMUX_IPSR_GPSR(IP6_20_19,	SSI_SDATA1),
-	PINMUX_IPSR_GPSR(IP6_20_19,	ARM_TRACEDATA_14),
-	PINMUX_IPSR_MSEL(IP6_20_19,	SCL1_A,		SEL_I2C1_A),
-	PINMUX_IPSR_MSEL(IP6_20_19,	SCK2_A,		SEL_SCIF2_A),
-
-	PINMUX_IPSR_GPSR(IP6_21,	SSI_SDATA0),
-	PINMUX_IPSR_GPSR(IP6_21,	ARM_TRACEDATA_15),
-
-	PINMUX_IPSR_GPSR(IP6_23_22,	SD0_CLK),
-	PINMUX_IPSR_GPSR(IP6_23_22,	SUB_TDO),
-
-	PINMUX_IPSR_GPSR(IP6_25_24,	SD0_CMD),
-	PINMUX_IPSR_GPSR(IP6_25_24,	SUB_TRST),
-
-	PINMUX_IPSR_GPSR(IP6_27_26,	SD0_DAT0),
-	PINMUX_IPSR_GPSR(IP6_27_26,	SUB_TMS),
-
-	PINMUX_IPSR_GPSR(IP6_29_28,	SD0_DAT1),
-	PINMUX_IPSR_GPSR(IP6_29_28,	SUB_TCK),
-
-	PINMUX_IPSR_GPSR(IP6_31_30,	SD0_DAT2),
-	PINMUX_IPSR_GPSR(IP6_31_30,	SUB_TDI),
-
-	/* IPSR7 */
-	PINMUX_IPSR_GPSR(IP7_1_0,	SD0_DAT3),
-	PINMUX_IPSR_MSEL(IP7_1_0,	IRQ1_B,		SEL_IRQ1_B),
-
-	PINMUX_IPSR_GPSR(IP7_3_2,	SD0_CD),
-	PINMUX_IPSR_GPSR(IP7_3_2,	TX5_A),
-
-	PINMUX_IPSR_GPSR(IP7_5_4,	SD0_WP),
-	PINMUX_IPSR_MSEL(IP7_5_4,	RX5_A,		SEL_SCIF5_A),
-
-	PINMUX_IPSR_GPSR(IP7_8_6,	VI1_CLKENB),
-	PINMUX_IPSR_MSEL(IP7_8_6,	HSPI_CLK0_A,	SEL_HSPI0_A),
-	PINMUX_IPSR_GPSR(IP7_8_6,	HTX1_A),
-	PINMUX_IPSR_MSEL(IP7_8_6,	RTS1_C,		SEL_SCIF1_C),
-
-	PINMUX_IPSR_GPSR(IP7_11_9,	VI1_FIELD),
-	PINMUX_IPSR_MSEL(IP7_11_9,	HSPI_CS0_A,	SEL_HSPI0_A),
-	PINMUX_IPSR_MSEL(IP7_11_9,	HRX1_A,		SEL_HSCIF1_A),
-	PINMUX_IPSR_MSEL(IP7_11_9,	SCK1_C,		SEL_SCIF1_C),
-
-	PINMUX_IPSR_GPSR(IP7_14_12,	VI1_HSYNC),
-	PINMUX_IPSR_MSEL(IP7_14_12,	HSPI_RX0_A,	SEL_HSPI0_A),
-	PINMUX_IPSR_MSEL(IP7_14_12,	HRTS1_A,	SEL_HSCIF1_A),
-	PINMUX_IPSR_MSEL(IP7_14_12,	FMCLK_A,	SEL_FM_A),
-	PINMUX_IPSR_MSEL(IP7_14_12,	RX1_C,		SEL_SCIF1_C),
-
-	PINMUX_IPSR_GPSR(IP7_17_15,	VI1_VSYNC),
-	PINMUX_IPSR_GPSR(IP7_17_15,	HSPI_TX0),
-	PINMUX_IPSR_MSEL(IP7_17_15,	HCTS1_A,	SEL_HSCIF1_A),
-	PINMUX_IPSR_GPSR(IP7_17_15,	BPFCLK_A),
-	PINMUX_IPSR_GPSR(IP7_17_15,	TX1_C),
-
-	PINMUX_IPSR_GPSR(IP7_20_18,	TCLK0),
-	PINMUX_IPSR_MSEL(IP7_20_18,	HSCK1_A,	SEL_HSCIF1_A),
-	PINMUX_IPSR_MSEL(IP7_20_18,	FMIN_A,		SEL_FM_A),
-	PINMUX_IPSR_MSEL(IP7_20_18,	IRQ2_C,		SEL_IRQ2_C),
-	PINMUX_IPSR_MSEL(IP7_20_18,	CTS1_C,		SEL_SCIF1_C),
-	PINMUX_IPSR_GPSR(IP7_20_18,	SPEEDIN),
-
-	PINMUX_IPSR_GPSR(IP7_21,	VI0_CLK),
-	PINMUX_IPSR_MSEL(IP7_21,	CAN_CLK_A,	SEL_CANCLK_A),
-
-	PINMUX_IPSR_GPSR(IP7_24_22,	VI0_CLKENB),
-	PINMUX_IPSR_MSEL(IP7_24_22,	SD2_DAT2_B,	SEL_SD2_B),
-	PINMUX_IPSR_GPSR(IP7_24_22,	VI1_DATA0),
-	PINMUX_IPSR_GPSR(IP7_24_22,	DU1_DG6),
-	PINMUX_IPSR_MSEL(IP7_24_22,	HSPI_RX1_A,	SEL_HSPI1_A),
-	PINMUX_IPSR_MSEL(IP7_24_22,	RX4_B,		SEL_SCIF4_B),
-
-	PINMUX_IPSR_GPSR(IP7_28_25,	VI0_FIELD),
-	PINMUX_IPSR_MSEL(IP7_28_25,	SD2_DAT3_B,	SEL_SD2_B),
-	PINMUX_DATA(VI0_R3_C_MARK,	FN_IP7_28_25,	FN_VI0_R3_C,	FN_SEL_VI0_C), /* see sel_vi0 */
-	PINMUX_DATA(VI0_R3_D_MARK,	FN_IP7_28_25,	FN_VI0_R3_C,	FN_SEL_VI0_D), /* see sel_vi0 */
-	PINMUX_IPSR_GPSR(IP7_28_25,	VI1_DATA1),
-	PINMUX_IPSR_GPSR(IP7_28_25,	DU1_DG7),
-	PINMUX_IPSR_MSEL(IP7_28_25,	HSPI_CLK1_A,	SEL_HSPI1_A),
-	PINMUX_IPSR_GPSR(IP7_28_25,	TX4_B),
-
-	PINMUX_IPSR_GPSR(IP7_31_29,	VI0_HSYNC),
-	PINMUX_IPSR_MSEL(IP7_31_29,	SD2_CD_B,	SEL_SD2_B),
-	PINMUX_IPSR_GPSR(IP7_31_29,	VI1_DATA2),
-	PINMUX_IPSR_GPSR(IP7_31_29,	DU1_DR2),
-	PINMUX_IPSR_MSEL(IP7_31_29,	HSPI_CS1_A,	SEL_HSPI1_A),
-	PINMUX_IPSR_MSEL(IP7_31_29,	RX3_B,		SEL_SCIF3_B),
-
-	/* IPSR8 */
-	PINMUX_IPSR_GPSR(IP8_2_0,	VI0_VSYNC),
-	PINMUX_IPSR_MSEL(IP8_2_0,	SD2_WP_B,	SEL_SD2_B),
-	PINMUX_IPSR_GPSR(IP8_2_0,	VI1_DATA3),
-	PINMUX_IPSR_GPSR(IP8_2_0,	DU1_DR3),
-	PINMUX_IPSR_GPSR(IP8_2_0,	HSPI_TX1_A),
-	PINMUX_IPSR_GPSR(IP8_2_0,	TX3_B),
-
-	PINMUX_IPSR_GPSR(IP8_5_3,	VI0_DATA0_VI0_B0),
-	PINMUX_IPSR_GPSR(IP8_5_3,	DU1_DG2),
-	PINMUX_IPSR_MSEL(IP8_5_3,	IRQ2_B,		SEL_IRQ2_B),
-	PINMUX_IPSR_MSEL(IP8_5_3,	RX3_D,		SEL_SCIF3_D),
-
-	PINMUX_IPSR_GPSR(IP8_8_6,	VI0_DATA1_VI0_B1),
-	PINMUX_IPSR_GPSR(IP8_8_6,	DU1_DG3),
-	PINMUX_IPSR_MSEL(IP8_8_6,	IRQ3_B,		SEL_IRQ3_B),
-	PINMUX_IPSR_GPSR(IP8_8_6,	TX3_D),
-
-	PINMUX_IPSR_GPSR(IP8_10_9,	VI0_DATA2_VI0_B2),
-	PINMUX_IPSR_GPSR(IP8_10_9,	DU1_DG4),
-	PINMUX_IPSR_MSEL(IP8_10_9,	RX0_C,		SEL_SCIF0_C),
-
-	PINMUX_IPSR_GPSR(IP8_13_11,	VI0_DATA3_VI0_B3),
-	PINMUX_IPSR_GPSR(IP8_13_11,	DU1_DG5),
-	PINMUX_IPSR_GPSR(IP8_13_11,	TX1_A),
-	PINMUX_IPSR_GPSR(IP8_13_11,	TX0_C),
-
-	PINMUX_IPSR_GPSR(IP8_15_14,	VI0_DATA4_VI0_B4),
-	PINMUX_IPSR_GPSR(IP8_15_14,	DU1_DB2),
-	PINMUX_IPSR_MSEL(IP8_15_14,	RX1_A,		SEL_SCIF1_A),
-
-	PINMUX_IPSR_GPSR(IP8_18_16,	VI0_DATA5_VI0_B5),
-	PINMUX_IPSR_GPSR(IP8_18_16,	DU1_DB3),
-	PINMUX_IPSR_MSEL(IP8_18_16,	SCK1_A,		SEL_SCIF1_A),
-	PINMUX_IPSR_GPSR(IP8_18_16,	PWM4),
-	PINMUX_IPSR_MSEL(IP8_18_16,	HSCK1_B,	SEL_HSCIF1_B),
-
-	PINMUX_IPSR_GPSR(IP8_21_19,	VI0_DATA6_VI0_G0),
-	PINMUX_IPSR_GPSR(IP8_21_19,	DU1_DB4),
-	PINMUX_IPSR_MSEL(IP8_21_19,	CTS1_A,		SEL_SCIF1_A),
-	PINMUX_IPSR_GPSR(IP8_21_19,	PWM5),
-
-	PINMUX_IPSR_GPSR(IP8_23_22,	VI0_DATA7_VI0_G1),
-	PINMUX_IPSR_GPSR(IP8_23_22,	DU1_DB5),
-	PINMUX_IPSR_MSEL(IP8_23_22,	RTS1_A,		SEL_SCIF1_A),
-
-	PINMUX_IPSR_GPSR(IP8_26_24,	VI0_G2),
-	PINMUX_IPSR_GPSR(IP8_26_24,	SD2_CLK_B),
-	PINMUX_IPSR_GPSR(IP8_26_24,	VI1_DATA4),
-	PINMUX_IPSR_GPSR(IP8_26_24,	DU1_DR4),
-	PINMUX_IPSR_GPSR(IP8_26_24,	HTX1_B),
-
-	PINMUX_IPSR_GPSR(IP8_29_27,	VI0_G3),
-	PINMUX_IPSR_MSEL(IP8_29_27,	SD2_CMD_B,	SEL_SD2_B),
-	PINMUX_IPSR_GPSR(IP8_29_27,	VI1_DATA5),
-	PINMUX_IPSR_GPSR(IP8_29_27,	DU1_DR5),
-	PINMUX_IPSR_MSEL(IP8_29_27,	HRX1_B,		SEL_HSCIF1_B),
-
-	/* IPSR9 */
-	PINMUX_IPSR_GPSR(IP9_2_0,	VI0_G4),
-	PINMUX_IPSR_MSEL(IP9_2_0,	SD2_DAT0_B,	SEL_SD2_B),
-	PINMUX_IPSR_GPSR(IP9_2_0,	VI1_DATA6),
-	PINMUX_IPSR_GPSR(IP9_2_0,	DU1_DR6),
-	PINMUX_IPSR_MSEL(IP9_2_0,	HRTS1_B,	SEL_HSCIF1_B),
-
-	PINMUX_IPSR_GPSR(IP9_5_3,	VI0_G5),
-	PINMUX_IPSR_MSEL(IP9_5_3,	SD2_DAT1_B,	SEL_SD2_B),
-	PINMUX_IPSR_GPSR(IP9_5_3,	VI1_DATA7),
-	PINMUX_IPSR_GPSR(IP9_5_3,	DU1_DR7),
-	PINMUX_IPSR_MSEL(IP9_5_3,	HCTS1_B,	SEL_HSCIF1_B),
-
-	PINMUX_DATA(VI0_R0_A_MARK,	FN_IP9_8_6,	FN_VI0_R0_A,	FN_SEL_VI0_A), /* see sel_vi0 */
-	PINMUX_DATA(VI0_R0_C_MARK,	FN_IP9_8_6,	FN_VI0_R0_A,	FN_SEL_VI0_C), /* see sel_vi0 */
-	PINMUX_IPSR_GPSR(IP9_8_6,	VI1_CLK),
-	PINMUX_IPSR_GPSR(IP9_8_6,	ETH_REF_CLK),
-	PINMUX_IPSR_GPSR(IP9_8_6,	DU1_DOTCLKIN),
-
-	PINMUX_DATA(VI0_R1_A_MARK,	FN_IP9_11_9,	FN_VI0_R1_A,	FN_SEL_VI0_A), /* see sel_vi0 */
-	PINMUX_DATA(VI0_R1_C_MARK,	FN_IP9_11_9,	FN_VI0_R1_A,	FN_SEL_VI0_C), /* see sel_vi0 */
-	PINMUX_IPSR_GPSR(IP9_11_9,	VI1_DATA8),
-	PINMUX_IPSR_GPSR(IP9_11_9,	DU1_DB6),
-	PINMUX_IPSR_GPSR(IP9_11_9,	ETH_TXD0),
-	PINMUX_IPSR_GPSR(IP9_11_9,	PWM2),
-	PINMUX_IPSR_GPSR(IP9_11_9,	TCLK1),
-
-	PINMUX_DATA(VI0_R2_A_MARK,	FN_IP9_14_12,	FN_VI0_R2_A,	FN_SEL_VI0_A), /* see sel_vi0 */
-	PINMUX_DATA(VI0_R2_C_MARK,	FN_IP9_14_12,	FN_VI0_R2_A,	FN_SEL_VI0_C), /* see sel_vi0 */
-	PINMUX_IPSR_GPSR(IP9_14_12,	VI1_DATA9),
-	PINMUX_IPSR_GPSR(IP9_14_12,	DU1_DB7),
-	PINMUX_IPSR_GPSR(IP9_14_12,	ETH_TXD1),
-	PINMUX_IPSR_GPSR(IP9_14_12,	PWM3),
-
-	PINMUX_IPSR_MSEL(IP9_17_15,	VI0_R3_A,	SEL_VI0_A),
-	PINMUX_IPSR_GPSR(IP9_17_15,	ETH_CRS_DV),
-	PINMUX_IPSR_GPSR(IP9_17_15,	IECLK),
-	PINMUX_IPSR_MSEL(IP9_17_15,	SCK2_C,		SEL_SCIF2_C),
-
-	PINMUX_DATA(VI0_R4_A_MARK,	FN_IP9_20_18,	FN_VI0_R4_A,	FN_SEL_VI0_A), /* see sel_vi0 */
-	PINMUX_DATA(VI0_R3_C_MARK,	FN_IP9_20_18,	FN_VI0_R4_A,	FN_SEL_VI0_C), /* see sel_vi0 */
-	PINMUX_IPSR_GPSR(IP9_20_18,	ETH_TX_EN),
-	PINMUX_IPSR_GPSR(IP9_20_18,	IETX),
-	PINMUX_IPSR_GPSR(IP9_20_18,	TX2_C),
-
-	PINMUX_DATA(VI0_R5_A_MARK,	FN_IP9_23_21,	FN_VI0_R5_A,	FN_SEL_VI0_A), /* see sel_vi0 */
-	PINMUX_DATA(VI0_R5_C_MARK,	FN_IP9_23_21,	FN_VI0_R5_A,	FN_SEL_VI0_C), /* see sel_vi0 */
-	PINMUX_IPSR_GPSR(IP9_23_21,	ETH_RX_ER),
-	PINMUX_IPSR_MSEL(IP9_23_21,	FMCLK_C,	SEL_FM_C),
-	PINMUX_IPSR_GPSR(IP9_23_21,	IERX),
-	PINMUX_IPSR_MSEL(IP9_23_21,	RX2_C,		SEL_SCIF2_C),
-
-	PINMUX_IPSR_MSEL(IP9_26_24,	VI1_DATA10_A,	SEL_VI1_A),
-	PINMUX_IPSR_GPSR(IP9_26_24,	DU1_DOTCLKOUT),
-	PINMUX_IPSR_GPSR(IP9_26_24,	ETH_RXD0),
-	PINMUX_IPSR_GPSR(IP9_26_24,	BPFCLK_C),
-	PINMUX_IPSR_GPSR(IP9_26_24,	TX2_D),
-	PINMUX_IPSR_MSEL(IP9_26_24,	SDA2_C,		SEL_I2C2_C),
-
-	PINMUX_IPSR_MSEL(IP9_29_27,	VI1_DATA11_A,	SEL_VI1_A),
-	PINMUX_IPSR_GPSR(IP9_29_27,	DU1_EXHSYNC_DU1_HSYNC),
-	PINMUX_IPSR_GPSR(IP9_29_27,	ETH_RXD1),
-	PINMUX_IPSR_MSEL(IP9_29_27,	FMIN_C,		SEL_FM_C),
-	PINMUX_IPSR_MSEL(IP9_29_27,	RX2_D,		SEL_SCIF2_D),
-	PINMUX_IPSR_MSEL(IP9_29_27,	SCL2_C,		SEL_I2C2_C),
-
-	/* IPSR10 */
-	PINMUX_IPSR_GPSR(IP10_2_0,	SD2_CLK_A),
-	PINMUX_IPSR_GPSR(IP10_2_0,	DU1_EXVSYNC_DU1_VSYNC),
-	PINMUX_IPSR_GPSR(IP10_2_0,	ATARD1),
-	PINMUX_IPSR_GPSR(IP10_2_0,	ETH_MDC),
-	PINMUX_IPSR_MSEL(IP10_2_0,	SDA1_B,		SEL_I2C1_B),
-
-	PINMUX_IPSR_MSEL(IP10_5_3,	SD2_CMD_A,	SEL_SD2_A),
-	PINMUX_IPSR_GPSR(IP10_5_3,	DU1_EXODDF_DU1_ODDF_DISP_CDE),
-	PINMUX_IPSR_GPSR(IP10_5_3,	ATAWR1),
-	PINMUX_IPSR_GPSR(IP10_5_3,	ETH_MDIO),
-	PINMUX_IPSR_MSEL(IP10_5_3,	SCL1_B,		SEL_I2C1_B),
-
-	PINMUX_IPSR_MSEL(IP10_8_6,	SD2_DAT0_A,	SEL_SD2_A),
-	PINMUX_IPSR_GPSR(IP10_8_6,	DU1_DISP),
-	PINMUX_IPSR_GPSR(IP10_8_6,	ATACS01),
-	PINMUX_IPSR_MSEL(IP10_8_6,	DREQ1_B,	SEL_DREQ1_B),
-	PINMUX_IPSR_GPSR(IP10_8_6,	ETH_LINK),
-	PINMUX_IPSR_MSEL(IP10_8_6,	CAN1_RX_A,	SEL_CAN1_A),
-
-	PINMUX_IPSR_MSEL(IP10_12_9,	SD2_DAT1_A,	SEL_SD2_A),
-	PINMUX_IPSR_GPSR(IP10_12_9,	DU1_CDE),
-	PINMUX_IPSR_GPSR(IP10_12_9,	ATACS11),
-	PINMUX_IPSR_GPSR(IP10_12_9,	DACK1_B),
-	PINMUX_IPSR_GPSR(IP10_12_9,	ETH_MAGIC),
-	PINMUX_IPSR_GPSR(IP10_12_9,	CAN1_TX_A),
-	PINMUX_IPSR_GPSR(IP10_12_9,	PWM6),
-
-	PINMUX_IPSR_MSEL(IP10_15_13,	SD2_DAT2_A,	SEL_SD2_A),
-	PINMUX_IPSR_GPSR(IP10_15_13,	VI1_DATA12),
-	PINMUX_IPSR_MSEL(IP10_15_13,	DREQ2_B,	SEL_DREQ2_B),
-	PINMUX_IPSR_GPSR(IP10_15_13,	ATADIR1),
-	PINMUX_IPSR_MSEL(IP10_15_13,	HSPI_CLK2_B,	SEL_HSPI2_B),
-	PINMUX_IPSR_MSEL(IP10_15_13,	GPSCLK_B,	SEL_GPS_B),
-
-	PINMUX_IPSR_MSEL(IP10_18_16,	SD2_DAT3_A,	SEL_SD2_A),
-	PINMUX_IPSR_GPSR(IP10_18_16,	VI1_DATA13),
-	PINMUX_IPSR_GPSR(IP10_18_16,	DACK2_B),
-	PINMUX_IPSR_GPSR(IP10_18_16,	ATAG1),
-	PINMUX_IPSR_MSEL(IP10_18_16,	HSPI_CS2_B,	SEL_HSPI2_B),
-	PINMUX_IPSR_MSEL(IP10_18_16,	GPSIN_B,	SEL_GPS_B),
-
-	PINMUX_IPSR_MSEL(IP10_21_19,	SD2_CD_A,	SEL_SD2_A),
-	PINMUX_IPSR_GPSR(IP10_21_19,	VI1_DATA14),
-	PINMUX_IPSR_MSEL(IP10_21_19,	EX_WAIT1_B,	SEL_WAIT1_B),
-	PINMUX_IPSR_MSEL(IP10_21_19,	DREQ0_B,	SEL_DREQ0_B),
-	PINMUX_IPSR_MSEL(IP10_21_19,	HSPI_RX2_B,	SEL_HSPI2_B),
-	PINMUX_IPSR_MSEL(IP10_21_19,	REMOCON_A,	SEL_REMOCON_A),
-
-	PINMUX_IPSR_MSEL(IP10_24_22,	SD2_WP_A,	SEL_SD2_A),
-	PINMUX_IPSR_GPSR(IP10_24_22,	VI1_DATA15),
-	PINMUX_IPSR_MSEL(IP10_24_22,	EX_WAIT2_B,	SEL_WAIT2_B),
-	PINMUX_IPSR_GPSR(IP10_24_22,	DACK0_B),
-	PINMUX_IPSR_GPSR(IP10_24_22,	HSPI_TX2_B),
-	PINMUX_IPSR_MSEL(IP10_24_22,	CAN_CLK_C,	SEL_CANCLK_C),
-};
-
-/*
- * Pins not associated with a GPIO port.
- */
-enum {
-	GP_ASSIGN_LAST(),
-	NOGP_ALL(),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	PINMUX_GPIO_GP_ALL(),
-	PINMUX_NOGP_ALL(),
-};
-
-/* - macro */
-#define SH_PFC_PINS(name, args...) \
-	static const unsigned int name ##_pins[] = { args }
-#define SH_PFC_MUX1(name, arg1)					\
-	static const unsigned int name ##_mux[]  = { arg1##_MARK }
-#define SH_PFC_MUX2(name, arg1, arg2)					\
-	static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, }
-#define SH_PFC_MUX3(name, arg1, arg2, arg3)					\
-	static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK,	\
-						     arg3##_MARK }
-#define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4)			\
-	static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, \
-						     arg3##_MARK, arg4##_MARK }
-#define SH_PFC_MUX8(name, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) \
-	static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, \
-						     arg3##_MARK, arg4##_MARK, \
-						     arg5##_MARK, arg6##_MARK, \
-						     arg7##_MARK, arg8##_MARK, }
-
-/* - AUDIO macro -------------------------------------------------------------*/
-#define AUDIO_PFC_PIN(name, pin)	SH_PFC_PINS(name, pin)
-#define AUDIO_PFC_DAT(name, pin)	SH_PFC_MUX1(name, pin)
-
-/* - AUDIO clock -------------------------------------------------------------*/
-AUDIO_PFC_PIN(audio_clk_a,	RCAR_GP_PIN(2, 22));
-AUDIO_PFC_DAT(audio_clk_a,	AUDIO_CLKA);
-AUDIO_PFC_PIN(audio_clk_b,	RCAR_GP_PIN(2, 23));
-AUDIO_PFC_DAT(audio_clk_b,	AUDIO_CLKB);
-AUDIO_PFC_PIN(audio_clk_c,	RCAR_GP_PIN(2, 7));
-AUDIO_PFC_DAT(audio_clk_c,	AUDIO_CLKC);
-AUDIO_PFC_PIN(audio_clkout_a,	RCAR_GP_PIN(2, 16));
-AUDIO_PFC_DAT(audio_clkout_a,	AUDIO_CLKOUT_A);
-AUDIO_PFC_PIN(audio_clkout_b,	RCAR_GP_PIN(1, 16));
-AUDIO_PFC_DAT(audio_clkout_b,	AUDIO_CLKOUT_B);
-
-/* - CAN macro --------_----------------------------------------------------- */
-#define CAN_PFC_PINS(name, args...)		SH_PFC_PINS(name, args)
-#define CAN_PFC_DATA(name, tx, rx)		SH_PFC_MUX2(name, tx, rx)
-#define CAN_PFC_CLK(name, clk)			SH_PFC_MUX1(name, clk)
-
-/* - CAN0 ------------------------------------------------------------------- */
-CAN_PFC_PINS(can0_data_a,	RCAR_GP_PIN(1, 30),	RCAR_GP_PIN(1, 31));
-CAN_PFC_DATA(can0_data_a,	CAN0_TX_A,		CAN0_RX_A);
-CAN_PFC_PINS(can0_data_b,	RCAR_GP_PIN(2, 26),	RCAR_GP_PIN(2, 27));
-CAN_PFC_DATA(can0_data_b,	CAN0_TX_B,		CAN0_RX_B);
-
-/* - CAN1 ------------------------------------------------------------------- */
-CAN_PFC_PINS(can1_data_a,	RCAR_GP_PIN(4, 20),	RCAR_GP_PIN(4, 19));
-CAN_PFC_DATA(can1_data_a,	CAN1_TX_A,		CAN1_RX_A);
-CAN_PFC_PINS(can1_data_b,	RCAR_GP_PIN(2, 28),	RCAR_GP_PIN(2, 29));
-CAN_PFC_DATA(can1_data_b,	CAN1_TX_B,		CAN1_RX_B);
-
-/* - CAN_CLK  --------------------------------------------------------------- */
-CAN_PFC_PINS(can_clk_a,		RCAR_GP_PIN(3, 24));
-CAN_PFC_CLK(can_clk_a,		CAN_CLK_A);
-CAN_PFC_PINS(can_clk_b,		RCAR_GP_PIN(1, 16));
-CAN_PFC_CLK(can_clk_b,		CAN_CLK_B);
-CAN_PFC_PINS(can_clk_c,		RCAR_GP_PIN(4, 24));
-CAN_PFC_CLK(can_clk_c,		CAN_CLK_C);
-CAN_PFC_PINS(can_clk_d,		RCAR_GP_PIN(2, 25));
-CAN_PFC_CLK(can_clk_d,		CAN_CLK_D);
-
-/* - Ether ------------------------------------------------------------------ */
-SH_PFC_PINS(ether_rmii,		RCAR_GP_PIN(4, 10),	RCAR_GP_PIN(4, 11),
-				RCAR_GP_PIN(4, 13),	RCAR_GP_PIN(4, 9),
-				RCAR_GP_PIN(4, 15),	RCAR_GP_PIN(4, 16),
-				RCAR_GP_PIN(4, 12),	RCAR_GP_PIN(4, 14),
-				RCAR_GP_PIN(4, 18),	RCAR_GP_PIN(4, 17));
-static const unsigned int ether_rmii_mux[] = {
-	ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK,  ETH_REF_CLK_MARK,
-	ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
-	ETH_MDIO_MARK, ETH_MDC_MARK,
-};
-SH_PFC_PINS(ether_link,		RCAR_GP_PIN(4, 19));
-SH_PFC_MUX1(ether_link,		ETH_LINK);
-SH_PFC_PINS(ether_magic,	RCAR_GP_PIN(4, 20));
-SH_PFC_MUX1(ether_magic,	ETH_MAGIC);
-
-/* - SCIF macro ------------------------------------------------------------- */
-#define SCIF_PFC_PIN(name, args...)	SH_PFC_PINS(name, args)
-#define SCIF_PFC_DAT(name, tx, rx)	SH_PFC_MUX2(name, tx, rx)
-#define SCIF_PFC_CTR(name, cts, rts)	SH_PFC_MUX2(name, cts, rts)
-#define SCIF_PFC_CLK(name, sck)		SH_PFC_MUX1(name, sck)
-
-/* - HSCIF0 ----------------------------------------------------------------- */
-SCIF_PFC_PIN(hscif0_data_a,	RCAR_GP_PIN(1, 17),	RCAR_GP_PIN(1, 18));
-SCIF_PFC_DAT(hscif0_data_a,	HTX0_A,			HRX0_A);
-SCIF_PFC_PIN(hscif0_data_b,	RCAR_GP_PIN(0, 29),	RCAR_GP_PIN(0, 30));
-SCIF_PFC_DAT(hscif0_data_b,	HTX0_B,			HRX0_B);
-SCIF_PFC_PIN(hscif0_ctrl_a,	RCAR_GP_PIN(1, 20),	RCAR_GP_PIN(1, 21));
-SCIF_PFC_CTR(hscif0_ctrl_a,	HCTS0_A,		HRTS0_A);
-SCIF_PFC_PIN(hscif0_ctrl_b,	RCAR_GP_PIN(0, 31),	RCAR_GP_PIN(0, 28));
-SCIF_PFC_CTR(hscif0_ctrl_b,	HCTS0_B,		HRTS0_B);
-SCIF_PFC_PIN(hscif0_clk,	RCAR_GP_PIN(1, 19));
-SCIF_PFC_CLK(hscif0_clk,	HSCK0);
-
-/* - HSCIF1 ----------------------------------------------------------------- */
-SCIF_PFC_PIN(hscif1_data_a,	RCAR_GP_PIN(3, 19),	RCAR_GP_PIN(3, 20));
-SCIF_PFC_DAT(hscif1_data_a,	HTX1_A,			HRX1_A);
-SCIF_PFC_PIN(hscif1_data_b,	RCAR_GP_PIN(4, 5),	RCAR_GP_PIN(4, 6));
-SCIF_PFC_DAT(hscif1_data_b,	HTX1_B,			HRX1_B);
-SCIF_PFC_PIN(hscif1_ctrl_a,	RCAR_GP_PIN(3, 22),	RCAR_GP_PIN(3, 21));
-SCIF_PFC_CTR(hscif1_ctrl_a,	HCTS1_A,		HRTS1_A);
-SCIF_PFC_PIN(hscif1_ctrl_b,	RCAR_GP_PIN(4, 8),	RCAR_GP_PIN(4, 7));
-SCIF_PFC_CTR(hscif1_ctrl_b,	HCTS1_B,		HRTS1_B);
-SCIF_PFC_PIN(hscif1_clk_a,	RCAR_GP_PIN(3, 23));
-SCIF_PFC_CLK(hscif1_clk_a,	HSCK1_A);
-SCIF_PFC_PIN(hscif1_clk_b,	RCAR_GP_PIN(4, 2));
-SCIF_PFC_CLK(hscif1_clk_b,	HSCK1_B);
-
-/* - HSPI macro --------------------------------------------------------------*/
-#define HSPI_PFC_PIN(name, args...)		SH_PFC_PINS(name, args)
-#define HSPI_PFC_DAT(name, clk, cs, rx, tx)	SH_PFC_MUX4(name, clk, cs, rx, tx)
-
-/* - HSPI0 -------------------------------------------------------------------*/
-HSPI_PFC_PIN(hspi0_a,	RCAR_GP_PIN(3, 19),	RCAR_GP_PIN(3, 20),
-			RCAR_GP_PIN(3, 21),	RCAR_GP_PIN(3, 22));
-HSPI_PFC_DAT(hspi0_a,	HSPI_CLK0_A,		HSPI_CS0_A,
-			HSPI_RX0_A,		HSPI_TX0);
-
-HSPI_PFC_PIN(hspi0_b,	RCAR_GP_PIN(2, 25),	RCAR_GP_PIN(2, 26),
-			RCAR_GP_PIN(2, 24),	RCAR_GP_PIN(2, 27));
-HSPI_PFC_DAT(hspi0_b,	HSPI_CLK0_B,		HSPI_CS0_B,
-			HSPI_RX0_B,		HSPI_TX0_B);
-
-/* - HSPI1 -------------------------------------------------------------------*/
-HSPI_PFC_PIN(hspi1_a,	RCAR_GP_PIN(3, 26),	RCAR_GP_PIN(3, 27),
-			RCAR_GP_PIN(3, 25),	RCAR_GP_PIN(3, 28));
-HSPI_PFC_DAT(hspi1_a,	HSPI_CLK1_A,		HSPI_CS1_A,
-			HSPI_RX1_A,		HSPI_TX1_A);
-
-HSPI_PFC_PIN(hspi1_b,	RCAR_GP_PIN(0, 27),	RCAR_GP_PIN(0, 26),
-			PIN_CS0,		PIN_CLKOUT);
-HSPI_PFC_DAT(hspi1_b,	HSPI_CLK1_B,		HSPI_CS1_B,
-			HSPI_RX1_B,		HSPI_TX1_B);
-
-/* - HSPI2 -------------------------------------------------------------------*/
-HSPI_PFC_PIN(hspi2_a,	RCAR_GP_PIN(2, 29),	RCAR_GP_PIN(3, 8),
-			RCAR_GP_PIN(2, 28),	RCAR_GP_PIN(2, 30));
-HSPI_PFC_DAT(hspi2_a,	HSPI_CLK2_A,		HSPI_CS2_A,
-			HSPI_RX2_A,		HSPI_TX2_A);
-
-HSPI_PFC_PIN(hspi2_b,	RCAR_GP_PIN(4, 21),	RCAR_GP_PIN(4, 22),
-			RCAR_GP_PIN(4, 23),	RCAR_GP_PIN(4, 24));
-HSPI_PFC_DAT(hspi2_b,	HSPI_CLK2_B,		HSPI_CS2_B,
-			HSPI_RX2_B,		HSPI_TX2_B);
-
-/* - I2C macro ------------------------------------------------------------- */
-#define I2C_PFC_PIN(name, args...)	SH_PFC_PINS(name, args)
-#define I2C_PFC_MUX(name, sda, scl)	SH_PFC_MUX2(name, sda, scl)
-
-/* - I2C1 ------------------------------------------------------------------ */
-I2C_PFC_PIN(i2c1_a,	RCAR_GP_PIN(3, 8),	RCAR_GP_PIN(3, 9));
-I2C_PFC_MUX(i2c1_a,	SDA1_A,			SCL1_A);
-I2C_PFC_PIN(i2c1_b,	RCAR_GP_PIN(4, 17),	RCAR_GP_PIN(4, 18));
-I2C_PFC_MUX(i2c1_b,	SDA1_B,			SCL1_B);
-
-/* - I2C2 ------------------------------------------------------------------ */
-I2C_PFC_PIN(i2c2_a,	PIN_CS1_A26,		RCAR_GP_PIN(1, 3));
-I2C_PFC_MUX(i2c2_a,	SDA2_A,			SCL2_A);
-I2C_PFC_PIN(i2c2_b,	RCAR_GP_PIN(0, 3),	RCAR_GP_PIN(0, 4));
-I2C_PFC_MUX(i2c2_b,	SDA2_B,			SCL2_B);
-I2C_PFC_PIN(i2c2_c,	RCAR_GP_PIN(4, 15),	RCAR_GP_PIN(4, 16));
-I2C_PFC_MUX(i2c2_c,	SDA2_C,			SCL2_C);
-
-/* - I2C3 ------------------------------------------------------------------ */
-I2C_PFC_PIN(i2c3_a,	RCAR_GP_PIN(1, 14),	RCAR_GP_PIN(1, 15));
-I2C_PFC_MUX(i2c3_a,	SDA3_A,			SCL3_A);
-I2C_PFC_PIN(i2c3_b,	RCAR_GP_PIN(1, 16),	RCAR_GP_PIN(1, 19));
-I2C_PFC_MUX(i2c3_b,	SDA3_B,			SCL3_B);
-I2C_PFC_PIN(i2c3_c,	RCAR_GP_PIN(1, 22),	RCAR_GP_PIN(1, 23));
-I2C_PFC_MUX(i2c3_c,	SDA3_C,			SCL3_C);
-
-/* - MMC macro -------------------------------------------------------------- */
-#define MMC_PFC_PINS(name, args...)		SH_PFC_PINS(name, args)
-#define MMC_PFC_CTRL(name, clk, cmd)		SH_PFC_MUX2(name, clk, cmd)
-#define MMC_PFC_DAT1(name, d0)			SH_PFC_MUX1(name, d0)
-#define MMC_PFC_DAT4(name, d0, d1, d2, d3)	SH_PFC_MUX4(name, d0, d1, d2, d3)
-#define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7)	\
-			SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
-
-/* - MMC -------------------------------------------------------------------- */
-MMC_PFC_PINS(mmc_ctrl,		RCAR_GP_PIN(1, 5),	RCAR_GP_PIN(1, 6));
-MMC_PFC_CTRL(mmc_ctrl,		MMC_CLK,		MMC_CMD);
-MMC_PFC_PINS(mmc_data1,		RCAR_GP_PIN(1, 7));
-MMC_PFC_DAT1(mmc_data1,		MMC_D0);
-MMC_PFC_PINS(mmc_data4,		RCAR_GP_PIN(1, 7),	RCAR_GP_PIN(1, 8),
-				RCAR_GP_PIN(0, 5),	RCAR_GP_PIN(0, 6));
-MMC_PFC_DAT4(mmc_data4,		MMC_D0,			MMC_D1,
-				MMC_D2,			MMC_D3);
-MMC_PFC_PINS(mmc_data8,		RCAR_GP_PIN(1, 7),	RCAR_GP_PIN(1, 8),
-				RCAR_GP_PIN(0, 5),	RCAR_GP_PIN(0, 6),
-				RCAR_GP_PIN(1, 4),	RCAR_GP_PIN(1, 0),
-				RCAR_GP_PIN(0, 30),	RCAR_GP_PIN(0, 31));
-MMC_PFC_DAT8(mmc_data8,		MMC_D0,			MMC_D1,
-				MMC_D2,			MMC_D3,
-				MMC_D4,			MMC_D5,
-				MMC_D6,			MMC_D7);
-
-/* - SCIF CLOCK ------------------------------------------------------------- */
-SCIF_PFC_PIN(scif_clk,		RCAR_GP_PIN(1, 16));
-SCIF_PFC_CLK(scif_clk,		SCIF_CLK);
-
-/* - SCIF0 ------------------------------------------------------------------ */
-SCIF_PFC_PIN(scif0_data_a,	RCAR_GP_PIN(1, 17),	RCAR_GP_PIN(1, 18));
-SCIF_PFC_DAT(scif0_data_a,	TX0_A,			RX0_A);
-SCIF_PFC_PIN(scif0_data_b,	RCAR_GP_PIN(2, 3),	RCAR_GP_PIN(2, 2));
-SCIF_PFC_DAT(scif0_data_b,	TX0_B,			RX0_B);
-SCIF_PFC_PIN(scif0_data_c,	RCAR_GP_PIN(4, 0),	RCAR_GP_PIN(3, 31));
-SCIF_PFC_DAT(scif0_data_c,	TX0_C,			RX0_C);
-SCIF_PFC_PIN(scif0_data_d,	RCAR_GP_PIN(3, 6),	RCAR_GP_PIN(3, 1));
-SCIF_PFC_DAT(scif0_data_d,	TX0_D,			RX0_D);
-SCIF_PFC_PIN(scif0_ctrl,	RCAR_GP_PIN(1, 20),	RCAR_GP_PIN(1, 21));
-SCIF_PFC_CTR(scif0_ctrl,	CTS0,			RTS0);
-SCIF_PFC_PIN(scif0_clk,		RCAR_GP_PIN(1, 19));
-SCIF_PFC_CLK(scif0_clk,		SCK0);
-
-/* - SCIF1 ------------------------------------------------------------------ */
-SCIF_PFC_PIN(scif1_data_a,	RCAR_GP_PIN(4, 0),	RCAR_GP_PIN(4, 1));
-SCIF_PFC_DAT(scif1_data_a,	TX1_A,			RX1_A);
-SCIF_PFC_PIN(scif1_data_b,	RCAR_GP_PIN(2, 24),	RCAR_GP_PIN(2, 25));
-SCIF_PFC_DAT(scif1_data_b,	TX1_B,			RX1_B);
-SCIF_PFC_PIN(scif1_data_c,	RCAR_GP_PIN(3, 22),	RCAR_GP_PIN(3, 21));
-SCIF_PFC_DAT(scif1_data_c,	TX1_C,			RX1_C);
-SCIF_PFC_PIN(scif1_data_d,	RCAR_GP_PIN(1, 30),	RCAR_GP_PIN(1, 31));
-SCIF_PFC_DAT(scif1_data_d,	TX1_D,			RX1_D);
-SCIF_PFC_PIN(scif1_ctrl_a,	RCAR_GP_PIN(4, 3),	RCAR_GP_PIN(4, 4));
-SCIF_PFC_CTR(scif1_ctrl_a,	CTS1_A,			RTS1_A);
-SCIF_PFC_PIN(scif1_ctrl_c,	RCAR_GP_PIN(3, 23),	RCAR_GP_PIN(3, 19));
-SCIF_PFC_CTR(scif1_ctrl_c,	CTS1_C,			RTS1_C);
-SCIF_PFC_PIN(scif1_clk_a,	RCAR_GP_PIN(4, 2));
-SCIF_PFC_CLK(scif1_clk_a,	SCK1_A);
-SCIF_PFC_PIN(scif1_clk_c,	RCAR_GP_PIN(3, 20));
-SCIF_PFC_CLK(scif1_clk_c,	SCK1_C);
-
-/* - SCIF2 ------------------------------------------------------------------ */
-SCIF_PFC_PIN(scif2_data_a,	RCAR_GP_PIN(2, 26),	RCAR_GP_PIN(2, 27));
-SCIF_PFC_DAT(scif2_data_a,	TX2_A,			RX2_A);
-SCIF_PFC_PIN(scif2_data_b,	RCAR_GP_PIN(0, 29),	RCAR_GP_PIN(0, 28));
-SCIF_PFC_DAT(scif2_data_b,	TX2_B,			RX2_B);
-SCIF_PFC_PIN(scif2_data_c,	RCAR_GP_PIN(4, 13),	RCAR_GP_PIN(4, 14));
-SCIF_PFC_DAT(scif2_data_c,	TX2_C,			RX2_C);
-SCIF_PFC_PIN(scif2_data_d,	RCAR_GP_PIN(4, 15),	RCAR_GP_PIN(4, 16));
-SCIF_PFC_DAT(scif2_data_d,	TX2_D,			RX2_D);
-SCIF_PFC_PIN(scif2_data_e,	RCAR_GP_PIN(0, 3),	RCAR_GP_PIN(0, 4));
-SCIF_PFC_DAT(scif2_data_e,	TX2_E,			RX2_E);
-SCIF_PFC_PIN(scif2_clk_a,	RCAR_GP_PIN(3, 9));
-SCIF_PFC_CLK(scif2_clk_a,	SCK2_A);
-SCIF_PFC_PIN(scif2_clk_b,	PIN_CS1_A26);
-SCIF_PFC_CLK(scif2_clk_b,	SCK2_B);
-SCIF_PFC_PIN(scif2_clk_c,	RCAR_GP_PIN(4, 12));
-SCIF_PFC_CLK(scif2_clk_c,	SCK2_C);
-
-/* - SCIF3 ------------------------------------------------------------------ */
-SCIF_PFC_PIN(scif3_data_a,	RCAR_GP_PIN(1, 10),	RCAR_GP_PIN(1, 9));
-SCIF_PFC_DAT(scif3_data_a,	TX3_A,			RX3_A);
-SCIF_PFC_PIN(scif3_data_b,	RCAR_GP_PIN(3, 28),	RCAR_GP_PIN(3, 27));
-SCIF_PFC_DAT(scif3_data_b,	TX3_B,			RX3_B);
-SCIF_PFC_PIN(scif3_data_c,	RCAR_GP_PIN(1, 3),	RCAR_GP_PIN(0, 31));
-SCIF_PFC_DAT(scif3_data_c,	TX3_C,			RX3_C);
-SCIF_PFC_PIN(scif3_data_d,	RCAR_GP_PIN(3, 30),	RCAR_GP_PIN(3, 29));
-SCIF_PFC_DAT(scif3_data_d,	TX3_D,			RX3_D);
-
-/* - SCIF4 ------------------------------------------------------------------ */
-SCIF_PFC_PIN(scif4_data_a,	RCAR_GP_PIN(2, 5),	RCAR_GP_PIN(2, 4));
-SCIF_PFC_DAT(scif4_data_a,	TX4_A,			RX4_A);
-SCIF_PFC_PIN(scif4_data_b,	RCAR_GP_PIN(3, 26),	RCAR_GP_PIN(3, 25));
-SCIF_PFC_DAT(scif4_data_b,	TX4_B,			RX4_B);
-SCIF_PFC_PIN(scif4_data_c,	RCAR_GP_PIN(3, 0),	RCAR_GP_PIN(2, 31));
-SCIF_PFC_DAT(scif4_data_c,	TX4_C,			RX4_C);
-
-/* - SCIF5 ------------------------------------------------------------------ */
-SCIF_PFC_PIN(scif5_data_a,	RCAR_GP_PIN(3, 17),	RCAR_GP_PIN(3, 18));
-SCIF_PFC_DAT(scif5_data_a,	TX5_A,			RX5_A);
-SCIF_PFC_PIN(scif5_data_b,	RCAR_GP_PIN(1, 15),	RCAR_GP_PIN(1, 14));
-SCIF_PFC_DAT(scif5_data_b,	TX5_B,			RX5_B);
-
-/* - SDHI macro ------------------------------------------------------------- */
-#define SDHI_PFC_PINS(name, args...)		SH_PFC_PINS(name, args)
-#define SDHI_PFC_DAT1(name, d0)			SH_PFC_MUX1(name, d0)
-#define SDHI_PFC_DAT4(name, d0, d1, d2, d3)	SH_PFC_MUX4(name, d0, d1, d2, d3)
-#define SDHI_PFC_CTRL(name, clk, cmd)		SH_PFC_MUX2(name, clk, cmd)
-#define SDHI_PFC_CDPN(name, cd)			SH_PFC_MUX1(name, cd)
-#define SDHI_PFC_WPPN(name, wp)			SH_PFC_MUX1(name, wp)
-
-/* - SDHI0 ------------------------------------------------------------------ */
-SDHI_PFC_PINS(sdhi0_cd,		RCAR_GP_PIN(3, 17));
-SDHI_PFC_CDPN(sdhi0_cd,		SD0_CD);
-SDHI_PFC_PINS(sdhi0_ctrl,	RCAR_GP_PIN(3, 11),	RCAR_GP_PIN(3, 12));
-SDHI_PFC_CTRL(sdhi0_ctrl,	SD0_CLK,		SD0_CMD);
-SDHI_PFC_PINS(sdhi0_data1,	RCAR_GP_PIN(3, 13));
-SDHI_PFC_DAT1(sdhi0_data1,	SD0_DAT0);
-SDHI_PFC_PINS(sdhi0_data4,	RCAR_GP_PIN(3, 13),	RCAR_GP_PIN(3, 14),
-				RCAR_GP_PIN(3, 15),	RCAR_GP_PIN(3, 16));
-SDHI_PFC_DAT4(sdhi0_data4,	SD0_DAT0,		SD0_DAT1,
-				SD0_DAT2,		SD0_DAT3);
-SDHI_PFC_PINS(sdhi0_wp,		RCAR_GP_PIN(3, 18));
-SDHI_PFC_WPPN(sdhi0_wp,		SD0_WP);
-
-/* - SDHI1 ------------------------------------------------------------------ */
-SDHI_PFC_PINS(sdhi1_cd_a,	RCAR_GP_PIN(0, 30));
-SDHI_PFC_CDPN(sdhi1_cd_a,	SD1_CD_A);
-SDHI_PFC_PINS(sdhi1_cd_b,	RCAR_GP_PIN(2, 24));
-SDHI_PFC_CDPN(sdhi1_cd_b,	SD1_CD_B);
-SDHI_PFC_PINS(sdhi1_ctrl_a,	RCAR_GP_PIN(1, 5),	RCAR_GP_PIN(1, 6));
-SDHI_PFC_CTRL(sdhi1_ctrl_a,	SD1_CLK_A,		SD1_CMD_A);
-SDHI_PFC_PINS(sdhi1_ctrl_b,	RCAR_GP_PIN(1, 17),	RCAR_GP_PIN(1, 16));
-SDHI_PFC_CTRL(sdhi1_ctrl_b,	SD1_CLK_B,		SD1_CMD_B);
-SDHI_PFC_PINS(sdhi1_data1_a,	RCAR_GP_PIN(1, 7));
-SDHI_PFC_DAT1(sdhi1_data1_a,	SD1_DAT0_A);
-SDHI_PFC_PINS(sdhi1_data1_b,	RCAR_GP_PIN(1, 18));
-SDHI_PFC_DAT1(sdhi1_data1_b,	SD1_DAT0_B);
-SDHI_PFC_PINS(sdhi1_data4_a,	RCAR_GP_PIN(1, 7),	RCAR_GP_PIN(1, 8),
-				RCAR_GP_PIN(0, 5),	RCAR_GP_PIN(0, 6));
-SDHI_PFC_DAT4(sdhi1_data4_a,	SD1_DAT0_A,		SD1_DAT1_A,
-				SD1_DAT2_A,		SD1_DAT3_A);
-SDHI_PFC_PINS(sdhi1_data4_b,	RCAR_GP_PIN(1, 18),	RCAR_GP_PIN(1, 19),
-				RCAR_GP_PIN(1, 20),	RCAR_GP_PIN(1, 21));
-SDHI_PFC_DAT4(sdhi1_data4_b,	SD1_DAT0_B,		SD1_DAT1_B,
-				SD1_DAT2_B,		SD1_DAT3_B);
-SDHI_PFC_PINS(sdhi1_wp_a,	RCAR_GP_PIN(0, 31));
-SDHI_PFC_WPPN(sdhi1_wp_a,	SD1_WP_A);
-SDHI_PFC_PINS(sdhi1_wp_b,	RCAR_GP_PIN(2, 25));
-SDHI_PFC_WPPN(sdhi1_wp_b,	SD1_WP_B);
-
-/* - SDH2 ------------------------------------------------------------------- */
-SDHI_PFC_PINS(sdhi2_cd_a,	RCAR_GP_PIN(4, 23));
-SDHI_PFC_CDPN(sdhi2_cd_a,	SD2_CD_A);
-SDHI_PFC_PINS(sdhi2_cd_b,	RCAR_GP_PIN(3, 27));
-SDHI_PFC_CDPN(sdhi2_cd_b,	SD2_CD_B);
-SDHI_PFC_PINS(sdhi2_ctrl_a,	RCAR_GP_PIN(4, 17),	RCAR_GP_PIN(4, 18));
-SDHI_PFC_CTRL(sdhi2_ctrl_a,	SD2_CLK_A,		SD2_CMD_A);
-SDHI_PFC_PINS(sdhi2_ctrl_b,	RCAR_GP_PIN(4, 5),	RCAR_GP_PIN(4, 6));
-SDHI_PFC_CTRL(sdhi2_ctrl_b,	SD2_CLK_B,		SD2_CMD_B);
-SDHI_PFC_PINS(sdhi2_data1_a,	RCAR_GP_PIN(4, 19));
-SDHI_PFC_DAT1(sdhi2_data1_a,	SD2_DAT0_A);
-SDHI_PFC_PINS(sdhi2_data1_b,	RCAR_GP_PIN(4, 7));
-SDHI_PFC_DAT1(sdhi2_data1_b,	SD2_DAT0_B);
-SDHI_PFC_PINS(sdhi2_data4_a,	RCAR_GP_PIN(4, 19),	RCAR_GP_PIN(4, 20),
-				RCAR_GP_PIN(4, 21),	RCAR_GP_PIN(4, 22));
-SDHI_PFC_DAT4(sdhi2_data4_a,	SD2_DAT0_A,		SD2_DAT1_A,
-				SD2_DAT2_A,		SD2_DAT3_A);
-SDHI_PFC_PINS(sdhi2_data4_b,	RCAR_GP_PIN(4, 7),	RCAR_GP_PIN(4, 8),
-				RCAR_GP_PIN(3, 25),	RCAR_GP_PIN(3, 26));
-SDHI_PFC_DAT4(sdhi2_data4_b,	SD2_DAT0_B,		SD2_DAT1_B,
-				SD2_DAT2_B,		SD2_DAT3_B);
-SDHI_PFC_PINS(sdhi2_wp_a,	RCAR_GP_PIN(4, 24));
-SDHI_PFC_WPPN(sdhi2_wp_a,	SD2_WP_A);
-SDHI_PFC_PINS(sdhi2_wp_b,	RCAR_GP_PIN(3, 28));
-SDHI_PFC_WPPN(sdhi2_wp_b,	SD2_WP_B);
-
-/* - SSI macro -------------------------------------------------------------- */
-#define SSI_PFC_PINS(name, args...)		SH_PFC_PINS(name, args)
-#define SSI_PFC_CTRL(name, sck, ws)		SH_PFC_MUX2(name, sck, ws)
-#define SSI_PFC_DATA(name, d)			SH_PFC_MUX1(name, d)
-
-/* - SSI 0/1/2 -------------------------------------------------------------- */
-SSI_PFC_PINS(ssi012_ctrl,	RCAR_GP_PIN(3, 6),	RCAR_GP_PIN(3, 7));
-SSI_PFC_CTRL(ssi012_ctrl,	SSI_SCK012,		SSI_WS012);
-SSI_PFC_PINS(ssi0_data,		RCAR_GP_PIN(3, 10));
-SSI_PFC_DATA(ssi0_data,		SSI_SDATA0);
-SSI_PFC_PINS(ssi1_a_ctrl,	RCAR_GP_PIN(2, 20),	RCAR_GP_PIN(2, 21));
-SSI_PFC_CTRL(ssi1_a_ctrl,	SSI_SCK1_A,		SSI_WS1_A);
-SSI_PFC_PINS(ssi1_b_ctrl,	PIN_CS1_A26,		RCAR_GP_PIN(1, 3));
-SSI_PFC_CTRL(ssi1_b_ctrl,	SSI_SCK1_B,		SSI_WS1_B);
-SSI_PFC_PINS(ssi1_data,		RCAR_GP_PIN(3, 9));
-SSI_PFC_DATA(ssi1_data,		SSI_SDATA1);
-SSI_PFC_PINS(ssi2_a_ctrl,	RCAR_GP_PIN(2, 26),	RCAR_GP_PIN(3, 4));
-SSI_PFC_CTRL(ssi2_a_ctrl,	SSI_SCK2_A,		SSI_WS2_A);
-SSI_PFC_PINS(ssi2_b_ctrl,	RCAR_GP_PIN(2, 6),	RCAR_GP_PIN(2, 17));
-SSI_PFC_CTRL(ssi2_b_ctrl,	SSI_SCK2_B,		SSI_WS2_B);
-SSI_PFC_PINS(ssi2_data,		RCAR_GP_PIN(3, 8));
-SSI_PFC_DATA(ssi2_data,		SSI_SDATA2);
-
-/* - SSI 3/4 ---------------------------------------------------------------- */
-SSI_PFC_PINS(ssi34_ctrl,	RCAR_GP_PIN(3, 2),	RCAR_GP_PIN(3, 3));
-SSI_PFC_CTRL(ssi34_ctrl,	SSI_SCK34,		SSI_WS34);
-SSI_PFC_PINS(ssi3_data,		RCAR_GP_PIN(3, 5));
-SSI_PFC_DATA(ssi3_data,		SSI_SDATA3);
-SSI_PFC_PINS(ssi4_ctrl,		RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 23));
-SSI_PFC_CTRL(ssi4_ctrl,		SSI_SCK4,               SSI_WS4);
-SSI_PFC_PINS(ssi4_data,		RCAR_GP_PIN(3, 4));
-SSI_PFC_DATA(ssi4_data,		SSI_SDATA4);
-
-/* - SSI 5 ------------------------------------------------------------------ */
-SSI_PFC_PINS(ssi5_ctrl,		RCAR_GP_PIN(2, 31),	RCAR_GP_PIN(3, 0));
-SSI_PFC_CTRL(ssi5_ctrl,		SSI_SCK5,		SSI_WS5);
-SSI_PFC_PINS(ssi5_data,		RCAR_GP_PIN(3, 1));
-SSI_PFC_DATA(ssi5_data,		SSI_SDATA5);
-
-/* - SSI 6 ------------------------------------------------------------------ */
-SSI_PFC_PINS(ssi6_ctrl,		RCAR_GP_PIN(2, 28),	RCAR_GP_PIN(2, 29));
-SSI_PFC_CTRL(ssi6_ctrl,		SSI_SCK6,		SSI_WS6);
-SSI_PFC_PINS(ssi6_data,		RCAR_GP_PIN(2, 30));
-SSI_PFC_DATA(ssi6_data,		SSI_SDATA6);
-
-/* - SSI 7/8  --------------------------------------------------------------- */
-SSI_PFC_PINS(ssi78_ctrl,	RCAR_GP_PIN(2, 24),	RCAR_GP_PIN(2, 25));
-SSI_PFC_CTRL(ssi78_ctrl,	SSI_SCK78,		SSI_WS78);
-SSI_PFC_PINS(ssi7_data,		RCAR_GP_PIN(2, 27));
-SSI_PFC_DATA(ssi7_data,		SSI_SDATA7);
-SSI_PFC_PINS(ssi8_data,		RCAR_GP_PIN(2, 26));
-SSI_PFC_DATA(ssi8_data,		SSI_SDATA8);
-
-/* - USB0 ------------------------------------------------------------------- */
-SH_PFC_PINS(usb0,		RCAR_GP_PIN(0, 1));
-SH_PFC_MUX1(usb0,		PENC0);
-SH_PFC_PINS(usb0_ovc,		RCAR_GP_PIN(0, 3));
-SH_PFC_MUX1(usb0_ovc,		USB_OVC0);
-
-/* - USB1 ------------------------------------------------------------------- */
-SH_PFC_PINS(usb1,		RCAR_GP_PIN(0, 2));
-SH_PFC_MUX1(usb1,		PENC1);
-SH_PFC_PINS(usb1_ovc,		RCAR_GP_PIN(0, 4));
-SH_PFC_MUX1(usb1_ovc,		USB_OVC1);
-
-/* - VIN macros ------------------------------------------------------------- */
-#define VIN_PFC_PINS(name, args...)		SH_PFC_PINS(name, args)
-#define VIN_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7)	\
-	SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
-#define VIN_PFC_CLK(name, clk)			SH_PFC_MUX1(name, clk)
-#define VIN_PFC_SYNC(name, hsync, vsync)	SH_PFC_MUX2(name, hsync, vsync)
-
-/* - VIN0 ------------------------------------------------------------------- */
-VIN_PFC_PINS(vin0_data8,	RCAR_GP_PIN(3, 29),	RCAR_GP_PIN(3, 30),
-				RCAR_GP_PIN(3, 31),	RCAR_GP_PIN(4, 0),
-				RCAR_GP_PIN(4, 1),	RCAR_GP_PIN(4, 2),
-				RCAR_GP_PIN(4, 3),	RCAR_GP_PIN(4, 4));
-VIN_PFC_DAT8(vin0_data8,	VI0_DATA0_VI0_B0,	VI0_DATA1_VI0_B1,
-				VI0_DATA2_VI0_B2,	VI0_DATA3_VI0_B3,
-				VI0_DATA4_VI0_B4,	VI0_DATA5_VI0_B5,
-				VI0_DATA6_VI0_G0,	VI0_DATA7_VI0_G1);
-VIN_PFC_PINS(vin0_clk,		RCAR_GP_PIN(3, 24));
-VIN_PFC_CLK(vin0_clk,		VI0_CLK);
-VIN_PFC_PINS(vin0_sync,		RCAR_GP_PIN(3, 27),	RCAR_GP_PIN(3, 28));
-VIN_PFC_SYNC(vin0_sync,		VI0_HSYNC,		VI0_VSYNC);
-/* - VIN1 ------------------------------------------------------------------- */
-VIN_PFC_PINS(vin1_data8,	RCAR_GP_PIN(3, 25),	RCAR_GP_PIN(3, 26),
-				RCAR_GP_PIN(3, 27),	RCAR_GP_PIN(3, 28),
-				RCAR_GP_PIN(4, 5),	RCAR_GP_PIN(4, 6),
-				RCAR_GP_PIN(4, 7),	RCAR_GP_PIN(4, 8));
-VIN_PFC_DAT8(vin1_data8,	VI1_DATA0,		VI1_DATA1,
-				VI1_DATA2,		VI1_DATA3,
-				VI1_DATA4,		VI1_DATA5,
-				VI1_DATA6,		VI1_DATA7);
-VIN_PFC_PINS(vin1_clk,		RCAR_GP_PIN(4, 9));
-VIN_PFC_CLK(vin1_clk,		VI1_CLK);
-VIN_PFC_PINS(vin1_sync,		RCAR_GP_PIN(3, 21),	RCAR_GP_PIN(3, 22));
-VIN_PFC_SYNC(vin1_sync,		VI1_HSYNC,		VI1_VSYNC);
-
-static const struct sh_pfc_pin_group pinmux_groups[] = {
-	SH_PFC_PIN_GROUP(audio_clk_a),
-	SH_PFC_PIN_GROUP(audio_clk_b),
-	SH_PFC_PIN_GROUP(audio_clk_c),
-	SH_PFC_PIN_GROUP(audio_clkout_a),
-	SH_PFC_PIN_GROUP(audio_clkout_b),
-	SH_PFC_PIN_GROUP(can0_data_a),
-	SH_PFC_PIN_GROUP(can0_data_b),
-	SH_PFC_PIN_GROUP(can1_data_a),
-	SH_PFC_PIN_GROUP(can1_data_b),
-	SH_PFC_PIN_GROUP(can_clk_a),
-	SH_PFC_PIN_GROUP(can_clk_b),
-	SH_PFC_PIN_GROUP(can_clk_c),
-	SH_PFC_PIN_GROUP(can_clk_d),
-	SH_PFC_PIN_GROUP(ether_rmii),
-	SH_PFC_PIN_GROUP(ether_link),
-	SH_PFC_PIN_GROUP(ether_magic),
-	SH_PFC_PIN_GROUP(hscif0_data_a),
-	SH_PFC_PIN_GROUP(hscif0_data_b),
-	SH_PFC_PIN_GROUP(hscif0_ctrl_a),
-	SH_PFC_PIN_GROUP(hscif0_ctrl_b),
-	SH_PFC_PIN_GROUP(hscif0_clk),
-	SH_PFC_PIN_GROUP(hscif1_data_a),
-	SH_PFC_PIN_GROUP(hscif1_data_b),
-	SH_PFC_PIN_GROUP(hscif1_ctrl_a),
-	SH_PFC_PIN_GROUP(hscif1_ctrl_b),
-	SH_PFC_PIN_GROUP(hscif1_clk_a),
-	SH_PFC_PIN_GROUP(hscif1_clk_b),
-	SH_PFC_PIN_GROUP(hspi0_a),
-	SH_PFC_PIN_GROUP(hspi0_b),
-	SH_PFC_PIN_GROUP(hspi1_a),
-	SH_PFC_PIN_GROUP(hspi1_b),
-	SH_PFC_PIN_GROUP(hspi2_a),
-	SH_PFC_PIN_GROUP(hspi2_b),
-	SH_PFC_PIN_GROUP(i2c1_a),
-	SH_PFC_PIN_GROUP(i2c1_b),
-	SH_PFC_PIN_GROUP(i2c2_a),
-	SH_PFC_PIN_GROUP(i2c2_b),
-	SH_PFC_PIN_GROUP(i2c2_c),
-	SH_PFC_PIN_GROUP(i2c3_a),
-	SH_PFC_PIN_GROUP(i2c3_b),
-	SH_PFC_PIN_GROUP(i2c3_c),
-	SH_PFC_PIN_GROUP(mmc_ctrl),
-	SH_PFC_PIN_GROUP(mmc_data1),
-	SH_PFC_PIN_GROUP(mmc_data4),
-	SH_PFC_PIN_GROUP(mmc_data8),
-	SH_PFC_PIN_GROUP(scif_clk),
-	SH_PFC_PIN_GROUP(scif0_data_a),
-	SH_PFC_PIN_GROUP(scif0_data_b),
-	SH_PFC_PIN_GROUP(scif0_data_c),
-	SH_PFC_PIN_GROUP(scif0_data_d),
-	SH_PFC_PIN_GROUP(scif0_ctrl),
-	SH_PFC_PIN_GROUP(scif0_clk),
-	SH_PFC_PIN_GROUP(scif1_data_a),
-	SH_PFC_PIN_GROUP(scif1_data_b),
-	SH_PFC_PIN_GROUP(scif1_data_c),
-	SH_PFC_PIN_GROUP(scif1_data_d),
-	SH_PFC_PIN_GROUP(scif1_ctrl_a),
-	SH_PFC_PIN_GROUP(scif1_ctrl_c),
-	SH_PFC_PIN_GROUP(scif1_clk_a),
-	SH_PFC_PIN_GROUP(scif1_clk_c),
-	SH_PFC_PIN_GROUP(scif2_data_a),
-	SH_PFC_PIN_GROUP(scif2_data_b),
-	SH_PFC_PIN_GROUP(scif2_data_c),
-	SH_PFC_PIN_GROUP(scif2_data_d),
-	SH_PFC_PIN_GROUP(scif2_data_e),
-	SH_PFC_PIN_GROUP(scif2_clk_a),
-	SH_PFC_PIN_GROUP(scif2_clk_b),
-	SH_PFC_PIN_GROUP(scif2_clk_c),
-	SH_PFC_PIN_GROUP(scif3_data_a),
-	SH_PFC_PIN_GROUP(scif3_data_b),
-	SH_PFC_PIN_GROUP(scif3_data_c),
-	SH_PFC_PIN_GROUP(scif3_data_d),
-	SH_PFC_PIN_GROUP(scif4_data_a),
-	SH_PFC_PIN_GROUP(scif4_data_b),
-	SH_PFC_PIN_GROUP(scif4_data_c),
-	SH_PFC_PIN_GROUP(scif5_data_a),
-	SH_PFC_PIN_GROUP(scif5_data_b),
-	SH_PFC_PIN_GROUP(sdhi0_cd),
-	SH_PFC_PIN_GROUP(sdhi0_ctrl),
-	SH_PFC_PIN_GROUP(sdhi0_data1),
-	SH_PFC_PIN_GROUP(sdhi0_data4),
-	SH_PFC_PIN_GROUP(sdhi0_wp),
-	SH_PFC_PIN_GROUP(sdhi1_cd_a),
-	SH_PFC_PIN_GROUP(sdhi1_cd_b),
-	SH_PFC_PIN_GROUP(sdhi1_ctrl_a),
-	SH_PFC_PIN_GROUP(sdhi1_ctrl_b),
-	SH_PFC_PIN_GROUP(sdhi1_data1_a),
-	SH_PFC_PIN_GROUP(sdhi1_data1_b),
-	SH_PFC_PIN_GROUP(sdhi1_data4_a),
-	SH_PFC_PIN_GROUP(sdhi1_data4_b),
-	SH_PFC_PIN_GROUP(sdhi1_wp_a),
-	SH_PFC_PIN_GROUP(sdhi1_wp_b),
-	SH_PFC_PIN_GROUP(sdhi2_cd_a),
-	SH_PFC_PIN_GROUP(sdhi2_cd_b),
-	SH_PFC_PIN_GROUP(sdhi2_ctrl_a),
-	SH_PFC_PIN_GROUP(sdhi2_ctrl_b),
-	SH_PFC_PIN_GROUP(sdhi2_data1_a),
-	SH_PFC_PIN_GROUP(sdhi2_data1_b),
-	SH_PFC_PIN_GROUP(sdhi2_data4_a),
-	SH_PFC_PIN_GROUP(sdhi2_data4_b),
-	SH_PFC_PIN_GROUP(sdhi2_wp_a),
-	SH_PFC_PIN_GROUP(sdhi2_wp_b),
-	SH_PFC_PIN_GROUP(ssi012_ctrl),
-	SH_PFC_PIN_GROUP(ssi0_data),
-	SH_PFC_PIN_GROUP(ssi1_a_ctrl),
-	SH_PFC_PIN_GROUP(ssi1_b_ctrl),
-	SH_PFC_PIN_GROUP(ssi1_data),
-	SH_PFC_PIN_GROUP(ssi2_a_ctrl),
-	SH_PFC_PIN_GROUP(ssi2_b_ctrl),
-	SH_PFC_PIN_GROUP(ssi2_data),
-	SH_PFC_PIN_GROUP(ssi34_ctrl),
-	SH_PFC_PIN_GROUP(ssi3_data),
-	SH_PFC_PIN_GROUP(ssi4_ctrl),
-	SH_PFC_PIN_GROUP(ssi4_data),
-	SH_PFC_PIN_GROUP(ssi5_ctrl),
-	SH_PFC_PIN_GROUP(ssi5_data),
-	SH_PFC_PIN_GROUP(ssi6_ctrl),
-	SH_PFC_PIN_GROUP(ssi6_data),
-	SH_PFC_PIN_GROUP(ssi78_ctrl),
-	SH_PFC_PIN_GROUP(ssi7_data),
-	SH_PFC_PIN_GROUP(ssi8_data),
-	SH_PFC_PIN_GROUP(usb0),
-	SH_PFC_PIN_GROUP(usb0_ovc),
-	SH_PFC_PIN_GROUP(usb1),
-	SH_PFC_PIN_GROUP(usb1_ovc),
-	SH_PFC_PIN_GROUP(vin0_data8),
-	SH_PFC_PIN_GROUP(vin0_clk),
-	SH_PFC_PIN_GROUP(vin0_sync),
-	SH_PFC_PIN_GROUP(vin1_data8),
-	SH_PFC_PIN_GROUP(vin1_clk),
-	SH_PFC_PIN_GROUP(vin1_sync),
-};
-
-static const char * const audio_clk_groups[] = {
-	"audio_clk_a",
-	"audio_clk_b",
-	"audio_clk_c",
-	"audio_clkout_a",
-	"audio_clkout_b",
-};
-
-static const char * const can0_groups[] = {
-	"can0_data_a",
-	"can0_data_b",
-	"can_clk_a",
-	"can_clk_b",
-	"can_clk_c",
-	"can_clk_d",
-};
-
-static const char * const can1_groups[] = {
-	"can1_data_a",
-	"can1_data_b",
-	"can_clk_a",
-	"can_clk_b",
-	"can_clk_c",
-	"can_clk_d",
-};
-
-static const char * const ether_groups[] = {
-	"ether_rmii",
-	"ether_link",
-	"ether_magic",
-};
-
-static const char * const hscif0_groups[] = {
-	"hscif0_data_a",
-	"hscif0_data_b",
-	"hscif0_ctrl_a",
-	"hscif0_ctrl_b",
-	"hscif0_clk",
-};
-
-static const char * const hscif1_groups[] = {
-	"hscif1_data_a",
-	"hscif1_data_b",
-	"hscif1_ctrl_a",
-	"hscif1_ctrl_b",
-	"hscif1_clk_a",
-	"hscif1_clk_b",
-};
-
-static const char * const hspi0_groups[] = {
-	"hspi0_a",
-	"hspi0_b",
-};
-
-static const char * const hspi1_groups[] = {
-	"hspi1_a",
-	"hspi1_b",
-};
-
-static const char * const hspi2_groups[] = {
-	"hspi2_a",
-	"hspi2_b",
-};
-
-static const char * const i2c1_groups[] = {
-	"i2c1_a",
-	"i2c1_b",
-};
-
-static const char * const i2c2_groups[] = {
-	"i2c2_a",
-	"i2c2_b",
-	"i2c2_c",
-};
-
-static const char * const i2c3_groups[] = {
-	"i2c3_a",
-	"i2c3_b",
-	"i2c3_c",
-};
-
-static const char * const mmc_groups[] = {
-	"mmc_ctrl",
-	"mmc_data1",
-	"mmc_data4",
-	"mmc_data8",
-};
-
-static const char * const scif_clk_groups[] = {
-	"scif_clk",
-};
-
-static const char * const scif0_groups[] = {
-	"scif0_data_a",
-	"scif0_data_b",
-	"scif0_data_c",
-	"scif0_data_d",
-	"scif0_ctrl",
-	"scif0_clk",
-};
-
-static const char * const scif1_groups[] = {
-	"scif1_data_a",
-	"scif1_data_b",
-	"scif1_data_c",
-	"scif1_data_d",
-	"scif1_ctrl_a",
-	"scif1_ctrl_c",
-	"scif1_clk_a",
-	"scif1_clk_c",
-};
-
-static const char * const scif2_groups[] = {
-	"scif2_data_a",
-	"scif2_data_b",
-	"scif2_data_c",
-	"scif2_data_d",
-	"scif2_data_e",
-	"scif2_clk_a",
-	"scif2_clk_b",
-	"scif2_clk_c",
-};
-
-static const char * const scif3_groups[] = {
-	"scif3_data_a",
-	"scif3_data_b",
-	"scif3_data_c",
-	"scif3_data_d",
-};
-
-static const char * const scif4_groups[] = {
-	"scif4_data_a",
-	"scif4_data_b",
-	"scif4_data_c",
-};
-
-static const char * const scif5_groups[] = {
-	"scif5_data_a",
-	"scif5_data_b",
-};
-
-
-static const char * const sdhi0_groups[] = {
-	"sdhi0_cd",
-	"sdhi0_ctrl",
-	"sdhi0_data1",
-	"sdhi0_data4",
-	"sdhi0_wp",
-};
-
-static const char * const sdhi1_groups[] = {
-	"sdhi1_cd_a",
-	"sdhi1_cd_b",
-	"sdhi1_ctrl_a",
-	"sdhi1_ctrl_b",
-	"sdhi1_data1_a",
-	"sdhi1_data1_b",
-	"sdhi1_data4_a",
-	"sdhi1_data4_b",
-	"sdhi1_wp_a",
-	"sdhi1_wp_b",
-};
-
-static const char * const sdhi2_groups[] = {
-	"sdhi2_cd_a",
-	"sdhi2_cd_b",
-	"sdhi2_ctrl_a",
-	"sdhi2_ctrl_b",
-	"sdhi2_data1_a",
-	"sdhi2_data1_b",
-	"sdhi2_data4_a",
-	"sdhi2_data4_b",
-	"sdhi2_wp_a",
-	"sdhi2_wp_b",
-};
-
-static const char * const ssi_groups[] = {
-	"ssi012_ctrl",
-	"ssi0_data",
-	"ssi1_a_ctrl",
-	"ssi1_b_ctrl",
-	"ssi1_data",
-	"ssi2_a_ctrl",
-	"ssi2_b_ctrl",
-	"ssi2_data",
-	"ssi34_ctrl",
-	"ssi3_data",
-	"ssi4_ctrl",
-	"ssi4_data",
-	"ssi5_ctrl",
-	"ssi5_data",
-	"ssi6_ctrl",
-	"ssi6_data",
-	"ssi78_ctrl",
-	"ssi7_data",
-	"ssi8_data",
-};
-
-static const char * const usb0_groups[] = {
-	"usb0",
-	"usb0_ovc",
-};
-
-static const char * const usb1_groups[] = {
-	"usb1",
-	"usb1_ovc",
-};
-
-static const char * const vin0_groups[] = {
-	"vin0_data8",
-	"vin0_clk",
-	"vin0_sync",
-};
-
-static const char * const vin1_groups[] = {
-	"vin1_data8",
-	"vin1_clk",
-	"vin1_sync",
-};
-
-static const struct sh_pfc_function pinmux_functions[] = {
-	SH_PFC_FUNCTION(audio_clk),
-	SH_PFC_FUNCTION(can0),
-	SH_PFC_FUNCTION(can1),
-	SH_PFC_FUNCTION(ether),
-	SH_PFC_FUNCTION(hscif0),
-	SH_PFC_FUNCTION(hscif1),
-	SH_PFC_FUNCTION(hspi0),
-	SH_PFC_FUNCTION(hspi1),
-	SH_PFC_FUNCTION(hspi2),
-	SH_PFC_FUNCTION(i2c1),
-	SH_PFC_FUNCTION(i2c2),
-	SH_PFC_FUNCTION(i2c3),
-	SH_PFC_FUNCTION(mmc),
-	SH_PFC_FUNCTION(scif_clk),
-	SH_PFC_FUNCTION(scif0),
-	SH_PFC_FUNCTION(scif1),
-	SH_PFC_FUNCTION(scif2),
-	SH_PFC_FUNCTION(scif3),
-	SH_PFC_FUNCTION(scif4),
-	SH_PFC_FUNCTION(scif5),
-	SH_PFC_FUNCTION(sdhi0),
-	SH_PFC_FUNCTION(sdhi1),
-	SH_PFC_FUNCTION(sdhi2),
-	SH_PFC_FUNCTION(ssi),
-	SH_PFC_FUNCTION(usb0),
-	SH_PFC_FUNCTION(usb1),
-	SH_PFC_FUNCTION(vin0),
-	SH_PFC_FUNCTION(vin1),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	{ PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1, GROUP(
-		GP_0_31_FN,	FN_IP1_14_11,
-		GP_0_30_FN,	FN_IP1_10_8,
-		GP_0_29_FN,	FN_IP1_7_5,
-		GP_0_28_FN,	FN_IP1_4_2,
-		GP_0_27_FN,	FN_IP1_1,
-		GP_0_26_FN,	FN_IP1_0,
-		GP_0_25_FN,	FN_IP0_30,
-		GP_0_24_FN,	FN_IP0_29,
-		GP_0_23_FN,	FN_IP0_28,
-		GP_0_22_FN,	FN_IP0_27,
-		GP_0_21_FN,	FN_IP0_26,
-		GP_0_20_FN,	FN_IP0_25,
-		GP_0_19_FN,	FN_IP0_24,
-		GP_0_18_FN,	FN_IP0_23,
-		GP_0_17_FN,	FN_IP0_22,
-		GP_0_16_FN,	FN_IP0_21,
-		GP_0_15_FN,	FN_IP0_20,
-		GP_0_14_FN,	FN_IP0_19,
-		GP_0_13_FN,	FN_IP0_18,
-		GP_0_12_FN,	FN_IP0_17,
-		GP_0_11_FN,	FN_IP0_16,
-		GP_0_10_FN,	FN_IP0_15,
-		GP_0_9_FN,	FN_A3,
-		GP_0_8_FN,	FN_A2,
-		GP_0_7_FN,	FN_A1,
-		GP_0_6_FN,	FN_IP0_14_12,
-		GP_0_5_FN,	FN_IP0_11_8,
-		GP_0_4_FN,	FN_IP0_7_5,
-		GP_0_3_FN,	FN_IP0_4_2,
-		GP_0_2_FN,	FN_PENC1,
-		GP_0_1_FN,	FN_PENC0,
-		GP_0_0_FN,	FN_IP0_1_0 ))
-	},
-	{ PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1, GROUP(
-		GP_1_31_FN,	FN_IP4_6_4,
-		GP_1_30_FN,	FN_IP4_3_1,
-		GP_1_29_FN,	FN_IP4_0,
-		GP_1_28_FN,	FN_IP3_31,
-		GP_1_27_FN,	FN_IP3_30,
-		GP_1_26_FN,	FN_IP3_29,
-		GP_1_25_FN,	FN_IP3_28,
-		GP_1_24_FN,	FN_IP3_27,
-		GP_1_23_FN,	FN_IP3_26_24,
-		GP_1_22_FN,	FN_IP3_23_21,
-		GP_1_21_FN,	FN_IP3_20_19,
-		GP_1_20_FN,	FN_IP3_18_16,
-		GP_1_19_FN,	FN_IP3_15_13,
-		GP_1_18_FN,	FN_IP3_12_10,
-		GP_1_17_FN,	FN_IP3_9_8,
-		GP_1_16_FN,	FN_IP3_7_5,
-		GP_1_15_FN,	FN_IP3_4_2,
-		GP_1_14_FN,	FN_IP3_1_0,
-		GP_1_13_FN,	FN_IP2_31,
-		GP_1_12_FN,	FN_IP2_30,
-		GP_1_11_FN,	FN_IP2_17,
-		GP_1_10_FN,	FN_IP2_16_14,
-		GP_1_9_FN,	FN_IP2_13_12,
-		GP_1_8_FN,	FN_IP2_11_9,
-		GP_1_7_FN,	FN_IP2_8_6,
-		GP_1_6_FN,	FN_IP2_5_3,
-		GP_1_5_FN,	FN_IP2_2_0,
-		GP_1_4_FN,	FN_IP1_29_28,
-		GP_1_3_FN,	FN_IP1_27_25,
-		GP_1_2_FN,	FN_IP1_24,
-		GP_1_1_FN,	FN_WE0,
-		GP_1_0_FN,	FN_IP1_23_21 ))
-	},
-	{ PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1, GROUP(
-		GP_2_31_FN,	FN_IP6_7,
-		GP_2_30_FN,	FN_IP6_6_5,
-		GP_2_29_FN,	FN_IP6_4_2,
-		GP_2_28_FN,	FN_IP6_1_0,
-		GP_2_27_FN,	FN_IP5_30_29,
-		GP_2_26_FN,	FN_IP5_28_26,
-		GP_2_25_FN,	FN_IP5_25_23,
-		GP_2_24_FN,	FN_IP5_22_21,
-		GP_2_23_FN,	FN_AUDIO_CLKB,
-		GP_2_22_FN,	FN_AUDIO_CLKA,
-		GP_2_21_FN,	FN_IP5_20_18,
-		GP_2_20_FN,	FN_IP5_17_15,
-		GP_2_19_FN,	FN_IP5_14_13,
-		GP_2_18_FN,	FN_IP5_12,
-		GP_2_17_FN,	FN_IP5_11_10,
-		GP_2_16_FN,	FN_IP5_9_8,
-		GP_2_15_FN,	FN_IP5_7,
-		GP_2_14_FN,	FN_IP5_6,
-		GP_2_13_FN,	FN_IP5_5_4,
-		GP_2_12_FN,	FN_IP5_3_2,
-		GP_2_11_FN,	FN_IP5_1_0,
-		GP_2_10_FN,	FN_IP4_30_29,
-		GP_2_9_FN,	FN_IP4_28_27,
-		GP_2_8_FN,	FN_IP4_26_25,
-		GP_2_7_FN,	FN_IP4_24_21,
-		GP_2_6_FN,	FN_IP4_20_17,
-		GP_2_5_FN,	FN_IP4_16_15,
-		GP_2_4_FN,	FN_IP4_14_13,
-		GP_2_3_FN,	FN_IP4_12_11,
-		GP_2_2_FN,	FN_IP4_10_9,
-		GP_2_1_FN,	FN_IP4_8,
-		GP_2_0_FN,	FN_IP4_7 ))
-	},
-	{ PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1, GROUP(
-		GP_3_31_FN,	FN_IP8_10_9,
-		GP_3_30_FN,	FN_IP8_8_6,
-		GP_3_29_FN,	FN_IP8_5_3,
-		GP_3_28_FN,	FN_IP8_2_0,
-		GP_3_27_FN,	FN_IP7_31_29,
-		GP_3_26_FN,	FN_IP7_28_25,
-		GP_3_25_FN,	FN_IP7_24_22,
-		GP_3_24_FN,	FN_IP7_21,
-		GP_3_23_FN,	FN_IP7_20_18,
-		GP_3_22_FN,	FN_IP7_17_15,
-		GP_3_21_FN,	FN_IP7_14_12,
-		GP_3_20_FN,	FN_IP7_11_9,
-		GP_3_19_FN,	FN_IP7_8_6,
-		GP_3_18_FN,	FN_IP7_5_4,
-		GP_3_17_FN,	FN_IP7_3_2,
-		GP_3_16_FN,	FN_IP7_1_0,
-		GP_3_15_FN,	FN_IP6_31_30,
-		GP_3_14_FN,	FN_IP6_29_28,
-		GP_3_13_FN,	FN_IP6_27_26,
-		GP_3_12_FN,	FN_IP6_25_24,
-		GP_3_11_FN,	FN_IP6_23_22,
-		GP_3_10_FN,	FN_IP6_21,
-		GP_3_9_FN,	FN_IP6_20_19,
-		GP_3_8_FN,	FN_IP6_18_17,
-		GP_3_7_FN,	FN_IP6_16,
-		GP_3_6_FN,	FN_IP6_15_14,
-		GP_3_5_FN,	FN_IP6_13,
-		GP_3_4_FN,	FN_IP6_12_11,
-		GP_3_3_FN,	FN_IP6_10,
-		GP_3_2_FN,	FN_SSI_SCK34,
-		GP_3_1_FN,	FN_IP6_9,
-		GP_3_0_FN,	FN_IP6_8 ))
-	},
-	{ PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_4_26_FN,	FN_AVS2,
-		GP_4_25_FN,	FN_AVS1,
-		GP_4_24_FN,	FN_IP10_24_22,
-		GP_4_23_FN,	FN_IP10_21_19,
-		GP_4_22_FN,	FN_IP10_18_16,
-		GP_4_21_FN,	FN_IP10_15_13,
-		GP_4_20_FN,	FN_IP10_12_9,
-		GP_4_19_FN,	FN_IP10_8_6,
-		GP_4_18_FN,	FN_IP10_5_3,
-		GP_4_17_FN,	FN_IP10_2_0,
-		GP_4_16_FN,	FN_IP9_29_27,
-		GP_4_15_FN,	FN_IP9_26_24,
-		GP_4_14_FN,	FN_IP9_23_21,
-		GP_4_13_FN,	FN_IP9_20_18,
-		GP_4_12_FN,	FN_IP9_17_15,
-		GP_4_11_FN,	FN_IP9_14_12,
-		GP_4_10_FN,	FN_IP9_11_9,
-		GP_4_9_FN,	FN_IP9_8_6,
-		GP_4_8_FN,	FN_IP9_5_3,
-		GP_4_7_FN,	FN_IP9_2_0,
-		GP_4_6_FN,	FN_IP8_29_27,
-		GP_4_5_FN,	FN_IP8_26_24,
-		GP_4_4_FN,	FN_IP8_23_22,
-		GP_4_3_FN,	FN_IP8_21_19,
-		GP_4_2_FN,	FN_IP8_18_16,
-		GP_4_1_FN,	FN_IP8_15_14,
-		GP_4_0_FN,	FN_IP8_13_11 ))
-	},
-
-	{ PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
-			     GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-				   1, 1, 1, 1, 1, 3, 4, 3, 3, 2),
-			     GROUP(
-		/* IP0_31 [1] */
-		0,	0,
-		/* IP0_30 [1] */
-		FN_A19,	0,
-		/* IP0_29 [1] */
-		FN_A18,	0,
-		/* IP0_28 [1] */
-		FN_A17,	0,
-		/* IP0_27 [1] */
-		FN_A16,	0,
-		/* IP0_26 [1] */
-		FN_A15,	0,
-		/* IP0_25 [1] */
-		FN_A14,	0,
-		/* IP0_24 [1] */
-		FN_A13,	0,
-		/* IP0_23 [1] */
-		FN_A12,	0,
-		/* IP0_22 [1] */
-		FN_A11,	0,
-		/* IP0_21 [1] */
-		FN_A10,	0,
-		/* IP0_20 [1] */
-		FN_A9,	0,
-		/* IP0_19 [1] */
-		FN_A8,	0,
-		/* IP0_18 [1] */
-		FN_A7,	0,
-		/* IP0_17 [1] */
-		FN_A6,	0,
-		/* IP0_16 [1] */
-		FN_A5,	0,
-		/* IP0_15 [1] */
-		FN_A4,	0,
-		/* IP0_14_12 [3] */
-		FN_SD1_DAT3_A,	FN_MMC_D3,	0,		FN_A0,
-		FN_ATAG0_A,	0,		FN_REMOCON_B,	0,
-		/* IP0_11_8 [4] */
-		FN_SD1_DAT2_A,	FN_MMC_D2,	0,		FN_BS,
-		FN_ATADIR0_A,	0,		FN_SDSELF_A,	0,
-		FN_PWM4_B,	0,		0,		0,
-		0,		0,		0,		0,
-		/* IP0_7_5 [3] */
-		FN_AUDATA1,	FN_ARM_TRACEDATA_1,	FN_GPSIN_C,	FN_USB_OVC1,
-		FN_RX2_E,	FN_SCL2_B,		0,		0,
-		/* IP0_4_2 [3] */
-		FN_AUDATA0,	FN_ARM_TRACEDATA_0,	FN_GPSCLK_C,	FN_USB_OVC0,
-		FN_TX2_E,	FN_SDA2_B,		0,		0,
-		/* IP0_1_0 [2] */
-		FN_PRESETOUT,	0,	FN_PWM1,	0,
-		))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
-			     GROUP(1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3,
-				   3, 1, 1),
-			     GROUP(
-		/* IP1_31 [1] */
-		0,	0,
-		/* IP1_30 [1] */
-		0,	0,
-		/* IP1_29_28 [2] */
-		FN_EX_CS1,	FN_MMC_D4,	0,	0,
-		/* IP1_27_25 [3] */
-		FN_SSI_WS1_B,	FN_EX_CS0,	FN_SCL2_A,	FN_TX3_C,
-		FN_TS_SCK0_A,	0,		0,		0,
-		/* IP1_24 [1] */
-		FN_WE1,		FN_ATAWR0_B,
-		/* IP1_23_21 [3] */
-		FN_MMC_D5,	FN_ATADIR0_B,	0,		FN_RD_WR,
-		0,		0,		0,		0,
-		/* IP1_20_18 [3] */
-		FN_SSI_SCK1_B,	FN_ATAG0_B,	FN_CS1_A26,	FN_SDA2_A,
-		FN_SCK2_B,	0,		0,		0,
-		/* IP1_17 [1] */
-		FN_CS0,		FN_HSPI_RX1_B,
-		/* IP1_16_15 [2] */
-		FN_CLKOUT,	FN_HSPI_TX1_B,	FN_PWM0_B,	0,
-		/* IP1_14_11 [4] */
-		FN_SD1_WP_A,	FN_MMC_D7,	0,		FN_A25,
-		FN_DACK1_A,	0,		FN_HCTS0_B,	FN_RX3_C,
-		FN_TS_SDAT0_A,	0,		0,		0,
-		0,		0,		0,		0,
-		/* IP1_10_8 [3] */
-		FN_SD1_CD_A,	FN_MMC_D6,	0,		FN_A24,
-		FN_DREQ1_A,	0,		FN_HRX0_B,	FN_TS_SPSYNC0_A,
-		/* IP1_7_5 [3] */
-		FN_A23,		FN_HTX0_B,	FN_TX2_B,	FN_DACK2_A,
-		FN_TS_SDEN0_A,	0,		0,		0,
-		/* IP1_4_2 [3] */
-		FN_A22,		FN_HRTS0_B,	FN_RX2_B,	FN_DREQ2_A,
-		0,		0,		0,		0,
-		/* IP1_1 [1] */
-		FN_A21,		FN_HSPI_CLK1_B,
-		/* IP1_0 [1] */
-		FN_A20,		FN_HSPI_CS1_B,
-		))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
-			     GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-				   1, 1, 1, 3, 2, 3, 3, 3, 3),
-			     GROUP(
-		/* IP2_31 [1] */
-		FN_MLB_CLK,	FN_IRQ1_A,
-		/* IP2_30 [1] */
-		FN_RD_WR_B,	FN_IRQ0,
-		/* IP2_29 [1] */
-		FN_D11,		0,
-		/* IP2_28 [1] */
-		FN_D10,		0,
-		/* IP2_27 [1] */
-		FN_D9,		0,
-		/* IP2_26 [1] */
-		FN_D8,		0,
-		/* IP2_25 [1] */
-		FN_D7,		0,
-		/* IP2_24 [1] */
-		FN_D6,		0,
-		/* IP2_23 [1] */
-		FN_D5,		0,
-		/* IP2_22 [1] */
-		FN_D4,		0,
-		/* IP2_21 [1] */
-		FN_D3,		0,
-		/* IP2_20 [1] */
-		FN_D2,		0,
-		/* IP2_19 [1] */
-		FN_D1,		0,
-		/* IP2_18 [1] */
-		FN_D0,		0,
-		/* IP2_17 [1] */
-		FN_EX_WAIT0,	FN_PWM0_C,
-		/* IP2_16_14 [3] */
-		FN_DACK0,	0,	0,	FN_TX3_A,
-		FN_DRACK0,	0,	0,	0,
-		/* IP2_13_12 [2] */
-		FN_DREQ0_A,	0,	0,	FN_RX3_A,
-		/* IP2_11_9 [3] */
-		FN_SD1_DAT1_A,	FN_MMC_D1,	0,	FN_ATAWR0_A,
-		FN_EX_CS5,	FN_EX_WAIT2_A,	0,	0,
-		/* IP2_8_6 [3] */
-		FN_SD1_DAT0_A,	FN_MMC_D0,	0,	FN_ATARD0,
-		FN_EX_CS4,	FN_EX_WAIT1_A,	0,	0,
-		/* IP2_5_3 [3] */
-		FN_SD1_CMD_A,	FN_MMC_CMD,	0,	FN_ATACS10,
-		FN_EX_CS3,	0,		0,	0,
-		/* IP2_2_0 [3] */
-		FN_SD1_CLK_A,	FN_MMC_CLK,	0,	FN_ATACS00,
-		FN_EX_CS2,	0,		0,	0,
-		))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
-			     GROUP(1, 1, 1, 1, 1, 3, 3, 2, 3, 3, 3, 2,
-				   3, 3, 2),
-			     GROUP(
-		/* IP3_31 [1] */
-		FN_DU0_DR6,	FN_LCDOUT6,
-		/* IP3_30 [1] */
-		FN_DU0_DR5,	FN_LCDOUT5,
-		/* IP3_29 [1] */
-		FN_DU0_DR4,	FN_LCDOUT4,
-		/* IP3_28 [1] */
-		FN_DU0_DR3,	FN_LCDOUT3,
-		/* IP3_27 [1] */
-		FN_DU0_DR2,	FN_LCDOUT2,
-		/* IP3_26_24 [3] */
-		FN_SSI_WS4,		FN_DU0_DR1,	FN_LCDOUT1,	FN_AUDATA3,
-		FN_ARM_TRACEDATA_3,	FN_SCL3_C,	FN_ADICHS2,	FN_TS_SPSYNC0_B,
-		/* IP3_23_21 [3] */
-		FN_SSI_SCK4,		FN_DU0_DR0,	FN_LCDOUT0,	FN_AUDATA2,
-		FN_ARM_TRACEDATA_2,	FN_SDA3_C,	FN_ADICHS1,	FN_TS_SDEN0_B,
-		/* IP3_20_19 [2] */
-		FN_SD1_DAT3_B,	FN_HRTS0_A,	FN_RTS0,	0,
-		/* IP3_18_16 [3] */
-		FN_SD1_DAT2_B,	FN_HCTS0_A,	FN_CTS0,	0,
-		0,		0,		0,		0,
-		/* IP3_15_13 [3] */
-		FN_SD1_DAT1_B,	FN_HSCK0,	FN_SCK0,	FN_SCL3_B,
-		0,		0,		0,		0,
-		/* IP3_12_10 [3] */
-		FN_SD1_DAT0_B,	FN_HRX0_A,	FN_RX0_A,	0,
-		0,		0,		0,		0,
-		/* IP3_9_8 [2] */
-		FN_SD1_CLK_B,	FN_HTX0_A,	FN_TX0_A,	0,
-		/* IP3_7_5 [3] */
-		FN_SD1_CMD_B,	FN_SCIF_CLK,	FN_AUDIO_CLKOUT_B,	FN_CAN_CLK_B,
-		FN_SDA3_B,	0,		0,			0,
-		/* IP3_4_2 [3] */
-		FN_MLB_DAT,	FN_TX5_B,	FN_SCL3_A,	FN_IRQ3_A,
-		FN_SDSELF_B,	0,		0,		0,
-		/* IP3_1_0 [2] */
-		FN_MLB_SIG,	FN_RX5_B,	FN_SDA3_A,	FN_IRQ2_A,
-		))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
-			     GROUP(1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1,
-				   3, 3, 1),
-			     GROUP(
-		/* IP4_31 [1] */
-		0,	0,
-		/* IP4_30_29 [2] */
-		FN_VI0_R4_B,	FN_DU0_DB4,	FN_LCDOUT20,	0,
-		/* IP4_28_27 [2] */
-		FN_VI0_R3_B,	FN_DU0_DB3,	FN_LCDOUT19,	0,
-		/* IP4_26_25 [2] */
-		FN_VI0_R2_B,	FN_DU0_DB2,	FN_LCDOUT18,	0,
-		/* IP4_24_21 [4] */
-		FN_AUDIO_CLKC,	FN_VI0_R1_B,		FN_DU0_DB1,	FN_LCDOUT17,
-		FN_AUDATA7,	FN_ARM_TRACEDATA_7,	FN_GPSIN_A,	0,
-		FN_ADICS_SAMP,	FN_TS_SCK0_B,		0,		0,
-		0,		0,			0,		0,
-		/* IP4_20_17 [4] */
-		FN_SSI_SCK2_B,	FN_VI0_R0_B,		FN_DU0_DB0,	FN_LCDOUT16,
-		FN_AUDATA6,	FN_ARM_TRACEDATA_6,	FN_GPSCLK_A,	FN_PWM0_A,
-		FN_ADICLK,	FN_TS_SDAT0_B,		0,		0,
-		0,		0,			0,		0,
-		/* IP4_16_15 [2] */
-		FN_DU0_DG7,	FN_LCDOUT15,	FN_TX4_A,	0,
-		/* IP4_14_13 [2] */
-		FN_DU0_DG6,	FN_LCDOUT14,	FN_RX4_A,	0,
-		/* IP4_12_11 [2] */
-		FN_DU0_DG5,	FN_LCDOUT13,	FN_TX0_B,	0,
-		/* IP4_10_9 [2] */
-		FN_DU0_DG4,	FN_LCDOUT12,	FN_RX0_B,	0,
-		/* IP4_8 [1] */
-		FN_DU0_DG3,	FN_LCDOUT11,
-		/* IP4_7 [1] */
-		FN_DU0_DG2,	FN_LCDOUT10,
-		/* IP4_6_4 [3] */
-		FN_DU0_DG1,	FN_LCDOUT9,	FN_AUDATA5,	FN_ARM_TRACEDATA_5,
-		FN_RX1_D,	FN_CAN0_RX_A,	FN_ADIDATA,	0,
-		/* IP4_3_1 [3] */
-		FN_DU0_DG0,	FN_LCDOUT8,	FN_AUDATA4,	FN_ARM_TRACEDATA_4,
-		FN_TX1_D,	FN_CAN0_TX_A,	FN_ADICHS0,	0,
-		/* IP4_0 [1] */
-		FN_DU0_DR7,	FN_LCDOUT7,
-		))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
-			     GROUP(1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1,
-				   1, 2, 2, 2),
-			     GROUP(
-
-		/* IP5_31 [1] */
-		0, 0,
-		/* IP5_30_29 [2] */
-		FN_SSI_SDATA7,	FN_HSPI_TX0_B,	FN_RX2_A,	FN_CAN0_RX_B,
-		/* IP5_28_26 [3] */
-		FN_SSI_SDATA8,	FN_SSI_SCK2_A,	FN_HSPI_CS0_B,	FN_TX2_A,
-		FN_CAN0_TX_B,	0,		0,		0,
-		/* IP5_25_23 [3] */
-		FN_SD1_WP_B,	FN_SSI_WS78,	FN_HSPI_CLK0_B,	FN_RX1_B,
-		FN_CAN_CLK_D,	0,		0,		0,
-		/* IP5_22_21 [2] */
-		FN_SD1_CD_B,	FN_SSI_SCK78,	FN_HSPI_RX0_B,	FN_TX1_B,
-		/* IP5_20_18 [3] */
-		FN_SSI_WS1_A,		FN_DU0_CDE,	FN_QPOLB,	FN_AUDSYNC,
-		FN_ARM_TRACECTL,	FN_FMIN_D,	0,		0,
-		/* IP5_17_15 [3] */
-		FN_SSI_SCK1_A,		FN_DU0_DISP,	FN_QPOLA,	FN_AUDCK,
-		FN_ARM_TRACECLK,	FN_BPFCLK_D,	0,		0,
-		/* IP5_14_13 [2] */
-		FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,	FN_QCPV_QDE,
-		FN_FMCLK_D,				0,
-		/* IP5_12 [1] */
-		FN_DU0_EXVSYNC_DU0_VSYNC,	FN_QSTB_QHE,
-		/* IP5_11_10 [2] */
-		FN_SSI_WS2_B,	FN_DU0_EXHSYNC_DU0_HSYNC,
-		FN_QSTH_QHS,	0,
-		/* IP5_9_8 [2] */
-		FN_DU0_DOTCLKO_UT1,	FN_QSTVB_QVE,
-		FN_AUDIO_CLKOUT_A,	FN_REMOCON_C,
-		/* IP5_7 [1] */
-		FN_DU0_DOTCLKO_UT0,	FN_QCLK,
-		/* IP5_6 [1] */
-		FN_DU0_DOTCLKIN,	FN_QSTVA_QVS,
-		/* IP5_5_4 [2] */
-		FN_VI1_DATA11_B,	FN_DU0_DB7,	FN_LCDOUT23,	0,
-		/* IP5_3_2 [2] */
-		FN_VI1_DATA10_B,	FN_DU0_DB6,	FN_LCDOUT22,	0,
-		/* IP5_1_0 [2] */
-		FN_VI0_R5_B,		FN_DU0_DB5,	FN_LCDOUT21,	0,
-		))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
-			     GROUP(2, 2, 2, 2, 2, 1, 2, 2, 1, 2, 1, 2,
-				   1, 1, 1, 1, 2, 3, 2),
-			     GROUP(
-		/* IP6_31_30 [2] */
-		FN_SD0_DAT2,	0,	FN_SUB_TDI,	0,
-		/* IP6_29_28 [2] */
-		FN_SD0_DAT1,	0,	FN_SUB_TCK,	0,
-		/* IP6_27_26 [2] */
-		FN_SD0_DAT0,	0,	FN_SUB_TMS,	0,
-		/* IP6_25_24 [2] */
-		FN_SD0_CMD,	0,	FN_SUB_TRST,	0,
-		/* IP6_23_22 [2] */
-		FN_SD0_CLK,	0,	FN_SUB_TDO,	0,
-		/* IP6_21 [1] */
-		FN_SSI_SDATA0,		FN_ARM_TRACEDATA_15,
-		/* IP6_20_19 [2] */
-		FN_SSI_SDATA1,		FN_ARM_TRACEDATA_14,
-		FN_SCL1_A,		FN_SCK2_A,
-		/* IP6_18_17 [2] */
-		FN_SSI_SDATA2,		FN_HSPI_CS2_A,
-		FN_ARM_TRACEDATA_13,	FN_SDA1_A,
-		/* IP6_16 [1] */
-		FN_SSI_WS012,		FN_ARM_TRACEDATA_12,
-		/* IP6_15_14 [2] */
-		FN_SSI_SCK012,		FN_ARM_TRACEDATA_11,
-		FN_TX0_D,		0,
-		/* IP6_13 [1] */
-		FN_SSI_SDATA3,		FN_ARM_TRACEDATA_10,
-		/* IP6_12_11 [2] */
-		FN_SSI_SDATA4,		FN_SSI_WS2_A,
-		FN_ARM_TRACEDATA_9,	0,
-		/* IP6_10 [1] */
-		FN_SSI_WS34,		FN_ARM_TRACEDATA_8,
-		/* IP6_9 [1] */
-		FN_SSI_SDATA5,		FN_RX0_D,
-		/* IP6_8 [1] */
-		FN_SSI_WS5,		FN_TX4_C,
-		/* IP6_7 [1] */
-		FN_SSI_SCK5,		FN_RX4_C,
-		/* IP6_6_5 [2] */
-		FN_SSI_SDATA6,		FN_HSPI_TX2_A,
-		FN_FMIN_B,		0,
-		/* IP6_4_2 [3] */
-		FN_SSI_WS6,		FN_HSPI_CLK2_A,
-		FN_BPFCLK_B,		FN_CAN1_RX_B,
-		0,	0,	0,	0,
-		/* IP6_1_0 [2] */
-		FN_SSI_SCK6,		FN_HSPI_RX2_A,
-		FN_FMCLK_B,		FN_CAN1_TX_B,
-		))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
-			     GROUP(3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2),
-			     GROUP(
-
-		/* IP7_31_29 [3] */
-		FN_VI0_HSYNC,	FN_SD2_CD_B,	FN_VI1_DATA2,	FN_DU1_DR2,
-		0,		FN_HSPI_CS1_A,	FN_RX3_B,	0,
-		/* IP7_28_25 [4] */
-		FN_VI0_FIELD,	FN_SD2_DAT3_B,	FN_VI0_R3_C,	FN_VI1_DATA1,
-		FN_DU1_DG7,	0,		FN_HSPI_CLK1_A,	FN_TX4_B,
-		0,	0,	0,	0,
-		0,	0,	0,	0,
-		/* IP7_24_22 [3] */
-		FN_VI0_CLKENB,	FN_SD2_DAT2_B,	FN_VI1_DATA0,	FN_DU1_DG6,
-		0,		FN_HSPI_RX1_A,	FN_RX4_B,	0,
-		/* IP7_21 [1] */
-		FN_VI0_CLK,	FN_CAN_CLK_A,
-		/* IP7_20_18 [3] */
-		FN_TCLK0,	FN_HSCK1_A,	FN_FMIN_A,	0,
-		FN_IRQ2_C,	FN_CTS1_C,	FN_SPEEDIN,	0,
-		/* IP7_17_15 [3] */
-		FN_VI1_VSYNC,	FN_HSPI_TX0,	FN_HCTS1_A,	FN_BPFCLK_A,
-		0,		FN_TX1_C,	0,		0,
-		/* IP7_14_12 [3] */
-		FN_VI1_HSYNC,	FN_HSPI_RX0_A,	FN_HRTS1_A,	FN_FMCLK_A,
-		0,		FN_RX1_C,	0,		0,
-		/* IP7_11_9 [3] */
-		FN_VI1_FIELD,	FN_HSPI_CS0_A,	FN_HRX1_A,	0,
-		FN_SCK1_C,	0,		0,		0,
-		/* IP7_8_6 [3] */
-		FN_VI1_CLKENB,	FN_HSPI_CLK0_A,	FN_HTX1_A,	0,
-		FN_RTS1_C,	0,		0,		0,
-		/* IP7_5_4 [2] */
-		FN_SD0_WP,	0,		FN_RX5_A,	0,
-		/* IP7_3_2 [2] */
-		FN_SD0_CD,	0,		FN_TX5_A,	0,
-		/* IP7_1_0 [2] */
-		FN_SD0_DAT3,	0,		FN_IRQ1_B,	0,
-		))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
-			     GROUP(1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3),
-			     GROUP(
-		/* IP8_31 [1] */
-		0, 0,
-		/* IP8_30 [1] */
-		0, 0,
-		/* IP8_29_27 [3] */
-		FN_VI0_G3,	FN_SD2_CMD_B,	FN_VI1_DATA5,	FN_DU1_DR5,
-		0,		FN_HRX1_B,	0,		0,
-		/* IP8_26_24 [3] */
-		FN_VI0_G2,	FN_SD2_CLK_B,	FN_VI1_DATA4,	FN_DU1_DR4,
-		0,		FN_HTX1_B,	0,		0,
-		/* IP8_23_22 [2] */
-		FN_VI0_DATA7_VI0_G1,	FN_DU1_DB5,
-		FN_RTS1_A,		0,
-		/* IP8_21_19 [3] */
-		FN_VI0_DATA6_VI0_G0,	FN_DU1_DB4,
-		FN_CTS1_A,		FN_PWM5,
-		0,	0,	0,	0,
-		/* IP8_18_16 [3] */
-		FN_VI0_DATA5_VI0_B5,	FN_DU1_DB3,	FN_SCK1_A,	FN_PWM4,
-		0,			FN_HSCK1_B,	0,		0,
-		/* IP8_15_14 [2] */
-		FN_VI0_DATA4_VI0_B4,	FN_DU1_DB2,	FN_RX1_A,	0,
-		/* IP8_13_11 [3] */
-		FN_VI0_DATA3_VI0_B3,	FN_DU1_DG5,	FN_TX1_A,	FN_TX0_C,
-		0,			 0,		0,		0,
-		/* IP8_10_9 [2] */
-		FN_VI0_DATA2_VI0_B2,	FN_DU1_DG4,	FN_RX0_C,	0,
-		/* IP8_8_6 [3] */
-		FN_VI0_DATA1_VI0_B1,	FN_DU1_DG3,	FN_IRQ3_B,	FN_TX3_D,
-		0,			 0,		0,		0,
-		/* IP8_5_3 [3] */
-		FN_VI0_DATA0_VI0_B0,	FN_DU1_DG2,	FN_IRQ2_B,	FN_RX3_D,
-		0,			 0,		0,		0,
-		/* IP8_2_0 [3] */
-		FN_VI0_VSYNC,		FN_SD2_WP_B,	FN_VI1_DATA3,	FN_DU1_DR3,
-		0,			FN_HSPI_TX1_A,	FN_TX3_B,	0,
-		))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
-			     GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
-			     GROUP(
-		/* IP9_31 [1] */
-		0, 0,
-		/* IP9_30 [1] */
-		0, 0,
-		/* IP9_29_27 [3] */
-		FN_VI1_DATA11_A,	FN_DU1_EXHSYNC_DU1_HSYNC,
-		FN_ETH_RXD1,		FN_FMIN_C,
-		0,			FN_RX2_D,
-		FN_SCL2_C,		0,
-		/* IP9_26_24 [3] */
-		FN_VI1_DATA10_A,	FN_DU1_DOTCLKOUT,
-		FN_ETH_RXD0,		FN_BPFCLK_C,
-		0,			FN_TX2_D,
-		FN_SDA2_C,		0,
-		/* IP9_23_21 [3] */
-		FN_VI0_R5_A,	0,		FN_ETH_RX_ER,	FN_FMCLK_C,
-		FN_IERX,	FN_RX2_C,	0,		0,
-		/* IP9_20_18 [3] */
-		FN_VI0_R4_A,	FN_ETH_TX_EN,	0,		0,
-		FN_IETX,	FN_TX2_C,	0,		0,
-		/* IP9_17_15 [3] */
-		FN_VI0_R3_A,	FN_ETH_CRS_DV,	0,		FN_IECLK,
-		FN_SCK2_C,	0,		0,		0,
-		/* IP9_14_12 [3] */
-		FN_VI0_R2_A,	FN_VI1_DATA9,	FN_DU1_DB7,	FN_ETH_TXD1,
-		0,		FN_PWM3,	0,		0,
-		/* IP9_11_9 [3] */
-		FN_VI0_R1_A,	FN_VI1_DATA8,	FN_DU1_DB6,	FN_ETH_TXD0,
-		0,		FN_PWM2,	FN_TCLK1,	0,
-		/* IP9_8_6 [3] */
-		FN_VI0_R0_A,	FN_VI1_CLK,	FN_ETH_REF_CLK,	FN_DU1_DOTCLKIN,
-		0,		0,		0,		0,
-		/* IP9_5_3 [3] */
-		FN_VI0_G5,	FN_SD2_DAT1_B,	FN_VI1_DATA7,	FN_DU1_DR7,
-		0,		FN_HCTS1_B,	0,		0,
-		/* IP9_2_0 [3] */
-		FN_VI0_G4,	FN_SD2_DAT0_B,	FN_VI1_DATA6,	FN_DU1_DR6,
-		0,		FN_HRTS1_B,	0,		0,
-		))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
-			     GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4,
-				   3, 3, 3),
-			     GROUP(
-
-		/* IP10_31 [1] */
-		0, 0,
-		/* IP10_30 [1] */
-		0, 0,
-		/* IP10_29 [1] */
-		0, 0,
-		/* IP10_28 [1] */
-		0, 0,
-		/* IP10_27 [1] */
-		0, 0,
-		/* IP10_26 [1] */
-		0, 0,
-		/* IP10_25 [1] */
-		0, 0,
-		/* IP10_24_22 [3] */
-		FN_SD2_WP_A,	FN_VI1_DATA15,	FN_EX_WAIT2_B,	FN_DACK0_B,
-		FN_HSPI_TX2_B,	FN_CAN_CLK_C,	0,		0,
-		/* IP10_21_19 [3] */
-		FN_SD2_CD_A,	FN_VI1_DATA14,	FN_EX_WAIT1_B,	FN_DREQ0_B,
-		FN_HSPI_RX2_B,	FN_REMOCON_A,	0,		0,
-		/* IP10_18_16 [3] */
-		FN_SD2_DAT3_A,	FN_VI1_DATA13,	FN_DACK2_B,	FN_ATAG1,
-		FN_HSPI_CS2_B,	FN_GPSIN_B,	0,		0,
-		/* IP10_15_13 [3] */
-		FN_SD2_DAT2_A,	FN_VI1_DATA12,	FN_DREQ2_B,	FN_ATADIR1,
-		FN_HSPI_CLK2_B,	FN_GPSCLK_B,	0,		0,
-		/* IP10_12_9 [4] */
-		FN_SD2_DAT1_A,	FN_DU1_CDE,	FN_ATACS11,	FN_DACK1_B,
-		FN_ETH_MAGIC,	FN_CAN1_TX_A,	0,		FN_PWM6,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		/* IP10_8_6 [3] */
-		FN_SD2_DAT0_A,	FN_DU1_DISP,	FN_ATACS01,	FN_DREQ1_B,
-		FN_ETH_LINK,	FN_CAN1_RX_A,	0,		0,
-		/* IP10_5_3 [3] */
-		FN_SD2_CMD_A,	FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
-		FN_ATAWR1,	FN_ETH_MDIO,
-		FN_SCL1_B,	0,
-		0,		0,
-		/* IP10_2_0 [3] */
-		FN_SD2_CLK_A,	FN_DU1_EXVSYNC_DU1_VSYNC,
-		FN_ATARD1,	FN_ETH_MDC,
-		FN_SDA1_B,	0,
-		0,		0,
-		))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32,
-			     GROUP(1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,
-				   1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
-			     GROUP(
-
-		/* SEL 31  [1] */
-		0, 0,
-		/* SEL_30 (SCIF5) [1] */
-		FN_SEL_SCIF5_A,		FN_SEL_SCIF5_B,
-		/* SEL_29_28 (SCIF4) [2] */
-		FN_SEL_SCIF4_A,		FN_SEL_SCIF4_B,
-		FN_SEL_SCIF4_C,		0,
-		/* SEL_27_26 (SCIF3) [2] */
-		FN_SEL_SCIF3_A,		FN_SEL_SCIF3_B,
-		FN_SEL_SCIF3_C,		FN_SEL_SCIF3_D,
-		/* SEL_25_23 (SCIF2) [3] */
-		FN_SEL_SCIF2_A,		FN_SEL_SCIF2_B,
-		FN_SEL_SCIF2_C,		FN_SEL_SCIF2_D,
-		FN_SEL_SCIF2_E,		0,
-		0,			0,
-		/* SEL_22_21 (SCIF1) [2] */
-		FN_SEL_SCIF1_A,		FN_SEL_SCIF1_B,
-		FN_SEL_SCIF1_C,		FN_SEL_SCIF1_D,
-		/* SEL_20_19 (SCIF0) [2] */
-		FN_SEL_SCIF0_A,		FN_SEL_SCIF0_B,
-		FN_SEL_SCIF0_C,		FN_SEL_SCIF0_D,
-		/* SEL_18 [1] */
-		0, 0,
-		/* SEL_17 (SSI2) [1] */
-		FN_SEL_SSI2_A,		FN_SEL_SSI2_B,
-		/* SEL_16 (SSI1) [1] */
-		FN_SEL_SSI1_A,		FN_SEL_SSI1_B,
-		/* SEL_15 (VI1) [1] */
-		FN_SEL_VI1_A,		FN_SEL_VI1_B,
-		/* SEL_14_13 (VI0) [2] */
-		FN_SEL_VI0_A,		FN_SEL_VI0_B,
-		FN_SEL_VI0_C,		FN_SEL_VI0_D,
-		/* SEL_12 [1] */
-		0, 0,
-		/* SEL_11 (SD2) [1] */
-		FN_SEL_SD2_A,		FN_SEL_SD2_B,
-		/* SEL_10 (SD1) [1] */
-		FN_SEL_SD1_A,		FN_SEL_SD1_B,
-		/* SEL_9 (IRQ3) [1] */
-		FN_SEL_IRQ3_A,		FN_SEL_IRQ3_B,
-		/* SEL_8_7 (IRQ2) [2] */
-		FN_SEL_IRQ2_A,		FN_SEL_IRQ2_B,
-		FN_SEL_IRQ2_C,		0,
-		/* SEL_6 (IRQ1) [1] */
-		FN_SEL_IRQ1_A,		FN_SEL_IRQ1_B,
-		/* SEL_5 [1] */
-		0, 0,
-		/* SEL_4 (DREQ2) [1] */
-		FN_SEL_DREQ2_A,		FN_SEL_DREQ2_B,
-		/* SEL_3 (DREQ1) [1] */
-		FN_SEL_DREQ1_A,		FN_SEL_DREQ1_B,
-		/* SEL_2 (DREQ0) [1] */
-		FN_SEL_DREQ0_A,		FN_SEL_DREQ0_B,
-		/* SEL_1 (WAIT2) [1] */
-		FN_SEL_WAIT2_A,		FN_SEL_WAIT2_B,
-		/* SEL_0 (WAIT1) [1] */
-		FN_SEL_WAIT1_A,		FN_SEL_WAIT1_B,
-		))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32,
-			     GROUP(1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1,
-				   1, 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1),
-			     GROUP(
-
-		/* SEL_31 [1] */
-		0, 0,
-		/* SEL_30 [1] */
-		0, 0,
-		/* SEL_29 [1] */
-		0, 0,
-		/* SEL_28 [1] */
-		0, 0,
-		/* SEL_27 (CAN1) [1] */
-		FN_SEL_CAN1_A,		FN_SEL_CAN1_B,
-		/* SEL_26 (CAN0) [1] */
-		FN_SEL_CAN0_A,		FN_SEL_CAN0_B,
-		/* SEL_25_24 (CANCLK) [2] */
-		FN_SEL_CANCLK_A,	FN_SEL_CANCLK_B,
-		FN_SEL_CANCLK_C,	FN_SEL_CANCLK_D,
-		/* SEL_23 (HSCIF1) [1] */
-		FN_SEL_HSCIF1_A,	FN_SEL_HSCIF1_B,
-		/* SEL_22 (HSCIF0) [1] */
-		FN_SEL_HSCIF0_A,	FN_SEL_HSCIF0_B,
-		/* SEL_21 [1] */
-		0, 0,
-		/* SEL_20 [1] */
-		0, 0,
-		/* SEL_19 [1] */
-		0, 0,
-		/* SEL_18 [1] */
-		0, 0,
-		/* SEL_17 [1] */
-		0, 0,
-		/* SEL_16 [1] */
-		0, 0,
-		/* SEL_15 [1] */
-		0, 0,
-		/* SEL_14_13 (REMOCON) [2] */
-		FN_SEL_REMOCON_A,	FN_SEL_REMOCON_B,
-		FN_SEL_REMOCON_C,	0,
-		/* SEL_12_11 (FM) [2] */
-		FN_SEL_FM_A,		FN_SEL_FM_B,
-		FN_SEL_FM_C,		FN_SEL_FM_D,
-		/* SEL_10_9 (GPS) [2] */
-		FN_SEL_GPS_A,		FN_SEL_GPS_B,
-		FN_SEL_GPS_C,		0,
-		/* SEL_8 (TSIF0) [1] */
-		FN_SEL_TSIF0_A,		FN_SEL_TSIF0_B,
-		/* SEL_7 (HSPI2) [1] */
-		FN_SEL_HSPI2_A,		FN_SEL_HSPI2_B,
-		/* SEL_6 (HSPI1) [1] */
-		FN_SEL_HSPI1_A,		FN_SEL_HSPI1_B,
-		/* SEL_5 (HSPI0) [1] */
-		FN_SEL_HSPI0_A,		FN_SEL_HSPI0_B,
-		/* SEL_4_3 (I2C3) [2] */
-		FN_SEL_I2C3_A,		FN_SEL_I2C3_B,
-		FN_SEL_I2C3_C,		0,
-		/* SEL_2_1 (I2C2) [2] */
-		FN_SEL_I2C2_A,		FN_SEL_I2C2_B,
-		FN_SEL_I2C2_C,		0,
-		/* SEL_0 (I2C1) [1] */
-		FN_SEL_I2C1_A,		FN_SEL_I2C1_B,
-		))
-	},
-	{ },
-};
-
-static const struct pinmux_bias_reg pinmux_bias_regs[] = {
-	{ PINMUX_BIAS_REG("PUPR0", 0x100, "N/A", 0) {
-		[ 0] = RCAR_GP_PIN(0,  6),	/* A0 */
-		[ 1] = RCAR_GP_PIN(0,  7),	/* A1 */
-		[ 2] = RCAR_GP_PIN(0,  8),	/* A2 */
-		[ 3] = RCAR_GP_PIN(0,  9),	/* A3 */
-		[ 4] = RCAR_GP_PIN(0, 10),	/* A4 */
-		[ 5] = RCAR_GP_PIN(0, 11),	/* A5 */
-		[ 6] = RCAR_GP_PIN(0, 12),	/* A6 */
-		[ 7] = RCAR_GP_PIN(0, 13),	/* A7 */
-		[ 8] = RCAR_GP_PIN(0, 14),	/* A8 */
-		[ 9] = RCAR_GP_PIN(0, 15),	/* A9 */
-		[10] = RCAR_GP_PIN(0, 16),	/* A10 */
-		[11] = RCAR_GP_PIN(0, 17),	/* A11 */
-		[12] = RCAR_GP_PIN(0, 18),	/* A12 */
-		[13] = RCAR_GP_PIN(0, 19),	/* A13 */
-		[14] = RCAR_GP_PIN(0, 20),	/* A14 */
-		[15] = RCAR_GP_PIN(0, 21),	/* A15 */
-		[16] = RCAR_GP_PIN(0, 22),	/* A16 */
-		[17] = RCAR_GP_PIN(0, 23),	/* A17 */
-		[18] = RCAR_GP_PIN(0, 24),	/* A18 */
-		[19] = RCAR_GP_PIN(0, 25),	/* A19 */
-		[20] = RCAR_GP_PIN(0, 26),	/* A20 */
-		[21] = RCAR_GP_PIN(0, 27),	/* A21 */
-		[22] = RCAR_GP_PIN(0, 28),	/* A22 */
-		[23] = RCAR_GP_PIN(0, 29),	/* A23 */
-		[24] = RCAR_GP_PIN(0, 30),	/* A24 */
-		[25] = RCAR_GP_PIN(0, 31),	/* A25 */
-		[26] = RCAR_GP_PIN(1,  3),	/* /EX_CS0 */
-		[27] = RCAR_GP_PIN(1,  4),	/* /EX_CS1 */
-		[28] = RCAR_GP_PIN(1,  5),	/* /EX_CS2 */
-		[29] = RCAR_GP_PIN(1,  6),	/* /EX_CS3 */
-		[30] = RCAR_GP_PIN(1,  7),	/* /EX_CS4 */
-		[31] = RCAR_GP_PIN(1,  8),	/* /EX_CS5 */
-	} },
-	{ PINMUX_BIAS_REG("PUPR1", 0x104, "N/A", 0) {
-		[ 0] = RCAR_GP_PIN(0,  0),	/* /PRESETOUT	*/
-		[ 1] = RCAR_GP_PIN(0,  5),	/* /BS		*/
-		[ 2] = RCAR_GP_PIN(1,  0),	/* RD//WR	*/
-		[ 3] = RCAR_GP_PIN(1,  1),	/* /WE0		*/
-		[ 4] = RCAR_GP_PIN(1,  2),	/* /WE1		*/
-		[ 5] = RCAR_GP_PIN(1, 11),	/* EX_WAIT0	*/
-		[ 6] = RCAR_GP_PIN(1,  9),	/* DREQ0	*/
-		[ 7] = RCAR_GP_PIN(1, 10),	/* DACK0	*/
-		[ 8] = RCAR_GP_PIN(1, 12),	/* IRQ0		*/
-		[ 9] = RCAR_GP_PIN(1, 13),	/* IRQ1		*/
-		[10] = SH_PFC_PIN_NONE,
-		[11] = SH_PFC_PIN_NONE,
-		[12] = SH_PFC_PIN_NONE,
-		[13] = SH_PFC_PIN_NONE,
-		[14] = SH_PFC_PIN_NONE,
-		[15] = SH_PFC_PIN_NONE,
-		[16] = SH_PFC_PIN_NONE,
-		[17] = SH_PFC_PIN_NONE,
-		[18] = SH_PFC_PIN_NONE,
-		[19] = SH_PFC_PIN_NONE,
-		[20] = SH_PFC_PIN_NONE,
-		[21] = SH_PFC_PIN_NONE,
-		[22] = SH_PFC_PIN_NONE,
-		[23] = SH_PFC_PIN_NONE,
-		[24] = SH_PFC_PIN_NONE,
-		[25] = SH_PFC_PIN_NONE,
-		[26] = SH_PFC_PIN_NONE,
-		[27] = SH_PFC_PIN_NONE,
-		[28] = SH_PFC_PIN_NONE,
-		[29] = SH_PFC_PIN_NONE,
-		[30] = SH_PFC_PIN_NONE,
-		[31] = SH_PFC_PIN_NONE,
-	} },
-	{ PINMUX_BIAS_REG("PUPR2", 0x108, "N/A", 0) {
-		[ 0] = RCAR_GP_PIN(1, 22),	/* DU0_DR0	*/
-		[ 1] = RCAR_GP_PIN(1, 23),	/* DU0_DR1	*/
-		[ 2] = RCAR_GP_PIN(1, 24),	/* DU0_DR2	*/
-		[ 3] = RCAR_GP_PIN(1, 25),	/* DU0_DR3	*/
-		[ 4] = RCAR_GP_PIN(1, 26),	/* DU0_DR4	*/
-		[ 5] = RCAR_GP_PIN(1, 27),	/* DU0_DR5	*/
-		[ 6] = RCAR_GP_PIN(1, 28),	/* DU0_DR6	*/
-		[ 7] = RCAR_GP_PIN(1, 29),	/* DU0_DR7	*/
-		[ 8] = RCAR_GP_PIN(1, 30),	/* DU0_DG0	*/
-		[ 9] = RCAR_GP_PIN(1, 31),	/* DU0_DG1	*/
-		[10] = RCAR_GP_PIN(2,  0),	/* DU0_DG2	*/
-		[11] = RCAR_GP_PIN(2,  1),	/* DU0_DG3	*/
-		[12] = RCAR_GP_PIN(2,  2),	/* DU0_DG4	*/
-		[13] = RCAR_GP_PIN(2,  3),	/* DU0_DG5	*/
-		[14] = RCAR_GP_PIN(2,  4),	/* DU0_DG6	*/
-		[15] = RCAR_GP_PIN(2,  5),	/* DU0_DG7	*/
-		[16] = RCAR_GP_PIN(2,  6),	/* DU0_DB0	*/
-		[17] = RCAR_GP_PIN(2,  7),	/* DU0_DB1	*/
-		[18] = RCAR_GP_PIN(2,  8),	/* DU0_DB2	*/
-		[19] = RCAR_GP_PIN(2,  9),	/* DU0_DB3	*/
-		[20] = RCAR_GP_PIN(2, 10),	/* DU0_DB4	*/
-		[21] = RCAR_GP_PIN(2, 11),	/* DU0_DB5	*/
-		[22] = RCAR_GP_PIN(2, 12),	/* DU0_DB6	*/
-		[23] = RCAR_GP_PIN(2, 13),	/* DU0_DB7	*/
-		[24] = RCAR_GP_PIN(2, 14),	/* DU0_DOTCLKIN	*/
-		[25] = RCAR_GP_PIN(2, 15),	/* DU0_DOTCLKOUT0 */
-		[26] = RCAR_GP_PIN(2, 17),	/* DU0_HSYNC	*/
-		[27] = RCAR_GP_PIN(2, 18),	/* DU0_VSYNC	*/
-		[28] = RCAR_GP_PIN(2, 19),	/* DU0_EXODDF	*/
-		[29] = RCAR_GP_PIN(2, 20),	/* DU0_DISP	*/
-		[30] = RCAR_GP_PIN(2, 21),	/* DU0_CDE	*/
-		[31] = RCAR_GP_PIN(2, 16),	/* DU0_DOTCLKOUT1 */
-	} },
-	{ PINMUX_BIAS_REG("PUPR3", 0x10c, "N/A", 0) {
-		[ 0] = RCAR_GP_PIN(3, 24),	/* VI0_CLK	*/
-		[ 1] = RCAR_GP_PIN(3, 25),	/* VI0_CLKENB	*/
-		[ 2] = RCAR_GP_PIN(3, 26),	/* VI0_FIELD	*/
-		[ 3] = RCAR_GP_PIN(3, 27),	/* /VI0_HSYNC	*/
-		[ 4] = RCAR_GP_PIN(3, 28),	/* /VI0_VSYNC	*/
-		[ 5] = RCAR_GP_PIN(3, 29),	/* VI0_DATA0	*/
-		[ 6] = RCAR_GP_PIN(3, 30),	/* VI0_DATA1	*/
-		[ 7] = RCAR_GP_PIN(3, 31),	/* VI0_DATA2	*/
-		[ 8] = RCAR_GP_PIN(4,  0),	/* VI0_DATA3	*/
-		[ 9] = RCAR_GP_PIN(4,  1),	/* VI0_DATA4	*/
-		[10] = RCAR_GP_PIN(4,  2),	/* VI0_DATA5	*/
-		[11] = RCAR_GP_PIN(4,  3),	/* VI0_DATA6	*/
-		[12] = RCAR_GP_PIN(4,  4),	/* VI0_DATA7	*/
-		[13] = RCAR_GP_PIN(4,  5),	/* VI0_G2	*/
-		[14] = RCAR_GP_PIN(4,  6),	/* VI0_G3	*/
-		[15] = RCAR_GP_PIN(4,  7),	/* VI0_G4	*/
-		[16] = RCAR_GP_PIN(4,  8),	/* VI0_G5	*/
-		[17] = RCAR_GP_PIN(4, 21),	/* VI1_DATA12	*/
-		[18] = RCAR_GP_PIN(4, 22),	/* VI1_DATA13	*/
-		[19] = RCAR_GP_PIN(4, 23),	/* VI1_DATA14	*/
-		[20] = RCAR_GP_PIN(4, 24),	/* VI1_DATA15	*/
-		[21] = RCAR_GP_PIN(4,  9),	/* ETH_REF_CLK	*/
-		[22] = RCAR_GP_PIN(4, 10),	/* ETH_TXD0	*/
-		[23] = RCAR_GP_PIN(4, 11),	/* ETH_TXD1	*/
-		[24] = RCAR_GP_PIN(4, 12),	/* ETH_CRS_DV	*/
-		[25] = RCAR_GP_PIN(4, 13),	/* ETH_TX_EN	*/
-		[26] = RCAR_GP_PIN(4, 14),	/* ETH_RX_ER	*/
-		[27] = RCAR_GP_PIN(4, 15),	/* ETH_RXD0	*/
-		[28] = RCAR_GP_PIN(4, 16),	/* ETH_RXD1	*/
-		[29] = RCAR_GP_PIN(4, 17),	/* ETH_MDC	*/
-		[30] = RCAR_GP_PIN(4, 18),	/* ETH_MDIO	*/
-		[31] = RCAR_GP_PIN(4, 19),	/* ETH_LINK	*/
-	} },
-	{ PINMUX_BIAS_REG("PUPR4", 0x110, "N/A", 0) {
-		[ 0] = RCAR_GP_PIN(3,  6),	/* SSI_SCK012	*/
-		[ 1] = RCAR_GP_PIN(3,  7),	/* SSI_WS012	*/
-		[ 2] = RCAR_GP_PIN(3, 10),	/* SSI_SDATA0	*/
-		[ 3] = RCAR_GP_PIN(3,  9),	/* SSI_SDATA1	*/
-		[ 4] = RCAR_GP_PIN(3,  8),	/* SSI_SDATA2	*/
-		[ 5] = RCAR_GP_PIN(3,  2),	/* SSI_SCK34	*/
-		[ 6] = RCAR_GP_PIN(3,  3),	/* SSI_WS34	*/
-		[ 7] = RCAR_GP_PIN(3,  5),	/* SSI_SDATA3	*/
-		[ 8] = RCAR_GP_PIN(3,  4),	/* SSI_SDATA4	*/
-		[ 9] = RCAR_GP_PIN(2, 31),	/* SSI_SCK5	*/
-		[10] = RCAR_GP_PIN(3,  0),	/* SSI_WS5	*/
-		[11] = RCAR_GP_PIN(3,  1),	/* SSI_SDATA5	*/
-		[12] = RCAR_GP_PIN(2, 28),	/* SSI_SCK6	*/
-		[13] = RCAR_GP_PIN(2, 29),	/* SSI_WS6	*/
-		[14] = RCAR_GP_PIN(2, 30),	/* SSI_SDATA6	*/
-		[15] = RCAR_GP_PIN(2, 24),	/* SSI_SCK78	*/
-		[16] = RCAR_GP_PIN(2, 25),	/* SSI_WS78	*/
-		[17] = RCAR_GP_PIN(2, 27),	/* SSI_SDATA7	*/
-		[18] = RCAR_GP_PIN(2, 26),	/* SSI_SDATA8	*/
-		[19] = RCAR_GP_PIN(3, 23),	/* TCLK0	*/
-		[20] = RCAR_GP_PIN(3, 11),	/* SD0_CLK	*/
-		[21] = RCAR_GP_PIN(3, 12),	/* SD0_CMD	*/
-		[22] = RCAR_GP_PIN(3, 13),	/* SD0_DAT0	*/
-		[23] = RCAR_GP_PIN(3, 14),	/* SD0_DAT1	*/
-		[24] = RCAR_GP_PIN(3, 15),	/* SD0_DAT2	*/
-		[25] = RCAR_GP_PIN(3, 16),	/* SD0_DAT3	*/
-		[26] = RCAR_GP_PIN(3, 17),	/* SD0_CD	*/
-		[27] = RCAR_GP_PIN(3, 18),	/* SD0_WP	*/
-		[28] = RCAR_GP_PIN(2, 22),	/* AUDIO_CLKA	*/
-		[29] = RCAR_GP_PIN(2, 23),	/* AUDIO_CLKB	*/
-		[30] = RCAR_GP_PIN(1, 14),	/* IRQ2		*/
-		[31] = RCAR_GP_PIN(1, 15),	/* IRQ3		*/
-	} },
-	{ PINMUX_BIAS_REG("PUPR5", 0x114, "N/A", 0) {
-		[ 0] = RCAR_GP_PIN(0,  1),	/* PENC0	*/
-		[ 1] = RCAR_GP_PIN(0,  2),	/* PENC1	*/
-		[ 2] = RCAR_GP_PIN(0,  3),	/* USB_OVC0	*/
-		[ 3] = RCAR_GP_PIN(0,  4),	/* USB_OVC1	*/
-		[ 4] = RCAR_GP_PIN(1, 16),	/* SCIF_CLK	*/
-		[ 5] = RCAR_GP_PIN(1, 17),	/* TX0		*/
-		[ 6] = RCAR_GP_PIN(1, 18),	/* RX0		*/
-		[ 7] = RCAR_GP_PIN(1, 19),	/* SCK0		*/
-		[ 8] = RCAR_GP_PIN(1, 20),	/* /CTS0	*/
-		[ 9] = RCAR_GP_PIN(1, 21),	/* /RTS0	*/
-		[10] = RCAR_GP_PIN(3, 19),	/* HSPI_CLK0	*/
-		[11] = RCAR_GP_PIN(3, 20),	/* /HSPI_CS0	*/
-		[12] = RCAR_GP_PIN(3, 21),	/* HSPI_RX0	*/
-		[13] = RCAR_GP_PIN(3, 22),	/* HSPI_TX0	*/
-		[14] = RCAR_GP_PIN(4, 20),	/* ETH_MAGIC	*/
-		[15] = RCAR_GP_PIN(4, 25),	/* AVS1		*/
-		[16] = RCAR_GP_PIN(4, 26),	/* AVS2		*/
-		[17] = SH_PFC_PIN_NONE,
-		[18] = SH_PFC_PIN_NONE,
-		[19] = SH_PFC_PIN_NONE,
-		[20] = SH_PFC_PIN_NONE,
-		[21] = SH_PFC_PIN_NONE,
-		[22] = SH_PFC_PIN_NONE,
-		[23] = SH_PFC_PIN_NONE,
-		[24] = SH_PFC_PIN_NONE,
-		[25] = SH_PFC_PIN_NONE,
-		[26] = SH_PFC_PIN_NONE,
-		[27] = SH_PFC_PIN_NONE,
-		[28] = SH_PFC_PIN_NONE,
-		[29] = SH_PFC_PIN_NONE,
-		[30] = SH_PFC_PIN_NONE,
-		[31] = SH_PFC_PIN_NONE,
-	} },
-	{ /* sentinel */ },
-};
-
-static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc,
-					    unsigned int pin)
-{
-	const struct pinmux_bias_reg *reg;
-	void __iomem *addr;
-	unsigned int bit;
-
-	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
-	if (!reg)
-		return PIN_CONFIG_BIAS_DISABLE;
-
-	addr = pfc->windows->virt + reg->puen;
-
-	if (ioread32(addr) & BIT(bit))
-		return PIN_CONFIG_BIAS_PULL_UP;
-	else
-		return PIN_CONFIG_BIAS_DISABLE;
-}
-
-static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
-				   unsigned int bias)
-{
-	const struct pinmux_bias_reg *reg;
-	void __iomem *addr;
-	unsigned int bit;
-	u32 value;
-
-	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
-	if (!reg)
-		return;
-
-	addr = pfc->windows->virt + reg->puen;
-
-	value = ioread32(addr) & ~BIT(bit);
-	if (bias == PIN_CONFIG_BIAS_PULL_UP)
-		value |= BIT(bit);
-	iowrite32(value, addr);
-}
-
-static const struct sh_pfc_soc_operations r8a7778_pfc_ops = {
-	.get_bias = r8a7778_pinmux_get_bias,
-	.set_bias = r8a7778_pinmux_set_bias,
-};
-
-const struct sh_pfc_soc_info r8a7778_pinmux_info = {
-	.name = "r8a7778_pfc",
-	.ops  = &r8a7778_pfc_ops,
-
-	.unlock_reg = 0xfffc0000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-
-	.groups = pinmux_groups,
-	.nr_groups = ARRAY_SIZE(pinmux_groups),
-
-	.functions = pinmux_functions,
-	.nr_functions = ARRAY_SIZE(pinmux_functions),
-
-	.cfg_regs = pinmux_config_regs,
-	.bias_regs = pinmux_bias_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
deleted file mode 100644
index 3e47cdc1411d..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ /dev/null
@@ -1,4029 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * r8a7779 processor support - PFC hardware block
- *
- * Copyright (C) 2011, 2013  Renesas Solutions Corp.
- * Copyright (C) 2011  Magnus Damm
- * Copyright (C) 2013  Cogent Embedded, Inc.
- */
-
-#include <linux/kernel.h>
-
-#include "sh_pfc.h"
-
-#define CPU_ALL_GP(fn, sfx)						\
-	PORT_GP_32(0, fn, sfx),						\
-	PORT_GP_32(1, fn, sfx),						\
-	PORT_GP_32(2, fn, sfx),						\
-	PORT_GP_32(3, fn, sfx),						\
-	PORT_GP_32(4, fn, sfx),						\
-	PORT_GP_32(5, fn, sfx),						\
-	PORT_GP_9(6, fn, sfx)
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */
-	PINMUX_DATA_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */
-
-	/* GPSR0 */
-	FN_AVS1, FN_AVS2, FN_IP0_7_6, FN_A17,
-	FN_A18, FN_A19, FN_IP0_9_8, FN_IP0_11_10,
-	FN_IP0_13_12, FN_IP0_15_14, FN_IP0_18_16, FN_IP0_22_19,
-	FN_IP0_24_23, FN_IP0_25, FN_IP0_27_26, FN_IP1_1_0,
-	FN_IP1_3_2, FN_IP1_6_4, FN_IP1_10_7, FN_IP1_14_11,
-	FN_IP1_18_15, FN_IP0_5_3, FN_IP0_30_28, FN_IP2_18_16,
-	FN_IP2_21_19, FN_IP2_30_28, FN_IP3_2_0, FN_IP3_11_9,
-	FN_IP3_14_12, FN_IP3_22_21, FN_IP3_26_24, FN_IP3_31_29,
-
-	/* GPSR1 */
-	FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, FN_IP4_10_8,
-	FN_IP4_11, FN_IP4_12, FN_IP4_13, FN_IP4_14,
-	FN_IP4_15, FN_IP4_16, FN_IP4_19_17, FN_IP4_22_20,
-	FN_IP4_23, FN_IP4_24, FN_IP4_25, FN_IP4_26,
-	FN_IP4_27, FN_IP4_28, FN_IP4_31_29, FN_IP5_2_0,
-	FN_IP5_3, FN_IP5_4, FN_IP5_5, FN_IP5_6,
-	FN_IP5_7, FN_IP5_8, FN_IP5_10_9, FN_IP5_12_11,
-	FN_IP5_14_13, FN_IP5_16_15, FN_IP5_20_17, FN_IP5_23_21,
-
-	/* GPSR2 */
-	FN_IP5_27_24, FN_IP8_20, FN_IP8_22_21, FN_IP8_24_23,
-	FN_IP8_27_25, FN_IP8_30_28, FN_IP9_1_0, FN_IP9_3_2,
-	FN_IP9_4, FN_IP9_5, FN_IP9_6, FN_IP9_7,
-	FN_IP9_9_8, FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14,
-	FN_IP9_18_16, FN_IP9_21_19, FN_IP9_23_22, FN_IP9_25_24,
-	FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
-	FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
-	FN_IP10_20_18, FN_IP10_23_21, FN_IP10_25_24, FN_IP10_28_26,
-
-	/* GPSR3 */
-	FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
-	FN_IP11_11_9, FN_IP11_14_12, FN_IP11_17_15, FN_IP11_20_18,
-	FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
-	FN_IP12_5_3, FN_IP12_8_6, FN_IP12_11_9, FN_IP12_14_12,
-	FN_IP12_17_15, FN_IP7_16_15, FN_IP7_18_17, FN_IP7_28_27,
-	FN_IP7_30_29, FN_IP7_20_19, FN_IP7_22_21, FN_IP7_24_23,
-	FN_IP7_26_25, FN_IP1_20_19, FN_IP1_22_21, FN_IP1_24_23,
-	FN_IP5_28, FN_IP5_30_29, FN_IP6_1_0, FN_IP6_3_2,
-
-	/* GPSR4 */
-	FN_IP6_5_4, FN_IP6_7_6, FN_IP6_8, FN_IP6_11_9,
-	FN_IP6_14_12, FN_IP6_17_15, FN_IP6_19_18, FN_IP6_22_20,
-	FN_IP6_24_23, FN_IP6_26_25, FN_IP6_30_29, FN_IP7_1_0,
-	FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
-	FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
-	FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
-	FN_IP8_11_8, FN_IP8_15_12, FN_USB_PENC0, FN_USB_PENC1,
-	FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
-
-	/* GPSR5 */
-	FN_A1, FN_A2, FN_A3, FN_A4,
-	FN_A5, FN_A6, FN_A7, FN_A8,
-	FN_A9, FN_A10, FN_A11, FN_A12,
-	FN_A13, FN_A14, FN_A15, FN_A16,
-	FN_RD, FN_WE0, FN_WE1, FN_EX_WAIT0,
-	FN_IP3_23, FN_IP3_27, FN_IP3_28, FN_IP2_22,
-	FN_IP2_23, FN_IP2_24, FN_IP2_25, FN_IP2_26,
-	FN_IP2_27, FN_IP3_3, FN_IP3_4, FN_IP3_5,
-
-	/* GPSR6 */
-	FN_IP3_6, FN_IP3_7, FN_IP3_8, FN_IP3_15,
-	FN_IP3_16, FN_IP3_17, FN_IP3_18, FN_IP3_19,
-	FN_IP3_20,
-
-	/* IPSR0 */
-	FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
-	FN_HRTS1, FN_RX4_C,
-	FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B,
-	FN_CS0, FN_HSPI_CS2_B,
-	FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B,
-	FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
-	FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
-	FN_CTS0_B,
-	FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
-	FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B,
-	FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
-	FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
-	FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B,
-	FN_A20, FN_TX5_D, FN_HSPI_TX2_B,
-	FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
-	FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
-	FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
-	FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
-	FN_SCIF_CLK, FN_TCLK0_C,
-
-	/* IPSR1 */
-	FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6,
-	FN_FD6, FN_EX_CS1, FN_MMC0_D7, FN_FD7,
-	FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
-	FN_ATACS00, FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD,
-	FN_FRE, FN_ATACS10, FN_VI1_R4, FN_RX5_B,
-	FN_HSCK1, FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9,
-	FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
-	FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
-	FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, FN_EX_CS5,
-	FN_SD1_DAT1, FN_MMC0_D1, FN_FD1, FN_ATAWR0,
-	FN_VI1_R6, FN_HRX1, FN_RX2_E, FN_RX0_B,
-	FN_SSI_WS9, FN_MLB_CLK, FN_PWM2, FN_SCK4,
-	FN_MLB_SIG, FN_PWM3, FN_TX4, FN_MLB_DAT,
-	FN_PWM4, FN_RX4, FN_HTX0, FN_TX1,
-	FN_SDATA, FN_CTS0_C, FN_SUB_TCK, FN_CC5_STATE2,
-	FN_CC5_STATE10, FN_CC5_STATE18, FN_CC5_STATE26, FN_CC5_STATE34,
-
-	/* IPSR2 */
-	FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
-	FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
-	FN_CC5_STATE27, FN_CC5_STATE35, FN_HSCK0, FN_SCK1,
-	FN_MTS, FN_PWM5, FN_SCK0_C, FN_SSI_SDATA9_B,
-	FN_SUB_TDO, FN_CC5_STATE0, FN_CC5_STATE8, FN_CC5_STATE16,
-	FN_CC5_STATE24, FN_CC5_STATE32, FN_HCTS0, FN_CTS1,
-	FN_STM, FN_PWM0_D, FN_RX0_C, FN_SCIF_CLK_C,
-	FN_SUB_TRST, FN_TCLK1_B, FN_CC5_OSCOUT, FN_HRTS0,
-	FN_RTS1_TANS, FN_MDATA, FN_TX0_C, FN_SUB_TMS,
-	FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17, FN_CC5_STATE25,
-	FN_CC5_STATE33, FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0,
-	FN_GPS_CLK_B, FN_AUDATA0, FN_TX5_C, FN_DU0_DR1,
-	FN_LCDOUT1, FN_DACK0, FN_DRACK0, FN_GPS_SIGN_B,
-	FN_AUDATA1, FN_RX5_C, FN_DU0_DR2, FN_LCDOUT2,
-	FN_DU0_DR3, FN_LCDOUT3, FN_DU0_DR4, FN_LCDOUT4,
-	FN_DU0_DR5, FN_LCDOUT5, FN_DU0_DR6, FN_LCDOUT6,
-	FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8,
-	FN_DREQ1, FN_SCL2, FN_AUDATA2,
-
-	/* IPSR3 */
-	FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
-	FN_AUDATA3, FN_DU0_DG2, FN_LCDOUT10, FN_DU0_DG3,
-	FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, FN_DU0_DG5,
-	FN_LCDOUT13, FN_DU0_DG6, FN_LCDOUT14, FN_DU0_DG7,
-	FN_LCDOUT15, FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1,
-	FN_SCL1, FN_TCLK1, FN_AUDATA4, FN_DU0_DB1,
-	FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1, FN_GPS_MAG_B,
-	FN_AUDATA5, FN_SCK5_C, FN_DU0_DB2, FN_LCDOUT18,
-	FN_DU0_DB3, FN_LCDOUT19, FN_DU0_DB4, FN_LCDOUT20,
-	FN_DU0_DB5, FN_LCDOUT21, FN_DU0_DB6, FN_LCDOUT22,
-	FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
-	FN_TX3_D_IRDA_TX_D, FN_SCL3_B, FN_DU0_DOTCLKOUT0, FN_QCLK,
-	FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
-	FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, FN_DU0_EXHSYNC_DU0_HSYNC,
-	FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
-	FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX,
-	FN_TX2_C, FN_SCL2_C, FN_REMOCON,
-
-	/* IPSR4 */
-	FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C,
-	FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
-	FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, FN_DU1_DR0,
-	FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK, FN_TX3_E_IRDA_TX_E,
-	FN_AUDCK, FN_PWMFSW0_B, FN_DU1_DR1, FN_VI2_DATA1_VI2_B1,
-	FN_PWM0, FN_SD3_CMD, FN_RX3_E_IRDA_RX_E, FN_AUDSYNC,
-	FN_CTS0_D, FN_DU1_DR2, FN_VI2_G0, FN_DU1_DR3,
-	FN_VI2_G1, FN_DU1_DR4, FN_VI2_G2, FN_DU1_DR5,
-	FN_VI2_G3, FN_DU1_DR6, FN_VI2_G4, FN_DU1_DR7,
-	FN_VI2_G5, FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B,
-	FN_SD3_DAT2, FN_SCK3_E, FN_AUDATA6, FN_TX0_D,
-	FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
-	FN_SCK5, FN_AUDATA7, FN_RX0_D, FN_DU1_DG2,
-	FN_VI2_G6, FN_DU1_DG3, FN_VI2_G7, FN_DU1_DG4,
-	FN_VI2_R0, FN_DU1_DG5, FN_VI2_R1, FN_DU1_DG6,
-	FN_VI2_R2, FN_DU1_DG7, FN_VI2_R3, FN_DU1_DB0,
-	FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, FN_TX5,
-	FN_SCK0_D,
-
-	/* IPSR5 */
-	FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
-	FN_RX5, FN_RTS0_D_TANS_D, FN_DU1_DB2, FN_VI2_R4,
-	FN_DU1_DB3, FN_VI2_R5, FN_DU1_DB4, FN_VI2_R6,
-	FN_DU1_DB5, FN_VI2_R7, FN_DU1_DB6, FN_SCL2_D,
-	FN_DU1_DB7, FN_SDA2_D, FN_DU1_DOTCLKIN, FN_VI2_CLKENB,
-	FN_HSPI_CS1, FN_SCL1_D, FN_DU1_DOTCLKOUT, FN_VI2_FIELD,
-	FN_SDA1_D, FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC,
-	FN_VI3_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC,
-	FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
-	FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
-	FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D,
-	FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
-	FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
-	FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B,
-	FN_SD3_WP, FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD,
-	FN_AUDIO_CLKOUT, FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D,
-	FN_AUDIO_CLKA, FN_CAN_TXCLK, FN_AUDIO_CLKB, FN_USB_OVC2,
-	FN_CAN_DEBUGOUT0, FN_MOUT0,
-
-	/* IPSR6 */
-	FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, FN_SSI_WS0129,
-	FN_CAN_DEBUGOUT2, FN_MOUT2, FN_SSI_SDATA0, FN_CAN_DEBUGOUT3,
-	FN_MOUT5, FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6,
-	FN_SSI_SDATA2, FN_CAN_DEBUGOUT5, FN_SSI_SCK34, FN_CAN_DEBUGOUT6,
-	FN_CAN0_TX_B, FN_IERX, FN_SSI_SCK9_C, FN_SSI_WS34,
-	FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX, FN_SSI_WS9_C,
-	FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
-	FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, FN_SSI_SDATA4,
-	FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, FN_SSI_SCK5, FN_ADICLK,
-	FN_CAN_DEBUGOUT10, FN_SCK3, FN_TCLK0_D, FN_SSI_WS5,
-	FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX, FN_SSI_SDATA5,
-	FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX, FN_SSI_SCK6,
-	FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
-
-	/* IPSR7 */
-	FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B,
-	FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
-	FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
-	FN_HSPI_CLK1_C, FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B,
-	FN_SSI_WS9_B, FN_HSPI_CS1_C, FN_SSI_SDATA7, FN_CAN_DEBUGOUT15,
-	FN_IRQ2_B, FN_TCLK1_C, FN_HSPI_TX1_C, FN_SSI_SDATA8,
-	FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C, FN_SD0_CLK,
-	FN_ATACS01, FN_SCK1_B, FN_SD0_CMD, FN_ATACS11,
-	FN_TX1_B, FN_CC5_TDO, FN_SD0_DAT0, FN_ATADIR1,
-	FN_RX1_B, FN_CC5_TRST, FN_SD0_DAT1, FN_ATAG1,
-	FN_SCK2_B, FN_CC5_TMS, FN_SD0_DAT2, FN_ATARD1,
-	FN_TX2_B, FN_CC5_TCK, FN_SD0_DAT3, FN_ATAWR1,
-	FN_RX2_B, FN_CC5_TDI, FN_SD0_CD, FN_DREQ2,
-	FN_RTS1_B_TANS_B, FN_SD0_WP, FN_DACK2, FN_CTS1_B,
-
-	/* IPSR8 */
-	FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
-	FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
-	FN_CC5_STATE36, FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1,
-	FN_AD_DI, FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21,
-	FN_CC5_STATE29, FN_CC5_STATE37, FN_HSPI_TX0, FN_TX0,
-	FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO, FN_CC5_STATE6, FN_CC5_STATE14,
-	FN_CC5_STATE22, FN_CC5_STATE30, FN_CC5_STATE38, FN_HSPI_RX0,
-	FN_RX0, FN_CAN_STEP0, FN_AD_NCS, FN_CC5_STATE7,
-	FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31, FN_CC5_STATE39,
-	FN_FMCLK, FN_RDS_CLK, FN_PCMOE, FN_BPFCLK,
-	FN_PCMWE, FN_FMIN, FN_RDS_DATA, FN_VI0_CLK,
-	FN_MMC1_CLK, FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B,
-	FN_MT1_SYNC, FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B,
-	FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
-	FN_MMC1_CMD, FN_HSCK1_B, FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B,
-	FN_RTS1_C_TANS_C, FN_RX4_D, FN_PWMFSW0_C,
-
-	/* IPSR9 */
-	FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, FN_VI0_DATA1_VI0_B1,
-	FN_HCTS1_B, FN_MT1_PWM, FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
-	FN_VI0_DATA3_VI0_B3, FN_MMC1_D1, FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
-	FN_VI0_DATA5_VI0_B5, FN_MMC1_D3, FN_VI0_DATA6_VI0_B6, FN_MMC1_D4,
-	FN_ARM_TRACEDATA_0, FN_VI0_DATA7_VI0_B7, FN_MMC1_D5,
-	FN_ARM_TRACEDATA_1, FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0,
-	FN_ARM_TRACEDATA_2, FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1,
-	FN_ARM_TRACEDATA_3, FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6,
-	FN_ARM_TRACEDATA_4, FN_TS_SPSYNC0, FN_VI0_G3, FN_ETH_CRS_DV,
-	FN_MMC1_D7, FN_ARM_TRACEDATA_5, FN_TS_SDAT0, FN_VI0_G4,
-	FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6, FN_VI0_G5,
-	FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7, FN_VI0_G6,
-	FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8, FN_VI0_G7,
-	FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
-
-	/* IPSR10 */
-	FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
-	FN_ARM_TRACEDATA_10, FN_DREQ0_C, FN_VI0_R1, FN_SSI_SDATA8_C,
-	FN_DACK1_B, FN_ARM_TRACEDATA_11, FN_DACK0_C, FN_DRACK0_C,
-	FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
-	FN_ARM_TRACEDATA_12, FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B,
-	FN_IRQ3, FN_ARM_TRACEDATA_13, FN_VI0_R4, FN_ETH_REFCLK,
-	FN_SD2_CD_B, FN_HSPI_CLK1_B, FN_ARM_TRACEDATA_14, FN_MT1_CLK,
-	FN_TS_SCK0, FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
-	FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, FN_VI0_R6,
-	FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B, FN_TRACECLK,
-	FN_MT1_BEN, FN_PWMFSW0_D, FN_VI0_R7, FN_ETH_MDIO,
-	FN_DACK2_C, FN_HSPI_RX1_B, FN_SCIF_CLK_D, FN_TRACECTL,
-	FN_MT1_PEN, FN_VI1_CLK, FN_SIM_D, FN_SDA3,
-	FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
-	FN_PWMFSW0_E, FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4,
-	FN_SIM_CLK, FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3,
-
-	/* IPSR11 */
-	FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
-	FN_ADICLK_B, FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK,
-	FN_SPV_TMS, FN_ADICS_B_SAMP_B, FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2,
-	FN_MT0_D, FN_SPVTDI, FN_ADIDATA_B, FN_VI1_DATA3_VI1_B3,
-	FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO, FN_ADICHS0_B,
-	FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
-	FN_HSPI_CLK1_D, FN_ADICHS1_B, FN_VI1_DATA5_VI1_B5, FN_SD2_CMD,
-	FN_MT0_SYNC, FN_SPA_TCK, FN_HSPI_CS1_D, FN_ADICHS2_B,
-	FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
-	FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM,
-	FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0,
-	FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
-	FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1,
-	FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B,
-
-	/* IPSR12 */
-	FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
-	FN_SCK2, FN_HSCK0_B, FN_VI1_G3, FN_VI3_DATA3,
-	FN_SSI_SCK2, FN_TS_SDAT1, FN_SCL1_C, FN_HTX0_B,
-	FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
-	FN_SIM_RST_B, FN_HRX0_B, FN_VI1_G5, FN_VI3_DATA5,
-	FN_GPS_CLK, FN_FSE, FN_TX4_B, FN_SIM_D_B,
-	FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
-	FN_RX4_B, FN_SIM_CLK_B, FN_VI1_G7, FN_VI3_DATA7,
-	FN_GPS_MAG, FN_FCE, FN_SCK4_B,
-
-	FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
-	FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
-	FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
-	FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
-	FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
-	FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
-	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
-	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
-	FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2,
-	FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
-	FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
-	FN_SEL_VI0_0, FN_SEL_VI0_1,
-	FN_SEL_SD2_0, FN_SEL_SD2_1,
-	FN_SEL_INT3_0, FN_SEL_INT3_1,
-	FN_SEL_INT2_0, FN_SEL_INT2_1,
-	FN_SEL_INT1_0, FN_SEL_INT1_1,
-	FN_SEL_INT0_0, FN_SEL_INT0_1,
-	FN_SEL_IE_0, FN_SEL_IE_1,
-	FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2,
-	FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
-	FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2,
-
-	FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2,
-	FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
-	FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
-	FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
-	FN_SEL_CAN0_0, FN_SEL_CAN0_1,
-	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
-	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
-	FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
-	FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4,
-	FN_SEL_ADI_0, FN_SEL_ADI_1,
-	FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
-	FN_SEL_SIM_0, FN_SEL_SIM_1,
-	FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
-	FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
-	FN_SEL_I2C3_0, FN_SEL_I2C3_1,
-	FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
-	FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-	AVS1_MARK, AVS2_MARK, A17_MARK, A18_MARK,
-	A19_MARK,
-
-	RD_WR_MARK, FWE_MARK, ATAG0_MARK, VI1_R7_MARK,
-	HRTS1_MARK, RX4_C_MARK,
-	CS1_A26_MARK, HSPI_TX2_MARK, SDSELF_B_MARK,
-	CS0_MARK, HSPI_CS2_B_MARK,
-	CLKOUT_MARK, TX3C_IRDA_TX_C_MARK, PWM0_B_MARK,
-	A25_MARK, SD1_WP_MARK, MMC0_D5_MARK, FD5_MARK,
-	HSPI_RX2_MARK, VI1_R3_MARK, TX5_B_MARK, SSI_SDATA7_B_MARK, CTS0_B_MARK,
-	A24_MARK, SD1_CD_MARK, MMC0_D4_MARK, FD4_MARK,
-	HSPI_CS2_MARK, VI1_R2_MARK, SSI_WS78_B_MARK,
-	A23_MARK, FCLE_MARK, HSPI_CLK2_MARK, VI1_R1_MARK,
-	A22_MARK, RX5_D_MARK, HSPI_RX2_B_MARK, VI1_R0_MARK,
-	A21_MARK, SCK5_D_MARK, HSPI_CLK2_B_MARK,
-	A20_MARK, TX5_D_MARK, HSPI_TX2_B_MARK,
-	A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
-	BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
-	ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
-	USB_PENC0_MARK, USB_PENC1_MARK, USB_PENC2_MARK,
-	SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
-	SCIF_CLK_MARK, TCLK0_C_MARK,
-
-	EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
-	FD6_MARK, EX_CS1_MARK, MMC0_D7_MARK, FD7_MARK,
-	EX_CS2_MARK, SD1_CLK_MARK, MMC0_CLK_MARK, FALE_MARK,
-	ATACS00_MARK, EX_CS3_MARK, SD1_CMD_MARK, MMC0_CMD_MARK,
-	FRE_MARK, ATACS10_MARK, VI1_R4_MARK, RX5_B_MARK,
-	HSCK1_MARK, SSI_SDATA8_B_MARK, RTS0_B_TANS_B_MARK, SSI_SDATA9_MARK,
-	EX_CS4_MARK, SD1_DAT0_MARK, MMC0_D0_MARK, FD0_MARK,
-	ATARD0_MARK, VI1_R5_MARK, SCK5_B_MARK, HTX1_MARK,
-	TX2_E_MARK, TX0_B_MARK, SSI_SCK9_MARK, EX_CS5_MARK,
-	SD1_DAT1_MARK, MMC0_D1_MARK, FD1_MARK, ATAWR0_MARK,
-	VI1_R6_MARK, HRX1_MARK, RX2_E_MARK, RX0_B_MARK,
-	SSI_WS9_MARK, MLB_CLK_MARK, PWM2_MARK, SCK4_MARK,
-	MLB_SIG_MARK, PWM3_MARK, TX4_MARK, MLB_DAT_MARK,
-	PWM4_MARK, RX4_MARK, HTX0_MARK, TX1_MARK,
-	SDATA_MARK, CTS0_C_MARK, SUB_TCK_MARK, CC5_STATE2_MARK,
-	CC5_STATE10_MARK, CC5_STATE18_MARK, CC5_STATE26_MARK, CC5_STATE34_MARK,
-
-	HRX0_MARK, RX1_MARK, SCKZ_MARK, RTS0_C_TANS_C_MARK,
-	SUB_TDI_MARK, CC5_STATE3_MARK, CC5_STATE11_MARK, CC5_STATE19_MARK,
-	CC5_STATE27_MARK, CC5_STATE35_MARK, HSCK0_MARK, SCK1_MARK,
-	MTS_MARK, PWM5_MARK, SCK0_C_MARK, SSI_SDATA9_B_MARK,
-	SUB_TDO_MARK, CC5_STATE0_MARK, CC5_STATE8_MARK, CC5_STATE16_MARK,
-	CC5_STATE24_MARK, CC5_STATE32_MARK, HCTS0_MARK, CTS1_MARK,
-	STM_MARK, PWM0_D_MARK, RX0_C_MARK, SCIF_CLK_C_MARK,
-	SUB_TRST_MARK, TCLK1_B_MARK, CC5_OSCOUT_MARK, HRTS0_MARK,
-	RTS1_TANS_MARK, MDATA_MARK, TX0_C_MARK, SUB_TMS_MARK,
-	CC5_STATE1_MARK, CC5_STATE9_MARK, CC5_STATE17_MARK, CC5_STATE25_MARK,
-	CC5_STATE33_MARK, DU0_DR0_MARK, LCDOUT0_MARK, DREQ0_MARK,
-	GPS_CLK_B_MARK, AUDATA0_MARK, TX5_C_MARK, DU0_DR1_MARK,
-	LCDOUT1_MARK, DACK0_MARK, DRACK0_MARK, GPS_SIGN_B_MARK,
-	AUDATA1_MARK, RX5_C_MARK, DU0_DR2_MARK, LCDOUT2_MARK,
-	DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK,
-	DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK,
-	DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK,
-	DREQ1_MARK, SCL2_MARK, AUDATA2_MARK,
-
-	DU0_DG1_MARK, LCDOUT9_MARK, DACK1_MARK, SDA2_MARK,
-	AUDATA3_MARK, DU0_DG2_MARK, LCDOUT10_MARK, DU0_DG3_MARK,
-	LCDOUT11_MARK, DU0_DG4_MARK, LCDOUT12_MARK, DU0_DG5_MARK,
-	LCDOUT13_MARK, DU0_DG6_MARK, LCDOUT14_MARK, DU0_DG7_MARK,
-	LCDOUT15_MARK, DU0_DB0_MARK, LCDOUT16_MARK, EX_WAIT1_MARK,
-	SCL1_MARK, TCLK1_MARK, AUDATA4_MARK, DU0_DB1_MARK,
-	LCDOUT17_MARK, EX_WAIT2_MARK, SDA1_MARK, GPS_MAG_B_MARK,
-	AUDATA5_MARK, SCK5_C_MARK, DU0_DB2_MARK, LCDOUT18_MARK,
-	DU0_DB3_MARK, LCDOUT19_MARK, DU0_DB4_MARK, LCDOUT20_MARK,
-	DU0_DB5_MARK, LCDOUT21_MARK, DU0_DB6_MARK, LCDOUT22_MARK,
-	DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
-	TX3_D_IRDA_TX_D_MARK, SCL3_B_MARK, DU0_DOTCLKOUT0_MARK, QCLK_MARK,
-	DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, RX3_D_IRDA_RX_D_MARK, SDA3_B_MARK,
-	SDA2_C_MARK, DACK0_B_MARK, DRACK0_B_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
-	QSTH_QHS_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
-	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CAN1_TX_MARK,
-	TX2_C_MARK, SCL2_C_MARK, REMOCON_MARK,
-
-	DU0_DISP_MARK, QPOLA_MARK, CAN_CLK_C_MARK, SCK2_C_MARK,
-	DU0_CDE_MARK, QPOLB_MARK, CAN1_RX_MARK, RX2_C_MARK,
-	DREQ0_B_MARK, SSI_SCK78_B_MARK, SCK0_B_MARK, DU1_DR0_MARK,
-	VI2_DATA0_VI2_B0_MARK, PWM6_MARK, SD3_CLK_MARK, TX3_E_IRDA_TX_E_MARK,
-	AUDCK_MARK, PWMFSW0_B_MARK, DU1_DR1_MARK, VI2_DATA1_VI2_B1_MARK,
-	PWM0_MARK, SD3_CMD_MARK, RX3_E_IRDA_RX_E_MARK, AUDSYNC_MARK,
-	CTS0_D_MARK, DU1_DR2_MARK, VI2_G0_MARK, DU1_DR3_MARK,
-	VI2_G1_MARK, DU1_DR4_MARK, VI2_G2_MARK, DU1_DR5_MARK,
-	VI2_G3_MARK, DU1_DR6_MARK, VI2_G4_MARK, DU1_DR7_MARK,
-	VI2_G5_MARK, DU1_DG0_MARK, VI2_DATA2_VI2_B2_MARK, SCL1_B_MARK,
-	SD3_DAT2_MARK, SCK3_E_MARK, AUDATA6_MARK, TX0_D_MARK,
-	DU1_DG1_MARK, VI2_DATA3_VI2_B3_MARK, SDA1_B_MARK, SD3_DAT3_MARK,
-	SCK5_MARK, AUDATA7_MARK, RX0_D_MARK, DU1_DG2_MARK,
-	VI2_G6_MARK, DU1_DG3_MARK, VI2_G7_MARK, DU1_DG4_MARK,
-	VI2_R0_MARK, DU1_DG5_MARK, VI2_R1_MARK, DU1_DG6_MARK,
-	VI2_R2_MARK, DU1_DG7_MARK, VI2_R3_MARK, DU1_DB0_MARK,
-	VI2_DATA4_VI2_B4_MARK, SCL2_B_MARK, SD3_DAT0_MARK, TX5_MARK,
-	SCK0_D_MARK,
-
-	DU1_DB1_MARK, VI2_DATA5_VI2_B5_MARK, SDA2_B_MARK, SD3_DAT1_MARK,
-	RX5_MARK, RTS0_D_TANS_D_MARK, DU1_DB2_MARK, VI2_R4_MARK,
-	DU1_DB3_MARK, VI2_R5_MARK, DU1_DB4_MARK, VI2_R6_MARK,
-	DU1_DB5_MARK, VI2_R7_MARK, DU1_DB6_MARK, SCL2_D_MARK,
-	DU1_DB7_MARK, SDA2_D_MARK, DU1_DOTCLKIN_MARK, VI2_CLKENB_MARK,
-	HSPI_CS1_MARK, SCL1_D_MARK, DU1_DOTCLKOUT_MARK, VI2_FIELD_MARK,
-	SDA1_D_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, VI2_HSYNC_MARK,
-	VI3_HSYNC_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, VI2_VSYNC_MARK,
-	VI3_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, VI2_CLK_MARK,
-	TX3_B_IRDA_TX_B_MARK, SD3_CD_MARK, HSPI_TX1_MARK, VI1_CLKENB_MARK,
-	VI3_CLKENB_MARK, AUDIO_CLKC_MARK, TX2_D_MARK, SPEEDIN_MARK,
-	GPS_SIGN_D_MARK, DU1_DISP_MARK, VI2_DATA6_VI2_B6_MARK, TCLK0_MARK,
-	QSTVA_B_QVS_B_MARK, HSPI_CLK1_MARK, SCK2_D_MARK, AUDIO_CLKOUT_B_MARK,
-	GPS_MAG_D_MARK, DU1_CDE_MARK, VI2_DATA7_VI2_B7_MARK,
-	RX3_B_IRDA_RX_B_MARK, SD3_WP_MARK, HSPI_RX1_MARK, VI1_FIELD_MARK,
-	VI3_FIELD_MARK, AUDIO_CLKOUT_MARK, RX2_D_MARK, GPS_CLK_C_MARK,
-	GPS_CLK_D_MARK, AUDIO_CLKA_MARK, CAN_TXCLK_MARK, AUDIO_CLKB_MARK,
-	USB_OVC2_MARK, CAN_DEBUGOUT0_MARK, MOUT0_MARK,
-
-	SSI_SCK0129_MARK, CAN_DEBUGOUT1_MARK, MOUT1_MARK, SSI_WS0129_MARK,
-	CAN_DEBUGOUT2_MARK, MOUT2_MARK, SSI_SDATA0_MARK, CAN_DEBUGOUT3_MARK,
-	MOUT5_MARK, SSI_SDATA1_MARK, CAN_DEBUGOUT4_MARK, MOUT6_MARK,
-	SSI_SDATA2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK34_MARK,
-	CAN_DEBUGOUT6_MARK, CAN0_TX_B_MARK, IERX_MARK, SSI_SCK9_C_MARK,
-	SSI_WS34_MARK, CAN_DEBUGOUT7_MARK, CAN0_RX_B_MARK, IETX_MARK,
-	SSI_WS9_C_MARK,	SSI_SDATA3_MARK, PWM0_C_MARK, CAN_DEBUGOUT8_MARK,
-	CAN_CLK_B_MARK,	IECLK_MARK, SCIF_CLK_B_MARK, TCLK0_B_MARK,
-	SSI_SDATA4_MARK, CAN_DEBUGOUT9_MARK, SSI_SDATA9_C_MARK, SSI_SCK5_MARK,
-	ADICLK_MARK, CAN_DEBUGOUT10_MARK, SCK3_MARK, TCLK0_D_MARK,
-	SSI_WS5_MARK, ADICS_SAMP_MARK, CAN_DEBUGOUT11_MARK, TX3_IRDA_TX_MARK,
-	SSI_SDATA5_MARK, ADIDATA_MARK, CAN_DEBUGOUT12_MARK, RX3_IRDA_RX_MARK,
-	SSI_SCK6_MARK, ADICHS0_MARK, CAN0_TX_MARK, IERX_B_MARK,
-
-	SSI_WS6_MARK, ADICHS1_MARK, CAN0_RX_MARK, IETX_B_MARK,
-	SSI_SDATA6_MARK, ADICHS2_MARK, CAN_CLK_MARK, IECLK_B_MARK,
-	SSI_SCK78_MARK, CAN_DEBUGOUT13_MARK, IRQ0_B_MARK, SSI_SCK9_B_MARK,
-	HSPI_CLK1_C_MARK, SSI_WS78_MARK, CAN_DEBUGOUT14_MARK, IRQ1_B_MARK,
-	SSI_WS9_B_MARK, HSPI_CS1_C_MARK, SSI_SDATA7_MARK, CAN_DEBUGOUT15_MARK,
-	IRQ2_B_MARK, TCLK1_C_MARK, HSPI_TX1_C_MARK, SSI_SDATA8_MARK,
-	VSP_MARK, IRQ3_B_MARK, HSPI_RX1_C_MARK, SD0_CLK_MARK,
-	ATACS01_MARK, SCK1_B_MARK, SD0_CMD_MARK, ATACS11_MARK,
-	TX1_B_MARK, CC5_TDO_MARK, SD0_DAT0_MARK, ATADIR1_MARK,
-	RX1_B_MARK, CC5_TRST_MARK, SD0_DAT1_MARK, ATAG1_MARK,
-	SCK2_B_MARK, CC5_TMS_MARK, SD0_DAT2_MARK, ATARD1_MARK,
-	TX2_B_MARK, CC5_TCK_MARK, SD0_DAT3_MARK, ATAWR1_MARK,
-	RX2_B_MARK, CC5_TDI_MARK, SD0_CD_MARK, DREQ2_MARK,
-	RTS1_B_TANS_B_MARK, SD0_WP_MARK, DACK2_MARK, CTS1_B_MARK,
-
-	HSPI_CLK0_MARK, CTS0_MARK, USB_OVC0_MARK, AD_CLK_MARK,
-	CC5_STATE4_MARK, CC5_STATE12_MARK, CC5_STATE20_MARK, CC5_STATE28_MARK,
-	CC5_STATE36_MARK, HSPI_CS0_MARK, RTS0_TANS_MARK, USB_OVC1_MARK,
-	AD_DI_MARK, CC5_STATE5_MARK, CC5_STATE13_MARK, CC5_STATE21_MARK,
-	CC5_STATE29_MARK, CC5_STATE37_MARK, HSPI_TX0_MARK, TX0_MARK,
-	CAN_DEBUG_HW_TRIGGER_MARK, AD_DO_MARK, CC5_STATE6_MARK,
-	CC5_STATE14_MARK, CC5_STATE22_MARK, CC5_STATE30_MARK,
-	CC5_STATE38_MARK, HSPI_RX0_MARK, RX0_MARK, CAN_STEP0_MARK,
-	AD_NCS_MARK, CC5_STATE7_MARK, CC5_STATE15_MARK, CC5_STATE23_MARK,
-	CC5_STATE31_MARK, CC5_STATE39_MARK, FMCLK_MARK, RDS_CLK_MARK,
-	PCMOE_MARK, BPFCLK_MARK, PCMWE_MARK, FMIN_MARK, RDS_DATA_MARK,
-	VI0_CLK_MARK, MMC1_CLK_MARK, VI0_CLKENB_MARK, TX1_C_MARK, HTX1_B_MARK,
-	MT1_SYNC_MARK, VI0_FIELD_MARK, RX1_C_MARK, HRX1_B_MARK,
-	VI0_HSYNC_MARK, VI0_DATA0_B_VI0_B0_B_MARK, CTS1_C_MARK, TX4_D_MARK,
-	MMC1_CMD_MARK, HSCK1_B_MARK, VI0_VSYNC_MARK, VI0_DATA1_B_VI0_B1_B_MARK,
-	RTS1_C_TANS_C_MARK, RX4_D_MARK, PWMFSW0_C_MARK,
-
-	VI0_DATA0_VI0_B0_MARK, HRTS1_B_MARK, MT1_VCXO_MARK,
-	VI0_DATA1_VI0_B1_MARK, HCTS1_B_MARK, MT1_PWM_MARK,
-	VI0_DATA2_VI0_B2_MARK, MMC1_D0_MARK, VI0_DATA3_VI0_B3_MARK,
-	MMC1_D1_MARK, VI0_DATA4_VI0_B4_MARK, MMC1_D2_MARK,
-	VI0_DATA5_VI0_B5_MARK, MMC1_D3_MARK, VI0_DATA6_VI0_B6_MARK,
-	MMC1_D4_MARK, ARM_TRACEDATA_0_MARK, VI0_DATA7_VI0_B7_MARK,
-	MMC1_D5_MARK, ARM_TRACEDATA_1_MARK, VI0_G0_MARK, SSI_SCK78_C_MARK,
-	IRQ0_MARK, ARM_TRACEDATA_2_MARK, VI0_G1_MARK, SSI_WS78_C_MARK,
-	IRQ1_MARK, ARM_TRACEDATA_3_MARK, VI0_G2_MARK, ETH_TXD1_MARK,
-	MMC1_D6_MARK, ARM_TRACEDATA_4_MARK, TS_SPSYNC0_MARK, VI0_G3_MARK,
-	ETH_CRS_DV_MARK, MMC1_D7_MARK, ARM_TRACEDATA_5_MARK, TS_SDAT0_MARK,
-	VI0_G4_MARK, ETH_TX_EN_MARK, SD2_DAT0_B_MARK, ARM_TRACEDATA_6_MARK,
-	VI0_G5_MARK, ETH_RX_ER_MARK, SD2_DAT1_B_MARK, ARM_TRACEDATA_7_MARK,
-	VI0_G6_MARK, ETH_RXD0_MARK, SD2_DAT2_B_MARK, ARM_TRACEDATA_8_MARK,
-	VI0_G7_MARK, ETH_RXD1_MARK, SD2_DAT3_B_MARK, ARM_TRACEDATA_9_MARK,
-
-	VI0_R0_MARK, SSI_SDATA7_C_MARK, SCK1_C_MARK, DREQ1_B_MARK,
-	ARM_TRACEDATA_10_MARK, DREQ0_C_MARK, VI0_R1_MARK, SSI_SDATA8_C_MARK,
-	DACK1_B_MARK, ARM_TRACEDATA_11_MARK, DACK0_C_MARK, DRACK0_C_MARK,
-	VI0_R2_MARK, ETH_LINK_MARK, SD2_CLK_B_MARK, IRQ2_MARK,
-	ARM_TRACEDATA_12_MARK, VI0_R3_MARK, ETH_MAGIC_MARK, SD2_CMD_B_MARK,
-	IRQ3_MARK, ARM_TRACEDATA_13_MARK, VI0_R4_MARK, ETH_REFCLK_MARK,
-	SD2_CD_B_MARK, HSPI_CLK1_B_MARK, ARM_TRACEDATA_14_MARK, MT1_CLK_MARK,
-	TS_SCK0_MARK, VI0_R5_MARK, ETH_TXD0_MARK, SD2_WP_B_MARK,
-	HSPI_CS1_B_MARK, ARM_TRACEDATA_15_MARK, MT1_D_MARK, TS_SDEN0_MARK,
-	VI0_R6_MARK, ETH_MDC_MARK, DREQ2_C_MARK, HSPI_TX1_B_MARK,
-	TRACECLK_MARK, MT1_BEN_MARK, PWMFSW0_D_MARK, VI0_R7_MARK,
-	ETH_MDIO_MARK, DACK2_C_MARK, HSPI_RX1_B_MARK, SCIF_CLK_D_MARK,
-	TRACECTL_MARK, MT1_PEN_MARK, VI1_CLK_MARK, SIM_D_MARK, SDA3_MARK,
-	VI1_HSYNC_MARK, VI3_CLK_MARK, SSI_SCK4_MARK, GPS_SIGN_C_MARK,
-	PWMFSW0_E_MARK, VI1_VSYNC_MARK, AUDIO_CLKOUT_C_MARK, SSI_WS4_MARK,
-	SIM_CLK_MARK, GPS_MAG_C_MARK, SPV_TRST_MARK, SCL3_MARK,
-
-	VI1_DATA0_VI1_B0_MARK, SD2_DAT0_MARK, SIM_RST_MARK, SPV_TCK_MARK,
-	ADICLK_B_MARK, VI1_DATA1_VI1_B1_MARK, SD2_DAT1_MARK, MT0_CLK_MARK,
-	SPV_TMS_MARK, ADICS_B_SAMP_B_MARK, VI1_DATA2_VI1_B2_MARK,
-	SD2_DAT2_MARK, MT0_D_MARK, SPVTDI_MARK, ADIDATA_B_MARK,
-	VI1_DATA3_VI1_B3_MARK, SD2_DAT3_MARK, MT0_BEN_MARK, SPV_TDO_MARK,
-	ADICHS0_B_MARK,	VI1_DATA4_VI1_B4_MARK, SD2_CLK_MARK, MT0_PEN_MARK,
-	SPA_TRST_MARK, HSPI_CLK1_D_MARK, ADICHS1_B_MARK,
-	VI1_DATA5_VI1_B5_MARK, SD2_CMD_MARK, MT0_SYNC_MARK, SPA_TCK_MARK,
-	HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK,
-	MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK,
-	SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK,
-	VI1_G0_MARK, VI3_DATA0_MARK, TS_SCK1_MARK,
-	DREQ2_B_MARK, TX2_MARK,	SPA_TDO_MARK, HCTS0_B_MARK,
-	VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK,
-	DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK,
-
-	VI1_G2_MARK, VI3_DATA2_MARK, SSI_WS1_MARK, TS_SPSYNC1_MARK,
-	SCK2_MARK, HSCK0_B_MARK, VI1_G3_MARK, VI3_DATA3_MARK,
-	SSI_SCK2_MARK, TS_SDAT1_MARK, SCL1_C_MARK, HTX0_B_MARK,
-	VI1_G4_MARK, VI3_DATA4_MARK, SSI_WS2_MARK, SDA1_C_MARK,
-	SIM_RST_B_MARK, HRX0_B_MARK, VI1_G5_MARK, VI3_DATA5_MARK,
-	GPS_CLK_MARK, FSE_MARK, TX4_B_MARK, SIM_D_B_MARK,
-	VI1_G6_MARK, VI3_DATA6_MARK, GPS_SIGN_MARK, FRB_MARK,
-	RX4_B_MARK, SIM_CLK_B_MARK, VI1_G7_MARK, VI3_DATA7_MARK,
-	GPS_MAG_MARK, FCE_MARK, SCK4_B_MARK,
-	PINMUX_MARK_END,
-};
-
-static const u16 pinmux_data[] = {
-	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
-
-	PINMUX_SINGLE(AVS1),
-	PINMUX_SINGLE(AVS1),
-	PINMUX_SINGLE(A17),
-	PINMUX_SINGLE(A18),
-	PINMUX_SINGLE(A19),
-
-	PINMUX_SINGLE(USB_PENC0),
-	PINMUX_SINGLE(USB_PENC1),
-
-	PINMUX_IPSR_GPSR(IP0_2_0, USB_PENC2),
-	PINMUX_IPSR_MSEL(IP0_2_0, SCK0, SEL_SCIF0_0),
-	PINMUX_IPSR_GPSR(IP0_2_0, PWM1),
-	PINMUX_IPSR_MSEL(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
-	PINMUX_IPSR_MSEL(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
-	PINMUX_IPSR_MSEL(IP0_2_0, TCLK0_C, SEL_TMU0_2),
-	PINMUX_IPSR_GPSR(IP0_5_3, BS),
-	PINMUX_IPSR_GPSR(IP0_5_3, SD1_DAT2),
-	PINMUX_IPSR_GPSR(IP0_5_3, MMC0_D2),
-	PINMUX_IPSR_GPSR(IP0_5_3, FD2),
-	PINMUX_IPSR_GPSR(IP0_5_3, ATADIR0),
-	PINMUX_IPSR_GPSR(IP0_5_3, SDSELF),
-	PINMUX_IPSR_MSEL(IP0_5_3, HCTS1, SEL_HSCIF1_0),
-	PINMUX_IPSR_GPSR(IP0_5_3, TX4_C),
-	PINMUX_IPSR_GPSR(IP0_7_6, A0),
-	PINMUX_IPSR_GPSR(IP0_7_6, SD1_DAT3),
-	PINMUX_IPSR_GPSR(IP0_7_6, MMC0_D3),
-	PINMUX_IPSR_GPSR(IP0_7_6, FD3),
-	PINMUX_IPSR_GPSR(IP0_9_8, A20),
-	PINMUX_IPSR_GPSR(IP0_9_8, TX5_D),
-	PINMUX_IPSR_GPSR(IP0_9_8, HSPI_TX2_B),
-	PINMUX_IPSR_GPSR(IP0_11_10, A21),
-	PINMUX_IPSR_MSEL(IP0_11_10, SCK5_D, SEL_SCIF5_3),
-	PINMUX_IPSR_MSEL(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
-	PINMUX_IPSR_GPSR(IP0_13_12, A22),
-	PINMUX_IPSR_MSEL(IP0_13_12, RX5_D, SEL_SCIF5_3),
-	PINMUX_IPSR_MSEL(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
-	PINMUX_IPSR_GPSR(IP0_13_12, VI1_R0),
-	PINMUX_IPSR_GPSR(IP0_15_14, A23),
-	PINMUX_IPSR_GPSR(IP0_15_14, FCLE),
-	PINMUX_IPSR_MSEL(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
-	PINMUX_IPSR_GPSR(IP0_15_14, VI1_R1),
-	PINMUX_IPSR_GPSR(IP0_18_16, A24),
-	PINMUX_IPSR_GPSR(IP0_18_16, SD1_CD),
-	PINMUX_IPSR_GPSR(IP0_18_16, MMC0_D4),
-	PINMUX_IPSR_GPSR(IP0_18_16, FD4),
-	PINMUX_IPSR_MSEL(IP0_18_16, HSPI_CS2, SEL_HSPI2_0),
-	PINMUX_IPSR_GPSR(IP0_18_16, VI1_R2),
-	PINMUX_IPSR_MSEL(IP0_18_16, SSI_WS78_B, SEL_SSI7_1),
-	PINMUX_IPSR_GPSR(IP0_22_19, A25),
-	PINMUX_IPSR_GPSR(IP0_22_19, SD1_WP),
-	PINMUX_IPSR_GPSR(IP0_22_19, MMC0_D5),
-	PINMUX_IPSR_GPSR(IP0_22_19, FD5),
-	PINMUX_IPSR_MSEL(IP0_22_19, HSPI_RX2, SEL_HSPI2_0),
-	PINMUX_IPSR_GPSR(IP0_22_19, VI1_R3),
-	PINMUX_IPSR_GPSR(IP0_22_19, TX5_B),
-	PINMUX_IPSR_MSEL(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1),
-	PINMUX_IPSR_MSEL(IP0_22_19, CTS0_B, SEL_SCIF0_1),
-	PINMUX_IPSR_GPSR(IP0_24_23, CLKOUT),
-	PINMUX_IPSR_GPSR(IP0_24_23, TX3C_IRDA_TX_C),
-	PINMUX_IPSR_GPSR(IP0_24_23, PWM0_B),
-	PINMUX_IPSR_GPSR(IP0_25, CS0),
-	PINMUX_IPSR_MSEL(IP0_25, HSPI_CS2_B, SEL_HSPI2_1),
-	PINMUX_IPSR_GPSR(IP0_27_26, CS1_A26),
-	PINMUX_IPSR_GPSR(IP0_27_26, HSPI_TX2),
-	PINMUX_IPSR_GPSR(IP0_27_26, SDSELF_B),
-	PINMUX_IPSR_GPSR(IP0_30_28, RD_WR),
-	PINMUX_IPSR_GPSR(IP0_30_28, FWE),
-	PINMUX_IPSR_GPSR(IP0_30_28, ATAG0),
-	PINMUX_IPSR_GPSR(IP0_30_28, VI1_R7),
-	PINMUX_IPSR_MSEL(IP0_30_28, HRTS1, SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP0_30_28, RX4_C, SEL_SCIF4_2),
-
-	PINMUX_IPSR_GPSR(IP1_1_0, EX_CS0),
-	PINMUX_IPSR_MSEL(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2),
-	PINMUX_IPSR_GPSR(IP1_1_0, MMC0_D6),
-	PINMUX_IPSR_GPSR(IP1_1_0, FD6),
-	PINMUX_IPSR_GPSR(IP1_3_2, EX_CS1),
-	PINMUX_IPSR_GPSR(IP1_3_2, MMC0_D7),
-	PINMUX_IPSR_GPSR(IP1_3_2, FD7),
-	PINMUX_IPSR_GPSR(IP1_6_4, EX_CS2),
-	PINMUX_IPSR_GPSR(IP1_6_4, SD1_CLK),
-	PINMUX_IPSR_GPSR(IP1_6_4, MMC0_CLK),
-	PINMUX_IPSR_GPSR(IP1_6_4, FALE),
-	PINMUX_IPSR_GPSR(IP1_6_4, ATACS00),
-	PINMUX_IPSR_GPSR(IP1_10_7, EX_CS3),
-	PINMUX_IPSR_GPSR(IP1_10_7, SD1_CMD),
-	PINMUX_IPSR_GPSR(IP1_10_7, MMC0_CMD),
-	PINMUX_IPSR_GPSR(IP1_10_7, FRE),
-	PINMUX_IPSR_GPSR(IP1_10_7, ATACS10),
-	PINMUX_IPSR_GPSR(IP1_10_7, VI1_R4),
-	PINMUX_IPSR_MSEL(IP1_10_7, RX5_B, SEL_SCIF5_1),
-	PINMUX_IPSR_MSEL(IP1_10_7, HSCK1, SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1),
-	PINMUX_IPSR_MSEL(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1),
-	PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA9, SEL_SSI9_0),
-	PINMUX_IPSR_GPSR(IP1_14_11, EX_CS4),
-	PINMUX_IPSR_GPSR(IP1_14_11, SD1_DAT0),
-	PINMUX_IPSR_GPSR(IP1_14_11, MMC0_D0),
-	PINMUX_IPSR_GPSR(IP1_14_11, FD0),
-	PINMUX_IPSR_GPSR(IP1_14_11, ATARD0),
-	PINMUX_IPSR_GPSR(IP1_14_11, VI1_R5),
-	PINMUX_IPSR_MSEL(IP1_14_11, SCK5_B, SEL_SCIF5_1),
-	PINMUX_IPSR_GPSR(IP1_14_11, HTX1),
-	PINMUX_IPSR_GPSR(IP1_14_11, TX2_E),
-	PINMUX_IPSR_GPSR(IP1_14_11, TX0_B),
-	PINMUX_IPSR_MSEL(IP1_14_11, SSI_SCK9, SEL_SSI9_0),
-	PINMUX_IPSR_GPSR(IP1_18_15, EX_CS5),
-	PINMUX_IPSR_GPSR(IP1_18_15, SD1_DAT1),
-	PINMUX_IPSR_GPSR(IP1_18_15, MMC0_D1),
-	PINMUX_IPSR_GPSR(IP1_18_15, FD1),
-	PINMUX_IPSR_GPSR(IP1_18_15, ATAWR0),
-	PINMUX_IPSR_GPSR(IP1_18_15, VI1_R6),
-	PINMUX_IPSR_MSEL(IP1_18_15, HRX1, SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP1_18_15, RX2_E, SEL_SCIF2_4),
-	PINMUX_IPSR_MSEL(IP1_18_15, RX0_B, SEL_SCIF0_1),
-	PINMUX_IPSR_MSEL(IP1_18_15, SSI_WS9, SEL_SSI9_0),
-	PINMUX_IPSR_GPSR(IP1_20_19, MLB_CLK),
-	PINMUX_IPSR_GPSR(IP1_20_19, PWM2),
-	PINMUX_IPSR_MSEL(IP1_20_19, SCK4, SEL_SCIF4_0),
-	PINMUX_IPSR_GPSR(IP1_22_21, MLB_SIG),
-	PINMUX_IPSR_GPSR(IP1_22_21, PWM3),
-	PINMUX_IPSR_GPSR(IP1_22_21, TX4),
-	PINMUX_IPSR_GPSR(IP1_24_23, MLB_DAT),
-	PINMUX_IPSR_GPSR(IP1_24_23, PWM4),
-	PINMUX_IPSR_MSEL(IP1_24_23, RX4, SEL_SCIF4_0),
-	PINMUX_IPSR_GPSR(IP1_28_25, HTX0),
-	PINMUX_IPSR_GPSR(IP1_28_25, TX1),
-	PINMUX_IPSR_GPSR(IP1_28_25, SDATA),
-	PINMUX_IPSR_MSEL(IP1_28_25, CTS0_C, SEL_SCIF0_2),
-	PINMUX_IPSR_GPSR(IP1_28_25, SUB_TCK),
-	PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE2),
-	PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE10),
-	PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE18),
-	PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE26),
-	PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE34),
-
-	PINMUX_IPSR_MSEL(IP2_3_0, HRX0, SEL_HSCIF0_0),
-	PINMUX_IPSR_MSEL(IP2_3_0, RX1, SEL_SCIF1_0),
-	PINMUX_IPSR_GPSR(IP2_3_0, SCKZ),
-	PINMUX_IPSR_MSEL(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2),
-	PINMUX_IPSR_GPSR(IP2_3_0, SUB_TDI),
-	PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE3),
-	PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE11),
-	PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE19),
-	PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE27),
-	PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE35),
-	PINMUX_IPSR_MSEL(IP2_7_4, HSCK0, SEL_HSCIF0_0),
-	PINMUX_IPSR_MSEL(IP2_7_4, SCK1, SEL_SCIF1_0),
-	PINMUX_IPSR_GPSR(IP2_7_4, MTS),
-	PINMUX_IPSR_GPSR(IP2_7_4, PWM5),
-	PINMUX_IPSR_MSEL(IP2_7_4, SCK0_C, SEL_SCIF0_2),
-	PINMUX_IPSR_MSEL(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1),
-	PINMUX_IPSR_GPSR(IP2_7_4, SUB_TDO),
-	PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE0),
-	PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE8),
-	PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE16),
-	PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE24),
-	PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE32),
-	PINMUX_IPSR_MSEL(IP2_11_8, HCTS0, SEL_HSCIF0_0),
-	PINMUX_IPSR_MSEL(IP2_11_8, CTS1, SEL_SCIF1_0),
-	PINMUX_IPSR_GPSR(IP2_11_8, STM),
-	PINMUX_IPSR_GPSR(IP2_11_8, PWM0_D),
-	PINMUX_IPSR_MSEL(IP2_11_8, RX0_C, SEL_SCIF0_2),
-	PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2),
-	PINMUX_IPSR_GPSR(IP2_11_8, SUB_TRST),
-	PINMUX_IPSR_MSEL(IP2_11_8, TCLK1_B, SEL_TMU1_1),
-	PINMUX_IPSR_GPSR(IP2_11_8, CC5_OSCOUT),
-	PINMUX_IPSR_MSEL(IP2_15_12, HRTS0, SEL_HSCIF0_0),
-	PINMUX_IPSR_MSEL(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
-	PINMUX_IPSR_GPSR(IP2_15_12, MDATA),
-	PINMUX_IPSR_GPSR(IP2_15_12, TX0_C),
-	PINMUX_IPSR_GPSR(IP2_15_12, SUB_TMS),
-	PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE1),
-	PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE9),
-	PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE17),
-	PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE25),
-	PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE33),
-	PINMUX_IPSR_GPSR(IP2_18_16, DU0_DR0),
-	PINMUX_IPSR_GPSR(IP2_18_16, LCDOUT0),
-	PINMUX_IPSR_MSEL(IP2_18_16, DREQ0, SEL_EXBUS0_0),
-	PINMUX_IPSR_MSEL(IP2_18_16, GPS_CLK_B, SEL_GPS_1),
-	PINMUX_IPSR_GPSR(IP2_18_16, AUDATA0),
-	PINMUX_IPSR_GPSR(IP2_18_16, TX5_C),
-	PINMUX_IPSR_GPSR(IP2_21_19, DU0_DR1),
-	PINMUX_IPSR_GPSR(IP2_21_19, LCDOUT1),
-	PINMUX_IPSR_GPSR(IP2_21_19, DACK0),
-	PINMUX_IPSR_GPSR(IP2_21_19, DRACK0),
-	PINMUX_IPSR_MSEL(IP2_21_19, GPS_SIGN_B, SEL_GPS_1),
-	PINMUX_IPSR_GPSR(IP2_21_19, AUDATA1),
-	PINMUX_IPSR_MSEL(IP2_21_19, RX5_C, SEL_SCIF5_2),
-	PINMUX_IPSR_GPSR(IP2_22, DU0_DR2),
-	PINMUX_IPSR_GPSR(IP2_22, LCDOUT2),
-	PINMUX_IPSR_GPSR(IP2_23, DU0_DR3),
-	PINMUX_IPSR_GPSR(IP2_23, LCDOUT3),
-	PINMUX_IPSR_GPSR(IP2_24, DU0_DR4),
-	PINMUX_IPSR_GPSR(IP2_24, LCDOUT4),
-	PINMUX_IPSR_GPSR(IP2_25, DU0_DR5),
-	PINMUX_IPSR_GPSR(IP2_25, LCDOUT5),
-	PINMUX_IPSR_GPSR(IP2_26, DU0_DR6),
-	PINMUX_IPSR_GPSR(IP2_26, LCDOUT6),
-	PINMUX_IPSR_GPSR(IP2_27, DU0_DR7),
-	PINMUX_IPSR_GPSR(IP2_27, LCDOUT7),
-	PINMUX_IPSR_GPSR(IP2_30_28, DU0_DG0),
-	PINMUX_IPSR_GPSR(IP2_30_28, LCDOUT8),
-	PINMUX_IPSR_MSEL(IP2_30_28, DREQ1, SEL_EXBUS1_0),
-	PINMUX_IPSR_MSEL(IP2_30_28, SCL2, SEL_I2C2_0),
-	PINMUX_IPSR_GPSR(IP2_30_28, AUDATA2),
-
-	PINMUX_IPSR_GPSR(IP3_2_0, DU0_DG1),
-	PINMUX_IPSR_GPSR(IP3_2_0, LCDOUT9),
-	PINMUX_IPSR_GPSR(IP3_2_0, DACK1),
-	PINMUX_IPSR_MSEL(IP3_2_0, SDA2, SEL_I2C2_0),
-	PINMUX_IPSR_GPSR(IP3_2_0, AUDATA3),
-	PINMUX_IPSR_GPSR(IP3_3, DU0_DG2),
-	PINMUX_IPSR_GPSR(IP3_3, LCDOUT10),
-	PINMUX_IPSR_GPSR(IP3_4, DU0_DG3),
-	PINMUX_IPSR_GPSR(IP3_4, LCDOUT11),
-	PINMUX_IPSR_GPSR(IP3_5, DU0_DG4),
-	PINMUX_IPSR_GPSR(IP3_5, LCDOUT12),
-	PINMUX_IPSR_GPSR(IP3_6, DU0_DG5),
-	PINMUX_IPSR_GPSR(IP3_6, LCDOUT13),
-	PINMUX_IPSR_GPSR(IP3_7, DU0_DG6),
-	PINMUX_IPSR_GPSR(IP3_7, LCDOUT14),
-	PINMUX_IPSR_GPSR(IP3_8, DU0_DG7),
-	PINMUX_IPSR_GPSR(IP3_8, LCDOUT15),
-	PINMUX_IPSR_GPSR(IP3_11_9, DU0_DB0),
-	PINMUX_IPSR_GPSR(IP3_11_9, LCDOUT16),
-	PINMUX_IPSR_GPSR(IP3_11_9, EX_WAIT1),
-	PINMUX_IPSR_MSEL(IP3_11_9, SCL1, SEL_I2C1_0),
-	PINMUX_IPSR_MSEL(IP3_11_9, TCLK1, SEL_TMU1_0),
-	PINMUX_IPSR_GPSR(IP3_11_9, AUDATA4),
-	PINMUX_IPSR_GPSR(IP3_14_12, DU0_DB1),
-	PINMUX_IPSR_GPSR(IP3_14_12, LCDOUT17),
-	PINMUX_IPSR_GPSR(IP3_14_12, EX_WAIT2),
-	PINMUX_IPSR_MSEL(IP3_14_12, SDA1, SEL_I2C1_0),
-	PINMUX_IPSR_MSEL(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
-	PINMUX_IPSR_GPSR(IP3_14_12, AUDATA5),
-	PINMUX_IPSR_MSEL(IP3_14_12, SCK5_C, SEL_SCIF5_2),
-	PINMUX_IPSR_GPSR(IP3_15, DU0_DB2),
-	PINMUX_IPSR_GPSR(IP3_15, LCDOUT18),
-	PINMUX_IPSR_GPSR(IP3_16, DU0_DB3),
-	PINMUX_IPSR_GPSR(IP3_16, LCDOUT19),
-	PINMUX_IPSR_GPSR(IP3_17, DU0_DB4),
-	PINMUX_IPSR_GPSR(IP3_17, LCDOUT20),
-	PINMUX_IPSR_GPSR(IP3_18, DU0_DB5),
-	PINMUX_IPSR_GPSR(IP3_18, LCDOUT21),
-	PINMUX_IPSR_GPSR(IP3_19, DU0_DB6),
-	PINMUX_IPSR_GPSR(IP3_19, LCDOUT22),
-	PINMUX_IPSR_GPSR(IP3_20, DU0_DB7),
-	PINMUX_IPSR_GPSR(IP3_20, LCDOUT23),
-	PINMUX_IPSR_GPSR(IP3_22_21, DU0_DOTCLKIN),
-	PINMUX_IPSR_GPSR(IP3_22_21, QSTVA_QVS),
-	PINMUX_IPSR_GPSR(IP3_22_21, TX3_D_IRDA_TX_D),
-	PINMUX_IPSR_MSEL(IP3_22_21, SCL3_B, SEL_I2C3_1),
-	PINMUX_IPSR_GPSR(IP3_23, DU0_DOTCLKOUT0),
-	PINMUX_IPSR_GPSR(IP3_23, QCLK),
-	PINMUX_IPSR_GPSR(IP3_26_24, DU0_DOTCLKOUT1),
-	PINMUX_IPSR_GPSR(IP3_26_24, QSTVB_QVE),
-	PINMUX_IPSR_MSEL(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
-	PINMUX_IPSR_MSEL(IP3_26_24, SDA3_B, SEL_I2C3_1),
-	PINMUX_IPSR_MSEL(IP3_26_24, SDA2_C, SEL_I2C2_2),
-	PINMUX_IPSR_GPSR(IP3_26_24, DACK0_B),
-	PINMUX_IPSR_GPSR(IP3_26_24, DRACK0_B),
-	PINMUX_IPSR_GPSR(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
-	PINMUX_IPSR_GPSR(IP3_27, QSTH_QHS),
-	PINMUX_IPSR_GPSR(IP3_28, DU0_EXVSYNC_DU0_VSYNC),
-	PINMUX_IPSR_GPSR(IP3_28, QSTB_QHE),
-	PINMUX_IPSR_GPSR(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE),
-	PINMUX_IPSR_GPSR(IP3_31_29, QCPV_QDE),
-	PINMUX_IPSR_GPSR(IP3_31_29, CAN1_TX),
-	PINMUX_IPSR_GPSR(IP3_31_29, TX2_C),
-	PINMUX_IPSR_MSEL(IP3_31_29, SCL2_C, SEL_I2C2_2),
-	PINMUX_IPSR_GPSR(IP3_31_29, REMOCON),
-
-	PINMUX_IPSR_GPSR(IP4_1_0, DU0_DISP),
-	PINMUX_IPSR_GPSR(IP4_1_0, QPOLA),
-	PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
-	PINMUX_IPSR_MSEL(IP4_1_0, SCK2_C, SEL_SCIF2_2),
-	PINMUX_IPSR_GPSR(IP4_4_2, DU0_CDE),
-	PINMUX_IPSR_GPSR(IP4_4_2, QPOLB),
-	PINMUX_IPSR_GPSR(IP4_4_2, CAN1_RX),
-	PINMUX_IPSR_MSEL(IP4_4_2, RX2_C, SEL_SCIF2_2),
-	PINMUX_IPSR_MSEL(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
-	PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
-	PINMUX_IPSR_MSEL(IP4_4_2, SCK0_B, SEL_SCIF0_1),
-	PINMUX_IPSR_GPSR(IP4_7_5, DU1_DR0),
-	PINMUX_IPSR_GPSR(IP4_7_5, VI2_DATA0_VI2_B0),
-	PINMUX_IPSR_GPSR(IP4_7_5, PWM6),
-	PINMUX_IPSR_GPSR(IP4_7_5, SD3_CLK),
-	PINMUX_IPSR_GPSR(IP4_7_5, TX3_E_IRDA_TX_E),
-	PINMUX_IPSR_GPSR(IP4_7_5, AUDCK),
-	PINMUX_IPSR_MSEL(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
-	PINMUX_IPSR_GPSR(IP4_10_8, DU1_DR1),
-	PINMUX_IPSR_GPSR(IP4_10_8, VI2_DATA1_VI2_B1),
-	PINMUX_IPSR_GPSR(IP4_10_8, PWM0),
-	PINMUX_IPSR_GPSR(IP4_10_8, SD3_CMD),
-	PINMUX_IPSR_MSEL(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
-	PINMUX_IPSR_GPSR(IP4_10_8, AUDSYNC),
-	PINMUX_IPSR_MSEL(IP4_10_8, CTS0_D, SEL_SCIF0_3),
-	PINMUX_IPSR_GPSR(IP4_11, DU1_DR2),
-	PINMUX_IPSR_GPSR(IP4_11, VI2_G0),
-	PINMUX_IPSR_GPSR(IP4_12, DU1_DR3),
-	PINMUX_IPSR_GPSR(IP4_12, VI2_G1),
-	PINMUX_IPSR_GPSR(IP4_13, DU1_DR4),
-	PINMUX_IPSR_GPSR(IP4_13, VI2_G2),
-	PINMUX_IPSR_GPSR(IP4_14, DU1_DR5),
-	PINMUX_IPSR_GPSR(IP4_14, VI2_G3),
-	PINMUX_IPSR_GPSR(IP4_15, DU1_DR6),
-	PINMUX_IPSR_GPSR(IP4_15, VI2_G4),
-	PINMUX_IPSR_GPSR(IP4_16, DU1_DR7),
-	PINMUX_IPSR_GPSR(IP4_16, VI2_G5),
-	PINMUX_IPSR_GPSR(IP4_19_17, DU1_DG0),
-	PINMUX_IPSR_GPSR(IP4_19_17, VI2_DATA2_VI2_B2),
-	PINMUX_IPSR_MSEL(IP4_19_17, SCL1_B, SEL_I2C1_1),
-	PINMUX_IPSR_GPSR(IP4_19_17, SD3_DAT2),
-	PINMUX_IPSR_MSEL(IP4_19_17, SCK3_E, SEL_SCIF3_4),
-	PINMUX_IPSR_GPSR(IP4_19_17, AUDATA6),
-	PINMUX_IPSR_GPSR(IP4_19_17, TX0_D),
-	PINMUX_IPSR_GPSR(IP4_22_20, DU1_DG1),
-	PINMUX_IPSR_GPSR(IP4_22_20, VI2_DATA3_VI2_B3),
-	PINMUX_IPSR_MSEL(IP4_22_20, SDA1_B, SEL_I2C1_1),
-	PINMUX_IPSR_GPSR(IP4_22_20, SD3_DAT3),
-	PINMUX_IPSR_MSEL(IP4_22_20, SCK5, SEL_SCIF5_0),
-	PINMUX_IPSR_GPSR(IP4_22_20, AUDATA7),
-	PINMUX_IPSR_MSEL(IP4_22_20, RX0_D, SEL_SCIF0_3),
-	PINMUX_IPSR_GPSR(IP4_23, DU1_DG2),
-	PINMUX_IPSR_GPSR(IP4_23, VI2_G6),
-	PINMUX_IPSR_GPSR(IP4_24, DU1_DG3),
-	PINMUX_IPSR_GPSR(IP4_24, VI2_G7),
-	PINMUX_IPSR_GPSR(IP4_25, DU1_DG4),
-	PINMUX_IPSR_GPSR(IP4_25, VI2_R0),
-	PINMUX_IPSR_GPSR(IP4_26, DU1_DG5),
-	PINMUX_IPSR_GPSR(IP4_26, VI2_R1),
-	PINMUX_IPSR_GPSR(IP4_27, DU1_DG6),
-	PINMUX_IPSR_GPSR(IP4_27, VI2_R2),
-	PINMUX_IPSR_GPSR(IP4_28, DU1_DG7),
-	PINMUX_IPSR_GPSR(IP4_28, VI2_R3),
-	PINMUX_IPSR_GPSR(IP4_31_29, DU1_DB0),
-	PINMUX_IPSR_GPSR(IP4_31_29, VI2_DATA4_VI2_B4),
-	PINMUX_IPSR_MSEL(IP4_31_29, SCL2_B, SEL_I2C2_1),
-	PINMUX_IPSR_GPSR(IP4_31_29, SD3_DAT0),
-	PINMUX_IPSR_GPSR(IP4_31_29, TX5),
-	PINMUX_IPSR_MSEL(IP4_31_29, SCK0_D, SEL_SCIF0_3),
-
-	PINMUX_IPSR_GPSR(IP5_2_0, DU1_DB1),
-	PINMUX_IPSR_GPSR(IP5_2_0, VI2_DATA5_VI2_B5),
-	PINMUX_IPSR_MSEL(IP5_2_0, SDA2_B, SEL_I2C2_1),
-	PINMUX_IPSR_GPSR(IP5_2_0, SD3_DAT1),
-	PINMUX_IPSR_MSEL(IP5_2_0, RX5, SEL_SCIF5_0),
-	PINMUX_IPSR_MSEL(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3),
-	PINMUX_IPSR_GPSR(IP5_3, DU1_DB2),
-	PINMUX_IPSR_GPSR(IP5_3, VI2_R4),
-	PINMUX_IPSR_GPSR(IP5_4, DU1_DB3),
-	PINMUX_IPSR_GPSR(IP5_4, VI2_R5),
-	PINMUX_IPSR_GPSR(IP5_5, DU1_DB4),
-	PINMUX_IPSR_GPSR(IP5_5, VI2_R6),
-	PINMUX_IPSR_GPSR(IP5_6, DU1_DB5),
-	PINMUX_IPSR_GPSR(IP5_6, VI2_R7),
-	PINMUX_IPSR_GPSR(IP5_7, DU1_DB6),
-	PINMUX_IPSR_MSEL(IP5_7, SCL2_D, SEL_I2C2_3),
-	PINMUX_IPSR_GPSR(IP5_8, DU1_DB7),
-	PINMUX_IPSR_MSEL(IP5_8, SDA2_D, SEL_I2C2_3),
-	PINMUX_IPSR_GPSR(IP5_10_9, DU1_DOTCLKIN),
-	PINMUX_IPSR_GPSR(IP5_10_9, VI2_CLKENB),
-	PINMUX_IPSR_MSEL(IP5_10_9, HSPI_CS1, SEL_HSPI1_0),
-	PINMUX_IPSR_MSEL(IP5_10_9, SCL1_D, SEL_I2C1_3),
-	PINMUX_IPSR_GPSR(IP5_12_11, DU1_DOTCLKOUT),
-	PINMUX_IPSR_GPSR(IP5_12_11, VI2_FIELD),
-	PINMUX_IPSR_MSEL(IP5_12_11, SDA1_D, SEL_I2C1_3),
-	PINMUX_IPSR_GPSR(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC),
-	PINMUX_IPSR_GPSR(IP5_14_13, VI2_HSYNC),
-	PINMUX_IPSR_GPSR(IP5_14_13, VI3_HSYNC),
-	PINMUX_IPSR_GPSR(IP5_16_15, DU1_EXVSYNC_DU1_VSYNC),
-	PINMUX_IPSR_GPSR(IP5_16_15, VI2_VSYNC),
-	PINMUX_IPSR_GPSR(IP5_16_15, VI3_VSYNC),
-	PINMUX_IPSR_GPSR(IP5_20_17, DU1_EXODDF_DU1_ODDF_DISP_CDE),
-	PINMUX_IPSR_GPSR(IP5_20_17, VI2_CLK),
-	PINMUX_IPSR_GPSR(IP5_20_17, TX3_B_IRDA_TX_B),
-	PINMUX_IPSR_GPSR(IP5_20_17, SD3_CD),
-	PINMUX_IPSR_GPSR(IP5_20_17, HSPI_TX1),
-	PINMUX_IPSR_GPSR(IP5_20_17, VI1_CLKENB),
-	PINMUX_IPSR_GPSR(IP5_20_17, VI3_CLKENB),
-	PINMUX_IPSR_GPSR(IP5_20_17, AUDIO_CLKC),
-	PINMUX_IPSR_GPSR(IP5_20_17, TX2_D),
-	PINMUX_IPSR_GPSR(IP5_20_17, SPEEDIN),
-	PINMUX_IPSR_MSEL(IP5_20_17, GPS_SIGN_D, SEL_GPS_3),
-	PINMUX_IPSR_GPSR(IP5_23_21, DU1_DISP),
-	PINMUX_IPSR_GPSR(IP5_23_21, VI2_DATA6_VI2_B6),
-	PINMUX_IPSR_MSEL(IP5_23_21, TCLK0, SEL_TMU0_0),
-	PINMUX_IPSR_GPSR(IP5_23_21, QSTVA_B_QVS_B),
-	PINMUX_IPSR_MSEL(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0),
-	PINMUX_IPSR_MSEL(IP5_23_21, SCK2_D, SEL_SCIF2_3),
-	PINMUX_IPSR_GPSR(IP5_23_21, AUDIO_CLKOUT_B),
-	PINMUX_IPSR_MSEL(IP5_23_21, GPS_MAG_D, SEL_GPS_3),
-	PINMUX_IPSR_GPSR(IP5_27_24, DU1_CDE),
-	PINMUX_IPSR_GPSR(IP5_27_24, VI2_DATA7_VI2_B7),
-	PINMUX_IPSR_MSEL(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
-	PINMUX_IPSR_GPSR(IP5_27_24, SD3_WP),
-	PINMUX_IPSR_MSEL(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
-	PINMUX_IPSR_GPSR(IP5_27_24, VI1_FIELD),
-	PINMUX_IPSR_GPSR(IP5_27_24, VI3_FIELD),
-	PINMUX_IPSR_GPSR(IP5_27_24, AUDIO_CLKOUT),
-	PINMUX_IPSR_MSEL(IP5_27_24, RX2_D, SEL_SCIF2_3),
-	PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_C, SEL_GPS_2),
-	PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_D, SEL_GPS_3),
-	PINMUX_IPSR_GPSR(IP5_28, AUDIO_CLKA),
-	PINMUX_IPSR_GPSR(IP5_28, CAN_TXCLK),
-	PINMUX_IPSR_GPSR(IP5_30_29, AUDIO_CLKB),
-	PINMUX_IPSR_GPSR(IP5_30_29, USB_OVC2),
-	PINMUX_IPSR_GPSR(IP5_30_29, CAN_DEBUGOUT0),
-	PINMUX_IPSR_GPSR(IP5_30_29, MOUT0),
-
-	PINMUX_IPSR_GPSR(IP6_1_0, SSI_SCK0129),
-	PINMUX_IPSR_GPSR(IP6_1_0, CAN_DEBUGOUT1),
-	PINMUX_IPSR_GPSR(IP6_1_0, MOUT1),
-	PINMUX_IPSR_GPSR(IP6_3_2, SSI_WS0129),
-	PINMUX_IPSR_GPSR(IP6_3_2, CAN_DEBUGOUT2),
-	PINMUX_IPSR_GPSR(IP6_3_2, MOUT2),
-	PINMUX_IPSR_GPSR(IP6_5_4, SSI_SDATA0),
-	PINMUX_IPSR_GPSR(IP6_5_4, CAN_DEBUGOUT3),
-	PINMUX_IPSR_GPSR(IP6_5_4, MOUT5),
-	PINMUX_IPSR_GPSR(IP6_7_6, SSI_SDATA1),
-	PINMUX_IPSR_GPSR(IP6_7_6, CAN_DEBUGOUT4),
-	PINMUX_IPSR_GPSR(IP6_7_6, MOUT6),
-	PINMUX_IPSR_GPSR(IP6_8, SSI_SDATA2),
-	PINMUX_IPSR_GPSR(IP6_8, CAN_DEBUGOUT5),
-	PINMUX_IPSR_GPSR(IP6_11_9, SSI_SCK34),
-	PINMUX_IPSR_GPSR(IP6_11_9, CAN_DEBUGOUT6),
-	PINMUX_IPSR_GPSR(IP6_11_9, CAN0_TX_B),
-	PINMUX_IPSR_MSEL(IP6_11_9, IERX, SEL_IE_0),
-	PINMUX_IPSR_MSEL(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2),
-	PINMUX_IPSR_GPSR(IP6_14_12, SSI_WS34),
-	PINMUX_IPSR_GPSR(IP6_14_12, CAN_DEBUGOUT7),
-	PINMUX_IPSR_MSEL(IP6_14_12, CAN0_RX_B, SEL_CAN0_1),
-	PINMUX_IPSR_GPSR(IP6_14_12, IETX),
-	PINMUX_IPSR_MSEL(IP6_14_12, SSI_WS9_C, SEL_SSI9_2),
-	PINMUX_IPSR_GPSR(IP6_17_15, SSI_SDATA3),
-	PINMUX_IPSR_GPSR(IP6_17_15, PWM0_C),
-	PINMUX_IPSR_GPSR(IP6_17_15, CAN_DEBUGOUT8),
-	PINMUX_IPSR_MSEL(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1),
-	PINMUX_IPSR_MSEL(IP6_17_15, IECLK, SEL_IE_0),
-	PINMUX_IPSR_MSEL(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1),
-	PINMUX_IPSR_MSEL(IP6_17_15, TCLK0_B, SEL_TMU0_1),
-	PINMUX_IPSR_GPSR(IP6_19_18, SSI_SDATA4),
-	PINMUX_IPSR_GPSR(IP6_19_18, CAN_DEBUGOUT9),
-	PINMUX_IPSR_MSEL(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2),
-	PINMUX_IPSR_GPSR(IP6_22_20, SSI_SCK5),
-	PINMUX_IPSR_GPSR(IP6_22_20, ADICLK),
-	PINMUX_IPSR_GPSR(IP6_22_20, CAN_DEBUGOUT10),
-	PINMUX_IPSR_MSEL(IP6_22_20, SCK3, SEL_SCIF3_0),
-	PINMUX_IPSR_MSEL(IP6_22_20, TCLK0_D, SEL_TMU0_3),
-	PINMUX_IPSR_GPSR(IP6_24_23, SSI_WS5),
-	PINMUX_IPSR_MSEL(IP6_24_23, ADICS_SAMP, SEL_ADI_0),
-	PINMUX_IPSR_GPSR(IP6_24_23, CAN_DEBUGOUT11),
-	PINMUX_IPSR_GPSR(IP6_24_23, TX3_IRDA_TX),
-	PINMUX_IPSR_GPSR(IP6_26_25, SSI_SDATA5),
-	PINMUX_IPSR_MSEL(IP6_26_25, ADIDATA, SEL_ADI_0),
-	PINMUX_IPSR_GPSR(IP6_26_25, CAN_DEBUGOUT12),
-	PINMUX_IPSR_MSEL(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0),
-	PINMUX_IPSR_GPSR(IP6_30_29, SSI_SCK6),
-	PINMUX_IPSR_GPSR(IP6_30_29, ADICHS0),
-	PINMUX_IPSR_GPSR(IP6_30_29, CAN0_TX),
-	PINMUX_IPSR_MSEL(IP6_30_29, IERX_B, SEL_IE_1),
-
-	PINMUX_IPSR_GPSR(IP7_1_0, SSI_WS6),
-	PINMUX_IPSR_GPSR(IP7_1_0, ADICHS1),
-	PINMUX_IPSR_MSEL(IP7_1_0, CAN0_RX, SEL_CAN0_0),
-	PINMUX_IPSR_GPSR(IP7_1_0, IETX_B),
-	PINMUX_IPSR_GPSR(IP7_3_2, SSI_SDATA6),
-	PINMUX_IPSR_GPSR(IP7_3_2, ADICHS2),
-	PINMUX_IPSR_MSEL(IP7_3_2, CAN_CLK, SEL_CANCLK_0),
-	PINMUX_IPSR_MSEL(IP7_3_2, IECLK_B, SEL_IE_1),
-	PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK78, SEL_SSI7_0),
-	PINMUX_IPSR_GPSR(IP7_6_4, CAN_DEBUGOUT13),
-	PINMUX_IPSR_MSEL(IP7_6_4, IRQ0_B, SEL_INT0_1),
-	PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1),
-	PINMUX_IPSR_MSEL(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2),
-	PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS78, SEL_SSI7_0),
-	PINMUX_IPSR_GPSR(IP7_9_7, CAN_DEBUGOUT14),
-	PINMUX_IPSR_MSEL(IP7_9_7, IRQ1_B, SEL_INT1_1),
-	PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS9_B, SEL_SSI9_1),
-	PINMUX_IPSR_MSEL(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2),
-	PINMUX_IPSR_MSEL(IP7_12_10, SSI_SDATA7, SEL_SSI7_0),
-	PINMUX_IPSR_GPSR(IP7_12_10, CAN_DEBUGOUT15),
-	PINMUX_IPSR_MSEL(IP7_12_10, IRQ2_B, SEL_INT2_1),
-	PINMUX_IPSR_MSEL(IP7_12_10, TCLK1_C, SEL_TMU1_2),
-	PINMUX_IPSR_GPSR(IP7_12_10, HSPI_TX1_C),
-	PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA8, SEL_SSI8_0),
-	PINMUX_IPSR_GPSR(IP7_14_13, VSP),
-	PINMUX_IPSR_MSEL(IP7_14_13, IRQ3_B, SEL_INT3_1),
-	PINMUX_IPSR_MSEL(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2),
-	PINMUX_IPSR_GPSR(IP7_16_15, SD0_CLK),
-	PINMUX_IPSR_GPSR(IP7_16_15, ATACS01),
-	PINMUX_IPSR_MSEL(IP7_16_15, SCK1_B, SEL_SCIF1_1),
-	PINMUX_IPSR_GPSR(IP7_18_17, SD0_CMD),
-	PINMUX_IPSR_GPSR(IP7_18_17, ATACS11),
-	PINMUX_IPSR_GPSR(IP7_18_17, TX1_B),
-	PINMUX_IPSR_GPSR(IP7_18_17, CC5_TDO),
-	PINMUX_IPSR_GPSR(IP7_20_19, SD0_DAT0),
-	PINMUX_IPSR_GPSR(IP7_20_19, ATADIR1),
-	PINMUX_IPSR_MSEL(IP7_20_19, RX1_B, SEL_SCIF1_1),
-	PINMUX_IPSR_GPSR(IP7_20_19, CC5_TRST),
-	PINMUX_IPSR_GPSR(IP7_22_21, SD0_DAT1),
-	PINMUX_IPSR_GPSR(IP7_22_21, ATAG1),
-	PINMUX_IPSR_MSEL(IP7_22_21, SCK2_B, SEL_SCIF2_1),
-	PINMUX_IPSR_GPSR(IP7_22_21, CC5_TMS),
-	PINMUX_IPSR_GPSR(IP7_24_23, SD0_DAT2),
-	PINMUX_IPSR_GPSR(IP7_24_23, ATARD1),
-	PINMUX_IPSR_GPSR(IP7_24_23, TX2_B),
-	PINMUX_IPSR_GPSR(IP7_24_23, CC5_TCK),
-	PINMUX_IPSR_GPSR(IP7_26_25, SD0_DAT3),
-	PINMUX_IPSR_GPSR(IP7_26_25, ATAWR1),
-	PINMUX_IPSR_MSEL(IP7_26_25, RX2_B, SEL_SCIF2_1),
-	PINMUX_IPSR_GPSR(IP7_26_25, CC5_TDI),
-	PINMUX_IPSR_GPSR(IP7_28_27, SD0_CD),
-	PINMUX_IPSR_MSEL(IP7_28_27, DREQ2, SEL_EXBUS2_0),
-	PINMUX_IPSR_MSEL(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1),
-	PINMUX_IPSR_GPSR(IP7_30_29, SD0_WP),
-	PINMUX_IPSR_GPSR(IP7_30_29, DACK2),
-	PINMUX_IPSR_MSEL(IP7_30_29, CTS1_B, SEL_SCIF1_1),
-
-	PINMUX_IPSR_GPSR(IP8_3_0, HSPI_CLK0),
-	PINMUX_IPSR_MSEL(IP8_3_0, CTS0, SEL_SCIF0_0),
-	PINMUX_IPSR_GPSR(IP8_3_0, USB_OVC0),
-	PINMUX_IPSR_GPSR(IP8_3_0, AD_CLK),
-	PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE4),
-	PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE12),
-	PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE20),
-	PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE28),
-	PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE36),
-	PINMUX_IPSR_GPSR(IP8_7_4, HSPI_CS0),
-	PINMUX_IPSR_MSEL(IP8_7_4, RTS0_TANS, SEL_SCIF0_0),
-	PINMUX_IPSR_GPSR(IP8_7_4, USB_OVC1),
-	PINMUX_IPSR_GPSR(IP8_7_4, AD_DI),
-	PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE5),
-	PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE13),
-	PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE21),
-	PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE29),
-	PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE37),
-	PINMUX_IPSR_GPSR(IP8_11_8, HSPI_TX0),
-	PINMUX_IPSR_GPSR(IP8_11_8, TX0),
-	PINMUX_IPSR_GPSR(IP8_11_8, CAN_DEBUG_HW_TRIGGER),
-	PINMUX_IPSR_GPSR(IP8_11_8, AD_DO),
-	PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE6),
-	PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE14),
-	PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE22),
-	PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE30),
-	PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE38),
-	PINMUX_IPSR_GPSR(IP8_15_12, HSPI_RX0),
-	PINMUX_IPSR_MSEL(IP8_15_12, RX0, SEL_SCIF0_0),
-	PINMUX_IPSR_GPSR(IP8_15_12, CAN_STEP0),
-	PINMUX_IPSR_GPSR(IP8_15_12, AD_NCS),
-	PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE7),
-	PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE15),
-	PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE23),
-	PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE31),
-	PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE39),
-	PINMUX_IPSR_GPSR(IP8_17_16, FMCLK),
-	PINMUX_IPSR_GPSR(IP8_17_16, RDS_CLK),
-	PINMUX_IPSR_GPSR(IP8_17_16, PCMOE),
-	PINMUX_IPSR_GPSR(IP8_18, BPFCLK),
-	PINMUX_IPSR_GPSR(IP8_18, PCMWE),
-	PINMUX_IPSR_GPSR(IP8_19, FMIN),
-	PINMUX_IPSR_GPSR(IP8_19, RDS_DATA),
-	PINMUX_IPSR_GPSR(IP8_20, VI0_CLK),
-	PINMUX_IPSR_GPSR(IP8_20, MMC1_CLK),
-	PINMUX_IPSR_GPSR(IP8_22_21, VI0_CLKENB),
-	PINMUX_IPSR_GPSR(IP8_22_21, TX1_C),
-	PINMUX_IPSR_GPSR(IP8_22_21, HTX1_B),
-	PINMUX_IPSR_GPSR(IP8_22_21, MT1_SYNC),
-	PINMUX_IPSR_GPSR(IP8_24_23, VI0_FIELD),
-	PINMUX_IPSR_MSEL(IP8_24_23, RX1_C, SEL_SCIF1_2),
-	PINMUX_IPSR_MSEL(IP8_24_23, HRX1_B, SEL_HSCIF1_1),
-	PINMUX_IPSR_GPSR(IP8_27_25, VI0_HSYNC),
-	PINMUX_IPSR_MSEL(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP8_27_25, CTS1_C, SEL_SCIF1_2),
-	PINMUX_IPSR_GPSR(IP8_27_25, TX4_D),
-	PINMUX_IPSR_GPSR(IP8_27_25, MMC1_CMD),
-	PINMUX_IPSR_MSEL(IP8_27_25, HSCK1_B, SEL_HSCIF1_1),
-	PINMUX_IPSR_GPSR(IP8_30_28, VI0_VSYNC),
-	PINMUX_IPSR_MSEL(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2),
-	PINMUX_IPSR_MSEL(IP8_30_28, RX4_D, SEL_SCIF4_3),
-	PINMUX_IPSR_MSEL(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2),
-
-	PINMUX_IPSR_MSEL(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP9_1_0, HRTS1_B, SEL_HSCIF1_1),
-	PINMUX_IPSR_GPSR(IP9_1_0, MT1_VCXO),
-	PINMUX_IPSR_MSEL(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP9_3_2, HCTS1_B, SEL_HSCIF1_1),
-	PINMUX_IPSR_GPSR(IP9_3_2, MT1_PWM),
-	PINMUX_IPSR_GPSR(IP9_4, VI0_DATA2_VI0_B2),
-	PINMUX_IPSR_GPSR(IP9_4, MMC1_D0),
-	PINMUX_IPSR_GPSR(IP9_5, VI0_DATA3_VI0_B3),
-	PINMUX_IPSR_GPSR(IP9_5, MMC1_D1),
-	PINMUX_IPSR_GPSR(IP9_6, VI0_DATA4_VI0_B4),
-	PINMUX_IPSR_GPSR(IP9_6, MMC1_D2),
-	PINMUX_IPSR_GPSR(IP9_7, VI0_DATA5_VI0_B5),
-	PINMUX_IPSR_GPSR(IP9_7, MMC1_D3),
-	PINMUX_IPSR_GPSR(IP9_9_8, VI0_DATA6_VI0_B6),
-	PINMUX_IPSR_GPSR(IP9_9_8, MMC1_D4),
-	PINMUX_IPSR_GPSR(IP9_9_8, ARM_TRACEDATA_0),
-	PINMUX_IPSR_GPSR(IP9_11_10, VI0_DATA7_VI0_B7),
-	PINMUX_IPSR_GPSR(IP9_11_10, MMC1_D5),
-	PINMUX_IPSR_GPSR(IP9_11_10, ARM_TRACEDATA_1),
-	PINMUX_IPSR_GPSR(IP9_13_12, VI0_G0),
-	PINMUX_IPSR_MSEL(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2),
-	PINMUX_IPSR_MSEL(IP9_13_12, IRQ0, SEL_INT0_0),
-	PINMUX_IPSR_GPSR(IP9_13_12, ARM_TRACEDATA_2),
-	PINMUX_IPSR_GPSR(IP9_15_14, VI0_G1),
-	PINMUX_IPSR_MSEL(IP9_15_14, SSI_WS78_C, SEL_SSI7_2),
-	PINMUX_IPSR_MSEL(IP9_15_14, IRQ1, SEL_INT1_0),
-	PINMUX_IPSR_GPSR(IP9_15_14, ARM_TRACEDATA_3),
-	PINMUX_IPSR_GPSR(IP9_18_16, VI0_G2),
-	PINMUX_IPSR_GPSR(IP9_18_16, ETH_TXD1),
-	PINMUX_IPSR_GPSR(IP9_18_16, MMC1_D6),
-	PINMUX_IPSR_GPSR(IP9_18_16, ARM_TRACEDATA_4),
-	PINMUX_IPSR_GPSR(IP9_18_16, TS_SPSYNC0),
-	PINMUX_IPSR_GPSR(IP9_21_19, VI0_G3),
-	PINMUX_IPSR_GPSR(IP9_21_19, ETH_CRS_DV),
-	PINMUX_IPSR_GPSR(IP9_21_19, MMC1_D7),
-	PINMUX_IPSR_GPSR(IP9_21_19, ARM_TRACEDATA_5),
-	PINMUX_IPSR_GPSR(IP9_21_19, TS_SDAT0),
-	PINMUX_IPSR_GPSR(IP9_23_22, VI0_G4),
-	PINMUX_IPSR_GPSR(IP9_23_22, ETH_TX_EN),
-	PINMUX_IPSR_MSEL(IP9_23_22, SD2_DAT0_B, SEL_SD2_1),
-	PINMUX_IPSR_GPSR(IP9_23_22, ARM_TRACEDATA_6),
-	PINMUX_IPSR_GPSR(IP9_25_24, VI0_G5),
-	PINMUX_IPSR_GPSR(IP9_25_24, ETH_RX_ER),
-	PINMUX_IPSR_MSEL(IP9_25_24, SD2_DAT1_B, SEL_SD2_1),
-	PINMUX_IPSR_GPSR(IP9_25_24, ARM_TRACEDATA_7),
-	PINMUX_IPSR_GPSR(IP9_27_26, VI0_G6),
-	PINMUX_IPSR_GPSR(IP9_27_26, ETH_RXD0),
-	PINMUX_IPSR_MSEL(IP9_27_26, SD2_DAT2_B, SEL_SD2_1),
-	PINMUX_IPSR_GPSR(IP9_27_26, ARM_TRACEDATA_8),
-	PINMUX_IPSR_GPSR(IP9_29_28, VI0_G7),
-	PINMUX_IPSR_GPSR(IP9_29_28, ETH_RXD1),
-	PINMUX_IPSR_MSEL(IP9_29_28, SD2_DAT3_B, SEL_SD2_1),
-	PINMUX_IPSR_GPSR(IP9_29_28, ARM_TRACEDATA_9),
-
-	PINMUX_IPSR_GPSR(IP10_2_0, VI0_R0),
-	PINMUX_IPSR_MSEL(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2),
-	PINMUX_IPSR_MSEL(IP10_2_0, SCK1_C, SEL_SCIF1_2),
-	PINMUX_IPSR_MSEL(IP10_2_0, DREQ1_B, SEL_EXBUS1_0),
-	PINMUX_IPSR_GPSR(IP10_2_0, ARM_TRACEDATA_10),
-	PINMUX_IPSR_MSEL(IP10_2_0, DREQ0_C, SEL_EXBUS0_2),
-	PINMUX_IPSR_GPSR(IP10_5_3, VI0_R1),
-	PINMUX_IPSR_MSEL(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2),
-	PINMUX_IPSR_GPSR(IP10_5_3, DACK1_B),
-	PINMUX_IPSR_GPSR(IP10_5_3, ARM_TRACEDATA_11),
-	PINMUX_IPSR_GPSR(IP10_5_3, DACK0_C),
-	PINMUX_IPSR_GPSR(IP10_5_3, DRACK0_C),
-	PINMUX_IPSR_GPSR(IP10_8_6, VI0_R2),
-	PINMUX_IPSR_GPSR(IP10_8_6, ETH_LINK),
-	PINMUX_IPSR_GPSR(IP10_8_6, SD2_CLK_B),
-	PINMUX_IPSR_MSEL(IP10_8_6, IRQ2, SEL_INT2_0),
-	PINMUX_IPSR_GPSR(IP10_8_6, ARM_TRACEDATA_12),
-	PINMUX_IPSR_GPSR(IP10_11_9, VI0_R3),
-	PINMUX_IPSR_GPSR(IP10_11_9, ETH_MAGIC),
-	PINMUX_IPSR_MSEL(IP10_11_9, SD2_CMD_B, SEL_SD2_1),
-	PINMUX_IPSR_MSEL(IP10_11_9, IRQ3, SEL_INT3_0),
-	PINMUX_IPSR_GPSR(IP10_11_9, ARM_TRACEDATA_13),
-	PINMUX_IPSR_GPSR(IP10_14_12, VI0_R4),
-	PINMUX_IPSR_GPSR(IP10_14_12, ETH_REFCLK),
-	PINMUX_IPSR_MSEL(IP10_14_12, SD2_CD_B, SEL_SD2_1),
-	PINMUX_IPSR_MSEL(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1),
-	PINMUX_IPSR_GPSR(IP10_14_12, ARM_TRACEDATA_14),
-	PINMUX_IPSR_GPSR(IP10_14_12, MT1_CLK),
-	PINMUX_IPSR_GPSR(IP10_14_12, TS_SCK0),
-	PINMUX_IPSR_GPSR(IP10_17_15, VI0_R5),
-	PINMUX_IPSR_GPSR(IP10_17_15, ETH_TXD0),
-	PINMUX_IPSR_MSEL(IP10_17_15, SD2_WP_B, SEL_SD2_1),
-	PINMUX_IPSR_MSEL(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1),
-	PINMUX_IPSR_GPSR(IP10_17_15, ARM_TRACEDATA_15),
-	PINMUX_IPSR_GPSR(IP10_17_15, MT1_D),
-	PINMUX_IPSR_GPSR(IP10_17_15, TS_SDEN0),
-	PINMUX_IPSR_GPSR(IP10_20_18, VI0_R6),
-	PINMUX_IPSR_GPSR(IP10_20_18, ETH_MDC),
-	PINMUX_IPSR_MSEL(IP10_20_18, DREQ2_C, SEL_EXBUS2_2),
-	PINMUX_IPSR_GPSR(IP10_20_18, HSPI_TX1_B),
-	PINMUX_IPSR_GPSR(IP10_20_18, TRACECLK),
-	PINMUX_IPSR_GPSR(IP10_20_18, MT1_BEN),
-	PINMUX_IPSR_MSEL(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3),
-	PINMUX_IPSR_GPSR(IP10_23_21, VI0_R7),
-	PINMUX_IPSR_GPSR(IP10_23_21, ETH_MDIO),
-	PINMUX_IPSR_GPSR(IP10_23_21, DACK2_C),
-	PINMUX_IPSR_MSEL(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1),
-	PINMUX_IPSR_MSEL(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3),
-	PINMUX_IPSR_GPSR(IP10_23_21, TRACECTL),
-	PINMUX_IPSR_GPSR(IP10_23_21, MT1_PEN),
-	PINMUX_IPSR_GPSR(IP10_25_24, VI1_CLK),
-	PINMUX_IPSR_MSEL(IP10_25_24, SIM_D, SEL_SIM_0),
-	PINMUX_IPSR_MSEL(IP10_25_24, SDA3, SEL_I2C3_0),
-	PINMUX_IPSR_GPSR(IP10_28_26, VI1_HSYNC),
-	PINMUX_IPSR_GPSR(IP10_28_26, VI3_CLK),
-	PINMUX_IPSR_GPSR(IP10_28_26, SSI_SCK4),
-	PINMUX_IPSR_MSEL(IP10_28_26, GPS_SIGN_C, SEL_GPS_2),
-	PINMUX_IPSR_MSEL(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4),
-	PINMUX_IPSR_GPSR(IP10_31_29, VI1_VSYNC),
-	PINMUX_IPSR_GPSR(IP10_31_29, AUDIO_CLKOUT_C),
-	PINMUX_IPSR_GPSR(IP10_31_29, SSI_WS4),
-	PINMUX_IPSR_GPSR(IP10_31_29, SIM_CLK),
-	PINMUX_IPSR_MSEL(IP10_31_29, GPS_MAG_C, SEL_GPS_2),
-	PINMUX_IPSR_GPSR(IP10_31_29, SPV_TRST),
-	PINMUX_IPSR_MSEL(IP10_31_29, SCL3, SEL_I2C3_0),
-
-	PINMUX_IPSR_GPSR(IP11_2_0, VI1_DATA0_VI1_B0),
-	PINMUX_IPSR_MSEL(IP11_2_0, SD2_DAT0, SEL_SD2_0),
-	PINMUX_IPSR_GPSR(IP11_2_0, SIM_RST),
-	PINMUX_IPSR_GPSR(IP11_2_0, SPV_TCK),
-	PINMUX_IPSR_GPSR(IP11_2_0, ADICLK_B),
-	PINMUX_IPSR_GPSR(IP11_5_3, VI1_DATA1_VI1_B1),
-	PINMUX_IPSR_MSEL(IP11_5_3, SD2_DAT1, SEL_SD2_0),
-	PINMUX_IPSR_GPSR(IP11_5_3, MT0_CLK),
-	PINMUX_IPSR_GPSR(IP11_5_3, SPV_TMS),
-	PINMUX_IPSR_MSEL(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1),
-	PINMUX_IPSR_GPSR(IP11_8_6, VI1_DATA2_VI1_B2),
-	PINMUX_IPSR_MSEL(IP11_8_6, SD2_DAT2, SEL_SD2_0),
-	PINMUX_IPSR_GPSR(IP11_8_6, MT0_D),
-	PINMUX_IPSR_GPSR(IP11_8_6, SPVTDI),
-	PINMUX_IPSR_MSEL(IP11_8_6, ADIDATA_B, SEL_ADI_1),
-	PINMUX_IPSR_GPSR(IP11_11_9, VI1_DATA3_VI1_B3),
-	PINMUX_IPSR_MSEL(IP11_11_9, SD2_DAT3, SEL_SD2_0),
-	PINMUX_IPSR_GPSR(IP11_11_9, MT0_BEN),
-	PINMUX_IPSR_GPSR(IP11_11_9, SPV_TDO),
-	PINMUX_IPSR_GPSR(IP11_11_9, ADICHS0_B),
-	PINMUX_IPSR_GPSR(IP11_14_12, VI1_DATA4_VI1_B4),
-	PINMUX_IPSR_GPSR(IP11_14_12, SD2_CLK),
-	PINMUX_IPSR_GPSR(IP11_14_12, MT0_PEN),
-	PINMUX_IPSR_GPSR(IP11_14_12, SPA_TRST),
-	PINMUX_IPSR_MSEL(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3),
-	PINMUX_IPSR_GPSR(IP11_14_12, ADICHS1_B),
-	PINMUX_IPSR_GPSR(IP11_17_15, VI1_DATA5_VI1_B5),
-	PINMUX_IPSR_MSEL(IP11_17_15, SD2_CMD, SEL_SD2_0),
-	PINMUX_IPSR_GPSR(IP11_17_15, MT0_SYNC),
-	PINMUX_IPSR_GPSR(IP11_17_15, SPA_TCK),
-	PINMUX_IPSR_MSEL(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3),
-	PINMUX_IPSR_GPSR(IP11_17_15, ADICHS2_B),
-	PINMUX_IPSR_GPSR(IP11_20_18, VI1_DATA6_VI1_B6),
-	PINMUX_IPSR_MSEL(IP11_20_18, SD2_CD, SEL_SD2_0),
-	PINMUX_IPSR_GPSR(IP11_20_18, MT0_VCXO),
-	PINMUX_IPSR_GPSR(IP11_20_18, SPA_TMS),
-	PINMUX_IPSR_GPSR(IP11_20_18, HSPI_TX1_D),
-	PINMUX_IPSR_GPSR(IP11_23_21, VI1_DATA7_VI1_B7),
-	PINMUX_IPSR_MSEL(IP11_23_21, SD2_WP, SEL_SD2_0),
-	PINMUX_IPSR_GPSR(IP11_23_21, MT0_PWM),
-	PINMUX_IPSR_GPSR(IP11_23_21, SPA_TDI),
-	PINMUX_IPSR_MSEL(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
-	PINMUX_IPSR_GPSR(IP11_26_24, VI1_G0),
-	PINMUX_IPSR_GPSR(IP11_26_24, VI3_DATA0),
-	PINMUX_IPSR_GPSR(IP11_26_24, TS_SCK1),
-	PINMUX_IPSR_MSEL(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
-	PINMUX_IPSR_GPSR(IP11_26_24, TX2),
-	PINMUX_IPSR_GPSR(IP11_26_24, SPA_TDO),
-	PINMUX_IPSR_MSEL(IP11_26_24, HCTS0_B, SEL_HSCIF0_1),
-	PINMUX_IPSR_GPSR(IP11_29_27, VI1_G1),
-	PINMUX_IPSR_GPSR(IP11_29_27, VI3_DATA1),
-	PINMUX_IPSR_GPSR(IP11_29_27, SSI_SCK1),
-	PINMUX_IPSR_GPSR(IP11_29_27, TS_SDEN1),
-	PINMUX_IPSR_GPSR(IP11_29_27, DACK2_B),
-	PINMUX_IPSR_MSEL(IP11_29_27, RX2, SEL_SCIF2_0),
-	PINMUX_IPSR_MSEL(IP11_29_27, HRTS0_B, SEL_HSCIF0_1),
-
-	PINMUX_IPSR_GPSR(IP12_2_0, VI1_G2),
-	PINMUX_IPSR_GPSR(IP12_2_0, VI3_DATA2),
-	PINMUX_IPSR_GPSR(IP12_2_0, SSI_WS1),
-	PINMUX_IPSR_GPSR(IP12_2_0, TS_SPSYNC1),
-	PINMUX_IPSR_MSEL(IP12_2_0, SCK2, SEL_SCIF2_0),
-	PINMUX_IPSR_MSEL(IP12_2_0, HSCK0_B, SEL_HSCIF0_1),
-	PINMUX_IPSR_GPSR(IP12_5_3, VI1_G3),
-	PINMUX_IPSR_GPSR(IP12_5_3, VI3_DATA3),
-	PINMUX_IPSR_GPSR(IP12_5_3, SSI_SCK2),
-	PINMUX_IPSR_GPSR(IP12_5_3, TS_SDAT1),
-	PINMUX_IPSR_MSEL(IP12_5_3, SCL1_C, SEL_I2C1_2),
-	PINMUX_IPSR_GPSR(IP12_5_3, HTX0_B),
-	PINMUX_IPSR_GPSR(IP12_8_6, VI1_G4),
-	PINMUX_IPSR_GPSR(IP12_8_6, VI3_DATA4),
-	PINMUX_IPSR_GPSR(IP12_8_6, SSI_WS2),
-	PINMUX_IPSR_MSEL(IP12_8_6, SDA1_C, SEL_I2C1_2),
-	PINMUX_IPSR_GPSR(IP12_8_6, SIM_RST_B),
-	PINMUX_IPSR_MSEL(IP12_8_6, HRX0_B, SEL_HSCIF0_1),
-	PINMUX_IPSR_GPSR(IP12_11_9, VI1_G5),
-	PINMUX_IPSR_GPSR(IP12_11_9, VI3_DATA5),
-	PINMUX_IPSR_MSEL(IP12_11_9, GPS_CLK, SEL_GPS_0),
-	PINMUX_IPSR_GPSR(IP12_11_9, FSE),
-	PINMUX_IPSR_GPSR(IP12_11_9, TX4_B),
-	PINMUX_IPSR_MSEL(IP12_11_9, SIM_D_B, SEL_SIM_1),
-	PINMUX_IPSR_GPSR(IP12_14_12, VI1_G6),
-	PINMUX_IPSR_GPSR(IP12_14_12, VI3_DATA6),
-	PINMUX_IPSR_MSEL(IP12_14_12, GPS_SIGN, SEL_GPS_0),
-	PINMUX_IPSR_GPSR(IP12_14_12, FRB),
-	PINMUX_IPSR_MSEL(IP12_14_12, RX4_B, SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP12_14_12, SIM_CLK_B),
-	PINMUX_IPSR_GPSR(IP12_17_15, VI1_G7),
-	PINMUX_IPSR_GPSR(IP12_17_15, VI3_DATA7),
-	PINMUX_IPSR_MSEL(IP12_17_15, GPS_MAG, SEL_GPS_0),
-	PINMUX_IPSR_GPSR(IP12_17_15, FCE),
-	PINMUX_IPSR_MSEL(IP12_17_15, SCK4_B, SEL_SCIF4_1),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	PINMUX_GPIO_GP_ALL(),
-};
-
-/* - DU0 -------------------------------------------------------------------- */
-static const unsigned int du0_rgb666_pins[] = {
-	/* R[7:2], G[7:2], B[7:2] */
-	RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
-	RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
-	RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),
-	RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29),
-	RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),  RCAR_GP_PIN(6, 6),
-	RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),  RCAR_GP_PIN(6, 3),
-};
-static const unsigned int du0_rgb666_mux[] = {
-	DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
-	DU0_DR3_MARK, DU0_DR2_MARK,
-	DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
-	DU0_DG3_MARK, DU0_DG2_MARK,
-	DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
-	DU0_DB3_MARK, DU0_DB2_MARK,
-};
-static const unsigned int du0_rgb888_pins[] = {
-	/* R[7:0], G[7:0], B[7:0] */
-	RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
-	RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
-	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), RCAR_GP_PIN(6, 2),
-	RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),  RCAR_GP_PIN(5, 31),
-	RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), RCAR_GP_PIN(0, 26),
-	RCAR_GP_PIN(0, 25), RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),
-	RCAR_GP_PIN(6, 6),  RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),
-	RCAR_GP_PIN(6, 3),  RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 27),
-};
-static const unsigned int du0_rgb888_mux[] = {
-	DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
-	DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
-	DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
-	DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
-	DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
-	DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
-};
-static const unsigned int du0_clk_in_pins[] = {
-	/* CLKIN */
-	RCAR_GP_PIN(0, 29),
-};
-static const unsigned int du0_clk_in_mux[] = {
-	DU0_DOTCLKIN_MARK,
-};
-static const unsigned int du0_clk_out_0_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(5, 20),
-};
-static const unsigned int du0_clk_out_0_mux[] = {
-	DU0_DOTCLKOUT0_MARK,
-};
-static const unsigned int du0_clk_out_1_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(0, 30),
-};
-static const unsigned int du0_clk_out_1_mux[] = {
-	DU0_DOTCLKOUT1_MARK,
-};
-static const unsigned int du0_sync_0_pins[] = {
-	/* VSYNC, HSYNC, DISP */
-	RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(0, 31),
-};
-static const unsigned int du0_sync_0_mux[] = {
-	DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
-	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
-};
-static const unsigned int du0_sync_1_pins[] = {
-	/* VSYNC, HSYNC, DISP */
-	RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(1, 0),
-};
-static const unsigned int du0_sync_1_mux[] = {
-	DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
-	DU0_DISP_MARK
-};
-static const unsigned int du0_oddf_pins[] = {
-	/* ODDF */
-	RCAR_GP_PIN(0, 31),
-};
-static const unsigned int du0_oddf_mux[] = {
-	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
-};
-static const unsigned int du0_cde_pins[] = {
-	/* CDE */
-	RCAR_GP_PIN(1, 1),
-};
-static const unsigned int du0_cde_mux[] = {
-	DU0_CDE_MARK
-};
-/* - DU1 -------------------------------------------------------------------- */
-static const unsigned int du1_rgb666_pins[] = {
-	/* R[7:2], G[7:2], B[7:2] */
-	RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
-	RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
-	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
-	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
-	RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
-	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 20),
-};
-static const unsigned int du1_rgb666_mux[] = {
-	DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
-	DU1_DR3_MARK, DU1_DR2_MARK,
-	DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
-	DU1_DG3_MARK, DU1_DG2_MARK,
-	DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
-	DU1_DB3_MARK, DU1_DB2_MARK,
-};
-static const unsigned int du1_rgb888_pins[] = {
-	/* R[7:0], G[7:0], B[7:0] */
-	RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
-	RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
-	RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 17),
-	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
-	RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11),
-	RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24),
-	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
-	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
-};
-static const unsigned int du1_rgb888_mux[] = {
-	DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
-	DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
-	DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
-	DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
-	DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
-	DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
-};
-static const unsigned int du1_clk_in_pins[] = {
-	/* CLKIN */
-	RCAR_GP_PIN(1, 26),
-};
-static const unsigned int du1_clk_in_mux[] = {
-	DU1_DOTCLKIN_MARK,
-};
-static const unsigned int du1_clk_out_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(1, 27),
-};
-static const unsigned int du1_clk_out_mux[] = {
-	DU1_DOTCLKOUT_MARK,
-};
-static const unsigned int du1_sync_0_pins[] = {
-	/* VSYNC, HSYNC, DISP */
-	RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 30),
-};
-static const unsigned int du1_sync_0_mux[] = {
-	DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
-	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
-};
-static const unsigned int du1_sync_1_pins[] = {
-	/* VSYNC, HSYNC, DISP */
-	RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 31),
-};
-static const unsigned int du1_sync_1_mux[] = {
-	DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
-	DU1_DISP_MARK
-};
-static const unsigned int du1_oddf_pins[] = {
-	/* ODDF */
-	RCAR_GP_PIN(1, 30),
-};
-static const unsigned int du1_oddf_mux[] = {
-	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
-};
-static const unsigned int du1_cde_pins[] = {
-	/* CDE */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int du1_cde_mux[] = {
-	DU1_CDE_MARK
-};
-/* - Ether ------------------------------------------------------------------ */
-static const unsigned int ether_rmii_pins[] = {
-	/*
-	 * ETH_TXD0, ETH_TXD1, ETH_TX_EN,  ETH_REFCLK,
-	 * ETH_RXD0, ETH_RXD1, ETH_CRS_DV, ETH_RX_ER,
-	 * ETH_MDIO, ETH_MDC
-	 */
-	RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 18),
-	RCAR_GP_PIN(2, 26),
-	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 17),
-	RCAR_GP_PIN(2, 19),
-	RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 28),
-};
-static const unsigned int ether_rmii_mux[] = {
-	ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK,  ETH_REFCLK_MARK,
-	ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
-	ETH_MDIO_MARK, ETH_MDC_MARK,
-};
-static const unsigned int ether_link_pins[] = {
-	/* ETH_LINK */
-	RCAR_GP_PIN(2, 24),
-};
-static const unsigned int ether_link_mux[] = {
-	ETH_LINK_MARK,
-};
-static const unsigned int ether_magic_pins[] = {
-	/* ETH_MAGIC */
-	RCAR_GP_PIN(2, 25),
-};
-static const unsigned int ether_magic_mux[] = {
-	ETH_MAGIC_MARK,
-};
-/* - HSCIF0 ----------------------------------------------------------------- */
-static const unsigned int hscif0_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21)
-};
-static const unsigned int hscif0_data_mux[] = {
-	HTX0_MARK, HRX0_MARK
-};
-static const unsigned int hscif0_data_b_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13)
-};
-static const unsigned int hscif0_data_b_mux[] = {
-	HTX0_B_MARK, HRX0_B_MARK
-};
-static const unsigned int hscif0_ctrl_pins[] = {
-	/* CTS, RTS */
-	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19)
-};
-static const unsigned int hscif0_ctrl_mux[] = {
-	HCTS0_MARK, HRTS0_MARK
-};
-static const unsigned int hscif0_ctrl_b_pins[] = {
-	/* CTS, RTS */
-	RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10)
-};
-static const unsigned int hscif0_ctrl_b_mux[] = {
-	HCTS0_B_MARK, HRTS0_B_MARK
-};
-static const unsigned int hscif0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 17)
-};
-static const unsigned int hscif0_clk_mux[] = {
-	HSCK0_MARK
-};
-static const unsigned int hscif0_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 11)
-};
-static const unsigned int hscif0_clk_b_mux[] = {
-	HSCK0_B_MARK
-};
-/* - HSCIF1 ----------------------------------------------------------------- */
-static const unsigned int hscif1_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20)
-};
-static const unsigned int hscif1_data_mux[] = {
-	HTX1_MARK, HRX1_MARK
-};
-static const unsigned int hscif1_data_b_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3)
-};
-static const unsigned int hscif1_data_b_mux[] = {
-	HTX1_B_MARK, HRX1_B_MARK
-};
-static const unsigned int hscif1_ctrl_pins[] = {
-	/* CTS, RTS */
-	RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22)
-};
-static const unsigned int hscif1_ctrl_mux[] = {
-	HCTS1_MARK, HRTS1_MARK
-};
-static const unsigned int hscif1_ctrl_b_pins[] = {
-	/* CTS, RTS */
-	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6)
-};
-static const unsigned int hscif1_ctrl_b_mux[] = {
-	HCTS1_B_MARK, HRTS1_B_MARK
-};
-static const unsigned int hscif1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 18)
-};
-static const unsigned int hscif1_clk_mux[] = {
-	HSCK1_MARK
-};
-static const unsigned int hscif1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 4)
-};
-static const unsigned int hscif1_clk_b_mux[] = {
-	HSCK1_B_MARK
-};
-/* - HSPI0 ------------------------------------------------------------------ */
-static const unsigned int hspi0_pins[] = {
-	/* CLK, CS, RX, TX */
-	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 25),
-	RCAR_GP_PIN(4, 24),
-};
-static const unsigned int hspi0_mux[] = {
-	HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK,
-};
-/* - HSPI1 ------------------------------------------------------------------ */
-static const unsigned int hspi1_pins[] = {
-	/* CLK, CS, RX, TX */
-	RCAR_GP_PIN(1, 31), RCAR_GP_PIN(1, 26), RCAR_GP_PIN(2, 0),
-	RCAR_GP_PIN(1, 30),
-};
-static const unsigned int hspi1_mux[] = {
-	HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK,
-};
-static const unsigned int hspi1_b_pins[] = {
-	/* CLK, CS, RX, TX */
-	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 29),
-	RCAR_GP_PIN(2, 28),
-};
-static const unsigned int hspi1_b_mux[] = {
-	HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK,
-};
-static const unsigned int hspi1_c_pins[] = {
-	/* CLK, CS, RX, TX */
-	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 16),
-	RCAR_GP_PIN(4, 15),
-};
-static const unsigned int hspi1_c_mux[] = {
-	HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK,
-};
-static const unsigned int hspi1_d_pins[] = {
-	/* CLK, CS, RX, TX */
-	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 8),
-	RCAR_GP_PIN(3, 7),
-};
-static const unsigned int hspi1_d_mux[] = {
-	HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK,
-};
-/* - HSPI2 ------------------------------------------------------------------ */
-static const unsigned int hspi2_pins[] = {
-	/* CLK, CS, RX, TX */
-	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-	RCAR_GP_PIN(0, 14),
-};
-static const unsigned int hspi2_mux[] = {
-	HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK,
-};
-static const unsigned int hspi2_b_pins[] = {
-	/* CLK, CS, RX, TX */
-	RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 8),
-	RCAR_GP_PIN(0, 6),
-};
-static const unsigned int hspi2_b_mux[] = {
-	HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
-};
-/* - I2C1 ------------------------------------------------------------------ */
-static const unsigned int i2c1_pins[] = {
-	/* SCL, SDA, */
-	RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
-};
-static const unsigned int i2c1_mux[] = {
-	SCL1_MARK, SDA1_MARK,
-};
-static const unsigned int i2c1_b_pins[] = {
-	/* SCL, SDA, */
-	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
-};
-static const unsigned int i2c1_b_mux[] = {
-	SCL1_B_MARK, SDA1_B_MARK,
-};
-static const unsigned int i2c1_c_pins[] = {
-	/* SCL, SDA, */
-	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
-};
-static const unsigned int i2c1_c_mux[] = {
-	SCL1_C_MARK, SDA1_C_MARK,
-};
-static const unsigned int i2c1_d_pins[] = {
-	/* SCL, SDA, */
-	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
-};
-static const unsigned int i2c1_d_mux[] = {
-	SCL1_D_MARK, SDA1_D_MARK,
-};
-/* - I2C2 ------------------------------------------------------------------ */
-static const unsigned int i2c2_pins[] = {
-	/* SCL, SDA, */
-	RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 26),
-};
-static const unsigned int i2c2_mux[] = {
-	SCL2_MARK, SDA2_MARK,
-};
-static const unsigned int i2c2_b_pins[] = {
-	/* SCL, SDA, */
-	RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
-};
-static const unsigned int i2c2_b_mux[] = {
-	SCL2_B_MARK, SDA2_B_MARK,
-};
-static const unsigned int i2c2_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 30),
-};
-static const unsigned int i2c2_c_mux[] = {
-	SCL2_C_MARK, SDA2_C_MARK,
-};
-static const unsigned int i2c2_d_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
-};
-static const unsigned int i2c2_d_mux[] = {
-	SCL2_D_MARK, SDA2_D_MARK,
-};
-/* - I2C3 ------------------------------------------------------------------ */
-static const unsigned int i2c3_pins[] = {
-	/* SCL, SDA, */
-	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 30),
-};
-static const unsigned int i2c3_mux[] = {
-	SCL3_MARK, SDA3_MARK,
-};
-static const unsigned int i2c3_b_pins[] = {
-	/* SCL, SDA, */
-	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30),
-};
-static const unsigned int i2c3_b_mux[] = {
-	SCL3_B_MARK, SDA3_B_MARK,
-};
-/* - INTC ------------------------------------------------------------------- */
-static const unsigned int intc_irq0_pins[] = {
-	/* IRQ */
-	RCAR_GP_PIN(2, 14),
-};
-static const unsigned int intc_irq0_mux[] = {
-	IRQ0_MARK,
-};
-static const unsigned int intc_irq0_b_pins[] = {
-	/* IRQ */
-	RCAR_GP_PIN(4, 13),
-};
-static const unsigned int intc_irq0_b_mux[] = {
-	IRQ0_B_MARK,
-};
-static const unsigned int intc_irq1_pins[] = {
-	/* IRQ */
-	RCAR_GP_PIN(2, 15),
-};
-static const unsigned int intc_irq1_mux[] = {
-	IRQ1_MARK,
-};
-static const unsigned int intc_irq1_b_pins[] = {
-	/* IRQ */
-	RCAR_GP_PIN(4, 14),
-};
-static const unsigned int intc_irq1_b_mux[] = {
-	IRQ1_B_MARK,
-};
-static const unsigned int intc_irq2_pins[] = {
-	/* IRQ */
-	RCAR_GP_PIN(2, 24),
-};
-static const unsigned int intc_irq2_mux[] = {
-	IRQ2_MARK,
-};
-static const unsigned int intc_irq2_b_pins[] = {
-	/* IRQ */
-	RCAR_GP_PIN(4, 15),
-};
-static const unsigned int intc_irq2_b_mux[] = {
-	IRQ2_B_MARK,
-};
-static const unsigned int intc_irq3_pins[] = {
-	/* IRQ */
-	RCAR_GP_PIN(2, 25),
-};
-static const unsigned int intc_irq3_mux[] = {
-	IRQ3_MARK,
-};
-static const unsigned int intc_irq3_b_pins[] = {
-	/* IRQ */
-	RCAR_GP_PIN(4, 16),
-};
-static const unsigned int intc_irq3_b_mux[] = {
-	IRQ3_B_MARK,
-};
-/* - LSBC ------------------------------------------------------------------- */
-static const unsigned int lbsc_cs0_pins[] = {
-	/* CS */
-	RCAR_GP_PIN(0, 13),
-};
-static const unsigned int lbsc_cs0_mux[] = {
-	CS0_MARK,
-};
-static const unsigned int lbsc_cs1_pins[] = {
-	/* CS */
-	RCAR_GP_PIN(0, 14),
-};
-static const unsigned int lbsc_cs1_mux[] = {
-	CS1_A26_MARK,
-};
-static const unsigned int lbsc_ex_cs0_pins[] = {
-	/* CS */
-	RCAR_GP_PIN(0, 15),
-};
-static const unsigned int lbsc_ex_cs0_mux[] = {
-	EX_CS0_MARK,
-};
-static const unsigned int lbsc_ex_cs1_pins[] = {
-	/* CS */
-	RCAR_GP_PIN(0, 16),
-};
-static const unsigned int lbsc_ex_cs1_mux[] = {
-	EX_CS1_MARK,
-};
-static const unsigned int lbsc_ex_cs2_pins[] = {
-	/* CS */
-	RCAR_GP_PIN(0, 17),
-};
-static const unsigned int lbsc_ex_cs2_mux[] = {
-	EX_CS2_MARK,
-};
-static const unsigned int lbsc_ex_cs3_pins[] = {
-	/* CS */
-	RCAR_GP_PIN(0, 18),
-};
-static const unsigned int lbsc_ex_cs3_mux[] = {
-	EX_CS3_MARK,
-};
-static const unsigned int lbsc_ex_cs4_pins[] = {
-	/* CS */
-	RCAR_GP_PIN(0, 19),
-};
-static const unsigned int lbsc_ex_cs4_mux[] = {
-	EX_CS4_MARK,
-};
-static const unsigned int lbsc_ex_cs5_pins[] = {
-	/* CS */
-	RCAR_GP_PIN(0, 20),
-};
-static const unsigned int lbsc_ex_cs5_mux[] = {
-	EX_CS5_MARK,
-};
-/* - MMCIF ------------------------------------------------------------------ */
-static const unsigned int mmc0_data1_pins[] = {
-	/* D[0] */
-	RCAR_GP_PIN(0, 19),
-};
-static const unsigned int mmc0_data1_mux[] = {
-	MMC0_D0_MARK,
-};
-static const unsigned int mmc0_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
-	RCAR_GP_PIN(0, 2),
-};
-static const unsigned int mmc0_data4_mux[] = {
-	MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
-};
-static const unsigned int mmc0_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
-	RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
-};
-static const unsigned int mmc0_data8_mux[] = {
-	MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
-	MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
-};
-static const unsigned int mmc0_ctrl_pins[] = {
-	/* CMD, CLK */
-	RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
-};
-static const unsigned int mmc0_ctrl_mux[] = {
-	MMC0_CMD_MARK, MMC0_CLK_MARK,
-};
-static const unsigned int mmc1_data1_pins[] = {
-	/* D[0] */
-	RCAR_GP_PIN(2, 8),
-};
-static const unsigned int mmc1_data1_mux[] = {
-	MMC1_D0_MARK,
-};
-static const unsigned int mmc1_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
-	RCAR_GP_PIN(2, 11),
-};
-static const unsigned int mmc1_data4_mux[] = {
-	MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
-};
-static const unsigned int mmc1_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(2, 8),  RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10),
-	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
-	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
-};
-static const unsigned int mmc1_data8_mux[] = {
-	MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
-	MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
-};
-static const unsigned int mmc1_ctrl_pins[] = {
-	/* CMD, CLK */
-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 1),
-};
-static const unsigned int mmc1_ctrl_mux[] = {
-	MMC1_CMD_MARK, MMC1_CLK_MARK,
-};
-/* - SCIF0 ------------------------------------------------------------------ */
-static const unsigned int scif0_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
-};
-static const unsigned int scif0_data_mux[] = {
-	RX0_MARK, TX0_MARK,
-};
-static const unsigned int scif0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 28),
-};
-static const unsigned int scif0_clk_mux[] = {
-	SCK0_MARK,
-};
-static const unsigned int scif0_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22),
-};
-static const unsigned int scif0_ctrl_mux[] = {
-	RTS0_TANS_MARK, CTS0_MARK,
-};
-static const unsigned int scif0_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
-};
-static const unsigned int scif0_data_b_mux[] = {
-	RX0_B_MARK, TX0_B_MARK,
-};
-static const unsigned int scif0_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 1),
-};
-static const unsigned int scif0_clk_b_mux[] = {
-	SCK0_B_MARK,
-};
-static const unsigned int scif0_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
-};
-static const unsigned int scif0_ctrl_b_mux[] = {
-	RTS0_B_TANS_B_MARK, CTS0_B_MARK,
-};
-static const unsigned int scif0_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
-};
-static const unsigned int scif0_data_c_mux[] = {
-	RX0_C_MARK, TX0_C_MARK,
-};
-static const unsigned int scif0_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 17),
-};
-static const unsigned int scif0_clk_c_mux[] = {
-	SCK0_C_MARK,
-};
-static const unsigned int scif0_ctrl_c_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
-};
-static const unsigned int scif0_ctrl_c_mux[] = {
-	RTS0_C_TANS_C_MARK, CTS0_C_MARK,
-};
-static const unsigned int scif0_data_d_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
-};
-static const unsigned int scif0_data_d_mux[] = {
-	RX0_D_MARK, TX0_D_MARK,
-};
-static const unsigned int scif0_clk_d_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 18),
-};
-static const unsigned int scif0_clk_d_mux[] = {
-	SCK0_D_MARK,
-};
-static const unsigned int scif0_ctrl_d_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 3),
-};
-static const unsigned int scif0_ctrl_d_mux[] = {
-	RTS0_D_TANS_D_MARK, CTS0_D_MARK,
-};
-/* - SCIF1 ------------------------------------------------------------------ */
-static const unsigned int scif1_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
-};
-static const unsigned int scif1_data_mux[] = {
-	RX1_MARK, TX1_MARK,
-};
-static const unsigned int scif1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 17),
-};
-static const unsigned int scif1_clk_mux[] = {
-	SCK1_MARK,
-};
-static const unsigned int scif1_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
-};
-static const unsigned int scif1_ctrl_mux[] = {
-	RTS1_TANS_MARK, CTS1_MARK,
-};
-static const unsigned int scif1_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 18),
-};
-static const unsigned int scif1_data_b_mux[] = {
-	RX1_B_MARK, TX1_B_MARK,
-};
-static const unsigned int scif1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 17),
-};
-static const unsigned int scif1_clk_b_mux[] = {
-	SCK1_B_MARK,
-};
-static const unsigned int scif1_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
-};
-static const unsigned int scif1_ctrl_b_mux[] = {
-	RTS1_B_TANS_B_MARK, CTS1_B_MARK,
-};
-static const unsigned int scif1_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
-};
-static const unsigned int scif1_data_c_mux[] = {
-	RX1_C_MARK, TX1_C_MARK,
-};
-static const unsigned int scif1_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 22),
-};
-static const unsigned int scif1_clk_c_mux[] = {
-	SCK1_C_MARK,
-};
-static const unsigned int scif1_ctrl_c_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
-};
-static const unsigned int scif1_ctrl_c_mux[] = {
-	RTS1_C_TANS_C_MARK, CTS1_C_MARK,
-};
-/* - SCIF2 ------------------------------------------------------------------ */
-static const unsigned int scif2_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 9),
-};
-static const unsigned int scif2_data_mux[] = {
-	RX2_MARK, TX2_MARK,
-};
-static const unsigned int scif2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 11),
-};
-static const unsigned int scif2_clk_mux[] = {
-	SCK2_MARK,
-};
-static const unsigned int scif2_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 23),
-};
-static const unsigned int scif2_data_b_mux[] = {
-	RX2_B_MARK, TX2_B_MARK,
-};
-static const unsigned int scif2_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 22),
-};
-static const unsigned int scif2_clk_b_mux[] = {
-	SCK2_B_MARK,
-};
-static const unsigned int scif2_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(0, 31),
-};
-static const unsigned int scif2_data_c_mux[] = {
-	RX2_C_MARK, TX2_C_MARK,
-};
-static const unsigned int scif2_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 0),
-};
-static const unsigned int scif2_clk_c_mux[] = {
-	SCK2_C_MARK,
-};
-static const unsigned int scif2_data_d_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
-};
-static const unsigned int scif2_data_d_mux[] = {
-	RX2_D_MARK, TX2_D_MARK,
-};
-static const unsigned int scif2_clk_d_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 31),
-};
-static const unsigned int scif2_clk_d_mux[] = {
-	SCK2_D_MARK,
-};
-static const unsigned int scif2_data_e_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
-};
-static const unsigned int scif2_data_e_mux[] = {
-	RX2_E_MARK, TX2_E_MARK,
-};
-/* - SCIF3 ------------------------------------------------------------------ */
-static const unsigned int scif3_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8),
-};
-static const unsigned int scif3_data_mux[] = {
-	RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK,
-};
-static const unsigned int scif3_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 7),
-};
-static const unsigned int scif3_clk_mux[] = {
-	SCK3_MARK,
-};
-
-static const unsigned int scif3_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
-};
-static const unsigned int scif3_data_b_mux[] = {
-	RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK,
-};
-static const unsigned int scif3_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 12),
-};
-static const unsigned int scif3_data_c_mux[] = {
-	RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK,
-};
-static const unsigned int scif3_data_d_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 29),
-};
-static const unsigned int scif3_data_d_mux[] = {
-	RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK,
-};
-static const unsigned int scif3_data_e_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
-};
-static const unsigned int scif3_data_e_mux[] = {
-	RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK,
-};
-static const unsigned int scif3_clk_e_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 10),
-};
-static const unsigned int scif3_clk_e_mux[] = {
-	SCK3_E_MARK,
-};
-/* - SCIF4 ------------------------------------------------------------------ */
-static const unsigned int scif4_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 26),
-};
-static const unsigned int scif4_data_mux[] = {
-	RX4_MARK, TX4_MARK,
-};
-static const unsigned int scif4_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 25),
-};
-static const unsigned int scif4_clk_mux[] = {
-	SCK4_MARK,
-};
-static const unsigned int scif4_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
-};
-static const unsigned int scif4_data_b_mux[] = {
-	RX4_B_MARK, TX4_B_MARK,
-};
-static const unsigned int scif4_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 16),
-};
-static const unsigned int scif4_clk_b_mux[] = {
-	SCK4_B_MARK,
-};
-static const unsigned int scif4_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
-};
-static const unsigned int scif4_data_c_mux[] = {
-	RX4_C_MARK, TX4_C_MARK,
-};
-static const unsigned int scif4_data_d_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
-};
-static const unsigned int scif4_data_d_mux[] = {
-	RX4_D_MARK, TX4_D_MARK,
-};
-/* - SCIF5 ------------------------------------------------------------------ */
-static const unsigned int scif5_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
-};
-static const unsigned int scif5_data_mux[] = {
-	RX5_MARK, TX5_MARK,
-};
-static const unsigned int scif5_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 11),
-};
-static const unsigned int scif5_clk_mux[] = {
-	SCK5_MARK,
-};
-static const unsigned int scif5_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
-};
-static const unsigned int scif5_data_b_mux[] = {
-	RX5_B_MARK, TX5_B_MARK,
-};
-static const unsigned int scif5_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 19),
-};
-static const unsigned int scif5_clk_b_mux[] = {
-	SCK5_B_MARK,
-};
-static const unsigned int scif5_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23),
-};
-static const unsigned int scif5_data_c_mux[] = {
-	RX5_C_MARK, TX5_C_MARK,
-};
-static const unsigned int scif5_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 28),
-};
-static const unsigned int scif5_clk_c_mux[] = {
-	SCK5_C_MARK,
-};
-static const unsigned int scif5_data_d_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6),
-};
-static const unsigned int scif5_data_d_mux[] = {
-	RX5_D_MARK, TX5_D_MARK,
-};
-static const unsigned int scif5_clk_d_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 7),
-};
-static const unsigned int scif5_clk_d_mux[] = {
-	SCK5_D_MARK,
-};
-/* - SCIF Clock ------------------------------------------------------------- */
-static const unsigned int scif_clk_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(4, 28),
-};
-static const unsigned int scif_clk_mux[] = {
-	SCIF_CLK_MARK,
-};
-static const unsigned int scif_clk_b_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(4, 5),
-};
-static const unsigned int scif_clk_b_mux[] = {
-	SCIF_CLK_B_MARK,
-};
-static const unsigned int scif_clk_c_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(4, 18),
-};
-static const unsigned int scif_clk_c_mux[] = {
-	SCIF_CLK_C_MARK,
-};
-static const unsigned int scif_clk_d_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(2, 29),
-};
-static const unsigned int scif_clk_d_mux[] = {
-	SCIF_CLK_D_MARK,
-};
-/* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 21),
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SD0_DAT0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
-	RCAR_GP_PIN(3, 24),
-};
-static const unsigned int sdhi0_data4_mux[] = {
-	SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
-};
-static const unsigned int sdhi0_ctrl_pins[] = {
-	/* CMD, CLK */
-	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 17),
-};
-static const unsigned int sdhi0_ctrl_mux[] = {
-	SD0_CMD_MARK, SD0_CLK_MARK,
-};
-static const unsigned int sdhi0_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(3, 19),
-};
-static const unsigned int sdhi0_cd_mux[] = {
-	SD0_CD_MARK,
-};
-static const unsigned int sdhi0_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(3, 20),
-};
-static const unsigned int sdhi0_wp_mux[] = {
-	SD0_WP_MARK,
-};
-/* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(0, 19),
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	SD1_DAT0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
-	RCAR_GP_PIN(0, 2),
-};
-static const unsigned int sdhi1_data4_mux[] = {
-	SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
-};
-static const unsigned int sdhi1_ctrl_pins[] = {
-	/* CMD, CLK */
-	RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
-};
-static const unsigned int sdhi1_ctrl_mux[] = {
-	SD1_CMD_MARK, SD1_CLK_MARK,
-};
-static const unsigned int sdhi1_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(0, 10),
-};
-static const unsigned int sdhi1_cd_mux[] = {
-	SD1_CD_MARK,
-};
-static const unsigned int sdhi1_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(0, 11),
-};
-static const unsigned int sdhi1_wp_mux[] = {
-	SD1_WP_MARK,
-};
-/* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 1),
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SD2_DAT0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
-	RCAR_GP_PIN(3, 4),
-};
-static const unsigned int sdhi2_data4_mux[] = {
-	SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
-};
-static const unsigned int sdhi2_ctrl_pins[] = {
-	/* CMD, CLK */
-	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
-};
-static const unsigned int sdhi2_ctrl_mux[] = {
-	SD2_CMD_MARK, SD2_CLK_MARK,
-};
-static const unsigned int sdhi2_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(3, 7),
-};
-static const unsigned int sdhi2_cd_mux[] = {
-	SD2_CD_MARK,
-};
-static const unsigned int sdhi2_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(3, 8),
-};
-static const unsigned int sdhi2_wp_mux[] = {
-	SD2_WP_MARK,
-};
-/* - SDHI3 ------------------------------------------------------------------ */
-static const unsigned int sdhi3_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(1, 18),
-};
-static const unsigned int sdhi3_data1_mux[] = {
-	SD3_DAT0_MARK,
-};
-static const unsigned int sdhi3_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20),
-	RCAR_GP_PIN(1, 21),
-};
-static const unsigned int sdhi3_data4_mux[] = {
-	SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
-};
-static const unsigned int sdhi3_ctrl_pins[] = {
-	/* CMD, CLK */
-	RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
-};
-static const unsigned int sdhi3_ctrl_mux[] = {
-	SD3_CMD_MARK, SD3_CLK_MARK,
-};
-static const unsigned int sdhi3_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(1, 30),
-};
-static const unsigned int sdhi3_cd_mux[] = {
-	SD3_CD_MARK,
-};
-static const unsigned int sdhi3_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int sdhi3_wp_mux[] = {
-	SD3_WP_MARK,
-};
-/* - USB0 ------------------------------------------------------------------- */
-static const unsigned int usb0_pins[] = {
-	/* PENC */
-	RCAR_GP_PIN(4, 26),
-};
-static const unsigned int usb0_mux[] = {
-	USB_PENC0_MARK,
-};
-static const unsigned int usb0_ovc_pins[] = {
-	/* USB_OVC */
-	RCAR_GP_PIN(4, 22),
-};
-static const unsigned int usb0_ovc_mux[] = {
-	USB_OVC0_MARK,
-};
-/* - USB1 ------------------------------------------------------------------- */
-static const unsigned int usb1_pins[] = {
-	/* PENC */
-	RCAR_GP_PIN(4, 27),
-};
-static const unsigned int usb1_mux[] = {
-	USB_PENC1_MARK,
-};
-static const unsigned int usb1_ovc_pins[] = {
-	/* USB_OVC */
-	RCAR_GP_PIN(4, 24),
-};
-static const unsigned int usb1_ovc_mux[] = {
-	USB_OVC1_MARK,
-};
-/* - USB2 ------------------------------------------------------------------- */
-static const unsigned int usb2_pins[] = {
-	/* PENC */
-	RCAR_GP_PIN(4, 28),
-};
-static const unsigned int usb2_mux[] = {
-	USB_PENC2_MARK,
-};
-static const unsigned int usb2_ovc_pins[] = {
-	/* USB_OVC */
-	RCAR_GP_PIN(3, 29),
-};
-static const unsigned int usb2_ovc_mux[] = {
-	USB_OVC2_MARK,
-};
-/* - VIN0 ------------------------------------------------------------------- */
-static const unsigned int vin0_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 8),
-	RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
-	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
-};
-static const unsigned int vin0_data8_mux[] = {
-	VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK,
-	VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
-	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
-};
-static const unsigned int vin0_clk_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(2, 1),
-};
-static const unsigned int vin0_clk_mux[] = {
-	VI0_CLK_MARK,
-};
-static const unsigned int vin0_sync_pins[] = {
-	/* HSYNC, VSYNC */
-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-};
-static const unsigned int vin0_sync_mux[] = {
-	VI0_HSYNC_MARK, VI0_VSYNC_MARK,
-};
-/* - VIN1 ------------------------------------------------------------------- */
-static const unsigned int vin1_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
-	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
-	RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
-};
-static const unsigned int vin1_data8_mux[] = {
-	VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK,
-	VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
-	VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
-};
-static const unsigned int vin1_clk_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(2, 30),
-};
-static const unsigned int vin1_clk_mux[] = {
-	VI1_CLK_MARK,
-};
-static const unsigned int vin1_sync_pins[] = {
-	/* HSYNC, VSYNC */
-	RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0),
-};
-static const unsigned int vin1_sync_mux[] = {
-	VI1_HSYNC_MARK, VI1_VSYNC_MARK,
-};
-/* - VIN2 ------------------------------------------------------------------- */
-static const unsigned int vin2_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
-	RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
-	RCAR_GP_PIN(1, 31), RCAR_GP_PIN(2, 0),
-};
-static const unsigned int vin2_data8_mux[] = {
-	VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, VI2_DATA2_VI2_B2_MARK,
-	VI2_DATA3_VI2_B3_MARK, VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
-	VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
-};
-static const unsigned int vin2_clk_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(1, 30),
-};
-static const unsigned int vin2_clk_mux[] = {
-	VI2_CLK_MARK,
-};
-static const unsigned int vin2_sync_pins[] = {
-	/* HSYNC, VSYNC */
-	RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
-};
-static const unsigned int vin2_sync_mux[] = {
-	VI2_HSYNC_MARK, VI2_VSYNC_MARK,
-};
-/* - VIN3 ------------------------------------------------------------------- */
-static const unsigned int vin3_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
-	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
-};
-static const unsigned int vin3_data8_mux[] = {
-	VI3_DATA0_MARK, VI3_DATA1_MARK, VI3_DATA2_MARK,
-	VI3_DATA3_MARK, VI3_DATA4_MARK, VI3_DATA5_MARK,
-	VI3_DATA6_MARK, VI3_DATA7_MARK,
-};
-static const unsigned int vin3_clk_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(2, 31),
-};
-static const unsigned int vin3_clk_mux[] = {
-	VI3_CLK_MARK,
-};
-static const unsigned int vin3_sync_pins[] = {
-	/* HSYNC, VSYNC */
-	RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
-};
-static const unsigned int vin3_sync_mux[] = {
-	VI3_HSYNC_MARK, VI3_VSYNC_MARK,
-};
-
-static const struct sh_pfc_pin_group pinmux_groups[] = {
-	SH_PFC_PIN_GROUP(du0_rgb666),
-	SH_PFC_PIN_GROUP(du0_rgb888),
-	SH_PFC_PIN_GROUP(du0_clk_in),
-	SH_PFC_PIN_GROUP(du0_clk_out_0),
-	SH_PFC_PIN_GROUP(du0_clk_out_1),
-	SH_PFC_PIN_GROUP(du0_sync_0),
-	SH_PFC_PIN_GROUP(du0_sync_1),
-	SH_PFC_PIN_GROUP(du0_oddf),
-	SH_PFC_PIN_GROUP(du0_cde),
-	SH_PFC_PIN_GROUP(du1_rgb666),
-	SH_PFC_PIN_GROUP(du1_rgb888),
-	SH_PFC_PIN_GROUP(du1_clk_in),
-	SH_PFC_PIN_GROUP(du1_clk_out),
-	SH_PFC_PIN_GROUP(du1_sync_0),
-	SH_PFC_PIN_GROUP(du1_sync_1),
-	SH_PFC_PIN_GROUP(du1_oddf),
-	SH_PFC_PIN_GROUP(du1_cde),
-	SH_PFC_PIN_GROUP(ether_rmii),
-	SH_PFC_PIN_GROUP(ether_link),
-	SH_PFC_PIN_GROUP(ether_magic),
-	SH_PFC_PIN_GROUP(hscif0_data),
-	SH_PFC_PIN_GROUP(hscif0_data_b),
-	SH_PFC_PIN_GROUP(hscif0_ctrl),
-	SH_PFC_PIN_GROUP(hscif0_ctrl_b),
-	SH_PFC_PIN_GROUP(hscif0_clk),
-	SH_PFC_PIN_GROUP(hscif0_clk_b),
-	SH_PFC_PIN_GROUP(hscif1_data),
-	SH_PFC_PIN_GROUP(hscif1_data_b),
-	SH_PFC_PIN_GROUP(hscif1_ctrl),
-	SH_PFC_PIN_GROUP(hscif1_ctrl_b),
-	SH_PFC_PIN_GROUP(hscif1_clk),
-	SH_PFC_PIN_GROUP(hscif1_clk_b),
-	SH_PFC_PIN_GROUP(hspi0),
-	SH_PFC_PIN_GROUP(hspi1),
-	SH_PFC_PIN_GROUP(hspi1_b),
-	SH_PFC_PIN_GROUP(hspi1_c),
-	SH_PFC_PIN_GROUP(hspi1_d),
-	SH_PFC_PIN_GROUP(hspi2),
-	SH_PFC_PIN_GROUP(hspi2_b),
-	SH_PFC_PIN_GROUP(i2c1),
-	SH_PFC_PIN_GROUP(i2c1_b),
-	SH_PFC_PIN_GROUP(i2c1_c),
-	SH_PFC_PIN_GROUP(i2c1_d),
-	SH_PFC_PIN_GROUP(i2c2),
-	SH_PFC_PIN_GROUP(i2c2_b),
-	SH_PFC_PIN_GROUP(i2c2_c),
-	SH_PFC_PIN_GROUP(i2c2_d),
-	SH_PFC_PIN_GROUP(i2c3),
-	SH_PFC_PIN_GROUP(i2c3_b),
-	SH_PFC_PIN_GROUP(intc_irq0),
-	SH_PFC_PIN_GROUP(intc_irq0_b),
-	SH_PFC_PIN_GROUP(intc_irq1),
-	SH_PFC_PIN_GROUP(intc_irq1_b),
-	SH_PFC_PIN_GROUP(intc_irq2),
-	SH_PFC_PIN_GROUP(intc_irq2_b),
-	SH_PFC_PIN_GROUP(intc_irq3),
-	SH_PFC_PIN_GROUP(intc_irq3_b),
-	SH_PFC_PIN_GROUP(lbsc_cs0),
-	SH_PFC_PIN_GROUP(lbsc_cs1),
-	SH_PFC_PIN_GROUP(lbsc_ex_cs0),
-	SH_PFC_PIN_GROUP(lbsc_ex_cs1),
-	SH_PFC_PIN_GROUP(lbsc_ex_cs2),
-	SH_PFC_PIN_GROUP(lbsc_ex_cs3),
-	SH_PFC_PIN_GROUP(lbsc_ex_cs4),
-	SH_PFC_PIN_GROUP(lbsc_ex_cs5),
-	SH_PFC_PIN_GROUP(mmc0_data1),
-	SH_PFC_PIN_GROUP(mmc0_data4),
-	SH_PFC_PIN_GROUP(mmc0_data8),
-	SH_PFC_PIN_GROUP(mmc0_ctrl),
-	SH_PFC_PIN_GROUP(mmc1_data1),
-	SH_PFC_PIN_GROUP(mmc1_data4),
-	SH_PFC_PIN_GROUP(mmc1_data8),
-	SH_PFC_PIN_GROUP(mmc1_ctrl),
-	SH_PFC_PIN_GROUP(scif0_data),
-	SH_PFC_PIN_GROUP(scif0_clk),
-	SH_PFC_PIN_GROUP(scif0_ctrl),
-	SH_PFC_PIN_GROUP(scif0_data_b),
-	SH_PFC_PIN_GROUP(scif0_clk_b),
-	SH_PFC_PIN_GROUP(scif0_ctrl_b),
-	SH_PFC_PIN_GROUP(scif0_data_c),
-	SH_PFC_PIN_GROUP(scif0_clk_c),
-	SH_PFC_PIN_GROUP(scif0_ctrl_c),
-	SH_PFC_PIN_GROUP(scif0_data_d),
-	SH_PFC_PIN_GROUP(scif0_clk_d),
-	SH_PFC_PIN_GROUP(scif0_ctrl_d),
-	SH_PFC_PIN_GROUP(scif1_data),
-	SH_PFC_PIN_GROUP(scif1_clk),
-	SH_PFC_PIN_GROUP(scif1_ctrl),
-	SH_PFC_PIN_GROUP(scif1_data_b),
-	SH_PFC_PIN_GROUP(scif1_clk_b),
-	SH_PFC_PIN_GROUP(scif1_ctrl_b),
-	SH_PFC_PIN_GROUP(scif1_data_c),
-	SH_PFC_PIN_GROUP(scif1_clk_c),
-	SH_PFC_PIN_GROUP(scif1_ctrl_c),
-	SH_PFC_PIN_GROUP(scif2_data),
-	SH_PFC_PIN_GROUP(scif2_clk),
-	SH_PFC_PIN_GROUP(scif2_data_b),
-	SH_PFC_PIN_GROUP(scif2_clk_b),
-	SH_PFC_PIN_GROUP(scif2_data_c),
-	SH_PFC_PIN_GROUP(scif2_clk_c),
-	SH_PFC_PIN_GROUP(scif2_data_d),
-	SH_PFC_PIN_GROUP(scif2_clk_d),
-	SH_PFC_PIN_GROUP(scif2_data_e),
-	SH_PFC_PIN_GROUP(scif3_data),
-	SH_PFC_PIN_GROUP(scif3_clk),
-	SH_PFC_PIN_GROUP(scif3_data_b),
-	SH_PFC_PIN_GROUP(scif3_data_c),
-	SH_PFC_PIN_GROUP(scif3_data_d),
-	SH_PFC_PIN_GROUP(scif3_data_e),
-	SH_PFC_PIN_GROUP(scif3_clk_e),
-	SH_PFC_PIN_GROUP(scif4_data),
-	SH_PFC_PIN_GROUP(scif4_clk),
-	SH_PFC_PIN_GROUP(scif4_data_b),
-	SH_PFC_PIN_GROUP(scif4_clk_b),
-	SH_PFC_PIN_GROUP(scif4_data_c),
-	SH_PFC_PIN_GROUP(scif4_data_d),
-	SH_PFC_PIN_GROUP(scif5_data),
-	SH_PFC_PIN_GROUP(scif5_clk),
-	SH_PFC_PIN_GROUP(scif5_data_b),
-	SH_PFC_PIN_GROUP(scif5_clk_b),
-	SH_PFC_PIN_GROUP(scif5_data_c),
-	SH_PFC_PIN_GROUP(scif5_clk_c),
-	SH_PFC_PIN_GROUP(scif5_data_d),
-	SH_PFC_PIN_GROUP(scif5_clk_d),
-	SH_PFC_PIN_GROUP(scif_clk),
-	SH_PFC_PIN_GROUP(scif_clk_b),
-	SH_PFC_PIN_GROUP(scif_clk_c),
-	SH_PFC_PIN_GROUP(scif_clk_d),
-	SH_PFC_PIN_GROUP(sdhi0_data1),
-	SH_PFC_PIN_GROUP(sdhi0_data4),
-	SH_PFC_PIN_GROUP(sdhi0_ctrl),
-	SH_PFC_PIN_GROUP(sdhi0_cd),
-	SH_PFC_PIN_GROUP(sdhi0_wp),
-	SH_PFC_PIN_GROUP(sdhi1_data1),
-	SH_PFC_PIN_GROUP(sdhi1_data4),
-	SH_PFC_PIN_GROUP(sdhi1_ctrl),
-	SH_PFC_PIN_GROUP(sdhi1_cd),
-	SH_PFC_PIN_GROUP(sdhi1_wp),
-	SH_PFC_PIN_GROUP(sdhi2_data1),
-	SH_PFC_PIN_GROUP(sdhi2_data4),
-	SH_PFC_PIN_GROUP(sdhi2_ctrl),
-	SH_PFC_PIN_GROUP(sdhi2_cd),
-	SH_PFC_PIN_GROUP(sdhi2_wp),
-	SH_PFC_PIN_GROUP(sdhi3_data1),
-	SH_PFC_PIN_GROUP(sdhi3_data4),
-	SH_PFC_PIN_GROUP(sdhi3_ctrl),
-	SH_PFC_PIN_GROUP(sdhi3_cd),
-	SH_PFC_PIN_GROUP(sdhi3_wp),
-	SH_PFC_PIN_GROUP(usb0),
-	SH_PFC_PIN_GROUP(usb0_ovc),
-	SH_PFC_PIN_GROUP(usb1),
-	SH_PFC_PIN_GROUP(usb1_ovc),
-	SH_PFC_PIN_GROUP(usb2),
-	SH_PFC_PIN_GROUP(usb2_ovc),
-	SH_PFC_PIN_GROUP(vin0_data8),
-	SH_PFC_PIN_GROUP(vin0_clk),
-	SH_PFC_PIN_GROUP(vin0_sync),
-	SH_PFC_PIN_GROUP(vin1_data8),
-	SH_PFC_PIN_GROUP(vin1_clk),
-	SH_PFC_PIN_GROUP(vin1_sync),
-	SH_PFC_PIN_GROUP(vin2_data8),
-	SH_PFC_PIN_GROUP(vin2_clk),
-	SH_PFC_PIN_GROUP(vin2_sync),
-	SH_PFC_PIN_GROUP(vin3_data8),
-	SH_PFC_PIN_GROUP(vin3_clk),
-	SH_PFC_PIN_GROUP(vin3_sync),
-};
-
-static const char * const du0_groups[] = {
-	"du0_rgb666",
-	"du0_rgb888",
-	"du0_clk_in",
-	"du0_clk_out_0",
-	"du0_clk_out_1",
-	"du0_sync_0",
-	"du0_sync_1",
-	"du0_oddf",
-	"du0_cde",
-};
-
-static const char * const du1_groups[] = {
-	"du1_rgb666",
-	"du1_rgb888",
-	"du1_clk_in",
-	"du1_clk_out",
-	"du1_sync_0",
-	"du1_sync_1",
-	"du1_oddf",
-	"du1_cde",
-};
-
-static const char * const ether_groups[] = {
-	"ether_rmii",
-	"ether_link",
-	"ether_magic",
-};
-
-static const char * const hscif0_groups[] = {
-	"hscif0_data",
-	"hscif0_data_b",
-	"hscif0_ctrl",
-	"hscif0_ctrl_b",
-	"hscif0_clk",
-	"hscif0_clk_b",
-};
-
-static const char * const hscif1_groups[] = {
-	"hscif1_data",
-	"hscif1_data_b",
-	"hscif1_ctrl",
-	"hscif1_ctrl_b",
-	"hscif1_clk",
-	"hscif1_clk_b",
-};
-
-static const char * const hspi0_groups[] = {
-	"hspi0",
-};
-
-static const char * const hspi1_groups[] = {
-	"hspi1",
-	"hspi1_b",
-	"hspi1_c",
-	"hspi1_d",
-};
-
-static const char * const hspi2_groups[] = {
-	"hspi2",
-	"hspi2_b",
-};
-
-static const char * const i2c1_groups[] = {
-	"i2c1",
-	"i2c1_b",
-	"i2c1_c",
-	"i2c1_d",
-};
-
-static const char * const i2c2_groups[] = {
-	"i2c2",
-	"i2c2_b",
-	"i2c2_c",
-	"i2c2_d",
-};
-
-static const char * const i2c3_groups[] = {
-	"i2c3",
-	"i2c3_b",
-};
-
-static const char * const intc_groups[] = {
-	"intc_irq0",
-	"intc_irq0_b",
-	"intc_irq1",
-	"intc_irq1_b",
-	"intc_irq2",
-	"intc_irq2_b",
-	"intc_irq3",
-	"intc_irq3_b",
-};
-
-static const char * const lbsc_groups[] = {
-	"lbsc_cs0",
-	"lbsc_cs1",
-	"lbsc_ex_cs0",
-	"lbsc_ex_cs1",
-	"lbsc_ex_cs2",
-	"lbsc_ex_cs3",
-	"lbsc_ex_cs4",
-	"lbsc_ex_cs5",
-};
-
-static const char * const mmc0_groups[] = {
-	"mmc0_data1",
-	"mmc0_data4",
-	"mmc0_data8",
-	"mmc0_ctrl",
-};
-
-static const char * const mmc1_groups[] = {
-	"mmc1_data1",
-	"mmc1_data4",
-	"mmc1_data8",
-	"mmc1_ctrl",
-};
-
-static const char * const scif0_groups[] = {
-	"scif0_data",
-	"scif0_clk",
-	"scif0_ctrl",
-	"scif0_data_b",
-	"scif0_clk_b",
-	"scif0_ctrl_b",
-	"scif0_data_c",
-	"scif0_clk_c",
-	"scif0_ctrl_c",
-	"scif0_data_d",
-	"scif0_clk_d",
-	"scif0_ctrl_d",
-};
-
-static const char * const scif1_groups[] = {
-	"scif1_data",
-	"scif1_clk",
-	"scif1_ctrl",
-	"scif1_data_b",
-	"scif1_clk_b",
-	"scif1_ctrl_b",
-	"scif1_data_c",
-	"scif1_clk_c",
-	"scif1_ctrl_c",
-};
-
-static const char * const scif2_groups[] = {
-	"scif2_data",
-	"scif2_clk",
-	"scif2_data_b",
-	"scif2_clk_b",
-	"scif2_data_c",
-	"scif2_clk_c",
-	"scif2_data_d",
-	"scif2_clk_d",
-	"scif2_data_e",
-};
-
-static const char * const scif3_groups[] = {
-	"scif3_data",
-	"scif3_clk",
-	"scif3_data_b",
-	"scif3_data_c",
-	"scif3_data_d",
-	"scif3_data_e",
-	"scif3_clk_e",
-};
-
-static const char * const scif4_groups[] = {
-	"scif4_data",
-	"scif4_clk",
-	"scif4_data_b",
-	"scif4_clk_b",
-	"scif4_data_c",
-	"scif4_data_d",
-};
-
-static const char * const scif5_groups[] = {
-	"scif5_data",
-	"scif5_clk",
-	"scif5_data_b",
-	"scif5_clk_b",
-	"scif5_data_c",
-	"scif5_clk_c",
-	"scif5_data_d",
-	"scif5_clk_d",
-};
-
-static const char * const scif_clk_groups[] = {
-	"scif_clk",
-	"scif_clk_b",
-	"scif_clk_c",
-	"scif_clk_d",
-};
-
-static const char * const sdhi0_groups[] = {
-	"sdhi0_data1",
-	"sdhi0_data4",
-	"sdhi0_ctrl",
-	"sdhi0_cd",
-	"sdhi0_wp",
-};
-
-static const char * const sdhi1_groups[] = {
-	"sdhi1_data1",
-	"sdhi1_data4",
-	"sdhi1_ctrl",
-	"sdhi1_cd",
-	"sdhi1_wp",
-};
-
-static const char * const sdhi2_groups[] = {
-	"sdhi2_data1",
-	"sdhi2_data4",
-	"sdhi2_ctrl",
-	"sdhi2_cd",
-	"sdhi2_wp",
-};
-
-static const char * const sdhi3_groups[] = {
-	"sdhi3_data1",
-	"sdhi3_data4",
-	"sdhi3_ctrl",
-	"sdhi3_cd",
-	"sdhi3_wp",
-};
-
-static const char * const usb0_groups[] = {
-	"usb0",
-	"usb0_ovc",
-};
-
-static const char * const usb1_groups[] = {
-	"usb1",
-	"usb1_ovc",
-};
-
-static const char * const usb2_groups[] = {
-	"usb2",
-	"usb2_ovc",
-};
-
-static const char * const vin0_groups[] = {
-	"vin0_data8",
-	"vin0_clk",
-	"vin0_sync",
-};
-
-static const char * const vin1_groups[] = {
-	"vin1_data8",
-	"vin1_clk",
-	"vin1_sync",
-};
-
-static const char * const vin2_groups[] = {
-	"vin2_data8",
-	"vin2_clk",
-	"vin2_sync",
-};
-
-static const char * const vin3_groups[] = {
-	"vin3_data8",
-	"vin3_clk",
-	"vin3_sync",
-};
-
-static const struct sh_pfc_function pinmux_functions[] = {
-	SH_PFC_FUNCTION(du0),
-	SH_PFC_FUNCTION(du1),
-	SH_PFC_FUNCTION(ether),
-	SH_PFC_FUNCTION(hscif0),
-	SH_PFC_FUNCTION(hscif1),
-	SH_PFC_FUNCTION(hspi0),
-	SH_PFC_FUNCTION(hspi1),
-	SH_PFC_FUNCTION(hspi2),
-	SH_PFC_FUNCTION(i2c1),
-	SH_PFC_FUNCTION(i2c2),
-	SH_PFC_FUNCTION(i2c3),
-	SH_PFC_FUNCTION(intc),
-	SH_PFC_FUNCTION(lbsc),
-	SH_PFC_FUNCTION(mmc0),
-	SH_PFC_FUNCTION(mmc1),
-	SH_PFC_FUNCTION(sdhi0),
-	SH_PFC_FUNCTION(sdhi1),
-	SH_PFC_FUNCTION(sdhi2),
-	SH_PFC_FUNCTION(sdhi3),
-	SH_PFC_FUNCTION(scif0),
-	SH_PFC_FUNCTION(scif1),
-	SH_PFC_FUNCTION(scif2),
-	SH_PFC_FUNCTION(scif3),
-	SH_PFC_FUNCTION(scif4),
-	SH_PFC_FUNCTION(scif5),
-	SH_PFC_FUNCTION(scif_clk),
-	SH_PFC_FUNCTION(usb0),
-	SH_PFC_FUNCTION(usb1),
-	SH_PFC_FUNCTION(usb2),
-	SH_PFC_FUNCTION(vin0),
-	SH_PFC_FUNCTION(vin1),
-	SH_PFC_FUNCTION(vin2),
-	SH_PFC_FUNCTION(vin3),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	{ PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1, GROUP(
-		GP_0_31_FN, FN_IP3_31_29,
-		GP_0_30_FN, FN_IP3_26_24,
-		GP_0_29_FN, FN_IP3_22_21,
-		GP_0_28_FN, FN_IP3_14_12,
-		GP_0_27_FN, FN_IP3_11_9,
-		GP_0_26_FN, FN_IP3_2_0,
-		GP_0_25_FN, FN_IP2_30_28,
-		GP_0_24_FN, FN_IP2_21_19,
-		GP_0_23_FN, FN_IP2_18_16,
-		GP_0_22_FN, FN_IP0_30_28,
-		GP_0_21_FN, FN_IP0_5_3,
-		GP_0_20_FN, FN_IP1_18_15,
-		GP_0_19_FN, FN_IP1_14_11,
-		GP_0_18_FN, FN_IP1_10_7,
-		GP_0_17_FN, FN_IP1_6_4,
-		GP_0_16_FN, FN_IP1_3_2,
-		GP_0_15_FN, FN_IP1_1_0,
-		GP_0_14_FN, FN_IP0_27_26,
-		GP_0_13_FN, FN_IP0_25,
-		GP_0_12_FN, FN_IP0_24_23,
-		GP_0_11_FN, FN_IP0_22_19,
-		GP_0_10_FN, FN_IP0_18_16,
-		GP_0_9_FN, FN_IP0_15_14,
-		GP_0_8_FN, FN_IP0_13_12,
-		GP_0_7_FN, FN_IP0_11_10,
-		GP_0_6_FN, FN_IP0_9_8,
-		GP_0_5_FN, FN_A19,
-		GP_0_4_FN, FN_A18,
-		GP_0_3_FN, FN_A17,
-		GP_0_2_FN, FN_IP0_7_6,
-		GP_0_1_FN, FN_AVS2,
-		GP_0_0_FN, FN_AVS1 ))
-	},
-	{ PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1, GROUP(
-		GP_1_31_FN, FN_IP5_23_21,
-		GP_1_30_FN, FN_IP5_20_17,
-		GP_1_29_FN, FN_IP5_16_15,
-		GP_1_28_FN, FN_IP5_14_13,
-		GP_1_27_FN, FN_IP5_12_11,
-		GP_1_26_FN, FN_IP5_10_9,
-		GP_1_25_FN, FN_IP5_8,
-		GP_1_24_FN, FN_IP5_7,
-		GP_1_23_FN, FN_IP5_6,
-		GP_1_22_FN, FN_IP5_5,
-		GP_1_21_FN, FN_IP5_4,
-		GP_1_20_FN, FN_IP5_3,
-		GP_1_19_FN, FN_IP5_2_0,
-		GP_1_18_FN, FN_IP4_31_29,
-		GP_1_17_FN, FN_IP4_28,
-		GP_1_16_FN, FN_IP4_27,
-		GP_1_15_FN, FN_IP4_26,
-		GP_1_14_FN, FN_IP4_25,
-		GP_1_13_FN, FN_IP4_24,
-		GP_1_12_FN, FN_IP4_23,
-		GP_1_11_FN, FN_IP4_22_20,
-		GP_1_10_FN, FN_IP4_19_17,
-		GP_1_9_FN, FN_IP4_16,
-		GP_1_8_FN, FN_IP4_15,
-		GP_1_7_FN, FN_IP4_14,
-		GP_1_6_FN, FN_IP4_13,
-		GP_1_5_FN, FN_IP4_12,
-		GP_1_4_FN, FN_IP4_11,
-		GP_1_3_FN, FN_IP4_10_8,
-		GP_1_2_FN, FN_IP4_7_5,
-		GP_1_1_FN, FN_IP4_4_2,
-		GP_1_0_FN, FN_IP4_1_0 ))
-	},
-	{ PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1, GROUP(
-		GP_2_31_FN, FN_IP10_28_26,
-		GP_2_30_FN, FN_IP10_25_24,
-		GP_2_29_FN, FN_IP10_23_21,
-		GP_2_28_FN, FN_IP10_20_18,
-		GP_2_27_FN, FN_IP10_17_15,
-		GP_2_26_FN, FN_IP10_14_12,
-		GP_2_25_FN, FN_IP10_11_9,
-		GP_2_24_FN, FN_IP10_8_6,
-		GP_2_23_FN, FN_IP10_5_3,
-		GP_2_22_FN, FN_IP10_2_0,
-		GP_2_21_FN, FN_IP9_29_28,
-		GP_2_20_FN, FN_IP9_27_26,
-		GP_2_19_FN, FN_IP9_25_24,
-		GP_2_18_FN, FN_IP9_23_22,
-		GP_2_17_FN, FN_IP9_21_19,
-		GP_2_16_FN, FN_IP9_18_16,
-		GP_2_15_FN, FN_IP9_15_14,
-		GP_2_14_FN, FN_IP9_13_12,
-		GP_2_13_FN, FN_IP9_11_10,
-		GP_2_12_FN, FN_IP9_9_8,
-		GP_2_11_FN, FN_IP9_7,
-		GP_2_10_FN, FN_IP9_6,
-		GP_2_9_FN, FN_IP9_5,
-		GP_2_8_FN, FN_IP9_4,
-		GP_2_7_FN, FN_IP9_3_2,
-		GP_2_6_FN, FN_IP9_1_0,
-		GP_2_5_FN, FN_IP8_30_28,
-		GP_2_4_FN, FN_IP8_27_25,
-		GP_2_3_FN, FN_IP8_24_23,
-		GP_2_2_FN, FN_IP8_22_21,
-		GP_2_1_FN, FN_IP8_20,
-		GP_2_0_FN, FN_IP5_27_24 ))
-	},
-	{ PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1, GROUP(
-		GP_3_31_FN, FN_IP6_3_2,
-		GP_3_30_FN, FN_IP6_1_0,
-		GP_3_29_FN, FN_IP5_30_29,
-		GP_3_28_FN, FN_IP5_28,
-		GP_3_27_FN, FN_IP1_24_23,
-		GP_3_26_FN, FN_IP1_22_21,
-		GP_3_25_FN, FN_IP1_20_19,
-		GP_3_24_FN, FN_IP7_26_25,
-		GP_3_23_FN, FN_IP7_24_23,
-		GP_3_22_FN, FN_IP7_22_21,
-		GP_3_21_FN, FN_IP7_20_19,
-		GP_3_20_FN, FN_IP7_30_29,
-		GP_3_19_FN, FN_IP7_28_27,
-		GP_3_18_FN, FN_IP7_18_17,
-		GP_3_17_FN, FN_IP7_16_15,
-		GP_3_16_FN, FN_IP12_17_15,
-		GP_3_15_FN, FN_IP12_14_12,
-		GP_3_14_FN, FN_IP12_11_9,
-		GP_3_13_FN, FN_IP12_8_6,
-		GP_3_12_FN, FN_IP12_5_3,
-		GP_3_11_FN, FN_IP12_2_0,
-		GP_3_10_FN, FN_IP11_29_27,
-		GP_3_9_FN, FN_IP11_26_24,
-		GP_3_8_FN, FN_IP11_23_21,
-		GP_3_7_FN, FN_IP11_20_18,
-		GP_3_6_FN, FN_IP11_17_15,
-		GP_3_5_FN, FN_IP11_14_12,
-		GP_3_4_FN, FN_IP11_11_9,
-		GP_3_3_FN, FN_IP11_8_6,
-		GP_3_2_FN, FN_IP11_5_3,
-		GP_3_1_FN, FN_IP11_2_0,
-		GP_3_0_FN, FN_IP10_31_29 ))
-	},
-	{ PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1, GROUP(
-		GP_4_31_FN, FN_IP8_19,
-		GP_4_30_FN, FN_IP8_18,
-		GP_4_29_FN, FN_IP8_17_16,
-		GP_4_28_FN, FN_IP0_2_0,
-		GP_4_27_FN, FN_USB_PENC1,
-		GP_4_26_FN, FN_USB_PENC0,
-		GP_4_25_FN, FN_IP8_15_12,
-		GP_4_24_FN, FN_IP8_11_8,
-		GP_4_23_FN, FN_IP8_7_4,
-		GP_4_22_FN, FN_IP8_3_0,
-		GP_4_21_FN, FN_IP2_3_0,
-		GP_4_20_FN, FN_IP1_28_25,
-		GP_4_19_FN, FN_IP2_15_12,
-		GP_4_18_FN, FN_IP2_11_8,
-		GP_4_17_FN, FN_IP2_7_4,
-		GP_4_16_FN, FN_IP7_14_13,
-		GP_4_15_FN, FN_IP7_12_10,
-		GP_4_14_FN, FN_IP7_9_7,
-		GP_4_13_FN, FN_IP7_6_4,
-		GP_4_12_FN, FN_IP7_3_2,
-		GP_4_11_FN, FN_IP7_1_0,
-		GP_4_10_FN, FN_IP6_30_29,
-		GP_4_9_FN, FN_IP6_26_25,
-		GP_4_8_FN, FN_IP6_24_23,
-		GP_4_7_FN, FN_IP6_22_20,
-		GP_4_6_FN, FN_IP6_19_18,
-		GP_4_5_FN, FN_IP6_17_15,
-		GP_4_4_FN, FN_IP6_14_12,
-		GP_4_3_FN, FN_IP6_11_9,
-		GP_4_2_FN, FN_IP6_8,
-		GP_4_1_FN, FN_IP6_7_6,
-		GP_4_0_FN, FN_IP6_5_4 ))
-	},
-	{ PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1, GROUP(
-		GP_5_31_FN, FN_IP3_5,
-		GP_5_30_FN, FN_IP3_4,
-		GP_5_29_FN, FN_IP3_3,
-		GP_5_28_FN, FN_IP2_27,
-		GP_5_27_FN, FN_IP2_26,
-		GP_5_26_FN, FN_IP2_25,
-		GP_5_25_FN, FN_IP2_24,
-		GP_5_24_FN, FN_IP2_23,
-		GP_5_23_FN, FN_IP2_22,
-		GP_5_22_FN, FN_IP3_28,
-		GP_5_21_FN, FN_IP3_27,
-		GP_5_20_FN, FN_IP3_23,
-		GP_5_19_FN, FN_EX_WAIT0,
-		GP_5_18_FN, FN_WE1,
-		GP_5_17_FN, FN_WE0,
-		GP_5_16_FN, FN_RD,
-		GP_5_15_FN, FN_A16,
-		GP_5_14_FN, FN_A15,
-		GP_5_13_FN, FN_A14,
-		GP_5_12_FN, FN_A13,
-		GP_5_11_FN, FN_A12,
-		GP_5_10_FN, FN_A11,
-		GP_5_9_FN, FN_A10,
-		GP_5_8_FN, FN_A9,
-		GP_5_7_FN, FN_A8,
-		GP_5_6_FN, FN_A7,
-		GP_5_5_FN, FN_A6,
-		GP_5_4_FN, FN_A5,
-		GP_5_3_FN, FN_A4,
-		GP_5_2_FN, FN_A3,
-		GP_5_1_FN, FN_A2,
-		GP_5_0_FN, FN_A1 ))
-	},
-	{ PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_6_8_FN, FN_IP3_20,
-		GP_6_7_FN, FN_IP3_19,
-		GP_6_6_FN, FN_IP3_18,
-		GP_6_5_FN, FN_IP3_17,
-		GP_6_4_FN, FN_IP3_16,
-		GP_6_3_FN, FN_IP3_15,
-		GP_6_2_FN, FN_IP3_8,
-		GP_6_1_FN, FN_IP3_7,
-		GP_6_0_FN, FN_IP3_6 ))
-	},
-
-	{ PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
-			     GROUP(1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3),
-			     GROUP(
-		/* IP0_31 [1] */
-		0, 0,
-		/* IP0_30_28 [3] */
-		FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
-		FN_HRTS1, FN_RX4_C, 0, 0,
-		/* IP0_27_26 [2] */
-		FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B, 0,
-		/* IP0_25 [1] */
-		FN_CS0, FN_HSPI_CS2_B,
-		/* IP0_24_23 [2] */
-		FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B, 0,
-		/* IP0_22_19 [4] */
-		FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
-		FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
-		FN_CTS0_B, 0, 0, 0,
-		0, 0, 0, 0,
-		/* IP0_18_16 [3] */
-		FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
-		FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B, 0,
-		/* IP0_15_14 [2] */
-		FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
-		/* IP0_13_12 [2] */
-		FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
-		/* IP0_11_10 [2] */
-		FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B, 0,
-		/* IP0_9_8 [2] */
-		FN_A20, FN_TX5_D, FN_HSPI_TX2_B, 0,
-		/* IP0_7_6 [2] */
-		FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
-		/* IP0_5_3 [3] */
-		FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
-		FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
-		/* IP0_2_0 [3] */
-		FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
-		FN_SCIF_CLK, FN_TCLK0_C, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
-			     GROUP(3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2),
-			     GROUP(
-		/* IP1_31_29 [3] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP1_28_25 [4] */
-		FN_HTX0, FN_TX1, FN_SDATA, FN_CTS0_C,
-		FN_SUB_TCK, FN_CC5_STATE2, FN_CC5_STATE10, FN_CC5_STATE18,
-		FN_CC5_STATE26, FN_CC5_STATE34, 0, 0,
-		0, 0, 0, 0,
-		/* IP1_24_23 [2] */
-		FN_MLB_DAT, FN_PWM4, FN_RX4, 0,
-		/* IP1_22_21 [2] */
-		FN_MLB_SIG, FN_PWM3, FN_TX4, 0,
-		/* IP1_20_19 [2] */
-		FN_MLB_CLK, FN_PWM2, FN_SCK4, 0,
-		/* IP1_18_15 [4] */
-		FN_EX_CS5, FN_SD1_DAT1, FN_MMC0_D1, FN_FD1,
-		FN_ATAWR0, FN_VI1_R6, FN_HRX1, FN_RX2_E,
-		FN_RX0_B, FN_SSI_WS9, 0, 0,
-		0, 0, 0, 0,
-		/* IP1_14_11 [4] */
-		FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
-		FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
-		FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, 0,
-		0, 0, 0, 0,
-		/* IP1_10_7 [4] */
-		FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD, FN_FRE,
-		FN_ATACS10, FN_VI1_R4, FN_RX5_B, FN_HSCK1,
-		FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9, 0,
-		0, 0, 0, 0,
-		/* IP1_6_4 [3] */
-		FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
-		FN_ATACS00, 0, 0, 0,
-		/* IP1_3_2 [2] */
-		FN_EX_CS1, FN_MMC0_D7, FN_FD7, 0,
-		/* IP1_1_0 [2] */
-		FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
-			     GROUP(1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4),
-			     GROUP(
-		/* IP2_31 [1] */
-		0, 0,
-		/* IP2_30_28 [3] */
-		FN_DU0_DG0, FN_LCDOUT8, FN_DREQ1, FN_SCL2,
-		FN_AUDATA2, 0, 0, 0,
-		/* IP2_27 [1] */
-		FN_DU0_DR7, FN_LCDOUT7,
-		/* IP2_26 [1] */
-		FN_DU0_DR6, FN_LCDOUT6,
-		/* IP2_25 [1] */
-		FN_DU0_DR5, FN_LCDOUT5,
-		/* IP2_24 [1] */
-		FN_DU0_DR4, FN_LCDOUT4,
-		/* IP2_23 [1] */
-		FN_DU0_DR3, FN_LCDOUT3,
-		/* IP2_22 [1] */
-		FN_DU0_DR2, FN_LCDOUT2,
-		/* IP2_21_19 [3] */
-		FN_DU0_DR1, FN_LCDOUT1, FN_DACK0, FN_DRACK0,
-		FN_GPS_SIGN_B, FN_AUDATA1, FN_RX5_C, 0,
-		/* IP2_18_16 [3] */
-		FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0, FN_GPS_CLK_B,
-		FN_AUDATA0, FN_TX5_C, 0, 0,
-		/* IP2_15_12 [4] */
-		FN_HRTS0, FN_RTS1_TANS, FN_MDATA, FN_TX0_C,
-		FN_SUB_TMS, FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17,
-		FN_CC5_STATE25, FN_CC5_STATE33, 0, 0,
-		0, 0, 0, 0,
-		/* IP2_11_8 [4] */
-		FN_HCTS0, FN_CTS1, FN_STM, FN_PWM0_D,
-		FN_RX0_C, FN_SCIF_CLK_C, FN_SUB_TRST, FN_TCLK1_B,
-		FN_CC5_OSCOUT, 0, 0, 0,
-		0, 0, 0, 0,
-		/* IP2_7_4 [4] */
-		FN_HSCK0, FN_SCK1, FN_MTS, FN_PWM5,
-		FN_SCK0_C, FN_SSI_SDATA9_B, FN_SUB_TDO, FN_CC5_STATE0,
-		FN_CC5_STATE8, FN_CC5_STATE16, FN_CC5_STATE24, FN_CC5_STATE32,
-		0, 0, 0, 0,
-		/* IP2_3_0 [4] */
-		FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
-		FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
-		FN_CC5_STATE27, FN_CC5_STATE35, 0, 0,
-		0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
-			     GROUP(3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1, 1,
-				   3, 3, 1, 1, 1, 1, 1, 1, 3),
-			     GROUP(
-	    /* IP3_31_29 [3] */
-	    FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, FN_TX2_C,
-	    FN_SCL2_C, FN_REMOCON, 0, 0,
-	    /* IP3_28 [1] */
-	    FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
-	    /* IP3_27 [1] */
-	    FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
-	    /* IP3_26_24 [3] */
-	    FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
-	    FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, 0,
-	    /* IP3_23 [1] */
-	    FN_DU0_DOTCLKOUT0, FN_QCLK,
-	    /* IP3_22_21 [2] */
-	    FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_TX3_D_IRDA_TX_D, FN_SCL3_B,
-	    /* IP3_20 [1] */
-	    FN_DU0_DB7, FN_LCDOUT23,
-	    /* IP3_19 [1] */
-	    FN_DU0_DB6, FN_LCDOUT22,
-	    /* IP3_18 [1] */
-	    FN_DU0_DB5, FN_LCDOUT21,
-	    /* IP3_17 [1] */
-	    FN_DU0_DB4, FN_LCDOUT20,
-	    /* IP3_16 [1] */
-	    FN_DU0_DB3, FN_LCDOUT19,
-	    /* IP3_15 [1] */
-	    FN_DU0_DB2, FN_LCDOUT18,
-	    /* IP3_14_12 [3] */
-	    FN_DU0_DB1, FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1,
-	    FN_GPS_MAG_B, FN_AUDATA5, FN_SCK5_C, 0,
-	    /* IP3_11_9 [3] */
-	    FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1, FN_SCL1,
-	    FN_TCLK1, FN_AUDATA4, 0, 0,
-	    /* IP3_8 [1] */
-	    FN_DU0_DG7, FN_LCDOUT15,
-	    /* IP3_7 [1] */
-	    FN_DU0_DG6, FN_LCDOUT14,
-	    /* IP3_6 [1] */
-	    FN_DU0_DG5, FN_LCDOUT13,
-	    /* IP3_5 [1] */
-	    FN_DU0_DG4, FN_LCDOUT12,
-	    /* IP3_4 [1] */
-	    FN_DU0_DG3, FN_LCDOUT11,
-	    /* IP3_3 [1] */
-	    FN_DU0_DG2, FN_LCDOUT10,
-	    /* IP3_2_0 [3] */
-	    FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
-	    FN_AUDATA3, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
-			     GROUP(3, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
-				   1, 1, 1, 3, 3, 3, 2),
-			     GROUP(
-	    /* IP4_31_29 [3] */
-	    FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0,
-	    FN_TX5, FN_SCK0_D, 0, 0,
-	    /* IP4_28 [1] */
-	    FN_DU1_DG7, FN_VI2_R3,
-	    /* IP4_27 [1] */
-	    FN_DU1_DG6, FN_VI2_R2,
-	    /* IP4_26 [1] */
-	    FN_DU1_DG5, FN_VI2_R1,
-	    /* IP4_25 [1] */
-	    FN_DU1_DG4, FN_VI2_R0,
-	    /* IP4_24 [1] */
-	    FN_DU1_DG3, FN_VI2_G7,
-	    /* IP4_23 [1] */
-	    FN_DU1_DG2, FN_VI2_G6,
-	    /* IP4_22_20 [3] */
-	    FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
-	    FN_SCK5, FN_AUDATA7, FN_RX0_D, 0,
-	    /* IP4_19_17 [3] */
-	    FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B, FN_SD3_DAT2,
-	    FN_SCK3_E, FN_AUDATA6, FN_TX0_D, 0,
-	    /* IP4_16 [1] */
-	    FN_DU1_DR7, FN_VI2_G5,
-	    /* IP4_15 [1] */
-	    FN_DU1_DR6, FN_VI2_G4,
-	    /* IP4_14 [1] */
-	    FN_DU1_DR5, FN_VI2_G3,
-	    /* IP4_13 [1] */
-	    FN_DU1_DR4, FN_VI2_G2,
-	    /* IP4_12 [1] */
-	    FN_DU1_DR3, FN_VI2_G1,
-	    /* IP4_11 [1] */
-	    FN_DU1_DR2, FN_VI2_G0,
-	    /* IP4_10_8 [3] */
-	    FN_DU1_DR1, FN_VI2_DATA1_VI2_B1, FN_PWM0, FN_SD3_CMD,
-	    FN_RX3_E_IRDA_RX_E, FN_AUDSYNC, FN_CTS0_D, 0,
-	    /* IP4_7_5 [3] */
-	    FN_DU1_DR0, FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK,
-	    FN_TX3_E_IRDA_TX_E, FN_AUDCK, FN_PWMFSW0_B, 0,
-	    /* IP4_4_2 [3] */
-	    FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
-	    FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, 0,
-	    /* IP4_1_0 [2] */
-	    FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
-			     GROUP(1, 2, 1, 4, 3, 4, 2, 2, 2, 2, 1, 1,
-				   1, 1, 1, 1, 3),
-			     GROUP(
-	    /* IP5_31 [1] */
-	    0, 0,
-	    /* IP5_30_29 [2] */
-	    FN_AUDIO_CLKB, FN_USB_OVC2, FN_CAN_DEBUGOUT0, FN_MOUT0,
-	    /* IP5_28 [1] */
-	    FN_AUDIO_CLKA, FN_CAN_TXCLK,
-	    /* IP5_27_24 [4] */
-	    FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B, FN_SD3_WP,
-	    FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD, FN_AUDIO_CLKOUT,
-	    FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D, 0,
-	    0, 0, 0, 0,
-	    /* IP5_23_21 [3] */
-	    FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
-	    FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
-	    /* IP5_20_17 [4] */
-	    FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
-	    FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
-	    FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D, 0,
-	    0, 0, 0, 0,
-	    /* IP5_16_15 [2] */
-	    FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC, 0,
-	    /* IP5_14_13 [2] */
-	    FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC, FN_VI3_HSYNC, 0,
-	    /* IP5_12_11 [2] */
-	    FN_DU1_DOTCLKOUT, FN_VI2_FIELD, FN_SDA1_D, 0,
-	    /* IP5_10_9 [2] */
-	    FN_DU1_DOTCLKIN, FN_VI2_CLKENB, FN_HSPI_CS1, FN_SCL1_D,
-	    /* IP5_8 [1] */
-	    FN_DU1_DB7, FN_SDA2_D,
-	    /* IP5_7 [1] */
-	    FN_DU1_DB6, FN_SCL2_D,
-	    /* IP5_6 [1] */
-	    FN_DU1_DB5, FN_VI2_R7,
-	    /* IP5_5 [1] */
-	    FN_DU1_DB4, FN_VI2_R6,
-	    /* IP5_4 [1] */
-	    FN_DU1_DB3, FN_VI2_R5,
-	    /* IP5_3 [1] */
-	    FN_DU1_DB2, FN_VI2_R4,
-	    /* IP5_2_0 [3] */
-	    FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
-	    FN_RX5, FN_RTS0_D_TANS_D, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
-			     GROUP(1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2,
-				   2, 2, 2),
-			     GROUP(
-	    /* IP6_31 [1] */
-	    0, 0,
-	    /* IP6_30_29 [2] */
-	    FN_SSI_SCK6, FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
-	    /* IP_28_27 [2] */
-	    0, 0, 0, 0,
-	    /* IP6_26_25 [2] */
-	    FN_SSI_SDATA5, FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX,
-	    /* IP6_24_23 [2] */
-	    FN_SSI_WS5, FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX,
-	    /* IP6_22_20 [3] */
-	    FN_SSI_SCK5, FN_ADICLK, FN_CAN_DEBUGOUT10, FN_SCK3,
-	    FN_TCLK0_D, 0, 0, 0,
-	    /* IP6_19_18 [2] */
-	    FN_SSI_SDATA4, FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, 0,
-	    /* IP6_17_15 [3] */
-	    FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
-	    FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, 0,
-	    /* IP6_14_12 [3] */
-	    FN_SSI_WS34, FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX,
-	    FN_SSI_WS9_C, 0, 0, 0,
-	    /* IP6_11_9 [3] */
-	    FN_SSI_SCK34, FN_CAN_DEBUGOUT6, FN_CAN0_TX_B, FN_IERX,
-	    FN_SSI_SCK9_C, 0, 0, 0,
-	    /* IP6_8 [1] */
-	    FN_SSI_SDATA2, FN_CAN_DEBUGOUT5,
-	    /* IP6_7_6 [2] */
-	    FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6, 0,
-	    /* IP6_5_4 [2] */
-	    FN_SSI_SDATA0, FN_CAN_DEBUGOUT3, FN_MOUT5, 0,
-	    /* IP6_3_2 [2] */
-	    FN_SSI_WS0129, FN_CAN_DEBUGOUT2, FN_MOUT2, 0,
-	    /* IP6_1_0 [2] */
-	    FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
-			     GROUP(1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,
-				   3, 2, 2),
-			     GROUP(
-	    /* IP7_31 [1] */
-	    0, 0,
-	    /* IP7_30_29 [2] */
-	    FN_SD0_WP, FN_DACK2, FN_CTS1_B, 0,
-	    /* IP7_28_27 [2] */
-	    FN_SD0_CD, FN_DREQ2, FN_RTS1_B_TANS_B, 0,
-	    /* IP7_26_25 [2] */
-	    FN_SD0_DAT3, FN_ATAWR1, FN_RX2_B, FN_CC5_TDI,
-	    /* IP7_24_23 [2] */
-	    FN_SD0_DAT2, FN_ATARD1, FN_TX2_B, FN_CC5_TCK,
-	    /* IP7_22_21 [2] */
-	    FN_SD0_DAT1, FN_ATAG1, FN_SCK2_B, FN_CC5_TMS,
-	    /* IP7_20_19 [2] */
-	    FN_SD0_DAT0, FN_ATADIR1, FN_RX1_B, FN_CC5_TRST,
-	    /* IP7_18_17 [2] */
-	    FN_SD0_CMD, FN_ATACS11, FN_TX1_B, FN_CC5_TDO,
-	    /* IP7_16_15 [2] */
-	    FN_SD0_CLK, FN_ATACS01, FN_SCK1_B, 0,
-	    /* IP7_14_13 [2] */
-	    FN_SSI_SDATA8, FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C,
-	    /* IP7_12_10 [3] */
-	    FN_SSI_SDATA7, FN_CAN_DEBUGOUT15, FN_IRQ2_B, FN_TCLK1_C,
-	    FN_HSPI_TX1_C, 0, 0, 0,
-	    /* IP7_9_7 [3] */
-	    FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B, FN_SSI_WS9_B,
-	    FN_HSPI_CS1_C, 0, 0, 0,
-	    /* IP7_6_4 [3] */
-	    FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
-	    FN_HSPI_CLK1_C, 0, 0, 0,
-	    /* IP7_3_2 [2] */
-	    FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
-	    /* IP7_1_0 [2] */
-	    FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
-			     GROUP(1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4),
-			     GROUP(
-	    /* IP8_31 [1] */
-	    0, 0,
-	    /* IP8_30_28 [3] */
-	    FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, FN_RTS1_C_TANS_C, FN_RX4_D,
-	    FN_PWMFSW0_C, 0, 0, 0,
-	    /* IP8_27_25 [3] */
-	    FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
-	    FN_MMC1_CMD, FN_HSCK1_B, 0, 0,
-	    /* IP8_24_23 [2] */
-	    FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B, 0,
-	    /* IP8_22_21 [2] */
-	    FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B, FN_MT1_SYNC,
-	    /* IP8_20 [1] */
-	    FN_VI0_CLK, FN_MMC1_CLK,
-	    /* IP8_19 [1] */
-	    FN_FMIN, FN_RDS_DATA,
-	    /* IP8_18 [1] */
-	    FN_BPFCLK, FN_PCMWE,
-	    /* IP8_17_16 [2] */
-	    FN_FMCLK, FN_RDS_CLK, FN_PCMOE, 0,
-	    /* IP8_15_12 [4] */
-	    FN_HSPI_RX0, FN_RX0, FN_CAN_STEP0, FN_AD_NCS,
-	    FN_CC5_STATE7, FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31,
-	    FN_CC5_STATE39, 0, 0, 0,
-	    0, 0, 0, 0,
-	    /* IP8_11_8 [4] */
-	    FN_HSPI_TX0, FN_TX0, FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO,
-	    FN_CC5_STATE6, FN_CC5_STATE14, FN_CC5_STATE22, FN_CC5_STATE30,
-	    FN_CC5_STATE38, 0, 0, 0,
-	    0, 0, 0, 0,
-	    /* IP8_7_4 [4] */
-	    FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1, FN_AD_DI,
-	    FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21, FN_CC5_STATE29,
-	    FN_CC5_STATE37, 0, 0, 0,
-	    0, 0, 0, 0,
-	    /* IP8_3_0 [4] */
-	    FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
-	    FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
-	    FN_CC5_STATE36, 0, 0, 0,
-	    0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
-			     GROUP(2, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 1,
-				   1, 1, 1, 2, 2),
-			     GROUP(
-	    /* IP9_31_30 [2] */
-	    0, 0, 0, 0,
-	    /* IP9_29_28 [2] */
-	    FN_VI0_G7, FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
-	    /* IP9_27_26 [2] */
-	    FN_VI0_G6, FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8,
-	    /* IP9_25_24 [2] */
-	    FN_VI0_G5, FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7,
-	    /* IP9_23_22 [2] */
-	    FN_VI0_G4, FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6,
-	    /* IP9_21_19 [3] */
-	    FN_VI0_G3, FN_ETH_CRS_DV, FN_MMC1_D7, FN_ARM_TRACEDATA_5,
-	    FN_TS_SDAT0, 0, 0, 0,
-	    /* IP9_18_16 [3] */
-	    FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6, FN_ARM_TRACEDATA_4,
-	    FN_TS_SPSYNC0, 0, 0, 0,
-	    /* IP9_15_14 [2] */
-	    FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1, FN_ARM_TRACEDATA_3,
-	    /* IP9_13_12 [2] */
-	    FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0, FN_ARM_TRACEDATA_2,
-	    /* IP9_11_10 [2] */
-	    FN_VI0_DATA7_VI0_B7, FN_MMC1_D5, FN_ARM_TRACEDATA_1, 0,
-	    /* IP9_9_8 [2] */
-	    FN_VI0_DATA6_VI0_B6, FN_MMC1_D4, FN_ARM_TRACEDATA_0, 0,
-	    /* IP9_7 [1] */
-	    FN_VI0_DATA5_VI0_B5, FN_MMC1_D3,
-	    /* IP9_6 [1] */
-	    FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
-	    /* IP9_5 [1] */
-	    FN_VI0_DATA3_VI0_B3, FN_MMC1_D1,
-	    /* IP9_4 [1] */
-	    FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
-	    /* IP9_3_2 [2] */
-	    FN_VI0_DATA1_VI0_B1, FN_HCTS1_B, FN_MT1_PWM, 0,
-	    /* IP9_1_0 [2] */
-	    FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
-			     GROUP(3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3),
-			     GROUP(
-	    /* IP10_31_29 [3] */
-	    FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, FN_SIM_CLK,
-	    FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 0,
-	    /* IP10_28_26 [3] */
-	    FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
-	    FN_PWMFSW0_E, 0, 0, 0,
-	    /* IP10_25_24 [2] */
-	    FN_VI1_CLK, FN_SIM_D, FN_SDA3, 0,
-	    /* IP10_23_21 [3] */
-	    FN_VI0_R7, FN_ETH_MDIO, FN_DACK2_C, FN_HSPI_RX1_B,
-	    FN_SCIF_CLK_D, FN_TRACECTL, FN_MT1_PEN, 0,
-	    /* IP10_20_18 [3] */
-	    FN_VI0_R6, FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B,
-	    FN_TRACECLK, FN_MT1_BEN, FN_PWMFSW0_D, 0,
-	    /* IP10_17_15 [3] */
-	    FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
-	    FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, 0,
-	    /* IP10_14_12 [3] */
-	    FN_VI0_R4, FN_ETH_REFCLK, FN_SD2_CD_B, FN_HSPI_CLK1_B,
-	    FN_ARM_TRACEDATA_14, FN_MT1_CLK, FN_TS_SCK0, 0,
-	    /* IP10_11_9 [3] */
-	    FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B, FN_IRQ3,
-	    FN_ARM_TRACEDATA_13, 0, 0, 0,
-	    /* IP10_8_6 [3] */
-	    FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
-	    FN_ARM_TRACEDATA_12, 0, 0, 0,
-	    /* IP10_5_3 [3] */
-	    FN_VI0_R1, FN_SSI_SDATA8_C, FN_DACK1_B, FN_ARM_TRACEDATA_11,
-	    FN_DACK0_C, FN_DRACK0_C, 0, 0,
-	    /* IP10_2_0 [3] */
-	    FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
-	    FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32,
-			     GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
-			     GROUP(
-	    /* IP11_31_30 [2] */
-	    0, 0, 0, 0,
-	    /* IP11_29_27 [3] */
-	    FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1,
-	    FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0,
-	    /* IP11_26_24 [3] */
-	    FN_VI1_G0, FN_VI3_DATA0, 0, FN_TS_SCK1,
-	    FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B,
-	    /* IP11_23_21 [3] */
-	    FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI,
-	    FN_HSPI_RX1_D, 0, 0, 0,
-	    /* IP11_20_18 [3] */
-	    FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
-	    FN_HSPI_TX1_D, 0, 0, 0,
-	    /* IP11_17_15 [3] */
-	    FN_VI1_DATA5_VI1_B5, FN_SD2_CMD, FN_MT0_SYNC, FN_SPA_TCK,
-	    FN_HSPI_CS1_D, FN_ADICHS2_B, 0, 0,
-	    /* IP11_14_12 [3] */
-	    FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
-	    FN_HSPI_CLK1_D, FN_ADICHS1_B, 0, 0,
-	    /* IP11_11_9 [3] */
-	    FN_VI1_DATA3_VI1_B3, FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO,
-	    FN_ADICHS0_B, 0, 0, 0,
-	    /* IP11_8_6 [3] */
-	    FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2, FN_MT0_D, FN_SPVTDI,
-	    FN_ADIDATA_B, 0, 0, 0,
-	    /* IP11_5_3 [3] */
-	    FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK, FN_SPV_TMS,
-	    FN_ADICS_B_SAMP_B, 0, 0, 0,
-	    /* IP11_2_0 [3] */
-	    FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
-	    FN_ADICLK_B, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32,
-			     GROUP(4, 4, 4, 2, 3, 3, 3, 3, 3, 3),
-			     GROUP(
-	    /* IP12_31_28 [4] */
-	    0, 0, 0, 0, 0, 0, 0, 0,
-	    0, 0, 0, 0, 0, 0, 0, 0,
-	    /* IP12_27_24 [4] */
-	    0, 0, 0, 0, 0, 0, 0, 0,
-	    0, 0, 0, 0, 0, 0, 0, 0,
-	    /* IP12_23_20 [4] */
-	    0, 0, 0, 0, 0, 0, 0, 0,
-	    0, 0, 0, 0, 0, 0, 0, 0,
-	    /* IP12_19_18 [2] */
-	    0, 0, 0, 0,
-	    /* IP12_17_15 [3] */
-	    FN_VI1_G7, FN_VI3_DATA7, FN_GPS_MAG, FN_FCE,
-	    FN_SCK4_B, 0, 0, 0,
-	    /* IP12_14_12 [3] */
-	    FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
-	    FN_RX4_B, FN_SIM_CLK_B, 0, 0,
-	    /* IP12_11_9 [3] */
-	    FN_VI1_G5, FN_VI3_DATA5, FN_GPS_CLK, FN_FSE,
-	    FN_TX4_B, FN_SIM_D_B, 0, 0,
-	    /* IP12_8_6 [3] */
-	    FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
-	    FN_SIM_RST_B, FN_HRX0_B, 0, 0,
-	    /* IP12_5_3 [3] */
-	    FN_VI1_G3, FN_VI3_DATA3, FN_SSI_SCK2, FN_TS_SDAT1,
-	    FN_SCL1_C, FN_HTX0_B, 0, 0,
-	    /* IP12_2_0 [3] */
-	    FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
-	    FN_SCK2, FN_HSCK0_B, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xfffc0090, 32,
-			     GROUP(2, 2, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1,
-				   1, 1, 1, 1, 2, 1, 2),
-			     GROUP(
-	    /* SEL_SCIF5 [2] */
-	    FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
-	    /* SEL_SCIF4 [2] */
-	    FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
-	    /* SEL_SCIF3 [3] */
-	    FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
-	    FN_SEL_SCIF3_4, 0, 0, 0,
-	    /* SEL_SCIF2 [3] */
-	    FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
-	    FN_SEL_SCIF2_4, 0, 0, 0,
-	    /* SEL_SCIF1 [2] */
-	    FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
-	    /* SEL_SCIF0 [2] */
-	    FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
-	    /* SEL_SSI9 [2] */
-	    FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2, 0,
-	    /* SEL_SSI8 [2] */
-	    FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0,
-	    /* SEL_SSI7 [2] */
-	    FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
-	    /* SEL_VI0 [1] */
-	    FN_SEL_VI0_0, FN_SEL_VI0_1,
-	    /* SEL_SD2 [1] */
-	    FN_SEL_SD2_0, FN_SEL_SD2_1,
-	    /* SEL_INT3 [1] */
-	    FN_SEL_INT3_0, FN_SEL_INT3_1,
-	    /* SEL_INT2 [1] */
-	    FN_SEL_INT2_0, FN_SEL_INT2_1,
-	    /* SEL_INT1 [1] */
-	    FN_SEL_INT1_0, FN_SEL_INT1_1,
-	    /* SEL_INT0 [1] */
-	    FN_SEL_INT0_0, FN_SEL_INT0_1,
-	    /* SEL_IE [1] */
-	    FN_SEL_IE_0, FN_SEL_IE_1,
-	    /* SEL_EXBUS2 [2] */
-	    FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2, 0,
-	    /* SEL_EXBUS1 [1] */
-	    FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
-	    /* SEL_EXBUS0 [2] */
-	    FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xfffc0094, 32,
-			     GROUP(2, 2, 2, 2, 1, 1, 1, 3, 1, 2, 2, 2,
-				   2, 1, 1, 2, 1, 2, 2),
-			     GROUP(
-	    /* SEL_TMU1 [2] */
-	    FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, 0,
-	    /* SEL_TMU0 [2] */
-	    FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
-	    /* SEL_SCIF [2] */
-	    FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
-	    /* SEL_CANCLK [2] */
-	    FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 0,
-	    /* SEL_CAN0 [1] */
-	    FN_SEL_CAN0_0, FN_SEL_CAN0_1,
-	    /* SEL_HSCIF1 [1] */
-	    FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
-	    /* SEL_HSCIF0 [1] */
-	    FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
-	    /* SEL_PWMFSW [3] */
-	    FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
-	    FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4, 0, 0, 0,
-	    /* SEL_ADI [1] */
-	    FN_SEL_ADI_0, FN_SEL_ADI_1,
-	    /* [2] */
-	    0, 0, 0, 0,
-	    /* [2] */
-	    0, 0, 0, 0,
-	    /* [2] */
-	    0, 0, 0, 0,
-	    /* SEL_GPS [2] */
-	    FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
-	    /* SEL_SIM [1] */
-	    FN_SEL_SIM_0, FN_SEL_SIM_1,
-	    /* SEL_HSPI2 [1] */
-	    FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
-	    /* SEL_HSPI1 [2] */
-	    FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
-	    /* SEL_I2C3 [1] */
-	    FN_SEL_I2C3_0, FN_SEL_I2C3_1,
-	    /* SEL_I2C2 [2] */
-	    FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
-	    /* SEL_I2C1 [2] */
-	    FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 ))
-	},
-	{ },
-};
-
-const struct sh_pfc_soc_info r8a7779_pinmux_info = {
-	.name = "r8a7779_pfc",
-
-	.unlock_reg = 0xfffc0000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups,
-	.nr_groups = ARRAY_SIZE(pinmux_groups),
-	.functions = pinmux_functions,
-	.nr_functions = ARRAY_SIZE(pinmux_functions),
-
-	.cfg_regs = pinmux_config_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
deleted file mode 100644
index 3366ed561cce..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ /dev/null
@@ -1,5757 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * R8A7790 processor support
- *
- * Copyright (C) 2013  Renesas Electronics Corporation
- * Copyright (C) 2013  Magnus Damm
- * Copyright (C) 2012  Renesas Solutions Corp.
- * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
- */
-
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/sys_soc.h>
-
-#include "core.h"
-#include "sh_pfc.h"
-
-/*
- * All pins assigned to GPIO bank 3 can be used for SD interfaces in
- * which case they support both 3.3V and 1.8V signalling.
- */
-#define CPU_ALL_GP(fn, sfx)						\
-	PORT_GP_32(0, fn, sfx),						\
-	PORT_GP_30(1, fn, sfx),						\
-	PORT_GP_30(2, fn, sfx),						\
-	PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),		\
-	PORT_GP_32(4, fn, sfx),						\
-	PORT_GP_32(5, fn, sfx)
-
-#define CPU_ALL_NOGP(fn)		\
-	PIN_NOGP(IIC0_SDA, "AF15", fn),	\
-	PIN_NOGP(IIC0_SCL, "AG15", fn),	\
-	PIN_NOGP(IIC3_SDA, "AH15", fn),	\
-	PIN_NOGP(IIC3_SCL, "AJ15", fn)
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	GP_ALL(DATA),
-	PINMUX_DATA_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	GP_ALL(FN),
-
-	/* GPSR0 */
-	FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
-	FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
-	FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
-	FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
-	FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
-	FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
-	FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
-	FN_IP3_14_12, FN_IP3_17_15,
-
-	/* GPSR1 */
-	FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
-	FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
-	FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
-	FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
-	FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
-	FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
-	FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
-
-	/* GPSR2 */
-	FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
-	FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
-	FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
-	FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
-	FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
-	FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
-	FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
-
-	/* GPSR3 */
-	FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
-	FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
-	FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
-	FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
-	FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
-	FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
-	FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
-
-	/* GPSR4 */
-	FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
-	FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
-	FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
-	FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
-	FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
-	FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
-	FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
-	FN_IP14_15_12, FN_IP14_18_16,
-
-	/* GPSR5 */
-	FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
-	FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
-	FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
-	FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
-	FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
-	FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
-	FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
-
-	/* IPSR0 */
-	FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
-	FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
-	FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
-	FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
-	FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
-	FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
-	FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
-	FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
-	FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
-	FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
-	FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
-	FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1,
-	FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
-	FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
-
-	/* IPSR1 */
-	FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
-	FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
-	FN_SCIFA1_TXD_C, FN_AVB_TXD2,
-	FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
-	FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
-	FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
-	FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
-	FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
-	FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
-	FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
-	FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
-	FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
-	FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
-	FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
-	FN_A0, FN_PWM3, FN_A1, FN_PWM4,
-
-	/* IPSR2 */
-	FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
-	FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
-	FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
-	FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
-	FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
-	FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
-	FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
-	FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
-	FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
-	FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
-	FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
-
-	/* IPSR3 */
-	FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
-	FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
-	FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
-	FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
-	FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
-	FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
-	FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
-	FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
-	FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
-	FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
-	FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
-	FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
-	FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
-
-	/* IPSR4 */
-	FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
-	FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
-	FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
-	FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
-	FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
-	FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
-	FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
-	FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
-	FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
-	FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
-	FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
-	FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
-	FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
-	FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
-	FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
-
-	/* IPSR5 */
-	FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
-	FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
-	FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
-	FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
-	FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
-	FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
-	FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
-	FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
-	FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
-	FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
-	FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
-	FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
-	FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
-	FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
-	FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
-	FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
-	FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
-	FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
-	FN_SSI_WS78_B,
-
-	/* IPSR6 */
-	FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
-	FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
-	FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
-	FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
-	FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
-	FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
-	FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
-	FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
-	FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
-	FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
-	FN_I2C2_SCL_E, FN_ETH_RX_ER,
-	FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
-	FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
-	FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
-	FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
-	FN_HRX0_E, FN_STP_ISSYNC_0_B,
-	FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
-	FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
-	FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
-	FN_ETH_REF_CLK, FN_HCTS0_N_E,
-	FN_STP_IVCXO27_1_B, FN_HRX0_F,
-
-	/* IPSR7 */
-	FN_ETH_MDIO, FN_HRTS0_N_E,
-	FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
-	FN_HTX0_F, FN_BPFCLK_G,
-	FN_ETH_TX_EN, FN_SIM0_CLK_C,
-	FN_HRTS0_N_F, FN_ETH_MAGIC,
-	FN_SIM0_RST_C, FN_ETH_TXD0,
-	FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
-	FN_ETH_MDC, FN_STP_ISD_1_B,
-	FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
-	FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
-	FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
-	FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
-	FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
-	FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1,
-	FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
-	FN_ATACS00_N, FN_AVB_RXD1,
-	FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
-
-	/* IPSR8 */
-	FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
-	FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
-	FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
-	FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
-	FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
-	FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
-	FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
-	FN_VI1_CLK, FN_AVB_RX_DV,
-	FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
-	FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
-	FN_SCIFA1_RXD_D, FN_AVB_MDC,
-	FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
-	FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
-	FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
-	FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
-	FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
-	FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
-	FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
-
-	/* IPSR9 */
-	FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
-	FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
-	FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
-	FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
-	FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
-	FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
-	FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
-	FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
-	FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
-	FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
-	FN_AVB_TX_EN, FN_SD1_CMD,
-	FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
-	FN_SD1_DAT0, FN_AVB_TX_CLK,
-	FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
-	FN_SCIFB0_TXD_B, FN_SD1_DAT2,
-	FN_AVB_COL, FN_SCIFB0_CTS_N_B,
-	FN_SD1_DAT3, FN_AVB_RXD0,
-	FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
-	FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
-	FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
-	FN_VI3_CLK_B,
-
-	/* IPSR10 */
-	FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
-	FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
-	FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
-	FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
-	FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
-	FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
-	FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
-	FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
-	FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
-	FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
-	FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
-	FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
-	FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
-	FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
-	FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
-	FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
-	FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
-	FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
-	FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
-	FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
-	FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
-	FN_GLO_I0_B, FN_VI3_DATA6_B,
-
-	/* IPSR11 */
-	FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
-	FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
-	FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
-	FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
-	FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
-	FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
-	FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
-	FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
-	FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
-	FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
-	FN_FMIN_E, FN_FMIN_F,
-	FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
-	FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
-	FN_I2C2_SDA_B, FN_MLB_DAT,
-	FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
-	FN_SSI_SCK0129, FN_CAN_CLK_B,
-	FN_MOUT0,
-
-	/* IPSR12 */
-	FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
-	FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
-	FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
-	FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
-	FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
-	FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
-	FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
-	FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
-	FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
-	FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
-	FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
-	FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
-	FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
-	FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
-	FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
-	FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
-	FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
-	FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
-	FN_CAN_DEBUGOUT4,
-
-	/* IPSR13 */
-	FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
-	FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
-	FN_SCIFB1_CTS_N, FN_BPFCLK_D,
-	FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
-	FN_BPFCLK_F, FN_SSI_WS6,
-	FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
-	FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
-	FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
-	FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
-	FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
-	FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
-	FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
-	FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
-	FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
-	FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
-	FN_BPFCLK_E, FN_SSI_SDATA7_B,
-	FN_FMIN_G, FN_SSI_SDATA8,
-	FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
-	FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
-	FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
-	FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
-	FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
-
-	/* IPSR14 */
-	FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
-	FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
-	FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
-	FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
-	FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
-	FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
-	FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
-	FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
-	FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
-	FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
-	FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
-	FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
-	FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
-	FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
-	FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
-	FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
-	FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
-	FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
-	FN_HRTS0_N_C,
-
-	/* IPSR15 */
-	FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
-	FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
-	FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
-	FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
-	FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
-	FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
-	FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
-	FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
-	FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
-	FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
-	FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
-	FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
-	FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
-	FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
-	FN_DU2_DG6, FN_LCDOUT14,
-
-	/* IPSR16 */
-	FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
-	FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
-	FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
-	FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
-	FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
-	FN_TCLK1_B,
-
-	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
-	FN_SEL_SCIF1_4,
-	FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
-	FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
-	FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
-	FN_SEL_SCIFB1_4,
-	FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
-	FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
-	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
-	FN_SEL_SCFA_0, FN_SEL_SCFA_1,
-	FN_SEL_SOF1_0, FN_SEL_SOF1_1,
-	FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
-	FN_SEL_SSI6_0, FN_SEL_SSI6_1,
-	FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
-	FN_SEL_VI3_0, FN_SEL_VI3_1,
-	FN_SEL_VI2_0, FN_SEL_VI2_1,
-	FN_SEL_VI1_0, FN_SEL_VI1_1,
-	FN_SEL_VI0_0, FN_SEL_VI0_1,
-	FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
-	FN_SEL_LBS_0, FN_SEL_LBS_1,
-	FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
-	FN_SEL_SOF3_0, FN_SEL_SOF3_1,
-	FN_SEL_SOF0_0, FN_SEL_SOF0_1,
-
-	FN_SEL_TMU1_0, FN_SEL_TMU1_1,
-	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
-	FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
-	FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
-	FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
-	FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
-	FN_SEL_CAN1_0, FN_SEL_CAN1_1,
-	FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
-	FN_SEL_ADI_0, FN_SEL_ADI_1,
-	FN_SEL_SSP_0, FN_SEL_SSP_1,
-	FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
-	FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
-	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
-	FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
-	FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
-	FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
-	FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
-
-	FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
-	FN_SEL_IIC0_0, FN_SEL_IIC0_1,
-	FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
-	FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
-	FN_SEL_IIC2_4,
-	FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
-	FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
-	FN_SEL_I2C2_4,
-	FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-
-	VI1_DATA7_VI1_B7_MARK,
-
-	USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
-	USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
-	DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
-
-	D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
-	D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
-	VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
-	VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
-	VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
-	SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
-	VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
-	SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
-	VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
-	IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
-	I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
-	VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK,
-	D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
-	VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
-
-	D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
-	VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
-	SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
-	VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
-	SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
-	VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
-	D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
-	VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
-	D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
-	VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
-	SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
-	VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
-	D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
-	VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
-	A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
-
-	A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
-	PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
-	TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
-	A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
-	SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
-	A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
-	VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK,
-	A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
-	VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK,
-	A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
-	VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
-
-	A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
-	VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
-	A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
-	VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
-	A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
-	MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
-	VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
-	ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
-	ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
-	A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
-	AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
-	ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
-	VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
-
-	A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
-	A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
-	VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
-	VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
-	VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
-	VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
-	VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
-	VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
-	CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
-	VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
-	VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
-	MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
-	HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
-	VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
-	VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
-
-	EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
-	VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
-	EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
-	VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
-	INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
-	MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
-	VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
-	I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
-	CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
-	CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
-	VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
-	INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
-	VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
-	WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
-	VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
-	IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
-	VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
-	MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
-	VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
-	SSI_WS78_B_MARK,
-
-	DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
-	VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
-	DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
-	SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
-	INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
-	DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
-	MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
-	SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
-	ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
-	TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
-	I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
-	STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
-	IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
-	STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
-	SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
-	HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
-	TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
-	RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
-	STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
-	ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
-	STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
-
-	ETH_MDIO_MARK, HRTS0_N_E_MARK,
-	SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
-	HTX0_F_MARK, BPFCLK_G_MARK,
-	ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
-	HRTS0_N_F_MARK, ETH_MAGIC_MARK,
-	SIM0_RST_C_MARK, ETH_TXD0_MARK,
-	STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
-	ETH_MDC_MARK, STP_ISD_1_B_MARK,
-	TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
-	SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
-	GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
-	STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
-	PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
-	PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK,
-	AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
-	ATACS00_N_MARK, AVB_RXD1_MARK,
-	VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
-
-	VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
-	VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
-	AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
-	AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
-	AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
-	AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
-	VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
-	VI1_CLK_MARK, AVB_RX_DV_MARK,
-	VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
-	AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
-	SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
-	VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
-	VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
-	AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
-	AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
-	AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
-	SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
-	SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
-
-	SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
-	SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
-	SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
-	SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
-	SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
-	GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
-	I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
-	MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
-	GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
-	I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
-	AVB_TX_EN_MARK, SD1_CMD_MARK,
-	AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
-	SD1_DAT0_MARK, AVB_TX_CLK_MARK,
-	SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
-	SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
-	AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
-	SD1_DAT3_MARK, AVB_RXD0_MARK,
-	SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
-	TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
-	IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
-	VI3_CLK_B_MARK,
-
-	SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
-	GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
-	SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
-	VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
-	VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
-	VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
-	TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
-	SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
-	VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
-	TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
-	SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
-	VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
-	TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
-	SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
-	VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
-	GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
-	MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
-	HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
-	VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
-	TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
-	VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
-	GLO_I0_B_MARK, VI3_DATA6_B_MARK,
-
-	SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
-	GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
-	TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
-	SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
-	MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
-	SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
-	MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
-	SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
-	VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
-	MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
-	FMIN_E_MARK, FMIN_F_MARK,
-	MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
-	MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
-	I2C2_SDA_B_MARK, MLB_DAT_MARK,
-	SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
-	SSI_SCK0129_MARK, CAN_CLK_B_MARK,
-	MOUT0_MARK,
-
-	SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
-	SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
-	SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
-	SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
-	SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
-	MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
-	STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
-	CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
-	SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
-	SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
-	MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
-	SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
-	MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
-	SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
-	CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
-	IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
-	CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
-	IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
-	CAN_DEBUGOUT4_MARK,
-
-	SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
-	LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
-	SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
-	DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
-	BPFCLK_F_MARK, SSI_WS6_MARK,
-	SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
-	LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
-	FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
-	CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
-	SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
-	CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
-	SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
-	LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
-	STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
-	TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
-	BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
-	FMIN_G_MARK, SSI_SDATA8_MARK,
-	STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
-	CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
-	STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
-	SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
-	SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
-
-	AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
-	DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
-	REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
-	MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
-	I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
-	DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
-	TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
-	HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
-	LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
-	SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
-	MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
-	SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
-	DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
-	SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
-	LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
-	CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
-	SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
-	MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
-	HRTS0_N_C_MARK,
-
-	SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
-	LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
-	TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
-	SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
-	IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
-	DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
-	DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
-	LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
-	LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
-	LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
-	DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
-	SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
-	HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
-	DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
-	DU2_DG6_MARK, LCDOUT14_MARK,
-
-	MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
-	DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
-	MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
-	ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
-	USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
-	TCLK1_B_MARK,
-
-	IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK,
-	IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK,
-	PINMUX_MARK_END,
-};
-
-static const u16 pinmux_data[] = {
-	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
-
-	PINMUX_SINGLE(VI1_DATA7_VI1_B7),
-	PINMUX_SINGLE(USB0_PWEN),
-	PINMUX_SINGLE(USB0_OVC_VBUS),
-	PINMUX_SINGLE(USB2_PWEN),
-	PINMUX_SINGLE(USB2_OVC),
-	PINMUX_SINGLE(AVS1),
-	PINMUX_SINGLE(AVS2),
-	PINMUX_SINGLE(DU_DOTCLKIN0),
-	PINMUX_SINGLE(DU_DOTCLKIN2),
-
-	PINMUX_IPSR_GPSR(IP0_2_0, D0),
-	PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
-	PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0),
-	PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1),
-	PINMUX_IPSR_GPSR(IP0_5_3, D1),
-	PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
-	PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0),
-	PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1),
-	PINMUX_IPSR_GPSR(IP0_8_6, D2),
-	PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
-	PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0),
-	PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6_B, SEL_VI0_1),
-	PINMUX_IPSR_GPSR(IP0_11_9, D3),
-	PINMUX_IPSR_MSEL(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
-	PINMUX_IPSR_MSEL(IP0_11_9, VI3_DATA3, SEL_VI3_0),
-	PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7_B, SEL_VI0_1),
-	PINMUX_IPSR_GPSR(IP0_15_12, D4),
-	PINMUX_IPSR_MSEL(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
-	PINMUX_IPSR_MSEL(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
-	PINMUX_IPSR_MSEL(IP0_15_12, VI3_DATA4, SEL_VI3_0),
-	PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP0_15_12, RX0_B, SEL_SCIF0_1),
-	PINMUX_IPSR_GPSR(IP0_19_16, D5),
-	PINMUX_IPSR_MSEL(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
-	PINMUX_IPSR_MSEL(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
-	PINMUX_IPSR_MSEL(IP0_19_16, VI3_DATA5, SEL_VI3_0),
-	PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP0_19_16, TX0_B, SEL_SCIF0_1),
-	PINMUX_IPSR_GPSR(IP0_22_20, D6),
-	PINMUX_IPSR_MSEL(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
-	PINMUX_IPSR_MSEL(IP0_22_20, VI3_DATA6, SEL_VI3_0),
-	PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
-	PINMUX_IPSR_GPSR(IP0_26_23, D7),
-	PINMUX_IPSR_MSEL(IP0_26_23, AD_DI_B, SEL_ADI_1),
-	PINMUX_IPSR_MSEL(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
-	PINMUX_IPSR_MSEL(IP0_26_23, VI3_DATA7, SEL_VI3_0),
-	PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
-	PINMUX_IPSR_MSEL(IP0_26_23, TCLK1, SEL_TMU1_0),
-	PINMUX_IPSR_GPSR(IP0_30_27, D8),
-	PINMUX_IPSR_MSEL(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
-	PINMUX_IPSR_GPSR(IP0_30_27, AVB_TXD0),
-	PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
-
-	PINMUX_IPSR_GPSR(IP1_3_0, D9),
-	PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
-	PINMUX_IPSR_GPSR(IP1_3_0, AVB_TXD1),
-	PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
-	PINMUX_IPSR_GPSR(IP1_7_4, D10),
-	PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
-	PINMUX_IPSR_GPSR(IP1_7_4, AVB_TXD2),
-	PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
-	PINMUX_IPSR_GPSR(IP1_11_8, D11),
-	PINMUX_IPSR_MSEL(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
-	PINMUX_IPSR_GPSR(IP1_11_8, AVB_TXD3),
-	PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
-	PINMUX_IPSR_GPSR(IP1_14_12, D12),
-	PINMUX_IPSR_MSEL(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
-	PINMUX_IPSR_GPSR(IP1_14_12, AVB_TXD4),
-	PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
-	PINMUX_IPSR_GPSR(IP1_17_15, D13),
-	PINMUX_IPSR_GPSR(IP1_17_15, AVB_TXD5),
-	PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
-	PINMUX_IPSR_GPSR(IP1_21_18, D14),
-	PINMUX_IPSR_MSEL(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
-	PINMUX_IPSR_GPSR(IP1_21_18, AVB_TXD6),
-	PINMUX_IPSR_MSEL(IP1_21_18, RX1_B, SEL_SCIF1_1),
-	PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
-	PINMUX_IPSR_GPSR(IP1_25_22, D15),
-	PINMUX_IPSR_MSEL(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
-	PINMUX_IPSR_GPSR(IP1_25_22, AVB_TXD7),
-	PINMUX_IPSR_MSEL(IP1_25_22, TX1_B, SEL_SCIF1_1),
-	PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
-	PINMUX_IPSR_GPSR(IP1_27_26, A0),
-	PINMUX_IPSR_GPSR(IP1_27_26, PWM3),
-	PINMUX_IPSR_GPSR(IP1_29_28, A1),
-	PINMUX_IPSR_GPSR(IP1_29_28, PWM4),
-
-	PINMUX_IPSR_GPSR(IP2_2_0, A2),
-	PINMUX_IPSR_GPSR(IP2_2_0, PWM5),
-	PINMUX_IPSR_MSEL(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
-	PINMUX_IPSR_GPSR(IP2_5_3, A3),
-	PINMUX_IPSR_GPSR(IP2_5_3, PWM6),
-	PINMUX_IPSR_MSEL(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
-	PINMUX_IPSR_GPSR(IP2_8_6, A4),
-	PINMUX_IPSR_MSEL(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
-	PINMUX_IPSR_GPSR(IP2_8_6, TPU0TO0),
-	PINMUX_IPSR_GPSR(IP2_11_9, A5),
-	PINMUX_IPSR_MSEL(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
-	PINMUX_IPSR_GPSR(IP2_11_9, TPU0TO1),
-	PINMUX_IPSR_GPSR(IP2_14_12, A6),
-	PINMUX_IPSR_MSEL(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
-	PINMUX_IPSR_GPSR(IP2_14_12, TPU0TO2),
-	PINMUX_IPSR_GPSR(IP2_17_15, A7),
-	PINMUX_IPSR_MSEL(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
-	PINMUX_IPSR_GPSR(IP2_17_15, AUDIO_CLKOUT_B),
-	PINMUX_IPSR_GPSR(IP2_17_15, TPU0TO3),
-	PINMUX_IPSR_GPSR(IP2_21_18, A8),
-	PINMUX_IPSR_MSEL(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
-	PINMUX_IPSR_MSEL(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
-	PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
-	PINMUX_IPSR_MSEL(IP2_21_18, RX2_B, SEL_SCIF2_1),
-	PINMUX_IPSR_MSEL(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
-	PINMUX_IPSR_GPSR(IP2_25_22, A9),
-	PINMUX_IPSR_MSEL(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
-	PINMUX_IPSR_MSEL(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
-	PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
-	PINMUX_IPSR_MSEL(IP2_25_22, TX2_B, SEL_SCIF2_1),
-	PINMUX_IPSR_MSEL(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
-	PINMUX_IPSR_GPSR(IP2_28_26, A10),
-	PINMUX_IPSR_MSEL(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
-	PINMUX_IPSR_GPSR(IP2_28_26, MSIOF2_SYNC),
-	PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
-
-	PINMUX_IPSR_GPSR(IP3_3_0, A11),
-	PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
-	PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SCK),
-	PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP3_3_0, VI2_G0),
-	PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
-	PINMUX_IPSR_GPSR(IP3_7_4, A12),
-	PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
-	PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
-	PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP3_7_4, VI2_G1),
-	PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
-	PINMUX_IPSR_GPSR(IP3_11_8, A13),
-	PINMUX_IPSR_MSEL(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
-	PINMUX_IPSR_GPSR(IP3_11_8, EX_WAIT2),
-	PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_RXD),
-	PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP3_11_8, VI2_G2),
-	PINMUX_IPSR_MSEL(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
-	PINMUX_IPSR_GPSR(IP3_14_12, A14),
-	PINMUX_IPSR_MSEL(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
-	PINMUX_IPSR_GPSR(IP3_14_12, ATACS11_N),
-	PINMUX_IPSR_GPSR(IP3_14_12, MSIOF2_SS1),
-	PINMUX_IPSR_GPSR(IP3_17_15, A15),
-	PINMUX_IPSR_MSEL(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
-	PINMUX_IPSR_GPSR(IP3_17_15, ATARD1_N),
-	PINMUX_IPSR_GPSR(IP3_17_15, MSIOF2_SS2),
-	PINMUX_IPSR_GPSR(IP3_19_18, A16),
-	PINMUX_IPSR_GPSR(IP3_19_18, ATAWR1_N),
-	PINMUX_IPSR_GPSR(IP3_22_20, A17),
-	PINMUX_IPSR_MSEL(IP3_22_20, AD_DO_B, SEL_ADI_1),
-	PINMUX_IPSR_GPSR(IP3_22_20, ATADIR1_N),
-	PINMUX_IPSR_GPSR(IP3_25_23, A18),
-	PINMUX_IPSR_MSEL(IP3_25_23, AD_CLK_B, SEL_ADI_1),
-	PINMUX_IPSR_GPSR(IP3_25_23, ATAG1_N),
-	PINMUX_IPSR_GPSR(IP3_28_26, A19),
-	PINMUX_IPSR_MSEL(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
-	PINMUX_IPSR_GPSR(IP3_28_26, ATACS01_N),
-	PINMUX_IPSR_MSEL(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
-	PINMUX_IPSR_GPSR(IP3_31_29, A20),
-	PINMUX_IPSR_GPSR(IP3_31_29, SPCLK),
-	PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP3_31_29, VI2_G4),
-
-	PINMUX_IPSR_GPSR(IP4_2_0, A21),
-	PINMUX_IPSR_GPSR(IP4_2_0, MOSI_IO0),
-	PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP4_2_0, VI2_G5),
-	PINMUX_IPSR_GPSR(IP4_5_3, A22),
-	PINMUX_IPSR_GPSR(IP4_5_3, MISO_IO1),
-	PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP4_5_3, VI2_G6),
-	PINMUX_IPSR_GPSR(IP4_8_6, A23),
-	PINMUX_IPSR_GPSR(IP4_8_6, IO2),
-	PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP4_8_6, VI2_G7),
-	PINMUX_IPSR_GPSR(IP4_11_9, A24),
-	PINMUX_IPSR_GPSR(IP4_11_9, IO3),
-	PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7_B, SEL_VI1_1),
-	PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
-	PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
-	PINMUX_IPSR_GPSR(IP4_14_12, A25),
-	PINMUX_IPSR_GPSR(IP4_14_12, SSL),
-	PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6_B, SEL_VI1_1),
-	PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD, SEL_VI2_0),
-	PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
-	PINMUX_IPSR_GPSR(IP4_17_15, CS0_N),
-	PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP4_17_15, VI2_G3),
-	PINMUX_IPSR_MSEL(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
-	PINMUX_IPSR_GPSR(IP4_20_18, CS1_N_A26),
-	PINMUX_IPSR_GPSR(IP4_20_18, SPEEDIN),
-	PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7, SEL_VI0_0),
-	PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK, SEL_VI2_0),
-	PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
-	PINMUX_IPSR_GPSR(IP4_23_21, EX_CS0_N),
-	PINMUX_IPSR_MSEL(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP4_23_21, VI2_R0),
-	PINMUX_IPSR_MSEL(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
-	PINMUX_IPSR_MSEL(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
-	PINMUX_IPSR_GPSR(IP4_26_24, EX_CS1_N),
-	PINMUX_IPSR_GPSR(IP4_26_24, GPS_CLK),
-	PINMUX_IPSR_MSEL(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP4_26_24, VI2_R1),
-	PINMUX_IPSR_GPSR(IP4_29_27, EX_CS2_N),
-	PINMUX_IPSR_GPSR(IP4_29_27, GPS_SIGN),
-	PINMUX_IPSR_MSEL(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
-	PINMUX_IPSR_GPSR(IP4_29_27, VI3_CLKENB),
-	PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP4_29_27, VI2_R2),
-
-	PINMUX_IPSR_GPSR(IP5_2_0, EX_CS3_N),
-	PINMUX_IPSR_GPSR(IP5_2_0, GPS_MAG),
-	PINMUX_IPSR_GPSR(IP5_2_0, VI3_FIELD),
-	PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP5_2_0, VI2_R3),
-	PINMUX_IPSR_GPSR(IP5_5_3, EX_CS4_N),
-	PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
-	PINMUX_IPSR_GPSR(IP5_5_3, VI3_HSYNC_N),
-	PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
-	PINMUX_IPSR_MSEL(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
-	PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
-	PINMUX_IPSR_GPSR(IP5_5_3, INTC_EN0_N),
-	PINMUX_IPSR_MSEL(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
-	PINMUX_IPSR_GPSR(IP5_9_6, EX_CS5_N),
-	PINMUX_IPSR_MSEL(IP5_9_6, CAN0_RX, SEL_CAN0_0),
-	PINMUX_IPSR_MSEL(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
-	PINMUX_IPSR_GPSR(IP5_9_6, VI3_VSYNC_N),
-	PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP5_9_6, VI2_R4),
-	PINMUX_IPSR_MSEL(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
-	PINMUX_IPSR_GPSR(IP5_9_6, INTC_EN1_N),
-	PINMUX_IPSR_MSEL(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
-	PINMUX_IPSR_GPSR(IP5_12_10, BS_N),
-	PINMUX_IPSR_MSEL(IP5_12_10, IETX, SEL_IEB_0),
-	PINMUX_IPSR_MSEL(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP5_12_10, CAN1_TX, SEL_CAN1_0),
-	PINMUX_IPSR_GPSR(IP5_12_10, DRACK0),
-	PINMUX_IPSR_MSEL(IP5_12_10, IETX_C, SEL_IEB_2),
-	PINMUX_IPSR_GPSR(IP5_14_13, RD_N),
-	PINMUX_IPSR_MSEL(IP5_14_13, CAN0_TX, SEL_CAN0_0),
-	PINMUX_IPSR_MSEL(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
-	PINMUX_IPSR_GPSR(IP5_17_15, RD_WR_N),
-	PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5),
-	PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
-	PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N),
-	PINMUX_IPSR_GPSR(IP5_20_18, WE0_N),
-	PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0),
-	PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
-	PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
-	PINMUX_IPSR_MSEL(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
-	PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
-	PINMUX_IPSR_GPSR(IP5_23_21, WE1_N),
-	PINMUX_IPSR_MSEL(IP5_23_21, IERX, SEL_IEB_0),
-	PINMUX_IPSR_MSEL(IP5_23_21, CAN1_RX, SEL_CAN1_0),
-	PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP5_23_21, VI2_R6),
-	PINMUX_IPSR_MSEL(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
-	PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2),
-	PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0),
-	PINMUX_IPSR_GPSR(IP5_26_24, IRQ3),
-	PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N),
-	PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0),
-	PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
-	PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
-	PINMUX_IPSR_MSEL(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
-	PINMUX_IPSR_GPSR(IP5_29_27, DREQ0_N),
-	PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP5_29_27, VI2_R7),
-	PINMUX_IPSR_MSEL(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
-	PINMUX_IPSR_MSEL(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
-
-	PINMUX_IPSR_GPSR(IP6_2_0, DACK0),
-	PINMUX_IPSR_GPSR(IP6_2_0, IRQ0),
-	PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N),
-	PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
-	PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
-	PINMUX_IPSR_MSEL(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
-	PINMUX_IPSR_GPSR(IP6_5_3, DREQ1_N),
-	PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
-	PINMUX_IPSR_MSEL(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
-	PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
-	PINMUX_IPSR_GPSR(IP6_8_6, DACK1),
-	PINMUX_IPSR_GPSR(IP6_8_6, IRQ1),
-	PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N),
-	PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
-	PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
-	PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N),
-	PINMUX_IPSR_MSEL(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
-	PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
-	PINMUX_IPSR_GPSR(IP6_13_11, DACK2),
-	PINMUX_IPSR_GPSR(IP6_13_11, IRQ2),
-	PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N),
-	PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
-	PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
-	PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
-	PINMUX_IPSR_GPSR(IP6_16_14, ETH_CRS_DV),
-	PINMUX_IPSR_MSEL(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
-	PINMUX_IPSR_MSEL(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
-	PINMUX_IPSR_MSEL(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
-	PINMUX_IPSR_MSEL(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
-	PINMUX_IPSR_GPSR(IP6_19_17, ETH_RX_ER),
-	PINMUX_IPSR_MSEL(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
-	PINMUX_IPSR_MSEL(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
-	PINMUX_IPSR_MSEL(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
-	PINMUX_IPSR_MSEL(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
-	PINMUX_IPSR_GPSR(IP6_22_20, ETH_RXD0),
-	PINMUX_IPSR_MSEL(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
-	PINMUX_IPSR_MSEL(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP6_22_20, GLO_I0_C, SEL_GPS_2),
-	PINMUX_IPSR_MSEL(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
-	PINMUX_IPSR_MSEL(IP6_22_20, SCK1_E, SEL_SCIF1_4),
-	PINMUX_IPSR_GPSR(IP6_25_23, ETH_RXD1),
-	PINMUX_IPSR_MSEL(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
-	PINMUX_IPSR_MSEL(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
-	PINMUX_IPSR_MSEL(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP6_25_23, GLO_I1_C, SEL_GPS_2),
-	PINMUX_IPSR_MSEL(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
-	PINMUX_IPSR_MSEL(IP6_25_23, RX1_E, SEL_SCIF1_4),
-	PINMUX_IPSR_GPSR(IP6_28_26, ETH_LINK),
-	PINMUX_IPSR_MSEL(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
-	PINMUX_IPSR_MSEL(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
-	PINMUX_IPSR_MSEL(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
-	PINMUX_IPSR_MSEL(IP6_28_26, TX1_E, SEL_SCIF1_4),
-	PINMUX_IPSR_GPSR(IP6_31_29, ETH_REF_CLK),
-	PINMUX_IPSR_MSEL(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
-	PINMUX_IPSR_MSEL(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
-	PINMUX_IPSR_MSEL(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
-
-	PINMUX_IPSR_GPSR(IP7_2_0, ETH_MDIO),
-	PINMUX_IPSR_MSEL(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
-	PINMUX_IPSR_MSEL(IP7_2_0, SIM0_D_C, SEL_SIM_2),
-	PINMUX_IPSR_MSEL(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
-	PINMUX_IPSR_GPSR(IP7_5_3, ETH_TXD1),
-	PINMUX_IPSR_MSEL(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
-	PINMUX_IPSR_MSEL(IP7_5_3, BPFCLK_G, SEL_FM_6),
-	PINMUX_IPSR_GPSR(IP7_7_6, ETH_TX_EN),
-	PINMUX_IPSR_MSEL(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
-	PINMUX_IPSR_MSEL(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
-	PINMUX_IPSR_GPSR(IP7_9_8, ETH_MAGIC),
-	PINMUX_IPSR_MSEL(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
-	PINMUX_IPSR_GPSR(IP7_12_10, ETH_TXD0),
-	PINMUX_IPSR_MSEL(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
-	PINMUX_IPSR_MSEL(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
-	PINMUX_IPSR_MSEL(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
-	PINMUX_IPSR_GPSR(IP7_15_13, ETH_MDC),
-	PINMUX_IPSR_MSEL(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
-	PINMUX_IPSR_MSEL(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
-	PINMUX_IPSR_MSEL(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
-	PINMUX_IPSR_GPSR(IP7_18_16, PWM0),
-	PINMUX_IPSR_MSEL(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
-	PINMUX_IPSR_MSEL(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
-	PINMUX_IPSR_MSEL(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
-	PINMUX_IPSR_MSEL(IP7_18_16, GLO_SS_C, SEL_GPS_2),
-	PINMUX_IPSR_GPSR(IP7_21_19, PWM1),
-	PINMUX_IPSR_MSEL(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
-	PINMUX_IPSR_MSEL(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
-	PINMUX_IPSR_MSEL(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
-	PINMUX_IPSR_MSEL(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
-	PINMUX_IPSR_GPSR(IP7_21_19, PCMOE_N),
-	PINMUX_IPSR_GPSR(IP7_24_22, PWM2),
-	PINMUX_IPSR_GPSR(IP7_24_22, PWMFSW0),
-	PINMUX_IPSR_MSEL(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
-	PINMUX_IPSR_GPSR(IP7_24_22, PCMWE_N),
-	PINMUX_IPSR_MSEL(IP7_24_22, IECLK_C, SEL_IEB_2),
-	PINMUX_IPSR_GPSR(IP7_26_25, DU_DOTCLKIN1),
-	PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKC),
-	PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKOUT_C),
-	PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0),
-	PINMUX_IPSR_GPSR(IP7_28_27, ATACS00_N),
-	PINMUX_IPSR_GPSR(IP7_28_27, AVB_RXD1),
-	PINMUX_IPSR_MSEL(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
-	PINMUX_IPSR_GPSR(IP7_30_29, ATACS10_N),
-	PINMUX_IPSR_GPSR(IP7_30_29, AVB_RXD2),
-
-	PINMUX_IPSR_MSEL(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
-	PINMUX_IPSR_GPSR(IP8_1_0, ATARD0_N),
-	PINMUX_IPSR_GPSR(IP8_1_0, AVB_RXD3),
-	PINMUX_IPSR_MSEL(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
-	PINMUX_IPSR_GPSR(IP8_3_2, ATAWR0_N),
-	PINMUX_IPSR_GPSR(IP8_3_2, AVB_RXD4),
-	PINMUX_IPSR_MSEL(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
-	PINMUX_IPSR_GPSR(IP8_5_4, ATADIR0_N),
-	PINMUX_IPSR_GPSR(IP8_5_4, AVB_RXD5),
-	PINMUX_IPSR_MSEL(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
-	PINMUX_IPSR_GPSR(IP8_7_6, ATAG0_N),
-	PINMUX_IPSR_GPSR(IP8_7_6, AVB_RXD6),
-	PINMUX_IPSR_MSEL(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
-	PINMUX_IPSR_GPSR(IP8_9_8, EX_WAIT1),
-	PINMUX_IPSR_GPSR(IP8_9_8, AVB_RXD7),
-	PINMUX_IPSR_MSEL(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
-	PINMUX_IPSR_GPSR(IP8_11_10, AVB_RX_ER),
-	PINMUX_IPSR_MSEL(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
-	PINMUX_IPSR_GPSR(IP8_13_12, AVB_RX_CLK),
-	PINMUX_IPSR_MSEL(IP8_15_14, VI1_CLK, SEL_VI1_0),
-	PINMUX_IPSR_GPSR(IP8_15_14, AVB_RX_DV),
-	PINMUX_IPSR_MSEL(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
-	PINMUX_IPSR_GPSR(IP8_17_16, AVB_CRS),
-	PINMUX_IPSR_MSEL(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
-	PINMUX_IPSR_GPSR(IP8_19_18, AVB_MDC),
-	PINMUX_IPSR_MSEL(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
-	PINMUX_IPSR_GPSR(IP8_21_20, AVB_MDIO),
-	PINMUX_IPSR_MSEL(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
-	PINMUX_IPSR_GPSR(IP8_23_22, AVB_GTX_CLK),
-	PINMUX_IPSR_MSEL(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
-	PINMUX_IPSR_MSEL(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
-	PINMUX_IPSR_GPSR(IP8_25_24, AVB_MAGIC),
-	PINMUX_IPSR_MSEL(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
-	PINMUX_IPSR_GPSR(IP8_26, AVB_PHY_INT),
-	PINMUX_IPSR_MSEL(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
-	PINMUX_IPSR_GPSR(IP8_27, AVB_GTXREFCLK),
-	PINMUX_IPSR_GPSR(IP8_28, SD0_CLK),
-	PINMUX_IPSR_MSEL(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP8_30_29, SD0_CMD),
-	PINMUX_IPSR_MSEL(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
-	PINMUX_IPSR_MSEL(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
-
-	PINMUX_IPSR_GPSR(IP9_1_0, SD0_DAT0),
-	PINMUX_IPSR_MSEL(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
-	PINMUX_IPSR_MSEL(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP9_3_2, SD0_DAT1),
-	PINMUX_IPSR_MSEL(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
-	PINMUX_IPSR_MSEL(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP9_5_4, SD0_DAT2),
-	PINMUX_IPSR_MSEL(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
-	PINMUX_IPSR_MSEL(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP9_7_6, SD0_DAT3),
-	PINMUX_IPSR_MSEL(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
-	PINMUX_IPSR_MSEL(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP9_11_8, SD0_CD),
-	PINMUX_IPSR_GPSR(IP9_11_8, MMC0_D6),
-	PINMUX_IPSR_MSEL(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
-	PINMUX_IPSR_GPSR(IP9_11_8, USB0_EXTP),
-	PINMUX_IPSR_MSEL(IP9_11_8, GLO_SCLK, SEL_GPS_0),
-	PINMUX_IPSR_MSEL(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
-	PINMUX_IPSR_MSEL(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
-	PINMUX_IPSR_MSEL(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
-	PINMUX_IPSR_MSEL(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
-	PINMUX_IPSR_GPSR(IP9_15_12, SD0_WP),
-	PINMUX_IPSR_GPSR(IP9_15_12, MMC0_D7),
-	PINMUX_IPSR_MSEL(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
-	PINMUX_IPSR_GPSR(IP9_15_12, USB0_IDIN),
-	PINMUX_IPSR_MSEL(IP9_15_12, GLO_SDATA, SEL_GPS_0),
-	PINMUX_IPSR_MSEL(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
-	PINMUX_IPSR_MSEL(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
-	PINMUX_IPSR_MSEL(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
-	PINMUX_IPSR_MSEL(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
-	PINMUX_IPSR_GPSR(IP9_17_16, SD1_CLK),
-	PINMUX_IPSR_GPSR(IP9_17_16, AVB_TX_EN),
-	PINMUX_IPSR_GPSR(IP9_19_18, SD1_CMD),
-	PINMUX_IPSR_GPSR(IP9_19_18, AVB_TX_ER),
-	PINMUX_IPSR_MSEL(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
-	PINMUX_IPSR_GPSR(IP9_21_20, SD1_DAT0),
-	PINMUX_IPSR_GPSR(IP9_21_20, AVB_TX_CLK),
-	PINMUX_IPSR_MSEL(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
-	PINMUX_IPSR_GPSR(IP9_23_22, SD1_DAT1),
-	PINMUX_IPSR_GPSR(IP9_23_22, AVB_LINK),
-	PINMUX_IPSR_MSEL(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
-	PINMUX_IPSR_GPSR(IP9_25_24, SD1_DAT2),
-	PINMUX_IPSR_GPSR(IP9_25_24, AVB_COL),
-	PINMUX_IPSR_MSEL(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
-	PINMUX_IPSR_GPSR(IP9_27_26, SD1_DAT3),
-	PINMUX_IPSR_GPSR(IP9_27_26, AVB_RXD0),
-	PINMUX_IPSR_MSEL(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
-	PINMUX_IPSR_GPSR(IP9_31_28, SD1_CD),
-	PINMUX_IPSR_GPSR(IP9_31_28, MMC1_D6),
-	PINMUX_IPSR_MSEL(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
-	PINMUX_IPSR_GPSR(IP9_31_28, USB1_EXTP),
-	PINMUX_IPSR_MSEL(IP9_31_28, GLO_SS, SEL_GPS_0),
-	PINMUX_IPSR_MSEL(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
-	PINMUX_IPSR_MSEL(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
-	PINMUX_IPSR_MSEL(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
-	PINMUX_IPSR_MSEL(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
-
-	PINMUX_IPSR_GPSR(IP10_3_0, SD1_WP),
-	PINMUX_IPSR_GPSR(IP10_3_0, MMC1_D7),
-	PINMUX_IPSR_MSEL(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
-	PINMUX_IPSR_GPSR(IP10_3_0, USB1_IDIN),
-	PINMUX_IPSR_MSEL(IP10_3_0, GLO_RFON, SEL_GPS_0),
-	PINMUX_IPSR_MSEL(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
-	PINMUX_IPSR_MSEL(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
-	PINMUX_IPSR_MSEL(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
-	PINMUX_IPSR_MSEL(IP10_3_0, SIM0_D_B, SEL_SIM_1),
-	PINMUX_IPSR_GPSR(IP10_6_4, SD2_CLK),
-	PINMUX_IPSR_GPSR(IP10_6_4, MMC0_CLK),
-	PINMUX_IPSR_MSEL(IP10_6_4, SIM0_CLK, SEL_SIM_0),
-	PINMUX_IPSR_MSEL(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
-	PINMUX_IPSR_MSEL(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
-	PINMUX_IPSR_GPSR(IP10_10_7, SD2_CMD),
-	PINMUX_IPSR_GPSR(IP10_10_7, MMC0_CMD),
-	PINMUX_IPSR_MSEL(IP10_10_7, SIM0_D, SEL_SIM_0),
-	PINMUX_IPSR_MSEL(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
-	PINMUX_IPSR_MSEL(IP10_10_7, SCK1_D, SEL_SCIF1_3),
-	PINMUX_IPSR_MSEL(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
-	PINMUX_IPSR_MSEL(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
-	PINMUX_IPSR_GPSR(IP10_14_11, SD2_DAT0),
-	PINMUX_IPSR_GPSR(IP10_14_11, MMC0_D0),
-	PINMUX_IPSR_MSEL(IP10_14_11, FMCLK_B, SEL_FM_1),
-	PINMUX_IPSR_MSEL(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
-	PINMUX_IPSR_MSEL(IP10_14_11, RX1_D, SEL_SCIF1_3),
-	PINMUX_IPSR_MSEL(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP10_14_11, GLO_SS_B, SEL_GPS_1),
-	PINMUX_IPSR_MSEL(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
-	PINMUX_IPSR_GPSR(IP10_18_15, SD2_DAT1),
-	PINMUX_IPSR_GPSR(IP10_18_15, MMC0_D1),
-	PINMUX_IPSR_MSEL(IP10_18_15, FMIN_B, SEL_FM_1),
-	PINMUX_IPSR_MSEL(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
-	PINMUX_IPSR_MSEL(IP10_18_15, TX1_D, SEL_SCIF1_3),
-	PINMUX_IPSR_MSEL(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
-	PINMUX_IPSR_MSEL(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
-	PINMUX_IPSR_GPSR(IP10_22_19, SD2_DAT2),
-	PINMUX_IPSR_GPSR(IP10_22_19, MMC0_D2),
-	PINMUX_IPSR_MSEL(IP10_22_19, BPFCLK_B, SEL_FM_1),
-	PINMUX_IPSR_MSEL(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
-	PINMUX_IPSR_MSEL(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
-	PINMUX_IPSR_MSEL(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
-	PINMUX_IPSR_MSEL(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
-	PINMUX_IPSR_GPSR(IP10_25_23, SD2_DAT3),
-	PINMUX_IPSR_GPSR(IP10_25_23, MMC0_D3),
-	PINMUX_IPSR_MSEL(IP10_25_23, SIM0_RST, SEL_SIM_0),
-	PINMUX_IPSR_MSEL(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
-	PINMUX_IPSR_MSEL(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
-	PINMUX_IPSR_MSEL(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
-	PINMUX_IPSR_MSEL(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
-	PINMUX_IPSR_GPSR(IP10_29_26, SD2_CD),
-	PINMUX_IPSR_GPSR(IP10_29_26, MMC0_D4),
-	PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
-	PINMUX_IPSR_GPSR(IP10_29_26, USB2_EXTP),
-	PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0, SEL_GPS_0),
-	PINMUX_IPSR_MSEL(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
-	PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
-	PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0_B, SEL_GPS_1),
-	PINMUX_IPSR_MSEL(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
-
-	PINMUX_IPSR_GPSR(IP11_3_0, SD2_WP),
-	PINMUX_IPSR_GPSR(IP11_3_0, MMC0_D5),
-	PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
-	PINMUX_IPSR_GPSR(IP11_3_0, USB2_IDIN),
-	PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1, SEL_GPS_0),
-	PINMUX_IPSR_MSEL(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
-	PINMUX_IPSR_MSEL(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
-	PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
-	PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1_B, SEL_GPS_1),
-	PINMUX_IPSR_MSEL(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
-	PINMUX_IPSR_GPSR(IP11_4, SD3_CLK),
-	PINMUX_IPSR_GPSR(IP11_4, MMC1_CLK),
-	PINMUX_IPSR_GPSR(IP11_6_5, SD3_CMD),
-	PINMUX_IPSR_GPSR(IP11_6_5, MMC1_CMD),
-	PINMUX_IPSR_GPSR(IP11_6_5, MTS_N),
-	PINMUX_IPSR_GPSR(IP11_8_7, SD3_DAT0),
-	PINMUX_IPSR_GPSR(IP11_8_7, MMC1_D0),
-	PINMUX_IPSR_GPSR(IP11_8_7, STM_N),
-	PINMUX_IPSR_GPSR(IP11_10_9, SD3_DAT1),
-	PINMUX_IPSR_GPSR(IP11_10_9, MMC1_D1),
-	PINMUX_IPSR_GPSR(IP11_10_9, MDATA),
-	PINMUX_IPSR_GPSR(IP11_12_11, SD3_DAT2),
-	PINMUX_IPSR_GPSR(IP11_12_11, MMC1_D2),
-	PINMUX_IPSR_GPSR(IP11_12_11, SDATA),
-	PINMUX_IPSR_GPSR(IP11_14_13, SD3_DAT3),
-	PINMUX_IPSR_GPSR(IP11_14_13, MMC1_D3),
-	PINMUX_IPSR_GPSR(IP11_14_13, SCKZ),
-	PINMUX_IPSR_GPSR(IP11_17_15, SD3_CD),
-	PINMUX_IPSR_GPSR(IP11_17_15, MMC1_D4),
-	PINMUX_IPSR_MSEL(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
-	PINMUX_IPSR_GPSR(IP11_17_15, VSP),
-	PINMUX_IPSR_MSEL(IP11_17_15, GLO_Q0, SEL_GPS_0),
-	PINMUX_IPSR_MSEL(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
-	PINMUX_IPSR_GPSR(IP11_21_18, SD3_WP),
-	PINMUX_IPSR_GPSR(IP11_21_18, MMC1_D5),
-	PINMUX_IPSR_MSEL(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
-	PINMUX_IPSR_MSEL(IP11_21_18, GLO_Q1, SEL_GPS_0),
-	PINMUX_IPSR_MSEL(IP11_21_18, FMIN_C, SEL_FM_2),
-	PINMUX_IPSR_MSEL(IP11_21_18, FMIN_E, SEL_FM_4),
-	PINMUX_IPSR_MSEL(IP11_21_18, FMIN_F, SEL_FM_5),
-	PINMUX_IPSR_GPSR(IP11_23_22, MLB_CLK),
-	PINMUX_IPSR_MSEL(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
-	PINMUX_IPSR_MSEL(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
-	PINMUX_IPSR_GPSR(IP11_26_24, MLB_SIG),
-	PINMUX_IPSR_MSEL(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
-	PINMUX_IPSR_MSEL(IP11_26_24, RX1_C, SEL_SCIF1_2),
-	PINMUX_IPSR_MSEL(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
-	PINMUX_IPSR_MSEL(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
-	PINMUX_IPSR_GPSR(IP11_29_27, MLB_DAT),
-	PINMUX_IPSR_MSEL(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
-	PINMUX_IPSR_MSEL(IP11_29_27, TX1_C, SEL_SCIF1_2),
-	PINMUX_IPSR_MSEL(IP11_29_27, BPFCLK_C, SEL_FM_2),
-	PINMUX_IPSR_GPSR(IP11_31_30, SSI_SCK0129),
-	PINMUX_IPSR_MSEL(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
-	PINMUX_IPSR_GPSR(IP11_31_30, MOUT0),
-
-	PINMUX_IPSR_GPSR(IP12_1_0, SSI_WS0129),
-	PINMUX_IPSR_MSEL(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
-	PINMUX_IPSR_GPSR(IP12_1_0, MOUT1),
-	PINMUX_IPSR_GPSR(IP12_3_2, SSI_SDATA0),
-	PINMUX_IPSR_MSEL(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
-	PINMUX_IPSR_GPSR(IP12_3_2, MOUT2),
-	PINMUX_IPSR_GPSR(IP12_5_4, SSI_SDATA1),
-	PINMUX_IPSR_MSEL(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
-	PINMUX_IPSR_GPSR(IP12_5_4, MOUT5),
-	PINMUX_IPSR_GPSR(IP12_7_6, SSI_SDATA2),
-	PINMUX_IPSR_MSEL(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
-	PINMUX_IPSR_GPSR(IP12_7_6, SSI_SCK1),
-	PINMUX_IPSR_GPSR(IP12_7_6, MOUT6),
-	PINMUX_IPSR_GPSR(IP12_10_8, SSI_SCK34),
-	PINMUX_IPSR_GPSR(IP12_10_8, STP_OPWM_0),
-	PINMUX_IPSR_MSEL(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
-	PINMUX_IPSR_MSEL(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
-	PINMUX_IPSR_GPSR(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
-	PINMUX_IPSR_GPSR(IP12_13_11, SSI_WS34),
-	PINMUX_IPSR_MSEL(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
-	PINMUX_IPSR_MSEL(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
-	PINMUX_IPSR_GPSR(IP12_13_11, MSIOF1_SYNC),
-	PINMUX_IPSR_GPSR(IP12_13_11, CAN_STEP0),
-	PINMUX_IPSR_GPSR(IP12_16_14, SSI_SDATA3),
-	PINMUX_IPSR_MSEL(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
-	PINMUX_IPSR_MSEL(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
-	PINMUX_IPSR_MSEL(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
-	PINMUX_IPSR_GPSR(IP12_16_14, CAN_TXCLK),
-	PINMUX_IPSR_GPSR(IP12_19_17, SSI_SCK4),
-	PINMUX_IPSR_MSEL(IP12_19_17, STP_ISD_0, SEL_SSP_0),
-	PINMUX_IPSR_MSEL(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
-	PINMUX_IPSR_MSEL(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
-	PINMUX_IPSR_MSEL(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
-	PINMUX_IPSR_GPSR(IP12_19_17, CAN_DEBUGOUT0),
-	PINMUX_IPSR_GPSR(IP12_22_20, SSI_WS4),
-	PINMUX_IPSR_MSEL(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
-	PINMUX_IPSR_MSEL(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
-	PINMUX_IPSR_MSEL(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
-	PINMUX_IPSR_MSEL(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
-	PINMUX_IPSR_GPSR(IP12_22_20, CAN_DEBUGOUT1),
-	PINMUX_IPSR_GPSR(IP12_24_23, SSI_SDATA4),
-	PINMUX_IPSR_MSEL(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
-	PINMUX_IPSR_MSEL(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
-	PINMUX_IPSR_GPSR(IP12_24_23, CAN_DEBUGOUT2),
-	PINMUX_IPSR_MSEL(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
-	PINMUX_IPSR_MSEL(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
-	PINMUX_IPSR_MSEL(IP12_27_25, IERX_B, SEL_IEB_1),
-	PINMUX_IPSR_GPSR(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
-	PINMUX_IPSR_GPSR(IP12_27_25, QSTH_QHS),
-	PINMUX_IPSR_GPSR(IP12_27_25, CAN_DEBUGOUT3),
-	PINMUX_IPSR_MSEL(IP12_30_28, SSI_WS5, SEL_SSI5_0),
-	PINMUX_IPSR_MSEL(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
-	PINMUX_IPSR_MSEL(IP12_30_28, IECLK_B, SEL_IEB_1),
-	PINMUX_IPSR_GPSR(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
-	PINMUX_IPSR_GPSR(IP12_30_28, QSTB_QHE),
-	PINMUX_IPSR_GPSR(IP12_30_28, CAN_DEBUGOUT4),
-
-	PINMUX_IPSR_MSEL(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
-	PINMUX_IPSR_MSEL(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
-	PINMUX_IPSR_MSEL(IP13_2_0, IETX_B, SEL_IEB_1),
-	PINMUX_IPSR_GPSR(IP13_2_0, DU2_DR2),
-	PINMUX_IPSR_GPSR(IP13_2_0, LCDOUT2),
-	PINMUX_IPSR_GPSR(IP13_2_0, CAN_DEBUGOUT5),
-	PINMUX_IPSR_MSEL(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
-	PINMUX_IPSR_MSEL(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
-	PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_D, SEL_FM_3),
-	PINMUX_IPSR_GPSR(IP13_6_3, DU2_DR3),
-	PINMUX_IPSR_GPSR(IP13_6_3, LCDOUT3),
-	PINMUX_IPSR_GPSR(IP13_6_3, CAN_DEBUGOUT6),
-	PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_F, SEL_FM_5),
-	PINMUX_IPSR_MSEL(IP13_9_7, SSI_WS6, SEL_SSI6_0),
-	PINMUX_IPSR_MSEL(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
-	PINMUX_IPSR_MSEL(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
-	PINMUX_IPSR_GPSR(IP13_9_7, DU2_DR4),
-	PINMUX_IPSR_GPSR(IP13_9_7, LCDOUT4),
-	PINMUX_IPSR_GPSR(IP13_9_7, CAN_DEBUGOUT7),
-	PINMUX_IPSR_MSEL(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
-	PINMUX_IPSR_MSEL(IP13_12_10, FMIN_D, SEL_FM_3),
-	PINMUX_IPSR_GPSR(IP13_12_10, DU2_DR5),
-	PINMUX_IPSR_GPSR(IP13_12_10, LCDOUT5),
-	PINMUX_IPSR_GPSR(IP13_12_10, CAN_DEBUGOUT8),
-	PINMUX_IPSR_MSEL(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
-	PINMUX_IPSR_MSEL(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
-	PINMUX_IPSR_MSEL(IP13_15_13, SCK1, SEL_SCIF1_0),
-	PINMUX_IPSR_MSEL(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
-	PINMUX_IPSR_GPSR(IP13_15_13, DU2_DR6),
-	PINMUX_IPSR_GPSR(IP13_15_13, LCDOUT6),
-	PINMUX_IPSR_GPSR(IP13_15_13, CAN_DEBUGOUT9),
-	PINMUX_IPSR_MSEL(IP13_18_16, SSI_WS78, SEL_SSI7_0),
-	PINMUX_IPSR_MSEL(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
-	PINMUX_IPSR_MSEL(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
-	PINMUX_IPSR_GPSR(IP13_18_16, SCIFA2_CTS_N),
-	PINMUX_IPSR_GPSR(IP13_18_16, DU2_DR7),
-	PINMUX_IPSR_GPSR(IP13_18_16, LCDOUT7),
-	PINMUX_IPSR_GPSR(IP13_18_16, CAN_DEBUGOUT10),
-	PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
-	PINMUX_IPSR_MSEL(IP13_22_19, STP_ISD_1, SEL_SSP_0),
-	PINMUX_IPSR_MSEL(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
-	PINMUX_IPSR_GPSR(IP13_22_19, SCIFA2_RTS_N),
-	PINMUX_IPSR_GPSR(IP13_22_19, TCLK2),
-	PINMUX_IPSR_GPSR(IP13_22_19, QSTVA_QVS),
-	PINMUX_IPSR_GPSR(IP13_22_19, CAN_DEBUGOUT11),
-	PINMUX_IPSR_MSEL(IP13_22_19, BPFCLK_E, SEL_FM_4),
-	PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
-	PINMUX_IPSR_MSEL(IP13_22_19, FMIN_G, SEL_FM_6),
-	PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
-	PINMUX_IPSR_MSEL(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
-	PINMUX_IPSR_MSEL(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
-	PINMUX_IPSR_MSEL(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
-	PINMUX_IPSR_GPSR(IP13_25_23, CAN_DEBUGOUT12),
-	PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
-	PINMUX_IPSR_GPSR(IP13_28_26, SSI_SDATA9),
-	PINMUX_IPSR_MSEL(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
-	PINMUX_IPSR_MSEL(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
-	PINMUX_IPSR_GPSR(IP13_28_26, SSI_WS1),
-	PINMUX_IPSR_MSEL(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
-	PINMUX_IPSR_GPSR(IP13_28_26, CAN_DEBUGOUT13),
-	PINMUX_IPSR_GPSR(IP13_30_29, AUDIO_CLKA),
-	PINMUX_IPSR_MSEL(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
-	PINMUX_IPSR_GPSR(IP13_30_29, CAN_DEBUGOUT14),
-
-	PINMUX_IPSR_GPSR(IP14_2_0, AUDIO_CLKB),
-	PINMUX_IPSR_MSEL(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
-	PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
-	PINMUX_IPSR_GPSR(IP14_2_0, DVC_MUTE),
-	PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
-	PINMUX_IPSR_GPSR(IP14_2_0, CAN_DEBUGOUT15),
-	PINMUX_IPSR_GPSR(IP14_2_0, REMOCON),
-	PINMUX_IPSR_MSEL(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
-	PINMUX_IPSR_MSEL(IP14_5_3, HSCK1, SEL_HSCIF1_0),
-	PINMUX_IPSR_GPSR(IP14_5_3, SCK0),
-	PINMUX_IPSR_GPSR(IP14_5_3, MSIOF3_SS2),
-	PINMUX_IPSR_GPSR(IP14_5_3, DU2_DG2),
-	PINMUX_IPSR_GPSR(IP14_5_3, LCDOUT10),
-	PINMUX_IPSR_MSEL(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
-	PINMUX_IPSR_MSEL(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
-	PINMUX_IPSR_MSEL(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
-	PINMUX_IPSR_MSEL(IP14_8_6, HRX1, SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0),
-	PINMUX_IPSR_GPSR(IP14_8_6, DU2_DR0),
-	PINMUX_IPSR_GPSR(IP14_8_6, LCDOUT0),
-	PINMUX_IPSR_MSEL(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
-	PINMUX_IPSR_MSEL(IP14_11_9, HTX1, SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP14_11_9, TX0, SEL_SCIF0_0),
-	PINMUX_IPSR_GPSR(IP14_11_9, DU2_DR1),
-	PINMUX_IPSR_GPSR(IP14_11_9, LCDOUT1),
-	PINMUX_IPSR_MSEL(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
-	PINMUX_IPSR_MSEL(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
-	PINMUX_IPSR_GPSR(IP14_15_12, CTS0_N),
-	PINMUX_IPSR_MSEL(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
-	PINMUX_IPSR_GPSR(IP14_15_12, DU2_DG3),
-	PINMUX_IPSR_GPSR(IP14_15_12, LCDOUT11),
-	PINMUX_IPSR_GPSR(IP14_15_12, PWM0_B),
-	PINMUX_IPSR_MSEL(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
-	PINMUX_IPSR_MSEL(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
-	PINMUX_IPSR_MSEL(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
-	PINMUX_IPSR_MSEL(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
-	PINMUX_IPSR_GPSR(IP14_18_16, RTS0_N),
-	PINMUX_IPSR_GPSR(IP14_18_16, MSIOF3_SS1),
-	PINMUX_IPSR_GPSR(IP14_18_16, DU2_DG0),
-	PINMUX_IPSR_GPSR(IP14_18_16, LCDOUT8),
-	PINMUX_IPSR_GPSR(IP14_18_16, PWM1_B),
-	PINMUX_IPSR_MSEL(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
-	PINMUX_IPSR_MSEL(IP14_21_19, AD_DI, SEL_ADI_0),
-	PINMUX_IPSR_MSEL(IP14_21_19, RX1, SEL_SCIF1_0),
-	PINMUX_IPSR_GPSR(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
-	PINMUX_IPSR_GPSR(IP14_21_19, QCPV_QDE),
-	PINMUX_IPSR_MSEL(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
-	PINMUX_IPSR_MSEL(IP14_24_22, AD_DO, SEL_ADI_0),
-	PINMUX_IPSR_MSEL(IP14_24_22, TX1, SEL_SCIF1_0),
-	PINMUX_IPSR_GPSR(IP14_24_22, DU2_DG1),
-	PINMUX_IPSR_GPSR(IP14_24_22, LCDOUT9),
-	PINMUX_IPSR_MSEL(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
-	PINMUX_IPSR_MSEL(IP14_27_25, AD_CLK, SEL_ADI_0),
-	PINMUX_IPSR_GPSR(IP14_27_25, CTS1_N),
-	PINMUX_IPSR_MSEL(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
-	PINMUX_IPSR_GPSR(IP14_27_25, DU0_DOTCLKOUT),
-	PINMUX_IPSR_GPSR(IP14_27_25, QCLK),
-	PINMUX_IPSR_MSEL(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
-	PINMUX_IPSR_MSEL(IP14_30_28, AD_NCS_N, SEL_ADI_0),
-	PINMUX_IPSR_GPSR(IP14_30_28, RTS1_N),
-	PINMUX_IPSR_MSEL(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
-	PINMUX_IPSR_GPSR(IP14_30_28, DU1_DOTCLKOUT),
-	PINMUX_IPSR_GPSR(IP14_30_28, QSTVB_QVE),
-	PINMUX_IPSR_MSEL(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
-
-	PINMUX_IPSR_MSEL(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
-	PINMUX_IPSR_MSEL(IP15_2_0, FMCLK, SEL_FM_0),
-	PINMUX_IPSR_GPSR(IP15_2_0, SCK2),
-	PINMUX_IPSR_MSEL(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
-	PINMUX_IPSR_GPSR(IP15_2_0, DU2_DG7),
-	PINMUX_IPSR_GPSR(IP15_2_0, LCDOUT15),
-	PINMUX_IPSR_MSEL(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
-	PINMUX_IPSR_MSEL(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
-	PINMUX_IPSR_MSEL(IP15_5_3, FMIN, SEL_FM_0),
-	PINMUX_IPSR_MSEL(IP15_5_3, TX2, SEL_SCIF2_0),
-	PINMUX_IPSR_GPSR(IP15_5_3, DU2_DB0),
-	PINMUX_IPSR_GPSR(IP15_5_3, LCDOUT16),
-	PINMUX_IPSR_MSEL(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
-	PINMUX_IPSR_MSEL(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
-	PINMUX_IPSR_MSEL(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
-	PINMUX_IPSR_MSEL(IP15_8_6, BPFCLK, SEL_FM_0),
-	PINMUX_IPSR_MSEL(IP15_8_6, RX2, SEL_SCIF2_0),
-	PINMUX_IPSR_GPSR(IP15_8_6, DU2_DB1),
-	PINMUX_IPSR_GPSR(IP15_8_6, LCDOUT17),
-	PINMUX_IPSR_MSEL(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
-	PINMUX_IPSR_MSEL(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
-	PINMUX_IPSR_GPSR(IP15_11_9, HSCK0),
-	PINMUX_IPSR_MSEL(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
-	PINMUX_IPSR_GPSR(IP15_11_9, DU2_DG4),
-	PINMUX_IPSR_GPSR(IP15_11_9, LCDOUT12),
-	PINMUX_IPSR_MSEL(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
-	PINMUX_IPSR_MSEL(IP15_13_12, HRX0, SEL_HSCIF0_0),
-	PINMUX_IPSR_GPSR(IP15_13_12, DU2_DB2),
-	PINMUX_IPSR_GPSR(IP15_13_12, LCDOUT18),
-	PINMUX_IPSR_MSEL(IP15_15_14, HTX0, SEL_HSCIF0_0),
-	PINMUX_IPSR_GPSR(IP15_15_14, DU2_DB3),
-	PINMUX_IPSR_GPSR(IP15_15_14, LCDOUT19),
-	PINMUX_IPSR_MSEL(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
-	PINMUX_IPSR_GPSR(IP15_17_16, SSI_SCK9),
-	PINMUX_IPSR_GPSR(IP15_17_16, DU2_DB4),
-	PINMUX_IPSR_GPSR(IP15_17_16, LCDOUT20),
-	PINMUX_IPSR_MSEL(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
-	PINMUX_IPSR_GPSR(IP15_19_18, SSI_WS9),
-	PINMUX_IPSR_GPSR(IP15_19_18, DU2_DB5),
-	PINMUX_IPSR_GPSR(IP15_19_18, LCDOUT21),
-	PINMUX_IPSR_MSEL(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
-	PINMUX_IPSR_MSEL(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
-	PINMUX_IPSR_GPSR(IP15_22_20, ADICLK),
-	PINMUX_IPSR_GPSR(IP15_22_20, DU2_DB6),
-	PINMUX_IPSR_GPSR(IP15_22_20, LCDOUT22),
-	PINMUX_IPSR_GPSR(IP15_25_23, MSIOF0_SYNC),
-	PINMUX_IPSR_MSEL(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
-	PINMUX_IPSR_GPSR(IP15_25_23, SSI_SCK2),
-	PINMUX_IPSR_GPSR(IP15_25_23, ADIDATA),
-	PINMUX_IPSR_GPSR(IP15_25_23, DU2_DB7),
-	PINMUX_IPSR_GPSR(IP15_25_23, LCDOUT23),
-	PINMUX_IPSR_MSEL(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
-	PINMUX_IPSR_MSEL(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
-	PINMUX_IPSR_GPSR(IP15_27_26, ADICHS0),
-	PINMUX_IPSR_GPSR(IP15_27_26, DU2_DG5),
-	PINMUX_IPSR_GPSR(IP15_27_26, LCDOUT13),
-	PINMUX_IPSR_MSEL(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
-	PINMUX_IPSR_GPSR(IP15_29_28, ADICHS1),
-	PINMUX_IPSR_GPSR(IP15_29_28, DU2_DG6),
-	PINMUX_IPSR_GPSR(IP15_29_28, LCDOUT14),
-
-	PINMUX_IPSR_MSEL(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
-	PINMUX_IPSR_GPSR(IP16_2_0, AUDIO_CLKOUT),
-	PINMUX_IPSR_GPSR(IP16_2_0, ADICHS2),
-	PINMUX_IPSR_GPSR(IP16_2_0, DU2_DISP),
-	PINMUX_IPSR_GPSR(IP16_2_0, QPOLA),
-	PINMUX_IPSR_MSEL(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
-	PINMUX_IPSR_MSEL(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
-	PINMUX_IPSR_MSEL(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
-	PINMUX_IPSR_MSEL(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
-	PINMUX_IPSR_GPSR(IP16_5_3, SSI_WS2),
-	PINMUX_IPSR_GPSR(IP16_5_3, ADICS_SAMP),
-	PINMUX_IPSR_GPSR(IP16_5_3, DU2_CDE),
-	PINMUX_IPSR_GPSR(IP16_5_3, QPOLB),
-	PINMUX_IPSR_MSEL(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
-	PINMUX_IPSR_GPSR(IP16_6, USB1_PWEN),
-	PINMUX_IPSR_GPSR(IP16_6, AUDIO_CLKOUT_D),
-	PINMUX_IPSR_GPSR(IP16_7, USB1_OVC),
-	PINMUX_IPSR_MSEL(IP16_7, TCLK1_B, SEL_TMU1_1),
-
-	PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0),
-	PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0),
-	PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1),
-	PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1),
-
-	PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0),
-	PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0),
-	PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
-	PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
-};
-
-/*
- * Pins not associated with a GPIO port.
- */
-enum {
-	GP_ASSIGN_LAST(),
-	NOGP_ALL(),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	PINMUX_GPIO_GP_ALL(),
-	PINMUX_NOGP_ALL(),
-};
-
-/* - AUDIO CLOCK ------------------------------------------------------------ */
-static const unsigned int audio_clk_a_pins[] = {
-	/* CLK A */
-	RCAR_GP_PIN(4, 25),
-};
-static const unsigned int audio_clk_a_mux[] = {
-	AUDIO_CLKA_MARK,
-};
-static const unsigned int audio_clk_b_pins[] = {
-	/* CLK B */
-	RCAR_GP_PIN(4, 26),
-};
-static const unsigned int audio_clk_b_mux[] = {
-	AUDIO_CLKB_MARK,
-};
-static const unsigned int audio_clk_c_pins[] = {
-	/* CLK C */
-	RCAR_GP_PIN(5, 27),
-};
-static const unsigned int audio_clk_c_mux[] = {
-	AUDIO_CLKC_MARK,
-};
-static const unsigned int audio_clkout_pins[] = {
-	/* CLK OUT */
-	RCAR_GP_PIN(5, 16),
-};
-static const unsigned int audio_clkout_mux[] = {
-	AUDIO_CLKOUT_MARK,
-};
-static const unsigned int audio_clkout_b_pins[] = {
-	/* CLK OUT B */
-	RCAR_GP_PIN(0, 23),
-};
-static const unsigned int audio_clkout_b_mux[] = {
-	AUDIO_CLKOUT_B_MARK,
-};
-static const unsigned int audio_clkout_c_pins[] = {
-	/* CLK OUT C */
-	RCAR_GP_PIN(5, 27),
-};
-static const unsigned int audio_clkout_c_mux[] = {
-	AUDIO_CLKOUT_C_MARK,
-};
-static const unsigned int audio_clkout_d_pins[] = {
-	/* CLK OUT D */
-	RCAR_GP_PIN(5, 20),
-};
-static const unsigned int audio_clkout_d_mux[] = {
-	AUDIO_CLKOUT_D_MARK,
-};
-/* - AVB -------------------------------------------------------------------- */
-static const unsigned int avb_link_pins[] = {
-	RCAR_GP_PIN(3, 11),
-};
-static const unsigned int avb_link_mux[] = {
-	AVB_LINK_MARK,
-};
-static const unsigned int avb_magic_pins[] = {
-	RCAR_GP_PIN(2, 14),
-};
-static const unsigned int avb_magic_mux[] = {
-	AVB_MAGIC_MARK,
-};
-static const unsigned int avb_phy_int_pins[] = {
-	RCAR_GP_PIN(2, 15),
-};
-static const unsigned int avb_phy_int_mux[] = {
-	AVB_PHY_INT_MARK,
-};
-static const unsigned int avb_mdio_pins[] = {
-	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
-};
-static const unsigned int avb_mdio_mux[] = {
-	AVB_MDC_MARK, AVB_MDIO_MARK,
-};
-static const unsigned int avb_mii_pins[] = {
-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
-	RCAR_GP_PIN(0, 11),
-
-	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-	RCAR_GP_PIN(2, 2),
-
-	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
-	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 12),
-};
-static const unsigned int avb_mii_mux[] = {
-	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
-	AVB_TXD3_MARK,
-
-	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
-	AVB_RXD3_MARK,
-
-	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
-	AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
-	AVB_TX_CLK_MARK, AVB_COL_MARK,
-};
-static const unsigned int avb_gmii_pins[] = {
-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
-	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-
-	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
-	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
-
-	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
-	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16),
-	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
-	RCAR_GP_PIN(3, 12),
-};
-static const unsigned int avb_gmii_mux[] = {
-	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
-	AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
-	AVB_TXD6_MARK, AVB_TXD7_MARK,
-
-	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
-	AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
-	AVB_RXD6_MARK, AVB_RXD7_MARK,
-
-	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
-	AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
-	AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
-	AVB_COL_MARK,
-};
-/* - DU RGB ----------------------------------------------------------------- */
-static const unsigned int du_rgb666_pins[] = {
-	/* R[7:2], G[7:2], B[7:2] */
-	RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
-	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
-	RCAR_GP_PIN(5, 4),  RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
-	RCAR_GP_PIN(5, 7),  RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
-	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
-	RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),  RCAR_GP_PIN(5, 8),
-};
-static const unsigned int du_rgb666_mux[] = {
-	DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
-	DU2_DR3_MARK, DU2_DR2_MARK,
-	DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
-	DU2_DG3_MARK, DU2_DG2_MARK,
-	DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
-	DU2_DB3_MARK, DU2_DB2_MARK,
-};
-static const unsigned int du_rgb888_pins[] = {
-	/* R[7:0], G[7:0], B[7:0] */
-	RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
-	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
-	RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4),
-	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7),
-	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1),
-	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12),
-	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),
-	RCAR_GP_PIN(5, 8),  RCAR_GP_PIN(5, 6),  RCAR_GP_PIN(5, 5),
-};
-static const unsigned int du_rgb888_mux[] = {
-	DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
-	DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK,
-	DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
-	DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK,
-	DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
-	DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK,
-};
-static const unsigned int du_clk_out_0_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(5, 2),
-};
-static const unsigned int du_clk_out_0_mux[] = {
-	DU0_DOTCLKOUT_MARK
-};
-static const unsigned int du_clk_out_1_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(5, 3),
-};
-static const unsigned int du_clk_out_1_mux[] = {
-	DU1_DOTCLKOUT_MARK
-};
-static const unsigned int du_sync_0_pins[] = {
-	/* VSYNC, HSYNC, DISP */
-	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0),
-};
-static const unsigned int du_sync_0_mux[] = {
-	DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
-	DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
-};
-static const unsigned int du_sync_1_pins[] = {
-	/* VSYNC, HSYNC, DISP */
-	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16),
-};
-static const unsigned int du_sync_1_mux[] = {
-	DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
-	DU2_DISP_MARK
-};
-static const unsigned int du_cde_pins[] = {
-	/* CDE */
-	RCAR_GP_PIN(5, 17),
-};
-static const unsigned int du_cde_mux[] = {
-	DU2_CDE_MARK,
-};
-/* - DU0 -------------------------------------------------------------------- */
-static const unsigned int du0_clk_in_pins[] = {
-	/* CLKIN */
-	RCAR_GP_PIN(5, 26),
-};
-static const unsigned int du0_clk_in_mux[] = {
-	DU_DOTCLKIN0_MARK
-};
-/* - DU1 -------------------------------------------------------------------- */
-static const unsigned int du1_clk_in_pins[] = {
-	/* CLKIN */
-	RCAR_GP_PIN(5, 27),
-};
-static const unsigned int du1_clk_in_mux[] = {
-	DU_DOTCLKIN1_MARK,
-};
-/* - DU2 -------------------------------------------------------------------- */
-static const unsigned int du2_clk_in_pins[] = {
-	/* CLKIN */
-	RCAR_GP_PIN(5, 28),
-};
-static const unsigned int du2_clk_in_mux[] = {
-	DU_DOTCLKIN2_MARK,
-};
-/* - ETH -------------------------------------------------------------------- */
-static const unsigned int eth_link_pins[] = {
-	/* LINK */
-	RCAR_GP_PIN(2, 22),
-};
-static const unsigned int eth_link_mux[] = {
-	ETH_LINK_MARK,
-};
-static const unsigned int eth_magic_pins[] = {
-	/* MAGIC */
-	RCAR_GP_PIN(2, 27),
-};
-static const unsigned int eth_magic_mux[] = {
-	ETH_MAGIC_MARK,
-};
-static const unsigned int eth_mdio_pins[] = {
-	/* MDC, MDIO */
-	RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
-};
-static const unsigned int eth_mdio_mux[] = {
-	ETH_MDC_MARK, ETH_MDIO_MARK,
-};
-static const unsigned int eth_rmii_pins[] = {
-	/* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
-	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
-	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
-	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
-};
-static const unsigned int eth_rmii_mux[] = {
-	ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
-	ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
-};
-/* - HSCIF0 ----------------------------------------------------------------- */
-static const unsigned int hscif0_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
-};
-static const unsigned int hscif0_data_mux[] = {
-	HRX0_MARK, HTX0_MARK,
-};
-static const unsigned int hscif0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 7),
-};
-static const unsigned int hscif0_clk_mux[] = {
-	HSCK0_MARK,
-};
-static const unsigned int hscif0_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
-};
-static const unsigned int hscif0_ctrl_mux[] = {
-	HRTS0_N_MARK, HCTS0_N_MARK,
-};
-static const unsigned int hscif0_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
-};
-static const unsigned int hscif0_data_b_mux[] = {
-	HRX0_B_MARK, HTX0_B_MARK,
-};
-static const unsigned int hscif0_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
-};
-static const unsigned int hscif0_ctrl_b_mux[] = {
-	HRTS0_N_B_MARK, HCTS0_N_B_MARK,
-};
-static const unsigned int hscif0_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
-};
-static const unsigned int hscif0_data_c_mux[] = {
-	HRX0_C_MARK, HTX0_C_MARK,
-};
-static const unsigned int hscif0_ctrl_c_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
-};
-static const unsigned int hscif0_ctrl_c_mux[] = {
-	HRTS0_N_C_MARK, HCTS0_N_C_MARK,
-};
-static const unsigned int hscif0_data_d_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
-};
-static const unsigned int hscif0_data_d_mux[] = {
-	HRX0_D_MARK, HTX0_D_MARK,
-};
-static const unsigned int hscif0_ctrl_d_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
-};
-static const unsigned int hscif0_ctrl_d_mux[] = {
-	HRTS0_N_D_MARK, HCTS0_N_D_MARK,
-};
-static const unsigned int hscif0_data_e_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
-};
-static const unsigned int hscif0_data_e_mux[] = {
-	HRX0_E_MARK, HTX0_E_MARK,
-};
-static const unsigned int hscif0_ctrl_e_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
-};
-static const unsigned int hscif0_ctrl_e_mux[] = {
-	HRTS0_N_E_MARK, HCTS0_N_E_MARK,
-};
-static const unsigned int hscif0_data_f_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
-};
-static const unsigned int hscif0_data_f_mux[] = {
-	HRX0_F_MARK, HTX0_F_MARK,
-};
-static const unsigned int hscif0_ctrl_f_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
-};
-static const unsigned int hscif0_ctrl_f_mux[] = {
-	HRTS0_N_F_MARK, HCTS0_N_F_MARK,
-};
-/* - HSCIF1 ----------------------------------------------------------------- */
-static const unsigned int hscif1_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
-};
-static const unsigned int hscif1_data_mux[] = {
-	HRX1_MARK, HTX1_MARK,
-};
-static const unsigned int hscif1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 27),
-};
-static const unsigned int hscif1_clk_mux[] = {
-	HSCK1_MARK,
-};
-static const unsigned int hscif1_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
-};
-static const unsigned int hscif1_ctrl_mux[] = {
-	HRTS1_N_MARK, HCTS1_N_MARK,
-};
-static const unsigned int hscif1_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
-};
-static const unsigned int hscif1_data_b_mux[] = {
-	HRX1_B_MARK, HTX1_B_MARK,
-};
-static const unsigned int hscif1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 28),
-};
-static const unsigned int hscif1_clk_b_mux[] = {
-	HSCK1_B_MARK,
-};
-static const unsigned int hscif1_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
-};
-static const unsigned int hscif1_ctrl_b_mux[] = {
-	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
-};
-/* - I2C0 ------------------------------------------------------------------- */
-static const unsigned int i2c0_pins[] = {
-	/* SCL, SDA */
-	PIN_IIC0_SCL, PIN_IIC0_SDA,
-};
-static const unsigned int i2c0_mux[] = {
-	I2C0_SCL_MARK, I2C0_SDA_MARK,
-};
-/* - I2C1 ------------------------------------------------------------------- */
-static const unsigned int i2c1_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
-};
-static const unsigned int i2c1_mux[] = {
-	I2C1_SCL_MARK, I2C1_SDA_MARK,
-};
-static const unsigned int i2c1_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-};
-static const unsigned int i2c1_b_mux[] = {
-	I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
-};
-static const unsigned int i2c1_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
-};
-static const unsigned int i2c1_c_mux[] = {
-	I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
-};
-/* - I2C2 ------------------------------------------------------------------- */
-static const unsigned int i2c2_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
-};
-static const unsigned int i2c2_mux[] = {
-	I2C2_SCL_MARK, I2C2_SDA_MARK,
-};
-static const unsigned int i2c2_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
-};
-static const unsigned int i2c2_b_mux[] = {
-	I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
-};
-static const unsigned int i2c2_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-};
-static const unsigned int i2c2_c_mux[] = {
-	I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
-};
-static const unsigned int i2c2_d_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
-};
-static const unsigned int i2c2_d_mux[] = {
-	I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
-};
-static const unsigned int i2c2_e_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
-};
-static const unsigned int i2c2_e_mux[] = {
-	I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
-};
-/* - I2C3 ------------------------------------------------------------------- */
-static const unsigned int i2c3_pins[] = {
-	/* SCL, SDA */
-	PIN_IIC3_SCL, PIN_IIC3_SDA,
-};
-static const unsigned int i2c3_mux[] = {
-	I2C3_SCL_MARK, I2C3_SDA_MARK,
-};
-/* - IIC0 (I2C4) ------------------------------------------------------------ */
-static const unsigned int iic0_pins[] = {
-	/* SCL, SDA */
-	PIN_IIC0_SCL, PIN_IIC0_SDA,
-};
-static const unsigned int iic0_mux[] = {
-	IIC0_SCL_MARK, IIC0_SDA_MARK,
-};
-/* - IIC1 (I2C5) ------------------------------------------------------------ */
-static const unsigned int iic1_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
-};
-static const unsigned int iic1_mux[] = {
-	IIC1_SCL_MARK, IIC1_SDA_MARK,
-};
-static const unsigned int iic1_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-};
-static const unsigned int iic1_b_mux[] = {
-	IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
-};
-static const unsigned int iic1_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
-};
-static const unsigned int iic1_c_mux[] = {
-	IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
-};
-/* - IIC2 (I2C6) ------------------------------------------------------------ */
-static const unsigned int iic2_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
-};
-static const unsigned int iic2_mux[] = {
-	IIC2_SCL_MARK, IIC2_SDA_MARK,
-};
-static const unsigned int iic2_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
-};
-static const unsigned int iic2_b_mux[] = {
-	IIC2_SCL_B_MARK, IIC2_SDA_B_MARK,
-};
-static const unsigned int iic2_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-};
-static const unsigned int iic2_c_mux[] = {
-	IIC2_SCL_C_MARK, IIC2_SDA_C_MARK,
-};
-static const unsigned int iic2_d_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
-};
-static const unsigned int iic2_d_mux[] = {
-	IIC2_SCL_D_MARK, IIC2_SDA_D_MARK,
-};
-static const unsigned int iic2_e_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
-};
-static const unsigned int iic2_e_mux[] = {
-	IIC2_SCL_E_MARK, IIC2_SDA_E_MARK,
-};
-/* - IIC3 (I2C7) ------------------------------------------------------------ */
-static const unsigned int iic3_pins[] = {
-	/* SCL, SDA */
-	PIN_IIC3_SCL, PIN_IIC3_SDA,
-};
-static const unsigned int iic3_mux[] = {
-	IIC3_SCL_MARK, IIC3_SDA_MARK,
-};
-/* - INTC ------------------------------------------------------------------- */
-static const unsigned int intc_irq0_pins[] = {
-	/* IRQ */
-	RCAR_GP_PIN(1, 25),
-};
-static const unsigned int intc_irq0_mux[] = {
-	IRQ0_MARK,
-};
-static const unsigned int intc_irq1_pins[] = {
-	/* IRQ */
-	RCAR_GP_PIN(1, 27),
-};
-static const unsigned int intc_irq1_mux[] = {
-	IRQ1_MARK,
-};
-static const unsigned int intc_irq2_pins[] = {
-	/* IRQ */
-	RCAR_GP_PIN(1, 29),
-};
-static const unsigned int intc_irq2_mux[] = {
-	IRQ2_MARK,
-};
-static const unsigned int intc_irq3_pins[] = {
-	/* IRQ */
-	RCAR_GP_PIN(1, 23),
-};
-static const unsigned int intc_irq3_mux[] = {
-	IRQ3_MARK,
-};
-/* - MLB+ ------------------------------------------------------------------- */
-static const unsigned int mlb_3pin_pins[] = {
-	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
-};
-static const unsigned int mlb_3pin_mux[] = {
-	MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
-};
-/* - MMCIF0 ----------------------------------------------------------------- */
-static const unsigned int mmc0_data1_pins[] = {
-	/* D[0] */
-	RCAR_GP_PIN(3, 18),
-};
-static const unsigned int mmc0_data1_mux[] = {
-	MMC0_D0_MARK,
-};
-static const unsigned int mmc0_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
-	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
-};
-static const unsigned int mmc0_data4_mux[] = {
-	MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
-};
-static const unsigned int mmc0_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
-	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
-	RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
-	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-};
-static const unsigned int mmc0_data8_mux[] = {
-	MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
-	MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
-};
-static const unsigned int mmc0_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
-};
-static const unsigned int mmc0_ctrl_mux[] = {
-	MMC0_CLK_MARK, MMC0_CMD_MARK,
-};
-/* - MMCIF1 ----------------------------------------------------------------- */
-static const unsigned int mmc1_data1_pins[] = {
-	/* D[0] */
-	RCAR_GP_PIN(3, 26),
-};
-static const unsigned int mmc1_data1_mux[] = {
-	MMC1_D0_MARK,
-};
-static const unsigned int mmc1_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
-	RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
-};
-static const unsigned int mmc1_data4_mux[] = {
-	MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
-};
-static const unsigned int mmc1_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
-	RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
-	RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
-	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
-};
-static const unsigned int mmc1_data8_mux[] = {
-	MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
-	MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
-};
-static const unsigned int mmc1_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
-};
-static const unsigned int mmc1_ctrl_mux[] = {
-	MMC1_CLK_MARK, MMC1_CMD_MARK,
-};
-/* - MSIOF0 ----------------------------------------------------------------- */
-static const unsigned int msiof0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 12),
-};
-static const unsigned int msiof0_clk_mux[] = {
-	MSIOF0_SCK_MARK,
-};
-static const unsigned int msiof0_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(5, 13),
-};
-static const unsigned int msiof0_sync_mux[] = {
-	MSIOF0_SYNC_MARK,
-};
-static const unsigned int msiof0_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(5, 14),
-};
-static const unsigned int msiof0_ss1_mux[] = {
-	MSIOF0_SS1_MARK,
-};
-static const unsigned int msiof0_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(5, 16),
-};
-static const unsigned int msiof0_ss2_mux[] = {
-	MSIOF0_SS2_MARK,
-};
-static const unsigned int msiof0_rx_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 17),
-};
-static const unsigned int msiof0_rx_mux[] = {
-	MSIOF0_RXD_MARK,
-};
-static const unsigned int msiof0_tx_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(5, 15),
-};
-static const unsigned int msiof0_tx_mux[] = {
-	MSIOF0_TXD_MARK,
-};
-
-static const unsigned int msiof0_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 23),
-};
-static const unsigned int msiof0_clk_b_mux[] = {
-	MSIOF0_SCK_B_MARK,
-};
-static const unsigned int msiof0_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(1, 12),
-};
-static const unsigned int msiof0_ss1_b_mux[] = {
-	MSIOF0_SS1_B_MARK,
-};
-static const unsigned int msiof0_ss2_b_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(1, 10),
-};
-static const unsigned int msiof0_ss2_b_mux[] = {
-	MSIOF0_SS2_B_MARK,
-};
-static const unsigned int msiof0_rx_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 29),
-};
-static const unsigned int msiof0_rx_b_mux[] = {
-	MSIOF0_RXD_B_MARK,
-};
-static const unsigned int msiof0_tx_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 28),
-};
-static const unsigned int msiof0_tx_b_mux[] = {
-	MSIOF0_TXD_B_MARK,
-};
-/* - MSIOF1 ----------------------------------------------------------------- */
-static const unsigned int msiof1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 8),
-};
-static const unsigned int msiof1_clk_mux[] = {
-	MSIOF1_SCK_MARK,
-};
-static const unsigned int msiof1_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(4, 9),
-};
-static const unsigned int msiof1_sync_mux[] = {
-	MSIOF1_SYNC_MARK,
-};
-static const unsigned int msiof1_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(4, 10),
-};
-static const unsigned int msiof1_ss1_mux[] = {
-	MSIOF1_SS1_MARK,
-};
-static const unsigned int msiof1_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(4, 11),
-};
-static const unsigned int msiof1_ss2_mux[] = {
-	MSIOF1_SS2_MARK,
-};
-static const unsigned int msiof1_rx_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(4, 13),
-};
-static const unsigned int msiof1_rx_mux[] = {
-	MSIOF1_RXD_MARK,
-};
-static const unsigned int msiof1_tx_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(4, 12),
-};
-static const unsigned int msiof1_tx_mux[] = {
-	MSIOF1_TXD_MARK,
-};
-
-static const unsigned int msiof1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 16),
-};
-static const unsigned int msiof1_clk_b_mux[] = {
-	MSIOF1_SCK_B_MARK,
-};
-static const unsigned int msiof1_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 18),
-};
-static const unsigned int msiof1_ss1_b_mux[] = {
-	MSIOF1_SS1_B_MARK,
-};
-static const unsigned int msiof1_ss2_b_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 19),
-};
-static const unsigned int msiof1_ss2_b_mux[] = {
-	MSIOF1_SS2_B_MARK,
-};
-static const unsigned int msiof1_rx_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 17),
-};
-static const unsigned int msiof1_rx_b_mux[] = {
-	MSIOF1_RXD_B_MARK,
-};
-static const unsigned int msiof1_tx_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 20),
-};
-static const unsigned int msiof1_tx_b_mux[] = {
-	MSIOF1_TXD_B_MARK,
-};
-/* - MSIOF2 ----------------------------------------------------------------- */
-static const unsigned int msiof2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 27),
-};
-static const unsigned int msiof2_clk_mux[] = {
-	MSIOF2_SCK_MARK,
-};
-static const unsigned int msiof2_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 26),
-};
-static const unsigned int msiof2_sync_mux[] = {
-	MSIOF2_SYNC_MARK,
-};
-static const unsigned int msiof2_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 30),
-};
-static const unsigned int msiof2_ss1_mux[] = {
-	MSIOF2_SS1_MARK,
-};
-static const unsigned int msiof2_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 31),
-};
-static const unsigned int msiof2_ss2_mux[] = {
-	MSIOF2_SS2_MARK,
-};
-static const unsigned int msiof2_rx_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 29),
-};
-static const unsigned int msiof2_rx_mux[] = {
-	MSIOF2_RXD_MARK,
-};
-static const unsigned int msiof2_tx_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 28),
-};
-static const unsigned int msiof2_tx_mux[] = {
-	MSIOF2_TXD_MARK,
-};
-/* - MSIOF3 ----------------------------------------------------------------- */
-static const unsigned int msiof3_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 4),
-};
-static const unsigned int msiof3_clk_mux[] = {
-	MSIOF3_SCK_MARK,
-};
-static const unsigned int msiof3_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(4, 30),
-};
-static const unsigned int msiof3_sync_mux[] = {
-	MSIOF3_SYNC_MARK,
-};
-static const unsigned int msiof3_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(4, 31),
-};
-static const unsigned int msiof3_ss1_mux[] = {
-	MSIOF3_SS1_MARK,
-};
-static const unsigned int msiof3_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(4, 27),
-};
-static const unsigned int msiof3_ss2_mux[] = {
-	MSIOF3_SS2_MARK,
-};
-static const unsigned int msiof3_rx_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 2),
-};
-static const unsigned int msiof3_rx_mux[] = {
-	MSIOF3_RXD_MARK,
-};
-static const unsigned int msiof3_tx_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(5, 3),
-};
-static const unsigned int msiof3_tx_mux[] = {
-	MSIOF3_TXD_MARK,
-};
-
-static const unsigned int msiof3_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 0),
-};
-static const unsigned int msiof3_clk_b_mux[] = {
-	MSIOF3_SCK_B_MARK,
-};
-static const unsigned int msiof3_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 1),
-};
-static const unsigned int msiof3_sync_b_mux[] = {
-	MSIOF3_SYNC_B_MARK,
-};
-static const unsigned int msiof3_rx_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 2),
-};
-static const unsigned int msiof3_rx_b_mux[] = {
-	MSIOF3_RXD_B_MARK,
-};
-static const unsigned int msiof3_tx_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 3),
-};
-static const unsigned int msiof3_tx_b_mux[] = {
-	MSIOF3_TXD_B_MARK,
-};
-/* - PWM -------------------------------------------------------------------- */
-static const unsigned int pwm0_pins[] = {
-	RCAR_GP_PIN(5, 29),
-};
-static const unsigned int pwm0_mux[] = {
-	PWM0_MARK,
-};
-static const unsigned int pwm0_b_pins[] = {
-	RCAR_GP_PIN(4, 30),
-};
-static const unsigned int pwm0_b_mux[] = {
-	PWM0_B_MARK,
-};
-static const unsigned int pwm1_pins[] = {
-	RCAR_GP_PIN(5, 30),
-};
-static const unsigned int pwm1_mux[] = {
-	PWM1_MARK,
-};
-static const unsigned int pwm1_b_pins[] = {
-	RCAR_GP_PIN(4, 31),
-};
-static const unsigned int pwm1_b_mux[] = {
-	PWM1_B_MARK,
-};
-static const unsigned int pwm2_pins[] = {
-	RCAR_GP_PIN(5, 31),
-};
-static const unsigned int pwm2_mux[] = {
-	PWM2_MARK,
-};
-static const unsigned int pwm3_pins[] = {
-	RCAR_GP_PIN(0, 16),
-};
-static const unsigned int pwm3_mux[] = {
-	PWM3_MARK,
-};
-static const unsigned int pwm4_pins[] = {
-	RCAR_GP_PIN(0, 17),
-};
-static const unsigned int pwm4_mux[] = {
-	PWM4_MARK,
-};
-static const unsigned int pwm5_pins[] = {
-	RCAR_GP_PIN(0, 18),
-};
-static const unsigned int pwm5_mux[] = {
-	PWM5_MARK,
-};
-static const unsigned int pwm6_pins[] = {
-	RCAR_GP_PIN(0, 19),
-};
-static const unsigned int pwm6_mux[] = {
-	PWM6_MARK,
-};
-/* - QSPI ------------------------------------------------------------------- */
-static const unsigned int qspi_ctrl_pins[] = {
-	/* SPCLK, SSL */
-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
-};
-static const unsigned int qspi_ctrl_mux[] = {
-	SPCLK_MARK, SSL_MARK,
-};
-static const unsigned int qspi_data2_pins[] = {
-	/* MOSI_IO0, MISO_IO1 */
-	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
-};
-static const unsigned int qspi_data2_mux[] = {
-	MOSI_IO0_MARK, MISO_IO1_MARK,
-};
-static const unsigned int qspi_data4_pins[] = {
-	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
-	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-	RCAR_GP_PIN(1, 8),
-};
-static const unsigned int qspi_data4_mux[] = {
-	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
-};
-/* - SCIF0 ------------------------------------------------------------------ */
-static const unsigned int scif0_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
-};
-static const unsigned int scif0_data_mux[] = {
-	RX0_MARK, TX0_MARK,
-};
-static const unsigned int scif0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 27),
-};
-static const unsigned int scif0_clk_mux[] = {
-	SCK0_MARK,
-};
-static const unsigned int scif0_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
-};
-static const unsigned int scif0_ctrl_mux[] = {
-	RTS0_N_MARK, CTS0_N_MARK,
-};
-static const unsigned int scif0_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-};
-static const unsigned int scif0_data_b_mux[] = {
-	RX0_B_MARK, TX0_B_MARK,
-};
-/* - SCIF1 ------------------------------------------------------------------ */
-static const unsigned int scif1_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
-};
-static const unsigned int scif1_data_mux[] = {
-	RX1_MARK, TX1_MARK,
-};
-static const unsigned int scif1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 20),
-};
-static const unsigned int scif1_clk_mux[] = {
-	SCK1_MARK,
-};
-static const unsigned int scif1_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
-};
-static const unsigned int scif1_ctrl_mux[] = {
-	RTS1_N_MARK, CTS1_N_MARK,
-};
-static const unsigned int scif1_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-};
-static const unsigned int scif1_data_b_mux[] = {
-	RX1_B_MARK, TX1_B_MARK,
-};
-static const unsigned int scif1_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
-};
-static const unsigned int scif1_data_c_mux[] = {
-	RX1_C_MARK, TX1_C_MARK,
-};
-static const unsigned int scif1_data_d_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
-};
-static const unsigned int scif1_data_d_mux[] = {
-	RX1_D_MARK, TX1_D_MARK,
-};
-static const unsigned int scif1_clk_d_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 17),
-};
-static const unsigned int scif1_clk_d_mux[] = {
-	SCK1_D_MARK,
-};
-static const unsigned int scif1_data_e_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
-};
-static const unsigned int scif1_data_e_mux[] = {
-	RX1_E_MARK, TX1_E_MARK,
-};
-static const unsigned int scif1_clk_e_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 20),
-};
-static const unsigned int scif1_clk_e_mux[] = {
-	SCK1_E_MARK,
-};
-/* - SCIF2 ------------------------------------------------------------------ */
-static const unsigned int scif2_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
-};
-static const unsigned int scif2_data_mux[] = {
-	RX2_MARK, TX2_MARK,
-};
-static const unsigned int scif2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 4),
-};
-static const unsigned int scif2_clk_mux[] = {
-	SCK2_MARK,
-};
-static const unsigned int scif2_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
-};
-static const unsigned int scif2_data_b_mux[] = {
-	RX2_B_MARK, TX2_B_MARK,
-};
-/* - SCIFA0 ----------------------------------------------------------------- */
-static const unsigned int scifa0_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
-};
-static const unsigned int scifa0_data_mux[] = {
-	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
-};
-static const unsigned int scifa0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 27),
-};
-static const unsigned int scifa0_clk_mux[] = {
-	SCIFA0_SCK_MARK,
-};
-static const unsigned int scifa0_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
-};
-static const unsigned int scifa0_ctrl_mux[] = {
-	SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
-};
-static const unsigned int scifa0_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
-};
-static const unsigned int scifa0_data_b_mux[] = {
-	SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
-};
-static const unsigned int scifa0_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 19),
-};
-static const unsigned int scifa0_clk_b_mux[] = {
-	SCIFA0_SCK_B_MARK,
-};
-static const unsigned int scifa0_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
-};
-static const unsigned int scifa0_ctrl_b_mux[] = {
-	SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
-};
-/* - SCIFA1 ----------------------------------------------------------------- */
-static const unsigned int scifa1_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
-};
-static const unsigned int scifa1_data_mux[] = {
-	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
-};
-static const unsigned int scifa1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 20),
-};
-static const unsigned int scifa1_clk_mux[] = {
-	SCIFA1_SCK_MARK,
-};
-static const unsigned int scifa1_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
-};
-static const unsigned int scifa1_ctrl_mux[] = {
-	SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
-};
-static const unsigned int scifa1_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
-};
-static const unsigned int scifa1_data_b_mux[] = {
-	SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
-};
-static const unsigned int scifa1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 23),
-};
-static const unsigned int scifa1_clk_b_mux[] = {
-	SCIFA1_SCK_B_MARK,
-};
-static const unsigned int scifa1_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
-};
-static const unsigned int scifa1_ctrl_b_mux[] = {
-	SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
-};
-static const unsigned int scifa1_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
-};
-static const unsigned int scifa1_data_c_mux[] = {
-	SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
-};
-static const unsigned int scifa1_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 8),
-};
-static const unsigned int scifa1_clk_c_mux[] = {
-	SCIFA1_SCK_C_MARK,
-};
-static const unsigned int scifa1_ctrl_c_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
-};
-static const unsigned int scifa1_ctrl_c_mux[] = {
-	SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
-};
-static const unsigned int scifa1_data_d_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
-};
-static const unsigned int scifa1_data_d_mux[] = {
-	SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
-};
-static const unsigned int scifa1_clk_d_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 10),
-};
-static const unsigned int scifa1_clk_d_mux[] = {
-	SCIFA1_SCK_D_MARK,
-};
-static const unsigned int scifa1_ctrl_d_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
-};
-static const unsigned int scifa1_ctrl_d_mux[] = {
-	SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
-};
-/* - SCIFA2 ----------------------------------------------------------------- */
-static const unsigned int scifa2_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
-};
-static const unsigned int scifa2_data_mux[] = {
-	SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
-};
-static const unsigned int scifa2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 4),
-};
-static const unsigned int scifa2_clk_mux[] = {
-	SCIFA2_SCK_MARK,
-};
-static const unsigned int scifa2_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
-};
-static const unsigned int scifa2_ctrl_mux[] = {
-	SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
-};
-static const unsigned int scifa2_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
-};
-static const unsigned int scifa2_data_b_mux[] = {
-	SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
-};
-static const unsigned int scifa2_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
-};
-static const unsigned int scifa2_data_c_mux[] = {
-	SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
-};
-static const unsigned int scifa2_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 29),
-};
-static const unsigned int scifa2_clk_c_mux[] = {
-	SCIFA2_SCK_C_MARK,
-};
-/* - SCIFB0 ----------------------------------------------------------------- */
-static const unsigned int scifb0_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
-};
-static const unsigned int scifb0_data_mux[] = {
-	SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
-};
-static const unsigned int scifb0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 8),
-};
-static const unsigned int scifb0_clk_mux[] = {
-	SCIFB0_SCK_MARK,
-};
-static const unsigned int scifb0_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
-};
-static const unsigned int scifb0_ctrl_mux[] = {
-	SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
-};
-static const unsigned int scifb0_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-};
-static const unsigned int scifb0_data_b_mux[] = {
-	SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
-};
-static const unsigned int scifb0_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 9),
-};
-static const unsigned int scifb0_clk_b_mux[] = {
-	SCIFB0_SCK_B_MARK,
-};
-static const unsigned int scifb0_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
-};
-static const unsigned int scifb0_ctrl_b_mux[] = {
-	SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
-};
-static const unsigned int scifb0_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-};
-static const unsigned int scifb0_data_c_mux[] = {
-	SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
-};
-/* - SCIFB1 ----------------------------------------------------------------- */
-static const unsigned int scifb1_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
-};
-static const unsigned int scifb1_data_mux[] = {
-	SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
-};
-static const unsigned int scifb1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 14),
-};
-static const unsigned int scifb1_clk_mux[] = {
-	SCIFB1_SCK_MARK,
-};
-static const unsigned int scifb1_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
-};
-static const unsigned int scifb1_ctrl_mux[] = {
-	SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
-};
-static const unsigned int scifb1_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
-};
-static const unsigned int scifb1_data_b_mux[] = {
-	SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
-};
-static const unsigned int scifb1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 1),
-};
-static const unsigned int scifb1_clk_b_mux[] = {
-	SCIFB1_SCK_B_MARK,
-};
-static const unsigned int scifb1_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
-};
-static const unsigned int scifb1_ctrl_b_mux[] = {
-	SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
-};
-static const unsigned int scifb1_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-};
-static const unsigned int scifb1_data_c_mux[] = {
-	SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
-};
-static const unsigned int scifb1_data_d_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
-};
-static const unsigned int scifb1_data_d_mux[] = {
-	SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
-};
-static const unsigned int scifb1_data_e_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
-};
-static const unsigned int scifb1_data_e_mux[] = {
-	SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
-};
-static const unsigned int scifb1_clk_e_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 17),
-};
-static const unsigned int scifb1_clk_e_mux[] = {
-	SCIFB1_SCK_E_MARK,
-};
-static const unsigned int scifb1_data_f_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-};
-static const unsigned int scifb1_data_f_mux[] = {
-	SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
-};
-static const unsigned int scifb1_data_g_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
-};
-static const unsigned int scifb1_data_g_mux[] = {
-	SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
-};
-static const unsigned int scifb1_clk_g_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 20),
-};
-static const unsigned int scifb1_clk_g_mux[] = {
-	SCIFB1_SCK_G_MARK,
-};
-/* - SCIFB2 ----------------------------------------------------------------- */
-static const unsigned int scifb2_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
-};
-static const unsigned int scifb2_data_mux[] = {
-	SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
-};
-static const unsigned int scifb2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 21),
-};
-static const unsigned int scifb2_clk_mux[] = {
-	SCIFB2_SCK_MARK,
-};
-static const unsigned int scifb2_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
-};
-static const unsigned int scifb2_ctrl_mux[] = {
-	SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
-};
-static const unsigned int scifb2_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
-};
-static const unsigned int scifb2_data_b_mux[] = {
-	SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
-};
-static const unsigned int scifb2_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 31),
-};
-static const unsigned int scifb2_clk_b_mux[] = {
-	SCIFB2_SCK_B_MARK,
-};
-static const unsigned int scifb2_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
-};
-static const unsigned int scifb2_ctrl_b_mux[] = {
-	SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
-};
-static const unsigned int scifb2_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
-};
-static const unsigned int scifb2_data_c_mux[] = {
-	SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
-};
-/* - SCIF Clock ------------------------------------------------------------- */
-static const unsigned int scif_clk_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(4, 26),
-};
-static const unsigned int scif_clk_mux[] = {
-	SCIF_CLK_MARK,
-};
-static const unsigned int scif_clk_b_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(5, 4),
-};
-static const unsigned int scif_clk_b_mux[] = {
-	SCIF_CLK_B_MARK,
-};
-/* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 2),
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SD0_DAT0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
-};
-static const unsigned int sdhi0_data4_mux[] = {
-	SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
-};
-static const unsigned int sdhi0_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
-};
-static const unsigned int sdhi0_ctrl_mux[] = {
-	SD0_CLK_MARK, SD0_CMD_MARK,
-};
-static const unsigned int sdhi0_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(3, 6),
-};
-static const unsigned int sdhi0_cd_mux[] = {
-	SD0_CD_MARK,
-};
-static const unsigned int sdhi0_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(3, 7),
-};
-static const unsigned int sdhi0_wp_mux[] = {
-	SD0_WP_MARK,
-};
-/* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 10),
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	SD1_DAT0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
-};
-static const unsigned int sdhi1_data4_mux[] = {
-	SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
-};
-static const unsigned int sdhi1_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-};
-static const unsigned int sdhi1_ctrl_mux[] = {
-	SD1_CLK_MARK, SD1_CMD_MARK,
-};
-static const unsigned int sdhi1_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(3, 14),
-};
-static const unsigned int sdhi1_cd_mux[] = {
-	SD1_CD_MARK,
-};
-static const unsigned int sdhi1_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(3, 15),
-};
-static const unsigned int sdhi1_wp_mux[] = {
-	SD1_WP_MARK,
-};
-/* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 18),
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SD2_DAT0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
-};
-static const unsigned int sdhi2_data4_mux[] = {
-	SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
-};
-static const unsigned int sdhi2_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
-};
-static const unsigned int sdhi2_ctrl_mux[] = {
-	SD2_CLK_MARK, SD2_CMD_MARK,
-};
-static const unsigned int sdhi2_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(3, 22),
-};
-static const unsigned int sdhi2_cd_mux[] = {
-	SD2_CD_MARK,
-};
-static const unsigned int sdhi2_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(3, 23),
-};
-static const unsigned int sdhi2_wp_mux[] = {
-	SD2_WP_MARK,
-};
-/* - SDHI3 ------------------------------------------------------------------ */
-static const unsigned int sdhi3_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 26),
-};
-static const unsigned int sdhi3_data1_mux[] = {
-	SD3_DAT0_MARK,
-};
-static const unsigned int sdhi3_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
-};
-static const unsigned int sdhi3_data4_mux[] = {
-	SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
-};
-static const unsigned int sdhi3_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
-};
-static const unsigned int sdhi3_ctrl_mux[] = {
-	SD3_CLK_MARK, SD3_CMD_MARK,
-};
-static const unsigned int sdhi3_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(3, 30),
-};
-static const unsigned int sdhi3_cd_mux[] = {
-	SD3_CD_MARK,
-};
-static const unsigned int sdhi3_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(3, 31),
-};
-static const unsigned int sdhi3_wp_mux[] = {
-	SD3_WP_MARK,
-};
-/* - SSI -------------------------------------------------------------------- */
-static const unsigned int ssi0_data_pins[] = {
-	/* SDATA0 */
-	RCAR_GP_PIN(4, 5),
-};
-static const unsigned int ssi0_data_mux[] = {
-	SSI_SDATA0_MARK,
-};
-static const unsigned int ssi0129_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4),
-};
-static const unsigned int ssi0129_ctrl_mux[] = {
-	SSI_SCK0129_MARK, SSI_WS0129_MARK,
-};
-static const unsigned int ssi1_data_pins[] = {
-	/* SDATA1 */
-	RCAR_GP_PIN(4, 6),
-};
-static const unsigned int ssi1_data_mux[] = {
-	SSI_SDATA1_MARK,
-};
-static const unsigned int ssi1_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24),
-};
-static const unsigned int ssi1_ctrl_mux[] = {
-	SSI_SCK1_MARK, SSI_WS1_MARK,
-};
-static const unsigned int ssi2_data_pins[] = {
-	/* SDATA2 */
-	RCAR_GP_PIN(4, 7),
-};
-static const unsigned int ssi2_data_mux[] = {
-	SSI_SDATA2_MARK,
-};
-static const unsigned int ssi2_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17),
-};
-static const unsigned int ssi2_ctrl_mux[] = {
-	SSI_SCK2_MARK, SSI_WS2_MARK,
-};
-static const unsigned int ssi3_data_pins[] = {
-	/* SDATA3 */
-	RCAR_GP_PIN(4, 10),
-};
-static const unsigned int ssi3_data_mux[] = {
-	SSI_SDATA3_MARK
-};
-static const unsigned int ssi34_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
-};
-static const unsigned int ssi34_ctrl_mux[] = {
-	SSI_SCK34_MARK, SSI_WS34_MARK,
-};
-static const unsigned int ssi4_data_pins[] = {
-	/* SDATA4 */
-	RCAR_GP_PIN(4, 13),
-};
-static const unsigned int ssi4_data_mux[] = {
-	SSI_SDATA4_MARK,
-};
-static const unsigned int ssi4_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
-};
-static const unsigned int ssi4_ctrl_mux[] = {
-	SSI_SCK4_MARK, SSI_WS4_MARK,
-};
-static const unsigned int ssi5_pins[] = {
-	/* SDATA5, SCK, WS */
-	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
-};
-static const unsigned int ssi5_mux[] = {
-	SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK,
-};
-static const unsigned int ssi5_b_pins[] = {
-	/* SDATA5, SCK, WS */
-	RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
-};
-static const unsigned int ssi5_b_mux[] = {
-	SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK
-};
-static const unsigned int ssi5_c_pins[] = {
-	/* SDATA5, SCK, WS */
-	RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
-};
-static const unsigned int ssi5_c_mux[] = {
-	SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK,
-};
-static const unsigned int ssi6_pins[] = {
-	/* SDATA6, SCK, WS */
-	RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
-};
-static const unsigned int ssi6_mux[] = {
-	SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK,
-};
-static const unsigned int ssi6_b_pins[] = {
-	/* SDATA6, SCK, WS */
-	RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27),
-};
-static const unsigned int ssi6_b_mux[] = {
-	SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
-};
-static const unsigned int ssi7_data_pins[] = {
-	/* SDATA7 */
-	RCAR_GP_PIN(4, 22),
-};
-static const unsigned int ssi7_data_mux[] = {
-	SSI_SDATA7_MARK,
-};
-static const unsigned int ssi7_b_data_pins[] = {
-	/* SDATA7 */
-	RCAR_GP_PIN(4, 22),
-};
-static const unsigned int ssi7_b_data_mux[] = {
-	SSI_SDATA7_B_MARK,
-};
-static const unsigned int ssi7_c_data_pins[] = {
-	/* SDATA7 */
-	RCAR_GP_PIN(1, 26),
-};
-static const unsigned int ssi7_c_data_mux[] = {
-	SSI_SDATA7_C_MARK,
-};
-static const unsigned int ssi78_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
-};
-static const unsigned int ssi78_ctrl_mux[] = {
-	SSI_SCK78_MARK, SSI_WS78_MARK,
-};
-static const unsigned int ssi78_b_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24),
-};
-static const unsigned int ssi78_b_ctrl_mux[] = {
-	SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
-};
-static const unsigned int ssi78_c_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
-};
-static const unsigned int ssi78_c_ctrl_mux[] = {
-	SSI_SCK78_C_MARK, SSI_WS78_C_MARK,
-};
-static const unsigned int ssi8_data_pins[] = {
-	/* SDATA8 */
-	RCAR_GP_PIN(4, 23),
-};
-static const unsigned int ssi8_data_mux[] = {
-	SSI_SDATA8_MARK,
-};
-static const unsigned int ssi8_b_data_pins[] = {
-	/* SDATA8 */
-	RCAR_GP_PIN(4, 23),
-};
-static const unsigned int ssi8_b_data_mux[] = {
-	SSI_SDATA8_B_MARK,
-};
-static const unsigned int ssi8_c_data_pins[] = {
-	/* SDATA8 */
-	RCAR_GP_PIN(1, 27),
-};
-static const unsigned int ssi8_c_data_mux[] = {
-	SSI_SDATA8_C_MARK,
-};
-static const unsigned int ssi9_data_pins[] = {
-	/* SDATA9 */
-	RCAR_GP_PIN(4, 24),
-};
-static const unsigned int ssi9_data_mux[] = {
-	SSI_SDATA9_MARK,
-};
-static const unsigned int ssi9_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
-};
-static const unsigned int ssi9_ctrl_mux[] = {
-	SSI_SCK9_MARK, SSI_WS9_MARK,
-};
-/* - TPU0 ------------------------------------------------------------------- */
-static const unsigned int tpu0_to0_pins[] = {
-	/* TO */
-	RCAR_GP_PIN(0, 20),
-};
-static const unsigned int tpu0_to0_mux[] = {
-	TPU0TO0_MARK,
-};
-static const unsigned int tpu0_to1_pins[] = {
-	/* TO */
-	RCAR_GP_PIN(0, 21),
-};
-static const unsigned int tpu0_to1_mux[] = {
-	TPU0TO1_MARK,
-};
-static const unsigned int tpu0_to2_pins[] = {
-	/* TO */
-	RCAR_GP_PIN(0, 22),
-};
-static const unsigned int tpu0_to2_mux[] = {
-	TPU0TO2_MARK,
-};
-static const unsigned int tpu0_to3_pins[] = {
-	/* TO */
-	RCAR_GP_PIN(0, 23),
-};
-static const unsigned int tpu0_to3_mux[] = {
-	TPU0TO3_MARK,
-};
-/* - USB0 ------------------------------------------------------------------- */
-static const unsigned int usb0_pins[] = {
-	/* PWEN, OVC/VBUS */
-	RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
-};
-static const unsigned int usb0_mux[] = {
-	USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
-};
-static const unsigned int usb0_ovc_vbus_pins[] = {
-	/* OVC/VBUS */
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int usb0_ovc_vbus_mux[] = {
-	USB0_OVC_VBUS_MARK,
-};
-/* - USB1 ------------------------------------------------------------------- */
-static const unsigned int usb1_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
-};
-static const unsigned int usb1_mux[] = {
-	USB1_PWEN_MARK, USB1_OVC_MARK,
-};
-/* - USB2 ------------------------------------------------------------------- */
-static const unsigned int usb2_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
-};
-static const unsigned int usb2_mux[] = {
-	USB2_PWEN_MARK, USB2_OVC_MARK,
-};
-/* - VIN0 ------------------------------------------------------------------- */
-static const union vin_data vin0_data_pins = {
-	.data24 = {
-		/* B */
-		RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
-		RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
-		RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
-		RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
-		/* G */
-		RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-		/* R */
-		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-		RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
-		RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
-	},
-};
-static const union vin_data vin0_data_mux = {
-	.data24 = {
-		/* B */
-		VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
-		VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
-		VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
-		VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
-		/* G */
-		VI0_G0_MARK, VI0_G1_MARK,
-		VI0_G2_MARK, VI0_G3_MARK,
-		VI0_G4_MARK, VI0_G5_MARK,
-		VI0_G6_MARK, VI0_G7_MARK,
-		/* R */
-		VI0_R0_MARK, VI0_R1_MARK,
-		VI0_R2_MARK, VI0_R3_MARK,
-		VI0_R4_MARK, VI0_R5_MARK,
-		VI0_R6_MARK, VI0_R7_MARK,
-	},
-};
-static const unsigned int vin0_data18_pins[] = {
-	/* B */
-	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
-	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
-	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
-	/* G */
-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-	/* R */
-	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
-	RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
-};
-static const unsigned int vin0_data18_mux[] = {
-	/* B */
-	VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
-	VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
-	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
-	/* G */
-	VI0_G2_MARK, VI0_G3_MARK,
-	VI0_G4_MARK, VI0_G5_MARK,
-	VI0_G6_MARK, VI0_G7_MARK,
-	/* R */
-	VI0_R2_MARK, VI0_R3_MARK,
-	VI0_R4_MARK, VI0_R5_MARK,
-	VI0_R6_MARK, VI0_R7_MARK,
-};
-static const unsigned int vin0_sync_pins[] = {
-	RCAR_GP_PIN(0, 12), /* HSYNC */
-	RCAR_GP_PIN(0, 13), /* VSYNC */
-};
-static const unsigned int vin0_sync_mux[] = {
-	VI0_HSYNC_N_MARK,
-	VI0_VSYNC_N_MARK,
-};
-static const unsigned int vin0_field_pins[] = {
-	RCAR_GP_PIN(0, 15),
-};
-static const unsigned int vin0_field_mux[] = {
-	VI0_FIELD_MARK,
-};
-static const unsigned int vin0_clkenb_pins[] = {
-	RCAR_GP_PIN(0, 14),
-};
-static const unsigned int vin0_clkenb_mux[] = {
-	VI0_CLKENB_MARK,
-};
-static const unsigned int vin0_clk_pins[] = {
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int vin0_clk_mux[] = {
-	VI0_CLK_MARK,
-};
-/* - VIN1 ------------------------------------------------------------------- */
-static const union vin_data vin1_data_pins = {
-	.data24 = {
-		/* B */
-		RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
-		RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
-		RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
-		RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
-		/* G */
-		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-		RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
-		RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
-		RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
-		/* R */
-		RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
-		RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
-		RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
-		RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
-	},
-};
-static const union vin_data vin1_data_mux = {
-	.data24 = {
-		/* B */
-		VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
-		VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
-		VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
-		VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
-		/* G */
-		VI1_G0_MARK, VI1_G1_MARK,
-		VI1_G2_MARK, VI1_G3_MARK,
-		VI1_G4_MARK, VI1_G5_MARK,
-		VI1_G6_MARK, VI1_G7_MARK,
-		/* R */
-		VI1_R0_MARK, VI1_R1_MARK,
-		VI1_R2_MARK, VI1_R3_MARK,
-		VI1_R4_MARK, VI1_R5_MARK,
-		VI1_R6_MARK, VI1_R7_MARK,
-	},
-};
-static const unsigned int vin1_data18_pins[] = {
-	/* B */
-	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
-	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
-	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
-	/* G */
-	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
-	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
-	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
-	/* R */
-	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
-	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
-	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
-};
-static const unsigned int vin1_data18_mux[] = {
-	/* B */
-	VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
-	VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
-	VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
-	/* G */
-	VI1_G2_MARK, VI1_G3_MARK,
-	VI1_G4_MARK, VI1_G5_MARK,
-	VI1_G6_MARK, VI1_G7_MARK,
-	/* R */
-	VI1_R2_MARK, VI1_R3_MARK,
-	VI1_R4_MARK, VI1_R5_MARK,
-	VI1_R6_MARK, VI1_R7_MARK,
-};
-static const unsigned int vin1_sync_pins[] = {
-	RCAR_GP_PIN(1, 24), /* HSYNC */
-	RCAR_GP_PIN(1, 25), /* VSYNC */
-};
-static const unsigned int vin1_sync_mux[] = {
-	VI1_HSYNC_N_MARK,
-	VI1_VSYNC_N_MARK,
-};
-static const unsigned int vin1_field_pins[] = {
-	RCAR_GP_PIN(1, 13),
-};
-static const unsigned int vin1_field_mux[] = {
-	VI1_FIELD_MARK,
-};
-static const unsigned int vin1_clkenb_pins[] = {
-	RCAR_GP_PIN(1, 26),
-};
-static const unsigned int vin1_clkenb_mux[] = {
-	VI1_CLKENB_MARK,
-};
-static const unsigned int vin1_clk_pins[] = {
-	RCAR_GP_PIN(2, 9),
-};
-static const unsigned int vin1_clk_mux[] = {
-	VI1_CLK_MARK,
-};
-/* - VIN2 ----------------------------------------------------------------- */
-static const union vin_data vin2_data_pins = {
-	.data24 = {
-		/* B */
-		RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-		RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-		RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-		/* G */
-		RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
-		RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
-		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-		/* R */
-		RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-		RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
-		RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
-	},
-};
-static const union vin_data vin2_data_mux = {
-	.data24 = {
-		/* B */
-		VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
-		VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
-		VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
-		VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
-		/* G */
-		VI2_G0_MARK, VI2_G1_MARK,
-		VI2_G2_MARK, VI2_G3_MARK,
-		VI2_G4_MARK, VI2_G5_MARK,
-		VI2_G6_MARK, VI2_G7_MARK,
-		/* R */
-		VI2_R0_MARK, VI2_R1_MARK,
-		VI2_R2_MARK, VI2_R3_MARK,
-		VI2_R4_MARK, VI2_R5_MARK,
-		VI2_R6_MARK, VI2_R7_MARK,
-	},
-};
-static const unsigned int vin2_data18_pins[] = {
-	/* B */
-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-	/* G */
-	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-	/* R */
-	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
-	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
-};
-static const unsigned int vin2_data18_mux[] = {
-	/* B */
-	VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
-	VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
-	VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
-	/* G */
-	VI2_G2_MARK, VI2_G3_MARK,
-	VI2_G4_MARK, VI2_G5_MARK,
-	VI2_G6_MARK, VI2_G7_MARK,
-	/* R */
-	VI2_R2_MARK, VI2_R3_MARK,
-	VI2_R4_MARK, VI2_R5_MARK,
-	VI2_R6_MARK, VI2_R7_MARK,
-};
-static const unsigned int vin2_sync_pins[] = {
-	RCAR_GP_PIN(1, 16), /* HSYNC */
-	RCAR_GP_PIN(1, 21), /* VSYNC */
-};
-static const unsigned int vin2_sync_mux[] = {
-	VI2_HSYNC_N_MARK,
-	VI2_VSYNC_N_MARK,
-};
-static const unsigned int vin2_field_pins[] = {
-	RCAR_GP_PIN(1, 9),
-};
-static const unsigned int vin2_field_mux[] = {
-	VI2_FIELD_MARK,
-};
-static const unsigned int vin2_clkenb_pins[] = {
-	RCAR_GP_PIN(1, 8),
-};
-static const unsigned int vin2_clkenb_mux[] = {
-	VI2_CLKENB_MARK,
-};
-static const unsigned int vin2_clk_pins[] = {
-	RCAR_GP_PIN(1, 11),
-};
-static const unsigned int vin2_clk_mux[] = {
-	VI2_CLK_MARK,
-};
-/* - VIN3 ----------------------------------------------------------------- */
-static const unsigned int vin3_data8_pins[] = {
-	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-};
-static const unsigned int vin3_data8_mux[] = {
-	VI3_DATA0_MARK, VI3_DATA1_MARK,
-	VI3_DATA2_MARK, VI3_DATA3_MARK,
-	VI3_DATA4_MARK, VI3_DATA5_MARK,
-	VI3_DATA6_MARK, VI3_DATA7_MARK,
-};
-static const unsigned int vin3_sync_pins[] = {
-	RCAR_GP_PIN(1, 16), /* HSYNC */
-	RCAR_GP_PIN(1, 17), /* VSYNC */
-};
-static const unsigned int vin3_sync_mux[] = {
-	VI3_HSYNC_N_MARK,
-	VI3_VSYNC_N_MARK,
-};
-static const unsigned int vin3_field_pins[] = {
-	RCAR_GP_PIN(1, 15),
-};
-static const unsigned int vin3_field_mux[] = {
-	VI3_FIELD_MARK,
-};
-static const unsigned int vin3_clkenb_pins[] = {
-	RCAR_GP_PIN(1, 14),
-};
-static const unsigned int vin3_clkenb_mux[] = {
-	VI3_CLKENB_MARK,
-};
-static const unsigned int vin3_clk_pins[] = {
-	RCAR_GP_PIN(1, 23),
-};
-static const unsigned int vin3_clk_mux[] = {
-	VI3_CLK_MARK,
-};
-
-static const struct sh_pfc_pin_group pinmux_groups[] = {
-	SH_PFC_PIN_GROUP(audio_clk_a),
-	SH_PFC_PIN_GROUP(audio_clk_b),
-	SH_PFC_PIN_GROUP(audio_clk_c),
-	SH_PFC_PIN_GROUP(audio_clkout),
-	SH_PFC_PIN_GROUP(audio_clkout_b),
-	SH_PFC_PIN_GROUP(audio_clkout_c),
-	SH_PFC_PIN_GROUP(audio_clkout_d),
-	SH_PFC_PIN_GROUP(avb_link),
-	SH_PFC_PIN_GROUP(avb_magic),
-	SH_PFC_PIN_GROUP(avb_phy_int),
-	SH_PFC_PIN_GROUP(avb_mdio),
-	SH_PFC_PIN_GROUP(avb_mii),
-	SH_PFC_PIN_GROUP(avb_gmii),
-	SH_PFC_PIN_GROUP(du_rgb666),
-	SH_PFC_PIN_GROUP(du_rgb888),
-	SH_PFC_PIN_GROUP(du_clk_out_0),
-	SH_PFC_PIN_GROUP(du_clk_out_1),
-	SH_PFC_PIN_GROUP(du_sync_0),
-	SH_PFC_PIN_GROUP(du_sync_1),
-	SH_PFC_PIN_GROUP(du_cde),
-	SH_PFC_PIN_GROUP(du0_clk_in),
-	SH_PFC_PIN_GROUP(du1_clk_in),
-	SH_PFC_PIN_GROUP(du2_clk_in),
-	SH_PFC_PIN_GROUP(eth_link),
-	SH_PFC_PIN_GROUP(eth_magic),
-	SH_PFC_PIN_GROUP(eth_mdio),
-	SH_PFC_PIN_GROUP(eth_rmii),
-	SH_PFC_PIN_GROUP(hscif0_data),
-	SH_PFC_PIN_GROUP(hscif0_clk),
-	SH_PFC_PIN_GROUP(hscif0_ctrl),
-	SH_PFC_PIN_GROUP(hscif0_data_b),
-	SH_PFC_PIN_GROUP(hscif0_ctrl_b),
-	SH_PFC_PIN_GROUP(hscif0_data_c),
-	SH_PFC_PIN_GROUP(hscif0_ctrl_c),
-	SH_PFC_PIN_GROUP(hscif0_data_d),
-	SH_PFC_PIN_GROUP(hscif0_ctrl_d),
-	SH_PFC_PIN_GROUP(hscif0_data_e),
-	SH_PFC_PIN_GROUP(hscif0_ctrl_e),
-	SH_PFC_PIN_GROUP(hscif0_data_f),
-	SH_PFC_PIN_GROUP(hscif0_ctrl_f),
-	SH_PFC_PIN_GROUP(hscif1_data),
-	SH_PFC_PIN_GROUP(hscif1_clk),
-	SH_PFC_PIN_GROUP(hscif1_ctrl),
-	SH_PFC_PIN_GROUP(hscif1_data_b),
-	SH_PFC_PIN_GROUP(hscif1_clk_b),
-	SH_PFC_PIN_GROUP(hscif1_ctrl_b),
-	SH_PFC_PIN_GROUP(i2c0),
-	SH_PFC_PIN_GROUP(i2c1),
-	SH_PFC_PIN_GROUP(i2c1_b),
-	SH_PFC_PIN_GROUP(i2c1_c),
-	SH_PFC_PIN_GROUP(i2c2),
-	SH_PFC_PIN_GROUP(i2c2_b),
-	SH_PFC_PIN_GROUP(i2c2_c),
-	SH_PFC_PIN_GROUP(i2c2_d),
-	SH_PFC_PIN_GROUP(i2c2_e),
-	SH_PFC_PIN_GROUP(i2c3),
-	SH_PFC_PIN_GROUP(iic0),
-	SH_PFC_PIN_GROUP(iic1),
-	SH_PFC_PIN_GROUP(iic1_b),
-	SH_PFC_PIN_GROUP(iic1_c),
-	SH_PFC_PIN_GROUP(iic2),
-	SH_PFC_PIN_GROUP(iic2_b),
-	SH_PFC_PIN_GROUP(iic2_c),
-	SH_PFC_PIN_GROUP(iic2_d),
-	SH_PFC_PIN_GROUP(iic2_e),
-	SH_PFC_PIN_GROUP(iic3),
-	SH_PFC_PIN_GROUP(intc_irq0),
-	SH_PFC_PIN_GROUP(intc_irq1),
-	SH_PFC_PIN_GROUP(intc_irq2),
-	SH_PFC_PIN_GROUP(intc_irq3),
-	SH_PFC_PIN_GROUP(mlb_3pin),
-	SH_PFC_PIN_GROUP(mmc0_data1),
-	SH_PFC_PIN_GROUP(mmc0_data4),
-	SH_PFC_PIN_GROUP(mmc0_data8),
-	SH_PFC_PIN_GROUP(mmc0_ctrl),
-	SH_PFC_PIN_GROUP(mmc1_data1),
-	SH_PFC_PIN_GROUP(mmc1_data4),
-	SH_PFC_PIN_GROUP(mmc1_data8),
-	SH_PFC_PIN_GROUP(mmc1_ctrl),
-	SH_PFC_PIN_GROUP(msiof0_clk),
-	SH_PFC_PIN_GROUP(msiof0_sync),
-	SH_PFC_PIN_GROUP(msiof0_ss1),
-	SH_PFC_PIN_GROUP(msiof0_ss2),
-	SH_PFC_PIN_GROUP(msiof0_rx),
-	SH_PFC_PIN_GROUP(msiof0_tx),
-	SH_PFC_PIN_GROUP(msiof0_clk_b),
-	SH_PFC_PIN_GROUP(msiof0_ss1_b),
-	SH_PFC_PIN_GROUP(msiof0_ss2_b),
-	SH_PFC_PIN_GROUP(msiof0_rx_b),
-	SH_PFC_PIN_GROUP(msiof0_tx_b),
-	SH_PFC_PIN_GROUP(msiof1_clk),
-	SH_PFC_PIN_GROUP(msiof1_sync),
-	SH_PFC_PIN_GROUP(msiof1_ss1),
-	SH_PFC_PIN_GROUP(msiof1_ss2),
-	SH_PFC_PIN_GROUP(msiof1_rx),
-	SH_PFC_PIN_GROUP(msiof1_tx),
-	SH_PFC_PIN_GROUP(msiof1_clk_b),
-	SH_PFC_PIN_GROUP(msiof1_ss1_b),
-	SH_PFC_PIN_GROUP(msiof1_ss2_b),
-	SH_PFC_PIN_GROUP(msiof1_rx_b),
-	SH_PFC_PIN_GROUP(msiof1_tx_b),
-	SH_PFC_PIN_GROUP(msiof2_clk),
-	SH_PFC_PIN_GROUP(msiof2_sync),
-	SH_PFC_PIN_GROUP(msiof2_ss1),
-	SH_PFC_PIN_GROUP(msiof2_ss2),
-	SH_PFC_PIN_GROUP(msiof2_rx),
-	SH_PFC_PIN_GROUP(msiof2_tx),
-	SH_PFC_PIN_GROUP(msiof3_clk),
-	SH_PFC_PIN_GROUP(msiof3_sync),
-	SH_PFC_PIN_GROUP(msiof3_ss1),
-	SH_PFC_PIN_GROUP(msiof3_ss2),
-	SH_PFC_PIN_GROUP(msiof3_rx),
-	SH_PFC_PIN_GROUP(msiof3_tx),
-	SH_PFC_PIN_GROUP(msiof3_clk_b),
-	SH_PFC_PIN_GROUP(msiof3_sync_b),
-	SH_PFC_PIN_GROUP(msiof3_rx_b),
-	SH_PFC_PIN_GROUP(msiof3_tx_b),
-	SH_PFC_PIN_GROUP(pwm0),
-	SH_PFC_PIN_GROUP(pwm0_b),
-	SH_PFC_PIN_GROUP(pwm1),
-	SH_PFC_PIN_GROUP(pwm1_b),
-	SH_PFC_PIN_GROUP(pwm2),
-	SH_PFC_PIN_GROUP(pwm3),
-	SH_PFC_PIN_GROUP(pwm4),
-	SH_PFC_PIN_GROUP(pwm5),
-	SH_PFC_PIN_GROUP(pwm6),
-	SH_PFC_PIN_GROUP(qspi_ctrl),
-	SH_PFC_PIN_GROUP(qspi_data2),
-	SH_PFC_PIN_GROUP(qspi_data4),
-	SH_PFC_PIN_GROUP(scif0_data),
-	SH_PFC_PIN_GROUP(scif0_clk),
-	SH_PFC_PIN_GROUP(scif0_ctrl),
-	SH_PFC_PIN_GROUP(scif0_data_b),
-	SH_PFC_PIN_GROUP(scif1_data),
-	SH_PFC_PIN_GROUP(scif1_clk),
-	SH_PFC_PIN_GROUP(scif1_ctrl),
-	SH_PFC_PIN_GROUP(scif1_data_b),
-	SH_PFC_PIN_GROUP(scif1_data_c),
-	SH_PFC_PIN_GROUP(scif1_data_d),
-	SH_PFC_PIN_GROUP(scif1_clk_d),
-	SH_PFC_PIN_GROUP(scif1_data_e),
-	SH_PFC_PIN_GROUP(scif1_clk_e),
-	SH_PFC_PIN_GROUP(scif2_data),
-	SH_PFC_PIN_GROUP(scif2_clk),
-	SH_PFC_PIN_GROUP(scif2_data_b),
-	SH_PFC_PIN_GROUP(scifa0_data),
-	SH_PFC_PIN_GROUP(scifa0_clk),
-	SH_PFC_PIN_GROUP(scifa0_ctrl),
-	SH_PFC_PIN_GROUP(scifa0_data_b),
-	SH_PFC_PIN_GROUP(scifa0_clk_b),
-	SH_PFC_PIN_GROUP(scifa0_ctrl_b),
-	SH_PFC_PIN_GROUP(scifa1_data),
-	SH_PFC_PIN_GROUP(scifa1_clk),
-	SH_PFC_PIN_GROUP(scifa1_ctrl),
-	SH_PFC_PIN_GROUP(scifa1_data_b),
-	SH_PFC_PIN_GROUP(scifa1_clk_b),
-	SH_PFC_PIN_GROUP(scifa1_ctrl_b),
-	SH_PFC_PIN_GROUP(scifa1_data_c),
-	SH_PFC_PIN_GROUP(scifa1_clk_c),
-	SH_PFC_PIN_GROUP(scifa1_ctrl_c),
-	SH_PFC_PIN_GROUP(scifa1_data_d),
-	SH_PFC_PIN_GROUP(scifa1_clk_d),
-	SH_PFC_PIN_GROUP(scifa1_ctrl_d),
-	SH_PFC_PIN_GROUP(scifa2_data),
-	SH_PFC_PIN_GROUP(scifa2_clk),
-	SH_PFC_PIN_GROUP(scifa2_ctrl),
-	SH_PFC_PIN_GROUP(scifa2_data_b),
-	SH_PFC_PIN_GROUP(scifa2_data_c),
-	SH_PFC_PIN_GROUP(scifa2_clk_c),
-	SH_PFC_PIN_GROUP(scifb0_data),
-	SH_PFC_PIN_GROUP(scifb0_clk),
-	SH_PFC_PIN_GROUP(scifb0_ctrl),
-	SH_PFC_PIN_GROUP(scifb0_data_b),
-	SH_PFC_PIN_GROUP(scifb0_clk_b),
-	SH_PFC_PIN_GROUP(scifb0_ctrl_b),
-	SH_PFC_PIN_GROUP(scifb0_data_c),
-	SH_PFC_PIN_GROUP(scifb1_data),
-	SH_PFC_PIN_GROUP(scifb1_clk),
-	SH_PFC_PIN_GROUP(scifb1_ctrl),
-	SH_PFC_PIN_GROUP(scifb1_data_b),
-	SH_PFC_PIN_GROUP(scifb1_clk_b),
-	SH_PFC_PIN_GROUP(scifb1_ctrl_b),
-	SH_PFC_PIN_GROUP(scifb1_data_c),
-	SH_PFC_PIN_GROUP(scifb1_data_d),
-	SH_PFC_PIN_GROUP(scifb1_data_e),
-	SH_PFC_PIN_GROUP(scifb1_clk_e),
-	SH_PFC_PIN_GROUP(scifb1_data_f),
-	SH_PFC_PIN_GROUP(scifb1_data_g),
-	SH_PFC_PIN_GROUP(scifb1_clk_g),
-	SH_PFC_PIN_GROUP(scifb2_data),
-	SH_PFC_PIN_GROUP(scifb2_clk),
-	SH_PFC_PIN_GROUP(scifb2_ctrl),
-	SH_PFC_PIN_GROUP(scifb2_data_b),
-	SH_PFC_PIN_GROUP(scifb2_clk_b),
-	SH_PFC_PIN_GROUP(scifb2_ctrl_b),
-	SH_PFC_PIN_GROUP(scifb2_data_c),
-	SH_PFC_PIN_GROUP(scif_clk),
-	SH_PFC_PIN_GROUP(scif_clk_b),
-	SH_PFC_PIN_GROUP(sdhi0_data1),
-	SH_PFC_PIN_GROUP(sdhi0_data4),
-	SH_PFC_PIN_GROUP(sdhi0_ctrl),
-	SH_PFC_PIN_GROUP(sdhi0_cd),
-	SH_PFC_PIN_GROUP(sdhi0_wp),
-	SH_PFC_PIN_GROUP(sdhi1_data1),
-	SH_PFC_PIN_GROUP(sdhi1_data4),
-	SH_PFC_PIN_GROUP(sdhi1_ctrl),
-	SH_PFC_PIN_GROUP(sdhi1_cd),
-	SH_PFC_PIN_GROUP(sdhi1_wp),
-	SH_PFC_PIN_GROUP(sdhi2_data1),
-	SH_PFC_PIN_GROUP(sdhi2_data4),
-	SH_PFC_PIN_GROUP(sdhi2_ctrl),
-	SH_PFC_PIN_GROUP(sdhi2_cd),
-	SH_PFC_PIN_GROUP(sdhi2_wp),
-	SH_PFC_PIN_GROUP(sdhi3_data1),
-	SH_PFC_PIN_GROUP(sdhi3_data4),
-	SH_PFC_PIN_GROUP(sdhi3_ctrl),
-	SH_PFC_PIN_GROUP(sdhi3_cd),
-	SH_PFC_PIN_GROUP(sdhi3_wp),
-	SH_PFC_PIN_GROUP(ssi0_data),
-	SH_PFC_PIN_GROUP(ssi0129_ctrl),
-	SH_PFC_PIN_GROUP(ssi1_data),
-	SH_PFC_PIN_GROUP(ssi1_ctrl),
-	SH_PFC_PIN_GROUP(ssi2_data),
-	SH_PFC_PIN_GROUP(ssi2_ctrl),
-	SH_PFC_PIN_GROUP(ssi3_data),
-	SH_PFC_PIN_GROUP(ssi34_ctrl),
-	SH_PFC_PIN_GROUP(ssi4_data),
-	SH_PFC_PIN_GROUP(ssi4_ctrl),
-	SH_PFC_PIN_GROUP(ssi5),
-	SH_PFC_PIN_GROUP(ssi5_b),
-	SH_PFC_PIN_GROUP(ssi5_c),
-	SH_PFC_PIN_GROUP(ssi6),
-	SH_PFC_PIN_GROUP(ssi6_b),
-	SH_PFC_PIN_GROUP(ssi7_data),
-	SH_PFC_PIN_GROUP(ssi7_b_data),
-	SH_PFC_PIN_GROUP(ssi7_c_data),
-	SH_PFC_PIN_GROUP(ssi78_ctrl),
-	SH_PFC_PIN_GROUP(ssi78_b_ctrl),
-	SH_PFC_PIN_GROUP(ssi78_c_ctrl),
-	SH_PFC_PIN_GROUP(ssi8_data),
-	SH_PFC_PIN_GROUP(ssi8_b_data),
-	SH_PFC_PIN_GROUP(ssi8_c_data),
-	SH_PFC_PIN_GROUP(ssi9_data),
-	SH_PFC_PIN_GROUP(ssi9_ctrl),
-	SH_PFC_PIN_GROUP(tpu0_to0),
-	SH_PFC_PIN_GROUP(tpu0_to1),
-	SH_PFC_PIN_GROUP(tpu0_to2),
-	SH_PFC_PIN_GROUP(tpu0_to3),
-	SH_PFC_PIN_GROUP(usb0),
-	SH_PFC_PIN_GROUP(usb0_ovc_vbus),
-	SH_PFC_PIN_GROUP(usb1),
-	SH_PFC_PIN_GROUP(usb2),
-	VIN_DATA_PIN_GROUP(vin0_data, 24),
-	VIN_DATA_PIN_GROUP(vin0_data, 20),
-	SH_PFC_PIN_GROUP(vin0_data18),
-	VIN_DATA_PIN_GROUP(vin0_data, 16),
-	VIN_DATA_PIN_GROUP(vin0_data, 12),
-	VIN_DATA_PIN_GROUP(vin0_data, 10),
-	VIN_DATA_PIN_GROUP(vin0_data, 8),
-	VIN_DATA_PIN_GROUP(vin0_data, 4),
-	SH_PFC_PIN_GROUP(vin0_sync),
-	SH_PFC_PIN_GROUP(vin0_field),
-	SH_PFC_PIN_GROUP(vin0_clkenb),
-	SH_PFC_PIN_GROUP(vin0_clk),
-	VIN_DATA_PIN_GROUP(vin1_data, 24),
-	VIN_DATA_PIN_GROUP(vin1_data, 20),
-	SH_PFC_PIN_GROUP(vin1_data18),
-	VIN_DATA_PIN_GROUP(vin1_data, 16),
-	VIN_DATA_PIN_GROUP(vin1_data, 12),
-	VIN_DATA_PIN_GROUP(vin1_data, 10),
-	VIN_DATA_PIN_GROUP(vin1_data, 8),
-	VIN_DATA_PIN_GROUP(vin1_data, 4),
-	SH_PFC_PIN_GROUP(vin1_sync),
-	SH_PFC_PIN_GROUP(vin1_field),
-	SH_PFC_PIN_GROUP(vin1_clkenb),
-	SH_PFC_PIN_GROUP(vin1_clk),
-	VIN_DATA_PIN_GROUP(vin2_data, 24),
-	SH_PFC_PIN_GROUP(vin2_data18),
-	VIN_DATA_PIN_GROUP(vin2_data, 16),
-	VIN_DATA_PIN_GROUP(vin2_data, 8),
-	VIN_DATA_PIN_GROUP(vin2_data, 4),
-	SH_PFC_PIN_GROUP(vin2_sync),
-	SH_PFC_PIN_GROUP(vin2_field),
-	SH_PFC_PIN_GROUP(vin2_clkenb),
-	SH_PFC_PIN_GROUP(vin2_clk),
-	SH_PFC_PIN_GROUP(vin3_data8),
-	SH_PFC_PIN_GROUP(vin3_sync),
-	SH_PFC_PIN_GROUP(vin3_field),
-	SH_PFC_PIN_GROUP(vin3_clkenb),
-	SH_PFC_PIN_GROUP(vin3_clk),
-};
-
-static const char * const audio_clk_groups[] = {
-	"audio_clk_a",
-	"audio_clk_b",
-	"audio_clk_c",
-	"audio_clkout",
-	"audio_clkout_b",
-	"audio_clkout_c",
-	"audio_clkout_d",
-};
-
-static const char * const avb_groups[] = {
-	"avb_link",
-	"avb_magic",
-	"avb_phy_int",
-	"avb_mdio",
-	"avb_mii",
-	"avb_gmii",
-};
-
-static const char * const du_groups[] = {
-	"du_rgb666",
-	"du_rgb888",
-	"du_clk_out_0",
-	"du_clk_out_1",
-	"du_sync_0",
-	"du_sync_1",
-	"du_cde",
-};
-
-static const char * const du0_groups[] = {
-	"du0_clk_in",
-};
-
-static const char * const du1_groups[] = {
-	"du1_clk_in",
-};
-
-static const char * const du2_groups[] = {
-	"du2_clk_in",
-};
-
-static const char * const eth_groups[] = {
-	"eth_link",
-	"eth_magic",
-	"eth_mdio",
-	"eth_rmii",
-};
-
-static const char * const hscif0_groups[] = {
-	"hscif0_data",
-	"hscif0_clk",
-	"hscif0_ctrl",
-	"hscif0_data_b",
-	"hscif0_ctrl_b",
-	"hscif0_data_c",
-	"hscif0_ctrl_c",
-	"hscif0_data_d",
-	"hscif0_ctrl_d",
-	"hscif0_data_e",
-	"hscif0_ctrl_e",
-	"hscif0_data_f",
-	"hscif0_ctrl_f",
-};
-
-static const char * const hscif1_groups[] = {
-	"hscif1_data",
-	"hscif1_clk",
-	"hscif1_ctrl",
-	"hscif1_data_b",
-	"hscif1_clk_b",
-	"hscif1_ctrl_b",
-};
-
-static const char * const i2c0_groups[] = {
-	"i2c0",
-};
-
-static const char * const i2c1_groups[] = {
-	"i2c1",
-	"i2c1_b",
-	"i2c1_c",
-};
-
-static const char * const i2c2_groups[] = {
-	"i2c2",
-	"i2c2_b",
-	"i2c2_c",
-	"i2c2_d",
-	"i2c2_e",
-};
-
-static const char * const i2c3_groups[] = {
-	"i2c3",
-};
-
-static const char * const iic0_groups[] = {
-	"iic0",
-};
-
-static const char * const iic1_groups[] = {
-	"iic1",
-	"iic1_b",
-	"iic1_c",
-};
-
-static const char * const iic2_groups[] = {
-	"iic2",
-	"iic2_b",
-	"iic2_c",
-	"iic2_d",
-	"iic2_e",
-};
-
-static const char * const iic3_groups[] = {
-	"iic3",
-};
-
-static const char * const intc_groups[] = {
-	"intc_irq0",
-	"intc_irq1",
-	"intc_irq2",
-	"intc_irq3",
-};
-
-static const char * const mlb_groups[] = {
-	"mlb_3pin",
-};
-
-static const char * const mmc0_groups[] = {
-	"mmc0_data1",
-	"mmc0_data4",
-	"mmc0_data8",
-	"mmc0_ctrl",
-};
-
-static const char * const mmc1_groups[] = {
-	"mmc1_data1",
-	"mmc1_data4",
-	"mmc1_data8",
-	"mmc1_ctrl",
-};
-
-static const char * const msiof0_groups[] = {
-	"msiof0_clk",
-	"msiof0_sync",
-	"msiof0_ss1",
-	"msiof0_ss2",
-	"msiof0_rx",
-	"msiof0_tx",
-	"msiof0_clk_b",
-	"msiof0_ss1_b",
-	"msiof0_ss2_b",
-	"msiof0_rx_b",
-	"msiof0_tx_b",
-};
-
-static const char * const msiof1_groups[] = {
-	"msiof1_clk",
-	"msiof1_sync",
-	"msiof1_ss1",
-	"msiof1_ss2",
-	"msiof1_rx",
-	"msiof1_tx",
-	"msiof1_clk_b",
-	"msiof1_ss1_b",
-	"msiof1_ss2_b",
-	"msiof1_rx_b",
-	"msiof1_tx_b",
-};
-
-static const char * const msiof2_groups[] = {
-	"msiof2_clk",
-	"msiof2_sync",
-	"msiof2_ss1",
-	"msiof2_ss2",
-	"msiof2_rx",
-	"msiof2_tx",
-};
-
-static const char * const msiof3_groups[] = {
-	"msiof3_clk",
-	"msiof3_sync",
-	"msiof3_ss1",
-	"msiof3_ss2",
-	"msiof3_rx",
-	"msiof3_tx",
-	"msiof3_clk_b",
-	"msiof3_sync_b",
-	"msiof3_rx_b",
-	"msiof3_tx_b",
-};
-
-static const char * const pwm0_groups[] = {
-	"pwm0",
-	"pwm0_b",
-};
-
-static const char * const pwm1_groups[] = {
-	"pwm1",
-	"pwm1_b",
-};
-
-static const char * const pwm2_groups[] = {
-	"pwm2",
-};
-
-static const char * const pwm3_groups[] = {
-	"pwm3",
-};
-
-static const char * const pwm4_groups[] = {
-	"pwm4",
-};
-
-static const char * const pwm5_groups[] = {
-	"pwm5",
-};
-
-static const char * const pwm6_groups[] = {
-	"pwm6",
-};
-
-static const char * const qspi_groups[] = {
-	"qspi_ctrl",
-	"qspi_data2",
-	"qspi_data4",
-};
-
-static const char * const scif0_groups[] = {
-	"scif0_data",
-	"scif0_clk",
-	"scif0_ctrl",
-	"scif0_data_b",
-};
-
-static const char * const scif1_groups[] = {
-	"scif1_data",
-	"scif1_clk",
-	"scif1_ctrl",
-	"scif1_data_b",
-	"scif1_data_c",
-	"scif1_data_d",
-	"scif1_clk_d",
-	"scif1_data_e",
-	"scif1_clk_e",
-};
-
-static const char * const scif2_groups[] = {
-	"scif2_data",
-	"scif2_clk",
-	"scif2_data_b",
-};
-
-static const char * const scifa0_groups[] = {
-	"scifa0_data",
-	"scifa0_clk",
-	"scifa0_ctrl",
-	"scifa0_data_b",
-	"scifa0_clk_b",
-	"scifa0_ctrl_b",
-};
-
-static const char * const scifa1_groups[] = {
-	"scifa1_data",
-	"scifa1_clk",
-	"scifa1_ctrl",
-	"scifa1_data_b",
-	"scifa1_clk_b",
-	"scifa1_ctrl_b",
-	"scifa1_data_c",
-	"scifa1_clk_c",
-	"scifa1_ctrl_c",
-	"scifa1_data_d",
-	"scifa1_clk_d",
-	"scifa1_ctrl_d",
-};
-
-static const char * const scifa2_groups[] = {
-	"scifa2_data",
-	"scifa2_clk",
-	"scifa2_ctrl",
-	"scifa2_data_b",
-	"scifa2_data_c",
-	"scifa2_clk_c",
-};
-
-static const char * const scifb0_groups[] = {
-	"scifb0_data",
-	"scifb0_clk",
-	"scifb0_ctrl",
-	"scifb0_data_b",
-	"scifb0_clk_b",
-	"scifb0_ctrl_b",
-	"scifb0_data_c",
-};
-
-static const char * const scifb1_groups[] = {
-	"scifb1_data",
-	"scifb1_clk",
-	"scifb1_ctrl",
-	"scifb1_data_b",
-	"scifb1_clk_b",
-	"scifb1_ctrl_b",
-	"scifb1_data_c",
-	"scifb1_data_d",
-	"scifb1_data_e",
-	"scifb1_clk_e",
-	"scifb1_data_f",
-	"scifb1_data_g",
-	"scifb1_clk_g",
-};
-
-static const char * const scifb2_groups[] = {
-	"scifb2_data",
-	"scifb2_clk",
-	"scifb2_ctrl",
-	"scifb2_data_b",
-	"scifb2_clk_b",
-	"scifb2_ctrl_b",
-	"scifb2_data_c",
-};
-
-static const char * const scif_clk_groups[] = {
-	"scif_clk",
-	"scif_clk_b",
-};
-
-static const char * const sdhi0_groups[] = {
-	"sdhi0_data1",
-	"sdhi0_data4",
-	"sdhi0_ctrl",
-	"sdhi0_cd",
-	"sdhi0_wp",
-};
-
-static const char * const sdhi1_groups[] = {
-	"sdhi1_data1",
-	"sdhi1_data4",
-	"sdhi1_ctrl",
-	"sdhi1_cd",
-	"sdhi1_wp",
-};
-
-static const char * const sdhi2_groups[] = {
-	"sdhi2_data1",
-	"sdhi2_data4",
-	"sdhi2_ctrl",
-	"sdhi2_cd",
-	"sdhi2_wp",
-};
-
-static const char * const sdhi3_groups[] = {
-	"sdhi3_data1",
-	"sdhi3_data4",
-	"sdhi3_ctrl",
-	"sdhi3_cd",
-	"sdhi3_wp",
-};
-
-static const char * const ssi_groups[] = {
-	"ssi0_data",
-	"ssi0129_ctrl",
-	"ssi1_data",
-	"ssi1_ctrl",
-	"ssi2_data",
-	"ssi2_ctrl",
-	"ssi3_data",
-	"ssi34_ctrl",
-	"ssi4_data",
-	"ssi4_ctrl",
-	"ssi5",
-	"ssi5_b",
-	"ssi5_c",
-	"ssi6",
-	"ssi6_b",
-	"ssi7_data",
-	"ssi7_b_data",
-	"ssi7_c_data",
-	"ssi78_ctrl",
-	"ssi78_b_ctrl",
-	"ssi78_c_ctrl",
-	"ssi8_data",
-	"ssi8_b_data",
-	"ssi8_c_data",
-	"ssi9_data",
-	"ssi9_ctrl",
-};
-
-static const char * const tpu0_groups[] = {
-	"tpu0_to0",
-	"tpu0_to1",
-	"tpu0_to2",
-	"tpu0_to3",
-};
-
-static const char * const usb0_groups[] = {
-	"usb0",
-	"usb0_ovc_vbus",
-};
-
-static const char * const usb1_groups[] = {
-	"usb1",
-};
-
-static const char * const usb2_groups[] = {
-	"usb2",
-};
-
-static const char * const vin0_groups[] = {
-	"vin0_data24",
-	"vin0_data20",
-	"vin0_data18",
-	"vin0_data16",
-	"vin0_data12",
-	"vin0_data10",
-	"vin0_data8",
-	"vin0_data4",
-	"vin0_sync",
-	"vin0_field",
-	"vin0_clkenb",
-	"vin0_clk",
-};
-
-static const char * const vin1_groups[] = {
-	"vin1_data24",
-	"vin1_data20",
-	"vin1_data18",
-	"vin1_data16",
-	"vin1_data12",
-	"vin1_data10",
-	"vin1_data8",
-	"vin1_data4",
-	"vin1_sync",
-	"vin1_field",
-	"vin1_clkenb",
-	"vin1_clk",
-};
-
-static const char * const vin2_groups[] = {
-	"vin2_data24",
-	"vin2_data18",
-	"vin2_data16",
-	"vin2_data8",
-	"vin2_data4",
-	"vin2_sync",
-	"vin2_field",
-	"vin2_clkenb",
-	"vin2_clk",
-};
-
-static const char * const vin3_groups[] = {
-	"vin3_data8",
-	"vin3_sync",
-	"vin3_field",
-	"vin3_clkenb",
-	"vin3_clk",
-};
-
-static const struct sh_pfc_function pinmux_functions[] = {
-	SH_PFC_FUNCTION(audio_clk),
-	SH_PFC_FUNCTION(avb),
-	SH_PFC_FUNCTION(du),
-	SH_PFC_FUNCTION(du0),
-	SH_PFC_FUNCTION(du1),
-	SH_PFC_FUNCTION(du2),
-	SH_PFC_FUNCTION(eth),
-	SH_PFC_FUNCTION(hscif0),
-	SH_PFC_FUNCTION(hscif1),
-	SH_PFC_FUNCTION(i2c0),
-	SH_PFC_FUNCTION(i2c1),
-	SH_PFC_FUNCTION(i2c2),
-	SH_PFC_FUNCTION(i2c3),
-	SH_PFC_FUNCTION(iic0),
-	SH_PFC_FUNCTION(iic1),
-	SH_PFC_FUNCTION(iic2),
-	SH_PFC_FUNCTION(iic3),
-	SH_PFC_FUNCTION(intc),
-	SH_PFC_FUNCTION(mlb),
-	SH_PFC_FUNCTION(mmc0),
-	SH_PFC_FUNCTION(mmc1),
-	SH_PFC_FUNCTION(msiof0),
-	SH_PFC_FUNCTION(msiof1),
-	SH_PFC_FUNCTION(msiof2),
-	SH_PFC_FUNCTION(msiof3),
-	SH_PFC_FUNCTION(pwm0),
-	SH_PFC_FUNCTION(pwm1),
-	SH_PFC_FUNCTION(pwm2),
-	SH_PFC_FUNCTION(pwm3),
-	SH_PFC_FUNCTION(pwm4),
-	SH_PFC_FUNCTION(pwm5),
-	SH_PFC_FUNCTION(pwm6),
-	SH_PFC_FUNCTION(qspi),
-	SH_PFC_FUNCTION(scif0),
-	SH_PFC_FUNCTION(scif1),
-	SH_PFC_FUNCTION(scif2),
-	SH_PFC_FUNCTION(scifa0),
-	SH_PFC_FUNCTION(scifa1),
-	SH_PFC_FUNCTION(scifa2),
-	SH_PFC_FUNCTION(scifb0),
-	SH_PFC_FUNCTION(scifb1),
-	SH_PFC_FUNCTION(scifb2),
-	SH_PFC_FUNCTION(scif_clk),
-	SH_PFC_FUNCTION(sdhi0),
-	SH_PFC_FUNCTION(sdhi1),
-	SH_PFC_FUNCTION(sdhi2),
-	SH_PFC_FUNCTION(sdhi3),
-	SH_PFC_FUNCTION(ssi),
-	SH_PFC_FUNCTION(tpu0),
-	SH_PFC_FUNCTION(usb0),
-	SH_PFC_FUNCTION(usb1),
-	SH_PFC_FUNCTION(usb2),
-	SH_PFC_FUNCTION(vin0),
-	SH_PFC_FUNCTION(vin1),
-	SH_PFC_FUNCTION(vin2),
-	SH_PFC_FUNCTION(vin3),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
-		GP_0_31_FN, FN_IP3_17_15,
-		GP_0_30_FN, FN_IP3_14_12,
-		GP_0_29_FN, FN_IP3_11_8,
-		GP_0_28_FN, FN_IP3_7_4,
-		GP_0_27_FN, FN_IP3_3_0,
-		GP_0_26_FN, FN_IP2_28_26,
-		GP_0_25_FN, FN_IP2_25_22,
-		GP_0_24_FN, FN_IP2_21_18,
-		GP_0_23_FN, FN_IP2_17_15,
-		GP_0_22_FN, FN_IP2_14_12,
-		GP_0_21_FN, FN_IP2_11_9,
-		GP_0_20_FN, FN_IP2_8_6,
-		GP_0_19_FN, FN_IP2_5_3,
-		GP_0_18_FN, FN_IP2_2_0,
-		GP_0_17_FN, FN_IP1_29_28,
-		GP_0_16_FN, FN_IP1_27_26,
-		GP_0_15_FN, FN_IP1_25_22,
-		GP_0_14_FN, FN_IP1_21_18,
-		GP_0_13_FN, FN_IP1_17_15,
-		GP_0_12_FN, FN_IP1_14_12,
-		GP_0_11_FN, FN_IP1_11_8,
-		GP_0_10_FN, FN_IP1_7_4,
-		GP_0_9_FN, FN_IP1_3_0,
-		GP_0_8_FN, FN_IP0_30_27,
-		GP_0_7_FN, FN_IP0_26_23,
-		GP_0_6_FN, FN_IP0_22_20,
-		GP_0_5_FN, FN_IP0_19_16,
-		GP_0_4_FN, FN_IP0_15_12,
-		GP_0_3_FN, FN_IP0_11_9,
-		GP_0_2_FN, FN_IP0_8_6,
-		GP_0_1_FN, FN_IP0_5_3,
-		GP_0_0_FN, FN_IP0_2_0 ))
-	},
-	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		GP_1_29_FN, FN_IP6_13_11,
-		GP_1_28_FN, FN_IP6_10_9,
-		GP_1_27_FN, FN_IP6_8_6,
-		GP_1_26_FN, FN_IP6_5_3,
-		GP_1_25_FN, FN_IP6_2_0,
-		GP_1_24_FN, FN_IP5_29_27,
-		GP_1_23_FN, FN_IP5_26_24,
-		GP_1_22_FN, FN_IP5_23_21,
-		GP_1_21_FN, FN_IP5_20_18,
-		GP_1_20_FN, FN_IP5_17_15,
-		GP_1_19_FN, FN_IP5_14_13,
-		GP_1_18_FN, FN_IP5_12_10,
-		GP_1_17_FN, FN_IP5_9_6,
-		GP_1_16_FN, FN_IP5_5_3,
-		GP_1_15_FN, FN_IP5_2_0,
-		GP_1_14_FN, FN_IP4_29_27,
-		GP_1_13_FN, FN_IP4_26_24,
-		GP_1_12_FN, FN_IP4_23_21,
-		GP_1_11_FN, FN_IP4_20_18,
-		GP_1_10_FN, FN_IP4_17_15,
-		GP_1_9_FN, FN_IP4_14_12,
-		GP_1_8_FN, FN_IP4_11_9,
-		GP_1_7_FN, FN_IP4_8_6,
-		GP_1_6_FN, FN_IP4_5_3,
-		GP_1_5_FN, FN_IP4_2_0,
-		GP_1_4_FN, FN_IP3_31_29,
-		GP_1_3_FN, FN_IP3_28_26,
-		GP_1_2_FN, FN_IP3_25_23,
-		GP_1_1_FN, FN_IP3_22_20,
-		GP_1_0_FN, FN_IP3_19_18, ))
-	},
-	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		GP_2_29_FN, FN_IP7_15_13,
-		GP_2_28_FN, FN_IP7_12_10,
-		GP_2_27_FN, FN_IP7_9_8,
-		GP_2_26_FN, FN_IP7_7_6,
-		GP_2_25_FN, FN_IP7_5_3,
-		GP_2_24_FN, FN_IP7_2_0,
-		GP_2_23_FN, FN_IP6_31_29,
-		GP_2_22_FN, FN_IP6_28_26,
-		GP_2_21_FN, FN_IP6_25_23,
-		GP_2_20_FN, FN_IP6_22_20,
-		GP_2_19_FN, FN_IP6_19_17,
-		GP_2_18_FN, FN_IP6_16_14,
-		GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
-		GP_2_16_FN, FN_IP8_27,
-		GP_2_15_FN, FN_IP8_26,
-		GP_2_14_FN, FN_IP8_25_24,
-		GP_2_13_FN, FN_IP8_23_22,
-		GP_2_12_FN, FN_IP8_21_20,
-		GP_2_11_FN, FN_IP8_19_18,
-		GP_2_10_FN, FN_IP8_17_16,
-		GP_2_9_FN, FN_IP8_15_14,
-		GP_2_8_FN, FN_IP8_13_12,
-		GP_2_7_FN, FN_IP8_11_10,
-		GP_2_6_FN, FN_IP8_9_8,
-		GP_2_5_FN, FN_IP8_7_6,
-		GP_2_4_FN, FN_IP8_5_4,
-		GP_2_3_FN, FN_IP8_3_2,
-		GP_2_2_FN, FN_IP8_1_0,
-		GP_2_1_FN, FN_IP7_30_29,
-		GP_2_0_FN, FN_IP7_28_27 ))
-	},
-	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
-		GP_3_31_FN, FN_IP11_21_18,
-		GP_3_30_FN, FN_IP11_17_15,
-		GP_3_29_FN, FN_IP11_14_13,
-		GP_3_28_FN, FN_IP11_12_11,
-		GP_3_27_FN, FN_IP11_10_9,
-		GP_3_26_FN, FN_IP11_8_7,
-		GP_3_25_FN, FN_IP11_6_5,
-		GP_3_24_FN, FN_IP11_4,
-		GP_3_23_FN, FN_IP11_3_0,
-		GP_3_22_FN, FN_IP10_29_26,
-		GP_3_21_FN, FN_IP10_25_23,
-		GP_3_20_FN, FN_IP10_22_19,
-		GP_3_19_FN, FN_IP10_18_15,
-		GP_3_18_FN, FN_IP10_14_11,
-		GP_3_17_FN, FN_IP10_10_7,
-		GP_3_16_FN, FN_IP10_6_4,
-		GP_3_15_FN, FN_IP10_3_0,
-		GP_3_14_FN, FN_IP9_31_28,
-		GP_3_13_FN, FN_IP9_27_26,
-		GP_3_12_FN, FN_IP9_25_24,
-		GP_3_11_FN, FN_IP9_23_22,
-		GP_3_10_FN, FN_IP9_21_20,
-		GP_3_9_FN, FN_IP9_19_18,
-		GP_3_8_FN, FN_IP9_17_16,
-		GP_3_7_FN, FN_IP9_15_12,
-		GP_3_6_FN, FN_IP9_11_8,
-		GP_3_5_FN, FN_IP9_7_6,
-		GP_3_4_FN, FN_IP9_5_4,
-		GP_3_3_FN, FN_IP9_3_2,
-		GP_3_2_FN, FN_IP9_1_0,
-		GP_3_1_FN, FN_IP8_30_29,
-		GP_3_0_FN, FN_IP8_28 ))
-	},
-	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
-		GP_4_31_FN, FN_IP14_18_16,
-		GP_4_30_FN, FN_IP14_15_12,
-		GP_4_29_FN, FN_IP14_11_9,
-		GP_4_28_FN, FN_IP14_8_6,
-		GP_4_27_FN, FN_IP14_5_3,
-		GP_4_26_FN, FN_IP14_2_0,
-		GP_4_25_FN, FN_IP13_30_29,
-		GP_4_24_FN, FN_IP13_28_26,
-		GP_4_23_FN, FN_IP13_25_23,
-		GP_4_22_FN, FN_IP13_22_19,
-		GP_4_21_FN, FN_IP13_18_16,
-		GP_4_20_FN, FN_IP13_15_13,
-		GP_4_19_FN, FN_IP13_12_10,
-		GP_4_18_FN, FN_IP13_9_7,
-		GP_4_17_FN, FN_IP13_6_3,
-		GP_4_16_FN, FN_IP13_2_0,
-		GP_4_15_FN, FN_IP12_30_28,
-		GP_4_14_FN, FN_IP12_27_25,
-		GP_4_13_FN, FN_IP12_24_23,
-		GP_4_12_FN, FN_IP12_22_20,
-		GP_4_11_FN, FN_IP12_19_17,
-		GP_4_10_FN, FN_IP12_16_14,
-		GP_4_9_FN, FN_IP12_13_11,
-		GP_4_8_FN, FN_IP12_10_8,
-		GP_4_7_FN, FN_IP12_7_6,
-		GP_4_6_FN, FN_IP12_5_4,
-		GP_4_5_FN, FN_IP12_3_2,
-		GP_4_4_FN, FN_IP12_1_0,
-		GP_4_3_FN, FN_IP11_31_30,
-		GP_4_2_FN, FN_IP11_29_27,
-		GP_4_1_FN, FN_IP11_26_24,
-		GP_4_0_FN, FN_IP11_23_22 ))
-	},
-	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
-		GP_5_31_FN, FN_IP7_24_22,
-		GP_5_30_FN, FN_IP7_21_19,
-		GP_5_29_FN, FN_IP7_18_16,
-		GP_5_28_FN, FN_DU_DOTCLKIN2,
-		GP_5_27_FN, FN_IP7_26_25,
-		GP_5_26_FN, FN_DU_DOTCLKIN0,
-		GP_5_25_FN, FN_AVS2,
-		GP_5_24_FN, FN_AVS1,
-		GP_5_23_FN, FN_USB2_OVC,
-		GP_5_22_FN, FN_USB2_PWEN,
-		GP_5_21_FN, FN_IP16_7,
-		GP_5_20_FN, FN_IP16_6,
-		GP_5_19_FN, FN_USB0_OVC_VBUS,
-		GP_5_18_FN, FN_USB0_PWEN,
-		GP_5_17_FN, FN_IP16_5_3,
-		GP_5_16_FN, FN_IP16_2_0,
-		GP_5_15_FN, FN_IP15_29_28,
-		GP_5_14_FN, FN_IP15_27_26,
-		GP_5_13_FN, FN_IP15_25_23,
-		GP_5_12_FN, FN_IP15_22_20,
-		GP_5_11_FN, FN_IP15_19_18,
-		GP_5_10_FN, FN_IP15_17_16,
-		GP_5_9_FN, FN_IP15_15_14,
-		GP_5_8_FN, FN_IP15_13_12,
-		GP_5_7_FN, FN_IP15_11_9,
-		GP_5_6_FN, FN_IP15_8_6,
-		GP_5_5_FN, FN_IP15_5_3,
-		GP_5_4_FN, FN_IP15_2_0,
-		GP_5_3_FN, FN_IP14_30_28,
-		GP_5_2_FN, FN_IP14_27_25,
-		GP_5_1_FN, FN_IP14_24_22,
-		GP_5_0_FN, FN_IP14_21_19 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
-			     GROUP(1, 4, 4, 3, 4, 4, 3, 3, 3, 3),
-			     GROUP(
-		/* IP0_31 [1] */
-		0, 0,
-		/* IP0_30_27 [4] */
-		FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
-		FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP0_26_23 [4] */
-		FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
-		FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
-		FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP0_22_20 [3] */
-		FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
-		FN_I2C2_SCL_C, 0, 0,
-		/* IP0_19_16 [4] */
-		FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
-		FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
-		0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP0_15_12 [4] */
-		FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
-		FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
-		0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP0_11_9 [3] */
-		FN_D3, FN_MSIOF3_TXD_B,	FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
-		0, 0, 0,
-		/* IP0_8_6 [3] */
-		FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
-		0, 0, 0,
-		/* IP0_5_3 [3] */
-		FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
-		0, 0, 0,
-		/* IP0_2_0 [3] */
-		FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
-		0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
-			     GROUP(2, 2, 2, 4, 4, 3, 3, 4, 4, 4),
-			     GROUP(
-		/* IP1_31_30 [2] */
-		0, 0, 0, 0,
-		/* IP1_29_28 [2] */
-		FN_A1, FN_PWM4, 0, 0,
-		/* IP1_27_26 [2] */
-		FN_A0, FN_PWM3, 0, 0,
-		/* IP1_25_22 [4] */
-		FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
-		FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
-		0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP1_21_18 [4] */
-		FN_D14,	FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
-		FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
-		0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP1_17_15 [3] */
-		FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
-		FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
-		0, 0, 0,
-		/* IP1_14_12 [3] */
-		FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
-		FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
-		0, 0,
-		/* IP1_11_8 [4] */
-		FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
-		FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
-		0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP1_7_4 [4] */
-		FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
-		FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
-		0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP1_3_0 [4] */
-		FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
-		FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
-			     GROUP(3, 3, 4, 4, 3, 3, 3, 3, 3, 3),
-			     GROUP(
-		/* IP2_31_29 [3] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP2_28_26 [3] */
-		FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
-		FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
-		/* IP2_25_22 [4] */
-		FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
-		FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP2_21_18 [4] */
-		FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
-		FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP2_17_15 [3] */
-		FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
-		0, 0, 0, 0,
-		/* IP2_14_12 [3] */
-		FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
-		/* IP2_11_9 [3] */
-		FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
-		/* IP2_8_6 [3] */
-		FN_A4, FN_MSIOF1_TXD_B,	FN_TPU0TO0, 0, 0, 0, 0, 0,
-		/* IP2_5_3 [3] */
-		FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
-		/* IP2_2_0 [3] */
-		FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0,	))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
-			     GROUP(3, 3, 3, 3, 2, 3, 3, 4, 4, 4),
-			     GROUP(
-		/* IP3_31_29 [3] */
-		FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
-		0, 0, 0,
-		/* IP3_28_26 [3] */
-		FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
-		0, 0, 0, 0,
-		/* IP3_25_23 [3] */
-		FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
-		/* IP3_22_20 [3] */
-		FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
-		/* IP3_19_18 [2] */
-		FN_A16, FN_ATAWR1_N, 0, 0,
-		/* IP3_17_15 [3] */
-		FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
-		0, 0, 0, 0,
-		/* IP3_14_12 [3] */
-		FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
-		0, 0, 0, 0,
-		/* IP3_11_8 [4] */
-		FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
-		FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
-		FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP3_7_4 [4] */
-		FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
-		FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
-		0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP3_3_0 [4] */
-		FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
-		FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
-			     GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
-			     GROUP(
-		/* IP4_31_30 [2] */
-		0, 0, 0, 0,
-		/* IP4_29_27 [3] */
-		FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
-		FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
-		/* IP4_26_24 [3] */
-		FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
-		FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
-		/* IP4_23_21 [3] */
-		FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
-		FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
-		/* IP4_20_18 [3] */
-		FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
-		FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
-		/* IP4_17_15 [3] */
-		FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
-		0, 0, 0,
-		/* IP4_14_12 [3] */
-		FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
-		FN_VI2_FIELD_B, 0, 0,
-		/* IP4_11_9 [3] */
-		FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
-		FN_VI2_CLKENB_B, 0, 0,
-		/* IP4_8_6 [3] */
-		FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
-		/* IP4_5_3 [3] */
-		FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
-		/* IP4_2_0 [3] */
-		FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
-		))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
-			     GROUP(2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3),
-			     GROUP(
-		/* IP5_31_30 [2] */
-		0, 0, 0, 0,
-		/* IP5_29_27 [3] */
-		FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
-		FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
-		/* IP5_26_24 [3] */
-		FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
-		FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
-		FN_MSIOF0_SCK_B, 0,
-		/* IP5_23_21 [3] */
-		FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
-		FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C,
-		/* IP5_20_18 [3] */
-		FN_WE0_N, FN_IECLK, FN_CAN_CLK,
-		FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
-		/* IP5_17_15 [3] */
-		FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
-		FN_INTC_IRQ4_N, 0, 0,
-		/* IP5_14_13 [2] */
-		FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
-		/* IP5_12_10 [3] */
-		FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
-		0, 0,
-		/* IP5_9_6 [4] */
-		FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
-		FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
-		FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
-		/* IP5_5_3 [3] */
-		FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
-		FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
-		FN_INTC_EN0_N, FN_I2C1_SCL,
-		/* IP5_2_0 [3] */
-		FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
-		FN_VI2_R3, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
-			     GROUP(3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3),
-			     GROUP(
-		/* IP6_31_29 [3] */
-		FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
-		FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
-		/* IP6_28_26 [3] */
-		FN_ETH_LINK, 0, FN_HTX0_E,
-		FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
-		/* IP6_25_23 [3] */
-		FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
-		FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
-		/* IP6_22_20 [3] */
-		FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
-		FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
-		/* IP6_19_17 [3] */
-		FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
-		FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
-		/* IP6_16_14 [3] */
-		FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
-		FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
-		FN_I2C2_SCL_E, 0,
-		/* IP6_13_11 [3] */
-		FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
-		FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
-		/* IP6_10_9 [2] */
-		FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
-		/* IP6_8_6 [3] */
-		FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
-		FN_SSI_SDATA8_C, 0, 0, 0,
-		/* IP6_5_3 [3] */
-		FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
-		FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
-		/* IP6_2_0 [3] */
-		FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
-		FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
-			     GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
-			     GROUP(
-		/* IP7_31 [1] */
-		0, 0,
-		/* IP7_30_29 [2] */
-		FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
-		/* IP7_28_27 [2] */
-		FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
-		/* IP7_26_25 [2] */
-		FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
-		/* IP7_24_22 [3] */
-		FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
-		0, 0, 0,
-		/* IP7_21_19 [3] */
-		FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
-		FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
-		/* IP7_18_16 [3] */
-		FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
-		FN_GLO_SS_C, 0, 0, 0,
-		/* IP7_15_13 [3] */
-		FN_ETH_MDC, 0, FN_STP_ISD_1_B,
-		FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
-		/* IP7_12_10 [3] */
-		FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
-		FN_GLO_SCLK_C, 0, 0, 0,
-		/* IP7_9_8 [2] */
-		FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
-		/* IP7_7_6 [2] */
-		FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
-		/* IP7_5_3 [3] */
-		FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
-		/* IP7_2_0 [3] */
-		FN_ETH_MDIO, 0, FN_HRTS0_N_E,
-		FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
-			     GROUP(1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
-				   2, 2, 2, 2, 2, 2),
-			     GROUP(
-		/* IP8_31 [1] */
-		0, 0,
-		/* IP8_30_29 [2] */
-		FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
-		/* IP8_28 [1] */
-		FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
-		/* IP8_27 [1] */
-		FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
-		/* IP8_26 [1] */
-		FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
-		/* IP8_25_24 [2] */
-		FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
-		FN_AVB_MAGIC, 0,
-		/* IP8_23_22 [2] */
-		FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
-		/* IP8_21_20 [2] */
-		FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
-		/* IP8_19_18 [2] */
-		FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
-		/* IP8_17_16 [2] */
-		FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
-		/* IP8_15_14 [2] */
-		FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
-		/* IP8_13_12 [2] */
-		FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
-		/* IP8_11_10 [2] */
-		FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
-		/* IP8_9_8 [2] */
-		FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
-		/* IP8_7_6 [2] */
-		FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
-		/* IP8_5_4 [2] */
-		FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
-		/* IP8_3_2 [2] */
-		FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
-		/* IP8_1_0 [2] */
-		FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
-			     GROUP(4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2),
-			     GROUP(
-		/* IP9_31_28 [4] */
-		FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
-		FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
-		FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
-		/* IP9_27_26 [2] */
-		FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
-		/* IP9_25_24 [2] */
-		FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
-		/* IP9_23_22 [2] */
-		FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
-		/* IP9_21_20 [2] */
-		FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
-		/* IP9_19_18 [2] */
-		FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
-		/* IP9_17_16 [2] */
-		FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
-		/* IP9_15_12 [4] */
-		FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
-		FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
-		FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
-		/* IP9_11_8 [4] */
-		FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
-		FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
-		FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
-		/* IP9_7_6 [2] */
-		FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
-		/* IP9_5_4 [2] */
-		FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
-		/* IP9_3_2 [2] */
-		FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
-		/* IP9_1_0 [2] */
-		FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
-			     GROUP(2, 4, 3, 4, 4, 4, 4, 3, 4),
-			     GROUP(
-		/* IP10_31_30 [2] */
-		0, 0, 0, 0,
-		/* IP10_29_26 [4] */
-		FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
-		FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
-		FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
-		/* IP10_25_23 [3] */
-		FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
-		FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
-		/* IP10_22_19 [4] */
-		FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
-		FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
-		FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
-		/* IP10_18_15 [4] */
-		FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
-		FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
-		FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
-		0, 0, 0, 0, 0, 0,
-		/* IP10_14_11 [4] */
-		FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
-		FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
-		FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
-		0, 0, 0, 0, 0, 0, 0,
-		/* IP10_10_7 [4] */
-		FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
-		FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
-		FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
-		0, 0, 0, 0, 0, 0, 0,
-		/* IP10_6_4 [3] */
-		FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
-		FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
-		FN_VI3_DATA0_B, 0,
-		/* IP10_3_0 [4] */
-		FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
-		FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
-		FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
-			     GROUP(2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4),
-			     GROUP(
-		/* IP11_31_30 [2] */
-		FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
-		/* IP11_29_27 [3] */
-		FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
-		0, 0, 0,
-		/* IP11_26_24 [3] */
-		FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
-		0, 0, 0,
-		/* IP11_23_22 [2] */
-		FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
-		/* IP11_21_18 [4] */
-		FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
-		0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
-		/* IP11_17_15 [3] */
-		FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
-		FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
-		/* IP11_14_13 [2] */
-		FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
-		/* IP11_12_11 [2] */
-		FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
-		/* IP11_10_9 [2] */
-		FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
-		/* IP11_8_7 [2] */
-		FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
-		/* IP11_6_5 [2] */
-		FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
-		/* IP11_4 [1] */
-		FN_SD3_CLK, FN_MMC1_CLK,
-		/* IP11_3_0 [4] */
-		FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
-		FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
-		FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
-			     GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2),
-			     GROUP(
-		/* IP12_31 [1] */
-		0, 0,
-		/* IP12_30_28 [3] */
-		FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
-		FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
-		FN_CAN_DEBUGOUT4, 0, 0,
-		/* IP12_27_25 [3] */
-		FN_SSI_SCK5, FN_SCIFB1_SCK,
-		FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
-		FN_CAN_DEBUGOUT3, 0, 0,
-		/* IP12_24_23 [2] */
-		FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
-		FN_CAN_DEBUGOUT2,
-		/* IP12_22_20 [3] */
-		FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
-		FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
-		/* IP12_19_17 [3] */
-		FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
-		FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
-		/* IP12_16_14 [3] */
-		FN_SSI_SDATA3, FN_STP_ISCLK_0,
-		FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
-		/* IP12_13_11 [3] */
-		FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
-		FN_CAN_STEP0, 0, 0, 0,
-		/* IP12_10_8 [3] */
-		FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
-		FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
-		/* IP12_7_6 [2] */
-		FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
-		/* IP12_5_4 [2] */
-		FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
-		/* IP12_3_2 [2] */
-		FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
-		/* IP12_1_0 [2] */
-		FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
-			     GROUP(1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3),
-			     GROUP(
-		/* IP13_31 [1] */
-		0, 0,
-		/* IP13_30_29 [2] */
-		FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
-		/* IP13_28_26 [3] */
-		FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
-		FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
-		/* IP13_25_23 [3] */
-		FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
-		FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
-		/* IP13_22_19 [4] */
-		FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
-		FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
-		0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
-		/* IP13_18_16 [3] */
-		FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
-		FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
-		/* IP13_15_13 [3] */
-		FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
-		FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
-		/* IP13_12_10 [3] */
-		FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
-		FN_CAN_DEBUGOUT8, 0, 0,
-		/* IP13_9_7 [3] */
-		FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
-		FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
-		/* IP13_6_3 [4] */
-		FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
-		FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
-		FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP13_2_0 [3] */
-		FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
-		FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
-			     GROUP(1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3),
-			     GROUP(
-		/* IP14_30 [1] */
-		0, 0,
-		/* IP14_30_28 [3] */
-		FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
-		FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
-		FN_HRTS0_N_C, 0,
-		/* IP14_27_25 [3] */
-		FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
-		FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
-		/* IP14_24_22 [3] */
-		FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
-		FN_LCDOUT9, 0, 0, 0,
-		/* IP14_21_19 [3] */
-		FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
-		FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
-		/* IP14_18_16 [3] */
-		FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
-		FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
-		/* IP14_15_12 [4] */
-		FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
-		FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
-		0, 0, 0, 0, 0, 0, 0,
-		/* IP14_11_9 [3] */
-		FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
-		0, 0, 0,
-		/* IP14_8_6 [3] */
-		FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
-		0, 0, 0,
-		/* IP14_5_3 [3] */
-		FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
-		FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
-		/* IP14_2_0 [3] */
-		FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
-		FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
-		FN_REMOCON, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
-			     GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3),
-			     GROUP(
-		/* IP15_31_30 [2] */
-		0, 0, 0, 0,
-		/* IP15_29_28 [2] */
-		FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
-		/* IP15_27_26 [2] */
-		FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
-		/* IP15_25_23 [3] */
-		FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
-		FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
-		/* IP15_22_20 [3] */
-		FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
-		FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
-		/* IP15_19_18 [2] */
-		FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
-		/* IP15_17_16 [2] */
-		FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
-		/* IP15_15_14 [2] */
-		FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
-		/* IP15_13_12 [2] */
-		FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
-		/* IP15_11_9 [3] */
-		FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
-		0, 0, 0,
-		/* IP15_8_6 [3] */
-		FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
-		FN_IIC2_SDA, FN_I2C2_SDA, 0,
-		/* IP15_5_3 [3] */
-		FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16,
-		FN_IIC2_SCL, FN_I2C2_SCL, 0,
-		/* IP15_2_0 [3] */
-		FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
-		FN_LCDOUT15, FN_SCIF_CLK_B, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
-			     GROUP(4, 4, 4, 4, 4, 4, 1, 1, 3, 3),
-			     GROUP(
-		/* IP16_31_28 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP16_27_24 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP16_23_20 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP16_19_16 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP16_15_12 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP16_11_8 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP16_7 [1] */
-		FN_USB1_OVC, FN_TCLK1_B,
-		/* IP16_6 [1] */
-		FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
-		/* IP16_5_3 [3] */
-		FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
-		FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
-		/* IP16_2_0 [3] */
-		FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
-		FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
-			     GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1,
-				   1, 1, 1, 2, 1, 1, 2, 1, 1),
-			     GROUP(
-		/* SEL_SCIF1 [3] */
-		FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
-		FN_SEL_SCIF1_4, 0, 0, 0,
-		/* SEL_SCIFB [2] */
-		FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
-		/* SEL_SCIFB2 [2] */
-		FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
-		/* SEL_SCIFB1 [3] */
-		FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
-		FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
-		FN_SEL_SCIFB1_6, 0,
-		/* SEL_SCIFA1 [2] */
-		FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
-		FN_SEL_SCIFA1_3,
-		/* SEL_SCIF0 [1] */
-		FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
-		/* SEL_SCIFA [1] */
-		FN_SEL_SCFA_0, FN_SEL_SCFA_1,
-		/* SEL_SOF1 [1] */
-		FN_SEL_SOF1_0, FN_SEL_SOF1_1,
-		/* SEL_SSI7 [2] */
-		FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
-		/* SEL_SSI6 [1] */
-		FN_SEL_SSI6_0, FN_SEL_SSI6_1,
-		/* SEL_SSI5 [2] */
-		FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
-		/* SEL_VI3 [1] */
-		FN_SEL_VI3_0, FN_SEL_VI3_1,
-		/* SEL_VI2 [1] */
-		FN_SEL_VI2_0, FN_SEL_VI2_1,
-		/* SEL_VI1 [1] */
-		FN_SEL_VI1_0, FN_SEL_VI1_1,
-		/* SEL_VI0 [1] */
-		FN_SEL_VI0_0, FN_SEL_VI0_1,
-		/* SEL_TSIF1 [2] */
-		FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* SEL_LBS [1] */
-		FN_SEL_LBS_0, FN_SEL_LBS_1,
-		/* SEL_TSIF0 [2] */
-		FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
-		/* SEL_SOF3 [1] */
-		FN_SEL_SOF3_0, FN_SEL_SOF3_1,
-		/* SEL_SOF0 [1] */
-		FN_SEL_SOF0_0, FN_SEL_SOF0_1, ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
-			     GROUP(3, 1, 1, 1, 2, 1, 2, 1, 2, 1, 1, 1,
-				   3, 3, 2, 3, 2, 2),
-			     GROUP(
-		/* RESERVED [3] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* SEL_TMU1 [1] */
-		FN_SEL_TMU1_0, FN_SEL_TMU1_1,
-		/* SEL_HSCIF1 [1] */
-		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
-		/* SEL_SCIFCLK [1] */
-		FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
-		/* SEL_CAN0 [2] */
-		FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
-		/* SEL_CANCLK [1] */
-		FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
-		/* SEL_SCIFA2 [2] */
-		FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
-		/* SEL_CAN1 [1] */
-		FN_SEL_CAN1_0, FN_SEL_CAN1_1,
-		/* RESERVED [2] */
-		0, 0, 0, 0,
-		/* SEL_SCIF2 [1] */
-		FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
-		/* SEL_ADI [1] */
-		FN_SEL_ADI_0, FN_SEL_ADI_1,
-		/* SEL_SSP [1] */
-		FN_SEL_SSP_0, FN_SEL_SSP_1,
-		/* SEL_FM [3] */
-		FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
-		FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
-		/* SEL_HSCIF0 [3] */
-		FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
-		FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
-		/* SEL_GPS [2] */
-		FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
-		/* RESERVED [3] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* SEL_SIM [2] */
-		FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
-		/* SEL_SSI8 [2] */
-		FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
-			     GROUP(1, 1, 2, 4, 4, 2, 2, 4, 2, 3, 2, 3, 2),
-			     GROUP(
-		/* SEL_IICDVFS [1] */
-		FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
-		/* SEL_IIC0 [1] */
-		FN_SEL_IIC0_0, FN_SEL_IIC0_1,
-		/* RESERVED [2] */
-		0, 0, 0, 0,
-		/* RESERVED [4] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED [4] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED [2] */
-		0, 0, 0, 0,
-		/* SEL_IEB [2] */
-		FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
-		/* RESERVED [4] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED [2] */
-		0, 0, 0, 0,
-		/* SEL_IIC2 [3] */
-		FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
-		FN_SEL_IIC2_4, 0, 0, 0,
-		/* SEL_IIC1 [2] */
-		FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
-		/* SEL_I2C2 [3] */
-		FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
-		FN_SEL_I2C2_4, 0, 0, 0,
-		/* SEL_I2C1 [2] */
-		FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, ))
-	},
-	{ },
-};
-
-static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
-{
-	if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31))
-		return -EINVAL;
-
-	*pocctrl = 0xe606008c;
-
-	return 31 - (pin & 0x1f);
-}
-
-static const struct soc_device_attribute r8a7790_tdsel[] = {
-	{ .soc_id = "r8a7790", .revision = "ES1.0" },
-	{ /* sentinel */ }
-};
-
-static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc)
-{
-	/* Initialize TDSEL on old revisions */
-	if (soc_device_match(r8a7790_tdsel))
-		sh_pfc_write(pfc, 0xe6060088, 0x00155554);
-
-	return 0;
-}
-
-static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
-	.init = r8a7790_pinmux_soc_init,
-	.pin_to_pocctrl = r8a7790_pin_to_pocctrl,
-};
-
-const struct sh_pfc_soc_info r8a7790_pinmux_info = {
-	.name = "r8a77900_pfc",
-	.ops = &r8a7790_pinmux_ops,
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups,
-	.nr_groups = ARRAY_SIZE(pinmux_groups),
-	.functions = pinmux_functions,
-	.nr_functions = ARRAY_SIZE(pinmux_functions),
-
-	.cfg_regs = pinmux_config_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
deleted file mode 100644
index bc9caf812fc1..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ /dev/null
@@ -1,6724 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * r8a7791/r8a7743 processor support - PFC hardware block.
- *
- * Copyright (C) 2013 Renesas Electronics Corporation
- * Copyright (C) 2014-2017 Cogent Embedded, Inc.
- */
-
-#include <linux/errno.h>
-#include <linux/kernel.h>
-
-#include "sh_pfc.h"
-
-/*
- * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
- * which case they support both 3.3V and 1.8V signalling.
- */
-#define CPU_ALL_GP(fn, sfx)						\
-	PORT_GP_32(0, fn, sfx),						\
-	PORT_GP_26(1, fn, sfx),						\
-	PORT_GP_32(2, fn, sfx),						\
-	PORT_GP_32(3, fn, sfx),						\
-	PORT_GP_32(4, fn, sfx),						\
-	PORT_GP_32(5, fn, sfx),						\
-	PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),		\
-	PORT_GP_1(6, 24, fn, sfx),					\
-	PORT_GP_1(6, 25, fn, sfx),					\
-	PORT_GP_1(6, 26, fn, sfx),					\
-	PORT_GP_1(6, 27, fn, sfx),					\
-	PORT_GP_1(6, 28, fn, sfx),					\
-	PORT_GP_1(6, 29, fn, sfx),					\
-	PORT_GP_1(6, 30, fn, sfx),					\
-	PORT_GP_1(6, 31, fn, sfx),					\
-	PORT_GP_26(7, fn, sfx)
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	GP_ALL(DATA),
-	PINMUX_DATA_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	GP_ALL(FN),
-
-	/* GPSR0 */
-	FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
-	FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
-	FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
-	FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
-	FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
-	FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
-
-	/* GPSR1 */
-	FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
-	FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
-	FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
-	FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
-	FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
-	FN_IP3_21_20,
-
-	/* GPSR2 */
-	FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
-	FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
-	FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
-	FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
-	FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
-	FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
-	FN_IP6_5_3, FN_IP6_7_6,
-
-	/* GPSR3 */
-	FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
-	FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
-	FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
-	FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
-	FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
-	FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
-	FN_IP9_18_17,
-
-	/* GPSR4 */
-	FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
-	FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
-	FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
-	FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
-	FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
-	FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
-	FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
-	FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
-
-	/* GPSR5 */
-	FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
-	FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
-	FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
-	FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
-	FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
-	FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
-	FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
-
-	/* GPSR6 */
-	FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
-	FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19,
-	FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK,
-	FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
-	FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
-	FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
-	FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
-	FN_USB1_OVC, FN_DU0_DOTCLKIN,
-
-	/* GPSR7 */
-	FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
-	FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
-	FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
-	FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
-	FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
-	FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
-
-	/* IPSR0 */
-	FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
-	FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
-	FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
-	FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
-	FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
-	FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
-
-	/* IPSR1 */
-	FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL,
-	FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA,
-	FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
-	FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
-	FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
-	FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
-	FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
-	FN_A15, FN_BPFCLK_C,
-	FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
-	FN_A17, FN_DACK2_B, FN_I2C0_SDA_C,
-	FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
-
-	/* IPSR2 */
-	FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
-	FN_A20, FN_SPCLK,
-	FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
-	FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
-	FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
-	FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
-	FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
-	FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL,
-	FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA,
-	FN_EX_CS1_N, FN_MSIOF2_SCK,
-	FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
-	FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
-
-	/* IPSR3 */
-	FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
-	FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
-	FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
-	FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
-	FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
-	FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
-	FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
-	FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
-	FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
-	FN_DREQ0, FN_PWM3, FN_TPU_TO3,
-	FN_DACK0, FN_DRACK0, FN_REMOCON,
-	FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
-	FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
-	FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
-	FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
-
-	/* IPSR4 */
-	FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
-	FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, FN_MSIOF2_SYNC_C,
-	FN_GLO_I0_D,
-	FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
-	FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
-	FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
-	FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
-	FN_GLO_Q1_D, FN_HCTS1_N_E,
-	FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
-	FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
-	FN_SSI_SCK4, FN_GLO_SS_D,
-	FN_SSI_WS4, FN_GLO_RFON_D,
-	FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
-	FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
-	FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
-
-	/* IPSR5 */
-	FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
-	FN_MSIOF2_TXD_D, FN_VI1_R3_B,
-	FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
-	FN_MSIOF2_SS1_D, FN_VI1_R4_B,
-	FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
-	FN_MSIOF2_RXD_D, FN_VI1_R5_B,
-	FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
-	FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
-	FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
-	FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
-	FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
-	FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
-	FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
-	FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
-	FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
-
-	/* IPSR6 */
-	FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
-	FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
-	FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
-	FN_SCIFA2_RXD, FN_FMIN_E,
-	FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
-	FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
-	FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
-	FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
-	FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
-	FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
-	FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
-	FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
-	FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
-	FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
-
-	/* IPSR7 */
-	FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
-	FN_SCIF_CLK_B, FN_GPS_MAG_D,
-	FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
-	FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
-	FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
-	FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
-	FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
-	FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
-	FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
-	FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
-	FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
-	FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
-	FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
-	FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
-	FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
-	FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
-	FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
-	FN_SCIFA1_SCK, FN_SSI_SCK78_B,
-
-	/* IPSR8 */
-	FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
-	FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
-	FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
-	FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
-	FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
-	FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
-	FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
-	FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
-	FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
-	FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
-	FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
-	FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
-	FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
-	FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
-	FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
-	FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
-	FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
-
-	/* IPSR9 */
-	FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
-	FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
-	FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
-	FN_DU1_DOTCLKOUT0, FN_QCLK,
-	FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
-	FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
-	FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
-	FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
-	FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
-	FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
-	FN_DU1_DISP, FN_QPOLA,
-	FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
-	FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
-	FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
-	FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
-	FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
-	FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
-	FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
-	FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
-
-	/* IPSR10 */
-	FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
-	FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
-	FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
-	FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
-	FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
-	FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
-	FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
-	FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
-	FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
-	FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
-	FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
-	FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
-	FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
-	FN_TS_SDATA0_C, FN_ATACS11_N,
-	FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
-	FN_TS_SCK0_C, FN_ATAG1_N,
-	FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
-	FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
-	FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
-
-	/* IPSR11 */
-	FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_I2C1_SDA_D,
-	FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
-	FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
-	FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
-	FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
-	FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
-	FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
-	FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
-	FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
-	FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
-	FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
-	FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
-	FN_VI1_DATA7, FN_AVB_MDC,
-	FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C,
-	FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C,
-
-	/* IPSR12 */
-	FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL,
-	FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
-	FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
-	FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
-	FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
-	FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
-	FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
-	FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
-	FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
-	FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
-	FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
-	FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
-	FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
-	FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
-	FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
-	FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
-	FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
-
-	/* IPSR13 */
-	FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
-	FN_ADICLK_B, FN_MSIOF0_SS1_C,
-	FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
-	FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
-	FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
-	FN_ADICHS2_B, FN_MSIOF0_TXD_C,
-	FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
-	FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
-	FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
-	FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
-	FN_SCIFA5_TXD_B, FN_TX3_C,
-	FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
-	FN_SCIFA5_RXD_B, FN_RX3_C,
-	FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
-	FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
-	FN_SD1_DATA3, FN_IERX_B,
-	FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
-
-	/* IPSR14 */
-	FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C,
-	FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
-	FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
-	FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
-	FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
-	FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
-	FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
-	FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
-	FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
-	FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
-	FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
-	FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B,
-	FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
-	FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B,
-
-	/* IPSR15 */
-	FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
-	FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
-	FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
-	FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
-	FN_PWM5_B, FN_SCIFA3_TXD_C,
-	FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
-	FN_VI1_G6_B, FN_SCIFA3_RXD_C,
-	FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
-	FN_VI1_G7_B, FN_SCIFA3_SCK_C,
-	FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
-	FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
-	FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
-	FN_TCLK2, FN_VI1_DATA3_C,
-	FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
-	FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
-
-	/* IPSR16 */
-	FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
-	FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
-	FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
-	FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
-	FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
-
-	/* MOD_SEL */
-	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
-	FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
-	FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
-	FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
-	FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
-	FN_SEL_SSI9_0, FN_SEL_SSI9_1,
-	FN_SEL_SCFA_0, FN_SEL_SCFA_1,
-	FN_SEL_QSP_0, FN_SEL_QSP_1,
-	FN_SEL_SSI7_0, FN_SEL_SSI7_1,
-	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
-	FN_SEL_HSCIF1_4,
-	FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
-	FN_SEL_TMU1_0, FN_SEL_TMU1_1,
-	FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
-	FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
-	FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
-
-	/* MOD_SEL2 */
-	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
-	FN_SEL_SCIF0_4,
-	FN_SEL_SCIF_0, FN_SEL_SCIF_1,
-	FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
-	FN_SEL_CAN0_4, FN_SEL_CAN0_5,
-	FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
-	FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
-	FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
-	FN_SEL_ADG_0, FN_SEL_ADG_1,
-	FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
-	FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
-	FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
-	FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
-	FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
-	FN_SEL_SIM_0, FN_SEL_SIM_1,
-	FN_SEL_SSI8_0, FN_SEL_SSI8_1,
-
-	/* MOD_SEL3 */
-	FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
-	FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
-	FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
-	FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
-	FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2,
-	FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
-	FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
-	FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
-	FN_SEL_MMC_0, FN_SEL_MMC_1,
-	FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
-	FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
-	FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
-	FN_SEL_I2C1_4,
-	FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2,
-
-	/* MOD_SEL4 */
-	FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
-	FN_SEL_SOF1_4,
-	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
-	FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
-	FN_SEL_RAD_0, FN_SEL_RAD_1,
-	FN_SEL_RCN_0, FN_SEL_RCN_1,
-	FN_SEL_RSP_0, FN_SEL_RSP_1,
-	FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
-	FN_SEL_SCIF2_4,
-	FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
-	FN_SEL_SOF2_4,
-	FN_SEL_SSI1_0, FN_SEL_SSI1_1,
-	FN_SEL_SSI0_0, FN_SEL_SSI0_1,
-	FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-
-	EX_CS0_N_MARK, RD_N_MARK,
-
-	AUDIO_CLKA_MARK,
-
-	VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
-	VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
-	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
-
-	SD1_CLK_MARK,
-
-	USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
-	DU0_DOTCLKIN_MARK,
-
-	/* IPSR0 */
-	D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
-	D6_MARK, D7_MARK, D8_MARK,
-	D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
-	A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, I2C0_SCL_C_MARK,
-	PWM2_B_MARK,
-	A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
-	A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
-	A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
-
-	/* IPSR1 */
-	A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, I2C0_SCL_MARK,
-	A9_MARK, MSIOF1_SS2_MARK, I2C0_SDA_MARK,
-	A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
-	A11_MARK, MSIOF1_RXD_MARK, I2C3_SCL_D_MARK, MSIOF1_RXD_D_MARK,
-	A12_MARK, FMCLK_MARK, I2C3_SDA_D_MARK, MSIOF1_SCK_D_MARK,
-	A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
-	A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
-	A15_MARK, BPFCLK_C_MARK,
-	A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
-	A17_MARK, DACK2_B_MARK, I2C0_SDA_C_MARK,
-	A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
-
-	/* IPSR2 */
-	A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
-	SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
-	A20_MARK, SPCLK_MARK,
-	A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
-	A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
-	A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
-	A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
-	A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
-	RX1_MARK, SCIFA1_RXD_MARK,
-	CS0_N_MARK, ATAG0_N_B_MARK, I2C1_SCL_MARK,
-	CS1_N_A26_MARK, ATADIR0_N_B_MARK, I2C1_SDA_MARK,
-	EX_CS1_N_MARK, MSIOF2_SCK_MARK,
-	EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
-	EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
-	ATAG0_N_MARK, EX_WAIT1_MARK,
-
-	/* IPSR3 */
-	EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
-	EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
-	SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
-	BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
-	SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
-	RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
-	SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
-	WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
-	WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
-	EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
-	DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
-	DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
-	SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
-	SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
-	SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
-	SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
-	SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
-	SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
-
-	/* IPSR4 */
-	SSI_SDATA0_MARK, I2C0_SCL_B_MARK, IIC0_SCL_B_MARK, MSIOF2_SCK_C_MARK,
-	SSI_SCK1_MARK, I2C0_SDA_B_MARK, IIC0_SDA_B_MARK,
-	MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
-	SSI_WS1_MARK, I2C1_SCL_B_MARK, IIC1_SCL_B_MARK,
-	MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
-	SSI_SDATA1_MARK, I2C1_SDA_B_MARK, IIC1_SDA_B_MARK, MSIOF2_RXD_C_MARK,
-	SSI_SCK2_MARK, I2C2_SCL_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK,
-	HSCK1_E_MARK,
-	SSI_WS2_MARK, I2C2_SDA_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
-	GLO_Q1_D_MARK, HCTS1_N_E_MARK,
-	SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
-	SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
-	SSI_SCK4_MARK, GLO_SS_D_MARK,
-	SSI_WS4_MARK, GLO_RFON_D_MARK,
-	SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
-	SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
-	MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
-
-	/* IPSR5 */
-	SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
-	MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
-	SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
-	MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
-	SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
-	MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
-	SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
-	SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
-	SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
-	SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
-	SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
-	SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
-	SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
-	SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
-	SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
-
-	/* IPSR6 */
-	AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
-	SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK,
-	AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
-	SCIFA2_RXD_MARK, FMIN_E_MARK,
-	AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
-	IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
-	IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
-	IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
-	IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
-	IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK,
-	MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
-	IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK,
-	IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
-	I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK,
-	IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
-	GPS_CLK_C_MARK, GPS_CLK_D_MARK,
-	IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
-	GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
-
-	/* IPSR7 */
-	IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
-	SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
-	DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
-	SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
-	DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
-	SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
-	DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
-	DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
-	DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
-	DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
-	DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
-	DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
-	DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
-	SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
-	DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
-	SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
-	DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
-	SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
-
-	/* IPSR8 */
-	DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
-	DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
-	SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
-	DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
-	SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
-	DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
-	SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
-	DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
-	SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
-	DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
-	SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
-	DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
-	SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
-	DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
-	SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
-	DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
-	DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
-	DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
-
-	/* IPSR9 */
-	DU1_DB6_MARK, LCDOUT22_MARK, I2C3_SCL_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
-	DU1_DB7_MARK, LCDOUT23_MARK, I2C3_SDA_C_MARK,
-	SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
-	DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
-	DU1_DOTCLKOUT0_MARK, QCLK_MARK,
-	DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
-	TX3_B_MARK, I2C2_SCL_B_MARK, PWM4_MARK,
-	DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
-	DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
-	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
-	CAN0_RX_MARK, RX3_B_MARK, I2C2_SDA_B_MARK,
-	DU1_DISP_MARK, QPOLA_MARK,
-	DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
-	VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
-	VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
-	VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
-	VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
-	VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
-	VI0_G0_MARK, IIC1_SCL_MARK, STP_IVCXO27_0_C_MARK, I2C4_SCL_MARK,
-	HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
-
-	/* IPSR10 */
-	VI0_G1_MARK, IIC1_SDA_MARK, STP_ISCLK_0_C_MARK, I2C4_SDA_MARK,
-	HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
-	VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, I2C3_SCL_B_MARK,
-	HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
-	VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, I2C3_SDA_B_MARK,
-	HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
-	VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
-	HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
-	VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
-	CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
-	VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
-	VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
-	VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
-	TS_SDATA0_C_MARK, ATACS11_N_MARK,
-	VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
-	TS_SCK0_C_MARK, ATAG1_N_MARK,
-	VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
-	VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
-	VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK,
-	I2C1_SCL_D_MARK,
-
-	/* IPSR11 */
-	VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK,
-	I2C1_SDA_D_MARK,
-	VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, I2C4_SCL_B_MARK,
-	VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
-	I2C4_SDA_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
-	VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
-	TX4_B_MARK, SCIFA4_TXD_B_MARK,
-	VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
-	RX4_B_MARK, SCIFA4_RXD_B_MARK,
-	VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
-	VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
-	VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
-	VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
-	VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
-	VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
-	VI1_DATA7_MARK, AVB_MDC_MARK,
-	ETH_MDIO_MARK, AVB_RX_CLK_MARK, I2C2_SCL_C_MARK,
-	ETH_CRS_DV_MARK, AVB_LINK_MARK, I2C2_SDA_C_MARK,
-
-	/* IPSR12 */
-	ETH_RX_ER_MARK, AVB_CRS_MARK, I2C3_SCL_MARK, IIC0_SCL_MARK,
-	ETH_RXD0_MARK, AVB_PHY_INT_MARK, I2C3_SDA_MARK, IIC0_SDA_MARK,
-	ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
-	I2C2_SCL_D_MARK, MSIOF1_RXD_E_MARK,
-	ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
-	I2C2_SDA_D_MARK, MSIOF1_SCK_E_MARK,
-	ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
-	CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
-	ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
-	CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
-	ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
-	ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
-	ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
-	ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
-	STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
-	ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
-	STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
-	ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
-
-	/* IPSR13 */
-	STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
-	ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
-	STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
-	STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
-	STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
-	ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
-	SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
-	SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
-	SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
-	SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
-	SCIFA5_TXD_B_MARK, TX3_C_MARK,
-	SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
-	SCIFA5_RXD_B_MARK, RX3_C_MARK,
-	SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
-	SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
-	SD1_DATA3_MARK, IERX_B_MARK,
-	SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, I2C1_SCL_C_MARK,
-
-	/* IPSR14 */
-	SD1_WP_MARK, PWM1_B_MARK, I2C1_SDA_C_MARK,
-	SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
-	SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
-	SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
-	SD2_CD_MARK, MMC_D4_MARK, IIC1_SCL_C_MARK, TX5_B_MARK,
-	SCIFA5_TXD_C_MARK,
-	SD2_WP_MARK, MMC_D5_MARK, IIC1_SDA_C_MARK, RX5_B_MARK,
-	SCIFA5_RXD_C_MARK,
-	MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
-	VI1_CLK_C_MARK, VI1_G0_B_MARK,
-	MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
-	VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
-	MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
-	MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
-	MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
-	VI1_HSYNC_N_C_MARK, IIC0_SCL_C_MARK, VI1_G4_B_MARK,
-	MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
-	VI1_VSYNC_N_C_MARK, IIC0_SDA_C_MARK, VI1_G5_B_MARK,
-
-	/* IPSR15 */
-	SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
-	SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
-	SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
-	GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
-	PWM5_B_MARK, SCIFA3_TXD_C_MARK,
-	GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
-	VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
-	GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
-	VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
-	HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
-	TCLK1_MARK, VI1_DATA1_C_MARK,
-	HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
-	HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
-	TCLK2_MARK, VI1_DATA3_C_MARK,
-	HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
-	CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
-	HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
-	CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
-
-	/* IPSR16 */
-	HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
-	GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
-	HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
-	GLO_SS_C_MARK, VI1_DATA7_C_MARK,
-	HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK,
-	HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
-	HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
-	PINMUX_MARK_END,
-};
-
-static const u16 pinmux_data[] = {
-	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
-
-	PINMUX_SINGLE(EX_CS0_N),
-	PINMUX_SINGLE(RD_N),
-	PINMUX_SINGLE(AUDIO_CLKA),
-	PINMUX_SINGLE(VI0_CLK),
-	PINMUX_SINGLE(VI0_DATA0_VI0_B0),
-	PINMUX_SINGLE(VI0_DATA1_VI0_B1),
-	PINMUX_SINGLE(VI0_DATA2_VI0_B2),
-	PINMUX_SINGLE(VI0_DATA4_VI0_B4),
-	PINMUX_SINGLE(VI0_DATA5_VI0_B5),
-	PINMUX_SINGLE(VI0_DATA6_VI0_B6),
-	PINMUX_SINGLE(VI0_DATA7_VI0_B7),
-	PINMUX_SINGLE(USB0_PWEN),
-	PINMUX_SINGLE(USB0_OVC),
-	PINMUX_SINGLE(USB1_PWEN),
-	PINMUX_SINGLE(USB1_OVC),
-	PINMUX_SINGLE(DU0_DOTCLKIN),
-	PINMUX_SINGLE(SD1_CLK),
-
-	/* IPSR0 */
-	PINMUX_IPSR_GPSR(IP0_0, D0),
-	PINMUX_IPSR_GPSR(IP0_1, D1),
-	PINMUX_IPSR_GPSR(IP0_2, D2),
-	PINMUX_IPSR_GPSR(IP0_3, D3),
-	PINMUX_IPSR_GPSR(IP0_4, D4),
-	PINMUX_IPSR_GPSR(IP0_5, D5),
-	PINMUX_IPSR_GPSR(IP0_6, D6),
-	PINMUX_IPSR_GPSR(IP0_7, D7),
-	PINMUX_IPSR_GPSR(IP0_8, D8),
-	PINMUX_IPSR_GPSR(IP0_9, D9),
-	PINMUX_IPSR_GPSR(IP0_10, D10),
-	PINMUX_IPSR_GPSR(IP0_11, D11),
-	PINMUX_IPSR_GPSR(IP0_12, D12),
-	PINMUX_IPSR_GPSR(IP0_13, D13),
-	PINMUX_IPSR_GPSR(IP0_14, D14),
-	PINMUX_IPSR_GPSR(IP0_15, D15),
-	PINMUX_IPSR_GPSR(IP0_18_16, A0),
-	PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
-	PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
-	PINMUX_IPSR_MSEL(IP0_18_16, I2C0_SCL_C, SEL_I2C0_2),
-	PINMUX_IPSR_GPSR(IP0_18_16, PWM2_B),
-	PINMUX_IPSR_GPSR(IP0_20_19, A1),
-	PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
-	PINMUX_IPSR_GPSR(IP0_22_21, A2),
-	PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
-	PINMUX_IPSR_GPSR(IP0_24_23, A3),
-	PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
-	PINMUX_IPSR_GPSR(IP0_26_25, A4),
-	PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
-	PINMUX_IPSR_GPSR(IP0_28_27, A5),
-	PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
-	PINMUX_IPSR_GPSR(IP0_30_29, A6),
-	PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
-
-	/* IPSR1 */
-	PINMUX_IPSR_GPSR(IP1_1_0, A7),
-	PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
-	PINMUX_IPSR_GPSR(IP1_3_2, A8),
-	PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
-	PINMUX_IPSR_MSEL(IP1_3_2, I2C0_SCL, SEL_I2C0_0),
-	PINMUX_IPSR_GPSR(IP1_5_4, A9),
-	PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
-	PINMUX_IPSR_MSEL(IP1_5_4, I2C0_SDA, SEL_I2C0_0),
-	PINMUX_IPSR_GPSR(IP1_7_6, A10),
-	PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
-	PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
-	PINMUX_IPSR_GPSR(IP1_10_8, A11),
-	PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
-	PINMUX_IPSR_MSEL(IP1_10_8, I2C3_SCL_D, SEL_I2C3_3),
-	PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
-	PINMUX_IPSR_GPSR(IP1_13_11, A12),
-	PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0),
-	PINMUX_IPSR_MSEL(IP1_13_11, I2C3_SDA_D, SEL_I2C3_3),
-	PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
-	PINMUX_IPSR_GPSR(IP1_16_14, A13),
-	PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
-	PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0),
-	PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
-	PINMUX_IPSR_GPSR(IP1_19_17, A14),
-	PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
-	PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0),
-	PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2),
-	PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
-	PINMUX_IPSR_GPSR(IP1_22_20, A15),
-	PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2),
-	PINMUX_IPSR_GPSR(IP1_25_23, A16),
-	PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1),
-	PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2),
-	PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
-	PINMUX_IPSR_GPSR(IP1_28_26, A17),
-	PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1),
-	PINMUX_IPSR_MSEL(IP1_28_26, I2C0_SDA_C, SEL_I2C0_2),
-	PINMUX_IPSR_GPSR(IP1_31_29, A18),
-	PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0),
-	PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
-	PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
-
-	/* IPSR2 */
-	PINMUX_IPSR_GPSR(IP2_2_0, A19),
-	PINMUX_IPSR_GPSR(IP2_2_0, DACK1),
-	PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
-	PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
-	PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1),
-	PINMUX_IPSR_GPSR(IP2_2_0, A20),
-	PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0),
-	PINMUX_IPSR_GPSR(IP2_6_5, A21),
-	PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
-	PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0),
-	PINMUX_IPSR_GPSR(IP2_9_7, A22),
-	PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0),
-	PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1),
-	PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0),
-	PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
-	PINMUX_IPSR_GPSR(IP2_12_10, A23),
-	PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0),
-	PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1),
-	PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
-	PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
-	PINMUX_IPSR_GPSR(IP2_15_13, A24),
-	PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0),
-	PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0),
-	PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0),
-	PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
-	PINMUX_IPSR_GPSR(IP2_18_16, A25),
-	PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0),
-	PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0),
-	PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2),
-	PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0),
-	PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
-	PINMUX_IPSR_GPSR(IP2_20_19, CS0_N),
-	PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
-	PINMUX_IPSR_MSEL(IP2_20_19, I2C1_SCL, SEL_I2C1_0),
-	PINMUX_IPSR_GPSR(IP2_22_21, CS1_N_A26),
-	PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
-	PINMUX_IPSR_MSEL(IP2_22_21, I2C1_SDA, SEL_I2C1_0),
-	PINMUX_IPSR_GPSR(IP2_24_23, EX_CS1_N),
-	PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
-	PINMUX_IPSR_GPSR(IP2_26_25, EX_CS2_N),
-	PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0),
-	PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
-	PINMUX_IPSR_GPSR(IP2_29_27, EX_CS3_N),
-	PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0),
-	PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
-	PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0),
-	PINMUX_IPSR_GPSR(IP2_29_27, EX_WAIT1),
-
-	/* IPSR3 */
-	PINMUX_IPSR_GPSR(IP3_2_0, EX_CS4_N),
-	PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0),
-	PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
-	PINMUX_IPSR_GPSR(IP3_2_0, EX_WAIT2),
-	PINMUX_IPSR_GPSR(IP3_5_3, EX_CS5_N),
-	PINMUX_IPSR_GPSR(IP3_5_3, ATACS00_N),
-	PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
-	PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
-	PINMUX_IPSR_GPSR(IP3_5_3, PWM1),
-	PINMUX_IPSR_GPSR(IP3_5_3, TPU_TO1),
-	PINMUX_IPSR_GPSR(IP3_8_6, BS_N),
-	PINMUX_IPSR_GPSR(IP3_8_6, ATACS10_N),
-	PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
-	PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
-	PINMUX_IPSR_GPSR(IP3_8_6, PWM2),
-	PINMUX_IPSR_GPSR(IP3_8_6, TPU_TO2),
-	PINMUX_IPSR_GPSR(IP3_11_9, RD_WR_N),
-	PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1),
-	PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
-	PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1),
-	PINMUX_IPSR_GPSR(IP3_13_12, WE0_N),
-	PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
-	PINMUX_IPSR_GPSR(IP3_15_14, WE1_N),
-	PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
-	PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
-	PINMUX_IPSR_GPSR(IP3_17_16, EX_WAIT0),
-	PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
-	PINMUX_IPSR_GPSR(IP3_19_18, DREQ0),
-	PINMUX_IPSR_GPSR(IP3_19_18, PWM3),
-	PINMUX_IPSR_GPSR(IP3_19_18, TPU_TO3),
-	PINMUX_IPSR_GPSR(IP3_21_20, DACK0),
-	PINMUX_IPSR_GPSR(IP3_21_20, DRACK0),
-	PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0),
-	PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0),
-	PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
-	PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
-	PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
-	PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
-	PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2),
-	PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
-	PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
-	PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
-	PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
-	PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
-	PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
-	PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
-	PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
-	PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
-	PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
-	PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
-
-	/* IPSR4 */
-	PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
-	PINMUX_IPSR_MSEL(IP4_1_0, I2C0_SCL_B, SEL_I2C0_1),
-	PINMUX_IPSR_MSEL(IP4_1_0, IIC0_SCL_B, SEL_IIC0_1),
-	PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
-	PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
-	PINMUX_IPSR_MSEL(IP4_4_2, I2C0_SDA_B, SEL_I2C0_1),
-	PINMUX_IPSR_MSEL(IP4_4_2, IIC0_SDA_B, SEL_IIC0_1),
-	PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
-	PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3),
-	PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0),
-	PINMUX_IPSR_MSEL(IP4_7_5, I2C1_SCL_B, SEL_I2C1_1),
-	PINMUX_IPSR_MSEL(IP4_7_5, IIC1_SCL_B, SEL_IIC1_1),
-	PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
-	PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3),
-	PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
-	PINMUX_IPSR_MSEL(IP4_9_8, I2C1_SDA_B, SEL_I2C1_1),
-	PINMUX_IPSR_MSEL(IP4_9_8, IIC1_SDA_B, SEL_IIC1_1),
-	PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
-	PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2),
-	PINMUX_IPSR_MSEL(IP4_12_10, I2C2_SCL, SEL_I2C2_0),
-	PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
-	PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
-	PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4),
-	PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2),
-	PINMUX_IPSR_MSEL(IP4_15_13, I2C2_SDA, SEL_I2C2_0),
-	PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
-	PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
-	PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
-	PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4),
-	PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2),
-	PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
-	PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
-	PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4),
-	PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34),
-	PINMUX_IPSR_GPSR(IP4_20, SSI_WS34),
-	PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3),
-	PINMUX_IPSR_GPSR(IP4_23_22, SSI_SCK4),
-	PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3),
-	PINMUX_IPSR_GPSR(IP4_25_24, SSI_WS4),
-	PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
-	PINMUX_IPSR_GPSR(IP4_27_26, SSI_SDATA4),
-	PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
-	PINMUX_IPSR_GPSR(IP4_30_28, SSI_SCK5),
-	PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
-	PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
-	PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0),
-	PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
-	PINMUX_IPSR_GPSR(IP4_30_28, VI1_R2_B),
-
-	/* IPSR5 */
-	PINMUX_IPSR_GPSR(IP5_2_0, SSI_WS5),
-	PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
-	PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
-	PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0),
-	PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
-	PINMUX_IPSR_GPSR(IP5_2_0, VI1_R3_B),
-	PINMUX_IPSR_GPSR(IP5_5_3, SSI_SDATA5),
-	PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
-	PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
-	PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0),
-	PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
-	PINMUX_IPSR_GPSR(IP5_5_3, VI1_R4_B),
-	PINMUX_IPSR_GPSR(IP5_8_6, SSI_SCK6),
-	PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
-	PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
-	PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0),
-	PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
-	PINMUX_IPSR_GPSR(IP5_8_6, VI1_R5_B),
-	PINMUX_IPSR_GPSR(IP5_11_9, SSI_WS6),
-	PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0),
-	PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
-	PINMUX_IPSR_GPSR(IP5_11_9, VI1_R6_B),
-	PINMUX_IPSR_GPSR(IP5_14_12, SSI_SDATA6),
-	PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
-	PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0),
-	PINMUX_IPSR_GPSR(IP5_14_12, VI1_R7_B),
-	PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
-	PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
-	PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0),
-	PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0),
-	PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3),
-	PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
-	PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0),
-	PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
-	PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3),
-	PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
-	PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
-	PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3),
-	PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
-	PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
-	PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3),
-	PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
-	PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0),
-	PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3),
-	PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
-	PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
-	PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
-	PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3),
-	PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
-
-	/* IPSR6 */
-	PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
-	PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
-	PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
-	PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
-	PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE),
-	PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
-	PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC),
-	PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
-	PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
-	PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0),
-	PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
-	PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
-	PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT),
-	PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
-	PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0),
-	PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
-	PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
-	PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
-	PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N),
-	PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),
-	PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
-	PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N),
-	PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),
-	PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
-	PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N),
-	PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),
-	PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2),
-	PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
-	PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N),
-	PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),
-	PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
-	PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2),
-	PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
-	PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N),
-	PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),
-	PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
-	PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4),
-	PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
-	PINMUX_IPSR_GPSR(IP6_23_21, IRQ6),
-	PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
-	PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
-	PINMUX_IPSR_MSEL(IP6_23_21, I2C1_SDA_E, SEL_I2C1_4),
-	PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
-	PINMUX_IPSR_GPSR(IP6_26_24, IRQ7),
-	PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
-	PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
-	PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
-	PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
-	PINMUX_IPSR_GPSR(IP6_29_27, IRQ8),
-	PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
-	PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
-	PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
-	PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
-
-	/* IPSR7 */
-	PINMUX_IPSR_GPSR(IP7_2_0, IRQ9),
-	PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
-	PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
-	PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
-	PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
-	PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
-	PINMUX_IPSR_GPSR(IP7_5_3, DU1_DR0),
-	PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0),
-	PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
-	PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1),
-	PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
-	PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
-	PINMUX_IPSR_GPSR(IP7_8_6, DU1_DR1),
-	PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1),
-	PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
-	PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1),
-	PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
-	PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
-	PINMUX_IPSR_GPSR(IP7_10_9, DU1_DR2),
-	PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2),
-	PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
-	PINMUX_IPSR_GPSR(IP7_12_11, DU1_DR3),
-	PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3),
-	PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
-	PINMUX_IPSR_GPSR(IP7_14_13, DU1_DR4),
-	PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4),
-	PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
-	PINMUX_IPSR_GPSR(IP7_16_15, DU1_DR5),
-	PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5),
-	PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
-	PINMUX_IPSR_GPSR(IP7_18_17, DU1_DR6),
-	PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6),
-	PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
-	PINMUX_IPSR_GPSR(IP7_20_19, DU1_DR7),
-	PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7),
-	PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
-	PINMUX_IPSR_GPSR(IP7_23_21, DU1_DG0),
-	PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8),
-	PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
-	PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1),
-	PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
-	PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
-	PINMUX_IPSR_GPSR(IP7_26_24, DU1_DG1),
-	PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9),
-	PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
-	PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1),
-	PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
-	PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
-	PINMUX_IPSR_GPSR(IP7_29_27, DU1_DG2),
-	PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10),
-	PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP7_29_27, SCIF1_SCK_B),
-	PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
-	PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
-
-	/* IPSR8 */
-	PINMUX_IPSR_GPSR(IP8_2_0, DU1_DG3),
-	PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11),
-	PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
-	PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
-	PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG4),
-	PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12),
-	PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
-	PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
-	PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
-	PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
-	PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG5),
-	PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13),
-	PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
-	PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
-	PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
-	PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
-	PINMUX_IPSR_GPSR(IP8_11_9, DU1_DG6),
-	PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14),
-	PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
-	PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
-	PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
-	PINMUX_IPSR_GPSR(IP8_14_12, DU1_DG7),
-	PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15),
-	PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
-	PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
-	PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
-	PINMUX_IPSR_GPSR(IP8_17_15, DU1_DB0),
-	PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16),
-	PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
-	PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1),
-	PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
-	PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
-	PINMUX_IPSR_GPSR(IP8_20_18, DU1_DB1),
-	PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17),
-	PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
-	PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1),
-	PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
-	PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
-	PINMUX_IPSR_GPSR(IP8_23_21, DU1_DB2),
-	PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18),
-	PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP8_23_21, SCIF2_SCK_B),
-	PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
-	PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
-	PINMUX_IPSR_GPSR(IP8_25_24, DU1_DB3),
-	PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19),
-	PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP8_27_26, DU1_DB4),
-	PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20),
-	PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
-	PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0),
-	PINMUX_IPSR_GPSR(IP8_30_28, DU1_DB5),
-	PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21),
-	PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0),
-	PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
-	PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0),
-
-	/* IPSR9 */
-	PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6),
-	PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22),
-	PINMUX_IPSR_MSEL(IP9_2_0, I2C3_SCL_C, SEL_I2C3_2),
-	PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0),
-	PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
-	PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7),
-	PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23),
-	PINMUX_IPSR_MSEL(IP9_5_3, I2C3_SDA_C, SEL_I2C3_2),
-	PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
-	PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
-	PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
-	PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS),
-	PINMUX_IPSR_GPSR(IP9_7, DU1_DOTCLKOUT0),
-	PINMUX_IPSR_GPSR(IP9_7, QCLK),
-	PINMUX_IPSR_GPSR(IP9_10_8, DU1_DOTCLKOUT1),
-	PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE),
-	PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0),
-	PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1),
-	PINMUX_IPSR_MSEL(IP9_10_8, I2C2_SCL_B, SEL_I2C2_1),
-	PINMUX_IPSR_GPSR(IP9_10_8, PWM4),
-	PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
-	PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS),
-	PINMUX_IPSR_GPSR(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
-	PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE),
-	PINMUX_IPSR_GPSR(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
-	PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE),
-	PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0),
-	PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1),
-	PINMUX_IPSR_MSEL(IP9_15_13, I2C2_SDA_B, SEL_I2C2_1),
-	PINMUX_IPSR_GPSR(IP9_16, DU1_DISP),
-	PINMUX_IPSR_GPSR(IP9_16, QPOLA),
-	PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE),
-	PINMUX_IPSR_GPSR(IP9_18_17, QPOLB),
-	PINMUX_IPSR_GPSR(IP9_18_17, PWM4_B),
-	PINMUX_IPSR_GPSR(IP9_20_19, VI0_CLKENB),
-	PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0),
-	PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
-	PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
-	PINMUX_IPSR_GPSR(IP9_22_21, VI0_FIELD),
-	PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0),
-	PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
-	PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
-	PINMUX_IPSR_GPSR(IP9_24_23, VI0_HSYNC_N),
-	PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0),
-	PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
-	PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
-	PINMUX_IPSR_GPSR(IP9_26_25, VI0_VSYNC_N),
-	PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0),
-	PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
-	PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
-	PINMUX_IPSR_GPSR(IP9_28_27, VI0_DATA3_VI0_B3),
-	PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
-	PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
-	PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0),
-	PINMUX_IPSR_MSEL(IP9_31_29, IIC1_SCL, SEL_IIC1_0),
-	PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
-	PINMUX_IPSR_MSEL(IP9_31_29, I2C4_SCL, SEL_I2C4_0),
-	PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
-	PINMUX_IPSR_GPSR(IP9_31_29, ATAWR1_N),
-
-	/* IPSR10 */
-	PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1),
-	PINMUX_IPSR_MSEL(IP10_2_0, IIC1_SDA, SEL_IIC1_0),
-	PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
-	PINMUX_IPSR_MSEL(IP10_2_0, I2C4_SDA, SEL_I2C4_0),
-	PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
-	PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N),
-	PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2),
-	PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N),
-	PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
-	PINMUX_IPSR_MSEL(IP10_5_3, I2C3_SCL_B, SEL_I2C3_1),
-	PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
-	PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N),
-	PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3),
-	PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N),
-	PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
-	PINMUX_IPSR_MSEL(IP10_8_6, I2C3_SDA_B, SEL_I2C3_1),
-	PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
-	PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N),
-	PINMUX_IPSR_GPSR(IP10_11_9, VI0_G4),
-	PINMUX_IPSR_GPSR(IP10_11_9, VI2_CLKENB),
-	PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
-	PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
-	PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
-	PINMUX_IPSR_GPSR(IP10_14_12, VI0_G5),
-	PINMUX_IPSR_GPSR(IP10_14_12, VI2_FIELD),
-	PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
-	PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3),
-	PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
-	PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
-	PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
-	PINMUX_IPSR_GPSR(IP10_16_15, VI0_G6),
-	PINMUX_IPSR_GPSR(IP10_16_15, VI2_CLK),
-	PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3),
-	PINMUX_IPSR_GPSR(IP10_18_17, VI0_G7),
-	PINMUX_IPSR_GPSR(IP10_18_17, VI2_DATA0),
-	PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3),
-	PINMUX_IPSR_GPSR(IP10_21_19, VI0_R0),
-	PINMUX_IPSR_GPSR(IP10_21_19, VI2_DATA1),
-	PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1),
-	PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
-	PINMUX_IPSR_GPSR(IP10_21_19, ATACS11_N),
-	PINMUX_IPSR_GPSR(IP10_24_22, VI0_R1),
-	PINMUX_IPSR_GPSR(IP10_24_22, VI2_DATA2),
-	PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1),
-	PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
-	PINMUX_IPSR_GPSR(IP10_24_22, ATAG1_N),
-	PINMUX_IPSR_GPSR(IP10_26_25, VI0_R2),
-	PINMUX_IPSR_GPSR(IP10_26_25, VI2_DATA3),
-	PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
-	PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
-	PINMUX_IPSR_GPSR(IP10_28_27, VI0_R3),
-	PINMUX_IPSR_GPSR(IP10_28_27, VI2_DATA4),
-	PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
-	PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
-	PINMUX_IPSR_GPSR(IP10_31_29, VI0_R4),
-	PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5),
-	PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
-	PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2),
-	PINMUX_IPSR_MSEL(IP10_31_29, I2C1_SCL_D, SEL_I2C1_3),
-
-	/* IPSR11 */
-	PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5),
-	PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6),
-	PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
-	PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2),
-	PINMUX_IPSR_MSEL(IP11_2_0, I2C1_SDA_D, SEL_I2C1_3),
-	PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6),
-	PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7),
-	PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1),
-	PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2),
-	PINMUX_IPSR_MSEL(IP11_5_3, I2C4_SCL_B, SEL_I2C4_1),
-	PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7),
-	PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
-	PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2),
-	PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
-	PINMUX_IPSR_MSEL(IP11_8_6, I2C4_SDA_B, SEL_I2C4_1),
-	PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
-	PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
-	PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
-	PINMUX_IPSR_GPSR(IP11_11_9, AVB_RXD0),
-	PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1),
-	PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
-	PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
-	PINMUX_IPSR_GPSR(IP11_14_12, AVB_RXD1),
-	PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1),
-	PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
-	PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
-	PINMUX_IPSR_GPSR(IP11_16_15, AVB_RXD2),
-	PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0),
-	PINMUX_IPSR_GPSR(IP11_18_17, AVB_RXD3),
-	PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0),
-	PINMUX_IPSR_GPSR(IP11_19, AVB_RXD4),
-	PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0),
-	PINMUX_IPSR_GPSR(IP11_20, AVB_RXD5),
-	PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0),
-	PINMUX_IPSR_GPSR(IP11_21, AVB_RXD6),
-	PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0),
-	PINMUX_IPSR_GPSR(IP11_22, AVB_RXD7),
-	PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0),
-	PINMUX_IPSR_GPSR(IP11_23, AVB_RX_ER),
-	PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0),
-	PINMUX_IPSR_GPSR(IP11_24, AVB_MDIO),
-	PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0),
-	PINMUX_IPSR_GPSR(IP11_25, AVB_RX_DV),
-	PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0),
-	PINMUX_IPSR_GPSR(IP11_26, AVB_MAGIC),
-	PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0),
-	PINMUX_IPSR_GPSR(IP11_27, AVB_MDC),
-	PINMUX_IPSR_GPSR(IP11_29_28, ETH_MDIO),
-	PINMUX_IPSR_GPSR(IP11_29_28, AVB_RX_CLK),
-	PINMUX_IPSR_MSEL(IP11_29_28, I2C2_SCL_C, SEL_I2C2_2),
-	PINMUX_IPSR_GPSR(IP11_31_30, ETH_CRS_DV),
-	PINMUX_IPSR_GPSR(IP11_31_30, AVB_LINK),
-	PINMUX_IPSR_MSEL(IP11_31_30, I2C2_SDA_C, SEL_I2C2_2),
-
-	/* IPSR12 */
-	PINMUX_IPSR_GPSR(IP12_1_0, ETH_RX_ER),
-	PINMUX_IPSR_GPSR(IP12_1_0, AVB_CRS),
-	PINMUX_IPSR_MSEL(IP12_1_0, I2C3_SCL, SEL_I2C3_0),
-	PINMUX_IPSR_MSEL(IP12_1_0, IIC0_SCL, SEL_IIC0_0),
-	PINMUX_IPSR_GPSR(IP12_3_2, ETH_RXD0),
-	PINMUX_IPSR_GPSR(IP12_3_2, AVB_PHY_INT),
-	PINMUX_IPSR_MSEL(IP12_3_2, I2C3_SDA, SEL_I2C3_0),
-	PINMUX_IPSR_MSEL(IP12_3_2, IIC0_SDA, SEL_IIC0_0),
-	PINMUX_IPSR_GPSR(IP12_6_4, ETH_RXD1),
-	PINMUX_IPSR_GPSR(IP12_6_4, AVB_GTXREFCLK),
-	PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
-	PINMUX_IPSR_MSEL(IP12_6_4, I2C2_SCL_D, SEL_I2C2_3),
-	PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
-	PINMUX_IPSR_GPSR(IP12_9_7, ETH_LINK),
-	PINMUX_IPSR_GPSR(IP12_9_7, AVB_TXD0),
-	PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
-	PINMUX_IPSR_MSEL(IP12_9_7, I2C2_SDA_D, SEL_I2C2_3),
-	PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
-	PINMUX_IPSR_GPSR(IP12_12_10, ETH_REFCLK),
-	PINMUX_IPSR_GPSR(IP12_12_10, AVB_TXD1),
-	PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
-	PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
-	PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
-	PINMUX_IPSR_GPSR(IP12_15_13, ETH_TXD1),
-	PINMUX_IPSR_GPSR(IP12_15_13, AVB_TXD2),
-	PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
-	PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
-	PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
-	PINMUX_IPSR_GPSR(IP12_17_16, ETH_TX_EN),
-	PINMUX_IPSR_GPSR(IP12_17_16, AVB_TXD3),
-	PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0),
-	PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
-	PINMUX_IPSR_GPSR(IP12_19_18, ETH_MAGIC),
-	PINMUX_IPSR_GPSR(IP12_19_18, AVB_TXD4),
-	PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2),
-	PINMUX_IPSR_GPSR(IP12_21_20, ETH_TXD0),
-	PINMUX_IPSR_GPSR(IP12_21_20, AVB_TXD5),
-	PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2),
-	PINMUX_IPSR_GPSR(IP12_23_22, ETH_MDC),
-	PINMUX_IPSR_GPSR(IP12_23_22, AVB_TXD6),
-	PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2),
-	PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
-	PINMUX_IPSR_GPSR(IP12_26_24, AVB_TXD7),
-	PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
-	PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1),
-	PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
-	PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
-	PINMUX_IPSR_GPSR(IP12_29_27, AVB_TX_EN),
-	PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
-	PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
-	PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
-
-	/* IPSR13 */
-	PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0),
-	PINMUX_IPSR_GPSR(IP13_2_0, AVB_TX_ER),
-	PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
-	PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1),
-	PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
-	PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
-	PINMUX_IPSR_GPSR(IP13_4_3, AVB_TX_CLK),
-	PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1),
-	PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
-	PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
-	PINMUX_IPSR_GPSR(IP13_6_5, AVB_COL),
-	PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1),
-	PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
-	PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
-	PINMUX_IPSR_GPSR(IP13_9_7, AVB_GTX_CLK),
-	PINMUX_IPSR_GPSR(IP13_9_7, PWM0_B),
-	PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1),
-	PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
-	PINMUX_IPSR_GPSR(IP13_10, SD0_CLK),
-	PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1),
-	PINMUX_IPSR_GPSR(IP13_11, SD0_CMD),
-	PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1),
-	PINMUX_IPSR_GPSR(IP13_12, SD0_DATA0),
-	PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1),
-	PINMUX_IPSR_GPSR(IP13_13, SD0_DATA1),
-	PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1),
-	PINMUX_IPSR_GPSR(IP13_14, SD0_DATA2),
-	PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1),
-	PINMUX_IPSR_GPSR(IP13_15, SD0_DATA3),
-	PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1),
-	PINMUX_IPSR_GPSR(IP13_18_16, SD0_CD),
-	PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1),
-	PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
-	PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
-	PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
-	PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2),
-	PINMUX_IPSR_GPSR(IP13_21_19, SD0_WP),
-	PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1),
-	PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1),
-	PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
-	PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
-	PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2),
-	PINMUX_IPSR_GPSR(IP13_22, SD1_CMD),
-	PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1),
-	PINMUX_IPSR_GPSR(IP13_24_23, SD1_DATA0),
-	PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
-	PINMUX_IPSR_GPSR(IP13_25, SD1_DATA1),
-	PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1),
-	PINMUX_IPSR_GPSR(IP13_26, SD1_DATA2),
-	PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1),
-	PINMUX_IPSR_GPSR(IP13_27, SD1_DATA3),
-	PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1),
-	PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD),
-	PINMUX_IPSR_GPSR(IP13_30_28, PWM0),
-	PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0),
-	PINMUX_IPSR_MSEL(IP13_30_28, I2C1_SCL_C, SEL_I2C1_2),
-
-	/* IPSR14 */
-	PINMUX_IPSR_GPSR(IP14_1_0, SD1_WP),
-	PINMUX_IPSR_GPSR(IP14_1_0, PWM1_B),
-	PINMUX_IPSR_MSEL(IP14_1_0, I2C1_SDA_C, SEL_I2C1_2),
-	PINMUX_IPSR_GPSR(IP14_2, SD2_CLK),
-	PINMUX_IPSR_GPSR(IP14_2, MMC_CLK),
-	PINMUX_IPSR_GPSR(IP14_3, SD2_CMD),
-	PINMUX_IPSR_GPSR(IP14_3, MMC_CMD),
-	PINMUX_IPSR_GPSR(IP14_4, SD2_DATA0),
-	PINMUX_IPSR_GPSR(IP14_4, MMC_D0),
-	PINMUX_IPSR_GPSR(IP14_5, SD2_DATA1),
-	PINMUX_IPSR_GPSR(IP14_5, MMC_D1),
-	PINMUX_IPSR_GPSR(IP14_6, SD2_DATA2),
-	PINMUX_IPSR_GPSR(IP14_6, MMC_D2),
-	PINMUX_IPSR_GPSR(IP14_7, SD2_DATA3),
-	PINMUX_IPSR_GPSR(IP14_7, MMC_D3),
-	PINMUX_IPSR_GPSR(IP14_10_8, SD2_CD),
-	PINMUX_IPSR_GPSR(IP14_10_8, MMC_D4),
-	PINMUX_IPSR_MSEL(IP14_10_8, IIC1_SCL_C, SEL_IIC1_2),
-	PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1),
-	PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
-	PINMUX_IPSR_GPSR(IP14_13_11, SD2_WP),
-	PINMUX_IPSR_GPSR(IP14_13_11, MMC_D5),
-	PINMUX_IPSR_MSEL(IP14_13_11, IIC1_SDA_C, SEL_IIC1_2),
-	PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1),
-	PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
-	PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
-	PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2),
-	PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0),
-	PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
-	PINMUX_IPSR_GPSR(IP14_16_14, VI1_G0_B),
-	PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
-	PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2),
-	PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
-	PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
-	PINMUX_IPSR_GPSR(IP14_19_17, VI1_G1_B),
-	PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
-	PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0),
-	PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
-	PINMUX_IPSR_GPSR(IP14_22_20, VI1_G2_B),
-	PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
-	PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0),
-	PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
-	PINMUX_IPSR_GPSR(IP14_25_23, VI1_G3_B),
-	PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
-	PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0),
-	PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0),
-	PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4),
-	PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
-	PINMUX_IPSR_MSEL(IP14_28_26, IIC0_SCL_C, SEL_IIC0_2),
-	PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B),
-	PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
-	PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0),
-	PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0),
-	PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4),
-	PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
-	PINMUX_IPSR_MSEL(IP14_31_29, IIC0_SDA_C, SEL_IIC0_2),
-	PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B),
-
-	/* IPSR15 */
-	PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0),
-	PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0),
-	PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
-	PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK),
-	PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0),
-	PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
-	PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0),
-	PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0),
-	PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
-	PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0),
-	PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
-	PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
-	PINMUX_IPSR_GPSR(IP15_8_6, PWM5_B),
-	PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
-	PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0),
-	PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2),
-	PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
-	PINMUX_IPSR_GPSR(IP15_11_9, PWM5),
-	PINMUX_IPSR_GPSR(IP15_11_9, VI1_G6_B),
-	PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
-	PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0),
-	PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2),
-	PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
-	PINMUX_IPSR_GPSR(IP15_14_12, PWM6),
-	PINMUX_IPSR_GPSR(IP15_14_12, VI1_G7_B),
-	PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
-	PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
-	PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
-	PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2),
-	PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0),
-	PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
-	PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
-	PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
-	PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2),
-	PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
-	PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0),
-	PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
-	PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
-	PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
-	PINMUX_IPSR_GPSR(IP15_23_21, TCLK2),
-	PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
-	PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0),
-	PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
-	PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
-	PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
-	PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
-	PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0),
-	PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
-	PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
-	PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
-	PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
-
-	/* IPSR16 */
-	PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
-	PINMUX_IPSR_GPSR(IP16_2_0, VI1_R0_B),
-	PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
-	PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
-	PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
-	PINMUX_IPSR_GPSR(IP16_5_3, VI1_R1_B),
-	PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2),
-	PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
-	PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
-	PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK),
-	PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
-	PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
-	PINMUX_IPSR_GPSR(IP16_9_8, SCIFB1_CTS_N),
-	PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG),
-	PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
-	PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
-	PINMUX_IPSR_GPSR(IP16_11_10, SCIFB1_RTS_N),
-	PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT),
-	PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	PINMUX_GPIO_GP_ALL(),
-};
-
-/* - ADI -------------------------------------------------------------------- */
-static const unsigned int adi_common_pins[] = {
-	/* ADIDATA, ADICS/SAMP, ADICLK */
-	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
-};
-static const unsigned int adi_common_mux[] = {
-	/* ADIDATA, ADICS/SAMP, ADICLK */
-	ADIDATA_MARK, ADICS_SAMP_MARK, ADICLK_MARK,
-};
-static const unsigned int adi_chsel0_pins[] = {
-	/* ADICHS 0 */
-	RCAR_GP_PIN(6, 27),
-};
-static const unsigned int adi_chsel0_mux[] = {
-	/* ADICHS 0 */
-	ADICHS0_MARK,
-};
-static const unsigned int adi_chsel1_pins[] = {
-	/* ADICHS 1 */
-	RCAR_GP_PIN(6, 28),
-};
-static const unsigned int adi_chsel1_mux[] = {
-	/* ADICHS 1 */
-	ADICHS1_MARK,
-};
-static const unsigned int adi_chsel2_pins[] = {
-	/* ADICHS 2 */
-	RCAR_GP_PIN(6, 29),
-};
-static const unsigned int adi_chsel2_mux[] = {
-	/* ADICHS 2 */
-	ADICHS2_MARK,
-};
-static const unsigned int adi_common_b_pins[] = {
-	/* ADIDATA B, ADICS/SAMP B, ADICLK B */
-	RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
-};
-static const unsigned int adi_common_b_mux[] = {
-	/* ADIDATA B, ADICS/SAMP B, ADICLK B */
-	ADIDATA_B_MARK, ADICS_SAMP_B_MARK, ADICLK_B_MARK,
-};
-static const unsigned int adi_chsel0_b_pins[] = {
-	/* ADICHS B 0 */
-	RCAR_GP_PIN(5, 28),
-};
-static const unsigned int adi_chsel0_b_mux[] = {
-	/* ADICHS B 0 */
-	ADICHS0_B_MARK,
-};
-static const unsigned int adi_chsel1_b_pins[] = {
-	/* ADICHS B 1 */
-	RCAR_GP_PIN(5, 29),
-};
-static const unsigned int adi_chsel1_b_mux[] = {
-	/* ADICHS B 1 */
-	ADICHS1_B_MARK,
-};
-static const unsigned int adi_chsel2_b_pins[] = {
-	/* ADICHS B 2 */
-	RCAR_GP_PIN(5, 30),
-};
-static const unsigned int adi_chsel2_b_mux[] = {
-	/* ADICHS B 2 */
-	ADICHS2_B_MARK,
-};
-
-/* - Audio Clock ------------------------------------------------------------ */
-static const unsigned int audio_clk_a_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(2, 28),
-};
-
-static const unsigned int audio_clk_a_mux[] = {
-	AUDIO_CLKA_MARK,
-};
-
-static const unsigned int audio_clk_b_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(2, 29),
-};
-
-static const unsigned int audio_clk_b_mux[] = {
-	AUDIO_CLKB_MARK,
-};
-
-static const unsigned int audio_clk_b_b_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(7, 20),
-};
-
-static const unsigned int audio_clk_b_b_mux[] = {
-	AUDIO_CLKB_B_MARK,
-};
-
-static const unsigned int audio_clk_c_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(2, 30),
-};
-
-static const unsigned int audio_clk_c_mux[] = {
-	AUDIO_CLKC_MARK,
-};
-
-static const unsigned int audio_clkout_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(2, 31),
-};
-
-static const unsigned int audio_clkout_mux[] = {
-	AUDIO_CLKOUT_MARK,
-};
-
-/* - AVB -------------------------------------------------------------------- */
-static const unsigned int avb_link_pins[] = {
-	RCAR_GP_PIN(5, 14),
-};
-static const unsigned int avb_link_mux[] = {
-	AVB_LINK_MARK,
-};
-static const unsigned int avb_magic_pins[] = {
-	RCAR_GP_PIN(5, 11),
-};
-static const unsigned int avb_magic_mux[] = {
-	AVB_MAGIC_MARK,
-};
-static const unsigned int avb_phy_int_pins[] = {
-	RCAR_GP_PIN(5, 16),
-};
-static const unsigned int avb_phy_int_mux[] = {
-	AVB_PHY_INT_MARK,
-};
-static const unsigned int avb_mdio_pins[] = {
-	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 9),
-};
-static const unsigned int avb_mdio_mux[] = {
-	AVB_MDC_MARK, AVB_MDIO_MARK,
-};
-static const unsigned int avb_mii_pins[] = {
-	RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
-	RCAR_GP_PIN(5, 21),
-
-	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-	RCAR_GP_PIN(5, 3),
-
-	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
-	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
-	RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
-};
-static const unsigned int avb_mii_mux[] = {
-	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
-	AVB_TXD3_MARK,
-
-	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
-	AVB_RXD3_MARK,
-
-	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
-	AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
-	AVB_TX_CLK_MARK, AVB_COL_MARK,
-};
-static const unsigned int avb_gmii_pins[] = {
-	RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
-	RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
-	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
-
-	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
-	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
-
-	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
-	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17),
-	RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28),
-	RCAR_GP_PIN(5, 29),
-};
-static const unsigned int avb_gmii_mux[] = {
-	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
-	AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
-	AVB_TXD6_MARK, AVB_TXD7_MARK,
-
-	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
-	AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
-	AVB_RXD6_MARK, AVB_RXD7_MARK,
-
-	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
-	AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
-	AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
-	AVB_COL_MARK,
-};
-
-/* - CAN -------------------------------------------------------------------- */
-
-static const unsigned int can0_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
-};
-
-static const unsigned int can0_data_mux[] = {
-	CAN0_TX_MARK, CAN0_RX_MARK,
-};
-
-static const unsigned int can0_data_b_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3),
-};
-
-static const unsigned int can0_data_b_mux[] = {
-	CAN0_TX_B_MARK, CAN0_RX_B_MARK,
-};
-
-static const unsigned int can0_data_c_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
-};
-
-static const unsigned int can0_data_c_mux[] = {
-	CAN0_TX_C_MARK,	CAN0_RX_C_MARK,
-};
-
-static const unsigned int can0_data_d_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27),
-};
-
-static const unsigned int can0_data_d_mux[] = {
-	CAN0_TX_D_MARK, CAN0_RX_D_MARK,
-};
-
-static const unsigned int can0_data_e_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28),
-};
-
-static const unsigned int can0_data_e_mux[] = {
-	CAN0_TX_E_MARK, CAN0_RX_E_MARK,
-};
-
-static const unsigned int can0_data_f_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
-};
-
-static const unsigned int can0_data_f_mux[] = {
-	CAN0_TX_F_MARK, CAN0_RX_F_MARK,
-};
-
-static const unsigned int can1_data_pins[] = {
-	/* TX, RX */
-	 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20),
-};
-
-static const unsigned int can1_data_mux[] = {
-	CAN1_TX_MARK, CAN1_RX_MARK,
-};
-
-static const unsigned int can1_data_b_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
-};
-
-static const unsigned int can1_data_b_mux[] = {
-	CAN1_TX_B_MARK, CAN1_RX_B_MARK,
-};
-
-static const unsigned int can1_data_c_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19),
-};
-
-static const unsigned int can1_data_c_mux[] = {
-	CAN1_TX_C_MARK, CAN1_RX_C_MARK,
-};
-
-static const unsigned int can1_data_d_pins[] = {
-	/* TX, RX */
-	 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31),
-};
-
-static const unsigned int can1_data_d_mux[] = {
-	CAN1_TX_D_MARK, CAN1_RX_D_MARK,
-};
-
-static const unsigned int can_clk_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(7, 2),
-};
-
-static const unsigned int can_clk_mux[] = {
-	CAN_CLK_MARK,
-};
-
-static const unsigned int can_clk_b_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(5, 21),
-};
-
-static const unsigned int can_clk_b_mux[] = {
-	CAN_CLK_B_MARK,
-};
-
-static const unsigned int can_clk_c_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(4, 30),
-};
-
-static const unsigned int can_clk_c_mux[] = {
-	CAN_CLK_C_MARK,
-};
-
-static const unsigned int can_clk_d_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(7, 19),
-};
-
-static const unsigned int can_clk_d_mux[] = {
-	CAN_CLK_D_MARK,
-};
-
-/* - DU --------------------------------------------------------------------- */
-static const unsigned int du_rgb666_pins[] = {
-	/* R[7:2], G[7:2], B[7:2] */
-	RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
-	RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
-	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
-	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
-	RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
-	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
-};
-static const unsigned int du_rgb666_mux[] = {
-	DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
-	DU1_DR3_MARK, DU1_DR2_MARK,
-	DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
-	DU1_DG3_MARK, DU1_DG2_MARK,
-	DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
-	DU1_DB3_MARK, DU1_DB2_MARK,
-};
-static const unsigned int du_rgb888_pins[] = {
-	/* R[7:0], G[7:0], B[7:0] */
-	RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
-	RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
-	RCAR_GP_PIN(3, 1),  RCAR_GP_PIN(3, 0),
-	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
-	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
-	RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 8),
-	RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
-	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
-	RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
-};
-static const unsigned int du_rgb888_mux[] = {
-	DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
-	DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
-	DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
-	DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
-	DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
-	DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
-};
-static const unsigned int du_clk_out_0_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(3, 25),
-};
-static const unsigned int du_clk_out_0_mux[] = {
-	DU1_DOTCLKOUT0_MARK
-};
-static const unsigned int du_clk_out_1_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(3, 26),
-};
-static const unsigned int du_clk_out_1_mux[] = {
-	DU1_DOTCLKOUT1_MARK
-};
-static const unsigned int du_sync_pins[] = {
-	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
-	RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
-};
-static const unsigned int du_sync_mux[] = {
-	DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
-};
-static const unsigned int du_oddf_pins[] = {
-	/* EXDISP/EXODDF/EXCDE */
-	RCAR_GP_PIN(3, 29),
-};
-static const unsigned int du_oddf_mux[] = {
-	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
-};
-static const unsigned int du_cde_pins[] = {
-	/* CDE */
-	RCAR_GP_PIN(3, 31),
-};
-static const unsigned int du_cde_mux[] = {
-	DU1_CDE_MARK,
-};
-static const unsigned int du_disp_pins[] = {
-	/* DISP */
-	RCAR_GP_PIN(3, 30),
-};
-static const unsigned int du_disp_mux[] = {
-	DU1_DISP_MARK,
-};
-static const unsigned int du0_clk_in_pins[] = {
-	/* CLKIN */
-	RCAR_GP_PIN(6, 31),
-};
-static const unsigned int du0_clk_in_mux[] = {
-	DU0_DOTCLKIN_MARK
-};
-static const unsigned int du1_clk_in_pins[] = {
-	/* CLKIN */
-	RCAR_GP_PIN(3, 24),
-};
-static const unsigned int du1_clk_in_mux[] = {
-	DU1_DOTCLKIN_MARK
-};
-static const unsigned int du1_clk_in_b_pins[] = {
-	/* CLKIN */
-	RCAR_GP_PIN(7, 19),
-};
-static const unsigned int du1_clk_in_b_mux[] = {
-	DU1_DOTCLKIN_B_MARK,
-};
-static const unsigned int du1_clk_in_c_pins[] = {
-	/* CLKIN */
-	RCAR_GP_PIN(7, 20),
-};
-static const unsigned int du1_clk_in_c_mux[] = {
-	DU1_DOTCLKIN_C_MARK,
-};
-/* - ETH -------------------------------------------------------------------- */
-static const unsigned int eth_link_pins[] = {
-	/* LINK */
-	RCAR_GP_PIN(5, 18),
-};
-static const unsigned int eth_link_mux[] = {
-	ETH_LINK_MARK,
-};
-static const unsigned int eth_magic_pins[] = {
-	/* MAGIC */
-	RCAR_GP_PIN(5, 22),
-};
-static const unsigned int eth_magic_mux[] = {
-	ETH_MAGIC_MARK,
-};
-static const unsigned int eth_mdio_pins[] = {
-	/* MDC, MDIO */
-	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
-};
-static const unsigned int eth_mdio_mux[] = {
-	ETH_MDC_MARK, ETH_MDIO_MARK,
-};
-static const unsigned int eth_rmii_pins[] = {
-	/* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
-	RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
-	RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
-	RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
-};
-static const unsigned int eth_rmii_mux[] = {
-	ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
-	ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
-};
-
-/* - HSCIF0 ----------------------------------------------------------------- */
-static const unsigned int hscif0_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
-};
-static const unsigned int hscif0_data_mux[] = {
-	HRX0_MARK, HTX0_MARK,
-};
-static const unsigned int hscif0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(7, 2),
-};
-static const unsigned int hscif0_clk_mux[] = {
-	HSCK0_MARK,
-};
-static const unsigned int hscif0_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
-};
-static const unsigned int hscif0_ctrl_mux[] = {
-	HRTS0_N_MARK, HCTS0_N_MARK,
-};
-static const unsigned int hscif0_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
-};
-static const unsigned int hscif0_data_b_mux[] = {
-	HRX0_B_MARK, HTX0_B_MARK,
-};
-static const unsigned int hscif0_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
-};
-static const unsigned int hscif0_ctrl_b_mux[] = {
-	HRTS0_N_B_MARK, HCTS0_N_B_MARK,
-};
-static const unsigned int hscif0_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-};
-static const unsigned int hscif0_data_c_mux[] = {
-	HRX0_C_MARK, HTX0_C_MARK,
-};
-static const unsigned int hscif0_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 31),
-};
-static const unsigned int hscif0_clk_c_mux[] = {
-	HSCK0_C_MARK,
-};
-/* - HSCIF1 ----------------------------------------------------------------- */
-static const unsigned int hscif1_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
-};
-static const unsigned int hscif1_data_mux[] = {
-	HRX1_MARK, HTX1_MARK,
-};
-static const unsigned int hscif1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(7, 7),
-};
-static const unsigned int hscif1_clk_mux[] = {
-	HSCK1_MARK,
-};
-static const unsigned int hscif1_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
-};
-static const unsigned int hscif1_ctrl_mux[] = {
-	HRTS1_N_MARK, HCTS1_N_MARK,
-};
-static const unsigned int hscif1_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
-};
-static const unsigned int hscif1_data_b_mux[] = {
-	HRX1_B_MARK, HTX1_B_MARK,
-};
-static const unsigned int hscif1_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
-};
-static const unsigned int hscif1_data_c_mux[] = {
-	HRX1_C_MARK, HTX1_C_MARK,
-};
-static const unsigned int hscif1_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(7, 16),
-};
-static const unsigned int hscif1_clk_c_mux[] = {
-	HSCK1_C_MARK,
-};
-static const unsigned int hscif1_ctrl_c_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
-};
-static const unsigned int hscif1_ctrl_c_mux[] = {
-	HRTS1_N_C_MARK, HCTS1_N_C_MARK,
-};
-static const unsigned int hscif1_data_d_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
-};
-static const unsigned int hscif1_data_d_mux[] = {
-	HRX1_D_MARK, HTX1_D_MARK,
-};
-static const unsigned int hscif1_data_e_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
-};
-static const unsigned int hscif1_data_e_mux[] = {
-	HRX1_C_MARK, HTX1_C_MARK,
-};
-static const unsigned int hscif1_clk_e_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 6),
-};
-static const unsigned int hscif1_clk_e_mux[] = {
-	HSCK1_E_MARK,
-};
-static const unsigned int hscif1_ctrl_e_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
-};
-static const unsigned int hscif1_ctrl_e_mux[] = {
-	HRTS1_N_E_MARK, HCTS1_N_E_MARK,
-};
-/* - HSCIF2 ----------------------------------------------------------------- */
-static const unsigned int hscif2_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
-};
-static const unsigned int hscif2_data_mux[] = {
-	HRX2_MARK, HTX2_MARK,
-};
-static const unsigned int hscif2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 15),
-};
-static const unsigned int hscif2_clk_mux[] = {
-	HSCK2_MARK,
-};
-static const unsigned int hscif2_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
-};
-static const unsigned int hscif2_ctrl_mux[] = {
-	HRTS2_N_MARK, HCTS2_N_MARK,
-};
-static const unsigned int hscif2_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22),
-};
-static const unsigned int hscif2_data_b_mux[] = {
-	HRX2_B_MARK, HTX2_B_MARK,
-};
-static const unsigned int hscif2_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21),
-};
-static const unsigned int hscif2_ctrl_b_mux[] = {
-	HRTS2_N_B_MARK, HCTS2_N_B_MARK,
-};
-static const unsigned int hscif2_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-};
-static const unsigned int hscif2_data_c_mux[] = {
-	HRX2_C_MARK, HTX2_C_MARK,
-};
-static const unsigned int hscif2_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 31),
-};
-static const unsigned int hscif2_clk_c_mux[] = {
-	HSCK2_C_MARK,
-};
-static const unsigned int hscif2_data_d_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31),
-};
-static const unsigned int hscif2_data_d_mux[] = {
-	HRX2_B_MARK, HTX2_D_MARK,
-};
-/* - I2C0 ------------------------------------------------------------------- */
-static const unsigned int i2c0_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
-};
-static const unsigned int i2c0_mux[] = {
-	I2C0_SCL_MARK, I2C0_SDA_MARK,
-};
-static const unsigned int i2c0_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-};
-static const unsigned int i2c0_b_mux[] = {
-	I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
-};
-static const unsigned int i2c0_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
-};
-static const unsigned int i2c0_c_mux[] = {
-	I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
-};
-/* - I2C1 ------------------------------------------------------------------- */
-static const unsigned int i2c1_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
-};
-static const unsigned int i2c1_mux[] = {
-	I2C1_SCL_MARK, I2C1_SDA_MARK,
-};
-static const unsigned int i2c1_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-};
-static const unsigned int i2c1_b_mux[] = {
-	I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
-};
-static const unsigned int i2c1_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
-};
-static const unsigned int i2c1_c_mux[] = {
-	I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
-};
-static const unsigned int i2c1_d_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
-};
-static const unsigned int i2c1_d_mux[] = {
-	I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
-};
-static const unsigned int i2c1_e_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
-};
-static const unsigned int i2c1_e_mux[] = {
-	I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
-};
-/* - I2C2 ------------------------------------------------------------------- */
-static const unsigned int i2c2_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-};
-static const unsigned int i2c2_mux[] = {
-	I2C2_SCL_MARK, I2C2_SDA_MARK,
-};
-static const unsigned int i2c2_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
-};
-static const unsigned int i2c2_b_mux[] = {
-	I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
-};
-static const unsigned int i2c2_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
-};
-static const unsigned int i2c2_c_mux[] = {
-	I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
-};
-static const unsigned int i2c2_d_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
-};
-static const unsigned int i2c2_d_mux[] = {
-	I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
-};
-/* - I2C3 ------------------------------------------------------------------- */
-static const unsigned int i2c3_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
-};
-static const unsigned int i2c3_mux[] = {
-	I2C3_SCL_MARK, I2C3_SDA_MARK,
-};
-static const unsigned int i2c3_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
-};
-static const unsigned int i2c3_b_mux[] = {
-	I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
-};
-static const unsigned int i2c3_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
-};
-static const unsigned int i2c3_c_mux[] = {
-	I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
-};
-static const unsigned int i2c3_d_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
-};
-static const unsigned int i2c3_d_mux[] = {
-	I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
-};
-/* - I2C4 ------------------------------------------------------------------- */
-static const unsigned int i2c4_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
-};
-static const unsigned int i2c4_mux[] = {
-	I2C4_SCL_MARK, I2C4_SDA_MARK,
-};
-static const unsigned int i2c4_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
-};
-static const unsigned int i2c4_b_mux[] = {
-	I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
-};
-static const unsigned int i2c4_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
-};
-static const unsigned int i2c4_c_mux[] = {
-	I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
-};
-/* - I2C7 ------------------------------------------------------------------- */
-static const unsigned int i2c7_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
-};
-static const unsigned int i2c7_mux[] = {
-	IIC0_SCL_MARK, IIC0_SDA_MARK,
-};
-static const unsigned int i2c7_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-};
-static const unsigned int i2c7_b_mux[] = {
-	IIC0_SCL_B_MARK, IIC0_SDA_B_MARK,
-};
-static const unsigned int i2c7_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
-};
-static const unsigned int i2c7_c_mux[] = {
-	IIC0_SCL_C_MARK, IIC0_SDA_C_MARK,
-};
-/* - I2C8 ------------------------------------------------------------------- */
-static const unsigned int i2c8_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
-};
-static const unsigned int i2c8_mux[] = {
-	IIC1_SCL_MARK, IIC1_SDA_MARK,
-};
-static const unsigned int i2c8_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-};
-static const unsigned int i2c8_b_mux[] = {
-	IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
-};
-static const unsigned int i2c8_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
-};
-static const unsigned int i2c8_c_mux[] = {
-	IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
-};
-/* - INTC ------------------------------------------------------------------- */
-static const unsigned int intc_irq0_pins[] = {
-	/* IRQ */
-	RCAR_GP_PIN(7, 10),
-};
-static const unsigned int intc_irq0_mux[] = {
-	IRQ0_MARK,
-};
-static const unsigned int intc_irq1_pins[] = {
-	/* IRQ */
-	RCAR_GP_PIN(7, 11),
-};
-static const unsigned int intc_irq1_mux[] = {
-	IRQ1_MARK,
-};
-static const unsigned int intc_irq2_pins[] = {
-	/* IRQ */
-	RCAR_GP_PIN(7, 12),
-};
-static const unsigned int intc_irq2_mux[] = {
-	IRQ2_MARK,
-};
-static const unsigned int intc_irq3_pins[] = {
-	/* IRQ */
-	RCAR_GP_PIN(7, 13),
-};
-static const unsigned int intc_irq3_mux[] = {
-	IRQ3_MARK,
-};
-/* - MLB+ ------------------------------------------------------------------- */
-static const unsigned int mlb_3pin_pins[] = {
-	RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
-};
-static const unsigned int mlb_3pin_mux[] = {
-	MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
-};
-/* - MMCIF ------------------------------------------------------------------ */
-static const unsigned int mmc_data1_pins[] = {
-	/* D[0] */
-	RCAR_GP_PIN(6, 18),
-};
-static const unsigned int mmc_data1_mux[] = {
-	MMC_D0_MARK,
-};
-static const unsigned int mmc_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
-	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
-};
-static const unsigned int mmc_data4_mux[] = {
-	MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
-};
-static const unsigned int mmc_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
-	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
-	RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
-	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
-};
-static const unsigned int mmc_data8_mux[] = {
-	MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
-	MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
-};
-static const unsigned int mmc_data8_b_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
-	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
-	RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
-	RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
-};
-static const unsigned int mmc_data8_b_mux[] = {
-	MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
-	MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK,
-};
-static const unsigned int mmc_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
-};
-static const unsigned int mmc_ctrl_mux[] = {
-	MMC_CLK_MARK, MMC_CMD_MARK,
-};
-/* - MSIOF0 ----------------------------------------------------------------- */
-static const unsigned int msiof0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 24),
-};
-static const unsigned int msiof0_clk_mux[] = {
-	MSIOF0_SCK_MARK,
-};
-static const unsigned int msiof0_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(6, 25),
-};
-static const unsigned int msiof0_sync_mux[] = {
-	MSIOF0_SYNC_MARK,
-};
-static const unsigned int msiof0_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(6, 28),
-};
-static const unsigned int msiof0_ss1_mux[] = {
-	MSIOF0_SS1_MARK,
-};
-static const unsigned int msiof0_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(6, 29),
-};
-static const unsigned int msiof0_ss2_mux[] = {
-	MSIOF0_SS2_MARK,
-};
-static const unsigned int msiof0_rx_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(6, 27),
-};
-static const unsigned int msiof0_rx_mux[] = {
-	MSIOF0_RXD_MARK,
-};
-static const unsigned int msiof0_tx_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(6, 26),
-};
-static const unsigned int msiof0_tx_mux[] = {
-	MSIOF0_TXD_MARK,
-};
-
-static const unsigned int msiof0_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 16),
-};
-static const unsigned int msiof0_clk_b_mux[] = {
-	MSIOF0_SCK_B_MARK,
-};
-static const unsigned int msiof0_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 17),
-};
-static const unsigned int msiof0_sync_b_mux[] = {
-	MSIOF0_SYNC_B_MARK,
-};
-static const unsigned int msiof0_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 18),
-};
-static const unsigned int msiof0_ss1_b_mux[] = {
-	MSIOF0_SS1_B_MARK,
-};
-static const unsigned int msiof0_ss2_b_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 19),
-};
-static const unsigned int msiof0_ss2_b_mux[] = {
-	MSIOF0_SS2_B_MARK,
-};
-static const unsigned int msiof0_rx_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 21),
-};
-static const unsigned int msiof0_rx_b_mux[] = {
-	MSIOF0_RXD_B_MARK,
-};
-static const unsigned int msiof0_tx_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 20),
-};
-static const unsigned int msiof0_tx_b_mux[] = {
-	MSIOF0_TXD_B_MARK,
-};
-
-static const unsigned int msiof0_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 26),
-};
-static const unsigned int msiof0_clk_c_mux[] = {
-	MSIOF0_SCK_C_MARK,
-};
-static const unsigned int msiof0_sync_c_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(5, 25),
-};
-static const unsigned int msiof0_sync_c_mux[] = {
-	MSIOF0_SYNC_C_MARK,
-};
-static const unsigned int msiof0_ss1_c_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(5, 27),
-};
-static const unsigned int msiof0_ss1_c_mux[] = {
-	MSIOF0_SS1_C_MARK,
-};
-static const unsigned int msiof0_ss2_c_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(5, 28),
-};
-static const unsigned int msiof0_ss2_c_mux[] = {
-	MSIOF0_SS2_C_MARK,
-};
-static const unsigned int msiof0_rx_c_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 29),
-};
-static const unsigned int msiof0_rx_c_mux[] = {
-	MSIOF0_RXD_C_MARK,
-};
-static const unsigned int msiof0_tx_c_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(5, 30),
-};
-static const unsigned int msiof0_tx_c_mux[] = {
-	MSIOF0_TXD_C_MARK,
-};
-/* - MSIOF1 ----------------------------------------------------------------- */
-static const unsigned int msiof1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 22),
-};
-static const unsigned int msiof1_clk_mux[] = {
-	MSIOF1_SCK_MARK,
-};
-static const unsigned int msiof1_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 23),
-};
-static const unsigned int msiof1_sync_mux[] = {
-	MSIOF1_SYNC_MARK,
-};
-static const unsigned int msiof1_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 24),
-};
-static const unsigned int msiof1_ss1_mux[] = {
-	MSIOF1_SS1_MARK,
-};
-static const unsigned int msiof1_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 25),
-};
-static const unsigned int msiof1_ss2_mux[] = {
-	MSIOF1_SS2_MARK,
-};
-static const unsigned int msiof1_rx_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 27),
-};
-static const unsigned int msiof1_rx_mux[] = {
-	MSIOF1_RXD_MARK,
-};
-static const unsigned int msiof1_tx_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 26),
-};
-static const unsigned int msiof1_tx_mux[] = {
-	MSIOF1_TXD_MARK,
-};
-
-static const unsigned int msiof1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 29),
-};
-static const unsigned int msiof1_clk_b_mux[] = {
-	MSIOF1_SCK_B_MARK,
-};
-static const unsigned int msiof1_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(2, 30),
-};
-static const unsigned int msiof1_sync_b_mux[] = {
-	MSIOF1_SYNC_B_MARK,
-};
-static const unsigned int msiof1_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(2, 31),
-};
-static const unsigned int msiof1_ss1_b_mux[] = {
-	MSIOF1_SS1_B_MARK,
-};
-static const unsigned int msiof1_ss2_b_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(7, 16),
-};
-static const unsigned int msiof1_ss2_b_mux[] = {
-	MSIOF1_SS2_B_MARK,
-};
-static const unsigned int msiof1_rx_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(7, 18),
-};
-static const unsigned int msiof1_rx_b_mux[] = {
-	MSIOF1_RXD_B_MARK,
-};
-static const unsigned int msiof1_tx_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(7, 17),
-};
-static const unsigned int msiof1_tx_b_mux[] = {
-	MSIOF1_TXD_B_MARK,
-};
-
-static const unsigned int msiof1_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 15),
-};
-static const unsigned int msiof1_clk_c_mux[] = {
-	MSIOF1_SCK_C_MARK,
-};
-static const unsigned int msiof1_sync_c_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(2, 16),
-};
-static const unsigned int msiof1_sync_c_mux[] = {
-	MSIOF1_SYNC_C_MARK,
-};
-static const unsigned int msiof1_rx_c_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(2, 18),
-};
-static const unsigned int msiof1_rx_c_mux[] = {
-	MSIOF1_RXD_C_MARK,
-};
-static const unsigned int msiof1_tx_c_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(2, 17),
-};
-static const unsigned int msiof1_tx_c_mux[] = {
-	MSIOF1_TXD_C_MARK,
-};
-
-static const unsigned int msiof1_clk_d_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 28),
-};
-static const unsigned int msiof1_clk_d_mux[] = {
-	MSIOF1_SCK_D_MARK,
-};
-static const unsigned int msiof1_sync_d_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 30),
-};
-static const unsigned int msiof1_sync_d_mux[] = {
-	MSIOF1_SYNC_D_MARK,
-};
-static const unsigned int msiof1_ss1_d_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 29),
-};
-static const unsigned int msiof1_ss1_d_mux[] = {
-	MSIOF1_SS1_D_MARK,
-};
-static const unsigned int msiof1_rx_d_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 27),
-};
-static const unsigned int msiof1_rx_d_mux[] = {
-	MSIOF1_RXD_D_MARK,
-};
-static const unsigned int msiof1_tx_d_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 26),
-};
-static const unsigned int msiof1_tx_d_mux[] = {
-	MSIOF1_TXD_D_MARK,
-};
-
-static const unsigned int msiof1_clk_e_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 18),
-};
-static const unsigned int msiof1_clk_e_mux[] = {
-	MSIOF1_SCK_E_MARK,
-};
-static const unsigned int msiof1_sync_e_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int msiof1_sync_e_mux[] = {
-	MSIOF1_SYNC_E_MARK,
-};
-static const unsigned int msiof1_rx_e_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 17),
-};
-static const unsigned int msiof1_rx_e_mux[] = {
-	MSIOF1_RXD_E_MARK,
-};
-static const unsigned int msiof1_tx_e_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(5, 20),
-};
-static const unsigned int msiof1_tx_e_mux[] = {
-	MSIOF1_TXD_E_MARK,
-};
-/* - MSIOF2 ----------------------------------------------------------------- */
-static const unsigned int msiof2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 13),
-};
-static const unsigned int msiof2_clk_mux[] = {
-	MSIOF2_SCK_MARK,
-};
-static const unsigned int msiof2_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 14),
-};
-static const unsigned int msiof2_sync_mux[] = {
-	MSIOF2_SYNC_MARK,
-};
-static const unsigned int msiof2_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(1, 17),
-};
-static const unsigned int msiof2_ss1_mux[] = {
-	MSIOF2_SS1_MARK,
-};
-static const unsigned int msiof2_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(1, 18),
-};
-static const unsigned int msiof2_ss2_mux[] = {
-	MSIOF2_SS2_MARK,
-};
-static const unsigned int msiof2_rx_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 16),
-};
-static const unsigned int msiof2_rx_mux[] = {
-	MSIOF2_RXD_MARK,
-};
-static const unsigned int msiof2_tx_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 15),
-};
-static const unsigned int msiof2_tx_mux[] = {
-	MSIOF2_TXD_MARK,
-};
-
-static const unsigned int msiof2_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 0),
-};
-static const unsigned int msiof2_clk_b_mux[] = {
-	MSIOF2_SCK_B_MARK,
-};
-static const unsigned int msiof2_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(3, 1),
-};
-static const unsigned int msiof2_sync_b_mux[] = {
-	MSIOF2_SYNC_B_MARK,
-};
-static const unsigned int msiof2_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(3, 8),
-};
-static const unsigned int msiof2_ss1_b_mux[] = {
-	MSIOF2_SS1_B_MARK,
-};
-static const unsigned int msiof2_ss2_b_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(3, 9),
-};
-static const unsigned int msiof2_ss2_b_mux[] = {
-	MSIOF2_SS2_B_MARK,
-};
-static const unsigned int msiof2_rx_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(3, 17),
-};
-static const unsigned int msiof2_rx_b_mux[] = {
-	MSIOF2_RXD_B_MARK,
-};
-static const unsigned int msiof2_tx_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(3, 16),
-};
-static const unsigned int msiof2_tx_b_mux[] = {
-	MSIOF2_TXD_B_MARK,
-};
-
-static const unsigned int msiof2_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 2),
-};
-static const unsigned int msiof2_clk_c_mux[] = {
-	MSIOF2_SCK_C_MARK,
-};
-static const unsigned int msiof2_sync_c_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(2, 3),
-};
-static const unsigned int msiof2_sync_c_mux[] = {
-	MSIOF2_SYNC_C_MARK,
-};
-static const unsigned int msiof2_rx_c_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(2, 5),
-};
-static const unsigned int msiof2_rx_c_mux[] = {
-	MSIOF2_RXD_C_MARK,
-};
-static const unsigned int msiof2_tx_c_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(2, 4),
-};
-static const unsigned int msiof2_tx_c_mux[] = {
-	MSIOF2_TXD_C_MARK,
-};
-
-static const unsigned int msiof2_clk_d_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 14),
-};
-static const unsigned int msiof2_clk_d_mux[] = {
-	MSIOF2_SCK_D_MARK,
-};
-static const unsigned int msiof2_sync_d_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(2, 15),
-};
-static const unsigned int msiof2_sync_d_mux[] = {
-	MSIOF2_SYNC_D_MARK,
-};
-static const unsigned int msiof2_ss1_d_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(2, 17),
-};
-static const unsigned int msiof2_ss1_d_mux[] = {
-	MSIOF2_SS1_D_MARK,
-};
-static const unsigned int msiof2_ss2_d_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(2, 19),
-};
-static const unsigned int msiof2_ss2_d_mux[] = {
-	MSIOF2_SS2_D_MARK,
-};
-static const unsigned int msiof2_rx_d_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(2, 18),
-};
-static const unsigned int msiof2_rx_d_mux[] = {
-	MSIOF2_RXD_D_MARK,
-};
-static const unsigned int msiof2_tx_d_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(2, 16),
-};
-static const unsigned int msiof2_tx_d_mux[] = {
-	MSIOF2_TXD_D_MARK,
-};
-
-static const unsigned int msiof2_clk_e_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(7, 15),
-};
-static const unsigned int msiof2_clk_e_mux[] = {
-	MSIOF2_SCK_E_MARK,
-};
-static const unsigned int msiof2_sync_e_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(7, 16),
-};
-static const unsigned int msiof2_sync_e_mux[] = {
-	MSIOF2_SYNC_E_MARK,
-};
-static const unsigned int msiof2_rx_e_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(7, 14),
-};
-static const unsigned int msiof2_rx_e_mux[] = {
-	MSIOF2_RXD_E_MARK,
-};
-static const unsigned int msiof2_tx_e_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(7, 13),
-};
-static const unsigned int msiof2_tx_e_mux[] = {
-	MSIOF2_TXD_E_MARK,
-};
-/* - PWM -------------------------------------------------------------------- */
-static const unsigned int pwm0_pins[] = {
-	RCAR_GP_PIN(6, 14),
-};
-static const unsigned int pwm0_mux[] = {
-	PWM0_MARK,
-};
-static const unsigned int pwm0_b_pins[] = {
-	RCAR_GP_PIN(5, 30),
-};
-static const unsigned int pwm0_b_mux[] = {
-	PWM0_B_MARK,
-};
-static const unsigned int pwm1_pins[] = {
-	RCAR_GP_PIN(1, 17),
-};
-static const unsigned int pwm1_mux[] = {
-	PWM1_MARK,
-};
-static const unsigned int pwm1_b_pins[] = {
-	RCAR_GP_PIN(6, 15),
-};
-static const unsigned int pwm1_b_mux[] = {
-	PWM1_B_MARK,
-};
-static const unsigned int pwm2_pins[] = {
-	RCAR_GP_PIN(1, 18),
-};
-static const unsigned int pwm2_mux[] = {
-	PWM2_MARK,
-};
-static const unsigned int pwm2_b_pins[] = {
-	RCAR_GP_PIN(0, 16),
-};
-static const unsigned int pwm2_b_mux[] = {
-	PWM2_B_MARK,
-};
-static const unsigned int pwm3_pins[] = {
-	RCAR_GP_PIN(1, 24),
-};
-static const unsigned int pwm3_mux[] = {
-	PWM3_MARK,
-};
-static const unsigned int pwm4_pins[] = {
-	RCAR_GP_PIN(3, 26),
-};
-static const unsigned int pwm4_mux[] = {
-	PWM4_MARK,
-};
-static const unsigned int pwm4_b_pins[] = {
-	RCAR_GP_PIN(3, 31),
-};
-static const unsigned int pwm4_b_mux[] = {
-	PWM4_B_MARK,
-};
-static const unsigned int pwm5_pins[] = {
-	RCAR_GP_PIN(7, 21),
-};
-static const unsigned int pwm5_mux[] = {
-	PWM5_MARK,
-};
-static const unsigned int pwm5_b_pins[] = {
-	RCAR_GP_PIN(7, 20),
-};
-static const unsigned int pwm5_b_mux[] = {
-	PWM5_B_MARK,
-};
-static const unsigned int pwm6_pins[] = {
-	RCAR_GP_PIN(7, 22),
-};
-static const unsigned int pwm6_mux[] = {
-	PWM6_MARK,
-};
-/* - QSPI ------------------------------------------------------------------- */
-static const unsigned int qspi_ctrl_pins[] = {
-	/* SPCLK, SSL */
-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
-};
-static const unsigned int qspi_ctrl_mux[] = {
-	SPCLK_MARK, SSL_MARK,
-};
-static const unsigned int qspi_data2_pins[] = {
-	/* MOSI_IO0, MISO_IO1 */
-	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
-};
-static const unsigned int qspi_data2_mux[] = {
-	MOSI_IO0_MARK, MISO_IO1_MARK,
-};
-static const unsigned int qspi_data4_pins[] = {
-	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
-	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-	RCAR_GP_PIN(1, 8),
-};
-static const unsigned int qspi_data4_mux[] = {
-	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
-};
-
-static const unsigned int qspi_ctrl_b_pins[] = {
-	/* SPCLK, SSL */
-	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
-};
-static const unsigned int qspi_ctrl_b_mux[] = {
-	SPCLK_B_MARK, SSL_B_MARK,
-};
-static const unsigned int qspi_data2_b_pins[] = {
-	/* MOSI_IO0, MISO_IO1 */
-	RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
-};
-static const unsigned int qspi_data2_b_mux[] = {
-	MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
-};
-static const unsigned int qspi_data4_b_pins[] = {
-	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
-	RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
-	RCAR_GP_PIN(6, 4),
-};
-static const unsigned int qspi_data4_b_mux[] = {
-	MOSI_IO0_B_MARK, MISO_IO1_B_MARK, IO2_B_MARK, IO3_B_MARK,
-};
-/* - SCIF0 ------------------------------------------------------------------ */
-static const unsigned int scif0_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
-};
-static const unsigned int scif0_data_mux[] = {
-	RX0_MARK, TX0_MARK,
-};
-static const unsigned int scif0_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
-};
-static const unsigned int scif0_data_b_mux[] = {
-	RX0_B_MARK, TX0_B_MARK,
-};
-static const unsigned int scif0_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
-};
-static const unsigned int scif0_data_c_mux[] = {
-	RX0_C_MARK, TX0_C_MARK,
-};
-static const unsigned int scif0_data_d_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
-};
-static const unsigned int scif0_data_d_mux[] = {
-	RX0_D_MARK, TX0_D_MARK,
-};
-static const unsigned int scif0_data_e_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
-};
-static const unsigned int scif0_data_e_mux[] = {
-	RX0_E_MARK, TX0_E_MARK,
-};
-/* - SCIF1 ------------------------------------------------------------------ */
-static const unsigned int scif1_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
-};
-static const unsigned int scif1_data_mux[] = {
-	RX1_MARK, TX1_MARK,
-};
-static const unsigned int scif1_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
-};
-static const unsigned int scif1_data_b_mux[] = {
-	RX1_B_MARK, TX1_B_MARK,
-};
-static const unsigned int scif1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 10),
-};
-static const unsigned int scif1_clk_b_mux[] = {
-	SCIF1_SCK_B_MARK,
-};
-static const unsigned int scif1_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
-};
-static const unsigned int scif1_data_c_mux[] = {
-	RX1_C_MARK, TX1_C_MARK,
-};
-static const unsigned int scif1_data_d_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
-};
-static const unsigned int scif1_data_d_mux[] = {
-	RX1_D_MARK, TX1_D_MARK,
-};
-/* - SCIF2 ------------------------------------------------------------------ */
-static const unsigned int scif2_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
-};
-static const unsigned int scif2_data_mux[] = {
-	RX2_MARK, TX2_MARK,
-};
-static const unsigned int scif2_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
-};
-static const unsigned int scif2_data_b_mux[] = {
-	RX2_B_MARK, TX2_B_MARK,
-};
-static const unsigned int scif2_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 18),
-};
-static const unsigned int scif2_clk_b_mux[] = {
-	SCIF2_SCK_B_MARK,
-};
-static const unsigned int scif2_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
-};
-static const unsigned int scif2_data_c_mux[] = {
-	RX2_C_MARK, TX2_C_MARK,
-};
-static const unsigned int scif2_data_e_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
-};
-static const unsigned int scif2_data_e_mux[] = {
-	RX2_E_MARK, TX2_E_MARK,
-};
-/* - SCIF3 ------------------------------------------------------------------ */
-static const unsigned int scif3_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
-};
-static const unsigned int scif3_data_mux[] = {
-	RX3_MARK, TX3_MARK,
-};
-static const unsigned int scif3_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 23),
-};
-static const unsigned int scif3_clk_mux[] = {
-	SCIF3_SCK_MARK,
-};
-static const unsigned int scif3_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
-};
-static const unsigned int scif3_data_b_mux[] = {
-	RX3_B_MARK, TX3_B_MARK,
-};
-static const unsigned int scif3_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 8),
-};
-static const unsigned int scif3_clk_b_mux[] = {
-	SCIF3_SCK_B_MARK,
-};
-static const unsigned int scif3_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
-};
-static const unsigned int scif3_data_c_mux[] = {
-	RX3_C_MARK, TX3_C_MARK,
-};
-static const unsigned int scif3_data_d_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
-};
-static const unsigned int scif3_data_d_mux[] = {
-	RX3_D_MARK, TX3_D_MARK,
-};
-/* - SCIF4 ------------------------------------------------------------------ */
-static const unsigned int scif4_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
-};
-static const unsigned int scif4_data_mux[] = {
-	RX4_MARK, TX4_MARK,
-};
-static const unsigned int scif4_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
-};
-static const unsigned int scif4_data_b_mux[] = {
-	RX4_B_MARK, TX4_B_MARK,
-};
-static const unsigned int scif4_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
-};
-static const unsigned int scif4_data_c_mux[] = {
-	RX4_C_MARK, TX4_C_MARK,
-};
-/* - SCIF5 ------------------------------------------------------------------ */
-static const unsigned int scif5_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
-};
-static const unsigned int scif5_data_mux[] = {
-	RX5_MARK, TX5_MARK,
-};
-static const unsigned int scif5_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
-};
-static const unsigned int scif5_data_b_mux[] = {
-	RX5_B_MARK, TX5_B_MARK,
-};
-/* - SCIFA0 ----------------------------------------------------------------- */
-static const unsigned int scifa0_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
-};
-static const unsigned int scifa0_data_mux[] = {
-	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
-};
-static const unsigned int scifa0_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
-};
-static const unsigned int scifa0_data_b_mux[] = {
-	SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
-};
-/* - SCIFA1 ----------------------------------------------------------------- */
-static const unsigned int scifa1_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
-};
-static const unsigned int scifa1_data_mux[] = {
-	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
-};
-static const unsigned int scifa1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 10),
-};
-static const unsigned int scifa1_clk_mux[] = {
-	SCIFA1_SCK_MARK,
-};
-static const unsigned int scifa1_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
-};
-static const unsigned int scifa1_data_b_mux[] = {
-	SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
-};
-static const unsigned int scifa1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 0),
-};
-static const unsigned int scifa1_clk_b_mux[] = {
-	SCIFA1_SCK_B_MARK,
-};
-static const unsigned int scifa1_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-};
-static const unsigned int scifa1_data_c_mux[] = {
-	SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
-};
-/* - SCIFA2 ----------------------------------------------------------------- */
-static const unsigned int scifa2_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
-};
-static const unsigned int scifa2_data_mux[] = {
-	SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
-};
-static const unsigned int scifa2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 18),
-};
-static const unsigned int scifa2_clk_mux[] = {
-	SCIFA2_SCK_MARK,
-};
-static const unsigned int scifa2_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
-};
-static const unsigned int scifa2_data_b_mux[] = {
-	SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
-};
-/* - SCIFA3 ----------------------------------------------------------------- */
-static const unsigned int scifa3_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
-};
-static const unsigned int scifa3_data_mux[] = {
-	SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
-};
-static const unsigned int scifa3_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 23),
-};
-static const unsigned int scifa3_clk_mux[] = {
-	SCIFA3_SCK_MARK,
-};
-static const unsigned int scifa3_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
-};
-static const unsigned int scifa3_data_b_mux[] = {
-	SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
-};
-static const unsigned int scifa3_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 8),
-};
-static const unsigned int scifa3_clk_b_mux[] = {
-	SCIFA3_SCK_B_MARK,
-};
-static const unsigned int scifa3_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
-};
-static const unsigned int scifa3_data_c_mux[] = {
-	SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
-};
-static const unsigned int scifa3_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(7, 22),
-};
-static const unsigned int scifa3_clk_c_mux[] = {
-	SCIFA3_SCK_C_MARK,
-};
-/* - SCIFA4 ----------------------------------------------------------------- */
-static const unsigned int scifa4_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
-};
-static const unsigned int scifa4_data_mux[] = {
-	SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
-};
-static const unsigned int scifa4_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
-};
-static const unsigned int scifa4_data_b_mux[] = {
-	SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
-};
-static const unsigned int scifa4_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
-};
-static const unsigned int scifa4_data_c_mux[] = {
-	SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
-};
-/* - SCIFA5 ----------------------------------------------------------------- */
-static const unsigned int scifa5_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
-};
-static const unsigned int scifa5_data_mux[] = {
-	SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
-};
-static const unsigned int scifa5_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
-};
-static const unsigned int scifa5_data_b_mux[] = {
-	SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
-};
-static const unsigned int scifa5_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
-};
-static const unsigned int scifa5_data_c_mux[] = {
-	SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
-};
-/* - SCIFB0 ----------------------------------------------------------------- */
-static const unsigned int scifb0_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
-};
-static const unsigned int scifb0_data_mux[] = {
-	SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
-};
-static const unsigned int scifb0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(7, 2),
-};
-static const unsigned int scifb0_clk_mux[] = {
-	SCIFB0_SCK_MARK,
-};
-static const unsigned int scifb0_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
-};
-static const unsigned int scifb0_ctrl_mux[] = {
-	SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
-};
-static const unsigned int scifb0_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
-};
-static const unsigned int scifb0_data_b_mux[] = {
-	SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
-};
-static const unsigned int scifb0_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 31),
-};
-static const unsigned int scifb0_clk_b_mux[] = {
-	SCIFB0_SCK_B_MARK,
-};
-static const unsigned int scifb0_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
-};
-static const unsigned int scifb0_ctrl_b_mux[] = {
-	SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
-};
-static const unsigned int scifb0_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-};
-static const unsigned int scifb0_data_c_mux[] = {
-	SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
-};
-static const unsigned int scifb0_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 30),
-};
-static const unsigned int scifb0_clk_c_mux[] = {
-	SCIFB0_SCK_C_MARK,
-};
-static const unsigned int scifb0_data_d_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
-};
-static const unsigned int scifb0_data_d_mux[] = {
-	SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
-};
-static const unsigned int scifb0_clk_d_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 17),
-};
-static const unsigned int scifb0_clk_d_mux[] = {
-	SCIFB0_SCK_D_MARK,
-};
-/* - SCIFB1 ----------------------------------------------------------------- */
-static const unsigned int scifb1_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
-};
-static const unsigned int scifb1_data_mux[] = {
-	SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
-};
-static const unsigned int scifb1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(7, 7),
-};
-static const unsigned int scifb1_clk_mux[] = {
-	SCIFB1_SCK_MARK,
-};
-static const unsigned int scifb1_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
-};
-static const unsigned int scifb1_ctrl_mux[] = {
-	SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
-};
-static const unsigned int scifb1_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
-};
-static const unsigned int scifb1_data_b_mux[] = {
-	SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
-};
-static const unsigned int scifb1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 3),
-};
-static const unsigned int scifb1_clk_b_mux[] = {
-	SCIFB1_SCK_B_MARK,
-};
-static const unsigned int scifb1_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-};
-static const unsigned int scifb1_data_c_mux[] = {
-	SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
-};
-static const unsigned int scifb1_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(7, 11),
-};
-static const unsigned int scifb1_clk_c_mux[] = {
-	SCIFB1_SCK_C_MARK,
-};
-static const unsigned int scifb1_data_d_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
-};
-static const unsigned int scifb1_data_d_mux[] = {
-	SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
-};
-/* - SCIFB2 ----------------------------------------------------------------- */
-static const unsigned int scifb2_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
-};
-static const unsigned int scifb2_data_mux[] = {
-	SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
-};
-static const unsigned int scifb2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 15),
-};
-static const unsigned int scifb2_clk_mux[] = {
-	SCIFB2_SCK_MARK,
-};
-static const unsigned int scifb2_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
-};
-static const unsigned int scifb2_ctrl_mux[] = {
-	SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
-};
-static const unsigned int scifb2_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
-};
-static const unsigned int scifb2_data_b_mux[] = {
-	SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
-};
-static const unsigned int scifb2_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 31),
-};
-static const unsigned int scifb2_clk_b_mux[] = {
-	SCIFB2_SCK_B_MARK,
-};
-static const unsigned int scifb2_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
-};
-static const unsigned int scifb2_ctrl_b_mux[] = {
-	SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
-};
-static const unsigned int scifb2_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-};
-static const unsigned int scifb2_data_c_mux[] = {
-	SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
-};
-static const unsigned int scifb2_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 27),
-};
-static const unsigned int scifb2_clk_c_mux[] = {
-	SCIFB2_SCK_C_MARK,
-};
-static const unsigned int scifb2_data_d_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
-};
-static const unsigned int scifb2_data_d_mux[] = {
-	SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
-};
-
-/* - SCIF Clock ------------------------------------------------------------- */
-static const unsigned int scif_clk_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(2, 29),
-};
-static const unsigned int scif_clk_mux[] = {
-	SCIF_CLK_MARK,
-};
-static const unsigned int scif_clk_b_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(7, 19),
-};
-static const unsigned int scif_clk_b_mux[] = {
-	SCIF_CLK_B_MARK,
-};
-
-/* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 2),
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SD0_DATA0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
-	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
-};
-static const unsigned int sdhi0_data4_mux[] = {
-	SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
-};
-static const unsigned int sdhi0_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
-};
-static const unsigned int sdhi0_ctrl_mux[] = {
-	SD0_CLK_MARK, SD0_CMD_MARK,
-};
-static const unsigned int sdhi0_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(6, 6),
-};
-static const unsigned int sdhi0_cd_mux[] = {
-	SD0_CD_MARK,
-};
-static const unsigned int sdhi0_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(6, 7),
-};
-static const unsigned int sdhi0_wp_mux[] = {
-	SD0_WP_MARK,
-};
-/* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 10),
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	SD1_DATA0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
-	RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
-};
-static const unsigned int sdhi1_data4_mux[] = {
-	SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
-};
-static const unsigned int sdhi1_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
-};
-static const unsigned int sdhi1_ctrl_mux[] = {
-	SD1_CLK_MARK, SD1_CMD_MARK,
-};
-static const unsigned int sdhi1_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(6, 14),
-};
-static const unsigned int sdhi1_cd_mux[] = {
-	SD1_CD_MARK,
-};
-static const unsigned int sdhi1_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(6, 15),
-};
-static const unsigned int sdhi1_wp_mux[] = {
-	SD1_WP_MARK,
-};
-/* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 18),
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SD2_DATA0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
-	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
-};
-static const unsigned int sdhi2_data4_mux[] = {
-	SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
-};
-static const unsigned int sdhi2_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
-};
-static const unsigned int sdhi2_ctrl_mux[] = {
-	SD2_CLK_MARK, SD2_CMD_MARK,
-};
-static const unsigned int sdhi2_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(6, 22),
-};
-static const unsigned int sdhi2_cd_mux[] = {
-	SD2_CD_MARK,
-};
-static const unsigned int sdhi2_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(6, 23),
-};
-static const unsigned int sdhi2_wp_mux[] = {
-	SD2_WP_MARK,
-};
-
-/* - SSI -------------------------------------------------------------------- */
-static const unsigned int ssi0_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(2, 2),
-};
-
-static const unsigned int ssi0_data_mux[] = {
-	SSI_SDATA0_MARK,
-};
-
-static const unsigned int ssi0_data_b_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(3, 4),
-};
-
-static const unsigned int ssi0_data_b_mux[] = {
-	SSI_SDATA0_B_MARK,
-};
-
-static const unsigned int ssi0129_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-};
-
-static const unsigned int ssi0129_ctrl_mux[] = {
-	SSI_SCK0129_MARK, SSI_WS0129_MARK,
-};
-
-static const unsigned int ssi0129_ctrl_b_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
-};
-
-static const unsigned int ssi0129_ctrl_b_mux[] = {
-	SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK,
-};
-
-static const unsigned int ssi1_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(2, 5),
-};
-
-static const unsigned int ssi1_data_mux[] = {
-	SSI_SDATA1_MARK,
-};
-
-static const unsigned int ssi1_data_b_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(3, 7),
-};
-
-static const unsigned int ssi1_data_b_mux[] = {
-	SSI_SDATA1_B_MARK,
-};
-
-static const unsigned int ssi1_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
-};
-
-static const unsigned int ssi1_ctrl_mux[] = {
-	SSI_SCK1_MARK, SSI_WS1_MARK,
-};
-
-static const unsigned int ssi1_ctrl_b_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
-};
-
-static const unsigned int ssi1_ctrl_b_mux[] = {
-	SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
-};
-
-static const unsigned int ssi2_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(2, 8),
-};
-
-static const unsigned int ssi2_data_mux[] = {
-	SSI_SDATA2_MARK,
-};
-
-static const unsigned int ssi2_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-};
-
-static const unsigned int ssi2_ctrl_mux[] = {
-	SSI_SCK2_MARK, SSI_WS2_MARK,
-};
-
-static const unsigned int ssi3_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(2, 11),
-};
-
-static const unsigned int ssi3_data_mux[] = {
-	SSI_SDATA3_MARK,
-};
-
-static const unsigned int ssi34_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
-};
-
-static const unsigned int ssi34_ctrl_mux[] = {
-	SSI_SCK34_MARK, SSI_WS34_MARK,
-};
-
-static const unsigned int ssi4_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(2, 14),
-};
-
-static const unsigned int ssi4_data_mux[] = {
-	SSI_SDATA4_MARK,
-};
-
-static const unsigned int ssi4_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
-};
-
-static const unsigned int ssi4_ctrl_mux[] = {
-	SSI_SCK4_MARK, SSI_WS4_MARK,
-};
-
-static const unsigned int ssi5_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(2, 17),
-};
-
-static const unsigned int ssi5_data_mux[] = {
-	SSI_SDATA5_MARK,
-};
-
-static const unsigned int ssi5_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
-};
-
-static const unsigned int ssi5_ctrl_mux[] = {
-	SSI_SCK5_MARK, SSI_WS5_MARK,
-};
-
-static const unsigned int ssi6_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(2, 20),
-};
-
-static const unsigned int ssi6_data_mux[] = {
-	SSI_SDATA6_MARK,
-};
-
-static const unsigned int ssi6_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
-};
-
-static const unsigned int ssi6_ctrl_mux[] = {
-	SSI_SCK6_MARK, SSI_WS6_MARK,
-};
-
-static const unsigned int ssi7_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(2, 23),
-};
-
-static const unsigned int ssi7_data_mux[] = {
-	SSI_SDATA7_MARK,
-};
-
-static const unsigned int ssi7_data_b_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(3, 12),
-};
-
-static const unsigned int ssi7_data_b_mux[] = {
-	SSI_SDATA7_B_MARK,
-};
-
-static const unsigned int ssi78_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
-};
-
-static const unsigned int ssi78_ctrl_mux[] = {
-	SSI_SCK78_MARK, SSI_WS78_MARK,
-};
-
-static const unsigned int ssi78_ctrl_b_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-};
-
-static const unsigned int ssi78_ctrl_b_mux[] = {
-	SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
-};
-
-static const unsigned int ssi8_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(2, 24),
-};
-
-static const unsigned int ssi8_data_mux[] = {
-	SSI_SDATA8_MARK,
-};
-
-static const unsigned int ssi8_data_b_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(3, 13),
-};
-
-static const unsigned int ssi8_data_b_mux[] = {
-	SSI_SDATA8_B_MARK,
-};
-
-static const unsigned int ssi9_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(2, 27),
-};
-
-static const unsigned int ssi9_data_mux[] = {
-	SSI_SDATA9_MARK,
-};
-
-static const unsigned int ssi9_data_b_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(3, 18),
-};
-
-static const unsigned int ssi9_data_b_mux[] = {
-	SSI_SDATA9_B_MARK,
-};
-
-static const unsigned int ssi9_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
-};
-
-static const unsigned int ssi9_ctrl_mux[] = {
-	SSI_SCK9_MARK, SSI_WS9_MARK,
-};
-
-static const unsigned int ssi9_ctrl_b_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
-};
-
-static const unsigned int ssi9_ctrl_b_mux[] = {
-	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
-};
-
-/* - TPU -------------------------------------------------------------------- */
-static const unsigned int tpu_to0_pins[] = {
-	RCAR_GP_PIN(6, 14),
-};
-static const unsigned int tpu_to0_mux[] = {
-	TPU_TO0_MARK,
-};
-static const unsigned int tpu_to1_pins[] = {
-	RCAR_GP_PIN(1, 17),
-};
-static const unsigned int tpu_to1_mux[] = {
-	TPU_TO1_MARK,
-};
-static const unsigned int tpu_to2_pins[] = {
-	RCAR_GP_PIN(1, 18),
-};
-static const unsigned int tpu_to2_mux[] = {
-	TPU_TO2_MARK,
-};
-static const unsigned int tpu_to3_pins[] = {
-	RCAR_GP_PIN(1, 24),
-};
-static const unsigned int tpu_to3_mux[] = {
-	TPU_TO3_MARK,
-};
-
-/* - USB0 ------------------------------------------------------------------- */
-static const unsigned int usb0_pins[] = {
-	RCAR_GP_PIN(7, 23), /* PWEN */
-	RCAR_GP_PIN(7, 24), /* OVC */
-};
-static const unsigned int usb0_mux[] = {
-	USB0_PWEN_MARK,
-	USB0_OVC_MARK,
-};
-/* - USB1 ------------------------------------------------------------------- */
-static const unsigned int usb1_pins[] = {
-	RCAR_GP_PIN(7, 25), /* PWEN */
-	RCAR_GP_PIN(6, 30), /* OVC */
-};
-static const unsigned int usb1_mux[] = {
-	USB1_PWEN_MARK,
-	USB1_OVC_MARK,
-};
-/* - VIN0 ------------------------------------------------------------------- */
-static const union vin_data vin0_data_pins = {
-	.data24 = {
-		/* B */
-		RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
-		RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
-		RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
-		RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
-		/* G */
-		RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
-		RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
-		RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
-		RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
-		/* R */
-		RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
-		RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
-		RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
-		RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
-	},
-};
-static const union vin_data vin0_data_mux = {
-	.data24 = {
-		/* B */
-		VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
-		VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
-		VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
-		VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
-		/* G */
-		VI0_G0_MARK, VI0_G1_MARK,
-		VI0_G2_MARK, VI0_G3_MARK,
-		VI0_G4_MARK, VI0_G5_MARK,
-		VI0_G6_MARK, VI0_G7_MARK,
-		/* R */
-		VI0_R0_MARK, VI0_R1_MARK,
-		VI0_R2_MARK, VI0_R3_MARK,
-		VI0_R4_MARK, VI0_R5_MARK,
-		VI0_R6_MARK, VI0_R7_MARK,
-	},
-};
-static const unsigned int vin0_data18_pins[] = {
-	/* B */
-	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
-	RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
-	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
-	/* G */
-	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
-	RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
-	RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
-	/* R */
-	RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
-	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
-	RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
-};
-static const unsigned int vin0_data18_mux[] = {
-	/* B */
-	VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
-	VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
-	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
-	/* G */
-	VI0_G2_MARK, VI0_G3_MARK,
-	VI0_G4_MARK, VI0_G5_MARK,
-	VI0_G6_MARK, VI0_G7_MARK,
-	/* R */
-	VI0_R2_MARK, VI0_R3_MARK,
-	VI0_R4_MARK, VI0_R5_MARK,
-	VI0_R6_MARK, VI0_R7_MARK,
-};
-static const unsigned int vin0_sync_pins[] = {
-	RCAR_GP_PIN(4, 3), /* HSYNC */
-	RCAR_GP_PIN(4, 4), /* VSYNC */
-};
-static const unsigned int vin0_sync_mux[] = {
-	VI0_HSYNC_N_MARK,
-	VI0_VSYNC_N_MARK,
-};
-static const unsigned int vin0_field_pins[] = {
-	RCAR_GP_PIN(4, 2),
-};
-static const unsigned int vin0_field_mux[] = {
-	VI0_FIELD_MARK,
-};
-static const unsigned int vin0_clkenb_pins[] = {
-	RCAR_GP_PIN(4, 1),
-};
-static const unsigned int vin0_clkenb_mux[] = {
-	VI0_CLKENB_MARK,
-};
-static const unsigned int vin0_clk_pins[] = {
-	RCAR_GP_PIN(4, 0),
-};
-static const unsigned int vin0_clk_mux[] = {
-	VI0_CLK_MARK,
-};
-/* - VIN1 ----------------------------------------------------------------- */
-static const unsigned int vin1_data8_pins[] = {
-	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
-	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
-	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
-	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
-};
-static const unsigned int vin1_data8_mux[] = {
-	VI1_DATA0_MARK, VI1_DATA1_MARK,
-	VI1_DATA2_MARK, VI1_DATA3_MARK,
-	VI1_DATA4_MARK, VI1_DATA5_MARK,
-	VI1_DATA6_MARK, VI1_DATA7_MARK,
-};
-static const unsigned int vin1_sync_pins[] = {
-	RCAR_GP_PIN(5, 0), /* HSYNC */
-	RCAR_GP_PIN(5, 1), /* VSYNC */
-};
-static const unsigned int vin1_sync_mux[] = {
-	VI1_HSYNC_N_MARK,
-	VI1_VSYNC_N_MARK,
-};
-static const unsigned int vin1_field_pins[] = {
-	RCAR_GP_PIN(5, 3),
-};
-static const unsigned int vin1_field_mux[] = {
-	VI1_FIELD_MARK,
-};
-static const unsigned int vin1_clkenb_pins[] = {
-	RCAR_GP_PIN(5, 2),
-};
-static const unsigned int vin1_clkenb_mux[] = {
-	VI1_CLKENB_MARK,
-};
-static const unsigned int vin1_clk_pins[] = {
-	RCAR_GP_PIN(5, 4),
-};
-static const unsigned int vin1_clk_mux[] = {
-	VI1_CLK_MARK,
-};
-static const union vin_data vin1_data_b_pins = {
-	.data24 = {
-		/* B */
-		RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
-		RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-		RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-		RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
-		/* G */
-		RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
-		RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
-		RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
-		RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
-		/* R */
-		RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
-		RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
-		RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
-		RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
-	},
-};
-static const union vin_data vin1_data_b_mux = {
-	.data24 = {
-		/* B */
-		VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
-		VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
-		VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
-		VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
-		/* G */
-		VI1_G0_B_MARK, VI1_G1_B_MARK,
-		VI1_G2_B_MARK, VI1_G3_B_MARK,
-		VI1_G4_B_MARK, VI1_G5_B_MARK,
-		VI1_G6_B_MARK, VI1_G7_B_MARK,
-		/* R */
-		VI1_R0_B_MARK, VI1_R1_B_MARK,
-		VI1_R2_B_MARK, VI1_R3_B_MARK,
-		VI1_R4_B_MARK, VI1_R5_B_MARK,
-		VI1_R6_B_MARK, VI1_R7_B_MARK,
-	},
-};
-static const unsigned int vin1_data18_b_pins[] = {
-	/* B */
-	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
-	/* G */
-	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
-	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
-	RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
-	/* R */
-	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
-	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
-	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
-};
-static const unsigned int vin1_data18_b_mux[] = {
-	/* B */
-	VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
-	VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
-	VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
-	/* G */
-	VI1_G2_B_MARK, VI1_G3_B_MARK,
-	VI1_G4_B_MARK, VI1_G5_B_MARK,
-	VI1_G6_B_MARK, VI1_G7_B_MARK,
-	/* R */
-	VI1_R2_B_MARK, VI1_R3_B_MARK,
-	VI1_R4_B_MARK, VI1_R5_B_MARK,
-	VI1_R6_B_MARK, VI1_R7_B_MARK,
-};
-static const unsigned int vin1_sync_b_pins[] = {
-	RCAR_GP_PIN(3, 17), /* HSYNC */
-	RCAR_GP_PIN(3, 18), /* VSYNC */
-};
-static const unsigned int vin1_sync_b_mux[] = {
-	VI1_HSYNC_N_B_MARK,
-	VI1_VSYNC_N_B_MARK,
-};
-static const unsigned int vin1_field_b_pins[] = {
-	RCAR_GP_PIN(3, 20),
-};
-static const unsigned int vin1_field_b_mux[] = {
-	VI1_FIELD_B_MARK,
-};
-static const unsigned int vin1_clkenb_b_pins[] = {
-	RCAR_GP_PIN(3, 19),
-};
-static const unsigned int vin1_clkenb_b_mux[] = {
-	VI1_CLKENB_B_MARK,
-};
-static const unsigned int vin1_clk_b_pins[] = {
-	RCAR_GP_PIN(3, 16),
-};
-static const unsigned int vin1_clk_b_mux[] = {
-	VI1_CLK_B_MARK,
-};
-/* - VIN2 ----------------------------------------------------------------- */
-static const unsigned int vin2_data8_pins[] = {
-	RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
-	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
-	RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
-	RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
-};
-static const unsigned int vin2_data8_mux[] = {
-	VI2_DATA0_MARK, VI2_DATA1_MARK,
-	VI2_DATA2_MARK, VI2_DATA3_MARK,
-	VI2_DATA4_MARK, VI2_DATA5_MARK,
-	VI2_DATA6_MARK, VI2_DATA7_MARK,
-};
-static const unsigned int vin2_sync_pins[] = {
-	RCAR_GP_PIN(4, 15), /* HSYNC */
-	RCAR_GP_PIN(4, 16), /* VSYNC */
-};
-static const unsigned int vin2_sync_mux[] = {
-	VI2_HSYNC_N_MARK,
-	VI2_VSYNC_N_MARK,
-};
-static const unsigned int vin2_field_pins[] = {
-	RCAR_GP_PIN(4, 18),
-};
-static const unsigned int vin2_field_mux[] = {
-	VI2_FIELD_MARK,
-};
-static const unsigned int vin2_clkenb_pins[] = {
-	RCAR_GP_PIN(4, 17),
-};
-static const unsigned int vin2_clkenb_mux[] = {
-	VI2_CLKENB_MARK,
-};
-static const unsigned int vin2_clk_pins[] = {
-	RCAR_GP_PIN(4, 19),
-};
-static const unsigned int vin2_clk_mux[] = {
-	VI2_CLK_MARK,
-};
-
-static const struct {
-	struct sh_pfc_pin_group common[346];
-	struct sh_pfc_pin_group automotive[9];
-} pinmux_groups = {
-	.common = {
-		SH_PFC_PIN_GROUP(audio_clk_a),
-		SH_PFC_PIN_GROUP(audio_clk_b),
-		SH_PFC_PIN_GROUP(audio_clk_b_b),
-		SH_PFC_PIN_GROUP(audio_clk_c),
-		SH_PFC_PIN_GROUP(audio_clkout),
-		SH_PFC_PIN_GROUP(avb_link),
-		SH_PFC_PIN_GROUP(avb_magic),
-		SH_PFC_PIN_GROUP(avb_phy_int),
-		SH_PFC_PIN_GROUP(avb_mdio),
-		SH_PFC_PIN_GROUP(avb_mii),
-		SH_PFC_PIN_GROUP(avb_gmii),
-		SH_PFC_PIN_GROUP(can0_data),
-		SH_PFC_PIN_GROUP(can0_data_b),
-		SH_PFC_PIN_GROUP(can0_data_c),
-		SH_PFC_PIN_GROUP(can0_data_d),
-		SH_PFC_PIN_GROUP(can0_data_e),
-		SH_PFC_PIN_GROUP(can0_data_f),
-		SH_PFC_PIN_GROUP(can1_data),
-		SH_PFC_PIN_GROUP(can1_data_b),
-		SH_PFC_PIN_GROUP(can1_data_c),
-		SH_PFC_PIN_GROUP(can1_data_d),
-		SH_PFC_PIN_GROUP(can_clk),
-		SH_PFC_PIN_GROUP(can_clk_b),
-		SH_PFC_PIN_GROUP(can_clk_c),
-		SH_PFC_PIN_GROUP(can_clk_d),
-		SH_PFC_PIN_GROUP(du_rgb666),
-		SH_PFC_PIN_GROUP(du_rgb888),
-		SH_PFC_PIN_GROUP(du_clk_out_0),
-		SH_PFC_PIN_GROUP(du_clk_out_1),
-		SH_PFC_PIN_GROUP(du_sync),
-		SH_PFC_PIN_GROUP(du_oddf),
-		SH_PFC_PIN_GROUP(du_cde),
-		SH_PFC_PIN_GROUP(du_disp),
-		SH_PFC_PIN_GROUP(du0_clk_in),
-		SH_PFC_PIN_GROUP(du1_clk_in),
-		SH_PFC_PIN_GROUP(du1_clk_in_b),
-		SH_PFC_PIN_GROUP(du1_clk_in_c),
-		SH_PFC_PIN_GROUP(eth_link),
-		SH_PFC_PIN_GROUP(eth_magic),
-		SH_PFC_PIN_GROUP(eth_mdio),
-		SH_PFC_PIN_GROUP(eth_rmii),
-		SH_PFC_PIN_GROUP(hscif0_data),
-		SH_PFC_PIN_GROUP(hscif0_clk),
-		SH_PFC_PIN_GROUP(hscif0_ctrl),
-		SH_PFC_PIN_GROUP(hscif0_data_b),
-		SH_PFC_PIN_GROUP(hscif0_ctrl_b),
-		SH_PFC_PIN_GROUP(hscif0_data_c),
-		SH_PFC_PIN_GROUP(hscif0_clk_c),
-		SH_PFC_PIN_GROUP(hscif1_data),
-		SH_PFC_PIN_GROUP(hscif1_clk),
-		SH_PFC_PIN_GROUP(hscif1_ctrl),
-		SH_PFC_PIN_GROUP(hscif1_data_b),
-		SH_PFC_PIN_GROUP(hscif1_data_c),
-		SH_PFC_PIN_GROUP(hscif1_clk_c),
-		SH_PFC_PIN_GROUP(hscif1_ctrl_c),
-		SH_PFC_PIN_GROUP(hscif1_data_d),
-		SH_PFC_PIN_GROUP(hscif1_data_e),
-		SH_PFC_PIN_GROUP(hscif1_clk_e),
-		SH_PFC_PIN_GROUP(hscif1_ctrl_e),
-		SH_PFC_PIN_GROUP(hscif2_data),
-		SH_PFC_PIN_GROUP(hscif2_clk),
-		SH_PFC_PIN_GROUP(hscif2_ctrl),
-		SH_PFC_PIN_GROUP(hscif2_data_b),
-		SH_PFC_PIN_GROUP(hscif2_ctrl_b),
-		SH_PFC_PIN_GROUP(hscif2_data_c),
-		SH_PFC_PIN_GROUP(hscif2_clk_c),
-		SH_PFC_PIN_GROUP(hscif2_data_d),
-		SH_PFC_PIN_GROUP(i2c0),
-		SH_PFC_PIN_GROUP(i2c0_b),
-		SH_PFC_PIN_GROUP(i2c0_c),
-		SH_PFC_PIN_GROUP(i2c1),
-		SH_PFC_PIN_GROUP(i2c1_b),
-		SH_PFC_PIN_GROUP(i2c1_c),
-		SH_PFC_PIN_GROUP(i2c1_d),
-		SH_PFC_PIN_GROUP(i2c1_e),
-		SH_PFC_PIN_GROUP(i2c2),
-		SH_PFC_PIN_GROUP(i2c2_b),
-		SH_PFC_PIN_GROUP(i2c2_c),
-		SH_PFC_PIN_GROUP(i2c2_d),
-		SH_PFC_PIN_GROUP(i2c3),
-		SH_PFC_PIN_GROUP(i2c3_b),
-		SH_PFC_PIN_GROUP(i2c3_c),
-		SH_PFC_PIN_GROUP(i2c3_d),
-		SH_PFC_PIN_GROUP(i2c4),
-		SH_PFC_PIN_GROUP(i2c4_b),
-		SH_PFC_PIN_GROUP(i2c4_c),
-		SH_PFC_PIN_GROUP(i2c7),
-		SH_PFC_PIN_GROUP(i2c7_b),
-		SH_PFC_PIN_GROUP(i2c7_c),
-		SH_PFC_PIN_GROUP(i2c8),
-		SH_PFC_PIN_GROUP(i2c8_b),
-		SH_PFC_PIN_GROUP(i2c8_c),
-		SH_PFC_PIN_GROUP(intc_irq0),
-		SH_PFC_PIN_GROUP(intc_irq1),
-		SH_PFC_PIN_GROUP(intc_irq2),
-		SH_PFC_PIN_GROUP(intc_irq3),
-		SH_PFC_PIN_GROUP(mmc_data1),
-		SH_PFC_PIN_GROUP(mmc_data4),
-		SH_PFC_PIN_GROUP(mmc_data8),
-		SH_PFC_PIN_GROUP(mmc_data8_b),
-		SH_PFC_PIN_GROUP(mmc_ctrl),
-		SH_PFC_PIN_GROUP(msiof0_clk),
-		SH_PFC_PIN_GROUP(msiof0_sync),
-		SH_PFC_PIN_GROUP(msiof0_ss1),
-		SH_PFC_PIN_GROUP(msiof0_ss2),
-		SH_PFC_PIN_GROUP(msiof0_rx),
-		SH_PFC_PIN_GROUP(msiof0_tx),
-		SH_PFC_PIN_GROUP(msiof0_clk_b),
-		SH_PFC_PIN_GROUP(msiof0_sync_b),
-		SH_PFC_PIN_GROUP(msiof0_ss1_b),
-		SH_PFC_PIN_GROUP(msiof0_ss2_b),
-		SH_PFC_PIN_GROUP(msiof0_rx_b),
-		SH_PFC_PIN_GROUP(msiof0_tx_b),
-		SH_PFC_PIN_GROUP(msiof0_clk_c),
-		SH_PFC_PIN_GROUP(msiof0_sync_c),
-		SH_PFC_PIN_GROUP(msiof0_ss1_c),
-		SH_PFC_PIN_GROUP(msiof0_ss2_c),
-		SH_PFC_PIN_GROUP(msiof0_rx_c),
-		SH_PFC_PIN_GROUP(msiof0_tx_c),
-		SH_PFC_PIN_GROUP(msiof1_clk),
-		SH_PFC_PIN_GROUP(msiof1_sync),
-		SH_PFC_PIN_GROUP(msiof1_ss1),
-		SH_PFC_PIN_GROUP(msiof1_ss2),
-		SH_PFC_PIN_GROUP(msiof1_rx),
-		SH_PFC_PIN_GROUP(msiof1_tx),
-		SH_PFC_PIN_GROUP(msiof1_clk_b),
-		SH_PFC_PIN_GROUP(msiof1_sync_b),
-		SH_PFC_PIN_GROUP(msiof1_ss1_b),
-		SH_PFC_PIN_GROUP(msiof1_ss2_b),
-		SH_PFC_PIN_GROUP(msiof1_rx_b),
-		SH_PFC_PIN_GROUP(msiof1_tx_b),
-		SH_PFC_PIN_GROUP(msiof1_clk_c),
-		SH_PFC_PIN_GROUP(msiof1_sync_c),
-		SH_PFC_PIN_GROUP(msiof1_rx_c),
-		SH_PFC_PIN_GROUP(msiof1_tx_c),
-		SH_PFC_PIN_GROUP(msiof1_clk_d),
-		SH_PFC_PIN_GROUP(msiof1_sync_d),
-		SH_PFC_PIN_GROUP(msiof1_ss1_d),
-		SH_PFC_PIN_GROUP(msiof1_rx_d),
-		SH_PFC_PIN_GROUP(msiof1_tx_d),
-		SH_PFC_PIN_GROUP(msiof1_clk_e),
-		SH_PFC_PIN_GROUP(msiof1_sync_e),
-		SH_PFC_PIN_GROUP(msiof1_rx_e),
-		SH_PFC_PIN_GROUP(msiof1_tx_e),
-		SH_PFC_PIN_GROUP(msiof2_clk),
-		SH_PFC_PIN_GROUP(msiof2_sync),
-		SH_PFC_PIN_GROUP(msiof2_ss1),
-		SH_PFC_PIN_GROUP(msiof2_ss2),
-		SH_PFC_PIN_GROUP(msiof2_rx),
-		SH_PFC_PIN_GROUP(msiof2_tx),
-		SH_PFC_PIN_GROUP(msiof2_clk_b),
-		SH_PFC_PIN_GROUP(msiof2_sync_b),
-		SH_PFC_PIN_GROUP(msiof2_ss1_b),
-		SH_PFC_PIN_GROUP(msiof2_ss2_b),
-		SH_PFC_PIN_GROUP(msiof2_rx_b),
-		SH_PFC_PIN_GROUP(msiof2_tx_b),
-		SH_PFC_PIN_GROUP(msiof2_clk_c),
-		SH_PFC_PIN_GROUP(msiof2_sync_c),
-		SH_PFC_PIN_GROUP(msiof2_rx_c),
-		SH_PFC_PIN_GROUP(msiof2_tx_c),
-		SH_PFC_PIN_GROUP(msiof2_clk_d),
-		SH_PFC_PIN_GROUP(msiof2_sync_d),
-		SH_PFC_PIN_GROUP(msiof2_ss1_d),
-		SH_PFC_PIN_GROUP(msiof2_ss2_d),
-		SH_PFC_PIN_GROUP(msiof2_rx_d),
-		SH_PFC_PIN_GROUP(msiof2_tx_d),
-		SH_PFC_PIN_GROUP(msiof2_clk_e),
-		SH_PFC_PIN_GROUP(msiof2_sync_e),
-		SH_PFC_PIN_GROUP(msiof2_rx_e),
-		SH_PFC_PIN_GROUP(msiof2_tx_e),
-		SH_PFC_PIN_GROUP(pwm0),
-		SH_PFC_PIN_GROUP(pwm0_b),
-		SH_PFC_PIN_GROUP(pwm1),
-		SH_PFC_PIN_GROUP(pwm1_b),
-		SH_PFC_PIN_GROUP(pwm2),
-		SH_PFC_PIN_GROUP(pwm2_b),
-		SH_PFC_PIN_GROUP(pwm3),
-		SH_PFC_PIN_GROUP(pwm4),
-		SH_PFC_PIN_GROUP(pwm4_b),
-		SH_PFC_PIN_GROUP(pwm5),
-		SH_PFC_PIN_GROUP(pwm5_b),
-		SH_PFC_PIN_GROUP(pwm6),
-		SH_PFC_PIN_GROUP(qspi_ctrl),
-		SH_PFC_PIN_GROUP(qspi_data2),
-		SH_PFC_PIN_GROUP(qspi_data4),
-		SH_PFC_PIN_GROUP(qspi_ctrl_b),
-		SH_PFC_PIN_GROUP(qspi_data2_b),
-		SH_PFC_PIN_GROUP(qspi_data4_b),
-		SH_PFC_PIN_GROUP(scif0_data),
-		SH_PFC_PIN_GROUP(scif0_data_b),
-		SH_PFC_PIN_GROUP(scif0_data_c),
-		SH_PFC_PIN_GROUP(scif0_data_d),
-		SH_PFC_PIN_GROUP(scif0_data_e),
-		SH_PFC_PIN_GROUP(scif1_data),
-		SH_PFC_PIN_GROUP(scif1_data_b),
-		SH_PFC_PIN_GROUP(scif1_clk_b),
-		SH_PFC_PIN_GROUP(scif1_data_c),
-		SH_PFC_PIN_GROUP(scif1_data_d),
-		SH_PFC_PIN_GROUP(scif2_data),
-		SH_PFC_PIN_GROUP(scif2_data_b),
-		SH_PFC_PIN_GROUP(scif2_clk_b),
-		SH_PFC_PIN_GROUP(scif2_data_c),
-		SH_PFC_PIN_GROUP(scif2_data_e),
-		SH_PFC_PIN_GROUP(scif3_data),
-		SH_PFC_PIN_GROUP(scif3_clk),
-		SH_PFC_PIN_GROUP(scif3_data_b),
-		SH_PFC_PIN_GROUP(scif3_clk_b),
-		SH_PFC_PIN_GROUP(scif3_data_c),
-		SH_PFC_PIN_GROUP(scif3_data_d),
-		SH_PFC_PIN_GROUP(scif4_data),
-		SH_PFC_PIN_GROUP(scif4_data_b),
-		SH_PFC_PIN_GROUP(scif4_data_c),
-		SH_PFC_PIN_GROUP(scif5_data),
-		SH_PFC_PIN_GROUP(scif5_data_b),
-		SH_PFC_PIN_GROUP(scifa0_data),
-		SH_PFC_PIN_GROUP(scifa0_data_b),
-		SH_PFC_PIN_GROUP(scifa1_data),
-		SH_PFC_PIN_GROUP(scifa1_clk),
-		SH_PFC_PIN_GROUP(scifa1_data_b),
-		SH_PFC_PIN_GROUP(scifa1_clk_b),
-		SH_PFC_PIN_GROUP(scifa1_data_c),
-		SH_PFC_PIN_GROUP(scifa2_data),
-		SH_PFC_PIN_GROUP(scifa2_clk),
-		SH_PFC_PIN_GROUP(scifa2_data_b),
-		SH_PFC_PIN_GROUP(scifa3_data),
-		SH_PFC_PIN_GROUP(scifa3_clk),
-		SH_PFC_PIN_GROUP(scifa3_data_b),
-		SH_PFC_PIN_GROUP(scifa3_clk_b),
-		SH_PFC_PIN_GROUP(scifa3_data_c),
-		SH_PFC_PIN_GROUP(scifa3_clk_c),
-		SH_PFC_PIN_GROUP(scifa4_data),
-		SH_PFC_PIN_GROUP(scifa4_data_b),
-		SH_PFC_PIN_GROUP(scifa4_data_c),
-		SH_PFC_PIN_GROUP(scifa5_data),
-		SH_PFC_PIN_GROUP(scifa5_data_b),
-		SH_PFC_PIN_GROUP(scifa5_data_c),
-		SH_PFC_PIN_GROUP(scifb0_data),
-		SH_PFC_PIN_GROUP(scifb0_clk),
-		SH_PFC_PIN_GROUP(scifb0_ctrl),
-		SH_PFC_PIN_GROUP(scifb0_data_b),
-		SH_PFC_PIN_GROUP(scifb0_clk_b),
-		SH_PFC_PIN_GROUP(scifb0_ctrl_b),
-		SH_PFC_PIN_GROUP(scifb0_data_c),
-		SH_PFC_PIN_GROUP(scifb0_clk_c),
-		SH_PFC_PIN_GROUP(scifb0_data_d),
-		SH_PFC_PIN_GROUP(scifb0_clk_d),
-		SH_PFC_PIN_GROUP(scifb1_data),
-		SH_PFC_PIN_GROUP(scifb1_clk),
-		SH_PFC_PIN_GROUP(scifb1_ctrl),
-		SH_PFC_PIN_GROUP(scifb1_data_b),
-		SH_PFC_PIN_GROUP(scifb1_clk_b),
-		SH_PFC_PIN_GROUP(scifb1_data_c),
-		SH_PFC_PIN_GROUP(scifb1_clk_c),
-		SH_PFC_PIN_GROUP(scifb1_data_d),
-		SH_PFC_PIN_GROUP(scifb2_data),
-		SH_PFC_PIN_GROUP(scifb2_clk),
-		SH_PFC_PIN_GROUP(scifb2_ctrl),
-		SH_PFC_PIN_GROUP(scifb2_data_b),
-		SH_PFC_PIN_GROUP(scifb2_clk_b),
-		SH_PFC_PIN_GROUP(scifb2_ctrl_b),
-		SH_PFC_PIN_GROUP(scifb2_data_c),
-		SH_PFC_PIN_GROUP(scifb2_clk_c),
-		SH_PFC_PIN_GROUP(scifb2_data_d),
-		SH_PFC_PIN_GROUP(scif_clk),
-		SH_PFC_PIN_GROUP(scif_clk_b),
-		SH_PFC_PIN_GROUP(sdhi0_data1),
-		SH_PFC_PIN_GROUP(sdhi0_data4),
-		SH_PFC_PIN_GROUP(sdhi0_ctrl),
-		SH_PFC_PIN_GROUP(sdhi0_cd),
-		SH_PFC_PIN_GROUP(sdhi0_wp),
-		SH_PFC_PIN_GROUP(sdhi1_data1),
-		SH_PFC_PIN_GROUP(sdhi1_data4),
-		SH_PFC_PIN_GROUP(sdhi1_ctrl),
-		SH_PFC_PIN_GROUP(sdhi1_cd),
-		SH_PFC_PIN_GROUP(sdhi1_wp),
-		SH_PFC_PIN_GROUP(sdhi2_data1),
-		SH_PFC_PIN_GROUP(sdhi2_data4),
-		SH_PFC_PIN_GROUP(sdhi2_ctrl),
-		SH_PFC_PIN_GROUP(sdhi2_cd),
-		SH_PFC_PIN_GROUP(sdhi2_wp),
-		SH_PFC_PIN_GROUP(ssi0_data),
-		SH_PFC_PIN_GROUP(ssi0_data_b),
-		SH_PFC_PIN_GROUP(ssi0129_ctrl),
-		SH_PFC_PIN_GROUP(ssi0129_ctrl_b),
-		SH_PFC_PIN_GROUP(ssi1_data),
-		SH_PFC_PIN_GROUP(ssi1_data_b),
-		SH_PFC_PIN_GROUP(ssi1_ctrl),
-		SH_PFC_PIN_GROUP(ssi1_ctrl_b),
-		SH_PFC_PIN_GROUP(ssi2_data),
-		SH_PFC_PIN_GROUP(ssi2_ctrl),
-		SH_PFC_PIN_GROUP(ssi3_data),
-		SH_PFC_PIN_GROUP(ssi34_ctrl),
-		SH_PFC_PIN_GROUP(ssi4_data),
-		SH_PFC_PIN_GROUP(ssi4_ctrl),
-		SH_PFC_PIN_GROUP(ssi5_data),
-		SH_PFC_PIN_GROUP(ssi5_ctrl),
-		SH_PFC_PIN_GROUP(ssi6_data),
-		SH_PFC_PIN_GROUP(ssi6_ctrl),
-		SH_PFC_PIN_GROUP(ssi7_data),
-		SH_PFC_PIN_GROUP(ssi7_data_b),
-		SH_PFC_PIN_GROUP(ssi78_ctrl),
-		SH_PFC_PIN_GROUP(ssi78_ctrl_b),
-		SH_PFC_PIN_GROUP(ssi8_data),
-		SH_PFC_PIN_GROUP(ssi8_data_b),
-		SH_PFC_PIN_GROUP(ssi9_data),
-		SH_PFC_PIN_GROUP(ssi9_data_b),
-		SH_PFC_PIN_GROUP(ssi9_ctrl),
-		SH_PFC_PIN_GROUP(ssi9_ctrl_b),
-		SH_PFC_PIN_GROUP(tpu_to0),
-		SH_PFC_PIN_GROUP(tpu_to1),
-		SH_PFC_PIN_GROUP(tpu_to2),
-		SH_PFC_PIN_GROUP(tpu_to3),
-		SH_PFC_PIN_GROUP(usb0),
-		SH_PFC_PIN_GROUP(usb1),
-		VIN_DATA_PIN_GROUP(vin0_data, 24),
-		VIN_DATA_PIN_GROUP(vin0_data, 20),
-		SH_PFC_PIN_GROUP(vin0_data18),
-		VIN_DATA_PIN_GROUP(vin0_data, 16),
-		VIN_DATA_PIN_GROUP(vin0_data, 12),
-		VIN_DATA_PIN_GROUP(vin0_data, 10),
-		VIN_DATA_PIN_GROUP(vin0_data, 8),
-		SH_PFC_PIN_GROUP(vin0_sync),
-		SH_PFC_PIN_GROUP(vin0_field),
-		SH_PFC_PIN_GROUP(vin0_clkenb),
-		SH_PFC_PIN_GROUP(vin0_clk),
-		SH_PFC_PIN_GROUP(vin1_data8),
-		SH_PFC_PIN_GROUP(vin1_sync),
-		SH_PFC_PIN_GROUP(vin1_field),
-		SH_PFC_PIN_GROUP(vin1_clkenb),
-		SH_PFC_PIN_GROUP(vin1_clk),
-		VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
-		VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
-		SH_PFC_PIN_GROUP(vin1_data18_b),
-		VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
-		VIN_DATA_PIN_GROUP(vin1_data, 12, _b),
-		VIN_DATA_PIN_GROUP(vin1_data, 10, _b),
-		VIN_DATA_PIN_GROUP(vin1_data, 8, _b),
-		SH_PFC_PIN_GROUP(vin1_sync_b),
-		SH_PFC_PIN_GROUP(vin1_field_b),
-		SH_PFC_PIN_GROUP(vin1_clkenb_b),
-		SH_PFC_PIN_GROUP(vin1_clk_b),
-		SH_PFC_PIN_GROUP(vin2_data8),
-		SH_PFC_PIN_GROUP(vin2_sync),
-		SH_PFC_PIN_GROUP(vin2_field),
-		SH_PFC_PIN_GROUP(vin2_clkenb),
-		SH_PFC_PIN_GROUP(vin2_clk),
-	},
-	.automotive = {
-		SH_PFC_PIN_GROUP(adi_common),
-		SH_PFC_PIN_GROUP(adi_chsel0),
-		SH_PFC_PIN_GROUP(adi_chsel1),
-		SH_PFC_PIN_GROUP(adi_chsel2),
-		SH_PFC_PIN_GROUP(adi_common_b),
-		SH_PFC_PIN_GROUP(adi_chsel0_b),
-		SH_PFC_PIN_GROUP(adi_chsel1_b),
-		SH_PFC_PIN_GROUP(adi_chsel2_b),
-		SH_PFC_PIN_GROUP(mlb_3pin),
-	}
-};
-
-static const char * const adi_groups[] = {
-	"adi_common",
-	"adi_chsel0",
-	"adi_chsel1",
-	"adi_chsel2",
-	"adi_common_b",
-	"adi_chsel0_b",
-	"adi_chsel1_b",
-	"adi_chsel2_b",
-};
-
-static const char * const audio_clk_groups[] = {
-	"audio_clk_a",
-	"audio_clk_b",
-	"audio_clk_b_b",
-	"audio_clk_c",
-	"audio_clkout",
-};
-
-static const char * const avb_groups[] = {
-	"avb_link",
-	"avb_magic",
-	"avb_phy_int",
-	"avb_mdio",
-	"avb_mii",
-	"avb_gmii",
-};
-
-static const char * const can0_groups[] = {
-	"can0_data",
-	"can0_data_b",
-	"can0_data_c",
-	"can0_data_d",
-	"can0_data_e",
-	"can0_data_f",
-	/*
-	 * Retained for backwards compatibility, use can_clk_groups in new
-	 * designs.
-	 */
-	"can_clk",
-	"can_clk_b",
-	"can_clk_c",
-	"can_clk_d",
-};
-
-static const char * const can1_groups[] = {
-	"can1_data",
-	"can1_data_b",
-	"can1_data_c",
-	"can1_data_d",
-	/*
-	 * Retained for backwards compatibility, use can_clk_groups in new
-	 * designs.
-	 */
-	"can_clk",
-	"can_clk_b",
-	"can_clk_c",
-	"can_clk_d",
-};
-
-/*
- * can_clk_groups allows for independent configuration, use can_clk function
- * in new designs.
- */
-static const char * const can_clk_groups[] = {
-	"can_clk",
-	"can_clk_b",
-	"can_clk_c",
-	"can_clk_d",
-};
-
-static const char * const du_groups[] = {
-	"du_rgb666",
-	"du_rgb888",
-	"du_clk_out_0",
-	"du_clk_out_1",
-	"du_sync",
-	"du_oddf",
-	"du_cde",
-	"du_disp",
-};
-
-static const char * const du0_groups[] = {
-	"du0_clk_in",
-};
-
-static const char * const du1_groups[] = {
-	"du1_clk_in",
-	"du1_clk_in_b",
-	"du1_clk_in_c",
-};
-
-static const char * const eth_groups[] = {
-	"eth_link",
-	"eth_magic",
-	"eth_mdio",
-	"eth_rmii",
-};
-
-static const char * const hscif0_groups[] = {
-	"hscif0_data",
-	"hscif0_clk",
-	"hscif0_ctrl",
-	"hscif0_data_b",
-	"hscif0_ctrl_b",
-	"hscif0_data_c",
-	"hscif0_clk_c",
-};
-
-static const char * const hscif1_groups[] = {
-	"hscif1_data",
-	"hscif1_clk",
-	"hscif1_ctrl",
-	"hscif1_data_b",
-	"hscif1_data_c",
-	"hscif1_clk_c",
-	"hscif1_ctrl_c",
-	"hscif1_data_d",
-	"hscif1_data_e",
-	"hscif1_clk_e",
-	"hscif1_ctrl_e",
-};
-
-static const char * const hscif2_groups[] = {
-	"hscif2_data",
-	"hscif2_clk",
-	"hscif2_ctrl",
-	"hscif2_data_b",
-	"hscif2_ctrl_b",
-	"hscif2_data_c",
-	"hscif2_clk_c",
-	"hscif2_data_d",
-};
-
-static const char * const i2c0_groups[] = {
-	"i2c0",
-	"i2c0_b",
-	"i2c0_c",
-};
-
-static const char * const i2c1_groups[] = {
-	"i2c1",
-	"i2c1_b",
-	"i2c1_c",
-	"i2c1_d",
-	"i2c1_e",
-};
-
-static const char * const i2c2_groups[] = {
-	"i2c2",
-	"i2c2_b",
-	"i2c2_c",
-	"i2c2_d",
-};
-
-static const char * const i2c3_groups[] = {
-	"i2c3",
-	"i2c3_b",
-	"i2c3_c",
-	"i2c3_d",
-};
-
-static const char * const i2c4_groups[] = {
-	"i2c4",
-	"i2c4_b",
-	"i2c4_c",
-};
-
-static const char * const i2c7_groups[] = {
-	"i2c7",
-	"i2c7_b",
-	"i2c7_c",
-};
-
-static const char * const i2c8_groups[] = {
-	"i2c8",
-	"i2c8_b",
-	"i2c8_c",
-};
-
-static const char * const intc_groups[] = {
-	"intc_irq0",
-	"intc_irq1",
-	"intc_irq2",
-	"intc_irq3",
-};
-
-static const char * const mlb_groups[] = {
-	"mlb_3pin",
-};
-
-static const char * const mmc_groups[] = {
-	"mmc_data1",
-	"mmc_data4",
-	"mmc_data8",
-	"mmc_data8_b",
-	"mmc_ctrl",
-};
-
-static const char * const msiof0_groups[] = {
-	"msiof0_clk",
-	"msiof0_sync",
-	"msiof0_ss1",
-	"msiof0_ss2",
-	"msiof0_rx",
-	"msiof0_tx",
-	"msiof0_clk_b",
-	"msiof0_sync_b",
-	"msiof0_ss1_b",
-	"msiof0_ss2_b",
-	"msiof0_rx_b",
-	"msiof0_tx_b",
-	"msiof0_clk_c",
-	"msiof0_sync_c",
-	"msiof0_ss1_c",
-	"msiof0_ss2_c",
-	"msiof0_rx_c",
-	"msiof0_tx_c",
-};
-
-static const char * const msiof1_groups[] = {
-	"msiof1_clk",
-	"msiof1_sync",
-	"msiof1_ss1",
-	"msiof1_ss2",
-	"msiof1_rx",
-	"msiof1_tx",
-	"msiof1_clk_b",
-	"msiof1_sync_b",
-	"msiof1_ss1_b",
-	"msiof1_ss2_b",
-	"msiof1_rx_b",
-	"msiof1_tx_b",
-	"msiof1_clk_c",
-	"msiof1_sync_c",
-	"msiof1_rx_c",
-	"msiof1_tx_c",
-	"msiof1_clk_d",
-	"msiof1_sync_d",
-	"msiof1_ss1_d",
-	"msiof1_rx_d",
-	"msiof1_tx_d",
-	"msiof1_clk_e",
-	"msiof1_sync_e",
-	"msiof1_rx_e",
-	"msiof1_tx_e",
-};
-
-static const char * const msiof2_groups[] = {
-	"msiof2_clk",
-	"msiof2_sync",
-	"msiof2_ss1",
-	"msiof2_ss2",
-	"msiof2_rx",
-	"msiof2_tx",
-	"msiof2_clk_b",
-	"msiof2_sync_b",
-	"msiof2_ss1_b",
-	"msiof2_ss2_b",
-	"msiof2_rx_b",
-	"msiof2_tx_b",
-	"msiof2_clk_c",
-	"msiof2_sync_c",
-	"msiof2_rx_c",
-	"msiof2_tx_c",
-	"msiof2_clk_d",
-	"msiof2_sync_d",
-	"msiof2_ss1_d",
-	"msiof2_ss2_d",
-	"msiof2_rx_d",
-	"msiof2_tx_d",
-	"msiof2_clk_e",
-	"msiof2_sync_e",
-	"msiof2_rx_e",
-	"msiof2_tx_e",
-};
-
-static const char * const pwm0_groups[] = {
-	"pwm0",
-	"pwm0_b",
-};
-
-static const char * const pwm1_groups[] = {
-	"pwm1",
-	"pwm1_b",
-};
-
-static const char * const pwm2_groups[] = {
-	"pwm2",
-	"pwm2_b",
-};
-
-static const char * const pwm3_groups[] = {
-	"pwm3",
-};
-
-static const char * const pwm4_groups[] = {
-	"pwm4",
-	"pwm4_b",
-};
-
-static const char * const pwm5_groups[] = {
-	"pwm5",
-	"pwm5_b",
-};
-
-static const char * const pwm6_groups[] = {
-	"pwm6",
-};
-
-static const char * const qspi_groups[] = {
-	"qspi_ctrl",
-	"qspi_data2",
-	"qspi_data4",
-	"qspi_ctrl_b",
-	"qspi_data2_b",
-	"qspi_data4_b",
-};
-
-static const char * const scif0_groups[] = {
-	"scif0_data",
-	"scif0_data_b",
-	"scif0_data_c",
-	"scif0_data_d",
-	"scif0_data_e",
-};
-
-static const char * const scif1_groups[] = {
-	"scif1_data",
-	"scif1_data_b",
-	"scif1_clk_b",
-	"scif1_data_c",
-	"scif1_data_d",
-};
-
-static const char * const scif2_groups[] = {
-	"scif2_data",
-	"scif2_data_b",
-	"scif2_clk_b",
-	"scif2_data_c",
-	"scif2_data_e",
-};
-static const char * const scif3_groups[] = {
-	"scif3_data",
-	"scif3_clk",
-	"scif3_data_b",
-	"scif3_clk_b",
-	"scif3_data_c",
-	"scif3_data_d",
-};
-static const char * const scif4_groups[] = {
-	"scif4_data",
-	"scif4_data_b",
-	"scif4_data_c",
-};
-static const char * const scif5_groups[] = {
-	"scif5_data",
-	"scif5_data_b",
-};
-static const char * const scifa0_groups[] = {
-	"scifa0_data",
-	"scifa0_data_b",
-};
-static const char * const scifa1_groups[] = {
-	"scifa1_data",
-	"scifa1_clk",
-	"scifa1_data_b",
-	"scifa1_clk_b",
-	"scifa1_data_c",
-};
-static const char * const scifa2_groups[] = {
-	"scifa2_data",
-	"scifa2_clk",
-	"scifa2_data_b",
-};
-static const char * const scifa3_groups[] = {
-	"scifa3_data",
-	"scifa3_clk",
-	"scifa3_data_b",
-	"scifa3_clk_b",
-	"scifa3_data_c",
-	"scifa3_clk_c",
-};
-static const char * const scifa4_groups[] = {
-	"scifa4_data",
-	"scifa4_data_b",
-	"scifa4_data_c",
-};
-static const char * const scifa5_groups[] = {
-	"scifa5_data",
-	"scifa5_data_b",
-	"scifa5_data_c",
-};
-static const char * const scifb0_groups[] = {
-	"scifb0_data",
-	"scifb0_clk",
-	"scifb0_ctrl",
-	"scifb0_data_b",
-	"scifb0_clk_b",
-	"scifb0_ctrl_b",
-	"scifb0_data_c",
-	"scifb0_clk_c",
-	"scifb0_data_d",
-	"scifb0_clk_d",
-};
-static const char * const scifb1_groups[] = {
-	"scifb1_data",
-	"scifb1_clk",
-	"scifb1_ctrl",
-	"scifb1_data_b",
-	"scifb1_clk_b",
-	"scifb1_data_c",
-	"scifb1_clk_c",
-	"scifb1_data_d",
-};
-static const char * const scifb2_groups[] = {
-	"scifb2_data",
-	"scifb2_clk",
-	"scifb2_ctrl",
-	"scifb2_data_b",
-	"scifb2_clk_b",
-	"scifb2_ctrl_b",
-	"scifb2_data_c",
-	"scifb2_clk_c",
-	"scifb2_data_d",
-};
-
-static const char * const scif_clk_groups[] = {
-	"scif_clk",
-	"scif_clk_b",
-};
-
-static const char * const sdhi0_groups[] = {
-	"sdhi0_data1",
-	"sdhi0_data4",
-	"sdhi0_ctrl",
-	"sdhi0_cd",
-	"sdhi0_wp",
-};
-
-static const char * const sdhi1_groups[] = {
-	"sdhi1_data1",
-	"sdhi1_data4",
-	"sdhi1_ctrl",
-	"sdhi1_cd",
-	"sdhi1_wp",
-};
-
-static const char * const sdhi2_groups[] = {
-	"sdhi2_data1",
-	"sdhi2_data4",
-	"sdhi2_ctrl",
-	"sdhi2_cd",
-	"sdhi2_wp",
-};
-
-static const char * const ssi_groups[] = {
-	"ssi0_data",
-	"ssi0_data_b",
-	"ssi0129_ctrl",
-	"ssi0129_ctrl_b",
-	"ssi1_data",
-	"ssi1_data_b",
-	"ssi1_ctrl",
-	"ssi1_ctrl_b",
-	"ssi2_data",
-	"ssi2_ctrl",
-	"ssi3_data",
-	"ssi34_ctrl",
-	"ssi4_data",
-	"ssi4_ctrl",
-	"ssi5_data",
-	"ssi5_ctrl",
-	"ssi6_data",
-	"ssi6_ctrl",
-	"ssi7_data",
-	"ssi7_data_b",
-	"ssi78_ctrl",
-	"ssi78_ctrl_b",
-	"ssi8_data",
-	"ssi8_data_b",
-	"ssi9_data",
-	"ssi9_data_b",
-	"ssi9_ctrl",
-	"ssi9_ctrl_b",
-};
-
-static const char * const tpu_groups[] = {
-	"tpu_to0",
-	"tpu_to1",
-	"tpu_to2",
-	"tpu_to3",
-};
-
-static const char * const usb0_groups[] = {
-	"usb0",
-};
-static const char * const usb1_groups[] = {
-	"usb1",
-};
-
-static const char * const vin0_groups[] = {
-	"vin0_data24",
-	"vin0_data20",
-	"vin0_data18",
-	"vin0_data16",
-	"vin0_data12",
-	"vin0_data10",
-	"vin0_data8",
-	"vin0_sync",
-	"vin0_field",
-	"vin0_clkenb",
-	"vin0_clk",
-};
-
-static const char * const vin1_groups[] = {
-	"vin1_data8",
-	"vin1_sync",
-	"vin1_field",
-	"vin1_clkenb",
-	"vin1_clk",
-	"vin1_data24_b",
-	"vin1_data20_b",
-	"vin1_data18_b",
-	"vin1_data16_b",
-	"vin1_data12_b",
-	"vin1_data10_b",
-	"vin1_data8_b",
-	"vin1_sync_b",
-	"vin1_field_b",
-	"vin1_clkenb_b",
-	"vin1_clk_b",
-};
-
-static const char * const vin2_groups[] = {
-	"vin2_data8",
-	"vin2_sync",
-	"vin2_field",
-	"vin2_clkenb",
-	"vin2_clk",
-};
-
-static const struct {
-	struct sh_pfc_function common[58];
-	struct sh_pfc_function automotive[2];
-} pinmux_functions = {
-	.common = {
-		SH_PFC_FUNCTION(audio_clk),
-		SH_PFC_FUNCTION(avb),
-		SH_PFC_FUNCTION(can0),
-		SH_PFC_FUNCTION(can1),
-		SH_PFC_FUNCTION(can_clk),
-		SH_PFC_FUNCTION(du),
-		SH_PFC_FUNCTION(du0),
-		SH_PFC_FUNCTION(du1),
-		SH_PFC_FUNCTION(eth),
-		SH_PFC_FUNCTION(hscif0),
-		SH_PFC_FUNCTION(hscif1),
-		SH_PFC_FUNCTION(hscif2),
-		SH_PFC_FUNCTION(i2c0),
-		SH_PFC_FUNCTION(i2c1),
-		SH_PFC_FUNCTION(i2c2),
-		SH_PFC_FUNCTION(i2c3),
-		SH_PFC_FUNCTION(i2c4),
-		SH_PFC_FUNCTION(i2c7),
-		SH_PFC_FUNCTION(i2c8),
-		SH_PFC_FUNCTION(intc),
-		SH_PFC_FUNCTION(mmc),
-		SH_PFC_FUNCTION(msiof0),
-		SH_PFC_FUNCTION(msiof1),
-		SH_PFC_FUNCTION(msiof2),
-		SH_PFC_FUNCTION(pwm0),
-		SH_PFC_FUNCTION(pwm1),
-		SH_PFC_FUNCTION(pwm2),
-		SH_PFC_FUNCTION(pwm3),
-		SH_PFC_FUNCTION(pwm4),
-		SH_PFC_FUNCTION(pwm5),
-		SH_PFC_FUNCTION(pwm6),
-		SH_PFC_FUNCTION(qspi),
-		SH_PFC_FUNCTION(scif0),
-		SH_PFC_FUNCTION(scif1),
-		SH_PFC_FUNCTION(scif2),
-		SH_PFC_FUNCTION(scif3),
-		SH_PFC_FUNCTION(scif4),
-		SH_PFC_FUNCTION(scif5),
-		SH_PFC_FUNCTION(scifa0),
-		SH_PFC_FUNCTION(scifa1),
-		SH_PFC_FUNCTION(scifa2),
-		SH_PFC_FUNCTION(scifa3),
-		SH_PFC_FUNCTION(scifa4),
-		SH_PFC_FUNCTION(scifa5),
-		SH_PFC_FUNCTION(scifb0),
-		SH_PFC_FUNCTION(scifb1),
-		SH_PFC_FUNCTION(scifb2),
-		SH_PFC_FUNCTION(scif_clk),
-		SH_PFC_FUNCTION(sdhi0),
-		SH_PFC_FUNCTION(sdhi1),
-		SH_PFC_FUNCTION(sdhi2),
-		SH_PFC_FUNCTION(ssi),
-		SH_PFC_FUNCTION(tpu),
-		SH_PFC_FUNCTION(usb0),
-		SH_PFC_FUNCTION(usb1),
-		SH_PFC_FUNCTION(vin0),
-		SH_PFC_FUNCTION(vin1),
-		SH_PFC_FUNCTION(vin2),
-	},
-	.automotive = {
-		SH_PFC_FUNCTION(adi),
-		SH_PFC_FUNCTION(mlb),
-	}
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
-		GP_0_31_FN, FN_IP1_22_20,
-		GP_0_30_FN, FN_IP1_19_17,
-		GP_0_29_FN, FN_IP1_16_14,
-		GP_0_28_FN, FN_IP1_13_11,
-		GP_0_27_FN, FN_IP1_10_8,
-		GP_0_26_FN, FN_IP1_7_6,
-		GP_0_25_FN, FN_IP1_5_4,
-		GP_0_24_FN, FN_IP1_3_2,
-		GP_0_23_FN, FN_IP1_1_0,
-		GP_0_22_FN, FN_IP0_30_29,
-		GP_0_21_FN, FN_IP0_28_27,
-		GP_0_20_FN, FN_IP0_26_25,
-		GP_0_19_FN, FN_IP0_24_23,
-		GP_0_18_FN, FN_IP0_22_21,
-		GP_0_17_FN, FN_IP0_20_19,
-		GP_0_16_FN, FN_IP0_18_16,
-		GP_0_15_FN, FN_IP0_15,
-		GP_0_14_FN, FN_IP0_14,
-		GP_0_13_FN, FN_IP0_13,
-		GP_0_12_FN, FN_IP0_12,
-		GP_0_11_FN, FN_IP0_11,
-		GP_0_10_FN, FN_IP0_10,
-		GP_0_9_FN, FN_IP0_9,
-		GP_0_8_FN, FN_IP0_8,
-		GP_0_7_FN, FN_IP0_7,
-		GP_0_6_FN, FN_IP0_6,
-		GP_0_5_FN, FN_IP0_5,
-		GP_0_4_FN, FN_IP0_4,
-		GP_0_3_FN, FN_IP0_3,
-		GP_0_2_FN, FN_IP0_2,
-		GP_0_1_FN, FN_IP0_1,
-		GP_0_0_FN, FN_IP0_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_1_25_FN, FN_IP3_21_20,
-		GP_1_24_FN, FN_IP3_19_18,
-		GP_1_23_FN, FN_IP3_17_16,
-		GP_1_22_FN, FN_IP3_15_14,
-		GP_1_21_FN, FN_IP3_13_12,
-		GP_1_20_FN, FN_IP3_11_9,
-		GP_1_19_FN, FN_RD_N,
-		GP_1_18_FN, FN_IP3_8_6,
-		GP_1_17_FN, FN_IP3_5_3,
-		GP_1_16_FN, FN_IP3_2_0,
-		GP_1_15_FN, FN_IP2_29_27,
-		GP_1_14_FN, FN_IP2_26_25,
-		GP_1_13_FN, FN_IP2_24_23,
-		GP_1_12_FN, FN_EX_CS0_N,
-		GP_1_11_FN, FN_IP2_22_21,
-		GP_1_10_FN, FN_IP2_20_19,
-		GP_1_9_FN, FN_IP2_18_16,
-		GP_1_8_FN, FN_IP2_15_13,
-		GP_1_7_FN, FN_IP2_12_10,
-		GP_1_6_FN, FN_IP2_9_7,
-		GP_1_5_FN, FN_IP2_6_5,
-		GP_1_4_FN, FN_IP2_4_3,
-		GP_1_3_FN, FN_IP2_2_0,
-		GP_1_2_FN, FN_IP1_31_29,
-		GP_1_1_FN, FN_IP1_28_26,
-		GP_1_0_FN, FN_IP1_25_23, ))
-	},
-	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
-		GP_2_31_FN, FN_IP6_7_6,
-		GP_2_30_FN, FN_IP6_5_3,
-		GP_2_29_FN, FN_IP6_2_0,
-		GP_2_28_FN, FN_AUDIO_CLKA,
-		GP_2_27_FN, FN_IP5_31_29,
-		GP_2_26_FN, FN_IP5_28_26,
-		GP_2_25_FN, FN_IP5_25_24,
-		GP_2_24_FN, FN_IP5_23_22,
-		GP_2_23_FN, FN_IP5_21_20,
-		GP_2_22_FN, FN_IP5_19_17,
-		GP_2_21_FN, FN_IP5_16_15,
-		GP_2_20_FN, FN_IP5_14_12,
-		GP_2_19_FN, FN_IP5_11_9,
-		GP_2_18_FN, FN_IP5_8_6,
-		GP_2_17_FN, FN_IP5_5_3,
-		GP_2_16_FN, FN_IP5_2_0,
-		GP_2_15_FN, FN_IP4_30_28,
-		GP_2_14_FN, FN_IP4_27_26,
-		GP_2_13_FN, FN_IP4_25_24,
-		GP_2_12_FN, FN_IP4_23_22,
-		GP_2_11_FN, FN_IP4_21,
-		GP_2_10_FN, FN_IP4_20,
-		GP_2_9_FN, FN_IP4_19,
-		GP_2_8_FN, FN_IP4_18_16,
-		GP_2_7_FN, FN_IP4_15_13,
-		GP_2_6_FN, FN_IP4_12_10,
-		GP_2_5_FN, FN_IP4_9_8,
-		GP_2_4_FN, FN_IP4_7_5,
-		GP_2_3_FN, FN_IP4_4_2,
-		GP_2_2_FN, FN_IP4_1_0,
-		GP_2_1_FN, FN_IP3_30_28,
-		GP_2_0_FN, FN_IP3_27_25 ))
-	},
-	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
-		GP_3_31_FN, FN_IP9_18_17,
-		GP_3_30_FN, FN_IP9_16,
-		GP_3_29_FN, FN_IP9_15_13,
-		GP_3_28_FN, FN_IP9_12,
-		GP_3_27_FN, FN_IP9_11,
-		GP_3_26_FN, FN_IP9_10_8,
-		GP_3_25_FN, FN_IP9_7,
-		GP_3_24_FN, FN_IP9_6,
-		GP_3_23_FN, FN_IP9_5_3,
-		GP_3_22_FN, FN_IP9_2_0,
-		GP_3_21_FN, FN_IP8_30_28,
-		GP_3_20_FN, FN_IP8_27_26,
-		GP_3_19_FN, FN_IP8_25_24,
-		GP_3_18_FN, FN_IP8_23_21,
-		GP_3_17_FN, FN_IP8_20_18,
-		GP_3_16_FN, FN_IP8_17_15,
-		GP_3_15_FN, FN_IP8_14_12,
-		GP_3_14_FN, FN_IP8_11_9,
-		GP_3_13_FN, FN_IP8_8_6,
-		GP_3_12_FN, FN_IP8_5_3,
-		GP_3_11_FN, FN_IP8_2_0,
-		GP_3_10_FN, FN_IP7_29_27,
-		GP_3_9_FN, FN_IP7_26_24,
-		GP_3_8_FN, FN_IP7_23_21,
-		GP_3_7_FN, FN_IP7_20_19,
-		GP_3_6_FN, FN_IP7_18_17,
-		GP_3_5_FN, FN_IP7_16_15,
-		GP_3_4_FN, FN_IP7_14_13,
-		GP_3_3_FN, FN_IP7_12_11,
-		GP_3_2_FN, FN_IP7_10_9,
-		GP_3_1_FN, FN_IP7_8_6,
-		GP_3_0_FN, FN_IP7_5_3 ))
-	},
-	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
-		GP_4_31_FN, FN_IP15_5_4,
-		GP_4_30_FN, FN_IP15_3_2,
-		GP_4_29_FN, FN_IP15_1_0,
-		GP_4_28_FN, FN_IP11_8_6,
-		GP_4_27_FN, FN_IP11_5_3,
-		GP_4_26_FN, FN_IP11_2_0,
-		GP_4_25_FN, FN_IP10_31_29,
-		GP_4_24_FN, FN_IP10_28_27,
-		GP_4_23_FN, FN_IP10_26_25,
-		GP_4_22_FN, FN_IP10_24_22,
-		GP_4_21_FN, FN_IP10_21_19,
-		GP_4_20_FN, FN_IP10_18_17,
-		GP_4_19_FN, FN_IP10_16_15,
-		GP_4_18_FN, FN_IP10_14_12,
-		GP_4_17_FN, FN_IP10_11_9,
-		GP_4_16_FN, FN_IP10_8_6,
-		GP_4_15_FN, FN_IP10_5_3,
-		GP_4_14_FN, FN_IP10_2_0,
-		GP_4_13_FN, FN_IP9_31_29,
-		GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
-		GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
-		GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
-		GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
-		GP_4_8_FN, FN_IP9_28_27,
-		GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
-		GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
-		GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
-		GP_4_4_FN, FN_IP9_26_25,
-		GP_4_3_FN, FN_IP9_24_23,
-		GP_4_2_FN, FN_IP9_22_21,
-		GP_4_1_FN, FN_IP9_20_19,
-		GP_4_0_FN, FN_VI0_CLK ))
-	},
-	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
-		GP_5_31_FN, FN_IP3_24_22,
-		GP_5_30_FN, FN_IP13_9_7,
-		GP_5_29_FN, FN_IP13_6_5,
-		GP_5_28_FN, FN_IP13_4_3,
-		GP_5_27_FN, FN_IP13_2_0,
-		GP_5_26_FN, FN_IP12_29_27,
-		GP_5_25_FN, FN_IP12_26_24,
-		GP_5_24_FN, FN_IP12_23_22,
-		GP_5_23_FN, FN_IP12_21_20,
-		GP_5_22_FN, FN_IP12_19_18,
-		GP_5_21_FN, FN_IP12_17_16,
-		GP_5_20_FN, FN_IP12_15_13,
-		GP_5_19_FN, FN_IP12_12_10,
-		GP_5_18_FN, FN_IP12_9_7,
-		GP_5_17_FN, FN_IP12_6_4,
-		GP_5_16_FN, FN_IP12_3_2,
-		GP_5_15_FN, FN_IP12_1_0,
-		GP_5_14_FN, FN_IP11_31_30,
-		GP_5_13_FN, FN_IP11_29_28,
-		GP_5_12_FN, FN_IP11_27,
-		GP_5_11_FN, FN_IP11_26,
-		GP_5_10_FN, FN_IP11_25,
-		GP_5_9_FN, FN_IP11_24,
-		GP_5_8_FN, FN_IP11_23,
-		GP_5_7_FN, FN_IP11_22,
-		GP_5_6_FN, FN_IP11_21,
-		GP_5_5_FN, FN_IP11_20,
-		GP_5_4_FN, FN_IP11_19,
-		GP_5_3_FN, FN_IP11_18_17,
-		GP_5_2_FN, FN_IP11_16_15,
-		GP_5_1_FN, FN_IP11_14_12,
-		GP_5_0_FN, FN_IP11_11_9 ))
-	},
-	{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
-		GP_6_31_FN, FN_DU0_DOTCLKIN,
-		GP_6_30_FN, FN_USB1_OVC,
-		GP_6_29_FN, FN_IP14_31_29,
-		GP_6_28_FN, FN_IP14_28_26,
-		GP_6_27_FN, FN_IP14_25_23,
-		GP_6_26_FN, FN_IP14_22_20,
-		GP_6_25_FN, FN_IP14_19_17,
-		GP_6_24_FN, FN_IP14_16_14,
-		GP_6_23_FN, FN_IP14_13_11,
-		GP_6_22_FN, FN_IP14_10_8,
-		GP_6_21_FN, FN_IP14_7,
-		GP_6_20_FN, FN_IP14_6,
-		GP_6_19_FN, FN_IP14_5,
-		GP_6_18_FN, FN_IP14_4,
-		GP_6_17_FN, FN_IP14_3,
-		GP_6_16_FN, FN_IP14_2,
-		GP_6_15_FN, FN_IP14_1_0,
-		GP_6_14_FN, FN_IP13_30_28,
-		GP_6_13_FN, FN_IP13_27,
-		GP_6_12_FN, FN_IP13_26,
-		GP_6_11_FN, FN_IP13_25,
-		GP_6_10_FN, FN_IP13_24_23,
-		GP_6_9_FN, FN_IP13_22,
-		GP_6_8_FN, FN_SD1_CLK,
-		GP_6_7_FN, FN_IP13_21_19,
-		GP_6_6_FN, FN_IP13_18_16,
-		GP_6_5_FN, FN_IP13_15,
-		GP_6_4_FN, FN_IP13_14,
-		GP_6_3_FN, FN_IP13_13,
-		GP_6_2_FN, FN_IP13_12,
-		GP_6_1_FN, FN_IP13_11,
-		GP_6_0_FN, FN_IP13_10 ))
-	},
-	{ PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_7_25_FN, FN_USB1_PWEN,
-		GP_7_24_FN, FN_USB0_OVC,
-		GP_7_23_FN, FN_USB0_PWEN,
-		GP_7_22_FN, FN_IP15_14_12,
-		GP_7_21_FN, FN_IP15_11_9,
-		GP_7_20_FN, FN_IP15_8_6,
-		GP_7_19_FN, FN_IP7_2_0,
-		GP_7_18_FN, FN_IP6_29_27,
-		GP_7_17_FN, FN_IP6_26_24,
-		GP_7_16_FN, FN_IP6_23_21,
-		GP_7_15_FN, FN_IP6_20_19,
-		GP_7_14_FN, FN_IP6_18_16,
-		GP_7_13_FN, FN_IP6_15_14,
-		GP_7_12_FN, FN_IP6_13_12,
-		GP_7_11_FN, FN_IP6_11_10,
-		GP_7_10_FN, FN_IP6_9_8,
-		GP_7_9_FN, FN_IP16_11_10,
-		GP_7_8_FN, FN_IP16_9_8,
-		GP_7_7_FN, FN_IP16_7_6,
-		GP_7_6_FN, FN_IP16_5_3,
-		GP_7_5_FN, FN_IP16_2_0,
-		GP_7_4_FN, FN_IP15_29_27,
-		GP_7_3_FN, FN_IP15_26_24,
-		GP_7_2_FN, FN_IP15_23_21,
-		GP_7_1_FN, FN_IP15_20_18,
-		GP_7_0_FN, FN_IP15_17_15 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
-			     GROUP(1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1,
-				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
-			     GROUP(
-		/* IP0_31 [1] */
-		0, 0,
-		/* IP0_30_29 [2] */
-		FN_A6, FN_MSIOF1_SCK,
-		0, 0,
-		/* IP0_28_27 [2] */
-		FN_A5, FN_MSIOF0_RXD_B,
-		0, 0,
-		/* IP0_26_25 [2] */
-		FN_A4, FN_MSIOF0_TXD_B,
-		0, 0,
-		/* IP0_24_23 [2] */
-		FN_A3, FN_MSIOF0_SS2_B,
-		0, 0,
-		/* IP0_22_21 [2] */
-		FN_A2, FN_MSIOF0_SS1_B,
-		0, 0,
-		/* IP0_20_19 [2] */
-		FN_A1, FN_MSIOF0_SYNC_B,
-		0, 0,
-		/* IP0_18_16 [3] */
-		FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
-		0, 0, 0,
-		/* IP0_15 [1] */
-		FN_D15, 0,
-		/* IP0_14 [1] */
-		FN_D14, 0,
-		/* IP0_13 [1] */
-		FN_D13, 0,
-		/* IP0_12 [1] */
-		FN_D12, 0,
-		/* IP0_11 [1] */
-		FN_D11, 0,
-		/* IP0_10 [1] */
-		FN_D10, 0,
-		/* IP0_9 [1] */
-		FN_D9, 0,
-		/* IP0_8 [1] */
-		FN_D8, 0,
-		/* IP0_7 [1] */
-		FN_D7, 0,
-		/* IP0_6 [1] */
-		FN_D6, 0,
-		/* IP0_5 [1] */
-		FN_D5, 0,
-		/* IP0_4 [1] */
-		FN_D4, 0,
-		/* IP0_3 [1] */
-		FN_D3, 0,
-		/* IP0_2 [1] */
-		FN_D2, 0,
-		/* IP0_1 [1] */
-		FN_D1, 0,
-		/* IP0_0 [1] */
-		FN_D0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
-			     GROUP(3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2),
-			     GROUP(
-		/* IP1_31_29 [3] */
-		FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
-		0, 0, 0,
-		/* IP1_28_26 [3] */
-		FN_A17, FN_DACK2_B, 0, FN_I2C0_SDA_C,
-		0, 0, 0, 0,
-		/* IP1_25_23 [3] */
-		FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
-		0, 0, 0,
-		/* IP1_22_20 [3] */
-		FN_A15, FN_BPFCLK_C,
-		0, 0, 0, 0, 0, 0,
-		/* IP1_19_17 [3] */
-		FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
-		0, 0, 0,
-		/* IP1_16_14 [3] */
-		FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
-		0, 0, 0, 0,
-		/* IP1_13_11 [3] */
-		FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
-		0, 0, 0, 0,
-		/* IP1_10_8 [3] */
-		FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
-		0, 0, 0, 0,
-		/* IP1_7_6 [2] */
-		FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
-		/* IP1_5_4 [2] */
-		FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, 0,
-		/* IP1_3_2 [2] */
-		FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0,
-		/* IP1_1_0 [2] */
-		FN_A7, FN_MSIOF1_SYNC,
-		0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
-			     GROUP(2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3),
-			     GROUP(
-		/* IP2_31_30 [2] */
-		0, 0, 0, 0,
-		/* IP2_29_27 [3] */
-		FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
-		FN_ATAG0_N, 0, FN_EX_WAIT1,
-		0, 0,
-		/* IP2_26_25 [2] */
-		FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
-		/* IP2_24_23 [2] */
-		FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
-		/* IP2_22_21 [2] */
-		FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, 0,
-		/* IP2_20_19 [2] */
-		FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, 0,
-		/* IP2_18_16 [3] */
-		FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
-		0, 0,
-		/* IP2_15_13 [3] */
-		FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
-		0, 0, 0,
-		/* IP2_12_10 [3] */
-		FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
-		0, 0, 0,
-		/* IP2_9_7 [3] */
-		FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
-		0, 0, 0,
-		/* IP2_6_5 [2] */
-		FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
-		/* IP2_4_3 [2] */
-		FN_A20, FN_SPCLK, 0, 0,
-		/* IP2_2_0 [3] */
-		FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
-		FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
-			     GROUP(1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3),
-			     GROUP(
-		/* IP3_31 [1] */
-		0, 0,
-		/* IP3_30_28 [3] */
-		FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
-		FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
-		0, 0, 0,
-		/* IP3_27_25 [3] */
-		FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
-		FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
-		0, 0, 0,
-		/* IP3_24_22 [3] */
-		FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
-		FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
-		/* IP3_21_20 [2] */
-		FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
-		/* IP3_19_18 [2] */
-		FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
-		/* IP3_17_16 [2] */
-		FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
-		/* IP3_15_14 [2] */
-		FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
-		/* IP3_13_12 [2] */
-		FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
-		/* IP3_11_9 [3] */
-		FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
-		0, 0, 0,
-		/* IP3_8_6 [3] */
-		FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
-		FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
-		/* IP3_5_3 [3] */
-		FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
-		FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
-		/* IP3_2_0 [3] */
-		FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
-		0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
-			     GROUP(1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2,
-				   3, 3, 2),
-			     GROUP(
-		/* IP4_31 [1] */
-		0, 0,
-		/* IP4_30_28 [3] */
-		FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
-		FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
-		0, 0,
-		/* IP4_27_26 [2] */
-		FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
-		/* IP4_25_24 [2] */
-		FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
-		/* IP4_23_22 [2] */
-		FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
-		/* IP4_21 [1] */
-		FN_SSI_SDATA3, 0,
-		/* IP4_20 [1] */
-		FN_SSI_WS34, 0,
-		/* IP4_19 [1] */
-		FN_SSI_SCK34, 0,
-		/* IP4_18_16 [3] */
-		FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
-		0, 0, 0, 0,
-		/* IP4_15_13 [3] */
-		FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
-		FN_GLO_Q1_D, FN_HCTS1_N_E,
-		0, 0,
-		/* IP4_12_10 [3] */
-		FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
-		0, 0, 0,
-		/* IP4_9_8 [2] */
-		FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
-		/* IP4_7_5 [3] */
-		FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C,
-		FN_GLO_I1_D, 0, 0, 0,
-		/* IP4_4_2 [3] */
-		FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B,
-		FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
-		0, 0, 0,
-		/* IP4_1_0 [2] */
-		FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
-		))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
-			     GROUP(3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3),
-			     GROUP(
-		/* IP5_31_29 [3] */
-		FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
-		0, 0, 0, 0, 0,
-		/* IP5_28_26 [3] */
-		FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
-		0, 0, 0, 0,
-		/* IP5_25_24 [2] */
-		FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
-		/* IP5_23_22 [2] */
-		FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
-		/* IP5_21_20 [2] */
-		FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
-		/* IP5_19_17 [3] */
-		FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
-		0, 0, 0, 0,
-		/* IP5_16_15 [2] */
-		FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
-		/* IP5_14_12 [3] */
-		FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
-		0, 0, 0, 0,
-		/* IP5_11_9 [3] */
-		FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
-		0, 0, 0, 0,
-		/* IP5_8_6 [3] */
-		FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
-		FN_MSIOF2_RXD_D, FN_VI1_R5_B,
-		0, 0,
-		/* IP5_5_3 [3] */
-		FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
-		FN_MSIOF2_SS1_D, FN_VI1_R4_B,
-		0, 0,
-		/* IP5_2_0 [3] */
-		FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
-		FN_MSIOF2_TXD_D, FN_VI1_R3_B,
-		0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
-			     GROUP(2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3),
-			     GROUP(
-		/* IP6_31_30 [2] */
-		0, 0, 0, 0,
-		/* IP6_29_27 [3] */
-		FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
-		FN_GPS_SIGN_C, FN_GPS_SIGN_D,
-		0, 0, 0,
-		/* IP6_26_24 [3] */
-		FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
-		FN_GPS_CLK_C, FN_GPS_CLK_D,
-		0, 0, 0,
-		/* IP6_23_21 [3] */
-		FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
-		FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
-		0, 0, 0,
-		/* IP6_20_19 [2] */
-		FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
-		/* IP6_18_16 [3] */
-		FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
-		FN_INTC_IRQ4_N,	0, 0, 0,
-		/* IP6_15_14 [2] */
-		FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
-		/* IP6_13_12 [2] */
-		FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
-		/* IP6_11_10 [2] */
-		FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
-		/* IP6_9_8 [2] */
-		FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
-		/* IP6_7_6 [2] */
-		FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
-		/* IP6_5_3 [3] */
-		FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
-		FN_SCIFA2_RXD, FN_FMIN_E,
-		0, 0,
-		/* IP6_2_0 [3] */
-		FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
-		FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
-		0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
-			     GROUP(2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3),
-			     GROUP(
-		/* IP7_31_30 [2] */
-		0, 0, 0, 0,
-		/* IP7_29_27 [3] */
-		FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
-		FN_SCIFA1_SCK, FN_SSI_SCK78_B,
-		0, 0,
-		/* IP7_26_24 [3] */
-		FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
-		FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
-		0, 0,
-		/* IP7_23_21 [3] */
-		FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
-		FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
-		0, 0,
-		/* IP7_20_19 [2] */
-		FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
-		/* IP7_18_17 [2] */
-		FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
-		/* IP7_16_15 [2] */
-		FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
-		/* IP7_14_13 [2] */
-		FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
-		/* IP7_12_11 [2] */
-		FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
-		/* IP7_10_9 [2] */
-		FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
-		/* IP7_8_6 [3] */
-		FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
-		FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
-		0, 0,
-		/* IP7_5_3 [3] */
-		FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
-		FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
-		0, 0,
-		/* IP7_2_0 [3] */
-		FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
-		FN_SCIF_CLK_B, FN_GPS_MAG_D,
-		0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
-			     GROUP(1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3),
-			     GROUP(
-		/* IP8_31 [1] */
-		0, 0,
-		/* IP8_30_28 [3] */
-		FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
-		0, 0, 0,
-		/* IP8_27_26 [2] */
-		FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
-		/* IP8_25_24 [2] */
-		FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
-		/* IP8_23_21 [3] */
-		FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
-		FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
-		0, 0,
-		/* IP8_20_18 [3] */
-		FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
-		FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
-		0, 0,
-		/* IP8_17_15 [3] */
-		FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
-		FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
-		0, 0,
-		/* IP8_14_12 [3] */
-		FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
-		FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
-		0, 0, 0,
-		/* IP8_11_9 [3] */
-		FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
-		FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
-		0, 0, 0,
-		/* IP8_8_6 [3] */
-		FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
-		FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
-		0, 0,
-		/* IP8_5_3 [3] */
-		FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
-		FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
-		0, 0,
-		/* IP8_2_0 [3] */
-		FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
-		0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
-			     GROUP(3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3,
-				   1, 1, 3, 3),
-			     GROUP(
-		/* IP9_31_29 [3] */
-		FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
-		FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
-		/* IP9_28_27 [2] */
-		FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
-		/* IP9_26_25 [2] */
-		FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
-		/* IP9_24_23 [2] */
-		FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
-		/* IP9_22_21 [2] */
-		FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
-		/* IP9_20_19 [2] */
-		FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
-		/* IP9_18_17 [2] */
-		FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
-		/* IP9_16 [1] */
-		FN_DU1_DISP, FN_QPOLA,
-		/* IP9_15_13 [3] */
-		FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
-		FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
-		0, 0, 0,
-		/* IP9_12 [1] */
-		FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
-		/* IP9_11 [1] */
-		FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
-		/* IP9_10_8 [3] */
-		FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
-		FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
-		0, 0,
-		/* IP9_7 [1] */
-		FN_DU1_DOTCLKOUT0, FN_QCLK,
-		/* IP9_6 [1] */
-		FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
-		/* IP9_5_3 [3] */
-		FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C,
-		FN_SCIF3_SCK, FN_SCIFA3_SCK,
-		0, 0, 0,
-		/* IP9_2_0 [3] */
-		FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
-		0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
-			     GROUP(3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3),
-			     GROUP(
-		/* IP10_31_29 [3] */
-		FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
-		0, 0, 0,
-		/* IP10_28_27 [2] */
-		FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
-		/* IP10_26_25 [2] */
-		FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
-		/* IP10_24_22 [3] */
-		FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
-		0, 0, 0,
-		/* IP10_21_19 [3] */
-		FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
-		FN_TS_SDATA0_C, FN_ATACS11_N,
-		0, 0, 0,
-		/* IP10_18_17 [2] */
-		FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
-		/* IP10_16_15 [2] */
-		FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
-		/* IP10_14_12 [3] */
-		FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
-		FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
-		/* IP10_11_9 [3] */
-		FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
-		FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
-		0, 0,
-		/* IP10_8_6 [3] */
-		FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
-		FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
-		/* IP10_5_3 [3] */
-		FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
-		FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
-		/* IP10_2_0 [3] */
-		FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
-		FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
-			     GROUP(2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
-				   2, 3, 3, 3, 3, 3),
-			     GROUP(
-		/* IP11_31_30 [2] */
-		FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0,
-		/* IP11_29_28 [2] */
-		FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, 0,
-		/* IP11_27 [1] */
-		FN_VI1_DATA7, FN_AVB_MDC,
-		/* IP11_26 [1] */
-		FN_VI1_DATA6, FN_AVB_MAGIC,
-		/* IP11_25 [1] */
-		FN_VI1_DATA5, FN_AVB_RX_DV,
-		/* IP11_24 [1] */
-		FN_VI1_DATA4, FN_AVB_MDIO,
-		/* IP11_23 [1] */
-		FN_VI1_DATA3, FN_AVB_RX_ER,
-		/* IP11_22 [1] */
-		FN_VI1_DATA2, FN_AVB_RXD7,
-		/* IP11_21 [1] */
-		FN_VI1_DATA1, FN_AVB_RXD6,
-		/* IP11_20 [1] */
-		FN_VI1_DATA0, FN_AVB_RXD5,
-		/* IP11_19 [1] */
-		FN_VI1_CLK, FN_AVB_RXD4,
-		/* IP11_18_17 [2] */
-		FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
-		/* IP11_16_15 [2] */
-		FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
-		/* IP11_14_12 [3] */
-		FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
-		FN_RX4_B, FN_SCIFA4_RXD_B,
-		0, 0, 0,
-		/* IP11_11_9 [3] */
-		FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
-		FN_TX4_B, FN_SCIFA4_TXD_B,
-		0, 0, 0,
-		/* IP11_8_6 [3] */
-		FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
-		FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
-		/* IP11_5_3 [3] */
-		FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
-		0, 0, 0,
-		/* IP11_2_0 [3] */
-		FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C,
-		FN_I2C1_SDA_D, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
-			     GROUP(2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2),
-			     GROUP(
-		/* IP12_31_30 [2] */
-		0, 0, 0, 0,
-		/* IP12_29_27 [3] */
-		FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
-		FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
-		0, 0, 0,
-		/* IP12_26_24 [3] */
-		FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
-		FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
-		0, 0, 0,
-		/* IP12_23_22 [2] */
-		FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
-		/* IP12_21_20 [2] */
-		FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
-		/* IP12_19_18 [2] */
-		FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
-		/* IP12_17_16 [2] */
-		FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
-		/* IP12_15_13 [3] */
-		FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
-		FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
-		0, 0, 0,
-		/* IP12_12_10 [3] */
-		FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
-		FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
-		0, 0, 0,
-		/* IP12_9_7 [3] */
-		FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
-		FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
-		0, 0, 0,
-		/* IP12_6_4 [3] */
-		FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
-		FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
-		0, 0, 0,
-		/* IP12_3_2 [2] */
-		FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
-		/* IP12_1_0 [2] */
-		FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
-			     GROUP(1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1,
-				   1, 1, 1, 3, 2, 2, 3),
-			     GROUP(
-		/* IP13_31 [1] */
-		0, 0,
-		/* IP13_30_28 [3] */
-		FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
-		0, 0, 0, 0,
-		/* IP13_27 [1] */
-		FN_SD1_DATA3, FN_IERX_B,
-		/* IP13_26 [1] */
-		FN_SD1_DATA2, FN_IECLK_B,
-		/* IP13_25 [1] */
-		FN_SD1_DATA1, FN_IETX_B,
-		/* IP13_24_23 [2] */
-		FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
-		/* IP13_22 [1] */
-		FN_SD1_CMD, FN_REMOCON_B,
-		/* IP13_21_19 [3] */
-		FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
-		FN_SCIFA5_RXD_B, FN_RX3_C,
-		0, 0,
-		/* IP13_18_16 [3] */
-		FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
-		FN_SCIFA5_TXD_B, FN_TX3_C,
-		0, 0,
-		/* IP13_15 [1] */
-		FN_SD0_DATA3, FN_SSL_B,
-		/* IP13_14 [1] */
-		FN_SD0_DATA2, FN_IO3_B,
-		/* IP13_13 [1] */
-		FN_SD0_DATA1, FN_IO2_B,
-		/* IP13_12 [1] */
-		FN_SD0_DATA0, FN_MISO_IO1_B,
-		/* IP13_11 [1] */
-		FN_SD0_CMD, FN_MOSI_IO0_B,
-		/* IP13_10 [1] */
-		FN_SD0_CLK, FN_SPCLK_B,
-		/* IP13_9_7 [3] */
-		FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
-		FN_ADICHS2_B, FN_MSIOF0_TXD_C,
-		0, 0, 0,
-		/* IP13_6_5 [2] */
-		FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
-		/* IP13_4_3 [2] */
-		FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
-		/* IP13_2_0 [3] */
-		FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
-		FN_ADICLK_B, FN_MSIOF0_SS1_C,
-		0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
-			     GROUP(3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1,
-				   1, 1, 2),
-			     GROUP(
-		/* IP14_31_29 [3] */
-		FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
-		FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0,
-		/* IP14_28_26 [3] */
-		FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
-		FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, 0,
-		/* IP14_25_23 [3] */
-		FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
-		0, 0, 0,
-		/* IP14_22_20 [3] */
-		FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
-		0, 0, 0,
-		/* IP14_19_17 [3] */
-		FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
-		FN_VI1_CLKENB_C, FN_VI1_G1_B,
-		0, 0,
-		/* IP14_16_14 [3] */
-		FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
-		FN_VI1_CLK_C, FN_VI1_G0_B,
-		0, 0,
-		/* IP14_13_11 [3] */
-		FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
-		0, 0, 0,
-		/* IP14_10_8 [3] */
-		FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
-		0, 0, 0,
-		/* IP14_7 [1] */
-		FN_SD2_DATA3, FN_MMC_D3,
-		/* IP14_6 [1] */
-		FN_SD2_DATA2, FN_MMC_D2,
-		/* IP14_5 [1] */
-		FN_SD2_DATA1, FN_MMC_D1,
-		/* IP14_4 [1] */
-		FN_SD2_DATA0, FN_MMC_D0,
-		/* IP14_3 [1] */
-		FN_SD2_CMD, FN_MMC_CMD,
-		/* IP14_2 [1] */
-		FN_SD2_CLK, FN_MMC_CLK,
-		/* IP14_1_0 [2] */
-		FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
-			     GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2),
-			     GROUP(
-		/* IP15_31_30 [2] */
-		0, 0, 0, 0,
-		/* IP15_29_27 [3] */
-		FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
-		FN_CAN0_TX_B, FN_VI1_DATA5_C,
-		0, 0,
-		/* IP15_26_24 [3] */
-		FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
-		FN_CAN0_RX_B, FN_VI1_DATA4_C,
-		0, 0,
-		/* IP15_23_21 [3] */
-		FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
-		FN_TCLK2, FN_VI1_DATA3_C, 0,
-		/* IP15_20_18 [3] */
-		FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
-		0, 0, 0,
-		/* IP15_17_15 [3] */
-		FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
-		FN_TCLK1, FN_VI1_DATA1_C,
-		0, 0,
-		/* IP15_14_12 [3] */
-		FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
-		FN_VI1_G7_B, FN_SCIFA3_SCK_C,
-		0, 0,
-		/* IP15_11_9 [3] */
-		FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
-		FN_VI1_G6_B, FN_SCIFA3_RXD_C,
-		0, 0,
-		/* IP15_8_6 [3] */
-		FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
-		FN_PWM5_B, FN_SCIFA3_TXD_C,
-		0, 0, 0,
-		/* IP15_5_4 [2] */
-		FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
-		/* IP15_3_2 [2] */
-		FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
-		/* IP15_1_0 [2] */
-		FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
-			     GROUP(4, 4, 4, 4, 4, 2, 2, 2, 3, 3),
-			     GROUP(
-		/* IP16_31_28 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP16_27_24 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP16_23_20 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP16_19_16 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP16_15_12 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP16_11_10 [2] */
-		FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
-		/* IP16_9_8 [2] */
-		FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
-		/* IP16_7_6 [2] */
-		FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
-		/* IP16_5_3 [3] */
-		FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
-		FN_GLO_SS_C, FN_VI1_DATA7_C,
-		0, 0, 0,
-		/* IP16_2_0 [3] */
-		FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
-		FN_GLO_SDATA_C, FN_VI1_DATA6_C,
-		0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
-			     GROUP(1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, 2,
-				   2, 2, 1, 2, 2, 2),
-			     GROUP(
-		/* RESERVED [1] */
-		0, 0,
-		/* SEL_SCIF1 [2] */
-		FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
-		/* SEL_SCIFB [2] */
-		FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
-		/* SEL_SCIFB2 [2] */
-		FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
-		FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
-		/* SEL_SCIFB1 [3] */
-		FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
-		FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
-		0, 0, 0, 0,
-		/* SEL_SCIFA1 [2] */
-		FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
-		/* SEL_SSI9 [1] */
-		FN_SEL_SSI9_0, FN_SEL_SSI9_1,
-		/* SEL_SCFA [1] */
-		FN_SEL_SCFA_0, FN_SEL_SCFA_1,
-		/* SEL_QSP [1] */
-		FN_SEL_QSP_0, FN_SEL_QSP_1,
-		/* SEL_SSI7 [1] */
-		FN_SEL_SSI7_0, FN_SEL_SSI7_1,
-		/* SEL_HSCIF1 [3] */
-		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
-		FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
-		0, 0, 0,
-		/* RESERVED [2] */
-		0, 0, 0, 0,
-		/* SEL_VI1 [2] */
-		FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
-		/* RESERVED [2] */
-		0, 0, 0, 0,
-		/* SEL_TMU [1] */
-		FN_SEL_TMU1_0, FN_SEL_TMU1_1,
-		/* SEL_LBS [2] */
-		FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
-		/* SEL_TSIF0 [2] */
-		FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
-		/* SEL_SOF0 [2] */
-		FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
-			     GROUP(3, 1, 1, 3, 2, 1, 1, 2, 2, 1, 3, 2,
-				   1, 2, 2, 2, 1, 1, 1),
-			     GROUP(
-		/* SEL_SCIF0 [3] */
-		FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
-		FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
-		0, 0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* SEL_SCIF [1] */
-		FN_SEL_SCIF_0, FN_SEL_SCIF_1,
-		/* SEL_CAN0 [3] */
-		FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
-		FN_SEL_CAN0_4, FN_SEL_CAN0_5,
-		0, 0,
-		/* SEL_CAN1 [2] */
-		FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
-		/* RESERVED [1] */
-		0, 0,
-		/* SEL_SCIFA2 [1] */
-		FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
-		/* SEL_SCIF4 [2] */
-		FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
-		/* RESERVED [2] */
-		0, 0, 0, 0,
-		/* SEL_ADG [1] */
-		FN_SEL_ADG_0, FN_SEL_ADG_1,
-		/* SEL_FM [3] */
-		FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
-		FN_SEL_FM_3, FN_SEL_FM_4,
-		0, 0, 0,
-		/* SEL_SCIFA5 [2] */
-		FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* SEL_GPS [2] */
-		FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
-		/* SEL_SCIFA4 [2] */
-		FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
-		/* SEL_SCIFA3 [2] */
-		FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
-		/* SEL_SIM [1] */
-		FN_SEL_SIM_0, FN_SEL_SIM_1,
-		/* RESERVED [1] */
-		0, 0,
-		/* SEL_SSI8 [1] */
-		FN_SEL_SSI8_0, FN_SEL_SSI8_1, ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
-			     GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 2, 2,
-				   3, 2, 2, 2, 1),
-			     GROUP(
-		/* SEL_HSCIF2 [2] */
-		FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
-		FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
-		/* SEL_CANCLK [2] */
-		FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
-		FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
-		/* SEL_IIC1 [2] */
-		FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
-		/* SEL_IIC0 [2] */
-		FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
-		/* SEL_I2C4 [2] */
-		FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, 0,
-		/* SEL_I2C3 [2] */
-		FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
-		/* SEL_SCIF3 [2] */
-		FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
-		/* SEL_IEB [2] */
-		FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
-		/* SEL_MMC [1] */
-		FN_SEL_MMC_0, FN_SEL_MMC_1,
-		/* SEL_SCIF5 [1] */
-		FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
-		/* RESERVED [2] */
-		0, 0, 0, 0,
-		/* SEL_I2C2 [2] */
-		FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
-		/* SEL_I2C1 [3] */
-		FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
-		FN_SEL_I2C1_4,
-		0, 0, 0,
-		/* SEL_I2C0 [2] */
-		FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0,
-		/* RESERVED [2] */
-		0, 0, 0, 0,
-		/* RESERVED [2] */
-		0, 0, 0, 0,
-		/* RESERVED [1] */
-		0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
-			     GROUP(3, 2, 2, 1, 1, 1, 1, 3, 2, 2, 3, 1,
-				   1, 1, 2, 2, 2, 2),
-			     GROUP(
-		/* SEL_SOF1 [3] */
-		FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
-		FN_SEL_SOF1_4,
-		0, 0, 0,
-		/* SEL_HSCIF0 [2] */
-		FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
-		/* SEL_DIS [2] */
-		FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* SEL_RAD [1] */
-		FN_SEL_RAD_0, FN_SEL_RAD_1,
-		/* SEL_RCN [1] */
-		FN_SEL_RCN_0, FN_SEL_RCN_1,
-		/* SEL_RSP [1] */
-		FN_SEL_RSP_0, FN_SEL_RSP_1,
-		/* SEL_SCIF2 [3] */
-		FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
-		FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
-		0, 0, 0,
-		/* RESERVED [2] */
-		0, 0, 0, 0,
-		/* RESERVED [2] */
-		0, 0, 0, 0,
-		/* SEL_SOF2 [3] */
-		FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
-		FN_SEL_SOF2_3, FN_SEL_SOF2_4,
-		0, 0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* SEL_SSI1 [1] */
-		FN_SEL_SSI1_0, FN_SEL_SSI1_1,
-		/* SEL_SSI0 [1] */
-		FN_SEL_SSI0_0, FN_SEL_SSI0_1,
-		/* SEL_SSP [2] */
-		FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
-		/* RESERVED [2] */
-		0, 0, 0, 0,
-		/* RESERVED [2] */
-		0, 0, 0, 0,
-		/* RESERVED [2] */
-		0, 0, 0, 0, ))
-	},
-	{ },
-};
-
-static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
-{
-	if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
-		return -EINVAL;
-
-	*pocctrl = 0xe606008c;
-
-	return 31 - (pin & 0x1f);
-}
-
-static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
-	.pin_to_pocctrl = r8a7791_pin_to_pocctrl,
-};
-
-#ifdef CONFIG_PINCTRL_PFC_R8A7743
-const struct sh_pfc_soc_info r8a7743_pinmux_info = {
-	.name = "r8a77430_pfc",
-	.ops = &r8a7791_pinmux_ops,
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups.common,
-	.nr_groups = ARRAY_SIZE(pinmux_groups.common),
-	.functions = pinmux_functions.common,
-	.nr_functions = ARRAY_SIZE(pinmux_functions.common),
-
-	.cfg_regs = pinmux_config_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
-#endif
-
-#ifdef CONFIG_PINCTRL_PFC_R8A7744
-const struct sh_pfc_soc_info r8a7744_pinmux_info = {
-	.name = "r8a77440_pfc",
-	.ops = &r8a7791_pinmux_ops,
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups.common,
-	.nr_groups = ARRAY_SIZE(pinmux_groups.common),
-	.functions = pinmux_functions.common,
-	.nr_functions = ARRAY_SIZE(pinmux_functions.common),
-
-	.cfg_regs = pinmux_config_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
-#endif
-
-#ifdef CONFIG_PINCTRL_PFC_R8A7791
-const struct sh_pfc_soc_info r8a7791_pinmux_info = {
-	.name = "r8a77910_pfc",
-	.ops = &r8a7791_pinmux_ops,
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups.common,
-	.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
-		     ARRAY_SIZE(pinmux_groups.automotive),
-	.functions = pinmux_functions.common,
-	.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
-			ARRAY_SIZE(pinmux_functions.automotive),
-
-	.cfg_regs = pinmux_config_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
-#endif
-
-#ifdef CONFIG_PINCTRL_PFC_R8A7793
-const struct sh_pfc_soc_info r8a7793_pinmux_info = {
-	.name = "r8a77930_pfc",
-	.ops = &r8a7791_pinmux_ops,
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups.common,
-	.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
-		     ARRAY_SIZE(pinmux_groups.automotive),
-	.functions = pinmux_functions.common,
-	.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
-			ARRAY_SIZE(pinmux_functions.automotive),
-
-	.cfg_regs = pinmux_config_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
-#endif
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
deleted file mode 100644
index 258f82fb31c0..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
+++ /dev/null
@@ -1,2800 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * r8a7792 processor support - PFC hardware block.
- *
- * Copyright (C) 2013-2014 Renesas Electronics Corporation
- * Copyright (C) 2016 Cogent Embedded, Inc., <source@cogentembedded.com>
- */
-
-#include <linux/kernel.h>
-
-#include "core.h"
-#include "sh_pfc.h"
-
-#define CPU_ALL_GP(fn, sfx)						\
-	PORT_GP_29(0, fn, sfx),						\
-	PORT_GP_23(1, fn, sfx),						\
-	PORT_GP_32(2, fn, sfx),						\
-	PORT_GP_28(3, fn, sfx),						\
-	PORT_GP_17(4, fn, sfx),						\
-	PORT_GP_17(5, fn, sfx),						\
-	PORT_GP_17(6, fn, sfx),						\
-	PORT_GP_17(7, fn, sfx),						\
-	PORT_GP_17(8, fn, sfx),						\
-	PORT_GP_17(9, fn, sfx),						\
-	PORT_GP_32(10, fn, sfx),					\
-	PORT_GP_30(11, fn, sfx)
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	GP_ALL(DATA),
-	PINMUX_DATA_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	GP_ALL(FN),
-
-	/* GPSR0 */
-	FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
-	FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
-	FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_16,
-	FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, FN_IP0_21,
-	FN_IP0_22, FN_IP0_23, FN_IP1_0, FN_IP1_1, FN_IP1_2,
-	FN_IP1_3, FN_IP1_4,
-
-	/* GPSR1 */
-	FN_IP1_5, FN_IP1_6, FN_IP1_7, FN_IP1_8, FN_IP1_9, FN_IP1_10,
-	FN_IP1_11, FN_IP1_12, FN_IP1_13, FN_IP1_14, FN_IP1_15, FN_IP1_16,
-	FN_DU1_DB2_C0_DATA12, FN_DU1_DB3_C1_DATA13, FN_DU1_DB4_C2_DATA14,
-	FN_DU1_DB5_C3_DATA15, FN_DU1_DB6_C4, FN_DU1_DB7_C5,
-	FN_DU1_EXHSYNC_DU1_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC,
-	FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_DU1_DISP, FN_DU1_CDE,
-
-	/* GPSR2 */
-	FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7,
-	FN_D8, FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
-	FN_A0, FN_A1, FN_A2, FN_A3, FN_A4, FN_A5, FN_A6, FN_A7,
-	FN_A8, FN_A9, FN_A10, FN_A11, FN_A12, FN_A13, FN_A14, FN_A15,
-
-	/* GPSR3 */
-	FN_A16, FN_A17, FN_A18, FN_A19, FN_IP1_17, FN_IP1_18,
-	FN_CS1_N_A26, FN_EX_CS0_N, FN_EX_CS1_N, FN_EX_CS2_N, FN_EX_CS3_N,
-	FN_EX_CS4_N, FN_EX_CS5_N, FN_BS_N, FN_RD_N, FN_RD_WR_N,
-	FN_WE0_N, FN_WE1_N, FN_EX_WAIT0, FN_IRQ0, FN_IRQ1, FN_IRQ2, FN_IRQ3,
-	FN_IP1_19, FN_IP1_20, FN_IP1_21, FN_IP1_22, FN_CS0_N,
-
-	/* GPSR4 */
-	FN_VI0_CLK, FN_VI0_CLKENB, FN_VI0_HSYNC_N, FN_VI0_VSYNC_N,
-	FN_VI0_D0_B0_C0, FN_VI0_D1_B1_C1, FN_VI0_D2_B2_C2, FN_VI0_D3_B3_C3,
-	FN_VI0_D4_B4_C4, FN_VI0_D5_B5_C5, FN_VI0_D6_B6_C6, FN_VI0_D7_B7_C7,
-	FN_VI0_D8_G0_Y0, FN_VI0_D9_G1_Y1, FN_VI0_D10_G2_Y2, FN_VI0_D11_G3_Y3,
-	FN_VI0_FIELD,
-
-	/* GPSR5 */
-	FN_VI1_CLK, FN_VI1_CLKENB, FN_VI1_HSYNC_N, FN_VI1_VSYNC_N,
-	FN_VI1_D0_B0_C0, FN_VI1_D1_B1_C1, FN_VI1_D2_B2_C2, FN_VI1_D3_B3_C3,
-	FN_VI1_D4_B4_C4, FN_VI1_D5_B5_C5, FN_VI1_D6_B6_C6, FN_VI1_D7_B7_C7,
-	FN_VI1_D8_G0_Y0, FN_VI1_D9_G1_Y1, FN_VI1_D10_G2_Y2, FN_VI1_D11_G3_Y3,
-	FN_VI1_FIELD,
-
-	/* GPSR6 */
-	FN_IP2_0, FN_IP2_1, FN_IP2_2, FN_IP2_3, FN_IP2_4, FN_IP2_5, FN_IP2_6,
-	FN_IP2_7, FN_IP2_8, FN_IP2_9, FN_IP2_10, FN_IP2_11, FN_IP2_12,
-	FN_IP2_13, FN_IP2_14, FN_IP2_15, FN_IP2_16,
-
-	/* GPSR7 */
-	FN_IP3_0, FN_IP3_1, FN_IP3_2, FN_IP3_3, FN_IP3_4, FN_IP3_5, FN_IP3_6,
-	FN_IP3_7, FN_IP3_8, FN_IP3_9, FN_IP3_10, FN_IP3_11, FN_IP3_12,
-	FN_IP3_13, FN_VI3_D10_Y2, FN_IP3_14, FN_VI3_FIELD,
-
-	/* GPSR8 */
-	FN_VI4_CLK, FN_IP4_0, FN_IP4_1, FN_IP4_3_2, FN_IP4_4, FN_IP4_6_5,
-	FN_IP4_8_7, FN_IP4_10_9, FN_IP4_12_11, FN_IP4_14_13, FN_IP4_16_15,
-	FN_IP4_18_17, FN_IP4_20_19, FN_IP4_21, FN_IP4_22, FN_IP4_23, FN_IP4_24,
-
-	/* GPSR9 */
-	FN_VI5_CLK, FN_IP5_0, FN_IP5_1, FN_IP5_2, FN_IP5_3, FN_IP5_4, FN_IP5_5,
-	FN_IP5_6, FN_IP5_7, FN_IP5_8, FN_IP5_9, FN_IP5_10, FN_IP5_11,
-	FN_VI5_D9_Y1, FN_VI5_D10_Y2, FN_VI5_D11_Y3, FN_VI5_FIELD,
-
-	/* GPSR10 */
-	FN_IP6_0, FN_IP6_1, FN_HRTS0_N, FN_IP6_2, FN_IP6_3, FN_IP6_4, FN_IP6_5,
-	FN_HCTS1_N, FN_IP6_6, FN_IP6_7,	FN_SCK0, FN_CTS0_N, FN_RTS0_N,
-	FN_TX0, FN_RX0, FN_SCK1, FN_CTS1_N, FN_RTS1_N, FN_TX1, FN_RX1,
-	FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_16,
-	FN_IP6_18_17, FN_SCIF_CLK, FN_CAN0_TX, FN_CAN0_RX, FN_CAN_CLK,
-	FN_CAN1_TX, FN_CAN1_RX,
-
-	/* GPSR11 */
-	FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_6, FN_IP7_7, FN_SD0_CLK,
-	FN_SD0_CMD, FN_SD0_DAT0, FN_SD0_DAT1, FN_SD0_DAT2, FN_SD0_DAT3,
-	FN_SD0_CD, FN_SD0_WP, FN_IP7_9_8, FN_IP7_11_10, FN_IP7_13_12,
-	FN_IP7_15_14, FN_IP7_16, FN_IP7_17, FN_IP7_18, FN_IP7_19, FN_IP7_20,
-	FN_ADICLK, FN_ADICS_SAMP, FN_ADIDATA, FN_ADICHS0, FN_ADICHS1,
-	FN_ADICHS2, FN_AVS1, FN_AVS2,
-
-	/* IPSR0 */
-	FN_DU0_DR0_DATA0, FN_DU0_DR1_DATA1, FN_DU0_DR2_Y4_DATA2,
-	FN_DU0_DR3_Y5_DATA3, FN_DU0_DR4_Y6_DATA4, FN_DU0_DR5_Y7_DATA5,
-	FN_DU0_DR6_Y8_DATA6, FN_DU0_DR7_Y9_DATA7, FN_DU0_DG0_DATA8,
-	FN_DU0_DG1_DATA9, FN_DU0_DG2_C6_DATA10, FN_DU0_DG3_C7_DATA11,
-	FN_DU0_DG4_Y0_DATA12, FN_DU0_DG5_Y1_DATA13, FN_DU0_DG6_Y2_DATA14,
-	FN_DU0_DG7_Y3_DATA15, FN_DU0_DB0, FN_DU0_DB1, FN_DU0_DB2_C0,
-	FN_DU0_DB3_C1, FN_DU0_DB4_C2, FN_DU0_DB5_C3, FN_DU0_DB6_C4,
-	FN_DU0_DB7_C5,
-
-	/* IPSR1 */
-	FN_DU0_EXHSYNC_DU0_HSYNC, FN_DU0_EXVSYNC_DU0_VSYNC,
-	FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_DU0_DISP, FN_DU0_CDE,
-	FN_DU1_DR2_Y4_DATA0, FN_DU1_DR3_Y5_DATA1, FN_DU1_DR4_Y6_DATA2,
-	FN_DU1_DR5_Y7_DATA3, FN_DU1_DR6_DATA4, FN_DU1_DR7_DATA5,
-	FN_DU1_DG2_C6_DATA6, FN_DU1_DG3_C7_DATA7, FN_DU1_DG4_Y0_DATA8,
-	FN_DU1_DG5_Y1_DATA9, FN_DU1_DG6_Y2_DATA10, FN_DU1_DG7_Y3_DATA11,
-	FN_A20, FN_MOSI_IO0, FN_A21, FN_MISO_IO1, FN_A22, FN_IO2,
-	FN_A23, FN_IO3, FN_A24, FN_SPCLK, FN_A25, FN_SSL,
-
-	/* IPSR2 */
-	FN_VI2_CLK, FN_AVB_RX_CLK, FN_VI2_CLKENB, FN_AVB_RX_DV,
-	FN_VI2_HSYNC_N, FN_AVB_RXD0, FN_VI2_VSYNC_N, FN_AVB_RXD1,
-	FN_VI2_D0_C0, FN_AVB_RXD2, FN_VI2_D1_C1, FN_AVB_RXD3,
-	FN_VI2_D2_C2, FN_AVB_RXD4, FN_VI2_D3_C3, FN_AVB_RXD5,
-	FN_VI2_D4_C4, FN_AVB_RXD6, FN_VI2_D5_C5, FN_AVB_RXD7,
-	FN_VI2_D6_C6, FN_AVB_RX_ER, FN_VI2_D7_C7, FN_AVB_COL,
-	FN_VI2_D8_Y0, FN_AVB_TXD3, FN_VI2_D9_Y1, FN_AVB_TX_EN,
-	FN_VI2_D10_Y2, FN_AVB_TXD0, FN_VI2_D11_Y3, FN_AVB_TXD1,
-	FN_VI2_FIELD, FN_AVB_TXD2,
-
-	/* IPSR3 */
-	FN_VI3_CLK, FN_AVB_TX_CLK, FN_VI3_CLKENB, FN_AVB_TXD4,
-	FN_VI3_HSYNC_N, FN_AVB_TXD5, FN_VI3_VSYNC_N, FN_AVB_TXD6,
-	FN_VI3_D0_C0, FN_AVB_TXD7, FN_VI3_D1_C1, FN_AVB_TX_ER,
-	FN_VI3_D2_C2, FN_AVB_GTX_CLK, FN_VI3_D3_C3, FN_AVB_MDC,
-	FN_VI3_D4_C4, FN_AVB_MDIO, FN_VI3_D5_C5, FN_AVB_LINK,
-	FN_VI3_D6_C6, FN_AVB_MAGIC, FN_VI3_D7_C7, FN_AVB_PHY_INT,
-	FN_VI3_D8_Y0, FN_AVB_CRS, FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
-	FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
-
-	/* IPSR4 */
-	FN_VI4_CLKENB, FN_VI0_D12_G4_Y4, FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
-	FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, FN_RDR_CLKOUT,
-	FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
-	FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4,
-	FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
-	FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6,
-	FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7,
-	FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4,
-	FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5,
-	FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6,
-	FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7,
-	FN_VI4_D9_Y1, FN_VI3_D12_Y4, FN_VI4_D10_Y2, FN_VI3_D13_Y5,
-	FN_VI4_D11_Y3, FN_VI3_D14_Y6, FN_VI4_FIELD, FN_VI3_D15_Y7,
-
-	/* IPSR5 */
-	FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B, FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
-	FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B, FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
-	FN_VI5_D1_C1, FN_VI1_D16_R0, FN_VI5_D2_C2, FN_VI1_D17_R1,
-	FN_VI5_D3_C3, FN_VI1_D18_R2, FN_VI5_D4_C4, FN_VI1_D19_R3,
-	FN_VI5_D5_C5, FN_VI1_D20_R4, FN_VI5_D6_C6, FN_VI1_D21_R5,
-	FN_VI5_D7_C7, FN_VI1_D22_R6, FN_VI5_D8_Y0, FN_VI1_D23_R7,
-
-	/* IPSR6 */
-	FN_MSIOF0_SCK, FN_HSCK0, FN_MSIOF0_SYNC, FN_HCTS0_N,
-	FN_MSIOF0_TXD, FN_HTX0, FN_MSIOF0_RXD, FN_HRX0,
-	FN_MSIOF1_SCK, FN_HSCK1, FN_MSIOF1_SYNC, FN_HRTS1_N,
-	FN_MSIOF1_TXD, FN_HTX1, FN_MSIOF1_RXD, FN_HRX1,
-	FN_DRACK0, FN_SCK2, FN_DACK0, FN_TX2, FN_DREQ0_N, FN_RX2,
-	FN_DACK1, FN_SCK3, FN_TX3, FN_DREQ1_N, FN_RX3,
-
-	/* IPSR7 */
-	FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, FN_PWM1, FN_TCLK2, FN_FSO_CFE_1,
-	FN_PWM2, FN_TCLK3, FN_FSO_TOE, FN_PWM3, FN_PWM4,
-	FN_SSI_SCK34, FN_TPU0TO0, FN_SSI_WS34, FN_TPU0TO1,
-	FN_SSI_SDATA3, FN_TPU0TO2, FN_SSI_SCK4, FN_TPU0TO3,
-	FN_SSI_WS4, FN_SSI_SDATA4, FN_AUDIO_CLKOUT,
-	FN_AUDIO_CLKA, FN_AUDIO_CLKB,
-
-	/* MOD_SEL */
-	FN_SEL_VI1_0, FN_SEL_VI1_1,
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-	DU1_DB2_C0_DATA12_MARK, DU1_DB3_C1_DATA13_MARK,
-	DU1_DB4_C2_DATA14_MARK, DU1_DB5_C3_DATA15_MARK,
-	DU1_DB6_C4_MARK, DU1_DB7_C5_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
-	DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
-	DU1_DISP_MARK, DU1_CDE_MARK,
-
-	D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, D6_MARK,
-	D7_MARK, D8_MARK, D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK,
-	D14_MARK, D15_MARK, A0_MARK, A1_MARK, A2_MARK, A3_MARK, A4_MARK,
-	A5_MARK, A6_MARK, A7_MARK, A8_MARK, A9_MARK, A10_MARK, A11_MARK,
-	A12_MARK, A13_MARK, A14_MARK, A15_MARK,
-
-	A16_MARK, A17_MARK, A18_MARK, A19_MARK, CS1_N_A26_MARK,
-	EX_CS0_N_MARK, EX_CS1_N_MARK, EX_CS2_N_MARK, EX_CS3_N_MARK,
-	EX_CS4_N_MARK, EX_CS5_N_MARK, BS_N_MARK, RD_N_MARK, RD_WR_N_MARK,
-	WE0_N_MARK, WE1_N_MARK, EX_WAIT0_MARK,
-	IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, CS0_N_MARK,
-
-	VI0_CLK_MARK, VI0_CLKENB_MARK, VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
-	VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, VI0_D2_B2_C2_MARK,
-	VI0_D3_B3_C3_MARK, VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
-	VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, VI0_D8_G0_Y0_MARK,
-	VI0_D9_G1_Y1_MARK, VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
-	VI0_FIELD_MARK,
-
-	VI1_CLK_MARK, VI1_CLKENB_MARK, VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
-	VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, VI1_D2_B2_C2_MARK,
-	VI1_D3_B3_C3_MARK, VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
-	VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, VI1_D8_G0_Y0_MARK,
-	VI1_D9_G1_Y1_MARK, VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
-	VI1_FIELD_MARK,
-
-	VI3_D10_Y2_MARK, VI3_FIELD_MARK,
-
-	VI4_CLK_MARK,
-
-	VI5_CLK_MARK, VI5_D9_Y1_MARK, VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
-	VI5_FIELD_MARK,
-
-	HRTS0_N_MARK, HCTS1_N_MARK, SCK0_MARK, CTS0_N_MARK, RTS0_N_MARK,
-	TX0_MARK, RX0_MARK, SCK1_MARK, CTS1_N_MARK, RTS1_N_MARK,
-	TX1_MARK, RX1_MARK, SCIF_CLK_MARK, CAN0_TX_MARK, CAN0_RX_MARK,
-	CAN_CLK_MARK, CAN1_TX_MARK, CAN1_RX_MARK,
-
-	SD0_CLK_MARK, SD0_CMD_MARK, SD0_DAT0_MARK, SD0_DAT1_MARK,
-	SD0_DAT2_MARK, SD0_DAT3_MARK, SD0_CD_MARK, SD0_WP_MARK,
-	ADICLK_MARK, ADICS_SAMP_MARK, ADIDATA_MARK, ADICHS0_MARK,
-	ADICHS1_MARK, ADICHS2_MARK, AVS1_MARK, AVS2_MARK,
-
-	/* IPSR0 */
-	DU0_DR0_DATA0_MARK, DU0_DR1_DATA1_MARK, DU0_DR2_Y4_DATA2_MARK,
-	DU0_DR3_Y5_DATA3_MARK, DU0_DR4_Y6_DATA4_MARK, DU0_DR5_Y7_DATA5_MARK,
-	DU0_DR6_Y8_DATA6_MARK, DU0_DR7_Y9_DATA7_MARK, DU0_DG0_DATA8_MARK,
-	DU0_DG1_DATA9_MARK, DU0_DG2_C6_DATA10_MARK, DU0_DG3_C7_DATA11_MARK,
-	DU0_DG4_Y0_DATA12_MARK, DU0_DG5_Y1_DATA13_MARK, DU0_DG6_Y2_DATA14_MARK,
-	DU0_DG7_Y3_DATA15_MARK, DU0_DB0_MARK, DU0_DB1_MARK,
-	DU0_DB2_C0_MARK, DU0_DB3_C1_MARK, DU0_DB4_C2_MARK, DU0_DB5_C3_MARK,
-	DU0_DB6_C4_MARK, DU0_DB7_C5_MARK,
-
-	/* IPSR1 */
-	DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
-	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, DU0_DISP_MARK, DU0_CDE_MARK,
-	DU1_DR2_Y4_DATA0_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR4_Y6_DATA2_MARK,
-	DU1_DR5_Y7_DATA3_MARK, DU1_DR6_DATA4_MARK, DU1_DR7_DATA5_MARK,
-	DU1_DG2_C6_DATA6_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG4_Y0_DATA8_MARK,
-	DU1_DG5_Y1_DATA9_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG7_Y3_DATA11_MARK,
-	A20_MARK, MOSI_IO0_MARK, A21_MARK, MISO_IO1_MARK, A22_MARK, IO2_MARK,
-	A23_MARK, IO3_MARK, A24_MARK, SPCLK_MARK, A25_MARK, SSL_MARK,
-
-	/* IPSR2 */
-	VI2_CLK_MARK, AVB_RX_CLK_MARK, VI2_CLKENB_MARK, AVB_RX_DV_MARK,
-	VI2_HSYNC_N_MARK, AVB_RXD0_MARK, VI2_VSYNC_N_MARK, AVB_RXD1_MARK,
-	VI2_D0_C0_MARK, AVB_RXD2_MARK, VI2_D1_C1_MARK, AVB_TX_CLK_MARK,
-	VI2_D2_C2_MARK, AVB_RXD4_MARK, VI2_D3_C3_MARK, AVB_RXD5_MARK,
-	VI2_D4_C4_MARK, AVB_RXD6_MARK, VI2_D5_C5_MARK, AVB_RXD7_MARK,
-	VI2_D6_C6_MARK, AVB_RX_ER_MARK, VI2_D7_C7_MARK, AVB_COL_MARK,
-	VI2_D8_Y0_MARK, AVB_RXD3_MARK, VI2_D9_Y1_MARK, AVB_TX_EN_MARK,
-	VI2_D10_Y2_MARK, AVB_TXD0_MARK,
-	VI2_D11_Y3_MARK, AVB_TXD1_MARK, VI2_FIELD_MARK, AVB_TXD2_MARK,
-
-	/* IPSR3 */
-	VI3_CLK_MARK, AVB_TXD3_MARK, VI3_CLKENB_MARK, AVB_TXD4_MARK,
-	VI3_HSYNC_N_MARK, AVB_TXD5_MARK, VI3_VSYNC_N_MARK, AVB_TXD6_MARK,
-	VI3_D0_C0_MARK, AVB_TXD7_MARK, VI3_D1_C1_MARK, AVB_TX_ER_MARK,
-	VI3_D2_C2_MARK, AVB_GTX_CLK_MARK, VI3_D3_C3_MARK, AVB_MDC_MARK,
-	VI3_D4_C4_MARK, AVB_MDIO_MARK, VI3_D5_C5_MARK, AVB_LINK_MARK,
-	VI3_D6_C6_MARK, AVB_MAGIC_MARK, VI3_D7_C7_MARK, AVB_PHY_INT_MARK,
-	VI3_D8_Y0_MARK, AVB_CRS_MARK, VI3_D9_Y1_MARK, AVB_GTXREFCLK_MARK,
-	VI3_D11_Y3_MARK, AVB_AVTP_MATCH_MARK,
-
-	/* IPSR4 */
-	VI4_CLKENB_MARK, VI0_D12_G4_Y4_MARK, VI4_HSYNC_N_MARK,
-	VI0_D13_G5_Y5_MARK, VI4_VSYNC_N_MARK, VI0_D14_G6_Y6_MARK,
-	RDR_CLKOUT_MARK, VI4_D0_C0_MARK, VI0_D15_G7_Y7_MARK, VI4_D1_C1_MARK,
-	VI0_D16_R0_MARK, VI1_D12_G4_Y4_MARK, VI4_D2_C2_MARK, VI0_D17_R1_MARK,
-	VI1_D13_G5_Y5_MARK, VI4_D3_C3_MARK, VI0_D18_R2_MARK, VI1_D14_G6_Y6_MARK,
-	VI4_D4_C4_MARK,	VI0_D19_R3_MARK, VI1_D15_G7_Y7_MARK, VI4_D5_C5_MARK,
-	VI0_D20_R4_MARK, VI2_D12_Y4_MARK, VI4_D6_C6_MARK, VI0_D21_R5_MARK,
-	VI2_D13_Y5_MARK, VI4_D7_C7_MARK, VI0_D22_R6_MARK, VI2_D14_Y6_MARK,
-	VI4_D8_Y0_MARK, VI0_D23_R7_MARK, VI2_D15_Y7_MARK, VI4_D9_Y1_MARK,
-	VI3_D12_Y4_MARK, VI4_D10_Y2_MARK, VI3_D13_Y5_MARK, VI4_D11_Y3_MARK,
-	VI3_D14_Y6_MARK, VI4_FIELD_MARK, VI3_D15_Y7_MARK,
-
-	/* IPSR5 */
-	VI5_CLKENB_MARK, VI1_D12_G4_Y4_B_MARK, VI5_HSYNC_N_MARK,
-	VI1_D13_G5_Y5_B_MARK, VI5_VSYNC_N_MARK, VI1_D14_G6_Y6_B_MARK,
-	VI5_D0_C0_MARK, VI1_D15_G7_Y7_B_MARK, VI5_D1_C1_MARK, VI1_D16_R0_MARK,
-	VI5_D2_C2_MARK, VI1_D17_R1_MARK, VI5_D3_C3_MARK, VI1_D18_R2_MARK,
-	VI5_D4_C4_MARK, VI1_D19_R3_MARK, VI5_D5_C5_MARK, VI1_D20_R4_MARK,
-	VI5_D6_C6_MARK, VI1_D21_R5_MARK, VI5_D7_C7_MARK, VI1_D22_R6_MARK,
-	VI5_D8_Y0_MARK, VI1_D23_R7_MARK,
-
-	/* IPSR6 */
-	MSIOF0_SCK_MARK, HSCK0_MARK, MSIOF0_SYNC_MARK, HCTS0_N_MARK,
-	MSIOF0_TXD_MARK, HTX0_MARK, MSIOF0_RXD_MARK, HRX0_MARK,
-	MSIOF1_SCK_MARK, HSCK1_MARK, MSIOF1_SYNC_MARK, HRTS1_N_MARK,
-	MSIOF1_TXD_MARK, HTX1_MARK, MSIOF1_RXD_MARK, HRX1_MARK,
-	DRACK0_MARK, SCK2_MARK, DACK0_MARK, TX2_MARK, DREQ0_N_MARK,
-	RX2_MARK, DACK1_MARK, SCK3_MARK, TX3_MARK, DREQ1_N_MARK,
-	RX3_MARK,
-
-	/* IPSR7 */
-	PWM0_MARK, TCLK1_MARK, FSO_CFE_0_MARK, PWM1_MARK, TCLK2_MARK,
-	FSO_CFE_1_MARK, PWM2_MARK, TCLK3_MARK, FSO_TOE_MARK, PWM3_MARK,
-	PWM4_MARK, SSI_SCK34_MARK, TPU0TO0_MARK, SSI_WS34_MARK, TPU0TO1_MARK,
-	SSI_SDATA3_MARK, TPU0TO2_MARK, SSI_SCK4_MARK, TPU0TO3_MARK,
-	SSI_WS4_MARK, SSI_SDATA4_MARK, AUDIO_CLKOUT_MARK, AUDIO_CLKA_MARK,
-	AUDIO_CLKB_MARK,
-	PINMUX_MARK_END,
-};
-
-static const u16 pinmux_data[] = {
-	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
-
-	PINMUX_SINGLE(DU1_DB2_C0_DATA12),
-	PINMUX_SINGLE(DU1_DB3_C1_DATA13),
-	PINMUX_SINGLE(DU1_DB4_C2_DATA14),
-	PINMUX_SINGLE(DU1_DB5_C3_DATA15),
-	PINMUX_SINGLE(DU1_DB6_C4),
-	PINMUX_SINGLE(DU1_DB7_C5),
-	PINMUX_SINGLE(DU1_EXHSYNC_DU1_HSYNC),
-	PINMUX_SINGLE(DU1_EXVSYNC_DU1_VSYNC),
-	PINMUX_SINGLE(DU1_EXODDF_DU1_ODDF_DISP_CDE),
-	PINMUX_SINGLE(DU1_DISP),
-	PINMUX_SINGLE(DU1_CDE),
-	PINMUX_SINGLE(D0),
-	PINMUX_SINGLE(D1),
-	PINMUX_SINGLE(D2),
-	PINMUX_SINGLE(D3),
-	PINMUX_SINGLE(D4),
-	PINMUX_SINGLE(D5),
-	PINMUX_SINGLE(D6),
-	PINMUX_SINGLE(D7),
-	PINMUX_SINGLE(D8),
-	PINMUX_SINGLE(D9),
-	PINMUX_SINGLE(D10),
-	PINMUX_SINGLE(D11),
-	PINMUX_SINGLE(D12),
-	PINMUX_SINGLE(D13),
-	PINMUX_SINGLE(D14),
-	PINMUX_SINGLE(D15),
-	PINMUX_SINGLE(A0),
-	PINMUX_SINGLE(A1),
-	PINMUX_SINGLE(A2),
-	PINMUX_SINGLE(A3),
-	PINMUX_SINGLE(A4),
-	PINMUX_SINGLE(A5),
-	PINMUX_SINGLE(A6),
-	PINMUX_SINGLE(A7),
-	PINMUX_SINGLE(A8),
-	PINMUX_SINGLE(A9),
-	PINMUX_SINGLE(A10),
-	PINMUX_SINGLE(A11),
-	PINMUX_SINGLE(A12),
-	PINMUX_SINGLE(A13),
-	PINMUX_SINGLE(A14),
-	PINMUX_SINGLE(A15),
-	PINMUX_SINGLE(A16),
-	PINMUX_SINGLE(A17),
-	PINMUX_SINGLE(A18),
-	PINMUX_SINGLE(A19),
-	PINMUX_SINGLE(CS1_N_A26),
-	PINMUX_SINGLE(EX_CS0_N),
-	PINMUX_SINGLE(EX_CS1_N),
-	PINMUX_SINGLE(EX_CS2_N),
-	PINMUX_SINGLE(EX_CS3_N),
-	PINMUX_SINGLE(EX_CS4_N),
-	PINMUX_SINGLE(EX_CS5_N),
-	PINMUX_SINGLE(BS_N),
-	PINMUX_SINGLE(RD_N),
-	PINMUX_SINGLE(RD_WR_N),
-	PINMUX_SINGLE(WE0_N),
-	PINMUX_SINGLE(WE1_N),
-	PINMUX_SINGLE(EX_WAIT0),
-	PINMUX_SINGLE(IRQ0),
-	PINMUX_SINGLE(IRQ1),
-	PINMUX_SINGLE(IRQ2),
-	PINMUX_SINGLE(IRQ3),
-	PINMUX_SINGLE(CS0_N),
-	PINMUX_SINGLE(VI0_CLK),
-	PINMUX_SINGLE(VI0_CLKENB),
-	PINMUX_SINGLE(VI0_HSYNC_N),
-	PINMUX_SINGLE(VI0_VSYNC_N),
-	PINMUX_SINGLE(VI0_D0_B0_C0),
-	PINMUX_SINGLE(VI0_D1_B1_C1),
-	PINMUX_SINGLE(VI0_D2_B2_C2),
-	PINMUX_SINGLE(VI0_D3_B3_C3),
-	PINMUX_SINGLE(VI0_D4_B4_C4),
-	PINMUX_SINGLE(VI0_D5_B5_C5),
-	PINMUX_SINGLE(VI0_D6_B6_C6),
-	PINMUX_SINGLE(VI0_D7_B7_C7),
-	PINMUX_SINGLE(VI0_D8_G0_Y0),
-	PINMUX_SINGLE(VI0_D9_G1_Y1),
-	PINMUX_SINGLE(VI0_D10_G2_Y2),
-	PINMUX_SINGLE(VI0_D11_G3_Y3),
-	PINMUX_SINGLE(VI0_FIELD),
-	PINMUX_SINGLE(VI1_CLK),
-	PINMUX_SINGLE(VI1_CLKENB),
-	PINMUX_SINGLE(VI1_HSYNC_N),
-	PINMUX_SINGLE(VI1_VSYNC_N),
-	PINMUX_SINGLE(VI1_D0_B0_C0),
-	PINMUX_SINGLE(VI1_D1_B1_C1),
-	PINMUX_SINGLE(VI1_D2_B2_C2),
-	PINMUX_SINGLE(VI1_D3_B3_C3),
-	PINMUX_SINGLE(VI1_D4_B4_C4),
-	PINMUX_SINGLE(VI1_D5_B5_C5),
-	PINMUX_SINGLE(VI1_D6_B6_C6),
-	PINMUX_SINGLE(VI1_D7_B7_C7),
-	PINMUX_SINGLE(VI1_D8_G0_Y0),
-	PINMUX_SINGLE(VI1_D9_G1_Y1),
-	PINMUX_SINGLE(VI1_D10_G2_Y2),
-	PINMUX_SINGLE(VI1_D11_G3_Y3),
-	PINMUX_SINGLE(VI1_FIELD),
-	PINMUX_SINGLE(VI3_D10_Y2),
-	PINMUX_SINGLE(VI3_FIELD),
-	PINMUX_SINGLE(VI4_CLK),
-	PINMUX_SINGLE(VI5_CLK),
-	PINMUX_SINGLE(VI5_D9_Y1),
-	PINMUX_SINGLE(VI5_D10_Y2),
-	PINMUX_SINGLE(VI5_D11_Y3),
-	PINMUX_SINGLE(VI5_FIELD),
-	PINMUX_SINGLE(HRTS0_N),
-	PINMUX_SINGLE(HCTS1_N),
-	PINMUX_SINGLE(SCK0),
-	PINMUX_SINGLE(CTS0_N),
-	PINMUX_SINGLE(RTS0_N),
-	PINMUX_SINGLE(TX0),
-	PINMUX_SINGLE(RX0),
-	PINMUX_SINGLE(SCK1),
-	PINMUX_SINGLE(CTS1_N),
-	PINMUX_SINGLE(RTS1_N),
-	PINMUX_SINGLE(TX1),
-	PINMUX_SINGLE(RX1),
-	PINMUX_SINGLE(SCIF_CLK),
-	PINMUX_SINGLE(CAN0_TX),
-	PINMUX_SINGLE(CAN0_RX),
-	PINMUX_SINGLE(CAN_CLK),
-	PINMUX_SINGLE(CAN1_TX),
-	PINMUX_SINGLE(CAN1_RX),
-	PINMUX_SINGLE(SD0_CLK),
-	PINMUX_SINGLE(SD0_CMD),
-	PINMUX_SINGLE(SD0_DAT0),
-	PINMUX_SINGLE(SD0_DAT1),
-	PINMUX_SINGLE(SD0_DAT2),
-	PINMUX_SINGLE(SD0_DAT3),
-	PINMUX_SINGLE(SD0_CD),
-	PINMUX_SINGLE(SD0_WP),
-	PINMUX_SINGLE(ADICLK),
-	PINMUX_SINGLE(ADICS_SAMP),
-	PINMUX_SINGLE(ADIDATA),
-	PINMUX_SINGLE(ADICHS0),
-	PINMUX_SINGLE(ADICHS1),
-	PINMUX_SINGLE(ADICHS2),
-	PINMUX_SINGLE(AVS1),
-	PINMUX_SINGLE(AVS2),
-
-	/* IPSR0 */
-	PINMUX_IPSR_GPSR(IP0_0, DU0_DR0_DATA0),
-	PINMUX_IPSR_GPSR(IP0_1, DU0_DR1_DATA1),
-	PINMUX_IPSR_GPSR(IP0_2, DU0_DR2_Y4_DATA2),
-	PINMUX_IPSR_GPSR(IP0_3, DU0_DR3_Y5_DATA3),
-	PINMUX_IPSR_GPSR(IP0_4, DU0_DR4_Y6_DATA4),
-	PINMUX_IPSR_GPSR(IP0_5, DU0_DR5_Y7_DATA5),
-	PINMUX_IPSR_GPSR(IP0_6, DU0_DR6_Y8_DATA6),
-	PINMUX_IPSR_GPSR(IP0_7, DU0_DR7_Y9_DATA7),
-	PINMUX_IPSR_GPSR(IP0_8, DU0_DG0_DATA8),
-	PINMUX_IPSR_GPSR(IP0_9, DU0_DG1_DATA9),
-	PINMUX_IPSR_GPSR(IP0_10, DU0_DG2_C6_DATA10),
-	PINMUX_IPSR_GPSR(IP0_11, DU0_DG3_C7_DATA11),
-	PINMUX_IPSR_GPSR(IP0_12, DU0_DG4_Y0_DATA12),
-	PINMUX_IPSR_GPSR(IP0_13, DU0_DG5_Y1_DATA13),
-	PINMUX_IPSR_GPSR(IP0_14, DU0_DG6_Y2_DATA14),
-	PINMUX_IPSR_GPSR(IP0_15, DU0_DG7_Y3_DATA15),
-	PINMUX_IPSR_GPSR(IP0_16, DU0_DB0),
-	PINMUX_IPSR_GPSR(IP0_17, DU0_DB1),
-	PINMUX_IPSR_GPSR(IP0_18, DU0_DB2_C0),
-	PINMUX_IPSR_GPSR(IP0_19, DU0_DB3_C1),
-	PINMUX_IPSR_GPSR(IP0_20, DU0_DB4_C2),
-	PINMUX_IPSR_GPSR(IP0_21, DU0_DB5_C3),
-	PINMUX_IPSR_GPSR(IP0_22, DU0_DB6_C4),
-	PINMUX_IPSR_GPSR(IP0_23, DU0_DB7_C5),
-
-	/* IPSR1 */
-	PINMUX_IPSR_GPSR(IP1_0, DU0_EXHSYNC_DU0_HSYNC),
-	PINMUX_IPSR_GPSR(IP1_1, DU0_EXVSYNC_DU0_VSYNC),
-	PINMUX_IPSR_GPSR(IP1_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
-	PINMUX_IPSR_GPSR(IP1_3, DU0_DISP),
-	PINMUX_IPSR_GPSR(IP1_4, DU0_CDE),
-	PINMUX_IPSR_GPSR(IP1_5, DU1_DR2_Y4_DATA0),
-	PINMUX_IPSR_GPSR(IP1_6, DU1_DR3_Y5_DATA1),
-	PINMUX_IPSR_GPSR(IP1_7, DU1_DR4_Y6_DATA2),
-	PINMUX_IPSR_GPSR(IP1_8, DU1_DR5_Y7_DATA3),
-	PINMUX_IPSR_GPSR(IP1_9, DU1_DR6_DATA4),
-	PINMUX_IPSR_GPSR(IP1_10, DU1_DR7_DATA5),
-	PINMUX_IPSR_GPSR(IP1_11, DU1_DG2_C6_DATA6),
-	PINMUX_IPSR_GPSR(IP1_12, DU1_DG3_C7_DATA7),
-	PINMUX_IPSR_GPSR(IP1_13, DU1_DG4_Y0_DATA8),
-	PINMUX_IPSR_GPSR(IP1_14, DU1_DG5_Y1_DATA9),
-	PINMUX_IPSR_GPSR(IP1_15, DU1_DG6_Y2_DATA10),
-	PINMUX_IPSR_GPSR(IP1_16, DU1_DG7_Y3_DATA11),
-	PINMUX_IPSR_GPSR(IP1_17, A20),
-	PINMUX_IPSR_GPSR(IP1_17, MOSI_IO0),
-	PINMUX_IPSR_GPSR(IP1_18, A21),
-	PINMUX_IPSR_GPSR(IP1_18, MISO_IO1),
-	PINMUX_IPSR_GPSR(IP1_19, A22),
-	PINMUX_IPSR_GPSR(IP1_19, IO2),
-	PINMUX_IPSR_GPSR(IP1_20, A23),
-	PINMUX_IPSR_GPSR(IP1_20, IO3),
-	PINMUX_IPSR_GPSR(IP1_21, A24),
-	PINMUX_IPSR_GPSR(IP1_21, SPCLK),
-	PINMUX_IPSR_GPSR(IP1_22, A25),
-	PINMUX_IPSR_GPSR(IP1_22, SSL),
-
-	/* IPSR2 */
-	PINMUX_IPSR_GPSR(IP2_0, VI2_CLK),
-	PINMUX_IPSR_GPSR(IP2_0, AVB_RX_CLK),
-	PINMUX_IPSR_GPSR(IP2_1, VI2_CLKENB),
-	PINMUX_IPSR_GPSR(IP2_1, AVB_RX_DV),
-	PINMUX_IPSR_GPSR(IP2_2, VI2_HSYNC_N),
-	PINMUX_IPSR_GPSR(IP2_2, AVB_RXD0),
-	PINMUX_IPSR_GPSR(IP2_3, VI2_VSYNC_N),
-	PINMUX_IPSR_GPSR(IP2_3, AVB_RXD1),
-	PINMUX_IPSR_GPSR(IP2_4, VI2_D0_C0),
-	PINMUX_IPSR_GPSR(IP2_4, AVB_RXD2),
-	PINMUX_IPSR_GPSR(IP2_5, VI2_D1_C1),
-	PINMUX_IPSR_GPSR(IP2_5, AVB_RXD3),
-	PINMUX_IPSR_GPSR(IP2_6, VI2_D2_C2),
-	PINMUX_IPSR_GPSR(IP2_6, AVB_RXD4),
-	PINMUX_IPSR_GPSR(IP2_7, VI2_D3_C3),
-	PINMUX_IPSR_GPSR(IP2_7, AVB_RXD5),
-	PINMUX_IPSR_GPSR(IP2_8, VI2_D4_C4),
-	PINMUX_IPSR_GPSR(IP2_8, AVB_RXD6),
-	PINMUX_IPSR_GPSR(IP2_9, VI2_D5_C5),
-	PINMUX_IPSR_GPSR(IP2_9, AVB_RXD7),
-	PINMUX_IPSR_GPSR(IP2_10, VI2_D6_C6),
-	PINMUX_IPSR_GPSR(IP2_10, AVB_RX_ER),
-	PINMUX_IPSR_GPSR(IP2_11, VI2_D7_C7),
-	PINMUX_IPSR_GPSR(IP2_11, AVB_COL),
-	PINMUX_IPSR_GPSR(IP2_12, VI2_D8_Y0),
-	PINMUX_IPSR_GPSR(IP2_12, AVB_TXD3),
-	PINMUX_IPSR_GPSR(IP2_13, VI2_D9_Y1),
-	PINMUX_IPSR_GPSR(IP2_13, AVB_TX_EN),
-	PINMUX_IPSR_GPSR(IP2_14, VI2_D10_Y2),
-	PINMUX_IPSR_GPSR(IP2_14, AVB_TXD0),
-	PINMUX_IPSR_GPSR(IP2_15, VI2_D11_Y3),
-	PINMUX_IPSR_GPSR(IP2_15, AVB_TXD1),
-	PINMUX_IPSR_GPSR(IP2_16, VI2_FIELD),
-	PINMUX_IPSR_GPSR(IP2_16, AVB_TXD2),
-
-	/* IPSR3 */
-	PINMUX_IPSR_GPSR(IP3_0, VI3_CLK),
-	PINMUX_IPSR_GPSR(IP3_0, AVB_TX_CLK),
-	PINMUX_IPSR_GPSR(IP3_1, VI3_CLKENB),
-	PINMUX_IPSR_GPSR(IP3_1, AVB_TXD4),
-	PINMUX_IPSR_GPSR(IP3_2, VI3_HSYNC_N),
-	PINMUX_IPSR_GPSR(IP3_2, AVB_TXD5),
-	PINMUX_IPSR_GPSR(IP3_3, VI3_VSYNC_N),
-	PINMUX_IPSR_GPSR(IP3_3, AVB_TXD6),
-	PINMUX_IPSR_GPSR(IP3_4, VI3_D0_C0),
-	PINMUX_IPSR_GPSR(IP3_4, AVB_TXD7),
-	PINMUX_IPSR_GPSR(IP3_5, VI3_D1_C1),
-	PINMUX_IPSR_GPSR(IP3_5, AVB_TX_ER),
-	PINMUX_IPSR_GPSR(IP3_6, VI3_D2_C2),
-	PINMUX_IPSR_GPSR(IP3_6, AVB_GTX_CLK),
-	PINMUX_IPSR_GPSR(IP3_7, VI3_D3_C3),
-	PINMUX_IPSR_GPSR(IP3_7, AVB_MDC),
-	PINMUX_IPSR_GPSR(IP3_8, VI3_D4_C4),
-	PINMUX_IPSR_GPSR(IP3_8, AVB_MDIO),
-	PINMUX_IPSR_GPSR(IP3_9, VI3_D5_C5),
-	PINMUX_IPSR_GPSR(IP3_9, AVB_LINK),
-	PINMUX_IPSR_GPSR(IP3_10, VI3_D6_C6),
-	PINMUX_IPSR_GPSR(IP3_10, AVB_MAGIC),
-	PINMUX_IPSR_GPSR(IP3_11, VI3_D7_C7),
-	PINMUX_IPSR_GPSR(IP3_11, AVB_PHY_INT),
-	PINMUX_IPSR_GPSR(IP3_12, VI3_D8_Y0),
-	PINMUX_IPSR_GPSR(IP3_12, AVB_CRS),
-	PINMUX_IPSR_GPSR(IP3_13, VI3_D9_Y1),
-	PINMUX_IPSR_GPSR(IP3_13, AVB_GTXREFCLK),
-	PINMUX_IPSR_GPSR(IP3_14, VI3_D11_Y3),
-	PINMUX_IPSR_GPSR(IP3_14, AVB_AVTP_MATCH),
-
-	/* IPSR4 */
-	PINMUX_IPSR_GPSR(IP4_0, VI4_CLKENB),
-	PINMUX_IPSR_GPSR(IP4_0, VI0_D12_G4_Y4),
-	PINMUX_IPSR_GPSR(IP4_1, VI4_HSYNC_N),
-	PINMUX_IPSR_GPSR(IP4_1, VI0_D13_G5_Y5),
-	PINMUX_IPSR_GPSR(IP4_3_2, VI4_VSYNC_N),
-	PINMUX_IPSR_GPSR(IP4_3_2, VI0_D14_G6_Y6),
-	PINMUX_IPSR_GPSR(IP4_4, VI4_D0_C0),
-	PINMUX_IPSR_GPSR(IP4_4, VI0_D15_G7_Y7),
-	PINMUX_IPSR_GPSR(IP4_6_5, VI4_D1_C1),
-	PINMUX_IPSR_GPSR(IP4_6_5, VI0_D16_R0),
-	PINMUX_IPSR_MSEL(IP4_6_5, VI1_D12_G4_Y4, SEL_VI1_0),
-	PINMUX_IPSR_GPSR(IP4_8_7, VI4_D2_C2),
-	PINMUX_IPSR_GPSR(IP4_8_7, VI0_D17_R1),
-	PINMUX_IPSR_MSEL(IP4_8_7, VI1_D13_G5_Y5, SEL_VI1_0),
-	PINMUX_IPSR_GPSR(IP4_10_9, VI4_D3_C3),
-	PINMUX_IPSR_GPSR(IP4_10_9, VI0_D18_R2),
-	PINMUX_IPSR_MSEL(IP4_10_9, VI1_D14_G6_Y6, SEL_VI1_0),
-	PINMUX_IPSR_GPSR(IP4_12_11, VI4_D4_C4),
-	PINMUX_IPSR_GPSR(IP4_12_11, VI0_D19_R3),
-	PINMUX_IPSR_MSEL(IP4_12_11, VI1_D15_G7_Y7, SEL_VI1_0),
-	PINMUX_IPSR_GPSR(IP4_14_13, VI4_D5_C5),
-	PINMUX_IPSR_GPSR(IP4_14_13, VI0_D20_R4),
-	PINMUX_IPSR_GPSR(IP4_14_13, VI2_D12_Y4),
-	PINMUX_IPSR_GPSR(IP4_16_15, VI4_D6_C6),
-	PINMUX_IPSR_GPSR(IP4_16_15, VI0_D21_R5),
-	PINMUX_IPSR_GPSR(IP4_16_15, VI2_D13_Y5),
-	PINMUX_IPSR_GPSR(IP4_18_17, VI4_D7_C7),
-	PINMUX_IPSR_GPSR(IP4_18_17, VI0_D22_R6),
-	PINMUX_IPSR_GPSR(IP4_18_17, VI2_D14_Y6),
-	PINMUX_IPSR_GPSR(IP4_20_19, VI4_D8_Y0),
-	PINMUX_IPSR_GPSR(IP4_20_19, VI0_D23_R7),
-	PINMUX_IPSR_GPSR(IP4_20_19, VI2_D15_Y7),
-	PINMUX_IPSR_GPSR(IP4_21, VI4_D9_Y1),
-	PINMUX_IPSR_GPSR(IP4_21, VI3_D12_Y4),
-	PINMUX_IPSR_GPSR(IP4_22, VI4_D10_Y2),
-	PINMUX_IPSR_GPSR(IP4_22, VI3_D13_Y5),
-	PINMUX_IPSR_GPSR(IP4_23, VI4_D11_Y3),
-	PINMUX_IPSR_GPSR(IP4_23, VI3_D14_Y6),
-	PINMUX_IPSR_GPSR(IP4_24, VI4_FIELD),
-	PINMUX_IPSR_GPSR(IP4_24, VI3_D15_Y7),
-
-	/* IPSR5 */
-	PINMUX_IPSR_GPSR(IP5_0, VI5_CLKENB),
-	PINMUX_IPSR_MSEL(IP5_0, VI1_D12_G4_Y4_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP5_1, VI5_HSYNC_N),
-	PINMUX_IPSR_MSEL(IP5_1, VI1_D13_G5_Y5_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP5_2, VI5_VSYNC_N),
-	PINMUX_IPSR_MSEL(IP5_2, VI1_D14_G6_Y6_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP5_3, VI5_D0_C0),
-	PINMUX_IPSR_MSEL(IP5_3, VI1_D15_G7_Y7_B, SEL_VI1_1),
-	PINMUX_IPSR_GPSR(IP5_4, VI5_D1_C1),
-	PINMUX_IPSR_GPSR(IP5_4, VI1_D16_R0),
-	PINMUX_IPSR_GPSR(IP5_5, VI5_D2_C2),
-	PINMUX_IPSR_GPSR(IP5_5, VI1_D17_R1),
-	PINMUX_IPSR_GPSR(IP5_6, VI5_D3_C3),
-	PINMUX_IPSR_GPSR(IP5_6, VI1_D18_R2),
-	PINMUX_IPSR_GPSR(IP5_7, VI5_D4_C4),
-	PINMUX_IPSR_GPSR(IP5_7, VI1_D19_R3),
-	PINMUX_IPSR_GPSR(IP5_8, VI5_D5_C5),
-	PINMUX_IPSR_GPSR(IP5_8, VI1_D20_R4),
-	PINMUX_IPSR_GPSR(IP5_9, VI5_D6_C6),
-	PINMUX_IPSR_GPSR(IP5_9, VI1_D21_R5),
-	PINMUX_IPSR_GPSR(IP5_10, VI5_D7_C7),
-	PINMUX_IPSR_GPSR(IP5_10, VI1_D22_R6),
-	PINMUX_IPSR_GPSR(IP5_11, VI5_D8_Y0),
-	PINMUX_IPSR_GPSR(IP5_11, VI1_D23_R7),
-
-	/* IPSR6 */
-	PINMUX_IPSR_GPSR(IP6_0, MSIOF0_SCK),
-	PINMUX_IPSR_GPSR(IP6_0, HSCK0),
-	PINMUX_IPSR_GPSR(IP6_1, MSIOF0_SYNC),
-	PINMUX_IPSR_GPSR(IP6_1, HCTS0_N),
-	PINMUX_IPSR_GPSR(IP6_2, MSIOF0_TXD),
-	PINMUX_IPSR_GPSR(IP6_2, HTX0),
-	PINMUX_IPSR_GPSR(IP6_3, MSIOF0_RXD),
-	PINMUX_IPSR_GPSR(IP6_3, HRX0),
-	PINMUX_IPSR_GPSR(IP6_4, MSIOF1_SCK),
-	PINMUX_IPSR_GPSR(IP6_4, HSCK1),
-	PINMUX_IPSR_GPSR(IP6_5, MSIOF1_SYNC),
-	PINMUX_IPSR_GPSR(IP6_5, HRTS1_N),
-	PINMUX_IPSR_GPSR(IP6_6, MSIOF1_TXD),
-	PINMUX_IPSR_GPSR(IP6_6, HTX1),
-	PINMUX_IPSR_GPSR(IP6_7, MSIOF1_RXD),
-	PINMUX_IPSR_GPSR(IP6_7, HRX1),
-	PINMUX_IPSR_GPSR(IP6_9_8, DRACK0),
-	PINMUX_IPSR_GPSR(IP6_9_8, SCK2),
-	PINMUX_IPSR_GPSR(IP6_11_10, DACK0),
-	PINMUX_IPSR_GPSR(IP6_11_10, TX2),
-	PINMUX_IPSR_GPSR(IP6_13_12, DREQ0_N),
-	PINMUX_IPSR_GPSR(IP6_13_12, RX2),
-	PINMUX_IPSR_GPSR(IP6_15_14, DACK1),
-	PINMUX_IPSR_GPSR(IP6_15_14, SCK3),
-	PINMUX_IPSR_GPSR(IP6_16, TX3),
-	PINMUX_IPSR_GPSR(IP6_18_17, DREQ1_N),
-	PINMUX_IPSR_GPSR(IP6_18_17, RX3),
-
-	/* IPSR7 */
-	PINMUX_IPSR_GPSR(IP7_1_0, PWM0),
-	PINMUX_IPSR_GPSR(IP7_1_0, TCLK1),
-	PINMUX_IPSR_GPSR(IP7_1_0, FSO_CFE_0),
-	PINMUX_IPSR_GPSR(IP7_3_2, PWM1),
-	PINMUX_IPSR_GPSR(IP7_3_2, TCLK2),
-	PINMUX_IPSR_GPSR(IP7_3_2, FSO_CFE_1),
-	PINMUX_IPSR_GPSR(IP7_5_4, PWM2),
-	PINMUX_IPSR_GPSR(IP7_5_4, TCLK3),
-	PINMUX_IPSR_GPSR(IP7_5_4, FSO_TOE),
-	PINMUX_IPSR_GPSR(IP7_6, PWM3),
-	PINMUX_IPSR_GPSR(IP7_7, PWM4),
-	PINMUX_IPSR_GPSR(IP7_9_8, SSI_SCK34),
-	PINMUX_IPSR_GPSR(IP7_9_8, TPU0TO0),
-	PINMUX_IPSR_GPSR(IP7_11_10, SSI_WS34),
-	PINMUX_IPSR_GPSR(IP7_11_10, TPU0TO1),
-	PINMUX_IPSR_GPSR(IP7_13_12, SSI_SDATA3),
-	PINMUX_IPSR_GPSR(IP7_13_12, TPU0TO2),
-	PINMUX_IPSR_GPSR(IP7_15_14, SSI_SCK4),
-	PINMUX_IPSR_GPSR(IP7_15_14, TPU0TO3),
-	PINMUX_IPSR_GPSR(IP7_16, SSI_WS4),
-	PINMUX_IPSR_GPSR(IP7_17, SSI_SDATA4),
-	PINMUX_IPSR_GPSR(IP7_18, AUDIO_CLKOUT),
-	PINMUX_IPSR_GPSR(IP7_19, AUDIO_CLKA),
-	PINMUX_IPSR_GPSR(IP7_20, AUDIO_CLKB),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	PINMUX_GPIO_GP_ALL(),
-};
-
-/* - AVB -------------------------------------------------------------------- */
-static const unsigned int avb_link_pins[] = {
-	RCAR_GP_PIN(7, 9),
-};
-static const unsigned int avb_link_mux[] = {
-	AVB_LINK_MARK,
-};
-static const unsigned int avb_magic_pins[] = {
-	RCAR_GP_PIN(7, 10),
-};
-static const unsigned int avb_magic_mux[] = {
-	AVB_MAGIC_MARK,
-};
-static const unsigned int avb_phy_int_pins[] = {
-	RCAR_GP_PIN(7, 11),
-};
-static const unsigned int avb_phy_int_mux[] = {
-	AVB_PHY_INT_MARK,
-};
-static const unsigned int avb_mdio_pins[] = {
-	RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8),
-};
-static const unsigned int avb_mdio_mux[] = {
-	AVB_MDC_MARK, AVB_MDIO_MARK,
-};
-static const unsigned int avb_mii_pins[] = {
-	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
-	RCAR_GP_PIN(6, 12),
-
-	RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 3),  RCAR_GP_PIN(6, 4),
-	RCAR_GP_PIN(6, 5),
-
-	RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0),  RCAR_GP_PIN(6, 1),
-	RCAR_GP_PIN(7, 12), RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5),
-	RCAR_GP_PIN(7, 0),  RCAR_GP_PIN(6, 11),
-};
-static const unsigned int avb_mii_mux[] = {
-	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
-	AVB_TXD3_MARK,
-
-	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
-	AVB_RXD3_MARK,
-
-	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
-	AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
-	AVB_TX_CLK_MARK, AVB_COL_MARK,
-};
-static const unsigned int avb_gmii_pins[] = {
-	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
-	RCAR_GP_PIN(6, 12), RCAR_GP_PIN(7, 1),  RCAR_GP_PIN(7, 2),
-	RCAR_GP_PIN(7, 3),  RCAR_GP_PIN(7, 4),
-
-	RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
-	RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
-	RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 9),
-
-	RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
-	RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 13),
-	RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 0),
-	RCAR_GP_PIN(6, 11),
-};
-static const unsigned int avb_gmii_mux[] = {
-	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
-	AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
-	AVB_TXD6_MARK, AVB_TXD7_MARK,
-
-	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
-	AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
-	AVB_RXD6_MARK, AVB_RXD7_MARK,
-
-	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
-	AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
-	AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
-	AVB_COL_MARK,
-};
-static const unsigned int avb_avtp_match_pins[] = {
-	RCAR_GP_PIN(7, 15),
-};
-static const unsigned int avb_avtp_match_mux[] = {
-	AVB_AVTP_MATCH_MARK,
-};
-/* - CAN -------------------------------------------------------------------- */
-static const unsigned int can0_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(10, 27), RCAR_GP_PIN(10, 28),
-};
-static const unsigned int can0_data_mux[] = {
-	CAN0_TX_MARK, CAN0_RX_MARK,
-};
-static const unsigned int can1_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(10, 30), RCAR_GP_PIN(10, 31),
-};
-static const unsigned int can1_data_mux[] = {
-	CAN1_TX_MARK, CAN1_RX_MARK,
-};
-static const unsigned int can_clk_pins[] = {
-	/* CAN_CLK */
-	RCAR_GP_PIN(10, 29),
-};
-static const unsigned int can_clk_mux[] = {
-	CAN_CLK_MARK,
-};
-/* - DU --------------------------------------------------------------------- */
-static const unsigned int du0_rgb666_pins[] = {
-	/* R[7:2], G[7:2], B[7:2] */
-	RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
-	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
-	RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
-	RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
-};
-static const unsigned int du0_rgb666_mux[] = {
-	DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
-	DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
-	DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
-	DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
-	DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
-	DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
-};
-static const unsigned int du0_rgb888_pins[] = {
-	/* R[7:0], G[7:0], B[7:0] */
-	RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
-	RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
-	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
-	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
-	RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
-	RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
-	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
-};
-static const unsigned int du0_rgb888_mux[] = {
-	DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
-	DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
-	DU0_DR1_DATA1_MARK, DU0_DR0_DATA0_MARK,
-	DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
-	DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
-	DU0_DG1_DATA9_MARK, DU0_DG0_DATA8_MARK,
-	DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
-	DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
-	DU0_DB1_MARK, DU0_DB0_MARK,
-};
-static const unsigned int du0_sync_pins[] = {
-	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
-	RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 24),
-};
-static const unsigned int du0_sync_mux[] = {
-	DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
-};
-static const unsigned int du0_oddf_pins[] = {
-	/* EXODDF/ODDF/DISP/CDE */
-	RCAR_GP_PIN(0, 26),
-};
-static const unsigned int du0_oddf_mux[] = {
-	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
-};
-static const unsigned int du0_disp_pins[] = {
-	/* DISP */
-	RCAR_GP_PIN(0, 27),
-};
-static const unsigned int du0_disp_mux[] = {
-	DU0_DISP_MARK,
-};
-static const unsigned int du0_cde_pins[] = {
-	/* CDE */
-	RCAR_GP_PIN(0, 28),
-};
-static const unsigned int du0_cde_mux[] = {
-	DU0_CDE_MARK,
-};
-static const unsigned int du1_rgb666_pins[] = {
-	/* R[7:2], G[7:2], B[7:2] */
-	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
-	RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
-	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
-	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
-	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
-};
-static const unsigned int du1_rgb666_mux[] = {
-	DU1_DR7_DATA5_MARK, DU1_DR6_DATA4_MARK, DU1_DR5_Y7_DATA3_MARK,
-	DU1_DR4_Y6_DATA2_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR2_Y4_DATA0_MARK,
-	DU1_DG7_Y3_DATA11_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG5_Y1_DATA9_MARK,
-	DU1_DG4_Y0_DATA8_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG2_C6_DATA6_MARK,
-	DU1_DB7_C5_MARK, DU1_DB6_C4_MARK, DU1_DB5_C3_DATA15_MARK,
-	DU1_DB4_C2_DATA14_MARK, DU1_DB3_C1_DATA13_MARK, DU1_DB2_C0_DATA12_MARK,
-};
-static const unsigned int du1_sync_pins[] = {
-	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
-	RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
-};
-static const unsigned int du1_sync_mux[] = {
-	DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
-};
-static const unsigned int du1_oddf_pins[] = {
-	/* EXODDF/ODDF/DISP/CDE */
-	RCAR_GP_PIN(1, 20),
-};
-static const unsigned int du1_oddf_mux[] = {
-	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
-};
-static const unsigned int du1_disp_pins[] = {
-	/* DISP */
-	RCAR_GP_PIN(1, 21),
-};
-static const unsigned int du1_disp_mux[] = {
-	DU1_DISP_MARK,
-};
-static const unsigned int du1_cde_pins[] = {
-	/* CDE */
-	RCAR_GP_PIN(1, 22),
-};
-static const unsigned int du1_cde_mux[] = {
-	DU1_CDE_MARK,
-};
-/* - INTC ------------------------------------------------------------------- */
-static const unsigned int intc_irq0_pins[] = {
-	/* IRQ0 */
-	RCAR_GP_PIN(3, 19),
-};
-static const unsigned int intc_irq0_mux[] = {
-	IRQ0_MARK,
-};
-static const unsigned int intc_irq1_pins[] = {
-	/* IRQ1 */
-	RCAR_GP_PIN(3, 20),
-};
-static const unsigned int intc_irq1_mux[] = {
-	IRQ1_MARK,
-};
-static const unsigned int intc_irq2_pins[] = {
-	/* IRQ2 */
-	RCAR_GP_PIN(3, 21),
-};
-static const unsigned int intc_irq2_mux[] = {
-	IRQ2_MARK,
-};
-static const unsigned int intc_irq3_pins[] = {
-	/* IRQ3 */
-	RCAR_GP_PIN(3, 22),
-};
-static const unsigned int intc_irq3_mux[] = {
-	IRQ3_MARK,
-};
-/* - LBSC ------------------------------------------------------------------- */
-static const unsigned int lbsc_cs0_pins[] = {
-	/* CS0# */
-	RCAR_GP_PIN(3, 27),
-};
-static const unsigned int lbsc_cs0_mux[] = {
-	CS0_N_MARK,
-};
-static const unsigned int lbsc_cs1_pins[] = {
-	/* CS1#_A26 */
-	RCAR_GP_PIN(3, 6),
-};
-static const unsigned int lbsc_cs1_mux[] = {
-	CS1_N_A26_MARK,
-};
-static const unsigned int lbsc_ex_cs0_pins[] = {
-	/* EX_CS0# */
-	RCAR_GP_PIN(3, 7),
-};
-static const unsigned int lbsc_ex_cs0_mux[] = {
-	EX_CS0_N_MARK,
-};
-static const unsigned int lbsc_ex_cs1_pins[] = {
-	/* EX_CS1# */
-	RCAR_GP_PIN(3, 8),
-};
-static const unsigned int lbsc_ex_cs1_mux[] = {
-	EX_CS1_N_MARK,
-};
-static const unsigned int lbsc_ex_cs2_pins[] = {
-	/* EX_CS2# */
-	RCAR_GP_PIN(3, 9),
-};
-static const unsigned int lbsc_ex_cs2_mux[] = {
-	EX_CS2_N_MARK,
-};
-static const unsigned int lbsc_ex_cs3_pins[] = {
-	/* EX_CS3# */
-	RCAR_GP_PIN(3, 10),
-};
-static const unsigned int lbsc_ex_cs3_mux[] = {
-	EX_CS3_N_MARK,
-};
-static const unsigned int lbsc_ex_cs4_pins[] = {
-	/* EX_CS4# */
-	RCAR_GP_PIN(3, 11),
-};
-static const unsigned int lbsc_ex_cs4_mux[] = {
-	EX_CS4_N_MARK,
-};
-static const unsigned int lbsc_ex_cs5_pins[] = {
-	/* EX_CS5# */
-	RCAR_GP_PIN(3, 12),
-};
-static const unsigned int lbsc_ex_cs5_mux[] = {
-	EX_CS5_N_MARK,
-};
-/* - MSIOF0 ----------------------------------------------------------------- */
-static const unsigned int msiof0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(10, 0),
-};
-static const unsigned int msiof0_clk_mux[] = {
-	MSIOF0_SCK_MARK,
-};
-static const unsigned int msiof0_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(10, 1),
-};
-static const unsigned int msiof0_sync_mux[] = {
-	MSIOF0_SYNC_MARK,
-};
-static const unsigned int msiof0_rx_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(10, 4),
-};
-static const unsigned int msiof0_rx_mux[] = {
-	MSIOF0_RXD_MARK,
-};
-static const unsigned int msiof0_tx_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(10, 3),
-};
-static const unsigned int msiof0_tx_mux[] = {
-	MSIOF0_TXD_MARK,
-};
-/* - MSIOF1 ----------------------------------------------------------------- */
-static const unsigned int msiof1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(10, 5),
-};
-static const unsigned int msiof1_clk_mux[] = {
-	MSIOF1_SCK_MARK,
-};
-static const unsigned int msiof1_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(10, 6),
-};
-static const unsigned int msiof1_sync_mux[] = {
-	MSIOF1_SYNC_MARK,
-};
-static const unsigned int msiof1_rx_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(10, 9),
-};
-static const unsigned int msiof1_rx_mux[] = {
-	MSIOF1_RXD_MARK,
-};
-static const unsigned int msiof1_tx_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(10, 8),
-};
-static const unsigned int msiof1_tx_mux[] = {
-	MSIOF1_TXD_MARK,
-};
-/* - QSPI ------------------------------------------------------------------- */
-static const unsigned int qspi_ctrl_pins[] = {
-	/* SPCLK, SSL */
-	RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
-};
-static const unsigned int qspi_ctrl_mux[] = {
-	SPCLK_MARK, SSL_MARK,
-};
-static const unsigned int qspi_data2_pins[] = {
-	/* MOSI_IO0, MISO_IO1 */
-	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
-};
-static const unsigned int qspi_data2_mux[] = {
-	MOSI_IO0_MARK, MISO_IO1_MARK,
-};
-static const unsigned int qspi_data4_pins[] = {
-	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
-	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
-	RCAR_GP_PIN(3, 24),
-};
-static const unsigned int qspi_data4_mux[] = {
-	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK,	IO3_MARK,
-};
-/* - SCIF0 ------------------------------------------------------------------ */
-static const unsigned int scif0_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(10, 14), RCAR_GP_PIN(10, 13),
-};
-static const unsigned int scif0_data_mux[] = {
-	RX0_MARK, TX0_MARK,
-};
-static const unsigned int scif0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(10, 10),
-};
-static const unsigned int scif0_clk_mux[] = {
-	SCK0_MARK,
-};
-static const unsigned int scif0_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(10, 12), RCAR_GP_PIN(10, 11),
-};
-static const unsigned int scif0_ctrl_mux[] = {
-	RTS0_N_MARK, CTS0_N_MARK,
-};
-/* - SCIF1 ------------------------------------------------------------------ */
-static const unsigned int scif1_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(10, 19), RCAR_GP_PIN(10, 18),
-};
-static const unsigned int scif1_data_mux[] = {
-	RX1_MARK, TX1_MARK,
-};
-static const unsigned int scif1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(10, 15),
-};
-static const unsigned int scif1_clk_mux[] = {
-	SCK1_MARK,
-};
-static const unsigned int scif1_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(10, 17), RCAR_GP_PIN(10, 16),
-};
-static const unsigned int scif1_ctrl_mux[] = {
-	RTS1_N_MARK, CTS1_N_MARK,
-};
-/* - SCIF2 ------------------------------------------------------------------ */
-static const unsigned int scif2_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(10, 22), RCAR_GP_PIN(10, 21),
-};
-static const unsigned int scif2_data_mux[] = {
-	RX2_MARK, TX2_MARK,
-};
-static const unsigned int scif2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(10, 20),
-};
-static const unsigned int scif2_clk_mux[] = {
-	SCK2_MARK,
-};
-/* - SCIF3 ------------------------------------------------------------------ */
-static const unsigned int scif3_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(10, 25), RCAR_GP_PIN(10, 24),
-};
-static const unsigned int scif3_data_mux[] = {
-	RX3_MARK, TX3_MARK,
-};
-static const unsigned int scif3_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(10, 23),
-};
-static const unsigned int scif3_clk_mux[] = {
-	SCK3_MARK,
-};
-/* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
-	/* DAT0 */
-	RCAR_GP_PIN(11, 7),
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SD0_DAT0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
-	/* DAT[0-3] */
-	RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8),
-	RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10),
-};
-static const unsigned int sdhi0_data4_mux[] = {
-	SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
-};
-static const unsigned int sdhi0_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(11, 5), RCAR_GP_PIN(11, 6),
-};
-static const unsigned int sdhi0_ctrl_mux[] = {
-	SD0_CLK_MARK, SD0_CMD_MARK,
-};
-static const unsigned int sdhi0_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(11, 11),
-};
-static const unsigned int sdhi0_cd_mux[] = {
-	SD0_CD_MARK,
-};
-static const unsigned int sdhi0_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(11, 12),
-};
-static const unsigned int sdhi0_wp_mux[] = {
-	SD0_WP_MARK,
-};
-/* - VIN0 ------------------------------------------------------------------- */
-static const union vin_data vin0_data_pins = {
-	.data24 = {
-		/* B */
-		RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-		RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
-		RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
-		RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
-		/* G */
-		RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
-		RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
-		RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
-		RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
-		/* R */
-		RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
-		RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
-		RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
-		RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
-	},
-};
-static const union vin_data vin0_data_mux = {
-	.data24 = {
-		/* B */
-		VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,
-		VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
-		VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
-		VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
-		/* G */
-		VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,
-		VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
-		VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
-		VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
-		/* R */
-		VI0_D16_R0_MARK, VI0_D17_R1_MARK,
-		VI0_D18_R2_MARK, VI0_D19_R3_MARK,
-		VI0_D20_R4_MARK, VI0_D21_R5_MARK,
-		VI0_D22_R6_MARK, VI0_D23_R7_MARK,
-	},
-};
-static const unsigned int vin0_data18_pins[] = {
-	/* B */
-	RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
-	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
-	RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
-	/* G */
-	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
-	RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
-	RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
-	/* R */
-	RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
-	RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
-	RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
-};
-static const unsigned int vin0_data18_mux[] = {
-	/* B */
-	VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
-	VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
-	VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
-	/* G */
-	VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
-	VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
-	VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
-	/* R */
-	VI0_D18_R2_MARK, VI0_D19_R3_MARK,
-	VI0_D20_R4_MARK, VI0_D21_R5_MARK,
-	VI0_D22_R6_MARK, VI0_D23_R7_MARK,
-};
-static const unsigned int vin0_sync_pins[] = {
-	/* HSYNC#, VSYNC# */
-	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
-};
-static const unsigned int vin0_sync_mux[] = {
-	VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
-};
-static const unsigned int vin0_field_pins[] = {
-	RCAR_GP_PIN(4, 16),
-};
-static const unsigned int vin0_field_mux[] = {
-	VI0_FIELD_MARK,
-};
-static const unsigned int vin0_clkenb_pins[] = {
-	RCAR_GP_PIN(4, 1),
-};
-static const unsigned int vin0_clkenb_mux[] = {
-	VI0_CLKENB_MARK,
-};
-static const unsigned int vin0_clk_pins[] = {
-	RCAR_GP_PIN(4, 0),
-};
-static const unsigned int vin0_clk_mux[] = {
-	VI0_CLK_MARK,
-};
-/* - VIN1 ------------------------------------------------------------------- */
-static const union vin_data vin1_data_pins = {
-	.data24 = {
-		/* B */
-		RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
-		RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
-		RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
-		RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
-		/* G */
-		RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
-		RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
-		RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
-		RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
-		/* R */
-		RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
-		RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
-		RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
-		RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
-	},
-};
-static const union vin_data vin1_data_mux = {
-	.data24 = {
-		/* B */
-		VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
-		VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
-		VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
-		VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
-		/* G */
-		VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
-		VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
-		VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
-		VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
-		/* R */
-		VI1_D16_R0_MARK, VI1_D17_R1_MARK,
-		VI1_D18_R2_MARK, VI1_D19_R3_MARK,
-		VI1_D20_R4_MARK, VI1_D21_R5_MARK,
-		VI1_D22_R6_MARK, VI1_D23_R7_MARK,
-	},
-};
-static const unsigned int vin1_data18_pins[] = {
-	/* B */
-	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
-	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
-	RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
-	/* G */
-	RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
-	RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
-	RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
-	/* R */
-	RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
-	RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
-	RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
-};
-static const unsigned int vin1_data18_mux[] = {
-	/* B */
-	VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
-	VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
-	VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
-	/* G */
-	VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
-	VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
-	VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
-	/* R */
-	VI1_D18_R2_MARK, VI1_D19_R3_MARK,
-	VI1_D20_R4_MARK, VI1_D21_R5_MARK,
-	VI1_D22_R6_MARK, VI1_D23_R7_MARK,
-};
-static const union vin_data vin1_data_b_pins = {
-	.data24 = {
-		/* B */
-		RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
-		RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
-		RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
-		RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
-		/* G */
-		RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
-		RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
-		RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
-		RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
-		/* R */
-		RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
-		RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
-		RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
-		RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
-	},
-};
-static const union vin_data vin1_data_b_mux = {
-	.data24 = {
-		/* B */
-		VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
-		VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
-		VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
-		VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
-		/* G */
-		VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
-		VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
-		VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
-		VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
-		/* R */
-		VI1_D16_R0_MARK, VI1_D17_R1_MARK,
-		VI1_D18_R2_MARK, VI1_D19_R3_MARK,
-		VI1_D20_R4_MARK, VI1_D21_R5_MARK,
-		VI1_D22_R6_MARK, VI1_D23_R7_MARK,
-	},
-};
-static const unsigned int vin1_data18_b_pins[] = {
-	/* B */
-	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
-	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
-	RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
-	/* G */
-	RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
-	RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
-	RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
-	/* R */
-	RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
-	RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
-	RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
-};
-static const unsigned int vin1_data18_b_mux[] = {
-	/* B */
-	VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
-	VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
-	VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
-	/* G */
-	VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
-	VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
-	VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
-	/* R */
-	VI1_D18_R2_MARK, VI1_D19_R3_MARK,
-	VI1_D20_R4_MARK, VI1_D21_R5_MARK,
-	VI1_D22_R6_MARK, VI1_D23_R7_MARK,
-};
-static const unsigned int vin1_sync_pins[] = {
-	/* HSYNC#, VSYNC# */
-	RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
-};
-static const unsigned int vin1_sync_mux[] = {
-	VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
-};
-static const unsigned int vin1_field_pins[] = {
-	RCAR_GP_PIN(5, 16),
-};
-static const unsigned int vin1_field_mux[] = {
-	VI1_FIELD_MARK,
-};
-static const unsigned int vin1_clkenb_pins[] = {
-	RCAR_GP_PIN(5, 1),
-};
-static const unsigned int vin1_clkenb_mux[] = {
-	VI1_CLKENB_MARK,
-};
-static const unsigned int vin1_clk_pins[] = {
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int vin1_clk_mux[] = {
-	VI1_CLK_MARK,
-};
-/* - VIN2 ------------------------------------------------------------------- */
-static const union vin_data16 vin2_data_pins = {
-	.data16 = {
-		RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
-		RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
-		RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
-		RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
-		RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
-		RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
-		RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
-		RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
-	},
-};
-static const union vin_data16 vin2_data_mux = {
-	.data16 = {
-		VI2_D0_C0_MARK, VI2_D1_C1_MARK,
-		VI2_D2_C2_MARK,	VI2_D3_C3_MARK,
-		VI2_D4_C4_MARK, VI2_D5_C5_MARK,
-		VI2_D6_C6_MARK, VI2_D7_C7_MARK,
-		VI2_D8_Y0_MARK,	VI2_D9_Y1_MARK,
-		VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,
-		VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,
-		VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
-	},
-};
-static const unsigned int vin2_sync_pins[] = {
-	/* HSYNC#, VSYNC# */
-	RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
-};
-static const unsigned int vin2_sync_mux[] = {
-	VI2_HSYNC_N_MARK, VI2_VSYNC_N_MARK,
-};
-static const unsigned int vin2_field_pins[] = {
-	RCAR_GP_PIN(6, 16),
-};
-static const unsigned int vin2_field_mux[] = {
-	VI2_FIELD_MARK,
-};
-static const unsigned int vin2_clkenb_pins[] = {
-	RCAR_GP_PIN(6, 1),
-};
-static const unsigned int vin2_clkenb_mux[] = {
-	VI2_CLKENB_MARK,
-};
-static const unsigned int vin2_clk_pins[] = {
-	RCAR_GP_PIN(6, 0),
-};
-static const unsigned int vin2_clk_mux[] = {
-	VI2_CLK_MARK,
-};
-/* - VIN3 ------------------------------------------------------------------- */
-static const union vin_data16 vin3_data_pins = {
-	.data16 = {
-		RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
-		RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
-		RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
-		RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
-		RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
-		RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
-		RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),
-		RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
-	},
-};
-static const union vin_data16 vin3_data_mux = {
-	.data16 = {
-		VI3_D0_C0_MARK, VI3_D1_C1_MARK,
-		VI3_D2_C2_MARK,	VI3_D3_C3_MARK,
-		VI3_D4_C4_MARK, VI3_D5_C5_MARK,
-		VI3_D6_C6_MARK, VI3_D7_C7_MARK,
-		VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,
-		VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
-		VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
-		VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
-	},
-};
-static const unsigned int vin3_sync_pins[] = {
-	/* HSYNC#, VSYNC# */
-	RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
-};
-static const unsigned int vin3_sync_mux[] = {
-	VI3_HSYNC_N_MARK, VI3_VSYNC_N_MARK,
-};
-static const unsigned int vin3_field_pins[] = {
-	RCAR_GP_PIN(7, 16),
-};
-static const unsigned int vin3_field_mux[] = {
-	VI3_FIELD_MARK,
-};
-static const unsigned int vin3_clkenb_pins[] = {
-	RCAR_GP_PIN(7, 1),
-};
-static const unsigned int vin3_clkenb_mux[] = {
-	VI3_CLKENB_MARK,
-};
-static const unsigned int vin3_clk_pins[] = {
-	RCAR_GP_PIN(7, 0),
-};
-static const unsigned int vin3_clk_mux[] = {
-	VI3_CLK_MARK,
-};
-/* - VIN4 ------------------------------------------------------------------- */
-static const union vin_data12 vin4_data_pins = {
-	.data12 = {
-		RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
-		RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
-		RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
-		RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
-		RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),
-		RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
-	},
-};
-static const union vin_data12 vin4_data_mux = {
-	.data12 = {
-		VI4_D0_C0_MARK, VI4_D1_C1_MARK,
-		VI4_D2_C2_MARK, VI4_D3_C3_MARK,
-		VI4_D4_C4_MARK, VI4_D5_C5_MARK,
-		VI4_D6_C6_MARK, VI4_D7_C7_MARK,
-		VI4_D8_Y0_MARK,	VI4_D9_Y1_MARK,
-		VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
-	},
-};
-static const unsigned int vin4_sync_pins[] = {
-	 /* HSYNC#, VSYNC# */
-	RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
-};
-static const unsigned int vin4_sync_mux[] = {
-	VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
-};
-static const unsigned int vin4_field_pins[] = {
-	RCAR_GP_PIN(8, 16),
-};
-static const unsigned int vin4_field_mux[] = {
-	VI4_FIELD_MARK,
-};
-static const unsigned int vin4_clkenb_pins[] = {
-	RCAR_GP_PIN(8, 1),
-};
-static const unsigned int vin4_clkenb_mux[] = {
-	VI4_CLKENB_MARK,
-};
-static const unsigned int vin4_clk_pins[] = {
-	RCAR_GP_PIN(8, 0),
-};
-static const unsigned int vin4_clk_mux[] = {
-	VI4_CLK_MARK,
-};
-/* - VIN5 ------------------------------------------------------------------- */
-static const union vin_data12 vin5_data_pins = {
-	.data12 = {
-		RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
-		RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
-		RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
-		RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
-		RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),
-		RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
-	},
-};
-static const union vin_data12 vin5_data_mux = {
-	.data12 = {
-		VI5_D0_C0_MARK, VI5_D1_C1_MARK,
-		VI5_D2_C2_MARK, VI5_D3_C3_MARK,
-		VI5_D4_C4_MARK, VI5_D5_C5_MARK,
-		VI5_D6_C6_MARK, VI5_D7_C7_MARK,
-		VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
-		VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
-	},
-};
-static const unsigned int vin5_sync_pins[] = {
-	/* HSYNC#, VSYNC# */
-	RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
-};
-static const unsigned int vin5_sync_mux[] = {
-	VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
-};
-static const unsigned int vin5_field_pins[] = {
-	RCAR_GP_PIN(9, 16),
-};
-static const unsigned int vin5_field_mux[] = {
-	VI5_FIELD_MARK,
-};
-static const unsigned int vin5_clkenb_pins[] = {
-	RCAR_GP_PIN(9, 1),
-};
-static const unsigned int vin5_clkenb_mux[] = {
-	VI5_CLKENB_MARK,
-};
-static const unsigned int vin5_clk_pins[] = {
-	RCAR_GP_PIN(9, 0),
-};
-static const unsigned int vin5_clk_mux[] = {
-	VI5_CLK_MARK,
-};
-
-static const struct sh_pfc_pin_group pinmux_groups[] = {
-	SH_PFC_PIN_GROUP(avb_link),
-	SH_PFC_PIN_GROUP(avb_magic),
-	SH_PFC_PIN_GROUP(avb_phy_int),
-	SH_PFC_PIN_GROUP(avb_mdio),
-	SH_PFC_PIN_GROUP(avb_mii),
-	SH_PFC_PIN_GROUP(avb_gmii),
-	SH_PFC_PIN_GROUP(avb_avtp_match),
-	SH_PFC_PIN_GROUP(can0_data),
-	SH_PFC_PIN_GROUP(can1_data),
-	SH_PFC_PIN_GROUP(can_clk),
-	SH_PFC_PIN_GROUP(du0_rgb666),
-	SH_PFC_PIN_GROUP(du0_rgb888),
-	SH_PFC_PIN_GROUP(du0_sync),
-	SH_PFC_PIN_GROUP(du0_oddf),
-	SH_PFC_PIN_GROUP(du0_disp),
-	SH_PFC_PIN_GROUP(du0_cde),
-	SH_PFC_PIN_GROUP(du1_rgb666),
-	SH_PFC_PIN_GROUP(du1_sync),
-	SH_PFC_PIN_GROUP(du1_oddf),
-	SH_PFC_PIN_GROUP(du1_disp),
-	SH_PFC_PIN_GROUP(du1_cde),
-	SH_PFC_PIN_GROUP(intc_irq0),
-	SH_PFC_PIN_GROUP(intc_irq1),
-	SH_PFC_PIN_GROUP(intc_irq2),
-	SH_PFC_PIN_GROUP(intc_irq3),
-	SH_PFC_PIN_GROUP(lbsc_cs0),
-	SH_PFC_PIN_GROUP(lbsc_cs1),
-	SH_PFC_PIN_GROUP(lbsc_ex_cs0),
-	SH_PFC_PIN_GROUP(lbsc_ex_cs1),
-	SH_PFC_PIN_GROUP(lbsc_ex_cs2),
-	SH_PFC_PIN_GROUP(lbsc_ex_cs3),
-	SH_PFC_PIN_GROUP(lbsc_ex_cs4),
-	SH_PFC_PIN_GROUP(lbsc_ex_cs5),
-	SH_PFC_PIN_GROUP(msiof0_clk),
-	SH_PFC_PIN_GROUP(msiof0_sync),
-	SH_PFC_PIN_GROUP(msiof0_rx),
-	SH_PFC_PIN_GROUP(msiof0_tx),
-	SH_PFC_PIN_GROUP(msiof1_clk),
-	SH_PFC_PIN_GROUP(msiof1_sync),
-	SH_PFC_PIN_GROUP(msiof1_rx),
-	SH_PFC_PIN_GROUP(msiof1_tx),
-	SH_PFC_PIN_GROUP(qspi_ctrl),
-	SH_PFC_PIN_GROUP(qspi_data2),
-	SH_PFC_PIN_GROUP(qspi_data4),
-	SH_PFC_PIN_GROUP(scif0_data),
-	SH_PFC_PIN_GROUP(scif0_clk),
-	SH_PFC_PIN_GROUP(scif0_ctrl),
-	SH_PFC_PIN_GROUP(scif1_data),
-	SH_PFC_PIN_GROUP(scif1_clk),
-	SH_PFC_PIN_GROUP(scif1_ctrl),
-	SH_PFC_PIN_GROUP(scif2_data),
-	SH_PFC_PIN_GROUP(scif2_clk),
-	SH_PFC_PIN_GROUP(scif3_data),
-	SH_PFC_PIN_GROUP(scif3_clk),
-	SH_PFC_PIN_GROUP(sdhi0_data1),
-	SH_PFC_PIN_GROUP(sdhi0_data4),
-	SH_PFC_PIN_GROUP(sdhi0_ctrl),
-	SH_PFC_PIN_GROUP(sdhi0_cd),
-	SH_PFC_PIN_GROUP(sdhi0_wp),
-	VIN_DATA_PIN_GROUP(vin0_data, 24),
-	VIN_DATA_PIN_GROUP(vin0_data, 20),
-	SH_PFC_PIN_GROUP(vin0_data18),
-	VIN_DATA_PIN_GROUP(vin0_data, 16),
-	VIN_DATA_PIN_GROUP(vin0_data, 12),
-	VIN_DATA_PIN_GROUP(vin0_data, 10),
-	VIN_DATA_PIN_GROUP(vin0_data, 8),
-	SH_PFC_PIN_GROUP(vin0_sync),
-	SH_PFC_PIN_GROUP(vin0_field),
-	SH_PFC_PIN_GROUP(vin0_clkenb),
-	SH_PFC_PIN_GROUP(vin0_clk),
-	VIN_DATA_PIN_GROUP(vin1_data, 24),
-	VIN_DATA_PIN_GROUP(vin1_data, 20),
-	SH_PFC_PIN_GROUP(vin1_data18),
-	VIN_DATA_PIN_GROUP(vin1_data, 16),
-	VIN_DATA_PIN_GROUP(vin1_data, 12),
-	VIN_DATA_PIN_GROUP(vin1_data, 10),
-	VIN_DATA_PIN_GROUP(vin1_data, 8),
-	VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
-	VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
-	SH_PFC_PIN_GROUP(vin1_data18_b),
-	VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
-	SH_PFC_PIN_GROUP(vin1_sync),
-	SH_PFC_PIN_GROUP(vin1_field),
-	SH_PFC_PIN_GROUP(vin1_clkenb),
-	SH_PFC_PIN_GROUP(vin1_clk),
-	VIN_DATA_PIN_GROUP(vin2_data, 16),
-	VIN_DATA_PIN_GROUP(vin2_data, 12),
-	VIN_DATA_PIN_GROUP(vin2_data, 10),
-	VIN_DATA_PIN_GROUP(vin2_data, 8),
-	SH_PFC_PIN_GROUP(vin2_sync),
-	SH_PFC_PIN_GROUP(vin2_field),
-	SH_PFC_PIN_GROUP(vin2_clkenb),
-	SH_PFC_PIN_GROUP(vin2_clk),
-	VIN_DATA_PIN_GROUP(vin3_data, 16),
-	VIN_DATA_PIN_GROUP(vin3_data, 12),
-	VIN_DATA_PIN_GROUP(vin3_data, 10),
-	VIN_DATA_PIN_GROUP(vin3_data, 8),
-	SH_PFC_PIN_GROUP(vin3_sync),
-	SH_PFC_PIN_GROUP(vin3_field),
-	SH_PFC_PIN_GROUP(vin3_clkenb),
-	SH_PFC_PIN_GROUP(vin3_clk),
-	VIN_DATA_PIN_GROUP(vin4_data, 12),
-	VIN_DATA_PIN_GROUP(vin4_data, 10),
-	VIN_DATA_PIN_GROUP(vin4_data, 8),
-	SH_PFC_PIN_GROUP(vin4_sync),
-	SH_PFC_PIN_GROUP(vin4_field),
-	SH_PFC_PIN_GROUP(vin4_clkenb),
-	SH_PFC_PIN_GROUP(vin4_clk),
-	VIN_DATA_PIN_GROUP(vin5_data, 12),
-	VIN_DATA_PIN_GROUP(vin5_data, 10),
-	VIN_DATA_PIN_GROUP(vin5_data, 8),
-	SH_PFC_PIN_GROUP(vin5_sync),
-	SH_PFC_PIN_GROUP(vin5_field),
-	SH_PFC_PIN_GROUP(vin5_clkenb),
-	SH_PFC_PIN_GROUP(vin5_clk),
-};
-
-static const char * const avb_groups[] = {
-	"avb_link",
-	"avb_magic",
-	"avb_phy_int",
-	"avb_mdio",
-	"avb_mii",
-	"avb_gmii",
-	"avb_avtp_match",
-};
-
-static const char * const can0_groups[] = {
-	"can0_data",
-	"can_clk",
-};
-
-static const char * const can1_groups[] = {
-	"can1_data",
-	"can_clk",
-};
-
-static const char * const du0_groups[] = {
-	"du0_rgb666",
-	"du0_rgb888",
-	"du0_sync",
-	"du0_oddf",
-	"du0_disp",
-	"du0_cde",
-};
-
-static const char * const du1_groups[] = {
-	"du1_rgb666",
-	"du1_sync",
-	"du1_oddf",
-	"du1_disp",
-	"du1_cde",
-};
-
-static const char * const intc_groups[] = {
-	"intc_irq0",
-	"intc_irq1",
-	"intc_irq2",
-	"intc_irq3",
-};
-
-static const char * const lbsc_groups[] = {
-	"lbsc_cs0",
-	"lbsc_cs1",
-	"lbsc_ex_cs0",
-	"lbsc_ex_cs1",
-	"lbsc_ex_cs2",
-	"lbsc_ex_cs3",
-	"lbsc_ex_cs4",
-	"lbsc_ex_cs5",
-};
-
-static const char * const msiof0_groups[] = {
-	"msiof0_clk",
-	"msiof0_sync",
-	"msiof0_rx",
-	"msiof0_tx",
-};
-
-static const char * const msiof1_groups[] = {
-	"msiof1_clk",
-	"msiof1_sync",
-	"msiof1_rx",
-	"msiof1_tx",
-};
-
-static const char * const qspi_groups[] = {
-	"qspi_ctrl",
-	"qspi_data2",
-	"qspi_data4",
-};
-
-static const char * const scif0_groups[] = {
-	"scif0_data",
-	"scif0_clk",
-	"scif0_ctrl",
-};
-
-static const char * const scif1_groups[] = {
-	"scif1_data",
-	"scif1_clk",
-	"scif1_ctrl",
-};
-
-static const char * const scif2_groups[] = {
-	"scif2_data",
-	"scif2_clk",
-};
-
-static const char * const scif3_groups[] = {
-	"scif3_data",
-	"scif3_clk",
-};
-
-static const char * const sdhi0_groups[] = {
-	"sdhi0_data1",
-	"sdhi0_data4",
-	"sdhi0_ctrl",
-	"sdhi0_cd",
-	"sdhi0_wp",
-};
-
-static const char * const vin0_groups[] = {
-	"vin0_data24",
-	"vin0_data20",
-	"vin0_data18",
-	"vin0_data16",
-	"vin0_data12",
-	"vin0_data10",
-	"vin0_data8",
-	"vin0_sync",
-	"vin0_field",
-	"vin0_clkenb",
-	"vin0_clk",
-};
-
-static const char * const vin1_groups[] = {
-	"vin1_data24",
-	"vin1_data20",
-	"vin1_data18",
-	"vin1_data16",
-	"vin1_data12",
-	"vin1_data10",
-	"vin1_data8",
-	"vin1_data24_b",
-	"vin1_data20_b",
-	"vin1_data18_b",
-	"vin1_data16_b",
-	"vin1_sync",
-	"vin1_field",
-	"vin1_clkenb",
-	"vin1_clk",
-};
-
-static const char * const vin2_groups[] = {
-	"vin2_data16",
-	"vin2_data12",
-	"vin2_data10",
-	"vin2_data8",
-	"vin2_sync",
-	"vin2_field",
-	"vin2_clkenb",
-	"vin2_clk",
-};
-
-static const char * const vin3_groups[] = {
-	"vin3_data16",
-	"vin3_data12",
-	"vin3_data10",
-	"vin3_data8",
-	"vin3_sync",
-	"vin3_field",
-	"vin3_clkenb",
-	"vin3_clk",
-};
-
-static const char * const vin4_groups[] = {
-	"vin4_data12",
-	"vin4_data10",
-	"vin4_data8",
-	"vin4_sync",
-	"vin4_field",
-	"vin4_clkenb",
-	"vin4_clk",
-};
-
-static const char * const vin5_groups[] = {
-	"vin5_data12",
-	"vin5_data10",
-	"vin5_data8",
-	"vin5_sync",
-	"vin5_field",
-	"vin5_clkenb",
-	"vin5_clk",
-};
-
-static const struct sh_pfc_function pinmux_functions[] = {
-	SH_PFC_FUNCTION(avb),
-	SH_PFC_FUNCTION(can0),
-	SH_PFC_FUNCTION(can1),
-	SH_PFC_FUNCTION(du0),
-	SH_PFC_FUNCTION(du1),
-	SH_PFC_FUNCTION(intc),
-	SH_PFC_FUNCTION(lbsc),
-	SH_PFC_FUNCTION(msiof0),
-	SH_PFC_FUNCTION(msiof1),
-	SH_PFC_FUNCTION(qspi),
-	SH_PFC_FUNCTION(scif0),
-	SH_PFC_FUNCTION(scif1),
-	SH_PFC_FUNCTION(scif2),
-	SH_PFC_FUNCTION(scif3),
-	SH_PFC_FUNCTION(sdhi0),
-	SH_PFC_FUNCTION(vin0),
-	SH_PFC_FUNCTION(vin1),
-	SH_PFC_FUNCTION(vin2),
-	SH_PFC_FUNCTION(vin3),
-	SH_PFC_FUNCTION(vin4),
-	SH_PFC_FUNCTION(vin5),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_0_28_FN, FN_IP1_4,
-		GP_0_27_FN, FN_IP1_3,
-		GP_0_26_FN, FN_IP1_2,
-		GP_0_25_FN, FN_IP1_1,
-		GP_0_24_FN, FN_IP1_0,
-		GP_0_23_FN, FN_IP0_23,
-		GP_0_22_FN, FN_IP0_22,
-		GP_0_21_FN, FN_IP0_21,
-		GP_0_20_FN, FN_IP0_20,
-		GP_0_19_FN, FN_IP0_19,
-		GP_0_18_FN, FN_IP0_18,
-		GP_0_17_FN, FN_IP0_17,
-		GP_0_16_FN, FN_IP0_16,
-		GP_0_15_FN, FN_IP0_15,
-		GP_0_14_FN, FN_IP0_14,
-		GP_0_13_FN, FN_IP0_13,
-		GP_0_12_FN, FN_IP0_12,
-		GP_0_11_FN, FN_IP0_11,
-		GP_0_10_FN, FN_IP0_10,
-		GP_0_9_FN, FN_IP0_9,
-		GP_0_8_FN, FN_IP0_8,
-		GP_0_7_FN, FN_IP0_7,
-		GP_0_6_FN, FN_IP0_6,
-		GP_0_5_FN, FN_IP0_5,
-		GP_0_4_FN, FN_IP0_4,
-		GP_0_3_FN, FN_IP0_3,
-		GP_0_2_FN, FN_IP0_2,
-		GP_0_1_FN, FN_IP0_1,
-		GP_0_0_FN, FN_IP0_0 ))
-	},
-	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_1_22_FN, FN_DU1_CDE,
-		GP_1_21_FN, FN_DU1_DISP,
-		GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
-		GP_1_19_FN, FN_DU1_EXVSYNC_DU1_VSYNC,
-		GP_1_18_FN, FN_DU1_EXHSYNC_DU1_HSYNC,
-		GP_1_17_FN, FN_DU1_DB7_C5,
-		GP_1_16_FN, FN_DU1_DB6_C4,
-		GP_1_15_FN, FN_DU1_DB5_C3_DATA15,
-		GP_1_14_FN, FN_DU1_DB4_C2_DATA14,
-		GP_1_13_FN, FN_DU1_DB3_C1_DATA13,
-		GP_1_12_FN, FN_DU1_DB2_C0_DATA12,
-		GP_1_11_FN, FN_IP1_16,
-		GP_1_10_FN, FN_IP1_15,
-		GP_1_9_FN, FN_IP1_14,
-		GP_1_8_FN, FN_IP1_13,
-		GP_1_7_FN, FN_IP1_12,
-		GP_1_6_FN, FN_IP1_11,
-		GP_1_5_FN, FN_IP1_10,
-		GP_1_4_FN, FN_IP1_9,
-		GP_1_3_FN, FN_IP1_8,
-		GP_1_2_FN, FN_IP1_7,
-		GP_1_1_FN, FN_IP1_6,
-		GP_1_0_FN, FN_IP1_5, ))
-	},
-	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
-		GP_2_31_FN, FN_A15,
-		GP_2_30_FN, FN_A14,
-		GP_2_29_FN, FN_A13,
-		GP_2_28_FN, FN_A12,
-		GP_2_27_FN, FN_A11,
-		GP_2_26_FN, FN_A10,
-		GP_2_25_FN, FN_A9,
-		GP_2_24_FN, FN_A8,
-		GP_2_23_FN, FN_A7,
-		GP_2_22_FN, FN_A6,
-		GP_2_21_FN, FN_A5,
-		GP_2_20_FN, FN_A4,
-		GP_2_19_FN, FN_A3,
-		GP_2_18_FN, FN_A2,
-		GP_2_17_FN, FN_A1,
-		GP_2_16_FN, FN_A0,
-		GP_2_15_FN, FN_D15,
-		GP_2_14_FN, FN_D14,
-		GP_2_13_FN, FN_D13,
-		GP_2_12_FN, FN_D12,
-		GP_2_11_FN, FN_D11,
-		GP_2_10_FN, FN_D10,
-		GP_2_9_FN, FN_D9,
-		GP_2_8_FN, FN_D8,
-		GP_2_7_FN, FN_D7,
-		GP_2_6_FN, FN_D6,
-		GP_2_5_FN, FN_D5,
-		GP_2_4_FN, FN_D4,
-		GP_2_3_FN, FN_D3,
-		GP_2_2_FN, FN_D2,
-		GP_2_1_FN, FN_D1,
-		GP_2_0_FN, FN_D0 ))
-	},
-	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_3_27_FN, FN_CS0_N,
-		GP_3_26_FN, FN_IP1_22,
-		GP_3_25_FN, FN_IP1_21,
-		GP_3_24_FN, FN_IP1_20,
-		GP_3_23_FN, FN_IP1_19,
-		GP_3_22_FN, FN_IRQ3,
-		GP_3_21_FN, FN_IRQ2,
-		GP_3_20_FN, FN_IRQ1,
-		GP_3_19_FN, FN_IRQ0,
-		GP_3_18_FN, FN_EX_WAIT0,
-		GP_3_17_FN, FN_WE1_N,
-		GP_3_16_FN, FN_WE0_N,
-		GP_3_15_FN, FN_RD_WR_N,
-		GP_3_14_FN, FN_RD_N,
-		GP_3_13_FN, FN_BS_N,
-		GP_3_12_FN, FN_EX_CS5_N,
-		GP_3_11_FN, FN_EX_CS4_N,
-		GP_3_10_FN, FN_EX_CS3_N,
-		GP_3_9_FN, FN_EX_CS2_N,
-		GP_3_8_FN, FN_EX_CS1_N,
-		GP_3_7_FN, FN_EX_CS0_N,
-		GP_3_6_FN, FN_CS1_N_A26,
-		GP_3_5_FN, FN_IP1_18,
-		GP_3_4_FN, FN_IP1_17,
-		GP_3_3_FN, FN_A19,
-		GP_3_2_FN, FN_A18,
-		GP_3_1_FN, FN_A17,
-		GP_3_0_FN, FN_A16 ))
-	},
-	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_4_16_FN, FN_VI0_FIELD,
-		GP_4_15_FN, FN_VI0_D11_G3_Y3,
-		GP_4_14_FN, FN_VI0_D10_G2_Y2,
-		GP_4_13_FN, FN_VI0_D9_G1_Y1,
-		GP_4_12_FN, FN_VI0_D8_G0_Y0,
-		GP_4_11_FN, FN_VI0_D7_B7_C7,
-		GP_4_10_FN, FN_VI0_D6_B6_C6,
-		GP_4_9_FN, FN_VI0_D5_B5_C5,
-		GP_4_8_FN, FN_VI0_D4_B4_C4,
-		GP_4_7_FN, FN_VI0_D3_B3_C3,
-		GP_4_6_FN, FN_VI0_D2_B2_C2,
-		GP_4_5_FN, FN_VI0_D1_B1_C1,
-		GP_4_4_FN, FN_VI0_D0_B0_C0,
-		GP_4_3_FN, FN_VI0_VSYNC_N,
-		GP_4_2_FN, FN_VI0_HSYNC_N,
-		GP_4_1_FN, FN_VI0_CLKENB,
-		GP_4_0_FN, FN_VI0_CLK ))
-	},
-	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_5_16_FN, FN_VI1_FIELD,
-		GP_5_15_FN, FN_VI1_D11_G3_Y3,
-		GP_5_14_FN, FN_VI1_D10_G2_Y2,
-		GP_5_13_FN, FN_VI1_D9_G1_Y1,
-		GP_5_12_FN, FN_VI1_D8_G0_Y0,
-		GP_5_11_FN, FN_VI1_D7_B7_C7,
-		GP_5_10_FN, FN_VI1_D6_B6_C6,
-		GP_5_9_FN, FN_VI1_D5_B5_C5,
-		GP_5_8_FN, FN_VI1_D4_B4_C4,
-		GP_5_7_FN, FN_VI1_D3_B3_C3,
-		GP_5_6_FN, FN_VI1_D2_B2_C2,
-		GP_5_5_FN, FN_VI1_D1_B1_C1,
-		GP_5_4_FN, FN_VI1_D0_B0_C0,
-		GP_5_3_FN, FN_VI1_VSYNC_N,
-		GP_5_2_FN, FN_VI1_HSYNC_N,
-		GP_5_1_FN, FN_VI1_CLKENB,
-		GP_5_0_FN, FN_VI1_CLK ))
-	},
-	{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_6_16_FN, FN_IP2_16,
-		GP_6_15_FN, FN_IP2_15,
-		GP_6_14_FN, FN_IP2_14,
-		GP_6_13_FN, FN_IP2_13,
-		GP_6_12_FN, FN_IP2_12,
-		GP_6_11_FN, FN_IP2_11,
-		GP_6_10_FN, FN_IP2_10,
-		GP_6_9_FN, FN_IP2_9,
-		GP_6_8_FN, FN_IP2_8,
-		GP_6_7_FN, FN_IP2_7,
-		GP_6_6_FN, FN_IP2_6,
-		GP_6_5_FN, FN_IP2_5,
-		GP_6_4_FN, FN_IP2_4,
-		GP_6_3_FN, FN_IP2_3,
-		GP_6_2_FN, FN_IP2_2,
-		GP_6_1_FN, FN_IP2_1,
-		GP_6_0_FN, FN_IP2_0 ))
-	},
-	{ PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_7_16_FN, FN_VI3_FIELD,
-		GP_7_15_FN, FN_IP3_14,
-		GP_7_14_FN, FN_VI3_D10_Y2,
-		GP_7_13_FN, FN_IP3_13,
-		GP_7_12_FN, FN_IP3_12,
-		GP_7_11_FN, FN_IP3_11,
-		GP_7_10_FN, FN_IP3_10,
-		GP_7_9_FN, FN_IP3_9,
-		GP_7_8_FN, FN_IP3_8,
-		GP_7_7_FN, FN_IP3_7,
-		GP_7_6_FN, FN_IP3_6,
-		GP_7_5_FN, FN_IP3_5,
-		GP_7_4_FN, FN_IP3_4,
-		GP_7_3_FN, FN_IP3_3,
-		GP_7_2_FN, FN_IP3_2,
-		GP_7_1_FN, FN_IP3_1,
-		GP_7_0_FN, FN_IP3_0 ))
-	},
-	{ PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_8_16_FN, FN_IP4_24,
-		GP_8_15_FN, FN_IP4_23,
-		GP_8_14_FN, FN_IP4_22,
-		GP_8_13_FN, FN_IP4_21,
-		GP_8_12_FN, FN_IP4_20_19,
-		GP_8_11_FN, FN_IP4_18_17,
-		GP_8_10_FN, FN_IP4_16_15,
-		GP_8_9_FN, FN_IP4_14_13,
-		GP_8_8_FN, FN_IP4_12_11,
-		GP_8_7_FN, FN_IP4_10_9,
-		GP_8_6_FN, FN_IP4_8_7,
-		GP_8_5_FN, FN_IP4_6_5,
-		GP_8_4_FN, FN_IP4_4,
-		GP_8_3_FN, FN_IP4_3_2,
-		GP_8_2_FN, FN_IP4_1,
-		GP_8_1_FN, FN_IP4_0,
-		GP_8_0_FN, FN_VI4_CLK ))
-	},
-	{ PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_9_16_FN, FN_VI5_FIELD,
-		GP_9_15_FN, FN_VI5_D11_Y3,
-		GP_9_14_FN, FN_VI5_D10_Y2,
-		GP_9_13_FN, FN_VI5_D9_Y1,
-		GP_9_12_FN, FN_IP5_11,
-		GP_9_11_FN, FN_IP5_10,
-		GP_9_10_FN, FN_IP5_9,
-		GP_9_9_FN, FN_IP5_8,
-		GP_9_8_FN, FN_IP5_7,
-		GP_9_7_FN, FN_IP5_6,
-		GP_9_6_FN, FN_IP5_5,
-		GP_9_5_FN, FN_IP5_4,
-		GP_9_4_FN, FN_IP5_3,
-		GP_9_3_FN, FN_IP5_2,
-		GP_9_2_FN, FN_IP5_1,
-		GP_9_1_FN, FN_IP5_0,
-		GP_9_0_FN, FN_VI5_CLK ))
-	},
-	{ PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1, GROUP(
-		GP_10_31_FN, FN_CAN1_RX,
-		GP_10_30_FN, FN_CAN1_TX,
-		GP_10_29_FN, FN_CAN_CLK,
-		GP_10_28_FN, FN_CAN0_RX,
-		GP_10_27_FN, FN_CAN0_TX,
-		GP_10_26_FN, FN_SCIF_CLK,
-		GP_10_25_FN, FN_IP6_18_17,
-		GP_10_24_FN, FN_IP6_16,
-		GP_10_23_FN, FN_IP6_15_14,
-		GP_10_22_FN, FN_IP6_13_12,
-		GP_10_21_FN, FN_IP6_11_10,
-		GP_10_20_FN, FN_IP6_9_8,
-		GP_10_19_FN, FN_RX1,
-		GP_10_18_FN, FN_TX1,
-		GP_10_17_FN, FN_RTS1_N,
-		GP_10_16_FN, FN_CTS1_N,
-		GP_10_15_FN, FN_SCK1,
-		GP_10_14_FN, FN_RX0,
-		GP_10_13_FN, FN_TX0,
-		GP_10_12_FN, FN_RTS0_N,
-		GP_10_11_FN, FN_CTS0_N,
-		GP_10_10_FN, FN_SCK0,
-		GP_10_9_FN, FN_IP6_7,
-		GP_10_8_FN, FN_IP6_6,
-		GP_10_7_FN, FN_HCTS1_N,
-		GP_10_6_FN, FN_IP6_5,
-		GP_10_5_FN, FN_IP6_4,
-		GP_10_4_FN, FN_IP6_3,
-		GP_10_3_FN, FN_IP6_2,
-		GP_10_2_FN, FN_HRTS0_N,
-		GP_10_1_FN, FN_IP6_1,
-		GP_10_0_FN, FN_IP6_0 ))
-	},
-	{ PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		GP_11_29_FN, FN_AVS2,
-		GP_11_28_FN, FN_AVS1,
-		GP_11_27_FN, FN_ADICHS2,
-		GP_11_26_FN, FN_ADICHS1,
-		GP_11_25_FN, FN_ADICHS0,
-		GP_11_24_FN, FN_ADIDATA,
-		GP_11_23_FN, FN_ADICS_SAMP,
-		GP_11_22_FN, FN_ADICLK,
-		GP_11_21_FN, FN_IP7_20,
-		GP_11_20_FN, FN_IP7_19,
-		GP_11_19_FN, FN_IP7_18,
-		GP_11_18_FN, FN_IP7_17,
-		GP_11_17_FN, FN_IP7_16,
-		GP_11_16_FN, FN_IP7_15_14,
-		GP_11_15_FN, FN_IP7_13_12,
-		GP_11_14_FN, FN_IP7_11_10,
-		GP_11_13_FN, FN_IP7_9_8,
-		GP_11_12_FN, FN_SD0_WP,
-		GP_11_11_FN, FN_SD0_CD,
-		GP_11_10_FN, FN_SD0_DAT3,
-		GP_11_9_FN, FN_SD0_DAT2,
-		GP_11_8_FN, FN_SD0_DAT1,
-		GP_11_7_FN, FN_SD0_DAT0,
-		GP_11_6_FN, FN_SD0_CMD,
-		GP_11_5_FN, FN_SD0_CLK,
-		GP_11_4_FN, FN_IP7_7,
-		GP_11_3_FN, FN_IP7_6,
-		GP_11_2_FN, FN_IP7_5_4,
-		GP_11_1_FN, FN_IP7_3_2,
-		GP_11_0_FN, FN_IP7_1_0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
-			     GROUP(4, 4,
-				   1, 1, 1, 1, 1, 1, 1, 1,
-				   1, 1, 1, 1, 1, 1, 1, 1,
-				   1, 1, 1, 1, 1, 1, 1, 1),
-			     GROUP(
-		/* IP0_31_28 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP0_27_24 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP0_23 [1] */
-		FN_DU0_DB7_C5, 0,
-		/* IP0_22 [1] */
-		FN_DU0_DB6_C4, 0,
-		/* IP0_21 [1] */
-		FN_DU0_DB5_C3, 0,
-		/* IP0_20 [1] */
-		FN_DU0_DB4_C2, 0,
-		/* IP0_19 [1] */
-		FN_DU0_DB3_C1, 0,
-		/* IP0_18 [1] */
-		FN_DU0_DB2_C0, 0,
-		/* IP0_17 [1] */
-		FN_DU0_DB1, 0,
-		/* IP0_16 [1] */
-		FN_DU0_DB0, 0,
-		/* IP0_15 [1] */
-		FN_DU0_DG7_Y3_DATA15, 0,
-		/* IP0_14 [1] */
-		FN_DU0_DG6_Y2_DATA14, 0,
-		/* IP0_13 [1] */
-		FN_DU0_DG5_Y1_DATA13, 0,
-		/* IP0_12 [1] */
-		FN_DU0_DG4_Y0_DATA12, 0,
-		/* IP0_11 [1] */
-		FN_DU0_DG3_C7_DATA11, 0,
-		/* IP0_10 [1] */
-		FN_DU0_DG2_C6_DATA10, 0,
-		/* IP0_9 [1] */
-		FN_DU0_DG1_DATA9, 0,
-		/* IP0_8 [1] */
-		FN_DU0_DG0_DATA8, 0,
-		/* IP0_7 [1] */
-		FN_DU0_DR7_Y9_DATA7, 0,
-		/* IP0_6 [1] */
-		FN_DU0_DR6_Y8_DATA6, 0,
-		/* IP0_5 [1] */
-		FN_DU0_DR5_Y7_DATA5, 0,
-		/* IP0_4 [1] */
-		FN_DU0_DR4_Y6_DATA4, 0,
-		/* IP0_3 [1] */
-		FN_DU0_DR3_Y5_DATA3, 0,
-		/* IP0_2 [1] */
-		FN_DU0_DR2_Y4_DATA2, 0,
-		/* IP0_1 [1] */
-		FN_DU0_DR1_DATA1, 0,
-		/* IP0_0 [1] */
-		FN_DU0_DR0_DATA0, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
-			     GROUP(4, 4,
-				   1, 1, 1, 1, 1, 1, 1, 1,
-				   1, 1, 1, 1, 1, 1, 1, 1,
-				   1, 1, 1, 1, 1, 1, 1, 1),
-			     GROUP(
-		/* IP1_31_28 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP1_27_24 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP1_23 [1] */
-		0, 0,
-		/* IP1_22 [1] */
-		FN_A25, FN_SSL,
-		/* IP1_21 [1] */
-		FN_A24, FN_SPCLK,
-		/* IP1_20 [1] */
-		FN_A23, FN_IO3,
-		/* IP1_19 [1] */
-		FN_A22, FN_IO2,
-		/* IP1_18 [1] */
-		FN_A21, FN_MISO_IO1,
-		/* IP1_17 [1] */
-		FN_A20, FN_MOSI_IO0,
-		/* IP1_16 [1] */
-		FN_DU1_DG7_Y3_DATA11, 0,
-		/* IP1_15 [1] */
-		FN_DU1_DG6_Y2_DATA10, 0,
-		/* IP1_14 [1] */
-		FN_DU1_DG5_Y1_DATA9, 0,
-		/* IP1_13 [1] */
-		FN_DU1_DG4_Y0_DATA8, 0,
-		/* IP1_12 [1] */
-		FN_DU1_DG3_C7_DATA7, 0,
-		/* IP1_11 [1] */
-		FN_DU1_DG2_C6_DATA6, 0,
-		/* IP1_10 [1] */
-		FN_DU1_DR7_DATA5, 0,
-		/* IP1_9 [1] */
-		FN_DU1_DR6_DATA4, 0,
-		/* IP1_8 [1] */
-		FN_DU1_DR5_Y7_DATA3, 0,
-		/* IP1_7 [1] */
-		FN_DU1_DR4_Y6_DATA2, 0,
-		/* IP1_6 [1] */
-		FN_DU1_DR3_Y5_DATA1, 0,
-		/* IP1_5 [1] */
-		FN_DU1_DR2_Y4_DATA0, 0,
-		/* IP1_4 [1] */
-		FN_DU0_CDE, 0,
-		/* IP1_3 [1] */
-		FN_DU0_DISP, 0,
-		/* IP1_2 [1] */
-		FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0,
-		/* IP1_1 [1] */
-		FN_DU0_EXVSYNC_DU0_VSYNC, 0,
-		/* IP1_0 [1] */
-		FN_DU0_EXHSYNC_DU0_HSYNC, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
-			     GROUP(4, 4,
-				   4, 3, 1,
-				   1, 1, 1, 1, 1, 1, 1, 1,
-				   1, 1, 1, 1, 1, 1, 1, 1),
-			     GROUP(
-		/* IP2_31_28 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP2_27_24 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP2_23_20 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP2_19_17 [3] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP2_16 [1] */
-		FN_VI2_FIELD, FN_AVB_TXD2,
-		/* IP2_15 [1] */
-		FN_VI2_D11_Y3, FN_AVB_TXD1,
-		/* IP2_14 [1] */
-		FN_VI2_D10_Y2, FN_AVB_TXD0,
-		/* IP2_13 [1] */
-		FN_VI2_D9_Y1, FN_AVB_TX_EN,
-		/* IP2_12 [1] */
-		FN_VI2_D8_Y0, FN_AVB_TXD3,
-		/* IP2_11 [1] */
-		FN_VI2_D7_C7, FN_AVB_COL,
-		/* IP2_10 [1] */
-		FN_VI2_D6_C6, FN_AVB_RX_ER,
-		/* IP2_9 [1] */
-		FN_VI2_D5_C5, FN_AVB_RXD7,
-		/* IP2_8 [1] */
-		FN_VI2_D4_C4, FN_AVB_RXD6,
-		/* IP2_7 [1] */
-		FN_VI2_D3_C3, FN_AVB_RXD5,
-		/* IP2_6 [1] */
-		FN_VI2_D2_C2, FN_AVB_RXD4,
-		/* IP2_5 [1] */
-		FN_VI2_D1_C1, FN_AVB_RXD3,
-		/* IP2_4 [1] */
-		FN_VI2_D0_C0, FN_AVB_RXD2,
-		/* IP2_3 [1] */
-		FN_VI2_VSYNC_N, FN_AVB_RXD1,
-		/* IP2_2 [1] */
-		FN_VI2_HSYNC_N, FN_AVB_RXD0,
-		/* IP2_1 [1] */
-		FN_VI2_CLKENB, FN_AVB_RX_DV,
-		/* IP2_0 [1] */
-		FN_VI2_CLK, FN_AVB_RX_CLK ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
-			     GROUP(4, 4,
-				   4, 4,
-				   1, 1, 1, 1, 1, 1, 1, 1,
-				   1, 1, 1, 1, 1, 1, 1, 1),
-			     GROUP(
-		/* IP3_31_28 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP3_27_24 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP3_23_20 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP3_19_16 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP3_15 [1] */
-		0, 0,
-		/* IP3_14 [1] */
-		FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
-		/* IP3_13 [1] */
-		FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
-		/* IP3_12 [1] */
-		FN_VI3_D8_Y0, FN_AVB_CRS,
-		/* IP3_11 [1] */
-		FN_VI3_D7_C7, FN_AVB_PHY_INT,
-		/* IP3_10 [1] */
-		FN_VI3_D6_C6, FN_AVB_MAGIC,
-		/* IP3_9 [1] */
-		FN_VI3_D5_C5, FN_AVB_LINK,
-		/* IP3_8 [1] */
-		FN_VI3_D4_C4, FN_AVB_MDIO,
-		/* IP3_7 [1] */
-		FN_VI3_D3_C3, FN_AVB_MDC,
-		/* IP3_6 [1] */
-		FN_VI3_D2_C2, FN_AVB_GTX_CLK,
-		/* IP3_5 [1] */
-		FN_VI3_D1_C1, FN_AVB_TX_ER,
-		/* IP3_4 [1] */
-		FN_VI3_D0_C0, FN_AVB_TXD7,
-		/* IP3_3 [1] */
-		FN_VI3_VSYNC_N, FN_AVB_TXD6,
-		/* IP3_2 [1] */
-		FN_VI3_HSYNC_N, FN_AVB_TXD5,
-		/* IP3_1 [1] */
-		FN_VI3_CLKENB, FN_AVB_TXD4,
-		/* IP3_0 [1] */
-		FN_VI3_CLK, FN_AVB_TX_CLK ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
-			     GROUP(4, 3, 1,
-				   1, 1, 1, 2, 2, 2,
-				   2, 2, 2, 2, 2, 1, 2, 1, 1),
-			     GROUP(
-		/* IP4_31_28 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP4_27_25 [3] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP4_24 [1] */
-		FN_VI4_FIELD, FN_VI3_D15_Y7,
-		/* IP4_23 [1] */
-		FN_VI4_D11_Y3, FN_VI3_D14_Y6,
-		/* IP4_22 [1] */
-		FN_VI4_D10_Y2, FN_VI3_D13_Y5,
-		/* IP4_21 [1] */
-		FN_VI4_D9_Y1, FN_VI3_D12_Y4,
-		/* IP4_20_19 [2] */
-		FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, 0,
-		/* IP4_18_17 [2] */
-		FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, 0,
-		/* IP4_16_15 [2] */
-		FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, 0,
-		/* IP4_14_13 [2] */
-		FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, 0,
-		/* IP4_12_11 [2] */
-		FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7, 0,
-		/* IP4_10_9 [2] */
-		FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6, 0,
-		/* IP4_8_7 [2] */
-		FN_VI4_D2_C2, 0, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
-		/* IP4_6_5 [2] */
-		FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4, 0,
-		/* IP4_4 [1] */
-		FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
-		/* IP4_3_2 [2] */
-		FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, 0, 0,
-		/* IP4_1 [1] */
-		FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
-		/* IP4_0 [1] */
-		FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
-			     GROUP(4, 4,
-				   4, 4,
-				   4, 1, 1, 1, 1,
-				   1, 1, 1, 1, 1, 1, 1, 1),
-			     GROUP(
-		/* IP5_31_28 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP5_27_24 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP5_23_20 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP5_19_16 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP5_15_12 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP5_11 [1] */
-		FN_VI5_D8_Y0, FN_VI1_D23_R7,
-		/* IP5_10 [1] */
-		FN_VI5_D7_C7, FN_VI1_D22_R6,
-		/* IP5_9 [1] */
-		FN_VI5_D6_C6, FN_VI1_D21_R5,
-		/* IP5_8 [1] */
-		FN_VI5_D5_C5, FN_VI1_D20_R4,
-		/* IP5_7 [1] */
-		FN_VI5_D4_C4, FN_VI1_D19_R3,
-		/* IP5_6 [1] */
-		FN_VI5_D3_C3, FN_VI1_D18_R2,
-		/* IP5_5 [1] */
-		FN_VI5_D2_C2, FN_VI1_D17_R1,
-		/* IP5_4 [1] */
-		FN_VI5_D1_C1, FN_VI1_D16_R0,
-		/* IP5_3 [1] */
-		FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
-		/* IP5_2 [1] */
-		FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B,
-		/* IP5_1 [1] */
-		FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
-		/* IP5_0 [1] */
-		FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
-			     GROUP(4, 4,
-				   4, 1, 2, 1,
-				   2, 2, 2, 2,
-				   1, 1, 1, 1, 1, 1, 1, 1),
-			     GROUP(
-		/* IP6_31_28 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP6_27_24 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP6_23_20 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP6_19 [1] */
-		0, 0,
-		/* IP6_18_17 [2] */
-		FN_DREQ1_N, FN_RX3, 0, 0,
-		/* IP6_16 [1] */
-		FN_TX3, 0,
-		/* IP6_15_14 [2] */
-		FN_DACK1, FN_SCK3, 0, 0,
-		/* IP6_13_12 [2] */
-		FN_DREQ0_N, FN_RX2, 0, 0,
-		/* IP6_11_10 [2] */
-		FN_DACK0, FN_TX2, 0, 0,
-		/* IP6_9_8 [2] */
-		FN_DRACK0, FN_SCK2, 0, 0,
-		/* IP6_7 [1] */
-		FN_MSIOF1_RXD, FN_HRX1,
-		/* IP6_6 [1] */
-		FN_MSIOF1_TXD, FN_HTX1,
-		/* IP6_5 [1] */
-		FN_MSIOF1_SYNC, FN_HRTS1_N,
-		/* IP6_4 [1] */
-		FN_MSIOF1_SCK, FN_HSCK1,
-		/* IP6_3 [1] */
-		FN_MSIOF0_RXD, FN_HRX0,
-		/* IP6_2 [1] */
-		FN_MSIOF0_TXD, FN_HTX0,
-		/* IP6_1 [1] */
-		FN_MSIOF0_SYNC, FN_HCTS0_N,
-		/* IP6_0 [1] */
-		FN_MSIOF0_SCK, FN_HSCK0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
-			     GROUP(4, 4,
-				   3, 1, 1, 1, 1, 1,
-				   2, 2, 2, 2,
-				   1, 1, 2, 2, 2),
-			     GROUP(
-		/* IP7_31_28 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP7_27_24 [4] */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP7_23_21 [3] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP7_20 [1] */
-		FN_AUDIO_CLKB, 0,
-		/* IP7_19 [1] */
-		FN_AUDIO_CLKA, 0,
-		/* IP7_18 [1] */
-		FN_AUDIO_CLKOUT, 0,
-		/* IP7_17 [1] */
-		FN_SSI_SDATA4, 0,
-		/* IP7_16 [1] */
-		FN_SSI_WS4, 0,
-		/* IP7_15_14 [2] */
-		FN_SSI_SCK4, FN_TPU0TO3, 0, 0,
-		/* IP7_13_12 [2] */
-		FN_SSI_SDATA3, FN_TPU0TO2, 0, 0,
-		/* IP7_11_10 [2] */
-		FN_SSI_WS34, FN_TPU0TO1, 0, 0,
-		/* IP7_9_8 [2] */
-		FN_SSI_SCK34, FN_TPU0TO0, 0, 0,
-		/* IP7_7 [1] */
-		FN_PWM4, 0,
-		/* IP7_6 [1] */
-		FN_PWM3, 0,
-		/* IP7_5_4 [2] */
-		FN_PWM2, FN_TCLK3, FN_FSO_TOE, 0,
-		/* IP7_3_2 [2] */
-		FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
-		/* IP7_1_0 [2] */
-		FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 ))
-	},
-	{ },
-};
-
-const struct sh_pfc_soc_info r8a7792_pinmux_info = {
-	.name = "r8a77920_pfc",
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups,
-	.nr_groups = ARRAY_SIZE(pinmux_groups),
-	.functions = pinmux_functions,
-	.nr_functions = ARRAY_SIZE(pinmux_functions),
-
-	.cfg_regs = pinmux_config_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
deleted file mode 100644
index 34481b6c4328..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+++ /dev/null
@@ -1,5644 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * r8a7794/r8a7745 processor support - PFC hardware block.
- *
- * Copyright (C) 2014-2015 Renesas Electronics Corporation
- * Copyright (C) 2015 Renesas Solutions Corp.
- * Copyright (C) 2015-2017 Cogent Embedded, Inc. <source@cogentembedded.com>
- */
-
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <linux/sys_soc.h>
-
-#include "core.h"
-#include "sh_pfc.h"
-
-#define CPU_ALL_GP(fn, sfx)						\
-	PORT_GP_32(0, fn, sfx),						\
-	PORT_GP_26(1, fn, sfx),						\
-	PORT_GP_32(2, fn, sfx),						\
-	PORT_GP_32(3, fn, sfx),						\
-	PORT_GP_32(4, fn, sfx),						\
-	PORT_GP_28(5, fn, sfx),						\
-	PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),		\
-	PORT_GP_1(6, 24, fn, sfx),					\
-	PORT_GP_1(6, 25, fn, sfx)
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	GP_ALL(DATA),
-	PINMUX_DATA_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	GP_ALL(FN),
-
-	/* GPSR0 */
-	FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
-	FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
-	FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
-	FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
-	FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
-	FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
-	FN_IP2_17_16,
-
-	/* GPSR1 */
-	FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
-	FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
-	FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
-	FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
-	FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
-
-	/* GPSR2 */
-	FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
-	FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
-	FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
-	FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
-	FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
-	FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
-	FN_IP6_5_4, FN_IP6_7_6,
-
-	/* GPSR3 */
-	FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
-	FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
-	FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
-	FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
-	FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
-	FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
-	FN_IP8_22_20,
-
-	/* GPSR4 */
-	FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
-	FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
-	FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
-	FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
-	FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
-	FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
-	FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
-
-	/* GPSR5 */
-	FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
-	FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
-	FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
-	FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
-	FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
-	FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
-
-	/* GPSR6 */
-	FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
-	FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
-	FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
-	FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
-	FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
-
-	/* IPSR0 */
-	FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
-	FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
-	FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
-	FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
-	FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
-	FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
-	FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
-	FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
-
-	/* IPSR1 */
-	FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D,
-	FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
-	FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B,
-	FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B,
-	FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
-	FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
-	FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
-	FN_D13, FN_SCIFA1_SCK, FN_PWM2_C, FN_TCLK2_B,
-	FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B,
-	FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B,
-	FN_A0, FN_SCIFB1_SCK, FN_PWM3_B,
-	FN_A1, FN_SCIFB1_TXD,
-	FN_A3, FN_SCIFB0_SCK,
-	FN_A4, FN_SCIFB0_TXD,
-	FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
-	FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
-
-	/* IPSR2 */
-	FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B,
-	FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B,
-	FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B,
-	FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B,
-	FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B,
-	FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B,
-	FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B,
-	FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
-	FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
-	FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_CAN_CLK_C,
-	FN_TPUTO2_B,
-	FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
-	FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
-	FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
-	FN_A20, FN_SPCLK,
-
-	/* IPSR3 */
-	FN_A21, FN_MOSI_IO0,
-	FN_A22, FN_MISO_IO1, FN_ATADIR1_N,
-	FN_A23, FN_IO2, FN_ATAWR1_N,
-	FN_A24, FN_IO3, FN_EX_WAIT2,
-	FN_A25, FN_SSL, FN_ATARD1_N,
-	FN_CS0_N, FN_VI1_DATA8,
-	FN_CS1_N_A26, FN_VI1_DATA9,
-	FN_EX_CS0_N, FN_VI1_DATA10,
-	FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
-	FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_TPUTO3,
-	FN_SCIFB2_TXD,
-	FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, FN_BPFCLK,
-	FN_SCIFB2_SCK,
-	FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_FMCLK,
-	FN_SCIFB2_CTS_N,
-	FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, FN_FMIN,
-	FN_SCIFB2_RTS_N,
-	FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
-	FN_RD_N, FN_ATACS11_N,
-	FN_RD_WR_N, FN_ATAG1_N,
-
-	/* IPSR4 */
-	FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK,
-	FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
-	FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
-	FN_DU0_DR2, FN_LCDOUT18,
-	FN_DU0_DR3, FN_LCDOUT19,
-	FN_DU0_DR4, FN_LCDOUT20,
-	FN_DU0_DR5, FN_LCDOUT21,
-	FN_DU0_DR6, FN_LCDOUT22,
-	FN_DU0_DR7, FN_LCDOUT23,
-	FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
-	FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
-	FN_DU0_DG2, FN_LCDOUT10,
-	FN_DU0_DG3, FN_LCDOUT11,
-	FN_DU0_DG4, FN_LCDOUT12,
-
-	/* IPSR5 */
-	FN_DU0_DG5, FN_LCDOUT13,
-	FN_DU0_DG6, FN_LCDOUT14,
-	FN_DU0_DG7, FN_LCDOUT15,
-	FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
-	FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, FN_CAN0_TX_C,
-	FN_DU0_DB2, FN_LCDOUT2,
-	FN_DU0_DB3, FN_LCDOUT3,
-	FN_DU0_DB4, FN_LCDOUT4,
-	FN_DU0_DB5, FN_LCDOUT5,
-	FN_DU0_DB6, FN_LCDOUT6,
-	FN_DU0_DB7, FN_LCDOUT7,
-	FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
-	FN_DU0_DOTCLKOUT0, FN_QCLK,
-	FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
-	FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
-
-	/* IPSR6 */
-	FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
-	FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE,
-	FN_DU0_DISP, FN_QPOLA,
-	FN_DU0_CDE, FN_QPOLB,
-	FN_VI0_CLK, FN_AVB_RX_CLK,
-	FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
-	FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
-	FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
-	FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
-	FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
-	FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
-	FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
-	FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
-	FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7,
-	FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER,
-	FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL,
-	FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B,
-	FN_AVB_TX_EN,
-	FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK,
-	FN_ADIDATA,
-
-	/* IPSR7 */
-	FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, FN_AVB_TXD0,
-	FN_ADICS_SAMP,
-	FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, FN_AVB_TXD1,
-	FN_ADICLK,
-	FN_ETH_RXD0, FN_VI0_G3,	FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2,
-	FN_ADICHS0,
-	FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
-	FN_ADICHS1,
-	FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, FN_AVB_TXD4,
-	FN_ADICHS2,
-	FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, FN_SSI_SCK5_B,
-	FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D, FN_AVB_TXD6,
-	FN_SSI_WS5_B,
-	FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D, FN_AVB_TXD7,
-	FN_SSI_SDATA5_B,
-	FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
-	FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
-	FN_SSI_WS6_B,
-	FN_DREQ0_N, FN_SCIFB1_RXD,
-
-	/* IPSR8 */
-	FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
-	FN_SSI_SDATA6_B,
-	FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, FN_AVB_MDIO,
-	FN_SSI_SCK78_B,
-	FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK,
-	FN_SSI_WS78_B,
-	FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
-	FN_AVB_MAGIC, FN_SSI_SDATA7_B,
-	FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
-	FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
-	FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
-	FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
-	FN_CAN1_RX_D, FN_TPUTO0_B,
-	FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, FN_DVC_MUTE,
-	FN_CAN1_TX_D,
-	FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, FN_TS_SDATA_D,
-	FN_TPUTO1_B,
-	FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_TS_SCK_D,
-	FN_BPFCLK_C,
-	FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, FN_TS_SDEN_D,
-	FN_FMCLK_C,
-
-	/* IPSR9 */
-	FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_TS_SPSYNC_D,
-	FN_FMIN_C,
-	FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, FN_TPUTO1_C,
-	FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_BPFCLK_B,
-	FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_FMCLK_B,
-	FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, FN_FMIN_B,
-	FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
-	FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
-	FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
-	FN_SPEEDIN_B,
-	FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, FN_SSI_SCK1_B,
-	FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
-	FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, FN_SSI_SDATA1_B,
-
-	/* IPSR10 */
-	FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
-	FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
-	FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
-	FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
-	FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
-	FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, FN_SSI_SDATA9_B,
-	FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
-	FN_SSI_SCK4_B,
-	FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C,
-	FN_SSI_WS4_B,
-	FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
-	FN_SSI_SDATA4_B,
-	FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
-	FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN,
-
-	/* IPSR11 */
-	FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
-	FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
-	FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
-	FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
-	FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
-	FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
-	FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
-	FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
-	FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
-	FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
-	FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
-	FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
-
-	/* IPSR12 */
-	FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
-	FN_DREQ1_N_B,
-	FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
-	FN_CAN1_RX_C, FN_DACK1_B,
-	FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
-	FN_CAN1_TX_C, FN_DREQ2_N,
-	FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B,
-	FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B,
-	FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, FN_REMOCON,
-	FN_DACK2, FN_ETH_MDIO_B,
-	FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
-	FN_ETH_CRS_DV_B,
-	FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D,
-	FN_ETH_RX_ER_B,
-	FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_ATAWR0_N,
-	FN_ETH_RXD0_B,
-	FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_ATAG0_N, FN_ETH_RXD1_B,
-
-	/* IPSR13 */
-	FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
-	FN_ATACS00_N, FN_ETH_LINK_B,
-	FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, FN_VI1_DATA4,
-	FN_ATACS10_N, FN_ETH_REFCLK_B,
-	FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_EX_WAIT1,
-	FN_ETH_TXD1_B,
-	FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, FN_ATARD0_N,
-	FN_ETH_TX_EN_B,
-	FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
-	FN_ATADIR0_N, FN_ETH_MAGIC_B,
-	FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
-	FN_TS_SDATA_C, FN_ETH_TXD0_B,
-	FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
-	FN_TS_SCK_C, FN_BPFCLK_E, FN_ETH_MDC_B,
-	FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
-	FN_TS_SDEN_C, FN_FMCLK_E,
-	FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
-	FN_TS_SPSYNC_C, FN_FMIN_E,
-
-	/* MOD_SEL */
-	FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
-	FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
-	FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
-	FN_SEL_DARC_4,
-	FN_SEL_ETH_0, FN_SEL_ETH_1,
-	FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2,	FN_SEL_I2C00_3,
-	FN_SEL_I2C00_4,
-	FN_SEL_I2C01_0, FN_SEL_I2C01_1,	FN_SEL_I2C01_2, FN_SEL_I2C01_3,
-	FN_SEL_I2C01_4,
-	FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
-	FN_SEL_I2C02_4,
-	FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
-	FN_SEL_I2C03_4,
-	FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2,	FN_SEL_I2C04_3,
-	FN_SEL_I2C04_4,
-	FN_SEL_I2C05_0, FN_SEL_I2C05_1,	FN_SEL_I2C05_2, FN_SEL_I2C05_3,
-
-	/* MOD_SEL2 */
-	FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
-	FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
-	FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1,
-	FN_SEL_MSI2_0, FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1,
-	FN_SEL_RCN_0, FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1,
-	FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3,
-	FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
-	FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
-	FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3,
-	FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3,
-	FN_SEL_TMU_0, FN_SEL_TMU_1,
-	FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
-	FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
-	FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
-	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
-
-	/* MOD_SEL3 */
-	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
-	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
-	FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
-	FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
-	FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
-	FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
-	FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
-	FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
-	FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
-	FN_SEL_SSI9_1,
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-	A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
-
-	USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
-
-	SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
-	SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
-
-	SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
-	SD1_DATA2_MARK, SD1_DATA3_MARK,
-
-	/* IPSR0 */
-	SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
-	MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
-	SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
-	SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
-	MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
-	CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
-	CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
-	SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
-	SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
-	SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
-
-	/* IPSR1 */
-	D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK,
-	D7_MARK, IRQ3_MARK, TCLK1_MARK, PWM6_B_MARK,
-	D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK,
-	D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK,
-	D10_MARK, HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
-	D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
-	D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
-	D13_MARK, SCIFA1_SCK_MARK, PWM2_C_MARK, TCLK2_B_MARK,
-	D14_MARK, SCIFA1_RXD_MARK, I2C5_SCL_B_MARK,
-	D15_MARK, SCIFA1_TXD_MARK, I2C5_SDA_B_MARK,
-	A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK,
-	A1_MARK, SCIFB1_TXD_MARK,
-	A3_MARK, SCIFB0_SCK_MARK,
-	A4_MARK, SCIFB0_TXD_MARK,
-	A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK,
-	A6_MARK, SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK,
-
-	/* IPSR2 */
-	A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK,
-	A8_MARK, MSIOF1_RXD_MARK, SCIFA0_RXD_B_MARK,
-	A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK,
-	A10_MARK, MSIOF1_SCK_MARK, IIC0_SCL_B_MARK,
-	A11_MARK, MSIOF1_SYNC_MARK, IIC0_SDA_B_MARK,
-	A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
-	A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK,
-	A14_MARK, MSIOF2_RXD_MARK, HSCIF0_HRX_B_MARK, DREQ1_N_MARK,
-	A15_MARK, MSIOF2_TXD_MARK, HSCIF0_HTX_B_MARK, DACK1_MARK,
-	A16_MARK, MSIOF2_SCK_MARK, HSCIF0_HSCK_B_MARK, SPEEDIN_MARK,
-	CAN_CLK_C_MARK, TPUTO2_B_MARK,
-	A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, CAN1_RX_B_MARK,
-	A18_MARK, MSIOF2_SS1_MARK, SCIF4_TXD_E_MARK, CAN1_TX_B_MARK,
-	A19_MARK, MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK,
-	A20_MARK, SPCLK_MARK,
-
-	/* IPSR3 */
-	A21_MARK, MOSI_IO0_MARK,
-	A22_MARK, MISO_IO1_MARK, ATADIR1_N_MARK,
-	A23_MARK, IO2_MARK, ATAWR1_N_MARK,
-	A24_MARK, IO3_MARK, EX_WAIT2_MARK,
-	A25_MARK, SSL_MARK, ATARD1_N_MARK,
-	CS0_N_MARK, VI1_DATA8_MARK,
-	CS1_N_A26_MARK, VI1_DATA9_MARK,
-	EX_CS0_N_MARK, VI1_DATA10_MARK,
-	EX_CS1_N_MARK, TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK,
-	EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK,
-	TPUTO3_MARK, SCIFB2_TXD_MARK,
-	EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK,
-	BPFCLK_MARK, SCIFB2_SCK_MARK,
-	EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK,
-	FMCLK_MARK, SCIFB2_CTS_N_MARK,
-	EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK,
-	FMIN_MARK, SCIFB2_RTS_N_MARK,
-	BS_N_MARK, DRACK0_MARK, PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK,
-	RD_N_MARK, ATACS11_N_MARK,
-	RD_WR_N_MARK, ATAG1_N_MARK,
-
-	/* IPSR4 */
-	EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK,
-	DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
-	DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, I2C2_SDA_D_MARK,
-	DU0_DR2_MARK, LCDOUT18_MARK,
-	DU0_DR3_MARK, LCDOUT19_MARK,
-	DU0_DR4_MARK, LCDOUT20_MARK,
-	DU0_DR5_MARK, LCDOUT21_MARK,
-	DU0_DR6_MARK, LCDOUT22_MARK,
-	DU0_DR7_MARK, LCDOUT23_MARK,
-	DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
-	DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, I2C3_SDA_D_MARK,
-	DU0_DG2_MARK, LCDOUT10_MARK,
-	DU0_DG3_MARK, LCDOUT11_MARK,
-	DU0_DG4_MARK, LCDOUT12_MARK,
-
-	/* IPSR5 */
-	DU0_DG5_MARK, LCDOUT13_MARK,
-	DU0_DG6_MARK, LCDOUT14_MARK,
-	DU0_DG7_MARK, LCDOUT15_MARK,
-	DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, I2C4_SCL_D_MARK,
-	CAN0_RX_C_MARK,
-	DU0_DB1_MARK, LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK,
-	CAN0_TX_C_MARK,
-	DU0_DB2_MARK, LCDOUT2_MARK,
-	DU0_DB3_MARK, LCDOUT3_MARK,
-	DU0_DB4_MARK, LCDOUT4_MARK,
-	DU0_DB5_MARK, LCDOUT5_MARK,
-	DU0_DB6_MARK, LCDOUT6_MARK,
-	DU0_DB7_MARK, LCDOUT7_MARK,
-	DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
-	DU0_DOTCLKOUT0_MARK, QCLK_MARK,
-	DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
-	DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
-
-	/* IPSR6 */
-	DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
-	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
-	DU0_DISP_MARK, QPOLA_MARK, DU0_CDE_MARK, QPOLB_MARK,
-	VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, AVB_RX_DV_MARK,
-	VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
-	VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK,
-	VI0_DATA3_VI0_B3_MARK, AVB_RXD2_MARK,
-	VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
-	VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK,
-	VI0_DATA6_VI0_B6_MARK, AVB_RXD5_MARK,
-	VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK,
-	VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK,
-	AVB_RXD7_MARK,
-	VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
-	AVB_RX_ER_MARK,
-	VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, IERX_C_MARK,
-	AVB_COL_MARK,
-	VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, I2C0_SDA_C_MARK,
-	AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK,
-	ETH_MDIO_MARK, VI0_G0_MARK, MSIOF2_RXD_B_MARK, I2C5_SCL_D_MARK,
-	AVB_TX_CLK_MARK, ADIDATA_MARK,
-
-	/* IPSR7 */
-	ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, I2C5_SDA_D_MARK,
-	AVB_TXD0_MARK, ADICS_SAMP_MARK,
-	ETH_RX_ER_MARK, VI0_G2_MARK, MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK,
-	AVB_TXD1_MARK, ADICLK_MARK,
-	ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, CAN0_TX_B_MARK,
-	AVB_TXD2_MARK, ADICHS0_MARK,
-	ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
-	AVB_TXD3_MARK, ADICHS1_MARK,
-	ETH_LINK_MARK, VI0_G5_MARK, MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK,
-	AVB_TXD4_MARK, ADICHS2_MARK,
-	ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
-	SSI_SCK5_B_MARK,
-	ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, IIC0_SCL_D_MARK,
-	AVB_TXD6_MARK, SSI_WS5_B_MARK,
-	ETH_TX_EN_MARK, VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC0_SDA_D_MARK,
-	AVB_TXD7_MARK, SSI_SDATA5_B_MARK,
-	ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, AVB_TX_ER_MARK,
-	SSI_SCK6_B_MARK,
-	ETH_TXD0_MARK, VI0_R2_MARK, SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK,
-	AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
-	DREQ0_N_MARK, SCIFB1_RXD_MARK,
-
-	/* IPSR8 */
-	ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
-	AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
-	I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
-	HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
-	AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
-	SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
-	HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
-	AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
-	HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
-	I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
-	AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
-	SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
-	CAN1_TX_D_MARK,
-	I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, DU1_DR0_MARK,
-	TS_SDATA_D_MARK, TPUTO1_B_MARK,
-	I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK,	TS_SCK_D_MARK,
-	BPFCLK_C_MARK,
-	MSIOF0_RXD_MARK, SCIF5_RXD_MARK, I2C2_SCL_C_MARK, DU1_DR2_MARK,
-	TS_SDEN_D_MARK, FMCLK_C_MARK,
-
-	/* IPSR9 */
-	MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
-	TS_SPSYNC_D_MARK, FMIN_C_MARK,
-	MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, TPUTO1_C_MARK,
-	MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, BPFCLK_B_MARK,
-	MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK, DU1_DR6_MARK,
-	FMCLK_B_MARK,
-	MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
-	FMIN_B_MARK,
-	HSCIF1_HRX_MARK, I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK,
-	HSCIF1_HTX_MARK, I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK,
-	HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
-	SPEEDIN_B_MARK,
-	HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, DU1_DG3_MARK,
-	SSI_SCK1_B_MARK,
-	HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, DU1_DG4_MARK,
-	SSI_WS1_B_MARK,
-	SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
-	CAN_TXCLK_MARK,
-
-	/* IPSR10 */
-	SCIF1_RXD_MARK, I2C5_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
-	SCIF1_TXD_MARK, I2C5_SDA_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
-	SCIF2_RXD_MARK, IIC0_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
-	SCIF2_TXD_MARK, IIC0_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK,
-	SCIF2_SCK_MARK, IRQ1_MARK, DU1_DB2_MARK, SSI_WS9_B_MARK,
-	SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, DU1_DB3_MARK,
-	SSI_SDATA9_B_MARK,
-	SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, DU1_DB4_MARK,
-	AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK,
-	SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, DU1_DB5_MARK,
-	AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
-	I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK,
-	SSI_SDATA4_B_MARK,
-	I2C2_SDA_MARK, SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
-	SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK,
-
-	/* IPSR11 */
-	SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
-	SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, DU1_DOTCLKOUT1_MARK,
-	SSI_SCK6_MARK, SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
-	SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
-	DU1_EXVSYNC_DU1_VSYNC_MARK,
-	SSI_SDATA6_MARK, SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK,
-	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
-	SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, I2C5_SDA_C_MARK, DU1_DISP_MARK,
-	SSI_WS78_MARK, SCIFA2_RXD_B_MARK, I2C5_SCL_C_MARK, DU1_CDE_MARK,
-	SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK,
-	CAN_CLK_D_MARK,
-	SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK,
-	SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, ADICS_SAMP_B_MARK,
-	SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK, ADICLK_B_MARK,
-
-	/* IPSR12 */
-	SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
-	DREQ1_N_B_MARK,
-	SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK, ADICHS1_B_MARK,
-	CAN1_RX_C_MARK, DACK1_B_MARK,
-	SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
-	CAN1_TX_C_MARK, DREQ2_N_MARK,
-	SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
-	SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK,
-	SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK,
-	SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
-	DACK2_MARK, ETH_MDIO_B_MARK,
-	SSI_SCK1_MARK, SCIF1_RXD_B_MARK, IIC0_SCL_C_MARK, VI1_CLK_MARK,
-	CAN0_RX_D_MARK, ETH_CRS_DV_B_MARK,
-	SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC0_SDA_C_MARK, VI1_DATA0_MARK,
-	CAN0_TX_D_MARK, ETH_RX_ER_B_MARK,
-	SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, ATAWR0_N_MARK,
-	ETH_RXD0_B_MARK,
-	SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, VI1_DATA2_MARK, ATAG0_N_MARK,
-	ETH_RXD1_B_MARK,
-
-	/* IPSR13 */
-	SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
-	ATACS00_N_MARK, ETH_LINK_B_MARK,
-	SSI_SDATA2_MARK, HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK,
-	VI1_DATA4_MARK, ATACS10_N_MARK, ETH_REFCLK_B_MARK,
-	SSI_SCK9_MARK, SCIF2_SCK_B_MARK, PWM2_B_MARK, VI1_DATA5_MARK,
-	EX_WAIT1_MARK, ETH_TXD1_B_MARK,
-	SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, VI1_DATA6_MARK,
-	ATARD0_N_MARK, ETH_TX_EN_B_MARK,
-	SSI_SDATA9_MARK, SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK,
-	ATADIR0_N_MARK, ETH_MAGIC_B_MARK,
-	AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, VI1_CLKENB_MARK,
-	TS_SDATA_C_MARK, ETH_TXD0_B_MARK,
-	AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
-	TS_SCK_C_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
-	AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
-	TS_SDEN_C_MARK, FMCLK_E_MARK,
-	AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
-	TS_SPSYNC_C_MARK, FMIN_E_MARK,
-	PINMUX_MARK_END,
-};
-
-static const u16 pinmux_data[] = {
-	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
-
-	PINMUX_SINGLE(A2),
-	PINMUX_SINGLE(WE0_N),
-	PINMUX_SINGLE(WE1_N),
-	PINMUX_SINGLE(DACK0),
-	PINMUX_SINGLE(USB0_PWEN),
-	PINMUX_SINGLE(USB0_OVC),
-	PINMUX_SINGLE(USB1_PWEN),
-	PINMUX_SINGLE(USB1_OVC),
-	PINMUX_SINGLE(SD0_CLK),
-	PINMUX_SINGLE(SD0_CMD),
-	PINMUX_SINGLE(SD0_DATA0),
-	PINMUX_SINGLE(SD0_DATA1),
-	PINMUX_SINGLE(SD0_DATA2),
-	PINMUX_SINGLE(SD0_DATA3),
-	PINMUX_SINGLE(SD0_CD),
-	PINMUX_SINGLE(SD0_WP),
-	PINMUX_SINGLE(SD1_CLK),
-	PINMUX_SINGLE(SD1_CMD),
-	PINMUX_SINGLE(SD1_DATA0),
-	PINMUX_SINGLE(SD1_DATA1),
-	PINMUX_SINGLE(SD1_DATA2),
-	PINMUX_SINGLE(SD1_DATA3),
-
-	/* IPSR0 */
-	PINMUX_IPSR_GPSR(IP0_0, SD1_CD),
-	PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0),
-	PINMUX_IPSR_GPSR(IP0_9_8, SD1_WP),
-	PINMUX_IPSR_GPSR(IP0_9_8, IRQ7),
-	PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0),
-	PINMUX_IPSR_GPSR(IP0_10, MMC_CLK),
-	PINMUX_IPSR_GPSR(IP0_10, SD2_CLK),
-	PINMUX_IPSR_GPSR(IP0_11, MMC_CMD),
-	PINMUX_IPSR_GPSR(IP0_11, SD2_CMD),
-	PINMUX_IPSR_GPSR(IP0_12, MMC_D0),
-	PINMUX_IPSR_GPSR(IP0_12, SD2_DATA0),
-	PINMUX_IPSR_GPSR(IP0_13, MMC_D1),
-	PINMUX_IPSR_GPSR(IP0_13, SD2_DATA1),
-	PINMUX_IPSR_GPSR(IP0_14, MMC_D2),
-	PINMUX_IPSR_GPSR(IP0_14, SD2_DATA2),
-	PINMUX_IPSR_GPSR(IP0_15, MMC_D3),
-	PINMUX_IPSR_GPSR(IP0_15, SD2_DATA3),
-	PINMUX_IPSR_GPSR(IP0_16, MMC_D4),
-	PINMUX_IPSR_GPSR(IP0_16, SD2_CD),
-	PINMUX_IPSR_GPSR(IP0_17, MMC_D5),
-	PINMUX_IPSR_GPSR(IP0_17, SD2_WP),
-	PINMUX_IPSR_GPSR(IP0_19_18, MMC_D6),
-	PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
-	PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
-	PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0),
-	PINMUX_IPSR_GPSR(IP0_21_20, MMC_D7),
-	PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
-	PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
-	PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0),
-	PINMUX_IPSR_GPSR(IP0_23_22, D0),
-	PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
-	PINMUX_IPSR_GPSR(IP0_23_22, IRQ4),
-	PINMUX_IPSR_GPSR(IP0_24, D1),
-	PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
-	PINMUX_IPSR_GPSR(IP0_25, D2),
-	PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
-	PINMUX_IPSR_GPSR(IP0_27_26, D3),
-	PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
-	PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
-	PINMUX_IPSR_GPSR(IP0_29_28, D4),
-	PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
-	PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
-	PINMUX_IPSR_GPSR(IP0_31_30, D5),
-	PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
-	PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
-
-	/* IPSR1 */
-	PINMUX_IPSR_GPSR(IP1_1_0, D6),
-	PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1),
-	PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3),
-	PINMUX_IPSR_GPSR(IP1_3_2, D7),
-	PINMUX_IPSR_GPSR(IP1_3_2, IRQ3),
-	PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0),
-	PINMUX_IPSR_GPSR(IP1_3_2, PWM6_B),
-	PINMUX_IPSR_GPSR(IP1_5_4, D8),
-	PINMUX_IPSR_GPSR(IP1_5_4, HSCIF2_HRX),
-	PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1),
-	PINMUX_IPSR_GPSR(IP1_7_6, D9),
-	PINMUX_IPSR_GPSR(IP1_7_6, HSCIF2_HTX),
-	PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1),
-	PINMUX_IPSR_GPSR(IP1_10_8, D10),
-	PINMUX_IPSR_GPSR(IP1_10_8, HSCIF2_HSCK),
-	PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2),
-	PINMUX_IPSR_GPSR(IP1_10_8, IRQ6),
-	PINMUX_IPSR_GPSR(IP1_10_8, PWM5_C),
-	PINMUX_IPSR_GPSR(IP1_12_11, D11),
-	PINMUX_IPSR_GPSR(IP1_12_11, HSCIF2_HCTS_N),
-	PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2),
-	PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3),
-	PINMUX_IPSR_GPSR(IP1_14_13, D12),
-	PINMUX_IPSR_GPSR(IP1_14_13, HSCIF2_HRTS_N),
-	PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2),
-	PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
-	PINMUX_IPSR_GPSR(IP1_17_15, D13),
-	PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
-	PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C),
-	PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
-	PINMUX_IPSR_GPSR(IP1_19_18, D14),
-	PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0),
-	PINMUX_IPSR_MSEL(IP1_19_18, I2C5_SCL_B, SEL_I2C05_1),
-	PINMUX_IPSR_GPSR(IP1_21_20, D15),
-	PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0),
-	PINMUX_IPSR_MSEL(IP1_21_20, I2C5_SDA_B, SEL_I2C05_1),
-	PINMUX_IPSR_GPSR(IP1_23_22, A0),
-	PINMUX_IPSR_GPSR(IP1_23_22, SCIFB1_SCK),
-	PINMUX_IPSR_GPSR(IP1_23_22, PWM3_B),
-	PINMUX_IPSR_GPSR(IP1_24, A1),
-	PINMUX_IPSR_GPSR(IP1_24, SCIFB1_TXD),
-	PINMUX_IPSR_GPSR(IP1_26, A3),
-	PINMUX_IPSR_GPSR(IP1_26, SCIFB0_SCK),
-	PINMUX_IPSR_GPSR(IP1_27, A4),
-	PINMUX_IPSR_GPSR(IP1_27, SCIFB0_TXD),
-	PINMUX_IPSR_GPSR(IP1_29_28, A5),
-	PINMUX_IPSR_GPSR(IP1_29_28, SCIFB0_RXD),
-	PINMUX_IPSR_GPSR(IP1_29_28, PWM4_B),
-	PINMUX_IPSR_GPSR(IP1_29_28, TPUTO3_C),
-	PINMUX_IPSR_GPSR(IP1_31_30, A6),
-	PINMUX_IPSR_GPSR(IP1_31_30, SCIFB0_CTS_N),
-	PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1),
-	PINMUX_IPSR_GPSR(IP1_31_30, TPUTO2_C),
-
-	/* IPSR2 */
-	PINMUX_IPSR_GPSR(IP2_1_0, A7),
-	PINMUX_IPSR_GPSR(IP2_1_0, SCIFB0_RTS_N),
-	PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1),
-	PINMUX_IPSR_GPSR(IP2_3_2, A8),
-	PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0),
-	PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1),
-	PINMUX_IPSR_GPSR(IP2_5_4, A9),
-	PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0),
-	PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1),
-	PINMUX_IPSR_GPSR(IP2_7_6, A10),
-	PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0),
-	PINMUX_IPSR_MSEL(IP2_7_6, IIC0_SCL_B, SEL_IIC0_1),
-	PINMUX_IPSR_GPSR(IP2_9_8, A11),
-	PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0),
-	PINMUX_IPSR_MSEL(IP2_9_8, IIC0_SDA_B, SEL_IIC0_1),
-	PINMUX_IPSR_GPSR(IP2_11_10, A12),
-	PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0),
-	PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1),
-	PINMUX_IPSR_GPSR(IP2_13_12, A13),
-	PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0),
-	PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1),
-	PINMUX_IPSR_GPSR(IP2_15_14, A14),
-	PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0),
-	PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1),
-	PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0),
-	PINMUX_IPSR_GPSR(IP2_17_16, A15),
-	PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0),
-	PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1),
-	PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0),
-	PINMUX_IPSR_GPSR(IP2_20_18, A16),
-	PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
-	PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
-	PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
-	PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
-	PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B),
-	PINMUX_IPSR_GPSR(IP2_23_21, A17),
-	PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
-	PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
-	PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
-	PINMUX_IPSR_GPSR(IP2_26_24, A18),
-	PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
-	PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
-	PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
-	PINMUX_IPSR_GPSR(IP2_29_27, A19),
-	PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
-	PINMUX_IPSR_GPSR(IP2_29_27, PWM4),
-	PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2),
-	PINMUX_IPSR_GPSR(IP2_31_30, A20),
-	PINMUX_IPSR_GPSR(IP2_31_30, SPCLK),
-
-	/* IPSR3 */
-	PINMUX_IPSR_GPSR(IP3_1_0, A21),
-	PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0),
-	PINMUX_IPSR_GPSR(IP3_3_2, A22),
-	PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1),
-	PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N),
-	PINMUX_IPSR_GPSR(IP3_5_4, A23),
-	PINMUX_IPSR_GPSR(IP3_5_4, IO2),
-	PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N),
-	PINMUX_IPSR_GPSR(IP3_7_6, A24),
-	PINMUX_IPSR_GPSR(IP3_7_6, IO3),
-	PINMUX_IPSR_GPSR(IP3_7_6, EX_WAIT2),
-	PINMUX_IPSR_GPSR(IP3_9_8, A25),
-	PINMUX_IPSR_GPSR(IP3_9_8, SSL),
-	PINMUX_IPSR_GPSR(IP3_9_8, ATARD1_N),
-	PINMUX_IPSR_GPSR(IP3_10, CS0_N),
-	PINMUX_IPSR_GPSR(IP3_10, VI1_DATA8),
-	PINMUX_IPSR_GPSR(IP3_11, CS1_N_A26),
-	PINMUX_IPSR_GPSR(IP3_11, VI1_DATA9),
-	PINMUX_IPSR_GPSR(IP3_12, EX_CS0_N),
-	PINMUX_IPSR_GPSR(IP3_12, VI1_DATA10),
-	PINMUX_IPSR_GPSR(IP3_14_13, EX_CS1_N),
-	PINMUX_IPSR_GPSR(IP3_14_13, TPUTO3_B),
-	PINMUX_IPSR_GPSR(IP3_14_13, SCIFB2_RXD),
-	PINMUX_IPSR_GPSR(IP3_14_13, VI1_DATA11),
-	PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N),
-	PINMUX_IPSR_GPSR(IP3_17_15, PWM0),
-	PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
-	PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
-	PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3),
-	PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD),
-	PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N),
-	PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
-	PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
-	PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
-	PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK),
-	PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N),
-	PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
-	PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
-	PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
-	PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N),
-	PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N),
-	PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
-	PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
-	PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
-	PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N),
-	PINMUX_IPSR_GPSR(IP3_29_27, BS_N),
-	PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
-	PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C),
-	PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C),
-	PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N),
-	PINMUX_IPSR_GPSR(IP3_30, RD_N),
-	PINMUX_IPSR_GPSR(IP3_30, ATACS11_N),
-	PINMUX_IPSR_GPSR(IP3_31, RD_WR_N),
-	PINMUX_IPSR_GPSR(IP3_31, ATAG1_N),
-
-	/* IPSR4 */
-	PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0),
-	PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
-	PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
-	PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0),
-	PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16),
-	PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
-	PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
-	PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1),
-	PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17),
-	PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
-	PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
-	PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2),
-	PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18),
-	PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3),
-	PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19),
-	PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4),
-	PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20),
-	PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5),
-	PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21),
-	PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6),
-	PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22),
-	PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7),
-	PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23),
-	PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0),
-	PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8),
-	PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
-	PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
-	PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1),
-	PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9),
-	PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
-	PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
-	PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2),
-	PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10),
-	PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3),
-	PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11),
-	PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4),
-	PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12),
-
-	/* IPSR5 */
-	PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5),
-	PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13),
-	PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6),
-	PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14),
-	PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7),
-	PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15),
-	PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0),
-	PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0),
-	PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
-	PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
-	PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
-	PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1),
-	PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1),
-	PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
-	PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
-	PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
-	PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2),
-	PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2),
-	PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3),
-	PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3),
-	PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4),
-	PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4),
-	PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5),
-	PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5),
-	PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6),
-	PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6),
-	PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7),
-	PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7),
-	PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN),
-	PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS),
-	PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0),
-	PINMUX_IPSR_GPSR(IP5_27_26, QCLK),
-	PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1),
-	PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE),
-	PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
-	PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS),
-
-	/* IPSR6 */
-	PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
-	PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE),
-	PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
-	PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE),
-	PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP),
-	PINMUX_IPSR_GPSR(IP6_5_4, QPOLA),
-	PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE),
-	PINMUX_IPSR_GPSR(IP6_7_6, QPOLB),
-	PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
-	PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK),
-	PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0),
-	PINMUX_IPSR_GPSR(IP6_9, AVB_RX_DV),
-	PINMUX_IPSR_GPSR(IP6_10, VI0_DATA1_VI0_B1),
-	PINMUX_IPSR_GPSR(IP6_10, AVB_RXD0),
-	PINMUX_IPSR_GPSR(IP6_11, VI0_DATA2_VI0_B2),
-	PINMUX_IPSR_GPSR(IP6_11, AVB_RXD1),
-	PINMUX_IPSR_GPSR(IP6_12, VI0_DATA3_VI0_B3),
-	PINMUX_IPSR_GPSR(IP6_12, AVB_RXD2),
-	PINMUX_IPSR_GPSR(IP6_13, VI0_DATA4_VI0_B4),
-	PINMUX_IPSR_GPSR(IP6_13, AVB_RXD3),
-	PINMUX_IPSR_GPSR(IP6_14, VI0_DATA5_VI0_B5),
-	PINMUX_IPSR_GPSR(IP6_14, AVB_RXD4),
-	PINMUX_IPSR_GPSR(IP6_15, VI0_DATA6_VI0_B6),
-	PINMUX_IPSR_GPSR(IP6_15, AVB_RXD5),
-	PINMUX_IPSR_GPSR(IP6_16, VI0_DATA7_VI0_B7),
-	PINMUX_IPSR_GPSR(IP6_16, AVB_RXD6),
-	PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB),
-	PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
-	PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
-	PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2),
-	PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7),
-	PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD),
-	PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
-	PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
-	PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2),
-	PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER),
-	PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N),
-	PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
-	PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
-	PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2),
-	PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL),
-	PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N),
-	PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
-	PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
-	PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
-	PINMUX_IPSR_GPSR(IP6_28_26, AVB_TX_EN),
-	PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0),
-	PINMUX_IPSR_GPSR(IP6_31_29, VI0_G0),
-	PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
-	PINMUX_IPSR_MSEL(IP6_31_29, I2C5_SCL_D, SEL_I2C05_3),
-	PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
-	PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
-
-	/* IPSR7 */
-	PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
-	PINMUX_IPSR_GPSR(IP7_2_0, VI0_G1),
-	PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
-	PINMUX_IPSR_MSEL(IP7_2_0, I2C5_SDA_D, SEL_I2C05_3),
-	PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
-	PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
-	PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
-	PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2),
-	PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
-	PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
-	PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1),
-	PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
-	PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
-	PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3),
-	PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
-	PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
-	PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2),
-	PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
-	PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
-	PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4),
-	PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
-	PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
-	PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3),
-	PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0),
-	PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0),
-	PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5),
-	PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
-	PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
-	PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4),
-	PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0),
-	PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
-	PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6),
-	PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
-	PINMUX_IPSR_GPSR(IP7_17_15, AVB_TXD5),
-	PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
-	PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0),
-	PINMUX_IPSR_GPSR(IP7_20_18, VI0_G7),
-	PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
-	PINMUX_IPSR_MSEL(IP7_20_18, IIC0_SCL_D, SEL_IIC0_3),
-	PINMUX_IPSR_GPSR(IP7_20_18, AVB_TXD6),
-	PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
-	PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
-	PINMUX_IPSR_GPSR(IP7_23_21, VI0_R0),
-	PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
-	PINMUX_IPSR_MSEL(IP7_23_21, IIC0_SDA_D, SEL_IIC0_3),
-	PINMUX_IPSR_GPSR(IP7_23_21, AVB_TXD7),
-	PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
-	PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
-	PINMUX_IPSR_GPSR(IP7_26_24, VI0_R1),
-	PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
-	PINMUX_IPSR_GPSR(IP7_26_24, AVB_TX_ER),
-	PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
-	PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0),
-	PINMUX_IPSR_GPSR(IP7_29_27, VI0_R2),
-	PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
-	PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
-	PINMUX_IPSR_GPSR(IP7_29_27, AVB_GTX_CLK),
-	PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
-	PINMUX_IPSR_GPSR(IP7_31, DREQ0_N),
-	PINMUX_IPSR_GPSR(IP7_31, SCIFB1_RXD),
-
-	/* IPSR8 */
-	PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0),
-	PINMUX_IPSR_GPSR(IP8_2_0, VI0_R3),
-	PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
-	PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
-	PINMUX_IPSR_GPSR(IP8_2_0, AVB_MDC),
-	PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
-	PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
-	PINMUX_IPSR_GPSR(IP8_5_3, VI0_R4),
-	PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
-	PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
-	PINMUX_IPSR_GPSR(IP8_5_3, AVB_MDIO),
-	PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
-	PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
-	PINMUX_IPSR_GPSR(IP8_8_6, VI0_R5),
-	PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
-	PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
-	PINMUX_IPSR_GPSR(IP8_5_3, AVB_LINK),
-	PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
-	PINMUX_IPSR_GPSR(IP8_11_9, HSCIF0_HCTS_N),
-	PINMUX_IPSR_GPSR(IP8_11_9, VI0_R6),
-	PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
-	PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
-	PINMUX_IPSR_GPSR(IP8_11_9, AVB_MAGIC),
-	PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
-	PINMUX_IPSR_GPSR(IP8_14_12, HSCIF0_HRTS_N),
-	PINMUX_IPSR_GPSR(IP8_14_12, VI0_R7),
-	PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
-	PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
-	PINMUX_IPSR_GPSR(IP8_14_12, AVB_PHY_INT),
-	PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
-	PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
-	PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
-	PINMUX_IPSR_GPSR(IP8_16_15, AVB_CRS),
-	PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
-	PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
-	PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
-	PINMUX_IPSR_GPSR(IP8_19_17, PWM5),
-	PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1),
-	PINMUX_IPSR_GPSR(IP8_19_17, AVB_GTXREFCLK),
-	PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
-	PINMUX_IPSR_GPSR(IP8_19_17, TPUTO0_B),
-	PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
-	PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
-	PINMUX_IPSR_GPSR(IP8_22_20, TPUTO0),
-	PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0),
-	PINMUX_IPSR_GPSR(IP8_22_20, DVC_MUTE),
-	PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
-	PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
-	PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
-	PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B),
-	PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0),
-	PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
-	PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B),
-	PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
-	PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
-	PINMUX_IPSR_GPSR(IP8_28_26, IRQ5),
-	PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1),
-	PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
-	PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD),
-	PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
-	PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
-	PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2),
-	PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
-
-	/* IPSR9 */
-	PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD),
-	PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
-	PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
-	PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3),
-	PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
-	PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK),
-	PINMUX_IPSR_GPSR(IP9_5_3, IRQ0),
-	PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
-	PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4),
-	PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C),
-	PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC),
-	PINMUX_IPSR_GPSR(IP9_8_6, PWM1),
-	PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
-	PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5),
-	PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
-	PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1),
-	PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
-	PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
-	PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6),
-	PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
-	PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2),
-	PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
-	PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
-	PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7),
-	PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
-	PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
-	PINMUX_IPSR_GPSR(IP9_16_15, PWM6),
-	PINMUX_IPSR_GPSR(IP9_16_15, DU1_DG0),
-	PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0),
-	PINMUX_IPSR_GPSR(IP9_18_17, TPUTO1),
-	PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1),
-	PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK),
-	PINMUX_IPSR_GPSR(IP9_21_19, PWM2),
-	PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0),
-	PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2),
-	PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
-	PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
-	PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
-	PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
-	PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3),
-	PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
-	PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
-	PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
-	PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4),
-	PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
-	PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
-	PINMUX_IPSR_GPSR(IP9_30_28, PWM3),
-	PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
-	PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5),
-	PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
-
-	/* IPSR10 */
-	PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
-	PINMUX_IPSR_MSEL(IP10_2_0, I2C5_SCL, SEL_I2C05_0),
-	PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6),
-	PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
-	PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
-	PINMUX_IPSR_MSEL(IP10_5_3, I2C5_SDA, SEL_I2C05_0),
-	PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7),
-	PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
-	PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
-	PINMUX_IPSR_MSEL(IP10_8_6, IIC0_SCL, SEL_IIC0_0),
-	PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0),
-	PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
-	PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
-	PINMUX_IPSR_MSEL(IP10_11_9, IIC0_SDA, SEL_IIC0_0),
-	PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1),
-	PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
-	PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
-	PINMUX_IPSR_GPSR(IP10_14_12, IRQ1),
-	PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2),
-	PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
-	PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
-	PINMUX_IPSR_GPSR(IP10_17_15, IRQ2),
-	PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
-	PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3),
-	PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
-	PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
-	PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
-	PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
-	PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4),
-	PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
-	PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
-	PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
-	PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
-	PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
-	PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5),
-	PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
-	PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
-	PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
-	PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
-	PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6),
-	PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
-	PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
-	PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
-	PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
-	PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7),
-	PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
-	PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
-	PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
-	PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN),
-
-	/* IPSR11 */
-	PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
-	PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
-	PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
-	PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0),
-	PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
-	PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
-	PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
-	PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1),
-	PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
-	PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
-	PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
-	PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
-	PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
-	PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
-	PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
-	PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
-	PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
-	PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
-	PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
-	PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
-	PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
-	PINMUX_IPSR_MSEL(IP11_15_14, I2C5_SDA_C, SEL_I2C05_2),
-	PINMUX_IPSR_GPSR(IP11_15_14, DU1_DISP),
-	PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0),
-	PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
-	PINMUX_IPSR_MSEL(IP11_17_16, I2C5_SCL_C, SEL_I2C05_2),
-	PINMUX_IPSR_GPSR(IP11_17_16, DU1_CDE),
-	PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
-	PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
-	PINMUX_IPSR_GPSR(IP11_20_18, IRQ8),
-	PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
-	PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
-	PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129),
-	PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
-	PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
-	PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
-	PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129),
-	PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
-	PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
-	PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
-	PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0),
-	PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
-	PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B),
-	PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
-
-	/* IPSR12 */
-	PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34),
-	PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
-	PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
-	PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
-	PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
-	PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34),
-	PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
-	PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
-	PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1),
-	PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
-	PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1),
-	PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3),
-	PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
-	PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
-	PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1),
-	PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
-	PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N),
-	PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
-	PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK),
-	PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
-	PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
-	PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG),
-	PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
-	PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
-	PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT),
-	PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
-	PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
-	PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
-	PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B),
-	PINMUX_IPSR_GPSR(IP12_17_15, IRQ9),
-	PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0),
-	PINMUX_IPSR_GPSR(IP12_17_15, DACK2),
-	PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
-	PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
-	PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1),
-	PINMUX_IPSR_MSEL(IP12_20_18, IIC0_SCL_C, SEL_IIC0_2),
-	PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK),
-	PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
-	PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
-	PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
-	PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
-	PINMUX_IPSR_MSEL(IP12_23_21, IIC0_SDA_C, SEL_IIC0_2),
-	PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0),
-	PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
-	PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
-	PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
-	PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
-	PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
-	PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N),
-	PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
-	PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
-	PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
-	PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
-	PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N),
-	PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
-
-	/* IPSR13 */
-	PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0),
-	PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
-	PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3),
-	PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N),
-	PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
-	PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
-	PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
-	PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4),
-	PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N),
-	PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
-	PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
-	PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
-	PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B),
-	PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5),
-	PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1),
-	PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
-	PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
-	PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1),
-	PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4),
-	PINMUX_IPSR_GPSR(IP13_11_9, VI1_DATA6),
-	PINMUX_IPSR_GPSR(IP13_11_9, ATARD0_N),
-	PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1),
-	PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0),
-	PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1),
-	PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4),
-	PINMUX_IPSR_GPSR(IP13_14_12, VI1_DATA7),
-	PINMUX_IPSR_GPSR(IP13_14_12, ATADIR0_N),
-	PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1),
-	PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0),
-	PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
-	PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
-	PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB),
-	PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
-	PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
-	PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
-	PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
-	PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD),
-	PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
-	PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
-	PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
-	PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
-	PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
-	PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N),
-	PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
-	PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
-	PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
-	PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
-	PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N),
-	PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	PINMUX_GPIO_GP_ALL(),
-};
-
-/* - Audio Clock ------------------------------------------------------------ */
-static const unsigned int audio_clka_pins[] = {
-	/* CLKA */
-	RCAR_GP_PIN(5, 20),
-};
-static const unsigned int audio_clka_mux[] = {
-	AUDIO_CLKA_MARK,
-};
-static const unsigned int audio_clka_b_pins[] = {
-	/* CLKA */
-	RCAR_GP_PIN(3, 25),
-};
-static const unsigned int audio_clka_b_mux[] = {
-	AUDIO_CLKA_B_MARK,
-};
-static const unsigned int audio_clka_c_pins[] = {
-	/* CLKA */
-	RCAR_GP_PIN(4, 20),
-};
-static const unsigned int audio_clka_c_mux[] = {
-	AUDIO_CLKA_C_MARK,
-};
-static const unsigned int audio_clka_d_pins[] = {
-	/* CLKA */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int audio_clka_d_mux[] = {
-	AUDIO_CLKA_D_MARK,
-};
-static const unsigned int audio_clkb_pins[] = {
-	/* CLKB */
-	RCAR_GP_PIN(5, 21),
-};
-static const unsigned int audio_clkb_mux[] = {
-	AUDIO_CLKB_MARK,
-};
-static const unsigned int audio_clkb_b_pins[] = {
-	/* CLKB */
-	RCAR_GP_PIN(3, 26),
-};
-static const unsigned int audio_clkb_b_mux[] = {
-	AUDIO_CLKB_B_MARK,
-};
-static const unsigned int audio_clkb_c_pins[] = {
-	/* CLKB */
-	RCAR_GP_PIN(4, 21),
-};
-static const unsigned int audio_clkb_c_mux[] = {
-	AUDIO_CLKB_C_MARK,
-};
-static const unsigned int audio_clkc_pins[] = {
-	/* CLKC */
-	RCAR_GP_PIN(5, 22),
-};
-static const unsigned int audio_clkc_mux[] = {
-	AUDIO_CLKC_MARK,
-};
-static const unsigned int audio_clkc_b_pins[] = {
-	/* CLKC */
-	RCAR_GP_PIN(3, 29),
-};
-static const unsigned int audio_clkc_b_mux[] = {
-	AUDIO_CLKC_B_MARK,
-};
-static const unsigned int audio_clkc_c_pins[] = {
-	/* CLKC */
-	RCAR_GP_PIN(4, 22),
-};
-static const unsigned int audio_clkc_c_mux[] = {
-	AUDIO_CLKC_C_MARK,
-};
-static const unsigned int audio_clkout_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(5, 23),
-};
-static const unsigned int audio_clkout_mux[] = {
-	AUDIO_CLKOUT_MARK,
-};
-static const unsigned int audio_clkout_b_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(3, 12),
-};
-static const unsigned int audio_clkout_b_mux[] = {
-	AUDIO_CLKOUT_B_MARK,
-};
-static const unsigned int audio_clkout_c_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(4, 23),
-};
-static const unsigned int audio_clkout_c_mux[] = {
-	AUDIO_CLKOUT_C_MARK,
-};
-/* - AVB -------------------------------------------------------------------- */
-static const unsigned int avb_link_pins[] = {
-	RCAR_GP_PIN(3, 26),
-};
-static const unsigned int avb_link_mux[] = {
-	AVB_LINK_MARK,
-};
-static const unsigned int avb_magic_pins[] = {
-	RCAR_GP_PIN(3, 27),
-};
-static const unsigned int avb_magic_mux[] = {
-	AVB_MAGIC_MARK,
-};
-static const unsigned int avb_phy_int_pins[] = {
-	RCAR_GP_PIN(3, 28),
-};
-static const unsigned int avb_phy_int_mux[] = {
-	AVB_PHY_INT_MARK,
-};
-static const unsigned int avb_mdio_pins[] = {
-	RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
-};
-static const unsigned int avb_mdio_mux[] = {
-	AVB_MDC_MARK, AVB_MDIO_MARK,
-};
-static const unsigned int avb_mii_pins[] = {
-	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
-	RCAR_GP_PIN(3, 17),
-
-	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
-	RCAR_GP_PIN(3, 5),
-
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
-	RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22),
-	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 11),
-};
-static const unsigned int avb_mii_mux[] = {
-	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
-	AVB_TXD3_MARK,
-
-	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
-	AVB_RXD3_MARK,
-
-	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
-	AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
-	AVB_TX_CLK_MARK, AVB_COL_MARK,
-};
-static const unsigned int avb_gmii_pins[] = {
-	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
-	RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
-	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
-
-	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
-	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
-	RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 30),
-	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 13),
-	RCAR_GP_PIN(3, 11),
-};
-static const unsigned int avb_gmii_mux[] = {
-	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
-	AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
-	AVB_TXD6_MARK, AVB_TXD7_MARK,
-
-	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
-	AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
-	AVB_RXD6_MARK, AVB_RXD7_MARK,
-
-	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
-	AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
-	AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
-	AVB_COL_MARK,
-};
-
-/* - CAN -------------------------------------------------------------------- */
-static const unsigned int can0_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
-};
-
-static const unsigned int can0_data_mux[] = {
-	CAN0_TX_MARK, CAN0_RX_MARK,
-};
-
-static const unsigned int can0_data_b_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
-};
-
-static const unsigned int can0_data_b_mux[] = {
-	CAN0_TX_B_MARK, CAN0_RX_B_MARK,
-};
-
-static const unsigned int can0_data_c_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
-};
-
-static const unsigned int can0_data_c_mux[] = {
-	CAN0_TX_C_MARK, CAN0_RX_C_MARK,
-};
-
-static const unsigned int can0_data_d_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
-};
-
-static const unsigned int can0_data_d_mux[] = {
-	CAN0_TX_D_MARK, CAN0_RX_D_MARK,
-};
-
-static const unsigned int can1_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 24),
-};
-
-static const unsigned int can1_data_mux[] = {
-	CAN1_TX_MARK, CAN1_RX_MARK,
-};
-
-static const unsigned int can1_data_b_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
-};
-
-static const unsigned int can1_data_b_mux[] = {
-	CAN1_TX_B_MARK, CAN1_RX_B_MARK,
-};
-
-static const unsigned int can1_data_c_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
-};
-
-static const unsigned int can1_data_c_mux[] = {
-	CAN1_TX_C_MARK, CAN1_RX_C_MARK,
-};
-
-static const unsigned int can1_data_d_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30),
-};
-
-static const unsigned int can1_data_d_mux[] = {
-	CAN1_TX_D_MARK, CAN1_RX_D_MARK,
-};
-
-static const unsigned int can_clk_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(3, 31),
-};
-
-static const unsigned int can_clk_mux[] = {
-	CAN_CLK_MARK,
-};
-
-static const unsigned int can_clk_b_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(1, 23),
-};
-
-static const unsigned int can_clk_b_mux[] = {
-	CAN_CLK_B_MARK,
-};
-
-static const unsigned int can_clk_c_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(1, 0),
-};
-
-static const unsigned int can_clk_c_mux[] = {
-	CAN_CLK_C_MARK,
-};
-
-static const unsigned int can_clk_d_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(5, 0),
-};
-
-static const unsigned int can_clk_d_mux[] = {
-	CAN_CLK_D_MARK,
-};
-
-/* - DU --------------------------------------------------------------------- */
-static const unsigned int du0_rgb666_pins[] = {
-	/* R[7:2], G[7:2], B[7:2] */
-	RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 5),
-	RCAR_GP_PIN(2, 4),  RCAR_GP_PIN(2, 3),  RCAR_GP_PIN(2, 2),
-	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
-	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
-	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
-	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
-};
-static const unsigned int du0_rgb666_mux[] = {
-	DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
-	DU0_DR3_MARK, DU0_DR2_MARK,
-	DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
-	DU0_DG3_MARK, DU0_DG2_MARK,
-	DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
-	DU0_DB3_MARK, DU0_DB2_MARK,
-};
-static const unsigned int du0_rgb888_pins[] = {
-	/* R[7:0], G[7:0], B[7:0] */
-	RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 5),
-	RCAR_GP_PIN(2, 4),  RCAR_GP_PIN(2, 3),  RCAR_GP_PIN(2, 2),
-	RCAR_GP_PIN(2, 1),  RCAR_GP_PIN(2, 0),
-	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
-	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
-	RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 8),
-	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
-	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
-	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
-};
-static const unsigned int du0_rgb888_mux[] = {
-	DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
-	DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
-	DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
-	DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
-	DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
-	DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
-};
-static const unsigned int du0_clk0_out_pins[] = {
-	/* DOTCLKOUT0 */
-	RCAR_GP_PIN(2, 25),
-};
-static const unsigned int du0_clk0_out_mux[] = {
-	DU0_DOTCLKOUT0_MARK
-};
-static const unsigned int du0_clk1_out_pins[] = {
-	/* DOTCLKOUT1 */
-	RCAR_GP_PIN(2, 26),
-};
-static const unsigned int du0_clk1_out_mux[] = {
-	DU0_DOTCLKOUT1_MARK
-};
-static const unsigned int du0_clk_in_pins[] = {
-	/* CLKIN */
-	RCAR_GP_PIN(2, 24),
-};
-static const unsigned int du0_clk_in_mux[] = {
-	DU0_DOTCLKIN_MARK
-};
-static const unsigned int du0_sync_pins[] = {
-	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
-	RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27),
-};
-static const unsigned int du0_sync_mux[] = {
-	DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK
-};
-static const unsigned int du0_oddf_pins[] = {
-	/* EXODDF/ODDF/DISP/CDE */
-	RCAR_GP_PIN(2, 29),
-};
-static const unsigned int du0_oddf_mux[] = {
-	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
-};
-static const unsigned int du0_cde_pins[] = {
-	/* CDE */
-	RCAR_GP_PIN(2, 31),
-};
-static const unsigned int du0_cde_mux[] = {
-	DU0_CDE_MARK,
-};
-static const unsigned int du0_disp_pins[] = {
-	/* DISP */
-	RCAR_GP_PIN(2, 30),
-};
-static const unsigned int du0_disp_mux[] = {
-	DU0_DISP_MARK
-};
-static const unsigned int du1_rgb666_pins[] = {
-	/* R[7:2], G[7:2], B[7:2] */
-	RCAR_GP_PIN(4, 7),  RCAR_GP_PIN(4, 6),  RCAR_GP_PIN(4, 5),
-	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 3),  RCAR_GP_PIN(4, 2),
-	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
-	RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
-	RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
-	RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
-};
-static const unsigned int du1_rgb666_mux[] = {
-	DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
-	DU1_DR3_MARK, DU1_DR2_MARK,
-	DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
-	DU1_DG3_MARK, DU1_DG2_MARK,
-	DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
-	DU1_DB3_MARK, DU1_DB2_MARK,
-};
-static const unsigned int du1_rgb888_pins[] = {
-	/* R[7:0], G[7:0], B[7:0] */
-	RCAR_GP_PIN(4, 7),  RCAR_GP_PIN(4, 6),  RCAR_GP_PIN(4, 5),
-	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 3),  RCAR_GP_PIN(4, 2),
-	RCAR_GP_PIN(4, 1),  RCAR_GP_PIN(4, 0),
-	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
-	RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
-	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 8),
-	RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
-	RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
-	RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
-};
-static const unsigned int du1_rgb888_mux[] = {
-	DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
-	DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
-	DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
-	DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
-	DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
-	DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
-};
-static const unsigned int du1_clk0_out_pins[] = {
-	/* DOTCLKOUT0 */
-	RCAR_GP_PIN(4, 25),
-};
-static const unsigned int du1_clk0_out_mux[] = {
-	DU1_DOTCLKOUT0_MARK
-};
-static const unsigned int du1_clk1_out_pins[] = {
-	/* DOTCLKOUT1 */
-	RCAR_GP_PIN(4, 26),
-};
-static const unsigned int du1_clk1_out_mux[] = {
-	DU1_DOTCLKOUT1_MARK
-};
-static const unsigned int du1_clk_in_pins[] = {
-	/* DOTCLKIN */
-	RCAR_GP_PIN(4, 24),
-};
-static const unsigned int du1_clk_in_mux[] = {
-	DU1_DOTCLKIN_MARK
-};
-static const unsigned int du1_sync_pins[] = {
-	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
-	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
-};
-static const unsigned int du1_sync_mux[] = {
-	DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
-};
-static const unsigned int du1_oddf_pins[] = {
-	/* EXODDF/ODDF/DISP/CDE */
-	RCAR_GP_PIN(4, 29),
-};
-static const unsigned int du1_oddf_mux[] = {
-	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
-};
-static const unsigned int du1_cde_pins[] = {
-	/* CDE */
-	RCAR_GP_PIN(4, 31),
-};
-static const unsigned int du1_cde_mux[] = {
-	DU1_CDE_MARK
-};
-static const unsigned int du1_disp_pins[] = {
-	/* DISP */
-	RCAR_GP_PIN(4, 30),
-};
-static const unsigned int du1_disp_mux[] = {
-	DU1_DISP_MARK
-};
-/* - ETH -------------------------------------------------------------------- */
-static const unsigned int eth_link_pins[] = {
-	/* LINK */
-	RCAR_GP_PIN(3, 18),
-};
-static const unsigned int eth_link_mux[] = {
-	ETH_LINK_MARK,
-};
-static const unsigned int eth_magic_pins[] = {
-	/* MAGIC */
-	RCAR_GP_PIN(3, 22),
-};
-static const unsigned int eth_magic_mux[] = {
-	ETH_MAGIC_MARK,
-};
-static const unsigned int eth_mdio_pins[] = {
-	/* MDC, MDIO */
-	RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13),
-};
-static const unsigned int eth_mdio_mux[] = {
-	ETH_MDC_MARK, ETH_MDIO_MARK,
-};
-static const unsigned int eth_rmii_pins[] = {
-	/* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
-	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15),
-	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20),
-	RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19),
-};
-static const unsigned int eth_rmii_mux[] = {
-	ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
-	ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
-};
-static const unsigned int eth_link_b_pins[] = {
-	/* LINK */
-	RCAR_GP_PIN(5, 15),
-};
-static const unsigned int eth_link_b_mux[] = {
-	ETH_LINK_B_MARK,
-};
-static const unsigned int eth_magic_b_pins[] = {
-	/* MAGIC */
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int eth_magic_b_mux[] = {
-	ETH_MAGIC_B_MARK,
-};
-static const unsigned int eth_mdio_b_pins[] = {
-	/* MDC, MDIO */
-	RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10),
-};
-static const unsigned int eth_mdio_b_mux[] = {
-	ETH_MDC_B_MARK, ETH_MDIO_B_MARK,
-};
-static const unsigned int eth_rmii_b_pins[] = {
-	/* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
-	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12),
-	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17),
-	RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16),
-};
-static const unsigned int eth_rmii_b_mux[] = {
-	ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK,
-	ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK,
-};
-/* - HSCIF0 ----------------------------------------------------------------- */
-static const unsigned int hscif0_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
-};
-static const unsigned int hscif0_data_mux[] = {
-	HSCIF0_HRX_MARK, HSCIF0_HTX_MARK,
-};
-static const unsigned int hscif0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 29),
-};
-static const unsigned int hscif0_clk_mux[] = {
-	HSCIF0_HSCK_MARK,
-};
-static const unsigned int hscif0_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
-};
-static const unsigned int hscif0_ctrl_mux[] = {
-	HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK,
-};
-static const unsigned int hscif0_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31),
-};
-static const unsigned int hscif0_data_b_mux[] = {
-	HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK,
-};
-static const unsigned int hscif0_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 0),
-};
-static const unsigned int hscif0_clk_b_mux[] = {
-	HSCIF0_HSCK_B_MARK,
-};
-/* - HSCIF1 ----------------------------------------------------------------- */
-static const unsigned int hscif1_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
-};
-static const unsigned int hscif1_data_mux[] = {
-	HSCIF1_HRX_MARK, HSCIF1_HTX_MARK,
-};
-static const unsigned int hscif1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 10),
-};
-static const unsigned int hscif1_clk_mux[] = {
-	HSCIF1_HSCK_MARK,
-};
-static const unsigned int hscif1_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
-};
-static const unsigned int hscif1_ctrl_mux[] = {
-	HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK,
-};
-static const unsigned int hscif1_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
-};
-static const unsigned int hscif1_data_b_mux[] = {
-	HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK,
-};
-static const unsigned int hscif1_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
-};
-static const unsigned int hscif1_ctrl_b_mux[] = {
-	HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK,
-};
-/* - HSCIF2 ----------------------------------------------------------------- */
-static const unsigned int hscif2_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-};
-static const unsigned int hscif2_data_mux[] = {
-	HSCIF2_HRX_MARK, HSCIF2_HTX_MARK,
-};
-static const unsigned int hscif2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 10),
-};
-static const unsigned int hscif2_clk_mux[] = {
-	HSCIF2_HSCK_MARK,
-};
-static const unsigned int hscif2_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
-};
-static const unsigned int hscif2_ctrl_mux[] = {
-	HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK,
-};
-/* - I2C0 ------------------------------------------------------------------- */
-static const unsigned int i2c0_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
-};
-static const unsigned int i2c0_mux[] = {
-	I2C0_SCL_MARK, I2C0_SDA_MARK,
-};
-static const unsigned int i2c0_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
-};
-static const unsigned int i2c0_b_mux[] = {
-	I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
-};
-static const unsigned int i2c0_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
-};
-static const unsigned int i2c0_c_mux[] = {
-	I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
-};
-static const unsigned int i2c0_d_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
-};
-static const unsigned int i2c0_d_mux[] = {
-	I2C0_SCL_D_MARK, I2C0_SDA_D_MARK,
-};
-static const unsigned int i2c0_e_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
-};
-static const unsigned int i2c0_e_mux[] = {
-	I2C0_SCL_E_MARK, I2C0_SDA_E_MARK,
-};
-/* - I2C1 ------------------------------------------------------------------- */
-static const unsigned int i2c1_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
-};
-static const unsigned int i2c1_mux[] = {
-	I2C1_SCL_MARK, I2C1_SDA_MARK,
-};
-static const unsigned int i2c1_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-};
-static const unsigned int i2c1_b_mux[] = {
-	I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
-};
-static const unsigned int i2c1_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
-};
-static const unsigned int i2c1_c_mux[] = {
-	I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
-};
-static const unsigned int i2c1_d_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
-};
-static const unsigned int i2c1_d_mux[] = {
-	I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
-};
-static const unsigned int i2c1_e_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
-};
-static const unsigned int i2c1_e_mux[] = {
-	I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
-};
-/* - I2C2 ------------------------------------------------------------------- */
-static const unsigned int i2c2_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
-};
-static const unsigned int i2c2_mux[] = {
-	I2C2_SCL_MARK, I2C2_SDA_MARK,
-};
-static const unsigned int i2c2_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
-};
-static const unsigned int i2c2_b_mux[] = {
-	I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
-};
-static const unsigned int i2c2_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
-};
-static const unsigned int i2c2_c_mux[] = {
-	I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
-};
-static const unsigned int i2c2_d_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-};
-static const unsigned int i2c2_d_mux[] = {
-	I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
-};
-static const unsigned int i2c2_e_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
-};
-static const unsigned int i2c2_e_mux[] = {
-	I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
-};
-/* - I2C3 ------------------------------------------------------------------- */
-static const unsigned int i2c3_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
-};
-static const unsigned int i2c3_mux[] = {
-	I2C3_SCL_MARK, I2C3_SDA_MARK,
-};
-static const unsigned int i2c3_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
-};
-static const unsigned int i2c3_b_mux[] = {
-	I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
-};
-static const unsigned int i2c3_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
-};
-static const unsigned int i2c3_c_mux[] = {
-	I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
-};
-static const unsigned int i2c3_d_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
-};
-static const unsigned int i2c3_d_mux[] = {
-	I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
-};
-static const unsigned int i2c3_e_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
-};
-static const unsigned int i2c3_e_mux[] = {
-	I2C3_SCL_E_MARK, I2C3_SDA_E_MARK,
-};
-/* - I2C4 ------------------------------------------------------------------- */
-static const unsigned int i2c4_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
-};
-static const unsigned int i2c4_mux[] = {
-	I2C4_SCL_MARK, I2C4_SDA_MARK,
-};
-static const unsigned int i2c4_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
-};
-static const unsigned int i2c4_b_mux[] = {
-	I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
-};
-static const unsigned int i2c4_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
-};
-static const unsigned int i2c4_c_mux[] = {
-	I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
-};
-static const unsigned int i2c4_d_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
-};
-static const unsigned int i2c4_d_mux[] = {
-	I2C4_SCL_D_MARK, I2C4_SDA_D_MARK,
-};
-static const unsigned int i2c4_e_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
-};
-static const unsigned int i2c4_e_mux[] = {
-	I2C4_SCL_E_MARK, I2C4_SDA_E_MARK,
-};
-/* - I2C5 ------------------------------------------------------------------- */
-static const unsigned int i2c5_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
-};
-static const unsigned int i2c5_mux[] = {
-	I2C5_SCL_MARK, I2C5_SDA_MARK,
-};
-static const unsigned int i2c5_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-};
-static const unsigned int i2c5_b_mux[] = {
-	I2C5_SCL_B_MARK, I2C5_SDA_B_MARK,
-};
-static const unsigned int i2c5_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
-};
-static const unsigned int i2c5_c_mux[] = {
-	I2C5_SCL_C_MARK, I2C5_SDA_C_MARK,
-};
-static const unsigned int i2c5_d_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
-};
-static const unsigned int i2c5_d_mux[] = {
-	I2C5_SCL_D_MARK, I2C5_SDA_D_MARK,
-};
-/* - INTC ------------------------------------------------------------------- */
-static const unsigned int intc_irq0_pins[] = {
-	/* IRQ0 */
-	RCAR_GP_PIN(4, 4),
-};
-static const unsigned int intc_irq0_mux[] = {
-	IRQ0_MARK,
-};
-static const unsigned int intc_irq1_pins[] = {
-	/* IRQ1 */
-	RCAR_GP_PIN(4, 18),
-};
-static const unsigned int intc_irq1_mux[] = {
-	IRQ1_MARK,
-};
-static const unsigned int intc_irq2_pins[] = {
-	/* IRQ2 */
-	RCAR_GP_PIN(4, 19),
-};
-static const unsigned int intc_irq2_mux[] = {
-	IRQ2_MARK,
-};
-static const unsigned int intc_irq3_pins[] = {
-	/* IRQ3 */
-	RCAR_GP_PIN(0, 7),
-};
-static const unsigned int intc_irq3_mux[] = {
-	IRQ3_MARK,
-};
-static const unsigned int intc_irq4_pins[] = {
-	/* IRQ4 */
-	RCAR_GP_PIN(0, 0),
-};
-static const unsigned int intc_irq4_mux[] = {
-	IRQ4_MARK,
-};
-static const unsigned int intc_irq5_pins[] = {
-	/* IRQ5 */
-	RCAR_GP_PIN(4, 1),
-};
-static const unsigned int intc_irq5_mux[] = {
-	IRQ5_MARK,
-};
-static const unsigned int intc_irq6_pins[] = {
-	/* IRQ6 */
-	RCAR_GP_PIN(0, 10),
-};
-static const unsigned int intc_irq6_mux[] = {
-	IRQ6_MARK,
-};
-static const unsigned int intc_irq7_pins[] = {
-	/* IRQ7 */
-	RCAR_GP_PIN(6, 15),
-};
-static const unsigned int intc_irq7_mux[] = {
-	IRQ7_MARK,
-};
-static const unsigned int intc_irq8_pins[] = {
-	/* IRQ8 */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int intc_irq8_mux[] = {
-	IRQ8_MARK,
-};
-static const unsigned int intc_irq9_pins[] = {
-	/* IRQ9 */
-	RCAR_GP_PIN(5, 10),
-};
-static const unsigned int intc_irq9_mux[] = {
-	IRQ9_MARK,
-};
-/* - MMCIF ------------------------------------------------------------------ */
-static const unsigned int mmc_data1_pins[] = {
-	/* D[0] */
-	RCAR_GP_PIN(6, 18),
-};
-static const unsigned int mmc_data1_mux[] = {
-	MMC_D0_MARK,
-};
-static const unsigned int mmc_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
-	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
-};
-static const unsigned int mmc_data4_mux[] = {
-	MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
-};
-static const unsigned int mmc_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
-	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
-	RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
-	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
-};
-static const unsigned int mmc_data8_mux[] = {
-	MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
-	MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
-};
-static const unsigned int mmc_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
-};
-static const unsigned int mmc_ctrl_mux[] = {
-	MMC_CLK_MARK, MMC_CMD_MARK,
-};
-/* - MSIOF0 ----------------------------------------------------------------- */
-static const unsigned int msiof0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 4),
-};
-static const unsigned int msiof0_clk_mux[] = {
-	MSIOF0_SCK_MARK,
-};
-static const unsigned int msiof0_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(4, 5),
-};
-static const unsigned int msiof0_sync_mux[] = {
-	MSIOF0_SYNC_MARK,
-};
-static const unsigned int msiof0_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(4, 6),
-};
-static const unsigned int msiof0_ss1_mux[] = {
-	MSIOF0_SS1_MARK,
-};
-static const unsigned int msiof0_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(4, 7),
-};
-static const unsigned int msiof0_ss2_mux[] = {
-	MSIOF0_SS2_MARK,
-};
-static const unsigned int msiof0_rx_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(4, 2),
-};
-static const unsigned int msiof0_rx_mux[] = {
-	MSIOF0_RXD_MARK,
-};
-static const unsigned int msiof0_tx_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(4, 3),
-};
-static const unsigned int msiof0_tx_mux[] = {
-	MSIOF0_TXD_MARK,
-};
-/* - MSIOF1 ----------------------------------------------------------------- */
-static const unsigned int msiof1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 26),
-};
-static const unsigned int msiof1_clk_mux[] = {
-	MSIOF1_SCK_MARK,
-};
-static const unsigned int msiof1_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 27),
-};
-static const unsigned int msiof1_sync_mux[] = {
-	MSIOF1_SYNC_MARK,
-};
-static const unsigned int msiof1_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 28),
-};
-static const unsigned int msiof1_ss1_mux[] = {
-	MSIOF1_SS1_MARK,
-};
-static const unsigned int msiof1_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 29),
-};
-static const unsigned int msiof1_ss2_mux[] = {
-	MSIOF1_SS2_MARK,
-};
-static const unsigned int msiof1_rx_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 24),
-};
-static const unsigned int msiof1_rx_mux[] = {
-	MSIOF1_RXD_MARK,
-};
-static const unsigned int msiof1_tx_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 25),
-};
-static const unsigned int msiof1_tx_mux[] = {
-	MSIOF1_TXD_MARK,
-};
-static const unsigned int msiof1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 3),
-};
-static const unsigned int msiof1_clk_b_mux[] = {
-	MSIOF1_SCK_B_MARK,
-};
-static const unsigned int msiof1_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(5, 4),
-};
-static const unsigned int msiof1_sync_b_mux[] = {
-	MSIOF1_SYNC_B_MARK,
-};
-static const unsigned int msiof1_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(5, 5),
-};
-static const unsigned int msiof1_ss1_b_mux[] = {
-	MSIOF1_SS1_B_MARK,
-};
-static const unsigned int msiof1_ss2_b_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(5, 6),
-};
-static const unsigned int msiof1_ss2_b_mux[] = {
-	MSIOF1_SS2_B_MARK,
-};
-static const unsigned int msiof1_rx_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 1),
-};
-static const unsigned int msiof1_rx_b_mux[] = {
-	MSIOF1_RXD_B_MARK,
-};
-static const unsigned int msiof1_tx_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(5, 2),
-};
-static const unsigned int msiof1_tx_b_mux[] = {
-	MSIOF1_TXD_B_MARK,
-};
-/* - MSIOF2 ----------------------------------------------------------------- */
-static const unsigned int msiof2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 0),
-};
-static const unsigned int msiof2_clk_mux[] = {
-	MSIOF2_SCK_MARK,
-};
-static const unsigned int msiof2_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 1),
-};
-static const unsigned int msiof2_sync_mux[] = {
-	MSIOF2_SYNC_MARK,
-};
-static const unsigned int msiof2_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(1, 2),
-};
-static const unsigned int msiof2_ss1_mux[] = {
-	MSIOF2_SS1_MARK,
-};
-static const unsigned int msiof2_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(1, 3),
-};
-static const unsigned int msiof2_ss2_mux[] = {
-	MSIOF2_SS2_MARK,
-};
-static const unsigned int msiof2_rx_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 30),
-};
-static const unsigned int msiof2_rx_mux[] = {
-	MSIOF2_RXD_MARK,
-};
-static const unsigned int msiof2_tx_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 31),
-};
-static const unsigned int msiof2_tx_mux[] = {
-	MSIOF2_TXD_MARK,
-};
-static const unsigned int msiof2_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 15),
-};
-static const unsigned int msiof2_clk_b_mux[] = {
-	MSIOF2_SCK_B_MARK,
-};
-static const unsigned int msiof2_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(3, 16),
-};
-static const unsigned int msiof2_sync_b_mux[] = {
-	MSIOF2_SYNC_B_MARK,
-};
-static const unsigned int msiof2_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(3, 17),
-};
-static const unsigned int msiof2_ss1_b_mux[] = {
-	MSIOF2_SS1_B_MARK,
-};
-static const unsigned int msiof2_ss2_b_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(3, 18),
-};
-static const unsigned int msiof2_ss2_b_mux[] = {
-	MSIOF2_SS2_B_MARK,
-};
-static const unsigned int msiof2_rx_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(3, 13),
-};
-static const unsigned int msiof2_rx_b_mux[] = {
-	MSIOF2_RXD_B_MARK,
-};
-static const unsigned int msiof2_tx_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(3, 14),
-};
-static const unsigned int msiof2_tx_b_mux[] = {
-	MSIOF2_TXD_B_MARK,
-};
-/* - PWM -------------------------------------------------------------------- */
-static const unsigned int pwm0_pins[] = {
-	RCAR_GP_PIN(1, 14),
-};
-static const unsigned int pwm0_mux[] = {
-	PWM0_MARK,
-};
-static const unsigned int pwm0_b_pins[] = {
-	RCAR_GP_PIN(5, 3),
-};
-static const unsigned int pwm0_b_mux[] = {
-	PWM0_B_MARK,
-};
-static const unsigned int pwm1_pins[] = {
-	RCAR_GP_PIN(4, 5),
-};
-static const unsigned int pwm1_mux[] = {
-	PWM1_MARK,
-};
-static const unsigned int pwm1_b_pins[] = {
-	RCAR_GP_PIN(5, 10),
-};
-static const unsigned int pwm1_b_mux[] = {
-	PWM1_B_MARK,
-};
-static const unsigned int pwm1_c_pins[] = {
-	RCAR_GP_PIN(1, 18),
-};
-static const unsigned int pwm1_c_mux[] = {
-	PWM1_C_MARK,
-};
-static const unsigned int pwm2_pins[] = {
-	RCAR_GP_PIN(4, 10),
-};
-static const unsigned int pwm2_mux[] = {
-	PWM2_MARK,
-};
-static const unsigned int pwm2_b_pins[] = {
-	RCAR_GP_PIN(5, 17),
-};
-static const unsigned int pwm2_b_mux[] = {
-	PWM2_B_MARK,
-};
-static const unsigned int pwm2_c_pins[] = {
-	RCAR_GP_PIN(0, 13),
-};
-static const unsigned int pwm2_c_mux[] = {
-	PWM2_C_MARK,
-};
-static const unsigned int pwm3_pins[] = {
-	RCAR_GP_PIN(4, 13),
-};
-static const unsigned int pwm3_mux[] = {
-	PWM3_MARK,
-};
-static const unsigned int pwm3_b_pins[] = {
-	RCAR_GP_PIN(0, 16),
-};
-static const unsigned int pwm3_b_mux[] = {
-	PWM3_B_MARK,
-};
-static const unsigned int pwm4_pins[] = {
-	RCAR_GP_PIN(1, 3),
-};
-static const unsigned int pwm4_mux[] = {
-	PWM4_MARK,
-};
-static const unsigned int pwm4_b_pins[] = {
-	RCAR_GP_PIN(0, 21),
-};
-static const unsigned int pwm4_b_mux[] = {
-	PWM4_B_MARK,
-};
-static const unsigned int pwm5_pins[] = {
-	RCAR_GP_PIN(3, 30),
-};
-static const unsigned int pwm5_mux[] = {
-	PWM5_MARK,
-};
-static const unsigned int pwm5_b_pins[] = {
-	RCAR_GP_PIN(4, 0),
-};
-static const unsigned int pwm5_b_mux[] = {
-	PWM5_B_MARK,
-};
-static const unsigned int pwm5_c_pins[] = {
-	RCAR_GP_PIN(0, 10),
-};
-static const unsigned int pwm5_c_mux[] = {
-	PWM5_C_MARK,
-};
-static const unsigned int pwm6_pins[] = {
-	RCAR_GP_PIN(4, 8),
-};
-static const unsigned int pwm6_mux[] = {
-	PWM6_MARK,
-};
-static const unsigned int pwm6_b_pins[] = {
-	RCAR_GP_PIN(0, 7),
-};
-static const unsigned int pwm6_b_mux[] = {
-	PWM6_B_MARK,
-};
-/* - QSPI ------------------------------------------------------------------- */
-static const unsigned int qspi_ctrl_pins[] = {
-	/* SPCLK, SSL */
-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
-};
-static const unsigned int qspi_ctrl_mux[] = {
-	SPCLK_MARK, SSL_MARK,
-};
-static const unsigned int qspi_data2_pins[] = {
-	/* MOSI_IO0, MISO_IO1 */
-	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
-};
-static const unsigned int qspi_data2_mux[] = {
-	MOSI_IO0_MARK, MISO_IO1_MARK,
-};
-static const unsigned int qspi_data4_pins[] = {
-	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
-	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-	RCAR_GP_PIN(1, 8),
-};
-static const unsigned int qspi_data4_mux[] = {
-	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
-};
-/* - SCIF0 ------------------------------------------------------------------ */
-static const unsigned int scif0_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
-};
-static const unsigned int scif0_data_mux[] = {
-	SCIF0_RXD_MARK, SCIF0_TXD_MARK,
-};
-static const unsigned int scif0_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
-};
-static const unsigned int scif0_data_b_mux[] = {
-	SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK,
-};
-static const unsigned int scif0_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
-};
-static const unsigned int scif0_data_c_mux[] = {
-	SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK,
-};
-static const unsigned int scif0_data_d_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
-};
-static const unsigned int scif0_data_d_mux[] = {
-	SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK,
-};
-/* - SCIF1 ------------------------------------------------------------------ */
-static const unsigned int scif1_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
-};
-static const unsigned int scif1_data_mux[] = {
-	SCIF1_RXD_MARK, SCIF1_TXD_MARK,
-};
-static const unsigned int scif1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 13),
-};
-static const unsigned int scif1_clk_mux[] = {
-	SCIF1_SCK_MARK,
-};
-static const unsigned int scif1_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
-};
-static const unsigned int scif1_data_b_mux[] = {
-	SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK,
-};
-static const unsigned int scif1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 10),
-};
-static const unsigned int scif1_clk_b_mux[] = {
-	SCIF1_SCK_B_MARK,
-};
-static const unsigned int scif1_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
-};
-static const unsigned int scif1_data_c_mux[] = {
-	SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK,
-};
-static const unsigned int scif1_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 10),
-};
-static const unsigned int scif1_clk_c_mux[] = {
-	SCIF1_SCK_C_MARK,
-};
-/* - SCIF2 ------------------------------------------------------------------ */
-static const unsigned int scif2_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
-};
-static const unsigned int scif2_data_mux[] = {
-	SCIF2_RXD_MARK, SCIF2_TXD_MARK,
-};
-static const unsigned int scif2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 18),
-};
-static const unsigned int scif2_clk_mux[] = {
-	SCIF2_SCK_MARK,
-};
-static const unsigned int scif2_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
-};
-static const unsigned int scif2_data_b_mux[] = {
-	SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK,
-};
-static const unsigned int scif2_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 17),
-};
-static const unsigned int scif2_clk_b_mux[] = {
-	SCIF2_SCK_B_MARK,
-};
-static const unsigned int scif2_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
-};
-static const unsigned int scif2_data_c_mux[] = {
-	SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK,
-};
-static const unsigned int scif2_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 19),
-};
-static const unsigned int scif2_clk_c_mux[] = {
-	SCIF2_SCK_C_MARK,
-};
-/* - SCIF3 ------------------------------------------------------------------ */
-static const unsigned int scif3_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
-};
-static const unsigned int scif3_data_mux[] = {
-	SCIF3_RXD_MARK, SCIF3_TXD_MARK,
-};
-static const unsigned int scif3_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 19),
-};
-static const unsigned int scif3_clk_mux[] = {
-	SCIF3_SCK_MARK,
-};
-static const unsigned int scif3_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
-};
-static const unsigned int scif3_data_b_mux[] = {
-	SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK,
-};
-static const unsigned int scif3_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 22),
-};
-static const unsigned int scif3_clk_b_mux[] = {
-	SCIF3_SCK_B_MARK,
-};
-/* - SCIF4 ------------------------------------------------------------------ */
-static const unsigned int scif4_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
-};
-static const unsigned int scif4_data_mux[] = {
-	SCIF4_RXD_MARK, SCIF4_TXD_MARK,
-};
-static const unsigned int scif4_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
-};
-static const unsigned int scif4_data_b_mux[] = {
-	SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK,
-};
-static const unsigned int scif4_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-};
-static const unsigned int scif4_data_c_mux[] = {
-	SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK,
-};
-static const unsigned int scif4_data_d_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
-};
-static const unsigned int scif4_data_d_mux[] = {
-	SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK,
-};
-static const unsigned int scif4_data_e_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
-};
-static const unsigned int scif4_data_e_mux[] = {
-	SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK,
-};
-/* - SCIF5 ------------------------------------------------------------------ */
-static const unsigned int scif5_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
-};
-static const unsigned int scif5_data_mux[] = {
-	SCIF5_RXD_MARK, SCIF5_TXD_MARK,
-};
-static const unsigned int scif5_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
-};
-static const unsigned int scif5_data_b_mux[] = {
-	SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK,
-};
-static const unsigned int scif5_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11),
-};
-static const unsigned int scif5_data_c_mux[] = {
-	SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK,
-};
-static const unsigned int scif5_data_d_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-};
-static const unsigned int scif5_data_d_mux[] = {
-	SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK,
-};
-/* - SCIFA0 ----------------------------------------------------------------- */
-static const unsigned int scifa0_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
-};
-static const unsigned int scifa0_data_mux[] = {
-	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
-};
-static const unsigned int scifa0_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
-};
-static const unsigned int scifa0_data_b_mux[] = {
-	SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
-};
-static const unsigned int scifa0_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
-};
-static const unsigned int scifa0_data_c_mux[] = {
-	SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK
-};
-static const unsigned int scifa0_data_d_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
-};
-static const unsigned int scifa0_data_d_mux[] = {
-	SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK
-};
-/* - SCIFA1 ----------------------------------------------------------------- */
-static const unsigned int scifa1_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-};
-static const unsigned int scifa1_data_mux[] = {
-	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
-};
-static const unsigned int scifa1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 13),
-};
-static const unsigned int scifa1_clk_mux[] = {
-	SCIFA1_SCK_MARK,
-};
-static const unsigned int scifa1_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
-};
-static const unsigned int scifa1_data_b_mux[] = {
-	SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
-};
-static const unsigned int scifa1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 27),
-};
-static const unsigned int scifa1_clk_b_mux[] = {
-	SCIFA1_SCK_B_MARK,
-};
-static const unsigned int scifa1_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
-};
-static const unsigned int scifa1_data_c_mux[] = {
-	SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
-};
-static const unsigned int scifa1_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 4),
-};
-static const unsigned int scifa1_clk_c_mux[] = {
-	SCIFA1_SCK_C_MARK,
-};
-/* - SCIFA2 ----------------------------------------------------------------- */
-static const unsigned int scifa2_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
-};
-static const unsigned int scifa2_data_mux[] = {
-	SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
-};
-static const unsigned int scifa2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 15),
-};
-static const unsigned int scifa2_clk_mux[] = {
-	SCIFA2_SCK_MARK,
-};
-static const unsigned int scifa2_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0),
-};
-static const unsigned int scifa2_data_b_mux[] = {
-	SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
-};
-static const unsigned int scifa2_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 30),
-};
-static const unsigned int scifa2_clk_b_mux[] = {
-	SCIFA2_SCK_B_MARK,
-};
-/* - SCIFA3 ----------------------------------------------------------------- */
-static const unsigned int scifa3_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
-};
-static const unsigned int scifa3_data_mux[] = {
-	SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
-};
-static const unsigned int scifa3_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 24),
-};
-static const unsigned int scifa3_clk_mux[] = {
-	SCIFA3_SCK_MARK,
-};
-static const unsigned int scifa3_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
-};
-static const unsigned int scifa3_data_b_mux[] = {
-	SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
-};
-static const unsigned int scifa3_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 0),
-};
-static const unsigned int scifa3_clk_b_mux[] = {
-	SCIFA3_SCK_B_MARK,
-};
-/* - SCIFA4 ----------------------------------------------------------------- */
-static const unsigned int scifa4_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12),
-};
-static const unsigned int scifa4_data_mux[] = {
-	SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
-};
-static const unsigned int scifa4_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23),
-};
-static const unsigned int scifa4_data_b_mux[] = {
-	SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
-};
-static const unsigned int scifa4_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
-};
-static const unsigned int scifa4_data_c_mux[] = {
-	SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
-};
-static const unsigned int scifa4_data_d_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
-};
-static const unsigned int scifa4_data_d_mux[] = {
-	SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK,
-};
-/* - SCIFA5 ----------------------------------------------------------------- */
-static const unsigned int scifa5_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
-};
-static const unsigned int scifa5_data_mux[] = {
-	SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
-};
-static const unsigned int scifa5_data_b_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29),
-};
-static const unsigned int scifa5_data_b_mux[] = {
-	SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
-};
-static const unsigned int scifa5_data_c_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
-};
-static const unsigned int scifa5_data_c_mux[] = {
-	SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
-};
-static const unsigned int scifa5_data_d_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
-};
-static const unsigned int scifa5_data_d_mux[] = {
-	SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK,
-};
-/* - SCIFB0 ----------------------------------------------------------------- */
-static const unsigned int scifb0_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20),
-};
-static const unsigned int scifb0_data_mux[] = {
-	SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
-};
-static const unsigned int scifb0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 19),
-};
-static const unsigned int scifb0_clk_mux[] = {
-	SCIFB0_SCK_MARK,
-};
-static const unsigned int scifb0_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22),
-};
-static const unsigned int scifb0_ctrl_mux[] = {
-	SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
-};
-/* - SCIFB1 ----------------------------------------------------------------- */
-static const unsigned int scifb1_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17),
-};
-static const unsigned int scifb1_data_mux[] = {
-	SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
-};
-static const unsigned int scifb1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 16),
-};
-static const unsigned int scifb1_clk_mux[] = {
-	SCIFB1_SCK_MARK,
-};
-/* - SCIFB2 ----------------------------------------------------------------- */
-static const unsigned int scifb2_data_pins[] = {
-	/* RXD, TXD */
-	RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
-};
-static const unsigned int scifb2_data_mux[] = {
-	SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
-};
-static const unsigned int scifb2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 15),
-};
-static const unsigned int scifb2_clk_mux[] = {
-	SCIFB2_SCK_MARK,
-};
-static const unsigned int scifb2_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
-};
-static const unsigned int scifb2_ctrl_mux[] = {
-	SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
-};
-/* - SCIF Clock ------------------------------------------------------------- */
-static const unsigned int scif_clk_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(1, 23),
-};
-static const unsigned int scif_clk_mux[] = {
-	SCIF_CLK_MARK,
-};
-static const unsigned int scif_clk_b_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(3, 29),
-};
-static const unsigned int scif_clk_b_mux[] = {
-	SCIF_CLK_B_MARK,
-};
-/* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 2),
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SD0_DATA0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
-	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
-};
-static const unsigned int sdhi0_data4_mux[] = {
-	SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
-};
-static const unsigned int sdhi0_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
-};
-static const unsigned int sdhi0_ctrl_mux[] = {
-	SD0_CLK_MARK, SD0_CMD_MARK,
-};
-static const unsigned int sdhi0_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(6, 6),
-};
-static const unsigned int sdhi0_cd_mux[] = {
-	SD0_CD_MARK,
-};
-static const unsigned int sdhi0_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(6, 7),
-};
-static const unsigned int sdhi0_wp_mux[] = {
-	SD0_WP_MARK,
-};
-/* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 10),
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	SD1_DATA0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
-	RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
-};
-static const unsigned int sdhi1_data4_mux[] = {
-	SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
-};
-static const unsigned int sdhi1_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
-};
-static const unsigned int sdhi1_ctrl_mux[] = {
-	SD1_CLK_MARK, SD1_CMD_MARK,
-};
-static const unsigned int sdhi1_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(6, 14),
-};
-static const unsigned int sdhi1_cd_mux[] = {
-	SD1_CD_MARK,
-};
-static const unsigned int sdhi1_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(6, 15),
-};
-static const unsigned int sdhi1_wp_mux[] = {
-	SD1_WP_MARK,
-};
-/* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 18),
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SD2_DATA0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
-	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
-};
-static const unsigned int sdhi2_data4_mux[] = {
-	SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
-};
-static const unsigned int sdhi2_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
-};
-static const unsigned int sdhi2_ctrl_mux[] = {
-	SD2_CLK_MARK, SD2_CMD_MARK,
-};
-static const unsigned int sdhi2_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(6, 22),
-};
-static const unsigned int sdhi2_cd_mux[] = {
-	SD2_CD_MARK,
-};
-static const unsigned int sdhi2_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(6, 23),
-};
-static const unsigned int sdhi2_wp_mux[] = {
-	SD2_WP_MARK,
-};
-/* - SSI -------------------------------------------------------------------- */
-static const unsigned int ssi0_data_pins[] = {
-	/* SDATA0 */
-	RCAR_GP_PIN(5, 3),
-};
-static const unsigned int ssi0_data_mux[] = {
-	SSI_SDATA0_MARK,
-};
-static const unsigned int ssi0129_ctrl_pins[] = {
-	/* SCK0129, WS0129 */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-};
-static const unsigned int ssi0129_ctrl_mux[] = {
-	SSI_SCK0129_MARK, SSI_WS0129_MARK,
-};
-static const unsigned int ssi1_data_pins[] = {
-	/* SDATA1 */
-	RCAR_GP_PIN(5, 13),
-};
-static const unsigned int ssi1_data_mux[] = {
-	SSI_SDATA1_MARK,
-};
-static const unsigned int ssi1_ctrl_pins[] = {
-	/* SCK1, WS1 */
-	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
-};
-static const unsigned int ssi1_ctrl_mux[] = {
-	SSI_SCK1_MARK, SSI_WS1_MARK,
-};
-static const unsigned int ssi1_data_b_pins[] = {
-	/* SDATA1 */
-	RCAR_GP_PIN(4, 13),
-};
-static const unsigned int ssi1_data_b_mux[] = {
-	SSI_SDATA1_B_MARK,
-};
-static const unsigned int ssi1_ctrl_b_pins[] = {
-	/* SCK1, WS1 */
-	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
-};
-static const unsigned int ssi1_ctrl_b_mux[] = {
-	SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
-};
-static const unsigned int ssi2_data_pins[] = {
-	/* SDATA2 */
-	RCAR_GP_PIN(5, 16),
-};
-static const unsigned int ssi2_data_mux[] = {
-	SSI_SDATA2_MARK,
-};
-static const unsigned int ssi2_ctrl_pins[] = {
-	/* SCK2, WS2 */
-	RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
-};
-static const unsigned int ssi2_ctrl_mux[] = {
-	SSI_SCK2_MARK, SSI_WS2_MARK,
-};
-static const unsigned int ssi2_data_b_pins[] = {
-	/* SDATA2 */
-	RCAR_GP_PIN(4, 16),
-};
-static const unsigned int ssi2_data_b_mux[] = {
-	SSI_SDATA2_B_MARK,
-};
-static const unsigned int ssi2_ctrl_b_pins[] = {
-	/* SCK2, WS2 */
-	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
-};
-static const unsigned int ssi2_ctrl_b_mux[] = {
-	SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
-};
-static const unsigned int ssi3_data_pins[] = {
-	/* SDATA3 */
-	RCAR_GP_PIN(5, 6),
-};
-static const unsigned int ssi3_data_mux[] = {
-	SSI_SDATA3_MARK
-};
-static const unsigned int ssi34_ctrl_pins[] = {
-	/* SCK34, WS34 */
-	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
-};
-static const unsigned int ssi34_ctrl_mux[] = {
-	SSI_SCK34_MARK, SSI_WS34_MARK,
-};
-static const unsigned int ssi4_data_pins[] = {
-	/* SDATA4 */
-	RCAR_GP_PIN(5, 9),
-};
-static const unsigned int ssi4_data_mux[] = {
-	SSI_SDATA4_MARK,
-};
-static const unsigned int ssi4_ctrl_pins[] = {
-	/* SCK4, WS4 */
-	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
-};
-static const unsigned int ssi4_ctrl_mux[] = {
-	SSI_SCK4_MARK, SSI_WS4_MARK,
-};
-static const unsigned int ssi4_data_b_pins[] = {
-	/* SDATA4 */
-	RCAR_GP_PIN(4, 22),
-};
-static const unsigned int ssi4_data_b_mux[] = {
-	SSI_SDATA4_B_MARK,
-};
-static const unsigned int ssi4_ctrl_b_pins[] = {
-	/* SCK4, WS4 */
-	RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
-};
-static const unsigned int ssi4_ctrl_b_mux[] = {
-	SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
-};
-static const unsigned int ssi5_data_pins[] = {
-	/* SDATA5 */
-	RCAR_GP_PIN(4, 26),
-};
-static const unsigned int ssi5_data_mux[] = {
-	SSI_SDATA5_MARK,
-};
-static const unsigned int ssi5_ctrl_pins[] = {
-	/* SCK5, WS5 */
-	RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
-};
-static const unsigned int ssi5_ctrl_mux[] = {
-	SSI_SCK5_MARK, SSI_WS5_MARK,
-};
-static const unsigned int ssi5_data_b_pins[] = {
-	/* SDATA5 */
-	RCAR_GP_PIN(3, 21),
-};
-static const unsigned int ssi5_data_b_mux[] = {
-	SSI_SDATA5_B_MARK,
-};
-static const unsigned int ssi5_ctrl_b_pins[] = {
-	/* SCK5, WS5 */
-	RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
-};
-static const unsigned int ssi5_ctrl_b_mux[] = {
-	SSI_SCK5_B_MARK, SSI_WS5_B_MARK,
-};
-static const unsigned int ssi6_data_pins[] = {
-	/* SDATA6 */
-	RCAR_GP_PIN(4, 29),
-};
-static const unsigned int ssi6_data_mux[] = {
-	SSI_SDATA6_MARK,
-};
-static const unsigned int ssi6_ctrl_pins[] = {
-	/* SCK6, WS6 */
-	RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
-};
-static const unsigned int ssi6_ctrl_mux[] = {
-	SSI_SCK6_MARK, SSI_WS6_MARK,
-};
-static const unsigned int ssi6_data_b_pins[] = {
-	/* SDATA6 */
-	RCAR_GP_PIN(3, 24),
-};
-static const unsigned int ssi6_data_b_mux[] = {
-	SSI_SDATA6_B_MARK,
-};
-static const unsigned int ssi6_ctrl_b_pins[] = {
-	/* SCK6, WS6 */
-	RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
-};
-static const unsigned int ssi6_ctrl_b_mux[] = {
-	SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
-};
-static const unsigned int ssi7_data_pins[] = {
-	/* SDATA7 */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int ssi7_data_mux[] = {
-	SSI_SDATA7_MARK,
-};
-static const unsigned int ssi78_ctrl_pins[] = {
-	/* SCK78, WS78 */
-	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 31),
-};
-static const unsigned int ssi78_ctrl_mux[] = {
-	SSI_SCK78_MARK, SSI_WS78_MARK,
-};
-static const unsigned int ssi7_data_b_pins[] = {
-	/* SDATA7 */
-	RCAR_GP_PIN(3, 27),
-};
-static const unsigned int ssi7_data_b_mux[] = {
-	SSI_SDATA7_B_MARK,
-};
-static const unsigned int ssi78_ctrl_b_pins[] = {
-	/* SCK78, WS78 */
-	RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
-};
-static const unsigned int ssi78_ctrl_b_mux[] = {
-	SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
-};
-static const unsigned int ssi8_data_pins[] = {
-	/* SDATA8 */
-	RCAR_GP_PIN(5, 10),
-};
-static const unsigned int ssi8_data_mux[] = {
-	SSI_SDATA8_MARK,
-};
-static const unsigned int ssi8_data_b_pins[] = {
-	/* SDATA8 */
-	RCAR_GP_PIN(3, 28),
-};
-static const unsigned int ssi8_data_b_mux[] = {
-	SSI_SDATA8_B_MARK,
-};
-static const unsigned int ssi9_data_pins[] = {
-	/* SDATA9 */
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int ssi9_data_mux[] = {
-	SSI_SDATA9_MARK,
-};
-static const unsigned int ssi9_ctrl_pins[] = {
-	/* SCK9, WS9 */
-	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
-};
-static const unsigned int ssi9_ctrl_mux[] = {
-	SSI_SCK9_MARK, SSI_WS9_MARK,
-};
-static const unsigned int ssi9_data_b_pins[] = {
-	/* SDATA9 */
-	RCAR_GP_PIN(4, 19),
-};
-static const unsigned int ssi9_data_b_mux[] = {
-	SSI_SDATA9_B_MARK,
-};
-static const unsigned int ssi9_ctrl_b_pins[] = {
-	/* SCK9, WS9 */
-	RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
-};
-static const unsigned int ssi9_ctrl_b_mux[] = {
-	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
-};
-/* - TPU -------------------------------------------------------------------- */
-static const unsigned int tpu_to0_pins[] = {
-	RCAR_GP_PIN(3, 31),
-};
-static const unsigned int tpu_to0_mux[] = {
-	TPUTO0_MARK,
-};
-static const unsigned int tpu_to0_b_pins[] = {
-	RCAR_GP_PIN(3, 30),
-};
-static const unsigned int tpu_to0_b_mux[] = {
-	TPUTO0_B_MARK,
-};
-static const unsigned int tpu_to0_c_pins[] = {
-	RCAR_GP_PIN(1, 18),
-};
-static const unsigned int tpu_to0_c_mux[] = {
-	TPUTO0_C_MARK,
-};
-static const unsigned int tpu_to1_pins[] = {
-	RCAR_GP_PIN(4, 9),
-};
-static const unsigned int tpu_to1_mux[] = {
-	TPUTO1_MARK,
-};
-static const unsigned int tpu_to1_b_pins[] = {
-	RCAR_GP_PIN(4, 0),
-};
-static const unsigned int tpu_to1_b_mux[] = {
-	TPUTO1_B_MARK,
-};
-static const unsigned int tpu_to1_c_pins[] = {
-	RCAR_GP_PIN(4, 4),
-};
-static const unsigned int tpu_to1_c_mux[] = {
-	TPUTO1_C_MARK,
-};
-static const unsigned int tpu_to2_pins[] = {
-	RCAR_GP_PIN(1, 3),
-};
-static const unsigned int tpu_to2_mux[] = {
-	TPUTO2_MARK,
-};
-static const unsigned int tpu_to2_b_pins[] = {
-	RCAR_GP_PIN(1, 0),
-};
-static const unsigned int tpu_to2_b_mux[] = {
-	TPUTO2_B_MARK,
-};
-static const unsigned int tpu_to2_c_pins[] = {
-	RCAR_GP_PIN(0, 22),
-};
-static const unsigned int tpu_to2_c_mux[] = {
-	TPUTO2_C_MARK,
-};
-static const unsigned int tpu_to3_pins[] = {
-	RCAR_GP_PIN(1, 14),
-};
-static const unsigned int tpu_to3_mux[] = {
-	TPUTO3_MARK,
-};
-static const unsigned int tpu_to3_b_pins[] = {
-	RCAR_GP_PIN(1, 13),
-};
-static const unsigned int tpu_to3_b_mux[] = {
-	TPUTO3_B_MARK,
-};
-static const unsigned int tpu_to3_c_pins[] = {
-	RCAR_GP_PIN(0, 21),
-};
-static const unsigned int tpu_to3_c_mux[] = {
-	TPUTO3_C_MARK,
-};
-/* - USB0 ------------------------------------------------------------------- */
-static const unsigned int usb0_pins[] = {
-	RCAR_GP_PIN(5, 24), /* PWEN */
-	RCAR_GP_PIN(5, 25), /* OVC */
-};
-static const unsigned int usb0_mux[] = {
-	USB0_PWEN_MARK,
-	USB0_OVC_MARK,
-};
-/* - USB1 ------------------------------------------------------------------- */
-static const unsigned int usb1_pins[] = {
-	RCAR_GP_PIN(5, 26), /* PWEN */
-	RCAR_GP_PIN(5, 27), /* OVC */
-};
-static const unsigned int usb1_mux[] = {
-	USB1_PWEN_MARK,
-	USB1_OVC_MARK,
-};
-/* - VIN0 ------------------------------------------------------------------- */
-static const union vin_data vin0_data_pins = {
-	.data24 = {
-		/* B */
-		RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
-		RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
-		RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
-		RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
-		/* G */
-		RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
-		RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
-		RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
-		RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
-		/* R */
-		RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
-		RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
-		RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
-		RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
-	},
-};
-static const union vin_data vin0_data_mux = {
-	.data24 = {
-		/* B */
-		VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
-		VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
-		VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
-		VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
-		/* G */
-		VI0_G0_MARK, VI0_G1_MARK,
-		VI0_G2_MARK, VI0_G3_MARK,
-		VI0_G4_MARK, VI0_G5_MARK,
-		VI0_G6_MARK, VI0_G7_MARK,
-		/* R */
-		VI0_R0_MARK, VI0_R1_MARK,
-		VI0_R2_MARK, VI0_R3_MARK,
-		VI0_R4_MARK, VI0_R5_MARK,
-		VI0_R6_MARK, VI0_R7_MARK,
-	},
-};
-static const unsigned int vin0_data18_pins[] = {
-	/* B */
-	RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
-	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
-	RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
-	/* G */
-	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
-	RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
-	RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
-	/* R */
-	RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
-	RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
-	RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
-};
-static const unsigned int vin0_data18_mux[] = {
-	/* B */
-	VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
-	VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
-	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
-	/* G */
-	VI0_G2_MARK, VI0_G3_MARK,
-	VI0_G4_MARK, VI0_G5_MARK,
-	VI0_G6_MARK, VI0_G7_MARK,
-	/* R */
-	VI0_R2_MARK, VI0_R3_MARK,
-	VI0_R4_MARK, VI0_R5_MARK,
-	VI0_R6_MARK, VI0_R7_MARK,
-};
-static const unsigned int vin0_sync_pins[] = {
-	RCAR_GP_PIN(3, 11), /* HSYNC */
-	RCAR_GP_PIN(3, 12), /* VSYNC */
-};
-static const unsigned int vin0_sync_mux[] = {
-	VI0_HSYNC_N_MARK,
-	VI0_VSYNC_N_MARK,
-};
-static const unsigned int vin0_field_pins[] = {
-	RCAR_GP_PIN(3, 10),
-};
-static const unsigned int vin0_field_mux[] = {
-	VI0_FIELD_MARK,
-};
-static const unsigned int vin0_clkenb_pins[] = {
-	RCAR_GP_PIN(3, 9),
-};
-static const unsigned int vin0_clkenb_mux[] = {
-	VI0_CLKENB_MARK,
-};
-static const unsigned int vin0_clk_pins[] = {
-	RCAR_GP_PIN(3, 0),
-};
-static const unsigned int vin0_clk_mux[] = {
-	VI0_CLK_MARK,
-};
-/* - VIN1 ------------------------------------------------------------------- */
-static const union vin_data12 vin1_data_pins = {
-	.data12 = {
-		RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
-		RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
-		RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
-		RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
-		RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
-		RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-	},
-};
-static const union vin_data12 vin1_data_mux = {
-	.data12 = {
-		VI1_DATA0_MARK, VI1_DATA1_MARK,
-		VI1_DATA2_MARK, VI1_DATA3_MARK,
-		VI1_DATA4_MARK, VI1_DATA5_MARK,
-		VI1_DATA6_MARK, VI1_DATA7_MARK,
-		VI1_DATA8_MARK, VI1_DATA9_MARK,
-		VI1_DATA10_MARK, VI1_DATA11_MARK,
-	},
-};
-static const unsigned int vin1_sync_pins[] = {
-	RCAR_GP_PIN(5, 22), /* HSYNC */
-	RCAR_GP_PIN(5, 23), /* VSYNC */
-};
-static const unsigned int vin1_sync_mux[] = {
-	VI1_HSYNC_N_MARK,
-	VI1_VSYNC_N_MARK,
-};
-static const unsigned int vin1_field_pins[] = {
-	RCAR_GP_PIN(5, 21),
-};
-static const unsigned int vin1_field_mux[] = {
-	VI1_FIELD_MARK,
-};
-static const unsigned int vin1_clkenb_pins[] = {
-	RCAR_GP_PIN(5, 20),
-};
-static const unsigned int vin1_clkenb_mux[] = {
-	VI1_CLKENB_MARK,
-};
-static const unsigned int vin1_clk_pins[] = {
-	RCAR_GP_PIN(5, 11),
-};
-static const unsigned int vin1_clk_mux[] = {
-	VI1_CLK_MARK,
-};
-
-static const struct sh_pfc_pin_group pinmux_groups[] = {
-	SH_PFC_PIN_GROUP(audio_clka),
-	SH_PFC_PIN_GROUP(audio_clka_b),
-	SH_PFC_PIN_GROUP(audio_clka_c),
-	SH_PFC_PIN_GROUP(audio_clka_d),
-	SH_PFC_PIN_GROUP(audio_clkb),
-	SH_PFC_PIN_GROUP(audio_clkb_b),
-	SH_PFC_PIN_GROUP(audio_clkb_c),
-	SH_PFC_PIN_GROUP(audio_clkc),
-	SH_PFC_PIN_GROUP(audio_clkc_b),
-	SH_PFC_PIN_GROUP(audio_clkc_c),
-	SH_PFC_PIN_GROUP(audio_clkout),
-	SH_PFC_PIN_GROUP(audio_clkout_b),
-	SH_PFC_PIN_GROUP(audio_clkout_c),
-	SH_PFC_PIN_GROUP(avb_link),
-	SH_PFC_PIN_GROUP(avb_magic),
-	SH_PFC_PIN_GROUP(avb_phy_int),
-	SH_PFC_PIN_GROUP(avb_mdio),
-	SH_PFC_PIN_GROUP(avb_mii),
-	SH_PFC_PIN_GROUP(avb_gmii),
-	SH_PFC_PIN_GROUP(can0_data),
-	SH_PFC_PIN_GROUP(can0_data_b),
-	SH_PFC_PIN_GROUP(can0_data_c),
-	SH_PFC_PIN_GROUP(can0_data_d),
-	SH_PFC_PIN_GROUP(can1_data),
-	SH_PFC_PIN_GROUP(can1_data_b),
-	SH_PFC_PIN_GROUP(can1_data_c),
-	SH_PFC_PIN_GROUP(can1_data_d),
-	SH_PFC_PIN_GROUP(can_clk),
-	SH_PFC_PIN_GROUP(can_clk_b),
-	SH_PFC_PIN_GROUP(can_clk_c),
-	SH_PFC_PIN_GROUP(can_clk_d),
-	SH_PFC_PIN_GROUP(du0_rgb666),
-	SH_PFC_PIN_GROUP(du0_rgb888),
-	SH_PFC_PIN_GROUP(du0_clk0_out),
-	SH_PFC_PIN_GROUP(du0_clk1_out),
-	SH_PFC_PIN_GROUP(du0_clk_in),
-	SH_PFC_PIN_GROUP(du0_sync),
-	SH_PFC_PIN_GROUP(du0_oddf),
-	SH_PFC_PIN_GROUP(du0_cde),
-	SH_PFC_PIN_GROUP(du0_disp),
-	SH_PFC_PIN_GROUP(du1_rgb666),
-	SH_PFC_PIN_GROUP(du1_rgb888),
-	SH_PFC_PIN_GROUP(du1_clk0_out),
-	SH_PFC_PIN_GROUP(du1_clk1_out),
-	SH_PFC_PIN_GROUP(du1_clk_in),
-	SH_PFC_PIN_GROUP(du1_sync),
-	SH_PFC_PIN_GROUP(du1_oddf),
-	SH_PFC_PIN_GROUP(du1_cde),
-	SH_PFC_PIN_GROUP(du1_disp),
-	SH_PFC_PIN_GROUP(eth_link),
-	SH_PFC_PIN_GROUP(eth_magic),
-	SH_PFC_PIN_GROUP(eth_mdio),
-	SH_PFC_PIN_GROUP(eth_rmii),
-	SH_PFC_PIN_GROUP(eth_link_b),
-	SH_PFC_PIN_GROUP(eth_magic_b),
-	SH_PFC_PIN_GROUP(eth_mdio_b),
-	SH_PFC_PIN_GROUP(eth_rmii_b),
-	SH_PFC_PIN_GROUP(hscif0_data),
-	SH_PFC_PIN_GROUP(hscif0_clk),
-	SH_PFC_PIN_GROUP(hscif0_ctrl),
-	SH_PFC_PIN_GROUP(hscif0_data_b),
-	SH_PFC_PIN_GROUP(hscif0_clk_b),
-	SH_PFC_PIN_GROUP(hscif1_data),
-	SH_PFC_PIN_GROUP(hscif1_clk),
-	SH_PFC_PIN_GROUP(hscif1_ctrl),
-	SH_PFC_PIN_GROUP(hscif1_data_b),
-	SH_PFC_PIN_GROUP(hscif1_ctrl_b),
-	SH_PFC_PIN_GROUP(hscif2_data),
-	SH_PFC_PIN_GROUP(hscif2_clk),
-	SH_PFC_PIN_GROUP(hscif2_ctrl),
-	SH_PFC_PIN_GROUP(i2c0),
-	SH_PFC_PIN_GROUP(i2c0_b),
-	SH_PFC_PIN_GROUP(i2c0_c),
-	SH_PFC_PIN_GROUP(i2c0_d),
-	SH_PFC_PIN_GROUP(i2c0_e),
-	SH_PFC_PIN_GROUP(i2c1),
-	SH_PFC_PIN_GROUP(i2c1_b),
-	SH_PFC_PIN_GROUP(i2c1_c),
-	SH_PFC_PIN_GROUP(i2c1_d),
-	SH_PFC_PIN_GROUP(i2c1_e),
-	SH_PFC_PIN_GROUP(i2c2),
-	SH_PFC_PIN_GROUP(i2c2_b),
-	SH_PFC_PIN_GROUP(i2c2_c),
-	SH_PFC_PIN_GROUP(i2c2_d),
-	SH_PFC_PIN_GROUP(i2c2_e),
-	SH_PFC_PIN_GROUP(i2c3),
-	SH_PFC_PIN_GROUP(i2c3_b),
-	SH_PFC_PIN_GROUP(i2c3_c),
-	SH_PFC_PIN_GROUP(i2c3_d),
-	SH_PFC_PIN_GROUP(i2c3_e),
-	SH_PFC_PIN_GROUP(i2c4),
-	SH_PFC_PIN_GROUP(i2c4_b),
-	SH_PFC_PIN_GROUP(i2c4_c),
-	SH_PFC_PIN_GROUP(i2c4_d),
-	SH_PFC_PIN_GROUP(i2c4_e),
-	SH_PFC_PIN_GROUP(i2c5),
-	SH_PFC_PIN_GROUP(i2c5_b),
-	SH_PFC_PIN_GROUP(i2c5_c),
-	SH_PFC_PIN_GROUP(i2c5_d),
-	SH_PFC_PIN_GROUP(intc_irq0),
-	SH_PFC_PIN_GROUP(intc_irq1),
-	SH_PFC_PIN_GROUP(intc_irq2),
-	SH_PFC_PIN_GROUP(intc_irq3),
-	SH_PFC_PIN_GROUP(intc_irq4),
-	SH_PFC_PIN_GROUP(intc_irq5),
-	SH_PFC_PIN_GROUP(intc_irq6),
-	SH_PFC_PIN_GROUP(intc_irq7),
-	SH_PFC_PIN_GROUP(intc_irq8),
-	SH_PFC_PIN_GROUP(intc_irq9),
-	SH_PFC_PIN_GROUP(mmc_data1),
-	SH_PFC_PIN_GROUP(mmc_data4),
-	SH_PFC_PIN_GROUP(mmc_data8),
-	SH_PFC_PIN_GROUP(mmc_ctrl),
-	SH_PFC_PIN_GROUP(msiof0_clk),
-	SH_PFC_PIN_GROUP(msiof0_sync),
-	SH_PFC_PIN_GROUP(msiof0_ss1),
-	SH_PFC_PIN_GROUP(msiof0_ss2),
-	SH_PFC_PIN_GROUP(msiof0_rx),
-	SH_PFC_PIN_GROUP(msiof0_tx),
-	SH_PFC_PIN_GROUP(msiof1_clk),
-	SH_PFC_PIN_GROUP(msiof1_sync),
-	SH_PFC_PIN_GROUP(msiof1_ss1),
-	SH_PFC_PIN_GROUP(msiof1_ss2),
-	SH_PFC_PIN_GROUP(msiof1_rx),
-	SH_PFC_PIN_GROUP(msiof1_tx),
-	SH_PFC_PIN_GROUP(msiof1_clk_b),
-	SH_PFC_PIN_GROUP(msiof1_sync_b),
-	SH_PFC_PIN_GROUP(msiof1_ss1_b),
-	SH_PFC_PIN_GROUP(msiof1_ss2_b),
-	SH_PFC_PIN_GROUP(msiof1_rx_b),
-	SH_PFC_PIN_GROUP(msiof1_tx_b),
-	SH_PFC_PIN_GROUP(msiof2_clk),
-	SH_PFC_PIN_GROUP(msiof2_sync),
-	SH_PFC_PIN_GROUP(msiof2_ss1),
-	SH_PFC_PIN_GROUP(msiof2_ss2),
-	SH_PFC_PIN_GROUP(msiof2_rx),
-	SH_PFC_PIN_GROUP(msiof2_tx),
-	SH_PFC_PIN_GROUP(msiof2_clk_b),
-	SH_PFC_PIN_GROUP(msiof2_sync_b),
-	SH_PFC_PIN_GROUP(msiof2_ss1_b),
-	SH_PFC_PIN_GROUP(msiof2_ss2_b),
-	SH_PFC_PIN_GROUP(msiof2_rx_b),
-	SH_PFC_PIN_GROUP(msiof2_tx_b),
-	SH_PFC_PIN_GROUP(pwm0),
-	SH_PFC_PIN_GROUP(pwm0_b),
-	SH_PFC_PIN_GROUP(pwm1),
-	SH_PFC_PIN_GROUP(pwm1_b),
-	SH_PFC_PIN_GROUP(pwm1_c),
-	SH_PFC_PIN_GROUP(pwm2),
-	SH_PFC_PIN_GROUP(pwm2_b),
-	SH_PFC_PIN_GROUP(pwm2_c),
-	SH_PFC_PIN_GROUP(pwm3),
-	SH_PFC_PIN_GROUP(pwm3_b),
-	SH_PFC_PIN_GROUP(pwm4),
-	SH_PFC_PIN_GROUP(pwm4_b),
-	SH_PFC_PIN_GROUP(pwm5),
-	SH_PFC_PIN_GROUP(pwm5_b),
-	SH_PFC_PIN_GROUP(pwm5_c),
-	SH_PFC_PIN_GROUP(pwm6),
-	SH_PFC_PIN_GROUP(pwm6_b),
-	SH_PFC_PIN_GROUP(qspi_ctrl),
-	SH_PFC_PIN_GROUP(qspi_data2),
-	SH_PFC_PIN_GROUP(qspi_data4),
-	SH_PFC_PIN_GROUP(scif0_data),
-	SH_PFC_PIN_GROUP(scif0_data_b),
-	SH_PFC_PIN_GROUP(scif0_data_c),
-	SH_PFC_PIN_GROUP(scif0_data_d),
-	SH_PFC_PIN_GROUP(scif1_data),
-	SH_PFC_PIN_GROUP(scif1_clk),
-	SH_PFC_PIN_GROUP(scif1_data_b),
-	SH_PFC_PIN_GROUP(scif1_clk_b),
-	SH_PFC_PIN_GROUP(scif1_data_c),
-	SH_PFC_PIN_GROUP(scif1_clk_c),
-	SH_PFC_PIN_GROUP(scif2_data),
-	SH_PFC_PIN_GROUP(scif2_clk),
-	SH_PFC_PIN_GROUP(scif2_data_b),
-	SH_PFC_PIN_GROUP(scif2_clk_b),
-	SH_PFC_PIN_GROUP(scif2_data_c),
-	SH_PFC_PIN_GROUP(scif2_clk_c),
-	SH_PFC_PIN_GROUP(scif3_data),
-	SH_PFC_PIN_GROUP(scif3_clk),
-	SH_PFC_PIN_GROUP(scif3_data_b),
-	SH_PFC_PIN_GROUP(scif3_clk_b),
-	SH_PFC_PIN_GROUP(scif4_data),
-	SH_PFC_PIN_GROUP(scif4_data_b),
-	SH_PFC_PIN_GROUP(scif4_data_c),
-	SH_PFC_PIN_GROUP(scif4_data_d),
-	SH_PFC_PIN_GROUP(scif4_data_e),
-	SH_PFC_PIN_GROUP(scif5_data),
-	SH_PFC_PIN_GROUP(scif5_data_b),
-	SH_PFC_PIN_GROUP(scif5_data_c),
-	SH_PFC_PIN_GROUP(scif5_data_d),
-	SH_PFC_PIN_GROUP(scifa0_data),
-	SH_PFC_PIN_GROUP(scifa0_data_b),
-	SH_PFC_PIN_GROUP(scifa0_data_c),
-	SH_PFC_PIN_GROUP(scifa0_data_d),
-	SH_PFC_PIN_GROUP(scifa1_data),
-	SH_PFC_PIN_GROUP(scifa1_clk),
-	SH_PFC_PIN_GROUP(scifa1_data_b),
-	SH_PFC_PIN_GROUP(scifa1_clk_b),
-	SH_PFC_PIN_GROUP(scifa1_data_c),
-	SH_PFC_PIN_GROUP(scifa1_clk_c),
-	SH_PFC_PIN_GROUP(scifa2_data),
-	SH_PFC_PIN_GROUP(scifa2_clk),
-	SH_PFC_PIN_GROUP(scifa2_data_b),
-	SH_PFC_PIN_GROUP(scifa2_clk_b),
-	SH_PFC_PIN_GROUP(scifa3_data),
-	SH_PFC_PIN_GROUP(scifa3_clk),
-	SH_PFC_PIN_GROUP(scifa3_data_b),
-	SH_PFC_PIN_GROUP(scifa3_clk_b),
-	SH_PFC_PIN_GROUP(scifa4_data),
-	SH_PFC_PIN_GROUP(scifa4_data_b),
-	SH_PFC_PIN_GROUP(scifa4_data_c),
-	SH_PFC_PIN_GROUP(scifa4_data_d),
-	SH_PFC_PIN_GROUP(scifa5_data),
-	SH_PFC_PIN_GROUP(scifa5_data_b),
-	SH_PFC_PIN_GROUP(scifa5_data_c),
-	SH_PFC_PIN_GROUP(scifa5_data_d),
-	SH_PFC_PIN_GROUP(scifb0_data),
-	SH_PFC_PIN_GROUP(scifb0_clk),
-	SH_PFC_PIN_GROUP(scifb0_ctrl),
-	SH_PFC_PIN_GROUP(scifb1_data),
-	SH_PFC_PIN_GROUP(scifb1_clk),
-	SH_PFC_PIN_GROUP(scifb2_data),
-	SH_PFC_PIN_GROUP(scifb2_clk),
-	SH_PFC_PIN_GROUP(scifb2_ctrl),
-	SH_PFC_PIN_GROUP(scif_clk),
-	SH_PFC_PIN_GROUP(scif_clk_b),
-	SH_PFC_PIN_GROUP(sdhi0_data1),
-	SH_PFC_PIN_GROUP(sdhi0_data4),
-	SH_PFC_PIN_GROUP(sdhi0_ctrl),
-	SH_PFC_PIN_GROUP(sdhi0_cd),
-	SH_PFC_PIN_GROUP(sdhi0_wp),
-	SH_PFC_PIN_GROUP(sdhi1_data1),
-	SH_PFC_PIN_GROUP(sdhi1_data4),
-	SH_PFC_PIN_GROUP(sdhi1_ctrl),
-	SH_PFC_PIN_GROUP(sdhi1_cd),
-	SH_PFC_PIN_GROUP(sdhi1_wp),
-	SH_PFC_PIN_GROUP(sdhi2_data1),
-	SH_PFC_PIN_GROUP(sdhi2_data4),
-	SH_PFC_PIN_GROUP(sdhi2_ctrl),
-	SH_PFC_PIN_GROUP(sdhi2_cd),
-	SH_PFC_PIN_GROUP(sdhi2_wp),
-	SH_PFC_PIN_GROUP(ssi0_data),
-	SH_PFC_PIN_GROUP(ssi0129_ctrl),
-	SH_PFC_PIN_GROUP(ssi1_data),
-	SH_PFC_PIN_GROUP(ssi1_ctrl),
-	SH_PFC_PIN_GROUP(ssi1_data_b),
-	SH_PFC_PIN_GROUP(ssi1_ctrl_b),
-	SH_PFC_PIN_GROUP(ssi2_data),
-	SH_PFC_PIN_GROUP(ssi2_ctrl),
-	SH_PFC_PIN_GROUP(ssi2_data_b),
-	SH_PFC_PIN_GROUP(ssi2_ctrl_b),
-	SH_PFC_PIN_GROUP(ssi3_data),
-	SH_PFC_PIN_GROUP(ssi34_ctrl),
-	SH_PFC_PIN_GROUP(ssi4_data),
-	SH_PFC_PIN_GROUP(ssi4_ctrl),
-	SH_PFC_PIN_GROUP(ssi4_data_b),
-	SH_PFC_PIN_GROUP(ssi4_ctrl_b),
-	SH_PFC_PIN_GROUP(ssi5_data),
-	SH_PFC_PIN_GROUP(ssi5_ctrl),
-	SH_PFC_PIN_GROUP(ssi5_data_b),
-	SH_PFC_PIN_GROUP(ssi5_ctrl_b),
-	SH_PFC_PIN_GROUP(ssi6_data),
-	SH_PFC_PIN_GROUP(ssi6_ctrl),
-	SH_PFC_PIN_GROUP(ssi6_data_b),
-	SH_PFC_PIN_GROUP(ssi6_ctrl_b),
-	SH_PFC_PIN_GROUP(ssi7_data),
-	SH_PFC_PIN_GROUP(ssi78_ctrl),
-	SH_PFC_PIN_GROUP(ssi7_data_b),
-	SH_PFC_PIN_GROUP(ssi78_ctrl_b),
-	SH_PFC_PIN_GROUP(ssi8_data),
-	SH_PFC_PIN_GROUP(ssi8_data_b),
-	SH_PFC_PIN_GROUP(ssi9_data),
-	SH_PFC_PIN_GROUP(ssi9_ctrl),
-	SH_PFC_PIN_GROUP(ssi9_data_b),
-	SH_PFC_PIN_GROUP(ssi9_ctrl_b),
-	SH_PFC_PIN_GROUP(tpu_to0),
-	SH_PFC_PIN_GROUP(tpu_to0_b),
-	SH_PFC_PIN_GROUP(tpu_to0_c),
-	SH_PFC_PIN_GROUP(tpu_to1),
-	SH_PFC_PIN_GROUP(tpu_to1_b),
-	SH_PFC_PIN_GROUP(tpu_to1_c),
-	SH_PFC_PIN_GROUP(tpu_to2),
-	SH_PFC_PIN_GROUP(tpu_to2_b),
-	SH_PFC_PIN_GROUP(tpu_to2_c),
-	SH_PFC_PIN_GROUP(tpu_to3),
-	SH_PFC_PIN_GROUP(tpu_to3_b),
-	SH_PFC_PIN_GROUP(tpu_to3_c),
-	SH_PFC_PIN_GROUP(usb0),
-	SH_PFC_PIN_GROUP(usb1),
-	VIN_DATA_PIN_GROUP(vin0_data, 24),
-	VIN_DATA_PIN_GROUP(vin0_data, 20),
-	SH_PFC_PIN_GROUP(vin0_data18),
-	VIN_DATA_PIN_GROUP(vin0_data, 16),
-	VIN_DATA_PIN_GROUP(vin0_data, 12),
-	VIN_DATA_PIN_GROUP(vin0_data, 10),
-	VIN_DATA_PIN_GROUP(vin0_data, 8),
-	SH_PFC_PIN_GROUP(vin0_sync),
-	SH_PFC_PIN_GROUP(vin0_field),
-	SH_PFC_PIN_GROUP(vin0_clkenb),
-	SH_PFC_PIN_GROUP(vin0_clk),
-	VIN_DATA_PIN_GROUP(vin1_data, 12),
-	VIN_DATA_PIN_GROUP(vin1_data, 10),
-	VIN_DATA_PIN_GROUP(vin1_data, 8),
-	SH_PFC_PIN_GROUP(vin1_sync),
-	SH_PFC_PIN_GROUP(vin1_field),
-	SH_PFC_PIN_GROUP(vin1_clkenb),
-	SH_PFC_PIN_GROUP(vin1_clk),
-};
-
-static const char * const audio_clk_groups[] = {
-	"audio_clka",
-	"audio_clka_b",
-	"audio_clka_c",
-	"audio_clka_d",
-	"audio_clkb",
-	"audio_clkb_b",
-	"audio_clkb_c",
-	"audio_clkc",
-	"audio_clkc_b",
-	"audio_clkc_c",
-	"audio_clkout",
-	"audio_clkout_b",
-	"audio_clkout_c",
-};
-
-static const char * const avb_groups[] = {
-	"avb_link",
-	"avb_magic",
-	"avb_phy_int",
-	"avb_mdio",
-	"avb_mii",
-	"avb_gmii",
-};
-
-static const char * const can0_groups[] = {
-	"can0_data",
-	"can0_data_b",
-	"can0_data_c",
-	"can0_data_d",
-	/*
-	 * Retained for backwards compatibility, use can_clk_groups in new
-	 * designs.
-	 */
-	"can_clk",
-	"can_clk_b",
-	"can_clk_c",
-	"can_clk_d",
-};
-
-static const char * const can1_groups[] = {
-	"can1_data",
-	"can1_data_b",
-	"can1_data_c",
-	"can1_data_d",
-	/*
-	 * Retained for backwards compatibility, use can_clk_groups in new
-	 * designs.
-	 */
-	"can_clk",
-	"can_clk_b",
-	"can_clk_c",
-	"can_clk_d",
-};
-
-/*
- * can_clk_groups allows for independent configuration, use can_clk function
- * in new designs.
- */
-static const char * const can_clk_groups[] = {
-	"can_clk",
-	"can_clk_b",
-	"can_clk_c",
-	"can_clk_d",
-};
-
-static const char * const du0_groups[] = {
-	"du0_rgb666",
-	"du0_rgb888",
-	"du0_clk0_out",
-	"du0_clk1_out",
-	"du0_clk_in",
-	"du0_sync",
-	"du0_oddf",
-	"du0_cde",
-	"du0_disp",
-};
-
-static const char * const du1_groups[] = {
-	"du1_rgb666",
-	"du1_rgb888",
-	"du1_clk0_out",
-	"du1_clk1_out",
-	"du1_clk_in",
-	"du1_sync",
-	"du1_oddf",
-	"du1_cde",
-	"du1_disp",
-};
-
-static const char * const eth_groups[] = {
-	"eth_link",
-	"eth_magic",
-	"eth_mdio",
-	"eth_rmii",
-	"eth_link_b",
-	"eth_magic_b",
-	"eth_mdio_b",
-	"eth_rmii_b",
-};
-
-static const char * const hscif0_groups[] = {
-	"hscif0_data",
-	"hscif0_clk",
-	"hscif0_ctrl",
-	"hscif0_data_b",
-	"hscif0_clk_b",
-};
-
-static const char * const hscif1_groups[] = {
-	"hscif1_data",
-	"hscif1_clk",
-	"hscif1_ctrl",
-	"hscif1_data_b",
-	"hscif1_ctrl_b",
-};
-
-static const char * const hscif2_groups[] = {
-	"hscif2_data",
-	"hscif2_clk",
-	"hscif2_ctrl",
-};
-
-static const char * const i2c0_groups[] = {
-	"i2c0",
-	"i2c0_b",
-	"i2c0_c",
-	"i2c0_d",
-	"i2c0_e",
-};
-
-static const char * const i2c1_groups[] = {
-	"i2c1",
-	"i2c1_b",
-	"i2c1_c",
-	"i2c1_d",
-	"i2c1_e",
-};
-
-static const char * const i2c2_groups[] = {
-	"i2c2",
-	"i2c2_b",
-	"i2c2_c",
-	"i2c2_d",
-	"i2c2_e",
-};
-
-static const char * const i2c3_groups[] = {
-	"i2c3",
-	"i2c3_b",
-	"i2c3_c",
-	"i2c3_d",
-	"i2c3_e",
-};
-
-static const char * const i2c4_groups[] = {
-	"i2c4",
-	"i2c4_b",
-	"i2c4_c",
-	"i2c4_d",
-	"i2c4_e",
-};
-
-static const char * const i2c5_groups[] = {
-	"i2c5",
-	"i2c5_b",
-	"i2c5_c",
-	"i2c5_d",
-};
-
-static const char * const intc_groups[] = {
-	"intc_irq0",
-	"intc_irq1",
-	"intc_irq2",
-	"intc_irq3",
-	"intc_irq4",
-	"intc_irq5",
-	"intc_irq6",
-	"intc_irq7",
-	"intc_irq8",
-	"intc_irq9",
-};
-
-static const char * const mmc_groups[] = {
-	"mmc_data1",
-	"mmc_data4",
-	"mmc_data8",
-	"mmc_ctrl",
-};
-
-static const char * const msiof0_groups[] = {
-	"msiof0_clk",
-	"msiof0_sync",
-	"msiof0_ss1",
-	"msiof0_ss2",
-	"msiof0_rx",
-	"msiof0_tx",
-};
-
-static const char * const msiof1_groups[] = {
-	"msiof1_clk",
-	"msiof1_sync",
-	"msiof1_ss1",
-	"msiof1_ss2",
-	"msiof1_rx",
-	"msiof1_tx",
-	"msiof1_clk_b",
-	"msiof1_sync_b",
-	"msiof1_ss1_b",
-	"msiof1_ss2_b",
-	"msiof1_rx_b",
-	"msiof1_tx_b",
-};
-
-static const char * const msiof2_groups[] = {
-	"msiof2_clk",
-	"msiof2_sync",
-	"msiof2_ss1",
-	"msiof2_ss2",
-	"msiof2_rx",
-	"msiof2_tx",
-	"msiof2_clk_b",
-	"msiof2_sync_b",
-	"msiof2_ss1_b",
-	"msiof2_ss2_b",
-	"msiof2_rx_b",
-	"msiof2_tx_b",
-};
-
-static const char * const pwm0_groups[] = {
-	"pwm0",
-	"pwm0_b",
-};
-
-static const char * const pwm1_groups[] = {
-	"pwm1",
-	"pwm1_b",
-	"pwm1_c",
-};
-
-static const char * const pwm2_groups[] = {
-	"pwm2",
-	"pwm2_b",
-	"pwm2_c",
-};
-
-static const char * const pwm3_groups[] = {
-	"pwm3",
-	"pwm3_b",
-};
-
-static const char * const pwm4_groups[] = {
-	"pwm4",
-	"pwm4_b",
-};
-
-static const char * const pwm5_groups[] = {
-	"pwm5",
-	"pwm5_b",
-	"pwm5_c",
-};
-
-static const char * const pwm6_groups[] = {
-	"pwm6",
-	"pwm6_b",
-};
-
-static const char * const qspi_groups[] = {
-	"qspi_ctrl",
-	"qspi_data2",
-	"qspi_data4",
-};
-
-static const char * const scif0_groups[] = {
-	"scif0_data",
-	"scif0_data_b",
-	"scif0_data_c",
-	"scif0_data_d",
-};
-
-static const char * const scif1_groups[] = {
-	"scif1_data",
-	"scif1_clk",
-	"scif1_data_b",
-	"scif1_clk_b",
-	"scif1_data_c",
-	"scif1_clk_c",
-};
-
-static const char * const scif2_groups[] = {
-	"scif2_data",
-	"scif2_clk",
-	"scif2_data_b",
-	"scif2_clk_b",
-	"scif2_data_c",
-	"scif2_clk_c",
-};
-
-static const char * const scif3_groups[] = {
-	"scif3_data",
-	"scif3_clk",
-	"scif3_data_b",
-	"scif3_clk_b",
-};
-
-static const char * const scif4_groups[] = {
-	"scif4_data",
-	"scif4_data_b",
-	"scif4_data_c",
-	"scif4_data_d",
-	"scif4_data_e",
-};
-
-static const char * const scif5_groups[] = {
-	"scif5_data",
-	"scif5_data_b",
-	"scif5_data_c",
-	"scif5_data_d",
-};
-
-static const char * const scifa0_groups[] = {
-	"scifa0_data",
-	"scifa0_data_b",
-	"scifa0_data_c",
-	"scifa0_data_d",
-};
-
-static const char * const scifa1_groups[] = {
-	"scifa1_data",
-	"scifa1_clk",
-	"scifa1_data_b",
-	"scifa1_clk_b",
-	"scifa1_data_c",
-	"scifa1_clk_c",
-};
-
-static const char * const scifa2_groups[] = {
-	"scifa2_data",
-	"scifa2_clk",
-	"scifa2_data_b",
-	"scifa2_clk_b",
-};
-
-static const char * const scifa3_groups[] = {
-	"scifa3_data",
-	"scifa3_clk",
-	"scifa3_data_b",
-	"scifa3_clk_b",
-};
-
-static const char * const scifa4_groups[] = {
-	"scifa4_data",
-	"scifa4_data_b",
-	"scifa4_data_c",
-	"scifa4_data_d",
-};
-
-static const char * const scifa5_groups[] = {
-	"scifa5_data",
-	"scifa5_data_b",
-	"scifa5_data_c",
-	"scifa5_data_d",
-};
-
-static const char * const scifb0_groups[] = {
-	"scifb0_data",
-	"scifb0_clk",
-	"scifb0_ctrl",
-};
-
-static const char * const scifb1_groups[] = {
-	"scifb1_data",
-	"scifb1_clk",
-};
-
-static const char * const scifb2_groups[] = {
-	"scifb2_data",
-	"scifb2_clk",
-	"scifb2_ctrl",
-};
-
-static const char * const scif_clk_groups[] = {
-	"scif_clk",
-	"scif_clk_b",
-};
-
-static const char * const sdhi0_groups[] = {
-	"sdhi0_data1",
-	"sdhi0_data4",
-	"sdhi0_ctrl",
-	"sdhi0_cd",
-	"sdhi0_wp",
-};
-
-static const char * const sdhi1_groups[] = {
-	"sdhi1_data1",
-	"sdhi1_data4",
-	"sdhi1_ctrl",
-	"sdhi1_cd",
-	"sdhi1_wp",
-};
-
-static const char * const sdhi2_groups[] = {
-	"sdhi2_data1",
-	"sdhi2_data4",
-	"sdhi2_ctrl",
-	"sdhi2_cd",
-	"sdhi2_wp",
-};
-
-static const char * const ssi_groups[] = {
-	"ssi0_data",
-	"ssi0129_ctrl",
-	"ssi1_data",
-	"ssi1_ctrl",
-	"ssi1_data_b",
-	"ssi1_ctrl_b",
-	"ssi2_data",
-	"ssi2_ctrl",
-	"ssi2_data_b",
-	"ssi2_ctrl_b",
-	"ssi3_data",
-	"ssi34_ctrl",
-	"ssi4_data",
-	"ssi4_ctrl",
-	"ssi4_data_b",
-	"ssi4_ctrl_b",
-	"ssi5_data",
-	"ssi5_ctrl",
-	"ssi5_data_b",
-	"ssi5_ctrl_b",
-	"ssi6_data",
-	"ssi6_ctrl",
-	"ssi6_data_b",
-	"ssi6_ctrl_b",
-	"ssi7_data",
-	"ssi78_ctrl",
-	"ssi7_data_b",
-	"ssi78_ctrl_b",
-	"ssi8_data",
-	"ssi8_data_b",
-	"ssi9_data",
-	"ssi9_ctrl",
-	"ssi9_data_b",
-	"ssi9_ctrl_b",
-};
-
-static const char * const tpu_groups[] = {
-	"tpu_to0",
-	"tpu_to0_b",
-	"tpu_to0_c",
-	"tpu_to1",
-	"tpu_to1_b",
-	"tpu_to1_c",
-	"tpu_to2",
-	"tpu_to2_b",
-	"tpu_to2_c",
-	"tpu_to3",
-	"tpu_to3_b",
-	"tpu_to3_c",
-};
-
-static const char * const usb0_groups[] = {
-	"usb0",
-};
-
-static const char * const usb1_groups[] = {
-	"usb1",
-};
-
-static const char * const vin0_groups[] = {
-	"vin0_data24",
-	"vin0_data20",
-	"vin0_data18",
-	"vin0_data16",
-	"vin0_data12",
-	"vin0_data10",
-	"vin0_data8",
-	"vin0_sync",
-	"vin0_field",
-	"vin0_clkenb",
-	"vin0_clk",
-};
-
-static const char * const vin1_groups[] = {
-	"vin1_data12",
-	"vin1_data10",
-	"vin1_data8",
-	"vin1_sync",
-	"vin1_field",
-	"vin1_clkenb",
-	"vin1_clk",
-};
-
-static const struct sh_pfc_function pinmux_functions[] = {
-	SH_PFC_FUNCTION(audio_clk),
-	SH_PFC_FUNCTION(avb),
-	SH_PFC_FUNCTION(can0),
-	SH_PFC_FUNCTION(can1),
-	SH_PFC_FUNCTION(can_clk),
-	SH_PFC_FUNCTION(du0),
-	SH_PFC_FUNCTION(du1),
-	SH_PFC_FUNCTION(eth),
-	SH_PFC_FUNCTION(hscif0),
-	SH_PFC_FUNCTION(hscif1),
-	SH_PFC_FUNCTION(hscif2),
-	SH_PFC_FUNCTION(i2c0),
-	SH_PFC_FUNCTION(i2c1),
-	SH_PFC_FUNCTION(i2c2),
-	SH_PFC_FUNCTION(i2c3),
-	SH_PFC_FUNCTION(i2c4),
-	SH_PFC_FUNCTION(i2c5),
-	SH_PFC_FUNCTION(intc),
-	SH_PFC_FUNCTION(mmc),
-	SH_PFC_FUNCTION(msiof0),
-	SH_PFC_FUNCTION(msiof1),
-	SH_PFC_FUNCTION(msiof2),
-	SH_PFC_FUNCTION(pwm0),
-	SH_PFC_FUNCTION(pwm1),
-	SH_PFC_FUNCTION(pwm2),
-	SH_PFC_FUNCTION(pwm3),
-	SH_PFC_FUNCTION(pwm4),
-	SH_PFC_FUNCTION(pwm5),
-	SH_PFC_FUNCTION(pwm6),
-	SH_PFC_FUNCTION(qspi),
-	SH_PFC_FUNCTION(scif0),
-	SH_PFC_FUNCTION(scif1),
-	SH_PFC_FUNCTION(scif2),
-	SH_PFC_FUNCTION(scif3),
-	SH_PFC_FUNCTION(scif4),
-	SH_PFC_FUNCTION(scif5),
-	SH_PFC_FUNCTION(scifa0),
-	SH_PFC_FUNCTION(scifa1),
-	SH_PFC_FUNCTION(scifa2),
-	SH_PFC_FUNCTION(scifa3),
-	SH_PFC_FUNCTION(scifa4),
-	SH_PFC_FUNCTION(scifa5),
-	SH_PFC_FUNCTION(scifb0),
-	SH_PFC_FUNCTION(scifb1),
-	SH_PFC_FUNCTION(scifb2),
-	SH_PFC_FUNCTION(scif_clk),
-	SH_PFC_FUNCTION(sdhi0),
-	SH_PFC_FUNCTION(sdhi1),
-	SH_PFC_FUNCTION(sdhi2),
-	SH_PFC_FUNCTION(ssi),
-	SH_PFC_FUNCTION(tpu),
-	SH_PFC_FUNCTION(usb0),
-	SH_PFC_FUNCTION(usb1),
-	SH_PFC_FUNCTION(vin0),
-	SH_PFC_FUNCTION(vin1),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
-		GP_0_31_FN, FN_IP2_17_16,
-		GP_0_30_FN, FN_IP2_15_14,
-		GP_0_29_FN, FN_IP2_13_12,
-		GP_0_28_FN, FN_IP2_11_10,
-		GP_0_27_FN, FN_IP2_9_8,
-		GP_0_26_FN, FN_IP2_7_6,
-		GP_0_25_FN, FN_IP2_5_4,
-		GP_0_24_FN, FN_IP2_3_2,
-		GP_0_23_FN, FN_IP2_1_0,
-		GP_0_22_FN, FN_IP1_31_30,
-		GP_0_21_FN, FN_IP1_29_28,
-		GP_0_20_FN, FN_IP1_27,
-		GP_0_19_FN, FN_IP1_26,
-		GP_0_18_FN, FN_A2,
-		GP_0_17_FN, FN_IP1_24,
-		GP_0_16_FN, FN_IP1_23_22,
-		GP_0_15_FN, FN_IP1_21_20,
-		GP_0_14_FN, FN_IP1_19_18,
-		GP_0_13_FN, FN_IP1_17_15,
-		GP_0_12_FN, FN_IP1_14_13,
-		GP_0_11_FN, FN_IP1_12_11,
-		GP_0_10_FN, FN_IP1_10_8,
-		GP_0_9_FN, FN_IP1_7_6,
-		GP_0_8_FN, FN_IP1_5_4,
-		GP_0_7_FN, FN_IP1_3_2,
-		GP_0_6_FN, FN_IP1_1_0,
-		GP_0_5_FN, FN_IP0_31_30,
-		GP_0_4_FN, FN_IP0_29_28,
-		GP_0_3_FN, FN_IP0_27_26,
-		GP_0_2_FN, FN_IP0_25,
-		GP_0_1_FN, FN_IP0_24,
-		GP_0_0_FN, FN_IP0_23_22, ))
-	},
-	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_1_25_FN, FN_DACK0,
-		GP_1_24_FN, FN_IP7_31,
-		GP_1_23_FN, FN_IP4_1_0,
-		GP_1_22_FN, FN_WE1_N,
-		GP_1_21_FN, FN_WE0_N,
-		GP_1_20_FN, FN_IP3_31,
-		GP_1_19_FN, FN_IP3_30,
-		GP_1_18_FN, FN_IP3_29_27,
-		GP_1_17_FN, FN_IP3_26_24,
-		GP_1_16_FN, FN_IP3_23_21,
-		GP_1_15_FN, FN_IP3_20_18,
-		GP_1_14_FN, FN_IP3_17_15,
-		GP_1_13_FN, FN_IP3_14_13,
-		GP_1_12_FN, FN_IP3_12,
-		GP_1_11_FN, FN_IP3_11,
-		GP_1_10_FN, FN_IP3_10,
-		GP_1_9_FN, FN_IP3_9_8,
-		GP_1_8_FN, FN_IP3_7_6,
-		GP_1_7_FN, FN_IP3_5_4,
-		GP_1_6_FN, FN_IP3_3_2,
-		GP_1_5_FN, FN_IP3_1_0,
-		GP_1_4_FN, FN_IP2_31_30,
-		GP_1_3_FN, FN_IP2_29_27,
-		GP_1_2_FN, FN_IP2_26_24,
-		GP_1_1_FN, FN_IP2_23_21,
-		GP_1_0_FN, FN_IP2_20_18, ))
-	},
-	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
-		GP_2_31_FN, FN_IP6_7_6,
-		GP_2_30_FN, FN_IP6_5_4,
-		GP_2_29_FN, FN_IP6_3_2,
-		GP_2_28_FN, FN_IP6_1_0,
-		GP_2_27_FN, FN_IP5_31_30,
-		GP_2_26_FN, FN_IP5_29_28,
-		GP_2_25_FN, FN_IP5_27_26,
-		GP_2_24_FN, FN_IP5_25_24,
-		GP_2_23_FN, FN_IP5_23_22,
-		GP_2_22_FN, FN_IP5_21_20,
-		GP_2_21_FN, FN_IP5_19_18,
-		GP_2_20_FN, FN_IP5_17_16,
-		GP_2_19_FN, FN_IP5_15_14,
-		GP_2_18_FN, FN_IP5_13_12,
-		GP_2_17_FN, FN_IP5_11_9,
-		GP_2_16_FN, FN_IP5_8_6,
-		GP_2_15_FN, FN_IP5_5_4,
-		GP_2_14_FN, FN_IP5_3_2,
-		GP_2_13_FN, FN_IP5_1_0,
-		GP_2_12_FN, FN_IP4_31_30,
-		GP_2_11_FN, FN_IP4_29_28,
-		GP_2_10_FN, FN_IP4_27_26,
-		GP_2_9_FN, FN_IP4_25_23,
-		GP_2_8_FN, FN_IP4_22_20,
-		GP_2_7_FN, FN_IP4_19_18,
-		GP_2_6_FN, FN_IP4_17_16,
-		GP_2_5_FN, FN_IP4_15_14,
-		GP_2_4_FN, FN_IP4_13_12,
-		GP_2_3_FN, FN_IP4_11_10,
-		GP_2_2_FN, FN_IP4_9_8,
-		GP_2_1_FN, FN_IP4_7_5,
-		GP_2_0_FN, FN_IP4_4_2 ))
-	},
-	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
-		GP_3_31_FN, FN_IP8_22_20,
-		GP_3_30_FN, FN_IP8_19_17,
-		GP_3_29_FN, FN_IP8_16_15,
-		GP_3_28_FN, FN_IP8_14_12,
-		GP_3_27_FN, FN_IP8_11_9,
-		GP_3_26_FN, FN_IP8_8_6,
-		GP_3_25_FN, FN_IP8_5_3,
-		GP_3_24_FN, FN_IP8_2_0,
-		GP_3_23_FN, FN_IP7_29_27,
-		GP_3_22_FN, FN_IP7_26_24,
-		GP_3_21_FN, FN_IP7_23_21,
-		GP_3_20_FN, FN_IP7_20_18,
-		GP_3_19_FN, FN_IP7_17_15,
-		GP_3_18_FN, FN_IP7_14_12,
-		GP_3_17_FN, FN_IP7_11_9,
-		GP_3_16_FN, FN_IP7_8_6,
-		GP_3_15_FN, FN_IP7_5_3,
-		GP_3_14_FN, FN_IP7_2_0,
-		GP_3_13_FN, FN_IP6_31_29,
-		GP_3_12_FN, FN_IP6_28_26,
-		GP_3_11_FN, FN_IP6_25_23,
-		GP_3_10_FN, FN_IP6_22_20,
-		GP_3_9_FN, FN_IP6_19_17,
-		GP_3_8_FN, FN_IP6_16,
-		GP_3_7_FN, FN_IP6_15,
-		GP_3_6_FN, FN_IP6_14,
-		GP_3_5_FN, FN_IP6_13,
-		GP_3_4_FN, FN_IP6_12,
-		GP_3_3_FN, FN_IP6_11,
-		GP_3_2_FN, FN_IP6_10,
-		GP_3_1_FN, FN_IP6_9,
-		GP_3_0_FN, FN_IP6_8 ))
-	},
-	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
-		GP_4_31_FN, FN_IP11_17_16,
-		GP_4_30_FN, FN_IP11_15_14,
-		GP_4_29_FN, FN_IP11_13_11,
-		GP_4_28_FN, FN_IP11_10_8,
-		GP_4_27_FN, FN_IP11_7_6,
-		GP_4_26_FN, FN_IP11_5_3,
-		GP_4_25_FN, FN_IP11_2_0,
-		GP_4_24_FN, FN_IP10_31_30,
-		GP_4_23_FN, FN_IP10_29_27,
-		GP_4_22_FN, FN_IP10_26_24,
-		GP_4_21_FN, FN_IP10_23_21,
-		GP_4_20_FN, FN_IP10_20_18,
-		GP_4_19_FN, FN_IP10_17_15,
-		GP_4_18_FN, FN_IP10_14_12,
-		GP_4_17_FN, FN_IP10_11_9,
-		GP_4_16_FN, FN_IP10_8_6,
-		GP_4_15_FN, FN_IP10_5_3,
-		GP_4_14_FN, FN_IP10_2_0,
-		GP_4_13_FN, FN_IP9_30_28,
-		GP_4_12_FN, FN_IP9_27_25,
-		GP_4_11_FN, FN_IP9_24_22,
-		GP_4_10_FN, FN_IP9_21_19,
-		GP_4_9_FN, FN_IP9_18_17,
-		GP_4_8_FN, FN_IP9_16_15,
-		GP_4_7_FN, FN_IP9_14_12,
-		GP_4_6_FN, FN_IP9_11_9,
-		GP_4_5_FN, FN_IP9_8_6,
-		GP_4_4_FN, FN_IP9_5_3,
-		GP_4_3_FN, FN_IP9_2_0,
-		GP_4_2_FN, FN_IP8_31_29,
-		GP_4_1_FN, FN_IP8_28_26,
-		GP_4_0_FN, FN_IP8_25_23 ))
-	},
-	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_5_27_FN, FN_USB1_OVC,
-		GP_5_26_FN, FN_USB1_PWEN,
-		GP_5_25_FN, FN_USB0_OVC,
-		GP_5_24_FN, FN_USB0_PWEN,
-		GP_5_23_FN, FN_IP13_26_24,
-		GP_5_22_FN, FN_IP13_23_21,
-		GP_5_21_FN, FN_IP13_20_18,
-		GP_5_20_FN, FN_IP13_17_15,
-		GP_5_19_FN, FN_IP13_14_12,
-		GP_5_18_FN, FN_IP13_11_9,
-		GP_5_17_FN, FN_IP13_8_6,
-		GP_5_16_FN, FN_IP13_5_3,
-		GP_5_15_FN, FN_IP13_2_0,
-		GP_5_14_FN, FN_IP12_29_27,
-		GP_5_13_FN, FN_IP12_26_24,
-		GP_5_12_FN, FN_IP12_23_21,
-		GP_5_11_FN, FN_IP12_20_18,
-		GP_5_10_FN, FN_IP12_17_15,
-		GP_5_9_FN, FN_IP12_14_13,
-		GP_5_8_FN, FN_IP12_12_11,
-		GP_5_7_FN, FN_IP12_10_9,
-		GP_5_6_FN, FN_IP12_8_6,
-		GP_5_5_FN, FN_IP12_5_3,
-		GP_5_4_FN, FN_IP12_2_0,
-		GP_5_3_FN, FN_IP11_29_27,
-		GP_5_2_FN, FN_IP11_26_24,
-		GP_5_1_FN, FN_IP11_23_21,
-		GP_5_0_FN, FN_IP11_20_18 ))
-	},
-	{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_6_25_FN, FN_IP0_21_20,
-		GP_6_24_FN, FN_IP0_19_18,
-		GP_6_23_FN, FN_IP0_17,
-		GP_6_22_FN, FN_IP0_16,
-		GP_6_21_FN, FN_IP0_15,
-		GP_6_20_FN, FN_IP0_14,
-		GP_6_19_FN, FN_IP0_13,
-		GP_6_18_FN, FN_IP0_12,
-		GP_6_17_FN, FN_IP0_11,
-		GP_6_16_FN, FN_IP0_10,
-		GP_6_15_FN, FN_IP0_9_8,
-		GP_6_14_FN, FN_IP0_0,
-		GP_6_13_FN, FN_SD1_DATA3,
-		GP_6_12_FN, FN_SD1_DATA2,
-		GP_6_11_FN, FN_SD1_DATA1,
-		GP_6_10_FN, FN_SD1_DATA0,
-		GP_6_9_FN, FN_SD1_CMD,
-		GP_6_8_FN, FN_SD1_CLK,
-		GP_6_7_FN, FN_SD0_WP,
-		GP_6_6_FN, FN_SD0_CD,
-		GP_6_5_FN, FN_SD0_DATA3,
-		GP_6_4_FN, FN_SD0_DATA2,
-		GP_6_3_FN, FN_SD0_DATA1,
-		GP_6_2_FN, FN_SD0_DATA0,
-		GP_6_1_FN, FN_SD0_CMD,
-		GP_6_0_FN, FN_SD0_CLK ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
-			     GROUP(2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1,
-				   1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1),
-			     GROUP(
-		/* IP0_31_30 [2] */
-		FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
-		/* IP0_29_28 [2] */
-		FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
-		/* IP0_27_26 [2] */
-		FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
-		/* IP0_25 [1] */
-		FN_D2, FN_SCIFA3_TXD_B,
-		/* IP0_24 [1] */
-		FN_D1, FN_SCIFA3_RXD_B,
-		/* IP0_23_22 [2] */
-		FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
-		/* IP0_21_20 [2] */
-		FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
-		/* IP0_19_18 [2] */
-		FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B,	FN_CAN1_RX,
-		/* IP0_17 [1] */
-		FN_MMC_D5, FN_SD2_WP,
-		/* IP0_16 [1] */
-		FN_MMC_D4, FN_SD2_CD,
-		/* IP0_15 [1] */
-		FN_MMC_D3, FN_SD2_DATA3,
-		/* IP0_14 [1] */
-		FN_MMC_D2, FN_SD2_DATA2,
-		/* IP0_13 [1] */
-		FN_MMC_D1, FN_SD2_DATA1,
-		/* IP0_12 [1] */
-		FN_MMC_D0, FN_SD2_DATA0,
-		/* IP0_11 [1] */
-		FN_MMC_CMD, FN_SD2_CMD,
-		/* IP0_10 [1] */
-		FN_MMC_CLK, FN_SD2_CLK,
-		/* IP0_9_8 [2] */
-		FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
-		/* IP0_7 [1] */
-		0, 0,
-		/* IP0_6 [1] */
-		0, 0,
-		/* IP0_5 [1] */
-		0, 0,
-		/* IP0_4 [1] */
-		0, 0,
-		/* IP0_3 [1] */
-		0, 0,
-		/* IP0_2 [1] */
-		0, 0,
-		/* IP0_1 [1] */
-		0, 0,
-		/* IP0_0 [1] */
-		FN_SD1_CD, FN_CAN0_RX, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
-			     GROUP(2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2,
-				   3, 2, 2, 2, 2),
-			     GROUP(
-		/* IP1_31_30 [2] */
-		FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
-		/* IP1_29_28 [2] */
-		FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
-		/* IP1_27 [1] */
-		FN_A4, FN_SCIFB0_TXD,
-		/* IP1_26 [1] */
-		FN_A3, FN_SCIFB0_SCK,
-		/* IP1_25 [1] */
-		0, 0,
-		/* IP1_24 [1] */
-		FN_A1, FN_SCIFB1_TXD,
-		/* IP1_23_22 [2] */
-		FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0,
-		/* IP1_21_20 [2] */
-		FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, 0,
-		/* IP1_19_18 [2] */
-		FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, 0,
-		/* IP1_17_15 [3] */
-		FN_D13, FN_SCIFA1_SCK, 0, FN_PWM2_C, FN_TCLK2_B,
-		0, 0, 0,
-		/* IP1_14_13 [2] */
-		FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
-		/* IP1_12_11 [2] */
-		FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
-		/* IP1_10_8 [3] */
-		FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
-		0, 0, 0,
-		/* IP1_7_6 [2] */
-		FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0,
-		/* IP1_5_4 [2] */
-		FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0,
-		/* IP1_3_2 [2] */
-		FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
-		/* IP1_1_0 [2] */
-		FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
-			     GROUP(2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2),
-			     GROUP(
-		/* IP2_31_30 [2] */
-		FN_A20, FN_SPCLK, 0, 0,
-		/* IP2_29_27 [3] */
-		FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
-		0, 0, 0, 0,
-		/* IP2_26_24 [3] */
-		FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
-		0, 0, 0, 0,
-		/* IP2_23_21 [3] */
-		FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
-		0, 0, 0, 0,
-		/* IP2_20_18 [3] */
-		FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN,
-		0, FN_CAN_CLK_C, FN_TPUTO2_B, 0,
-		/* IP2_17_16 [2] */
-		FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
-		/* IP2_15_14 [2] */
-		FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
-		/* IP2_13_12 [2] */
-		FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0,
-		/* IP2_11_10 [2] */
-		FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0,
-		/* IP2_9_8 [2] */
-		FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B, 0,
-		/* IP2_7_6 [2] */
-		FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B, 0,
-		/* IP2_5_4 [2] */
-		FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0,
-		/* IP2_3_2 [2] */
-		FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
-		/* IP2_1_0 [2] */
-		FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
-			     GROUP(1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2,
-				   2, 2, 2, 2),
-			     GROUP(
-		/* IP3_31 [1] */
-		FN_RD_WR_N, FN_ATAG1_N,
-		/* IP3_30 [1] */
-		FN_RD_N, FN_ATACS11_N,
-		/* IP3_29_27 [3] */
-		FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
-		0, 0, 0,
-		/* IP3_26_24 [3] */
-		FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B,
-		0, FN_FMIN, FN_SCIFB2_RTS_N, 0,
-		/* IP3_23_21 [3] */
-		FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B,
-		0, FN_FMCLK, FN_SCIFB2_CTS_N, 0,
-		/* IP3_20_18 [3] */
-		FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
-		0, FN_BPFCLK, FN_SCIFB2_SCK, 0,
-		/* IP3_17_15 [3] */
-		FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B,
-		0, FN_TPUTO3, FN_SCIFB2_TXD, 0,
-		/* IP3_14_13 [2] */
-		FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
-		/* IP3_12 [1] */
-		FN_EX_CS0_N, FN_VI1_DATA10,
-		/* IP3_11 [1] */
-		FN_CS1_N_A26, FN_VI1_DATA9,
-		/* IP3_10 [1] */
-		FN_CS0_N, FN_VI1_DATA8,
-		/* IP3_9_8 [2] */
-		FN_A25, FN_SSL, FN_ATARD1_N, 0,
-		/* IP3_7_6 [2] */
-		FN_A24, FN_IO3, FN_EX_WAIT2, 0,
-		/* IP3_5_4 [2] */
-		FN_A23, FN_IO2, 0, FN_ATAWR1_N,
-		/* IP3_3_2 [2] */
-		FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N,
-		/* IP3_1_0 [2] */
-		FN_A21, FN_MOSI_IO0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
-			     GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2),
-			     GROUP(
-		/* IP4_31_30 [2] */
-		FN_DU0_DG4, FN_LCDOUT12, 0, 0,
-		/* IP4_29_28 [2] */
-		FN_DU0_DG3, FN_LCDOUT11, 0, 0,
-		/* IP4_27_26 [2] */
-		FN_DU0_DG2, FN_LCDOUT10, 0, 0,
-		/* IP4_25_23 [3] */
-		FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
-		0, 0, 0, 0,
-		/* IP4_22_20 [3] */
-		FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
-		0, 0, 0, 0,
-		/* IP4_19_18 [2] */
-		FN_DU0_DR7, FN_LCDOUT23, 0, 0,
-		/* IP4_17_16 [2] */
-		FN_DU0_DR6, FN_LCDOUT22, 0, 0,
-		/* IP4_15_14 [2] */
-		FN_DU0_DR5, FN_LCDOUT21, 0, 0,
-		/* IP4_13_12 [2] */
-		FN_DU0_DR4, FN_LCDOUT20, 0, 0,
-		/* IP4_11_10 [2] */
-		FN_DU0_DR3, FN_LCDOUT19, 0, 0,
-		/* IP4_9_8 [2] */
-		FN_DU0_DR2, FN_LCDOUT18, 0, 0,
-		/* IP4_7_5 [3] */
-		FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
-		0, 0, 0, 0,
-		/* IP4_4_2 [3] */
-		FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
-		0, 0, 0, 0,
-		/* IP4_1_0 [2] */
-		FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
-			     GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,
-				   2, 2, 2),
-			     GROUP(
-		/* IP5_31_30 [2] */
-		FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0,
-		/* IP5_29_28 [2] */
-		FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, 0, 0,
-		/* IP5_27_26 [2] */
-		FN_DU0_DOTCLKOUT0, FN_QCLK, 0, 0,
-		/* IP5_25_24 [2] */
-		FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 0, 0,
-		/* IP5_23_22 [2] */
-		FN_DU0_DB7, FN_LCDOUT7, 0, 0,
-		/* IP5_21_20 [2] */
-		FN_DU0_DB6, FN_LCDOUT6, 0, 0,
-		/* IP5_19_18 [2] */
-		FN_DU0_DB5, FN_LCDOUT5, 0, 0,
-		/* IP5_17_16 [2] */
-		FN_DU0_DB4, FN_LCDOUT4, 0, 0,
-		/* IP5_15_14 [2] */
-		FN_DU0_DB3, FN_LCDOUT3, 0, 0,
-		/* IP5_13_12 [2] */
-		FN_DU0_DB2, FN_LCDOUT2, 0, 0,
-		/* IP5_11_9 [3] */
-		FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
-		FN_CAN0_TX_C, 0, 0, 0,
-		/* IP5_8_6 [3] */
-		FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D,
-		FN_CAN0_RX_C, 0, 0, 0,
-		/* IP5_5_4 [2] */
-		FN_DU0_DG7, FN_LCDOUT15, 0, 0,
-		/* IP5_3_2 [2] */
-		FN_DU0_DG6, FN_LCDOUT14, 0, 0,
-		/* IP5_1_0 [2] */
-		FN_DU0_DG5, FN_LCDOUT13, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
-			     GROUP(3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1,
-				   1, 1, 2, 2, 2, 2),
-			     GROUP(
-		/* IP6_31_29 [3] */
-		FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D,
-		FN_AVB_TX_CLK, FN_ADIDATA, 0, 0,
-		/* IP6_28_26 [3] */
-		FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
-		FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
-		/* IP6_25_23 [3] */
-		FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
-		FN_AVB_COL, 0, 0, 0,
-		/* IP6_22_20 [3] */
-		FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
-		FN_AVB_RX_ER, 0, 0, 0,
-		/* IP6_19_17 [3] */
-		FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
-		FN_AVB_RXD7, 0, 0, 0,
-		/* IP6_16 [1] */
-		FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
-		/* IP6_15 [1] */
-		FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
-		/* IP6_14 [1] */
-		FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
-		/* IP6_13 [1] */
-		FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
-		/* IP6_12 [1] */
-		FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
-		/* IP6_11 [1] */
-		FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
-		/* IP6_10 [1] */
-		FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
-		/* IP6_9 [1] */
-		FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
-		/* IP6_8 [1] */
-		FN_VI0_CLK, FN_AVB_RX_CLK,
-		/* IP6_7_6 [2] */
-		FN_DU0_CDE, FN_QPOLB, 0, 0,
-		/* IP6_5_4 [2] */
-		FN_DU0_DISP, FN_QPOLA, 0, 0,
-		/* IP6_3_2 [2] */
-		FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0,
-		0,
-		/* IP6_1_0 [2] */
-		FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
-			     GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
-			     GROUP(
-		/* IP7_31 [1] */
-		FN_DREQ0_N, FN_SCIFB1_RXD,
-		/* IP7_30 [1] */
-		0, 0,
-		/* IP7_29_27 [3] */
-		FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
-		FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
-		/* IP7_26_24 [3] */
-		FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
-		FN_SSI_SCK6_B, 0, 0, 0,
-		/* IP7_23_21 [3] */
-		FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D,
-		FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
-		/* IP7_20_18 [3] */
-		FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D,
-		FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
-		/* IP7_17_15 [3] */
-		FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
-		FN_SSI_SCK5_B, 0, 0, 0,
-		/* IP7_14_12 [3] */
-		FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
-		FN_AVB_TXD4, FN_ADICHS2, 0, 0,
-		/* IP7_11_9 [3] */
-		FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
-		FN_AVB_TXD3, FN_ADICHS1, 0, 0,
-		/* IP7_8_6 [3] */
-		FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
-		FN_AVB_TXD2, FN_ADICHS0, 0, 0,
-		/* IP7_5_3 [3] */
-		FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
-		FN_AVB_TXD1, FN_ADICLK, 0, 0,
-		/* IP7_2_0 [3] */
-		FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D,
-		FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
-			     GROUP(3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3),
-			     GROUP(
-		/* IP8_31_29 [3] */
-		FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
-		0, FN_TS_SDEN_D, FN_FMCLK_C, 0,
-		/* IP8_28_26 [3] */
-		FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
-		0, FN_TS_SCK_D, FN_BPFCLK_C, 0,
-		/* IP8_25_23 [3] */
-		FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
-		0, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
-		/* IP8_22_20 [3] */
-		FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
-		FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
-		/* IP8_19_17 [3] */
-		FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
-		FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
-		/* IP8_16_15 [2] */
-		FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
-		/* IP8_14_12 [3] */
-		FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
-		FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
-		/* IP8_11_9 [3] */
-		FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
-		FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
-		/* IP8_8_6 [3] */
-		FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
-		FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
-		/* IP8_5_3 [3] */
-		FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
-		FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
-		/* IP8_2_0 [3] */
-		FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
-		FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
-			     GROUP(1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3),
-			     GROUP(
-		/* IP9_31 [1] */
-		0, 0,
-		/* IP9_30_28 [3] */
-		FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
-		FN_SSI_SDATA1_B, 0, 0, 0,
-		/* IP9_27_25 [3] */
-		FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4,
-		FN_SSI_WS1_B, 0, 0, 0,
-		/* IP9_24_22 [3] */
-		FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3,
-		FN_SSI_SCK1_B, 0, 0, 0,
-		/* IP9_21_19 [3] */
-		FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2,
-		FN_REMOCON_B, FN_SPEEDIN_B, 0, 0,
-		/* IP9_18_17 [2] */
-		FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
-		/* IP9_16_15 [2] */
-		FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
-		/* IP9_14_12 [3] */
-		FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
-		0, FN_FMIN_B, 0, 0,
-		/* IP9_11_9 [3] */
-		FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6,
-		0, FN_FMCLK_B, 0, 0,
-		/* IP9_8_6 [3] */
-		FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5,
-		0, FN_BPFCLK_B, 0, 0,
-		/* IP9_5_3 [3] */
-		FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4,
-		0, FN_TPUTO1_C, 0, 0,
-		/* IP9_2_0 [3] */
-		FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
-		0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
-			     GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
-			     GROUP(
-		/* IP10_31_30 [2] */
-		FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0,
-		/* IP10_29_27 [3] */
-		FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
-		0, 0, 0, 0,
-		/* IP10_26_24 [3] */
-		FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
-		FN_SSI_SDATA4_B, 0, 0, 0,
-		/* IP10_23_21 [3] */
-		FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5,
-		FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0,
-		/* IP10_20_18 [3] */
-		FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4,
-		FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, 0, 0,
-		/* IP10_17_15 [3] */
-		FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
-		FN_SSI_SDATA9_B, 0, 0, 0,
-		/* IP10_14_12 [3] */
-		FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
-		0, 0, 0, 0,
-		/* IP10_11_9 [3] */
-		FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
-		0, 0, 0, 0,
-		/* IP10_8_6 [3] */
-		FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
-		0, 0, 0, 0,
-		/* IP10_5_3 [3] */
-		FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
-		0, 0, 0, 0,
-		/* IP10_2_0 [3] */
-		FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
-		0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
-			     GROUP(2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3),
-			     GROUP(
-		/* IP11_31_30 [2] */
-		0, 0, 0, 0,
-		/* IP11_29_27 [3] */
-		FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
-		0, 0, 0, 0,
-		/* IP11_26_24 [3] */
-		FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
-		0, 0, 0, 0,
-		/* IP11_23_21 [3] */
-		FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
-		0, 0, 0, 0,
-		/* IP11_20_18 [3] */
-		FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
-		FN_CAN_CLK_D, 0, 0, 0,
-		/* IP11_17_16 [2] */
-		FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
-		/* IP11_15_14 [2] */
-		FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
-		/* IP11_13_11 [3] */
-		FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
-		FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0, 0, 0,
-		/* IP11_10_8 [3] */
-		FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
-		FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0, 0, 0,
-		/* IP11_7_6 [2] */
-		FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, 0,
-		/* IP11_5_3 [3] */
-		FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
-		0, 0, 0, 0,
-		/* IP11_2_0 [3] */
-		FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
-		0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
-			     GROUP(2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3),
-			     GROUP(
-		/* IP12_31_30 [2] */
-		0, 0, 0, 0,
-		/* IP12_29_27 [3] */
-		FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 0,
-		FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0,
-		/* IP12_26_24 [3] */
-		FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, 0,
-		FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0,
-		/* IP12_23_21 [3] */
-		FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0,
-		FN_CAN0_TX_D, 0, FN_ETH_RX_ER_B, 0,
-		/* IP12_20_18 [3] */
-		FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK,
-		FN_CAN0_RX_D, 0, FN_ETH_CRS_DV_B, 0,
-		/* IP12_17_15 [3] */
-		FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
-		FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0,
-		/* IP12_14_13 [2] */
-		FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, 0,
-		/* IP12_12_11 [2] */
-		FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, 0,
-		/* IP12_10_9 [2] */
-		FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, 0,
-		/* IP12_8_6 [3] */
-		FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
-		FN_CAN1_TX_C, FN_DREQ2_N, 0, 0,
-		/* IP12_5_3 [3] */
-		FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
-		FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
-		/* IP12_2_0 [3] */
-		FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
-		0, FN_DREQ1_N_B, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
-			     GROUP(1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3),
-			     GROUP(
-		/* IP13_31 [1] */
-		0, 0,
-		/* IP13_30 [1] */
-		0, 0,
-		/* IP13_29 [1] */
-		0, 0,
-		/* IP13_28 [1] */
-		0, 0,
-		/* IP13_27 [1] */
-		0, 0,
-		/* IP13_26_24 [3] */
-		FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
-		FN_TS_SPSYNC_C, 0, FN_FMIN_E, 0,
-		/* IP13_23_21 [3] */
-		FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
-		FN_TS_SDEN_C, 0, FN_FMCLK_E, 0,
-		/* IP13_20_18 [3] */
-		FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
-		FN_TS_SCK_C, 0, FN_BPFCLK_E, FN_ETH_MDC_B,
-		/* IP13_17_15 [3] */
-		FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
-		FN_TS_SDATA_C, 0, FN_ETH_TXD0_B, 0,
-		/* IP13_14_12 [3] */
-		FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
-		FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0,
-		/* IP13_11_9 [3] */
-		FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6,
-		FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0,
-		/* IP13_8_6 [3] */
-		FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5,
-		0, FN_EX_WAIT1, FN_ETH_TXD1_B, 0,
-		/* IP13_5_3 [2] */
-		FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D,
-		FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
-		/* IP13_2_0 [3] */
-		FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
-		0, FN_ATACS00_N, FN_ETH_LINK_B, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
-			     GROUP(2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, 2, 1),
-			     GROUP(
-		/* SEL_ADG [2] */
-		FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
-		/* RESERVED [1] */
-		0, 0,
-		/* SEL_CAN [2] */
-		FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
-		/* SEL_DARC [3] */
-		FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
-		FN_SEL_DARC_4, 0, 0, 0,
-		/* RESERVED [4] */
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		/* SEL_ETH [1] */
-		FN_SEL_ETH_0, FN_SEL_ETH_1,
-		/* RESERVED [1] */
-		0, 0,
-		/* SEL_IC200 [3] */
-		FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
-		FN_SEL_I2C00_4, 0, 0, 0,
-		/* SEL_I2C01 [3] */
-		FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
-		FN_SEL_I2C01_4, 0, 0, 0,
-		/* SEL_I2C02 [3] */
-		FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
-		FN_SEL_I2C02_4, 0, 0, 0,
-		/* SEL_I2C03 [3] */
-		FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
-		FN_SEL_I2C03_4, 0, 0, 0,
-		/* SEL_I2C04 [3] */
-		FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
-		FN_SEL_I2C04_4, 0, 0, 0,
-		/* SEL_I2C05 [2] */
-		FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
-		/* RESERVED [1] */
-		0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
-			     GROUP(2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1,
-				   2, 2, 1, 1, 2, 2, 2, 1, 1, 2),
-			     GROUP(
-		/* SEL_IEB [2] */
-		FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
-		/* SEL_IIC0 [2] */
-		FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
-		/* SEL_LBS [1] */
-		FN_SEL_LBS_0, FN_SEL_LBS_1,
-		/* SEL_MSI1 [1] */
-		FN_SEL_MSI1_0, FN_SEL_MSI1_1,
-		/* SEL_MSI2 [1] */
-		FN_SEL_MSI2_0, FN_SEL_MSI2_1,
-		/* SEL_RAD [1] */
-		FN_SEL_RAD_0, FN_SEL_RAD_1,
-		/* SEL_RCN [1] */
-		FN_SEL_RCN_0, FN_SEL_RCN_1,
-		/* SEL_RSP [1] */
-		FN_SEL_RSP_0, FN_SEL_RSP_1,
-		/* SEL_SCIFA0 [2] */
-		FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
-		FN_SEL_SCIFA0_3,
-		/* SEL_SCIFA1 [2] */
-		FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
-		/* SEL_SCIFA2 [1] */
-		FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
-		/* SEL_SCIFA3 [1] */
-		FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
-		/* SEL_SCIFA4 [2] */
-		FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
-		FN_SEL_SCIFA4_3,
-		/* SEL_SCIFA5 [2] */
-		FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
-		FN_SEL_SCIFA5_3,
-		/* RESERVED [1] */
-		0, 0,
-		/* SEL_TMU [1] */
-		FN_SEL_TMU_0, FN_SEL_TMU_1,
-		/* SEL_TSIF0 [2] */
-		FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
-		/* SEL_CAN0 [2] */
-		FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
-		/* SEL_CAN1 [2] */
-		FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
-		/* SEL_HSCIF0 [1] */
-		FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
-		/* SEL_HSCIF1 [1] */
-		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
-		/* RESERVED [2] */
-		0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
-			     GROUP(2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1,
-				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
-			     GROUP(
-		/* SEL_SCIF0 [2] */
-		FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
-		/* SEL_SCIF1 [2] */
-		FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
-		/* SEL_SCIF2 [2] */
-		FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
-		/* SEL_SCIF3 [1] */
-		FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
-		/* SEL_SCIF4 [3] */
-		FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
-		FN_SEL_SCIF4_4, 0, 0, 0,
-		/* SEL_SCIF5 [2] */
-		FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
-		/* SEL_SSI1 [1] */
-		FN_SEL_SSI1_0, FN_SEL_SSI1_1,
-		/* SEL_SSI2 [1] */
-		FN_SEL_SSI2_0, FN_SEL_SSI2_1,
-		/* SEL_SSI4 [1] */
-		FN_SEL_SSI4_0, FN_SEL_SSI4_1,
-		/* SEL_SSI5 [1] */
-		FN_SEL_SSI5_0, FN_SEL_SSI5_1,
-		/* SEL_SSI6 [1] */
-		FN_SEL_SSI6_0, FN_SEL_SSI6_1,
-		/* SEL_SSI7 [1] */
-		FN_SEL_SSI7_0, FN_SEL_SSI7_1,
-		/* SEL_SSI8 [1] */
-		FN_SEL_SSI8_0, FN_SEL_SSI8_1,
-		/* SEL_SSI9 [1] */
-		FN_SEL_SSI9_0, FN_SEL_SSI9_1,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0,
-		/* RESERVED [1] */
-		0, 0, ))
-	},
-	{ },
-};
-
-static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
-{
-	*pocctrl = 0xe606006c;
-
-	switch (pin & 0x1f) {
-	case 6: return 23;
-	case 7: return 16;
-	case 14: return 15;
-	case 15: return 8;
-	case 0 ... 5:
-	case 8 ... 13:
-		return 22 - (pin & 0x1f);
-	case 16 ... 23:
-		return 47 - (pin & 0x1f);
-	}
-
-	return -EINVAL;
-}
-
-static const struct soc_device_attribute r8a7794_tdsel[] = {
-	{ .soc_id = "r8a7794", .revision = "ES1.0" },
-	{ /* sentinel */ }
-};
-
-static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc)
-{
-	/* Initialize TDSEL on old revisions */
-	if (soc_device_match(r8a7794_tdsel))
-		sh_pfc_write(pfc, 0xe6060068, 0x55555500);
-
-	return 0;
-}
-
-static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
-	.init = r8a7794_pinmux_soc_init,
-	.pin_to_pocctrl = r8a7794_pin_to_pocctrl,
-};
-
-#ifdef CONFIG_PINCTRL_PFC_R8A7745
-const struct sh_pfc_soc_info r8a7745_pinmux_info = {
-	.name = "r8a77450_pfc",
-	.ops = &r8a7794_pinmux_ops,
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups,
-	.nr_groups = ARRAY_SIZE(pinmux_groups),
-	.functions = pinmux_functions,
-	.nr_functions = ARRAY_SIZE(pinmux_functions),
-
-	.cfg_regs = pinmux_config_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
-#endif
-
-#ifdef CONFIG_PINCTRL_PFC_R8A7794
-const struct sh_pfc_soc_info r8a7794_pinmux_info = {
-	.name = "r8a77940_pfc",
-	.ops = &r8a7794_pinmux_ops,
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups,
-	.nr_groups = ARRAY_SIZE(pinmux_groups),
-	.functions = pinmux_functions,
-	.nr_functions = ARRAY_SIZE(pinmux_functions),
-
-	.cfg_regs = pinmux_config_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
-#endif
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77950.c b/drivers/pinctrl/sh-pfc/pfc-r8a77950.c
deleted file mode 100644
index 04812e62f3a4..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77950.c
+++ /dev/null
@@ -1,5891 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * R8A77950 processor support - PFC hardware block.
- *
- * Copyright (C) 2015-2017  Renesas Electronics Corporation
- */
-
-#include <linux/errno.h>
-#include <linux/kernel.h>
-
-#include "core.h"
-#include "sh_pfc.h"
-
-#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
-
-#define CPU_ALL_GP(fn, sfx)						\
-	PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
-
-#define CPU_ALL_NOGP(fn)						\
-	PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS),			\
-	PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(CLKOUT, "CLKOUT", fn, CFG_FLAGS),			\
-	PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
-	PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
-	PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
-	PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
-	PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS),			\
-	PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
-
-/*
- * F_() : just information
- * FM() : macro for FN_xxx / xxx_MARK
- */
-
-/* GPSR0 */
-#define GPSR0_15	F_(D15,			IP7_11_8)
-#define GPSR0_14	F_(D14,			IP7_7_4)
-#define GPSR0_13	F_(D13,			IP7_3_0)
-#define GPSR0_12	F_(D12,			IP6_31_28)
-#define GPSR0_11	F_(D11,			IP6_27_24)
-#define GPSR0_10	F_(D10,			IP6_23_20)
-#define GPSR0_9		F_(D9,			IP6_19_16)
-#define GPSR0_8		F_(D8,			IP6_15_12)
-#define GPSR0_7		F_(D7,			IP6_11_8)
-#define GPSR0_6		F_(D6,			IP6_7_4)
-#define GPSR0_5		F_(D5,			IP6_3_0)
-#define GPSR0_4		F_(D4,			IP5_31_28)
-#define GPSR0_3		F_(D3,			IP5_27_24)
-#define GPSR0_2		F_(D2,			IP5_23_20)
-#define GPSR0_1		F_(D1,			IP5_19_16)
-#define GPSR0_0		F_(D0,			IP5_15_12)
-
-/* GPSR1 */
-#define GPSR1_27	F_(EX_WAIT0_A,		IP5_11_8)
-#define GPSR1_26	F_(WE1_N,		IP5_7_4)
-#define GPSR1_25	F_(WE0_N,		IP5_3_0)
-#define GPSR1_24	F_(RD_WR_N,		IP4_31_28)
-#define GPSR1_23	F_(RD_N,		IP4_27_24)
-#define GPSR1_22	F_(BS_N,		IP4_23_20)
-#define GPSR1_21	F_(CS1_N_A26,		IP4_19_16)
-#define GPSR1_20	F_(CS0_N,		IP4_15_12)
-#define GPSR1_19	F_(A19,			IP4_11_8)
-#define GPSR1_18	F_(A18,			IP4_7_4)
-#define GPSR1_17	F_(A17,			IP4_3_0)
-#define GPSR1_16	F_(A16,			IP3_31_28)
-#define GPSR1_15	F_(A15,			IP3_27_24)
-#define GPSR1_14	F_(A14,			IP3_23_20)
-#define GPSR1_13	F_(A13,			IP3_19_16)
-#define GPSR1_12	F_(A12,			IP3_15_12)
-#define GPSR1_11	F_(A11,			IP3_11_8)
-#define GPSR1_10	F_(A10,			IP3_7_4)
-#define GPSR1_9		F_(A9,			IP3_3_0)
-#define GPSR1_8		F_(A8,			IP2_31_28)
-#define GPSR1_7		F_(A7,			IP2_27_24)
-#define GPSR1_6		F_(A6,			IP2_23_20)
-#define GPSR1_5		F_(A5,			IP2_19_16)
-#define GPSR1_4		F_(A4,			IP2_15_12)
-#define GPSR1_3		F_(A3,			IP2_11_8)
-#define GPSR1_2		F_(A2,			IP2_7_4)
-#define GPSR1_1		F_(A1,			IP2_3_0)
-#define GPSR1_0		F_(A0,			IP1_31_28)
-
-/* GPSR2 */
-#define GPSR2_14	F_(AVB_AVTP_CAPTURE_A,	IP0_23_20)
-#define GPSR2_13	F_(AVB_AVTP_MATCH_A,	IP0_19_16)
-#define GPSR2_12	F_(AVB_LINK,		IP0_15_12)
-#define GPSR2_11	F_(AVB_PHY_INT,		IP0_11_8)
-#define GPSR2_10	F_(AVB_MAGIC,		IP0_7_4)
-#define GPSR2_9		F_(AVB_MDC,		IP0_3_0)
-#define GPSR2_8		F_(PWM2_A,		IP1_27_24)
-#define GPSR2_7		F_(PWM1_A,		IP1_23_20)
-#define GPSR2_6		F_(PWM0,		IP1_19_16)
-#define GPSR2_5		F_(IRQ5,		IP1_15_12)
-#define GPSR2_4		F_(IRQ4,		IP1_11_8)
-#define GPSR2_3		F_(IRQ3,		IP1_7_4)
-#define GPSR2_2		F_(IRQ2,		IP1_3_0)
-#define GPSR2_1		F_(IRQ1,		IP0_31_28)
-#define GPSR2_0		F_(IRQ0,		IP0_27_24)
-
-/* GPSR3 */
-#define GPSR3_15	F_(SD1_WP,		IP10_23_20)
-#define GPSR3_14	F_(SD1_CD,		IP10_19_16)
-#define GPSR3_13	F_(SD0_WP,		IP10_15_12)
-#define GPSR3_12	F_(SD0_CD,		IP10_11_8)
-#define GPSR3_11	F_(SD1_DAT3,		IP8_31_28)
-#define GPSR3_10	F_(SD1_DAT2,		IP8_27_24)
-#define GPSR3_9		F_(SD1_DAT1,		IP8_23_20)
-#define GPSR3_8		F_(SD1_DAT0,		IP8_19_16)
-#define GPSR3_7		F_(SD1_CMD,		IP8_15_12)
-#define GPSR3_6		F_(SD1_CLK,		IP8_11_8)
-#define GPSR3_5		F_(SD0_DAT3,		IP8_7_4)
-#define GPSR3_4		F_(SD0_DAT2,		IP8_3_0)
-#define GPSR3_3		F_(SD0_DAT1,		IP7_31_28)
-#define GPSR3_2		F_(SD0_DAT0,		IP7_27_24)
-#define GPSR3_1		F_(SD0_CMD,		IP7_23_20)
-#define GPSR3_0		F_(SD0_CLK,		IP7_19_16)
-
-/* GPSR4 */
-#define GPSR4_17	FM(SD3_DS)
-#define GPSR4_16	F_(SD3_DAT7,		IP10_7_4)
-#define GPSR4_15	F_(SD3_DAT6,		IP10_3_0)
-#define GPSR4_14	F_(SD3_DAT5,		IP9_31_28)
-#define GPSR4_13	F_(SD3_DAT4,		IP9_27_24)
-#define GPSR4_12	FM(SD3_DAT3)
-#define GPSR4_11	FM(SD3_DAT2)
-#define GPSR4_10	FM(SD3_DAT1)
-#define GPSR4_9		FM(SD3_DAT0)
-#define GPSR4_8		FM(SD3_CMD)
-#define GPSR4_7		FM(SD3_CLK)
-#define GPSR4_6		F_(SD2_DS,		IP9_23_20)
-#define GPSR4_5		F_(SD2_DAT3,		IP9_19_16)
-#define GPSR4_4		F_(SD2_DAT2,		IP9_15_12)
-#define GPSR4_3		F_(SD2_DAT1,		IP9_11_8)
-#define GPSR4_2		F_(SD2_DAT0,		IP9_7_4)
-#define GPSR4_1		FM(SD2_CMD)
-#define GPSR4_0		F_(SD2_CLK,		IP9_3_0)
-
-/* GPSR5 */
-#define GPSR5_25	F_(MLB_DAT,		IP13_19_16)
-#define GPSR5_24	F_(MLB_SIG,		IP13_15_12)
-#define GPSR5_23	F_(MLB_CLK,		IP13_11_8)
-#define GPSR5_22	FM(MSIOF0_RXD)
-#define GPSR5_21	F_(MSIOF0_SS2,		IP13_7_4)
-#define GPSR5_20	FM(MSIOF0_TXD)
-#define GPSR5_19	F_(MSIOF0_SS1,		IP13_3_0)
-#define GPSR5_18	F_(MSIOF0_SYNC,		IP12_31_28)
-#define GPSR5_17	FM(MSIOF0_SCK)
-#define GPSR5_16	F_(HRTS0_N,		IP12_27_24)
-#define GPSR5_15	F_(HCTS0_N,		IP12_23_20)
-#define GPSR5_14	F_(HTX0,		IP12_19_16)
-#define GPSR5_13	F_(HRX0,		IP12_15_12)
-#define GPSR5_12	F_(HSCK0,		IP12_11_8)
-#define GPSR5_11	F_(RX2_A,		IP12_7_4)
-#define GPSR5_10	F_(TX2_A,		IP12_3_0)
-#define GPSR5_9		F_(SCK2,		IP11_31_28)
-#define GPSR5_8		F_(RTS1_N,		IP11_27_24)
-#define GPSR5_7		F_(CTS1_N,		IP11_23_20)
-#define GPSR5_6		F_(TX1_A,		IP11_19_16)
-#define GPSR5_5		F_(RX1_A,		IP11_15_12)
-#define GPSR5_4		F_(RTS0_N,		IP11_11_8)
-#define GPSR5_3		F_(CTS0_N,		IP11_7_4)
-#define GPSR5_2		F_(TX0,			IP11_3_0)
-#define GPSR5_1		F_(RX0,			IP10_31_28)
-#define GPSR5_0		F_(SCK0,		IP10_27_24)
-
-/* GPSR6 */
-#define GPSR6_31	F_(USB31_OVC,		IP17_7_4)
-#define GPSR6_30	F_(USB31_PWEN,		IP17_3_0)
-#define GPSR6_29	F_(USB30_OVC,		IP16_31_28)
-#define GPSR6_28	F_(USB30_PWEN,		IP16_27_24)
-#define GPSR6_27	F_(USB1_OVC,		IP16_23_20)
-#define GPSR6_26	F_(USB1_PWEN,		IP16_19_16)
-#define GPSR6_25	F_(USB0_OVC,		IP16_15_12)
-#define GPSR6_24	F_(USB0_PWEN,		IP16_11_8)
-#define GPSR6_23	F_(AUDIO_CLKB_B,	IP16_7_4)
-#define GPSR6_22	F_(AUDIO_CLKA_A,	IP16_3_0)
-#define GPSR6_21	F_(SSI_SDATA9_A,	IP15_31_28)
-#define GPSR6_20	F_(SSI_SDATA8,		IP15_27_24)
-#define GPSR6_19	F_(SSI_SDATA7,		IP15_23_20)
-#define GPSR6_18	F_(SSI_WS78,		IP15_19_16)
-#define GPSR6_17	F_(SSI_SCK78,		IP15_15_12)
-#define GPSR6_16	F_(SSI_SDATA6,		IP15_11_8)
-#define GPSR6_15	F_(SSI_WS6,		IP15_7_4)
-#define GPSR6_14	F_(SSI_SCK6,		IP15_3_0)
-#define GPSR6_13	FM(SSI_SDATA5)
-#define GPSR6_12	FM(SSI_WS5)
-#define GPSR6_11	FM(SSI_SCK5)
-#define GPSR6_10	F_(SSI_SDATA4,		IP14_31_28)
-#define GPSR6_9		F_(SSI_WS4,		IP14_27_24)
-#define GPSR6_8		F_(SSI_SCK4,		IP14_23_20)
-#define GPSR6_7		F_(SSI_SDATA3,		IP14_19_16)
-#define GPSR6_6		F_(SSI_WS349,		IP14_15_12)
-#define GPSR6_5		F_(SSI_SCK349,		IP14_11_8)
-#define GPSR6_4		F_(SSI_SDATA2_A,	IP14_7_4)
-#define GPSR6_3		F_(SSI_SDATA1_A,	IP14_3_0)
-#define GPSR6_2		F_(SSI_SDATA0,		IP13_31_28)
-#define GPSR6_1		F_(SSI_WS01239,		IP13_27_24)
-#define GPSR6_0		F_(SSI_SCK01239,	IP13_23_20)
-
-/* GPSR7 */
-#define GPSR7_3		FM(GP7_03)
-#define GPSR7_2		FM(GP7_02)
-#define GPSR7_1		FM(AVS2)
-#define GPSR7_0		FM(AVS1)
-
-
-/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
-#define IP0_3_0		FM(AVB_MDC)		F_(0, 0)	FM(MSIOF2_SS2_C)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_7_4		FM(AVB_MAGIC)		F_(0, 0)	FM(MSIOF2_SS1_C)	FM(SCK4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_11_8	FM(AVB_PHY_INT)		F_(0, 0)	FM(MSIOF2_SYNC_C)	FM(RX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_15_12	FM(AVB_LINK)		F_(0, 0)	FM(MSIOF2_SCK_C)	FM(TX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_19_16	FM(AVB_AVTP_MATCH_A)	F_(0, 0)	FM(MSIOF2_RXD_C)	FM(CTS4_N_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_23_20	FM(AVB_AVTP_CAPTURE_A)	F_(0, 0)	FM(MSIOF2_TXD_C)	FM(RTS4_N_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_27_24	FM(IRQ0)		FM(QPOLB)	F_(0, 0)		FM(DU_CDE)			FM(VI4_DATA0_B)	FM(CAN0_TX_B)	FM(CANFD0_TX_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_31_28	FM(IRQ1)		FM(QPOLA)	F_(0, 0)		FM(DU_DISP)			FM(VI4_DATA1_B)	FM(CAN0_RX_B)	FM(CANFD0_RX_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_3_0		FM(IRQ2)		FM(QCPV_QDE)	F_(0, 0)		FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(VI4_DATA2_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(PWM3_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_7_4		FM(IRQ3)		FM(QSTVB_QVE)	FM(A25)			FM(DU_DOTCLKOUT1)		FM(VI4_DATA3_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(PWM4_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_11_8	FM(IRQ4)		FM(QSTH_QHS)	FM(A24)			FM(DU_EXHSYNC_DU_HSYNC)		FM(VI4_DATA4_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(PWM5_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_15_12	FM(IRQ5)		FM(QSTB_QHE)	FM(A23)			FM(DU_EXVSYNC_DU_VSYNC)		FM(VI4_DATA5_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(PWM6_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_19_16	FM(PWM0)		FM(AVB_AVTP_PPS)FM(A22)			F_(0, 0)			FM(VI4_DATA6_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IECLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_23_20	FM(PWM1_A)		F_(0, 0)	FM(A21)			FM(HRX3_D)			FM(VI4_DATA7_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IERX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_27_24	FM(PWM2_A)		F_(0, 0)	FM(A20)			FM(HTX3_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IETX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_31_28	FM(A0)			FM(LCDOUT16)	FM(MSIOF3_SYNC_B)	F_(0, 0)			FM(VI4_DATA8)	F_(0, 0)	FM(DU_DB0)		F_(0, 0)	F_(0, 0)		FM(PWM3_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_3_0		FM(A1)			FM(LCDOUT17)	FM(MSIOF3_TXD_B)	F_(0, 0)			FM(VI4_DATA9)	F_(0, 0)	FM(DU_DB1)		F_(0, 0)	F_(0, 0)		FM(PWM4_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_7_4		FM(A2)			FM(LCDOUT18)	FM(MSIOF3_SCK_B)	F_(0, 0)			FM(VI4_DATA10)	F_(0, 0)	FM(DU_DB2)		F_(0, 0)	F_(0, 0)		FM(PWM5_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_11_8	FM(A3)			FM(LCDOUT19)	FM(MSIOF3_RXD_B)	F_(0, 0)			FM(VI4_DATA11)	F_(0, 0)	FM(DU_DB3)		F_(0, 0)	F_(0, 0)		FM(PWM6_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
-#define IP2_15_12	FM(A4)			FM(LCDOUT20)	FM(MSIOF3_SS1_B)	F_(0, 0)			FM(VI4_DATA12)	FM(VI5_DATA12)	FM(DU_DB4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_19_16	FM(A5)			FM(LCDOUT21)	FM(MSIOF3_SS2_B)	FM(SCK4_B)			FM(VI4_DATA13)	FM(VI5_DATA13)	FM(DU_DB5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_23_20	FM(A6)			FM(LCDOUT22)	FM(MSIOF2_SS1_A)	FM(RX4_B)			FM(VI4_DATA14)	FM(VI5_DATA14)	FM(DU_DB6)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_27_24	FM(A7)			FM(LCDOUT23)	FM(MSIOF2_SS2_A)	FM(TX4_B)			FM(VI4_DATA15)	FM(VI5_DATA15)	FM(DU_DB7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_31_28	FM(A8)			FM(RX3_B)	FM(MSIOF2_SYNC_A)	FM(HRX4_B)			F_(0, 0)	F_(0, 0)	F_(0, 0)		FM(SDA6_A)	FM(AVB_AVTP_MATCH_B)	FM(PWM1_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_3_0		FM(A9)			F_(0, 0)	FM(MSIOF2_SCK_A)	FM(CTS4_N_B)			F_(0, 0)	FM(VI5_VSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_7_4		FM(A10)			F_(0, 0)	FM(MSIOF2_RXD_A)	FM(RTS4_N_B)			F_(0, 0)	FM(VI5_HSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_11_8	FM(A11)			FM(TX3_B)	FM(MSIOF2_TXD_A)	FM(HTX4_B)			FM(HSCK4)	FM(VI5_FIELD)	F_(0, 0)		FM(SCL6_A)	FM(AVB_AVTP_CAPTURE_B)	FM(PWM2_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_15_12	FM(A12)			FM(LCDOUT12)	FM(MSIOF3_SCK_C)	F_(0, 0)			FM(HRX4_A)	FM(VI5_DATA8)	FM(DU_DG4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_19_16	FM(A13)			FM(LCDOUT13)	FM(MSIOF3_SYNC_C)	F_(0, 0)			FM(HTX4_A)	FM(VI5_DATA9)	FM(DU_DG5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_23_20	FM(A14)			FM(LCDOUT14)	FM(MSIOF3_RXD_C)	F_(0, 0)			FM(HCTS4_N)	FM(VI5_DATA10)	FM(DU_DG6)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_27_24	FM(A15)			FM(LCDOUT15)	FM(MSIOF3_TXD_C)	F_(0, 0)			FM(HRTS4_N)	FM(VI5_DATA11)	FM(DU_DG7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_31_28	FM(A16)			FM(LCDOUT8)	F_(0, 0)		F_(0, 0)			FM(VI4_FIELD)	F_(0, 0)	FM(DU_DG0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_3_0		FM(A17)			FM(LCDOUT9)	F_(0, 0)		F_(0, 0)			FM(VI4_VSYNC_N)	F_(0, 0)	FM(DU_DG1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_7_4		FM(A18)			FM(LCDOUT10)	F_(0, 0)		F_(0, 0)			FM(VI4_HSYNC_N)	F_(0, 0)	FM(DU_DG2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_11_8	FM(A19)			FM(LCDOUT11)	F_(0, 0)		F_(0, 0)			FM(VI4_CLKENB)	F_(0, 0)	FM(DU_DG3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_15_12	FM(CS0_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(VI5_CLKENB)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_19_16	FM(CS1_N_A26)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(VI5_CLK)	F_(0, 0)		FM(EX_WAIT0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_23_20	FM(BS_N)		FM(QSTVA_QVS)	FM(MSIOF3_SCK_D)	FM(SCK3)			FM(HSCK3)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN1_TX)		FM(CANFD1_TX)	FM(IETX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_27_24	FM(RD_N)		F_(0, 0)	FM(MSIOF3_SYNC_D)	FM(RX3_A)			FM(HRX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_TX_A)		FM(CANFD0_TX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_31_28	FM(RD_WR_N)		F_(0, 0)	FM(MSIOF3_RXD_D)	FM(TX3_A)			FM(HTX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_RX_A)		FM(CANFD0_RX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_3_0		FM(WE0_N)		F_(0, 0)	FM(MSIOF3_TXD_D)	FM(CTS3_N)			FM(HCTS3_N)	F_(0, 0)	F_(0, 0)		FM(SCL6_B)	FM(CAN_CLK)		F_(0, 0)	FM(IECLK_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_7_4		FM(WE1_N)		F_(0, 0)	FM(MSIOF3_SS1_D)	FM(RTS3_N)			FM(HRTS3_N)	F_(0, 0)	F_(0, 0)		FM(SDA6_B)	FM(CAN1_RX)		FM(CANFD1_RX)	FM(IERX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_11_8	FM(EX_WAIT0_A)		FM(QCLK)	F_(0, 0)		F_(0, 0)			FM(VI4_CLK)	F_(0, 0)	FM(DU_DOTCLKOUT0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_15_12	FM(D0)			FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)	F_(0, 0)			FM(VI4_DATA16)	FM(VI5_DATA0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_19_16	FM(D1)			FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)	F_(0, 0)			FM(VI4_DATA17)	FM(VI5_DATA1)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_23_20	FM(D2)			F_(0, 0)	FM(MSIOF3_RXD_A)	F_(0, 0)			FM(VI4_DATA18)	FM(VI5_DATA2)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_27_24	FM(D3)			F_(0, 0)	FM(MSIOF3_TXD_A)	F_(0, 0)			FM(VI4_DATA19)	FM(VI5_DATA3)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_31_28	FM(D4)			FM(MSIOF2_SCK_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA20)	FM(VI5_DATA4)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_3_0		FM(D5)			FM(MSIOF2_SYNC_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA21)	FM(VI5_DATA5)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_7_4		FM(D6)			FM(MSIOF2_RXD_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA22)	FM(VI5_DATA6)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_11_8	FM(D7)			FM(MSIOF2_TXD_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA23)	FM(VI5_DATA7)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_15_12	FM(D8)			FM(LCDOUT0)	FM(MSIOF2_SCK_D)	FM(SCK4_C)			FM(VI4_DATA0_A)	F_(0, 0)	FM(DU_DR0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_19_16	FM(D9)			FM(LCDOUT1)	FM(MSIOF2_SYNC_D)	F_(0, 0)			FM(VI4_DATA1_A)	F_(0, 0)	FM(DU_DR1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_23_20	FM(D10)			FM(LCDOUT2)	FM(MSIOF2_RXD_D)	FM(HRX3_B)			FM(VI4_DATA2_A)	FM(CTS4_N_C)	FM(DU_DR2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_27_24	FM(D11)			FM(LCDOUT3)	FM(MSIOF2_TXD_D)	FM(HTX3_B)			FM(VI4_DATA3_A)	FM(RTS4_N_C)	FM(DU_DR3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_31_28	FM(D12)			FM(LCDOUT4)	FM(MSIOF2_SS1_D)	FM(RX4_C)			FM(VI4_DATA4_A)	F_(0, 0)	FM(DU_DR4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_3_0		FM(D13)			FM(LCDOUT5)	FM(MSIOF2_SS2_D)	FM(TX4_C)			FM(VI4_DATA5_A)	F_(0, 0)	FM(DU_DR5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_7_4		FM(D14)			FM(LCDOUT6)	FM(MSIOF3_SS1_A)	FM(HRX3_C)			FM(VI4_DATA6_A)	F_(0, 0)	FM(DU_DR6)		FM(SCL6_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_11_8	FM(D15)			FM(LCDOUT7)	FM(MSIOF3_SS2_A)	FM(HTX3_C)			FM(VI4_DATA7_A)	F_(0, 0)	FM(DU_DR7)		FM(SDA6_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_15_12	FM(FSCLKST)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_19_16	FM(SD0_CLK)		F_(0, 0)	FM(MSIOF1_SCK_E)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_OPWM_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
-#define IP7_23_20	FM(SD0_CMD)		F_(0, 0)	FM(MSIOF1_SYNC_E)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_27_24	FM(SD0_DAT0)		F_(0, 0)	FM(MSIOF1_RXD_E)	F_(0, 0)			F_(0, 0)	FM(TS_SCK0_B)	FM(STP_ISCLK_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_31_28	FM(SD0_DAT1)		F_(0, 0)	FM(MSIOF1_TXD_E)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_3_0		FM(SD0_DAT2)		F_(0, 0)	FM(MSIOF1_SS1_E)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_B)	FM(STP_ISD_0_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_7_4		FM(SD0_DAT3)		F_(0, 0)	FM(MSIOF1_SS2_E)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_B)	FM(STP_ISEN_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_11_8	FM(SD1_CLK)		F_(0, 0)	FM(MSIOF1_SCK_G)	F_(0, 0)			F_(0, 0)	FM(SIM0_CLK_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_15_12	FM(SD1_CMD)		F_(0, 0)	FM(MSIOF1_SYNC_G)	F_(0, 0)			F_(0, 0)	FM(SIM0_D_A)	FM(STP_IVCXO27_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_19_16	FM(SD1_DAT0)		FM(SD2_DAT4)	FM(MSIOF1_RXD_G)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_B)	FM(STP_ISCLK_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_23_20	FM(SD1_DAT1)		FM(SD2_DAT5)	FM(MSIOF1_TXD_G)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_27_24	FM(SD1_DAT2)		FM(SD2_DAT6)	FM(MSIOF1_SS1_G)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_B)	FM(STP_ISD_1_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_31_28	FM(SD1_DAT3)		FM(SD2_DAT7)	FM(MSIOF1_SS2_G)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_B)	FM(STP_ISEN_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_3_0		FM(SD2_CLK)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_7_4		FM(SD2_DAT0)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_11_8	FM(SD2_DAT1)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_15_12	FM(SD2_DAT2)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_19_16	FM(SD2_DAT3)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_23_20	FM(SD2_DS)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(SATA_DEVSLP_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_27_24	FM(SD3_DAT4)		FM(SD2_CD_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_31_28	FM(SD3_DAT5)		FM(SD2_WP_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_3_0	FM(SD3_DAT6)		FM(SD3_CD)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_7_4	FM(SD3_DAT7)		FM(SD3_WP)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_11_8	FM(SD0_CD)		F_(0, 0)	F_(0, 0)		F_(0, 0)			FM(SCL2_B)	FM(SIM0_RST_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_15_12	FM(SD0_WP)		F_(0, 0)	F_(0, 0)		F_(0, 0)			FM(SDA2_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_19_16	FM(SD1_CD)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(SIM0_CLK_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_23_20	FM(SD1_WP)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(SIM0_D_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_27_24	FM(SCK0)		FM(HSCK1_B)	FM(MSIOF1_SS2_B)	FM(AUDIO_CLKC_B)		FM(SDA2_A)	FM(SIM0_RST_B)	FM(STP_OPWM_0_C)	FM(RIF0_CLK_B)	F_(0, 0)		FM(ADICHS2)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_31_28	FM(RX0)			FM(HRX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SCK0_C)	FM(STP_ISCLK_0_C)	FM(RIF0_D0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_3_0	FM(TX0)			FM(HTX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)	FM(RIF0_D1_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_7_4	FM(CTS0_N)		FM(HCTS1_N_B)	FM(MSIOF1_SYNC_B)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)	FM(RIF1_SYNC_B)	FM(AUDIO_CLKOUT_C)	FM(ADICS_SAMP)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_11_8	FM(RTS0_N)		FM(HRTS1_N_B)	FM(MSIOF1_SS1_B)	FM(AUDIO_CLKA_B)		FM(SCL2_A)	F_(0, 0)	FM(STP_IVCXO27_1_C)	FM(RIF0_SYNC_B)	F_(0, 0)		FM(ADICHS1)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_15_12	FM(RX1_A)		FM(HRX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_C)	FM(STP_ISD_0_C)		FM(RIF1_CLK_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_19_16	FM(TX1_A)		FM(HTX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_C)	FM(STP_ISEN_0_C)	FM(RIF1_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_23_20	FM(CTS1_N)		FM(HCTS1_N_A)	FM(MSIOF1_RXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_C)	FM(STP_ISEN_1_C)	FM(RIF1_D0_B)	F_(0, 0)		FM(ADIDATA)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_27_24	FM(RTS1_N)		FM(HRTS1_N_A)	FM(MSIOF1_TXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_C)	FM(STP_ISD_1_C)		FM(RIF1_D1_B)	F_(0, 0)		FM(ADICHS0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_31_28	FM(SCK2)		FM(SCIF_CLK_B)	FM(MSIOF1_SCK_B)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_C)	FM(STP_ISCLK_1_C)	FM(RIF1_CLK_B)	F_(0, 0)		FM(ADICLK)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_3_0	FM(TX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_CD_B)			FM(SCL1_A)	F_(0, 0)	FM(FMCLK_A)		FM(RIF1_D1_C)	F_(0, 0)		FM(FSO_CFE_0_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_7_4	FM(RX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_WP_B)			FM(SDA1_A)	F_(0, 0)	FM(FMIN_A)		FM(RIF1_SYNC_C)	F_(0, 0)		FM(FSO_CFE_1_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_11_8	FM(HSCK0)		F_(0, 0)	FM(MSIOF1_SCK_D)	FM(AUDIO_CLKB_A)		FM(SSI_SDATA1_B)FM(TS_SCK0_D)	FM(STP_ISCLK_0_D)	FM(RIF0_CLK_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_15_12	FM(HRX0)		F_(0, 0)	FM(MSIOF1_RXD_D)	F_(0, 0)			FM(SSI_SDATA2_B)FM(TS_SDEN0_D)	FM(STP_ISEN_0_D)	FM(RIF0_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_19_16	FM(HTX0)		F_(0, 0)	FM(MSIOF1_TXD_D)	F_(0, 0)			FM(SSI_SDATA9_B)FM(TS_SDAT0_D)	FM(STP_ISD_0_D)		FM(RIF0_D1_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_23_20	FM(HCTS0_N)		FM(RX2_B)	FM(MSIOF1_SYNC_D)	F_(0, 0)			FM(SSI_SCK9_A)	FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)	FM(RIF0_SYNC_C)	FM(AUDIO_CLKOUT1_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_27_24	FM(HRTS0_N)		FM(TX2_B)	FM(MSIOF1_SS1_D)	F_(0, 0)			FM(SSI_WS9_A)	F_(0, 0)	FM(STP_IVCXO27_0_D)	FM(BPFCLK_A)	FM(AUDIO_CLKOUT2_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
-#define IP12_31_28	FM(MSIOF0_SYNC)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(AUDIO_CLKOUT_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_3_0	FM(MSIOF0_SS1)		FM(RX5)		F_(0, 0)		FM(AUDIO_CLKA_C)		FM(SSI_SCK2_A)	F_(0, 0)	FM(STP_IVCXO27_0_C)	F_(0, 0)	FM(AUDIO_CLKOUT3_A)	F_(0, 0)	FM(TCLK1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_7_4	FM(MSIOF0_SS2)		FM(TX5)		FM(MSIOF1_SS2_D)	FM(AUDIO_CLKC_A)		FM(SSI_WS2_A)	F_(0, 0)	FM(STP_OPWM_0_D)	F_(0, 0)	FM(AUDIO_CLKOUT_D)	F_(0, 0)	FM(SPEEDIN_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_11_8	FM(MLB_CLK)		F_(0, 0)	FM(MSIOF1_SCK_F)	F_(0, 0)			FM(SCL1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_15_12	FM(MLB_SIG)		FM(RX1_B)	FM(MSIOF1_SYNC_F)	F_(0, 0)			FM(SDA1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_19_16	FM(MLB_DAT)		FM(TX1_B)	FM(MSIOF1_RXD_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_23_20	FM(SSI_SCK01239)	F_(0, 0)	FM(MSIOF1_TXD_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_27_24	FM(SSI_WS01239)		F_(0, 0)	FM(MSIOF1_SS1_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_31_28	FM(SSI_SDATA0)		F_(0, 0)	FM(MSIOF1_SS2_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_3_0	FM(SSI_SDATA1_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_7_4	FM(SSI_SDATA2_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			FM(SSI_SCK1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_11_8	FM(SSI_SCK349)		F_(0, 0)	FM(MSIOF1_SS1_A)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_OPWM_0_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_15_12	FM(SSI_WS349)		FM(HCTS2_N_A)	FM(MSIOF1_SS2_A)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_0_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_19_16	FM(SSI_SDATA3)		FM(HRTS2_N_A)	FM(MSIOF1_TXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SCK0_A)	FM(STP_ISCLK_0_A)	FM(RIF0_D1_A)	FM(RIF2_D0_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_23_20	FM(SSI_SCK4)		FM(HRX2_A)	FM(MSIOF1_SCK_A)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_A)	FM(STP_ISD_0_A)		FM(RIF0_CLK_A)	FM(RIF2_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_27_24	FM(SSI_WS4)		FM(HTX2_A)	FM(MSIOF1_SYNC_A)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_A)	FM(STP_ISEN_0_A)	FM(RIF0_SYNC_A)	FM(RIF2_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_31_28	FM(SSI_SDATA4)		FM(HSCK2_A)	FM(MSIOF1_RXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)	FM(RIF0_D0_A)	FM(RIF2_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_3_0	FM(SSI_SCK6)		FM(USB2_PWEN)	F_(0, 0)		FM(SIM0_RST_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_7_4	FM(SSI_WS6)		FM(USB2_OVC)	F_(0, 0)		FM(SIM0_D_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_11_8	FM(SSI_SDATA6)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(SATA_DEVSLP_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_15_12	FM(SSI_SCK78)		FM(HRX2_B)	FM(MSIOF1_SCK_C)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_A)	FM(STP_ISCLK_1_A)	FM(RIF1_CLK_A)	FM(RIF3_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_19_16	FM(SSI_WS78)		FM(HTX2_B)	FM(MSIOF1_SYNC_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_A)	FM(STP_ISD_1_A)		FM(RIF1_SYNC_A)	FM(RIF3_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_23_20	FM(SSI_SDATA7)		FM(HCTS2_N_B)	FM(MSIOF1_RXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_A)	FM(STP_ISEN_1_A)	FM(RIF1_D0_A)	FM(RIF3_D0_A)		F_(0, 0)	FM(TCLK2_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_27_24	FM(SSI_SDATA8)		FM(HRTS2_N_B)	FM(MSIOF1_TXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)	FM(RIF1_D1_A)	FM(RIF3_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_31_28	FM(SSI_SDATA9_A)	FM(HSCK2_B)	FM(MSIOF1_SS1_C)	FM(HSCK1_A)			FM(SSI_WS1_B)	FM(SCK1)	FM(STP_IVCXO27_1_A)	FM(SCK5)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_3_0	FM(AUDIO_CLKA_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_7_4	FM(AUDIO_CLKB_B)	FM(SCIF_CLK_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_1_D)	FM(REMOCON_A)	F_(0, 0)		F_(0, 0)	FM(TCLK1_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_11_8	FM(USB0_PWEN)		F_(0, 0)	F_(0, 0)		FM(SIM0_RST_C)			F_(0, 0)	FM(TS_SCK1_D)	FM(STP_ISCLK_1_D)	FM(BPFCLK_B)	FM(RIF3_CLK_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_15_12	FM(USB0_OVC)		F_(0, 0)	F_(0, 0)		FM(SIM0_D_C)			F_(0, 0)	FM(TS_SDAT1_D)	FM(STP_ISD_1_D)		F_(0, 0)	FM(RIF3_SYNC_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_19_16	FM(USB1_PWEN)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_C)			FM(SSI_SCK1_A)	FM(TS_SCK0_E)	FM(STP_ISCLK_0_E)	FM(FMCLK_B)	FM(RIF2_CLK_B)		F_(0, 0)	FM(SPEEDIN_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_23_20	FM(USB1_OVC)		F_(0, 0)	FM(MSIOF1_SS2_C)	F_(0, 0)			FM(SSI_WS1_A)	FM(TS_SDAT0_E)	FM(STP_ISD_0_E)		FM(FMIN_B)	FM(RIF2_SYNC_B)		F_(0, 0)	FM(REMOCON_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_27_24	FM(USB30_PWEN)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT_B)		FM(SSI_SCK2_B)	FM(TS_SDEN1_D)	FM(STP_ISEN_1_D)	FM(STP_OPWM_0_E)FM(RIF3_D0_B)		F_(0, 0)	FM(TCLK2_B)	FM(TPU0TO0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_31_28	FM(USB30_OVC)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT1_B)		FM(SSI_WS2_B)	FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)	FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)	F_(0, 0)	FM(FSO_TOE_B)	FM(TPU0TO1)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP17_3_0	FM(USB31_PWEN)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT2_B)		FM(SSI_SCK9_B)	FM(TS_SDEN0_E)	FM(STP_ISEN_0_E)	F_(0, 0)	FM(RIF2_D0_B)		F_(0, 0)	F_(0, 0)	FM(TPU0TO2)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP17_7_4	FM(USB31_OVC)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT3_B)		FM(SSI_WS9_B)	FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)	F_(0, 0)	FM(RIF2_D1_B)		F_(0, 0)	F_(0, 0)	FM(TPU0TO3)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-#define PINMUX_GPSR	\
-\
-												GPSR6_31 \
-												GPSR6_30 \
-												GPSR6_29 \
-												GPSR6_28 \
-		GPSR1_27									GPSR6_27 \
-		GPSR1_26									GPSR6_26 \
-		GPSR1_25							GPSR5_25	GPSR6_25 \
-		GPSR1_24							GPSR5_24	GPSR6_24 \
-		GPSR1_23							GPSR5_23	GPSR6_23 \
-		GPSR1_22							GPSR5_22	GPSR6_22 \
-		GPSR1_21							GPSR5_21	GPSR6_21 \
-		GPSR1_20							GPSR5_20	GPSR6_20 \
-		GPSR1_19							GPSR5_19	GPSR6_19 \
-		GPSR1_18							GPSR5_18	GPSR6_18 \
-		GPSR1_17					GPSR4_17	GPSR5_17	GPSR6_17 \
-		GPSR1_16					GPSR4_16	GPSR5_16	GPSR6_16 \
-GPSR0_15	GPSR1_15			GPSR3_15	GPSR4_15	GPSR5_15	GPSR6_15 \
-GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14	GPSR4_14	GPSR5_14	GPSR6_14 \
-GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13	GPSR4_13	GPSR5_13	GPSR6_13 \
-GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12	GPSR4_12	GPSR5_12	GPSR6_12 \
-GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11	GPSR4_11	GPSR5_11	GPSR6_11 \
-GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10	GPSR6_10 \
-GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9		GPSR6_9 \
-GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8		GPSR6_8 \
-GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7		GPSR6_7 \
-GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6		GPSR6_6 \
-GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5		GPSR6_5 \
-GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4		GPSR6_4 \
-GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3		GPSR6_3		GPSR7_3 \
-GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2		GPSR6_2		GPSR7_2 \
-GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1		GPSR6_1		GPSR7_1 \
-GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0		GPSR6_0		GPSR7_0
-
-#define PINMUX_IPSR				\
-\
-FM(IP0_3_0)	IP0_3_0		FM(IP1_3_0)	IP1_3_0		FM(IP2_3_0)	IP2_3_0		FM(IP3_3_0)	IP3_3_0 \
-FM(IP0_7_4)	IP0_7_4		FM(IP1_7_4)	IP1_7_4		FM(IP2_7_4)	IP2_7_4		FM(IP3_7_4)	IP3_7_4 \
-FM(IP0_11_8)	IP0_11_8	FM(IP1_11_8)	IP1_11_8	FM(IP2_11_8)	IP2_11_8	FM(IP3_11_8)	IP3_11_8 \
-FM(IP0_15_12)	IP0_15_12	FM(IP1_15_12)	IP1_15_12	FM(IP2_15_12)	IP2_15_12	FM(IP3_15_12)	IP3_15_12 \
-FM(IP0_19_16)	IP0_19_16	FM(IP1_19_16)	IP1_19_16	FM(IP2_19_16)	IP2_19_16	FM(IP3_19_16)	IP3_19_16 \
-FM(IP0_23_20)	IP0_23_20	FM(IP1_23_20)	IP1_23_20	FM(IP2_23_20)	IP2_23_20	FM(IP3_23_20)	IP3_23_20 \
-FM(IP0_27_24)	IP0_27_24	FM(IP1_27_24)	IP1_27_24	FM(IP2_27_24)	IP2_27_24	FM(IP3_27_24)	IP3_27_24 \
-FM(IP0_31_28)	IP0_31_28	FM(IP1_31_28)	IP1_31_28	FM(IP2_31_28)	IP2_31_28	FM(IP3_31_28)	IP3_31_28 \
-\
-FM(IP4_3_0)	IP4_3_0		FM(IP5_3_0)	IP5_3_0		FM(IP6_3_0)	IP6_3_0		FM(IP7_3_0)	IP7_3_0 \
-FM(IP4_7_4)	IP4_7_4		FM(IP5_7_4)	IP5_7_4		FM(IP6_7_4)	IP6_7_4		FM(IP7_7_4)	IP7_7_4 \
-FM(IP4_11_8)	IP4_11_8	FM(IP5_11_8)	IP5_11_8	FM(IP6_11_8)	IP6_11_8	FM(IP7_11_8)	IP7_11_8 \
-FM(IP4_15_12)	IP4_15_12	FM(IP5_15_12)	IP5_15_12	FM(IP6_15_12)	IP6_15_12	FM(IP7_15_12)	IP7_15_12 \
-FM(IP4_19_16)	IP4_19_16	FM(IP5_19_16)	IP5_19_16	FM(IP6_19_16)	IP6_19_16	FM(IP7_19_16)	IP7_19_16 \
-FM(IP4_23_20)	IP4_23_20	FM(IP5_23_20)	IP5_23_20	FM(IP6_23_20)	IP6_23_20	FM(IP7_23_20)	IP7_23_20 \
-FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
-FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
-\
-FM(IP8_3_0)	IP8_3_0		FM(IP9_3_0)	IP9_3_0		FM(IP10_3_0)	IP10_3_0	FM(IP11_3_0)	IP11_3_0 \
-FM(IP8_7_4)	IP8_7_4		FM(IP9_7_4)	IP9_7_4		FM(IP10_7_4)	IP10_7_4	FM(IP11_7_4)	IP11_7_4 \
-FM(IP8_11_8)	IP8_11_8	FM(IP9_11_8)	IP9_11_8	FM(IP10_11_8)	IP10_11_8	FM(IP11_11_8)	IP11_11_8 \
-FM(IP8_15_12)	IP8_15_12	FM(IP9_15_12)	IP9_15_12	FM(IP10_15_12)	IP10_15_12	FM(IP11_15_12)	IP11_15_12 \
-FM(IP8_19_16)	IP8_19_16	FM(IP9_19_16)	IP9_19_16	FM(IP10_19_16)	IP10_19_16	FM(IP11_19_16)	IP11_19_16 \
-FM(IP8_23_20)	IP8_23_20	FM(IP9_23_20)	IP9_23_20	FM(IP10_23_20)	IP10_23_20	FM(IP11_23_20)	IP11_23_20 \
-FM(IP8_27_24)	IP8_27_24	FM(IP9_27_24)	IP9_27_24	FM(IP10_27_24)	IP10_27_24	FM(IP11_27_24)	IP11_27_24 \
-FM(IP8_31_28)	IP8_31_28	FM(IP9_31_28)	IP9_31_28	FM(IP10_31_28)	IP10_31_28	FM(IP11_31_28)	IP11_31_28 \
-\
-FM(IP12_3_0)	IP12_3_0	FM(IP13_3_0)	IP13_3_0	FM(IP14_3_0)	IP14_3_0	FM(IP15_3_0)	IP15_3_0 \
-FM(IP12_7_4)	IP12_7_4	FM(IP13_7_4)	IP13_7_4	FM(IP14_7_4)	IP14_7_4	FM(IP15_7_4)	IP15_7_4 \
-FM(IP12_11_8)	IP12_11_8	FM(IP13_11_8)	IP13_11_8	FM(IP14_11_8)	IP14_11_8	FM(IP15_11_8)	IP15_11_8 \
-FM(IP12_15_12)	IP12_15_12	FM(IP13_15_12)	IP13_15_12	FM(IP14_15_12)	IP14_15_12	FM(IP15_15_12)	IP15_15_12 \
-FM(IP12_19_16)	IP12_19_16	FM(IP13_19_16)	IP13_19_16	FM(IP14_19_16)	IP14_19_16	FM(IP15_19_16)	IP15_19_16 \
-FM(IP12_23_20)	IP12_23_20	FM(IP13_23_20)	IP13_23_20	FM(IP14_23_20)	IP14_23_20	FM(IP15_23_20)	IP15_23_20 \
-FM(IP12_27_24)	IP12_27_24	FM(IP13_27_24)	IP13_27_24	FM(IP14_27_24)	IP14_27_24	FM(IP15_27_24)	IP15_27_24 \
-FM(IP12_31_28)	IP12_31_28	FM(IP13_31_28)	IP13_31_28	FM(IP14_31_28)	IP14_31_28	FM(IP15_31_28)	IP15_31_28 \
-\
-FM(IP16_3_0)	IP16_3_0	FM(IP17_3_0)	IP17_3_0 \
-FM(IP16_7_4)	IP16_7_4	FM(IP17_7_4)	IP17_7_4 \
-FM(IP16_11_8)	IP16_11_8 \
-FM(IP16_15_12)	IP16_15_12 \
-FM(IP16_19_16)	IP16_19_16 \
-FM(IP16_23_20)	IP16_23_20 \
-FM(IP16_27_24)	IP16_27_24 \
-FM(IP16_31_28)	IP16_31_28
-
-/* MOD_SEL0 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
-#define MOD_SEL0_30_29		FM(SEL_MSIOF3_0)	FM(SEL_MSIOF3_1)	FM(SEL_MSIOF3_2)	FM(SEL_MSIOF3_3)
-#define MOD_SEL0_28_27		FM(SEL_MSIOF2_0)	FM(SEL_MSIOF2_1)	FM(SEL_MSIOF2_2)	FM(SEL_MSIOF2_3)
-#define MOD_SEL0_26_25_24	FM(SEL_MSIOF1_0)	FM(SEL_MSIOF1_1)	FM(SEL_MSIOF1_2)	FM(SEL_MSIOF1_3)	FM(SEL_MSIOF1_4)	FM(SEL_MSIOF1_5)	FM(SEL_MSIOF1_6)	F_(0, 0)
-#define MOD_SEL0_23		FM(SEL_LBSC_0)		FM(SEL_LBSC_1)
-#define MOD_SEL0_22		FM(SEL_IEBUS_0)		FM(SEL_IEBUS_1)
-#define MOD_SEL0_21_20		FM(SEL_I2C6_0)		FM(SEL_I2C6_1)		FM(SEL_I2C6_2)		F_(0, 0)
-#define MOD_SEL0_19		FM(SEL_I2C2_0)		FM(SEL_I2C2_1)
-#define MOD_SEL0_18		FM(SEL_I2C1_0)		FM(SEL_I2C1_1)
-#define MOD_SEL0_17		FM(SEL_HSCIF4_0)	FM(SEL_HSCIF4_1)
-#define MOD_SEL0_16_15		FM(SEL_HSCIF3_0)	FM(SEL_HSCIF3_1)	FM(SEL_HSCIF3_2)	FM(SEL_HSCIF3_3)
-#define MOD_SEL0_14		FM(SEL_HSCIF2_0)	FM(SEL_HSCIF2_1)
-#define MOD_SEL0_13		FM(SEL_HSCIF1_0)	FM(SEL_HSCIF1_1)
-#define MOD_SEL0_12		FM(SEL_FSO_0)		FM(SEL_FSO_1)
-#define MOD_SEL0_11		FM(SEL_FM_0)		FM(SEL_FM_1)
-#define MOD_SEL0_10		FM(SEL_ETHERAVB_0)	FM(SEL_ETHERAVB_1)
-#define MOD_SEL0_9		FM(SEL_DRIF3_0)		FM(SEL_DRIF3_1)
-#define MOD_SEL0_8		FM(SEL_DRIF2_0)		FM(SEL_DRIF2_1)
-#define MOD_SEL0_7_6		FM(SEL_DRIF1_0)		FM(SEL_DRIF1_1)		FM(SEL_DRIF1_2)		F_(0, 0)
-#define MOD_SEL0_5_4		FM(SEL_DRIF0_0)		FM(SEL_DRIF0_1)		FM(SEL_DRIF0_2)		F_(0, 0)
-#define MOD_SEL0_3		FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
-#define MOD_SEL0_2_1		FM(SEL_ADG_0)		FM(SEL_ADG_1)		FM(SEL_ADG_2)		FM(SEL_ADG_3)
-
-/* MOD_SEL1 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
-#define MOD_SEL1_31_30		FM(SEL_TSIF1_0)		FM(SEL_TSIF1_1)		FM(SEL_TSIF1_2)		FM(SEL_TSIF1_3)
-#define MOD_SEL1_29_28_27	FM(SEL_TSIF0_0)		FM(SEL_TSIF0_1)		FM(SEL_TSIF0_2)		FM(SEL_TSIF0_3)		FM(SEL_TSIF0_4)		F_(0, 0)		F_(0, 0)		F_(0, 0)
-#define MOD_SEL1_26		FM(SEL_TIMER_TMU_0)	FM(SEL_TIMER_TMU_1)
-#define MOD_SEL1_25_24		FM(SEL_SSP1_1_0)	FM(SEL_SSP1_1_1)	FM(SEL_SSP1_1_2)	FM(SEL_SSP1_1_3)
-#define MOD_SEL1_23_22_21	FM(SEL_SSP1_0_0)	FM(SEL_SSP1_0_1)	FM(SEL_SSP1_0_2)	FM(SEL_SSP1_0_3)	FM(SEL_SSP1_0_4)	F_(0, 0)		F_(0, 0)		F_(0, 0)
-#define MOD_SEL1_20		FM(SEL_SSI_0)		FM(SEL_SSI_1)
-#define MOD_SEL1_19		FM(SEL_SPEED_PULSE_0)	FM(SEL_SPEED_PULSE_1)
-#define MOD_SEL1_18_17		FM(SEL_SIMCARD_0)	FM(SEL_SIMCARD_1)	FM(SEL_SIMCARD_2)	FM(SEL_SIMCARD_3)
-#define MOD_SEL1_16		FM(SEL_SDHI2_0)		FM(SEL_SDHI2_1)
-#define MOD_SEL1_15_14		FM(SEL_SCIF4_0)		FM(SEL_SCIF4_1)		FM(SEL_SCIF4_2)		F_(0, 0)
-#define MOD_SEL1_13		FM(SEL_SCIF3_0)		FM(SEL_SCIF3_1)
-#define MOD_SEL1_12		FM(SEL_SCIF2_0)		FM(SEL_SCIF2_1)
-#define MOD_SEL1_11		FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
-#define MOD_SEL1_10		FM(SEL_SATA_0)		FM(SEL_SATA_1)
-#define MOD_SEL1_9		FM(SEL_REMOCON_0)	FM(SEL_REMOCON_1)
-#define MOD_SEL1_6		FM(SEL_RCAN0_0)		FM(SEL_RCAN0_1)
-#define MOD_SEL1_5		FM(SEL_PWM6_0)		FM(SEL_PWM6_1)
-#define MOD_SEL1_4		FM(SEL_PWM5_0)		FM(SEL_PWM5_1)
-#define MOD_SEL1_3		FM(SEL_PWM4_0)		FM(SEL_PWM4_1)
-#define MOD_SEL1_2		FM(SEL_PWM3_0)		FM(SEL_PWM3_1)
-#define MOD_SEL1_1		FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
-#define MOD_SEL1_0		FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
-
-/* MOD_SEL2 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */
-#define MOD_SEL2_31		FM(I2C_SEL_5_0)		FM(I2C_SEL_5_1)
-#define MOD_SEL2_30		FM(I2C_SEL_3_0)		FM(I2C_SEL_3_1)
-#define MOD_SEL2_29		FM(I2C_SEL_0_0)		FM(I2C_SEL_0_1)
-#define MOD_SEL2_0		FM(SEL_VIN4_0)		FM(SEL_VIN4_1)
-
-#define PINMUX_MOD_SELS\
-\
-			MOD_SEL1_31_30		MOD_SEL2_31 \
-MOD_SEL0_30_29					MOD_SEL2_30 \
-			MOD_SEL1_29_28_27	MOD_SEL2_29 \
-MOD_SEL0_28_27 \
-\
-MOD_SEL0_26_25_24	MOD_SEL1_26 \
-			MOD_SEL1_25_24 \
-\
-MOD_SEL0_23		MOD_SEL1_23_22_21 \
-MOD_SEL0_22 \
-MOD_SEL0_21_20 \
-			MOD_SEL1_20 \
-MOD_SEL0_19		MOD_SEL1_19 \
-MOD_SEL0_18		MOD_SEL1_18_17 \
-MOD_SEL0_17 \
-MOD_SEL0_16_15		MOD_SEL1_16 \
-			MOD_SEL1_15_14 \
-MOD_SEL0_14 \
-MOD_SEL0_13		MOD_SEL1_13 \
-MOD_SEL0_12		MOD_SEL1_12 \
-MOD_SEL0_11		MOD_SEL1_11 \
-MOD_SEL0_10		MOD_SEL1_10 \
-MOD_SEL0_9		MOD_SEL1_9 \
-MOD_SEL0_8 \
-MOD_SEL0_7_6 \
-			MOD_SEL1_6 \
-MOD_SEL0_5_4		MOD_SEL1_5 \
-			MOD_SEL1_4 \
-MOD_SEL0_3		MOD_SEL1_3 \
-MOD_SEL0_2_1		MOD_SEL1_2 \
-			MOD_SEL1_1 \
-			MOD_SEL1_0		MOD_SEL2_0
-
-/*
- * These pins are not able to be muxed but have other properties
- * that can be set, such as drive-strength or pull-up/pull-down enable.
- */
-#define PINMUX_STATIC \
-	FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
-	FM(QSPI0_IO2) FM(QSPI0_IO3) \
-	FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
-	FM(QSPI1_IO2) FM(QSPI1_IO3) \
-	FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
-	FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
-	FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
-	FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
-	FM(CLKOUT) FM(PRESETOUT) \
-	FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
-	FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
-
-#define PINMUX_PHYS \
-	FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	GP_ALL(DATA),
-	PINMUX_DATA_END,
-
-#define F_(x, y)
-#define FM(x)	FN_##x,
-	PINMUX_FUNCTION_BEGIN,
-	GP_ALL(FN),
-	PINMUX_GPSR
-	PINMUX_IPSR
-	PINMUX_MOD_SELS
-	PINMUX_FUNCTION_END,
-#undef F_
-#undef FM
-
-#define F_(x, y)
-#define FM(x)	x##_MARK,
-	PINMUX_MARK_BEGIN,
-	PINMUX_GPSR
-	PINMUX_IPSR
-	PINMUX_MOD_SELS
-	PINMUX_STATIC
-	PINMUX_PHYS
-	PINMUX_MARK_END,
-#undef F_
-#undef FM
-};
-
-static const u16 pinmux_data[] = {
-	PINMUX_DATA_GP_ALL(),
-
-	PINMUX_SINGLE(AVS1),
-	PINMUX_SINGLE(AVS2),
-	PINMUX_SINGLE(GP7_02),
-	PINMUX_SINGLE(GP7_03),
-	PINMUX_SINGLE(MSIOF0_RXD),
-	PINMUX_SINGLE(MSIOF0_SCK),
-	PINMUX_SINGLE(MSIOF0_TXD),
-	PINMUX_SINGLE(SD2_CMD),
-	PINMUX_SINGLE(SD3_CLK),
-	PINMUX_SINGLE(SD3_CMD),
-	PINMUX_SINGLE(SD3_DAT0),
-	PINMUX_SINGLE(SD3_DAT1),
-	PINMUX_SINGLE(SD3_DAT2),
-	PINMUX_SINGLE(SD3_DAT3),
-	PINMUX_SINGLE(SD3_DS),
-	PINMUX_SINGLE(SSI_SCK5),
-	PINMUX_SINGLE(SSI_SDATA5),
-	PINMUX_SINGLE(SSI_WS5),
-
-	/* IPSR0 */
-	PINMUX_IPSR_GPSR(IP0_3_0,	AVB_MDC),
-	PINMUX_IPSR_MSEL(IP0_3_0,	MSIOF2_SS2_C,		SEL_MSIOF2_2),
-
-	PINMUX_IPSR_GPSR(IP0_7_4,	AVB_MAGIC),
-	PINMUX_IPSR_MSEL(IP0_7_4,	MSIOF2_SS1_C,		SEL_MSIOF2_2),
-	PINMUX_IPSR_MSEL(IP0_7_4,	SCK4_A,			SEL_SCIF4_0),
-
-	PINMUX_IPSR_GPSR(IP0_11_8,	AVB_PHY_INT),
-	PINMUX_IPSR_MSEL(IP0_11_8,	MSIOF2_SYNC_C,		SEL_MSIOF2_2),
-	PINMUX_IPSR_MSEL(IP0_11_8,	RX4_A,			SEL_SCIF4_0),
-
-	PINMUX_IPSR_GPSR(IP0_15_12,	AVB_LINK),
-	PINMUX_IPSR_MSEL(IP0_15_12,	MSIOF2_SCK_C,		SEL_MSIOF2_2),
-	PINMUX_IPSR_MSEL(IP0_15_12,	TX4_A,			SEL_SCIF4_0),
-
-	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,	I2C_SEL_5_0,	SEL_ETHERAVB_0),
-	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C,		I2C_SEL_5_0,	SEL_MSIOF2_2),
-	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A,		I2C_SEL_5_0,	SEL_SCIF4_0),
-	PINMUX_IPSR_PHYS(IP0_19_16,	SCL5,			I2C_SEL_5_1),
-
-	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A,	I2C_SEL_5_0,	SEL_ETHERAVB_0),
-	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C,		I2C_SEL_5_0,	SEL_MSIOF2_2),
-	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A,		I2C_SEL_5_0,	SEL_SCIF4_0),
-	PINMUX_IPSR_PHYS(IP0_23_20,	SDA5,			I2C_SEL_5_1),
-
-	PINMUX_IPSR_GPSR(IP0_27_24,	IRQ0),
-	PINMUX_IPSR_GPSR(IP0_27_24,	QPOLB),
-	PINMUX_IPSR_GPSR(IP0_27_24,	DU_CDE),
-	PINMUX_IPSR_MSEL(IP0_27_24,	VI4_DATA0_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP0_27_24,	CAN0_TX_B,		SEL_RCAN0_1),
-	PINMUX_IPSR_MSEL(IP0_27_24,	CANFD0_TX_B,		SEL_CANFD0_1),
-
-	PINMUX_IPSR_GPSR(IP0_31_28,	IRQ1),
-	PINMUX_IPSR_GPSR(IP0_31_28,	QPOLA),
-	PINMUX_IPSR_GPSR(IP0_31_28,	DU_DISP),
-	PINMUX_IPSR_MSEL(IP0_31_28,	VI4_DATA1_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP0_31_28,	CAN0_RX_B,		SEL_RCAN0_1),
-	PINMUX_IPSR_MSEL(IP0_31_28,	CANFD0_RX_B,		SEL_CANFD0_1),
-
-	/* IPSR1 */
-	PINMUX_IPSR_GPSR(IP1_3_0,	IRQ2),
-	PINMUX_IPSR_GPSR(IP1_3_0,	QCPV_QDE),
-	PINMUX_IPSR_GPSR(IP1_3_0,	DU_EXODDF_DU_ODDF_DISP_CDE),
-	PINMUX_IPSR_MSEL(IP1_3_0,	VI4_DATA2_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP1_3_0,	PWM3_B,			SEL_PWM3_1),
-
-	PINMUX_IPSR_GPSR(IP1_7_4,	IRQ3),
-	PINMUX_IPSR_GPSR(IP1_7_4,	QSTVB_QVE),
-	PINMUX_IPSR_GPSR(IP1_7_4,	A25),
-	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DOTCLKOUT1),
-	PINMUX_IPSR_MSEL(IP1_7_4,	VI4_DATA3_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP1_7_4,	PWM4_B,			SEL_PWM4_1),
-
-	PINMUX_IPSR_GPSR(IP1_11_8,	IRQ4),
-	PINMUX_IPSR_GPSR(IP1_11_8,	QSTH_QHS),
-	PINMUX_IPSR_GPSR(IP1_11_8,	A24),
-	PINMUX_IPSR_GPSR(IP1_11_8,	DU_EXHSYNC_DU_HSYNC),
-	PINMUX_IPSR_MSEL(IP1_11_8,	VI4_DATA4_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP1_11_8,	PWM5_B,			SEL_PWM5_1),
-
-	PINMUX_IPSR_GPSR(IP1_15_12,	IRQ5),
-	PINMUX_IPSR_GPSR(IP1_15_12,	QSTB_QHE),
-	PINMUX_IPSR_GPSR(IP1_15_12,	A23),
-	PINMUX_IPSR_GPSR(IP1_15_12,	DU_EXVSYNC_DU_VSYNC),
-	PINMUX_IPSR_MSEL(IP1_15_12,	VI4_DATA5_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP1_15_12,	PWM6_B,			SEL_PWM6_1),
-
-	PINMUX_IPSR_GPSR(IP1_19_16,	PWM0),
-	PINMUX_IPSR_GPSR(IP1_19_16,	AVB_AVTP_PPS),
-	PINMUX_IPSR_GPSR(IP1_19_16,	A22),
-	PINMUX_IPSR_MSEL(IP1_19_16,	VI4_DATA6_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP1_19_16,	IECLK_B,		SEL_IEBUS_1),
-
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A,		I2C_SEL_3_0,	SEL_PWM1_0),
-	PINMUX_IPSR_MSEL(IP1_23_20,	A21,			I2C_SEL_3_0),
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B,		I2C_SEL_3_0,	SEL_VIN4_1),
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
-	PINMUX_IPSR_PHYS(IP1_23_20,	SCL3,			I2C_SEL_3_1),
-
-	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A,		I2C_SEL_3_0,	SEL_PWM2_0),
-	PINMUX_IPSR_MSEL(IP1_27_24,	A20,			I2C_SEL_3_0),
-	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
-	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
-	PINMUX_IPSR_PHYS(IP1_27_24,	SDA3,			I2C_SEL_3_1),
-
-	PINMUX_IPSR_GPSR(IP1_31_28,	A0),
-	PINMUX_IPSR_GPSR(IP1_31_28,	LCDOUT16),
-	PINMUX_IPSR_MSEL(IP1_31_28,	MSIOF3_SYNC_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP1_31_28,	VI4_DATA8),
-	PINMUX_IPSR_GPSR(IP1_31_28,	DU_DB0),
-	PINMUX_IPSR_MSEL(IP1_31_28,	PWM3_A,			SEL_PWM3_0),
-
-	/* IPSR2 */
-	PINMUX_IPSR_GPSR(IP2_3_0,	A1),
-	PINMUX_IPSR_GPSR(IP2_3_0,	LCDOUT17),
-	PINMUX_IPSR_MSEL(IP2_3_0,	MSIOF3_TXD_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP2_3_0,	VI4_DATA9),
-	PINMUX_IPSR_GPSR(IP2_3_0,	DU_DB1),
-	PINMUX_IPSR_MSEL(IP2_3_0,	PWM4_A,			SEL_PWM4_0),
-
-	PINMUX_IPSR_GPSR(IP2_7_4,	A2),
-	PINMUX_IPSR_GPSR(IP2_7_4,	LCDOUT18),
-	PINMUX_IPSR_MSEL(IP2_7_4,	MSIOF3_SCK_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP2_7_4,	VI4_DATA10),
-	PINMUX_IPSR_GPSR(IP2_7_4,	DU_DB2),
-	PINMUX_IPSR_MSEL(IP2_7_4,	PWM5_A,			SEL_PWM5_0),
-
-	PINMUX_IPSR_GPSR(IP2_11_8,	A3),
-	PINMUX_IPSR_GPSR(IP2_11_8,	LCDOUT19),
-	PINMUX_IPSR_MSEL(IP2_11_8,	MSIOF3_RXD_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP2_11_8,	VI4_DATA11),
-	PINMUX_IPSR_GPSR(IP2_11_8,	DU_DB3),
-	PINMUX_IPSR_MSEL(IP2_11_8,	PWM6_A,			SEL_PWM6_0),
-
-	PINMUX_IPSR_GPSR(IP2_15_12,	A4),
-	PINMUX_IPSR_GPSR(IP2_15_12,	LCDOUT20),
-	PINMUX_IPSR_MSEL(IP2_15_12,	MSIOF3_SS1_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP2_15_12,	VI4_DATA12),
-	PINMUX_IPSR_GPSR(IP2_15_12,	VI5_DATA12),
-	PINMUX_IPSR_GPSR(IP2_15_12,	DU_DB4),
-
-	PINMUX_IPSR_GPSR(IP2_19_16,	A5),
-	PINMUX_IPSR_GPSR(IP2_19_16,	LCDOUT21),
-	PINMUX_IPSR_MSEL(IP2_19_16,	MSIOF3_SS2_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_MSEL(IP2_19_16,	SCK4_B,			SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP2_19_16,	VI4_DATA13),
-	PINMUX_IPSR_GPSR(IP2_19_16,	VI5_DATA13),
-	PINMUX_IPSR_GPSR(IP2_19_16,	DU_DB5),
-
-	PINMUX_IPSR_GPSR(IP2_23_20,	A6),
-	PINMUX_IPSR_GPSR(IP2_23_20,	LCDOUT22),
-	PINMUX_IPSR_MSEL(IP2_23_20,	MSIOF2_SS1_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP2_23_20,	RX4_B,			SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP2_23_20,	VI4_DATA14),
-	PINMUX_IPSR_GPSR(IP2_23_20,	VI5_DATA14),
-	PINMUX_IPSR_GPSR(IP2_23_20,	DU_DB6),
-
-	PINMUX_IPSR_GPSR(IP2_27_24,	A7),
-	PINMUX_IPSR_GPSR(IP2_27_24,	LCDOUT23),
-	PINMUX_IPSR_MSEL(IP2_27_24,	MSIOF2_SS2_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP2_27_24,	TX4_B,			SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP2_27_24,	VI4_DATA15),
-	PINMUX_IPSR_GPSR(IP2_27_24,	VI5_DATA15),
-	PINMUX_IPSR_GPSR(IP2_27_24,	DU_DB7),
-
-	PINMUX_IPSR_GPSR(IP2_31_28,	A8),
-	PINMUX_IPSR_MSEL(IP2_31_28,	RX3_B,			SEL_SCIF3_1),
-	PINMUX_IPSR_MSEL(IP2_31_28,	MSIOF2_SYNC_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP2_31_28,	HRX4_B,			SEL_HSCIF4_1),
-	PINMUX_IPSR_MSEL(IP2_31_28,	SDA6_A,			SEL_I2C6_0),
-	PINMUX_IPSR_MSEL(IP2_31_28,	AVB_AVTP_MATCH_B,	SEL_ETHERAVB_1),
-	PINMUX_IPSR_MSEL(IP2_31_28,	PWM1_B,			SEL_PWM1_1),
-
-	/* IPSR3 */
-	PINMUX_IPSR_GPSR(IP3_3_0,	A9),
-	PINMUX_IPSR_MSEL(IP3_3_0,	MSIOF2_SCK_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP3_3_0,	CTS4_N_B,		SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP3_3_0,	VI5_VSYNC_N),
-
-	PINMUX_IPSR_GPSR(IP3_7_4,	A10),
-	PINMUX_IPSR_MSEL(IP3_7_4,	MSIOF2_RXD_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP3_7_4,	RTS4_N_B,		SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP3_7_4,	VI5_HSYNC_N),
-
-	PINMUX_IPSR_GPSR(IP3_11_8,	A11),
-	PINMUX_IPSR_MSEL(IP3_11_8,	TX3_B,			SEL_SCIF3_1),
-	PINMUX_IPSR_MSEL(IP3_11_8,	MSIOF2_TXD_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP3_11_8,	HTX4_B,			SEL_HSCIF4_1),
-	PINMUX_IPSR_GPSR(IP3_11_8,	HSCK4),
-	PINMUX_IPSR_GPSR(IP3_11_8,	VI5_FIELD),
-	PINMUX_IPSR_MSEL(IP3_11_8,	SCL6_A,			SEL_I2C6_0),
-	PINMUX_IPSR_MSEL(IP3_11_8,	AVB_AVTP_CAPTURE_B,	SEL_ETHERAVB_1),
-	PINMUX_IPSR_MSEL(IP3_11_8,	PWM2_B,			SEL_PWM2_1),
-
-	PINMUX_IPSR_GPSR(IP3_15_12,	A12),
-	PINMUX_IPSR_GPSR(IP3_15_12,	LCDOUT12),
-	PINMUX_IPSR_MSEL(IP3_15_12,	MSIOF3_SCK_C,		SEL_MSIOF3_2),
-	PINMUX_IPSR_MSEL(IP3_15_12,	HRX4_A,			SEL_HSCIF4_0),
-	PINMUX_IPSR_GPSR(IP3_15_12,	VI5_DATA8),
-	PINMUX_IPSR_GPSR(IP3_15_12,	DU_DG4),
-
-	PINMUX_IPSR_GPSR(IP3_19_16,	A13),
-	PINMUX_IPSR_GPSR(IP3_19_16,	LCDOUT13),
-	PINMUX_IPSR_MSEL(IP3_19_16,	MSIOF3_SYNC_C,		SEL_MSIOF3_2),
-	PINMUX_IPSR_MSEL(IP3_19_16,	HTX4_A,			SEL_HSCIF4_0),
-	PINMUX_IPSR_GPSR(IP3_19_16,	VI5_DATA9),
-	PINMUX_IPSR_GPSR(IP3_19_16,	DU_DG5),
-
-	PINMUX_IPSR_GPSR(IP3_23_20,	A14),
-	PINMUX_IPSR_GPSR(IP3_23_20,	LCDOUT14),
-	PINMUX_IPSR_MSEL(IP3_23_20,	MSIOF3_RXD_C,		SEL_MSIOF3_2),
-	PINMUX_IPSR_GPSR(IP3_23_20,	HCTS4_N),
-	PINMUX_IPSR_GPSR(IP3_23_20,	VI5_DATA10),
-	PINMUX_IPSR_GPSR(IP3_23_20,	DU_DG6),
-
-	PINMUX_IPSR_GPSR(IP3_27_24,	A15),
-	PINMUX_IPSR_GPSR(IP3_27_24,	LCDOUT15),
-	PINMUX_IPSR_MSEL(IP3_27_24,	MSIOF3_TXD_C,		SEL_MSIOF3_2),
-	PINMUX_IPSR_GPSR(IP3_27_24,	HRTS4_N),
-	PINMUX_IPSR_GPSR(IP3_27_24,	VI5_DATA11),
-	PINMUX_IPSR_GPSR(IP3_27_24,	DU_DG7),
-
-	PINMUX_IPSR_GPSR(IP3_31_28,	A16),
-	PINMUX_IPSR_GPSR(IP3_31_28,	LCDOUT8),
-	PINMUX_IPSR_GPSR(IP3_31_28,	VI4_FIELD),
-	PINMUX_IPSR_GPSR(IP3_31_28,	DU_DG0),
-
-	/* IPSR4 */
-	PINMUX_IPSR_GPSR(IP4_3_0,	A17),
-	PINMUX_IPSR_GPSR(IP4_3_0,	LCDOUT9),
-	PINMUX_IPSR_GPSR(IP4_3_0,	VI4_VSYNC_N),
-	PINMUX_IPSR_GPSR(IP4_3_0,	DU_DG1),
-
-	PINMUX_IPSR_GPSR(IP4_7_4,	A18),
-	PINMUX_IPSR_GPSR(IP4_7_4,	LCDOUT10),
-	PINMUX_IPSR_GPSR(IP4_7_4,	VI4_HSYNC_N),
-	PINMUX_IPSR_GPSR(IP4_7_4,	DU_DG2),
-
-	PINMUX_IPSR_GPSR(IP4_11_8,	A19),
-	PINMUX_IPSR_GPSR(IP4_11_8,	LCDOUT11),
-	PINMUX_IPSR_GPSR(IP4_11_8,	VI4_CLKENB),
-	PINMUX_IPSR_GPSR(IP4_11_8,	DU_DG3),
-
-	PINMUX_IPSR_GPSR(IP4_15_12,	CS0_N),
-	PINMUX_IPSR_GPSR(IP4_15_12,	VI5_CLKENB),
-
-	PINMUX_IPSR_GPSR(IP4_19_16,	CS1_N_A26),
-	PINMUX_IPSR_GPSR(IP4_19_16,	VI5_CLK),
-	PINMUX_IPSR_MSEL(IP4_19_16,	EX_WAIT0_B,		SEL_LBSC_1),
-
-	PINMUX_IPSR_GPSR(IP4_23_20,	BS_N),
-	PINMUX_IPSR_GPSR(IP4_23_20,	QSTVA_QVS),
-	PINMUX_IPSR_MSEL(IP4_23_20,	MSIOF3_SCK_D,		SEL_MSIOF3_3),
-	PINMUX_IPSR_GPSR(IP4_23_20,	SCK3),
-	PINMUX_IPSR_GPSR(IP4_23_20,	HSCK3),
-	PINMUX_IPSR_GPSR(IP4_23_20,	CAN1_TX),
-	PINMUX_IPSR_GPSR(IP4_23_20,	CANFD1_TX),
-	PINMUX_IPSR_MSEL(IP4_23_20,	IETX_A,			SEL_IEBUS_0),
-
-	PINMUX_IPSR_GPSR(IP4_27_24,	RD_N),
-	PINMUX_IPSR_MSEL(IP4_27_24,	MSIOF3_SYNC_D,		SEL_MSIOF3_3),
-	PINMUX_IPSR_MSEL(IP4_27_24,	RX3_A,			SEL_SCIF3_0),
-	PINMUX_IPSR_MSEL(IP4_27_24,	HRX3_A,			SEL_HSCIF3_0),
-	PINMUX_IPSR_MSEL(IP4_27_24,	CAN0_TX_A,		SEL_RCAN0_0),
-	PINMUX_IPSR_MSEL(IP4_27_24,	CANFD0_TX_A,		SEL_CANFD0_0),
-
-	PINMUX_IPSR_GPSR(IP4_31_28,	RD_WR_N),
-	PINMUX_IPSR_MSEL(IP4_31_28,	MSIOF3_RXD_D,		SEL_MSIOF3_3),
-	PINMUX_IPSR_MSEL(IP4_31_28,	TX3_A,			SEL_SCIF3_0),
-	PINMUX_IPSR_MSEL(IP4_31_28,	HTX3_A,			SEL_HSCIF3_0),
-	PINMUX_IPSR_MSEL(IP4_31_28,	CAN0_RX_A,		SEL_RCAN0_0),
-	PINMUX_IPSR_MSEL(IP4_31_28,	CANFD0_RX_A,		SEL_CANFD0_0),
-
-	/* IPSR5 */
-	PINMUX_IPSR_GPSR(IP5_3_0,	WE0_N),
-	PINMUX_IPSR_MSEL(IP5_3_0,	MSIOF3_TXD_D,		SEL_MSIOF3_3),
-	PINMUX_IPSR_GPSR(IP5_3_0,	CTS3_N),
-	PINMUX_IPSR_GPSR(IP5_3_0,	HCTS3_N),
-	PINMUX_IPSR_MSEL(IP5_3_0,	SCL6_B,			SEL_I2C6_1),
-	PINMUX_IPSR_GPSR(IP5_3_0,	CAN_CLK),
-	PINMUX_IPSR_MSEL(IP5_3_0,	IECLK_A,		SEL_IEBUS_0),
-
-	PINMUX_IPSR_GPSR(IP5_7_4,	WE1_N),
-	PINMUX_IPSR_MSEL(IP5_7_4,	MSIOF3_SS1_D,		SEL_MSIOF3_3),
-	PINMUX_IPSR_GPSR(IP5_7_4,	RTS3_N),
-	PINMUX_IPSR_GPSR(IP5_7_4,	HRTS3_N),
-	PINMUX_IPSR_MSEL(IP5_7_4,	SDA6_B,			SEL_I2C6_1),
-	PINMUX_IPSR_GPSR(IP5_7_4,	CAN1_RX),
-	PINMUX_IPSR_GPSR(IP5_7_4,	CANFD1_RX),
-	PINMUX_IPSR_MSEL(IP5_7_4,	IERX_A,			SEL_IEBUS_0),
-
-	PINMUX_IPSR_MSEL(IP5_11_8,	EX_WAIT0_A,		SEL_LBSC_0),
-	PINMUX_IPSR_GPSR(IP5_11_8,	QCLK),
-	PINMUX_IPSR_GPSR(IP5_11_8,	VI4_CLK),
-	PINMUX_IPSR_GPSR(IP5_11_8,	DU_DOTCLKOUT0),
-
-	PINMUX_IPSR_GPSR(IP5_15_12,	D0),
-	PINMUX_IPSR_MSEL(IP5_15_12,	MSIOF2_SS1_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_MSEL(IP5_15_12,	MSIOF3_SCK_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_GPSR(IP5_15_12,	VI4_DATA16),
-	PINMUX_IPSR_GPSR(IP5_15_12,	VI5_DATA0),
-
-	PINMUX_IPSR_GPSR(IP5_19_16,	D1),
-	PINMUX_IPSR_MSEL(IP5_19_16,	MSIOF2_SS2_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_MSEL(IP5_19_16,	MSIOF3_SYNC_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_GPSR(IP5_19_16,	VI4_DATA17),
-	PINMUX_IPSR_GPSR(IP5_19_16,	VI5_DATA1),
-
-	PINMUX_IPSR_GPSR(IP5_23_20,	D2),
-	PINMUX_IPSR_MSEL(IP5_23_20,	MSIOF3_RXD_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_GPSR(IP5_23_20,	VI4_DATA18),
-	PINMUX_IPSR_GPSR(IP5_23_20,	VI5_DATA2),
-
-	PINMUX_IPSR_GPSR(IP5_27_24,	D3),
-	PINMUX_IPSR_MSEL(IP5_27_24,	MSIOF3_TXD_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_GPSR(IP5_27_24,	VI4_DATA19),
-	PINMUX_IPSR_GPSR(IP5_27_24,	VI5_DATA3),
-
-	PINMUX_IPSR_GPSR(IP5_31_28,	D4),
-	PINMUX_IPSR_MSEL(IP5_31_28,	MSIOF2_SCK_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP5_31_28,	VI4_DATA20),
-	PINMUX_IPSR_GPSR(IP5_31_28,	VI5_DATA4),
-
-	/* IPSR6 */
-	PINMUX_IPSR_GPSR(IP6_3_0,	D5),
-	PINMUX_IPSR_MSEL(IP6_3_0,	MSIOF2_SYNC_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP6_3_0,	VI4_DATA21),
-	PINMUX_IPSR_GPSR(IP6_3_0,	VI5_DATA5),
-
-	PINMUX_IPSR_GPSR(IP6_7_4,	D6),
-	PINMUX_IPSR_MSEL(IP6_7_4,	MSIOF2_RXD_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP6_7_4,	VI4_DATA22),
-	PINMUX_IPSR_GPSR(IP6_7_4,	VI5_DATA6),
-
-	PINMUX_IPSR_GPSR(IP6_11_8,	D7),
-	PINMUX_IPSR_MSEL(IP6_11_8,	MSIOF2_TXD_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP6_11_8,	VI4_DATA23),
-	PINMUX_IPSR_GPSR(IP6_11_8,	VI5_DATA7),
-
-	PINMUX_IPSR_GPSR(IP6_15_12,	D8),
-	PINMUX_IPSR_GPSR(IP6_15_12,	LCDOUT0),
-	PINMUX_IPSR_MSEL(IP6_15_12,	MSIOF2_SCK_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP6_15_12,	SCK4_C,			SEL_SCIF4_2),
-	PINMUX_IPSR_MSEL(IP6_15_12,	VI4_DATA0_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP6_15_12,	DU_DR0),
-
-	PINMUX_IPSR_GPSR(IP6_19_16,	D9),
-	PINMUX_IPSR_GPSR(IP6_19_16,	LCDOUT1),
-	PINMUX_IPSR_MSEL(IP6_19_16,	MSIOF2_SYNC_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP6_19_16,	VI4_DATA1_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP6_19_16,	DU_DR1),
-
-	PINMUX_IPSR_GPSR(IP6_23_20,	D10),
-	PINMUX_IPSR_GPSR(IP6_23_20,	LCDOUT2),
-	PINMUX_IPSR_MSEL(IP6_23_20,	MSIOF2_RXD_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP6_23_20,	HRX3_B,			SEL_HSCIF3_1),
-	PINMUX_IPSR_MSEL(IP6_23_20,	VI4_DATA2_A,		SEL_VIN4_0),
-	PINMUX_IPSR_MSEL(IP6_23_20,	CTS4_N_C,		SEL_SCIF4_2),
-	PINMUX_IPSR_GPSR(IP6_23_20,	DU_DR2),
-
-	PINMUX_IPSR_GPSR(IP6_27_24,	D11),
-	PINMUX_IPSR_GPSR(IP6_27_24,	LCDOUT3),
-	PINMUX_IPSR_MSEL(IP6_27_24,	MSIOF2_TXD_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP6_27_24,	HTX3_B,			SEL_HSCIF3_1),
-	PINMUX_IPSR_MSEL(IP6_27_24,	VI4_DATA3_A,		SEL_VIN4_0),
-	PINMUX_IPSR_MSEL(IP6_27_24,	RTS4_N_C,		SEL_SCIF4_2),
-	PINMUX_IPSR_GPSR(IP6_27_24,	DU_DR3),
-
-	PINMUX_IPSR_GPSR(IP6_31_28,	D12),
-	PINMUX_IPSR_GPSR(IP6_31_28,	LCDOUT4),
-	PINMUX_IPSR_MSEL(IP6_31_28,	MSIOF2_SS1_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP6_31_28,	RX4_C,			SEL_SCIF4_2),
-	PINMUX_IPSR_MSEL(IP6_31_28,	VI4_DATA4_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP6_31_28,	DU_DR4),
-
-	/* IPSR7 */
-	PINMUX_IPSR_GPSR(IP7_3_0,	D13),
-	PINMUX_IPSR_GPSR(IP7_3_0,	LCDOUT5),
-	PINMUX_IPSR_MSEL(IP7_3_0,	MSIOF2_SS2_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP7_3_0,	TX4_C,			SEL_SCIF4_2),
-	PINMUX_IPSR_MSEL(IP7_3_0,	VI4_DATA5_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP7_3_0,	DU_DR5),
-
-	PINMUX_IPSR_GPSR(IP7_7_4,	D14),
-	PINMUX_IPSR_GPSR(IP7_7_4,	LCDOUT6),
-	PINMUX_IPSR_MSEL(IP7_7_4,	MSIOF3_SS1_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_MSEL(IP7_7_4,	HRX3_C,			SEL_HSCIF3_2),
-	PINMUX_IPSR_MSEL(IP7_7_4,	VI4_DATA6_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP7_7_4,	DU_DR6),
-	PINMUX_IPSR_MSEL(IP7_7_4,	SCL6_C,			SEL_I2C6_2),
-
-	PINMUX_IPSR_GPSR(IP7_11_8,	D15),
-	PINMUX_IPSR_GPSR(IP7_11_8,	LCDOUT7),
-	PINMUX_IPSR_MSEL(IP7_11_8,	MSIOF3_SS2_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_MSEL(IP7_11_8,	HTX3_C,			SEL_HSCIF3_2),
-	PINMUX_IPSR_MSEL(IP7_11_8,	VI4_DATA7_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP7_11_8,	DU_DR7),
-	PINMUX_IPSR_MSEL(IP7_11_8,	SDA6_C,			SEL_I2C6_2),
-
-	PINMUX_IPSR_GPSR(IP7_15_12,	FSCLKST),
-
-	PINMUX_IPSR_GPSR(IP7_19_16,	SD0_CLK),
-	PINMUX_IPSR_MSEL(IP7_19_16,	MSIOF1_SCK_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP7_19_16,	STP_OPWM_0_B,		SEL_SSP1_0_1),
-
-	PINMUX_IPSR_GPSR(IP7_23_20,	SD0_CMD),
-	PINMUX_IPSR_MSEL(IP7_23_20,	MSIOF1_SYNC_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP7_23_20,	STP_IVCXO27_0_B,	SEL_SSP1_0_1),
-
-	PINMUX_IPSR_GPSR(IP7_27_24,	SD0_DAT0),
-	PINMUX_IPSR_MSEL(IP7_27_24,	MSIOF1_RXD_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP7_27_24,	TS_SCK0_B,		SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP7_27_24,	STP_ISCLK_0_B,		SEL_SSP1_0_1),
-
-	PINMUX_IPSR_GPSR(IP7_31_28,	SD0_DAT1),
-	PINMUX_IPSR_MSEL(IP7_31_28,	MSIOF1_TXD_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP7_31_28,	TS_SPSYNC0_B,		SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP7_31_28,	STP_ISSYNC_0_B,		SEL_SSP1_0_1),
-
-	/* IPSR8 */
-	PINMUX_IPSR_GPSR(IP8_3_0,	SD0_DAT2),
-	PINMUX_IPSR_MSEL(IP8_3_0,	MSIOF1_SS1_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP8_3_0,	TS_SDAT0_B,		SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP8_3_0,	STP_ISD_0_B,		SEL_SSP1_0_1),
-
-	PINMUX_IPSR_GPSR(IP8_7_4,	SD0_DAT3),
-	PINMUX_IPSR_MSEL(IP8_7_4,	MSIOF1_SS2_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP8_7_4,	TS_SDEN0_B,		SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP8_7_4,	STP_ISEN_0_B,		SEL_SSP1_0_1),
-
-	PINMUX_IPSR_GPSR(IP8_11_8,	SD1_CLK),
-	PINMUX_IPSR_MSEL(IP8_11_8,	MSIOF1_SCK_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_MSEL(IP8_11_8,	SIM0_CLK_A,		SEL_SIMCARD_0),
-
-	PINMUX_IPSR_GPSR(IP8_15_12,	SD1_CMD),
-	PINMUX_IPSR_MSEL(IP8_15_12,	MSIOF1_SYNC_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_MSEL(IP8_15_12,	SIM0_D_A,		SEL_SIMCARD_0),
-	PINMUX_IPSR_MSEL(IP8_15_12,	STP_IVCXO27_1_B,	SEL_SSP1_1_1),
-
-	PINMUX_IPSR_GPSR(IP8_19_16,	SD1_DAT0),
-	PINMUX_IPSR_GPSR(IP8_19_16,	SD2_DAT4),
-	PINMUX_IPSR_MSEL(IP8_19_16,	MSIOF1_RXD_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_MSEL(IP8_19_16,	TS_SCK1_B,		SEL_TSIF1_1),
-	PINMUX_IPSR_MSEL(IP8_19_16,	STP_ISCLK_1_B,		SEL_SSP1_1_1),
-
-	PINMUX_IPSR_GPSR(IP8_23_20,	SD1_DAT1),
-	PINMUX_IPSR_GPSR(IP8_23_20,	SD2_DAT5),
-	PINMUX_IPSR_MSEL(IP8_23_20,	MSIOF1_TXD_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_MSEL(IP8_23_20,	TS_SPSYNC1_B,		SEL_TSIF1_1),
-	PINMUX_IPSR_MSEL(IP8_23_20,	STP_ISSYNC_1_B,		SEL_SSP1_1_1),
-
-	PINMUX_IPSR_GPSR(IP8_27_24,	SD1_DAT2),
-	PINMUX_IPSR_GPSR(IP8_27_24,	SD2_DAT6),
-	PINMUX_IPSR_MSEL(IP8_27_24,	MSIOF1_SS1_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_MSEL(IP8_27_24,	TS_SDAT1_B,		SEL_TSIF1_1),
-	PINMUX_IPSR_MSEL(IP8_27_24,	STP_ISD_1_B,		SEL_SSP1_1_1),
-
-	PINMUX_IPSR_GPSR(IP8_31_28,	SD1_DAT3),
-	PINMUX_IPSR_GPSR(IP8_31_28,	SD2_DAT7),
-	PINMUX_IPSR_MSEL(IP8_31_28,	MSIOF1_SS2_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_MSEL(IP8_31_28,	TS_SDEN1_B,		SEL_TSIF1_1),
-	PINMUX_IPSR_MSEL(IP8_31_28,	STP_ISEN_1_B,		SEL_SSP1_1_1),
-
-	/* IPSR9 */
-	PINMUX_IPSR_GPSR(IP9_3_0,	SD2_CLK),
-
-	PINMUX_IPSR_GPSR(IP9_7_4,	SD2_DAT0),
-
-	PINMUX_IPSR_GPSR(IP9_11_8,	SD2_DAT1),
-
-	PINMUX_IPSR_GPSR(IP9_15_12,	SD2_DAT2),
-
-	PINMUX_IPSR_GPSR(IP9_19_16,	SD2_DAT3),
-
-	PINMUX_IPSR_GPSR(IP9_23_20,	SD2_DS),
-	PINMUX_IPSR_MSEL(IP9_23_20,	SATA_DEVSLP_B,		SEL_SATA_1),
-
-	PINMUX_IPSR_GPSR(IP9_27_24,	SD3_DAT4),
-	PINMUX_IPSR_MSEL(IP9_27_24,	SD2_CD_A,		SEL_SDHI2_0),
-
-	PINMUX_IPSR_GPSR(IP9_31_28,	SD3_DAT5),
-	PINMUX_IPSR_MSEL(IP9_31_28,	SD2_WP_A,		SEL_SDHI2_0),
-
-	/* IPSR10 */
-	PINMUX_IPSR_GPSR(IP10_3_0,	SD3_DAT6),
-	PINMUX_IPSR_GPSR(IP10_3_0,	SD3_CD),
-
-	PINMUX_IPSR_GPSR(IP10_7_4,	SD3_DAT7),
-	PINMUX_IPSR_GPSR(IP10_7_4,	SD3_WP),
-
-	PINMUX_IPSR_GPSR(IP10_11_8,	SD0_CD),
-	PINMUX_IPSR_MSEL(IP10_11_8,	SCL2_B,			SEL_I2C2_1),
-	PINMUX_IPSR_MSEL(IP10_11_8,	SIM0_RST_A,		SEL_SIMCARD_0),
-
-	PINMUX_IPSR_GPSR(IP10_15_12,	SD0_WP),
-	PINMUX_IPSR_MSEL(IP10_15_12,	SDA2_B,			SEL_I2C2_1),
-
-	PINMUX_IPSR_MSEL(IP10_19_16,	SD1_CD,			I2C_SEL_0_0),
-	PINMUX_IPSR_PHYS_MSEL(IP10_19_16, SIM0_CLK_B,		I2C_SEL_0_0,	SEL_SIMCARD_1),
-	PINMUX_IPSR_PHYS(IP10_19_16,	SCL0,			I2C_SEL_0_1),
-
-	PINMUX_IPSR_MSEL(IP10_23_20,	SD1_WP,			I2C_SEL_0_0),
-	PINMUX_IPSR_PHYS_MSEL(IP10_23_20, SIM0_D_B,		I2C_SEL_0_0,	SEL_SIMCARD_1),
-	PINMUX_IPSR_PHYS(IP10_23_20,	SDA0,			I2C_SEL_0_1),
-
-	PINMUX_IPSR_GPSR(IP10_27_24,	SCK0),
-	PINMUX_IPSR_MSEL(IP10_27_24,	HSCK1_B,		SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP10_27_24,	MSIOF1_SS2_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP10_27_24,	AUDIO_CLKC_B,		SEL_ADG_1),
-	PINMUX_IPSR_MSEL(IP10_27_24,	SDA2_A,			SEL_I2C2_0),
-	PINMUX_IPSR_MSEL(IP10_27_24,	SIM0_RST_B,		SEL_SIMCARD_1),
-	PINMUX_IPSR_MSEL(IP10_27_24,	STP_OPWM_0_C,		SEL_SSP1_0_2),
-	PINMUX_IPSR_MSEL(IP10_27_24,	RIF0_CLK_B,		SEL_DRIF0_1),
-	PINMUX_IPSR_GPSR(IP10_27_24,	ADICHS2),
-
-	PINMUX_IPSR_GPSR(IP10_31_28,	RX0),
-	PINMUX_IPSR_MSEL(IP10_31_28,	HRX1_B,			SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP10_31_28,	TS_SCK0_C,		SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP10_31_28,	STP_ISCLK_0_C,		SEL_SSP1_0_2),
-	PINMUX_IPSR_MSEL(IP10_31_28,	RIF0_D0_B,		SEL_DRIF0_1),
-
-	/* IPSR11 */
-	PINMUX_IPSR_GPSR(IP11_3_0,	TX0),
-	PINMUX_IPSR_MSEL(IP11_3_0,	HTX1_B,			SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP11_3_0,	TS_SPSYNC0_C,		SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP11_3_0,	STP_ISSYNC_0_C,		SEL_SSP1_0_2),
-	PINMUX_IPSR_MSEL(IP11_3_0,	RIF0_D1_B,		SEL_DRIF0_1),
-
-	PINMUX_IPSR_GPSR(IP11_7_4,	CTS0_N),
-	PINMUX_IPSR_MSEL(IP11_7_4,	HCTS1_N_B,		SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP11_7_4,	MSIOF1_SYNC_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP11_7_4,	TS_SPSYNC1_C,		SEL_TSIF1_2),
-	PINMUX_IPSR_MSEL(IP11_7_4,	STP_ISSYNC_1_C,		SEL_SSP1_1_2),
-	PINMUX_IPSR_MSEL(IP11_7_4,	RIF1_SYNC_B,		SEL_DRIF1_1),
-	PINMUX_IPSR_MSEL(IP11_7_4,	AUDIO_CLKOUT_C,		SEL_ADG_2),
-	PINMUX_IPSR_GPSR(IP11_7_4,	ADICS_SAMP),
-
-	PINMUX_IPSR_GPSR(IP11_11_8,	RTS0_N),
-	PINMUX_IPSR_MSEL(IP11_11_8,	HRTS1_N_B,		SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP11_11_8,	MSIOF1_SS1_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP11_11_8,	AUDIO_CLKA_B,		SEL_ADG_1),
-	PINMUX_IPSR_MSEL(IP11_11_8,	SCL2_A,			SEL_I2C2_0),
-	PINMUX_IPSR_MSEL(IP11_11_8,	STP_IVCXO27_1_C,	SEL_SSP1_1_2),
-	PINMUX_IPSR_MSEL(IP11_11_8,	RIF0_SYNC_B,		SEL_DRIF0_1),
-	PINMUX_IPSR_GPSR(IP11_11_8,	ADICHS1),
-
-	PINMUX_IPSR_MSEL(IP11_15_12,	RX1_A,			SEL_SCIF1_0),
-	PINMUX_IPSR_MSEL(IP11_15_12,	HRX1_A,			SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP11_15_12,	TS_SDAT0_C,		SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP11_15_12,	STP_ISD_0_C,		SEL_SSP1_0_2),
-	PINMUX_IPSR_MSEL(IP11_15_12,	RIF1_CLK_C,		SEL_DRIF1_2),
-
-	PINMUX_IPSR_MSEL(IP11_19_16,	TX1_A,			SEL_SCIF1_0),
-	PINMUX_IPSR_MSEL(IP11_19_16,	HTX1_A,			SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP11_19_16,	TS_SDEN0_C,		SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP11_19_16,	STP_ISEN_0_C,		SEL_SSP1_0_2),
-	PINMUX_IPSR_MSEL(IP11_19_16,	RIF1_D0_C,		SEL_DRIF1_2),
-
-	PINMUX_IPSR_GPSR(IP11_23_20,	CTS1_N),
-	PINMUX_IPSR_MSEL(IP11_23_20,	HCTS1_N_A,		SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP11_23_20,	MSIOF1_RXD_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP11_23_20,	TS_SDEN1_C,		SEL_TSIF1_2),
-	PINMUX_IPSR_MSEL(IP11_23_20,	STP_ISEN_1_C,		SEL_SSP1_1_2),
-	PINMUX_IPSR_MSEL(IP11_23_20,	RIF1_D0_B,		SEL_DRIF1_1),
-	PINMUX_IPSR_GPSR(IP11_23_20,	ADIDATA),
-
-	PINMUX_IPSR_GPSR(IP11_27_24,	RTS1_N),
-	PINMUX_IPSR_MSEL(IP11_27_24,	HRTS1_N_A,		SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP11_27_24,	MSIOF1_TXD_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP11_27_24,	TS_SDAT1_C,		SEL_TSIF1_2),
-	PINMUX_IPSR_MSEL(IP11_27_24,	STP_ISD_1_C,		SEL_SSP1_1_2),
-	PINMUX_IPSR_MSEL(IP11_27_24,	RIF1_D1_B,		SEL_DRIF1_1),
-	PINMUX_IPSR_GPSR(IP11_27_24,	ADICHS0),
-
-	PINMUX_IPSR_GPSR(IP11_31_28,	SCK2),
-	PINMUX_IPSR_MSEL(IP11_31_28,	SCIF_CLK_B,		SEL_SCIF1_1),
-	PINMUX_IPSR_MSEL(IP11_31_28,	MSIOF1_SCK_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP11_31_28,	TS_SCK1_C,		SEL_TSIF1_2),
-	PINMUX_IPSR_MSEL(IP11_31_28,	STP_ISCLK_1_C,		SEL_SSP1_1_2),
-	PINMUX_IPSR_MSEL(IP11_31_28,	RIF1_CLK_B,		SEL_DRIF1_1),
-	PINMUX_IPSR_GPSR(IP11_31_28,	ADICLK),
-
-	/* IPSR12 */
-	PINMUX_IPSR_MSEL(IP12_3_0,	TX2_A,			SEL_SCIF2_0),
-	PINMUX_IPSR_MSEL(IP12_3_0,	SD2_CD_B,		SEL_SDHI2_1),
-	PINMUX_IPSR_MSEL(IP12_3_0,	SCL1_A,			SEL_I2C1_0),
-	PINMUX_IPSR_MSEL(IP12_3_0,	FMCLK_A,		SEL_FM_0),
-	PINMUX_IPSR_MSEL(IP12_3_0,	RIF1_D1_C,		SEL_DRIF1_2),
-	PINMUX_IPSR_MSEL(IP12_3_0,	FSO_CFE_0_B,		SEL_FSO_1),
-
-	PINMUX_IPSR_MSEL(IP12_7_4,	RX2_A,			SEL_SCIF2_0),
-	PINMUX_IPSR_MSEL(IP12_7_4,	SD2_WP_B,		SEL_SDHI2_1),
-	PINMUX_IPSR_MSEL(IP12_7_4,	SDA1_A,			SEL_I2C1_0),
-	PINMUX_IPSR_MSEL(IP12_7_4,	FMIN_A,			SEL_FM_0),
-	PINMUX_IPSR_MSEL(IP12_7_4,	RIF1_SYNC_C,		SEL_DRIF1_2),
-	PINMUX_IPSR_MSEL(IP12_7_4,	FSO_CFE_1_B,		SEL_FSO_1),
-
-	PINMUX_IPSR_GPSR(IP12_11_8,	HSCK0),
-	PINMUX_IPSR_MSEL(IP12_11_8,	MSIOF1_SCK_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP12_11_8,	AUDIO_CLKB_A,		SEL_ADG_0),
-	PINMUX_IPSR_MSEL(IP12_11_8,	SSI_SDATA1_B,		SEL_SSI_1),
-	PINMUX_IPSR_MSEL(IP12_11_8,	TS_SCK0_D,		SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP12_11_8,	STP_ISCLK_0_D,		SEL_SSP1_0_3),
-	PINMUX_IPSR_MSEL(IP12_11_8,	RIF0_CLK_C,		SEL_DRIF0_2),
-
-	PINMUX_IPSR_GPSR(IP12_15_12,	HRX0),
-	PINMUX_IPSR_MSEL(IP12_15_12,	MSIOF1_RXD_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP12_15_12,	SSI_SDATA2_B,		SEL_SSI_1),
-	PINMUX_IPSR_MSEL(IP12_15_12,	TS_SDEN0_D,		SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP12_15_12,	STP_ISEN_0_D,		SEL_SSP1_0_3),
-	PINMUX_IPSR_MSEL(IP12_15_12,	RIF0_D0_C,		SEL_DRIF0_2),
-
-	PINMUX_IPSR_GPSR(IP12_19_16,	HTX0),
-	PINMUX_IPSR_MSEL(IP12_19_16,	MSIOF1_TXD_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP12_19_16,	SSI_SDATA9_B,		SEL_SSI_1),
-	PINMUX_IPSR_MSEL(IP12_19_16,	TS_SDAT0_D,		SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP12_19_16,	STP_ISD_0_D,		SEL_SSP1_0_3),
-	PINMUX_IPSR_MSEL(IP12_19_16,	RIF0_D1_C,		SEL_DRIF0_2),
-
-	PINMUX_IPSR_GPSR(IP12_23_20,	HCTS0_N),
-	PINMUX_IPSR_MSEL(IP12_23_20,	RX2_B,			SEL_SCIF2_1),
-	PINMUX_IPSR_MSEL(IP12_23_20,	MSIOF1_SYNC_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP12_23_20,	SSI_SCK9_A,		SEL_SSI_0),
-	PINMUX_IPSR_MSEL(IP12_23_20,	TS_SPSYNC0_D,		SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP12_23_20,	STP_ISSYNC_0_D,		SEL_SSP1_0_3),
-	PINMUX_IPSR_MSEL(IP12_23_20,	RIF0_SYNC_C,		SEL_DRIF0_2),
-	PINMUX_IPSR_MSEL(IP12_23_20,	AUDIO_CLKOUT1_A,	SEL_ADG_0),
-
-	PINMUX_IPSR_GPSR(IP12_27_24,	HRTS0_N),
-	PINMUX_IPSR_MSEL(IP12_27_24,	TX2_B,			SEL_SCIF2_1),
-	PINMUX_IPSR_MSEL(IP12_27_24,	MSIOF1_SS1_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP12_27_24,	SSI_WS9_A,		SEL_SSI_0),
-	PINMUX_IPSR_MSEL(IP12_27_24,	STP_IVCXO27_0_D,	SEL_SSP1_0_3),
-	PINMUX_IPSR_MSEL(IP12_27_24,	BPFCLK_A,		SEL_FM_0),
-	PINMUX_IPSR_MSEL(IP12_27_24,	AUDIO_CLKOUT2_A,	SEL_ADG_0),
-
-	PINMUX_IPSR_GPSR(IP12_31_28,	MSIOF0_SYNC),
-	PINMUX_IPSR_MSEL(IP12_31_28,	AUDIO_CLKOUT_A,		SEL_ADG_0),
-
-	/* IPSR13 */
-	PINMUX_IPSR_GPSR(IP13_3_0,	MSIOF0_SS1),
-	PINMUX_IPSR_GPSR(IP13_3_0,	RX5),
-	PINMUX_IPSR_MSEL(IP13_3_0,	AUDIO_CLKA_C,		SEL_ADG_2),
-	PINMUX_IPSR_MSEL(IP13_3_0,	SSI_SCK2_A,		SEL_SSI_0),
-	PINMUX_IPSR_MSEL(IP13_3_0,	STP_IVCXO27_0_C,	SEL_SSP1_0_2),
-	PINMUX_IPSR_MSEL(IP13_3_0,	AUDIO_CLKOUT3_A,	SEL_ADG_0),
-	PINMUX_IPSR_MSEL(IP13_3_0,	TCLK1_B,		SEL_TIMER_TMU_1),
-
-	PINMUX_IPSR_GPSR(IP13_7_4,	MSIOF0_SS2),
-	PINMUX_IPSR_GPSR(IP13_7_4,	TX5),
-	PINMUX_IPSR_MSEL(IP13_7_4,	MSIOF1_SS2_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP13_7_4,	AUDIO_CLKC_A,		SEL_ADG_0),
-	PINMUX_IPSR_MSEL(IP13_7_4,	SSI_WS2_A,		SEL_SSI_0),
-	PINMUX_IPSR_MSEL(IP13_7_4,	STP_OPWM_0_D,		SEL_SSP1_0_3),
-	PINMUX_IPSR_MSEL(IP13_7_4,	AUDIO_CLKOUT_D,		SEL_ADG_3),
-	PINMUX_IPSR_MSEL(IP13_7_4,	SPEEDIN_B,		SEL_SPEED_PULSE_1),
-
-	PINMUX_IPSR_GPSR(IP13_11_8,	MLB_CLK),
-	PINMUX_IPSR_MSEL(IP13_11_8,	MSIOF1_SCK_F,		SEL_MSIOF1_5),
-	PINMUX_IPSR_MSEL(IP13_11_8,	SCL1_B,			SEL_I2C1_1),
-
-	PINMUX_IPSR_GPSR(IP13_15_12,	MLB_SIG),
-	PINMUX_IPSR_MSEL(IP13_15_12,	RX1_B,			SEL_SCIF1_1),
-	PINMUX_IPSR_MSEL(IP13_15_12,	MSIOF1_SYNC_F,		SEL_MSIOF1_5),
-	PINMUX_IPSR_MSEL(IP13_15_12,	SDA1_B,			SEL_I2C1_1),
-
-	PINMUX_IPSR_GPSR(IP13_19_16,	MLB_DAT),
-	PINMUX_IPSR_MSEL(IP13_19_16,	TX1_B,			SEL_SCIF1_1),
-	PINMUX_IPSR_MSEL(IP13_19_16,	MSIOF1_RXD_F,		SEL_MSIOF1_5),
-
-	PINMUX_IPSR_GPSR(IP13_23_20,	SSI_SCK01239),
-	PINMUX_IPSR_MSEL(IP13_23_20,	MSIOF1_TXD_F,		SEL_MSIOF1_5),
-
-	PINMUX_IPSR_GPSR(IP13_27_24,	SSI_WS01239),
-	PINMUX_IPSR_MSEL(IP13_27_24,	MSIOF1_SS1_F,		SEL_MSIOF1_5),
-
-	PINMUX_IPSR_GPSR(IP13_31_28,	SSI_SDATA0),
-	PINMUX_IPSR_MSEL(IP13_31_28,	MSIOF1_SS2_F,		SEL_MSIOF1_5),
-
-	/* IPSR14 */
-	PINMUX_IPSR_MSEL(IP14_3_0,	SSI_SDATA1_A,		SEL_SSI_0),
-
-	PINMUX_IPSR_MSEL(IP14_7_4,	SSI_SDATA2_A,		SEL_SSI_0),
-	PINMUX_IPSR_MSEL(IP14_7_4,	SSI_SCK1_B,		SEL_SSI_1),
-
-	PINMUX_IPSR_GPSR(IP14_11_8,	SSI_SCK349),
-	PINMUX_IPSR_MSEL(IP14_11_8,	MSIOF1_SS1_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP14_11_8,	STP_OPWM_0_A,		SEL_SSP1_0_0),
-
-	PINMUX_IPSR_GPSR(IP14_15_12,	SSI_WS349),
-	PINMUX_IPSR_MSEL(IP14_15_12,	HCTS2_N_A,		SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP14_15_12,	MSIOF1_SS2_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP14_15_12,	STP_IVCXO27_0_A,	SEL_SSP1_0_0),
-
-	PINMUX_IPSR_GPSR(IP14_19_16,	SSI_SDATA3),
-	PINMUX_IPSR_MSEL(IP14_19_16,	HRTS2_N_A,		SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP14_19_16,	MSIOF1_TXD_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP14_19_16,	TS_SCK0_A,		SEL_TSIF0_0),
-	PINMUX_IPSR_MSEL(IP14_19_16,	STP_ISCLK_0_A,		SEL_SSP1_0_0),
-	PINMUX_IPSR_MSEL(IP14_19_16,	RIF0_D1_A,		SEL_DRIF0_0),
-	PINMUX_IPSR_MSEL(IP14_19_16,	RIF2_D0_A,		SEL_DRIF2_0),
-
-	PINMUX_IPSR_GPSR(IP14_23_20,	SSI_SCK4),
-	PINMUX_IPSR_MSEL(IP14_23_20,	HRX2_A,			SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP14_23_20,	MSIOF1_SCK_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP14_23_20,	TS_SDAT0_A,		SEL_TSIF0_0),
-	PINMUX_IPSR_MSEL(IP14_23_20,	STP_ISD_0_A,		SEL_SSP1_0_0),
-	PINMUX_IPSR_MSEL(IP14_23_20,	RIF0_CLK_A,		SEL_DRIF0_0),
-	PINMUX_IPSR_MSEL(IP14_23_20,	RIF2_CLK_A,		SEL_DRIF2_0),
-
-	PINMUX_IPSR_GPSR(IP14_27_24,	SSI_WS4),
-	PINMUX_IPSR_MSEL(IP14_27_24,	HTX2_A,			SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP14_27_24,	MSIOF1_SYNC_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP14_27_24,	TS_SDEN0_A,		SEL_TSIF0_0),
-	PINMUX_IPSR_MSEL(IP14_27_24,	STP_ISEN_0_A,		SEL_SSP1_0_0),
-	PINMUX_IPSR_MSEL(IP14_27_24,	RIF0_SYNC_A,		SEL_DRIF0_0),
-	PINMUX_IPSR_MSEL(IP14_27_24,	RIF2_SYNC_A,		SEL_DRIF2_0),
-
-	PINMUX_IPSR_GPSR(IP14_31_28,	SSI_SDATA4),
-	PINMUX_IPSR_MSEL(IP14_31_28,	HSCK2_A,		SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP14_31_28,	MSIOF1_RXD_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP14_31_28,	TS_SPSYNC0_A,		SEL_TSIF0_0),
-	PINMUX_IPSR_MSEL(IP14_31_28,	STP_ISSYNC_0_A,		SEL_SSP1_0_0),
-	PINMUX_IPSR_MSEL(IP14_31_28,	RIF0_D0_A,		SEL_DRIF0_0),
-	PINMUX_IPSR_MSEL(IP14_31_28,	RIF2_D1_A,		SEL_DRIF2_0),
-
-	/* IPSR15 */
-	PINMUX_IPSR_GPSR(IP15_3_0,	SSI_SCK6),
-	PINMUX_IPSR_GPSR(IP15_3_0,	USB2_PWEN),
-	PINMUX_IPSR_MSEL(IP15_3_0,	SIM0_RST_D,		SEL_SIMCARD_3),
-
-	PINMUX_IPSR_GPSR(IP15_7_4,	SSI_WS6),
-	PINMUX_IPSR_GPSR(IP15_7_4,	USB2_OVC),
-	PINMUX_IPSR_MSEL(IP15_7_4,	SIM0_D_D,		SEL_SIMCARD_3),
-
-	PINMUX_IPSR_GPSR(IP15_11_8,	SSI_SDATA6),
-	PINMUX_IPSR_MSEL(IP15_11_8,	SIM0_CLK_D,		SEL_SIMCARD_3),
-	PINMUX_IPSR_MSEL(IP15_11_8,	SATA_DEVSLP_A,		SEL_SATA_0),
-
-	PINMUX_IPSR_GPSR(IP15_15_12,	SSI_SCK78),
-	PINMUX_IPSR_MSEL(IP15_15_12,	HRX2_B,			SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP15_15_12,	MSIOF1_SCK_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP15_15_12,	TS_SCK1_A,		SEL_TSIF1_0),
-	PINMUX_IPSR_MSEL(IP15_15_12,	STP_ISCLK_1_A,		SEL_SSP1_1_0),
-	PINMUX_IPSR_MSEL(IP15_15_12,	RIF1_CLK_A,		SEL_DRIF1_0),
-	PINMUX_IPSR_MSEL(IP15_15_12,	RIF3_CLK_A,		SEL_DRIF3_0),
-
-	PINMUX_IPSR_GPSR(IP15_19_16,	SSI_WS78),
-	PINMUX_IPSR_MSEL(IP15_19_16,	HTX2_B,			SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP15_19_16,	MSIOF1_SYNC_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP15_19_16,	TS_SDAT1_A,		SEL_TSIF1_0),
-	PINMUX_IPSR_MSEL(IP15_19_16,	STP_ISD_1_A,		SEL_SSP1_1_0),
-	PINMUX_IPSR_MSEL(IP15_19_16,	RIF1_SYNC_A,		SEL_DRIF1_0),
-	PINMUX_IPSR_MSEL(IP15_19_16,	RIF3_SYNC_A,		SEL_DRIF3_0),
-
-	PINMUX_IPSR_GPSR(IP15_23_20,	SSI_SDATA7),
-	PINMUX_IPSR_MSEL(IP15_23_20,	HCTS2_N_B,		SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP15_23_20,	MSIOF1_RXD_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP15_23_20,	TS_SDEN1_A,		SEL_TSIF1_0),
-	PINMUX_IPSR_MSEL(IP15_23_20,	STP_ISEN_1_A,		SEL_SSP1_1_0),
-	PINMUX_IPSR_MSEL(IP15_23_20,	RIF1_D0_A,		SEL_DRIF1_0),
-	PINMUX_IPSR_MSEL(IP15_23_20,	RIF3_D0_A,		SEL_DRIF3_0),
-	PINMUX_IPSR_MSEL(IP15_23_20,	TCLK2_A,		SEL_TIMER_TMU_0),
-
-	PINMUX_IPSR_GPSR(IP15_27_24,	SSI_SDATA8),
-	PINMUX_IPSR_MSEL(IP15_27_24,	HRTS2_N_B,		SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP15_27_24,	MSIOF1_TXD_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP15_27_24,	TS_SPSYNC1_A,		SEL_TSIF1_0),
-	PINMUX_IPSR_MSEL(IP15_27_24,	STP_ISSYNC_1_A,		SEL_SSP1_1_0),
-	PINMUX_IPSR_MSEL(IP15_27_24,	RIF1_D1_A,		SEL_DRIF1_0),
-	PINMUX_IPSR_MSEL(IP15_27_24,	RIF3_D1_A,		SEL_DRIF3_0),
-
-	PINMUX_IPSR_MSEL(IP15_31_28,	SSI_SDATA9_A,		SEL_SSI_0),
-	PINMUX_IPSR_MSEL(IP15_31_28,	HSCK2_B,		SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP15_31_28,	MSIOF1_SS1_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP15_31_28,	HSCK1_A,		SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP15_31_28,	SSI_WS1_B,		SEL_SSI_1),
-	PINMUX_IPSR_GPSR(IP15_31_28,	SCK1),
-	PINMUX_IPSR_MSEL(IP15_31_28,	STP_IVCXO27_1_A,	SEL_SSP1_1_0),
-	PINMUX_IPSR_GPSR(IP15_31_28,	SCK5),
-
-	/* IPSR16 */
-	PINMUX_IPSR_MSEL(IP16_3_0,	AUDIO_CLKA_A,		SEL_ADG_0),
-
-	PINMUX_IPSR_MSEL(IP16_7_4,	AUDIO_CLKB_B,		SEL_ADG_1),
-	PINMUX_IPSR_MSEL(IP16_7_4,	SCIF_CLK_A,		SEL_SCIF1_0),
-	PINMUX_IPSR_MSEL(IP16_7_4,	STP_IVCXO27_1_D,	SEL_SSP1_1_3),
-	PINMUX_IPSR_MSEL(IP16_7_4,	REMOCON_A,		SEL_REMOCON_0),
-	PINMUX_IPSR_MSEL(IP16_7_4,	TCLK1_A,		SEL_TIMER_TMU_0),
-
-	PINMUX_IPSR_GPSR(IP16_11_8,	USB0_PWEN),
-	PINMUX_IPSR_MSEL(IP16_11_8,	SIM0_RST_C,		SEL_SIMCARD_2),
-	PINMUX_IPSR_MSEL(IP16_11_8,	TS_SCK1_D,		SEL_TSIF1_3),
-	PINMUX_IPSR_MSEL(IP16_11_8,	STP_ISCLK_1_D,		SEL_SSP1_1_3),
-	PINMUX_IPSR_MSEL(IP16_11_8,	BPFCLK_B,		SEL_FM_1),
-	PINMUX_IPSR_MSEL(IP16_11_8,	RIF3_CLK_B,		SEL_DRIF3_1),
-
-	PINMUX_IPSR_GPSR(IP16_15_12,	USB0_OVC),
-	PINMUX_IPSR_MSEL(IP16_11_8,	SIM0_D_C,		SEL_SIMCARD_2),
-	PINMUX_IPSR_MSEL(IP16_11_8,	TS_SDAT1_D,		SEL_TSIF1_3),
-	PINMUX_IPSR_MSEL(IP16_11_8,	STP_ISD_1_D,		SEL_SSP1_1_3),
-	PINMUX_IPSR_MSEL(IP16_11_8,	RIF3_SYNC_B,		SEL_DRIF3_1),
-
-	PINMUX_IPSR_GPSR(IP16_19_16,	USB1_PWEN),
-	PINMUX_IPSR_MSEL(IP16_19_16,	SIM0_CLK_C,		SEL_SIMCARD_2),
-	PINMUX_IPSR_MSEL(IP16_19_16,	SSI_SCK1_A,		SEL_SSI_0),
-	PINMUX_IPSR_MSEL(IP16_19_16,	TS_SCK0_E,		SEL_TSIF0_4),
-	PINMUX_IPSR_MSEL(IP16_19_16,	STP_ISCLK_0_E,		SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP16_19_16,	FMCLK_B,		SEL_FM_1),
-	PINMUX_IPSR_MSEL(IP16_19_16,	RIF2_CLK_B,		SEL_DRIF2_1),
-	PINMUX_IPSR_MSEL(IP16_19_16,	SPEEDIN_A,		SEL_SPEED_PULSE_0),
-
-	PINMUX_IPSR_GPSR(IP16_23_20,	USB1_OVC),
-	PINMUX_IPSR_MSEL(IP16_23_20,	MSIOF1_SS2_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP16_23_20,	SSI_WS1_A,		SEL_SSI_0),
-	PINMUX_IPSR_MSEL(IP16_23_20,	TS_SDAT0_E,		SEL_TSIF0_4),
-	PINMUX_IPSR_MSEL(IP16_23_20,	STP_ISD_0_E,		SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP16_23_20,	FMIN_B,			SEL_FM_1),
-	PINMUX_IPSR_MSEL(IP16_23_20,	RIF2_SYNC_B,		SEL_DRIF2_1),
-	PINMUX_IPSR_MSEL(IP16_23_20,	REMOCON_B,		SEL_REMOCON_1),
-
-	PINMUX_IPSR_GPSR(IP16_27_24,	USB30_PWEN),
-	PINMUX_IPSR_MSEL(IP16_27_24,	AUDIO_CLKOUT_B,		SEL_ADG_1),
-	PINMUX_IPSR_MSEL(IP16_27_24,	SSI_SCK2_B,		SEL_SSI_1),
-	PINMUX_IPSR_MSEL(IP16_27_24,	TS_SDEN1_D,		SEL_TSIF1_3),
-	PINMUX_IPSR_MSEL(IP16_27_24,	STP_ISEN_1_D,		SEL_SSP1_1_3),
-	PINMUX_IPSR_MSEL(IP16_27_24,	STP_OPWM_0_E,		SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP16_27_24,	RIF3_D0_B,		SEL_DRIF3_1),
-	PINMUX_IPSR_MSEL(IP16_27_24,	TCLK2_B,		SEL_TIMER_TMU_1),
-	PINMUX_IPSR_GPSR(IP16_27_24,	TPU0TO0),
-
-	PINMUX_IPSR_GPSR(IP16_31_28,	USB30_OVC),
-	PINMUX_IPSR_MSEL(IP16_31_28,	AUDIO_CLKOUT1_B,	SEL_ADG_1),
-	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_WS2_B,		SEL_SSI_1),
-	PINMUX_IPSR_MSEL(IP16_31_28,	TS_SPSYNC1_D,		SEL_TSIF1_3),
-	PINMUX_IPSR_MSEL(IP16_31_28,	STP_ISSYNC_1_D,		SEL_SSP1_1_3),
-	PINMUX_IPSR_MSEL(IP16_31_28,	STP_IVCXO27_0_E,	SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP16_31_28,	RIF3_D1_B,		SEL_DRIF3_1),
-	PINMUX_IPSR_MSEL(IP16_31_28,	FSO_TOE_B,		SEL_FSO_1),
-	PINMUX_IPSR_GPSR(IP16_31_28,	TPU0TO1),
-
-	/* IPSR17 */
-	PINMUX_IPSR_GPSR(IP17_3_0,	USB31_PWEN),
-	PINMUX_IPSR_MSEL(IP17_3_0,	AUDIO_CLKOUT2_B,	SEL_ADG_1),
-	PINMUX_IPSR_MSEL(IP17_3_0,	SSI_SCK9_B,		SEL_SSI_1),
-	PINMUX_IPSR_MSEL(IP17_3_0,	TS_SDEN0_E,		SEL_TSIF0_4),
-	PINMUX_IPSR_MSEL(IP17_3_0,	STP_ISEN_0_E,		SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP17_3_0,	RIF2_D0_B,		SEL_DRIF2_1),
-	PINMUX_IPSR_GPSR(IP17_3_0,	TPU0TO2),
-
-	PINMUX_IPSR_GPSR(IP17_7_4,	USB31_OVC),
-	PINMUX_IPSR_MSEL(IP17_7_4,	AUDIO_CLKOUT3_B,	SEL_ADG_1),
-	PINMUX_IPSR_MSEL(IP17_7_4,	SSI_WS9_B,		SEL_SSI_1),
-	PINMUX_IPSR_MSEL(IP17_7_4,	TS_SPSYNC0_E,		SEL_TSIF0_4),
-	PINMUX_IPSR_MSEL(IP17_7_4,	STP_ISSYNC_0_E,		SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP17_7_4,	RIF2_D1_B,		SEL_DRIF2_1),
-	PINMUX_IPSR_GPSR(IP17_7_4,	TPU0TO3),
-
-/*
- * Static pins can not be muxed between different functions but
- * still need mark entries in the pinmux list. Add each static
- * pin to the list without an associated function. The sh-pfc
- * core will do the right thing and skip trying to mux the pin
- * while still applying configuration to it.
- */
-#define FM(x)	PINMUX_DATA(x##_MARK, 0),
-	PINMUX_STATIC
-#undef FM
-};
-
-/*
- * Pins not associated with a GPIO port.
- */
-enum {
-	GP_ASSIGN_LAST(),
-	NOGP_ALL(),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	PINMUX_GPIO_GP_ALL(),
-	PINMUX_NOGP_ALL(),
-};
-
-/* - AUDIO CLOCK ------------------------------------------------------------ */
-static const unsigned int audio_clk_a_a_pins[] = {
-	/* CLK A */
-	RCAR_GP_PIN(6, 22),
-};
-static const unsigned int audio_clk_a_a_mux[] = {
-	AUDIO_CLKA_A_MARK,
-};
-static const unsigned int audio_clk_a_b_pins[] = {
-	/* CLK A */
-	RCAR_GP_PIN(5, 4),
-};
-static const unsigned int audio_clk_a_b_mux[] = {
-	AUDIO_CLKA_B_MARK,
-};
-static const unsigned int audio_clk_a_c_pins[] = {
-	/* CLK A */
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int audio_clk_a_c_mux[] = {
-	AUDIO_CLKA_C_MARK,
-};
-static const unsigned int audio_clk_b_a_pins[] = {
-	/* CLK B */
-	RCAR_GP_PIN(5, 12),
-};
-static const unsigned int audio_clk_b_a_mux[] = {
-	AUDIO_CLKB_A_MARK,
-};
-static const unsigned int audio_clk_b_b_pins[] = {
-	/* CLK B */
-	RCAR_GP_PIN(6, 23),
-};
-static const unsigned int audio_clk_b_b_mux[] = {
-	AUDIO_CLKB_B_MARK,
-};
-static const unsigned int audio_clk_c_a_pins[] = {
-	/* CLK C */
-	RCAR_GP_PIN(5, 21),
-};
-static const unsigned int audio_clk_c_a_mux[] = {
-	AUDIO_CLKC_A_MARK,
-};
-static const unsigned int audio_clk_c_b_pins[] = {
-	/* CLK C */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int audio_clk_c_b_mux[] = {
-	AUDIO_CLKC_B_MARK,
-};
-static const unsigned int audio_clkout_a_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(5, 18),
-};
-static const unsigned int audio_clkout_a_mux[] = {
-	AUDIO_CLKOUT_A_MARK,
-};
-static const unsigned int audio_clkout_b_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(6, 28),
-};
-static const unsigned int audio_clkout_b_mux[] = {
-	AUDIO_CLKOUT_B_MARK,
-};
-static const unsigned int audio_clkout_c_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(5, 3),
-};
-static const unsigned int audio_clkout_c_mux[] = {
-	AUDIO_CLKOUT_C_MARK,
-};
-static const unsigned int audio_clkout_d_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(5, 21),
-};
-static const unsigned int audio_clkout_d_mux[] = {
-	AUDIO_CLKOUT_D_MARK,
-};
-static const unsigned int audio_clkout1_a_pins[] = {
-	/* CLKOUT1 */
-	RCAR_GP_PIN(5, 15),
-};
-static const unsigned int audio_clkout1_a_mux[] = {
-	AUDIO_CLKOUT1_A_MARK,
-};
-static const unsigned int audio_clkout1_b_pins[] = {
-	/* CLKOUT1 */
-	RCAR_GP_PIN(6, 29),
-};
-static const unsigned int audio_clkout1_b_mux[] = {
-	AUDIO_CLKOUT1_B_MARK,
-};
-static const unsigned int audio_clkout2_a_pins[] = {
-	/* CLKOUT2 */
-	RCAR_GP_PIN(5, 16),
-};
-static const unsigned int audio_clkout2_a_mux[] = {
-	AUDIO_CLKOUT2_A_MARK,
-};
-static const unsigned int audio_clkout2_b_pins[] = {
-	/* CLKOUT2 */
-	RCAR_GP_PIN(6, 30),
-};
-static const unsigned int audio_clkout2_b_mux[] = {
-	AUDIO_CLKOUT2_B_MARK,
-};
-
-static const unsigned int audio_clkout3_a_pins[] = {
-	/* CLKOUT3 */
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int audio_clkout3_a_mux[] = {
-	AUDIO_CLKOUT3_A_MARK,
-};
-static const unsigned int audio_clkout3_b_pins[] = {
-	/* CLKOUT3 */
-	RCAR_GP_PIN(6, 31),
-};
-static const unsigned int audio_clkout3_b_mux[] = {
-	AUDIO_CLKOUT3_B_MARK,
-};
-
-/* - EtherAVB --------------------------------------------------------------- */
-static const unsigned int avb_link_pins[] = {
-	/* AVB_LINK */
-	RCAR_GP_PIN(2, 12),
-};
-static const unsigned int avb_link_mux[] = {
-	AVB_LINK_MARK,
-};
-static const unsigned int avb_magic_pins[] = {
-	/* AVB_MAGIC_ */
-	RCAR_GP_PIN(2, 10),
-};
-static const unsigned int avb_magic_mux[] = {
-	AVB_MAGIC_MARK,
-};
-static const unsigned int avb_phy_int_pins[] = {
-	/* AVB_PHY_INT */
-	RCAR_GP_PIN(2, 11),
-};
-static const unsigned int avb_phy_int_mux[] = {
-	AVB_PHY_INT_MARK,
-};
-static const unsigned int avb_mdio_pins[] = {
-	/* AVB_MDC, AVB_MDIO */
-	RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
-};
-static const unsigned int avb_mdio_mux[] = {
-	AVB_MDC_MARK, AVB_MDIO_MARK,
-};
-static const unsigned int avb_mii_pins[] = {
-	/*
-	 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
-	 * AVB_TD1, AVB_TD2, AVB_TD3,
-	 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
-	 * AVB_RD1, AVB_RD2, AVB_RD3,
-	 * AVB_TXCREFCLK
-	 */
-	PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
-	PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
-	PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
-	PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
-	PIN_AVB_TXCREFCLK,
-
-};
-static const unsigned int avb_mii_mux[] = {
-	AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
-	AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
-	AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
-	AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
-	AVB_TXCREFCLK_MARK,
-};
-static const unsigned int avb_avtp_pps_pins[] = {
-	/* AVB_AVTP_PPS */
-	RCAR_GP_PIN(2, 6),
-};
-static const unsigned int avb_avtp_pps_mux[] = {
-	AVB_AVTP_PPS_MARK,
-};
-static const unsigned int avb_avtp_match_a_pins[] = {
-	/* AVB_AVTP_MATCH_A */
-	RCAR_GP_PIN(2, 13),
-};
-static const unsigned int avb_avtp_match_a_mux[] = {
-	AVB_AVTP_MATCH_A_MARK,
-};
-static const unsigned int avb_avtp_capture_a_pins[] = {
-	/* AVB_AVTP_CAPTURE_A */
-	RCAR_GP_PIN(2, 14),
-};
-static const unsigned int avb_avtp_capture_a_mux[] = {
-	AVB_AVTP_CAPTURE_A_MARK,
-};
-static const unsigned int avb_avtp_match_b_pins[] = {
-	/*  AVB_AVTP_MATCH_B */
-	RCAR_GP_PIN(1, 8),
-};
-static const unsigned int avb_avtp_match_b_mux[] = {
-	AVB_AVTP_MATCH_B_MARK,
-};
-static const unsigned int avb_avtp_capture_b_pins[] = {
-	/* AVB_AVTP_CAPTURE_B */
-	RCAR_GP_PIN(1, 11),
-};
-static const unsigned int avb_avtp_capture_b_mux[] = {
-	AVB_AVTP_CAPTURE_B_MARK,
-};
-
-/* - CAN ------------------------------------------------------------------ */
-static const unsigned int can0_data_a_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(1, 23),	RCAR_GP_PIN(1, 24),
-};
-static const unsigned int can0_data_a_mux[] = {
-	CAN0_TX_A_MARK,		CAN0_RX_A_MARK,
-};
-static const unsigned int can0_data_b_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(2, 0),	RCAR_GP_PIN(2, 1),
-};
-static const unsigned int can0_data_b_mux[] = {
-	CAN0_TX_B_MARK,		CAN0_RX_B_MARK,
-};
-static const unsigned int can1_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(1, 22),	RCAR_GP_PIN(1, 26),
-};
-static const unsigned int can1_data_mux[] = {
-	CAN1_TX_MARK,		CAN1_RX_MARK,
-};
-
-/* - CAN Clock -------------------------------------------------------------- */
-static const unsigned int can_clk_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(1, 25),
-};
-static const unsigned int can_clk_mux[] = {
-	CAN_CLK_MARK,
-};
-
-/* - CAN FD --------------------------------------------------------------- */
-static const unsigned int canfd0_data_a_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
-};
-static const unsigned int canfd0_data_a_mux[] = {
-	CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
-};
-static const unsigned int canfd0_data_b_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
-};
-static const unsigned int canfd0_data_b_mux[] = {
-	CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
-};
-static const unsigned int canfd1_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
-};
-static const unsigned int canfd1_data_mux[] = {
-	CANFD1_TX_MARK,         CANFD1_RX_MARK,
-};
-
-/* - DRIF0 --------------------------------------------------------------- */
-static const unsigned int drif0_ctrl_a_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
-};
-static const unsigned int drif0_ctrl_a_mux[] = {
-	RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
-};
-static const unsigned int drif0_data0_a_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 10),
-};
-static const unsigned int drif0_data0_a_mux[] = {
-	RIF0_D0_A_MARK,
-};
-static const unsigned int drif0_data1_a_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 7),
-};
-static const unsigned int drif0_data1_a_mux[] = {
-	RIF0_D1_A_MARK,
-};
-static const unsigned int drif0_ctrl_b_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
-};
-static const unsigned int drif0_ctrl_b_mux[] = {
-	RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
-};
-static const unsigned int drif0_data0_b_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(5, 1),
-};
-static const unsigned int drif0_data0_b_mux[] = {
-	RIF0_D0_B_MARK,
-};
-static const unsigned int drif0_data1_b_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(5, 2),
-};
-static const unsigned int drif0_data1_b_mux[] = {
-	RIF0_D1_B_MARK,
-};
-static const unsigned int drif0_ctrl_c_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
-};
-static const unsigned int drif0_ctrl_c_mux[] = {
-	RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
-};
-static const unsigned int drif0_data0_c_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(5, 13),
-};
-static const unsigned int drif0_data0_c_mux[] = {
-	RIF0_D0_C_MARK,
-};
-static const unsigned int drif0_data1_c_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(5, 14),
-};
-static const unsigned int drif0_data1_c_mux[] = {
-	RIF0_D1_C_MARK,
-};
-/* - DRIF1 --------------------------------------------------------------- */
-static const unsigned int drif1_ctrl_a_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
-};
-static const unsigned int drif1_ctrl_a_mux[] = {
-	RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
-};
-static const unsigned int drif1_data0_a_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 19),
-};
-static const unsigned int drif1_data0_a_mux[] = {
-	RIF1_D0_A_MARK,
-};
-static const unsigned int drif1_data1_a_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 20),
-};
-static const unsigned int drif1_data1_a_mux[] = {
-	RIF1_D1_A_MARK,
-};
-static const unsigned int drif1_ctrl_b_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
-};
-static const unsigned int drif1_ctrl_b_mux[] = {
-	RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
-};
-static const unsigned int drif1_data0_b_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(5, 7),
-};
-static const unsigned int drif1_data0_b_mux[] = {
-	RIF1_D0_B_MARK,
-};
-static const unsigned int drif1_data1_b_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(5, 8),
-};
-static const unsigned int drif1_data1_b_mux[] = {
-	RIF1_D1_B_MARK,
-};
-static const unsigned int drif1_ctrl_c_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
-};
-static const unsigned int drif1_ctrl_c_mux[] = {
-	RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
-};
-static const unsigned int drif1_data0_c_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(5, 6),
-};
-static const unsigned int drif1_data0_c_mux[] = {
-	RIF1_D0_C_MARK,
-};
-static const unsigned int drif1_data1_c_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(5, 10),
-};
-static const unsigned int drif1_data1_c_mux[] = {
-	RIF1_D1_C_MARK,
-};
-/* - DRIF2 --------------------------------------------------------------- */
-static const unsigned int drif2_ctrl_a_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
-};
-static const unsigned int drif2_ctrl_a_mux[] = {
-	RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
-};
-static const unsigned int drif2_data0_a_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 7),
-};
-static const unsigned int drif2_data0_a_mux[] = {
-	RIF2_D0_A_MARK,
-};
-static const unsigned int drif2_data1_a_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 10),
-};
-static const unsigned int drif2_data1_a_mux[] = {
-	RIF2_D1_A_MARK,
-};
-static const unsigned int drif2_ctrl_b_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
-};
-static const unsigned int drif2_ctrl_b_mux[] = {
-	RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
-};
-static const unsigned int drif2_data0_b_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 30),
-};
-static const unsigned int drif2_data0_b_mux[] = {
-	RIF2_D0_B_MARK,
-};
-static const unsigned int drif2_data1_b_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 31),
-};
-static const unsigned int drif2_data1_b_mux[] = {
-	RIF2_D1_B_MARK,
-};
-/* - DRIF3 --------------------------------------------------------------- */
-static const unsigned int drif3_ctrl_a_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
-};
-static const unsigned int drif3_ctrl_a_mux[] = {
-	RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
-};
-static const unsigned int drif3_data0_a_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 19),
-};
-static const unsigned int drif3_data0_a_mux[] = {
-	RIF3_D0_A_MARK,
-};
-static const unsigned int drif3_data1_a_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 20),
-};
-static const unsigned int drif3_data1_a_mux[] = {
-	RIF3_D1_A_MARK,
-};
-static const unsigned int drif3_ctrl_b_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
-};
-static const unsigned int drif3_ctrl_b_mux[] = {
-	RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
-};
-static const unsigned int drif3_data0_b_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 28),
-};
-static const unsigned int drif3_data0_b_mux[] = {
-	RIF3_D0_B_MARK,
-};
-static const unsigned int drif3_data1_b_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 29),
-};
-static const unsigned int drif3_data1_b_mux[] = {
-	RIF3_D1_B_MARK,
-};
-
-/* - DU --------------------------------------------------------------------- */
-static const unsigned int du_rgb666_pins[] = {
-	/* R[7:2], G[7:2], B[7:2] */
-	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
-	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
-	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
-	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
-};
-static const unsigned int du_rgb666_mux[] = {
-	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
-	DU_DR3_MARK, DU_DR2_MARK,
-	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
-	DU_DG3_MARK, DU_DG2_MARK,
-	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
-	DU_DB3_MARK, DU_DB2_MARK,
-};
-static const unsigned int du_rgb888_pins[] = {
-	/* R[7:0], G[7:0], B[7:0] */
-	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
-	RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
-	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
-	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
-	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
-	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
-	RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
-};
-static const unsigned int du_rgb888_mux[] = {
-	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
-	DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
-	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
-	DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
-	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
-	DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
-};
-static const unsigned int du_clk_out_0_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(1, 27),
-};
-static const unsigned int du_clk_out_0_mux[] = {
-	DU_DOTCLKOUT0_MARK
-};
-static const unsigned int du_clk_out_1_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(2, 3),
-};
-static const unsigned int du_clk_out_1_mux[] = {
-	DU_DOTCLKOUT1_MARK
-};
-static const unsigned int du_sync_pins[] = {
-	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
-	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
-};
-static const unsigned int du_sync_mux[] = {
-	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
-};
-static const unsigned int du_oddf_pins[] = {
-	/* EXDISP/EXODDF/EXCDE */
-	RCAR_GP_PIN(2, 2),
-};
-static const unsigned int du_oddf_mux[] = {
-	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
-};
-static const unsigned int du_cde_pins[] = {
-	/* CDE */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int du_cde_mux[] = {
-	DU_CDE_MARK,
-};
-static const unsigned int du_disp_pins[] = {
-	/* DISP */
-	RCAR_GP_PIN(2, 1),
-};
-static const unsigned int du_disp_mux[] = {
-	DU_DISP_MARK,
-};
-/* - HSCIF0 ----------------------------------------------------------------- */
-static const unsigned int hscif0_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
-};
-static const unsigned int hscif0_data_mux[] = {
-	HRX0_MARK, HTX0_MARK,
-};
-static const unsigned int hscif0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 12),
-};
-static const unsigned int hscif0_clk_mux[] = {
-	HSCK0_MARK,
-};
-static const unsigned int hscif0_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
-};
-static const unsigned int hscif0_ctrl_mux[] = {
-	HRTS0_N_MARK, HCTS0_N_MARK,
-};
-/* - HSCIF1 ----------------------------------------------------------------- */
-static const unsigned int hscif1_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
-};
-static const unsigned int hscif1_data_a_mux[] = {
-	HRX1_A_MARK, HTX1_A_MARK,
-};
-static const unsigned int hscif1_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int hscif1_clk_a_mux[] = {
-	HSCK1_A_MARK,
-};
-static const unsigned int hscif1_ctrl_a_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
-};
-static const unsigned int hscif1_ctrl_a_mux[] = {
-	HRTS1_N_A_MARK, HCTS1_N_A_MARK,
-};
-
-static const unsigned int hscif1_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-};
-static const unsigned int hscif1_data_b_mux[] = {
-	HRX1_B_MARK, HTX1_B_MARK,
-};
-static const unsigned int hscif1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int hscif1_clk_b_mux[] = {
-	HSCK1_B_MARK,
-};
-static const unsigned int hscif1_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
-};
-static const unsigned int hscif1_ctrl_b_mux[] = {
-	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
-};
-/* - HSCIF2 ----------------------------------------------------------------- */
-static const unsigned int hscif2_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
-};
-static const unsigned int hscif2_data_a_mux[] = {
-	HRX2_A_MARK, HTX2_A_MARK,
-};
-static const unsigned int hscif2_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 10),
-};
-static const unsigned int hscif2_clk_a_mux[] = {
-	HSCK2_A_MARK,
-};
-static const unsigned int hscif2_ctrl_a_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
-};
-static const unsigned int hscif2_ctrl_a_mux[] = {
-	HRTS2_N_A_MARK, HCTS2_N_A_MARK,
-};
-
-static const unsigned int hscif2_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
-};
-static const unsigned int hscif2_data_b_mux[] = {
-	HRX2_B_MARK, HTX2_B_MARK,
-};
-static const unsigned int hscif2_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int hscif2_clk_b_mux[] = {
-	HSCK2_B_MARK,
-};
-static const unsigned int hscif2_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
-};
-static const unsigned int hscif2_ctrl_b_mux[] = {
-	HRTS2_N_B_MARK, HCTS2_N_B_MARK,
-};
-/* - HSCIF3 ----------------------------------------------------------------- */
-static const unsigned int hscif3_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
-};
-static const unsigned int hscif3_data_a_mux[] = {
-	HRX3_A_MARK, HTX3_A_MARK,
-};
-static const unsigned int hscif3_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 22),
-};
-static const unsigned int hscif3_clk_mux[] = {
-	HSCK3_MARK,
-};
-static const unsigned int hscif3_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
-};
-static const unsigned int hscif3_ctrl_mux[] = {
-	HRTS3_N_MARK, HCTS3_N_MARK,
-};
-
-static const unsigned int hscif3_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-};
-static const unsigned int hscif3_data_b_mux[] = {
-	HRX3_B_MARK, HTX3_B_MARK,
-};
-static const unsigned int hscif3_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-};
-static const unsigned int hscif3_data_c_mux[] = {
-	HRX3_C_MARK, HTX3_C_MARK,
-};
-static const unsigned int hscif3_data_d_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
-};
-static const unsigned int hscif3_data_d_mux[] = {
-	HRX3_D_MARK, HTX3_D_MARK,
-};
-/* - HSCIF4 ----------------------------------------------------------------- */
-static const unsigned int hscif4_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-};
-static const unsigned int hscif4_data_a_mux[] = {
-	HRX4_A_MARK, HTX4_A_MARK,
-};
-static const unsigned int hscif4_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 11),
-};
-static const unsigned int hscif4_clk_mux[] = {
-	HSCK4_MARK,
-};
-static const unsigned int hscif4_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
-};
-static const unsigned int hscif4_ctrl_mux[] = {
-	HRTS4_N_MARK, HCTS4_N_MARK,
-};
-
-static const unsigned int hscif4_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
-};
-static const unsigned int hscif4_data_b_mux[] = {
-	HRX4_B_MARK, HTX4_B_MARK,
-};
-
-/* - I2C -------------------------------------------------------------------- */
-static const unsigned int i2c0_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
-};
-
-static const unsigned int i2c0_mux[] = {
-	SCL0_MARK, SDA0_MARK,
-};
-
-static const unsigned int i2c1_a_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
-};
-static const unsigned int i2c1_a_mux[] = {
-	SDA1_A_MARK, SCL1_A_MARK,
-};
-static const unsigned int i2c1_b_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
-};
-static const unsigned int i2c1_b_mux[] = {
-	SDA1_B_MARK, SCL1_B_MARK,
-};
-static const unsigned int i2c2_a_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
-};
-static const unsigned int i2c2_a_mux[] = {
-	SDA2_A_MARK, SCL2_A_MARK,
-};
-static const unsigned int i2c2_b_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
-};
-static const unsigned int i2c2_b_mux[] = {
-	SDA2_B_MARK, SCL2_B_MARK,
-};
-
-static const unsigned int i2c3_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
-};
-
-static const unsigned int i2c3_mux[] = {
-	SCL3_MARK, SDA3_MARK,
-};
-
-static const unsigned int i2c5_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
-};
-
-static const unsigned int i2c5_mux[] = {
-	SCL5_MARK, SDA5_MARK,
-};
-
-static const unsigned int i2c6_a_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
-};
-static const unsigned int i2c6_a_mux[] = {
-	SDA6_A_MARK, SCL6_A_MARK,
-};
-static const unsigned int i2c6_b_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
-};
-static const unsigned int i2c6_b_mux[] = {
-	SDA6_B_MARK, SCL6_B_MARK,
-};
-static const unsigned int i2c6_c_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
-};
-static const unsigned int i2c6_c_mux[] = {
-	SDA6_C_MARK, SCL6_C_MARK,
-};
-
-/* - INTC-EX ---------------------------------------------------------------- */
-static const unsigned int intc_ex_irq0_pins[] = {
-	/* IRQ0 */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int intc_ex_irq0_mux[] = {
-	IRQ0_MARK,
-};
-static const unsigned int intc_ex_irq1_pins[] = {
-	/* IRQ1 */
-	RCAR_GP_PIN(2, 1),
-};
-static const unsigned int intc_ex_irq1_mux[] = {
-	IRQ1_MARK,
-};
-static const unsigned int intc_ex_irq2_pins[] = {
-	/* IRQ2 */
-	RCAR_GP_PIN(2, 2),
-};
-static const unsigned int intc_ex_irq2_mux[] = {
-	IRQ2_MARK,
-};
-static const unsigned int intc_ex_irq3_pins[] = {
-	/* IRQ3 */
-	RCAR_GP_PIN(2, 3),
-};
-static const unsigned int intc_ex_irq3_mux[] = {
-	IRQ3_MARK,
-};
-static const unsigned int intc_ex_irq4_pins[] = {
-	/* IRQ4 */
-	RCAR_GP_PIN(2, 4),
-};
-static const unsigned int intc_ex_irq4_mux[] = {
-	IRQ4_MARK,
-};
-static const unsigned int intc_ex_irq5_pins[] = {
-	/* IRQ5 */
-	RCAR_GP_PIN(2, 5),
-};
-static const unsigned int intc_ex_irq5_mux[] = {
-	IRQ5_MARK,
-};
-
-/* - MSIOF0 ----------------------------------------------------------------- */
-static const unsigned int msiof0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 17),
-};
-static const unsigned int msiof0_clk_mux[] = {
-	MSIOF0_SCK_MARK,
-};
-static const unsigned int msiof0_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(5, 18),
-};
-static const unsigned int msiof0_sync_mux[] = {
-	MSIOF0_SYNC_MARK,
-};
-static const unsigned int msiof0_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int msiof0_ss1_mux[] = {
-	MSIOF0_SS1_MARK,
-};
-static const unsigned int msiof0_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(5, 21),
-};
-static const unsigned int msiof0_ss2_mux[] = {
-	MSIOF0_SS2_MARK,
-};
-static const unsigned int msiof0_txd_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(5, 20),
-};
-static const unsigned int msiof0_txd_mux[] = {
-	MSIOF0_TXD_MARK,
-};
-static const unsigned int msiof0_rxd_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 22),
-};
-static const unsigned int msiof0_rxd_mux[] = {
-	MSIOF0_RXD_MARK,
-};
-/* - MSIOF1 ----------------------------------------------------------------- */
-static const unsigned int msiof1_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 8),
-};
-static const unsigned int msiof1_clk_a_mux[] = {
-	MSIOF1_SCK_A_MARK,
-};
-static const unsigned int msiof1_sync_a_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(6, 9),
-};
-static const unsigned int msiof1_sync_a_mux[] = {
-	MSIOF1_SYNC_A_MARK,
-};
-static const unsigned int msiof1_ss1_a_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(6, 5),
-};
-static const unsigned int msiof1_ss1_a_mux[] = {
-	MSIOF1_SS1_A_MARK,
-};
-static const unsigned int msiof1_ss2_a_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(6, 6),
-};
-static const unsigned int msiof1_ss2_a_mux[] = {
-	MSIOF1_SS2_A_MARK,
-};
-static const unsigned int msiof1_txd_a_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(6, 7),
-};
-static const unsigned int msiof1_txd_a_mux[] = {
-	MSIOF1_TXD_A_MARK,
-};
-static const unsigned int msiof1_rxd_a_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(6, 10),
-};
-static const unsigned int msiof1_rxd_a_mux[] = {
-	MSIOF1_RXD_A_MARK,
-};
-static const unsigned int msiof1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 9),
-};
-static const unsigned int msiof1_clk_b_mux[] = {
-	MSIOF1_SCK_B_MARK,
-};
-static const unsigned int msiof1_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(5, 3),
-};
-static const unsigned int msiof1_sync_b_mux[] = {
-	MSIOF1_SYNC_B_MARK,
-};
-static const unsigned int msiof1_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(5, 4),
-};
-static const unsigned int msiof1_ss1_b_mux[] = {
-	MSIOF1_SS1_B_MARK,
-};
-static const unsigned int msiof1_ss2_b_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int msiof1_ss2_b_mux[] = {
-	MSIOF1_SS2_B_MARK,
-};
-static const unsigned int msiof1_txd_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(5, 8),
-};
-static const unsigned int msiof1_txd_b_mux[] = {
-	MSIOF1_TXD_B_MARK,
-};
-static const unsigned int msiof1_rxd_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 7),
-};
-static const unsigned int msiof1_rxd_b_mux[] = {
-	MSIOF1_RXD_B_MARK,
-};
-static const unsigned int msiof1_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 17),
-};
-static const unsigned int msiof1_clk_c_mux[] = {
-	MSIOF1_SCK_C_MARK,
-};
-static const unsigned int msiof1_sync_c_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(6, 18),
-};
-static const unsigned int msiof1_sync_c_mux[] = {
-	MSIOF1_SYNC_C_MARK,
-};
-static const unsigned int msiof1_ss1_c_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int msiof1_ss1_c_mux[] = {
-	MSIOF1_SS1_C_MARK,
-};
-static const unsigned int msiof1_ss2_c_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(6, 27),
-};
-static const unsigned int msiof1_ss2_c_mux[] = {
-	MSIOF1_SS2_C_MARK,
-};
-static const unsigned int msiof1_txd_c_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(6, 20),
-};
-static const unsigned int msiof1_txd_c_mux[] = {
-	MSIOF1_TXD_C_MARK,
-};
-static const unsigned int msiof1_rxd_c_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(6, 19),
-};
-static const unsigned int msiof1_rxd_c_mux[] = {
-	MSIOF1_RXD_C_MARK,
-};
-static const unsigned int msiof1_clk_d_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 12),
-};
-static const unsigned int msiof1_clk_d_mux[] = {
-	MSIOF1_SCK_D_MARK,
-};
-static const unsigned int msiof1_sync_d_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(5, 15),
-};
-static const unsigned int msiof1_sync_d_mux[] = {
-	MSIOF1_SYNC_D_MARK,
-};
-static const unsigned int msiof1_ss1_d_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(5, 16),
-};
-static const unsigned int msiof1_ss1_d_mux[] = {
-	MSIOF1_SS1_D_MARK,
-};
-static const unsigned int msiof1_ss2_d_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(5, 21),
-};
-static const unsigned int msiof1_ss2_d_mux[] = {
-	MSIOF1_SS2_D_MARK,
-};
-static const unsigned int msiof1_txd_d_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(5, 14),
-};
-static const unsigned int msiof1_txd_d_mux[] = {
-	MSIOF1_TXD_D_MARK,
-};
-static const unsigned int msiof1_rxd_d_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 13),
-};
-static const unsigned int msiof1_rxd_d_mux[] = {
-	MSIOF1_RXD_D_MARK,
-};
-static const unsigned int msiof1_clk_e_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 0),
-};
-static const unsigned int msiof1_clk_e_mux[] = {
-	MSIOF1_SCK_E_MARK,
-};
-static const unsigned int msiof1_sync_e_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(3, 1),
-};
-static const unsigned int msiof1_sync_e_mux[] = {
-	MSIOF1_SYNC_E_MARK,
-};
-static const unsigned int msiof1_ss1_e_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(3, 4),
-};
-static const unsigned int msiof1_ss1_e_mux[] = {
-	MSIOF1_SS1_E_MARK,
-};
-static const unsigned int msiof1_ss2_e_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(3, 5),
-};
-static const unsigned int msiof1_ss2_e_mux[] = {
-	MSIOF1_SS2_E_MARK,
-};
-static const unsigned int msiof1_txd_e_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(3, 3),
-};
-static const unsigned int msiof1_txd_e_mux[] = {
-	MSIOF1_TXD_E_MARK,
-};
-static const unsigned int msiof1_rxd_e_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(3, 2),
-};
-static const unsigned int msiof1_rxd_e_mux[] = {
-	MSIOF1_RXD_E_MARK,
-};
-static const unsigned int msiof1_clk_f_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 23),
-};
-static const unsigned int msiof1_clk_f_mux[] = {
-	MSIOF1_SCK_F_MARK,
-};
-static const unsigned int msiof1_sync_f_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(5, 24),
-};
-static const unsigned int msiof1_sync_f_mux[] = {
-	MSIOF1_SYNC_F_MARK,
-};
-static const unsigned int msiof1_ss1_f_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(6, 1),
-};
-static const unsigned int msiof1_ss1_f_mux[] = {
-	MSIOF1_SS1_F_MARK,
-};
-static const unsigned int msiof1_ss2_f_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(6, 2),
-};
-static const unsigned int msiof1_ss2_f_mux[] = {
-	MSIOF1_SS2_F_MARK,
-};
-static const unsigned int msiof1_txd_f_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(6, 0),
-};
-static const unsigned int msiof1_txd_f_mux[] = {
-	MSIOF1_TXD_F_MARK,
-};
-static const unsigned int msiof1_rxd_f_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 25),
-};
-static const unsigned int msiof1_rxd_f_mux[] = {
-	MSIOF1_RXD_F_MARK,
-};
-static const unsigned int msiof1_clk_g_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 6),
-};
-static const unsigned int msiof1_clk_g_mux[] = {
-	MSIOF1_SCK_G_MARK,
-};
-static const unsigned int msiof1_sync_g_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(3, 7),
-};
-static const unsigned int msiof1_sync_g_mux[] = {
-	MSIOF1_SYNC_G_MARK,
-};
-static const unsigned int msiof1_ss1_g_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(3, 10),
-};
-static const unsigned int msiof1_ss1_g_mux[] = {
-	MSIOF1_SS1_G_MARK,
-};
-static const unsigned int msiof1_ss2_g_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(3, 11),
-};
-static const unsigned int msiof1_ss2_g_mux[] = {
-	MSIOF1_SS2_G_MARK,
-};
-static const unsigned int msiof1_txd_g_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(3, 9),
-};
-static const unsigned int msiof1_txd_g_mux[] = {
-	MSIOF1_TXD_G_MARK,
-};
-static const unsigned int msiof1_rxd_g_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(3, 8),
-};
-static const unsigned int msiof1_rxd_g_mux[] = {
-	MSIOF1_RXD_G_MARK,
-};
-/* - MSIOF2 ----------------------------------------------------------------- */
-static const unsigned int msiof2_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 9),
-};
-static const unsigned int msiof2_clk_a_mux[] = {
-	MSIOF2_SCK_A_MARK,
-};
-static const unsigned int msiof2_sync_a_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 8),
-};
-static const unsigned int msiof2_sync_a_mux[] = {
-	MSIOF2_SYNC_A_MARK,
-};
-static const unsigned int msiof2_ss1_a_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(1, 6),
-};
-static const unsigned int msiof2_ss1_a_mux[] = {
-	MSIOF2_SS1_A_MARK,
-};
-static const unsigned int msiof2_ss2_a_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(1, 7),
-};
-static const unsigned int msiof2_ss2_a_mux[] = {
-	MSIOF2_SS2_A_MARK,
-};
-static const unsigned int msiof2_txd_a_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 11),
-};
-static const unsigned int msiof2_txd_a_mux[] = {
-	MSIOF2_TXD_A_MARK,
-};
-static const unsigned int msiof2_rxd_a_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 10),
-};
-static const unsigned int msiof2_rxd_a_mux[] = {
-	MSIOF2_RXD_A_MARK,
-};
-static const unsigned int msiof2_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 4),
-};
-static const unsigned int msiof2_clk_b_mux[] = {
-	MSIOF2_SCK_B_MARK,
-};
-static const unsigned int msiof2_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 5),
-};
-static const unsigned int msiof2_sync_b_mux[] = {
-	MSIOF2_SYNC_B_MARK,
-};
-static const unsigned int msiof2_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 0),
-};
-static const unsigned int msiof2_ss1_b_mux[] = {
-	MSIOF2_SS1_B_MARK,
-};
-static const unsigned int msiof2_ss2_b_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 1),
-};
-static const unsigned int msiof2_ss2_b_mux[] = {
-	MSIOF2_SS2_B_MARK,
-};
-static const unsigned int msiof2_txd_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 7),
-};
-static const unsigned int msiof2_txd_b_mux[] = {
-	MSIOF2_TXD_B_MARK,
-};
-static const unsigned int msiof2_rxd_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 6),
-};
-static const unsigned int msiof2_rxd_b_mux[] = {
-	MSIOF2_RXD_B_MARK,
-};
-static const unsigned int msiof2_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 12),
-};
-static const unsigned int msiof2_clk_c_mux[] = {
-	MSIOF2_SCK_C_MARK,
-};
-static const unsigned int msiof2_sync_c_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(2, 11),
-};
-static const unsigned int msiof2_sync_c_mux[] = {
-	MSIOF2_SYNC_C_MARK,
-};
-static const unsigned int msiof2_ss1_c_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(2, 10),
-};
-static const unsigned int msiof2_ss1_c_mux[] = {
-	MSIOF2_SS1_C_MARK,
-};
-static const unsigned int msiof2_ss2_c_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(2, 9),
-};
-static const unsigned int msiof2_ss2_c_mux[] = {
-	MSIOF2_SS2_C_MARK,
-};
-static const unsigned int msiof2_txd_c_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(2, 14),
-};
-static const unsigned int msiof2_txd_c_mux[] = {
-	MSIOF2_TXD_C_MARK,
-};
-static const unsigned int msiof2_rxd_c_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(2, 13),
-};
-static const unsigned int msiof2_rxd_c_mux[] = {
-	MSIOF2_RXD_C_MARK,
-};
-static const unsigned int msiof2_clk_d_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 8),
-};
-static const unsigned int msiof2_clk_d_mux[] = {
-	MSIOF2_SCK_D_MARK,
-};
-static const unsigned int msiof2_sync_d_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 9),
-};
-static const unsigned int msiof2_sync_d_mux[] = {
-	MSIOF2_SYNC_D_MARK,
-};
-static const unsigned int msiof2_ss1_d_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 12),
-};
-static const unsigned int msiof2_ss1_d_mux[] = {
-	MSIOF2_SS1_D_MARK,
-};
-static const unsigned int msiof2_ss2_d_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 13),
-};
-static const unsigned int msiof2_ss2_d_mux[] = {
-	MSIOF2_SS2_D_MARK,
-};
-static const unsigned int msiof2_txd_d_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 11),
-};
-static const unsigned int msiof2_txd_d_mux[] = {
-	MSIOF2_TXD_D_MARK,
-};
-static const unsigned int msiof2_rxd_d_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 10),
-};
-static const unsigned int msiof2_rxd_d_mux[] = {
-	MSIOF2_RXD_D_MARK,
-};
-/* - MSIOF3 ----------------------------------------------------------------- */
-static const unsigned int msiof3_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 0),
-};
-static const unsigned int msiof3_clk_a_mux[] = {
-	MSIOF3_SCK_A_MARK,
-};
-static const unsigned int msiof3_sync_a_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 1),
-};
-static const unsigned int msiof3_sync_a_mux[] = {
-	MSIOF3_SYNC_A_MARK,
-};
-static const unsigned int msiof3_ss1_a_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 14),
-};
-static const unsigned int msiof3_ss1_a_mux[] = {
-	MSIOF3_SS1_A_MARK,
-};
-static const unsigned int msiof3_ss2_a_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 15),
-};
-static const unsigned int msiof3_ss2_a_mux[] = {
-	MSIOF3_SS2_A_MARK,
-};
-static const unsigned int msiof3_txd_a_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 3),
-};
-static const unsigned int msiof3_txd_a_mux[] = {
-	MSIOF3_TXD_A_MARK,
-};
-static const unsigned int msiof3_rxd_a_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 2),
-};
-static const unsigned int msiof3_rxd_a_mux[] = {
-	MSIOF3_RXD_A_MARK,
-};
-static const unsigned int msiof3_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 2),
-};
-static const unsigned int msiof3_clk_b_mux[] = {
-	MSIOF3_SCK_B_MARK,
-};
-static const unsigned int msiof3_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 0),
-};
-static const unsigned int msiof3_sync_b_mux[] = {
-	MSIOF3_SYNC_B_MARK,
-};
-static const unsigned int msiof3_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(1, 4),
-};
-static const unsigned int msiof3_ss1_b_mux[] = {
-	MSIOF3_SS1_B_MARK,
-};
-static const unsigned int msiof3_ss2_b_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(1, 5),
-};
-static const unsigned int msiof3_ss2_b_mux[] = {
-	MSIOF3_SS2_B_MARK,
-};
-static const unsigned int msiof3_txd_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 1),
-};
-static const unsigned int msiof3_txd_b_mux[] = {
-	MSIOF3_TXD_B_MARK,
-};
-static const unsigned int msiof3_rxd_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 3),
-};
-static const unsigned int msiof3_rxd_b_mux[] = {
-	MSIOF3_RXD_B_MARK,
-};
-static const unsigned int msiof3_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 12),
-};
-static const unsigned int msiof3_clk_c_mux[] = {
-	MSIOF3_SCK_C_MARK,
-};
-static const unsigned int msiof3_sync_c_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 13),
-};
-static const unsigned int msiof3_sync_c_mux[] = {
-	MSIOF3_SYNC_C_MARK,
-};
-static const unsigned int msiof3_txd_c_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 15),
-};
-static const unsigned int msiof3_txd_c_mux[] = {
-	MSIOF3_TXD_C_MARK,
-};
-static const unsigned int msiof3_rxd_c_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 14),
-};
-static const unsigned int msiof3_rxd_c_mux[] = {
-	MSIOF3_RXD_C_MARK,
-};
-static const unsigned int msiof3_clk_d_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 22),
-};
-static const unsigned int msiof3_clk_d_mux[] = {
-	MSIOF3_SCK_D_MARK,
-};
-static const unsigned int msiof3_sync_d_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 23),
-};
-static const unsigned int msiof3_sync_d_mux[] = {
-	MSIOF3_SYNC_D_MARK,
-};
-static const unsigned int msiof3_ss1_d_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(1, 26),
-};
-static const unsigned int msiof3_ss1_d_mux[] = {
-	MSIOF3_SS1_D_MARK,
-};
-static const unsigned int msiof3_txd_d_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 25),
-};
-static const unsigned int msiof3_txd_d_mux[] = {
-	MSIOF3_TXD_D_MARK,
-};
-static const unsigned int msiof3_rxd_d_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 24),
-};
-static const unsigned int msiof3_rxd_d_mux[] = {
-	MSIOF3_RXD_D_MARK,
-};
-
-/* - PWM0 --------------------------------------------------------------------*/
-static const unsigned int pwm0_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 6),
-};
-static const unsigned int pwm0_mux[] = {
-	PWM0_MARK,
-};
-/* - PWM1 --------------------------------------------------------------------*/
-static const unsigned int pwm1_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 7),
-};
-static const unsigned int pwm1_a_mux[] = {
-	PWM1_A_MARK,
-};
-static const unsigned int pwm1_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 8),
-};
-static const unsigned int pwm1_b_mux[] = {
-	PWM1_B_MARK,
-};
-/* - PWM2 --------------------------------------------------------------------*/
-static const unsigned int pwm2_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 8),
-};
-static const unsigned int pwm2_a_mux[] = {
-	PWM2_A_MARK,
-};
-static const unsigned int pwm2_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 11),
-};
-static const unsigned int pwm2_b_mux[] = {
-	PWM2_B_MARK,
-};
-/* - PWM3 --------------------------------------------------------------------*/
-static const unsigned int pwm3_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 0),
-};
-static const unsigned int pwm3_a_mux[] = {
-	PWM3_A_MARK,
-};
-static const unsigned int pwm3_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 2),
-};
-static const unsigned int pwm3_b_mux[] = {
-	PWM3_B_MARK,
-};
-/* - PWM4 --------------------------------------------------------------------*/
-static const unsigned int pwm4_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 1),
-};
-static const unsigned int pwm4_a_mux[] = {
-	PWM4_A_MARK,
-};
-static const unsigned int pwm4_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 3),
-};
-static const unsigned int pwm4_b_mux[] = {
-	PWM4_B_MARK,
-};
-/* - PWM5 --------------------------------------------------------------------*/
-static const unsigned int pwm5_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 2),
-};
-static const unsigned int pwm5_a_mux[] = {
-	PWM5_A_MARK,
-};
-static const unsigned int pwm5_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 4),
-};
-static const unsigned int pwm5_b_mux[] = {
-	PWM5_B_MARK,
-};
-/* - PWM6 --------------------------------------------------------------------*/
-static const unsigned int pwm6_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 3),
-};
-static const unsigned int pwm6_a_mux[] = {
-	PWM6_A_MARK,
-};
-static const unsigned int pwm6_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 5),
-};
-static const unsigned int pwm6_b_mux[] = {
-	PWM6_B_MARK,
-};
-
-/* - QSPI0 ------------------------------------------------------------------ */
-static const unsigned int qspi0_ctrl_pins[] = {
-	/* QSPI0_SPCLK, QSPI0_SSL */
-	PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
-};
-static const unsigned int qspi0_ctrl_mux[] = {
-	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
-};
-static const unsigned int qspi0_data2_pins[] = {
-	/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
-	PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
-};
-static const unsigned int qspi0_data2_mux[] = {
-	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
-};
-static const unsigned int qspi0_data4_pins[] = {
-	/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */
-	PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, PIN_QSPI0_IO2, PIN_QSPI0_IO3,
-};
-static const unsigned int qspi0_data4_mux[] = {
-	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
-	QSPI0_IO2_MARK, QSPI0_IO3_MARK,
-};
-/* - QSPI1 ------------------------------------------------------------------ */
-static const unsigned int qspi1_ctrl_pins[] = {
-	/* QSPI1_SPCLK, QSPI1_SSL */
-	PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
-};
-static const unsigned int qspi1_ctrl_mux[] = {
-	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
-};
-static const unsigned int qspi1_data2_pins[] = {
-	/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
-	PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
-};
-static const unsigned int qspi1_data2_mux[] = {
-	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
-};
-static const unsigned int qspi1_data4_pins[] = {
-	/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */
-	PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, PIN_QSPI1_IO2, PIN_QSPI1_IO3,
-};
-static const unsigned int qspi1_data4_mux[] = {
-	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
-	QSPI1_IO2_MARK, QSPI1_IO3_MARK,
-};
-
-/* - SATA --------------------------------------------------------------------*/
-static const unsigned int sata0_devslp_a_pins[] = {
-	/* DEVSLP */
-	RCAR_GP_PIN(6, 16),
-};
-static const unsigned int sata0_devslp_a_mux[] = {
-	SATA_DEVSLP_A_MARK,
-};
-static const unsigned int sata0_devslp_b_pins[] = {
-	/* DEVSLP */
-	RCAR_GP_PIN(4, 6),
-};
-static const unsigned int sata0_devslp_b_mux[] = {
-	SATA_DEVSLP_B_MARK,
-};
-
-/* - SCIF0 ------------------------------------------------------------------ */
-static const unsigned int scif0_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-};
-static const unsigned int scif0_data_mux[] = {
-	RX0_MARK, TX0_MARK,
-};
-static const unsigned int scif0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int scif0_clk_mux[] = {
-	SCK0_MARK,
-};
-static const unsigned int scif0_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
-};
-static const unsigned int scif0_ctrl_mux[] = {
-	RTS0_N_MARK, CTS0_N_MARK,
-};
-/* - SCIF1 ------------------------------------------------------------------ */
-static const unsigned int scif1_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
-};
-static const unsigned int scif1_data_a_mux[] = {
-	RX1_A_MARK, TX1_A_MARK,
-};
-static const unsigned int scif1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int scif1_clk_mux[] = {
-	SCK1_MARK,
-};
-static const unsigned int scif1_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
-};
-static const unsigned int scif1_ctrl_mux[] = {
-	RTS1_N_MARK, CTS1_N_MARK,
-};
-
-static const unsigned int scif1_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
-};
-static const unsigned int scif1_data_b_mux[] = {
-	RX1_B_MARK, TX1_B_MARK,
-};
-/* - SCIF2 ------------------------------------------------------------------ */
-static const unsigned int scif2_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
-};
-static const unsigned int scif2_data_a_mux[] = {
-	RX2_A_MARK, TX2_A_MARK,
-};
-static const unsigned int scif2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 9),
-};
-static const unsigned int scif2_clk_mux[] = {
-	SCK2_MARK,
-};
-static const unsigned int scif2_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
-};
-static const unsigned int scif2_data_b_mux[] = {
-	RX2_B_MARK, TX2_B_MARK,
-};
-/* - SCIF3 ------------------------------------------------------------------ */
-static const unsigned int scif3_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
-};
-static const unsigned int scif3_data_a_mux[] = {
-	RX3_A_MARK, TX3_A_MARK,
-};
-static const unsigned int scif3_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 22),
-};
-static const unsigned int scif3_clk_mux[] = {
-	SCK3_MARK,
-};
-static const unsigned int scif3_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
-};
-static const unsigned int scif3_ctrl_mux[] = {
-	RTS3_N_MARK, CTS3_N_MARK,
-};
-static const unsigned int scif3_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
-};
-static const unsigned int scif3_data_b_mux[] = {
-	RX3_B_MARK, TX3_B_MARK,
-};
-/* - SCIF4 ------------------------------------------------------------------ */
-static const unsigned int scif4_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
-};
-static const unsigned int scif4_data_a_mux[] = {
-	RX4_A_MARK, TX4_A_MARK,
-};
-static const unsigned int scif4_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 10),
-};
-static const unsigned int scif4_clk_a_mux[] = {
-	SCK4_A_MARK,
-};
-static const unsigned int scif4_ctrl_a_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
-};
-static const unsigned int scif4_ctrl_a_mux[] = {
-	RTS4_N_A_MARK, CTS4_N_A_MARK,
-};
-static const unsigned int scif4_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-};
-static const unsigned int scif4_data_b_mux[] = {
-	RX4_B_MARK, TX4_B_MARK,
-};
-static const unsigned int scif4_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 5),
-};
-static const unsigned int scif4_clk_b_mux[] = {
-	SCK4_B_MARK,
-};
-static const unsigned int scif4_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
-};
-static const unsigned int scif4_ctrl_b_mux[] = {
-	RTS4_N_B_MARK, CTS4_N_B_MARK,
-};
-static const unsigned int scif4_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-};
-static const unsigned int scif4_data_c_mux[] = {
-	RX4_C_MARK, TX4_C_MARK,
-};
-static const unsigned int scif4_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 8),
-};
-static const unsigned int scif4_clk_c_mux[] = {
-	SCK4_C_MARK,
-};
-static const unsigned int scif4_ctrl_c_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
-};
-static const unsigned int scif4_ctrl_c_mux[] = {
-	RTS4_N_C_MARK, CTS4_N_C_MARK,
-};
-/* - SCIF5 ------------------------------------------------------------------ */
-static const unsigned int scif5_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
-};
-static const unsigned int scif5_data_mux[] = {
-	RX5_MARK, TX5_MARK,
-};
-static const unsigned int scif5_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int scif5_clk_mux[] = {
-	SCK5_MARK,
-};
-
-/* - SCIF Clock ------------------------------------------------------------- */
-static const unsigned int scif_clk_a_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(6, 23),
-};
-static const unsigned int scif_clk_a_mux[] = {
-	SCIF_CLK_A_MARK,
-};
-static const unsigned int scif_clk_b_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(5, 9),
-};
-static const unsigned int scif_clk_b_mux[] = {
-	SCIF_CLK_B_MARK,
-};
-
-/* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 2),
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SD0_DAT0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
-	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
-};
-static const unsigned int sdhi0_data4_mux[] = {
-	SD0_DAT0_MARK, SD0_DAT1_MARK,
-	SD0_DAT2_MARK, SD0_DAT3_MARK,
-};
-static const unsigned int sdhi0_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
-};
-static const unsigned int sdhi0_ctrl_mux[] = {
-	SD0_CLK_MARK, SD0_CMD_MARK,
-};
-static const unsigned int sdhi0_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(3, 12),
-};
-static const unsigned int sdhi0_cd_mux[] = {
-	SD0_CD_MARK,
-};
-static const unsigned int sdhi0_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(3, 13),
-};
-static const unsigned int sdhi0_wp_mux[] = {
-	SD0_WP_MARK,
-};
-/* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 8),
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	SD1_DAT0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-};
-static const unsigned int sdhi1_data4_mux[] = {
-	SD1_DAT0_MARK, SD1_DAT1_MARK,
-	SD1_DAT2_MARK, SD1_DAT3_MARK,
-};
-static const unsigned int sdhi1_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-};
-static const unsigned int sdhi1_ctrl_mux[] = {
-	SD1_CLK_MARK, SD1_CMD_MARK,
-};
-static const unsigned int sdhi1_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(3, 14),
-};
-static const unsigned int sdhi1_cd_mux[] = {
-	SD1_CD_MARK,
-};
-static const unsigned int sdhi1_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(3, 15),
-};
-static const unsigned int sdhi1_wp_mux[] = {
-	SD1_WP_MARK,
-};
-/* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(4, 2),
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SD2_DAT0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-};
-static const unsigned int sdhi2_data4_mux[] = {
-	SD2_DAT0_MARK, SD2_DAT1_MARK,
-	SD2_DAT2_MARK, SD2_DAT3_MARK,
-};
-static const unsigned int sdhi2_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
-	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
-	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-};
-static const unsigned int sdhi2_data8_mux[] = {
-	SD2_DAT0_MARK, SD2_DAT1_MARK,
-	SD2_DAT2_MARK, SD2_DAT3_MARK,
-	SD2_DAT4_MARK, SD2_DAT5_MARK,
-	SD2_DAT6_MARK, SD2_DAT7_MARK,
-};
-static const unsigned int sdhi2_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
-};
-static const unsigned int sdhi2_ctrl_mux[] = {
-	SD2_CLK_MARK, SD2_CMD_MARK,
-};
-static const unsigned int sdhi2_cd_a_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(4, 13),
-};
-static const unsigned int sdhi2_cd_a_mux[] = {
-	SD2_CD_A_MARK,
-};
-static const unsigned int sdhi2_cd_b_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(5, 10),
-};
-static const unsigned int sdhi2_cd_b_mux[] = {
-	SD2_CD_B_MARK,
-};
-static const unsigned int sdhi2_wp_a_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(4, 14),
-};
-static const unsigned int sdhi2_wp_a_mux[] = {
-	SD2_WP_A_MARK,
-};
-static const unsigned int sdhi2_wp_b_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(5, 11),
-};
-static const unsigned int sdhi2_wp_b_mux[] = {
-	SD2_WP_B_MARK,
-};
-static const unsigned int sdhi2_ds_pins[] = {
-	/* DS */
-	RCAR_GP_PIN(4, 6),
-};
-static const unsigned int sdhi2_ds_mux[] = {
-	SD2_DS_MARK,
-};
-/* - SDHI3 ------------------------------------------------------------------ */
-static const unsigned int sdhi3_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(4, 9),
-};
-static const unsigned int sdhi3_data1_mux[] = {
-	SD3_DAT0_MARK,
-};
-static const unsigned int sdhi3_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
-	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
-};
-static const unsigned int sdhi3_data4_mux[] = {
-	SD3_DAT0_MARK, SD3_DAT1_MARK,
-	SD3_DAT2_MARK, SD3_DAT3_MARK,
-};
-static const unsigned int sdhi3_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
-	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
-	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
-	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
-};
-static const unsigned int sdhi3_data8_mux[] = {
-	SD3_DAT0_MARK, SD3_DAT1_MARK,
-	SD3_DAT2_MARK, SD3_DAT3_MARK,
-	SD3_DAT4_MARK, SD3_DAT5_MARK,
-	SD3_DAT6_MARK, SD3_DAT7_MARK,
-};
-static const unsigned int sdhi3_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
-};
-static const unsigned int sdhi3_ctrl_mux[] = {
-	SD3_CLK_MARK, SD3_CMD_MARK,
-};
-static const unsigned int sdhi3_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(4, 15),
-};
-static const unsigned int sdhi3_cd_mux[] = {
-	SD3_CD_MARK,
-};
-static const unsigned int sdhi3_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(4, 16),
-};
-static const unsigned int sdhi3_wp_mux[] = {
-	SD3_WP_MARK,
-};
-static const unsigned int sdhi3_ds_pins[] = {
-	/* DS */
-	RCAR_GP_PIN(4, 17),
-};
-static const unsigned int sdhi3_ds_mux[] = {
-	SD3_DS_MARK,
-};
-
-/* - SSI -------------------------------------------------------------------- */
-static const unsigned int ssi0_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 2),
-};
-static const unsigned int ssi0_data_mux[] = {
-	SSI_SDATA0_MARK,
-};
-static const unsigned int ssi01239_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
-};
-static const unsigned int ssi01239_ctrl_mux[] = {
-	SSI_SCK01239_MARK, SSI_WS01239_MARK,
-};
-static const unsigned int ssi1_data_a_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 3),
-};
-static const unsigned int ssi1_data_a_mux[] = {
-	SSI_SDATA1_A_MARK,
-};
-static const unsigned int ssi1_data_b_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(5, 12),
-};
-static const unsigned int ssi1_data_b_mux[] = {
-	SSI_SDATA1_B_MARK,
-};
-static const unsigned int ssi1_ctrl_a_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
-};
-static const unsigned int ssi1_ctrl_a_mux[] = {
-	SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
-};
-static const unsigned int ssi1_ctrl_b_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
-};
-static const unsigned int ssi1_ctrl_b_mux[] = {
-	SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
-};
-static const unsigned int ssi2_data_a_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 4),
-};
-static const unsigned int ssi2_data_a_mux[] = {
-	SSI_SDATA2_A_MARK,
-};
-static const unsigned int ssi2_data_b_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(5, 13),
-};
-static const unsigned int ssi2_data_b_mux[] = {
-	SSI_SDATA2_B_MARK,
-};
-static const unsigned int ssi2_ctrl_a_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
-};
-static const unsigned int ssi2_ctrl_a_mux[] = {
-	SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
-};
-static const unsigned int ssi2_ctrl_b_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
-};
-static const unsigned int ssi2_ctrl_b_mux[] = {
-	SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
-};
-static const unsigned int ssi3_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 7),
-};
-static const unsigned int ssi3_data_mux[] = {
-	SSI_SDATA3_MARK,
-};
-static const unsigned int ssi349_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
-};
-static const unsigned int ssi349_ctrl_mux[] = {
-	SSI_SCK349_MARK, SSI_WS349_MARK,
-};
-static const unsigned int ssi4_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 10),
-};
-static const unsigned int ssi4_data_mux[] = {
-	SSI_SDATA4_MARK,
-};
-static const unsigned int ssi4_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
-};
-static const unsigned int ssi4_ctrl_mux[] = {
-	SSI_SCK4_MARK, SSI_WS4_MARK,
-};
-static const unsigned int ssi5_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 13),
-};
-static const unsigned int ssi5_data_mux[] = {
-	SSI_SDATA5_MARK,
-};
-static const unsigned int ssi5_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
-};
-static const unsigned int ssi5_ctrl_mux[] = {
-	SSI_SCK5_MARK, SSI_WS5_MARK,
-};
-static const unsigned int ssi6_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 16),
-};
-static const unsigned int ssi6_data_mux[] = {
-	SSI_SDATA6_MARK,
-};
-static const unsigned int ssi6_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
-};
-static const unsigned int ssi6_ctrl_mux[] = {
-	SSI_SCK6_MARK, SSI_WS6_MARK,
-};
-static const unsigned int ssi7_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 19),
-};
-static const unsigned int ssi7_data_mux[] = {
-	SSI_SDATA7_MARK,
-};
-static const unsigned int ssi78_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
-};
-static const unsigned int ssi78_ctrl_mux[] = {
-	SSI_SCK78_MARK, SSI_WS78_MARK,
-};
-static const unsigned int ssi8_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 20),
-};
-static const unsigned int ssi8_data_mux[] = {
-	SSI_SDATA8_MARK,
-};
-static const unsigned int ssi9_data_a_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int ssi9_data_a_mux[] = {
-	SSI_SDATA9_A_MARK,
-};
-static const unsigned int ssi9_data_b_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(5, 14),
-};
-static const unsigned int ssi9_data_b_mux[] = {
-	SSI_SDATA9_B_MARK,
-};
-static const unsigned int ssi9_ctrl_a_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
-};
-static const unsigned int ssi9_ctrl_a_mux[] = {
-	SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
-};
-static const unsigned int ssi9_ctrl_b_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
-};
-static const unsigned int ssi9_ctrl_b_mux[] = {
-	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
-};
-
-/* - TMU -------------------------------------------------------------------- */
-static const unsigned int tmu_tclk1_a_pins[] = {
-	/* TCLK */
-	RCAR_GP_PIN(6, 23),
-};
-static const unsigned int tmu_tclk1_a_mux[] = {
-	TCLK1_A_MARK,
-};
-static const unsigned int tmu_tclk1_b_pins[] = {
-	/* TCLK */
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int tmu_tclk1_b_mux[] = {
-	TCLK1_B_MARK,
-};
-static const unsigned int tmu_tclk2_a_pins[] = {
-	/* TCLK */
-	RCAR_GP_PIN(6, 19),
-};
-static const unsigned int tmu_tclk2_a_mux[] = {
-	TCLK2_A_MARK,
-};
-static const unsigned int tmu_tclk2_b_pins[] = {
-	/* TCLK */
-	RCAR_GP_PIN(6, 28),
-};
-static const unsigned int tmu_tclk2_b_mux[] = {
-	TCLK2_B_MARK,
-};
-
-/* - TPU ------------------------------------------------------------------- */
-static const unsigned int tpu_to0_pins[] = {
-	/* TPU0TO0 */
-	RCAR_GP_PIN(6, 28),
-};
-static const unsigned int tpu_to0_mux[] = {
-	TPU0TO0_MARK,
-};
-static const unsigned int tpu_to1_pins[] = {
-	/* TPU0TO1 */
-	RCAR_GP_PIN(6, 29),
-};
-static const unsigned int tpu_to1_mux[] = {
-	TPU0TO1_MARK,
-};
-static const unsigned int tpu_to2_pins[] = {
-	/* TPU0TO2 */
-	RCAR_GP_PIN(6, 30),
-};
-static const unsigned int tpu_to2_mux[] = {
-	TPU0TO2_MARK,
-};
-static const unsigned int tpu_to3_pins[] = {
-	/* TPU0TO3 */
-	RCAR_GP_PIN(6, 31),
-};
-static const unsigned int tpu_to3_mux[] = {
-	TPU0TO3_MARK,
-};
-
-/* - USB0 ------------------------------------------------------------------- */
-static const unsigned int usb0_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
-};
-static const unsigned int usb0_mux[] = {
-	USB0_PWEN_MARK, USB0_OVC_MARK,
-};
-/* - USB1 ------------------------------------------------------------------- */
-static const unsigned int usb1_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
-};
-static const unsigned int usb1_mux[] = {
-	USB1_PWEN_MARK, USB1_OVC_MARK,
-};
-/* - USB2 ------------------------------------------------------------------- */
-static const unsigned int usb2_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
-};
-static const unsigned int usb2_mux[] = {
-	USB2_PWEN_MARK, USB2_OVC_MARK,
-};
-
-/* - USB30 ------------------------------------------------------------------ */
-static const unsigned int usb30_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
-};
-static const unsigned int usb30_mux[] = {
-	USB30_PWEN_MARK, USB30_OVC_MARK,
-};
-/* - USB31 ------------------------------------------------------------------ */
-static const unsigned int usb31_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
-};
-static const unsigned int usb31_mux[] = {
-	USB31_PWEN_MARK, USB31_OVC_MARK,
-};
-
-static const struct sh_pfc_pin_group pinmux_groups[] = {
-	SH_PFC_PIN_GROUP(audio_clk_a_a),
-	SH_PFC_PIN_GROUP(audio_clk_a_b),
-	SH_PFC_PIN_GROUP(audio_clk_a_c),
-	SH_PFC_PIN_GROUP(audio_clk_b_a),
-	SH_PFC_PIN_GROUP(audio_clk_b_b),
-	SH_PFC_PIN_GROUP(audio_clk_c_a),
-	SH_PFC_PIN_GROUP(audio_clk_c_b),
-	SH_PFC_PIN_GROUP(audio_clkout_a),
-	SH_PFC_PIN_GROUP(audio_clkout_b),
-	SH_PFC_PIN_GROUP(audio_clkout_c),
-	SH_PFC_PIN_GROUP(audio_clkout_d),
-	SH_PFC_PIN_GROUP(audio_clkout1_a),
-	SH_PFC_PIN_GROUP(audio_clkout1_b),
-	SH_PFC_PIN_GROUP(audio_clkout2_a),
-	SH_PFC_PIN_GROUP(audio_clkout2_b),
-	SH_PFC_PIN_GROUP(audio_clkout3_a),
-	SH_PFC_PIN_GROUP(audio_clkout3_b),
-	SH_PFC_PIN_GROUP(avb_link),
-	SH_PFC_PIN_GROUP(avb_magic),
-	SH_PFC_PIN_GROUP(avb_phy_int),
-	SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),	/* Deprecated */
-	SH_PFC_PIN_GROUP(avb_mdio),
-	SH_PFC_PIN_GROUP(avb_mii),
-	SH_PFC_PIN_GROUP(avb_avtp_pps),
-	SH_PFC_PIN_GROUP(avb_avtp_match_a),
-	SH_PFC_PIN_GROUP(avb_avtp_capture_a),
-	SH_PFC_PIN_GROUP(avb_avtp_match_b),
-	SH_PFC_PIN_GROUP(avb_avtp_capture_b),
-	SH_PFC_PIN_GROUP(can0_data_a),
-	SH_PFC_PIN_GROUP(can0_data_b),
-	SH_PFC_PIN_GROUP(can1_data),
-	SH_PFC_PIN_GROUP(can_clk),
-	SH_PFC_PIN_GROUP(canfd0_data_a),
-	SH_PFC_PIN_GROUP(canfd0_data_b),
-	SH_PFC_PIN_GROUP(canfd1_data),
-	SH_PFC_PIN_GROUP(drif0_ctrl_a),
-	SH_PFC_PIN_GROUP(drif0_data0_a),
-	SH_PFC_PIN_GROUP(drif0_data1_a),
-	SH_PFC_PIN_GROUP(drif0_ctrl_b),
-	SH_PFC_PIN_GROUP(drif0_data0_b),
-	SH_PFC_PIN_GROUP(drif0_data1_b),
-	SH_PFC_PIN_GROUP(drif0_ctrl_c),
-	SH_PFC_PIN_GROUP(drif0_data0_c),
-	SH_PFC_PIN_GROUP(drif0_data1_c),
-	SH_PFC_PIN_GROUP(drif1_ctrl_a),
-	SH_PFC_PIN_GROUP(drif1_data0_a),
-	SH_PFC_PIN_GROUP(drif1_data1_a),
-	SH_PFC_PIN_GROUP(drif1_ctrl_b),
-	SH_PFC_PIN_GROUP(drif1_data0_b),
-	SH_PFC_PIN_GROUP(drif1_data1_b),
-	SH_PFC_PIN_GROUP(drif1_ctrl_c),
-	SH_PFC_PIN_GROUP(drif1_data0_c),
-	SH_PFC_PIN_GROUP(drif1_data1_c),
-	SH_PFC_PIN_GROUP(drif2_ctrl_a),
-	SH_PFC_PIN_GROUP(drif2_data0_a),
-	SH_PFC_PIN_GROUP(drif2_data1_a),
-	SH_PFC_PIN_GROUP(drif2_ctrl_b),
-	SH_PFC_PIN_GROUP(drif2_data0_b),
-	SH_PFC_PIN_GROUP(drif2_data1_b),
-	SH_PFC_PIN_GROUP(drif3_ctrl_a),
-	SH_PFC_PIN_GROUP(drif3_data0_a),
-	SH_PFC_PIN_GROUP(drif3_data1_a),
-	SH_PFC_PIN_GROUP(drif3_ctrl_b),
-	SH_PFC_PIN_GROUP(drif3_data0_b),
-	SH_PFC_PIN_GROUP(drif3_data1_b),
-	SH_PFC_PIN_GROUP(du_rgb666),
-	SH_PFC_PIN_GROUP(du_rgb888),
-	SH_PFC_PIN_GROUP(du_clk_out_0),
-	SH_PFC_PIN_GROUP(du_clk_out_1),
-	SH_PFC_PIN_GROUP(du_sync),
-	SH_PFC_PIN_GROUP(du_oddf),
-	SH_PFC_PIN_GROUP(du_cde),
-	SH_PFC_PIN_GROUP(du_disp),
-	SH_PFC_PIN_GROUP(hscif0_data),
-	SH_PFC_PIN_GROUP(hscif0_clk),
-	SH_PFC_PIN_GROUP(hscif0_ctrl),
-	SH_PFC_PIN_GROUP(hscif1_data_a),
-	SH_PFC_PIN_GROUP(hscif1_clk_a),
-	SH_PFC_PIN_GROUP(hscif1_ctrl_a),
-	SH_PFC_PIN_GROUP(hscif1_data_b),
-	SH_PFC_PIN_GROUP(hscif1_clk_b),
-	SH_PFC_PIN_GROUP(hscif1_ctrl_b),
-	SH_PFC_PIN_GROUP(hscif2_data_a),
-	SH_PFC_PIN_GROUP(hscif2_clk_a),
-	SH_PFC_PIN_GROUP(hscif2_ctrl_a),
-	SH_PFC_PIN_GROUP(hscif2_data_b),
-	SH_PFC_PIN_GROUP(hscif2_clk_b),
-	SH_PFC_PIN_GROUP(hscif2_ctrl_b),
-	SH_PFC_PIN_GROUP(hscif3_data_a),
-	SH_PFC_PIN_GROUP(hscif3_clk),
-	SH_PFC_PIN_GROUP(hscif3_ctrl),
-	SH_PFC_PIN_GROUP(hscif3_data_b),
-	SH_PFC_PIN_GROUP(hscif3_data_c),
-	SH_PFC_PIN_GROUP(hscif3_data_d),
-	SH_PFC_PIN_GROUP(hscif4_data_a),
-	SH_PFC_PIN_GROUP(hscif4_clk),
-	SH_PFC_PIN_GROUP(hscif4_ctrl),
-	SH_PFC_PIN_GROUP(hscif4_data_b),
-	SH_PFC_PIN_GROUP(i2c0),
-	SH_PFC_PIN_GROUP(i2c1_a),
-	SH_PFC_PIN_GROUP(i2c1_b),
-	SH_PFC_PIN_GROUP(i2c2_a),
-	SH_PFC_PIN_GROUP(i2c2_b),
-	SH_PFC_PIN_GROUP(i2c3),
-	SH_PFC_PIN_GROUP(i2c5),
-	SH_PFC_PIN_GROUP(i2c6_a),
-	SH_PFC_PIN_GROUP(i2c6_b),
-	SH_PFC_PIN_GROUP(i2c6_c),
-	SH_PFC_PIN_GROUP(intc_ex_irq0),
-	SH_PFC_PIN_GROUP(intc_ex_irq1),
-	SH_PFC_PIN_GROUP(intc_ex_irq2),
-	SH_PFC_PIN_GROUP(intc_ex_irq3),
-	SH_PFC_PIN_GROUP(intc_ex_irq4),
-	SH_PFC_PIN_GROUP(intc_ex_irq5),
-	SH_PFC_PIN_GROUP(msiof0_clk),
-	SH_PFC_PIN_GROUP(msiof0_sync),
-	SH_PFC_PIN_GROUP(msiof0_ss1),
-	SH_PFC_PIN_GROUP(msiof0_ss2),
-	SH_PFC_PIN_GROUP(msiof0_txd),
-	SH_PFC_PIN_GROUP(msiof0_rxd),
-	SH_PFC_PIN_GROUP(msiof1_clk_a),
-	SH_PFC_PIN_GROUP(msiof1_sync_a),
-	SH_PFC_PIN_GROUP(msiof1_ss1_a),
-	SH_PFC_PIN_GROUP(msiof1_ss2_a),
-	SH_PFC_PIN_GROUP(msiof1_txd_a),
-	SH_PFC_PIN_GROUP(msiof1_rxd_a),
-	SH_PFC_PIN_GROUP(msiof1_clk_b),
-	SH_PFC_PIN_GROUP(msiof1_sync_b),
-	SH_PFC_PIN_GROUP(msiof1_ss1_b),
-	SH_PFC_PIN_GROUP(msiof1_ss2_b),
-	SH_PFC_PIN_GROUP(msiof1_txd_b),
-	SH_PFC_PIN_GROUP(msiof1_rxd_b),
-	SH_PFC_PIN_GROUP(msiof1_clk_c),
-	SH_PFC_PIN_GROUP(msiof1_sync_c),
-	SH_PFC_PIN_GROUP(msiof1_ss1_c),
-	SH_PFC_PIN_GROUP(msiof1_ss2_c),
-	SH_PFC_PIN_GROUP(msiof1_txd_c),
-	SH_PFC_PIN_GROUP(msiof1_rxd_c),
-	SH_PFC_PIN_GROUP(msiof1_clk_d),
-	SH_PFC_PIN_GROUP(msiof1_sync_d),
-	SH_PFC_PIN_GROUP(msiof1_ss1_d),
-	SH_PFC_PIN_GROUP(msiof1_ss2_d),
-	SH_PFC_PIN_GROUP(msiof1_txd_d),
-	SH_PFC_PIN_GROUP(msiof1_rxd_d),
-	SH_PFC_PIN_GROUP(msiof1_clk_e),
-	SH_PFC_PIN_GROUP(msiof1_sync_e),
-	SH_PFC_PIN_GROUP(msiof1_ss1_e),
-	SH_PFC_PIN_GROUP(msiof1_ss2_e),
-	SH_PFC_PIN_GROUP(msiof1_txd_e),
-	SH_PFC_PIN_GROUP(msiof1_rxd_e),
-	SH_PFC_PIN_GROUP(msiof1_clk_f),
-	SH_PFC_PIN_GROUP(msiof1_sync_f),
-	SH_PFC_PIN_GROUP(msiof1_ss1_f),
-	SH_PFC_PIN_GROUP(msiof1_ss2_f),
-	SH_PFC_PIN_GROUP(msiof1_txd_f),
-	SH_PFC_PIN_GROUP(msiof1_rxd_f),
-	SH_PFC_PIN_GROUP(msiof1_clk_g),
-	SH_PFC_PIN_GROUP(msiof1_sync_g),
-	SH_PFC_PIN_GROUP(msiof1_ss1_g),
-	SH_PFC_PIN_GROUP(msiof1_ss2_g),
-	SH_PFC_PIN_GROUP(msiof1_txd_g),
-	SH_PFC_PIN_GROUP(msiof1_rxd_g),
-	SH_PFC_PIN_GROUP(msiof2_clk_a),
-	SH_PFC_PIN_GROUP(msiof2_sync_a),
-	SH_PFC_PIN_GROUP(msiof2_ss1_a),
-	SH_PFC_PIN_GROUP(msiof2_ss2_a),
-	SH_PFC_PIN_GROUP(msiof2_txd_a),
-	SH_PFC_PIN_GROUP(msiof2_rxd_a),
-	SH_PFC_PIN_GROUP(msiof2_clk_b),
-	SH_PFC_PIN_GROUP(msiof2_sync_b),
-	SH_PFC_PIN_GROUP(msiof2_ss1_b),
-	SH_PFC_PIN_GROUP(msiof2_ss2_b),
-	SH_PFC_PIN_GROUP(msiof2_txd_b),
-	SH_PFC_PIN_GROUP(msiof2_rxd_b),
-	SH_PFC_PIN_GROUP(msiof2_clk_c),
-	SH_PFC_PIN_GROUP(msiof2_sync_c),
-	SH_PFC_PIN_GROUP(msiof2_ss1_c),
-	SH_PFC_PIN_GROUP(msiof2_ss2_c),
-	SH_PFC_PIN_GROUP(msiof2_txd_c),
-	SH_PFC_PIN_GROUP(msiof2_rxd_c),
-	SH_PFC_PIN_GROUP(msiof2_clk_d),
-	SH_PFC_PIN_GROUP(msiof2_sync_d),
-	SH_PFC_PIN_GROUP(msiof2_ss1_d),
-	SH_PFC_PIN_GROUP(msiof2_ss2_d),
-	SH_PFC_PIN_GROUP(msiof2_txd_d),
-	SH_PFC_PIN_GROUP(msiof2_rxd_d),
-	SH_PFC_PIN_GROUP(msiof3_clk_a),
-	SH_PFC_PIN_GROUP(msiof3_sync_a),
-	SH_PFC_PIN_GROUP(msiof3_ss1_a),
-	SH_PFC_PIN_GROUP(msiof3_ss2_a),
-	SH_PFC_PIN_GROUP(msiof3_txd_a),
-	SH_PFC_PIN_GROUP(msiof3_rxd_a),
-	SH_PFC_PIN_GROUP(msiof3_clk_b),
-	SH_PFC_PIN_GROUP(msiof3_sync_b),
-	SH_PFC_PIN_GROUP(msiof3_ss1_b),
-	SH_PFC_PIN_GROUP(msiof3_ss2_b),
-	SH_PFC_PIN_GROUP(msiof3_txd_b),
-	SH_PFC_PIN_GROUP(msiof3_rxd_b),
-	SH_PFC_PIN_GROUP(msiof3_clk_c),
-	SH_PFC_PIN_GROUP(msiof3_sync_c),
-	SH_PFC_PIN_GROUP(msiof3_txd_c),
-	SH_PFC_PIN_GROUP(msiof3_rxd_c),
-	SH_PFC_PIN_GROUP(msiof3_clk_d),
-	SH_PFC_PIN_GROUP(msiof3_sync_d),
-	SH_PFC_PIN_GROUP(msiof3_ss1_d),
-	SH_PFC_PIN_GROUP(msiof3_txd_d),
-	SH_PFC_PIN_GROUP(msiof3_rxd_d),
-	SH_PFC_PIN_GROUP(pwm0),
-	SH_PFC_PIN_GROUP(pwm1_a),
-	SH_PFC_PIN_GROUP(pwm1_b),
-	SH_PFC_PIN_GROUP(pwm2_a),
-	SH_PFC_PIN_GROUP(pwm2_b),
-	SH_PFC_PIN_GROUP(pwm3_a),
-	SH_PFC_PIN_GROUP(pwm3_b),
-	SH_PFC_PIN_GROUP(pwm4_a),
-	SH_PFC_PIN_GROUP(pwm4_b),
-	SH_PFC_PIN_GROUP(pwm5_a),
-	SH_PFC_PIN_GROUP(pwm5_b),
-	SH_PFC_PIN_GROUP(pwm6_a),
-	SH_PFC_PIN_GROUP(pwm6_b),
-	SH_PFC_PIN_GROUP(qspi0_ctrl),
-	SH_PFC_PIN_GROUP(qspi0_data2),
-	SH_PFC_PIN_GROUP(qspi0_data4),
-	SH_PFC_PIN_GROUP(qspi1_ctrl),
-	SH_PFC_PIN_GROUP(qspi1_data2),
-	SH_PFC_PIN_GROUP(qspi1_data4),
-	SH_PFC_PIN_GROUP(sata0_devslp_a),
-	SH_PFC_PIN_GROUP(sata0_devslp_b),
-	SH_PFC_PIN_GROUP(scif0_data),
-	SH_PFC_PIN_GROUP(scif0_clk),
-	SH_PFC_PIN_GROUP(scif0_ctrl),
-	SH_PFC_PIN_GROUP(scif1_data_a),
-	SH_PFC_PIN_GROUP(scif1_clk),
-	SH_PFC_PIN_GROUP(scif1_ctrl),
-	SH_PFC_PIN_GROUP(scif1_data_b),
-	SH_PFC_PIN_GROUP(scif2_data_a),
-	SH_PFC_PIN_GROUP(scif2_clk),
-	SH_PFC_PIN_GROUP(scif2_data_b),
-	SH_PFC_PIN_GROUP(scif3_data_a),
-	SH_PFC_PIN_GROUP(scif3_clk),
-	SH_PFC_PIN_GROUP(scif3_ctrl),
-	SH_PFC_PIN_GROUP(scif3_data_b),
-	SH_PFC_PIN_GROUP(scif4_data_a),
-	SH_PFC_PIN_GROUP(scif4_clk_a),
-	SH_PFC_PIN_GROUP(scif4_ctrl_a),
-	SH_PFC_PIN_GROUP(scif4_data_b),
-	SH_PFC_PIN_GROUP(scif4_clk_b),
-	SH_PFC_PIN_GROUP(scif4_ctrl_b),
-	SH_PFC_PIN_GROUP(scif4_data_c),
-	SH_PFC_PIN_GROUP(scif4_clk_c),
-	SH_PFC_PIN_GROUP(scif4_ctrl_c),
-	SH_PFC_PIN_GROUP(scif5_data),
-	SH_PFC_PIN_GROUP(scif5_clk),
-	SH_PFC_PIN_GROUP(scif_clk_a),
-	SH_PFC_PIN_GROUP(scif_clk_b),
-	SH_PFC_PIN_GROUP(sdhi0_data1),
-	SH_PFC_PIN_GROUP(sdhi0_data4),
-	SH_PFC_PIN_GROUP(sdhi0_ctrl),
-	SH_PFC_PIN_GROUP(sdhi0_cd),
-	SH_PFC_PIN_GROUP(sdhi0_wp),
-	SH_PFC_PIN_GROUP(sdhi1_data1),
-	SH_PFC_PIN_GROUP(sdhi1_data4),
-	SH_PFC_PIN_GROUP(sdhi1_ctrl),
-	SH_PFC_PIN_GROUP(sdhi1_cd),
-	SH_PFC_PIN_GROUP(sdhi1_wp),
-	SH_PFC_PIN_GROUP(sdhi2_data1),
-	SH_PFC_PIN_GROUP(sdhi2_data4),
-	SH_PFC_PIN_GROUP(sdhi2_data8),
-	SH_PFC_PIN_GROUP(sdhi2_ctrl),
-	SH_PFC_PIN_GROUP(sdhi2_cd_a),
-	SH_PFC_PIN_GROUP(sdhi2_wp_a),
-	SH_PFC_PIN_GROUP(sdhi2_cd_b),
-	SH_PFC_PIN_GROUP(sdhi2_wp_b),
-	SH_PFC_PIN_GROUP(sdhi2_ds),
-	SH_PFC_PIN_GROUP(sdhi3_data1),
-	SH_PFC_PIN_GROUP(sdhi3_data4),
-	SH_PFC_PIN_GROUP(sdhi3_data8),
-	SH_PFC_PIN_GROUP(sdhi3_ctrl),
-	SH_PFC_PIN_GROUP(sdhi3_cd),
-	SH_PFC_PIN_GROUP(sdhi3_wp),
-	SH_PFC_PIN_GROUP(sdhi3_ds),
-	SH_PFC_PIN_GROUP(ssi0_data),
-	SH_PFC_PIN_GROUP(ssi01239_ctrl),
-	SH_PFC_PIN_GROUP(ssi1_data_a),
-	SH_PFC_PIN_GROUP(ssi1_data_b),
-	SH_PFC_PIN_GROUP(ssi1_ctrl_a),
-	SH_PFC_PIN_GROUP(ssi1_ctrl_b),
-	SH_PFC_PIN_GROUP(ssi2_data_a),
-	SH_PFC_PIN_GROUP(ssi2_data_b),
-	SH_PFC_PIN_GROUP(ssi2_ctrl_a),
-	SH_PFC_PIN_GROUP(ssi2_ctrl_b),
-	SH_PFC_PIN_GROUP(ssi3_data),
-	SH_PFC_PIN_GROUP(ssi349_ctrl),
-	SH_PFC_PIN_GROUP(ssi4_data),
-	SH_PFC_PIN_GROUP(ssi4_ctrl),
-	SH_PFC_PIN_GROUP(ssi5_data),
-	SH_PFC_PIN_GROUP(ssi5_ctrl),
-	SH_PFC_PIN_GROUP(ssi6_data),
-	SH_PFC_PIN_GROUP(ssi6_ctrl),
-	SH_PFC_PIN_GROUP(ssi7_data),
-	SH_PFC_PIN_GROUP(ssi78_ctrl),
-	SH_PFC_PIN_GROUP(ssi8_data),
-	SH_PFC_PIN_GROUP(ssi9_data_a),
-	SH_PFC_PIN_GROUP(ssi9_data_b),
-	SH_PFC_PIN_GROUP(ssi9_ctrl_a),
-	SH_PFC_PIN_GROUP(ssi9_ctrl_b),
-	SH_PFC_PIN_GROUP(tmu_tclk1_a),
-	SH_PFC_PIN_GROUP(tmu_tclk1_b),
-	SH_PFC_PIN_GROUP(tmu_tclk2_a),
-	SH_PFC_PIN_GROUP(tmu_tclk2_b),
-	SH_PFC_PIN_GROUP(tpu_to0),
-	SH_PFC_PIN_GROUP(tpu_to1),
-	SH_PFC_PIN_GROUP(tpu_to2),
-	SH_PFC_PIN_GROUP(tpu_to3),
-	SH_PFC_PIN_GROUP(usb0),
-	SH_PFC_PIN_GROUP(usb1),
-	SH_PFC_PIN_GROUP(usb2),
-	SH_PFC_PIN_GROUP(usb30),
-	SH_PFC_PIN_GROUP(usb31),
-};
-
-static const char * const audio_clk_groups[] = {
-	"audio_clk_a_a",
-	"audio_clk_a_b",
-	"audio_clk_a_c",
-	"audio_clk_b_a",
-	"audio_clk_b_b",
-	"audio_clk_c_a",
-	"audio_clk_c_b",
-	"audio_clkout_a",
-	"audio_clkout_b",
-	"audio_clkout_c",
-	"audio_clkout_d",
-	"audio_clkout1_a",
-	"audio_clkout1_b",
-	"audio_clkout2_a",
-	"audio_clkout2_b",
-	"audio_clkout3_a",
-	"audio_clkout3_b",
-};
-
-static const char * const avb_groups[] = {
-	"avb_link",
-	"avb_magic",
-	"avb_phy_int",
-	"avb_mdc",	/* Deprecated, please use "avb_mdio" instead */
-	"avb_mdio",
-	"avb_mii",
-	"avb_avtp_pps",
-	"avb_avtp_match_a",
-	"avb_avtp_capture_a",
-	"avb_avtp_match_b",
-	"avb_avtp_capture_b",
-};
-
-static const char * const can0_groups[] = {
-	"can0_data_a",
-	"can0_data_b",
-};
-
-static const char * const can1_groups[] = {
-	"can1_data",
-};
-
-static const char * const can_clk_groups[] = {
-	"can_clk",
-};
-
-static const char * const canfd0_groups[] = {
-	"canfd0_data_a",
-	"canfd0_data_b",
-};
-
-static const char * const canfd1_groups[] = {
-	"canfd1_data",
-};
-
-static const char * const drif0_groups[] = {
-	"drif0_ctrl_a",
-	"drif0_data0_a",
-	"drif0_data1_a",
-	"drif0_ctrl_b",
-	"drif0_data0_b",
-	"drif0_data1_b",
-	"drif0_ctrl_c",
-	"drif0_data0_c",
-	"drif0_data1_c",
-};
-
-static const char * const drif1_groups[] = {
-	"drif1_ctrl_a",
-	"drif1_data0_a",
-	"drif1_data1_a",
-	"drif1_ctrl_b",
-	"drif1_data0_b",
-	"drif1_data1_b",
-	"drif1_ctrl_c",
-	"drif1_data0_c",
-	"drif1_data1_c",
-};
-
-static const char * const drif2_groups[] = {
-	"drif2_ctrl_a",
-	"drif2_data0_a",
-	"drif2_data1_a",
-	"drif2_ctrl_b",
-	"drif2_data0_b",
-	"drif2_data1_b",
-};
-
-static const char * const drif3_groups[] = {
-	"drif3_ctrl_a",
-	"drif3_data0_a",
-	"drif3_data1_a",
-	"drif3_ctrl_b",
-	"drif3_data0_b",
-	"drif3_data1_b",
-};
-
-static const char * const du_groups[] = {
-	"du_rgb666",
-	"du_rgb888",
-	"du_clk_out_0",
-	"du_clk_out_1",
-	"du_sync",
-	"du_oddf",
-	"du_cde",
-	"du_disp",
-};
-
-static const char * const hscif0_groups[] = {
-	"hscif0_data",
-	"hscif0_clk",
-	"hscif0_ctrl",
-};
-
-static const char * const hscif1_groups[] = {
-	"hscif1_data_a",
-	"hscif1_clk_a",
-	"hscif1_ctrl_a",
-	"hscif1_data_b",
-	"hscif1_clk_b",
-	"hscif1_ctrl_b",
-};
-
-static const char * const hscif2_groups[] = {
-	"hscif2_data_a",
-	"hscif2_clk_a",
-	"hscif2_ctrl_a",
-	"hscif2_data_b",
-	"hscif2_clk_b",
-	"hscif2_ctrl_b",
-};
-
-static const char * const hscif3_groups[] = {
-	"hscif3_data_a",
-	"hscif3_clk",
-	"hscif3_ctrl",
-	"hscif3_data_b",
-	"hscif3_data_c",
-	"hscif3_data_d",
-};
-
-static const char * const hscif4_groups[] = {
-	"hscif4_data_a",
-	"hscif4_clk",
-	"hscif4_ctrl",
-	"hscif4_data_b",
-};
-
-static const char * const i2c0_groups[] = {
-	"i2c0",
-};
-
-static const char * const i2c1_groups[] = {
-	"i2c1_a",
-	"i2c1_b",
-};
-
-static const char * const i2c2_groups[] = {
-	"i2c2_a",
-	"i2c2_b",
-};
-
-static const char * const i2c3_groups[] = {
-	"i2c3",
-};
-
-static const char * const i2c5_groups[] = {
-	"i2c5",
-};
-
-static const char * const i2c6_groups[] = {
-	"i2c6_a",
-	"i2c6_b",
-	"i2c6_c",
-};
-
-static const char * const intc_ex_groups[] = {
-	"intc_ex_irq0",
-	"intc_ex_irq1",
-	"intc_ex_irq2",
-	"intc_ex_irq3",
-	"intc_ex_irq4",
-	"intc_ex_irq5",
-};
-
-static const char * const msiof0_groups[] = {
-	"msiof0_clk",
-	"msiof0_sync",
-	"msiof0_ss1",
-	"msiof0_ss2",
-	"msiof0_txd",
-	"msiof0_rxd",
-};
-
-static const char * const msiof1_groups[] = {
-	"msiof1_clk_a",
-	"msiof1_sync_a",
-	"msiof1_ss1_a",
-	"msiof1_ss2_a",
-	"msiof1_txd_a",
-	"msiof1_rxd_a",
-	"msiof1_clk_b",
-	"msiof1_sync_b",
-	"msiof1_ss1_b",
-	"msiof1_ss2_b",
-	"msiof1_txd_b",
-	"msiof1_rxd_b",
-	"msiof1_clk_c",
-	"msiof1_sync_c",
-	"msiof1_ss1_c",
-	"msiof1_ss2_c",
-	"msiof1_txd_c",
-	"msiof1_rxd_c",
-	"msiof1_clk_d",
-	"msiof1_sync_d",
-	"msiof1_ss1_d",
-	"msiof1_ss2_d",
-	"msiof1_txd_d",
-	"msiof1_rxd_d",
-	"msiof1_clk_e",
-	"msiof1_sync_e",
-	"msiof1_ss1_e",
-	"msiof1_ss2_e",
-	"msiof1_txd_e",
-	"msiof1_rxd_e",
-	"msiof1_clk_f",
-	"msiof1_sync_f",
-	"msiof1_ss1_f",
-	"msiof1_ss2_f",
-	"msiof1_txd_f",
-	"msiof1_rxd_f",
-	"msiof1_clk_g",
-	"msiof1_sync_g",
-	"msiof1_ss1_g",
-	"msiof1_ss2_g",
-	"msiof1_txd_g",
-	"msiof1_rxd_g",
-};
-
-static const char * const msiof2_groups[] = {
-	"msiof2_clk_a",
-	"msiof2_sync_a",
-	"msiof2_ss1_a",
-	"msiof2_ss2_a",
-	"msiof2_txd_a",
-	"msiof2_rxd_a",
-	"msiof2_clk_b",
-	"msiof2_sync_b",
-	"msiof2_ss1_b",
-	"msiof2_ss2_b",
-	"msiof2_txd_b",
-	"msiof2_rxd_b",
-	"msiof2_clk_c",
-	"msiof2_sync_c",
-	"msiof2_ss1_c",
-	"msiof2_ss2_c",
-	"msiof2_txd_c",
-	"msiof2_rxd_c",
-	"msiof2_clk_d",
-	"msiof2_sync_d",
-	"msiof2_ss1_d",
-	"msiof2_ss2_d",
-	"msiof2_txd_d",
-	"msiof2_rxd_d",
-};
-
-static const char * const msiof3_groups[] = {
-	"msiof3_clk_a",
-	"msiof3_sync_a",
-	"msiof3_ss1_a",
-	"msiof3_ss2_a",
-	"msiof3_txd_a",
-	"msiof3_rxd_a",
-	"msiof3_clk_b",
-	"msiof3_sync_b",
-	"msiof3_ss1_b",
-	"msiof3_ss2_b",
-	"msiof3_txd_b",
-	"msiof3_rxd_b",
-	"msiof3_clk_c",
-	"msiof3_sync_c",
-	"msiof3_txd_c",
-	"msiof3_rxd_c",
-	"msiof3_clk_d",
-	"msiof3_sync_d",
-	"msiof3_ss1_d",
-	"msiof3_txd_d",
-	"msiof3_rxd_d",
-};
-
-static const char * const pwm0_groups[] = {
-	"pwm0",
-};
-
-static const char * const pwm1_groups[] = {
-	"pwm1_a",
-	"pwm1_b",
-};
-
-static const char * const pwm2_groups[] = {
-	"pwm2_a",
-	"pwm2_b",
-};
-
-static const char * const pwm3_groups[] = {
-	"pwm3_a",
-	"pwm3_b",
-};
-
-static const char * const pwm4_groups[] = {
-	"pwm4_a",
-	"pwm4_b",
-};
-
-static const char * const pwm5_groups[] = {
-	"pwm5_a",
-	"pwm5_b",
-};
-
-static const char * const pwm6_groups[] = {
-	"pwm6_a",
-	"pwm6_b",
-};
-
-static const char * const qspi0_groups[] = {
-	"qspi0_ctrl",
-	"qspi0_data2",
-	"qspi0_data4",
-};
-
-static const char * const qspi1_groups[] = {
-	"qspi1_ctrl",
-	"qspi1_data2",
-	"qspi1_data4",
-};
-
-static const char * const sata0_groups[] = {
-	"sata0_devslp_a",
-	"sata0_devslp_b",
-};
-
-static const char * const scif0_groups[] = {
-	"scif0_data",
-	"scif0_clk",
-	"scif0_ctrl",
-};
-
-static const char * const scif1_groups[] = {
-	"scif1_data_a",
-	"scif1_clk",
-	"scif1_ctrl",
-	"scif1_data_b",
-};
-
-static const char * const scif2_groups[] = {
-	"scif2_data_a",
-	"scif2_clk",
-	"scif2_data_b",
-};
-
-static const char * const scif3_groups[] = {
-	"scif3_data_a",
-	"scif3_clk",
-	"scif3_ctrl",
-	"scif3_data_b",
-};
-
-static const char * const scif4_groups[] = {
-	"scif4_data_a",
-	"scif4_clk_a",
-	"scif4_ctrl_a",
-	"scif4_data_b",
-	"scif4_clk_b",
-	"scif4_ctrl_b",
-	"scif4_data_c",
-	"scif4_clk_c",
-	"scif4_ctrl_c",
-};
-
-static const char * const scif5_groups[] = {
-	"scif5_data",
-	"scif5_clk",
-};
-
-static const char * const scif_clk_groups[] = {
-	"scif_clk_a",
-	"scif_clk_b",
-};
-
-static const char * const sdhi0_groups[] = {
-	"sdhi0_data1",
-	"sdhi0_data4",
-	"sdhi0_ctrl",
-	"sdhi0_cd",
-	"sdhi0_wp",
-};
-
-static const char * const sdhi1_groups[] = {
-	"sdhi1_data1",
-	"sdhi1_data4",
-	"sdhi1_ctrl",
-	"sdhi1_cd",
-	"sdhi1_wp",
-};
-
-static const char * const sdhi2_groups[] = {
-	"sdhi2_data1",
-	"sdhi2_data4",
-	"sdhi2_data8",
-	"sdhi2_ctrl",
-	"sdhi2_cd_a",
-	"sdhi2_wp_a",
-	"sdhi2_cd_b",
-	"sdhi2_wp_b",
-	"sdhi2_ds",
-};
-
-static const char * const sdhi3_groups[] = {
-	"sdhi3_data1",
-	"sdhi3_data4",
-	"sdhi3_data8",
-	"sdhi3_ctrl",
-	"sdhi3_cd",
-	"sdhi3_wp",
-	"sdhi3_ds",
-};
-
-static const char * const ssi_groups[] = {
-	"ssi0_data",
-	"ssi01239_ctrl",
-	"ssi1_data_a",
-	"ssi1_data_b",
-	"ssi1_ctrl_a",
-	"ssi1_ctrl_b",
-	"ssi2_data_a",
-	"ssi2_data_b",
-	"ssi2_ctrl_a",
-	"ssi2_ctrl_b",
-	"ssi3_data",
-	"ssi349_ctrl",
-	"ssi4_data",
-	"ssi4_ctrl",
-	"ssi5_data",
-	"ssi5_ctrl",
-	"ssi6_data",
-	"ssi6_ctrl",
-	"ssi7_data",
-	"ssi78_ctrl",
-	"ssi8_data",
-	"ssi9_data_a",
-	"ssi9_data_b",
-	"ssi9_ctrl_a",
-	"ssi9_ctrl_b",
-};
-
-static const char * const tmu_groups[] = {
-	"tmu_tclk1_a",
-	"tmu_tclk1_b",
-	"tmu_tclk2_a",
-	"tmu_tclk2_b",
-};
-
-static const char * const tpu_groups[] = {
-	"tpu_to0",
-	"tpu_to1",
-	"tpu_to2",
-	"tpu_to3",
-};
-
-static const char * const usb0_groups[] = {
-	"usb0",
-};
-
-static const char * const usb1_groups[] = {
-	"usb1",
-};
-
-static const char * const usb2_groups[] = {
-	"usb2",
-};
-
-static const char * const usb30_groups[] = {
-	"usb30",
-};
-
-static const char * const usb31_groups[] = {
-	"usb31",
-};
-
-static const struct sh_pfc_function pinmux_functions[] = {
-	SH_PFC_FUNCTION(audio_clk),
-	SH_PFC_FUNCTION(avb),
-	SH_PFC_FUNCTION(can0),
-	SH_PFC_FUNCTION(can1),
-	SH_PFC_FUNCTION(can_clk),
-	SH_PFC_FUNCTION(canfd0),
-	SH_PFC_FUNCTION(canfd1),
-	SH_PFC_FUNCTION(drif0),
-	SH_PFC_FUNCTION(drif1),
-	SH_PFC_FUNCTION(drif2),
-	SH_PFC_FUNCTION(drif3),
-	SH_PFC_FUNCTION(du),
-	SH_PFC_FUNCTION(hscif0),
-	SH_PFC_FUNCTION(hscif1),
-	SH_PFC_FUNCTION(hscif2),
-	SH_PFC_FUNCTION(hscif3),
-	SH_PFC_FUNCTION(hscif4),
-	SH_PFC_FUNCTION(i2c0),
-	SH_PFC_FUNCTION(i2c1),
-	SH_PFC_FUNCTION(i2c2),
-	SH_PFC_FUNCTION(i2c3),
-	SH_PFC_FUNCTION(i2c5),
-	SH_PFC_FUNCTION(i2c6),
-	SH_PFC_FUNCTION(intc_ex),
-	SH_PFC_FUNCTION(msiof0),
-	SH_PFC_FUNCTION(msiof1),
-	SH_PFC_FUNCTION(msiof2),
-	SH_PFC_FUNCTION(msiof3),
-	SH_PFC_FUNCTION(pwm0),
-	SH_PFC_FUNCTION(pwm1),
-	SH_PFC_FUNCTION(pwm2),
-	SH_PFC_FUNCTION(pwm3),
-	SH_PFC_FUNCTION(pwm4),
-	SH_PFC_FUNCTION(pwm5),
-	SH_PFC_FUNCTION(pwm6),
-	SH_PFC_FUNCTION(qspi0),
-	SH_PFC_FUNCTION(qspi1),
-	SH_PFC_FUNCTION(sata0),
-	SH_PFC_FUNCTION(scif0),
-	SH_PFC_FUNCTION(scif1),
-	SH_PFC_FUNCTION(scif2),
-	SH_PFC_FUNCTION(scif3),
-	SH_PFC_FUNCTION(scif4),
-	SH_PFC_FUNCTION(scif5),
-	SH_PFC_FUNCTION(scif_clk),
-	SH_PFC_FUNCTION(sdhi0),
-	SH_PFC_FUNCTION(sdhi1),
-	SH_PFC_FUNCTION(sdhi2),
-	SH_PFC_FUNCTION(sdhi3),
-	SH_PFC_FUNCTION(ssi),
-	SH_PFC_FUNCTION(tmu),
-	SH_PFC_FUNCTION(tpu),
-	SH_PFC_FUNCTION(usb0),
-	SH_PFC_FUNCTION(usb1),
-	SH_PFC_FUNCTION(usb2),
-	SH_PFC_FUNCTION(usb30),
-	SH_PFC_FUNCTION(usb31),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-#define F_(x, y)	FN_##y
-#define FM(x)		FN_##x
-	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_0_15_FN,	GPSR0_15,
-		GP_0_14_FN,	GPSR0_14,
-		GP_0_13_FN,	GPSR0_13,
-		GP_0_12_FN,	GPSR0_12,
-		GP_0_11_FN,	GPSR0_11,
-		GP_0_10_FN,	GPSR0_10,
-		GP_0_9_FN,	GPSR0_9,
-		GP_0_8_FN,	GPSR0_8,
-		GP_0_7_FN,	GPSR0_7,
-		GP_0_6_FN,	GPSR0_6,
-		GP_0_5_FN,	GPSR0_5,
-		GP_0_4_FN,	GPSR0_4,
-		GP_0_3_FN,	GPSR0_3,
-		GP_0_2_FN,	GPSR0_2,
-		GP_0_1_FN,	GPSR0_1,
-		GP_0_0_FN,	GPSR0_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_1_27_FN,	GPSR1_27,
-		GP_1_26_FN,	GPSR1_26,
-		GP_1_25_FN,	GPSR1_25,
-		GP_1_24_FN,	GPSR1_24,
-		GP_1_23_FN,	GPSR1_23,
-		GP_1_22_FN,	GPSR1_22,
-		GP_1_21_FN,	GPSR1_21,
-		GP_1_20_FN,	GPSR1_20,
-		GP_1_19_FN,	GPSR1_19,
-		GP_1_18_FN,	GPSR1_18,
-		GP_1_17_FN,	GPSR1_17,
-		GP_1_16_FN,	GPSR1_16,
-		GP_1_15_FN,	GPSR1_15,
-		GP_1_14_FN,	GPSR1_14,
-		GP_1_13_FN,	GPSR1_13,
-		GP_1_12_FN,	GPSR1_12,
-		GP_1_11_FN,	GPSR1_11,
-		GP_1_10_FN,	GPSR1_10,
-		GP_1_9_FN,	GPSR1_9,
-		GP_1_8_FN,	GPSR1_8,
-		GP_1_7_FN,	GPSR1_7,
-		GP_1_6_FN,	GPSR1_6,
-		GP_1_5_FN,	GPSR1_5,
-		GP_1_4_FN,	GPSR1_4,
-		GP_1_3_FN,	GPSR1_3,
-		GP_1_2_FN,	GPSR1_2,
-		GP_1_1_FN,	GPSR1_1,
-		GP_1_0_FN,	GPSR1_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_2_14_FN,	GPSR2_14,
-		GP_2_13_FN,	GPSR2_13,
-		GP_2_12_FN,	GPSR2_12,
-		GP_2_11_FN,	GPSR2_11,
-		GP_2_10_FN,	GPSR2_10,
-		GP_2_9_FN,	GPSR2_9,
-		GP_2_8_FN,	GPSR2_8,
-		GP_2_7_FN,	GPSR2_7,
-		GP_2_6_FN,	GPSR2_6,
-		GP_2_5_FN,	GPSR2_5,
-		GP_2_4_FN,	GPSR2_4,
-		GP_2_3_FN,	GPSR2_3,
-		GP_2_2_FN,	GPSR2_2,
-		GP_2_1_FN,	GPSR2_1,
-		GP_2_0_FN,	GPSR2_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_3_15_FN,	GPSR3_15,
-		GP_3_14_FN,	GPSR3_14,
-		GP_3_13_FN,	GPSR3_13,
-		GP_3_12_FN,	GPSR3_12,
-		GP_3_11_FN,	GPSR3_11,
-		GP_3_10_FN,	GPSR3_10,
-		GP_3_9_FN,	GPSR3_9,
-		GP_3_8_FN,	GPSR3_8,
-		GP_3_7_FN,	GPSR3_7,
-		GP_3_6_FN,	GPSR3_6,
-		GP_3_5_FN,	GPSR3_5,
-		GP_3_4_FN,	GPSR3_4,
-		GP_3_3_FN,	GPSR3_3,
-		GP_3_2_FN,	GPSR3_2,
-		GP_3_1_FN,	GPSR3_1,
-		GP_3_0_FN,	GPSR3_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_4_17_FN,	GPSR4_17,
-		GP_4_16_FN,	GPSR4_16,
-		GP_4_15_FN,	GPSR4_15,
-		GP_4_14_FN,	GPSR4_14,
-		GP_4_13_FN,	GPSR4_13,
-		GP_4_12_FN,	GPSR4_12,
-		GP_4_11_FN,	GPSR4_11,
-		GP_4_10_FN,	GPSR4_10,
-		GP_4_9_FN,	GPSR4_9,
-		GP_4_8_FN,	GPSR4_8,
-		GP_4_7_FN,	GPSR4_7,
-		GP_4_6_FN,	GPSR4_6,
-		GP_4_5_FN,	GPSR4_5,
-		GP_4_4_FN,	GPSR4_4,
-		GP_4_3_FN,	GPSR4_3,
-		GP_4_2_FN,	GPSR4_2,
-		GP_4_1_FN,	GPSR4_1,
-		GP_4_0_FN,	GPSR4_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_5_25_FN,	GPSR5_25,
-		GP_5_24_FN,	GPSR5_24,
-		GP_5_23_FN,	GPSR5_23,
-		GP_5_22_FN,	GPSR5_22,
-		GP_5_21_FN,	GPSR5_21,
-		GP_5_20_FN,	GPSR5_20,
-		GP_5_19_FN,	GPSR5_19,
-		GP_5_18_FN,	GPSR5_18,
-		GP_5_17_FN,	GPSR5_17,
-		GP_5_16_FN,	GPSR5_16,
-		GP_5_15_FN,	GPSR5_15,
-		GP_5_14_FN,	GPSR5_14,
-		GP_5_13_FN,	GPSR5_13,
-		GP_5_12_FN,	GPSR5_12,
-		GP_5_11_FN,	GPSR5_11,
-		GP_5_10_FN,	GPSR5_10,
-		GP_5_9_FN,	GPSR5_9,
-		GP_5_8_FN,	GPSR5_8,
-		GP_5_7_FN,	GPSR5_7,
-		GP_5_6_FN,	GPSR5_6,
-		GP_5_5_FN,	GPSR5_5,
-		GP_5_4_FN,	GPSR5_4,
-		GP_5_3_FN,	GPSR5_3,
-		GP_5_2_FN,	GPSR5_2,
-		GP_5_1_FN,	GPSR5_1,
-		GP_5_0_FN,	GPSR5_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
-		GP_6_31_FN,	GPSR6_31,
-		GP_6_30_FN,	GPSR6_30,
-		GP_6_29_FN,	GPSR6_29,
-		GP_6_28_FN,	GPSR6_28,
-		GP_6_27_FN,	GPSR6_27,
-		GP_6_26_FN,	GPSR6_26,
-		GP_6_25_FN,	GPSR6_25,
-		GP_6_24_FN,	GPSR6_24,
-		GP_6_23_FN,	GPSR6_23,
-		GP_6_22_FN,	GPSR6_22,
-		GP_6_21_FN,	GPSR6_21,
-		GP_6_20_FN,	GPSR6_20,
-		GP_6_19_FN,	GPSR6_19,
-		GP_6_18_FN,	GPSR6_18,
-		GP_6_17_FN,	GPSR6_17,
-		GP_6_16_FN,	GPSR6_16,
-		GP_6_15_FN,	GPSR6_15,
-		GP_6_14_FN,	GPSR6_14,
-		GP_6_13_FN,	GPSR6_13,
-		GP_6_12_FN,	GPSR6_12,
-		GP_6_11_FN,	GPSR6_11,
-		GP_6_10_FN,	GPSR6_10,
-		GP_6_9_FN,	GPSR6_9,
-		GP_6_8_FN,	GPSR6_8,
-		GP_6_7_FN,	GPSR6_7,
-		GP_6_6_FN,	GPSR6_6,
-		GP_6_5_FN,	GPSR6_5,
-		GP_6_4_FN,	GPSR6_4,
-		GP_6_3_FN,	GPSR6_3,
-		GP_6_2_FN,	GPSR6_2,
-		GP_6_1_FN,	GPSR6_1,
-		GP_6_0_FN,	GPSR6_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_7_3_FN, GPSR7_3,
-		GP_7_2_FN, GPSR7_2,
-		GP_7_1_FN, GPSR7_1,
-		GP_7_0_FN, GPSR7_0, ))
-	},
-#undef F_
-#undef FM
-
-#define F_(x, y)	x,
-#define FM(x)		FN_##x,
-	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
-		IP0_31_28
-		IP0_27_24
-		IP0_23_20
-		IP0_19_16
-		IP0_15_12
-		IP0_11_8
-		IP0_7_4
-		IP0_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
-		IP1_31_28
-		IP1_27_24
-		IP1_23_20
-		IP1_19_16
-		IP1_15_12
-		IP1_11_8
-		IP1_7_4
-		IP1_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
-		IP2_31_28
-		IP2_27_24
-		IP2_23_20
-		IP2_19_16
-		IP2_15_12
-		IP2_11_8
-		IP2_7_4
-		IP2_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
-		IP3_31_28
-		IP3_27_24
-		IP3_23_20
-		IP3_19_16
-		IP3_15_12
-		IP3_11_8
-		IP3_7_4
-		IP3_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
-		IP4_31_28
-		IP4_27_24
-		IP4_23_20
-		IP4_19_16
-		IP4_15_12
-		IP4_11_8
-		IP4_7_4
-		IP4_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
-		IP5_31_28
-		IP5_27_24
-		IP5_23_20
-		IP5_19_16
-		IP5_15_12
-		IP5_11_8
-		IP5_7_4
-		IP5_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
-		IP6_31_28
-		IP6_27_24
-		IP6_23_20
-		IP6_19_16
-		IP6_15_12
-		IP6_11_8
-		IP6_7_4
-		IP6_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
-		IP7_31_28
-		IP7_27_24
-		IP7_23_20
-		IP7_19_16
-		IP7_15_12
-		IP7_11_8
-		IP7_7_4
-		IP7_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
-		IP8_31_28
-		IP8_27_24
-		IP8_23_20
-		IP8_19_16
-		IP8_15_12
-		IP8_11_8
-		IP8_7_4
-		IP8_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
-		IP9_31_28
-		IP9_27_24
-		IP9_23_20
-		IP9_19_16
-		IP9_15_12
-		IP9_11_8
-		IP9_7_4
-		IP9_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
-		IP10_31_28
-		IP10_27_24
-		IP10_23_20
-		IP10_19_16
-		IP10_15_12
-		IP10_11_8
-		IP10_7_4
-		IP10_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
-		IP11_31_28
-		IP11_27_24
-		IP11_23_20
-		IP11_19_16
-		IP11_15_12
-		IP11_11_8
-		IP11_7_4
-		IP11_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
-		IP12_31_28
-		IP12_27_24
-		IP12_23_20
-		IP12_19_16
-		IP12_15_12
-		IP12_11_8
-		IP12_7_4
-		IP12_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
-		IP13_31_28
-		IP13_27_24
-		IP13_23_20
-		IP13_19_16
-		IP13_15_12
-		IP13_11_8
-		IP13_7_4
-		IP13_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
-		IP14_31_28
-		IP14_27_24
-		IP14_23_20
-		IP14_19_16
-		IP14_15_12
-		IP14_11_8
-		IP14_7_4
-		IP14_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
-		IP15_31_28
-		IP15_27_24
-		IP15_23_20
-		IP15_19_16
-		IP15_15_12
-		IP15_11_8
-		IP15_7_4
-		IP15_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
-		IP16_31_28
-		IP16_27_24
-		IP16_23_20
-		IP16_19_16
-		IP16_15_12
-		IP16_11_8
-		IP16_7_4
-		IP16_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
-		/* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP17_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		IP17_7_4
-		IP17_3_0 ))
-	},
-#undef F_
-#undef FM
-
-#define F_(x, y)	x,
-#define FM(x)		FN_##x,
-	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
-			     GROUP(1, 2, 2, 3, 1, 1, 2, 1, 1, 1, 2, 1,
-				   1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1),
-			     GROUP(
-		0, 0, /* RESERVED 31 */
-		MOD_SEL0_30_29
-		MOD_SEL0_28_27
-		MOD_SEL0_26_25_24
-		MOD_SEL0_23
-		MOD_SEL0_22
-		MOD_SEL0_21_20
-		MOD_SEL0_19
-		MOD_SEL0_18
-		MOD_SEL0_17
-		MOD_SEL0_16_15
-		MOD_SEL0_14
-		MOD_SEL0_13
-		MOD_SEL0_12
-		MOD_SEL0_11
-		MOD_SEL0_10
-		MOD_SEL0_9
-		MOD_SEL0_8
-		MOD_SEL0_7_6
-		MOD_SEL0_5_4
-		MOD_SEL0_3
-		MOD_SEL0_2_1
-		0, 0, /* RESERVED 0 */ ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
-			     GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
-				   1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
-			     GROUP(
-		MOD_SEL1_31_30
-		MOD_SEL1_29_28_27
-		MOD_SEL1_26
-		MOD_SEL1_25_24
-		MOD_SEL1_23_22_21
-		MOD_SEL1_20
-		MOD_SEL1_19
-		MOD_SEL1_18_17
-		MOD_SEL1_16
-		MOD_SEL1_15_14
-		MOD_SEL1_13
-		MOD_SEL1_12
-		MOD_SEL1_11
-		MOD_SEL1_10
-		MOD_SEL1_9
-		0, 0, 0, 0, /* RESERVED 8, 7 */
-		MOD_SEL1_6
-		MOD_SEL1_5
-		MOD_SEL1_4
-		MOD_SEL1_3
-		MOD_SEL1_2
-		MOD_SEL1_1
-		MOD_SEL1_0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
-			     GROUP(1, 1, 1, 1, 4, 4, 4, 4, 4, 4, 1, 2, 1),
-			     GROUP(
-		MOD_SEL2_31
-		MOD_SEL2_30
-		MOD_SEL2_29
-		/* RESERVED 28 */
-		0, 0,
-		/* RESERVED 27, 26, 25, 24 */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 23, 22, 21, 20 */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 19, 18, 17, 16 */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 15, 14, 13, 12 */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 11, 10, 9, 8 */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 7, 6, 5, 4 */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 3 */
-		0, 0,
-		/* RESERVED 2, 1 */
-		0, 0, 0, 0,
-		MOD_SEL2_0 ))
-	},
-	{ },
-};
-
-static const struct pinmux_drive_reg pinmux_drive_regs[] = {
-	{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
-		{ PIN_QSPI0_SPCLK,    28, 2 },	/* QSPI0_SPCLK */
-		{ PIN_QSPI0_MOSI_IO0, 24, 2 },	/* QSPI0_MOSI_IO0 */
-		{ PIN_QSPI0_MISO_IO1, 20, 2 },	/* QSPI0_MISO_IO1 */
-		{ PIN_QSPI0_IO2,      16, 2 },	/* QSPI0_IO2 */
-		{ PIN_QSPI0_IO3,      12, 2 },	/* QSPI0_IO3 */
-		{ PIN_QSPI0_SSL,       8, 2 },	/* QSPI0_SSL */
-		{ PIN_QSPI1_SPCLK,     4, 2 },	/* QSPI1_SPCLK */
-		{ PIN_QSPI1_MOSI_IO0,  0, 2 },	/* QSPI1_MOSI_IO0 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
-		{ PIN_QSPI1_MISO_IO1, 28, 2 },	/* QSPI1_MISO_IO1 */
-		{ PIN_QSPI1_IO2,      24, 2 },	/* QSPI1_IO2 */
-		{ PIN_QSPI1_IO3,      20, 2 },	/* QSPI1_IO3 */
-		{ PIN_QSPI1_SSL,      16, 2 },	/* QSPI1_SSL */
-		{ PIN_RPC_INT_N,      12, 2 },	/* RPC_INT# */
-		{ PIN_RPC_WP_N,        8, 2 },	/* RPC_WP# */
-		{ PIN_RPC_RESET_N,     4, 2 },	/* RPC_RESET# */
-		{ PIN_AVB_RX_CTL,      0, 3 },	/* AVB_RX_CTL */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
-		{ PIN_AVB_RXC,        28, 3 },	/* AVB_RXC */
-		{ PIN_AVB_RD0,        24, 3 },	/* AVB_RD0 */
-		{ PIN_AVB_RD1,        20, 3 },	/* AVB_RD1 */
-		{ PIN_AVB_RD2,        16, 3 },	/* AVB_RD2 */
-		{ PIN_AVB_RD3,        12, 3 },	/* AVB_RD3 */
-		{ PIN_AVB_TX_CTL,      8, 3 },	/* AVB_TX_CTL */
-		{ PIN_AVB_TXC,         4, 3 },	/* AVB_TXC */
-		{ PIN_AVB_TD0,         0, 3 },	/* AVB_TD0 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
-		{ PIN_AVB_TD1,        28, 3 },	/* AVB_TD1 */
-		{ PIN_AVB_TD2,        24, 3 },	/* AVB_TD2 */
-		{ PIN_AVB_TD3,        20, 3 },	/* AVB_TD3 */
-		{ PIN_AVB_TXCREFCLK,  16, 3 },	/* AVB_TXCREFCLK */
-		{ PIN_AVB_MDIO,       12, 3 },	/* AVB_MDIO */
-		{ RCAR_GP_PIN(2,  9),  8, 3 },	/* AVB_MDC */
-		{ RCAR_GP_PIN(2, 10),  4, 3 },	/* AVB_MAGIC */
-		{ RCAR_GP_PIN(2, 11),  0, 3 },	/* AVB_PHY_INT */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
-		{ RCAR_GP_PIN(2, 12), 28, 3 },	/* AVB_LINK */
-		{ RCAR_GP_PIN(2, 13), 24, 3 },	/* AVB_AVTP_MATCH */
-		{ RCAR_GP_PIN(2, 14), 20, 3 },	/* AVB_AVTP_CAPTURE */
-		{ RCAR_GP_PIN(2,  0), 16, 3 },	/* IRQ0 */
-		{ RCAR_GP_PIN(2,  1), 12, 3 },	/* IRQ1 */
-		{ RCAR_GP_PIN(2,  2),  8, 3 },	/* IRQ2 */
-		{ RCAR_GP_PIN(2,  3),  4, 3 },	/* IRQ3 */
-		{ RCAR_GP_PIN(2,  4),  0, 3 },	/* IRQ4 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
-		{ RCAR_GP_PIN(2,  5), 28, 3 },	/* IRQ5 */
-		{ RCAR_GP_PIN(2,  6), 24, 3 },	/* PWM0 */
-		{ RCAR_GP_PIN(2,  7), 20, 3 },	/* PWM1 */
-		{ RCAR_GP_PIN(2,  8), 16, 3 },	/* PWM2 */
-		{ RCAR_GP_PIN(1,  0), 12, 3 },	/* A0 */
-		{ RCAR_GP_PIN(1,  1),  8, 3 },	/* A1 */
-		{ RCAR_GP_PIN(1,  2),  4, 3 },	/* A2 */
-		{ RCAR_GP_PIN(1,  3),  0, 3 },	/* A3 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
-		{ RCAR_GP_PIN(1,  4), 28, 3 },	/* A4 */
-		{ RCAR_GP_PIN(1,  5), 24, 3 },	/* A5 */
-		{ RCAR_GP_PIN(1,  6), 20, 3 },	/* A6 */
-		{ RCAR_GP_PIN(1,  7), 16, 3 },	/* A7 */
-		{ RCAR_GP_PIN(1,  8), 12, 3 },	/* A8 */
-		{ RCAR_GP_PIN(1,  9),  8, 3 },	/* A9 */
-		{ RCAR_GP_PIN(1, 10),  4, 3 },	/* A10 */
-		{ RCAR_GP_PIN(1, 11),  0, 3 },	/* A11 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
-		{ RCAR_GP_PIN(1, 12), 28, 3 },	/* A12 */
-		{ RCAR_GP_PIN(1, 13), 24, 3 },	/* A13 */
-		{ RCAR_GP_PIN(1, 14), 20, 3 },	/* A14 */
-		{ RCAR_GP_PIN(1, 15), 16, 3 },	/* A15 */
-		{ RCAR_GP_PIN(1, 16), 12, 3 },	/* A16 */
-		{ RCAR_GP_PIN(1, 17),  8, 3 },	/* A17 */
-		{ RCAR_GP_PIN(1, 18),  4, 3 },	/* A18 */
-		{ RCAR_GP_PIN(1, 19),  0, 3 },	/* A19 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
-		{ PIN_CLKOUT,         28, 3 },	/* CLKOUT */
-		{ RCAR_GP_PIN(1, 20), 24, 3 },	/* CS0 */
-		{ RCAR_GP_PIN(1, 21), 20, 3 },	/* CS1_A26 */
-		{ RCAR_GP_PIN(1, 22), 16, 3 },	/* BS */
-		{ RCAR_GP_PIN(1, 23), 12, 3 },	/* RD */
-		{ RCAR_GP_PIN(1, 24),  8, 3 },	/* RD_WR */
-		{ RCAR_GP_PIN(1, 25),  4, 3 },	/* WE0 */
-		{ RCAR_GP_PIN(1, 26),  0, 3 },	/* WE1 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
-		{ RCAR_GP_PIN(1, 27), 28, 3 },	/* EX_WAIT0 */
-		{ PIN_PRESETOUT_N,    24, 3 },	/* PRESETOUT# */
-		{ RCAR_GP_PIN(0,  0), 20, 3 },	/* D0 */
-		{ RCAR_GP_PIN(0,  1), 16, 3 },	/* D1 */
-		{ RCAR_GP_PIN(0,  2), 12, 3 },	/* D2 */
-		{ RCAR_GP_PIN(0,  3),  8, 3 },	/* D3 */
-		{ RCAR_GP_PIN(0,  4),  4, 3 },	/* D4 */
-		{ RCAR_GP_PIN(0,  5),  0, 3 },	/* D5 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
-		{ RCAR_GP_PIN(0,  6), 28, 3 },	/* D6 */
-		{ RCAR_GP_PIN(0,  7), 24, 3 },	/* D7 */
-		{ RCAR_GP_PIN(0,  8), 20, 3 },	/* D8 */
-		{ RCAR_GP_PIN(0,  9), 16, 3 },	/* D9 */
-		{ RCAR_GP_PIN(0, 10), 12, 3 },	/* D10 */
-		{ RCAR_GP_PIN(0, 11),  8, 3 },	/* D11 */
-		{ RCAR_GP_PIN(0, 12),  4, 3 },	/* D12 */
-		{ RCAR_GP_PIN(0, 13),  0, 3 },	/* D13 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
-		{ RCAR_GP_PIN(0, 14), 28, 3 },	/* D14 */
-		{ RCAR_GP_PIN(0, 15), 24, 3 },	/* D15 */
-		{ RCAR_GP_PIN(7,  0), 20, 3 },	/* AVS1 */
-		{ RCAR_GP_PIN(7,  1), 16, 3 },	/* AVS2 */
-		{ RCAR_GP_PIN(7,  2), 12, 3 },	/* GP7_02 */
-		{ RCAR_GP_PIN(7,  3),  8, 3 },	/* GP7_03 */
-		{ PIN_DU_DOTCLKIN0,    4, 2 },	/* DU_DOTCLKIN0 */
-		{ PIN_DU_DOTCLKIN1,    0, 2 },	/* DU_DOTCLKIN1 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
-		{ PIN_DU_DOTCLKIN2,   28, 2 },	/* DU_DOTCLKIN2 */
-		{ PIN_DU_DOTCLKIN3,   24, 2 },	/* DU_DOTCLKIN3 */
-		{ PIN_FSCLKST_N,      20, 2 },	/* FSCLKST# */
-		{ PIN_TMS,             4, 2 },	/* TMS */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
-		{ PIN_TDO,            28, 2 },	/* TDO */
-		{ PIN_ASEBRK,         24, 2 },	/* ASEBRK */
-		{ RCAR_GP_PIN(3,  0), 20, 3 },	/* SD0_CLK */
-		{ RCAR_GP_PIN(3,  1), 16, 3 },	/* SD0_CMD */
-		{ RCAR_GP_PIN(3,  2), 12, 3 },	/* SD0_DAT0 */
-		{ RCAR_GP_PIN(3,  3),  8, 3 },	/* SD0_DAT1 */
-		{ RCAR_GP_PIN(3,  4),  4, 3 },	/* SD0_DAT2 */
-		{ RCAR_GP_PIN(3,  5),  0, 3 },	/* SD0_DAT3 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
-		{ RCAR_GP_PIN(3,  6), 28, 3 },	/* SD1_CLK */
-		{ RCAR_GP_PIN(3,  7), 24, 3 },	/* SD1_CMD */
-		{ RCAR_GP_PIN(3,  8), 20, 3 },	/* SD1_DAT0 */
-		{ RCAR_GP_PIN(3,  9), 16, 3 },	/* SD1_DAT1 */
-		{ RCAR_GP_PIN(3, 10), 12, 3 },	/* SD1_DAT2 */
-		{ RCAR_GP_PIN(3, 11),  8, 3 },	/* SD1_DAT3 */
-		{ RCAR_GP_PIN(4,  0),  4, 3 },	/* SD2_CLK */
-		{ RCAR_GP_PIN(4,  1),  0, 3 },	/* SD2_CMD */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
-		{ RCAR_GP_PIN(4,  2), 28, 3 },	/* SD2_DAT0 */
-		{ RCAR_GP_PIN(4,  3), 24, 3 },	/* SD2_DAT1 */
-		{ RCAR_GP_PIN(4,  4), 20, 3 },	/* SD2_DAT2 */
-		{ RCAR_GP_PIN(4,  5), 16, 3 },	/* SD2_DAT3 */
-		{ RCAR_GP_PIN(4,  6), 12, 3 },	/* SD2_DS */
-		{ RCAR_GP_PIN(4,  7),  8, 3 },	/* SD3_CLK */
-		{ RCAR_GP_PIN(4,  8),  4, 3 },	/* SD3_CMD */
-		{ RCAR_GP_PIN(4,  9),  0, 3 },	/* SD3_DAT0 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
-		{ RCAR_GP_PIN(4, 10), 28, 3 },	/* SD3_DAT1 */
-		{ RCAR_GP_PIN(4, 11), 24, 3 },	/* SD3_DAT2 */
-		{ RCAR_GP_PIN(4, 12), 20, 3 },	/* SD3_DAT3 */
-		{ RCAR_GP_PIN(4, 13), 16, 3 },	/* SD3_DAT4 */
-		{ RCAR_GP_PIN(4, 14), 12, 3 },	/* SD3_DAT5 */
-		{ RCAR_GP_PIN(4, 15),  8, 3 },	/* SD3_DAT6 */
-		{ RCAR_GP_PIN(4, 16),  4, 3 },	/* SD3_DAT7 */
-		{ RCAR_GP_PIN(4, 17),  0, 3 },	/* SD3_DS */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
-		{ RCAR_GP_PIN(3, 12), 28, 3 },	/* SD0_CD */
-		{ RCAR_GP_PIN(3, 13), 24, 3 },	/* SD0_WP */
-		{ RCAR_GP_PIN(3, 14), 20, 3 },	/* SD1_CD */
-		{ RCAR_GP_PIN(3, 15), 16, 3 },	/* SD1_WP */
-		{ RCAR_GP_PIN(5,  0), 12, 3 },	/* SCK0 */
-		{ RCAR_GP_PIN(5,  1),  8, 3 },	/* RX0 */
-		{ RCAR_GP_PIN(5,  2),  4, 3 },	/* TX0 */
-		{ RCAR_GP_PIN(5,  3),  0, 3 },	/* CTS0 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
-		{ RCAR_GP_PIN(5,  4), 28, 3 },	/* RTS0 */
-		{ RCAR_GP_PIN(5,  5), 24, 3 },	/* RX1 */
-		{ RCAR_GP_PIN(5,  6), 20, 3 },	/* TX1 */
-		{ RCAR_GP_PIN(5,  7), 16, 3 },	/* CTS1 */
-		{ RCAR_GP_PIN(5,  8), 12, 3 },	/* RTS1 */
-		{ RCAR_GP_PIN(5,  9),  8, 3 },	/* SCK2 */
-		{ RCAR_GP_PIN(5, 10),  4, 3 },	/* TX2 */
-		{ RCAR_GP_PIN(5, 11),  0, 3 },	/* RX2 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
-		{ RCAR_GP_PIN(5, 12), 28, 3 },	/* HSCK0 */
-		{ RCAR_GP_PIN(5, 13), 24, 3 },	/* HRX0 */
-		{ RCAR_GP_PIN(5, 14), 20, 3 },	/* HTX0 */
-		{ RCAR_GP_PIN(5, 15), 16, 3 },	/* HCTS0 */
-		{ RCAR_GP_PIN(5, 16), 12, 3 },	/* HRTS0 */
-		{ RCAR_GP_PIN(5, 17),  8, 3 },	/* MSIOF0_SCK */
-		{ RCAR_GP_PIN(5, 18),  4, 3 },	/* MSIOF0_SYNC */
-		{ RCAR_GP_PIN(5, 19),  0, 3 },	/* MSIOF0_SS1 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
-		{ RCAR_GP_PIN(5, 20), 28, 3 },	/* MSIOF0_TXD */
-		{ RCAR_GP_PIN(5, 21), 24, 3 },	/* MSIOF0_SS2 */
-		{ RCAR_GP_PIN(5, 22), 20, 3 },	/* MSIOF0_RXD */
-		{ RCAR_GP_PIN(5, 23), 16, 3 },	/* MLB_CLK */
-		{ RCAR_GP_PIN(5, 24), 12, 3 },	/* MLB_SIG */
-		{ RCAR_GP_PIN(5, 25),  8, 3 },	/* MLB_DAT */
-		{ PIN_MLB_REF,         4, 3 },	/* MLB_REF */
-		{ RCAR_GP_PIN(6,  0),  0, 3 },	/* SSI_SCK01239 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
-		{ RCAR_GP_PIN(6,  1), 28, 3 },	/* SSI_WS01239 */
-		{ RCAR_GP_PIN(6,  2), 24, 3 },	/* SSI_SDATA0 */
-		{ RCAR_GP_PIN(6,  3), 20, 3 },	/* SSI_SDATA1 */
-		{ RCAR_GP_PIN(6,  4), 16, 3 },	/* SSI_SDATA2 */
-		{ RCAR_GP_PIN(6,  5), 12, 3 },	/* SSI_SCK349 */
-		{ RCAR_GP_PIN(6,  6),  8, 3 },	/* SSI_WS349 */
-		{ RCAR_GP_PIN(6,  7),  4, 3 },	/* SSI_SDATA3 */
-		{ RCAR_GP_PIN(6,  8),  0, 3 },	/* SSI_SCK4 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
-		{ RCAR_GP_PIN(6,  9), 28, 3 },	/* SSI_WS4 */
-		{ RCAR_GP_PIN(6, 10), 24, 3 },	/* SSI_SDATA4 */
-		{ RCAR_GP_PIN(6, 11), 20, 3 },	/* SSI_SCK5 */
-		{ RCAR_GP_PIN(6, 12), 16, 3 },	/* SSI_WS5 */
-		{ RCAR_GP_PIN(6, 13), 12, 3 },	/* SSI_SDATA5 */
-		{ RCAR_GP_PIN(6, 14),  8, 3 },	/* SSI_SCK6 */
-		{ RCAR_GP_PIN(6, 15),  4, 3 },	/* SSI_WS6 */
-		{ RCAR_GP_PIN(6, 16),  0, 3 },	/* SSI_SDATA6 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
-		{ RCAR_GP_PIN(6, 17), 28, 3 },	/* SSI_SCK78 */
-		{ RCAR_GP_PIN(6, 18), 24, 3 },	/* SSI_WS78 */
-		{ RCAR_GP_PIN(6, 19), 20, 3 },	/* SSI_SDATA7 */
-		{ RCAR_GP_PIN(6, 20), 16, 3 },	/* SSI_SDATA8 */
-		{ RCAR_GP_PIN(6, 21), 12, 3 },	/* SSI_SDATA9 */
-		{ RCAR_GP_PIN(6, 22),  8, 3 },	/* AUDIO_CLKA */
-		{ RCAR_GP_PIN(6, 23),  4, 3 },	/* AUDIO_CLKB */
-		{ RCAR_GP_PIN(6, 24),  0, 3 },	/* USB0_PWEN */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
-		{ RCAR_GP_PIN(6, 25), 28, 3 },	/* USB0_OVC */
-		{ RCAR_GP_PIN(6, 26), 24, 3 },	/* USB1_PWEN */
-		{ RCAR_GP_PIN(6, 27), 20, 3 },	/* USB1_OVC */
-		{ RCAR_GP_PIN(6, 28), 16, 3 },	/* USB30_PWEN */
-		{ RCAR_GP_PIN(6, 29), 12, 3 },	/* USB30_OVC */
-		{ RCAR_GP_PIN(6, 30),  8, 3 },	/* USB31_PWEN */
-		{ RCAR_GP_PIN(6, 31),  4, 3 },	/* USB31_OVC */
-	} },
-	{ },
-};
-
-enum ioctrl_regs {
-	POCCTRL,
-	TDSELCTRL,
-};
-
-static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
-	[POCCTRL] = { 0xe6060380, },
-	[TDSELCTRL] = { 0xe60603c0, },
-	{ /* sentinel */ },
-};
-
-static int r8a77950_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
-				   u32 *pocctrl)
-{
-	int bit = -EINVAL;
-
-	*pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
-
-	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
-		bit = pin & 0x1f;
-
-	if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
-		bit = (pin & 0x1f) + 12;
-
-	return bit;
-}
-
-static const struct pinmux_bias_reg pinmux_bias_regs[] = {
-	{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
-		[ 0] = PIN_QSPI0_SPCLK,		/* QSPI0_SPCLK */
-		[ 1] = PIN_QSPI0_MOSI_IO0,	/* QSPI0_MOSI_IO0 */
-		[ 2] = PIN_QSPI0_MISO_IO1,	/* QSPI0_MISO_IO1 */
-		[ 3] = PIN_QSPI0_IO2,		/* QSPI0_IO2 */
-		[ 4] = PIN_QSPI0_IO3,		/* QSPI0_IO3 */
-		[ 5] = PIN_QSPI0_SSL,		/* QSPI0_SSL */
-		[ 6] = PIN_QSPI1_SPCLK,		/* QSPI1_SPCLK */
-		[ 7] = PIN_QSPI1_MOSI_IO0,	/* QSPI1_MOSI_IO0 */
-		[ 8] = PIN_QSPI1_MISO_IO1,	/* QSPI1_MISO_IO1 */
-		[ 9] = PIN_QSPI1_IO2,		/* QSPI1_IO2 */
-		[10] = PIN_QSPI1_IO3,		/* QSPI1_IO3 */
-		[11] = PIN_QSPI1_SSL,		/* QSPI1_SSL */
-		[12] = PIN_RPC_INT_N,		/* RPC_INT# */
-		[13] = PIN_RPC_WP_N,		/* RPC_WP# */
-		[14] = PIN_RPC_RESET_N,		/* RPC_RESET# */
-		[15] = PIN_AVB_RX_CTL,		/* AVB_RX_CTL */
-		[16] = PIN_AVB_RXC,		/* AVB_RXC */
-		[17] = PIN_AVB_RD0,		/* AVB_RD0 */
-		[18] = PIN_AVB_RD1,		/* AVB_RD1 */
-		[19] = PIN_AVB_RD2,		/* AVB_RD2 */
-		[20] = PIN_AVB_RD3,		/* AVB_RD3 */
-		[21] = PIN_AVB_TX_CTL,		/* AVB_TX_CTL */
-		[22] = PIN_AVB_TXC,		/* AVB_TXC */
-		[23] = PIN_AVB_TD0,		/* AVB_TD0 */
-		[24] = PIN_AVB_TD1,		/* AVB_TD1 */
-		[25] = PIN_AVB_TD2,		/* AVB_TD2 */
-		[26] = PIN_AVB_TD3,		/* AVB_TD3 */
-		[27] = PIN_AVB_TXCREFCLK,	/* AVB_TXCREFCLK */
-		[28] = PIN_AVB_MDIO,		/* AVB_MDIO */
-		[29] = RCAR_GP_PIN(2,  9),	/* AVB_MDC */
-		[30] = RCAR_GP_PIN(2, 10),	/* AVB_MAGIC */
-		[31] = RCAR_GP_PIN(2, 11),	/* AVB_PHY_INT */
-	} },
-	{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
-		[ 0] = RCAR_GP_PIN(2, 12),	/* AVB_LINK */
-		[ 1] = RCAR_GP_PIN(2, 13),	/* AVB_AVTP_MATCH_A */
-		[ 2] = RCAR_GP_PIN(2, 14),	/* AVB_AVTP_CAPTURE_A */
-		[ 3] = RCAR_GP_PIN(2,  0),	/* IRQ0 */
-		[ 4] = RCAR_GP_PIN(2,  1),	/* IRQ1 */
-		[ 5] = RCAR_GP_PIN(2,  2),	/* IRQ2 */
-		[ 6] = RCAR_GP_PIN(2,  3),	/* IRQ3 */
-		[ 7] = RCAR_GP_PIN(2,  4),	/* IRQ4 */
-		[ 8] = RCAR_GP_PIN(2,  5),	/* IRQ5 */
-		[ 9] = RCAR_GP_PIN(2,  6),	/* PWM0 */
-		[10] = RCAR_GP_PIN(2,  7),	/* PWM1_A */
-		[11] = RCAR_GP_PIN(2,  8),	/* PWM2_A */
-		[12] = RCAR_GP_PIN(1,  0),	/* A0 */
-		[13] = RCAR_GP_PIN(1,  1),	/* A1 */
-		[14] = RCAR_GP_PIN(1,  2),	/* A2 */
-		[15] = RCAR_GP_PIN(1,  3),	/* A3 */
-		[16] = RCAR_GP_PIN(1,  4),	/* A4 */
-		[17] = RCAR_GP_PIN(1,  5),	/* A5 */
-		[18] = RCAR_GP_PIN(1,  6),	/* A6 */
-		[19] = RCAR_GP_PIN(1,  7),	/* A7 */
-		[20] = RCAR_GP_PIN(1,  8),	/* A8 */
-		[21] = RCAR_GP_PIN(1,  9),	/* A9 */
-		[22] = RCAR_GP_PIN(1, 10),	/* A10 */
-		[23] = RCAR_GP_PIN(1, 11),	/* A11 */
-		[24] = RCAR_GP_PIN(1, 12),	/* A12 */
-		[25] = RCAR_GP_PIN(1, 13),	/* A13 */
-		[26] = RCAR_GP_PIN(1, 14),	/* A14 */
-		[27] = RCAR_GP_PIN(1, 15),	/* A15 */
-		[28] = RCAR_GP_PIN(1, 16),	/* A16 */
-		[29] = RCAR_GP_PIN(1, 17),	/* A17 */
-		[30] = RCAR_GP_PIN(1, 18),	/* A18 */
-		[31] = RCAR_GP_PIN(1, 19),	/* A19 */
-	} },
-	{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
-		[ 0] = PIN_CLKOUT,		/* CLKOUT */
-		[ 1] = RCAR_GP_PIN(1, 20),	/* CS0_N */
-		[ 2] = RCAR_GP_PIN(1, 21),	/* CS1_N_A26 */
-		[ 3] = RCAR_GP_PIN(1, 22),	/* BS_N */
-		[ 4] = RCAR_GP_PIN(1, 23),	/* RD_N */
-		[ 5] = RCAR_GP_PIN(1, 24),	/* RD_WR_N */
-		[ 6] = RCAR_GP_PIN(1, 25),	/* WE0_N */
-		[ 7] = RCAR_GP_PIN(1, 26),	/* WE1_N */
-		[ 8] = RCAR_GP_PIN(1, 27),	/* EX_WAIT0_A */
-		[ 9] = PIN_PRESETOUT_N,		/* PRESETOUT# */
-		[10] = RCAR_GP_PIN(0,  0),	/* D0 */
-		[11] = RCAR_GP_PIN(0,  1),	/* D1 */
-		[12] = RCAR_GP_PIN(0,  2),	/* D2 */
-		[13] = RCAR_GP_PIN(0,  3),	/* D3 */
-		[14] = RCAR_GP_PIN(0,  4),	/* D4 */
-		[15] = RCAR_GP_PIN(0,  5),	/* D5 */
-		[16] = RCAR_GP_PIN(0,  6),	/* D6 */
-		[17] = RCAR_GP_PIN(0,  7),	/* D7 */
-		[18] = RCAR_GP_PIN(0,  8),	/* D8 */
-		[19] = RCAR_GP_PIN(0,  9),	/* D9 */
-		[20] = RCAR_GP_PIN(0, 10),	/* D10 */
-		[21] = RCAR_GP_PIN(0, 11),	/* D11 */
-		[22] = RCAR_GP_PIN(0, 12),	/* D12 */
-		[23] = RCAR_GP_PIN(0, 13),	/* D13 */
-		[24] = RCAR_GP_PIN(0, 14),	/* D14 */
-		[25] = RCAR_GP_PIN(0, 15),	/* D15 */
-		[26] = RCAR_GP_PIN(7,  0),	/* AVS1 */
-		[27] = RCAR_GP_PIN(7,  1),	/* AVS2 */
-		[28] = RCAR_GP_PIN(7,  2),	/* GP7_02 */
-		[29] = RCAR_GP_PIN(7,  3),	/* GP7_03 */
-		[30] = PIN_DU_DOTCLKIN0,	/* DU_DOTCLKIN0 */
-		[31] = PIN_DU_DOTCLKIN1,	/* DU_DOTCLKIN1 */
-	} },
-	{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
-		[ 0] = PIN_DU_DOTCLKIN2,	/* DU_DOTCLKIN2 */
-		[ 1] = PIN_DU_DOTCLKIN3,	/* DU_DOTCLKIN3 */
-		[ 2] = PIN_FSCLKST_N,		/* FSCLKST# */
-		[ 3] = PIN_EXTALR,		/* EXTALR*/
-		[ 4] = PIN_TRST_N,		/* TRST# */
-		[ 5] = PIN_TCK,			/* TCK */
-		[ 6] = PIN_TMS,			/* TMS */
-		[ 7] = PIN_TDI,			/* TDI */
-		[ 8] = SH_PFC_PIN_NONE,
-		[ 9] = PIN_ASEBRK,		/* ASEBRK */
-		[10] = RCAR_GP_PIN(3,  0),	/* SD0_CLK */
-		[11] = RCAR_GP_PIN(3,  1),	/* SD0_CMD */
-		[12] = RCAR_GP_PIN(3,  2),	/* SD0_DAT0 */
-		[13] = RCAR_GP_PIN(3,  3),	/* SD0_DAT1 */
-		[14] = RCAR_GP_PIN(3,  4),	/* SD0_DAT2 */
-		[15] = RCAR_GP_PIN(3,  5),	/* SD0_DAT3 */
-		[16] = RCAR_GP_PIN(3,  6),	/* SD1_CLK */
-		[17] = RCAR_GP_PIN(3,  7),	/* SD1_CMD */
-		[18] = RCAR_GP_PIN(3,  8),	/* SD1_DAT0 */
-		[19] = RCAR_GP_PIN(3,  9),	/* SD1_DAT1 */
-		[20] = RCAR_GP_PIN(3, 10),	/* SD1_DAT2 */
-		[21] = RCAR_GP_PIN(3, 11),	/* SD1_DAT3 */
-		[22] = RCAR_GP_PIN(4,  0),	/* SD2_CLK */
-		[23] = RCAR_GP_PIN(4,  1),	/* SD2_CMD */
-		[24] = RCAR_GP_PIN(4,  2),	/* SD2_DAT0 */
-		[25] = RCAR_GP_PIN(4,  3),	/* SD2_DAT1 */
-		[26] = RCAR_GP_PIN(4,  4),	/* SD2_DAT2 */
-		[27] = RCAR_GP_PIN(4,  5),	/* SD2_DAT3 */
-		[28] = RCAR_GP_PIN(4,  6),	/* SD2_DS */
-		[29] = RCAR_GP_PIN(4,  7),	/* SD3_CLK */
-		[30] = RCAR_GP_PIN(4,  8),	/* SD3_CMD */
-		[31] = RCAR_GP_PIN(4,  9),	/* SD3_DAT0 */
-	} },
-	{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
-		[ 0] = RCAR_GP_PIN(4, 10),	/* SD3_DAT1 */
-		[ 1] = RCAR_GP_PIN(4, 11),	/* SD3_DAT2 */
-		[ 2] = RCAR_GP_PIN(4, 12),	/* SD3_DAT3 */
-		[ 3] = RCAR_GP_PIN(4, 13),	/* SD3_DAT4 */
-		[ 4] = RCAR_GP_PIN(4, 14),	/* SD3_DAT5 */
-		[ 5] = RCAR_GP_PIN(4, 15),	/* SD3_DAT6 */
-		[ 6] = RCAR_GP_PIN(4, 16),	/* SD3_DAT7 */
-		[ 7] = RCAR_GP_PIN(4, 17),	/* SD3_DS */
-		[ 8] = RCAR_GP_PIN(3, 12),	/* SD0_CD */
-		[ 9] = RCAR_GP_PIN(3, 13),	/* SD0_WP */
-		[10] = RCAR_GP_PIN(3, 14),	/* SD1_CD */
-		[11] = RCAR_GP_PIN(3, 15),	/* SD1_WP */
-		[12] = RCAR_GP_PIN(5,  0),	/* SCK0 */
-		[13] = RCAR_GP_PIN(5,  1),	/* RX0 */
-		[14] = RCAR_GP_PIN(5,  2),	/* TX0 */
-		[15] = RCAR_GP_PIN(5,  3),	/* CTS0_N */
-		[16] = RCAR_GP_PIN(5,  4),	/* RTS0_N */
-		[17] = RCAR_GP_PIN(5,  5),	/* RX1_A */
-		[18] = RCAR_GP_PIN(5,  6),	/* TX1_A */
-		[19] = RCAR_GP_PIN(5,  7),	/* CTS1_N */
-		[20] = RCAR_GP_PIN(5,  8),	/* RTS1_N */
-		[21] = RCAR_GP_PIN(5,  9),	/* SCK2 */
-		[22] = RCAR_GP_PIN(5, 10),	/* TX2_A */
-		[23] = RCAR_GP_PIN(5, 11),	/* RX2_A */
-		[24] = RCAR_GP_PIN(5, 12),	/* HSCK0 */
-		[25] = RCAR_GP_PIN(5, 13),	/* HRX0 */
-		[26] = RCAR_GP_PIN(5, 14),	/* HTX0 */
-		[27] = RCAR_GP_PIN(5, 15),	/* HCTS0_N */
-		[28] = RCAR_GP_PIN(5, 16),	/* HRTS0_N */
-		[29] = RCAR_GP_PIN(5, 17),	/* MSIOF0_SCK */
-		[30] = RCAR_GP_PIN(5, 18),	/* MSIOF0_SYNC */
-		[31] = RCAR_GP_PIN(5, 19),	/* MSIOF0_SS1 */
-	} },
-	{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
-		[ 0] = RCAR_GP_PIN(5, 20),	/* MSIOF0_TXD */
-		[ 1] = RCAR_GP_PIN(5, 21),	/* MSIOF0_SS2 */
-		[ 2] = RCAR_GP_PIN(5, 22),	/* MSIOF0_RXD */
-		[ 3] = RCAR_GP_PIN(5, 23),	/* MLB_CLK */
-		[ 4] = RCAR_GP_PIN(5, 24),	/* MLB_SIG */
-		[ 5] = RCAR_GP_PIN(5, 25),	/* MLB_DAT */
-		[ 6] = PIN_MLB_REF,		/* MLB_REF */
-		[ 7] = RCAR_GP_PIN(6,  0),	/* SSI_SCK01239 */
-		[ 8] = RCAR_GP_PIN(6,  1),	/* SSI_WS01239 */
-		[ 9] = RCAR_GP_PIN(6,  2),	/* SSI_SDATA0 */
-		[10] = RCAR_GP_PIN(6,  3),	/* SSI_SDATA1_A */
-		[11] = RCAR_GP_PIN(6,  4),	/* SSI_SDATA2_A */
-		[12] = RCAR_GP_PIN(6,  5),	/* SSI_SCK349 */
-		[13] = RCAR_GP_PIN(6,  6),	/* SSI_WS349 */
-		[14] = RCAR_GP_PIN(6,  7),	/* SSI_SDATA3 */
-		[15] = RCAR_GP_PIN(6,  8),	/* SSI_SCK4 */
-		[16] = RCAR_GP_PIN(6,  9),	/* SSI_WS4 */
-		[17] = RCAR_GP_PIN(6, 10),	/* SSI_SDATA4 */
-		[18] = RCAR_GP_PIN(6, 11),	/* SSI_SCK5 */
-		[19] = RCAR_GP_PIN(6, 12),	/* SSI_WS5 */
-		[20] = RCAR_GP_PIN(6, 13),	/* SSI_SDATA5 */
-		[21] = RCAR_GP_PIN(6, 14),	/* SSI_SCK6 */
-		[22] = RCAR_GP_PIN(6, 15),	/* SSI_WS6 */
-		[23] = RCAR_GP_PIN(6, 16),	/* SSI_SDATA6 */
-		[24] = RCAR_GP_PIN(6, 17),	/* SSI_SCK78 */
-		[25] = RCAR_GP_PIN(6, 18),	/* SSI_WS78 */
-		[26] = RCAR_GP_PIN(6, 19),	/* SSI_SDATA7 */
-		[27] = RCAR_GP_PIN(6, 20),	/* SSI_SDATA8 */
-		[28] = RCAR_GP_PIN(6, 21),	/* SSI_SDATA9_A */
-		[29] = RCAR_GP_PIN(6, 22),	/* AUDIO_CLKA_A */
-		[30] = RCAR_GP_PIN(6, 23),	/* AUDIO_CLKB_B */
-		[31] = RCAR_GP_PIN(6, 24),	/* USB0_PWEN */
-	} },
-	{ PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
-		[ 0] = RCAR_GP_PIN(6, 25),	/* USB0_OVC */
-		[ 1] = RCAR_GP_PIN(6, 26),	/* USB1_PWEN */
-		[ 2] = RCAR_GP_PIN(6, 27),	/* USB1_OVC */
-		[ 3] = RCAR_GP_PIN(6, 28),	/* USB30_PWEN */
-		[ 4] = RCAR_GP_PIN(6, 29),	/* USB30_OVC */
-		[ 5] = RCAR_GP_PIN(6, 30),	/* USB31_PWEN */
-		[ 6] = RCAR_GP_PIN(6, 31),	/* USB31_OVC */
-		[ 7] = SH_PFC_PIN_NONE,
-		[ 8] = SH_PFC_PIN_NONE,
-		[ 9] = SH_PFC_PIN_NONE,
-		[10] = SH_PFC_PIN_NONE,
-		[11] = SH_PFC_PIN_NONE,
-		[12] = SH_PFC_PIN_NONE,
-		[13] = SH_PFC_PIN_NONE,
-		[14] = SH_PFC_PIN_NONE,
-		[15] = SH_PFC_PIN_NONE,
-		[16] = SH_PFC_PIN_NONE,
-		[17] = SH_PFC_PIN_NONE,
-		[18] = SH_PFC_PIN_NONE,
-		[19] = SH_PFC_PIN_NONE,
-		[20] = SH_PFC_PIN_NONE,
-		[21] = SH_PFC_PIN_NONE,
-		[22] = SH_PFC_PIN_NONE,
-		[23] = SH_PFC_PIN_NONE,
-		[24] = SH_PFC_PIN_NONE,
-		[25] = SH_PFC_PIN_NONE,
-		[26] = SH_PFC_PIN_NONE,
-		[27] = SH_PFC_PIN_NONE,
-		[28] = SH_PFC_PIN_NONE,
-		[29] = SH_PFC_PIN_NONE,
-		[30] = SH_PFC_PIN_NONE,
-		[31] = SH_PFC_PIN_NONE,
-	} },
-	{ /* sentinel */ },
-};
-
-static unsigned int r8a77950_pinmux_get_bias(struct sh_pfc *pfc,
-					     unsigned int pin)
-{
-	const struct pinmux_bias_reg *reg;
-	unsigned int bit;
-
-	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
-	if (!reg)
-		return PIN_CONFIG_BIAS_DISABLE;
-
-	if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
-		return PIN_CONFIG_BIAS_DISABLE;
-	else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
-		return PIN_CONFIG_BIAS_PULL_UP;
-	else
-		return PIN_CONFIG_BIAS_PULL_DOWN;
-}
-
-static void r8a77950_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
-				     unsigned int bias)
-{
-	const struct pinmux_bias_reg *reg;
-	u32 enable, updown;
-	unsigned int bit;
-
-	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
-	if (!reg)
-		return;
-
-	enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
-	if (bias != PIN_CONFIG_BIAS_DISABLE)
-		enable |= BIT(bit);
-
-	updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
-	if (bias == PIN_CONFIG_BIAS_PULL_UP)
-		updown |= BIT(bit);
-
-	sh_pfc_write(pfc, reg->pud, updown);
-	sh_pfc_write(pfc, reg->puen, enable);
-}
-
-static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = {
-	.pin_to_pocctrl = r8a77950_pin_to_pocctrl,
-	.get_bias = r8a77950_pinmux_get_bias,
-	.set_bias = r8a77950_pinmux_set_bias,
-};
-
-const struct sh_pfc_soc_info r8a77950_pinmux_info = {
-	.name = "r8a77950_pfc",
-	.ops = &r8a77950_pinmux_ops,
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups,
-	.nr_groups = ARRAY_SIZE(pinmux_groups),
-	.functions = pinmux_functions,
-	.nr_functions = ARRAY_SIZE(pinmux_functions),
-
-	.cfg_regs = pinmux_config_regs,
-	.drive_regs = pinmux_drive_regs,
-	.bias_regs = pinmux_bias_regs,
-	.ioctrl_regs = pinmux_ioctrl_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77951.c b/drivers/pinctrl/sh-pfc/pfc-r8a77951.c
deleted file mode 100644
index 256fab4b03d3..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77951.c
+++ /dev/null
@@ -1,6244 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * R8A77951 processor support - PFC hardware block.
- *
- * Copyright (C) 2015-2019 Renesas Electronics Corporation
- */
-
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <linux/sys_soc.h>
-
-#include "core.h"
-#include "sh_pfc.h"
-
-#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
-
-#define CPU_ALL_GP(fn, sfx)						\
-	PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
-
-#define CPU_ALL_NOGP(fn)						\
-	PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS),			\
-	PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
-	PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
-	PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
-	PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
-	PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS),			\
-	PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
-
-/*
- * F_() : just information
- * FM() : macro for FN_xxx / xxx_MARK
- */
-
-/* GPSR0 */
-#define GPSR0_15	F_(D15,			IP7_11_8)
-#define GPSR0_14	F_(D14,			IP7_7_4)
-#define GPSR0_13	F_(D13,			IP7_3_0)
-#define GPSR0_12	F_(D12,			IP6_31_28)
-#define GPSR0_11	F_(D11,			IP6_27_24)
-#define GPSR0_10	F_(D10,			IP6_23_20)
-#define GPSR0_9		F_(D9,			IP6_19_16)
-#define GPSR0_8		F_(D8,			IP6_15_12)
-#define GPSR0_7		F_(D7,			IP6_11_8)
-#define GPSR0_6		F_(D6,			IP6_7_4)
-#define GPSR0_5		F_(D5,			IP6_3_0)
-#define GPSR0_4		F_(D4,			IP5_31_28)
-#define GPSR0_3		F_(D3,			IP5_27_24)
-#define GPSR0_2		F_(D2,			IP5_23_20)
-#define GPSR0_1		F_(D1,			IP5_19_16)
-#define GPSR0_0		F_(D0,			IP5_15_12)
-
-/* GPSR1 */
-#define GPSR1_28	FM(CLKOUT)
-#define GPSR1_27	F_(EX_WAIT0_A,		IP5_11_8)
-#define GPSR1_26	F_(WE1_N,		IP5_7_4)
-#define GPSR1_25	F_(WE0_N,		IP5_3_0)
-#define GPSR1_24	F_(RD_WR_N,		IP4_31_28)
-#define GPSR1_23	F_(RD_N,		IP4_27_24)
-#define GPSR1_22	F_(BS_N,		IP4_23_20)
-#define GPSR1_21	F_(CS1_N,		IP4_19_16)
-#define GPSR1_20	F_(CS0_N,		IP4_15_12)
-#define GPSR1_19	F_(A19,			IP4_11_8)
-#define GPSR1_18	F_(A18,			IP4_7_4)
-#define GPSR1_17	F_(A17,			IP4_3_0)
-#define GPSR1_16	F_(A16,			IP3_31_28)
-#define GPSR1_15	F_(A15,			IP3_27_24)
-#define GPSR1_14	F_(A14,			IP3_23_20)
-#define GPSR1_13	F_(A13,			IP3_19_16)
-#define GPSR1_12	F_(A12,			IP3_15_12)
-#define GPSR1_11	F_(A11,			IP3_11_8)
-#define GPSR1_10	F_(A10,			IP3_7_4)
-#define GPSR1_9		F_(A9,			IP3_3_0)
-#define GPSR1_8		F_(A8,			IP2_31_28)
-#define GPSR1_7		F_(A7,			IP2_27_24)
-#define GPSR1_6		F_(A6,			IP2_23_20)
-#define GPSR1_5		F_(A5,			IP2_19_16)
-#define GPSR1_4		F_(A4,			IP2_15_12)
-#define GPSR1_3		F_(A3,			IP2_11_8)
-#define GPSR1_2		F_(A2,			IP2_7_4)
-#define GPSR1_1		F_(A1,			IP2_3_0)
-#define GPSR1_0		F_(A0,			IP1_31_28)
-
-/* GPSR2 */
-#define GPSR2_14	F_(AVB_AVTP_CAPTURE_A,	IP0_23_20)
-#define GPSR2_13	F_(AVB_AVTP_MATCH_A,	IP0_19_16)
-#define GPSR2_12	F_(AVB_LINK,		IP0_15_12)
-#define GPSR2_11	F_(AVB_PHY_INT,		IP0_11_8)
-#define GPSR2_10	F_(AVB_MAGIC,		IP0_7_4)
-#define GPSR2_9		F_(AVB_MDC,		IP0_3_0)
-#define GPSR2_8		F_(PWM2_A,		IP1_27_24)
-#define GPSR2_7		F_(PWM1_A,		IP1_23_20)
-#define GPSR2_6		F_(PWM0,		IP1_19_16)
-#define GPSR2_5		F_(IRQ5,		IP1_15_12)
-#define GPSR2_4		F_(IRQ4,		IP1_11_8)
-#define GPSR2_3		F_(IRQ3,		IP1_7_4)
-#define GPSR2_2		F_(IRQ2,		IP1_3_0)
-#define GPSR2_1		F_(IRQ1,		IP0_31_28)
-#define GPSR2_0		F_(IRQ0,		IP0_27_24)
-
-/* GPSR3 */
-#define GPSR3_15	F_(SD1_WP,		IP11_23_20)
-#define GPSR3_14	F_(SD1_CD,		IP11_19_16)
-#define GPSR3_13	F_(SD0_WP,		IP11_15_12)
-#define GPSR3_12	F_(SD0_CD,		IP11_11_8)
-#define GPSR3_11	F_(SD1_DAT3,		IP8_31_28)
-#define GPSR3_10	F_(SD1_DAT2,		IP8_27_24)
-#define GPSR3_9		F_(SD1_DAT1,		IP8_23_20)
-#define GPSR3_8		F_(SD1_DAT0,		IP8_19_16)
-#define GPSR3_7		F_(SD1_CMD,		IP8_15_12)
-#define GPSR3_6		F_(SD1_CLK,		IP8_11_8)
-#define GPSR3_5		F_(SD0_DAT3,		IP8_7_4)
-#define GPSR3_4		F_(SD0_DAT2,		IP8_3_0)
-#define GPSR3_3		F_(SD0_DAT1,		IP7_31_28)
-#define GPSR3_2		F_(SD0_DAT0,		IP7_27_24)
-#define GPSR3_1		F_(SD0_CMD,		IP7_23_20)
-#define GPSR3_0		F_(SD0_CLK,		IP7_19_16)
-
-/* GPSR4 */
-#define GPSR4_17	F_(SD3_DS,		IP11_7_4)
-#define GPSR4_16	F_(SD3_DAT7,		IP11_3_0)
-#define GPSR4_15	F_(SD3_DAT6,		IP10_31_28)
-#define GPSR4_14	F_(SD3_DAT5,		IP10_27_24)
-#define GPSR4_13	F_(SD3_DAT4,		IP10_23_20)
-#define GPSR4_12	F_(SD3_DAT3,		IP10_19_16)
-#define GPSR4_11	F_(SD3_DAT2,		IP10_15_12)
-#define GPSR4_10	F_(SD3_DAT1,		IP10_11_8)
-#define GPSR4_9		F_(SD3_DAT0,		IP10_7_4)
-#define GPSR4_8		F_(SD3_CMD,		IP10_3_0)
-#define GPSR4_7		F_(SD3_CLK,		IP9_31_28)
-#define GPSR4_6		F_(SD2_DS,		IP9_27_24)
-#define GPSR4_5		F_(SD2_DAT3,		IP9_23_20)
-#define GPSR4_4		F_(SD2_DAT2,		IP9_19_16)
-#define GPSR4_3		F_(SD2_DAT1,		IP9_15_12)
-#define GPSR4_2		F_(SD2_DAT0,		IP9_11_8)
-#define GPSR4_1		F_(SD2_CMD,		IP9_7_4)
-#define GPSR4_0		F_(SD2_CLK,		IP9_3_0)
-
-/* GPSR5 */
-#define GPSR5_25	F_(MLB_DAT,		IP14_19_16)
-#define GPSR5_24	F_(MLB_SIG,		IP14_15_12)
-#define GPSR5_23	F_(MLB_CLK,		IP14_11_8)
-#define GPSR5_22	FM(MSIOF0_RXD)
-#define GPSR5_21	F_(MSIOF0_SS2,		IP14_7_4)
-#define GPSR5_20	FM(MSIOF0_TXD)
-#define GPSR5_19	F_(MSIOF0_SS1,		IP14_3_0)
-#define GPSR5_18	F_(MSIOF0_SYNC,		IP13_31_28)
-#define GPSR5_17	FM(MSIOF0_SCK)
-#define GPSR5_16	F_(HRTS0_N,		IP13_27_24)
-#define GPSR5_15	F_(HCTS0_N,		IP13_23_20)
-#define GPSR5_14	F_(HTX0,		IP13_19_16)
-#define GPSR5_13	F_(HRX0,		IP13_15_12)
-#define GPSR5_12	F_(HSCK0,		IP13_11_8)
-#define GPSR5_11	F_(RX2_A,		IP13_7_4)
-#define GPSR5_10	F_(TX2_A,		IP13_3_0)
-#define GPSR5_9		F_(SCK2,		IP12_31_28)
-#define GPSR5_8		F_(RTS1_N,		IP12_27_24)
-#define GPSR5_7		F_(CTS1_N,		IP12_23_20)
-#define GPSR5_6		F_(TX1_A,		IP12_19_16)
-#define GPSR5_5		F_(RX1_A,		IP12_15_12)
-#define GPSR5_4		F_(RTS0_N,		IP12_11_8)
-#define GPSR5_3		F_(CTS0_N,		IP12_7_4)
-#define GPSR5_2		F_(TX0,			IP12_3_0)
-#define GPSR5_1		F_(RX0,			IP11_31_28)
-#define GPSR5_0		F_(SCK0,		IP11_27_24)
-
-/* GPSR6 */
-#define GPSR6_31	F_(USB2_CH3_OVC,	IP18_7_4)
-#define GPSR6_30	F_(USB2_CH3_PWEN,	IP18_3_0)
-#define GPSR6_29	F_(USB30_OVC,		IP17_31_28)
-#define GPSR6_28	F_(USB30_PWEN,		IP17_27_24)
-#define GPSR6_27	F_(USB1_OVC,		IP17_23_20)
-#define GPSR6_26	F_(USB1_PWEN,		IP17_19_16)
-#define GPSR6_25	F_(USB0_OVC,		IP17_15_12)
-#define GPSR6_24	F_(USB0_PWEN,		IP17_11_8)
-#define GPSR6_23	F_(AUDIO_CLKB_B,	IP17_7_4)
-#define GPSR6_22	F_(AUDIO_CLKA_A,	IP17_3_0)
-#define GPSR6_21	F_(SSI_SDATA9_A,	IP16_31_28)
-#define GPSR6_20	F_(SSI_SDATA8,		IP16_27_24)
-#define GPSR6_19	F_(SSI_SDATA7,		IP16_23_20)
-#define GPSR6_18	F_(SSI_WS78,		IP16_19_16)
-#define GPSR6_17	F_(SSI_SCK78,		IP16_15_12)
-#define GPSR6_16	F_(SSI_SDATA6,		IP16_11_8)
-#define GPSR6_15	F_(SSI_WS6,		IP16_7_4)
-#define GPSR6_14	F_(SSI_SCK6,		IP16_3_0)
-#define GPSR6_13	FM(SSI_SDATA5)
-#define GPSR6_12	FM(SSI_WS5)
-#define GPSR6_11	FM(SSI_SCK5)
-#define GPSR6_10	F_(SSI_SDATA4,		IP15_31_28)
-#define GPSR6_9		F_(SSI_WS4,		IP15_27_24)
-#define GPSR6_8		F_(SSI_SCK4,		IP15_23_20)
-#define GPSR6_7		F_(SSI_SDATA3,		IP15_19_16)
-#define GPSR6_6		F_(SSI_WS349,		IP15_15_12)
-#define GPSR6_5		F_(SSI_SCK349,		IP15_11_8)
-#define GPSR6_4		F_(SSI_SDATA2_A,	IP15_7_4)
-#define GPSR6_3		F_(SSI_SDATA1_A,	IP15_3_0)
-#define GPSR6_2		F_(SSI_SDATA0,		IP14_31_28)
-#define GPSR6_1		F_(SSI_WS01239,		IP14_27_24)
-#define GPSR6_0		F_(SSI_SCK01239,		IP14_23_20)
-
-/* GPSR7 */
-#define GPSR7_3		FM(GP7_03)
-#define GPSR7_2		FM(GP7_02)
-#define GPSR7_1		FM(AVS2)
-#define GPSR7_0		FM(AVS1)
-
-
-/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
-#define IP0_3_0		FM(AVB_MDC)		F_(0, 0)	FM(MSIOF2_SS2_C)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_7_4		FM(AVB_MAGIC)		F_(0, 0)	FM(MSIOF2_SS1_C)	FM(SCK4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_11_8	FM(AVB_PHY_INT)		F_(0, 0)	FM(MSIOF2_SYNC_C)	FM(RX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_15_12	FM(AVB_LINK)		F_(0, 0)	FM(MSIOF2_SCK_C)	FM(TX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_19_16	FM(AVB_AVTP_MATCH_A)	F_(0, 0)	FM(MSIOF2_RXD_C)	FM(CTS4_N_A)			F_(0, 0)	FM(FSCLKST2_N_A) F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_23_20	FM(AVB_AVTP_CAPTURE_A)	F_(0, 0)	FM(MSIOF2_TXD_C)	FM(RTS4_N_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_27_24	FM(IRQ0)		FM(QPOLB)	F_(0, 0)		FM(DU_CDE)			FM(VI4_DATA0_B) FM(CAN0_TX_B)	FM(CANFD0_TX_B)		FM(MSIOF3_SS2_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_31_28	FM(IRQ1)		FM(QPOLA)	F_(0, 0)		FM(DU_DISP)			FM(VI4_DATA1_B) FM(CAN0_RX_B)	FM(CANFD0_RX_B)		FM(MSIOF3_SS1_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_3_0		FM(IRQ2)		FM(QCPV_QDE)	F_(0, 0)		FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(VI4_DATA2_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SYNC_E) F_(0, 0)		FM(PWM3_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_7_4		FM(IRQ3)		FM(QSTVB_QVE)	F_(0, 0)		FM(DU_DOTCLKOUT1)		FM(VI4_DATA3_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SCK_E) F_(0, 0)		FM(PWM4_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_11_8	FM(IRQ4)		FM(QSTH_QHS)	F_(0, 0)		FM(DU_EXHSYNC_DU_HSYNC)		FM(VI4_DATA4_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_RXD_E) F_(0, 0)		FM(PWM5_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_15_12	FM(IRQ5)		FM(QSTB_QHE)	F_(0, 0)		FM(DU_EXVSYNC_DU_VSYNC)		FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0)		FM(MSIOF3_TXD_E) F_(0, 0)		FM(PWM6_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_19_16	FM(PWM0)		FM(AVB_AVTP_PPS)F_(0, 0)		F_(0, 0)			FM(VI4_DATA6_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IECLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_23_20	FM(PWM1_A)		F_(0, 0)	F_(0, 0)		FM(HRX3_D)			FM(VI4_DATA7_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IERX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_27_24	FM(PWM2_A)		F_(0, 0)	F_(0, 0)		FM(HTX3_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IETX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_31_28	FM(A0)			FM(LCDOUT16)	FM(MSIOF3_SYNC_B)	F_(0, 0)			FM(VI4_DATA8)	F_(0, 0)	FM(DU_DB0)		F_(0, 0)	F_(0, 0)		FM(PWM3_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_3_0		FM(A1)			FM(LCDOUT17)	FM(MSIOF3_TXD_B)	F_(0, 0)			FM(VI4_DATA9)	F_(0, 0)	FM(DU_DB1)		F_(0, 0)	F_(0, 0)		FM(PWM4_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_7_4		FM(A2)			FM(LCDOUT18)	FM(MSIOF3_SCK_B)	F_(0, 0)			FM(VI4_DATA10)	F_(0, 0)	FM(DU_DB2)		F_(0, 0)	F_(0, 0)		FM(PWM5_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_11_8	FM(A3)			FM(LCDOUT19)	FM(MSIOF3_RXD_B)	F_(0, 0)			FM(VI4_DATA11)	F_(0, 0)	FM(DU_DB3)		F_(0, 0)	F_(0, 0)		FM(PWM6_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
-#define IP2_15_12	FM(A4)			FM(LCDOUT20)	FM(MSIOF3_SS1_B)	F_(0, 0)			FM(VI4_DATA12)	FM(VI5_DATA12)	FM(DU_DB4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_19_16	FM(A5)			FM(LCDOUT21)	FM(MSIOF3_SS2_B)	FM(SCK4_B)			FM(VI4_DATA13)	FM(VI5_DATA13)	FM(DU_DB5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_23_20	FM(A6)			FM(LCDOUT22)	FM(MSIOF2_SS1_A)	FM(RX4_B)			FM(VI4_DATA14)	FM(VI5_DATA14)	FM(DU_DB6)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_27_24	FM(A7)			FM(LCDOUT23)	FM(MSIOF2_SS2_A)	FM(TX4_B)			FM(VI4_DATA15)	FM(VI5_DATA15)	FM(DU_DB7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_31_28	FM(A8)			FM(RX3_B)	FM(MSIOF2_SYNC_A)	FM(HRX4_B)			F_(0, 0)	F_(0, 0)	F_(0, 0)		FM(SDA6_A)	FM(AVB_AVTP_MATCH_B)	FM(PWM1_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_3_0		FM(A9)			F_(0, 0)	FM(MSIOF2_SCK_A)	FM(CTS4_N_B)			F_(0, 0)	FM(VI5_VSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_7_4		FM(A10)			F_(0, 0)	FM(MSIOF2_RXD_A)	FM(RTS4_N_B)			F_(0, 0)	FM(VI5_HSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_11_8	FM(A11)			FM(TX3_B)	FM(MSIOF2_TXD_A)	FM(HTX4_B)			FM(HSCK4)	FM(VI5_FIELD)	F_(0, 0)		FM(SCL6_A)	FM(AVB_AVTP_CAPTURE_B)	FM(PWM2_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_15_12	FM(A12)			FM(LCDOUT12)	FM(MSIOF3_SCK_C)	F_(0, 0)			FM(HRX4_A)	FM(VI5_DATA8)	FM(DU_DG4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_19_16	FM(A13)			FM(LCDOUT13)	FM(MSIOF3_SYNC_C)	F_(0, 0)			FM(HTX4_A)	FM(VI5_DATA9)	FM(DU_DG5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_23_20	FM(A14)			FM(LCDOUT14)	FM(MSIOF3_RXD_C)	F_(0, 0)			FM(HCTS4_N)	FM(VI5_DATA10)	FM(DU_DG6)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_27_24	FM(A15)			FM(LCDOUT15)	FM(MSIOF3_TXD_C)	F_(0, 0)			FM(HRTS4_N)	FM(VI5_DATA11)	FM(DU_DG7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_31_28	FM(A16)			FM(LCDOUT8)	F_(0, 0)		F_(0, 0)			FM(VI4_FIELD)	F_(0, 0)	FM(DU_DG0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_3_0		FM(A17)			FM(LCDOUT9)	F_(0, 0)		F_(0, 0)			FM(VI4_VSYNC_N)	F_(0, 0)	FM(DU_DG1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_7_4		FM(A18)			FM(LCDOUT10)	F_(0, 0)		F_(0, 0)			FM(VI4_HSYNC_N)	F_(0, 0)	FM(DU_DG2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_11_8	FM(A19)			FM(LCDOUT11)	F_(0, 0)		F_(0, 0)			FM(VI4_CLKENB)	F_(0, 0)	FM(DU_DG3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_15_12	FM(CS0_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(VI5_CLKENB)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_19_16	FM(CS1_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(VI5_CLK)	F_(0, 0)		FM(EX_WAIT0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_23_20	FM(BS_N)		FM(QSTVA_QVS)	FM(MSIOF3_SCK_D)	FM(SCK3)			FM(HSCK3)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN1_TX)		FM(CANFD1_TX)	FM(IETX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_27_24	FM(RD_N)		F_(0, 0)	FM(MSIOF3_SYNC_D)	FM(RX3_A)			FM(HRX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_TX_A)		FM(CANFD0_TX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_31_28	FM(RD_WR_N)		F_(0, 0)	FM(MSIOF3_RXD_D)	FM(TX3_A)			FM(HTX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_RX_A)		FM(CANFD0_RX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_3_0		FM(WE0_N)		F_(0, 0)	FM(MSIOF3_TXD_D)	FM(CTS3_N)			FM(HCTS3_N)	F_(0, 0)	F_(0, 0)		FM(SCL6_B)	FM(CAN_CLK)		F_(0, 0)	FM(IECLK_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_7_4		FM(WE1_N)		F_(0, 0)	FM(MSIOF3_SS1_D)	FM(RTS3_N)			FM(HRTS3_N)	F_(0, 0)	F_(0, 0)		FM(SDA6_B)	FM(CAN1_RX)		FM(CANFD1_RX)	FM(IERX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_11_8	FM(EX_WAIT0_A)		FM(QCLK)	F_(0, 0)		F_(0, 0)			FM(VI4_CLK)	F_(0, 0)	FM(DU_DOTCLKOUT0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_15_12	FM(D0)			FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)	F_(0, 0)			FM(VI4_DATA16)	FM(VI5_DATA0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_19_16	FM(D1)			FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)	F_(0, 0)			FM(VI4_DATA17)	FM(VI5_DATA1)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_23_20	FM(D2)			F_(0, 0)	FM(MSIOF3_RXD_A)	F_(0, 0)			FM(VI4_DATA18)	FM(VI5_DATA2)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_27_24	FM(D3)			F_(0, 0)	FM(MSIOF3_TXD_A)	F_(0, 0)			FM(VI4_DATA19)	FM(VI5_DATA3)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_31_28	FM(D4)			FM(MSIOF2_SCK_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA20)	FM(VI5_DATA4)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_3_0		FM(D5)			FM(MSIOF2_SYNC_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA21)	FM(VI5_DATA5)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_7_4		FM(D6)			FM(MSIOF2_RXD_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA22)	FM(VI5_DATA6)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_11_8	FM(D7)			FM(MSIOF2_TXD_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA23)	FM(VI5_DATA7)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_15_12	FM(D8)			FM(LCDOUT0)	FM(MSIOF2_SCK_D)	FM(SCK4_C)			FM(VI4_DATA0_A)	F_(0, 0)	FM(DU_DR0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_19_16	FM(D9)			FM(LCDOUT1)	FM(MSIOF2_SYNC_D)	F_(0, 0)			FM(VI4_DATA1_A)	F_(0, 0)	FM(DU_DR1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_23_20	FM(D10)			FM(LCDOUT2)	FM(MSIOF2_RXD_D)	FM(HRX3_B)			FM(VI4_DATA2_A)	FM(CTS4_N_C)	FM(DU_DR2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_27_24	FM(D11)			FM(LCDOUT3)	FM(MSIOF2_TXD_D)	FM(HTX3_B)			FM(VI4_DATA3_A)	FM(RTS4_N_C)	FM(DU_DR3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_31_28	FM(D12)			FM(LCDOUT4)	FM(MSIOF2_SS1_D)	FM(RX4_C)			FM(VI4_DATA4_A)	F_(0, 0)	FM(DU_DR4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_3_0		FM(D13)			FM(LCDOUT5)	FM(MSIOF2_SS2_D)	FM(TX4_C)			FM(VI4_DATA5_A)	F_(0, 0)	FM(DU_DR5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_7_4		FM(D14)			FM(LCDOUT6)	FM(MSIOF3_SS1_A)	FM(HRX3_C)			FM(VI4_DATA6_A)	F_(0, 0)	FM(DU_DR6)		FM(SCL6_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_11_8	FM(D15)			FM(LCDOUT7)	FM(MSIOF3_SS2_A)	FM(HTX3_C)			FM(VI4_DATA7_A)	F_(0, 0)	FM(DU_DR7)		FM(SDA6_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_19_16	FM(SD0_CLK)		F_(0, 0)	FM(MSIOF1_SCK_E)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_OPWM_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
-#define IP7_23_20	FM(SD0_CMD)		F_(0, 0)	FM(MSIOF1_SYNC_E)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_27_24	FM(SD0_DAT0)		F_(0, 0)	FM(MSIOF1_RXD_E)	F_(0, 0)			F_(0, 0)	FM(TS_SCK0_B)	FM(STP_ISCLK_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_31_28	FM(SD0_DAT1)		F_(0, 0)	FM(MSIOF1_TXD_E)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_3_0		FM(SD0_DAT2)		F_(0, 0)	FM(MSIOF1_SS1_E)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_B)	FM(STP_ISD_0_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_7_4		FM(SD0_DAT3)		F_(0, 0)	FM(MSIOF1_SS2_E)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_B)	FM(STP_ISEN_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_11_8	FM(SD1_CLK)		F_(0, 0)	FM(MSIOF1_SCK_G)	F_(0, 0)			F_(0, 0)	FM(SIM0_CLK_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_15_12	FM(SD1_CMD)		F_(0, 0)	FM(MSIOF1_SYNC_G)	FM(NFCE_N_B)			F_(0, 0)	FM(SIM0_D_A)	FM(STP_IVCXO27_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_19_16	FM(SD1_DAT0)		FM(SD2_DAT4)	FM(MSIOF1_RXD_G)	FM(NFWP_N_B)			F_(0, 0)	FM(TS_SCK1_B)	FM(STP_ISCLK_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_23_20	FM(SD1_DAT1)		FM(SD2_DAT5)	FM(MSIOF1_TXD_G)	FM(NFDATA14_B)			F_(0, 0)	FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_27_24	FM(SD1_DAT2)		FM(SD2_DAT6)	FM(MSIOF1_SS1_G)	FM(NFDATA15_B)			F_(0, 0)	FM(TS_SDAT1_B)	FM(STP_ISD_1_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_31_28	FM(SD1_DAT3)		FM(SD2_DAT7)	FM(MSIOF1_SS2_G)	FM(NFRB_N_B)			F_(0, 0)	FM(TS_SDEN1_B)	FM(STP_ISEN_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_3_0		FM(SD2_CLK)		F_(0, 0)	FM(NFDATA8)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_7_4		FM(SD2_CMD)		F_(0, 0)	FM(NFDATA9)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_11_8	FM(SD2_DAT0)		F_(0, 0)	FM(NFDATA10)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_15_12	FM(SD2_DAT1)		F_(0, 0)	FM(NFDATA11)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_19_16	FM(SD2_DAT2)		F_(0, 0)	FM(NFDATA12)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_23_20	FM(SD2_DAT3)		F_(0, 0)	FM(NFDATA13)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_27_24	FM(SD2_DS)		F_(0, 0)	FM(NFALE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(SATA_DEVSLP_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_31_28	FM(SD3_CLK)		F_(0, 0)	FM(NFWE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_3_0	FM(SD3_CMD)		F_(0, 0)	FM(NFRE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_7_4	FM(SD3_DAT0)		F_(0, 0)	FM(NFDATA0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_11_8	FM(SD3_DAT1)		F_(0, 0)	FM(NFDATA1)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_15_12	FM(SD3_DAT2)		F_(0, 0)	FM(NFDATA2)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_19_16	FM(SD3_DAT3)		F_(0, 0)	FM(NFDATA3)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_23_20	FM(SD3_DAT4)		FM(SD2_CD_A)	FM(NFDATA4)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_27_24	FM(SD3_DAT5)		FM(SD2_WP_A)	FM(NFDATA5)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_31_28	FM(SD3_DAT6)		FM(SD3_CD)	FM(NFDATA6)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_3_0	FM(SD3_DAT7)		FM(SD3_WP)	FM(NFDATA7)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_7_4	FM(SD3_DS)		F_(0, 0)	FM(NFCLE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_11_8	FM(SD0_CD)		F_(0, 0)	FM(NFDATA14_A)		F_(0, 0)			FM(SCL2_B)	FM(SIM0_RST_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
-#define IP11_15_12	FM(SD0_WP)		F_(0, 0)	FM(NFDATA15_A)		F_(0, 0)			FM(SDA2_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_19_16	FM(SD1_CD)		F_(0, 0)	FM(NFRB_N_A)		F_(0, 0)			F_(0, 0)	FM(SIM0_CLK_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_23_20	FM(SD1_WP)		F_(0, 0)	FM(NFCE_N_A)		F_(0, 0)			F_(0, 0)	FM(SIM0_D_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_27_24	FM(SCK0)		FM(HSCK1_B)	FM(MSIOF1_SS2_B)	FM(AUDIO_CLKC_B)		FM(SDA2_A)	FM(SIM0_RST_B)	FM(STP_OPWM_0_C)	FM(RIF0_CLK_B)	F_(0, 0)		FM(ADICHS2)	FM(SCK5_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_31_28	FM(RX0)			FM(HRX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SCK0_C)	FM(STP_ISCLK_0_C)	FM(RIF0_D0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_3_0	FM(TX0)			FM(HTX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)	FM(RIF0_D1_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_7_4	FM(CTS0_N)		FM(HCTS1_N_B)	FM(MSIOF1_SYNC_B)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)	FM(RIF1_SYNC_B)	FM(AUDIO_CLKOUT_C)	FM(ADICS_SAMP)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_11_8	FM(RTS0_N)		FM(HRTS1_N_B)	FM(MSIOF1_SS1_B)	FM(AUDIO_CLKA_B)		FM(SCL2_A)	F_(0, 0)	FM(STP_IVCXO27_1_C)	FM(RIF0_SYNC_B)	F_(0, 0)		FM(ADICHS1)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_15_12	FM(RX1_A)		FM(HRX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_C)	FM(STP_ISD_0_C)		FM(RIF1_CLK_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_19_16	FM(TX1_A)		FM(HTX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_C)	FM(STP_ISEN_0_C)	FM(RIF1_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_23_20	FM(CTS1_N)		FM(HCTS1_N_A)	FM(MSIOF1_RXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_C)	FM(STP_ISEN_1_C)	FM(RIF1_D0_B)	F_(0, 0)		FM(ADIDATA)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_27_24	FM(RTS1_N)		FM(HRTS1_N_A)	FM(MSIOF1_TXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_C)	FM(STP_ISD_1_C)		FM(RIF1_D1_B)	F_(0, 0)		FM(ADICHS0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_31_28	FM(SCK2)		FM(SCIF_CLK_B)	FM(MSIOF1_SCK_B)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_C)	FM(STP_ISCLK_1_C)	FM(RIF1_CLK_B)	F_(0, 0)		FM(ADICLK)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_3_0	FM(TX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_CD_B)			FM(SCL1_A)	F_(0, 0)	FM(FMCLK_A)		FM(RIF1_D1_C)	F_(0, 0)		FM(FSO_CFE_0_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_7_4	FM(RX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_WP_B)			FM(SDA1_A)	F_(0, 0)	FM(FMIN_A)		FM(RIF1_SYNC_C)	F_(0, 0)		FM(FSO_CFE_1_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_11_8	FM(HSCK0)		F_(0, 0)	FM(MSIOF1_SCK_D)	FM(AUDIO_CLKB_A)		FM(SSI_SDATA1_B)FM(TS_SCK0_D)	FM(STP_ISCLK_0_D)	FM(RIF0_CLK_C)	F_(0, 0)		F_(0, 0)	FM(RX5_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_15_12	FM(HRX0)		F_(0, 0)	FM(MSIOF1_RXD_D)	F_(0, 0)			FM(SSI_SDATA2_B)FM(TS_SDEN0_D)	FM(STP_ISEN_0_D)	FM(RIF0_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_19_16	FM(HTX0)		F_(0, 0)	FM(MSIOF1_TXD_D)	F_(0, 0)			FM(SSI_SDATA9_B)FM(TS_SDAT0_D)	FM(STP_ISD_0_D)		FM(RIF0_D1_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_23_20	FM(HCTS0_N)		FM(RX2_B)	FM(MSIOF1_SYNC_D)	F_(0, 0)			FM(SSI_SCK9_A)	FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)	FM(RIF0_SYNC_C)	FM(AUDIO_CLKOUT1_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_27_24	FM(HRTS0_N)		FM(TX2_B)	FM(MSIOF1_SS1_D)	F_(0, 0)			FM(SSI_WS9_A)	F_(0, 0)	FM(STP_IVCXO27_0_D)	FM(BPFCLK_A)	FM(AUDIO_CLKOUT2_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_31_28	FM(MSIOF0_SYNC)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(AUDIO_CLKOUT_A)	F_(0, 0)	FM(TX5_B)	F_(0, 0)	F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
-#define IP14_3_0	FM(MSIOF0_SS1)		FM(RX5_A)	FM(NFWP_N_A)		FM(AUDIO_CLKA_C)		FM(SSI_SCK2_A)	F_(0, 0)	FM(STP_IVCXO27_0_C)	F_(0, 0)	FM(AUDIO_CLKOUT3_A)	F_(0, 0)	FM(TCLK1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_7_4	FM(MSIOF0_SS2)		FM(TX5_A)	FM(MSIOF1_SS2_D)	FM(AUDIO_CLKC_A)		FM(SSI_WS2_A)	F_(0, 0)	FM(STP_OPWM_0_D)	F_(0, 0)	FM(AUDIO_CLKOUT_D)	F_(0, 0)	FM(SPEEDIN_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_11_8	FM(MLB_CLK)		F_(0, 0)	FM(MSIOF1_SCK_F)	F_(0, 0)			FM(SCL1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_15_12	FM(MLB_SIG)		FM(RX1_B)	FM(MSIOF1_SYNC_F)	F_(0, 0)			FM(SDA1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_19_16	FM(MLB_DAT)		FM(TX1_B)	FM(MSIOF1_RXD_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_23_20	FM(SSI_SCK01239)	F_(0, 0)	FM(MSIOF1_TXD_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_27_24	FM(SSI_WS01239)		F_(0, 0)	FM(MSIOF1_SS1_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
-#define IP14_31_28	FM(SSI_SDATA0)		F_(0, 0)	FM(MSIOF1_SS2_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_3_0	FM(SSI_SDATA1_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_7_4	FM(SSI_SDATA2_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			FM(SSI_SCK1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_11_8	FM(SSI_SCK349)		F_(0, 0)	FM(MSIOF1_SS1_A)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_OPWM_0_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_15_12	FM(SSI_WS349)		FM(HCTS2_N_A)	FM(MSIOF1_SS2_A)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_0_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_19_16	FM(SSI_SDATA3)		FM(HRTS2_N_A)	FM(MSIOF1_TXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SCK0_A)	FM(STP_ISCLK_0_A)	FM(RIF0_D1_A)	FM(RIF2_D0_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_23_20	FM(SSI_SCK4)		FM(HRX2_A)	FM(MSIOF1_SCK_A)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_A)	FM(STP_ISD_0_A)		FM(RIF0_CLK_A)	FM(RIF2_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_27_24	FM(SSI_WS4)		FM(HTX2_A)	FM(MSIOF1_SYNC_A)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_A)	FM(STP_ISEN_0_A)	FM(RIF0_SYNC_A)	FM(RIF2_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_31_28	FM(SSI_SDATA4)		FM(HSCK2_A)	FM(MSIOF1_RXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)	FM(RIF0_D0_A)	FM(RIF2_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_3_0	FM(SSI_SCK6)		FM(USB2_PWEN)	F_(0, 0)		FM(SIM0_RST_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_7_4	FM(SSI_WS6)		FM(USB2_OVC)	F_(0, 0)		FM(SIM0_D_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_11_8	FM(SSI_SDATA6)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(SATA_DEVSLP_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_15_12	FM(SSI_SCK78)		FM(HRX2_B)	FM(MSIOF1_SCK_C)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_A)	FM(STP_ISCLK_1_A)	FM(RIF1_CLK_A)	FM(RIF3_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_19_16	FM(SSI_WS78)		FM(HTX2_B)	FM(MSIOF1_SYNC_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_A)	FM(STP_ISD_1_A)		FM(RIF1_SYNC_A)	FM(RIF3_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_23_20	FM(SSI_SDATA7)		FM(HCTS2_N_B)	FM(MSIOF1_RXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_A)	FM(STP_ISEN_1_A)	FM(RIF1_D0_A)	FM(RIF3_D0_A)		F_(0, 0)	FM(TCLK2_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_27_24	FM(SSI_SDATA8)		FM(HRTS2_N_B)	FM(MSIOF1_TXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)	FM(RIF1_D1_A)	FM(RIF3_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_31_28	FM(SSI_SDATA9_A)	FM(HSCK2_B)	FM(MSIOF1_SS1_C)	FM(HSCK1_A)			FM(SSI_WS1_B)	FM(SCK1)	FM(STP_IVCXO27_1_A)	FM(SCK5_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP17_3_0	FM(AUDIO_CLKA_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP17_7_4	FM(AUDIO_CLKB_B)	FM(SCIF_CLK_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_1_D)	FM(REMOCON_A)	F_(0, 0)		F_(0, 0)	FM(TCLK1_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP17_11_8	FM(USB0_PWEN)		F_(0, 0)	F_(0, 0)		FM(SIM0_RST_C)			F_(0, 0)	FM(TS_SCK1_D)	FM(STP_ISCLK_1_D)	FM(BPFCLK_B)	FM(RIF3_CLK_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
-#define IP17_15_12	FM(USB0_OVC)		F_(0, 0)	F_(0, 0)		FM(SIM0_D_C)			F_(0, 0)	FM(TS_SDAT1_D)	FM(STP_ISD_1_D)		F_(0, 0)	FM(RIF3_SYNC_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
-#define IP17_19_16	FM(USB1_PWEN)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_C)			FM(SSI_SCK1_A)	FM(TS_SCK0_E)	FM(STP_ISCLK_0_E)	FM(FMCLK_B)	FM(RIF2_CLK_B)		F_(0, 0)	FM(SPEEDIN_A)	F_(0, 0)	F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
-#define IP17_23_20	FM(USB1_OVC)		F_(0, 0)	FM(MSIOF1_SS2_C)	F_(0, 0)			FM(SSI_WS1_A)	FM(TS_SDAT0_E)	FM(STP_ISD_0_E)		FM(FMIN_B)	FM(RIF2_SYNC_B)		F_(0, 0)	FM(REMOCON_B)	F_(0, 0)	F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
-#define IP17_27_24	FM(USB30_PWEN)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT_B)		FM(SSI_SCK2_B)	FM(TS_SDEN1_D)	FM(STP_ISEN_1_D)	FM(STP_OPWM_0_E)FM(RIF3_D0_B)		F_(0, 0)	FM(TCLK2_B)	FM(TPU0TO0)	FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
-#define IP17_31_28	FM(USB30_OVC)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT1_B)		FM(SSI_WS2_B)	FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)	FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)	F_(0, 0)	FM(FSO_TOE_N)	FM(TPU0TO1)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP18_3_0	FM(USB2_CH3_PWEN)	F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT2_B)		FM(SSI_SCK9_B)	FM(TS_SDEN0_E)	FM(STP_ISEN_0_E)	F_(0, 0)	FM(RIF2_D0_B)		F_(0, 0)	F_(0, 0)	FM(TPU0TO2)	FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
-#define IP18_7_4	FM(USB2_CH3_OVC)	F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT3_B)		FM(SSI_WS9_B)	FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)	F_(0, 0)	FM(RIF2_D1_B)		F_(0, 0)	F_(0, 0)	FM(TPU0TO3)	FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
-
-#define PINMUX_GPSR	\
-\
-												GPSR6_31 \
-												GPSR6_30 \
-												GPSR6_29 \
-		GPSR1_28									GPSR6_28 \
-		GPSR1_27									GPSR6_27 \
-		GPSR1_26									GPSR6_26 \
-		GPSR1_25							GPSR5_25	GPSR6_25 \
-		GPSR1_24							GPSR5_24	GPSR6_24 \
-		GPSR1_23							GPSR5_23	GPSR6_23 \
-		GPSR1_22							GPSR5_22	GPSR6_22 \
-		GPSR1_21							GPSR5_21	GPSR6_21 \
-		GPSR1_20							GPSR5_20	GPSR6_20 \
-		GPSR1_19							GPSR5_19	GPSR6_19 \
-		GPSR1_18							GPSR5_18	GPSR6_18 \
-		GPSR1_17					GPSR4_17	GPSR5_17	GPSR6_17 \
-		GPSR1_16					GPSR4_16	GPSR5_16	GPSR6_16 \
-GPSR0_15	GPSR1_15			GPSR3_15	GPSR4_15	GPSR5_15	GPSR6_15 \
-GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14	GPSR4_14	GPSR5_14	GPSR6_14 \
-GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13	GPSR4_13	GPSR5_13	GPSR6_13 \
-GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12	GPSR4_12	GPSR5_12	GPSR6_12 \
-GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11	GPSR4_11	GPSR5_11	GPSR6_11 \
-GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10	GPSR6_10 \
-GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9		GPSR6_9 \
-GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8		GPSR6_8 \
-GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7		GPSR6_7 \
-GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6		GPSR6_6 \
-GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5		GPSR6_5 \
-GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4		GPSR6_4 \
-GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3		GPSR6_3		GPSR7_3 \
-GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2		GPSR6_2		GPSR7_2 \
-GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1		GPSR6_1		GPSR7_1 \
-GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0		GPSR6_0		GPSR7_0
-
-#define PINMUX_IPSR				\
-\
-FM(IP0_3_0)	IP0_3_0		FM(IP1_3_0)	IP1_3_0		FM(IP2_3_0)	IP2_3_0		FM(IP3_3_0)	IP3_3_0 \
-FM(IP0_7_4)	IP0_7_4		FM(IP1_7_4)	IP1_7_4		FM(IP2_7_4)	IP2_7_4		FM(IP3_7_4)	IP3_7_4 \
-FM(IP0_11_8)	IP0_11_8	FM(IP1_11_8)	IP1_11_8	FM(IP2_11_8)	IP2_11_8	FM(IP3_11_8)	IP3_11_8 \
-FM(IP0_15_12)	IP0_15_12	FM(IP1_15_12)	IP1_15_12	FM(IP2_15_12)	IP2_15_12	FM(IP3_15_12)	IP3_15_12 \
-FM(IP0_19_16)	IP0_19_16	FM(IP1_19_16)	IP1_19_16	FM(IP2_19_16)	IP2_19_16	FM(IP3_19_16)	IP3_19_16 \
-FM(IP0_23_20)	IP0_23_20	FM(IP1_23_20)	IP1_23_20	FM(IP2_23_20)	IP2_23_20	FM(IP3_23_20)	IP3_23_20 \
-FM(IP0_27_24)	IP0_27_24	FM(IP1_27_24)	IP1_27_24	FM(IP2_27_24)	IP2_27_24	FM(IP3_27_24)	IP3_27_24 \
-FM(IP0_31_28)	IP0_31_28	FM(IP1_31_28)	IP1_31_28	FM(IP2_31_28)	IP2_31_28	FM(IP3_31_28)	IP3_31_28 \
-\
-FM(IP4_3_0)	IP4_3_0		FM(IP5_3_0)	IP5_3_0		FM(IP6_3_0)	IP6_3_0		FM(IP7_3_0)	IP7_3_0 \
-FM(IP4_7_4)	IP4_7_4		FM(IP5_7_4)	IP5_7_4		FM(IP6_7_4)	IP6_7_4		FM(IP7_7_4)	IP7_7_4 \
-FM(IP4_11_8)	IP4_11_8	FM(IP5_11_8)	IP5_11_8	FM(IP6_11_8)	IP6_11_8	FM(IP7_11_8)	IP7_11_8 \
-FM(IP4_15_12)	IP4_15_12	FM(IP5_15_12)	IP5_15_12	FM(IP6_15_12)	IP6_15_12 \
-FM(IP4_19_16)	IP4_19_16	FM(IP5_19_16)	IP5_19_16	FM(IP6_19_16)	IP6_19_16	FM(IP7_19_16)	IP7_19_16 \
-FM(IP4_23_20)	IP4_23_20	FM(IP5_23_20)	IP5_23_20	FM(IP6_23_20)	IP6_23_20	FM(IP7_23_20)	IP7_23_20 \
-FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
-FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
-\
-FM(IP8_3_0)	IP8_3_0		FM(IP9_3_0)	IP9_3_0		FM(IP10_3_0)	IP10_3_0	FM(IP11_3_0)	IP11_3_0 \
-FM(IP8_7_4)	IP8_7_4		FM(IP9_7_4)	IP9_7_4		FM(IP10_7_4)	IP10_7_4	FM(IP11_7_4)	IP11_7_4 \
-FM(IP8_11_8)	IP8_11_8	FM(IP9_11_8)	IP9_11_8	FM(IP10_11_8)	IP10_11_8	FM(IP11_11_8)	IP11_11_8 \
-FM(IP8_15_12)	IP8_15_12	FM(IP9_15_12)	IP9_15_12	FM(IP10_15_12)	IP10_15_12	FM(IP11_15_12)	IP11_15_12 \
-FM(IP8_19_16)	IP8_19_16	FM(IP9_19_16)	IP9_19_16	FM(IP10_19_16)	IP10_19_16	FM(IP11_19_16)	IP11_19_16 \
-FM(IP8_23_20)	IP8_23_20	FM(IP9_23_20)	IP9_23_20	FM(IP10_23_20)	IP10_23_20	FM(IP11_23_20)	IP11_23_20 \
-FM(IP8_27_24)	IP8_27_24	FM(IP9_27_24)	IP9_27_24	FM(IP10_27_24)	IP10_27_24	FM(IP11_27_24)	IP11_27_24 \
-FM(IP8_31_28)	IP8_31_28	FM(IP9_31_28)	IP9_31_28	FM(IP10_31_28)	IP10_31_28	FM(IP11_31_28)	IP11_31_28 \
-\
-FM(IP12_3_0)	IP12_3_0	FM(IP13_3_0)	IP13_3_0	FM(IP14_3_0)	IP14_3_0	FM(IP15_3_0)	IP15_3_0 \
-FM(IP12_7_4)	IP12_7_4	FM(IP13_7_4)	IP13_7_4	FM(IP14_7_4)	IP14_7_4	FM(IP15_7_4)	IP15_7_4 \
-FM(IP12_11_8)	IP12_11_8	FM(IP13_11_8)	IP13_11_8	FM(IP14_11_8)	IP14_11_8	FM(IP15_11_8)	IP15_11_8 \
-FM(IP12_15_12)	IP12_15_12	FM(IP13_15_12)	IP13_15_12	FM(IP14_15_12)	IP14_15_12	FM(IP15_15_12)	IP15_15_12 \
-FM(IP12_19_16)	IP12_19_16	FM(IP13_19_16)	IP13_19_16	FM(IP14_19_16)	IP14_19_16	FM(IP15_19_16)	IP15_19_16 \
-FM(IP12_23_20)	IP12_23_20	FM(IP13_23_20)	IP13_23_20	FM(IP14_23_20)	IP14_23_20	FM(IP15_23_20)	IP15_23_20 \
-FM(IP12_27_24)	IP12_27_24	FM(IP13_27_24)	IP13_27_24	FM(IP14_27_24)	IP14_27_24	FM(IP15_27_24)	IP15_27_24 \
-FM(IP12_31_28)	IP12_31_28	FM(IP13_31_28)	IP13_31_28	FM(IP14_31_28)	IP14_31_28	FM(IP15_31_28)	IP15_31_28 \
-\
-FM(IP16_3_0)	IP16_3_0	FM(IP17_3_0)	IP17_3_0	FM(IP18_3_0)	IP18_3_0 \
-FM(IP16_7_4)	IP16_7_4	FM(IP17_7_4)	IP17_7_4	FM(IP18_7_4)	IP18_7_4 \
-FM(IP16_11_8)	IP16_11_8	FM(IP17_11_8)	IP17_11_8 \
-FM(IP16_15_12)	IP16_15_12	FM(IP17_15_12)	IP17_15_12 \
-FM(IP16_19_16)	IP16_19_16	FM(IP17_19_16)	IP17_19_16 \
-FM(IP16_23_20)	IP16_23_20	FM(IP17_23_20)	IP17_23_20 \
-FM(IP16_27_24)	IP16_27_24	FM(IP17_27_24)	IP17_27_24 \
-FM(IP16_31_28)	IP16_31_28	FM(IP17_31_28)	IP17_31_28
-
-/* MOD_SEL0 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
-#define MOD_SEL0_31_30_29	FM(SEL_MSIOF3_0)	FM(SEL_MSIOF3_1)	FM(SEL_MSIOF3_2)	FM(SEL_MSIOF3_3)	FM(SEL_MSIOF3_4)	F_(0, 0)		F_(0, 0)		F_(0, 0)
-#define MOD_SEL0_28_27		FM(SEL_MSIOF2_0)	FM(SEL_MSIOF2_1)	FM(SEL_MSIOF2_2)	FM(SEL_MSIOF2_3)
-#define MOD_SEL0_26_25_24	FM(SEL_MSIOF1_0)	FM(SEL_MSIOF1_1)	FM(SEL_MSIOF1_2)	FM(SEL_MSIOF1_3)	FM(SEL_MSIOF1_4)	FM(SEL_MSIOF1_5)	FM(SEL_MSIOF1_6)	F_(0, 0)
-#define MOD_SEL0_23		FM(SEL_LBSC_0)		FM(SEL_LBSC_1)
-#define MOD_SEL0_22		FM(SEL_IEBUS_0)		FM(SEL_IEBUS_1)
-#define MOD_SEL0_21		FM(SEL_I2C2_0)		FM(SEL_I2C2_1)
-#define MOD_SEL0_20		FM(SEL_I2C1_0)		FM(SEL_I2C1_1)
-#define MOD_SEL0_19		FM(SEL_HSCIF4_0)	FM(SEL_HSCIF4_1)
-#define MOD_SEL0_18_17		FM(SEL_HSCIF3_0)	FM(SEL_HSCIF3_1)	FM(SEL_HSCIF3_2)	FM(SEL_HSCIF3_3)
-#define MOD_SEL0_16		FM(SEL_HSCIF1_0)	FM(SEL_HSCIF1_1)
-#define MOD_SEL0_14_13		FM(SEL_HSCIF2_0)	FM(SEL_HSCIF2_1)	FM(SEL_HSCIF2_2)	F_(0, 0)
-#define MOD_SEL0_12		FM(SEL_ETHERAVB_0)	FM(SEL_ETHERAVB_1)
-#define MOD_SEL0_11		FM(SEL_DRIF3_0)		FM(SEL_DRIF3_1)
-#define MOD_SEL0_10		FM(SEL_DRIF2_0)		FM(SEL_DRIF2_1)
-#define MOD_SEL0_9_8		FM(SEL_DRIF1_0)		FM(SEL_DRIF1_1)		FM(SEL_DRIF1_2)		F_(0, 0)
-#define MOD_SEL0_7_6		FM(SEL_DRIF0_0)		FM(SEL_DRIF0_1)		FM(SEL_DRIF0_2)		F_(0, 0)
-#define MOD_SEL0_5		FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
-#define MOD_SEL0_4_3		FM(SEL_ADGA_0)		FM(SEL_ADGA_1)		FM(SEL_ADGA_2)		FM(SEL_ADGA_3)
-
-/* MOD_SEL1 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
-#define MOD_SEL1_31_30		FM(SEL_TSIF1_0)		FM(SEL_TSIF1_1)		FM(SEL_TSIF1_2)		FM(SEL_TSIF1_3)
-#define MOD_SEL1_29_28_27	FM(SEL_TSIF0_0)		FM(SEL_TSIF0_1)		FM(SEL_TSIF0_2)		FM(SEL_TSIF0_3)		FM(SEL_TSIF0_4)		F_(0, 0)		F_(0, 0)		F_(0, 0)
-#define MOD_SEL1_26		FM(SEL_TIMER_TMU1_0)	FM(SEL_TIMER_TMU1_1)
-#define MOD_SEL1_25_24		FM(SEL_SSP1_1_0)	FM(SEL_SSP1_1_1)	FM(SEL_SSP1_1_2)	FM(SEL_SSP1_1_3)
-#define MOD_SEL1_23_22_21	FM(SEL_SSP1_0_0)	FM(SEL_SSP1_0_1)	FM(SEL_SSP1_0_2)	FM(SEL_SSP1_0_3)	FM(SEL_SSP1_0_4)	F_(0, 0)		F_(0, 0)		F_(0, 0)
-#define MOD_SEL1_20		FM(SEL_SSI1_0)		FM(SEL_SSI1_1)
-#define MOD_SEL1_19		FM(SEL_SPEED_PULSE_0)	FM(SEL_SPEED_PULSE_1)
-#define MOD_SEL1_18_17		FM(SEL_SIMCARD_0)	FM(SEL_SIMCARD_1)	FM(SEL_SIMCARD_2)	FM(SEL_SIMCARD_3)
-#define MOD_SEL1_16		FM(SEL_SDHI2_0)		FM(SEL_SDHI2_1)
-#define MOD_SEL1_15_14		FM(SEL_SCIF4_0)		FM(SEL_SCIF4_1)		FM(SEL_SCIF4_2)		F_(0, 0)
-#define MOD_SEL1_13		FM(SEL_SCIF3_0)		FM(SEL_SCIF3_1)
-#define MOD_SEL1_12		FM(SEL_SCIF2_0)		FM(SEL_SCIF2_1)
-#define MOD_SEL1_11		FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
-#define MOD_SEL1_10		FM(SEL_SCIF_0)		FM(SEL_SCIF_1)
-#define MOD_SEL1_9		FM(SEL_REMOCON_0)	FM(SEL_REMOCON_1)
-#define MOD_SEL1_6		FM(SEL_RCAN0_0)		FM(SEL_RCAN0_1)
-#define MOD_SEL1_5		FM(SEL_PWM6_0)		FM(SEL_PWM6_1)
-#define MOD_SEL1_4		FM(SEL_PWM5_0)		FM(SEL_PWM5_1)
-#define MOD_SEL1_3		FM(SEL_PWM4_0)		FM(SEL_PWM4_1)
-#define MOD_SEL1_2		FM(SEL_PWM3_0)		FM(SEL_PWM3_1)
-#define MOD_SEL1_1		FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
-#define MOD_SEL1_0		FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
-
-/* MOD_SEL2 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */
-#define MOD_SEL2_31		FM(I2C_SEL_5_0)		FM(I2C_SEL_5_1)
-#define MOD_SEL2_30		FM(I2C_SEL_3_0)		FM(I2C_SEL_3_1)
-#define MOD_SEL2_29		FM(I2C_SEL_0_0)		FM(I2C_SEL_0_1)
-#define MOD_SEL2_28_27		FM(SEL_FM_0)		FM(SEL_FM_1)		FM(SEL_FM_2)		FM(SEL_FM_3)
-#define MOD_SEL2_26		FM(SEL_SCIF5_0)		FM(SEL_SCIF5_1)
-#define MOD_SEL2_25_24_23	FM(SEL_I2C6_0)		FM(SEL_I2C6_1)		FM(SEL_I2C6_2)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)
-#define MOD_SEL2_21		FM(SEL_SSI2_0)		FM(SEL_SSI2_1)
-#define MOD_SEL2_20		FM(SEL_SSI9_0)		FM(SEL_SSI9_1)
-#define MOD_SEL2_19		FM(SEL_TIMER_TMU2_0)	FM(SEL_TIMER_TMU2_1)
-#define MOD_SEL2_18		FM(SEL_ADGB_0)		FM(SEL_ADGB_1)
-#define MOD_SEL2_17		FM(SEL_ADGC_0)		FM(SEL_ADGC_1)
-#define MOD_SEL2_0		FM(SEL_VIN4_0)		FM(SEL_VIN4_1)
-
-#define PINMUX_MOD_SELS	\
-\
-MOD_SEL0_31_30_29	MOD_SEL1_31_30		MOD_SEL2_31 \
-						MOD_SEL2_30 \
-			MOD_SEL1_29_28_27	MOD_SEL2_29 \
-MOD_SEL0_28_27					MOD_SEL2_28_27 \
-MOD_SEL0_26_25_24	MOD_SEL1_26		MOD_SEL2_26 \
-			MOD_SEL1_25_24		MOD_SEL2_25_24_23 \
-MOD_SEL0_23		MOD_SEL1_23_22_21 \
-MOD_SEL0_22 \
-MOD_SEL0_21					MOD_SEL2_21 \
-MOD_SEL0_20		MOD_SEL1_20		MOD_SEL2_20 \
-MOD_SEL0_19		MOD_SEL1_19		MOD_SEL2_19 \
-MOD_SEL0_18_17		MOD_SEL1_18_17		MOD_SEL2_18 \
-						MOD_SEL2_17 \
-MOD_SEL0_16		MOD_SEL1_16 \
-			MOD_SEL1_15_14 \
-MOD_SEL0_14_13 \
-			MOD_SEL1_13 \
-MOD_SEL0_12		MOD_SEL1_12 \
-MOD_SEL0_11		MOD_SEL1_11 \
-MOD_SEL0_10		MOD_SEL1_10 \
-MOD_SEL0_9_8		MOD_SEL1_9 \
-MOD_SEL0_7_6 \
-			MOD_SEL1_6 \
-MOD_SEL0_5		MOD_SEL1_5 \
-MOD_SEL0_4_3		MOD_SEL1_4 \
-			MOD_SEL1_3 \
-			MOD_SEL1_2 \
-			MOD_SEL1_1 \
-			MOD_SEL1_0		MOD_SEL2_0
-
-/*
- * These pins are not able to be muxed but have other properties
- * that can be set, such as drive-strength or pull-up/pull-down enable.
- */
-#define PINMUX_STATIC \
-	FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
-	FM(QSPI0_IO2) FM(QSPI0_IO3) \
-	FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
-	FM(QSPI1_IO2) FM(QSPI1_IO3) \
-	FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
-	FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
-	FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
-	FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
-	FM(PRESETOUT) \
-	FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
-	FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
-
-#define PINMUX_PHYS \
-	FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	GP_ALL(DATA),
-	PINMUX_DATA_END,
-
-#define F_(x, y)
-#define FM(x)	FN_##x,
-	PINMUX_FUNCTION_BEGIN,
-	GP_ALL(FN),
-	PINMUX_GPSR
-	PINMUX_IPSR
-	PINMUX_MOD_SELS
-	PINMUX_FUNCTION_END,
-#undef F_
-#undef FM
-
-#define F_(x, y)
-#define FM(x)	x##_MARK,
-	PINMUX_MARK_BEGIN,
-	PINMUX_GPSR
-	PINMUX_IPSR
-	PINMUX_MOD_SELS
-	PINMUX_STATIC
-	PINMUX_PHYS
-	PINMUX_MARK_END,
-#undef F_
-#undef FM
-};
-
-static const u16 pinmux_data[] = {
-	PINMUX_DATA_GP_ALL(),
-
-	PINMUX_SINGLE(AVS1),
-	PINMUX_SINGLE(AVS2),
-	PINMUX_SINGLE(CLKOUT),
-	PINMUX_SINGLE(GP7_02),
-	PINMUX_SINGLE(GP7_03),
-	PINMUX_SINGLE(MSIOF0_RXD),
-	PINMUX_SINGLE(MSIOF0_SCK),
-	PINMUX_SINGLE(MSIOF0_TXD),
-	PINMUX_SINGLE(SSI_SCK5),
-	PINMUX_SINGLE(SSI_SDATA5),
-	PINMUX_SINGLE(SSI_WS5),
-
-	/* IPSR0 */
-	PINMUX_IPSR_GPSR(IP0_3_0,	AVB_MDC),
-	PINMUX_IPSR_MSEL(IP0_3_0,	MSIOF2_SS2_C,		SEL_MSIOF2_2),
-
-	PINMUX_IPSR_GPSR(IP0_7_4,	AVB_MAGIC),
-	PINMUX_IPSR_MSEL(IP0_7_4,	MSIOF2_SS1_C,		SEL_MSIOF2_2),
-	PINMUX_IPSR_MSEL(IP0_7_4,	SCK4_A,			SEL_SCIF4_0),
-
-	PINMUX_IPSR_GPSR(IP0_11_8,	AVB_PHY_INT),
-	PINMUX_IPSR_MSEL(IP0_11_8,	MSIOF2_SYNC_C,		SEL_MSIOF2_2),
-	PINMUX_IPSR_MSEL(IP0_11_8,	RX4_A,			SEL_SCIF4_0),
-
-	PINMUX_IPSR_GPSR(IP0_15_12,	AVB_LINK),
-	PINMUX_IPSR_MSEL(IP0_15_12,	MSIOF2_SCK_C,		SEL_MSIOF2_2),
-	PINMUX_IPSR_MSEL(IP0_15_12,	TX4_A,			SEL_SCIF4_0),
-
-	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,	I2C_SEL_5_0,	SEL_ETHERAVB_0),
-	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C,		I2C_SEL_5_0,	SEL_MSIOF2_2),
-	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A,		I2C_SEL_5_0,	SEL_SCIF4_0),
-	PINMUX_IPSR_MSEL(IP0_19_16,	FSCLKST2_N_A,		I2C_SEL_5_0),
-	PINMUX_IPSR_PHYS(IP0_19_16,     SCL5,                   I2C_SEL_5_1),
-
-	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A,	I2C_SEL_5_0,	SEL_ETHERAVB_0),
-	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C,		I2C_SEL_5_0,	SEL_MSIOF2_2),
-	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A,		I2C_SEL_5_0,	SEL_SCIF4_0),
-	PINMUX_IPSR_PHYS(IP0_23_20,     SDA5,                   I2C_SEL_5_1),
-
-	PINMUX_IPSR_GPSR(IP0_27_24,	IRQ0),
-	PINMUX_IPSR_GPSR(IP0_27_24,	QPOLB),
-	PINMUX_IPSR_GPSR(IP0_27_24,	DU_CDE),
-	PINMUX_IPSR_MSEL(IP0_27_24,	VI4_DATA0_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP0_27_24,	CAN0_TX_B,		SEL_RCAN0_1),
-	PINMUX_IPSR_MSEL(IP0_27_24,	CANFD0_TX_B,		SEL_CANFD0_1),
-	PINMUX_IPSR_MSEL(IP0_27_24,	MSIOF3_SS2_E,		SEL_MSIOF3_4),
-
-	PINMUX_IPSR_GPSR(IP0_31_28,	IRQ1),
-	PINMUX_IPSR_GPSR(IP0_31_28,	QPOLA),
-	PINMUX_IPSR_GPSR(IP0_31_28,	DU_DISP),
-	PINMUX_IPSR_MSEL(IP0_31_28,	VI4_DATA1_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP0_31_28,	CAN0_RX_B,		SEL_RCAN0_1),
-	PINMUX_IPSR_MSEL(IP0_31_28,	CANFD0_RX_B,		SEL_CANFD0_1),
-	PINMUX_IPSR_MSEL(IP0_31_28,	MSIOF3_SS1_E,		SEL_MSIOF3_4),
-
-	/* IPSR1 */
-	PINMUX_IPSR_GPSR(IP1_3_0,	IRQ2),
-	PINMUX_IPSR_GPSR(IP1_3_0,	QCPV_QDE),
-	PINMUX_IPSR_GPSR(IP1_3_0,	DU_EXODDF_DU_ODDF_DISP_CDE),
-	PINMUX_IPSR_MSEL(IP1_3_0,	VI4_DATA2_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP1_3_0,	PWM3_B,			SEL_PWM3_1),
-	PINMUX_IPSR_MSEL(IP1_3_0,	MSIOF3_SYNC_E,		SEL_MSIOF3_4),
-
-	PINMUX_IPSR_GPSR(IP1_7_4,	IRQ3),
-	PINMUX_IPSR_GPSR(IP1_7_4,	QSTVB_QVE),
-	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DOTCLKOUT1),
-	PINMUX_IPSR_MSEL(IP1_7_4,	VI4_DATA3_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP1_7_4,	PWM4_B,			SEL_PWM4_1),
-	PINMUX_IPSR_MSEL(IP1_7_4,	MSIOF3_SCK_E,		SEL_MSIOF3_4),
-
-	PINMUX_IPSR_GPSR(IP1_11_8,	IRQ4),
-	PINMUX_IPSR_GPSR(IP1_11_8,	QSTH_QHS),
-	PINMUX_IPSR_GPSR(IP1_11_8,	DU_EXHSYNC_DU_HSYNC),
-	PINMUX_IPSR_MSEL(IP1_11_8,	VI4_DATA4_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP1_11_8,	PWM5_B,			SEL_PWM5_1),
-	PINMUX_IPSR_MSEL(IP1_11_8,	MSIOF3_RXD_E,		SEL_MSIOF3_4),
-
-	PINMUX_IPSR_GPSR(IP1_15_12,	IRQ5),
-	PINMUX_IPSR_GPSR(IP1_15_12,	QSTB_QHE),
-	PINMUX_IPSR_GPSR(IP1_15_12,	DU_EXVSYNC_DU_VSYNC),
-	PINMUX_IPSR_MSEL(IP1_15_12,	VI4_DATA5_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP1_15_12,	PWM6_B,			SEL_PWM6_1),
-	PINMUX_IPSR_GPSR(IP1_15_12,	FSCLKST2_N_B),
-	PINMUX_IPSR_MSEL(IP1_15_12,	MSIOF3_TXD_E,		SEL_MSIOF3_4),
-
-	PINMUX_IPSR_GPSR(IP1_19_16,	PWM0),
-	PINMUX_IPSR_GPSR(IP1_19_16,	AVB_AVTP_PPS),
-	PINMUX_IPSR_MSEL(IP1_19_16,	VI4_DATA6_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP1_19_16,	IECLK_B,		SEL_IEBUS_1),
-
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A,		I2C_SEL_3_0,	SEL_PWM1_0),
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B,		I2C_SEL_3_0,	SEL_VIN4_1),
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
-	PINMUX_IPSR_PHYS(IP1_23_20,	SCL3,			I2C_SEL_3_1),
-
-	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A,		I2C_SEL_3_0,	SEL_PWM2_0),
-	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
-	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
-	PINMUX_IPSR_PHYS(IP1_27_24,	SDA3,			I2C_SEL_3_1),
-
-	PINMUX_IPSR_GPSR(IP1_31_28,	A0),
-	PINMUX_IPSR_GPSR(IP1_31_28,	LCDOUT16),
-	PINMUX_IPSR_MSEL(IP1_31_28,	MSIOF3_SYNC_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP1_31_28,	VI4_DATA8),
-	PINMUX_IPSR_GPSR(IP1_31_28,	DU_DB0),
-	PINMUX_IPSR_MSEL(IP1_31_28,	PWM3_A,			SEL_PWM3_0),
-
-	/* IPSR2 */
-	PINMUX_IPSR_GPSR(IP2_3_0,	A1),
-	PINMUX_IPSR_GPSR(IP2_3_0,	LCDOUT17),
-	PINMUX_IPSR_MSEL(IP2_3_0,	MSIOF3_TXD_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP2_3_0,	VI4_DATA9),
-	PINMUX_IPSR_GPSR(IP2_3_0,	DU_DB1),
-	PINMUX_IPSR_MSEL(IP2_3_0,	PWM4_A,			SEL_PWM4_0),
-
-	PINMUX_IPSR_GPSR(IP2_7_4,	A2),
-	PINMUX_IPSR_GPSR(IP2_7_4,	LCDOUT18),
-	PINMUX_IPSR_MSEL(IP2_7_4,	MSIOF3_SCK_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP2_7_4,	VI4_DATA10),
-	PINMUX_IPSR_GPSR(IP2_7_4,	DU_DB2),
-	PINMUX_IPSR_MSEL(IP2_7_4,	PWM5_A,			SEL_PWM5_0),
-
-	PINMUX_IPSR_GPSR(IP2_11_8,	A3),
-	PINMUX_IPSR_GPSR(IP2_11_8,	LCDOUT19),
-	PINMUX_IPSR_MSEL(IP2_11_8,	MSIOF3_RXD_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP2_11_8,	VI4_DATA11),
-	PINMUX_IPSR_GPSR(IP2_11_8,	DU_DB3),
-	PINMUX_IPSR_MSEL(IP2_11_8,	PWM6_A,			SEL_PWM6_0),
-
-	PINMUX_IPSR_GPSR(IP2_15_12,	A4),
-	PINMUX_IPSR_GPSR(IP2_15_12,	LCDOUT20),
-	PINMUX_IPSR_MSEL(IP2_15_12,	MSIOF3_SS1_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP2_15_12,	VI4_DATA12),
-	PINMUX_IPSR_GPSR(IP2_15_12,	VI5_DATA12),
-	PINMUX_IPSR_GPSR(IP2_15_12,	DU_DB4),
-
-	PINMUX_IPSR_GPSR(IP2_19_16,	A5),
-	PINMUX_IPSR_GPSR(IP2_19_16,	LCDOUT21),
-	PINMUX_IPSR_MSEL(IP2_19_16,	MSIOF3_SS2_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_MSEL(IP2_19_16,	SCK4_B,			SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP2_19_16,	VI4_DATA13),
-	PINMUX_IPSR_GPSR(IP2_19_16,	VI5_DATA13),
-	PINMUX_IPSR_GPSR(IP2_19_16,	DU_DB5),
-
-	PINMUX_IPSR_GPSR(IP2_23_20,	A6),
-	PINMUX_IPSR_GPSR(IP2_23_20,	LCDOUT22),
-	PINMUX_IPSR_MSEL(IP2_23_20,	MSIOF2_SS1_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP2_23_20,	RX4_B,			SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP2_23_20,	VI4_DATA14),
-	PINMUX_IPSR_GPSR(IP2_23_20,	VI5_DATA14),
-	PINMUX_IPSR_GPSR(IP2_23_20,	DU_DB6),
-
-	PINMUX_IPSR_GPSR(IP2_27_24,	A7),
-	PINMUX_IPSR_GPSR(IP2_27_24,	LCDOUT23),
-	PINMUX_IPSR_MSEL(IP2_27_24,	MSIOF2_SS2_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP2_27_24,	TX4_B,			SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP2_27_24,	VI4_DATA15),
-	PINMUX_IPSR_GPSR(IP2_27_24,	VI5_DATA15),
-	PINMUX_IPSR_GPSR(IP2_27_24,	DU_DB7),
-
-	PINMUX_IPSR_GPSR(IP2_31_28,	A8),
-	PINMUX_IPSR_MSEL(IP2_31_28,	RX3_B,			SEL_SCIF3_1),
-	PINMUX_IPSR_MSEL(IP2_31_28,	MSIOF2_SYNC_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP2_31_28,	HRX4_B,			SEL_HSCIF4_1),
-	PINMUX_IPSR_MSEL(IP2_31_28,	SDA6_A,			SEL_I2C6_0),
-	PINMUX_IPSR_MSEL(IP2_31_28,	AVB_AVTP_MATCH_B,	SEL_ETHERAVB_1),
-	PINMUX_IPSR_MSEL(IP2_31_28,	PWM1_B,			SEL_PWM1_1),
-
-	/* IPSR3 */
-	PINMUX_IPSR_GPSR(IP3_3_0,	A9),
-	PINMUX_IPSR_MSEL(IP3_3_0,	MSIOF2_SCK_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP3_3_0,	CTS4_N_B,		SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP3_3_0,	VI5_VSYNC_N),
-
-	PINMUX_IPSR_GPSR(IP3_7_4,	A10),
-	PINMUX_IPSR_MSEL(IP3_7_4,	MSIOF2_RXD_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP3_7_4,	RTS4_N_B,		SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP3_7_4,	VI5_HSYNC_N),
-
-	PINMUX_IPSR_GPSR(IP3_11_8,	A11),
-	PINMUX_IPSR_MSEL(IP3_11_8,	TX3_B,			SEL_SCIF3_1),
-	PINMUX_IPSR_MSEL(IP3_11_8,	MSIOF2_TXD_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP3_11_8,	HTX4_B,			SEL_HSCIF4_1),
-	PINMUX_IPSR_GPSR(IP3_11_8,	HSCK4),
-	PINMUX_IPSR_GPSR(IP3_11_8,	VI5_FIELD),
-	PINMUX_IPSR_MSEL(IP3_11_8,	SCL6_A,			SEL_I2C6_0),
-	PINMUX_IPSR_MSEL(IP3_11_8,	AVB_AVTP_CAPTURE_B,	SEL_ETHERAVB_1),
-	PINMUX_IPSR_MSEL(IP3_11_8,	PWM2_B,			SEL_PWM2_1),
-
-	PINMUX_IPSR_GPSR(IP3_15_12,	A12),
-	PINMUX_IPSR_GPSR(IP3_15_12,	LCDOUT12),
-	PINMUX_IPSR_MSEL(IP3_15_12,	MSIOF3_SCK_C,		SEL_MSIOF3_2),
-	PINMUX_IPSR_MSEL(IP3_15_12,	HRX4_A,			SEL_HSCIF4_0),
-	PINMUX_IPSR_GPSR(IP3_15_12,	VI5_DATA8),
-	PINMUX_IPSR_GPSR(IP3_15_12,	DU_DG4),
-
-	PINMUX_IPSR_GPSR(IP3_19_16,	A13),
-	PINMUX_IPSR_GPSR(IP3_19_16,	LCDOUT13),
-	PINMUX_IPSR_MSEL(IP3_19_16,	MSIOF3_SYNC_C,		SEL_MSIOF3_2),
-	PINMUX_IPSR_MSEL(IP3_19_16,	HTX4_A,			SEL_HSCIF4_0),
-	PINMUX_IPSR_GPSR(IP3_19_16,	VI5_DATA9),
-	PINMUX_IPSR_GPSR(IP3_19_16,	DU_DG5),
-
-	PINMUX_IPSR_GPSR(IP3_23_20,	A14),
-	PINMUX_IPSR_GPSR(IP3_23_20,	LCDOUT14),
-	PINMUX_IPSR_MSEL(IP3_23_20,	MSIOF3_RXD_C,		SEL_MSIOF3_2),
-	PINMUX_IPSR_GPSR(IP3_23_20,	HCTS4_N),
-	PINMUX_IPSR_GPSR(IP3_23_20,	VI5_DATA10),
-	PINMUX_IPSR_GPSR(IP3_23_20,	DU_DG6),
-
-	PINMUX_IPSR_GPSR(IP3_27_24,	A15),
-	PINMUX_IPSR_GPSR(IP3_27_24,	LCDOUT15),
-	PINMUX_IPSR_MSEL(IP3_27_24,	MSIOF3_TXD_C,		SEL_MSIOF3_2),
-	PINMUX_IPSR_GPSR(IP3_27_24,	HRTS4_N),
-	PINMUX_IPSR_GPSR(IP3_27_24,	VI5_DATA11),
-	PINMUX_IPSR_GPSR(IP3_27_24,	DU_DG7),
-
-	PINMUX_IPSR_GPSR(IP3_31_28,	A16),
-	PINMUX_IPSR_GPSR(IP3_31_28,	LCDOUT8),
-	PINMUX_IPSR_GPSR(IP3_31_28,	VI4_FIELD),
-	PINMUX_IPSR_GPSR(IP3_31_28,	DU_DG0),
-
-	/* IPSR4 */
-	PINMUX_IPSR_GPSR(IP4_3_0,	A17),
-	PINMUX_IPSR_GPSR(IP4_3_0,	LCDOUT9),
-	PINMUX_IPSR_GPSR(IP4_3_0,	VI4_VSYNC_N),
-	PINMUX_IPSR_GPSR(IP4_3_0,	DU_DG1),
-
-	PINMUX_IPSR_GPSR(IP4_7_4,	A18),
-	PINMUX_IPSR_GPSR(IP4_7_4,	LCDOUT10),
-	PINMUX_IPSR_GPSR(IP4_7_4,	VI4_HSYNC_N),
-	PINMUX_IPSR_GPSR(IP4_7_4,	DU_DG2),
-
-	PINMUX_IPSR_GPSR(IP4_11_8,	A19),
-	PINMUX_IPSR_GPSR(IP4_11_8,	LCDOUT11),
-	PINMUX_IPSR_GPSR(IP4_11_8,	VI4_CLKENB),
-	PINMUX_IPSR_GPSR(IP4_11_8,	DU_DG3),
-
-	PINMUX_IPSR_GPSR(IP4_15_12,	CS0_N),
-	PINMUX_IPSR_GPSR(IP4_15_12,	VI5_CLKENB),
-
-	PINMUX_IPSR_GPSR(IP4_19_16,	CS1_N),
-	PINMUX_IPSR_GPSR(IP4_19_16,	VI5_CLK),
-	PINMUX_IPSR_MSEL(IP4_19_16,	EX_WAIT0_B,		SEL_LBSC_1),
-
-	PINMUX_IPSR_GPSR(IP4_23_20,	BS_N),
-	PINMUX_IPSR_GPSR(IP4_23_20,	QSTVA_QVS),
-	PINMUX_IPSR_MSEL(IP4_23_20,	MSIOF3_SCK_D,		SEL_MSIOF3_3),
-	PINMUX_IPSR_GPSR(IP4_23_20,	SCK3),
-	PINMUX_IPSR_GPSR(IP4_23_20,	HSCK3),
-	PINMUX_IPSR_GPSR(IP4_23_20,	CAN1_TX),
-	PINMUX_IPSR_GPSR(IP4_23_20,	CANFD1_TX),
-	PINMUX_IPSR_MSEL(IP4_23_20,	IETX_A,			SEL_IEBUS_0),
-
-	PINMUX_IPSR_GPSR(IP4_27_24,	RD_N),
-	PINMUX_IPSR_MSEL(IP4_27_24,	MSIOF3_SYNC_D,		SEL_MSIOF3_3),
-	PINMUX_IPSR_MSEL(IP4_27_24,	RX3_A,			SEL_SCIF3_0),
-	PINMUX_IPSR_MSEL(IP4_27_24,	HRX3_A,			SEL_HSCIF3_0),
-	PINMUX_IPSR_MSEL(IP4_27_24,	CAN0_TX_A,		SEL_RCAN0_0),
-	PINMUX_IPSR_MSEL(IP4_27_24,	CANFD0_TX_A,		SEL_CANFD0_0),
-
-	PINMUX_IPSR_GPSR(IP4_31_28,	RD_WR_N),
-	PINMUX_IPSR_MSEL(IP4_31_28,	MSIOF3_RXD_D,		SEL_MSIOF3_3),
-	PINMUX_IPSR_MSEL(IP4_31_28,	TX3_A,			SEL_SCIF3_0),
-	PINMUX_IPSR_MSEL(IP4_31_28,	HTX3_A,			SEL_HSCIF3_0),
-	PINMUX_IPSR_MSEL(IP4_31_28,	CAN0_RX_A,		SEL_RCAN0_0),
-	PINMUX_IPSR_MSEL(IP4_31_28,	CANFD0_RX_A,		SEL_CANFD0_0),
-
-	/* IPSR5 */
-	PINMUX_IPSR_GPSR(IP5_3_0,	WE0_N),
-	PINMUX_IPSR_MSEL(IP5_3_0,	MSIOF3_TXD_D,		SEL_MSIOF3_3),
-	PINMUX_IPSR_GPSR(IP5_3_0,	CTS3_N),
-	PINMUX_IPSR_GPSR(IP5_3_0,	HCTS3_N),
-	PINMUX_IPSR_MSEL(IP5_3_0,	SCL6_B,			SEL_I2C6_1),
-	PINMUX_IPSR_GPSR(IP5_3_0,	CAN_CLK),
-	PINMUX_IPSR_MSEL(IP5_3_0,	IECLK_A,		SEL_IEBUS_0),
-
-	PINMUX_IPSR_GPSR(IP5_7_4,	WE1_N),
-	PINMUX_IPSR_MSEL(IP5_7_4,	MSIOF3_SS1_D,		SEL_MSIOF3_3),
-	PINMUX_IPSR_GPSR(IP5_7_4,	RTS3_N),
-	PINMUX_IPSR_GPSR(IP5_7_4,	HRTS3_N),
-	PINMUX_IPSR_MSEL(IP5_7_4,	SDA6_B,			SEL_I2C6_1),
-	PINMUX_IPSR_GPSR(IP5_7_4,	CAN1_RX),
-	PINMUX_IPSR_GPSR(IP5_7_4,	CANFD1_RX),
-	PINMUX_IPSR_MSEL(IP5_7_4,	IERX_A,			SEL_IEBUS_0),
-
-	PINMUX_IPSR_MSEL(IP5_11_8,	EX_WAIT0_A,		SEL_LBSC_0),
-	PINMUX_IPSR_GPSR(IP5_11_8,	QCLK),
-	PINMUX_IPSR_GPSR(IP5_11_8,	VI4_CLK),
-	PINMUX_IPSR_GPSR(IP5_11_8,	DU_DOTCLKOUT0),
-
-	PINMUX_IPSR_GPSR(IP5_15_12,	D0),
-	PINMUX_IPSR_MSEL(IP5_15_12,	MSIOF2_SS1_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_MSEL(IP5_15_12,	MSIOF3_SCK_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_GPSR(IP5_15_12,	VI4_DATA16),
-	PINMUX_IPSR_GPSR(IP5_15_12,	VI5_DATA0),
-
-	PINMUX_IPSR_GPSR(IP5_19_16,	D1),
-	PINMUX_IPSR_MSEL(IP5_19_16,	MSIOF2_SS2_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_MSEL(IP5_19_16,	MSIOF3_SYNC_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_GPSR(IP5_19_16,	VI4_DATA17),
-	PINMUX_IPSR_GPSR(IP5_19_16,	VI5_DATA1),
-
-	PINMUX_IPSR_GPSR(IP5_23_20,	D2),
-	PINMUX_IPSR_MSEL(IP5_23_20,	MSIOF3_RXD_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_GPSR(IP5_23_20,	VI4_DATA18),
-	PINMUX_IPSR_GPSR(IP5_23_20,	VI5_DATA2),
-
-	PINMUX_IPSR_GPSR(IP5_27_24,	D3),
-	PINMUX_IPSR_MSEL(IP5_27_24,	MSIOF3_TXD_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_GPSR(IP5_27_24,	VI4_DATA19),
-	PINMUX_IPSR_GPSR(IP5_27_24,	VI5_DATA3),
-
-	PINMUX_IPSR_GPSR(IP5_31_28,	D4),
-	PINMUX_IPSR_MSEL(IP5_31_28,	MSIOF2_SCK_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP5_31_28,	VI4_DATA20),
-	PINMUX_IPSR_GPSR(IP5_31_28,	VI5_DATA4),
-
-	/* IPSR6 */
-	PINMUX_IPSR_GPSR(IP6_3_0,	D5),
-	PINMUX_IPSR_MSEL(IP6_3_0,	MSIOF2_SYNC_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP6_3_0,	VI4_DATA21),
-	PINMUX_IPSR_GPSR(IP6_3_0,	VI5_DATA5),
-
-	PINMUX_IPSR_GPSR(IP6_7_4,	D6),
-	PINMUX_IPSR_MSEL(IP6_7_4,	MSIOF2_RXD_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP6_7_4,	VI4_DATA22),
-	PINMUX_IPSR_GPSR(IP6_7_4,	VI5_DATA6),
-
-	PINMUX_IPSR_GPSR(IP6_11_8,	D7),
-	PINMUX_IPSR_MSEL(IP6_11_8,	MSIOF2_TXD_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP6_11_8,	VI4_DATA23),
-	PINMUX_IPSR_GPSR(IP6_11_8,	VI5_DATA7),
-
-	PINMUX_IPSR_GPSR(IP6_15_12,	D8),
-	PINMUX_IPSR_GPSR(IP6_15_12,	LCDOUT0),
-	PINMUX_IPSR_MSEL(IP6_15_12,	MSIOF2_SCK_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP6_15_12,	SCK4_C,			SEL_SCIF4_2),
-	PINMUX_IPSR_MSEL(IP6_15_12,	VI4_DATA0_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP6_15_12,	DU_DR0),
-
-	PINMUX_IPSR_GPSR(IP6_19_16,	D9),
-	PINMUX_IPSR_GPSR(IP6_19_16,	LCDOUT1),
-	PINMUX_IPSR_MSEL(IP6_19_16,	MSIOF2_SYNC_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP6_19_16,	VI4_DATA1_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP6_19_16,	DU_DR1),
-
-	PINMUX_IPSR_GPSR(IP6_23_20,	D10),
-	PINMUX_IPSR_GPSR(IP6_23_20,	LCDOUT2),
-	PINMUX_IPSR_MSEL(IP6_23_20,	MSIOF2_RXD_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP6_23_20,	HRX3_B,			SEL_HSCIF3_1),
-	PINMUX_IPSR_MSEL(IP6_23_20,	VI4_DATA2_A,		SEL_VIN4_0),
-	PINMUX_IPSR_MSEL(IP6_23_20,	CTS4_N_C,		SEL_SCIF4_2),
-	PINMUX_IPSR_GPSR(IP6_23_20,	DU_DR2),
-
-	PINMUX_IPSR_GPSR(IP6_27_24,	D11),
-	PINMUX_IPSR_GPSR(IP6_27_24,	LCDOUT3),
-	PINMUX_IPSR_MSEL(IP6_27_24,	MSIOF2_TXD_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP6_27_24,	HTX3_B,			SEL_HSCIF3_1),
-	PINMUX_IPSR_MSEL(IP6_27_24,	VI4_DATA3_A,		SEL_VIN4_0),
-	PINMUX_IPSR_MSEL(IP6_27_24,	RTS4_N_C,		SEL_SCIF4_2),
-	PINMUX_IPSR_GPSR(IP6_27_24,	DU_DR3),
-
-	PINMUX_IPSR_GPSR(IP6_31_28,	D12),
-	PINMUX_IPSR_GPSR(IP6_31_28,	LCDOUT4),
-	PINMUX_IPSR_MSEL(IP6_31_28,	MSIOF2_SS1_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP6_31_28,	RX4_C,			SEL_SCIF4_2),
-	PINMUX_IPSR_MSEL(IP6_31_28,	VI4_DATA4_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP6_31_28,	DU_DR4),
-
-	/* IPSR7 */
-	PINMUX_IPSR_GPSR(IP7_3_0,	D13),
-	PINMUX_IPSR_GPSR(IP7_3_0,	LCDOUT5),
-	PINMUX_IPSR_MSEL(IP7_3_0,	MSIOF2_SS2_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP7_3_0,	TX4_C,			SEL_SCIF4_2),
-	PINMUX_IPSR_MSEL(IP7_3_0,	VI4_DATA5_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP7_3_0,	DU_DR5),
-
-	PINMUX_IPSR_GPSR(IP7_7_4,	D14),
-	PINMUX_IPSR_GPSR(IP7_7_4,	LCDOUT6),
-	PINMUX_IPSR_MSEL(IP7_7_4,	MSIOF3_SS1_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_MSEL(IP7_7_4,	HRX3_C,			SEL_HSCIF3_2),
-	PINMUX_IPSR_MSEL(IP7_7_4,	VI4_DATA6_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP7_7_4,	DU_DR6),
-	PINMUX_IPSR_MSEL(IP7_7_4,	SCL6_C,			SEL_I2C6_2),
-
-	PINMUX_IPSR_GPSR(IP7_11_8,	D15),
-	PINMUX_IPSR_GPSR(IP7_11_8,	LCDOUT7),
-	PINMUX_IPSR_MSEL(IP7_11_8,	MSIOF3_SS2_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_MSEL(IP7_11_8,	HTX3_C,			SEL_HSCIF3_2),
-	PINMUX_IPSR_MSEL(IP7_11_8,	VI4_DATA7_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP7_11_8,	DU_DR7),
-	PINMUX_IPSR_MSEL(IP7_11_8,	SDA6_C,			SEL_I2C6_2),
-
-	PINMUX_IPSR_GPSR(IP7_19_16,	SD0_CLK),
-	PINMUX_IPSR_MSEL(IP7_19_16,	MSIOF1_SCK_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP7_19_16,	STP_OPWM_0_B,		SEL_SSP1_0_1),
-
-	PINMUX_IPSR_GPSR(IP7_23_20,	SD0_CMD),
-	PINMUX_IPSR_MSEL(IP7_23_20,	MSIOF1_SYNC_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP7_23_20,	STP_IVCXO27_0_B,	SEL_SSP1_0_1),
-
-	PINMUX_IPSR_GPSR(IP7_27_24,	SD0_DAT0),
-	PINMUX_IPSR_MSEL(IP7_27_24,	MSIOF1_RXD_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP7_27_24,	TS_SCK0_B,		SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP7_27_24,	STP_ISCLK_0_B,		SEL_SSP1_0_1),
-
-	PINMUX_IPSR_GPSR(IP7_31_28,	SD0_DAT1),
-	PINMUX_IPSR_MSEL(IP7_31_28,	MSIOF1_TXD_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP7_31_28,	TS_SPSYNC0_B,		SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP7_31_28,	STP_ISSYNC_0_B,		SEL_SSP1_0_1),
-
-	/* IPSR8 */
-	PINMUX_IPSR_GPSR(IP8_3_0,	SD0_DAT2),
-	PINMUX_IPSR_MSEL(IP8_3_0,	MSIOF1_SS1_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP8_3_0,	TS_SDAT0_B,		SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP8_3_0,	STP_ISD_0_B,		SEL_SSP1_0_1),
-
-	PINMUX_IPSR_GPSR(IP8_7_4,	SD0_DAT3),
-	PINMUX_IPSR_MSEL(IP8_7_4,	MSIOF1_SS2_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP8_7_4,	TS_SDEN0_B,		SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP8_7_4,	STP_ISEN_0_B,		SEL_SSP1_0_1),
-
-	PINMUX_IPSR_GPSR(IP8_11_8,	SD1_CLK),
-	PINMUX_IPSR_MSEL(IP8_11_8,	MSIOF1_SCK_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_MSEL(IP8_11_8,	SIM0_CLK_A,		SEL_SIMCARD_0),
-
-	PINMUX_IPSR_GPSR(IP8_15_12,	SD1_CMD),
-	PINMUX_IPSR_MSEL(IP8_15_12,	MSIOF1_SYNC_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_GPSR(IP8_15_12,	NFCE_N_B),
-	PINMUX_IPSR_MSEL(IP8_15_12,	SIM0_D_A,		SEL_SIMCARD_0),
-	PINMUX_IPSR_MSEL(IP8_15_12,	STP_IVCXO27_1_B,	SEL_SSP1_1_1),
-
-	PINMUX_IPSR_GPSR(IP8_19_16,	SD1_DAT0),
-	PINMUX_IPSR_GPSR(IP8_19_16,	SD2_DAT4),
-	PINMUX_IPSR_MSEL(IP8_19_16,	MSIOF1_RXD_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_GPSR(IP8_19_16,	NFWP_N_B),
-	PINMUX_IPSR_MSEL(IP8_19_16,	TS_SCK1_B,		SEL_TSIF1_1),
-	PINMUX_IPSR_MSEL(IP8_19_16,	STP_ISCLK_1_B,		SEL_SSP1_1_1),
-
-	PINMUX_IPSR_GPSR(IP8_23_20,	SD1_DAT1),
-	PINMUX_IPSR_GPSR(IP8_23_20,	SD2_DAT5),
-	PINMUX_IPSR_MSEL(IP8_23_20,	MSIOF1_TXD_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_GPSR(IP8_23_20,	NFDATA14_B),
-	PINMUX_IPSR_MSEL(IP8_23_20,	TS_SPSYNC1_B,		SEL_TSIF1_1),
-	PINMUX_IPSR_MSEL(IP8_23_20,	STP_ISSYNC_1_B,		SEL_SSP1_1_1),
-
-	PINMUX_IPSR_GPSR(IP8_27_24,	SD1_DAT2),
-	PINMUX_IPSR_GPSR(IP8_27_24,	SD2_DAT6),
-	PINMUX_IPSR_MSEL(IP8_27_24,	MSIOF1_SS1_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_GPSR(IP8_27_24,	NFDATA15_B),
-	PINMUX_IPSR_MSEL(IP8_27_24,	TS_SDAT1_B,		SEL_TSIF1_1),
-	PINMUX_IPSR_MSEL(IP8_27_24,	STP_ISD_1_B,		SEL_SSP1_1_1),
-
-	PINMUX_IPSR_GPSR(IP8_31_28,	SD1_DAT3),
-	PINMUX_IPSR_GPSR(IP8_31_28,	SD2_DAT7),
-	PINMUX_IPSR_MSEL(IP8_31_28,	MSIOF1_SS2_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_GPSR(IP8_31_28,	NFRB_N_B),
-	PINMUX_IPSR_MSEL(IP8_31_28,	TS_SDEN1_B,		SEL_TSIF1_1),
-	PINMUX_IPSR_MSEL(IP8_31_28,	STP_ISEN_1_B,		SEL_SSP1_1_1),
-
-	/* IPSR9 */
-	PINMUX_IPSR_GPSR(IP9_3_0,	SD2_CLK),
-	PINMUX_IPSR_GPSR(IP9_3_0,	NFDATA8),
-
-	PINMUX_IPSR_GPSR(IP9_7_4,	SD2_CMD),
-	PINMUX_IPSR_GPSR(IP9_7_4,	NFDATA9),
-
-	PINMUX_IPSR_GPSR(IP9_11_8,	SD2_DAT0),
-	PINMUX_IPSR_GPSR(IP9_11_8,	NFDATA10),
-
-	PINMUX_IPSR_GPSR(IP9_15_12,	SD2_DAT1),
-	PINMUX_IPSR_GPSR(IP9_15_12,	NFDATA11),
-
-	PINMUX_IPSR_GPSR(IP9_19_16,	SD2_DAT2),
-	PINMUX_IPSR_GPSR(IP9_19_16,	NFDATA12),
-
-	PINMUX_IPSR_GPSR(IP9_23_20,	SD2_DAT3),
-	PINMUX_IPSR_GPSR(IP9_23_20,	NFDATA13),
-
-	PINMUX_IPSR_GPSR(IP9_27_24,	SD2_DS),
-	PINMUX_IPSR_GPSR(IP9_27_24,	NFALE),
-	PINMUX_IPSR_GPSR(IP9_27_24,	SATA_DEVSLP_B),
-
-	PINMUX_IPSR_GPSR(IP9_31_28,	SD3_CLK),
-	PINMUX_IPSR_GPSR(IP9_31_28,	NFWE_N),
-
-	/* IPSR10 */
-	PINMUX_IPSR_GPSR(IP10_3_0,	SD3_CMD),
-	PINMUX_IPSR_GPSR(IP10_3_0,	NFRE_N),
-
-	PINMUX_IPSR_GPSR(IP10_7_4,	SD3_DAT0),
-	PINMUX_IPSR_GPSR(IP10_7_4,	NFDATA0),
-
-	PINMUX_IPSR_GPSR(IP10_11_8,	SD3_DAT1),
-	PINMUX_IPSR_GPSR(IP10_11_8,	NFDATA1),
-
-	PINMUX_IPSR_GPSR(IP10_15_12,	SD3_DAT2),
-	PINMUX_IPSR_GPSR(IP10_15_12,	NFDATA2),
-
-	PINMUX_IPSR_GPSR(IP10_19_16,	SD3_DAT3),
-	PINMUX_IPSR_GPSR(IP10_19_16,	NFDATA3),
-
-	PINMUX_IPSR_GPSR(IP10_23_20,	SD3_DAT4),
-	PINMUX_IPSR_MSEL(IP10_23_20,	SD2_CD_A,		SEL_SDHI2_0),
-	PINMUX_IPSR_GPSR(IP10_23_20,	NFDATA4),
-
-	PINMUX_IPSR_GPSR(IP10_27_24,	SD3_DAT5),
-	PINMUX_IPSR_MSEL(IP10_27_24,	SD2_WP_A,		SEL_SDHI2_0),
-	PINMUX_IPSR_GPSR(IP10_27_24,	NFDATA5),
-
-	PINMUX_IPSR_GPSR(IP10_31_28,	SD3_DAT6),
-	PINMUX_IPSR_GPSR(IP10_31_28,	SD3_CD),
-	PINMUX_IPSR_GPSR(IP10_31_28,	NFDATA6),
-
-	/* IPSR11 */
-	PINMUX_IPSR_GPSR(IP11_3_0,	SD3_DAT7),
-	PINMUX_IPSR_GPSR(IP11_3_0,	SD3_WP),
-	PINMUX_IPSR_GPSR(IP11_3_0,	NFDATA7),
-
-	PINMUX_IPSR_GPSR(IP11_7_4,	SD3_DS),
-	PINMUX_IPSR_GPSR(IP11_7_4,	NFCLE),
-
-	PINMUX_IPSR_GPSR(IP11_11_8,	SD0_CD),
-	PINMUX_IPSR_MSEL(IP11_11_8,	SCL2_B,			SEL_I2C2_1),
-	PINMUX_IPSR_MSEL(IP11_11_8,	SIM0_RST_A,		SEL_SIMCARD_0),
-
-	PINMUX_IPSR_GPSR(IP11_15_12,	SD0_WP),
-	PINMUX_IPSR_MSEL(IP11_15_12,	SDA2_B,			SEL_I2C2_1),
-
-	PINMUX_IPSR_MSEL(IP11_19_16,	SD1_CD,			I2C_SEL_0_0),
-	PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B,		I2C_SEL_0_0,	SEL_SIMCARD_1),
-	PINMUX_IPSR_PHYS(IP11_19_16,	SCL0,			I2C_SEL_0_1),
-
-	PINMUX_IPSR_MSEL(IP11_23_20,	SD1_WP,			I2C_SEL_0_0),
-	PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B,		I2C_SEL_0_0,	SEL_SIMCARD_1),
-	PINMUX_IPSR_PHYS(IP11_23_20,	SDA0,			I2C_SEL_0_1),
-
-	PINMUX_IPSR_GPSR(IP11_27_24,	SCK0),
-	PINMUX_IPSR_MSEL(IP11_27_24,	HSCK1_B,		SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP11_27_24,	MSIOF1_SS2_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP11_27_24,	AUDIO_CLKC_B,		SEL_ADGC_1),
-	PINMUX_IPSR_MSEL(IP11_27_24,	SDA2_A,			SEL_I2C2_0),
-	PINMUX_IPSR_MSEL(IP11_27_24,	SIM0_RST_B,		SEL_SIMCARD_1),
-	PINMUX_IPSR_MSEL(IP11_27_24,	STP_OPWM_0_C,		SEL_SSP1_0_2),
-	PINMUX_IPSR_MSEL(IP11_27_24,	RIF0_CLK_B,		SEL_DRIF0_1),
-	PINMUX_IPSR_GPSR(IP11_27_24,	ADICHS2),
-	PINMUX_IPSR_MSEL(IP11_27_24,	SCK5_B,			SEL_SCIF5_1),
-
-	PINMUX_IPSR_GPSR(IP11_31_28,	RX0),
-	PINMUX_IPSR_MSEL(IP11_31_28,	HRX1_B,			SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP11_31_28,	TS_SCK0_C,		SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP11_31_28,	STP_ISCLK_0_C,		SEL_SSP1_0_2),
-	PINMUX_IPSR_MSEL(IP11_31_28,	RIF0_D0_B,		SEL_DRIF0_1),
-
-	/* IPSR12 */
-	PINMUX_IPSR_GPSR(IP12_3_0,	TX0),
-	PINMUX_IPSR_MSEL(IP12_3_0,	HTX1_B,			SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP12_3_0,	TS_SPSYNC0_C,		SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP12_3_0,	STP_ISSYNC_0_C,		SEL_SSP1_0_2),
-	PINMUX_IPSR_MSEL(IP12_3_0,	RIF0_D1_B,		SEL_DRIF0_1),
-
-	PINMUX_IPSR_GPSR(IP12_7_4,	CTS0_N),
-	PINMUX_IPSR_MSEL(IP12_7_4,	HCTS1_N_B,		SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP12_7_4,	MSIOF1_SYNC_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP12_7_4,	TS_SPSYNC1_C,		SEL_TSIF1_2),
-	PINMUX_IPSR_MSEL(IP12_7_4,	STP_ISSYNC_1_C,		SEL_SSP1_1_2),
-	PINMUX_IPSR_MSEL(IP12_7_4,	RIF1_SYNC_B,		SEL_DRIF1_1),
-	PINMUX_IPSR_GPSR(IP12_7_4,	AUDIO_CLKOUT_C),
-	PINMUX_IPSR_GPSR(IP12_7_4,	ADICS_SAMP),
-
-	PINMUX_IPSR_GPSR(IP12_11_8,	RTS0_N),
-	PINMUX_IPSR_MSEL(IP12_11_8,	HRTS1_N_B,		SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP12_11_8,	MSIOF1_SS1_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP12_11_8,	AUDIO_CLKA_B,		SEL_ADGA_1),
-	PINMUX_IPSR_MSEL(IP12_11_8,	SCL2_A,			SEL_I2C2_0),
-	PINMUX_IPSR_MSEL(IP12_11_8,	STP_IVCXO27_1_C,	SEL_SSP1_1_2),
-	PINMUX_IPSR_MSEL(IP12_11_8,	RIF0_SYNC_B,		SEL_DRIF0_1),
-	PINMUX_IPSR_GPSR(IP12_11_8,	ADICHS1),
-
-	PINMUX_IPSR_MSEL(IP12_15_12,	RX1_A,			SEL_SCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_15_12,	HRX1_A,			SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_15_12,	TS_SDAT0_C,		SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP12_15_12,	STP_ISD_0_C,		SEL_SSP1_0_2),
-	PINMUX_IPSR_MSEL(IP12_15_12,	RIF1_CLK_C,		SEL_DRIF1_2),
-
-	PINMUX_IPSR_MSEL(IP12_19_16,	TX1_A,			SEL_SCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_19_16,	HTX1_A,			SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_19_16,	TS_SDEN0_C,		SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP12_19_16,	STP_ISEN_0_C,		SEL_SSP1_0_2),
-	PINMUX_IPSR_MSEL(IP12_19_16,	RIF1_D0_C,		SEL_DRIF1_2),
-
-	PINMUX_IPSR_GPSR(IP12_23_20,	CTS1_N),
-	PINMUX_IPSR_MSEL(IP12_23_20,	HCTS1_N_A,		SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_23_20,	MSIOF1_RXD_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP12_23_20,	TS_SDEN1_C,		SEL_TSIF1_2),
-	PINMUX_IPSR_MSEL(IP12_23_20,	STP_ISEN_1_C,		SEL_SSP1_1_2),
-	PINMUX_IPSR_MSEL(IP12_23_20,	RIF1_D0_B,		SEL_DRIF1_1),
-	PINMUX_IPSR_GPSR(IP12_23_20,	ADIDATA),
-
-	PINMUX_IPSR_GPSR(IP12_27_24,	RTS1_N),
-	PINMUX_IPSR_MSEL(IP12_27_24,	HRTS1_N_A,		SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_27_24,	MSIOF1_TXD_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP12_27_24,	TS_SDAT1_C,		SEL_TSIF1_2),
-	PINMUX_IPSR_MSEL(IP12_27_24,	STP_ISD_1_C,		SEL_SSP1_1_2),
-	PINMUX_IPSR_MSEL(IP12_27_24,	RIF1_D1_B,		SEL_DRIF1_1),
-	PINMUX_IPSR_GPSR(IP12_27_24,	ADICHS0),
-
-	PINMUX_IPSR_GPSR(IP12_31_28,	SCK2),
-	PINMUX_IPSR_MSEL(IP12_31_28,	SCIF_CLK_B,		SEL_SCIF_1),
-	PINMUX_IPSR_MSEL(IP12_31_28,	MSIOF1_SCK_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP12_31_28,	TS_SCK1_C,		SEL_TSIF1_2),
-	PINMUX_IPSR_MSEL(IP12_31_28,	STP_ISCLK_1_C,		SEL_SSP1_1_2),
-	PINMUX_IPSR_MSEL(IP12_31_28,	RIF1_CLK_B,		SEL_DRIF1_1),
-	PINMUX_IPSR_GPSR(IP12_31_28,	ADICLK),
-
-	/* IPSR13 */
-	PINMUX_IPSR_MSEL(IP13_3_0,	TX2_A,			SEL_SCIF2_0),
-	PINMUX_IPSR_MSEL(IP13_3_0,	SD2_CD_B,		SEL_SDHI2_1),
-	PINMUX_IPSR_MSEL(IP13_3_0,	SCL1_A,			SEL_I2C1_0),
-	PINMUX_IPSR_MSEL(IP13_3_0,	FMCLK_A,		SEL_FM_0),
-	PINMUX_IPSR_MSEL(IP13_3_0,	RIF1_D1_C,		SEL_DRIF1_2),
-	PINMUX_IPSR_GPSR(IP13_3_0,	FSO_CFE_0_N),
-
-	PINMUX_IPSR_MSEL(IP13_7_4,	RX2_A,			SEL_SCIF2_0),
-	PINMUX_IPSR_MSEL(IP13_7_4,	SD2_WP_B,		SEL_SDHI2_1),
-	PINMUX_IPSR_MSEL(IP13_7_4,	SDA1_A,			SEL_I2C1_0),
-	PINMUX_IPSR_MSEL(IP13_7_4,	FMIN_A,			SEL_FM_0),
-	PINMUX_IPSR_MSEL(IP13_7_4,	RIF1_SYNC_C,		SEL_DRIF1_2),
-	PINMUX_IPSR_GPSR(IP13_7_4,	FSO_CFE_1_N),
-
-	PINMUX_IPSR_GPSR(IP13_11_8,	HSCK0),
-	PINMUX_IPSR_MSEL(IP13_11_8,	MSIOF1_SCK_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP13_11_8,	AUDIO_CLKB_A,		SEL_ADGB_0),
-	PINMUX_IPSR_MSEL(IP13_11_8,	SSI_SDATA1_B,		SEL_SSI1_1),
-	PINMUX_IPSR_MSEL(IP13_11_8,	TS_SCK0_D,		SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP13_11_8,	STP_ISCLK_0_D,		SEL_SSP1_0_3),
-	PINMUX_IPSR_MSEL(IP13_11_8,	RIF0_CLK_C,		SEL_DRIF0_2),
-	PINMUX_IPSR_MSEL(IP13_11_8,	RX5_B,			SEL_SCIF5_1),
-
-	PINMUX_IPSR_GPSR(IP13_15_12,	HRX0),
-	PINMUX_IPSR_MSEL(IP13_15_12,	MSIOF1_RXD_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP13_15_12,	SSI_SDATA2_B,		SEL_SSI2_1),
-	PINMUX_IPSR_MSEL(IP13_15_12,	TS_SDEN0_D,		SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP13_15_12,	STP_ISEN_0_D,		SEL_SSP1_0_3),
-	PINMUX_IPSR_MSEL(IP13_15_12,	RIF0_D0_C,		SEL_DRIF0_2),
-
-	PINMUX_IPSR_GPSR(IP13_19_16,	HTX0),
-	PINMUX_IPSR_MSEL(IP13_19_16,	MSIOF1_TXD_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP13_19_16,	SSI_SDATA9_B,		SEL_SSI9_1),
-	PINMUX_IPSR_MSEL(IP13_19_16,	TS_SDAT0_D,		SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP13_19_16,	STP_ISD_0_D,		SEL_SSP1_0_3),
-	PINMUX_IPSR_MSEL(IP13_19_16,	RIF0_D1_C,		SEL_DRIF0_2),
-
-	PINMUX_IPSR_GPSR(IP13_23_20,	HCTS0_N),
-	PINMUX_IPSR_MSEL(IP13_23_20,	RX2_B,			SEL_SCIF2_1),
-	PINMUX_IPSR_MSEL(IP13_23_20,	MSIOF1_SYNC_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP13_23_20,	SSI_SCK9_A,		SEL_SSI9_0),
-	PINMUX_IPSR_MSEL(IP13_23_20,	TS_SPSYNC0_D,		SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP13_23_20,	STP_ISSYNC_0_D,		SEL_SSP1_0_3),
-	PINMUX_IPSR_MSEL(IP13_23_20,	RIF0_SYNC_C,		SEL_DRIF0_2),
-	PINMUX_IPSR_GPSR(IP13_23_20,	AUDIO_CLKOUT1_A),
-
-	PINMUX_IPSR_GPSR(IP13_27_24,	HRTS0_N),
-	PINMUX_IPSR_MSEL(IP13_27_24,	TX2_B,			SEL_SCIF2_1),
-	PINMUX_IPSR_MSEL(IP13_27_24,	MSIOF1_SS1_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP13_27_24,	SSI_WS9_A,		SEL_SSI9_0),
-	PINMUX_IPSR_MSEL(IP13_27_24,	STP_IVCXO27_0_D,	SEL_SSP1_0_3),
-	PINMUX_IPSR_MSEL(IP13_27_24,	BPFCLK_A,		SEL_FM_0),
-	PINMUX_IPSR_GPSR(IP13_27_24,	AUDIO_CLKOUT2_A),
-
-	PINMUX_IPSR_GPSR(IP13_31_28,	MSIOF0_SYNC),
-	PINMUX_IPSR_GPSR(IP13_31_28,	AUDIO_CLKOUT_A),
-	PINMUX_IPSR_MSEL(IP13_31_28,	TX5_B,			SEL_SCIF5_1),
-	PINMUX_IPSR_MSEL(IP13_31_28,	BPFCLK_D,		SEL_FM_3),
-
-	/* IPSR14 */
-	PINMUX_IPSR_GPSR(IP14_3_0,	MSIOF0_SS1),
-	PINMUX_IPSR_MSEL(IP14_3_0,	RX5_A,			SEL_SCIF5_0),
-	PINMUX_IPSR_GPSR(IP14_3_0,	NFWP_N_A),
-	PINMUX_IPSR_MSEL(IP14_3_0,	AUDIO_CLKA_C,		SEL_ADGA_2),
-	PINMUX_IPSR_MSEL(IP14_3_0,	SSI_SCK2_A,		SEL_SSI2_0),
-	PINMUX_IPSR_MSEL(IP14_3_0,	STP_IVCXO27_0_C,	SEL_SSP1_0_2),
-	PINMUX_IPSR_GPSR(IP14_3_0,	AUDIO_CLKOUT3_A),
-	PINMUX_IPSR_MSEL(IP14_3_0,	TCLK1_B,		SEL_TIMER_TMU1_1),
-
-	PINMUX_IPSR_GPSR(IP14_7_4,	MSIOF0_SS2),
-	PINMUX_IPSR_MSEL(IP14_7_4,	TX5_A,			SEL_SCIF5_0),
-	PINMUX_IPSR_MSEL(IP14_7_4,	MSIOF1_SS2_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP14_7_4,	AUDIO_CLKC_A,		SEL_ADGC_0),
-	PINMUX_IPSR_MSEL(IP14_7_4,	SSI_WS2_A,		SEL_SSI2_0),
-	PINMUX_IPSR_MSEL(IP14_7_4,	STP_OPWM_0_D,		SEL_SSP1_0_3),
-	PINMUX_IPSR_GPSR(IP14_7_4,	AUDIO_CLKOUT_D),
-	PINMUX_IPSR_MSEL(IP14_7_4,	SPEEDIN_B,		SEL_SPEED_PULSE_1),
-
-	PINMUX_IPSR_GPSR(IP14_11_8,	MLB_CLK),
-	PINMUX_IPSR_MSEL(IP14_11_8,	MSIOF1_SCK_F,		SEL_MSIOF1_5),
-	PINMUX_IPSR_MSEL(IP14_11_8,	SCL1_B,			SEL_I2C1_1),
-
-	PINMUX_IPSR_GPSR(IP14_15_12,	MLB_SIG),
-	PINMUX_IPSR_MSEL(IP14_15_12,	RX1_B,			SEL_SCIF1_1),
-	PINMUX_IPSR_MSEL(IP14_15_12,	MSIOF1_SYNC_F,		SEL_MSIOF1_5),
-	PINMUX_IPSR_MSEL(IP14_15_12,	SDA1_B,			SEL_I2C1_1),
-
-	PINMUX_IPSR_GPSR(IP14_19_16,	MLB_DAT),
-	PINMUX_IPSR_MSEL(IP14_19_16,	TX1_B,			SEL_SCIF1_1),
-	PINMUX_IPSR_MSEL(IP14_19_16,	MSIOF1_RXD_F,		SEL_MSIOF1_5),
-
-	PINMUX_IPSR_GPSR(IP14_23_20,	SSI_SCK01239),
-	PINMUX_IPSR_MSEL(IP14_23_20,	MSIOF1_TXD_F,		SEL_MSIOF1_5),
-
-	PINMUX_IPSR_GPSR(IP14_27_24,	SSI_WS01239),
-	PINMUX_IPSR_MSEL(IP14_27_24,	MSIOF1_SS1_F,		SEL_MSIOF1_5),
-
-	PINMUX_IPSR_GPSR(IP14_31_28,	SSI_SDATA0),
-	PINMUX_IPSR_MSEL(IP14_31_28,	MSIOF1_SS2_F,		SEL_MSIOF1_5),
-
-	/* IPSR15 */
-	PINMUX_IPSR_MSEL(IP15_3_0,	SSI_SDATA1_A,		SEL_SSI1_0),
-
-	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SDATA2_A,		SEL_SSI2_0),
-	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SCK1_B,		SEL_SSI1_1),
-
-	PINMUX_IPSR_GPSR(IP15_11_8,	SSI_SCK349),
-	PINMUX_IPSR_MSEL(IP15_11_8,	MSIOF1_SS1_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP15_11_8,	STP_OPWM_0_A,		SEL_SSP1_0_0),
-
-	PINMUX_IPSR_GPSR(IP15_15_12,	SSI_WS349),
-	PINMUX_IPSR_MSEL(IP15_15_12,	HCTS2_N_A,		SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP15_15_12,	MSIOF1_SS2_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP15_15_12,	STP_IVCXO27_0_A,	SEL_SSP1_0_0),
-
-	PINMUX_IPSR_GPSR(IP15_19_16,	SSI_SDATA3),
-	PINMUX_IPSR_MSEL(IP15_19_16,	HRTS2_N_A,		SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP15_19_16,	MSIOF1_TXD_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP15_19_16,	TS_SCK0_A,		SEL_TSIF0_0),
-	PINMUX_IPSR_MSEL(IP15_19_16,	STP_ISCLK_0_A,		SEL_SSP1_0_0),
-	PINMUX_IPSR_MSEL(IP15_19_16,	RIF0_D1_A,		SEL_DRIF0_0),
-	PINMUX_IPSR_MSEL(IP15_19_16,	RIF2_D0_A,		SEL_DRIF2_0),
-
-	PINMUX_IPSR_GPSR(IP15_23_20,	SSI_SCK4),
-	PINMUX_IPSR_MSEL(IP15_23_20,	HRX2_A,			SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP15_23_20,	MSIOF1_SCK_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP15_23_20,	TS_SDAT0_A,		SEL_TSIF0_0),
-	PINMUX_IPSR_MSEL(IP15_23_20,	STP_ISD_0_A,		SEL_SSP1_0_0),
-	PINMUX_IPSR_MSEL(IP15_23_20,	RIF0_CLK_A,		SEL_DRIF0_0),
-	PINMUX_IPSR_MSEL(IP15_23_20,	RIF2_CLK_A,		SEL_DRIF2_0),
-
-	PINMUX_IPSR_GPSR(IP15_27_24,	SSI_WS4),
-	PINMUX_IPSR_MSEL(IP15_27_24,	HTX2_A,			SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP15_27_24,	MSIOF1_SYNC_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP15_27_24,	TS_SDEN0_A,		SEL_TSIF0_0),
-	PINMUX_IPSR_MSEL(IP15_27_24,	STP_ISEN_0_A,		SEL_SSP1_0_0),
-	PINMUX_IPSR_MSEL(IP15_27_24,	RIF0_SYNC_A,		SEL_DRIF0_0),
-	PINMUX_IPSR_MSEL(IP15_27_24,	RIF2_SYNC_A,		SEL_DRIF2_0),
-
-	PINMUX_IPSR_GPSR(IP15_31_28,	SSI_SDATA4),
-	PINMUX_IPSR_MSEL(IP15_31_28,	HSCK2_A,		SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP15_31_28,	MSIOF1_RXD_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP15_31_28,	TS_SPSYNC0_A,		SEL_TSIF0_0),
-	PINMUX_IPSR_MSEL(IP15_31_28,	STP_ISSYNC_0_A,		SEL_SSP1_0_0),
-	PINMUX_IPSR_MSEL(IP15_31_28,	RIF0_D0_A,		SEL_DRIF0_0),
-	PINMUX_IPSR_MSEL(IP15_31_28,	RIF2_D1_A,		SEL_DRIF2_0),
-
-	/* IPSR16 */
-	PINMUX_IPSR_GPSR(IP16_3_0,	SSI_SCK6),
-	PINMUX_IPSR_GPSR(IP16_3_0,	USB2_PWEN),
-	PINMUX_IPSR_MSEL(IP16_3_0,	SIM0_RST_D,		SEL_SIMCARD_3),
-
-	PINMUX_IPSR_GPSR(IP16_7_4,	SSI_WS6),
-	PINMUX_IPSR_GPSR(IP16_7_4,	USB2_OVC),
-	PINMUX_IPSR_MSEL(IP16_7_4,	SIM0_D_D,		SEL_SIMCARD_3),
-
-	PINMUX_IPSR_GPSR(IP16_11_8,	SSI_SDATA6),
-	PINMUX_IPSR_MSEL(IP16_11_8,	SIM0_CLK_D,		SEL_SIMCARD_3),
-	PINMUX_IPSR_GPSR(IP16_11_8,	SATA_DEVSLP_A),
-
-	PINMUX_IPSR_GPSR(IP16_15_12,	SSI_SCK78),
-	PINMUX_IPSR_MSEL(IP16_15_12,	HRX2_B,			SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP16_15_12,	MSIOF1_SCK_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP16_15_12,	TS_SCK1_A,		SEL_TSIF1_0),
-	PINMUX_IPSR_MSEL(IP16_15_12,	STP_ISCLK_1_A,		SEL_SSP1_1_0),
-	PINMUX_IPSR_MSEL(IP16_15_12,	RIF1_CLK_A,		SEL_DRIF1_0),
-	PINMUX_IPSR_MSEL(IP16_15_12,	RIF3_CLK_A,		SEL_DRIF3_0),
-
-	PINMUX_IPSR_GPSR(IP16_19_16,	SSI_WS78),
-	PINMUX_IPSR_MSEL(IP16_19_16,	HTX2_B,			SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP16_19_16,	MSIOF1_SYNC_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP16_19_16,	TS_SDAT1_A,		SEL_TSIF1_0),
-	PINMUX_IPSR_MSEL(IP16_19_16,	STP_ISD_1_A,		SEL_SSP1_1_0),
-	PINMUX_IPSR_MSEL(IP16_19_16,	RIF1_SYNC_A,		SEL_DRIF1_0),
-	PINMUX_IPSR_MSEL(IP16_19_16,	RIF3_SYNC_A,		SEL_DRIF3_0),
-
-	PINMUX_IPSR_GPSR(IP16_23_20,	SSI_SDATA7),
-	PINMUX_IPSR_MSEL(IP16_23_20,	HCTS2_N_B,		SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP16_23_20,	MSIOF1_RXD_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP16_23_20,	TS_SDEN1_A,		SEL_TSIF1_0),
-	PINMUX_IPSR_MSEL(IP16_23_20,	STP_ISEN_1_A,		SEL_SSP1_1_0),
-	PINMUX_IPSR_MSEL(IP16_23_20,	RIF1_D0_A,		SEL_DRIF1_0),
-	PINMUX_IPSR_MSEL(IP16_23_20,	RIF3_D0_A,		SEL_DRIF3_0),
-	PINMUX_IPSR_MSEL(IP16_23_20,	TCLK2_A,		SEL_TIMER_TMU2_0),
-
-	PINMUX_IPSR_GPSR(IP16_27_24,	SSI_SDATA8),
-	PINMUX_IPSR_MSEL(IP16_27_24,	HRTS2_N_B,		SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP16_27_24,	MSIOF1_TXD_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP16_27_24,	TS_SPSYNC1_A,		SEL_TSIF1_0),
-	PINMUX_IPSR_MSEL(IP16_27_24,	STP_ISSYNC_1_A,		SEL_SSP1_1_0),
-	PINMUX_IPSR_MSEL(IP16_27_24,	RIF1_D1_A,		SEL_DRIF1_0),
-	PINMUX_IPSR_MSEL(IP16_27_24,	RIF3_D1_A,		SEL_DRIF3_0),
-
-	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_SDATA9_A,		SEL_SSI9_0),
-	PINMUX_IPSR_MSEL(IP16_31_28,	HSCK2_B,		SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP16_31_28,	MSIOF1_SS1_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP16_31_28,	HSCK1_A,		SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_WS1_B,		SEL_SSI1_1),
-	PINMUX_IPSR_GPSR(IP16_31_28,	SCK1),
-	PINMUX_IPSR_MSEL(IP16_31_28,	STP_IVCXO27_1_A,	SEL_SSP1_1_0),
-	PINMUX_IPSR_MSEL(IP16_31_28,	SCK5_A,			SEL_SCIF5_0),
-
-	/* IPSR17 */
-	PINMUX_IPSR_MSEL(IP17_3_0,	AUDIO_CLKA_A,		SEL_ADGA_0),
-
-	PINMUX_IPSR_MSEL(IP17_7_4,	AUDIO_CLKB_B,		SEL_ADGB_1),
-	PINMUX_IPSR_MSEL(IP17_7_4,	SCIF_CLK_A,		SEL_SCIF_0),
-	PINMUX_IPSR_MSEL(IP17_7_4,	STP_IVCXO27_1_D,	SEL_SSP1_1_3),
-	PINMUX_IPSR_MSEL(IP17_7_4,	REMOCON_A,		SEL_REMOCON_0),
-	PINMUX_IPSR_MSEL(IP17_7_4,	TCLK1_A,		SEL_TIMER_TMU1_0),
-
-	PINMUX_IPSR_GPSR(IP17_11_8,	USB0_PWEN),
-	PINMUX_IPSR_MSEL(IP17_11_8,	SIM0_RST_C,		SEL_SIMCARD_2),
-	PINMUX_IPSR_MSEL(IP17_11_8,	TS_SCK1_D,		SEL_TSIF1_3),
-	PINMUX_IPSR_MSEL(IP17_11_8,	STP_ISCLK_1_D,		SEL_SSP1_1_3),
-	PINMUX_IPSR_MSEL(IP17_11_8,	BPFCLK_B,		SEL_FM_1),
-	PINMUX_IPSR_MSEL(IP17_11_8,	RIF3_CLK_B,		SEL_DRIF3_1),
-	PINMUX_IPSR_MSEL(IP17_11_8,	HSCK2_C,		SEL_HSCIF2_2),
-
-	PINMUX_IPSR_GPSR(IP17_15_12,	USB0_OVC),
-	PINMUX_IPSR_MSEL(IP17_15_12,	SIM0_D_C,		SEL_SIMCARD_2),
-	PINMUX_IPSR_MSEL(IP17_15_12,	TS_SDAT1_D,		SEL_TSIF1_3),
-	PINMUX_IPSR_MSEL(IP17_15_12,	STP_ISD_1_D,		SEL_SSP1_1_3),
-	PINMUX_IPSR_MSEL(IP17_15_12,	RIF3_SYNC_B,		SEL_DRIF3_1),
-	PINMUX_IPSR_MSEL(IP17_15_12,	HRX2_C,			SEL_HSCIF2_2),
-
-	PINMUX_IPSR_GPSR(IP17_19_16,	USB1_PWEN),
-	PINMUX_IPSR_MSEL(IP17_19_16,	SIM0_CLK_C,		SEL_SIMCARD_2),
-	PINMUX_IPSR_MSEL(IP17_19_16,	SSI_SCK1_A,		SEL_SSI1_0),
-	PINMUX_IPSR_MSEL(IP17_19_16,	TS_SCK0_E,		SEL_TSIF0_4),
-	PINMUX_IPSR_MSEL(IP17_19_16,	STP_ISCLK_0_E,		SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP17_19_16,	FMCLK_B,		SEL_FM_1),
-	PINMUX_IPSR_MSEL(IP17_19_16,	RIF2_CLK_B,		SEL_DRIF2_1),
-	PINMUX_IPSR_MSEL(IP17_19_16,	SPEEDIN_A,		SEL_SPEED_PULSE_0),
-	PINMUX_IPSR_MSEL(IP17_19_16,	HTX2_C,			SEL_HSCIF2_2),
-
-	PINMUX_IPSR_GPSR(IP17_23_20,	USB1_OVC),
-	PINMUX_IPSR_MSEL(IP17_23_20,	MSIOF1_SS2_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP17_23_20,	SSI_WS1_A,		SEL_SSI1_0),
-	PINMUX_IPSR_MSEL(IP17_23_20,	TS_SDAT0_E,		SEL_TSIF0_4),
-	PINMUX_IPSR_MSEL(IP17_23_20,	STP_ISD_0_E,		SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP17_23_20,	FMIN_B,			SEL_FM_1),
-	PINMUX_IPSR_MSEL(IP17_23_20,	RIF2_SYNC_B,		SEL_DRIF2_1),
-	PINMUX_IPSR_MSEL(IP17_23_20,	REMOCON_B,		SEL_REMOCON_1),
-	PINMUX_IPSR_MSEL(IP17_23_20,	HCTS2_N_C,		SEL_HSCIF2_2),
-
-	PINMUX_IPSR_GPSR(IP17_27_24,	USB30_PWEN),
-	PINMUX_IPSR_GPSR(IP17_27_24,	AUDIO_CLKOUT_B),
-	PINMUX_IPSR_MSEL(IP17_27_24,	SSI_SCK2_B,		SEL_SSI2_1),
-	PINMUX_IPSR_MSEL(IP17_27_24,	TS_SDEN1_D,		SEL_TSIF1_3),
-	PINMUX_IPSR_MSEL(IP17_27_24,	STP_ISEN_1_D,		SEL_SSP1_1_3),
-	PINMUX_IPSR_MSEL(IP17_27_24,	STP_OPWM_0_E,		SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP17_27_24,	RIF3_D0_B,		SEL_DRIF3_1),
-	PINMUX_IPSR_MSEL(IP17_27_24,	TCLK2_B,		SEL_TIMER_TMU2_1),
-	PINMUX_IPSR_GPSR(IP17_27_24,	TPU0TO0),
-	PINMUX_IPSR_MSEL(IP17_27_24,	BPFCLK_C,		SEL_FM_2),
-	PINMUX_IPSR_MSEL(IP17_27_24,	HRTS2_N_C,		SEL_HSCIF2_2),
-
-	PINMUX_IPSR_GPSR(IP17_31_28,	USB30_OVC),
-	PINMUX_IPSR_GPSR(IP17_31_28,	AUDIO_CLKOUT1_B),
-	PINMUX_IPSR_MSEL(IP17_31_28,	SSI_WS2_B,		SEL_SSI2_1),
-	PINMUX_IPSR_MSEL(IP17_31_28,	TS_SPSYNC1_D,		SEL_TSIF1_3),
-	PINMUX_IPSR_MSEL(IP17_31_28,	STP_ISSYNC_1_D,		SEL_SSP1_1_3),
-	PINMUX_IPSR_MSEL(IP17_31_28,	STP_IVCXO27_0_E,	SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP17_31_28,	RIF3_D1_B,		SEL_DRIF3_1),
-	PINMUX_IPSR_GPSR(IP17_31_28,	FSO_TOE_N),
-	PINMUX_IPSR_GPSR(IP17_31_28,	TPU0TO1),
-
-	/* IPSR18 */
-	PINMUX_IPSR_GPSR(IP18_3_0,	USB2_CH3_PWEN),
-	PINMUX_IPSR_GPSR(IP18_3_0,	AUDIO_CLKOUT2_B),
-	PINMUX_IPSR_MSEL(IP18_3_0,	SSI_SCK9_B,		SEL_SSI9_1),
-	PINMUX_IPSR_MSEL(IP18_3_0,	TS_SDEN0_E,		SEL_TSIF0_4),
-	PINMUX_IPSR_MSEL(IP18_3_0,	STP_ISEN_0_E,		SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP18_3_0,	RIF2_D0_B,		SEL_DRIF2_1),
-	PINMUX_IPSR_GPSR(IP18_3_0,	TPU0TO2),
-	PINMUX_IPSR_MSEL(IP18_3_0,	FMCLK_C,		SEL_FM_2),
-	PINMUX_IPSR_MSEL(IP18_3_0,	FMCLK_D,		SEL_FM_3),
-
-	PINMUX_IPSR_GPSR(IP18_7_4,	USB2_CH3_OVC),
-	PINMUX_IPSR_GPSR(IP18_7_4,	AUDIO_CLKOUT3_B),
-	PINMUX_IPSR_MSEL(IP18_7_4,	SSI_WS9_B,		SEL_SSI9_1),
-	PINMUX_IPSR_MSEL(IP18_7_4,	TS_SPSYNC0_E,		SEL_TSIF0_4),
-	PINMUX_IPSR_MSEL(IP18_7_4,	STP_ISSYNC_0_E,		SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP18_7_4,	RIF2_D1_B,		SEL_DRIF2_1),
-	PINMUX_IPSR_GPSR(IP18_7_4,	TPU0TO3),
-	PINMUX_IPSR_MSEL(IP18_7_4,	FMIN_C,			SEL_FM_2),
-	PINMUX_IPSR_MSEL(IP18_7_4,	FMIN_D,			SEL_FM_3),
-
-/*
- * Static pins can not be muxed between different functions but
- * still need mark entries in the pinmux list. Add each static
- * pin to the list without an associated function. The sh-pfc
- * core will do the right thing and skip trying to mux the pin
- * while still applying configuration to it.
- */
-#define FM(x)	PINMUX_DATA(x##_MARK, 0),
-	PINMUX_STATIC
-#undef FM
-};
-
-/*
- * Pins not associated with a GPIO port.
- */
-enum {
-	GP_ASSIGN_LAST(),
-	NOGP_ALL(),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	PINMUX_GPIO_GP_ALL(),
-	PINMUX_NOGP_ALL(),
-};
-
-/* - AUDIO CLOCK ------------------------------------------------------------ */
-static const unsigned int audio_clk_a_a_pins[] = {
-	/* CLK A */
-	RCAR_GP_PIN(6, 22),
-};
-static const unsigned int audio_clk_a_a_mux[] = {
-	AUDIO_CLKA_A_MARK,
-};
-static const unsigned int audio_clk_a_b_pins[] = {
-	/* CLK A */
-	RCAR_GP_PIN(5, 4),
-};
-static const unsigned int audio_clk_a_b_mux[] = {
-	AUDIO_CLKA_B_MARK,
-};
-static const unsigned int audio_clk_a_c_pins[] = {
-	/* CLK A */
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int audio_clk_a_c_mux[] = {
-	AUDIO_CLKA_C_MARK,
-};
-static const unsigned int audio_clk_b_a_pins[] = {
-	/* CLK B */
-	RCAR_GP_PIN(5, 12),
-};
-static const unsigned int audio_clk_b_a_mux[] = {
-	AUDIO_CLKB_A_MARK,
-};
-static const unsigned int audio_clk_b_b_pins[] = {
-	/* CLK B */
-	RCAR_GP_PIN(6, 23),
-};
-static const unsigned int audio_clk_b_b_mux[] = {
-	AUDIO_CLKB_B_MARK,
-};
-static const unsigned int audio_clk_c_a_pins[] = {
-	/* CLK C */
-	RCAR_GP_PIN(5, 21),
-};
-static const unsigned int audio_clk_c_a_mux[] = {
-	AUDIO_CLKC_A_MARK,
-};
-static const unsigned int audio_clk_c_b_pins[] = {
-	/* CLK C */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int audio_clk_c_b_mux[] = {
-	AUDIO_CLKC_B_MARK,
-};
-static const unsigned int audio_clkout_a_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(5, 18),
-};
-static const unsigned int audio_clkout_a_mux[] = {
-	AUDIO_CLKOUT_A_MARK,
-};
-static const unsigned int audio_clkout_b_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(6, 28),
-};
-static const unsigned int audio_clkout_b_mux[] = {
-	AUDIO_CLKOUT_B_MARK,
-};
-static const unsigned int audio_clkout_c_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(5, 3),
-};
-static const unsigned int audio_clkout_c_mux[] = {
-	AUDIO_CLKOUT_C_MARK,
-};
-static const unsigned int audio_clkout_d_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(5, 21),
-};
-static const unsigned int audio_clkout_d_mux[] = {
-	AUDIO_CLKOUT_D_MARK,
-};
-static const unsigned int audio_clkout1_a_pins[] = {
-	/* CLKOUT1 */
-	RCAR_GP_PIN(5, 15),
-};
-static const unsigned int audio_clkout1_a_mux[] = {
-	AUDIO_CLKOUT1_A_MARK,
-};
-static const unsigned int audio_clkout1_b_pins[] = {
-	/* CLKOUT1 */
-	RCAR_GP_PIN(6, 29),
-};
-static const unsigned int audio_clkout1_b_mux[] = {
-	AUDIO_CLKOUT1_B_MARK,
-};
-static const unsigned int audio_clkout2_a_pins[] = {
-	/* CLKOUT2 */
-	RCAR_GP_PIN(5, 16),
-};
-static const unsigned int audio_clkout2_a_mux[] = {
-	AUDIO_CLKOUT2_A_MARK,
-};
-static const unsigned int audio_clkout2_b_pins[] = {
-	/* CLKOUT2 */
-	RCAR_GP_PIN(6, 30),
-};
-static const unsigned int audio_clkout2_b_mux[] = {
-	AUDIO_CLKOUT2_B_MARK,
-};
-static const unsigned int audio_clkout3_a_pins[] = {
-	/* CLKOUT3 */
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int audio_clkout3_a_mux[] = {
-	AUDIO_CLKOUT3_A_MARK,
-};
-static const unsigned int audio_clkout3_b_pins[] = {
-	/* CLKOUT3 */
-	RCAR_GP_PIN(6, 31),
-};
-static const unsigned int audio_clkout3_b_mux[] = {
-	AUDIO_CLKOUT3_B_MARK,
-};
-
-/* - EtherAVB --------------------------------------------------------------- */
-static const unsigned int avb_link_pins[] = {
-	/* AVB_LINK */
-	RCAR_GP_PIN(2, 12),
-};
-static const unsigned int avb_link_mux[] = {
-	AVB_LINK_MARK,
-};
-static const unsigned int avb_magic_pins[] = {
-	/* AVB_MAGIC_ */
-	RCAR_GP_PIN(2, 10),
-};
-static const unsigned int avb_magic_mux[] = {
-	AVB_MAGIC_MARK,
-};
-static const unsigned int avb_phy_int_pins[] = {
-	/* AVB_PHY_INT */
-	RCAR_GP_PIN(2, 11),
-};
-static const unsigned int avb_phy_int_mux[] = {
-	AVB_PHY_INT_MARK,
-};
-static const unsigned int avb_mdio_pins[] = {
-	/* AVB_MDC, AVB_MDIO */
-	RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
-};
-static const unsigned int avb_mdio_mux[] = {
-	AVB_MDC_MARK, AVB_MDIO_MARK,
-};
-static const unsigned int avb_mii_pins[] = {
-	/*
-	 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
-	 * AVB_TD1, AVB_TD2, AVB_TD3,
-	 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
-	 * AVB_RD1, AVB_RD2, AVB_RD3,
-	 * AVB_TXCREFCLK
-	 */
-	PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
-	PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
-	PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
-	PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
-	PIN_AVB_TXCREFCLK,
-
-};
-static const unsigned int avb_mii_mux[] = {
-	AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
-	AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
-	AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
-	AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
-	AVB_TXCREFCLK_MARK,
-};
-static const unsigned int avb_avtp_pps_pins[] = {
-	/* AVB_AVTP_PPS */
-	RCAR_GP_PIN(2, 6),
-};
-static const unsigned int avb_avtp_pps_mux[] = {
-	AVB_AVTP_PPS_MARK,
-};
-static const unsigned int avb_avtp_match_a_pins[] = {
-	/* AVB_AVTP_MATCH_A */
-	RCAR_GP_PIN(2, 13),
-};
-static const unsigned int avb_avtp_match_a_mux[] = {
-	AVB_AVTP_MATCH_A_MARK,
-};
-static const unsigned int avb_avtp_capture_a_pins[] = {
-	/* AVB_AVTP_CAPTURE_A */
-	RCAR_GP_PIN(2, 14),
-};
-static const unsigned int avb_avtp_capture_a_mux[] = {
-	AVB_AVTP_CAPTURE_A_MARK,
-};
-static const unsigned int avb_avtp_match_b_pins[] = {
-	/*  AVB_AVTP_MATCH_B */
-	RCAR_GP_PIN(1, 8),
-};
-static const unsigned int avb_avtp_match_b_mux[] = {
-	AVB_AVTP_MATCH_B_MARK,
-};
-static const unsigned int avb_avtp_capture_b_pins[] = {
-	/* AVB_AVTP_CAPTURE_B */
-	RCAR_GP_PIN(1, 11),
-};
-static const unsigned int avb_avtp_capture_b_mux[] = {
-	AVB_AVTP_CAPTURE_B_MARK,
-};
-
-/* - CAN ------------------------------------------------------------------ */
-static const unsigned int can0_data_a_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(1, 23),	RCAR_GP_PIN(1, 24),
-};
-static const unsigned int can0_data_a_mux[] = {
-	CAN0_TX_A_MARK,		CAN0_RX_A_MARK,
-};
-static const unsigned int can0_data_b_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(2, 0),	RCAR_GP_PIN(2, 1),
-};
-static const unsigned int can0_data_b_mux[] = {
-	CAN0_TX_B_MARK,		CAN0_RX_B_MARK,
-};
-static const unsigned int can1_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(1, 22),	RCAR_GP_PIN(1, 26),
-};
-static const unsigned int can1_data_mux[] = {
-	CAN1_TX_MARK,		CAN1_RX_MARK,
-};
-
-/* - CAN Clock -------------------------------------------------------------- */
-static const unsigned int can_clk_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(1, 25),
-};
-static const unsigned int can_clk_mux[] = {
-	CAN_CLK_MARK,
-};
-
-/* - CAN FD --------------------------------------------------------------- */
-static const unsigned int canfd0_data_a_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
-};
-static const unsigned int canfd0_data_a_mux[] = {
-	CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
-};
-static const unsigned int canfd0_data_b_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
-};
-static const unsigned int canfd0_data_b_mux[] = {
-	CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
-};
-static const unsigned int canfd1_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
-};
-static const unsigned int canfd1_data_mux[] = {
-	CANFD1_TX_MARK,         CANFD1_RX_MARK,
-};
-
-/* - DRIF0 --------------------------------------------------------------- */
-static const unsigned int drif0_ctrl_a_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
-};
-static const unsigned int drif0_ctrl_a_mux[] = {
-	RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
-};
-static const unsigned int drif0_data0_a_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 10),
-};
-static const unsigned int drif0_data0_a_mux[] = {
-	RIF0_D0_A_MARK,
-};
-static const unsigned int drif0_data1_a_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 7),
-};
-static const unsigned int drif0_data1_a_mux[] = {
-	RIF0_D1_A_MARK,
-};
-static const unsigned int drif0_ctrl_b_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
-};
-static const unsigned int drif0_ctrl_b_mux[] = {
-	RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
-};
-static const unsigned int drif0_data0_b_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(5, 1),
-};
-static const unsigned int drif0_data0_b_mux[] = {
-	RIF0_D0_B_MARK,
-};
-static const unsigned int drif0_data1_b_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(5, 2),
-};
-static const unsigned int drif0_data1_b_mux[] = {
-	RIF0_D1_B_MARK,
-};
-static const unsigned int drif0_ctrl_c_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
-};
-static const unsigned int drif0_ctrl_c_mux[] = {
-	RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
-};
-static const unsigned int drif0_data0_c_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(5, 13),
-};
-static const unsigned int drif0_data0_c_mux[] = {
-	RIF0_D0_C_MARK,
-};
-static const unsigned int drif0_data1_c_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(5, 14),
-};
-static const unsigned int drif0_data1_c_mux[] = {
-	RIF0_D1_C_MARK,
-};
-/* - DRIF1 --------------------------------------------------------------- */
-static const unsigned int drif1_ctrl_a_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
-};
-static const unsigned int drif1_ctrl_a_mux[] = {
-	RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
-};
-static const unsigned int drif1_data0_a_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 19),
-};
-static const unsigned int drif1_data0_a_mux[] = {
-	RIF1_D0_A_MARK,
-};
-static const unsigned int drif1_data1_a_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 20),
-};
-static const unsigned int drif1_data1_a_mux[] = {
-	RIF1_D1_A_MARK,
-};
-static const unsigned int drif1_ctrl_b_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
-};
-static const unsigned int drif1_ctrl_b_mux[] = {
-	RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
-};
-static const unsigned int drif1_data0_b_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(5, 7),
-};
-static const unsigned int drif1_data0_b_mux[] = {
-	RIF1_D0_B_MARK,
-};
-static const unsigned int drif1_data1_b_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(5, 8),
-};
-static const unsigned int drif1_data1_b_mux[] = {
-	RIF1_D1_B_MARK,
-};
-static const unsigned int drif1_ctrl_c_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
-};
-static const unsigned int drif1_ctrl_c_mux[] = {
-	RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
-};
-static const unsigned int drif1_data0_c_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(5, 6),
-};
-static const unsigned int drif1_data0_c_mux[] = {
-	RIF1_D0_C_MARK,
-};
-static const unsigned int drif1_data1_c_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(5, 10),
-};
-static const unsigned int drif1_data1_c_mux[] = {
-	RIF1_D1_C_MARK,
-};
-/* - DRIF2 --------------------------------------------------------------- */
-static const unsigned int drif2_ctrl_a_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
-};
-static const unsigned int drif2_ctrl_a_mux[] = {
-	RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
-};
-static const unsigned int drif2_data0_a_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 7),
-};
-static const unsigned int drif2_data0_a_mux[] = {
-	RIF2_D0_A_MARK,
-};
-static const unsigned int drif2_data1_a_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 10),
-};
-static const unsigned int drif2_data1_a_mux[] = {
-	RIF2_D1_A_MARK,
-};
-static const unsigned int drif2_ctrl_b_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
-};
-static const unsigned int drif2_ctrl_b_mux[] = {
-	RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
-};
-static const unsigned int drif2_data0_b_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 30),
-};
-static const unsigned int drif2_data0_b_mux[] = {
-	RIF2_D0_B_MARK,
-};
-static const unsigned int drif2_data1_b_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 31),
-};
-static const unsigned int drif2_data1_b_mux[] = {
-	RIF2_D1_B_MARK,
-};
-/* - DRIF3 --------------------------------------------------------------- */
-static const unsigned int drif3_ctrl_a_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
-};
-static const unsigned int drif3_ctrl_a_mux[] = {
-	RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
-};
-static const unsigned int drif3_data0_a_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 19),
-};
-static const unsigned int drif3_data0_a_mux[] = {
-	RIF3_D0_A_MARK,
-};
-static const unsigned int drif3_data1_a_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 20),
-};
-static const unsigned int drif3_data1_a_mux[] = {
-	RIF3_D1_A_MARK,
-};
-static const unsigned int drif3_ctrl_b_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
-};
-static const unsigned int drif3_ctrl_b_mux[] = {
-	RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
-};
-static const unsigned int drif3_data0_b_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 28),
-};
-static const unsigned int drif3_data0_b_mux[] = {
-	RIF3_D0_B_MARK,
-};
-static const unsigned int drif3_data1_b_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 29),
-};
-static const unsigned int drif3_data1_b_mux[] = {
-	RIF3_D1_B_MARK,
-};
-
-/* - DU --------------------------------------------------------------------- */
-static const unsigned int du_rgb666_pins[] = {
-	/* R[7:2], G[7:2], B[7:2] */
-	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
-	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
-	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
-	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
-};
-static const unsigned int du_rgb666_mux[] = {
-	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
-	DU_DR3_MARK, DU_DR2_MARK,
-	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
-	DU_DG3_MARK, DU_DG2_MARK,
-	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
-	DU_DB3_MARK, DU_DB2_MARK,
-};
-static const unsigned int du_rgb888_pins[] = {
-	/* R[7:0], G[7:0], B[7:0] */
-	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
-	RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
-	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
-	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
-	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
-	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
-	RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
-};
-static const unsigned int du_rgb888_mux[] = {
-	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
-	DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
-	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
-	DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
-	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
-	DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
-};
-static const unsigned int du_clk_out_0_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(1, 27),
-};
-static const unsigned int du_clk_out_0_mux[] = {
-	DU_DOTCLKOUT0_MARK
-};
-static const unsigned int du_clk_out_1_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(2, 3),
-};
-static const unsigned int du_clk_out_1_mux[] = {
-	DU_DOTCLKOUT1_MARK
-};
-static const unsigned int du_sync_pins[] = {
-	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
-	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
-};
-static const unsigned int du_sync_mux[] = {
-	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
-};
-static const unsigned int du_oddf_pins[] = {
-	/* EXDISP/EXODDF/EXCDE */
-	RCAR_GP_PIN(2, 2),
-};
-static const unsigned int du_oddf_mux[] = {
-	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
-};
-static const unsigned int du_cde_pins[] = {
-	/* CDE */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int du_cde_mux[] = {
-	DU_CDE_MARK,
-};
-static const unsigned int du_disp_pins[] = {
-	/* DISP */
-	RCAR_GP_PIN(2, 1),
-};
-static const unsigned int du_disp_mux[] = {
-	DU_DISP_MARK,
-};
-
-/* - HSCIF0 ----------------------------------------------------------------- */
-static const unsigned int hscif0_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
-};
-static const unsigned int hscif0_data_mux[] = {
-	HRX0_MARK, HTX0_MARK,
-};
-static const unsigned int hscif0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 12),
-};
-static const unsigned int hscif0_clk_mux[] = {
-	HSCK0_MARK,
-};
-static const unsigned int hscif0_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
-};
-static const unsigned int hscif0_ctrl_mux[] = {
-	HRTS0_N_MARK, HCTS0_N_MARK,
-};
-/* - HSCIF1 ----------------------------------------------------------------- */
-static const unsigned int hscif1_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
-};
-static const unsigned int hscif1_data_a_mux[] = {
-	HRX1_A_MARK, HTX1_A_MARK,
-};
-static const unsigned int hscif1_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int hscif1_clk_a_mux[] = {
-	HSCK1_A_MARK,
-};
-static const unsigned int hscif1_ctrl_a_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
-};
-static const unsigned int hscif1_ctrl_a_mux[] = {
-	HRTS1_N_A_MARK, HCTS1_N_A_MARK,
-};
-
-static const unsigned int hscif1_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-};
-static const unsigned int hscif1_data_b_mux[] = {
-	HRX1_B_MARK, HTX1_B_MARK,
-};
-static const unsigned int hscif1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int hscif1_clk_b_mux[] = {
-	HSCK1_B_MARK,
-};
-static const unsigned int hscif1_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
-};
-static const unsigned int hscif1_ctrl_b_mux[] = {
-	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
-};
-/* - HSCIF2 ----------------------------------------------------------------- */
-static const unsigned int hscif2_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
-};
-static const unsigned int hscif2_data_a_mux[] = {
-	HRX2_A_MARK, HTX2_A_MARK,
-};
-static const unsigned int hscif2_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 10),
-};
-static const unsigned int hscif2_clk_a_mux[] = {
-	HSCK2_A_MARK,
-};
-static const unsigned int hscif2_ctrl_a_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
-};
-static const unsigned int hscif2_ctrl_a_mux[] = {
-	HRTS2_N_A_MARK, HCTS2_N_A_MARK,
-};
-
-static const unsigned int hscif2_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
-};
-static const unsigned int hscif2_data_b_mux[] = {
-	HRX2_B_MARK, HTX2_B_MARK,
-};
-static const unsigned int hscif2_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int hscif2_clk_b_mux[] = {
-	HSCK2_B_MARK,
-};
-static const unsigned int hscif2_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
-};
-static const unsigned int hscif2_ctrl_b_mux[] = {
-	HRTS2_N_B_MARK, HCTS2_N_B_MARK,
-};
-
-static const unsigned int hscif2_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
-};
-static const unsigned int hscif2_data_c_mux[] = {
-	HRX2_C_MARK, HTX2_C_MARK,
-};
-static const unsigned int hscif2_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 24),
-};
-static const unsigned int hscif2_clk_c_mux[] = {
-	HSCK2_C_MARK,
-};
-static const unsigned int hscif2_ctrl_c_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
-};
-static const unsigned int hscif2_ctrl_c_mux[] = {
-	HRTS2_N_C_MARK, HCTS2_N_C_MARK,
-};
-/* - HSCIF3 ----------------------------------------------------------------- */
-static const unsigned int hscif3_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
-};
-static const unsigned int hscif3_data_a_mux[] = {
-	HRX3_A_MARK, HTX3_A_MARK,
-};
-static const unsigned int hscif3_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 22),
-};
-static const unsigned int hscif3_clk_mux[] = {
-	HSCK3_MARK,
-};
-static const unsigned int hscif3_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
-};
-static const unsigned int hscif3_ctrl_mux[] = {
-	HRTS3_N_MARK, HCTS3_N_MARK,
-};
-
-static const unsigned int hscif3_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-};
-static const unsigned int hscif3_data_b_mux[] = {
-	HRX3_B_MARK, HTX3_B_MARK,
-};
-static const unsigned int hscif3_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-};
-static const unsigned int hscif3_data_c_mux[] = {
-	HRX3_C_MARK, HTX3_C_MARK,
-};
-static const unsigned int hscif3_data_d_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
-};
-static const unsigned int hscif3_data_d_mux[] = {
-	HRX3_D_MARK, HTX3_D_MARK,
-};
-/* - HSCIF4 ----------------------------------------------------------------- */
-static const unsigned int hscif4_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-};
-static const unsigned int hscif4_data_a_mux[] = {
-	HRX4_A_MARK, HTX4_A_MARK,
-};
-static const unsigned int hscif4_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 11),
-};
-static const unsigned int hscif4_clk_mux[] = {
-	HSCK4_MARK,
-};
-static const unsigned int hscif4_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
-};
-static const unsigned int hscif4_ctrl_mux[] = {
-	HRTS4_N_MARK, HCTS4_N_MARK,
-};
-
-static const unsigned int hscif4_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
-};
-static const unsigned int hscif4_data_b_mux[] = {
-	HRX4_B_MARK, HTX4_B_MARK,
-};
-
-/* - I2C -------------------------------------------------------------------- */
-static const unsigned int i2c0_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
-};
-
-static const unsigned int i2c0_mux[] = {
-	SCL0_MARK, SDA0_MARK,
-};
-
-static const unsigned int i2c1_a_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
-};
-static const unsigned int i2c1_a_mux[] = {
-	SDA1_A_MARK, SCL1_A_MARK,
-};
-static const unsigned int i2c1_b_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
-};
-static const unsigned int i2c1_b_mux[] = {
-	SDA1_B_MARK, SCL1_B_MARK,
-};
-static const unsigned int i2c2_a_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
-};
-static const unsigned int i2c2_a_mux[] = {
-	SDA2_A_MARK, SCL2_A_MARK,
-};
-static const unsigned int i2c2_b_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
-};
-static const unsigned int i2c2_b_mux[] = {
-	SDA2_B_MARK, SCL2_B_MARK,
-};
-
-static const unsigned int i2c3_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
-};
-
-static const unsigned int i2c3_mux[] = {
-	SCL3_MARK, SDA3_MARK,
-};
-
-static const unsigned int i2c5_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
-};
-
-static const unsigned int i2c5_mux[] = {
-	SCL5_MARK, SDA5_MARK,
-};
-
-static const unsigned int i2c6_a_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
-};
-static const unsigned int i2c6_a_mux[] = {
-	SDA6_A_MARK, SCL6_A_MARK,
-};
-static const unsigned int i2c6_b_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
-};
-static const unsigned int i2c6_b_mux[] = {
-	SDA6_B_MARK, SCL6_B_MARK,
-};
-static const unsigned int i2c6_c_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
-};
-static const unsigned int i2c6_c_mux[] = {
-	SDA6_C_MARK, SCL6_C_MARK,
-};
-
-/* - INTC-EX ---------------------------------------------------------------- */
-static const unsigned int intc_ex_irq0_pins[] = {
-	/* IRQ0 */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int intc_ex_irq0_mux[] = {
-	IRQ0_MARK,
-};
-static const unsigned int intc_ex_irq1_pins[] = {
-	/* IRQ1 */
-	RCAR_GP_PIN(2, 1),
-};
-static const unsigned int intc_ex_irq1_mux[] = {
-	IRQ1_MARK,
-};
-static const unsigned int intc_ex_irq2_pins[] = {
-	/* IRQ2 */
-	RCAR_GP_PIN(2, 2),
-};
-static const unsigned int intc_ex_irq2_mux[] = {
-	IRQ2_MARK,
-};
-static const unsigned int intc_ex_irq3_pins[] = {
-	/* IRQ3 */
-	RCAR_GP_PIN(2, 3),
-};
-static const unsigned int intc_ex_irq3_mux[] = {
-	IRQ3_MARK,
-};
-static const unsigned int intc_ex_irq4_pins[] = {
-	/* IRQ4 */
-	RCAR_GP_PIN(2, 4),
-};
-static const unsigned int intc_ex_irq4_mux[] = {
-	IRQ4_MARK,
-};
-static const unsigned int intc_ex_irq5_pins[] = {
-	/* IRQ5 */
-	RCAR_GP_PIN(2, 5),
-};
-static const unsigned int intc_ex_irq5_mux[] = {
-	IRQ5_MARK,
-};
-
-/* - MSIOF0 ----------------------------------------------------------------- */
-static const unsigned int msiof0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 17),
-};
-static const unsigned int msiof0_clk_mux[] = {
-	MSIOF0_SCK_MARK,
-};
-static const unsigned int msiof0_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(5, 18),
-};
-static const unsigned int msiof0_sync_mux[] = {
-	MSIOF0_SYNC_MARK,
-};
-static const unsigned int msiof0_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int msiof0_ss1_mux[] = {
-	MSIOF0_SS1_MARK,
-};
-static const unsigned int msiof0_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(5, 21),
-};
-static const unsigned int msiof0_ss2_mux[] = {
-	MSIOF0_SS2_MARK,
-};
-static const unsigned int msiof0_txd_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(5, 20),
-};
-static const unsigned int msiof0_txd_mux[] = {
-	MSIOF0_TXD_MARK,
-};
-static const unsigned int msiof0_rxd_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 22),
-};
-static const unsigned int msiof0_rxd_mux[] = {
-	MSIOF0_RXD_MARK,
-};
-/* - MSIOF1 ----------------------------------------------------------------- */
-static const unsigned int msiof1_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 8),
-};
-static const unsigned int msiof1_clk_a_mux[] = {
-	MSIOF1_SCK_A_MARK,
-};
-static const unsigned int msiof1_sync_a_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(6, 9),
-};
-static const unsigned int msiof1_sync_a_mux[] = {
-	MSIOF1_SYNC_A_MARK,
-};
-static const unsigned int msiof1_ss1_a_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(6, 5),
-};
-static const unsigned int msiof1_ss1_a_mux[] = {
-	MSIOF1_SS1_A_MARK,
-};
-static const unsigned int msiof1_ss2_a_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(6, 6),
-};
-static const unsigned int msiof1_ss2_a_mux[] = {
-	MSIOF1_SS2_A_MARK,
-};
-static const unsigned int msiof1_txd_a_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(6, 7),
-};
-static const unsigned int msiof1_txd_a_mux[] = {
-	MSIOF1_TXD_A_MARK,
-};
-static const unsigned int msiof1_rxd_a_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(6, 10),
-};
-static const unsigned int msiof1_rxd_a_mux[] = {
-	MSIOF1_RXD_A_MARK,
-};
-static const unsigned int msiof1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 9),
-};
-static const unsigned int msiof1_clk_b_mux[] = {
-	MSIOF1_SCK_B_MARK,
-};
-static const unsigned int msiof1_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(5, 3),
-};
-static const unsigned int msiof1_sync_b_mux[] = {
-	MSIOF1_SYNC_B_MARK,
-};
-static const unsigned int msiof1_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(5, 4),
-};
-static const unsigned int msiof1_ss1_b_mux[] = {
-	MSIOF1_SS1_B_MARK,
-};
-static const unsigned int msiof1_ss2_b_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int msiof1_ss2_b_mux[] = {
-	MSIOF1_SS2_B_MARK,
-};
-static const unsigned int msiof1_txd_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(5, 8),
-};
-static const unsigned int msiof1_txd_b_mux[] = {
-	MSIOF1_TXD_B_MARK,
-};
-static const unsigned int msiof1_rxd_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 7),
-};
-static const unsigned int msiof1_rxd_b_mux[] = {
-	MSIOF1_RXD_B_MARK,
-};
-static const unsigned int msiof1_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 17),
-};
-static const unsigned int msiof1_clk_c_mux[] = {
-	MSIOF1_SCK_C_MARK,
-};
-static const unsigned int msiof1_sync_c_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(6, 18),
-};
-static const unsigned int msiof1_sync_c_mux[] = {
-	MSIOF1_SYNC_C_MARK,
-};
-static const unsigned int msiof1_ss1_c_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int msiof1_ss1_c_mux[] = {
-	MSIOF1_SS1_C_MARK,
-};
-static const unsigned int msiof1_ss2_c_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(6, 27),
-};
-static const unsigned int msiof1_ss2_c_mux[] = {
-	MSIOF1_SS2_C_MARK,
-};
-static const unsigned int msiof1_txd_c_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(6, 20),
-};
-static const unsigned int msiof1_txd_c_mux[] = {
-	MSIOF1_TXD_C_MARK,
-};
-static const unsigned int msiof1_rxd_c_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(6, 19),
-};
-static const unsigned int msiof1_rxd_c_mux[] = {
-	MSIOF1_RXD_C_MARK,
-};
-static const unsigned int msiof1_clk_d_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 12),
-};
-static const unsigned int msiof1_clk_d_mux[] = {
-	MSIOF1_SCK_D_MARK,
-};
-static const unsigned int msiof1_sync_d_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(5, 15),
-};
-static const unsigned int msiof1_sync_d_mux[] = {
-	MSIOF1_SYNC_D_MARK,
-};
-static const unsigned int msiof1_ss1_d_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(5, 16),
-};
-static const unsigned int msiof1_ss1_d_mux[] = {
-	MSIOF1_SS1_D_MARK,
-};
-static const unsigned int msiof1_ss2_d_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(5, 21),
-};
-static const unsigned int msiof1_ss2_d_mux[] = {
-	MSIOF1_SS2_D_MARK,
-};
-static const unsigned int msiof1_txd_d_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(5, 14),
-};
-static const unsigned int msiof1_txd_d_mux[] = {
-	MSIOF1_TXD_D_MARK,
-};
-static const unsigned int msiof1_rxd_d_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 13),
-};
-static const unsigned int msiof1_rxd_d_mux[] = {
-	MSIOF1_RXD_D_MARK,
-};
-static const unsigned int msiof1_clk_e_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 0),
-};
-static const unsigned int msiof1_clk_e_mux[] = {
-	MSIOF1_SCK_E_MARK,
-};
-static const unsigned int msiof1_sync_e_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(3, 1),
-};
-static const unsigned int msiof1_sync_e_mux[] = {
-	MSIOF1_SYNC_E_MARK,
-};
-static const unsigned int msiof1_ss1_e_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(3, 4),
-};
-static const unsigned int msiof1_ss1_e_mux[] = {
-	MSIOF1_SS1_E_MARK,
-};
-static const unsigned int msiof1_ss2_e_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(3, 5),
-};
-static const unsigned int msiof1_ss2_e_mux[] = {
-	MSIOF1_SS2_E_MARK,
-};
-static const unsigned int msiof1_txd_e_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(3, 3),
-};
-static const unsigned int msiof1_txd_e_mux[] = {
-	MSIOF1_TXD_E_MARK,
-};
-static const unsigned int msiof1_rxd_e_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(3, 2),
-};
-static const unsigned int msiof1_rxd_e_mux[] = {
-	MSIOF1_RXD_E_MARK,
-};
-static const unsigned int msiof1_clk_f_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 23),
-};
-static const unsigned int msiof1_clk_f_mux[] = {
-	MSIOF1_SCK_F_MARK,
-};
-static const unsigned int msiof1_sync_f_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(5, 24),
-};
-static const unsigned int msiof1_sync_f_mux[] = {
-	MSIOF1_SYNC_F_MARK,
-};
-static const unsigned int msiof1_ss1_f_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(6, 1),
-};
-static const unsigned int msiof1_ss1_f_mux[] = {
-	MSIOF1_SS1_F_MARK,
-};
-static const unsigned int msiof1_ss2_f_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(6, 2),
-};
-static const unsigned int msiof1_ss2_f_mux[] = {
-	MSIOF1_SS2_F_MARK,
-};
-static const unsigned int msiof1_txd_f_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(6, 0),
-};
-static const unsigned int msiof1_txd_f_mux[] = {
-	MSIOF1_TXD_F_MARK,
-};
-static const unsigned int msiof1_rxd_f_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 25),
-};
-static const unsigned int msiof1_rxd_f_mux[] = {
-	MSIOF1_RXD_F_MARK,
-};
-static const unsigned int msiof1_clk_g_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 6),
-};
-static const unsigned int msiof1_clk_g_mux[] = {
-	MSIOF1_SCK_G_MARK,
-};
-static const unsigned int msiof1_sync_g_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(3, 7),
-};
-static const unsigned int msiof1_sync_g_mux[] = {
-	MSIOF1_SYNC_G_MARK,
-};
-static const unsigned int msiof1_ss1_g_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(3, 10),
-};
-static const unsigned int msiof1_ss1_g_mux[] = {
-	MSIOF1_SS1_G_MARK,
-};
-static const unsigned int msiof1_ss2_g_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(3, 11),
-};
-static const unsigned int msiof1_ss2_g_mux[] = {
-	MSIOF1_SS2_G_MARK,
-};
-static const unsigned int msiof1_txd_g_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(3, 9),
-};
-static const unsigned int msiof1_txd_g_mux[] = {
-	MSIOF1_TXD_G_MARK,
-};
-static const unsigned int msiof1_rxd_g_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(3, 8),
-};
-static const unsigned int msiof1_rxd_g_mux[] = {
-	MSIOF1_RXD_G_MARK,
-};
-/* - MSIOF2 ----------------------------------------------------------------- */
-static const unsigned int msiof2_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 9),
-};
-static const unsigned int msiof2_clk_a_mux[] = {
-	MSIOF2_SCK_A_MARK,
-};
-static const unsigned int msiof2_sync_a_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 8),
-};
-static const unsigned int msiof2_sync_a_mux[] = {
-	MSIOF2_SYNC_A_MARK,
-};
-static const unsigned int msiof2_ss1_a_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(1, 6),
-};
-static const unsigned int msiof2_ss1_a_mux[] = {
-	MSIOF2_SS1_A_MARK,
-};
-static const unsigned int msiof2_ss2_a_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(1, 7),
-};
-static const unsigned int msiof2_ss2_a_mux[] = {
-	MSIOF2_SS2_A_MARK,
-};
-static const unsigned int msiof2_txd_a_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 11),
-};
-static const unsigned int msiof2_txd_a_mux[] = {
-	MSIOF2_TXD_A_MARK,
-};
-static const unsigned int msiof2_rxd_a_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 10),
-};
-static const unsigned int msiof2_rxd_a_mux[] = {
-	MSIOF2_RXD_A_MARK,
-};
-static const unsigned int msiof2_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 4),
-};
-static const unsigned int msiof2_clk_b_mux[] = {
-	MSIOF2_SCK_B_MARK,
-};
-static const unsigned int msiof2_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 5),
-};
-static const unsigned int msiof2_sync_b_mux[] = {
-	MSIOF2_SYNC_B_MARK,
-};
-static const unsigned int msiof2_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 0),
-};
-static const unsigned int msiof2_ss1_b_mux[] = {
-	MSIOF2_SS1_B_MARK,
-};
-static const unsigned int msiof2_ss2_b_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 1),
-};
-static const unsigned int msiof2_ss2_b_mux[] = {
-	MSIOF2_SS2_B_MARK,
-};
-static const unsigned int msiof2_txd_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 7),
-};
-static const unsigned int msiof2_txd_b_mux[] = {
-	MSIOF2_TXD_B_MARK,
-};
-static const unsigned int msiof2_rxd_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 6),
-};
-static const unsigned int msiof2_rxd_b_mux[] = {
-	MSIOF2_RXD_B_MARK,
-};
-static const unsigned int msiof2_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 12),
-};
-static const unsigned int msiof2_clk_c_mux[] = {
-	MSIOF2_SCK_C_MARK,
-};
-static const unsigned int msiof2_sync_c_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(2, 11),
-};
-static const unsigned int msiof2_sync_c_mux[] = {
-	MSIOF2_SYNC_C_MARK,
-};
-static const unsigned int msiof2_ss1_c_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(2, 10),
-};
-static const unsigned int msiof2_ss1_c_mux[] = {
-	MSIOF2_SS1_C_MARK,
-};
-static const unsigned int msiof2_ss2_c_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(2, 9),
-};
-static const unsigned int msiof2_ss2_c_mux[] = {
-	MSIOF2_SS2_C_MARK,
-};
-static const unsigned int msiof2_txd_c_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(2, 14),
-};
-static const unsigned int msiof2_txd_c_mux[] = {
-	MSIOF2_TXD_C_MARK,
-};
-static const unsigned int msiof2_rxd_c_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(2, 13),
-};
-static const unsigned int msiof2_rxd_c_mux[] = {
-	MSIOF2_RXD_C_MARK,
-};
-static const unsigned int msiof2_clk_d_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 8),
-};
-static const unsigned int msiof2_clk_d_mux[] = {
-	MSIOF2_SCK_D_MARK,
-};
-static const unsigned int msiof2_sync_d_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 9),
-};
-static const unsigned int msiof2_sync_d_mux[] = {
-	MSIOF2_SYNC_D_MARK,
-};
-static const unsigned int msiof2_ss1_d_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 12),
-};
-static const unsigned int msiof2_ss1_d_mux[] = {
-	MSIOF2_SS1_D_MARK,
-};
-static const unsigned int msiof2_ss2_d_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 13),
-};
-static const unsigned int msiof2_ss2_d_mux[] = {
-	MSIOF2_SS2_D_MARK,
-};
-static const unsigned int msiof2_txd_d_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 11),
-};
-static const unsigned int msiof2_txd_d_mux[] = {
-	MSIOF2_TXD_D_MARK,
-};
-static const unsigned int msiof2_rxd_d_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 10),
-};
-static const unsigned int msiof2_rxd_d_mux[] = {
-	MSIOF2_RXD_D_MARK,
-};
-/* - MSIOF3 ----------------------------------------------------------------- */
-static const unsigned int msiof3_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 0),
-};
-static const unsigned int msiof3_clk_a_mux[] = {
-	MSIOF3_SCK_A_MARK,
-};
-static const unsigned int msiof3_sync_a_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 1),
-};
-static const unsigned int msiof3_sync_a_mux[] = {
-	MSIOF3_SYNC_A_MARK,
-};
-static const unsigned int msiof3_ss1_a_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 14),
-};
-static const unsigned int msiof3_ss1_a_mux[] = {
-	MSIOF3_SS1_A_MARK,
-};
-static const unsigned int msiof3_ss2_a_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 15),
-};
-static const unsigned int msiof3_ss2_a_mux[] = {
-	MSIOF3_SS2_A_MARK,
-};
-static const unsigned int msiof3_txd_a_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 3),
-};
-static const unsigned int msiof3_txd_a_mux[] = {
-	MSIOF3_TXD_A_MARK,
-};
-static const unsigned int msiof3_rxd_a_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 2),
-};
-static const unsigned int msiof3_rxd_a_mux[] = {
-	MSIOF3_RXD_A_MARK,
-};
-static const unsigned int msiof3_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 2),
-};
-static const unsigned int msiof3_clk_b_mux[] = {
-	MSIOF3_SCK_B_MARK,
-};
-static const unsigned int msiof3_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 0),
-};
-static const unsigned int msiof3_sync_b_mux[] = {
-	MSIOF3_SYNC_B_MARK,
-};
-static const unsigned int msiof3_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(1, 4),
-};
-static const unsigned int msiof3_ss1_b_mux[] = {
-	MSIOF3_SS1_B_MARK,
-};
-static const unsigned int msiof3_ss2_b_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(1, 5),
-};
-static const unsigned int msiof3_ss2_b_mux[] = {
-	MSIOF3_SS2_B_MARK,
-};
-static const unsigned int msiof3_txd_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 1),
-};
-static const unsigned int msiof3_txd_b_mux[] = {
-	MSIOF3_TXD_B_MARK,
-};
-static const unsigned int msiof3_rxd_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 3),
-};
-static const unsigned int msiof3_rxd_b_mux[] = {
-	MSIOF3_RXD_B_MARK,
-};
-static const unsigned int msiof3_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 12),
-};
-static const unsigned int msiof3_clk_c_mux[] = {
-	MSIOF3_SCK_C_MARK,
-};
-static const unsigned int msiof3_sync_c_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 13),
-};
-static const unsigned int msiof3_sync_c_mux[] = {
-	MSIOF3_SYNC_C_MARK,
-};
-static const unsigned int msiof3_txd_c_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 15),
-};
-static const unsigned int msiof3_txd_c_mux[] = {
-	MSIOF3_TXD_C_MARK,
-};
-static const unsigned int msiof3_rxd_c_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 14),
-};
-static const unsigned int msiof3_rxd_c_mux[] = {
-	MSIOF3_RXD_C_MARK,
-};
-static const unsigned int msiof3_clk_d_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 22),
-};
-static const unsigned int msiof3_clk_d_mux[] = {
-	MSIOF3_SCK_D_MARK,
-};
-static const unsigned int msiof3_sync_d_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 23),
-};
-static const unsigned int msiof3_sync_d_mux[] = {
-	MSIOF3_SYNC_D_MARK,
-};
-static const unsigned int msiof3_ss1_d_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(1, 26),
-};
-static const unsigned int msiof3_ss1_d_mux[] = {
-	MSIOF3_SS1_D_MARK,
-};
-static const unsigned int msiof3_txd_d_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 25),
-};
-static const unsigned int msiof3_txd_d_mux[] = {
-	MSIOF3_TXD_D_MARK,
-};
-static const unsigned int msiof3_rxd_d_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 24),
-};
-static const unsigned int msiof3_rxd_d_mux[] = {
-	MSIOF3_RXD_D_MARK,
-};
-static const unsigned int msiof3_clk_e_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 3),
-};
-static const unsigned int msiof3_clk_e_mux[] = {
-	MSIOF3_SCK_E_MARK,
-};
-static const unsigned int msiof3_sync_e_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(2, 2),
-};
-static const unsigned int msiof3_sync_e_mux[] = {
-	MSIOF3_SYNC_E_MARK,
-};
-static const unsigned int msiof3_ss1_e_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(2, 1),
-};
-static const unsigned int msiof3_ss1_e_mux[] = {
-	MSIOF3_SS1_E_MARK,
-};
-static const unsigned int msiof3_ss2_e_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int msiof3_ss2_e_mux[] = {
-	MSIOF3_SS2_E_MARK,
-};
-static const unsigned int msiof3_txd_e_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(2, 5),
-};
-static const unsigned int msiof3_txd_e_mux[] = {
-	MSIOF3_TXD_E_MARK,
-};
-static const unsigned int msiof3_rxd_e_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(2, 4),
-};
-static const unsigned int msiof3_rxd_e_mux[] = {
-	MSIOF3_RXD_E_MARK,
-};
-
-/* - PWM0 --------------------------------------------------------------------*/
-static const unsigned int pwm0_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 6),
-};
-static const unsigned int pwm0_mux[] = {
-	PWM0_MARK,
-};
-/* - PWM1 --------------------------------------------------------------------*/
-static const unsigned int pwm1_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 7),
-};
-static const unsigned int pwm1_a_mux[] = {
-	PWM1_A_MARK,
-};
-static const unsigned int pwm1_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 8),
-};
-static const unsigned int pwm1_b_mux[] = {
-	PWM1_B_MARK,
-};
-/* - PWM2 --------------------------------------------------------------------*/
-static const unsigned int pwm2_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 8),
-};
-static const unsigned int pwm2_a_mux[] = {
-	PWM2_A_MARK,
-};
-static const unsigned int pwm2_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 11),
-};
-static const unsigned int pwm2_b_mux[] = {
-	PWM2_B_MARK,
-};
-/* - PWM3 --------------------------------------------------------------------*/
-static const unsigned int pwm3_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 0),
-};
-static const unsigned int pwm3_a_mux[] = {
-	PWM3_A_MARK,
-};
-static const unsigned int pwm3_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 2),
-};
-static const unsigned int pwm3_b_mux[] = {
-	PWM3_B_MARK,
-};
-/* - PWM4 --------------------------------------------------------------------*/
-static const unsigned int pwm4_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 1),
-};
-static const unsigned int pwm4_a_mux[] = {
-	PWM4_A_MARK,
-};
-static const unsigned int pwm4_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 3),
-};
-static const unsigned int pwm4_b_mux[] = {
-	PWM4_B_MARK,
-};
-/* - PWM5 --------------------------------------------------------------------*/
-static const unsigned int pwm5_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 2),
-};
-static const unsigned int pwm5_a_mux[] = {
-	PWM5_A_MARK,
-};
-static const unsigned int pwm5_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 4),
-};
-static const unsigned int pwm5_b_mux[] = {
-	PWM5_B_MARK,
-};
-/* - PWM6 --------------------------------------------------------------------*/
-static const unsigned int pwm6_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 3),
-};
-static const unsigned int pwm6_a_mux[] = {
-	PWM6_A_MARK,
-};
-static const unsigned int pwm6_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 5),
-};
-static const unsigned int pwm6_b_mux[] = {
-	PWM6_B_MARK,
-};
-
-/* - SATA --------------------------------------------------------------------*/
-static const unsigned int sata0_devslp_a_pins[] = {
-	/* DEVSLP */
-	RCAR_GP_PIN(6, 16),
-};
-static const unsigned int sata0_devslp_a_mux[] = {
-	SATA_DEVSLP_A_MARK,
-};
-static const unsigned int sata0_devslp_b_pins[] = {
-	/* DEVSLP */
-	RCAR_GP_PIN(4, 6),
-};
-static const unsigned int sata0_devslp_b_mux[] = {
-	SATA_DEVSLP_B_MARK,
-};
-
-/* - SCIF0 ------------------------------------------------------------------ */
-static const unsigned int scif0_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-};
-static const unsigned int scif0_data_mux[] = {
-	RX0_MARK, TX0_MARK,
-};
-static const unsigned int scif0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int scif0_clk_mux[] = {
-	SCK0_MARK,
-};
-static const unsigned int scif0_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
-};
-static const unsigned int scif0_ctrl_mux[] = {
-	RTS0_N_MARK, CTS0_N_MARK,
-};
-/* - SCIF1 ------------------------------------------------------------------ */
-static const unsigned int scif1_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
-};
-static const unsigned int scif1_data_a_mux[] = {
-	RX1_A_MARK, TX1_A_MARK,
-};
-static const unsigned int scif1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int scif1_clk_mux[] = {
-	SCK1_MARK,
-};
-static const unsigned int scif1_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
-};
-static const unsigned int scif1_ctrl_mux[] = {
-	RTS1_N_MARK, CTS1_N_MARK,
-};
-
-static const unsigned int scif1_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
-};
-static const unsigned int scif1_data_b_mux[] = {
-	RX1_B_MARK, TX1_B_MARK,
-};
-/* - SCIF2 ------------------------------------------------------------------ */
-static const unsigned int scif2_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
-};
-static const unsigned int scif2_data_a_mux[] = {
-	RX2_A_MARK, TX2_A_MARK,
-};
-static const unsigned int scif2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 9),
-};
-static const unsigned int scif2_clk_mux[] = {
-	SCK2_MARK,
-};
-static const unsigned int scif2_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
-};
-static const unsigned int scif2_data_b_mux[] = {
-	RX2_B_MARK, TX2_B_MARK,
-};
-/* - SCIF3 ------------------------------------------------------------------ */
-static const unsigned int scif3_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
-};
-static const unsigned int scif3_data_a_mux[] = {
-	RX3_A_MARK, TX3_A_MARK,
-};
-static const unsigned int scif3_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 22),
-};
-static const unsigned int scif3_clk_mux[] = {
-	SCK3_MARK,
-};
-static const unsigned int scif3_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
-};
-static const unsigned int scif3_ctrl_mux[] = {
-	RTS3_N_MARK, CTS3_N_MARK,
-};
-static const unsigned int scif3_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
-};
-static const unsigned int scif3_data_b_mux[] = {
-	RX3_B_MARK, TX3_B_MARK,
-};
-/* - SCIF4 ------------------------------------------------------------------ */
-static const unsigned int scif4_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
-};
-static const unsigned int scif4_data_a_mux[] = {
-	RX4_A_MARK, TX4_A_MARK,
-};
-static const unsigned int scif4_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 10),
-};
-static const unsigned int scif4_clk_a_mux[] = {
-	SCK4_A_MARK,
-};
-static const unsigned int scif4_ctrl_a_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
-};
-static const unsigned int scif4_ctrl_a_mux[] = {
-	RTS4_N_A_MARK, CTS4_N_A_MARK,
-};
-static const unsigned int scif4_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-};
-static const unsigned int scif4_data_b_mux[] = {
-	RX4_B_MARK, TX4_B_MARK,
-};
-static const unsigned int scif4_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 5),
-};
-static const unsigned int scif4_clk_b_mux[] = {
-	SCK4_B_MARK,
-};
-static const unsigned int scif4_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
-};
-static const unsigned int scif4_ctrl_b_mux[] = {
-	RTS4_N_B_MARK, CTS4_N_B_MARK,
-};
-static const unsigned int scif4_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-};
-static const unsigned int scif4_data_c_mux[] = {
-	RX4_C_MARK, TX4_C_MARK,
-};
-static const unsigned int scif4_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 8),
-};
-static const unsigned int scif4_clk_c_mux[] = {
-	SCK4_C_MARK,
-};
-static const unsigned int scif4_ctrl_c_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
-};
-static const unsigned int scif4_ctrl_c_mux[] = {
-	RTS4_N_C_MARK, CTS4_N_C_MARK,
-};
-/* - SCIF5 ------------------------------------------------------------------ */
-static const unsigned int scif5_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
-};
-static const unsigned int scif5_data_a_mux[] = {
-	RX5_A_MARK, TX5_A_MARK,
-};
-static const unsigned int scif5_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int scif5_clk_a_mux[] = {
-	SCK5_A_MARK,
-};
-static const unsigned int scif5_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
-};
-static const unsigned int scif5_data_b_mux[] = {
-	RX5_B_MARK, TX5_B_MARK,
-};
-static const unsigned int scif5_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int scif5_clk_b_mux[] = {
-	SCK5_B_MARK,
-};
-
-/* - SCIF Clock ------------------------------------------------------------- */
-static const unsigned int scif_clk_a_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(6, 23),
-};
-static const unsigned int scif_clk_a_mux[] = {
-	SCIF_CLK_A_MARK,
-};
-static const unsigned int scif_clk_b_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(5, 9),
-};
-static const unsigned int scif_clk_b_mux[] = {
-	SCIF_CLK_B_MARK,
-};
-
-/* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 2),
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SD0_DAT0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
-	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
-};
-static const unsigned int sdhi0_data4_mux[] = {
-	SD0_DAT0_MARK, SD0_DAT1_MARK,
-	SD0_DAT2_MARK, SD0_DAT3_MARK,
-};
-static const unsigned int sdhi0_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
-};
-static const unsigned int sdhi0_ctrl_mux[] = {
-	SD0_CLK_MARK, SD0_CMD_MARK,
-};
-static const unsigned int sdhi0_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(3, 12),
-};
-static const unsigned int sdhi0_cd_mux[] = {
-	SD0_CD_MARK,
-};
-static const unsigned int sdhi0_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(3, 13),
-};
-static const unsigned int sdhi0_wp_mux[] = {
-	SD0_WP_MARK,
-};
-/* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 8),
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	SD1_DAT0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-};
-static const unsigned int sdhi1_data4_mux[] = {
-	SD1_DAT0_MARK, SD1_DAT1_MARK,
-	SD1_DAT2_MARK, SD1_DAT3_MARK,
-};
-static const unsigned int sdhi1_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-};
-static const unsigned int sdhi1_ctrl_mux[] = {
-	SD1_CLK_MARK, SD1_CMD_MARK,
-};
-static const unsigned int sdhi1_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(3, 14),
-};
-static const unsigned int sdhi1_cd_mux[] = {
-	SD1_CD_MARK,
-};
-static const unsigned int sdhi1_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(3, 15),
-};
-static const unsigned int sdhi1_wp_mux[] = {
-	SD1_WP_MARK,
-};
-/* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(4, 2),
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SD2_DAT0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-};
-static const unsigned int sdhi2_data4_mux[] = {
-	SD2_DAT0_MARK, SD2_DAT1_MARK,
-	SD2_DAT2_MARK, SD2_DAT3_MARK,
-};
-static const unsigned int sdhi2_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
-	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
-	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-};
-static const unsigned int sdhi2_data8_mux[] = {
-	SD2_DAT0_MARK, SD2_DAT1_MARK,
-	SD2_DAT2_MARK, SD2_DAT3_MARK,
-	SD2_DAT4_MARK, SD2_DAT5_MARK,
-	SD2_DAT6_MARK, SD2_DAT7_MARK,
-};
-static const unsigned int sdhi2_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
-};
-static const unsigned int sdhi2_ctrl_mux[] = {
-	SD2_CLK_MARK, SD2_CMD_MARK,
-};
-static const unsigned int sdhi2_cd_a_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(4, 13),
-};
-static const unsigned int sdhi2_cd_a_mux[] = {
-	SD2_CD_A_MARK,
-};
-static const unsigned int sdhi2_cd_b_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(5, 10),
-};
-static const unsigned int sdhi2_cd_b_mux[] = {
-	SD2_CD_B_MARK,
-};
-static const unsigned int sdhi2_wp_a_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(4, 14),
-};
-static const unsigned int sdhi2_wp_a_mux[] = {
-	SD2_WP_A_MARK,
-};
-static const unsigned int sdhi2_wp_b_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(5, 11),
-};
-static const unsigned int sdhi2_wp_b_mux[] = {
-	SD2_WP_B_MARK,
-};
-static const unsigned int sdhi2_ds_pins[] = {
-	/* DS */
-	RCAR_GP_PIN(4, 6),
-};
-static const unsigned int sdhi2_ds_mux[] = {
-	SD2_DS_MARK,
-};
-/* - SDHI3 ------------------------------------------------------------------ */
-static const unsigned int sdhi3_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(4, 9),
-};
-static const unsigned int sdhi3_data1_mux[] = {
-	SD3_DAT0_MARK,
-};
-static const unsigned int sdhi3_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
-	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
-};
-static const unsigned int sdhi3_data4_mux[] = {
-	SD3_DAT0_MARK, SD3_DAT1_MARK,
-	SD3_DAT2_MARK, SD3_DAT3_MARK,
-};
-static const unsigned int sdhi3_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
-	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
-	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
-	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
-};
-static const unsigned int sdhi3_data8_mux[] = {
-	SD3_DAT0_MARK, SD3_DAT1_MARK,
-	SD3_DAT2_MARK, SD3_DAT3_MARK,
-	SD3_DAT4_MARK, SD3_DAT5_MARK,
-	SD3_DAT6_MARK, SD3_DAT7_MARK,
-};
-static const unsigned int sdhi3_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
-};
-static const unsigned int sdhi3_ctrl_mux[] = {
-	SD3_CLK_MARK, SD3_CMD_MARK,
-};
-static const unsigned int sdhi3_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(4, 15),
-};
-static const unsigned int sdhi3_cd_mux[] = {
-	SD3_CD_MARK,
-};
-static const unsigned int sdhi3_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(4, 16),
-};
-static const unsigned int sdhi3_wp_mux[] = {
-	SD3_WP_MARK,
-};
-static const unsigned int sdhi3_ds_pins[] = {
-	/* DS */
-	RCAR_GP_PIN(4, 17),
-};
-static const unsigned int sdhi3_ds_mux[] = {
-	SD3_DS_MARK,
-};
-
-/* - SSI -------------------------------------------------------------------- */
-static const unsigned int ssi0_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 2),
-};
-static const unsigned int ssi0_data_mux[] = {
-	SSI_SDATA0_MARK,
-};
-static const unsigned int ssi01239_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
-};
-static const unsigned int ssi01239_ctrl_mux[] = {
-	SSI_SCK01239_MARK, SSI_WS01239_MARK,
-};
-static const unsigned int ssi1_data_a_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 3),
-};
-static const unsigned int ssi1_data_a_mux[] = {
-	SSI_SDATA1_A_MARK,
-};
-static const unsigned int ssi1_data_b_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(5, 12),
-};
-static const unsigned int ssi1_data_b_mux[] = {
-	SSI_SDATA1_B_MARK,
-};
-static const unsigned int ssi1_ctrl_a_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
-};
-static const unsigned int ssi1_ctrl_a_mux[] = {
-	SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
-};
-static const unsigned int ssi1_ctrl_b_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
-};
-static const unsigned int ssi1_ctrl_b_mux[] = {
-	SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
-};
-static const unsigned int ssi2_data_a_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 4),
-};
-static const unsigned int ssi2_data_a_mux[] = {
-	SSI_SDATA2_A_MARK,
-};
-static const unsigned int ssi2_data_b_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(5, 13),
-};
-static const unsigned int ssi2_data_b_mux[] = {
-	SSI_SDATA2_B_MARK,
-};
-static const unsigned int ssi2_ctrl_a_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
-};
-static const unsigned int ssi2_ctrl_a_mux[] = {
-	SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
-};
-static const unsigned int ssi2_ctrl_b_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
-};
-static const unsigned int ssi2_ctrl_b_mux[] = {
-	SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
-};
-static const unsigned int ssi3_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 7),
-};
-static const unsigned int ssi3_data_mux[] = {
-	SSI_SDATA3_MARK,
-};
-static const unsigned int ssi349_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
-};
-static const unsigned int ssi349_ctrl_mux[] = {
-	SSI_SCK349_MARK, SSI_WS349_MARK,
-};
-static const unsigned int ssi4_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 10),
-};
-static const unsigned int ssi4_data_mux[] = {
-	SSI_SDATA4_MARK,
-};
-static const unsigned int ssi4_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
-};
-static const unsigned int ssi4_ctrl_mux[] = {
-	SSI_SCK4_MARK, SSI_WS4_MARK,
-};
-static const unsigned int ssi5_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 13),
-};
-static const unsigned int ssi5_data_mux[] = {
-	SSI_SDATA5_MARK,
-};
-static const unsigned int ssi5_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
-};
-static const unsigned int ssi5_ctrl_mux[] = {
-	SSI_SCK5_MARK, SSI_WS5_MARK,
-};
-static const unsigned int ssi6_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 16),
-};
-static const unsigned int ssi6_data_mux[] = {
-	SSI_SDATA6_MARK,
-};
-static const unsigned int ssi6_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
-};
-static const unsigned int ssi6_ctrl_mux[] = {
-	SSI_SCK6_MARK, SSI_WS6_MARK,
-};
-static const unsigned int ssi7_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 19),
-};
-static const unsigned int ssi7_data_mux[] = {
-	SSI_SDATA7_MARK,
-};
-static const unsigned int ssi78_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
-};
-static const unsigned int ssi78_ctrl_mux[] = {
-	SSI_SCK78_MARK, SSI_WS78_MARK,
-};
-static const unsigned int ssi8_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 20),
-};
-static const unsigned int ssi8_data_mux[] = {
-	SSI_SDATA8_MARK,
-};
-static const unsigned int ssi9_data_a_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int ssi9_data_a_mux[] = {
-	SSI_SDATA9_A_MARK,
-};
-static const unsigned int ssi9_data_b_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(5, 14),
-};
-static const unsigned int ssi9_data_b_mux[] = {
-	SSI_SDATA9_B_MARK,
-};
-static const unsigned int ssi9_ctrl_a_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
-};
-static const unsigned int ssi9_ctrl_a_mux[] = {
-	SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
-};
-static const unsigned int ssi9_ctrl_b_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
-};
-static const unsigned int ssi9_ctrl_b_mux[] = {
-	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
-};
-
-/* - TMU -------------------------------------------------------------------- */
-static const unsigned int tmu_tclk1_a_pins[] = {
-	/* TCLK */
-	RCAR_GP_PIN(6, 23),
-};
-static const unsigned int tmu_tclk1_a_mux[] = {
-	TCLK1_A_MARK,
-};
-static const unsigned int tmu_tclk1_b_pins[] = {
-	/* TCLK */
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int tmu_tclk1_b_mux[] = {
-	TCLK1_B_MARK,
-};
-static const unsigned int tmu_tclk2_a_pins[] = {
-	/* TCLK */
-	RCAR_GP_PIN(6, 19),
-};
-static const unsigned int tmu_tclk2_a_mux[] = {
-	TCLK2_A_MARK,
-};
-static const unsigned int tmu_tclk2_b_pins[] = {
-	/* TCLK */
-	RCAR_GP_PIN(6, 28),
-};
-static const unsigned int tmu_tclk2_b_mux[] = {
-	TCLK2_B_MARK,
-};
-
-/* - TPU ------------------------------------------------------------------- */
-static const unsigned int tpu_to0_pins[] = {
-	/* TPU0TO0 */
-	RCAR_GP_PIN(6, 28),
-};
-static const unsigned int tpu_to0_mux[] = {
-	TPU0TO0_MARK,
-};
-static const unsigned int tpu_to1_pins[] = {
-	/* TPU0TO1 */
-	RCAR_GP_PIN(6, 29),
-};
-static const unsigned int tpu_to1_mux[] = {
-	TPU0TO1_MARK,
-};
-static const unsigned int tpu_to2_pins[] = {
-	/* TPU0TO2 */
-	RCAR_GP_PIN(6, 30),
-};
-static const unsigned int tpu_to2_mux[] = {
-	TPU0TO2_MARK,
-};
-static const unsigned int tpu_to3_pins[] = {
-	/* TPU0TO3 */
-	RCAR_GP_PIN(6, 31),
-};
-static const unsigned int tpu_to3_mux[] = {
-	TPU0TO3_MARK,
-};
-
-/* - USB0 ------------------------------------------------------------------- */
-static const unsigned int usb0_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
-};
-static const unsigned int usb0_mux[] = {
-	USB0_PWEN_MARK, USB0_OVC_MARK,
-};
-/* - USB1 ------------------------------------------------------------------- */
-static const unsigned int usb1_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
-};
-static const unsigned int usb1_mux[] = {
-	USB1_PWEN_MARK, USB1_OVC_MARK,
-};
-/* - USB2 ------------------------------------------------------------------- */
-static const unsigned int usb2_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
-};
-static const unsigned int usb2_mux[] = {
-	USB2_PWEN_MARK, USB2_OVC_MARK,
-};
-/* - USB2_CH3 --------------------------------------------------------------- */
-static const unsigned int usb2_ch3_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
-};
-static const unsigned int usb2_ch3_mux[] = {
-	USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
-};
-
-/* - USB30 ------------------------------------------------------------------ */
-static const unsigned int usb30_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
-};
-static const unsigned int usb30_mux[] = {
-	USB30_PWEN_MARK, USB30_OVC_MARK,
-};
-
-/* - VIN4 ------------------------------------------------------------------- */
-static const unsigned int vin4_data18_a_pins[] = {
-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-};
-static const unsigned int vin4_data18_a_mux[] = {
-	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-	VI4_DATA10_MARK, VI4_DATA11_MARK,
-	VI4_DATA12_MARK, VI4_DATA13_MARK,
-	VI4_DATA14_MARK, VI4_DATA15_MARK,
-	VI4_DATA18_MARK, VI4_DATA19_MARK,
-	VI4_DATA20_MARK, VI4_DATA21_MARK,
-	VI4_DATA22_MARK, VI4_DATA23_MARK,
-};
-static const unsigned int vin4_data18_b_pins[] = {
-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-};
-static const unsigned int vin4_data18_b_mux[] = {
-	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
-	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
-	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
-	VI4_DATA10_MARK, VI4_DATA11_MARK,
-	VI4_DATA12_MARK, VI4_DATA13_MARK,
-	VI4_DATA14_MARK, VI4_DATA15_MARK,
-	VI4_DATA18_MARK, VI4_DATA19_MARK,
-	VI4_DATA20_MARK, VI4_DATA21_MARK,
-	VI4_DATA22_MARK, VI4_DATA23_MARK,
-};
-static const union vin_data vin4_data_a_pins = {
-	.data24 = {
-		RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-		RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-		RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-		RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-		RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-	},
-};
-static const union vin_data vin4_data_a_mux = {
-	.data24 = {
-		VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
-		VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-		VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-		VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-		VI4_DATA8_MARK,  VI4_DATA9_MARK,
-		VI4_DATA10_MARK, VI4_DATA11_MARK,
-		VI4_DATA12_MARK, VI4_DATA13_MARK,
-		VI4_DATA14_MARK, VI4_DATA15_MARK,
-		VI4_DATA16_MARK, VI4_DATA17_MARK,
-		VI4_DATA18_MARK, VI4_DATA19_MARK,
-		VI4_DATA20_MARK, VI4_DATA21_MARK,
-		VI4_DATA22_MARK, VI4_DATA23_MARK,
-	},
-};
-static const union vin_data vin4_data_b_pins = {
-	.data24 = {
-		RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-		RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-		RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-		RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-		RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-		RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-	},
-};
-static const union vin_data vin4_data_b_mux = {
-	.data24 = {
-		VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
-		VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
-		VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
-		VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
-		VI4_DATA8_MARK,  VI4_DATA9_MARK,
-		VI4_DATA10_MARK, VI4_DATA11_MARK,
-		VI4_DATA12_MARK, VI4_DATA13_MARK,
-		VI4_DATA14_MARK, VI4_DATA15_MARK,
-		VI4_DATA16_MARK, VI4_DATA17_MARK,
-		VI4_DATA18_MARK, VI4_DATA19_MARK,
-		VI4_DATA20_MARK, VI4_DATA21_MARK,
-		VI4_DATA22_MARK, VI4_DATA23_MARK,
-	},
-};
-static const unsigned int vin4_sync_pins[] = {
-	/* HSYNC#, VSYNC# */
-	RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
-};
-static const unsigned int vin4_sync_mux[] = {
-	VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
-};
-static const unsigned int vin4_field_pins[] = {
-	/* FIELD */
-	RCAR_GP_PIN(1, 16),
-};
-static const unsigned int vin4_field_mux[] = {
-	VI4_FIELD_MARK,
-};
-static const unsigned int vin4_clkenb_pins[] = {
-	/* CLKENB */
-	RCAR_GP_PIN(1, 19),
-};
-static const unsigned int vin4_clkenb_mux[] = {
-	VI4_CLKENB_MARK,
-};
-static const unsigned int vin4_clk_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(1, 27),
-};
-static const unsigned int vin4_clk_mux[] = {
-	VI4_CLK_MARK,
-};
-
-/* - VIN5 ------------------------------------------------------------------- */
-static const union vin_data16 vin5_data_pins = {
-	.data16 = {
-		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-		RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-	},
-};
-static const union vin_data16 vin5_data_mux = {
-	.data16 = {
-		VI5_DATA0_MARK, VI5_DATA1_MARK,
-		VI5_DATA2_MARK, VI5_DATA3_MARK,
-		VI5_DATA4_MARK, VI5_DATA5_MARK,
-		VI5_DATA6_MARK, VI5_DATA7_MARK,
-		VI5_DATA8_MARK,  VI5_DATA9_MARK,
-		VI5_DATA10_MARK, VI5_DATA11_MARK,
-		VI5_DATA12_MARK, VI5_DATA13_MARK,
-		VI5_DATA14_MARK, VI5_DATA15_MARK,
-	},
-};
-static const unsigned int vin5_sync_pins[] = {
-	/* HSYNC#, VSYNC# */
-	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
-};
-static const unsigned int vin5_sync_mux[] = {
-	VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
-};
-static const unsigned int vin5_field_pins[] = {
-	RCAR_GP_PIN(1, 11),
-};
-static const unsigned int vin5_field_mux[] = {
-	/* FIELD */
-	VI5_FIELD_MARK,
-};
-static const unsigned int vin5_clkenb_pins[] = {
-	RCAR_GP_PIN(1, 20),
-};
-static const unsigned int vin5_clkenb_mux[] = {
-	/* CLKENB */
-	VI5_CLKENB_MARK,
-};
-static const unsigned int vin5_clk_pins[] = {
-	RCAR_GP_PIN(1, 21),
-};
-static const unsigned int vin5_clk_mux[] = {
-	/* CLK */
-	VI5_CLK_MARK,
-};
-
-static const struct sh_pfc_pin_group pinmux_groups[] = {
-	SH_PFC_PIN_GROUP(audio_clk_a_a),
-	SH_PFC_PIN_GROUP(audio_clk_a_b),
-	SH_PFC_PIN_GROUP(audio_clk_a_c),
-	SH_PFC_PIN_GROUP(audio_clk_b_a),
-	SH_PFC_PIN_GROUP(audio_clk_b_b),
-	SH_PFC_PIN_GROUP(audio_clk_c_a),
-	SH_PFC_PIN_GROUP(audio_clk_c_b),
-	SH_PFC_PIN_GROUP(audio_clkout_a),
-	SH_PFC_PIN_GROUP(audio_clkout_b),
-	SH_PFC_PIN_GROUP(audio_clkout_c),
-	SH_PFC_PIN_GROUP(audio_clkout_d),
-	SH_PFC_PIN_GROUP(audio_clkout1_a),
-	SH_PFC_PIN_GROUP(audio_clkout1_b),
-	SH_PFC_PIN_GROUP(audio_clkout2_a),
-	SH_PFC_PIN_GROUP(audio_clkout2_b),
-	SH_PFC_PIN_GROUP(audio_clkout3_a),
-	SH_PFC_PIN_GROUP(audio_clkout3_b),
-	SH_PFC_PIN_GROUP(avb_link),
-	SH_PFC_PIN_GROUP(avb_magic),
-	SH_PFC_PIN_GROUP(avb_phy_int),
-	SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),	/* Deprecated */
-	SH_PFC_PIN_GROUP(avb_mdio),
-	SH_PFC_PIN_GROUP(avb_mii),
-	SH_PFC_PIN_GROUP(avb_avtp_pps),
-	SH_PFC_PIN_GROUP(avb_avtp_match_a),
-	SH_PFC_PIN_GROUP(avb_avtp_capture_a),
-	SH_PFC_PIN_GROUP(avb_avtp_match_b),
-	SH_PFC_PIN_GROUP(avb_avtp_capture_b),
-	SH_PFC_PIN_GROUP(can0_data_a),
-	SH_PFC_PIN_GROUP(can0_data_b),
-	SH_PFC_PIN_GROUP(can1_data),
-	SH_PFC_PIN_GROUP(can_clk),
-	SH_PFC_PIN_GROUP(canfd0_data_a),
-	SH_PFC_PIN_GROUP(canfd0_data_b),
-	SH_PFC_PIN_GROUP(canfd1_data),
-	SH_PFC_PIN_GROUP(drif0_ctrl_a),
-	SH_PFC_PIN_GROUP(drif0_data0_a),
-	SH_PFC_PIN_GROUP(drif0_data1_a),
-	SH_PFC_PIN_GROUP(drif0_ctrl_b),
-	SH_PFC_PIN_GROUP(drif0_data0_b),
-	SH_PFC_PIN_GROUP(drif0_data1_b),
-	SH_PFC_PIN_GROUP(drif0_ctrl_c),
-	SH_PFC_PIN_GROUP(drif0_data0_c),
-	SH_PFC_PIN_GROUP(drif0_data1_c),
-	SH_PFC_PIN_GROUP(drif1_ctrl_a),
-	SH_PFC_PIN_GROUP(drif1_data0_a),
-	SH_PFC_PIN_GROUP(drif1_data1_a),
-	SH_PFC_PIN_GROUP(drif1_ctrl_b),
-	SH_PFC_PIN_GROUP(drif1_data0_b),
-	SH_PFC_PIN_GROUP(drif1_data1_b),
-	SH_PFC_PIN_GROUP(drif1_ctrl_c),
-	SH_PFC_PIN_GROUP(drif1_data0_c),
-	SH_PFC_PIN_GROUP(drif1_data1_c),
-	SH_PFC_PIN_GROUP(drif2_ctrl_a),
-	SH_PFC_PIN_GROUP(drif2_data0_a),
-	SH_PFC_PIN_GROUP(drif2_data1_a),
-	SH_PFC_PIN_GROUP(drif2_ctrl_b),
-	SH_PFC_PIN_GROUP(drif2_data0_b),
-	SH_PFC_PIN_GROUP(drif2_data1_b),
-	SH_PFC_PIN_GROUP(drif3_ctrl_a),
-	SH_PFC_PIN_GROUP(drif3_data0_a),
-	SH_PFC_PIN_GROUP(drif3_data1_a),
-	SH_PFC_PIN_GROUP(drif3_ctrl_b),
-	SH_PFC_PIN_GROUP(drif3_data0_b),
-	SH_PFC_PIN_GROUP(drif3_data1_b),
-	SH_PFC_PIN_GROUP(du_rgb666),
-	SH_PFC_PIN_GROUP(du_rgb888),
-	SH_PFC_PIN_GROUP(du_clk_out_0),
-	SH_PFC_PIN_GROUP(du_clk_out_1),
-	SH_PFC_PIN_GROUP(du_sync),
-	SH_PFC_PIN_GROUP(du_oddf),
-	SH_PFC_PIN_GROUP(du_cde),
-	SH_PFC_PIN_GROUP(du_disp),
-	SH_PFC_PIN_GROUP(hscif0_data),
-	SH_PFC_PIN_GROUP(hscif0_clk),
-	SH_PFC_PIN_GROUP(hscif0_ctrl),
-	SH_PFC_PIN_GROUP(hscif1_data_a),
-	SH_PFC_PIN_GROUP(hscif1_clk_a),
-	SH_PFC_PIN_GROUP(hscif1_ctrl_a),
-	SH_PFC_PIN_GROUP(hscif1_data_b),
-	SH_PFC_PIN_GROUP(hscif1_clk_b),
-	SH_PFC_PIN_GROUP(hscif1_ctrl_b),
-	SH_PFC_PIN_GROUP(hscif2_data_a),
-	SH_PFC_PIN_GROUP(hscif2_clk_a),
-	SH_PFC_PIN_GROUP(hscif2_ctrl_a),
-	SH_PFC_PIN_GROUP(hscif2_data_b),
-	SH_PFC_PIN_GROUP(hscif2_clk_b),
-	SH_PFC_PIN_GROUP(hscif2_ctrl_b),
-	SH_PFC_PIN_GROUP(hscif2_data_c),
-	SH_PFC_PIN_GROUP(hscif2_clk_c),
-	SH_PFC_PIN_GROUP(hscif2_ctrl_c),
-	SH_PFC_PIN_GROUP(hscif3_data_a),
-	SH_PFC_PIN_GROUP(hscif3_clk),
-	SH_PFC_PIN_GROUP(hscif3_ctrl),
-	SH_PFC_PIN_GROUP(hscif3_data_b),
-	SH_PFC_PIN_GROUP(hscif3_data_c),
-	SH_PFC_PIN_GROUP(hscif3_data_d),
-	SH_PFC_PIN_GROUP(hscif4_data_a),
-	SH_PFC_PIN_GROUP(hscif4_clk),
-	SH_PFC_PIN_GROUP(hscif4_ctrl),
-	SH_PFC_PIN_GROUP(hscif4_data_b),
-	SH_PFC_PIN_GROUP(i2c0),
-	SH_PFC_PIN_GROUP(i2c1_a),
-	SH_PFC_PIN_GROUP(i2c1_b),
-	SH_PFC_PIN_GROUP(i2c2_a),
-	SH_PFC_PIN_GROUP(i2c2_b),
-	SH_PFC_PIN_GROUP(i2c3),
-	SH_PFC_PIN_GROUP(i2c5),
-	SH_PFC_PIN_GROUP(i2c6_a),
-	SH_PFC_PIN_GROUP(i2c6_b),
-	SH_PFC_PIN_GROUP(i2c6_c),
-	SH_PFC_PIN_GROUP(intc_ex_irq0),
-	SH_PFC_PIN_GROUP(intc_ex_irq1),
-	SH_PFC_PIN_GROUP(intc_ex_irq2),
-	SH_PFC_PIN_GROUP(intc_ex_irq3),
-	SH_PFC_PIN_GROUP(intc_ex_irq4),
-	SH_PFC_PIN_GROUP(intc_ex_irq5),
-	SH_PFC_PIN_GROUP(msiof0_clk),
-	SH_PFC_PIN_GROUP(msiof0_sync),
-	SH_PFC_PIN_GROUP(msiof0_ss1),
-	SH_PFC_PIN_GROUP(msiof0_ss2),
-	SH_PFC_PIN_GROUP(msiof0_txd),
-	SH_PFC_PIN_GROUP(msiof0_rxd),
-	SH_PFC_PIN_GROUP(msiof1_clk_a),
-	SH_PFC_PIN_GROUP(msiof1_sync_a),
-	SH_PFC_PIN_GROUP(msiof1_ss1_a),
-	SH_PFC_PIN_GROUP(msiof1_ss2_a),
-	SH_PFC_PIN_GROUP(msiof1_txd_a),
-	SH_PFC_PIN_GROUP(msiof1_rxd_a),
-	SH_PFC_PIN_GROUP(msiof1_clk_b),
-	SH_PFC_PIN_GROUP(msiof1_sync_b),
-	SH_PFC_PIN_GROUP(msiof1_ss1_b),
-	SH_PFC_PIN_GROUP(msiof1_ss2_b),
-	SH_PFC_PIN_GROUP(msiof1_txd_b),
-	SH_PFC_PIN_GROUP(msiof1_rxd_b),
-	SH_PFC_PIN_GROUP(msiof1_clk_c),
-	SH_PFC_PIN_GROUP(msiof1_sync_c),
-	SH_PFC_PIN_GROUP(msiof1_ss1_c),
-	SH_PFC_PIN_GROUP(msiof1_ss2_c),
-	SH_PFC_PIN_GROUP(msiof1_txd_c),
-	SH_PFC_PIN_GROUP(msiof1_rxd_c),
-	SH_PFC_PIN_GROUP(msiof1_clk_d),
-	SH_PFC_PIN_GROUP(msiof1_sync_d),
-	SH_PFC_PIN_GROUP(msiof1_ss1_d),
-	SH_PFC_PIN_GROUP(msiof1_ss2_d),
-	SH_PFC_PIN_GROUP(msiof1_txd_d),
-	SH_PFC_PIN_GROUP(msiof1_rxd_d),
-	SH_PFC_PIN_GROUP(msiof1_clk_e),
-	SH_PFC_PIN_GROUP(msiof1_sync_e),
-	SH_PFC_PIN_GROUP(msiof1_ss1_e),
-	SH_PFC_PIN_GROUP(msiof1_ss2_e),
-	SH_PFC_PIN_GROUP(msiof1_txd_e),
-	SH_PFC_PIN_GROUP(msiof1_rxd_e),
-	SH_PFC_PIN_GROUP(msiof1_clk_f),
-	SH_PFC_PIN_GROUP(msiof1_sync_f),
-	SH_PFC_PIN_GROUP(msiof1_ss1_f),
-	SH_PFC_PIN_GROUP(msiof1_ss2_f),
-	SH_PFC_PIN_GROUP(msiof1_txd_f),
-	SH_PFC_PIN_GROUP(msiof1_rxd_f),
-	SH_PFC_PIN_GROUP(msiof1_clk_g),
-	SH_PFC_PIN_GROUP(msiof1_sync_g),
-	SH_PFC_PIN_GROUP(msiof1_ss1_g),
-	SH_PFC_PIN_GROUP(msiof1_ss2_g),
-	SH_PFC_PIN_GROUP(msiof1_txd_g),
-	SH_PFC_PIN_GROUP(msiof1_rxd_g),
-	SH_PFC_PIN_GROUP(msiof2_clk_a),
-	SH_PFC_PIN_GROUP(msiof2_sync_a),
-	SH_PFC_PIN_GROUP(msiof2_ss1_a),
-	SH_PFC_PIN_GROUP(msiof2_ss2_a),
-	SH_PFC_PIN_GROUP(msiof2_txd_a),
-	SH_PFC_PIN_GROUP(msiof2_rxd_a),
-	SH_PFC_PIN_GROUP(msiof2_clk_b),
-	SH_PFC_PIN_GROUP(msiof2_sync_b),
-	SH_PFC_PIN_GROUP(msiof2_ss1_b),
-	SH_PFC_PIN_GROUP(msiof2_ss2_b),
-	SH_PFC_PIN_GROUP(msiof2_txd_b),
-	SH_PFC_PIN_GROUP(msiof2_rxd_b),
-	SH_PFC_PIN_GROUP(msiof2_clk_c),
-	SH_PFC_PIN_GROUP(msiof2_sync_c),
-	SH_PFC_PIN_GROUP(msiof2_ss1_c),
-	SH_PFC_PIN_GROUP(msiof2_ss2_c),
-	SH_PFC_PIN_GROUP(msiof2_txd_c),
-	SH_PFC_PIN_GROUP(msiof2_rxd_c),
-	SH_PFC_PIN_GROUP(msiof2_clk_d),
-	SH_PFC_PIN_GROUP(msiof2_sync_d),
-	SH_PFC_PIN_GROUP(msiof2_ss1_d),
-	SH_PFC_PIN_GROUP(msiof2_ss2_d),
-	SH_PFC_PIN_GROUP(msiof2_txd_d),
-	SH_PFC_PIN_GROUP(msiof2_rxd_d),
-	SH_PFC_PIN_GROUP(msiof3_clk_a),
-	SH_PFC_PIN_GROUP(msiof3_sync_a),
-	SH_PFC_PIN_GROUP(msiof3_ss1_a),
-	SH_PFC_PIN_GROUP(msiof3_ss2_a),
-	SH_PFC_PIN_GROUP(msiof3_txd_a),
-	SH_PFC_PIN_GROUP(msiof3_rxd_a),
-	SH_PFC_PIN_GROUP(msiof3_clk_b),
-	SH_PFC_PIN_GROUP(msiof3_sync_b),
-	SH_PFC_PIN_GROUP(msiof3_ss1_b),
-	SH_PFC_PIN_GROUP(msiof3_ss2_b),
-	SH_PFC_PIN_GROUP(msiof3_txd_b),
-	SH_PFC_PIN_GROUP(msiof3_rxd_b),
-	SH_PFC_PIN_GROUP(msiof3_clk_c),
-	SH_PFC_PIN_GROUP(msiof3_sync_c),
-	SH_PFC_PIN_GROUP(msiof3_txd_c),
-	SH_PFC_PIN_GROUP(msiof3_rxd_c),
-	SH_PFC_PIN_GROUP(msiof3_clk_d),
-	SH_PFC_PIN_GROUP(msiof3_sync_d),
-	SH_PFC_PIN_GROUP(msiof3_ss1_d),
-	SH_PFC_PIN_GROUP(msiof3_txd_d),
-	SH_PFC_PIN_GROUP(msiof3_rxd_d),
-	SH_PFC_PIN_GROUP(msiof3_clk_e),
-	SH_PFC_PIN_GROUP(msiof3_sync_e),
-	SH_PFC_PIN_GROUP(msiof3_ss1_e),
-	SH_PFC_PIN_GROUP(msiof3_ss2_e),
-	SH_PFC_PIN_GROUP(msiof3_txd_e),
-	SH_PFC_PIN_GROUP(msiof3_rxd_e),
-	SH_PFC_PIN_GROUP(pwm0),
-	SH_PFC_PIN_GROUP(pwm1_a),
-	SH_PFC_PIN_GROUP(pwm1_b),
-	SH_PFC_PIN_GROUP(pwm2_a),
-	SH_PFC_PIN_GROUP(pwm2_b),
-	SH_PFC_PIN_GROUP(pwm3_a),
-	SH_PFC_PIN_GROUP(pwm3_b),
-	SH_PFC_PIN_GROUP(pwm4_a),
-	SH_PFC_PIN_GROUP(pwm4_b),
-	SH_PFC_PIN_GROUP(pwm5_a),
-	SH_PFC_PIN_GROUP(pwm5_b),
-	SH_PFC_PIN_GROUP(pwm6_a),
-	SH_PFC_PIN_GROUP(pwm6_b),
-	SH_PFC_PIN_GROUP(sata0_devslp_a),
-	SH_PFC_PIN_GROUP(sata0_devslp_b),
-	SH_PFC_PIN_GROUP(scif0_data),
-	SH_PFC_PIN_GROUP(scif0_clk),
-	SH_PFC_PIN_GROUP(scif0_ctrl),
-	SH_PFC_PIN_GROUP(scif1_data_a),
-	SH_PFC_PIN_GROUP(scif1_clk),
-	SH_PFC_PIN_GROUP(scif1_ctrl),
-	SH_PFC_PIN_GROUP(scif1_data_b),
-	SH_PFC_PIN_GROUP(scif2_data_a),
-	SH_PFC_PIN_GROUP(scif2_clk),
-	SH_PFC_PIN_GROUP(scif2_data_b),
-	SH_PFC_PIN_GROUP(scif3_data_a),
-	SH_PFC_PIN_GROUP(scif3_clk),
-	SH_PFC_PIN_GROUP(scif3_ctrl),
-	SH_PFC_PIN_GROUP(scif3_data_b),
-	SH_PFC_PIN_GROUP(scif4_data_a),
-	SH_PFC_PIN_GROUP(scif4_clk_a),
-	SH_PFC_PIN_GROUP(scif4_ctrl_a),
-	SH_PFC_PIN_GROUP(scif4_data_b),
-	SH_PFC_PIN_GROUP(scif4_clk_b),
-	SH_PFC_PIN_GROUP(scif4_ctrl_b),
-	SH_PFC_PIN_GROUP(scif4_data_c),
-	SH_PFC_PIN_GROUP(scif4_clk_c),
-	SH_PFC_PIN_GROUP(scif4_ctrl_c),
-	SH_PFC_PIN_GROUP(scif5_data_a),
-	SH_PFC_PIN_GROUP(scif5_clk_a),
-	SH_PFC_PIN_GROUP(scif5_data_b),
-	SH_PFC_PIN_GROUP(scif5_clk_b),
-	SH_PFC_PIN_GROUP(scif_clk_a),
-	SH_PFC_PIN_GROUP(scif_clk_b),
-	SH_PFC_PIN_GROUP(sdhi0_data1),
-	SH_PFC_PIN_GROUP(sdhi0_data4),
-	SH_PFC_PIN_GROUP(sdhi0_ctrl),
-	SH_PFC_PIN_GROUP(sdhi0_cd),
-	SH_PFC_PIN_GROUP(sdhi0_wp),
-	SH_PFC_PIN_GROUP(sdhi1_data1),
-	SH_PFC_PIN_GROUP(sdhi1_data4),
-	SH_PFC_PIN_GROUP(sdhi1_ctrl),
-	SH_PFC_PIN_GROUP(sdhi1_cd),
-	SH_PFC_PIN_GROUP(sdhi1_wp),
-	SH_PFC_PIN_GROUP(sdhi2_data1),
-	SH_PFC_PIN_GROUP(sdhi2_data4),
-	SH_PFC_PIN_GROUP(sdhi2_data8),
-	SH_PFC_PIN_GROUP(sdhi2_ctrl),
-	SH_PFC_PIN_GROUP(sdhi2_cd_a),
-	SH_PFC_PIN_GROUP(sdhi2_wp_a),
-	SH_PFC_PIN_GROUP(sdhi2_cd_b),
-	SH_PFC_PIN_GROUP(sdhi2_wp_b),
-	SH_PFC_PIN_GROUP(sdhi2_ds),
-	SH_PFC_PIN_GROUP(sdhi3_data1),
-	SH_PFC_PIN_GROUP(sdhi3_data4),
-	SH_PFC_PIN_GROUP(sdhi3_data8),
-	SH_PFC_PIN_GROUP(sdhi3_ctrl),
-	SH_PFC_PIN_GROUP(sdhi3_cd),
-	SH_PFC_PIN_GROUP(sdhi3_wp),
-	SH_PFC_PIN_GROUP(sdhi3_ds),
-	SH_PFC_PIN_GROUP(ssi0_data),
-	SH_PFC_PIN_GROUP(ssi01239_ctrl),
-	SH_PFC_PIN_GROUP(ssi1_data_a),
-	SH_PFC_PIN_GROUP(ssi1_data_b),
-	SH_PFC_PIN_GROUP(ssi1_ctrl_a),
-	SH_PFC_PIN_GROUP(ssi1_ctrl_b),
-	SH_PFC_PIN_GROUP(ssi2_data_a),
-	SH_PFC_PIN_GROUP(ssi2_data_b),
-	SH_PFC_PIN_GROUP(ssi2_ctrl_a),
-	SH_PFC_PIN_GROUP(ssi2_ctrl_b),
-	SH_PFC_PIN_GROUP(ssi3_data),
-	SH_PFC_PIN_GROUP(ssi349_ctrl),
-	SH_PFC_PIN_GROUP(ssi4_data),
-	SH_PFC_PIN_GROUP(ssi4_ctrl),
-	SH_PFC_PIN_GROUP(ssi5_data),
-	SH_PFC_PIN_GROUP(ssi5_ctrl),
-	SH_PFC_PIN_GROUP(ssi6_data),
-	SH_PFC_PIN_GROUP(ssi6_ctrl),
-	SH_PFC_PIN_GROUP(ssi7_data),
-	SH_PFC_PIN_GROUP(ssi78_ctrl),
-	SH_PFC_PIN_GROUP(ssi8_data),
-	SH_PFC_PIN_GROUP(ssi9_data_a),
-	SH_PFC_PIN_GROUP(ssi9_data_b),
-	SH_PFC_PIN_GROUP(ssi9_ctrl_a),
-	SH_PFC_PIN_GROUP(ssi9_ctrl_b),
-	SH_PFC_PIN_GROUP(tmu_tclk1_a),
-	SH_PFC_PIN_GROUP(tmu_tclk1_b),
-	SH_PFC_PIN_GROUP(tmu_tclk2_a),
-	SH_PFC_PIN_GROUP(tmu_tclk2_b),
-	SH_PFC_PIN_GROUP(tpu_to0),
-	SH_PFC_PIN_GROUP(tpu_to1),
-	SH_PFC_PIN_GROUP(tpu_to2),
-	SH_PFC_PIN_GROUP(tpu_to3),
-	SH_PFC_PIN_GROUP(usb0),
-	SH_PFC_PIN_GROUP(usb1),
-	SH_PFC_PIN_GROUP(usb2),
-	SH_PFC_PIN_GROUP(usb2_ch3),
-	SH_PFC_PIN_GROUP(usb30),
-	VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
-	VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
-	VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
-	VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
-	SH_PFC_PIN_GROUP(vin4_data18_a),
-	VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
-	VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
-	VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
-	VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
-	VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
-	VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
-	SH_PFC_PIN_GROUP(vin4_data18_b),
-	VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
-	VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
-	SH_PFC_PIN_GROUP(vin4_sync),
-	SH_PFC_PIN_GROUP(vin4_field),
-	SH_PFC_PIN_GROUP(vin4_clkenb),
-	SH_PFC_PIN_GROUP(vin4_clk),
-	VIN_DATA_PIN_GROUP(vin5_data, 8),
-	VIN_DATA_PIN_GROUP(vin5_data, 10),
-	VIN_DATA_PIN_GROUP(vin5_data, 12),
-	VIN_DATA_PIN_GROUP(vin5_data, 16),
-	SH_PFC_PIN_GROUP(vin5_sync),
-	SH_PFC_PIN_GROUP(vin5_field),
-	SH_PFC_PIN_GROUP(vin5_clkenb),
-	SH_PFC_PIN_GROUP(vin5_clk),
-};
-
-static const char * const audio_clk_groups[] = {
-	"audio_clk_a_a",
-	"audio_clk_a_b",
-	"audio_clk_a_c",
-	"audio_clk_b_a",
-	"audio_clk_b_b",
-	"audio_clk_c_a",
-	"audio_clk_c_b",
-	"audio_clkout_a",
-	"audio_clkout_b",
-	"audio_clkout_c",
-	"audio_clkout_d",
-	"audio_clkout1_a",
-	"audio_clkout1_b",
-	"audio_clkout2_a",
-	"audio_clkout2_b",
-	"audio_clkout3_a",
-	"audio_clkout3_b",
-};
-
-static const char * const avb_groups[] = {
-	"avb_link",
-	"avb_magic",
-	"avb_phy_int",
-	"avb_mdc",	/* Deprecated, please use "avb_mdio" instead */
-	"avb_mdio",
-	"avb_mii",
-	"avb_avtp_pps",
-	"avb_avtp_match_a",
-	"avb_avtp_capture_a",
-	"avb_avtp_match_b",
-	"avb_avtp_capture_b",
-};
-
-static const char * const can0_groups[] = {
-	"can0_data_a",
-	"can0_data_b",
-};
-
-static const char * const can1_groups[] = {
-	"can1_data",
-};
-
-static const char * const can_clk_groups[] = {
-	"can_clk",
-};
-
-static const char * const canfd0_groups[] = {
-	"canfd0_data_a",
-	"canfd0_data_b",
-};
-
-static const char * const canfd1_groups[] = {
-	"canfd1_data",
-};
-
-static const char * const drif0_groups[] = {
-	"drif0_ctrl_a",
-	"drif0_data0_a",
-	"drif0_data1_a",
-	"drif0_ctrl_b",
-	"drif0_data0_b",
-	"drif0_data1_b",
-	"drif0_ctrl_c",
-	"drif0_data0_c",
-	"drif0_data1_c",
-};
-
-static const char * const drif1_groups[] = {
-	"drif1_ctrl_a",
-	"drif1_data0_a",
-	"drif1_data1_a",
-	"drif1_ctrl_b",
-	"drif1_data0_b",
-	"drif1_data1_b",
-	"drif1_ctrl_c",
-	"drif1_data0_c",
-	"drif1_data1_c",
-};
-
-static const char * const drif2_groups[] = {
-	"drif2_ctrl_a",
-	"drif2_data0_a",
-	"drif2_data1_a",
-	"drif2_ctrl_b",
-	"drif2_data0_b",
-	"drif2_data1_b",
-};
-
-static const char * const drif3_groups[] = {
-	"drif3_ctrl_a",
-	"drif3_data0_a",
-	"drif3_data1_a",
-	"drif3_ctrl_b",
-	"drif3_data0_b",
-	"drif3_data1_b",
-};
-
-static const char * const du_groups[] = {
-	"du_rgb666",
-	"du_rgb888",
-	"du_clk_out_0",
-	"du_clk_out_1",
-	"du_sync",
-	"du_oddf",
-	"du_cde",
-	"du_disp",
-};
-
-static const char * const hscif0_groups[] = {
-	"hscif0_data",
-	"hscif0_clk",
-	"hscif0_ctrl",
-};
-
-static const char * const hscif1_groups[] = {
-	"hscif1_data_a",
-	"hscif1_clk_a",
-	"hscif1_ctrl_a",
-	"hscif1_data_b",
-	"hscif1_clk_b",
-	"hscif1_ctrl_b",
-};
-
-static const char * const hscif2_groups[] = {
-	"hscif2_data_a",
-	"hscif2_clk_a",
-	"hscif2_ctrl_a",
-	"hscif2_data_b",
-	"hscif2_clk_b",
-	"hscif2_ctrl_b",
-	"hscif2_data_c",
-	"hscif2_clk_c",
-	"hscif2_ctrl_c",
-};
-
-static const char * const hscif3_groups[] = {
-	"hscif3_data_a",
-	"hscif3_clk",
-	"hscif3_ctrl",
-	"hscif3_data_b",
-	"hscif3_data_c",
-	"hscif3_data_d",
-};
-
-static const char * const hscif4_groups[] = {
-	"hscif4_data_a",
-	"hscif4_clk",
-	"hscif4_ctrl",
-	"hscif4_data_b",
-};
-
-static const char * const i2c0_groups[] = {
-	"i2c0",
-};
-
-static const char * const i2c1_groups[] = {
-	"i2c1_a",
-	"i2c1_b",
-};
-
-static const char * const i2c2_groups[] = {
-	"i2c2_a",
-	"i2c2_b",
-};
-
-static const char * const i2c3_groups[] = {
-	"i2c3",
-};
-
-static const char * const i2c5_groups[] = {
-	"i2c5",
-};
-
-static const char * const i2c6_groups[] = {
-	"i2c6_a",
-	"i2c6_b",
-	"i2c6_c",
-};
-
-static const char * const intc_ex_groups[] = {
-	"intc_ex_irq0",
-	"intc_ex_irq1",
-	"intc_ex_irq2",
-	"intc_ex_irq3",
-	"intc_ex_irq4",
-	"intc_ex_irq5",
-};
-
-static const char * const msiof0_groups[] = {
-	"msiof0_clk",
-	"msiof0_sync",
-	"msiof0_ss1",
-	"msiof0_ss2",
-	"msiof0_txd",
-	"msiof0_rxd",
-};
-
-static const char * const msiof1_groups[] = {
-	"msiof1_clk_a",
-	"msiof1_sync_a",
-	"msiof1_ss1_a",
-	"msiof1_ss2_a",
-	"msiof1_txd_a",
-	"msiof1_rxd_a",
-	"msiof1_clk_b",
-	"msiof1_sync_b",
-	"msiof1_ss1_b",
-	"msiof1_ss2_b",
-	"msiof1_txd_b",
-	"msiof1_rxd_b",
-	"msiof1_clk_c",
-	"msiof1_sync_c",
-	"msiof1_ss1_c",
-	"msiof1_ss2_c",
-	"msiof1_txd_c",
-	"msiof1_rxd_c",
-	"msiof1_clk_d",
-	"msiof1_sync_d",
-	"msiof1_ss1_d",
-	"msiof1_ss2_d",
-	"msiof1_txd_d",
-	"msiof1_rxd_d",
-	"msiof1_clk_e",
-	"msiof1_sync_e",
-	"msiof1_ss1_e",
-	"msiof1_ss2_e",
-	"msiof1_txd_e",
-	"msiof1_rxd_e",
-	"msiof1_clk_f",
-	"msiof1_sync_f",
-	"msiof1_ss1_f",
-	"msiof1_ss2_f",
-	"msiof1_txd_f",
-	"msiof1_rxd_f",
-	"msiof1_clk_g",
-	"msiof1_sync_g",
-	"msiof1_ss1_g",
-	"msiof1_ss2_g",
-	"msiof1_txd_g",
-	"msiof1_rxd_g",
-};
-
-static const char * const msiof2_groups[] = {
-	"msiof2_clk_a",
-	"msiof2_sync_a",
-	"msiof2_ss1_a",
-	"msiof2_ss2_a",
-	"msiof2_txd_a",
-	"msiof2_rxd_a",
-	"msiof2_clk_b",
-	"msiof2_sync_b",
-	"msiof2_ss1_b",
-	"msiof2_ss2_b",
-	"msiof2_txd_b",
-	"msiof2_rxd_b",
-	"msiof2_clk_c",
-	"msiof2_sync_c",
-	"msiof2_ss1_c",
-	"msiof2_ss2_c",
-	"msiof2_txd_c",
-	"msiof2_rxd_c",
-	"msiof2_clk_d",
-	"msiof2_sync_d",
-	"msiof2_ss1_d",
-	"msiof2_ss2_d",
-	"msiof2_txd_d",
-	"msiof2_rxd_d",
-};
-
-static const char * const msiof3_groups[] = {
-	"msiof3_clk_a",
-	"msiof3_sync_a",
-	"msiof3_ss1_a",
-	"msiof3_ss2_a",
-	"msiof3_txd_a",
-	"msiof3_rxd_a",
-	"msiof3_clk_b",
-	"msiof3_sync_b",
-	"msiof3_ss1_b",
-	"msiof3_ss2_b",
-	"msiof3_txd_b",
-	"msiof3_rxd_b",
-	"msiof3_clk_c",
-	"msiof3_sync_c",
-	"msiof3_txd_c",
-	"msiof3_rxd_c",
-	"msiof3_clk_d",
-	"msiof3_sync_d",
-	"msiof3_ss1_d",
-	"msiof3_txd_d",
-	"msiof3_rxd_d",
-	"msiof3_clk_e",
-	"msiof3_sync_e",
-	"msiof3_ss1_e",
-	"msiof3_ss2_e",
-	"msiof3_txd_e",
-	"msiof3_rxd_e",
-};
-
-static const char * const pwm0_groups[] = {
-	"pwm0",
-};
-
-static const char * const pwm1_groups[] = {
-	"pwm1_a",
-	"pwm1_b",
-};
-
-static const char * const pwm2_groups[] = {
-	"pwm2_a",
-	"pwm2_b",
-};
-
-static const char * const pwm3_groups[] = {
-	"pwm3_a",
-	"pwm3_b",
-};
-
-static const char * const pwm4_groups[] = {
-	"pwm4_a",
-	"pwm4_b",
-};
-
-static const char * const pwm5_groups[] = {
-	"pwm5_a",
-	"pwm5_b",
-};
-
-static const char * const pwm6_groups[] = {
-	"pwm6_a",
-	"pwm6_b",
-};
-
-static const char * const sata0_groups[] = {
-	"sata0_devslp_a",
-	"sata0_devslp_b",
-};
-
-static const char * const scif0_groups[] = {
-	"scif0_data",
-	"scif0_clk",
-	"scif0_ctrl",
-};
-
-static const char * const scif1_groups[] = {
-	"scif1_data_a",
-	"scif1_clk",
-	"scif1_ctrl",
-	"scif1_data_b",
-};
-
-static const char * const scif2_groups[] = {
-	"scif2_data_a",
-	"scif2_clk",
-	"scif2_data_b",
-};
-
-static const char * const scif3_groups[] = {
-	"scif3_data_a",
-	"scif3_clk",
-	"scif3_ctrl",
-	"scif3_data_b",
-};
-
-static const char * const scif4_groups[] = {
-	"scif4_data_a",
-	"scif4_clk_a",
-	"scif4_ctrl_a",
-	"scif4_data_b",
-	"scif4_clk_b",
-	"scif4_ctrl_b",
-	"scif4_data_c",
-	"scif4_clk_c",
-	"scif4_ctrl_c",
-};
-
-static const char * const scif5_groups[] = {
-	"scif5_data_a",
-	"scif5_clk_a",
-	"scif5_data_b",
-	"scif5_clk_b",
-};
-
-static const char * const scif_clk_groups[] = {
-	"scif_clk_a",
-	"scif_clk_b",
-};
-
-static const char * const sdhi0_groups[] = {
-	"sdhi0_data1",
-	"sdhi0_data4",
-	"sdhi0_ctrl",
-	"sdhi0_cd",
-	"sdhi0_wp",
-};
-
-static const char * const sdhi1_groups[] = {
-	"sdhi1_data1",
-	"sdhi1_data4",
-	"sdhi1_ctrl",
-	"sdhi1_cd",
-	"sdhi1_wp",
-};
-
-static const char * const sdhi2_groups[] = {
-	"sdhi2_data1",
-	"sdhi2_data4",
-	"sdhi2_data8",
-	"sdhi2_ctrl",
-	"sdhi2_cd_a",
-	"sdhi2_wp_a",
-	"sdhi2_cd_b",
-	"sdhi2_wp_b",
-	"sdhi2_ds",
-};
-
-static const char * const sdhi3_groups[] = {
-	"sdhi3_data1",
-	"sdhi3_data4",
-	"sdhi3_data8",
-	"sdhi3_ctrl",
-	"sdhi3_cd",
-	"sdhi3_wp",
-	"sdhi3_ds",
-};
-
-static const char * const ssi_groups[] = {
-	"ssi0_data",
-	"ssi01239_ctrl",
-	"ssi1_data_a",
-	"ssi1_data_b",
-	"ssi1_ctrl_a",
-	"ssi1_ctrl_b",
-	"ssi2_data_a",
-	"ssi2_data_b",
-	"ssi2_ctrl_a",
-	"ssi2_ctrl_b",
-	"ssi3_data",
-	"ssi349_ctrl",
-	"ssi4_data",
-	"ssi4_ctrl",
-	"ssi5_data",
-	"ssi5_ctrl",
-	"ssi6_data",
-	"ssi6_ctrl",
-	"ssi7_data",
-	"ssi78_ctrl",
-	"ssi8_data",
-	"ssi9_data_a",
-	"ssi9_data_b",
-	"ssi9_ctrl_a",
-	"ssi9_ctrl_b",
-};
-
-static const char * const tmu_groups[] = {
-	"tmu_tclk1_a",
-	"tmu_tclk1_b",
-	"tmu_tclk2_a",
-	"tmu_tclk2_b",
-};
-
-static const char * const tpu_groups[] = {
-	"tpu_to0",
-	"tpu_to1",
-	"tpu_to2",
-	"tpu_to3",
-};
-
-static const char * const usb0_groups[] = {
-	"usb0",
-};
-
-static const char * const usb1_groups[] = {
-	"usb1",
-};
-
-static const char * const usb2_groups[] = {
-	"usb2",
-};
-
-static const char * const usb2_ch3_groups[] = {
-	"usb2_ch3",
-};
-
-static const char * const usb30_groups[] = {
-	"usb30",
-};
-
-static const char * const vin4_groups[] = {
-	"vin4_data8_a",
-	"vin4_data10_a",
-	"vin4_data12_a",
-	"vin4_data16_a",
-	"vin4_data18_a",
-	"vin4_data20_a",
-	"vin4_data24_a",
-	"vin4_data8_b",
-	"vin4_data10_b",
-	"vin4_data12_b",
-	"vin4_data16_b",
-	"vin4_data18_b",
-	"vin4_data20_b",
-	"vin4_data24_b",
-	"vin4_sync",
-	"vin4_field",
-	"vin4_clkenb",
-	"vin4_clk",
-};
-
-static const char * const vin5_groups[] = {
-	"vin5_data8",
-	"vin5_data10",
-	"vin5_data12",
-	"vin5_data16",
-	"vin5_sync",
-	"vin5_field",
-	"vin5_clkenb",
-	"vin5_clk",
-};
-
-static const struct sh_pfc_function pinmux_functions[] = {
-	SH_PFC_FUNCTION(audio_clk),
-	SH_PFC_FUNCTION(avb),
-	SH_PFC_FUNCTION(can0),
-	SH_PFC_FUNCTION(can1),
-	SH_PFC_FUNCTION(can_clk),
-	SH_PFC_FUNCTION(canfd0),
-	SH_PFC_FUNCTION(canfd1),
-	SH_PFC_FUNCTION(drif0),
-	SH_PFC_FUNCTION(drif1),
-	SH_PFC_FUNCTION(drif2),
-	SH_PFC_FUNCTION(drif3),
-	SH_PFC_FUNCTION(du),
-	SH_PFC_FUNCTION(hscif0),
-	SH_PFC_FUNCTION(hscif1),
-	SH_PFC_FUNCTION(hscif2),
-	SH_PFC_FUNCTION(hscif3),
-	SH_PFC_FUNCTION(hscif4),
-	SH_PFC_FUNCTION(i2c0),
-	SH_PFC_FUNCTION(i2c1),
-	SH_PFC_FUNCTION(i2c2),
-	SH_PFC_FUNCTION(i2c3),
-	SH_PFC_FUNCTION(i2c5),
-	SH_PFC_FUNCTION(i2c6),
-	SH_PFC_FUNCTION(intc_ex),
-	SH_PFC_FUNCTION(msiof0),
-	SH_PFC_FUNCTION(msiof1),
-	SH_PFC_FUNCTION(msiof2),
-	SH_PFC_FUNCTION(msiof3),
-	SH_PFC_FUNCTION(pwm0),
-	SH_PFC_FUNCTION(pwm1),
-	SH_PFC_FUNCTION(pwm2),
-	SH_PFC_FUNCTION(pwm3),
-	SH_PFC_FUNCTION(pwm4),
-	SH_PFC_FUNCTION(pwm5),
-	SH_PFC_FUNCTION(pwm6),
-	SH_PFC_FUNCTION(sata0),
-	SH_PFC_FUNCTION(scif0),
-	SH_PFC_FUNCTION(scif1),
-	SH_PFC_FUNCTION(scif2),
-	SH_PFC_FUNCTION(scif3),
-	SH_PFC_FUNCTION(scif4),
-	SH_PFC_FUNCTION(scif5),
-	SH_PFC_FUNCTION(scif_clk),
-	SH_PFC_FUNCTION(sdhi0),
-	SH_PFC_FUNCTION(sdhi1),
-	SH_PFC_FUNCTION(sdhi2),
-	SH_PFC_FUNCTION(sdhi3),
-	SH_PFC_FUNCTION(ssi),
-	SH_PFC_FUNCTION(tmu),
-	SH_PFC_FUNCTION(tpu),
-	SH_PFC_FUNCTION(usb0),
-	SH_PFC_FUNCTION(usb1),
-	SH_PFC_FUNCTION(usb2),
-	SH_PFC_FUNCTION(usb2_ch3),
-	SH_PFC_FUNCTION(usb30),
-	SH_PFC_FUNCTION(vin4),
-	SH_PFC_FUNCTION(vin5),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-#define F_(x, y)	FN_##y
-#define FM(x)		FN_##x
-	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_0_15_FN,	GPSR0_15,
-		GP_0_14_FN,	GPSR0_14,
-		GP_0_13_FN,	GPSR0_13,
-		GP_0_12_FN,	GPSR0_12,
-		GP_0_11_FN,	GPSR0_11,
-		GP_0_10_FN,	GPSR0_10,
-		GP_0_9_FN,	GPSR0_9,
-		GP_0_8_FN,	GPSR0_8,
-		GP_0_7_FN,	GPSR0_7,
-		GP_0_6_FN,	GPSR0_6,
-		GP_0_5_FN,	GPSR0_5,
-		GP_0_4_FN,	GPSR0_4,
-		GP_0_3_FN,	GPSR0_3,
-		GP_0_2_FN,	GPSR0_2,
-		GP_0_1_FN,	GPSR0_1,
-		GP_0_0_FN,	GPSR0_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_1_28_FN,	GPSR1_28,
-		GP_1_27_FN,	GPSR1_27,
-		GP_1_26_FN,	GPSR1_26,
-		GP_1_25_FN,	GPSR1_25,
-		GP_1_24_FN,	GPSR1_24,
-		GP_1_23_FN,	GPSR1_23,
-		GP_1_22_FN,	GPSR1_22,
-		GP_1_21_FN,	GPSR1_21,
-		GP_1_20_FN,	GPSR1_20,
-		GP_1_19_FN,	GPSR1_19,
-		GP_1_18_FN,	GPSR1_18,
-		GP_1_17_FN,	GPSR1_17,
-		GP_1_16_FN,	GPSR1_16,
-		GP_1_15_FN,	GPSR1_15,
-		GP_1_14_FN,	GPSR1_14,
-		GP_1_13_FN,	GPSR1_13,
-		GP_1_12_FN,	GPSR1_12,
-		GP_1_11_FN,	GPSR1_11,
-		GP_1_10_FN,	GPSR1_10,
-		GP_1_9_FN,	GPSR1_9,
-		GP_1_8_FN,	GPSR1_8,
-		GP_1_7_FN,	GPSR1_7,
-		GP_1_6_FN,	GPSR1_6,
-		GP_1_5_FN,	GPSR1_5,
-		GP_1_4_FN,	GPSR1_4,
-		GP_1_3_FN,	GPSR1_3,
-		GP_1_2_FN,	GPSR1_2,
-		GP_1_1_FN,	GPSR1_1,
-		GP_1_0_FN,	GPSR1_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_2_14_FN,	GPSR2_14,
-		GP_2_13_FN,	GPSR2_13,
-		GP_2_12_FN,	GPSR2_12,
-		GP_2_11_FN,	GPSR2_11,
-		GP_2_10_FN,	GPSR2_10,
-		GP_2_9_FN,	GPSR2_9,
-		GP_2_8_FN,	GPSR2_8,
-		GP_2_7_FN,	GPSR2_7,
-		GP_2_6_FN,	GPSR2_6,
-		GP_2_5_FN,	GPSR2_5,
-		GP_2_4_FN,	GPSR2_4,
-		GP_2_3_FN,	GPSR2_3,
-		GP_2_2_FN,	GPSR2_2,
-		GP_2_1_FN,	GPSR2_1,
-		GP_2_0_FN,	GPSR2_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_3_15_FN,	GPSR3_15,
-		GP_3_14_FN,	GPSR3_14,
-		GP_3_13_FN,	GPSR3_13,
-		GP_3_12_FN,	GPSR3_12,
-		GP_3_11_FN,	GPSR3_11,
-		GP_3_10_FN,	GPSR3_10,
-		GP_3_9_FN,	GPSR3_9,
-		GP_3_8_FN,	GPSR3_8,
-		GP_3_7_FN,	GPSR3_7,
-		GP_3_6_FN,	GPSR3_6,
-		GP_3_5_FN,	GPSR3_5,
-		GP_3_4_FN,	GPSR3_4,
-		GP_3_3_FN,	GPSR3_3,
-		GP_3_2_FN,	GPSR3_2,
-		GP_3_1_FN,	GPSR3_1,
-		GP_3_0_FN,	GPSR3_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_4_17_FN,	GPSR4_17,
-		GP_4_16_FN,	GPSR4_16,
-		GP_4_15_FN,	GPSR4_15,
-		GP_4_14_FN,	GPSR4_14,
-		GP_4_13_FN,	GPSR4_13,
-		GP_4_12_FN,	GPSR4_12,
-		GP_4_11_FN,	GPSR4_11,
-		GP_4_10_FN,	GPSR4_10,
-		GP_4_9_FN,	GPSR4_9,
-		GP_4_8_FN,	GPSR4_8,
-		GP_4_7_FN,	GPSR4_7,
-		GP_4_6_FN,	GPSR4_6,
-		GP_4_5_FN,	GPSR4_5,
-		GP_4_4_FN,	GPSR4_4,
-		GP_4_3_FN,	GPSR4_3,
-		GP_4_2_FN,	GPSR4_2,
-		GP_4_1_FN,	GPSR4_1,
-		GP_4_0_FN,	GPSR4_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_5_25_FN,	GPSR5_25,
-		GP_5_24_FN,	GPSR5_24,
-		GP_5_23_FN,	GPSR5_23,
-		GP_5_22_FN,	GPSR5_22,
-		GP_5_21_FN,	GPSR5_21,
-		GP_5_20_FN,	GPSR5_20,
-		GP_5_19_FN,	GPSR5_19,
-		GP_5_18_FN,	GPSR5_18,
-		GP_5_17_FN,	GPSR5_17,
-		GP_5_16_FN,	GPSR5_16,
-		GP_5_15_FN,	GPSR5_15,
-		GP_5_14_FN,	GPSR5_14,
-		GP_5_13_FN,	GPSR5_13,
-		GP_5_12_FN,	GPSR5_12,
-		GP_5_11_FN,	GPSR5_11,
-		GP_5_10_FN,	GPSR5_10,
-		GP_5_9_FN,	GPSR5_9,
-		GP_5_8_FN,	GPSR5_8,
-		GP_5_7_FN,	GPSR5_7,
-		GP_5_6_FN,	GPSR5_6,
-		GP_5_5_FN,	GPSR5_5,
-		GP_5_4_FN,	GPSR5_4,
-		GP_5_3_FN,	GPSR5_3,
-		GP_5_2_FN,	GPSR5_2,
-		GP_5_1_FN,	GPSR5_1,
-		GP_5_0_FN,	GPSR5_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
-		GP_6_31_FN,	GPSR6_31,
-		GP_6_30_FN,	GPSR6_30,
-		GP_6_29_FN,	GPSR6_29,
-		GP_6_28_FN,	GPSR6_28,
-		GP_6_27_FN,	GPSR6_27,
-		GP_6_26_FN,	GPSR6_26,
-		GP_6_25_FN,	GPSR6_25,
-		GP_6_24_FN,	GPSR6_24,
-		GP_6_23_FN,	GPSR6_23,
-		GP_6_22_FN,	GPSR6_22,
-		GP_6_21_FN,	GPSR6_21,
-		GP_6_20_FN,	GPSR6_20,
-		GP_6_19_FN,	GPSR6_19,
-		GP_6_18_FN,	GPSR6_18,
-		GP_6_17_FN,	GPSR6_17,
-		GP_6_16_FN,	GPSR6_16,
-		GP_6_15_FN,	GPSR6_15,
-		GP_6_14_FN,	GPSR6_14,
-		GP_6_13_FN,	GPSR6_13,
-		GP_6_12_FN,	GPSR6_12,
-		GP_6_11_FN,	GPSR6_11,
-		GP_6_10_FN,	GPSR6_10,
-		GP_6_9_FN,	GPSR6_9,
-		GP_6_8_FN,	GPSR6_8,
-		GP_6_7_FN,	GPSR6_7,
-		GP_6_6_FN,	GPSR6_6,
-		GP_6_5_FN,	GPSR6_5,
-		GP_6_4_FN,	GPSR6_4,
-		GP_6_3_FN,	GPSR6_3,
-		GP_6_2_FN,	GPSR6_2,
-		GP_6_1_FN,	GPSR6_1,
-		GP_6_0_FN,	GPSR6_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_7_3_FN, GPSR7_3,
-		GP_7_2_FN, GPSR7_2,
-		GP_7_1_FN, GPSR7_1,
-		GP_7_0_FN, GPSR7_0, ))
-	},
-#undef F_
-#undef FM
-
-#define F_(x, y)	x,
-#define FM(x)		FN_##x,
-	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
-		IP0_31_28
-		IP0_27_24
-		IP0_23_20
-		IP0_19_16
-		IP0_15_12
-		IP0_11_8
-		IP0_7_4
-		IP0_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
-		IP1_31_28
-		IP1_27_24
-		IP1_23_20
-		IP1_19_16
-		IP1_15_12
-		IP1_11_8
-		IP1_7_4
-		IP1_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
-		IP2_31_28
-		IP2_27_24
-		IP2_23_20
-		IP2_19_16
-		IP2_15_12
-		IP2_11_8
-		IP2_7_4
-		IP2_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
-		IP3_31_28
-		IP3_27_24
-		IP3_23_20
-		IP3_19_16
-		IP3_15_12
-		IP3_11_8
-		IP3_7_4
-		IP3_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
-		IP4_31_28
-		IP4_27_24
-		IP4_23_20
-		IP4_19_16
-		IP4_15_12
-		IP4_11_8
-		IP4_7_4
-		IP4_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
-		IP5_31_28
-		IP5_27_24
-		IP5_23_20
-		IP5_19_16
-		IP5_15_12
-		IP5_11_8
-		IP5_7_4
-		IP5_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
-		IP6_31_28
-		IP6_27_24
-		IP6_23_20
-		IP6_19_16
-		IP6_15_12
-		IP6_11_8
-		IP6_7_4
-		IP6_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
-		IP7_31_28
-		IP7_27_24
-		IP7_23_20
-		IP7_19_16
-		/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		IP7_11_8
-		IP7_7_4
-		IP7_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
-		IP8_31_28
-		IP8_27_24
-		IP8_23_20
-		IP8_19_16
-		IP8_15_12
-		IP8_11_8
-		IP8_7_4
-		IP8_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
-		IP9_31_28
-		IP9_27_24
-		IP9_23_20
-		IP9_19_16
-		IP9_15_12
-		IP9_11_8
-		IP9_7_4
-		IP9_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
-		IP10_31_28
-		IP10_27_24
-		IP10_23_20
-		IP10_19_16
-		IP10_15_12
-		IP10_11_8
-		IP10_7_4
-		IP10_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
-		IP11_31_28
-		IP11_27_24
-		IP11_23_20
-		IP11_19_16
-		IP11_15_12
-		IP11_11_8
-		IP11_7_4
-		IP11_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
-		IP12_31_28
-		IP12_27_24
-		IP12_23_20
-		IP12_19_16
-		IP12_15_12
-		IP12_11_8
-		IP12_7_4
-		IP12_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
-		IP13_31_28
-		IP13_27_24
-		IP13_23_20
-		IP13_19_16
-		IP13_15_12
-		IP13_11_8
-		IP13_7_4
-		IP13_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
-		IP14_31_28
-		IP14_27_24
-		IP14_23_20
-		IP14_19_16
-		IP14_15_12
-		IP14_11_8
-		IP14_7_4
-		IP14_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
-		IP15_31_28
-		IP15_27_24
-		IP15_23_20
-		IP15_19_16
-		IP15_15_12
-		IP15_11_8
-		IP15_7_4
-		IP15_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
-		IP16_31_28
-		IP16_27_24
-		IP16_23_20
-		IP16_19_16
-		IP16_15_12
-		IP16_11_8
-		IP16_7_4
-		IP16_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
-		IP17_31_28
-		IP17_27_24
-		IP17_23_20
-		IP17_19_16
-		IP17_15_12
-		IP17_11_8
-		IP17_7_4
-		IP17_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
-		/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP18_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		IP18_7_4
-		IP18_3_0 ))
-	},
-#undef F_
-#undef FM
-
-#define F_(x, y)	x,
-#define FM(x)		FN_##x,
-	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
-			     GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
-				   1, 1, 1, 2, 2, 1, 2, 3),
-			     GROUP(
-		MOD_SEL0_31_30_29
-		MOD_SEL0_28_27
-		MOD_SEL0_26_25_24
-		MOD_SEL0_23
-		MOD_SEL0_22
-		MOD_SEL0_21
-		MOD_SEL0_20
-		MOD_SEL0_19
-		MOD_SEL0_18_17
-		MOD_SEL0_16
-		0, 0, /* RESERVED 15 */
-		MOD_SEL0_14_13
-		MOD_SEL0_12
-		MOD_SEL0_11
-		MOD_SEL0_10
-		MOD_SEL0_9_8
-		MOD_SEL0_7_6
-		MOD_SEL0_5
-		MOD_SEL0_4_3
-		/* RESERVED 2, 1, 0 */
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
-			     GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
-				   1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
-			     GROUP(
-		MOD_SEL1_31_30
-		MOD_SEL1_29_28_27
-		MOD_SEL1_26
-		MOD_SEL1_25_24
-		MOD_SEL1_23_22_21
-		MOD_SEL1_20
-		MOD_SEL1_19
-		MOD_SEL1_18_17
-		MOD_SEL1_16
-		MOD_SEL1_15_14
-		MOD_SEL1_13
-		MOD_SEL1_12
-		MOD_SEL1_11
-		MOD_SEL1_10
-		MOD_SEL1_9
-		0, 0, 0, 0, /* RESERVED 8, 7 */
-		MOD_SEL1_6
-		MOD_SEL1_5
-		MOD_SEL1_4
-		MOD_SEL1_3
-		MOD_SEL1_2
-		MOD_SEL1_1
-		MOD_SEL1_0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
-			     GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
-				   1, 4, 4, 4, 3, 1),
-			     GROUP(
-		MOD_SEL2_31
-		MOD_SEL2_30
-		MOD_SEL2_29
-		MOD_SEL2_28_27
-		MOD_SEL2_26
-		MOD_SEL2_25_24_23
-		/* RESERVED 22 */
-		0, 0,
-		MOD_SEL2_21
-		MOD_SEL2_20
-		MOD_SEL2_19
-		MOD_SEL2_18
-		MOD_SEL2_17
-		/* RESERVED 16 */
-		0, 0,
-		/* RESERVED 15, 14, 13, 12 */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 11, 10, 9, 8 */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 7, 6, 5, 4 */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 3, 2, 1 */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		MOD_SEL2_0 ))
-	},
-	{ },
-};
-
-static const struct pinmux_drive_reg pinmux_drive_regs[] = {
-	{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
-		{ PIN_QSPI0_SPCLK,    28, 2 },	/* QSPI0_SPCLK */
-		{ PIN_QSPI0_MOSI_IO0, 24, 2 },	/* QSPI0_MOSI_IO0 */
-		{ PIN_QSPI0_MISO_IO1, 20, 2 },	/* QSPI0_MISO_IO1 */
-		{ PIN_QSPI0_IO2,      16, 2 },	/* QSPI0_IO2 */
-		{ PIN_QSPI0_IO3,      12, 2 },	/* QSPI0_IO3 */
-		{ PIN_QSPI0_SSL,       8, 2 },	/* QSPI0_SSL */
-		{ PIN_QSPI1_SPCLK,     4, 2 },	/* QSPI1_SPCLK */
-		{ PIN_QSPI1_MOSI_IO0,  0, 2 },	/* QSPI1_MOSI_IO0 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
-		{ PIN_QSPI1_MISO_IO1, 28, 2 },	/* QSPI1_MISO_IO1 */
-		{ PIN_QSPI1_IO2,      24, 2 },	/* QSPI1_IO2 */
-		{ PIN_QSPI1_IO3,      20, 2 },	/* QSPI1_IO3 */
-		{ PIN_QSPI1_SSL,      16, 2 },	/* QSPI1_SSL */
-		{ PIN_RPC_INT_N,      12, 2 },	/* RPC_INT# */
-		{ PIN_RPC_WP_N,        8, 2 },	/* RPC_WP# */
-		{ PIN_RPC_RESET_N,     4, 2 },	/* RPC_RESET# */
-		{ PIN_AVB_RX_CTL,      0, 3 },	/* AVB_RX_CTL */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
-		{ PIN_AVB_RXC,        28, 3 },	/* AVB_RXC */
-		{ PIN_AVB_RD0,        24, 3 },	/* AVB_RD0 */
-		{ PIN_AVB_RD1,        20, 3 },	/* AVB_RD1 */
-		{ PIN_AVB_RD2,        16, 3 },	/* AVB_RD2 */
-		{ PIN_AVB_RD3,        12, 3 },	/* AVB_RD3 */
-		{ PIN_AVB_TX_CTL,      8, 3 },	/* AVB_TX_CTL */
-		{ PIN_AVB_TXC,         4, 3 },	/* AVB_TXC */
-		{ PIN_AVB_TD0,         0, 3 },	/* AVB_TD0 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
-		{ PIN_AVB_TD1,        28, 3 },	/* AVB_TD1 */
-		{ PIN_AVB_TD2,        24, 3 },	/* AVB_TD2 */
-		{ PIN_AVB_TD3,        20, 3 },	/* AVB_TD3 */
-		{ PIN_AVB_TXCREFCLK,  16, 3 },	/* AVB_TXCREFCLK */
-		{ PIN_AVB_MDIO,       12, 3 },	/* AVB_MDIO */
-		{ RCAR_GP_PIN(2,  9),  8, 3 },	/* AVB_MDC */
-		{ RCAR_GP_PIN(2, 10),  4, 3 },	/* AVB_MAGIC */
-		{ RCAR_GP_PIN(2, 11),  0, 3 },	/* AVB_PHY_INT */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
-		{ RCAR_GP_PIN(2, 12), 28, 3 },	/* AVB_LINK */
-		{ RCAR_GP_PIN(2, 13), 24, 3 },	/* AVB_AVTP_MATCH */
-		{ RCAR_GP_PIN(2, 14), 20, 3 },	/* AVB_AVTP_CAPTURE */
-		{ RCAR_GP_PIN(2,  0), 16, 3 },	/* IRQ0 */
-		{ RCAR_GP_PIN(2,  1), 12, 3 },	/* IRQ1 */
-		{ RCAR_GP_PIN(2,  2),  8, 3 },	/* IRQ2 */
-		{ RCAR_GP_PIN(2,  3),  4, 3 },	/* IRQ3 */
-		{ RCAR_GP_PIN(2,  4),  0, 3 },	/* IRQ4 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
-		{ RCAR_GP_PIN(2,  5), 28, 3 },	/* IRQ5 */
-		{ RCAR_GP_PIN(2,  6), 24, 3 },	/* PWM0 */
-		{ RCAR_GP_PIN(2,  7), 20, 3 },	/* PWM1 */
-		{ RCAR_GP_PIN(2,  8), 16, 3 },	/* PWM2 */
-		{ RCAR_GP_PIN(1,  0), 12, 3 },	/* A0 */
-		{ RCAR_GP_PIN(1,  1),  8, 3 },	/* A1 */
-		{ RCAR_GP_PIN(1,  2),  4, 3 },	/* A2 */
-		{ RCAR_GP_PIN(1,  3),  0, 3 },	/* A3 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
-		{ RCAR_GP_PIN(1,  4), 28, 3 },	/* A4 */
-		{ RCAR_GP_PIN(1,  5), 24, 3 },	/* A5 */
-		{ RCAR_GP_PIN(1,  6), 20, 3 },	/* A6 */
-		{ RCAR_GP_PIN(1,  7), 16, 3 },	/* A7 */
-		{ RCAR_GP_PIN(1,  8), 12, 3 },	/* A8 */
-		{ RCAR_GP_PIN(1,  9),  8, 3 },	/* A9 */
-		{ RCAR_GP_PIN(1, 10),  4, 3 },	/* A10 */
-		{ RCAR_GP_PIN(1, 11),  0, 3 },	/* A11 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
-		{ RCAR_GP_PIN(1, 12), 28, 3 },	/* A12 */
-		{ RCAR_GP_PIN(1, 13), 24, 3 },	/* A13 */
-		{ RCAR_GP_PIN(1, 14), 20, 3 },	/* A14 */
-		{ RCAR_GP_PIN(1, 15), 16, 3 },	/* A15 */
-		{ RCAR_GP_PIN(1, 16), 12, 3 },	/* A16 */
-		{ RCAR_GP_PIN(1, 17),  8, 3 },	/* A17 */
-		{ RCAR_GP_PIN(1, 18),  4, 3 },	/* A18 */
-		{ RCAR_GP_PIN(1, 19),  0, 3 },	/* A19 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
-		{ RCAR_GP_PIN(1, 28), 28, 3 },	/* CLKOUT */
-		{ RCAR_GP_PIN(1, 20), 24, 3 },	/* CS0 */
-		{ RCAR_GP_PIN(1, 21), 20, 3 },	/* CS1_A26 */
-		{ RCAR_GP_PIN(1, 22), 16, 3 },	/* BS */
-		{ RCAR_GP_PIN(1, 23), 12, 3 },	/* RD */
-		{ RCAR_GP_PIN(1, 24),  8, 3 },	/* RD_WR */
-		{ RCAR_GP_PIN(1, 25),  4, 3 },	/* WE0 */
-		{ RCAR_GP_PIN(1, 26),  0, 3 },	/* WE1 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
-		{ RCAR_GP_PIN(1, 27), 28, 3 },	/* EX_WAIT0 */
-		{ PIN_PRESETOUT_N,    24, 3 },	/* PRESETOUT# */
-		{ RCAR_GP_PIN(0,  0), 20, 3 },	/* D0 */
-		{ RCAR_GP_PIN(0,  1), 16, 3 },	/* D1 */
-		{ RCAR_GP_PIN(0,  2), 12, 3 },	/* D2 */
-		{ RCAR_GP_PIN(0,  3),  8, 3 },	/* D3 */
-		{ RCAR_GP_PIN(0,  4),  4, 3 },	/* D4 */
-		{ RCAR_GP_PIN(0,  5),  0, 3 },	/* D5 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
-		{ RCAR_GP_PIN(0,  6), 28, 3 },	/* D6 */
-		{ RCAR_GP_PIN(0,  7), 24, 3 },	/* D7 */
-		{ RCAR_GP_PIN(0,  8), 20, 3 },	/* D8 */
-		{ RCAR_GP_PIN(0,  9), 16, 3 },	/* D9 */
-		{ RCAR_GP_PIN(0, 10), 12, 3 },	/* D10 */
-		{ RCAR_GP_PIN(0, 11),  8, 3 },	/* D11 */
-		{ RCAR_GP_PIN(0, 12),  4, 3 },	/* D12 */
-		{ RCAR_GP_PIN(0, 13),  0, 3 },	/* D13 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
-		{ RCAR_GP_PIN(0, 14), 28, 3 },	/* D14 */
-		{ RCAR_GP_PIN(0, 15), 24, 3 },	/* D15 */
-		{ RCAR_GP_PIN(7,  0), 20, 3 },	/* AVS1 */
-		{ RCAR_GP_PIN(7,  1), 16, 3 },	/* AVS2 */
-		{ RCAR_GP_PIN(7,  2), 12, 3 },	/* GP7_02 */
-		{ RCAR_GP_PIN(7,  3),  8, 3 },	/* GP7_03 */
-		{ PIN_DU_DOTCLKIN0,    4, 2 },	/* DU_DOTCLKIN0 */
-		{ PIN_DU_DOTCLKIN1,    0, 2 },	/* DU_DOTCLKIN1 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
-		{ PIN_DU_DOTCLKIN2,   28, 2 },	/* DU_DOTCLKIN2 */
-		{ PIN_DU_DOTCLKIN3,   24, 2 },	/* DU_DOTCLKIN3 */
-		{ PIN_FSCLKST_N,      20, 2 },	/* FSCLKST# */
-		{ PIN_TMS,             4, 2 },	/* TMS */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
-		{ PIN_TDO,            28, 2 },	/* TDO */
-		{ PIN_ASEBRK,         24, 2 },	/* ASEBRK */
-		{ RCAR_GP_PIN(3,  0), 20, 3 },	/* SD0_CLK */
-		{ RCAR_GP_PIN(3,  1), 16, 3 },	/* SD0_CMD */
-		{ RCAR_GP_PIN(3,  2), 12, 3 },	/* SD0_DAT0 */
-		{ RCAR_GP_PIN(3,  3),  8, 3 },	/* SD0_DAT1 */
-		{ RCAR_GP_PIN(3,  4),  4, 3 },	/* SD0_DAT2 */
-		{ RCAR_GP_PIN(3,  5),  0, 3 },	/* SD0_DAT3 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
-		{ RCAR_GP_PIN(3,  6), 28, 3 },	/* SD1_CLK */
-		{ RCAR_GP_PIN(3,  7), 24, 3 },	/* SD1_CMD */
-		{ RCAR_GP_PIN(3,  8), 20, 3 },	/* SD1_DAT0 */
-		{ RCAR_GP_PIN(3,  9), 16, 3 },	/* SD1_DAT1 */
-		{ RCAR_GP_PIN(3, 10), 12, 3 },	/* SD1_DAT2 */
-		{ RCAR_GP_PIN(3, 11),  8, 3 },	/* SD1_DAT3 */
-		{ RCAR_GP_PIN(4,  0),  4, 3 },	/* SD2_CLK */
-		{ RCAR_GP_PIN(4,  1),  0, 3 },	/* SD2_CMD */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
-		{ RCAR_GP_PIN(4,  2), 28, 3 },	/* SD2_DAT0 */
-		{ RCAR_GP_PIN(4,  3), 24, 3 },	/* SD2_DAT1 */
-		{ RCAR_GP_PIN(4,  4), 20, 3 },	/* SD2_DAT2 */
-		{ RCAR_GP_PIN(4,  5), 16, 3 },	/* SD2_DAT3 */
-		{ RCAR_GP_PIN(4,  6), 12, 3 },	/* SD2_DS */
-		{ RCAR_GP_PIN(4,  7),  8, 3 },	/* SD3_CLK */
-		{ RCAR_GP_PIN(4,  8),  4, 3 },	/* SD3_CMD */
-		{ RCAR_GP_PIN(4,  9),  0, 3 },	/* SD3_DAT0 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
-		{ RCAR_GP_PIN(4, 10), 28, 3 },	/* SD3_DAT1 */
-		{ RCAR_GP_PIN(4, 11), 24, 3 },	/* SD3_DAT2 */
-		{ RCAR_GP_PIN(4, 12), 20, 3 },	/* SD3_DAT3 */
-		{ RCAR_GP_PIN(4, 13), 16, 3 },	/* SD3_DAT4 */
-		{ RCAR_GP_PIN(4, 14), 12, 3 },	/* SD3_DAT5 */
-		{ RCAR_GP_PIN(4, 15),  8, 3 },	/* SD3_DAT6 */
-		{ RCAR_GP_PIN(4, 16),  4, 3 },	/* SD3_DAT7 */
-		{ RCAR_GP_PIN(4, 17),  0, 3 },	/* SD3_DS */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
-		{ RCAR_GP_PIN(3, 12), 28, 3 },	/* SD0_CD */
-		{ RCAR_GP_PIN(3, 13), 24, 3 },	/* SD0_WP */
-		{ RCAR_GP_PIN(3, 14), 20, 3 },	/* SD1_CD */
-		{ RCAR_GP_PIN(3, 15), 16, 3 },	/* SD1_WP */
-		{ RCAR_GP_PIN(5,  0), 12, 3 },	/* SCK0 */
-		{ RCAR_GP_PIN(5,  1),  8, 3 },	/* RX0 */
-		{ RCAR_GP_PIN(5,  2),  4, 3 },	/* TX0 */
-		{ RCAR_GP_PIN(5,  3),  0, 3 },	/* CTS0 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
-		{ RCAR_GP_PIN(5,  4), 28, 3 },	/* RTS0 */
-		{ RCAR_GP_PIN(5,  5), 24, 3 },	/* RX1 */
-		{ RCAR_GP_PIN(5,  6), 20, 3 },	/* TX1 */
-		{ RCAR_GP_PIN(5,  7), 16, 3 },	/* CTS1 */
-		{ RCAR_GP_PIN(5,  8), 12, 3 },	/* RTS1 */
-		{ RCAR_GP_PIN(5,  9),  8, 3 },	/* SCK2 */
-		{ RCAR_GP_PIN(5, 10),  4, 3 },	/* TX2 */
-		{ RCAR_GP_PIN(5, 11),  0, 3 },	/* RX2 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
-		{ RCAR_GP_PIN(5, 12), 28, 3 },	/* HSCK0 */
-		{ RCAR_GP_PIN(5, 13), 24, 3 },	/* HRX0 */
-		{ RCAR_GP_PIN(5, 14), 20, 3 },	/* HTX0 */
-		{ RCAR_GP_PIN(5, 15), 16, 3 },	/* HCTS0 */
-		{ RCAR_GP_PIN(5, 16), 12, 3 },	/* HRTS0 */
-		{ RCAR_GP_PIN(5, 17),  8, 3 },	/* MSIOF0_SCK */
-		{ RCAR_GP_PIN(5, 18),  4, 3 },	/* MSIOF0_SYNC */
-		{ RCAR_GP_PIN(5, 19),  0, 3 },	/* MSIOF0_SS1 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
-		{ RCAR_GP_PIN(5, 20), 28, 3 },	/* MSIOF0_TXD */
-		{ RCAR_GP_PIN(5, 21), 24, 3 },	/* MSIOF0_SS2 */
-		{ RCAR_GP_PIN(5, 22), 20, 3 },	/* MSIOF0_RXD */
-		{ RCAR_GP_PIN(5, 23), 16, 3 },	/* MLB_CLK */
-		{ RCAR_GP_PIN(5, 24), 12, 3 },	/* MLB_SIG */
-		{ RCAR_GP_PIN(5, 25),  8, 3 },	/* MLB_DAT */
-		{ PIN_MLB_REF,         4, 3 },	/* MLB_REF */
-		{ RCAR_GP_PIN(6,  0),  0, 3 },	/* SSI_SCK01239 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
-		{ RCAR_GP_PIN(6,  1), 28, 3 },	/* SSI_WS01239 */
-		{ RCAR_GP_PIN(6,  2), 24, 3 },	/* SSI_SDATA0 */
-		{ RCAR_GP_PIN(6,  3), 20, 3 },	/* SSI_SDATA1 */
-		{ RCAR_GP_PIN(6,  4), 16, 3 },	/* SSI_SDATA2 */
-		{ RCAR_GP_PIN(6,  5), 12, 3 },	/* SSI_SCK349 */
-		{ RCAR_GP_PIN(6,  6),  8, 3 },	/* SSI_WS349 */
-		{ RCAR_GP_PIN(6,  7),  4, 3 },	/* SSI_SDATA3 */
-		{ RCAR_GP_PIN(6,  8),  0, 3 },	/* SSI_SCK4 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
-		{ RCAR_GP_PIN(6,  9), 28, 3 },	/* SSI_WS4 */
-		{ RCAR_GP_PIN(6, 10), 24, 3 },	/* SSI_SDATA4 */
-		{ RCAR_GP_PIN(6, 11), 20, 3 },	/* SSI_SCK5 */
-		{ RCAR_GP_PIN(6, 12), 16, 3 },	/* SSI_WS5 */
-		{ RCAR_GP_PIN(6, 13), 12, 3 },	/* SSI_SDATA5 */
-		{ RCAR_GP_PIN(6, 14),  8, 3 },	/* SSI_SCK6 */
-		{ RCAR_GP_PIN(6, 15),  4, 3 },	/* SSI_WS6 */
-		{ RCAR_GP_PIN(6, 16),  0, 3 },	/* SSI_SDATA6 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
-		{ RCAR_GP_PIN(6, 17), 28, 3 },	/* SSI_SCK78 */
-		{ RCAR_GP_PIN(6, 18), 24, 3 },	/* SSI_WS78 */
-		{ RCAR_GP_PIN(6, 19), 20, 3 },	/* SSI_SDATA7 */
-		{ RCAR_GP_PIN(6, 20), 16, 3 },	/* SSI_SDATA8 */
-		{ RCAR_GP_PIN(6, 21), 12, 3 },	/* SSI_SDATA9 */
-		{ RCAR_GP_PIN(6, 22),  8, 3 },	/* AUDIO_CLKA */
-		{ RCAR_GP_PIN(6, 23),  4, 3 },	/* AUDIO_CLKB */
-		{ RCAR_GP_PIN(6, 24),  0, 3 },	/* USB0_PWEN */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
-		{ RCAR_GP_PIN(6, 25), 28, 3 },	/* USB0_OVC */
-		{ RCAR_GP_PIN(6, 26), 24, 3 },	/* USB1_PWEN */
-		{ RCAR_GP_PIN(6, 27), 20, 3 },	/* USB1_OVC */
-		{ RCAR_GP_PIN(6, 28), 16, 3 },	/* USB30_PWEN */
-		{ RCAR_GP_PIN(6, 29), 12, 3 },	/* USB30_OVC */
-		{ RCAR_GP_PIN(6, 30),  8, 3 },	/* USB2_CH3_PWEN */
-		{ RCAR_GP_PIN(6, 31),  4, 3 },	/* USB2_CH3_OVC */
-	} },
-	{ },
-};
-
-enum ioctrl_regs {
-	POCCTRL,
-	TDSELCTRL,
-};
-
-static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
-	[POCCTRL] = { 0xe6060380, },
-	[TDSELCTRL] = { 0xe60603c0, },
-	{ /* sentinel */ },
-};
-
-static int r8a77951_pin_to_pocctrl(struct sh_pfc *pfc,
-				   unsigned int pin, u32 *pocctrl)
-{
-	int bit = -EINVAL;
-
-	*pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
-
-	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
-		bit = pin & 0x1f;
-
-	if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
-		bit = (pin & 0x1f) + 12;
-
-	return bit;
-}
-
-static const struct pinmux_bias_reg pinmux_bias_regs[] = {
-	{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
-		[ 0] = PIN_QSPI0_SPCLK,		/* QSPI0_SPCLK */
-		[ 1] = PIN_QSPI0_MOSI_IO0,	/* QSPI0_MOSI_IO0 */
-		[ 2] = PIN_QSPI0_MISO_IO1,	/* QSPI0_MISO_IO1 */
-		[ 3] = PIN_QSPI0_IO2,		/* QSPI0_IO2 */
-		[ 4] = PIN_QSPI0_IO3,		/* QSPI0_IO3 */
-		[ 5] = PIN_QSPI0_SSL,		/* QSPI0_SSL */
-		[ 6] = PIN_QSPI1_SPCLK,		/* QSPI1_SPCLK */
-		[ 7] = PIN_QSPI1_MOSI_IO0,	/* QSPI1_MOSI_IO0 */
-		[ 8] = PIN_QSPI1_MISO_IO1,	/* QSPI1_MISO_IO1 */
-		[ 9] = PIN_QSPI1_IO2,		/* QSPI1_IO2 */
-		[10] = PIN_QSPI1_IO3,		/* QSPI1_IO3 */
-		[11] = PIN_QSPI1_SSL,		/* QSPI1_SSL */
-		[12] = PIN_RPC_INT_N,		/* RPC_INT# */
-		[13] = PIN_RPC_WP_N,		/* RPC_WP# */
-		[14] = PIN_RPC_RESET_N,		/* RPC_RESET# */
-		[15] = PIN_AVB_RX_CTL,		/* AVB_RX_CTL */
-		[16] = PIN_AVB_RXC,		/* AVB_RXC */
-		[17] = PIN_AVB_RD0,		/* AVB_RD0 */
-		[18] = PIN_AVB_RD1,		/* AVB_RD1 */
-		[19] = PIN_AVB_RD2,		/* AVB_RD2 */
-		[20] = PIN_AVB_RD3,		/* AVB_RD3 */
-		[21] = PIN_AVB_TX_CTL,		/* AVB_TX_CTL */
-		[22] = PIN_AVB_TXC,		/* AVB_TXC */
-		[23] = PIN_AVB_TD0,		/* AVB_TD0 */
-		[24] = PIN_AVB_TD1,		/* AVB_TD1 */
-		[25] = PIN_AVB_TD2,		/* AVB_TD2 */
-		[26] = PIN_AVB_TD3,		/* AVB_TD3 */
-		[27] = PIN_AVB_TXCREFCLK,	/* AVB_TXCREFCLK */
-		[28] = PIN_AVB_MDIO,		/* AVB_MDIO */
-		[29] = RCAR_GP_PIN(2,  9),	/* AVB_MDC */
-		[30] = RCAR_GP_PIN(2, 10),	/* AVB_MAGIC */
-		[31] = RCAR_GP_PIN(2, 11),	/* AVB_PHY_INT */
-	} },
-	{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
-		[ 0] = RCAR_GP_PIN(2, 12),	/* AVB_LINK */
-		[ 1] = RCAR_GP_PIN(2, 13),	/* AVB_AVTP_MATCH_A */
-		[ 2] = RCAR_GP_PIN(2, 14),	/* AVB_AVTP_CAPTURE_A */
-		[ 3] = RCAR_GP_PIN(2,  0),	/* IRQ0 */
-		[ 4] = RCAR_GP_PIN(2,  1),	/* IRQ1 */
-		[ 5] = RCAR_GP_PIN(2,  2),	/* IRQ2 */
-		[ 6] = RCAR_GP_PIN(2,  3),	/* IRQ3 */
-		[ 7] = RCAR_GP_PIN(2,  4),	/* IRQ4 */
-		[ 8] = RCAR_GP_PIN(2,  5),	/* IRQ5 */
-		[ 9] = RCAR_GP_PIN(2,  6),	/* PWM0 */
-		[10] = RCAR_GP_PIN(2,  7),	/* PWM1_A */
-		[11] = RCAR_GP_PIN(2,  8),	/* PWM2_A */
-		[12] = RCAR_GP_PIN(1,  0),	/* A0 */
-		[13] = RCAR_GP_PIN(1,  1),	/* A1 */
-		[14] = RCAR_GP_PIN(1,  2),	/* A2 */
-		[15] = RCAR_GP_PIN(1,  3),	/* A3 */
-		[16] = RCAR_GP_PIN(1,  4),	/* A4 */
-		[17] = RCAR_GP_PIN(1,  5),	/* A5 */
-		[18] = RCAR_GP_PIN(1,  6),	/* A6 */
-		[19] = RCAR_GP_PIN(1,  7),	/* A7 */
-		[20] = RCAR_GP_PIN(1,  8),	/* A8 */
-		[21] = RCAR_GP_PIN(1,  9),	/* A9 */
-		[22] = RCAR_GP_PIN(1, 10),	/* A10 */
-		[23] = RCAR_GP_PIN(1, 11),	/* A11 */
-		[24] = RCAR_GP_PIN(1, 12),	/* A12 */
-		[25] = RCAR_GP_PIN(1, 13),	/* A13 */
-		[26] = RCAR_GP_PIN(1, 14),	/* A14 */
-		[27] = RCAR_GP_PIN(1, 15),	/* A15 */
-		[28] = RCAR_GP_PIN(1, 16),	/* A16 */
-		[29] = RCAR_GP_PIN(1, 17),	/* A17 */
-		[30] = RCAR_GP_PIN(1, 18),	/* A18 */
-		[31] = RCAR_GP_PIN(1, 19),	/* A19 */
-	} },
-	{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
-		[ 0] = RCAR_GP_PIN(1, 28),	/* CLKOUT */
-		[ 1] = RCAR_GP_PIN(1, 20),	/* CS0_N */
-		[ 2] = RCAR_GP_PIN(1, 21),	/* CS1_N */
-		[ 3] = RCAR_GP_PIN(1, 22),	/* BS_N */
-		[ 4] = RCAR_GP_PIN(1, 23),	/* RD_N */
-		[ 5] = RCAR_GP_PIN(1, 24),	/* RD_WR_N */
-		[ 6] = RCAR_GP_PIN(1, 25),	/* WE0_N */
-		[ 7] = RCAR_GP_PIN(1, 26),	/* WE1_N */
-		[ 8] = RCAR_GP_PIN(1, 27),	/* EX_WAIT0_A */
-		[ 9] = PIN_PRESETOUT_N,		/* PRESETOUT# */
-		[10] = RCAR_GP_PIN(0,  0),	/* D0 */
-		[11] = RCAR_GP_PIN(0,  1),	/* D1 */
-		[12] = RCAR_GP_PIN(0,  2),	/* D2 */
-		[13] = RCAR_GP_PIN(0,  3),	/* D3 */
-		[14] = RCAR_GP_PIN(0,  4),	/* D4 */
-		[15] = RCAR_GP_PIN(0,  5),	/* D5 */
-		[16] = RCAR_GP_PIN(0,  6),	/* D6 */
-		[17] = RCAR_GP_PIN(0,  7),	/* D7 */
-		[18] = RCAR_GP_PIN(0,  8),	/* D8 */
-		[19] = RCAR_GP_PIN(0,  9),	/* D9 */
-		[20] = RCAR_GP_PIN(0, 10),	/* D10 */
-		[21] = RCAR_GP_PIN(0, 11),	/* D11 */
-		[22] = RCAR_GP_PIN(0, 12),	/* D12 */
-		[23] = RCAR_GP_PIN(0, 13),	/* D13 */
-		[24] = RCAR_GP_PIN(0, 14),	/* D14 */
-		[25] = RCAR_GP_PIN(0, 15),	/* D15 */
-		[26] = RCAR_GP_PIN(7,  0),	/* AVS1 */
-		[27] = RCAR_GP_PIN(7,  1),	/* AVS2 */
-		[28] = RCAR_GP_PIN(7,  2),	/* GP7_02 */
-		[29] = RCAR_GP_PIN(7,  3),	/* GP7_03 */
-		[30] = PIN_DU_DOTCLKIN0,	/* DU_DOTCLKIN0 */
-		[31] = PIN_DU_DOTCLKIN1,	/* DU_DOTCLKIN1 */
-	} },
-	{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
-		[ 0] = PIN_DU_DOTCLKIN2,	/* DU_DOTCLKIN2 */
-		[ 1] = PIN_DU_DOTCLKIN3,	/* DU_DOTCLKIN3 */
-		[ 2] = PIN_FSCLKST_N,		/* FSCLKST# */
-		[ 3] = PIN_EXTALR,		/* EXTALR*/
-		[ 4] = PIN_TRST_N,		/* TRST# */
-		[ 5] = PIN_TCK,			/* TCK */
-		[ 6] = PIN_TMS,			/* TMS */
-		[ 7] = PIN_TDI,			/* TDI */
-		[ 8] = SH_PFC_PIN_NONE,
-		[ 9] = PIN_ASEBRK,		/* ASEBRK */
-		[10] = RCAR_GP_PIN(3,  0),	/* SD0_CLK */
-		[11] = RCAR_GP_PIN(3,  1),	/* SD0_CMD */
-		[12] = RCAR_GP_PIN(3,  2),	/* SD0_DAT0 */
-		[13] = RCAR_GP_PIN(3,  3),	/* SD0_DAT1 */
-		[14] = RCAR_GP_PIN(3,  4),	/* SD0_DAT2 */
-		[15] = RCAR_GP_PIN(3,  5),	/* SD0_DAT3 */
-		[16] = RCAR_GP_PIN(3,  6),	/* SD1_CLK */
-		[17] = RCAR_GP_PIN(3,  7),	/* SD1_CMD */
-		[18] = RCAR_GP_PIN(3,  8),	/* SD1_DAT0 */
-		[19] = RCAR_GP_PIN(3,  9),	/* SD1_DAT1 */
-		[20] = RCAR_GP_PIN(3, 10),	/* SD1_DAT2 */
-		[21] = RCAR_GP_PIN(3, 11),	/* SD1_DAT3 */
-		[22] = RCAR_GP_PIN(4,  0),	/* SD2_CLK */
-		[23] = RCAR_GP_PIN(4,  1),	/* SD2_CMD */
-		[24] = RCAR_GP_PIN(4,  2),	/* SD2_DAT0 */
-		[25] = RCAR_GP_PIN(4,  3),	/* SD2_DAT1 */
-		[26] = RCAR_GP_PIN(4,  4),	/* SD2_DAT2 */
-		[27] = RCAR_GP_PIN(4,  5),	/* SD2_DAT3 */
-		[28] = RCAR_GP_PIN(4,  6),	/* SD2_DS */
-		[29] = RCAR_GP_PIN(4,  7),	/* SD3_CLK */
-		[30] = RCAR_GP_PIN(4,  8),	/* SD3_CMD */
-		[31] = RCAR_GP_PIN(4,  9),	/* SD3_DAT0 */
-	} },
-	{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
-		[ 0] = RCAR_GP_PIN(4, 10),	/* SD3_DAT1 */
-		[ 1] = RCAR_GP_PIN(4, 11),	/* SD3_DAT2 */
-		[ 2] = RCAR_GP_PIN(4, 12),	/* SD3_DAT3 */
-		[ 3] = RCAR_GP_PIN(4, 13),	/* SD3_DAT4 */
-		[ 4] = RCAR_GP_PIN(4, 14),	/* SD3_DAT5 */
-		[ 5] = RCAR_GP_PIN(4, 15),	/* SD3_DAT6 */
-		[ 6] = RCAR_GP_PIN(4, 16),	/* SD3_DAT7 */
-		[ 7] = RCAR_GP_PIN(4, 17),	/* SD3_DS */
-		[ 8] = RCAR_GP_PIN(3, 12),	/* SD0_CD */
-		[ 9] = RCAR_GP_PIN(3, 13),	/* SD0_WP */
-		[10] = RCAR_GP_PIN(3, 14),	/* SD1_CD */
-		[11] = RCAR_GP_PIN(3, 15),	/* SD1_WP */
-		[12] = RCAR_GP_PIN(5,  0),	/* SCK0 */
-		[13] = RCAR_GP_PIN(5,  1),	/* RX0 */
-		[14] = RCAR_GP_PIN(5,  2),	/* TX0 */
-		[15] = RCAR_GP_PIN(5,  3),	/* CTS0_N */
-		[16] = RCAR_GP_PIN(5,  4),	/* RTS0_N */
-		[17] = RCAR_GP_PIN(5,  5),	/* RX1_A */
-		[18] = RCAR_GP_PIN(5,  6),	/* TX1_A */
-		[19] = RCAR_GP_PIN(5,  7),	/* CTS1_N */
-		[20] = RCAR_GP_PIN(5,  8),	/* RTS1_N */
-		[21] = RCAR_GP_PIN(5,  9),	/* SCK2 */
-		[22] = RCAR_GP_PIN(5, 10),	/* TX2_A */
-		[23] = RCAR_GP_PIN(5, 11),	/* RX2_A */
-		[24] = RCAR_GP_PIN(5, 12),	/* HSCK0 */
-		[25] = RCAR_GP_PIN(5, 13),	/* HRX0 */
-		[26] = RCAR_GP_PIN(5, 14),	/* HTX0 */
-		[27] = RCAR_GP_PIN(5, 15),	/* HCTS0_N */
-		[28] = RCAR_GP_PIN(5, 16),	/* HRTS0_N */
-		[29] = RCAR_GP_PIN(5, 17),	/* MSIOF0_SCK */
-		[30] = RCAR_GP_PIN(5, 18),	/* MSIOF0_SYNC */
-		[31] = RCAR_GP_PIN(5, 19),	/* MSIOF0_SS1 */
-	} },
-	{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
-		[ 0] = RCAR_GP_PIN(5, 20),	/* MSIOF0_TXD */
-		[ 1] = RCAR_GP_PIN(5, 21),	/* MSIOF0_SS2 */
-		[ 2] = RCAR_GP_PIN(5, 22),	/* MSIOF0_RXD */
-		[ 3] = RCAR_GP_PIN(5, 23),	/* MLB_CLK */
-		[ 4] = RCAR_GP_PIN(5, 24),	/* MLB_SIG */
-		[ 5] = RCAR_GP_PIN(5, 25),	/* MLB_DAT */
-		[ 6] = PIN_MLB_REF,		/* MLB_REF */
-		[ 7] = RCAR_GP_PIN(6,  0),	/* SSI_SCK01239 */
-		[ 8] = RCAR_GP_PIN(6,  1),	/* SSI_WS01239 */
-		[ 9] = RCAR_GP_PIN(6,  2),	/* SSI_SDATA0 */
-		[10] = RCAR_GP_PIN(6,  3),	/* SSI_SDATA1_A */
-		[11] = RCAR_GP_PIN(6,  4),	/* SSI_SDATA2_A */
-		[12] = RCAR_GP_PIN(6,  5),	/* SSI_SCK349 */
-		[13] = RCAR_GP_PIN(6,  6),	/* SSI_WS349 */
-		[14] = RCAR_GP_PIN(6,  7),	/* SSI_SDATA3 */
-		[15] = RCAR_GP_PIN(6,  8),	/* SSI_SCK4 */
-		[16] = RCAR_GP_PIN(6,  9),	/* SSI_WS4 */
-		[17] = RCAR_GP_PIN(6, 10),	/* SSI_SDATA4 */
-		[18] = RCAR_GP_PIN(6, 11),	/* SSI_SCK5 */
-		[19] = RCAR_GP_PIN(6, 12),	/* SSI_WS5 */
-		[20] = RCAR_GP_PIN(6, 13),	/* SSI_SDATA5 */
-		[21] = RCAR_GP_PIN(6, 14),	/* SSI_SCK6 */
-		[22] = RCAR_GP_PIN(6, 15),	/* SSI_WS6 */
-		[23] = RCAR_GP_PIN(6, 16),	/* SSI_SDATA6 */
-		[24] = RCAR_GP_PIN(6, 17),	/* SSI_SCK78 */
-		[25] = RCAR_GP_PIN(6, 18),	/* SSI_WS78 */
-		[26] = RCAR_GP_PIN(6, 19),	/* SSI_SDATA7 */
-		[27] = RCAR_GP_PIN(6, 20),	/* SSI_SDATA8 */
-		[28] = RCAR_GP_PIN(6, 21),	/* SSI_SDATA9_A */
-		[29] = RCAR_GP_PIN(6, 22),	/* AUDIO_CLKA_A */
-		[30] = RCAR_GP_PIN(6, 23),	/* AUDIO_CLKB_B */
-		[31] = RCAR_GP_PIN(6, 24),	/* USB0_PWEN */
-	} },
-	{ PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
-		[ 0] = RCAR_GP_PIN(6, 25),	/* USB0_OVC */
-		[ 1] = RCAR_GP_PIN(6, 26),	/* USB1_PWEN */
-		[ 2] = RCAR_GP_PIN(6, 27),	/* USB1_OVC */
-		[ 3] = RCAR_GP_PIN(6, 28),	/* USB30_PWEN */
-		[ 4] = RCAR_GP_PIN(6, 29),	/* USB30_OVC */
-		[ 5] = RCAR_GP_PIN(6, 30),	/* USB2_CH3_PWEN */
-		[ 6] = RCAR_GP_PIN(6, 31),	/* USB2_CH3_OVC */
-		[ 7] = SH_PFC_PIN_NONE,
-		[ 8] = SH_PFC_PIN_NONE,
-		[ 9] = SH_PFC_PIN_NONE,
-		[10] = SH_PFC_PIN_NONE,
-		[11] = SH_PFC_PIN_NONE,
-		[12] = SH_PFC_PIN_NONE,
-		[13] = SH_PFC_PIN_NONE,
-		[14] = SH_PFC_PIN_NONE,
-		[15] = SH_PFC_PIN_NONE,
-		[16] = SH_PFC_PIN_NONE,
-		[17] = SH_PFC_PIN_NONE,
-		[18] = SH_PFC_PIN_NONE,
-		[19] = SH_PFC_PIN_NONE,
-		[20] = SH_PFC_PIN_NONE,
-		[21] = SH_PFC_PIN_NONE,
-		[22] = SH_PFC_PIN_NONE,
-		[23] = SH_PFC_PIN_NONE,
-		[24] = SH_PFC_PIN_NONE,
-		[25] = SH_PFC_PIN_NONE,
-		[26] = SH_PFC_PIN_NONE,
-		[27] = SH_PFC_PIN_NONE,
-		[28] = SH_PFC_PIN_NONE,
-		[29] = SH_PFC_PIN_NONE,
-		[30] = SH_PFC_PIN_NONE,
-		[31] = SH_PFC_PIN_NONE,
-	} },
-	{ /* sentinel */ },
-};
-
-static unsigned int r8a77951_pinmux_get_bias(struct sh_pfc *pfc,
-					     unsigned int pin)
-{
-	const struct pinmux_bias_reg *reg;
-	unsigned int bit;
-
-	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
-	if (!reg)
-		return PIN_CONFIG_BIAS_DISABLE;
-
-	if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
-		return PIN_CONFIG_BIAS_DISABLE;
-	else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
-		return PIN_CONFIG_BIAS_PULL_UP;
-	else
-		return PIN_CONFIG_BIAS_PULL_DOWN;
-}
-
-static void r8a77951_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
-				     unsigned int bias)
-{
-	const struct pinmux_bias_reg *reg;
-	u32 enable, updown;
-	unsigned int bit;
-
-	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
-	if (!reg)
-		return;
-
-	enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
-	if (bias != PIN_CONFIG_BIAS_DISABLE)
-		enable |= BIT(bit);
-
-	updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
-	if (bias == PIN_CONFIG_BIAS_PULL_UP)
-		updown |= BIT(bit);
-
-	sh_pfc_write(pfc, reg->pud, updown);
-	sh_pfc_write(pfc, reg->puen, enable);
-}
-
-static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = {
-	.pin_to_pocctrl = r8a77951_pin_to_pocctrl,
-	.get_bias = r8a77951_pinmux_get_bias,
-	.set_bias = r8a77951_pinmux_set_bias,
-};
-
-const struct sh_pfc_soc_info r8a77951_pinmux_info = {
-	.name = "r8a77951_pfc",
-	.ops = &r8a77951_pinmux_ops,
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups,
-	.nr_groups = ARRAY_SIZE(pinmux_groups),
-	.functions = pinmux_functions,
-	.nr_functions = ARRAY_SIZE(pinmux_functions),
-
-	.cfg_regs = pinmux_config_regs,
-	.drive_regs = pinmux_drive_regs,
-	.bias_regs = pinmux_bias_regs,
-	.ioctrl_regs = pinmux_ioctrl_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
deleted file mode 100644
index a2496baca85d..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ /dev/null
@@ -1,6265 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
- *
- * Copyright (C) 2016-2019 Renesas Electronics Corp.
- *
- * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
- *
- * R-Car Gen3 processor support - PFC hardware block.
- *
- * Copyright (C) 2015  Renesas Electronics Corporation
- */
-
-#include <linux/errno.h>
-#include <linux/kernel.h>
-
-#include "core.h"
-#include "sh_pfc.h"
-
-#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
-
-#define CPU_ALL_GP(fn, sfx)						\
-	PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
-
-#define CPU_ALL_NOGP(fn)						\
-	PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS),			\
-	PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
-	PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
-	PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
-	PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
-	PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS),			\
-	PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
-
-/*
- * F_() : just information
- * FM() : macro for FN_xxx / xxx_MARK
- */
-
-/* GPSR0 */
-#define GPSR0_15	F_(D15,			IP7_11_8)
-#define GPSR0_14	F_(D14,			IP7_7_4)
-#define GPSR0_13	F_(D13,			IP7_3_0)
-#define GPSR0_12	F_(D12,			IP6_31_28)
-#define GPSR0_11	F_(D11,			IP6_27_24)
-#define GPSR0_10	F_(D10,			IP6_23_20)
-#define GPSR0_9		F_(D9,			IP6_19_16)
-#define GPSR0_8		F_(D8,			IP6_15_12)
-#define GPSR0_7		F_(D7,			IP6_11_8)
-#define GPSR0_6		F_(D6,			IP6_7_4)
-#define GPSR0_5		F_(D5,			IP6_3_0)
-#define GPSR0_4		F_(D4,			IP5_31_28)
-#define GPSR0_3		F_(D3,			IP5_27_24)
-#define GPSR0_2		F_(D2,			IP5_23_20)
-#define GPSR0_1		F_(D1,			IP5_19_16)
-#define GPSR0_0		F_(D0,			IP5_15_12)
-
-/* GPSR1 */
-#define GPSR1_28	FM(CLKOUT)
-#define GPSR1_27	F_(EX_WAIT0_A,		IP5_11_8)
-#define GPSR1_26	F_(WE1_N,		IP5_7_4)
-#define GPSR1_25	F_(WE0_N,		IP5_3_0)
-#define GPSR1_24	F_(RD_WR_N,		IP4_31_28)
-#define GPSR1_23	F_(RD_N,		IP4_27_24)
-#define GPSR1_22	F_(BS_N,		IP4_23_20)
-#define GPSR1_21	F_(CS1_N,		IP4_19_16)
-#define GPSR1_20	F_(CS0_N,		IP4_15_12)
-#define GPSR1_19	F_(A19,			IP4_11_8)
-#define GPSR1_18	F_(A18,			IP4_7_4)
-#define GPSR1_17	F_(A17,			IP4_3_0)
-#define GPSR1_16	F_(A16,			IP3_31_28)
-#define GPSR1_15	F_(A15,			IP3_27_24)
-#define GPSR1_14	F_(A14,			IP3_23_20)
-#define GPSR1_13	F_(A13,			IP3_19_16)
-#define GPSR1_12	F_(A12,			IP3_15_12)
-#define GPSR1_11	F_(A11,			IP3_11_8)
-#define GPSR1_10	F_(A10,			IP3_7_4)
-#define GPSR1_9		F_(A9,			IP3_3_0)
-#define GPSR1_8		F_(A8,			IP2_31_28)
-#define GPSR1_7		F_(A7,			IP2_27_24)
-#define GPSR1_6		F_(A6,			IP2_23_20)
-#define GPSR1_5		F_(A5,			IP2_19_16)
-#define GPSR1_4		F_(A4,			IP2_15_12)
-#define GPSR1_3		F_(A3,			IP2_11_8)
-#define GPSR1_2		F_(A2,			IP2_7_4)
-#define GPSR1_1		F_(A1,			IP2_3_0)
-#define GPSR1_0		F_(A0,			IP1_31_28)
-
-/* GPSR2 */
-#define GPSR2_14	F_(AVB_AVTP_CAPTURE_A,	IP0_23_20)
-#define GPSR2_13	F_(AVB_AVTP_MATCH_A,	IP0_19_16)
-#define GPSR2_12	F_(AVB_LINK,		IP0_15_12)
-#define GPSR2_11	F_(AVB_PHY_INT,		IP0_11_8)
-#define GPSR2_10	F_(AVB_MAGIC,		IP0_7_4)
-#define GPSR2_9		F_(AVB_MDC,		IP0_3_0)
-#define GPSR2_8		F_(PWM2_A,		IP1_27_24)
-#define GPSR2_7		F_(PWM1_A,		IP1_23_20)
-#define GPSR2_6		F_(PWM0,		IP1_19_16)
-#define GPSR2_5		F_(IRQ5,		IP1_15_12)
-#define GPSR2_4		F_(IRQ4,		IP1_11_8)
-#define GPSR2_3		F_(IRQ3,		IP1_7_4)
-#define GPSR2_2		F_(IRQ2,		IP1_3_0)
-#define GPSR2_1		F_(IRQ1,		IP0_31_28)
-#define GPSR2_0		F_(IRQ0,		IP0_27_24)
-
-/* GPSR3 */
-#define GPSR3_15	F_(SD1_WP,		IP11_23_20)
-#define GPSR3_14	F_(SD1_CD,		IP11_19_16)
-#define GPSR3_13	F_(SD0_WP,		IP11_15_12)
-#define GPSR3_12	F_(SD0_CD,		IP11_11_8)
-#define GPSR3_11	F_(SD1_DAT3,		IP8_31_28)
-#define GPSR3_10	F_(SD1_DAT2,		IP8_27_24)
-#define GPSR3_9		F_(SD1_DAT1,		IP8_23_20)
-#define GPSR3_8		F_(SD1_DAT0,		IP8_19_16)
-#define GPSR3_7		F_(SD1_CMD,		IP8_15_12)
-#define GPSR3_6		F_(SD1_CLK,		IP8_11_8)
-#define GPSR3_5		F_(SD0_DAT3,		IP8_7_4)
-#define GPSR3_4		F_(SD0_DAT2,		IP8_3_0)
-#define GPSR3_3		F_(SD0_DAT1,		IP7_31_28)
-#define GPSR3_2		F_(SD0_DAT0,		IP7_27_24)
-#define GPSR3_1		F_(SD0_CMD,		IP7_23_20)
-#define GPSR3_0		F_(SD0_CLK,		IP7_19_16)
-
-/* GPSR4 */
-#define GPSR4_17	F_(SD3_DS,		IP11_7_4)
-#define GPSR4_16	F_(SD3_DAT7,		IP11_3_0)
-#define GPSR4_15	F_(SD3_DAT6,		IP10_31_28)
-#define GPSR4_14	F_(SD3_DAT5,		IP10_27_24)
-#define GPSR4_13	F_(SD3_DAT4,		IP10_23_20)
-#define GPSR4_12	F_(SD3_DAT3,		IP10_19_16)
-#define GPSR4_11	F_(SD3_DAT2,		IP10_15_12)
-#define GPSR4_10	F_(SD3_DAT1,		IP10_11_8)
-#define GPSR4_9		F_(SD3_DAT0,		IP10_7_4)
-#define GPSR4_8		F_(SD3_CMD,		IP10_3_0)
-#define GPSR4_7		F_(SD3_CLK,		IP9_31_28)
-#define GPSR4_6		F_(SD2_DS,		IP9_27_24)
-#define GPSR4_5		F_(SD2_DAT3,		IP9_23_20)
-#define GPSR4_4		F_(SD2_DAT2,		IP9_19_16)
-#define GPSR4_3		F_(SD2_DAT1,		IP9_15_12)
-#define GPSR4_2		F_(SD2_DAT0,		IP9_11_8)
-#define GPSR4_1		F_(SD2_CMD,		IP9_7_4)
-#define GPSR4_0		F_(SD2_CLK,		IP9_3_0)
-
-/* GPSR5 */
-#define GPSR5_25	F_(MLB_DAT,		IP14_19_16)
-#define GPSR5_24	F_(MLB_SIG,		IP14_15_12)
-#define GPSR5_23	F_(MLB_CLK,		IP14_11_8)
-#define GPSR5_22	FM(MSIOF0_RXD)
-#define GPSR5_21	F_(MSIOF0_SS2,		IP14_7_4)
-#define GPSR5_20	FM(MSIOF0_TXD)
-#define GPSR5_19	F_(MSIOF0_SS1,		IP14_3_0)
-#define GPSR5_18	F_(MSIOF0_SYNC,		IP13_31_28)
-#define GPSR5_17	FM(MSIOF0_SCK)
-#define GPSR5_16	F_(HRTS0_N,		IP13_27_24)
-#define GPSR5_15	F_(HCTS0_N,		IP13_23_20)
-#define GPSR5_14	F_(HTX0,		IP13_19_16)
-#define GPSR5_13	F_(HRX0,		IP13_15_12)
-#define GPSR5_12	F_(HSCK0,		IP13_11_8)
-#define GPSR5_11	F_(RX2_A,		IP13_7_4)
-#define GPSR5_10	F_(TX2_A,		IP13_3_0)
-#define GPSR5_9		F_(SCK2,		IP12_31_28)
-#define GPSR5_8		F_(RTS1_N,		IP12_27_24)
-#define GPSR5_7		F_(CTS1_N,		IP12_23_20)
-#define GPSR5_6		F_(TX1_A,		IP12_19_16)
-#define GPSR5_5		F_(RX1_A,		IP12_15_12)
-#define GPSR5_4		F_(RTS0_N,		IP12_11_8)
-#define GPSR5_3		F_(CTS0_N,		IP12_7_4)
-#define GPSR5_2		F_(TX0,			IP12_3_0)
-#define GPSR5_1		F_(RX0,			IP11_31_28)
-#define GPSR5_0		F_(SCK0,		IP11_27_24)
-
-/* GPSR6 */
-#define GPSR6_31	F_(GP6_31,		IP18_7_4)
-#define GPSR6_30	F_(GP6_30,		IP18_3_0)
-#define GPSR6_29	F_(USB30_OVC,		IP17_31_28)
-#define GPSR6_28	F_(USB30_PWEN,		IP17_27_24)
-#define GPSR6_27	F_(USB1_OVC,		IP17_23_20)
-#define GPSR6_26	F_(USB1_PWEN,		IP17_19_16)
-#define GPSR6_25	F_(USB0_OVC,		IP17_15_12)
-#define GPSR6_24	F_(USB0_PWEN,		IP17_11_8)
-#define GPSR6_23	F_(AUDIO_CLKB_B,	IP17_7_4)
-#define GPSR6_22	F_(AUDIO_CLKA_A,	IP17_3_0)
-#define GPSR6_21	F_(SSI_SDATA9_A,	IP16_31_28)
-#define GPSR6_20	F_(SSI_SDATA8,		IP16_27_24)
-#define GPSR6_19	F_(SSI_SDATA7,		IP16_23_20)
-#define GPSR6_18	F_(SSI_WS78,		IP16_19_16)
-#define GPSR6_17	F_(SSI_SCK78,		IP16_15_12)
-#define GPSR6_16	F_(SSI_SDATA6,		IP16_11_8)
-#define GPSR6_15	F_(SSI_WS6,		IP16_7_4)
-#define GPSR6_14	F_(SSI_SCK6,		IP16_3_0)
-#define GPSR6_13	FM(SSI_SDATA5)
-#define GPSR6_12	FM(SSI_WS5)
-#define GPSR6_11	FM(SSI_SCK5)
-#define GPSR6_10	F_(SSI_SDATA4,		IP15_31_28)
-#define GPSR6_9		F_(SSI_WS4,		IP15_27_24)
-#define GPSR6_8		F_(SSI_SCK4,		IP15_23_20)
-#define GPSR6_7		F_(SSI_SDATA3,		IP15_19_16)
-#define GPSR6_6		F_(SSI_WS349,		IP15_15_12)
-#define GPSR6_5		F_(SSI_SCK349,		IP15_11_8)
-#define GPSR6_4		F_(SSI_SDATA2_A,	IP15_7_4)
-#define GPSR6_3		F_(SSI_SDATA1_A,	IP15_3_0)
-#define GPSR6_2		F_(SSI_SDATA0,		IP14_31_28)
-#define GPSR6_1		F_(SSI_WS01239,		IP14_27_24)
-#define GPSR6_0		F_(SSI_SCK01239,	IP14_23_20)
-
-/* GPSR7 */
-#define GPSR7_3		FM(GP7_03)
-#define GPSR7_2		FM(GP7_02)
-#define GPSR7_1		FM(AVS2)
-#define GPSR7_0		FM(AVS1)
-
-
-/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
-#define IP0_3_0		FM(AVB_MDC)		F_(0, 0)	FM(MSIOF2_SS2_C)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_7_4		FM(AVB_MAGIC)		F_(0, 0)	FM(MSIOF2_SS1_C)	FM(SCK4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_11_8	FM(AVB_PHY_INT)		F_(0, 0)	FM(MSIOF2_SYNC_C)	FM(RX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_15_12	FM(AVB_LINK)		F_(0, 0)	FM(MSIOF2_SCK_C)	FM(TX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_19_16	FM(AVB_AVTP_MATCH_A)	F_(0, 0)	FM(MSIOF2_RXD_C)	FM(CTS4_N_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_23_20	FM(AVB_AVTP_CAPTURE_A)	F_(0, 0)	FM(MSIOF2_TXD_C)	FM(RTS4_N_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_27_24	FM(IRQ0)		FM(QPOLB)	F_(0, 0)		FM(DU_CDE)			FM(VI4_DATA0_B) FM(CAN0_TX_B)	FM(CANFD0_TX_B)		FM(MSIOF3_SS2_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_31_28	FM(IRQ1)		FM(QPOLA)	F_(0, 0)		FM(DU_DISP)			FM(VI4_DATA1_B) FM(CAN0_RX_B)	FM(CANFD0_RX_B)		FM(MSIOF3_SS1_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_3_0		FM(IRQ2)		FM(QCPV_QDE)	F_(0, 0)		FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(VI4_DATA2_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SYNC_E) F_(0, 0)		FM(PWM3_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_7_4		FM(IRQ3)		FM(QSTVB_QVE)	F_(0, 0)		FM(DU_DOTCLKOUT1)		FM(VI4_DATA3_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SCK_E) F_(0, 0)		FM(PWM4_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_11_8	FM(IRQ4)		FM(QSTH_QHS)	F_(0, 0)		FM(DU_EXHSYNC_DU_HSYNC)		FM(VI4_DATA4_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_RXD_E) F_(0, 0)		FM(PWM5_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_15_12	FM(IRQ5)		FM(QSTB_QHE)	F_(0, 0)		FM(DU_EXVSYNC_DU_VSYNC)		FM(VI4_DATA5_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_TXD_E) F_(0, 0)		FM(PWM6_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_19_16	FM(PWM0)		FM(AVB_AVTP_PPS)F_(0, 0)		F_(0, 0)			FM(VI4_DATA6_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IECLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_23_20	FM(PWM1_A)		F_(0, 0)	F_(0, 0)		FM(HRX3_D)			FM(VI4_DATA7_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IERX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_27_24	FM(PWM2_A)		F_(0, 0)	F_(0, 0)		FM(HTX3_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IETX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_31_28	FM(A0)			FM(LCDOUT16)	FM(MSIOF3_SYNC_B)	F_(0, 0)			FM(VI4_DATA8)	F_(0, 0)	FM(DU_DB0)		F_(0, 0)	F_(0, 0)		FM(PWM3_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_3_0		FM(A1)			FM(LCDOUT17)	FM(MSIOF3_TXD_B)	F_(0, 0)			FM(VI4_DATA9)	F_(0, 0)	FM(DU_DB1)		F_(0, 0)	F_(0, 0)		FM(PWM4_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_7_4		FM(A2)			FM(LCDOUT18)	FM(MSIOF3_SCK_B)	F_(0, 0)			FM(VI4_DATA10)	F_(0, 0)	FM(DU_DB2)		F_(0, 0)	F_(0, 0)		FM(PWM5_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_11_8	FM(A3)			FM(LCDOUT19)	FM(MSIOF3_RXD_B)	F_(0, 0)			FM(VI4_DATA11)	F_(0, 0)	FM(DU_DB3)		F_(0, 0)	F_(0, 0)		FM(PWM6_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_15_12	FM(A4)			FM(LCDOUT20)	FM(MSIOF3_SS1_B)	F_(0, 0)			FM(VI4_DATA12)	FM(VI5_DATA12)	FM(DU_DB4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_19_16	FM(A5)			FM(LCDOUT21)	FM(MSIOF3_SS2_B)	FM(SCK4_B)			FM(VI4_DATA13)	FM(VI5_DATA13)	FM(DU_DB5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_23_20	FM(A6)			FM(LCDOUT22)	FM(MSIOF2_SS1_A)	FM(RX4_B)			FM(VI4_DATA14)	FM(VI5_DATA14)	FM(DU_DB6)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_27_24	FM(A7)			FM(LCDOUT23)	FM(MSIOF2_SS2_A)	FM(TX4_B)			FM(VI4_DATA15)	FM(VI5_DATA15)	FM(DU_DB7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_31_28	FM(A8)			FM(RX3_B)	FM(MSIOF2_SYNC_A)	FM(HRX4_B)			F_(0, 0)	F_(0, 0)	F_(0, 0)		FM(SDA6_A)	FM(AVB_AVTP_MATCH_B)	FM(PWM1_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_3_0		FM(A9)			F_(0, 0)	FM(MSIOF2_SCK_A)	FM(CTS4_N_B)			F_(0, 0)	FM(VI5_VSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_7_4		FM(A10)			F_(0, 0)	FM(MSIOF2_RXD_A)	FM(RTS4_N_B)			F_(0, 0)	FM(VI5_HSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_11_8	FM(A11)			FM(TX3_B)	FM(MSIOF2_TXD_A)	FM(HTX4_B)			FM(HSCK4)	FM(VI5_FIELD)	F_(0, 0)		FM(SCL6_A)	FM(AVB_AVTP_CAPTURE_B)	FM(PWM2_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
-#define IP3_15_12	FM(A12)			FM(LCDOUT12)	FM(MSIOF3_SCK_C)	F_(0, 0)			FM(HRX4_A)	FM(VI5_DATA8)	FM(DU_DG4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_19_16	FM(A13)			FM(LCDOUT13)	FM(MSIOF3_SYNC_C)	F_(0, 0)			FM(HTX4_A)	FM(VI5_DATA9)	FM(DU_DG5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_23_20	FM(A14)			FM(LCDOUT14)	FM(MSIOF3_RXD_C)	F_(0, 0)			FM(HCTS4_N)	FM(VI5_DATA10)	FM(DU_DG6)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_27_24	FM(A15)			FM(LCDOUT15)	FM(MSIOF3_TXD_C)	F_(0, 0)			FM(HRTS4_N)	FM(VI5_DATA11)	FM(DU_DG7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_31_28	FM(A16)			FM(LCDOUT8)	F_(0, 0)		F_(0, 0)			FM(VI4_FIELD)	F_(0, 0)	FM(DU_DG0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_3_0		FM(A17)			FM(LCDOUT9)	F_(0, 0)		F_(0, 0)			FM(VI4_VSYNC_N)	F_(0, 0)	FM(DU_DG1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_7_4		FM(A18)			FM(LCDOUT10)	F_(0, 0)		F_(0, 0)			FM(VI4_HSYNC_N)	F_(0, 0)	FM(DU_DG2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_11_8	FM(A19)			FM(LCDOUT11)	F_(0, 0)		F_(0, 0)			FM(VI4_CLKENB)	F_(0, 0)	FM(DU_DG3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_15_12	FM(CS0_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(VI5_CLKENB)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_19_16	FM(CS1_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(VI5_CLK)	F_(0, 0)		FM(EX_WAIT0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_23_20	FM(BS_N)		FM(QSTVA_QVS)	FM(MSIOF3_SCK_D)	FM(SCK3)			FM(HSCK3)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN1_TX)		FM(CANFD1_TX)	FM(IETX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_27_24	FM(RD_N)		F_(0, 0)	FM(MSIOF3_SYNC_D)	FM(RX3_A)			FM(HRX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_TX_A)		FM(CANFD0_TX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_31_28	FM(RD_WR_N)		F_(0, 0)	FM(MSIOF3_RXD_D)	FM(TX3_A)			FM(HTX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_RX_A)		FM(CANFD0_RX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_3_0		FM(WE0_N)		F_(0, 0)	FM(MSIOF3_TXD_D)	FM(CTS3_N)			FM(HCTS3_N)	F_(0, 0)	F_(0, 0)		FM(SCL6_B)	FM(CAN_CLK)		F_(0, 0)	FM(IECLK_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_7_4		FM(WE1_N)		F_(0, 0)	FM(MSIOF3_SS1_D)	FM(RTS3_N)			FM(HRTS3_N)	F_(0, 0)	F_(0, 0)		FM(SDA6_B)	FM(CAN1_RX)		FM(CANFD1_RX)	FM(IERX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_11_8	FM(EX_WAIT0_A)		FM(QCLK)	F_(0, 0)		F_(0, 0)			FM(VI4_CLK)	F_(0, 0)	FM(DU_DOTCLKOUT0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_15_12	FM(D0)			FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)	F_(0, 0)			FM(VI4_DATA16)	FM(VI5_DATA0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_19_16	FM(D1)			FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)	F_(0, 0)			FM(VI4_DATA17)	FM(VI5_DATA1)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_23_20	FM(D2)			F_(0, 0)	FM(MSIOF3_RXD_A)	F_(0, 0)			FM(VI4_DATA18)	FM(VI5_DATA2)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_27_24	FM(D3)			F_(0, 0)	FM(MSIOF3_TXD_A)	F_(0, 0)			FM(VI4_DATA19)	FM(VI5_DATA3)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_31_28	FM(D4)			FM(MSIOF2_SCK_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA20)	FM(VI5_DATA4)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_3_0		FM(D5)			FM(MSIOF2_SYNC_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA21)	FM(VI5_DATA5)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_7_4		FM(D6)			FM(MSIOF2_RXD_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA22)	FM(VI5_DATA6)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_11_8	FM(D7)			FM(MSIOF2_TXD_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA23)	FM(VI5_DATA7)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_15_12	FM(D8)			FM(LCDOUT0)	FM(MSIOF2_SCK_D)	FM(SCK4_C)			FM(VI4_DATA0_A)	F_(0, 0)	FM(DU_DR0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_19_16	FM(D9)			FM(LCDOUT1)	FM(MSIOF2_SYNC_D)	F_(0, 0)			FM(VI4_DATA1_A)	F_(0, 0)	FM(DU_DR1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_23_20	FM(D10)			FM(LCDOUT2)	FM(MSIOF2_RXD_D)	FM(HRX3_B)			FM(VI4_DATA2_A)	FM(CTS4_N_C)	FM(DU_DR2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_27_24	FM(D11)			FM(LCDOUT3)	FM(MSIOF2_TXD_D)	FM(HTX3_B)			FM(VI4_DATA3_A)	FM(RTS4_N_C)	FM(DU_DR3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_31_28	FM(D12)			FM(LCDOUT4)	FM(MSIOF2_SS1_D)	FM(RX4_C)			FM(VI4_DATA4_A)	F_(0, 0)	FM(DU_DR4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
-#define IP7_3_0		FM(D13)			FM(LCDOUT5)	FM(MSIOF2_SS2_D)	FM(TX4_C)			FM(VI4_DATA5_A)	F_(0, 0)	FM(DU_DR5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_7_4		FM(D14)			FM(LCDOUT6)	FM(MSIOF3_SS1_A)	FM(HRX3_C)			FM(VI4_DATA6_A)	F_(0, 0)	FM(DU_DR6)		FM(SCL6_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_11_8	FM(D15)			FM(LCDOUT7)	FM(MSIOF3_SS2_A)	FM(HTX3_C)			FM(VI4_DATA7_A)	F_(0, 0)	FM(DU_DR7)		FM(SDA6_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_19_16	FM(SD0_CLK)		F_(0, 0)	FM(MSIOF1_SCK_E)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_OPWM_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_23_20	FM(SD0_CMD)		F_(0, 0)	FM(MSIOF1_SYNC_E)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_27_24	FM(SD0_DAT0)		F_(0, 0)	FM(MSIOF1_RXD_E)	F_(0, 0)			F_(0, 0)	FM(TS_SCK0_B)	FM(STP_ISCLK_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_31_28	FM(SD0_DAT1)		F_(0, 0)	FM(MSIOF1_TXD_E)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_3_0		FM(SD0_DAT2)		F_(0, 0)	FM(MSIOF1_SS1_E)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_B)	FM(STP_ISD_0_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_7_4		FM(SD0_DAT3)		F_(0, 0)	FM(MSIOF1_SS2_E)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_B)	FM(STP_ISEN_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_11_8	FM(SD1_CLK)		F_(0, 0)	FM(MSIOF1_SCK_G)	F_(0, 0)			F_(0, 0)	FM(SIM0_CLK_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_15_12	FM(SD1_CMD)		F_(0, 0)	FM(MSIOF1_SYNC_G)	FM(NFCE_N_B)			F_(0, 0)	FM(SIM0_D_A)	FM(STP_IVCXO27_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_19_16	FM(SD1_DAT0)		FM(SD2_DAT4)	FM(MSIOF1_RXD_G)	FM(NFWP_N_B)			F_(0, 0)	FM(TS_SCK1_B)	FM(STP_ISCLK_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_23_20	FM(SD1_DAT1)		FM(SD2_DAT5)	FM(MSIOF1_TXD_G)	FM(NFDATA14_B)			F_(0, 0)	FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_27_24	FM(SD1_DAT2)		FM(SD2_DAT6)	FM(MSIOF1_SS1_G)	FM(NFDATA15_B)			F_(0, 0)	FM(TS_SDAT1_B)	FM(STP_ISD_1_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_31_28	FM(SD1_DAT3)		FM(SD2_DAT7)	FM(MSIOF1_SS2_G)	FM(NFRB_N_B)			F_(0, 0)	FM(TS_SDEN1_B)	FM(STP_ISEN_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_3_0		FM(SD2_CLK)		F_(0, 0)	FM(NFDATA8)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_7_4		FM(SD2_CMD)		F_(0, 0)	FM(NFDATA9)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_11_8	FM(SD2_DAT0)		F_(0, 0)	FM(NFDATA10)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_15_12	FM(SD2_DAT1)		F_(0, 0)	FM(NFDATA11)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_19_16	FM(SD2_DAT2)		F_(0, 0)	FM(NFDATA12)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_23_20	FM(SD2_DAT3)		F_(0, 0)	FM(NFDATA13)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_27_24	FM(SD2_DS)		F_(0, 0)	FM(NFALE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_31_28	FM(SD3_CLK)		F_(0, 0)	FM(NFWE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_3_0	FM(SD3_CMD)		F_(0, 0)	FM(NFRE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_7_4	FM(SD3_DAT0)		F_(0, 0)	FM(NFDATA0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_11_8	FM(SD3_DAT1)		F_(0, 0)	FM(NFDATA1)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_15_12	FM(SD3_DAT2)		F_(0, 0)	FM(NFDATA2)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_19_16	FM(SD3_DAT3)		F_(0, 0)	FM(NFDATA3)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_23_20	FM(SD3_DAT4)		FM(SD2_CD_A)	FM(NFDATA4)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_27_24	FM(SD3_DAT5)		FM(SD2_WP_A)	FM(NFDATA5)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_31_28	FM(SD3_DAT6)		FM(SD3_CD)	FM(NFDATA6)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_3_0	FM(SD3_DAT7)		FM(SD3_WP)	FM(NFDATA7)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_7_4	FM(SD3_DS)		F_(0, 0)	FM(NFCLE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_11_8	FM(SD0_CD)		F_(0, 0)	FM(NFDATA14_A)		F_(0, 0)			FM(SCL2_B)	FM(SIM0_RST_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
-#define IP11_15_12	FM(SD0_WP)		F_(0, 0)	FM(NFDATA15_A)		F_(0, 0)			FM(SDA2_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_19_16	FM(SD1_CD)		F_(0, 0)	FM(NFRB_N_A)		F_(0, 0)			F_(0, 0)	FM(SIM0_CLK_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_23_20	FM(SD1_WP)		F_(0, 0)	FM(NFCE_N_A)		F_(0, 0)			F_(0, 0)	FM(SIM0_D_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_27_24	FM(SCK0)		FM(HSCK1_B)	FM(MSIOF1_SS2_B)	FM(AUDIO_CLKC_B)		FM(SDA2_A)	FM(SIM0_RST_B)	FM(STP_OPWM_0_C)	FM(RIF0_CLK_B)	F_(0, 0)		FM(ADICHS2)	FM(SCK5_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_31_28	FM(RX0)			FM(HRX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SCK0_C)	FM(STP_ISCLK_0_C)	FM(RIF0_D0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_3_0	FM(TX0)			FM(HTX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)	FM(RIF0_D1_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_7_4	FM(CTS0_N)		FM(HCTS1_N_B)	FM(MSIOF1_SYNC_B)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)	FM(RIF1_SYNC_B)	FM(AUDIO_CLKOUT_C)	FM(ADICS_SAMP)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_11_8	FM(RTS0_N)		FM(HRTS1_N_B)	FM(MSIOF1_SS1_B)	FM(AUDIO_CLKA_B)		FM(SCL2_A)	F_(0, 0)	FM(STP_IVCXO27_1_C)	FM(RIF0_SYNC_B)	F_(0, 0)		FM(ADICHS1)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_15_12	FM(RX1_A)		FM(HRX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_C)	FM(STP_ISD_0_C)		FM(RIF1_CLK_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_19_16	FM(TX1_A)		FM(HTX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_C)	FM(STP_ISEN_0_C)	FM(RIF1_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_23_20	FM(CTS1_N)		FM(HCTS1_N_A)	FM(MSIOF1_RXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_C)	FM(STP_ISEN_1_C)	FM(RIF1_D0_B)	F_(0, 0)		FM(ADIDATA)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_27_24	FM(RTS1_N)		FM(HRTS1_N_A)	FM(MSIOF1_TXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_C)	FM(STP_ISD_1_C)		FM(RIF1_D1_B)	F_(0, 0)		FM(ADICHS0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_31_28	FM(SCK2)		FM(SCIF_CLK_B)	FM(MSIOF1_SCK_B)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_C)	FM(STP_ISCLK_1_C)	FM(RIF1_CLK_B)	F_(0, 0)		FM(ADICLK)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_3_0	FM(TX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_CD_B)			FM(SCL1_A)	F_(0, 0)	FM(FMCLK_A)		FM(RIF1_D1_C)	F_(0, 0)		FM(FSO_CFE_0_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_7_4	FM(RX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_WP_B)			FM(SDA1_A)	F_(0, 0)	FM(FMIN_A)		FM(RIF1_SYNC_C)	F_(0, 0)		FM(FSO_CFE_1_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_11_8	FM(HSCK0)		F_(0, 0)	FM(MSIOF1_SCK_D)	FM(AUDIO_CLKB_A)		FM(SSI_SDATA1_B)FM(TS_SCK0_D)	FM(STP_ISCLK_0_D)	FM(RIF0_CLK_C)	F_(0, 0)		F_(0, 0)	FM(RX5_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_15_12	FM(HRX0)		F_(0, 0)	FM(MSIOF1_RXD_D)	F_(0, 0)			FM(SSI_SDATA2_B)FM(TS_SDEN0_D)	FM(STP_ISEN_0_D)	FM(RIF0_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_19_16	FM(HTX0)		F_(0, 0)	FM(MSIOF1_TXD_D)	F_(0, 0)			FM(SSI_SDATA9_B)FM(TS_SDAT0_D)	FM(STP_ISD_0_D)		FM(RIF0_D1_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_23_20	FM(HCTS0_N)		FM(RX2_B)	FM(MSIOF1_SYNC_D)	F_(0, 0)			FM(SSI_SCK9_A)	FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)	FM(RIF0_SYNC_C)	FM(AUDIO_CLKOUT1_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_27_24	FM(HRTS0_N)		FM(TX2_B)	FM(MSIOF1_SS1_D)	F_(0, 0)			FM(SSI_WS9_A)	F_(0, 0)	FM(STP_IVCXO27_0_D)	FM(BPFCLK_A)	FM(AUDIO_CLKOUT2_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_31_28	FM(MSIOF0_SYNC)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(AUDIO_CLKOUT_A)	F_(0, 0)	FM(TX5_B)	F_(0, 0)	F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
-#define IP14_3_0	FM(MSIOF0_SS1)		FM(RX5_A)	FM(NFWP_N_A)		FM(AUDIO_CLKA_C)		FM(SSI_SCK2_A)	F_(0, 0)	FM(STP_IVCXO27_0_C)	F_(0, 0)	FM(AUDIO_CLKOUT3_A)	F_(0, 0)	FM(TCLK1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_7_4	FM(MSIOF0_SS2)		FM(TX5_A)	FM(MSIOF1_SS2_D)	FM(AUDIO_CLKC_A)		FM(SSI_WS2_A)	F_(0, 0)	FM(STP_OPWM_0_D)	F_(0, 0)	FM(AUDIO_CLKOUT_D)	F_(0, 0)	FM(SPEEDIN_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_11_8	FM(MLB_CLK)		F_(0, 0)	FM(MSIOF1_SCK_F)	F_(0, 0)			FM(SCL1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_15_12	FM(MLB_SIG)		FM(RX1_B)	FM(MSIOF1_SYNC_F)	F_(0, 0)			FM(SDA1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_19_16	FM(MLB_DAT)		FM(TX1_B)	FM(MSIOF1_RXD_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_23_20	FM(SSI_SCK01239)	F_(0, 0)	FM(MSIOF1_TXD_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_27_24	FM(SSI_WS01239)		F_(0, 0)	FM(MSIOF1_SS1_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
-#define IP14_31_28	FM(SSI_SDATA0)		F_(0, 0)	FM(MSIOF1_SS2_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_3_0	FM(SSI_SDATA1_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_7_4	FM(SSI_SDATA2_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			FM(SSI_SCK1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_11_8	FM(SSI_SCK349)		F_(0, 0)	FM(MSIOF1_SS1_A)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_OPWM_0_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_15_12	FM(SSI_WS349)		FM(HCTS2_N_A)	FM(MSIOF1_SS2_A)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_0_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_19_16	FM(SSI_SDATA3)		FM(HRTS2_N_A)	FM(MSIOF1_TXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SCK0_A)	FM(STP_ISCLK_0_A)	FM(RIF0_D1_A)	FM(RIF2_D0_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_23_20	FM(SSI_SCK4)		FM(HRX2_A)	FM(MSIOF1_SCK_A)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_A)	FM(STP_ISD_0_A)		FM(RIF0_CLK_A)	FM(RIF2_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_27_24	FM(SSI_WS4)		FM(HTX2_A)	FM(MSIOF1_SYNC_A)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_A)	FM(STP_ISEN_0_A)	FM(RIF0_SYNC_A)	FM(RIF2_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_31_28	FM(SSI_SDATA4)		FM(HSCK2_A)	FM(MSIOF1_RXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)	FM(RIF0_D0_A)	FM(RIF2_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_3_0	FM(SSI_SCK6)		F_(0, 0)	F_(0, 0)		FM(SIM0_RST_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_7_4	FM(SSI_WS6)		F_(0, 0)	F_(0, 0)		FM(SIM0_D_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_11_8	FM(SSI_SDATA6)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_15_12	FM(SSI_SCK78)		FM(HRX2_B)	FM(MSIOF1_SCK_C)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_A)	FM(STP_ISCLK_1_A)	FM(RIF1_CLK_A)	FM(RIF3_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_19_16	FM(SSI_WS78)		FM(HTX2_B)	FM(MSIOF1_SYNC_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_A)	FM(STP_ISD_1_A)		FM(RIF1_SYNC_A)	FM(RIF3_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_23_20	FM(SSI_SDATA7)		FM(HCTS2_N_B)	FM(MSIOF1_RXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_A)	FM(STP_ISEN_1_A)	FM(RIF1_D0_A)	FM(RIF3_D0_A)		F_(0, 0)	FM(TCLK2_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_27_24	FM(SSI_SDATA8)		FM(HRTS2_N_B)	FM(MSIOF1_TXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)	FM(RIF1_D1_A)	FM(RIF3_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_31_28	FM(SSI_SDATA9_A)	FM(HSCK2_B)	FM(MSIOF1_SS1_C)	FM(HSCK1_A)			FM(SSI_WS1_B)	FM(SCK1)	FM(STP_IVCXO27_1_A)	FM(SCK5_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP17_3_0	FM(AUDIO_CLKA_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP17_7_4	FM(AUDIO_CLKB_B)	FM(SCIF_CLK_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_1_D)	FM(REMOCON_A)	F_(0, 0)		F_(0, 0)	FM(TCLK1_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP17_11_8	FM(USB0_PWEN)		F_(0, 0)	F_(0, 0)		FM(SIM0_RST_C)			F_(0, 0)	FM(TS_SCK1_D)	FM(STP_ISCLK_1_D)	FM(BPFCLK_B)	FM(RIF3_CLK_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
-#define IP17_15_12	FM(USB0_OVC)		F_(0, 0)	F_(0, 0)		FM(SIM0_D_C)			F_(0, 0)	FM(TS_SDAT1_D)	FM(STP_ISD_1_D)		F_(0, 0)	FM(RIF3_SYNC_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
-#define IP17_19_16	FM(USB1_PWEN)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_C)			FM(SSI_SCK1_A)	FM(TS_SCK0_E)	FM(STP_ISCLK_0_E)	FM(FMCLK_B)	FM(RIF2_CLK_B)		F_(0, 0)	FM(SPEEDIN_A)	F_(0, 0)	F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
-#define IP17_23_20	FM(USB1_OVC)		F_(0, 0)	FM(MSIOF1_SS2_C)	F_(0, 0)			FM(SSI_WS1_A)	FM(TS_SDAT0_E)	FM(STP_ISD_0_E)		FM(FMIN_B)	FM(RIF2_SYNC_B)		F_(0, 0)	FM(REMOCON_B)	F_(0, 0)	F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
-#define IP17_27_24	FM(USB30_PWEN)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT_B)		FM(SSI_SCK2_B)	FM(TS_SDEN1_D)	FM(STP_ISEN_1_D)	FM(STP_OPWM_0_E)FM(RIF3_D0_B)		F_(0, 0)	FM(TCLK2_B)	FM(TPU0TO0)	FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
-#define IP17_31_28	FM(USB30_OVC)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT1_B)		FM(SSI_WS2_B)	FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)	FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)	F_(0, 0)	FM(FSO_TOE_N)	FM(TPU0TO1)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP18_3_0	FM(GP6_30)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT2_B)		FM(SSI_SCK9_B)	FM(TS_SDEN0_E)	FM(STP_ISEN_0_E)	F_(0, 0)	FM(RIF2_D0_B)		F_(0, 0)	F_(0, 0)	FM(TPU0TO2)	FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
-#define IP18_7_4	FM(GP6_31)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT3_B)		FM(SSI_WS9_B)	FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)	F_(0, 0)	FM(RIF2_D1_B)		F_(0, 0)	F_(0, 0)	FM(TPU0TO3)	FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
-
-#define PINMUX_GPSR	\
-\
-												GPSR6_31 \
-												GPSR6_30 \
-												GPSR6_29 \
-		GPSR1_28									GPSR6_28 \
-		GPSR1_27									GPSR6_27 \
-		GPSR1_26									GPSR6_26 \
-		GPSR1_25							GPSR5_25	GPSR6_25 \
-		GPSR1_24							GPSR5_24	GPSR6_24 \
-		GPSR1_23							GPSR5_23	GPSR6_23 \
-		GPSR1_22							GPSR5_22	GPSR6_22 \
-		GPSR1_21							GPSR5_21	GPSR6_21 \
-		GPSR1_20							GPSR5_20	GPSR6_20 \
-		GPSR1_19							GPSR5_19	GPSR6_19 \
-		GPSR1_18							GPSR5_18	GPSR6_18 \
-		GPSR1_17					GPSR4_17	GPSR5_17	GPSR6_17 \
-		GPSR1_16					GPSR4_16	GPSR5_16	GPSR6_16 \
-GPSR0_15	GPSR1_15			GPSR3_15	GPSR4_15	GPSR5_15	GPSR6_15 \
-GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14	GPSR4_14	GPSR5_14	GPSR6_14 \
-GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13	GPSR4_13	GPSR5_13	GPSR6_13 \
-GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12	GPSR4_12	GPSR5_12	GPSR6_12 \
-GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11	GPSR4_11	GPSR5_11	GPSR6_11 \
-GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10	GPSR6_10 \
-GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9		GPSR6_9 \
-GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8		GPSR6_8 \
-GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7		GPSR6_7 \
-GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6		GPSR6_6 \
-GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5		GPSR6_5 \
-GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4		GPSR6_4 \
-GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3		GPSR6_3		GPSR7_3 \
-GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2		GPSR6_2		GPSR7_2 \
-GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1		GPSR6_1		GPSR7_1 \
-GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0		GPSR6_0		GPSR7_0
-
-#define PINMUX_IPSR				\
-\
-FM(IP0_3_0)	IP0_3_0		FM(IP1_3_0)	IP1_3_0		FM(IP2_3_0)	IP2_3_0		FM(IP3_3_0)	IP3_3_0 \
-FM(IP0_7_4)	IP0_7_4		FM(IP1_7_4)	IP1_7_4		FM(IP2_7_4)	IP2_7_4		FM(IP3_7_4)	IP3_7_4 \
-FM(IP0_11_8)	IP0_11_8	FM(IP1_11_8)	IP1_11_8	FM(IP2_11_8)	IP2_11_8	FM(IP3_11_8)	IP3_11_8 \
-FM(IP0_15_12)	IP0_15_12	FM(IP1_15_12)	IP1_15_12	FM(IP2_15_12)	IP2_15_12	FM(IP3_15_12)	IP3_15_12 \
-FM(IP0_19_16)	IP0_19_16	FM(IP1_19_16)	IP1_19_16	FM(IP2_19_16)	IP2_19_16	FM(IP3_19_16)	IP3_19_16 \
-FM(IP0_23_20)	IP0_23_20	FM(IP1_23_20)	IP1_23_20	FM(IP2_23_20)	IP2_23_20	FM(IP3_23_20)	IP3_23_20 \
-FM(IP0_27_24)	IP0_27_24	FM(IP1_27_24)	IP1_27_24	FM(IP2_27_24)	IP2_27_24	FM(IP3_27_24)	IP3_27_24 \
-FM(IP0_31_28)	IP0_31_28	FM(IP1_31_28)	IP1_31_28	FM(IP2_31_28)	IP2_31_28	FM(IP3_31_28)	IP3_31_28 \
-\
-FM(IP4_3_0)	IP4_3_0		FM(IP5_3_0)	IP5_3_0		FM(IP6_3_0)	IP6_3_0		FM(IP7_3_0)	IP7_3_0 \
-FM(IP4_7_4)	IP4_7_4		FM(IP5_7_4)	IP5_7_4		FM(IP6_7_4)	IP6_7_4		FM(IP7_7_4)	IP7_7_4 \
-FM(IP4_11_8)	IP4_11_8	FM(IP5_11_8)	IP5_11_8	FM(IP6_11_8)	IP6_11_8	FM(IP7_11_8)	IP7_11_8 \
-FM(IP4_15_12)	IP4_15_12	FM(IP5_15_12)	IP5_15_12	FM(IP6_15_12)	IP6_15_12 \
-FM(IP4_19_16)	IP4_19_16	FM(IP5_19_16)	IP5_19_16	FM(IP6_19_16)	IP6_19_16	FM(IP7_19_16)	IP7_19_16 \
-FM(IP4_23_20)	IP4_23_20	FM(IP5_23_20)	IP5_23_20	FM(IP6_23_20)	IP6_23_20	FM(IP7_23_20)	IP7_23_20 \
-FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
-FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
-\
-FM(IP8_3_0)	IP8_3_0		FM(IP9_3_0)	IP9_3_0		FM(IP10_3_0)	IP10_3_0	FM(IP11_3_0)	IP11_3_0 \
-FM(IP8_7_4)	IP8_7_4		FM(IP9_7_4)	IP9_7_4		FM(IP10_7_4)	IP10_7_4	FM(IP11_7_4)	IP11_7_4 \
-FM(IP8_11_8)	IP8_11_8	FM(IP9_11_8)	IP9_11_8	FM(IP10_11_8)	IP10_11_8	FM(IP11_11_8)	IP11_11_8 \
-FM(IP8_15_12)	IP8_15_12	FM(IP9_15_12)	IP9_15_12	FM(IP10_15_12)	IP10_15_12	FM(IP11_15_12)	IP11_15_12 \
-FM(IP8_19_16)	IP8_19_16	FM(IP9_19_16)	IP9_19_16	FM(IP10_19_16)	IP10_19_16	FM(IP11_19_16)	IP11_19_16 \
-FM(IP8_23_20)	IP8_23_20	FM(IP9_23_20)	IP9_23_20	FM(IP10_23_20)	IP10_23_20	FM(IP11_23_20)	IP11_23_20 \
-FM(IP8_27_24)	IP8_27_24	FM(IP9_27_24)	IP9_27_24	FM(IP10_27_24)	IP10_27_24	FM(IP11_27_24)	IP11_27_24 \
-FM(IP8_31_28)	IP8_31_28	FM(IP9_31_28)	IP9_31_28	FM(IP10_31_28)	IP10_31_28	FM(IP11_31_28)	IP11_31_28 \
-\
-FM(IP12_3_0)	IP12_3_0	FM(IP13_3_0)	IP13_3_0	FM(IP14_3_0)	IP14_3_0	FM(IP15_3_0)	IP15_3_0 \
-FM(IP12_7_4)	IP12_7_4	FM(IP13_7_4)	IP13_7_4	FM(IP14_7_4)	IP14_7_4	FM(IP15_7_4)	IP15_7_4 \
-FM(IP12_11_8)	IP12_11_8	FM(IP13_11_8)	IP13_11_8	FM(IP14_11_8)	IP14_11_8	FM(IP15_11_8)	IP15_11_8 \
-FM(IP12_15_12)	IP12_15_12	FM(IP13_15_12)	IP13_15_12	FM(IP14_15_12)	IP14_15_12	FM(IP15_15_12)	IP15_15_12 \
-FM(IP12_19_16)	IP12_19_16	FM(IP13_19_16)	IP13_19_16	FM(IP14_19_16)	IP14_19_16	FM(IP15_19_16)	IP15_19_16 \
-FM(IP12_23_20)	IP12_23_20	FM(IP13_23_20)	IP13_23_20	FM(IP14_23_20)	IP14_23_20	FM(IP15_23_20)	IP15_23_20 \
-FM(IP12_27_24)	IP12_27_24	FM(IP13_27_24)	IP13_27_24	FM(IP14_27_24)	IP14_27_24	FM(IP15_27_24)	IP15_27_24 \
-FM(IP12_31_28)	IP12_31_28	FM(IP13_31_28)	IP13_31_28	FM(IP14_31_28)	IP14_31_28	FM(IP15_31_28)	IP15_31_28 \
-\
-FM(IP16_3_0)	IP16_3_0	FM(IP17_3_0)	IP17_3_0	FM(IP18_3_0)	IP18_3_0 \
-FM(IP16_7_4)	IP16_7_4	FM(IP17_7_4)	IP17_7_4	FM(IP18_7_4)	IP18_7_4 \
-FM(IP16_11_8)	IP16_11_8	FM(IP17_11_8)	IP17_11_8 \
-FM(IP16_15_12)	IP16_15_12	FM(IP17_15_12)	IP17_15_12 \
-FM(IP16_19_16)	IP16_19_16	FM(IP17_19_16)	IP17_19_16 \
-FM(IP16_23_20)	IP16_23_20	FM(IP17_23_20)	IP17_23_20 \
-FM(IP16_27_24)	IP16_27_24	FM(IP17_27_24)	IP17_27_24 \
-FM(IP16_31_28)	IP16_31_28	FM(IP17_31_28)	IP17_31_28
-
-/* MOD_SEL0 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
-#define MOD_SEL0_31_30_29	FM(SEL_MSIOF3_0)	FM(SEL_MSIOF3_1)	FM(SEL_MSIOF3_2)	FM(SEL_MSIOF3_3)	FM(SEL_MSIOF3_4)	F_(0, 0)		F_(0, 0)		F_(0, 0)
-#define MOD_SEL0_28_27		FM(SEL_MSIOF2_0)	FM(SEL_MSIOF2_1)	FM(SEL_MSIOF2_2)	FM(SEL_MSIOF2_3)
-#define MOD_SEL0_26_25_24	FM(SEL_MSIOF1_0)	FM(SEL_MSIOF1_1)	FM(SEL_MSIOF1_2)	FM(SEL_MSIOF1_3)	FM(SEL_MSIOF1_4)	FM(SEL_MSIOF1_5)	FM(SEL_MSIOF1_6)	F_(0, 0)
-#define MOD_SEL0_23		FM(SEL_LBSC_0)		FM(SEL_LBSC_1)
-#define MOD_SEL0_22		FM(SEL_IEBUS_0)		FM(SEL_IEBUS_1)
-#define MOD_SEL0_21		FM(SEL_I2C2_0)		FM(SEL_I2C2_1)
-#define MOD_SEL0_20		FM(SEL_I2C1_0)		FM(SEL_I2C1_1)
-#define MOD_SEL0_19		FM(SEL_HSCIF4_0)	FM(SEL_HSCIF4_1)
-#define MOD_SEL0_18_17		FM(SEL_HSCIF3_0)	FM(SEL_HSCIF3_1)	FM(SEL_HSCIF3_2)	FM(SEL_HSCIF3_3)
-#define MOD_SEL0_16		FM(SEL_HSCIF1_0)	FM(SEL_HSCIF1_1)
-#define MOD_SEL0_14_13		FM(SEL_HSCIF2_0)	FM(SEL_HSCIF2_1)	FM(SEL_HSCIF2_2)	F_(0, 0)
-#define MOD_SEL0_12		FM(SEL_ETHERAVB_0)	FM(SEL_ETHERAVB_1)
-#define MOD_SEL0_11		FM(SEL_DRIF3_0)		FM(SEL_DRIF3_1)
-#define MOD_SEL0_10		FM(SEL_DRIF2_0)		FM(SEL_DRIF2_1)
-#define MOD_SEL0_9_8		FM(SEL_DRIF1_0)		FM(SEL_DRIF1_1)		FM(SEL_DRIF1_2)		F_(0, 0)
-#define MOD_SEL0_7_6		FM(SEL_DRIF0_0)		FM(SEL_DRIF0_1)		FM(SEL_DRIF0_2)		F_(0, 0)
-#define MOD_SEL0_5		FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
-#define MOD_SEL0_4_3		FM(SEL_ADGA_0)		FM(SEL_ADGA_1)		FM(SEL_ADGA_2)		FM(SEL_ADGA_3)
-
-/* MOD_SEL1 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
-#define MOD_SEL1_31_30		FM(SEL_TSIF1_0)		FM(SEL_TSIF1_1)		FM(SEL_TSIF1_2)		FM(SEL_TSIF1_3)
-#define MOD_SEL1_29_28_27	FM(SEL_TSIF0_0)		FM(SEL_TSIF0_1)		FM(SEL_TSIF0_2)		FM(SEL_TSIF0_3)		FM(SEL_TSIF0_4)		F_(0, 0)		F_(0, 0)		F_(0, 0)
-#define MOD_SEL1_26		FM(SEL_TIMER_TMU_0)	FM(SEL_TIMER_TMU_1)
-#define MOD_SEL1_25_24		FM(SEL_SSP1_1_0)	FM(SEL_SSP1_1_1)	FM(SEL_SSP1_1_2)	FM(SEL_SSP1_1_3)
-#define MOD_SEL1_23_22_21	FM(SEL_SSP1_0_0)	FM(SEL_SSP1_0_1)	FM(SEL_SSP1_0_2)	FM(SEL_SSP1_0_3)	FM(SEL_SSP1_0_4)	F_(0, 0)		F_(0, 0)		F_(0, 0)
-#define MOD_SEL1_20		FM(SEL_SSI1_0)		FM(SEL_SSI1_1)
-#define MOD_SEL1_19		FM(SEL_SPEED_PULSE_0)	FM(SEL_SPEED_PULSE_1)
-#define MOD_SEL1_18_17		FM(SEL_SIMCARD_0)	FM(SEL_SIMCARD_1)	FM(SEL_SIMCARD_2)	FM(SEL_SIMCARD_3)
-#define MOD_SEL1_16		FM(SEL_SDHI2_0)		FM(SEL_SDHI2_1)
-#define MOD_SEL1_15_14		FM(SEL_SCIF4_0)		FM(SEL_SCIF4_1)		FM(SEL_SCIF4_2)		F_(0, 0)
-#define MOD_SEL1_13		FM(SEL_SCIF3_0)		FM(SEL_SCIF3_1)
-#define MOD_SEL1_12		FM(SEL_SCIF2_0)		FM(SEL_SCIF2_1)
-#define MOD_SEL1_11		FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
-#define MOD_SEL1_10		FM(SEL_SCIF_0)		FM(SEL_SCIF_1)
-#define MOD_SEL1_9		FM(SEL_REMOCON_0)	FM(SEL_REMOCON_1)
-#define MOD_SEL1_6		FM(SEL_RCAN0_0)		FM(SEL_RCAN0_1)
-#define MOD_SEL1_5		FM(SEL_PWM6_0)		FM(SEL_PWM6_1)
-#define MOD_SEL1_4		FM(SEL_PWM5_0)		FM(SEL_PWM5_1)
-#define MOD_SEL1_3		FM(SEL_PWM4_0)		FM(SEL_PWM4_1)
-#define MOD_SEL1_2		FM(SEL_PWM3_0)		FM(SEL_PWM3_1)
-#define MOD_SEL1_1		FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
-#define MOD_SEL1_0		FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
-
-/* MOD_SEL2 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
-#define MOD_SEL2_31		FM(I2C_SEL_5_0)		FM(I2C_SEL_5_1)
-#define MOD_SEL2_30		FM(I2C_SEL_3_0)		FM(I2C_SEL_3_1)
-#define MOD_SEL2_29		FM(I2C_SEL_0_0)		FM(I2C_SEL_0_1)
-#define MOD_SEL2_28_27		FM(SEL_FM_0)		FM(SEL_FM_1)		FM(SEL_FM_2)		FM(SEL_FM_3)
-#define MOD_SEL2_26		FM(SEL_SCIF5_0)		FM(SEL_SCIF5_1)
-#define MOD_SEL2_25_24_23	FM(SEL_I2C6_0)		FM(SEL_I2C6_1)		FM(SEL_I2C6_2)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)
-#define MOD_SEL2_22		FM(SEL_NDF_0)		FM(SEL_NDF_1)
-#define MOD_SEL2_21		FM(SEL_SSI2_0)		FM(SEL_SSI2_1)
-#define MOD_SEL2_20		FM(SEL_SSI9_0)		FM(SEL_SSI9_1)
-#define MOD_SEL2_19		FM(SEL_TIMER_TMU2_0)	FM(SEL_TIMER_TMU2_1)
-#define MOD_SEL2_18		FM(SEL_ADGB_0)		FM(SEL_ADGB_1)
-#define MOD_SEL2_17		FM(SEL_ADGC_0)		FM(SEL_ADGC_1)
-#define MOD_SEL2_0		FM(SEL_VIN4_0)		FM(SEL_VIN4_1)
-
-#define PINMUX_MOD_SELS	\
-\
-MOD_SEL0_31_30_29	MOD_SEL1_31_30		MOD_SEL2_31 \
-						MOD_SEL2_30 \
-			MOD_SEL1_29_28_27	MOD_SEL2_29 \
-MOD_SEL0_28_27					MOD_SEL2_28_27 \
-MOD_SEL0_26_25_24	MOD_SEL1_26		MOD_SEL2_26 \
-			MOD_SEL1_25_24		MOD_SEL2_25_24_23 \
-MOD_SEL0_23		MOD_SEL1_23_22_21 \
-MOD_SEL0_22					MOD_SEL2_22 \
-MOD_SEL0_21					MOD_SEL2_21 \
-MOD_SEL0_20		MOD_SEL1_20		MOD_SEL2_20 \
-MOD_SEL0_19		MOD_SEL1_19		MOD_SEL2_19 \
-MOD_SEL0_18_17		MOD_SEL1_18_17		MOD_SEL2_18 \
-						MOD_SEL2_17 \
-MOD_SEL0_16		MOD_SEL1_16 \
-			MOD_SEL1_15_14 \
-MOD_SEL0_14_13 \
-			MOD_SEL1_13 \
-MOD_SEL0_12		MOD_SEL1_12 \
-MOD_SEL0_11		MOD_SEL1_11 \
-MOD_SEL0_10		MOD_SEL1_10 \
-MOD_SEL0_9_8		MOD_SEL1_9 \
-MOD_SEL0_7_6 \
-			MOD_SEL1_6 \
-MOD_SEL0_5		MOD_SEL1_5 \
-MOD_SEL0_4_3		MOD_SEL1_4 \
-			MOD_SEL1_3 \
-			MOD_SEL1_2 \
-			MOD_SEL1_1 \
-			MOD_SEL1_0		MOD_SEL2_0
-
-/*
- * These pins are not able to be muxed but have other properties
- * that can be set, such as drive-strength or pull-up/pull-down enable.
- */
-#define PINMUX_STATIC \
-	FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
-	FM(QSPI0_IO2) FM(QSPI0_IO3) \
-	FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
-	FM(QSPI1_IO2) FM(QSPI1_IO3) \
-	FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
-	FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
-	FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
-	FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
-	FM(PRESETOUT) \
-	FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
-	FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
-
-#define PINMUX_PHYS \
-	FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	GP_ALL(DATA),
-	PINMUX_DATA_END,
-
-#define F_(x, y)
-#define FM(x)	FN_##x,
-	PINMUX_FUNCTION_BEGIN,
-	GP_ALL(FN),
-	PINMUX_GPSR
-	PINMUX_IPSR
-	PINMUX_MOD_SELS
-	PINMUX_FUNCTION_END,
-#undef F_
-#undef FM
-
-#define F_(x, y)
-#define FM(x)	x##_MARK,
-	PINMUX_MARK_BEGIN,
-	PINMUX_GPSR
-	PINMUX_IPSR
-	PINMUX_MOD_SELS
-	PINMUX_STATIC
-	PINMUX_PHYS
-	PINMUX_MARK_END,
-#undef F_
-#undef FM
-};
-
-static const u16 pinmux_data[] = {
-	PINMUX_DATA_GP_ALL(),
-
-	PINMUX_SINGLE(AVS1),
-	PINMUX_SINGLE(AVS2),
-	PINMUX_SINGLE(CLKOUT),
-	PINMUX_SINGLE(GP7_03),
-	PINMUX_SINGLE(GP7_02),
-	PINMUX_SINGLE(MSIOF0_RXD),
-	PINMUX_SINGLE(MSIOF0_SCK),
-	PINMUX_SINGLE(MSIOF0_TXD),
-	PINMUX_SINGLE(SSI_SCK5),
-	PINMUX_SINGLE(SSI_SDATA5),
-	PINMUX_SINGLE(SSI_WS5),
-
-	/* IPSR0 */
-	PINMUX_IPSR_GPSR(IP0_3_0,	AVB_MDC),
-	PINMUX_IPSR_MSEL(IP0_3_0,	MSIOF2_SS2_C,		SEL_MSIOF2_2),
-
-	PINMUX_IPSR_GPSR(IP0_7_4,	AVB_MAGIC),
-	PINMUX_IPSR_MSEL(IP0_7_4,	MSIOF2_SS1_C,		SEL_MSIOF2_2),
-	PINMUX_IPSR_MSEL(IP0_7_4,	SCK4_A,			SEL_SCIF4_0),
-
-	PINMUX_IPSR_GPSR(IP0_11_8,	AVB_PHY_INT),
-	PINMUX_IPSR_MSEL(IP0_11_8,	MSIOF2_SYNC_C,		SEL_MSIOF2_2),
-	PINMUX_IPSR_MSEL(IP0_11_8,	RX4_A,			SEL_SCIF4_0),
-
-	PINMUX_IPSR_GPSR(IP0_15_12,	AVB_LINK),
-	PINMUX_IPSR_MSEL(IP0_15_12,	MSIOF2_SCK_C,		SEL_MSIOF2_2),
-	PINMUX_IPSR_MSEL(IP0_15_12,	TX4_A,			SEL_SCIF4_0),
-
-	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,	I2C_SEL_5_0,	SEL_ETHERAVB_0),
-	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C,		I2C_SEL_5_0,	SEL_MSIOF2_2),
-	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A,		I2C_SEL_5_0,	SEL_SCIF4_0),
-	PINMUX_IPSR_PHYS(IP0_19_16,	SCL5,			I2C_SEL_5_1),
-
-	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A,	I2C_SEL_5_0,	SEL_ETHERAVB_0),
-	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C,		I2C_SEL_5_0,	SEL_MSIOF2_2),
-	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A,		I2C_SEL_5_0,	SEL_SCIF4_0),
-	PINMUX_IPSR_PHYS(IP0_23_20,	SDA5,			I2C_SEL_5_1),
-
-	PINMUX_IPSR_GPSR(IP0_27_24,	IRQ0),
-	PINMUX_IPSR_GPSR(IP0_27_24,	QPOLB),
-	PINMUX_IPSR_GPSR(IP0_27_24,	DU_CDE),
-	PINMUX_IPSR_MSEL(IP0_27_24,	VI4_DATA0_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP0_27_24,	CAN0_TX_B,		SEL_RCAN0_1),
-	PINMUX_IPSR_MSEL(IP0_27_24,	CANFD0_TX_B,		SEL_CANFD0_1),
-	PINMUX_IPSR_MSEL(IP0_27_24,	MSIOF3_SS2_E,		SEL_MSIOF3_4),
-
-	PINMUX_IPSR_GPSR(IP0_31_28,	IRQ1),
-	PINMUX_IPSR_GPSR(IP0_31_28,	QPOLA),
-	PINMUX_IPSR_GPSR(IP0_31_28,	DU_DISP),
-	PINMUX_IPSR_MSEL(IP0_31_28,	VI4_DATA1_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP0_31_28,	CAN0_RX_B,		SEL_RCAN0_1),
-	PINMUX_IPSR_MSEL(IP0_31_28,	CANFD0_RX_B,		SEL_CANFD0_1),
-	PINMUX_IPSR_MSEL(IP0_31_28,	MSIOF3_SS1_E,		SEL_MSIOF3_4),
-
-	/* IPSR1 */
-	PINMUX_IPSR_GPSR(IP1_3_0,	IRQ2),
-	PINMUX_IPSR_GPSR(IP1_3_0,	QCPV_QDE),
-	PINMUX_IPSR_GPSR(IP1_3_0,	DU_EXODDF_DU_ODDF_DISP_CDE),
-	PINMUX_IPSR_MSEL(IP1_3_0,	VI4_DATA2_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP1_3_0,	PWM3_B,			SEL_PWM3_1),
-	PINMUX_IPSR_MSEL(IP1_3_0,	MSIOF3_SYNC_E,		SEL_MSIOF3_4),
-
-	PINMUX_IPSR_GPSR(IP1_7_4,	IRQ3),
-	PINMUX_IPSR_GPSR(IP1_7_4,	QSTVB_QVE),
-	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DOTCLKOUT1),
-	PINMUX_IPSR_MSEL(IP1_7_4,	VI4_DATA3_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP1_7_4,	PWM4_B,			SEL_PWM4_1),
-	PINMUX_IPSR_MSEL(IP1_7_4,	MSIOF3_SCK_E,		SEL_MSIOF3_4),
-
-	PINMUX_IPSR_GPSR(IP1_11_8,	IRQ4),
-	PINMUX_IPSR_GPSR(IP1_11_8,	QSTH_QHS),
-	PINMUX_IPSR_GPSR(IP1_11_8,	DU_EXHSYNC_DU_HSYNC),
-	PINMUX_IPSR_MSEL(IP1_11_8,	VI4_DATA4_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP1_11_8,	PWM5_B,			SEL_PWM5_1),
-	PINMUX_IPSR_MSEL(IP1_11_8,	MSIOF3_RXD_E,		SEL_MSIOF3_4),
-
-	PINMUX_IPSR_GPSR(IP1_15_12,	IRQ5),
-	PINMUX_IPSR_GPSR(IP1_15_12,	QSTB_QHE),
-	PINMUX_IPSR_GPSR(IP1_15_12,	DU_EXVSYNC_DU_VSYNC),
-	PINMUX_IPSR_MSEL(IP1_15_12,	VI4_DATA5_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP1_15_12,	PWM6_B,			SEL_PWM6_1),
-	PINMUX_IPSR_MSEL(IP1_15_12,	MSIOF3_TXD_E,		SEL_MSIOF3_4),
-
-	PINMUX_IPSR_GPSR(IP1_19_16,	PWM0),
-	PINMUX_IPSR_GPSR(IP1_19_16,	AVB_AVTP_PPS),
-	PINMUX_IPSR_MSEL(IP1_19_16,	VI4_DATA6_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP1_19_16,	IECLK_B,		SEL_IEBUS_1),
-
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A,		I2C_SEL_3_0,	SEL_PWM1_0),
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B,		I2C_SEL_3_0,	SEL_VIN4_1),
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
-	PINMUX_IPSR_PHYS(IP1_23_20,	SCL3,			I2C_SEL_3_1),
-
-	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A,		I2C_SEL_3_0,	SEL_PWM2_0),
-	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
-	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
-	PINMUX_IPSR_PHYS(IP1_27_24,	SDA3,			I2C_SEL_3_1),
-
-	PINMUX_IPSR_GPSR(IP1_31_28,	A0),
-	PINMUX_IPSR_GPSR(IP1_31_28,	LCDOUT16),
-	PINMUX_IPSR_MSEL(IP1_31_28,	MSIOF3_SYNC_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP1_31_28,	VI4_DATA8),
-	PINMUX_IPSR_GPSR(IP1_31_28,	DU_DB0),
-	PINMUX_IPSR_MSEL(IP1_31_28,	PWM3_A,			SEL_PWM3_0),
-
-	/* IPSR2 */
-	PINMUX_IPSR_GPSR(IP2_3_0,	A1),
-	PINMUX_IPSR_GPSR(IP2_3_0,	LCDOUT17),
-	PINMUX_IPSR_MSEL(IP2_3_0,	MSIOF3_TXD_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP2_3_0,	VI4_DATA9),
-	PINMUX_IPSR_GPSR(IP2_3_0,	DU_DB1),
-	PINMUX_IPSR_MSEL(IP2_3_0,	PWM4_A,			SEL_PWM4_0),
-
-	PINMUX_IPSR_GPSR(IP2_7_4,	A2),
-	PINMUX_IPSR_GPSR(IP2_7_4,	LCDOUT18),
-	PINMUX_IPSR_MSEL(IP2_7_4,	MSIOF3_SCK_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP2_7_4,	VI4_DATA10),
-	PINMUX_IPSR_GPSR(IP2_7_4,	DU_DB2),
-	PINMUX_IPSR_MSEL(IP2_7_4,	PWM5_A,			SEL_PWM5_0),
-
-	PINMUX_IPSR_GPSR(IP2_11_8,	A3),
-	PINMUX_IPSR_GPSR(IP2_11_8,	LCDOUT19),
-	PINMUX_IPSR_MSEL(IP2_11_8,	MSIOF3_RXD_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP2_11_8,	VI4_DATA11),
-	PINMUX_IPSR_GPSR(IP2_11_8,	DU_DB3),
-	PINMUX_IPSR_MSEL(IP2_11_8,	PWM6_A,			SEL_PWM6_0),
-
-	PINMUX_IPSR_GPSR(IP2_15_12,	A4),
-	PINMUX_IPSR_GPSR(IP2_15_12,	LCDOUT20),
-	PINMUX_IPSR_MSEL(IP2_15_12,	MSIOF3_SS1_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP2_15_12,	VI4_DATA12),
-	PINMUX_IPSR_GPSR(IP2_15_12,	VI5_DATA12),
-	PINMUX_IPSR_GPSR(IP2_15_12,	DU_DB4),
-
-	PINMUX_IPSR_GPSR(IP2_19_16,	A5),
-	PINMUX_IPSR_GPSR(IP2_19_16,	LCDOUT21),
-	PINMUX_IPSR_MSEL(IP2_19_16,	MSIOF3_SS2_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_MSEL(IP2_19_16,	SCK4_B,			SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP2_19_16,	VI4_DATA13),
-	PINMUX_IPSR_GPSR(IP2_19_16,	VI5_DATA13),
-	PINMUX_IPSR_GPSR(IP2_19_16,	DU_DB5),
-
-	PINMUX_IPSR_GPSR(IP2_23_20,	A6),
-	PINMUX_IPSR_GPSR(IP2_23_20,	LCDOUT22),
-	PINMUX_IPSR_MSEL(IP2_23_20,	MSIOF2_SS1_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP2_23_20,	RX4_B,			SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP2_23_20,	VI4_DATA14),
-	PINMUX_IPSR_GPSR(IP2_23_20,	VI5_DATA14),
-	PINMUX_IPSR_GPSR(IP2_23_20,	DU_DB6),
-
-	PINMUX_IPSR_GPSR(IP2_27_24,	A7),
-	PINMUX_IPSR_GPSR(IP2_27_24,	LCDOUT23),
-	PINMUX_IPSR_MSEL(IP2_27_24,	MSIOF2_SS2_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP2_27_24,	TX4_B,			SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP2_27_24,	VI4_DATA15),
-	PINMUX_IPSR_GPSR(IP2_27_24,	VI5_DATA15),
-	PINMUX_IPSR_GPSR(IP2_27_24,	DU_DB7),
-
-	PINMUX_IPSR_GPSR(IP2_31_28,	A8),
-	PINMUX_IPSR_MSEL(IP2_31_28,	RX3_B,			SEL_SCIF3_1),
-	PINMUX_IPSR_MSEL(IP2_31_28,	MSIOF2_SYNC_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP2_31_28,	HRX4_B,			SEL_HSCIF4_1),
-	PINMUX_IPSR_MSEL(IP2_31_28,	SDA6_A,			SEL_I2C6_0),
-	PINMUX_IPSR_MSEL(IP2_31_28,	AVB_AVTP_MATCH_B,	SEL_ETHERAVB_1),
-	PINMUX_IPSR_MSEL(IP2_31_28,	PWM1_B,			SEL_PWM1_1),
-
-	/* IPSR3 */
-	PINMUX_IPSR_GPSR(IP3_3_0,	A9),
-	PINMUX_IPSR_MSEL(IP3_3_0,	MSIOF2_SCK_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP3_3_0,	CTS4_N_B,		SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP3_3_0,	VI5_VSYNC_N),
-
-	PINMUX_IPSR_GPSR(IP3_7_4,	A10),
-	PINMUX_IPSR_MSEL(IP3_7_4,	MSIOF2_RXD_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP3_7_4,	RTS4_N_B,		SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP3_7_4,	VI5_HSYNC_N),
-
-	PINMUX_IPSR_GPSR(IP3_11_8,	A11),
-	PINMUX_IPSR_MSEL(IP3_11_8,	TX3_B,			SEL_SCIF3_1),
-	PINMUX_IPSR_MSEL(IP3_11_8,	MSIOF2_TXD_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP3_11_8,	HTX4_B,			SEL_HSCIF4_1),
-	PINMUX_IPSR_GPSR(IP3_11_8,	HSCK4),
-	PINMUX_IPSR_GPSR(IP3_11_8,	VI5_FIELD),
-	PINMUX_IPSR_MSEL(IP3_11_8,	SCL6_A,			SEL_I2C6_0),
-	PINMUX_IPSR_MSEL(IP3_11_8,	AVB_AVTP_CAPTURE_B,	SEL_ETHERAVB_1),
-	PINMUX_IPSR_MSEL(IP3_11_8,	PWM2_B,			SEL_PWM2_1),
-
-	PINMUX_IPSR_GPSR(IP3_15_12,	A12),
-	PINMUX_IPSR_GPSR(IP3_15_12,	LCDOUT12),
-	PINMUX_IPSR_MSEL(IP3_15_12,	MSIOF3_SCK_C,		SEL_MSIOF3_2),
-	PINMUX_IPSR_MSEL(IP3_15_12,	HRX4_A,			SEL_HSCIF4_0),
-	PINMUX_IPSR_GPSR(IP3_15_12,	VI5_DATA8),
-	PINMUX_IPSR_GPSR(IP3_15_12,	DU_DG4),
-
-	PINMUX_IPSR_GPSR(IP3_19_16,	A13),
-	PINMUX_IPSR_GPSR(IP3_19_16,	LCDOUT13),
-	PINMUX_IPSR_MSEL(IP3_19_16,	MSIOF3_SYNC_C,		SEL_MSIOF3_2),
-	PINMUX_IPSR_MSEL(IP3_19_16,	HTX4_A,			SEL_HSCIF4_0),
-	PINMUX_IPSR_GPSR(IP3_19_16,	VI5_DATA9),
-	PINMUX_IPSR_GPSR(IP3_19_16,	DU_DG5),
-
-	PINMUX_IPSR_GPSR(IP3_23_20,	A14),
-	PINMUX_IPSR_GPSR(IP3_23_20,	LCDOUT14),
-	PINMUX_IPSR_MSEL(IP3_23_20,	MSIOF3_RXD_C,		SEL_MSIOF3_2),
-	PINMUX_IPSR_GPSR(IP3_23_20,	HCTS4_N),
-	PINMUX_IPSR_GPSR(IP3_23_20,	VI5_DATA10),
-	PINMUX_IPSR_GPSR(IP3_23_20,	DU_DG6),
-
-	PINMUX_IPSR_GPSR(IP3_27_24,	A15),
-	PINMUX_IPSR_GPSR(IP3_27_24,	LCDOUT15),
-	PINMUX_IPSR_MSEL(IP3_27_24,	MSIOF3_TXD_C,		SEL_MSIOF3_2),
-	PINMUX_IPSR_GPSR(IP3_27_24,	HRTS4_N),
-	PINMUX_IPSR_GPSR(IP3_27_24,	VI5_DATA11),
-	PINMUX_IPSR_GPSR(IP3_27_24,	DU_DG7),
-
-	PINMUX_IPSR_GPSR(IP3_31_28,	A16),
-	PINMUX_IPSR_GPSR(IP3_31_28,	LCDOUT8),
-	PINMUX_IPSR_GPSR(IP3_31_28,	VI4_FIELD),
-	PINMUX_IPSR_GPSR(IP3_31_28,	DU_DG0),
-
-	/* IPSR4 */
-	PINMUX_IPSR_GPSR(IP4_3_0,	A17),
-	PINMUX_IPSR_GPSR(IP4_3_0,	LCDOUT9),
-	PINMUX_IPSR_GPSR(IP4_3_0,	VI4_VSYNC_N),
-	PINMUX_IPSR_GPSR(IP4_3_0,	DU_DG1),
-
-	PINMUX_IPSR_GPSR(IP4_7_4,	A18),
-	PINMUX_IPSR_GPSR(IP4_7_4,	LCDOUT10),
-	PINMUX_IPSR_GPSR(IP4_7_4,	VI4_HSYNC_N),
-	PINMUX_IPSR_GPSR(IP4_7_4,	DU_DG2),
-
-	PINMUX_IPSR_GPSR(IP4_11_8,	A19),
-	PINMUX_IPSR_GPSR(IP4_11_8,	LCDOUT11),
-	PINMUX_IPSR_GPSR(IP4_11_8,	VI4_CLKENB),
-	PINMUX_IPSR_GPSR(IP4_11_8,	DU_DG3),
-
-	PINMUX_IPSR_GPSR(IP4_15_12,	CS0_N),
-	PINMUX_IPSR_GPSR(IP4_15_12,	VI5_CLKENB),
-
-	PINMUX_IPSR_GPSR(IP4_19_16,	CS1_N),
-	PINMUX_IPSR_GPSR(IP4_19_16,	VI5_CLK),
-	PINMUX_IPSR_MSEL(IP4_19_16,	EX_WAIT0_B,		SEL_LBSC_1),
-
-	PINMUX_IPSR_GPSR(IP4_23_20,	BS_N),
-	PINMUX_IPSR_GPSR(IP4_23_20,	QSTVA_QVS),
-	PINMUX_IPSR_MSEL(IP4_23_20,	MSIOF3_SCK_D,		SEL_MSIOF3_3),
-	PINMUX_IPSR_GPSR(IP4_23_20,	SCK3),
-	PINMUX_IPSR_GPSR(IP4_23_20,	HSCK3),
-	PINMUX_IPSR_GPSR(IP4_23_20,	CAN1_TX),
-	PINMUX_IPSR_GPSR(IP4_23_20,	CANFD1_TX),
-	PINMUX_IPSR_MSEL(IP4_23_20,	IETX_A,			SEL_IEBUS_0),
-
-	PINMUX_IPSR_GPSR(IP4_27_24,	RD_N),
-	PINMUX_IPSR_MSEL(IP4_27_24,	MSIOF3_SYNC_D,		SEL_MSIOF3_3),
-	PINMUX_IPSR_MSEL(IP4_27_24,	RX3_A,			SEL_SCIF3_0),
-	PINMUX_IPSR_MSEL(IP4_27_24,	HRX3_A,			SEL_HSCIF3_0),
-	PINMUX_IPSR_MSEL(IP4_27_24,	CAN0_TX_A,		SEL_RCAN0_0),
-	PINMUX_IPSR_MSEL(IP4_27_24,	CANFD0_TX_A,		SEL_CANFD0_0),
-
-	PINMUX_IPSR_GPSR(IP4_31_28,	RD_WR_N),
-	PINMUX_IPSR_MSEL(IP4_31_28,	MSIOF3_RXD_D,		SEL_MSIOF3_3),
-	PINMUX_IPSR_MSEL(IP4_31_28,	TX3_A,			SEL_SCIF3_0),
-	PINMUX_IPSR_MSEL(IP4_31_28,	HTX3_A,			SEL_HSCIF3_0),
-	PINMUX_IPSR_MSEL(IP4_31_28,	CAN0_RX_A,		SEL_RCAN0_0),
-	PINMUX_IPSR_MSEL(IP4_31_28,	CANFD0_RX_A,		SEL_CANFD0_0),
-
-	/* IPSR5 */
-	PINMUX_IPSR_GPSR(IP5_3_0,	WE0_N),
-	PINMUX_IPSR_MSEL(IP5_3_0,	MSIOF3_TXD_D,		SEL_MSIOF3_3),
-	PINMUX_IPSR_GPSR(IP5_3_0,	CTS3_N),
-	PINMUX_IPSR_GPSR(IP5_3_0,	HCTS3_N),
-	PINMUX_IPSR_MSEL(IP5_3_0,	SCL6_B,			SEL_I2C6_1),
-	PINMUX_IPSR_GPSR(IP5_3_0,	CAN_CLK),
-	PINMUX_IPSR_MSEL(IP5_3_0,	IECLK_A,		SEL_IEBUS_0),
-
-	PINMUX_IPSR_GPSR(IP5_7_4,	WE1_N),
-	PINMUX_IPSR_MSEL(IP5_7_4,	MSIOF3_SS1_D,		SEL_MSIOF3_3),
-	PINMUX_IPSR_GPSR(IP5_7_4,	RTS3_N),
-	PINMUX_IPSR_GPSR(IP5_7_4,	HRTS3_N),
-	PINMUX_IPSR_MSEL(IP5_7_4,	SDA6_B,			SEL_I2C6_1),
-	PINMUX_IPSR_GPSR(IP5_7_4,	CAN1_RX),
-	PINMUX_IPSR_GPSR(IP5_7_4,	CANFD1_RX),
-	PINMUX_IPSR_MSEL(IP5_7_4,	IERX_A,			SEL_IEBUS_0),
-
-	PINMUX_IPSR_MSEL(IP5_11_8,	EX_WAIT0_A,		SEL_LBSC_0),
-	PINMUX_IPSR_GPSR(IP5_11_8,	QCLK),
-	PINMUX_IPSR_GPSR(IP5_11_8,	VI4_CLK),
-	PINMUX_IPSR_GPSR(IP5_11_8,	DU_DOTCLKOUT0),
-
-	PINMUX_IPSR_GPSR(IP5_15_12,	D0),
-	PINMUX_IPSR_MSEL(IP5_15_12,	MSIOF2_SS1_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_MSEL(IP5_15_12,	MSIOF3_SCK_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_GPSR(IP5_15_12,	VI4_DATA16),
-	PINMUX_IPSR_GPSR(IP5_15_12,	VI5_DATA0),
-
-	PINMUX_IPSR_GPSR(IP5_19_16,	D1),
-	PINMUX_IPSR_MSEL(IP5_19_16,	MSIOF2_SS2_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_MSEL(IP5_19_16,	MSIOF3_SYNC_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_GPSR(IP5_19_16,	VI4_DATA17),
-	PINMUX_IPSR_GPSR(IP5_19_16,	VI5_DATA1),
-
-	PINMUX_IPSR_GPSR(IP5_23_20,	D2),
-	PINMUX_IPSR_MSEL(IP5_23_20,	MSIOF3_RXD_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_GPSR(IP5_23_20,	VI4_DATA18),
-	PINMUX_IPSR_GPSR(IP5_23_20,	VI5_DATA2),
-
-	PINMUX_IPSR_GPSR(IP5_27_24,	D3),
-	PINMUX_IPSR_MSEL(IP5_27_24,	MSIOF3_TXD_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_GPSR(IP5_27_24,	VI4_DATA19),
-	PINMUX_IPSR_GPSR(IP5_27_24,	VI5_DATA3),
-
-	PINMUX_IPSR_GPSR(IP5_31_28,	D4),
-	PINMUX_IPSR_MSEL(IP5_31_28,	MSIOF2_SCK_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP5_31_28,	VI4_DATA20),
-	PINMUX_IPSR_GPSR(IP5_31_28,	VI5_DATA4),
-
-	/* IPSR6 */
-	PINMUX_IPSR_GPSR(IP6_3_0,	D5),
-	PINMUX_IPSR_MSEL(IP6_3_0,	MSIOF2_SYNC_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP6_3_0,	VI4_DATA21),
-	PINMUX_IPSR_GPSR(IP6_3_0,	VI5_DATA5),
-
-	PINMUX_IPSR_GPSR(IP6_7_4,	D6),
-	PINMUX_IPSR_MSEL(IP6_7_4,	MSIOF2_RXD_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP6_7_4,	VI4_DATA22),
-	PINMUX_IPSR_GPSR(IP6_7_4,	VI5_DATA6),
-
-	PINMUX_IPSR_GPSR(IP6_11_8,	D7),
-	PINMUX_IPSR_MSEL(IP6_11_8,	MSIOF2_TXD_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP6_11_8,	VI4_DATA23),
-	PINMUX_IPSR_GPSR(IP6_11_8,	VI5_DATA7),
-
-	PINMUX_IPSR_GPSR(IP6_15_12,	D8),
-	PINMUX_IPSR_GPSR(IP6_15_12,	LCDOUT0),
-	PINMUX_IPSR_MSEL(IP6_15_12,	MSIOF2_SCK_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP6_15_12,	SCK4_C,			SEL_SCIF4_2),
-	PINMUX_IPSR_MSEL(IP6_15_12,	VI4_DATA0_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP6_15_12,	DU_DR0),
-
-	PINMUX_IPSR_GPSR(IP6_19_16,	D9),
-	PINMUX_IPSR_GPSR(IP6_19_16,	LCDOUT1),
-	PINMUX_IPSR_MSEL(IP6_19_16,	MSIOF2_SYNC_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP6_19_16,	VI4_DATA1_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP6_19_16,	DU_DR1),
-
-	PINMUX_IPSR_GPSR(IP6_23_20,	D10),
-	PINMUX_IPSR_GPSR(IP6_23_20,	LCDOUT2),
-	PINMUX_IPSR_MSEL(IP6_23_20,	MSIOF2_RXD_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP6_23_20,	HRX3_B,			SEL_HSCIF3_1),
-	PINMUX_IPSR_MSEL(IP6_23_20,	VI4_DATA2_A,		SEL_VIN4_0),
-	PINMUX_IPSR_MSEL(IP6_23_20,	CTS4_N_C,		SEL_SCIF4_2),
-	PINMUX_IPSR_GPSR(IP6_23_20,	DU_DR2),
-
-	PINMUX_IPSR_GPSR(IP6_27_24,	D11),
-	PINMUX_IPSR_GPSR(IP6_27_24,	LCDOUT3),
-	PINMUX_IPSR_MSEL(IP6_27_24,	MSIOF2_TXD_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP6_27_24,	HTX3_B,			SEL_HSCIF3_1),
-	PINMUX_IPSR_MSEL(IP6_27_24,	VI4_DATA3_A,		SEL_VIN4_0),
-	PINMUX_IPSR_MSEL(IP6_27_24,	RTS4_N_C,		SEL_SCIF4_2),
-	PINMUX_IPSR_GPSR(IP6_27_24,	DU_DR3),
-
-	PINMUX_IPSR_GPSR(IP6_31_28,	D12),
-	PINMUX_IPSR_GPSR(IP6_31_28,	LCDOUT4),
-	PINMUX_IPSR_MSEL(IP6_31_28,	MSIOF2_SS1_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP6_31_28,	RX4_C,			SEL_SCIF4_2),
-	PINMUX_IPSR_MSEL(IP6_31_28,	VI4_DATA4_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP6_31_28,	DU_DR4),
-
-	/* IPSR7 */
-	PINMUX_IPSR_GPSR(IP7_3_0,	D13),
-	PINMUX_IPSR_GPSR(IP7_3_0,	LCDOUT5),
-	PINMUX_IPSR_MSEL(IP7_3_0,	MSIOF2_SS2_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP7_3_0,	TX4_C,			SEL_SCIF4_2),
-	PINMUX_IPSR_MSEL(IP7_3_0,	VI4_DATA5_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP7_3_0,	DU_DR5),
-
-	PINMUX_IPSR_GPSR(IP7_7_4,	D14),
-	PINMUX_IPSR_GPSR(IP7_7_4,	LCDOUT6),
-	PINMUX_IPSR_MSEL(IP7_7_4,	MSIOF3_SS1_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_MSEL(IP7_7_4,	HRX3_C,			SEL_HSCIF3_2),
-	PINMUX_IPSR_MSEL(IP7_7_4,	VI4_DATA6_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP7_7_4,	DU_DR6),
-	PINMUX_IPSR_MSEL(IP7_7_4,	SCL6_C,			SEL_I2C6_2),
-
-	PINMUX_IPSR_GPSR(IP7_11_8,	D15),
-	PINMUX_IPSR_GPSR(IP7_11_8,	LCDOUT7),
-	PINMUX_IPSR_MSEL(IP7_11_8,	MSIOF3_SS2_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_MSEL(IP7_11_8,	HTX3_C,			SEL_HSCIF3_2),
-	PINMUX_IPSR_MSEL(IP7_11_8,	VI4_DATA7_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP7_11_8,	DU_DR7),
-	PINMUX_IPSR_MSEL(IP7_11_8,	SDA6_C,			SEL_I2C6_2),
-
-	PINMUX_IPSR_GPSR(IP7_19_16,	SD0_CLK),
-	PINMUX_IPSR_MSEL(IP7_19_16,	MSIOF1_SCK_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP7_19_16,	STP_OPWM_0_B,		SEL_SSP1_0_1),
-
-	PINMUX_IPSR_GPSR(IP7_23_20,	SD0_CMD),
-	PINMUX_IPSR_MSEL(IP7_23_20,	MSIOF1_SYNC_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP7_23_20,	STP_IVCXO27_0_B,	SEL_SSP1_0_1),
-
-	PINMUX_IPSR_GPSR(IP7_27_24,	SD0_DAT0),
-	PINMUX_IPSR_MSEL(IP7_27_24,	MSIOF1_RXD_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP7_27_24,	TS_SCK0_B,		SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP7_27_24,	STP_ISCLK_0_B,		SEL_SSP1_0_1),
-
-	PINMUX_IPSR_GPSR(IP7_31_28,	SD0_DAT1),
-	PINMUX_IPSR_MSEL(IP7_31_28,	MSIOF1_TXD_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP7_31_28,	TS_SPSYNC0_B,		SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP7_31_28,	STP_ISSYNC_0_B,		SEL_SSP1_0_1),
-
-	/* IPSR8 */
-	PINMUX_IPSR_GPSR(IP8_3_0,	SD0_DAT2),
-	PINMUX_IPSR_MSEL(IP8_3_0,	MSIOF1_SS1_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP8_3_0,	TS_SDAT0_B,		SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP8_3_0,	STP_ISD_0_B,		SEL_SSP1_0_1),
-
-	PINMUX_IPSR_GPSR(IP8_7_4,	SD0_DAT3),
-	PINMUX_IPSR_MSEL(IP8_7_4,	MSIOF1_SS2_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP8_7_4,	TS_SDEN0_B,		SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP8_7_4,	STP_ISEN_0_B,		SEL_SSP1_0_1),
-
-	PINMUX_IPSR_GPSR(IP8_11_8,	SD1_CLK),
-	PINMUX_IPSR_MSEL(IP8_11_8,	MSIOF1_SCK_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_MSEL(IP8_11_8,	SIM0_CLK_A,		SEL_SIMCARD_0),
-
-	PINMUX_IPSR_GPSR(IP8_15_12,	SD1_CMD),
-	PINMUX_IPSR_MSEL(IP8_15_12,	MSIOF1_SYNC_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_MSEL(IP8_15_12,	NFCE_N_B,		SEL_NDF_1),
-	PINMUX_IPSR_MSEL(IP8_15_12,	SIM0_D_A,		SEL_SIMCARD_0),
-	PINMUX_IPSR_MSEL(IP8_15_12,	STP_IVCXO27_1_B,	SEL_SSP1_1_1),
-
-	PINMUX_IPSR_GPSR(IP8_19_16,	SD1_DAT0),
-	PINMUX_IPSR_GPSR(IP8_19_16,	SD2_DAT4),
-	PINMUX_IPSR_MSEL(IP8_19_16,	MSIOF1_RXD_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_MSEL(IP8_19_16,	NFWP_N_B,		SEL_NDF_1),
-	PINMUX_IPSR_MSEL(IP8_19_16,	TS_SCK1_B,		SEL_TSIF1_1),
-	PINMUX_IPSR_MSEL(IP8_19_16,	STP_ISCLK_1_B,		SEL_SSP1_1_1),
-
-	PINMUX_IPSR_GPSR(IP8_23_20,	SD1_DAT1),
-	PINMUX_IPSR_GPSR(IP8_23_20,	SD2_DAT5),
-	PINMUX_IPSR_MSEL(IP8_23_20,	MSIOF1_TXD_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_MSEL(IP8_23_20,	NFDATA14_B,		SEL_NDF_1),
-	PINMUX_IPSR_MSEL(IP8_23_20,	TS_SPSYNC1_B,		SEL_TSIF1_1),
-	PINMUX_IPSR_MSEL(IP8_23_20,	STP_ISSYNC_1_B,		SEL_SSP1_1_1),
-
-	PINMUX_IPSR_GPSR(IP8_27_24,	SD1_DAT2),
-	PINMUX_IPSR_GPSR(IP8_27_24,	SD2_DAT6),
-	PINMUX_IPSR_MSEL(IP8_27_24,	MSIOF1_SS1_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_MSEL(IP8_27_24,	NFDATA15_B,		SEL_NDF_1),
-	PINMUX_IPSR_MSEL(IP8_27_24,	TS_SDAT1_B,		SEL_TSIF1_1),
-	PINMUX_IPSR_MSEL(IP8_27_24,	STP_ISD_1_B,		SEL_SSP1_1_1),
-
-	PINMUX_IPSR_GPSR(IP8_31_28,	SD1_DAT3),
-	PINMUX_IPSR_GPSR(IP8_31_28,	SD2_DAT7),
-	PINMUX_IPSR_MSEL(IP8_31_28,	MSIOF1_SS2_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_MSEL(IP8_31_28,	NFRB_N_B,		SEL_NDF_1),
-	PINMUX_IPSR_MSEL(IP8_31_28,	TS_SDEN1_B,		SEL_TSIF1_1),
-	PINMUX_IPSR_MSEL(IP8_31_28,	STP_ISEN_1_B,		SEL_SSP1_1_1),
-
-	/* IPSR9 */
-	PINMUX_IPSR_GPSR(IP9_3_0,	SD2_CLK),
-	PINMUX_IPSR_GPSR(IP9_3_0,	NFDATA8),
-
-	PINMUX_IPSR_GPSR(IP9_7_4,	SD2_CMD),
-	PINMUX_IPSR_GPSR(IP9_7_4,	NFDATA9),
-
-	PINMUX_IPSR_GPSR(IP9_11_8,	SD2_DAT0),
-	PINMUX_IPSR_GPSR(IP9_11_8,	NFDATA10),
-
-	PINMUX_IPSR_GPSR(IP9_15_12,	SD2_DAT1),
-	PINMUX_IPSR_GPSR(IP9_15_12,	NFDATA11),
-
-	PINMUX_IPSR_GPSR(IP9_19_16,	SD2_DAT2),
-	PINMUX_IPSR_GPSR(IP9_19_16,	NFDATA12),
-
-	PINMUX_IPSR_GPSR(IP9_23_20,	SD2_DAT3),
-	PINMUX_IPSR_GPSR(IP9_23_20,	NFDATA13),
-
-	PINMUX_IPSR_GPSR(IP9_27_24,	SD2_DS),
-	PINMUX_IPSR_GPSR(IP9_27_24,	NFALE),
-
-	PINMUX_IPSR_GPSR(IP9_31_28,	SD3_CLK),
-	PINMUX_IPSR_GPSR(IP9_31_28,	NFWE_N),
-
-	/* IPSR10 */
-	PINMUX_IPSR_GPSR(IP10_3_0,	SD3_CMD),
-	PINMUX_IPSR_GPSR(IP10_3_0,	NFRE_N),
-
-	PINMUX_IPSR_GPSR(IP10_7_4,	SD3_DAT0),
-	PINMUX_IPSR_GPSR(IP10_7_4,	NFDATA0),
-
-	PINMUX_IPSR_GPSR(IP10_11_8,	SD3_DAT1),
-	PINMUX_IPSR_GPSR(IP10_11_8,	NFDATA1),
-
-	PINMUX_IPSR_GPSR(IP10_15_12,	SD3_DAT2),
-	PINMUX_IPSR_GPSR(IP10_15_12,	NFDATA2),
-
-	PINMUX_IPSR_GPSR(IP10_19_16,	SD3_DAT3),
-	PINMUX_IPSR_GPSR(IP10_19_16,	NFDATA3),
-
-	PINMUX_IPSR_GPSR(IP10_23_20,	SD3_DAT4),
-	PINMUX_IPSR_MSEL(IP10_23_20,	SD2_CD_A,		SEL_SDHI2_0),
-	PINMUX_IPSR_GPSR(IP10_23_20,	NFDATA4),
-
-	PINMUX_IPSR_GPSR(IP10_27_24,	SD3_DAT5),
-	PINMUX_IPSR_MSEL(IP10_27_24,	SD2_WP_A,		SEL_SDHI2_0),
-	PINMUX_IPSR_GPSR(IP10_27_24,	NFDATA5),
-
-	PINMUX_IPSR_GPSR(IP10_31_28,	SD3_DAT6),
-	PINMUX_IPSR_GPSR(IP10_31_28,	SD3_CD),
-	PINMUX_IPSR_GPSR(IP10_31_28,	NFDATA6),
-
-	/* IPSR11 */
-	PINMUX_IPSR_GPSR(IP11_3_0,	SD3_DAT7),
-	PINMUX_IPSR_GPSR(IP11_3_0,	SD3_WP),
-	PINMUX_IPSR_GPSR(IP11_3_0,	NFDATA7),
-
-	PINMUX_IPSR_GPSR(IP11_7_4,	SD3_DS),
-	PINMUX_IPSR_GPSR(IP11_7_4,	NFCLE),
-
-	PINMUX_IPSR_GPSR(IP11_11_8,	SD0_CD),
-	PINMUX_IPSR_MSEL(IP11_11_8,	NFDATA14_A,		SEL_NDF_0),
-	PINMUX_IPSR_MSEL(IP11_11_8,	SCL2_B,			SEL_I2C2_1),
-	PINMUX_IPSR_MSEL(IP11_11_8,	SIM0_RST_A,		SEL_SIMCARD_0),
-
-	PINMUX_IPSR_GPSR(IP11_15_12,	SD0_WP),
-	PINMUX_IPSR_MSEL(IP11_15_12,	NFDATA15_A,		SEL_NDF_0),
-	PINMUX_IPSR_MSEL(IP11_15_12,	SDA2_B,			SEL_I2C2_1),
-
-	PINMUX_IPSR_MSEL(IP11_19_16,	SD1_CD,			I2C_SEL_0_0),
-	PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A,		I2C_SEL_0_0,	SEL_NDF_0),
-	PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B,		I2C_SEL_0_0,	SEL_SIMCARD_1),
-	PINMUX_IPSR_PHYS(IP11_19_16,	SCL0,			I2C_SEL_0_1),
-
-	PINMUX_IPSR_MSEL(IP11_23_20,	SD1_WP,			I2C_SEL_0_0),
-	PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A,		I2C_SEL_0_0,	SEL_NDF_0),
-	PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B,		I2C_SEL_0_0,	SEL_SIMCARD_1),
-	PINMUX_IPSR_PHYS(IP11_23_20,	SDA0,			I2C_SEL_0_1),
-
-	PINMUX_IPSR_GPSR(IP11_27_24,	SCK0),
-	PINMUX_IPSR_MSEL(IP11_27_24,	HSCK1_B,		SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP11_27_24,	MSIOF1_SS2_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP11_27_24,	AUDIO_CLKC_B,		SEL_ADGC_1),
-	PINMUX_IPSR_MSEL(IP11_27_24,	SDA2_A,			SEL_I2C2_0),
-	PINMUX_IPSR_MSEL(IP11_27_24,	SIM0_RST_B,		SEL_SIMCARD_1),
-	PINMUX_IPSR_MSEL(IP11_27_24,	STP_OPWM_0_C,		SEL_SSP1_0_2),
-	PINMUX_IPSR_MSEL(IP11_27_24,	RIF0_CLK_B,		SEL_DRIF0_1),
-	PINMUX_IPSR_GPSR(IP11_27_24,	ADICHS2),
-	PINMUX_IPSR_MSEL(IP11_27_24,	SCK5_B,			SEL_SCIF5_1),
-
-	PINMUX_IPSR_GPSR(IP11_31_28,	RX0),
-	PINMUX_IPSR_MSEL(IP11_31_28,	HRX1_B,			SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP11_31_28,	TS_SCK0_C,		SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP11_31_28,	STP_ISCLK_0_C,		SEL_SSP1_0_2),
-	PINMUX_IPSR_MSEL(IP11_31_28,	RIF0_D0_B,		SEL_DRIF0_1),
-
-	/* IPSR12 */
-	PINMUX_IPSR_GPSR(IP12_3_0,	TX0),
-	PINMUX_IPSR_MSEL(IP12_3_0,	HTX1_B,			SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP12_3_0,	TS_SPSYNC0_C,		SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP12_3_0,	STP_ISSYNC_0_C,		SEL_SSP1_0_2),
-	PINMUX_IPSR_MSEL(IP12_3_0,	RIF0_D1_B,		SEL_DRIF0_1),
-
-	PINMUX_IPSR_GPSR(IP12_7_4,	CTS0_N),
-	PINMUX_IPSR_MSEL(IP12_7_4,	HCTS1_N_B,		SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP12_7_4,	MSIOF1_SYNC_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP12_7_4,	TS_SPSYNC1_C,		SEL_TSIF1_2),
-	PINMUX_IPSR_MSEL(IP12_7_4,	STP_ISSYNC_1_C,		SEL_SSP1_1_2),
-	PINMUX_IPSR_MSEL(IP12_7_4,	RIF1_SYNC_B,		SEL_DRIF1_1),
-	PINMUX_IPSR_GPSR(IP12_7_4,	AUDIO_CLKOUT_C),
-	PINMUX_IPSR_GPSR(IP12_7_4,	ADICS_SAMP),
-
-	PINMUX_IPSR_GPSR(IP12_11_8,	RTS0_N),
-	PINMUX_IPSR_MSEL(IP12_11_8,	HRTS1_N_B,		SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP12_11_8,	MSIOF1_SS1_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP12_11_8,	AUDIO_CLKA_B,		SEL_ADGA_1),
-	PINMUX_IPSR_MSEL(IP12_11_8,	SCL2_A,			SEL_I2C2_0),
-	PINMUX_IPSR_MSEL(IP12_11_8,	STP_IVCXO27_1_C,	SEL_SSP1_1_2),
-	PINMUX_IPSR_MSEL(IP12_11_8,	RIF0_SYNC_B,		SEL_DRIF0_1),
-	PINMUX_IPSR_GPSR(IP12_11_8,	ADICHS1),
-
-	PINMUX_IPSR_MSEL(IP12_15_12,	RX1_A,			SEL_SCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_15_12,	HRX1_A,			SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_15_12,	TS_SDAT0_C,		SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP12_15_12,	STP_ISD_0_C,		SEL_SSP1_0_2),
-	PINMUX_IPSR_MSEL(IP12_15_12,	RIF1_CLK_C,		SEL_DRIF1_2),
-
-	PINMUX_IPSR_MSEL(IP12_19_16,	TX1_A,			SEL_SCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_19_16,	HTX1_A,			SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_19_16,	TS_SDEN0_C,		SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP12_19_16,	STP_ISEN_0_C,		SEL_SSP1_0_2),
-	PINMUX_IPSR_MSEL(IP12_19_16,	RIF1_D0_C,		SEL_DRIF1_2),
-
-	PINMUX_IPSR_GPSR(IP12_23_20,	CTS1_N),
-	PINMUX_IPSR_MSEL(IP12_23_20,	HCTS1_N_A,		SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_23_20,	MSIOF1_RXD_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP12_23_20,	TS_SDEN1_C,		SEL_TSIF1_2),
-	PINMUX_IPSR_MSEL(IP12_23_20,	STP_ISEN_1_C,		SEL_SSP1_1_2),
-	PINMUX_IPSR_MSEL(IP12_23_20,	RIF1_D0_B,		SEL_DRIF1_1),
-	PINMUX_IPSR_GPSR(IP12_23_20,	ADIDATA),
-
-	PINMUX_IPSR_GPSR(IP12_27_24,	RTS1_N),
-	PINMUX_IPSR_MSEL(IP12_27_24,	HRTS1_N_A,		SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_27_24,	MSIOF1_TXD_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP12_27_24,	TS_SDAT1_C,		SEL_TSIF1_2),
-	PINMUX_IPSR_MSEL(IP12_27_24,	STP_ISD_1_C,		SEL_SSP1_1_2),
-	PINMUX_IPSR_MSEL(IP12_27_24,	RIF1_D1_B,		SEL_DRIF1_1),
-	PINMUX_IPSR_GPSR(IP12_27_24,	ADICHS0),
-
-	PINMUX_IPSR_GPSR(IP12_31_28,	SCK2),
-	PINMUX_IPSR_MSEL(IP12_31_28,	SCIF_CLK_B,		SEL_SCIF_1),
-	PINMUX_IPSR_MSEL(IP12_31_28,	MSIOF1_SCK_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP12_31_28,	TS_SCK1_C,		SEL_TSIF1_2),
-	PINMUX_IPSR_MSEL(IP12_31_28,	STP_ISCLK_1_C,		SEL_SSP1_1_2),
-	PINMUX_IPSR_MSEL(IP12_31_28,	RIF1_CLK_B,		SEL_DRIF1_1),
-	PINMUX_IPSR_GPSR(IP12_31_28,	ADICLK),
-
-	/* IPSR13 */
-	PINMUX_IPSR_MSEL(IP13_3_0,	TX2_A,			SEL_SCIF2_0),
-	PINMUX_IPSR_MSEL(IP13_3_0,	SD2_CD_B,		SEL_SDHI2_1),
-	PINMUX_IPSR_MSEL(IP13_3_0,	SCL1_A,			SEL_I2C1_0),
-	PINMUX_IPSR_MSEL(IP13_3_0,	FMCLK_A,		SEL_FM_0),
-	PINMUX_IPSR_MSEL(IP13_3_0,	RIF1_D1_C,		SEL_DRIF1_2),
-	PINMUX_IPSR_GPSR(IP13_3_0,	FSO_CFE_0_N),
-
-	PINMUX_IPSR_MSEL(IP13_7_4,	RX2_A,			SEL_SCIF2_0),
-	PINMUX_IPSR_MSEL(IP13_7_4,	SD2_WP_B,		SEL_SDHI2_1),
-	PINMUX_IPSR_MSEL(IP13_7_4,	SDA1_A,			SEL_I2C1_0),
-	PINMUX_IPSR_MSEL(IP13_7_4,	FMIN_A,			SEL_FM_0),
-	PINMUX_IPSR_MSEL(IP13_7_4,	RIF1_SYNC_C,		SEL_DRIF1_2),
-	PINMUX_IPSR_GPSR(IP13_7_4,	FSO_CFE_1_N),
-
-	PINMUX_IPSR_GPSR(IP13_11_8,	HSCK0),
-	PINMUX_IPSR_MSEL(IP13_11_8,	MSIOF1_SCK_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP13_11_8,	AUDIO_CLKB_A,		SEL_ADGB_0),
-	PINMUX_IPSR_MSEL(IP13_11_8,	SSI_SDATA1_B,		SEL_SSI1_1),
-	PINMUX_IPSR_MSEL(IP13_11_8,	TS_SCK0_D,		SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP13_11_8,	STP_ISCLK_0_D,		SEL_SSP1_0_3),
-	PINMUX_IPSR_MSEL(IP13_11_8,	RIF0_CLK_C,		SEL_DRIF0_2),
-	PINMUX_IPSR_MSEL(IP13_11_8,	RX5_B,			SEL_SCIF5_1),
-
-	PINMUX_IPSR_GPSR(IP13_15_12,	HRX0),
-	PINMUX_IPSR_MSEL(IP13_15_12,	MSIOF1_RXD_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP13_15_12,	SSI_SDATA2_B,		SEL_SSI2_1),
-	PINMUX_IPSR_MSEL(IP13_15_12,	TS_SDEN0_D,		SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP13_15_12,	STP_ISEN_0_D,		SEL_SSP1_0_3),
-	PINMUX_IPSR_MSEL(IP13_15_12,	RIF0_D0_C,		SEL_DRIF0_2),
-
-	PINMUX_IPSR_GPSR(IP13_19_16,	HTX0),
-	PINMUX_IPSR_MSEL(IP13_19_16,	MSIOF1_TXD_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP13_19_16,	SSI_SDATA9_B,		SEL_SSI9_1),
-	PINMUX_IPSR_MSEL(IP13_19_16,	TS_SDAT0_D,		SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP13_19_16,	STP_ISD_0_D,		SEL_SSP1_0_3),
-	PINMUX_IPSR_MSEL(IP13_19_16,	RIF0_D1_C,		SEL_DRIF0_2),
-
-	PINMUX_IPSR_GPSR(IP13_23_20,	HCTS0_N),
-	PINMUX_IPSR_MSEL(IP13_23_20,	RX2_B,			SEL_SCIF2_1),
-	PINMUX_IPSR_MSEL(IP13_23_20,	MSIOF1_SYNC_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP13_23_20,	SSI_SCK9_A,		SEL_SSI9_0),
-	PINMUX_IPSR_MSEL(IP13_23_20,	TS_SPSYNC0_D,		SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP13_23_20,	STP_ISSYNC_0_D,		SEL_SSP1_0_3),
-	PINMUX_IPSR_MSEL(IP13_23_20,	RIF0_SYNC_C,		SEL_DRIF0_2),
-	PINMUX_IPSR_GPSR(IP13_23_20,	AUDIO_CLKOUT1_A),
-
-	PINMUX_IPSR_GPSR(IP13_27_24,	HRTS0_N),
-	PINMUX_IPSR_MSEL(IP13_27_24,	TX2_B,			SEL_SCIF2_1),
-	PINMUX_IPSR_MSEL(IP13_27_24,	MSIOF1_SS1_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP13_27_24,	SSI_WS9_A,		SEL_SSI9_0),
-	PINMUX_IPSR_MSEL(IP13_27_24,	STP_IVCXO27_0_D,	SEL_SSP1_0_3),
-	PINMUX_IPSR_MSEL(IP13_27_24,	BPFCLK_A,		SEL_FM_0),
-	PINMUX_IPSR_GPSR(IP13_27_24,	AUDIO_CLKOUT2_A),
-
-	PINMUX_IPSR_GPSR(IP13_31_28,	MSIOF0_SYNC),
-	PINMUX_IPSR_GPSR(IP13_31_28,	AUDIO_CLKOUT_A),
-	PINMUX_IPSR_MSEL(IP13_31_28,	TX5_B,			SEL_SCIF5_1),
-	PINMUX_IPSR_MSEL(IP13_31_28,	BPFCLK_D,		SEL_FM_3),
-
-	/* IPSR14 */
-	PINMUX_IPSR_GPSR(IP14_3_0,	MSIOF0_SS1),
-	PINMUX_IPSR_MSEL(IP14_3_0,	RX5_A,			SEL_SCIF5_0),
-	PINMUX_IPSR_MSEL(IP14_3_0,	NFWP_N_A,		SEL_NDF_0),
-	PINMUX_IPSR_MSEL(IP14_3_0,	AUDIO_CLKA_C,		SEL_ADGA_2),
-	PINMUX_IPSR_MSEL(IP14_3_0,	SSI_SCK2_A,		SEL_SSI2_0),
-	PINMUX_IPSR_MSEL(IP14_3_0,	STP_IVCXO27_0_C,	SEL_SSP1_0_2),
-	PINMUX_IPSR_GPSR(IP14_3_0,	AUDIO_CLKOUT3_A),
-	PINMUX_IPSR_MSEL(IP14_3_0,	TCLK1_B,		SEL_TIMER_TMU_1),
-
-	PINMUX_IPSR_GPSR(IP14_7_4,	MSIOF0_SS2),
-	PINMUX_IPSR_MSEL(IP14_7_4,	TX5_A,			SEL_SCIF5_0),
-	PINMUX_IPSR_MSEL(IP14_7_4,	MSIOF1_SS2_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP14_7_4,	AUDIO_CLKC_A,		SEL_ADGC_0),
-	PINMUX_IPSR_MSEL(IP14_7_4,	SSI_WS2_A,		SEL_SSI2_0),
-	PINMUX_IPSR_MSEL(IP14_7_4,	STP_OPWM_0_D,		SEL_SSP1_0_3),
-	PINMUX_IPSR_GPSR(IP14_7_4,	AUDIO_CLKOUT_D),
-	PINMUX_IPSR_MSEL(IP14_7_4,	SPEEDIN_B,		SEL_SPEED_PULSE_1),
-
-	PINMUX_IPSR_GPSR(IP14_11_8,	MLB_CLK),
-	PINMUX_IPSR_MSEL(IP14_11_8,	MSIOF1_SCK_F,		SEL_MSIOF1_5),
-	PINMUX_IPSR_MSEL(IP14_11_8,	SCL1_B,			SEL_I2C1_1),
-
-	PINMUX_IPSR_GPSR(IP14_15_12,	MLB_SIG),
-	PINMUX_IPSR_MSEL(IP14_15_12,	RX1_B,			SEL_SCIF1_1),
-	PINMUX_IPSR_MSEL(IP14_15_12,	MSIOF1_SYNC_F,		SEL_MSIOF1_5),
-	PINMUX_IPSR_MSEL(IP14_15_12,	SDA1_B,			SEL_I2C1_1),
-
-	PINMUX_IPSR_GPSR(IP14_19_16,	MLB_DAT),
-	PINMUX_IPSR_MSEL(IP14_19_16,	TX1_B,			SEL_SCIF1_1),
-	PINMUX_IPSR_MSEL(IP14_19_16,	MSIOF1_RXD_F,		SEL_MSIOF1_5),
-
-	PINMUX_IPSR_GPSR(IP14_23_20,	SSI_SCK01239),
-	PINMUX_IPSR_MSEL(IP14_23_20,	MSIOF1_TXD_F,		SEL_MSIOF1_5),
-
-	PINMUX_IPSR_GPSR(IP14_27_24,	SSI_WS01239),
-	PINMUX_IPSR_MSEL(IP14_27_24,	MSIOF1_SS1_F,		SEL_MSIOF1_5),
-
-	PINMUX_IPSR_GPSR(IP14_31_28,	SSI_SDATA0),
-	PINMUX_IPSR_MSEL(IP14_31_28,	MSIOF1_SS2_F,		SEL_MSIOF1_5),
-
-	/* IPSR15 */
-	PINMUX_IPSR_MSEL(IP15_3_0,	SSI_SDATA1_A,		SEL_SSI1_0),
-
-	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SDATA2_A,		SEL_SSI2_0),
-	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SCK1_B,		SEL_SSI1_1),
-
-	PINMUX_IPSR_GPSR(IP15_11_8,	SSI_SCK349),
-	PINMUX_IPSR_MSEL(IP15_11_8,	MSIOF1_SS1_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP15_11_8,	STP_OPWM_0_A,		SEL_SSP1_0_0),
-
-	PINMUX_IPSR_GPSR(IP15_15_12,	SSI_WS349),
-	PINMUX_IPSR_MSEL(IP15_15_12,	HCTS2_N_A,		SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP15_15_12,	MSIOF1_SS2_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP15_15_12,	STP_IVCXO27_0_A,	SEL_SSP1_0_0),
-
-	PINMUX_IPSR_GPSR(IP15_19_16,	SSI_SDATA3),
-	PINMUX_IPSR_MSEL(IP15_19_16,	HRTS2_N_A,		SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP15_19_16,	MSIOF1_TXD_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP15_19_16,	TS_SCK0_A,		SEL_TSIF0_0),
-	PINMUX_IPSR_MSEL(IP15_19_16,	STP_ISCLK_0_A,		SEL_SSP1_0_0),
-	PINMUX_IPSR_MSEL(IP15_19_16,	RIF0_D1_A,		SEL_DRIF0_0),
-	PINMUX_IPSR_MSEL(IP15_19_16,	RIF2_D0_A,		SEL_DRIF2_0),
-
-	PINMUX_IPSR_GPSR(IP15_23_20,	SSI_SCK4),
-	PINMUX_IPSR_MSEL(IP15_23_20,	HRX2_A,			SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP15_23_20,	MSIOF1_SCK_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP15_23_20,	TS_SDAT0_A,		SEL_TSIF0_0),
-	PINMUX_IPSR_MSEL(IP15_23_20,	STP_ISD_0_A,		SEL_SSP1_0_0),
-	PINMUX_IPSR_MSEL(IP15_23_20,	RIF0_CLK_A,		SEL_DRIF0_0),
-	PINMUX_IPSR_MSEL(IP15_23_20,	RIF2_CLK_A,		SEL_DRIF2_0),
-
-	PINMUX_IPSR_GPSR(IP15_27_24,	SSI_WS4),
-	PINMUX_IPSR_MSEL(IP15_27_24,	HTX2_A,			SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP15_27_24,	MSIOF1_SYNC_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP15_27_24,	TS_SDEN0_A,		SEL_TSIF0_0),
-	PINMUX_IPSR_MSEL(IP15_27_24,	STP_ISEN_0_A,		SEL_SSP1_0_0),
-	PINMUX_IPSR_MSEL(IP15_27_24,	RIF0_SYNC_A,		SEL_DRIF0_0),
-	PINMUX_IPSR_MSEL(IP15_27_24,	RIF2_SYNC_A,		SEL_DRIF2_0),
-
-	PINMUX_IPSR_GPSR(IP15_31_28,	SSI_SDATA4),
-	PINMUX_IPSR_MSEL(IP15_31_28,	HSCK2_A,		SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP15_31_28,	MSIOF1_RXD_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP15_31_28,	TS_SPSYNC0_A,		SEL_TSIF0_0),
-	PINMUX_IPSR_MSEL(IP15_31_28,	STP_ISSYNC_0_A,		SEL_SSP1_0_0),
-	PINMUX_IPSR_MSEL(IP15_31_28,	RIF0_D0_A,		SEL_DRIF0_0),
-	PINMUX_IPSR_MSEL(IP15_31_28,	RIF2_D1_A,		SEL_DRIF2_0),
-
-	/* IPSR16 */
-	PINMUX_IPSR_GPSR(IP16_3_0,	SSI_SCK6),
-	PINMUX_IPSR_MSEL(IP16_3_0,	SIM0_RST_D,		SEL_SIMCARD_3),
-
-	PINMUX_IPSR_GPSR(IP16_7_4,	SSI_WS6),
-	PINMUX_IPSR_MSEL(IP16_7_4,	SIM0_D_D,		SEL_SIMCARD_3),
-
-	PINMUX_IPSR_GPSR(IP16_11_8,	SSI_SDATA6),
-	PINMUX_IPSR_MSEL(IP16_11_8,	SIM0_CLK_D,		SEL_SIMCARD_3),
-
-	PINMUX_IPSR_GPSR(IP16_15_12,	SSI_SCK78),
-	PINMUX_IPSR_MSEL(IP16_15_12,	HRX2_B,			SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP16_15_12,	MSIOF1_SCK_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP16_15_12,	TS_SCK1_A,		SEL_TSIF1_0),
-	PINMUX_IPSR_MSEL(IP16_15_12,	STP_ISCLK_1_A,		SEL_SSP1_1_0),
-	PINMUX_IPSR_MSEL(IP16_15_12,	RIF1_CLK_A,		SEL_DRIF1_0),
-	PINMUX_IPSR_MSEL(IP16_15_12,	RIF3_CLK_A,		SEL_DRIF3_0),
-
-	PINMUX_IPSR_GPSR(IP16_19_16,	SSI_WS78),
-	PINMUX_IPSR_MSEL(IP16_19_16,	HTX2_B,			SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP16_19_16,	MSIOF1_SYNC_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP16_19_16,	TS_SDAT1_A,		SEL_TSIF1_0),
-	PINMUX_IPSR_MSEL(IP16_19_16,	STP_ISD_1_A,		SEL_SSP1_1_0),
-	PINMUX_IPSR_MSEL(IP16_19_16,	RIF1_SYNC_A,		SEL_DRIF1_0),
-	PINMUX_IPSR_MSEL(IP16_19_16,	RIF3_SYNC_A,		SEL_DRIF3_0),
-
-	PINMUX_IPSR_GPSR(IP16_23_20,	SSI_SDATA7),
-	PINMUX_IPSR_MSEL(IP16_23_20,	HCTS2_N_B,		SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP16_23_20,	MSIOF1_RXD_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP16_23_20,	TS_SDEN1_A,		SEL_TSIF1_0),
-	PINMUX_IPSR_MSEL(IP16_23_20,	STP_ISEN_1_A,		SEL_SSP1_1_0),
-	PINMUX_IPSR_MSEL(IP16_23_20,	RIF1_D0_A,		SEL_DRIF1_0),
-	PINMUX_IPSR_MSEL(IP16_23_20,	RIF3_D0_A,		SEL_DRIF3_0),
-	PINMUX_IPSR_MSEL(IP16_23_20,	TCLK2_A,		SEL_TIMER_TMU2_0),
-
-	PINMUX_IPSR_GPSR(IP16_27_24,	SSI_SDATA8),
-	PINMUX_IPSR_MSEL(IP16_27_24,	HRTS2_N_B,		SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP16_27_24,	MSIOF1_TXD_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP16_27_24,	TS_SPSYNC1_A,		SEL_TSIF1_0),
-	PINMUX_IPSR_MSEL(IP16_27_24,	STP_ISSYNC_1_A,		SEL_SSP1_1_0),
-	PINMUX_IPSR_MSEL(IP16_27_24,	RIF1_D1_A,		SEL_DRIF1_0),
-	PINMUX_IPSR_MSEL(IP16_27_24,	RIF3_D1_A,		SEL_DRIF3_0),
-
-	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_SDATA9_A,		SEL_SSI9_0),
-	PINMUX_IPSR_MSEL(IP16_31_28,	HSCK2_B,		SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP16_31_28,	MSIOF1_SS1_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP16_31_28,	HSCK1_A,		SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_WS1_B,		SEL_SSI1_1),
-	PINMUX_IPSR_GPSR(IP16_31_28,	SCK1),
-	PINMUX_IPSR_MSEL(IP16_31_28,	STP_IVCXO27_1_A,	SEL_SSP1_1_0),
-	PINMUX_IPSR_MSEL(IP16_31_28,	SCK5_A,			SEL_SCIF5_0),
-
-	/* IPSR17 */
-	PINMUX_IPSR_MSEL(IP17_3_0,	AUDIO_CLKA_A,		SEL_ADGA_0),
-
-	PINMUX_IPSR_MSEL(IP17_7_4,	AUDIO_CLKB_B,		SEL_ADGB_1),
-	PINMUX_IPSR_MSEL(IP17_7_4,	SCIF_CLK_A,		SEL_SCIF_0),
-	PINMUX_IPSR_MSEL(IP17_7_4,	STP_IVCXO27_1_D,	SEL_SSP1_1_3),
-	PINMUX_IPSR_MSEL(IP17_7_4,	REMOCON_A,		SEL_REMOCON_0),
-	PINMUX_IPSR_MSEL(IP17_7_4,	TCLK1_A,		SEL_TIMER_TMU_0),
-
-	PINMUX_IPSR_GPSR(IP17_11_8,	USB0_PWEN),
-	PINMUX_IPSR_MSEL(IP17_11_8,	SIM0_RST_C,		SEL_SIMCARD_2),
-	PINMUX_IPSR_MSEL(IP17_11_8,	TS_SCK1_D,		SEL_TSIF1_3),
-	PINMUX_IPSR_MSEL(IP17_11_8,	STP_ISCLK_1_D,		SEL_SSP1_1_3),
-	PINMUX_IPSR_MSEL(IP17_11_8,	BPFCLK_B,		SEL_FM_1),
-	PINMUX_IPSR_MSEL(IP17_11_8,	RIF3_CLK_B,		SEL_DRIF3_1),
-	PINMUX_IPSR_MSEL(IP17_11_8,	HSCK2_C,		SEL_HSCIF2_2),
-
-	PINMUX_IPSR_GPSR(IP17_15_12,	USB0_OVC),
-	PINMUX_IPSR_MSEL(IP17_15_12,	SIM0_D_C,		SEL_SIMCARD_2),
-	PINMUX_IPSR_MSEL(IP17_15_12,	TS_SDAT1_D,		SEL_TSIF1_3),
-	PINMUX_IPSR_MSEL(IP17_15_12,	STP_ISD_1_D,		SEL_SSP1_1_3),
-	PINMUX_IPSR_MSEL(IP17_15_12,	RIF3_SYNC_B,		SEL_DRIF3_1),
-	PINMUX_IPSR_MSEL(IP17_15_12,	HRX2_C,			SEL_HSCIF2_2),
-
-	PINMUX_IPSR_GPSR(IP17_19_16,	USB1_PWEN),
-	PINMUX_IPSR_MSEL(IP17_19_16,	SIM0_CLK_C,		SEL_SIMCARD_2),
-	PINMUX_IPSR_MSEL(IP17_19_16,	SSI_SCK1_A,		SEL_SSI1_0),
-	PINMUX_IPSR_MSEL(IP17_19_16,	TS_SCK0_E,		SEL_TSIF0_4),
-	PINMUX_IPSR_MSEL(IP17_19_16,	STP_ISCLK_0_E,		SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP17_19_16,	FMCLK_B,		SEL_FM_1),
-	PINMUX_IPSR_MSEL(IP17_19_16,	RIF2_CLK_B,		SEL_DRIF2_1),
-	PINMUX_IPSR_MSEL(IP17_19_16,	SPEEDIN_A,		SEL_SPEED_PULSE_0),
-	PINMUX_IPSR_MSEL(IP17_19_16,	HTX2_C,			SEL_HSCIF2_2),
-
-	PINMUX_IPSR_GPSR(IP17_23_20,	USB1_OVC),
-	PINMUX_IPSR_MSEL(IP17_23_20,	MSIOF1_SS2_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP17_23_20,	SSI_WS1_A,		SEL_SSI1_0),
-	PINMUX_IPSR_MSEL(IP17_23_20,	TS_SDAT0_E,		SEL_TSIF0_4),
-	PINMUX_IPSR_MSEL(IP17_23_20,	STP_ISD_0_E,		SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP17_23_20,	FMIN_B,			SEL_FM_1),
-	PINMUX_IPSR_MSEL(IP17_23_20,	RIF2_SYNC_B,		SEL_DRIF2_1),
-	PINMUX_IPSR_MSEL(IP17_23_20,	REMOCON_B,		SEL_REMOCON_1),
-	PINMUX_IPSR_MSEL(IP17_23_20,	HCTS2_N_C,		SEL_HSCIF2_2),
-
-	PINMUX_IPSR_GPSR(IP17_27_24,	USB30_PWEN),
-	PINMUX_IPSR_GPSR(IP17_27_24,	AUDIO_CLKOUT_B),
-	PINMUX_IPSR_MSEL(IP17_27_24,	SSI_SCK2_B,		SEL_SSI2_1),
-	PINMUX_IPSR_MSEL(IP17_27_24,	TS_SDEN1_D,		SEL_TSIF1_3),
-	PINMUX_IPSR_MSEL(IP17_27_24,	STP_ISEN_1_D,		SEL_SSP1_1_3),
-	PINMUX_IPSR_MSEL(IP17_27_24,	STP_OPWM_0_E,		SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP17_27_24,	RIF3_D0_B,		SEL_DRIF3_1),
-	PINMUX_IPSR_MSEL(IP17_27_24,	TCLK2_B,		SEL_TIMER_TMU2_1),
-	PINMUX_IPSR_GPSR(IP17_27_24,	TPU0TO0),
-	PINMUX_IPSR_MSEL(IP17_27_24,	BPFCLK_C,		SEL_FM_2),
-	PINMUX_IPSR_MSEL(IP17_27_24,	HRTS2_N_C,		SEL_HSCIF2_2),
-
-	PINMUX_IPSR_GPSR(IP17_31_28,	USB30_OVC),
-	PINMUX_IPSR_GPSR(IP17_31_28,	AUDIO_CLKOUT1_B),
-	PINMUX_IPSR_MSEL(IP17_31_28,	SSI_WS2_B,		SEL_SSI2_1),
-	PINMUX_IPSR_MSEL(IP17_31_28,	TS_SPSYNC1_D,		SEL_TSIF1_3),
-	PINMUX_IPSR_MSEL(IP17_31_28,	STP_ISSYNC_1_D,		SEL_SSP1_1_3),
-	PINMUX_IPSR_MSEL(IP17_31_28,	STP_IVCXO27_0_E,	SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP17_31_28,	RIF3_D1_B,		SEL_DRIF3_1),
-	PINMUX_IPSR_GPSR(IP17_31_28,	FSO_TOE_N),
-	PINMUX_IPSR_GPSR(IP17_31_28,	TPU0TO1),
-
-	/* IPSR18 */
-	PINMUX_IPSR_GPSR(IP18_3_0,	GP6_30),
-	PINMUX_IPSR_GPSR(IP18_3_0,	AUDIO_CLKOUT2_B),
-	PINMUX_IPSR_MSEL(IP18_3_0,	SSI_SCK9_B,		SEL_SSI9_1),
-	PINMUX_IPSR_MSEL(IP18_3_0,	TS_SDEN0_E,		SEL_TSIF0_4),
-	PINMUX_IPSR_MSEL(IP18_3_0,	STP_ISEN_0_E,		SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP18_3_0,	RIF2_D0_B,		SEL_DRIF2_1),
-	PINMUX_IPSR_GPSR(IP18_3_0,	TPU0TO2),
-	PINMUX_IPSR_MSEL(IP18_3_0,	FMCLK_C,		SEL_FM_2),
-	PINMUX_IPSR_MSEL(IP18_3_0,	FMCLK_D,		SEL_FM_3),
-
-	PINMUX_IPSR_GPSR(IP18_7_4,	GP6_31),
-	PINMUX_IPSR_GPSR(IP18_7_4,	AUDIO_CLKOUT3_B),
-	PINMUX_IPSR_MSEL(IP18_7_4,	SSI_WS9_B,		SEL_SSI9_1),
-	PINMUX_IPSR_MSEL(IP18_7_4,	TS_SPSYNC0_E,		SEL_TSIF0_4),
-	PINMUX_IPSR_MSEL(IP18_7_4,	STP_ISSYNC_0_E,		SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP18_7_4,	RIF2_D1_B,		SEL_DRIF2_1),
-	PINMUX_IPSR_GPSR(IP18_7_4,	TPU0TO3),
-	PINMUX_IPSR_MSEL(IP18_7_4,	FMIN_C,			SEL_FM_2),
-	PINMUX_IPSR_MSEL(IP18_7_4,	FMIN_D,			SEL_FM_3),
-
-/*
- * Static pins can not be muxed between different functions but
- * still need mark entries in the pinmux list. Add each static
- * pin to the list without an associated function. The sh-pfc
- * core will do the right thing and skip trying to mux the pin
- * while still applying configuration to it.
- */
-#define FM(x)   PINMUX_DATA(x##_MARK, 0),
-	PINMUX_STATIC
-#undef FM
-};
-
-/*
- * Pins not associated with a GPIO port.
- */
-enum {
-	GP_ASSIGN_LAST(),
-	NOGP_ALL(),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	PINMUX_GPIO_GP_ALL(),
-	PINMUX_NOGP_ALL(),
-};
-
-/* - AUDIO CLOCK ------------------------------------------------------------ */
-static const unsigned int audio_clk_a_a_pins[] = {
-	/* CLK A */
-	RCAR_GP_PIN(6, 22),
-};
-static const unsigned int audio_clk_a_a_mux[] = {
-	AUDIO_CLKA_A_MARK,
-};
-static const unsigned int audio_clk_a_b_pins[] = {
-	/* CLK A */
-	RCAR_GP_PIN(5, 4),
-};
-static const unsigned int audio_clk_a_b_mux[] = {
-	AUDIO_CLKA_B_MARK,
-};
-static const unsigned int audio_clk_a_c_pins[] = {
-	/* CLK A */
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int audio_clk_a_c_mux[] = {
-	AUDIO_CLKA_C_MARK,
-};
-static const unsigned int audio_clk_b_a_pins[] = {
-	/* CLK B */
-	RCAR_GP_PIN(5, 12),
-};
-static const unsigned int audio_clk_b_a_mux[] = {
-	AUDIO_CLKB_A_MARK,
-};
-static const unsigned int audio_clk_b_b_pins[] = {
-	/* CLK B */
-	RCAR_GP_PIN(6, 23),
-};
-static const unsigned int audio_clk_b_b_mux[] = {
-	AUDIO_CLKB_B_MARK,
-};
-static const unsigned int audio_clk_c_a_pins[] = {
-	/* CLK C */
-	RCAR_GP_PIN(5, 21),
-};
-static const unsigned int audio_clk_c_a_mux[] = {
-	AUDIO_CLKC_A_MARK,
-};
-static const unsigned int audio_clk_c_b_pins[] = {
-	/* CLK C */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int audio_clk_c_b_mux[] = {
-	AUDIO_CLKC_B_MARK,
-};
-static const unsigned int audio_clkout_a_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(5, 18),
-};
-static const unsigned int audio_clkout_a_mux[] = {
-	AUDIO_CLKOUT_A_MARK,
-};
-static const unsigned int audio_clkout_b_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(6, 28),
-};
-static const unsigned int audio_clkout_b_mux[] = {
-	AUDIO_CLKOUT_B_MARK,
-};
-static const unsigned int audio_clkout_c_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(5, 3),
-};
-static const unsigned int audio_clkout_c_mux[] = {
-	AUDIO_CLKOUT_C_MARK,
-};
-static const unsigned int audio_clkout_d_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(5, 21),
-};
-static const unsigned int audio_clkout_d_mux[] = {
-	AUDIO_CLKOUT_D_MARK,
-};
-static const unsigned int audio_clkout1_a_pins[] = {
-	/* CLKOUT1 */
-	RCAR_GP_PIN(5, 15),
-};
-static const unsigned int audio_clkout1_a_mux[] = {
-	AUDIO_CLKOUT1_A_MARK,
-};
-static const unsigned int audio_clkout1_b_pins[] = {
-	/* CLKOUT1 */
-	RCAR_GP_PIN(6, 29),
-};
-static const unsigned int audio_clkout1_b_mux[] = {
-	AUDIO_CLKOUT1_B_MARK,
-};
-static const unsigned int audio_clkout2_a_pins[] = {
-	/* CLKOUT2 */
-	RCAR_GP_PIN(5, 16),
-};
-static const unsigned int audio_clkout2_a_mux[] = {
-	AUDIO_CLKOUT2_A_MARK,
-};
-static const unsigned int audio_clkout2_b_pins[] = {
-	/* CLKOUT2 */
-	RCAR_GP_PIN(6, 30),
-};
-static const unsigned int audio_clkout2_b_mux[] = {
-	AUDIO_CLKOUT2_B_MARK,
-};
-
-static const unsigned int audio_clkout3_a_pins[] = {
-	/* CLKOUT3 */
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int audio_clkout3_a_mux[] = {
-	AUDIO_CLKOUT3_A_MARK,
-};
-static const unsigned int audio_clkout3_b_pins[] = {
-	/* CLKOUT3 */
-	RCAR_GP_PIN(6, 31),
-};
-static const unsigned int audio_clkout3_b_mux[] = {
-	AUDIO_CLKOUT3_B_MARK,
-};
-
-/* - EtherAVB --------------------------------------------------------------- */
-static const unsigned int avb_link_pins[] = {
-	/* AVB_LINK */
-	RCAR_GP_PIN(2, 12),
-};
-static const unsigned int avb_link_mux[] = {
-	AVB_LINK_MARK,
-};
-static const unsigned int avb_magic_pins[] = {
-	/* AVB_MAGIC_ */
-	RCAR_GP_PIN(2, 10),
-};
-static const unsigned int avb_magic_mux[] = {
-	AVB_MAGIC_MARK,
-};
-static const unsigned int avb_phy_int_pins[] = {
-	/* AVB_PHY_INT */
-	RCAR_GP_PIN(2, 11),
-};
-static const unsigned int avb_phy_int_mux[] = {
-	AVB_PHY_INT_MARK,
-};
-static const unsigned int avb_mdio_pins[] = {
-	/* AVB_MDC, AVB_MDIO */
-	RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
-};
-static const unsigned int avb_mdio_mux[] = {
-	AVB_MDC_MARK, AVB_MDIO_MARK,
-};
-static const unsigned int avb_mii_pins[] = {
-	/*
-	 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
-	 * AVB_TD1, AVB_TD2, AVB_TD3,
-	 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
-	 * AVB_RD1, AVB_RD2, AVB_RD3,
-	 * AVB_TXCREFCLK
-	 */
-	PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
-	PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
-	PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
-	PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
-	PIN_AVB_TXCREFCLK,
-
-};
-static const unsigned int avb_mii_mux[] = {
-	AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
-	AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
-	AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
-	AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
-	AVB_TXCREFCLK_MARK,
-};
-static const unsigned int avb_avtp_pps_pins[] = {
-	/* AVB_AVTP_PPS */
-	RCAR_GP_PIN(2, 6),
-};
-static const unsigned int avb_avtp_pps_mux[] = {
-	AVB_AVTP_PPS_MARK,
-};
-static const unsigned int avb_avtp_match_a_pins[] = {
-	/* AVB_AVTP_MATCH_A */
-	RCAR_GP_PIN(2, 13),
-};
-static const unsigned int avb_avtp_match_a_mux[] = {
-	AVB_AVTP_MATCH_A_MARK,
-};
-static const unsigned int avb_avtp_capture_a_pins[] = {
-	/* AVB_AVTP_CAPTURE_A */
-	RCAR_GP_PIN(2, 14),
-};
-static const unsigned int avb_avtp_capture_a_mux[] = {
-	AVB_AVTP_CAPTURE_A_MARK,
-};
-static const unsigned int avb_avtp_match_b_pins[] = {
-	/*  AVB_AVTP_MATCH_B */
-	RCAR_GP_PIN(1, 8),
-};
-static const unsigned int avb_avtp_match_b_mux[] = {
-	AVB_AVTP_MATCH_B_MARK,
-};
-static const unsigned int avb_avtp_capture_b_pins[] = {
-	/* AVB_AVTP_CAPTURE_B */
-	RCAR_GP_PIN(1, 11),
-};
-static const unsigned int avb_avtp_capture_b_mux[] = {
-	AVB_AVTP_CAPTURE_B_MARK,
-};
-
-/* - CAN ------------------------------------------------------------------ */
-static const unsigned int can0_data_a_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(1, 23),	RCAR_GP_PIN(1, 24),
-};
-static const unsigned int can0_data_a_mux[] = {
-	CAN0_TX_A_MARK,		CAN0_RX_A_MARK,
-};
-static const unsigned int can0_data_b_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(2, 0),	RCAR_GP_PIN(2, 1),
-};
-static const unsigned int can0_data_b_mux[] = {
-	CAN0_TX_B_MARK,		CAN0_RX_B_MARK,
-};
-static const unsigned int can1_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(1, 22),	RCAR_GP_PIN(1, 26),
-};
-static const unsigned int can1_data_mux[] = {
-	CAN1_TX_MARK,		CAN1_RX_MARK,
-};
-
-/* - CAN Clock -------------------------------------------------------------- */
-static const unsigned int can_clk_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(1, 25),
-};
-static const unsigned int can_clk_mux[] = {
-	CAN_CLK_MARK,
-};
-
-/* - CAN FD --------------------------------------------------------------- */
-static const unsigned int canfd0_data_a_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
-};
-static const unsigned int canfd0_data_a_mux[] = {
-	CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
-};
-static const unsigned int canfd0_data_b_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
-};
-static const unsigned int canfd0_data_b_mux[] = {
-	CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
-};
-static const unsigned int canfd1_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
-};
-static const unsigned int canfd1_data_mux[] = {
-	CANFD1_TX_MARK,         CANFD1_RX_MARK,
-};
-
-/* - DRIF0 --------------------------------------------------------------- */
-static const unsigned int drif0_ctrl_a_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
-};
-static const unsigned int drif0_ctrl_a_mux[] = {
-	RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
-};
-static const unsigned int drif0_data0_a_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 10),
-};
-static const unsigned int drif0_data0_a_mux[] = {
-	RIF0_D0_A_MARK,
-};
-static const unsigned int drif0_data1_a_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 7),
-};
-static const unsigned int drif0_data1_a_mux[] = {
-	RIF0_D1_A_MARK,
-};
-static const unsigned int drif0_ctrl_b_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
-};
-static const unsigned int drif0_ctrl_b_mux[] = {
-	RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
-};
-static const unsigned int drif0_data0_b_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(5, 1),
-};
-static const unsigned int drif0_data0_b_mux[] = {
-	RIF0_D0_B_MARK,
-};
-static const unsigned int drif0_data1_b_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(5, 2),
-};
-static const unsigned int drif0_data1_b_mux[] = {
-	RIF0_D1_B_MARK,
-};
-static const unsigned int drif0_ctrl_c_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
-};
-static const unsigned int drif0_ctrl_c_mux[] = {
-	RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
-};
-static const unsigned int drif0_data0_c_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(5, 13),
-};
-static const unsigned int drif0_data0_c_mux[] = {
-	RIF0_D0_C_MARK,
-};
-static const unsigned int drif0_data1_c_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(5, 14),
-};
-static const unsigned int drif0_data1_c_mux[] = {
-	RIF0_D1_C_MARK,
-};
-/* - DRIF1 --------------------------------------------------------------- */
-static const unsigned int drif1_ctrl_a_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
-};
-static const unsigned int drif1_ctrl_a_mux[] = {
-	RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
-};
-static const unsigned int drif1_data0_a_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 19),
-};
-static const unsigned int drif1_data0_a_mux[] = {
-	RIF1_D0_A_MARK,
-};
-static const unsigned int drif1_data1_a_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 20),
-};
-static const unsigned int drif1_data1_a_mux[] = {
-	RIF1_D1_A_MARK,
-};
-static const unsigned int drif1_ctrl_b_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
-};
-static const unsigned int drif1_ctrl_b_mux[] = {
-	RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
-};
-static const unsigned int drif1_data0_b_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(5, 7),
-};
-static const unsigned int drif1_data0_b_mux[] = {
-	RIF1_D0_B_MARK,
-};
-static const unsigned int drif1_data1_b_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(5, 8),
-};
-static const unsigned int drif1_data1_b_mux[] = {
-	RIF1_D1_B_MARK,
-};
-static const unsigned int drif1_ctrl_c_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
-};
-static const unsigned int drif1_ctrl_c_mux[] = {
-	RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
-};
-static const unsigned int drif1_data0_c_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(5, 6),
-};
-static const unsigned int drif1_data0_c_mux[] = {
-	RIF1_D0_C_MARK,
-};
-static const unsigned int drif1_data1_c_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(5, 10),
-};
-static const unsigned int drif1_data1_c_mux[] = {
-	RIF1_D1_C_MARK,
-};
-/* - DRIF2 --------------------------------------------------------------- */
-static const unsigned int drif2_ctrl_a_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
-};
-static const unsigned int drif2_ctrl_a_mux[] = {
-	RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
-};
-static const unsigned int drif2_data0_a_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 7),
-};
-static const unsigned int drif2_data0_a_mux[] = {
-	RIF2_D0_A_MARK,
-};
-static const unsigned int drif2_data1_a_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 10),
-};
-static const unsigned int drif2_data1_a_mux[] = {
-	RIF2_D1_A_MARK,
-};
-static const unsigned int drif2_ctrl_b_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
-};
-static const unsigned int drif2_ctrl_b_mux[] = {
-	RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
-};
-static const unsigned int drif2_data0_b_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 30),
-};
-static const unsigned int drif2_data0_b_mux[] = {
-	RIF2_D0_B_MARK,
-};
-static const unsigned int drif2_data1_b_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 31),
-};
-static const unsigned int drif2_data1_b_mux[] = {
-	RIF2_D1_B_MARK,
-};
-/* - DRIF3 --------------------------------------------------------------- */
-static const unsigned int drif3_ctrl_a_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
-};
-static const unsigned int drif3_ctrl_a_mux[] = {
-	RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
-};
-static const unsigned int drif3_data0_a_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 19),
-};
-static const unsigned int drif3_data0_a_mux[] = {
-	RIF3_D0_A_MARK,
-};
-static const unsigned int drif3_data1_a_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 20),
-};
-static const unsigned int drif3_data1_a_mux[] = {
-	RIF3_D1_A_MARK,
-};
-static const unsigned int drif3_ctrl_b_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
-};
-static const unsigned int drif3_ctrl_b_mux[] = {
-	RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
-};
-static const unsigned int drif3_data0_b_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 28),
-};
-static const unsigned int drif3_data0_b_mux[] = {
-	RIF3_D0_B_MARK,
-};
-static const unsigned int drif3_data1_b_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 29),
-};
-static const unsigned int drif3_data1_b_mux[] = {
-	RIF3_D1_B_MARK,
-};
-
-/* - DU --------------------------------------------------------------------- */
-static const unsigned int du_rgb666_pins[] = {
-	/* R[7:2], G[7:2], B[7:2] */
-	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
-	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
-	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
-	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
-};
-static const unsigned int du_rgb666_mux[] = {
-	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
-	DU_DR3_MARK, DU_DR2_MARK,
-	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
-	DU_DG3_MARK, DU_DG2_MARK,
-	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
-	DU_DB3_MARK, DU_DB2_MARK,
-};
-static const unsigned int du_rgb888_pins[] = {
-	/* R[7:0], G[7:0], B[7:0] */
-	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
-	RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
-	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
-	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
-	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
-	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
-	RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
-};
-static const unsigned int du_rgb888_mux[] = {
-	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
-	DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
-	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
-	DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
-	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
-	DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
-};
-static const unsigned int du_clk_out_0_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(1, 27),
-};
-static const unsigned int du_clk_out_0_mux[] = {
-	DU_DOTCLKOUT0_MARK
-};
-static const unsigned int du_clk_out_1_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(2, 3),
-};
-static const unsigned int du_clk_out_1_mux[] = {
-	DU_DOTCLKOUT1_MARK
-};
-static const unsigned int du_sync_pins[] = {
-	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
-	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
-};
-static const unsigned int du_sync_mux[] = {
-	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
-};
-static const unsigned int du_oddf_pins[] = {
-	/* EXDISP/EXODDF/EXCDE */
-	RCAR_GP_PIN(2, 2),
-};
-static const unsigned int du_oddf_mux[] = {
-	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
-};
-static const unsigned int du_cde_pins[] = {
-	/* CDE */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int du_cde_mux[] = {
-	DU_CDE_MARK,
-};
-static const unsigned int du_disp_pins[] = {
-	/* DISP */
-	RCAR_GP_PIN(2, 1),
-};
-static const unsigned int du_disp_mux[] = {
-	DU_DISP_MARK,
-};
-
-/* - HSCIF0 ----------------------------------------------------------------- */
-static const unsigned int hscif0_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
-};
-static const unsigned int hscif0_data_mux[] = {
-	HRX0_MARK, HTX0_MARK,
-};
-static const unsigned int hscif0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 12),
-};
-static const unsigned int hscif0_clk_mux[] = {
-	HSCK0_MARK,
-};
-static const unsigned int hscif0_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
-};
-static const unsigned int hscif0_ctrl_mux[] = {
-	HRTS0_N_MARK, HCTS0_N_MARK,
-};
-/* - HSCIF1 ----------------------------------------------------------------- */
-static const unsigned int hscif1_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
-};
-static const unsigned int hscif1_data_a_mux[] = {
-	HRX1_A_MARK, HTX1_A_MARK,
-};
-static const unsigned int hscif1_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int hscif1_clk_a_mux[] = {
-	HSCK1_A_MARK,
-};
-static const unsigned int hscif1_ctrl_a_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
-};
-static const unsigned int hscif1_ctrl_a_mux[] = {
-	HRTS1_N_A_MARK, HCTS1_N_A_MARK,
-};
-
-static const unsigned int hscif1_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-};
-static const unsigned int hscif1_data_b_mux[] = {
-	HRX1_B_MARK, HTX1_B_MARK,
-};
-static const unsigned int hscif1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int hscif1_clk_b_mux[] = {
-	HSCK1_B_MARK,
-};
-static const unsigned int hscif1_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
-};
-static const unsigned int hscif1_ctrl_b_mux[] = {
-	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
-};
-/* - HSCIF2 ----------------------------------------------------------------- */
-static const unsigned int hscif2_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
-};
-static const unsigned int hscif2_data_a_mux[] = {
-	HRX2_A_MARK, HTX2_A_MARK,
-};
-static const unsigned int hscif2_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 10),
-};
-static const unsigned int hscif2_clk_a_mux[] = {
-	HSCK2_A_MARK,
-};
-static const unsigned int hscif2_ctrl_a_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
-};
-static const unsigned int hscif2_ctrl_a_mux[] = {
-	HRTS2_N_A_MARK, HCTS2_N_A_MARK,
-};
-
-static const unsigned int hscif2_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
-};
-static const unsigned int hscif2_data_b_mux[] = {
-	HRX2_B_MARK, HTX2_B_MARK,
-};
-static const unsigned int hscif2_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int hscif2_clk_b_mux[] = {
-	HSCK2_B_MARK,
-};
-static const unsigned int hscif2_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
-};
-static const unsigned int hscif2_ctrl_b_mux[] = {
-	HRTS2_N_B_MARK, HCTS2_N_B_MARK,
-};
-
-static const unsigned int hscif2_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
-};
-static const unsigned int hscif2_data_c_mux[] = {
-	HRX2_C_MARK, HTX2_C_MARK,
-};
-static const unsigned int hscif2_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 24),
-};
-static const unsigned int hscif2_clk_c_mux[] = {
-	HSCK2_C_MARK,
-};
-static const unsigned int hscif2_ctrl_c_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
-};
-static const unsigned int hscif2_ctrl_c_mux[] = {
-	HRTS2_N_C_MARK, HCTS2_N_C_MARK,
-};
-/* - HSCIF3 ----------------------------------------------------------------- */
-static const unsigned int hscif3_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
-};
-static const unsigned int hscif3_data_a_mux[] = {
-	HRX3_A_MARK, HTX3_A_MARK,
-};
-static const unsigned int hscif3_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 22),
-};
-static const unsigned int hscif3_clk_mux[] = {
-	HSCK3_MARK,
-};
-static const unsigned int hscif3_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
-};
-static const unsigned int hscif3_ctrl_mux[] = {
-	HRTS3_N_MARK, HCTS3_N_MARK,
-};
-
-static const unsigned int hscif3_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-};
-static const unsigned int hscif3_data_b_mux[] = {
-	HRX3_B_MARK, HTX3_B_MARK,
-};
-static const unsigned int hscif3_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-};
-static const unsigned int hscif3_data_c_mux[] = {
-	HRX3_C_MARK, HTX3_C_MARK,
-};
-static const unsigned int hscif3_data_d_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
-};
-static const unsigned int hscif3_data_d_mux[] = {
-	HRX3_D_MARK, HTX3_D_MARK,
-};
-/* - HSCIF4 ----------------------------------------------------------------- */
-static const unsigned int hscif4_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-};
-static const unsigned int hscif4_data_a_mux[] = {
-	HRX4_A_MARK, HTX4_A_MARK,
-};
-static const unsigned int hscif4_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 11),
-};
-static const unsigned int hscif4_clk_mux[] = {
-	HSCK4_MARK,
-};
-static const unsigned int hscif4_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
-};
-static const unsigned int hscif4_ctrl_mux[] = {
-	HRTS4_N_MARK, HCTS4_N_MARK,
-};
-
-static const unsigned int hscif4_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
-};
-static const unsigned int hscif4_data_b_mux[] = {
-	HRX4_B_MARK, HTX4_B_MARK,
-};
-
-/* - I2C -------------------------------------------------------------------- */
-static const unsigned int i2c0_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
-};
-
-static const unsigned int i2c0_mux[] = {
-	SCL0_MARK, SDA0_MARK,
-};
-
-static const unsigned int i2c1_a_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
-};
-static const unsigned int i2c1_a_mux[] = {
-	SDA1_A_MARK, SCL1_A_MARK,
-};
-static const unsigned int i2c1_b_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
-};
-static const unsigned int i2c1_b_mux[] = {
-	SDA1_B_MARK, SCL1_B_MARK,
-};
-static const unsigned int i2c2_a_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
-};
-static const unsigned int i2c2_a_mux[] = {
-	SDA2_A_MARK, SCL2_A_MARK,
-};
-static const unsigned int i2c2_b_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
-};
-static const unsigned int i2c2_b_mux[] = {
-	SDA2_B_MARK, SCL2_B_MARK,
-};
-
-static const unsigned int i2c3_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
-};
-
-static const unsigned int i2c3_mux[] = {
-	SCL3_MARK, SDA3_MARK,
-};
-
-static const unsigned int i2c5_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
-};
-
-static const unsigned int i2c5_mux[] = {
-	SCL5_MARK, SDA5_MARK,
-};
-
-static const unsigned int i2c6_a_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
-};
-static const unsigned int i2c6_a_mux[] = {
-	SDA6_A_MARK, SCL6_A_MARK,
-};
-static const unsigned int i2c6_b_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
-};
-static const unsigned int i2c6_b_mux[] = {
-	SDA6_B_MARK, SCL6_B_MARK,
-};
-static const unsigned int i2c6_c_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
-};
-static const unsigned int i2c6_c_mux[] = {
-	SDA6_C_MARK, SCL6_C_MARK,
-};
-
-/* - INTC-EX ---------------------------------------------------------------- */
-static const unsigned int intc_ex_irq0_pins[] = {
-	/* IRQ0 */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int intc_ex_irq0_mux[] = {
-	IRQ0_MARK,
-};
-static const unsigned int intc_ex_irq1_pins[] = {
-	/* IRQ1 */
-	RCAR_GP_PIN(2, 1),
-};
-static const unsigned int intc_ex_irq1_mux[] = {
-	IRQ1_MARK,
-};
-static const unsigned int intc_ex_irq2_pins[] = {
-	/* IRQ2 */
-	RCAR_GP_PIN(2, 2),
-};
-static const unsigned int intc_ex_irq2_mux[] = {
-	IRQ2_MARK,
-};
-static const unsigned int intc_ex_irq3_pins[] = {
-	/* IRQ3 */
-	RCAR_GP_PIN(2, 3),
-};
-static const unsigned int intc_ex_irq3_mux[] = {
-	IRQ3_MARK,
-};
-static const unsigned int intc_ex_irq4_pins[] = {
-	/* IRQ4 */
-	RCAR_GP_PIN(2, 4),
-};
-static const unsigned int intc_ex_irq4_mux[] = {
-	IRQ4_MARK,
-};
-static const unsigned int intc_ex_irq5_pins[] = {
-	/* IRQ5 */
-	RCAR_GP_PIN(2, 5),
-};
-static const unsigned int intc_ex_irq5_mux[] = {
-	IRQ5_MARK,
-};
-
-/* - MSIOF0 ----------------------------------------------------------------- */
-static const unsigned int msiof0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 17),
-};
-static const unsigned int msiof0_clk_mux[] = {
-	MSIOF0_SCK_MARK,
-};
-static const unsigned int msiof0_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(5, 18),
-};
-static const unsigned int msiof0_sync_mux[] = {
-	MSIOF0_SYNC_MARK,
-};
-static const unsigned int msiof0_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int msiof0_ss1_mux[] = {
-	MSIOF0_SS1_MARK,
-};
-static const unsigned int msiof0_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(5, 21),
-};
-static const unsigned int msiof0_ss2_mux[] = {
-	MSIOF0_SS2_MARK,
-};
-static const unsigned int msiof0_txd_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(5, 20),
-};
-static const unsigned int msiof0_txd_mux[] = {
-	MSIOF0_TXD_MARK,
-};
-static const unsigned int msiof0_rxd_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 22),
-};
-static const unsigned int msiof0_rxd_mux[] = {
-	MSIOF0_RXD_MARK,
-};
-/* - MSIOF1 ----------------------------------------------------------------- */
-static const unsigned int msiof1_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 8),
-};
-static const unsigned int msiof1_clk_a_mux[] = {
-	MSIOF1_SCK_A_MARK,
-};
-static const unsigned int msiof1_sync_a_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(6, 9),
-};
-static const unsigned int msiof1_sync_a_mux[] = {
-	MSIOF1_SYNC_A_MARK,
-};
-static const unsigned int msiof1_ss1_a_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(6, 5),
-};
-static const unsigned int msiof1_ss1_a_mux[] = {
-	MSIOF1_SS1_A_MARK,
-};
-static const unsigned int msiof1_ss2_a_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(6, 6),
-};
-static const unsigned int msiof1_ss2_a_mux[] = {
-	MSIOF1_SS2_A_MARK,
-};
-static const unsigned int msiof1_txd_a_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(6, 7),
-};
-static const unsigned int msiof1_txd_a_mux[] = {
-	MSIOF1_TXD_A_MARK,
-};
-static const unsigned int msiof1_rxd_a_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(6, 10),
-};
-static const unsigned int msiof1_rxd_a_mux[] = {
-	MSIOF1_RXD_A_MARK,
-};
-static const unsigned int msiof1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 9),
-};
-static const unsigned int msiof1_clk_b_mux[] = {
-	MSIOF1_SCK_B_MARK,
-};
-static const unsigned int msiof1_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(5, 3),
-};
-static const unsigned int msiof1_sync_b_mux[] = {
-	MSIOF1_SYNC_B_MARK,
-};
-static const unsigned int msiof1_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(5, 4),
-};
-static const unsigned int msiof1_ss1_b_mux[] = {
-	MSIOF1_SS1_B_MARK,
-};
-static const unsigned int msiof1_ss2_b_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int msiof1_ss2_b_mux[] = {
-	MSIOF1_SS2_B_MARK,
-};
-static const unsigned int msiof1_txd_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(5, 8),
-};
-static const unsigned int msiof1_txd_b_mux[] = {
-	MSIOF1_TXD_B_MARK,
-};
-static const unsigned int msiof1_rxd_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 7),
-};
-static const unsigned int msiof1_rxd_b_mux[] = {
-	MSIOF1_RXD_B_MARK,
-};
-static const unsigned int msiof1_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 17),
-};
-static const unsigned int msiof1_clk_c_mux[] = {
-	MSIOF1_SCK_C_MARK,
-};
-static const unsigned int msiof1_sync_c_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(6, 18),
-};
-static const unsigned int msiof1_sync_c_mux[] = {
-	MSIOF1_SYNC_C_MARK,
-};
-static const unsigned int msiof1_ss1_c_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int msiof1_ss1_c_mux[] = {
-	MSIOF1_SS1_C_MARK,
-};
-static const unsigned int msiof1_ss2_c_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(6, 27),
-};
-static const unsigned int msiof1_ss2_c_mux[] = {
-	MSIOF1_SS2_C_MARK,
-};
-static const unsigned int msiof1_txd_c_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(6, 20),
-};
-static const unsigned int msiof1_txd_c_mux[] = {
-	MSIOF1_TXD_C_MARK,
-};
-static const unsigned int msiof1_rxd_c_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(6, 19),
-};
-static const unsigned int msiof1_rxd_c_mux[] = {
-	MSIOF1_RXD_C_MARK,
-};
-static const unsigned int msiof1_clk_d_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 12),
-};
-static const unsigned int msiof1_clk_d_mux[] = {
-	MSIOF1_SCK_D_MARK,
-};
-static const unsigned int msiof1_sync_d_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(5, 15),
-};
-static const unsigned int msiof1_sync_d_mux[] = {
-	MSIOF1_SYNC_D_MARK,
-};
-static const unsigned int msiof1_ss1_d_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(5, 16),
-};
-static const unsigned int msiof1_ss1_d_mux[] = {
-	MSIOF1_SS1_D_MARK,
-};
-static const unsigned int msiof1_ss2_d_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(5, 21),
-};
-static const unsigned int msiof1_ss2_d_mux[] = {
-	MSIOF1_SS2_D_MARK,
-};
-static const unsigned int msiof1_txd_d_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(5, 14),
-};
-static const unsigned int msiof1_txd_d_mux[] = {
-	MSIOF1_TXD_D_MARK,
-};
-static const unsigned int msiof1_rxd_d_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 13),
-};
-static const unsigned int msiof1_rxd_d_mux[] = {
-	MSIOF1_RXD_D_MARK,
-};
-static const unsigned int msiof1_clk_e_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 0),
-};
-static const unsigned int msiof1_clk_e_mux[] = {
-	MSIOF1_SCK_E_MARK,
-};
-static const unsigned int msiof1_sync_e_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(3, 1),
-};
-static const unsigned int msiof1_sync_e_mux[] = {
-	MSIOF1_SYNC_E_MARK,
-};
-static const unsigned int msiof1_ss1_e_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(3, 4),
-};
-static const unsigned int msiof1_ss1_e_mux[] = {
-	MSIOF1_SS1_E_MARK,
-};
-static const unsigned int msiof1_ss2_e_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(3, 5),
-};
-static const unsigned int msiof1_ss2_e_mux[] = {
-	MSIOF1_SS2_E_MARK,
-};
-static const unsigned int msiof1_txd_e_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(3, 3),
-};
-static const unsigned int msiof1_txd_e_mux[] = {
-	MSIOF1_TXD_E_MARK,
-};
-static const unsigned int msiof1_rxd_e_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(3, 2),
-};
-static const unsigned int msiof1_rxd_e_mux[] = {
-	MSIOF1_RXD_E_MARK,
-};
-static const unsigned int msiof1_clk_f_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 23),
-};
-static const unsigned int msiof1_clk_f_mux[] = {
-	MSIOF1_SCK_F_MARK,
-};
-static const unsigned int msiof1_sync_f_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(5, 24),
-};
-static const unsigned int msiof1_sync_f_mux[] = {
-	MSIOF1_SYNC_F_MARK,
-};
-static const unsigned int msiof1_ss1_f_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(6, 1),
-};
-static const unsigned int msiof1_ss1_f_mux[] = {
-	MSIOF1_SS1_F_MARK,
-};
-static const unsigned int msiof1_ss2_f_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(6, 2),
-};
-static const unsigned int msiof1_ss2_f_mux[] = {
-	MSIOF1_SS2_F_MARK,
-};
-static const unsigned int msiof1_txd_f_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(6, 0),
-};
-static const unsigned int msiof1_txd_f_mux[] = {
-	MSIOF1_TXD_F_MARK,
-};
-static const unsigned int msiof1_rxd_f_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 25),
-};
-static const unsigned int msiof1_rxd_f_mux[] = {
-	MSIOF1_RXD_F_MARK,
-};
-static const unsigned int msiof1_clk_g_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 6),
-};
-static const unsigned int msiof1_clk_g_mux[] = {
-	MSIOF1_SCK_G_MARK,
-};
-static const unsigned int msiof1_sync_g_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(3, 7),
-};
-static const unsigned int msiof1_sync_g_mux[] = {
-	MSIOF1_SYNC_G_MARK,
-};
-static const unsigned int msiof1_ss1_g_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(3, 10),
-};
-static const unsigned int msiof1_ss1_g_mux[] = {
-	MSIOF1_SS1_G_MARK,
-};
-static const unsigned int msiof1_ss2_g_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(3, 11),
-};
-static const unsigned int msiof1_ss2_g_mux[] = {
-	MSIOF1_SS2_G_MARK,
-};
-static const unsigned int msiof1_txd_g_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(3, 9),
-};
-static const unsigned int msiof1_txd_g_mux[] = {
-	MSIOF1_TXD_G_MARK,
-};
-static const unsigned int msiof1_rxd_g_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(3, 8),
-};
-static const unsigned int msiof1_rxd_g_mux[] = {
-	MSIOF1_RXD_G_MARK,
-};
-/* - MSIOF2 ----------------------------------------------------------------- */
-static const unsigned int msiof2_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 9),
-};
-static const unsigned int msiof2_clk_a_mux[] = {
-	MSIOF2_SCK_A_MARK,
-};
-static const unsigned int msiof2_sync_a_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 8),
-};
-static const unsigned int msiof2_sync_a_mux[] = {
-	MSIOF2_SYNC_A_MARK,
-};
-static const unsigned int msiof2_ss1_a_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(1, 6),
-};
-static const unsigned int msiof2_ss1_a_mux[] = {
-	MSIOF2_SS1_A_MARK,
-};
-static const unsigned int msiof2_ss2_a_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(1, 7),
-};
-static const unsigned int msiof2_ss2_a_mux[] = {
-	MSIOF2_SS2_A_MARK,
-};
-static const unsigned int msiof2_txd_a_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 11),
-};
-static const unsigned int msiof2_txd_a_mux[] = {
-	MSIOF2_TXD_A_MARK,
-};
-static const unsigned int msiof2_rxd_a_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 10),
-};
-static const unsigned int msiof2_rxd_a_mux[] = {
-	MSIOF2_RXD_A_MARK,
-};
-static const unsigned int msiof2_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 4),
-};
-static const unsigned int msiof2_clk_b_mux[] = {
-	MSIOF2_SCK_B_MARK,
-};
-static const unsigned int msiof2_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 5),
-};
-static const unsigned int msiof2_sync_b_mux[] = {
-	MSIOF2_SYNC_B_MARK,
-};
-static const unsigned int msiof2_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 0),
-};
-static const unsigned int msiof2_ss1_b_mux[] = {
-	MSIOF2_SS1_B_MARK,
-};
-static const unsigned int msiof2_ss2_b_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 1),
-};
-static const unsigned int msiof2_ss2_b_mux[] = {
-	MSIOF2_SS2_B_MARK,
-};
-static const unsigned int msiof2_txd_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 7),
-};
-static const unsigned int msiof2_txd_b_mux[] = {
-	MSIOF2_TXD_B_MARK,
-};
-static const unsigned int msiof2_rxd_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 6),
-};
-static const unsigned int msiof2_rxd_b_mux[] = {
-	MSIOF2_RXD_B_MARK,
-};
-static const unsigned int msiof2_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 12),
-};
-static const unsigned int msiof2_clk_c_mux[] = {
-	MSIOF2_SCK_C_MARK,
-};
-static const unsigned int msiof2_sync_c_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(2, 11),
-};
-static const unsigned int msiof2_sync_c_mux[] = {
-	MSIOF2_SYNC_C_MARK,
-};
-static const unsigned int msiof2_ss1_c_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(2, 10),
-};
-static const unsigned int msiof2_ss1_c_mux[] = {
-	MSIOF2_SS1_C_MARK,
-};
-static const unsigned int msiof2_ss2_c_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(2, 9),
-};
-static const unsigned int msiof2_ss2_c_mux[] = {
-	MSIOF2_SS2_C_MARK,
-};
-static const unsigned int msiof2_txd_c_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(2, 14),
-};
-static const unsigned int msiof2_txd_c_mux[] = {
-	MSIOF2_TXD_C_MARK,
-};
-static const unsigned int msiof2_rxd_c_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(2, 13),
-};
-static const unsigned int msiof2_rxd_c_mux[] = {
-	MSIOF2_RXD_C_MARK,
-};
-static const unsigned int msiof2_clk_d_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 8),
-};
-static const unsigned int msiof2_clk_d_mux[] = {
-	MSIOF2_SCK_D_MARK,
-};
-static const unsigned int msiof2_sync_d_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 9),
-};
-static const unsigned int msiof2_sync_d_mux[] = {
-	MSIOF2_SYNC_D_MARK,
-};
-static const unsigned int msiof2_ss1_d_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 12),
-};
-static const unsigned int msiof2_ss1_d_mux[] = {
-	MSIOF2_SS1_D_MARK,
-};
-static const unsigned int msiof2_ss2_d_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 13),
-};
-static const unsigned int msiof2_ss2_d_mux[] = {
-	MSIOF2_SS2_D_MARK,
-};
-static const unsigned int msiof2_txd_d_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 11),
-};
-static const unsigned int msiof2_txd_d_mux[] = {
-	MSIOF2_TXD_D_MARK,
-};
-static const unsigned int msiof2_rxd_d_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 10),
-};
-static const unsigned int msiof2_rxd_d_mux[] = {
-	MSIOF2_RXD_D_MARK,
-};
-/* - MSIOF3 ----------------------------------------------------------------- */
-static const unsigned int msiof3_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 0),
-};
-static const unsigned int msiof3_clk_a_mux[] = {
-	MSIOF3_SCK_A_MARK,
-};
-static const unsigned int msiof3_sync_a_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 1),
-};
-static const unsigned int msiof3_sync_a_mux[] = {
-	MSIOF3_SYNC_A_MARK,
-};
-static const unsigned int msiof3_ss1_a_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 14),
-};
-static const unsigned int msiof3_ss1_a_mux[] = {
-	MSIOF3_SS1_A_MARK,
-};
-static const unsigned int msiof3_ss2_a_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 15),
-};
-static const unsigned int msiof3_ss2_a_mux[] = {
-	MSIOF3_SS2_A_MARK,
-};
-static const unsigned int msiof3_txd_a_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 3),
-};
-static const unsigned int msiof3_txd_a_mux[] = {
-	MSIOF3_TXD_A_MARK,
-};
-static const unsigned int msiof3_rxd_a_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 2),
-};
-static const unsigned int msiof3_rxd_a_mux[] = {
-	MSIOF3_RXD_A_MARK,
-};
-static const unsigned int msiof3_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 2),
-};
-static const unsigned int msiof3_clk_b_mux[] = {
-	MSIOF3_SCK_B_MARK,
-};
-static const unsigned int msiof3_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 0),
-};
-static const unsigned int msiof3_sync_b_mux[] = {
-	MSIOF3_SYNC_B_MARK,
-};
-static const unsigned int msiof3_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(1, 4),
-};
-static const unsigned int msiof3_ss1_b_mux[] = {
-	MSIOF3_SS1_B_MARK,
-};
-static const unsigned int msiof3_ss2_b_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(1, 5),
-};
-static const unsigned int msiof3_ss2_b_mux[] = {
-	MSIOF3_SS2_B_MARK,
-};
-static const unsigned int msiof3_txd_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 1),
-};
-static const unsigned int msiof3_txd_b_mux[] = {
-	MSIOF3_TXD_B_MARK,
-};
-static const unsigned int msiof3_rxd_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 3),
-};
-static const unsigned int msiof3_rxd_b_mux[] = {
-	MSIOF3_RXD_B_MARK,
-};
-static const unsigned int msiof3_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 12),
-};
-static const unsigned int msiof3_clk_c_mux[] = {
-	MSIOF3_SCK_C_MARK,
-};
-static const unsigned int msiof3_sync_c_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 13),
-};
-static const unsigned int msiof3_sync_c_mux[] = {
-	MSIOF3_SYNC_C_MARK,
-};
-static const unsigned int msiof3_txd_c_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 15),
-};
-static const unsigned int msiof3_txd_c_mux[] = {
-	MSIOF3_TXD_C_MARK,
-};
-static const unsigned int msiof3_rxd_c_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 14),
-};
-static const unsigned int msiof3_rxd_c_mux[] = {
-	MSIOF3_RXD_C_MARK,
-};
-static const unsigned int msiof3_clk_d_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 22),
-};
-static const unsigned int msiof3_clk_d_mux[] = {
-	MSIOF3_SCK_D_MARK,
-};
-static const unsigned int msiof3_sync_d_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 23),
-};
-static const unsigned int msiof3_sync_d_mux[] = {
-	MSIOF3_SYNC_D_MARK,
-};
-static const unsigned int msiof3_ss1_d_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(1, 26),
-};
-static const unsigned int msiof3_ss1_d_mux[] = {
-	MSIOF3_SS1_D_MARK,
-};
-static const unsigned int msiof3_txd_d_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 25),
-};
-static const unsigned int msiof3_txd_d_mux[] = {
-	MSIOF3_TXD_D_MARK,
-};
-static const unsigned int msiof3_rxd_d_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 24),
-};
-static const unsigned int msiof3_rxd_d_mux[] = {
-	MSIOF3_RXD_D_MARK,
-};
-
-static const unsigned int msiof3_clk_e_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 3),
-};
-static const unsigned int msiof3_clk_e_mux[] = {
-	MSIOF3_SCK_E_MARK,
-};
-static const unsigned int msiof3_sync_e_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(2, 2),
-};
-static const unsigned int msiof3_sync_e_mux[] = {
-	MSIOF3_SYNC_E_MARK,
-};
-static const unsigned int msiof3_ss1_e_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(2, 1),
-};
-static const unsigned int msiof3_ss1_e_mux[] = {
-	MSIOF3_SS1_E_MARK,
-};
-static const unsigned int msiof3_ss2_e_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int msiof3_ss2_e_mux[] = {
-	MSIOF3_SS2_E_MARK,
-};
-static const unsigned int msiof3_txd_e_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(2, 5),
-};
-static const unsigned int msiof3_txd_e_mux[] = {
-	MSIOF3_TXD_E_MARK,
-};
-static const unsigned int msiof3_rxd_e_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(2, 4),
-};
-static const unsigned int msiof3_rxd_e_mux[] = {
-	MSIOF3_RXD_E_MARK,
-};
-
-/* - PWM0 --------------------------------------------------------------------*/
-static const unsigned int pwm0_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 6),
-};
-static const unsigned int pwm0_mux[] = {
-	PWM0_MARK,
-};
-/* - PWM1 --------------------------------------------------------------------*/
-static const unsigned int pwm1_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 7),
-};
-static const unsigned int pwm1_a_mux[] = {
-	PWM1_A_MARK,
-};
-static const unsigned int pwm1_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 8),
-};
-static const unsigned int pwm1_b_mux[] = {
-	PWM1_B_MARK,
-};
-/* - PWM2 --------------------------------------------------------------------*/
-static const unsigned int pwm2_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 8),
-};
-static const unsigned int pwm2_a_mux[] = {
-	PWM2_A_MARK,
-};
-static const unsigned int pwm2_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 11),
-};
-static const unsigned int pwm2_b_mux[] = {
-	PWM2_B_MARK,
-};
-/* - PWM3 --------------------------------------------------------------------*/
-static const unsigned int pwm3_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 0),
-};
-static const unsigned int pwm3_a_mux[] = {
-	PWM3_A_MARK,
-};
-static const unsigned int pwm3_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 2),
-};
-static const unsigned int pwm3_b_mux[] = {
-	PWM3_B_MARK,
-};
-/* - PWM4 --------------------------------------------------------------------*/
-static const unsigned int pwm4_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 1),
-};
-static const unsigned int pwm4_a_mux[] = {
-	PWM4_A_MARK,
-};
-static const unsigned int pwm4_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 3),
-};
-static const unsigned int pwm4_b_mux[] = {
-	PWM4_B_MARK,
-};
-/* - PWM5 --------------------------------------------------------------------*/
-static const unsigned int pwm5_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 2),
-};
-static const unsigned int pwm5_a_mux[] = {
-	PWM5_A_MARK,
-};
-static const unsigned int pwm5_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 4),
-};
-static const unsigned int pwm5_b_mux[] = {
-	PWM5_B_MARK,
-};
-/* - PWM6 --------------------------------------------------------------------*/
-static const unsigned int pwm6_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 3),
-};
-static const unsigned int pwm6_a_mux[] = {
-	PWM6_A_MARK,
-};
-static const unsigned int pwm6_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 5),
-};
-static const unsigned int pwm6_b_mux[] = {
-	PWM6_B_MARK,
-};
-
-/* - SCIF0 ------------------------------------------------------------------ */
-static const unsigned int scif0_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-};
-static const unsigned int scif0_data_mux[] = {
-	RX0_MARK, TX0_MARK,
-};
-static const unsigned int scif0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int scif0_clk_mux[] = {
-	SCK0_MARK,
-};
-static const unsigned int scif0_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
-};
-static const unsigned int scif0_ctrl_mux[] = {
-	RTS0_N_MARK, CTS0_N_MARK,
-};
-/* - SCIF1 ------------------------------------------------------------------ */
-static const unsigned int scif1_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
-};
-static const unsigned int scif1_data_a_mux[] = {
-	RX1_A_MARK, TX1_A_MARK,
-};
-static const unsigned int scif1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int scif1_clk_mux[] = {
-	SCK1_MARK,
-};
-static const unsigned int scif1_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
-};
-static const unsigned int scif1_ctrl_mux[] = {
-	RTS1_N_MARK, CTS1_N_MARK,
-};
-
-static const unsigned int scif1_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
-};
-static const unsigned int scif1_data_b_mux[] = {
-	RX1_B_MARK, TX1_B_MARK,
-};
-/* - SCIF2 ------------------------------------------------------------------ */
-static const unsigned int scif2_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
-};
-static const unsigned int scif2_data_a_mux[] = {
-	RX2_A_MARK, TX2_A_MARK,
-};
-static const unsigned int scif2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 9),
-};
-static const unsigned int scif2_clk_mux[] = {
-	SCK2_MARK,
-};
-static const unsigned int scif2_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
-};
-static const unsigned int scif2_data_b_mux[] = {
-	RX2_B_MARK, TX2_B_MARK,
-};
-/* - SCIF3 ------------------------------------------------------------------ */
-static const unsigned int scif3_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
-};
-static const unsigned int scif3_data_a_mux[] = {
-	RX3_A_MARK, TX3_A_MARK,
-};
-static const unsigned int scif3_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 22),
-};
-static const unsigned int scif3_clk_mux[] = {
-	SCK3_MARK,
-};
-static const unsigned int scif3_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
-};
-static const unsigned int scif3_ctrl_mux[] = {
-	RTS3_N_MARK, CTS3_N_MARK,
-};
-static const unsigned int scif3_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
-};
-static const unsigned int scif3_data_b_mux[] = {
-	RX3_B_MARK, TX3_B_MARK,
-};
-/* - SCIF4 ------------------------------------------------------------------ */
-static const unsigned int scif4_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
-};
-static const unsigned int scif4_data_a_mux[] = {
-	RX4_A_MARK, TX4_A_MARK,
-};
-static const unsigned int scif4_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 10),
-};
-static const unsigned int scif4_clk_a_mux[] = {
-	SCK4_A_MARK,
-};
-static const unsigned int scif4_ctrl_a_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
-};
-static const unsigned int scif4_ctrl_a_mux[] = {
-	RTS4_N_A_MARK, CTS4_N_A_MARK,
-};
-static const unsigned int scif4_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-};
-static const unsigned int scif4_data_b_mux[] = {
-	RX4_B_MARK, TX4_B_MARK,
-};
-static const unsigned int scif4_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 5),
-};
-static const unsigned int scif4_clk_b_mux[] = {
-	SCK4_B_MARK,
-};
-static const unsigned int scif4_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
-};
-static const unsigned int scif4_ctrl_b_mux[] = {
-	RTS4_N_B_MARK, CTS4_N_B_MARK,
-};
-static const unsigned int scif4_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-};
-static const unsigned int scif4_data_c_mux[] = {
-	RX4_C_MARK, TX4_C_MARK,
-};
-static const unsigned int scif4_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 8),
-};
-static const unsigned int scif4_clk_c_mux[] = {
-	SCK4_C_MARK,
-};
-static const unsigned int scif4_ctrl_c_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
-};
-static const unsigned int scif4_ctrl_c_mux[] = {
-	RTS4_N_C_MARK, CTS4_N_C_MARK,
-};
-/* - SCIF5 ------------------------------------------------------------------ */
-static const unsigned int scif5_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
-};
-static const unsigned int scif5_data_a_mux[] = {
-	RX5_A_MARK, TX5_A_MARK,
-};
-static const unsigned int scif5_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int scif5_clk_a_mux[] = {
-	SCK5_A_MARK,
-};
-
-static const unsigned int scif5_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
-};
-static const unsigned int scif5_data_b_mux[] = {
-	RX5_B_MARK, TX5_B_MARK,
-};
-static const unsigned int scif5_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int scif5_clk_b_mux[] = {
-	SCK5_B_MARK,
-};
-
-/* - SCIF Clock ------------------------------------------------------------- */
-static const unsigned int scif_clk_a_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(6, 23),
-};
-static const unsigned int scif_clk_a_mux[] = {
-	SCIF_CLK_A_MARK,
-};
-static const unsigned int scif_clk_b_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(5, 9),
-};
-static const unsigned int scif_clk_b_mux[] = {
-	SCIF_CLK_B_MARK,
-};
-
-/* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 2),
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SD0_DAT0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
-	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
-};
-static const unsigned int sdhi0_data4_mux[] = {
-	SD0_DAT0_MARK, SD0_DAT1_MARK,
-	SD0_DAT2_MARK, SD0_DAT3_MARK,
-};
-static const unsigned int sdhi0_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
-};
-static const unsigned int sdhi0_ctrl_mux[] = {
-	SD0_CLK_MARK, SD0_CMD_MARK,
-};
-static const unsigned int sdhi0_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(3, 12),
-};
-static const unsigned int sdhi0_cd_mux[] = {
-	SD0_CD_MARK,
-};
-static const unsigned int sdhi0_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(3, 13),
-};
-static const unsigned int sdhi0_wp_mux[] = {
-	SD0_WP_MARK,
-};
-/* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 8),
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	SD1_DAT0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-};
-static const unsigned int sdhi1_data4_mux[] = {
-	SD1_DAT0_MARK, SD1_DAT1_MARK,
-	SD1_DAT2_MARK, SD1_DAT3_MARK,
-};
-static const unsigned int sdhi1_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-};
-static const unsigned int sdhi1_ctrl_mux[] = {
-	SD1_CLK_MARK, SD1_CMD_MARK,
-};
-static const unsigned int sdhi1_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(3, 14),
-};
-static const unsigned int sdhi1_cd_mux[] = {
-	SD1_CD_MARK,
-};
-static const unsigned int sdhi1_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(3, 15),
-};
-static const unsigned int sdhi1_wp_mux[] = {
-	SD1_WP_MARK,
-};
-/* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(4, 2),
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SD2_DAT0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-};
-static const unsigned int sdhi2_data4_mux[] = {
-	SD2_DAT0_MARK, SD2_DAT1_MARK,
-	SD2_DAT2_MARK, SD2_DAT3_MARK,
-};
-static const unsigned int sdhi2_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
-	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
-	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-};
-static const unsigned int sdhi2_data8_mux[] = {
-	SD2_DAT0_MARK, SD2_DAT1_MARK,
-	SD2_DAT2_MARK, SD2_DAT3_MARK,
-	SD2_DAT4_MARK, SD2_DAT5_MARK,
-	SD2_DAT6_MARK, SD2_DAT7_MARK,
-};
-static const unsigned int sdhi2_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
-};
-static const unsigned int sdhi2_ctrl_mux[] = {
-	SD2_CLK_MARK, SD2_CMD_MARK,
-};
-static const unsigned int sdhi2_cd_a_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(4, 13),
-};
-static const unsigned int sdhi2_cd_a_mux[] = {
-	SD2_CD_A_MARK,
-};
-static const unsigned int sdhi2_cd_b_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(5, 10),
-};
-static const unsigned int sdhi2_cd_b_mux[] = {
-	SD2_CD_B_MARK,
-};
-static const unsigned int sdhi2_wp_a_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(4, 14),
-};
-static const unsigned int sdhi2_wp_a_mux[] = {
-	SD2_WP_A_MARK,
-};
-static const unsigned int sdhi2_wp_b_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(5, 11),
-};
-static const unsigned int sdhi2_wp_b_mux[] = {
-	SD2_WP_B_MARK,
-};
-static const unsigned int sdhi2_ds_pins[] = {
-	/* DS */
-	RCAR_GP_PIN(4, 6),
-};
-static const unsigned int sdhi2_ds_mux[] = {
-	SD2_DS_MARK,
-};
-/* - SDHI3 ------------------------------------------------------------------ */
-static const unsigned int sdhi3_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(4, 9),
-};
-static const unsigned int sdhi3_data1_mux[] = {
-	SD3_DAT0_MARK,
-};
-static const unsigned int sdhi3_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
-	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
-};
-static const unsigned int sdhi3_data4_mux[] = {
-	SD3_DAT0_MARK, SD3_DAT1_MARK,
-	SD3_DAT2_MARK, SD3_DAT3_MARK,
-};
-static const unsigned int sdhi3_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
-	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
-	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
-	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
-};
-static const unsigned int sdhi3_data8_mux[] = {
-	SD3_DAT0_MARK, SD3_DAT1_MARK,
-	SD3_DAT2_MARK, SD3_DAT3_MARK,
-	SD3_DAT4_MARK, SD3_DAT5_MARK,
-	SD3_DAT6_MARK, SD3_DAT7_MARK,
-};
-static const unsigned int sdhi3_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
-};
-static const unsigned int sdhi3_ctrl_mux[] = {
-	SD3_CLK_MARK, SD3_CMD_MARK,
-};
-static const unsigned int sdhi3_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(4, 15),
-};
-static const unsigned int sdhi3_cd_mux[] = {
-	SD3_CD_MARK,
-};
-static const unsigned int sdhi3_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(4, 16),
-};
-static const unsigned int sdhi3_wp_mux[] = {
-	SD3_WP_MARK,
-};
-static const unsigned int sdhi3_ds_pins[] = {
-	/* DS */
-	RCAR_GP_PIN(4, 17),
-};
-static const unsigned int sdhi3_ds_mux[] = {
-	SD3_DS_MARK,
-};
-
-/* - SSI -------------------------------------------------------------------- */
-static const unsigned int ssi0_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 2),
-};
-static const unsigned int ssi0_data_mux[] = {
-	SSI_SDATA0_MARK,
-};
-static const unsigned int ssi01239_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
-};
-static const unsigned int ssi01239_ctrl_mux[] = {
-	SSI_SCK01239_MARK, SSI_WS01239_MARK,
-};
-static const unsigned int ssi1_data_a_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 3),
-};
-static const unsigned int ssi1_data_a_mux[] = {
-	SSI_SDATA1_A_MARK,
-};
-static const unsigned int ssi1_data_b_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(5, 12),
-};
-static const unsigned int ssi1_data_b_mux[] = {
-	SSI_SDATA1_B_MARK,
-};
-static const unsigned int ssi1_ctrl_a_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
-};
-static const unsigned int ssi1_ctrl_a_mux[] = {
-	SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
-};
-static const unsigned int ssi1_ctrl_b_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
-};
-static const unsigned int ssi1_ctrl_b_mux[] = {
-	SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
-};
-static const unsigned int ssi2_data_a_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 4),
-};
-static const unsigned int ssi2_data_a_mux[] = {
-	SSI_SDATA2_A_MARK,
-};
-static const unsigned int ssi2_data_b_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(5, 13),
-};
-static const unsigned int ssi2_data_b_mux[] = {
-	SSI_SDATA2_B_MARK,
-};
-static const unsigned int ssi2_ctrl_a_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
-};
-static const unsigned int ssi2_ctrl_a_mux[] = {
-	SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
-};
-static const unsigned int ssi2_ctrl_b_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
-};
-static const unsigned int ssi2_ctrl_b_mux[] = {
-	SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
-};
-static const unsigned int ssi3_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 7),
-};
-static const unsigned int ssi3_data_mux[] = {
-	SSI_SDATA3_MARK,
-};
-static const unsigned int ssi349_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
-};
-static const unsigned int ssi349_ctrl_mux[] = {
-	SSI_SCK349_MARK, SSI_WS349_MARK,
-};
-static const unsigned int ssi4_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 10),
-};
-static const unsigned int ssi4_data_mux[] = {
-	SSI_SDATA4_MARK,
-};
-static const unsigned int ssi4_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
-};
-static const unsigned int ssi4_ctrl_mux[] = {
-	SSI_SCK4_MARK, SSI_WS4_MARK,
-};
-static const unsigned int ssi5_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 13),
-};
-static const unsigned int ssi5_data_mux[] = {
-	SSI_SDATA5_MARK,
-};
-static const unsigned int ssi5_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
-};
-static const unsigned int ssi5_ctrl_mux[] = {
-	SSI_SCK5_MARK, SSI_WS5_MARK,
-};
-static const unsigned int ssi6_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 16),
-};
-static const unsigned int ssi6_data_mux[] = {
-	SSI_SDATA6_MARK,
-};
-static const unsigned int ssi6_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
-};
-static const unsigned int ssi6_ctrl_mux[] = {
-	SSI_SCK6_MARK, SSI_WS6_MARK,
-};
-static const unsigned int ssi7_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 19),
-};
-static const unsigned int ssi7_data_mux[] = {
-	SSI_SDATA7_MARK,
-};
-static const unsigned int ssi78_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
-};
-static const unsigned int ssi78_ctrl_mux[] = {
-	SSI_SCK78_MARK, SSI_WS78_MARK,
-};
-static const unsigned int ssi8_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 20),
-};
-static const unsigned int ssi8_data_mux[] = {
-	SSI_SDATA8_MARK,
-};
-static const unsigned int ssi9_data_a_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int ssi9_data_a_mux[] = {
-	SSI_SDATA9_A_MARK,
-};
-static const unsigned int ssi9_data_b_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(5, 14),
-};
-static const unsigned int ssi9_data_b_mux[] = {
-	SSI_SDATA9_B_MARK,
-};
-static const unsigned int ssi9_ctrl_a_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
-};
-static const unsigned int ssi9_ctrl_a_mux[] = {
-	SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
-};
-static const unsigned int ssi9_ctrl_b_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
-};
-static const unsigned int ssi9_ctrl_b_mux[] = {
-	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
-};
-
-/* - TMU -------------------------------------------------------------------- */
-static const unsigned int tmu_tclk1_a_pins[] = {
-	/* TCLK */
-	RCAR_GP_PIN(6, 23),
-};
-static const unsigned int tmu_tclk1_a_mux[] = {
-	TCLK1_A_MARK,
-};
-static const unsigned int tmu_tclk1_b_pins[] = {
-	/* TCLK */
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int tmu_tclk1_b_mux[] = {
-	TCLK1_B_MARK,
-};
-static const unsigned int tmu_tclk2_a_pins[] = {
-	/* TCLK */
-	RCAR_GP_PIN(6, 19),
-};
-static const unsigned int tmu_tclk2_a_mux[] = {
-	TCLK2_A_MARK,
-};
-static const unsigned int tmu_tclk2_b_pins[] = {
-	/* TCLK */
-	RCAR_GP_PIN(6, 28),
-};
-static const unsigned int tmu_tclk2_b_mux[] = {
-	TCLK2_B_MARK,
-};
-
-/* - TPU ------------------------------------------------------------------- */
-static const unsigned int tpu_to0_pins[] = {
-	/* TPU0TO0 */
-	RCAR_GP_PIN(6, 28),
-};
-static const unsigned int tpu_to0_mux[] = {
-	TPU0TO0_MARK,
-};
-static const unsigned int tpu_to1_pins[] = {
-	/* TPU0TO1 */
-	RCAR_GP_PIN(6, 29),
-};
-static const unsigned int tpu_to1_mux[] = {
-	TPU0TO1_MARK,
-};
-static const unsigned int tpu_to2_pins[] = {
-	/* TPU0TO2 */
-	RCAR_GP_PIN(6, 30),
-};
-static const unsigned int tpu_to2_mux[] = {
-	TPU0TO2_MARK,
-};
-static const unsigned int tpu_to3_pins[] = {
-	/* TPU0TO3 */
-	RCAR_GP_PIN(6, 31),
-};
-static const unsigned int tpu_to3_mux[] = {
-	TPU0TO3_MARK,
-};
-
-/* - USB0 ------------------------------------------------------------------- */
-static const unsigned int usb0_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
-};
-static const unsigned int usb0_mux[] = {
-	USB0_PWEN_MARK, USB0_OVC_MARK,
-};
-/* - USB1 ------------------------------------------------------------------- */
-static const unsigned int usb1_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
-};
-static const unsigned int usb1_mux[] = {
-	USB1_PWEN_MARK, USB1_OVC_MARK,
-};
-
-/* - USB30 ------------------------------------------------------------------ */
-static const unsigned int usb30_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
-};
-static const unsigned int usb30_mux[] = {
-	USB30_PWEN_MARK, USB30_OVC_MARK,
-};
-
-/* - VIN4 ------------------------------------------------------------------- */
-static const unsigned int vin4_data18_a_pins[] = {
-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-};
-static const unsigned int vin4_data18_a_mux[] = {
-	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-	VI4_DATA10_MARK, VI4_DATA11_MARK,
-	VI4_DATA12_MARK, VI4_DATA13_MARK,
-	VI4_DATA14_MARK, VI4_DATA15_MARK,
-	VI4_DATA18_MARK, VI4_DATA19_MARK,
-	VI4_DATA20_MARK, VI4_DATA21_MARK,
-	VI4_DATA22_MARK, VI4_DATA23_MARK,
-};
-static const unsigned int vin4_data18_b_pins[] = {
-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-};
-static const unsigned int vin4_data18_b_mux[] = {
-	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
-	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
-	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
-	VI4_DATA10_MARK, VI4_DATA11_MARK,
-	VI4_DATA12_MARK, VI4_DATA13_MARK,
-	VI4_DATA14_MARK, VI4_DATA15_MARK,
-	VI4_DATA18_MARK, VI4_DATA19_MARK,
-	VI4_DATA20_MARK, VI4_DATA21_MARK,
-	VI4_DATA22_MARK, VI4_DATA23_MARK,
-};
-static const union vin_data vin4_data_a_pins = {
-	.data24 = {
-		RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-		RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-		RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-		RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-		RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-	},
-};
-static const union vin_data vin4_data_a_mux = {
-	.data24 = {
-		VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
-		VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-		VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-		VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-		VI4_DATA8_MARK,  VI4_DATA9_MARK,
-		VI4_DATA10_MARK, VI4_DATA11_MARK,
-		VI4_DATA12_MARK, VI4_DATA13_MARK,
-		VI4_DATA14_MARK, VI4_DATA15_MARK,
-		VI4_DATA16_MARK, VI4_DATA17_MARK,
-		VI4_DATA18_MARK, VI4_DATA19_MARK,
-		VI4_DATA20_MARK, VI4_DATA21_MARK,
-		VI4_DATA22_MARK, VI4_DATA23_MARK,
-	},
-};
-static const union vin_data vin4_data_b_pins = {
-	.data24 = {
-		RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-		RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-		RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-		RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-		RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-		RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-	},
-};
-static const union vin_data vin4_data_b_mux = {
-	.data24 = {
-		VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
-		VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
-		VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
-		VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
-		VI4_DATA8_MARK,  VI4_DATA9_MARK,
-		VI4_DATA10_MARK, VI4_DATA11_MARK,
-		VI4_DATA12_MARK, VI4_DATA13_MARK,
-		VI4_DATA14_MARK, VI4_DATA15_MARK,
-		VI4_DATA16_MARK, VI4_DATA17_MARK,
-		VI4_DATA18_MARK, VI4_DATA19_MARK,
-		VI4_DATA20_MARK, VI4_DATA21_MARK,
-		VI4_DATA22_MARK, VI4_DATA23_MARK,
-	},
-};
-static const unsigned int vin4_sync_pins[] = {
-	/* HSYNC#, VSYNC# */
-	RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
-};
-static const unsigned int vin4_sync_mux[] = {
-	VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
-};
-static const unsigned int vin4_field_pins[] = {
-	/* FIELD */
-	RCAR_GP_PIN(1, 16),
-};
-static const unsigned int vin4_field_mux[] = {
-	VI4_FIELD_MARK,
-};
-static const unsigned int vin4_clkenb_pins[] = {
-	/* CLKENB */
-	RCAR_GP_PIN(1, 19),
-};
-static const unsigned int vin4_clkenb_mux[] = {
-	VI4_CLKENB_MARK,
-};
-static const unsigned int vin4_clk_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(1, 27),
-};
-static const unsigned int vin4_clk_mux[] = {
-	VI4_CLK_MARK,
-};
-
-/* - VIN5 ------------------------------------------------------------------- */
-static const union vin_data16 vin5_data_pins = {
-	.data16 = {
-		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-		RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-	},
-};
-static const union vin_data16 vin5_data_mux = {
-	.data16 = {
-		VI5_DATA0_MARK, VI5_DATA1_MARK,
-		VI5_DATA2_MARK, VI5_DATA3_MARK,
-		VI5_DATA4_MARK, VI5_DATA5_MARK,
-		VI5_DATA6_MARK, VI5_DATA7_MARK,
-		VI5_DATA8_MARK,  VI5_DATA9_MARK,
-		VI5_DATA10_MARK, VI5_DATA11_MARK,
-		VI5_DATA12_MARK, VI5_DATA13_MARK,
-		VI5_DATA14_MARK, VI5_DATA15_MARK,
-	},
-};
-static const unsigned int vin5_sync_pins[] = {
-	/* HSYNC#, VSYNC# */
-	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
-};
-static const unsigned int vin5_sync_mux[] = {
-	VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
-};
-static const unsigned int vin5_field_pins[] = {
-	RCAR_GP_PIN(1, 11),
-};
-static const unsigned int vin5_field_mux[] = {
-	/* FIELD */
-	VI5_FIELD_MARK,
-};
-static const unsigned int vin5_clkenb_pins[] = {
-	RCAR_GP_PIN(1, 20),
-};
-static const unsigned int vin5_clkenb_mux[] = {
-	/* CLKENB */
-	VI5_CLKENB_MARK,
-};
-static const unsigned int vin5_clk_pins[] = {
-	RCAR_GP_PIN(1, 21),
-};
-static const unsigned int vin5_clk_mux[] = {
-	/* CLK */
-	VI5_CLK_MARK,
-};
-
-static const struct {
-	struct sh_pfc_pin_group common[316];
-	struct sh_pfc_pin_group automotive[30];
-} pinmux_groups = {
-	.common = {
-		SH_PFC_PIN_GROUP(audio_clk_a_a),
-		SH_PFC_PIN_GROUP(audio_clk_a_b),
-		SH_PFC_PIN_GROUP(audio_clk_a_c),
-		SH_PFC_PIN_GROUP(audio_clk_b_a),
-		SH_PFC_PIN_GROUP(audio_clk_b_b),
-		SH_PFC_PIN_GROUP(audio_clk_c_a),
-		SH_PFC_PIN_GROUP(audio_clk_c_b),
-		SH_PFC_PIN_GROUP(audio_clkout_a),
-		SH_PFC_PIN_GROUP(audio_clkout_b),
-		SH_PFC_PIN_GROUP(audio_clkout_c),
-		SH_PFC_PIN_GROUP(audio_clkout_d),
-		SH_PFC_PIN_GROUP(audio_clkout1_a),
-		SH_PFC_PIN_GROUP(audio_clkout1_b),
-		SH_PFC_PIN_GROUP(audio_clkout2_a),
-		SH_PFC_PIN_GROUP(audio_clkout2_b),
-		SH_PFC_PIN_GROUP(audio_clkout3_a),
-		SH_PFC_PIN_GROUP(audio_clkout3_b),
-		SH_PFC_PIN_GROUP(avb_link),
-		SH_PFC_PIN_GROUP(avb_magic),
-		SH_PFC_PIN_GROUP(avb_phy_int),
-		SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
-		SH_PFC_PIN_GROUP(avb_mdio),
-		SH_PFC_PIN_GROUP(avb_mii),
-		SH_PFC_PIN_GROUP(avb_avtp_pps),
-		SH_PFC_PIN_GROUP(avb_avtp_match_a),
-		SH_PFC_PIN_GROUP(avb_avtp_capture_a),
-		SH_PFC_PIN_GROUP(avb_avtp_match_b),
-		SH_PFC_PIN_GROUP(avb_avtp_capture_b),
-		SH_PFC_PIN_GROUP(can0_data_a),
-		SH_PFC_PIN_GROUP(can0_data_b),
-		SH_PFC_PIN_GROUP(can1_data),
-		SH_PFC_PIN_GROUP(can_clk),
-		SH_PFC_PIN_GROUP(canfd0_data_a),
-		SH_PFC_PIN_GROUP(canfd0_data_b),
-		SH_PFC_PIN_GROUP(canfd1_data),
-		SH_PFC_PIN_GROUP(du_rgb666),
-		SH_PFC_PIN_GROUP(du_rgb888),
-		SH_PFC_PIN_GROUP(du_clk_out_0),
-		SH_PFC_PIN_GROUP(du_clk_out_1),
-		SH_PFC_PIN_GROUP(du_sync),
-		SH_PFC_PIN_GROUP(du_oddf),
-		SH_PFC_PIN_GROUP(du_cde),
-		SH_PFC_PIN_GROUP(du_disp),
-		SH_PFC_PIN_GROUP(hscif0_data),
-		SH_PFC_PIN_GROUP(hscif0_clk),
-		SH_PFC_PIN_GROUP(hscif0_ctrl),
-		SH_PFC_PIN_GROUP(hscif1_data_a),
-		SH_PFC_PIN_GROUP(hscif1_clk_a),
-		SH_PFC_PIN_GROUP(hscif1_ctrl_a),
-		SH_PFC_PIN_GROUP(hscif1_data_b),
-		SH_PFC_PIN_GROUP(hscif1_clk_b),
-		SH_PFC_PIN_GROUP(hscif1_ctrl_b),
-		SH_PFC_PIN_GROUP(hscif2_data_a),
-		SH_PFC_PIN_GROUP(hscif2_clk_a),
-		SH_PFC_PIN_GROUP(hscif2_ctrl_a),
-		SH_PFC_PIN_GROUP(hscif2_data_b),
-		SH_PFC_PIN_GROUP(hscif2_clk_b),
-		SH_PFC_PIN_GROUP(hscif2_ctrl_b),
-		SH_PFC_PIN_GROUP(hscif2_data_c),
-		SH_PFC_PIN_GROUP(hscif2_clk_c),
-		SH_PFC_PIN_GROUP(hscif2_ctrl_c),
-		SH_PFC_PIN_GROUP(hscif3_data_a),
-		SH_PFC_PIN_GROUP(hscif3_clk),
-		SH_PFC_PIN_GROUP(hscif3_ctrl),
-		SH_PFC_PIN_GROUP(hscif3_data_b),
-		SH_PFC_PIN_GROUP(hscif3_data_c),
-		SH_PFC_PIN_GROUP(hscif3_data_d),
-		SH_PFC_PIN_GROUP(hscif4_data_a),
-		SH_PFC_PIN_GROUP(hscif4_clk),
-		SH_PFC_PIN_GROUP(hscif4_ctrl),
-		SH_PFC_PIN_GROUP(hscif4_data_b),
-		SH_PFC_PIN_GROUP(i2c0),
-		SH_PFC_PIN_GROUP(i2c1_a),
-		SH_PFC_PIN_GROUP(i2c1_b),
-		SH_PFC_PIN_GROUP(i2c2_a),
-		SH_PFC_PIN_GROUP(i2c2_b),
-		SH_PFC_PIN_GROUP(i2c3),
-		SH_PFC_PIN_GROUP(i2c5),
-		SH_PFC_PIN_GROUP(i2c6_a),
-		SH_PFC_PIN_GROUP(i2c6_b),
-		SH_PFC_PIN_GROUP(i2c6_c),
-		SH_PFC_PIN_GROUP(intc_ex_irq0),
-		SH_PFC_PIN_GROUP(intc_ex_irq1),
-		SH_PFC_PIN_GROUP(intc_ex_irq2),
-		SH_PFC_PIN_GROUP(intc_ex_irq3),
-		SH_PFC_PIN_GROUP(intc_ex_irq4),
-		SH_PFC_PIN_GROUP(intc_ex_irq5),
-		SH_PFC_PIN_GROUP(msiof0_clk),
-		SH_PFC_PIN_GROUP(msiof0_sync),
-		SH_PFC_PIN_GROUP(msiof0_ss1),
-		SH_PFC_PIN_GROUP(msiof0_ss2),
-		SH_PFC_PIN_GROUP(msiof0_txd),
-		SH_PFC_PIN_GROUP(msiof0_rxd),
-		SH_PFC_PIN_GROUP(msiof1_clk_a),
-		SH_PFC_PIN_GROUP(msiof1_sync_a),
-		SH_PFC_PIN_GROUP(msiof1_ss1_a),
-		SH_PFC_PIN_GROUP(msiof1_ss2_a),
-		SH_PFC_PIN_GROUP(msiof1_txd_a),
-		SH_PFC_PIN_GROUP(msiof1_rxd_a),
-		SH_PFC_PIN_GROUP(msiof1_clk_b),
-		SH_PFC_PIN_GROUP(msiof1_sync_b),
-		SH_PFC_PIN_GROUP(msiof1_ss1_b),
-		SH_PFC_PIN_GROUP(msiof1_ss2_b),
-		SH_PFC_PIN_GROUP(msiof1_txd_b),
-		SH_PFC_PIN_GROUP(msiof1_rxd_b),
-		SH_PFC_PIN_GROUP(msiof1_clk_c),
-		SH_PFC_PIN_GROUP(msiof1_sync_c),
-		SH_PFC_PIN_GROUP(msiof1_ss1_c),
-		SH_PFC_PIN_GROUP(msiof1_ss2_c),
-		SH_PFC_PIN_GROUP(msiof1_txd_c),
-		SH_PFC_PIN_GROUP(msiof1_rxd_c),
-		SH_PFC_PIN_GROUP(msiof1_clk_d),
-		SH_PFC_PIN_GROUP(msiof1_sync_d),
-		SH_PFC_PIN_GROUP(msiof1_ss1_d),
-		SH_PFC_PIN_GROUP(msiof1_ss2_d),
-		SH_PFC_PIN_GROUP(msiof1_txd_d),
-		SH_PFC_PIN_GROUP(msiof1_rxd_d),
-		SH_PFC_PIN_GROUP(msiof1_clk_e),
-		SH_PFC_PIN_GROUP(msiof1_sync_e),
-		SH_PFC_PIN_GROUP(msiof1_ss1_e),
-		SH_PFC_PIN_GROUP(msiof1_ss2_e),
-		SH_PFC_PIN_GROUP(msiof1_txd_e),
-		SH_PFC_PIN_GROUP(msiof1_rxd_e),
-		SH_PFC_PIN_GROUP(msiof1_clk_f),
-		SH_PFC_PIN_GROUP(msiof1_sync_f),
-		SH_PFC_PIN_GROUP(msiof1_ss1_f),
-		SH_PFC_PIN_GROUP(msiof1_ss2_f),
-		SH_PFC_PIN_GROUP(msiof1_txd_f),
-		SH_PFC_PIN_GROUP(msiof1_rxd_f),
-		SH_PFC_PIN_GROUP(msiof1_clk_g),
-		SH_PFC_PIN_GROUP(msiof1_sync_g),
-		SH_PFC_PIN_GROUP(msiof1_ss1_g),
-		SH_PFC_PIN_GROUP(msiof1_ss2_g),
-		SH_PFC_PIN_GROUP(msiof1_txd_g),
-		SH_PFC_PIN_GROUP(msiof1_rxd_g),
-		SH_PFC_PIN_GROUP(msiof2_clk_a),
-		SH_PFC_PIN_GROUP(msiof2_sync_a),
-		SH_PFC_PIN_GROUP(msiof2_ss1_a),
-		SH_PFC_PIN_GROUP(msiof2_ss2_a),
-		SH_PFC_PIN_GROUP(msiof2_txd_a),
-		SH_PFC_PIN_GROUP(msiof2_rxd_a),
-		SH_PFC_PIN_GROUP(msiof2_clk_b),
-		SH_PFC_PIN_GROUP(msiof2_sync_b),
-		SH_PFC_PIN_GROUP(msiof2_ss1_b),
-		SH_PFC_PIN_GROUP(msiof2_ss2_b),
-		SH_PFC_PIN_GROUP(msiof2_txd_b),
-		SH_PFC_PIN_GROUP(msiof2_rxd_b),
-		SH_PFC_PIN_GROUP(msiof2_clk_c),
-		SH_PFC_PIN_GROUP(msiof2_sync_c),
-		SH_PFC_PIN_GROUP(msiof2_ss1_c),
-		SH_PFC_PIN_GROUP(msiof2_ss2_c),
-		SH_PFC_PIN_GROUP(msiof2_txd_c),
-		SH_PFC_PIN_GROUP(msiof2_rxd_c),
-		SH_PFC_PIN_GROUP(msiof2_clk_d),
-		SH_PFC_PIN_GROUP(msiof2_sync_d),
-		SH_PFC_PIN_GROUP(msiof2_ss1_d),
-		SH_PFC_PIN_GROUP(msiof2_ss2_d),
-		SH_PFC_PIN_GROUP(msiof2_txd_d),
-		SH_PFC_PIN_GROUP(msiof2_rxd_d),
-		SH_PFC_PIN_GROUP(msiof3_clk_a),
-		SH_PFC_PIN_GROUP(msiof3_sync_a),
-		SH_PFC_PIN_GROUP(msiof3_ss1_a),
-		SH_PFC_PIN_GROUP(msiof3_ss2_a),
-		SH_PFC_PIN_GROUP(msiof3_txd_a),
-		SH_PFC_PIN_GROUP(msiof3_rxd_a),
-		SH_PFC_PIN_GROUP(msiof3_clk_b),
-		SH_PFC_PIN_GROUP(msiof3_sync_b),
-		SH_PFC_PIN_GROUP(msiof3_ss1_b),
-		SH_PFC_PIN_GROUP(msiof3_ss2_b),
-		SH_PFC_PIN_GROUP(msiof3_txd_b),
-		SH_PFC_PIN_GROUP(msiof3_rxd_b),
-		SH_PFC_PIN_GROUP(msiof3_clk_c),
-		SH_PFC_PIN_GROUP(msiof3_sync_c),
-		SH_PFC_PIN_GROUP(msiof3_txd_c),
-		SH_PFC_PIN_GROUP(msiof3_rxd_c),
-		SH_PFC_PIN_GROUP(msiof3_clk_d),
-		SH_PFC_PIN_GROUP(msiof3_sync_d),
-		SH_PFC_PIN_GROUP(msiof3_ss1_d),
-		SH_PFC_PIN_GROUP(msiof3_txd_d),
-		SH_PFC_PIN_GROUP(msiof3_rxd_d),
-		SH_PFC_PIN_GROUP(msiof3_clk_e),
-		SH_PFC_PIN_GROUP(msiof3_sync_e),
-		SH_PFC_PIN_GROUP(msiof3_ss1_e),
-		SH_PFC_PIN_GROUP(msiof3_ss2_e),
-		SH_PFC_PIN_GROUP(msiof3_txd_e),
-		SH_PFC_PIN_GROUP(msiof3_rxd_e),
-		SH_PFC_PIN_GROUP(pwm0),
-		SH_PFC_PIN_GROUP(pwm1_a),
-		SH_PFC_PIN_GROUP(pwm1_b),
-		SH_PFC_PIN_GROUP(pwm2_a),
-		SH_PFC_PIN_GROUP(pwm2_b),
-		SH_PFC_PIN_GROUP(pwm3_a),
-		SH_PFC_PIN_GROUP(pwm3_b),
-		SH_PFC_PIN_GROUP(pwm4_a),
-		SH_PFC_PIN_GROUP(pwm4_b),
-		SH_PFC_PIN_GROUP(pwm5_a),
-		SH_PFC_PIN_GROUP(pwm5_b),
-		SH_PFC_PIN_GROUP(pwm6_a),
-		SH_PFC_PIN_GROUP(pwm6_b),
-		SH_PFC_PIN_GROUP(scif0_data),
-		SH_PFC_PIN_GROUP(scif0_clk),
-		SH_PFC_PIN_GROUP(scif0_ctrl),
-		SH_PFC_PIN_GROUP(scif1_data_a),
-		SH_PFC_PIN_GROUP(scif1_clk),
-		SH_PFC_PIN_GROUP(scif1_ctrl),
-		SH_PFC_PIN_GROUP(scif1_data_b),
-		SH_PFC_PIN_GROUP(scif2_data_a),
-		SH_PFC_PIN_GROUP(scif2_clk),
-		SH_PFC_PIN_GROUP(scif2_data_b),
-		SH_PFC_PIN_GROUP(scif3_data_a),
-		SH_PFC_PIN_GROUP(scif3_clk),
-		SH_PFC_PIN_GROUP(scif3_ctrl),
-		SH_PFC_PIN_GROUP(scif3_data_b),
-		SH_PFC_PIN_GROUP(scif4_data_a),
-		SH_PFC_PIN_GROUP(scif4_clk_a),
-		SH_PFC_PIN_GROUP(scif4_ctrl_a),
-		SH_PFC_PIN_GROUP(scif4_data_b),
-		SH_PFC_PIN_GROUP(scif4_clk_b),
-		SH_PFC_PIN_GROUP(scif4_ctrl_b),
-		SH_PFC_PIN_GROUP(scif4_data_c),
-		SH_PFC_PIN_GROUP(scif4_clk_c),
-		SH_PFC_PIN_GROUP(scif4_ctrl_c),
-		SH_PFC_PIN_GROUP(scif5_data_a),
-		SH_PFC_PIN_GROUP(scif5_clk_a),
-		SH_PFC_PIN_GROUP(scif5_data_b),
-		SH_PFC_PIN_GROUP(scif5_clk_b),
-		SH_PFC_PIN_GROUP(scif_clk_a),
-		SH_PFC_PIN_GROUP(scif_clk_b),
-		SH_PFC_PIN_GROUP(sdhi0_data1),
-		SH_PFC_PIN_GROUP(sdhi0_data4),
-		SH_PFC_PIN_GROUP(sdhi0_ctrl),
-		SH_PFC_PIN_GROUP(sdhi0_cd),
-		SH_PFC_PIN_GROUP(sdhi0_wp),
-		SH_PFC_PIN_GROUP(sdhi1_data1),
-		SH_PFC_PIN_GROUP(sdhi1_data4),
-		SH_PFC_PIN_GROUP(sdhi1_ctrl),
-		SH_PFC_PIN_GROUP(sdhi1_cd),
-		SH_PFC_PIN_GROUP(sdhi1_wp),
-		SH_PFC_PIN_GROUP(sdhi2_data1),
-		SH_PFC_PIN_GROUP(sdhi2_data4),
-		SH_PFC_PIN_GROUP(sdhi2_data8),
-		SH_PFC_PIN_GROUP(sdhi2_ctrl),
-		SH_PFC_PIN_GROUP(sdhi2_cd_a),
-		SH_PFC_PIN_GROUP(sdhi2_wp_a),
-		SH_PFC_PIN_GROUP(sdhi2_cd_b),
-		SH_PFC_PIN_GROUP(sdhi2_wp_b),
-		SH_PFC_PIN_GROUP(sdhi2_ds),
-		SH_PFC_PIN_GROUP(sdhi3_data1),
-		SH_PFC_PIN_GROUP(sdhi3_data4),
-		SH_PFC_PIN_GROUP(sdhi3_data8),
-		SH_PFC_PIN_GROUP(sdhi3_ctrl),
-		SH_PFC_PIN_GROUP(sdhi3_cd),
-		SH_PFC_PIN_GROUP(sdhi3_wp),
-		SH_PFC_PIN_GROUP(sdhi3_ds),
-		SH_PFC_PIN_GROUP(ssi0_data),
-		SH_PFC_PIN_GROUP(ssi01239_ctrl),
-		SH_PFC_PIN_GROUP(ssi1_data_a),
-		SH_PFC_PIN_GROUP(ssi1_data_b),
-		SH_PFC_PIN_GROUP(ssi1_ctrl_a),
-		SH_PFC_PIN_GROUP(ssi1_ctrl_b),
-		SH_PFC_PIN_GROUP(ssi2_data_a),
-		SH_PFC_PIN_GROUP(ssi2_data_b),
-		SH_PFC_PIN_GROUP(ssi2_ctrl_a),
-		SH_PFC_PIN_GROUP(ssi2_ctrl_b),
-		SH_PFC_PIN_GROUP(ssi3_data),
-		SH_PFC_PIN_GROUP(ssi349_ctrl),
-		SH_PFC_PIN_GROUP(ssi4_data),
-		SH_PFC_PIN_GROUP(ssi4_ctrl),
-		SH_PFC_PIN_GROUP(ssi5_data),
-		SH_PFC_PIN_GROUP(ssi5_ctrl),
-		SH_PFC_PIN_GROUP(ssi6_data),
-		SH_PFC_PIN_GROUP(ssi6_ctrl),
-		SH_PFC_PIN_GROUP(ssi7_data),
-		SH_PFC_PIN_GROUP(ssi78_ctrl),
-		SH_PFC_PIN_GROUP(ssi8_data),
-		SH_PFC_PIN_GROUP(ssi9_data_a),
-		SH_PFC_PIN_GROUP(ssi9_data_b),
-		SH_PFC_PIN_GROUP(ssi9_ctrl_a),
-		SH_PFC_PIN_GROUP(ssi9_ctrl_b),
-		SH_PFC_PIN_GROUP(tmu_tclk1_a),
-		SH_PFC_PIN_GROUP(tmu_tclk1_b),
-		SH_PFC_PIN_GROUP(tmu_tclk2_a),
-		SH_PFC_PIN_GROUP(tmu_tclk2_b),
-		SH_PFC_PIN_GROUP(tpu_to0),
-		SH_PFC_PIN_GROUP(tpu_to1),
-		SH_PFC_PIN_GROUP(tpu_to2),
-		SH_PFC_PIN_GROUP(tpu_to3),
-		SH_PFC_PIN_GROUP(usb0),
-		SH_PFC_PIN_GROUP(usb1),
-		SH_PFC_PIN_GROUP(usb30),
-		VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
-		SH_PFC_PIN_GROUP(vin4_data18_a),
-		VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
-		SH_PFC_PIN_GROUP(vin4_data18_b),
-		VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
-		SH_PFC_PIN_GROUP(vin4_sync),
-		SH_PFC_PIN_GROUP(vin4_field),
-		SH_PFC_PIN_GROUP(vin4_clkenb),
-		SH_PFC_PIN_GROUP(vin4_clk),
-		VIN_DATA_PIN_GROUP(vin5_data, 8),
-		VIN_DATA_PIN_GROUP(vin5_data, 10),
-		VIN_DATA_PIN_GROUP(vin5_data, 12),
-		VIN_DATA_PIN_GROUP(vin5_data, 16),
-		SH_PFC_PIN_GROUP(vin5_sync),
-		SH_PFC_PIN_GROUP(vin5_field),
-		SH_PFC_PIN_GROUP(vin5_clkenb),
-		SH_PFC_PIN_GROUP(vin5_clk),
-	},
-	.automotive = {
-		SH_PFC_PIN_GROUP(drif0_ctrl_a),
-		SH_PFC_PIN_GROUP(drif0_data0_a),
-		SH_PFC_PIN_GROUP(drif0_data1_a),
-		SH_PFC_PIN_GROUP(drif0_ctrl_b),
-		SH_PFC_PIN_GROUP(drif0_data0_b),
-		SH_PFC_PIN_GROUP(drif0_data1_b),
-		SH_PFC_PIN_GROUP(drif0_ctrl_c),
-		SH_PFC_PIN_GROUP(drif0_data0_c),
-		SH_PFC_PIN_GROUP(drif0_data1_c),
-		SH_PFC_PIN_GROUP(drif1_ctrl_a),
-		SH_PFC_PIN_GROUP(drif1_data0_a),
-		SH_PFC_PIN_GROUP(drif1_data1_a),
-		SH_PFC_PIN_GROUP(drif1_ctrl_b),
-		SH_PFC_PIN_GROUP(drif1_data0_b),
-		SH_PFC_PIN_GROUP(drif1_data1_b),
-		SH_PFC_PIN_GROUP(drif1_ctrl_c),
-		SH_PFC_PIN_GROUP(drif1_data0_c),
-		SH_PFC_PIN_GROUP(drif1_data1_c),
-		SH_PFC_PIN_GROUP(drif2_ctrl_a),
-		SH_PFC_PIN_GROUP(drif2_data0_a),
-		SH_PFC_PIN_GROUP(drif2_data1_a),
-		SH_PFC_PIN_GROUP(drif2_ctrl_b),
-		SH_PFC_PIN_GROUP(drif2_data0_b),
-		SH_PFC_PIN_GROUP(drif2_data1_b),
-		SH_PFC_PIN_GROUP(drif3_ctrl_a),
-		SH_PFC_PIN_GROUP(drif3_data0_a),
-		SH_PFC_PIN_GROUP(drif3_data1_a),
-		SH_PFC_PIN_GROUP(drif3_ctrl_b),
-		SH_PFC_PIN_GROUP(drif3_data0_b),
-		SH_PFC_PIN_GROUP(drif3_data1_b),
-	}
-};
-
-static const char * const audio_clk_groups[] = {
-	"audio_clk_a_a",
-	"audio_clk_a_b",
-	"audio_clk_a_c",
-	"audio_clk_b_a",
-	"audio_clk_b_b",
-	"audio_clk_c_a",
-	"audio_clk_c_b",
-	"audio_clkout_a",
-	"audio_clkout_b",
-	"audio_clkout_c",
-	"audio_clkout_d",
-	"audio_clkout1_a",
-	"audio_clkout1_b",
-	"audio_clkout2_a",
-	"audio_clkout2_b",
-	"audio_clkout3_a",
-	"audio_clkout3_b",
-};
-
-static const char * const avb_groups[] = {
-	"avb_link",
-	"avb_magic",
-	"avb_phy_int",
-	"avb_mdc",	/* Deprecated, please use "avb_mdio" instead */
-	"avb_mdio",
-	"avb_mii",
-	"avb_avtp_pps",
-	"avb_avtp_match_a",
-	"avb_avtp_capture_a",
-	"avb_avtp_match_b",
-	"avb_avtp_capture_b",
-};
-
-static const char * const can0_groups[] = {
-	"can0_data_a",
-	"can0_data_b",
-};
-
-static const char * const can1_groups[] = {
-	"can1_data",
-};
-
-static const char * const can_clk_groups[] = {
-	"can_clk",
-};
-
-static const char * const canfd0_groups[] = {
-	"canfd0_data_a",
-	"canfd0_data_b",
-};
-
-static const char * const canfd1_groups[] = {
-	"canfd1_data",
-};
-
-static const char * const drif0_groups[] = {
-	"drif0_ctrl_a",
-	"drif0_data0_a",
-	"drif0_data1_a",
-	"drif0_ctrl_b",
-	"drif0_data0_b",
-	"drif0_data1_b",
-	"drif0_ctrl_c",
-	"drif0_data0_c",
-	"drif0_data1_c",
-};
-
-static const char * const drif1_groups[] = {
-	"drif1_ctrl_a",
-	"drif1_data0_a",
-	"drif1_data1_a",
-	"drif1_ctrl_b",
-	"drif1_data0_b",
-	"drif1_data1_b",
-	"drif1_ctrl_c",
-	"drif1_data0_c",
-	"drif1_data1_c",
-};
-
-static const char * const drif2_groups[] = {
-	"drif2_ctrl_a",
-	"drif2_data0_a",
-	"drif2_data1_a",
-	"drif2_ctrl_b",
-	"drif2_data0_b",
-	"drif2_data1_b",
-};
-
-static const char * const drif3_groups[] = {
-	"drif3_ctrl_a",
-	"drif3_data0_a",
-	"drif3_data1_a",
-	"drif3_ctrl_b",
-	"drif3_data0_b",
-	"drif3_data1_b",
-};
-
-static const char * const du_groups[] = {
-	"du_rgb666",
-	"du_rgb888",
-	"du_clk_out_0",
-	"du_clk_out_1",
-	"du_sync",
-	"du_oddf",
-	"du_cde",
-	"du_disp",
-};
-
-static const char * const hscif0_groups[] = {
-	"hscif0_data",
-	"hscif0_clk",
-	"hscif0_ctrl",
-};
-
-static const char * const hscif1_groups[] = {
-	"hscif1_data_a",
-	"hscif1_clk_a",
-	"hscif1_ctrl_a",
-	"hscif1_data_b",
-	"hscif1_clk_b",
-	"hscif1_ctrl_b",
-};
-
-static const char * const hscif2_groups[] = {
-	"hscif2_data_a",
-	"hscif2_clk_a",
-	"hscif2_ctrl_a",
-	"hscif2_data_b",
-	"hscif2_clk_b",
-	"hscif2_ctrl_b",
-	"hscif2_data_c",
-	"hscif2_clk_c",
-	"hscif2_ctrl_c",
-};
-
-static const char * const hscif3_groups[] = {
-	"hscif3_data_a",
-	"hscif3_clk",
-	"hscif3_ctrl",
-	"hscif3_data_b",
-	"hscif3_data_c",
-	"hscif3_data_d",
-};
-
-static const char * const hscif4_groups[] = {
-	"hscif4_data_a",
-	"hscif4_clk",
-	"hscif4_ctrl",
-	"hscif4_data_b",
-};
-
-static const char * const i2c0_groups[] = {
-	"i2c0",
-};
-
-static const char * const i2c1_groups[] = {
-	"i2c1_a",
-	"i2c1_b",
-};
-
-static const char * const i2c2_groups[] = {
-	"i2c2_a",
-	"i2c2_b",
-};
-
-static const char * const i2c3_groups[] = {
-	"i2c3",
-};
-
-static const char * const i2c5_groups[] = {
-	"i2c5",
-};
-
-static const char * const i2c6_groups[] = {
-	"i2c6_a",
-	"i2c6_b",
-	"i2c6_c",
-};
-
-static const char * const intc_ex_groups[] = {
-	"intc_ex_irq0",
-	"intc_ex_irq1",
-	"intc_ex_irq2",
-	"intc_ex_irq3",
-	"intc_ex_irq4",
-	"intc_ex_irq5",
-};
-
-static const char * const msiof0_groups[] = {
-	"msiof0_clk",
-	"msiof0_sync",
-	"msiof0_ss1",
-	"msiof0_ss2",
-	"msiof0_txd",
-	"msiof0_rxd",
-};
-
-static const char * const msiof1_groups[] = {
-	"msiof1_clk_a",
-	"msiof1_sync_a",
-	"msiof1_ss1_a",
-	"msiof1_ss2_a",
-	"msiof1_txd_a",
-	"msiof1_rxd_a",
-	"msiof1_clk_b",
-	"msiof1_sync_b",
-	"msiof1_ss1_b",
-	"msiof1_ss2_b",
-	"msiof1_txd_b",
-	"msiof1_rxd_b",
-	"msiof1_clk_c",
-	"msiof1_sync_c",
-	"msiof1_ss1_c",
-	"msiof1_ss2_c",
-	"msiof1_txd_c",
-	"msiof1_rxd_c",
-	"msiof1_clk_d",
-	"msiof1_sync_d",
-	"msiof1_ss1_d",
-	"msiof1_ss2_d",
-	"msiof1_txd_d",
-	"msiof1_rxd_d",
-	"msiof1_clk_e",
-	"msiof1_sync_e",
-	"msiof1_ss1_e",
-	"msiof1_ss2_e",
-	"msiof1_txd_e",
-	"msiof1_rxd_e",
-	"msiof1_clk_f",
-	"msiof1_sync_f",
-	"msiof1_ss1_f",
-	"msiof1_ss2_f",
-	"msiof1_txd_f",
-	"msiof1_rxd_f",
-	"msiof1_clk_g",
-	"msiof1_sync_g",
-	"msiof1_ss1_g",
-	"msiof1_ss2_g",
-	"msiof1_txd_g",
-	"msiof1_rxd_g",
-};
-
-static const char * const msiof2_groups[] = {
-	"msiof2_clk_a",
-	"msiof2_sync_a",
-	"msiof2_ss1_a",
-	"msiof2_ss2_a",
-	"msiof2_txd_a",
-	"msiof2_rxd_a",
-	"msiof2_clk_b",
-	"msiof2_sync_b",
-	"msiof2_ss1_b",
-	"msiof2_ss2_b",
-	"msiof2_txd_b",
-	"msiof2_rxd_b",
-	"msiof2_clk_c",
-	"msiof2_sync_c",
-	"msiof2_ss1_c",
-	"msiof2_ss2_c",
-	"msiof2_txd_c",
-	"msiof2_rxd_c",
-	"msiof2_clk_d",
-	"msiof2_sync_d",
-	"msiof2_ss1_d",
-	"msiof2_ss2_d",
-	"msiof2_txd_d",
-	"msiof2_rxd_d",
-};
-
-static const char * const msiof3_groups[] = {
-	"msiof3_clk_a",
-	"msiof3_sync_a",
-	"msiof3_ss1_a",
-	"msiof3_ss2_a",
-	"msiof3_txd_a",
-	"msiof3_rxd_a",
-	"msiof3_clk_b",
-	"msiof3_sync_b",
-	"msiof3_ss1_b",
-	"msiof3_ss2_b",
-	"msiof3_txd_b",
-	"msiof3_rxd_b",
-	"msiof3_clk_c",
-	"msiof3_sync_c",
-	"msiof3_txd_c",
-	"msiof3_rxd_c",
-	"msiof3_clk_d",
-	"msiof3_sync_d",
-	"msiof3_ss1_d",
-	"msiof3_txd_d",
-	"msiof3_rxd_d",
-	"msiof3_clk_e",
-	"msiof3_sync_e",
-	"msiof3_ss1_e",
-	"msiof3_ss2_e",
-	"msiof3_txd_e",
-	"msiof3_rxd_e",
-};
-
-static const char * const pwm0_groups[] = {
-	"pwm0",
-};
-
-static const char * const pwm1_groups[] = {
-	"pwm1_a",
-	"pwm1_b",
-};
-
-static const char * const pwm2_groups[] = {
-	"pwm2_a",
-	"pwm2_b",
-};
-
-static const char * const pwm3_groups[] = {
-	"pwm3_a",
-	"pwm3_b",
-};
-
-static const char * const pwm4_groups[] = {
-	"pwm4_a",
-	"pwm4_b",
-};
-
-static const char * const pwm5_groups[] = {
-	"pwm5_a",
-	"pwm5_b",
-};
-
-static const char * const pwm6_groups[] = {
-	"pwm6_a",
-	"pwm6_b",
-};
-
-static const char * const scif0_groups[] = {
-	"scif0_data",
-	"scif0_clk",
-	"scif0_ctrl",
-};
-
-static const char * const scif1_groups[] = {
-	"scif1_data_a",
-	"scif1_clk",
-	"scif1_ctrl",
-	"scif1_data_b",
-};
-
-static const char * const scif2_groups[] = {
-	"scif2_data_a",
-	"scif2_clk",
-	"scif2_data_b",
-};
-
-static const char * const scif3_groups[] = {
-	"scif3_data_a",
-	"scif3_clk",
-	"scif3_ctrl",
-	"scif3_data_b",
-};
-
-static const char * const scif4_groups[] = {
-	"scif4_data_a",
-	"scif4_clk_a",
-	"scif4_ctrl_a",
-	"scif4_data_b",
-	"scif4_clk_b",
-	"scif4_ctrl_b",
-	"scif4_data_c",
-	"scif4_clk_c",
-	"scif4_ctrl_c",
-};
-
-static const char * const scif5_groups[] = {
-	"scif5_data_a",
-	"scif5_clk_a",
-	"scif5_data_b",
-	"scif5_clk_b",
-};
-
-static const char * const scif_clk_groups[] = {
-	"scif_clk_a",
-	"scif_clk_b",
-};
-
-static const char * const sdhi0_groups[] = {
-	"sdhi0_data1",
-	"sdhi0_data4",
-	"sdhi0_ctrl",
-	"sdhi0_cd",
-	"sdhi0_wp",
-};
-
-static const char * const sdhi1_groups[] = {
-	"sdhi1_data1",
-	"sdhi1_data4",
-	"sdhi1_ctrl",
-	"sdhi1_cd",
-	"sdhi1_wp",
-};
-
-static const char * const sdhi2_groups[] = {
-	"sdhi2_data1",
-	"sdhi2_data4",
-	"sdhi2_data8",
-	"sdhi2_ctrl",
-	"sdhi2_cd_a",
-	"sdhi2_wp_a",
-	"sdhi2_cd_b",
-	"sdhi2_wp_b",
-	"sdhi2_ds",
-};
-
-static const char * const sdhi3_groups[] = {
-	"sdhi3_data1",
-	"sdhi3_data4",
-	"sdhi3_data8",
-	"sdhi3_ctrl",
-	"sdhi3_cd",
-	"sdhi3_wp",
-	"sdhi3_ds",
-};
-
-static const char * const ssi_groups[] = {
-	"ssi0_data",
-	"ssi01239_ctrl",
-	"ssi1_data_a",
-	"ssi1_data_b",
-	"ssi1_ctrl_a",
-	"ssi1_ctrl_b",
-	"ssi2_data_a",
-	"ssi2_data_b",
-	"ssi2_ctrl_a",
-	"ssi2_ctrl_b",
-	"ssi3_data",
-	"ssi349_ctrl",
-	"ssi4_data",
-	"ssi4_ctrl",
-	"ssi5_data",
-	"ssi5_ctrl",
-	"ssi6_data",
-	"ssi6_ctrl",
-	"ssi7_data",
-	"ssi78_ctrl",
-	"ssi8_data",
-	"ssi9_data_a",
-	"ssi9_data_b",
-	"ssi9_ctrl_a",
-	"ssi9_ctrl_b",
-};
-
-static const char * const tmu_groups[] = {
-	"tmu_tclk1_a",
-	"tmu_tclk1_b",
-	"tmu_tclk2_a",
-	"tmu_tclk2_b",
-};
-
-static const char * const tpu_groups[] = {
-	"tpu_to0",
-	"tpu_to1",
-	"tpu_to2",
-	"tpu_to3",
-};
-
-static const char * const usb0_groups[] = {
-	"usb0",
-};
-
-static const char * const usb1_groups[] = {
-	"usb1",
-};
-
-static const char * const usb30_groups[] = {
-	"usb30",
-};
-
-static const char * const vin4_groups[] = {
-	"vin4_data8_a",
-	"vin4_data10_a",
-	"vin4_data12_a",
-	"vin4_data16_a",
-	"vin4_data18_a",
-	"vin4_data20_a",
-	"vin4_data24_a",
-	"vin4_data8_b",
-	"vin4_data10_b",
-	"vin4_data12_b",
-	"vin4_data16_b",
-	"vin4_data18_b",
-	"vin4_data20_b",
-	"vin4_data24_b",
-	"vin4_sync",
-	"vin4_field",
-	"vin4_clkenb",
-	"vin4_clk",
-};
-
-static const char * const vin5_groups[] = {
-	"vin5_data8",
-	"vin5_data10",
-	"vin5_data12",
-	"vin5_data16",
-	"vin5_sync",
-	"vin5_field",
-	"vin5_clkenb",
-	"vin5_clk",
-};
-
-static const struct {
-	struct sh_pfc_function common[50];
-	struct sh_pfc_function automotive[4];
-} pinmux_functions = {
-	.common = {
-		SH_PFC_FUNCTION(audio_clk),
-		SH_PFC_FUNCTION(avb),
-		SH_PFC_FUNCTION(can0),
-		SH_PFC_FUNCTION(can1),
-		SH_PFC_FUNCTION(can_clk),
-		SH_PFC_FUNCTION(canfd0),
-		SH_PFC_FUNCTION(canfd1),
-		SH_PFC_FUNCTION(du),
-		SH_PFC_FUNCTION(hscif0),
-		SH_PFC_FUNCTION(hscif1),
-		SH_PFC_FUNCTION(hscif2),
-		SH_PFC_FUNCTION(hscif3),
-		SH_PFC_FUNCTION(hscif4),
-		SH_PFC_FUNCTION(i2c0),
-		SH_PFC_FUNCTION(i2c1),
-		SH_PFC_FUNCTION(i2c2),
-		SH_PFC_FUNCTION(i2c3),
-		SH_PFC_FUNCTION(i2c5),
-		SH_PFC_FUNCTION(i2c6),
-		SH_PFC_FUNCTION(intc_ex),
-		SH_PFC_FUNCTION(msiof0),
-		SH_PFC_FUNCTION(msiof1),
-		SH_PFC_FUNCTION(msiof2),
-		SH_PFC_FUNCTION(msiof3),
-		SH_PFC_FUNCTION(pwm0),
-		SH_PFC_FUNCTION(pwm1),
-		SH_PFC_FUNCTION(pwm2),
-		SH_PFC_FUNCTION(pwm3),
-		SH_PFC_FUNCTION(pwm4),
-		SH_PFC_FUNCTION(pwm5),
-		SH_PFC_FUNCTION(pwm6),
-		SH_PFC_FUNCTION(scif0),
-		SH_PFC_FUNCTION(scif1),
-		SH_PFC_FUNCTION(scif2),
-		SH_PFC_FUNCTION(scif3),
-		SH_PFC_FUNCTION(scif4),
-		SH_PFC_FUNCTION(scif5),
-		SH_PFC_FUNCTION(scif_clk),
-		SH_PFC_FUNCTION(sdhi0),
-		SH_PFC_FUNCTION(sdhi1),
-		SH_PFC_FUNCTION(sdhi2),
-		SH_PFC_FUNCTION(sdhi3),
-		SH_PFC_FUNCTION(ssi),
-		SH_PFC_FUNCTION(tmu),
-		SH_PFC_FUNCTION(tpu),
-		SH_PFC_FUNCTION(usb0),
-		SH_PFC_FUNCTION(usb1),
-		SH_PFC_FUNCTION(usb30),
-		SH_PFC_FUNCTION(vin4),
-		SH_PFC_FUNCTION(vin5),
-	},
-	.automotive = {
-		SH_PFC_FUNCTION(drif0),
-		SH_PFC_FUNCTION(drif1),
-		SH_PFC_FUNCTION(drif2),
-		SH_PFC_FUNCTION(drif3),
-	}
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-#define F_(x, y)	FN_##y
-#define FM(x)		FN_##x
-	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_0_15_FN,	GPSR0_15,
-		GP_0_14_FN,	GPSR0_14,
-		GP_0_13_FN,	GPSR0_13,
-		GP_0_12_FN,	GPSR0_12,
-		GP_0_11_FN,	GPSR0_11,
-		GP_0_10_FN,	GPSR0_10,
-		GP_0_9_FN,	GPSR0_9,
-		GP_0_8_FN,	GPSR0_8,
-		GP_0_7_FN,	GPSR0_7,
-		GP_0_6_FN,	GPSR0_6,
-		GP_0_5_FN,	GPSR0_5,
-		GP_0_4_FN,	GPSR0_4,
-		GP_0_3_FN,	GPSR0_3,
-		GP_0_2_FN,	GPSR0_2,
-		GP_0_1_FN,	GPSR0_1,
-		GP_0_0_FN,	GPSR0_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_1_28_FN,	GPSR1_28,
-		GP_1_27_FN,	GPSR1_27,
-		GP_1_26_FN,	GPSR1_26,
-		GP_1_25_FN,	GPSR1_25,
-		GP_1_24_FN,	GPSR1_24,
-		GP_1_23_FN,	GPSR1_23,
-		GP_1_22_FN,	GPSR1_22,
-		GP_1_21_FN,	GPSR1_21,
-		GP_1_20_FN,	GPSR1_20,
-		GP_1_19_FN,	GPSR1_19,
-		GP_1_18_FN,	GPSR1_18,
-		GP_1_17_FN,	GPSR1_17,
-		GP_1_16_FN,	GPSR1_16,
-		GP_1_15_FN,	GPSR1_15,
-		GP_1_14_FN,	GPSR1_14,
-		GP_1_13_FN,	GPSR1_13,
-		GP_1_12_FN,	GPSR1_12,
-		GP_1_11_FN,	GPSR1_11,
-		GP_1_10_FN,	GPSR1_10,
-		GP_1_9_FN,	GPSR1_9,
-		GP_1_8_FN,	GPSR1_8,
-		GP_1_7_FN,	GPSR1_7,
-		GP_1_6_FN,	GPSR1_6,
-		GP_1_5_FN,	GPSR1_5,
-		GP_1_4_FN,	GPSR1_4,
-		GP_1_3_FN,	GPSR1_3,
-		GP_1_2_FN,	GPSR1_2,
-		GP_1_1_FN,	GPSR1_1,
-		GP_1_0_FN,	GPSR1_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_2_14_FN,	GPSR2_14,
-		GP_2_13_FN,	GPSR2_13,
-		GP_2_12_FN,	GPSR2_12,
-		GP_2_11_FN,	GPSR2_11,
-		GP_2_10_FN,	GPSR2_10,
-		GP_2_9_FN,	GPSR2_9,
-		GP_2_8_FN,	GPSR2_8,
-		GP_2_7_FN,	GPSR2_7,
-		GP_2_6_FN,	GPSR2_6,
-		GP_2_5_FN,	GPSR2_5,
-		GP_2_4_FN,	GPSR2_4,
-		GP_2_3_FN,	GPSR2_3,
-		GP_2_2_FN,	GPSR2_2,
-		GP_2_1_FN,	GPSR2_1,
-		GP_2_0_FN,	GPSR2_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_3_15_FN,	GPSR3_15,
-		GP_3_14_FN,	GPSR3_14,
-		GP_3_13_FN,	GPSR3_13,
-		GP_3_12_FN,	GPSR3_12,
-		GP_3_11_FN,	GPSR3_11,
-		GP_3_10_FN,	GPSR3_10,
-		GP_3_9_FN,	GPSR3_9,
-		GP_3_8_FN,	GPSR3_8,
-		GP_3_7_FN,	GPSR3_7,
-		GP_3_6_FN,	GPSR3_6,
-		GP_3_5_FN,	GPSR3_5,
-		GP_3_4_FN,	GPSR3_4,
-		GP_3_3_FN,	GPSR3_3,
-		GP_3_2_FN,	GPSR3_2,
-		GP_3_1_FN,	GPSR3_1,
-		GP_3_0_FN,	GPSR3_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_4_17_FN,	GPSR4_17,
-		GP_4_16_FN,	GPSR4_16,
-		GP_4_15_FN,	GPSR4_15,
-		GP_4_14_FN,	GPSR4_14,
-		GP_4_13_FN,	GPSR4_13,
-		GP_4_12_FN,	GPSR4_12,
-		GP_4_11_FN,	GPSR4_11,
-		GP_4_10_FN,	GPSR4_10,
-		GP_4_9_FN,	GPSR4_9,
-		GP_4_8_FN,	GPSR4_8,
-		GP_4_7_FN,	GPSR4_7,
-		GP_4_6_FN,	GPSR4_6,
-		GP_4_5_FN,	GPSR4_5,
-		GP_4_4_FN,	GPSR4_4,
-		GP_4_3_FN,	GPSR4_3,
-		GP_4_2_FN,	GPSR4_2,
-		GP_4_1_FN,	GPSR4_1,
-		GP_4_0_FN,	GPSR4_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_5_25_FN,	GPSR5_25,
-		GP_5_24_FN,	GPSR5_24,
-		GP_5_23_FN,	GPSR5_23,
-		GP_5_22_FN,	GPSR5_22,
-		GP_5_21_FN,	GPSR5_21,
-		GP_5_20_FN,	GPSR5_20,
-		GP_5_19_FN,	GPSR5_19,
-		GP_5_18_FN,	GPSR5_18,
-		GP_5_17_FN,	GPSR5_17,
-		GP_5_16_FN,	GPSR5_16,
-		GP_5_15_FN,	GPSR5_15,
-		GP_5_14_FN,	GPSR5_14,
-		GP_5_13_FN,	GPSR5_13,
-		GP_5_12_FN,	GPSR5_12,
-		GP_5_11_FN,	GPSR5_11,
-		GP_5_10_FN,	GPSR5_10,
-		GP_5_9_FN,	GPSR5_9,
-		GP_5_8_FN,	GPSR5_8,
-		GP_5_7_FN,	GPSR5_7,
-		GP_5_6_FN,	GPSR5_6,
-		GP_5_5_FN,	GPSR5_5,
-		GP_5_4_FN,	GPSR5_4,
-		GP_5_3_FN,	GPSR5_3,
-		GP_5_2_FN,	GPSR5_2,
-		GP_5_1_FN,	GPSR5_1,
-		GP_5_0_FN,	GPSR5_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
-		GP_6_31_FN,	GPSR6_31,
-		GP_6_30_FN,	GPSR6_30,
-		GP_6_29_FN,	GPSR6_29,
-		GP_6_28_FN,	GPSR6_28,
-		GP_6_27_FN,	GPSR6_27,
-		GP_6_26_FN,	GPSR6_26,
-		GP_6_25_FN,	GPSR6_25,
-		GP_6_24_FN,	GPSR6_24,
-		GP_6_23_FN,	GPSR6_23,
-		GP_6_22_FN,	GPSR6_22,
-		GP_6_21_FN,	GPSR6_21,
-		GP_6_20_FN,	GPSR6_20,
-		GP_6_19_FN,	GPSR6_19,
-		GP_6_18_FN,	GPSR6_18,
-		GP_6_17_FN,	GPSR6_17,
-		GP_6_16_FN,	GPSR6_16,
-		GP_6_15_FN,	GPSR6_15,
-		GP_6_14_FN,	GPSR6_14,
-		GP_6_13_FN,	GPSR6_13,
-		GP_6_12_FN,	GPSR6_12,
-		GP_6_11_FN,	GPSR6_11,
-		GP_6_10_FN,	GPSR6_10,
-		GP_6_9_FN,	GPSR6_9,
-		GP_6_8_FN,	GPSR6_8,
-		GP_6_7_FN,	GPSR6_7,
-		GP_6_6_FN,	GPSR6_6,
-		GP_6_5_FN,	GPSR6_5,
-		GP_6_4_FN,	GPSR6_4,
-		GP_6_3_FN,	GPSR6_3,
-		GP_6_2_FN,	GPSR6_2,
-		GP_6_1_FN,	GPSR6_1,
-		GP_6_0_FN,	GPSR6_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_7_3_FN, GPSR7_3,
-		GP_7_2_FN, GPSR7_2,
-		GP_7_1_FN, GPSR7_1,
-		GP_7_0_FN, GPSR7_0, ))
-	},
-#undef F_
-#undef FM
-
-#define F_(x, y)	x,
-#define FM(x)		FN_##x,
-	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
-		IP0_31_28
-		IP0_27_24
-		IP0_23_20
-		IP0_19_16
-		IP0_15_12
-		IP0_11_8
-		IP0_7_4
-		IP0_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
-		IP1_31_28
-		IP1_27_24
-		IP1_23_20
-		IP1_19_16
-		IP1_15_12
-		IP1_11_8
-		IP1_7_4
-		IP1_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
-		IP2_31_28
-		IP2_27_24
-		IP2_23_20
-		IP2_19_16
-		IP2_15_12
-		IP2_11_8
-		IP2_7_4
-		IP2_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
-		IP3_31_28
-		IP3_27_24
-		IP3_23_20
-		IP3_19_16
-		IP3_15_12
-		IP3_11_8
-		IP3_7_4
-		IP3_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
-		IP4_31_28
-		IP4_27_24
-		IP4_23_20
-		IP4_19_16
-		IP4_15_12
-		IP4_11_8
-		IP4_7_4
-		IP4_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
-		IP5_31_28
-		IP5_27_24
-		IP5_23_20
-		IP5_19_16
-		IP5_15_12
-		IP5_11_8
-		IP5_7_4
-		IP5_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
-		IP6_31_28
-		IP6_27_24
-		IP6_23_20
-		IP6_19_16
-		IP6_15_12
-		IP6_11_8
-		IP6_7_4
-		IP6_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
-		IP7_31_28
-		IP7_27_24
-		IP7_23_20
-		IP7_19_16
-		/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		IP7_11_8
-		IP7_7_4
-		IP7_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
-		IP8_31_28
-		IP8_27_24
-		IP8_23_20
-		IP8_19_16
-		IP8_15_12
-		IP8_11_8
-		IP8_7_4
-		IP8_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
-		IP9_31_28
-		IP9_27_24
-		IP9_23_20
-		IP9_19_16
-		IP9_15_12
-		IP9_11_8
-		IP9_7_4
-		IP9_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
-		IP10_31_28
-		IP10_27_24
-		IP10_23_20
-		IP10_19_16
-		IP10_15_12
-		IP10_11_8
-		IP10_7_4
-		IP10_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
-		IP11_31_28
-		IP11_27_24
-		IP11_23_20
-		IP11_19_16
-		IP11_15_12
-		IP11_11_8
-		IP11_7_4
-		IP11_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
-		IP12_31_28
-		IP12_27_24
-		IP12_23_20
-		IP12_19_16
-		IP12_15_12
-		IP12_11_8
-		IP12_7_4
-		IP12_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
-		IP13_31_28
-		IP13_27_24
-		IP13_23_20
-		IP13_19_16
-		IP13_15_12
-		IP13_11_8
-		IP13_7_4
-		IP13_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
-		IP14_31_28
-		IP14_27_24
-		IP14_23_20
-		IP14_19_16
-		IP14_15_12
-		IP14_11_8
-		IP14_7_4
-		IP14_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
-		IP15_31_28
-		IP15_27_24
-		IP15_23_20
-		IP15_19_16
-		IP15_15_12
-		IP15_11_8
-		IP15_7_4
-		IP15_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
-		IP16_31_28
-		IP16_27_24
-		IP16_23_20
-		IP16_19_16
-		IP16_15_12
-		IP16_11_8
-		IP16_7_4
-		IP16_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
-		IP17_31_28
-		IP17_27_24
-		IP17_23_20
-		IP17_19_16
-		IP17_15_12
-		IP17_11_8
-		IP17_7_4
-		IP17_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
-		/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP18_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		IP18_7_4
-		IP18_3_0 ))
-	},
-#undef F_
-#undef FM
-
-#define F_(x, y)	x,
-#define FM(x)		FN_##x,
-	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
-			     GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
-				   1, 1, 1, 2, 2, 1, 2, 3),
-			     GROUP(
-		MOD_SEL0_31_30_29
-		MOD_SEL0_28_27
-		MOD_SEL0_26_25_24
-		MOD_SEL0_23
-		MOD_SEL0_22
-		MOD_SEL0_21
-		MOD_SEL0_20
-		MOD_SEL0_19
-		MOD_SEL0_18_17
-		MOD_SEL0_16
-		0, 0, /* RESERVED 15 */
-		MOD_SEL0_14_13
-		MOD_SEL0_12
-		MOD_SEL0_11
-		MOD_SEL0_10
-		MOD_SEL0_9_8
-		MOD_SEL0_7_6
-		MOD_SEL0_5
-		MOD_SEL0_4_3
-		/* RESERVED 2, 1, 0 */
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
-			     GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
-				   1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
-			     GROUP(
-		MOD_SEL1_31_30
-		MOD_SEL1_29_28_27
-		MOD_SEL1_26
-		MOD_SEL1_25_24
-		MOD_SEL1_23_22_21
-		MOD_SEL1_20
-		MOD_SEL1_19
-		MOD_SEL1_18_17
-		MOD_SEL1_16
-		MOD_SEL1_15_14
-		MOD_SEL1_13
-		MOD_SEL1_12
-		MOD_SEL1_11
-		MOD_SEL1_10
-		MOD_SEL1_9
-		0, 0, 0, 0, /* RESERVED 8, 7 */
-		MOD_SEL1_6
-		MOD_SEL1_5
-		MOD_SEL1_4
-		MOD_SEL1_3
-		MOD_SEL1_2
-		MOD_SEL1_1
-		MOD_SEL1_0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
-			     GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
-				   1, 4, 4, 4, 3, 1),
-			     GROUP(
-		MOD_SEL2_31
-		MOD_SEL2_30
-		MOD_SEL2_29
-		MOD_SEL2_28_27
-		MOD_SEL2_26
-		MOD_SEL2_25_24_23
-		MOD_SEL2_22
-		MOD_SEL2_21
-		MOD_SEL2_20
-		MOD_SEL2_19
-		MOD_SEL2_18
-		MOD_SEL2_17
-		/* RESERVED 16 */
-		0, 0,
-		/* RESERVED 15, 14, 13, 12 */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 11, 10, 9, 8 */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 7, 6, 5, 4 */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 3, 2, 1 */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		MOD_SEL2_0 ))
-	},
-	{ },
-};
-
-static const struct pinmux_drive_reg pinmux_drive_regs[] = {
-	{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
-		{ PIN_QSPI0_SPCLK,    28, 2 },	/* QSPI0_SPCLK */
-		{ PIN_QSPI0_MOSI_IO0, 24, 2 },	/* QSPI0_MOSI_IO0 */
-		{ PIN_QSPI0_MISO_IO1, 20, 2 },	/* QSPI0_MISO_IO1 */
-		{ PIN_QSPI0_IO2,      16, 2 },	/* QSPI0_IO2 */
-		{ PIN_QSPI0_IO3,      12, 2 },	/* QSPI0_IO3 */
-		{ PIN_QSPI0_SSL,       8, 2 },	/* QSPI0_SSL */
-		{ PIN_QSPI1_SPCLK,     4, 2 },	/* QSPI1_SPCLK */
-		{ PIN_QSPI1_MOSI_IO0,  0, 2 },	/* QSPI1_MOSI_IO0 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
-		{ PIN_QSPI1_MISO_IO1, 28, 2 },	/* QSPI1_MISO_IO1 */
-		{ PIN_QSPI1_IO2,      24, 2 },	/* QSPI1_IO2 */
-		{ PIN_QSPI1_IO3,      20, 2 },	/* QSPI1_IO3 */
-		{ PIN_QSPI1_SSL,      16, 2 },	/* QSPI1_SSL */
-		{ PIN_RPC_INT_N,      12, 2 },	/* RPC_INT# */
-		{ PIN_RPC_WP_N,        8, 2 },	/* RPC_WP# */
-		{ PIN_RPC_RESET_N,     4, 2 },	/* RPC_RESET# */
-		{ PIN_AVB_RX_CTL,      0, 3 },	/* AVB_RX_CTL */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
-		{ PIN_AVB_RXC,        28, 3 },	/* AVB_RXC */
-		{ PIN_AVB_RD0,        24, 3 },	/* AVB_RD0 */
-		{ PIN_AVB_RD1,        20, 3 },	/* AVB_RD1 */
-		{ PIN_AVB_RD2,        16, 3 },	/* AVB_RD2 */
-		{ PIN_AVB_RD3,        12, 3 },	/* AVB_RD3 */
-		{ PIN_AVB_TX_CTL,      8, 3 },	/* AVB_TX_CTL */
-		{ PIN_AVB_TXC,         4, 3 },	/* AVB_TXC */
-		{ PIN_AVB_TD0,         0, 3 },	/* AVB_TD0 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
-		{ PIN_AVB_TD1,        28, 3 },	/* AVB_TD1 */
-		{ PIN_AVB_TD2,        24, 3 },	/* AVB_TD2 */
-		{ PIN_AVB_TD3,        20, 3 },	/* AVB_TD3 */
-		{ PIN_AVB_TXCREFCLK,  16, 3 },	/* AVB_TXCREFCLK */
-		{ PIN_AVB_MDIO,       12, 3 },	/* AVB_MDIO */
-		{ RCAR_GP_PIN(2,  9),  8, 3 },	/* AVB_MDC */
-		{ RCAR_GP_PIN(2, 10),  4, 3 },	/* AVB_MAGIC */
-		{ RCAR_GP_PIN(2, 11),  0, 3 },	/* AVB_PHY_INT */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
-		{ RCAR_GP_PIN(2, 12), 28, 3 },	/* AVB_LINK */
-		{ RCAR_GP_PIN(2, 13), 24, 3 },	/* AVB_AVTP_MATCH */
-		{ RCAR_GP_PIN(2, 14), 20, 3 },	/* AVB_AVTP_CAPTURE */
-		{ RCAR_GP_PIN(2,  0), 16, 3 },	/* IRQ0 */
-		{ RCAR_GP_PIN(2,  1), 12, 3 },	/* IRQ1 */
-		{ RCAR_GP_PIN(2,  2),  8, 3 },	/* IRQ2 */
-		{ RCAR_GP_PIN(2,  3),  4, 3 },	/* IRQ3 */
-		{ RCAR_GP_PIN(2,  4),  0, 3 },	/* IRQ4 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
-		{ RCAR_GP_PIN(2,  5), 28, 3 },	/* IRQ5 */
-		{ RCAR_GP_PIN(2,  6), 24, 3 },	/* PWM0 */
-		{ RCAR_GP_PIN(2,  7), 20, 3 },	/* PWM1 */
-		{ RCAR_GP_PIN(2,  8), 16, 3 },	/* PWM2 */
-		{ RCAR_GP_PIN(1,  0), 12, 3 },	/* A0 */
-		{ RCAR_GP_PIN(1,  1),  8, 3 },	/* A1 */
-		{ RCAR_GP_PIN(1,  2),  4, 3 },	/* A2 */
-		{ RCAR_GP_PIN(1,  3),  0, 3 },	/* A3 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
-		{ RCAR_GP_PIN(1,  4), 28, 3 },	/* A4 */
-		{ RCAR_GP_PIN(1,  5), 24, 3 },	/* A5 */
-		{ RCAR_GP_PIN(1,  6), 20, 3 },	/* A6 */
-		{ RCAR_GP_PIN(1,  7), 16, 3 },	/* A7 */
-		{ RCAR_GP_PIN(1,  8), 12, 3 },	/* A8 */
-		{ RCAR_GP_PIN(1,  9),  8, 3 },	/* A9 */
-		{ RCAR_GP_PIN(1, 10),  4, 3 },	/* A10 */
-		{ RCAR_GP_PIN(1, 11),  0, 3 },	/* A11 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
-		{ RCAR_GP_PIN(1, 12), 28, 3 },	/* A12 */
-		{ RCAR_GP_PIN(1, 13), 24, 3 },	/* A13 */
-		{ RCAR_GP_PIN(1, 14), 20, 3 },	/* A14 */
-		{ RCAR_GP_PIN(1, 15), 16, 3 },	/* A15 */
-		{ RCAR_GP_PIN(1, 16), 12, 3 },	/* A16 */
-		{ RCAR_GP_PIN(1, 17),  8, 3 },	/* A17 */
-		{ RCAR_GP_PIN(1, 18),  4, 3 },	/* A18 */
-		{ RCAR_GP_PIN(1, 19),  0, 3 },	/* A19 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
-		{ RCAR_GP_PIN(1, 28), 28, 3 },	/* CLKOUT */
-		{ RCAR_GP_PIN(1, 20), 24, 3 },	/* CS0 */
-		{ RCAR_GP_PIN(1, 21), 20, 3 },	/* CS1_A26 */
-		{ RCAR_GP_PIN(1, 22), 16, 3 },	/* BS */
-		{ RCAR_GP_PIN(1, 23), 12, 3 },	/* RD */
-		{ RCAR_GP_PIN(1, 24),  8, 3 },	/* RD_WR */
-		{ RCAR_GP_PIN(1, 25),  4, 3 },	/* WE0 */
-		{ RCAR_GP_PIN(1, 26),  0, 3 },	/* WE1 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
-		{ RCAR_GP_PIN(1, 27), 28, 3 },	/* EX_WAIT0 */
-		{ PIN_PRESETOUT_N,    24, 3 },	/* PRESETOUT# */
-		{ RCAR_GP_PIN(0,  0), 20, 3 },	/* D0 */
-		{ RCAR_GP_PIN(0,  1), 16, 3 },	/* D1 */
-		{ RCAR_GP_PIN(0,  2), 12, 3 },	/* D2 */
-		{ RCAR_GP_PIN(0,  3),  8, 3 },	/* D3 */
-		{ RCAR_GP_PIN(0,  4),  4, 3 },	/* D4 */
-		{ RCAR_GP_PIN(0,  5),  0, 3 },	/* D5 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
-		{ RCAR_GP_PIN(0,  6), 28, 3 },	/* D6 */
-		{ RCAR_GP_PIN(0,  7), 24, 3 },	/* D7 */
-		{ RCAR_GP_PIN(0,  8), 20, 3 },	/* D8 */
-		{ RCAR_GP_PIN(0,  9), 16, 3 },	/* D9 */
-		{ RCAR_GP_PIN(0, 10), 12, 3 },	/* D10 */
-		{ RCAR_GP_PIN(0, 11),  8, 3 },	/* D11 */
-		{ RCAR_GP_PIN(0, 12),  4, 3 },	/* D12 */
-		{ RCAR_GP_PIN(0, 13),  0, 3 },	/* D13 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
-		{ RCAR_GP_PIN(0, 14), 28, 3 },	/* D14 */
-		{ RCAR_GP_PIN(0, 15), 24, 3 },	/* D15 */
-		{ RCAR_GP_PIN(7,  0), 20, 3 },	/* AVS1 */
-		{ RCAR_GP_PIN(7,  1), 16, 3 },	/* AVS2 */
-		{ RCAR_GP_PIN(7,  2), 12, 3 },	/* GP7_02 */
-		{ RCAR_GP_PIN(7,  3),  8, 3 },	/* GP7_03 */
-		{ PIN_DU_DOTCLKIN0,    4, 2 },	/* DU_DOTCLKIN0 */
-		{ PIN_DU_DOTCLKIN1,    0, 2 },	/* DU_DOTCLKIN1 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
-		{ PIN_DU_DOTCLKIN2,   28, 2 },	/* DU_DOTCLKIN2 */
-		{ PIN_FSCLKST,        20, 2 },	/* FSCLKST */
-		{ PIN_TMS,             4, 2 },	/* TMS */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
-		{ PIN_TDO,            28, 2 },	/* TDO */
-		{ PIN_ASEBRK,         24, 2 },	/* ASEBRK */
-		{ RCAR_GP_PIN(3,  0), 20, 3 },	/* SD0_CLK */
-		{ RCAR_GP_PIN(3,  1), 16, 3 },	/* SD0_CMD */
-		{ RCAR_GP_PIN(3,  2), 12, 3 },	/* SD0_DAT0 */
-		{ RCAR_GP_PIN(3,  3),  8, 3 },	/* SD0_DAT1 */
-		{ RCAR_GP_PIN(3,  4),  4, 3 },	/* SD0_DAT2 */
-		{ RCAR_GP_PIN(3,  5),  0, 3 },	/* SD0_DAT3 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
-		{ RCAR_GP_PIN(3,  6), 28, 3 },	/* SD1_CLK */
-		{ RCAR_GP_PIN(3,  7), 24, 3 },	/* SD1_CMD */
-		{ RCAR_GP_PIN(3,  8), 20, 3 },	/* SD1_DAT0 */
-		{ RCAR_GP_PIN(3,  9), 16, 3 },	/* SD1_DAT1 */
-		{ RCAR_GP_PIN(3, 10), 12, 3 },	/* SD1_DAT2 */
-		{ RCAR_GP_PIN(3, 11),  8, 3 },	/* SD1_DAT3 */
-		{ RCAR_GP_PIN(4,  0),  4, 3 },	/* SD2_CLK */
-		{ RCAR_GP_PIN(4,  1),  0, 3 },	/* SD2_CMD */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
-		{ RCAR_GP_PIN(4,  2), 28, 3 },	/* SD2_DAT0 */
-		{ RCAR_GP_PIN(4,  3), 24, 3 },	/* SD2_DAT1 */
-		{ RCAR_GP_PIN(4,  4), 20, 3 },	/* SD2_DAT2 */
-		{ RCAR_GP_PIN(4,  5), 16, 3 },	/* SD2_DAT3 */
-		{ RCAR_GP_PIN(4,  6), 12, 3 },	/* SD2_DS */
-		{ RCAR_GP_PIN(4,  7),  8, 3 },	/* SD3_CLK */
-		{ RCAR_GP_PIN(4,  8),  4, 3 },	/* SD3_CMD */
-		{ RCAR_GP_PIN(4,  9),  0, 3 },	/* SD3_DAT0 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
-		{ RCAR_GP_PIN(4, 10), 28, 3 },	/* SD3_DAT1 */
-		{ RCAR_GP_PIN(4, 11), 24, 3 },	/* SD3_DAT2 */
-		{ RCAR_GP_PIN(4, 12), 20, 3 },	/* SD3_DAT3 */
-		{ RCAR_GP_PIN(4, 13), 16, 3 },	/* SD3_DAT4 */
-		{ RCAR_GP_PIN(4, 14), 12, 3 },	/* SD3_DAT5 */
-		{ RCAR_GP_PIN(4, 15),  8, 3 },	/* SD3_DAT6 */
-		{ RCAR_GP_PIN(4, 16),  4, 3 },	/* SD3_DAT7 */
-		{ RCAR_GP_PIN(4, 17),  0, 3 },	/* SD3_DS */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
-		{ RCAR_GP_PIN(3, 12), 28, 3 },	/* SD0_CD */
-		{ RCAR_GP_PIN(3, 13), 24, 3 },	/* SD0_WP */
-		{ RCAR_GP_PIN(3, 14), 20, 3 },	/* SD1_CD */
-		{ RCAR_GP_PIN(3, 15), 16, 3 },	/* SD1_WP */
-		{ RCAR_GP_PIN(5,  0), 12, 3 },	/* SCK0 */
-		{ RCAR_GP_PIN(5,  1),  8, 3 },	/* RX0 */
-		{ RCAR_GP_PIN(5,  2),  4, 3 },	/* TX0 */
-		{ RCAR_GP_PIN(5,  3),  0, 3 },	/* CTS0 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
-		{ RCAR_GP_PIN(5,  4), 28, 3 },	/* RTS0 */
-		{ RCAR_GP_PIN(5,  5), 24, 3 },	/* RX1 */
-		{ RCAR_GP_PIN(5,  6), 20, 3 },	/* TX1 */
-		{ RCAR_GP_PIN(5,  7), 16, 3 },	/* CTS1 */
-		{ RCAR_GP_PIN(5,  8), 12, 3 },	/* RTS1 */
-		{ RCAR_GP_PIN(5,  9),  8, 3 },	/* SCK2 */
-		{ RCAR_GP_PIN(5, 10),  4, 3 },	/* TX2 */
-		{ RCAR_GP_PIN(5, 11),  0, 3 },	/* RX2 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
-		{ RCAR_GP_PIN(5, 12), 28, 3 },	/* HSCK0 */
-		{ RCAR_GP_PIN(5, 13), 24, 3 },	/* HRX0 */
-		{ RCAR_GP_PIN(5, 14), 20, 3 },	/* HTX0 */
-		{ RCAR_GP_PIN(5, 15), 16, 3 },	/* HCTS0 */
-		{ RCAR_GP_PIN(5, 16), 12, 3 },	/* HRTS0 */
-		{ RCAR_GP_PIN(5, 17),  8, 3 },	/* MSIOF0_SCK */
-		{ RCAR_GP_PIN(5, 18),  4, 3 },	/* MSIOF0_SYNC */
-		{ RCAR_GP_PIN(5, 19),  0, 3 },	/* MSIOF0_SS1 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
-		{ RCAR_GP_PIN(5, 20), 28, 3 },	/* MSIOF0_TXD */
-		{ RCAR_GP_PIN(5, 21), 24, 3 },	/* MSIOF0_SS2 */
-		{ RCAR_GP_PIN(5, 22), 20, 3 },	/* MSIOF0_RXD */
-		{ RCAR_GP_PIN(5, 23), 16, 3 },	/* MLB_CLK */
-		{ RCAR_GP_PIN(5, 24), 12, 3 },	/* MLB_SIG */
-		{ RCAR_GP_PIN(5, 25),  8, 3 },	/* MLB_DAT */
-		{ PIN_MLB_REF,         4, 3 },	/* MLB_REF */
-		{ RCAR_GP_PIN(6,  0),  0, 3 },	/* SSI_SCK01239 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
-		{ RCAR_GP_PIN(6,  1), 28, 3 },	/* SSI_WS01239 */
-		{ RCAR_GP_PIN(6,  2), 24, 3 },	/* SSI_SDATA0 */
-		{ RCAR_GP_PIN(6,  3), 20, 3 },	/* SSI_SDATA1 */
-		{ RCAR_GP_PIN(6,  4), 16, 3 },	/* SSI_SDATA2 */
-		{ RCAR_GP_PIN(6,  5), 12, 3 },	/* SSI_SCK349 */
-		{ RCAR_GP_PIN(6,  6),  8, 3 },	/* SSI_WS349 */
-		{ RCAR_GP_PIN(6,  7),  4, 3 },	/* SSI_SDATA3 */
-		{ RCAR_GP_PIN(6,  8),  0, 3 },	/* SSI_SCK4 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
-		{ RCAR_GP_PIN(6,  9), 28, 3 },	/* SSI_WS4 */
-		{ RCAR_GP_PIN(6, 10), 24, 3 },	/* SSI_SDATA4 */
-		{ RCAR_GP_PIN(6, 11), 20, 3 },	/* SSI_SCK5 */
-		{ RCAR_GP_PIN(6, 12), 16, 3 },	/* SSI_WS5 */
-		{ RCAR_GP_PIN(6, 13), 12, 3 },	/* SSI_SDATA5 */
-		{ RCAR_GP_PIN(6, 14),  8, 3 },	/* SSI_SCK6 */
-		{ RCAR_GP_PIN(6, 15),  4, 3 },	/* SSI_WS6 */
-		{ RCAR_GP_PIN(6, 16),  0, 3 },	/* SSI_SDATA6 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
-		{ RCAR_GP_PIN(6, 17), 28, 3 },	/* SSI_SCK78 */
-		{ RCAR_GP_PIN(6, 18), 24, 3 },	/* SSI_WS78 */
-		{ RCAR_GP_PIN(6, 19), 20, 3 },	/* SSI_SDATA7 */
-		{ RCAR_GP_PIN(6, 20), 16, 3 },	/* SSI_SDATA8 */
-		{ RCAR_GP_PIN(6, 21), 12, 3 },	/* SSI_SDATA9 */
-		{ RCAR_GP_PIN(6, 22),  8, 3 },	/* AUDIO_CLKA */
-		{ RCAR_GP_PIN(6, 23),  4, 3 },	/* AUDIO_CLKB */
-		{ RCAR_GP_PIN(6, 24),  0, 3 },	/* USB0_PWEN */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
-		{ RCAR_GP_PIN(6, 25), 28, 3 },	/* USB0_OVC */
-		{ RCAR_GP_PIN(6, 26), 24, 3 },	/* USB1_PWEN */
-		{ RCAR_GP_PIN(6, 27), 20, 3 },	/* USB1_OVC */
-		{ RCAR_GP_PIN(6, 28), 16, 3 },	/* USB30_PWEN */
-		{ RCAR_GP_PIN(6, 29), 12, 3 },	/* USB30_OVC */
-		{ RCAR_GP_PIN(6, 30),  8, 3 },	/* GP6_30 */
-		{ RCAR_GP_PIN(6, 31),  4, 3 },	/* GP6_31 */
-	} },
-	{ },
-};
-
-enum ioctrl_regs {
-	POCCTRL,
-	TDSELCTRL,
-};
-
-static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
-	[POCCTRL] = { 0xe6060380, },
-	[TDSELCTRL] = { 0xe60603c0, },
-	{ /* sentinel */ },
-};
-
-static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
-{
-	int bit = -EINVAL;
-
-	*pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
-
-	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
-		bit = pin & 0x1f;
-
-	if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
-		bit = (pin & 0x1f) + 12;
-
-	return bit;
-}
-
-static const struct pinmux_bias_reg pinmux_bias_regs[] = {
-	{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
-		[ 0] = PIN_QSPI0_SPCLK,		/* QSPI0_SPCLK */
-		[ 1] = PIN_QSPI0_MOSI_IO0,	/* QSPI0_MOSI_IO0 */
-		[ 2] = PIN_QSPI0_MISO_IO1,	/* QSPI0_MISO_IO1 */
-		[ 3] = PIN_QSPI0_IO2,		/* QSPI0_IO2 */
-		[ 4] = PIN_QSPI0_IO3,		/* QSPI0_IO3 */
-		[ 5] = PIN_QSPI0_SSL,		/* QSPI0_SSL */
-		[ 6] = PIN_QSPI1_SPCLK,		/* QSPI1_SPCLK */
-		[ 7] = PIN_QSPI1_MOSI_IO0,	/* QSPI1_MOSI_IO0 */
-		[ 8] = PIN_QSPI1_MISO_IO1,	/* QSPI1_MISO_IO1 */
-		[ 9] = PIN_QSPI1_IO2,		/* QSPI1_IO2 */
-		[10] = PIN_QSPI1_IO3,		/* QSPI1_IO3 */
-		[11] = PIN_QSPI1_SSL,		/* QSPI1_SSL */
-		[12] = PIN_RPC_INT_N,		/* RPC_INT# */
-		[13] = PIN_RPC_WP_N,		/* RPC_WP# */
-		[14] = PIN_RPC_RESET_N,		/* RPC_RESET# */
-		[15] = PIN_AVB_RX_CTL,		/* AVB_RX_CTL */
-		[16] = PIN_AVB_RXC,		/* AVB_RXC */
-		[17] = PIN_AVB_RD0,		/* AVB_RD0 */
-		[18] = PIN_AVB_RD1,		/* AVB_RD1 */
-		[19] = PIN_AVB_RD2,		/* AVB_RD2 */
-		[20] = PIN_AVB_RD3,		/* AVB_RD3 */
-		[21] = PIN_AVB_TX_CTL,		/* AVB_TX_CTL */
-		[22] = PIN_AVB_TXC,		/* AVB_TXC */
-		[23] = PIN_AVB_TD0,		/* AVB_TD0 */
-		[24] = PIN_AVB_TD1,		/* AVB_TD1 */
-		[25] = PIN_AVB_TD2,		/* AVB_TD2 */
-		[26] = PIN_AVB_TD3,		/* AVB_TD3 */
-		[27] = PIN_AVB_TXCREFCLK,	/* AVB_TXCREFCLK */
-		[28] = PIN_AVB_MDIO,		/* AVB_MDIO */
-		[29] = RCAR_GP_PIN(2,  9),	/* AVB_MDC */
-		[30] = RCAR_GP_PIN(2, 10),	/* AVB_MAGIC */
-		[31] = RCAR_GP_PIN(2, 11),	/* AVB_PHY_INT */
-	} },
-	{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
-		[ 0] = RCAR_GP_PIN(2, 12),	/* AVB_LINK */
-		[ 1] = RCAR_GP_PIN(2, 13),	/* AVB_AVTP_MATCH_A */
-		[ 2] = RCAR_GP_PIN(2, 14),	/* AVB_AVTP_CAPTURE_A */
-		[ 3] = RCAR_GP_PIN(2,  0),	/* IRQ0 */
-		[ 4] = RCAR_GP_PIN(2,  1),	/* IRQ1 */
-		[ 5] = RCAR_GP_PIN(2,  2),	/* IRQ2 */
-		[ 6] = RCAR_GP_PIN(2,  3),	/* IRQ3 */
-		[ 7] = RCAR_GP_PIN(2,  4),	/* IRQ4 */
-		[ 8] = RCAR_GP_PIN(2,  5),	/* IRQ5 */
-		[ 9] = RCAR_GP_PIN(2,  6),	/* PWM0 */
-		[10] = RCAR_GP_PIN(2,  7),	/* PWM1_A */
-		[11] = RCAR_GP_PIN(2,  8),	/* PWM2_A */
-		[12] = RCAR_GP_PIN(1,  0),	/* A0 */
-		[13] = RCAR_GP_PIN(1,  1),	/* A1 */
-		[14] = RCAR_GP_PIN(1,  2),	/* A2 */
-		[15] = RCAR_GP_PIN(1,  3),	/* A3 */
-		[16] = RCAR_GP_PIN(1,  4),	/* A4 */
-		[17] = RCAR_GP_PIN(1,  5),	/* A5 */
-		[18] = RCAR_GP_PIN(1,  6),	/* A6 */
-		[19] = RCAR_GP_PIN(1,  7),	/* A7 */
-		[20] = RCAR_GP_PIN(1,  8),	/* A8 */
-		[21] = RCAR_GP_PIN(1,  9),	/* A9 */
-		[22] = RCAR_GP_PIN(1, 10),	/* A10 */
-		[23] = RCAR_GP_PIN(1, 11),	/* A11 */
-		[24] = RCAR_GP_PIN(1, 12),	/* A12 */
-		[25] = RCAR_GP_PIN(1, 13),	/* A13 */
-		[26] = RCAR_GP_PIN(1, 14),	/* A14 */
-		[27] = RCAR_GP_PIN(1, 15),	/* A15 */
-		[28] = RCAR_GP_PIN(1, 16),	/* A16 */
-		[29] = RCAR_GP_PIN(1, 17),	/* A17 */
-		[30] = RCAR_GP_PIN(1, 18),	/* A18 */
-		[31] = RCAR_GP_PIN(1, 19),	/* A19 */
-	} },
-	{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
-		[ 0] = RCAR_GP_PIN(1, 28),	/* CLKOUT */
-		[ 1] = RCAR_GP_PIN(1, 20),	/* CS0_N */
-		[ 2] = RCAR_GP_PIN(1, 21),	/* CS1_N */
-		[ 3] = RCAR_GP_PIN(1, 22),	/* BS_N */
-		[ 4] = RCAR_GP_PIN(1, 23),	/* RD_N */
-		[ 5] = RCAR_GP_PIN(1, 24),	/* RD_WR_N */
-		[ 6] = RCAR_GP_PIN(1, 25),	/* WE0_N */
-		[ 7] = RCAR_GP_PIN(1, 26),	/* WE1_N */
-		[ 8] = RCAR_GP_PIN(1, 27),	/* EX_WAIT0_A */
-		[ 9] = PIN_PRESETOUT_N,		/* PRESETOUT# */
-		[10] = RCAR_GP_PIN(0,  0),	/* D0 */
-		[11] = RCAR_GP_PIN(0,  1),	/* D1 */
-		[12] = RCAR_GP_PIN(0,  2),	/* D2 */
-		[13] = RCAR_GP_PIN(0,  3),	/* D3 */
-		[14] = RCAR_GP_PIN(0,  4),	/* D4 */
-		[15] = RCAR_GP_PIN(0,  5),	/* D5 */
-		[16] = RCAR_GP_PIN(0,  6),	/* D6 */
-		[17] = RCAR_GP_PIN(0,  7),	/* D7 */
-		[18] = RCAR_GP_PIN(0,  8),	/* D8 */
-		[19] = RCAR_GP_PIN(0,  9),	/* D9 */
-		[20] = RCAR_GP_PIN(0, 10),	/* D10 */
-		[21] = RCAR_GP_PIN(0, 11),	/* D11 */
-		[22] = RCAR_GP_PIN(0, 12),	/* D12 */
-		[23] = RCAR_GP_PIN(0, 13),	/* D13 */
-		[24] = RCAR_GP_PIN(0, 14),	/* D14 */
-		[25] = RCAR_GP_PIN(0, 15),	/* D15 */
-		[26] = RCAR_GP_PIN(7,  0),	/* AVS1 */
-		[27] = RCAR_GP_PIN(7,  1),	/* AVS2 */
-		[28] = RCAR_GP_PIN(7,  2),	/* GP7_02 */
-		[29] = RCAR_GP_PIN(7,  3),	/* GP7_03 */
-		[30] = PIN_DU_DOTCLKIN0,	/* DU_DOTCLKIN0 */
-		[31] = PIN_DU_DOTCLKIN1,	/* DU_DOTCLKIN1 */
-	} },
-	{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
-		[ 0] = PIN_DU_DOTCLKIN2,	/* DU_DOTCLKIN2 */
-		[ 1] = SH_PFC_PIN_NONE,
-		[ 2] = PIN_FSCLKST,		/* FSCLKST */
-		[ 3] = PIN_EXTALR,		/* EXTALR*/
-		[ 4] = PIN_TRST_N,		/* TRST# */
-		[ 5] = PIN_TCK,			/* TCK */
-		[ 6] = PIN_TMS,			/* TMS */
-		[ 7] = PIN_TDI,			/* TDI */
-		[ 8] = SH_PFC_PIN_NONE,
-		[ 9] = PIN_ASEBRK,		/* ASEBRK */
-		[10] = RCAR_GP_PIN(3,  0),	/* SD0_CLK */
-		[11] = RCAR_GP_PIN(3,  1),	/* SD0_CMD */
-		[12] = RCAR_GP_PIN(3,  2),	/* SD0_DAT0 */
-		[13] = RCAR_GP_PIN(3,  3),	/* SD0_DAT1 */
-		[14] = RCAR_GP_PIN(3,  4),	/* SD0_DAT2 */
-		[15] = RCAR_GP_PIN(3,  5),	/* SD0_DAT3 */
-		[16] = RCAR_GP_PIN(3,  6),	/* SD1_CLK */
-		[17] = RCAR_GP_PIN(3,  7),	/* SD1_CMD */
-		[18] = RCAR_GP_PIN(3,  8),	/* SD1_DAT0 */
-		[19] = RCAR_GP_PIN(3,  9),	/* SD1_DAT1 */
-		[20] = RCAR_GP_PIN(3, 10),	/* SD1_DAT2 */
-		[21] = RCAR_GP_PIN(3, 11),	/* SD1_DAT3 */
-		[22] = RCAR_GP_PIN(4,  0),	/* SD2_CLK */
-		[23] = RCAR_GP_PIN(4,  1),	/* SD2_CMD */
-		[24] = RCAR_GP_PIN(4,  2),	/* SD2_DAT0 */
-		[25] = RCAR_GP_PIN(4,  3),	/* SD2_DAT1 */
-		[26] = RCAR_GP_PIN(4,  4),	/* SD2_DAT2 */
-		[27] = RCAR_GP_PIN(4,  5),	/* SD2_DAT3 */
-		[28] = RCAR_GP_PIN(4,  6),	/* SD2_DS */
-		[29] = RCAR_GP_PIN(4,  7),	/* SD3_CLK */
-		[30] = RCAR_GP_PIN(4,  8),	/* SD3_CMD */
-		[31] = RCAR_GP_PIN(4,  9),	/* SD3_DAT0 */
-	} },
-	{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
-		[ 0] = RCAR_GP_PIN(4, 10),	/* SD3_DAT1 */
-		[ 1] = RCAR_GP_PIN(4, 11),	/* SD3_DAT2 */
-		[ 2] = RCAR_GP_PIN(4, 12),	/* SD3_DAT3 */
-		[ 3] = RCAR_GP_PIN(4, 13),	/* SD3_DAT4 */
-		[ 4] = RCAR_GP_PIN(4, 14),	/* SD3_DAT5 */
-		[ 5] = RCAR_GP_PIN(4, 15),	/* SD3_DAT6 */
-		[ 6] = RCAR_GP_PIN(4, 16),	/* SD3_DAT7 */
-		[ 7] = RCAR_GP_PIN(4, 17),	/* SD3_DS */
-		[ 8] = RCAR_GP_PIN(3, 12),	/* SD0_CD */
-		[ 9] = RCAR_GP_PIN(3, 13),	/* SD0_WP */
-		[10] = RCAR_GP_PIN(3, 14),	/* SD1_CD */
-		[11] = RCAR_GP_PIN(3, 15),	/* SD1_WP */
-		[12] = RCAR_GP_PIN(5,  0),	/* SCK0 */
-		[13] = RCAR_GP_PIN(5,  1),	/* RX0 */
-		[14] = RCAR_GP_PIN(5,  2),	/* TX0 */
-		[15] = RCAR_GP_PIN(5,  3),	/* CTS0_N */
-		[16] = RCAR_GP_PIN(5,  4),	/* RTS0_N */
-		[17] = RCAR_GP_PIN(5,  5),	/* RX1_A */
-		[18] = RCAR_GP_PIN(5,  6),	/* TX1_A */
-		[19] = RCAR_GP_PIN(5,  7),	/* CTS1_N */
-		[20] = RCAR_GP_PIN(5,  8),	/* RTS1_N */
-		[21] = RCAR_GP_PIN(5,  9),	/* SCK2 */
-		[22] = RCAR_GP_PIN(5, 10),	/* TX2_A */
-		[23] = RCAR_GP_PIN(5, 11),	/* RX2_A */
-		[24] = RCAR_GP_PIN(5, 12),	/* HSCK0 */
-		[25] = RCAR_GP_PIN(5, 13),	/* HRX0 */
-		[26] = RCAR_GP_PIN(5, 14),	/* HTX0 */
-		[27] = RCAR_GP_PIN(5, 15),	/* HCTS0_N */
-		[28] = RCAR_GP_PIN(5, 16),	/* HRTS0_N */
-		[29] = RCAR_GP_PIN(5, 17),	/* MSIOF0_SCK */
-		[30] = RCAR_GP_PIN(5, 18),	/* MSIOF0_SYNC */
-		[31] = RCAR_GP_PIN(5, 19),	/* MSIOF0_SS1 */
-	} },
-	{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
-		[ 0] = RCAR_GP_PIN(5, 20),	/* MSIOF0_TXD */
-		[ 1] = RCAR_GP_PIN(5, 21),	/* MSIOF0_SS2 */
-		[ 2] = RCAR_GP_PIN(5, 22),	/* MSIOF0_RXD */
-		[ 3] = RCAR_GP_PIN(5, 23),	/* MLB_CLK */
-		[ 4] = RCAR_GP_PIN(5, 24),	/* MLB_SIG */
-		[ 5] = RCAR_GP_PIN(5, 25),	/* MLB_DAT */
-		[ 6] = PIN_MLB_REF,		/* MLB_REF */
-		[ 7] = RCAR_GP_PIN(6,  0),	/* SSI_SCK01239 */
-		[ 8] = RCAR_GP_PIN(6,  1),	/* SSI_WS01239 */
-		[ 9] = RCAR_GP_PIN(6,  2),	/* SSI_SDATA0 */
-		[10] = RCAR_GP_PIN(6,  3),	/* SSI_SDATA1_A */
-		[11] = RCAR_GP_PIN(6,  4),	/* SSI_SDATA2_A */
-		[12] = RCAR_GP_PIN(6,  5),	/* SSI_SCK349 */
-		[13] = RCAR_GP_PIN(6,  6),	/* SSI_WS349 */
-		[14] = RCAR_GP_PIN(6,  7),	/* SSI_SDATA3 */
-		[15] = RCAR_GP_PIN(6,  8),	/* SSI_SCK4 */
-		[16] = RCAR_GP_PIN(6,  9),	/* SSI_WS4 */
-		[17] = RCAR_GP_PIN(6, 10),	/* SSI_SDATA4 */
-		[18] = RCAR_GP_PIN(6, 11),	/* SSI_SCK5 */
-		[19] = RCAR_GP_PIN(6, 12),	/* SSI_WS5 */
-		[20] = RCAR_GP_PIN(6, 13),	/* SSI_SDATA5 */
-		[21] = RCAR_GP_PIN(6, 14),	/* SSI_SCK6 */
-		[22] = RCAR_GP_PIN(6, 15),	/* SSI_WS6 */
-		[23] = RCAR_GP_PIN(6, 16),	/* SSI_SDATA6 */
-		[24] = RCAR_GP_PIN(6, 17),	/* SSI_SCK78 */
-		[25] = RCAR_GP_PIN(6, 18),	/* SSI_WS78 */
-		[26] = RCAR_GP_PIN(6, 19),	/* SSI_SDATA7 */
-		[27] = RCAR_GP_PIN(6, 20),	/* SSI_SDATA8 */
-		[28] = RCAR_GP_PIN(6, 21),	/* SSI_SDATA9_A */
-		[29] = RCAR_GP_PIN(6, 22),	/* AUDIO_CLKA_A */
-		[30] = RCAR_GP_PIN(6, 23),	/* AUDIO_CLKB_B */
-		[31] = RCAR_GP_PIN(6, 24),	/* USB0_PWEN */
-	} },
-	{ PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
-		[ 0] = RCAR_GP_PIN(6, 25),	/* USB0_OVC */
-		[ 1] = RCAR_GP_PIN(6, 26),	/* USB1_PWEN */
-		[ 2] = RCAR_GP_PIN(6, 27),	/* USB1_OVC */
-		[ 3] = RCAR_GP_PIN(6, 28),	/* USB30_PWEN */
-		[ 4] = RCAR_GP_PIN(6, 29),	/* USB30_OVC */
-		[ 5] = RCAR_GP_PIN(6, 30),	/* GP6_30 */
-		[ 6] = RCAR_GP_PIN(6, 31),	/* GP6_31 */
-		[ 7] = SH_PFC_PIN_NONE,
-		[ 8] = SH_PFC_PIN_NONE,
-		[ 9] = SH_PFC_PIN_NONE,
-		[10] = SH_PFC_PIN_NONE,
-		[11] = SH_PFC_PIN_NONE,
-		[12] = SH_PFC_PIN_NONE,
-		[13] = SH_PFC_PIN_NONE,
-		[14] = SH_PFC_PIN_NONE,
-		[15] = SH_PFC_PIN_NONE,
-		[16] = SH_PFC_PIN_NONE,
-		[17] = SH_PFC_PIN_NONE,
-		[18] = SH_PFC_PIN_NONE,
-		[19] = SH_PFC_PIN_NONE,
-		[20] = SH_PFC_PIN_NONE,
-		[21] = SH_PFC_PIN_NONE,
-		[22] = SH_PFC_PIN_NONE,
-		[23] = SH_PFC_PIN_NONE,
-		[24] = SH_PFC_PIN_NONE,
-		[25] = SH_PFC_PIN_NONE,
-		[26] = SH_PFC_PIN_NONE,
-		[27] = SH_PFC_PIN_NONE,
-		[28] = SH_PFC_PIN_NONE,
-		[29] = SH_PFC_PIN_NONE,
-		[30] = SH_PFC_PIN_NONE,
-		[31] = SH_PFC_PIN_NONE,
-	} },
-	{ /* sentinel */ },
-};
-
-static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
-					    unsigned int pin)
-{
-	const struct pinmux_bias_reg *reg;
-	unsigned int bit;
-
-	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
-	if (!reg)
-		return PIN_CONFIG_BIAS_DISABLE;
-
-	if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
-		return PIN_CONFIG_BIAS_DISABLE;
-	else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
-		return PIN_CONFIG_BIAS_PULL_UP;
-	else
-		return PIN_CONFIG_BIAS_PULL_DOWN;
-}
-
-static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
-				   unsigned int bias)
-{
-	const struct pinmux_bias_reg *reg;
-	u32 enable, updown;
-	unsigned int bit;
-
-	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
-	if (!reg)
-		return;
-
-	enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
-	if (bias != PIN_CONFIG_BIAS_DISABLE)
-		enable |= BIT(bit);
-
-	updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
-	if (bias == PIN_CONFIG_BIAS_PULL_UP)
-		updown |= BIT(bit);
-
-	sh_pfc_write(pfc, reg->pud, updown);
-	sh_pfc_write(pfc, reg->puen, enable);
-}
-
-static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
-	.pin_to_pocctrl = r8a7796_pin_to_pocctrl,
-	.get_bias = r8a7796_pinmux_get_bias,
-	.set_bias = r8a7796_pinmux_set_bias,
-};
-
-#ifdef CONFIG_PINCTRL_PFC_R8A774A1
-const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
-	.name = "r8a774a1_pfc",
-	.ops = &r8a7796_pinmux_ops,
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups.common,
-	.nr_groups = ARRAY_SIZE(pinmux_groups.common),
-	.functions = pinmux_functions.common,
-	.nr_functions = ARRAY_SIZE(pinmux_functions.common),
-
-	.cfg_regs = pinmux_config_regs,
-	.drive_regs = pinmux_drive_regs,
-	.bias_regs = pinmux_bias_regs,
-	.ioctrl_regs = pinmux_ioctrl_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
-#endif
-
-#ifdef CONFIG_PINCTRL_PFC_R8A77960
-const struct sh_pfc_soc_info r8a77960_pinmux_info = {
-	.name = "r8a77960_pfc",
-	.ops = &r8a7796_pinmux_ops,
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups.common,
-	.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
-		ARRAY_SIZE(pinmux_groups.automotive),
-	.functions = pinmux_functions.common,
-	.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
-		ARRAY_SIZE(pinmux_functions.automotive),
-
-	.cfg_regs = pinmux_config_regs,
-	.drive_regs = pinmux_drive_regs,
-	.bias_regs = pinmux_bias_regs,
-	.ioctrl_regs = pinmux_ioctrl_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
-#endif
-
-#ifdef CONFIG_PINCTRL_PFC_R8A77961
-const struct sh_pfc_soc_info r8a77961_pinmux_info = {
-	.name = "r8a77961_pfc",
-	.ops = &r8a7796_pinmux_ops,
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups.common,
-	.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
-		ARRAY_SIZE(pinmux_groups.automotive),
-	.functions = pinmux_functions.common,
-	.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
-		ARRAY_SIZE(pinmux_functions.automotive),
-
-	.cfg_regs = pinmux_config_regs,
-	.drive_regs = pinmux_drive_regs,
-	.bias_regs = pinmux_bias_regs,
-	.ioctrl_regs = pinmux_ioctrl_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
-#endif
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
deleted file mode 100644
index 6616f5210b9d..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+++ /dev/null
@@ -1,6492 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * R8A77965 processor support - PFC hardware block.
- *
- * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
- * Copyright (C) 2016-2019 Renesas Electronics Corp.
- *
- * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
- *
- * R-Car Gen3 processor support - PFC hardware block.
- *
- * Copyright (C) 2015  Renesas Electronics Corporation
- */
-
-#include <linux/errno.h>
-#include <linux/kernel.h>
-
-#include "core.h"
-#include "sh_pfc.h"
-
-#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
-
-#define CPU_ALL_GP(fn, sfx)						\
-	PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),	\
-	PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
-
-#define CPU_ALL_NOGP(fn)						\
-	PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS),			\
-	PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
-	PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
-	PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
-	PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
-	PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS),			\
-	PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
-
-/*
- * F_() : just information
- * FM() : macro for FN_xxx / xxx_MARK
- */
-
-/* GPSR0 */
-#define GPSR0_15	F_(D15,			IP7_11_8)
-#define GPSR0_14	F_(D14,			IP7_7_4)
-#define GPSR0_13	F_(D13,			IP7_3_0)
-#define GPSR0_12	F_(D12,			IP6_31_28)
-#define GPSR0_11	F_(D11,			IP6_27_24)
-#define GPSR0_10	F_(D10,			IP6_23_20)
-#define GPSR0_9		F_(D9,			IP6_19_16)
-#define GPSR0_8		F_(D8,			IP6_15_12)
-#define GPSR0_7		F_(D7,			IP6_11_8)
-#define GPSR0_6		F_(D6,			IP6_7_4)
-#define GPSR0_5		F_(D5,			IP6_3_0)
-#define GPSR0_4		F_(D4,			IP5_31_28)
-#define GPSR0_3		F_(D3,			IP5_27_24)
-#define GPSR0_2		F_(D2,			IP5_23_20)
-#define GPSR0_1		F_(D1,			IP5_19_16)
-#define GPSR0_0		F_(D0,			IP5_15_12)
-
-/* GPSR1 */
-#define GPSR1_28	FM(CLKOUT)
-#define GPSR1_27	F_(EX_WAIT0_A,		IP5_11_8)
-#define GPSR1_26	F_(WE1_N,		IP5_7_4)
-#define GPSR1_25	F_(WE0_N,		IP5_3_0)
-#define GPSR1_24	F_(RD_WR_N,		IP4_31_28)
-#define GPSR1_23	F_(RD_N,		IP4_27_24)
-#define GPSR1_22	F_(BS_N,		IP4_23_20)
-#define GPSR1_21	F_(CS1_N,		IP4_19_16)
-#define GPSR1_20	F_(CS0_N,		IP4_15_12)
-#define GPSR1_19	F_(A19,			IP4_11_8)
-#define GPSR1_18	F_(A18,			IP4_7_4)
-#define GPSR1_17	F_(A17,			IP4_3_0)
-#define GPSR1_16	F_(A16,			IP3_31_28)
-#define GPSR1_15	F_(A15,			IP3_27_24)
-#define GPSR1_14	F_(A14,			IP3_23_20)
-#define GPSR1_13	F_(A13,			IP3_19_16)
-#define GPSR1_12	F_(A12,			IP3_15_12)
-#define GPSR1_11	F_(A11,			IP3_11_8)
-#define GPSR1_10	F_(A10,			IP3_7_4)
-#define GPSR1_9		F_(A9,			IP3_3_0)
-#define GPSR1_8		F_(A8,			IP2_31_28)
-#define GPSR1_7		F_(A7,			IP2_27_24)
-#define GPSR1_6		F_(A6,			IP2_23_20)
-#define GPSR1_5		F_(A5,			IP2_19_16)
-#define GPSR1_4		F_(A4,			IP2_15_12)
-#define GPSR1_3		F_(A3,			IP2_11_8)
-#define GPSR1_2		F_(A2,			IP2_7_4)
-#define GPSR1_1		F_(A1,			IP2_3_0)
-#define GPSR1_0		F_(A0,			IP1_31_28)
-
-/* GPSR2 */
-#define GPSR2_14	F_(AVB_AVTP_CAPTURE_A,	IP0_23_20)
-#define GPSR2_13	F_(AVB_AVTP_MATCH_A,	IP0_19_16)
-#define GPSR2_12	F_(AVB_LINK,		IP0_15_12)
-#define GPSR2_11	F_(AVB_PHY_INT,		IP0_11_8)
-#define GPSR2_10	F_(AVB_MAGIC,		IP0_7_4)
-#define GPSR2_9		F_(AVB_MDC,		IP0_3_0)
-#define GPSR2_8		F_(PWM2_A,		IP1_27_24)
-#define GPSR2_7		F_(PWM1_A,		IP1_23_20)
-#define GPSR2_6		F_(PWM0,		IP1_19_16)
-#define GPSR2_5		F_(IRQ5,		IP1_15_12)
-#define GPSR2_4		F_(IRQ4,		IP1_11_8)
-#define GPSR2_3		F_(IRQ3,		IP1_7_4)
-#define GPSR2_2		F_(IRQ2,		IP1_3_0)
-#define GPSR2_1		F_(IRQ1,		IP0_31_28)
-#define GPSR2_0		F_(IRQ0,		IP0_27_24)
-
-/* GPSR3 */
-#define GPSR3_15	F_(SD1_WP,		IP11_23_20)
-#define GPSR3_14	F_(SD1_CD,		IP11_19_16)
-#define GPSR3_13	F_(SD0_WP,		IP11_15_12)
-#define GPSR3_12	F_(SD0_CD,		IP11_11_8)
-#define GPSR3_11	F_(SD1_DAT3,		IP8_31_28)
-#define GPSR3_10	F_(SD1_DAT2,		IP8_27_24)
-#define GPSR3_9		F_(SD1_DAT1,		IP8_23_20)
-#define GPSR3_8		F_(SD1_DAT0,		IP8_19_16)
-#define GPSR3_7		F_(SD1_CMD,		IP8_15_12)
-#define GPSR3_6		F_(SD1_CLK,		IP8_11_8)
-#define GPSR3_5		F_(SD0_DAT3,		IP8_7_4)
-#define GPSR3_4		F_(SD0_DAT2,		IP8_3_0)
-#define GPSR3_3		F_(SD0_DAT1,		IP7_31_28)
-#define GPSR3_2		F_(SD0_DAT0,		IP7_27_24)
-#define GPSR3_1		F_(SD0_CMD,		IP7_23_20)
-#define GPSR3_0		F_(SD0_CLK,		IP7_19_16)
-
-/* GPSR4 */
-#define GPSR4_17	F_(SD3_DS,		IP11_7_4)
-#define GPSR4_16	F_(SD3_DAT7,		IP11_3_0)
-#define GPSR4_15	F_(SD3_DAT6,		IP10_31_28)
-#define GPSR4_14	F_(SD3_DAT5,		IP10_27_24)
-#define GPSR4_13	F_(SD3_DAT4,		IP10_23_20)
-#define GPSR4_12	F_(SD3_DAT3,		IP10_19_16)
-#define GPSR4_11	F_(SD3_DAT2,		IP10_15_12)
-#define GPSR4_10	F_(SD3_DAT1,		IP10_11_8)
-#define GPSR4_9		F_(SD3_DAT0,		IP10_7_4)
-#define GPSR4_8		F_(SD3_CMD,		IP10_3_0)
-#define GPSR4_7		F_(SD3_CLK,		IP9_31_28)
-#define GPSR4_6		F_(SD2_DS,		IP9_27_24)
-#define GPSR4_5		F_(SD2_DAT3,		IP9_23_20)
-#define GPSR4_4		F_(SD2_DAT2,		IP9_19_16)
-#define GPSR4_3		F_(SD2_DAT1,		IP9_15_12)
-#define GPSR4_2		F_(SD2_DAT0,		IP9_11_8)
-#define GPSR4_1		F_(SD2_CMD,		IP9_7_4)
-#define GPSR4_0		F_(SD2_CLK,		IP9_3_0)
-
-/* GPSR5 */
-#define GPSR5_25	F_(MLB_DAT,		IP14_19_16)
-#define GPSR5_24	F_(MLB_SIG,		IP14_15_12)
-#define GPSR5_23	F_(MLB_CLK,		IP14_11_8)
-#define GPSR5_22	FM(MSIOF0_RXD)
-#define GPSR5_21	F_(MSIOF0_SS2,		IP14_7_4)
-#define GPSR5_20	FM(MSIOF0_TXD)
-#define GPSR5_19	F_(MSIOF0_SS1,		IP14_3_0)
-#define GPSR5_18	F_(MSIOF0_SYNC,		IP13_31_28)
-#define GPSR5_17	FM(MSIOF0_SCK)
-#define GPSR5_16	F_(HRTS0_N,		IP13_27_24)
-#define GPSR5_15	F_(HCTS0_N,		IP13_23_20)
-#define GPSR5_14	F_(HTX0,		IP13_19_16)
-#define GPSR5_13	F_(HRX0,		IP13_15_12)
-#define GPSR5_12	F_(HSCK0,		IP13_11_8)
-#define GPSR5_11	F_(RX2_A,		IP13_7_4)
-#define GPSR5_10	F_(TX2_A,		IP13_3_0)
-#define GPSR5_9		F_(SCK2,		IP12_31_28)
-#define GPSR5_8		F_(RTS1_N,		IP12_27_24)
-#define GPSR5_7		F_(CTS1_N,		IP12_23_20)
-#define GPSR5_6		F_(TX1_A,		IP12_19_16)
-#define GPSR5_5		F_(RX1_A,		IP12_15_12)
-#define GPSR5_4		F_(RTS0_N,		IP12_11_8)
-#define GPSR5_3		F_(CTS0_N,		IP12_7_4)
-#define GPSR5_2		F_(TX0,			IP12_3_0)
-#define GPSR5_1		F_(RX0,			IP11_31_28)
-#define GPSR5_0		F_(SCK0,		IP11_27_24)
-
-/* GPSR6 */
-#define GPSR6_31	F_(GP6_31,		IP18_7_4)
-#define GPSR6_30	F_(GP6_30,		IP18_3_0)
-#define GPSR6_29	F_(USB30_OVC,		IP17_31_28)
-#define GPSR6_28	F_(USB30_PWEN,		IP17_27_24)
-#define GPSR6_27	F_(USB1_OVC,		IP17_23_20)
-#define GPSR6_26	F_(USB1_PWEN,		IP17_19_16)
-#define GPSR6_25	F_(USB0_OVC,		IP17_15_12)
-#define GPSR6_24	F_(USB0_PWEN,		IP17_11_8)
-#define GPSR6_23	F_(AUDIO_CLKB_B,	IP17_7_4)
-#define GPSR6_22	F_(AUDIO_CLKA_A,	IP17_3_0)
-#define GPSR6_21	F_(SSI_SDATA9_A,	IP16_31_28)
-#define GPSR6_20	F_(SSI_SDATA8,		IP16_27_24)
-#define GPSR6_19	F_(SSI_SDATA7,		IP16_23_20)
-#define GPSR6_18	F_(SSI_WS78,		IP16_19_16)
-#define GPSR6_17	F_(SSI_SCK78,		IP16_15_12)
-#define GPSR6_16	F_(SSI_SDATA6,		IP16_11_8)
-#define GPSR6_15	F_(SSI_WS6,		IP16_7_4)
-#define GPSR6_14	F_(SSI_SCK6,		IP16_3_0)
-#define GPSR6_13	FM(SSI_SDATA5)
-#define GPSR6_12	FM(SSI_WS5)
-#define GPSR6_11	FM(SSI_SCK5)
-#define GPSR6_10	F_(SSI_SDATA4,		IP15_31_28)
-#define GPSR6_9		F_(SSI_WS4,		IP15_27_24)
-#define GPSR6_8		F_(SSI_SCK4,		IP15_23_20)
-#define GPSR6_7		F_(SSI_SDATA3,		IP15_19_16)
-#define GPSR6_6		F_(SSI_WS349,		IP15_15_12)
-#define GPSR6_5		F_(SSI_SCK349,		IP15_11_8)
-#define GPSR6_4		F_(SSI_SDATA2_A,	IP15_7_4)
-#define GPSR6_3		F_(SSI_SDATA1_A,	IP15_3_0)
-#define GPSR6_2		F_(SSI_SDATA0,		IP14_31_28)
-#define GPSR6_1		F_(SSI_WS01239,		IP14_27_24)
-#define GPSR6_0		F_(SSI_SCK01239,	IP14_23_20)
-
-/* GPSR7 */
-#define GPSR7_3		FM(GP7_03)
-#define GPSR7_2		FM(GP7_02)
-#define GPSR7_1		FM(AVS2)
-#define GPSR7_0		FM(AVS1)
-
-
-/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
-#define IP0_3_0		FM(AVB_MDC)		F_(0, 0)	FM(MSIOF2_SS2_C)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_7_4		FM(AVB_MAGIC)		F_(0, 0)	FM(MSIOF2_SS1_C)	FM(SCK4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_11_8	FM(AVB_PHY_INT)		F_(0, 0)	FM(MSIOF2_SYNC_C)	FM(RX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_15_12	FM(AVB_LINK)		F_(0, 0)	FM(MSIOF2_SCK_C)	FM(TX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_19_16	FM(AVB_AVTP_MATCH_A)	F_(0, 0)	FM(MSIOF2_RXD_C)	FM(CTS4_N_A)			F_(0, 0)	FM(FSCLKST2_N_A) F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_23_20	FM(AVB_AVTP_CAPTURE_A)	F_(0, 0)	FM(MSIOF2_TXD_C)	FM(RTS4_N_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_27_24	FM(IRQ0)		FM(QPOLB)	F_(0, 0)		FM(DU_CDE)			FM(VI4_DATA0_B) FM(CAN0_TX_B)	FM(CANFD0_TX_B)		FM(MSIOF3_SS2_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_31_28	FM(IRQ1)		FM(QPOLA)	F_(0, 0)		FM(DU_DISP)			FM(VI4_DATA1_B) FM(CAN0_RX_B)	FM(CANFD0_RX_B)		FM(MSIOF3_SS1_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_3_0		FM(IRQ2)		FM(QCPV_QDE)	F_(0, 0)		FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(VI4_DATA2_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SYNC_E) F_(0, 0)		FM(PWM3_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_7_4		FM(IRQ3)		FM(QSTVB_QVE)	F_(0, 0)		FM(DU_DOTCLKOUT1)		FM(VI4_DATA3_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SCK_E) F_(0, 0)		FM(PWM4_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_11_8	FM(IRQ4)		FM(QSTH_QHS)	F_(0, 0)		FM(DU_EXHSYNC_DU_HSYNC)		FM(VI4_DATA4_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_RXD_E) F_(0, 0)		FM(PWM5_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_15_12	FM(IRQ5)		FM(QSTB_QHE)	F_(0, 0)		FM(DU_EXVSYNC_DU_VSYNC)		FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0)		FM(MSIOF3_TXD_E) F_(0, 0)		FM(PWM6_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_19_16	FM(PWM0)		FM(AVB_AVTP_PPS)F_(0, 0)		F_(0, 0)			FM(VI4_DATA6_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IECLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_23_20	FM(PWM1_A)		F_(0, 0)	F_(0, 0)		FM(HRX3_D)			FM(VI4_DATA7_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IERX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_27_24	FM(PWM2_A)		F_(0, 0)	F_(0, 0)		FM(HTX3_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IETX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_31_28	FM(A0)			FM(LCDOUT16)	FM(MSIOF3_SYNC_B)	F_(0, 0)			FM(VI4_DATA8)	F_(0, 0)	FM(DU_DB0)		F_(0, 0)	F_(0, 0)		FM(PWM3_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_3_0		FM(A1)			FM(LCDOUT17)	FM(MSIOF3_TXD_B)	F_(0, 0)			FM(VI4_DATA9)	F_(0, 0)	FM(DU_DB1)		F_(0, 0)	F_(0, 0)		FM(PWM4_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_7_4		FM(A2)			FM(LCDOUT18)	FM(MSIOF3_SCK_B)	F_(0, 0)			FM(VI4_DATA10)	F_(0, 0)	FM(DU_DB2)		F_(0, 0)	F_(0, 0)		FM(PWM5_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_11_8	FM(A3)			FM(LCDOUT19)	FM(MSIOF3_RXD_B)	F_(0, 0)			FM(VI4_DATA11)	F_(0, 0)	FM(DU_DB3)		F_(0, 0)	F_(0, 0)		FM(PWM6_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_15_12	FM(A4)			FM(LCDOUT20)	FM(MSIOF3_SS1_B)	F_(0, 0)			FM(VI4_DATA12)	FM(VI5_DATA12)	FM(DU_DB4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_19_16	FM(A5)			FM(LCDOUT21)	FM(MSIOF3_SS2_B)	FM(SCK4_B)			FM(VI4_DATA13)	FM(VI5_DATA13)	FM(DU_DB5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_23_20	FM(A6)			FM(LCDOUT22)	FM(MSIOF2_SS1_A)	FM(RX4_B)			FM(VI4_DATA14)	FM(VI5_DATA14)	FM(DU_DB6)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_27_24	FM(A7)			FM(LCDOUT23)	FM(MSIOF2_SS2_A)	FM(TX4_B)			FM(VI4_DATA15)	FM(VI5_DATA15)	FM(DU_DB7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_31_28	FM(A8)			FM(RX3_B)	FM(MSIOF2_SYNC_A)	FM(HRX4_B)			F_(0, 0)	F_(0, 0)	F_(0, 0)		FM(SDA6_A)	FM(AVB_AVTP_MATCH_B)	FM(PWM1_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_3_0		FM(A9)			F_(0, 0)	FM(MSIOF2_SCK_A)	FM(CTS4_N_B)			F_(0, 0)	FM(VI5_VSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_7_4		FM(A10)			F_(0, 0)	FM(MSIOF2_RXD_A)	FM(RTS4_N_B)			F_(0, 0)	FM(VI5_HSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_11_8	FM(A11)			FM(TX3_B)	FM(MSIOF2_TXD_A)	FM(HTX4_B)			FM(HSCK4)	FM(VI5_FIELD)	F_(0, 0)		FM(SCL6_A)	FM(AVB_AVTP_CAPTURE_B)	FM(PWM2_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
-#define IP3_15_12	FM(A12)			FM(LCDOUT12)	FM(MSIOF3_SCK_C)	F_(0, 0)			FM(HRX4_A)	FM(VI5_DATA8)	FM(DU_DG4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_19_16	FM(A13)			FM(LCDOUT13)	FM(MSIOF3_SYNC_C)	F_(0, 0)			FM(HTX4_A)	FM(VI5_DATA9)	FM(DU_DG5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_23_20	FM(A14)			FM(LCDOUT14)	FM(MSIOF3_RXD_C)	F_(0, 0)			FM(HCTS4_N)	FM(VI5_DATA10)	FM(DU_DG6)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_27_24	FM(A15)			FM(LCDOUT15)	FM(MSIOF3_TXD_C)	F_(0, 0)			FM(HRTS4_N)	FM(VI5_DATA11)	FM(DU_DG7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_31_28	FM(A16)			FM(LCDOUT8)	F_(0, 0)		F_(0, 0)			FM(VI4_FIELD)	F_(0, 0)	FM(DU_DG0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_3_0		FM(A17)			FM(LCDOUT9)	F_(0, 0)		F_(0, 0)			FM(VI4_VSYNC_N)	F_(0, 0)	FM(DU_DG1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_7_4		FM(A18)			FM(LCDOUT10)	F_(0, 0)		F_(0, 0)			FM(VI4_HSYNC_N)	F_(0, 0)	FM(DU_DG2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_11_8	FM(A19)			FM(LCDOUT11)	F_(0, 0)		F_(0, 0)			FM(VI4_CLKENB)	F_(0, 0)	FM(DU_DG3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_15_12	FM(CS0_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(VI5_CLKENB)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_19_16	FM(CS1_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(VI5_CLK)	F_(0, 0)		FM(EX_WAIT0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_23_20	FM(BS_N)		FM(QSTVA_QVS)	FM(MSIOF3_SCK_D)	FM(SCK3)			FM(HSCK3)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN1_TX)		FM(CANFD1_TX)	FM(IETX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_27_24	FM(RD_N)		F_(0, 0)	FM(MSIOF3_SYNC_D)	FM(RX3_A)			FM(HRX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_TX_A)		FM(CANFD0_TX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_31_28	FM(RD_WR_N)		F_(0, 0)	FM(MSIOF3_RXD_D)	FM(TX3_A)			FM(HTX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_RX_A)		FM(CANFD0_RX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_3_0		FM(WE0_N)		F_(0, 0)	FM(MSIOF3_TXD_D)	FM(CTS3_N)			FM(HCTS3_N)	F_(0, 0)	F_(0, 0)		FM(SCL6_B)	FM(CAN_CLK)		F_(0, 0)	FM(IECLK_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_7_4		FM(WE1_N)		F_(0, 0)	FM(MSIOF3_SS1_D)	FM(RTS3_N)			FM(HRTS3_N)	F_(0, 0)	F_(0, 0)		FM(SDA6_B)	FM(CAN1_RX)		FM(CANFD1_RX)	FM(IERX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_11_8	FM(EX_WAIT0_A)		FM(QCLK)	F_(0, 0)		F_(0, 0)			FM(VI4_CLK)	F_(0, 0)	FM(DU_DOTCLKOUT0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_15_12	FM(D0)			FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)	F_(0, 0)			FM(VI4_DATA16)	FM(VI5_DATA0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_19_16	FM(D1)			FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)	F_(0, 0)			FM(VI4_DATA17)	FM(VI5_DATA1)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_23_20	FM(D2)			F_(0, 0)	FM(MSIOF3_RXD_A)	F_(0, 0)			FM(VI4_DATA18)	FM(VI5_DATA2)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_27_24	FM(D3)			F_(0, 0)	FM(MSIOF3_TXD_A)	F_(0, 0)			FM(VI4_DATA19)	FM(VI5_DATA3)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_31_28	FM(D4)			FM(MSIOF2_SCK_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA20)	FM(VI5_DATA4)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_3_0		FM(D5)			FM(MSIOF2_SYNC_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA21)	FM(VI5_DATA5)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_7_4		FM(D6)			FM(MSIOF2_RXD_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA22)	FM(VI5_DATA6)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_11_8	FM(D7)			FM(MSIOF2_TXD_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA23)	FM(VI5_DATA7)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_15_12	FM(D8)			FM(LCDOUT0)	FM(MSIOF2_SCK_D)	FM(SCK4_C)			FM(VI4_DATA0_A)	F_(0, 0)	FM(DU_DR0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_19_16	FM(D9)			FM(LCDOUT1)	FM(MSIOF2_SYNC_D)	F_(0, 0)			FM(VI4_DATA1_A)	F_(0, 0)	FM(DU_DR1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_23_20	FM(D10)			FM(LCDOUT2)	FM(MSIOF2_RXD_D)	FM(HRX3_B)			FM(VI4_DATA2_A)	FM(CTS4_N_C)	FM(DU_DR2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_27_24	FM(D11)			FM(LCDOUT3)	FM(MSIOF2_TXD_D)	FM(HTX3_B)			FM(VI4_DATA3_A)	FM(RTS4_N_C)	FM(DU_DR3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_31_28	FM(D12)			FM(LCDOUT4)	FM(MSIOF2_SS1_D)	FM(RX4_C)			FM(VI4_DATA4_A)	F_(0, 0)	FM(DU_DR4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
-#define IP7_3_0		FM(D13)			FM(LCDOUT5)	FM(MSIOF2_SS2_D)	FM(TX4_C)			FM(VI4_DATA5_A)	F_(0, 0)	FM(DU_DR5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_7_4		FM(D14)			FM(LCDOUT6)	FM(MSIOF3_SS1_A)	FM(HRX3_C)			FM(VI4_DATA6_A)	F_(0, 0)	FM(DU_DR6)		FM(SCL6_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_11_8	FM(D15)			FM(LCDOUT7)	FM(MSIOF3_SS2_A)	FM(HTX3_C)			FM(VI4_DATA7_A)	F_(0, 0)	FM(DU_DR7)		FM(SDA6_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_19_16	FM(SD0_CLK)		F_(0, 0)	FM(MSIOF1_SCK_E)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_OPWM_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_23_20	FM(SD0_CMD)		F_(0, 0)	FM(MSIOF1_SYNC_E)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_27_24	FM(SD0_DAT0)		F_(0, 0)	FM(MSIOF1_RXD_E)	F_(0, 0)			F_(0, 0)	FM(TS_SCK0_B)	FM(STP_ISCLK_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_31_28	FM(SD0_DAT1)		F_(0, 0)	FM(MSIOF1_TXD_E)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_3_0		FM(SD0_DAT2)		F_(0, 0)	FM(MSIOF1_SS1_E)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_B)	FM(STP_ISD_0_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_7_4		FM(SD0_DAT3)		F_(0, 0)	FM(MSIOF1_SS2_E)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_B)	FM(STP_ISEN_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_11_8	FM(SD1_CLK)		F_(0, 0)	FM(MSIOF1_SCK_G)	F_(0, 0)			F_(0, 0)	FM(SIM0_CLK_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_15_12	FM(SD1_CMD)		F_(0, 0)	FM(MSIOF1_SYNC_G)	FM(NFCE_N_B)			F_(0, 0)	FM(SIM0_D_A)	FM(STP_IVCXO27_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_19_16	FM(SD1_DAT0)		FM(SD2_DAT4)	FM(MSIOF1_RXD_G)	FM(NFWP_N_B)			F_(0, 0)	FM(TS_SCK1_B)	FM(STP_ISCLK_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_23_20	FM(SD1_DAT1)		FM(SD2_DAT5)	FM(MSIOF1_TXD_G)	FM(NFDATA14_B)			F_(0, 0)	FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_27_24	FM(SD1_DAT2)		FM(SD2_DAT6)	FM(MSIOF1_SS1_G)	FM(NFDATA15_B)			F_(0, 0)	FM(TS_SDAT1_B)	FM(STP_ISD_1_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_31_28	FM(SD1_DAT3)		FM(SD2_DAT7)	FM(MSIOF1_SS2_G)	FM(NFRB_N_B)			F_(0, 0)	FM(TS_SDEN1_B)	FM(STP_ISEN_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_3_0		FM(SD2_CLK)		F_(0, 0)	FM(NFDATA8)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_7_4		FM(SD2_CMD)		F_(0, 0)	FM(NFDATA9)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_11_8	FM(SD2_DAT0)		F_(0, 0)	FM(NFDATA10)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_15_12	FM(SD2_DAT1)		F_(0, 0)	FM(NFDATA11)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_19_16	FM(SD2_DAT2)		F_(0, 0)	FM(NFDATA12)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_23_20	FM(SD2_DAT3)		F_(0, 0)	FM(NFDATA13)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_27_24	FM(SD2_DS)		F_(0, 0)	FM(NFALE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(SATA_DEVSLP_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_31_28	FM(SD3_CLK)		F_(0, 0)	FM(NFWE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_3_0	FM(SD3_CMD)		F_(0, 0)	FM(NFRE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_7_4	FM(SD3_DAT0)		F_(0, 0)	FM(NFDATA0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_11_8	FM(SD3_DAT1)		F_(0, 0)	FM(NFDATA1)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_15_12	FM(SD3_DAT2)		F_(0, 0)	FM(NFDATA2)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_19_16	FM(SD3_DAT3)		F_(0, 0)	FM(NFDATA3)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_23_20	FM(SD3_DAT4)		FM(SD2_CD_A)	FM(NFDATA4)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_27_24	FM(SD3_DAT5)		FM(SD2_WP_A)	FM(NFDATA5)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_31_28	FM(SD3_DAT6)		FM(SD3_CD)	FM(NFDATA6)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_3_0	FM(SD3_DAT7)		FM(SD3_WP)	FM(NFDATA7)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_7_4	FM(SD3_DS)		F_(0, 0)	FM(NFCLE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_11_8	FM(SD0_CD)		F_(0, 0)	FM(NFDATA14_A)		F_(0, 0)			FM(SCL2_B)	FM(SIM0_RST_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
-#define IP11_15_12	FM(SD0_WP)		F_(0, 0)	FM(NFDATA15_A)		F_(0, 0)			FM(SDA2_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_19_16	FM(SD1_CD)		F_(0, 0)	FM(NFRB_N_A)		F_(0, 0)			F_(0, 0)	FM(SIM0_CLK_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_23_20	FM(SD1_WP)		F_(0, 0)	FM(NFCE_N_A)		F_(0, 0)			F_(0, 0)	FM(SIM0_D_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_27_24	FM(SCK0)		FM(HSCK1_B)	FM(MSIOF1_SS2_B)	FM(AUDIO_CLKC_B)		FM(SDA2_A)	FM(SIM0_RST_B)	FM(STP_OPWM_0_C)	FM(RIF0_CLK_B)	F_(0, 0)		FM(ADICHS2)	FM(SCK5_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_31_28	FM(RX0)			FM(HRX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SCK0_C)	FM(STP_ISCLK_0_C)	FM(RIF0_D0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_3_0	FM(TX0)			FM(HTX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)	FM(RIF0_D1_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_7_4	FM(CTS0_N)		FM(HCTS1_N_B)	FM(MSIOF1_SYNC_B)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)	FM(RIF1_SYNC_B)	FM(AUDIO_CLKOUT_C)	FM(ADICS_SAMP)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_11_8	FM(RTS0_N)		FM(HRTS1_N_B)	FM(MSIOF1_SS1_B)	FM(AUDIO_CLKA_B)		FM(SCL2_A)	F_(0, 0)	FM(STP_IVCXO27_1_C)	FM(RIF0_SYNC_B)	F_(0, 0)		FM(ADICHS1)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_15_12	FM(RX1_A)		FM(HRX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_C)	FM(STP_ISD_0_C)		FM(RIF1_CLK_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_19_16	FM(TX1_A)		FM(HTX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_C)	FM(STP_ISEN_0_C)	FM(RIF1_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_23_20	FM(CTS1_N)		FM(HCTS1_N_A)	FM(MSIOF1_RXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_C)	FM(STP_ISEN_1_C)	FM(RIF1_D0_B)	F_(0, 0)		FM(ADIDATA)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_27_24	FM(RTS1_N)		FM(HRTS1_N_A)	FM(MSIOF1_TXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_C)	FM(STP_ISD_1_C)		FM(RIF1_D1_B)	F_(0, 0)		FM(ADICHS0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_31_28	FM(SCK2)		FM(SCIF_CLK_B)	FM(MSIOF1_SCK_B)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_C)	FM(STP_ISCLK_1_C)	FM(RIF1_CLK_B)	F_(0, 0)		FM(ADICLK)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_3_0	FM(TX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_CD_B)			FM(SCL1_A)	F_(0, 0)	FM(FMCLK_A)		FM(RIF1_D1_C)	F_(0, 0)		FM(FSO_CFE_0_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_7_4	FM(RX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_WP_B)			FM(SDA1_A)	F_(0, 0)	FM(FMIN_A)		FM(RIF1_SYNC_C)	F_(0, 0)		FM(FSO_CFE_1_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_11_8	FM(HSCK0)		F_(0, 0)	FM(MSIOF1_SCK_D)	FM(AUDIO_CLKB_A)		FM(SSI_SDATA1_B)FM(TS_SCK0_D)	FM(STP_ISCLK_0_D)	FM(RIF0_CLK_C)	F_(0, 0)		F_(0, 0)	FM(RX5_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_15_12	FM(HRX0)		F_(0, 0)	FM(MSIOF1_RXD_D)	F_(0, 0)			FM(SSI_SDATA2_B)FM(TS_SDEN0_D)	FM(STP_ISEN_0_D)	FM(RIF0_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_19_16	FM(HTX0)		F_(0, 0)	FM(MSIOF1_TXD_D)	F_(0, 0)			FM(SSI_SDATA9_B)FM(TS_SDAT0_D)	FM(STP_ISD_0_D)		FM(RIF0_D1_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_23_20	FM(HCTS0_N)		FM(RX2_B)	FM(MSIOF1_SYNC_D)	F_(0, 0)			FM(SSI_SCK9_A)	FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)	FM(RIF0_SYNC_C)	FM(AUDIO_CLKOUT1_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_27_24	FM(HRTS0_N)		FM(TX2_B)	FM(MSIOF1_SS1_D)	F_(0, 0)			FM(SSI_WS9_A)	F_(0, 0)	FM(STP_IVCXO27_0_D)	FM(BPFCLK_A)	FM(AUDIO_CLKOUT2_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_31_28	FM(MSIOF0_SYNC)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(AUDIO_CLKOUT_A)	F_(0, 0)	FM(TX5_B)	F_(0, 0)	F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
-#define IP14_3_0	FM(MSIOF0_SS1)		FM(RX5_A)	FM(NFWP_N_A)		FM(AUDIO_CLKA_C)		FM(SSI_SCK2_A)	F_(0, 0)	FM(STP_IVCXO27_0_C)	F_(0, 0)	FM(AUDIO_CLKOUT3_A)	F_(0, 0)	FM(TCLK1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_7_4	FM(MSIOF0_SS2)		FM(TX5_A)	FM(MSIOF1_SS2_D)	FM(AUDIO_CLKC_A)		FM(SSI_WS2_A)	F_(0, 0)	FM(STP_OPWM_0_D)	F_(0, 0)	FM(AUDIO_CLKOUT_D)	F_(0, 0)	FM(SPEEDIN_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_11_8	FM(MLB_CLK)		F_(0, 0)	FM(MSIOF1_SCK_F)	F_(0, 0)			FM(SCL1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_15_12	FM(MLB_SIG)		FM(RX1_B)	FM(MSIOF1_SYNC_F)	F_(0, 0)			FM(SDA1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_19_16	FM(MLB_DAT)		FM(TX1_B)	FM(MSIOF1_RXD_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_23_20	FM(SSI_SCK01239)	F_(0, 0)	FM(MSIOF1_TXD_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_27_24	FM(SSI_WS01239)		F_(0, 0)	FM(MSIOF1_SS1_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
-#define IP14_31_28	FM(SSI_SDATA0)		F_(0, 0)	FM(MSIOF1_SS2_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_3_0	FM(SSI_SDATA1_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_7_4	FM(SSI_SDATA2_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			FM(SSI_SCK1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_11_8	FM(SSI_SCK349)		F_(0, 0)	FM(MSIOF1_SS1_A)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_OPWM_0_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_15_12	FM(SSI_WS349)		FM(HCTS2_N_A)	FM(MSIOF1_SS2_A)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_0_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_19_16	FM(SSI_SDATA3)		FM(HRTS2_N_A)	FM(MSIOF1_TXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SCK0_A)	FM(STP_ISCLK_0_A)	FM(RIF0_D1_A)	FM(RIF2_D0_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_23_20	FM(SSI_SCK4)		FM(HRX2_A)	FM(MSIOF1_SCK_A)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_A)	FM(STP_ISD_0_A)		FM(RIF0_CLK_A)	FM(RIF2_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_27_24	FM(SSI_WS4)		FM(HTX2_A)	FM(MSIOF1_SYNC_A)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_A)	FM(STP_ISEN_0_A)	FM(RIF0_SYNC_A)	FM(RIF2_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_31_28	FM(SSI_SDATA4)		FM(HSCK2_A)	FM(MSIOF1_RXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)	FM(RIF0_D0_A)	FM(RIF2_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_3_0	FM(SSI_SCK6)		F_(0, 0)	F_(0, 0)		FM(SIM0_RST_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_7_4	FM(SSI_WS6)		F_(0, 0)	F_(0, 0)		FM(SIM0_D_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_11_8	FM(SSI_SDATA6)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(SATA_DEVSLP_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_15_12	FM(SSI_SCK78)		FM(HRX2_B)	FM(MSIOF1_SCK_C)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_A)	FM(STP_ISCLK_1_A)	FM(RIF1_CLK_A)	FM(RIF3_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_19_16	FM(SSI_WS78)		FM(HTX2_B)	FM(MSIOF1_SYNC_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_A)	FM(STP_ISD_1_A)		FM(RIF1_SYNC_A)	FM(RIF3_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_23_20	FM(SSI_SDATA7)		FM(HCTS2_N_B)	FM(MSIOF1_RXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_A)	FM(STP_ISEN_1_A)	FM(RIF1_D0_A)	FM(RIF3_D0_A)		F_(0, 0)	FM(TCLK2_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_27_24	FM(SSI_SDATA8)		FM(HRTS2_N_B)	FM(MSIOF1_TXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)	FM(RIF1_D1_A)	FM(RIF3_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_31_28	FM(SSI_SDATA9_A)	FM(HSCK2_B)	FM(MSIOF1_SS1_C)	FM(HSCK1_A)			FM(SSI_WS1_B)	FM(SCK1)	FM(STP_IVCXO27_1_A)	FM(SCK5_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP17_3_0	FM(AUDIO_CLKA_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP17_7_4	FM(AUDIO_CLKB_B)	FM(SCIF_CLK_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_1_D)	FM(REMOCON_A)	F_(0, 0)		F_(0, 0)	FM(TCLK1_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP17_11_8	FM(USB0_PWEN)		F_(0, 0)	F_(0, 0)		FM(SIM0_RST_C)			F_(0, 0)	FM(TS_SCK1_D)	FM(STP_ISCLK_1_D)	FM(BPFCLK_B)	FM(RIF3_CLK_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
-#define IP17_15_12	FM(USB0_OVC)		F_(0, 0)	F_(0, 0)		FM(SIM0_D_C)			F_(0, 0)	FM(TS_SDAT1_D)	FM(STP_ISD_1_D)		F_(0, 0)	FM(RIF3_SYNC_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
-#define IP17_19_16	FM(USB1_PWEN)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_C)			FM(SSI_SCK1_A)	FM(TS_SCK0_E)	FM(STP_ISCLK_0_E)	FM(FMCLK_B)	FM(RIF2_CLK_B)		F_(0, 0)	FM(SPEEDIN_A)	F_(0, 0)	F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
-#define IP17_23_20	FM(USB1_OVC)		F_(0, 0)	FM(MSIOF1_SS2_C)	F_(0, 0)			FM(SSI_WS1_A)	FM(TS_SDAT0_E)	FM(STP_ISD_0_E)		FM(FMIN_B)	FM(RIF2_SYNC_B)		F_(0, 0)	FM(REMOCON_B)	F_(0, 0)	F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
-#define IP17_27_24	FM(USB30_PWEN)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT_B)		FM(SSI_SCK2_B)	FM(TS_SDEN1_D)	FM(STP_ISEN_1_D)	FM(STP_OPWM_0_E)FM(RIF3_D0_B)		F_(0, 0)	FM(TCLK2_B)	FM(TPU0TO0)	FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
-#define IP17_31_28	FM(USB30_OVC)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT1_B)		FM(SSI_WS2_B)	FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)	FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)	F_(0, 0)	FM(FSO_TOE_N)	FM(TPU0TO1)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP18_3_0	FM(GP6_30)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT2_B)		FM(SSI_SCK9_B)	FM(TS_SDEN0_E)	FM(STP_ISEN_0_E)	F_(0, 0)	FM(RIF2_D0_B)		F_(0, 0)	F_(0, 0)	FM(TPU0TO2)	FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
-#define IP18_7_4	FM(GP6_31)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT3_B)		FM(SSI_WS9_B)	FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)	F_(0, 0)	FM(RIF2_D1_B)		F_(0, 0)	F_(0, 0)	FM(TPU0TO3)	FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
-
-#define PINMUX_GPSR	\
-\
-												GPSR6_31 \
-												GPSR6_30 \
-												GPSR6_29 \
-		GPSR1_28									GPSR6_28 \
-		GPSR1_27									GPSR6_27 \
-		GPSR1_26									GPSR6_26 \
-		GPSR1_25							GPSR5_25	GPSR6_25 \
-		GPSR1_24							GPSR5_24	GPSR6_24 \
-		GPSR1_23							GPSR5_23	GPSR6_23 \
-		GPSR1_22							GPSR5_22	GPSR6_22 \
-		GPSR1_21							GPSR5_21	GPSR6_21 \
-		GPSR1_20							GPSR5_20	GPSR6_20 \
-		GPSR1_19							GPSR5_19	GPSR6_19 \
-		GPSR1_18							GPSR5_18	GPSR6_18 \
-		GPSR1_17					GPSR4_17	GPSR5_17	GPSR6_17 \
-		GPSR1_16					GPSR4_16	GPSR5_16	GPSR6_16 \
-GPSR0_15	GPSR1_15			GPSR3_15	GPSR4_15	GPSR5_15	GPSR6_15 \
-GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14	GPSR4_14	GPSR5_14	GPSR6_14 \
-GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13	GPSR4_13	GPSR5_13	GPSR6_13 \
-GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12	GPSR4_12	GPSR5_12	GPSR6_12 \
-GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11	GPSR4_11	GPSR5_11	GPSR6_11 \
-GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10	GPSR6_10 \
-GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9		GPSR6_9 \
-GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8		GPSR6_8 \
-GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7		GPSR6_7 \
-GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6		GPSR6_6 \
-GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5		GPSR6_5 \
-GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4		GPSR6_4 \
-GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3		GPSR6_3		GPSR7_3 \
-GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2		GPSR6_2		GPSR7_2 \
-GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1		GPSR6_1		GPSR7_1 \
-GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0		GPSR6_0		GPSR7_0
-
-#define PINMUX_IPSR				\
-\
-FM(IP0_3_0)	IP0_3_0		FM(IP1_3_0)	IP1_3_0		FM(IP2_3_0)	IP2_3_0		FM(IP3_3_0)	IP3_3_0 \
-FM(IP0_7_4)	IP0_7_4		FM(IP1_7_4)	IP1_7_4		FM(IP2_7_4)	IP2_7_4		FM(IP3_7_4)	IP3_7_4 \
-FM(IP0_11_8)	IP0_11_8	FM(IP1_11_8)	IP1_11_8	FM(IP2_11_8)	IP2_11_8	FM(IP3_11_8)	IP3_11_8 \
-FM(IP0_15_12)	IP0_15_12	FM(IP1_15_12)	IP1_15_12	FM(IP2_15_12)	IP2_15_12	FM(IP3_15_12)	IP3_15_12 \
-FM(IP0_19_16)	IP0_19_16	FM(IP1_19_16)	IP1_19_16	FM(IP2_19_16)	IP2_19_16	FM(IP3_19_16)	IP3_19_16 \
-FM(IP0_23_20)	IP0_23_20	FM(IP1_23_20)	IP1_23_20	FM(IP2_23_20)	IP2_23_20	FM(IP3_23_20)	IP3_23_20 \
-FM(IP0_27_24)	IP0_27_24	FM(IP1_27_24)	IP1_27_24	FM(IP2_27_24)	IP2_27_24	FM(IP3_27_24)	IP3_27_24 \
-FM(IP0_31_28)	IP0_31_28	FM(IP1_31_28)	IP1_31_28	FM(IP2_31_28)	IP2_31_28	FM(IP3_31_28)	IP3_31_28 \
-\
-FM(IP4_3_0)	IP4_3_0		FM(IP5_3_0)	IP5_3_0		FM(IP6_3_0)	IP6_3_0		FM(IP7_3_0)	IP7_3_0 \
-FM(IP4_7_4)	IP4_7_4		FM(IP5_7_4)	IP5_7_4		FM(IP6_7_4)	IP6_7_4		FM(IP7_7_4)	IP7_7_4 \
-FM(IP4_11_8)	IP4_11_8	FM(IP5_11_8)	IP5_11_8	FM(IP6_11_8)	IP6_11_8	FM(IP7_11_8)	IP7_11_8 \
-FM(IP4_15_12)	IP4_15_12	FM(IP5_15_12)	IP5_15_12	FM(IP6_15_12)	IP6_15_12 \
-FM(IP4_19_16)	IP4_19_16	FM(IP5_19_16)	IP5_19_16	FM(IP6_19_16)	IP6_19_16	FM(IP7_19_16)	IP7_19_16 \
-FM(IP4_23_20)	IP4_23_20	FM(IP5_23_20)	IP5_23_20	FM(IP6_23_20)	IP6_23_20	FM(IP7_23_20)	IP7_23_20 \
-FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
-FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
-\
-FM(IP8_3_0)	IP8_3_0		FM(IP9_3_0)	IP9_3_0		FM(IP10_3_0)	IP10_3_0	FM(IP11_3_0)	IP11_3_0 \
-FM(IP8_7_4)	IP8_7_4		FM(IP9_7_4)	IP9_7_4		FM(IP10_7_4)	IP10_7_4	FM(IP11_7_4)	IP11_7_4 \
-FM(IP8_11_8)	IP8_11_8	FM(IP9_11_8)	IP9_11_8	FM(IP10_11_8)	IP10_11_8	FM(IP11_11_8)	IP11_11_8 \
-FM(IP8_15_12)	IP8_15_12	FM(IP9_15_12)	IP9_15_12	FM(IP10_15_12)	IP10_15_12	FM(IP11_15_12)	IP11_15_12 \
-FM(IP8_19_16)	IP8_19_16	FM(IP9_19_16)	IP9_19_16	FM(IP10_19_16)	IP10_19_16	FM(IP11_19_16)	IP11_19_16 \
-FM(IP8_23_20)	IP8_23_20	FM(IP9_23_20)	IP9_23_20	FM(IP10_23_20)	IP10_23_20	FM(IP11_23_20)	IP11_23_20 \
-FM(IP8_27_24)	IP8_27_24	FM(IP9_27_24)	IP9_27_24	FM(IP10_27_24)	IP10_27_24	FM(IP11_27_24)	IP11_27_24 \
-FM(IP8_31_28)	IP8_31_28	FM(IP9_31_28)	IP9_31_28	FM(IP10_31_28)	IP10_31_28	FM(IP11_31_28)	IP11_31_28 \
-\
-FM(IP12_3_0)	IP12_3_0	FM(IP13_3_0)	IP13_3_0	FM(IP14_3_0)	IP14_3_0	FM(IP15_3_0)	IP15_3_0 \
-FM(IP12_7_4)	IP12_7_4	FM(IP13_7_4)	IP13_7_4	FM(IP14_7_4)	IP14_7_4	FM(IP15_7_4)	IP15_7_4 \
-FM(IP12_11_8)	IP12_11_8	FM(IP13_11_8)	IP13_11_8	FM(IP14_11_8)	IP14_11_8	FM(IP15_11_8)	IP15_11_8 \
-FM(IP12_15_12)	IP12_15_12	FM(IP13_15_12)	IP13_15_12	FM(IP14_15_12)	IP14_15_12	FM(IP15_15_12)	IP15_15_12 \
-FM(IP12_19_16)	IP12_19_16	FM(IP13_19_16)	IP13_19_16	FM(IP14_19_16)	IP14_19_16	FM(IP15_19_16)	IP15_19_16 \
-FM(IP12_23_20)	IP12_23_20	FM(IP13_23_20)	IP13_23_20	FM(IP14_23_20)	IP14_23_20	FM(IP15_23_20)	IP15_23_20 \
-FM(IP12_27_24)	IP12_27_24	FM(IP13_27_24)	IP13_27_24	FM(IP14_27_24)	IP14_27_24	FM(IP15_27_24)	IP15_27_24 \
-FM(IP12_31_28)	IP12_31_28	FM(IP13_31_28)	IP13_31_28	FM(IP14_31_28)	IP14_31_28	FM(IP15_31_28)	IP15_31_28 \
-\
-FM(IP16_3_0)	IP16_3_0	FM(IP17_3_0)	IP17_3_0	FM(IP18_3_0)	IP18_3_0 \
-FM(IP16_7_4)	IP16_7_4	FM(IP17_7_4)	IP17_7_4	FM(IP18_7_4)	IP18_7_4 \
-FM(IP16_11_8)	IP16_11_8	FM(IP17_11_8)	IP17_11_8 \
-FM(IP16_15_12)	IP16_15_12	FM(IP17_15_12)	IP17_15_12 \
-FM(IP16_19_16)	IP16_19_16	FM(IP17_19_16)	IP17_19_16 \
-FM(IP16_23_20)	IP16_23_20	FM(IP17_23_20)	IP17_23_20 \
-FM(IP16_27_24)	IP16_27_24	FM(IP17_27_24)	IP17_27_24 \
-FM(IP16_31_28)	IP16_31_28	FM(IP17_31_28)	IP17_31_28
-
-/* MOD_SEL0 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
-#define MOD_SEL0_31_30_29	FM(SEL_MSIOF3_0)	FM(SEL_MSIOF3_1)	FM(SEL_MSIOF3_2)	FM(SEL_MSIOF3_3)	FM(SEL_MSIOF3_4)	F_(0, 0)		F_(0, 0)		F_(0, 0)
-#define MOD_SEL0_28_27		FM(SEL_MSIOF2_0)	FM(SEL_MSIOF2_1)	FM(SEL_MSIOF2_2)	FM(SEL_MSIOF2_3)
-#define MOD_SEL0_26_25_24	FM(SEL_MSIOF1_0)	FM(SEL_MSIOF1_1)	FM(SEL_MSIOF1_2)	FM(SEL_MSIOF1_3)	FM(SEL_MSIOF1_4)	FM(SEL_MSIOF1_5)	FM(SEL_MSIOF1_6)	F_(0, 0)
-#define MOD_SEL0_23		FM(SEL_LBSC_0)		FM(SEL_LBSC_1)
-#define MOD_SEL0_22		FM(SEL_IEBUS_0)		FM(SEL_IEBUS_1)
-#define MOD_SEL0_21		FM(SEL_I2C2_0)		FM(SEL_I2C2_1)
-#define MOD_SEL0_20		FM(SEL_I2C1_0)		FM(SEL_I2C1_1)
-#define MOD_SEL0_19		FM(SEL_HSCIF4_0)	FM(SEL_HSCIF4_1)
-#define MOD_SEL0_18_17		FM(SEL_HSCIF3_0)	FM(SEL_HSCIF3_1)	FM(SEL_HSCIF3_2)	FM(SEL_HSCIF3_3)
-#define MOD_SEL0_16		FM(SEL_HSCIF1_0)	FM(SEL_HSCIF1_1)
-#define MOD_SEL0_14_13		FM(SEL_HSCIF2_0)	FM(SEL_HSCIF2_1)	FM(SEL_HSCIF2_2)	F_(0, 0)
-#define MOD_SEL0_12		FM(SEL_ETHERAVB_0)	FM(SEL_ETHERAVB_1)
-#define MOD_SEL0_11		FM(SEL_DRIF3_0)		FM(SEL_DRIF3_1)
-#define MOD_SEL0_10		FM(SEL_DRIF2_0)		FM(SEL_DRIF2_1)
-#define MOD_SEL0_9_8		FM(SEL_DRIF1_0)		FM(SEL_DRIF1_1)		FM(SEL_DRIF1_2)		F_(0, 0)
-#define MOD_SEL0_7_6		FM(SEL_DRIF0_0)		FM(SEL_DRIF0_1)		FM(SEL_DRIF0_2)		F_(0, 0)
-#define MOD_SEL0_5		FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
-#define MOD_SEL0_4_3		FM(SEL_ADGA_0)		FM(SEL_ADGA_1)		FM(SEL_ADGA_2)		FM(SEL_ADGA_3)
-
-/* MOD_SEL1 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
-#define MOD_SEL1_31_30		FM(SEL_TSIF1_0)		FM(SEL_TSIF1_1)		FM(SEL_TSIF1_2)		FM(SEL_TSIF1_3)
-#define MOD_SEL1_29_28_27	FM(SEL_TSIF0_0)		FM(SEL_TSIF0_1)		FM(SEL_TSIF0_2)		FM(SEL_TSIF0_3)		FM(SEL_TSIF0_4)		F_(0, 0)		F_(0, 0)		F_(0, 0)
-#define MOD_SEL1_26		FM(SEL_TIMER_TMU_0)	FM(SEL_TIMER_TMU_1)
-#define MOD_SEL1_25_24		FM(SEL_SSP1_1_0)	FM(SEL_SSP1_1_1)	FM(SEL_SSP1_1_2)	FM(SEL_SSP1_1_3)
-#define MOD_SEL1_23_22_21	FM(SEL_SSP1_0_0)	FM(SEL_SSP1_0_1)	FM(SEL_SSP1_0_2)	FM(SEL_SSP1_0_3)	FM(SEL_SSP1_0_4)	F_(0, 0)		F_(0, 0)		F_(0, 0)
-#define MOD_SEL1_20		FM(SEL_SSI1_0)		FM(SEL_SSI1_1)
-#define MOD_SEL1_19		FM(SEL_SPEED_PULSE_0)	FM(SEL_SPEED_PULSE_1)
-#define MOD_SEL1_18_17		FM(SEL_SIMCARD_0)	FM(SEL_SIMCARD_1)	FM(SEL_SIMCARD_2)	FM(SEL_SIMCARD_3)
-#define MOD_SEL1_16		FM(SEL_SDHI2_0)		FM(SEL_SDHI2_1)
-#define MOD_SEL1_15_14		FM(SEL_SCIF4_0)		FM(SEL_SCIF4_1)		FM(SEL_SCIF4_2)		F_(0, 0)
-#define MOD_SEL1_13		FM(SEL_SCIF3_0)		FM(SEL_SCIF3_1)
-#define MOD_SEL1_12		FM(SEL_SCIF2_0)		FM(SEL_SCIF2_1)
-#define MOD_SEL1_11		FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
-#define MOD_SEL1_10		FM(SEL_SCIF_0)		FM(SEL_SCIF_1)
-#define MOD_SEL1_9		FM(SEL_REMOCON_0)	FM(SEL_REMOCON_1)
-#define MOD_SEL1_6		FM(SEL_RCAN0_0)		FM(SEL_RCAN0_1)
-#define MOD_SEL1_5		FM(SEL_PWM6_0)		FM(SEL_PWM6_1)
-#define MOD_SEL1_4		FM(SEL_PWM5_0)		FM(SEL_PWM5_1)
-#define MOD_SEL1_3		FM(SEL_PWM4_0)		FM(SEL_PWM4_1)
-#define MOD_SEL1_2		FM(SEL_PWM3_0)		FM(SEL_PWM3_1)
-#define MOD_SEL1_1		FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
-#define MOD_SEL1_0		FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
-
-/* MOD_SEL2 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
-#define MOD_SEL2_31		FM(I2C_SEL_5_0)		FM(I2C_SEL_5_1)
-#define MOD_SEL2_30		FM(I2C_SEL_3_0)		FM(I2C_SEL_3_1)
-#define MOD_SEL2_29		FM(I2C_SEL_0_0)		FM(I2C_SEL_0_1)
-#define MOD_SEL2_28_27		FM(SEL_FM_0)		FM(SEL_FM_1)		FM(SEL_FM_2)		FM(SEL_FM_3)
-#define MOD_SEL2_26		FM(SEL_SCIF5_0)		FM(SEL_SCIF5_1)
-#define MOD_SEL2_25_24_23	FM(SEL_I2C6_0)		FM(SEL_I2C6_1)		FM(SEL_I2C6_2)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)
-#define MOD_SEL2_22		FM(SEL_NDF_0)		FM(SEL_NDF_1)
-#define MOD_SEL2_21		FM(SEL_SSI2_0)		FM(SEL_SSI2_1)
-#define MOD_SEL2_20		FM(SEL_SSI9_0)		FM(SEL_SSI9_1)
-#define MOD_SEL2_19		FM(SEL_TIMER_TMU2_0)	FM(SEL_TIMER_TMU2_1)
-#define MOD_SEL2_18		FM(SEL_ADGB_0)		FM(SEL_ADGB_1)
-#define MOD_SEL2_17		FM(SEL_ADGC_0)		FM(SEL_ADGC_1)
-#define MOD_SEL2_0		FM(SEL_VIN4_0)		FM(SEL_VIN4_1)
-
-#define PINMUX_MOD_SELS	\
-\
-MOD_SEL0_31_30_29	MOD_SEL1_31_30		MOD_SEL2_31 \
-						MOD_SEL2_30 \
-			MOD_SEL1_29_28_27	MOD_SEL2_29 \
-MOD_SEL0_28_27					MOD_SEL2_28_27 \
-MOD_SEL0_26_25_24	MOD_SEL1_26		MOD_SEL2_26 \
-			MOD_SEL1_25_24		MOD_SEL2_25_24_23 \
-MOD_SEL0_23		MOD_SEL1_23_22_21 \
-MOD_SEL0_22					MOD_SEL2_22 \
-MOD_SEL0_21					MOD_SEL2_21 \
-MOD_SEL0_20		MOD_SEL1_20		MOD_SEL2_20 \
-MOD_SEL0_19		MOD_SEL1_19		MOD_SEL2_19 \
-MOD_SEL0_18_17		MOD_SEL1_18_17		MOD_SEL2_18 \
-						MOD_SEL2_17 \
-MOD_SEL0_16		MOD_SEL1_16 \
-			MOD_SEL1_15_14 \
-MOD_SEL0_14_13 \
-			MOD_SEL1_13 \
-MOD_SEL0_12		MOD_SEL1_12 \
-MOD_SEL0_11		MOD_SEL1_11 \
-MOD_SEL0_10		MOD_SEL1_10 \
-MOD_SEL0_9_8		MOD_SEL1_9 \
-MOD_SEL0_7_6 \
-			MOD_SEL1_6 \
-MOD_SEL0_5		MOD_SEL1_5 \
-MOD_SEL0_4_3		MOD_SEL1_4 \
-			MOD_SEL1_3 \
-			MOD_SEL1_2 \
-			MOD_SEL1_1 \
-			MOD_SEL1_0		MOD_SEL2_0
-
-/*
- * These pins are not able to be muxed but have other properties
- * that can be set, such as drive-strength or pull-up/pull-down enable.
- */
-#define PINMUX_STATIC \
-	FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
-	FM(QSPI0_IO2) FM(QSPI0_IO3) \
-	FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
-	FM(QSPI1_IO2) FM(QSPI1_IO3) \
-	FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
-	FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
-	FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
-	FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
-	FM(PRESETOUT) \
-	FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
-	FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
-
-#define PINMUX_PHYS \
-	FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	GP_ALL(DATA),
-	PINMUX_DATA_END,
-
-#define F_(x, y)
-#define FM(x)	FN_##x,
-	PINMUX_FUNCTION_BEGIN,
-	GP_ALL(FN),
-	PINMUX_GPSR
-	PINMUX_IPSR
-	PINMUX_MOD_SELS
-	PINMUX_FUNCTION_END,
-#undef F_
-#undef FM
-
-#define F_(x, y)
-#define FM(x)	x##_MARK,
-	PINMUX_MARK_BEGIN,
-	PINMUX_GPSR
-	PINMUX_IPSR
-	PINMUX_MOD_SELS
-	PINMUX_STATIC
-	PINMUX_PHYS
-	PINMUX_MARK_END,
-#undef F_
-#undef FM
-};
-
-static const u16 pinmux_data[] = {
-	PINMUX_DATA_GP_ALL(),
-
-	PINMUX_SINGLE(AVS1),
-	PINMUX_SINGLE(AVS2),
-	PINMUX_SINGLE(CLKOUT),
-	PINMUX_SINGLE(GP7_03),
-	PINMUX_SINGLE(GP7_02),
-	PINMUX_SINGLE(MSIOF0_RXD),
-	PINMUX_SINGLE(MSIOF0_SCK),
-	PINMUX_SINGLE(MSIOF0_TXD),
-	PINMUX_SINGLE(SSI_SCK5),
-	PINMUX_SINGLE(SSI_SDATA5),
-	PINMUX_SINGLE(SSI_WS5),
-
-	/* IPSR0 */
-	PINMUX_IPSR_GPSR(IP0_3_0,	AVB_MDC),
-	PINMUX_IPSR_MSEL(IP0_3_0,	MSIOF2_SS2_C,		SEL_MSIOF2_2),
-
-	PINMUX_IPSR_GPSR(IP0_7_4,	AVB_MAGIC),
-	PINMUX_IPSR_MSEL(IP0_7_4,	MSIOF2_SS1_C,		SEL_MSIOF2_2),
-	PINMUX_IPSR_MSEL(IP0_7_4,	SCK4_A,			SEL_SCIF4_0),
-
-	PINMUX_IPSR_GPSR(IP0_11_8,	AVB_PHY_INT),
-	PINMUX_IPSR_MSEL(IP0_11_8,	MSIOF2_SYNC_C,		SEL_MSIOF2_2),
-	PINMUX_IPSR_MSEL(IP0_11_8,	RX4_A,			SEL_SCIF4_0),
-
-	PINMUX_IPSR_GPSR(IP0_15_12,	AVB_LINK),
-	PINMUX_IPSR_MSEL(IP0_15_12,	MSIOF2_SCK_C,		SEL_MSIOF2_2),
-	PINMUX_IPSR_MSEL(IP0_15_12,	TX4_A,			SEL_SCIF4_0),
-	PINMUX_IPSR_GPSR(IP0_19_16,	FSCLKST2_N_A),
-
-	PINMUX_IPSR_PHYS_MSEL(IP0_19_16,	AVB_AVTP_MATCH_A,	I2C_SEL_5_0, SEL_ETHERAVB_0),
-	PINMUX_IPSR_PHYS_MSEL(IP0_19_16,	MSIOF2_RXD_C,	I2C_SEL_5_0, SEL_MSIOF2_2),
-	PINMUX_IPSR_PHYS_MSEL(IP0_19_16,	CTS4_N_A,	I2C_SEL_5_0, SEL_SCIF4_0),
-	PINMUX_IPSR_PHYS(IP0_19_16,	SCL5,			I2C_SEL_5_1),
-
-	PINMUX_IPSR_PHYS_MSEL(IP0_23_20,	AVB_AVTP_CAPTURE_A,	I2C_SEL_5_0, SEL_ETHERAVB_0),
-	PINMUX_IPSR_PHYS_MSEL(IP0_23_20,	MSIOF2_TXD_C,		I2C_SEL_5_0, SEL_MSIOF2_2),
-	PINMUX_IPSR_PHYS_MSEL(IP0_23_20,	RTS4_N_A,		I2C_SEL_5_0, SEL_SCIF4_0),
-	PINMUX_IPSR_PHYS(IP0_23_20,	SDA5,			I2C_SEL_5_1),
-
-	PINMUX_IPSR_GPSR(IP0_27_24,	IRQ0),
-	PINMUX_IPSR_GPSR(IP0_27_24,	QPOLB),
-	PINMUX_IPSR_GPSR(IP0_27_24,	DU_CDE),
-	PINMUX_IPSR_MSEL(IP0_27_24,	VI4_DATA0_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP0_27_24,	CAN0_TX_B,		SEL_RCAN0_1),
-	PINMUX_IPSR_MSEL(IP0_27_24,	CANFD0_TX_B,		SEL_CANFD0_1),
-	PINMUX_IPSR_MSEL(IP0_27_24,	MSIOF3_SS2_E,		SEL_MSIOF3_4),
-
-	PINMUX_IPSR_GPSR(IP0_31_28,	IRQ1),
-	PINMUX_IPSR_GPSR(IP0_31_28,	QPOLA),
-	PINMUX_IPSR_GPSR(IP0_31_28,	DU_DISP),
-	PINMUX_IPSR_MSEL(IP0_31_28,	VI4_DATA1_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP0_31_28,	CAN0_RX_B,		SEL_RCAN0_1),
-	PINMUX_IPSR_MSEL(IP0_31_28,	CANFD0_RX_B,		SEL_CANFD0_1),
-	PINMUX_IPSR_MSEL(IP0_31_28,	MSIOF3_SS1_E,		SEL_MSIOF3_4),
-
-	/* IPSR1 */
-	PINMUX_IPSR_GPSR(IP1_3_0,	IRQ2),
-	PINMUX_IPSR_GPSR(IP1_3_0,	QCPV_QDE),
-	PINMUX_IPSR_GPSR(IP1_3_0,	DU_EXODDF_DU_ODDF_DISP_CDE),
-	PINMUX_IPSR_MSEL(IP1_3_0,	VI4_DATA2_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP1_3_0,	PWM3_B,			SEL_PWM3_1),
-	PINMUX_IPSR_MSEL(IP1_3_0,	MSIOF3_SYNC_E,		SEL_MSIOF3_4),
-
-	PINMUX_IPSR_GPSR(IP1_7_4,	IRQ3),
-	PINMUX_IPSR_GPSR(IP1_7_4,	QSTVB_QVE),
-	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DOTCLKOUT1),
-	PINMUX_IPSR_MSEL(IP1_7_4,	VI4_DATA3_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP1_7_4,	PWM4_B,			SEL_PWM4_1),
-	PINMUX_IPSR_MSEL(IP1_7_4,	MSIOF3_SCK_E,		SEL_MSIOF3_4),
-
-	PINMUX_IPSR_GPSR(IP1_11_8,	IRQ4),
-	PINMUX_IPSR_GPSR(IP1_11_8,	QSTH_QHS),
-	PINMUX_IPSR_GPSR(IP1_11_8,	DU_EXHSYNC_DU_HSYNC),
-	PINMUX_IPSR_MSEL(IP1_11_8,	VI4_DATA4_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP1_11_8,	PWM5_B,			SEL_PWM5_1),
-	PINMUX_IPSR_MSEL(IP1_11_8,	MSIOF3_RXD_E,		SEL_MSIOF3_4),
-
-	PINMUX_IPSR_GPSR(IP1_15_12,	IRQ5),
-	PINMUX_IPSR_GPSR(IP1_15_12,	QSTB_QHE),
-	PINMUX_IPSR_GPSR(IP1_15_12,	DU_EXVSYNC_DU_VSYNC),
-	PINMUX_IPSR_MSEL(IP1_15_12,	VI4_DATA5_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP1_15_12,	PWM6_B,			SEL_PWM6_1),
-	PINMUX_IPSR_GPSR(IP1_15_12,	FSCLKST2_N_B),
-	PINMUX_IPSR_MSEL(IP1_15_12,	MSIOF3_TXD_E,		SEL_MSIOF3_4),
-
-	PINMUX_IPSR_GPSR(IP1_19_16,	PWM0),
-	PINMUX_IPSR_GPSR(IP1_19_16,	AVB_AVTP_PPS),
-	PINMUX_IPSR_MSEL(IP1_19_16,	VI4_DATA6_B,		SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP1_19_16,	IECLK_B,		SEL_IEBUS_1),
-
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20,	PWM1_A,		I2C_SEL_3_0,	SEL_PWM1_0),
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20,	HRX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20,	VI4_DATA7_B,	I2C_SEL_3_0,	SEL_VIN4_1),
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20,	IERX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
-	PINMUX_IPSR_PHYS(IP1_23_20,	SCL3,		I2C_SEL_3_1),
-
-	PINMUX_IPSR_PHYS_MSEL(IP1_27_24,	PWM2_A,		I2C_SEL_3_0,	SEL_PWM2_0),
-	PINMUX_IPSR_PHYS_MSEL(IP1_27_24,	HTX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
-	PINMUX_IPSR_PHYS_MSEL(IP1_27_24,	IETX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
-	PINMUX_IPSR_PHYS(IP1_27_24,	SDA3,		I2C_SEL_3_1),
-
-	PINMUX_IPSR_GPSR(IP1_31_28,	A0),
-	PINMUX_IPSR_GPSR(IP1_31_28,	LCDOUT16),
-	PINMUX_IPSR_MSEL(IP1_31_28,	MSIOF3_SYNC_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP1_31_28,	VI4_DATA8),
-	PINMUX_IPSR_GPSR(IP1_31_28,	DU_DB0),
-	PINMUX_IPSR_MSEL(IP1_31_28,	PWM3_A,			SEL_PWM3_0),
-
-	/* IPSR2 */
-	PINMUX_IPSR_GPSR(IP2_3_0,	A1),
-	PINMUX_IPSR_GPSR(IP2_3_0,	LCDOUT17),
-	PINMUX_IPSR_MSEL(IP2_3_0,	MSIOF3_TXD_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP2_3_0,	VI4_DATA9),
-	PINMUX_IPSR_GPSR(IP2_3_0,	DU_DB1),
-	PINMUX_IPSR_MSEL(IP2_3_0,	PWM4_A,			SEL_PWM4_0),
-
-	PINMUX_IPSR_GPSR(IP2_7_4,	A2),
-	PINMUX_IPSR_GPSR(IP2_7_4,	LCDOUT18),
-	PINMUX_IPSR_MSEL(IP2_7_4,	MSIOF3_SCK_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP2_7_4,	VI4_DATA10),
-	PINMUX_IPSR_GPSR(IP2_7_4,	DU_DB2),
-	PINMUX_IPSR_MSEL(IP2_7_4,	PWM5_A,			SEL_PWM5_0),
-
-	PINMUX_IPSR_GPSR(IP2_11_8,	A3),
-	PINMUX_IPSR_GPSR(IP2_11_8,	LCDOUT19),
-	PINMUX_IPSR_MSEL(IP2_11_8,	MSIOF3_RXD_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP2_11_8,	VI4_DATA11),
-	PINMUX_IPSR_GPSR(IP2_11_8,	DU_DB3),
-	PINMUX_IPSR_MSEL(IP2_11_8,	PWM6_A,			SEL_PWM6_0),
-
-	PINMUX_IPSR_GPSR(IP2_15_12,	A4),
-	PINMUX_IPSR_GPSR(IP2_15_12,	LCDOUT20),
-	PINMUX_IPSR_MSEL(IP2_15_12,	MSIOF3_SS1_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP2_15_12,	VI4_DATA12),
-	PINMUX_IPSR_GPSR(IP2_15_12,	VI5_DATA12),
-	PINMUX_IPSR_GPSR(IP2_15_12,	DU_DB4),
-
-	PINMUX_IPSR_GPSR(IP2_19_16,	A5),
-	PINMUX_IPSR_GPSR(IP2_19_16,	LCDOUT21),
-	PINMUX_IPSR_MSEL(IP2_19_16,	MSIOF3_SS2_B,		SEL_MSIOF3_1),
-	PINMUX_IPSR_MSEL(IP2_19_16,	SCK4_B,			SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP2_19_16,	VI4_DATA13),
-	PINMUX_IPSR_GPSR(IP2_19_16,	VI5_DATA13),
-	PINMUX_IPSR_GPSR(IP2_19_16,	DU_DB5),
-
-	PINMUX_IPSR_GPSR(IP2_23_20,	A6),
-	PINMUX_IPSR_GPSR(IP2_23_20,	LCDOUT22),
-	PINMUX_IPSR_MSEL(IP2_23_20,	MSIOF2_SS1_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP2_23_20,	RX4_B,			SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP2_23_20,	VI4_DATA14),
-	PINMUX_IPSR_GPSR(IP2_23_20,	VI5_DATA14),
-	PINMUX_IPSR_GPSR(IP2_23_20,	DU_DB6),
-
-	PINMUX_IPSR_GPSR(IP2_27_24,	A7),
-	PINMUX_IPSR_GPSR(IP2_27_24,	LCDOUT23),
-	PINMUX_IPSR_MSEL(IP2_27_24,	MSIOF2_SS2_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP2_27_24,	TX4_B,			SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP2_27_24,	VI4_DATA15),
-	PINMUX_IPSR_GPSR(IP2_27_24,	VI5_DATA15),
-	PINMUX_IPSR_GPSR(IP2_27_24,	DU_DB7),
-
-	PINMUX_IPSR_GPSR(IP2_31_28,	A8),
-	PINMUX_IPSR_MSEL(IP2_31_28,	RX3_B,			SEL_SCIF3_1),
-	PINMUX_IPSR_MSEL(IP2_31_28,	MSIOF2_SYNC_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP2_31_28,	HRX4_B,			SEL_HSCIF4_1),
-	PINMUX_IPSR_MSEL(IP2_31_28,	SDA6_A,			SEL_I2C6_0),
-	PINMUX_IPSR_MSEL(IP2_31_28,	AVB_AVTP_MATCH_B,	SEL_ETHERAVB_1),
-	PINMUX_IPSR_MSEL(IP2_31_28,	PWM1_B,			SEL_PWM1_1),
-
-	/* IPSR3 */
-	PINMUX_IPSR_GPSR(IP3_3_0,	A9),
-	PINMUX_IPSR_MSEL(IP3_3_0,	MSIOF2_SCK_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP3_3_0,	CTS4_N_B,		SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP3_3_0,	VI5_VSYNC_N),
-
-	PINMUX_IPSR_GPSR(IP3_7_4,	A10),
-	PINMUX_IPSR_MSEL(IP3_7_4,	MSIOF2_RXD_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP3_7_4,	RTS4_N_B,		SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP3_7_4,	VI5_HSYNC_N),
-
-	PINMUX_IPSR_GPSR(IP3_11_8,	A11),
-	PINMUX_IPSR_MSEL(IP3_11_8,	TX3_B,			SEL_SCIF3_1),
-	PINMUX_IPSR_MSEL(IP3_11_8,	MSIOF2_TXD_A,		SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP3_11_8,	HTX4_B,			SEL_HSCIF4_1),
-	PINMUX_IPSR_GPSR(IP3_11_8,	HSCK4),
-	PINMUX_IPSR_GPSR(IP3_11_8,	VI5_FIELD),
-	PINMUX_IPSR_MSEL(IP3_11_8,	SCL6_A,			SEL_I2C6_0),
-	PINMUX_IPSR_MSEL(IP3_11_8,	AVB_AVTP_CAPTURE_B,	SEL_ETHERAVB_1),
-	PINMUX_IPSR_MSEL(IP3_11_8,	PWM2_B,			SEL_PWM2_1),
-
-	PINMUX_IPSR_GPSR(IP3_15_12,	A12),
-	PINMUX_IPSR_GPSR(IP3_15_12,	LCDOUT12),
-	PINMUX_IPSR_MSEL(IP3_15_12,	MSIOF3_SCK_C,		SEL_MSIOF3_2),
-	PINMUX_IPSR_MSEL(IP3_15_12,	HRX4_A,			SEL_HSCIF4_0),
-	PINMUX_IPSR_GPSR(IP3_15_12,	VI5_DATA8),
-	PINMUX_IPSR_GPSR(IP3_15_12,	DU_DG4),
-
-	PINMUX_IPSR_GPSR(IP3_19_16,	A13),
-	PINMUX_IPSR_GPSR(IP3_19_16,	LCDOUT13),
-	PINMUX_IPSR_MSEL(IP3_19_16,	MSIOF3_SYNC_C,		SEL_MSIOF3_2),
-	PINMUX_IPSR_MSEL(IP3_19_16,	HTX4_A,			SEL_HSCIF4_0),
-	PINMUX_IPSR_GPSR(IP3_19_16,	VI5_DATA9),
-	PINMUX_IPSR_GPSR(IP3_19_16,	DU_DG5),
-
-	PINMUX_IPSR_GPSR(IP3_23_20,	A14),
-	PINMUX_IPSR_GPSR(IP3_23_20,	LCDOUT14),
-	PINMUX_IPSR_MSEL(IP3_23_20,	MSIOF3_RXD_C,		SEL_MSIOF3_2),
-	PINMUX_IPSR_GPSR(IP3_23_20,	HCTS4_N),
-	PINMUX_IPSR_GPSR(IP3_23_20,	VI5_DATA10),
-	PINMUX_IPSR_GPSR(IP3_23_20,	DU_DG6),
-
-	PINMUX_IPSR_GPSR(IP3_27_24,	A15),
-	PINMUX_IPSR_GPSR(IP3_27_24,	LCDOUT15),
-	PINMUX_IPSR_MSEL(IP3_27_24,	MSIOF3_TXD_C,		SEL_MSIOF3_2),
-	PINMUX_IPSR_GPSR(IP3_27_24,	HRTS4_N),
-	PINMUX_IPSR_GPSR(IP3_27_24,	VI5_DATA11),
-	PINMUX_IPSR_GPSR(IP3_27_24,	DU_DG7),
-
-	PINMUX_IPSR_GPSR(IP3_31_28,	A16),
-	PINMUX_IPSR_GPSR(IP3_31_28,	LCDOUT8),
-	PINMUX_IPSR_GPSR(IP3_31_28,	VI4_FIELD),
-	PINMUX_IPSR_GPSR(IP3_31_28,	DU_DG0),
-
-	/* IPSR4 */
-	PINMUX_IPSR_GPSR(IP4_3_0,	A17),
-	PINMUX_IPSR_GPSR(IP4_3_0,	LCDOUT9),
-	PINMUX_IPSR_GPSR(IP4_3_0,	VI4_VSYNC_N),
-	PINMUX_IPSR_GPSR(IP4_3_0,	DU_DG1),
-
-	PINMUX_IPSR_GPSR(IP4_7_4,	A18),
-	PINMUX_IPSR_GPSR(IP4_7_4,	LCDOUT10),
-	PINMUX_IPSR_GPSR(IP4_7_4,	VI4_HSYNC_N),
-	PINMUX_IPSR_GPSR(IP4_7_4,	DU_DG2),
-
-	PINMUX_IPSR_GPSR(IP4_11_8,	A19),
-	PINMUX_IPSR_GPSR(IP4_11_8,	LCDOUT11),
-	PINMUX_IPSR_GPSR(IP4_11_8,	VI4_CLKENB),
-	PINMUX_IPSR_GPSR(IP4_11_8,	DU_DG3),
-
-	PINMUX_IPSR_GPSR(IP4_15_12,	CS0_N),
-	PINMUX_IPSR_GPSR(IP4_15_12,	VI5_CLKENB),
-
-	PINMUX_IPSR_GPSR(IP4_19_16,	CS1_N),
-	PINMUX_IPSR_GPSR(IP4_19_16,	VI5_CLK),
-	PINMUX_IPSR_MSEL(IP4_19_16,	EX_WAIT0_B,		SEL_LBSC_1),
-
-	PINMUX_IPSR_GPSR(IP4_23_20,	BS_N),
-	PINMUX_IPSR_GPSR(IP4_23_20,	QSTVA_QVS),
-	PINMUX_IPSR_MSEL(IP4_23_20,	MSIOF3_SCK_D,		SEL_MSIOF3_3),
-	PINMUX_IPSR_GPSR(IP4_23_20,	SCK3),
-	PINMUX_IPSR_GPSR(IP4_23_20,	HSCK3),
-	PINMUX_IPSR_GPSR(IP4_23_20,	CAN1_TX),
-	PINMUX_IPSR_GPSR(IP4_23_20,	CANFD1_TX),
-	PINMUX_IPSR_MSEL(IP4_23_20,	IETX_A,			SEL_IEBUS_0),
-
-	PINMUX_IPSR_GPSR(IP4_27_24,	RD_N),
-	PINMUX_IPSR_MSEL(IP4_27_24,	MSIOF3_SYNC_D,		SEL_MSIOF3_3),
-	PINMUX_IPSR_MSEL(IP4_27_24,	RX3_A,			SEL_SCIF3_0),
-	PINMUX_IPSR_MSEL(IP4_27_24,	HRX3_A,			SEL_HSCIF3_0),
-	PINMUX_IPSR_MSEL(IP4_27_24,	CAN0_TX_A,		SEL_RCAN0_0),
-	PINMUX_IPSR_MSEL(IP4_27_24,	CANFD0_TX_A,		SEL_CANFD0_0),
-
-	PINMUX_IPSR_GPSR(IP4_31_28,	RD_WR_N),
-	PINMUX_IPSR_MSEL(IP4_31_28,	MSIOF3_RXD_D,		SEL_MSIOF3_3),
-	PINMUX_IPSR_MSEL(IP4_31_28,	TX3_A,			SEL_SCIF3_0),
-	PINMUX_IPSR_MSEL(IP4_31_28,	HTX3_A,			SEL_HSCIF3_0),
-	PINMUX_IPSR_MSEL(IP4_31_28,	CAN0_RX_A,		SEL_RCAN0_0),
-	PINMUX_IPSR_MSEL(IP4_31_28,	CANFD0_RX_A,		SEL_CANFD0_0),
-
-	/* IPSR5 */
-	PINMUX_IPSR_GPSR(IP5_3_0,	WE0_N),
-	PINMUX_IPSR_MSEL(IP5_3_0,	MSIOF3_TXD_D,		SEL_MSIOF3_3),
-	PINMUX_IPSR_GPSR(IP5_3_0,	CTS3_N),
-	PINMUX_IPSR_GPSR(IP5_3_0,	HCTS3_N),
-	PINMUX_IPSR_MSEL(IP5_3_0,	SCL6_B,			SEL_I2C6_1),
-	PINMUX_IPSR_GPSR(IP5_3_0,	CAN_CLK),
-	PINMUX_IPSR_MSEL(IP5_3_0,	IECLK_A,		SEL_IEBUS_0),
-
-	PINMUX_IPSR_GPSR(IP5_7_4,	WE1_N),
-	PINMUX_IPSR_MSEL(IP5_7_4,	MSIOF3_SS1_D,		SEL_MSIOF3_3),
-	PINMUX_IPSR_GPSR(IP5_7_4,	RTS3_N),
-	PINMUX_IPSR_GPSR(IP5_7_4,	HRTS3_N),
-	PINMUX_IPSR_MSEL(IP5_7_4,	SDA6_B,			SEL_I2C6_1),
-	PINMUX_IPSR_GPSR(IP5_7_4,	CAN1_RX),
-	PINMUX_IPSR_GPSR(IP5_7_4,	CANFD1_RX),
-	PINMUX_IPSR_MSEL(IP5_7_4,	IERX_A,			SEL_IEBUS_0),
-
-	PINMUX_IPSR_MSEL(IP5_11_8,	EX_WAIT0_A,		SEL_LBSC_0),
-	PINMUX_IPSR_GPSR(IP5_11_8,	QCLK),
-	PINMUX_IPSR_GPSR(IP5_11_8,	VI4_CLK),
-	PINMUX_IPSR_GPSR(IP5_11_8,	DU_DOTCLKOUT0),
-
-	PINMUX_IPSR_GPSR(IP5_15_12,	D0),
-	PINMUX_IPSR_MSEL(IP5_15_12,	MSIOF2_SS1_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_MSEL(IP5_15_12,	MSIOF3_SCK_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_GPSR(IP5_15_12,	VI4_DATA16),
-	PINMUX_IPSR_GPSR(IP5_15_12,	VI5_DATA0),
-
-	PINMUX_IPSR_GPSR(IP5_19_16,	D1),
-	PINMUX_IPSR_MSEL(IP5_19_16,	MSIOF2_SS2_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_MSEL(IP5_19_16,	MSIOF3_SYNC_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_GPSR(IP5_19_16,	VI4_DATA17),
-	PINMUX_IPSR_GPSR(IP5_19_16,	VI5_DATA1),
-
-	PINMUX_IPSR_GPSR(IP5_23_20,	D2),
-	PINMUX_IPSR_MSEL(IP5_23_20,	MSIOF3_RXD_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_GPSR(IP5_23_20,	VI4_DATA18),
-	PINMUX_IPSR_GPSR(IP5_23_20,	VI5_DATA2),
-
-	PINMUX_IPSR_GPSR(IP5_27_24,	D3),
-	PINMUX_IPSR_MSEL(IP5_27_24,	MSIOF3_TXD_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_GPSR(IP5_27_24,	VI4_DATA19),
-	PINMUX_IPSR_GPSR(IP5_27_24,	VI5_DATA3),
-
-	PINMUX_IPSR_GPSR(IP5_31_28,	D4),
-	PINMUX_IPSR_MSEL(IP5_31_28,	MSIOF2_SCK_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP5_31_28,	VI4_DATA20),
-	PINMUX_IPSR_GPSR(IP5_31_28,	VI5_DATA4),
-
-	/* IPSR6 */
-	PINMUX_IPSR_GPSR(IP6_3_0,	D5),
-	PINMUX_IPSR_MSEL(IP6_3_0,	MSIOF2_SYNC_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP6_3_0,	VI4_DATA21),
-	PINMUX_IPSR_GPSR(IP6_3_0,	VI5_DATA5),
-
-	PINMUX_IPSR_GPSR(IP6_7_4,	D6),
-	PINMUX_IPSR_MSEL(IP6_7_4,	MSIOF2_RXD_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP6_7_4,	VI4_DATA22),
-	PINMUX_IPSR_GPSR(IP6_7_4,	VI5_DATA6),
-
-	PINMUX_IPSR_GPSR(IP6_11_8,	D7),
-	PINMUX_IPSR_MSEL(IP6_11_8,	MSIOF2_TXD_B,		SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP6_11_8,	VI4_DATA23),
-	PINMUX_IPSR_GPSR(IP6_11_8,	VI5_DATA7),
-
-	PINMUX_IPSR_GPSR(IP6_15_12,	D8),
-	PINMUX_IPSR_GPSR(IP6_15_12,	LCDOUT0),
-	PINMUX_IPSR_MSEL(IP6_15_12,	MSIOF2_SCK_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP6_15_12,	SCK4_C,			SEL_SCIF4_2),
-	PINMUX_IPSR_MSEL(IP6_15_12,	VI4_DATA0_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP6_15_12,	DU_DR0),
-
-	PINMUX_IPSR_GPSR(IP6_19_16,	D9),
-	PINMUX_IPSR_GPSR(IP6_19_16,	LCDOUT1),
-	PINMUX_IPSR_MSEL(IP6_19_16,	MSIOF2_SYNC_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP6_19_16,	VI4_DATA1_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP6_19_16,	DU_DR1),
-
-	PINMUX_IPSR_GPSR(IP6_23_20,	D10),
-	PINMUX_IPSR_GPSR(IP6_23_20,	LCDOUT2),
-	PINMUX_IPSR_MSEL(IP6_23_20,	MSIOF2_RXD_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP6_23_20,	HRX3_B,			SEL_HSCIF3_1),
-	PINMUX_IPSR_MSEL(IP6_23_20,	VI4_DATA2_A,		SEL_VIN4_0),
-	PINMUX_IPSR_MSEL(IP6_23_20,	CTS4_N_C,		SEL_SCIF4_2),
-	PINMUX_IPSR_GPSR(IP6_23_20,	DU_DR2),
-
-	PINMUX_IPSR_GPSR(IP6_27_24,	D11),
-	PINMUX_IPSR_GPSR(IP6_27_24,	LCDOUT3),
-	PINMUX_IPSR_MSEL(IP6_27_24,	MSIOF2_TXD_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP6_27_24,	HTX3_B,			SEL_HSCIF3_1),
-	PINMUX_IPSR_MSEL(IP6_27_24,	VI4_DATA3_A,		SEL_VIN4_0),
-	PINMUX_IPSR_MSEL(IP6_27_24,	RTS4_N_C,		SEL_SCIF4_2),
-	PINMUX_IPSR_GPSR(IP6_27_24,	DU_DR3),
-
-	PINMUX_IPSR_GPSR(IP6_31_28,	D12),
-	PINMUX_IPSR_GPSR(IP6_31_28,	LCDOUT4),
-	PINMUX_IPSR_MSEL(IP6_31_28,	MSIOF2_SS1_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP6_31_28,	RX4_C,			SEL_SCIF4_2),
-	PINMUX_IPSR_MSEL(IP6_31_28,	VI4_DATA4_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP6_31_28,	DU_DR4),
-
-	/* IPSR7 */
-	PINMUX_IPSR_GPSR(IP7_3_0,	D13),
-	PINMUX_IPSR_GPSR(IP7_3_0,	LCDOUT5),
-	PINMUX_IPSR_MSEL(IP7_3_0,	MSIOF2_SS2_D,		SEL_MSIOF2_3),
-	PINMUX_IPSR_MSEL(IP7_3_0,	TX4_C,			SEL_SCIF4_2),
-	PINMUX_IPSR_MSEL(IP7_3_0,	VI4_DATA5_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP7_3_0,	DU_DR5),
-
-	PINMUX_IPSR_GPSR(IP7_7_4,	D14),
-	PINMUX_IPSR_GPSR(IP7_7_4,	LCDOUT6),
-	PINMUX_IPSR_MSEL(IP7_7_4,	MSIOF3_SS1_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_MSEL(IP7_7_4,	HRX3_C,			SEL_HSCIF3_2),
-	PINMUX_IPSR_MSEL(IP7_7_4,	VI4_DATA6_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP7_7_4,	DU_DR6),
-	PINMUX_IPSR_MSEL(IP7_7_4,	SCL6_C,			SEL_I2C6_2),
-
-	PINMUX_IPSR_GPSR(IP7_11_8,	D15),
-	PINMUX_IPSR_GPSR(IP7_11_8,	LCDOUT7),
-	PINMUX_IPSR_MSEL(IP7_11_8,	MSIOF3_SS2_A,		SEL_MSIOF3_0),
-	PINMUX_IPSR_MSEL(IP7_11_8,	HTX3_C,			SEL_HSCIF3_2),
-	PINMUX_IPSR_MSEL(IP7_11_8,	VI4_DATA7_A,		SEL_VIN4_0),
-	PINMUX_IPSR_GPSR(IP7_11_8,	DU_DR7),
-	PINMUX_IPSR_MSEL(IP7_11_8,	SDA6_C,			SEL_I2C6_2),
-
-	PINMUX_IPSR_GPSR(IP7_19_16,	SD0_CLK),
-	PINMUX_IPSR_MSEL(IP7_19_16,	MSIOF1_SCK_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP7_19_16,	STP_OPWM_0_B,		SEL_SSP1_0_1),
-
-	PINMUX_IPSR_GPSR(IP7_23_20,	SD0_CMD),
-	PINMUX_IPSR_MSEL(IP7_23_20,	MSIOF1_SYNC_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP7_23_20,	STP_IVCXO27_0_B,	SEL_SSP1_0_1),
-
-	PINMUX_IPSR_GPSR(IP7_27_24,	SD0_DAT0),
-	PINMUX_IPSR_MSEL(IP7_27_24,	MSIOF1_RXD_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP7_27_24,	TS_SCK0_B,		SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP7_27_24,	STP_ISCLK_0_B,		SEL_SSP1_0_1),
-
-	PINMUX_IPSR_GPSR(IP7_31_28,	SD0_DAT1),
-	PINMUX_IPSR_MSEL(IP7_31_28,	MSIOF1_TXD_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP7_31_28,	TS_SPSYNC0_B,		SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP7_31_28,	STP_ISSYNC_0_B,		SEL_SSP1_0_1),
-
-	/* IPSR8 */
-	PINMUX_IPSR_GPSR(IP8_3_0,	SD0_DAT2),
-	PINMUX_IPSR_MSEL(IP8_3_0,	MSIOF1_SS1_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP8_3_0,	TS_SDAT0_B,		SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP8_3_0,	STP_ISD_0_B,		SEL_SSP1_0_1),
-
-	PINMUX_IPSR_GPSR(IP8_7_4,	SD0_DAT3),
-	PINMUX_IPSR_MSEL(IP8_7_4,	MSIOF1_SS2_E,		SEL_MSIOF1_4),
-	PINMUX_IPSR_MSEL(IP8_7_4,	TS_SDEN0_B,		SEL_TSIF0_1),
-	PINMUX_IPSR_MSEL(IP8_7_4,	STP_ISEN_0_B,		SEL_SSP1_0_1),
-
-	PINMUX_IPSR_GPSR(IP8_11_8,	SD1_CLK),
-	PINMUX_IPSR_MSEL(IP8_11_8,	MSIOF1_SCK_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_MSEL(IP8_11_8,	SIM0_CLK_A,		SEL_SIMCARD_0),
-
-	PINMUX_IPSR_GPSR(IP8_15_12,	SD1_CMD),
-	PINMUX_IPSR_MSEL(IP8_15_12,	MSIOF1_SYNC_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_MSEL(IP8_15_12,	NFCE_N_B,		SEL_NDF_1),
-	PINMUX_IPSR_MSEL(IP8_15_12,	SIM0_D_A,		SEL_SIMCARD_0),
-	PINMUX_IPSR_MSEL(IP8_15_12,	STP_IVCXO27_1_B,	SEL_SSP1_1_1),
-
-	PINMUX_IPSR_GPSR(IP8_19_16,	SD1_DAT0),
-	PINMUX_IPSR_GPSR(IP8_19_16,	SD2_DAT4),
-	PINMUX_IPSR_MSEL(IP8_19_16,	MSIOF1_RXD_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_MSEL(IP8_19_16,	NFWP_N_B,		SEL_NDF_1),
-	PINMUX_IPSR_MSEL(IP8_19_16,	TS_SCK1_B,		SEL_TSIF1_1),
-	PINMUX_IPSR_MSEL(IP8_19_16,	STP_ISCLK_1_B,		SEL_SSP1_1_1),
-
-	PINMUX_IPSR_GPSR(IP8_23_20,	SD1_DAT1),
-	PINMUX_IPSR_GPSR(IP8_23_20,	SD2_DAT5),
-	PINMUX_IPSR_MSEL(IP8_23_20,	MSIOF1_TXD_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_MSEL(IP8_23_20,	NFDATA14_B,		SEL_NDF_1),
-	PINMUX_IPSR_MSEL(IP8_23_20,	TS_SPSYNC1_B,		SEL_TSIF1_1),
-	PINMUX_IPSR_MSEL(IP8_23_20,	STP_ISSYNC_1_B,		SEL_SSP1_1_1),
-
-	PINMUX_IPSR_GPSR(IP8_27_24,	SD1_DAT2),
-	PINMUX_IPSR_GPSR(IP8_27_24,	SD2_DAT6),
-	PINMUX_IPSR_MSEL(IP8_27_24,	MSIOF1_SS1_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_MSEL(IP8_27_24,	NFDATA15_B,		SEL_NDF_1),
-	PINMUX_IPSR_MSEL(IP8_27_24,	TS_SDAT1_B,		SEL_TSIF1_1),
-	PINMUX_IPSR_MSEL(IP8_27_24,	STP_ISD_1_B,		SEL_SSP1_1_1),
-
-	PINMUX_IPSR_GPSR(IP8_31_28,	SD1_DAT3),
-	PINMUX_IPSR_GPSR(IP8_31_28,	SD2_DAT7),
-	PINMUX_IPSR_MSEL(IP8_31_28,	MSIOF1_SS2_G,		SEL_MSIOF1_6),
-	PINMUX_IPSR_MSEL(IP8_31_28,	NFRB_N_B,		SEL_NDF_1),
-	PINMUX_IPSR_MSEL(IP8_31_28,	TS_SDEN1_B,		SEL_TSIF1_1),
-	PINMUX_IPSR_MSEL(IP8_31_28,	STP_ISEN_1_B,		SEL_SSP1_1_1),
-
-	/* IPSR9 */
-	PINMUX_IPSR_GPSR(IP9_3_0,	SD2_CLK),
-	PINMUX_IPSR_GPSR(IP9_3_0,	NFDATA8),
-
-	PINMUX_IPSR_GPSR(IP9_7_4,	SD2_CMD),
-	PINMUX_IPSR_GPSR(IP9_7_4,	NFDATA9),
-
-	PINMUX_IPSR_GPSR(IP9_11_8,	SD2_DAT0),
-	PINMUX_IPSR_GPSR(IP9_11_8,	NFDATA10),
-
-	PINMUX_IPSR_GPSR(IP9_15_12,	SD2_DAT1),
-	PINMUX_IPSR_GPSR(IP9_15_12,	NFDATA11),
-
-	PINMUX_IPSR_GPSR(IP9_19_16,	SD2_DAT2),
-	PINMUX_IPSR_GPSR(IP9_19_16,	NFDATA12),
-
-	PINMUX_IPSR_GPSR(IP9_23_20,	SD2_DAT3),
-	PINMUX_IPSR_GPSR(IP9_23_20,	NFDATA13),
-
-	PINMUX_IPSR_GPSR(IP9_27_24,	SD2_DS),
-	PINMUX_IPSR_GPSR(IP9_27_24,	NFALE),
-	PINMUX_IPSR_GPSR(IP9_27_24,	SATA_DEVSLP_B),
-
-	PINMUX_IPSR_GPSR(IP9_31_28,	SD3_CLK),
-	PINMUX_IPSR_GPSR(IP9_31_28,	NFWE_N),
-
-	/* IPSR10 */
-	PINMUX_IPSR_GPSR(IP10_3_0,	SD3_CMD),
-	PINMUX_IPSR_GPSR(IP10_3_0,	NFRE_N),
-
-	PINMUX_IPSR_GPSR(IP10_7_4,	SD3_DAT0),
-	PINMUX_IPSR_GPSR(IP10_7_4,	NFDATA0),
-
-	PINMUX_IPSR_GPSR(IP10_11_8,	SD3_DAT1),
-	PINMUX_IPSR_GPSR(IP10_11_8,	NFDATA1),
-
-	PINMUX_IPSR_GPSR(IP10_15_12,	SD3_DAT2),
-	PINMUX_IPSR_GPSR(IP10_15_12,	NFDATA2),
-
-	PINMUX_IPSR_GPSR(IP10_19_16,	SD3_DAT3),
-	PINMUX_IPSR_GPSR(IP10_19_16,	NFDATA3),
-
-	PINMUX_IPSR_GPSR(IP10_23_20,	SD3_DAT4),
-	PINMUX_IPSR_MSEL(IP10_23_20,	SD2_CD_A,		SEL_SDHI2_0),
-	PINMUX_IPSR_GPSR(IP10_23_20,	NFDATA4),
-
-	PINMUX_IPSR_GPSR(IP10_27_24,	SD3_DAT5),
-	PINMUX_IPSR_MSEL(IP10_27_24,	SD2_WP_A,		SEL_SDHI2_0),
-	PINMUX_IPSR_GPSR(IP10_27_24,	NFDATA5),
-
-	PINMUX_IPSR_GPSR(IP10_31_28,	SD3_DAT6),
-	PINMUX_IPSR_GPSR(IP10_31_28,	SD3_CD),
-	PINMUX_IPSR_GPSR(IP10_31_28,	NFDATA6),
-
-	/* IPSR11 */
-	PINMUX_IPSR_GPSR(IP11_3_0,	SD3_DAT7),
-	PINMUX_IPSR_GPSR(IP11_3_0,	SD3_WP),
-	PINMUX_IPSR_GPSR(IP11_3_0,	NFDATA7),
-
-	PINMUX_IPSR_GPSR(IP11_7_4,	SD3_DS),
-	PINMUX_IPSR_GPSR(IP11_7_4,	NFCLE),
-
-	PINMUX_IPSR_GPSR(IP11_11_8,	SD0_CD),
-	PINMUX_IPSR_MSEL(IP11_11_8,	NFDATA14_A,		SEL_NDF_0),
-	PINMUX_IPSR_MSEL(IP11_11_8,	SCL2_B,			SEL_I2C2_1),
-	PINMUX_IPSR_MSEL(IP11_11_8,	SIM0_RST_A,		SEL_SIMCARD_0),
-
-	PINMUX_IPSR_GPSR(IP11_15_12,	SD0_WP),
-	PINMUX_IPSR_MSEL(IP11_15_12,	NFDATA15_A,		SEL_NDF_0),
-	PINMUX_IPSR_MSEL(IP11_15_12,	SDA2_B,			SEL_I2C2_1),
-
-	PINMUX_IPSR_MSEL(IP11_19_16,	SD1_CD,			I2C_SEL_0_0),
-	PINMUX_IPSR_PHYS_MSEL(IP11_19_16,	NFRB_N_A,	I2C_SEL_0_0, SEL_NDF_0),
-	PINMUX_IPSR_PHYS_MSEL(IP11_19_16,	SIM0_CLK_B,	I2C_SEL_0_0, SEL_SIMCARD_1),
-	PINMUX_IPSR_PHYS(IP11_19_16,	SCL0,			I2C_SEL_0_1),
-
-	PINMUX_IPSR_MSEL(IP11_23_20,	SD1_WP,			I2C_SEL_0_0),
-	PINMUX_IPSR_PHYS_MSEL(IP11_23_20,	NFCE_N_A,	I2C_SEL_0_0, SEL_NDF_0),
-	PINMUX_IPSR_PHYS_MSEL(IP11_23_20,	SIM0_D_B,	I2C_SEL_0_0, SEL_SIMCARD_1),
-	PINMUX_IPSR_PHYS(IP11_23_20,	SDA0,			I2C_SEL_0_1),
-
-	PINMUX_IPSR_GPSR(IP11_27_24,	SCK0),
-	PINMUX_IPSR_MSEL(IP11_27_24,	HSCK1_B,		SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP11_27_24,	MSIOF1_SS2_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP11_27_24,	AUDIO_CLKC_B,		SEL_ADGC_1),
-	PINMUX_IPSR_MSEL(IP11_27_24,	SDA2_A,			SEL_I2C2_0),
-	PINMUX_IPSR_MSEL(IP11_27_24,	SIM0_RST_B,		SEL_SIMCARD_1),
-	PINMUX_IPSR_MSEL(IP11_27_24,	STP_OPWM_0_C,		SEL_SSP1_0_2),
-	PINMUX_IPSR_MSEL(IP11_27_24,	RIF0_CLK_B,		SEL_DRIF0_1),
-	PINMUX_IPSR_GPSR(IP11_27_24,	ADICHS2),
-	PINMUX_IPSR_MSEL(IP11_27_24,	SCK5_B,			SEL_SCIF5_1),
-
-	PINMUX_IPSR_GPSR(IP11_31_28,	RX0),
-	PINMUX_IPSR_MSEL(IP11_31_28,	HRX1_B,			SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP11_31_28,	TS_SCK0_C,		SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP11_31_28,	STP_ISCLK_0_C,		SEL_SSP1_0_2),
-	PINMUX_IPSR_MSEL(IP11_31_28,	RIF0_D0_B,		SEL_DRIF0_1),
-
-	/* IPSR12 */
-	PINMUX_IPSR_GPSR(IP12_3_0,	TX0),
-	PINMUX_IPSR_MSEL(IP12_3_0,	HTX1_B,			SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP12_3_0,	TS_SPSYNC0_C,		SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP12_3_0,	STP_ISSYNC_0_C,		SEL_SSP1_0_2),
-	PINMUX_IPSR_MSEL(IP12_3_0,	RIF0_D1_B,		SEL_DRIF0_1),
-
-	PINMUX_IPSR_GPSR(IP12_7_4,	CTS0_N),
-	PINMUX_IPSR_MSEL(IP12_7_4,	HCTS1_N_B,		SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP12_7_4,	MSIOF1_SYNC_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP12_7_4,	TS_SPSYNC1_C,		SEL_TSIF1_2),
-	PINMUX_IPSR_MSEL(IP12_7_4,	STP_ISSYNC_1_C,		SEL_SSP1_1_2),
-	PINMUX_IPSR_MSEL(IP12_7_4,	RIF1_SYNC_B,		SEL_DRIF1_1),
-	PINMUX_IPSR_GPSR(IP12_7_4,	AUDIO_CLKOUT_C),
-	PINMUX_IPSR_GPSR(IP12_7_4,	ADICS_SAMP),
-
-	PINMUX_IPSR_GPSR(IP12_11_8,	RTS0_N),
-	PINMUX_IPSR_MSEL(IP12_11_8,	HRTS1_N_B,		SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP12_11_8,	MSIOF1_SS1_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP12_11_8,	AUDIO_CLKA_B,		SEL_ADGA_1),
-	PINMUX_IPSR_MSEL(IP12_11_8,	SCL2_A,			SEL_I2C2_0),
-	PINMUX_IPSR_MSEL(IP12_11_8,	STP_IVCXO27_1_C,	SEL_SSP1_1_2),
-	PINMUX_IPSR_MSEL(IP12_11_8,	RIF0_SYNC_B,		SEL_DRIF0_1),
-	PINMUX_IPSR_GPSR(IP12_11_8,	ADICHS1),
-
-	PINMUX_IPSR_MSEL(IP12_15_12,	RX1_A,			SEL_SCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_15_12,	HRX1_A,			SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_15_12,	TS_SDAT0_C,		SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP12_15_12,	STP_ISD_0_C,		SEL_SSP1_0_2),
-	PINMUX_IPSR_MSEL(IP12_15_12,	RIF1_CLK_C,		SEL_DRIF1_2),
-
-	PINMUX_IPSR_MSEL(IP12_19_16,	TX1_A,			SEL_SCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_19_16,	HTX1_A,			SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_19_16,	TS_SDEN0_C,		SEL_TSIF0_2),
-	PINMUX_IPSR_MSEL(IP12_19_16,	STP_ISEN_0_C,		SEL_SSP1_0_2),
-	PINMUX_IPSR_MSEL(IP12_19_16,	RIF1_D0_C,		SEL_DRIF1_2),
-
-	PINMUX_IPSR_GPSR(IP12_23_20,	CTS1_N),
-	PINMUX_IPSR_MSEL(IP12_23_20,	HCTS1_N_A,		SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_23_20,	MSIOF1_RXD_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP12_23_20,	TS_SDEN1_C,		SEL_TSIF1_2),
-	PINMUX_IPSR_MSEL(IP12_23_20,	STP_ISEN_1_C,		SEL_SSP1_1_2),
-	PINMUX_IPSR_MSEL(IP12_23_20,	RIF1_D0_B,		SEL_DRIF1_1),
-	PINMUX_IPSR_GPSR(IP12_23_20,	ADIDATA),
-
-	PINMUX_IPSR_GPSR(IP12_27_24,	RTS1_N),
-	PINMUX_IPSR_MSEL(IP12_27_24,	HRTS1_N_A,		SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP12_27_24,	MSIOF1_TXD_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP12_27_24,	TS_SDAT1_C,		SEL_TSIF1_2),
-	PINMUX_IPSR_MSEL(IP12_27_24,	STP_ISD_1_C,		SEL_SSP1_1_2),
-	PINMUX_IPSR_MSEL(IP12_27_24,	RIF1_D1_B,		SEL_DRIF1_1),
-	PINMUX_IPSR_GPSR(IP12_27_24,	ADICHS0),
-
-	PINMUX_IPSR_GPSR(IP12_31_28,	SCK2),
-	PINMUX_IPSR_MSEL(IP12_31_28,	SCIF_CLK_B,		SEL_SCIF_1),
-	PINMUX_IPSR_MSEL(IP12_31_28,	MSIOF1_SCK_B,		SEL_MSIOF1_1),
-	PINMUX_IPSR_MSEL(IP12_31_28,	TS_SCK1_C,		SEL_TSIF1_2),
-	PINMUX_IPSR_MSEL(IP12_31_28,	STP_ISCLK_1_C,		SEL_SSP1_1_2),
-	PINMUX_IPSR_MSEL(IP12_31_28,	RIF1_CLK_B,		SEL_DRIF1_1),
-	PINMUX_IPSR_GPSR(IP12_31_28,	ADICLK),
-
-	/* IPSR13 */
-	PINMUX_IPSR_MSEL(IP13_3_0,	TX2_A,			SEL_SCIF2_0),
-	PINMUX_IPSR_MSEL(IP13_3_0,	SD2_CD_B,		SEL_SDHI2_1),
-	PINMUX_IPSR_MSEL(IP13_3_0,	SCL1_A,			SEL_I2C1_0),
-	PINMUX_IPSR_MSEL(IP13_3_0,	FMCLK_A,		SEL_FM_0),
-	PINMUX_IPSR_MSEL(IP13_3_0,	RIF1_D1_C,		SEL_DRIF1_2),
-	PINMUX_IPSR_GPSR(IP13_3_0,	FSO_CFE_0_N),
-
-	PINMUX_IPSR_MSEL(IP13_7_4,	RX2_A,			SEL_SCIF2_0),
-	PINMUX_IPSR_MSEL(IP13_7_4,	SD2_WP_B,		SEL_SDHI2_1),
-	PINMUX_IPSR_MSEL(IP13_7_4,	SDA1_A,			SEL_I2C1_0),
-	PINMUX_IPSR_MSEL(IP13_7_4,	FMIN_A,			SEL_FM_0),
-	PINMUX_IPSR_MSEL(IP13_7_4,	RIF1_SYNC_C,		SEL_DRIF1_2),
-	PINMUX_IPSR_GPSR(IP13_7_4,	FSO_CFE_1_N),
-
-	PINMUX_IPSR_GPSR(IP13_11_8,	HSCK0),
-	PINMUX_IPSR_MSEL(IP13_11_8,	MSIOF1_SCK_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP13_11_8,	AUDIO_CLKB_A,		SEL_ADGB_0),
-	PINMUX_IPSR_MSEL(IP13_11_8,	SSI_SDATA1_B,		SEL_SSI1_1),
-	PINMUX_IPSR_MSEL(IP13_11_8,	TS_SCK0_D,		SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP13_11_8,	STP_ISCLK_0_D,		SEL_SSP1_0_3),
-	PINMUX_IPSR_MSEL(IP13_11_8,	RIF0_CLK_C,		SEL_DRIF0_2),
-	PINMUX_IPSR_MSEL(IP13_11_8,	RX5_B,			SEL_SCIF5_1),
-
-	PINMUX_IPSR_GPSR(IP13_15_12,	HRX0),
-	PINMUX_IPSR_MSEL(IP13_15_12,	MSIOF1_RXD_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP13_15_12,	SSI_SDATA2_B,		SEL_SSI2_1),
-	PINMUX_IPSR_MSEL(IP13_15_12,	TS_SDEN0_D,		SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP13_15_12,	STP_ISEN_0_D,		SEL_SSP1_0_3),
-	PINMUX_IPSR_MSEL(IP13_15_12,	RIF0_D0_C,		SEL_DRIF0_2),
-
-	PINMUX_IPSR_GPSR(IP13_19_16,	HTX0),
-	PINMUX_IPSR_MSEL(IP13_19_16,	MSIOF1_TXD_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP13_19_16,	SSI_SDATA9_B,		SEL_SSI9_1),
-	PINMUX_IPSR_MSEL(IP13_19_16,	TS_SDAT0_D,		SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP13_19_16,	STP_ISD_0_D,		SEL_SSP1_0_3),
-	PINMUX_IPSR_MSEL(IP13_19_16,	RIF0_D1_C,		SEL_DRIF0_2),
-
-	PINMUX_IPSR_GPSR(IP13_23_20,	HCTS0_N),
-	PINMUX_IPSR_MSEL(IP13_23_20,	RX2_B,			SEL_SCIF2_1),
-	PINMUX_IPSR_MSEL(IP13_23_20,	MSIOF1_SYNC_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP13_23_20,	SSI_SCK9_A,		SEL_SSI9_0),
-	PINMUX_IPSR_MSEL(IP13_23_20,	TS_SPSYNC0_D,		SEL_TSIF0_3),
-	PINMUX_IPSR_MSEL(IP13_23_20,	STP_ISSYNC_0_D,		SEL_SSP1_0_3),
-	PINMUX_IPSR_MSEL(IP13_23_20,	RIF0_SYNC_C,		SEL_DRIF0_2),
-	PINMUX_IPSR_GPSR(IP13_23_20,	AUDIO_CLKOUT1_A),
-
-	PINMUX_IPSR_GPSR(IP13_27_24,	HRTS0_N),
-	PINMUX_IPSR_MSEL(IP13_27_24,	TX2_B,			SEL_SCIF2_1),
-	PINMUX_IPSR_MSEL(IP13_27_24,	MSIOF1_SS1_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP13_27_24,	SSI_WS9_A,		SEL_SSI9_0),
-	PINMUX_IPSR_MSEL(IP13_27_24,	STP_IVCXO27_0_D,	SEL_SSP1_0_3),
-	PINMUX_IPSR_MSEL(IP13_27_24,	BPFCLK_A,		SEL_FM_0),
-	PINMUX_IPSR_GPSR(IP13_27_24,	AUDIO_CLKOUT2_A),
-
-	PINMUX_IPSR_GPSR(IP13_31_28,	MSIOF0_SYNC),
-	PINMUX_IPSR_GPSR(IP13_31_28,	AUDIO_CLKOUT_A),
-	PINMUX_IPSR_MSEL(IP13_31_28,	TX5_B,			SEL_SCIF5_1),
-	PINMUX_IPSR_MSEL(IP13_31_28,	BPFCLK_D,		SEL_FM_3),
-
-	/* IPSR14 */
-	PINMUX_IPSR_GPSR(IP14_3_0,	MSIOF0_SS1),
-	PINMUX_IPSR_MSEL(IP14_3_0,	RX5_A,			SEL_SCIF5_0),
-	PINMUX_IPSR_MSEL(IP14_3_0,	NFWP_N_A,		SEL_NDF_0),
-	PINMUX_IPSR_MSEL(IP14_3_0,	AUDIO_CLKA_C,		SEL_ADGA_2),
-	PINMUX_IPSR_MSEL(IP14_3_0,	SSI_SCK2_A,		SEL_SSI2_0),
-	PINMUX_IPSR_MSEL(IP14_3_0,	STP_IVCXO27_0_C,	SEL_SSP1_0_2),
-	PINMUX_IPSR_GPSR(IP14_3_0,	AUDIO_CLKOUT3_A),
-	PINMUX_IPSR_MSEL(IP14_3_0,	TCLK1_B,		SEL_TIMER_TMU_1),
-
-	PINMUX_IPSR_GPSR(IP14_7_4,	MSIOF0_SS2),
-	PINMUX_IPSR_MSEL(IP14_7_4,	TX5_A,			SEL_SCIF5_0),
-	PINMUX_IPSR_MSEL(IP14_7_4,	MSIOF1_SS2_D,		SEL_MSIOF1_3),
-	PINMUX_IPSR_MSEL(IP14_7_4,	AUDIO_CLKC_A,		SEL_ADGC_0),
-	PINMUX_IPSR_MSEL(IP14_7_4,	SSI_WS2_A,		SEL_SSI2_0),
-	PINMUX_IPSR_MSEL(IP14_7_4,	STP_OPWM_0_D,		SEL_SSP1_0_3),
-	PINMUX_IPSR_GPSR(IP14_7_4,	AUDIO_CLKOUT_D),
-	PINMUX_IPSR_MSEL(IP14_7_4,	SPEEDIN_B,		SEL_SPEED_PULSE_1),
-
-	PINMUX_IPSR_GPSR(IP14_11_8,	MLB_CLK),
-	PINMUX_IPSR_MSEL(IP14_11_8,	MSIOF1_SCK_F,		SEL_MSIOF1_5),
-	PINMUX_IPSR_MSEL(IP14_11_8,	SCL1_B,			SEL_I2C1_1),
-
-	PINMUX_IPSR_GPSR(IP14_15_12,	MLB_SIG),
-	PINMUX_IPSR_MSEL(IP14_15_12,	RX1_B,			SEL_SCIF1_1),
-	PINMUX_IPSR_MSEL(IP14_15_12,	MSIOF1_SYNC_F,		SEL_MSIOF1_5),
-	PINMUX_IPSR_MSEL(IP14_15_12,	SDA1_B,			SEL_I2C1_1),
-
-	PINMUX_IPSR_GPSR(IP14_19_16,	MLB_DAT),
-	PINMUX_IPSR_MSEL(IP14_19_16,	TX1_B,			SEL_SCIF1_1),
-	PINMUX_IPSR_MSEL(IP14_19_16,	MSIOF1_RXD_F,		SEL_MSIOF1_5),
-
-	PINMUX_IPSR_GPSR(IP14_23_20,	SSI_SCK01239),
-	PINMUX_IPSR_MSEL(IP14_23_20,	MSIOF1_TXD_F,		SEL_MSIOF1_5),
-
-	PINMUX_IPSR_GPSR(IP14_27_24,	SSI_WS01239),
-	PINMUX_IPSR_MSEL(IP14_27_24,	MSIOF1_SS1_F,		SEL_MSIOF1_5),
-
-	PINMUX_IPSR_GPSR(IP14_31_28,	SSI_SDATA0),
-	PINMUX_IPSR_MSEL(IP14_31_28,	MSIOF1_SS2_F,		SEL_MSIOF1_5),
-
-	/* IPSR15 */
-	PINMUX_IPSR_MSEL(IP15_3_0,	SSI_SDATA1_A,		SEL_SSI1_0),
-
-	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SDATA2_A,		SEL_SSI2_0),
-	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SCK1_B,		SEL_SSI1_1),
-
-	PINMUX_IPSR_GPSR(IP15_11_8,	SSI_SCK349),
-	PINMUX_IPSR_MSEL(IP15_11_8,	MSIOF1_SS1_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP15_11_8,	STP_OPWM_0_A,		SEL_SSP1_0_0),
-
-	PINMUX_IPSR_GPSR(IP15_15_12,	SSI_WS349),
-	PINMUX_IPSR_MSEL(IP15_15_12,	HCTS2_N_A,		SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP15_15_12,	MSIOF1_SS2_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP15_15_12,	STP_IVCXO27_0_A,	SEL_SSP1_0_0),
-
-	PINMUX_IPSR_GPSR(IP15_19_16,	SSI_SDATA3),
-	PINMUX_IPSR_MSEL(IP15_19_16,	HRTS2_N_A,		SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP15_19_16,	MSIOF1_TXD_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP15_19_16,	TS_SCK0_A,		SEL_TSIF0_0),
-	PINMUX_IPSR_MSEL(IP15_19_16,	STP_ISCLK_0_A,		SEL_SSP1_0_0),
-	PINMUX_IPSR_MSEL(IP15_19_16,	RIF0_D1_A,		SEL_DRIF0_0),
-	PINMUX_IPSR_MSEL(IP15_19_16,	RIF2_D0_A,		SEL_DRIF2_0),
-
-	PINMUX_IPSR_GPSR(IP15_23_20,	SSI_SCK4),
-	PINMUX_IPSR_MSEL(IP15_23_20,	HRX2_A,			SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP15_23_20,	MSIOF1_SCK_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP15_23_20,	TS_SDAT0_A,		SEL_TSIF0_0),
-	PINMUX_IPSR_MSEL(IP15_23_20,	STP_ISD_0_A,		SEL_SSP1_0_0),
-	PINMUX_IPSR_MSEL(IP15_23_20,	RIF0_CLK_A,		SEL_DRIF0_0),
-	PINMUX_IPSR_MSEL(IP15_23_20,	RIF2_CLK_A,		SEL_DRIF2_0),
-
-	PINMUX_IPSR_GPSR(IP15_27_24,	SSI_WS4),
-	PINMUX_IPSR_MSEL(IP15_27_24,	HTX2_A,			SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP15_27_24,	MSIOF1_SYNC_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP15_27_24,	TS_SDEN0_A,		SEL_TSIF0_0),
-	PINMUX_IPSR_MSEL(IP15_27_24,	STP_ISEN_0_A,		SEL_SSP1_0_0),
-	PINMUX_IPSR_MSEL(IP15_27_24,	RIF0_SYNC_A,		SEL_DRIF0_0),
-	PINMUX_IPSR_MSEL(IP15_27_24,	RIF2_SYNC_A,		SEL_DRIF2_0),
-
-	PINMUX_IPSR_GPSR(IP15_31_28,	SSI_SDATA4),
-	PINMUX_IPSR_MSEL(IP15_31_28,	HSCK2_A,		SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP15_31_28,	MSIOF1_RXD_A,		SEL_MSIOF1_0),
-	PINMUX_IPSR_MSEL(IP15_31_28,	TS_SPSYNC0_A,		SEL_TSIF0_0),
-	PINMUX_IPSR_MSEL(IP15_31_28,	STP_ISSYNC_0_A,		SEL_SSP1_0_0),
-	PINMUX_IPSR_MSEL(IP15_31_28,	RIF0_D0_A,		SEL_DRIF0_0),
-	PINMUX_IPSR_MSEL(IP15_31_28,	RIF2_D1_A,		SEL_DRIF2_0),
-
-	/* IPSR16 */
-	PINMUX_IPSR_GPSR(IP16_3_0,	SSI_SCK6),
-	PINMUX_IPSR_MSEL(IP16_3_0,	SIM0_RST_D,		SEL_SIMCARD_3),
-
-	PINMUX_IPSR_GPSR(IP16_7_4,	SSI_WS6),
-	PINMUX_IPSR_MSEL(IP16_7_4,	SIM0_D_D,		SEL_SIMCARD_3),
-
-	PINMUX_IPSR_GPSR(IP16_11_8,	SSI_SDATA6),
-	PINMUX_IPSR_MSEL(IP16_11_8,	SIM0_CLK_D,		SEL_SIMCARD_3),
-	PINMUX_IPSR_GPSR(IP16_11_8,	SATA_DEVSLP_A),
-
-	PINMUX_IPSR_GPSR(IP16_15_12,	SSI_SCK78),
-	PINMUX_IPSR_MSEL(IP16_15_12,	HRX2_B,			SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP16_15_12,	MSIOF1_SCK_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP16_15_12,	TS_SCK1_A,		SEL_TSIF1_0),
-	PINMUX_IPSR_MSEL(IP16_15_12,	STP_ISCLK_1_A,		SEL_SSP1_1_0),
-	PINMUX_IPSR_MSEL(IP16_15_12,	RIF1_CLK_A,		SEL_DRIF1_0),
-	PINMUX_IPSR_MSEL(IP16_15_12,	RIF3_CLK_A,		SEL_DRIF3_0),
-
-	PINMUX_IPSR_GPSR(IP16_19_16,	SSI_WS78),
-	PINMUX_IPSR_MSEL(IP16_19_16,	HTX2_B,			SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP16_19_16,	MSIOF1_SYNC_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP16_19_16,	TS_SDAT1_A,		SEL_TSIF1_0),
-	PINMUX_IPSR_MSEL(IP16_19_16,	STP_ISD_1_A,		SEL_SSP1_1_0),
-	PINMUX_IPSR_MSEL(IP16_19_16,	RIF1_SYNC_A,		SEL_DRIF1_0),
-	PINMUX_IPSR_MSEL(IP16_19_16,	RIF3_SYNC_A,		SEL_DRIF3_0),
-
-	PINMUX_IPSR_GPSR(IP16_23_20,	SSI_SDATA7),
-	PINMUX_IPSR_MSEL(IP16_23_20,	HCTS2_N_B,		SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP16_23_20,	MSIOF1_RXD_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP16_23_20,	TS_SDEN1_A,		SEL_TSIF1_0),
-	PINMUX_IPSR_MSEL(IP16_23_20,	STP_ISEN_1_A,		SEL_SSP1_1_0),
-	PINMUX_IPSR_MSEL(IP16_23_20,	RIF1_D0_A,		SEL_DRIF1_0),
-	PINMUX_IPSR_MSEL(IP16_23_20,	RIF3_D0_A,		SEL_DRIF3_0),
-	PINMUX_IPSR_MSEL(IP16_23_20,	TCLK2_A,		SEL_TIMER_TMU2_0),
-
-	PINMUX_IPSR_GPSR(IP16_27_24,	SSI_SDATA8),
-	PINMUX_IPSR_MSEL(IP16_27_24,	HRTS2_N_B,		SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP16_27_24,	MSIOF1_TXD_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP16_27_24,	TS_SPSYNC1_A,		SEL_TSIF1_0),
-	PINMUX_IPSR_MSEL(IP16_27_24,	STP_ISSYNC_1_A,		SEL_SSP1_1_0),
-	PINMUX_IPSR_MSEL(IP16_27_24,	RIF1_D1_A,		SEL_DRIF1_0),
-	PINMUX_IPSR_MSEL(IP16_27_24,	RIF3_D1_A,		SEL_DRIF3_0),
-
-	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_SDATA9_A,		SEL_SSI9_0),
-	PINMUX_IPSR_MSEL(IP16_31_28,	HSCK2_B,		SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP16_31_28,	MSIOF1_SS1_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP16_31_28,	HSCK1_A,		SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_WS1_B,		SEL_SSI1_1),
-	PINMUX_IPSR_GPSR(IP16_31_28,	SCK1),
-	PINMUX_IPSR_MSEL(IP16_31_28,	STP_IVCXO27_1_A,	SEL_SSP1_1_0),
-	PINMUX_IPSR_MSEL(IP16_31_28,	SCK5_A,			SEL_SCIF5_0),
-
-	/* IPSR17 */
-	PINMUX_IPSR_MSEL(IP17_3_0,	AUDIO_CLKA_A,		SEL_ADGA_0),
-
-	PINMUX_IPSR_MSEL(IP17_7_4,	AUDIO_CLKB_B,		SEL_ADGB_1),
-	PINMUX_IPSR_MSEL(IP17_7_4,	SCIF_CLK_A,		SEL_SCIF_0),
-	PINMUX_IPSR_MSEL(IP17_7_4,	STP_IVCXO27_1_D,	SEL_SSP1_1_3),
-	PINMUX_IPSR_MSEL(IP17_7_4,	REMOCON_A,		SEL_REMOCON_0),
-	PINMUX_IPSR_MSEL(IP17_7_4,	TCLK1_A,		SEL_TIMER_TMU_0),
-
-	PINMUX_IPSR_GPSR(IP17_11_8,	USB0_PWEN),
-	PINMUX_IPSR_MSEL(IP17_11_8,	SIM0_RST_C,		SEL_SIMCARD_2),
-	PINMUX_IPSR_MSEL(IP17_11_8,	TS_SCK1_D,		SEL_TSIF1_3),
-	PINMUX_IPSR_MSEL(IP17_11_8,	STP_ISCLK_1_D,		SEL_SSP1_1_3),
-	PINMUX_IPSR_MSEL(IP17_11_8,	BPFCLK_B,		SEL_FM_1),
-	PINMUX_IPSR_MSEL(IP17_11_8,	RIF3_CLK_B,		SEL_DRIF3_1),
-	PINMUX_IPSR_MSEL(IP17_11_8,	HSCK2_C,		SEL_HSCIF2_2),
-
-	PINMUX_IPSR_GPSR(IP17_15_12,	USB0_OVC),
-	PINMUX_IPSR_MSEL(IP17_15_12,	SIM0_D_C,		SEL_SIMCARD_2),
-	PINMUX_IPSR_MSEL(IP17_15_12,	TS_SDAT1_D,		SEL_TSIF1_3),
-	PINMUX_IPSR_MSEL(IP17_15_12,	STP_ISD_1_D,		SEL_SSP1_1_3),
-	PINMUX_IPSR_MSEL(IP17_15_12,	RIF3_SYNC_B,		SEL_DRIF3_1),
-	PINMUX_IPSR_MSEL(IP17_15_12,	HRX2_C,			SEL_HSCIF2_2),
-
-	PINMUX_IPSR_GPSR(IP17_19_16,	USB1_PWEN),
-	PINMUX_IPSR_MSEL(IP17_19_16,	SIM0_CLK_C,		SEL_SIMCARD_2),
-	PINMUX_IPSR_MSEL(IP17_19_16,	SSI_SCK1_A,		SEL_SSI1_0),
-	PINMUX_IPSR_MSEL(IP17_19_16,	TS_SCK0_E,		SEL_TSIF0_4),
-	PINMUX_IPSR_MSEL(IP17_19_16,	STP_ISCLK_0_E,		SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP17_19_16,	FMCLK_B,		SEL_FM_1),
-	PINMUX_IPSR_MSEL(IP17_19_16,	RIF2_CLK_B,		SEL_DRIF2_1),
-	PINMUX_IPSR_MSEL(IP17_19_16,	SPEEDIN_A,		SEL_SPEED_PULSE_0),
-	PINMUX_IPSR_MSEL(IP17_19_16,	HTX2_C,			SEL_HSCIF2_2),
-
-	PINMUX_IPSR_GPSR(IP17_23_20,	USB1_OVC),
-	PINMUX_IPSR_MSEL(IP17_23_20,	MSIOF1_SS2_C,		SEL_MSIOF1_2),
-	PINMUX_IPSR_MSEL(IP17_23_20,	SSI_WS1_A,		SEL_SSI1_0),
-	PINMUX_IPSR_MSEL(IP17_23_20,	TS_SDAT0_E,		SEL_TSIF0_4),
-	PINMUX_IPSR_MSEL(IP17_23_20,	STP_ISD_0_E,		SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP17_23_20,	FMIN_B,			SEL_FM_1),
-	PINMUX_IPSR_MSEL(IP17_23_20,	RIF2_SYNC_B,		SEL_DRIF2_1),
-	PINMUX_IPSR_MSEL(IP17_23_20,	REMOCON_B,		SEL_REMOCON_1),
-	PINMUX_IPSR_MSEL(IP17_23_20,	HCTS2_N_C,		SEL_HSCIF2_2),
-
-	PINMUX_IPSR_GPSR(IP17_27_24,	USB30_PWEN),
-	PINMUX_IPSR_GPSR(IP17_27_24,	AUDIO_CLKOUT_B),
-	PINMUX_IPSR_MSEL(IP17_27_24,	SSI_SCK2_B,		SEL_SSI2_1),
-	PINMUX_IPSR_MSEL(IP17_27_24,	TS_SDEN1_D,		SEL_TSIF1_3),
-	PINMUX_IPSR_MSEL(IP17_27_24,	STP_ISEN_1_D,		SEL_SSP1_1_3),
-	PINMUX_IPSR_MSEL(IP17_27_24,	STP_OPWM_0_E,		SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP17_27_24,	RIF3_D0_B,		SEL_DRIF3_1),
-	PINMUX_IPSR_MSEL(IP17_27_24,	TCLK2_B,		SEL_TIMER_TMU2_1),
-	PINMUX_IPSR_GPSR(IP17_27_24,	TPU0TO0),
-	PINMUX_IPSR_MSEL(IP17_27_24,	BPFCLK_C,		SEL_FM_2),
-	PINMUX_IPSR_MSEL(IP17_27_24,	HRTS2_N_C,		SEL_HSCIF2_2),
-
-	PINMUX_IPSR_GPSR(IP17_31_28,	USB30_OVC),
-	PINMUX_IPSR_GPSR(IP17_31_28,	AUDIO_CLKOUT1_B),
-	PINMUX_IPSR_MSEL(IP17_31_28,	SSI_WS2_B,		SEL_SSI2_1),
-	PINMUX_IPSR_MSEL(IP17_31_28,	TS_SPSYNC1_D,		SEL_TSIF1_3),
-	PINMUX_IPSR_MSEL(IP17_31_28,	STP_ISSYNC_1_D,		SEL_SSP1_1_3),
-	PINMUX_IPSR_MSEL(IP17_31_28,	STP_IVCXO27_0_E,	SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP17_31_28,	RIF3_D1_B,		SEL_DRIF3_1),
-	PINMUX_IPSR_GPSR(IP17_31_28,	FSO_TOE_N),
-	PINMUX_IPSR_GPSR(IP17_31_28,	TPU0TO1),
-
-	/* IPSR18 */
-	PINMUX_IPSR_GPSR(IP18_3_0,	GP6_30),
-	PINMUX_IPSR_GPSR(IP18_3_0,	AUDIO_CLKOUT2_B),
-	PINMUX_IPSR_MSEL(IP18_3_0,	SSI_SCK9_B,		SEL_SSI9_1),
-	PINMUX_IPSR_MSEL(IP18_3_0,	TS_SDEN0_E,		SEL_TSIF0_4),
-	PINMUX_IPSR_MSEL(IP18_3_0,	STP_ISEN_0_E,		SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP18_3_0,	RIF2_D0_B,		SEL_DRIF2_1),
-	PINMUX_IPSR_GPSR(IP18_3_0,	TPU0TO2),
-	PINMUX_IPSR_MSEL(IP18_3_0,	FMCLK_C,		SEL_FM_2),
-	PINMUX_IPSR_MSEL(IP18_3_0,	FMCLK_D,		SEL_FM_3),
-
-	PINMUX_IPSR_GPSR(IP18_7_4,	GP6_31),
-	PINMUX_IPSR_GPSR(IP18_7_4,	AUDIO_CLKOUT3_B),
-	PINMUX_IPSR_MSEL(IP18_7_4,	SSI_WS9_B,		SEL_SSI9_1),
-	PINMUX_IPSR_MSEL(IP18_7_4,	TS_SPSYNC0_E,		SEL_TSIF0_4),
-	PINMUX_IPSR_MSEL(IP18_7_4,	STP_ISSYNC_0_E,		SEL_SSP1_0_4),
-	PINMUX_IPSR_MSEL(IP18_7_4,	RIF2_D1_B,		SEL_DRIF2_1),
-	PINMUX_IPSR_GPSR(IP18_7_4,	TPU0TO3),
-	PINMUX_IPSR_MSEL(IP18_7_4,	FMIN_C,			SEL_FM_2),
-	PINMUX_IPSR_MSEL(IP18_7_4,	FMIN_D,			SEL_FM_3),
-
-/*
- * Static pins can not be muxed between different functions but
- * still need mark entries in the pinmux list. Add each static
- * pin to the list without an associated function. The sh-pfc
- * core will do the right thing and skip trying to mux the pin
- * while still applying configuration to it.
- */
-#define FM(x)   PINMUX_DATA(x##_MARK, 0),
-	PINMUX_STATIC
-#undef FM
-};
-
-/*
- * Pins not associated with a GPIO port.
- */
-enum {
-	GP_ASSIGN_LAST(),
-	NOGP_ALL(),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	PINMUX_GPIO_GP_ALL(),
-	PINMUX_NOGP_ALL(),
-};
-
-/* - AUDIO CLOCK ------------------------------------------------------------ */
-static const unsigned int audio_clk_a_a_pins[] = {
-	/* CLK A */
-	RCAR_GP_PIN(6, 22),
-};
-static const unsigned int audio_clk_a_a_mux[] = {
-	AUDIO_CLKA_A_MARK,
-};
-static const unsigned int audio_clk_a_b_pins[] = {
-	/* CLK A */
-	RCAR_GP_PIN(5, 4),
-};
-static const unsigned int audio_clk_a_b_mux[] = {
-	AUDIO_CLKA_B_MARK,
-};
-static const unsigned int audio_clk_a_c_pins[] = {
-	/* CLK A */
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int audio_clk_a_c_mux[] = {
-	AUDIO_CLKA_C_MARK,
-};
-static const unsigned int audio_clk_b_a_pins[] = {
-	/* CLK B */
-	RCAR_GP_PIN(5, 12),
-};
-static const unsigned int audio_clk_b_a_mux[] = {
-	AUDIO_CLKB_A_MARK,
-};
-static const unsigned int audio_clk_b_b_pins[] = {
-	/* CLK B */
-	RCAR_GP_PIN(6, 23),
-};
-static const unsigned int audio_clk_b_b_mux[] = {
-	AUDIO_CLKB_B_MARK,
-};
-static const unsigned int audio_clk_c_a_pins[] = {
-	/* CLK C */
-	RCAR_GP_PIN(5, 21),
-};
-static const unsigned int audio_clk_c_a_mux[] = {
-	AUDIO_CLKC_A_MARK,
-};
-static const unsigned int audio_clk_c_b_pins[] = {
-	/* CLK C */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int audio_clk_c_b_mux[] = {
-	AUDIO_CLKC_B_MARK,
-};
-static const unsigned int audio_clkout_a_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(5, 18),
-};
-static const unsigned int audio_clkout_a_mux[] = {
-	AUDIO_CLKOUT_A_MARK,
-};
-static const unsigned int audio_clkout_b_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(6, 28),
-};
-static const unsigned int audio_clkout_b_mux[] = {
-	AUDIO_CLKOUT_B_MARK,
-};
-static const unsigned int audio_clkout_c_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(5, 3),
-};
-static const unsigned int audio_clkout_c_mux[] = {
-	AUDIO_CLKOUT_C_MARK,
-};
-static const unsigned int audio_clkout_d_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(5, 21),
-};
-static const unsigned int audio_clkout_d_mux[] = {
-	AUDIO_CLKOUT_D_MARK,
-};
-static const unsigned int audio_clkout1_a_pins[] = {
-	/* CLKOUT1 */
-	RCAR_GP_PIN(5, 15),
-};
-static const unsigned int audio_clkout1_a_mux[] = {
-	AUDIO_CLKOUT1_A_MARK,
-};
-static const unsigned int audio_clkout1_b_pins[] = {
-	/* CLKOUT1 */
-	RCAR_GP_PIN(6, 29),
-};
-static const unsigned int audio_clkout1_b_mux[] = {
-	AUDIO_CLKOUT1_B_MARK,
-};
-static const unsigned int audio_clkout2_a_pins[] = {
-	/* CLKOUT2 */
-	RCAR_GP_PIN(5, 16),
-};
-static const unsigned int audio_clkout2_a_mux[] = {
-	AUDIO_CLKOUT2_A_MARK,
-};
-static const unsigned int audio_clkout2_b_pins[] = {
-	/* CLKOUT2 */
-	RCAR_GP_PIN(6, 30),
-};
-static const unsigned int audio_clkout2_b_mux[] = {
-	AUDIO_CLKOUT2_B_MARK,
-};
-
-static const unsigned int audio_clkout3_a_pins[] = {
-	/* CLKOUT3 */
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int audio_clkout3_a_mux[] = {
-	AUDIO_CLKOUT3_A_MARK,
-};
-static const unsigned int audio_clkout3_b_pins[] = {
-	/* CLKOUT3 */
-	RCAR_GP_PIN(6, 31),
-};
-static const unsigned int audio_clkout3_b_mux[] = {
-	AUDIO_CLKOUT3_B_MARK,
-};
-
-/* - EtherAVB --------------------------------------------------------------- */
-static const unsigned int avb_link_pins[] = {
-	/* AVB_LINK */
-	RCAR_GP_PIN(2, 12),
-};
-static const unsigned int avb_link_mux[] = {
-	AVB_LINK_MARK,
-};
-static const unsigned int avb_magic_pins[] = {
-	/* AVB_MAGIC_ */
-	RCAR_GP_PIN(2, 10),
-};
-static const unsigned int avb_magic_mux[] = {
-	AVB_MAGIC_MARK,
-};
-static const unsigned int avb_phy_int_pins[] = {
-	/* AVB_PHY_INT */
-	RCAR_GP_PIN(2, 11),
-};
-static const unsigned int avb_phy_int_mux[] = {
-	AVB_PHY_INT_MARK,
-};
-static const unsigned int avb_mdio_pins[] = {
-	/* AVB_MDC, AVB_MDIO */
-	RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
-};
-static const unsigned int avb_mdio_mux[] = {
-	AVB_MDC_MARK, AVB_MDIO_MARK,
-};
-static const unsigned int avb_mii_pins[] = {
-	/*
-	 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
-	 * AVB_TD1, AVB_TD2, AVB_TD3,
-	 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
-	 * AVB_RD1, AVB_RD2, AVB_RD3,
-	 * AVB_TXCREFCLK
-	 */
-	PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
-	PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
-	PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
-	PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
-	PIN_AVB_TXCREFCLK,
-
-};
-static const unsigned int avb_mii_mux[] = {
-	AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
-	AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
-	AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
-	AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
-	AVB_TXCREFCLK_MARK,
-};
-static const unsigned int avb_avtp_pps_pins[] = {
-	/* AVB_AVTP_PPS */
-	RCAR_GP_PIN(2, 6),
-};
-static const unsigned int avb_avtp_pps_mux[] = {
-	AVB_AVTP_PPS_MARK,
-};
-static const unsigned int avb_avtp_match_a_pins[] = {
-	/* AVB_AVTP_MATCH_A */
-	RCAR_GP_PIN(2, 13),
-};
-static const unsigned int avb_avtp_match_a_mux[] = {
-	AVB_AVTP_MATCH_A_MARK,
-};
-static const unsigned int avb_avtp_capture_a_pins[] = {
-	/* AVB_AVTP_CAPTURE_A */
-	RCAR_GP_PIN(2, 14),
-};
-static const unsigned int avb_avtp_capture_a_mux[] = {
-	AVB_AVTP_CAPTURE_A_MARK,
-};
-static const unsigned int avb_avtp_match_b_pins[] = {
-	/*  AVB_AVTP_MATCH_B */
-	RCAR_GP_PIN(1, 8),
-};
-static const unsigned int avb_avtp_match_b_mux[] = {
-	AVB_AVTP_MATCH_B_MARK,
-};
-static const unsigned int avb_avtp_capture_b_pins[] = {
-	/* AVB_AVTP_CAPTURE_B */
-	RCAR_GP_PIN(1, 11),
-};
-static const unsigned int avb_avtp_capture_b_mux[] = {
-	AVB_AVTP_CAPTURE_B_MARK,
-};
-
-/* - CAN ------------------------------------------------------------------ */
-static const unsigned int can0_data_a_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(1, 23),	RCAR_GP_PIN(1, 24),
-};
-
-static const unsigned int can0_data_a_mux[] = {
-	CAN0_TX_A_MARK,		CAN0_RX_A_MARK,
-};
-
-static const unsigned int can0_data_b_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(2, 0),	RCAR_GP_PIN(2, 1),
-};
-
-static const unsigned int can0_data_b_mux[] = {
-	CAN0_TX_B_MARK,		CAN0_RX_B_MARK,
-};
-
-static const unsigned int can1_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(1, 22),	RCAR_GP_PIN(1, 26),
-};
-
-static const unsigned int can1_data_mux[] = {
-	CAN1_TX_MARK,		CAN1_RX_MARK,
-};
-
-/* - CAN Clock -------------------------------------------------------------- */
-static const unsigned int can_clk_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(1, 25),
-};
-
-static const unsigned int can_clk_mux[] = {
-	CAN_CLK_MARK,
-};
-
-/* - CAN FD --------------------------------------------------------------- */
-static const unsigned int canfd0_data_a_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
-};
-
-static const unsigned int canfd0_data_a_mux[] = {
-	CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
-};
-
-static const unsigned int canfd0_data_b_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
-};
-
-static const unsigned int canfd0_data_b_mux[] = {
-	CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
-};
-
-static const unsigned int canfd1_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
-};
-
-static const unsigned int canfd1_data_mux[] = {
-	CANFD1_TX_MARK,         CANFD1_RX_MARK,
-};
-
-/* - DRIF0 --------------------------------------------------------------- */
-static const unsigned int drif0_ctrl_a_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
-};
-
-static const unsigned int drif0_ctrl_a_mux[] = {
-	RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
-};
-
-static const unsigned int drif0_data0_a_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 10),
-};
-
-static const unsigned int drif0_data0_a_mux[] = {
-	RIF0_D0_A_MARK,
-};
-
-static const unsigned int drif0_data1_a_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 7),
-};
-
-static const unsigned int drif0_data1_a_mux[] = {
-	RIF0_D1_A_MARK,
-};
-
-static const unsigned int drif0_ctrl_b_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
-};
-
-static const unsigned int drif0_ctrl_b_mux[] = {
-	RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
-};
-
-static const unsigned int drif0_data0_b_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(5, 1),
-};
-
-static const unsigned int drif0_data0_b_mux[] = {
-	RIF0_D0_B_MARK,
-};
-
-static const unsigned int drif0_data1_b_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(5, 2),
-};
-
-static const unsigned int drif0_data1_b_mux[] = {
-	RIF0_D1_B_MARK,
-};
-
-static const unsigned int drif0_ctrl_c_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
-};
-
-static const unsigned int drif0_ctrl_c_mux[] = {
-	RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
-};
-
-static const unsigned int drif0_data0_c_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(5, 13),
-};
-
-static const unsigned int drif0_data0_c_mux[] = {
-	RIF0_D0_C_MARK,
-};
-
-static const unsigned int drif0_data1_c_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(5, 14),
-};
-
-static const unsigned int drif0_data1_c_mux[] = {
-	RIF0_D1_C_MARK,
-};
-
-/* - DRIF1 --------------------------------------------------------------- */
-static const unsigned int drif1_ctrl_a_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
-};
-
-static const unsigned int drif1_ctrl_a_mux[] = {
-	RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
-};
-
-static const unsigned int drif1_data0_a_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 19),
-};
-
-static const unsigned int drif1_data0_a_mux[] = {
-	RIF1_D0_A_MARK,
-};
-
-static const unsigned int drif1_data1_a_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 20),
-};
-
-static const unsigned int drif1_data1_a_mux[] = {
-	RIF1_D1_A_MARK,
-};
-
-static const unsigned int drif1_ctrl_b_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
-};
-
-static const unsigned int drif1_ctrl_b_mux[] = {
-	RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
-};
-
-static const unsigned int drif1_data0_b_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(5, 7),
-};
-
-static const unsigned int drif1_data0_b_mux[] = {
-	RIF1_D0_B_MARK,
-};
-
-static const unsigned int drif1_data1_b_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(5, 8),
-};
-
-static const unsigned int drif1_data1_b_mux[] = {
-	RIF1_D1_B_MARK,
-};
-
-static const unsigned int drif1_ctrl_c_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
-};
-
-static const unsigned int drif1_ctrl_c_mux[] = {
-	RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
-};
-
-static const unsigned int drif1_data0_c_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(5, 6),
-};
-
-static const unsigned int drif1_data0_c_mux[] = {
-	RIF1_D0_C_MARK,
-};
-
-static const unsigned int drif1_data1_c_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(5, 10),
-};
-
-static const unsigned int drif1_data1_c_mux[] = {
-	RIF1_D1_C_MARK,
-};
-
-/* - DRIF2 --------------------------------------------------------------- */
-static const unsigned int drif2_ctrl_a_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
-};
-
-static const unsigned int drif2_ctrl_a_mux[] = {
-	RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
-};
-
-static const unsigned int drif2_data0_a_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 7),
-};
-
-static const unsigned int drif2_data0_a_mux[] = {
-	RIF2_D0_A_MARK,
-};
-
-static const unsigned int drif2_data1_a_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 10),
-};
-
-static const unsigned int drif2_data1_a_mux[] = {
-	RIF2_D1_A_MARK,
-};
-
-static const unsigned int drif2_ctrl_b_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
-};
-
-static const unsigned int drif2_ctrl_b_mux[] = {
-	RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
-};
-
-static const unsigned int drif2_data0_b_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 30),
-};
-
-static const unsigned int drif2_data0_b_mux[] = {
-	RIF2_D0_B_MARK,
-};
-
-static const unsigned int drif2_data1_b_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 31),
-};
-
-static const unsigned int drif2_data1_b_mux[] = {
-	RIF2_D1_B_MARK,
-};
-
-/* - DRIF3 --------------------------------------------------------------- */
-static const unsigned int drif3_ctrl_a_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
-};
-
-static const unsigned int drif3_ctrl_a_mux[] = {
-	RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
-};
-
-static const unsigned int drif3_data0_a_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 19),
-};
-
-static const unsigned int drif3_data0_a_mux[] = {
-	RIF3_D0_A_MARK,
-};
-
-static const unsigned int drif3_data1_a_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 20),
-};
-
-static const unsigned int drif3_data1_a_mux[] = {
-	RIF3_D1_A_MARK,
-};
-
-static const unsigned int drif3_ctrl_b_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
-};
-
-static const unsigned int drif3_ctrl_b_mux[] = {
-	RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
-};
-
-static const unsigned int drif3_data0_b_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(6, 28),
-};
-
-static const unsigned int drif3_data0_b_mux[] = {
-	RIF3_D0_B_MARK,
-};
-
-static const unsigned int drif3_data1_b_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(6, 29),
-};
-
-static const unsigned int drif3_data1_b_mux[] = {
-	RIF3_D1_B_MARK,
-};
-
-/* - DU --------------------------------------------------------------------- */
-static const unsigned int du_rgb666_pins[] = {
-	/* R[7:2], G[7:2], B[7:2] */
-	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
-	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
-	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
-	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
-};
-
-static const unsigned int du_rgb666_mux[] = {
-	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
-	DU_DR3_MARK, DU_DR2_MARK,
-	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
-	DU_DG3_MARK, DU_DG2_MARK,
-	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
-	DU_DB3_MARK, DU_DB2_MARK,
-};
-
-static const unsigned int du_rgb888_pins[] = {
-	/* R[7:0], G[7:0], B[7:0] */
-	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
-	RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
-	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
-	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
-	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
-	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
-	RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
-};
-
-static const unsigned int du_rgb888_mux[] = {
-	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
-	DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
-	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
-	DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
-	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
-	DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
-};
-
-static const unsigned int du_clk_out_0_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(1, 27),
-};
-
-static const unsigned int du_clk_out_0_mux[] = {
-	DU_DOTCLKOUT0_MARK
-};
-
-static const unsigned int du_clk_out_1_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(2, 3),
-};
-
-static const unsigned int du_clk_out_1_mux[] = {
-	DU_DOTCLKOUT1_MARK
-};
-
-static const unsigned int du_sync_pins[] = {
-	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
-	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
-};
-
-static const unsigned int du_sync_mux[] = {
-	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
-};
-
-static const unsigned int du_oddf_pins[] = {
-	/* EXDISP/EXODDF/EXCDE */
-	RCAR_GP_PIN(2, 2),
-};
-
-static const unsigned int du_oddf_mux[] = {
-	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
-};
-
-static const unsigned int du_cde_pins[] = {
-	/* CDE */
-	RCAR_GP_PIN(2, 0),
-};
-
-static const unsigned int du_cde_mux[] = {
-	DU_CDE_MARK,
-};
-
-static const unsigned int du_disp_pins[] = {
-	/* DISP */
-	RCAR_GP_PIN(2, 1),
-};
-
-static const unsigned int du_disp_mux[] = {
-	DU_DISP_MARK,
-};
-
-/* - HSCIF0 ----------------------------------------------------------------- */
-static const unsigned int hscif0_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
-};
-
-static const unsigned int hscif0_data_mux[] = {
-	HRX0_MARK, HTX0_MARK,
-};
-
-static const unsigned int hscif0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 12),
-};
-
-static const unsigned int hscif0_clk_mux[] = {
-	HSCK0_MARK,
-};
-
-static const unsigned int hscif0_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
-};
-
-static const unsigned int hscif0_ctrl_mux[] = {
-	HRTS0_N_MARK, HCTS0_N_MARK,
-};
-
-/* - HSCIF1 ----------------------------------------------------------------- */
-static const unsigned int hscif1_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
-};
-
-static const unsigned int hscif1_data_a_mux[] = {
-	HRX1_A_MARK, HTX1_A_MARK,
-};
-
-static const unsigned int hscif1_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 21),
-};
-
-static const unsigned int hscif1_clk_a_mux[] = {
-	HSCK1_A_MARK,
-};
-
-static const unsigned int hscif1_ctrl_a_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
-};
-
-static const unsigned int hscif1_ctrl_a_mux[] = {
-	HRTS1_N_A_MARK, HCTS1_N_A_MARK,
-};
-
-static const unsigned int hscif1_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-};
-
-static const unsigned int hscif1_data_b_mux[] = {
-	HRX1_B_MARK, HTX1_B_MARK,
-};
-
-static const unsigned int hscif1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 0),
-};
-
-static const unsigned int hscif1_clk_b_mux[] = {
-	HSCK1_B_MARK,
-};
-
-static const unsigned int hscif1_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
-};
-
-static const unsigned int hscif1_ctrl_b_mux[] = {
-	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
-};
-
-/* - HSCIF2 ----------------------------------------------------------------- */
-static const unsigned int hscif2_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
-};
-
-static const unsigned int hscif2_data_a_mux[] = {
-	HRX2_A_MARK, HTX2_A_MARK,
-};
-
-static const unsigned int hscif2_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 10),
-};
-
-static const unsigned int hscif2_clk_a_mux[] = {
-	HSCK2_A_MARK,
-};
-
-static const unsigned int hscif2_ctrl_a_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
-};
-
-static const unsigned int hscif2_ctrl_a_mux[] = {
-	HRTS2_N_A_MARK, HCTS2_N_A_MARK,
-};
-
-static const unsigned int hscif2_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
-};
-
-static const unsigned int hscif2_data_b_mux[] = {
-	HRX2_B_MARK, HTX2_B_MARK,
-};
-
-static const unsigned int hscif2_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 21),
-};
-
-static const unsigned int hscif2_clk_b_mux[] = {
-	HSCK2_B_MARK,
-};
-
-static const unsigned int hscif2_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
-};
-
-static const unsigned int hscif2_ctrl_b_mux[] = {
-	HRTS2_N_B_MARK, HCTS2_N_B_MARK,
-};
-
-static const unsigned int hscif2_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
-};
-
-static const unsigned int hscif2_data_c_mux[] = {
-	HRX2_C_MARK, HTX2_C_MARK,
-};
-
-static const unsigned int hscif2_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 24),
-};
-
-static const unsigned int hscif2_clk_c_mux[] = {
-	HSCK2_C_MARK,
-};
-
-static const unsigned int hscif2_ctrl_c_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
-};
-
-static const unsigned int hscif2_ctrl_c_mux[] = {
-	HRTS2_N_C_MARK, HCTS2_N_C_MARK,
-};
-
-/* - HSCIF3 ----------------------------------------------------------------- */
-static const unsigned int hscif3_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
-};
-
-static const unsigned int hscif3_data_a_mux[] = {
-	HRX3_A_MARK, HTX3_A_MARK,
-};
-
-static const unsigned int hscif3_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 22),
-};
-
-static const unsigned int hscif3_clk_mux[] = {
-	HSCK3_MARK,
-};
-
-static const unsigned int hscif3_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
-};
-
-static const unsigned int hscif3_ctrl_mux[] = {
-	HRTS3_N_MARK, HCTS3_N_MARK,
-};
-
-static const unsigned int hscif3_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-};
-
-static const unsigned int hscif3_data_b_mux[] = {
-	HRX3_B_MARK, HTX3_B_MARK,
-};
-
-static const unsigned int hscif3_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-};
-
-static const unsigned int hscif3_data_c_mux[] = {
-	HRX3_C_MARK, HTX3_C_MARK,
-};
-
-static const unsigned int hscif3_data_d_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
-};
-
-static const unsigned int hscif3_data_d_mux[] = {
-	HRX3_D_MARK, HTX3_D_MARK,
-};
-
-/* - HSCIF4 ----------------------------------------------------------------- */
-static const unsigned int hscif4_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-};
-
-static const unsigned int hscif4_data_a_mux[] = {
-	HRX4_A_MARK, HTX4_A_MARK,
-};
-
-static const unsigned int hscif4_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 11),
-};
-
-static const unsigned int hscif4_clk_mux[] = {
-	HSCK4_MARK,
-};
-
-static const unsigned int hscif4_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
-};
-
-static const unsigned int hscif4_ctrl_mux[] = {
-	HRTS4_N_MARK, HCTS4_N_MARK,
-};
-
-static const unsigned int hscif4_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
-};
-
-static const unsigned int hscif4_data_b_mux[] = {
-	HRX4_B_MARK, HTX4_B_MARK,
-};
-
-/* - I2C -------------------------------------------------------------------- */
-static const unsigned int i2c0_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
-};
-
-static const unsigned int i2c0_mux[] = {
-	SCL0_MARK, SDA0_MARK,
-};
-
-static const unsigned int i2c1_a_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
-};
-
-static const unsigned int i2c1_a_mux[] = {
-	SDA1_A_MARK, SCL1_A_MARK,
-};
-
-static const unsigned int i2c1_b_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
-};
-
-static const unsigned int i2c1_b_mux[] = {
-	SDA1_B_MARK, SCL1_B_MARK,
-};
-
-static const unsigned int i2c2_a_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
-};
-
-static const unsigned int i2c2_a_mux[] = {
-	SDA2_A_MARK, SCL2_A_MARK,
-};
-
-static const unsigned int i2c2_b_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
-};
-
-static const unsigned int i2c2_b_mux[] = {
-	SDA2_B_MARK, SCL2_B_MARK,
-};
-
-static const unsigned int i2c3_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
-};
-
-static const unsigned int i2c3_mux[] = {
-	SCL3_MARK, SDA3_MARK,
-};
-
-static const unsigned int i2c5_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
-};
-
-static const unsigned int i2c5_mux[] = {
-	SCL5_MARK, SDA5_MARK,
-};
-
-static const unsigned int i2c6_a_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
-};
-
-static const unsigned int i2c6_a_mux[] = {
-	SDA6_A_MARK, SCL6_A_MARK,
-};
-
-static const unsigned int i2c6_b_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
-};
-
-static const unsigned int i2c6_b_mux[] = {
-	SDA6_B_MARK, SCL6_B_MARK,
-};
-
-static const unsigned int i2c6_c_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
-};
-
-static const unsigned int i2c6_c_mux[] = {
-	SDA6_C_MARK, SCL6_C_MARK,
-};
-
-/* - INTC-EX ---------------------------------------------------------------- */
-static const unsigned int intc_ex_irq0_pins[] = {
-	/* IRQ0 */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int intc_ex_irq0_mux[] = {
-	IRQ0_MARK,
-};
-static const unsigned int intc_ex_irq1_pins[] = {
-	/* IRQ1 */
-	RCAR_GP_PIN(2, 1),
-};
-static const unsigned int intc_ex_irq1_mux[] = {
-	IRQ1_MARK,
-};
-static const unsigned int intc_ex_irq2_pins[] = {
-	/* IRQ2 */
-	RCAR_GP_PIN(2, 2),
-};
-static const unsigned int intc_ex_irq2_mux[] = {
-	IRQ2_MARK,
-};
-static const unsigned int intc_ex_irq3_pins[] = {
-	/* IRQ3 */
-	RCAR_GP_PIN(2, 3),
-};
-static const unsigned int intc_ex_irq3_mux[] = {
-	IRQ3_MARK,
-};
-static const unsigned int intc_ex_irq4_pins[] = {
-	/* IRQ4 */
-	RCAR_GP_PIN(2, 4),
-};
-static const unsigned int intc_ex_irq4_mux[] = {
-	IRQ4_MARK,
-};
-static const unsigned int intc_ex_irq5_pins[] = {
-	/* IRQ5 */
-	RCAR_GP_PIN(2, 5),
-};
-static const unsigned int intc_ex_irq5_mux[] = {
-	IRQ5_MARK,
-};
-
-/* - MSIOF0 ----------------------------------------------------------------- */
-static const unsigned int msiof0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 17),
-};
-static const unsigned int msiof0_clk_mux[] = {
-	MSIOF0_SCK_MARK,
-};
-static const unsigned int msiof0_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(5, 18),
-};
-static const unsigned int msiof0_sync_mux[] = {
-	MSIOF0_SYNC_MARK,
-};
-static const unsigned int msiof0_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int msiof0_ss1_mux[] = {
-	MSIOF0_SS1_MARK,
-};
-static const unsigned int msiof0_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(5, 21),
-};
-static const unsigned int msiof0_ss2_mux[] = {
-	MSIOF0_SS2_MARK,
-};
-static const unsigned int msiof0_txd_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(5, 20),
-};
-static const unsigned int msiof0_txd_mux[] = {
-	MSIOF0_TXD_MARK,
-};
-static const unsigned int msiof0_rxd_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 22),
-};
-static const unsigned int msiof0_rxd_mux[] = {
-	MSIOF0_RXD_MARK,
-};
-/* - MSIOF1 ----------------------------------------------------------------- */
-static const unsigned int msiof1_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 8),
-};
-static const unsigned int msiof1_clk_a_mux[] = {
-	MSIOF1_SCK_A_MARK,
-};
-static const unsigned int msiof1_sync_a_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(6, 9),
-};
-static const unsigned int msiof1_sync_a_mux[] = {
-	MSIOF1_SYNC_A_MARK,
-};
-static const unsigned int msiof1_ss1_a_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(6, 5),
-};
-static const unsigned int msiof1_ss1_a_mux[] = {
-	MSIOF1_SS1_A_MARK,
-};
-static const unsigned int msiof1_ss2_a_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(6, 6),
-};
-static const unsigned int msiof1_ss2_a_mux[] = {
-	MSIOF1_SS2_A_MARK,
-};
-static const unsigned int msiof1_txd_a_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(6, 7),
-};
-static const unsigned int msiof1_txd_a_mux[] = {
-	MSIOF1_TXD_A_MARK,
-};
-static const unsigned int msiof1_rxd_a_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(6, 10),
-};
-static const unsigned int msiof1_rxd_a_mux[] = {
-	MSIOF1_RXD_A_MARK,
-};
-static const unsigned int msiof1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 9),
-};
-static const unsigned int msiof1_clk_b_mux[] = {
-	MSIOF1_SCK_B_MARK,
-};
-static const unsigned int msiof1_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(5, 3),
-};
-static const unsigned int msiof1_sync_b_mux[] = {
-	MSIOF1_SYNC_B_MARK,
-};
-static const unsigned int msiof1_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(5, 4),
-};
-static const unsigned int msiof1_ss1_b_mux[] = {
-	MSIOF1_SS1_B_MARK,
-};
-static const unsigned int msiof1_ss2_b_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int msiof1_ss2_b_mux[] = {
-	MSIOF1_SS2_B_MARK,
-};
-static const unsigned int msiof1_txd_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(5, 8),
-};
-static const unsigned int msiof1_txd_b_mux[] = {
-	MSIOF1_TXD_B_MARK,
-};
-static const unsigned int msiof1_rxd_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 7),
-};
-static const unsigned int msiof1_rxd_b_mux[] = {
-	MSIOF1_RXD_B_MARK,
-};
-static const unsigned int msiof1_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 17),
-};
-static const unsigned int msiof1_clk_c_mux[] = {
-	MSIOF1_SCK_C_MARK,
-};
-static const unsigned int msiof1_sync_c_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(6, 18),
-};
-static const unsigned int msiof1_sync_c_mux[] = {
-	MSIOF1_SYNC_C_MARK,
-};
-static const unsigned int msiof1_ss1_c_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int msiof1_ss1_c_mux[] = {
-	MSIOF1_SS1_C_MARK,
-};
-static const unsigned int msiof1_ss2_c_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(6, 27),
-};
-static const unsigned int msiof1_ss2_c_mux[] = {
-	MSIOF1_SS2_C_MARK,
-};
-static const unsigned int msiof1_txd_c_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(6, 20),
-};
-static const unsigned int msiof1_txd_c_mux[] = {
-	MSIOF1_TXD_C_MARK,
-};
-static const unsigned int msiof1_rxd_c_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(6, 19),
-};
-static const unsigned int msiof1_rxd_c_mux[] = {
-	MSIOF1_RXD_C_MARK,
-};
-static const unsigned int msiof1_clk_d_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 12),
-};
-static const unsigned int msiof1_clk_d_mux[] = {
-	MSIOF1_SCK_D_MARK,
-};
-static const unsigned int msiof1_sync_d_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(5, 15),
-};
-static const unsigned int msiof1_sync_d_mux[] = {
-	MSIOF1_SYNC_D_MARK,
-};
-static const unsigned int msiof1_ss1_d_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(5, 16),
-};
-static const unsigned int msiof1_ss1_d_mux[] = {
-	MSIOF1_SS1_D_MARK,
-};
-static const unsigned int msiof1_ss2_d_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(5, 21),
-};
-static const unsigned int msiof1_ss2_d_mux[] = {
-	MSIOF1_SS2_D_MARK,
-};
-static const unsigned int msiof1_txd_d_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(5, 14),
-};
-static const unsigned int msiof1_txd_d_mux[] = {
-	MSIOF1_TXD_D_MARK,
-};
-static const unsigned int msiof1_rxd_d_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 13),
-};
-static const unsigned int msiof1_rxd_d_mux[] = {
-	MSIOF1_RXD_D_MARK,
-};
-static const unsigned int msiof1_clk_e_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 0),
-};
-static const unsigned int msiof1_clk_e_mux[] = {
-	MSIOF1_SCK_E_MARK,
-};
-static const unsigned int msiof1_sync_e_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(3, 1),
-};
-static const unsigned int msiof1_sync_e_mux[] = {
-	MSIOF1_SYNC_E_MARK,
-};
-static const unsigned int msiof1_ss1_e_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(3, 4),
-};
-static const unsigned int msiof1_ss1_e_mux[] = {
-	MSIOF1_SS1_E_MARK,
-};
-static const unsigned int msiof1_ss2_e_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(3, 5),
-};
-static const unsigned int msiof1_ss2_e_mux[] = {
-	MSIOF1_SS2_E_MARK,
-};
-static const unsigned int msiof1_txd_e_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(3, 3),
-};
-static const unsigned int msiof1_txd_e_mux[] = {
-	MSIOF1_TXD_E_MARK,
-};
-static const unsigned int msiof1_rxd_e_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(3, 2),
-};
-static const unsigned int msiof1_rxd_e_mux[] = {
-	MSIOF1_RXD_E_MARK,
-};
-static const unsigned int msiof1_clk_f_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 23),
-};
-static const unsigned int msiof1_clk_f_mux[] = {
-	MSIOF1_SCK_F_MARK,
-};
-static const unsigned int msiof1_sync_f_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(5, 24),
-};
-static const unsigned int msiof1_sync_f_mux[] = {
-	MSIOF1_SYNC_F_MARK,
-};
-static const unsigned int msiof1_ss1_f_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(6, 1),
-};
-static const unsigned int msiof1_ss1_f_mux[] = {
-	MSIOF1_SS1_F_MARK,
-};
-static const unsigned int msiof1_ss2_f_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(6, 2),
-};
-static const unsigned int msiof1_ss2_f_mux[] = {
-	MSIOF1_SS2_F_MARK,
-};
-static const unsigned int msiof1_txd_f_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(6, 0),
-};
-static const unsigned int msiof1_txd_f_mux[] = {
-	MSIOF1_TXD_F_MARK,
-};
-static const unsigned int msiof1_rxd_f_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 25),
-};
-static const unsigned int msiof1_rxd_f_mux[] = {
-	MSIOF1_RXD_F_MARK,
-};
-static const unsigned int msiof1_clk_g_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 6),
-};
-static const unsigned int msiof1_clk_g_mux[] = {
-	MSIOF1_SCK_G_MARK,
-};
-static const unsigned int msiof1_sync_g_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(3, 7),
-};
-static const unsigned int msiof1_sync_g_mux[] = {
-	MSIOF1_SYNC_G_MARK,
-};
-static const unsigned int msiof1_ss1_g_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(3, 10),
-};
-static const unsigned int msiof1_ss1_g_mux[] = {
-	MSIOF1_SS1_G_MARK,
-};
-static const unsigned int msiof1_ss2_g_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(3, 11),
-};
-static const unsigned int msiof1_ss2_g_mux[] = {
-	MSIOF1_SS2_G_MARK,
-};
-static const unsigned int msiof1_txd_g_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(3, 9),
-};
-static const unsigned int msiof1_txd_g_mux[] = {
-	MSIOF1_TXD_G_MARK,
-};
-static const unsigned int msiof1_rxd_g_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(3, 8),
-};
-static const unsigned int msiof1_rxd_g_mux[] = {
-	MSIOF1_RXD_G_MARK,
-};
-/* - MSIOF2 ----------------------------------------------------------------- */
-static const unsigned int msiof2_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 9),
-};
-static const unsigned int msiof2_clk_a_mux[] = {
-	MSIOF2_SCK_A_MARK,
-};
-static const unsigned int msiof2_sync_a_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 8),
-};
-static const unsigned int msiof2_sync_a_mux[] = {
-	MSIOF2_SYNC_A_MARK,
-};
-static const unsigned int msiof2_ss1_a_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(1, 6),
-};
-static const unsigned int msiof2_ss1_a_mux[] = {
-	MSIOF2_SS1_A_MARK,
-};
-static const unsigned int msiof2_ss2_a_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(1, 7),
-};
-static const unsigned int msiof2_ss2_a_mux[] = {
-	MSIOF2_SS2_A_MARK,
-};
-static const unsigned int msiof2_txd_a_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 11),
-};
-static const unsigned int msiof2_txd_a_mux[] = {
-	MSIOF2_TXD_A_MARK,
-};
-static const unsigned int msiof2_rxd_a_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 10),
-};
-static const unsigned int msiof2_rxd_a_mux[] = {
-	MSIOF2_RXD_A_MARK,
-};
-static const unsigned int msiof2_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 4),
-};
-static const unsigned int msiof2_clk_b_mux[] = {
-	MSIOF2_SCK_B_MARK,
-};
-static const unsigned int msiof2_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 5),
-};
-static const unsigned int msiof2_sync_b_mux[] = {
-	MSIOF2_SYNC_B_MARK,
-};
-static const unsigned int msiof2_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 0),
-};
-static const unsigned int msiof2_ss1_b_mux[] = {
-	MSIOF2_SS1_B_MARK,
-};
-static const unsigned int msiof2_ss2_b_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 1),
-};
-static const unsigned int msiof2_ss2_b_mux[] = {
-	MSIOF2_SS2_B_MARK,
-};
-static const unsigned int msiof2_txd_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 7),
-};
-static const unsigned int msiof2_txd_b_mux[] = {
-	MSIOF2_TXD_B_MARK,
-};
-static const unsigned int msiof2_rxd_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 6),
-};
-static const unsigned int msiof2_rxd_b_mux[] = {
-	MSIOF2_RXD_B_MARK,
-};
-static const unsigned int msiof2_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 12),
-};
-static const unsigned int msiof2_clk_c_mux[] = {
-	MSIOF2_SCK_C_MARK,
-};
-static const unsigned int msiof2_sync_c_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(2, 11),
-};
-static const unsigned int msiof2_sync_c_mux[] = {
-	MSIOF2_SYNC_C_MARK,
-};
-static const unsigned int msiof2_ss1_c_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(2, 10),
-};
-static const unsigned int msiof2_ss1_c_mux[] = {
-	MSIOF2_SS1_C_MARK,
-};
-static const unsigned int msiof2_ss2_c_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(2, 9),
-};
-static const unsigned int msiof2_ss2_c_mux[] = {
-	MSIOF2_SS2_C_MARK,
-};
-static const unsigned int msiof2_txd_c_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(2, 14),
-};
-static const unsigned int msiof2_txd_c_mux[] = {
-	MSIOF2_TXD_C_MARK,
-};
-static const unsigned int msiof2_rxd_c_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(2, 13),
-};
-static const unsigned int msiof2_rxd_c_mux[] = {
-	MSIOF2_RXD_C_MARK,
-};
-static const unsigned int msiof2_clk_d_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 8),
-};
-static const unsigned int msiof2_clk_d_mux[] = {
-	MSIOF2_SCK_D_MARK,
-};
-static const unsigned int msiof2_sync_d_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 9),
-};
-static const unsigned int msiof2_sync_d_mux[] = {
-	MSIOF2_SYNC_D_MARK,
-};
-static const unsigned int msiof2_ss1_d_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 12),
-};
-static const unsigned int msiof2_ss1_d_mux[] = {
-	MSIOF2_SS1_D_MARK,
-};
-static const unsigned int msiof2_ss2_d_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 13),
-};
-static const unsigned int msiof2_ss2_d_mux[] = {
-	MSIOF2_SS2_D_MARK,
-};
-static const unsigned int msiof2_txd_d_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 11),
-};
-static const unsigned int msiof2_txd_d_mux[] = {
-	MSIOF2_TXD_D_MARK,
-};
-static const unsigned int msiof2_rxd_d_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 10),
-};
-static const unsigned int msiof2_rxd_d_mux[] = {
-	MSIOF2_RXD_D_MARK,
-};
-/* - MSIOF3 ----------------------------------------------------------------- */
-static const unsigned int msiof3_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 0),
-};
-static const unsigned int msiof3_clk_a_mux[] = {
-	MSIOF3_SCK_A_MARK,
-};
-static const unsigned int msiof3_sync_a_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 1),
-};
-static const unsigned int msiof3_sync_a_mux[] = {
-	MSIOF3_SYNC_A_MARK,
-};
-static const unsigned int msiof3_ss1_a_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 14),
-};
-static const unsigned int msiof3_ss1_a_mux[] = {
-	MSIOF3_SS1_A_MARK,
-};
-static const unsigned int msiof3_ss2_a_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 15),
-};
-static const unsigned int msiof3_ss2_a_mux[] = {
-	MSIOF3_SS2_A_MARK,
-};
-static const unsigned int msiof3_txd_a_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 3),
-};
-static const unsigned int msiof3_txd_a_mux[] = {
-	MSIOF3_TXD_A_MARK,
-};
-static const unsigned int msiof3_rxd_a_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 2),
-};
-static const unsigned int msiof3_rxd_a_mux[] = {
-	MSIOF3_RXD_A_MARK,
-};
-static const unsigned int msiof3_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 2),
-};
-static const unsigned int msiof3_clk_b_mux[] = {
-	MSIOF3_SCK_B_MARK,
-};
-static const unsigned int msiof3_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 0),
-};
-static const unsigned int msiof3_sync_b_mux[] = {
-	MSIOF3_SYNC_B_MARK,
-};
-static const unsigned int msiof3_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(1, 4),
-};
-static const unsigned int msiof3_ss1_b_mux[] = {
-	MSIOF3_SS1_B_MARK,
-};
-static const unsigned int msiof3_ss2_b_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(1, 5),
-};
-static const unsigned int msiof3_ss2_b_mux[] = {
-	MSIOF3_SS2_B_MARK,
-};
-static const unsigned int msiof3_txd_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 1),
-};
-static const unsigned int msiof3_txd_b_mux[] = {
-	MSIOF3_TXD_B_MARK,
-};
-static const unsigned int msiof3_rxd_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 3),
-};
-static const unsigned int msiof3_rxd_b_mux[] = {
-	MSIOF3_RXD_B_MARK,
-};
-static const unsigned int msiof3_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 12),
-};
-static const unsigned int msiof3_clk_c_mux[] = {
-	MSIOF3_SCK_C_MARK,
-};
-static const unsigned int msiof3_sync_c_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 13),
-};
-static const unsigned int msiof3_sync_c_mux[] = {
-	MSIOF3_SYNC_C_MARK,
-};
-static const unsigned int msiof3_txd_c_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 15),
-};
-static const unsigned int msiof3_txd_c_mux[] = {
-	MSIOF3_TXD_C_MARK,
-};
-static const unsigned int msiof3_rxd_c_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 14),
-};
-static const unsigned int msiof3_rxd_c_mux[] = {
-	MSIOF3_RXD_C_MARK,
-};
-static const unsigned int msiof3_clk_d_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 22),
-};
-static const unsigned int msiof3_clk_d_mux[] = {
-	MSIOF3_SCK_D_MARK,
-};
-static const unsigned int msiof3_sync_d_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 23),
-};
-static const unsigned int msiof3_sync_d_mux[] = {
-	MSIOF3_SYNC_D_MARK,
-};
-static const unsigned int msiof3_ss1_d_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(1, 26),
-};
-static const unsigned int msiof3_ss1_d_mux[] = {
-	MSIOF3_SS1_D_MARK,
-};
-static const unsigned int msiof3_txd_d_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 25),
-};
-static const unsigned int msiof3_txd_d_mux[] = {
-	MSIOF3_TXD_D_MARK,
-};
-static const unsigned int msiof3_rxd_d_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 24),
-};
-static const unsigned int msiof3_rxd_d_mux[] = {
-	MSIOF3_RXD_D_MARK,
-};
-static const unsigned int msiof3_clk_e_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 3),
-};
-static const unsigned int msiof3_clk_e_mux[] = {
-	MSIOF3_SCK_E_MARK,
-};
-static const unsigned int msiof3_sync_e_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(2, 2),
-};
-static const unsigned int msiof3_sync_e_mux[] = {
-	MSIOF3_SYNC_E_MARK,
-};
-static const unsigned int msiof3_ss1_e_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(2, 1),
-};
-static const unsigned int msiof3_ss1_e_mux[] = {
-	MSIOF3_SS1_E_MARK,
-};
-static const unsigned int msiof3_ss2_e_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int msiof3_ss2_e_mux[] = {
-	MSIOF3_SS2_E_MARK,
-};
-static const unsigned int msiof3_txd_e_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(2, 5),
-};
-static const unsigned int msiof3_txd_e_mux[] = {
-	MSIOF3_TXD_E_MARK,
-};
-static const unsigned int msiof3_rxd_e_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(2, 4),
-};
-static const unsigned int msiof3_rxd_e_mux[] = {
-	MSIOF3_RXD_E_MARK,
-};
-
-/* - PWM0 --------------------------------------------------------------------*/
-static const unsigned int pwm0_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 6),
-};
-static const unsigned int pwm0_mux[] = {
-	PWM0_MARK,
-};
-/* - PWM1 --------------------------------------------------------------------*/
-static const unsigned int pwm1_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 7),
-};
-static const unsigned int pwm1_a_mux[] = {
-	PWM1_A_MARK,
-};
-static const unsigned int pwm1_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 8),
-};
-static const unsigned int pwm1_b_mux[] = {
-	PWM1_B_MARK,
-};
-/* - PWM2 --------------------------------------------------------------------*/
-static const unsigned int pwm2_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 8),
-};
-static const unsigned int pwm2_a_mux[] = {
-	PWM2_A_MARK,
-};
-static const unsigned int pwm2_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 11),
-};
-static const unsigned int pwm2_b_mux[] = {
-	PWM2_B_MARK,
-};
-/* - PWM3 --------------------------------------------------------------------*/
-static const unsigned int pwm3_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 0),
-};
-static const unsigned int pwm3_a_mux[] = {
-	PWM3_A_MARK,
-};
-static const unsigned int pwm3_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 2),
-};
-static const unsigned int pwm3_b_mux[] = {
-	PWM3_B_MARK,
-};
-/* - PWM4 --------------------------------------------------------------------*/
-static const unsigned int pwm4_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 1),
-};
-static const unsigned int pwm4_a_mux[] = {
-	PWM4_A_MARK,
-};
-static const unsigned int pwm4_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 3),
-};
-static const unsigned int pwm4_b_mux[] = {
-	PWM4_B_MARK,
-};
-/* - PWM5 --------------------------------------------------------------------*/
-static const unsigned int pwm5_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 2),
-};
-static const unsigned int pwm5_a_mux[] = {
-	PWM5_A_MARK,
-};
-static const unsigned int pwm5_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 4),
-};
-static const unsigned int pwm5_b_mux[] = {
-	PWM5_B_MARK,
-};
-/* - PWM6 --------------------------------------------------------------------*/
-static const unsigned int pwm6_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 3),
-};
-static const unsigned int pwm6_a_mux[] = {
-	PWM6_A_MARK,
-};
-static const unsigned int pwm6_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 5),
-};
-static const unsigned int pwm6_b_mux[] = {
-	PWM6_B_MARK,
-};
-
-/* - SATA --------------------------------------------------------------------*/
-static const unsigned int sata0_devslp_a_pins[] = {
-	/* DEVSLP */
-	RCAR_GP_PIN(6, 16),
-};
-
-static const unsigned int sata0_devslp_a_mux[] = {
-	SATA_DEVSLP_A_MARK,
-};
-
-static const unsigned int sata0_devslp_b_pins[] = {
-	/* DEVSLP */
-	RCAR_GP_PIN(4, 6),
-};
-
-static const unsigned int sata0_devslp_b_mux[] = {
-	SATA_DEVSLP_B_MARK,
-};
-
-/* - SCIF0 ------------------------------------------------------------------ */
-static const unsigned int scif0_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-};
-static const unsigned int scif0_data_mux[] = {
-	RX0_MARK, TX0_MARK,
-};
-static const unsigned int scif0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int scif0_clk_mux[] = {
-	SCK0_MARK,
-};
-static const unsigned int scif0_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
-};
-static const unsigned int scif0_ctrl_mux[] = {
-	RTS0_N_MARK, CTS0_N_MARK,
-};
-/* - SCIF1 ------------------------------------------------------------------ */
-static const unsigned int scif1_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
-};
-static const unsigned int scif1_data_a_mux[] = {
-	RX1_A_MARK, TX1_A_MARK,
-};
-static const unsigned int scif1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int scif1_clk_mux[] = {
-	SCK1_MARK,
-};
-static const unsigned int scif1_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
-};
-static const unsigned int scif1_ctrl_mux[] = {
-	RTS1_N_MARK, CTS1_N_MARK,
-};
-static const unsigned int scif1_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
-};
-static const unsigned int scif1_data_b_mux[] = {
-	RX1_B_MARK, TX1_B_MARK,
-};
-/* - SCIF2 ------------------------------------------------------------------ */
-static const unsigned int scif2_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
-};
-static const unsigned int scif2_data_a_mux[] = {
-	RX2_A_MARK, TX2_A_MARK,
-};
-static const unsigned int scif2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 9),
-};
-static const unsigned int scif2_clk_mux[] = {
-	SCK2_MARK,
-};
-static const unsigned int scif2_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
-};
-static const unsigned int scif2_data_b_mux[] = {
-	RX2_B_MARK, TX2_B_MARK,
-};
-/* - SCIF3 ------------------------------------------------------------------ */
-static const unsigned int scif3_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
-};
-static const unsigned int scif3_data_a_mux[] = {
-	RX3_A_MARK, TX3_A_MARK,
-};
-static const unsigned int scif3_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 22),
-};
-static const unsigned int scif3_clk_mux[] = {
-	SCK3_MARK,
-};
-static const unsigned int scif3_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
-};
-static const unsigned int scif3_ctrl_mux[] = {
-	RTS3_N_MARK, CTS3_N_MARK,
-};
-static const unsigned int scif3_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
-};
-static const unsigned int scif3_data_b_mux[] = {
-	RX3_B_MARK, TX3_B_MARK,
-};
-/* - SCIF4 ------------------------------------------------------------------ */
-static const unsigned int scif4_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
-};
-static const unsigned int scif4_data_a_mux[] = {
-	RX4_A_MARK, TX4_A_MARK,
-};
-static const unsigned int scif4_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 10),
-};
-static const unsigned int scif4_clk_a_mux[] = {
-	SCK4_A_MARK,
-};
-static const unsigned int scif4_ctrl_a_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
-};
-static const unsigned int scif4_ctrl_a_mux[] = {
-	RTS4_N_A_MARK, CTS4_N_A_MARK,
-};
-static const unsigned int scif4_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-};
-static const unsigned int scif4_data_b_mux[] = {
-	RX4_B_MARK, TX4_B_MARK,
-};
-static const unsigned int scif4_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 5),
-};
-static const unsigned int scif4_clk_b_mux[] = {
-	SCK4_B_MARK,
-};
-static const unsigned int scif4_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
-};
-static const unsigned int scif4_ctrl_b_mux[] = {
-	RTS4_N_B_MARK, CTS4_N_B_MARK,
-};
-static const unsigned int scif4_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-};
-static const unsigned int scif4_data_c_mux[] = {
-	RX4_C_MARK, TX4_C_MARK,
-};
-static const unsigned int scif4_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 8),
-};
-static const unsigned int scif4_clk_c_mux[] = {
-	SCK4_C_MARK,
-};
-static const unsigned int scif4_ctrl_c_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
-};
-static const unsigned int scif4_ctrl_c_mux[] = {
-	RTS4_N_C_MARK, CTS4_N_C_MARK,
-};
-/* - SCIF5 ------------------------------------------------------------------ */
-static const unsigned int scif5_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
-};
-static const unsigned int scif5_data_a_mux[] = {
-	RX5_A_MARK, TX5_A_MARK,
-};
-static const unsigned int scif5_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int scif5_clk_a_mux[] = {
-	SCK5_A_MARK,
-};
-static const unsigned int scif5_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
-};
-static const unsigned int scif5_data_b_mux[] = {
-	RX5_B_MARK, TX5_B_MARK,
-};
-static const unsigned int scif5_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int scif5_clk_b_mux[] = {
-	SCK5_B_MARK,
-};
-/* - SCIF Clock ------------------------------------------------------------- */
-static const unsigned int scif_clk_a_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(6, 23),
-};
-static const unsigned int scif_clk_a_mux[] = {
-	SCIF_CLK_A_MARK,
-};
-static const unsigned int scif_clk_b_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(5, 9),
-};
-static const unsigned int scif_clk_b_mux[] = {
-	SCIF_CLK_B_MARK,
-};
-
-/* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 2),
-};
-
-static const unsigned int sdhi0_data1_mux[] = {
-	SD0_DAT0_MARK,
-};
-
-static const unsigned int sdhi0_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
-	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
-};
-
-static const unsigned int sdhi0_data4_mux[] = {
-	SD0_DAT0_MARK, SD0_DAT1_MARK,
-	SD0_DAT2_MARK, SD0_DAT3_MARK,
-};
-
-static const unsigned int sdhi0_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
-};
-
-static const unsigned int sdhi0_ctrl_mux[] = {
-	SD0_CLK_MARK, SD0_CMD_MARK,
-};
-
-static const unsigned int sdhi0_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(3, 12),
-};
-
-static const unsigned int sdhi0_cd_mux[] = {
-	SD0_CD_MARK,
-};
-
-static const unsigned int sdhi0_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(3, 13),
-};
-
-static const unsigned int sdhi0_wp_mux[] = {
-	SD0_WP_MARK,
-};
-
-/* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 8),
-};
-
-static const unsigned int sdhi1_data1_mux[] = {
-	SD1_DAT0_MARK,
-};
-
-static const unsigned int sdhi1_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-};
-
-static const unsigned int sdhi1_data4_mux[] = {
-	SD1_DAT0_MARK, SD1_DAT1_MARK,
-	SD1_DAT2_MARK, SD1_DAT3_MARK,
-};
-
-static const unsigned int sdhi1_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-};
-
-static const unsigned int sdhi1_ctrl_mux[] = {
-	SD1_CLK_MARK, SD1_CMD_MARK,
-};
-
-static const unsigned int sdhi1_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(3, 14),
-};
-
-static const unsigned int sdhi1_cd_mux[] = {
-	SD1_CD_MARK,
-};
-
-static const unsigned int sdhi1_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(3, 15),
-};
-
-static const unsigned int sdhi1_wp_mux[] = {
-	SD1_WP_MARK,
-};
-
-/* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(4, 2),
-};
-
-static const unsigned int sdhi2_data1_mux[] = {
-	SD2_DAT0_MARK,
-};
-
-static const unsigned int sdhi2_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-};
-
-static const unsigned int sdhi2_data4_mux[] = {
-	SD2_DAT0_MARK, SD2_DAT1_MARK,
-	SD2_DAT2_MARK, SD2_DAT3_MARK,
-};
-
-static const unsigned int sdhi2_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
-	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
-	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-};
-
-static const unsigned int sdhi2_data8_mux[] = {
-	SD2_DAT0_MARK, SD2_DAT1_MARK,
-	SD2_DAT2_MARK, SD2_DAT3_MARK,
-	SD2_DAT4_MARK, SD2_DAT5_MARK,
-	SD2_DAT6_MARK, SD2_DAT7_MARK,
-};
-
-static const unsigned int sdhi2_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
-};
-
-static const unsigned int sdhi2_ctrl_mux[] = {
-	SD2_CLK_MARK, SD2_CMD_MARK,
-};
-
-static const unsigned int sdhi2_cd_a_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(4, 13),
-};
-
-static const unsigned int sdhi2_cd_a_mux[] = {
-	SD2_CD_A_MARK,
-};
-
-static const unsigned int sdhi2_cd_b_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(5, 10),
-};
-
-static const unsigned int sdhi2_cd_b_mux[] = {
-	SD2_CD_B_MARK,
-};
-
-static const unsigned int sdhi2_wp_a_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(4, 14),
-};
-
-static const unsigned int sdhi2_wp_a_mux[] = {
-	SD2_WP_A_MARK,
-};
-
-static const unsigned int sdhi2_wp_b_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(5, 11),
-};
-
-static const unsigned int sdhi2_wp_b_mux[] = {
-	SD2_WP_B_MARK,
-};
-
-static const unsigned int sdhi2_ds_pins[] = {
-	/* DS */
-	RCAR_GP_PIN(4, 6),
-};
-
-static const unsigned int sdhi2_ds_mux[] = {
-	SD2_DS_MARK,
-};
-
-/* - SDHI3 ------------------------------------------------------------------ */
-static const unsigned int sdhi3_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(4, 9),
-};
-
-static const unsigned int sdhi3_data1_mux[] = {
-	SD3_DAT0_MARK,
-};
-
-static const unsigned int sdhi3_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
-	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
-};
-
-static const unsigned int sdhi3_data4_mux[] = {
-	SD3_DAT0_MARK, SD3_DAT1_MARK,
-	SD3_DAT2_MARK, SD3_DAT3_MARK,
-};
-
-static const unsigned int sdhi3_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
-	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
-	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
-	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
-};
-
-static const unsigned int sdhi3_data8_mux[] = {
-	SD3_DAT0_MARK, SD3_DAT1_MARK,
-	SD3_DAT2_MARK, SD3_DAT3_MARK,
-	SD3_DAT4_MARK, SD3_DAT5_MARK,
-	SD3_DAT6_MARK, SD3_DAT7_MARK,
-};
-
-static const unsigned int sdhi3_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
-};
-
-static const unsigned int sdhi3_ctrl_mux[] = {
-	SD3_CLK_MARK, SD3_CMD_MARK,
-};
-
-static const unsigned int sdhi3_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(4, 15),
-};
-
-static const unsigned int sdhi3_cd_mux[] = {
-	SD3_CD_MARK,
-};
-
-static const unsigned int sdhi3_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(4, 16),
-};
-
-static const unsigned int sdhi3_wp_mux[] = {
-	SD3_WP_MARK,
-};
-
-static const unsigned int sdhi3_ds_pins[] = {
-	/* DS */
-	RCAR_GP_PIN(4, 17),
-};
-
-static const unsigned int sdhi3_ds_mux[] = {
-	SD3_DS_MARK,
-};
-
-/* - SSI -------------------------------------------------------------------- */
-static const unsigned int ssi0_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 2),
-};
-static const unsigned int ssi0_data_mux[] = {
-	SSI_SDATA0_MARK,
-};
-static const unsigned int ssi01239_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
-};
-static const unsigned int ssi01239_ctrl_mux[] = {
-	SSI_SCK01239_MARK, SSI_WS01239_MARK,
-};
-static const unsigned int ssi1_data_a_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 3),
-};
-static const unsigned int ssi1_data_a_mux[] = {
-	SSI_SDATA1_A_MARK,
-};
-static const unsigned int ssi1_data_b_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(5, 12),
-};
-static const unsigned int ssi1_data_b_mux[] = {
-	SSI_SDATA1_B_MARK,
-};
-static const unsigned int ssi1_ctrl_a_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
-};
-static const unsigned int ssi1_ctrl_a_mux[] = {
-	SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
-};
-static const unsigned int ssi1_ctrl_b_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
-};
-static const unsigned int ssi1_ctrl_b_mux[] = {
-	SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
-};
-static const unsigned int ssi2_data_a_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 4),
-};
-static const unsigned int ssi2_data_a_mux[] = {
-	SSI_SDATA2_A_MARK,
-};
-static const unsigned int ssi2_data_b_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(5, 13),
-};
-static const unsigned int ssi2_data_b_mux[] = {
-	SSI_SDATA2_B_MARK,
-};
-static const unsigned int ssi2_ctrl_a_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
-};
-static const unsigned int ssi2_ctrl_a_mux[] = {
-	SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
-};
-static const unsigned int ssi2_ctrl_b_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
-};
-static const unsigned int ssi2_ctrl_b_mux[] = {
-	SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
-};
-static const unsigned int ssi3_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 7),
-};
-static const unsigned int ssi3_data_mux[] = {
-	SSI_SDATA3_MARK,
-};
-static const unsigned int ssi349_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
-};
-static const unsigned int ssi349_ctrl_mux[] = {
-	SSI_SCK349_MARK, SSI_WS349_MARK,
-};
-static const unsigned int ssi4_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 10),
-};
-static const unsigned int ssi4_data_mux[] = {
-	SSI_SDATA4_MARK,
-};
-static const unsigned int ssi4_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
-};
-static const unsigned int ssi4_ctrl_mux[] = {
-	SSI_SCK4_MARK, SSI_WS4_MARK,
-};
-static const unsigned int ssi5_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 13),
-};
-static const unsigned int ssi5_data_mux[] = {
-	SSI_SDATA5_MARK,
-};
-static const unsigned int ssi5_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
-};
-static const unsigned int ssi5_ctrl_mux[] = {
-	SSI_SCK5_MARK, SSI_WS5_MARK,
-};
-static const unsigned int ssi6_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 16),
-};
-static const unsigned int ssi6_data_mux[] = {
-	SSI_SDATA6_MARK,
-};
-static const unsigned int ssi6_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
-};
-static const unsigned int ssi6_ctrl_mux[] = {
-	SSI_SCK6_MARK, SSI_WS6_MARK,
-};
-static const unsigned int ssi7_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 19),
-};
-static const unsigned int ssi7_data_mux[] = {
-	SSI_SDATA7_MARK,
-};
-static const unsigned int ssi78_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
-};
-static const unsigned int ssi78_ctrl_mux[] = {
-	SSI_SCK78_MARK, SSI_WS78_MARK,
-};
-static const unsigned int ssi8_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 20),
-};
-static const unsigned int ssi8_data_mux[] = {
-	SSI_SDATA8_MARK,
-};
-static const unsigned int ssi9_data_a_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 21),
-};
-static const unsigned int ssi9_data_a_mux[] = {
-	SSI_SDATA9_A_MARK,
-};
-static const unsigned int ssi9_data_b_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(5, 14),
-};
-static const unsigned int ssi9_data_b_mux[] = {
-	SSI_SDATA9_B_MARK,
-};
-static const unsigned int ssi9_ctrl_a_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
-};
-static const unsigned int ssi9_ctrl_a_mux[] = {
-	SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
-};
-static const unsigned int ssi9_ctrl_b_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
-};
-static const unsigned int ssi9_ctrl_b_mux[] = {
-	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
-};
-
-/* - TMU -------------------------------------------------------------------- */
-static const unsigned int tmu_tclk1_a_pins[] = {
-	/* TCLK */
-	RCAR_GP_PIN(6, 23),
-};
-
-static const unsigned int tmu_tclk1_a_mux[] = {
-	TCLK1_A_MARK,
-};
-
-static const unsigned int tmu_tclk1_b_pins[] = {
-	/* TCLK */
-	RCAR_GP_PIN(5, 19),
-};
-
-static const unsigned int tmu_tclk1_b_mux[] = {
-	TCLK1_B_MARK,
-};
-
-static const unsigned int tmu_tclk2_a_pins[] = {
-	/* TCLK */
-	RCAR_GP_PIN(6, 19),
-};
-
-static const unsigned int tmu_tclk2_a_mux[] = {
-	TCLK2_A_MARK,
-};
-
-static const unsigned int tmu_tclk2_b_pins[] = {
-	/* TCLK */
-	RCAR_GP_PIN(6, 28),
-};
-
-static const unsigned int tmu_tclk2_b_mux[] = {
-	TCLK2_B_MARK,
-};
-
-/* - TPU ------------------------------------------------------------------- */
-static const unsigned int tpu_to0_pins[] = {
-	/* TPU0TO0 */
-	RCAR_GP_PIN(6, 28),
-};
-static const unsigned int tpu_to0_mux[] = {
-	TPU0TO0_MARK,
-};
-static const unsigned int tpu_to1_pins[] = {
-	/* TPU0TO1 */
-	RCAR_GP_PIN(6, 29),
-};
-static const unsigned int tpu_to1_mux[] = {
-	TPU0TO1_MARK,
-};
-static const unsigned int tpu_to2_pins[] = {
-	/* TPU0TO2 */
-	RCAR_GP_PIN(6, 30),
-};
-static const unsigned int tpu_to2_mux[] = {
-	TPU0TO2_MARK,
-};
-static const unsigned int tpu_to3_pins[] = {
-	/* TPU0TO3 */
-	RCAR_GP_PIN(6, 31),
-};
-static const unsigned int tpu_to3_mux[] = {
-	TPU0TO3_MARK,
-};
-
-/* - USB0 ------------------------------------------------------------------- */
-static const unsigned int usb0_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
-};
-
-static const unsigned int usb0_mux[] = {
-	USB0_PWEN_MARK, USB0_OVC_MARK,
-};
-
-/* - USB1 ------------------------------------------------------------------- */
-static const unsigned int usb1_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
-};
-
-static const unsigned int usb1_mux[] = {
-	USB1_PWEN_MARK, USB1_OVC_MARK,
-};
-
-/* - USB30 ------------------------------------------------------------------ */
-static const unsigned int usb30_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
-};
-
-static const unsigned int usb30_mux[] = {
-	USB30_PWEN_MARK, USB30_OVC_MARK,
-};
-
-/* - VIN4 ------------------------------------------------------------------- */
-static const unsigned int vin4_data18_a_pins[] = {
-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-	RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),
-	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
-	RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 3),
-	RCAR_GP_PIN(0, 4),  RCAR_GP_PIN(0, 5),
-	RCAR_GP_PIN(0, 6),  RCAR_GP_PIN(0, 7),
-};
-
-static const unsigned int vin4_data18_a_mux[] = {
-	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-	VI4_DATA10_MARK,  VI4_DATA11_MARK,
-	VI4_DATA12_MARK,  VI4_DATA13_MARK,
-	VI4_DATA14_MARK,  VI4_DATA15_MARK,
-	VI4_DATA18_MARK,  VI4_DATA19_MARK,
-	VI4_DATA20_MARK,  VI4_DATA21_MARK,
-	VI4_DATA22_MARK,  VI4_DATA23_MARK,
-};
-
-static const union vin_data vin4_data_a_pins = {
-	.data24 = {
-		RCAR_GP_PIN(0, 8),  RCAR_GP_PIN(0, 9),
-		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-		RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-		RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-		RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 1),
-		RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),
-		RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
-		RCAR_GP_PIN(0, 0),  RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 3),
-		RCAR_GP_PIN(0, 4),  RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 6),  RCAR_GP_PIN(0, 7),
-	},
-};
-
-static const union vin_data vin4_data_a_mux = {
-	.data24 = {
-		VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
-		VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-		VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-		VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-		VI4_DATA8_MARK,   VI4_DATA9_MARK,
-		VI4_DATA10_MARK,  VI4_DATA11_MARK,
-		VI4_DATA12_MARK,  VI4_DATA13_MARK,
-		VI4_DATA14_MARK,  VI4_DATA15_MARK,
-		VI4_DATA16_MARK,  VI4_DATA17_MARK,
-		VI4_DATA18_MARK,  VI4_DATA19_MARK,
-		VI4_DATA20_MARK,  VI4_DATA21_MARK,
-		VI4_DATA22_MARK,  VI4_DATA23_MARK,
-	},
-};
-
-static const unsigned int vin4_data18_b_pins[] = {
-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-};
-
-static const unsigned int vin4_data18_b_mux[] = {
-	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
-	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
-	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
-	VI4_DATA10_MARK,  VI4_DATA11_MARK,
-	VI4_DATA12_MARK,  VI4_DATA13_MARK,
-	VI4_DATA14_MARK,  VI4_DATA15_MARK,
-	VI4_DATA18_MARK,  VI4_DATA19_MARK,
-	VI4_DATA20_MARK,  VI4_DATA21_MARK,
-	VI4_DATA22_MARK,  VI4_DATA23_MARK,
-};
-
-static const union vin_data vin4_data_b_pins = {
-	.data24 = {
-		RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-		RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-		RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-		RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-		RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-		RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-	},
-};
-
-static const union vin_data vin4_data_b_mux = {
-	.data24 = {
-		VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
-		VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
-		VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
-		VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
-		VI4_DATA8_MARK,   VI4_DATA9_MARK,
-		VI4_DATA10_MARK,  VI4_DATA11_MARK,
-		VI4_DATA12_MARK,  VI4_DATA13_MARK,
-		VI4_DATA14_MARK,  VI4_DATA15_MARK,
-		VI4_DATA16_MARK,  VI4_DATA17_MARK,
-		VI4_DATA18_MARK,  VI4_DATA19_MARK,
-		VI4_DATA20_MARK,  VI4_DATA21_MARK,
-		VI4_DATA22_MARK,  VI4_DATA23_MARK,
-	},
-};
-
-static const unsigned int vin4_sync_pins[] = {
-	/* VSYNC_N, HSYNC_N */
-	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
-};
-
-static const unsigned int vin4_sync_mux[] = {
-	VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
-};
-
-static const unsigned int vin4_field_pins[] = {
-	RCAR_GP_PIN(1, 16),
-};
-
-static const unsigned int vin4_field_mux[] = {
-	VI4_FIELD_MARK,
-};
-
-static const unsigned int vin4_clkenb_pins[] = {
-	RCAR_GP_PIN(1, 19),
-};
-
-static const unsigned int vin4_clkenb_mux[] = {
-	VI4_CLKENB_MARK,
-};
-
-static const unsigned int vin4_clk_pins[] = {
-	RCAR_GP_PIN(1, 27),
-};
-
-static const unsigned int vin4_clk_mux[] = {
-	VI4_CLK_MARK,
-};
-
-/* - VIN5 ------------------------------------------------------------------- */
-static const union vin_data16 vin5_data_pins = {
-	.data16 = {
-		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-		RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-		RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
-	},
-};
-
-static const union vin_data16 vin5_data_mux = {
-	.data16 = {
-		VI5_DATA0_MARK, VI5_DATA1_MARK,
-		VI5_DATA2_MARK, VI5_DATA3_MARK,
-		VI5_DATA4_MARK, VI5_DATA5_MARK,
-		VI5_DATA6_MARK, VI5_DATA7_MARK,
-		VI5_DATA8_MARK,  VI5_DATA9_MARK,
-		VI5_DATA10_MARK, VI5_DATA11_MARK,
-		VI5_DATA12_MARK, VI5_DATA13_MARK,
-		VI5_DATA14_MARK, VI5_DATA15_MARK,
-	},
-};
-
-static const unsigned int vin5_sync_pins[] = {
-	/* VSYNC_N, HSYNC_N */
-	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
-};
-
-static const unsigned int vin5_sync_mux[] = {
-	VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
-};
-
-static const unsigned int vin5_field_pins[] = {
-	RCAR_GP_PIN(1, 11),
-};
-
-static const unsigned int vin5_field_mux[] = {
-	VI5_FIELD_MARK,
-};
-
-static const unsigned int vin5_clkenb_pins[] = {
-	RCAR_GP_PIN(1, 20),
-};
-
-static const unsigned int vin5_clkenb_mux[] = {
-	VI5_CLKENB_MARK,
-};
-
-static const unsigned int vin5_clk_pins[] = {
-	RCAR_GP_PIN(1, 21),
-};
-
-static const unsigned int vin5_clk_mux[] = {
-	VI5_CLK_MARK,
-};
-
-static const struct {
-	struct sh_pfc_pin_group common[318];
-	struct sh_pfc_pin_group automotive[30];
-} pinmux_groups = {
-	.common = {
-		SH_PFC_PIN_GROUP(audio_clk_a_a),
-		SH_PFC_PIN_GROUP(audio_clk_a_b),
-		SH_PFC_PIN_GROUP(audio_clk_a_c),
-		SH_PFC_PIN_GROUP(audio_clk_b_a),
-		SH_PFC_PIN_GROUP(audio_clk_b_b),
-		SH_PFC_PIN_GROUP(audio_clk_c_a),
-		SH_PFC_PIN_GROUP(audio_clk_c_b),
-		SH_PFC_PIN_GROUP(audio_clkout_a),
-		SH_PFC_PIN_GROUP(audio_clkout_b),
-		SH_PFC_PIN_GROUP(audio_clkout_c),
-		SH_PFC_PIN_GROUP(audio_clkout_d),
-		SH_PFC_PIN_GROUP(audio_clkout1_a),
-		SH_PFC_PIN_GROUP(audio_clkout1_b),
-		SH_PFC_PIN_GROUP(audio_clkout2_a),
-		SH_PFC_PIN_GROUP(audio_clkout2_b),
-		SH_PFC_PIN_GROUP(audio_clkout3_a),
-		SH_PFC_PIN_GROUP(audio_clkout3_b),
-		SH_PFC_PIN_GROUP(avb_link),
-		SH_PFC_PIN_GROUP(avb_magic),
-		SH_PFC_PIN_GROUP(avb_phy_int),
-		SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),	/* Deprecated */
-		SH_PFC_PIN_GROUP(avb_mdio),
-		SH_PFC_PIN_GROUP(avb_mii),
-		SH_PFC_PIN_GROUP(avb_avtp_pps),
-		SH_PFC_PIN_GROUP(avb_avtp_match_a),
-		SH_PFC_PIN_GROUP(avb_avtp_capture_a),
-		SH_PFC_PIN_GROUP(avb_avtp_match_b),
-		SH_PFC_PIN_GROUP(avb_avtp_capture_b),
-		SH_PFC_PIN_GROUP(can0_data_a),
-		SH_PFC_PIN_GROUP(can0_data_b),
-		SH_PFC_PIN_GROUP(can1_data),
-		SH_PFC_PIN_GROUP(can_clk),
-		SH_PFC_PIN_GROUP(canfd0_data_a),
-		SH_PFC_PIN_GROUP(canfd0_data_b),
-		SH_PFC_PIN_GROUP(canfd1_data),
-		SH_PFC_PIN_GROUP(du_rgb666),
-		SH_PFC_PIN_GROUP(du_rgb888),
-		SH_PFC_PIN_GROUP(du_clk_out_0),
-		SH_PFC_PIN_GROUP(du_clk_out_1),
-		SH_PFC_PIN_GROUP(du_sync),
-		SH_PFC_PIN_GROUP(du_oddf),
-		SH_PFC_PIN_GROUP(du_cde),
-		SH_PFC_PIN_GROUP(du_disp),
-		SH_PFC_PIN_GROUP(hscif0_data),
-		SH_PFC_PIN_GROUP(hscif0_clk),
-		SH_PFC_PIN_GROUP(hscif0_ctrl),
-		SH_PFC_PIN_GROUP(hscif1_data_a),
-		SH_PFC_PIN_GROUP(hscif1_clk_a),
-		SH_PFC_PIN_GROUP(hscif1_ctrl_a),
-		SH_PFC_PIN_GROUP(hscif1_data_b),
-		SH_PFC_PIN_GROUP(hscif1_clk_b),
-		SH_PFC_PIN_GROUP(hscif1_ctrl_b),
-		SH_PFC_PIN_GROUP(hscif2_data_a),
-		SH_PFC_PIN_GROUP(hscif2_clk_a),
-		SH_PFC_PIN_GROUP(hscif2_ctrl_a),
-		SH_PFC_PIN_GROUP(hscif2_data_b),
-		SH_PFC_PIN_GROUP(hscif2_clk_b),
-		SH_PFC_PIN_GROUP(hscif2_ctrl_b),
-		SH_PFC_PIN_GROUP(hscif2_data_c),
-		SH_PFC_PIN_GROUP(hscif2_clk_c),
-		SH_PFC_PIN_GROUP(hscif2_ctrl_c),
-		SH_PFC_PIN_GROUP(hscif3_data_a),
-		SH_PFC_PIN_GROUP(hscif3_clk),
-		SH_PFC_PIN_GROUP(hscif3_ctrl),
-		SH_PFC_PIN_GROUP(hscif3_data_b),
-		SH_PFC_PIN_GROUP(hscif3_data_c),
-		SH_PFC_PIN_GROUP(hscif3_data_d),
-		SH_PFC_PIN_GROUP(hscif4_data_a),
-		SH_PFC_PIN_GROUP(hscif4_clk),
-		SH_PFC_PIN_GROUP(hscif4_ctrl),
-		SH_PFC_PIN_GROUP(hscif4_data_b),
-		SH_PFC_PIN_GROUP(i2c0),
-		SH_PFC_PIN_GROUP(i2c1_a),
-		SH_PFC_PIN_GROUP(i2c1_b),
-		SH_PFC_PIN_GROUP(i2c2_a),
-		SH_PFC_PIN_GROUP(i2c2_b),
-		SH_PFC_PIN_GROUP(i2c3),
-		SH_PFC_PIN_GROUP(i2c5),
-		SH_PFC_PIN_GROUP(i2c6_a),
-		SH_PFC_PIN_GROUP(i2c6_b),
-		SH_PFC_PIN_GROUP(i2c6_c),
-		SH_PFC_PIN_GROUP(intc_ex_irq0),
-		SH_PFC_PIN_GROUP(intc_ex_irq1),
-		SH_PFC_PIN_GROUP(intc_ex_irq2),
-		SH_PFC_PIN_GROUP(intc_ex_irq3),
-		SH_PFC_PIN_GROUP(intc_ex_irq4),
-		SH_PFC_PIN_GROUP(intc_ex_irq5),
-		SH_PFC_PIN_GROUP(msiof0_clk),
-		SH_PFC_PIN_GROUP(msiof0_sync),
-		SH_PFC_PIN_GROUP(msiof0_ss1),
-		SH_PFC_PIN_GROUP(msiof0_ss2),
-		SH_PFC_PIN_GROUP(msiof0_txd),
-		SH_PFC_PIN_GROUP(msiof0_rxd),
-		SH_PFC_PIN_GROUP(msiof1_clk_a),
-		SH_PFC_PIN_GROUP(msiof1_sync_a),
-		SH_PFC_PIN_GROUP(msiof1_ss1_a),
-		SH_PFC_PIN_GROUP(msiof1_ss2_a),
-		SH_PFC_PIN_GROUP(msiof1_txd_a),
-		SH_PFC_PIN_GROUP(msiof1_rxd_a),
-		SH_PFC_PIN_GROUP(msiof1_clk_b),
-		SH_PFC_PIN_GROUP(msiof1_sync_b),
-		SH_PFC_PIN_GROUP(msiof1_ss1_b),
-		SH_PFC_PIN_GROUP(msiof1_ss2_b),
-		SH_PFC_PIN_GROUP(msiof1_txd_b),
-		SH_PFC_PIN_GROUP(msiof1_rxd_b),
-		SH_PFC_PIN_GROUP(msiof1_clk_c),
-		SH_PFC_PIN_GROUP(msiof1_sync_c),
-		SH_PFC_PIN_GROUP(msiof1_ss1_c),
-		SH_PFC_PIN_GROUP(msiof1_ss2_c),
-		SH_PFC_PIN_GROUP(msiof1_txd_c),
-		SH_PFC_PIN_GROUP(msiof1_rxd_c),
-		SH_PFC_PIN_GROUP(msiof1_clk_d),
-		SH_PFC_PIN_GROUP(msiof1_sync_d),
-		SH_PFC_PIN_GROUP(msiof1_ss1_d),
-		SH_PFC_PIN_GROUP(msiof1_ss2_d),
-		SH_PFC_PIN_GROUP(msiof1_txd_d),
-		SH_PFC_PIN_GROUP(msiof1_rxd_d),
-		SH_PFC_PIN_GROUP(msiof1_clk_e),
-		SH_PFC_PIN_GROUP(msiof1_sync_e),
-		SH_PFC_PIN_GROUP(msiof1_ss1_e),
-		SH_PFC_PIN_GROUP(msiof1_ss2_e),
-		SH_PFC_PIN_GROUP(msiof1_txd_e),
-		SH_PFC_PIN_GROUP(msiof1_rxd_e),
-		SH_PFC_PIN_GROUP(msiof1_clk_f),
-		SH_PFC_PIN_GROUP(msiof1_sync_f),
-		SH_PFC_PIN_GROUP(msiof1_ss1_f),
-		SH_PFC_PIN_GROUP(msiof1_ss2_f),
-		SH_PFC_PIN_GROUP(msiof1_txd_f),
-		SH_PFC_PIN_GROUP(msiof1_rxd_f),
-		SH_PFC_PIN_GROUP(msiof1_clk_g),
-		SH_PFC_PIN_GROUP(msiof1_sync_g),
-		SH_PFC_PIN_GROUP(msiof1_ss1_g),
-		SH_PFC_PIN_GROUP(msiof1_ss2_g),
-		SH_PFC_PIN_GROUP(msiof1_txd_g),
-		SH_PFC_PIN_GROUP(msiof1_rxd_g),
-		SH_PFC_PIN_GROUP(msiof2_clk_a),
-		SH_PFC_PIN_GROUP(msiof2_sync_a),
-		SH_PFC_PIN_GROUP(msiof2_ss1_a),
-		SH_PFC_PIN_GROUP(msiof2_ss2_a),
-		SH_PFC_PIN_GROUP(msiof2_txd_a),
-		SH_PFC_PIN_GROUP(msiof2_rxd_a),
-		SH_PFC_PIN_GROUP(msiof2_clk_b),
-		SH_PFC_PIN_GROUP(msiof2_sync_b),
-		SH_PFC_PIN_GROUP(msiof2_ss1_b),
-		SH_PFC_PIN_GROUP(msiof2_ss2_b),
-		SH_PFC_PIN_GROUP(msiof2_txd_b),
-		SH_PFC_PIN_GROUP(msiof2_rxd_b),
-		SH_PFC_PIN_GROUP(msiof2_clk_c),
-		SH_PFC_PIN_GROUP(msiof2_sync_c),
-		SH_PFC_PIN_GROUP(msiof2_ss1_c),
-		SH_PFC_PIN_GROUP(msiof2_ss2_c),
-		SH_PFC_PIN_GROUP(msiof2_txd_c),
-		SH_PFC_PIN_GROUP(msiof2_rxd_c),
-		SH_PFC_PIN_GROUP(msiof2_clk_d),
-		SH_PFC_PIN_GROUP(msiof2_sync_d),
-		SH_PFC_PIN_GROUP(msiof2_ss1_d),
-		SH_PFC_PIN_GROUP(msiof2_ss2_d),
-		SH_PFC_PIN_GROUP(msiof2_txd_d),
-		SH_PFC_PIN_GROUP(msiof2_rxd_d),
-		SH_PFC_PIN_GROUP(msiof3_clk_a),
-		SH_PFC_PIN_GROUP(msiof3_sync_a),
-		SH_PFC_PIN_GROUP(msiof3_ss1_a),
-		SH_PFC_PIN_GROUP(msiof3_ss2_a),
-		SH_PFC_PIN_GROUP(msiof3_txd_a),
-		SH_PFC_PIN_GROUP(msiof3_rxd_a),
-		SH_PFC_PIN_GROUP(msiof3_clk_b),
-		SH_PFC_PIN_GROUP(msiof3_sync_b),
-		SH_PFC_PIN_GROUP(msiof3_ss1_b),
-		SH_PFC_PIN_GROUP(msiof3_ss2_b),
-		SH_PFC_PIN_GROUP(msiof3_txd_b),
-		SH_PFC_PIN_GROUP(msiof3_rxd_b),
-		SH_PFC_PIN_GROUP(msiof3_clk_c),
-		SH_PFC_PIN_GROUP(msiof3_sync_c),
-		SH_PFC_PIN_GROUP(msiof3_txd_c),
-		SH_PFC_PIN_GROUP(msiof3_rxd_c),
-		SH_PFC_PIN_GROUP(msiof3_clk_d),
-		SH_PFC_PIN_GROUP(msiof3_sync_d),
-		SH_PFC_PIN_GROUP(msiof3_ss1_d),
-		SH_PFC_PIN_GROUP(msiof3_txd_d),
-		SH_PFC_PIN_GROUP(msiof3_rxd_d),
-		SH_PFC_PIN_GROUP(msiof3_clk_e),
-		SH_PFC_PIN_GROUP(msiof3_sync_e),
-		SH_PFC_PIN_GROUP(msiof3_ss1_e),
-		SH_PFC_PIN_GROUP(msiof3_ss2_e),
-		SH_PFC_PIN_GROUP(msiof3_txd_e),
-		SH_PFC_PIN_GROUP(msiof3_rxd_e),
-		SH_PFC_PIN_GROUP(pwm0),
-		SH_PFC_PIN_GROUP(pwm1_a),
-		SH_PFC_PIN_GROUP(pwm1_b),
-		SH_PFC_PIN_GROUP(pwm2_a),
-		SH_PFC_PIN_GROUP(pwm2_b),
-		SH_PFC_PIN_GROUP(pwm3_a),
-		SH_PFC_PIN_GROUP(pwm3_b),
-		SH_PFC_PIN_GROUP(pwm4_a),
-		SH_PFC_PIN_GROUP(pwm4_b),
-		SH_PFC_PIN_GROUP(pwm5_a),
-		SH_PFC_PIN_GROUP(pwm5_b),
-		SH_PFC_PIN_GROUP(pwm6_a),
-		SH_PFC_PIN_GROUP(pwm6_b),
-		SH_PFC_PIN_GROUP(sata0_devslp_a),
-		SH_PFC_PIN_GROUP(sata0_devslp_b),
-		SH_PFC_PIN_GROUP(scif0_data),
-		SH_PFC_PIN_GROUP(scif0_clk),
-		SH_PFC_PIN_GROUP(scif0_ctrl),
-		SH_PFC_PIN_GROUP(scif1_data_a),
-		SH_PFC_PIN_GROUP(scif1_clk),
-		SH_PFC_PIN_GROUP(scif1_ctrl),
-		SH_PFC_PIN_GROUP(scif1_data_b),
-		SH_PFC_PIN_GROUP(scif2_data_a),
-		SH_PFC_PIN_GROUP(scif2_clk),
-		SH_PFC_PIN_GROUP(scif2_data_b),
-		SH_PFC_PIN_GROUP(scif3_data_a),
-		SH_PFC_PIN_GROUP(scif3_clk),
-		SH_PFC_PIN_GROUP(scif3_ctrl),
-		SH_PFC_PIN_GROUP(scif3_data_b),
-		SH_PFC_PIN_GROUP(scif4_data_a),
-		SH_PFC_PIN_GROUP(scif4_clk_a),
-		SH_PFC_PIN_GROUP(scif4_ctrl_a),
-		SH_PFC_PIN_GROUP(scif4_data_b),
-		SH_PFC_PIN_GROUP(scif4_clk_b),
-		SH_PFC_PIN_GROUP(scif4_ctrl_b),
-		SH_PFC_PIN_GROUP(scif4_data_c),
-		SH_PFC_PIN_GROUP(scif4_clk_c),
-		SH_PFC_PIN_GROUP(scif4_ctrl_c),
-		SH_PFC_PIN_GROUP(scif5_data_a),
-		SH_PFC_PIN_GROUP(scif5_clk_a),
-		SH_PFC_PIN_GROUP(scif5_data_b),
-		SH_PFC_PIN_GROUP(scif5_clk_b),
-		SH_PFC_PIN_GROUP(scif_clk_a),
-		SH_PFC_PIN_GROUP(scif_clk_b),
-		SH_PFC_PIN_GROUP(sdhi0_data1),
-		SH_PFC_PIN_GROUP(sdhi0_data4),
-		SH_PFC_PIN_GROUP(sdhi0_ctrl),
-		SH_PFC_PIN_GROUP(sdhi0_cd),
-		SH_PFC_PIN_GROUP(sdhi0_wp),
-		SH_PFC_PIN_GROUP(sdhi1_data1),
-		SH_PFC_PIN_GROUP(sdhi1_data4),
-		SH_PFC_PIN_GROUP(sdhi1_ctrl),
-		SH_PFC_PIN_GROUP(sdhi1_cd),
-		SH_PFC_PIN_GROUP(sdhi1_wp),
-		SH_PFC_PIN_GROUP(sdhi2_data1),
-		SH_PFC_PIN_GROUP(sdhi2_data4),
-		SH_PFC_PIN_GROUP(sdhi2_data8),
-		SH_PFC_PIN_GROUP(sdhi2_ctrl),
-		SH_PFC_PIN_GROUP(sdhi2_cd_a),
-		SH_PFC_PIN_GROUP(sdhi2_wp_a),
-		SH_PFC_PIN_GROUP(sdhi2_cd_b),
-		SH_PFC_PIN_GROUP(sdhi2_wp_b),
-		SH_PFC_PIN_GROUP(sdhi2_ds),
-		SH_PFC_PIN_GROUP(sdhi3_data1),
-		SH_PFC_PIN_GROUP(sdhi3_data4),
-		SH_PFC_PIN_GROUP(sdhi3_data8),
-		SH_PFC_PIN_GROUP(sdhi3_ctrl),
-		SH_PFC_PIN_GROUP(sdhi3_cd),
-		SH_PFC_PIN_GROUP(sdhi3_wp),
-		SH_PFC_PIN_GROUP(sdhi3_ds),
-		SH_PFC_PIN_GROUP(ssi0_data),
-		SH_PFC_PIN_GROUP(ssi01239_ctrl),
-		SH_PFC_PIN_GROUP(ssi1_data_a),
-		SH_PFC_PIN_GROUP(ssi1_data_b),
-		SH_PFC_PIN_GROUP(ssi1_ctrl_a),
-		SH_PFC_PIN_GROUP(ssi1_ctrl_b),
-		SH_PFC_PIN_GROUP(ssi2_data_a),
-		SH_PFC_PIN_GROUP(ssi2_data_b),
-		SH_PFC_PIN_GROUP(ssi2_ctrl_a),
-		SH_PFC_PIN_GROUP(ssi2_ctrl_b),
-		SH_PFC_PIN_GROUP(ssi3_data),
-		SH_PFC_PIN_GROUP(ssi349_ctrl),
-		SH_PFC_PIN_GROUP(ssi4_data),
-		SH_PFC_PIN_GROUP(ssi4_ctrl),
-		SH_PFC_PIN_GROUP(ssi5_data),
-		SH_PFC_PIN_GROUP(ssi5_ctrl),
-		SH_PFC_PIN_GROUP(ssi6_data),
-		SH_PFC_PIN_GROUP(ssi6_ctrl),
-		SH_PFC_PIN_GROUP(ssi7_data),
-		SH_PFC_PIN_GROUP(ssi78_ctrl),
-		SH_PFC_PIN_GROUP(ssi8_data),
-		SH_PFC_PIN_GROUP(ssi9_data_a),
-		SH_PFC_PIN_GROUP(ssi9_data_b),
-		SH_PFC_PIN_GROUP(ssi9_ctrl_a),
-		SH_PFC_PIN_GROUP(ssi9_ctrl_b),
-		SH_PFC_PIN_GROUP(tmu_tclk1_a),
-		SH_PFC_PIN_GROUP(tmu_tclk1_b),
-		SH_PFC_PIN_GROUP(tmu_tclk2_a),
-		SH_PFC_PIN_GROUP(tmu_tclk2_b),
-		SH_PFC_PIN_GROUP(tpu_to0),
-		SH_PFC_PIN_GROUP(tpu_to1),
-		SH_PFC_PIN_GROUP(tpu_to2),
-		SH_PFC_PIN_GROUP(tpu_to3),
-		SH_PFC_PIN_GROUP(usb0),
-		SH_PFC_PIN_GROUP(usb1),
-		SH_PFC_PIN_GROUP(usb30),
-		VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
-		SH_PFC_PIN_GROUP(vin4_data18_a),
-		VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
-		SH_PFC_PIN_GROUP(vin4_data18_b),
-		VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
-		SH_PFC_PIN_GROUP(vin4_sync),
-		SH_PFC_PIN_GROUP(vin4_field),
-		SH_PFC_PIN_GROUP(vin4_clkenb),
-		SH_PFC_PIN_GROUP(vin4_clk),
-		VIN_DATA_PIN_GROUP(vin5_data, 8),
-		VIN_DATA_PIN_GROUP(vin5_data, 10),
-		VIN_DATA_PIN_GROUP(vin5_data, 12),
-		VIN_DATA_PIN_GROUP(vin5_data, 16),
-		SH_PFC_PIN_GROUP(vin5_sync),
-		SH_PFC_PIN_GROUP(vin5_field),
-		SH_PFC_PIN_GROUP(vin5_clkenb),
-		SH_PFC_PIN_GROUP(vin5_clk),
-	},
-	.automotive = {
-		SH_PFC_PIN_GROUP(drif0_ctrl_a),
-		SH_PFC_PIN_GROUP(drif0_data0_a),
-		SH_PFC_PIN_GROUP(drif0_data1_a),
-		SH_PFC_PIN_GROUP(drif0_ctrl_b),
-		SH_PFC_PIN_GROUP(drif0_data0_b),
-		SH_PFC_PIN_GROUP(drif0_data1_b),
-		SH_PFC_PIN_GROUP(drif0_ctrl_c),
-		SH_PFC_PIN_GROUP(drif0_data0_c),
-		SH_PFC_PIN_GROUP(drif0_data1_c),
-		SH_PFC_PIN_GROUP(drif1_ctrl_a),
-		SH_PFC_PIN_GROUP(drif1_data0_a),
-		SH_PFC_PIN_GROUP(drif1_data1_a),
-		SH_PFC_PIN_GROUP(drif1_ctrl_b),
-		SH_PFC_PIN_GROUP(drif1_data0_b),
-		SH_PFC_PIN_GROUP(drif1_data1_b),
-		SH_PFC_PIN_GROUP(drif1_ctrl_c),
-		SH_PFC_PIN_GROUP(drif1_data0_c),
-		SH_PFC_PIN_GROUP(drif1_data1_c),
-		SH_PFC_PIN_GROUP(drif2_ctrl_a),
-		SH_PFC_PIN_GROUP(drif2_data0_a),
-		SH_PFC_PIN_GROUP(drif2_data1_a),
-		SH_PFC_PIN_GROUP(drif2_ctrl_b),
-		SH_PFC_PIN_GROUP(drif2_data0_b),
-		SH_PFC_PIN_GROUP(drif2_data1_b),
-		SH_PFC_PIN_GROUP(drif3_ctrl_a),
-		SH_PFC_PIN_GROUP(drif3_data0_a),
-		SH_PFC_PIN_GROUP(drif3_data1_a),
-		SH_PFC_PIN_GROUP(drif3_ctrl_b),
-		SH_PFC_PIN_GROUP(drif3_data0_b),
-		SH_PFC_PIN_GROUP(drif3_data1_b),
-	}
-};
-
-static const char * const audio_clk_groups[] = {
-	"audio_clk_a_a",
-	"audio_clk_a_b",
-	"audio_clk_a_c",
-	"audio_clk_b_a",
-	"audio_clk_b_b",
-	"audio_clk_c_a",
-	"audio_clk_c_b",
-	"audio_clkout_a",
-	"audio_clkout_b",
-	"audio_clkout_c",
-	"audio_clkout_d",
-	"audio_clkout1_a",
-	"audio_clkout1_b",
-	"audio_clkout2_a",
-	"audio_clkout2_b",
-	"audio_clkout3_a",
-	"audio_clkout3_b",
-};
-
-static const char * const avb_groups[] = {
-	"avb_link",
-	"avb_magic",
-	"avb_phy_int",
-	"avb_mdc",	/* Deprecated, please use "avb_mdio" instead */
-	"avb_mdio",
-	"avb_mii",
-	"avb_avtp_pps",
-	"avb_avtp_match_a",
-	"avb_avtp_capture_a",
-	"avb_avtp_match_b",
-	"avb_avtp_capture_b",
-};
-
-static const char * const can0_groups[] = {
-	"can0_data_a",
-	"can0_data_b",
-};
-
-static const char * const can1_groups[] = {
-	"can1_data",
-};
-
-static const char * const can_clk_groups[] = {
-	"can_clk",
-};
-
-static const char * const canfd0_groups[] = {
-	"canfd0_data_a",
-	"canfd0_data_b",
-};
-
-static const char * const canfd1_groups[] = {
-	"canfd1_data",
-};
-
-static const char * const drif0_groups[] = {
-	"drif0_ctrl_a",
-	"drif0_data0_a",
-	"drif0_data1_a",
-	"drif0_ctrl_b",
-	"drif0_data0_b",
-	"drif0_data1_b",
-	"drif0_ctrl_c",
-	"drif0_data0_c",
-	"drif0_data1_c",
-};
-
-static const char * const drif1_groups[] = {
-	"drif1_ctrl_a",
-	"drif1_data0_a",
-	"drif1_data1_a",
-	"drif1_ctrl_b",
-	"drif1_data0_b",
-	"drif1_data1_b",
-	"drif1_ctrl_c",
-	"drif1_data0_c",
-	"drif1_data1_c",
-};
-
-static const char * const drif2_groups[] = {
-	"drif2_ctrl_a",
-	"drif2_data0_a",
-	"drif2_data1_a",
-	"drif2_ctrl_b",
-	"drif2_data0_b",
-	"drif2_data1_b",
-};
-
-static const char * const drif3_groups[] = {
-	"drif3_ctrl_a",
-	"drif3_data0_a",
-	"drif3_data1_a",
-	"drif3_ctrl_b",
-	"drif3_data0_b",
-	"drif3_data1_b",
-};
-
-static const char * const du_groups[] = {
-	"du_rgb666",
-	"du_rgb888",
-	"du_clk_out_0",
-	"du_clk_out_1",
-	"du_sync",
-	"du_oddf",
-	"du_cde",
-	"du_disp",
-};
-
-static const char * const hscif0_groups[] = {
-	"hscif0_data",
-	"hscif0_clk",
-	"hscif0_ctrl",
-};
-
-static const char * const hscif1_groups[] = {
-	"hscif1_data_a",
-	"hscif1_clk_a",
-	"hscif1_ctrl_a",
-	"hscif1_data_b",
-	"hscif1_clk_b",
-	"hscif1_ctrl_b",
-};
-
-static const char * const hscif2_groups[] = {
-	"hscif2_data_a",
-	"hscif2_clk_a",
-	"hscif2_ctrl_a",
-	"hscif2_data_b",
-	"hscif2_clk_b",
-	"hscif2_ctrl_b",
-	"hscif2_data_c",
-	"hscif2_clk_c",
-	"hscif2_ctrl_c",
-};
-
-static const char * const hscif3_groups[] = {
-	"hscif3_data_a",
-	"hscif3_clk",
-	"hscif3_ctrl",
-	"hscif3_data_b",
-	"hscif3_data_c",
-	"hscif3_data_d",
-};
-
-static const char * const hscif4_groups[] = {
-	"hscif4_data_a",
-	"hscif4_clk",
-	"hscif4_ctrl",
-	"hscif4_data_b",
-};
-
-static const char * const i2c0_groups[] = {
-	"i2c0",
-};
-
-static const char * const i2c1_groups[] = {
-	"i2c1_a",
-	"i2c1_b",
-};
-
-static const char * const i2c2_groups[] = {
-	"i2c2_a",
-	"i2c2_b",
-};
-
-static const char * const i2c3_groups[] = {
-	"i2c3",
-};
-
-static const char * const i2c5_groups[] = {
-	"i2c5",
-};
-
-static const char * const i2c6_groups[] = {
-	"i2c6_a",
-	"i2c6_b",
-	"i2c6_c",
-};
-
-static const char * const intc_ex_groups[] = {
-	"intc_ex_irq0",
-	"intc_ex_irq1",
-	"intc_ex_irq2",
-	"intc_ex_irq3",
-	"intc_ex_irq4",
-	"intc_ex_irq5",
-};
-
-static const char * const msiof0_groups[] = {
-	"msiof0_clk",
-	"msiof0_sync",
-	"msiof0_ss1",
-	"msiof0_ss2",
-	"msiof0_txd",
-	"msiof0_rxd",
-};
-
-static const char * const msiof1_groups[] = {
-	"msiof1_clk_a",
-	"msiof1_sync_a",
-	"msiof1_ss1_a",
-	"msiof1_ss2_a",
-	"msiof1_txd_a",
-	"msiof1_rxd_a",
-	"msiof1_clk_b",
-	"msiof1_sync_b",
-	"msiof1_ss1_b",
-	"msiof1_ss2_b",
-	"msiof1_txd_b",
-	"msiof1_rxd_b",
-	"msiof1_clk_c",
-	"msiof1_sync_c",
-	"msiof1_ss1_c",
-	"msiof1_ss2_c",
-	"msiof1_txd_c",
-	"msiof1_rxd_c",
-	"msiof1_clk_d",
-	"msiof1_sync_d",
-	"msiof1_ss1_d",
-	"msiof1_ss2_d",
-	"msiof1_txd_d",
-	"msiof1_rxd_d",
-	"msiof1_clk_e",
-	"msiof1_sync_e",
-	"msiof1_ss1_e",
-	"msiof1_ss2_e",
-	"msiof1_txd_e",
-	"msiof1_rxd_e",
-	"msiof1_clk_f",
-	"msiof1_sync_f",
-	"msiof1_ss1_f",
-	"msiof1_ss2_f",
-	"msiof1_txd_f",
-	"msiof1_rxd_f",
-	"msiof1_clk_g",
-	"msiof1_sync_g",
-	"msiof1_ss1_g",
-	"msiof1_ss2_g",
-	"msiof1_txd_g",
-	"msiof1_rxd_g",
-};
-
-static const char * const msiof2_groups[] = {
-	"msiof2_clk_a",
-	"msiof2_sync_a",
-	"msiof2_ss1_a",
-	"msiof2_ss2_a",
-	"msiof2_txd_a",
-	"msiof2_rxd_a",
-	"msiof2_clk_b",
-	"msiof2_sync_b",
-	"msiof2_ss1_b",
-	"msiof2_ss2_b",
-	"msiof2_txd_b",
-	"msiof2_rxd_b",
-	"msiof2_clk_c",
-	"msiof2_sync_c",
-	"msiof2_ss1_c",
-	"msiof2_ss2_c",
-	"msiof2_txd_c",
-	"msiof2_rxd_c",
-	"msiof2_clk_d",
-	"msiof2_sync_d",
-	"msiof2_ss1_d",
-	"msiof2_ss2_d",
-	"msiof2_txd_d",
-	"msiof2_rxd_d",
-};
-
-static const char * const msiof3_groups[] = {
-	"msiof3_clk_a",
-	"msiof3_sync_a",
-	"msiof3_ss1_a",
-	"msiof3_ss2_a",
-	"msiof3_txd_a",
-	"msiof3_rxd_a",
-	"msiof3_clk_b",
-	"msiof3_sync_b",
-	"msiof3_ss1_b",
-	"msiof3_ss2_b",
-	"msiof3_txd_b",
-	"msiof3_rxd_b",
-	"msiof3_clk_c",
-	"msiof3_sync_c",
-	"msiof3_txd_c",
-	"msiof3_rxd_c",
-	"msiof3_clk_d",
-	"msiof3_sync_d",
-	"msiof3_ss1_d",
-	"msiof3_txd_d",
-	"msiof3_rxd_d",
-	"msiof3_clk_e",
-	"msiof3_sync_e",
-	"msiof3_ss1_e",
-	"msiof3_ss2_e",
-	"msiof3_txd_e",
-	"msiof3_rxd_e",
-};
-
-static const char * const pwm0_groups[] = {
-	"pwm0",
-};
-
-static const char * const pwm1_groups[] = {
-	"pwm1_a",
-	"pwm1_b",
-};
-
-static const char * const pwm2_groups[] = {
-	"pwm2_a",
-	"pwm2_b",
-};
-
-static const char * const pwm3_groups[] = {
-	"pwm3_a",
-	"pwm3_b",
-};
-
-static const char * const pwm4_groups[] = {
-	"pwm4_a",
-	"pwm4_b",
-};
-
-static const char * const pwm5_groups[] = {
-	"pwm5_a",
-	"pwm5_b",
-};
-
-static const char * const pwm6_groups[] = {
-	"pwm6_a",
-	"pwm6_b",
-};
-
-static const char * const sata0_groups[] = {
-	"sata0_devslp_a",
-	"sata0_devslp_b",
-};
-
-static const char * const scif0_groups[] = {
-	"scif0_data",
-	"scif0_clk",
-	"scif0_ctrl",
-};
-
-static const char * const scif1_groups[] = {
-	"scif1_data_a",
-	"scif1_clk",
-	"scif1_ctrl",
-	"scif1_data_b",
-};
-static const char * const scif2_groups[] = {
-	"scif2_data_a",
-	"scif2_clk",
-	"scif2_data_b",
-};
-
-static const char * const scif3_groups[] = {
-	"scif3_data_a",
-	"scif3_clk",
-	"scif3_ctrl",
-	"scif3_data_b",
-};
-
-static const char * const scif4_groups[] = {
-	"scif4_data_a",
-	"scif4_clk_a",
-	"scif4_ctrl_a",
-	"scif4_data_b",
-	"scif4_clk_b",
-	"scif4_ctrl_b",
-	"scif4_data_c",
-	"scif4_clk_c",
-	"scif4_ctrl_c",
-};
-
-static const char * const scif5_groups[] = {
-	"scif5_data_a",
-	"scif5_clk_a",
-	"scif5_data_b",
-	"scif5_clk_b",
-};
-
-static const char * const scif_clk_groups[] = {
-	"scif_clk_a",
-	"scif_clk_b",
-};
-
-static const char * const sdhi0_groups[] = {
-	"sdhi0_data1",
-	"sdhi0_data4",
-	"sdhi0_ctrl",
-	"sdhi0_cd",
-	"sdhi0_wp",
-};
-
-static const char * const sdhi1_groups[] = {
-	"sdhi1_data1",
-	"sdhi1_data4",
-	"sdhi1_ctrl",
-	"sdhi1_cd",
-	"sdhi1_wp",
-};
-
-static const char * const sdhi2_groups[] = {
-	"sdhi2_data1",
-	"sdhi2_data4",
-	"sdhi2_data8",
-	"sdhi2_ctrl",
-	"sdhi2_cd_a",
-	"sdhi2_wp_a",
-	"sdhi2_cd_b",
-	"sdhi2_wp_b",
-	"sdhi2_ds",
-};
-
-static const char * const sdhi3_groups[] = {
-	"sdhi3_data1",
-	"sdhi3_data4",
-	"sdhi3_data8",
-	"sdhi3_ctrl",
-	"sdhi3_cd",
-	"sdhi3_wp",
-	"sdhi3_ds",
-};
-
-static const char * const ssi_groups[] = {
-	"ssi0_data",
-	"ssi01239_ctrl",
-	"ssi1_data_a",
-	"ssi1_data_b",
-	"ssi1_ctrl_a",
-	"ssi1_ctrl_b",
-	"ssi2_data_a",
-	"ssi2_data_b",
-	"ssi2_ctrl_a",
-	"ssi2_ctrl_b",
-	"ssi3_data",
-	"ssi349_ctrl",
-	"ssi4_data",
-	"ssi4_ctrl",
-	"ssi5_data",
-	"ssi5_ctrl",
-	"ssi6_data",
-	"ssi6_ctrl",
-	"ssi7_data",
-	"ssi78_ctrl",
-	"ssi8_data",
-	"ssi9_data_a",
-	"ssi9_data_b",
-	"ssi9_ctrl_a",
-	"ssi9_ctrl_b",
-};
-
-static const char * const tmu_groups[] = {
-	"tmu_tclk1_a",
-	"tmu_tclk1_b",
-	"tmu_tclk2_a",
-	"tmu_tclk2_b",
-};
-
-static const char * const tpu_groups[] = {
-	"tpu_to0",
-	"tpu_to1",
-	"tpu_to2",
-	"tpu_to3",
-};
-
-static const char * const usb0_groups[] = {
-	"usb0",
-};
-
-static const char * const usb1_groups[] = {
-	"usb1",
-};
-
-static const char * const usb30_groups[] = {
-	"usb30",
-};
-
-static const char * const vin4_groups[] = {
-	"vin4_data8_a",
-	"vin4_data10_a",
-	"vin4_data12_a",
-	"vin4_data16_a",
-	"vin4_data18_a",
-	"vin4_data20_a",
-	"vin4_data24_a",
-	"vin4_data8_b",
-	"vin4_data10_b",
-	"vin4_data12_b",
-	"vin4_data16_b",
-	"vin4_data18_b",
-	"vin4_data20_b",
-	"vin4_data24_b",
-	"vin4_sync",
-	"vin4_field",
-	"vin4_clkenb",
-	"vin4_clk",
-};
-
-static const char * const vin5_groups[] = {
-	"vin5_data8",
-	"vin5_data10",
-	"vin5_data12",
-	"vin5_data16",
-	"vin5_sync",
-	"vin5_field",
-	"vin5_clkenb",
-	"vin5_clk",
-};
-
-static const struct {
-	struct sh_pfc_function common[51];
-	struct sh_pfc_function automotive[4];
-} pinmux_functions = {
-	.common = {
-		SH_PFC_FUNCTION(audio_clk),
-		SH_PFC_FUNCTION(avb),
-		SH_PFC_FUNCTION(can0),
-		SH_PFC_FUNCTION(can1),
-		SH_PFC_FUNCTION(can_clk),
-		SH_PFC_FUNCTION(canfd0),
-		SH_PFC_FUNCTION(canfd1),
-		SH_PFC_FUNCTION(du),
-		SH_PFC_FUNCTION(hscif0),
-		SH_PFC_FUNCTION(hscif1),
-		SH_PFC_FUNCTION(hscif2),
-		SH_PFC_FUNCTION(hscif3),
-		SH_PFC_FUNCTION(hscif4),
-		SH_PFC_FUNCTION(i2c0),
-		SH_PFC_FUNCTION(i2c1),
-		SH_PFC_FUNCTION(i2c2),
-		SH_PFC_FUNCTION(i2c3),
-		SH_PFC_FUNCTION(i2c5),
-		SH_PFC_FUNCTION(i2c6),
-		SH_PFC_FUNCTION(intc_ex),
-		SH_PFC_FUNCTION(msiof0),
-		SH_PFC_FUNCTION(msiof1),
-		SH_PFC_FUNCTION(msiof2),
-		SH_PFC_FUNCTION(msiof3),
-		SH_PFC_FUNCTION(pwm0),
-		SH_PFC_FUNCTION(pwm1),
-		SH_PFC_FUNCTION(pwm2),
-		SH_PFC_FUNCTION(pwm3),
-		SH_PFC_FUNCTION(pwm4),
-		SH_PFC_FUNCTION(pwm5),
-		SH_PFC_FUNCTION(pwm6),
-		SH_PFC_FUNCTION(sata0),
-		SH_PFC_FUNCTION(scif0),
-		SH_PFC_FUNCTION(scif1),
-		SH_PFC_FUNCTION(scif2),
-		SH_PFC_FUNCTION(scif3),
-		SH_PFC_FUNCTION(scif4),
-		SH_PFC_FUNCTION(scif5),
-		SH_PFC_FUNCTION(scif_clk),
-		SH_PFC_FUNCTION(sdhi0),
-		SH_PFC_FUNCTION(sdhi1),
-		SH_PFC_FUNCTION(sdhi2),
-		SH_PFC_FUNCTION(sdhi3),
-		SH_PFC_FUNCTION(ssi),
-		SH_PFC_FUNCTION(tmu),
-		SH_PFC_FUNCTION(tpu),
-		SH_PFC_FUNCTION(usb0),
-		SH_PFC_FUNCTION(usb1),
-		SH_PFC_FUNCTION(usb30),
-		SH_PFC_FUNCTION(vin4),
-		SH_PFC_FUNCTION(vin5),
-	},
-	.automotive = {
-		SH_PFC_FUNCTION(drif0),
-		SH_PFC_FUNCTION(drif1),
-		SH_PFC_FUNCTION(drif2),
-		SH_PFC_FUNCTION(drif3),
-	}
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-#define F_(x, y)	FN_##y
-#define FM(x)		FN_##x
-	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_0_15_FN,	GPSR0_15,
-		GP_0_14_FN,	GPSR0_14,
-		GP_0_13_FN,	GPSR0_13,
-		GP_0_12_FN,	GPSR0_12,
-		GP_0_11_FN,	GPSR0_11,
-		GP_0_10_FN,	GPSR0_10,
-		GP_0_9_FN,	GPSR0_9,
-		GP_0_8_FN,	GPSR0_8,
-		GP_0_7_FN,	GPSR0_7,
-		GP_0_6_FN,	GPSR0_6,
-		GP_0_5_FN,	GPSR0_5,
-		GP_0_4_FN,	GPSR0_4,
-		GP_0_3_FN,	GPSR0_3,
-		GP_0_2_FN,	GPSR0_2,
-		GP_0_1_FN,	GPSR0_1,
-		GP_0_0_FN,	GPSR0_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_1_28_FN,	GPSR1_28,
-		GP_1_27_FN,	GPSR1_27,
-		GP_1_26_FN,	GPSR1_26,
-		GP_1_25_FN,	GPSR1_25,
-		GP_1_24_FN,	GPSR1_24,
-		GP_1_23_FN,	GPSR1_23,
-		GP_1_22_FN,	GPSR1_22,
-		GP_1_21_FN,	GPSR1_21,
-		GP_1_20_FN,	GPSR1_20,
-		GP_1_19_FN,	GPSR1_19,
-		GP_1_18_FN,	GPSR1_18,
-		GP_1_17_FN,	GPSR1_17,
-		GP_1_16_FN,	GPSR1_16,
-		GP_1_15_FN,	GPSR1_15,
-		GP_1_14_FN,	GPSR1_14,
-		GP_1_13_FN,	GPSR1_13,
-		GP_1_12_FN,	GPSR1_12,
-		GP_1_11_FN,	GPSR1_11,
-		GP_1_10_FN,	GPSR1_10,
-		GP_1_9_FN,	GPSR1_9,
-		GP_1_8_FN,	GPSR1_8,
-		GP_1_7_FN,	GPSR1_7,
-		GP_1_6_FN,	GPSR1_6,
-		GP_1_5_FN,	GPSR1_5,
-		GP_1_4_FN,	GPSR1_4,
-		GP_1_3_FN,	GPSR1_3,
-		GP_1_2_FN,	GPSR1_2,
-		GP_1_1_FN,	GPSR1_1,
-		GP_1_0_FN,	GPSR1_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_2_14_FN,	GPSR2_14,
-		GP_2_13_FN,	GPSR2_13,
-		GP_2_12_FN,	GPSR2_12,
-		GP_2_11_FN,	GPSR2_11,
-		GP_2_10_FN,	GPSR2_10,
-		GP_2_9_FN,	GPSR2_9,
-		GP_2_8_FN,	GPSR2_8,
-		GP_2_7_FN,	GPSR2_7,
-		GP_2_6_FN,	GPSR2_6,
-		GP_2_5_FN,	GPSR2_5,
-		GP_2_4_FN,	GPSR2_4,
-		GP_2_3_FN,	GPSR2_3,
-		GP_2_2_FN,	GPSR2_2,
-		GP_2_1_FN,	GPSR2_1,
-		GP_2_0_FN,	GPSR2_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_3_15_FN,	GPSR3_15,
-		GP_3_14_FN,	GPSR3_14,
-		GP_3_13_FN,	GPSR3_13,
-		GP_3_12_FN,	GPSR3_12,
-		GP_3_11_FN,	GPSR3_11,
-		GP_3_10_FN,	GPSR3_10,
-		GP_3_9_FN,	GPSR3_9,
-		GP_3_8_FN,	GPSR3_8,
-		GP_3_7_FN,	GPSR3_7,
-		GP_3_6_FN,	GPSR3_6,
-		GP_3_5_FN,	GPSR3_5,
-		GP_3_4_FN,	GPSR3_4,
-		GP_3_3_FN,	GPSR3_3,
-		GP_3_2_FN,	GPSR3_2,
-		GP_3_1_FN,	GPSR3_1,
-		GP_3_0_FN,	GPSR3_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_4_17_FN,	GPSR4_17,
-		GP_4_16_FN,	GPSR4_16,
-		GP_4_15_FN,	GPSR4_15,
-		GP_4_14_FN,	GPSR4_14,
-		GP_4_13_FN,	GPSR4_13,
-		GP_4_12_FN,	GPSR4_12,
-		GP_4_11_FN,	GPSR4_11,
-		GP_4_10_FN,	GPSR4_10,
-		GP_4_9_FN,	GPSR4_9,
-		GP_4_8_FN,	GPSR4_8,
-		GP_4_7_FN,	GPSR4_7,
-		GP_4_6_FN,	GPSR4_6,
-		GP_4_5_FN,	GPSR4_5,
-		GP_4_4_FN,	GPSR4_4,
-		GP_4_3_FN,	GPSR4_3,
-		GP_4_2_FN,	GPSR4_2,
-		GP_4_1_FN,	GPSR4_1,
-		GP_4_0_FN,	GPSR4_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_5_25_FN,	GPSR5_25,
-		GP_5_24_FN,	GPSR5_24,
-		GP_5_23_FN,	GPSR5_23,
-		GP_5_22_FN,	GPSR5_22,
-		GP_5_21_FN,	GPSR5_21,
-		GP_5_20_FN,	GPSR5_20,
-		GP_5_19_FN,	GPSR5_19,
-		GP_5_18_FN,	GPSR5_18,
-		GP_5_17_FN,	GPSR5_17,
-		GP_5_16_FN,	GPSR5_16,
-		GP_5_15_FN,	GPSR5_15,
-		GP_5_14_FN,	GPSR5_14,
-		GP_5_13_FN,	GPSR5_13,
-		GP_5_12_FN,	GPSR5_12,
-		GP_5_11_FN,	GPSR5_11,
-		GP_5_10_FN,	GPSR5_10,
-		GP_5_9_FN,	GPSR5_9,
-		GP_5_8_FN,	GPSR5_8,
-		GP_5_7_FN,	GPSR5_7,
-		GP_5_6_FN,	GPSR5_6,
-		GP_5_5_FN,	GPSR5_5,
-		GP_5_4_FN,	GPSR5_4,
-		GP_5_3_FN,	GPSR5_3,
-		GP_5_2_FN,	GPSR5_2,
-		GP_5_1_FN,	GPSR5_1,
-		GP_5_0_FN,	GPSR5_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
-		GP_6_31_FN,	GPSR6_31,
-		GP_6_30_FN,	GPSR6_30,
-		GP_6_29_FN,	GPSR6_29,
-		GP_6_28_FN,	GPSR6_28,
-		GP_6_27_FN,	GPSR6_27,
-		GP_6_26_FN,	GPSR6_26,
-		GP_6_25_FN,	GPSR6_25,
-		GP_6_24_FN,	GPSR6_24,
-		GP_6_23_FN,	GPSR6_23,
-		GP_6_22_FN,	GPSR6_22,
-		GP_6_21_FN,	GPSR6_21,
-		GP_6_20_FN,	GPSR6_20,
-		GP_6_19_FN,	GPSR6_19,
-		GP_6_18_FN,	GPSR6_18,
-		GP_6_17_FN,	GPSR6_17,
-		GP_6_16_FN,	GPSR6_16,
-		GP_6_15_FN,	GPSR6_15,
-		GP_6_14_FN,	GPSR6_14,
-		GP_6_13_FN,	GPSR6_13,
-		GP_6_12_FN,	GPSR6_12,
-		GP_6_11_FN,	GPSR6_11,
-		GP_6_10_FN,	GPSR6_10,
-		GP_6_9_FN,	GPSR6_9,
-		GP_6_8_FN,	GPSR6_8,
-		GP_6_7_FN,	GPSR6_7,
-		GP_6_6_FN,	GPSR6_6,
-		GP_6_5_FN,	GPSR6_5,
-		GP_6_4_FN,	GPSR6_4,
-		GP_6_3_FN,	GPSR6_3,
-		GP_6_2_FN,	GPSR6_2,
-		GP_6_1_FN,	GPSR6_1,
-		GP_6_0_FN,	GPSR6_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_7_3_FN, GPSR7_3,
-		GP_7_2_FN, GPSR7_2,
-		GP_7_1_FN, GPSR7_1,
-		GP_7_0_FN, GPSR7_0, ))
-	},
-#undef F_
-#undef FM
-
-#define F_(x, y)	x,
-#define FM(x)		FN_##x,
-	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
-		IP0_31_28
-		IP0_27_24
-		IP0_23_20
-		IP0_19_16
-		IP0_15_12
-		IP0_11_8
-		IP0_7_4
-		IP0_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
-		IP1_31_28
-		IP1_27_24
-		IP1_23_20
-		IP1_19_16
-		IP1_15_12
-		IP1_11_8
-		IP1_7_4
-		IP1_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
-		IP2_31_28
-		IP2_27_24
-		IP2_23_20
-		IP2_19_16
-		IP2_15_12
-		IP2_11_8
-		IP2_7_4
-		IP2_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
-		IP3_31_28
-		IP3_27_24
-		IP3_23_20
-		IP3_19_16
-		IP3_15_12
-		IP3_11_8
-		IP3_7_4
-		IP3_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
-		IP4_31_28
-		IP4_27_24
-		IP4_23_20
-		IP4_19_16
-		IP4_15_12
-		IP4_11_8
-		IP4_7_4
-		IP4_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
-		IP5_31_28
-		IP5_27_24
-		IP5_23_20
-		IP5_19_16
-		IP5_15_12
-		IP5_11_8
-		IP5_7_4
-		IP5_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
-		IP6_31_28
-		IP6_27_24
-		IP6_23_20
-		IP6_19_16
-		IP6_15_12
-		IP6_11_8
-		IP6_7_4
-		IP6_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
-		IP7_31_28
-		IP7_27_24
-		IP7_23_20
-		IP7_19_16
-		/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		IP7_11_8
-		IP7_7_4
-		IP7_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
-		IP8_31_28
-		IP8_27_24
-		IP8_23_20
-		IP8_19_16
-		IP8_15_12
-		IP8_11_8
-		IP8_7_4
-		IP8_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
-		IP9_31_28
-		IP9_27_24
-		IP9_23_20
-		IP9_19_16
-		IP9_15_12
-		IP9_11_8
-		IP9_7_4
-		IP9_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
-		IP10_31_28
-		IP10_27_24
-		IP10_23_20
-		IP10_19_16
-		IP10_15_12
-		IP10_11_8
-		IP10_7_4
-		IP10_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
-		IP11_31_28
-		IP11_27_24
-		IP11_23_20
-		IP11_19_16
-		IP11_15_12
-		IP11_11_8
-		IP11_7_4
-		IP11_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
-		IP12_31_28
-		IP12_27_24
-		IP12_23_20
-		IP12_19_16
-		IP12_15_12
-		IP12_11_8
-		IP12_7_4
-		IP12_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
-		IP13_31_28
-		IP13_27_24
-		IP13_23_20
-		IP13_19_16
-		IP13_15_12
-		IP13_11_8
-		IP13_7_4
-		IP13_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
-		IP14_31_28
-		IP14_27_24
-		IP14_23_20
-		IP14_19_16
-		IP14_15_12
-		IP14_11_8
-		IP14_7_4
-		IP14_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
-		IP15_31_28
-		IP15_27_24
-		IP15_23_20
-		IP15_19_16
-		IP15_15_12
-		IP15_11_8
-		IP15_7_4
-		IP15_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
-		IP16_31_28
-		IP16_27_24
-		IP16_23_20
-		IP16_19_16
-		IP16_15_12
-		IP16_11_8
-		IP16_7_4
-		IP16_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
-		IP17_31_28
-		IP17_27_24
-		IP17_23_20
-		IP17_19_16
-		IP17_15_12
-		IP17_11_8
-		IP17_7_4
-		IP17_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
-		/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP18_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		IP18_7_4
-		IP18_3_0 ))
-	},
-#undef F_
-#undef FM
-
-#define F_(x, y)	x,
-#define FM(x)		FN_##x,
-	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
-			     GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
-				   1, 1, 1, 2, 2, 1, 2, 3),
-			     GROUP(
-		MOD_SEL0_31_30_29
-		MOD_SEL0_28_27
-		MOD_SEL0_26_25_24
-		MOD_SEL0_23
-		MOD_SEL0_22
-		MOD_SEL0_21
-		MOD_SEL0_20
-		MOD_SEL0_19
-		MOD_SEL0_18_17
-		MOD_SEL0_16
-		0, 0, /* RESERVED 15 */
-		MOD_SEL0_14_13
-		MOD_SEL0_12
-		MOD_SEL0_11
-		MOD_SEL0_10
-		MOD_SEL0_9_8
-		MOD_SEL0_7_6
-		MOD_SEL0_5
-		MOD_SEL0_4_3
-		/* RESERVED 2, 1, 0 */
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
-			     GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
-				   1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
-			     GROUP(
-		MOD_SEL1_31_30
-		MOD_SEL1_29_28_27
-		MOD_SEL1_26
-		MOD_SEL1_25_24
-		MOD_SEL1_23_22_21
-		MOD_SEL1_20
-		MOD_SEL1_19
-		MOD_SEL1_18_17
-		MOD_SEL1_16
-		MOD_SEL1_15_14
-		MOD_SEL1_13
-		MOD_SEL1_12
-		MOD_SEL1_11
-		MOD_SEL1_10
-		MOD_SEL1_9
-		0, 0, 0, 0, /* RESERVED 8, 7 */
-		MOD_SEL1_6
-		MOD_SEL1_5
-		MOD_SEL1_4
-		MOD_SEL1_3
-		MOD_SEL1_2
-		MOD_SEL1_1
-		MOD_SEL1_0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
-			     GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
-				   1, 4, 4, 4, 3, 1),
-			     GROUP(
-		MOD_SEL2_31
-		MOD_SEL2_30
-		MOD_SEL2_29
-		MOD_SEL2_28_27
-		MOD_SEL2_26
-		MOD_SEL2_25_24_23
-		MOD_SEL2_22
-		MOD_SEL2_21
-		MOD_SEL2_20
-		MOD_SEL2_19
-		MOD_SEL2_18
-		MOD_SEL2_17
-		/* RESERVED 16 */
-		0, 0,
-		/* RESERVED 15, 14, 13, 12 */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 11, 10, 9, 8 */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 7, 6, 5, 4 */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 3, 2, 1 */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		MOD_SEL2_0 ))
-	},
-	{ },
-};
-
-static const struct pinmux_drive_reg pinmux_drive_regs[] = {
-	{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
-		{ PIN_QSPI0_SPCLK,    28, 2 },	/* QSPI0_SPCLK */
-		{ PIN_QSPI0_MOSI_IO0, 24, 2 },	/* QSPI0_MOSI_IO0 */
-		{ PIN_QSPI0_MISO_IO1, 20, 2 },	/* QSPI0_MISO_IO1 */
-		{ PIN_QSPI0_IO2,      16, 2 },	/* QSPI0_IO2 */
-		{ PIN_QSPI0_IO3,      12, 2 },	/* QSPI0_IO3 */
-		{ PIN_QSPI0_SSL,       8, 2 },	/* QSPI0_SSL */
-		{ PIN_QSPI1_SPCLK,     4, 2 },	/* QSPI1_SPCLK */
-		{ PIN_QSPI1_MOSI_IO0,  0, 2 },	/* QSPI1_MOSI_IO0 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
-		{ PIN_QSPI1_MISO_IO1, 28, 2 },	/* QSPI1_MISO_IO1 */
-		{ PIN_QSPI1_IO2,      24, 2 },	/* QSPI1_IO2 */
-		{ PIN_QSPI1_IO3,      20, 2 },	/* QSPI1_IO3 */
-		{ PIN_QSPI1_SSL,      16, 2 },	/* QSPI1_SSL */
-		{ PIN_RPC_INT_N,      12, 2 },	/* RPC_INT# */
-		{ PIN_RPC_WP_N,        8, 2 },	/* RPC_WP# */
-		{ PIN_RPC_RESET_N,     4, 2 },	/* RPC_RESET# */
-		{ PIN_AVB_RX_CTL,      0, 3 },	/* AVB_RX_CTL */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
-		{ PIN_AVB_RXC,        28, 3 },	/* AVB_RXC */
-		{ PIN_AVB_RD0,        24, 3 },	/* AVB_RD0 */
-		{ PIN_AVB_RD1,        20, 3 },	/* AVB_RD1 */
-		{ PIN_AVB_RD2,        16, 3 },	/* AVB_RD2 */
-		{ PIN_AVB_RD3,        12, 3 },	/* AVB_RD3 */
-		{ PIN_AVB_TX_CTL,      8, 3 },	/* AVB_TX_CTL */
-		{ PIN_AVB_TXC,         4, 3 },	/* AVB_TXC */
-		{ PIN_AVB_TD0,         0, 3 },	/* AVB_TD0 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
-		{ PIN_AVB_TD1,        28, 3 },	/* AVB_TD1 */
-		{ PIN_AVB_TD2,        24, 3 },	/* AVB_TD2 */
-		{ PIN_AVB_TD3,        20, 3 },	/* AVB_TD3 */
-		{ PIN_AVB_TXCREFCLK,  16, 3 },	/* AVB_TXCREFCLK */
-		{ PIN_AVB_MDIO,       12, 3 },	/* AVB_MDIO */
-		{ RCAR_GP_PIN(2,  9),  8, 3 },	/* AVB_MDC */
-		{ RCAR_GP_PIN(2, 10),  4, 3 },	/* AVB_MAGIC */
-		{ RCAR_GP_PIN(2, 11),  0, 3 },	/* AVB_PHY_INT */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
-		{ RCAR_GP_PIN(2, 12), 28, 3 },	/* AVB_LINK */
-		{ RCAR_GP_PIN(2, 13), 24, 3 },	/* AVB_AVTP_MATCH */
-		{ RCAR_GP_PIN(2, 14), 20, 3 },	/* AVB_AVTP_CAPTURE */
-		{ RCAR_GP_PIN(2,  0), 16, 3 },	/* IRQ0 */
-		{ RCAR_GP_PIN(2,  1), 12, 3 },	/* IRQ1 */
-		{ RCAR_GP_PIN(2,  2),  8, 3 },	/* IRQ2 */
-		{ RCAR_GP_PIN(2,  3),  4, 3 },	/* IRQ3 */
-		{ RCAR_GP_PIN(2,  4),  0, 3 },	/* IRQ4 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
-		{ RCAR_GP_PIN(2,  5), 28, 3 },	/* IRQ5 */
-		{ RCAR_GP_PIN(2,  6), 24, 3 },	/* PWM0 */
-		{ RCAR_GP_PIN(2,  7), 20, 3 },	/* PWM1 */
-		{ RCAR_GP_PIN(2,  8), 16, 3 },	/* PWM2 */
-		{ RCAR_GP_PIN(1,  0), 12, 3 },	/* A0 */
-		{ RCAR_GP_PIN(1,  1),  8, 3 },	/* A1 */
-		{ RCAR_GP_PIN(1,  2),  4, 3 },	/* A2 */
-		{ RCAR_GP_PIN(1,  3),  0, 3 },	/* A3 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
-		{ RCAR_GP_PIN(1,  4), 28, 3 },	/* A4 */
-		{ RCAR_GP_PIN(1,  5), 24, 3 },	/* A5 */
-		{ RCAR_GP_PIN(1,  6), 20, 3 },	/* A6 */
-		{ RCAR_GP_PIN(1,  7), 16, 3 },	/* A7 */
-		{ RCAR_GP_PIN(1,  8), 12, 3 },	/* A8 */
-		{ RCAR_GP_PIN(1,  9),  8, 3 },	/* A9 */
-		{ RCAR_GP_PIN(1, 10),  4, 3 },	/* A10 */
-		{ RCAR_GP_PIN(1, 11),  0, 3 },	/* A11 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
-		{ RCAR_GP_PIN(1, 12), 28, 3 },	/* A12 */
-		{ RCAR_GP_PIN(1, 13), 24, 3 },	/* A13 */
-		{ RCAR_GP_PIN(1, 14), 20, 3 },	/* A14 */
-		{ RCAR_GP_PIN(1, 15), 16, 3 },	/* A15 */
-		{ RCAR_GP_PIN(1, 16), 12, 3 },	/* A16 */
-		{ RCAR_GP_PIN(1, 17),  8, 3 },	/* A17 */
-		{ RCAR_GP_PIN(1, 18),  4, 3 },	/* A18 */
-		{ RCAR_GP_PIN(1, 19),  0, 3 },	/* A19 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
-		{ RCAR_GP_PIN(1, 28), 28, 3 },	/* CLKOUT */
-		{ RCAR_GP_PIN(1, 20), 24, 3 },	/* CS0 */
-		{ RCAR_GP_PIN(1, 21), 20, 3 },	/* CS1_A26 */
-		{ RCAR_GP_PIN(1, 22), 16, 3 },	/* BS */
-		{ RCAR_GP_PIN(1, 23), 12, 3 },	/* RD */
-		{ RCAR_GP_PIN(1, 24),  8, 3 },	/* RD_WR */
-		{ RCAR_GP_PIN(1, 25),  4, 3 },	/* WE0 */
-		{ RCAR_GP_PIN(1, 26),  0, 3 },	/* WE1 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
-		{ RCAR_GP_PIN(1, 27), 28, 3 },	/* EX_WAIT0 */
-		{ PIN_PRESETOUT_N,    24, 3 },	/* PRESETOUT# */
-		{ RCAR_GP_PIN(0,  0), 20, 3 },	/* D0 */
-		{ RCAR_GP_PIN(0,  1), 16, 3 },	/* D1 */
-		{ RCAR_GP_PIN(0,  2), 12, 3 },	/* D2 */
-		{ RCAR_GP_PIN(0,  3),  8, 3 },	/* D3 */
-		{ RCAR_GP_PIN(0,  4),  4, 3 },	/* D4 */
-		{ RCAR_GP_PIN(0,  5),  0, 3 },	/* D5 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
-		{ RCAR_GP_PIN(0,  6), 28, 3 },	/* D6 */
-		{ RCAR_GP_PIN(0,  7), 24, 3 },	/* D7 */
-		{ RCAR_GP_PIN(0,  8), 20, 3 },	/* D8 */
-		{ RCAR_GP_PIN(0,  9), 16, 3 },	/* D9 */
-		{ RCAR_GP_PIN(0, 10), 12, 3 },	/* D10 */
-		{ RCAR_GP_PIN(0, 11),  8, 3 },	/* D11 */
-		{ RCAR_GP_PIN(0, 12),  4, 3 },	/* D12 */
-		{ RCAR_GP_PIN(0, 13),  0, 3 },	/* D13 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
-		{ RCAR_GP_PIN(0, 14), 28, 3 },	/* D14 */
-		{ RCAR_GP_PIN(0, 15), 24, 3 },	/* D15 */
-		{ RCAR_GP_PIN(7,  0), 20, 3 },	/* AVS1 */
-		{ RCAR_GP_PIN(7,  1), 16, 3 },	/* AVS2 */
-		{ RCAR_GP_PIN(7,  2), 12, 3 },	/* GP7_02 */
-		{ RCAR_GP_PIN(7,  3),  8, 3 },	/* GP7_03 */
-		{ PIN_DU_DOTCLKIN0,    4, 2 },	/* DU_DOTCLKIN0 */
-		{ PIN_DU_DOTCLKIN1,    0, 2 },	/* DU_DOTCLKIN1 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
-		{ PIN_DU_DOTCLKIN3,   24, 2 },	/* DU_DOTCLKIN3 */
-		{ PIN_FSCLKST,        20, 2 },	/* FSCLKST */
-		{ PIN_TMS,             4, 2 },	/* TMS */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
-		{ PIN_TDO,            28, 2 },	/* TDO */
-		{ PIN_ASEBRK,         24, 2 },	/* ASEBRK */
-		{ RCAR_GP_PIN(3,  0), 20, 3 },	/* SD0_CLK */
-		{ RCAR_GP_PIN(3,  1), 16, 3 },	/* SD0_CMD */
-		{ RCAR_GP_PIN(3,  2), 12, 3 },	/* SD0_DAT0 */
-		{ RCAR_GP_PIN(3,  3),  8, 3 },	/* SD0_DAT1 */
-		{ RCAR_GP_PIN(3,  4),  4, 3 },	/* SD0_DAT2 */
-		{ RCAR_GP_PIN(3,  5),  0, 3 },	/* SD0_DAT3 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
-		{ RCAR_GP_PIN(3,  6), 28, 3 },	/* SD1_CLK */
-		{ RCAR_GP_PIN(3,  7), 24, 3 },	/* SD1_CMD */
-		{ RCAR_GP_PIN(3,  8), 20, 3 },	/* SD1_DAT0 */
-		{ RCAR_GP_PIN(3,  9), 16, 3 },	/* SD1_DAT1 */
-		{ RCAR_GP_PIN(3, 10), 12, 3 },	/* SD1_DAT2 */
-		{ RCAR_GP_PIN(3, 11),  8, 3 },	/* SD1_DAT3 */
-		{ RCAR_GP_PIN(4,  0),  4, 3 },	/* SD2_CLK */
-		{ RCAR_GP_PIN(4,  1),  0, 3 },	/* SD2_CMD */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
-		{ RCAR_GP_PIN(4,  2), 28, 3 },	/* SD2_DAT0 */
-		{ RCAR_GP_PIN(4,  3), 24, 3 },	/* SD2_DAT1 */
-		{ RCAR_GP_PIN(4,  4), 20, 3 },	/* SD2_DAT2 */
-		{ RCAR_GP_PIN(4,  5), 16, 3 },	/* SD2_DAT3 */
-		{ RCAR_GP_PIN(4,  6), 12, 3 },	/* SD2_DS */
-		{ RCAR_GP_PIN(4,  7),  8, 3 },	/* SD3_CLK */
-		{ RCAR_GP_PIN(4,  8),  4, 3 },	/* SD3_CMD */
-		{ RCAR_GP_PIN(4,  9),  0, 3 },	/* SD3_DAT0 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
-		{ RCAR_GP_PIN(4, 10), 28, 3 },	/* SD3_DAT1 */
-		{ RCAR_GP_PIN(4, 11), 24, 3 },	/* SD3_DAT2 */
-		{ RCAR_GP_PIN(4, 12), 20, 3 },	/* SD3_DAT3 */
-		{ RCAR_GP_PIN(4, 13), 16, 3 },	/* SD3_DAT4 */
-		{ RCAR_GP_PIN(4, 14), 12, 3 },	/* SD3_DAT5 */
-		{ RCAR_GP_PIN(4, 15),  8, 3 },	/* SD3_DAT6 */
-		{ RCAR_GP_PIN(4, 16),  4, 3 },	/* SD3_DAT7 */
-		{ RCAR_GP_PIN(4, 17),  0, 3 },	/* SD3_DS */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
-		{ RCAR_GP_PIN(3, 12), 28, 3 },	/* SD0_CD */
-		{ RCAR_GP_PIN(3, 13), 24, 3 },	/* SD0_WP */
-		{ RCAR_GP_PIN(3, 14), 20, 3 },	/* SD1_CD */
-		{ RCAR_GP_PIN(3, 15), 16, 3 },	/* SD1_WP */
-		{ RCAR_GP_PIN(5,  0), 12, 3 },	/* SCK0 */
-		{ RCAR_GP_PIN(5,  1),  8, 3 },	/* RX0 */
-		{ RCAR_GP_PIN(5,  2),  4, 3 },	/* TX0 */
-		{ RCAR_GP_PIN(5,  3),  0, 3 },	/* CTS0 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
-		{ RCAR_GP_PIN(5,  4), 28, 3 },	/* RTS0 */
-		{ RCAR_GP_PIN(5,  5), 24, 3 },	/* RX1 */
-		{ RCAR_GP_PIN(5,  6), 20, 3 },	/* TX1 */
-		{ RCAR_GP_PIN(5,  7), 16, 3 },	/* CTS1 */
-		{ RCAR_GP_PIN(5,  8), 12, 3 },	/* RTS1 */
-		{ RCAR_GP_PIN(5,  9),  8, 3 },	/* SCK2 */
-		{ RCAR_GP_PIN(5, 10),  4, 3 },	/* TX2 */
-		{ RCAR_GP_PIN(5, 11),  0, 3 },	/* RX2 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
-		{ RCAR_GP_PIN(5, 12), 28, 3 },	/* HSCK0 */
-		{ RCAR_GP_PIN(5, 13), 24, 3 },	/* HRX0 */
-		{ RCAR_GP_PIN(5, 14), 20, 3 },	/* HTX0 */
-		{ RCAR_GP_PIN(5, 15), 16, 3 },	/* HCTS0 */
-		{ RCAR_GP_PIN(5, 16), 12, 3 },	/* HRTS0 */
-		{ RCAR_GP_PIN(5, 17),  8, 3 },	/* MSIOF0_SCK */
-		{ RCAR_GP_PIN(5, 18),  4, 3 },	/* MSIOF0_SYNC */
-		{ RCAR_GP_PIN(5, 19),  0, 3 },	/* MSIOF0_SS1 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
-		{ RCAR_GP_PIN(5, 20), 28, 3 },	/* MSIOF0_TXD */
-		{ RCAR_GP_PIN(5, 21), 24, 3 },	/* MSIOF0_SS2 */
-		{ RCAR_GP_PIN(5, 22), 20, 3 },	/* MSIOF0_RXD */
-		{ RCAR_GP_PIN(5, 23), 16, 3 },	/* MLB_CLK */
-		{ RCAR_GP_PIN(5, 24), 12, 3 },	/* MLB_SIG */
-		{ RCAR_GP_PIN(5, 25),  8, 3 },	/* MLB_DAT */
-		{ PIN_MLB_REF,         4, 3 },	/* MLB_REF */
-		{ RCAR_GP_PIN(6,  0),  0, 3 },	/* SSI_SCK01239 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
-		{ RCAR_GP_PIN(6,  1), 28, 3 },	/* SSI_WS01239 */
-		{ RCAR_GP_PIN(6,  2), 24, 3 },	/* SSI_SDATA0 */
-		{ RCAR_GP_PIN(6,  3), 20, 3 },	/* SSI_SDATA1 */
-		{ RCAR_GP_PIN(6,  4), 16, 3 },	/* SSI_SDATA2 */
-		{ RCAR_GP_PIN(6,  5), 12, 3 },	/* SSI_SCK349 */
-		{ RCAR_GP_PIN(6,  6),  8, 3 },	/* SSI_WS349 */
-		{ RCAR_GP_PIN(6,  7),  4, 3 },	/* SSI_SDATA3 */
-		{ RCAR_GP_PIN(6,  8),  0, 3 },	/* SSI_SCK4 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
-		{ RCAR_GP_PIN(6,  9), 28, 3 },	/* SSI_WS4 */
-		{ RCAR_GP_PIN(6, 10), 24, 3 },	/* SSI_SDATA4 */
-		{ RCAR_GP_PIN(6, 11), 20, 3 },	/* SSI_SCK5 */
-		{ RCAR_GP_PIN(6, 12), 16, 3 },	/* SSI_WS5 */
-		{ RCAR_GP_PIN(6, 13), 12, 3 },	/* SSI_SDATA5 */
-		{ RCAR_GP_PIN(6, 14),  8, 3 },	/* SSI_SCK6 */
-		{ RCAR_GP_PIN(6, 15),  4, 3 },	/* SSI_WS6 */
-		{ RCAR_GP_PIN(6, 16),  0, 3 },	/* SSI_SDATA6 */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
-		{ RCAR_GP_PIN(6, 17), 28, 3 },	/* SSI_SCK78 */
-		{ RCAR_GP_PIN(6, 18), 24, 3 },	/* SSI_WS78 */
-		{ RCAR_GP_PIN(6, 19), 20, 3 },	/* SSI_SDATA7 */
-		{ RCAR_GP_PIN(6, 20), 16, 3 },	/* SSI_SDATA8 */
-		{ RCAR_GP_PIN(6, 21), 12, 3 },	/* SSI_SDATA9 */
-		{ RCAR_GP_PIN(6, 22),  8, 3 },	/* AUDIO_CLKA */
-		{ RCAR_GP_PIN(6, 23),  4, 3 },	/* AUDIO_CLKB */
-		{ RCAR_GP_PIN(6, 24),  0, 3 },	/* USB0_PWEN */
-	} },
-	{ PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
-		{ RCAR_GP_PIN(6, 25), 28, 3 },	/* USB0_OVC */
-		{ RCAR_GP_PIN(6, 26), 24, 3 },	/* USB1_PWEN */
-		{ RCAR_GP_PIN(6, 27), 20, 3 },	/* USB1_OVC */
-		{ RCAR_GP_PIN(6, 28), 16, 3 },	/* USB30_PWEN */
-		{ RCAR_GP_PIN(6, 29), 12, 3 },	/* USB30_OVC */
-		{ RCAR_GP_PIN(6, 30),  8, 3 },	/* GP6_30 */
-		{ RCAR_GP_PIN(6, 31),  4, 3 },	/* GP6_31 */
-	} },
-	{ },
-};
-
-enum ioctrl_regs {
-	POCCTRL,
-	TDSELCTRL,
-};
-
-static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
-	[POCCTRL] = { 0xe6060380, },
-	[TDSELCTRL] = { 0xe60603c0, },
-	{ /* sentinel */ },
-};
-
-static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
-{
-	int bit = -EINVAL;
-
-	*pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
-
-	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
-		bit = pin & 0x1f;
-
-	if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
-		bit = (pin & 0x1f) + 12;
-
-	return bit;
-}
-
-static const struct pinmux_bias_reg pinmux_bias_regs[] = {
-	{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
-		[ 0] = PIN_QSPI0_SPCLK,		/* QSPI0_SPCLK */
-		[ 1] = PIN_QSPI0_MOSI_IO0,	/* QSPI0_MOSI_IO0 */
-		[ 2] = PIN_QSPI0_MISO_IO1,	/* QSPI0_MISO_IO1 */
-		[ 3] = PIN_QSPI0_IO2,		/* QSPI0_IO2 */
-		[ 4] = PIN_QSPI0_IO3,		/* QSPI0_IO3 */
-		[ 5] = PIN_QSPI0_SSL,		/* QSPI0_SSL */
-		[ 6] = PIN_QSPI1_SPCLK,		/* QSPI1_SPCLK */
-		[ 7] = PIN_QSPI1_MOSI_IO0,	/* QSPI1_MOSI_IO0 */
-		[ 8] = PIN_QSPI1_MISO_IO1,	/* QSPI1_MISO_IO1 */
-		[ 9] = PIN_QSPI1_IO2,		/* QSPI1_IO2 */
-		[10] = PIN_QSPI1_IO3,		/* QSPI1_IO3 */
-		[11] = PIN_QSPI1_SSL,		/* QSPI1_SSL */
-		[12] = PIN_RPC_INT_N,		/* RPC_INT# */
-		[13] = PIN_RPC_WP_N,		/* RPC_WP# */
-		[14] = PIN_RPC_RESET_N,		/* RPC_RESET# */
-		[15] = PIN_AVB_RX_CTL,		/* AVB_RX_CTL */
-		[16] = PIN_AVB_RXC,		/* AVB_RXC */
-		[17] = PIN_AVB_RD0,		/* AVB_RD0 */
-		[18] = PIN_AVB_RD1,		/* AVB_RD1 */
-		[19] = PIN_AVB_RD2,		/* AVB_RD2 */
-		[20] = PIN_AVB_RD3,		/* AVB_RD3 */
-		[21] = PIN_AVB_TX_CTL,		/* AVB_TX_CTL */
-		[22] = PIN_AVB_TXC,		/* AVB_TXC */
-		[23] = PIN_AVB_TD0,		/* AVB_TD0 */
-		[24] = PIN_AVB_TD1,		/* AVB_TD1 */
-		[25] = PIN_AVB_TD2,		/* AVB_TD2 */
-		[26] = PIN_AVB_TD3,		/* AVB_TD3 */
-		[27] = PIN_AVB_TXCREFCLK,	/* AVB_TXCREFCLK */
-		[28] = PIN_AVB_MDIO,		/* AVB_MDIO */
-		[29] = RCAR_GP_PIN(2,  9),	/* AVB_MDC */
-		[30] = RCAR_GP_PIN(2, 10),	/* AVB_MAGIC */
-		[31] = RCAR_GP_PIN(2, 11),	/* AVB_PHY_INT */
-	} },
-	{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
-		[ 0] = RCAR_GP_PIN(2, 12),	/* AVB_LINK */
-		[ 1] = RCAR_GP_PIN(2, 13),	/* AVB_AVTP_MATCH_A */
-		[ 2] = RCAR_GP_PIN(2, 14),	/* AVB_AVTP_CAPTURE_A */
-		[ 3] = RCAR_GP_PIN(2,  0),	/* IRQ0 */
-		[ 4] = RCAR_GP_PIN(2,  1),	/* IRQ1 */
-		[ 5] = RCAR_GP_PIN(2,  2),	/* IRQ2 */
-		[ 6] = RCAR_GP_PIN(2,  3),	/* IRQ3 */
-		[ 7] = RCAR_GP_PIN(2,  4),	/* IRQ4 */
-		[ 8] = RCAR_GP_PIN(2,  5),	/* IRQ5 */
-		[ 9] = RCAR_GP_PIN(2,  6),	/* PWM0 */
-		[10] = RCAR_GP_PIN(2,  7),	/* PWM1_A */
-		[11] = RCAR_GP_PIN(2,  8),	/* PWM2_A */
-		[12] = RCAR_GP_PIN(1,  0),	/* A0 */
-		[13] = RCAR_GP_PIN(1,  1),	/* A1 */
-		[14] = RCAR_GP_PIN(1,  2),	/* A2 */
-		[15] = RCAR_GP_PIN(1,  3),	/* A3 */
-		[16] = RCAR_GP_PIN(1,  4),	/* A4 */
-		[17] = RCAR_GP_PIN(1,  5),	/* A5 */
-		[18] = RCAR_GP_PIN(1,  6),	/* A6 */
-		[19] = RCAR_GP_PIN(1,  7),	/* A7 */
-		[20] = RCAR_GP_PIN(1,  8),	/* A8 */
-		[21] = RCAR_GP_PIN(1,  9),	/* A9 */
-		[22] = RCAR_GP_PIN(1, 10),	/* A10 */
-		[23] = RCAR_GP_PIN(1, 11),	/* A11 */
-		[24] = RCAR_GP_PIN(1, 12),	/* A12 */
-		[25] = RCAR_GP_PIN(1, 13),	/* A13 */
-		[26] = RCAR_GP_PIN(1, 14),	/* A14 */
-		[27] = RCAR_GP_PIN(1, 15),	/* A15 */
-		[28] = RCAR_GP_PIN(1, 16),	/* A16 */
-		[29] = RCAR_GP_PIN(1, 17),	/* A17 */
-		[30] = RCAR_GP_PIN(1, 18),	/* A18 */
-		[31] = RCAR_GP_PIN(1, 19),	/* A19 */
-	} },
-	{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
-		[ 0] = RCAR_GP_PIN(1, 28),	/* CLKOUT */
-		[ 1] = RCAR_GP_PIN(1, 20),	/* CS0_N */
-		[ 2] = RCAR_GP_PIN(1, 21),	/* CS1_N */
-		[ 3] = RCAR_GP_PIN(1, 22),	/* BS_N */
-		[ 4] = RCAR_GP_PIN(1, 23),	/* RD_N */
-		[ 5] = RCAR_GP_PIN(1, 24),	/* RD_WR_N */
-		[ 6] = RCAR_GP_PIN(1, 25),	/* WE0_N */
-		[ 7] = RCAR_GP_PIN(1, 26),	/* WE1_N */
-		[ 8] = RCAR_GP_PIN(1, 27),	/* EX_WAIT0_A */
-		[ 9] = PIN_PRESETOUT_N,		/* PRESETOUT# */
-		[10] = RCAR_GP_PIN(0,  0),	/* D0 */
-		[11] = RCAR_GP_PIN(0,  1),	/* D1 */
-		[12] = RCAR_GP_PIN(0,  2),	/* D2 */
-		[13] = RCAR_GP_PIN(0,  3),	/* D3 */
-		[14] = RCAR_GP_PIN(0,  4),	/* D4 */
-		[15] = RCAR_GP_PIN(0,  5),	/* D5 */
-		[16] = RCAR_GP_PIN(0,  6),	/* D6 */
-		[17] = RCAR_GP_PIN(0,  7),	/* D7 */
-		[18] = RCAR_GP_PIN(0,  8),	/* D8 */
-		[19] = RCAR_GP_PIN(0,  9),	/* D9 */
-		[20] = RCAR_GP_PIN(0, 10),	/* D10 */
-		[21] = RCAR_GP_PIN(0, 11),	/* D11 */
-		[22] = RCAR_GP_PIN(0, 12),	/* D12 */
-		[23] = RCAR_GP_PIN(0, 13),	/* D13 */
-		[24] = RCAR_GP_PIN(0, 14),	/* D14 */
-		[25] = RCAR_GP_PIN(0, 15),	/* D15 */
-		[26] = RCAR_GP_PIN(7,  0),	/* AVS1 */
-		[27] = RCAR_GP_PIN(7,  1),	/* AVS2 */
-		[28] = RCAR_GP_PIN(7,  2),	/* GP7_02 */
-		[29] = RCAR_GP_PIN(7,  3),	/* GP7_03 */
-		[30] = PIN_DU_DOTCLKIN0,	/* DU_DOTCLKIN0 */
-		[31] = PIN_DU_DOTCLKIN1,	/* DU_DOTCLKIN1 */
-	} },
-	{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
-		[ 0] = SH_PFC_PIN_NONE,
-		[ 1] = PIN_DU_DOTCLKIN3,	/* DU_DOTCLKIN3 */
-		[ 2] = PIN_FSCLKST,		/* FSCLKST */
-		[ 3] = PIN_EXTALR,		/* EXTALR*/
-		[ 4] = PIN_TRST_N,		/* TRST# */
-		[ 5] = PIN_TCK,			/* TCK */
-		[ 6] = PIN_TMS,			/* TMS */
-		[ 7] = PIN_TDI,			/* TDI */
-		[ 8] = SH_PFC_PIN_NONE,
-		[ 9] = PIN_ASEBRK,		/* ASEBRK */
-		[10] = RCAR_GP_PIN(3,  0),	/* SD0_CLK */
-		[11] = RCAR_GP_PIN(3,  1),	/* SD0_CMD */
-		[12] = RCAR_GP_PIN(3,  2),	/* SD0_DAT0 */
-		[13] = RCAR_GP_PIN(3,  3),	/* SD0_DAT1 */
-		[14] = RCAR_GP_PIN(3,  4),	/* SD0_DAT2 */
-		[15] = RCAR_GP_PIN(3,  5),	/* SD0_DAT3 */
-		[16] = RCAR_GP_PIN(3,  6),	/* SD1_CLK */
-		[17] = RCAR_GP_PIN(3,  7),	/* SD1_CMD */
-		[18] = RCAR_GP_PIN(3,  8),	/* SD1_DAT0 */
-		[19] = RCAR_GP_PIN(3,  9),	/* SD1_DAT1 */
-		[20] = RCAR_GP_PIN(3, 10),	/* SD1_DAT2 */
-		[21] = RCAR_GP_PIN(3, 11),	/* SD1_DAT3 */
-		[22] = RCAR_GP_PIN(4,  0),	/* SD2_CLK */
-		[23] = RCAR_GP_PIN(4,  1),	/* SD2_CMD */
-		[24] = RCAR_GP_PIN(4,  2),	/* SD2_DAT0 */
-		[25] = RCAR_GP_PIN(4,  3),	/* SD2_DAT1 */
-		[26] = RCAR_GP_PIN(4,  4),	/* SD2_DAT2 */
-		[27] = RCAR_GP_PIN(4,  5),	/* SD2_DAT3 */
-		[28] = RCAR_GP_PIN(4,  6),	/* SD2_DS */
-		[29] = RCAR_GP_PIN(4,  7),	/* SD3_CLK */
-		[30] = RCAR_GP_PIN(4,  8),	/* SD3_CMD */
-		[31] = RCAR_GP_PIN(4,  9),	/* SD3_DAT0 */
-	} },
-	{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
-		[ 0] = RCAR_GP_PIN(4, 10),	/* SD3_DAT1 */
-		[ 1] = RCAR_GP_PIN(4, 11),	/* SD3_DAT2 */
-		[ 2] = RCAR_GP_PIN(4, 12),	/* SD3_DAT3 */
-		[ 3] = RCAR_GP_PIN(4, 13),	/* SD3_DAT4 */
-		[ 4] = RCAR_GP_PIN(4, 14),	/* SD3_DAT5 */
-		[ 5] = RCAR_GP_PIN(4, 15),	/* SD3_DAT6 */
-		[ 6] = RCAR_GP_PIN(4, 16),	/* SD3_DAT7 */
-		[ 7] = RCAR_GP_PIN(4, 17),	/* SD3_DS */
-		[ 8] = RCAR_GP_PIN(3, 12),	/* SD0_CD */
-		[ 9] = RCAR_GP_PIN(3, 13),	/* SD0_WP */
-		[10] = RCAR_GP_PIN(3, 14),	/* SD1_CD */
-		[11] = RCAR_GP_PIN(3, 15),	/* SD1_WP */
-		[12] = RCAR_GP_PIN(5,  0),	/* SCK0 */
-		[13] = RCAR_GP_PIN(5,  1),	/* RX0 */
-		[14] = RCAR_GP_PIN(5,  2),	/* TX0 */
-		[15] = RCAR_GP_PIN(5,  3),	/* CTS0_N */
-		[16] = RCAR_GP_PIN(5,  4),	/* RTS0_N */
-		[17] = RCAR_GP_PIN(5,  5),	/* RX1_A */
-		[18] = RCAR_GP_PIN(5,  6),	/* TX1_A */
-		[19] = RCAR_GP_PIN(5,  7),	/* CTS1_N */
-		[20] = RCAR_GP_PIN(5,  8),	/* RTS1_N */
-		[21] = RCAR_GP_PIN(5,  9),	/* SCK2 */
-		[22] = RCAR_GP_PIN(5, 10),	/* TX2_A */
-		[23] = RCAR_GP_PIN(5, 11),	/* RX2_A */
-		[24] = RCAR_GP_PIN(5, 12),	/* HSCK0 */
-		[25] = RCAR_GP_PIN(5, 13),	/* HRX0 */
-		[26] = RCAR_GP_PIN(5, 14),	/* HTX0 */
-		[27] = RCAR_GP_PIN(5, 15),	/* HCTS0_N */
-		[28] = RCAR_GP_PIN(5, 16),	/* HRTS0_N */
-		[29] = RCAR_GP_PIN(5, 17),	/* MSIOF0_SCK */
-		[30] = RCAR_GP_PIN(5, 18),	/* MSIOF0_SYNC */
-		[31] = RCAR_GP_PIN(5, 19),	/* MSIOF0_SS1 */
-	} },
-	{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
-		[ 0] = RCAR_GP_PIN(5, 20),	/* MSIOF0_TXD */
-		[ 1] = RCAR_GP_PIN(5, 21),	/* MSIOF0_SS2 */
-		[ 2] = RCAR_GP_PIN(5, 22),	/* MSIOF0_RXD */
-		[ 3] = RCAR_GP_PIN(5, 23),	/* MLB_CLK */
-		[ 4] = RCAR_GP_PIN(5, 24),	/* MLB_SIG */
-		[ 5] = RCAR_GP_PIN(5, 25),	/* MLB_DAT */
-		[ 6] = PIN_MLB_REF,		/* MLB_REF */
-		[ 7] = RCAR_GP_PIN(6,  0),	/* SSI_SCK01239 */
-		[ 8] = RCAR_GP_PIN(6,  1),	/* SSI_WS01239 */
-		[ 9] = RCAR_GP_PIN(6,  2),	/* SSI_SDATA0 */
-		[10] = RCAR_GP_PIN(6,  3),	/* SSI_SDATA1_A */
-		[11] = RCAR_GP_PIN(6,  4),	/* SSI_SDATA2_A */
-		[12] = RCAR_GP_PIN(6,  5),	/* SSI_SCK349 */
-		[13] = RCAR_GP_PIN(6,  6),	/* SSI_WS349 */
-		[14] = RCAR_GP_PIN(6,  7),	/* SSI_SDATA3 */
-		[15] = RCAR_GP_PIN(6,  8),	/* SSI_SCK4 */
-		[16] = RCAR_GP_PIN(6,  9),	/* SSI_WS4 */
-		[17] = RCAR_GP_PIN(6, 10),	/* SSI_SDATA4 */
-		[18] = RCAR_GP_PIN(6, 11),	/* SSI_SCK5 */
-		[19] = RCAR_GP_PIN(6, 12),	/* SSI_WS5 */
-		[20] = RCAR_GP_PIN(6, 13),	/* SSI_SDATA5 */
-		[21] = RCAR_GP_PIN(6, 14),	/* SSI_SCK6 */
-		[22] = RCAR_GP_PIN(6, 15),	/* SSI_WS6 */
-		[23] = RCAR_GP_PIN(6, 16),	/* SSI_SDATA6 */
-		[24] = RCAR_GP_PIN(6, 17),	/* SSI_SCK78 */
-		[25] = RCAR_GP_PIN(6, 18),	/* SSI_WS78 */
-		[26] = RCAR_GP_PIN(6, 19),	/* SSI_SDATA7 */
-		[27] = RCAR_GP_PIN(6, 20),	/* SSI_SDATA8 */
-		[28] = RCAR_GP_PIN(6, 21),	/* SSI_SDATA9_A */
-		[29] = RCAR_GP_PIN(6, 22),	/* AUDIO_CLKA_A */
-		[30] = RCAR_GP_PIN(6, 23),	/* AUDIO_CLKB_B */
-		[31] = RCAR_GP_PIN(6, 24),	/* USB0_PWEN */
-	} },
-	{ PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
-		[ 0] = RCAR_GP_PIN(6, 25),	/* USB0_OVC */
-		[ 1] = RCAR_GP_PIN(6, 26),	/* USB1_PWEN */
-		[ 2] = RCAR_GP_PIN(6, 27),	/* USB1_OVC */
-		[ 3] = RCAR_GP_PIN(6, 28),	/* USB30_PWEN */
-		[ 4] = RCAR_GP_PIN(6, 29),	/* USB30_OVC */
-		[ 5] = RCAR_GP_PIN(6, 30),	/* GP6_30 */
-		[ 6] = RCAR_GP_PIN(6, 31),	/* GP6_31 */
-		[ 7] = SH_PFC_PIN_NONE,
-		[ 8] = SH_PFC_PIN_NONE,
-		[ 9] = SH_PFC_PIN_NONE,
-		[10] = SH_PFC_PIN_NONE,
-		[11] = SH_PFC_PIN_NONE,
-		[12] = SH_PFC_PIN_NONE,
-		[13] = SH_PFC_PIN_NONE,
-		[14] = SH_PFC_PIN_NONE,
-		[15] = SH_PFC_PIN_NONE,
-		[16] = SH_PFC_PIN_NONE,
-		[17] = SH_PFC_PIN_NONE,
-		[18] = SH_PFC_PIN_NONE,
-		[19] = SH_PFC_PIN_NONE,
-		[20] = SH_PFC_PIN_NONE,
-		[21] = SH_PFC_PIN_NONE,
-		[22] = SH_PFC_PIN_NONE,
-		[23] = SH_PFC_PIN_NONE,
-		[24] = SH_PFC_PIN_NONE,
-		[25] = SH_PFC_PIN_NONE,
-		[26] = SH_PFC_PIN_NONE,
-		[27] = SH_PFC_PIN_NONE,
-		[28] = SH_PFC_PIN_NONE,
-		[29] = SH_PFC_PIN_NONE,
-		[30] = SH_PFC_PIN_NONE,
-		[31] = SH_PFC_PIN_NONE,
-	} },
-	{ /* sentinel */ },
-};
-
-static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc,
-					    unsigned int pin)
-{
-	const struct pinmux_bias_reg *reg;
-	unsigned int bit;
-
-	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
-	if (!reg)
-		return PIN_CONFIG_BIAS_DISABLE;
-
-	if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
-		return PIN_CONFIG_BIAS_DISABLE;
-	else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
-		return PIN_CONFIG_BIAS_PULL_UP;
-	else
-		return PIN_CONFIG_BIAS_PULL_DOWN;
-}
-
-static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
-				   unsigned int bias)
-{
-	const struct pinmux_bias_reg *reg;
-	u32 enable, updown;
-	unsigned int bit;
-
-	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
-	if (!reg)
-		return;
-
-	enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
-	if (bias != PIN_CONFIG_BIAS_DISABLE)
-		enable |= BIT(bit);
-
-	updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
-	if (bias == PIN_CONFIG_BIAS_PULL_UP)
-		updown |= BIT(bit);
-
-	sh_pfc_write(pfc, reg->pud, updown);
-	sh_pfc_write(pfc, reg->puen, enable);
-}
-
-static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
-	.pin_to_pocctrl = r8a77965_pin_to_pocctrl,
-	.get_bias = r8a77965_pinmux_get_bias,
-	.set_bias = r8a77965_pinmux_set_bias,
-};
-
-#ifdef CONFIG_PINCTRL_PFC_R8A774B1
-const struct sh_pfc_soc_info r8a774b1_pinmux_info = {
-	.name = "r8a774b1_pfc",
-	.ops = &r8a77965_pinmux_ops,
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups.common,
-	.nr_groups = ARRAY_SIZE(pinmux_groups.common),
-	.functions = pinmux_functions.common,
-	.nr_functions = ARRAY_SIZE(pinmux_functions.common),
-
-	.cfg_regs = pinmux_config_regs,
-	.drive_regs = pinmux_drive_regs,
-	.bias_regs = pinmux_bias_regs,
-	.ioctrl_regs = pinmux_ioctrl_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
-#endif
-
-#ifdef CONFIG_PINCTRL_PFC_R8A77965
-const struct sh_pfc_soc_info r8a77965_pinmux_info = {
-	.name = "r8a77965_pfc",
-	.ops = &r8a77965_pinmux_ops,
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups.common,
-	.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
-		ARRAY_SIZE(pinmux_groups.automotive),
-	.functions = pinmux_functions.common,
-	.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
-		ARRAY_SIZE(pinmux_functions.automotive),
-
-	.cfg_regs = pinmux_config_regs,
-	.drive_regs = pinmux_drive_regs,
-	.bias_regs = pinmux_bias_regs,
-	.ioctrl_regs = pinmux_ioctrl_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
-#endif
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
deleted file mode 100644
index 25e27b6bee89..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
+++ /dev/null
@@ -1,2447 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * R8A77970 processor support - PFC hardware block.
- *
- * Copyright (C) 2016 Renesas Electronics Corp.
- * Copyright (C) 2017 Cogent Embedded, Inc. <source@cogentembedded.com>
- *
- * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
- *
- * R-Car Gen3 processor support - PFC hardware block.
- *
- * Copyright (C) 2015  Renesas Electronics Corporation
- */
-
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-
-#include "core.h"
-#include "sh_pfc.h"
-
-#define CPU_ALL_GP(fn, sfx)						\
-	PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),		\
-	PORT_GP_28(1, fn, sfx),						\
-	PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),		\
-	PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),		\
-	PORT_GP_6(4,  fn, sfx),						\
-	PORT_GP_15(5, fn, sfx)
-/*
- * F_() : just information
- * FM() : macro for FN_xxx / xxx_MARK
- */
-
-/* GPSR0 */
-#define GPSR0_21	F_(DU_EXODDF_DU_ODDF_DISP_CDE,	IP2_23_20)
-#define GPSR0_20	F_(DU_EXVSYNC_DU_VSYNC,		IP2_19_16)
-#define GPSR0_19	F_(DU_EXHSYNC_DU_HSYNC,		IP2_15_12)
-#define GPSR0_18	F_(DU_DOTCLKOUT,		IP2_11_8)
-#define GPSR0_17	F_(DU_DB7,			IP2_7_4)
-#define GPSR0_16	F_(DU_DB6,			IP2_3_0)
-#define GPSR0_15	F_(DU_DB5,			IP1_31_28)
-#define GPSR0_14	F_(DU_DB4,			IP1_27_24)
-#define GPSR0_13	F_(DU_DB3,			IP1_23_20)
-#define GPSR0_12	F_(DU_DB2,			IP1_19_16)
-#define GPSR0_11	F_(DU_DG7,			IP1_15_12)
-#define GPSR0_10	F_(DU_DG6,			IP1_11_8)
-#define GPSR0_9		F_(DU_DG5,			IP1_7_4)
-#define GPSR0_8		F_(DU_DG4,			IP1_3_0)
-#define GPSR0_7		F_(DU_DG3,			IP0_31_28)
-#define GPSR0_6		F_(DU_DG2,			IP0_27_24)
-#define GPSR0_5		F_(DU_DR7,			IP0_23_20)
-#define GPSR0_4		F_(DU_DR6,			IP0_19_16)
-#define GPSR0_3		F_(DU_DR5,			IP0_15_12)
-#define GPSR0_2		F_(DU_DR4,			IP0_11_8)
-#define GPSR0_1		F_(DU_DR3,			IP0_7_4)
-#define GPSR0_0		F_(DU_DR2,			IP0_3_0)
-
-/* GPSR1 */
-#define GPSR1_27	F_(DIGRF_CLKOUT,	IP8_27_24)
-#define GPSR1_26	F_(DIGRF_CLKIN,		IP8_23_20)
-#define GPSR1_25	F_(CANFD_CLK_A,		IP8_19_16)
-#define GPSR1_24	F_(CANFD1_RX,		IP8_15_12)
-#define GPSR1_23	F_(CANFD1_TX,		IP8_11_8)
-#define GPSR1_22	F_(CANFD0_RX_A,		IP8_7_4)
-#define GPSR1_21	F_(CANFD0_TX_A,		IP8_3_0)
-#define GPSR1_20	F_(AVB0_AVTP_CAPTURE,	IP7_31_28)
-#define GPSR1_19	FM(AVB0_AVTP_MATCH)
-#define GPSR1_18	FM(AVB0_LINK)
-#define GPSR1_17	FM(AVB0_PHY_INT)
-#define GPSR1_16	FM(AVB0_MAGIC)
-#define GPSR1_15	FM(AVB0_MDC)
-#define GPSR1_14	FM(AVB0_MDIO)
-#define GPSR1_13	FM(AVB0_TXCREFCLK)
-#define GPSR1_12	FM(AVB0_TD3)
-#define GPSR1_11	FM(AVB0_TD2)
-#define GPSR1_10	FM(AVB0_TD1)
-#define GPSR1_9		FM(AVB0_TD0)
-#define GPSR1_8		FM(AVB0_TXC)
-#define GPSR1_7		FM(AVB0_TX_CTL)
-#define GPSR1_6		FM(AVB0_RD3)
-#define GPSR1_5		FM(AVB0_RD2)
-#define GPSR1_4		FM(AVB0_RD1)
-#define GPSR1_3		FM(AVB0_RD0)
-#define GPSR1_2		FM(AVB0_RXC)
-#define GPSR1_1		FM(AVB0_RX_CTL)
-#define GPSR1_0		F_(IRQ0,		IP2_27_24)
-
-/* GPSR2 */
-#define GPSR2_16	F_(VI0_FIELD,		IP4_31_28)
-#define GPSR2_15	F_(VI0_DATA11,		IP4_27_24)
-#define GPSR2_14	F_(VI0_DATA10,		IP4_23_20)
-#define GPSR2_13	F_(VI0_DATA9,		IP4_19_16)
-#define GPSR2_12	F_(VI0_DATA8,		IP4_15_12)
-#define GPSR2_11	F_(VI0_DATA7,		IP4_11_8)
-#define GPSR2_10	F_(VI0_DATA6,		IP4_7_4)
-#define GPSR2_9		F_(VI0_DATA5,		IP4_3_0)
-#define GPSR2_8		F_(VI0_DATA4,		IP3_31_28)
-#define GPSR2_7		F_(VI0_DATA3,		IP3_27_24)
-#define GPSR2_6		F_(VI0_DATA2,		IP3_23_20)
-#define GPSR2_5		F_(VI0_DATA1,		IP3_19_16)
-#define GPSR2_4		F_(VI0_DATA0,		IP3_15_12)
-#define GPSR2_3		F_(VI0_VSYNC_N,		IP3_11_8)
-#define GPSR2_2		F_(VI0_HSYNC_N,		IP3_7_4)
-#define GPSR2_1		F_(VI0_CLKENB,		IP3_3_0)
-#define GPSR2_0		F_(VI0_CLK,		IP2_31_28)
-
-/* GPSR3 */
-#define GPSR3_16	F_(VI1_FIELD,		IP7_3_0)
-#define GPSR3_15	F_(VI1_DATA11,		IP6_31_28)
-#define GPSR3_14	F_(VI1_DATA10,		IP6_27_24)
-#define GPSR3_13	F_(VI1_DATA9,		IP6_23_20)
-#define GPSR3_12	F_(VI1_DATA8,		IP6_19_16)
-#define GPSR3_11	F_(VI1_DATA7,		IP6_15_12)
-#define GPSR3_10	F_(VI1_DATA6,		IP6_11_8)
-#define GPSR3_9		F_(VI1_DATA5,		IP6_7_4)
-#define GPSR3_8		F_(VI1_DATA4,		IP6_3_0)
-#define GPSR3_7		F_(VI1_DATA3,		IP5_31_28)
-#define GPSR3_6		F_(VI1_DATA2,		IP5_27_24)
-#define GPSR3_5		F_(VI1_DATA1,		IP5_23_20)
-#define GPSR3_4		F_(VI1_DATA0,		IP5_19_16)
-#define GPSR3_3		F_(VI1_VSYNC_N,		IP5_15_12)
-#define GPSR3_2		F_(VI1_HSYNC_N,		IP5_11_8)
-#define GPSR3_1		F_(VI1_CLKENB,		IP5_7_4)
-#define GPSR3_0		F_(VI1_CLK,		IP5_3_0)
-
-/* GPSR4 */
-#define GPSR4_5		F_(SDA2,		IP7_27_24)
-#define GPSR4_4		F_(SCL2,		IP7_23_20)
-#define GPSR4_3		F_(SDA1,		IP7_19_16)
-#define GPSR4_2		F_(SCL1,		IP7_15_12)
-#define GPSR4_1		F_(SDA0,		IP7_11_8)
-#define GPSR4_0		F_(SCL0,		IP7_7_4)
-
-/* GPSR5 */
-#define GPSR5_14	FM(RPC_INT_N)
-#define GPSR5_13	FM(RPC_WP_N)
-#define GPSR5_12	FM(RPC_RESET_N)
-#define GPSR5_11	FM(QSPI1_SSL)
-#define GPSR5_10	FM(QSPI1_IO3)
-#define GPSR5_9		FM(QSPI1_IO2)
-#define GPSR5_8		FM(QSPI1_MISO_IO1)
-#define GPSR5_7		FM(QSPI1_MOSI_IO0)
-#define GPSR5_6		FM(QSPI1_SPCLK)
-#define GPSR5_5		FM(QSPI0_SSL)
-#define GPSR5_4		FM(QSPI0_IO3)
-#define GPSR5_3		FM(QSPI0_IO2)
-#define GPSR5_2		FM(QSPI0_MISO_IO1)
-#define GPSR5_1		FM(QSPI0_MOSI_IO0)
-#define GPSR5_0		FM(QSPI0_SPCLK)
-
-
-/* IPSRx */		/* 0 */				/* 1 */			/* 2 */		/* 3 */		/* 4 */			/* 5 */		/* 6 - F */
-#define IP0_3_0		FM(DU_DR2)			FM(HSCK0)		F_(0, 0)	FM(A0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_7_4		FM(DU_DR3)			FM(HRTS0_N)		F_(0, 0)	FM(A1)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_11_8	FM(DU_DR4)			FM(HCTS0_N)		F_(0, 0)	FM(A2)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)	F_(0, 0) F_(0, 0)
-#define IP0_15_12	FM(DU_DR5)			FM(HTX0)		F_(0, 0)	FM(A3)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_19_16	FM(DU_DR6)			FM(MSIOF3_RXD)		F_(0, 0)	FM(A4)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_23_20	FM(DU_DR7)			FM(MSIOF3_TXD)		F_(0, 0)	FM(A5)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_27_24	FM(DU_DG2)			FM(MSIOF3_SS1)		F_(0, 0)	FM(A6)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_31_28	FM(DU_DG3)			FM(MSIOF3_SS2)		F_(0, 0)	FM(A7)		FM(PWMFSW0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_3_0		FM(DU_DG4)			F_(0, 0)		F_(0, 0)	FM(A8)		FM(FSO_CFE_0_N_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_7_4		FM(DU_DG5)			F_(0, 0)		F_(0, 0)	FM(A9)		FM(FSO_CFE_1_N_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_11_8	FM(DU_DG6)			F_(0, 0)		F_(0, 0)	FM(A10)		FM(FSO_TOE_N_A) 	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_15_12	FM(DU_DG7)			F_(0, 0)		F_(0, 0)	FM(A11)		FM(IRQ1)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_19_16	FM(DU_DB2)			F_(0, 0)		F_(0, 0)	FM(A12)		FM(IRQ2)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_23_20	FM(DU_DB3)			F_(0, 0)		F_(0, 0)	FM(A13)		FM(FXR_CLKOUT1)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_27_24	FM(DU_DB4)			F_(0, 0)		F_(0, 0)	FM(A14)		FM(FXR_CLKOUT2)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_31_28	FM(DU_DB5)			F_(0, 0)		F_(0, 0)	FM(A15)		FM(FXR_TXENA_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_3_0		FM(DU_DB6)			F_(0, 0)		F_(0, 0)	FM(A16)		FM(FXR_TXENB_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_7_4		FM(DU_DB7)			F_(0, 0)		F_(0, 0)	FM(A17)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_11_8	FM(DU_DOTCLKOUT)		FM(SCIF_CLK_A)		F_(0, 0)	FM(A18)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_15_12	FM(DU_EXHSYNC_DU_HSYNC)		FM(HRX0)		F_(0, 0)	FM(A19)		FM(IRQ3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_19_16	FM(DU_EXVSYNC_DU_VSYNC)		FM(MSIOF3_SCK)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_23_20	FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(MSIOF3_SYNC)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_27_24	FM(IRQ0)			F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_31_28	FM(VI0_CLK)			FM(MSIOF2_SCK)		FM(SCK3)	F_(0, 0)	FM(HSCK3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_3_0		FM(VI0_CLKENB)			FM(MSIOF2_RXD)		FM(RX3)		FM(RD_WR_N)	FM(HCTS3_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_7_4		FM(VI0_HSYNC_N)			FM(MSIOF2_TXD)		FM(TX3)		F_(0, 0)	FM(HRTS3_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_11_8	FM(VI0_VSYNC_N)			FM(MSIOF2_SYNC)		FM(CTS3_N)	F_(0, 0)	FM(HTX3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_15_12	FM(VI0_DATA0)			FM(MSIOF2_SS1)		FM(RTS3_N)	F_(0, 0)	FM(HRX3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_19_16	FM(VI0_DATA1)			FM(MSIOF2_SS2)		FM(SCK1)	F_(0, 0)	FM(SPEEDIN_A)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_23_20	FM(VI0_DATA2)			FM(AVB0_AVTP_PPS)	FM(SDA3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_27_24	FM(VI0_DATA3)			FM(HSCK1)		FM(SCL3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_31_28	FM(VI0_DATA4)			FM(HRTS1_N)		FM(RX1_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_3_0		FM(VI0_DATA5)			FM(HCTS1_N)		FM(TX1_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_7_4		FM(VI0_DATA6)			FM(HTX1)		FM(CTS1_N)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_11_8	FM(VI0_DATA7)			FM(HRX1)		FM(RTS1_N)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_15_12	FM(VI0_DATA8)			FM(HSCK2)		FM(PWM0_A)	FM(A22)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_19_16	FM(VI0_DATA9)			FM(HCTS2_N)		FM(PWM1_A)	FM(A23)		FM(FSO_CFE_0_N_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_23_20	FM(VI0_DATA10)			FM(HRTS2_N)		FM(PWM2_A)	FM(A24)		FM(FSO_CFE_1_N_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_27_24	FM(VI0_DATA11)			FM(HTX2)		FM(PWM3_A)	FM(A25)		FM(FSO_TOE_N_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_31_28	FM(VI0_FIELD)			FM(HRX2)		FM(PWM4_A)	FM(CS1_N)	FM(FSCLKST2_N_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_3_0		FM(VI1_CLK)			FM(MSIOF1_RXD)		F_(0, 0)	FM(CS0_N)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_7_4		FM(VI1_CLKENB)			FM(MSIOF1_TXD)		F_(0, 0)	FM(D0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_11_8	FM(VI1_HSYNC_N)			FM(MSIOF1_SCK)		F_(0, 0)	FM(D1)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_15_12	FM(VI1_VSYNC_N)			FM(MSIOF1_SYNC)		F_(0, 0)	FM(D2)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_19_16	FM(VI1_DATA0)			FM(MSIOF1_SS1)		F_(0, 0)	FM(D3)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_23_20	FM(VI1_DATA1)			FM(MSIOF1_SS2)		F_(0, 0)	FM(D4)		FM(MMC_CMD)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_27_24	FM(VI1_DATA2)			FM(CANFD0_TX_B)		F_(0, 0)	FM(D5)		FM(MMC_D0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_31_28	FM(VI1_DATA3)			FM(CANFD0_RX_B)		F_(0, 0)	FM(D6)		FM(MMC_D1)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_3_0		FM(VI1_DATA4)			FM(CANFD_CLK_B)		F_(0, 0)	FM(D7)		FM(MMC_D2)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_7_4		FM(VI1_DATA5)			F_(0, 0)		FM(SCK4)	FM(D8)		FM(MMC_D3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_11_8	FM(VI1_DATA6)			F_(0, 0)		FM(RX4)		FM(D9)		FM(MMC_CLK)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_15_12	FM(VI1_DATA7)			F_(0, 0)		FM(TX4)		FM(D10)		FM(MMC_D4)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_19_16	FM(VI1_DATA8)			F_(0, 0)		FM(CTS4_N)	FM(D11)		FM(MMC_D5)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_23_20	FM(VI1_DATA9)			F_(0, 0)		FM(RTS4_N)	FM(D12)		FM(MMC_D6)		FM(SCL3_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_27_24	FM(VI1_DATA10)			F_(0, 0)		F_(0, 0)	FM(D13)		FM(MMC_D7)		FM(SDA3_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_31_28	FM(VI1_DATA11)			FM(SCL4)		FM(IRQ4)	FM(D14)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_3_0		FM(VI1_FIELD)			FM(SDA4)		FM(IRQ5)	FM(D15)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_7_4		FM(SCL0)			FM(DU_DR0)		FM(TPU0TO0)	FM(CLKOUT)	F_(0, 0)		FM(MSIOF0_RXD)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_11_8	FM(SDA0)			FM(DU_DR1)		FM(TPU0TO1)	FM(BS_N)	FM(SCK0)		FM(MSIOF0_TXD)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_15_12	FM(SCL1)			FM(DU_DG0)		FM(TPU0TO2)	FM(RD_N)	FM(CTS0_N)		FM(MSIOF0_SCK)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_19_16	FM(SDA1)			FM(DU_DG1)		FM(TPU0TO3)	FM(WE0_N)	FM(RTS0_N)		FM(MSIOF0_SYNC)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_23_20	FM(SCL2)			FM(DU_DB0)		FM(TCLK1_A)	FM(WE1_N)	FM(RX0)			FM(MSIOF0_SS1)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_27_24	FM(SDA2)			FM(DU_DB1)		FM(TCLK2_A)	FM(EX_WAIT0)	FM(TX0)			FM(MSIOF0_SS2)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_31_28	FM(AVB0_AVTP_CAPTURE)		F_(0, 0)		F_(0, 0)	F_(0, 0)	FM(FSCLKST2_N_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_3_0		FM(CANFD0_TX_A)			FM(FXR_TXDA)		FM(PWM0_B)	FM(DU_DISP)	FM(FSCLKST2_N_C)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_7_4		FM(CANFD0_RX_A)			FM(RXDA_EXTFXR)		FM(PWM1_B)	FM(DU_CDE)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_11_8	FM(CANFD1_TX)			FM(FXR_TXDB)		FM(PWM2_B)	FM(TCLK1_B)	FM(TX1_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_15_12	FM(CANFD1_RX)			FM(RXDB_EXTFXR)		FM(PWM3_B)	FM(TCLK2_B)	FM(RX1_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_19_16	FM(CANFD_CLK_A)			FM(CLK_EXTFXR)		FM(PWM4_B)	FM(SPEEDIN_B)	FM(SCIF_CLK_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_23_20	FM(DIGRF_CLKIN)			FM(DIGRF_CLKEN_IN)	F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_27_24	FM(DIGRF_CLKOUT)		FM(DIGRF_CLKEN_OUT)	F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_31_28	F_(0, 0)			F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0)
-
-#define PINMUX_GPSR	\
-\
-		GPSR1_27 \
-		GPSR1_26 \
-		GPSR1_25 \
-		GPSR1_24 \
-		GPSR1_23 \
-		GPSR1_22 \
-GPSR0_21	GPSR1_21 \
-GPSR0_20	GPSR1_20 \
-GPSR0_19	GPSR1_19 \
-GPSR0_18	GPSR1_18 \
-GPSR0_17	GPSR1_17 \
-GPSR0_16	GPSR1_16	GPSR2_16	GPSR3_16 \
-GPSR0_15	GPSR1_15	GPSR2_15	GPSR3_15 \
-GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14			GPSR5_14 \
-GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13			GPSR5_13 \
-GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12			GPSR5_12 \
-GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11			GPSR5_11 \
-GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10			GPSR5_10 \
-GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9				GPSR5_9 \
-GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8				GPSR5_8 \
-GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7				GPSR5_7 \
-GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6				GPSR5_6 \
-GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5 \
-GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4 \
-GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3 \
-GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2 \
-GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1 \
-GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0
-
-#define PINMUX_IPSR	\
-\
-FM(IP0_3_0)	IP0_3_0		FM(IP1_3_0)	IP1_3_0		FM(IP2_3_0)	IP2_3_0		FM(IP3_3_0)	IP3_3_0 \
-FM(IP0_7_4)	IP0_7_4		FM(IP1_7_4)	IP1_7_4		FM(IP2_7_4)	IP2_7_4		FM(IP3_7_4)	IP3_7_4 \
-FM(IP0_11_8)	IP0_11_8	FM(IP1_11_8)	IP1_11_8	FM(IP2_11_8)	IP2_11_8	FM(IP3_11_8)	IP3_11_8 \
-FM(IP0_15_12)	IP0_15_12	FM(IP1_15_12)	IP1_15_12	FM(IP2_15_12)	IP2_15_12	FM(IP3_15_12)	IP3_15_12 \
-FM(IP0_19_16)	IP0_19_16	FM(IP1_19_16)	IP1_19_16	FM(IP2_19_16)	IP2_19_16	FM(IP3_19_16)	IP3_19_16 \
-FM(IP0_23_20)	IP0_23_20	FM(IP1_23_20)	IP1_23_20	FM(IP2_23_20)	IP2_23_20	FM(IP3_23_20)	IP3_23_20 \
-FM(IP0_27_24)	IP0_27_24	FM(IP1_27_24)	IP1_27_24	FM(IP2_27_24)	IP2_27_24	FM(IP3_27_24)	IP3_27_24 \
-FM(IP0_31_28)	IP0_31_28	FM(IP1_31_28)	IP1_31_28	FM(IP2_31_28)	IP2_31_28	FM(IP3_31_28)	IP3_31_28 \
-\
-FM(IP4_3_0)	IP4_3_0		FM(IP5_3_0)	IP5_3_0		FM(IP6_3_0)	IP6_3_0		FM(IP7_3_0)	IP7_3_0 \
-FM(IP4_7_4)	IP4_7_4		FM(IP5_7_4)	IP5_7_4		FM(IP6_7_4)	IP6_7_4		FM(IP7_7_4)	IP7_7_4 \
-FM(IP4_11_8)	IP4_11_8	FM(IP5_11_8)	IP5_11_8	FM(IP6_11_8)	IP6_11_8	FM(IP7_11_8)	IP7_11_8 \
-FM(IP4_15_12)	IP4_15_12	FM(IP5_15_12)	IP5_15_12	FM(IP6_15_12)	IP6_15_12	FM(IP7_15_12)	IP7_15_12 \
-FM(IP4_19_16)	IP4_19_16	FM(IP5_19_16)	IP5_19_16	FM(IP6_19_16)	IP6_19_16	FM(IP7_19_16)	IP7_19_16 \
-FM(IP4_23_20)	IP4_23_20	FM(IP5_23_20)	IP5_23_20	FM(IP6_23_20)	IP6_23_20	FM(IP7_23_20)	IP7_23_20 \
-FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
-FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
-\
-FM(IP8_3_0)	IP8_3_0 \
-FM(IP8_7_4)	IP8_7_4 \
-FM(IP8_11_8)	IP8_11_8 \
-FM(IP8_15_12)	IP8_15_12 \
-FM(IP8_19_16)	IP8_19_16 \
-FM(IP8_23_20)	IP8_23_20 \
-FM(IP8_27_24)	IP8_27_24 \
-FM(IP8_31_28)	IP8_31_28
-
-/* MOD_SEL0 */		/* 0 */			/* 1 */
-#define MOD_SEL0_11	FM(SEL_I2C3_0)		FM(SEL_I2C3_1)
-#define MOD_SEL0_10	FM(SEL_HSCIF0_0)	FM(SEL_HSCIF0_1)
-#define MOD_SEL0_9	FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
-#define MOD_SEL0_8	FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
-#define MOD_SEL0_7	FM(SEL_PWM4_0)		FM(SEL_PWM4_1)
-#define MOD_SEL0_6	FM(SEL_PWM3_0)		FM(SEL_PWM3_1)
-#define MOD_SEL0_5	FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
-#define MOD_SEL0_4	FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
-#define MOD_SEL0_3	FM(SEL_PWM0_0)		FM(SEL_PWM0_1)
-#define MOD_SEL0_2	FM(SEL_RFSO_0)		FM(SEL_RFSO_1)
-#define MOD_SEL0_1	FM(SEL_RSP_0)		FM(SEL_RSP_1)
-#define MOD_SEL0_0	FM(SEL_TMU_0)		FM(SEL_TMU_1)
-
-#define PINMUX_MOD_SELS \
-\
-MOD_SEL0_11 \
-MOD_SEL0_10 \
-MOD_SEL0_9 \
-MOD_SEL0_8 \
-MOD_SEL0_7 \
-MOD_SEL0_6 \
-MOD_SEL0_5 \
-MOD_SEL0_4 \
-MOD_SEL0_3 \
-MOD_SEL0_2 \
-MOD_SEL0_1 \
-MOD_SEL0_0
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	GP_ALL(DATA),
-	PINMUX_DATA_END,
-
-#define F_(x, y)
-#define FM(x)   FN_##x,
-	PINMUX_FUNCTION_BEGIN,
-	GP_ALL(FN),
-	PINMUX_GPSR
-	PINMUX_IPSR
-	PINMUX_MOD_SELS
-	PINMUX_FUNCTION_END,
-#undef F_
-#undef FM
-
-#define F_(x, y)
-#define FM(x)	x##_MARK,
-	PINMUX_MARK_BEGIN,
-	PINMUX_GPSR
-	PINMUX_IPSR
-	PINMUX_MOD_SELS
-	PINMUX_MARK_END,
-#undef F_
-#undef FM
-};
-
-static const u16 pinmux_data[] = {
-	PINMUX_DATA_GP_ALL(),
-
-	PINMUX_SINGLE(AVB0_RX_CTL),
-	PINMUX_SINGLE(AVB0_RXC),
-	PINMUX_SINGLE(AVB0_RD0),
-	PINMUX_SINGLE(AVB0_RD1),
-	PINMUX_SINGLE(AVB0_RD2),
-	PINMUX_SINGLE(AVB0_RD3),
-	PINMUX_SINGLE(AVB0_TX_CTL),
-	PINMUX_SINGLE(AVB0_TXC),
-	PINMUX_SINGLE(AVB0_TD0),
-	PINMUX_SINGLE(AVB0_TD1),
-	PINMUX_SINGLE(AVB0_TD2),
-	PINMUX_SINGLE(AVB0_TD3),
-	PINMUX_SINGLE(AVB0_TXCREFCLK),
-	PINMUX_SINGLE(AVB0_MDIO),
-	PINMUX_SINGLE(AVB0_MDC),
-	PINMUX_SINGLE(AVB0_MAGIC),
-	PINMUX_SINGLE(AVB0_PHY_INT),
-	PINMUX_SINGLE(AVB0_LINK),
-	PINMUX_SINGLE(AVB0_AVTP_MATCH),
-
-	PINMUX_SINGLE(QSPI0_SPCLK),
-	PINMUX_SINGLE(QSPI0_MOSI_IO0),
-	PINMUX_SINGLE(QSPI0_MISO_IO1),
-	PINMUX_SINGLE(QSPI0_IO2),
-	PINMUX_SINGLE(QSPI0_IO3),
-	PINMUX_SINGLE(QSPI0_SSL),
-	PINMUX_SINGLE(QSPI1_SPCLK),
-	PINMUX_SINGLE(QSPI1_MOSI_IO0),
-	PINMUX_SINGLE(QSPI1_MISO_IO1),
-	PINMUX_SINGLE(QSPI1_IO2),
-	PINMUX_SINGLE(QSPI1_IO3),
-	PINMUX_SINGLE(QSPI1_SSL),
-	PINMUX_SINGLE(RPC_RESET_N),
-	PINMUX_SINGLE(RPC_WP_N),
-	PINMUX_SINGLE(RPC_INT_N),
-
-	/* IPSR0 */
-	PINMUX_IPSR_GPSR(IP0_3_0,	DU_DR2),
-	PINMUX_IPSR_GPSR(IP0_3_0,	HSCK0),
-	PINMUX_IPSR_GPSR(IP0_3_0,	A0),
-
-	PINMUX_IPSR_GPSR(IP0_7_4,	DU_DR3),
-	PINMUX_IPSR_GPSR(IP0_7_4,	HRTS0_N),
-	PINMUX_IPSR_GPSR(IP0_7_4,	A1),
-
-	PINMUX_IPSR_GPSR(IP0_11_8,	DU_DR4),
-	PINMUX_IPSR_GPSR(IP0_11_8,	HCTS0_N),
-	PINMUX_IPSR_GPSR(IP0_11_8,	A2),
-
-	PINMUX_IPSR_GPSR(IP0_15_12,	DU_DR5),
-	PINMUX_IPSR_GPSR(IP0_15_12,	HTX0),
-	PINMUX_IPSR_GPSR(IP0_15_12,	A3),
-
-	PINMUX_IPSR_GPSR(IP0_19_16,	DU_DR6),
-	PINMUX_IPSR_GPSR(IP0_19_16,	MSIOF3_RXD),
-	PINMUX_IPSR_GPSR(IP0_19_16,	A4),
-
-	PINMUX_IPSR_GPSR(IP0_23_20,	DU_DR7),
-	PINMUX_IPSR_GPSR(IP0_23_20,	MSIOF3_TXD),
-	PINMUX_IPSR_GPSR(IP0_23_20,	A5),
-
-	PINMUX_IPSR_GPSR(IP0_27_24,	DU_DG2),
-	PINMUX_IPSR_GPSR(IP0_27_24,	MSIOF3_SS1),
-	PINMUX_IPSR_GPSR(IP0_27_24,	A6),
-
-	PINMUX_IPSR_GPSR(IP0_31_28,	DU_DG3),
-	PINMUX_IPSR_GPSR(IP0_31_28,	MSIOF3_SS2),
-	PINMUX_IPSR_GPSR(IP0_31_28,	A7),
-	PINMUX_IPSR_GPSR(IP0_31_28,	PWMFSW0),
-
-	/* IPSR1 */
-	PINMUX_IPSR_GPSR(IP1_3_0,	DU_DG4),
-	PINMUX_IPSR_GPSR(IP1_3_0,	A8),
-	PINMUX_IPSR_MSEL(IP1_3_0,	FSO_CFE_0_N_A,	SEL_RFSO_0),
-
-	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DG5),
-	PINMUX_IPSR_GPSR(IP1_7_4,	A9),
-	PINMUX_IPSR_MSEL(IP1_7_4,	FSO_CFE_1_N_A,	SEL_RFSO_0),
-
-	PINMUX_IPSR_GPSR(IP1_11_8,	DU_DG6),
-	PINMUX_IPSR_GPSR(IP1_11_8,	A10),
-	PINMUX_IPSR_MSEL(IP1_11_8,	FSO_TOE_N_A,	SEL_RFSO_0),
-
-	PINMUX_IPSR_GPSR(IP1_15_12,	DU_DG7),
-	PINMUX_IPSR_GPSR(IP1_15_12,	A11),
-	PINMUX_IPSR_GPSR(IP1_15_12,	IRQ1),
-
-	PINMUX_IPSR_GPSR(IP1_19_16,	DU_DB2),
-	PINMUX_IPSR_GPSR(IP1_19_16,	A12),
-	PINMUX_IPSR_GPSR(IP1_19_16,	IRQ2),
-
-	PINMUX_IPSR_GPSR(IP1_23_20,	DU_DB3),
-	PINMUX_IPSR_GPSR(IP1_23_20,	A13),
-	PINMUX_IPSR_GPSR(IP1_23_20,	FXR_CLKOUT1),
-
-	PINMUX_IPSR_GPSR(IP1_27_24,	DU_DB4),
-	PINMUX_IPSR_GPSR(IP1_27_24,	A14),
-	PINMUX_IPSR_GPSR(IP1_27_24,	FXR_CLKOUT2),
-
-	PINMUX_IPSR_GPSR(IP1_31_28,	DU_DB5),
-	PINMUX_IPSR_GPSR(IP1_31_28,	A15),
-	PINMUX_IPSR_GPSR(IP1_31_28,	FXR_TXENA_N),
-
-	/* IPSR2 */
-	PINMUX_IPSR_GPSR(IP2_3_0,	DU_DB6),
-	PINMUX_IPSR_GPSR(IP2_3_0,	A16),
-	PINMUX_IPSR_GPSR(IP2_3_0,	FXR_TXENB_N),
-
-	PINMUX_IPSR_GPSR(IP2_7_4,	DU_DB7),
-	PINMUX_IPSR_GPSR(IP2_7_4,	A17),
-
-	PINMUX_IPSR_GPSR(IP2_11_8,	DU_DOTCLKOUT),
-	PINMUX_IPSR_MSEL(IP2_11_8,	SCIF_CLK_A,	SEL_HSCIF0_0),
-	PINMUX_IPSR_GPSR(IP2_11_8,	A18),
-
-	PINMUX_IPSR_GPSR(IP2_15_12,	DU_EXHSYNC_DU_HSYNC),
-	PINMUX_IPSR_GPSR(IP2_15_12,	HRX0),
-	PINMUX_IPSR_GPSR(IP2_15_12,	A19),
-	PINMUX_IPSR_GPSR(IP2_15_12,	IRQ3),
-
-	PINMUX_IPSR_GPSR(IP2_19_16,	DU_EXVSYNC_DU_VSYNC),
-	PINMUX_IPSR_GPSR(IP2_19_16,	MSIOF3_SCK),
-
-	PINMUX_IPSR_GPSR(IP2_23_20,	DU_EXODDF_DU_ODDF_DISP_CDE),
-	PINMUX_IPSR_GPSR(IP2_23_20,	MSIOF3_SYNC),
-
-	PINMUX_IPSR_GPSR(IP2_27_24,	IRQ0),
-
-	PINMUX_IPSR_GPSR(IP2_31_28,	VI0_CLK),
-	PINMUX_IPSR_GPSR(IP2_31_28,	MSIOF2_SCK),
-	PINMUX_IPSR_GPSR(IP2_31_28,	SCK3),
-	PINMUX_IPSR_GPSR(IP2_31_28,	HSCK3),
-
-	/* IPSR3 */
-	PINMUX_IPSR_GPSR(IP3_3_0,	VI0_CLKENB),
-	PINMUX_IPSR_GPSR(IP3_3_0,	MSIOF2_RXD),
-	PINMUX_IPSR_GPSR(IP3_3_0,	RX3),
-	PINMUX_IPSR_GPSR(IP3_3_0,	RD_WR_N),
-	PINMUX_IPSR_GPSR(IP3_3_0,	HCTS3_N),
-
-	PINMUX_IPSR_GPSR(IP3_7_4,	VI0_HSYNC_N),
-	PINMUX_IPSR_GPSR(IP3_7_4,	MSIOF2_TXD),
-	PINMUX_IPSR_GPSR(IP3_7_4,	TX3),
-	PINMUX_IPSR_GPSR(IP3_7_4,	HRTS3_N),
-
-	PINMUX_IPSR_GPSR(IP3_11_8,	VI0_VSYNC_N),
-	PINMUX_IPSR_GPSR(IP3_11_8,	MSIOF2_SYNC),
-	PINMUX_IPSR_GPSR(IP3_11_8,	CTS3_N),
-	PINMUX_IPSR_GPSR(IP3_11_8,	HTX3),
-
-	PINMUX_IPSR_GPSR(IP3_15_12,	VI0_DATA0),
-	PINMUX_IPSR_GPSR(IP3_15_12,	MSIOF2_SS1),
-	PINMUX_IPSR_GPSR(IP3_15_12,	RTS3_N),
-	PINMUX_IPSR_GPSR(IP3_15_12,	HRX3),
-
-	PINMUX_IPSR_GPSR(IP3_19_16,	VI0_DATA1),
-	PINMUX_IPSR_GPSR(IP3_19_16,	MSIOF2_SS2),
-	PINMUX_IPSR_GPSR(IP3_19_16,	SCK1),
-	PINMUX_IPSR_MSEL(IP3_19_16,	SPEEDIN_A,	SEL_RSP_0),
-
-	PINMUX_IPSR_GPSR(IP3_23_20,	VI0_DATA2),
-	PINMUX_IPSR_GPSR(IP3_23_20,	AVB0_AVTP_PPS),
-	PINMUX_IPSR_MSEL(IP3_23_20,	SDA3_A,		SEL_I2C3_0),
-
-	PINMUX_IPSR_GPSR(IP3_27_24,	VI0_DATA3),
-	PINMUX_IPSR_GPSR(IP3_27_24,	HSCK1),
-	PINMUX_IPSR_MSEL(IP3_27_24,	SCL3_A,		SEL_I2C3_0),
-
-	PINMUX_IPSR_GPSR(IP3_31_28,	VI0_DATA4),
-	PINMUX_IPSR_GPSR(IP3_31_28,	HRTS1_N),
-	PINMUX_IPSR_MSEL(IP3_31_28,	RX1_A,	SEL_SCIF1_0),
-
-	/* IPSR4 */
-	PINMUX_IPSR_GPSR(IP4_3_0,	VI0_DATA5),
-	PINMUX_IPSR_GPSR(IP4_3_0,	HCTS1_N),
-	PINMUX_IPSR_MSEL(IP4_3_0,	TX1_A,	SEL_SCIF1_0),
-
-	PINMUX_IPSR_GPSR(IP4_7_4,	VI0_DATA6),
-	PINMUX_IPSR_GPSR(IP4_7_4,	HTX1),
-	PINMUX_IPSR_GPSR(IP4_7_4,	CTS1_N),
-
-	PINMUX_IPSR_GPSR(IP4_11_8,	VI0_DATA7),
-	PINMUX_IPSR_GPSR(IP4_11_8,	HRX1),
-	PINMUX_IPSR_GPSR(IP4_11_8,	RTS1_N),
-
-	PINMUX_IPSR_GPSR(IP4_15_12,	VI0_DATA8),
-	PINMUX_IPSR_GPSR(IP4_15_12,	HSCK2),
-	PINMUX_IPSR_MSEL(IP4_15_12,	PWM0_A,	SEL_PWM0_0),
-
-	PINMUX_IPSR_GPSR(IP4_19_16,	VI0_DATA9),
-	PINMUX_IPSR_GPSR(IP4_19_16,	HCTS2_N),
-	PINMUX_IPSR_MSEL(IP4_19_16,	PWM1_A,	SEL_PWM1_0),
-	PINMUX_IPSR_MSEL(IP4_19_16,	FSO_CFE_0_N_B,	SEL_RFSO_1),
-
-	PINMUX_IPSR_GPSR(IP4_23_20,	VI0_DATA10),
-	PINMUX_IPSR_GPSR(IP4_23_20,	HRTS2_N),
-	PINMUX_IPSR_MSEL(IP4_23_20,	PWM2_A,	SEL_PWM2_0),
-	PINMUX_IPSR_MSEL(IP4_23_20,	FSO_CFE_1_N_B,	SEL_RFSO_1),
-
-	PINMUX_IPSR_GPSR(IP4_27_24,	VI0_DATA11),
-	PINMUX_IPSR_GPSR(IP4_27_24,	HTX2),
-	PINMUX_IPSR_MSEL(IP4_27_24,	PWM3_A,	SEL_PWM3_0),
-	PINMUX_IPSR_MSEL(IP4_27_24,	FSO_TOE_N_B,	SEL_RFSO_1),
-
-	PINMUX_IPSR_GPSR(IP4_31_28,	VI0_FIELD),
-	PINMUX_IPSR_GPSR(IP4_31_28,	HRX2),
-	PINMUX_IPSR_MSEL(IP4_31_28,	PWM4_A,	SEL_PWM4_0),
-	PINMUX_IPSR_GPSR(IP4_31_28,	CS1_N),
-	PINMUX_IPSR_GPSR(IP4_31_28,	FSCLKST2_N_A),
-
-	/* IPSR5 */
-	PINMUX_IPSR_GPSR(IP5_3_0,	VI1_CLK),
-	PINMUX_IPSR_GPSR(IP5_3_0,	MSIOF1_RXD),
-	PINMUX_IPSR_GPSR(IP5_3_0,	CS0_N),
-
-	PINMUX_IPSR_GPSR(IP5_7_4,	VI1_CLKENB),
-	PINMUX_IPSR_GPSR(IP5_7_4,	MSIOF1_TXD),
-	PINMUX_IPSR_GPSR(IP5_7_4,	D0),
-
-	PINMUX_IPSR_GPSR(IP5_11_8,	VI1_HSYNC_N),
-	PINMUX_IPSR_GPSR(IP5_11_8,	MSIOF1_SCK),
-	PINMUX_IPSR_GPSR(IP5_11_8,	D1),
-
-	PINMUX_IPSR_GPSR(IP5_15_12,	VI1_VSYNC_N),
-	PINMUX_IPSR_GPSR(IP5_15_12,	MSIOF1_SYNC),
-	PINMUX_IPSR_GPSR(IP5_15_12,	D2),
-
-	PINMUX_IPSR_GPSR(IP5_19_16,	VI1_DATA0),
-	PINMUX_IPSR_GPSR(IP5_19_16,	MSIOF1_SS1),
-	PINMUX_IPSR_GPSR(IP5_19_16,	D3),
-
-	PINMUX_IPSR_GPSR(IP5_23_20,	VI1_DATA1),
-	PINMUX_IPSR_GPSR(IP5_23_20,	MSIOF1_SS2),
-	PINMUX_IPSR_GPSR(IP5_23_20,	D4),
-	PINMUX_IPSR_GPSR(IP5_23_20,	MMC_CMD),
-
-	PINMUX_IPSR_GPSR(IP5_27_24,	VI1_DATA2),
-	PINMUX_IPSR_MSEL(IP5_27_24,	CANFD0_TX_B,	SEL_CANFD0_1),
-	PINMUX_IPSR_GPSR(IP5_27_24,	D5),
-	PINMUX_IPSR_GPSR(IP5_27_24,	MMC_D0),
-
-	PINMUX_IPSR_GPSR(IP5_31_28,	VI1_DATA3),
-	PINMUX_IPSR_MSEL(IP5_31_28,	CANFD0_RX_B,	SEL_CANFD0_1),
-	PINMUX_IPSR_GPSR(IP5_31_28,	D6),
-	PINMUX_IPSR_GPSR(IP5_31_28,	MMC_D1),
-
-	/* IPSR6 */
-	PINMUX_IPSR_GPSR(IP6_3_0,	VI1_DATA4),
-	PINMUX_IPSR_MSEL(IP6_3_0,	CANFD_CLK_B,	SEL_CANFD0_1),
-	PINMUX_IPSR_GPSR(IP6_3_0,	D7),
-	PINMUX_IPSR_GPSR(IP6_3_0,	MMC_D2),
-
-	PINMUX_IPSR_GPSR(IP6_7_4,	VI1_DATA5),
-	PINMUX_IPSR_GPSR(IP6_7_4,	SCK4),
-	PINMUX_IPSR_GPSR(IP6_7_4,	D8),
-	PINMUX_IPSR_GPSR(IP6_7_4,	MMC_D3),
-
-	PINMUX_IPSR_GPSR(IP6_11_8,	VI1_DATA6),
-	PINMUX_IPSR_GPSR(IP6_11_8,	RX4),
-	PINMUX_IPSR_GPSR(IP6_11_8,	D9),
-	PINMUX_IPSR_GPSR(IP6_11_8,	MMC_CLK),
-
-	PINMUX_IPSR_GPSR(IP6_15_12,	VI1_DATA7),
-	PINMUX_IPSR_GPSR(IP6_15_12,	TX4),
-	PINMUX_IPSR_GPSR(IP6_15_12,	D10),
-	PINMUX_IPSR_GPSR(IP6_15_12,	MMC_D4),
-
-	PINMUX_IPSR_GPSR(IP6_19_16,	VI1_DATA8),
-	PINMUX_IPSR_GPSR(IP6_19_16,	CTS4_N),
-	PINMUX_IPSR_GPSR(IP6_19_16,	D11),
-	PINMUX_IPSR_GPSR(IP6_19_16,	MMC_D5),
-
-	PINMUX_IPSR_GPSR(IP6_23_20,	VI1_DATA9),
-	PINMUX_IPSR_GPSR(IP6_23_20,	RTS4_N),
-	PINMUX_IPSR_GPSR(IP6_23_20,	D12),
-	PINMUX_IPSR_GPSR(IP6_23_20,	MMC_D6),
-	PINMUX_IPSR_MSEL(IP6_23_20,	SCL3_B,	SEL_I2C3_1),
-
-	PINMUX_IPSR_GPSR(IP6_27_24,	VI1_DATA10),
-	PINMUX_IPSR_GPSR(IP6_27_24,	D13),
-	PINMUX_IPSR_GPSR(IP6_27_24,	MMC_D7),
-	PINMUX_IPSR_MSEL(IP6_27_24,	SDA3_B,	SEL_I2C3_1),
-
-	PINMUX_IPSR_GPSR(IP6_31_28,	VI1_DATA11),
-	PINMUX_IPSR_GPSR(IP6_31_28,	SCL4),
-	PINMUX_IPSR_GPSR(IP6_31_28,	IRQ4),
-	PINMUX_IPSR_GPSR(IP6_31_28,	D14),
-
-	/* IPSR7 */
-	PINMUX_IPSR_GPSR(IP7_3_0,	VI1_FIELD),
-	PINMUX_IPSR_GPSR(IP7_3_0,	SDA4),
-	PINMUX_IPSR_GPSR(IP7_3_0,	IRQ5),
-	PINMUX_IPSR_GPSR(IP7_3_0,	D15),
-
-	PINMUX_IPSR_GPSR(IP7_7_4,	SCL0),
-	PINMUX_IPSR_GPSR(IP7_7_4,	DU_DR0),
-	PINMUX_IPSR_GPSR(IP7_7_4,	TPU0TO0),
-	PINMUX_IPSR_GPSR(IP7_7_4,	CLKOUT),
-	PINMUX_IPSR_GPSR(IP7_7_4,	MSIOF0_RXD),
-
-	PINMUX_IPSR_GPSR(IP7_11_8,	SDA0),
-	PINMUX_IPSR_GPSR(IP7_11_8,	DU_DR1),
-	PINMUX_IPSR_GPSR(IP7_11_8,	TPU0TO1),
-	PINMUX_IPSR_GPSR(IP7_11_8,	BS_N),
-	PINMUX_IPSR_GPSR(IP7_11_8,	SCK0),
-	PINMUX_IPSR_GPSR(IP7_11_8,	MSIOF0_TXD),
-
-	PINMUX_IPSR_GPSR(IP7_15_12,	SCL1),
-	PINMUX_IPSR_GPSR(IP7_15_12,	DU_DG0),
-	PINMUX_IPSR_GPSR(IP7_15_12,	TPU0TO2),
-	PINMUX_IPSR_GPSR(IP7_15_12,	RD_N),
-	PINMUX_IPSR_GPSR(IP7_15_12,	CTS0_N),
-	PINMUX_IPSR_GPSR(IP7_15_12,	MSIOF0_SCK),
-
-	PINMUX_IPSR_GPSR(IP7_19_16,	SDA1),
-	PINMUX_IPSR_GPSR(IP7_19_16,	DU_DG1),
-	PINMUX_IPSR_GPSR(IP7_19_16,	TPU0TO3),
-	PINMUX_IPSR_GPSR(IP7_19_16,	WE0_N),
-	PINMUX_IPSR_GPSR(IP7_19_16,	RTS0_N),
-	PINMUX_IPSR_GPSR(IP7_19_16,	MSIOF0_SYNC),
-
-	PINMUX_IPSR_GPSR(IP7_23_20,	SCL2),
-	PINMUX_IPSR_GPSR(IP7_23_20,	DU_DB0),
-	PINMUX_IPSR_MSEL(IP7_23_20,	TCLK1_A,	SEL_TMU_0),
-	PINMUX_IPSR_GPSR(IP7_23_20,	WE1_N),
-	PINMUX_IPSR_GPSR(IP7_23_20,	RX0),
-	PINMUX_IPSR_GPSR(IP7_23_20,	MSIOF0_SS1),
-
-	PINMUX_IPSR_GPSR(IP7_27_24,	SDA2),
-	PINMUX_IPSR_GPSR(IP7_27_24,	DU_DB1),
-	PINMUX_IPSR_MSEL(IP7_27_24,	TCLK2_A,	SEL_TMU_0),
-	PINMUX_IPSR_GPSR(IP7_27_24,	EX_WAIT0),
-	PINMUX_IPSR_GPSR(IP7_27_24,	TX0),
-	PINMUX_IPSR_GPSR(IP7_27_24,	MSIOF0_SS2),
-
-	PINMUX_IPSR_GPSR(IP7_31_28,	AVB0_AVTP_CAPTURE),
-	PINMUX_IPSR_GPSR(IP7_31_28,	FSCLKST2_N_B),
-
-	/* IPSR8 */
-	PINMUX_IPSR_MSEL(IP8_3_0,	CANFD0_TX_A,	SEL_CANFD0_0),
-	PINMUX_IPSR_GPSR(IP8_3_0,	FXR_TXDA),
-	PINMUX_IPSR_MSEL(IP8_3_0,	PWM0_B,		SEL_PWM0_1),
-	PINMUX_IPSR_GPSR(IP8_3_0,	DU_DISP),
-	PINMUX_IPSR_GPSR(IP8_3_0,	FSCLKST2_N_C),
-
-	PINMUX_IPSR_MSEL(IP8_7_4,	CANFD0_RX_A,	SEL_CANFD0_0),
-	PINMUX_IPSR_GPSR(IP8_7_4,	RXDA_EXTFXR),
-	PINMUX_IPSR_MSEL(IP8_7_4,	PWM1_B,		SEL_PWM1_1),
-	PINMUX_IPSR_GPSR(IP8_7_4,	DU_CDE),
-
-	PINMUX_IPSR_GPSR(IP8_11_8,	CANFD1_TX),
-	PINMUX_IPSR_GPSR(IP8_11_8,	FXR_TXDB),
-	PINMUX_IPSR_MSEL(IP8_11_8,	PWM2_B,		SEL_PWM2_1),
-	PINMUX_IPSR_MSEL(IP8_11_8,	TCLK1_B,	SEL_TMU_1),
-	PINMUX_IPSR_MSEL(IP8_11_8,	TX1_B,		SEL_SCIF1_1),
-
-	PINMUX_IPSR_GPSR(IP8_15_12,	CANFD1_RX),
-	PINMUX_IPSR_GPSR(IP8_15_12,	RXDB_EXTFXR),
-	PINMUX_IPSR_MSEL(IP8_15_12,	PWM3_B,		SEL_PWM3_1),
-	PINMUX_IPSR_MSEL(IP8_15_12,	TCLK2_B,	SEL_TMU_1),
-	PINMUX_IPSR_MSEL(IP8_15_12,	RX1_B,		SEL_SCIF1_1),
-
-	PINMUX_IPSR_MSEL(IP8_19_16,	CANFD_CLK_A,	SEL_CANFD0_0),
-	PINMUX_IPSR_GPSR(IP8_19_16,	CLK_EXTFXR),
-	PINMUX_IPSR_MSEL(IP8_19_16,	PWM4_B,		SEL_PWM4_1),
-	PINMUX_IPSR_MSEL(IP8_19_16,	SPEEDIN_B,	SEL_RSP_1),
-	PINMUX_IPSR_MSEL(IP8_19_16,	SCIF_CLK_B,	SEL_HSCIF0_1),
-
-	PINMUX_IPSR_GPSR(IP8_23_20,	DIGRF_CLKIN),
-	PINMUX_IPSR_GPSR(IP8_23_20,	DIGRF_CLKEN_IN),
-
-	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKOUT),
-	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKEN_OUT),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	PINMUX_GPIO_GP_ALL(),
-};
-
-/* - AVB0 ------------------------------------------------------------------- */
-static const unsigned int avb0_link_pins[] = {
-	/* AVB0_LINK */
-	RCAR_GP_PIN(1, 18),
-};
-static const unsigned int avb0_link_mux[] = {
-	AVB0_LINK_MARK,
-};
-static const unsigned int avb0_magic_pins[] = {
-	/* AVB0_MAGIC */
-	RCAR_GP_PIN(1, 16),
-};
-static const unsigned int avb0_magic_mux[] = {
-	AVB0_MAGIC_MARK,
-};
-static const unsigned int avb0_phy_int_pins[] = {
-	/* AVB0_PHY_INT */
-	RCAR_GP_PIN(1, 17),
-};
-static const unsigned int avb0_phy_int_mux[] = {
-	AVB0_PHY_INT_MARK,
-};
-static const unsigned int avb0_mdio_pins[] = {
-	/* AVB0_MDC, AVB0_MDIO */
-	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
-};
-static const unsigned int avb0_mdio_mux[] = {
-	AVB0_MDC_MARK, AVB0_MDIO_MARK,
-};
-static const unsigned int avb0_rgmii_pins[] = {
-	/*
-	 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
-	 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3
-	 */
-	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
-	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
-	RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
-	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
-	RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
-	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
-};
-static const unsigned int avb0_rgmii_mux[] = {
-	AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
-	AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
-	AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
-	AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
-};
-static const unsigned int avb0_txcrefclk_pins[] = {
-	/* AVB0_TXCREFCLK */
-	RCAR_GP_PIN(1, 13),
-};
-static const unsigned int avb0_txcrefclk_mux[] = {
-	AVB0_TXCREFCLK_MARK,
-};
-static const unsigned int avb0_avtp_pps_pins[] = {
-	/* AVB0_AVTP_PPS */
-	RCAR_GP_PIN(2, 6),
-};
-static const unsigned int avb0_avtp_pps_mux[] = {
-	AVB0_AVTP_PPS_MARK,
-};
-static const unsigned int avb0_avtp_capture_pins[] = {
-	/* AVB0_AVTP_CAPTURE */
-	RCAR_GP_PIN(1, 20),
-};
-static const unsigned int avb0_avtp_capture_mux[] = {
-	AVB0_AVTP_CAPTURE_MARK,
-};
-static const unsigned int avb0_avtp_match_pins[] = {
-	/* AVB0_AVTP_MATCH */
-	RCAR_GP_PIN(1, 19),
-};
-static const unsigned int avb0_avtp_match_mux[] = {
-	AVB0_AVTP_MATCH_MARK,
-};
-
-/* - CANFD Clock ------------------------------------------------------------ */
-static const unsigned int canfd_clk_a_pins[] = {
-	/* CANFD_CLK */
-	RCAR_GP_PIN(1, 25),
-};
-static const unsigned int canfd_clk_a_mux[] = {
-	CANFD_CLK_A_MARK,
-};
-static const unsigned int canfd_clk_b_pins[] = {
-	/* CANFD_CLK */
-	RCAR_GP_PIN(3, 8),
-};
-static const unsigned int canfd_clk_b_mux[] = {
-	CANFD_CLK_B_MARK,
-};
-
-/* - CANFD0 ----------------------------------------------------------------- */
-static const unsigned int canfd0_data_a_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
-};
-static const unsigned int canfd0_data_a_mux[] = {
-	CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
-};
-static const unsigned int canfd0_data_b_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-};
-static const unsigned int canfd0_data_b_mux[] = {
-	CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
-};
-
-/* - CANFD1 ----------------------------------------------------------------- */
-static const unsigned int canfd1_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
-};
-static const unsigned int canfd1_data_mux[] = {
-	CANFD1_TX_MARK, CANFD1_RX_MARK,
-};
-
-/* - DU --------------------------------------------------------------------- */
-static const unsigned int du_rgb666_pins[] = {
-	/* R[7:2], G[7:2], B[7:2] */
-	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
-	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
-	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
-};
-static const unsigned int du_rgb666_mux[] = {
-	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
-	DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
-	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
-	DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
-	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
-	DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
-};
-static const unsigned int du_clk_out_pins[] = {
-	/* DOTCLKOUT */
-	RCAR_GP_PIN(0, 18),
-};
-static const unsigned int du_clk_out_mux[] = {
-	DU_DOTCLKOUT_MARK,
-};
-static const unsigned int du_sync_pins[] = {
-	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
-	RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
-};
-static const unsigned int du_sync_mux[] = {
-	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
-};
-static const unsigned int du_oddf_pins[] = {
-	/* EXODDF/ODDF/DISP/CDE */
-	RCAR_GP_PIN(0, 21),
-};
-static const unsigned int du_oddf_mux[] = {
-	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
-};
-static const unsigned int du_cde_pins[] = {
-	/* CDE */
-	RCAR_GP_PIN(1, 22),
-};
-static const unsigned int du_cde_mux[] = {
-	DU_CDE_MARK,
-};
-static const unsigned int du_disp_pins[] = {
-	/* DISP */
-	RCAR_GP_PIN(1, 21),
-};
-static const unsigned int du_disp_mux[] = {
-	DU_DISP_MARK,
-};
-
-/* - HSCIF0 ----------------------------------------------------------------- */
-static const unsigned int hscif0_data_pins[] = {
-	/* HRX, HTX */
-	RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
-};
-static const unsigned int hscif0_data_mux[] = {
-	HRX0_MARK, HTX0_MARK,
-};
-static const unsigned int hscif0_clk_pins[] = {
-	/* HSCK */
-	RCAR_GP_PIN(0, 0),
-};
-static const unsigned int hscif0_clk_mux[] = {
-	HSCK0_MARK,
-};
-static const unsigned int hscif0_ctrl_pins[] = {
-	/* HRTS#, HCTS# */
-	RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
-};
-static const unsigned int hscif0_ctrl_mux[] = {
-	HRTS0_N_MARK, HCTS0_N_MARK,
-};
-
-/* - HSCIF1 ----------------------------------------------------------------- */
-static const unsigned int hscif1_data_pins[] = {
-	/* HRX, HTX */
-	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
-};
-static const unsigned int hscif1_data_mux[] = {
-	HRX1_MARK, HTX1_MARK,
-};
-static const unsigned int hscif1_clk_pins[] = {
-	/* HSCK */
-	RCAR_GP_PIN(2, 7),
-};
-static const unsigned int hscif1_clk_mux[] = {
-	HSCK1_MARK,
-};
-static const unsigned int hscif1_ctrl_pins[] = {
-	/* HRTS#, HCTS# */
-	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
-};
-static const unsigned int hscif1_ctrl_mux[] = {
-	HRTS1_N_MARK, HCTS1_N_MARK,
-};
-
-/* - HSCIF2 ----------------------------------------------------------------- */
-static const unsigned int hscif2_data_pins[] = {
-	/* HRX, HTX */
-	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
-};
-static const unsigned int hscif2_data_mux[] = {
-	HRX2_MARK, HTX2_MARK,
-};
-static const unsigned int hscif2_clk_pins[] = {
-	/* HSCK */
-	RCAR_GP_PIN(2, 12),
-};
-static const unsigned int hscif2_clk_mux[] = {
-	HSCK2_MARK,
-};
-static const unsigned int hscif2_ctrl_pins[] = {
-	/* HRTS#, HCTS# */
-	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
-};
-static const unsigned int hscif2_ctrl_mux[] = {
-	HRTS2_N_MARK, HCTS2_N_MARK,
-};
-
-/* - HSCIF3 ----------------------------------------------------------------- */
-static const unsigned int hscif3_data_pins[] = {
-	/* HRX, HTX */
-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
-};
-static const unsigned int hscif3_data_mux[] = {
-	HRX3_MARK, HTX3_MARK,
-};
-static const unsigned int hscif3_clk_pins[] = {
-	/* HSCK */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int hscif3_clk_mux[] = {
-	HSCK3_MARK,
-};
-static const unsigned int hscif3_ctrl_pins[] = {
-	/* HRTS#, HCTS# */
-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
-};
-static const unsigned int hscif3_ctrl_mux[] = {
-	HRTS3_N_MARK, HCTS3_N_MARK,
-};
-
-/* - I2C0 ------------------------------------------------------------------- */
-static const unsigned int i2c0_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
-};
-static const unsigned int i2c0_mux[] = {
-	SDA0_MARK, SCL0_MARK,
-};
-
-/* - I2C1 ------------------------------------------------------------------- */
-static const unsigned int i2c1_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
-};
-static const unsigned int i2c1_mux[] = {
-	SDA1_MARK, SCL1_MARK,
-};
-
-/* - I2C2 ------------------------------------------------------------------- */
-static const unsigned int i2c2_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
-};
-static const unsigned int i2c2_mux[] = {
-	SDA2_MARK, SCL2_MARK,
-};
-
-/* - I2C3 ------------------------------------------------------------------- */
-static const unsigned int i2c3_a_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-};
-static const unsigned int i2c3_a_mux[] = {
-	SDA3_A_MARK, SCL3_A_MARK,
-};
-static const unsigned int i2c3_b_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
-};
-static const unsigned int i2c3_b_mux[] = {
-	SDA3_B_MARK, SCL3_B_MARK,
-};
-
-/* - I2C4 ------------------------------------------------------------------- */
-static const unsigned int i2c4_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
-};
-static const unsigned int i2c4_mux[] = {
-	SDA4_MARK, SCL4_MARK,
-};
-
-/* - INTC-EX ---------------------------------------------------------------- */
-static const unsigned int intc_ex_irq0_pins[] = {
-	/* IRQ0 */
-	RCAR_GP_PIN(1, 0),
-};
-static const unsigned int intc_ex_irq0_mux[] = {
-	IRQ0_MARK,
-};
-static const unsigned int intc_ex_irq1_pins[] = {
-	/* IRQ1 */
-	RCAR_GP_PIN(0, 11),
-};
-static const unsigned int intc_ex_irq1_mux[] = {
-	IRQ1_MARK,
-};
-static const unsigned int intc_ex_irq2_pins[] = {
-	/* IRQ2 */
-	RCAR_GP_PIN(0, 12),
-};
-static const unsigned int intc_ex_irq2_mux[] = {
-	IRQ2_MARK,
-};
-static const unsigned int intc_ex_irq3_pins[] = {
-	/* IRQ3 */
-	RCAR_GP_PIN(0, 19),
-};
-static const unsigned int intc_ex_irq3_mux[] = {
-	IRQ3_MARK,
-};
-static const unsigned int intc_ex_irq4_pins[] = {
-	/* IRQ4 */
-	RCAR_GP_PIN(3, 15),
-};
-static const unsigned int intc_ex_irq4_mux[] = {
-	IRQ4_MARK,
-};
-static const unsigned int intc_ex_irq5_pins[] = {
-	/* IRQ5 */
-	RCAR_GP_PIN(3, 16),
-};
-static const unsigned int intc_ex_irq5_mux[] = {
-	IRQ5_MARK,
-};
-
-/* - MMC -------------------------------------------------------------------- */
-static const unsigned int mmc_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 6),
-};
-static const unsigned int mmc_data1_mux[] = {
-	MMC_D0_MARK,
-};
-static const unsigned int mmc_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-};
-static const unsigned int mmc_data4_mux[] = {
-	MMC_D0_MARK, MMC_D1_MARK,
-	MMC_D2_MARK, MMC_D3_MARK,
-};
-static const unsigned int mmc_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-	RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
-	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
-};
-static const unsigned int mmc_data8_mux[] = {
-	MMC_D0_MARK, MMC_D1_MARK,
-	MMC_D2_MARK, MMC_D3_MARK,
-	MMC_D4_MARK, MMC_D5_MARK,
-	MMC_D6_MARK, MMC_D7_MARK,
-};
-static const unsigned int mmc_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 5),
-};
-static const unsigned int mmc_ctrl_mux[] = {
-	MMC_CLK_MARK, MMC_CMD_MARK,
-};
-
-/* - MSIOF0 ----------------------------------------------------------------- */
-static const unsigned int msiof0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 2),
-};
-static const unsigned int msiof0_clk_mux[] = {
-	MSIOF0_SCK_MARK,
-};
-static const unsigned int msiof0_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(4, 3),
-};
-static const unsigned int msiof0_sync_mux[] = {
-	MSIOF0_SYNC_MARK,
-};
-static const unsigned int msiof0_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(4, 4),
-};
-static const unsigned int msiof0_ss1_mux[] = {
-	MSIOF0_SS1_MARK,
-};
-static const unsigned int msiof0_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(4, 5),
-};
-static const unsigned int msiof0_ss2_mux[] = {
-	MSIOF0_SS2_MARK,
-};
-static const unsigned int msiof0_txd_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(4, 1),
-};
-static const unsigned int msiof0_txd_mux[] = {
-	MSIOF0_TXD_MARK,
-};
-static const unsigned int msiof0_rxd_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(4, 0),
-};
-static const unsigned int msiof0_rxd_mux[] = {
-	MSIOF0_RXD_MARK,
-};
-
-/* - MSIOF1 ----------------------------------------------------------------- */
-static const unsigned int msiof1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 2),
-};
-static const unsigned int msiof1_clk_mux[] = {
-	MSIOF1_SCK_MARK,
-};
-static const unsigned int msiof1_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(3, 3),
-};
-static const unsigned int msiof1_sync_mux[] = {
-	MSIOF1_SYNC_MARK,
-};
-static const unsigned int msiof1_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(3, 4),
-};
-static const unsigned int msiof1_ss1_mux[] = {
-	MSIOF1_SS1_MARK,
-};
-static const unsigned int msiof1_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(3, 5),
-};
-static const unsigned int msiof1_ss2_mux[] = {
-	MSIOF1_SS2_MARK,
-};
-static const unsigned int msiof1_txd_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(3, 1),
-};
-static const unsigned int msiof1_txd_mux[] = {
-	MSIOF1_TXD_MARK,
-};
-static const unsigned int msiof1_rxd_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(3, 0),
-};
-static const unsigned int msiof1_rxd_mux[] = {
-	MSIOF1_RXD_MARK,
-};
-
-/* - MSIOF2 ----------------------------------------------------------------- */
-static const unsigned int msiof2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int msiof2_clk_mux[] = {
-	MSIOF2_SCK_MARK,
-};
-static const unsigned int msiof2_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(2, 3),
-};
-static const unsigned int msiof2_sync_mux[] = {
-	MSIOF2_SYNC_MARK,
-};
-static const unsigned int msiof2_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(2, 4),
-};
-static const unsigned int msiof2_ss1_mux[] = {
-	MSIOF2_SS1_MARK,
-};
-static const unsigned int msiof2_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(2, 5),
-};
-static const unsigned int msiof2_ss2_mux[] = {
-	MSIOF2_SS2_MARK,
-};
-static const unsigned int msiof2_txd_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(2, 2),
-};
-static const unsigned int msiof2_txd_mux[] = {
-	MSIOF2_TXD_MARK,
-};
-static const unsigned int msiof2_rxd_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(2, 1),
-};
-static const unsigned int msiof2_rxd_mux[] = {
-	MSIOF2_RXD_MARK,
-};
-
-/* - MSIOF3 ----------------------------------------------------------------- */
-static const unsigned int msiof3_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 20),
-};
-static const unsigned int msiof3_clk_mux[] = {
-	MSIOF3_SCK_MARK,
-};
-static const unsigned int msiof3_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 21),
-};
-static const unsigned int msiof3_sync_mux[] = {
-	MSIOF3_SYNC_MARK,
-};
-static const unsigned int msiof3_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 6),
-};
-static const unsigned int msiof3_ss1_mux[] = {
-	MSIOF3_SS1_MARK,
-};
-static const unsigned int msiof3_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 7),
-};
-static const unsigned int msiof3_ss2_mux[] = {
-	MSIOF3_SS2_MARK,
-};
-static const unsigned int msiof3_txd_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 5),
-};
-static const unsigned int msiof3_txd_mux[] = {
-	MSIOF3_TXD_MARK,
-};
-static const unsigned int msiof3_rxd_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 4),
-};
-static const unsigned int msiof3_rxd_mux[] = {
-	MSIOF3_RXD_MARK,
-};
-
-/* - PWM0 ------------------------------------------------------------------- */
-static const unsigned int pwm0_a_pins[] = {
-	RCAR_GP_PIN(2, 12),
-};
-static const unsigned int pwm0_a_mux[] = {
-	PWM0_A_MARK,
-};
-static const unsigned int pwm0_b_pins[] = {
-	RCAR_GP_PIN(1, 21),
-};
-static const unsigned int pwm0_b_mux[] = {
-	PWM0_B_MARK,
-};
-
-/* - PWM1 ------------------------------------------------------------------- */
-static const unsigned int pwm1_a_pins[] = {
-	RCAR_GP_PIN(2, 13),
-};
-static const unsigned int pwm1_a_mux[] = {
-	PWM1_A_MARK,
-};
-static const unsigned int pwm1_b_pins[] = {
-	RCAR_GP_PIN(1, 22),
-};
-static const unsigned int pwm1_b_mux[] = {
-	PWM1_B_MARK,
-};
-
-/* - PWM2 ------------------------------------------------------------------- */
-static const unsigned int pwm2_a_pins[] = {
-	RCAR_GP_PIN(2, 14),
-};
-static const unsigned int pwm2_a_mux[] = {
-	PWM2_A_MARK,
-};
-static const unsigned int pwm2_b_pins[] = {
-	RCAR_GP_PIN(1, 23),
-};
-static const unsigned int pwm2_b_mux[] = {
-	PWM2_B_MARK,
-};
-
-/* - PWM3 ------------------------------------------------------------------- */
-static const unsigned int pwm3_a_pins[] = {
-	RCAR_GP_PIN(2, 15),
-};
-static const unsigned int pwm3_a_mux[] = {
-	PWM3_A_MARK,
-};
-static const unsigned int pwm3_b_pins[] = {
-	RCAR_GP_PIN(1, 24),
-};
-static const unsigned int pwm3_b_mux[] = {
-	PWM3_B_MARK,
-};
-
-/* - PWM4 ------------------------------------------------------------------- */
-static const unsigned int pwm4_a_pins[] = {
-	RCAR_GP_PIN(2, 16),
-};
-static const unsigned int pwm4_a_mux[] = {
-	PWM4_A_MARK,
-};
-static const unsigned int pwm4_b_pins[] = {
-	RCAR_GP_PIN(1, 25),
-};
-static const unsigned int pwm4_b_mux[] = {
-	PWM4_B_MARK,
-};
-
-/* - QSPI0 ------------------------------------------------------------------ */
-static const unsigned int qspi0_ctrl_pins[] = {
-	/* SPCLK, SSL */
-	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
-};
-static const unsigned int qspi0_ctrl_mux[] = {
-	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
-};
-static const unsigned int qspi0_data2_pins[] = {
-	/* MOSI_IO0, MISO_IO1 */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-};
-static const unsigned int qspi0_data2_mux[] = {
-	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
-};
-static const unsigned int qspi0_data4_pins[] = {
-	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
-};
-static const unsigned int qspi0_data4_mux[] = {
-	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
-	QSPI0_IO2_MARK, QSPI0_IO3_MARK
-};
-
-/* - QSPI1 ------------------------------------------------------------------ */
-static const unsigned int qspi1_ctrl_pins[] = {
-	/* SPCLK, SSL */
-	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
-};
-static const unsigned int qspi1_ctrl_mux[] = {
-	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
-};
-static const unsigned int qspi1_data2_pins[] = {
-	/* MOSI_IO0, MISO_IO1 */
-	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
-};
-static const unsigned int qspi1_data2_mux[] = {
-	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
-};
-static const unsigned int qspi1_data4_pins[] = {
-	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
-	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
-	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
-};
-static const unsigned int qspi1_data4_mux[] = {
-	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
-	QSPI1_IO2_MARK, QSPI1_IO3_MARK
-};
-
-/* - SCIF Clock ------------------------------------------------------------- */
-static const unsigned int scif_clk_a_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(0, 18),
-};
-static const unsigned int scif_clk_a_mux[] = {
-	SCIF_CLK_A_MARK,
-};
-static const unsigned int scif_clk_b_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(1, 25),
-};
-static const unsigned int scif_clk_b_mux[] = {
-	SCIF_CLK_B_MARK,
-};
-
-/* - SCIF0 ------------------------------------------------------------------ */
-static const unsigned int scif0_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-};
-static const unsigned int scif0_data_mux[] = {
-	RX0_MARK, TX0_MARK,
-};
-static const unsigned int scif0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 1),
-};
-static const unsigned int scif0_clk_mux[] = {
-	SCK0_MARK,
-};
-static const unsigned int scif0_ctrl_pins[] = {
-	/* RTS#, CTS# */
-	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
-};
-static const unsigned int scif0_ctrl_mux[] = {
-	RTS0_N_MARK, CTS0_N_MARK,
-};
-
-/* - SCIF1 ------------------------------------------------------------------ */
-static const unsigned int scif1_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
-};
-static const unsigned int scif1_data_a_mux[] = {
-	RX1_A_MARK, TX1_A_MARK,
-};
-static const unsigned int scif1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 5),
-};
-static const unsigned int scif1_clk_mux[] = {
-	SCK1_MARK,
-};
-static const unsigned int scif1_ctrl_pins[] = {
-	/* RTS#, CTS# */
-	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
-};
-static const unsigned int scif1_ctrl_mux[] = {
-	RTS1_N_MARK, CTS1_N_MARK,
-};
-static const unsigned int scif1_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
-};
-static const unsigned int scif1_data_b_mux[] = {
-	RX1_B_MARK, TX1_B_MARK,
-};
-
-/* - SCIF3 ------------------------------------------------------------------ */
-static const unsigned int scif3_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
-};
-static const unsigned int scif3_data_mux[] = {
-	RX3_MARK, TX3_MARK,
-};
-static const unsigned int scif3_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int scif3_clk_mux[] = {
-	SCK3_MARK,
-};
-static const unsigned int scif3_ctrl_pins[] = {
-	/* RTS#, CTS# */
-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
-};
-static const unsigned int scif3_ctrl_mux[] = {
-	RTS3_N_MARK, CTS3_N_MARK,
-};
-
-/* - SCIF4 ------------------------------------------------------------------ */
-static const unsigned int scif4_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-};
-static const unsigned int scif4_data_mux[] = {
-	RX4_MARK, TX4_MARK,
-};
-static const unsigned int scif4_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 9),
-};
-static const unsigned int scif4_clk_mux[] = {
-	SCK4_MARK,
-};
-static const unsigned int scif4_ctrl_pins[] = {
-	/* RTS#, CTS# */
-	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
-};
-static const unsigned int scif4_ctrl_mux[] = {
-	RTS4_N_MARK, CTS4_N_MARK,
-};
-
-/* - TMU -------------------------------------------------------------------- */
-static const unsigned int tmu_tclk1_a_pins[] = {
-	/* TCLK1 */
-	RCAR_GP_PIN(4, 4),
-};
-static const unsigned int tmu_tclk1_a_mux[] = {
-	TCLK1_A_MARK,
-};
-static const unsigned int tmu_tclk1_b_pins[] = {
-	/* TCLK1 */
-	RCAR_GP_PIN(1, 23),
-};
-static const unsigned int tmu_tclk1_b_mux[] = {
-	TCLK1_B_MARK,
-};
-static const unsigned int tmu_tclk2_a_pins[] = {
-	/* TCLK2 */
-	RCAR_GP_PIN(4, 5),
-};
-static const unsigned int tmu_tclk2_a_mux[] = {
-	TCLK2_A_MARK,
-};
-static const unsigned int tmu_tclk2_b_pins[] = {
-	/* TCLK2 */
-	RCAR_GP_PIN(1, 24),
-};
-static const unsigned int tmu_tclk2_b_mux[] = {
-	TCLK2_B_MARK,
-};
-
-/* - VIN0 ------------------------------------------------------------------- */
-static const union vin_data12 vin0_data_pins = {
-	.data12 = {
-		RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-		RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-		RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
-		RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
-		RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
-		RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
-	},
-};
-static const union vin_data12 vin0_data_mux = {
-	.data12 = {
-		VI0_DATA0_MARK, VI0_DATA1_MARK,
-		VI0_DATA2_MARK, VI0_DATA3_MARK,
-		VI0_DATA4_MARK, VI0_DATA5_MARK,
-		VI0_DATA6_MARK, VI0_DATA7_MARK,
-		VI0_DATA8_MARK,  VI0_DATA9_MARK,
-		VI0_DATA10_MARK, VI0_DATA11_MARK,
-	},
-};
-static const unsigned int vin0_sync_pins[] = {
-	/* HSYNC#, VSYNC# */
-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-};
-static const unsigned int vin0_sync_mux[] = {
-	VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
-};
-static const unsigned int vin0_field_pins[] = {
-	/* FIELD */
-	RCAR_GP_PIN(2, 16),
-};
-static const unsigned int vin0_field_mux[] = {
-	VI0_FIELD_MARK,
-};
-static const unsigned int vin0_clkenb_pins[] = {
-	/* CLKENB */
-	RCAR_GP_PIN(2, 1),
-};
-static const unsigned int vin0_clkenb_mux[] = {
-	VI0_CLKENB_MARK,
-};
-static const unsigned int vin0_clk_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int vin0_clk_mux[] = {
-	VI0_CLK_MARK,
-};
-
-/* - VIN1 ------------------------------------------------------------------- */
-static const union vin_data12 vin1_data_pins = {
-	.data12 = {
-		RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
-		RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-		RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-		RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-		RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
-		RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
-	},
-};
-static const union vin_data12 vin1_data_mux = {
-	.data12 = {
-		VI1_DATA0_MARK, VI1_DATA1_MARK,
-		VI1_DATA2_MARK, VI1_DATA3_MARK,
-		VI1_DATA4_MARK, VI1_DATA5_MARK,
-		VI1_DATA6_MARK, VI1_DATA7_MARK,
-		VI1_DATA8_MARK,  VI1_DATA9_MARK,
-		VI1_DATA10_MARK, VI1_DATA11_MARK,
-	},
-};
-static const unsigned int vin1_sync_pins[] = {
-	/* HSYNC#, VSYNC# */
-	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
-};
-static const unsigned int vin1_sync_mux[] = {
-	VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
-};
-static const unsigned int vin1_field_pins[] = {
-	RCAR_GP_PIN(3, 16),
-};
-static const unsigned int vin1_field_mux[] = {
-	/* FIELD */
-	VI1_FIELD_MARK,
-};
-static const unsigned int vin1_clkenb_pins[] = {
-	RCAR_GP_PIN(3, 1),
-};
-static const unsigned int vin1_clkenb_mux[] = {
-	/* CLKENB */
-	VI1_CLKENB_MARK,
-};
-static const unsigned int vin1_clk_pins[] = {
-	RCAR_GP_PIN(3, 0),
-};
-static const unsigned int vin1_clk_mux[] = {
-	/* CLK */
-	VI1_CLK_MARK,
-};
-
-static const struct sh_pfc_pin_group pinmux_groups[] = {
-	SH_PFC_PIN_GROUP(avb0_link),
-	SH_PFC_PIN_GROUP(avb0_magic),
-	SH_PFC_PIN_GROUP(avb0_phy_int),
-	SH_PFC_PIN_GROUP(avb0_mdio),
-	SH_PFC_PIN_GROUP(avb0_rgmii),
-	SH_PFC_PIN_GROUP(avb0_txcrefclk),
-	SH_PFC_PIN_GROUP(avb0_avtp_pps),
-	SH_PFC_PIN_GROUP(avb0_avtp_capture),
-	SH_PFC_PIN_GROUP(avb0_avtp_match),
-	SH_PFC_PIN_GROUP(canfd_clk_a),
-	SH_PFC_PIN_GROUP(canfd_clk_b),
-	SH_PFC_PIN_GROUP(canfd0_data_a),
-	SH_PFC_PIN_GROUP(canfd0_data_b),
-	SH_PFC_PIN_GROUP(canfd1_data),
-	SH_PFC_PIN_GROUP(du_rgb666),
-	SH_PFC_PIN_GROUP(du_clk_out),
-	SH_PFC_PIN_GROUP(du_sync),
-	SH_PFC_PIN_GROUP(du_oddf),
-	SH_PFC_PIN_GROUP(du_cde),
-	SH_PFC_PIN_GROUP(du_disp),
-	SH_PFC_PIN_GROUP(hscif0_data),
-	SH_PFC_PIN_GROUP(hscif0_clk),
-	SH_PFC_PIN_GROUP(hscif0_ctrl),
-	SH_PFC_PIN_GROUP(hscif1_data),
-	SH_PFC_PIN_GROUP(hscif1_clk),
-	SH_PFC_PIN_GROUP(hscif1_ctrl),
-	SH_PFC_PIN_GROUP(hscif2_data),
-	SH_PFC_PIN_GROUP(hscif2_clk),
-	SH_PFC_PIN_GROUP(hscif2_ctrl),
-	SH_PFC_PIN_GROUP(hscif3_data),
-	SH_PFC_PIN_GROUP(hscif3_clk),
-	SH_PFC_PIN_GROUP(hscif3_ctrl),
-	SH_PFC_PIN_GROUP(i2c0),
-	SH_PFC_PIN_GROUP(i2c1),
-	SH_PFC_PIN_GROUP(i2c2),
-	SH_PFC_PIN_GROUP(i2c3_a),
-	SH_PFC_PIN_GROUP(i2c3_b),
-	SH_PFC_PIN_GROUP(i2c4),
-	SH_PFC_PIN_GROUP(intc_ex_irq0),
-	SH_PFC_PIN_GROUP(intc_ex_irq1),
-	SH_PFC_PIN_GROUP(intc_ex_irq2),
-	SH_PFC_PIN_GROUP(intc_ex_irq3),
-	SH_PFC_PIN_GROUP(intc_ex_irq4),
-	SH_PFC_PIN_GROUP(intc_ex_irq5),
-	SH_PFC_PIN_GROUP(mmc_data1),
-	SH_PFC_PIN_GROUP(mmc_data4),
-	SH_PFC_PIN_GROUP(mmc_data8),
-	SH_PFC_PIN_GROUP(mmc_ctrl),
-	SH_PFC_PIN_GROUP(msiof0_clk),
-	SH_PFC_PIN_GROUP(msiof0_sync),
-	SH_PFC_PIN_GROUP(msiof0_ss1),
-	SH_PFC_PIN_GROUP(msiof0_ss2),
-	SH_PFC_PIN_GROUP(msiof0_txd),
-	SH_PFC_PIN_GROUP(msiof0_rxd),
-	SH_PFC_PIN_GROUP(msiof1_clk),
-	SH_PFC_PIN_GROUP(msiof1_sync),
-	SH_PFC_PIN_GROUP(msiof1_ss1),
-	SH_PFC_PIN_GROUP(msiof1_ss2),
-	SH_PFC_PIN_GROUP(msiof1_txd),
-	SH_PFC_PIN_GROUP(msiof1_rxd),
-	SH_PFC_PIN_GROUP(msiof2_clk),
-	SH_PFC_PIN_GROUP(msiof2_sync),
-	SH_PFC_PIN_GROUP(msiof2_ss1),
-	SH_PFC_PIN_GROUP(msiof2_ss2),
-	SH_PFC_PIN_GROUP(msiof2_txd),
-	SH_PFC_PIN_GROUP(msiof2_rxd),
-	SH_PFC_PIN_GROUP(msiof3_clk),
-	SH_PFC_PIN_GROUP(msiof3_sync),
-	SH_PFC_PIN_GROUP(msiof3_ss1),
-	SH_PFC_PIN_GROUP(msiof3_ss2),
-	SH_PFC_PIN_GROUP(msiof3_txd),
-	SH_PFC_PIN_GROUP(msiof3_rxd),
-	SH_PFC_PIN_GROUP(pwm0_a),
-	SH_PFC_PIN_GROUP(pwm0_b),
-	SH_PFC_PIN_GROUP(pwm1_a),
-	SH_PFC_PIN_GROUP(pwm1_b),
-	SH_PFC_PIN_GROUP(pwm2_a),
-	SH_PFC_PIN_GROUP(pwm2_b),
-	SH_PFC_PIN_GROUP(pwm3_a),
-	SH_PFC_PIN_GROUP(pwm3_b),
-	SH_PFC_PIN_GROUP(pwm4_a),
-	SH_PFC_PIN_GROUP(pwm4_b),
-	SH_PFC_PIN_GROUP(qspi0_ctrl),
-	SH_PFC_PIN_GROUP(qspi0_data2),
-	SH_PFC_PIN_GROUP(qspi0_data4),
-	SH_PFC_PIN_GROUP(qspi1_ctrl),
-	SH_PFC_PIN_GROUP(qspi1_data2),
-	SH_PFC_PIN_GROUP(qspi1_data4),
-	SH_PFC_PIN_GROUP(scif_clk_a),
-	SH_PFC_PIN_GROUP(scif_clk_b),
-	SH_PFC_PIN_GROUP(scif0_data),
-	SH_PFC_PIN_GROUP(scif0_clk),
-	SH_PFC_PIN_GROUP(scif0_ctrl),
-	SH_PFC_PIN_GROUP(scif1_data_a),
-	SH_PFC_PIN_GROUP(scif1_clk),
-	SH_PFC_PIN_GROUP(scif1_ctrl),
-	SH_PFC_PIN_GROUP(scif1_data_b),
-	SH_PFC_PIN_GROUP(scif3_data),
-	SH_PFC_PIN_GROUP(scif3_clk),
-	SH_PFC_PIN_GROUP(scif3_ctrl),
-	SH_PFC_PIN_GROUP(scif4_data),
-	SH_PFC_PIN_GROUP(scif4_clk),
-	SH_PFC_PIN_GROUP(scif4_ctrl),
-	SH_PFC_PIN_GROUP(tmu_tclk1_a),
-	SH_PFC_PIN_GROUP(tmu_tclk1_b),
-	SH_PFC_PIN_GROUP(tmu_tclk2_a),
-	SH_PFC_PIN_GROUP(tmu_tclk2_b),
-	VIN_DATA_PIN_GROUP(vin0_data, 8),
-	VIN_DATA_PIN_GROUP(vin0_data, 10),
-	VIN_DATA_PIN_GROUP(vin0_data, 12),
-	SH_PFC_PIN_GROUP(vin0_sync),
-	SH_PFC_PIN_GROUP(vin0_field),
-	SH_PFC_PIN_GROUP(vin0_clkenb),
-	SH_PFC_PIN_GROUP(vin0_clk),
-	VIN_DATA_PIN_GROUP(vin1_data, 8),
-	VIN_DATA_PIN_GROUP(vin1_data, 10),
-	VIN_DATA_PIN_GROUP(vin1_data, 12),
-	SH_PFC_PIN_GROUP(vin1_sync),
-	SH_PFC_PIN_GROUP(vin1_field),
-	SH_PFC_PIN_GROUP(vin1_clkenb),
-	SH_PFC_PIN_GROUP(vin1_clk),
-};
-
-static const char * const avb0_groups[] = {
-	"avb0_link",
-	"avb0_magic",
-	"avb0_phy_int",
-	"avb0_mdio",
-	"avb0_rgmii",
-	"avb0_txcrefclk",
-	"avb0_avtp_pps",
-	"avb0_avtp_capture",
-	"avb0_avtp_match",
-};
-
-static const char * const canfd_clk_groups[] = {
-	"canfd_clk_a",
-	"canfd_clk_b",
-};
-
-static const char * const canfd0_groups[] = {
-	"canfd0_data_a",
-	"canfd0_data_b",
-};
-
-static const char * const canfd1_groups[] = {
-	"canfd1_data",
-};
-
-static const char * const du_groups[] = {
-	"du_rgb666",
-	"du_clk_out",
-	"du_sync",
-	"du_oddf",
-	"du_cde",
-	"du_disp",
-};
-
-static const char * const hscif0_groups[] = {
-	"hscif0_data",
-	"hscif0_clk",
-	"hscif0_ctrl",
-};
-
-static const char * const hscif1_groups[] = {
-	"hscif1_data",
-	"hscif1_clk",
-	"hscif1_ctrl",
-};
-
-static const char * const hscif2_groups[] = {
-	"hscif2_data",
-	"hscif2_clk",
-	"hscif2_ctrl",
-};
-
-static const char * const hscif3_groups[] = {
-	"hscif3_data",
-	"hscif3_clk",
-	"hscif3_ctrl",
-};
-
-static const char * const i2c0_groups[] = {
-	"i2c0",
-};
-
-static const char * const i2c1_groups[] = {
-	"i2c1",
-};
-
-static const char * const i2c2_groups[] = {
-	"i2c2",
-};
-
-static const char * const i2c3_groups[] = {
-	"i2c3_a",
-	"i2c3_b",
-};
-
-static const char * const i2c4_groups[] = {
-	"i2c4",
-};
-
-static const char * const intc_ex_groups[] = {
-	"intc_ex_irq0",
-	"intc_ex_irq1",
-	"intc_ex_irq2",
-	"intc_ex_irq3",
-	"intc_ex_irq4",
-	"intc_ex_irq5",
-};
-
-static const char * const mmc_groups[] = {
-	"mmc_data1",
-	"mmc_data4",
-	"mmc_data8",
-	"mmc_ctrl",
-};
-
-static const char * const msiof0_groups[] = {
-	"msiof0_clk",
-	"msiof0_sync",
-	"msiof0_ss1",
-	"msiof0_ss2",
-	"msiof0_txd",
-	"msiof0_rxd",
-};
-
-static const char * const msiof1_groups[] = {
-	"msiof1_clk",
-	"msiof1_sync",
-	"msiof1_ss1",
-	"msiof1_ss2",
-	"msiof1_txd",
-	"msiof1_rxd",
-};
-
-static const char * const msiof2_groups[] = {
-	"msiof2_clk",
-	"msiof2_sync",
-	"msiof2_ss1",
-	"msiof2_ss2",
-	"msiof2_txd",
-	"msiof2_rxd",
-};
-
-static const char * const msiof3_groups[] = {
-	"msiof3_clk",
-	"msiof3_sync",
-	"msiof3_ss1",
-	"msiof3_ss2",
-	"msiof3_txd",
-	"msiof3_rxd",
-};
-
-static const char * const pwm0_groups[] = {
-	"pwm0_a",
-	"pwm0_b",
-};
-
-static const char * const pwm1_groups[] = {
-	"pwm1_a",
-	"pwm1_b",
-};
-
-static const char * const pwm2_groups[] = {
-	"pwm2_a",
-	"pwm2_b",
-};
-
-static const char * const pwm3_groups[] = {
-	"pwm3_a",
-	"pwm3_b",
-};
-
-static const char * const pwm4_groups[] = {
-	"pwm4_a",
-	"pwm4_b",
-};
-
-static const char * const qspi0_groups[] = {
-	"qspi0_ctrl",
-	"qspi0_data2",
-	"qspi0_data4",
-};
-
-static const char * const qspi1_groups[] = {
-	"qspi1_ctrl",
-	"qspi1_data2",
-	"qspi1_data4",
-};
-
-static const char * const scif_clk_groups[] = {
-	"scif_clk_a",
-	"scif_clk_b",
-};
-
-static const char * const scif0_groups[] = {
-	"scif0_data",
-	"scif0_clk",
-	"scif0_ctrl",
-};
-
-static const char * const scif1_groups[] = {
-	"scif1_data_a",
-	"scif1_clk",
-	"scif1_ctrl",
-	"scif1_data_b",
-};
-
-static const char * const scif3_groups[] = {
-	"scif3_data",
-	"scif3_clk",
-	"scif3_ctrl",
-};
-
-static const char * const scif4_groups[] = {
-	"scif4_data",
-	"scif4_clk",
-	"scif4_ctrl",
-};
-
-static const char * const tmu_groups[] = {
-	"tmu_tclk1_a",
-	"tmu_tclk1_b",
-	"tmu_tclk2_a",
-	"tmu_tclk2_b",
-};
-
-static const char * const vin0_groups[] = {
-	"vin0_data8",
-	"vin0_data10",
-	"vin0_data12",
-	"vin0_sync",
-	"vin0_field",
-	"vin0_clkenb",
-	"vin0_clk",
-};
-
-static const char * const vin1_groups[] = {
-	"vin1_data8",
-	"vin1_data10",
-	"vin1_data12",
-	"vin1_sync",
-	"vin1_field",
-	"vin1_clkenb",
-	"vin1_clk",
-};
-
-static const struct sh_pfc_function pinmux_functions[] = {
-	SH_PFC_FUNCTION(avb0),
-	SH_PFC_FUNCTION(canfd_clk),
-	SH_PFC_FUNCTION(canfd0),
-	SH_PFC_FUNCTION(canfd1),
-	SH_PFC_FUNCTION(du),
-	SH_PFC_FUNCTION(hscif0),
-	SH_PFC_FUNCTION(hscif1),
-	SH_PFC_FUNCTION(hscif2),
-	SH_PFC_FUNCTION(hscif3),
-	SH_PFC_FUNCTION(i2c0),
-	SH_PFC_FUNCTION(i2c1),
-	SH_PFC_FUNCTION(i2c2),
-	SH_PFC_FUNCTION(i2c3),
-	SH_PFC_FUNCTION(i2c4),
-	SH_PFC_FUNCTION(intc_ex),
-	SH_PFC_FUNCTION(mmc),
-	SH_PFC_FUNCTION(msiof0),
-	SH_PFC_FUNCTION(msiof1),
-	SH_PFC_FUNCTION(msiof2),
-	SH_PFC_FUNCTION(msiof3),
-	SH_PFC_FUNCTION(pwm0),
-	SH_PFC_FUNCTION(pwm1),
-	SH_PFC_FUNCTION(pwm2),
-	SH_PFC_FUNCTION(pwm3),
-	SH_PFC_FUNCTION(pwm4),
-	SH_PFC_FUNCTION(qspi0),
-	SH_PFC_FUNCTION(qspi1),
-	SH_PFC_FUNCTION(scif_clk),
-	SH_PFC_FUNCTION(scif0),
-	SH_PFC_FUNCTION(scif1),
-	SH_PFC_FUNCTION(scif3),
-	SH_PFC_FUNCTION(scif4),
-	SH_PFC_FUNCTION(tmu),
-	SH_PFC_FUNCTION(vin0),
-	SH_PFC_FUNCTION(vin1),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-#define F_(x, y)	FN_##y
-#define FM(x)		FN_##x
-	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_0_21_FN,	GPSR0_21,
-		GP_0_20_FN,	GPSR0_20,
-		GP_0_19_FN,	GPSR0_19,
-		GP_0_18_FN,	GPSR0_18,
-		GP_0_17_FN,	GPSR0_17,
-		GP_0_16_FN,	GPSR0_16,
-		GP_0_15_FN,	GPSR0_15,
-		GP_0_14_FN,	GPSR0_14,
-		GP_0_13_FN,	GPSR0_13,
-		GP_0_12_FN,	GPSR0_12,
-		GP_0_11_FN,	GPSR0_11,
-		GP_0_10_FN,	GPSR0_10,
-		GP_0_9_FN,	GPSR0_9,
-		GP_0_8_FN,	GPSR0_8,
-		GP_0_7_FN,	GPSR0_7,
-		GP_0_6_FN,	GPSR0_6,
-		GP_0_5_FN,	GPSR0_5,
-		GP_0_4_FN,	GPSR0_4,
-		GP_0_3_FN,	GPSR0_3,
-		GP_0_2_FN,	GPSR0_2,
-		GP_0_1_FN,	GPSR0_1,
-		GP_0_0_FN,	GPSR0_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_1_27_FN,	GPSR1_27,
-		GP_1_26_FN,	GPSR1_26,
-		GP_1_25_FN,	GPSR1_25,
-		GP_1_24_FN,	GPSR1_24,
-		GP_1_23_FN,	GPSR1_23,
-		GP_1_22_FN,	GPSR1_22,
-		GP_1_21_FN,	GPSR1_21,
-		GP_1_20_FN,	GPSR1_20,
-		GP_1_19_FN,	GPSR1_19,
-		GP_1_18_FN,	GPSR1_18,
-		GP_1_17_FN,	GPSR1_17,
-		GP_1_16_FN,	GPSR1_16,
-		GP_1_15_FN,	GPSR1_15,
-		GP_1_14_FN,	GPSR1_14,
-		GP_1_13_FN,	GPSR1_13,
-		GP_1_12_FN,	GPSR1_12,
-		GP_1_11_FN,	GPSR1_11,
-		GP_1_10_FN,	GPSR1_10,
-		GP_1_9_FN,	GPSR1_9,
-		GP_1_8_FN,	GPSR1_8,
-		GP_1_7_FN,	GPSR1_7,
-		GP_1_6_FN,	GPSR1_6,
-		GP_1_5_FN,	GPSR1_5,
-		GP_1_4_FN,	GPSR1_4,
-		GP_1_3_FN,	GPSR1_3,
-		GP_1_2_FN,	GPSR1_2,
-		GP_1_1_FN,	GPSR1_1,
-		GP_1_0_FN,	GPSR1_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_2_16_FN,	GPSR2_16,
-		GP_2_15_FN,	GPSR2_15,
-		GP_2_14_FN,	GPSR2_14,
-		GP_2_13_FN,	GPSR2_13,
-		GP_2_12_FN,	GPSR2_12,
-		GP_2_11_FN,	GPSR2_11,
-		GP_2_10_FN,	GPSR2_10,
-		GP_2_9_FN,	GPSR2_9,
-		GP_2_8_FN,	GPSR2_8,
-		GP_2_7_FN,	GPSR2_7,
-		GP_2_6_FN,	GPSR2_6,
-		GP_2_5_FN,	GPSR2_5,
-		GP_2_4_FN,	GPSR2_4,
-		GP_2_3_FN,	GPSR2_3,
-		GP_2_2_FN,	GPSR2_2,
-		GP_2_1_FN,	GPSR2_1,
-		GP_2_0_FN,	GPSR2_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_3_16_FN,	GPSR3_16,
-		GP_3_15_FN,	GPSR3_15,
-		GP_3_14_FN,	GPSR3_14,
-		GP_3_13_FN,	GPSR3_13,
-		GP_3_12_FN,	GPSR3_12,
-		GP_3_11_FN,	GPSR3_11,
-		GP_3_10_FN,	GPSR3_10,
-		GP_3_9_FN,	GPSR3_9,
-		GP_3_8_FN,	GPSR3_8,
-		GP_3_7_FN,	GPSR3_7,
-		GP_3_6_FN,	GPSR3_6,
-		GP_3_5_FN,	GPSR3_5,
-		GP_3_4_FN,	GPSR3_4,
-		GP_3_3_FN,	GPSR3_3,
-		GP_3_2_FN,	GPSR3_2,
-		GP_3_1_FN,	GPSR3_1,
-		GP_3_0_FN,	GPSR3_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_4_5_FN,	GPSR4_5,
-		GP_4_4_FN,	GPSR4_4,
-		GP_4_3_FN,	GPSR4_3,
-		GP_4_2_FN,	GPSR4_2,
-		GP_4_1_FN,	GPSR4_1,
-		GP_4_0_FN,	GPSR4_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_5_14_FN,	GPSR5_14,
-		GP_5_13_FN,	GPSR5_13,
-		GP_5_12_FN,	GPSR5_12,
-		GP_5_11_FN,	GPSR5_11,
-		GP_5_10_FN,	GPSR5_10,
-		GP_5_9_FN,	GPSR5_9,
-		GP_5_8_FN,	GPSR5_8,
-		GP_5_7_FN,	GPSR5_7,
-		GP_5_6_FN,	GPSR5_6,
-		GP_5_5_FN,	GPSR5_5,
-		GP_5_4_FN,	GPSR5_4,
-		GP_5_3_FN,	GPSR5_3,
-		GP_5_2_FN,	GPSR5_2,
-		GP_5_1_FN,	GPSR5_1,
-		GP_5_0_FN,	GPSR5_0, ))
-	},
-#undef F_
-#undef FM
-
-#define F_(x, y)	x,
-#define FM(x)		FN_##x,
-	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
-		IP0_31_28
-		IP0_27_24
-		IP0_23_20
-		IP0_19_16
-		IP0_15_12
-		IP0_11_8
-		IP0_7_4
-		IP0_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
-		IP1_31_28
-		IP1_27_24
-		IP1_23_20
-		IP1_19_16
-		IP1_15_12
-		IP1_11_8
-		IP1_7_4
-		IP1_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
-		IP2_31_28
-		IP2_27_24
-		IP2_23_20
-		IP2_19_16
-		IP2_15_12
-		IP2_11_8
-		IP2_7_4
-		IP2_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
-		IP3_31_28
-		IP3_27_24
-		IP3_23_20
-		IP3_19_16
-		IP3_15_12
-		IP3_11_8
-		IP3_7_4
-		IP3_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
-		IP4_31_28
-		IP4_27_24
-		IP4_23_20
-		IP4_19_16
-		IP4_15_12
-		IP4_11_8
-		IP4_7_4
-		IP4_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
-		IP5_31_28
-		IP5_27_24
-		IP5_23_20
-		IP5_19_16
-		IP5_15_12
-		IP5_11_8
-		IP5_7_4
-		IP5_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
-		IP6_31_28
-		IP6_27_24
-		IP6_23_20
-		IP6_19_16
-		IP6_15_12
-		IP6_11_8
-		IP6_7_4
-		IP6_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
-		IP7_31_28
-		IP7_27_24
-		IP7_23_20
-		IP7_19_16
-		IP7_15_12
-		IP7_11_8
-		IP7_7_4
-		IP7_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
-		IP8_31_28
-		IP8_27_24
-		IP8_23_20
-		IP8_19_16
-		IP8_15_12
-		IP8_11_8
-		IP8_7_4
-		IP8_3_0 ))
-	},
-#undef F_
-#undef FM
-
-#define F_(x, y)	x,
-#define FM(x)		FN_##x,
-	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
-			     GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
-				   1, 1, 1, 1, 1),
-			     GROUP(
-		/* RESERVED 31, 30, 29, 28 */
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 27, 26, 25, 24 */
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 23, 22, 21, 20 */
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 19, 18, 17, 16 */
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 15, 14, 13, 12 */
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		MOD_SEL0_11
-		MOD_SEL0_10
-		MOD_SEL0_9
-		MOD_SEL0_8
-		MOD_SEL0_7
-		MOD_SEL0_6
-		MOD_SEL0_5
-		MOD_SEL0_4
-		MOD_SEL0_3
-		MOD_SEL0_2
-		MOD_SEL0_1
-		MOD_SEL0_0 ))
-	},
-	{ },
-};
-
-enum ioctrl_regs {
-	POCCTRL0,
-	POCCTRL1,
-	POCCTRL2,
-	TDSELCTRL,
-};
-
-static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
-	[POCCTRL0] = { 0xe6060380 },
-	[POCCTRL1] = { 0xe6060384 },
-	[POCCTRL2] = { 0xe6060388 },
-	[TDSELCTRL] = { 0xe60603c0, },
-	{ /* sentinel */ },
-};
-
-static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
-				   u32 *pocctrl)
-{
-	int bit = pin & 0x1f;
-
-	*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
-	if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
-		return bit;
-	if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
-		return bit + 22;
-
-	*pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
-	if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
-		return bit - 10;
-	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
-		return bit + 7;
-
-	return -EINVAL;
-}
-
-static const struct sh_pfc_soc_operations pinmux_ops = {
-	.pin_to_pocctrl = r8a77970_pin_to_pocctrl,
-};
-
-const struct sh_pfc_soc_info r8a77970_pinmux_info = {
-	.name = "r8a77970_pfc",
-	.ops = &pinmux_ops,
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups,
-	.nr_groups = ARRAY_SIZE(pinmux_groups),
-	.functions = pinmux_functions,
-	.nr_functions = ARRAY_SIZE(pinmux_functions),
-
-	.cfg_regs = pinmux_config_regs,
-	.ioctrl_regs = pinmux_ioctrl_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
deleted file mode 100644
index 14fe4032a52d..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
+++ /dev/null
@@ -1,2896 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * R8A77980 processor support - PFC hardware block.
- *
- * Copyright (C) 2018 Renesas Electronics Corp.
- * Copyright (C) 2018 Cogent Embedded, Inc.
- *
- * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
- *
- * R-Car Gen3 processor support - PFC hardware block.
- *
- * Copyright (C) 2015 Renesas Electronics Corporation
- */
-
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-
-#include "core.h"
-#include "sh_pfc.h"
-
-#define CPU_ALL_GP(fn, sfx)	\
-	PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_28(1, fn, sfx),	\
-	PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
-	PORT_GP_25(4, fn, sfx),	\
-	PORT_GP_15(5, fn, sfx)
-
-/*
- * F_() : just information
- * FM() : macro for FN_xxx / xxx_MARK
- */
-
-/* GPSR0 */
-#define GPSR0_21	F_(DU_EXODDF_DU_ODDF_DISP_CDE,	IP2_23_20)
-#define GPSR0_20	F_(DU_EXVSYNC_DU_VSYNC,		IP2_19_16)
-#define GPSR0_19	F_(DU_EXHSYNC_DU_HSYNC,		IP2_15_12)
-#define GPSR0_18	F_(DU_DOTCLKOUT,		IP2_11_8)
-#define GPSR0_17	F_(DU_DB7,			IP2_7_4)
-#define GPSR0_16	F_(DU_DB6,			IP2_3_0)
-#define GPSR0_15	F_(DU_DB5,			IP1_31_28)
-#define GPSR0_14	F_(DU_DB4,			IP1_27_24)
-#define GPSR0_13	F_(DU_DB3,			IP1_23_20)
-#define GPSR0_12	F_(DU_DB2,			IP1_19_16)
-#define GPSR0_11	F_(DU_DG7,			IP1_15_12)
-#define GPSR0_10	F_(DU_DG6,			IP1_11_8)
-#define GPSR0_9		F_(DU_DG5,			IP1_7_4)
-#define GPSR0_8		F_(DU_DG4,			IP1_3_0)
-#define GPSR0_7		F_(DU_DG3,			IP0_31_28)
-#define GPSR0_6		F_(DU_DG2,			IP0_27_24)
-#define GPSR0_5		F_(DU_DR7,			IP0_23_20)
-#define GPSR0_4		F_(DU_DR6,			IP0_19_16)
-#define GPSR0_3		F_(DU_DR5,			IP0_15_12)
-#define GPSR0_2		F_(DU_DR4,			IP0_11_8)
-#define GPSR0_1		F_(DU_DR3,			IP0_7_4)
-#define GPSR0_0		F_(DU_DR2,			IP0_3_0)
-
-/* GPSR1 */
-#define GPSR1_27	F_(DIGRF_CLKOUT,	IP8_31_28)
-#define GPSR1_26	F_(DIGRF_CLKIN,		IP8_27_24)
-#define GPSR1_25	F_(CANFD_CLK_A,		IP8_23_20)
-#define GPSR1_24	F_(CANFD1_RX,		IP8_19_16)
-#define GPSR1_23	F_(CANFD1_TX,		IP8_15_12)
-#define GPSR1_22	F_(CANFD0_RX_A,		IP8_11_8)
-#define GPSR1_21	F_(CANFD0_TX_A,		IP8_7_4)
-#define GPSR1_20	F_(AVB_AVTP_CAPTURE,	IP8_3_0)
-#define GPSR1_19	F_(AVB_AVTP_MATCH,	IP7_31_28)
-#define GPSR1_18	FM(AVB_LINK)
-#define GPSR1_17	FM(AVB_PHY_INT)
-#define GPSR1_16	FM(AVB_MAGIC)
-#define GPSR1_15	FM(AVB_MDC)
-#define GPSR1_14	FM(AVB_MDIO)
-#define GPSR1_13	FM(AVB_TXCREFCLK)
-#define GPSR1_12	FM(AVB_TD3)
-#define GPSR1_11	FM(AVB_TD2)
-#define GPSR1_10	FM(AVB_TD1)
-#define GPSR1_9		FM(AVB_TD0)
-#define GPSR1_8		FM(AVB_TXC)
-#define GPSR1_7		FM(AVB_TX_CTL)
-#define GPSR1_6		FM(AVB_RD3)
-#define GPSR1_5		FM(AVB_RD2)
-#define GPSR1_4		FM(AVB_RD1)
-#define GPSR1_3		FM(AVB_RD0)
-#define GPSR1_2		FM(AVB_RXC)
-#define GPSR1_1		FM(AVB_RX_CTL)
-#define GPSR1_0		F_(IRQ0,		IP2_27_24)
-
-/* GPSR2 */
-#define GPSR2_29	F_(FSO_TOE_N,  		IP10_19_16)
-#define GPSR2_28	F_(FSO_CFE_1_N,		IP10_15_12)
-#define GPSR2_27	F_(FSO_CFE_0_N,		IP10_11_8)
-#define GPSR2_26	F_(SDA3,		IP10_7_4)
-#define GPSR2_25	F_(SCL3,		IP10_3_0)
-#define GPSR2_24	F_(MSIOF0_SS2,		IP9_31_28)
-#define GPSR2_23	F_(MSIOF0_SS1,		IP9_27_24)
-#define GPSR2_22	F_(MSIOF0_SYNC,		IP9_23_20)
-#define GPSR2_21	F_(MSIOF0_SCK,		IP9_19_16)
-#define GPSR2_20	F_(MSIOF0_TXD,		IP9_15_12)
-#define GPSR2_19	F_(MSIOF0_RXD,		IP9_11_8)
-#define GPSR2_18	F_(IRQ5,		IP9_7_4)
-#define GPSR2_17	F_(IRQ4,		IP9_3_0)
-#define GPSR2_16	F_(VI0_FIELD,		IP4_31_28)
-#define GPSR2_15	F_(VI0_DATA11,		IP4_27_24)
-#define GPSR2_14	F_(VI0_DATA10,		IP4_23_20)
-#define GPSR2_13	F_(VI0_DATA9,		IP4_19_16)
-#define GPSR2_12	F_(VI0_DATA8,		IP4_15_12)
-#define GPSR2_11	F_(VI0_DATA7,		IP4_11_8)
-#define GPSR2_10	F_(VI0_DATA6,		IP4_7_4)
-#define GPSR2_9		F_(VI0_DATA5,		IP4_3_0)
-#define GPSR2_8		F_(VI0_DATA4,		IP3_31_28)
-#define GPSR2_7		F_(VI0_DATA3,		IP3_27_24)
-#define GPSR2_6		F_(VI0_DATA2,		IP3_23_20)
-#define GPSR2_5		F_(VI0_DATA1,		IP3_19_16)
-#define GPSR2_4		F_(VI0_DATA0,		IP3_15_12)
-#define GPSR2_3		F_(VI0_VSYNC_N,		IP3_11_8)
-#define GPSR2_2		F_(VI0_HSYNC_N,		IP3_7_4)
-#define GPSR2_1		F_(VI0_CLKENB,		IP3_3_0)
-#define GPSR2_0		F_(VI0_CLK,		IP2_31_28)
-
-/* GPSR3 */
-#define GPSR3_16	F_(VI1_FIELD,		IP7_3_0)
-#define GPSR3_15	F_(VI1_DATA11,		IP6_31_28)
-#define GPSR3_14	F_(VI1_DATA10,		IP6_27_24)
-#define GPSR3_13	F_(VI1_DATA9,		IP6_23_20)
-#define GPSR3_12	F_(VI1_DATA8,		IP6_19_16)
-#define GPSR3_11	F_(VI1_DATA7,		IP6_15_12)
-#define GPSR3_10	F_(VI1_DATA6,		IP6_11_8)
-#define GPSR3_9		F_(VI1_DATA5,		IP6_7_4)
-#define GPSR3_8		F_(VI1_DATA4,		IP6_3_0)
-#define GPSR3_7		F_(VI1_DATA3,		IP5_31_28)
-#define GPSR3_6		F_(VI1_DATA2,		IP5_27_24)
-#define GPSR3_5		F_(VI1_DATA1,		IP5_23_20)
-#define GPSR3_4		F_(VI1_DATA0,		IP5_19_16)
-#define GPSR3_3		F_(VI1_VSYNC_N,		IP5_15_12)
-#define GPSR3_2		F_(VI1_HSYNC_N,		IP5_11_8)
-#define GPSR3_1		F_(VI1_CLKENB,		IP5_7_4)
-#define GPSR3_0		F_(VI1_CLK,		IP5_3_0)
-
-/* GPSR4 */
-#define GPSR4_24	FM(GETHER_LINK_A)
-#define GPSR4_23	FM(GETHER_PHY_INT_A)
-#define GPSR4_22	FM(GETHER_MAGIC)
-#define GPSR4_21	FM(GETHER_MDC_A)
-#define GPSR4_20	FM(GETHER_MDIO_A)
-#define GPSR4_19	FM(GETHER_TXCREFCLK_MEGA)
-#define GPSR4_18	FM(GETHER_TXCREFCLK)
-#define GPSR4_17	FM(GETHER_TD3)
-#define GPSR4_16	FM(GETHER_TD2)
-#define GPSR4_15	FM(GETHER_TD1)
-#define GPSR4_14	FM(GETHER_TD0)
-#define GPSR4_13	FM(GETHER_TXC)
-#define GPSR4_12	FM(GETHER_TX_CTL)
-#define GPSR4_11	FM(GETHER_RD3)
-#define GPSR4_10	FM(GETHER_RD2)
-#define GPSR4_9		FM(GETHER_RD1)
-#define GPSR4_8		FM(GETHER_RD0)
-#define GPSR4_7		FM(GETHER_RXC)
-#define GPSR4_6		FM(GETHER_RX_CTL)
-#define GPSR4_5		F_(SDA2,		IP7_27_24)
-#define GPSR4_4		F_(SCL2,		IP7_23_20)
-#define GPSR4_3		F_(SDA1,		IP7_19_16)
-#define GPSR4_2		F_(SCL1,		IP7_15_12)
-#define GPSR4_1		F_(SDA0,		IP7_11_8)
-#define GPSR4_0		F_(SCL0,		IP7_7_4)
-
-/* GPSR5 */
-#define GPSR5_14	FM(RPC_INT_N)
-#define GPSR5_13	FM(RPC_WP_N)
-#define GPSR5_12	FM(RPC_RESET_N)
-#define GPSR5_11	FM(QSPI1_SSL)
-#define GPSR5_10	FM(QSPI1_IO3)
-#define GPSR5_9		FM(QSPI1_IO2)
-#define GPSR5_8		FM(QSPI1_MISO_IO1)
-#define GPSR5_7		FM(QSPI1_MOSI_IO0)
-#define GPSR5_6		FM(QSPI1_SPCLK)
-#define GPSR5_5		FM(QSPI0_SSL)
-#define GPSR5_4		FM(QSPI0_IO3)
-#define GPSR5_3		FM(QSPI0_IO2)
-#define GPSR5_2		FM(QSPI0_MISO_IO1)
-#define GPSR5_1		FM(QSPI0_MOSI_IO0)
-#define GPSR5_0		FM(QSPI0_SPCLK)
-
-
-/* IPSRx */		/* 0 */				/* 1 */			/* 2 */			/* 3 */		/* 4 */		/* 5 */		/* 6 - F */
-#define IP0_3_0		FM(DU_DR2)			FM(SCK4)		FM(GETHER_RMII_CRS_DV)	FM(A0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_7_4		FM(DU_DR3)			FM(RX4)			FM(GETHER_RMII_RX_ER)	FM(A1)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_11_8	FM(DU_DR4)			FM(TX4)			FM(GETHER_RMII_RXD0)	FM(A2)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_15_12	FM(DU_DR5)			FM(CTS4_N)		FM(GETHER_RMII_RXD1)	FM(A3)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_19_16	FM(DU_DR6)			FM(RTS4_N)		FM(GETHER_RMII_TXD_EN)	FM(A4)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_23_20	FM(DU_DR7)			F_(0, 0)		FM(GETHER_RMII_TXD0)	FM(A5)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_27_24	FM(DU_DG2)			F_(0, 0)		FM(GETHER_RMII_TXD1)	FM(A6)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_31_28	FM(DU_DG3)			FM(CPG_CPCKOUT)		FM(GETHER_RMII_REFCLK)	FM(A7)		FM(PWMFSW0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_3_0		FM(DU_DG4)			FM(SCL5)		F_(0, 0)		FM(A8)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_7_4		FM(DU_DG5)			FM(SDA5)		FM(GETHER_MDC_B)	FM(A9)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_11_8	FM(DU_DG6)			FM(SCIF_CLK_A)		FM(GETHER_MDIO_B)	FM(A10)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_15_12	FM(DU_DG7)			FM(HRX0_A)		F_(0, 0)		FM(A11)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_19_16	FM(DU_DB2)			FM(HSCK0_A)		F_(0, 0)		FM(A12)		FM(IRQ1)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_23_20	FM(DU_DB3)			FM(HRTS0_N_A)		F_(0, 0)		FM(A13)		FM(IRQ2)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_27_24	FM(DU_DB4)			FM(HCTS0_N_A)		F_(0, 0)		FM(A14)		FM(IRQ3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_31_28	FM(DU_DB5)			FM(HTX0_A)		FM(PWM0_A)		FM(A15)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_3_0		FM(DU_DB6)			FM(MSIOF3_RXD)		F_(0, 0)		FM(A16)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_7_4		FM(DU_DB7)			FM(MSIOF3_TXD)		F_(0, 0)		FM(A17)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_11_8	FM(DU_DOTCLKOUT)		FM(MSIOF3_SS1)		FM(GETHER_LINK_B)	FM(A18)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_15_12	FM(DU_EXHSYNC_DU_HSYNC)		FM(MSIOF3_SS2)		FM(GETHER_PHY_INT_B)	FM(A19)		FM(FXR_TXENA_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_19_16	FM(DU_EXVSYNC_DU_VSYNC)		FM(MSIOF3_SCK)		F_(0, 0)		F_(0, 0)	FM(FXR_TXENB_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_23_20	FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(MSIOF3_SYNC)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_27_24	FM(IRQ0)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_31_28	FM(VI0_CLK)			FM(MSIOF2_SCK)		FM(SCK3)		F_(0, 0)	FM(HSCK3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_3_0		FM(VI0_CLKENB)			FM(MSIOF2_RXD)		FM(RX3)			FM(RD_WR_N)	FM(HCTS3_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_7_4		FM(VI0_HSYNC_N)			FM(MSIOF2_TXD)		FM(TX3)			F_(0, 0)	FM(HRTS3_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_11_8	FM(VI0_VSYNC_N)			FM(MSIOF2_SYNC)		FM(CTS3_N)		F_(0, 0)	FM(HTX3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_15_12	FM(VI0_DATA0)			FM(MSIOF2_SS1)		FM(RTS3_N)		F_(0, 0)	FM(HRX3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_19_16	FM(VI0_DATA1)			FM(MSIOF2_SS2)		FM(SCK1)		F_(0, 0)	FM(SPEEDIN_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_23_20	FM(VI0_DATA2)			FM(AVB_AVTP_PPS)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_27_24	FM(VI0_DATA3)			FM(HSCK1)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_31_28	FM(VI0_DATA4)			FM(HRTS1_N)		FM(RX1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_3_0		FM(VI0_DATA5)			FM(HCTS1_N)		FM(TX1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_7_4		FM(VI0_DATA6)			FM(HTX1)		FM(CTS1_N)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_11_8	FM(VI0_DATA7)			FM(HRX1)		FM(RTS1_N)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_15_12	FM(VI0_DATA8)			FM(HSCK2)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_19_16	FM(VI0_DATA9)			FM(HCTS2_N)		FM(PWM1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_23_20	FM(VI0_DATA10)			FM(HRTS2_N)		FM(PWM2_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_27_24	FM(VI0_DATA11)			FM(HTX2)		FM(PWM3_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_31_28	FM(VI0_FIELD)			FM(HRX2)		FM(PWM4_A)		FM(CS1_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_3_0		FM(VI1_CLK)			FM(MSIOF1_RXD)		F_(0, 0)		FM(CS0_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_7_4		FM(VI1_CLKENB)			FM(MSIOF1_TXD)		F_(0, 0)		FM(D0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_11_8	FM(VI1_HSYNC_N)			FM(MSIOF1_SCK)		F_(0, 0)		FM(D1)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_15_12	FM(VI1_VSYNC_N)			FM(MSIOF1_SYNC)		F_(0, 0)		FM(D2)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_19_16	FM(VI1_DATA0)			FM(MSIOF1_SS1)		F_(0, 0)		FM(D3)		FM(MMC_WP)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_23_20	FM(VI1_DATA1)			FM(MSIOF1_SS2)		F_(0, 0)		FM(D4)		FM(MMC_CD)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_27_24	FM(VI1_DATA2)			FM(CANFD0_TX_B)		F_(0, 0)		FM(D5)		FM(MMC_DS)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_31_28	FM(VI1_DATA3)			FM(CANFD0_RX_B)		F_(0, 0)		FM(D6)		FM(MMC_CMD)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_3_0		FM(VI1_DATA4)			FM(CANFD_CLK_B)		F_(0, 0)		FM(D7)		FM(MMC_D0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_7_4		FM(VI1_DATA5)			F_(0, 0)		F_(0, 0)		FM(D8)		FM(MMC_D1)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_11_8	FM(VI1_DATA6)			F_(0, 0)		F_(0, 0)		FM(D9)		FM(MMC_D2)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_15_12	FM(VI1_DATA7)			F_(0, 0)		F_(0, 0)		FM(D10)		FM(MMC_D3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_19_16	FM(VI1_DATA8)			F_(0, 0)		F_(0, 0)		FM(D11)		FM(MMC_CLK)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_23_20	FM(VI1_DATA9)			FM(TCLK1_A)		F_(0, 0)		FM(D12)		FM(MMC_D4)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_27_24	FM(VI1_DATA10)			FM(TCLK2_A)		F_(0, 0)		FM(D13)		FM(MMC_D5)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_31_28	FM(VI1_DATA11)			FM(SCL4)		F_(0, 0)		FM(D14)		FM(MMC_D6)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_3_0		FM(VI1_FIELD)			FM(SDA4)		F_(0, 0)		FM(D15)		FM(MMC_D7)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_7_4		FM(SCL0)			F_(0, 0)		F_(0, 0)		FM(CLKOUT)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_11_8	FM(SDA0)			F_(0, 0)		F_(0, 0)		FM(BS_N)	FM(SCK0)	FM(HSCK0_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_15_12	FM(SCL1)			F_(0, 0)		FM(TPU0TO2)		FM(RD_N)	FM(CTS0_N)	FM(HCTS0_N_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_19_16	FM(SDA1)			F_(0, 0)		FM(TPU0TO3)		FM(WE0_N)	FM(RTS0_N)	FM(HRTS0_N_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_23_20	FM(SCL2)			F_(0, 0)		F_(0, 0)		FM(WE1_N)	FM(RX0)		FM(HRX0_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_27_24	FM(SDA2)			F_(0, 0)		F_(0, 0)		FM(EX_WAIT0)	FM(TX0)		FM(HTX0_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_31_28	FM(AVB_AVTP_MATCH)		FM(TPU0TO0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_3_0		FM(AVB_AVTP_CAPTURE)		FM(TPU0TO1)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_7_4		FM(CANFD0_TX_A)			FM(FXR_TXDA)		FM(PWM0_B)		FM(DU_DISP)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_11_8	FM(CANFD0_RX_A)			FM(RXDA_EXTFXR)		FM(PWM1_B)		FM(DU_CDE)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_15_12	FM(CANFD1_TX)			FM(FXR_TXDB)		FM(PWM2_B)		FM(TCLK1_B)	FM(TX1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_19_16	FM(CANFD1_RX)			FM(RXDB_EXTFXR)		FM(PWM3_B)		FM(TCLK2_B)	FM(RX1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_23_20	FM(CANFD_CLK_A) 		FM(CLK_EXTFXR)		FM(PWM4_B)		FM(SPEEDIN_B)	FM(SCIF_CLK_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_27_24	FM(DIGRF_CLKIN)			FM(DIGRF_CLKEN_IN)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_31_28	FM(DIGRF_CLKOUT)		FM(DIGRF_CLKEN_OUT)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_3_0		FM(IRQ4)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA12)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_7_4 	FM(IRQ5)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA13)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_11_8	FM(MSIOF0_RXD)			FM(DU_DR0)		F_(0, 0)		FM(VI0_DATA14)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_15_12	FM(MSIOF0_TXD)			FM(DU_DR1)		F_(0, 0)		FM(VI0_DATA15)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_19_16	FM(MSIOF0_SCK)			FM(DU_DG0)		F_(0, 0)		FM(VI0_DATA16)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_23_20	FM(MSIOF0_SYNC)			FM(DU_DG1)		F_(0, 0)		FM(VI0_DATA17)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_27_24	FM(MSIOF0_SS1)			FM(DU_DB0)		FM(TCLK3)		FM(VI0_DATA18)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_31_28	FM(MSIOF0_SS2)			FM(DU_DB1)		FM(TCLK4)		FM(VI0_DATA19)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_3_0	FM(SCL3)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA20)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_7_4	FM(SDA3)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA21)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_11_8	FM(FSO_CFE_0_N)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA22)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_15_12	FM(FSO_CFE_1_N)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA23)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_19_16	FM(FSO_TOE_N)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_23_20	F_(0, 0)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_27_24	F_(0, 0)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_31_28	F_(0, 0)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-#define PINMUX_GPSR	\
-\
-				GPSR2_29 \
-				GPSR2_28 \
-		GPSR1_27	GPSR2_27 \
-		GPSR1_26	GPSR2_26 \
-		GPSR1_25	GPSR2_25 \
-		GPSR1_24	GPSR2_24			GPSR4_24 \
-		GPSR1_23	GPSR2_23			GPSR4_23 \
-		GPSR1_22	GPSR2_22			GPSR4_22 \
-GPSR0_21	GPSR1_21	GPSR2_21			GPSR4_21 \
-GPSR0_20	GPSR1_20	GPSR2_20			GPSR4_20 \
-GPSR0_19	GPSR1_19	GPSR2_19			GPSR4_19 \
-GPSR0_18	GPSR1_18	GPSR2_18			GPSR4_18 \
-GPSR0_17	GPSR1_17	GPSR2_17			GPSR4_17 \
-GPSR0_16	GPSR1_16	GPSR2_16	GPSR3_16	GPSR4_16 \
-GPSR0_15	GPSR1_15	GPSR2_15	GPSR3_15	GPSR4_15 \
-GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14	GPSR4_14	GPSR5_14 \
-GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13	GPSR4_13	GPSR5_13 \
-GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12	GPSR4_12	GPSR5_12 \
-GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11	GPSR4_11	GPSR5_11 \
-GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10 \
-GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9 \
-GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8 \
-GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7 \
-GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6 \
-GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5 \
-GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4 \
-GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3 \
-GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2 \
-GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1 \
-GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0
-
-#define PINMUX_IPSR	\
-\
-FM(IP0_3_0)	IP0_3_0		FM(IP1_3_0)	IP1_3_0		FM(IP2_3_0)	IP2_3_0		FM(IP3_3_0)	IP3_3_0 \
-FM(IP0_7_4)	IP0_7_4		FM(IP1_7_4)	IP1_7_4		FM(IP2_7_4)	IP2_7_4		FM(IP3_7_4)	IP3_7_4 \
-FM(IP0_11_8)	IP0_11_8	FM(IP1_11_8)	IP1_11_8	FM(IP2_11_8)	IP2_11_8	FM(IP3_11_8)	IP3_11_8 \
-FM(IP0_15_12)	IP0_15_12	FM(IP1_15_12)	IP1_15_12	FM(IP2_15_12)	IP2_15_12	FM(IP3_15_12)	IP3_15_12 \
-FM(IP0_19_16)	IP0_19_16	FM(IP1_19_16)	IP1_19_16	FM(IP2_19_16)	IP2_19_16	FM(IP3_19_16)	IP3_19_16 \
-FM(IP0_23_20)	IP0_23_20	FM(IP1_23_20)	IP1_23_20	FM(IP2_23_20)	IP2_23_20	FM(IP3_23_20)	IP3_23_20 \
-FM(IP0_27_24)	IP0_27_24	FM(IP1_27_24)	IP1_27_24	FM(IP2_27_24)	IP2_27_24	FM(IP3_27_24)	IP3_27_24 \
-FM(IP0_31_28)	IP0_31_28	FM(IP1_31_28)	IP1_31_28	FM(IP2_31_28)	IP2_31_28	FM(IP3_31_28)	IP3_31_28 \
-\
-FM(IP4_3_0)	IP4_3_0		FM(IP5_3_0)	IP5_3_0		FM(IP6_3_0)	IP6_3_0		FM(IP7_3_0)	IP7_3_0 \
-FM(IP4_7_4)	IP4_7_4		FM(IP5_7_4)	IP5_7_4		FM(IP6_7_4)	IP6_7_4		FM(IP7_7_4)	IP7_7_4 \
-FM(IP4_11_8)	IP4_11_8	FM(IP5_11_8)	IP5_11_8	FM(IP6_11_8)	IP6_11_8	FM(IP7_11_8)	IP7_11_8 \
-FM(IP4_15_12)	IP4_15_12	FM(IP5_15_12)	IP5_15_12	FM(IP6_15_12)	IP6_15_12	FM(IP7_15_12)	IP7_15_12 \
-FM(IP4_19_16)	IP4_19_16	FM(IP5_19_16)	IP5_19_16	FM(IP6_19_16)	IP6_19_16	FM(IP7_19_16)	IP7_19_16 \
-FM(IP4_23_20)	IP4_23_20	FM(IP5_23_20)	IP5_23_20	FM(IP6_23_20)	IP6_23_20	FM(IP7_23_20)	IP7_23_20 \
-FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
-FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
-\
-FM(IP8_3_0)	IP8_3_0		FM(IP9_3_0)	IP9_3_0		FM(IP10_3_0)	IP10_3_0 \
-FM(IP8_7_4)	IP8_7_4		FM(IP9_7_4)	IP9_7_4		FM(IP10_7_4)	IP10_7_4 \
-FM(IP8_11_8)	IP8_11_8	FM(IP9_11_8)	IP9_11_8	FM(IP10_11_8)	IP10_11_8 \
-FM(IP8_15_12)	IP8_15_12	FM(IP9_15_12)	IP9_15_12	FM(IP10_15_12)	IP10_15_12 \
-FM(IP8_19_16)	IP8_19_16	FM(IP9_19_16)	IP9_19_16	FM(IP10_19_16)	IP10_19_16 \
-FM(IP8_23_20)	IP8_23_20	FM(IP9_23_20)	IP9_23_20	FM(IP10_23_20)	IP10_23_20 \
-FM(IP8_27_24)	IP8_27_24	FM(IP9_27_24)	IP9_27_24	FM(IP10_27_24)	IP10_27_24 \
-FM(IP8_31_28)	IP8_31_28	FM(IP9_31_28)	IP9_31_28	FM(IP10_31_28)	IP10_31_28
-
-/* MOD_SEL0 */		/* 0 */			/* 1 */
-#define MOD_SEL0_11	FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
-#define MOD_SEL0_10	FM(SEL_GETHER_0)	FM(SEL_GETHER_1)
-#define MOD_SEL0_9	FM(SEL_HSCIF0_0)	FM(SEL_HSCIF0_1)
-#define MOD_SEL0_8	FM(SEL_PWM0_0)		FM(SEL_PWM0_1)
-#define MOD_SEL0_7	FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
-#define MOD_SEL0_6	FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
-#define MOD_SEL0_5	FM(SEL_PWM3_0)		FM(SEL_PWM3_1)
-#define MOD_SEL0_4	FM(SEL_PWM4_0)		FM(SEL_PWM4_1)
-#define MOD_SEL0_2	FM(SEL_RSP_0)		FM(SEL_RSP_1)
-#define MOD_SEL0_1	FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
-#define MOD_SEL0_0	FM(SEL_TMU_0)		FM(SEL_TMU_1)
-
-#define PINMUX_MOD_SELS \
-\
-MOD_SEL0_11 \
-MOD_SEL0_10 \
-MOD_SEL0_9 \
-MOD_SEL0_8 \
-MOD_SEL0_7 \
-MOD_SEL0_6 \
-MOD_SEL0_5 \
-MOD_SEL0_4 \
-MOD_SEL0_2 \
-MOD_SEL0_1 \
-MOD_SEL0_0
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	GP_ALL(DATA),
-	PINMUX_DATA_END,
-
-#define F_(x, y)
-#define FM(x)   FN_##x,
-	PINMUX_FUNCTION_BEGIN,
-	GP_ALL(FN),
-	PINMUX_GPSR
-	PINMUX_IPSR
-	PINMUX_MOD_SELS
-	PINMUX_FUNCTION_END,
-#undef F_
-#undef FM
-
-#define F_(x, y)
-#define FM(x)	x##_MARK,
-	PINMUX_MARK_BEGIN,
-	PINMUX_GPSR
-	PINMUX_IPSR
-	PINMUX_MOD_SELS
-	PINMUX_MARK_END,
-#undef F_
-#undef FM
-};
-
-static const u16 pinmux_data[] = {
-	PINMUX_DATA_GP_ALL(),
-
-	PINMUX_SINGLE(AVB_RX_CTL),
-	PINMUX_SINGLE(AVB_RXC),
-	PINMUX_SINGLE(AVB_RD0),
-	PINMUX_SINGLE(AVB_RD1),
-	PINMUX_SINGLE(AVB_RD2),
-	PINMUX_SINGLE(AVB_RD3),
-	PINMUX_SINGLE(AVB_TX_CTL),
-	PINMUX_SINGLE(AVB_TXC),
-	PINMUX_SINGLE(AVB_TD0),
-	PINMUX_SINGLE(AVB_TD1),
-	PINMUX_SINGLE(AVB_TD2),
-	PINMUX_SINGLE(AVB_TD3),
-	PINMUX_SINGLE(AVB_TXCREFCLK),
-	PINMUX_SINGLE(AVB_MDIO),
-	PINMUX_SINGLE(AVB_MDC),
-	PINMUX_SINGLE(AVB_MAGIC),
-	PINMUX_SINGLE(AVB_PHY_INT),
-	PINMUX_SINGLE(AVB_LINK),
-
-	PINMUX_SINGLE(GETHER_RX_CTL),
-	PINMUX_SINGLE(GETHER_RXC),
-	PINMUX_SINGLE(GETHER_RD0),
-	PINMUX_SINGLE(GETHER_RD1),
-	PINMUX_SINGLE(GETHER_RD2),
-	PINMUX_SINGLE(GETHER_RD3),
-	PINMUX_SINGLE(GETHER_TX_CTL),
-	PINMUX_SINGLE(GETHER_TXC),
-	PINMUX_SINGLE(GETHER_TD0),
-	PINMUX_SINGLE(GETHER_TD1),
-	PINMUX_SINGLE(GETHER_TD2),
-	PINMUX_SINGLE(GETHER_TD3),
-	PINMUX_SINGLE(GETHER_TXCREFCLK),
-	PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA),
-	PINMUX_SINGLE(GETHER_MDIO_A),
-	PINMUX_SINGLE(GETHER_MDC_A),
-	PINMUX_SINGLE(GETHER_MAGIC),
-	PINMUX_SINGLE(GETHER_PHY_INT_A),
-	PINMUX_SINGLE(GETHER_LINK_A),
-
-	PINMUX_SINGLE(QSPI0_SPCLK),
-	PINMUX_SINGLE(QSPI0_MOSI_IO0),
-	PINMUX_SINGLE(QSPI0_MISO_IO1),
-	PINMUX_SINGLE(QSPI0_IO2),
-	PINMUX_SINGLE(QSPI0_IO3),
-	PINMUX_SINGLE(QSPI0_SSL),
-	PINMUX_SINGLE(QSPI1_SPCLK),
-	PINMUX_SINGLE(QSPI1_MOSI_IO0),
-	PINMUX_SINGLE(QSPI1_MISO_IO1),
-	PINMUX_SINGLE(QSPI1_IO2),
-	PINMUX_SINGLE(QSPI1_IO3),
-	PINMUX_SINGLE(QSPI1_SSL),
-	PINMUX_SINGLE(RPC_RESET_N),
-	PINMUX_SINGLE(RPC_WP_N),
-	PINMUX_SINGLE(RPC_INT_N),
-
-	/* IPSR0 */
-	PINMUX_IPSR_GPSR(IP0_3_0,	DU_DR2),
-	PINMUX_IPSR_GPSR(IP0_3_0,	SCK4),
-	PINMUX_IPSR_GPSR(IP0_3_0,	GETHER_RMII_CRS_DV),
-	PINMUX_IPSR_GPSR(IP0_3_0,	A0),
-
-	PINMUX_IPSR_GPSR(IP0_7_4,	DU_DR3),
-	PINMUX_IPSR_GPSR(IP0_7_4,	RX4),
-	PINMUX_IPSR_GPSR(IP0_7_4,	GETHER_RMII_RX_ER),
-	PINMUX_IPSR_GPSR(IP0_7_4,	A1),
-
-	PINMUX_IPSR_GPSR(IP0_11_8,	DU_DR4),
-	PINMUX_IPSR_GPSR(IP0_11_8,	TX4),
-	PINMUX_IPSR_GPSR(IP0_11_8,	GETHER_RMII_RXD0),
-	PINMUX_IPSR_GPSR(IP0_11_8,	A2),
-
-	PINMUX_IPSR_GPSR(IP0_15_12,	DU_DR5),
-	PINMUX_IPSR_GPSR(IP0_15_12,	CTS4_N),
-	PINMUX_IPSR_GPSR(IP0_15_12,	GETHER_RMII_RXD1),
-	PINMUX_IPSR_GPSR(IP0_15_12,	A3),
-
-	PINMUX_IPSR_GPSR(IP0_19_16,	DU_DR6),
-	PINMUX_IPSR_GPSR(IP0_19_16,	RTS4_N),
-	PINMUX_IPSR_GPSR(IP0_19_16,	GETHER_RMII_TXD_EN),
-	PINMUX_IPSR_GPSR(IP0_19_16,	A4),
-
-	PINMUX_IPSR_GPSR(IP0_23_20,	DU_DR7),
-	PINMUX_IPSR_GPSR(IP0_23_20,	GETHER_RMII_TXD0),
-	PINMUX_IPSR_GPSR(IP0_23_20,	A5),
-
-	PINMUX_IPSR_GPSR(IP0_27_24,	DU_DG2),
-	PINMUX_IPSR_GPSR(IP0_27_24,	GETHER_RMII_TXD1),
-	PINMUX_IPSR_GPSR(IP0_27_24,	A6),
-
-	PINMUX_IPSR_GPSR(IP0_31_28,	DU_DG3),
-	PINMUX_IPSR_GPSR(IP0_31_28,	CPG_CPCKOUT),
-	PINMUX_IPSR_GPSR(IP0_31_28,	GETHER_RMII_REFCLK),
-	PINMUX_IPSR_GPSR(IP0_31_28,	A7),
-	PINMUX_IPSR_GPSR(IP0_31_28,	PWMFSW0),
-
-	/* IPSR1 */
-	PINMUX_IPSR_GPSR(IP1_3_0,	DU_DG4),
-	PINMUX_IPSR_GPSR(IP1_3_0,	SCL5),
-	PINMUX_IPSR_GPSR(IP1_3_0,	A8),
-
-	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DG5),
-	PINMUX_IPSR_GPSR(IP1_7_4,	SDA5),
-	PINMUX_IPSR_MSEL(IP1_7_4,	GETHER_MDC_B, SEL_GETHER_1),
-	PINMUX_IPSR_GPSR(IP1_7_4,	A9),
-
-	PINMUX_IPSR_GPSR(IP1_11_8,	DU_DG6),
-	PINMUX_IPSR_MSEL(IP1_11_8,	SCIF_CLK_A, SEL_HSCIF0_0),
-	PINMUX_IPSR_MSEL(IP1_11_8,	GETHER_MDIO_B, SEL_GETHER_1),
-	PINMUX_IPSR_GPSR(IP1_11_8,	A10),
-
-	PINMUX_IPSR_GPSR(IP1_15_12,	DU_DG7),
-	PINMUX_IPSR_MSEL(IP1_15_12,	HRX0_A, SEL_HSCIF0_0),
-	PINMUX_IPSR_GPSR(IP1_15_12,	A11),
-
-	PINMUX_IPSR_GPSR(IP1_19_16,	DU_DB2),
-	PINMUX_IPSR_MSEL(IP1_19_16,	HSCK0_A, SEL_HSCIF0_0),
-	PINMUX_IPSR_GPSR(IP1_19_16,	A12),
-	PINMUX_IPSR_GPSR(IP1_19_16,	IRQ1),
-
-	PINMUX_IPSR_GPSR(IP1_23_20,	DU_DB3),
-	PINMUX_IPSR_MSEL(IP1_23_20,	HRTS0_N_A, SEL_HSCIF0_0),
-	PINMUX_IPSR_GPSR(IP1_23_20,	A13),
-	PINMUX_IPSR_GPSR(IP1_23_20,	IRQ2),
-
-	PINMUX_IPSR_GPSR(IP1_27_24,	DU_DB4),
-	PINMUX_IPSR_MSEL(IP1_27_24,	HCTS0_N_A, SEL_HSCIF0_0),
-	PINMUX_IPSR_GPSR(IP1_27_24,	A14),
-	PINMUX_IPSR_GPSR(IP1_27_24,	IRQ3),
-
-	PINMUX_IPSR_GPSR(IP1_31_28,	DU_DB5),
-	PINMUX_IPSR_MSEL(IP1_31_28,	HTX0_A, SEL_HSCIF0_0),
-	PINMUX_IPSR_MSEL(IP1_31_28,	PWM0_A, SEL_PWM0_0),
-	PINMUX_IPSR_GPSR(IP1_31_28,	A15),
-
-	/* IPSR2 */
-	PINMUX_IPSR_GPSR(IP2_3_0,	DU_DB6),
-	PINMUX_IPSR_GPSR(IP2_3_0,	MSIOF3_RXD),
-	PINMUX_IPSR_GPSR(IP2_3_0,	A16),
-
-	PINMUX_IPSR_GPSR(IP2_7_4,	DU_DB7),
-	PINMUX_IPSR_GPSR(IP2_7_4,	MSIOF3_TXD),
-	PINMUX_IPSR_GPSR(IP2_7_4,	A17),
-
-	PINMUX_IPSR_GPSR(IP2_11_8,	DU_DOTCLKOUT),
-	PINMUX_IPSR_GPSR(IP2_11_8,	MSIOF3_SS1),
-	PINMUX_IPSR_MSEL(IP2_11_8,	GETHER_LINK_B, SEL_GETHER_1),
-	PINMUX_IPSR_GPSR(IP2_11_8,	A18),
-
-	PINMUX_IPSR_GPSR(IP2_15_12,	DU_EXHSYNC_DU_HSYNC),
-	PINMUX_IPSR_GPSR(IP2_15_12,	MSIOF3_SS2),
-	PINMUX_IPSR_MSEL(IP2_15_12,	GETHER_PHY_INT_B, SEL_GETHER_1),
-	PINMUX_IPSR_GPSR(IP2_15_12,	A19),
-	PINMUX_IPSR_GPSR(IP2_15_12,	FXR_TXENA_N),
-
-	PINMUX_IPSR_GPSR(IP2_19_16,	DU_EXVSYNC_DU_VSYNC),
-	PINMUX_IPSR_GPSR(IP2_19_16,	MSIOF3_SCK),
-	PINMUX_IPSR_GPSR(IP2_19_16,	FXR_TXENB_N),
-
-	PINMUX_IPSR_GPSR(IP2_23_20,	DU_EXODDF_DU_ODDF_DISP_CDE),
-	PINMUX_IPSR_GPSR(IP2_23_20,	MSIOF3_SYNC),
-
-	PINMUX_IPSR_GPSR(IP2_27_24,	IRQ0),
-
-	PINMUX_IPSR_GPSR(IP2_31_28,	VI0_CLK),
-	PINMUX_IPSR_GPSR(IP2_31_28,	MSIOF2_SCK),
-	PINMUX_IPSR_GPSR(IP2_31_28,	SCK3),
-	PINMUX_IPSR_GPSR(IP2_31_28,	HSCK3),
-
-	/* IPSR3 */
-	PINMUX_IPSR_GPSR(IP3_3_0,	VI0_CLKENB),
-	PINMUX_IPSR_GPSR(IP3_3_0,	MSIOF2_RXD),
-	PINMUX_IPSR_GPSR(IP3_3_0,	RX3),
-	PINMUX_IPSR_GPSR(IP3_3_0,	RD_WR_N),
-	PINMUX_IPSR_GPSR(IP3_3_0,	HCTS3_N),
-
-	PINMUX_IPSR_GPSR(IP3_7_4,	VI0_HSYNC_N),
-	PINMUX_IPSR_GPSR(IP3_7_4,	MSIOF2_TXD),
-	PINMUX_IPSR_GPSR(IP3_7_4,	TX3),
-	PINMUX_IPSR_GPSR(IP3_7_4,	HRTS3_N),
-
-	PINMUX_IPSR_GPSR(IP3_11_8,	VI0_VSYNC_N),
-	PINMUX_IPSR_GPSR(IP3_11_8,	MSIOF2_SYNC),
-	PINMUX_IPSR_GPSR(IP3_11_8,	CTS3_N),
-	PINMUX_IPSR_GPSR(IP3_11_8,	HTX3),
-
-	PINMUX_IPSR_GPSR(IP3_15_12,	VI0_DATA0),
-	PINMUX_IPSR_GPSR(IP3_15_12,	MSIOF2_SS1),
-	PINMUX_IPSR_GPSR(IP3_15_12,	RTS3_N),
-	PINMUX_IPSR_GPSR(IP3_15_12,	HRX3),
-
-	PINMUX_IPSR_GPSR(IP3_19_16,	VI0_DATA1),
-	PINMUX_IPSR_GPSR(IP3_19_16,	MSIOF2_SS2),
-	PINMUX_IPSR_GPSR(IP3_19_16,	SCK1),
-	PINMUX_IPSR_MSEL(IP3_19_16,	SPEEDIN_A, SEL_RSP_0),
-
-	PINMUX_IPSR_GPSR(IP3_23_20,	VI0_DATA2),
-	PINMUX_IPSR_GPSR(IP3_23_20,	AVB_AVTP_PPS),
-
-	PINMUX_IPSR_GPSR(IP3_27_24,	VI0_DATA3),
-	PINMUX_IPSR_GPSR(IP3_27_24,	HSCK1),
-
-	PINMUX_IPSR_GPSR(IP3_31_28,	VI0_DATA4),
-	PINMUX_IPSR_GPSR(IP3_31_28,	HRTS1_N),
-	PINMUX_IPSR_MSEL(IP3_31_28,	RX1_A, SEL_SCIF1_0),
-
-	/* IPSR4 */
-	PINMUX_IPSR_GPSR(IP4_3_0,	VI0_DATA5),
-	PINMUX_IPSR_GPSR(IP4_3_0,	HCTS1_N),
-	PINMUX_IPSR_MSEL(IP4_3_0,	TX1_A, SEL_SCIF1_0),
-
-	PINMUX_IPSR_GPSR(IP4_7_4,	VI0_DATA6),
-	PINMUX_IPSR_GPSR(IP4_7_4,	HTX1),
-	PINMUX_IPSR_GPSR(IP4_7_4,	CTS1_N),
-
-	PINMUX_IPSR_GPSR(IP4_11_8,	VI0_DATA7),
-	PINMUX_IPSR_GPSR(IP4_11_8,	HRX1),
-	PINMUX_IPSR_GPSR(IP4_11_8,	RTS1_N),
-
-	PINMUX_IPSR_GPSR(IP4_15_12,	VI0_DATA8),
-	PINMUX_IPSR_GPSR(IP4_15_12,	HSCK2),
-
-	PINMUX_IPSR_GPSR(IP4_19_16,	VI0_DATA9),
-	PINMUX_IPSR_GPSR(IP4_19_16,	HCTS2_N),
-	PINMUX_IPSR_MSEL(IP4_19_16,	PWM1_A, SEL_PWM1_0),
-
-	PINMUX_IPSR_GPSR(IP4_23_20,	VI0_DATA10),
-	PINMUX_IPSR_GPSR(IP4_23_20,	HRTS2_N),
-	PINMUX_IPSR_MSEL(IP4_23_20,	PWM2_A, SEL_PWM2_0),
-
-	PINMUX_IPSR_GPSR(IP4_27_24,	VI0_DATA11),
-	PINMUX_IPSR_GPSR(IP4_27_24,	HTX2),
-	PINMUX_IPSR_MSEL(IP4_27_24,	PWM3_A, SEL_PWM3_0),
-
-	PINMUX_IPSR_GPSR(IP4_31_28,	VI0_FIELD),
-	PINMUX_IPSR_GPSR(IP4_31_28,	HRX2),
-	PINMUX_IPSR_MSEL(IP4_31_28,	PWM4_A, SEL_PWM4_0),
-	PINMUX_IPSR_GPSR(IP4_31_28,	CS1_N),
-
-	/* IPSR5 */
-	PINMUX_IPSR_GPSR(IP5_3_0,	VI1_CLK),
-	PINMUX_IPSR_GPSR(IP5_3_0,	MSIOF1_RXD),
-	PINMUX_IPSR_GPSR(IP5_3_0,	CS0_N),
-
-	PINMUX_IPSR_GPSR(IP5_7_4,	VI1_CLKENB),
-	PINMUX_IPSR_GPSR(IP5_7_4,	MSIOF1_TXD),
-	PINMUX_IPSR_GPSR(IP5_7_4,	D0),
-
-	PINMUX_IPSR_GPSR(IP5_11_8,	VI1_HSYNC_N),
-	PINMUX_IPSR_GPSR(IP5_11_8,	MSIOF1_SCK),
-	PINMUX_IPSR_GPSR(IP5_11_8,	D1),
-
-	PINMUX_IPSR_GPSR(IP5_15_12,	VI1_VSYNC_N),
-	PINMUX_IPSR_GPSR(IP5_15_12,	MSIOF1_SYNC),
-	PINMUX_IPSR_GPSR(IP5_15_12,	D2),
-
-	PINMUX_IPSR_GPSR(IP5_19_16,	VI1_DATA0),
-	PINMUX_IPSR_GPSR(IP5_19_16,	MSIOF1_SS1),
-	PINMUX_IPSR_GPSR(IP5_19_16,	D3),
-	PINMUX_IPSR_GPSR(IP5_19_16,	MMC_WP),
-
-	PINMUX_IPSR_GPSR(IP5_23_20,	VI1_DATA1),
-	PINMUX_IPSR_GPSR(IP5_23_20,	MSIOF1_SS2),
-	PINMUX_IPSR_GPSR(IP5_23_20,	D4),
-	PINMUX_IPSR_GPSR(IP5_23_20,	MMC_CD),
-
-	PINMUX_IPSR_GPSR(IP5_27_24,	VI1_DATA2),
-	PINMUX_IPSR_MSEL(IP5_27_24,	CANFD0_TX_B, SEL_CANFD0_1),
-	PINMUX_IPSR_GPSR(IP5_27_24,	D5),
-	PINMUX_IPSR_GPSR(IP5_27_24,	MMC_DS),
-
-	PINMUX_IPSR_GPSR(IP5_31_28,	VI1_DATA3),
-	PINMUX_IPSR_MSEL(IP5_31_28,	CANFD0_RX_B, SEL_CANFD0_1),
-	PINMUX_IPSR_GPSR(IP5_31_28,	D6),
-	PINMUX_IPSR_GPSR(IP5_31_28,	MMC_CMD),
-
-	/* IPSR6 */
-	PINMUX_IPSR_GPSR(IP6_3_0,	VI1_DATA4),
-	PINMUX_IPSR_MSEL(IP6_3_0,	CANFD_CLK_B, SEL_CANFD0_1),
-	PINMUX_IPSR_GPSR(IP6_3_0,	D7),
-	PINMUX_IPSR_GPSR(IP6_3_0,	MMC_D0),
-
-	PINMUX_IPSR_GPSR(IP6_7_4,	VI1_DATA5),
-	PINMUX_IPSR_GPSR(IP6_7_4,	D8),
-	PINMUX_IPSR_GPSR(IP6_7_4,	MMC_D1),
-
-	PINMUX_IPSR_GPSR(IP6_11_8,	VI1_DATA6),
-	PINMUX_IPSR_GPSR(IP6_11_8,	D9),
-	PINMUX_IPSR_GPSR(IP6_11_8,	MMC_D2),
-
-	PINMUX_IPSR_GPSR(IP6_15_12,	VI1_DATA7),
-	PINMUX_IPSR_GPSR(IP6_15_12,	D10),
-	PINMUX_IPSR_GPSR(IP6_15_12,	MMC_D3),
-
-	PINMUX_IPSR_GPSR(IP6_19_16,	VI1_DATA8),
-	PINMUX_IPSR_GPSR(IP6_19_16,	D11),
-	PINMUX_IPSR_GPSR(IP6_19_16,	MMC_CLK),
-
-	PINMUX_IPSR_GPSR(IP6_23_20,	VI1_DATA9),
-	PINMUX_IPSR_MSEL(IP6_23_20,	TCLK1_A, SEL_TMU_0),
-	PINMUX_IPSR_GPSR(IP6_23_20,	D12),
-	PINMUX_IPSR_GPSR(IP6_23_20,	MMC_D4),
-
-	PINMUX_IPSR_GPSR(IP6_27_24,	VI1_DATA10),
-	PINMUX_IPSR_MSEL(IP6_27_24,	TCLK2_A, SEL_TMU_0),
-	PINMUX_IPSR_GPSR(IP6_27_24,	D13),
-	PINMUX_IPSR_GPSR(IP6_27_24,	MMC_D5),
-
-	PINMUX_IPSR_GPSR(IP6_31_28,	VI1_DATA11),
-	PINMUX_IPSR_GPSR(IP6_31_28,	SCL4),
-	PINMUX_IPSR_GPSR(IP6_31_28,	D14),
-	PINMUX_IPSR_GPSR(IP6_31_28,	MMC_D6),
-
-	/* IPSR7 */
-	PINMUX_IPSR_GPSR(IP7_3_0,	VI1_FIELD),
-	PINMUX_IPSR_GPSR(IP7_3_0,	SDA4),
-	PINMUX_IPSR_GPSR(IP7_3_0,	D15),
-	PINMUX_IPSR_GPSR(IP7_3_0,	MMC_D7),
-
-	PINMUX_IPSR_GPSR(IP7_7_4,	SCL0),
-	PINMUX_IPSR_GPSR(IP7_7_4,	CLKOUT),
-
-	PINMUX_IPSR_GPSR(IP7_11_8,	SDA0),
-	PINMUX_IPSR_GPSR(IP7_11_8,	BS_N),
-	PINMUX_IPSR_GPSR(IP7_11_8,	SCK0),
-	PINMUX_IPSR_MSEL(IP7_11_8,	HSCK0_B, SEL_HSCIF0_1),
-
-	PINMUX_IPSR_GPSR(IP7_15_12,	SCL1),
-	PINMUX_IPSR_GPSR(IP7_15_12,	TPU0TO2),
-	PINMUX_IPSR_GPSR(IP7_15_12,	RD_N),
-	PINMUX_IPSR_GPSR(IP7_15_12,	CTS0_N),
-	PINMUX_IPSR_GPSR(IP7_15_12,	HCTS0_N_B),
-
-	PINMUX_IPSR_GPSR(IP7_19_16,	SDA1),
-	PINMUX_IPSR_GPSR(IP7_19_16,	TPU0TO3),
-	PINMUX_IPSR_GPSR(IP7_19_16,	WE0_N),
-	PINMUX_IPSR_GPSR(IP7_19_16,	RTS0_N),
-	PINMUX_IPSR_MSEL(IP1_23_20,	HRTS0_N_B, SEL_HSCIF0_1),
-
-	PINMUX_IPSR_GPSR(IP7_23_20,	SCL2),
-	PINMUX_IPSR_GPSR(IP7_23_20,	WE1_N),
-	PINMUX_IPSR_GPSR(IP7_23_20,	RX0),
-	PINMUX_IPSR_MSEL(IP7_23_20,	HRX0_B, SEL_HSCIF0_1),
-
-	PINMUX_IPSR_GPSR(IP7_27_24,	SDA2),
-	PINMUX_IPSR_GPSR(IP7_27_24,	EX_WAIT0),
-	PINMUX_IPSR_GPSR(IP7_27_24,	TX0),
-	PINMUX_IPSR_MSEL(IP7_27_24,	HTX0_B, SEL_HSCIF0_1),
-
-	PINMUX_IPSR_GPSR(IP7_31_28,	AVB_AVTP_MATCH),
-	PINMUX_IPSR_GPSR(IP7_31_28,	TPU0TO0),
-
-	/* IPSR8 */
-	PINMUX_IPSR_GPSR(IP8_3_0,	AVB_AVTP_CAPTURE),
-	PINMUX_IPSR_GPSR(IP8_3_0,	TPU0TO1),
-
-	PINMUX_IPSR_MSEL(IP8_7_4,	CANFD0_TX_A, SEL_CANFD0_0),
-	PINMUX_IPSR_GPSR(IP8_7_4,	FXR_TXDA),
-	PINMUX_IPSR_MSEL(IP8_7_4,	PWM0_B, SEL_PWM0_1),
-	PINMUX_IPSR_GPSR(IP8_7_4,	DU_DISP),
-
-	PINMUX_IPSR_MSEL(IP8_11_8,	CANFD0_RX_A, SEL_CANFD0_0),
-	PINMUX_IPSR_GPSR(IP8_11_8,	RXDA_EXTFXR),
-	PINMUX_IPSR_MSEL(IP8_11_8,	PWM1_B, SEL_PWM1_1),
-	PINMUX_IPSR_GPSR(IP8_11_8,	DU_CDE),
-
-	PINMUX_IPSR_GPSR(IP8_15_12,	CANFD1_TX),
-	PINMUX_IPSR_GPSR(IP8_15_12,	FXR_TXDB),
-	PINMUX_IPSR_MSEL(IP8_15_12,	PWM2_B, SEL_PWM2_1),
-	PINMUX_IPSR_MSEL(IP8_15_12,	TCLK1_B, SEL_TMU_1),
-	PINMUX_IPSR_MSEL(IP8_15_12,	TX1_B, SEL_SCIF1_1),
-
-	PINMUX_IPSR_GPSR(IP8_19_16,	CANFD1_RX),
-	PINMUX_IPSR_GPSR(IP8_19_16,	RXDB_EXTFXR),
-	PINMUX_IPSR_MSEL(IP8_19_16,	PWM3_B, SEL_PWM3_1),
-	PINMUX_IPSR_MSEL(IP8_19_16,	TCLK2_B, SEL_TMU_1),
-	PINMUX_IPSR_MSEL(IP8_19_16,	RX1_B, SEL_SCIF1_1),
-
-	PINMUX_IPSR_MSEL(IP8_23_20,	CANFD_CLK_A, SEL_CANFD0_0),
-	PINMUX_IPSR_GPSR(IP8_23_20,	CLK_EXTFXR),
-	PINMUX_IPSR_MSEL(IP8_23_20,	PWM4_B, SEL_PWM4_1),
-	PINMUX_IPSR_MSEL(IP8_23_20,	SPEEDIN_B, SEL_RSP_1),
-	PINMUX_IPSR_MSEL(IP8_23_20,	SCIF_CLK_B, SEL_HSCIF0_1),
-
-	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKIN),
-	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKEN_IN),
-
-	PINMUX_IPSR_GPSR(IP8_31_28,	DIGRF_CLKOUT),
-	PINMUX_IPSR_GPSR(IP8_31_28,	DIGRF_CLKEN_OUT),
-
-	/* IPSR9 */
-	PINMUX_IPSR_GPSR(IP9_3_0,	IRQ4),
-	PINMUX_IPSR_GPSR(IP9_3_0,	VI0_DATA12),
-
-	PINMUX_IPSR_GPSR(IP9_7_4,	IRQ5),
-	PINMUX_IPSR_GPSR(IP9_7_4,	VI0_DATA13),
-
-	PINMUX_IPSR_GPSR(IP9_11_8,	MSIOF0_RXD),
-	PINMUX_IPSR_GPSR(IP9_11_8,	DU_DR0),
-	PINMUX_IPSR_GPSR(IP9_11_8,	VI0_DATA14),
-
-	PINMUX_IPSR_GPSR(IP9_15_12,	MSIOF0_TXD),
-	PINMUX_IPSR_GPSR(IP9_15_12,	DU_DR1),
-	PINMUX_IPSR_GPSR(IP9_15_12,	VI0_DATA15),
-
-	PINMUX_IPSR_GPSR(IP9_19_16,	MSIOF0_SCK),
-	PINMUX_IPSR_GPSR(IP9_19_16,	DU_DG0),
-	PINMUX_IPSR_GPSR(IP9_19_16,	VI0_DATA16),
-
-	PINMUX_IPSR_GPSR(IP9_23_20,	MSIOF0_SYNC),
-	PINMUX_IPSR_GPSR(IP9_23_20,	DU_DG1),
-	PINMUX_IPSR_GPSR(IP9_23_20,	VI0_DATA17),
-
-	PINMUX_IPSR_GPSR(IP9_27_24,	MSIOF0_SS1),
-	PINMUX_IPSR_GPSR(IP9_27_24,	DU_DB0),
-	PINMUX_IPSR_GPSR(IP9_27_24,	TCLK3),
-	PINMUX_IPSR_GPSR(IP9_27_24,	VI0_DATA18),
-
-	PINMUX_IPSR_GPSR(IP9_31_28,	MSIOF0_SS2),
-	PINMUX_IPSR_GPSR(IP9_31_28,	DU_DB1),
-	PINMUX_IPSR_GPSR(IP9_31_28,	TCLK4),
-	PINMUX_IPSR_GPSR(IP9_31_28,	VI0_DATA19),
-
-	/* IPSR10 */
-	PINMUX_IPSR_GPSR(IP10_3_0,	SCL3),
-	PINMUX_IPSR_GPSR(IP10_3_0,	VI0_DATA20),
-
-	PINMUX_IPSR_GPSR(IP10_7_4,	SDA3),
-	PINMUX_IPSR_GPSR(IP10_7_4,	VI0_DATA21),
-
-	PINMUX_IPSR_GPSR(IP10_11_8,	FSO_CFE_0_N),
-	PINMUX_IPSR_GPSR(IP10_11_8,	VI0_DATA22),
-
-	PINMUX_IPSR_GPSR(IP10_15_12,	FSO_CFE_1_N),
-	PINMUX_IPSR_GPSR(IP10_15_12,	VI0_DATA23),
-
-	PINMUX_IPSR_GPSR(IP10_19_16,	FSO_TOE_N),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	PINMUX_GPIO_GP_ALL(),
-};
-
-/* - AVB -------------------------------------------------------------------- */
-static const unsigned int avb_link_pins[] = {
-	/* AVB_LINK */
-	RCAR_GP_PIN(1, 18),
-};
-static const unsigned int avb_link_mux[] = {
-	AVB_LINK_MARK,
-};
-static const unsigned int avb_magic_pins[] = {
-	/* AVB_MAGIC */
-	RCAR_GP_PIN(1, 16),
-};
-static const unsigned int avb_magic_mux[] = {
-	AVB_MAGIC_MARK,
-};
-static const unsigned int avb_phy_int_pins[] = {
-	/* AVB_PHY_INT */
-	RCAR_GP_PIN(1, 17),
-};
-static const unsigned int avb_phy_int_mux[] = {
-	AVB_PHY_INT_MARK,
-};
-static const unsigned int avb_mdio_pins[] = {
-	/* AVB_MDC, AVB_MDIO */
-	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
-};
-static const unsigned int avb_mdio_mux[] = {
-	AVB_MDC_MARK, AVB_MDIO_MARK,
-};
-static const unsigned int avb_rgmii_pins[] = {
-	/*
-	 * AVB_TX_CTL, AVB_TXC, AVB_TD0, AVB_TD1, AVB_TD2, AVB_TD3,
-	 * AVB_RX_CTL, AVB_RXC, AVB_RD0, AVB_RD1, AVB_RD2, AVB_RD3,
-	 */
-	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
-	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
-	RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
-	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
-	RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
-	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
-};
-static const unsigned int avb_rgmii_mux[] = {
-	AVB_TX_CTL_MARK, AVB_TXC_MARK,
-	AVB_TD0_MARK, AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
-	AVB_RX_CTL_MARK, AVB_RXC_MARK,
-	AVB_RD0_MARK, AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
-};
-static const unsigned int avb_txcrefclk_pins[] = {
-	/* AVB_TXCREFCLK */
-	RCAR_GP_PIN(1, 13),
-};
-static const unsigned int avb_txcrefclk_mux[] = {
-	AVB_TXCREFCLK_MARK,
-};
-static const unsigned int avb_avtp_pps_pins[] = {
-	/* AVB_AVTP_PPS */
-	RCAR_GP_PIN(2, 6),
-};
-static const unsigned int avb_avtp_pps_mux[] = {
-	AVB_AVTP_PPS_MARK,
-};
-static const unsigned int avb_avtp_capture_pins[] = {
-	/* AVB_AVTP_CAPTURE */
-	RCAR_GP_PIN(1, 20),
-};
-static const unsigned int avb_avtp_capture_mux[] = {
-	AVB_AVTP_CAPTURE_MARK,
-};
-static const unsigned int avb_avtp_match_pins[] = {
-	/* AVB_AVTP_MATCH */
-	RCAR_GP_PIN(1, 19),
-};
-static const unsigned int avb_avtp_match_mux[] = {
-	AVB_AVTP_MATCH_MARK,
-};
-
-/* - CANFD0 ----------------------------------------------------------------- */
-static const unsigned int canfd0_data_a_pins[] = {
-	/* CANFD0_TX, CANFD0_RX */
-	RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
-};
-static const unsigned int canfd0_data_a_mux[] = {
-	CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
-};
-static const unsigned int canfd0_data_b_pins[] = {
-	/* CANFD0_TX, CANFD0_RX */
-	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-};
-static const unsigned int canfd0_data_b_mux[] = {
-	CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
-};
-
-/* - CANFD1 ----------------------------------------------------------------- */
-static const unsigned int canfd1_data_pins[] = {
-	/* CANFD1_TX, CANFD1_RX */
-	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
-};
-static const unsigned int canfd1_data_mux[] = {
-	CANFD1_TX_MARK, CANFD1_RX_MARK,
-};
-
-/* - CANFD Clock ------------------------------------------------------------ */
-static const unsigned int canfd_clk_a_pins[] = {
-	/* CANFD_CLK */
-	RCAR_GP_PIN(1, 25),
-};
-static const unsigned int canfd_clk_a_mux[] = {
-	CANFD_CLK_A_MARK,
-};
-static const unsigned int canfd_clk_b_pins[] = {
-	/* CANFD_CLK */
-	RCAR_GP_PIN(3, 8),
-};
-static const unsigned int canfd_clk_b_mux[] = {
-	CANFD_CLK_B_MARK,
-};
-
-/* - DU --------------------------------------------------------------------- */
-static const unsigned int du_rgb666_pins[] = {
-	/* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
-	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
-	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
-	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
-};
-static const unsigned int du_rgb666_mux[] = {
-	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
-	DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
-	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
-	DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
-	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
-	DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
-};
-static const unsigned int du_rgb888_pins[] = {
-	/* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */
-	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
-	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19),
-	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
-	RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
-	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
-	RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
-};
-static const unsigned int du_rgb888_mux[] = {
-	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
-	DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
-	DU_DR1_MARK, DU_DR0_MARK,
-	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
-	DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
-	DU_DG1_MARK, DU_DG0_MARK,
-	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
-	DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
-	DU_DB1_MARK, DU_DB0_MARK,
-};
-static const unsigned int du_clk_out_pins[] = {
-	/* DU_DOTCLKOUT */
-	RCAR_GP_PIN(0, 18),
-};
-static const unsigned int du_clk_out_mux[] = {
-	DU_DOTCLKOUT_MARK,
-};
-static const unsigned int du_sync_pins[] = {
-	/* DU_EXVSYNC/DU_VSYNC, DU_EXHSYNC/DU_HSYNC */
-	RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
-};
-static const unsigned int du_sync_mux[] = {
-	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
-};
-static const unsigned int du_oddf_pins[] = {
-	/* DU_EXODDF/DU_ODDF/DISP/CDE */
-	RCAR_GP_PIN(0, 21),
-};
-static const unsigned int du_oddf_mux[] = {
-	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
-};
-static const unsigned int du_cde_pins[] = {
-	/* DU_CDE */
-	RCAR_GP_PIN(1, 22),
-};
-static const unsigned int du_cde_mux[] = {
-	DU_CDE_MARK,
-};
-static const unsigned int du_disp_pins[] = {
-	/* DU_DISP */
-	RCAR_GP_PIN(1, 21),
-};
-static const unsigned int du_disp_mux[] = {
-	DU_DISP_MARK,
-};
-
-/* - GETHER ----------------------------------------------------------------- */
-static const unsigned int gether_link_a_pins[] = {
-	/* GETHER_LINK */
-	RCAR_GP_PIN(4, 24),
-};
-static const unsigned int gether_link_a_mux[] = {
-	GETHER_LINK_A_MARK,
-};
-static const unsigned int gether_phy_int_a_pins[] = {
-	/* GETHER_PHY_INT */
-	RCAR_GP_PIN(4, 23),
-};
-static const unsigned int gether_phy_int_a_mux[] = {
-	GETHER_PHY_INT_A_MARK,
-};
-static const unsigned int gether_mdio_a_pins[] = {
-	/* GETHER_MDC, GETHER_MDIO */
-	RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
-};
-static const unsigned int gether_mdio_a_mux[] = {
-	GETHER_MDC_A_MARK, GETHER_MDIO_A_MARK,
-};
-static const unsigned int gether_link_b_pins[] = {
-	/* GETHER_LINK */
-	RCAR_GP_PIN(0, 18),
-};
-static const unsigned int gether_link_b_mux[] = {
-	GETHER_LINK_B_MARK,
-};
-static const unsigned int gether_phy_int_b_pins[] = {
-	/* GETHER_PHY_INT */
-	RCAR_GP_PIN(0, 19),
-};
-static const unsigned int gether_phy_int_b_mux[] = {
-	GETHER_PHY_INT_B_MARK,
-};
-static const unsigned int gether_mdio_b_mux[] = {
-	GETHER_MDC_B_MARK, GETHER_MDIO_B_MARK,
-};
-static const unsigned int gether_mdio_b_pins[] = {
-	/* GETHER_MDC, GETHER_MDIO */
-	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
-};
-static const unsigned int gether_magic_pins[] = {
-	/* GETHER_MAGIC */
-	RCAR_GP_PIN(4, 22),
-};
-static const unsigned int gether_magic_mux[] = {
-	GETHER_MAGIC_MARK,
-};
-static const unsigned int gether_rgmii_pins[] = {
-	/*
-	 * GETHER_TX_CTL, GETHER_TXC,
-	 * GETHER_TD0, GETHER_TD1, GETHER_TD2, GETHER_TD3,
-	 * GETHER_RX_CTL, GETHER_RXC,
-	 * GETHER_RD0, GETHER_RD1, GETHER_RD2, GETHER_RD3,
-	 */
-	RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
-	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
-	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
-	RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
-	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
-	RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
-};
-static const unsigned int gether_rgmii_mux[] = {
-	GETHER_TX_CTL_MARK, GETHER_TXC_MARK,
-	GETHER_TD0_MARK, GETHER_TD1_MARK,
-	GETHER_TD2_MARK, GETHER_TD3_MARK,
-	GETHER_RX_CTL_MARK, GETHER_RXC_MARK,
-	GETHER_RD0_MARK, AVB_RD1_MARK,
-	GETHER_RD2_MARK, AVB_RD3_MARK,
-};
-static const unsigned int gether_txcrefclk_pins[] = {
-	/* GETHER_TXCREFCLK */
-	RCAR_GP_PIN(4, 18),
-};
-static const unsigned int gether_txcrefclk_mux[] = {
-	GETHER_TXCREFCLK_MARK,
-};
-static const unsigned int gether_txcrefclk_mega_pins[] = {
-	/* GETHER_TXCREFCLK_MEGA */
-	RCAR_GP_PIN(4, 19),
-};
-static const unsigned int gether_txcrefclk_mega_mux[] = {
-	GETHER_TXCREFCLK_MEGA_MARK,
-};
-static const unsigned int gether_rmii_pins[] = {
-	/*
-	 * GETHER_RMII_CRS_DV, GETHER_RMII_RX_ER,
-	 * GETHER_RMII_RXD0, GETHER_RMII_RXD1,
-	 * GETHER_RMII_TXD_EN, GETHER_RMII_TXD0,
-	 * GETHER_RMII_TXD1, GETHER_RMII_REFCLK
-	 */
-	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-};
-static const unsigned int gether_rmii_mux[] = {
-	GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK,
-	GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK,
-	GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK,
-	GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK,
-};
-
-/* - HSCIF0 ----------------------------------------------------------------- */
-static const unsigned int hscif0_data_a_pins[] = {
-	/* HRX0, HTX0 */
-	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15),
-};
-static const unsigned int hscif0_data_a_mux[] = {
-	HRX0_A_MARK, HTX0_A_MARK,
-};
-static const unsigned int hscif0_clk_a_pins[] = {
-	/* HSCK0 */
-	RCAR_GP_PIN(0, 12),
-};
-static const unsigned int hscif0_clk_a_mux[] = {
-	HSCK0_A_MARK,
-};
-static const unsigned int hscif0_ctrl_a_pins[] = {
-	/* HRTS0#, HCTS0# */
-	RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
-};
-static const unsigned int hscif0_ctrl_a_mux[] = {
-	HRTS0_N_A_MARK, HCTS0_N_A_MARK,
-};
-static const unsigned int hscif0_data_b_pins[] = {
-	/* HRX0, HTX0 */
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-};
-static const unsigned int hscif0_data_b_mux[] = {
-	HRX0_B_MARK, HTX0_B_MARK,
-};
-static const unsigned int hscif0_clk_b_pins[] = {
-	/* HSCK0 */
-	RCAR_GP_PIN(4, 1),
-};
-static const unsigned int hscif0_clk_b_mux[] = {
-	HSCK0_B_MARK,
-};
-static const unsigned int hscif0_ctrl_b_pins[] = {
-	/* HRTS0#, HCTS0# */
-	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
-};
-static const unsigned int hscif0_ctrl_b_mux[] = {
-	HRTS0_N_B_MARK, HCTS0_N_B_MARK,
-};
-
-/* - HSCIF1 ----------------------------------------------------------------- */
-static const unsigned int hscif1_data_pins[] = {
-	/* HRX1, HTX1 */
-	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
-};
-static const unsigned int hscif1_data_mux[] = {
-	HRX1_MARK, HTX1_MARK,
-};
-static const unsigned int hscif1_clk_pins[] = {
-	/* HSCK1 */
-	RCAR_GP_PIN(2, 7),
-};
-static const unsigned int hscif1_clk_mux[] = {
-	HSCK1_MARK,
-};
-static const unsigned int hscif1_ctrl_pins[] = {
-	/* HRTS1#, HCTS1# */
-	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
-};
-static const unsigned int hscif1_ctrl_mux[] = {
-	HRTS1_N_MARK, HCTS1_N_MARK,
-};
-
-/* - HSCIF2 ----------------------------------------------------------------- */
-static const unsigned int hscif2_data_pins[] = {
-	/* HRX2, HTX2 */
-	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
-};
-static const unsigned int hscif2_data_mux[] = {
-	HRX2_MARK, HTX2_MARK,
-};
-static const unsigned int hscif2_clk_pins[] = {
-	/* HSCK2 */
-	RCAR_GP_PIN(2, 12),
-};
-static const unsigned int hscif2_clk_mux[] = {
-	HSCK2_MARK,
-};
-static const unsigned int hscif2_ctrl_pins[] = {
-	/* HRTS2#, HCTS2# */
-	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
-};
-static const unsigned int hscif2_ctrl_mux[] = {
-	HRTS2_N_MARK, HCTS2_N_MARK,
-};
-
-/* - HSCIF3 ----------------------------------------------------------------- */
-static const unsigned int hscif3_data_pins[] = {
-	/* HRX3, HTX3 */
-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
-};
-static const unsigned int hscif3_data_mux[] = {
-	HRX3_MARK, HTX3_MARK,
-};
-static const unsigned int hscif3_clk_pins[] = {
-	/* HSCK3 */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int hscif3_clk_mux[] = {
-	HSCK3_MARK,
-};
-static const unsigned int hscif3_ctrl_pins[] = {
-	/* HRTS3#, HCTS3# */
-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
-};
-static const unsigned int hscif3_ctrl_mux[] = {
-	HRTS3_N_MARK, HCTS3_N_MARK,
-};
-
-/* - I2C0 ------------------------------------------------------------------- */
-static const unsigned int i2c0_pins[] = {
-	/* SDA0, SCL0 */
-	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
-};
-static const unsigned int i2c0_mux[] = {
-	SDA0_MARK, SCL0_MARK,
-};
-
-/* - I2C1 ------------------------------------------------------------------- */
-static const unsigned int i2c1_pins[] = {
-	/* SDA1, SCL1 */
-	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
-};
-static const unsigned int i2c1_mux[] = {
-	SDA1_MARK, SCL1_MARK,
-};
-
-/* - I2C2 ------------------------------------------------------------------- */
-static const unsigned int i2c2_pins[] = {
-	/* SDA2, SCL2 */
-	RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
-};
-static const unsigned int i2c2_mux[] = {
-	SDA2_MARK, SCL2_MARK,
-};
-
-/* - I2C3 ------------------------------------------------------------------- */
-static const unsigned int i2c3_pins[] = {
-	/* SDA3, SCL3 */
-	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
-};
-static const unsigned int i2c3_mux[] = {
-	SDA3_MARK, SCL3_MARK,
-};
-
-/* - I2C4 ------------------------------------------------------------------- */
-static const unsigned int i2c4_pins[] = {
-	/* SDA4, SCL4 */
-	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
-};
-static const unsigned int i2c4_mux[] = {
-	SDA4_MARK, SCL4_MARK,
-};
-
-/* - I2C5 ------------------------------------------------------------------- */
-static const unsigned int i2c5_pins[] = {
-	/* SDA5, SCL5 */
-	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
-};
-static const unsigned int i2c5_mux[] = {
-	SDA5_MARK, SCL5_MARK,
-};
-
-/* - INTC-EX ---------------------------------------------------------------- */
-static const unsigned int intc_ex_irq0_pins[] = {
-	/* IRQ0 */
-	RCAR_GP_PIN(1, 0),
-};
-static const unsigned int intc_ex_irq0_mux[] = {
-	IRQ0_MARK,
-};
-static const unsigned int intc_ex_irq1_pins[] = {
-	/* IRQ1 */
-	RCAR_GP_PIN(0, 12),
-};
-static const unsigned int intc_ex_irq1_mux[] = {
-	IRQ1_MARK,
-};
-static const unsigned int intc_ex_irq2_pins[] = {
-	/* IRQ2 */
-	RCAR_GP_PIN(0, 13),
-};
-static const unsigned int intc_ex_irq2_mux[] = {
-	IRQ2_MARK,
-};
-static const unsigned int intc_ex_irq3_pins[] = {
-	/* IRQ3 */
-	RCAR_GP_PIN(0, 14),
-};
-static const unsigned int intc_ex_irq3_mux[] = {
-	IRQ3_MARK,
-};
-static const unsigned int intc_ex_irq4_pins[] = {
-	/* IRQ4 */
-	RCAR_GP_PIN(2, 17),
-};
-static const unsigned int intc_ex_irq4_mux[] = {
-	IRQ4_MARK,
-};
-static const unsigned int intc_ex_irq5_pins[] = {
-	/* IRQ5 */
-	RCAR_GP_PIN(2, 18),
-};
-static const unsigned int intc_ex_irq5_mux[] = {
-	IRQ5_MARK,
-};
-
-/* - MMC -------------------------------------------------------------------- */
-static const unsigned int mmc_data1_pins[] = {
-	/* MMC_D0 */
-	RCAR_GP_PIN(3, 8),
-};
-static const unsigned int mmc_data1_mux[] = {
-	MMC_D0_MARK,
-};
-static const unsigned int mmc_data4_pins[] = {
-	/* MMC_D[0:3] */
-	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-};
-static const unsigned int mmc_data4_mux[] = {
-	MMC_D0_MARK, MMC_D1_MARK,
-	MMC_D2_MARK, MMC_D3_MARK,
-};
-static const unsigned int mmc_data8_pins[] = {
-	/* MMC_D[0:7] */
-	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
-	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
-};
-static const unsigned int mmc_data8_mux[] = {
-	MMC_D0_MARK, MMC_D1_MARK,
-	MMC_D2_MARK, MMC_D3_MARK,
-	MMC_D4_MARK, MMC_D5_MARK,
-	MMC_D6_MARK, MMC_D7_MARK,
-};
-static const unsigned int mmc_ctrl_pins[] = {
-	/* MMC_CLK, MMC_CMD */
-	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7),
-};
-static const unsigned int mmc_ctrl_mux[] = {
-	MMC_CLK_MARK, MMC_CMD_MARK,
-};
-static const unsigned int mmc_cd_pins[] = {
-	/* MMC_CD */
-	RCAR_GP_PIN(3, 5),
-};
-static const unsigned int mmc_cd_mux[] = {
-	MMC_CD_MARK,
-};
-static const unsigned int mmc_wp_pins[] = {
-	/* MMC_WP */
-	RCAR_GP_PIN(3, 4),
-};
-static const unsigned int mmc_wp_mux[] = {
-	MMC_WP_MARK,
-};
-static const unsigned int mmc_ds_pins[] = {
-	/* MMC_DS */
-	RCAR_GP_PIN(3, 6),
-};
-static const unsigned int mmc_ds_mux[] = {
-	MMC_DS_MARK,
-};
-
-/* - MSIOF0 ----------------------------------------------------------------- */
-static const unsigned int msiof0_clk_pins[] = {
-	/* MSIOF0_SCK */
-	RCAR_GP_PIN(2, 21),
-};
-static const unsigned int msiof0_clk_mux[] = {
-	MSIOF0_SCK_MARK,
-};
-static const unsigned int msiof0_sync_pins[] = {
-	/* MSIOF0_SYNC */
-	RCAR_GP_PIN(2, 22),
-};
-static const unsigned int msiof0_sync_mux[] = {
-	MSIOF0_SYNC_MARK,
-};
-static const unsigned int msiof0_ss1_pins[] = {
-	/* MSIOF0_SS1 */
-	RCAR_GP_PIN(2, 23),
-};
-static const unsigned int msiof0_ss1_mux[] = {
-	MSIOF0_SS1_MARK,
-};
-static const unsigned int msiof0_ss2_pins[] = {
-	/* MSIOF0_SS2 */
-	RCAR_GP_PIN(2, 24),
-};
-static const unsigned int msiof0_ss2_mux[] = {
-	MSIOF0_SS2_MARK,
-};
-static const unsigned int msiof0_txd_pins[] = {
-	/* MSIOF0_TXD */
-	RCAR_GP_PIN(2, 20),
-};
-static const unsigned int msiof0_txd_mux[] = {
-	MSIOF0_TXD_MARK,
-};
-static const unsigned int msiof0_rxd_pins[] = {
-	/* MSIOF0_RXD */
-	RCAR_GP_PIN(2, 19),
-};
-static const unsigned int msiof0_rxd_mux[] = {
-	MSIOF0_RXD_MARK,
-};
-
-/* - MSIOF1 ----------------------------------------------------------------- */
-static const unsigned int msiof1_clk_pins[] = {
-	/* MSIOF1_SCK */
-	RCAR_GP_PIN(3, 2),
-};
-static const unsigned int msiof1_clk_mux[] = {
-	MSIOF1_SCK_MARK,
-};
-static const unsigned int msiof1_sync_pins[] = {
-	/* MSIOF1_SYNC */
-	RCAR_GP_PIN(3, 3),
-};
-static const unsigned int msiof1_sync_mux[] = {
-	MSIOF1_SYNC_MARK,
-};
-static const unsigned int msiof1_ss1_pins[] = {
-	/* MSIOF1_SS1 */
-	RCAR_GP_PIN(3, 4),
-};
-static const unsigned int msiof1_ss1_mux[] = {
-	MSIOF1_SS1_MARK,
-};
-static const unsigned int msiof1_ss2_pins[] = {
-	/* MSIOF1_SS2 */
-	RCAR_GP_PIN(3, 5),
-};
-static const unsigned int msiof1_ss2_mux[] = {
-	MSIOF1_SS2_MARK,
-};
-static const unsigned int msiof1_txd_pins[] = {
-	/* MSIOF1_TXD */
-	RCAR_GP_PIN(3, 1),
-};
-static const unsigned int msiof1_txd_mux[] = {
-	MSIOF1_TXD_MARK,
-};
-static const unsigned int msiof1_rxd_pins[] = {
-	/* MSIOF1_RXD */
-	RCAR_GP_PIN(3, 0),
-};
-static const unsigned int msiof1_rxd_mux[] = {
-	MSIOF1_RXD_MARK,
-};
-
-/* - MSIOF2 ----------------------------------------------------------------- */
-static const unsigned int msiof2_clk_pins[] = {
-	/* MSIOF2_SCK */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int msiof2_clk_mux[] = {
-	MSIOF2_SCK_MARK,
-};
-static const unsigned int msiof2_sync_pins[] = {
-	/* MSIOF2_SYNC */
-	RCAR_GP_PIN(2, 3),
-};
-static const unsigned int msiof2_sync_mux[] = {
-	MSIOF2_SYNC_MARK,
-};
-static const unsigned int msiof2_ss1_pins[] = {
-	/* MSIOF2_SS1 */
-	RCAR_GP_PIN(2, 4),
-};
-static const unsigned int msiof2_ss1_mux[] = {
-	MSIOF2_SS1_MARK,
-};
-static const unsigned int msiof2_ss2_pins[] = {
-	/* MSIOF2_SS2 */
-	RCAR_GP_PIN(2, 5),
-};
-static const unsigned int msiof2_ss2_mux[] = {
-	MSIOF2_SS2_MARK,
-};
-static const unsigned int msiof2_txd_pins[] = {
-	/* MSIOF2_TXD */
-	RCAR_GP_PIN(2, 2),
-};
-static const unsigned int msiof2_txd_mux[] = {
-	MSIOF2_TXD_MARK,
-};
-static const unsigned int msiof2_rxd_pins[] = {
-	/* MSIOF2_RXD */
-	RCAR_GP_PIN(2, 1),
-};
-static const unsigned int msiof2_rxd_mux[] = {
-	MSIOF2_RXD_MARK,
-};
-
-/* - MSIOF3 ----------------------------------------------------------------- */
-static const unsigned int msiof3_clk_pins[] = {
-	/* MSIOF3_SCK */
-	RCAR_GP_PIN(0, 20),
-};
-static const unsigned int msiof3_clk_mux[] = {
-	MSIOF3_SCK_MARK,
-};
-static const unsigned int msiof3_sync_pins[] = {
-	/* MSIOF3_SYNC */
-	RCAR_GP_PIN(0, 21),
-};
-static const unsigned int msiof3_sync_mux[] = {
-	MSIOF3_SYNC_MARK,
-};
-static const unsigned int msiof3_ss1_pins[] = {
-	/* MSIOF3_SS1 */
-	RCAR_GP_PIN(0, 18),
-};
-static const unsigned int msiof3_ss1_mux[] = {
-	MSIOF3_SS1_MARK,
-};
-static const unsigned int msiof3_ss2_pins[] = {
-	/* MSIOF3_SS2 */
-	RCAR_GP_PIN(0, 19),
-};
-static const unsigned int msiof3_ss2_mux[] = {
-	MSIOF3_SS2_MARK,
-};
-static const unsigned int msiof3_txd_pins[] = {
-	/* MSIOF3_TXD */
-	RCAR_GP_PIN(0, 17),
-};
-static const unsigned int msiof3_txd_mux[] = {
-	MSIOF3_TXD_MARK,
-};
-static const unsigned int msiof3_rxd_pins[] = {
-	/* MSIOF3_RXD */
-	RCAR_GP_PIN(0, 16),
-};
-static const unsigned int msiof3_rxd_mux[] = {
-	MSIOF3_RXD_MARK,
-};
-
-/* - PWM0 ------------------------------------------------------------------- */
-static const unsigned int pwm0_a_pins[] = {
-	/* PWM0 */
-	RCAR_GP_PIN(0, 15),
-};
-static const unsigned int pwm0_a_mux[] = {
-	PWM0_A_MARK,
-};
-static const unsigned int pwm0_b_pins[] = {
-	/* PWM0 */
-	RCAR_GP_PIN(1, 21),
-};
-static const unsigned int pwm0_b_mux[] = {
-	PWM0_B_MARK,
-};
-
-/* - PWM1 ------------------------------------------------------------------- */
-static const unsigned int pwm1_a_pins[] = {
-	/* PWM1 */
-	RCAR_GP_PIN(2, 13),
-};
-static const unsigned int pwm1_a_mux[] = {
-	PWM1_A_MARK,
-};
-static const unsigned int pwm1_b_pins[] = {
-	/* PWM1 */
-	RCAR_GP_PIN(1, 22),
-};
-static const unsigned int pwm1_b_mux[] = {
-	PWM1_B_MARK,
-};
-
-/* - PWM2 ------------------------------------------------------------------- */
-static const unsigned int pwm2_a_pins[] = {
-	/* PWM2 */
-	RCAR_GP_PIN(2, 14),
-};
-static const unsigned int pwm2_a_mux[] = {
-	PWM2_A_MARK,
-};
-static const unsigned int pwm2_b_pins[] = {
-	/* PWM2 */
-	RCAR_GP_PIN(1, 23),
-};
-static const unsigned int pwm2_b_mux[] = {
-	PWM2_B_MARK,
-};
-
-/* - PWM3 ------------------------------------------------------------------- */
-static const unsigned int pwm3_a_pins[] = {
-	/* PWM3 */
-	RCAR_GP_PIN(2, 15),
-};
-static const unsigned int pwm3_a_mux[] = {
-	PWM3_A_MARK,
-};
-static const unsigned int pwm3_b_pins[] = {
-	/* PWM3 */
-	RCAR_GP_PIN(1, 24),
-};
-static const unsigned int pwm3_b_mux[] = {
-	PWM3_B_MARK,
-};
-
-/* - PWM4 ------------------------------------------------------------------- */
-static const unsigned int pwm4_a_pins[] = {
-	/* PWM4 */
-	RCAR_GP_PIN(2, 16),
-};
-static const unsigned int pwm4_a_mux[] = {
-	PWM4_A_MARK,
-};
-static const unsigned int pwm4_b_pins[] = {
-	/* PWM4 */
-	RCAR_GP_PIN(1, 25),
-};
-static const unsigned int pwm4_b_mux[] = {
-	PWM4_B_MARK,
-};
-
-/* - QSPI0 ------------------------------------------------------------------ */
-static const unsigned int qspi0_ctrl_pins[] = {
-	/* SPCLK, SSL */
-	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
-};
-static const unsigned int qspi0_ctrl_mux[] = {
-	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
-};
-static const unsigned int qspi0_data2_pins[] = {
-	/* MOSI_IO0, MISO_IO1 */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-};
-static const unsigned int qspi0_data2_mux[] = {
-	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
-};
-static const unsigned int qspi0_data4_pins[] = {
-	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
-};
-static const unsigned int qspi0_data4_mux[] = {
-	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
-	QSPI0_IO2_MARK, QSPI0_IO3_MARK
-};
-
-/* - QSPI1 ------------------------------------------------------------------ */
-static const unsigned int qspi1_ctrl_pins[] = {
-	/* SPCLK, SSL */
-	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
-};
-static const unsigned int qspi1_ctrl_mux[] = {
-	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
-};
-static const unsigned int qspi1_data2_pins[] = {
-	/* MOSI_IO0, MISO_IO1 */
-	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
-};
-static const unsigned int qspi1_data2_mux[] = {
-	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
-};
-static const unsigned int qspi1_data4_pins[] = {
-	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
-	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
-	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
-};
-static const unsigned int qspi1_data4_mux[] = {
-	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
-	QSPI1_IO2_MARK, QSPI1_IO3_MARK
-};
-
-/* - SCIF0 ------------------------------------------------------------------ */
-static const unsigned int scif0_data_pins[] = {
-	/* RX0, TX0 */
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-};
-static const unsigned int scif0_data_mux[] = {
-	RX0_MARK, TX0_MARK,
-};
-static const unsigned int scif0_clk_pins[] = {
-	/* SCK0 */
-	RCAR_GP_PIN(4, 1),
-};
-static const unsigned int scif0_clk_mux[] = {
-	SCK0_MARK,
-};
-static const unsigned int scif0_ctrl_pins[] = {
-	/* RTS0#, CTS0# */
-	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
-};
-static const unsigned int scif0_ctrl_mux[] = {
-	RTS0_N_MARK, CTS0_N_MARK,
-};
-
-/* - SCIF1 ------------------------------------------------------------------ */
-static const unsigned int scif1_data_a_pins[] = {
-	/* RX1, TX1 */
-	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
-};
-static const unsigned int scif1_data_a_mux[] = {
-	RX1_A_MARK, TX1_A_MARK,
-};
-static const unsigned int scif1_clk_pins[] = {
-	/* SCK1 */
-	RCAR_GP_PIN(2, 5),
-};
-static const unsigned int scif1_clk_mux[] = {
-	SCK1_MARK,
-};
-static const unsigned int scif1_ctrl_pins[] = {
-	/* RTS1#, CTS1# */
-	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
-};
-static const unsigned int scif1_ctrl_mux[] = {
-	RTS1_N_MARK, CTS1_N_MARK,
-};
-static const unsigned int scif1_data_b_pins[] = {
-	/* RX1, TX1 */
-	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
-};
-static const unsigned int scif1_data_b_mux[] = {
-	RX1_B_MARK, TX1_B_MARK,
-};
-
-/* - SCIF3 ------------------------------------------------------------------ */
-static const unsigned int scif3_data_pins[] = {
-	/* RX3, TX3 */
-	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
-};
-static const unsigned int scif3_data_mux[] = {
-	RX3_MARK, TX3_MARK,
-};
-static const unsigned int scif3_clk_pins[] = {
-	/* SCK3 */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int scif3_clk_mux[] = {
-	SCK3_MARK,
-};
-static const unsigned int scif3_ctrl_pins[] = {
-	/* RTS3#, CTS3# */
-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
-};
-static const unsigned int scif3_ctrl_mux[] = {
-	RTS3_N_MARK, CTS3_N_MARK,
-};
-
-/* - SCIF4 ------------------------------------------------------------------ */
-static const unsigned int scif4_data_pins[] = {
-	/* RX4, TX4 */
-	RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
-};
-static const unsigned int scif4_data_mux[] = {
-	RX4_MARK, TX4_MARK,
-};
-static const unsigned int scif4_clk_pins[] = {
-	/* SCK4 */
-	RCAR_GP_PIN(0, 0),
-};
-static const unsigned int scif4_clk_mux[] = {
-	SCK4_MARK,
-};
-static const unsigned int scif4_ctrl_pins[] = {
-	/* RTS4#, CTS4# */
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
-};
-static const unsigned int scif4_ctrl_mux[] = {
-	RTS4_N_MARK, CTS4_N_MARK,
-};
-
-/* - SCIF Clock ------------------------------------------------------------- */
-static const unsigned int scif_clk_a_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(0, 10),
-};
-static const unsigned int scif_clk_a_mux[] = {
-	SCIF_CLK_A_MARK,
-};
-static const unsigned int scif_clk_b_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(1, 25),
-};
-static const unsigned int scif_clk_b_mux[] = {
-	SCIF_CLK_B_MARK,
-};
-
-/* - TMU -------------------------------------------------------------------- */
-static const unsigned int tmu_tclk1_a_pins[] = {
-	/* TCLK1 */
-	RCAR_GP_PIN(3, 13),
-};
-static const unsigned int tmu_tclk1_a_mux[] = {
-	TCLK1_A_MARK,
-};
-static const unsigned int tmu_tclk1_b_pins[] = {
-	/* TCLK1 */
-	RCAR_GP_PIN(1, 23),
-};
-static const unsigned int tmu_tclk1_b_mux[] = {
-	TCLK1_B_MARK,
-};
-static const unsigned int tmu_tclk2_a_pins[] = {
-	/* TCLK2 */
-	RCAR_GP_PIN(3, 14),
-};
-static const unsigned int tmu_tclk2_a_mux[] = {
-	TCLK2_A_MARK,
-};
-static const unsigned int tmu_tclk2_b_pins[] = {
-	/* TCLK2 */
-	RCAR_GP_PIN(1, 24),
-};
-static const unsigned int tmu_tclk2_b_mux[] = {
-	TCLK2_B_MARK,
-};
-
-/* - TPU ------------------------------------------------------------------- */
-static const unsigned int tpu_to0_pins[] = {
-	/* TPU0TO0 */
-	RCAR_GP_PIN(1, 19),
-};
-static const unsigned int tpu_to0_mux[] = {
-	TPU0TO0_MARK,
-};
-static const unsigned int tpu_to1_pins[] = {
-	/* TPU0TO1 */
-	RCAR_GP_PIN(1, 20),
-};
-static const unsigned int tpu_to1_mux[] = {
-	TPU0TO1_MARK,
-};
-static const unsigned int tpu_to2_pins[] = {
-	/* TPU0TO2 */
-	RCAR_GP_PIN(4, 2),
-};
-static const unsigned int tpu_to2_mux[] = {
-	TPU0TO2_MARK,
-};
-static const unsigned int tpu_to3_pins[] = {
-	/* TPU0TO3 */
-	RCAR_GP_PIN(4, 3),
-};
-static const unsigned int tpu_to3_mux[] = {
-	TPU0TO3_MARK,
-};
-
-/* - VIN0 ------------------------------------------------------------------- */
-static const union vin_data vin0_data_pins = {
-	.data24 = {
-		RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-		RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-		RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
-		RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
-		RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
-		RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
-		RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
-		RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
-		RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
-		RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
-		RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
-		RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
-	},
-};
-static const union vin_data vin0_data_mux = {
-	.data24 = {
-		VI0_DATA0_MARK, VI0_DATA1_MARK,
-		VI0_DATA2_MARK, VI0_DATA3_MARK,
-		VI0_DATA4_MARK, VI0_DATA5_MARK,
-		VI0_DATA6_MARK, VI0_DATA7_MARK,
-		VI0_DATA8_MARK, VI0_DATA9_MARK,
-		VI0_DATA10_MARK, VI0_DATA11_MARK,
-		VI0_DATA12_MARK, VI0_DATA13_MARK,
-		VI0_DATA14_MARK, VI0_DATA15_MARK,
-		VI0_DATA16_MARK, VI0_DATA17_MARK,
-		VI0_DATA18_MARK, VI0_DATA19_MARK,
-		VI0_DATA20_MARK, VI0_DATA21_MARK,
-		VI0_DATA22_MARK, VI0_DATA23_MARK,
-	},
-};
-static const unsigned int vin0_data18_pins[] = {
-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
-	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
-	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
-	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
-	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
-	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
-	RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
-	RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
-};
-static const unsigned int vin0_data18_mux[] = {
-	VI0_DATA2_MARK, VI0_DATA3_MARK,
-	VI0_DATA4_MARK, VI0_DATA5_MARK,
-	VI0_DATA6_MARK, VI0_DATA7_MARK,
-	VI0_DATA10_MARK, VI0_DATA11_MARK,
-	VI0_DATA12_MARK, VI0_DATA13_MARK,
-	VI0_DATA14_MARK, VI0_DATA15_MARK,
-	VI0_DATA18_MARK, VI0_DATA19_MARK,
-	VI0_DATA20_MARK, VI0_DATA21_MARK,
-	VI0_DATA22_MARK, VI0_DATA23_MARK,
-};
-static const unsigned int vin0_sync_pins[] = {
-	/* VI0_VSYNC#, VI0_HSYNC# */
-	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
-};
-static const unsigned int vin0_sync_mux[] = {
-	VI0_VSYNC_N_MARK, VI0_HSYNC_N_MARK,
-};
-static const unsigned int vin0_field_pins[] = {
-	/* VI0_FIELD */
-	RCAR_GP_PIN(2, 16),
-};
-static const unsigned int vin0_field_mux[] = {
-	VI0_FIELD_MARK,
-};
-static const unsigned int vin0_clkenb_pins[] = {
-	/* VI0_CLKENB */
-	RCAR_GP_PIN(2, 1),
-};
-static const unsigned int vin0_clkenb_mux[] = {
-	VI0_CLKENB_MARK,
-};
-static const unsigned int vin0_clk_pins[] = {
-	/* VI0_CLK */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int vin0_clk_mux[] = {
-	VI0_CLK_MARK,
-};
-
-/* - VIN1 ------------------------------------------------------------------- */
-static const union vin_data12 vin1_data_pins = {
-	.data12 = {
-		RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
-		RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-		RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-		RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-		RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
-		RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
-	},
-};
-static const union vin_data12 vin1_data_mux = {
-	.data12 = {
-		VI1_DATA0_MARK, VI1_DATA1_MARK,
-		VI1_DATA2_MARK, VI1_DATA3_MARK,
-		VI1_DATA4_MARK, VI1_DATA5_MARK,
-		VI1_DATA6_MARK, VI1_DATA7_MARK,
-		VI1_DATA8_MARK,  VI1_DATA9_MARK,
-		VI1_DATA10_MARK, VI1_DATA11_MARK,
-	},
-};
-static const unsigned int vin1_sync_pins[] = {
-	/* VI1_VSYNC#, VI1_HSYNC# */
-	 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
-};
-static const unsigned int vin1_sync_mux[] = {
-	VI1_VSYNC_N_MARK, VI1_HSYNC_N_MARK,
-};
-static const unsigned int vin1_field_pins[] = {
-	/* VI1_FIELD */
-	RCAR_GP_PIN(3, 16),
-};
-static const unsigned int vin1_field_mux[] = {
-	VI1_FIELD_MARK,
-};
-static const unsigned int vin1_clkenb_pins[] = {
-	/* VI1_CLKENB */
-	RCAR_GP_PIN(3, 1),
-};
-static const unsigned int vin1_clkenb_mux[] = {
-	VI1_CLKENB_MARK,
-};
-static const unsigned int vin1_clk_pins[] = {
-	/* VI1_CLK */
-	RCAR_GP_PIN(3, 0),
-};
-static const unsigned int vin1_clk_mux[] = {
-	VI1_CLK_MARK,
-};
-
-static const struct sh_pfc_pin_group pinmux_groups[] = {
-	SH_PFC_PIN_GROUP(avb_link),
-	SH_PFC_PIN_GROUP(avb_magic),
-	SH_PFC_PIN_GROUP(avb_phy_int),
-	SH_PFC_PIN_GROUP(avb_mdio),
-	SH_PFC_PIN_GROUP(avb_rgmii),
-	SH_PFC_PIN_GROUP(avb_txcrefclk),
-	SH_PFC_PIN_GROUP(avb_avtp_pps),
-	SH_PFC_PIN_GROUP(avb_avtp_capture),
-	SH_PFC_PIN_GROUP(avb_avtp_match),
-	SH_PFC_PIN_GROUP(canfd0_data_a),
-	SH_PFC_PIN_GROUP(canfd0_data_b),
-	SH_PFC_PIN_GROUP(canfd1_data),
-	SH_PFC_PIN_GROUP(canfd_clk_a),
-	SH_PFC_PIN_GROUP(canfd_clk_b),
-	SH_PFC_PIN_GROUP(du_rgb666),
-	SH_PFC_PIN_GROUP(du_rgb888),
-	SH_PFC_PIN_GROUP(du_clk_out),
-	SH_PFC_PIN_GROUP(du_sync),
-	SH_PFC_PIN_GROUP(du_oddf),
-	SH_PFC_PIN_GROUP(du_cde),
-	SH_PFC_PIN_GROUP(du_disp),
-	SH_PFC_PIN_GROUP(gether_link_a),
-	SH_PFC_PIN_GROUP(gether_phy_int_a),
-	SH_PFC_PIN_GROUP(gether_mdio_a),
-	SH_PFC_PIN_GROUP(gether_link_b),
-	SH_PFC_PIN_GROUP(gether_phy_int_b),
-	SH_PFC_PIN_GROUP(gether_mdio_b),
-	SH_PFC_PIN_GROUP(gether_magic),
-	SH_PFC_PIN_GROUP(gether_rgmii),
-	SH_PFC_PIN_GROUP(gether_txcrefclk),
-	SH_PFC_PIN_GROUP(gether_txcrefclk_mega),
-	SH_PFC_PIN_GROUP(gether_rmii),
-	SH_PFC_PIN_GROUP(hscif0_data_a),
-	SH_PFC_PIN_GROUP(hscif0_clk_a),
-	SH_PFC_PIN_GROUP(hscif0_ctrl_a),
-	SH_PFC_PIN_GROUP(hscif0_data_b),
-	SH_PFC_PIN_GROUP(hscif0_clk_b),
-	SH_PFC_PIN_GROUP(hscif0_ctrl_b),
-	SH_PFC_PIN_GROUP(hscif1_data),
-	SH_PFC_PIN_GROUP(hscif1_clk),
-	SH_PFC_PIN_GROUP(hscif1_ctrl),
-	SH_PFC_PIN_GROUP(hscif2_data),
-	SH_PFC_PIN_GROUP(hscif2_clk),
-	SH_PFC_PIN_GROUP(hscif2_ctrl),
-	SH_PFC_PIN_GROUP(hscif3_data),
-	SH_PFC_PIN_GROUP(hscif3_clk),
-	SH_PFC_PIN_GROUP(hscif3_ctrl),
-	SH_PFC_PIN_GROUP(i2c0),
-	SH_PFC_PIN_GROUP(i2c1),
-	SH_PFC_PIN_GROUP(i2c2),
-	SH_PFC_PIN_GROUP(i2c3),
-	SH_PFC_PIN_GROUP(i2c4),
-	SH_PFC_PIN_GROUP(i2c5),
-	SH_PFC_PIN_GROUP(intc_ex_irq0),
-	SH_PFC_PIN_GROUP(intc_ex_irq1),
-	SH_PFC_PIN_GROUP(intc_ex_irq2),
-	SH_PFC_PIN_GROUP(intc_ex_irq3),
-	SH_PFC_PIN_GROUP(intc_ex_irq4),
-	SH_PFC_PIN_GROUP(intc_ex_irq5),
-	SH_PFC_PIN_GROUP(mmc_data1),
-	SH_PFC_PIN_GROUP(mmc_data4),
-	SH_PFC_PIN_GROUP(mmc_data8),
-	SH_PFC_PIN_GROUP(mmc_ctrl),
-	SH_PFC_PIN_GROUP(mmc_cd),
-	SH_PFC_PIN_GROUP(mmc_wp),
-	SH_PFC_PIN_GROUP(mmc_ds),
-	SH_PFC_PIN_GROUP(msiof0_clk),
-	SH_PFC_PIN_GROUP(msiof0_sync),
-	SH_PFC_PIN_GROUP(msiof0_ss1),
-	SH_PFC_PIN_GROUP(msiof0_ss2),
-	SH_PFC_PIN_GROUP(msiof0_txd),
-	SH_PFC_PIN_GROUP(msiof0_rxd),
-	SH_PFC_PIN_GROUP(msiof1_clk),
-	SH_PFC_PIN_GROUP(msiof1_sync),
-	SH_PFC_PIN_GROUP(msiof1_ss1),
-	SH_PFC_PIN_GROUP(msiof1_ss2),
-	SH_PFC_PIN_GROUP(msiof1_txd),
-	SH_PFC_PIN_GROUP(msiof1_rxd),
-	SH_PFC_PIN_GROUP(msiof2_clk),
-	SH_PFC_PIN_GROUP(msiof2_sync),
-	SH_PFC_PIN_GROUP(msiof2_ss1),
-	SH_PFC_PIN_GROUP(msiof2_ss2),
-	SH_PFC_PIN_GROUP(msiof2_txd),
-	SH_PFC_PIN_GROUP(msiof2_rxd),
-	SH_PFC_PIN_GROUP(msiof3_clk),
-	SH_PFC_PIN_GROUP(msiof3_sync),
-	SH_PFC_PIN_GROUP(msiof3_ss1),
-	SH_PFC_PIN_GROUP(msiof3_ss2),
-	SH_PFC_PIN_GROUP(msiof3_txd),
-	SH_PFC_PIN_GROUP(msiof3_rxd),
-	SH_PFC_PIN_GROUP(pwm0_a),
-	SH_PFC_PIN_GROUP(pwm0_b),
-	SH_PFC_PIN_GROUP(pwm1_a),
-	SH_PFC_PIN_GROUP(pwm1_b),
-	SH_PFC_PIN_GROUP(pwm2_a),
-	SH_PFC_PIN_GROUP(pwm2_b),
-	SH_PFC_PIN_GROUP(pwm3_a),
-	SH_PFC_PIN_GROUP(pwm3_b),
-	SH_PFC_PIN_GROUP(pwm4_a),
-	SH_PFC_PIN_GROUP(pwm4_b),
-	SH_PFC_PIN_GROUP(qspi0_ctrl),
-	SH_PFC_PIN_GROUP(qspi0_data2),
-	SH_PFC_PIN_GROUP(qspi0_data4),
-	SH_PFC_PIN_GROUP(qspi1_ctrl),
-	SH_PFC_PIN_GROUP(qspi1_data2),
-	SH_PFC_PIN_GROUP(qspi1_data4),
-	SH_PFC_PIN_GROUP(scif0_data),
-	SH_PFC_PIN_GROUP(scif0_clk),
-	SH_PFC_PIN_GROUP(scif0_ctrl),
-	SH_PFC_PIN_GROUP(scif1_data_a),
-	SH_PFC_PIN_GROUP(scif1_clk),
-	SH_PFC_PIN_GROUP(scif1_ctrl),
-	SH_PFC_PIN_GROUP(scif1_data_b),
-	SH_PFC_PIN_GROUP(scif3_data),
-	SH_PFC_PIN_GROUP(scif3_clk),
-	SH_PFC_PIN_GROUP(scif3_ctrl),
-	SH_PFC_PIN_GROUP(scif4_data),
-	SH_PFC_PIN_GROUP(scif4_clk),
-	SH_PFC_PIN_GROUP(scif4_ctrl),
-	SH_PFC_PIN_GROUP(scif_clk_a),
-	SH_PFC_PIN_GROUP(scif_clk_b),
-	SH_PFC_PIN_GROUP(tmu_tclk1_a),
-	SH_PFC_PIN_GROUP(tmu_tclk1_b),
-	SH_PFC_PIN_GROUP(tmu_tclk2_a),
-	SH_PFC_PIN_GROUP(tmu_tclk2_b),
-	SH_PFC_PIN_GROUP(tpu_to0),
-	SH_PFC_PIN_GROUP(tpu_to1),
-	SH_PFC_PIN_GROUP(tpu_to2),
-	SH_PFC_PIN_GROUP(tpu_to3),
-	VIN_DATA_PIN_GROUP(vin0_data, 8),
-	VIN_DATA_PIN_GROUP(vin0_data, 10),
-	VIN_DATA_PIN_GROUP(vin0_data, 12),
-	VIN_DATA_PIN_GROUP(vin0_data, 16),
-	SH_PFC_PIN_GROUP(vin0_data18),
-	VIN_DATA_PIN_GROUP(vin0_data, 20),
-	VIN_DATA_PIN_GROUP(vin0_data, 24),
-	SH_PFC_PIN_GROUP(vin0_sync),
-	SH_PFC_PIN_GROUP(vin0_field),
-	SH_PFC_PIN_GROUP(vin0_clkenb),
-	SH_PFC_PIN_GROUP(vin0_clk),
-	VIN_DATA_PIN_GROUP(vin1_data, 8),
-	VIN_DATA_PIN_GROUP(vin1_data, 10),
-	VIN_DATA_PIN_GROUP(vin1_data, 12),
-	SH_PFC_PIN_GROUP(vin1_sync),
-	SH_PFC_PIN_GROUP(vin1_field),
-	SH_PFC_PIN_GROUP(vin1_clkenb),
-	SH_PFC_PIN_GROUP(vin1_clk),
-};
-
-static const char * const avb_groups[] = {
-	"avb_link",
-	"avb_magic",
-	"avb_phy_int",
-	"avb_mdio",
-	"avb_rgmii",
-	"avb_txcrefclk",
-	"avb_avtp_pps",
-	"avb_avtp_capture",
-	"avb_avtp_match",
-};
-
-static const char * const canfd0_groups[] = {
-	"canfd0_data_a",
-	"canfd0_data_b",
-};
-
-static const char * const canfd1_groups[] = {
-	"canfd1_data",
-};
-
-static const char * const canfd_clk_groups[] = {
-	"canfd_clk_a",
-	"canfd_clk_b",
-};
-
-static const char * const du_groups[] = {
-	"du_rgb666",
-	"du_rgb888",
-	"du_clk_out",
-	"du_sync",
-	"du_oddf",
-	"du_cde",
-	"du_disp",
-};
-
-static const char * const gether_groups[] = {
-	"gether_link_a",
-	"gether_phy_int_a",
-	"gether_mdio_a",
-	"gether_link_b",
-	"gether_phy_int_b",
-	"gether_mdio_b",
-	"gether_magic",
-	"gether_rgmii",
-	"gether_txcrefclk",
-	"gether_txcrefclk_mega",
-	"gether_rmii",
-};
-
-static const char * const hscif0_groups[] = {
-	"hscif0_data_a",
-	"hscif0_clk_a",
-	"hscif0_ctrl_a",
-	"hscif0_data_b",
-	"hscif0_clk_b",
-	"hscif0_ctrl_b",
-};
-
-static const char * const hscif1_groups[] = {
-	"hscif1_data",
-	"hscif1_clk",
-	"hscif1_ctrl",
-};
-
-static const char * const hscif2_groups[] = {
-	"hscif2_data",
-	"hscif2_clk",
-	"hscif2_ctrl",
-};
-
-static const char * const hscif3_groups[] = {
-	"hscif3_data",
-	"hscif3_clk",
-	"hscif3_ctrl",
-};
-
-static const char * const i2c0_groups[] = {
-	"i2c0",
-};
-
-static const char * const i2c1_groups[] = {
-	"i2c1",
-};
-
-static const char * const i2c2_groups[] = {
-	"i2c2",
-};
-
-static const char * const i2c3_groups[] = {
-	"i2c3",
-};
-
-static const char * const i2c4_groups[] = {
-	"i2c4",
-};
-
-static const char * const i2c5_groups[] = {
-	"i2c5",
-};
-
-static const char * const intc_ex_groups[] = {
-	"intc_ex_irq0",
-	"intc_ex_irq1",
-	"intc_ex_irq2",
-	"intc_ex_irq3",
-	"intc_ex_irq4",
-	"intc_ex_irq5",
-};
-
-static const char * const mmc_groups[] = {
-	"mmc_data1",
-	"mmc_data4",
-	"mmc_data8",
-	"mmc_ctrl",
-	"mmc_cd",
-	"mmc_wp",
-	"mmc_ds",
-};
-
-static const char * const msiof0_groups[] = {
-	"msiof0_clk",
-	"msiof0_sync",
-	"msiof0_ss1",
-	"msiof0_ss2",
-	"msiof0_txd",
-	"msiof0_rxd",
-};
-
-static const char * const msiof1_groups[] = {
-	"msiof1_clk",
-	"msiof1_sync",
-	"msiof1_ss1",
-	"msiof1_ss2",
-	"msiof1_txd",
-	"msiof1_rxd",
-};
-
-static const char * const msiof2_groups[] = {
-	"msiof2_clk",
-	"msiof2_sync",
-	"msiof2_ss1",
-	"msiof2_ss2",
-	"msiof2_txd",
-	"msiof2_rxd",
-};
-
-static const char * const msiof3_groups[] = {
-	"msiof3_clk",
-	"msiof3_sync",
-	"msiof3_ss1",
-	"msiof3_ss2",
-	"msiof3_txd",
-	"msiof3_rxd",
-};
-
-static const char * const pwm0_groups[] = {
-	"pwm0_a",
-	"pwm0_b",
-};
-
-static const char * const pwm1_groups[] = {
-	"pwm1_a",
-	"pwm1_b",
-};
-
-static const char * const pwm2_groups[] = {
-	"pwm2_a",
-	"pwm2_b",
-};
-
-static const char * const pwm3_groups[] = {
-	"pwm3_a",
-	"pwm3_b",
-};
-
-static const char * const pwm4_groups[] = {
-	"pwm4_a",
-	"pwm4_b",
-};
-
-static const char * const qspi0_groups[] = {
-	"qspi0_ctrl",
-	"qspi0_data2",
-	"qspi0_data4",
-};
-
-static const char * const qspi1_groups[] = {
-	"qspi1_ctrl",
-	"qspi1_data2",
-	"qspi1_data4",
-};
-
-static const char * const scif0_groups[] = {
-	"scif0_data",
-	"scif0_clk",
-	"scif0_ctrl",
-};
-
-static const char * const scif1_groups[] = {
-	"scif1_data_a",
-	"scif1_clk",
-	"scif1_ctrl",
-	"scif1_data_b",
-};
-
-static const char * const scif3_groups[] = {
-	"scif3_data",
-	"scif3_clk",
-	"scif3_ctrl",
-};
-
-static const char * const scif4_groups[] = {
-	"scif4_data",
-	"scif4_clk",
-	"scif4_ctrl",
-};
-
-static const char * const scif_clk_groups[] = {
-	"scif_clk_a",
-	"scif_clk_b",
-};
-
-static const char * const tmu_groups[] = {
-	"tmu_tclk1_a",
-	"tmu_tclk1_b",
-	"tmu_tclk2_a",
-	"tmu_tclk2_b",
-};
-
-static const char * const tpu_groups[] = {
-	"tpu_to0",
-	"tpu_to1",
-	"tpu_to2",
-	"tpu_to3",
-};
-
-static const char * const vin0_groups[] = {
-	"vin0_data8",
-	"vin0_data10",
-	"vin0_data12",
-	"vin0_data16",
-	"vin0_data18",
-	"vin0_data20",
-	"vin0_data24",
-	"vin0_sync",
-	"vin0_field",
-	"vin0_clkenb",
-	"vin0_clk",
-};
-
-static const char * const vin1_groups[] = {
-	"vin1_data8",
-	"vin1_data10",
-	"vin1_data12",
-	"vin1_sync",
-	"vin1_field",
-	"vin1_clkenb",
-	"vin1_clk",
-};
-
-static const struct sh_pfc_function pinmux_functions[] = {
-	SH_PFC_FUNCTION(avb),
-	SH_PFC_FUNCTION(canfd0),
-	SH_PFC_FUNCTION(canfd1),
-	SH_PFC_FUNCTION(canfd_clk),
-	SH_PFC_FUNCTION(du),
-	SH_PFC_FUNCTION(gether),
-	SH_PFC_FUNCTION(hscif0),
-	SH_PFC_FUNCTION(hscif1),
-	SH_PFC_FUNCTION(hscif2),
-	SH_PFC_FUNCTION(hscif3),
-	SH_PFC_FUNCTION(i2c0),
-	SH_PFC_FUNCTION(i2c1),
-	SH_PFC_FUNCTION(i2c2),
-	SH_PFC_FUNCTION(i2c3),
-	SH_PFC_FUNCTION(i2c4),
-	SH_PFC_FUNCTION(i2c5),
-	SH_PFC_FUNCTION(intc_ex),
-	SH_PFC_FUNCTION(mmc),
-	SH_PFC_FUNCTION(msiof0),
-	SH_PFC_FUNCTION(msiof1),
-	SH_PFC_FUNCTION(msiof2),
-	SH_PFC_FUNCTION(msiof3),
-	SH_PFC_FUNCTION(pwm0),
-	SH_PFC_FUNCTION(pwm1),
-	SH_PFC_FUNCTION(pwm2),
-	SH_PFC_FUNCTION(pwm3),
-	SH_PFC_FUNCTION(pwm4),
-	SH_PFC_FUNCTION(qspi0),
-	SH_PFC_FUNCTION(qspi1),
-	SH_PFC_FUNCTION(scif0),
-	SH_PFC_FUNCTION(scif1),
-	SH_PFC_FUNCTION(scif3),
-	SH_PFC_FUNCTION(scif4),
-	SH_PFC_FUNCTION(scif_clk),
-	SH_PFC_FUNCTION(tmu),
-	SH_PFC_FUNCTION(tpu),
-	SH_PFC_FUNCTION(vin0),
-	SH_PFC_FUNCTION(vin1),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-#define F_(x, y)	FN_##y
-#define FM(x)		FN_##x
-	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_0_21_FN,	GPSR0_21,
-		GP_0_20_FN,	GPSR0_20,
-		GP_0_19_FN,	GPSR0_19,
-		GP_0_18_FN,	GPSR0_18,
-		GP_0_17_FN,	GPSR0_17,
-		GP_0_16_FN,	GPSR0_16,
-		GP_0_15_FN,	GPSR0_15,
-		GP_0_14_FN,	GPSR0_14,
-		GP_0_13_FN,	GPSR0_13,
-		GP_0_12_FN,	GPSR0_12,
-		GP_0_11_FN,	GPSR0_11,
-		GP_0_10_FN,	GPSR0_10,
-		GP_0_9_FN,	GPSR0_9,
-		GP_0_8_FN,	GPSR0_8,
-		GP_0_7_FN,	GPSR0_7,
-		GP_0_6_FN,	GPSR0_6,
-		GP_0_5_FN,	GPSR0_5,
-		GP_0_4_FN,	GPSR0_4,
-		GP_0_3_FN,	GPSR0_3,
-		GP_0_2_FN,	GPSR0_2,
-		GP_0_1_FN,	GPSR0_1,
-		GP_0_0_FN,	GPSR0_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_1_27_FN,	GPSR1_27,
-		GP_1_26_FN,	GPSR1_26,
-		GP_1_25_FN,	GPSR1_25,
-		GP_1_24_FN,	GPSR1_24,
-		GP_1_23_FN,	GPSR1_23,
-		GP_1_22_FN,	GPSR1_22,
-		GP_1_21_FN,	GPSR1_21,
-		GP_1_20_FN,	GPSR1_20,
-		GP_1_19_FN,	GPSR1_19,
-		GP_1_18_FN,	GPSR1_18,
-		GP_1_17_FN,	GPSR1_17,
-		GP_1_16_FN,	GPSR1_16,
-		GP_1_15_FN,	GPSR1_15,
-		GP_1_14_FN,	GPSR1_14,
-		GP_1_13_FN,	GPSR1_13,
-		GP_1_12_FN,	GPSR1_12,
-		GP_1_11_FN,	GPSR1_11,
-		GP_1_10_FN,	GPSR1_10,
-		GP_1_9_FN,	GPSR1_9,
-		GP_1_8_FN,	GPSR1_8,
-		GP_1_7_FN,	GPSR1_7,
-		GP_1_6_FN,	GPSR1_6,
-		GP_1_5_FN,	GPSR1_5,
-		GP_1_4_FN,	GPSR1_4,
-		GP_1_3_FN,	GPSR1_3,
-		GP_1_2_FN,	GPSR1_2,
-		GP_1_1_FN,	GPSR1_1,
-		GP_1_0_FN,	GPSR1_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		GP_2_29_FN,	GPSR2_29,
-		GP_2_28_FN,	GPSR2_28,
-		GP_2_27_FN,	GPSR2_27,
-		GP_2_26_FN,	GPSR2_26,
-		GP_2_25_FN,	GPSR2_25,
-		GP_2_24_FN,	GPSR2_24,
-		GP_2_23_FN,	GPSR2_23,
-		GP_2_22_FN,	GPSR2_22,
-		GP_2_21_FN,	GPSR2_21,
-		GP_2_20_FN,	GPSR2_20,
-		GP_2_19_FN,	GPSR2_19,
-		GP_2_18_FN,	GPSR2_18,
-		GP_2_17_FN,	GPSR2_17,
-		GP_2_16_FN,	GPSR2_16,
-		GP_2_15_FN,	GPSR2_15,
-		GP_2_14_FN,	GPSR2_14,
-		GP_2_13_FN,	GPSR2_13,
-		GP_2_12_FN,	GPSR2_12,
-		GP_2_11_FN,	GPSR2_11,
-		GP_2_10_FN,	GPSR2_10,
-		GP_2_9_FN,	GPSR2_9,
-		GP_2_8_FN,	GPSR2_8,
-		GP_2_7_FN,	GPSR2_7,
-		GP_2_6_FN,	GPSR2_6,
-		GP_2_5_FN,	GPSR2_5,
-		GP_2_4_FN,	GPSR2_4,
-		GP_2_3_FN,	GPSR2_3,
-		GP_2_2_FN,	GPSR2_2,
-		GP_2_1_FN,	GPSR2_1,
-		GP_2_0_FN,	GPSR2_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_3_16_FN,	GPSR3_16,
-		GP_3_15_FN,	GPSR3_15,
-		GP_3_14_FN,	GPSR3_14,
-		GP_3_13_FN,	GPSR3_13,
-		GP_3_12_FN,	GPSR3_12,
-		GP_3_11_FN,	GPSR3_11,
-		GP_3_10_FN,	GPSR3_10,
-		GP_3_9_FN,	GPSR3_9,
-		GP_3_8_FN,	GPSR3_8,
-		GP_3_7_FN,	GPSR3_7,
-		GP_3_6_FN,	GPSR3_6,
-		GP_3_5_FN,	GPSR3_5,
-		GP_3_4_FN,	GPSR3_4,
-		GP_3_3_FN,	GPSR3_3,
-		GP_3_2_FN,	GPSR3_2,
-		GP_3_1_FN,	GPSR3_1,
-		GP_3_0_FN,	GPSR3_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_4_24_FN,	GPSR4_24,
-		GP_4_23_FN,	GPSR4_23,
-		GP_4_22_FN,	GPSR4_22,
-		GP_4_21_FN,	GPSR4_21,
-		GP_4_20_FN,	GPSR4_20,
-		GP_4_19_FN,	GPSR4_19,
-		GP_4_18_FN,	GPSR4_18,
-		GP_4_17_FN,	GPSR4_17,
-		GP_4_16_FN,	GPSR4_16,
-		GP_4_15_FN,	GPSR4_15,
-		GP_4_14_FN,	GPSR4_14,
-		GP_4_13_FN,	GPSR4_13,
-		GP_4_12_FN,	GPSR4_12,
-		GP_4_11_FN,	GPSR4_11,
-		GP_4_10_FN,	GPSR4_10,
-		GP_4_9_FN,	GPSR4_9,
-		GP_4_8_FN,	GPSR4_8,
-		GP_4_7_FN,	GPSR4_7,
-		GP_4_6_FN,	GPSR4_6,
-		GP_4_5_FN,	GPSR4_5,
-		GP_4_4_FN,	GPSR4_4,
-		GP_4_3_FN,	GPSR4_3,
-		GP_4_2_FN,	GPSR4_2,
-		GP_4_1_FN,	GPSR4_1,
-		GP_4_0_FN,	GPSR4_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_5_14_FN,	GPSR5_14,
-		GP_5_13_FN,	GPSR5_13,
-		GP_5_12_FN,	GPSR5_12,
-		GP_5_11_FN,	GPSR5_11,
-		GP_5_10_FN,	GPSR5_10,
-		GP_5_9_FN,	GPSR5_9,
-		GP_5_8_FN,	GPSR5_8,
-		GP_5_7_FN,	GPSR5_7,
-		GP_5_6_FN,	GPSR5_6,
-		GP_5_5_FN,	GPSR5_5,
-		GP_5_4_FN,	GPSR5_4,
-		GP_5_3_FN,	GPSR5_3,
-		GP_5_2_FN,	GPSR5_2,
-		GP_5_1_FN,	GPSR5_1,
-		GP_5_0_FN,	GPSR5_0, ))
-	},
-#undef F_
-#undef FM
-
-#define F_(x, y)	x,
-#define FM(x)		FN_##x,
-	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
-		IP0_31_28
-		IP0_27_24
-		IP0_23_20
-		IP0_19_16
-		IP0_15_12
-		IP0_11_8
-		IP0_7_4
-		IP0_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
-		IP1_31_28
-		IP1_27_24
-		IP1_23_20
-		IP1_19_16
-		IP1_15_12
-		IP1_11_8
-		IP1_7_4
-		IP1_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
-		IP2_31_28
-		IP2_27_24
-		IP2_23_20
-		IP2_19_16
-		IP2_15_12
-		IP2_11_8
-		IP2_7_4
-		IP2_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
-		IP3_31_28
-		IP3_27_24
-		IP3_23_20
-		IP3_19_16
-		IP3_15_12
-		IP3_11_8
-		IP3_7_4
-		IP3_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
-		IP4_31_28
-		IP4_27_24
-		IP4_23_20
-		IP4_19_16
-		IP4_15_12
-		IP4_11_8
-		IP4_7_4
-		IP4_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
-		IP5_31_28
-		IP5_27_24
-		IP5_23_20
-		IP5_19_16
-		IP5_15_12
-		IP5_11_8
-		IP5_7_4
-		IP5_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
-		IP6_31_28
-		IP6_27_24
-		IP6_23_20
-		IP6_19_16
-		IP6_15_12
-		IP6_11_8
-		IP6_7_4
-		IP6_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
-		IP7_31_28
-		IP7_27_24
-		IP7_23_20
-		IP7_19_16
-		IP7_15_12
-		IP7_11_8
-		IP7_7_4
-		IP7_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
-		IP8_31_28
-		IP8_27_24
-		IP8_23_20
-		IP8_19_16
-		IP8_15_12
-		IP8_11_8
-		IP8_7_4
-		IP8_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
-		IP9_31_28
-		IP9_27_24
-		IP9_23_20
-		IP9_19_16
-		IP9_15_12
-		IP9_11_8
-		IP9_7_4
-		IP9_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
-		IP10_31_28
-		IP10_27_24
-		IP10_23_20
-		IP10_19_16
-		IP10_15_12
-		IP10_11_8
-		IP10_7_4
-		IP10_3_0 ))
-	},
-#undef F_
-#undef FM
-
-#define F_(x, y)	x,
-#define FM(x)		FN_##x,
-	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
-			     GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
-				   1, 1, 1, 1, 1),
-			     GROUP(
-		/* RESERVED 31, 30, 29, 28 */
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 27, 26, 25, 24 */
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 23, 22, 21, 20 */
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 19, 18, 17, 16 */
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 15, 14, 13, 12 */
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		MOD_SEL0_11
-		MOD_SEL0_10
-		MOD_SEL0_9
-		MOD_SEL0_8
-		MOD_SEL0_7
-		MOD_SEL0_6
-		MOD_SEL0_5
-		MOD_SEL0_4
-		0, 0,
-		MOD_SEL0_2
-		MOD_SEL0_1
-		MOD_SEL0_0 ))
-	},
-	{ },
-};
-
-enum ioctrl_regs {
-	POCCTRL0,
-	POCCTRL1,
-	POCCTRL2,
-	POCCTRL3,
-	TDSELCTRL,
-};
-
-static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
-	[POCCTRL0] = { 0xe6060380, },
-	[POCCTRL1] = { 0xe6060384, },
-	[POCCTRL2] = { 0xe6060388, },
-	[POCCTRL3] = { 0xe606038c, },
-	[TDSELCTRL] = { 0xe60603c0, },
-	{ /* sentinel */ },
-};
-
-static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
-				   u32 *pocctrl)
-{
-	int bit = pin & 0x1f;
-
-	*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
-	if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
-		return bit;
-	else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
-		return bit + 22;
-
-	*pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
-	if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
-		return bit - 10;
-	if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) ||
-	    (pin >= RCAR_GP_PIN(3,  0) && pin <= RCAR_GP_PIN(3, 16)))
-		return bit + 7;
-
-	*pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
-	if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29))
-		return pin - 25;
-
-	return -EINVAL;
-}
-
-static const struct sh_pfc_soc_operations pinmux_ops = {
-	.pin_to_pocctrl = r8a77980_pin_to_pocctrl,
-};
-
-const struct sh_pfc_soc_info r8a77980_pinmux_info = {
-	.name = "r8a77980_pfc",
-	.ops = &pinmux_ops,
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups,
-	.nr_groups = ARRAY_SIZE(pinmux_groups),
-	.functions = pinmux_functions,
-	.nr_functions = ARRAY_SIZE(pinmux_functions),
-
-	.cfg_regs = pinmux_config_regs,
-	.ioctrl_regs = pinmux_ioctrl_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
deleted file mode 100644
index c926a59dd21c..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ /dev/null
@@ -1,5323 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * R8A77990 processor support - PFC hardware block.
- *
- * Copyright (C) 2018-2019 Renesas Electronics Corp.
- *
- * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
- *
- * R8A7796 processor support - PFC hardware block.
- *
- * Copyright (C) 2016-2017 Renesas Electronics Corp.
- */
-
-#include <linux/errno.h>
-#include <linux/kernel.h>
-
-#include "core.h"
-#include "sh_pfc.h"
-
-#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP_DOWN)
-
-#define CPU_ALL_GP(fn, sfx) \
-	PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
-	PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
-	PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
-	PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
-	PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
-	PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
-	PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
-	PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
-	PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
-	PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
-	PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \
-	PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
-	PORT_GP_CFG_1(6, 10, fn, sfx, CFG_FLAGS), \
-	PORT_GP_CFG_1(6, 11, fn, sfx, CFG_FLAGS), \
-	PORT_GP_CFG_1(6, 12, fn, sfx, CFG_FLAGS), \
-	PORT_GP_CFG_1(6, 13, fn, sfx, CFG_FLAGS), \
-	PORT_GP_CFG_1(6, 14, fn, sfx, CFG_FLAGS), \
-	PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \
-	PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \
-	PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS)
-
-#define CPU_ALL_NOGP(fn)						\
-	PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS),			\
-	PIN_NOGP_CFG(AVB_MDC, "AVB_MDC", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS),		\
-	PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(TCK, "TCK", fn, CFG_FLAGS),			\
-	PIN_NOGP_CFG(TDI, "TDI", fn, CFG_FLAGS),			\
-	PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS),			\
-	PIN_NOGP_CFG(TRST_N, "TRST_N", fn, CFG_FLAGS)
-
-/*
- * F_() : just information
- * FM() : macro for FN_xxx / xxx_MARK
- */
-
-/* GPSR0 */
-#define GPSR0_17	F_(SDA4,		IP7_27_24)
-#define GPSR0_16	F_(SCL4,		IP7_23_20)
-#define GPSR0_15	F_(D15,			IP7_19_16)
-#define GPSR0_14	F_(D14,			IP7_15_12)
-#define GPSR0_13	F_(D13,			IP7_11_8)
-#define GPSR0_12	F_(D12,			IP7_7_4)
-#define GPSR0_11	F_(D11,			IP7_3_0)
-#define GPSR0_10	F_(D10,			IP6_31_28)
-#define GPSR0_9		F_(D9,			IP6_27_24)
-#define GPSR0_8		F_(D8,			IP6_23_20)
-#define GPSR0_7		F_(D7,			IP6_19_16)
-#define GPSR0_6		F_(D6,			IP6_15_12)
-#define GPSR0_5		F_(D5,			IP6_11_8)
-#define GPSR0_4		F_(D4,			IP6_7_4)
-#define GPSR0_3		F_(D3,			IP6_3_0)
-#define GPSR0_2		F_(D2,			IP5_31_28)
-#define GPSR0_1		F_(D1,			IP5_27_24)
-#define GPSR0_0		F_(D0,			IP5_23_20)
-
-/* GPSR1 */
-#define GPSR1_22	F_(WE0_N,		IP5_19_16)
-#define GPSR1_21	F_(CS0_N,		IP5_15_12)
-#define GPSR1_20	FM(CLKOUT)
-#define GPSR1_19	F_(A19,			IP5_11_8)
-#define GPSR1_18	F_(A18,			IP5_7_4)
-#define GPSR1_17	F_(A17,			IP5_3_0)
-#define GPSR1_16	F_(A16,			IP4_31_28)
-#define GPSR1_15	F_(A15,			IP4_27_24)
-#define GPSR1_14	F_(A14,			IP4_23_20)
-#define GPSR1_13	F_(A13,			IP4_19_16)
-#define GPSR1_12	F_(A12,			IP4_15_12)
-#define GPSR1_11	F_(A11,			IP4_11_8)
-#define GPSR1_10	F_(A10,			IP4_7_4)
-#define GPSR1_9		F_(A9,			IP4_3_0)
-#define GPSR1_8		F_(A8,			IP3_31_28)
-#define GPSR1_7		F_(A7,			IP3_27_24)
-#define GPSR1_6		F_(A6,			IP3_23_20)
-#define GPSR1_5		F_(A5,			IP3_19_16)
-#define GPSR1_4		F_(A4,			IP3_15_12)
-#define GPSR1_3		F_(A3,			IP3_11_8)
-#define GPSR1_2		F_(A2,			IP3_7_4)
-#define GPSR1_1		F_(A1,			IP3_3_0)
-#define GPSR1_0		F_(A0,			IP2_31_28)
-
-/* GPSR2 */
-#define GPSR2_25	F_(EX_WAIT0,		IP2_27_24)
-#define GPSR2_24	F_(RD_WR_N,		IP2_23_20)
-#define GPSR2_23	F_(RD_N,		IP2_19_16)
-#define GPSR2_22	F_(BS_N,		IP2_15_12)
-#define GPSR2_21	FM(AVB_PHY_INT)
-#define GPSR2_20	F_(AVB_TXCREFCLK,	IP2_3_0)
-#define GPSR2_19	FM(AVB_RD3)
-#define GPSR2_18	F_(AVB_RD2,		IP1_31_28)
-#define GPSR2_17	F_(AVB_RD1,		IP1_27_24)
-#define GPSR2_16	F_(AVB_RD0,		IP1_23_20)
-#define GPSR2_15	FM(AVB_RXC)
-#define GPSR2_14	FM(AVB_RX_CTL)
-#define GPSR2_13	F_(RPC_RESET_N,		IP1_19_16)
-#define GPSR2_12	F_(RPC_INT_N,		IP1_15_12)
-#define GPSR2_11	F_(QSPI1_SSL,		IP1_11_8)
-#define GPSR2_10	F_(QSPI1_IO3,		IP1_7_4)
-#define GPSR2_9		F_(QSPI1_IO2,		IP1_3_0)
-#define GPSR2_8		F_(QSPI1_MISO_IO1,	IP0_31_28)
-#define GPSR2_7		F_(QSPI1_MOSI_IO0,	IP0_27_24)
-#define GPSR2_6		F_(QSPI1_SPCLK,		IP0_23_20)
-#define GPSR2_5		FM(QSPI0_SSL)
-#define GPSR2_4		F_(QSPI0_IO3,		IP0_19_16)
-#define GPSR2_3		F_(QSPI0_IO2,		IP0_15_12)
-#define GPSR2_2		F_(QSPI0_MISO_IO1,	IP0_11_8)
-#define GPSR2_1		F_(QSPI0_MOSI_IO0,	IP0_7_4)
-#define GPSR2_0		F_(QSPI0_SPCLK,		IP0_3_0)
-
-/* GPSR3 */
-#define GPSR3_15	F_(SD1_WP,		IP11_7_4)
-#define GPSR3_14	F_(SD1_CD,		IP11_3_0)
-#define GPSR3_13	F_(SD0_WP,		IP10_31_28)
-#define GPSR3_12	F_(SD0_CD,		IP10_27_24)
-#define GPSR3_11	F_(SD1_DAT3,		IP9_11_8)
-#define GPSR3_10	F_(SD1_DAT2,		IP9_7_4)
-#define GPSR3_9		F_(SD1_DAT1,		IP9_3_0)
-#define GPSR3_8		F_(SD1_DAT0,		IP8_31_28)
-#define GPSR3_7		F_(SD1_CMD,		IP8_27_24)
-#define GPSR3_6		F_(SD1_CLK,		IP8_23_20)
-#define GPSR3_5		F_(SD0_DAT3,		IP8_19_16)
-#define GPSR3_4		F_(SD0_DAT2,		IP8_15_12)
-#define GPSR3_3		F_(SD0_DAT1,		IP8_11_8)
-#define GPSR3_2		F_(SD0_DAT0,		IP8_7_4)
-#define GPSR3_1		F_(SD0_CMD,		IP8_3_0)
-#define GPSR3_0		F_(SD0_CLK,		IP7_31_28)
-
-/* GPSR4 */
-#define GPSR4_10	F_(SD3_DS,		IP10_23_20)
-#define GPSR4_9		F_(SD3_DAT7,		IP10_19_16)
-#define GPSR4_8		F_(SD3_DAT6,		IP10_15_12)
-#define GPSR4_7		F_(SD3_DAT5,		IP10_11_8)
-#define GPSR4_6		F_(SD3_DAT4,		IP10_7_4)
-#define GPSR4_5		F_(SD3_DAT3,		IP10_3_0)
-#define GPSR4_4		F_(SD3_DAT2,		IP9_31_28)
-#define GPSR4_3		F_(SD3_DAT1,		IP9_27_24)
-#define GPSR4_2		F_(SD3_DAT0,		IP9_23_20)
-#define GPSR4_1		F_(SD3_CMD,		IP9_19_16)
-#define GPSR4_0		F_(SD3_CLK,		IP9_15_12)
-
-/* GPSR5 */
-#define GPSR5_19	F_(MLB_DAT,		IP13_23_20)
-#define GPSR5_18	F_(MLB_SIG,		IP13_19_16)
-#define GPSR5_17	F_(MLB_CLK,		IP13_15_12)
-#define GPSR5_16	F_(SSI_SDATA9,		IP13_11_8)
-#define GPSR5_15	F_(MSIOF0_SS2,		IP13_7_4)
-#define GPSR5_14	F_(MSIOF0_SS1,		IP13_3_0)
-#define GPSR5_13	F_(MSIOF0_SYNC,		IP12_31_28)
-#define GPSR5_12	F_(MSIOF0_TXD,		IP12_27_24)
-#define GPSR5_11	F_(MSIOF0_RXD,		IP12_23_20)
-#define GPSR5_10	F_(MSIOF0_SCK,		IP12_19_16)
-#define GPSR5_9		F_(RX2_A,		IP12_15_12)
-#define GPSR5_8		F_(TX2_A,		IP12_11_8)
-#define GPSR5_7		F_(SCK2_A,		IP12_7_4)
-#define GPSR5_6		F_(TX1,			IP12_3_0)
-#define GPSR5_5		F_(RX1,			IP11_31_28)
-#define GPSR5_4		F_(RTS0_N_A,		IP11_23_20)
-#define GPSR5_3		F_(CTS0_N_A,		IP11_19_16)
-#define GPSR5_2		F_(TX0_A,		IP11_15_12)
-#define GPSR5_1		F_(RX0_A,		IP11_11_8)
-#define GPSR5_0		F_(SCK0_A,		IP11_27_24)
-
-/* GPSR6 */
-#define GPSR6_17	F_(USB30_PWEN,		IP15_27_24)
-#define GPSR6_16	F_(SSI_SDATA6,		IP15_19_16)
-#define GPSR6_15	F_(SSI_WS6,		IP15_15_12)
-#define GPSR6_14	F_(SSI_SCK6,		IP15_11_8)
-#define GPSR6_13	F_(SSI_SDATA5,		IP15_7_4)
-#define GPSR6_12	F_(SSI_WS5,		IP15_3_0)
-#define GPSR6_11	F_(SSI_SCK5,		IP14_31_28)
-#define GPSR6_10	F_(SSI_SDATA4,		IP14_27_24)
-#define GPSR6_9		F_(USB30_OVC,		IP15_31_28)
-#define GPSR6_8		F_(AUDIO_CLKA,		IP15_23_20)
-#define GPSR6_7		F_(SSI_SDATA3,		IP14_23_20)
-#define GPSR6_6		F_(SSI_WS349,		IP14_19_16)
-#define GPSR6_5		F_(SSI_SCK349,		IP14_15_12)
-#define GPSR6_4		F_(SSI_SDATA2,		IP14_11_8)
-#define GPSR6_3		F_(SSI_SDATA1,		IP14_7_4)
-#define GPSR6_2		F_(SSI_SDATA0,		IP14_3_0)
-#define GPSR6_1		F_(SSI_WS01239,		IP13_31_28)
-#define GPSR6_0		F_(SSI_SCK01239,	IP13_27_24)
-
-/* IPSRx */		/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */		/* 6 */		/* 7 */		/* 8 */		/* 9 - F */
-#define IP0_3_0		FM(QSPI0_SPCLK)		FM(HSCK4_A)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_7_4		FM(QSPI0_MOSI_IO0)	FM(HCTS4_N_A)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_11_8	FM(QSPI0_MISO_IO1)	FM(HRTS4_N_A)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_15_12	FM(QSPI0_IO2)		FM(HTX4_A)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_19_16	FM(QSPI0_IO3)		FM(HRX4_A)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_23_20	FM(QSPI1_SPCLK)		FM(RIF2_CLK_A)		FM(HSCK4_B)		FM(VI4_DATA0_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_27_24	FM(QSPI1_MOSI_IO0)	FM(RIF2_SYNC_A)		FM(HTX4_B)		FM(VI4_DATA1_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_31_28	FM(QSPI1_MISO_IO1)	FM(RIF2_D0_A)		FM(HRX4_B)		FM(VI4_DATA2_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_3_0		FM(QSPI1_IO2)		FM(RIF2_D1_A)		FM(HTX3_C)		FM(VI4_DATA3_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_7_4		FM(QSPI1_IO3)		FM(RIF3_CLK_A)		FM(HRX3_C)		FM(VI4_DATA4_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_11_8	FM(QSPI1_SSL)		FM(RIF3_SYNC_A)		FM(HSCK3_C)		FM(VI4_DATA5_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_15_12	FM(RPC_INT_N)		FM(RIF3_D0_A)		FM(HCTS3_N_C)		FM(VI4_DATA6_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_19_16	FM(RPC_RESET_N)		FM(RIF3_D1_A)		FM(HRTS3_N_C)		FM(VI4_DATA7_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_23_20	FM(AVB_RD0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_27_24	FM(AVB_RD1)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_31_28	FM(AVB_RD2)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_3_0		FM(AVB_TXCREFCLK)	F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_7_4		FM(AVB_MDIO)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_11_8	FM(AVB_MDC)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_15_12	FM(BS_N)		FM(PWM0_A)		FM(AVB_MAGIC)		FM(VI4_CLK)		F_(0, 0)		FM(TX3_C)	F_(0, 0)	FM(VI5_CLK_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_19_16	FM(RD_N)		FM(PWM1_A)		FM(AVB_LINK)		FM(VI4_FIELD)		F_(0, 0)		FM(RX3_C)	FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_23_20	FM(RD_WR_N)		FM(SCL7_A)		FM(AVB_AVTP_MATCH)	FM(VI4_VSYNC_N)		FM(TX5_B)		FM(SCK3_C)	FM(PWM5_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_27_24	FM(EX_WAIT0)		FM(SDA7_A)		FM(AVB_AVTP_CAPTURE)	FM(VI4_HSYNC_N)		FM(RX5_B)		FM(PWM6_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_31_28	FM(A0)			FM(IRQ0)		FM(PWM2_A)		FM(MSIOF3_SS1_B)	FM(VI5_CLK_A)		FM(DU_CDE)	FM(HRX3_D)	FM(IERX)	FM(QSTB_QHE)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_3_0		FM(A1)			FM(IRQ1)		FM(PWM3_A)		FM(DU_DOTCLKIN1)	FM(VI5_DATA0_A)		FM(DU_DISP_CDE) FM(SDA6_B)	FM(IETX)	FM(QCPV_QDE)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_7_4		FM(A2)			FM(IRQ2)		FM(AVB_AVTP_PPS)	FM(VI4_CLKENB)		FM(VI5_DATA1_A)		FM(DU_DISP)	FM(SCL6_B)	F_(0, 0)	FM(QSTVB_QVE)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_11_8	FM(A3)			FM(CTS4_N_A)		FM(PWM4_A)		FM(VI4_DATA12)		F_(0, 0)		FM(DU_DOTCLKOUT0) FM(HTX3_D)	FM(IECLK)	FM(LCDOUT12)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_15_12	FM(A4)			FM(RTS4_N_A)		FM(MSIOF3_SYNC_B)	FM(VI4_DATA8)		FM(PWM2_B)		FM(DU_DG4)	FM(RIF2_CLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_19_16	FM(A5)			FM(SCK4_A)		FM(MSIOF3_SCK_B)	FM(VI4_DATA9)		FM(PWM3_B)		F_(0, 0)	FM(RIF2_SYNC_B)	F_(0, 0)	FM(QPOLA)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_23_20	FM(A6)			FM(RX4_A)		FM(MSIOF3_RXD_B)	FM(VI4_DATA10)		F_(0, 0)		F_(0, 0)	FM(RIF2_D0_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_27_24	FM(A7)			FM(TX4_A)		FM(MSIOF3_TXD_B)	FM(VI4_DATA11)		F_(0, 0)		F_(0, 0)	FM(RIF2_D1_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_31_28	FM(A8)			FM(SDA6_A)		FM(RX3_B)		FM(HRX4_C)		FM(VI5_HSYNC_N_A)	FM(DU_HSYNC)	FM(VI4_DATA0_B)	F_(0, 0)	FM(QSTH_QHS)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IPSRx */		/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */		/* 6 */		/* 7 */		/* 8 */		/* 9 - F */
-#define IP4_3_0		FM(A9)			FM(TX5_A)		FM(IRQ3)		FM(VI4_DATA16)		FM(VI5_VSYNC_N_A)	FM(DU_DG7)	F_(0, 0)	F_(0, 0)	FM(LCDOUT15)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_7_4		FM(A10)			FM(IRQ4)		FM(MSIOF2_SYNC_B)	FM(VI4_DATA13)		FM(VI5_FIELD_A)		FM(DU_DG5)	FM(FSCLKST2_N_B) F_(0, 0)	FM(LCDOUT13)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_11_8	FM(A11)			FM(SCL6_A)		FM(TX3_B)		FM(HTX4_C)		F_(0, 0)		FM(DU_VSYNC)	FM(VI4_DATA1_B)	F_(0, 0)	FM(QSTVA_QVS)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_15_12	FM(A12)			FM(RX5_A)		FM(MSIOF2_SS2_B)	FM(VI4_DATA17)		FM(VI5_DATA3_A)		FM(DU_DG6)	F_(0, 0)	F_(0, 0)	FM(LCDOUT14)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_19_16	FM(A13)			FM(SCK5_A)		FM(MSIOF2_SCK_B)	FM(VI4_DATA14)		FM(HRX4_D)		FM(DU_DB2)	F_(0, 0)	F_(0, 0)	FM(LCDOUT2)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_23_20	FM(A14)			FM(MSIOF1_SS1)		FM(MSIOF2_RXD_B)	FM(VI4_DATA15)		FM(HTX4_D)		FM(DU_DB3)	F_(0, 0)	F_(0, 0)	FM(LCDOUT3)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_27_24	FM(A15)			FM(MSIOF1_SS2)		FM(MSIOF2_TXD_B)	FM(VI4_DATA18)		FM(VI5_DATA4_A)		FM(DU_DB4)	F_(0, 0)	F_(0, 0)	FM(LCDOUT4)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_31_28	FM(A16)			FM(MSIOF1_SYNC)		FM(MSIOF2_SS1_B)	FM(VI4_DATA19)		FM(VI5_DATA5_A)		FM(DU_DB5)	F_(0, 0)	F_(0, 0)	FM(LCDOUT5)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_3_0		FM(A17)			FM(MSIOF1_RXD)		F_(0, 0)		FM(VI4_DATA20)		FM(VI5_DATA6_A)		FM(DU_DB6)	F_(0, 0)	F_(0, 0)	FM(LCDOUT6)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_7_4		FM(A18)			FM(MSIOF1_TXD)		F_(0, 0)		FM(VI4_DATA21)		FM(VI5_DATA7_A)		FM(DU_DB0)	F_(0, 0)	FM(HRX4_E)	FM(LCDOUT0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_11_8	FM(A19)			FM(MSIOF1_SCK)		F_(0, 0)		FM(VI4_DATA22)		FM(VI5_DATA2_A)		FM(DU_DB1)	F_(0, 0)	FM(HTX4_E)	FM(LCDOUT1)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_15_12	FM(CS0_N)		FM(SCL5)		F_(0, 0)		F_(0, 0)		F_(0, 0)		FM(DU_DR0)	FM(VI4_DATA2_B)	F_(0, 0)	FM(LCDOUT16)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_19_16	FM(WE0_N)		FM(SDA5)		F_(0, 0)		F_(0, 0)		F_(0, 0)		FM(DU_DR1)	FM(VI4_DATA3_B)	F_(0, 0)	FM(LCDOUT17)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_23_20	FM(D0)			FM(MSIOF3_SCK_A)	F_(0, 0)		F_(0, 0)		F_(0, 0)		FM(DU_DR2)	FM(CTS4_N_C)	F_(0, 0)	FM(LCDOUT18)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_27_24	FM(D1)			FM(MSIOF3_SYNC_A)	FM(SCK3_A)		FM(VI4_DATA23)		FM(VI5_CLKENB_A)	FM(DU_DB7)	FM(RTS4_N_C)	F_(0, 0)	FM(LCDOUT7)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_31_28	FM(D2)			FM(MSIOF3_RXD_A)	FM(RX5_C)		F_(0, 0)		FM(VI5_DATA14_A)	FM(DU_DR3)	FM(RX4_C)	F_(0, 0)	FM(LCDOUT19)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_3_0		FM(D3)			FM(MSIOF3_TXD_A)	FM(TX5_C)		F_(0, 0)		FM(VI5_DATA15_A)	FM(DU_DR4)	FM(TX4_C)	F_(0, 0)	FM(LCDOUT20)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_7_4		FM(D4)			FM(CANFD1_TX)		FM(HSCK3_B)		FM(CAN1_TX)		FM(RTS3_N_A)		FM(MSIOF3_SS2_A) F_(0, 0)	FM(VI5_DATA1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_11_8	FM(D5)			FM(RX3_A)		FM(HRX3_B)		F_(0, 0)		F_(0, 0)		FM(DU_DR5)	FM(VI4_DATA4_B)	F_(0, 0)	FM(LCDOUT21)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_15_12	FM(D6)			FM(TX3_A)		FM(HTX3_B)		F_(0, 0)		F_(0, 0)		FM(DU_DR6)	FM(VI4_DATA5_B)	F_(0, 0)	FM(LCDOUT22)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_19_16	FM(D7)			FM(CANFD1_RX)		FM(IRQ5)		FM(CAN1_RX)		FM(CTS3_N_A)		F_(0, 0)	F_(0, 0)	FM(VI5_DATA2_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_23_20	FM(D8)			FM(MSIOF2_SCK_A)	FM(SCK4_B)		F_(0, 0)		FM(VI5_DATA12_A)	FM(DU_DR7)	FM(RIF3_CLK_B)	FM(HCTS3_N_E)	FM(LCDOUT23)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_27_24	FM(D9)			FM(MSIOF2_SYNC_A)	F_(0, 0)		F_(0, 0)		FM(VI5_DATA10_A)	FM(DU_DG0)	FM(RIF3_SYNC_B)	FM(HRX3_E)	FM(LCDOUT8)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_31_28	FM(D10)			FM(MSIOF2_RXD_A)	F_(0, 0)		F_(0, 0)		FM(VI5_DATA13_A)	FM(DU_DG1)	FM(RIF3_D0_B)	FM(HTX3_E)	FM(LCDOUT9)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_3_0		FM(D11)			FM(MSIOF2_TXD_A)	F_(0, 0)		F_(0, 0)		FM(VI5_DATA11_A)	FM(DU_DG2)	FM(RIF3_D1_B)	FM(HRTS3_N_E)	FM(LCDOUT10)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_7_4		FM(D12)			FM(CANFD0_TX)		FM(TX4_B)		FM(CAN0_TX)		FM(VI5_DATA8_A)		F_(0, 0)	F_(0, 0)	FM(VI5_DATA3_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_11_8	FM(D13)			FM(CANFD0_RX)		FM(RX4_B)		FM(CAN0_RX)		FM(VI5_DATA9_A)		FM(SCL7_B)	F_(0, 0)	FM(VI5_DATA4_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_15_12	FM(D14)			FM(CAN_CLK)		FM(HRX3_A)		FM(MSIOF2_SS2_A)	F_(0, 0)		FM(SDA7_B)	F_(0, 0)	FM(VI5_DATA5_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_19_16	FM(D15)			FM(MSIOF2_SS1_A)	FM(HTX3_A)		FM(MSIOF3_SS1_A)	F_(0, 0)		FM(DU_DG3)	F_(0, 0)	F_(0, 0)	FM(LCDOUT11)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_23_20	FM(SCL4)		FM(CS1_N_A26)		F_(0, 0)		F_(0, 0)		F_(0, 0)		FM(DU_DOTCLKIN0) FM(VI4_DATA6_B) FM(VI5_DATA6_B) FM(QCLK)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_27_24	FM(SDA4)		FM(WE1_N)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	FM(VI4_DATA7_B)	FM(VI5_DATA7_B)	FM(QPOLB)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_31_28	FM(SD0_CLK)		FM(NFDATA8)		FM(SCL1_C)		FM(HSCK1_B)		FM(SDA2_E)		FM(FMCLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IPSRx */		/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */		/* 6 */		/* 7 */		/* 8 */		/* 9 - F */
-#define IP8_3_0		FM(SD0_CMD)		FM(NFDATA9)		F_(0, 0)		FM(HRX1_B)		F_(0, 0)		FM(SPEEDIN_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_7_4		FM(SD0_DAT0)		FM(NFDATA10)		F_(0, 0)		FM(HTX1_B)		F_(0, 0)		FM(REMOCON_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_11_8	FM(SD0_DAT1)		FM(NFDATA11)		FM(SDA2_C)		FM(HCTS1_N_B)		F_(0, 0)		FM(FMIN_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_15_12	FM(SD0_DAT2)		FM(NFDATA12)		FM(SCL2_C)		FM(HRTS1_N_B)		F_(0, 0)		FM(BPFCLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_19_16	FM(SD0_DAT3)		FM(NFDATA13)		FM(SDA1_C)		FM(SCL2_E)		FM(SPEEDIN_C)		FM(REMOCON_C)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_23_20	FM(SD1_CLK)		FM(NFDATA14_B)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_27_24	FM(SD1_CMD)		FM(NFDATA15_B)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_31_28	FM(SD1_DAT0)		FM(NFWP_N_B)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_3_0		FM(SD1_DAT1)		FM(NFCE_N_B)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_7_4		FM(SD1_DAT2)		FM(NFALE_B)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_11_8	FM(SD1_DAT3)		FM(NFRB_N_B)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_15_12	FM(SD3_CLK)		FM(NFWE_N)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_19_16	FM(SD3_CMD)		FM(NFRE_N)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_23_20	FM(SD3_DAT0)		FM(NFDATA0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_27_24	FM(SD3_DAT1)		FM(NFDATA1)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_31_28	FM(SD3_DAT2)		FM(NFDATA2)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_3_0	FM(SD3_DAT3)		FM(NFDATA3)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_7_4	FM(SD3_DAT4)		FM(NFDATA4)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_11_8	FM(SD3_DAT5)		FM(NFDATA5)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_15_12	FM(SD3_DAT6)		FM(NFDATA6)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_19_16	FM(SD3_DAT7)		FM(NFDATA7)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_23_20	FM(SD3_DS)		FM(NFCLE)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_27_24	FM(SD0_CD)		FM(NFALE_A)		FM(SD3_CD)		FM(RIF0_CLK_B)		FM(SCL2_B)		FM(TCLK1_A)	FM(SSI_SCK2_B)	FM(TS_SCK0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_31_28	FM(SD0_WP)		FM(NFRB_N_A)		FM(SD3_WP)		FM(RIF0_D0_B)		FM(SDA2_B)		FM(TCLK2_A)	FM(SSI_WS2_B)	FM(TS_SDAT0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_3_0	FM(SD1_CD)		FM(NFCE_N_A)		FM(SSI_SCK1)		FM(RIF0_D1_B)		F_(0, 0)		F_(0, 0)	F_(0, 0)	FM(TS_SDEN0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_7_4	FM(SD1_WP)		FM(NFWP_N_A)		FM(SSI_WS1)		FM(RIF0_SYNC_B)		F_(0, 0)		F_(0, 0)	F_(0, 0)	FM(TS_SPSYNC0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_11_8	FM(RX0_A)		FM(HRX1_A)		FM(SSI_SCK2_A)		FM(RIF1_SYNC)		F_(0, 0)		F_(0, 0)	F_(0, 0)	FM(TS_SCK1)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_15_12	FM(TX0_A)		FM(HTX1_A)		FM(SSI_WS2_A)		FM(RIF1_D0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	FM(TS_SDAT1)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_19_16	FM(CTS0_N_A)		FM(NFDATA14_A)		FM(AUDIO_CLKOUT_A)	FM(RIF1_D1)		FM(SCIF_CLK_A)		FM(FMCLK_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_23_20	FM(RTS0_N_A)		FM(NFDATA15_A)		FM(AUDIO_CLKOUT1_A)	FM(RIF1_CLK)		FM(SCL2_A)		FM(FMIN_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_27_24	FM(SCK0_A)		FM(HSCK1_A)		FM(USB3HS0_ID)		FM(RTS1_N)		FM(SDA2_A)		FM(FMCLK_C)	F_(0, 0)	F_(0, 0)	FM(USB0_ID)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_31_28	FM(RX1)			FM(HRX2_B)		FM(SSI_SCK9_B)		FM(AUDIO_CLKOUT1_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IPSRx */		/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */		/* 6 */		/* 7 */		/* 8 */		/* 9 - F */
-#define IP12_3_0	FM(TX1)			FM(HTX2_B)		FM(SSI_WS9_B)		FM(AUDIO_CLKOUT3_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_7_4	FM(SCK2_A)		FM(HSCK0_A)		FM(AUDIO_CLKB_A)	FM(CTS1_N)		FM(RIF0_CLK_A)		FM(REMOCON_A)	FM(SCIF_CLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_11_8	FM(TX2_A)		FM(HRX0_A)		FM(AUDIO_CLKOUT2_A)	F_(0, 0)		FM(SCL1_A)		F_(0, 0)	FM(FSO_CFE_0_N_A) FM(TS_SDEN1)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_15_12	FM(RX2_A)		FM(HTX0_A)		FM(AUDIO_CLKOUT3_A)	F_(0, 0)		FM(SDA1_A)		F_(0, 0)	FM(FSO_CFE_1_N_A) FM(TS_SPSYNC1) F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_19_16	FM(MSIOF0_SCK)		F_(0, 0)		FM(SSI_SCK78)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_23_20	FM(MSIOF0_RXD)		F_(0, 0)		FM(SSI_WS78)		F_(0, 0)		F_(0, 0)		FM(TX2_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_27_24	FM(MSIOF0_TXD)		F_(0, 0)		FM(SSI_SDATA7)		F_(0, 0)		F_(0, 0)		FM(RX2_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_31_28	FM(MSIOF0_SYNC)		FM(AUDIO_CLKOUT_B)	FM(SSI_SDATA8)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_3_0	FM(MSIOF0_SS1)		FM(HRX2_A)		FM(SSI_SCK4)		FM(HCTS0_N_A)		FM(BPFCLK_C)		FM(SPEEDIN_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_7_4	FM(MSIOF0_SS2)		FM(HTX2_A)		FM(SSI_WS4)		FM(HRTS0_N_A)		FM(FMIN_C)		FM(BPFCLK_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_11_8	FM(SSI_SDATA9)		F_(0, 0)		FM(AUDIO_CLKC_A)	FM(SCK1)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_15_12	FM(MLB_CLK)		FM(RX0_B)		F_(0, 0)		FM(RIF0_D0_A)		FM(SCL1_B)		FM(TCLK1_B)	F_(0, 0)	F_(0, 0)	FM(SIM0_RST_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_19_16	FM(MLB_SIG)		FM(SCK0_B)		F_(0, 0)		FM(RIF0_D1_A)		FM(SDA1_B)		FM(TCLK2_B)	F_(0, 0)	F_(0, 0)	FM(SIM0_D_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_23_20	FM(MLB_DAT)		FM(TX0_B)		F_(0, 0)		FM(RIF0_SYNC_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(SIM0_CLK_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_27_24	FM(SSI_SCK01239)	F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_31_28	FM(SSI_WS01239)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_3_0	FM(SSI_SDATA0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_7_4	FM(SSI_SDATA1)		FM(AUDIO_CLKC_B)	F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	FM(PWM0_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_11_8	FM(SSI_SDATA2)		FM(AUDIO_CLKOUT2_B)	FM(SSI_SCK9_A)		F_(0, 0)		F_(0, 0)		F_(0, 0)	FM(PWM1_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_15_12	FM(SSI_SCK349)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	FM(PWM2_C)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_19_16	FM(SSI_WS349)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	FM(PWM3_C)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_23_20	FM(SSI_SDATA3)		FM(AUDIO_CLKOUT1_C)	FM(AUDIO_CLKB_B)	F_(0, 0)		F_(0, 0)		F_(0, 0)	FM(PWM4_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_27_24	FM(SSI_SDATA4)		F_(0, 0)		FM(SSI_WS9_A)		F_(0, 0)		F_(0, 0)		F_(0, 0)	FM(PWM5_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP14_31_28	FM(SSI_SCK5)		FM(HRX0_B)		F_(0, 0)		FM(USB0_PWEN_B)		FM(SCL2_D)		F_(0, 0)	FM(PWM6_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_3_0	FM(SSI_WS5)		FM(HTX0_B)		F_(0, 0)		FM(USB0_OVC_B)		FM(SDA2_D)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_7_4	FM(SSI_SDATA5)		FM(HSCK0_B)		FM(AUDIO_CLKB_C)	FM(TPU0TO0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_11_8	FM(SSI_SCK6)		FM(HSCK2_A)		FM(AUDIO_CLKC_C)	FM(TPU0TO1)		F_(0, 0)		F_(0, 0)	FM(FSO_CFE_0_N_B) F_(0, 0)	FM(SIM0_RST_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_15_12	FM(SSI_WS6)		FM(HCTS2_N_A)		FM(AUDIO_CLKOUT2_C)	FM(TPU0TO2)		FM(SDA1_D)		F_(0, 0)	FM(FSO_CFE_1_N_B) F_(0, 0)	FM(SIM0_D_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_19_16	FM(SSI_SDATA6)		FM(HRTS2_N_A)		FM(AUDIO_CLKOUT3_C)	FM(TPU0TO3)		FM(SCL1_D)		F_(0, 0)	FM(FSO_TOE_N_B)	F_(0, 0)	FM(SIM0_CLK_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_23_20	FM(AUDIO_CLKA)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_27_24	FM(USB30_PWEN)		FM(USB0_PWEN_A)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP15_31_28	FM(USB30_OVC)		FM(USB0_OVC_A)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	FM(FSO_TOE_N_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-#define PINMUX_GPSR	\
-\
-													 \
-													 \
-													 \
-													 \
-													 \
-													 \
-				GPSR2_25								 \
-				GPSR2_24								 \
-				GPSR2_23								 \
-		GPSR1_22	GPSR2_22								 \
-		GPSR1_21	GPSR2_21								 \
-		GPSR1_20	GPSR2_20								 \
-		GPSR1_19	GPSR2_19					GPSR5_19		 \
-		GPSR1_18	GPSR2_18					GPSR5_18		 \
-GPSR0_17	GPSR1_17	GPSR2_17					GPSR5_17	GPSR6_17 \
-GPSR0_16	GPSR1_16	GPSR2_16					GPSR5_16	GPSR6_16 \
-GPSR0_15	GPSR1_15	GPSR2_15	GPSR3_15			GPSR5_15	GPSR6_15 \
-GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14			GPSR5_14	GPSR6_14 \
-GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13			GPSR5_13	GPSR6_13 \
-GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12			GPSR5_12	GPSR6_12 \
-GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11			GPSR5_11	GPSR6_11 \
-GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10	GPSR6_10 \
-GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9		GPSR6_9 \
-GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8		GPSR6_8 \
-GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7		GPSR6_7 \
-GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6		GPSR6_6 \
-GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5		GPSR6_5 \
-GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4		GPSR6_4 \
-GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3		GPSR6_3 \
-GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2		GPSR6_2 \
-GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1		GPSR6_1 \
-GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0		GPSR6_0
-
-#define PINMUX_IPSR				\
-\
-FM(IP0_3_0)	IP0_3_0		FM(IP1_3_0)	IP1_3_0		FM(IP2_3_0)	IP2_3_0		FM(IP3_3_0)	IP3_3_0 \
-FM(IP0_7_4)	IP0_7_4		FM(IP1_7_4)	IP1_7_4		FM(IP2_7_4)	IP2_7_4		FM(IP3_7_4)	IP3_7_4 \
-FM(IP0_11_8)	IP0_11_8	FM(IP1_11_8)	IP1_11_8	FM(IP2_11_8)	IP2_11_8	FM(IP3_11_8)	IP3_11_8 \
-FM(IP0_15_12)	IP0_15_12	FM(IP1_15_12)	IP1_15_12	FM(IP2_15_12)	IP2_15_12	FM(IP3_15_12)	IP3_15_12 \
-FM(IP0_19_16)	IP0_19_16	FM(IP1_19_16)	IP1_19_16	FM(IP2_19_16)	IP2_19_16	FM(IP3_19_16)	IP3_19_16 \
-FM(IP0_23_20)	IP0_23_20	FM(IP1_23_20)	IP1_23_20	FM(IP2_23_20)	IP2_23_20	FM(IP3_23_20)	IP3_23_20 \
-FM(IP0_27_24)	IP0_27_24	FM(IP1_27_24)	IP1_27_24	FM(IP2_27_24)	IP2_27_24	FM(IP3_27_24)	IP3_27_24 \
-FM(IP0_31_28)	IP0_31_28	FM(IP1_31_28)	IP1_31_28	FM(IP2_31_28)	IP2_31_28	FM(IP3_31_28)	IP3_31_28 \
-\
-FM(IP4_3_0)	IP4_3_0		FM(IP5_3_0)	IP5_3_0		FM(IP6_3_0)	IP6_3_0		FM(IP7_3_0)	IP7_3_0 \
-FM(IP4_7_4)	IP4_7_4		FM(IP5_7_4)	IP5_7_4		FM(IP6_7_4)	IP6_7_4		FM(IP7_7_4)	IP7_7_4 \
-FM(IP4_11_8)	IP4_11_8	FM(IP5_11_8)	IP5_11_8	FM(IP6_11_8)	IP6_11_8	FM(IP7_11_8)	IP7_11_8 \
-FM(IP4_15_12)	IP4_15_12	FM(IP5_15_12)	IP5_15_12	FM(IP6_15_12)	IP6_15_12	FM(IP7_15_12)	IP7_15_12 \
-FM(IP4_19_16)	IP4_19_16	FM(IP5_19_16)	IP5_19_16	FM(IP6_19_16)	IP6_19_16	FM(IP7_19_16)	IP7_19_16 \
-FM(IP4_23_20)	IP4_23_20	FM(IP5_23_20)	IP5_23_20	FM(IP6_23_20)	IP6_23_20	FM(IP7_23_20)	IP7_23_20 \
-FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
-FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
-\
-FM(IP8_3_0)	IP8_3_0		FM(IP9_3_0)	IP9_3_0		FM(IP10_3_0)	IP10_3_0	FM(IP11_3_0)	IP11_3_0 \
-FM(IP8_7_4)	IP8_7_4		FM(IP9_7_4)	IP9_7_4		FM(IP10_7_4)	IP10_7_4	FM(IP11_7_4)	IP11_7_4 \
-FM(IP8_11_8)	IP8_11_8	FM(IP9_11_8)	IP9_11_8	FM(IP10_11_8)	IP10_11_8	FM(IP11_11_8)	IP11_11_8 \
-FM(IP8_15_12)	IP8_15_12	FM(IP9_15_12)	IP9_15_12	FM(IP10_15_12)	IP10_15_12	FM(IP11_15_12)	IP11_15_12 \
-FM(IP8_19_16)	IP8_19_16	FM(IP9_19_16)	IP9_19_16	FM(IP10_19_16)	IP10_19_16	FM(IP11_19_16)	IP11_19_16 \
-FM(IP8_23_20)	IP8_23_20	FM(IP9_23_20)	IP9_23_20	FM(IP10_23_20)	IP10_23_20	FM(IP11_23_20)	IP11_23_20 \
-FM(IP8_27_24)	IP8_27_24	FM(IP9_27_24)	IP9_27_24	FM(IP10_27_24)	IP10_27_24	FM(IP11_27_24)	IP11_27_24 \
-FM(IP8_31_28)	IP8_31_28	FM(IP9_31_28)	IP9_31_28	FM(IP10_31_28)	IP10_31_28	FM(IP11_31_28)	IP11_31_28 \
-\
-FM(IP12_3_0)	IP12_3_0	FM(IP13_3_0)	IP13_3_0	FM(IP14_3_0)	IP14_3_0	FM(IP15_3_0)	IP15_3_0 \
-FM(IP12_7_4)	IP12_7_4	FM(IP13_7_4)	IP13_7_4	FM(IP14_7_4)	IP14_7_4	FM(IP15_7_4)	IP15_7_4 \
-FM(IP12_11_8)	IP12_11_8	FM(IP13_11_8)	IP13_11_8	FM(IP14_11_8)	IP14_11_8	FM(IP15_11_8)	IP15_11_8 \
-FM(IP12_15_12)	IP12_15_12	FM(IP13_15_12)	IP13_15_12	FM(IP14_15_12)	IP14_15_12	FM(IP15_15_12)	IP15_15_12 \
-FM(IP12_19_16)	IP12_19_16	FM(IP13_19_16)	IP13_19_16	FM(IP14_19_16)	IP14_19_16	FM(IP15_19_16)	IP15_19_16 \
-FM(IP12_23_20)	IP12_23_20	FM(IP13_23_20)	IP13_23_20	FM(IP14_23_20)	IP14_23_20	FM(IP15_23_20)	IP15_23_20 \
-FM(IP12_27_24)	IP12_27_24	FM(IP13_27_24)	IP13_27_24	FM(IP14_27_24)	IP14_27_24	FM(IP15_27_24)	IP15_27_24 \
-FM(IP12_31_28)	IP12_31_28	FM(IP13_31_28)	IP13_31_28	FM(IP14_31_28)	IP14_31_28	FM(IP15_31_28)	IP15_31_28
-
-/* The bit numbering in MOD_SEL fields is reversed */
-#define REV4(f0, f1, f2, f3)			f0 f2 f1 f3
-#define REV8(f0, f1, f2, f3, f4, f5, f6, f7)	f0 f4 f2 f6 f1 f5 f3 f7
-
-/* MOD_SEL0 */			/* 0 */				/* 1 */				/* 2 */				/* 3 */			/* 4 */			/* 5 */		/* 6 */		/* 7 */
-#define MOD_SEL0_30_29	   REV4(FM(SEL_ADGB_0),			FM(SEL_ADGB_1),			FM(SEL_ADGB_2),			F_(0, 0))
-#define MOD_SEL0_28		FM(SEL_DRIF0_0)			FM(SEL_DRIF0_1)
-#define MOD_SEL0_27_26	   REV4(FM(SEL_FM_0),			FM(SEL_FM_1),			FM(SEL_FM_2),			F_(0, 0))
-#define MOD_SEL0_25		FM(SEL_FSO_0)			FM(SEL_FSO_1)
-#define MOD_SEL0_24		FM(SEL_HSCIF0_0)		FM(SEL_HSCIF0_1)
-#define MOD_SEL0_23		FM(SEL_HSCIF1_0)		FM(SEL_HSCIF1_1)
-#define MOD_SEL0_22		FM(SEL_HSCIF2_0)		FM(SEL_HSCIF2_1)
-#define MOD_SEL0_21_20	   REV4(FM(SEL_I2C1_0),			FM(SEL_I2C1_1),			FM(SEL_I2C1_2),			FM(SEL_I2C1_3))
-#define MOD_SEL0_19_18_17  REV8(FM(SEL_I2C2_0),			FM(SEL_I2C2_1),			FM(SEL_I2C2_2),			FM(SEL_I2C2_3),		FM(SEL_I2C2_4),		F_(0, 0),	F_(0, 0),	F_(0, 0))
-#define MOD_SEL0_16		FM(SEL_NDF_0)			FM(SEL_NDF_1)
-#define MOD_SEL0_15		FM(SEL_PWM0_0)			FM(SEL_PWM0_1)
-#define MOD_SEL0_14		FM(SEL_PWM1_0)			FM(SEL_PWM1_1)
-#define MOD_SEL0_13_12	   REV4(FM(SEL_PWM2_0),			FM(SEL_PWM2_1),			FM(SEL_PWM2_2),			F_(0, 0))
-#define MOD_SEL0_11_10	   REV4(FM(SEL_PWM3_0),			FM(SEL_PWM3_1),			FM(SEL_PWM3_2),			F_(0, 0))
-#define MOD_SEL0_9		FM(SEL_PWM4_0)			FM(SEL_PWM4_1)
-#define MOD_SEL0_8		FM(SEL_PWM5_0)			FM(SEL_PWM5_1)
-#define MOD_SEL0_7		FM(SEL_PWM6_0)			FM(SEL_PWM6_1)
-#define MOD_SEL0_6_5	   REV4(FM(SEL_REMOCON_0),		FM(SEL_REMOCON_1),		FM(SEL_REMOCON_2),		F_(0, 0))
-#define MOD_SEL0_4		FM(SEL_SCIF_0)			FM(SEL_SCIF_1)
-#define MOD_SEL0_3		FM(SEL_SCIF0_0)			FM(SEL_SCIF0_1)
-#define MOD_SEL0_2		FM(SEL_SCIF2_0)			FM(SEL_SCIF2_1)
-#define MOD_SEL0_1_0	   REV4(FM(SEL_SPEED_PULSE_IF_0),	FM(SEL_SPEED_PULSE_IF_1),	FM(SEL_SPEED_PULSE_IF_2),	F_(0, 0))
-
-/* MOD_SEL1 */			/* 0 */				/* 1 */				/* 2 */				/* 3 */			/* 4 */			/* 5 */		/* 6 */		/* 7 */
-#define MOD_SEL1_31		FM(SEL_SIMCARD_0)		FM(SEL_SIMCARD_1)
-#define MOD_SEL1_30		FM(SEL_SSI2_0)			FM(SEL_SSI2_1)
-#define MOD_SEL1_29		FM(SEL_TIMER_TMU_0)		FM(SEL_TIMER_TMU_1)
-#define MOD_SEL1_28		FM(SEL_USB_20_CH0_0)		FM(SEL_USB_20_CH0_1)
-#define MOD_SEL1_26		FM(SEL_DRIF2_0)			FM(SEL_DRIF2_1)
-#define MOD_SEL1_25		FM(SEL_DRIF3_0)			FM(SEL_DRIF3_1)
-#define MOD_SEL1_24_23_22  REV8(FM(SEL_HSCIF3_0),		FM(SEL_HSCIF3_1),		FM(SEL_HSCIF3_2),		FM(SEL_HSCIF3_3),	FM(SEL_HSCIF3_4),	F_(0, 0),	F_(0, 0),	F_(0, 0))
-#define MOD_SEL1_21_20_19  REV8(FM(SEL_HSCIF4_0),		FM(SEL_HSCIF4_1),		FM(SEL_HSCIF4_2),		FM(SEL_HSCIF4_3),	FM(SEL_HSCIF4_4),	F_(0, 0),	F_(0, 0),	F_(0, 0))
-#define MOD_SEL1_18		FM(SEL_I2C6_0)			FM(SEL_I2C6_1)
-#define MOD_SEL1_17		FM(SEL_I2C7_0)			FM(SEL_I2C7_1)
-#define MOD_SEL1_16		FM(SEL_MSIOF2_0)		FM(SEL_MSIOF2_1)
-#define MOD_SEL1_15		FM(SEL_MSIOF3_0)		FM(SEL_MSIOF3_1)
-#define MOD_SEL1_14_13	   REV4(FM(SEL_SCIF3_0),		FM(SEL_SCIF3_1),		FM(SEL_SCIF3_2),		F_(0, 0))
-#define MOD_SEL1_12_11	   REV4(FM(SEL_SCIF4_0),		FM(SEL_SCIF4_1),		FM(SEL_SCIF4_2),		F_(0, 0))
-#define MOD_SEL1_10_9	   REV4(FM(SEL_SCIF5_0),		FM(SEL_SCIF5_1),		FM(SEL_SCIF5_2),		F_(0, 0))
-#define MOD_SEL1_8		FM(SEL_VIN4_0)			FM(SEL_VIN4_1)
-#define MOD_SEL1_7		FM(SEL_VIN5_0)			FM(SEL_VIN5_1)
-#define MOD_SEL1_6_5	   REV4(FM(SEL_ADGC_0),			FM(SEL_ADGC_1),			FM(SEL_ADGC_2),			F_(0, 0))
-#define MOD_SEL1_4		FM(SEL_SSI9_0)			FM(SEL_SSI9_1)
-
-#define PINMUX_MOD_SELS	\
-\
-			MOD_SEL1_31 \
-MOD_SEL0_30_29		MOD_SEL1_30 \
-			MOD_SEL1_29 \
-MOD_SEL0_28		MOD_SEL1_28 \
-MOD_SEL0_27_26 \
-			MOD_SEL1_26 \
-MOD_SEL0_25		MOD_SEL1_25 \
-MOD_SEL0_24		MOD_SEL1_24_23_22 \
-MOD_SEL0_23 \
-MOD_SEL0_22 \
-MOD_SEL0_21_20		MOD_SEL1_21_20_19 \
-MOD_SEL0_19_18_17	MOD_SEL1_18 \
-			MOD_SEL1_17 \
-MOD_SEL0_16		MOD_SEL1_16 \
-MOD_SEL0_15		MOD_SEL1_15 \
-MOD_SEL0_14		MOD_SEL1_14_13 \
-MOD_SEL0_13_12 \
-			MOD_SEL1_12_11 \
-MOD_SEL0_11_10 \
-			MOD_SEL1_10_9 \
-MOD_SEL0_9 \
-MOD_SEL0_8		MOD_SEL1_8 \
-MOD_SEL0_7		MOD_SEL1_7 \
-MOD_SEL0_6_5		MOD_SEL1_6_5 \
-MOD_SEL0_4		MOD_SEL1_4 \
-MOD_SEL0_3 \
-MOD_SEL0_2 \
-MOD_SEL0_1_0
-
-/*
- * These pins are not able to be muxed but have other properties
- * that can be set, such as pull-up/pull-down enable.
- */
-#define PINMUX_STATIC \
-	FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \
-	FM(AVB_TD3) \
-	FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \
-	FM(ASEBRK) \
-	FM(MLB_REF)
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	GP_ALL(DATA),
-	PINMUX_DATA_END,
-
-#define F_(x, y)
-#define FM(x)	FN_##x,
-	PINMUX_FUNCTION_BEGIN,
-	GP_ALL(FN),
-	PINMUX_GPSR
-	PINMUX_IPSR
-	PINMUX_MOD_SELS
-	PINMUX_FUNCTION_END,
-#undef F_
-#undef FM
-
-#define F_(x, y)
-#define FM(x)	x##_MARK,
-	PINMUX_MARK_BEGIN,
-	PINMUX_GPSR
-	PINMUX_IPSR
-	PINMUX_MOD_SELS
-	PINMUX_STATIC
-	PINMUX_MARK_END,
-#undef F_
-#undef FM
-};
-
-static const u16 pinmux_data[] = {
-	PINMUX_DATA_GP_ALL(),
-
-	PINMUX_SINGLE(CLKOUT),
-	PINMUX_SINGLE(AVB_PHY_INT),
-	PINMUX_SINGLE(AVB_RD3),
-	PINMUX_SINGLE(AVB_RXC),
-	PINMUX_SINGLE(AVB_RX_CTL),
-	PINMUX_SINGLE(QSPI0_SSL),
-
-	/* IPSR0 */
-	PINMUX_IPSR_GPSR(IP0_3_0,		QSPI0_SPCLK),
-	PINMUX_IPSR_MSEL(IP0_3_0,		HSCK4_A,	SEL_HSCIF4_0),
-
-	PINMUX_IPSR_GPSR(IP0_7_4,		QSPI0_MOSI_IO0),
-	PINMUX_IPSR_MSEL(IP0_7_4,		HCTS4_N_A,	SEL_HSCIF4_0),
-
-	PINMUX_IPSR_GPSR(IP0_11_8,		QSPI0_MISO_IO1),
-	PINMUX_IPSR_MSEL(IP0_11_8,		HRTS4_N_A,	SEL_HSCIF4_0),
-
-	PINMUX_IPSR_GPSR(IP0_15_12,		QSPI0_IO2),
-	PINMUX_IPSR_GPSR(IP0_15_12,		HTX4_A),
-
-	PINMUX_IPSR_GPSR(IP0_19_16,		QSPI0_IO3),
-	PINMUX_IPSR_MSEL(IP0_19_16,		HRX4_A,		SEL_HSCIF4_0),
-
-	PINMUX_IPSR_GPSR(IP0_23_20,		QSPI1_SPCLK),
-	PINMUX_IPSR_MSEL(IP0_23_20,		RIF2_CLK_A,	SEL_DRIF2_0),
-	PINMUX_IPSR_MSEL(IP0_23_20,		HSCK4_B,	SEL_HSCIF4_1),
-	PINMUX_IPSR_MSEL(IP0_23_20,		VI4_DATA0_A,	SEL_VIN4_0),
-
-	PINMUX_IPSR_GPSR(IP0_27_24,		QSPI1_MOSI_IO0),
-	PINMUX_IPSR_MSEL(IP0_27_24,		RIF2_SYNC_A,	SEL_DRIF2_0),
-	PINMUX_IPSR_GPSR(IP0_27_24,		HTX4_B),
-	PINMUX_IPSR_MSEL(IP0_27_24,		VI4_DATA1_A,	SEL_VIN4_0),
-
-	PINMUX_IPSR_GPSR(IP0_31_28,		QSPI1_MISO_IO1),
-	PINMUX_IPSR_MSEL(IP0_31_28,		RIF2_D0_A,	SEL_DRIF2_0),
-	PINMUX_IPSR_MSEL(IP0_31_28,		HRX4_B,		SEL_HSCIF4_1),
-	PINMUX_IPSR_MSEL(IP0_31_28,		VI4_DATA2_A,	SEL_VIN4_0),
-
-	/* IPSR1 */
-	PINMUX_IPSR_GPSR(IP1_3_0,		QSPI1_IO2),
-	PINMUX_IPSR_MSEL(IP1_3_0,		RIF2_D1_A,	SEL_DRIF2_0),
-	PINMUX_IPSR_GPSR(IP1_3_0,		HTX3_C),
-	PINMUX_IPSR_MSEL(IP1_3_0,		VI4_DATA3_A,	SEL_VIN4_0),
-
-	PINMUX_IPSR_GPSR(IP1_7_4,		QSPI1_IO3),
-	PINMUX_IPSR_MSEL(IP1_7_4,		RIF3_CLK_A,	SEL_DRIF3_0),
-	PINMUX_IPSR_MSEL(IP1_7_4,		HRX3_C,		SEL_HSCIF3_2),
-	PINMUX_IPSR_MSEL(IP1_7_4,		VI4_DATA4_A,	SEL_VIN4_0),
-
-	PINMUX_IPSR_GPSR(IP1_11_8,		QSPI1_SSL),
-	PINMUX_IPSR_MSEL(IP1_11_8,		RIF3_SYNC_A,	SEL_DRIF3_0),
-	PINMUX_IPSR_MSEL(IP1_11_8,		HSCK3_C,	SEL_HSCIF3_2),
-	PINMUX_IPSR_MSEL(IP1_11_8,		VI4_DATA5_A,	SEL_VIN4_0),
-
-	PINMUX_IPSR_GPSR(IP1_15_12,		RPC_INT_N),
-	PINMUX_IPSR_MSEL(IP1_15_12,		RIF3_D0_A,	SEL_DRIF3_0),
-	PINMUX_IPSR_MSEL(IP1_15_12,		HCTS3_N_C,	SEL_HSCIF3_2),
-	PINMUX_IPSR_MSEL(IP1_15_12,		VI4_DATA6_A,	SEL_VIN4_0),
-
-	PINMUX_IPSR_GPSR(IP1_19_16,		RPC_RESET_N),
-	PINMUX_IPSR_MSEL(IP1_19_16,		RIF3_D1_A,	SEL_DRIF3_0),
-	PINMUX_IPSR_MSEL(IP1_19_16,		HRTS3_N_C,	SEL_HSCIF3_2),
-	PINMUX_IPSR_MSEL(IP1_19_16,		VI4_DATA7_A,	SEL_VIN4_0),
-
-	PINMUX_IPSR_GPSR(IP1_23_20,		AVB_RD0),
-
-	PINMUX_IPSR_GPSR(IP1_27_24,		AVB_RD1),
-
-	PINMUX_IPSR_GPSR(IP1_31_28,		AVB_RD2),
-
-	/* IPSR2 */
-	PINMUX_IPSR_GPSR(IP2_3_0,		AVB_TXCREFCLK),
-
-	PINMUX_IPSR_GPSR(IP2_7_4,		AVB_MDIO),
-
-	PINMUX_IPSR_GPSR(IP2_11_8,		AVB_MDC),
-
-	PINMUX_IPSR_GPSR(IP2_15_12,		BS_N),
-	PINMUX_IPSR_MSEL(IP2_15_12,		PWM0_A,		SEL_PWM0_0),
-	PINMUX_IPSR_GPSR(IP2_15_12,		AVB_MAGIC),
-	PINMUX_IPSR_GPSR(IP2_15_12,		VI4_CLK),
-	PINMUX_IPSR_GPSR(IP2_15_12,		TX3_C),
-	PINMUX_IPSR_MSEL(IP2_15_12,		VI5_CLK_B,	SEL_VIN5_1),
-
-	PINMUX_IPSR_GPSR(IP2_19_16,		RD_N),
-	PINMUX_IPSR_MSEL(IP2_19_16,		PWM1_A,		SEL_PWM1_0),
-	PINMUX_IPSR_GPSR(IP2_19_16,		AVB_LINK),
-	PINMUX_IPSR_GPSR(IP2_19_16,		VI4_FIELD),
-	PINMUX_IPSR_MSEL(IP2_19_16,		RX3_C,		SEL_SCIF3_2),
-	PINMUX_IPSR_GPSR(IP2_19_16,		FSCLKST2_N_A),
-	PINMUX_IPSR_MSEL(IP2_19_16,		VI5_DATA0_B,	SEL_VIN5_1),
-
-	PINMUX_IPSR_GPSR(IP2_23_20,		RD_WR_N),
-	PINMUX_IPSR_MSEL(IP2_23_20,		SCL7_A,		SEL_I2C7_0),
-	PINMUX_IPSR_GPSR(IP2_23_20,		AVB_AVTP_MATCH),
-	PINMUX_IPSR_GPSR(IP2_23_20,		VI4_VSYNC_N),
-	PINMUX_IPSR_GPSR(IP2_23_20,		TX5_B),
-	PINMUX_IPSR_MSEL(IP2_23_20,		SCK3_C,		SEL_SCIF3_2),
-	PINMUX_IPSR_MSEL(IP2_23_20,		PWM5_A,		SEL_PWM5_0),
-
-	PINMUX_IPSR_GPSR(IP2_27_24,		EX_WAIT0),
-	PINMUX_IPSR_MSEL(IP2_27_24,		SDA7_A,		SEL_I2C7_0),
-	PINMUX_IPSR_GPSR(IP2_27_24,		AVB_AVTP_CAPTURE),
-	PINMUX_IPSR_GPSR(IP2_27_24,		VI4_HSYNC_N),
-	PINMUX_IPSR_MSEL(IP2_27_24,		RX5_B,		SEL_SCIF5_1),
-	PINMUX_IPSR_MSEL(IP2_27_24,		PWM6_A,		SEL_PWM6_0),
-
-	PINMUX_IPSR_GPSR(IP2_31_28,		A0),
-	PINMUX_IPSR_GPSR(IP2_31_28,		IRQ0),
-	PINMUX_IPSR_MSEL(IP2_31_28,		PWM2_A,		SEL_PWM2_0),
-	PINMUX_IPSR_MSEL(IP2_31_28,		MSIOF3_SS1_B,	SEL_MSIOF3_1),
-	PINMUX_IPSR_MSEL(IP2_31_28,		VI5_CLK_A,	SEL_VIN5_0),
-	PINMUX_IPSR_GPSR(IP2_31_28,		DU_CDE),
-	PINMUX_IPSR_MSEL(IP2_31_28,		HRX3_D,		SEL_HSCIF3_3),
-	PINMUX_IPSR_GPSR(IP2_31_28,		IERX),
-	PINMUX_IPSR_GPSR(IP2_31_28,		QSTB_QHE),
-
-	/* IPSR3 */
-	PINMUX_IPSR_GPSR(IP3_3_0,		A1),
-	PINMUX_IPSR_GPSR(IP3_3_0,		IRQ1),
-	PINMUX_IPSR_MSEL(IP3_3_0,		PWM3_A,		SEL_PWM3_0),
-	PINMUX_IPSR_GPSR(IP3_3_0,		DU_DOTCLKIN1),
-	PINMUX_IPSR_MSEL(IP3_3_0,		VI5_DATA0_A,	SEL_VIN5_0),
-	PINMUX_IPSR_GPSR(IP3_3_0,		DU_DISP_CDE),
-	PINMUX_IPSR_MSEL(IP3_3_0,		SDA6_B,		SEL_I2C6_1),
-	PINMUX_IPSR_GPSR(IP3_3_0,		IETX),
-	PINMUX_IPSR_GPSR(IP3_3_0,		QCPV_QDE),
-
-	PINMUX_IPSR_GPSR(IP3_7_4,		A2),
-	PINMUX_IPSR_GPSR(IP3_7_4,		IRQ2),
-	PINMUX_IPSR_GPSR(IP3_7_4,		AVB_AVTP_PPS),
-	PINMUX_IPSR_GPSR(IP3_7_4,		VI4_CLKENB),
-	PINMUX_IPSR_MSEL(IP3_7_4,		VI5_DATA1_A,	SEL_VIN5_0),
-	PINMUX_IPSR_GPSR(IP3_7_4,		DU_DISP),
-	PINMUX_IPSR_MSEL(IP3_7_4,		SCL6_B,		SEL_I2C6_1),
-	PINMUX_IPSR_GPSR(IP3_7_4,		QSTVB_QVE),
-
-	PINMUX_IPSR_GPSR(IP3_11_8,		A3),
-	PINMUX_IPSR_MSEL(IP3_11_8,		CTS4_N_A,	SEL_SCIF4_0),
-	PINMUX_IPSR_MSEL(IP3_11_8,		PWM4_A,		SEL_PWM4_0),
-	PINMUX_IPSR_GPSR(IP3_11_8,		VI4_DATA12),
-	PINMUX_IPSR_GPSR(IP3_11_8,		DU_DOTCLKOUT0),
-	PINMUX_IPSR_GPSR(IP3_11_8,		HTX3_D),
-	PINMUX_IPSR_GPSR(IP3_11_8,		IECLK),
-	PINMUX_IPSR_GPSR(IP3_11_8,		LCDOUT12),
-
-	PINMUX_IPSR_GPSR(IP3_15_12,		A4),
-	PINMUX_IPSR_MSEL(IP3_15_12,		RTS4_N_A,	SEL_SCIF4_0),
-	PINMUX_IPSR_MSEL(IP3_15_12,		MSIOF3_SYNC_B,	SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP3_15_12,		VI4_DATA8),
-	PINMUX_IPSR_MSEL(IP3_15_12,		PWM2_B,		SEL_PWM2_1),
-	PINMUX_IPSR_GPSR(IP3_15_12,		DU_DG4),
-	PINMUX_IPSR_MSEL(IP3_15_12,		RIF2_CLK_B,	SEL_DRIF2_1),
-
-	PINMUX_IPSR_GPSR(IP3_19_16,		A5),
-	PINMUX_IPSR_MSEL(IP3_19_16,		SCK4_A,		SEL_SCIF4_0),
-	PINMUX_IPSR_MSEL(IP3_19_16,		MSIOF3_SCK_B,	SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP3_19_16,		VI4_DATA9),
-	PINMUX_IPSR_MSEL(IP3_19_16,		PWM3_B,		SEL_PWM3_1),
-	PINMUX_IPSR_MSEL(IP3_19_16,		RIF2_SYNC_B,	SEL_DRIF2_1),
-	PINMUX_IPSR_GPSR(IP3_19_16,		QPOLA),
-
-	PINMUX_IPSR_GPSR(IP3_23_20,		A6),
-	PINMUX_IPSR_MSEL(IP3_23_20,		RX4_A,		SEL_SCIF4_0),
-	PINMUX_IPSR_MSEL(IP3_23_20,		MSIOF3_RXD_B,	SEL_MSIOF3_1),
-	PINMUX_IPSR_GPSR(IP3_23_20,		VI4_DATA10),
-	PINMUX_IPSR_MSEL(IP3_23_20,		RIF2_D0_B,	SEL_DRIF2_1),
-
-	PINMUX_IPSR_GPSR(IP3_27_24,		A7),
-	PINMUX_IPSR_GPSR(IP3_27_24,		TX4_A),
-	PINMUX_IPSR_GPSR(IP3_27_24,		MSIOF3_TXD_B),
-	PINMUX_IPSR_GPSR(IP3_27_24,		VI4_DATA11),
-	PINMUX_IPSR_MSEL(IP3_27_24,		RIF2_D1_B,	SEL_DRIF2_1),
-
-	PINMUX_IPSR_GPSR(IP3_31_28,		A8),
-	PINMUX_IPSR_MSEL(IP3_31_28,		SDA6_A,		SEL_I2C6_0),
-	PINMUX_IPSR_MSEL(IP3_31_28,		RX3_B,		SEL_SCIF3_1),
-	PINMUX_IPSR_MSEL(IP3_31_28,		HRX4_C,		SEL_HSCIF4_2),
-	PINMUX_IPSR_MSEL(IP3_31_28,		VI5_HSYNC_N_A,	SEL_VIN5_0),
-	PINMUX_IPSR_GPSR(IP3_31_28,		DU_HSYNC),
-	PINMUX_IPSR_MSEL(IP3_31_28,		VI4_DATA0_B,	SEL_VIN4_1),
-	PINMUX_IPSR_GPSR(IP3_31_28,		QSTH_QHS),
-
-	/* IPSR4 */
-	PINMUX_IPSR_GPSR(IP4_3_0,		A9),
-	PINMUX_IPSR_GPSR(IP4_3_0,		TX5_A),
-	PINMUX_IPSR_GPSR(IP4_3_0,		IRQ3),
-	PINMUX_IPSR_GPSR(IP4_3_0,		VI4_DATA16),
-	PINMUX_IPSR_MSEL(IP4_3_0,		VI5_VSYNC_N_A,	SEL_VIN5_0),
-	PINMUX_IPSR_GPSR(IP4_3_0,		DU_DG7),
-	PINMUX_IPSR_GPSR(IP4_3_0,		LCDOUT15),
-
-	PINMUX_IPSR_GPSR(IP4_7_4,		A10),
-	PINMUX_IPSR_GPSR(IP4_7_4,		IRQ4),
-	PINMUX_IPSR_MSEL(IP4_7_4,		MSIOF2_SYNC_B,	SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP4_7_4,		VI4_DATA13),
-	PINMUX_IPSR_MSEL(IP4_7_4,		VI5_FIELD_A,	SEL_VIN5_0),
-	PINMUX_IPSR_GPSR(IP4_7_4,		DU_DG5),
-	PINMUX_IPSR_GPSR(IP4_7_4,		FSCLKST2_N_B),
-	PINMUX_IPSR_GPSR(IP4_7_4,		LCDOUT13),
-
-	PINMUX_IPSR_GPSR(IP4_11_8,		A11),
-	PINMUX_IPSR_MSEL(IP4_11_8,		SCL6_A,		SEL_I2C6_0),
-	PINMUX_IPSR_GPSR(IP4_11_8,		TX3_B),
-	PINMUX_IPSR_GPSR(IP4_11_8,		HTX4_C),
-	PINMUX_IPSR_GPSR(IP4_11_8,		DU_VSYNC),
-	PINMUX_IPSR_MSEL(IP4_11_8,		VI4_DATA1_B,	SEL_VIN4_1),
-	PINMUX_IPSR_GPSR(IP4_11_8,		QSTVA_QVS),
-
-	PINMUX_IPSR_GPSR(IP4_15_12,		A12),
-	PINMUX_IPSR_MSEL(IP4_15_12,		RX5_A,		SEL_SCIF5_0),
-	PINMUX_IPSR_GPSR(IP4_15_12,		MSIOF2_SS2_B),
-	PINMUX_IPSR_GPSR(IP4_15_12,		VI4_DATA17),
-	PINMUX_IPSR_MSEL(IP4_15_12,		VI5_DATA3_A,	SEL_VIN5_0),
-	PINMUX_IPSR_GPSR(IP4_15_12,		DU_DG6),
-	PINMUX_IPSR_GPSR(IP4_15_12,		LCDOUT14),
-
-	PINMUX_IPSR_GPSR(IP4_19_16,		A13),
-	PINMUX_IPSR_MSEL(IP4_19_16,		SCK5_A,		SEL_SCIF5_0),
-	PINMUX_IPSR_MSEL(IP4_19_16,		MSIOF2_SCK_B,	SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP4_19_16,		VI4_DATA14),
-	PINMUX_IPSR_MSEL(IP4_19_16,		HRX4_D,		SEL_HSCIF4_3),
-	PINMUX_IPSR_GPSR(IP4_19_16,		DU_DB2),
-	PINMUX_IPSR_GPSR(IP4_19_16,		LCDOUT2),
-
-	PINMUX_IPSR_GPSR(IP4_23_20,		A14),
-	PINMUX_IPSR_GPSR(IP4_23_20,		MSIOF1_SS1),
-	PINMUX_IPSR_MSEL(IP4_23_20,		MSIOF2_RXD_B,	SEL_MSIOF2_1),
-	PINMUX_IPSR_GPSR(IP4_23_20,		VI4_DATA15),
-	PINMUX_IPSR_GPSR(IP4_23_20,		HTX4_D),
-	PINMUX_IPSR_GPSR(IP4_23_20,		DU_DB3),
-	PINMUX_IPSR_GPSR(IP4_23_20,		LCDOUT3),
-
-	PINMUX_IPSR_GPSR(IP4_27_24,		A15),
-	PINMUX_IPSR_GPSR(IP4_27_24,		MSIOF1_SS2),
-	PINMUX_IPSR_GPSR(IP4_27_24,		MSIOF2_TXD_B),
-	PINMUX_IPSR_GPSR(IP4_27_24,		VI4_DATA18),
-	PINMUX_IPSR_MSEL(IP4_27_24,		VI5_DATA4_A,	SEL_VIN5_0),
-	PINMUX_IPSR_GPSR(IP4_27_24,		DU_DB4),
-	PINMUX_IPSR_GPSR(IP4_27_24,		LCDOUT4),
-
-	PINMUX_IPSR_GPSR(IP4_31_28,		A16),
-	PINMUX_IPSR_GPSR(IP4_31_28,		MSIOF1_SYNC),
-	PINMUX_IPSR_GPSR(IP4_31_28,		MSIOF2_SS1_B),
-	PINMUX_IPSR_GPSR(IP4_31_28,		VI4_DATA19),
-	PINMUX_IPSR_MSEL(IP4_31_28,		VI5_DATA5_A,	SEL_VIN5_0),
-	PINMUX_IPSR_GPSR(IP4_31_28,		DU_DB5),
-	PINMUX_IPSR_GPSR(IP4_31_28,		LCDOUT5),
-
-	/* IPSR5 */
-	PINMUX_IPSR_GPSR(IP5_3_0,		A17),
-	PINMUX_IPSR_GPSR(IP5_3_0,		MSIOF1_RXD),
-	PINMUX_IPSR_GPSR(IP5_3_0,		VI4_DATA20),
-	PINMUX_IPSR_MSEL(IP5_3_0,		VI5_DATA6_A,	SEL_VIN5_0),
-	PINMUX_IPSR_GPSR(IP5_3_0,		DU_DB6),
-	PINMUX_IPSR_GPSR(IP5_3_0,		LCDOUT6),
-
-	PINMUX_IPSR_GPSR(IP5_7_4,		A18),
-	PINMUX_IPSR_GPSR(IP5_7_4,		MSIOF1_TXD),
-	PINMUX_IPSR_GPSR(IP5_7_4,		VI4_DATA21),
-	PINMUX_IPSR_MSEL(IP5_7_4,		VI5_DATA7_A,	SEL_VIN5_0),
-	PINMUX_IPSR_GPSR(IP5_7_4,		DU_DB0),
-	PINMUX_IPSR_MSEL(IP5_7_4,		HRX4_E,		SEL_HSCIF4_4),
-	PINMUX_IPSR_GPSR(IP5_7_4,		LCDOUT0),
-
-	PINMUX_IPSR_GPSR(IP5_11_8,		A19),
-	PINMUX_IPSR_GPSR(IP5_11_8,		MSIOF1_SCK),
-	PINMUX_IPSR_GPSR(IP5_11_8,		VI4_DATA22),
-	PINMUX_IPSR_MSEL(IP5_11_8,		VI5_DATA2_A,	SEL_VIN5_0),
-	PINMUX_IPSR_GPSR(IP5_11_8,		DU_DB1),
-	PINMUX_IPSR_GPSR(IP5_11_8,		HTX4_E),
-	PINMUX_IPSR_GPSR(IP5_11_8,		LCDOUT1),
-
-	PINMUX_IPSR_GPSR(IP5_15_12,		CS0_N),
-	PINMUX_IPSR_GPSR(IP5_15_12,		SCL5),
-	PINMUX_IPSR_GPSR(IP5_15_12,		DU_DR0),
-	PINMUX_IPSR_MSEL(IP5_15_12,		VI4_DATA2_B,	SEL_VIN4_1),
-	PINMUX_IPSR_GPSR(IP5_15_12,		LCDOUT16),
-
-	PINMUX_IPSR_GPSR(IP5_19_16,		WE0_N),
-	PINMUX_IPSR_GPSR(IP5_19_16,		SDA5),
-	PINMUX_IPSR_GPSR(IP5_19_16,		DU_DR1),
-	PINMUX_IPSR_MSEL(IP5_19_16,		VI4_DATA3_B,	SEL_VIN4_1),
-	PINMUX_IPSR_GPSR(IP5_19_16,		LCDOUT17),
-
-	PINMUX_IPSR_GPSR(IP5_23_20,		D0),
-	PINMUX_IPSR_MSEL(IP5_23_20,		MSIOF3_SCK_A,	SEL_MSIOF3_0),
-	PINMUX_IPSR_GPSR(IP5_23_20,		DU_DR2),
-	PINMUX_IPSR_MSEL(IP5_23_20,		CTS4_N_C,	SEL_SCIF4_2),
-	PINMUX_IPSR_GPSR(IP5_23_20,		LCDOUT18),
-
-	PINMUX_IPSR_GPSR(IP5_27_24,		D1),
-	PINMUX_IPSR_MSEL(IP5_27_24,		MSIOF3_SYNC_A,	SEL_MSIOF3_0),
-	PINMUX_IPSR_MSEL(IP5_27_24,		SCK3_A,		SEL_SCIF3_0),
-	PINMUX_IPSR_GPSR(IP5_27_24,		VI4_DATA23),
-	PINMUX_IPSR_MSEL(IP5_27_24,		VI5_CLKENB_A,	SEL_VIN5_0),
-	PINMUX_IPSR_GPSR(IP5_27_24,		DU_DB7),
-	PINMUX_IPSR_MSEL(IP5_27_24,		RTS4_N_C,	SEL_SCIF4_2),
-	PINMUX_IPSR_GPSR(IP5_27_24,		LCDOUT7),
-
-	PINMUX_IPSR_GPSR(IP5_31_28,		D2),
-	PINMUX_IPSR_MSEL(IP5_31_28,		MSIOF3_RXD_A,	SEL_MSIOF3_0),
-	PINMUX_IPSR_MSEL(IP5_31_28,		RX5_C,		SEL_SCIF5_2),
-	PINMUX_IPSR_MSEL(IP5_31_28,		VI5_DATA14_A,	SEL_VIN5_0),
-	PINMUX_IPSR_GPSR(IP5_31_28,		DU_DR3),
-	PINMUX_IPSR_MSEL(IP5_31_28,		RX4_C,		SEL_SCIF4_2),
-	PINMUX_IPSR_GPSR(IP5_31_28,		LCDOUT19),
-
-	/* IPSR6 */
-	PINMUX_IPSR_GPSR(IP6_3_0,		D3),
-	PINMUX_IPSR_GPSR(IP6_3_0,		MSIOF3_TXD_A),
-	PINMUX_IPSR_GPSR(IP6_3_0,		TX5_C),
-	PINMUX_IPSR_MSEL(IP6_3_0,		VI5_DATA15_A,	SEL_VIN5_0),
-	PINMUX_IPSR_GPSR(IP6_3_0,		DU_DR4),
-	PINMUX_IPSR_GPSR(IP6_3_0,		TX4_C),
-	PINMUX_IPSR_GPSR(IP6_3_0,		LCDOUT20),
-
-	PINMUX_IPSR_GPSR(IP6_7_4,		D4),
-	PINMUX_IPSR_GPSR(IP6_7_4,		CANFD1_TX),
-	PINMUX_IPSR_MSEL(IP6_7_4,		HSCK3_B,	SEL_HSCIF3_1),
-	PINMUX_IPSR_GPSR(IP6_7_4,		CAN1_TX),
-	PINMUX_IPSR_MSEL(IP6_7_4,		RTS3_N_A,	SEL_SCIF3_0),
-	PINMUX_IPSR_GPSR(IP6_7_4,		MSIOF3_SS2_A),
-	PINMUX_IPSR_MSEL(IP6_7_4,		VI5_DATA1_B,	SEL_VIN5_1),
-
-	PINMUX_IPSR_GPSR(IP6_11_8,		D5),
-	PINMUX_IPSR_MSEL(IP6_11_8,		RX3_A,		SEL_SCIF3_0),
-	PINMUX_IPSR_MSEL(IP6_11_8,		HRX3_B,		SEL_HSCIF3_1),
-	PINMUX_IPSR_GPSR(IP6_11_8,		DU_DR5),
-	PINMUX_IPSR_MSEL(IP6_11_8,		VI4_DATA4_B,	SEL_VIN4_1),
-	PINMUX_IPSR_GPSR(IP6_11_8,		LCDOUT21),
-
-	PINMUX_IPSR_GPSR(IP6_15_12,		D6),
-	PINMUX_IPSR_GPSR(IP6_15_12,		TX3_A),
-	PINMUX_IPSR_GPSR(IP6_15_12,		HTX3_B),
-	PINMUX_IPSR_GPSR(IP6_15_12,		DU_DR6),
-	PINMUX_IPSR_MSEL(IP6_15_12,		VI4_DATA5_B,	SEL_VIN4_1),
-	PINMUX_IPSR_GPSR(IP6_15_12,		LCDOUT22),
-
-	PINMUX_IPSR_GPSR(IP6_19_16,		D7),
-	PINMUX_IPSR_GPSR(IP6_19_16,		CANFD1_RX),
-	PINMUX_IPSR_GPSR(IP6_19_16,		IRQ5),
-	PINMUX_IPSR_GPSR(IP6_19_16,		CAN1_RX),
-	PINMUX_IPSR_MSEL(IP6_19_16,		CTS3_N_A,	SEL_SCIF3_0),
-	PINMUX_IPSR_MSEL(IP6_19_16,		VI5_DATA2_B,	SEL_VIN5_1),
-
-	PINMUX_IPSR_GPSR(IP6_23_20,		D8),
-	PINMUX_IPSR_MSEL(IP6_23_20,		MSIOF2_SCK_A,	SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP6_23_20,		SCK4_B,		SEL_SCIF4_1),
-	PINMUX_IPSR_MSEL(IP6_23_20,		VI5_DATA12_A,	SEL_VIN5_0),
-	PINMUX_IPSR_GPSR(IP6_23_20,		DU_DR7),
-	PINMUX_IPSR_MSEL(IP6_23_20,		RIF3_CLK_B,	SEL_DRIF3_1),
-	PINMUX_IPSR_MSEL(IP6_23_20,		HCTS3_N_E,	SEL_HSCIF3_4),
-	PINMUX_IPSR_GPSR(IP6_23_20,		LCDOUT23),
-
-	PINMUX_IPSR_GPSR(IP6_27_24,		D9),
-	PINMUX_IPSR_MSEL(IP6_27_24,		MSIOF2_SYNC_A,	SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP6_27_24,		VI5_DATA10_A,	SEL_VIN5_0),
-	PINMUX_IPSR_GPSR(IP6_27_24,		DU_DG0),
-	PINMUX_IPSR_MSEL(IP6_27_24,		RIF3_SYNC_B,	SEL_DRIF3_1),
-	PINMUX_IPSR_MSEL(IP6_27_24,		HRX3_E,		SEL_HSCIF3_4),
-	PINMUX_IPSR_GPSR(IP6_27_24,		LCDOUT8),
-
-	PINMUX_IPSR_GPSR(IP6_31_28,		D10),
-	PINMUX_IPSR_MSEL(IP6_31_28,		MSIOF2_RXD_A,	SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP6_31_28,		VI5_DATA13_A,	SEL_VIN5_0),
-	PINMUX_IPSR_GPSR(IP6_31_28,		DU_DG1),
-	PINMUX_IPSR_MSEL(IP6_31_28,		RIF3_D0_B,	SEL_DRIF3_1),
-	PINMUX_IPSR_GPSR(IP6_31_28,		HTX3_E),
-	PINMUX_IPSR_GPSR(IP6_31_28,		LCDOUT9),
-
-	/* IPSR7 */
-	PINMUX_IPSR_GPSR(IP7_3_0,		D11),
-	PINMUX_IPSR_GPSR(IP7_3_0,		MSIOF2_TXD_A),
-	PINMUX_IPSR_MSEL(IP7_3_0,		VI5_DATA11_A,	SEL_VIN5_0),
-	PINMUX_IPSR_GPSR(IP7_3_0,		DU_DG2),
-	PINMUX_IPSR_MSEL(IP7_3_0,		RIF3_D1_B,	SEL_DRIF3_1),
-	PINMUX_IPSR_MSEL(IP7_3_0,		HRTS3_N_E,	SEL_HSCIF3_4),
-	PINMUX_IPSR_GPSR(IP7_3_0,		LCDOUT10),
-
-	PINMUX_IPSR_GPSR(IP7_7_4,		D12),
-	PINMUX_IPSR_GPSR(IP7_7_4,		CANFD0_TX),
-	PINMUX_IPSR_GPSR(IP7_7_4,		TX4_B),
-	PINMUX_IPSR_GPSR(IP7_7_4,		CAN0_TX),
-	PINMUX_IPSR_MSEL(IP7_7_4,		VI5_DATA8_A,	SEL_VIN5_0),
-	PINMUX_IPSR_MSEL(IP7_7_4,		VI5_DATA3_B,	SEL_VIN5_1),
-
-	PINMUX_IPSR_GPSR(IP7_11_8,		D13),
-	PINMUX_IPSR_GPSR(IP7_11_8,		CANFD0_RX),
-	PINMUX_IPSR_MSEL(IP7_11_8,		RX4_B,		SEL_SCIF4_1),
-	PINMUX_IPSR_GPSR(IP7_11_8,		CAN0_RX),
-	PINMUX_IPSR_MSEL(IP7_11_8,		VI5_DATA9_A,	SEL_VIN5_0),
-	PINMUX_IPSR_MSEL(IP7_11_8,		SCL7_B,		SEL_I2C7_1),
-	PINMUX_IPSR_MSEL(IP7_11_8,		VI5_DATA4_B,	SEL_VIN5_1),
-
-	PINMUX_IPSR_GPSR(IP7_15_12,		D14),
-	PINMUX_IPSR_GPSR(IP7_15_12,		CAN_CLK),
-	PINMUX_IPSR_MSEL(IP7_15_12,		HRX3_A,		SEL_HSCIF3_0),
-	PINMUX_IPSR_GPSR(IP7_15_12,		MSIOF2_SS2_A),
-	PINMUX_IPSR_MSEL(IP7_15_12,		SDA7_B,		SEL_I2C7_1),
-	PINMUX_IPSR_MSEL(IP7_15_12,		VI5_DATA5_B,	SEL_VIN5_1),
-
-	PINMUX_IPSR_GPSR(IP7_19_16,		D15),
-	PINMUX_IPSR_GPSR(IP7_19_16,		MSIOF2_SS1_A),
-	PINMUX_IPSR_GPSR(IP7_19_16,		HTX3_A),
-	PINMUX_IPSR_GPSR(IP7_19_16,		MSIOF3_SS1_A),
-	PINMUX_IPSR_GPSR(IP7_19_16,		DU_DG3),
-	PINMUX_IPSR_GPSR(IP7_19_16,		LCDOUT11),
-
-	PINMUX_IPSR_GPSR(IP7_23_20,		SCL4),
-	PINMUX_IPSR_GPSR(IP7_23_20,		CS1_N_A26),
-	PINMUX_IPSR_GPSR(IP7_23_20,		DU_DOTCLKIN0),
-	PINMUX_IPSR_MSEL(IP7_23_20,		VI4_DATA6_B,	SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP7_23_20,		VI5_DATA6_B,	SEL_VIN5_1),
-	PINMUX_IPSR_GPSR(IP7_23_20,		QCLK),
-
-	PINMUX_IPSR_GPSR(IP7_27_24,		SDA4),
-	PINMUX_IPSR_GPSR(IP7_27_24,		WE1_N),
-	PINMUX_IPSR_MSEL(IP7_27_24,		VI4_DATA7_B,	SEL_VIN4_1),
-	PINMUX_IPSR_MSEL(IP7_27_24,		VI5_DATA7_B,	SEL_VIN5_1),
-	PINMUX_IPSR_GPSR(IP7_27_24,		QPOLB),
-
-	PINMUX_IPSR_GPSR(IP7_31_28,		SD0_CLK),
-	PINMUX_IPSR_GPSR(IP7_31_28,		NFDATA8),
-	PINMUX_IPSR_MSEL(IP7_31_28,		SCL1_C,		SEL_I2C1_2),
-	PINMUX_IPSR_MSEL(IP7_31_28,		HSCK1_B,	SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP7_31_28,		SDA2_E,		SEL_I2C2_4),
-	PINMUX_IPSR_MSEL(IP7_31_28,		FMCLK_B,	SEL_FM_1),
-
-	/* IPSR8 */
-	PINMUX_IPSR_GPSR(IP8_3_0,		SD0_CMD),
-	PINMUX_IPSR_GPSR(IP8_3_0,		NFDATA9),
-	PINMUX_IPSR_MSEL(IP8_3_0,		HRX1_B,		SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP8_3_0,		SPEEDIN_B,	SEL_SPEED_PULSE_IF_1),
-
-	PINMUX_IPSR_GPSR(IP8_7_4,		SD0_DAT0),
-	PINMUX_IPSR_GPSR(IP8_7_4,		NFDATA10),
-	PINMUX_IPSR_GPSR(IP8_7_4,		HTX1_B),
-	PINMUX_IPSR_MSEL(IP8_7_4,		REMOCON_B,	SEL_REMOCON_1),
-
-	PINMUX_IPSR_GPSR(IP8_11_8,		SD0_DAT1),
-	PINMUX_IPSR_GPSR(IP8_11_8,		NFDATA11),
-	PINMUX_IPSR_MSEL(IP8_11_8,		SDA2_C,		SEL_I2C2_2),
-	PINMUX_IPSR_MSEL(IP8_11_8,		HCTS1_N_B,	SEL_HSCIF1_1),
-	PINMUX_IPSR_MSEL(IP8_11_8,		FMIN_B,		SEL_FM_1),
-
-	PINMUX_IPSR_GPSR(IP8_15_12,		SD0_DAT2),
-	PINMUX_IPSR_GPSR(IP8_15_12,		NFDATA12),
-	PINMUX_IPSR_MSEL(IP8_15_12,		SCL2_C,		SEL_I2C2_2),
-	PINMUX_IPSR_MSEL(IP8_15_12,		HRTS1_N_B,	SEL_HSCIF1_1),
-	PINMUX_IPSR_GPSR(IP8_15_12,		BPFCLK_B),
-
-	PINMUX_IPSR_GPSR(IP8_19_16,		SD0_DAT3),
-	PINMUX_IPSR_GPSR(IP8_19_16,		NFDATA13),
-	PINMUX_IPSR_MSEL(IP8_19_16,		SDA1_C,		SEL_I2C1_2),
-	PINMUX_IPSR_MSEL(IP8_19_16,		SCL2_E,		SEL_I2C2_4),
-	PINMUX_IPSR_MSEL(IP8_19_16,		SPEEDIN_C,	SEL_SPEED_PULSE_IF_2),
-	PINMUX_IPSR_MSEL(IP8_19_16,		REMOCON_C,	SEL_REMOCON_2),
-
-	PINMUX_IPSR_GPSR(IP8_23_20,		SD1_CLK),
-	PINMUX_IPSR_MSEL(IP8_23_20,		NFDATA14_B,	SEL_NDF_1),
-
-	PINMUX_IPSR_GPSR(IP8_27_24,		SD1_CMD),
-	PINMUX_IPSR_MSEL(IP8_27_24,		NFDATA15_B,	SEL_NDF_1),
-
-	PINMUX_IPSR_GPSR(IP8_31_28,		SD1_DAT0),
-	PINMUX_IPSR_MSEL(IP8_31_28,		NFWP_N_B,	SEL_NDF_1),
-
-	/* IPSR9 */
-	PINMUX_IPSR_GPSR(IP9_3_0,		SD1_DAT1),
-	PINMUX_IPSR_MSEL(IP9_3_0,		NFCE_N_B,	SEL_NDF_1),
-
-	PINMUX_IPSR_GPSR(IP9_7_4,		SD1_DAT2),
-	PINMUX_IPSR_MSEL(IP9_7_4,		NFALE_B,	SEL_NDF_1),
-
-	PINMUX_IPSR_GPSR(IP9_11_8,		SD1_DAT3),
-	PINMUX_IPSR_MSEL(IP9_11_8,		NFRB_N_B,	SEL_NDF_1),
-
-	PINMUX_IPSR_GPSR(IP9_15_12,		SD3_CLK),
-	PINMUX_IPSR_GPSR(IP9_15_12,		NFWE_N),
-
-	PINMUX_IPSR_GPSR(IP9_19_16,		SD3_CMD),
-	PINMUX_IPSR_GPSR(IP9_19_16,		NFRE_N),
-
-	PINMUX_IPSR_GPSR(IP9_23_20,		SD3_DAT0),
-	PINMUX_IPSR_GPSR(IP9_23_20,		NFDATA0),
-
-	PINMUX_IPSR_GPSR(IP9_27_24,		SD3_DAT1),
-	PINMUX_IPSR_GPSR(IP9_27_24,		NFDATA1),
-
-	PINMUX_IPSR_GPSR(IP9_31_28,		SD3_DAT2),
-	PINMUX_IPSR_GPSR(IP9_31_28,		NFDATA2),
-
-	/* IPSR10 */
-	PINMUX_IPSR_GPSR(IP10_3_0,		SD3_DAT3),
-	PINMUX_IPSR_GPSR(IP10_3_0,		NFDATA3),
-
-	PINMUX_IPSR_GPSR(IP10_7_4,		SD3_DAT4),
-	PINMUX_IPSR_GPSR(IP10_7_4,		NFDATA4),
-
-	PINMUX_IPSR_GPSR(IP10_11_8,		SD3_DAT5),
-	PINMUX_IPSR_GPSR(IP10_11_8,		NFDATA5),
-
-	PINMUX_IPSR_GPSR(IP10_15_12,		SD3_DAT6),
-	PINMUX_IPSR_GPSR(IP10_15_12,		NFDATA6),
-
-	PINMUX_IPSR_GPSR(IP10_19_16,		SD3_DAT7),
-	PINMUX_IPSR_GPSR(IP10_19_16,		NFDATA7),
-
-	PINMUX_IPSR_GPSR(IP10_23_20,		SD3_DS),
-	PINMUX_IPSR_GPSR(IP10_23_20,		NFCLE),
-
-	PINMUX_IPSR_GPSR(IP10_27_24,		SD0_CD),
-	PINMUX_IPSR_MSEL(IP10_27_24,		NFALE_A,	SEL_NDF_0),
-	PINMUX_IPSR_GPSR(IP10_27_24,		SD3_CD),
-	PINMUX_IPSR_MSEL(IP10_27_24,		RIF0_CLK_B,	SEL_DRIF0_1),
-	PINMUX_IPSR_MSEL(IP10_27_24,		SCL2_B,		SEL_I2C2_1),
-	PINMUX_IPSR_MSEL(IP10_27_24,		TCLK1_A,	SEL_TIMER_TMU_0),
-	PINMUX_IPSR_MSEL(IP10_27_24,		SSI_SCK2_B,	SEL_SSI2_1),
-	PINMUX_IPSR_GPSR(IP10_27_24,		TS_SCK0),
-
-	PINMUX_IPSR_GPSR(IP10_31_28,		SD0_WP),
-	PINMUX_IPSR_MSEL(IP10_31_28,		NFRB_N_A,	SEL_NDF_0),
-	PINMUX_IPSR_GPSR(IP10_31_28,		SD3_WP),
-	PINMUX_IPSR_MSEL(IP10_31_28,		RIF0_D0_B,	SEL_DRIF0_1),
-	PINMUX_IPSR_MSEL(IP10_31_28,		SDA2_B,		SEL_I2C2_1),
-	PINMUX_IPSR_MSEL(IP10_31_28,		TCLK2_A,	SEL_TIMER_TMU_0),
-	PINMUX_IPSR_MSEL(IP10_31_28,		SSI_WS2_B,	SEL_SSI2_1),
-	PINMUX_IPSR_GPSR(IP10_31_28,		TS_SDAT0),
-
-	/* IPSR11 */
-	PINMUX_IPSR_GPSR(IP11_3_0,		SD1_CD),
-	PINMUX_IPSR_MSEL(IP11_3_0,		NFCE_N_A,	SEL_NDF_0),
-	PINMUX_IPSR_GPSR(IP11_3_0,		SSI_SCK1),
-	PINMUX_IPSR_MSEL(IP11_3_0,		RIF0_D1_B,	SEL_DRIF0_1),
-	PINMUX_IPSR_GPSR(IP11_3_0,		TS_SDEN0),
-
-	PINMUX_IPSR_GPSR(IP11_7_4,		SD1_WP),
-	PINMUX_IPSR_MSEL(IP11_7_4,		NFWP_N_A,	SEL_NDF_0),
-	PINMUX_IPSR_GPSR(IP11_7_4,		SSI_WS1),
-	PINMUX_IPSR_MSEL(IP11_7_4,		RIF0_SYNC_B,	SEL_DRIF0_1),
-	PINMUX_IPSR_GPSR(IP11_7_4,		TS_SPSYNC0),
-
-	PINMUX_IPSR_MSEL(IP11_11_8,		RX0_A,		SEL_SCIF0_0),
-	PINMUX_IPSR_MSEL(IP11_11_8,		HRX1_A,		SEL_HSCIF1_0),
-	PINMUX_IPSR_MSEL(IP11_11_8,		SSI_SCK2_A,	SEL_SSI2_0),
-	PINMUX_IPSR_GPSR(IP11_11_8,		RIF1_SYNC),
-	PINMUX_IPSR_GPSR(IP11_11_8,		TS_SCK1),
-
-	PINMUX_IPSR_MSEL(IP11_15_12,		TX0_A,		SEL_SCIF0_0),
-	PINMUX_IPSR_GPSR(IP11_15_12,		HTX1_A),
-	PINMUX_IPSR_MSEL(IP11_15_12,		SSI_WS2_A,	SEL_SSI2_0),
-	PINMUX_IPSR_GPSR(IP11_15_12,		RIF1_D0),
-	PINMUX_IPSR_GPSR(IP11_15_12,		TS_SDAT1),
-
-	PINMUX_IPSR_MSEL(IP11_19_16,		CTS0_N_A,	SEL_SCIF0_0),
-	PINMUX_IPSR_MSEL(IP11_19_16,		NFDATA14_A,	SEL_NDF_0),
-	PINMUX_IPSR_GPSR(IP11_19_16,		AUDIO_CLKOUT_A),
-	PINMUX_IPSR_GPSR(IP11_19_16,		RIF1_D1),
-	PINMUX_IPSR_MSEL(IP11_19_16,		SCIF_CLK_A,	SEL_SCIF_0),
-	PINMUX_IPSR_MSEL(IP11_19_16,		FMCLK_A,	SEL_FM_0),
-
-	PINMUX_IPSR_MSEL(IP11_23_20,		RTS0_N_A,	SEL_SCIF0_0),
-	PINMUX_IPSR_MSEL(IP11_23_20,		NFDATA15_A,	SEL_NDF_0),
-	PINMUX_IPSR_GPSR(IP11_23_20,		AUDIO_CLKOUT1_A),
-	PINMUX_IPSR_GPSR(IP11_23_20,		RIF1_CLK),
-	PINMUX_IPSR_MSEL(IP11_23_20,		SCL2_A,		SEL_I2C2_0),
-	PINMUX_IPSR_MSEL(IP11_23_20,		FMIN_A,		SEL_FM_0),
-
-	PINMUX_IPSR_MSEL(IP11_27_24,		SCK0_A,		SEL_SCIF0_0),
-	PINMUX_IPSR_MSEL(IP11_27_24,		HSCK1_A,	SEL_HSCIF1_0),
-	PINMUX_IPSR_GPSR(IP11_27_24,		USB3HS0_ID),
-	PINMUX_IPSR_GPSR(IP11_27_24,		RTS1_N),
-	PINMUX_IPSR_MSEL(IP11_27_24,		SDA2_A,		SEL_I2C2_0),
-	PINMUX_IPSR_MSEL(IP11_27_24,		FMCLK_C,	SEL_FM_2),
-	PINMUX_IPSR_GPSR(IP11_27_24,		USB0_ID),
-
-	PINMUX_IPSR_GPSR(IP11_31_28,		RX1),
-	PINMUX_IPSR_MSEL(IP11_31_28,		HRX2_B,		SEL_HSCIF2_1),
-	PINMUX_IPSR_MSEL(IP11_31_28,		SSI_SCK9_B,	SEL_SSI9_1),
-	PINMUX_IPSR_GPSR(IP11_31_28,		AUDIO_CLKOUT1_B),
-
-	/* IPSR12 */
-	PINMUX_IPSR_GPSR(IP12_3_0,		TX1),
-	PINMUX_IPSR_GPSR(IP12_3_0,		HTX2_B),
-	PINMUX_IPSR_MSEL(IP12_3_0,		SSI_WS9_B,	SEL_SSI9_1),
-	PINMUX_IPSR_GPSR(IP12_3_0,		AUDIO_CLKOUT3_B),
-
-	PINMUX_IPSR_MSEL(IP12_7_4,		SCK2_A,		SEL_SCIF2_0),
-	PINMUX_IPSR_MSEL(IP12_7_4,		HSCK0_A,	SEL_HSCIF0_0),
-	PINMUX_IPSR_MSEL(IP12_7_4,		AUDIO_CLKB_A,	SEL_ADGB_0),
-	PINMUX_IPSR_GPSR(IP12_7_4,		CTS1_N),
-	PINMUX_IPSR_MSEL(IP12_7_4,		RIF0_CLK_A,	SEL_DRIF0_0),
-	PINMUX_IPSR_MSEL(IP12_7_4,		REMOCON_A,	SEL_REMOCON_0),
-	PINMUX_IPSR_MSEL(IP12_7_4,		SCIF_CLK_B,	SEL_SCIF_1),
-
-	PINMUX_IPSR_MSEL(IP12_11_8,		TX2_A,		SEL_SCIF2_0),
-	PINMUX_IPSR_MSEL(IP12_11_8,		HRX0_A,		SEL_HSCIF0_0),
-	PINMUX_IPSR_GPSR(IP12_11_8,		AUDIO_CLKOUT2_A),
-	PINMUX_IPSR_MSEL(IP12_11_8,		SCL1_A,		SEL_I2C1_0),
-	PINMUX_IPSR_MSEL(IP12_11_8,		FSO_CFE_0_N_A,	SEL_FSO_0),
-	PINMUX_IPSR_GPSR(IP12_11_8,		TS_SDEN1),
-
-	PINMUX_IPSR_MSEL(IP12_15_12,		RX2_A,		SEL_SCIF2_0),
-	PINMUX_IPSR_GPSR(IP12_15_12,		HTX0_A),
-	PINMUX_IPSR_GPSR(IP12_15_12,		AUDIO_CLKOUT3_A),
-	PINMUX_IPSR_MSEL(IP12_15_12,		SDA1_A,		SEL_I2C1_0),
-	PINMUX_IPSR_MSEL(IP12_15_12,		FSO_CFE_1_N_A,	SEL_FSO_0),
-	PINMUX_IPSR_GPSR(IP12_15_12,		TS_SPSYNC1),
-
-	PINMUX_IPSR_GPSR(IP12_19_16,		MSIOF0_SCK),
-	PINMUX_IPSR_GPSR(IP12_19_16,		SSI_SCK78),
-
-	PINMUX_IPSR_GPSR(IP12_23_20,		MSIOF0_RXD),
-	PINMUX_IPSR_GPSR(IP12_23_20,		SSI_WS78),
-	PINMUX_IPSR_MSEL(IP12_23_20,		TX2_B,		SEL_SCIF2_1),
-
-	PINMUX_IPSR_GPSR(IP12_27_24,		MSIOF0_TXD),
-	PINMUX_IPSR_GPSR(IP12_27_24,		SSI_SDATA7),
-	PINMUX_IPSR_MSEL(IP12_27_24,		RX2_B,		SEL_SCIF2_1),
-
-	PINMUX_IPSR_GPSR(IP12_31_28,		MSIOF0_SYNC),
-	PINMUX_IPSR_GPSR(IP12_31_28,		AUDIO_CLKOUT_B),
-	PINMUX_IPSR_GPSR(IP12_31_28,		SSI_SDATA8),
-
-	/* IPSR13 */
-	PINMUX_IPSR_GPSR(IP13_3_0,		MSIOF0_SS1),
-	PINMUX_IPSR_MSEL(IP13_3_0,		HRX2_A,		SEL_HSCIF2_0),
-	PINMUX_IPSR_GPSR(IP13_3_0,		SSI_SCK4),
-	PINMUX_IPSR_MSEL(IP13_3_0,		HCTS0_N_A,	SEL_HSCIF0_0),
-	PINMUX_IPSR_GPSR(IP13_3_0,		BPFCLK_C),
-	PINMUX_IPSR_MSEL(IP13_3_0,		SPEEDIN_A,	SEL_SPEED_PULSE_IF_0),
-
-	PINMUX_IPSR_GPSR(IP13_7_4,		MSIOF0_SS2),
-	PINMUX_IPSR_GPSR(IP13_7_4,		HTX2_A),
-	PINMUX_IPSR_GPSR(IP13_7_4,		SSI_WS4),
-	PINMUX_IPSR_MSEL(IP13_7_4,		HRTS0_N_A,	SEL_HSCIF0_0),
-	PINMUX_IPSR_MSEL(IP13_7_4,		FMIN_C,		SEL_FM_2),
-	PINMUX_IPSR_GPSR(IP13_7_4,		BPFCLK_A),
-
-	PINMUX_IPSR_GPSR(IP13_11_8,		SSI_SDATA9),
-	PINMUX_IPSR_MSEL(IP13_11_8,		AUDIO_CLKC_A,	SEL_ADGC_0),
-	PINMUX_IPSR_GPSR(IP13_11_8,		SCK1),
-
-	PINMUX_IPSR_GPSR(IP13_15_12,		MLB_CLK),
-	PINMUX_IPSR_MSEL(IP13_15_12,		RX0_B,		SEL_SCIF0_1),
-	PINMUX_IPSR_MSEL(IP13_15_12,		RIF0_D0_A,	SEL_DRIF0_0),
-	PINMUX_IPSR_MSEL(IP13_15_12,		SCL1_B,		SEL_I2C1_1),
-	PINMUX_IPSR_MSEL(IP13_15_12,		TCLK1_B,	SEL_TIMER_TMU_1),
-	PINMUX_IPSR_GPSR(IP13_15_12,		SIM0_RST_A),
-
-	PINMUX_IPSR_GPSR(IP13_19_16,		MLB_SIG),
-	PINMUX_IPSR_MSEL(IP13_19_16,		SCK0_B,		SEL_SCIF0_1),
-	PINMUX_IPSR_MSEL(IP13_19_16,		RIF0_D1_A,	SEL_DRIF0_0),
-	PINMUX_IPSR_MSEL(IP13_19_16,		SDA1_B,		SEL_I2C1_1),
-	PINMUX_IPSR_MSEL(IP13_19_16,		TCLK2_B,	SEL_TIMER_TMU_1),
-	PINMUX_IPSR_MSEL(IP13_19_16,		SIM0_D_A,	SEL_SIMCARD_0),
-
-	PINMUX_IPSR_GPSR(IP13_23_20,		MLB_DAT),
-	PINMUX_IPSR_MSEL(IP13_23_20,		TX0_B,		SEL_SCIF0_1),
-	PINMUX_IPSR_MSEL(IP13_23_20,		RIF0_SYNC_A,	SEL_DRIF0_0),
-	PINMUX_IPSR_GPSR(IP13_23_20,		SIM0_CLK_A),
-
-	PINMUX_IPSR_GPSR(IP13_27_24,		SSI_SCK01239),
-
-	PINMUX_IPSR_GPSR(IP13_31_28,		SSI_WS01239),
-
-	/* IPSR14 */
-	PINMUX_IPSR_GPSR(IP14_3_0,		SSI_SDATA0),
-
-	PINMUX_IPSR_GPSR(IP14_7_4,		SSI_SDATA1),
-	PINMUX_IPSR_MSEL(IP14_7_4,		AUDIO_CLKC_B,	SEL_ADGC_1),
-	PINMUX_IPSR_MSEL(IP14_7_4,		PWM0_B,		SEL_PWM0_1),
-
-	PINMUX_IPSR_GPSR(IP14_11_8,		SSI_SDATA2),
-	PINMUX_IPSR_GPSR(IP14_11_8,		AUDIO_CLKOUT2_B),
-	PINMUX_IPSR_MSEL(IP14_11_8,		SSI_SCK9_A,	SEL_SSI9_0),
-	PINMUX_IPSR_MSEL(IP14_11_8,		PWM1_B,		SEL_PWM1_1),
-
-	PINMUX_IPSR_GPSR(IP14_15_12,		SSI_SCK349),
-	PINMUX_IPSR_MSEL(IP14_15_12,		PWM2_C,		SEL_PWM2_2),
-
-	PINMUX_IPSR_GPSR(IP14_19_16,		SSI_WS349),
-	PINMUX_IPSR_MSEL(IP14_19_16,		PWM3_C,		SEL_PWM3_2),
-
-	PINMUX_IPSR_GPSR(IP14_23_20,		SSI_SDATA3),
-	PINMUX_IPSR_GPSR(IP14_23_20,		AUDIO_CLKOUT1_C),
-	PINMUX_IPSR_MSEL(IP14_23_20,		AUDIO_CLKB_B,	SEL_ADGB_1),
-	PINMUX_IPSR_MSEL(IP14_23_20,		PWM4_B,		SEL_PWM4_1),
-
-	PINMUX_IPSR_GPSR(IP14_27_24,		SSI_SDATA4),
-	PINMUX_IPSR_MSEL(IP14_27_24,		SSI_WS9_A,	SEL_SSI9_0),
-	PINMUX_IPSR_MSEL(IP14_27_24,		PWM5_B,		SEL_PWM5_1),
-
-	PINMUX_IPSR_GPSR(IP14_31_28,		SSI_SCK5),
-	PINMUX_IPSR_MSEL(IP14_31_28,		HRX0_B,		SEL_HSCIF0_1),
-	PINMUX_IPSR_GPSR(IP14_31_28,		USB0_PWEN_B),
-	PINMUX_IPSR_MSEL(IP14_31_28,		SCL2_D,		SEL_I2C2_3),
-	PINMUX_IPSR_MSEL(IP14_31_28,		PWM6_B,		SEL_PWM6_1),
-
-	/* IPSR15 */
-	PINMUX_IPSR_GPSR(IP15_3_0,		SSI_WS5),
-	PINMUX_IPSR_GPSR(IP15_3_0,		HTX0_B),
-	PINMUX_IPSR_MSEL(IP15_3_0,		USB0_OVC_B,	SEL_USB_20_CH0_1),
-	PINMUX_IPSR_MSEL(IP15_3_0,		SDA2_D,		SEL_I2C2_3),
-
-	PINMUX_IPSR_GPSR(IP15_7_4,		SSI_SDATA5),
-	PINMUX_IPSR_MSEL(IP15_7_4,		HSCK0_B,	SEL_HSCIF0_1),
-	PINMUX_IPSR_MSEL(IP15_7_4,		AUDIO_CLKB_C,	SEL_ADGB_2),
-	PINMUX_IPSR_GPSR(IP15_7_4,		TPU0TO0),
-
-	PINMUX_IPSR_GPSR(IP15_11_8,		SSI_SCK6),
-	PINMUX_IPSR_MSEL(IP15_11_8,		HSCK2_A,	SEL_HSCIF2_0),
-	PINMUX_IPSR_MSEL(IP15_11_8,		AUDIO_CLKC_C,	SEL_ADGC_2),
-	PINMUX_IPSR_GPSR(IP15_11_8,		TPU0TO1),
-	PINMUX_IPSR_MSEL(IP15_11_8,		FSO_CFE_0_N_B,	SEL_FSO_1),
-	PINMUX_IPSR_GPSR(IP15_11_8,		SIM0_RST_B),
-
-	PINMUX_IPSR_GPSR(IP15_15_12,		SSI_WS6),
-	PINMUX_IPSR_MSEL(IP15_15_12,		HCTS2_N_A,	SEL_HSCIF2_0),
-	PINMUX_IPSR_GPSR(IP15_15_12,		AUDIO_CLKOUT2_C),
-	PINMUX_IPSR_GPSR(IP15_15_12,		TPU0TO2),
-	PINMUX_IPSR_MSEL(IP15_15_12,		SDA1_D,		SEL_I2C1_3),
-	PINMUX_IPSR_MSEL(IP15_15_12,		FSO_CFE_1_N_B,	SEL_FSO_1),
-	PINMUX_IPSR_MSEL(IP15_15_12,		SIM0_D_B,	SEL_SIMCARD_1),
-
-	PINMUX_IPSR_GPSR(IP15_19_16,		SSI_SDATA6),
-	PINMUX_IPSR_MSEL(IP15_19_16,		HRTS2_N_A,	SEL_HSCIF2_0),
-	PINMUX_IPSR_GPSR(IP15_19_16,		AUDIO_CLKOUT3_C),
-	PINMUX_IPSR_GPSR(IP15_19_16,		TPU0TO3),
-	PINMUX_IPSR_MSEL(IP15_19_16,		SCL1_D,		SEL_I2C1_3),
-	PINMUX_IPSR_MSEL(IP15_19_16,		FSO_TOE_N_B,	SEL_FSO_1),
-	PINMUX_IPSR_GPSR(IP15_19_16,		SIM0_CLK_B),
-
-	PINMUX_IPSR_GPSR(IP15_23_20,		AUDIO_CLKA),
-
-	PINMUX_IPSR_GPSR(IP15_27_24,		USB30_PWEN),
-	PINMUX_IPSR_GPSR(IP15_27_24,		USB0_PWEN_A),
-
-	PINMUX_IPSR_GPSR(IP15_31_28,		USB30_OVC),
-	PINMUX_IPSR_MSEL(IP15_31_28,		USB0_OVC_A,	SEL_USB_20_CH0_0),
-
-/*
- * Static pins can not be muxed between different functions but
- * still need mark entries in the pinmux list. Add each static
- * pin to the list without an associated function. The sh-pfc
- * core will do the right thing and skip trying to mux the pin
- * while still applying configuration to it.
- */
-#define FM(x)   PINMUX_DATA(x##_MARK, 0),
-	PINMUX_STATIC
-#undef FM
-};
-
-/*
- * Pins not associated with a GPIO port.
- */
-enum {
-	GP_ASSIGN_LAST(),
-	NOGP_ALL(),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	PINMUX_GPIO_GP_ALL(),
-	PINMUX_NOGP_ALL(),
-};
-
-/* - AUDIO CLOCK ------------------------------------------------------------ */
-static const unsigned int audio_clk_a_pins[] = {
-	/* CLK A */
-	RCAR_GP_PIN(6, 8),
-};
-
-static const unsigned int audio_clk_a_mux[] = {
-	AUDIO_CLKA_MARK,
-};
-
-static const unsigned int audio_clk_b_a_pins[] = {
-	/* CLK B_A */
-	RCAR_GP_PIN(5, 7),
-};
-
-static const unsigned int audio_clk_b_a_mux[] = {
-	AUDIO_CLKB_A_MARK,
-};
-
-static const unsigned int audio_clk_b_b_pins[] = {
-	/* CLK B_B */
-	RCAR_GP_PIN(6, 7),
-};
-
-static const unsigned int audio_clk_b_b_mux[] = {
-	AUDIO_CLKB_B_MARK,
-};
-
-static const unsigned int audio_clk_b_c_pins[] = {
-	/* CLK B_C */
-	RCAR_GP_PIN(6, 13),
-};
-
-static const unsigned int audio_clk_b_c_mux[] = {
-	AUDIO_CLKB_C_MARK,
-};
-
-static const unsigned int audio_clk_c_a_pins[] = {
-	/* CLK C_A */
-	RCAR_GP_PIN(5, 16),
-};
-
-static const unsigned int audio_clk_c_a_mux[] = {
-	AUDIO_CLKC_A_MARK,
-};
-
-static const unsigned int audio_clk_c_b_pins[] = {
-	/* CLK C_B */
-	RCAR_GP_PIN(6, 3),
-};
-
-static const unsigned int audio_clk_c_b_mux[] = {
-	AUDIO_CLKC_B_MARK,
-};
-
-static const unsigned int audio_clk_c_c_pins[] = {
-	/* CLK C_C */
-	RCAR_GP_PIN(6, 14),
-};
-
-static const unsigned int audio_clk_c_c_mux[] = {
-	AUDIO_CLKC_C_MARK,
-};
-
-static const unsigned int audio_clkout_a_pins[] = {
-	/* CLKOUT_A */
-	RCAR_GP_PIN(5, 3),
-};
-
-static const unsigned int audio_clkout_a_mux[] = {
-	AUDIO_CLKOUT_A_MARK,
-};
-
-static const unsigned int audio_clkout_b_pins[] = {
-	/* CLKOUT_B */
-	RCAR_GP_PIN(5, 13),
-};
-
-static const unsigned int audio_clkout_b_mux[] = {
-	AUDIO_CLKOUT_B_MARK,
-};
-
-static const unsigned int audio_clkout1_a_pins[] = {
-	/* CLKOUT1_A */
-	RCAR_GP_PIN(5, 4),
-};
-
-static const unsigned int audio_clkout1_a_mux[] = {
-	AUDIO_CLKOUT1_A_MARK,
-};
-
-static const unsigned int audio_clkout1_b_pins[] = {
-	/* CLKOUT1_B */
-	RCAR_GP_PIN(5, 5),
-};
-
-static const unsigned int audio_clkout1_b_mux[] = {
-	AUDIO_CLKOUT1_B_MARK,
-};
-
-static const unsigned int audio_clkout1_c_pins[] = {
-	/* CLKOUT1_C */
-	RCAR_GP_PIN(6, 7),
-};
-
-static const unsigned int audio_clkout1_c_mux[] = {
-	AUDIO_CLKOUT1_C_MARK,
-};
-
-static const unsigned int audio_clkout2_a_pins[] = {
-	/* CLKOUT2_A */
-	RCAR_GP_PIN(5, 8),
-};
-
-static const unsigned int audio_clkout2_a_mux[] = {
-	AUDIO_CLKOUT2_A_MARK,
-};
-
-static const unsigned int audio_clkout2_b_pins[] = {
-	/* CLKOUT2_B */
-	RCAR_GP_PIN(6, 4),
-};
-
-static const unsigned int audio_clkout2_b_mux[] = {
-	AUDIO_CLKOUT2_B_MARK,
-};
-
-static const unsigned int audio_clkout2_c_pins[] = {
-	/* CLKOUT2_C */
-	RCAR_GP_PIN(6, 15),
-};
-
-static const unsigned int audio_clkout2_c_mux[] = {
-	AUDIO_CLKOUT2_C_MARK,
-};
-
-static const unsigned int audio_clkout3_a_pins[] = {
-	/* CLKOUT3_A */
-	RCAR_GP_PIN(5, 9),
-};
-
-static const unsigned int audio_clkout3_a_mux[] = {
-	AUDIO_CLKOUT3_A_MARK,
-};
-
-static const unsigned int audio_clkout3_b_pins[] = {
-	/* CLKOUT3_B */
-	RCAR_GP_PIN(5, 6),
-};
-
-static const unsigned int audio_clkout3_b_mux[] = {
-	AUDIO_CLKOUT3_B_MARK,
-};
-
-static const unsigned int audio_clkout3_c_pins[] = {
-	/* CLKOUT3_C */
-	RCAR_GP_PIN(6, 16),
-};
-
-static const unsigned int audio_clkout3_c_mux[] = {
-	AUDIO_CLKOUT3_C_MARK,
-};
-
-/* - EtherAVB --------------------------------------------------------------- */
-static const unsigned int avb_link_pins[] = {
-	/* AVB_LINK */
-	RCAR_GP_PIN(2, 23),
-};
-
-static const unsigned int avb_link_mux[] = {
-	AVB_LINK_MARK,
-};
-
-static const unsigned int avb_magic_pins[] = {
-	/* AVB_MAGIC */
-	RCAR_GP_PIN(2, 22),
-};
-
-static const unsigned int avb_magic_mux[] = {
-	AVB_MAGIC_MARK,
-};
-
-static const unsigned int avb_phy_int_pins[] = {
-	/* AVB_PHY_INT */
-	RCAR_GP_PIN(2, 21),
-};
-
-static const unsigned int avb_phy_int_mux[] = {
-	AVB_PHY_INT_MARK,
-};
-
-static const unsigned int avb_mii_pins[] = {
-	/*
-	 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
-	 * AVB_RD1, AVB_RD2, AVB_RD3,
-	 * AVB_TXCREFCLK
-	 */
-	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
-	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
-	RCAR_GP_PIN(2, 20),
-};
-
-static const unsigned int avb_mii_mux[] = {
-	AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
-	AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
-	AVB_TXCREFCLK_MARK,
-};
-
-static const unsigned int avb_avtp_pps_pins[] = {
-	/* AVB_AVTP_PPS */
-	RCAR_GP_PIN(1, 2),
-};
-
-static const unsigned int avb_avtp_pps_mux[] = {
-	AVB_AVTP_PPS_MARK,
-};
-
-static const unsigned int avb_avtp_match_pins[] = {
-	/* AVB_AVTP_MATCH */
-	RCAR_GP_PIN(2, 24),
-};
-
-static const unsigned int avb_avtp_match_mux[] = {
-	AVB_AVTP_MATCH_MARK,
-};
-
-static const unsigned int avb_avtp_capture_pins[] = {
-	/* AVB_AVTP_CAPTURE */
-	RCAR_GP_PIN(2, 25),
-};
-
-static const unsigned int avb_avtp_capture_mux[] = {
-	AVB_AVTP_CAPTURE_MARK,
-};
-
-/* - CAN ------------------------------------------------------------------ */
-static const unsigned int can0_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-};
-
-static const unsigned int can0_data_mux[] = {
-	CAN0_TX_MARK, CAN0_RX_MARK,
-};
-
-static const unsigned int can1_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
-};
-
-static const unsigned int can1_data_mux[] = {
-	CAN1_TX_MARK, CAN1_RX_MARK,
-};
-
-/* - CAN Clock -------------------------------------------------------------- */
-static const unsigned int can_clk_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(0, 14),
-};
-
-static const unsigned int can_clk_mux[] = {
-	CAN_CLK_MARK,
-};
-
-/* - CAN FD --------------------------------------------------------------- */
-static const unsigned int canfd0_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-};
-
-static const unsigned int canfd0_data_mux[] = {
-	CANFD0_TX_MARK, CANFD0_RX_MARK,
-};
-
-static const unsigned int canfd1_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
-};
-
-static const unsigned int canfd1_data_mux[] = {
-	CANFD1_TX_MARK, CANFD1_RX_MARK,
-};
-
-/* - DRIF0 --------------------------------------------------------------- */
-static const unsigned int drif0_ctrl_a_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 19),
-};
-
-static const unsigned int drif0_ctrl_a_mux[] = {
-	RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
-};
-
-static const unsigned int drif0_data0_a_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(5, 17),
-};
-
-static const unsigned int drif0_data0_a_mux[] = {
-	RIF0_D0_A_MARK,
-};
-
-static const unsigned int drif0_data1_a_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(5, 18),
-};
-
-static const unsigned int drif0_data1_a_mux[] = {
-	RIF0_D1_A_MARK,
-};
-
-static const unsigned int drif0_ctrl_b_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
-};
-
-static const unsigned int drif0_ctrl_b_mux[] = {
-	RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
-};
-
-static const unsigned int drif0_data0_b_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 13),
-};
-
-static const unsigned int drif0_data0_b_mux[] = {
-	RIF0_D0_B_MARK,
-};
-
-static const unsigned int drif0_data1_b_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(3, 14),
-};
-
-static const unsigned int drif0_data1_b_mux[] = {
-	RIF0_D1_B_MARK,
-};
-
-/* - DRIF1 --------------------------------------------------------------- */
-static const unsigned int drif1_ctrl_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 1),
-};
-
-static const unsigned int drif1_ctrl_mux[] = {
-	RIF1_CLK_MARK, RIF1_SYNC_MARK,
-};
-
-static const unsigned int drif1_data0_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(5, 2),
-};
-
-static const unsigned int drif1_data0_mux[] = {
-	RIF1_D0_MARK,
-};
-
-static const unsigned int drif1_data1_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(5, 3),
-};
-
-static const unsigned int drif1_data1_mux[] = {
-	RIF1_D1_MARK,
-};
-
-/* - DRIF2 --------------------------------------------------------------- */
-static const unsigned int drif2_ctrl_a_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-};
-
-static const unsigned int drif2_ctrl_a_mux[] = {
-	RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
-};
-
-static const unsigned int drif2_data0_a_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(2, 8),
-};
-
-static const unsigned int drif2_data0_a_mux[] = {
-	RIF2_D0_A_MARK,
-};
-
-static const unsigned int drif2_data1_a_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(2, 9),
-};
-
-static const unsigned int drif2_data1_a_mux[] = {
-	RIF2_D1_A_MARK,
-};
-
-static const unsigned int drif2_ctrl_b_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-};
-
-static const unsigned int drif2_ctrl_b_mux[] = {
-	RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
-};
-
-static const unsigned int drif2_data0_b_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(1, 6),
-};
-
-static const unsigned int drif2_data0_b_mux[] = {
-	RIF2_D0_B_MARK,
-};
-
-static const unsigned int drif2_data1_b_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(1, 7),
-};
-
-static const unsigned int drif2_data1_b_mux[] = {
-	RIF2_D1_B_MARK,
-};
-
-/* - DRIF3 --------------------------------------------------------------- */
-static const unsigned int drif3_ctrl_a_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
-};
-
-static const unsigned int drif3_ctrl_a_mux[] = {
-	RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
-};
-
-static const unsigned int drif3_data0_a_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(2, 12),
-};
-
-static const unsigned int drif3_data0_a_mux[] = {
-	RIF3_D0_A_MARK,
-};
-
-static const unsigned int drif3_data1_a_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(2, 13),
-};
-
-static const unsigned int drif3_data1_a_mux[] = {
-	RIF3_D1_A_MARK,
-};
-
-static const unsigned int drif3_ctrl_b_pins[] = {
-	/* CLK, SYNC */
-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-};
-
-static const unsigned int drif3_ctrl_b_mux[] = {
-	RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
-};
-
-static const unsigned int drif3_data0_b_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(0, 10),
-};
-
-static const unsigned int drif3_data0_b_mux[] = {
-	RIF3_D0_B_MARK,
-};
-
-static const unsigned int drif3_data1_b_pins[] = {
-	/* D1 */
-	RCAR_GP_PIN(0, 11),
-};
-
-static const unsigned int drif3_data1_b_mux[] = {
-	RIF3_D1_B_MARK,
-};
-
-/* - DU --------------------------------------------------------------------- */
-static const unsigned int du_rgb666_pins[] = {
-	/* R[7:2], G[7:2], B[7:2] */
-	RCAR_GP_PIN(0, 8),  RCAR_GP_PIN(0, 6),  RCAR_GP_PIN(0, 5),
-	RCAR_GP_PIN(0, 3),  RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 0),
-	RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
-	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
-	RCAR_GP_PIN(0, 1),  RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
-	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
-};
-static const unsigned int du_rgb666_mux[] = {
-	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
-	DU_DR3_MARK, DU_DR2_MARK,
-	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
-	DU_DG3_MARK, DU_DG2_MARK,
-	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
-	DU_DB3_MARK, DU_DB2_MARK,
-};
-static const unsigned int du_rgb888_pins[] = {
-	/* R[7:0], G[7:0], B[7:0] */
-	RCAR_GP_PIN(0, 8),  RCAR_GP_PIN(0, 6),  RCAR_GP_PIN(0, 5),
-	RCAR_GP_PIN(0, 3),  RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 0),
-	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
-	RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
-	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
-	RCAR_GP_PIN(0, 1),  RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
-	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
-	RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
-};
-static const unsigned int du_rgb888_mux[] = {
-	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
-	DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
-	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
-	DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
-	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
-	DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
-};
-static const unsigned int du_clk_in_0_pins[] = {
-	/* CLKIN0 */
-	RCAR_GP_PIN(0, 16),
-};
-static const unsigned int du_clk_in_0_mux[] = {
-	DU_DOTCLKIN0_MARK
-};
-static const unsigned int du_clk_in_1_pins[] = {
-	/* CLKIN1 */
-	RCAR_GP_PIN(1, 1),
-};
-static const unsigned int du_clk_in_1_mux[] = {
-	DU_DOTCLKIN1_MARK
-};
-static const unsigned int du_clk_out_0_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(1, 3),
-};
-static const unsigned int du_clk_out_0_mux[] = {
-	DU_DOTCLKOUT0_MARK
-};
-static const unsigned int du_sync_pins[] = {
-	/* VSYNC, HSYNC */
-	RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
-};
-static const unsigned int du_sync_mux[] = {
-	DU_VSYNC_MARK, DU_HSYNC_MARK
-};
-static const unsigned int du_disp_cde_pins[] = {
-	/* DISP_CDE */
-	RCAR_GP_PIN(1, 1),
-};
-static const unsigned int du_disp_cde_mux[] = {
-	DU_DISP_CDE_MARK,
-};
-static const unsigned int du_cde_pins[] = {
-	/* CDE */
-	RCAR_GP_PIN(1, 0),
-};
-static const unsigned int du_cde_mux[] = {
-	DU_CDE_MARK,
-};
-static const unsigned int du_disp_pins[] = {
-	/* DISP */
-	RCAR_GP_PIN(1, 2),
-};
-static const unsigned int du_disp_mux[] = {
-	DU_DISP_MARK,
-};
-
-/* - HSCIF0 --------------------------------------------------*/
-static const unsigned int hscif0_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
-};
-
-static const unsigned int hscif0_data_a_mux[] = {
-	HRX0_A_MARK, HTX0_A_MARK,
-};
-
-static const unsigned int hscif0_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 7),
-};
-
-static const unsigned int hscif0_clk_a_mux[] = {
-	HSCK0_A_MARK,
-};
-
-static const unsigned int hscif0_ctrl_a_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
-};
-
-static const unsigned int hscif0_ctrl_a_mux[] = {
-	HRTS0_N_A_MARK, HCTS0_N_A_MARK,
-};
-
-static const unsigned int hscif0_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
-};
-
-static const unsigned int hscif0_data_b_mux[] = {
-	HRX0_B_MARK, HTX0_B_MARK,
-};
-
-static const unsigned int hscif0_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 13),
-};
-
-static const unsigned int hscif0_clk_b_mux[] = {
-	HSCK0_B_MARK,
-};
-
-/* - HSCIF1 ------------------------------------------------- */
-static const unsigned int hscif1_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-};
-
-static const unsigned int hscif1_data_a_mux[] = {
-	HRX1_A_MARK, HTX1_A_MARK,
-};
-
-static const unsigned int hscif1_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 0),
-};
-
-static const unsigned int hscif1_clk_a_mux[] = {
-	HSCK1_A_MARK,
-};
-
-static const unsigned int hscif1_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
-};
-
-static const unsigned int hscif1_data_b_mux[] = {
-	HRX1_B_MARK, HTX1_B_MARK,
-};
-
-static const unsigned int hscif1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 0),
-};
-
-static const unsigned int hscif1_clk_b_mux[] = {
-	HSCK1_B_MARK,
-};
-
-static const unsigned int hscif1_ctrl_b_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
-};
-
-static const unsigned int hscif1_ctrl_b_mux[] = {
-	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
-};
-
-/* - HSCIF2 ------------------------------------------------- */
-static const unsigned int hscif2_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
-};
-
-static const unsigned int hscif2_data_a_mux[] = {
-	HRX2_A_MARK, HTX2_A_MARK,
-};
-
-static const unsigned int hscif2_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(6, 14),
-};
-
-static const unsigned int hscif2_clk_a_mux[] = {
-	HSCK2_A_MARK,
-};
-
-static const unsigned int hscif2_ctrl_a_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
-};
-
-static const unsigned int hscif2_ctrl_a_mux[] = {
-	HRTS2_N_A_MARK, HCTS2_N_A_MARK,
-};
-
-static const unsigned int hscif2_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
-};
-
-static const unsigned int hscif2_data_b_mux[] = {
-	HRX2_B_MARK, HTX2_B_MARK,
-};
-
-/* - HSCIF3 ------------------------------------------------*/
-static const unsigned int hscif3_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-};
-
-static const unsigned int hscif3_data_a_mux[] = {
-	HRX3_A_MARK, HTX3_A_MARK,
-};
-
-static const unsigned int hscif3_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
-};
-
-static const unsigned int hscif3_data_b_mux[] = {
-	HRX3_B_MARK, HTX3_B_MARK,
-};
-
-static const unsigned int hscif3_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 4),
-};
-
-static const unsigned int hscif3_clk_b_mux[] = {
-	HSCK3_B_MARK,
-};
-
-static const unsigned int hscif3_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9),
-};
-
-static const unsigned int hscif3_data_c_mux[] = {
-	HRX3_C_MARK, HTX3_C_MARK,
-};
-
-static const unsigned int hscif3_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 11),
-};
-
-static const unsigned int hscif3_clk_c_mux[] = {
-	HSCK3_C_MARK,
-};
-
-static const unsigned int hscif3_ctrl_c_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
-};
-
-static const unsigned int hscif3_ctrl_c_mux[] = {
-	HRTS3_N_C_MARK, HCTS3_N_C_MARK,
-};
-
-static const unsigned int hscif3_data_d_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 3),
-};
-
-static const unsigned int hscif3_data_d_mux[] = {
-	HRX3_D_MARK, HTX3_D_MARK,
-};
-
-static const unsigned int hscif3_data_e_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
-};
-
-static const unsigned int hscif3_data_e_mux[] = {
-	HRX3_E_MARK, HTX3_E_MARK,
-};
-
-static const unsigned int hscif3_ctrl_e_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 8),
-};
-
-static const unsigned int hscif3_ctrl_e_mux[] = {
-	HRTS3_N_E_MARK, HCTS3_N_E_MARK,
-};
-
-/* - HSCIF4 -------------------------------------------------- */
-static const unsigned int hscif4_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
-};
-
-static const unsigned int hscif4_data_a_mux[] = {
-	HRX4_A_MARK, HTX4_A_MARK,
-};
-
-static const unsigned int hscif4_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 0),
-};
-
-static const unsigned int hscif4_clk_a_mux[] = {
-	HSCK4_A_MARK,
-};
-
-static const unsigned int hscif4_ctrl_a_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
-};
-
-static const unsigned int hscif4_ctrl_a_mux[] = {
-	HRTS4_N_A_MARK, HCTS4_N_A_MARK,
-};
-
-static const unsigned int hscif4_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
-};
-
-static const unsigned int hscif4_data_b_mux[] = {
-	HRX4_B_MARK, HTX4_B_MARK,
-};
-
-static const unsigned int hscif4_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 6),
-};
-
-static const unsigned int hscif4_clk_b_mux[] = {
-	HSCK4_B_MARK,
-};
-
-static const unsigned int hscif4_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
-};
-
-static const unsigned int hscif4_data_c_mux[] = {
-	HRX4_C_MARK, HTX4_C_MARK,
-};
-
-static const unsigned int hscif4_data_d_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
-};
-
-static const unsigned int hscif4_data_d_mux[] = {
-	HRX4_D_MARK, HTX4_D_MARK,
-};
-
-static const unsigned int hscif4_data_e_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
-};
-
-static const unsigned int hscif4_data_e_mux[] = {
-	HRX4_E_MARK, HTX4_E_MARK,
-};
-
-/* - I2C -------------------------------------------------------------------- */
-static const unsigned int i2c1_a_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
-};
-
-static const unsigned int i2c1_a_mux[] = {
-	SCL1_A_MARK, SDA1_A_MARK,
-};
-
-static const unsigned int i2c1_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
-};
-
-static const unsigned int i2c1_b_mux[] = {
-	SCL1_B_MARK, SDA1_B_MARK,
-};
-
-static const unsigned int i2c1_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 5),
-};
-
-static const unsigned int i2c1_c_mux[] = {
-	SCL1_C_MARK, SDA1_C_MARK,
-};
-
-static const unsigned int i2c1_d_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
-};
-
-static const unsigned int i2c1_d_mux[] = {
-	SCL1_D_MARK, SDA1_D_MARK,
-};
-
-static const unsigned int i2c2_a_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 0),
-};
-
-static const unsigned int i2c2_a_mux[] = {
-	SCL2_A_MARK, SDA2_A_MARK,
-};
-
-static const unsigned int i2c2_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
-};
-
-static const unsigned int i2c2_b_mux[] = {
-	SCL2_B_MARK, SDA2_B_MARK,
-};
-
-static const unsigned int i2c2_c_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
-};
-
-static const unsigned int i2c2_c_mux[] = {
-	SCL2_C_MARK, SDA2_C_MARK,
-};
-
-static const unsigned int i2c2_d_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
-};
-
-static const unsigned int i2c2_d_mux[] = {
-	SCL2_D_MARK, SDA2_D_MARK,
-};
-
-static const unsigned int i2c2_e_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
-};
-
-static const unsigned int i2c2_e_mux[] = {
-	SCL2_E_MARK, SDA2_E_MARK,
-};
-
-static const unsigned int i2c4_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
-};
-
-static const unsigned int i2c4_mux[] = {
-	SCL4_MARK, SDA4_MARK,
-};
-
-static const unsigned int i2c5_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
-};
-
-static const unsigned int i2c5_mux[] = {
-	SCL5_MARK, SDA5_MARK,
-};
-
-static const unsigned int i2c6_a_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
-};
-
-static const unsigned int i2c6_a_mux[] = {
-	SCL6_A_MARK, SDA6_A_MARK,
-};
-
-static const unsigned int i2c6_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
-};
-
-static const unsigned int i2c6_b_mux[] = {
-	SCL6_B_MARK, SDA6_B_MARK,
-};
-
-static const unsigned int i2c7_a_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25),
-};
-
-static const unsigned int i2c7_a_mux[] = {
-	SCL7_A_MARK, SDA7_A_MARK,
-};
-
-static const unsigned int i2c7_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
-};
-
-static const unsigned int i2c7_b_mux[] = {
-	SCL7_B_MARK, SDA7_B_MARK,
-};
-
-/* - INTC-EX ---------------------------------------------------------------- */
-static const unsigned int intc_ex_irq0_pins[] = {
-	/* IRQ0 */
-	RCAR_GP_PIN(1, 0),
-};
-static const unsigned int intc_ex_irq0_mux[] = {
-	IRQ0_MARK,
-};
-static const unsigned int intc_ex_irq1_pins[] = {
-	/* IRQ1 */
-	RCAR_GP_PIN(1, 1),
-};
-static const unsigned int intc_ex_irq1_mux[] = {
-	IRQ1_MARK,
-};
-static const unsigned int intc_ex_irq2_pins[] = {
-	/* IRQ2 */
-	RCAR_GP_PIN(1, 2),
-};
-static const unsigned int intc_ex_irq2_mux[] = {
-	IRQ2_MARK,
-};
-static const unsigned int intc_ex_irq3_pins[] = {
-	/* IRQ3 */
-	RCAR_GP_PIN(1, 9),
-};
-static const unsigned int intc_ex_irq3_mux[] = {
-	IRQ3_MARK,
-};
-static const unsigned int intc_ex_irq4_pins[] = {
-	/* IRQ4 */
-	RCAR_GP_PIN(1, 10),
-};
-static const unsigned int intc_ex_irq4_mux[] = {
-	IRQ4_MARK,
-};
-static const unsigned int intc_ex_irq5_pins[] = {
-	/* IRQ5 */
-	RCAR_GP_PIN(0, 7),
-};
-static const unsigned int intc_ex_irq5_mux[] = {
-	IRQ5_MARK,
-};
-
-/* - MSIOF0 ----------------------------------------------------------------- */
-static const unsigned int msiof0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 10),
-};
-
-static const unsigned int msiof0_clk_mux[] = {
-	MSIOF0_SCK_MARK,
-};
-
-static const unsigned int msiof0_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(5, 13),
-};
-
-static const unsigned int msiof0_sync_mux[] = {
-	MSIOF0_SYNC_MARK,
-};
-
-static const unsigned int msiof0_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(5, 14),
-};
-
-static const unsigned int msiof0_ss1_mux[] = {
-	MSIOF0_SS1_MARK,
-};
-
-static const unsigned int msiof0_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(5, 15),
-};
-
-static const unsigned int msiof0_ss2_mux[] = {
-	MSIOF0_SS2_MARK,
-};
-
-static const unsigned int msiof0_txd_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(5, 12),
-};
-
-static const unsigned int msiof0_txd_mux[] = {
-	MSIOF0_TXD_MARK,
-};
-
-static const unsigned int msiof0_rxd_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(5, 11),
-};
-
-static const unsigned int msiof0_rxd_mux[] = {
-	MSIOF0_RXD_MARK,
-};
-
-/* - MSIOF1 ----------------------------------------------------------------- */
-static const unsigned int msiof1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 19),
-};
-
-static const unsigned int msiof1_clk_mux[] = {
-	MSIOF1_SCK_MARK,
-};
-
-static const unsigned int msiof1_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 16),
-};
-
-static const unsigned int msiof1_sync_mux[] = {
-	MSIOF1_SYNC_MARK,
-};
-
-static const unsigned int msiof1_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(1, 14),
-};
-
-static const unsigned int msiof1_ss1_mux[] = {
-	MSIOF1_SS1_MARK,
-};
-
-static const unsigned int msiof1_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(1, 15),
-};
-
-static const unsigned int msiof1_ss2_mux[] = {
-	MSIOF1_SS2_MARK,
-};
-
-static const unsigned int msiof1_txd_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 18),
-};
-
-static const unsigned int msiof1_txd_mux[] = {
-	MSIOF1_TXD_MARK,
-};
-
-static const unsigned int msiof1_rxd_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 17),
-};
-
-static const unsigned int msiof1_rxd_mux[] = {
-	MSIOF1_RXD_MARK,
-};
-
-/* - MSIOF2 ----------------------------------------------------------------- */
-static const unsigned int msiof2_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 8),
-};
-
-static const unsigned int msiof2_clk_a_mux[] = {
-	MSIOF2_SCK_A_MARK,
-};
-
-static const unsigned int msiof2_sync_a_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 9),
-};
-
-static const unsigned int msiof2_sync_a_mux[] = {
-	MSIOF2_SYNC_A_MARK,
-};
-
-static const unsigned int msiof2_ss1_a_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 15),
-};
-
-static const unsigned int msiof2_ss1_a_mux[] = {
-	MSIOF2_SS1_A_MARK,
-};
-
-static const unsigned int msiof2_ss2_a_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 14),
-};
-
-static const unsigned int msiof2_ss2_a_mux[] = {
-	MSIOF2_SS2_A_MARK,
-};
-
-static const unsigned int msiof2_txd_a_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 11),
-};
-
-static const unsigned int msiof2_txd_a_mux[] = {
-	MSIOF2_TXD_A_MARK,
-};
-
-static const unsigned int msiof2_rxd_a_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 10),
-};
-
-static const unsigned int msiof2_rxd_a_mux[] = {
-	MSIOF2_RXD_A_MARK,
-};
-
-static const unsigned int msiof2_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 13),
-};
-
-static const unsigned int msiof2_clk_b_mux[] = {
-	MSIOF2_SCK_B_MARK,
-};
-
-static const unsigned int msiof2_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 10),
-};
-
-static const unsigned int msiof2_sync_b_mux[] = {
-	MSIOF2_SYNC_B_MARK,
-};
-
-static const unsigned int msiof2_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(1, 16),
-};
-
-static const unsigned int msiof2_ss1_b_mux[] = {
-	MSIOF2_SS1_B_MARK,
-};
-
-static const unsigned int msiof2_ss2_b_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(1, 12),
-};
-
-static const unsigned int msiof2_ss2_b_mux[] = {
-	MSIOF2_SS2_B_MARK,
-};
-
-static const unsigned int msiof2_txd_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 15),
-};
-
-static const unsigned int msiof2_txd_b_mux[] = {
-	MSIOF2_TXD_B_MARK,
-};
-
-static const unsigned int msiof2_rxd_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 14),
-};
-
-static const unsigned int msiof2_rxd_b_mux[] = {
-	MSIOF2_RXD_B_MARK,
-};
-
-/* - MSIOF3 ----------------------------------------------------------------- */
-static const unsigned int msiof3_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 0),
-};
-
-static const unsigned int msiof3_clk_a_mux[] = {
-	MSIOF3_SCK_A_MARK,
-};
-
-static const unsigned int msiof3_sync_a_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 1),
-};
-
-static const unsigned int msiof3_sync_a_mux[] = {
-	MSIOF3_SYNC_A_MARK,
-};
-
-static const unsigned int msiof3_ss1_a_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 15),
-};
-
-static const unsigned int msiof3_ss1_a_mux[] = {
-	MSIOF3_SS1_A_MARK,
-};
-
-static const unsigned int msiof3_ss2_a_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 4),
-};
-
-static const unsigned int msiof3_ss2_a_mux[] = {
-	MSIOF3_SS2_A_MARK,
-};
-
-static const unsigned int msiof3_txd_a_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 3),
-};
-
-static const unsigned int msiof3_txd_a_mux[] = {
-	MSIOF3_TXD_A_MARK,
-};
-
-static const unsigned int msiof3_rxd_a_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 2),
-};
-
-static const unsigned int msiof3_rxd_a_mux[] = {
-	MSIOF3_RXD_A_MARK,
-};
-
-static const unsigned int msiof3_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 5),
-};
-
-static const unsigned int msiof3_clk_b_mux[] = {
-	MSIOF3_SCK_B_MARK,
-};
-
-static const unsigned int msiof3_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 4),
-};
-
-static const unsigned int msiof3_sync_b_mux[] = {
-	MSIOF3_SYNC_B_MARK,
-};
-
-static const unsigned int msiof3_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(1, 0),
-};
-
-static const unsigned int msiof3_ss1_b_mux[] = {
-	MSIOF3_SS1_B_MARK,
-};
-
-static const unsigned int msiof3_txd_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 7),
-};
-
-static const unsigned int msiof3_txd_b_mux[] = {
-	MSIOF3_TXD_B_MARK,
-};
-
-static const unsigned int msiof3_rxd_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 6),
-};
-
-static const unsigned int msiof3_rxd_b_mux[] = {
-	MSIOF3_RXD_B_MARK,
-};
-
-/* - PWM0 --------------------------------------------------------------------*/
-static const unsigned int pwm0_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 22),
-};
-
-static const unsigned int pwm0_a_mux[] = {
-	PWM0_A_MARK,
-};
-
-static const unsigned int pwm0_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(6, 3),
-};
-
-static const unsigned int pwm0_b_mux[] = {
-	PWM0_B_MARK,
-};
-
-/* - PWM1 --------------------------------------------------------------------*/
-static const unsigned int pwm1_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 23),
-};
-
-static const unsigned int pwm1_a_mux[] = {
-	PWM1_A_MARK,
-};
-
-static const unsigned int pwm1_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(6, 4),
-};
-
-static const unsigned int pwm1_b_mux[] = {
-	PWM1_B_MARK,
-};
-
-/* - PWM2 --------------------------------------------------------------------*/
-static const unsigned int pwm2_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 0),
-};
-
-static const unsigned int pwm2_a_mux[] = {
-	PWM2_A_MARK,
-};
-
-static const unsigned int pwm2_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 4),
-};
-
-static const unsigned int pwm2_b_mux[] = {
-	PWM2_B_MARK,
-};
-
-static const unsigned int pwm2_c_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(6, 5),
-};
-
-static const unsigned int pwm2_c_mux[] = {
-	PWM2_C_MARK,
-};
-
-/* - PWM3 --------------------------------------------------------------------*/
-static const unsigned int pwm3_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 1),
-};
-
-static const unsigned int pwm3_a_mux[] = {
-	PWM3_A_MARK,
-};
-
-static const unsigned int pwm3_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 5),
-};
-
-static const unsigned int pwm3_b_mux[] = {
-	PWM3_B_MARK,
-};
-
-static const unsigned int pwm3_c_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(6, 6),
-};
-
-static const unsigned int pwm3_c_mux[] = {
-	PWM3_C_MARK,
-};
-
-/* - PWM4 --------------------------------------------------------------------*/
-static const unsigned int pwm4_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 3),
-};
-
-static const unsigned int pwm4_a_mux[] = {
-	PWM4_A_MARK,
-};
-
-static const unsigned int pwm4_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(6, 7),
-};
-
-static const unsigned int pwm4_b_mux[] = {
-	PWM4_B_MARK,
-};
-
-/* - PWM5 --------------------------------------------------------------------*/
-static const unsigned int pwm5_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 24),
-};
-
-static const unsigned int pwm5_a_mux[] = {
-	PWM5_A_MARK,
-};
-
-static const unsigned int pwm5_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(6, 10),
-};
-
-static const unsigned int pwm5_b_mux[] = {
-	PWM5_B_MARK,
-};
-
-/* - PWM6 --------------------------------------------------------------------*/
-static const unsigned int pwm6_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 25),
-};
-
-static const unsigned int pwm6_a_mux[] = {
-	PWM6_A_MARK,
-};
-
-static const unsigned int pwm6_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(6, 11),
-};
-
-static const unsigned int pwm6_b_mux[] = {
-	PWM6_B_MARK,
-};
-
-/* - SCIF0 ------------------------------------------------------------------ */
-static const unsigned int scif0_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-};
-
-static const unsigned int scif0_data_a_mux[] = {
-	RX0_A_MARK, TX0_A_MARK,
-};
-
-static const unsigned int scif0_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 0),
-};
-
-static const unsigned int scif0_clk_a_mux[] = {
-	SCK0_A_MARK,
-};
-
-static const unsigned int scif0_ctrl_a_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
-};
-
-static const unsigned int scif0_ctrl_a_mux[] = {
-	RTS0_N_A_MARK, CTS0_N_A_MARK,
-};
-
-static const unsigned int scif0_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
-};
-
-static const unsigned int scif0_data_b_mux[] = {
-	RX0_B_MARK, TX0_B_MARK,
-};
-
-static const unsigned int scif0_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 18),
-};
-
-static const unsigned int scif0_clk_b_mux[] = {
-	SCK0_B_MARK,
-};
-
-/* - SCIF1 ------------------------------------------------------------------ */
-static const unsigned int scif1_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
-};
-
-static const unsigned int scif1_data_mux[] = {
-	RX1_MARK, TX1_MARK,
-};
-
-static const unsigned int scif1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 16),
-};
-
-static const unsigned int scif1_clk_mux[] = {
-	SCK1_MARK,
-};
-
-static const unsigned int scif1_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 7),
-};
-
-static const unsigned int scif1_ctrl_mux[] = {
-	RTS1_N_MARK, CTS1_N_MARK,
-};
-
-/* - SCIF2 ------------------------------------------------------------------ */
-static const unsigned int scif2_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
-};
-
-static const unsigned int scif2_data_a_mux[] = {
-	RX2_A_MARK, TX2_A_MARK,
-};
-
-static const unsigned int scif2_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 7),
-};
-
-static const unsigned int scif2_clk_a_mux[] = {
-	SCK2_A_MARK,
-};
-
-static const unsigned int scif2_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
-};
-
-static const unsigned int scif2_data_b_mux[] = {
-	RX2_B_MARK, TX2_B_MARK,
-};
-
-/* - SCIF3 ------------------------------------------------------------------ */
-static const unsigned int scif3_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
-};
-
-static const unsigned int scif3_data_a_mux[] = {
-	RX3_A_MARK, TX3_A_MARK,
-};
-
-static const unsigned int scif3_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 1),
-};
-
-static const unsigned int scif3_clk_a_mux[] = {
-	SCK3_A_MARK,
-};
-
-static const unsigned int scif3_ctrl_a_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
-};
-
-static const unsigned int scif3_ctrl_a_mux[] = {
-	RTS3_N_A_MARK, CTS3_N_A_MARK,
-};
-
-static const unsigned int scif3_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
-};
-
-static const unsigned int scif3_data_b_mux[] = {
-	RX3_B_MARK, TX3_B_MARK,
-};
-
-static const unsigned int scif3_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
-};
-
-static const unsigned int scif3_data_c_mux[] = {
-	RX3_C_MARK, TX3_C_MARK,
-};
-
-static const unsigned int scif3_clk_c_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 24),
-};
-
-static const unsigned int scif3_clk_c_mux[] = {
-	SCK3_C_MARK,
-};
-
-/* - SCIF4 ------------------------------------------------------------------ */
-static const unsigned int scif4_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-};
-
-static const unsigned int scif4_data_a_mux[] = {
-	RX4_A_MARK, TX4_A_MARK,
-};
-
-static const unsigned int scif4_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 5),
-};
-
-static const unsigned int scif4_clk_a_mux[] = {
-	SCK4_A_MARK,
-};
-
-static const unsigned int scif4_ctrl_a_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
-};
-
-static const unsigned int scif4_ctrl_a_mux[] = {
-	RTS4_N_A_MARK, CTS4_N_A_MARK,
-};
-
-static const unsigned int scif4_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
-};
-
-static const unsigned int scif4_data_b_mux[] = {
-	RX4_B_MARK, TX4_B_MARK,
-};
-
-static const unsigned int scif4_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 8),
-};
-
-static const unsigned int scif4_clk_b_mux[] = {
-	SCK4_B_MARK,
-};
-
-static const unsigned int scif4_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-};
-
-static const unsigned int scif4_data_c_mux[] = {
-	RX4_C_MARK, TX4_C_MARK,
-};
-
-static const unsigned int scif4_ctrl_c_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
-};
-
-static const unsigned int scif4_ctrl_c_mux[] = {
-	RTS4_N_C_MARK, CTS4_N_C_MARK,
-};
-
-/* - SCIF5 ------------------------------------------------------------------ */
-static const unsigned int scif5_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 9),
-};
-
-static const unsigned int scif5_data_a_mux[] = {
-	RX5_A_MARK, TX5_A_MARK,
-};
-
-static const unsigned int scif5_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 13),
-};
-
-static const unsigned int scif5_clk_a_mux[] = {
-	SCK5_A_MARK,
-};
-
-static const unsigned int scif5_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
-};
-
-static const unsigned int scif5_data_b_mux[] = {
-	RX5_B_MARK, TX5_B_MARK,
-};
-
-static const unsigned int scif5_data_c_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-};
-
-static const unsigned int scif5_data_c_mux[] = {
-	RX5_C_MARK, TX5_C_MARK,
-};
-
-/* - SCIF Clock ------------------------------------------------------------- */
-static const unsigned int scif_clk_a_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(5, 3),
-};
-
-static const unsigned int scif_clk_a_mux[] = {
-	SCIF_CLK_A_MARK,
-};
-
-static const unsigned int scif_clk_b_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(5, 7),
-};
-
-static const unsigned int scif_clk_b_mux[] = {
-	SCIF_CLK_B_MARK,
-};
-
-/* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 2),
-};
-
-static const unsigned int sdhi0_data1_mux[] = {
-	SD0_DAT0_MARK,
-};
-
-static const unsigned int sdhi0_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
-	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
-};
-
-static const unsigned int sdhi0_data4_mux[] = {
-	SD0_DAT0_MARK, SD0_DAT1_MARK,
-	SD0_DAT2_MARK, SD0_DAT3_MARK,
-};
-
-static const unsigned int sdhi0_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
-};
-
-static const unsigned int sdhi0_ctrl_mux[] = {
-	SD0_CLK_MARK, SD0_CMD_MARK,
-};
-
-static const unsigned int sdhi0_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(3, 12),
-};
-
-static const unsigned int sdhi0_cd_mux[] = {
-	SD0_CD_MARK,
-};
-
-static const unsigned int sdhi0_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(3, 13),
-};
-
-static const unsigned int sdhi0_wp_mux[] = {
-	SD0_WP_MARK,
-};
-
-/* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 8),
-};
-
-static const unsigned int sdhi1_data1_mux[] = {
-	SD1_DAT0_MARK,
-};
-
-static const unsigned int sdhi1_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-};
-
-static const unsigned int sdhi1_data4_mux[] = {
-	SD1_DAT0_MARK, SD1_DAT1_MARK,
-	SD1_DAT2_MARK, SD1_DAT3_MARK,
-};
-
-static const unsigned int sdhi1_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-};
-
-static const unsigned int sdhi1_ctrl_mux[] = {
-	SD1_CLK_MARK, SD1_CMD_MARK,
-};
-
-static const unsigned int sdhi1_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(3, 14),
-};
-
-static const unsigned int sdhi1_cd_mux[] = {
-	SD1_CD_MARK,
-};
-
-static const unsigned int sdhi1_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(3, 15),
-};
-
-static const unsigned int sdhi1_wp_mux[] = {
-	SD1_WP_MARK,
-};
-
-/* - SDHI3 ------------------------------------------------------------------ */
-static const unsigned int sdhi3_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(4, 2),
-};
-
-static const unsigned int sdhi3_data1_mux[] = {
-	SD3_DAT0_MARK,
-};
-
-static const unsigned int sdhi3_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-};
-
-static const unsigned int sdhi3_data4_mux[] = {
-	SD3_DAT0_MARK, SD3_DAT1_MARK,
-	SD3_DAT2_MARK, SD3_DAT3_MARK,
-};
-
-static const unsigned int sdhi3_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-	RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
-	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
-};
-
-static const unsigned int sdhi3_data8_mux[] = {
-	SD3_DAT0_MARK, SD3_DAT1_MARK,
-	SD3_DAT2_MARK, SD3_DAT3_MARK,
-	SD3_DAT4_MARK, SD3_DAT5_MARK,
-	SD3_DAT6_MARK, SD3_DAT7_MARK,
-};
-
-static const unsigned int sdhi3_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
-};
-
-static const unsigned int sdhi3_ctrl_mux[] = {
-	SD3_CLK_MARK, SD3_CMD_MARK,
-};
-
-static const unsigned int sdhi3_cd_pins[] = {
-	/* CD */
-	RCAR_GP_PIN(3, 12),
-};
-
-static const unsigned int sdhi3_cd_mux[] = {
-	SD3_CD_MARK,
-};
-
-static const unsigned int sdhi3_wp_pins[] = {
-	/* WP */
-	RCAR_GP_PIN(3, 13),
-};
-
-static const unsigned int sdhi3_wp_mux[] = {
-	SD3_WP_MARK,
-};
-
-static const unsigned int sdhi3_ds_pins[] = {
-	/* DS */
-	RCAR_GP_PIN(4, 10),
-};
-
-static const unsigned int sdhi3_ds_mux[] = {
-	SD3_DS_MARK,
-};
-
-/* - SSI -------------------------------------------------------------------- */
-static const unsigned int ssi0_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 2),
-};
-
-static const unsigned int ssi0_data_mux[] = {
-	SSI_SDATA0_MARK,
-};
-
-static const unsigned int ssi01239_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
-};
-
-static const unsigned int ssi01239_ctrl_mux[] = {
-	SSI_SCK01239_MARK, SSI_WS01239_MARK,
-};
-
-static const unsigned int ssi1_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 3),
-};
-
-static const unsigned int ssi1_data_mux[] = {
-	SSI_SDATA1_MARK,
-};
-
-static const unsigned int ssi1_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
-};
-
-static const unsigned int ssi1_ctrl_mux[] = {
-	SSI_SCK1_MARK, SSI_WS1_MARK,
-};
-
-static const unsigned int ssi2_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 4),
-};
-
-static const unsigned int ssi2_data_mux[] = {
-	SSI_SDATA2_MARK,
-};
-
-static const unsigned int ssi2_ctrl_a_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
-};
-
-static const unsigned int ssi2_ctrl_a_mux[] = {
-	SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
-};
-
-static const unsigned int ssi2_ctrl_b_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
-};
-
-static const unsigned int ssi2_ctrl_b_mux[] = {
-	SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
-};
-
-static const unsigned int ssi3_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 7),
-};
-
-static const unsigned int ssi3_data_mux[] = {
-	SSI_SDATA3_MARK,
-};
-
-static const unsigned int ssi349_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
-};
-
-static const unsigned int ssi349_ctrl_mux[] = {
-	SSI_SCK349_MARK, SSI_WS349_MARK,
-};
-
-static const unsigned int ssi4_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 10),
-};
-
-static const unsigned int ssi4_data_mux[] = {
-	SSI_SDATA4_MARK,
-};
-
-static const unsigned int ssi4_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
-};
-
-static const unsigned int ssi4_ctrl_mux[] = {
-	SSI_SCK4_MARK, SSI_WS4_MARK,
-};
-
-static const unsigned int ssi5_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 13),
-};
-
-static const unsigned int ssi5_data_mux[] = {
-	SSI_SDATA5_MARK,
-};
-
-static const unsigned int ssi5_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
-};
-
-static const unsigned int ssi5_ctrl_mux[] = {
-	SSI_SCK5_MARK, SSI_WS5_MARK,
-};
-
-static const unsigned int ssi6_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(6, 16),
-};
-
-static const unsigned int ssi6_data_mux[] = {
-	SSI_SDATA6_MARK,
-};
-
-static const unsigned int ssi6_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
-};
-
-static const unsigned int ssi6_ctrl_mux[] = {
-	SSI_SCK6_MARK, SSI_WS6_MARK,
-};
-
-static const unsigned int ssi7_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(5, 12),
-};
-
-static const unsigned int ssi7_data_mux[] = {
-	SSI_SDATA7_MARK,
-};
-
-static const unsigned int ssi78_ctrl_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
-};
-
-static const unsigned int ssi78_ctrl_mux[] = {
-	SSI_SCK78_MARK, SSI_WS78_MARK,
-};
-
-static const unsigned int ssi8_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(5, 13),
-};
-
-static const unsigned int ssi8_data_mux[] = {
-	SSI_SDATA8_MARK,
-};
-
-static const unsigned int ssi9_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(5, 16),
-};
-
-static const unsigned int ssi9_data_mux[] = {
-	SSI_SDATA9_MARK,
-};
-
-static const unsigned int ssi9_ctrl_a_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 10),
-};
-
-static const unsigned int ssi9_ctrl_a_mux[] = {
-	SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
-};
-
-static const unsigned int ssi9_ctrl_b_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
-};
-
-static const unsigned int ssi9_ctrl_b_mux[] = {
-	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
-};
-
-/* - TMU -------------------------------------------------------------------- */
-static const unsigned int tmu_tclk1_a_pins[] = {
-	/* TCLK */
-	RCAR_GP_PIN(3, 12),
-};
-
-static const unsigned int tmu_tclk1_a_mux[] = {
-	TCLK1_A_MARK,
-};
-
-static const unsigned int tmu_tclk1_b_pins[] = {
-	/* TCLK */
-	RCAR_GP_PIN(5, 17),
-};
-
-static const unsigned int tmu_tclk1_b_mux[] = {
-	TCLK1_B_MARK,
-};
-
-static const unsigned int tmu_tclk2_a_pins[] = {
-	/* TCLK */
-	RCAR_GP_PIN(3, 13),
-};
-
-static const unsigned int tmu_tclk2_a_mux[] = {
-	TCLK2_A_MARK,
-};
-
-static const unsigned int tmu_tclk2_b_pins[] = {
-	/* TCLK */
-	RCAR_GP_PIN(5, 18),
-};
-
-static const unsigned int tmu_tclk2_b_mux[] = {
-	TCLK2_B_MARK,
-};
-
-/* - USB0 ------------------------------------------------------------------- */
-static const unsigned int usb0_a_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
-};
-
-static const unsigned int usb0_a_mux[] = {
-	USB0_PWEN_A_MARK, USB0_OVC_A_MARK,
-};
-
-static const unsigned int usb0_b_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
-};
-
-static const unsigned int usb0_b_mux[] = {
-	USB0_PWEN_B_MARK, USB0_OVC_B_MARK,
-};
-
-static const unsigned int usb0_id_pins[] = {
-	/* ID */
-	RCAR_GP_PIN(5, 0)
-};
-
-static const unsigned int usb0_id_mux[] = {
-	USB0_ID_MARK,
-};
-
-/* - USB30 ------------------------------------------------------------------ */
-static const unsigned int usb30_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
-};
-
-static const unsigned int usb30_mux[] = {
-	USB30_PWEN_MARK, USB30_OVC_MARK,
-};
-
-static const unsigned int usb30_id_pins[] = {
-	/* ID */
-	RCAR_GP_PIN(5, 0),
-};
-
-static const unsigned int usb30_id_mux[] = {
-	USB3HS0_ID_MARK,
-};
-
-/* - VIN4 ------------------------------------------------------------------- */
-static const unsigned int vin4_data18_a_pins[] = {
-	RCAR_GP_PIN(2, 8),  RCAR_GP_PIN(2, 9),
-	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
-	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
-	RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
-	RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
-	RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
-	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
-	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
-	RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
-};
-
-static const unsigned int vin4_data18_a_mux[] = {
-	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-	VI4_DATA10_MARK,  VI4_DATA11_MARK,
-	VI4_DATA12_MARK,  VI4_DATA13_MARK,
-	VI4_DATA14_MARK,  VI4_DATA15_MARK,
-	VI4_DATA18_MARK,  VI4_DATA19_MARK,
-	VI4_DATA20_MARK,  VI4_DATA21_MARK,
-	VI4_DATA22_MARK,  VI4_DATA23_MARK,
-};
-
-static const union vin_data vin4_data_a_pins = {
-	.data24 = {
-		RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 7),
-		RCAR_GP_PIN(2, 8),  RCAR_GP_PIN(2, 9),
-		RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
-		RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
-		RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
-		RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
-		RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
-		RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 12),
-		RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
-		RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
-		RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
-	},
-};
-
-static const union vin_data vin4_data_a_mux = {
-	.data24 = {
-		VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
-		VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-		VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-		VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-		VI4_DATA8_MARK,   VI4_DATA9_MARK,
-		VI4_DATA10_MARK,  VI4_DATA11_MARK,
-		VI4_DATA12_MARK,  VI4_DATA13_MARK,
-		VI4_DATA14_MARK,  VI4_DATA15_MARK,
-		VI4_DATA16_MARK,  VI4_DATA17_MARK,
-		VI4_DATA18_MARK,  VI4_DATA19_MARK,
-		VI4_DATA20_MARK,  VI4_DATA21_MARK,
-		VI4_DATA22_MARK,  VI4_DATA23_MARK,
-	},
-};
-
-static const unsigned int vin4_data18_b_pins[] = {
-	RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
-	RCAR_GP_PIN(0, 5),  RCAR_GP_PIN(0, 6),
-	RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
-	RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
-	RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
-	RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
-	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
-	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
-	RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
-};
-
-static const unsigned int vin4_data18_b_mux[] = {
-	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
-	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
-	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
-	VI4_DATA10_MARK,  VI4_DATA11_MARK,
-	VI4_DATA12_MARK,  VI4_DATA13_MARK,
-	VI4_DATA14_MARK,  VI4_DATA15_MARK,
-	VI4_DATA18_MARK,  VI4_DATA19_MARK,
-	VI4_DATA20_MARK,  VI4_DATA21_MARK,
-	VI4_DATA22_MARK,  VI4_DATA23_MARK,
-};
-
-static const union vin_data vin4_data_b_pins = {
-	.data24 = {
-		RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 11),
-		RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
-		RCAR_GP_PIN(0, 5),  RCAR_GP_PIN(0, 6),
-		RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
-		RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
-		RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
-		RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
-		RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 12),
-		RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
-		RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
-		RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
-	},
-};
-
-static const union vin_data vin4_data_b_mux = {
-	.data24 = {
-		VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
-		VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
-		VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
-		VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
-		VI4_DATA8_MARK,   VI4_DATA9_MARK,
-		VI4_DATA10_MARK,  VI4_DATA11_MARK,
-		VI4_DATA12_MARK,  VI4_DATA13_MARK,
-		VI4_DATA14_MARK,  VI4_DATA15_MARK,
-		VI4_DATA16_MARK,  VI4_DATA17_MARK,
-		VI4_DATA18_MARK,  VI4_DATA19_MARK,
-		VI4_DATA20_MARK,  VI4_DATA21_MARK,
-		VI4_DATA22_MARK,  VI4_DATA23_MARK,
-	},
-};
-
-static const unsigned int vin4_sync_pins[] = {
-	/* HSYNC, VSYNC */
-	RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
-};
-
-static const unsigned int vin4_sync_mux[] = {
-	VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
-};
-
-static const unsigned int vin4_field_pins[] = {
-	RCAR_GP_PIN(2, 23),
-};
-
-static const unsigned int vin4_field_mux[] = {
-	VI4_FIELD_MARK,
-};
-
-static const unsigned int vin4_clkenb_pins[] = {
-	RCAR_GP_PIN(1, 2),
-};
-
-static const unsigned int vin4_clkenb_mux[] = {
-	VI4_CLKENB_MARK,
-};
-
-static const unsigned int vin4_clk_pins[] = {
-	RCAR_GP_PIN(2, 22),
-};
-
-static const unsigned int vin4_clk_mux[] = {
-	VI4_CLK_MARK,
-};
-
-/* - VIN5 ------------------------------------------------------------------- */
-static const union vin_data16 vin5_data_a_pins = {
-	.data16 = {
-		RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 2),
-		RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12),
-		RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
-		RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
-		RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-		RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 11),
-		RCAR_GP_PIN(0, 8),  RCAR_GP_PIN(0, 10),
-		RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 3),
-	},
-};
-
-static const union vin_data16 vin5_data_a_mux = {
-	.data16 = {
-		VI5_DATA0_A_MARK,  VI5_DATA1_A_MARK,
-		VI5_DATA2_A_MARK,  VI5_DATA3_A_MARK,
-		VI5_DATA4_A_MARK,  VI5_DATA5_A_MARK,
-		VI5_DATA6_A_MARK,  VI5_DATA7_A_MARK,
-		VI5_DATA8_A_MARK,  VI5_DATA9_A_MARK,
-		VI5_DATA10_A_MARK, VI5_DATA11_A_MARK,
-		VI5_DATA12_A_MARK, VI5_DATA13_A_MARK,
-		VI5_DATA14_A_MARK, VI5_DATA15_A_MARK,
-	},
-};
-
-static const unsigned int vin5_data8_b_pins[] = {
-	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(0, 4),
-	RCAR_GP_PIN(0, 7),  RCAR_GP_PIN(0, 12),
-	RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
-	RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
-};
-
-static const unsigned int vin5_data8_b_mux[] = {
-	VI5_DATA0_B_MARK,  VI5_DATA1_B_MARK,
-	VI5_DATA2_B_MARK,  VI5_DATA3_B_MARK,
-	VI5_DATA4_B_MARK,  VI5_DATA5_B_MARK,
-	VI5_DATA6_B_MARK,  VI5_DATA7_B_MARK,
-};
-
-static const unsigned int vin5_sync_a_pins[] = {
-	/* HSYNC_N, VSYNC_N */
-	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
-};
-
-static const unsigned int vin5_sync_a_mux[] = {
-	VI5_HSYNC_N_A_MARK, VI5_VSYNC_N_A_MARK,
-};
-
-static const unsigned int vin5_field_a_pins[] = {
-	RCAR_GP_PIN(1, 10),
-};
-
-static const unsigned int vin5_field_a_mux[] = {
-	VI5_FIELD_A_MARK,
-};
-
-static const unsigned int vin5_clkenb_a_pins[] = {
-	RCAR_GP_PIN(0, 1),
-};
-
-static const unsigned int vin5_clkenb_a_mux[] = {
-	VI5_CLKENB_A_MARK,
-};
-
-static const unsigned int vin5_clk_a_pins[] = {
-	RCAR_GP_PIN(1, 0),
-};
-
-static const unsigned int vin5_clk_a_mux[] = {
-	VI5_CLK_A_MARK,
-};
-
-static const unsigned int vin5_clk_b_pins[] = {
-	RCAR_GP_PIN(2, 22),
-};
-
-static const unsigned int vin5_clk_b_mux[] = {
-	VI5_CLK_B_MARK,
-};
-
-static const struct {
-	struct sh_pfc_pin_group common[247];
-	struct sh_pfc_pin_group automotive[21];
-} pinmux_groups = {
-	.common = {
-		SH_PFC_PIN_GROUP(audio_clk_a),
-		SH_PFC_PIN_GROUP(audio_clk_b_a),
-		SH_PFC_PIN_GROUP(audio_clk_b_b),
-		SH_PFC_PIN_GROUP(audio_clk_b_c),
-		SH_PFC_PIN_GROUP(audio_clk_c_a),
-		SH_PFC_PIN_GROUP(audio_clk_c_b),
-		SH_PFC_PIN_GROUP(audio_clk_c_c),
-		SH_PFC_PIN_GROUP(audio_clkout_a),
-		SH_PFC_PIN_GROUP(audio_clkout_b),
-		SH_PFC_PIN_GROUP(audio_clkout1_a),
-		SH_PFC_PIN_GROUP(audio_clkout1_b),
-		SH_PFC_PIN_GROUP(audio_clkout1_c),
-		SH_PFC_PIN_GROUP(audio_clkout2_a),
-		SH_PFC_PIN_GROUP(audio_clkout2_b),
-		SH_PFC_PIN_GROUP(audio_clkout2_c),
-		SH_PFC_PIN_GROUP(audio_clkout3_a),
-		SH_PFC_PIN_GROUP(audio_clkout3_b),
-		SH_PFC_PIN_GROUP(audio_clkout3_c),
-		SH_PFC_PIN_GROUP(avb_link),
-		SH_PFC_PIN_GROUP(avb_magic),
-		SH_PFC_PIN_GROUP(avb_phy_int),
-		SH_PFC_PIN_GROUP(avb_mii),
-		SH_PFC_PIN_GROUP(avb_avtp_pps),
-		SH_PFC_PIN_GROUP(avb_avtp_match),
-		SH_PFC_PIN_GROUP(avb_avtp_capture),
-		SH_PFC_PIN_GROUP(can0_data),
-		SH_PFC_PIN_GROUP(can1_data),
-		SH_PFC_PIN_GROUP(can_clk),
-		SH_PFC_PIN_GROUP(canfd0_data),
-		SH_PFC_PIN_GROUP(canfd1_data),
-		SH_PFC_PIN_GROUP(du_rgb666),
-		SH_PFC_PIN_GROUP(du_rgb888),
-		SH_PFC_PIN_GROUP(du_clk_in_0),
-		SH_PFC_PIN_GROUP(du_clk_in_1),
-		SH_PFC_PIN_GROUP(du_clk_out_0),
-		SH_PFC_PIN_GROUP(du_sync),
-		SH_PFC_PIN_GROUP(du_disp_cde),
-		SH_PFC_PIN_GROUP(du_cde),
-		SH_PFC_PIN_GROUP(du_disp),
-		SH_PFC_PIN_GROUP(hscif0_data_a),
-		SH_PFC_PIN_GROUP(hscif0_clk_a),
-		SH_PFC_PIN_GROUP(hscif0_ctrl_a),
-		SH_PFC_PIN_GROUP(hscif0_data_b),
-		SH_PFC_PIN_GROUP(hscif0_clk_b),
-		SH_PFC_PIN_GROUP(hscif1_data_a),
-		SH_PFC_PIN_GROUP(hscif1_clk_a),
-		SH_PFC_PIN_GROUP(hscif1_data_b),
-		SH_PFC_PIN_GROUP(hscif1_clk_b),
-		SH_PFC_PIN_GROUP(hscif1_ctrl_b),
-		SH_PFC_PIN_GROUP(hscif2_data_a),
-		SH_PFC_PIN_GROUP(hscif2_clk_a),
-		SH_PFC_PIN_GROUP(hscif2_ctrl_a),
-		SH_PFC_PIN_GROUP(hscif2_data_b),
-		SH_PFC_PIN_GROUP(hscif3_data_a),
-		SH_PFC_PIN_GROUP(hscif3_data_b),
-		SH_PFC_PIN_GROUP(hscif3_clk_b),
-		SH_PFC_PIN_GROUP(hscif3_data_c),
-		SH_PFC_PIN_GROUP(hscif3_clk_c),
-		SH_PFC_PIN_GROUP(hscif3_ctrl_c),
-		SH_PFC_PIN_GROUP(hscif3_data_d),
-		SH_PFC_PIN_GROUP(hscif3_data_e),
-		SH_PFC_PIN_GROUP(hscif3_ctrl_e),
-		SH_PFC_PIN_GROUP(hscif4_data_a),
-		SH_PFC_PIN_GROUP(hscif4_clk_a),
-		SH_PFC_PIN_GROUP(hscif4_ctrl_a),
-		SH_PFC_PIN_GROUP(hscif4_data_b),
-		SH_PFC_PIN_GROUP(hscif4_clk_b),
-		SH_PFC_PIN_GROUP(hscif4_data_c),
-		SH_PFC_PIN_GROUP(hscif4_data_d),
-		SH_PFC_PIN_GROUP(hscif4_data_e),
-		SH_PFC_PIN_GROUP(i2c1_a),
-		SH_PFC_PIN_GROUP(i2c1_b),
-		SH_PFC_PIN_GROUP(i2c1_c),
-		SH_PFC_PIN_GROUP(i2c1_d),
-		SH_PFC_PIN_GROUP(i2c2_a),
-		SH_PFC_PIN_GROUP(i2c2_b),
-		SH_PFC_PIN_GROUP(i2c2_c),
-		SH_PFC_PIN_GROUP(i2c2_d),
-		SH_PFC_PIN_GROUP(i2c2_e),
-		SH_PFC_PIN_GROUP(i2c4),
-		SH_PFC_PIN_GROUP(i2c5),
-		SH_PFC_PIN_GROUP(i2c6_a),
-		SH_PFC_PIN_GROUP(i2c6_b),
-		SH_PFC_PIN_GROUP(i2c7_a),
-		SH_PFC_PIN_GROUP(i2c7_b),
-		SH_PFC_PIN_GROUP(intc_ex_irq0),
-		SH_PFC_PIN_GROUP(intc_ex_irq1),
-		SH_PFC_PIN_GROUP(intc_ex_irq2),
-		SH_PFC_PIN_GROUP(intc_ex_irq3),
-		SH_PFC_PIN_GROUP(intc_ex_irq4),
-		SH_PFC_PIN_GROUP(intc_ex_irq5),
-		SH_PFC_PIN_GROUP(msiof0_clk),
-		SH_PFC_PIN_GROUP(msiof0_sync),
-		SH_PFC_PIN_GROUP(msiof0_ss1),
-		SH_PFC_PIN_GROUP(msiof0_ss2),
-		SH_PFC_PIN_GROUP(msiof0_txd),
-		SH_PFC_PIN_GROUP(msiof0_rxd),
-		SH_PFC_PIN_GROUP(msiof1_clk),
-		SH_PFC_PIN_GROUP(msiof1_sync),
-		SH_PFC_PIN_GROUP(msiof1_ss1),
-		SH_PFC_PIN_GROUP(msiof1_ss2),
-		SH_PFC_PIN_GROUP(msiof1_txd),
-		SH_PFC_PIN_GROUP(msiof1_rxd),
-		SH_PFC_PIN_GROUP(msiof2_clk_a),
-		SH_PFC_PIN_GROUP(msiof2_sync_a),
-		SH_PFC_PIN_GROUP(msiof2_ss1_a),
-		SH_PFC_PIN_GROUP(msiof2_ss2_a),
-		SH_PFC_PIN_GROUP(msiof2_txd_a),
-		SH_PFC_PIN_GROUP(msiof2_rxd_a),
-		SH_PFC_PIN_GROUP(msiof2_clk_b),
-		SH_PFC_PIN_GROUP(msiof2_sync_b),
-		SH_PFC_PIN_GROUP(msiof2_ss1_b),
-		SH_PFC_PIN_GROUP(msiof2_ss2_b),
-		SH_PFC_PIN_GROUP(msiof2_txd_b),
-		SH_PFC_PIN_GROUP(msiof2_rxd_b),
-		SH_PFC_PIN_GROUP(msiof3_clk_a),
-		SH_PFC_PIN_GROUP(msiof3_sync_a),
-		SH_PFC_PIN_GROUP(msiof3_ss1_a),
-		SH_PFC_PIN_GROUP(msiof3_ss2_a),
-		SH_PFC_PIN_GROUP(msiof3_txd_a),
-		SH_PFC_PIN_GROUP(msiof3_rxd_a),
-		SH_PFC_PIN_GROUP(msiof3_clk_b),
-		SH_PFC_PIN_GROUP(msiof3_sync_b),
-		SH_PFC_PIN_GROUP(msiof3_ss1_b),
-		SH_PFC_PIN_GROUP(msiof3_txd_b),
-		SH_PFC_PIN_GROUP(msiof3_rxd_b),
-		SH_PFC_PIN_GROUP(pwm0_a),
-		SH_PFC_PIN_GROUP(pwm0_b),
-		SH_PFC_PIN_GROUP(pwm1_a),
-		SH_PFC_PIN_GROUP(pwm1_b),
-		SH_PFC_PIN_GROUP(pwm2_a),
-		SH_PFC_PIN_GROUP(pwm2_b),
-		SH_PFC_PIN_GROUP(pwm2_c),
-		SH_PFC_PIN_GROUP(pwm3_a),
-		SH_PFC_PIN_GROUP(pwm3_b),
-		SH_PFC_PIN_GROUP(pwm3_c),
-		SH_PFC_PIN_GROUP(pwm4_a),
-		SH_PFC_PIN_GROUP(pwm4_b),
-		SH_PFC_PIN_GROUP(pwm5_a),
-		SH_PFC_PIN_GROUP(pwm5_b),
-		SH_PFC_PIN_GROUP(pwm6_a),
-		SH_PFC_PIN_GROUP(pwm6_b),
-		SH_PFC_PIN_GROUP(scif0_data_a),
-		SH_PFC_PIN_GROUP(scif0_clk_a),
-		SH_PFC_PIN_GROUP(scif0_ctrl_a),
-		SH_PFC_PIN_GROUP(scif0_data_b),
-		SH_PFC_PIN_GROUP(scif0_clk_b),
-		SH_PFC_PIN_GROUP(scif1_data),
-		SH_PFC_PIN_GROUP(scif1_clk),
-		SH_PFC_PIN_GROUP(scif1_ctrl),
-		SH_PFC_PIN_GROUP(scif2_data_a),
-		SH_PFC_PIN_GROUP(scif2_clk_a),
-		SH_PFC_PIN_GROUP(scif2_data_b),
-		SH_PFC_PIN_GROUP(scif3_data_a),
-		SH_PFC_PIN_GROUP(scif3_clk_a),
-		SH_PFC_PIN_GROUP(scif3_ctrl_a),
-		SH_PFC_PIN_GROUP(scif3_data_b),
-		SH_PFC_PIN_GROUP(scif3_data_c),
-		SH_PFC_PIN_GROUP(scif3_clk_c),
-		SH_PFC_PIN_GROUP(scif4_data_a),
-		SH_PFC_PIN_GROUP(scif4_clk_a),
-		SH_PFC_PIN_GROUP(scif4_ctrl_a),
-		SH_PFC_PIN_GROUP(scif4_data_b),
-		SH_PFC_PIN_GROUP(scif4_clk_b),
-		SH_PFC_PIN_GROUP(scif4_data_c),
-		SH_PFC_PIN_GROUP(scif4_ctrl_c),
-		SH_PFC_PIN_GROUP(scif5_data_a),
-		SH_PFC_PIN_GROUP(scif5_clk_a),
-		SH_PFC_PIN_GROUP(scif5_data_b),
-		SH_PFC_PIN_GROUP(scif5_data_c),
-		SH_PFC_PIN_GROUP(scif_clk_a),
-		SH_PFC_PIN_GROUP(scif_clk_b),
-		SH_PFC_PIN_GROUP(sdhi0_data1),
-		SH_PFC_PIN_GROUP(sdhi0_data4),
-		SH_PFC_PIN_GROUP(sdhi0_ctrl),
-		SH_PFC_PIN_GROUP(sdhi0_cd),
-		SH_PFC_PIN_GROUP(sdhi0_wp),
-		SH_PFC_PIN_GROUP(sdhi1_data1),
-		SH_PFC_PIN_GROUP(sdhi1_data4),
-		SH_PFC_PIN_GROUP(sdhi1_ctrl),
-		SH_PFC_PIN_GROUP(sdhi1_cd),
-		SH_PFC_PIN_GROUP(sdhi1_wp),
-		SH_PFC_PIN_GROUP(sdhi3_data1),
-		SH_PFC_PIN_GROUP(sdhi3_data4),
-		SH_PFC_PIN_GROUP(sdhi3_data8),
-		SH_PFC_PIN_GROUP(sdhi3_ctrl),
-		SH_PFC_PIN_GROUP(sdhi3_cd),
-		SH_PFC_PIN_GROUP(sdhi3_wp),
-		SH_PFC_PIN_GROUP(sdhi3_ds),
-		SH_PFC_PIN_GROUP(ssi0_data),
-		SH_PFC_PIN_GROUP(ssi01239_ctrl),
-		SH_PFC_PIN_GROUP(ssi1_data),
-		SH_PFC_PIN_GROUP(ssi1_ctrl),
-		SH_PFC_PIN_GROUP(ssi2_data),
-		SH_PFC_PIN_GROUP(ssi2_ctrl_a),
-		SH_PFC_PIN_GROUP(ssi2_ctrl_b),
-		SH_PFC_PIN_GROUP(ssi3_data),
-		SH_PFC_PIN_GROUP(ssi349_ctrl),
-		SH_PFC_PIN_GROUP(ssi4_data),
-		SH_PFC_PIN_GROUP(ssi4_ctrl),
-		SH_PFC_PIN_GROUP(ssi5_data),
-		SH_PFC_PIN_GROUP(ssi5_ctrl),
-		SH_PFC_PIN_GROUP(ssi6_data),
-		SH_PFC_PIN_GROUP(ssi6_ctrl),
-		SH_PFC_PIN_GROUP(ssi7_data),
-		SH_PFC_PIN_GROUP(ssi78_ctrl),
-		SH_PFC_PIN_GROUP(ssi8_data),
-		SH_PFC_PIN_GROUP(ssi9_data),
-		SH_PFC_PIN_GROUP(ssi9_ctrl_a),
-		SH_PFC_PIN_GROUP(ssi9_ctrl_b),
-		SH_PFC_PIN_GROUP(tmu_tclk1_a),
-		SH_PFC_PIN_GROUP(tmu_tclk1_b),
-		SH_PFC_PIN_GROUP(tmu_tclk2_a),
-		SH_PFC_PIN_GROUP(tmu_tclk2_b),
-		SH_PFC_PIN_GROUP(usb0_a),
-		SH_PFC_PIN_GROUP(usb0_b),
-		SH_PFC_PIN_GROUP(usb0_id),
-		SH_PFC_PIN_GROUP(usb30),
-		SH_PFC_PIN_GROUP(usb30_id),
-		VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
-		SH_PFC_PIN_GROUP(vin4_data18_a),
-		VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
-		VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
-		SH_PFC_PIN_GROUP(vin4_data18_b),
-		VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
-		VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
-		SH_PFC_PIN_GROUP(vin4_sync),
-		SH_PFC_PIN_GROUP(vin4_field),
-		SH_PFC_PIN_GROUP(vin4_clkenb),
-		SH_PFC_PIN_GROUP(vin4_clk),
-		VIN_DATA_PIN_GROUP(vin5_data, 8, _a),
-		VIN_DATA_PIN_GROUP(vin5_data, 10, _a),
-		VIN_DATA_PIN_GROUP(vin5_data, 12, _a),
-		VIN_DATA_PIN_GROUP(vin5_data, 16, _a),
-		SH_PFC_PIN_GROUP(vin5_data8_b),
-		SH_PFC_PIN_GROUP(vin5_sync_a),
-		SH_PFC_PIN_GROUP(vin5_field_a),
-		SH_PFC_PIN_GROUP(vin5_clkenb_a),
-		SH_PFC_PIN_GROUP(vin5_clk_a),
-		SH_PFC_PIN_GROUP(vin5_clk_b),
-	},
-	.automotive = {
-		SH_PFC_PIN_GROUP(drif0_ctrl_a),
-		SH_PFC_PIN_GROUP(drif0_data0_a),
-		SH_PFC_PIN_GROUP(drif0_data1_a),
-		SH_PFC_PIN_GROUP(drif0_ctrl_b),
-		SH_PFC_PIN_GROUP(drif0_data0_b),
-		SH_PFC_PIN_GROUP(drif0_data1_b),
-		SH_PFC_PIN_GROUP(drif1_ctrl),
-		SH_PFC_PIN_GROUP(drif1_data0),
-		SH_PFC_PIN_GROUP(drif1_data1),
-		SH_PFC_PIN_GROUP(drif2_ctrl_a),
-		SH_PFC_PIN_GROUP(drif2_data0_a),
-		SH_PFC_PIN_GROUP(drif2_data1_a),
-		SH_PFC_PIN_GROUP(drif2_ctrl_b),
-		SH_PFC_PIN_GROUP(drif2_data0_b),
-		SH_PFC_PIN_GROUP(drif2_data1_b),
-		SH_PFC_PIN_GROUP(drif3_ctrl_a),
-		SH_PFC_PIN_GROUP(drif3_data0_a),
-		SH_PFC_PIN_GROUP(drif3_data1_a),
-		SH_PFC_PIN_GROUP(drif3_ctrl_b),
-		SH_PFC_PIN_GROUP(drif3_data0_b),
-		SH_PFC_PIN_GROUP(drif3_data1_b),
-	}
-};
-
-static const char * const audio_clk_groups[] = {
-	"audio_clk_a",
-	"audio_clk_b_a",
-	"audio_clk_b_b",
-	"audio_clk_b_c",
-	"audio_clk_c_a",
-	"audio_clk_c_b",
-	"audio_clk_c_c",
-	"audio_clkout_a",
-	"audio_clkout_b",
-	"audio_clkout1_a",
-	"audio_clkout1_b",
-	"audio_clkout1_c",
-	"audio_clkout2_a",
-	"audio_clkout2_b",
-	"audio_clkout2_c",
-	"audio_clkout3_a",
-	"audio_clkout3_b",
-	"audio_clkout3_c",
-};
-
-static const char * const avb_groups[] = {
-	"avb_link",
-	"avb_magic",
-	"avb_phy_int",
-	"avb_mii",
-	"avb_avtp_pps",
-	"avb_avtp_match",
-	"avb_avtp_capture",
-};
-
-static const char * const can0_groups[] = {
-	"can0_data",
-};
-
-static const char * const can1_groups[] = {
-	"can1_data",
-};
-
-static const char * const can_clk_groups[] = {
-	"can_clk",
-};
-
-static const char * const canfd0_groups[] = {
-	"canfd0_data",
-};
-
-static const char * const canfd1_groups[] = {
-	"canfd1_data",
-};
-
-static const char * const drif0_groups[] = {
-	"drif0_ctrl_a",
-	"drif0_data0_a",
-	"drif0_data1_a",
-	"drif0_ctrl_b",
-	"drif0_data0_b",
-	"drif0_data1_b",
-};
-
-static const char * const drif1_groups[] = {
-	"drif1_ctrl",
-	"drif1_data0",
-	"drif1_data1",
-};
-
-static const char * const drif2_groups[] = {
-	"drif2_ctrl_a",
-	"drif2_data0_a",
-	"drif2_data1_a",
-	"drif2_ctrl_b",
-	"drif2_data0_b",
-	"drif2_data1_b",
-};
-
-static const char * const drif3_groups[] = {
-	"drif3_ctrl_a",
-	"drif3_data0_a",
-	"drif3_data1_a",
-	"drif3_ctrl_b",
-	"drif3_data0_b",
-	"drif3_data1_b",
-};
-
-static const char * const du_groups[] = {
-	"du_rgb666",
-	"du_rgb888",
-	"du_clk_in_0",
-	"du_clk_in_1",
-	"du_clk_out_0",
-	"du_sync",
-	"du_disp_cde",
-	"du_cde",
-	"du_disp",
-};
-
-static const char * const hscif0_groups[] = {
-	"hscif0_data_a",
-	"hscif0_clk_a",
-	"hscif0_ctrl_a",
-	"hscif0_data_b",
-	"hscif0_clk_b",
-};
-
-static const char * const hscif1_groups[] = {
-	"hscif1_data_a",
-	"hscif1_clk_a",
-	"hscif1_data_b",
-	"hscif1_clk_b",
-	"hscif1_ctrl_b",
-};
-
-static const char * const hscif2_groups[] = {
-	"hscif2_data_a",
-	"hscif2_clk_a",
-	"hscif2_ctrl_a",
-	"hscif2_data_b",
-};
-
-static const char * const hscif3_groups[] = {
-	"hscif3_data_a",
-	"hscif3_data_b",
-	"hscif3_clk_b",
-	"hscif3_data_c",
-	"hscif3_clk_c",
-	"hscif3_ctrl_c",
-	"hscif3_data_d",
-	"hscif3_data_e",
-	"hscif3_ctrl_e",
-};
-
-static const char * const hscif4_groups[] = {
-	"hscif4_data_a",
-	"hscif4_clk_a",
-	"hscif4_ctrl_a",
-	"hscif4_data_b",
-	"hscif4_clk_b",
-	"hscif4_data_c",
-	"hscif4_data_d",
-	"hscif4_data_e",
-};
-
-static const char * const i2c1_groups[] = {
-	"i2c1_a",
-	"i2c1_b",
-	"i2c1_c",
-	"i2c1_d",
-};
-
-static const char * const i2c2_groups[] = {
-	"i2c2_a",
-	"i2c2_b",
-	"i2c2_c",
-	"i2c2_d",
-	"i2c2_e",
-};
-
-static const char * const i2c4_groups[] = {
-	"i2c4",
-};
-
-static const char * const i2c5_groups[] = {
-	"i2c5",
-};
-
-static const char * const i2c6_groups[] = {
-	"i2c6_a",
-	"i2c6_b",
-};
-
-static const char * const i2c7_groups[] = {
-	"i2c7_a",
-	"i2c7_b",
-};
-
-static const char * const intc_ex_groups[] = {
-	"intc_ex_irq0",
-	"intc_ex_irq1",
-	"intc_ex_irq2",
-	"intc_ex_irq3",
-	"intc_ex_irq4",
-	"intc_ex_irq5",
-};
-
-static const char * const msiof0_groups[] = {
-	"msiof0_clk",
-	"msiof0_sync",
-	"msiof0_ss1",
-	"msiof0_ss2",
-	"msiof0_txd",
-	"msiof0_rxd",
-};
-
-static const char * const msiof1_groups[] = {
-	"msiof1_clk",
-	"msiof1_sync",
-	"msiof1_ss1",
-	"msiof1_ss2",
-	"msiof1_txd",
-	"msiof1_rxd",
-};
-
-static const char * const msiof2_groups[] = {
-	"msiof2_clk_a",
-	"msiof2_sync_a",
-	"msiof2_ss1_a",
-	"msiof2_ss2_a",
-	"msiof2_txd_a",
-	"msiof2_rxd_a",
-	"msiof2_clk_b",
-	"msiof2_sync_b",
-	"msiof2_ss1_b",
-	"msiof2_ss2_b",
-	"msiof2_txd_b",
-	"msiof2_rxd_b",
-};
-
-static const char * const msiof3_groups[] = {
-	"msiof3_clk_a",
-	"msiof3_sync_a",
-	"msiof3_ss1_a",
-	"msiof3_ss2_a",
-	"msiof3_txd_a",
-	"msiof3_rxd_a",
-	"msiof3_clk_b",
-	"msiof3_sync_b",
-	"msiof3_ss1_b",
-	"msiof3_txd_b",
-	"msiof3_rxd_b",
-};
-
-static const char * const pwm0_groups[] = {
-	"pwm0_a",
-	"pwm0_b",
-};
-
-static const char * const pwm1_groups[] = {
-	"pwm1_a",
-	"pwm1_b",
-};
-
-static const char * const pwm2_groups[] = {
-	"pwm2_a",
-	"pwm2_b",
-	"pwm2_c",
-};
-
-static const char * const pwm3_groups[] = {
-	"pwm3_a",
-	"pwm3_b",
-	"pwm3_c",
-};
-
-static const char * const pwm4_groups[] = {
-	"pwm4_a",
-	"pwm4_b",
-};
-
-static const char * const pwm5_groups[] = {
-	"pwm5_a",
-	"pwm5_b",
-};
-
-static const char * const pwm6_groups[] = {
-	"pwm6_a",
-	"pwm6_b",
-};
-
-static const char * const scif0_groups[] = {
-	"scif0_data_a",
-	"scif0_clk_a",
-	"scif0_ctrl_a",
-	"scif0_data_b",
-	"scif0_clk_b",
-};
-
-static const char * const scif1_groups[] = {
-	"scif1_data",
-	"scif1_clk",
-	"scif1_ctrl",
-};
-
-static const char * const scif2_groups[] = {
-	"scif2_data_a",
-	"scif2_clk_a",
-	"scif2_data_b",
-};
-
-static const char * const scif3_groups[] = {
-	"scif3_data_a",
-	"scif3_clk_a",
-	"scif3_ctrl_a",
-	"scif3_data_b",
-	"scif3_data_c",
-	"scif3_clk_c",
-};
-
-static const char * const scif4_groups[] = {
-	"scif4_data_a",
-	"scif4_clk_a",
-	"scif4_ctrl_a",
-	"scif4_data_b",
-	"scif4_clk_b",
-	"scif4_data_c",
-	"scif4_ctrl_c",
-};
-
-static const char * const scif5_groups[] = {
-	"scif5_data_a",
-	"scif5_clk_a",
-	"scif5_data_b",
-	"scif5_data_c",
-};
-
-static const char * const scif_clk_groups[] = {
-	"scif_clk_a",
-	"scif_clk_b",
-};
-
-static const char * const sdhi0_groups[] = {
-	"sdhi0_data1",
-	"sdhi0_data4",
-	"sdhi0_ctrl",
-	"sdhi0_cd",
-	"sdhi0_wp",
-};
-
-static const char * const sdhi1_groups[] = {
-	"sdhi1_data1",
-	"sdhi1_data4",
-	"sdhi1_ctrl",
-	"sdhi1_cd",
-	"sdhi1_wp",
-};
-
-static const char * const sdhi3_groups[] = {
-	"sdhi3_data1",
-	"sdhi3_data4",
-	"sdhi3_data8",
-	"sdhi3_ctrl",
-	"sdhi3_cd",
-	"sdhi3_wp",
-	"sdhi3_ds",
-};
-
-static const char * const ssi_groups[] = {
-	"ssi0_data",
-	"ssi01239_ctrl",
-	"ssi1_data",
-	"ssi1_ctrl",
-	"ssi2_data",
-	"ssi2_ctrl_a",
-	"ssi2_ctrl_b",
-	"ssi3_data",
-	"ssi349_ctrl",
-	"ssi4_data",
-	"ssi4_ctrl",
-	"ssi5_data",
-	"ssi5_ctrl",
-	"ssi6_data",
-	"ssi6_ctrl",
-	"ssi7_data",
-	"ssi78_ctrl",
-	"ssi8_data",
-	"ssi9_data",
-	"ssi9_ctrl_a",
-	"ssi9_ctrl_b",
-};
-
-static const char * const tmu_groups[] = {
-	"tmu_tclk1_a",
-	"tmu_tclk1_b",
-	"tmu_tclk2_a",
-	"tmu_tclk2_b",
-};
-
-static const char * const usb0_groups[] = {
-	"usb0_a",
-	"usb0_b",
-	"usb0_id",
-};
-
-static const char * const usb30_groups[] = {
-	"usb30",
-	"usb30_id",
-};
-
-static const char * const vin4_groups[] = {
-	"vin4_data8_a",
-	"vin4_data10_a",
-	"vin4_data12_a",
-	"vin4_data16_a",
-	"vin4_data18_a",
-	"vin4_data20_a",
-	"vin4_data24_a",
-	"vin4_data8_b",
-	"vin4_data10_b",
-	"vin4_data12_b",
-	"vin4_data16_b",
-	"vin4_data18_b",
-	"vin4_data20_b",
-	"vin4_data24_b",
-	"vin4_sync",
-	"vin4_field",
-	"vin4_clkenb",
-	"vin4_clk",
-};
-
-static const char * const vin5_groups[] = {
-	"vin5_data8_a",
-	"vin5_data10_a",
-	"vin5_data12_a",
-	"vin5_data16_a",
-	"vin5_data8_b",
-	"vin5_sync_a",
-	"vin5_field_a",
-	"vin5_clkenb_a",
-	"vin5_clk_a",
-	"vin5_clk_b",
-};
-
-static const struct {
-	struct sh_pfc_function common[47];
-	struct sh_pfc_function automotive[4];
-} pinmux_functions = {
-	.common = {
-		SH_PFC_FUNCTION(audio_clk),
-		SH_PFC_FUNCTION(avb),
-		SH_PFC_FUNCTION(can0),
-		SH_PFC_FUNCTION(can1),
-		SH_PFC_FUNCTION(can_clk),
-		SH_PFC_FUNCTION(canfd0),
-		SH_PFC_FUNCTION(canfd1),
-		SH_PFC_FUNCTION(du),
-		SH_PFC_FUNCTION(hscif0),
-		SH_PFC_FUNCTION(hscif1),
-		SH_PFC_FUNCTION(hscif2),
-		SH_PFC_FUNCTION(hscif3),
-		SH_PFC_FUNCTION(hscif4),
-		SH_PFC_FUNCTION(i2c1),
-		SH_PFC_FUNCTION(i2c2),
-		SH_PFC_FUNCTION(i2c4),
-		SH_PFC_FUNCTION(i2c5),
-		SH_PFC_FUNCTION(i2c6),
-		SH_PFC_FUNCTION(i2c7),
-		SH_PFC_FUNCTION(intc_ex),
-		SH_PFC_FUNCTION(msiof0),
-		SH_PFC_FUNCTION(msiof1),
-		SH_PFC_FUNCTION(msiof2),
-		SH_PFC_FUNCTION(msiof3),
-		SH_PFC_FUNCTION(pwm0),
-		SH_PFC_FUNCTION(pwm1),
-		SH_PFC_FUNCTION(pwm2),
-		SH_PFC_FUNCTION(pwm3),
-		SH_PFC_FUNCTION(pwm4),
-		SH_PFC_FUNCTION(pwm5),
-		SH_PFC_FUNCTION(pwm6),
-		SH_PFC_FUNCTION(scif0),
-		SH_PFC_FUNCTION(scif1),
-		SH_PFC_FUNCTION(scif2),
-		SH_PFC_FUNCTION(scif3),
-		SH_PFC_FUNCTION(scif4),
-		SH_PFC_FUNCTION(scif5),
-		SH_PFC_FUNCTION(scif_clk),
-		SH_PFC_FUNCTION(sdhi0),
-		SH_PFC_FUNCTION(sdhi1),
-		SH_PFC_FUNCTION(sdhi3),
-		SH_PFC_FUNCTION(ssi),
-		SH_PFC_FUNCTION(tmu),
-		SH_PFC_FUNCTION(usb0),
-		SH_PFC_FUNCTION(usb30),
-		SH_PFC_FUNCTION(vin4),
-		SH_PFC_FUNCTION(vin5),
-	},
-	.automotive = {
-		SH_PFC_FUNCTION(drif0),
-		SH_PFC_FUNCTION(drif1),
-		SH_PFC_FUNCTION(drif2),
-		SH_PFC_FUNCTION(drif3),
-	}
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-#define F_(x, y)	FN_##y
-#define FM(x)		FN_##x
-	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_0_17_FN,	GPSR0_17,
-		GP_0_16_FN,	GPSR0_16,
-		GP_0_15_FN,	GPSR0_15,
-		GP_0_14_FN,	GPSR0_14,
-		GP_0_13_FN,	GPSR0_13,
-		GP_0_12_FN,	GPSR0_12,
-		GP_0_11_FN,	GPSR0_11,
-		GP_0_10_FN,	GPSR0_10,
-		GP_0_9_FN,	GPSR0_9,
-		GP_0_8_FN,	GPSR0_8,
-		GP_0_7_FN,	GPSR0_7,
-		GP_0_6_FN,	GPSR0_6,
-		GP_0_5_FN,	GPSR0_5,
-		GP_0_4_FN,	GPSR0_4,
-		GP_0_3_FN,	GPSR0_3,
-		GP_0_2_FN,	GPSR0_2,
-		GP_0_1_FN,	GPSR0_1,
-		GP_0_0_FN,	GPSR0_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_1_22_FN,	GPSR1_22,
-		GP_1_21_FN,	GPSR1_21,
-		GP_1_20_FN,	GPSR1_20,
-		GP_1_19_FN,	GPSR1_19,
-		GP_1_18_FN,	GPSR1_18,
-		GP_1_17_FN,	GPSR1_17,
-		GP_1_16_FN,	GPSR1_16,
-		GP_1_15_FN,	GPSR1_15,
-		GP_1_14_FN,	GPSR1_14,
-		GP_1_13_FN,	GPSR1_13,
-		GP_1_12_FN,	GPSR1_12,
-		GP_1_11_FN,	GPSR1_11,
-		GP_1_10_FN,	GPSR1_10,
-		GP_1_9_FN,	GPSR1_9,
-		GP_1_8_FN,	GPSR1_8,
-		GP_1_7_FN,	GPSR1_7,
-		GP_1_6_FN,	GPSR1_6,
-		GP_1_5_FN,	GPSR1_5,
-		GP_1_4_FN,	GPSR1_4,
-		GP_1_3_FN,	GPSR1_3,
-		GP_1_2_FN,	GPSR1_2,
-		GP_1_1_FN,	GPSR1_1,
-		GP_1_0_FN,	GPSR1_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_2_25_FN,	GPSR2_25,
-		GP_2_24_FN,	GPSR2_24,
-		GP_2_23_FN,	GPSR2_23,
-		GP_2_22_FN,	GPSR2_22,
-		GP_2_21_FN,	GPSR2_21,
-		GP_2_20_FN,	GPSR2_20,
-		GP_2_19_FN,	GPSR2_19,
-		GP_2_18_FN,	GPSR2_18,
-		GP_2_17_FN,	GPSR2_17,
-		GP_2_16_FN,	GPSR2_16,
-		GP_2_15_FN,	GPSR2_15,
-		GP_2_14_FN,	GPSR2_14,
-		GP_2_13_FN,	GPSR2_13,
-		GP_2_12_FN,	GPSR2_12,
-		GP_2_11_FN,	GPSR2_11,
-		GP_2_10_FN,	GPSR2_10,
-		GP_2_9_FN,	GPSR2_9,
-		GP_2_8_FN,	GPSR2_8,
-		GP_2_7_FN,	GPSR2_7,
-		GP_2_6_FN,	GPSR2_6,
-		GP_2_5_FN,	GPSR2_5,
-		GP_2_4_FN,	GPSR2_4,
-		GP_2_3_FN,	GPSR2_3,
-		GP_2_2_FN,	GPSR2_2,
-		GP_2_1_FN,	GPSR2_1,
-		GP_2_0_FN,	GPSR2_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_3_15_FN,	GPSR3_15,
-		GP_3_14_FN,	GPSR3_14,
-		GP_3_13_FN,	GPSR3_13,
-		GP_3_12_FN,	GPSR3_12,
-		GP_3_11_FN,	GPSR3_11,
-		GP_3_10_FN,	GPSR3_10,
-		GP_3_9_FN,	GPSR3_9,
-		GP_3_8_FN,	GPSR3_8,
-		GP_3_7_FN,	GPSR3_7,
-		GP_3_6_FN,	GPSR3_6,
-		GP_3_5_FN,	GPSR3_5,
-		GP_3_4_FN,	GPSR3_4,
-		GP_3_3_FN,	GPSR3_3,
-		GP_3_2_FN,	GPSR3_2,
-		GP_3_1_FN,	GPSR3_1,
-		GP_3_0_FN,	GPSR3_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_4_10_FN,	GPSR4_10,
-		GP_4_9_FN,	GPSR4_9,
-		GP_4_8_FN,	GPSR4_8,
-		GP_4_7_FN,	GPSR4_7,
-		GP_4_6_FN,	GPSR4_6,
-		GP_4_5_FN,	GPSR4_5,
-		GP_4_4_FN,	GPSR4_4,
-		GP_4_3_FN,	GPSR4_3,
-		GP_4_2_FN,	GPSR4_2,
-		GP_4_1_FN,	GPSR4_1,
-		GP_4_0_FN,	GPSR4_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_5_19_FN,	GPSR5_19,
-		GP_5_18_FN,	GPSR5_18,
-		GP_5_17_FN,	GPSR5_17,
-		GP_5_16_FN,	GPSR5_16,
-		GP_5_15_FN,	GPSR5_15,
-		GP_5_14_FN,	GPSR5_14,
-		GP_5_13_FN,	GPSR5_13,
-		GP_5_12_FN,	GPSR5_12,
-		GP_5_11_FN,	GPSR5_11,
-		GP_5_10_FN,	GPSR5_10,
-		GP_5_9_FN,	GPSR5_9,
-		GP_5_8_FN,	GPSR5_8,
-		GP_5_7_FN,	GPSR5_7,
-		GP_5_6_FN,	GPSR5_6,
-		GP_5_5_FN,	GPSR5_5,
-		GP_5_4_FN,	GPSR5_4,
-		GP_5_3_FN,	GPSR5_3,
-		GP_5_2_FN,	GPSR5_2,
-		GP_5_1_FN,	GPSR5_1,
-		GP_5_0_FN,	GPSR5_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_6_17_FN,	GPSR6_17,
-		GP_6_16_FN,	GPSR6_16,
-		GP_6_15_FN,	GPSR6_15,
-		GP_6_14_FN,	GPSR6_14,
-		GP_6_13_FN,	GPSR6_13,
-		GP_6_12_FN,	GPSR6_12,
-		GP_6_11_FN,	GPSR6_11,
-		GP_6_10_FN,	GPSR6_10,
-		GP_6_9_FN,	GPSR6_9,
-		GP_6_8_FN,	GPSR6_8,
-		GP_6_7_FN,	GPSR6_7,
-		GP_6_6_FN,	GPSR6_6,
-		GP_6_5_FN,	GPSR6_5,
-		GP_6_4_FN,	GPSR6_4,
-		GP_6_3_FN,	GPSR6_3,
-		GP_6_2_FN,	GPSR6_2,
-		GP_6_1_FN,	GPSR6_1,
-		GP_6_0_FN,	GPSR6_0, ))
-	},
-#undef F_
-#undef FM
-
-#define F_(x, y)	x,
-#define FM(x)		FN_##x,
-	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
-		IP0_31_28
-		IP0_27_24
-		IP0_23_20
-		IP0_19_16
-		IP0_15_12
-		IP0_11_8
-		IP0_7_4
-		IP0_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
-		IP1_31_28
-		IP1_27_24
-		IP1_23_20
-		IP1_19_16
-		IP1_15_12
-		IP1_11_8
-		IP1_7_4
-		IP1_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
-		IP2_31_28
-		IP2_27_24
-		IP2_23_20
-		IP2_19_16
-		IP2_15_12
-		IP2_11_8
-		IP2_7_4
-		IP2_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
-		IP3_31_28
-		IP3_27_24
-		IP3_23_20
-		IP3_19_16
-		IP3_15_12
-		IP3_11_8
-		IP3_7_4
-		IP3_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
-		IP4_31_28
-		IP4_27_24
-		IP4_23_20
-		IP4_19_16
-		IP4_15_12
-		IP4_11_8
-		IP4_7_4
-		IP4_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
-		IP5_31_28
-		IP5_27_24
-		IP5_23_20
-		IP5_19_16
-		IP5_15_12
-		IP5_11_8
-		IP5_7_4
-		IP5_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
-		IP6_31_28
-		IP6_27_24
-		IP6_23_20
-		IP6_19_16
-		IP6_15_12
-		IP6_11_8
-		IP6_7_4
-		IP6_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
-		IP7_31_28
-		IP7_27_24
-		IP7_23_20
-		IP7_19_16
-		IP7_15_12
-		IP7_11_8
-		IP7_7_4
-		IP7_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
-		IP8_31_28
-		IP8_27_24
-		IP8_23_20
-		IP8_19_16
-		IP8_15_12
-		IP8_11_8
-		IP8_7_4
-		IP8_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
-		IP9_31_28
-		IP9_27_24
-		IP9_23_20
-		IP9_19_16
-		IP9_15_12
-		IP9_11_8
-		IP9_7_4
-		IP9_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
-		IP10_31_28
-		IP10_27_24
-		IP10_23_20
-		IP10_19_16
-		IP10_15_12
-		IP10_11_8
-		IP10_7_4
-		IP10_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
-		IP11_31_28
-		IP11_27_24
-		IP11_23_20
-		IP11_19_16
-		IP11_15_12
-		IP11_11_8
-		IP11_7_4
-		IP11_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
-		IP12_31_28
-		IP12_27_24
-		IP12_23_20
-		IP12_19_16
-		IP12_15_12
-		IP12_11_8
-		IP12_7_4
-		IP12_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
-		IP13_31_28
-		IP13_27_24
-		IP13_23_20
-		IP13_19_16
-		IP13_15_12
-		IP13_11_8
-		IP13_7_4
-		IP13_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
-		IP14_31_28
-		IP14_27_24
-		IP14_23_20
-		IP14_19_16
-		IP14_15_12
-		IP14_11_8
-		IP14_7_4
-		IP14_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
-		IP15_31_28
-		IP15_27_24
-		IP15_23_20
-		IP15_19_16
-		IP15_15_12
-		IP15_11_8
-		IP15_7_4
-		IP15_3_0 ))
-	},
-#undef F_
-#undef FM
-
-#define F_(x, y)	x,
-#define FM(x)		FN_##x,
-	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
-			     GROUP(1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1,
-				   1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2),
-			     GROUP(
-		/* RESERVED 31 */
-		0, 0,
-		MOD_SEL0_30_29
-		MOD_SEL0_28
-		MOD_SEL0_27_26
-		MOD_SEL0_25
-		MOD_SEL0_24
-		MOD_SEL0_23
-		MOD_SEL0_22
-		MOD_SEL0_21_20
-		MOD_SEL0_19_18_17
-		MOD_SEL0_16
-		MOD_SEL0_15
-		MOD_SEL0_14
-		MOD_SEL0_13_12
-		MOD_SEL0_11_10
-		MOD_SEL0_9
-		MOD_SEL0_8
-		MOD_SEL0_7
-		MOD_SEL0_6_5
-		MOD_SEL0_4
-		MOD_SEL0_3
-		MOD_SEL0_2
-		MOD_SEL0_1_0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
-			     GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
-				   1, 2, 2, 2, 1, 1, 2, 1, 4),
-			     GROUP(
-		MOD_SEL1_31
-		MOD_SEL1_30
-		MOD_SEL1_29
-		MOD_SEL1_28
-		/* RESERVED 27 */
-		0, 0,
-		MOD_SEL1_26
-		MOD_SEL1_25
-		MOD_SEL1_24_23_22
-		MOD_SEL1_21_20_19
-		MOD_SEL1_18
-		MOD_SEL1_17
-		MOD_SEL1_16
-		MOD_SEL1_15
-		MOD_SEL1_14_13
-		MOD_SEL1_12_11
-		MOD_SEL1_10_9
-		MOD_SEL1_8
-		MOD_SEL1_7
-		MOD_SEL1_6_5
-		MOD_SEL1_4
-		/* RESERVED 3, 2, 1, 0  */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ },
-};
-
-enum ioctrl_regs {
-	POCCTRL0,
-	TDSELCTRL,
-};
-
-static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
-	[POCCTRL0] = { 0xe6060380, },
-	[TDSELCTRL] = { 0xe60603c0, },
-	{ /* sentinel */ },
-};
-
-static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
-				   u32 *pocctrl)
-{
-	int bit = -EINVAL;
-
-	*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
-
-	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
-		bit = pin & 0x1f;
-
-	if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10))
-		bit = (pin & 0x1f) + 19;
-
-	return bit;
-}
-
-static const struct pinmux_bias_reg pinmux_bias_regs[] = {
-	{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
-		 [0] = RCAR_GP_PIN(2, 23),	/* RD# */
-		 [1] = RCAR_GP_PIN(2, 22),	/* BS# */
-		 [2] = RCAR_GP_PIN(2, 21),	/* AVB_PHY_INT */
-		 [3] = PIN_AVB_MDC,		/* AVB_MDC */
-		 [4] = PIN_AVB_MDIO,		/* AVB_MDIO */
-		 [5] = RCAR_GP_PIN(2, 20),	/* AVB_TXCREFCLK */
-		 [6] = PIN_AVB_TD3,		/* AVB_TD3 */
-		 [7] = PIN_AVB_TD2,		/* AVB_TD2 */
-		 [8] = PIN_AVB_TD1,		/* AVB_TD1 */
-		 [9] = PIN_AVB_TD0,		/* AVB_TD0 */
-		[10] = PIN_AVB_TXC,		/* AVB_TXC */
-		[11] = PIN_AVB_TX_CTL,		/* AVB_TX_CTL */
-		[12] = RCAR_GP_PIN(2, 19),	/* AVB_RD3 */
-		[13] = RCAR_GP_PIN(2, 18),	/* AVB_RD2 */
-		[14] = RCAR_GP_PIN(2, 17),	/* AVB_RD1 */
-		[15] = RCAR_GP_PIN(2, 16),	/* AVB_RD0 */
-		[16] = RCAR_GP_PIN(2, 15),	/* AVB_RXC */
-		[17] = RCAR_GP_PIN(2, 14),	/* AVB_RX_CTL */
-		[18] = RCAR_GP_PIN(2, 13),	/* RPC_RESET# */
-		[19] = RCAR_GP_PIN(2, 12),	/* RPC_INT# */
-		[20] = RCAR_GP_PIN(2, 11),	/* QSPI1_SSL */
-		[21] = RCAR_GP_PIN(2, 10),	/* QSPI1_IO3 */
-		[22] = RCAR_GP_PIN(2,  9),	/* QSPI1_IO2 */
-		[23] = RCAR_GP_PIN(2,  8),	/* QSPI1_MISO/IO1 */
-		[24] = RCAR_GP_PIN(2,  7),	/* QSPI1_MOSI/IO0 */
-		[25] = RCAR_GP_PIN(2,  6),	/* QSPI1_SPCLK */
-		[26] = RCAR_GP_PIN(2,  5),	/* QSPI0_SSL */
-		[27] = RCAR_GP_PIN(2,  4),	/* QSPI0_IO3 */
-		[28] = RCAR_GP_PIN(2,  3),	/* QSPI0_IO2 */
-		[29] = RCAR_GP_PIN(2,  2),	/* QSPI0_MISO/IO1 */
-		[30] = RCAR_GP_PIN(2,  1),	/* QSPI0_MOSI/IO0 */
-		[31] = RCAR_GP_PIN(2,  0),	/* QSPI0_SPCLK */
-	} },
-	{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
-		 [0] = RCAR_GP_PIN(0,  4),	/* D4 */
-		 [1] = RCAR_GP_PIN(0,  3),	/* D3 */
-		 [2] = RCAR_GP_PIN(0,  2),	/* D2 */
-		 [3] = RCAR_GP_PIN(0,  1),	/* D1 */
-		 [4] = RCAR_GP_PIN(0,  0),	/* D0 */
-		 [5] = RCAR_GP_PIN(1, 22),	/* WE0# */
-		 [6] = RCAR_GP_PIN(1, 21),	/* CS0# */
-		 [7] = RCAR_GP_PIN(1, 20),	/* CLKOUT */
-		 [8] = RCAR_GP_PIN(1, 19),	/* A19 */
-		 [9] = RCAR_GP_PIN(1, 18),	/* A18 */
-		[10] = RCAR_GP_PIN(1, 17),	/* A17 */
-		[11] = RCAR_GP_PIN(1, 16),	/* A16 */
-		[12] = RCAR_GP_PIN(1, 15),	/* A15 */
-		[13] = RCAR_GP_PIN(1, 14),	/* A14 */
-		[14] = RCAR_GP_PIN(1, 13),	/* A13 */
-		[15] = RCAR_GP_PIN(1, 12),	/* A12 */
-		[16] = RCAR_GP_PIN(1, 11),	/* A11 */
-		[17] = RCAR_GP_PIN(1, 10),	/* A10 */
-		[18] = RCAR_GP_PIN(1,  9),	/* A9 */
-		[19] = RCAR_GP_PIN(1,  8),	/* A8 */
-		[20] = RCAR_GP_PIN(1,  7),	/* A7 */
-		[21] = RCAR_GP_PIN(1,  6),	/* A6 */
-		[22] = RCAR_GP_PIN(1,  5),	/* A5 */
-		[23] = RCAR_GP_PIN(1,  4),	/* A4 */
-		[24] = RCAR_GP_PIN(1,  3),	/* A3 */
-		[25] = RCAR_GP_PIN(1,  2),	/* A2 */
-		[26] = RCAR_GP_PIN(1,  1),	/* A1 */
-		[27] = RCAR_GP_PIN(1,  0),	/* A0 */
-		[28] = SH_PFC_PIN_NONE,
-		[29] = SH_PFC_PIN_NONE,
-		[30] = RCAR_GP_PIN(2, 25),	/* PUEN_EX_WAIT0 */
-		[31] = RCAR_GP_PIN(2, 24),	/* PUEN_RD/WR# */
-	} },
-	{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
-		 [0] = RCAR_GP_PIN(3,  1),	/* SD0_CMD */
-		 [1] = RCAR_GP_PIN(3,  0),	/* SD0_CLK */
-		 [2] = PIN_ASEBRK,		/* ASEBRK */
-		 [3] = SH_PFC_PIN_NONE,
-		 [4] = PIN_TDI,			/* TDI */
-		 [5] = PIN_TMS,			/* TMS */
-		 [6] = PIN_TCK,			/* TCK */
-		 [7] = PIN_TRST_N,		/* TRST# */
-		 [8] = SH_PFC_PIN_NONE,
-		 [9] = SH_PFC_PIN_NONE,
-		[10] = SH_PFC_PIN_NONE,
-		[11] = SH_PFC_PIN_NONE,
-		[12] = SH_PFC_PIN_NONE,
-		[13] = SH_PFC_PIN_NONE,
-		[14] = SH_PFC_PIN_NONE,
-		[15] = PIN_FSCLKST_N,		/* FSCLKST# */
-		[16] = RCAR_GP_PIN(0, 17),	/* SDA4 */
-		[17] = RCAR_GP_PIN(0, 16),	/* SCL4 */
-		[18] = SH_PFC_PIN_NONE,
-		[19] = SH_PFC_PIN_NONE,
-		[20] = PIN_PRESETOUT_N,		/* PRESETOUT# */
-		[21] = RCAR_GP_PIN(0, 15),	/* D15 */
-		[22] = RCAR_GP_PIN(0, 14),	/* D14 */
-		[23] = RCAR_GP_PIN(0, 13),	/* D13 */
-		[24] = RCAR_GP_PIN(0, 12),	/* D12 */
-		[25] = RCAR_GP_PIN(0, 11),	/* D11 */
-		[26] = RCAR_GP_PIN(0, 10),	/* D10 */
-		[27] = RCAR_GP_PIN(0,  9),	/* D9 */
-		[28] = RCAR_GP_PIN(0,  8),	/* D8 */
-		[29] = RCAR_GP_PIN(0,  7),	/* D7 */
-		[30] = RCAR_GP_PIN(0,  6),	/* D6 */
-		[31] = RCAR_GP_PIN(0,  5),	/* D5 */
-	} },
-	{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
-		 [0] = RCAR_GP_PIN(5,  0),	/* SCK0_A */
-		 [1] = RCAR_GP_PIN(5,  4),	/* RTS0#_A */
-		 [2] = RCAR_GP_PIN(5,  3),	/* CTS0#_A */
-		 [3] = RCAR_GP_PIN(5,  2),	/* TX0_A */
-		 [4] = RCAR_GP_PIN(5,  1),	/* RX0_A */
-		 [5] = SH_PFC_PIN_NONE,
-		 [6] = SH_PFC_PIN_NONE,
-		 [7] = RCAR_GP_PIN(3, 15),	/* SD1_WP */
-		 [8] = RCAR_GP_PIN(3, 14),	/* SD1_CD */
-		 [9] = RCAR_GP_PIN(3, 13),	/* SD0_WP */
-		[10] = RCAR_GP_PIN(3, 12),	/* SD0_CD */
-		[11] = RCAR_GP_PIN(4, 10),	/* SD3_DS */
-		[12] = RCAR_GP_PIN(4,  9),	/* SD3_DAT7 */
-		[13] = RCAR_GP_PIN(4,  8),	/* SD3_DAT6 */
-		[14] = RCAR_GP_PIN(4,  7),	/* SD3_DAT5 */
-		[15] = RCAR_GP_PIN(4,  6),	/* SD3_DAT4 */
-		[16] = RCAR_GP_PIN(4,  5),	/* SD3_DAT3 */
-		[17] = RCAR_GP_PIN(4,  4),	/* SD3_DAT2 */
-		[18] = RCAR_GP_PIN(4,  3),	/* SD3_DAT1 */
-		[19] = RCAR_GP_PIN(4,  2),	/* SD3_DAT0 */
-		[20] = RCAR_GP_PIN(4,  1),	/* SD3_CMD */
-		[21] = RCAR_GP_PIN(4,  0),	/* SD3_CLK */
-		[22] = RCAR_GP_PIN(3, 11),	/* SD1_DAT3 */
-		[23] = RCAR_GP_PIN(3, 10),	/* SD1_DAT2 */
-		[24] = RCAR_GP_PIN(3,  9),	/* SD1_DAT1 */
-		[25] = RCAR_GP_PIN(3,  8),	/* SD1_DAT0 */
-		[26] = RCAR_GP_PIN(3,  7),	/* SD1_CMD */
-		[27] = RCAR_GP_PIN(3,  6),	/* SD1_CLK */
-		[28] = RCAR_GP_PIN(3,  5),	/* SD0_DAT3 */
-		[29] = RCAR_GP_PIN(3,  4),	/* SD0_DAT2 */
-		[30] = RCAR_GP_PIN(3,  3),	/* SD0_DAT1 */
-		[31] = RCAR_GP_PIN(3,  2),	/* SD0_DAT0 */
-	} },
-	{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
-		 [0] = RCAR_GP_PIN(6,  8),	/* AUDIO_CLKA */
-		 [1] = RCAR_GP_PIN(6, 16),	/* SSI_SDATA6 */
-		 [2] = RCAR_GP_PIN(6, 15),	/* SSI_WS6 */
-		 [3] = RCAR_GP_PIN(6, 14),	/* SSI_SCK6 */
-		 [4] = RCAR_GP_PIN(6, 13),	/* SSI_SDATA5 */
-		 [5] = RCAR_GP_PIN(6, 12),	/* SSI_WS5 */
-		 [6] = RCAR_GP_PIN(6, 11),	/* SSI_SCK5 */
-		 [7] = RCAR_GP_PIN(6, 10),	/* SSI_SDATA4 */
-		 [8] = RCAR_GP_PIN(6,  7),	/* SSI_SDATA3 */
-		 [9] = RCAR_GP_PIN(6,  6),	/* SSI_WS349 */
-		[10] = RCAR_GP_PIN(6,  5),	/* SSI_SCK349 */
-		[11] = RCAR_GP_PIN(6,  4),	/* SSI_SDATA2 */
-		[12] = RCAR_GP_PIN(6,  3),	/* SSI_SDATA1 */
-		[13] = RCAR_GP_PIN(6,  2),	/* SSI_SDATA0 */
-		[14] = RCAR_GP_PIN(6,  1),	/* SSI_WS01239 */
-		[15] = RCAR_GP_PIN(6,  0),	/* SSI_SCK01239 */
-		[16] = PIN_MLB_REF,		/* MLB_REF */
-		[17] = RCAR_GP_PIN(5, 19),	/* MLB_DAT */
-		[18] = RCAR_GP_PIN(5, 18),	/* MLB_SIG */
-		[19] = RCAR_GP_PIN(5, 17),	/* MLB_CLK */
-		[20] = RCAR_GP_PIN(5, 16),	/* SSI_SDATA9 */
-		[21] = RCAR_GP_PIN(5, 15),	/* MSIOF0_SS2 */
-		[22] = RCAR_GP_PIN(5, 14),	/* MSIOF0_SS1 */
-		[23] = RCAR_GP_PIN(5, 13),	/* MSIOF0_SYNC */
-		[24] = RCAR_GP_PIN(5, 12),	/* MSIOF0_TXD */
-		[25] = RCAR_GP_PIN(5, 11),	/* MSIOF0_RXD */
-		[26] = RCAR_GP_PIN(5, 10),	/* MSIOF0_SCK */
-		[27] = RCAR_GP_PIN(5,  9),	/* RX2_A */
-		[28] = RCAR_GP_PIN(5,  8),	/* TX2_A */
-		[29] = RCAR_GP_PIN(5,  7),	/* SCK2_A */
-		[30] = RCAR_GP_PIN(5,  6),	/* TX1 */
-		[31] = RCAR_GP_PIN(5,  5),	/* RX1 */
-	} },
-	{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
-		 [0] = SH_PFC_PIN_NONE,
-		 [1] = SH_PFC_PIN_NONE,
-		 [2] = SH_PFC_PIN_NONE,
-		 [3] = SH_PFC_PIN_NONE,
-		 [4] = SH_PFC_PIN_NONE,
-		 [5] = SH_PFC_PIN_NONE,
-		 [6] = SH_PFC_PIN_NONE,
-		 [7] = SH_PFC_PIN_NONE,
-		 [8] = SH_PFC_PIN_NONE,
-		 [9] = SH_PFC_PIN_NONE,
-		[10] = SH_PFC_PIN_NONE,
-		[11] = SH_PFC_PIN_NONE,
-		[12] = SH_PFC_PIN_NONE,
-		[13] = SH_PFC_PIN_NONE,
-		[14] = SH_PFC_PIN_NONE,
-		[15] = SH_PFC_PIN_NONE,
-		[16] = SH_PFC_PIN_NONE,
-		[17] = SH_PFC_PIN_NONE,
-		[18] = SH_PFC_PIN_NONE,
-		[19] = SH_PFC_PIN_NONE,
-		[20] = SH_PFC_PIN_NONE,
-		[21] = SH_PFC_PIN_NONE,
-		[22] = SH_PFC_PIN_NONE,
-		[23] = SH_PFC_PIN_NONE,
-		[24] = SH_PFC_PIN_NONE,
-		[25] = SH_PFC_PIN_NONE,
-		[26] = SH_PFC_PIN_NONE,
-		[27] = SH_PFC_PIN_NONE,
-		[28] = SH_PFC_PIN_NONE,
-		[29] = SH_PFC_PIN_NONE,
-		[30] = RCAR_GP_PIN(6,  9),	/* PUEN_USB30_OVC */
-		[31] = RCAR_GP_PIN(6, 17),	/* PUEN_USB30_PWEN */
-	} },
-	{ /* sentinel */ },
-};
-
-static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc,
-					     unsigned int pin)
-{
-	const struct pinmux_bias_reg *reg;
-	unsigned int bit;
-
-	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
-	if (!reg)
-		return PIN_CONFIG_BIAS_DISABLE;
-
-	if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
-		return PIN_CONFIG_BIAS_DISABLE;
-	else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
-		return PIN_CONFIG_BIAS_PULL_UP;
-	else
-		return PIN_CONFIG_BIAS_PULL_DOWN;
-}
-
-static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
-				     unsigned int bias)
-{
-	const struct pinmux_bias_reg *reg;
-	u32 enable, updown;
-	unsigned int bit;
-
-	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
-	if (!reg)
-		return;
-
-	enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
-	if (bias != PIN_CONFIG_BIAS_DISABLE)
-		enable |= BIT(bit);
-
-	updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
-	if (bias == PIN_CONFIG_BIAS_PULL_UP)
-		updown |= BIT(bit);
-
-	sh_pfc_write(pfc, reg->pud, updown);
-	sh_pfc_write(pfc, reg->puen, enable);
-}
-
-static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = {
-	.pin_to_pocctrl = r8a77990_pin_to_pocctrl,
-	.get_bias = r8a77990_pinmux_get_bias,
-	.set_bias = r8a77990_pinmux_set_bias,
-};
-
-#ifdef CONFIG_PINCTRL_PFC_R8A774C0
-const struct sh_pfc_soc_info r8a774c0_pinmux_info = {
-	.name = "r8a774c0_pfc",
-	.ops = &r8a77990_pinmux_ops,
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups.common,
-	.nr_groups = ARRAY_SIZE(pinmux_groups.common),
-	.functions = pinmux_functions.common,
-	.nr_functions = ARRAY_SIZE(pinmux_functions.common),
-
-	.cfg_regs = pinmux_config_regs,
-	.bias_regs = pinmux_bias_regs,
-	.ioctrl_regs = pinmux_ioctrl_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
-#endif
-
-#ifdef CONFIG_PINCTRL_PFC_R8A77990
-const struct sh_pfc_soc_info r8a77990_pinmux_info = {
-	.name = "r8a77990_pfc",
-	.ops = &r8a77990_pinmux_ops,
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups.common,
-	.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
-		ARRAY_SIZE(pinmux_groups.automotive),
-	.functions = pinmux_functions.common,
-	.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
-		ARRAY_SIZE(pinmux_functions.automotive),
-
-	.cfg_regs = pinmux_config_regs,
-	.bias_regs = pinmux_bias_regs,
-	.ioctrl_regs = pinmux_ioctrl_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
-#endif
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
deleted file mode 100644
index c10b756476b1..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+++ /dev/null
@@ -1,2870 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * R8A77995 processor support - PFC hardware block.
- *
- * Copyright (C) 2017 Renesas Electronics Corp.
- *
- * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
- *
- * R-Car Gen3 processor support - PFC hardware block.
- *
- * Copyright (C) 2015  Renesas Electronics Corporation
- */
-
-#include <linux/errno.h>
-#include <linux/kernel.h>
-
-#include "core.h"
-#include "sh_pfc.h"
-
-#define CPU_ALL_GP(fn, sfx)			\
-		PORT_GP_9(0,  fn, sfx),		\
-		PORT_GP_32(1, fn, sfx),		\
-		PORT_GP_32(2, fn, sfx),		\
-		PORT_GP_CFG_10(3,  fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-		PORT_GP_32(4, fn, sfx),		\
-		PORT_GP_21(5, fn, sfx),		\
-		PORT_GP_14(6, fn, sfx)
-
-/*
- * F_() : just information
- * FM() : macro for FN_xxx / xxx_MARK
- */
-
-/* GPSR0 */
-#define GPSR0_8		F_(MLB_SIG,		IP0_27_24)
-#define GPSR0_7		F_(MLB_DAT,		IP0_23_20)
-#define GPSR0_6		F_(MLB_CLK,		IP0_19_16)
-#define GPSR0_5		F_(MSIOF2_RXD,		IP0_15_12)
-#define GPSR0_4		F_(MSIOF2_TXD,		IP0_11_8)
-#define GPSR0_3		F_(MSIOF2_SCK,		IP0_7_4)
-#define GPSR0_2		F_(IRQ0_A,		IP0_3_0)
-#define GPSR0_1		FM(USB0_OVC)
-#define GPSR0_0		FM(USB0_PWEN)
-
-/* GPSR1 */
-#define GPSR1_31	F_(QPOLB,		IP4_27_24)
-#define GPSR1_30	F_(QPOLA,		IP4_23_20)
-#define GPSR1_29	F_(DU_CDE,		IP4_19_16)
-#define GPSR1_28	F_(DU_DISP_CDE,		IP4_15_12)
-#define GPSR1_27	F_(DU_DISP,		IP4_11_8)
-#define GPSR1_26	F_(DU_VSYNC,		IP4_7_4)
-#define GPSR1_25	F_(DU_HSYNC,		IP4_3_0)
-#define GPSR1_24	F_(DU_DOTCLKOUT0,	IP3_31_28)
-#define GPSR1_23	F_(DU_DR7,		IP3_27_24)
-#define GPSR1_22	F_(DU_DR6,		IP3_23_20)
-#define GPSR1_21	F_(DU_DR5,		IP3_19_16)
-#define GPSR1_20	F_(DU_DR4,		IP3_15_12)
-#define GPSR1_19	F_(DU_DR3,		IP3_11_8)
-#define GPSR1_18	F_(DU_DR2,		IP3_7_4)
-#define GPSR1_17	F_(DU_DR1,		IP3_3_0)
-#define GPSR1_16	F_(DU_DR0,		IP2_31_28)
-#define GPSR1_15	F_(DU_DG7,		IP2_27_24)
-#define GPSR1_14	F_(DU_DG6,		IP2_23_20)
-#define GPSR1_13	F_(DU_DG5,		IP2_19_16)
-#define GPSR1_12	F_(DU_DG4,		IP2_15_12)
-#define GPSR1_11	F_(DU_DG3,		IP2_11_8)
-#define GPSR1_10	F_(DU_DG2,		IP2_7_4)
-#define GPSR1_9		F_(DU_DG1,		IP2_3_0)
-#define GPSR1_8		F_(DU_DG0,		IP1_31_28)
-#define GPSR1_7		F_(DU_DB7,		IP1_27_24)
-#define GPSR1_6		F_(DU_DB6,		IP1_23_20)
-#define GPSR1_5		F_(DU_DB5,		IP1_19_16)
-#define GPSR1_4		F_(DU_DB4,		IP1_15_12)
-#define GPSR1_3		F_(DU_DB3,		IP1_11_8)
-#define GPSR1_2		F_(DU_DB2,		IP1_7_4)
-#define GPSR1_1		F_(DU_DB1,		IP1_3_0)
-#define GPSR1_0		F_(DU_DB0,		IP0_31_28)
-
-/* GPSR2 */
-#define GPSR2_31	F_(NFCE_N,		IP8_19_16)
-#define GPSR2_30	F_(NFCLE,		IP8_15_12)
-#define GPSR2_29	F_(NFALE,		IP8_11_8)
-#define GPSR2_28	F_(VI4_CLKENB,		IP8_7_4)
-#define GPSR2_27	F_(VI4_FIELD,		IP8_3_0)
-#define GPSR2_26	F_(VI4_HSYNC_N,		IP7_31_28)
-#define GPSR2_25	F_(VI4_VSYNC_N,		IP7_27_24)
-#define GPSR2_24	F_(VI4_DATA23,		IP7_23_20)
-#define GPSR2_23	F_(VI4_DATA22,		IP7_19_16)
-#define GPSR2_22	F_(VI4_DATA21,		IP7_15_12)
-#define GPSR2_21	F_(VI4_DATA20,		IP7_11_8)
-#define GPSR2_20	F_(VI4_DATA19,		IP7_7_4)
-#define GPSR2_19	F_(VI4_DATA18,		IP7_3_0)
-#define GPSR2_18	F_(VI4_DATA17,		IP6_31_28)
-#define GPSR2_17	F_(VI4_DATA16,		IP6_27_24)
-#define GPSR2_16	F_(VI4_DATA15,		IP6_23_20)
-#define GPSR2_15	F_(VI4_DATA14,		IP6_19_16)
-#define GPSR2_14	F_(VI4_DATA13,		IP6_15_12)
-#define GPSR2_13	F_(VI4_DATA12,		IP6_11_8)
-#define GPSR2_12	F_(VI4_DATA11,		IP6_7_4)
-#define GPSR2_11	F_(VI4_DATA10,		IP6_3_0)
-#define GPSR2_10	F_(VI4_DATA9,		IP5_31_28)
-#define GPSR2_9		F_(VI4_DATA8,		IP5_27_24)
-#define GPSR2_8		F_(VI4_DATA7,		IP5_23_20)
-#define GPSR2_7		F_(VI4_DATA6,		IP5_19_16)
-#define GPSR2_6		F_(VI4_DATA5,		IP5_15_12)
-#define GPSR2_5		FM(VI4_DATA4)
-#define GPSR2_4		F_(VI4_DATA3,		IP5_11_8)
-#define GPSR2_3		F_(VI4_DATA2,		IP5_7_4)
-#define GPSR2_2		F_(VI4_DATA1,		IP5_3_0)
-#define GPSR2_1		F_(VI4_DATA0,		IP4_31_28)
-#define GPSR2_0		FM(VI4_CLK)
-
-/* GPSR3 */
-#define GPSR3_9		F_(NFDATA7,		IP9_31_28)
-#define GPSR3_8		F_(NFDATA6,		IP9_27_24)
-#define GPSR3_7		F_(NFDATA5,		IP9_23_20)
-#define GPSR3_6		F_(NFDATA4,		IP9_19_16)
-#define GPSR3_5		F_(NFDATA3,		IP9_15_12)
-#define GPSR3_4		F_(NFDATA2,		IP9_11_8)
-#define GPSR3_3		F_(NFDATA1,		IP9_7_4)
-#define GPSR3_2		F_(NFDATA0,		IP9_3_0)
-#define GPSR3_1		F_(NFWE_N,		IP8_31_28)
-#define GPSR3_0		F_(NFRE_N,		IP8_27_24)
-
-/* GPSR4 */
-#define GPSR4_31	F_(CAN0_RX_A,		IP12_27_24)
-#define GPSR4_30	F_(CAN1_TX_A,		IP13_7_4)
-#define GPSR4_29	F_(CAN1_RX_A,		IP13_3_0)
-#define GPSR4_28	F_(CAN0_TX_A,		IP12_31_28)
-#define GPSR4_27	FM(TX2)
-#define GPSR4_26	FM(RX2)
-#define GPSR4_25	F_(SCK2,		IP12_11_8)
-#define GPSR4_24	F_(TX1_A,		IP12_7_4)
-#define GPSR4_23	F_(RX1_A,		IP12_3_0)
-#define GPSR4_22	F_(SCK1_A,		IP11_31_28)
-#define GPSR4_21	F_(TX0_A,		IP11_27_24)
-#define GPSR4_20	F_(RX0_A,		IP11_23_20)
-#define GPSR4_19	F_(SCK0_A,		IP11_19_16)
-#define GPSR4_18	F_(MSIOF1_RXD,		IP11_15_12)
-#define GPSR4_17	F_(MSIOF1_TXD,		IP11_11_8)
-#define GPSR4_16	F_(MSIOF1_SCK,		IP11_7_4)
-#define GPSR4_15	FM(MSIOF0_RXD)
-#define GPSR4_14	FM(MSIOF0_TXD)
-#define GPSR4_13	FM(MSIOF0_SYNC)
-#define GPSR4_12	FM(MSIOF0_SCK)
-#define GPSR4_11	F_(SDA1,		IP11_3_0)
-#define GPSR4_10	F_(SCL1,		IP10_31_28)
-#define GPSR4_9		FM(SDA0)
-#define GPSR4_8		FM(SCL0)
-#define GPSR4_7		F_(SSI_WS4_A,		IP10_27_24)
-#define GPSR4_6		F_(SSI_SDATA4_A,	IP10_23_20)
-#define GPSR4_5		F_(SSI_SCK4_A,		IP10_19_16)
-#define GPSR4_4		F_(SSI_WS34,		IP10_15_12)
-#define GPSR4_3		F_(SSI_SDATA3,		IP10_11_8)
-#define GPSR4_2		F_(SSI_SCK34,		IP10_7_4)
-#define GPSR4_1		F_(AUDIO_CLKA,		IP10_3_0)
-#define GPSR4_0		F_(NFRB_N,		IP8_23_20)
-
-/* GPSR5 */
-#define GPSR5_20	FM(AVB0_LINK)
-#define GPSR5_19	FM(AVB0_PHY_INT)
-#define GPSR5_18	FM(AVB0_MAGIC)
-#define GPSR5_17	FM(AVB0_MDC)
-#define GPSR5_16	FM(AVB0_MDIO)
-#define GPSR5_15	FM(AVB0_TXCREFCLK)
-#define GPSR5_14	FM(AVB0_TD3)
-#define GPSR5_13	FM(AVB0_TD2)
-#define GPSR5_12	FM(AVB0_TD1)
-#define GPSR5_11	FM(AVB0_TD0)
-#define GPSR5_10	FM(AVB0_TXC)
-#define GPSR5_9		FM(AVB0_TX_CTL)
-#define GPSR5_8		FM(AVB0_RD3)
-#define GPSR5_7		FM(AVB0_RD2)
-#define GPSR5_6		FM(AVB0_RD1)
-#define GPSR5_5		FM(AVB0_RD0)
-#define GPSR5_4		FM(AVB0_RXC)
-#define GPSR5_3		FM(AVB0_RX_CTL)
-#define GPSR5_2		F_(CAN_CLK,		IP12_23_20)
-#define GPSR5_1		F_(TPU0TO1_A,		IP12_19_16)
-#define GPSR5_0		F_(TPU0TO0_A,		IP12_15_12)
-
-/* GPSR6 */
-#define GPSR6_13	FM(RPC_INT_N)
-#define GPSR6_12	FM(RPC_RESET_N)
-#define GPSR6_11	FM(QSPI1_SSL)
-#define GPSR6_10	FM(QSPI1_IO3)
-#define GPSR6_9		FM(QSPI1_IO2)
-#define GPSR6_8		FM(QSPI1_MISO_IO1)
-#define GPSR6_7		FM(QSPI1_MOSI_IO0)
-#define GPSR6_6		FM(QSPI1_SPCLK)
-#define GPSR6_5		FM(QSPI0_SSL)
-#define GPSR6_4		FM(QSPI0_IO3)
-#define GPSR6_3		FM(QSPI0_IO2)
-#define GPSR6_2		FM(QSPI0_MISO_IO1)
-#define GPSR6_1		FM(QSPI0_MOSI_IO0)
-#define GPSR6_0		FM(QSPI0_SPCLK)
-
-/* IPSRx */		/* 0 */			/* 1 */			/* 2 */			/* 3 */		/* 4 */			/* 5 */		/* 6  - F */
-#define IP0_3_0		FM(IRQ0_A)		FM(MSIOF2_SYNC_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_7_4		FM(MSIOF2_SCK)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_11_8	FM(MSIOF2_TXD)		FM(SCL3_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_15_12	FM(MSIOF2_RXD)		FM(SDA3_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_19_16	FM(MLB_CLK)		FM(MSIOF2_SYNC_A)	FM(SCK5_A)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_23_20	FM(MLB_DAT)		FM(MSIOF2_SS1)		FM(RX5_A)		FM(SCL3_B)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_27_24	FM(MLB_SIG)		FM(MSIOF2_SS2)		FM(TX5_A)		FM(SDA3_B)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_31_28	FM(DU_DB0)		FM(LCDOUT0)		FM(MSIOF3_TXD_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_3_0		FM(DU_DB1)		FM(LCDOUT1)		FM(MSIOF3_RXD_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_7_4		FM(DU_DB2)		FM(LCDOUT2)		FM(IRQ0_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_11_8	FM(DU_DB3)		FM(LCDOUT3)		FM(SCK5_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_15_12	FM(DU_DB4)		FM(LCDOUT4)		FM(RX5_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_19_16	FM(DU_DB5)		FM(LCDOUT5)		FM(TX5_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_23_20	FM(DU_DB6)		FM(LCDOUT6)		FM(MSIOF3_SS1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_27_24	FM(DU_DB7)		FM(LCDOUT7)		FM(MSIOF3_SS2_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_31_28	FM(DU_DG0)		FM(LCDOUT8)		FM(MSIOF3_SCK_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_3_0		FM(DU_DG1)		FM(LCDOUT9)		FM(MSIOF3_SYNC_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_7_4		FM(DU_DG2)		FM(LCDOUT10)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_11_8	FM(DU_DG3)		FM(LCDOUT11)		FM(IRQ1_A)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_15_12	FM(DU_DG4)		FM(LCDOUT12)		FM(HSCK3_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_19_16	FM(DU_DG5)		FM(LCDOUT13)		FM(HTX3_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_23_20	FM(DU_DG6)		FM(LCDOUT14)		FM(HRX3_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_27_24	FM(DU_DG7)		FM(LCDOUT15)		FM(SCK4_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_31_28	FM(DU_DR0)		FM(LCDOUT16)		FM(RX4_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_3_0		FM(DU_DR1)		FM(LCDOUT17)		FM(TX4_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_7_4		FM(DU_DR2)		FM(LCDOUT18)		FM(PWM0_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_11_8	FM(DU_DR3)		FM(LCDOUT19)		FM(PWM1_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_15_12	FM(DU_DR4)		FM(LCDOUT20)		FM(TCLK2_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_19_16	FM(DU_DR5)		FM(LCDOUT21)		FM(NMI)			F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_23_20	FM(DU_DR6)		FM(LCDOUT22)		FM(PWM2_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_27_24	FM(DU_DR7)		FM(LCDOUT23)		FM(TCLK1_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_31_28	FM(DU_DOTCLKOUT0)	FM(QCLK)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IPSRx */		/* 0 */			/* 1 */			/* 2 */			/* 3 */		/* 4 */			/* 5 */		/* 6  - F */
-#define IP4_3_0		FM(DU_HSYNC)		FM(QSTH_QHS)		FM(IRQ3_A)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_7_4		FM(DU_VSYNC)		FM(QSTVA_QVS)		FM(IRQ4_A)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_11_8	FM(DU_DISP)		FM(QSTVB_QVE)		FM(PWM3_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_15_12	FM(DU_DISP_CDE)		FM(QCPV_QDE)		FM(IRQ2_B)		FM(DU_DOTCLKIN1)F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_19_16	FM(DU_CDE)		FM(QSTB_QHE)		FM(SCK3_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_23_20	FM(QPOLA)		F_(0, 0)		FM(RX3_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_27_24	FM(QPOLB)		F_(0, 0)		FM(TX3_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_31_28	FM(VI4_DATA0)		FM(PWM0_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_3_0		FM(VI4_DATA1)		FM(PWM1_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_7_4		FM(VI4_DATA2)		FM(PWM2_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_11_8	FM(VI4_DATA3)		FM(PWM3_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_15_12	FM(VI4_DATA5)		FM(SCK4_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_19_16	FM(VI4_DATA6)		FM(IRQ2_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_23_20	FM(VI4_DATA7)		FM(TCLK2_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_27_24	FM(VI4_DATA8)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_31_28	FM(VI4_DATA9)		FM(MSIOF3_SS2_A)	FM(IRQ1_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_3_0		FM(VI4_DATA10)		FM(RX4_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_7_4		FM(VI4_DATA11)		FM(TX4_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_11_8	FM(VI4_DATA12)		FM(TCLK1_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_15_12	FM(VI4_DATA13)		FM(MSIOF3_SS1_A)	FM(HCTS3_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_19_16	FM(VI4_DATA14)		FM(SSI_SCK4_B)		FM(HRTS3_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_23_20	FM(VI4_DATA15)		FM(SSI_SDATA4_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_27_24	FM(VI4_DATA16)		FM(HRX3_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_31_28	FM(VI4_DATA17)		FM(HTX3_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_3_0		FM(VI4_DATA18)		FM(HSCK3_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_7_4		FM(VI4_DATA19)		FM(SSI_WS4_B)		F_(0, 0)		F_(0, 0)	FM(NFDATA15)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_11_8	FM(VI4_DATA20)		FM(MSIOF3_SYNC_A)	F_(0, 0)		F_(0, 0)	FM(NFDATA14)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_15_12	FM(VI4_DATA21)		FM(MSIOF3_TXD_A)	F_(0, 0)		F_(0, 0)	FM(NFDATA13)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_19_16	FM(VI4_DATA22)		FM(MSIOF3_RXD_A)	F_(0, 0)		F_(0, 0)	FM(NFDATA12)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_23_20	FM(VI4_DATA23)		FM(MSIOF3_SCK_A)	F_(0, 0)		F_(0, 0)	FM(NFDATA11)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_27_24	FM(VI4_VSYNC_N)		FM(SCK1_B)		F_(0, 0)		F_(0, 0)	FM(NFDATA10)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_31_28	FM(VI4_HSYNC_N)		FM(RX1_B)		F_(0, 0)		F_(0, 0)	FM(NFDATA9)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IPSRx */		/* 0 */			/* 1 */			/* 2 */			/* 3 */		/* 4 */			/* 5 */		/* 6  - F */
-#define IP8_3_0		FM(VI4_FIELD)		FM(AUDIO_CLKB)		FM(IRQ5_A)		FM(SCIF_CLK)	FM(NFDATA8)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_7_4		FM(VI4_CLKENB)		FM(TX1_B)		F_(0, 0)		F_(0, 0)	FM(NFWP_N)		FM(DVC_MUTE_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_11_8	FM(NFALE)		FM(SCL2_B)		FM(IRQ3_B)		FM(PWM0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_15_12	FM(NFCLE)		FM(SDA2_B)		FM(SCK3_A)		FM(PWM1_C)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_19_16	FM(NFCE_N)		F_(0, 0)		FM(RX3_A)		FM(PWM2_C)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_23_20	FM(NFRB_N)		F_(0, 0)		FM(TX3_A)		FM(PWM3_C)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_27_24	FM(NFRE_N)		FM(MMC_CMD)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_31_28	FM(NFWE_N)		FM(MMC_CLK)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_3_0		FM(NFDATA0)		FM(MMC_D0)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_7_4		FM(NFDATA1)		FM(MMC_D1)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_11_8	FM(NFDATA2)		FM(MMC_D2)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_15_12	FM(NFDATA3)		FM(MMC_D3)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_19_16	FM(NFDATA4)		FM(MMC_D4)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_23_20	FM(NFDATA5)		FM(MMC_D5)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_27_24	FM(NFDATA6)		FM(MMC_D6)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_31_28	FM(NFDATA7)		FM(MMC_D7)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_3_0	FM(AUDIO_CLKA)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(DVC_MUTE_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_7_4	FM(SSI_SCK34)		FM(FSO_CFE_0_N_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_11_8	FM(SSI_SDATA3)		FM(FSO_CFE_1_N_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_15_12	FM(SSI_WS34)		FM(FSO_TOE_N_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_19_16	FM(SSI_SCK4_A)		FM(HSCK0)		FM(AUDIO_CLKOUT)	FM(CAN0_RX_B)	FM(IRQ4_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_23_20	FM(SSI_SDATA4_A)	FM(HTX0)		FM(SCL2_A)		FM(CAN1_RX_B)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_27_24	FM(SSI_WS4_A)		FM(HRX0)		FM(SDA2_A)		FM(CAN1_TX_B)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_31_28	FM(SCL1)		FM(CTS1_N)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_3_0	FM(SDA1)		FM(RTS1_N)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_7_4	FM(MSIOF1_SCK)		FM(AVB0_AVTP_PPS_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_11_8	FM(MSIOF1_TXD)		FM(AVB0_AVTP_CAPTURE_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_15_12	FM(MSIOF1_RXD)		FM(AVB0_AVTP_MATCH_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_19_16	FM(SCK0_A)		FM(MSIOF1_SYNC)		FM(FSO_CFE_0_N_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_23_20	FM(RX0_A)		FM(MSIOF0_SS1)		FM(FSO_CFE_1_N_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_27_24	FM(TX0_A)		FM(MSIOF0_SS2)		FM(FSO_TOE_N_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_31_28	FM(SCK1_A)		FM(MSIOF1_SS2)		FM(TPU0TO2_B)		FM(CAN0_TX_B)	FM(AUDIO_CLKOUT1)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-/* IPSRx */		/* 0 */			/* 1 */			/* 2 */			/* 3 */		/* 4 */			/* 5 */		/* 6  - F */
-#define IP12_3_0	FM(RX1_A)		FM(CTS0_N)		FM(TPU0TO0_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_7_4	FM(TX1_A)		FM(RTS0_N)		FM(TPU0TO1_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_11_8	FM(SCK2)		FM(MSIOF1_SS1)		FM(TPU0TO3_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_15_12	FM(TPU0TO0_A)		FM(AVB0_AVTP_CAPTURE_A)	FM(HCTS0_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_19_16	FM(TPU0TO1_A)		FM(AVB0_AVTP_MATCH_A)	FM(HRTS0_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_23_20	FM(CAN_CLK)		FM(AVB0_AVTP_PPS_A)	FM(SCK0_B)		FM(IRQ5_B)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_27_24	FM(CAN0_RX_A)		FM(CANFD0_RX)		FM(RX0_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_31_28	FM(CAN0_TX_A)		FM(CANFD0_TX)		FM(TX0_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_3_0	FM(CAN1_RX_A)		FM(CANFD1_RX)		FM(TPU0TO2_A)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_7_4	FM(CAN1_TX_A)		FM(CANFD1_TX)		FM(TPU0TO3_A)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
-#define PINMUX_GPSR	\
-\
-		GPSR1_31	GPSR2_31			GPSR4_31		 \
-		GPSR1_30	GPSR2_30			GPSR4_30		 \
-		GPSR1_29	GPSR2_29			GPSR4_29		 \
-		GPSR1_28	GPSR2_28			GPSR4_28		 \
-		GPSR1_27	GPSR2_27			GPSR4_27		 \
-		GPSR1_26	GPSR2_26			GPSR4_26		 \
-		GPSR1_25	GPSR2_25			GPSR4_25		 \
-		GPSR1_24	GPSR2_24			GPSR4_24		 \
-		GPSR1_23	GPSR2_23			GPSR4_23		 \
-		GPSR1_22	GPSR2_22			GPSR4_22		 \
-		GPSR1_21	GPSR2_21			GPSR4_21		 \
-		GPSR1_20	GPSR2_20			GPSR4_20	GPSR5_20 \
-		GPSR1_19	GPSR2_19			GPSR4_19	GPSR5_19 \
-		GPSR1_18	GPSR2_18			GPSR4_18	GPSR5_18 \
-		GPSR1_17	GPSR2_17			GPSR4_17	GPSR5_17 \
-		GPSR1_16	GPSR2_16			GPSR4_16	GPSR5_16 \
-		GPSR1_15	GPSR2_15			GPSR4_15	GPSR5_15 \
-		GPSR1_14	GPSR2_14			GPSR4_14	GPSR5_14 \
-		GPSR1_13	GPSR2_13			GPSR4_13	GPSR5_13	GPSR6_13 \
-		GPSR1_12	GPSR2_12			GPSR4_12	GPSR5_12	GPSR6_12 \
-		GPSR1_11	GPSR2_11			GPSR4_11	GPSR5_11	GPSR6_11 \
-		GPSR1_10	GPSR2_10			GPSR4_10	GPSR5_10	GPSR6_10 \
-		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9		GPSR6_9 \
-GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8		GPSR6_8 \
-GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7		GPSR6_7 \
-GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6		GPSR6_6 \
-GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5		GPSR6_5 \
-GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4		GPSR6_4 \
-GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3		GPSR6_3 \
-GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2		GPSR6_2 \
-GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1		GPSR6_1 \
-GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0		GPSR6_0
-
-#define PINMUX_IPSR				\
-\
-FM(IP0_3_0)	IP0_3_0		FM(IP1_3_0)	IP1_3_0		FM(IP2_3_0)	IP2_3_0		FM(IP3_3_0)	IP3_3_0 \
-FM(IP0_7_4)	IP0_7_4		FM(IP1_7_4)	IP1_7_4		FM(IP2_7_4)	IP2_7_4		FM(IP3_7_4)	IP3_7_4 \
-FM(IP0_11_8)	IP0_11_8	FM(IP1_11_8)	IP1_11_8	FM(IP2_11_8)	IP2_11_8	FM(IP3_11_8)	IP3_11_8 \
-FM(IP0_15_12)	IP0_15_12	FM(IP1_15_12)	IP1_15_12	FM(IP2_15_12)	IP2_15_12	FM(IP3_15_12)	IP3_15_12 \
-FM(IP0_19_16)	IP0_19_16	FM(IP1_19_16)	IP1_19_16	FM(IP2_19_16)	IP2_19_16	FM(IP3_19_16)	IP3_19_16 \
-FM(IP0_23_20)	IP0_23_20	FM(IP1_23_20)	IP1_23_20	FM(IP2_23_20)	IP2_23_20	FM(IP3_23_20)	IP3_23_20 \
-FM(IP0_27_24)	IP0_27_24	FM(IP1_27_24)	IP1_27_24	FM(IP2_27_24)	IP2_27_24	FM(IP3_27_24)	IP3_27_24 \
-FM(IP0_31_28)	IP0_31_28	FM(IP1_31_28)	IP1_31_28	FM(IP2_31_28)	IP2_31_28	FM(IP3_31_28)	IP3_31_28 \
-\
-FM(IP4_3_0)	IP4_3_0		FM(IP5_3_0)	IP5_3_0		FM(IP6_3_0)	IP6_3_0		FM(IP7_3_0)	IP7_3_0 \
-FM(IP4_7_4)	IP4_7_4		FM(IP5_7_4)	IP5_7_4		FM(IP6_7_4)	IP6_7_4		FM(IP7_7_4)	IP7_7_4 \
-FM(IP4_11_8)	IP4_11_8	FM(IP5_11_8)	IP5_11_8	FM(IP6_11_8)	IP6_11_8	FM(IP7_11_8)	IP7_11_8 \
-FM(IP4_15_12)	IP4_15_12	FM(IP5_15_12)	IP5_15_12	FM(IP6_15_12)	IP6_15_12	FM(IP7_15_12)	IP7_15_12 \
-FM(IP4_19_16)	IP4_19_16	FM(IP5_19_16)	IP5_19_16	FM(IP6_19_16)	IP6_19_16	FM(IP7_19_16)	IP7_19_16 \
-FM(IP4_23_20)	IP4_23_20	FM(IP5_23_20)	IP5_23_20	FM(IP6_23_20)	IP6_23_20	FM(IP7_23_20)	IP7_23_20 \
-FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
-FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
-\
-FM(IP8_3_0)	IP8_3_0		FM(IP9_3_0)	IP9_3_0		FM(IP10_3_0)	IP10_3_0	FM(IP11_3_0)	IP11_3_0 \
-FM(IP8_7_4)	IP8_7_4		FM(IP9_7_4)	IP9_7_4		FM(IP10_7_4)	IP10_7_4	FM(IP11_7_4)	IP11_7_4 \
-FM(IP8_11_8)	IP8_11_8	FM(IP9_11_8)	IP9_11_8	FM(IP10_11_8)	IP10_11_8	FM(IP11_11_8)	IP11_11_8 \
-FM(IP8_15_12)	IP8_15_12	FM(IP9_15_12)	IP9_15_12	FM(IP10_15_12)	IP10_15_12	FM(IP11_15_12)	IP11_15_12 \
-FM(IP8_19_16)	IP8_19_16	FM(IP9_19_16)	IP9_19_16	FM(IP10_19_16)	IP10_19_16	FM(IP11_19_16)	IP11_19_16 \
-FM(IP8_23_20)	IP8_23_20	FM(IP9_23_20)	IP9_23_20	FM(IP10_23_20)	IP10_23_20	FM(IP11_23_20)	IP11_23_20 \
-FM(IP8_27_24)	IP8_27_24	FM(IP9_27_24)	IP9_27_24	FM(IP10_27_24)	IP10_27_24	FM(IP11_27_24)	IP11_27_24 \
-FM(IP8_31_28)	IP8_31_28	FM(IP9_31_28)	IP9_31_28	FM(IP10_31_28)	IP10_31_28	FM(IP11_31_28)	IP11_31_28 \
-\
-FM(IP12_3_0)	IP12_3_0	FM(IP13_3_0)	IP13_3_0 \
-FM(IP12_7_4)	IP12_7_4	FM(IP13_7_4)	IP13_7_4 \
-FM(IP12_11_8)	IP12_11_8 \
-FM(IP12_15_12)	IP12_15_12 \
-FM(IP12_19_16)	IP12_19_16 \
-FM(IP12_23_20)	IP12_23_20 \
-FM(IP12_27_24)	IP12_27_24 \
-FM(IP12_31_28)	IP12_31_28 \
-
-/* The bit numbering in MOD_SEL fields is reversed */
-#define REV4(f0, f1, f2, f3)			f0 f2 f1 f3
-
-/* MOD_SEL0 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */
-#define MOD_SEL0_30		FM(SEL_MSIOF2_0)	FM(SEL_MSIOF2_1)
-#define MOD_SEL0_29		FM(SEL_I2C3_0)		FM(SEL_I2C3_1)
-#define MOD_SEL0_28		FM(SEL_SCIF5_0)		FM(SEL_SCIF5_1)
-#define MOD_SEL0_27		FM(SEL_MSIOF3_0)	FM(SEL_MSIOF3_1)
-#define MOD_SEL0_26		FM(SEL_HSCIF3_0)	FM(SEL_HSCIF3_1)
-#define MOD_SEL0_25		FM(SEL_SCIF4_0)		FM(SEL_SCIF4_1)
-#define MOD_SEL0_24_23	   REV4(FM(SEL_PWM0_0),		FM(SEL_PWM0_1),		FM(SEL_PWM0_2),		F_(0, 0))
-#define MOD_SEL0_22_21	   REV4(FM(SEL_PWM1_0),		FM(SEL_PWM1_1),		FM(SEL_PWM1_2),		F_(0, 0))
-#define MOD_SEL0_20_19	   REV4(FM(SEL_PWM2_0),		FM(SEL_PWM2_1),		FM(SEL_PWM2_2),		F_(0, 0))
-#define MOD_SEL0_18_17	   REV4(FM(SEL_PWM3_0),		FM(SEL_PWM3_1),		FM(SEL_PWM3_2),		F_(0, 0))
-#define MOD_SEL0_15		FM(SEL_IRQ_0_0)		FM(SEL_IRQ_0_1)
-#define MOD_SEL0_14		FM(SEL_IRQ_1_0)		FM(SEL_IRQ_1_1)
-#define MOD_SEL0_13		FM(SEL_IRQ_2_0)		FM(SEL_IRQ_2_1)
-#define MOD_SEL0_12		FM(SEL_IRQ_3_0)		FM(SEL_IRQ_3_1)
-#define MOD_SEL0_11		FM(SEL_IRQ_4_0)		FM(SEL_IRQ_4_1)
-#define MOD_SEL0_10		FM(SEL_IRQ_5_0)		FM(SEL_IRQ_5_1)
-#define MOD_SEL0_5		FM(SEL_TMU_0_0)		FM(SEL_TMU_0_1)
-#define MOD_SEL0_4		FM(SEL_TMU_1_0)		FM(SEL_TMU_1_1)
-#define MOD_SEL0_3		FM(SEL_SCIF3_0)		FM(SEL_SCIF3_1)
-#define MOD_SEL0_2		FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
-#define MOD_SEL0_1		FM(SEL_SCU_0)		FM(SEL_SCU_1)
-#define MOD_SEL0_0		FM(SEL_RFSO_0)		FM(SEL_RFSO_1)
-
-#define MOD_SEL1_31		FM(SEL_CAN0_0)		FM(SEL_CAN0_1)
-#define MOD_SEL1_30		FM(SEL_CAN1_0)		FM(SEL_CAN1_1)
-#define MOD_SEL1_29		FM(SEL_I2C2_0)		FM(SEL_I2C2_1)
-#define MOD_SEL1_28		FM(SEL_ETHERAVB_0)	FM(SEL_ETHERAVB_1)
-#define MOD_SEL1_27		FM(SEL_SCIF0_0)		FM(SEL_SCIF0_1)
-#define MOD_SEL1_26		FM(SEL_SSIF4_0)		FM(SEL_SSIF4_1)
-
-
-#define PINMUX_MOD_SELS	\
-\
-		MOD_SEL1_31 \
-MOD_SEL0_30	MOD_SEL1_30 \
-MOD_SEL0_29	MOD_SEL1_29 \
-MOD_SEL0_28	MOD_SEL1_28 \
-MOD_SEL0_27	MOD_SEL1_27 \
-MOD_SEL0_26	MOD_SEL1_26 \
-MOD_SEL0_25 \
-MOD_SEL0_24_23 \
-MOD_SEL0_22_21 \
-MOD_SEL0_20_19 \
-MOD_SEL0_18_17 \
-MOD_SEL0_15 \
-MOD_SEL0_14 \
-MOD_SEL0_13 \
-MOD_SEL0_12 \
-MOD_SEL0_11 \
-MOD_SEL0_10 \
-MOD_SEL0_5 \
-MOD_SEL0_4 \
-MOD_SEL0_3 \
-MOD_SEL0_2 \
-MOD_SEL0_1 \
-MOD_SEL0_0
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	GP_ALL(DATA),
-	PINMUX_DATA_END,
-
-#define F_(x, y)
-#define FM(x)	FN_##x,
-	PINMUX_FUNCTION_BEGIN,
-	GP_ALL(FN),
-	PINMUX_GPSR
-	PINMUX_IPSR
-	PINMUX_MOD_SELS
-	PINMUX_FUNCTION_END,
-#undef F_
-#undef FM
-
-#define F_(x, y)
-#define FM(x)	x##_MARK,
-	PINMUX_MARK_BEGIN,
-	PINMUX_GPSR
-	PINMUX_IPSR
-	PINMUX_MOD_SELS
-	PINMUX_MARK_END,
-#undef F_
-#undef FM
-};
-
-static const u16 pinmux_data[] = {
-	PINMUX_DATA_GP_ALL(),
-
-	PINMUX_SINGLE(USB0_OVC),
-	PINMUX_SINGLE(USB0_PWEN),
-	PINMUX_SINGLE(VI4_DATA4),
-	PINMUX_SINGLE(VI4_CLK),
-	PINMUX_SINGLE(TX2),
-	PINMUX_SINGLE(RX2),
-	PINMUX_SINGLE(AVB0_LINK),
-	PINMUX_SINGLE(AVB0_PHY_INT),
-	PINMUX_SINGLE(AVB0_MAGIC),
-	PINMUX_SINGLE(AVB0_MDC),
-	PINMUX_SINGLE(AVB0_MDIO),
-	PINMUX_SINGLE(AVB0_TXCREFCLK),
-	PINMUX_SINGLE(AVB0_TD3),
-	PINMUX_SINGLE(AVB0_TD2),
-	PINMUX_SINGLE(AVB0_TD1),
-	PINMUX_SINGLE(AVB0_TD0),
-	PINMUX_SINGLE(AVB0_TXC),
-	PINMUX_SINGLE(AVB0_TX_CTL),
-	PINMUX_SINGLE(AVB0_RD3),
-	PINMUX_SINGLE(AVB0_RD2),
-	PINMUX_SINGLE(AVB0_RD1),
-	PINMUX_SINGLE(AVB0_RD0),
-	PINMUX_SINGLE(AVB0_RXC),
-	PINMUX_SINGLE(AVB0_RX_CTL),
-	PINMUX_SINGLE(RPC_INT_N),
-	PINMUX_SINGLE(RPC_RESET_N),
-	PINMUX_SINGLE(QSPI1_SSL),
-	PINMUX_SINGLE(QSPI1_IO3),
-	PINMUX_SINGLE(QSPI1_IO2),
-	PINMUX_SINGLE(QSPI1_MISO_IO1),
-	PINMUX_SINGLE(QSPI1_MOSI_IO0),
-	PINMUX_SINGLE(QSPI1_SPCLK),
-	PINMUX_SINGLE(QSPI0_SSL),
-	PINMUX_SINGLE(QSPI0_IO3),
-	PINMUX_SINGLE(QSPI0_IO2),
-	PINMUX_SINGLE(QSPI0_MISO_IO1),
-	PINMUX_SINGLE(QSPI0_MOSI_IO0),
-	PINMUX_SINGLE(QSPI0_SPCLK),
-	PINMUX_SINGLE(SCL0),
-	PINMUX_SINGLE(SDA0),
-	PINMUX_SINGLE(MSIOF0_RXD),
-	PINMUX_SINGLE(MSIOF0_TXD),
-	PINMUX_SINGLE(MSIOF0_SYNC),
-	PINMUX_SINGLE(MSIOF0_SCK),
-
-	/* IPSR0 */
-	PINMUX_IPSR_MSEL(IP0_3_0,	IRQ0_A, SEL_IRQ_0_0),
-	PINMUX_IPSR_MSEL(IP0_3_0,	MSIOF2_SYNC_B, SEL_MSIOF2_1),
-
-	PINMUX_IPSR_GPSR(IP0_7_4,	MSIOF2_SCK),
-
-	PINMUX_IPSR_GPSR(IP0_11_8,	MSIOF2_TXD),
-	PINMUX_IPSR_MSEL(IP0_11_8,	SCL3_A, SEL_I2C3_0),
-
-	PINMUX_IPSR_GPSR(IP0_15_12,	MSIOF2_RXD),
-	PINMUX_IPSR_MSEL(IP0_15_12,	SDA3_A, SEL_I2C3_0),
-
-	PINMUX_IPSR_GPSR(IP0_19_16,	MLB_CLK),
-	PINMUX_IPSR_MSEL(IP0_19_16,	MSIOF2_SYNC_A, SEL_MSIOF2_0),
-	PINMUX_IPSR_MSEL(IP0_19_16,	SCK5_A, SEL_SCIF5_0),
-
-	PINMUX_IPSR_GPSR(IP0_23_20,	MLB_DAT),
-	PINMUX_IPSR_GPSR(IP0_23_20,	MSIOF2_SS1),
-	PINMUX_IPSR_MSEL(IP0_23_20,	RX5_A, SEL_SCIF5_0),
-	PINMUX_IPSR_MSEL(IP0_23_20,	SCL3_B, SEL_I2C3_1),
-
-	PINMUX_IPSR_GPSR(IP0_27_24,	MLB_SIG),
-	PINMUX_IPSR_GPSR(IP0_27_24,	MSIOF2_SS2),
-	PINMUX_IPSR_MSEL(IP0_27_24,	TX5_A, SEL_SCIF5_0),
-	PINMUX_IPSR_MSEL(IP0_27_24,	SDA3_B, SEL_I2C3_1),
-
-	PINMUX_IPSR_GPSR(IP0_31_28,	DU_DB0),
-	PINMUX_IPSR_GPSR(IP0_31_28,	LCDOUT0),
-	PINMUX_IPSR_MSEL(IP0_31_28,	MSIOF3_TXD_B, SEL_MSIOF3_1),
-
-	/* IPSR1 */
-	PINMUX_IPSR_GPSR(IP1_3_0,	DU_DB1),
-	PINMUX_IPSR_GPSR(IP1_3_0,	LCDOUT1),
-	PINMUX_IPSR_MSEL(IP1_3_0,	MSIOF3_RXD_B, SEL_MSIOF3_1),
-
-	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DB2),
-	PINMUX_IPSR_GPSR(IP1_7_4,	LCDOUT2),
-	PINMUX_IPSR_MSEL(IP1_7_4,	IRQ0_B, SEL_IRQ_0_1),
-
-	PINMUX_IPSR_GPSR(IP1_11_8,	DU_DB3),
-	PINMUX_IPSR_GPSR(IP1_11_8,	LCDOUT3),
-	PINMUX_IPSR_MSEL(IP1_11_8,	SCK5_B, SEL_SCIF5_1),
-
-	PINMUX_IPSR_GPSR(IP1_15_12,	DU_DB4),
-	PINMUX_IPSR_GPSR(IP1_15_12,	LCDOUT4),
-	PINMUX_IPSR_MSEL(IP1_15_12,	RX5_B, SEL_SCIF5_1),
-
-	PINMUX_IPSR_GPSR(IP1_19_16,	DU_DB5),
-	PINMUX_IPSR_GPSR(IP1_19_16,	LCDOUT5),
-	PINMUX_IPSR_MSEL(IP1_19_16,	TX5_B, SEL_SCIF5_1),
-
-	PINMUX_IPSR_GPSR(IP1_23_20,	DU_DB6),
-	PINMUX_IPSR_GPSR(IP1_23_20,	LCDOUT6),
-	PINMUX_IPSR_MSEL(IP1_23_20,	MSIOF3_SS1_B, SEL_MSIOF3_1),
-
-	PINMUX_IPSR_GPSR(IP1_27_24,	DU_DB7),
-	PINMUX_IPSR_GPSR(IP1_27_24,	LCDOUT7),
-	PINMUX_IPSR_MSEL(IP1_27_24,	MSIOF3_SS2_B, SEL_MSIOF3_1),
-
-	PINMUX_IPSR_GPSR(IP1_31_28,	DU_DG0),
-	PINMUX_IPSR_GPSR(IP1_31_28,	LCDOUT8),
-	PINMUX_IPSR_MSEL(IP1_31_28,	MSIOF3_SCK_B, SEL_MSIOF3_1),
-
-	/* IPSR2 */
-	PINMUX_IPSR_GPSR(IP2_3_0,	DU_DG1),
-	PINMUX_IPSR_GPSR(IP2_3_0,	LCDOUT9),
-	PINMUX_IPSR_MSEL(IP2_3_0,	MSIOF3_SYNC_B, SEL_MSIOF3_1),
-
-	PINMUX_IPSR_GPSR(IP2_7_4,	DU_DG2),
-	PINMUX_IPSR_GPSR(IP2_7_4,	LCDOUT10),
-
-	PINMUX_IPSR_GPSR(IP2_11_8,	DU_DG3),
-	PINMUX_IPSR_GPSR(IP2_11_8,	LCDOUT11),
-	PINMUX_IPSR_MSEL(IP2_11_8,	IRQ1_A, SEL_IRQ_1_0),
-
-	PINMUX_IPSR_GPSR(IP2_15_12,	DU_DG4),
-	PINMUX_IPSR_GPSR(IP2_15_12,	LCDOUT12),
-	PINMUX_IPSR_MSEL(IP2_15_12,	HSCK3_B, SEL_HSCIF3_1),
-
-	PINMUX_IPSR_GPSR(IP2_19_16,	DU_DG5),
-	PINMUX_IPSR_GPSR(IP2_19_16,	LCDOUT13),
-	PINMUX_IPSR_MSEL(IP2_19_16,	HTX3_B, SEL_HSCIF3_1),
-
-	PINMUX_IPSR_GPSR(IP2_23_20,	DU_DG6),
-	PINMUX_IPSR_GPSR(IP2_23_20,	LCDOUT14),
-	PINMUX_IPSR_MSEL(IP2_23_20,	HRX3_B, SEL_HSCIF3_1),
-
-	PINMUX_IPSR_GPSR(IP2_27_24,	DU_DG7),
-	PINMUX_IPSR_GPSR(IP2_27_24,	LCDOUT15),
-	PINMUX_IPSR_MSEL(IP2_27_24,	SCK4_B, SEL_SCIF4_1),
-
-	PINMUX_IPSR_GPSR(IP2_31_28,	DU_DR0),
-	PINMUX_IPSR_GPSR(IP2_31_28,	LCDOUT16),
-	PINMUX_IPSR_MSEL(IP2_31_28,	RX4_B, SEL_SCIF4_1),
-
-	/* IPSR3 */
-	PINMUX_IPSR_GPSR(IP3_3_0,	DU_DR1),
-	PINMUX_IPSR_GPSR(IP3_3_0,	LCDOUT17),
-	PINMUX_IPSR_MSEL(IP3_3_0,	TX4_B, SEL_SCIF4_1),
-
-	PINMUX_IPSR_GPSR(IP3_7_4,	DU_DR2),
-	PINMUX_IPSR_GPSR(IP3_7_4,	LCDOUT18),
-	PINMUX_IPSR_MSEL(IP3_7_4,	PWM0_B, SEL_PWM0_2),
-
-	PINMUX_IPSR_GPSR(IP3_11_8,	DU_DR3),
-	PINMUX_IPSR_GPSR(IP3_11_8,	LCDOUT19),
-	PINMUX_IPSR_MSEL(IP3_11_8,	PWM1_B, SEL_PWM1_2),
-
-	PINMUX_IPSR_GPSR(IP3_15_12,	DU_DR4),
-	PINMUX_IPSR_GPSR(IP3_15_12,	LCDOUT20),
-	PINMUX_IPSR_MSEL(IP3_15_12,	TCLK2_B, SEL_TMU_0_1),
-
-	PINMUX_IPSR_GPSR(IP3_19_16,	DU_DR5),
-	PINMUX_IPSR_GPSR(IP3_19_16,	LCDOUT21),
-	PINMUX_IPSR_GPSR(IP3_19_16,	NMI),
-
-	PINMUX_IPSR_GPSR(IP3_23_20,	DU_DR6),
-	PINMUX_IPSR_GPSR(IP3_23_20,	LCDOUT22),
-	PINMUX_IPSR_MSEL(IP3_23_20,	PWM2_B, SEL_PWM2_2),
-
-	PINMUX_IPSR_GPSR(IP3_27_24,	DU_DR7),
-	PINMUX_IPSR_GPSR(IP3_27_24,	LCDOUT23),
-	PINMUX_IPSR_MSEL(IP3_27_24,	TCLK1_B, SEL_TMU_1_1),
-
-	PINMUX_IPSR_GPSR(IP3_31_28,	DU_DOTCLKOUT0),
-	PINMUX_IPSR_GPSR(IP3_31_28,	QCLK),
-
-	/* IPSR4 */
-	PINMUX_IPSR_GPSR(IP4_3_0,	DU_HSYNC),
-	PINMUX_IPSR_GPSR(IP4_3_0,	QSTH_QHS),
-	PINMUX_IPSR_MSEL(IP4_3_0,	IRQ3_A, SEL_IRQ_3_0),
-
-	PINMUX_IPSR_GPSR(IP4_7_4,	DU_VSYNC),
-	PINMUX_IPSR_GPSR(IP4_7_4,	QSTVA_QVS),
-	PINMUX_IPSR_MSEL(IP4_7_4,	IRQ4_A, SEL_IRQ_4_0),
-
-	PINMUX_IPSR_GPSR(IP4_11_8,	DU_DISP),
-	PINMUX_IPSR_GPSR(IP4_11_8,	QSTVB_QVE),
-	PINMUX_IPSR_MSEL(IP4_11_8,	PWM3_B, SEL_PWM3_2),
-
-	PINMUX_IPSR_GPSR(IP4_15_12,	DU_DISP_CDE),
-	PINMUX_IPSR_GPSR(IP4_15_12,	QCPV_QDE),
-	PINMUX_IPSR_MSEL(IP4_15_12,	IRQ2_B, SEL_IRQ_2_1),
-	PINMUX_IPSR_GPSR(IP4_15_12,	DU_DOTCLKIN1),
-
-	PINMUX_IPSR_GPSR(IP4_19_16,	DU_CDE),
-	PINMUX_IPSR_GPSR(IP4_19_16,	QSTB_QHE),
-	PINMUX_IPSR_MSEL(IP4_19_16,	SCK3_B, SEL_SCIF3_1),
-
-	PINMUX_IPSR_GPSR(IP4_23_20,	QPOLA),
-	PINMUX_IPSR_MSEL(IP4_23_20,	RX3_B, SEL_SCIF3_1),
-
-	PINMUX_IPSR_GPSR(IP4_27_24,	QPOLB),
-	PINMUX_IPSR_MSEL(IP4_27_24,	TX3_B, SEL_SCIF3_1),
-
-	PINMUX_IPSR_GPSR(IP4_31_28,	VI4_DATA0),
-	PINMUX_IPSR_MSEL(IP4_31_28,	PWM0_A, SEL_PWM0_0),
-
-	/* IPSR5 */
-	PINMUX_IPSR_GPSR(IP5_3_0,	VI4_DATA1),
-	PINMUX_IPSR_MSEL(IP5_3_0,	PWM1_A, SEL_PWM1_0),
-
-	PINMUX_IPSR_GPSR(IP5_7_4,	VI4_DATA2),
-	PINMUX_IPSR_MSEL(IP5_7_4,	PWM2_A, SEL_PWM2_0),
-
-	PINMUX_IPSR_GPSR(IP5_11_8,	VI4_DATA3),
-	PINMUX_IPSR_MSEL(IP5_11_8,	PWM3_A, SEL_PWM3_0),
-
-	PINMUX_IPSR_GPSR(IP5_15_12,	VI4_DATA5),
-	PINMUX_IPSR_MSEL(IP5_15_12,	SCK4_A, SEL_SCIF4_0),
-
-	PINMUX_IPSR_GPSR(IP5_19_16,	VI4_DATA6),
-	PINMUX_IPSR_MSEL(IP5_19_16,	IRQ2_A, SEL_IRQ_2_0),
-
-	PINMUX_IPSR_GPSR(IP5_23_20,	VI4_DATA7),
-	PINMUX_IPSR_MSEL(IP5_23_20,	TCLK2_A, SEL_TMU_0_0),
-
-	PINMUX_IPSR_GPSR(IP5_27_24,	VI4_DATA8),
-
-	PINMUX_IPSR_GPSR(IP5_31_28,	VI4_DATA9),
-	PINMUX_IPSR_MSEL(IP5_31_28,	MSIOF3_SS2_A, SEL_MSIOF3_0),
-	PINMUX_IPSR_MSEL(IP5_31_28,	IRQ1_B, SEL_IRQ_1_1),
-
-	/* IPSR6 */
-	PINMUX_IPSR_GPSR(IP6_3_0,	VI4_DATA10),
-	PINMUX_IPSR_MSEL(IP6_3_0,	RX4_A, SEL_SCIF4_0),
-
-	PINMUX_IPSR_GPSR(IP6_7_4,	VI4_DATA11),
-	PINMUX_IPSR_MSEL(IP6_7_4,	TX4_A, SEL_SCIF4_0),
-
-	PINMUX_IPSR_GPSR(IP6_11_8,	VI4_DATA12),
-	PINMUX_IPSR_MSEL(IP6_11_8,	TCLK1_A, SEL_TMU_1_0),
-
-	PINMUX_IPSR_GPSR(IP6_15_12,	VI4_DATA13),
-	PINMUX_IPSR_MSEL(IP6_15_12,	MSIOF3_SS1_A, SEL_MSIOF3_0),
-	PINMUX_IPSR_GPSR(IP6_15_12,	HCTS3_N),
-
-	PINMUX_IPSR_GPSR(IP6_19_16,	VI4_DATA14),
-	PINMUX_IPSR_MSEL(IP6_19_16,	SSI_SCK4_B, SEL_SSIF4_1),
-	PINMUX_IPSR_GPSR(IP6_19_16,	HRTS3_N),
-
-	PINMUX_IPSR_GPSR(IP6_23_20,	VI4_DATA15),
-	PINMUX_IPSR_MSEL(IP6_23_20,	SSI_SDATA4_B, SEL_SSIF4_1),
-
-	PINMUX_IPSR_GPSR(IP6_27_24,	VI4_DATA16),
-	PINMUX_IPSR_MSEL(IP6_27_24,	HRX3_A, SEL_HSCIF3_0),
-
-	PINMUX_IPSR_GPSR(IP6_31_28,	VI4_DATA17),
-	PINMUX_IPSR_MSEL(IP6_31_28,	HTX3_A, SEL_HSCIF3_0),
-
-	/* IPSR7 */
-	PINMUX_IPSR_GPSR(IP7_3_0,	VI4_DATA18),
-	PINMUX_IPSR_MSEL(IP7_3_0,	HSCK3_A, SEL_HSCIF3_0),
-
-	PINMUX_IPSR_GPSR(IP7_7_4,	VI4_DATA19),
-	PINMUX_IPSR_MSEL(IP7_7_4,	SSI_WS4_B, SEL_SSIF4_1),
-	PINMUX_IPSR_GPSR(IP7_7_4,	NFDATA15),
-
-	PINMUX_IPSR_GPSR(IP7_11_8,	VI4_DATA20),
-	PINMUX_IPSR_MSEL(IP7_11_8,	MSIOF3_SYNC_A, SEL_MSIOF3_0),
-	PINMUX_IPSR_GPSR(IP7_11_8,	NFDATA14),
-
-	PINMUX_IPSR_GPSR(IP7_15_12,	VI4_DATA21),
-	PINMUX_IPSR_MSEL(IP7_15_12,	MSIOF3_TXD_A, SEL_MSIOF3_0),
-
-	PINMUX_IPSR_GPSR(IP7_15_12,	NFDATA13),
-	PINMUX_IPSR_GPSR(IP7_19_16,	VI4_DATA22),
-	PINMUX_IPSR_MSEL(IP7_19_16,	MSIOF3_RXD_A, SEL_MSIOF3_0),
-
-	PINMUX_IPSR_GPSR(IP7_19_16,	NFDATA12),
-	PINMUX_IPSR_GPSR(IP7_23_20,	VI4_DATA23),
-	PINMUX_IPSR_MSEL(IP7_23_20,	MSIOF3_SCK_A, SEL_MSIOF3_0),
-
-	PINMUX_IPSR_GPSR(IP7_23_20,	NFDATA11),
-
-	PINMUX_IPSR_GPSR(IP7_27_24,	VI4_VSYNC_N),
-	PINMUX_IPSR_MSEL(IP7_27_24,	SCK1_B, SEL_SCIF1_1),
-	PINMUX_IPSR_GPSR(IP7_27_24,	NFDATA10),
-
-	PINMUX_IPSR_GPSR(IP7_31_28,	VI4_HSYNC_N),
-	PINMUX_IPSR_MSEL(IP7_31_28,	RX1_B, SEL_SCIF1_1),
-	PINMUX_IPSR_GPSR(IP7_31_28,	NFDATA9),
-
-	/* IPSR8 */
-	PINMUX_IPSR_GPSR(IP8_3_0,	VI4_FIELD),
-	PINMUX_IPSR_GPSR(IP8_3_0,	AUDIO_CLKB),
-	PINMUX_IPSR_MSEL(IP8_3_0,	IRQ5_A, SEL_IRQ_5_0),
-	PINMUX_IPSR_GPSR(IP8_3_0,	SCIF_CLK),
-	PINMUX_IPSR_GPSR(IP8_3_0,	NFDATA8),
-
-	PINMUX_IPSR_GPSR(IP8_7_4,	VI4_CLKENB),
-	PINMUX_IPSR_MSEL(IP8_7_4,	TX1_B, SEL_SCIF1_1),
-	PINMUX_IPSR_GPSR(IP8_7_4,	NFWP_N),
-	PINMUX_IPSR_MSEL(IP8_7_4,	DVC_MUTE_A, SEL_SCU_0),
-
-	PINMUX_IPSR_GPSR(IP8_11_8,	NFALE),
-	PINMUX_IPSR_MSEL(IP8_11_8,	SCL2_B, SEL_I2C2_1),
-	PINMUX_IPSR_MSEL(IP8_11_8,	IRQ3_B, SEL_IRQ_3_1),
-	PINMUX_IPSR_MSEL(IP8_11_8,	PWM0_C, SEL_PWM0_1),
-
-	PINMUX_IPSR_GPSR(IP8_15_12,	NFCLE),
-	PINMUX_IPSR_MSEL(IP8_15_12,	SDA2_B, SEL_I2C2_1),
-	PINMUX_IPSR_MSEL(IP8_15_12,	SCK3_A, SEL_SCIF3_0),
-	PINMUX_IPSR_MSEL(IP8_15_12,	PWM1_C, SEL_PWM1_1),
-
-	PINMUX_IPSR_GPSR(IP8_19_16,	NFCE_N),
-	PINMUX_IPSR_MSEL(IP8_19_16,	RX3_A, SEL_SCIF3_0),
-	PINMUX_IPSR_MSEL(IP8_19_16,	PWM2_C, SEL_PWM2_1),
-
-	PINMUX_IPSR_GPSR(IP8_23_20,	NFRB_N),
-	PINMUX_IPSR_MSEL(IP8_23_20,	TX3_A, SEL_SCIF3_0),
-	PINMUX_IPSR_MSEL(IP8_23_20,	PWM3_C, SEL_PWM3_1),
-
-	PINMUX_IPSR_GPSR(IP8_27_24,	NFRE_N),
-	PINMUX_IPSR_GPSR(IP8_27_24,	MMC_CMD),
-
-	PINMUX_IPSR_GPSR(IP8_31_28,	NFWE_N),
-	PINMUX_IPSR_GPSR(IP8_31_28,	MMC_CLK),
-
-	/* IPSR9 */
-	PINMUX_IPSR_GPSR(IP9_3_0,	NFDATA0),
-	PINMUX_IPSR_GPSR(IP9_3_0,	MMC_D0),
-
-	PINMUX_IPSR_GPSR(IP9_7_4,	NFDATA1),
-	PINMUX_IPSR_GPSR(IP9_7_4,	MMC_D1),
-
-	PINMUX_IPSR_GPSR(IP9_11_8,	NFDATA2),
-	PINMUX_IPSR_GPSR(IP9_11_8,	MMC_D2),
-
-	PINMUX_IPSR_GPSR(IP9_15_12,	NFDATA3),
-	PINMUX_IPSR_GPSR(IP9_15_12,	MMC_D3),
-
-	PINMUX_IPSR_GPSR(IP9_19_16,	NFDATA4),
-	PINMUX_IPSR_GPSR(IP9_19_16,	MMC_D4),
-
-	PINMUX_IPSR_GPSR(IP9_23_20,	NFDATA5),
-	PINMUX_IPSR_GPSR(IP9_23_20,	MMC_D5),
-
-	PINMUX_IPSR_GPSR(IP9_27_24,	NFDATA6),
-	PINMUX_IPSR_GPSR(IP9_27_24,	MMC_D6),
-
-	PINMUX_IPSR_GPSR(IP9_31_28,	NFDATA7),
-	PINMUX_IPSR_GPSR(IP9_31_28,	MMC_D7),
-
-	/* IPSR10 */
-	PINMUX_IPSR_GPSR(IP10_3_0,	AUDIO_CLKA),
-	PINMUX_IPSR_MSEL(IP10_3_0,	DVC_MUTE_B, SEL_SCU_1),
-
-	PINMUX_IPSR_GPSR(IP10_7_4,	SSI_SCK34),
-	PINMUX_IPSR_MSEL(IP10_7_4,	FSO_CFE_0_N_A, SEL_RFSO_0),
-
-	PINMUX_IPSR_GPSR(IP10_11_8,	SSI_SDATA3),
-	PINMUX_IPSR_MSEL(IP10_11_8,	FSO_CFE_1_N_A, SEL_RFSO_0),
-
-	PINMUX_IPSR_GPSR(IP10_15_12,	SSI_WS34),
-	PINMUX_IPSR_MSEL(IP10_15_12,	FSO_TOE_N_A, SEL_RFSO_0),
-
-	PINMUX_IPSR_MSEL(IP10_19_16,	SSI_SCK4_A, SEL_SSIF4_0),
-	PINMUX_IPSR_GPSR(IP10_19_16,	HSCK0),
-	PINMUX_IPSR_GPSR(IP10_19_16,	AUDIO_CLKOUT),
-	PINMUX_IPSR_MSEL(IP10_19_16,	CAN0_RX_B, SEL_CAN0_1),
-	PINMUX_IPSR_MSEL(IP10_19_16,	IRQ4_B, SEL_IRQ_4_1),
-
-	PINMUX_IPSR_MSEL(IP10_23_20,	SSI_SDATA4_A, SEL_SSIF4_0),
-	PINMUX_IPSR_GPSR(IP10_23_20,	HTX0),
-	PINMUX_IPSR_MSEL(IP10_23_20,	SCL2_A, SEL_I2C2_0),
-	PINMUX_IPSR_MSEL(IP10_23_20,	CAN1_RX_B, SEL_CAN1_1),
-
-	PINMUX_IPSR_MSEL(IP10_27_24,	SSI_WS4_A, SEL_SSIF4_0),
-	PINMUX_IPSR_GPSR(IP10_27_24,	HRX0),
-	PINMUX_IPSR_MSEL(IP10_27_24,	SDA2_A, SEL_I2C2_0),
-	PINMUX_IPSR_MSEL(IP10_27_24,	CAN1_TX_B, SEL_CAN1_1),
-
-	PINMUX_IPSR_GPSR(IP10_31_28,	SCL1),
-	PINMUX_IPSR_GPSR(IP10_31_28,	CTS1_N),
-
-	/* IPSR11 */
-	PINMUX_IPSR_GPSR(IP11_3_0,	SDA1),
-	PINMUX_IPSR_GPSR(IP11_3_0,	RTS1_N),
-
-	PINMUX_IPSR_GPSR(IP11_7_4,	MSIOF1_SCK),
-	PINMUX_IPSR_MSEL(IP11_7_4,	AVB0_AVTP_PPS_B, SEL_ETHERAVB_1),
-
-	PINMUX_IPSR_GPSR(IP11_11_8,	MSIOF1_TXD),
-	PINMUX_IPSR_MSEL(IP11_11_8,	AVB0_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
-
-	PINMUX_IPSR_GPSR(IP11_15_12,	MSIOF1_RXD),
-	PINMUX_IPSR_MSEL(IP11_15_12,	AVB0_AVTP_MATCH_B, SEL_ETHERAVB_1),
-
-	PINMUX_IPSR_MSEL(IP11_19_16,	SCK0_A, SEL_SCIF0_0),
-	PINMUX_IPSR_GPSR(IP11_19_16,	MSIOF1_SYNC),
-	PINMUX_IPSR_MSEL(IP11_19_16,	FSO_CFE_0_N_B, SEL_RFSO_1),
-
-	PINMUX_IPSR_MSEL(IP11_23_20,	RX0_A, SEL_SCIF0_0),
-	PINMUX_IPSR_GPSR(IP11_23_20,	MSIOF0_SS1),
-	PINMUX_IPSR_MSEL(IP11_23_20,	FSO_CFE_1_N_B, SEL_RFSO_1),
-
-	PINMUX_IPSR_MSEL(IP11_27_24,	TX0_A, SEL_SCIF0_0),
-	PINMUX_IPSR_GPSR(IP11_27_24,	MSIOF0_SS2),
-	PINMUX_IPSR_MSEL(IP11_27_24,	FSO_TOE_N_B, SEL_RFSO_1),
-
-	PINMUX_IPSR_MSEL(IP11_31_28,	SCK1_A, SEL_SCIF1_0),
-	PINMUX_IPSR_GPSR(IP11_31_28,	MSIOF1_SS2),
-	PINMUX_IPSR_GPSR(IP11_31_28,	TPU0TO2_B),
-	PINMUX_IPSR_MSEL(IP11_31_28,	CAN0_TX_B, SEL_CAN0_1),
-	PINMUX_IPSR_GPSR(IP11_31_28,	AUDIO_CLKOUT1),
-
-	/* IPSR12 */
-	PINMUX_IPSR_MSEL(IP12_3_0,	RX1_A, SEL_SCIF1_0),
-	PINMUX_IPSR_GPSR(IP12_3_0,	CTS0_N),
-	PINMUX_IPSR_GPSR(IP12_3_0,	TPU0TO0_B),
-
-	PINMUX_IPSR_MSEL(IP12_7_4,	TX1_A, SEL_SCIF1_0),
-	PINMUX_IPSR_GPSR(IP12_7_4,	RTS0_N),
-	PINMUX_IPSR_GPSR(IP12_7_4,	TPU0TO1_B),
-
-	PINMUX_IPSR_GPSR(IP12_11_8,	SCK2),
-	PINMUX_IPSR_GPSR(IP12_11_8,	MSIOF1_SS1),
-	PINMUX_IPSR_GPSR(IP12_11_8,	TPU0TO3_B),
-
-	PINMUX_IPSR_GPSR(IP12_15_12,	TPU0TO0_A),
-	PINMUX_IPSR_MSEL(IP12_15_12,	AVB0_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
-	PINMUX_IPSR_GPSR(IP12_15_12,	HCTS0_N),
-
-	PINMUX_IPSR_GPSR(IP12_19_16,	TPU0TO1_A),
-	PINMUX_IPSR_MSEL(IP12_19_16,	AVB0_AVTP_MATCH_A, SEL_ETHERAVB_0),
-	PINMUX_IPSR_GPSR(IP12_19_16,	HRTS0_N),
-
-	PINMUX_IPSR_GPSR(IP12_23_20,	CAN_CLK),
-	PINMUX_IPSR_MSEL(IP12_23_20,	AVB0_AVTP_PPS_A, SEL_ETHERAVB_0),
-	PINMUX_IPSR_MSEL(IP12_23_20,	SCK0_B, SEL_SCIF0_1),
-	PINMUX_IPSR_MSEL(IP12_23_20,	IRQ5_B, SEL_IRQ_5_1),
-
-	PINMUX_IPSR_MSEL(IP12_27_24,	CAN0_RX_A, SEL_CAN0_0),
-	PINMUX_IPSR_GPSR(IP12_27_24,	CANFD0_RX),
-	PINMUX_IPSR_MSEL(IP12_27_24,	RX0_B, SEL_SCIF0_1),
-
-	PINMUX_IPSR_MSEL(IP12_31_28,	CAN0_TX_A, SEL_CAN0_0),
-	PINMUX_IPSR_GPSR(IP12_31_28,	CANFD0_TX),
-	PINMUX_IPSR_MSEL(IP12_31_28,	TX0_B, SEL_SCIF0_1),
-
-	/* IPSR13 */
-	PINMUX_IPSR_MSEL(IP13_3_0,	CAN1_RX_A, SEL_CAN1_0),
-	PINMUX_IPSR_GPSR(IP13_3_0,	CANFD1_RX),
-	PINMUX_IPSR_GPSR(IP13_3_0,	TPU0TO2_A),
-
-	PINMUX_IPSR_MSEL(IP13_7_4,	CAN1_TX_A, SEL_CAN1_0),
-	PINMUX_IPSR_GPSR(IP13_7_4,	CANFD1_TX),
-	PINMUX_IPSR_GPSR(IP13_7_4,	TPU0TO3_A),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	PINMUX_GPIO_GP_ALL(),
-};
-
-/* - AUDIO CLOCK ------------------------------------------------------------- */
-static const unsigned int audio_clk_a_pins[] = {
-	/* CLK A */
-	RCAR_GP_PIN(4, 1),
-};
-static const unsigned int audio_clk_a_mux[] = {
-	AUDIO_CLKA_MARK,
-};
-static const unsigned int audio_clk_b_pins[] = {
-	/* CLK B */
-	RCAR_GP_PIN(2, 27),
-};
-static const unsigned int audio_clk_b_mux[] = {
-	AUDIO_CLKB_MARK,
-};
-static const unsigned int audio_clkout_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(4, 5),
-};
-static const unsigned int audio_clkout_mux[] = {
-	AUDIO_CLKOUT_MARK,
-};
-static const unsigned int audio_clkout1_pins[] = {
-	/* CLKOUT1 */
-	RCAR_GP_PIN(4, 22),
-};
-static const unsigned int audio_clkout1_mux[] = {
-	AUDIO_CLKOUT1_MARK,
-};
-
-/* - EtherAVB --------------------------------------------------------------- */
-static const unsigned int avb0_link_pins[] = {
-	/* AVB0_LINK */
-	RCAR_GP_PIN(5, 20),
-};
-static const unsigned int avb0_link_mux[] = {
-	AVB0_LINK_MARK,
-};
-static const unsigned int avb0_magic_pins[] = {
-	/* AVB0_MAGIC */
-	RCAR_GP_PIN(5, 18),
-};
-static const unsigned int avb0_magic_mux[] = {
-	AVB0_MAGIC_MARK,
-};
-static const unsigned int avb0_phy_int_pins[] = {
-	/* AVB0_PHY_INT */
-	RCAR_GP_PIN(5, 19),
-};
-static const unsigned int avb0_phy_int_mux[] = {
-	AVB0_PHY_INT_MARK,
-};
-static const unsigned int avb0_mdio_pins[] = {
-	/* AVB0_MDC, AVB0_MDIO */
-	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 16),
-};
-static const unsigned int avb0_mdio_mux[] = {
-	AVB0_MDC_MARK, AVB0_MDIO_MARK,
-};
-static const unsigned int avb0_mii_pins[] = {
-	/*
-	 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0,
-	 * AVB0_TD1, AVB0_TD2, AVB0_TD3,
-	 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0,
-	 * AVB0_RD1, AVB0_RD2, AVB0_RD3,
-	 * AVB0_TXCREFCLK
-	 */
-	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
-	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
-	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
-	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
-	RCAR_GP_PIN(5, 15),
-};
-static const unsigned int avb0_mii_mux[] = {
-	AVB0_TX_CTL_MARK, AVB0_TXC_MARK, AVB0_TD0_MARK,
-	AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
-	AVB0_RX_CTL_MARK, AVB0_RXC_MARK, AVB0_RD0_MARK,
-	AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
-	AVB0_TXCREFCLK_MARK,
-};
-static const unsigned int avb0_avtp_pps_a_pins[] = {
-	/* AVB0_AVTP_PPS_A */
-	RCAR_GP_PIN(5, 2),
-};
-static const unsigned int avb0_avtp_pps_a_mux[] = {
-	AVB0_AVTP_PPS_A_MARK,
-};
-static const unsigned int avb0_avtp_match_a_pins[] = {
-	/* AVB0_AVTP_MATCH_A */
-	RCAR_GP_PIN(5, 1),
-};
-static const unsigned int avb0_avtp_match_a_mux[] = {
-	AVB0_AVTP_MATCH_A_MARK,
-};
-static const unsigned int avb0_avtp_capture_a_pins[] = {
-	/* AVB0_AVTP_CAPTURE_A */
-	RCAR_GP_PIN(5, 0),
-};
-static const unsigned int avb0_avtp_capture_a_mux[] = {
-	AVB0_AVTP_CAPTURE_A_MARK,
-};
-static const unsigned int avb0_avtp_pps_b_pins[] = {
-	/* AVB0_AVTP_PPS_B */
-	RCAR_GP_PIN(4, 16),
-};
-static const unsigned int avb0_avtp_pps_b_mux[] = {
-	AVB0_AVTP_PPS_B_MARK,
-};
-static const unsigned int avb0_avtp_match_b_pins[] = {
-	/*  AVB0_AVTP_MATCH_B */
-	RCAR_GP_PIN(4, 18),
-};
-static const unsigned int avb0_avtp_match_b_mux[] = {
-	AVB0_AVTP_MATCH_B_MARK,
-};
-static const unsigned int avb0_avtp_capture_b_pins[] = {
-	/* AVB0_AVTP_CAPTURE_B */
-	RCAR_GP_PIN(4, 17),
-};
-static const unsigned int avb0_avtp_capture_b_mux[] = {
-	AVB0_AVTP_CAPTURE_B_MARK,
-};
-
-/* - CAN ------------------------------------------------------------------ */
-static const unsigned int can0_data_a_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
-};
-static const unsigned int can0_data_a_mux[] = {
-	CAN0_TX_A_MARK, CAN0_RX_A_MARK,
-};
-static const unsigned int can0_data_b_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 5),
-};
-static const unsigned int can0_data_b_mux[] = {
-	CAN0_TX_B_MARK, CAN0_RX_B_MARK,
-};
-static const unsigned int can1_data_a_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
-};
-static const unsigned int can1_data_a_mux[] = {
-	CAN1_TX_A_MARK, CAN1_RX_A_MARK,
-};
-static const unsigned int can1_data_b_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6),
-};
-static const unsigned int can1_data_b_mux[] = {
-	CAN1_TX_B_MARK, CAN1_RX_B_MARK,
-};
-
-/* - CAN Clock -------------------------------------------------------------- */
-static const unsigned int can_clk_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(5, 2),
-};
-static const unsigned int can_clk_mux[] = {
-	CAN_CLK_MARK,
-};
-
-/* - CAN FD ----------------------------------------------------------------- */
-static const unsigned int canfd0_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
-};
-static const unsigned int canfd0_data_mux[] = {
-	CANFD0_TX_MARK, CANFD0_RX_MARK,
-};
-static const unsigned int canfd1_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
-};
-static const unsigned int canfd1_data_mux[] = {
-	CANFD1_TX_MARK, CANFD1_RX_MARK,
-};
-
-/* - DU --------------------------------------------------------------------- */
-static const unsigned int du_rgb666_pins[] = {
-	/* R[7:2], G[7:2], B[7:2] */
-	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
-	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
-	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
-	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
-	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
-};
-static const unsigned int du_rgb666_mux[] = {
-	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
-	DU_DR3_MARK, DU_DR2_MARK,
-	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
-	DU_DG3_MARK, DU_DG2_MARK,
-	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
-	DU_DB3_MARK, DU_DB2_MARK,
-};
-static const unsigned int du_rgb888_pins[] = {
-	/* R[7:0], G[7:0], B[7:0] */
-	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
-	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
-	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
-	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
-	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
-	RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),
-	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
-	RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
-};
-static const unsigned int du_rgb888_mux[] = {
-	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
-	DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
-	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
-	DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
-	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
-	DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
-};
-static const unsigned int du_clk_in_1_pins[] = {
-	/* CLKIN */
-	RCAR_GP_PIN(1, 28),
-};
-static const unsigned int du_clk_in_1_mux[] = {
-	DU_DOTCLKIN1_MARK
-};
-static const unsigned int du_clk_out_0_pins[] = {
-	/* CLKOUT */
-	RCAR_GP_PIN(1, 24),
-};
-static const unsigned int du_clk_out_0_mux[] = {
-	DU_DOTCLKOUT0_MARK
-};
-static const unsigned int du_sync_pins[] = {
-	/* VSYNC, HSYNC */
-	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
-};
-static const unsigned int du_sync_mux[] = {
-	DU_VSYNC_MARK, DU_HSYNC_MARK
-};
-static const unsigned int du_disp_cde_pins[] = {
-	/* DISP_CDE */
-	RCAR_GP_PIN(1, 28),
-};
-static const unsigned int du_disp_cde_mux[] = {
-	DU_DISP_CDE_MARK,
-};
-static const unsigned int du_cde_pins[] = {
-	/* CDE */
-	RCAR_GP_PIN(1, 29),
-};
-static const unsigned int du_cde_mux[] = {
-	DU_CDE_MARK,
-};
-static const unsigned int du_disp_pins[] = {
-	/* DISP */
-	RCAR_GP_PIN(1, 27),
-};
-static const unsigned int du_disp_mux[] = {
-	DU_DISP_MARK,
-};
-
-/* - I2C -------------------------------------------------------------------- */
-static const unsigned int i2c0_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
-};
-static const unsigned int i2c0_mux[] = {
-	SCL0_MARK, SDA0_MARK,
-};
-static const unsigned int i2c1_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
-};
-static const unsigned int i2c1_mux[] = {
-	SCL1_MARK, SDA1_MARK,
-};
-static const unsigned int i2c2_a_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
-};
-static const unsigned int i2c2_a_mux[] = {
-	SCL2_A_MARK, SDA2_A_MARK,
-};
-static const unsigned int i2c2_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 30),
-};
-static const unsigned int i2c2_b_mux[] = {
-	SCL2_B_MARK, SDA2_B_MARK,
-};
-static const unsigned int i2c3_a_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-};
-static const unsigned int i2c3_a_mux[] = {
-	SCL3_A_MARK, SDA3_A_MARK,
-};
-static const unsigned int i2c3_b_pins[] = {
-	/* SCL, SDA */
-	RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
-};
-static const unsigned int i2c3_b_mux[] = {
-	SCL3_B_MARK, SDA3_B_MARK,
-};
-
-/* - MMC ------------------------------------------------------------------- */
-static const unsigned int mmc_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 2),
-};
-static const unsigned int mmc_data1_mux[] = {
-	MMC_D0_MARK,
-};
-static const unsigned int mmc_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
-	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
-};
-static const unsigned int mmc_data4_mux[] = {
-	MMC_D0_MARK, MMC_D1_MARK,
-	MMC_D2_MARK, MMC_D3_MARK,
-};
-static const unsigned int mmc_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
-	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
-	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-};
-static const unsigned int mmc_data8_mux[] = {
-	MMC_D0_MARK, MMC_D1_MARK,
-	MMC_D2_MARK, MMC_D3_MARK,
-	MMC_D4_MARK, MMC_D5_MARK,
-	MMC_D6_MARK, MMC_D7_MARK,
-};
-static const unsigned int mmc_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
-};
-static const unsigned int mmc_ctrl_mux[] = {
-	MMC_CLK_MARK, MMC_CMD_MARK,
-};
-
-/* - MSIOF0 ----------------------------------------------------------------- */
-static const unsigned int msiof0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 12),
-};
-
-static const unsigned int msiof0_clk_mux[] = {
-	MSIOF0_SCK_MARK,
-};
-
-static const unsigned int msiof0_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(4, 13),
-};
-
-static const unsigned int msiof0_sync_mux[] = {
-	MSIOF0_SYNC_MARK,
-};
-
-static const unsigned int msiof0_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(4, 20),
-};
-
-static const unsigned int msiof0_ss1_mux[] = {
-	MSIOF0_SS1_MARK,
-};
-
-static const unsigned int msiof0_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(4, 21),
-};
-
-static const unsigned int msiof0_ss2_mux[] = {
-	MSIOF0_SS2_MARK,
-};
-
-static const unsigned int msiof0_txd_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(4, 14),
-};
-
-static const unsigned int msiof0_txd_mux[] = {
-	MSIOF0_TXD_MARK,
-};
-
-static const unsigned int msiof0_rxd_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(4, 15),
-};
-
-static const unsigned int msiof0_rxd_mux[] = {
-	MSIOF0_RXD_MARK,
-};
-
-/* - MSIOF1 ----------------------------------------------------------------- */
-static const unsigned int msiof1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 16),
-};
-
-static const unsigned int msiof1_clk_mux[] = {
-	MSIOF1_SCK_MARK,
-};
-
-static const unsigned int msiof1_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(4, 19),
-};
-
-static const unsigned int msiof1_sync_mux[] = {
-	MSIOF1_SYNC_MARK,
-};
-
-static const unsigned int msiof1_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(4, 25),
-};
-
-static const unsigned int msiof1_ss1_mux[] = {
-	MSIOF1_SS1_MARK,
-};
-
-static const unsigned int msiof1_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(4, 22),
-};
-
-static const unsigned int msiof1_ss2_mux[] = {
-	MSIOF1_SS2_MARK,
-};
-
-static const unsigned int msiof1_txd_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(4, 17),
-};
-
-static const unsigned int msiof1_txd_mux[] = {
-	MSIOF1_TXD_MARK,
-};
-
-static const unsigned int msiof1_rxd_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(4, 18),
-};
-
-static const unsigned int msiof1_rxd_mux[] = {
-	MSIOF1_RXD_MARK,
-};
-
-/* - MSIOF2 ----------------------------------------------------------------- */
-static const unsigned int msiof2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 3),
-};
-
-static const unsigned int msiof2_clk_mux[] = {
-	MSIOF2_SCK_MARK,
-};
-
-static const unsigned int msiof2_sync_a_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 6),
-};
-
-static const unsigned int msiof2_sync_a_mux[] = {
-	MSIOF2_SYNC_A_MARK,
-};
-
-static const unsigned int msiof2_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(0, 2),
-};
-
-static const unsigned int msiof2_sync_b_mux[] = {
-	MSIOF2_SYNC_B_MARK,
-};
-
-static const unsigned int msiof2_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 7),
-};
-
-static const unsigned int msiof2_ss1_mux[] = {
-	MSIOF2_SS1_MARK,
-};
-
-static const unsigned int msiof2_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 8),
-};
-
-static const unsigned int msiof2_ss2_mux[] = {
-	MSIOF2_SS2_MARK,
-};
-
-static const unsigned int msiof2_txd_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 4),
-};
-
-static const unsigned int msiof2_txd_mux[] = {
-	MSIOF2_TXD_MARK,
-};
-
-static const unsigned int msiof2_rxd_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 5),
-};
-
-static const unsigned int msiof2_rxd_mux[] = {
-	MSIOF2_RXD_MARK,
-};
-
-/* - MSIOF3 ----------------------------------------------------------------- */
-static const unsigned int msiof3_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 24),
-};
-
-static const unsigned int msiof3_clk_a_mux[] = {
-	MSIOF3_SCK_A_MARK,
-};
-
-static const unsigned int msiof3_sync_a_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(2, 21),
-};
-
-static const unsigned int msiof3_sync_a_mux[] = {
-	MSIOF3_SYNC_A_MARK,
-};
-
-static const unsigned int msiof3_ss1_a_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(2, 14),
-};
-
-static const unsigned int msiof3_ss1_a_mux[] = {
-	MSIOF3_SS1_A_MARK,
-};
-
-static const unsigned int msiof3_ss2_a_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(2, 10),
-};
-
-static const unsigned int msiof3_ss2_a_mux[] = {
-	MSIOF3_SS2_A_MARK,
-};
-
-static const unsigned int msiof3_txd_a_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(2, 22),
-};
-
-static const unsigned int msiof3_txd_a_mux[] = {
-	MSIOF3_TXD_A_MARK,
-};
-
-static const unsigned int msiof3_rxd_a_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(2, 23),
-};
-
-static const unsigned int msiof3_rxd_a_mux[] = {
-	MSIOF3_RXD_A_MARK,
-};
-
-static const unsigned int msiof3_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 8),
-};
-
-static const unsigned int msiof3_clk_b_mux[] = {
-	MSIOF3_SCK_B_MARK,
-};
-
-static const unsigned int msiof3_sync_b_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(1, 9),
-};
-
-static const unsigned int msiof3_sync_b_mux[] = {
-	MSIOF3_SYNC_B_MARK,
-};
-
-static const unsigned int msiof3_ss1_b_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(1, 6),
-};
-
-static const unsigned int msiof3_ss1_b_mux[] = {
-	MSIOF3_SS1_B_MARK,
-};
-
-static const unsigned int msiof3_ss2_b_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(1, 7),
-};
-
-static const unsigned int msiof3_ss2_b_mux[] = {
-	MSIOF3_SS2_B_MARK,
-};
-
-static const unsigned int msiof3_txd_b_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(1, 0),
-};
-
-static const unsigned int msiof3_txd_b_mux[] = {
-	MSIOF3_TXD_B_MARK,
-};
-
-static const unsigned int msiof3_rxd_b_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(1, 1),
-};
-
-static const unsigned int msiof3_rxd_b_mux[] = {
-	MSIOF3_RXD_B_MARK,
-};
-
-/* - PWM0 ------------------------------------------------------------------ */
-static const unsigned int pwm0_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 1),
-};
-
-static const unsigned int pwm0_a_mux[] = {
-	PWM0_A_MARK,
-};
-
-static const unsigned int pwm0_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 18),
-};
-
-static const unsigned int pwm0_b_mux[] = {
-	PWM0_B_MARK,
-};
-
-static const unsigned int pwm0_c_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 29),
-};
-
-static const unsigned int pwm0_c_mux[] = {
-	PWM0_C_MARK,
-};
-
-/* - PWM1 ------------------------------------------------------------------ */
-static const unsigned int pwm1_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 2),
-};
-
-static const unsigned int pwm1_a_mux[] = {
-	PWM1_A_MARK,
-};
-
-static const unsigned int pwm1_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 19),
-};
-
-static const unsigned int pwm1_b_mux[] = {
-	PWM1_B_MARK,
-};
-
-static const unsigned int pwm1_c_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 30),
-};
-
-static const unsigned int pwm1_c_mux[] = {
-	PWM1_C_MARK,
-};
-
-/* - PWM2 ------------------------------------------------------------------ */
-static const unsigned int pwm2_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 3),
-};
-
-static const unsigned int pwm2_a_mux[] = {
-	PWM2_A_MARK,
-};
-
-static const unsigned int pwm2_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 22),
-};
-
-static const unsigned int pwm2_b_mux[] = {
-	PWM2_B_MARK,
-};
-
-static const unsigned int pwm2_c_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 31),
-};
-
-static const unsigned int pwm2_c_mux[] = {
-	PWM2_C_MARK,
-};
-
-/* - PWM3 ------------------------------------------------------------------ */
-static const unsigned int pwm3_a_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(2, 4),
-};
-
-static const unsigned int pwm3_a_mux[] = {
-	PWM3_A_MARK,
-};
-
-static const unsigned int pwm3_b_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(1, 27),
-};
-
-static const unsigned int pwm3_b_mux[] = {
-	PWM3_B_MARK,
-};
-
-static const unsigned int pwm3_c_pins[] = {
-	/* PWM */
-	RCAR_GP_PIN(4, 0),
-};
-
-static const unsigned int pwm3_c_mux[] = {
-	PWM3_C_MARK,
-};
-
-/* - SCIF0 ------------------------------------------------------------------ */
-static const unsigned int scif0_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
-};
-static const unsigned int scif0_data_a_mux[] = {
-	RX0_A_MARK, TX0_A_MARK,
-};
-static const unsigned int scif0_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 19),
-};
-static const unsigned int scif0_clk_a_mux[] = {
-	SCK0_A_MARK,
-};
-static const unsigned int scif0_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 28),
-};
-static const unsigned int scif0_data_b_mux[] = {
-	RX0_B_MARK, TX0_B_MARK,
-};
-static const unsigned int scif0_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(5, 2),
-};
-static const unsigned int scif0_clk_b_mux[] = {
-	SCK0_B_MARK,
-};
-static const unsigned int scif0_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
-};
-static const unsigned int scif0_ctrl_mux[] = {
-	RTS0_N_MARK, CTS0_N_MARK,
-};
-/* - SCIF1 ------------------------------------------------------------------ */
-static const unsigned int scif1_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
-};
-static const unsigned int scif1_data_a_mux[] = {
-	RX1_A_MARK, TX1_A_MARK,
-};
-static const unsigned int scif1_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 22),
-};
-static const unsigned int scif1_clk_a_mux[] = {
-	SCK1_A_MARK,
-};
-static const unsigned int scif1_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 28),
-};
-static const unsigned int scif1_data_b_mux[] = {
-	RX1_B_MARK, TX1_B_MARK,
-};
-static const unsigned int scif1_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 25),
-};
-static const unsigned int scif1_clk_b_mux[] = {
-	SCK1_B_MARK,
-};
-static const unsigned int scif1_ctrl_pins[] = {
-	/* RTS, CTS */
-	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
-};
-static const unsigned int scif1_ctrl_mux[] = {
-	RTS1_N_MARK, CTS1_N_MARK,
-};
-
-/* - SCIF2 ------------------------------------------------------------------ */
-static const unsigned int scif2_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
-};
-static const unsigned int scif2_data_mux[] = {
-	RX2_MARK, TX2_MARK,
-};
-static const unsigned int scif2_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 25),
-};
-static const unsigned int scif2_clk_mux[] = {
-	SCK2_MARK,
-};
-/* - SCIF3 ------------------------------------------------------------------ */
-static const unsigned int scif3_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 31), RCAR_GP_PIN(4, 00),
-};
-static const unsigned int scif3_data_a_mux[] = {
-	RX3_A_MARK, TX3_A_MARK,
-};
-static const unsigned int scif3_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 30),
-};
-static const unsigned int scif3_clk_a_mux[] = {
-	SCK3_A_MARK,
-};
-static const unsigned int scif3_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31),
-};
-static const unsigned int scif3_data_b_mux[] = {
-	RX3_B_MARK, TX3_B_MARK,
-};
-static const unsigned int scif3_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 29),
-};
-static const unsigned int scif3_clk_b_mux[] = {
-	SCK3_B_MARK,
-};
-/* - SCIF4 ------------------------------------------------------------------ */
-static const unsigned int scif4_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
-};
-static const unsigned int scif4_data_a_mux[] = {
-	RX4_A_MARK, TX4_A_MARK,
-};
-static const unsigned int scif4_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 6),
-};
-static const unsigned int scif4_clk_a_mux[] = {
-	SCK4_A_MARK,
-};
-static const unsigned int scif4_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
-};
-static const unsigned int scif4_data_b_mux[] = {
-	RX4_B_MARK, TX4_B_MARK,
-};
-static const unsigned int scif4_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 15),
-};
-static const unsigned int scif4_clk_b_mux[] = {
-	SCK4_B_MARK,
-};
-/* - SCIF5 ------------------------------------------------------------------ */
-static const unsigned int scif5_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
-};
-static const unsigned int scif5_data_a_mux[] = {
-	RX5_A_MARK, TX5_A_MARK,
-};
-static const unsigned int scif5_clk_a_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(0, 6),
-};
-static const unsigned int scif5_clk_a_mux[] = {
-	SCK5_A_MARK,
-};
-static const unsigned int scif5_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-};
-static const unsigned int scif5_data_b_mux[] = {
-	RX5_B_MARK, TX5_B_MARK,
-};
-static const unsigned int scif5_clk_b_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(1, 3),
-};
-static const unsigned int scif5_clk_b_mux[] = {
-	SCK5_B_MARK,
-};
-/* - SCIF Clock ------------------------------------------------------------- */
-static const unsigned int scif_clk_pins[] = {
-	/* SCIF_CLK */
-	RCAR_GP_PIN(2, 27),
-};
-static const unsigned int scif_clk_mux[] = {
-	SCIF_CLK_MARK,
-};
-
-/* - SSI ---------------------------------------------------------------*/
-static const unsigned int ssi3_data_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(4, 3),
-};
-static const unsigned int ssi3_data_mux[] = {
-	SSI_SDATA3_MARK,
-};
-static const unsigned int ssi34_ctrl_pins[] = {
-	/* SCK,  WS */
-	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 4),
-};
-static const unsigned int ssi34_ctrl_mux[] = {
-	SSI_SCK34_MARK, SSI_WS34_MARK,
-};
-static const unsigned int ssi4_ctrl_a_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
-};
-static const unsigned int ssi4_ctrl_a_mux[] = {
-	SSI_SCK4_A_MARK, SSI_WS4_A_MARK,
-};
-static const unsigned int ssi4_data_a_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(4, 6),
-};
-static const unsigned int ssi4_data_a_mux[] = {
-	SSI_SDATA4_A_MARK,
-};
-static const unsigned int ssi4_ctrl_b_pins[] = {
-	/* SCK, WS */
-	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 20),
-};
-static const unsigned int ssi4_ctrl_b_mux[] = {
-	SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
-};
-static const unsigned int ssi4_data_b_pins[] = {
-	/* SDATA */
-	RCAR_GP_PIN(2, 16),
-};
-static const unsigned int ssi4_data_b_mux[] = {
-	SSI_SDATA4_B_MARK,
-};
-
-/* - USB0 ------------------------------------------------------------------- */
-static const unsigned int usb0_pins[] = {
-	/* PWEN, OVC */
-	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-};
-static const unsigned int usb0_mux[] = {
-	USB0_PWEN_MARK, USB0_OVC_MARK,
-};
-
-/* - VIN4 ------------------------------------------------------------------- */
-static const unsigned int vin4_data18_pins[] = {
-	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
-	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
-	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
-	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
-	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
-	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
-	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
-	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
-	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
-};
-static const unsigned int vin4_data18_mux[] = {
-	VI4_DATA2_MARK, VI4_DATA3_MARK,
-	VI4_DATA4_MARK, VI4_DATA5_MARK,
-	VI4_DATA6_MARK, VI4_DATA7_MARK,
-	VI4_DATA10_MARK, VI4_DATA11_MARK,
-	VI4_DATA12_MARK, VI4_DATA13_MARK,
-	VI4_DATA14_MARK, VI4_DATA15_MARK,
-	VI4_DATA18_MARK, VI4_DATA19_MARK,
-	VI4_DATA20_MARK, VI4_DATA21_MARK,
-	VI4_DATA22_MARK, VI4_DATA23_MARK,
-};
-static const union vin_data vin4_data_pins = {
-	.data24 = {
-		RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
-		RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
-		RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
-		RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
-		RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
-		RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
-		RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
-		RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
-		RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
-		RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
-		RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
-		RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
-	},
-};
-static const union vin_data vin4_data_mux = {
-	.data24 = {
-		VI4_DATA0_MARK, VI4_DATA1_MARK,
-		VI4_DATA2_MARK, VI4_DATA3_MARK,
-		VI4_DATA4_MARK, VI4_DATA5_MARK,
-		VI4_DATA6_MARK, VI4_DATA7_MARK,
-		VI4_DATA8_MARK,  VI4_DATA9_MARK,
-		VI4_DATA10_MARK, VI4_DATA11_MARK,
-		VI4_DATA12_MARK, VI4_DATA13_MARK,
-		VI4_DATA14_MARK, VI4_DATA15_MARK,
-		VI4_DATA16_MARK, VI4_DATA17_MARK,
-		VI4_DATA18_MARK, VI4_DATA19_MARK,
-		VI4_DATA20_MARK, VI4_DATA21_MARK,
-		VI4_DATA22_MARK, VI4_DATA23_MARK,
-	},
-};
-static const unsigned int vin4_sync_pins[] = {
-	/* HSYNC#, VSYNC# */
-	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
-};
-static const unsigned int vin4_sync_mux[] = {
-	VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
-};
-static const unsigned int vin4_field_pins[] = {
-	/* FIELD */
-	RCAR_GP_PIN(2, 27),
-};
-static const unsigned int vin4_field_mux[] = {
-	VI4_FIELD_MARK,
-};
-static const unsigned int vin4_clkenb_pins[] = {
-	/* CLKENB */
-	RCAR_GP_PIN(2, 28),
-};
-static const unsigned int vin4_clkenb_mux[] = {
-	VI4_CLKENB_MARK,
-};
-static const unsigned int vin4_clk_pins[] = {
-	/* CLK */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int vin4_clk_mux[] = {
-	VI4_CLK_MARK,
-};
-
-static const struct sh_pfc_pin_group pinmux_groups[] = {
-	SH_PFC_PIN_GROUP(audio_clk_a),
-	SH_PFC_PIN_GROUP(audio_clk_b),
-	SH_PFC_PIN_GROUP(audio_clkout),
-	SH_PFC_PIN_GROUP(audio_clkout1),
-	SH_PFC_PIN_GROUP(avb0_link),
-	SH_PFC_PIN_GROUP(avb0_magic),
-	SH_PFC_PIN_GROUP(avb0_phy_int),
-	SH_PFC_PIN_GROUP_ALIAS(avb0_mdc, avb0_mdio),	/* Deprecated */
-	SH_PFC_PIN_GROUP(avb0_mdio),
-	SH_PFC_PIN_GROUP(avb0_mii),
-	SH_PFC_PIN_GROUP(avb0_avtp_pps_a),
-	SH_PFC_PIN_GROUP(avb0_avtp_match_a),
-	SH_PFC_PIN_GROUP(avb0_avtp_capture_a),
-	SH_PFC_PIN_GROUP(avb0_avtp_pps_b),
-	SH_PFC_PIN_GROUP(avb0_avtp_match_b),
-	SH_PFC_PIN_GROUP(avb0_avtp_capture_b),
-	SH_PFC_PIN_GROUP(can0_data_a),
-	SH_PFC_PIN_GROUP(can0_data_b),
-	SH_PFC_PIN_GROUP(can1_data_a),
-	SH_PFC_PIN_GROUP(can1_data_b),
-	SH_PFC_PIN_GROUP(can_clk),
-	SH_PFC_PIN_GROUP(canfd0_data),
-	SH_PFC_PIN_GROUP(canfd1_data),
-	SH_PFC_PIN_GROUP(du_rgb666),
-	SH_PFC_PIN_GROUP(du_rgb888),
-	SH_PFC_PIN_GROUP(du_clk_in_1),
-	SH_PFC_PIN_GROUP(du_clk_out_0),
-	SH_PFC_PIN_GROUP(du_sync),
-	SH_PFC_PIN_GROUP(du_disp_cde),
-	SH_PFC_PIN_GROUP(du_cde),
-	SH_PFC_PIN_GROUP(du_disp),
-	SH_PFC_PIN_GROUP(i2c0),
-	SH_PFC_PIN_GROUP(i2c1),
-	SH_PFC_PIN_GROUP(i2c2_a),
-	SH_PFC_PIN_GROUP(i2c2_b),
-	SH_PFC_PIN_GROUP(i2c3_a),
-	SH_PFC_PIN_GROUP(i2c3_b),
-	SH_PFC_PIN_GROUP(mmc_data1),
-	SH_PFC_PIN_GROUP(mmc_data4),
-	SH_PFC_PIN_GROUP(mmc_data8),
-	SH_PFC_PIN_GROUP(mmc_ctrl),
-	SH_PFC_PIN_GROUP(msiof0_clk),
-	SH_PFC_PIN_GROUP(msiof0_sync),
-	SH_PFC_PIN_GROUP(msiof0_ss1),
-	SH_PFC_PIN_GROUP(msiof0_ss2),
-	SH_PFC_PIN_GROUP(msiof0_txd),
-	SH_PFC_PIN_GROUP(msiof0_rxd),
-	SH_PFC_PIN_GROUP(msiof1_clk),
-	SH_PFC_PIN_GROUP(msiof1_sync),
-	SH_PFC_PIN_GROUP(msiof1_ss1),
-	SH_PFC_PIN_GROUP(msiof1_ss2),
-	SH_PFC_PIN_GROUP(msiof1_txd),
-	SH_PFC_PIN_GROUP(msiof1_rxd),
-	SH_PFC_PIN_GROUP(msiof2_clk),
-	SH_PFC_PIN_GROUP(msiof2_sync_a),
-	SH_PFC_PIN_GROUP(msiof2_sync_b),
-	SH_PFC_PIN_GROUP(msiof2_ss1),
-	SH_PFC_PIN_GROUP(msiof2_ss2),
-	SH_PFC_PIN_GROUP(msiof2_txd),
-	SH_PFC_PIN_GROUP(msiof2_rxd),
-	SH_PFC_PIN_GROUP(msiof3_clk_a),
-	SH_PFC_PIN_GROUP(msiof3_sync_a),
-	SH_PFC_PIN_GROUP(msiof3_ss1_a),
-	SH_PFC_PIN_GROUP(msiof3_ss2_a),
-	SH_PFC_PIN_GROUP(msiof3_txd_a),
-	SH_PFC_PIN_GROUP(msiof3_rxd_a),
-	SH_PFC_PIN_GROUP(msiof3_clk_b),
-	SH_PFC_PIN_GROUP(msiof3_sync_b),
-	SH_PFC_PIN_GROUP(msiof3_ss1_b),
-	SH_PFC_PIN_GROUP(msiof3_ss2_b),
-	SH_PFC_PIN_GROUP(msiof3_txd_b),
-	SH_PFC_PIN_GROUP(msiof3_rxd_b),
-	SH_PFC_PIN_GROUP(pwm0_a),
-	SH_PFC_PIN_GROUP(pwm0_b),
-	SH_PFC_PIN_GROUP(pwm0_c),
-	SH_PFC_PIN_GROUP(pwm1_a),
-	SH_PFC_PIN_GROUP(pwm1_b),
-	SH_PFC_PIN_GROUP(pwm1_c),
-	SH_PFC_PIN_GROUP(pwm2_a),
-	SH_PFC_PIN_GROUP(pwm2_b),
-	SH_PFC_PIN_GROUP(pwm2_c),
-	SH_PFC_PIN_GROUP(pwm3_a),
-	SH_PFC_PIN_GROUP(pwm3_b),
-	SH_PFC_PIN_GROUP(pwm3_c),
-	SH_PFC_PIN_GROUP(scif0_data_a),
-	SH_PFC_PIN_GROUP(scif0_clk_a),
-	SH_PFC_PIN_GROUP(scif0_data_b),
-	SH_PFC_PIN_GROUP(scif0_clk_b),
-	SH_PFC_PIN_GROUP(scif0_ctrl),
-	SH_PFC_PIN_GROUP(scif1_data_a),
-	SH_PFC_PIN_GROUP(scif1_clk_a),
-	SH_PFC_PIN_GROUP(scif1_data_b),
-	SH_PFC_PIN_GROUP(scif1_clk_b),
-	SH_PFC_PIN_GROUP(scif1_ctrl),
-	SH_PFC_PIN_GROUP(scif2_data),
-	SH_PFC_PIN_GROUP(scif2_clk),
-	SH_PFC_PIN_GROUP(scif3_data_a),
-	SH_PFC_PIN_GROUP(scif3_clk_a),
-	SH_PFC_PIN_GROUP(scif3_data_b),
-	SH_PFC_PIN_GROUP(scif3_clk_b),
-	SH_PFC_PIN_GROUP(scif4_data_a),
-	SH_PFC_PIN_GROUP(scif4_clk_a),
-	SH_PFC_PIN_GROUP(scif4_data_b),
-	SH_PFC_PIN_GROUP(scif4_clk_b),
-	SH_PFC_PIN_GROUP(scif5_data_a),
-	SH_PFC_PIN_GROUP(scif5_clk_a),
-	SH_PFC_PIN_GROUP(scif5_data_b),
-	SH_PFC_PIN_GROUP(scif5_clk_b),
-	SH_PFC_PIN_GROUP(scif_clk),
-	SH_PFC_PIN_GROUP(ssi3_data),
-	SH_PFC_PIN_GROUP(ssi34_ctrl),
-	SH_PFC_PIN_GROUP(ssi4_ctrl_a),
-	SH_PFC_PIN_GROUP(ssi4_data_a),
-	SH_PFC_PIN_GROUP(ssi4_ctrl_b),
-	SH_PFC_PIN_GROUP(ssi4_data_b),
-	SH_PFC_PIN_GROUP(usb0),
-	VIN_DATA_PIN_GROUP(vin4_data, 8),
-	VIN_DATA_PIN_GROUP(vin4_data, 10),
-	VIN_DATA_PIN_GROUP(vin4_data, 12),
-	VIN_DATA_PIN_GROUP(vin4_data, 16),
-	SH_PFC_PIN_GROUP(vin4_data18),
-	VIN_DATA_PIN_GROUP(vin4_data, 20),
-	VIN_DATA_PIN_GROUP(vin4_data, 24),
-	SH_PFC_PIN_GROUP(vin4_sync),
-	SH_PFC_PIN_GROUP(vin4_field),
-	SH_PFC_PIN_GROUP(vin4_clkenb),
-	SH_PFC_PIN_GROUP(vin4_clk),
-};
-
-static const char * const audio_clk_groups[] = {
-	"audio_clk_a",
-	"audio_clk_b",
-	"audio_clkout",
-	"audio_clkout1",
-};
-
-static const char * const avb0_groups[] = {
-	"avb0_link",
-	"avb0_magic",
-	"avb0_phy_int",
-	"avb0_mdc",	/* Deprecated, please use "avb0_mdio" instead */
-	"avb0_mdio",
-	"avb0_mii",
-	"avb0_avtp_pps_a",
-	"avb0_avtp_match_a",
-	"avb0_avtp_capture_a",
-	"avb0_avtp_pps_b",
-	"avb0_avtp_match_b",
-	"avb0_avtp_capture_b",
-};
-
-static const char * const can0_groups[] = {
-	"can0_data_a",
-	"can0_data_b",
-};
-static const char * const can1_groups[] = {
-	"can1_data_a",
-	"can1_data_b",
-};
-static const char * const can_clk_groups[] = {
-	"can_clk",
-};
-
-static const char * const canfd0_groups[] = {
-	"canfd0_data",
-};
-static const char * const canfd1_groups[] = {
-	"canfd1_data",
-};
-
-static const char * const du_groups[] = {
-	"du_rgb666",
-	"du_rgb888",
-	"du_clk_in_1",
-	"du_clk_out_0",
-	"du_sync",
-	"du_disp_cde",
-	"du_cde",
-	"du_disp",
-};
-
-static const char * const i2c0_groups[] = {
-	"i2c0",
-};
-static const char * const i2c1_groups[] = {
-	"i2c1",
-};
-
-static const char * const i2c2_groups[] = {
-	"i2c2_a",
-	"i2c2_b",
-};
-
-static const char * const i2c3_groups[] = {
-	"i2c3_a",
-	"i2c3_b",
-};
-
-static const char * const mmc_groups[] = {
-	"mmc_data1",
-	"mmc_data4",
-	"mmc_data8",
-	"mmc_ctrl",
-};
-
-static const char * const pwm0_groups[] = {
-	"pwm0_a",
-	"pwm0_b",
-	"pwm0_c",
-};
-
-static const char * const pwm1_groups[] = {
-	"pwm1_a",
-	"pwm1_b",
-	"pwm1_c",
-};
-
-static const char * const pwm2_groups[] = {
-	"pwm2_a",
-	"pwm2_b",
-	"pwm2_c",
-};
-
-static const char * const pwm3_groups[] = {
-	"pwm3_a",
-	"pwm3_b",
-	"pwm3_c",
-};
-
-static const char * const scif0_groups[] = {
-	"scif0_data_a",
-	"scif0_clk_a",
-	"scif0_data_b",
-	"scif0_clk_b",
-	"scif0_ctrl",
-};
-
-static const char * const scif1_groups[] = {
-	"scif1_data_a",
-	"scif1_clk_a",
-	"scif1_data_b",
-	"scif1_clk_b",
-	"scif1_ctrl",
-};
-
-static const char * const scif2_groups[] = {
-	"scif2_data",
-	"scif2_clk",
-};
-
-static const char * const scif3_groups[] = {
-	"scif3_data_a",
-	"scif3_clk_a",
-	"scif3_data_b",
-	"scif3_clk_b",
-};
-
-static const char * const scif4_groups[] = {
-	"scif4_data_a",
-	"scif4_clk_a",
-	"scif4_data_b",
-	"scif4_clk_b",
-};
-
-static const char * const scif5_groups[] = {
-	"scif5_data_a",
-	"scif5_clk_a",
-	"scif5_data_b",
-	"scif5_clk_b",
-};
-
-static const char * const scif_clk_groups[] = {
-	"scif_clk",
-};
-
-static const char * const ssi_groups[] = {
-	"ssi3_data",
-	"ssi34_ctrl",
-	"ssi4_ctrl_a",
-	"ssi4_data_a",
-	"ssi4_ctrl_b",
-	"ssi4_data_b",
-};
-
-static const char * const usb0_groups[] = {
-	"usb0",
-};
-
-static const char * const vin4_groups[] = {
-	"vin4_data8",
-	"vin4_data10",
-	"vin4_data12",
-	"vin4_data16",
-	"vin4_data18",
-	"vin4_data20",
-	"vin4_data24",
-	"vin4_sync",
-	"vin4_field",
-	"vin4_clkenb",
-	"vin4_clk",
-};
-
-static const char * const msiof0_groups[] = {
-	"msiof0_clk",
-	"msiof0_sync",
-	"msiof0_ss1",
-	"msiof0_ss2",
-	"msiof0_txd",
-	"msiof0_rxd",
-};
-
-static const char * const msiof1_groups[] = {
-	"msiof1_clk",
-	"msiof1_sync",
-	"msiof1_ss1",
-	"msiof1_ss2",
-	"msiof1_txd",
-	"msiof1_rxd",
-};
-
-static const char * const msiof2_groups[] = {
-	"msiof2_clk",
-	"msiof2_sync_a",
-	"msiof2_sync_b",
-	"msiof2_ss1",
-	"msiof2_ss2",
-	"msiof2_txd",
-	"msiof2_rxd",
-};
-
-static const char * const msiof3_groups[] = {
-	"msiof3_clk_a",
-	"msiof3_sync_a",
-	"msiof3_ss1_a",
-	"msiof3_ss2_a",
-	"msiof3_txd_a",
-	"msiof3_rxd_a",
-	"msiof3_clk_b",
-	"msiof3_sync_b",
-	"msiof3_ss1_b",
-	"msiof3_ss2_b",
-	"msiof3_txd_b",
-	"msiof3_rxd_b",
-};
-
-static const struct sh_pfc_function pinmux_functions[] = {
-	SH_PFC_FUNCTION(audio_clk),
-	SH_PFC_FUNCTION(avb0),
-	SH_PFC_FUNCTION(can0),
-	SH_PFC_FUNCTION(can1),
-	SH_PFC_FUNCTION(can_clk),
-	SH_PFC_FUNCTION(canfd0),
-	SH_PFC_FUNCTION(canfd1),
-	SH_PFC_FUNCTION(du),
-	SH_PFC_FUNCTION(i2c0),
-	SH_PFC_FUNCTION(i2c1),
-	SH_PFC_FUNCTION(i2c2),
-	SH_PFC_FUNCTION(i2c3),
-	SH_PFC_FUNCTION(mmc),
-	SH_PFC_FUNCTION(msiof0),
-	SH_PFC_FUNCTION(msiof1),
-	SH_PFC_FUNCTION(msiof2),
-	SH_PFC_FUNCTION(msiof3),
-	SH_PFC_FUNCTION(pwm0),
-	SH_PFC_FUNCTION(pwm1),
-	SH_PFC_FUNCTION(pwm2),
-	SH_PFC_FUNCTION(pwm3),
-	SH_PFC_FUNCTION(scif0),
-	SH_PFC_FUNCTION(scif1),
-	SH_PFC_FUNCTION(scif2),
-	SH_PFC_FUNCTION(scif3),
-	SH_PFC_FUNCTION(scif4),
-	SH_PFC_FUNCTION(scif5),
-	SH_PFC_FUNCTION(scif_clk),
-	SH_PFC_FUNCTION(ssi),
-	SH_PFC_FUNCTION(usb0),
-	SH_PFC_FUNCTION(vin4),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-#define F_(x, y)	FN_##y
-#define FM(x)		FN_##x
-	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_0_8_FN,	GPSR0_8,
-		GP_0_7_FN,	GPSR0_7,
-		GP_0_6_FN,	GPSR0_6,
-		GP_0_5_FN,	GPSR0_5,
-		GP_0_4_FN,	GPSR0_4,
-		GP_0_3_FN,	GPSR0_3,
-		GP_0_2_FN,	GPSR0_2,
-		GP_0_1_FN,	GPSR0_1,
-		GP_0_0_FN,	GPSR0_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
-		GP_1_31_FN,	GPSR1_31,
-		GP_1_30_FN,	GPSR1_30,
-		GP_1_29_FN,	GPSR1_29,
-		GP_1_28_FN,	GPSR1_28,
-		GP_1_27_FN,	GPSR1_27,
-		GP_1_26_FN,	GPSR1_26,
-		GP_1_25_FN,	GPSR1_25,
-		GP_1_24_FN,	GPSR1_24,
-		GP_1_23_FN,	GPSR1_23,
-		GP_1_22_FN,	GPSR1_22,
-		GP_1_21_FN,	GPSR1_21,
-		GP_1_20_FN,	GPSR1_20,
-		GP_1_19_FN,	GPSR1_19,
-		GP_1_18_FN,	GPSR1_18,
-		GP_1_17_FN,	GPSR1_17,
-		GP_1_16_FN,	GPSR1_16,
-		GP_1_15_FN,	GPSR1_15,
-		GP_1_14_FN,	GPSR1_14,
-		GP_1_13_FN,	GPSR1_13,
-		GP_1_12_FN,	GPSR1_12,
-		GP_1_11_FN,	GPSR1_11,
-		GP_1_10_FN,	GPSR1_10,
-		GP_1_9_FN,	GPSR1_9,
-		GP_1_8_FN,	GPSR1_8,
-		GP_1_7_FN,	GPSR1_7,
-		GP_1_6_FN,	GPSR1_6,
-		GP_1_5_FN,	GPSR1_5,
-		GP_1_4_FN,	GPSR1_4,
-		GP_1_3_FN,	GPSR1_3,
-		GP_1_2_FN,	GPSR1_2,
-		GP_1_1_FN,	GPSR1_1,
-		GP_1_0_FN,	GPSR1_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
-		GP_2_31_FN,	GPSR2_31,
-		GP_2_30_FN,	GPSR2_30,
-		GP_2_29_FN,	GPSR2_29,
-		GP_2_28_FN,	GPSR2_28,
-		GP_2_27_FN,	GPSR2_27,
-		GP_2_26_FN,	GPSR2_26,
-		GP_2_25_FN,	GPSR2_25,
-		GP_2_24_FN,	GPSR2_24,
-		GP_2_23_FN,	GPSR2_23,
-		GP_2_22_FN,	GPSR2_22,
-		GP_2_21_FN,	GPSR2_21,
-		GP_2_20_FN,	GPSR2_20,
-		GP_2_19_FN,	GPSR2_19,
-		GP_2_18_FN,	GPSR2_18,
-		GP_2_17_FN,	GPSR2_17,
-		GP_2_16_FN,	GPSR2_16,
-		GP_2_15_FN,	GPSR2_15,
-		GP_2_14_FN,	GPSR2_14,
-		GP_2_13_FN,	GPSR2_13,
-		GP_2_12_FN,	GPSR2_12,
-		GP_2_11_FN,	GPSR2_11,
-		GP_2_10_FN,	GPSR2_10,
-		GP_2_9_FN,	GPSR2_9,
-		GP_2_8_FN,	GPSR2_8,
-		GP_2_7_FN,	GPSR2_7,
-		GP_2_6_FN,	GPSR2_6,
-		GP_2_5_FN,	GPSR2_5,
-		GP_2_4_FN,	GPSR2_4,
-		GP_2_3_FN,	GPSR2_3,
-		GP_2_2_FN,	GPSR2_2,
-		GP_2_1_FN,	GPSR2_1,
-		GP_2_0_FN,	GPSR2_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_3_9_FN,	GPSR3_9,
-		GP_3_8_FN,	GPSR3_8,
-		GP_3_7_FN,	GPSR3_7,
-		GP_3_6_FN,	GPSR3_6,
-		GP_3_5_FN,	GPSR3_5,
-		GP_3_4_FN,	GPSR3_4,
-		GP_3_3_FN,	GPSR3_3,
-		GP_3_2_FN,	GPSR3_2,
-		GP_3_1_FN,	GPSR3_1,
-		GP_3_0_FN,	GPSR3_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
-		GP_4_31_FN,	GPSR4_31,
-		GP_4_30_FN,	GPSR4_30,
-		GP_4_29_FN,	GPSR4_29,
-		GP_4_28_FN,	GPSR4_28,
-		GP_4_27_FN,	GPSR4_27,
-		GP_4_26_FN,	GPSR4_26,
-		GP_4_25_FN,	GPSR4_25,
-		GP_4_24_FN,	GPSR4_24,
-		GP_4_23_FN,	GPSR4_23,
-		GP_4_22_FN,	GPSR4_22,
-		GP_4_21_FN,	GPSR4_21,
-		GP_4_20_FN,	GPSR4_20,
-		GP_4_19_FN,	GPSR4_19,
-		GP_4_18_FN,	GPSR4_18,
-		GP_4_17_FN,	GPSR4_17,
-		GP_4_16_FN,	GPSR4_16,
-		GP_4_15_FN,	GPSR4_15,
-		GP_4_14_FN,	GPSR4_14,
-		GP_4_13_FN,	GPSR4_13,
-		GP_4_12_FN,	GPSR4_12,
-		GP_4_11_FN,	GPSR4_11,
-		GP_4_10_FN,	GPSR4_10,
-		GP_4_9_FN,	GPSR4_9,
-		GP_4_8_FN,	GPSR4_8,
-		GP_4_7_FN,	GPSR4_7,
-		GP_4_6_FN,	GPSR4_6,
-		GP_4_5_FN,	GPSR4_5,
-		GP_4_4_FN,	GPSR4_4,
-		GP_4_3_FN,	GPSR4_3,
-		GP_4_2_FN,	GPSR4_2,
-		GP_4_1_FN,	GPSR4_1,
-		GP_4_0_FN,	GPSR4_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_5_20_FN,	GPSR5_20,
-		GP_5_19_FN,	GPSR5_19,
-		GP_5_18_FN,	GPSR5_18,
-		GP_5_17_FN,	GPSR5_17,
-		GP_5_16_FN,	GPSR5_16,
-		GP_5_15_FN,	GPSR5_15,
-		GP_5_14_FN,	GPSR5_14,
-		GP_5_13_FN,	GPSR5_13,
-		GP_5_12_FN,	GPSR5_12,
-		GP_5_11_FN,	GPSR5_11,
-		GP_5_10_FN,	GPSR5_10,
-		GP_5_9_FN,	GPSR5_9,
-		GP_5_8_FN,	GPSR5_8,
-		GP_5_7_FN,	GPSR5_7,
-		GP_5_6_FN,	GPSR5_6,
-		GP_5_5_FN,	GPSR5_5,
-		GP_5_4_FN,	GPSR5_4,
-		GP_5_3_FN,	GPSR5_3,
-		GP_5_2_FN,	GPSR5_2,
-		GP_5_1_FN,	GPSR5_1,
-		GP_5_0_FN,	GPSR5_0, ))
-	},
-	{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_6_13_FN,	GPSR6_13,
-		GP_6_12_FN,	GPSR6_12,
-		GP_6_11_FN,	GPSR6_11,
-		GP_6_10_FN,	GPSR6_10,
-		GP_6_9_FN,	GPSR6_9,
-		GP_6_8_FN,	GPSR6_8,
-		GP_6_7_FN,	GPSR6_7,
-		GP_6_6_FN,	GPSR6_6,
-		GP_6_5_FN,	GPSR6_5,
-		GP_6_4_FN,	GPSR6_4,
-		GP_6_3_FN,	GPSR6_3,
-		GP_6_2_FN,	GPSR6_2,
-		GP_6_1_FN,	GPSR6_1,
-		GP_6_0_FN,	GPSR6_0, ))
-	},
-#undef F_
-#undef FM
-
-#define F_(x, y)	x,
-#define FM(x)		FN_##x,
-	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
-		IP0_31_28
-		IP0_27_24
-		IP0_23_20
-		IP0_19_16
-		IP0_15_12
-		IP0_11_8
-		IP0_7_4
-		IP0_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
-		IP1_31_28
-		IP1_27_24
-		IP1_23_20
-		IP1_19_16
-		IP1_15_12
-		IP1_11_8
-		IP1_7_4
-		IP1_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
-		IP2_31_28
-		IP2_27_24
-		IP2_23_20
-		IP2_19_16
-		IP2_15_12
-		IP2_11_8
-		IP2_7_4
-		IP2_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
-		IP3_31_28
-		IP3_27_24
-		IP3_23_20
-		IP3_19_16
-		IP3_15_12
-		IP3_11_8
-		IP3_7_4
-		IP3_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
-		IP4_31_28
-		IP4_27_24
-		IP4_23_20
-		IP4_19_16
-		IP4_15_12
-		IP4_11_8
-		IP4_7_4
-		IP4_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
-		IP5_31_28
-		IP5_27_24
-		IP5_23_20
-		IP5_19_16
-		IP5_15_12
-		IP5_11_8
-		IP5_7_4
-		IP5_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
-		IP6_31_28
-		IP6_27_24
-		IP6_23_20
-		IP6_19_16
-		IP6_15_12
-		IP6_11_8
-		IP6_7_4
-		IP6_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
-		IP7_31_28
-		IP7_27_24
-		IP7_23_20
-		IP7_19_16
-		IP7_15_12
-		IP7_11_8
-		IP7_7_4
-		IP7_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
-		IP8_31_28
-		IP8_27_24
-		IP8_23_20
-		IP8_19_16
-		IP8_15_12
-		IP8_11_8
-		IP8_7_4
-		IP8_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
-		IP9_31_28
-		IP9_27_24
-		IP9_23_20
-		IP9_19_16
-		IP9_15_12
-		IP9_11_8
-		IP9_7_4
-		IP9_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
-		IP10_31_28
-		IP10_27_24
-		IP10_23_20
-		IP10_19_16
-		IP10_15_12
-		IP10_11_8
-		IP10_7_4
-		IP10_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
-		IP11_31_28
-		IP11_27_24
-		IP11_23_20
-		IP11_19_16
-		IP11_15_12
-		IP11_11_8
-		IP11_7_4
-		IP11_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
-		IP12_31_28
-		IP12_27_24
-		IP12_23_20
-		IP12_19_16
-		IP12_15_12
-		IP12_11_8
-		IP12_7_4
-		IP12_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
-		/* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP13_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* IP13_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		IP13_7_4
-		IP13_3_0 ))
-	},
-#undef F_
-#undef FM
-
-#define F_(x, y)	x,
-#define FM(x)		FN_##x,
-	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
-			     GROUP(1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
-				   1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1),
-			     GROUP(
-		/* RESERVED 31 */
-		0, 0,
-		MOD_SEL0_30
-		MOD_SEL0_29
-		MOD_SEL0_28
-		MOD_SEL0_27
-		MOD_SEL0_26
-		MOD_SEL0_25
-		MOD_SEL0_24_23
-		MOD_SEL0_22_21
-		MOD_SEL0_20_19
-		MOD_SEL0_18_17
-		/* RESERVED 16 */
-		0, 0,
-		MOD_SEL0_15
-		MOD_SEL0_14
-		MOD_SEL0_13
-		MOD_SEL0_12
-		MOD_SEL0_11
-		MOD_SEL0_10
-		/* RESERVED 9, 8, 7, 6 */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		MOD_SEL0_5
-		MOD_SEL0_4
-		MOD_SEL0_3
-		MOD_SEL0_2
-		MOD_SEL0_1
-		MOD_SEL0_0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
-			     GROUP(1, 1, 1, 1, 1, 1, 2, 4, 4, 4, 4, 4, 4),
-			     GROUP(
-		MOD_SEL1_31
-		MOD_SEL1_30
-		MOD_SEL1_29
-		MOD_SEL1_28
-		MOD_SEL1_27
-		MOD_SEL1_26
-		/* RESERVED 25, 24 */
-		0, 0, 0, 0,
-		/* RESERVED 23, 22, 21, 20 */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 19, 18, 17, 16 */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 15, 14, 13, 12 */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 11, 10, 9, 8  */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 7, 6, 5, 4  */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESERVED 3, 2, 1, 0  */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ },
-};
-
-static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
-{
-	int bit = -EINVAL;
-
-	*pocctrl = 0xe6060380;
-
-	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9))
-		bit = 29 - (pin - RCAR_GP_PIN(3, 0));
-
-	return bit;
-}
-
-enum ioctrl_regs {
-	TDSELCTRL,
-};
-
-static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
-	[TDSELCTRL] = { 0xe60603c0, },
-	{ /* sentinel */ },
-};
-
-static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
-	.pin_to_pocctrl = r8a77995_pin_to_pocctrl,
-};
-
-const struct sh_pfc_soc_info r8a77995_pinmux_info = {
-	.name = "r8a77995_pfc",
-	.ops = &r8a77995_pinmux_ops,
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups,
-	.nr_groups = ARRAY_SIZE(pinmux_groups),
-	.functions = pinmux_functions,
-	.nr_functions = ARRAY_SIZE(pinmux_functions),
-
-	.cfg_regs = pinmux_config_regs,
-	.ioctrl_regs = pinmux_ioctrl_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
deleted file mode 100644
index 811a6f2cb1fc..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c
+++ /dev/null
@@ -1,1589 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * SH7203 Pinmux
- *
- *  Copyright (C) 2008  Magnus Damm
- */
-
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <cpu/sh7203.h>
-
-#include "sh_pfc.h"
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
-	PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
-	PB12_DATA,
-	PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
-	PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
-	PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
-	PC14_DATA, PC13_DATA, PC12_DATA,
-	PC11_DATA, PC10_DATA, PC9_DATA, PC8_DATA,
-	PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
-	PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
-	PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
-	PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
-	PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
-	PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
-	PE15_DATA, PE14_DATA, PE13_DATA, PE12_DATA,
-	PE11_DATA, PE10_DATA, PE9_DATA, PE8_DATA,
-	PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
-	PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
-	PF30_DATA, PF29_DATA, PF28_DATA,
-	PF27_DATA, PF26_DATA, PF25_DATA, PF24_DATA,
-	PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA,
-	PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA,
-	PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA,
-	PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
-	PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
-	PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
-	PINMUX_DATA_END,
-
-	PINMUX_INPUT_BEGIN,
-	FORCE_IN,
-	PA7_IN, PA6_IN, PA5_IN, PA4_IN,
-	PA3_IN, PA2_IN, PA1_IN, PA0_IN,
-	PB11_IN, PB10_IN, PB9_IN, PB8_IN,
-	PC14_IN, PC13_IN, PC12_IN,
-	PC11_IN, PC10_IN, PC9_IN, PC8_IN,
-	PC7_IN, PC6_IN, PC5_IN, PC4_IN,
-	PC3_IN, PC2_IN, PC1_IN, PC0_IN,
-	PD15_IN, PD14_IN, PD13_IN, PD12_IN,
-	PD11_IN, PD10_IN, PD9_IN, PD8_IN,
-	PD7_IN, PD6_IN, PD5_IN, PD4_IN,
-	PD3_IN, PD2_IN, PD1_IN, PD0_IN,
-	PE15_IN, PE14_IN, PE13_IN, PE12_IN,
-	PE11_IN, PE10_IN, PE9_IN, PE8_IN,
-	PE7_IN, PE6_IN, PE5_IN, PE4_IN,
-	PE3_IN, PE2_IN, PE1_IN, PE0_IN,
-	PF30_IN, PF29_IN, PF28_IN,
-	PF27_IN, PF26_IN, PF25_IN, PF24_IN,
-	PF23_IN, PF22_IN, PF21_IN, PF20_IN,
-	PF19_IN, PF18_IN, PF17_IN, PF16_IN,
-	PF15_IN, PF14_IN, PF13_IN, PF12_IN,
-	PF11_IN, PF10_IN, PF9_IN, PF8_IN,
-	PF7_IN, PF6_IN, PF5_IN, PF4_IN,
-	PF3_IN, PF2_IN, PF1_IN, PF0_IN,
-	PINMUX_INPUT_END,
-
-	PINMUX_OUTPUT_BEGIN,
-	FORCE_OUT,
-	PB11_OUT, PB10_OUT, PB9_OUT, PB8_OUT,
-	PC14_OUT, PC13_OUT, PC12_OUT,
-	PC11_OUT, PC10_OUT, PC9_OUT, PC8_OUT,
-	PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
-	PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
-	PD15_OUT, PD14_OUT, PD13_OUT, PD12_OUT,
-	PD11_OUT, PD10_OUT, PD9_OUT, PD8_OUT,
-	PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
-	PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
-	PE15_OUT, PE14_OUT, PE13_OUT, PE12_OUT,
-	PE11_OUT, PE10_OUT, PE9_OUT, PE8_OUT,
-	PE7_OUT, PE6_OUT, PE5_OUT, PE4_OUT,
-	PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
-	PF30_OUT, PF29_OUT, PF28_OUT,
-	PF27_OUT, PF26_OUT, PF25_OUT, PF24_OUT,
-	PF23_OUT, PF22_OUT, PF21_OUT, PF20_OUT,
-	PF19_OUT, PF18_OUT, PF17_OUT, PF16_OUT,
-	PF15_OUT, PF14_OUT, PF13_OUT, PF12_OUT,
-	PF11_OUT, PF10_OUT, PF9_OUT, PF8_OUT,
-	PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
-	PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
-	PINMUX_OUTPUT_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	PB11_IOR_IN, PB11_IOR_OUT,
-	PB10_IOR_IN, PB10_IOR_OUT,
-	PB9_IOR_IN, PB9_IOR_OUT,
-	PB8_IOR_IN, PB8_IOR_OUT,
-	PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11,
-	PB11MD_0, PB11MD_1,
-	PB10MD_0, PB10MD_1,
-	PB9MD_00, PB9MD_01, PB9MD_10,
-	PB8MD_00, PB8MD_01, PB8MD_10,
-	PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11,
-	PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11,
-	PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11,
-	PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11,
-	PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11,
-	PB2MD_00, PB2MD_01, PB2MD_10, PB2MD_11,
-	PB1MD_00, PB1MD_01, PB1MD_10, PB1MD_11,
-	PB0MD_00, PB0MD_01, PB0MD_10, PB0MD_11,
-
-	PB12IRQ_00, PB12IRQ_01, PB12IRQ_10,
-
-	PC14MD_0, PC14MD_1,
-	PC13MD_0, PC13MD_1,
-	PC12MD_0, PC12MD_1,
-	PC11MD_00, PC11MD_01, PC11MD_10,
-	PC10MD_00, PC10MD_01, PC10MD_10,
-	PC9MD_0, PC9MD_1,
-	PC8MD_0, PC8MD_1,
-	PC7MD_0, PC7MD_1,
-	PC6MD_0, PC6MD_1,
-	PC5MD_0, PC5MD_1,
-	PC4MD_0, PC4MD_1,
-	PC3MD_0, PC3MD_1,
-	PC2MD_0, PC2MD_1,
-	PC1MD_0, PC1MD_1,
-	PC0MD_00, PC0MD_01, PC0MD_10,
-
-	PD15MD_000, PD15MD_001, PD15MD_010, PD15MD_100, PD15MD_101,
-	PD14MD_000, PD14MD_001, PD14MD_010, PD14MD_101,
-	PD13MD_000, PD13MD_001, PD13MD_010, PD13MD_100, PD13MD_101,
-	PD12MD_000, PD12MD_001, PD12MD_010, PD12MD_100, PD12MD_101,
-	PD11MD_000, PD11MD_001, PD11MD_010, PD11MD_100, PD11MD_101,
-	PD10MD_000, PD10MD_001, PD10MD_010, PD10MD_100, PD10MD_101,
-	PD9MD_000, PD9MD_001, PD9MD_010, PD9MD_100, PD9MD_101,
-	PD8MD_000, PD8MD_001, PD8MD_010, PD8MD_100, PD8MD_101,
-	PD7MD_000, PD7MD_001, PD7MD_010, PD7MD_011, PD7MD_100, PD7MD_101,
-	PD6MD_000, PD6MD_001, PD6MD_010, PD6MD_011, PD6MD_100, PD6MD_101,
-	PD5MD_000, PD5MD_001, PD5MD_010, PD5MD_011, PD5MD_100, PD5MD_101,
-	PD4MD_000, PD4MD_001, PD4MD_010, PD4MD_011, PD4MD_100, PD4MD_101,
-	PD3MD_000, PD3MD_001, PD3MD_010, PD3MD_011, PD3MD_100, PD3MD_101,
-	PD2MD_000, PD2MD_001, PD2MD_010, PD2MD_011, PD2MD_100, PD2MD_101,
-	PD1MD_000, PD1MD_001, PD1MD_010, PD1MD_011, PD1MD_100, PD1MD_101,
-	PD0MD_000, PD0MD_001, PD0MD_010, PD0MD_011, PD0MD_100, PD0MD_101,
-
-	PE15MD_00, PE15MD_01, PE15MD_11,
-	PE14MD_00, PE14MD_01, PE14MD_11,
-	PE13MD_00, PE13MD_11,
-	PE12MD_00, PE12MD_11,
-	PE11MD_000, PE11MD_001, PE11MD_010, PE11MD_100,
-	PE10MD_000, PE10MD_001, PE10MD_010, PE10MD_100,
-	PE9MD_00, PE9MD_01, PE9MD_10, PE9MD_11,
-	PE8MD_00, PE8MD_01, PE8MD_10, PE8MD_11,
-	PE7MD_000, PE7MD_001, PE7MD_010, PE7MD_011, PE7MD_100,
-	PE6MD_000, PE6MD_001, PE6MD_010, PE6MD_011, PE6MD_100,
-	PE5MD_000, PE5MD_001, PE5MD_010, PE5MD_011, PE5MD_100,
-	PE4MD_000, PE4MD_001, PE4MD_010, PE4MD_011, PE4MD_100,
-	PE3MD_00, PE3MD_01, PE3MD_11,
-	PE2MD_00, PE2MD_01, PE2MD_11,
-	PE1MD_00, PE1MD_01, PE1MD_10, PE1MD_11,
-	PE0MD_000, PE0MD_001, PE0MD_011, PE0MD_100,
-
-	PF30MD_0, PF30MD_1,
-	PF29MD_0, PF29MD_1,
-	PF28MD_0, PF28MD_1,
-	PF27MD_0, PF27MD_1,
-	PF26MD_0, PF26MD_1,
-	PF25MD_0, PF25MD_1,
-	PF24MD_0, PF24MD_1,
-	PF23MD_00, PF23MD_01, PF23MD_10,
-	PF22MD_00, PF22MD_01, PF22MD_10,
-	PF21MD_00, PF21MD_01, PF21MD_10,
-	PF20MD_00, PF20MD_01, PF20MD_10,
-	PF19MD_00, PF19MD_01, PF19MD_10,
-	PF18MD_00, PF18MD_01, PF18MD_10,
-	PF17MD_00, PF17MD_01, PF17MD_10,
-	PF16MD_00, PF16MD_01, PF16MD_10,
-	PF15MD_00, PF15MD_01, PF15MD_10,
-	PF14MD_00, PF14MD_01, PF14MD_10,
-	PF13MD_00, PF13MD_01, PF13MD_10,
-	PF12MD_00, PF12MD_01, PF12MD_10,
-	PF11MD_00, PF11MD_01, PF11MD_10,
-	PF10MD_00, PF10MD_01, PF10MD_10,
-	PF9MD_00, PF9MD_01, PF9MD_10,
-	PF8MD_00, PF8MD_01, PF8MD_10,
-	PF7MD_00, PF7MD_01, PF7MD_10, PF7MD_11,
-	PF6MD_00, PF6MD_01, PF6MD_10, PF6MD_11,
-	PF5MD_00, PF5MD_01, PF5MD_10, PF5MD_11,
-	PF4MD_00, PF4MD_01, PF4MD_10, PF4MD_11,
-	PF3MD_00, PF3MD_01, PF3MD_10, PF3MD_11,
-	PF2MD_00, PF2MD_01, PF2MD_10, PF2MD_11,
-	PF1MD_00, PF1MD_01, PF1MD_10, PF1MD_11,
-	PF0MD_00, PF0MD_01, PF0MD_10, PF0MD_11,
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-	PINT7_PB_MARK, PINT6_PB_MARK, PINT5_PB_MARK, PINT4_PB_MARK,
-	PINT3_PB_MARK, PINT2_PB_MARK, PINT1_PB_MARK, PINT0_PB_MARK,
-	PINT7_PD_MARK, PINT6_PD_MARK, PINT5_PD_MARK, PINT4_PD_MARK,
-	PINT3_PD_MARK, PINT2_PD_MARK, PINT1_PD_MARK, PINT0_PD_MARK,
-	IRQ7_PB_MARK, IRQ6_PB_MARK, IRQ5_PB_MARK, IRQ4_PB_MARK,
-	IRQ3_PB_MARK, IRQ2_PB_MARK, IRQ1_PB_MARK, IRQ0_PB_MARK,
-	IRQ7_PD_MARK, IRQ6_PD_MARK, IRQ5_PD_MARK, IRQ4_PD_MARK,
-	IRQ3_PD_MARK, IRQ2_PD_MARK, IRQ1_PD_MARK, IRQ0_PD_MARK,
-	IRQ7_PE_MARK, IRQ6_PE_MARK, IRQ5_PE_MARK, IRQ4_PE_MARK,
-	IRQ3_PE_MARK, IRQ2_PE_MARK, IRQ1_PE_MARK, IRQ0_PE_MARK,
-	WDTOVF_MARK, IRQOUT_MARK, REFOUT_MARK, IRQOUT_REFOUT_MARK,
-	UBCTRG_MARK,
-	CTX1_MARK, CRX1_MARK, CTX0_MARK, CTX0_CTX1_MARK,
-	CRX0_MARK, CRX0_CRX1_MARK,
-	SDA3_MARK, SCL3_MARK,
-	SDA2_MARK, SCL2_MARK,
-	SDA1_MARK, SCL1_MARK,
-	SDA0_MARK, SCL0_MARK,
-	TEND0_PD_MARK, TEND0_PE_MARK, DACK0_PD_MARK, DACK0_PE_MARK,
-	DREQ0_PD_MARK, DREQ0_PE_MARK, TEND1_PD_MARK, TEND1_PE_MARK,
-	DACK1_PD_MARK, DACK1_PE_MARK, DREQ1_PD_MARK, DREQ1_PE_MARK,
-	DACK2_MARK, DREQ2_MARK, DACK3_MARK, DREQ3_MARK,
-	ADTRG_PD_MARK, ADTRG_PE_MARK,
-	D31_MARK, D30_MARK, D29_MARK, D28_MARK,
-	D27_MARK, D26_MARK, D25_MARK, D24_MARK,
-	D23_MARK, D22_MARK, D21_MARK, D20_MARK,
-	D19_MARK, D18_MARK, D17_MARK, D16_MARK,
-	A25_MARK, A24_MARK, A23_MARK, A22_MARK,
-	A21_MARK, CS4_MARK, MRES_MARK, BS_MARK,
-	IOIS16_MARK, CS1_MARK, CS6_CE1B_MARK, CE2B_MARK,
-	CS5_CE1A_MARK, CE2A_MARK, FRAME_MARK, WAIT_MARK,
-	RDWR_MARK, CKE_MARK, CASU_MARK,	BREQ_MARK,
-	RASU_MARK, BACK_MARK, CASL_MARK, RASL_MARK,
-	WE3_DQMUU_AH_ICIO_WR_MARK, WE2_DQMUL_ICIORD_MARK,
-	WE1_DQMLU_WE_MARK, WE0_DQMLL_MARK,
-	CS3_MARK, CS2_MARK, A1_MARK, A0_MARK, CS7_MARK,
-	TIOC4D_MARK, TIOC4C_MARK, TIOC4B_MARK, TIOC4A_MARK,
-	TIOC3D_MARK, TIOC3C_MARK, TIOC3B_MARK, TIOC3A_MARK,
-	TIOC2B_MARK, TIOC1B_MARK, TIOC2A_MARK, TIOC1A_MARK,
-	TIOC0D_MARK, TIOC0C_MARK, TIOC0B_MARK, TIOC0A_MARK,
-	TCLKD_PD_MARK, TCLKC_PD_MARK, TCLKB_PD_MARK, TCLKA_PD_MARK,
-	TCLKD_PF_MARK, TCLKC_PF_MARK, TCLKB_PF_MARK, TCLKA_PF_MARK,
-	SCS0_PD_MARK, SSO0_PD_MARK, SSI0_PD_MARK, SSCK0_PD_MARK,
-	SCS0_PF_MARK, SSO0_PF_MARK, SSI0_PF_MARK, SSCK0_PF_MARK,
-	SCS1_PD_MARK, SSO1_PD_MARK, SSI1_PD_MARK, SSCK1_PD_MARK,
-	SCS1_PF_MARK, SSO1_PF_MARK, SSI1_PF_MARK, SSCK1_PF_MARK,
-	TXD0_MARK, RXD0_MARK, SCK0_MARK,
-	TXD1_MARK, RXD1_MARK, SCK1_MARK,
-	TXD2_MARK, RXD2_MARK, SCK2_MARK,
-	RTS3_MARK, CTS3_MARK, TXD3_MARK,
-	RXD3_MARK, SCK3_MARK,
-	AUDIO_CLK_MARK,
-	SSIDATA3_MARK, SSIWS3_MARK, SSISCK3_MARK,
-	SSIDATA2_MARK, SSIWS2_MARK, SSISCK2_MARK,
-	SSIDATA1_MARK, SSIWS1_MARK, SSISCK1_MARK,
-	SSIDATA0_MARK, SSIWS0_MARK, SSISCK0_MARK,
-	FCE_MARK, FRB_MARK,
-	NAF7_MARK, NAF6_MARK, NAF5_MARK, NAF4_MARK,
-	NAF3_MARK, NAF2_MARK, NAF1_MARK, NAF0_MARK,
-	FSC_MARK, FOE_MARK, FCDE_MARK, FWE_MARK,
-	LCD_VEPWC_MARK, LCD_VCPWC_MARK,	LCD_CLK_MARK, LCD_FLM_MARK,
-	LCD_M_DISP_MARK, LCD_CL2_MARK, LCD_CL1_MARK, LCD_DON_MARK,
-	LCD_DATA15_MARK, LCD_DATA14_MARK, LCD_DATA13_MARK, LCD_DATA12_MARK,
-	LCD_DATA11_MARK, LCD_DATA10_MARK, LCD_DATA9_MARK, LCD_DATA8_MARK,
-	LCD_DATA7_MARK, LCD_DATA6_MARK, LCD_DATA5_MARK, LCD_DATA4_MARK,
-	LCD_DATA3_MARK, LCD_DATA2_MARK, LCD_DATA1_MARK, LCD_DATA0_MARK,
-	PINMUX_MARK_END,
-};
-
-static const u16 pinmux_data[] = {
-	/* PA */
-	PINMUX_DATA(PA7_DATA, PA7_IN),
-	PINMUX_DATA(PA6_DATA, PA6_IN),
-	PINMUX_DATA(PA5_DATA, PA5_IN),
-	PINMUX_DATA(PA4_DATA, PA4_IN),
-	PINMUX_DATA(PA3_DATA, PA3_IN),
-	PINMUX_DATA(PA2_DATA, PA2_IN),
-	PINMUX_DATA(PA1_DATA, PA1_IN),
-	PINMUX_DATA(PA0_DATA, PA0_IN),
-
-	/* PB */
-	PINMUX_DATA(PB12_DATA, PB12MD_00, FORCE_OUT),
-	PINMUX_DATA(WDTOVF_MARK, PB12MD_01),
-	PINMUX_DATA(IRQOUT_MARK, PB12MD_10, PB12IRQ_00),
-	PINMUX_DATA(REFOUT_MARK, PB12MD_10, PB12IRQ_01),
-	PINMUX_DATA(IRQOUT_REFOUT_MARK, PB12MD_10, PB12IRQ_10),
-	PINMUX_DATA(UBCTRG_MARK, PB12MD_11),
-
-	PINMUX_DATA(PB11_DATA, PB11MD_0, PB11_IN, PB11_OUT),
-	PINMUX_DATA(CTX1_MARK, PB11MD_1),
-
-	PINMUX_DATA(PB10_DATA, PB10MD_0, PB10_IN, PB10_OUT),
-	PINMUX_DATA(CRX1_MARK, PB10MD_1),
-
-	PINMUX_DATA(PB9_DATA, PB9MD_00, PB9_IN, PB9_OUT),
-	PINMUX_DATA(CTX0_MARK, PB9MD_01),
-	PINMUX_DATA(CTX0_CTX1_MARK, PB9MD_10),
-
-	PINMUX_DATA(PB8_DATA, PB8MD_00, PB8_IN, PB8_OUT),
-	PINMUX_DATA(CRX0_MARK, PB8MD_01),
-	PINMUX_DATA(CRX0_CRX1_MARK, PB8MD_10),
-
-	PINMUX_DATA(PB7_DATA, PB7MD_00, FORCE_IN),
-	PINMUX_DATA(SDA3_MARK, PB7MD_01),
-	PINMUX_DATA(PINT7_PB_MARK, PB7MD_10),
-	PINMUX_DATA(IRQ7_PB_MARK, PB7MD_11),
-
-	PINMUX_DATA(PB6_DATA, PB6MD_00, FORCE_IN),
-	PINMUX_DATA(SCL3_MARK, PB6MD_01),
-	PINMUX_DATA(PINT6_PB_MARK, PB6MD_10),
-	PINMUX_DATA(IRQ6_PB_MARK, PB6MD_11),
-
-	PINMUX_DATA(PB5_DATA, PB5MD_00, FORCE_IN),
-	PINMUX_DATA(SDA2_MARK, PB6MD_01),
-	PINMUX_DATA(PINT5_PB_MARK, PB6MD_10),
-	PINMUX_DATA(IRQ5_PB_MARK, PB6MD_11),
-
-	PINMUX_DATA(PB4_DATA, PB4MD_00, FORCE_IN),
-	PINMUX_DATA(SCL2_MARK, PB4MD_01),
-	PINMUX_DATA(PINT4_PB_MARK, PB4MD_10),
-	PINMUX_DATA(IRQ4_PB_MARK, PB4MD_11),
-
-	PINMUX_DATA(PB3_DATA, PB3MD_00, FORCE_IN),
-	PINMUX_DATA(SDA1_MARK, PB3MD_01),
-	PINMUX_DATA(PINT3_PB_MARK, PB3MD_10),
-	PINMUX_DATA(IRQ3_PB_MARK, PB3MD_11),
-
-	PINMUX_DATA(PB2_DATA, PB2MD_00, FORCE_IN),
-	PINMUX_DATA(SCL1_MARK, PB2MD_01),
-	PINMUX_DATA(PINT2_PB_MARK, PB2MD_10),
-	PINMUX_DATA(IRQ2_PB_MARK, PB2MD_11),
-
-	PINMUX_DATA(PB1_DATA, PB1MD_00, FORCE_IN),
-	PINMUX_DATA(SDA0_MARK, PB1MD_01),
-	PINMUX_DATA(PINT1_PB_MARK, PB1MD_10),
-	PINMUX_DATA(IRQ1_PB_MARK, PB1MD_11),
-
-	PINMUX_DATA(PB0_DATA, PB0MD_00, FORCE_IN),
-	PINMUX_DATA(SCL0_MARK, PB0MD_01),
-	PINMUX_DATA(PINT0_PB_MARK, PB0MD_10),
-	PINMUX_DATA(IRQ0_PB_MARK, PB0MD_11),
-
-	/* PC */
-	PINMUX_DATA(PC14_DATA, PC14MD_0, PC14_IN, PC14_OUT),
-	PINMUX_DATA(WAIT_MARK, PC14MD_1),
-
-	PINMUX_DATA(PC13_DATA, PC13MD_0, PC13_IN, PC13_OUT),
-	PINMUX_DATA(RDWR_MARK, PC13MD_1),
-
-	PINMUX_DATA(PC12_DATA, PC12MD_0, PC12_IN, PC12_OUT),
-	PINMUX_DATA(CKE_MARK, PC12MD_1),
-
-	PINMUX_DATA(PC11_DATA, PC11MD_00, PC11_IN, PC11_OUT),
-	PINMUX_DATA(CASU_MARK, PC11MD_01),
-	PINMUX_DATA(BREQ_MARK, PC11MD_10),
-
-	PINMUX_DATA(PC10_DATA, PC10MD_00, PC10_IN, PC10_OUT),
-	PINMUX_DATA(RASU_MARK, PC10MD_01),
-	PINMUX_DATA(BACK_MARK, PC10MD_10),
-
-	PINMUX_DATA(PC9_DATA, PC9MD_0, PC9_IN, PC9_OUT),
-	PINMUX_DATA(CASL_MARK, PC9MD_1),
-
-	PINMUX_DATA(PC8_DATA, PC8MD_0, PC8_IN, PC8_OUT),
-	PINMUX_DATA(RASL_MARK, PC8MD_1),
-
-	PINMUX_DATA(PC7_DATA, PC7MD_0, PC7_IN, PC7_OUT),
-	PINMUX_DATA(WE3_DQMUU_AH_ICIO_WR_MARK, PC7MD_1),
-
-	PINMUX_DATA(PC6_DATA, PC6MD_0, PC6_IN, PC6_OUT),
-	PINMUX_DATA(WE2_DQMUL_ICIORD_MARK, PC6MD_1),
-
-	PINMUX_DATA(PC5_DATA, PC5MD_0, PC5_IN, PC5_OUT),
-	PINMUX_DATA(WE1_DQMLU_WE_MARK, PC5MD_1),
-
-	PINMUX_DATA(PC4_DATA, PC4MD_0, PC4_IN, PC4_OUT),
-	PINMUX_DATA(WE0_DQMLL_MARK, PC4MD_1),
-
-	PINMUX_DATA(PC3_DATA, PC3MD_0, PC3_IN, PC3_OUT),
-	PINMUX_DATA(CS3_MARK, PC3MD_1),
-
-	PINMUX_DATA(PC2_DATA, PC2MD_0, PC2_IN, PC2_OUT),
-	PINMUX_DATA(CS2_MARK, PC2MD_1),
-
-	PINMUX_DATA(PC1_DATA, PC1MD_0, PC1_IN, PC1_OUT),
-	PINMUX_DATA(A1_MARK, PC1MD_1),
-
-	PINMUX_DATA(PC0_DATA, PC0MD_00, PC0_IN, PC0_OUT),
-	PINMUX_DATA(A0_MARK, PC0MD_01),
-	PINMUX_DATA(CS7_MARK, PC0MD_10),
-
-	/* PD */
-	PINMUX_DATA(PD15_DATA, PD15MD_000, PD15_IN, PD15_OUT),
-	PINMUX_DATA(D31_MARK, PD15MD_001),
-	PINMUX_DATA(PINT7_PD_MARK, PD15MD_010),
-	PINMUX_DATA(ADTRG_PD_MARK, PD15MD_100),
-	PINMUX_DATA(TIOC4D_MARK, PD15MD_101),
-
-	PINMUX_DATA(PD14_DATA, PD14MD_000, PD14_IN, PD14_OUT),
-	PINMUX_DATA(D30_MARK, PD14MD_001),
-	PINMUX_DATA(PINT6_PD_MARK, PD14MD_010),
-	PINMUX_DATA(TIOC4C_MARK, PD14MD_101),
-
-	PINMUX_DATA(PD13_DATA, PD13MD_000, PD13_IN, PD13_OUT),
-	PINMUX_DATA(D29_MARK, PD13MD_001),
-	PINMUX_DATA(PINT5_PD_MARK, PD13MD_010),
-	PINMUX_DATA(TEND1_PD_MARK, PD13MD_100),
-	PINMUX_DATA(TIOC4B_MARK, PD13MD_101),
-
-	PINMUX_DATA(PD12_DATA, PD12MD_000, PD12_IN, PD12_OUT),
-	PINMUX_DATA(D28_MARK, PD12MD_001),
-	PINMUX_DATA(PINT4_PD_MARK, PD12MD_010),
-	PINMUX_DATA(DACK1_PD_MARK, PD12MD_100),
-	PINMUX_DATA(TIOC4A_MARK, PD12MD_101),
-
-	PINMUX_DATA(PD11_DATA, PD11MD_000, PD11_IN, PD11_OUT),
-	PINMUX_DATA(D27_MARK, PD11MD_001),
-	PINMUX_DATA(PINT3_PD_MARK, PD11MD_010),
-	PINMUX_DATA(DREQ1_PD_MARK, PD11MD_100),
-	PINMUX_DATA(TIOC3D_MARK, PD11MD_101),
-
-	PINMUX_DATA(PD10_DATA, PD10MD_000, PD10_IN, PD10_OUT),
-	PINMUX_DATA(D26_MARK, PD10MD_001),
-	PINMUX_DATA(PINT2_PD_MARK, PD10MD_010),
-	PINMUX_DATA(TEND0_PD_MARK, PD10MD_100),
-	PINMUX_DATA(TIOC3C_MARK, PD10MD_101),
-
-	PINMUX_DATA(PD9_DATA, PD9MD_000, PD9_IN, PD9_OUT),
-	PINMUX_DATA(D25_MARK, PD9MD_001),
-	PINMUX_DATA(PINT1_PD_MARK, PD9MD_010),
-	PINMUX_DATA(DACK0_PD_MARK, PD9MD_100),
-	PINMUX_DATA(TIOC3B_MARK, PD9MD_101),
-
-	PINMUX_DATA(PD8_DATA, PD8MD_000, PD8_IN, PD8_OUT),
-	PINMUX_DATA(D24_MARK, PD8MD_001),
-	PINMUX_DATA(PINT0_PD_MARK, PD8MD_010),
-	PINMUX_DATA(DREQ0_PD_MARK, PD8MD_100),
-	PINMUX_DATA(TIOC3A_MARK, PD8MD_101),
-
-	PINMUX_DATA(PD7_DATA, PD7MD_000, PD7_IN, PD7_OUT),
-	PINMUX_DATA(D23_MARK, PD7MD_001),
-	PINMUX_DATA(IRQ7_PD_MARK, PD7MD_010),
-	PINMUX_DATA(SCS1_PD_MARK, PD7MD_011),
-	PINMUX_DATA(TCLKD_PD_MARK, PD7MD_100),
-	PINMUX_DATA(TIOC2B_MARK, PD7MD_101),
-
-	PINMUX_DATA(PD6_DATA, PD6MD_000, PD6_IN, PD6_OUT),
-	PINMUX_DATA(D22_MARK, PD6MD_001),
-	PINMUX_DATA(IRQ6_PD_MARK, PD6MD_010),
-	PINMUX_DATA(SSO1_PD_MARK, PD6MD_011),
-	PINMUX_DATA(TCLKC_PD_MARK, PD6MD_100),
-	PINMUX_DATA(TIOC2A_MARK, PD6MD_101),
-
-	PINMUX_DATA(PD5_DATA, PD5MD_000, PD5_IN, PD5_OUT),
-	PINMUX_DATA(D21_MARK, PD5MD_001),
-	PINMUX_DATA(IRQ5_PD_MARK, PD5MD_010),
-	PINMUX_DATA(SSI1_PD_MARK, PD5MD_011),
-	PINMUX_DATA(TCLKB_PD_MARK, PD5MD_100),
-	PINMUX_DATA(TIOC1B_MARK, PD5MD_101),
-
-	PINMUX_DATA(PD4_DATA, PD4MD_000, PD4_IN, PD4_OUT),
-	PINMUX_DATA(D20_MARK, PD4MD_001),
-	PINMUX_DATA(IRQ4_PD_MARK, PD4MD_010),
-	PINMUX_DATA(SSCK1_PD_MARK, PD4MD_011),
-	PINMUX_DATA(TCLKA_PD_MARK, PD4MD_100),
-	PINMUX_DATA(TIOC1A_MARK, PD4MD_101),
-
-	PINMUX_DATA(PD3_DATA, PD3MD_000, PD3_IN, PD3_OUT),
-	PINMUX_DATA(D19_MARK, PD3MD_001),
-	PINMUX_DATA(IRQ3_PD_MARK, PD3MD_010),
-	PINMUX_DATA(SCS0_PD_MARK, PD3MD_011),
-	PINMUX_DATA(DACK3_MARK, PD3MD_100),
-	PINMUX_DATA(TIOC0D_MARK, PD3MD_101),
-
-	PINMUX_DATA(PD2_DATA, PD2MD_000, PD2_IN, PD2_OUT),
-	PINMUX_DATA(D18_MARK, PD2MD_001),
-	PINMUX_DATA(IRQ2_PD_MARK, PD2MD_010),
-	PINMUX_DATA(SSO0_PD_MARK, PD2MD_011),
-	PINMUX_DATA(DREQ3_MARK, PD2MD_100),
-	PINMUX_DATA(TIOC0C_MARK, PD2MD_101),
-
-	PINMUX_DATA(PD1_DATA, PD1MD_000, PD1_IN, PD1_OUT),
-	PINMUX_DATA(D17_MARK, PD1MD_001),
-	PINMUX_DATA(IRQ1_PD_MARK, PD1MD_010),
-	PINMUX_DATA(SSI0_PD_MARK, PD1MD_011),
-	PINMUX_DATA(DACK2_MARK, PD1MD_100),
-	PINMUX_DATA(TIOC0B_MARK, PD1MD_101),
-
-	PINMUX_DATA(PD0_DATA, PD0MD_000, PD0_IN, PD0_OUT),
-	PINMUX_DATA(D16_MARK, PD0MD_001),
-	PINMUX_DATA(IRQ0_PD_MARK, PD0MD_010),
-	PINMUX_DATA(SSCK0_PD_MARK, PD0MD_011),
-	PINMUX_DATA(DREQ2_MARK, PD0MD_100),
-	PINMUX_DATA(TIOC0A_MARK, PD0MD_101),
-
-	/* PE */
-	PINMUX_DATA(PE15_DATA, PE15MD_00, PE15_IN, PE15_OUT),
-	PINMUX_DATA(IOIS16_MARK, PE15MD_01),
-	PINMUX_DATA(RTS3_MARK, PE15MD_11),
-
-	PINMUX_DATA(PE14_DATA, PE14MD_00, PE14_IN, PE14_OUT),
-	PINMUX_DATA(CS1_MARK, PE14MD_01),
-	PINMUX_DATA(CTS3_MARK, PE14MD_11),
-
-	PINMUX_DATA(PE13_DATA, PE13MD_00, PE13_IN, PE13_OUT),
-	PINMUX_DATA(TXD3_MARK, PE13MD_11),
-
-	PINMUX_DATA(PE12_DATA, PE12MD_00, PE12_IN, PE12_OUT),
-	PINMUX_DATA(RXD3_MARK, PE12MD_11),
-
-	PINMUX_DATA(PE11_DATA, PE11MD_000, PE11_IN, PE11_OUT),
-	PINMUX_DATA(CS6_CE1B_MARK, PE11MD_001),
-	PINMUX_DATA(IRQ7_PE_MARK, PE11MD_010),
-	PINMUX_DATA(TEND1_PE_MARK, PE11MD_100),
-
-	PINMUX_DATA(PE10_DATA, PE10MD_000, PE10_IN, PE10_OUT),
-	PINMUX_DATA(CE2B_MARK, PE10MD_001),
-	PINMUX_DATA(IRQ6_PE_MARK, PE10MD_010),
-	PINMUX_DATA(TEND0_PE_MARK, PE10MD_100),
-
-	PINMUX_DATA(PE9_DATA, PE9MD_00, PE9_IN, PE9_OUT),
-	PINMUX_DATA(CS5_CE1A_MARK, PE9MD_01),
-	PINMUX_DATA(IRQ5_PE_MARK, PE9MD_10),
-	PINMUX_DATA(SCK3_MARK, PE9MD_11),
-
-	PINMUX_DATA(PE8_DATA, PE8MD_00, PE8_IN, PE8_OUT),
-	PINMUX_DATA(CE2A_MARK, PE8MD_01),
-	PINMUX_DATA(IRQ4_PE_MARK, PE8MD_10),
-	PINMUX_DATA(SCK2_MARK, PE8MD_11),
-
-	PINMUX_DATA(PE7_DATA, PE7MD_000, PE7_IN, PE7_OUT),
-	PINMUX_DATA(FRAME_MARK, PE7MD_001),
-	PINMUX_DATA(IRQ3_PE_MARK, PE7MD_010),
-	PINMUX_DATA(TXD2_MARK, PE7MD_011),
-	PINMUX_DATA(DACK1_PE_MARK, PE7MD_100),
-
-	PINMUX_DATA(PE6_DATA, PE6MD_000, PE6_IN, PE6_OUT),
-	PINMUX_DATA(A25_MARK, PE6MD_001),
-	PINMUX_DATA(IRQ2_PE_MARK, PE6MD_010),
-	PINMUX_DATA(RXD2_MARK, PE6MD_011),
-	PINMUX_DATA(DREQ1_PE_MARK, PE6MD_100),
-
-	PINMUX_DATA(PE5_DATA, PE5MD_000, PE5_IN, PE5_OUT),
-	PINMUX_DATA(A24_MARK, PE5MD_001),
-	PINMUX_DATA(IRQ1_PE_MARK, PE5MD_010),
-	PINMUX_DATA(TXD1_MARK, PE5MD_011),
-	PINMUX_DATA(DACK0_PE_MARK, PE5MD_100),
-
-	PINMUX_DATA(PE4_DATA, PE4MD_000, PE4_IN, PE4_OUT),
-	PINMUX_DATA(A23_MARK, PE4MD_001),
-	PINMUX_DATA(IRQ0_PE_MARK, PE4MD_010),
-	PINMUX_DATA(RXD1_MARK, PE4MD_011),
-	PINMUX_DATA(DREQ0_PE_MARK, PE4MD_100),
-
-	PINMUX_DATA(PE3_DATA, PE3MD_00, PE3_IN, PE3_OUT),
-	PINMUX_DATA(A22_MARK, PE3MD_01),
-	PINMUX_DATA(SCK1_MARK, PE3MD_11),
-
-	PINMUX_DATA(PE2_DATA, PE2MD_00, PE2_IN, PE2_OUT),
-	PINMUX_DATA(A21_MARK, PE2MD_01),
-	PINMUX_DATA(SCK0_MARK, PE2MD_11),
-
-	PINMUX_DATA(PE1_DATA, PE1MD_00, PE1_IN, PE1_OUT),
-	PINMUX_DATA(CS4_MARK, PE1MD_01),
-	PINMUX_DATA(MRES_MARK, PE1MD_10),
-	PINMUX_DATA(TXD0_MARK, PE1MD_11),
-
-	PINMUX_DATA(PE0_DATA, PE0MD_000, PE0_IN, PE0_OUT),
-	PINMUX_DATA(BS_MARK, PE0MD_001),
-	PINMUX_DATA(RXD0_MARK, PE0MD_011),
-	PINMUX_DATA(ADTRG_PE_MARK, PE0MD_100),
-
-	/* PF */
-	PINMUX_DATA(PF30_DATA, PF30MD_0, PF30_IN, PF30_OUT),
-	PINMUX_DATA(AUDIO_CLK_MARK, PF30MD_1),
-
-	PINMUX_DATA(PF29_DATA, PF29MD_0, PF29_IN, PF29_OUT),
-	PINMUX_DATA(SSIDATA3_MARK, PF29MD_1),
-
-	PINMUX_DATA(PF28_DATA, PF28MD_0, PF28_IN, PF28_OUT),
-	PINMUX_DATA(SSIWS3_MARK, PF28MD_1),
-
-	PINMUX_DATA(PF27_DATA, PF27MD_0, PF27_IN, PF27_OUT),
-	PINMUX_DATA(SSISCK3_MARK, PF27MD_1),
-
-	PINMUX_DATA(PF26_DATA, PF26MD_0, PF26_IN, PF26_OUT),
-	PINMUX_DATA(SSIDATA2_MARK, PF26MD_1),
-
-	PINMUX_DATA(PF25_DATA, PF25MD_0, PF25_IN, PF25_OUT),
-	PINMUX_DATA(SSIWS2_MARK, PF25MD_1),
-
-	PINMUX_DATA(PF24_DATA, PF24MD_0, PF24_IN, PF24_OUT),
-	PINMUX_DATA(SSISCK2_MARK, PF24MD_1),
-
-	PINMUX_DATA(PF23_DATA, PF23MD_00, PF23_IN, PF23_OUT),
-	PINMUX_DATA(SSIDATA1_MARK, PF23MD_01),
-	PINMUX_DATA(LCD_VEPWC_MARK, PF23MD_10),
-
-	PINMUX_DATA(PF22_DATA, PF22MD_00, PF22_IN, PF22_OUT),
-	PINMUX_DATA(SSIWS1_MARK, PF22MD_01),
-	PINMUX_DATA(LCD_VCPWC_MARK, PF22MD_10),
-
-	PINMUX_DATA(PF21_DATA, PF21MD_00, PF21_IN, PF21_OUT),
-	PINMUX_DATA(SSISCK1_MARK, PF21MD_01),
-	PINMUX_DATA(LCD_CLK_MARK, PF21MD_10),
-
-	PINMUX_DATA(PF20_DATA, PF20MD_00, PF20_IN, PF20_OUT),
-	PINMUX_DATA(SSIDATA0_MARK, PF20MD_01),
-	PINMUX_DATA(LCD_FLM_MARK, PF20MD_10),
-
-	PINMUX_DATA(PF19_DATA, PF19MD_00, PF19_IN, PF19_OUT),
-	PINMUX_DATA(SSIWS0_MARK, PF19MD_01),
-	PINMUX_DATA(LCD_M_DISP_MARK, PF19MD_10),
-
-	PINMUX_DATA(PF18_DATA, PF18MD_00, PF18_IN, PF18_OUT),
-	PINMUX_DATA(SSISCK0_MARK, PF18MD_01),
-	PINMUX_DATA(LCD_CL2_MARK, PF18MD_10),
-
-	PINMUX_DATA(PF17_DATA, PF17MD_00, PF17_IN, PF17_OUT),
-	PINMUX_DATA(FCE_MARK, PF17MD_01),
-	PINMUX_DATA(LCD_CL1_MARK, PF17MD_10),
-
-	PINMUX_DATA(PF16_DATA, PF16MD_00, PF16_IN, PF16_OUT),
-	PINMUX_DATA(FRB_MARK, PF16MD_01),
-	PINMUX_DATA(LCD_DON_MARK, PF16MD_10),
-
-	PINMUX_DATA(PF15_DATA, PF15MD_00, PF15_IN, PF15_OUT),
-	PINMUX_DATA(NAF7_MARK, PF15MD_01),
-	PINMUX_DATA(LCD_DATA15_MARK, PF15MD_10),
-
-	PINMUX_DATA(PF14_DATA, PF14MD_00, PF14_IN, PF14_OUT),
-	PINMUX_DATA(NAF6_MARK, PF14MD_01),
-	PINMUX_DATA(LCD_DATA14_MARK, PF14MD_10),
-
-	PINMUX_DATA(PF13_DATA, PF13MD_00, PF13_IN, PF13_OUT),
-	PINMUX_DATA(NAF5_MARK, PF13MD_01),
-	PINMUX_DATA(LCD_DATA13_MARK, PF13MD_10),
-
-	PINMUX_DATA(PF12_DATA, PF12MD_00, PF12_IN, PF12_OUT),
-	PINMUX_DATA(NAF4_MARK, PF12MD_01),
-	PINMUX_DATA(LCD_DATA12_MARK, PF12MD_10),
-
-	PINMUX_DATA(PF11_DATA, PF11MD_00, PF11_IN, PF11_OUT),
-	PINMUX_DATA(NAF3_MARK, PF11MD_01),
-	PINMUX_DATA(LCD_DATA11_MARK, PF11MD_10),
-
-	PINMUX_DATA(PF10_DATA, PF10MD_00, PF10_IN, PF10_OUT),
-	PINMUX_DATA(NAF2_MARK, PF10MD_01),
-	PINMUX_DATA(LCD_DATA10_MARK, PF10MD_10),
-
-	PINMUX_DATA(PF9_DATA, PF9MD_00, PF9_IN, PF9_OUT),
-	PINMUX_DATA(NAF1_MARK, PF9MD_01),
-	PINMUX_DATA(LCD_DATA9_MARK, PF9MD_10),
-
-	PINMUX_DATA(PF8_DATA, PF8MD_00, PF8_IN, PF8_OUT),
-	PINMUX_DATA(NAF0_MARK, PF8MD_01),
-	PINMUX_DATA(LCD_DATA8_MARK, PF8MD_10),
-
-	PINMUX_DATA(PF7_DATA, PF7MD_00, PF7_IN, PF7_OUT),
-	PINMUX_DATA(FSC_MARK, PF7MD_01),
-	PINMUX_DATA(LCD_DATA7_MARK, PF7MD_10),
-	PINMUX_DATA(SCS1_PF_MARK, PF7MD_11),
-
-	PINMUX_DATA(PF6_DATA, PF6MD_00, PF6_IN, PF6_OUT),
-	PINMUX_DATA(FOE_MARK, PF6MD_01),
-	PINMUX_DATA(LCD_DATA6_MARK, PF6MD_10),
-	PINMUX_DATA(SSO1_PF_MARK, PF6MD_11),
-
-	PINMUX_DATA(PF5_DATA, PF5MD_00, PF5_IN, PF5_OUT),
-	PINMUX_DATA(FCDE_MARK, PF5MD_01),
-	PINMUX_DATA(LCD_DATA5_MARK, PF5MD_10),
-	PINMUX_DATA(SSI1_PF_MARK, PF5MD_11),
-
-	PINMUX_DATA(PF4_DATA, PF4MD_00, PF4_IN, PF4_OUT),
-	PINMUX_DATA(FWE_MARK, PF4MD_01),
-	PINMUX_DATA(LCD_DATA4_MARK, PF4MD_10),
-	PINMUX_DATA(SSCK1_PF_MARK, PF4MD_11),
-
-	PINMUX_DATA(PF3_DATA, PF3MD_00, PF3_IN, PF3_OUT),
-	PINMUX_DATA(TCLKD_PF_MARK, PF3MD_01),
-	PINMUX_DATA(LCD_DATA3_MARK, PF3MD_10),
-	PINMUX_DATA(SCS0_PF_MARK, PF3MD_11),
-
-	PINMUX_DATA(PF2_DATA, PF2MD_00, PF2_IN, PF2_OUT),
-	PINMUX_DATA(TCLKC_PF_MARK, PF2MD_01),
-	PINMUX_DATA(LCD_DATA2_MARK, PF2MD_10),
-	PINMUX_DATA(SSO0_PF_MARK, PF2MD_11),
-
-	PINMUX_DATA(PF1_DATA, PF1MD_00, PF1_IN, PF1_OUT),
-	PINMUX_DATA(TCLKB_PF_MARK, PF1MD_01),
-	PINMUX_DATA(LCD_DATA1_MARK, PF1MD_10),
-	PINMUX_DATA(SSI0_PF_MARK, PF1MD_11),
-
-	PINMUX_DATA(PF0_DATA, PF0MD_00, PF0_IN, PF0_OUT),
-	PINMUX_DATA(TCLKA_PF_MARK, PF0MD_01),
-	PINMUX_DATA(LCD_DATA0_MARK, PF0MD_10),
-	PINMUX_DATA(SSCK0_PF_MARK, PF0MD_11),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	/* PA */
-	PINMUX_GPIO(PA7),
-	PINMUX_GPIO(PA6),
-	PINMUX_GPIO(PA5),
-	PINMUX_GPIO(PA4),
-	PINMUX_GPIO(PA3),
-	PINMUX_GPIO(PA2),
-	PINMUX_GPIO(PA1),
-	PINMUX_GPIO(PA0),
-
-	/* PB */
-	PINMUX_GPIO(PB12),
-	PINMUX_GPIO(PB11),
-	PINMUX_GPIO(PB10),
-	PINMUX_GPIO(PB9),
-	PINMUX_GPIO(PB8),
-	PINMUX_GPIO(PB7),
-	PINMUX_GPIO(PB6),
-	PINMUX_GPIO(PB5),
-	PINMUX_GPIO(PB4),
-	PINMUX_GPIO(PB3),
-	PINMUX_GPIO(PB2),
-	PINMUX_GPIO(PB1),
-	PINMUX_GPIO(PB0),
-
-	/* PC */
-	PINMUX_GPIO(PC14),
-	PINMUX_GPIO(PC13),
-	PINMUX_GPIO(PC12),
-	PINMUX_GPIO(PC11),
-	PINMUX_GPIO(PC10),
-	PINMUX_GPIO(PC9),
-	PINMUX_GPIO(PC8),
-	PINMUX_GPIO(PC7),
-	PINMUX_GPIO(PC6),
-	PINMUX_GPIO(PC5),
-	PINMUX_GPIO(PC4),
-	PINMUX_GPIO(PC3),
-	PINMUX_GPIO(PC2),
-	PINMUX_GPIO(PC1),
-	PINMUX_GPIO(PC0),
-
-	/* PD */
-	PINMUX_GPIO(PD15),
-	PINMUX_GPIO(PD14),
-	PINMUX_GPIO(PD13),
-	PINMUX_GPIO(PD12),
-	PINMUX_GPIO(PD11),
-	PINMUX_GPIO(PD10),
-	PINMUX_GPIO(PD9),
-	PINMUX_GPIO(PD8),
-	PINMUX_GPIO(PD7),
-	PINMUX_GPIO(PD6),
-	PINMUX_GPIO(PD5),
-	PINMUX_GPIO(PD4),
-	PINMUX_GPIO(PD3),
-	PINMUX_GPIO(PD2),
-	PINMUX_GPIO(PD1),
-	PINMUX_GPIO(PD0),
-
-	/* PE */
-	PINMUX_GPIO(PE15),
-	PINMUX_GPIO(PE14),
-	PINMUX_GPIO(PE13),
-	PINMUX_GPIO(PE12),
-	PINMUX_GPIO(PE11),
-	PINMUX_GPIO(PE10),
-	PINMUX_GPIO(PE9),
-	PINMUX_GPIO(PE8),
-	PINMUX_GPIO(PE7),
-	PINMUX_GPIO(PE6),
-	PINMUX_GPIO(PE5),
-	PINMUX_GPIO(PE4),
-	PINMUX_GPIO(PE3),
-	PINMUX_GPIO(PE2),
-	PINMUX_GPIO(PE1),
-	PINMUX_GPIO(PE0),
-
-	/* PF */
-	PINMUX_GPIO(PF30),
-	PINMUX_GPIO(PF29),
-	PINMUX_GPIO(PF28),
-	PINMUX_GPIO(PF27),
-	PINMUX_GPIO(PF26),
-	PINMUX_GPIO(PF25),
-	PINMUX_GPIO(PF24),
-	PINMUX_GPIO(PF23),
-	PINMUX_GPIO(PF22),
-	PINMUX_GPIO(PF21),
-	PINMUX_GPIO(PF20),
-	PINMUX_GPIO(PF19),
-	PINMUX_GPIO(PF18),
-	PINMUX_GPIO(PF17),
-	PINMUX_GPIO(PF16),
-	PINMUX_GPIO(PF15),
-	PINMUX_GPIO(PF14),
-	PINMUX_GPIO(PF13),
-	PINMUX_GPIO(PF12),
-	PINMUX_GPIO(PF11),
-	PINMUX_GPIO(PF10),
-	PINMUX_GPIO(PF9),
-	PINMUX_GPIO(PF8),
-	PINMUX_GPIO(PF7),
-	PINMUX_GPIO(PF6),
-	PINMUX_GPIO(PF5),
-	PINMUX_GPIO(PF4),
-	PINMUX_GPIO(PF3),
-	PINMUX_GPIO(PF2),
-	PINMUX_GPIO(PF1),
-	PINMUX_GPIO(PF0),
-};
-
-#define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-	/* INTC */
-	GPIO_FN(PINT7_PB),
-	GPIO_FN(PINT6_PB),
-	GPIO_FN(PINT5_PB),
-	GPIO_FN(PINT4_PB),
-	GPIO_FN(PINT3_PB),
-	GPIO_FN(PINT2_PB),
-	GPIO_FN(PINT1_PB),
-	GPIO_FN(PINT0_PB),
-	GPIO_FN(PINT7_PD),
-	GPIO_FN(PINT6_PD),
-	GPIO_FN(PINT5_PD),
-	GPIO_FN(PINT4_PD),
-	GPIO_FN(PINT3_PD),
-	GPIO_FN(PINT2_PD),
-	GPIO_FN(PINT1_PD),
-	GPIO_FN(PINT0_PD),
-	GPIO_FN(IRQ7_PB),
-	GPIO_FN(IRQ6_PB),
-	GPIO_FN(IRQ5_PB),
-	GPIO_FN(IRQ4_PB),
-	GPIO_FN(IRQ3_PB),
-	GPIO_FN(IRQ2_PB),
-	GPIO_FN(IRQ1_PB),
-	GPIO_FN(IRQ0_PB),
-	GPIO_FN(IRQ7_PD),
-	GPIO_FN(IRQ6_PD),
-	GPIO_FN(IRQ5_PD),
-	GPIO_FN(IRQ4_PD),
-	GPIO_FN(IRQ3_PD),
-	GPIO_FN(IRQ2_PD),
-	GPIO_FN(IRQ1_PD),
-	GPIO_FN(IRQ0_PD),
-	GPIO_FN(IRQ7_PE),
-	GPIO_FN(IRQ6_PE),
-	GPIO_FN(IRQ5_PE),
-	GPIO_FN(IRQ4_PE),
-	GPIO_FN(IRQ3_PE),
-	GPIO_FN(IRQ2_PE),
-	GPIO_FN(IRQ1_PE),
-	GPIO_FN(IRQ0_PE),
-
-	GPIO_FN(WDTOVF),
-	GPIO_FN(IRQOUT),
-	GPIO_FN(REFOUT),
-	GPIO_FN(IRQOUT_REFOUT),
-	GPIO_FN(UBCTRG),
-
-	/* CAN */
-	GPIO_FN(CTX1),
-	GPIO_FN(CRX1),
-	GPIO_FN(CTX0),
-	GPIO_FN(CTX0_CTX1),
-	GPIO_FN(CRX0),
-	GPIO_FN(CRX0_CRX1),
-
-	/* IIC3 */
-	GPIO_FN(SDA3),
-	GPIO_FN(SCL3),
-	GPIO_FN(SDA2),
-	GPIO_FN(SCL2),
-	GPIO_FN(SDA1),
-	GPIO_FN(SCL1),
-	GPIO_FN(SDA0),
-	GPIO_FN(SCL0),
-
-	/* DMAC */
-	GPIO_FN(TEND0_PD),
-	GPIO_FN(TEND0_PE),
-	GPIO_FN(DACK0_PD),
-	GPIO_FN(DACK0_PE),
-	GPIO_FN(DREQ0_PD),
-	GPIO_FN(DREQ0_PE),
-	GPIO_FN(TEND1_PD),
-	GPIO_FN(TEND1_PE),
-	GPIO_FN(DACK1_PD),
-	GPIO_FN(DACK1_PE),
-	GPIO_FN(DREQ1_PD),
-	GPIO_FN(DREQ1_PE),
-	GPIO_FN(DACK2),
-	GPIO_FN(DREQ2),
-	GPIO_FN(DACK3),
-	GPIO_FN(DREQ3),
-
-	/* ADC */
-	GPIO_FN(ADTRG_PD),
-	GPIO_FN(ADTRG_PE),
-
-	/* BSC */
-	GPIO_FN(D31),
-	GPIO_FN(D30),
-	GPIO_FN(D29),
-	GPIO_FN(D28),
-	GPIO_FN(D27),
-	GPIO_FN(D26),
-	GPIO_FN(D25),
-	GPIO_FN(D24),
-	GPIO_FN(D23),
-	GPIO_FN(D22),
-	GPIO_FN(D21),
-	GPIO_FN(D20),
-	GPIO_FN(D19),
-	GPIO_FN(D18),
-	GPIO_FN(D17),
-	GPIO_FN(D16),
-	GPIO_FN(A25),
-	GPIO_FN(A24),
-	GPIO_FN(A23),
-	GPIO_FN(A22),
-	GPIO_FN(A21),
-	GPIO_FN(CS4),
-	GPIO_FN(MRES),
-	GPIO_FN(BS),
-	GPIO_FN(IOIS16),
-	GPIO_FN(CS1),
-	GPIO_FN(CS6_CE1B),
-	GPIO_FN(CE2B),
-	GPIO_FN(CS5_CE1A),
-	GPIO_FN(CE2A),
-	GPIO_FN(FRAME),
-	GPIO_FN(WAIT),
-	GPIO_FN(RDWR),
-	GPIO_FN(CKE),
-	GPIO_FN(CASU),
-	GPIO_FN(BREQ),
-	GPIO_FN(RASU),
-	GPIO_FN(BACK),
-	GPIO_FN(CASL),
-	GPIO_FN(RASL),
-	GPIO_FN(WE3_DQMUU_AH_ICIO_WR),
-	GPIO_FN(WE2_DQMUL_ICIORD),
-	GPIO_FN(WE1_DQMLU_WE),
-	GPIO_FN(WE0_DQMLL),
-	GPIO_FN(CS3),
-	GPIO_FN(CS2),
-	GPIO_FN(A1),
-	GPIO_FN(A0),
-	GPIO_FN(CS7),
-
-	/* TMU */
-	GPIO_FN(TIOC4D),
-	GPIO_FN(TIOC4C),
-	GPIO_FN(TIOC4B),
-	GPIO_FN(TIOC4A),
-	GPIO_FN(TIOC3D),
-	GPIO_FN(TIOC3C),
-	GPIO_FN(TIOC3B),
-	GPIO_FN(TIOC3A),
-	GPIO_FN(TIOC2B),
-	GPIO_FN(TIOC1B),
-	GPIO_FN(TIOC2A),
-	GPIO_FN(TIOC1A),
-	GPIO_FN(TIOC0D),
-	GPIO_FN(TIOC0C),
-	GPIO_FN(TIOC0B),
-	GPIO_FN(TIOC0A),
-	GPIO_FN(TCLKD_PD),
-	GPIO_FN(TCLKC_PD),
-	GPIO_FN(TCLKB_PD),
-	GPIO_FN(TCLKA_PD),
-	GPIO_FN(TCLKD_PF),
-	GPIO_FN(TCLKC_PF),
-	GPIO_FN(TCLKB_PF),
-	GPIO_FN(TCLKA_PF),
-
-	/* SSU */
-	GPIO_FN(SCS0_PD),
-	GPIO_FN(SSO0_PD),
-	GPIO_FN(SSI0_PD),
-	GPIO_FN(SSCK0_PD),
-	GPIO_FN(SCS0_PF),
-	GPIO_FN(SSO0_PF),
-	GPIO_FN(SSI0_PF),
-	GPIO_FN(SSCK0_PF),
-	GPIO_FN(SCS1_PD),
-	GPIO_FN(SSO1_PD),
-	GPIO_FN(SSI1_PD),
-	GPIO_FN(SSCK1_PD),
-	GPIO_FN(SCS1_PF),
-	GPIO_FN(SSO1_PF),
-	GPIO_FN(SSI1_PF),
-	GPIO_FN(SSCK1_PF),
-
-	/* SCIF */
-	GPIO_FN(TXD0),
-	GPIO_FN(RXD0),
-	GPIO_FN(SCK0),
-	GPIO_FN(TXD1),
-	GPIO_FN(RXD1),
-	GPIO_FN(SCK1),
-	GPIO_FN(TXD2),
-	GPIO_FN(RXD2),
-	GPIO_FN(SCK2),
-	GPIO_FN(RTS3),
-	GPIO_FN(CTS3),
-	GPIO_FN(TXD3),
-	GPIO_FN(RXD3),
-	GPIO_FN(SCK3),
-
-	/* SSI */
-	GPIO_FN(AUDIO_CLK),
-	GPIO_FN(SSIDATA3),
-	GPIO_FN(SSIWS3),
-	GPIO_FN(SSISCK3),
-	GPIO_FN(SSIDATA2),
-	GPIO_FN(SSIWS2),
-	GPIO_FN(SSISCK2),
-	GPIO_FN(SSIDATA1),
-	GPIO_FN(SSIWS1),
-	GPIO_FN(SSISCK1),
-	GPIO_FN(SSIDATA0),
-	GPIO_FN(SSIWS0),
-	GPIO_FN(SSISCK0),
-
-	/* FLCTL */
-	GPIO_FN(FCE),
-	GPIO_FN(FRB),
-	GPIO_FN(NAF7),
-	GPIO_FN(NAF6),
-	GPIO_FN(NAF5),
-	GPIO_FN(NAF4),
-	GPIO_FN(NAF3),
-	GPIO_FN(NAF2),
-	GPIO_FN(NAF1),
-	GPIO_FN(NAF0),
-	GPIO_FN(FSC),
-	GPIO_FN(FOE),
-	GPIO_FN(FCDE),
-	GPIO_FN(FWE),
-
-	/* LCDC */
-	GPIO_FN(LCD_VEPWC),
-	GPIO_FN(LCD_VCPWC),
-	GPIO_FN(LCD_CLK),
-	GPIO_FN(LCD_FLM),
-	GPIO_FN(LCD_M_DISP),
-	GPIO_FN(LCD_CL2),
-	GPIO_FN(LCD_CL1),
-	GPIO_FN(LCD_DON),
-	GPIO_FN(LCD_DATA15),
-	GPIO_FN(LCD_DATA14),
-	GPIO_FN(LCD_DATA13),
-	GPIO_FN(LCD_DATA12),
-	GPIO_FN(LCD_DATA11),
-	GPIO_FN(LCD_DATA10),
-	GPIO_FN(LCD_DATA9),
-	GPIO_FN(LCD_DATA8),
-	GPIO_FN(LCD_DATA7),
-	GPIO_FN(LCD_DATA6),
-	GPIO_FN(LCD_DATA5),
-	GPIO_FN(LCD_DATA4),
-	GPIO_FN(LCD_DATA3),
-	GPIO_FN(LCD_DATA2),
-	GPIO_FN(LCD_DATA1),
-	GPIO_FN(LCD_DATA0),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	{ PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		PB11_IN, PB11_OUT,
-		PB10_IN, PB10_OUT,
-		PB9_IN, PB9_OUT,
-		PB8_IN, PB8_OUT,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PBCRL4", 0xfffe3890, 16, 4, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PBCRL3", 0xfffe3892, 16, 4, GROUP(
-		PB11MD_0, PB11MD_1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB10MD_0, PB10MD_1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB9MD_00, PB9MD_01, PB9MD_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB8MD_00, PB8MD_01, PB8MD_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PBCRL2", 0xfffe3894, 16, 4, GROUP(
-		PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PBCRL1", 0xfffe3896, 16, 4, GROUP(
-		PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB2MD_00, PB2MD_01, PB2MD_10, PB2MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB1MD_00, PB1MD_01, PB1MD_10, PB1MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB0MD_00, PB0MD_01, PB0MD_10, PB0MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("IFCR", 0xfffe38a2, 16, 4, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB12IRQ_00, PB12IRQ_01, PB12IRQ_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PCIORL", 0xfffe3906, 16, 1, GROUP(
-		0, 0,
-		PC14_IN, PC14_OUT,
-		PC13_IN, PC13_OUT,
-		PC12_IN, PC12_OUT,
-		PC11_IN, PC11_OUT,
-		PC10_IN, PC10_OUT,
-		PC9_IN, PC9_OUT,
-		PC8_IN, PC8_OUT,
-		PC7_IN, PC7_OUT,
-		PC6_IN, PC6_OUT,
-		PC5_IN, PC5_OUT,
-		PC4_IN, PC4_OUT,
-		PC3_IN, PC3_OUT,
-		PC2_IN, PC2_OUT,
-		PC1_IN, PC1_OUT,
-		PC0_IN, PC0_OUT ))
-	},
-	{ PINMUX_CFG_REG("PCCRL4", 0xfffe3910, 16, 4, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PC14MD_0, PC14MD_1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PC13MD_0, PC13MD_1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PC12MD_0, PC12MD_1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PCCRL3", 0xfffe3912, 16, 4, GROUP(
-		PC11MD_00, PC11MD_01, PC11MD_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PC10MD_00, PC10MD_01, PC10MD_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PC9MD_0, PC9MD_1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PC8MD_0, PC8MD_1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PCCRL2", 0xfffe3914, 16, 4, GROUP(
-		PC7MD_0, PC7MD_1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PC6MD_0, PC6MD_1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PC5MD_0, PC5MD_1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PC4MD_0, PC4MD_1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PCCRL1", 0xfffe3916, 16, 4, GROUP(
-		PC3MD_0, PC3MD_1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PC2MD_0, PC2MD_1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PC1MD_0, PC1MD_1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PC0MD_00, PC0MD_01, PC0MD_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PDIORL", 0xfffe3986, 16, 1, GROUP(
-		PD15_IN, PD15_OUT,
-		PD14_IN, PD14_OUT,
-		PD13_IN, PD13_OUT,
-		PD12_IN, PD12_OUT,
-		PD11_IN, PD11_OUT,
-		PD10_IN, PD10_OUT,
-		PD9_IN, PD9_OUT,
-		PD8_IN, PD8_OUT,
-		PD7_IN, PD7_OUT,
-		PD6_IN, PD6_OUT,
-		PD5_IN, PD5_OUT,
-		PD4_IN, PD4_OUT,
-		PD3_IN, PD3_OUT,
-		PD2_IN, PD2_OUT,
-		PD1_IN, PD1_OUT,
-		PD0_IN, PD0_OUT ))
-	},
-	{ PINMUX_CFG_REG("PDCRL4", 0xfffe3990, 16, 4, GROUP(
-		PD15MD_000, PD15MD_001, PD15MD_010, 0,
-		PD15MD_100, PD15MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD14MD_000, PD14MD_001, PD14MD_010, 0,
-		0, PD14MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD13MD_000, PD13MD_001, PD13MD_010, 0,
-		PD13MD_100, PD13MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD12MD_000, PD12MD_001, PD12MD_010, 0,
-		PD12MD_100, PD12MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PDCRL3", 0xfffe3992, 16, 4, GROUP(
-		PD11MD_000, PD11MD_001, PD11MD_010, 0,
-		PD11MD_100, PD11MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD10MD_000, PD10MD_001, PD10MD_010, 0,
-		PD10MD_100, PD10MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD9MD_000, PD9MD_001, PD9MD_010, 0,
-		PD9MD_100, PD9MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD8MD_000, PD8MD_001, PD8MD_010, 0,
-		PD8MD_100, PD8MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PDCRL2", 0xfffe3994, 16, 4, GROUP(
-		PD7MD_000, PD7MD_001, PD7MD_010, PD7MD_011,
-		PD7MD_100, PD7MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD6MD_000, PD6MD_001, PD6MD_010, PD6MD_011,
-		PD6MD_100, PD6MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD5MD_000, PD5MD_001, PD5MD_010, PD5MD_011,
-		PD5MD_100, PD5MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD4MD_000, PD4MD_001, PD4MD_010, PD4MD_011,
-		PD4MD_100, PD4MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PDCRL1", 0xfffe3996, 16, 4, GROUP(
-		PD3MD_000, PD3MD_001, PD3MD_010, PD3MD_011,
-		PD3MD_100, PD3MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD2MD_000, PD2MD_001, PD2MD_010, PD2MD_011,
-		PD2MD_100, PD2MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD1MD_000, PD1MD_001, PD1MD_010, PD1MD_011,
-		PD1MD_100, PD1MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD0MD_000, PD0MD_001, PD0MD_010, PD0MD_011,
-		PD0MD_100, PD0MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PEIORL", 0xfffe3a06, 16, 1, GROUP(
-		PE15_IN, PE15_OUT,
-		PE14_IN, PE14_OUT,
-		PE13_IN, PE13_OUT,
-		PE12_IN, PE12_OUT,
-		PE11_IN, PE11_OUT,
-		PE10_IN, PE10_OUT,
-		PE9_IN, PE9_OUT,
-		PE8_IN, PE8_OUT,
-		PE7_IN, PE7_OUT,
-		PE6_IN, PE6_OUT,
-		PE5_IN, PE5_OUT,
-		PE4_IN, PE4_OUT,
-		PE3_IN, PE3_OUT,
-		PE2_IN, PE2_OUT,
-		PE1_IN, PE1_OUT,
-		PE0_IN, PE0_OUT ))
-	},
-	{ PINMUX_CFG_REG("PECRL4", 0xfffe3a10, 16, 4, GROUP(
-		PE15MD_00, PE15MD_01, 0, PE15MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PE14MD_00, PE14MD_01, 0, PE14MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PE13MD_00, 0, 0, PE13MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PE12MD_00, 0, 0, PE12MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PECRL3", 0xfffe3a12, 16, 4, GROUP(
-		PE11MD_000, PE11MD_001, PE11MD_010, 0,
-		PE11MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PE10MD_000, PE10MD_001, PE10MD_010, 0,
-		PE10MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PE9MD_00, PE9MD_01, PE9MD_10, PE9MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PE8MD_00, PE8MD_01, PE8MD_10, PE8MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PECRL2", 0xfffe3a14, 16, 4, GROUP(
-		PE7MD_000, PE7MD_001, PE7MD_010, PE7MD_011,
-		PE7MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PE6MD_000, PE6MD_001, PE6MD_010, PE6MD_011,
-		PE6MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PE5MD_000, PE5MD_001, PE5MD_010, PE5MD_011,
-		PE5MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PE4MD_000, PE4MD_001, PE4MD_010, PE4MD_011,
-		PE4MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PECRL1", 0xfffe3a16, 16, 4, GROUP(
-		PE3MD_00, PE3MD_01, 0, PE3MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PE2MD_00, PE2MD_01, 0, PE2MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PE1MD_00, PE1MD_01, PE1MD_10, PE1MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PE0MD_000, PE0MD_001, 0, PE0MD_011,
-		PE0MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PFIORH", 0xfffe3a84, 16, 1, GROUP(
-		0, 0,
-		PF30_IN, PF30_OUT,
-		PF29_IN, PF29_OUT,
-		PF28_IN, PF28_OUT,
-		PF27_IN, PF27_OUT,
-		PF26_IN, PF26_OUT,
-		PF25_IN, PF25_OUT,
-		PF24_IN, PF24_OUT,
-		PF23_IN, PF23_OUT,
-		PF22_IN, PF22_OUT,
-		PF21_IN, PF21_OUT,
-		PF20_IN, PF20_OUT,
-		PF19_IN, PF19_OUT,
-		PF18_IN, PF18_OUT,
-		PF17_IN, PF17_OUT,
-		PF16_IN, PF16_OUT ))
-	},
-	{ PINMUX_CFG_REG("PFIORL", 0xfffe3a86, 16, 1, GROUP(
-		PF15_IN, PF15_OUT,
-		PF14_IN, PF14_OUT,
-		PF13_IN, PF13_OUT,
-		PF12_IN, PF12_OUT,
-		PF11_IN, PF11_OUT,
-		PF10_IN, PF10_OUT,
-		PF9_IN, PF9_OUT,
-		PF8_IN, PF8_OUT,
-		PF7_IN, PF7_OUT,
-		PF6_IN, PF6_OUT,
-		PF5_IN, PF5_OUT,
-		PF4_IN, PF4_OUT,
-		PF3_IN, PF3_OUT,
-		PF2_IN, PF2_OUT,
-		PF1_IN, PF1_OUT,
-		PF0_IN, PF0_OUT ))
-	},
-	{ PINMUX_CFG_REG("PFCRH4", 0xfffe3a88, 16, 4, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF30MD_0, PF30MD_1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF29MD_0, PF29MD_1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF28MD_0, PF28MD_1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PFCRH3", 0xfffe3a8a, 16, 4, GROUP(
-		PF27MD_0, PF27MD_1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF26MD_0, PF26MD_1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF25MD_0, PF25MD_1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF24MD_0, PF24MD_1,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PFCRH2", 0xfffe3a8c, 16, 4, GROUP(
-		PF23MD_00, PF23MD_01, PF23MD_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF22MD_00, PF22MD_01, PF22MD_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF21MD_00, PF21MD_01, PF21MD_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF20MD_00, PF20MD_01, PF20MD_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PFCRH1", 0xfffe3a8e, 16, 4, GROUP(
-		PF19MD_00, PF19MD_01, PF19MD_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF18MD_00, PF18MD_01, PF18MD_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF17MD_00, PF17MD_01, PF17MD_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF16MD_00, PF16MD_01, PF16MD_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PFCRL4", 0xfffe3a90, 16, 4, GROUP(
-		PF15MD_00, PF15MD_01, PF15MD_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF14MD_00, PF14MD_01, PF14MD_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF13MD_00, PF13MD_01, PF13MD_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF12MD_00, PF12MD_01, PF12MD_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PFCRL3", 0xfffe3a92, 16, 4, GROUP(
-		PF11MD_00, PF11MD_01, PF11MD_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF10MD_00, PF10MD_01, PF10MD_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF9MD_00, PF9MD_01, PF9MD_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF8MD_00, PF8MD_01, PF8MD_10, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PFCRL2", 0xfffe3a94, 16, 4, GROUP(
-		PF7MD_00, PF7MD_01, PF7MD_10, PF7MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF6MD_00, PF6MD_01, PF6MD_10, PF6MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF5MD_00, PF5MD_01, PF5MD_10, PF5MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF4MD_00, PF4MD_01, PF4MD_10, PF4MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PFCRL1", 0xfffe3a96, 16, 4, GROUP(
-		PF3MD_00, PF3MD_01, PF3MD_10, PF3MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF2MD_00, PF2MD_01, PF2MD_10, PF2MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF1MD_00, PF1MD_01, PF1MD_10, PF1MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF0MD_00, PF0MD_01, PF0MD_10, PF0MD_11,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{}
-};
-
-static const struct pinmux_data_reg pinmux_data_regs[] = {
-	{ PINMUX_DATA_REG("PADRL", 0xfffe3802, 16, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
-		PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PBDRL", 0xfffe3882, 16, GROUP(
-		0, 0, 0, PB12_DATA,
-		PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
-		PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
-		PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PCDRL", 0xfffe3902, 16, GROUP(
-		0, PC14_DATA, PC13_DATA, PC12_DATA,
-		PC11_DATA, PC10_DATA, PC9_DATA, PC8_DATA,
-		PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
-		PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PDDRL", 0xfffe3982, 16, GROUP(
-		PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
-		PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
-		PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
-		PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PEDRL", 0xfffe3a02, 16, GROUP(
-		PE15_DATA, PE14_DATA, PE13_DATA, PE12_DATA,
-		PE11_DATA, PE10_DATA, PE9_DATA, PE8_DATA,
-		PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
-		PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PFDRH", 0xfffe3a80, 16, GROUP(
-		0, PF30_DATA, PF29_DATA, PF28_DATA,
-		PF27_DATA, PF26_DATA, PF25_DATA, PF24_DATA,
-		PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA,
-		PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA ))
-	},
-	{ PINMUX_DATA_REG("PFDRL", 0xfffe3a82, 16, GROUP(
-		PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA,
-		PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
-		PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
-		PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
-	},
-	{ },
-};
-
-const struct sh_pfc_soc_info sh7203_pinmux_info = {
-	.name = "sh7203_pfc",
-	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
-	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.func_gpios = pinmux_func_gpios,
-	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
-	.cfg_regs = pinmux_config_regs,
-	.data_regs = pinmux_data_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
deleted file mode 100644
index 908837ea487b..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c
+++ /dev/null
@@ -1,2132 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * SH7264 Pinmux
- *
- *  Copyright (C) 2012  Renesas Electronics Europe Ltd
- */
-
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <cpu/sh7264.h>
-
-#include "sh_pfc.h"
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	/* Port A */
-	PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
-	/* Port B */
-	PB22_DATA, PB21_DATA, PB20_DATA,
-	PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA,
-	PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA,
-	PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
-	PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
-	PB3_DATA, PB2_DATA, PB1_DATA,
-	/* Port C */
-	PC10_DATA, PC9_DATA, PC8_DATA,
-	PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
-	PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
-	/* Port D */
-	PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
-	PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
-	PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
-	PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
-	/* Port E */
-	PE5_DATA, PE4_DATA,
-	PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
-	/* Port F */
-	PF12_DATA,
-	PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
-	PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
-	PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
-	/* Port G */
-	PG24_DATA,
-	PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA,
-	PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA,
-	PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA,
-	PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA,
-	PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
-	PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
-	/* Port H */
-	/* NOTE - Port H does not have a Data Register, but PH Data is
-	   connected to PH Port Register */
-	PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
-	PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
-	/* Port I - not on device */
-	/* Port J */
-	PJ12_DATA,
-	PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA,
-	PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
-	PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA,
-	/* Port K */
-	PK12_DATA,
-	PK11_DATA, PK10_DATA, PK9_DATA, PK8_DATA,
-	PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
-	PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA,
-	PINMUX_DATA_END,
-
-	PINMUX_INPUT_BEGIN,
-	FORCE_IN,
-	/* Port A */
-	PA3_IN, PA2_IN, PA1_IN, PA0_IN,
-	/* Port B */
-	PB22_IN, PB21_IN, PB20_IN,
-	PB19_IN, PB18_IN, PB17_IN, PB16_IN,
-	PB15_IN, PB14_IN, PB13_IN, PB12_IN,
-	PB11_IN, PB10_IN, PB9_IN, PB8_IN,
-	PB7_IN, PB6_IN, PB5_IN, PB4_IN,
-	PB3_IN, PB2_IN, PB1_IN,
-	/* Port C */
-	PC10_IN, PC9_IN, PC8_IN,
-	PC7_IN, PC6_IN, PC5_IN, PC4_IN,
-	PC3_IN, PC2_IN, PC1_IN, PC0_IN,
-	/* Port D */
-	PD15_IN, PD14_IN, PD13_IN, PD12_IN,
-	PD11_IN, PD10_IN, PD9_IN, PD8_IN,
-	PD7_IN, PD6_IN, PD5_IN, PD4_IN,
-	PD3_IN, PD2_IN, PD1_IN, PD0_IN,
-	/* Port E */
-	PE5_IN, PE4_IN,
-	PE3_IN, PE2_IN, PE1_IN, PE0_IN,
-	/* Port F */
-	PF12_IN,
-	PF11_IN, PF10_IN, PF9_IN, PF8_IN,
-	PF7_IN, PF6_IN, PF5_IN, PF4_IN,
-	PF3_IN, PF2_IN, PF1_IN, PF0_IN,
-	/* Port G */
-	PG24_IN,
-	PG23_IN, PG22_IN, PG21_IN, PG20_IN,
-	PG19_IN, PG18_IN, PG17_IN, PG16_IN,
-	PG15_IN, PG14_IN, PG13_IN, PG12_IN,
-	PG11_IN, PG10_IN, PG9_IN, PG8_IN,
-	PG7_IN, PG6_IN, PG5_IN, PG4_IN,
-	PG3_IN, PG2_IN, PG1_IN, PG0_IN,
-	/* Port H - Port H does not have a Data Register */
-	/* Port I - not on device */
-	/* Port J */
-	PJ12_IN,
-	PJ11_IN, PJ10_IN, PJ9_IN, PJ8_IN,
-	PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
-	PJ3_IN, PJ2_IN, PJ1_IN, PJ0_IN,
-	/* Port K */
-	PK12_IN,
-	PK11_IN, PK10_IN, PK9_IN, PK8_IN,
-	PK7_IN, PK6_IN, PK5_IN, PK4_IN,
-	PK3_IN, PK2_IN, PK1_IN, PK0_IN,
-	PINMUX_INPUT_END,
-
-	PINMUX_OUTPUT_BEGIN,
-	FORCE_OUT,
-	/* Port A */
-	PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
-	/* Port B */
-	PB22_OUT, PB21_OUT, PB20_OUT,
-	PB19_OUT, PB18_OUT, PB17_OUT, PB16_OUT,
-	PB15_OUT, PB14_OUT, PB13_OUT, PB12_OUT,
-	PB11_OUT, PB10_OUT, PB9_OUT, PB8_OUT,
-	PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
-	PB3_OUT, PB2_OUT, PB1_OUT,
-	/* Port C */
-	PC10_OUT, PC9_OUT, PC8_OUT,
-	PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
-	PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
-	/* Port D */
-	PD15_OUT, PD14_OUT, PD13_OUT, PD12_OUT,
-	PD11_OUT, PD10_OUT, PD9_OUT, PD8_OUT,
-	PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
-	PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
-	/* Port E */
-	PE5_OUT, PE4_OUT,
-	PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
-	/* Port F */
-	PF12_OUT,
-	PF11_OUT, PF10_OUT, PF9_OUT, PF8_OUT,
-	PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
-	PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
-	/* Port G */
-	PG24_OUT,
-	PG23_OUT, PG22_OUT, PG21_OUT, PG20_OUT,
-	PG19_OUT, PG18_OUT, PG17_OUT, PG16_OUT,
-	PG15_OUT, PG14_OUT, PG13_OUT, PG12_OUT,
-	PG11_OUT, PG10_OUT, PG9_OUT, PG8_OUT,
-	PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT,
-	PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT,
-	/* Port H - Port H does not have a Data Register */
-	/* Port I - not on device */
-	/* Port J */
-	PJ12_OUT,
-	PJ11_OUT, PJ10_OUT, PJ9_OUT, PJ8_OUT,
-	PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
-	PJ3_OUT, PJ2_OUT, PJ1_OUT, PJ0_OUT,
-	/* Port K */
-	PK12_OUT,
-	PK11_OUT, PK10_OUT, PK9_OUT, PK8_OUT,
-	PK7_OUT, PK6_OUT, PK5_OUT, PK4_OUT,
-	PK3_OUT, PK2_OUT, PK1_OUT, PK0_OUT,
-	PINMUX_OUTPUT_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	/* Port A */
-	PA3_IOR_IN, PA3_IOR_OUT,
-	PA2_IOR_IN, PA2_IOR_OUT,
-	PA1_IOR_IN, PA1_IOR_OUT,
-	PA0_IOR_IN, PA0_IOR_OUT,
-
-	/* Port B */
-	PB11_IOR_IN, PB11_IOR_OUT,
-	PB10_IOR_IN, PB10_IOR_OUT,
-	PB9_IOR_IN, PB9_IOR_OUT,
-	PB8_IOR_IN, PB8_IOR_OUT,
-
-	PB22MD_00, PB22MD_01, PB22MD_10,
-	PB21MD_0, PB21MD_1,
-	PB20MD_0, PB20MD_1,
-	PB19MD_00, PB19MD_01, PB19MD_10, PB19MD_11,
-	PB18MD_00, PB18MD_01, PB18MD_10, PB18MD_11,
-	PB17MD_00, PB17MD_01, PB17MD_10, PB17MD_11,
-	PB16MD_00, PB16MD_01, PB16MD_10, PB16MD_11,
-	PB15MD_00, PB15MD_01, PB15MD_10, PB15MD_11,
-	PB14MD_00, PB14MD_01, PB14MD_10, PB14MD_11,
-	PB13MD_00, PB13MD_01, PB13MD_10, PB13MD_11,
-	PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11,
-	PB11MD_00, PB11MD_01, PB11MD_10, PB11MD_11,
-	PB10MD_00, PB10MD_01, PB10MD_10, PB10MD_11,
-	PB9MD_00, PB9MD_01, PB9MD_10, PB9MD_11,
-	PB8MD_00, PB8MD_01, PB8MD_10, PB8MD_11,
-	PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11,
-	PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11,
-	PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11,
-	PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11,
-	PB3MD_0, PB3MD_1,
-	PB2MD_0, PB2MD_1,
-	PB1MD_0, PB1MD_1,
-
-	/* Port C */
-	PC14_IOR_IN, PC14_IOR_OUT,
-	PC13_IOR_IN, PC13_IOR_OUT,
-	PC12_IOR_IN, PC12_IOR_OUT,
-	PC11_IOR_IN, PC11_IOR_OUT,
-	PC10_IOR_IN, PC10_IOR_OUT,
-	PC9_IOR_IN, PC9_IOR_OUT,
-	PC8_IOR_IN, PC8_IOR_OUT,
-	PC7_IOR_IN, PC7_IOR_OUT,
-	PC6_IOR_IN, PC6_IOR_OUT,
-	PC5_IOR_IN, PC5_IOR_OUT,
-	PC4_IOR_IN, PC4_IOR_OUT,
-	PC3_IOR_IN, PC3_IOR_OUT,
-	PC2_IOR_IN, PC2_IOR_OUT,
-	PC1_IOR_IN, PC1_IOR_OUT,
-	PC0_IOR_IN, PC0_IOR_OUT,
-
-	PC10MD_0, PC10MD_1,
-	PC9MD_0, PC9MD_1,
-	PC8MD_00, PC8MD_01, PC8MD_10, PC8MD_11,
-	PC7MD_00, PC7MD_01, PC7MD_10, PC7MD_11,
-	PC6MD_00, PC6MD_01, PC6MD_10, PC6MD_11,
-	PC5MD_00, PC5MD_01, PC5MD_10, PC5MD_11,
-	PC4MD_0, PC4MD_1,
-	PC3MD_0, PC3MD_1,
-	PC2MD_0, PC2MD_1,
-	PC1MD_0, PC1MD_1,
-	PC0MD_0, PC0MD_1,
-
-	/* Port D */
-	PD15_IOR_IN, PD15_IOR_OUT,
-	PD14_IOR_IN, PD14_IOR_OUT,
-	PD13_IOR_IN, PD13_IOR_OUT,
-	PD12_IOR_IN, PD12_IOR_OUT,
-	PD11_IOR_IN, PD11_IOR_OUT,
-	PD10_IOR_IN, PD10_IOR_OUT,
-	PD9_IOR_IN, PD9_IOR_OUT,
-	PD8_IOR_IN, PD8_IOR_OUT,
-	PD7_IOR_IN, PD7_IOR_OUT,
-	PD6_IOR_IN, PD6_IOR_OUT,
-	PD5_IOR_IN, PD5_IOR_OUT,
-	PD4_IOR_IN, PD4_IOR_OUT,
-	PD3_IOR_IN, PD3_IOR_OUT,
-	PD2_IOR_IN, PD2_IOR_OUT,
-	PD1_IOR_IN, PD1_IOR_OUT,
-	PD0_IOR_IN, PD0_IOR_OUT,
-
-	PD15MD_00, PD15MD_01, PD15MD_10, PD15MD_11,
-	PD14MD_00, PD14MD_01, PD14MD_10, PD14MD_11,
-	PD13MD_00, PD13MD_01, PD13MD_10, PD13MD_11,
-	PD12MD_00, PD12MD_01, PD12MD_10, PD12MD_11,
-	PD11MD_00, PD11MD_01, PD11MD_10, PD11MD_11,
-	PD10MD_00, PD10MD_01, PD10MD_10, PD10MD_11,
-	PD9MD_00, PD9MD_01, PD9MD_10, PD9MD_11,
-	PD8MD_00, PD8MD_01, PD8MD_10, PD8MD_11,
-	PD7MD_00, PD7MD_01, PD7MD_10, PD7MD_11,
-	PD6MD_00, PD6MD_01, PD6MD_10, PD6MD_11,
-	PD5MD_00, PD5MD_01, PD5MD_10, PD5MD_11,
-	PD4MD_00, PD4MD_01, PD4MD_10, PD4MD_11,
-	PD3MD_00, PD3MD_01, PD3MD_10, PD3MD_11,
-	PD2MD_00, PD2MD_01, PD2MD_10, PD2MD_11,
-	PD1MD_00, PD1MD_01, PD1MD_10, PD1MD_11,
-	PD0MD_00, PD0MD_01, PD0MD_10, PD0MD_11,
-
-	/* Port E */
-	PE5_IOR_IN, PE5_IOR_OUT,
-	PE4_IOR_IN, PE4_IOR_OUT,
-	PE3_IOR_IN, PE3_IOR_OUT,
-	PE2_IOR_IN, PE2_IOR_OUT,
-	PE1_IOR_IN, PE1_IOR_OUT,
-	PE0_IOR_IN, PE0_IOR_OUT,
-
-	PE5MD_00, PE5MD_01, PE5MD_10, PE5MD_11,
-	PE4MD_00, PE4MD_01, PE4MD_10, PE4MD_11,
-	PE3MD_00, PE3MD_01, PE3MD_10, PE3MD_11,
-	PE2MD_00, PE2MD_01, PE2MD_10, PE2MD_11,
-	PE1MD_000, PE1MD_001, PE1MD_010, PE1MD_011,
-	PE1MD_100, PE1MD_101, PE1MD_110, PE1MD_111,
-	PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11,
-
-	/* Port F */
-	PF12_IOR_IN, PF12_IOR_OUT,
-	PF11_IOR_IN, PF11_IOR_OUT,
-	PF10_IOR_IN, PF10_IOR_OUT,
-	PF9_IOR_IN, PF9_IOR_OUT,
-	PF8_IOR_IN, PF8_IOR_OUT,
-	PF7_IOR_IN, PF7_IOR_OUT,
-	PF6_IOR_IN, PF6_IOR_OUT,
-	PF5_IOR_IN, PF5_IOR_OUT,
-	PF4_IOR_IN, PF4_IOR_OUT,
-	PF3_IOR_IN, PF3_IOR_OUT,
-	PF2_IOR_IN, PF2_IOR_OUT,
-	PF1_IOR_IN, PF1_IOR_OUT,
-	PF0_IOR_IN, PF0_IOR_OUT,
-
-	PF12MD_000, PF12MD_001, PF12MD_010, PF12MD_011,
-	PF12MD_100, PF12MD_101, PF12MD_110, PF12MD_111,
-	PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011,
-	PF11MD_100, PF11MD_101, PF11MD_110, PF11MD_111,
-	PF10MD_000, PF10MD_001, PF10MD_010, PF10MD_011,
-	PF10MD_100, PF10MD_101, PF10MD_110, PF10MD_111,
-	PF9MD_000, PF9MD_001, PF9MD_010, PF9MD_011,
-	PF9MD_100, PF9MD_101, PF9MD_110, PF9MD_111,
-	PF8MD_00, PF8MD_01, PF8MD_10, PF8MD_11,
-	PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011,
-	PF7MD_100, PF7MD_101, PF7MD_110, PF7MD_111,
-	PF6MD_000, PF6MD_001, PF6MD_010, PF6MD_011,
-	PF6MD_100, PF6MD_101, PF6MD_110, PF6MD_111,
-	PF5MD_000, PF5MD_001, PF5MD_010, PF5MD_011,
-	PF5MD_100, PF5MD_101, PF5MD_110, PF5MD_111,
-	PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011,
-	PF4MD_100, PF4MD_101, PF4MD_110, PF4MD_111,
-	PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011,
-	PF3MD_100, PF3MD_101, PF3MD_110, PF3MD_111,
-	PF2MD_000, PF2MD_001, PF2MD_010, PF2MD_011,
-	PF2MD_100, PF2MD_101, PF2MD_110, PF2MD_111,
-	PF1MD_000, PF1MD_001, PF1MD_010, PF1MD_011,
-	PF1MD_100, PF1MD_101, PF1MD_110, PF1MD_111,
-	PF0MD_000, PF0MD_001, PF0MD_010, PF0MD_011,
-	PF0MD_100, PF0MD_101, PF0MD_110, PF0MD_111,
-
-	/* Port G */
-	PG24_IOR_IN, PG24_IOR_OUT,
-	PG23_IOR_IN, PG23_IOR_OUT,
-	PG22_IOR_IN, PG22_IOR_OUT,
-	PG21_IOR_IN, PG21_IOR_OUT,
-	PG20_IOR_IN, PG20_IOR_OUT,
-	PG19_IOR_IN, PG19_IOR_OUT,
-	PG18_IOR_IN, PG18_IOR_OUT,
-	PG17_IOR_IN, PG17_IOR_OUT,
-	PG16_IOR_IN, PG16_IOR_OUT,
-	PG15_IOR_IN, PG15_IOR_OUT,
-	PG14_IOR_IN, PG14_IOR_OUT,
-	PG13_IOR_IN, PG13_IOR_OUT,
-	PG12_IOR_IN, PG12_IOR_OUT,
-	PG11_IOR_IN, PG11_IOR_OUT,
-	PG10_IOR_IN, PG10_IOR_OUT,
-	PG9_IOR_IN, PG9_IOR_OUT,
-	PG8_IOR_IN, PG8_IOR_OUT,
-	PG7_IOR_IN, PG7_IOR_OUT,
-	PG6_IOR_IN, PG6_IOR_OUT,
-	PG5_IOR_IN, PG5_IOR_OUT,
-	PG4_IOR_IN, PG4_IOR_OUT,
-	PG3_IOR_IN, PG3_IOR_OUT,
-	PG2_IOR_IN, PG2_IOR_OUT,
-	PG1_IOR_IN, PG1_IOR_OUT,
-	PG0_IOR_IN, PG0_IOR_OUT,
-
-	PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11,
-	PG23MD_00, PG23MD_01, PG23MD_10, PG23MD_11,
-	PG22MD_00, PG22MD_01, PG22MD_10, PG22MD_11,
-	PG21MD_00, PG21MD_01, PG21MD_10, PG21MD_11,
-	PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011,
-	PG20MD_100, PG20MD_101, PG20MD_110, PG20MD_111,
-	PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011,
-	PG19MD_100, PG19MD_101, PG19MD_110, PG19MD_111,
-	PG18MD_000, PG18MD_001, PG18MD_010, PG18MD_011,
-	PG18MD_100, PG18MD_101, PG18MD_110, PG18MD_111,
-	PG17MD_000, PG17MD_001, PG17MD_010, PG17MD_011,
-	PG17MD_100, PG17MD_101, PG17MD_110, PG17MD_111,
-	PG16MD_000, PG16MD_001, PG16MD_010, PG16MD_011,
-	PG16MD_100, PG16MD_101, PG16MD_110, PG16MD_111,
-	PG15MD_000, PG15MD_001, PG15MD_010, PG15MD_011,
-	PG15MD_100, PG15MD_101, PG15MD_110, PG15MD_111,
-	PG14MD_000, PG14MD_001, PG14MD_010, PG14MD_011,
-	PG14MD_100, PG14MD_101, PG14MD_110, PG14MD_111,
-	PG13MD_000, PG13MD_001, PG13MD_010, PG13MD_011,
-	PG13MD_100, PG13MD_101, PG13MD_110, PG13MD_111,
-	PG12MD_000, PG12MD_001, PG12MD_010, PG12MD_011,
-	PG12MD_100, PG12MD_101, PG12MD_110, PG12MD_111,
-	PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011,
-	PG11MD_100, PG11MD_101, PG11MD_110, PG11MD_111,
-	PG10MD_000, PG10MD_001, PG10MD_010, PG10MD_011,
-	PG10MD_100, PG10MD_101, PG10MD_110, PG10MD_111,
-	PG9MD_000, PG9MD_001, PG9MD_010, PG9MD_011,
-	PG9MD_100, PG9MD_101, PG9MD_110, PG9MD_111,
-	PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011,
-	PG8MD_100, PG8MD_101, PG8MD_110, PG8MD_111,
-	PG7MD_00, PG7MD_01, PG7MD_10, PG7MD_11,
-	PG6MD_00, PG6MD_01, PG6MD_10, PG6MD_11,
-	PG5MD_00, PG5MD_01, PG5MD_10, PG5MD_11,
-	PG4MD_00, PG4MD_01, PG4MD_10, PG4MD_11,
-	PG3MD_00, PG3MD_01, PG3MD_10, PG3MD_11,
-	PG2MD_00, PG2MD_01, PG2MD_10, PG2MD_11,
-	PG1MD_00, PG1MD_01, PG1MD_10, PG1MD_11,
-	PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011,
-	PG0MD_100, PG0MD_101, PG0MD_110, PG0MD_111,
-
-	/* Port H */
-	PH7MD_0, PH7MD_1,
-	PH6MD_0, PH6MD_1,
-	PH5MD_0, PH5MD_1,
-	PH4MD_0, PH4MD_1,
-	PH3MD_0, PH3MD_1,
-	PH2MD_0, PH2MD_1,
-	PH1MD_0, PH1MD_1,
-	PH0MD_0, PH0MD_1,
-
-	/* Port I - not on device */
-
-	/* Port J */
-	PJ11_IOR_IN, PJ11_IOR_OUT,
-	PJ10_IOR_IN, PJ10_IOR_OUT,
-	PJ9_IOR_IN, PJ9_IOR_OUT,
-	PJ8_IOR_IN, PJ8_IOR_OUT,
-	PJ7_IOR_IN, PJ7_IOR_OUT,
-	PJ6_IOR_IN, PJ6_IOR_OUT,
-	PJ5_IOR_IN, PJ5_IOR_OUT,
-	PJ4_IOR_IN, PJ4_IOR_OUT,
-	PJ3_IOR_IN, PJ3_IOR_OUT,
-	PJ2_IOR_IN, PJ2_IOR_OUT,
-	PJ1_IOR_IN, PJ1_IOR_OUT,
-	PJ0_IOR_IN, PJ0_IOR_OUT,
-
-	PJ11MD_00, PJ11MD_01, PJ11MD_10, PJ11MD_11,
-	PJ10MD_00, PJ10MD_01, PJ10MD_10, PJ10MD_11,
-	PJ9MD_00, PJ9MD_01, PJ9MD_10, PJ9MD_11,
-	PJ8MD_00, PJ8MD_01, PJ8MD_10, PJ8MD_11,
-	PJ7MD_00, PJ7MD_01, PJ7MD_10, PJ7MD_11,
-	PJ6MD_00, PJ6MD_01, PJ6MD_10, PJ6MD_11,
-	PJ5MD_00, PJ5MD_01, PJ5MD_10, PJ5MD_11,
-	PJ4MD_00, PJ4MD_01, PJ4MD_10, PJ4MD_11,
-	PJ3MD_00, PJ3MD_01, PJ3MD_10, PJ3MD_11,
-	PJ2MD_000, PJ2MD_001, PJ2MD_010, PJ2MD_011,
-	PJ2MD_100, PJ2MD_101, PJ2MD_110, PJ2MD_111,
-	PJ1MD_000, PJ1MD_001, PJ1MD_010, PJ1MD_011,
-	PJ1MD_100, PJ1MD_101, PJ1MD_110, PJ1MD_111,
-	PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011,
-	PJ0MD_100, PJ0MD_101, PJ0MD_110, PJ0MD_111,
-
-	/* Port K */
-	PK11_IOR_IN, PK11_IOR_OUT,
-	PK10_IOR_IN, PK10_IOR_OUT,
-	PK9_IOR_IN, PK9_IOR_OUT,
-	PK8_IOR_IN, PK8_IOR_OUT,
-	PK7_IOR_IN, PK7_IOR_OUT,
-	PK6_IOR_IN, PK6_IOR_OUT,
-	PK5_IOR_IN, PK5_IOR_OUT,
-	PK4_IOR_IN, PK4_IOR_OUT,
-	PK3_IOR_IN, PK3_IOR_OUT,
-	PK2_IOR_IN, PK2_IOR_OUT,
-	PK1_IOR_IN, PK1_IOR_OUT,
-	PK0_IOR_IN, PK0_IOR_OUT,
-
-	PK11MD_00, PK11MD_01, PK11MD_10, PK11MD_11,
-	PK10MD_00, PK10MD_01, PK10MD_10, PK10MD_11,
-	PK9MD_00, PK9MD_01, PK9MD_10, PK9MD_11,
-	PK8MD_00, PK8MD_01, PK8MD_10, PK8MD_11,
-	PK7MD_00, PK7MD_01, PK7MD_10, PK7MD_11,
-	PK6MD_00, PK6MD_01, PK6MD_10, PK6MD_11,
-	PK5MD_00, PK5MD_01, PK5MD_10, PK5MD_11,
-	PK4MD_00, PK4MD_01, PK4MD_10, PK4MD_11,
-	PK3MD_00, PK3MD_01, PK3MD_10, PK3MD_11,
-	PK2MD_00, PK2MD_01, PK2MD_10, PK2MD_11,
-	PK1MD_00, PK1MD_01, PK1MD_10, PK1MD_11,
-	PK0MD_00, PK0MD_01, PK0MD_10, PK0MD_11,
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-	/* Port A */
-
-	/* Port B */
-
-	/* Port C */
-
-	/* Port D */
-
-	/* Port E */
-
-	/* Port F */
-
-	/* Port G */
-
-	/* Port H */
-	PHAN7_MARK, PHAN6_MARK, PHAN5_MARK, PHAN4_MARK,
-	PHAN3_MARK, PHAN2_MARK, PHAN1_MARK, PHAN0_MARK,
-
-	/* Port I - not on device */
-
-	/* Port J */
-
-	/* Port K */
-
-	IRQ7_PC_MARK, IRQ6_PC_MARK, IRQ5_PC_MARK, IRQ4_PC_MARK,
-	IRQ3_PG_MARK, IRQ2_PG_MARK, IRQ1_PJ_MARK, IRQ0_PJ_MARK,
-	IRQ3_PE_MARK, IRQ2_PE_MARK, IRQ1_PE_MARK, IRQ0_PE_MARK,
-
-	PINT7_PG_MARK, PINT6_PG_MARK, PINT5_PG_MARK, PINT4_PG_MARK,
-	PINT3_PG_MARK, PINT2_PG_MARK, PINT1_PG_MARK, PINT0_PG_MARK,
-
-	SD_CD_MARK, SD_D0_MARK, SD_D1_MARK, SD_D2_MARK, SD_D3_MARK,
-	SD_WP_MARK, SD_CLK_MARK, SD_CMD_MARK,
-	CRX0_MARK, CRX1_MARK,
-	CTX0_MARK, CTX1_MARK,
-	CRX0_CRX1_MARK, CTX0_CTX1_MARK,
-
-	PWM1A_MARK, PWM1B_MARK, PWM1C_MARK, PWM1D_MARK,
-	PWM1E_MARK, PWM1F_MARK, PWM1G_MARK, PWM1H_MARK,
-	PWM2A_MARK, PWM2B_MARK, PWM2C_MARK, PWM2D_MARK,
-	PWM2E_MARK, PWM2F_MARK, PWM2G_MARK, PWM2H_MARK,
-	IERXD_MARK, IETXD_MARK,
-	WDTOVF_MARK,
-
-	/* DMAC */
-	TEND0_MARK, DACK0_MARK, DREQ0_MARK,
-	TEND1_MARK, DACK1_MARK, DREQ1_MARK,
-
-	/* ADC */
-	ADTRG_MARK,
-
-	/* BSC */
-	A25_MARK, A24_MARK,
-	A23_MARK, A22_MARK, A21_MARK, A20_MARK,
-	A19_MARK, A18_MARK, A17_MARK, A16_MARK,
-	A15_MARK, A14_MARK, A13_MARK, A12_MARK,
-	A11_MARK, A10_MARK, A9_MARK, A8_MARK,
-	A7_MARK, A6_MARK, A5_MARK, A4_MARK,
-	A3_MARK, A2_MARK, A1_MARK, A0_MARK,
-	D15_MARK, D14_MARK, D13_MARK, D12_MARK,
-	D11_MARK, D10_MARK, D9_MARK, D8_MARK,
-	D7_MARK, D6_MARK, D5_MARK, D4_MARK,
-	D3_MARK, D2_MARK, D1_MARK, D0_MARK,
-	BS_MARK,
-	CS4_MARK, CS3_MARK, CS2_MARK, CS1_MARK, CS0_MARK,
-	CS6CE1B_MARK, CS5CE1A_MARK,
-	CE2A_MARK, CE2B_MARK,
-	RD_MARK, RDWR_MARK,
-	ICIOWRAH_MARK,
-	ICIORD_MARK,
-	WE1DQMUWE_MARK,
-	WE0DQML_MARK,
-	RAS_MARK, CAS_MARK, CKE_MARK,
-	WAIT_MARK, BREQ_MARK, BACK_MARK, IOIS16_MARK,
-
-	/* TMU */
-	TIOC0A_MARK, TIOC0B_MARK, TIOC0C_MARK, TIOC0D_MARK,
-	TIOC1A_MARK, TIOC1B_MARK,
-	TIOC2A_MARK, TIOC2B_MARK,
-	TIOC3A_MARK, TIOC3B_MARK, TIOC3C_MARK, TIOC3D_MARK,
-	TIOC4A_MARK, TIOC4B_MARK, TIOC4C_MARK, TIOC4D_MARK,
-	TCLKA_MARK,	TCLKB_MARK, TCLKC_MARK, TCLKD_MARK,
-
-	/* SCIF */
-	SCK0_MARK, SCK1_MARK, SCK2_MARK, SCK3_MARK,
-	RXD0_MARK, RXD1_MARK, RXD2_MARK, RXD3_MARK,
-	TXD0_MARK, TXD1_MARK, TXD2_MARK, TXD3_MARK,
-	RXD4_MARK, RXD5_MARK, RXD6_MARK, RXD7_MARK,
-	TXD4_MARK, TXD5_MARK, TXD6_MARK, TXD7_MARK,
-	RTS1_MARK, RTS3_MARK,
-	CTS1_MARK, CTS3_MARK,
-
-	/* RSPI */
-	RSPCK0_MARK, RSPCK1_MARK,
-	MOSI0_MARK, MOSI1_MARK,
-	MISO0_PF12_MARK, MISO1_MARK, MISO1_PG19_MARK,
-	SSL00_MARK, SSL10_MARK,
-
-	/* IIC3 */
-	SCL0_MARK, SCL1_MARK, SCL2_MARK,
-	SDA0_MARK, SDA1_MARK, SDA2_MARK,
-
-	/* SSI */
-	SSISCK0_MARK,
-	SSIWS0_MARK,
-	SSITXD0_MARK,
-	SSIRXD0_MARK,
-	SSIWS1_MARK, SSIWS2_MARK, SSIWS3_MARK,
-	SSISCK1_MARK, SSISCK2_MARK, SSISCK3_MARK,
-	SSIDATA1_MARK, SSIDATA2_MARK, SSIDATA3_MARK,
-	AUDIO_CLK_MARK,
-
-	/* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
-	SIOFTXD_MARK, SIOFRXD_MARK, SIOFSYNC_MARK, SIOFSCK_MARK,
-
-	/* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
-	SPDIF_IN_MARK, SPDIF_OUT_MARK,
-
-	/* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
-	FCE_MARK,
-	FRB_MARK,
-
-	/* VDC3 */
-	DV_CLK_MARK,
-	DV_VSYNC_MARK, DV_HSYNC_MARK,
-	DV_DATA7_MARK, DV_DATA6_MARK, DV_DATA5_MARK, DV_DATA4_MARK,
-	DV_DATA3_MARK, DV_DATA2_MARK, DV_DATA1_MARK, DV_DATA0_MARK,
-	LCD_CLK_MARK, LCD_EXTCLK_MARK,
-	LCD_VSYNC_MARK, LCD_HSYNC_MARK, LCD_DE_MARK,
-	LCD_DATA15_MARK, LCD_DATA14_MARK, LCD_DATA13_MARK, LCD_DATA12_MARK,
-	LCD_DATA11_MARK, LCD_DATA10_MARK, LCD_DATA9_MARK, LCD_DATA8_MARK,
-	LCD_DATA7_MARK, LCD_DATA6_MARK, LCD_DATA5_MARK, LCD_DATA4_MARK,
-	LCD_DATA3_MARK, LCD_DATA2_MARK, LCD_DATA1_MARK, LCD_DATA0_MARK,
-	LCD_M_DISP_MARK,
-	PINMUX_MARK_END,
-};
-
-static const u16 pinmux_data[] = {
-	/* Port A */
-	PINMUX_DATA(PA3_DATA, PA3_IN),
-	PINMUX_DATA(PA2_DATA, PA2_IN),
-	PINMUX_DATA(PA1_DATA, PA1_IN),
-	PINMUX_DATA(PA0_DATA, PA0_IN),
-
-	/* Port B */
-	PINMUX_DATA(PB22_DATA, PB22MD_00, PB22_IN, PB22_OUT),
-	PINMUX_DATA(A22_MARK, PB22MD_01),
-	PINMUX_DATA(CS4_MARK, PB22MD_10),
-
-	PINMUX_DATA(PB21_DATA, PB21MD_0, PB21_IN, PB21_OUT),
-	PINMUX_DATA(A21_MARK, PB21MD_1),
-	PINMUX_DATA(A20_MARK, PB20MD_1),
-	PINMUX_DATA(A19_MARK, PB19MD_01),
-	PINMUX_DATA(A18_MARK, PB18MD_01),
-	PINMUX_DATA(A17_MARK, PB17MD_01),
-	PINMUX_DATA(A16_MARK, PB16MD_01),
-	PINMUX_DATA(A15_MARK, PB15MD_01),
-	PINMUX_DATA(A14_MARK, PB14MD_01),
-	PINMUX_DATA(A13_MARK, PB13MD_01),
-	PINMUX_DATA(A12_MARK, PB12MD_01),
-	PINMUX_DATA(A11_MARK, PB11MD_01),
-	PINMUX_DATA(A10_MARK, PB10MD_01),
-	PINMUX_DATA(A9_MARK, PB9MD_01),
-	PINMUX_DATA(A8_MARK, PB8MD_01),
-	PINMUX_DATA(A7_MARK, PB7MD_01),
-	PINMUX_DATA(A6_MARK, PB6MD_01),
-	PINMUX_DATA(A5_MARK, PB5MD_01),
-	PINMUX_DATA(A4_MARK, PB4MD_01),
-	PINMUX_DATA(A3_MARK, PB3MD_1),
-	PINMUX_DATA(A2_MARK, PB2MD_1),
-	PINMUX_DATA(A1_MARK, PB1MD_1),
-
-	/* Port C */
-	PINMUX_DATA(PC10_DATA, PC10MD_0),
-	PINMUX_DATA(TIOC2B_MARK, PC1MD_1),
-	PINMUX_DATA(PC9_DATA, PC9MD_0),
-	PINMUX_DATA(TIOC2A_MARK, PC9MD_1),
-	PINMUX_DATA(PC8_DATA, PC8MD_00),
-	PINMUX_DATA(CS3_MARK, PC8MD_01),
-	PINMUX_DATA(TIOC4D_MARK, PC8MD_10),
-	PINMUX_DATA(IRQ7_PC_MARK, PC8MD_11),
-	PINMUX_DATA(PC7_DATA, PC7MD_00),
-	PINMUX_DATA(CKE_MARK, PC7MD_01),
-	PINMUX_DATA(TIOC4C_MARK, PC7MD_10),
-	PINMUX_DATA(IRQ6_PC_MARK, PC7MD_11),
-	PINMUX_DATA(PC6_DATA, PC6MD_00),
-	PINMUX_DATA(CAS_MARK, PC6MD_01),
-	PINMUX_DATA(TIOC4B_MARK, PC6MD_10),
-	PINMUX_DATA(IRQ5_PC_MARK, PC6MD_11),
-	PINMUX_DATA(PC5_DATA, PC5MD_00),
-	PINMUX_DATA(RAS_MARK, PC5MD_01),
-	PINMUX_DATA(TIOC4A_MARK, PC5MD_10),
-	PINMUX_DATA(IRQ4_PC_MARK, PC5MD_11),
-	PINMUX_DATA(PC4_DATA, PC4MD_0),
-	PINMUX_DATA(WE1DQMUWE_MARK, PC4MD_1),
-	PINMUX_DATA(PC3_DATA, PC3MD_0),
-	PINMUX_DATA(WE0DQML_MARK, PC3MD_1),
-	PINMUX_DATA(PC2_DATA, PC2MD_0),
-	PINMUX_DATA(RDWR_MARK, PC2MD_1),
-	PINMUX_DATA(PC1_DATA, PC1MD_0),
-	PINMUX_DATA(RD_MARK, PC1MD_1),
-	PINMUX_DATA(PC0_DATA, PC0MD_0),
-	PINMUX_DATA(CS0_MARK, PC0MD_1),
-
-	/* Port D */
-	PINMUX_DATA(D15_MARK, PD15MD_01),
-	PINMUX_DATA(D14_MARK, PD14MD_01),
-	PINMUX_DATA(D13_MARK, PD13MD_01),
-	PINMUX_DATA(D12_MARK, PD12MD_01),
-	PINMUX_DATA(D11_MARK, PD11MD_01),
-	PINMUX_DATA(D10_MARK, PD10MD_01),
-	PINMUX_DATA(D9_MARK, PD9MD_01),
-	PINMUX_DATA(D8_MARK, PD8MD_01),
-	PINMUX_DATA(D7_MARK, PD7MD_01),
-	PINMUX_DATA(D6_MARK, PD6MD_01),
-	PINMUX_DATA(D5_MARK, PD5MD_01),
-	PINMUX_DATA(D4_MARK, PD4MD_01),
-	PINMUX_DATA(D3_MARK, PD3MD_01),
-	PINMUX_DATA(D2_MARK, PD2MD_01),
-	PINMUX_DATA(D1_MARK, PD1MD_01),
-	PINMUX_DATA(D0_MARK, PD0MD_01),
-
-	/* Port E */
-	PINMUX_DATA(PE5_DATA, PE5MD_00),
-	PINMUX_DATA(SDA2_MARK, PE5MD_01),
-	PINMUX_DATA(DV_HSYNC_MARK, PE5MD_11),
-
-	PINMUX_DATA(PE4_DATA, PE4MD_00),
-	PINMUX_DATA(SCL2_MARK, PE4MD_01),
-	PINMUX_DATA(DV_VSYNC_MARK, PE4MD_11),
-
-	PINMUX_DATA(PE3_DATA, PE3MD_00),
-	PINMUX_DATA(SDA1_MARK, PE3MD_01),
-	PINMUX_DATA(IRQ3_PE_MARK, PE3MD_11),
-
-	PINMUX_DATA(PE2_DATA, PE2MD_00),
-	PINMUX_DATA(SCL1_MARK, PE2MD_01),
-	PINMUX_DATA(IRQ2_PE_MARK, PE2MD_11),
-
-	PINMUX_DATA(PE1_DATA, PE1MD_000),
-	PINMUX_DATA(SDA0_MARK, PE1MD_001),
-	PINMUX_DATA(IOIS16_MARK, PE1MD_010),
-	PINMUX_DATA(IRQ1_PE_MARK, PE1MD_011),
-	PINMUX_DATA(TCLKA_MARK, PE1MD_100),
-	PINMUX_DATA(ADTRG_MARK, PE1MD_101),
-
-	PINMUX_DATA(PE0_DATA, PE0MD_00),
-	PINMUX_DATA(SCL0_MARK, PE0MD_01),
-	PINMUX_DATA(AUDIO_CLK_MARK, PE0MD_10),
-	PINMUX_DATA(IRQ0_PE_MARK, PE0MD_11),
-
-	/* Port F */
-	PINMUX_DATA(PF12_DATA, PF12MD_000),
-	PINMUX_DATA(BS_MARK, PF12MD_001),
-	PINMUX_DATA(MISO0_PF12_MARK, PF12MD_011),
-	PINMUX_DATA(TIOC3D_MARK, PF12MD_100),
-	PINMUX_DATA(SPDIF_OUT_MARK, PF12MD_101),
-
-	PINMUX_DATA(PF11_DATA, PF11MD_000),
-	PINMUX_DATA(A25_MARK, PF11MD_001),
-	PINMUX_DATA(SSIDATA3_MARK, PF11MD_010),
-	PINMUX_DATA(MOSI0_MARK, PF11MD_011),
-	PINMUX_DATA(TIOC3C_MARK, PF11MD_100),
-	PINMUX_DATA(SPDIF_IN_MARK, PF11MD_101),
-
-	PINMUX_DATA(PF10_DATA, PF10MD_000),
-	PINMUX_DATA(A24_MARK, PF10MD_001),
-	PINMUX_DATA(SSIWS3_MARK, PF10MD_010),
-	PINMUX_DATA(SSL00_MARK, PF10MD_011),
-	PINMUX_DATA(TIOC3B_MARK, PF10MD_100),
-	PINMUX_DATA(FCE_MARK, PF10MD_101),
-
-	PINMUX_DATA(PF9_DATA, PF9MD_000),
-	PINMUX_DATA(A23_MARK, PF9MD_001),
-	PINMUX_DATA(SSISCK3_MARK, PF9MD_010),
-	PINMUX_DATA(RSPCK0_MARK, PF9MD_011),
-	PINMUX_DATA(TIOC3A_MARK, PF9MD_100),
-	PINMUX_DATA(FRB_MARK, PF9MD_101),
-
-	PINMUX_DATA(PF8_DATA, PF8MD_00),
-	PINMUX_DATA(CE2B_MARK, PF8MD_01),
-	PINMUX_DATA(SSIDATA3_MARK, PF8MD_10),
-	PINMUX_DATA(DV_CLK_MARK, PF8MD_11),
-
-	PINMUX_DATA(PF7_DATA, PF7MD_000),
-	PINMUX_DATA(CE2A_MARK, PF7MD_001),
-	PINMUX_DATA(SSIWS3_MARK, PF7MD_010),
-	PINMUX_DATA(DV_DATA7_MARK, PF7MD_011),
-	PINMUX_DATA(TCLKD_MARK, PF7MD_100),
-
-	PINMUX_DATA(PF6_DATA, PF6MD_000),
-	PINMUX_DATA(CS6CE1B_MARK, PF6MD_001),
-	PINMUX_DATA(SSISCK3_MARK, PF6MD_010),
-	PINMUX_DATA(DV_DATA6_MARK, PF6MD_011),
-	PINMUX_DATA(TCLKB_MARK, PF6MD_100),
-
-	PINMUX_DATA(PF5_DATA, PF5MD_000),
-	PINMUX_DATA(CS5CE1A_MARK, PF5MD_001),
-	PINMUX_DATA(SSIDATA2_MARK, PF5MD_010),
-	PINMUX_DATA(DV_DATA5_MARK, PF5MD_011),
-	PINMUX_DATA(TCLKC_MARK, PF5MD_100),
-
-	PINMUX_DATA(PF4_DATA, PF4MD_000),
-	PINMUX_DATA(ICIOWRAH_MARK, PF4MD_001),
-	PINMUX_DATA(SSIWS2_MARK, PF4MD_010),
-	PINMUX_DATA(DV_DATA4_MARK, PF4MD_011),
-	PINMUX_DATA(TXD3_MARK, PF4MD_100),
-
-	PINMUX_DATA(PF3_DATA, PF3MD_000),
-	PINMUX_DATA(ICIORD_MARK, PF3MD_001),
-	PINMUX_DATA(SSISCK2_MARK, PF3MD_010),
-	PINMUX_DATA(DV_DATA3_MARK, PF3MD_011),
-	PINMUX_DATA(RXD3_MARK, PF3MD_100),
-
-	PINMUX_DATA(PF2_DATA, PF2MD_000),
-	PINMUX_DATA(BACK_MARK, PF2MD_001),
-	PINMUX_DATA(SSIDATA1_MARK, PF2MD_010),
-	PINMUX_DATA(DV_DATA2_MARK, PF2MD_011),
-	PINMUX_DATA(TXD2_MARK, PF2MD_100),
-	PINMUX_DATA(DACK0_MARK, PF2MD_101),
-
-	PINMUX_DATA(PF1_DATA, PF1MD_000),
-	PINMUX_DATA(BREQ_MARK, PF1MD_001),
-	PINMUX_DATA(SSIWS1_MARK, PF1MD_010),
-	PINMUX_DATA(DV_DATA1_MARK, PF1MD_011),
-	PINMUX_DATA(RXD2_MARK, PF1MD_100),
-	PINMUX_DATA(DREQ0_MARK, PF1MD_101),
-
-	PINMUX_DATA(PF0_DATA, PF0MD_000),
-	PINMUX_DATA(WAIT_MARK, PF0MD_001),
-	PINMUX_DATA(SSISCK1_MARK, PF0MD_010),
-	PINMUX_DATA(DV_DATA0_MARK, PF0MD_011),
-	PINMUX_DATA(SCK2_MARK, PF0MD_100),
-	PINMUX_DATA(TEND0_MARK, PF0MD_101),
-
-	/* Port G */
-	PINMUX_DATA(PG24_DATA, PG24MD_00),
-	PINMUX_DATA(MOSI0_MARK, PG24MD_01),
-	PINMUX_DATA(TIOC0D_MARK, PG24MD_10),
-
-	PINMUX_DATA(PG23_DATA, PG23MD_00),
-	PINMUX_DATA(MOSI1_MARK, PG23MD_01),
-	PINMUX_DATA(TIOC0C_MARK, PG23MD_10),
-
-	PINMUX_DATA(PG22_DATA, PG22MD_00),
-	PINMUX_DATA(SSL10_MARK, PG22MD_01),
-	PINMUX_DATA(TIOC0B_MARK, PG22MD_10),
-
-	PINMUX_DATA(PG21_DATA, PG21MD_00),
-	PINMUX_DATA(RSPCK1_MARK, PG21MD_01),
-	PINMUX_DATA(TIOC0A_MARK, PG21MD_10),
-
-	PINMUX_DATA(PG20_DATA, PG20MD_000),
-	PINMUX_DATA(LCD_EXTCLK_MARK, PG20MD_001),
-	PINMUX_DATA(MISO1_MARK, PG20MD_011),
-	PINMUX_DATA(TXD7_MARK, PG20MD_100),
-
-	PINMUX_DATA(PG19_DATA, PG19MD_000),
-	PINMUX_DATA(LCD_CLK_MARK, PG19MD_001),
-	PINMUX_DATA(TIOC2B_MARK, PG19MD_010),
-	PINMUX_DATA(MISO1_PG19_MARK, PG19MD_011),
-	PINMUX_DATA(RXD7_MARK, PG19MD_100),
-
-	PINMUX_DATA(PG18_DATA, PG18MD_000),
-	PINMUX_DATA(LCD_DE_MARK, PG18MD_001),
-	PINMUX_DATA(TIOC2A_MARK, PG18MD_010),
-	PINMUX_DATA(SSL10_MARK, PG18MD_011),
-	PINMUX_DATA(TXD6_MARK, PG18MD_100),
-
-	PINMUX_DATA(PG17_DATA, PG17MD_000),
-	PINMUX_DATA(LCD_HSYNC_MARK, PG17MD_001),
-	PINMUX_DATA(TIOC1B_MARK, PG17MD_010),
-	PINMUX_DATA(RSPCK1_MARK, PG17MD_011),
-	PINMUX_DATA(RXD6_MARK, PG17MD_100),
-
-	PINMUX_DATA(PG16_DATA, PG16MD_000),
-	PINMUX_DATA(LCD_VSYNC_MARK, PG16MD_001),
-	PINMUX_DATA(TIOC1A_MARK, PG16MD_010),
-	PINMUX_DATA(TXD3_MARK, PG16MD_011),
-	PINMUX_DATA(CTS1_MARK, PG16MD_100),
-
-	PINMUX_DATA(PG15_DATA, PG15MD_000),
-	PINMUX_DATA(LCD_DATA15_MARK, PG15MD_001),
-	PINMUX_DATA(TIOC0D_MARK, PG15MD_010),
-	PINMUX_DATA(RXD3_MARK, PG15MD_011),
-	PINMUX_DATA(RTS1_MARK, PG15MD_100),
-
-	PINMUX_DATA(PG14_DATA, PG14MD_000),
-	PINMUX_DATA(LCD_DATA14_MARK, PG14MD_001),
-	PINMUX_DATA(TIOC0C_MARK, PG14MD_010),
-	PINMUX_DATA(SCK1_MARK, PG14MD_100),
-
-	PINMUX_DATA(PG13_DATA, PG13MD_000),
-	PINMUX_DATA(LCD_DATA13_MARK, PG13MD_001),
-	PINMUX_DATA(TIOC0B_MARK, PG13MD_010),
-	PINMUX_DATA(TXD1_MARK, PG13MD_100),
-
-	PINMUX_DATA(PG12_DATA, PG12MD_000),
-	PINMUX_DATA(LCD_DATA12_MARK, PG12MD_001),
-	PINMUX_DATA(TIOC0A_MARK, PG12MD_010),
-	PINMUX_DATA(RXD1_MARK, PG12MD_100),
-
-	PINMUX_DATA(PG11_DATA, PG11MD_000),
-	PINMUX_DATA(LCD_DATA11_MARK, PG11MD_001),
-	PINMUX_DATA(SSITXD0_MARK, PG11MD_010),
-	PINMUX_DATA(IRQ3_PG_MARK, PG11MD_011),
-	PINMUX_DATA(TXD5_MARK, PG11MD_100),
-	PINMUX_DATA(SIOFTXD_MARK, PG11MD_101),
-
-	PINMUX_DATA(PG10_DATA, PG10MD_000),
-	PINMUX_DATA(LCD_DATA10_MARK, PG10MD_001),
-	PINMUX_DATA(SSIRXD0_MARK, PG10MD_010),
-	PINMUX_DATA(IRQ2_PG_MARK, PG10MD_011),
-	PINMUX_DATA(RXD5_MARK, PG10MD_100),
-	PINMUX_DATA(SIOFRXD_MARK, PG10MD_101),
-
-	PINMUX_DATA(PG9_DATA, PG9MD_000),
-	PINMUX_DATA(LCD_DATA9_MARK, PG9MD_001),
-	PINMUX_DATA(SSIWS0_MARK, PG9MD_010),
-	PINMUX_DATA(TXD4_MARK, PG9MD_100),
-	PINMUX_DATA(SIOFSYNC_MARK, PG9MD_101),
-
-	PINMUX_DATA(PG8_DATA, PG8MD_000),
-	PINMUX_DATA(LCD_DATA8_MARK, PG8MD_001),
-	PINMUX_DATA(SSISCK0_MARK, PG8MD_010),
-	PINMUX_DATA(RXD4_MARK, PG8MD_100),
-	PINMUX_DATA(SIOFSCK_MARK, PG8MD_101),
-
-	PINMUX_DATA(PG7_DATA, PG7MD_00),
-	PINMUX_DATA(LCD_DATA7_MARK, PG7MD_01),
-	PINMUX_DATA(SD_CD_MARK, PG7MD_10),
-	PINMUX_DATA(PINT7_PG_MARK, PG7MD_11),
-
-	PINMUX_DATA(PG6_DATA, PG7MD_00),
-	PINMUX_DATA(LCD_DATA6_MARK, PG7MD_01),
-	PINMUX_DATA(SD_WP_MARK, PG7MD_10),
-	PINMUX_DATA(PINT6_PG_MARK, PG7MD_11),
-
-	PINMUX_DATA(PG5_DATA, PG5MD_00),
-	PINMUX_DATA(LCD_DATA5_MARK, PG5MD_01),
-	PINMUX_DATA(SD_D1_MARK, PG5MD_10),
-	PINMUX_DATA(PINT5_PG_MARK, PG5MD_11),
-
-	PINMUX_DATA(PG4_DATA, PG4MD_00),
-	PINMUX_DATA(LCD_DATA4_MARK, PG4MD_01),
-	PINMUX_DATA(SD_D0_MARK, PG4MD_10),
-	PINMUX_DATA(PINT4_PG_MARK, PG4MD_11),
-
-	PINMUX_DATA(PG3_DATA, PG3MD_00),
-	PINMUX_DATA(LCD_DATA3_MARK, PG3MD_01),
-	PINMUX_DATA(SD_CLK_MARK, PG3MD_10),
-	PINMUX_DATA(PINT3_PG_MARK, PG3MD_11),
-
-	PINMUX_DATA(PG2_DATA, PG2MD_00),
-	PINMUX_DATA(LCD_DATA2_MARK, PG2MD_01),
-	PINMUX_DATA(SD_CMD_MARK, PG2MD_10),
-	PINMUX_DATA(PINT2_PG_MARK, PG2MD_11),
-
-	PINMUX_DATA(PG1_DATA, PG1MD_00),
-	PINMUX_DATA(LCD_DATA1_MARK, PG1MD_01),
-	PINMUX_DATA(SD_D3_MARK, PG1MD_10),
-	PINMUX_DATA(PINT1_PG_MARK, PG1MD_11),
-
-	PINMUX_DATA(PG0_DATA, PG0MD_000),
-	PINMUX_DATA(LCD_DATA0_MARK, PG0MD_001),
-	PINMUX_DATA(SD_D2_MARK, PG0MD_010),
-	PINMUX_DATA(PINT0_PG_MARK, PG0MD_011),
-	PINMUX_DATA(WDTOVF_MARK, PG0MD_100),
-
-	/* Port H */
-	PINMUX_DATA(PH7_DATA, PH7MD_0),
-	PINMUX_DATA(PHAN7_MARK, PH7MD_1),
-
-	PINMUX_DATA(PH6_DATA, PH6MD_0),
-	PINMUX_DATA(PHAN6_MARK, PH6MD_1),
-
-	PINMUX_DATA(PH5_DATA, PH5MD_0),
-	PINMUX_DATA(PHAN5_MARK, PH5MD_1),
-
-	PINMUX_DATA(PH4_DATA, PH4MD_0),
-	PINMUX_DATA(PHAN4_MARK, PH4MD_1),
-
-	PINMUX_DATA(PH3_DATA, PH3MD_0),
-	PINMUX_DATA(PHAN3_MARK, PH3MD_1),
-
-	PINMUX_DATA(PH2_DATA, PH2MD_0),
-	PINMUX_DATA(PHAN2_MARK, PH2MD_1),
-
-	PINMUX_DATA(PH1_DATA, PH1MD_0),
-	PINMUX_DATA(PHAN1_MARK, PH1MD_1),
-
-	PINMUX_DATA(PH0_DATA, PH0MD_0),
-	PINMUX_DATA(PHAN0_MARK, PH0MD_1),
-
-	/* Port I - not on device */
-
-	/* Port J */
-	PINMUX_DATA(PJ11_DATA, PJ11MD_00),
-	PINMUX_DATA(PWM2H_MARK, PJ11MD_01),
-	PINMUX_DATA(DACK1_MARK, PJ11MD_10),
-
-	PINMUX_DATA(PJ10_DATA, PJ10MD_00),
-	PINMUX_DATA(PWM2G_MARK, PJ10MD_01),
-	PINMUX_DATA(DREQ1_MARK, PJ10MD_10),
-
-	PINMUX_DATA(PJ9_DATA, PJ9MD_00),
-	PINMUX_DATA(PWM2F_MARK, PJ9MD_01),
-	PINMUX_DATA(TEND1_MARK, PJ9MD_10),
-
-	PINMUX_DATA(PJ8_DATA, PJ8MD_00),
-	PINMUX_DATA(PWM2E_MARK, PJ8MD_01),
-	PINMUX_DATA(RTS3_MARK, PJ8MD_10),
-
-	PINMUX_DATA(PJ7_DATA, PJ7MD_00),
-	PINMUX_DATA(TIOC1B_MARK, PJ7MD_01),
-	PINMUX_DATA(CTS3_MARK, PJ7MD_10),
-
-	PINMUX_DATA(PJ6_DATA, PJ6MD_00),
-	PINMUX_DATA(TIOC1A_MARK, PJ6MD_01),
-	PINMUX_DATA(SCK3_MARK, PJ6MD_10),
-
-	PINMUX_DATA(PJ5_DATA, PJ5MD_00),
-	PINMUX_DATA(IERXD_MARK, PJ5MD_01),
-	PINMUX_DATA(TXD3_MARK, PJ5MD_10),
-
-	PINMUX_DATA(PJ4_DATA, PJ4MD_00),
-	PINMUX_DATA(IETXD_MARK, PJ4MD_01),
-	PINMUX_DATA(RXD3_MARK, PJ4MD_10),
-
-	PINMUX_DATA(PJ3_DATA, PJ3MD_00),
-	PINMUX_DATA(CRX1_MARK, PJ3MD_01),
-	PINMUX_DATA(CRX0_CRX1_MARK, PJ3MD_10),
-	PINMUX_DATA(IRQ1_PJ_MARK, PJ3MD_11),
-
-	PINMUX_DATA(PJ2_DATA, PJ2MD_000),
-	PINMUX_DATA(CTX1_MARK, PJ2MD_001),
-	PINMUX_DATA(CTX0_CTX1_MARK, PJ2MD_010),
-	PINMUX_DATA(CS2_MARK, PJ2MD_011),
-	PINMUX_DATA(SCK0_MARK, PJ2MD_100),
-	PINMUX_DATA(LCD_M_DISP_MARK, PJ2MD_101),
-
-	PINMUX_DATA(PJ1_DATA, PJ1MD_000),
-	PINMUX_DATA(CRX0_MARK, PJ1MD_001),
-	PINMUX_DATA(IERXD_MARK, PJ1MD_010),
-	PINMUX_DATA(IRQ0_PJ_MARK, PJ1MD_011),
-	PINMUX_DATA(RXD0_MARK, PJ1MD_100),
-
-	PINMUX_DATA(PJ0_DATA, PJ0MD_000),
-	PINMUX_DATA(CTX0_MARK, PJ0MD_001),
-	PINMUX_DATA(IERXD_MARK, PJ0MD_010),
-	PINMUX_DATA(CS1_MARK, PJ0MD_011),
-	PINMUX_DATA(TXD0_MARK, PJ0MD_100),
-	PINMUX_DATA(A0_MARK, PJ0MD_101),
-
-	/* Port K */
-	PINMUX_DATA(PK11_DATA, PK11MD_00),
-	PINMUX_DATA(PWM2D_MARK, PK11MD_01),
-	PINMUX_DATA(SSITXD0_MARK, PK11MD_10),
-
-	PINMUX_DATA(PK10_DATA, PK10MD_00),
-	PINMUX_DATA(PWM2C_MARK, PK10MD_01),
-	PINMUX_DATA(SSIRXD0_MARK, PK10MD_10),
-
-	PINMUX_DATA(PK9_DATA, PK9MD_00),
-	PINMUX_DATA(PWM2B_MARK, PK9MD_01),
-	PINMUX_DATA(SSIWS0_MARK, PK9MD_10),
-
-	PINMUX_DATA(PK8_DATA, PK8MD_00),
-	PINMUX_DATA(PWM2A_MARK, PK8MD_01),
-	PINMUX_DATA(SSISCK0_MARK, PK8MD_10),
-
-	PINMUX_DATA(PK7_DATA, PK7MD_00),
-	PINMUX_DATA(PWM1H_MARK, PK7MD_01),
-	PINMUX_DATA(SD_CD_MARK, PK7MD_10),
-
-	PINMUX_DATA(PK6_DATA, PK6MD_00),
-	PINMUX_DATA(PWM1G_MARK, PK6MD_01),
-	PINMUX_DATA(SD_WP_MARK, PK6MD_10),
-
-	PINMUX_DATA(PK5_DATA, PK5MD_00),
-	PINMUX_DATA(PWM1F_MARK, PK5MD_01),
-	PINMUX_DATA(SD_D1_MARK, PK5MD_10),
-
-	PINMUX_DATA(PK4_DATA, PK4MD_00),
-	PINMUX_DATA(PWM1E_MARK, PK4MD_01),
-	PINMUX_DATA(SD_D0_MARK, PK4MD_10),
-
-	PINMUX_DATA(PK3_DATA, PK3MD_00),
-	PINMUX_DATA(PWM1D_MARK, PK3MD_01),
-	PINMUX_DATA(SD_CLK_MARK, PK3MD_10),
-
-	PINMUX_DATA(PK2_DATA, PK2MD_00),
-	PINMUX_DATA(PWM1C_MARK, PK2MD_01),
-	PINMUX_DATA(SD_CMD_MARK, PK2MD_10),
-
-	PINMUX_DATA(PK1_DATA, PK1MD_00),
-	PINMUX_DATA(PWM1B_MARK, PK1MD_01),
-	PINMUX_DATA(SD_D3_MARK, PK1MD_10),
-
-	PINMUX_DATA(PK0_DATA, PK0MD_00),
-	PINMUX_DATA(PWM1A_MARK, PK0MD_01),
-	PINMUX_DATA(SD_D2_MARK, PK0MD_10),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	/* Port A */
-	PINMUX_GPIO(PA3),
-	PINMUX_GPIO(PA2),
-	PINMUX_GPIO(PA1),
-	PINMUX_GPIO(PA0),
-
-	/* Port B */
-	PINMUX_GPIO(PB22),
-	PINMUX_GPIO(PB21),
-	PINMUX_GPIO(PB20),
-	PINMUX_GPIO(PB19),
-	PINMUX_GPIO(PB18),
-	PINMUX_GPIO(PB17),
-	PINMUX_GPIO(PB16),
-	PINMUX_GPIO(PB15),
-	PINMUX_GPIO(PB14),
-	PINMUX_GPIO(PB13),
-	PINMUX_GPIO(PB12),
-	PINMUX_GPIO(PB11),
-	PINMUX_GPIO(PB10),
-	PINMUX_GPIO(PB9),
-	PINMUX_GPIO(PB8),
-	PINMUX_GPIO(PB7),
-	PINMUX_GPIO(PB6),
-	PINMUX_GPIO(PB5),
-	PINMUX_GPIO(PB4),
-	PINMUX_GPIO(PB3),
-	PINMUX_GPIO(PB2),
-	PINMUX_GPIO(PB1),
-
-	/* Port C */
-	PINMUX_GPIO(PC10),
-	PINMUX_GPIO(PC9),
-	PINMUX_GPIO(PC8),
-	PINMUX_GPIO(PC7),
-	PINMUX_GPIO(PC6),
-	PINMUX_GPIO(PC5),
-	PINMUX_GPIO(PC4),
-	PINMUX_GPIO(PC3),
-	PINMUX_GPIO(PC2),
-	PINMUX_GPIO(PC1),
-	PINMUX_GPIO(PC0),
-
-	/* Port D */
-	PINMUX_GPIO(PD15),
-	PINMUX_GPIO(PD14),
-	PINMUX_GPIO(PD13),
-	PINMUX_GPIO(PD12),
-	PINMUX_GPIO(PD11),
-	PINMUX_GPIO(PD10),
-	PINMUX_GPIO(PD9),
-	PINMUX_GPIO(PD8),
-	PINMUX_GPIO(PD7),
-	PINMUX_GPIO(PD6),
-	PINMUX_GPIO(PD5),
-	PINMUX_GPIO(PD4),
-	PINMUX_GPIO(PD3),
-	PINMUX_GPIO(PD2),
-	PINMUX_GPIO(PD1),
-	PINMUX_GPIO(PD0),
-
-	/* Port E */
-	PINMUX_GPIO(PE5),
-	PINMUX_GPIO(PE4),
-	PINMUX_GPIO(PE3),
-	PINMUX_GPIO(PE2),
-	PINMUX_GPIO(PE1),
-	PINMUX_GPIO(PE0),
-
-	/* Port F */
-	PINMUX_GPIO(PF12),
-	PINMUX_GPIO(PF11),
-	PINMUX_GPIO(PF10),
-	PINMUX_GPIO(PF9),
-	PINMUX_GPIO(PF8),
-	PINMUX_GPIO(PF7),
-	PINMUX_GPIO(PF6),
-	PINMUX_GPIO(PF5),
-	PINMUX_GPIO(PF4),
-	PINMUX_GPIO(PF3),
-	PINMUX_GPIO(PF2),
-	PINMUX_GPIO(PF1),
-	PINMUX_GPIO(PF0),
-
-	/* Port G */
-	PINMUX_GPIO(PG24),
-	PINMUX_GPIO(PG23),
-	PINMUX_GPIO(PG22),
-	PINMUX_GPIO(PG21),
-	PINMUX_GPIO(PG20),
-	PINMUX_GPIO(PG19),
-	PINMUX_GPIO(PG18),
-	PINMUX_GPIO(PG17),
-	PINMUX_GPIO(PG16),
-	PINMUX_GPIO(PG15),
-	PINMUX_GPIO(PG14),
-	PINMUX_GPIO(PG13),
-	PINMUX_GPIO(PG12),
-	PINMUX_GPIO(PG11),
-	PINMUX_GPIO(PG10),
-	PINMUX_GPIO(PG9),
-	PINMUX_GPIO(PG8),
-	PINMUX_GPIO(PG7),
-	PINMUX_GPIO(PG6),
-	PINMUX_GPIO(PG5),
-	PINMUX_GPIO(PG4),
-	PINMUX_GPIO(PG3),
-	PINMUX_GPIO(PG2),
-	PINMUX_GPIO(PG1),
-	PINMUX_GPIO(PG0),
-
-	/* Port H - Port H does not have a Data Register */
-
-	/* Port I - not on device */
-
-	/* Port J */
-	PINMUX_GPIO(PJ11),
-	PINMUX_GPIO(PJ10),
-	PINMUX_GPIO(PJ9),
-	PINMUX_GPIO(PJ8),
-	PINMUX_GPIO(PJ7),
-	PINMUX_GPIO(PJ6),
-	PINMUX_GPIO(PJ5),
-	PINMUX_GPIO(PJ4),
-	PINMUX_GPIO(PJ3),
-	PINMUX_GPIO(PJ2),
-	PINMUX_GPIO(PJ1),
-	PINMUX_GPIO(PJ0),
-
-	/* Port K */
-	PINMUX_GPIO(PK11),
-	PINMUX_GPIO(PK10),
-	PINMUX_GPIO(PK9),
-	PINMUX_GPIO(PK8),
-	PINMUX_GPIO(PK7),
-	PINMUX_GPIO(PK6),
-	PINMUX_GPIO(PK5),
-	PINMUX_GPIO(PK4),
-	PINMUX_GPIO(PK3),
-	PINMUX_GPIO(PK2),
-	PINMUX_GPIO(PK1),
-	PINMUX_GPIO(PK0),
-};
-
-#define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-	/* INTC */
-	GPIO_FN(PINT7_PG),
-	GPIO_FN(PINT6_PG),
-	GPIO_FN(PINT5_PG),
-	GPIO_FN(PINT4_PG),
-	GPIO_FN(PINT3_PG),
-	GPIO_FN(PINT2_PG),
-	GPIO_FN(PINT1_PG),
-
-	GPIO_FN(IRQ7_PC),
-	GPIO_FN(IRQ6_PC),
-	GPIO_FN(IRQ5_PC),
-	GPIO_FN(IRQ4_PC),
-	GPIO_FN(IRQ3_PG),
-	GPIO_FN(IRQ2_PG),
-	GPIO_FN(IRQ1_PJ),
-	GPIO_FN(IRQ0_PJ),
-	GPIO_FN(IRQ3_PE),
-	GPIO_FN(IRQ2_PE),
-	GPIO_FN(IRQ1_PE),
-	GPIO_FN(IRQ0_PE),
-
-	/* WDT */
-	GPIO_FN(WDTOVF),
-
-	/* CAN */
-	GPIO_FN(CTX1),
-	GPIO_FN(CRX1),
-	GPIO_FN(CTX0),
-	GPIO_FN(CTX0_CTX1),
-	GPIO_FN(CRX0),
-	GPIO_FN(CRX0_CRX1),
-
-	/* DMAC */
-	GPIO_FN(TEND0),
-	GPIO_FN(DACK0),
-	GPIO_FN(DREQ0),
-	GPIO_FN(TEND1),
-	GPIO_FN(DACK1),
-	GPIO_FN(DREQ1),
-
-	/* ADC */
-	GPIO_FN(ADTRG),
-
-	/* BSCh */
-	GPIO_FN(A25),
-	GPIO_FN(A24),
-	GPIO_FN(A23),
-	GPIO_FN(A22),
-	GPIO_FN(A21),
-	GPIO_FN(A20),
-	GPIO_FN(A19),
-	GPIO_FN(A18),
-	GPIO_FN(A17),
-	GPIO_FN(A16),
-	GPIO_FN(A15),
-	GPIO_FN(A14),
-	GPIO_FN(A13),
-	GPIO_FN(A12),
-	GPIO_FN(A11),
-	GPIO_FN(A10),
-	GPIO_FN(A9),
-	GPIO_FN(A8),
-	GPIO_FN(A7),
-	GPIO_FN(A6),
-	GPIO_FN(A5),
-	GPIO_FN(A4),
-	GPIO_FN(A3),
-	GPIO_FN(A2),
-	GPIO_FN(A1),
-	GPIO_FN(A0),
-
-	GPIO_FN(D15),
-	GPIO_FN(D14),
-	GPIO_FN(D13),
-	GPIO_FN(D12),
-	GPIO_FN(D11),
-	GPIO_FN(D10),
-	GPIO_FN(D9),
-	GPIO_FN(D8),
-	GPIO_FN(D7),
-	GPIO_FN(D6),
-	GPIO_FN(D5),
-	GPIO_FN(D4),
-	GPIO_FN(D3),
-	GPIO_FN(D2),
-	GPIO_FN(D1),
-	GPIO_FN(D0),
-
-	GPIO_FN(BS),
-	GPIO_FN(CS4),
-	GPIO_FN(CS3),
-	GPIO_FN(CS2),
-	GPIO_FN(CS1),
-	GPIO_FN(CS0),
-	GPIO_FN(CS6CE1B),
-	GPIO_FN(CS5CE1A),
-	GPIO_FN(CE2A),
-	GPIO_FN(CE2B),
-	GPIO_FN(RD),
-	GPIO_FN(RDWR),
-	GPIO_FN(ICIOWRAH),
-	GPIO_FN(ICIORD),
-	GPIO_FN(WE1DQMUWE),
-	GPIO_FN(WE0DQML),
-	GPIO_FN(RAS),
-	GPIO_FN(CAS),
-	GPIO_FN(CKE),
-	GPIO_FN(WAIT),
-	GPIO_FN(BREQ),
-	GPIO_FN(BACK),
-	GPIO_FN(IOIS16),
-
-	/* TMU */
-	GPIO_FN(TIOC4D),
-	GPIO_FN(TIOC4C),
-	GPIO_FN(TIOC4B),
-	GPIO_FN(TIOC4A),
-	GPIO_FN(TIOC3D),
-	GPIO_FN(TIOC3C),
-	GPIO_FN(TIOC3B),
-	GPIO_FN(TIOC3A),
-	GPIO_FN(TIOC2B),
-	GPIO_FN(TIOC1B),
-	GPIO_FN(TIOC2A),
-	GPIO_FN(TIOC1A),
-	GPIO_FN(TIOC0D),
-	GPIO_FN(TIOC0C),
-	GPIO_FN(TIOC0B),
-	GPIO_FN(TIOC0A),
-	GPIO_FN(TCLKD),
-	GPIO_FN(TCLKC),
-	GPIO_FN(TCLKB),
-	GPIO_FN(TCLKA),
-
-	/* SCIF */
-	GPIO_FN(TXD0),
-	GPIO_FN(RXD0),
-	GPIO_FN(SCK0),
-	GPIO_FN(TXD1),
-	GPIO_FN(RXD1),
-	GPIO_FN(SCK1),
-	GPIO_FN(TXD2),
-	GPIO_FN(RXD2),
-	GPIO_FN(SCK2),
-	GPIO_FN(RTS3),
-	GPIO_FN(CTS3),
-	GPIO_FN(TXD3),
-	GPIO_FN(RXD3),
-	GPIO_FN(SCK3),
-	GPIO_FN(TXD4),
-	GPIO_FN(RXD4),
-	GPIO_FN(TXD5),
-	GPIO_FN(RXD5),
-	GPIO_FN(TXD6),
-	GPIO_FN(RXD6),
-	GPIO_FN(TXD7),
-	GPIO_FN(RXD7),
-	GPIO_FN(RTS1),
-	GPIO_FN(CTS1),
-
-	/* RSPI */
-	GPIO_FN(RSPCK0),
-	GPIO_FN(MOSI0),
-	GPIO_FN(MISO0_PF12),
-	GPIO_FN(MISO1),
-	GPIO_FN(SSL00),
-	GPIO_FN(RSPCK1),
-	GPIO_FN(MOSI1),
-	GPIO_FN(MISO1_PG19),
-	GPIO_FN(SSL10),
-
-	/* IIC3 */
-	GPIO_FN(SCL0),
-	GPIO_FN(SCL1),
-	GPIO_FN(SCL2),
-	GPIO_FN(SDA0),
-	GPIO_FN(SDA1),
-	GPIO_FN(SDA2),
-
-	/* SSI */
-	GPIO_FN(SSISCK0),
-	GPIO_FN(SSIWS0),
-	GPIO_FN(SSITXD0),
-	GPIO_FN(SSIRXD0),
-	GPIO_FN(SSIWS1),
-	GPIO_FN(SSIWS2),
-	GPIO_FN(SSIWS3),
-	GPIO_FN(SSISCK1),
-	GPIO_FN(SSISCK2),
-	GPIO_FN(SSISCK3),
-	GPIO_FN(SSIDATA1),
-	GPIO_FN(SSIDATA2),
-	GPIO_FN(SSIDATA3),
-	GPIO_FN(AUDIO_CLK),
-
-	/* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
-	GPIO_FN(SIOFTXD),
-	GPIO_FN(SIOFRXD),
-	GPIO_FN(SIOFSYNC),
-	GPIO_FN(SIOFSCK),
-
-	/* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
-	GPIO_FN(SPDIF_IN),
-	GPIO_FN(SPDIF_OUT),
-
-	/* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
-	GPIO_FN(FCE),
-	GPIO_FN(FRB),
-
-	/* VDC3 */
-	GPIO_FN(DV_CLK),
-	GPIO_FN(DV_VSYNC),
-	GPIO_FN(DV_HSYNC),
-
-	GPIO_FN(DV_DATA7),
-	GPIO_FN(DV_DATA6),
-	GPIO_FN(DV_DATA5),
-	GPIO_FN(DV_DATA4),
-	GPIO_FN(DV_DATA3),
-	GPIO_FN(DV_DATA2),
-	GPIO_FN(DV_DATA1),
-	GPIO_FN(DV_DATA0),
-
-	GPIO_FN(LCD_CLK),
-	GPIO_FN(LCD_EXTCLK),
-	GPIO_FN(LCD_VSYNC),
-	GPIO_FN(LCD_HSYNC),
-	GPIO_FN(LCD_DE),
-
-	GPIO_FN(LCD_DATA15),
-	GPIO_FN(LCD_DATA14),
-	GPIO_FN(LCD_DATA13),
-	GPIO_FN(LCD_DATA12),
-	GPIO_FN(LCD_DATA11),
-	GPIO_FN(LCD_DATA10),
-	GPIO_FN(LCD_DATA9),
-	GPIO_FN(LCD_DATA8),
-	GPIO_FN(LCD_DATA7),
-	GPIO_FN(LCD_DATA6),
-	GPIO_FN(LCD_DATA5),
-	GPIO_FN(LCD_DATA4),
-	GPIO_FN(LCD_DATA3),
-	GPIO_FN(LCD_DATA2),
-	GPIO_FN(LCD_DATA1),
-	GPIO_FN(LCD_DATA0),
-
-	GPIO_FN(LCD_M_DISP),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	{ PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PA3_IN, PA3_OUT,
-		PA2_IN, PA2_OUT,
-		PA1_IN, PA1_OUT,
-		PA0_IN,	PA0_OUT ))
-	},
-
-	{ PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PB22MD_00, PB22MD_01, PB22MD_10, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PB21MD_0, PB21MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PB20MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-
-	},
-	{ PINMUX_CFG_REG("PBCR4", 0xfffe3826, 16, 4, GROUP(
-		0, PB19MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PB18MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PB17MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PB16MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PBCR3", 0xfffe3828, 16, 4, GROUP(
-		0, PB15MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PB14MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PB13MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PB12MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PBCR2", 0xfffe382a, 16, 4, GROUP(
-		0, PB11MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PB10MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PB9MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PB8MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PBCR1", 0xfffe382c, 16, 4, GROUP(
-		0, PB7MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PB6MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PB5MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PB4MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4, GROUP(
-		0, PB3MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PB2MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PB1MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0,
-		PB22_IN, PB22_OUT,
-		PB21_IN, PB21_OUT,
-		PB20_IN, PB20_OUT,
-		PB19_IN, PB19_OUT,
-		PB18_IN, PB18_OUT,
-		PB17_IN, PB17_OUT,
-		PB16_IN, PB16_OUT ))
-	},
-
-	{ PINMUX_CFG_REG("PBIOR0", 0xfffe3832, 16, 1, GROUP(
-		PB15_IN, PB15_OUT,
-		PB14_IN, PB14_OUT,
-		PB13_IN, PB13_OUT,
-		PB12_IN, PB12_OUT,
-		PB11_IN, PB11_OUT,
-		PB10_IN, PB10_OUT,
-		PB9_IN, PB9_OUT,
-		PB8_IN, PB8_OUT,
-		PB7_IN, PB7_OUT,
-		PB6_IN, PB6_OUT,
-		PB5_IN, PB5_OUT,
-		PB4_IN, PB4_OUT,
-		PB3_IN, PB3_OUT,
-		PB2_IN, PB2_OUT,
-		PB1_IN, PB1_OUT,
-		0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PC10MD_0, PC10MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PC9MD_0, PC9MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PC8MD_00, PC8MD_01, PC8MD_10, PC8MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PCCR1", 0xfffe384c, 16, 4, GROUP(
-		PC7MD_00, PC7MD_01, PC7MD_10, PC7MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PC6MD_00, PC6MD_01, PC6MD_10, PC6MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PC5MD_00, PC5MD_01, PC5MD_10, PC5MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PC4MD_0, PC4MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PCCR0", 0xfffe384e, 16, 4, GROUP(
-		PC3MD_0, PC3MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PC2MD_0, PC2MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PC1MD_0, PC1MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PC0MD_0, PC0MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PCIOR0", 0xfffe3852, 16, 1, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		PC10_IN, PC10_OUT,
-		PC9_IN, PC9_OUT,
-		PC8_IN, PC8_OUT,
-		PC7_IN, PC7_OUT,
-		PC6_IN, PC6_OUT,
-		PC5_IN, PC5_OUT,
-		PC4_IN, PC4_OUT,
-		PC3_IN, PC3_OUT,
-		PC2_IN, PC2_OUT,
-		PC1_IN, PC1_OUT,
-		PC0_IN, PC0_OUT
-	 ))
-	},
-
-	{ PINMUX_CFG_REG("PDCR3", 0xfffe3868, 16, 4, GROUP(
-		0, PD15MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PD14MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PD13MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PD12MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PDCR2", 0xfffe386a, 16, 4, GROUP(
-		0, PD11MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PD10MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PD9MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PD8MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PDCR1", 0xfffe386c, 16, 4, GROUP(
-		0, PD7MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PD6MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PD5MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PD4MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PDCR0", 0xfffe386e, 16, 4, GROUP(
-		0, PD3MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PD2MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PD1MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PD0MD_01, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PDIOR0", 0xfffe3872, 16, 1, GROUP(
-		PD15_IN, PD15_OUT,
-		PD14_IN, PD14_OUT,
-		PD13_IN, PD13_OUT,
-		PD12_IN, PD12_OUT,
-		PD11_IN, PD11_OUT,
-		PD10_IN, PD10_OUT,
-		PD9_IN, PD9_OUT,
-		PD8_IN, PD8_OUT,
-		PD7_IN, PD7_OUT,
-		PD6_IN, PD6_OUT,
-		PD5_IN, PD5_OUT,
-		PD4_IN, PD4_OUT,
-		PD3_IN, PD3_OUT,
-		PD2_IN, PD2_OUT,
-		PD1_IN, PD1_OUT,
-		PD0_IN, PD0_OUT ))
-	},
-
-	{ PINMUX_CFG_REG("PECR1", 0xfffe388c, 16, 4, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PE5MD_00, PE5MD_01, 0, PE5MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PE4MD_00, PE4MD_01, 0, PE4MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PECR0", 0xfffe388e, 16, 4, GROUP(
-		PE3MD_00, PE3MD_01, 0, PE3MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PE2MD_00, PE2MD_01, 0, PE2MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PE1MD_000, PE1MD_001, PE1MD_010, PE1MD_011,
-		PE1MD_100, PE1MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PEIOR0", 0xfffe3892, 16, 1, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0,
-		PE5_IN, PE5_OUT,
-		PE4_IN, PE4_OUT,
-		PE3_IN, PE3_OUT,
-		PE2_IN, PE2_OUT,
-		PE1_IN, PE1_OUT,
-		PE0_IN, PE0_OUT ))
-	},
-
-	{ PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		PF12MD_000, PF12MD_001, 0, PF12MD_011,
-		PF12MD_100, PF12MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PFCR2", 0xfffe38aa, 16, 4, GROUP(
-		PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011,
-		PF11MD_100, PF11MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PF10MD_000, PF10MD_001, PF10MD_010, PF10MD_011,
-		PF10MD_100, PF10MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PF9MD_000, PF9MD_001, PF9MD_010, PF9MD_011,
-		PF9MD_100, PF9MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PF8MD_00, PF8MD_01, PF8MD_10, PF8MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PFCR1", 0xfffe38ac, 16, 4, GROUP(
-		PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011,
-		PF7MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PF6MD_000, PF6MD_001, PF6MD_010, PF6MD_011,
-		PF6MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PF5MD_000, PF5MD_001, PF5MD_010, PF5MD_011,
-		PF5MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011,
-		PF4MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PFCR0", 0xfffe38ae, 16, 4, GROUP(
-		PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011,
-		PF3MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PF2MD_000, PF2MD_001, PF2MD_010, PF2MD_011,
-		PF2MD_100, PF2MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PF1MD_000, PF1MD_001, PF1MD_010, PF1MD_011,
-		PF1MD_100, PF1MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PF0MD_000, PF0MD_001, PF0MD_010, PF0MD_011,
-		PF0MD_100, PF0MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PFIOR0", 0xfffe38b2, 16, 1, GROUP(
-		0, 0, 0, 0, 0, 0,
-		PF12_IN, PF12_OUT,
-		PF11_IN, PF11_OUT,
-		PF10_IN, PF10_OUT,
-		PF9_IN, PF9_OUT,
-		PF8_IN, PF8_OUT,
-		PF7_IN, PF7_OUT,
-		PF6_IN, PF6_OUT,
-		PF5_IN, PF5_OUT,
-		PF4_IN, PF4_OUT,
-		PF3_IN, PF3_OUT,
-		PF2_IN, PF2_OUT,
-		PF1_IN, PF1_OUT,
-		PF0_IN, PF0_OUT ))
-	},
-
-	{ PINMUX_CFG_REG("PGCR7", 0xfffe38c0, 16, 4, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011,
-		PG0MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PGCR6", 0xfffe38c2, 16, 4, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PGCR5", 0xfffe38c4, 16, 4, GROUP(
-		PG23MD_00, PG23MD_01, PG23MD_10, PG23MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PG22MD_00, PG22MD_01, PG22MD_10, PG22MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PG21MD_00, PG21MD_01, PG21MD_10, PG21MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011,
-		PG20MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PGCR4", 0xfffe38c6, 16, 4, GROUP(
-		PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011,
-		PG19MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PG18MD_000, PG18MD_001, PG18MD_010, PG18MD_011,
-		PG18MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PG17MD_000, PG17MD_001, PG17MD_010, PG17MD_011,
-		PG17MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PG16MD_000, PG16MD_001, PG16MD_010, PG16MD_011,
-		PG16MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PGCR3", 0xfffe38c8, 16, 4, GROUP(
-		PG15MD_000, PG15MD_001, PG15MD_010, PG15MD_011,
-		PG15MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PG14MD_000, PG14MD_001, PG14MD_010, 0,
-		PG14MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PG13MD_000, PG13MD_001, PG13MD_010, 0,
-		PG13MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PG12MD_000, PG12MD_001, PG12MD_010, 0,
-		PG12MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PGCR2", 0xfffe38ca, 16, 4, GROUP(
-		PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011,
-		PG11MD_100, PG11MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PG10MD_000, PG10MD_001, PG10MD_010, PG10MD_011,
-		PG10MD_100, PG10MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PG9MD_000, PG9MD_001, PG9MD_010, PG9MD_011,
-		PG9MD_100, PG9MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011,
-		PG8MD_100, PG8MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PGCR1", 0xfffe38cc, 16, 4, GROUP(
-		PG7MD_00, PG7MD_01, PG7MD_10, PG7MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PG6MD_00, PG6MD_01, PG6MD_10, PG6MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PG5MD_00, PG5MD_01, PG5MD_10, PG5MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PG4MD_00, PG4MD_01, PG4MD_10, PG4MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PGCR0", 0xfffe38ce, 16, 4, GROUP(
-		PG3MD_00, PG3MD_01, PG3MD_10, PG3MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PG2MD_00, PG2MD_01, PG2MD_10, PG2MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PG1MD_00, PG1MD_01, PG1MD_10, PG1MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PGIOR1", 0xfffe38d0, 16, 1, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0,
-		PG24_IN, PG24_OUT,
-		PG23_IN, PG23_OUT,
-		PG22_IN, PG22_OUT,
-		PG21_IN, PG21_OUT,
-		PG20_IN, PG20_OUT,
-		PG19_IN, PG19_OUT,
-		PG18_IN, PG18_OUT,
-		PG17_IN, PG17_OUT,
-		PG16_IN, PG16_OUT ))
-	},
-
-	{ PINMUX_CFG_REG("PGIOR0", 0xfffe38d2, 16, 1, GROUP(
-		PG15_IN, PG15_OUT,
-		PG14_IN, PG14_OUT,
-		PG13_IN, PG13_OUT,
-		PG12_IN, PG12_OUT,
-		PG11_IN, PG11_OUT,
-		PG10_IN, PG10_OUT,
-		PG9_IN, PG9_OUT,
-		PG8_IN, PG8_OUT,
-		PG7_IN, PG7_OUT,
-		PG6_IN, PG6_OUT,
-		PG5_IN, PG5_OUT,
-		PG4_IN, PG4_OUT,
-		PG3_IN, PG3_OUT,
-		PG2_IN, PG2_OUT,
-		PG1_IN, PG1_OUT,
-		PG0_IN, PG0_OUT
-	 ))
-	},
-
-	{ PINMUX_CFG_REG("PHCR1", 0xfffe38ec, 16, 4, GROUP(
-		PH7MD_0, PH7MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PH6MD_0, PH6MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PH5MD_0, PH5MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PH4MD_0, PH4MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PHCR0", 0xfffe38ee, 16, 4, GROUP(
-		PH3MD_0, PH3MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PH2MD_0, PH2MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PH1MD_0, PH1MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PH0MD_0, PH0MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PJCR2", 0xfffe390a, 16, 4, GROUP(
-		PJ11MD_00, PJ11MD_01, PJ11MD_10, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PJ10MD_00, PJ10MD_01, PJ10MD_10, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PJ9MD_00, PJ9MD_01, PJ9MD_10, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PJ8MD_00, PJ8MD_01, PJ8MD_10, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PJCR1", 0xfffe390c, 16, 4, GROUP(
-		PJ7MD_00, PJ7MD_01, PJ7MD_10, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PJ6MD_00, PJ6MD_01, PJ6MD_10, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PJ5MD_00, PJ5MD_01, PJ5MD_10, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PJ4MD_00, PJ4MD_01, PJ4MD_10, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PJCR0", 0xfffe390e, 16, 4, GROUP(
-		PJ3MD_00, PJ3MD_01, PJ3MD_10, PJ3MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PJ2MD_000, PJ2MD_001, PJ2MD_010, PJ2MD_011,
-		PJ2MD_100, PJ2MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PJ1MD_000, PJ1MD_001, PJ1MD_010, PJ1MD_011,
-		PJ1MD_100, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011,
-		PJ0MD_100, PJ0MD_101, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG("PJIOR0", 0xfffe3912, 16, 1, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PJ11_IN, PJ11_OUT,
-		PJ10_IN, PJ10_OUT,
-		PJ9_IN, PJ9_OUT,
-		PJ8_IN, PJ8_OUT,
-		PJ7_IN, PJ7_OUT,
-		PJ6_IN, PJ6_OUT,
-		PJ5_IN, PJ5_OUT,
-		PJ4_IN, PJ4_OUT,
-		PJ3_IN, PJ3_OUT,
-		PJ2_IN, PJ2_OUT,
-		PJ1_IN, PJ1_OUT,
-		PJ0_IN, PJ0_OUT ))
-	},
-
-	{ PINMUX_CFG_REG("PKCR2", 0xfffe392a, 16, 4, GROUP(
-		PK11MD_00, PK11MD_01, PK11MD_10, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PK10MD_00, PK10MD_01, PK10MD_10, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PK9MD_00, PK9MD_01, PK9MD_10, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PK8MD_00, PK8MD_01, PK8MD_10, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PKCR1", 0xfffe392c, 16, 4, GROUP(
-		PK7MD_00, PK7MD_01, PK7MD_10, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PK6MD_00, PK6MD_01, PK6MD_10, 0,  0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PK5MD_00, PK5MD_01, PK5MD_10, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PK4MD_00, PK4MD_01, PK4MD_10, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PKCR0", 0xfffe392e, 16, 4, GROUP(
-		PK3MD_00, PK3MD_01, PK3MD_10, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PK2MD_00, PK2MD_01, PK2MD_10, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PK1MD_00, PK1MD_01, PK1MD_10, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PK0MD_00, PK0MD_01, PK0MD_10, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PKIOR0", 0xfffe3932, 16, 1, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PK11_IN, PK11_OUT,
-		PK10_IN, PK10_OUT,
-		PK9_IN, PK9_OUT,
-		PK8_IN, PK8_OUT,
-		PK7_IN, PK7_OUT,
-		PK6_IN, PK6_OUT,
-		PK5_IN, PK5_OUT,
-		PK4_IN, PK4_OUT,
-		PK3_IN, PK3_OUT,
-		PK2_IN, PK2_OUT,
-		PK1_IN, PK1_OUT,
-		PK0_IN, PK0_OUT ))
-	},
-	{}
-};
-
-static const struct pinmux_data_reg pinmux_data_regs[] = {
-	{ PINMUX_DATA_REG("PADR1", 0xfffe3814, 16, GROUP(
-		0, 0, 0, 0, 0, 0, 0, PA3_DATA,
-		0, 0, 0, 0, 0, 0, 0, PA2_DATA ))
-	},
-
-	{ PINMUX_DATA_REG("PADR0", 0xfffe3816, 16, GROUP(
-		0, 0, 0, 0, 0, 0, 0, PA1_DATA,
-		0, 0, 0, 0, 0, 0, 0, PA0_DATA ))
-	},
-
-	{ PINMUX_DATA_REG("PBDR1", 0xfffe3834, 16, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PB22_DATA, PB21_DATA, PB20_DATA,
-		PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA ))
-	},
-
-	{ PINMUX_DATA_REG("PBDR0", 0xfffe3836, 16, GROUP(
-		PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA,
-		PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
-		PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
-		PB3_DATA, PB2_DATA, PB1_DATA, 0 ))
-	},
-
-	{ PINMUX_DATA_REG("PCDR0", 0xfffe3856, 16, GROUP(
-		0, 0, 0, 0,
-		0, PC10_DATA, PC9_DATA, PC8_DATA,
-		PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
-		PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
-	},
-
-	{ PINMUX_DATA_REG("PDDR0", 0xfffe3876, 16, GROUP(
-		PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
-		PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
-		PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
-		PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
-	},
-
-	{ PINMUX_DATA_REG("PEDR0", 0xfffe3896, 16, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, PE5_DATA, PE4_DATA,
-		PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA ))
-	},
-
-	{ PINMUX_DATA_REG("PFDR0", 0xfffe38b6, 16, GROUP(
-		0, 0, 0, PF12_DATA,
-		PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
-		PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
-		PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
-	},
-
-	{ PINMUX_DATA_REG("PGDR1", 0xfffe38d4, 16, GROUP(
-		0, 0, 0, 0, 0, 0, 0, PG24_DATA,
-		PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA,
-		PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA ))
-	},
-
-	{ PINMUX_DATA_REG("PGDR0", 0xfffe38d6, 16, GROUP(
-		PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA,
-		PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA,
-		PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
-		PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PJDR0", 0xfffe3916, 16, GROUP(
-		0, 0, 0, PJ12_DATA,
-		PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA,
-		PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
-		PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PKDR0", 0xfffe3936, 16, GROUP(
-		0, 0, 0, PK12_DATA,
-		PK11_DATA, PK10_DATA, PK9_DATA, PK8_DATA,
-		PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
-		PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA ))
-	},
-	{ }
-};
-
-const struct sh_pfc_soc_info sh7264_pinmux_info = {
-	.name = "sh7264_pfc",
-	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
-	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.func_gpios = pinmux_func_gpios,
-	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
-	.cfg_regs = pinmux_config_regs,
-	.data_regs = pinmux_data_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
deleted file mode 100644
index d20974a55d93..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c
+++ /dev/null
@@ -1,2847 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * SH7269 Pinmux
- *
- * Copyright (C) 2012  Renesas Electronics Europe Ltd
- * Copyright (C) 2012  Phil Edworthy
- */
-
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <cpu/sh7269.h>
-
-#include "sh_pfc.h"
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	/* Port A */
-	PA1_DATA, PA0_DATA,
-	/* Port B */
-	PB22_DATA, PB21_DATA, PB20_DATA,
-	PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA,
-	PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA,
-	PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
-	PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
-	PB3_DATA, PB2_DATA, PB1_DATA,
-	/* Port C */
-	PC8_DATA,
-	PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
-	PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
-	/* Port D */
-	PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
-	PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
-	PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
-	PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
-	/* Port E */
-	PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
-	PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
-	/* Port F */
-	PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA,
-	PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA,
-	PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA,
-	PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
-	PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
-	PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
-	/* Port G */
-	PG27_DATA, PG26_DATA, PG25_DATA, PG24_DATA,
-	PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA,
-	PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA,
-	PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA,
-	PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA,
-	PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
-	PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
-	/* Port H */
-	/* NOTE - Port H does not have a Data Register, but PH Data is
-	   connected to PH Port Register */
-	PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
-	PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
-	/* Port I - not on device */
-	/* Port J */
-	PJ31_DATA, PJ30_DATA, PJ29_DATA, PJ28_DATA,
-	PJ27_DATA, PJ26_DATA, PJ25_DATA, PJ24_DATA,
-	PJ23_DATA, PJ22_DATA, PJ21_DATA, PJ20_DATA,
-	PJ19_DATA, PJ18_DATA, PJ17_DATA, PJ16_DATA,
-	PJ15_DATA, PJ14_DATA, PJ13_DATA, PJ12_DATA,
-	PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA,
-	PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
-	PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA,
-	PINMUX_DATA_END,
-
-	PINMUX_INPUT_BEGIN,
-	FORCE_IN,
-	/* Port A */
-	PA1_IN, PA0_IN,
-	/* Port B */
-	PB22_IN, PB21_IN, PB20_IN,
-	PB19_IN, PB18_IN, PB17_IN, PB16_IN,
-	PB15_IN, PB14_IN, PB13_IN, PB12_IN,
-	PB11_IN, PB10_IN, PB9_IN, PB8_IN,
-	PB7_IN, PB6_IN, PB5_IN, PB4_IN,
-	PB3_IN, PB2_IN, PB1_IN,
-	/* Port C */
-	PC8_IN,
-	PC7_IN, PC6_IN, PC5_IN, PC4_IN,
-	PC3_IN, PC2_IN, PC1_IN, PC0_IN,
-	/* Port D */
-	PD15_IN, PD14_IN, PD13_IN, PD12_IN,
-	PD11_IN, PD10_IN, PD9_IN, PD8_IN,
-	PD7_IN, PD6_IN, PD5_IN, PD4_IN,
-	PD3_IN, PD2_IN, PD1_IN, PD0_IN,
-	/* Port E */
-	PE7_IN, PE6_IN, PE5_IN, PE4_IN,
-	PE3_IN, PE2_IN, PE1_IN, PE0_IN,
-	/* Port F */
-	PF23_IN, PF22_IN, PF21_IN, PF20_IN,
-	PF19_IN, PF18_IN, PF17_IN, PF16_IN,
-	PF15_IN, PF14_IN, PF13_IN, PF12_IN,
-	PF11_IN, PF10_IN, PF9_IN, PF8_IN,
-	PF7_IN, PF6_IN, PF5_IN, PF4_IN,
-	PF3_IN, PF2_IN, PF1_IN, PF0_IN,
-	/* Port G */
-	PG27_IN, PG26_IN, PG25_IN, PG24_IN,
-	PG23_IN, PG22_IN, PG21_IN, PG20_IN,
-	PG19_IN, PG18_IN, PG17_IN, PG16_IN,
-	PG15_IN, PG14_IN, PG13_IN, PG12_IN,
-	PG11_IN, PG10_IN, PG9_IN, PG8_IN,
-	PG7_IN, PG6_IN, PG5_IN, PG4_IN,
-	PG3_IN, PG2_IN, PG1_IN, PG0_IN,
-	/* Port H - Port H does not have a Data Register */
-	/* Port I - not on device */
-	/* Port J */
-	PJ31_IN, PJ30_IN, PJ29_IN, PJ28_IN,
-	PJ27_IN, PJ26_IN, PJ25_IN, PJ24_IN,
-	PJ23_IN, PJ22_IN, PJ21_IN, PJ20_IN,
-	PJ19_IN, PJ18_IN, PJ17_IN, PJ16_IN,
-	PJ15_IN, PJ14_IN, PJ13_IN, PJ12_IN,
-	PJ11_IN, PJ10_IN, PJ9_IN, PJ8_IN,
-	PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
-	PJ3_IN, PJ2_IN, PJ1_IN, PJ0_IN,
-	PINMUX_INPUT_END,
-
-	PINMUX_OUTPUT_BEGIN,
-	FORCE_OUT,
-	/* Port A */
-	PA1_OUT, PA0_OUT,
-	/* Port B */
-	PB22_OUT, PB21_OUT, PB20_OUT,
-	PB19_OUT, PB18_OUT, PB17_OUT, PB16_OUT,
-	PB15_OUT, PB14_OUT, PB13_OUT, PB12_OUT,
-	PB11_OUT, PB10_OUT, PB9_OUT, PB8_OUT,
-	PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
-	PB3_OUT, PB2_OUT, PB1_OUT,
-	/* Port C */
-	PC8_OUT,
-	PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
-	PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
-	/* Port D */
-	PD15_OUT, PD14_OUT, PD13_OUT, PD12_OUT,
-	PD11_OUT, PD10_OUT, PD9_OUT, PD8_OUT,
-	PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
-	PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
-	/* Port E */
-	PE7_OUT, PE6_OUT, PE5_OUT, PE4_OUT,
-	PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
-	/* Port F */
-	PF23_OUT, PF22_OUT, PF21_OUT, PF20_OUT,
-	PF19_OUT, PF18_OUT, PF17_OUT, PF16_OUT,
-	PF15_OUT, PF14_OUT, PF13_OUT, PF12_OUT,
-	PF11_OUT, PF10_OUT, PF9_OUT, PF8_OUT,
-	PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
-	PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
-	/* Port G */
-	PG27_OUT, PG26_OUT, PG25_OUT, PG24_OUT,
-	PG23_OUT, PG22_OUT, PG21_OUT, PG20_OUT,
-	PG19_OUT, PG18_OUT, PG17_OUT, PG16_OUT,
-	PG15_OUT, PG14_OUT, PG13_OUT, PG12_OUT,
-	PG11_OUT, PG10_OUT, PG9_OUT, PG8_OUT,
-	PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT,
-	PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT,
-	/* Port H - Port H does not have a Data Register */
-	/* Port I - not on device */
-	/* Port J */
-	PJ31_OUT, PJ30_OUT, PJ29_OUT, PJ28_OUT,
-	PJ27_OUT, PJ26_OUT, PJ25_OUT, PJ24_OUT,
-	PJ23_OUT, PJ22_OUT, PJ21_OUT, PJ20_OUT,
-	PJ19_OUT, PJ18_OUT, PJ17_OUT, PJ16_OUT,
-	PJ15_OUT, PJ14_OUT, PJ13_OUT, PJ12_OUT,
-	PJ11_OUT, PJ10_OUT, PJ9_OUT, PJ8_OUT,
-	PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
-	PJ3_OUT, PJ2_OUT, PJ1_OUT, PJ0_OUT,
-	PINMUX_OUTPUT_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	/* Port A */
-	PA1_IOR_IN, PA1_IOR_OUT,
-	PA0_IOR_IN, PA0_IOR_OUT,
-
-	/* Port B */
-	PB22_IOR_IN, PB22_IOR_OUT,
-	PB21_IOR_IN, PB21_IOR_OUT,
-	PB20_IOR_IN, PB20_IOR_OUT,
-	PB19_IOR_IN, PB19_IOR_OUT,
-	PB18_IOR_IN, PB18_IOR_OUT,
-	PB17_IOR_IN, PB17_IOR_OUT,
-	PB16_IOR_IN, PB16_IOR_OUT,
-
-	PB15_IOR_IN, PB15_IOR_OUT,
-	PB14_IOR_IN, PB14_IOR_OUT,
-	PB13_IOR_IN, PB13_IOR_OUT,
-	PB12_IOR_IN, PB12_IOR_OUT,
-	PB11_IOR_IN, PB11_IOR_OUT,
-	PB10_IOR_IN, PB10_IOR_OUT,
-	PB9_IOR_IN, PB9_IOR_OUT,
-	PB8_IOR_IN, PB8_IOR_OUT,
-
-	PB7_IOR_IN, PB7_IOR_OUT,
-	PB6_IOR_IN, PB6_IOR_OUT,
-	PB5_IOR_IN, PB5_IOR_OUT,
-	PB4_IOR_IN, PB4_IOR_OUT,
-	PB3_IOR_IN, PB3_IOR_OUT,
-	PB2_IOR_IN, PB2_IOR_OUT,
-	PB1_IOR_IN, PB1_IOR_OUT,
-	PB0_IOR_IN, PB0_IOR_OUT,
-
-	PB22MD_000, PB22MD_001, PB22MD_010, PB22MD_011,
-	PB22MD_100, PB22MD_101, PB22MD_110, PB22MD_111,
-	PB21MD_00, PB21MD_01, PB21MD_10, PB21MD_11,
-	PB20MD_000, PB20MD_001, PB20MD_010, PB20MD_011,
-	PB20MD_100, PB20MD_101, PB20MD_110, PB20MD_111,
-	PB19MD_000, PB19MD_001, PB19MD_010, PB19MD_011,
-	PB19MD_100, PB19MD_101, PB19MD_110, PB19MD_111,
-	PB18MD_000, PB18MD_001, PB18MD_010, PB18MD_011,
-	PB18MD_100, PB18MD_101, PB18MD_110, PB18MD_111,
-	PB17MD_000, PB17MD_001, PB17MD_010, PB17MD_011,
-	PB17MD_100, PB17MD_101, PB17MD_110, PB17MD_111,
-	PB16MD_000, PB16MD_001, PB16MD_010, PB16MD_011,
-	PB16MD_100, PB16MD_101, PB16MD_110, PB16MD_111,
-	PB15MD_000, PB15MD_001, PB15MD_010, PB15MD_011,
-	PB15MD_100, PB15MD_101, PB15MD_110, PB15MD_111,
-	PB14MD_000, PB14MD_001, PB14MD_010, PB14MD_011,
-	PB14MD_100, PB14MD_101, PB14MD_110, PB14MD_111,
-	PB13MD_000, PB13MD_001, PB13MD_010, PB13MD_011,
-	PB13MD_100, PB13MD_101, PB13MD_110, PB13MD_111,
-	PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11,
-
-	PB11MD_00, PB11MD_01, PB11MD_10, PB11MD_11,
-	PB10MD_00, PB10MD_01, PB10MD_10, PB10MD_11,
-	PB9MD_00, PB9MD_01, PB9MD_10, PB9MD_11,
-	PB8MD_00, PB8MD_01, PB8MD_10, PB8MD_11,
-
-	PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11,
-	PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11,
-	PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11,
-	PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11,
-
-	PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11,
-	PB2MD_00, PB2MD_01, PB2MD_10, PB2MD_11,
-	PB1MD_00, PB1MD_01, PB1MD_10, PB1MD_11,
-
-	/* Port C */
-	PC8_IOR_IN, PC8_IOR_OUT,
-	PC7_IOR_IN, PC7_IOR_OUT,
-	PC6_IOR_IN, PC6_IOR_OUT,
-	PC5_IOR_IN, PC5_IOR_OUT,
-	PC4_IOR_IN, PC4_IOR_OUT,
-	PC3_IOR_IN, PC3_IOR_OUT,
-	PC2_IOR_IN, PC2_IOR_OUT,
-	PC1_IOR_IN, PC1_IOR_OUT,
-	PC0_IOR_IN, PC0_IOR_OUT,
-
-	PC8MD_000, PC8MD_001, PC8MD_010, PC8MD_011,
-	PC8MD_100, PC8MD_101, PC8MD_110, PC8MD_111,
-	PC7MD_000, PC7MD_001, PC7MD_010, PC7MD_011,
-	PC7MD_100, PC7MD_101, PC7MD_110, PC7MD_111,
-	PC6MD_000, PC6MD_001, PC6MD_010, PC6MD_011,
-	PC6MD_100, PC6MD_101, PC6MD_110, PC6MD_111,
-	PC5MD_000, PC5MD_001, PC5MD_010, PC5MD_011,
-	PC5MD_100, PC5MD_101, PC5MD_110, PC5MD_111,
-	PC4MD_00, PC4MD_01, PC4MD_10, PC4MD_11,
-
-	PC3MD_00, PC3MD_01, PC3MD_10, PC3MD_11,
-	PC2MD_00, PC2MD_01, PC2MD_10, PC2MD_11,
-	PC1MD_0, PC1MD_1,
-	PC0MD_0, PC0MD_1,
-
-	/* Port D */
-	PD15_IOR_IN, PD15_IOR_OUT,
-	PD14_IOR_IN, PD14_IOR_OUT,
-	PD13_IOR_IN, PD13_IOR_OUT,
-	PD12_IOR_IN, PD12_IOR_OUT,
-	PD11_IOR_IN, PD11_IOR_OUT,
-	PD10_IOR_IN, PD10_IOR_OUT,
-	PD9_IOR_IN, PD9_IOR_OUT,
-	PD8_IOR_IN, PD8_IOR_OUT,
-	PD7_IOR_IN, PD7_IOR_OUT,
-	PD6_IOR_IN, PD6_IOR_OUT,
-	PD5_IOR_IN, PD5_IOR_OUT,
-	PD4_IOR_IN, PD4_IOR_OUT,
-	PD3_IOR_IN, PD3_IOR_OUT,
-	PD2_IOR_IN, PD2_IOR_OUT,
-	PD1_IOR_IN, PD1_IOR_OUT,
-	PD0_IOR_IN, PD0_IOR_OUT,
-
-	PD15MD_00, PD15MD_01, PD15MD_10, PD15MD_11,
-	PD14MD_00, PD14MD_01, PD14MD_10, PD14MD_11,
-	PD13MD_00, PD13MD_01, PD13MD_10, PD13MD_11,
-	PD12MD_00, PD12MD_01, PD12MD_10, PD12MD_11,
-
-	PD11MD_00, PD11MD_01, PD11MD_10, PD11MD_11,
-	PD10MD_00, PD10MD_01, PD10MD_10, PD10MD_11,
-	PD9MD_00, PD9MD_01, PD9MD_10, PD9MD_11,
-	PD8MD_00, PD8MD_01, PD8MD_10, PD8MD_11,
-
-	PD7MD_00, PD7MD_01, PD7MD_10, PD7MD_11,
-	PD6MD_00, PD6MD_01, PD6MD_10, PD6MD_11,
-	PD5MD_00, PD5MD_01, PD5MD_10, PD5MD_11,
-	PD4MD_00, PD4MD_01, PD4MD_10, PD4MD_11,
-
-	PD3MD_00, PD3MD_01, PD3MD_10, PD3MD_11,
-	PD2MD_00, PD2MD_01, PD2MD_10, PD2MD_11,
-	PD1MD_00, PD1MD_01, PD1MD_10, PD1MD_11,
-	PD0MD_00, PD0MD_01, PD0MD_10, PD0MD_11,
-
-	/* Port E */
-	PE7_IOR_IN, PE7_IOR_OUT,
-	PE6_IOR_IN, PE6_IOR_OUT,
-	PE5_IOR_IN, PE5_IOR_OUT,
-	PE4_IOR_IN, PE4_IOR_OUT,
-	PE3_IOR_IN, PE3_IOR_OUT,
-	PE2_IOR_IN, PE2_IOR_OUT,
-	PE1_IOR_IN, PE1_IOR_OUT,
-	PE0_IOR_IN, PE0_IOR_OUT,
-
-	PE7MD_00, PE7MD_01, PE7MD_10, PE7MD_11,
-	PE6MD_00, PE6MD_01, PE6MD_10, PE6MD_11,
-	PE5MD_00, PE5MD_01, PE5MD_10, PE5MD_11,
-	PE4MD_00, PE4MD_01, PE4MD_10, PE4MD_11,
-
-	PE3MD_000, PE3MD_001, PE3MD_010, PE3MD_011,
-	PE3MD_100, PE3MD_101, PE3MD_110, PE3MD_111,
-	PE2MD_000, PE2MD_001, PE2MD_010, PE2MD_011,
-	PE2MD_100, PE2MD_101, PE2MD_110, PE2MD_111,
-	PE1MD_000, PE1MD_001, PE1MD_010, PE1MD_011,
-	PE1MD_100, PE1MD_101, PE1MD_110, PE1MD_111,
-	PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11,
-
-	/* Port F */
-	PF23_IOR_IN, PF23_IOR_OUT,
-	PF22_IOR_IN, PF22_IOR_OUT,
-	PF21_IOR_IN, PF21_IOR_OUT,
-	PF20_IOR_IN, PF20_IOR_OUT,
-	PF19_IOR_IN, PF19_IOR_OUT,
-	PF18_IOR_IN, PF18_IOR_OUT,
-	PF17_IOR_IN, PF17_IOR_OUT,
-	PF16_IOR_IN, PF16_IOR_OUT,
-	PF15_IOR_IN, PF15_IOR_OUT,
-	PF14_IOR_IN, PF14_IOR_OUT,
-	PF13_IOR_IN, PF13_IOR_OUT,
-	PF12_IOR_IN, PF12_IOR_OUT,
-	PF11_IOR_IN, PF11_IOR_OUT,
-	PF10_IOR_IN, PF10_IOR_OUT,
-	PF9_IOR_IN, PF9_IOR_OUT,
-	PF8_IOR_IN, PF8_IOR_OUT,
-	PF7_IOR_IN, PF7_IOR_OUT,
-	PF6_IOR_IN, PF6_IOR_OUT,
-	PF5_IOR_IN, PF5_IOR_OUT,
-	PF4_IOR_IN, PF4_IOR_OUT,
-	PF3_IOR_IN, PF3_IOR_OUT,
-	PF2_IOR_IN, PF2_IOR_OUT,
-	PF1_IOR_IN, PF1_IOR_OUT,
-	PF0_IOR_IN, PF0_IOR_OUT,
-
-	PF23MD_000, PF23MD_001, PF23MD_010, PF23MD_011,
-	PF23MD_100, PF23MD_101, PF23MD_110, PF23MD_111,
-	PF22MD_000, PF22MD_001, PF22MD_010, PF22MD_011,
-	PF22MD_100, PF22MD_101, PF22MD_110, PF22MD_111,
-	PF21MD_000, PF21MD_001, PF21MD_010, PF21MD_011,
-	PF21MD_100, PF21MD_101, PF21MD_110, PF21MD_111,
-	PF20MD_000, PF20MD_001, PF20MD_010, PF20MD_011,
-	PF20MD_100, PF20MD_101, PF20MD_110, PF20MD_111,
-
-	PF19MD_000, PF19MD_001, PF19MD_010, PF19MD_011,
-	PF19MD_100, PF19MD_101, PF19MD_110, PF19MD_111,
-	PF18MD_000, PF18MD_001, PF18MD_010, PF18MD_011,
-	PF18MD_100, PF18MD_101, PF18MD_110, PF18MD_111,
-	PF17MD_000, PF17MD_001, PF17MD_010, PF17MD_011,
-	PF17MD_100, PF17MD_101, PF17MD_110, PF17MD_111,
-	PF16MD_000, PF16MD_001, PF16MD_010, PF16MD_011,
-	PF16MD_100, PF16MD_101, PF16MD_110, PF16MD_111,
-
-	PF15MD_000, PF15MD_001, PF15MD_010, PF15MD_011,
-	PF15MD_100, PF15MD_101, PF15MD_110, PF15MD_111,
-	PF14MD_000, PF14MD_001, PF14MD_010, PF14MD_011,
-	PF14MD_100, PF14MD_101, PF14MD_110, PF14MD_111,
-	PF13MD_000, PF13MD_001, PF13MD_010, PF13MD_011,
-	PF13MD_100, PF13MD_101, PF13MD_110, PF13MD_111,
-	PF12MD_000, PF12MD_001, PF12MD_010, PF12MD_011,
-	PF12MD_100, PF12MD_101, PF12MD_110, PF12MD_111,
-
-	PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011,
-	PF11MD_100, PF11MD_101, PF11MD_110, PF11MD_111,
-	PF10MD_000, PF10MD_001, PF10MD_010, PF10MD_011,
-	PF10MD_100, PF10MD_101, PF10MD_110, PF10MD_111,
-	PF9MD_000, PF9MD_001, PF9MD_010, PF9MD_011,
-	PF9MD_100, PF9MD_101, PF9MD_110, PF9MD_111,
-	PF8MD_000, PF8MD_001, PF8MD_010, PF8MD_011,
-	PF8MD_100, PF8MD_101, PF8MD_110, PF8MD_111,
-
-	PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011,
-	PF7MD_100, PF7MD_101, PF7MD_110, PF7MD_111,
-	PF6MD_000, PF6MD_001, PF6MD_010, PF6MD_011,
-	PF6MD_100, PF6MD_101, PF6MD_110, PF6MD_111,
-	PF5MD_000, PF5MD_001, PF5MD_010, PF5MD_011,
-	PF5MD_100, PF5MD_101, PF5MD_110, PF5MD_111,
-	PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011,
-	PF4MD_100, PF4MD_101, PF4MD_110, PF4MD_111,
-
-	PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011,
-	PF3MD_100, PF3MD_101, PF3MD_110, PF3MD_111,
-	PF2MD_000, PF2MD_001, PF2MD_010, PF2MD_011,
-	PF2MD_100, PF2MD_101, PF2MD_110, PF2MD_111,
-	PF1MD_000, PF1MD_001, PF1MD_010, PF1MD_011,
-	PF1MD_100, PF1MD_101, PF1MD_110, PF1MD_111,
-	PF0MD_000, PF0MD_001, PF0MD_010, PF0MD_011,
-	PF0MD_100, PF0MD_101, PF0MD_110, PF0MD_111,
-
-	/* Port G */
-	PG27_IOR_IN, PG27_IOR_OUT,
-	PG26_IOR_IN, PG26_IOR_OUT,
-	PG25_IOR_IN, PG25_IOR_OUT,
-	PG24_IOR_IN, PG24_IOR_OUT,
-	PG23_IOR_IN, PG23_IOR_OUT,
-	PG22_IOR_IN, PG22_IOR_OUT,
-	PG21_IOR_IN, PG21_IOR_OUT,
-	PG20_IOR_IN, PG20_IOR_OUT,
-	PG19_IOR_IN, PG19_IOR_OUT,
-	PG18_IOR_IN, PG18_IOR_OUT,
-	PG17_IOR_IN, PG17_IOR_OUT,
-	PG16_IOR_IN, PG16_IOR_OUT,
-	PG15_IOR_IN, PG15_IOR_OUT,
-	PG14_IOR_IN, PG14_IOR_OUT,
-	PG13_IOR_IN, PG13_IOR_OUT,
-	PG12_IOR_IN, PG12_IOR_OUT,
-	PG11_IOR_IN, PG11_IOR_OUT,
-	PG10_IOR_IN, PG10_IOR_OUT,
-	PG9_IOR_IN, PG9_IOR_OUT,
-	PG8_IOR_IN, PG8_IOR_OUT,
-	PG7_IOR_IN, PG7_IOR_OUT,
-	PG6_IOR_IN, PG6_IOR_OUT,
-	PG5_IOR_IN, PG5_IOR_OUT,
-	PG4_IOR_IN, PG4_IOR_OUT,
-	PG3_IOR_IN, PG3_IOR_OUT,
-	PG2_IOR_IN, PG2_IOR_OUT,
-	PG1_IOR_IN, PG1_IOR_OUT,
-	PG0_IOR_IN, PG0_IOR_OUT,
-
-	PG27MD_00, PG27MD_01, PG27MD_10, PG27MD_11,
-	PG26MD_00, PG26MD_01, PG26MD_10, PG26MD_11,
-	PG25MD_00, PG25MD_01, PG25MD_10, PG25MD_11,
-	PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11,
-
-	PG23MD_000, PG23MD_001, PG23MD_010, PG23MD_011,
-	PG23MD_100, PG23MD_101, PG23MD_110, PG23MD_111,
-	PG22MD_000, PG22MD_001, PG22MD_010, PG22MD_011,
-	PG22MD_100, PG22MD_101, PG22MD_110, PG22MD_111,
-	PG21MD_000, PG21MD_001, PG21MD_010, PG21MD_011,
-	PG21MD_100, PG21MD_101, PG21MD_110, PG21MD_111,
-	PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011,
-	PG20MD_100, PG20MD_101, PG20MD_110, PG20MD_111,
-
-	PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011,
-	PG19MD_100, PG19MD_101, PG19MD_110, PG19MD_111,
-	PG18MD_000, PG18MD_001, PG18MD_010, PG18MD_011,
-	PG18MD_100, PG18MD_101, PG18MD_110, PG18MD_111,
-	PG17MD_00, PG17MD_01, PG17MD_10, PG17MD_11,
-	PG16MD_00, PG16MD_01, PG16MD_10, PG16MD_11,
-
-	PG15MD_00, PG15MD_01, PG15MD_10, PG15MD_11,
-	PG14MD_00, PG14MD_01, PG14MD_10, PG14MD_11,
-	PG13MD_00, PG13MD_01, PG13MD_10, PG13MD_11,
-	PG12MD_00, PG12MD_01, PG12MD_10, PG12MD_11,
-
-	PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011,
-	PG11MD_100, PG11MD_101, PG11MD_110, PG11MD_111,
-	PG10MD_000, PG10MD_001, PG10MD_010, PG10MD_011,
-	PG10MD_100, PG10MD_101, PG10MD_110, PG10MD_111,
-	PG9MD_000, PG9MD_001, PG9MD_010, PG9MD_011,
-	PG9MD_100, PG9MD_101, PG9MD_110, PG9MD_111,
-	PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011,
-	PG8MD_100, PG8MD_101, PG8MD_110, PG8MD_111,
-
-	PG7MD_000, PG7MD_001, PG7MD_010, PG7MD_011,
-	PG7MD_100, PG7MD_101, PG7MD_110, PG7MD_111,
-	PG6MD_000, PG6MD_001, PG6MD_010, PG6MD_011,
-	PG6MD_100, PG6MD_101, PG6MD_110, PG6MD_111,
-	PG5MD_000, PG5MD_001, PG5MD_010, PG5MD_011,
-	PG5MD_100, PG5MD_101, PG5MD_110, PG5MD_111,
-	PG4MD_000, PG4MD_001, PG4MD_010, PG4MD_011,
-	PG4MD_100, PG4MD_101, PG4MD_110, PG4MD_111,
-
-	PG3MD_000, PG3MD_001, PG3MD_010, PG3MD_011,
-	PG3MD_100, PG3MD_101, PG3MD_110, PG3MD_111,
-	PG2MD_000, PG2MD_001, PG2MD_010, PG2MD_011,
-	PG2MD_100, PG2MD_101, PG2MD_110, PG2MD_111,
-	PG1MD_000, PG1MD_001, PG1MD_010, PG1MD_011,
-	PG1MD_100, PG1MD_101, PG1MD_110, PG1MD_111,
-	PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011,
-	PG0MD_100, PG0MD_101, PG0MD_110, PG0MD_111,
-
-	/* Port H */
-	PH7MD_00, PH7MD_01, PH7MD_10, PH7MD_11,
-	PH6MD_00, PH6MD_01, PH6MD_10, PH6MD_11,
-	PH5MD_00, PH5MD_01, PH5MD_10, PH5MD_11,
-	PH4MD_00, PH4MD_01, PH4MD_10, PH4MD_11,
-
-	PH3MD_00, PH3MD_01, PH3MD_10, PH3MD_11,
-	PH2MD_00, PH2MD_01, PH2MD_10, PH2MD_11,
-	PH1MD_00, PH1MD_01, PH1MD_10, PH1MD_11,
-	PH0MD_00, PH0MD_01, PH0MD_10, PH0MD_11,
-
-	/* Port I - not on device */
-
-	/* Port J */
-	PJ31_IOR_IN, PJ31_IOR_OUT,
-	PJ30_IOR_IN, PJ30_IOR_OUT,
-	PJ29_IOR_IN, PJ29_IOR_OUT,
-	PJ28_IOR_IN, PJ28_IOR_OUT,
-	PJ27_IOR_IN, PJ27_IOR_OUT,
-	PJ26_IOR_IN, PJ26_IOR_OUT,
-	PJ25_IOR_IN, PJ25_IOR_OUT,
-	PJ24_IOR_IN, PJ24_IOR_OUT,
-	PJ23_IOR_IN, PJ23_IOR_OUT,
-	PJ22_IOR_IN, PJ22_IOR_OUT,
-	PJ21_IOR_IN, PJ21_IOR_OUT,
-	PJ20_IOR_IN, PJ20_IOR_OUT,
-	PJ19_IOR_IN, PJ19_IOR_OUT,
-	PJ18_IOR_IN, PJ18_IOR_OUT,
-	PJ17_IOR_IN, PJ17_IOR_OUT,
-	PJ16_IOR_IN, PJ16_IOR_OUT,
-	PJ15_IOR_IN, PJ15_IOR_OUT,
-	PJ14_IOR_IN, PJ14_IOR_OUT,
-	PJ13_IOR_IN, PJ13_IOR_OUT,
-	PJ12_IOR_IN, PJ12_IOR_OUT,
-	PJ11_IOR_IN, PJ11_IOR_OUT,
-	PJ10_IOR_IN, PJ10_IOR_OUT,
-	PJ9_IOR_IN, PJ9_IOR_OUT,
-	PJ8_IOR_IN, PJ8_IOR_OUT,
-	PJ7_IOR_IN, PJ7_IOR_OUT,
-	PJ6_IOR_IN, PJ6_IOR_OUT,
-	PJ5_IOR_IN, PJ5_IOR_OUT,
-	PJ4_IOR_IN, PJ4_IOR_OUT,
-	PJ3_IOR_IN, PJ3_IOR_OUT,
-	PJ2_IOR_IN, PJ2_IOR_OUT,
-	PJ1_IOR_IN, PJ1_IOR_OUT,
-	PJ0_IOR_IN, PJ0_IOR_OUT,
-
-	PJ31MD_0, PJ31MD_1,
-	PJ30MD_000, PJ30MD_001, PJ30MD_010, PJ30MD_011,
-	PJ30MD_100, PJ30MD_101, PJ30MD_110, PJ30MD_111,
-	PJ29MD_000, PJ29MD_001, PJ29MD_010, PJ29MD_011,
-	PJ29MD_100, PJ29MD_101, PJ29MD_110, PJ29MD_111,
-	PJ28MD_000, PJ28MD_001, PJ28MD_010, PJ28MD_011,
-	PJ28MD_100, PJ28MD_101, PJ28MD_110, PJ28MD_111,
-
-	PJ27MD_000, PJ27MD_001, PJ27MD_010, PJ27MD_011,
-	PJ27MD_100, PJ27MD_101, PJ27MD_110, PJ27MD_111,
-	PJ26MD_000, PJ26MD_001, PJ26MD_010, PJ26MD_011,
-	PJ26MD_100, PJ26MD_101, PJ26MD_110, PJ26MD_111,
-	PJ25MD_000, PJ25MD_001, PJ25MD_010, PJ25MD_011,
-	PJ25MD_100, PJ25MD_101, PJ25MD_110, PJ25MD_111,
-	PJ24MD_000, PJ24MD_001, PJ24MD_010, PJ24MD_011,
-	PJ24MD_100, PJ24MD_101, PJ24MD_110, PJ24MD_111,
-
-	PJ23MD_000, PJ23MD_001, PJ23MD_010, PJ23MD_011,
-	PJ23MD_100, PJ23MD_101, PJ23MD_110, PJ23MD_111,
-	PJ22MD_000, PJ22MD_001, PJ22MD_010, PJ22MD_011,
-	PJ22MD_100, PJ22MD_101, PJ22MD_110, PJ22MD_111,
-	PJ21MD_000, PJ21MD_001, PJ21MD_010, PJ21MD_011,
-	PJ21MD_100, PJ21MD_101, PJ21MD_110, PJ21MD_111,
-	PJ20MD_000, PJ20MD_001, PJ20MD_010, PJ20MD_011,
-	PJ20MD_100, PJ20MD_101, PJ20MD_110, PJ20MD_111,
-
-	PJ19MD_000, PJ19MD_001, PJ19MD_010, PJ19MD_011,
-	PJ19MD_100, PJ19MD_101, PJ19MD_110, PJ19MD_111,
-	PJ18MD_000, PJ18MD_001, PJ18MD_010, PJ18MD_011,
-	PJ18MD_100, PJ18MD_101, PJ18MD_110, PJ18MD_111,
-	PJ17MD_000, PJ17MD_001, PJ17MD_010, PJ17MD_011,
-	PJ17MD_100, PJ17MD_101, PJ17MD_110, PJ17MD_111,
-	PJ16MD_000, PJ16MD_001, PJ16MD_010, PJ16MD_011,
-	PJ16MD_100, PJ16MD_101, PJ16MD_110, PJ16MD_111,
-
-	PJ15MD_000, PJ15MD_001, PJ15MD_010, PJ15MD_011,
-	PJ15MD_100, PJ15MD_101, PJ15MD_110, PJ15MD_111,
-	PJ14MD_000, PJ14MD_001, PJ14MD_010, PJ14MD_011,
-	PJ14MD_100, PJ14MD_101, PJ14MD_110, PJ14MD_111,
-	PJ13MD_000, PJ13MD_001, PJ13MD_010, PJ13MD_011,
-	PJ13MD_100, PJ13MD_101, PJ13MD_110, PJ13MD_111,
-	PJ12MD_000, PJ12MD_001, PJ12MD_010, PJ12MD_011,
-	PJ12MD_100, PJ12MD_101, PJ12MD_110, PJ12MD_111,
-
-	PJ11MD_000, PJ11MD_001, PJ11MD_010, PJ11MD_011,
-	PJ11MD_100, PJ11MD_101, PJ11MD_110, PJ11MD_111,
-	PJ10MD_000, PJ10MD_001, PJ10MD_010, PJ10MD_011,
-	PJ10MD_100, PJ10MD_101, PJ10MD_110, PJ10MD_111,
-	PJ9MD_000, PJ9MD_001, PJ9MD_010, PJ9MD_011,
-	PJ9MD_100, PJ9MD_101, PJ9MD_110, PJ9MD_111,
-	PJ8MD_000, PJ8MD_001, PJ8MD_010, PJ8MD_011,
-	PJ8MD_100, PJ8MD_101, PJ8MD_110, PJ8MD_111,
-
-	PJ7MD_000, PJ7MD_001, PJ7MD_010, PJ7MD_011,
-	PJ7MD_100, PJ7MD_101, PJ7MD_110, PJ7MD_111,
-	PJ6MD_000, PJ6MD_001, PJ6MD_010, PJ6MD_011,
-	PJ6MD_100, PJ6MD_101, PJ6MD_110, PJ6MD_111,
-	PJ5MD_000, PJ5MD_001, PJ5MD_010, PJ5MD_011,
-	PJ5MD_100, PJ5MD_101, PJ5MD_110, PJ5MD_111,
-	PJ4MD_000, PJ4MD_001, PJ4MD_010, PJ4MD_011,
-	PJ4MD_100, PJ4MD_101, PJ4MD_110, PJ4MD_111,
-
-	PJ3MD_000, PJ3MD_001, PJ3MD_010, PJ3MD_011,
-	PJ3MD_100, PJ3MD_101, PJ3MD_110, PJ3MD_111,
-	PJ2MD_000, PJ2MD_001, PJ2MD_010, PJ2MD_011,
-	PJ2MD_100, PJ2MD_101, PJ2MD_110, PJ2MD_111,
-	PJ1MD_000, PJ1MD_001, PJ1MD_010, PJ1MD_011,
-	PJ1MD_100, PJ1MD_101, PJ1MD_110, PJ1MD_111,
-	PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011,
-	PJ0MD_100, PJ0MD_101, PJ0MD_110, PJ0MD_111,
-
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-	/* Port H */
-	PHAN7_MARK, PHAN6_MARK, PHAN5_MARK, PHAN4_MARK,
-	PHAN3_MARK, PHAN2_MARK, PHAN1_MARK, PHAN0_MARK,
-
-	/* IRQs */
-	IRQ7_PG_MARK, IRQ6_PG_MARK, IRQ5_PG_MARK, IRQ4_PG_MARK,
-	IRQ3_PG_MARK, IRQ2_PG_MARK, IRQ1_PG_MARK, IRQ0_PG_MARK,
-	IRQ7_PF_MARK, IRQ6_PF_MARK, IRQ5_PF_MARK, IRQ4_PF_MARK,
-	IRQ3_PJ_MARK, IRQ2_PJ_MARK, IRQ1_PJ_MARK, IRQ0_PJ_MARK,
-	IRQ1_PC_MARK, IRQ0_PC_MARK,
-
-	PINT7_PG_MARK, PINT6_PG_MARK, PINT5_PG_MARK, PINT4_PG_MARK,
-	PINT3_PG_MARK, PINT2_PG_MARK, PINT1_PG_MARK, PINT0_PG_MARK,
-	PINT7_PH_MARK, PINT6_PH_MARK, PINT5_PH_MARK, PINT4_PH_MARK,
-	PINT3_PH_MARK, PINT2_PH_MARK, PINT1_PH_MARK, PINT0_PH_MARK,
-	PINT7_PJ_MARK, PINT6_PJ_MARK, PINT5_PJ_MARK, PINT4_PJ_MARK,
-	PINT3_PJ_MARK, PINT2_PJ_MARK, PINT1_PJ_MARK, PINT0_PJ_MARK,
-
-	/* SD */
-	SD_D0_MARK, SD_D1_MARK, SD_D2_MARK, SD_D3_MARK,
-	SD_WP_MARK, SD_CLK_MARK, SD_CMD_MARK, SD_CD_MARK,
-
-	/* MMC */
-	MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
-	MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
-	MMC_CLK_MARK, MMC_CMD_MARK, MMC_CD_MARK,
-
-	/* PWM */
-	PWM1A_MARK, PWM1B_MARK, PWM1C_MARK, PWM1D_MARK,
-	PWM1E_MARK, PWM1F_MARK, PWM1G_MARK, PWM1H_MARK,
-	PWM2A_MARK, PWM2B_MARK, PWM2C_MARK, PWM2D_MARK,
-	PWM2E_MARK, PWM2F_MARK, PWM2G_MARK, PWM2H_MARK,
-
-	/* IEBus */
-	IERXD_MARK, IETXD_MARK,
-
-	/* WDT */
-	WDTOVF_MARK,
-
-	/* DMAC */
-	TEND0_MARK, DACK0_MARK, DREQ0_MARK,
-	TEND1_MARK, DACK1_MARK, DREQ1_MARK,
-
-	/* ADC */
-	ADTRG_MARK,
-
-	/* BSC */
-	A25_MARK, A24_MARK,
-	A23_MARK, A22_MARK, A21_MARK, A20_MARK,
-	A19_MARK, A18_MARK, A17_MARK, A16_MARK,
-	A15_MARK, A14_MARK, A13_MARK, A12_MARK,
-	A11_MARK, A10_MARK, A9_MARK, A8_MARK,
-	A7_MARK, A6_MARK, A5_MARK, A4_MARK,
-	A3_MARK, A2_MARK, A1_MARK, A0_MARK,
-	D31_MARK, D30_MARK, D29_MARK, D28_MARK,
-	D27_MARK, D26_MARK, D25_MARK, D24_MARK,
-	D23_MARK, D22_MARK, D21_MARK, D20_MARK,
-	D19_MARK, D18_MARK, D17_MARK, D16_MARK,
-	D15_MARK, D14_MARK, D13_MARK, D12_MARK,
-	D11_MARK, D10_MARK, D9_MARK, D8_MARK,
-	D7_MARK, D6_MARK, D5_MARK, D4_MARK,
-	D3_MARK, D2_MARK, D1_MARK, D0_MARK,
-	BS_MARK,
-	CS4_MARK, CS3_MARK, CS2_MARK, CS1_MARK, CS0_MARK,
-	CS5CE1A_MARK,
-	CE2A_MARK, CE2B_MARK,
-	RD_MARK, RDWR_MARK,
-	WE3ICIOWRAHDQMUU_MARK,
-	WE2ICIORDDQMUL_MARK,
-	WE1DQMUWE_MARK,
-	WE0DQML_MARK,
-	RAS_MARK, CAS_MARK, CKE_MARK,
-	WAIT_MARK, BREQ_MARK, BACK_MARK, IOIS16_MARK,
-
-	/* TMU */
-	TIOC0A_MARK, TIOC0B_MARK, TIOC0C_MARK, TIOC0D_MARK,
-	TIOC1A_MARK, TIOC1B_MARK,
-	TIOC2A_MARK, TIOC2B_MARK,
-	TIOC3A_MARK, TIOC3B_MARK, TIOC3C_MARK, TIOC3D_MARK,
-	TIOC4A_MARK, TIOC4B_MARK, TIOC4C_MARK, TIOC4D_MARK,
-	TCLKA_MARK, TCLKB_MARK, TCLKC_MARK, TCLKD_MARK,
-
-	/* SCIF */
-	SCK0_MARK, RXD0_MARK, TXD0_MARK,
-	SCK1_MARK, RXD1_MARK, TXD1_MARK, RTS1_MARK, CTS1_MARK,
-	SCK2_MARK, RXD2_MARK, TXD2_MARK,
-	SCK3_MARK, RXD3_MARK, TXD3_MARK,
-	SCK4_MARK, RXD4_MARK, TXD4_MARK,
-	SCK5_MARK, RXD5_MARK, TXD5_MARK, RTS5_MARK, CTS5_MARK,
-	SCK6_MARK, RXD6_MARK, TXD6_MARK,
-	SCK7_MARK, RXD7_MARK, TXD7_MARK, RTS7_MARK, CTS7_MARK,
-
-	/* RSPI */
-	MISO0_PB20_MARK, MOSI0_PB19_MARK, SSL00_PB18_MARK, RSPCK0_PB17_MARK,
-	MISO0_PJ19_MARK, MOSI0_PJ18_MARK, SSL00_PJ17_MARK, RSPCK0_PJ16_MARK,
-	MISO1_MARK, MOSI1_MARK, SSL10_MARK, RSPCK1_MARK,
-
-	/* IIC3 */
-	SCL0_MARK, SDA0_MARK,
-	SCL1_MARK, SDA1_MARK,
-	SCL2_MARK, SDA2_MARK,
-	SCL3_MARK, SDA3_MARK,
-
-	/* SSI */
-	SSISCK0_MARK, SSIWS0_MARK, SSITXD0_MARK, SSIRXD0_MARK,
-	SSISCK1_MARK, SSIWS1_MARK, SSIDATA1_MARK,
-	SSISCK2_MARK, SSIWS2_MARK, SSIDATA2_MARK,
-	SSISCK3_MARK, SSIWS3_MARK, SSIDATA3_MARK,
-	SSISCK4_MARK, SSIWS4_MARK, SSIDATA4_MARK,
-	SSISCK5_MARK, SSIWS5_MARK, SSIDATA5_MARK,
-	AUDIO_CLK_MARK,
-	AUDIO_XOUT_MARK,
-
-	/* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
-	SIOFTXD_MARK, SIOFRXD_MARK, SIOFSYNC_MARK, SIOFSCK_MARK,
-
-	/* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
-	SPDIF_IN_MARK, SPDIF_OUT_MARK,
-	SPDIF_IN_PJ24_MARK, SPDIF_OUT_PJ25_MARK,
-
-	/* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
-	FCE_MARK,
-	FRB_MARK,
-
-	/* CAN */
-	CRX0_MARK, CTX0_MARK,
-	CRX1_MARK, CTX1_MARK,
-	CRX2_MARK, CTX2_MARK,
-	CRX0_CRX1_MARK, CTX0_CTX1_MARK,
-	CRX0_CRX1_CRX2_MARK, CTX0_CTX1_CTX2_MARK,
-	CRX1_PJ22_MARK, CTX1_PJ23_MARK,
-	CRX2_PJ20_MARK, CTX2_PJ21_MARK,
-	CRX0_CRX1_PJ22_MARK, CTX0_CTX1_PJ23_MARK,
-	CRX0_CRX1_CRX2_PJ20_MARK, CTX0_CTX1_CTX2_PJ21_MARK,
-
-	/* VDC */
-	DV_CLK_MARK,
-	DV_VSYNC_MARK, DV_HSYNC_MARK,
-	DV_DATA23_MARK, DV_DATA22_MARK, DV_DATA21_MARK, DV_DATA20_MARK,
-	DV_DATA19_MARK, DV_DATA18_MARK, DV_DATA17_MARK, DV_DATA16_MARK,
-	DV_DATA15_MARK, DV_DATA14_MARK, DV_DATA13_MARK, DV_DATA12_MARK,
-	DV_DATA11_MARK, DV_DATA10_MARK, DV_DATA9_MARK, DV_DATA8_MARK,
-	DV_DATA7_MARK, DV_DATA6_MARK, DV_DATA5_MARK, DV_DATA4_MARK,
-	DV_DATA3_MARK, DV_DATA2_MARK, DV_DATA1_MARK, DV_DATA0_MARK,
-	LCD_CLK_MARK, LCD_EXTCLK_MARK,
-	LCD_VSYNC_MARK, LCD_HSYNC_MARK, LCD_DE_MARK,
-	LCD_DATA23_PG23_MARK, LCD_DATA22_PG22_MARK, LCD_DATA21_PG21_MARK,
-	LCD_DATA20_PG20_MARK, LCD_DATA19_PG19_MARK, LCD_DATA18_PG18_MARK,
-	LCD_DATA17_PG17_MARK, LCD_DATA16_PG16_MARK, LCD_DATA15_PG15_MARK,
-	LCD_DATA14_PG14_MARK, LCD_DATA13_PG13_MARK, LCD_DATA12_PG12_MARK,
-	LCD_DATA11_PG11_MARK, LCD_DATA10_PG10_MARK, LCD_DATA9_PG9_MARK,
-	LCD_DATA8_PG8_MARK, LCD_DATA7_PG7_MARK, LCD_DATA6_PG6_MARK,
-	LCD_DATA5_PG5_MARK, LCD_DATA4_PG4_MARK, LCD_DATA3_PG3_MARK,
-	LCD_DATA2_PG2_MARK, LCD_DATA1_PG1_MARK, LCD_DATA0_PG0_MARK,
-	LCD_DATA23_PJ23_MARK, LCD_DATA22_PJ22_MARK, LCD_DATA21_PJ21_MARK,
-	LCD_DATA20_PJ20_MARK, LCD_DATA19_PJ19_MARK, LCD_DATA18_PJ18_MARK,
-	LCD_DATA17_PJ17_MARK, LCD_DATA16_PJ16_MARK, LCD_DATA15_PJ15_MARK,
-	LCD_DATA14_PJ14_MARK, LCD_DATA13_PJ13_MARK, LCD_DATA12_PJ12_MARK,
-	LCD_DATA11_PJ11_MARK, LCD_DATA10_PJ10_MARK, LCD_DATA9_PJ9_MARK,
-	LCD_DATA8_PJ8_MARK, LCD_DATA7_PJ7_MARK, LCD_DATA6_PJ6_MARK,
-	LCD_DATA5_PJ5_MARK, LCD_DATA4_PJ4_MARK, LCD_DATA3_PJ3_MARK,
-	LCD_DATA2_PJ2_MARK, LCD_DATA1_PJ1_MARK, LCD_DATA0_PJ0_MARK,
-	LCD_TCON6_MARK, LCD_TCON5_MARK, LCD_TCON4_MARK,
-	LCD_TCON3_MARK, LCD_TCON2_MARK, LCD_TCON1_MARK, LCD_TCON0_MARK,
-	LCD_M_DISP_MARK,
-	PINMUX_MARK_END,
-};
-
-static const u16 pinmux_data[] = {
-	/* Port A */
-	PINMUX_DATA(PA1_DATA, PA1_IN),
-	PINMUX_DATA(PA0_DATA, PA0_IN),
-
-	/* Port B */
-	PINMUX_DATA(PB22_DATA, PB22MD_000, PB22_IN, PB22_OUT),
-	PINMUX_DATA(A22_MARK, PB22MD_001),
-	PINMUX_DATA(CTX2_MARK, PB22MD_010),
-	PINMUX_DATA(IETXD_MARK, PB22MD_011),
-	PINMUX_DATA(CS4_MARK, PB22MD_100),
-
-	PINMUX_DATA(PB21_DATA, PB21MD_00, PB21_IN, PB21_OUT),
-	PINMUX_DATA(A21_MARK, PB21MD_01),
-	PINMUX_DATA(CRX2_MARK, PB21MD_10),
-	PINMUX_DATA(IERXD_MARK, PB21MD_11),
-
-	PINMUX_DATA(A20_MARK, PB20MD_001),
-	PINMUX_DATA(A19_MARK, PB19MD_001),
-	PINMUX_DATA(A18_MARK, PB18MD_001),
-	PINMUX_DATA(A17_MARK, PB17MD_001),
-	PINMUX_DATA(A16_MARK, PB16MD_001),
-	PINMUX_DATA(A15_MARK, PB15MD_001),
-	PINMUX_DATA(A14_MARK, PB14MD_001),
-	PINMUX_DATA(A13_MARK, PB13MD_001),
-	PINMUX_DATA(A12_MARK, PB12MD_01),
-	PINMUX_DATA(A11_MARK, PB11MD_01),
-	PINMUX_DATA(A10_MARK, PB10MD_01),
-	PINMUX_DATA(A9_MARK, PB9MD_01),
-	PINMUX_DATA(A8_MARK, PB8MD_01),
-	PINMUX_DATA(A7_MARK, PB7MD_01),
-	PINMUX_DATA(A6_MARK, PB6MD_01),
-	PINMUX_DATA(A5_MARK, PB5MD_01),
-	PINMUX_DATA(A4_MARK, PB4MD_01),
-	PINMUX_DATA(A3_MARK, PB3MD_01),
-	PINMUX_DATA(A2_MARK, PB2MD_01),
-	PINMUX_DATA(A1_MARK, PB1MD_01),
-
-	/* Port C */
-	PINMUX_DATA(PC8_DATA, PC8MD_000),
-	PINMUX_DATA(CS3_MARK, PC8MD_001),
-	PINMUX_DATA(TXD7_MARK, PC8MD_010),
-	PINMUX_DATA(CTX1_MARK, PC8MD_011),
-	PINMUX_DATA(CTX0_CTX1_MARK, PC8MD_100),
-
-	PINMUX_DATA(PC7_DATA, PC7MD_000),
-	PINMUX_DATA(CKE_MARK, PC7MD_001),
-	PINMUX_DATA(RXD7_MARK, PC7MD_010),
-	PINMUX_DATA(CRX1_MARK, PC7MD_011),
-	PINMUX_DATA(CRX0_CRX1_MARK, PC7MD_100),
-	PINMUX_DATA(IRQ1_PC_MARK, PC7MD_101),
-
-	PINMUX_DATA(PC6_DATA, PC6MD_000),
-	PINMUX_DATA(CAS_MARK, PC6MD_001),
-	PINMUX_DATA(SCK7_MARK, PC6MD_010),
-	PINMUX_DATA(CTX0_MARK, PC6MD_011),
-	PINMUX_DATA(CTX0_CTX1_CTX2_MARK, PC6MD_100),
-
-	PINMUX_DATA(PC5_DATA, PC5MD_000),
-	PINMUX_DATA(RAS_MARK, PC5MD_001),
-	PINMUX_DATA(CRX0_MARK, PC5MD_011),
-	PINMUX_DATA(CTX0_CTX1_CTX2_MARK, PC5MD_100),
-	PINMUX_DATA(IRQ0_PC_MARK, PC5MD_101),
-
-	PINMUX_DATA(PC4_DATA, PC4MD_00),
-	PINMUX_DATA(WE1DQMUWE_MARK, PC4MD_01),
-	PINMUX_DATA(TXD6_MARK, PC4MD_10),
-
-	PINMUX_DATA(PC3_DATA, PC3MD_00),
-	PINMUX_DATA(WE0DQML_MARK, PC3MD_01),
-	PINMUX_DATA(RXD6_MARK, PC3MD_10),
-
-	PINMUX_DATA(PC2_DATA, PC2MD_00),
-	PINMUX_DATA(RDWR_MARK, PC2MD_01),
-	PINMUX_DATA(SCK5_MARK, PC2MD_10),
-
-	PINMUX_DATA(PC1_DATA, PC1MD_0),
-	PINMUX_DATA(RD_MARK, PC1MD_1),
-
-	PINMUX_DATA(PC0_DATA, PC0MD_0),
-	PINMUX_DATA(CS0_MARK, PC0MD_1),
-
-	/* Port D */
-	PINMUX_DATA(D15_MARK, PD15MD_01),
-	PINMUX_DATA(D14_MARK, PD14MD_01),
-
-	PINMUX_DATA(PD13_DATA, PD13MD_00),
-	PINMUX_DATA(D13_MARK, PD13MD_01),
-	PINMUX_DATA(PWM2F_MARK, PD13MD_10),
-
-	PINMUX_DATA(PD12_DATA, PD12MD_00),
-	PINMUX_DATA(D12_MARK, PD12MD_01),
-	PINMUX_DATA(PWM2E_MARK, PD12MD_10),
-
-	PINMUX_DATA(D11_MARK, PD11MD_01),
-	PINMUX_DATA(D10_MARK, PD10MD_01),
-	PINMUX_DATA(D9_MARK, PD9MD_01),
-	PINMUX_DATA(D8_MARK, PD8MD_01),
-	PINMUX_DATA(D7_MARK, PD7MD_01),
-	PINMUX_DATA(D6_MARK, PD6MD_01),
-	PINMUX_DATA(D5_MARK, PD5MD_01),
-	PINMUX_DATA(D4_MARK, PD4MD_01),
-	PINMUX_DATA(D3_MARK, PD3MD_01),
-	PINMUX_DATA(D2_MARK, PD2MD_01),
-	PINMUX_DATA(D1_MARK, PD1MD_01),
-	PINMUX_DATA(D0_MARK, PD0MD_01),
-
-	/* Port E */
-	PINMUX_DATA(PE7_DATA, PE7MD_00),
-	PINMUX_DATA(SDA3_MARK, PE7MD_01),
-	PINMUX_DATA(RXD7_MARK, PE7MD_10),
-
-	PINMUX_DATA(PE6_DATA, PE6MD_00),
-	PINMUX_DATA(SCL3_MARK, PE6MD_01),
-	PINMUX_DATA(RXD6_MARK, PE6MD_10),
-
-	PINMUX_DATA(PE5_DATA, PE5MD_00),
-	PINMUX_DATA(SDA2_MARK, PE5MD_01),
-	PINMUX_DATA(RXD5_MARK, PE5MD_10),
-	PINMUX_DATA(DV_HSYNC_MARK, PE5MD_11),
-
-	PINMUX_DATA(PE4_DATA, PE4MD_00),
-	PINMUX_DATA(SCL2_MARK, PE4MD_01),
-	PINMUX_DATA(DV_VSYNC_MARK, PE4MD_11),
-
-	PINMUX_DATA(PE3_DATA, PE3MD_000),
-	PINMUX_DATA(SDA1_MARK, PE3MD_001),
-	PINMUX_DATA(TCLKD_MARK, PE3MD_010),
-	PINMUX_DATA(ADTRG_MARK, PE3MD_011),
-	PINMUX_DATA(DV_HSYNC_MARK, PE3MD_100),
-
-	PINMUX_DATA(PE2_DATA, PE2MD_000),
-	PINMUX_DATA(SCL1_MARK, PE2MD_001),
-	PINMUX_DATA(TCLKD_MARK, PE2MD_010),
-	PINMUX_DATA(IOIS16_MARK, PE2MD_011),
-	PINMUX_DATA(DV_VSYNC_MARK, PE2MD_100),
-
-	PINMUX_DATA(PE1_DATA, PE1MD_000),
-	PINMUX_DATA(SDA0_MARK, PE1MD_001),
-	PINMUX_DATA(TCLKB_MARK, PE1MD_010),
-	PINMUX_DATA(AUDIO_CLK_MARK, PE1MD_010),
-	PINMUX_DATA(DV_CLK_MARK, PE1MD_100),
-
-	PINMUX_DATA(PE0_DATA, PE0MD_00),
-	PINMUX_DATA(SCL0_MARK, PE0MD_01),
-	PINMUX_DATA(TCLKA_MARK, PE0MD_10),
-	PINMUX_DATA(LCD_EXTCLK_MARK, PE0MD_11),
-
-	/* Port F */
-	PINMUX_DATA(PF23_DATA, PF23MD_000),
-	PINMUX_DATA(SD_D2_MARK, PF23MD_001),
-	PINMUX_DATA(TXD3_MARK, PF23MD_100),
-	PINMUX_DATA(MMC_D2_MARK, PF23MD_101),
-
-	PINMUX_DATA(PF22_DATA, PF22MD_000),
-	PINMUX_DATA(SD_D3_MARK, PF22MD_001),
-	PINMUX_DATA(RXD3_MARK, PF22MD_100),
-	PINMUX_DATA(MMC_D3_MARK, PF22MD_101),
-
-	PINMUX_DATA(PF21_DATA, PF21MD_000),
-	PINMUX_DATA(SD_CMD_MARK, PF21MD_001),
-	PINMUX_DATA(SCK3_MARK, PF21MD_100),
-	PINMUX_DATA(MMC_CMD_MARK, PF21MD_101),
-
-	PINMUX_DATA(PF20_DATA, PF20MD_000),
-	PINMUX_DATA(SD_CLK_MARK, PF20MD_001),
-	PINMUX_DATA(SSIDATA3_MARK, PF20MD_010),
-	PINMUX_DATA(MMC_CLK_MARK, PF20MD_101),
-
-	PINMUX_DATA(PF19_DATA, PF19MD_000),
-	PINMUX_DATA(SD_D0_MARK, PF19MD_001),
-	PINMUX_DATA(SSIWS3_MARK, PF19MD_010),
-	PINMUX_DATA(IRQ7_PF_MARK, PF19MD_100),
-	PINMUX_DATA(MMC_D0_MARK, PF19MD_101),
-
-	PINMUX_DATA(PF18_DATA, PF18MD_000),
-	PINMUX_DATA(SD_D1_MARK, PF18MD_001),
-	PINMUX_DATA(SSISCK3_MARK, PF18MD_010),
-	PINMUX_DATA(IRQ6_PF_MARK, PF18MD_100),
-	PINMUX_DATA(MMC_D1_MARK, PF18MD_101),
-
-	PINMUX_DATA(PF17_DATA, PF17MD_000),
-	PINMUX_DATA(SD_WP_MARK, PF17MD_001),
-	PINMUX_DATA(FRB_MARK, PF17MD_011),
-	PINMUX_DATA(IRQ5_PF_MARK, PF17MD_100),
-
-	PINMUX_DATA(PF16_DATA, PF16MD_000),
-	PINMUX_DATA(SD_CD_MARK, PF16MD_001),
-	PINMUX_DATA(FCE_MARK, PF16MD_011),
-	PINMUX_DATA(IRQ4_PF_MARK, PF16MD_100),
-	PINMUX_DATA(MMC_CD_MARK, PF16MD_101),
-
-	PINMUX_DATA(PF15_DATA, PF15MD_000),
-	PINMUX_DATA(A0_MARK, PF15MD_001),
-	PINMUX_DATA(SSIDATA2_MARK, PF15MD_010),
-	PINMUX_DATA(WDTOVF_MARK, PF15MD_011),
-	PINMUX_DATA(TXD2_MARK, PF15MD_100),
-
-	PINMUX_DATA(PF14_DATA, PF14MD_000),
-	PINMUX_DATA(A25_MARK, PF14MD_001),
-	PINMUX_DATA(SSIWS2_MARK, PF14MD_010),
-	PINMUX_DATA(RXD2_MARK, PF14MD_100),
-
-	PINMUX_DATA(PF13_DATA, PF13MD_000),
-	PINMUX_DATA(A24_MARK, PF13MD_001),
-	PINMUX_DATA(SSISCK2_MARK, PF13MD_010),
-	PINMUX_DATA(SCK2_MARK, PF13MD_100),
-
-	PINMUX_DATA(PF12_DATA, PF12MD_000),
-	PINMUX_DATA(SSIDATA1_MARK, PF12MD_010),
-	PINMUX_DATA(DV_DATA12_MARK, PF12MD_011),
-	PINMUX_DATA(TXD1_MARK, PF12MD_100),
-	PINMUX_DATA(MMC_D7_MARK, PF12MD_101),
-
-	PINMUX_DATA(PF11_DATA, PF11MD_000),
-	PINMUX_DATA(SSIWS1_MARK, PF11MD_010),
-	PINMUX_DATA(DV_DATA2_MARK, PF11MD_011),
-	PINMUX_DATA(RXD1_MARK, PF11MD_100),
-	PINMUX_DATA(MMC_D6_MARK, PF11MD_101),
-
-	PINMUX_DATA(PF10_DATA, PF10MD_000),
-	PINMUX_DATA(CS1_MARK, PF10MD_001),
-	PINMUX_DATA(SSISCK1_MARK, PF10MD_010),
-	PINMUX_DATA(DV_DATA1_MARK, PF10MD_011),
-	PINMUX_DATA(SCK1_MARK, PF10MD_100),
-	PINMUX_DATA(MMC_D5_MARK, PF10MD_101),
-
-	PINMUX_DATA(PF9_DATA, PF9MD_000),
-	PINMUX_DATA(BS_MARK, PF9MD_001),
-	PINMUX_DATA(DV_DATA0_MARK, PF9MD_011),
-	PINMUX_DATA(SCK0_MARK, PF9MD_100),
-	PINMUX_DATA(MMC_D4_MARK, PF9MD_101),
-	PINMUX_DATA(RTS1_MARK, PF9MD_110),
-
-	PINMUX_DATA(PF8_DATA, PF8MD_000),
-	PINMUX_DATA(A23_MARK, PF8MD_001),
-	PINMUX_DATA(TXD0_MARK, PF8MD_100),
-
-	PINMUX_DATA(PF7_DATA, PF7MD_000),
-	PINMUX_DATA(SSIRXD0_MARK, PF7MD_010),
-	PINMUX_DATA(RXD0_MARK, PF7MD_100),
-	PINMUX_DATA(CTS1_MARK, PF7MD_110),
-
-	PINMUX_DATA(PF6_DATA, PF6MD_000),
-	PINMUX_DATA(CE2A_MARK, PF6MD_001),
-	PINMUX_DATA(SSITXD0_MARK, PF6MD_010),
-
-	PINMUX_DATA(PF5_DATA, PF5MD_000),
-	PINMUX_DATA(SSIWS0_MARK, PF5MD_010),
-
-	PINMUX_DATA(PF4_DATA, PF4MD_000),
-	PINMUX_DATA(CS5CE1A_MARK, PF4MD_001),
-	PINMUX_DATA(SSISCK0_MARK, PF4MD_010),
-
-	PINMUX_DATA(PF3_DATA, PF3MD_000),
-	PINMUX_DATA(CS2_MARK, PF3MD_001),
-	PINMUX_DATA(MISO1_MARK, PF3MD_011),
-	PINMUX_DATA(TIOC4D_MARK, PF3MD_100),
-
-	PINMUX_DATA(PF2_DATA, PF2MD_000),
-	PINMUX_DATA(WAIT_MARK, PF2MD_001),
-	PINMUX_DATA(MOSI1_MARK, PF2MD_011),
-	PINMUX_DATA(TIOC4C_MARK, PF2MD_100),
-	PINMUX_DATA(TEND0_MARK, PF2MD_101),
-
-	PINMUX_DATA(PF1_DATA, PF1MD_000),
-	PINMUX_DATA(BACK_MARK, PF1MD_001),
-	PINMUX_DATA(SSL10_MARK, PF1MD_011),
-	PINMUX_DATA(TIOC4B_MARK, PF1MD_100),
-	PINMUX_DATA(DACK0_MARK, PF1MD_101),
-
-	PINMUX_DATA(PF0_DATA, PF0MD_000),
-	PINMUX_DATA(BREQ_MARK, PF0MD_001),
-	PINMUX_DATA(RSPCK1_MARK, PF0MD_011),
-	PINMUX_DATA(TIOC4A_MARK, PF0MD_100),
-	PINMUX_DATA(DREQ0_MARK, PF0MD_101),
-
-	/* Port G */
-	PINMUX_DATA(PG27_DATA, PG27MD_00),
-	PINMUX_DATA(LCD_TCON2_MARK, PG27MD_10),
-	PINMUX_DATA(LCD_EXTCLK_MARK, PG27MD_11),
-	PINMUX_DATA(LCD_DE_MARK, PG27MD_11),
-
-	PINMUX_DATA(PG26_DATA, PG26MD_00),
-	PINMUX_DATA(LCD_TCON1_MARK, PG26MD_10),
-	PINMUX_DATA(LCD_HSYNC_MARK, PG26MD_10),
-
-	PINMUX_DATA(PG25_DATA, PG25MD_00),
-	PINMUX_DATA(LCD_TCON0_MARK, PG25MD_10),
-	PINMUX_DATA(LCD_VSYNC_MARK, PG25MD_10),
-
-	PINMUX_DATA(PG24_DATA, PG24MD_00),
-	PINMUX_DATA(LCD_CLK_MARK, PG24MD_10),
-
-	PINMUX_DATA(PG23_DATA, PG23MD_000),
-	PINMUX_DATA(LCD_DATA23_PG23_MARK, PG23MD_010),
-	PINMUX_DATA(LCD_TCON6_MARK, PG23MD_011),
-	PINMUX_DATA(TXD5_MARK, PG23MD_100),
-
-	PINMUX_DATA(PG22_DATA, PG22MD_000),
-	PINMUX_DATA(LCD_DATA22_PG22_MARK, PG22MD_010),
-	PINMUX_DATA(LCD_TCON5_MARK, PG22MD_011),
-	PINMUX_DATA(RXD5_MARK, PG22MD_100),
-
-	PINMUX_DATA(PG21_DATA, PG21MD_000),
-	PINMUX_DATA(DV_DATA7_MARK, PG21MD_001),
-	PINMUX_DATA(LCD_DATA21_PG21_MARK, PG21MD_010),
-	PINMUX_DATA(LCD_TCON4_MARK, PG21MD_011),
-	PINMUX_DATA(TXD4_MARK, PG21MD_100),
-
-	PINMUX_DATA(PG20_DATA, PG20MD_000),
-	PINMUX_DATA(DV_DATA6_MARK, PG20MD_001),
-	PINMUX_DATA(LCD_DATA20_PG20_MARK, PG21MD_010),
-	PINMUX_DATA(LCD_TCON3_MARK, PG20MD_011),
-	PINMUX_DATA(RXD4_MARK, PG20MD_100),
-
-	PINMUX_DATA(PG19_DATA, PG19MD_000),
-	PINMUX_DATA(DV_DATA5_MARK, PG19MD_001),
-	PINMUX_DATA(LCD_DATA19_PG19_MARK, PG19MD_010),
-	PINMUX_DATA(SPDIF_OUT_MARK, PG19MD_011),
-	PINMUX_DATA(SCK5_MARK, PG19MD_100),
-
-	PINMUX_DATA(PG18_DATA, PG18MD_000),
-	PINMUX_DATA(DV_DATA4_MARK, PG18MD_001),
-	PINMUX_DATA(LCD_DATA18_PG18_MARK, PG18MD_010),
-	PINMUX_DATA(SPDIF_IN_MARK, PG18MD_011),
-	PINMUX_DATA(SCK4_MARK, PG18MD_100),
-
-// TODO hardware manual has PG17 3 bits wide in reg picture and 2 bits in description
-// we're going with 2 bits
-	PINMUX_DATA(PG17_DATA, PG17MD_00),
-	PINMUX_DATA(WE3ICIOWRAHDQMUU_MARK, PG17MD_01),
-	PINMUX_DATA(LCD_DATA17_PG17_MARK, PG17MD_10),
-
-// TODO hardware manual has PG16 3 bits wide in reg picture and 2 bits in description
-// we're going with 2 bits
-	PINMUX_DATA(PG16_DATA, PG16MD_00),
-	PINMUX_DATA(WE2ICIORDDQMUL_MARK, PG16MD_01),
-	PINMUX_DATA(LCD_DATA16_PG16_MARK, PG16MD_10),
-
-	PINMUX_DATA(PG15_DATA, PG15MD_00),
-	PINMUX_DATA(D31_MARK, PG15MD_01),
-	PINMUX_DATA(LCD_DATA15_PG15_MARK, PG15MD_10),
-	PINMUX_DATA(PINT7_PG_MARK, PG15MD_11),
-
-	PINMUX_DATA(PG14_DATA, PG14MD_00),
-	PINMUX_DATA(D30_MARK, PG14MD_01),
-	PINMUX_DATA(LCD_DATA14_PG14_MARK, PG14MD_10),
-	PINMUX_DATA(PINT6_PG_MARK, PG14MD_11),
-
-	PINMUX_DATA(PG13_DATA, PG13MD_00),
-	PINMUX_DATA(D29_MARK, PG13MD_01),
-	PINMUX_DATA(LCD_DATA13_PG13_MARK, PG13MD_10),
-	PINMUX_DATA(PINT5_PG_MARK, PG13MD_11),
-
-	PINMUX_DATA(PG12_DATA, PG12MD_00),
-	PINMUX_DATA(D28_MARK, PG12MD_01),
-	PINMUX_DATA(LCD_DATA12_PG12_MARK, PG12MD_10),
-	PINMUX_DATA(PINT4_PG_MARK, PG12MD_11),
-
-	PINMUX_DATA(PG11_DATA, PG11MD_000),
-	PINMUX_DATA(D27_MARK, PG11MD_001),
-	PINMUX_DATA(LCD_DATA11_PG11_MARK, PG11MD_010),
-	PINMUX_DATA(PINT3_PG_MARK, PG11MD_011),
-	PINMUX_DATA(TIOC3D_MARK, PG11MD_100),
-
-	PINMUX_DATA(PG10_DATA, PG10MD_000),
-	PINMUX_DATA(D26_MARK, PG10MD_001),
-	PINMUX_DATA(LCD_DATA10_PG10_MARK, PG10MD_010),
-	PINMUX_DATA(PINT2_PG_MARK, PG10MD_011),
-	PINMUX_DATA(TIOC3C_MARK, PG10MD_100),
-
-	PINMUX_DATA(PG9_DATA, PG9MD_000),
-	PINMUX_DATA(D25_MARK, PG9MD_001),
-	PINMUX_DATA(LCD_DATA9_PG9_MARK, PG9MD_010),
-	PINMUX_DATA(PINT1_PG_MARK, PG9MD_011),
-	PINMUX_DATA(TIOC3B_MARK, PG9MD_100),
-
-	PINMUX_DATA(PG8_DATA, PG8MD_000),
-	PINMUX_DATA(D24_MARK, PG8MD_001),
-	PINMUX_DATA(LCD_DATA8_PG8_MARK, PG8MD_010),
-	PINMUX_DATA(PINT0_PG_MARK, PG8MD_011),
-	PINMUX_DATA(TIOC3A_MARK, PG8MD_100),
-
-	PINMUX_DATA(PG7_DATA, PG7MD_000),
-	PINMUX_DATA(D23_MARK, PG7MD_001),
-	PINMUX_DATA(LCD_DATA7_PG7_MARK, PG7MD_010),
-	PINMUX_DATA(IRQ7_PG_MARK, PG7MD_011),
-	PINMUX_DATA(TIOC2B_MARK, PG7MD_100),
-
-	PINMUX_DATA(PG6_DATA, PG6MD_000),
-	PINMUX_DATA(D22_MARK, PG6MD_001),
-	PINMUX_DATA(LCD_DATA6_PG6_MARK, PG6MD_010),
-	PINMUX_DATA(IRQ6_PG_MARK, PG6MD_011),
-	PINMUX_DATA(TIOC2A_MARK, PG6MD_100),
-
-	PINMUX_DATA(PG5_DATA, PG5MD_000),
-	PINMUX_DATA(D21_MARK, PG5MD_001),
-	PINMUX_DATA(LCD_DATA5_PG5_MARK, PG5MD_010),
-	PINMUX_DATA(IRQ5_PG_MARK, PG5MD_011),
-	PINMUX_DATA(TIOC1B_MARK, PG5MD_100),
-
-	PINMUX_DATA(PG4_DATA, PG4MD_000),
-	PINMUX_DATA(D20_MARK, PG4MD_001),
-	PINMUX_DATA(LCD_DATA4_PG4_MARK, PG4MD_010),
-	PINMUX_DATA(IRQ4_PG_MARK, PG4MD_011),
-	PINMUX_DATA(TIOC1A_MARK, PG4MD_100),
-
-	PINMUX_DATA(PG3_DATA, PG3MD_000),
-	PINMUX_DATA(D19_MARK, PG3MD_001),
-	PINMUX_DATA(LCD_DATA3_PG3_MARK, PG3MD_010),
-	PINMUX_DATA(IRQ3_PG_MARK, PG3MD_011),
-	PINMUX_DATA(TIOC0D_MARK, PG3MD_100),
-
-	PINMUX_DATA(PG2_DATA, PG2MD_000),
-	PINMUX_DATA(D18_MARK, PG2MD_001),
-	PINMUX_DATA(LCD_DATA2_PG2_MARK, PG2MD_010),
-	PINMUX_DATA(IRQ2_PG_MARK, PG2MD_011),
-	PINMUX_DATA(TIOC0C_MARK, PG2MD_100),
-
-	PINMUX_DATA(PG1_DATA, PG1MD_000),
-	PINMUX_DATA(D17_MARK, PG1MD_001),
-	PINMUX_DATA(LCD_DATA1_PG1_MARK, PG1MD_010),
-	PINMUX_DATA(IRQ1_PG_MARK, PG1MD_011),
-	PINMUX_DATA(TIOC0B_MARK, PG1MD_100),
-
-	PINMUX_DATA(PG0_DATA, PG0MD_000),
-	PINMUX_DATA(D16_MARK, PG0MD_001),
-	PINMUX_DATA(LCD_DATA0_PG0_MARK, PG0MD_010),
-	PINMUX_DATA(IRQ0_PG_MARK, PG0MD_011),
-	PINMUX_DATA(TIOC0A_MARK, PG0MD_100),
-
-	/* Port H */
-	PINMUX_DATA(PH7_DATA, PH7MD_00),
-	PINMUX_DATA(PHAN7_MARK, PH7MD_01),
-	PINMUX_DATA(PINT7_PH_MARK, PH7MD_10),
-
-	PINMUX_DATA(PH6_DATA, PH6MD_00),
-	PINMUX_DATA(PHAN6_MARK, PH6MD_01),
-	PINMUX_DATA(PINT6_PH_MARK, PH6MD_10),
-
-	PINMUX_DATA(PH5_DATA, PH5MD_00),
-	PINMUX_DATA(PHAN5_MARK, PH5MD_01),
-	PINMUX_DATA(PINT5_PH_MARK, PH5MD_10),
-	PINMUX_DATA(LCD_EXTCLK_MARK, PH5MD_11),
-
-	PINMUX_DATA(PH4_DATA, PH4MD_00),
-	PINMUX_DATA(PHAN4_MARK, PH4MD_01),
-	PINMUX_DATA(PINT4_PH_MARK, PH4MD_10),
-
-	PINMUX_DATA(PH3_DATA, PH3MD_00),
-	PINMUX_DATA(PHAN3_MARK, PH3MD_01),
-	PINMUX_DATA(PINT3_PH_MARK, PH3MD_10),
-
-	PINMUX_DATA(PH2_DATA, PH2MD_00),
-	PINMUX_DATA(PHAN2_MARK, PH2MD_01),
-	PINMUX_DATA(PINT2_PH_MARK, PH2MD_10),
-
-	PINMUX_DATA(PH1_DATA, PH1MD_00),
-	PINMUX_DATA(PHAN1_MARK, PH1MD_01),
-	PINMUX_DATA(PINT1_PH_MARK, PH1MD_10),
-
-	PINMUX_DATA(PH0_DATA, PH0MD_00),
-	PINMUX_DATA(PHAN0_MARK, PH0MD_01),
-	PINMUX_DATA(PINT0_PH_MARK, PH0MD_10),
-
-	/* Port I - not on device */
-
-	/* Port J */
-	PINMUX_DATA(PJ31_DATA, PJ31MD_0),
-	PINMUX_DATA(DV_CLK_MARK, PJ31MD_1),
-
-	PINMUX_DATA(PJ30_DATA, PJ30MD_000),
-	PINMUX_DATA(SSIDATA5_MARK, PJ30MD_010),
-	PINMUX_DATA(TIOC2B_MARK, PJ30MD_100),
-	PINMUX_DATA(IETXD_MARK, PJ30MD_101),
-
-	PINMUX_DATA(PJ29_DATA, PJ29MD_000),
-	PINMUX_DATA(SSIWS5_MARK, PJ29MD_010),
-	PINMUX_DATA(TIOC2A_MARK, PJ29MD_100),
-	PINMUX_DATA(IERXD_MARK, PJ29MD_101),
-
-	PINMUX_DATA(PJ28_DATA, PJ28MD_000),
-	PINMUX_DATA(SSISCK5_MARK, PJ28MD_010),
-	PINMUX_DATA(TIOC1B_MARK, PJ28MD_100),
-	PINMUX_DATA(RTS7_MARK, PJ28MD_101),
-
-	PINMUX_DATA(PJ27_DATA, PJ27MD_000),
-	PINMUX_DATA(TIOC1A_MARK, PJ27MD_100),
-	PINMUX_DATA(CTS7_MARK, PJ27MD_101),
-
-	PINMUX_DATA(PJ26_DATA, PJ26MD_000),
-	PINMUX_DATA(SSIDATA4_MARK, PJ26MD_010),
-	PINMUX_DATA(LCD_TCON5_MARK, PJ26MD_011),
-	PINMUX_DATA(TXD7_MARK, PJ26MD_101),
-
-	PINMUX_DATA(PJ25_DATA, PJ25MD_000),
-	PINMUX_DATA(SSIWS4_MARK, PJ25MD_010),
-	PINMUX_DATA(LCD_TCON4_MARK, PJ25MD_011),
-	PINMUX_DATA(SPDIF_OUT_MARK, PJ25MD_100),
-	PINMUX_DATA(RXD7_MARK, PJ25MD_101),
-
-	PINMUX_DATA(PJ24_DATA, PJ24MD_000),
-	PINMUX_DATA(SSISCK4_MARK, PJ24MD_010),
-	PINMUX_DATA(LCD_TCON3_MARK, PJ24MD_011),
-	PINMUX_DATA(SPDIF_IN_MARK, PJ24MD_100),
-	PINMUX_DATA(SCK7_MARK, PJ24MD_101),
-
-	PINMUX_DATA(PJ23_DATA, PJ23MD_000),
-	PINMUX_DATA(DV_DATA23_MARK, PJ23MD_001),
-	PINMUX_DATA(LCD_DATA23_PJ23_MARK, PJ23MD_010),
-	PINMUX_DATA(LCD_TCON6_MARK, PJ23MD_011),
-	PINMUX_DATA(IRQ3_PJ_MARK, PJ23MD_100),
-	PINMUX_DATA(CTX1_PJ23_MARK, PJ23MD_101),
-	PINMUX_DATA(CTX0_CTX1_PJ23_MARK, PJ23MD_110),
-
-	PINMUX_DATA(PJ22_DATA, PJ22MD_000),
-	PINMUX_DATA(DV_DATA22_MARK, PJ22MD_001),
-	PINMUX_DATA(LCD_DATA22_PJ22_MARK, PJ22MD_010),
-	PINMUX_DATA(LCD_TCON5_MARK, PJ22MD_011),
-	PINMUX_DATA(IRQ2_PJ_MARK, PJ22MD_100),
-	PINMUX_DATA(CRX1_PJ22_MARK, PJ22MD_101),
-	PINMUX_DATA(CRX0_CRX1_PJ22_MARK, PJ22MD_110),
-
-	PINMUX_DATA(PJ21_DATA, PJ21MD_000),
-	PINMUX_DATA(DV_DATA21_MARK, PJ21MD_001),
-	PINMUX_DATA(LCD_DATA21_PJ21_MARK, PJ21MD_010),
-	PINMUX_DATA(LCD_TCON4_MARK, PJ21MD_011),
-	PINMUX_DATA(IRQ1_PJ_MARK, PJ21MD_100),
-	PINMUX_DATA(CTX2_PJ21_MARK, PJ21MD_101),
-	PINMUX_DATA(CTX0_CTX1_CTX2_PJ21_MARK, PJ21MD_110),
-
-	PINMUX_DATA(PJ20_DATA, PJ20MD_000),
-	PINMUX_DATA(DV_DATA20_MARK, PJ20MD_001),
-	PINMUX_DATA(LCD_DATA20_PJ20_MARK, PJ20MD_010),
-	PINMUX_DATA(LCD_TCON3_MARK, PJ20MD_011),
-	PINMUX_DATA(IRQ0_PJ_MARK, PJ20MD_100),
-	PINMUX_DATA(CRX2_PJ20_MARK, PJ20MD_101),
-	PINMUX_DATA(CRX0_CRX1_CRX2_PJ20_MARK, PJ20MD_110),
-
-	PINMUX_DATA(PJ19_DATA, PJ19MD_000),
-	PINMUX_DATA(DV_DATA19_MARK, PJ19MD_001),
-	PINMUX_DATA(LCD_DATA19_PJ19_MARK, PJ19MD_010),
-	PINMUX_DATA(MISO0_PJ19_MARK, PJ19MD_011),
-	PINMUX_DATA(TIOC0D_MARK, PJ19MD_100),
-	PINMUX_DATA(SIOFRXD_MARK, PJ19MD_101),
-	PINMUX_DATA(AUDIO_XOUT_MARK, PJ19MD_110),
-
-	PINMUX_DATA(PJ18_DATA, PJ18MD_000),
-	PINMUX_DATA(DV_DATA18_MARK, PJ18MD_001),
-	PINMUX_DATA(LCD_DATA18_PJ18_MARK, PJ18MD_010),
-	PINMUX_DATA(MOSI0_PJ18_MARK, PJ18MD_011),
-	PINMUX_DATA(TIOC0C_MARK, PJ18MD_100),
-	PINMUX_DATA(SIOFTXD_MARK, PJ18MD_101),
-
-	PINMUX_DATA(PJ17_DATA, PJ17MD_000),
-	PINMUX_DATA(DV_DATA17_MARK, PJ17MD_001),
-	PINMUX_DATA(LCD_DATA17_PJ17_MARK, PJ17MD_010),
-	PINMUX_DATA(SSL00_PJ17_MARK, PJ17MD_011),
-	PINMUX_DATA(TIOC0B_MARK, PJ17MD_100),
-	PINMUX_DATA(SIOFSYNC_MARK, PJ17MD_101),
-
-	PINMUX_DATA(PJ16_DATA, PJ16MD_000),
-	PINMUX_DATA(DV_DATA16_MARK, PJ16MD_001),
-	PINMUX_DATA(LCD_DATA16_PJ16_MARK, PJ16MD_010),
-	PINMUX_DATA(RSPCK0_PJ16_MARK, PJ16MD_011),
-	PINMUX_DATA(TIOC0A_MARK, PJ16MD_100),
-	PINMUX_DATA(SIOFSCK_MARK, PJ16MD_101),
-
-	PINMUX_DATA(PJ15_DATA, PJ15MD_000),
-	PINMUX_DATA(DV_DATA15_MARK, PJ15MD_001),
-	PINMUX_DATA(LCD_DATA15_PJ15_MARK, PJ15MD_010),
-	PINMUX_DATA(PINT7_PJ_MARK, PJ15MD_011),
-	PINMUX_DATA(PWM2H_MARK, PJ15MD_100),
-	PINMUX_DATA(TXD7_MARK, PJ15MD_101),
-
-	PINMUX_DATA(PJ14_DATA, PJ14MD_000),
-	PINMUX_DATA(DV_DATA14_MARK, PJ14MD_001),
-	PINMUX_DATA(LCD_DATA14_PJ14_MARK, PJ14MD_010),
-	PINMUX_DATA(PINT6_PJ_MARK, PJ14MD_011),
-	PINMUX_DATA(PWM2G_MARK, PJ14MD_100),
-	PINMUX_DATA(TXD6_MARK, PJ14MD_101),
-
-	PINMUX_DATA(PJ13_DATA, PJ13MD_000),
-	PINMUX_DATA(DV_DATA13_MARK, PJ13MD_001),
-	PINMUX_DATA(LCD_DATA13_PJ13_MARK, PJ13MD_010),
-	PINMUX_DATA(PINT5_PJ_MARK, PJ13MD_011),
-	PINMUX_DATA(PWM2F_MARK, PJ13MD_100),
-	PINMUX_DATA(TXD5_MARK, PJ13MD_101),
-
-	PINMUX_DATA(PJ12_DATA, PJ12MD_000),
-	PINMUX_DATA(DV_DATA12_MARK, PJ12MD_001),
-	PINMUX_DATA(LCD_DATA12_PJ12_MARK, PJ12MD_010),
-	PINMUX_DATA(PINT4_PJ_MARK, PJ12MD_011),
-	PINMUX_DATA(PWM2E_MARK, PJ12MD_100),
-	PINMUX_DATA(SCK7_MARK, PJ12MD_101),
-
-	PINMUX_DATA(PJ11_DATA, PJ11MD_000),
-	PINMUX_DATA(DV_DATA11_MARK, PJ11MD_001),
-	PINMUX_DATA(LCD_DATA11_PJ11_MARK, PJ11MD_010),
-	PINMUX_DATA(PINT3_PJ_MARK, PJ11MD_011),
-	PINMUX_DATA(PWM2D_MARK, PJ11MD_100),
-	PINMUX_DATA(SCK6_MARK, PJ11MD_101),
-
-	PINMUX_DATA(PJ10_DATA, PJ10MD_000),
-	PINMUX_DATA(DV_DATA10_MARK, PJ10MD_001),
-	PINMUX_DATA(LCD_DATA10_PJ10_MARK, PJ10MD_010),
-	PINMUX_DATA(PINT2_PJ_MARK, PJ10MD_011),
-	PINMUX_DATA(PWM2C_MARK, PJ10MD_100),
-	PINMUX_DATA(SCK5_MARK, PJ10MD_101),
-
-	PINMUX_DATA(PJ9_DATA, PJ9MD_000),
-	PINMUX_DATA(DV_DATA9_MARK, PJ9MD_001),
-	PINMUX_DATA(LCD_DATA9_PJ9_MARK, PJ9MD_010),
-	PINMUX_DATA(PINT1_PJ_MARK, PJ9MD_011),
-	PINMUX_DATA(PWM2B_MARK, PJ9MD_100),
-	PINMUX_DATA(RTS5_MARK, PJ9MD_101),
-
-	PINMUX_DATA(PJ8_DATA, PJ8MD_000),
-	PINMUX_DATA(DV_DATA8_MARK, PJ8MD_001),
-	PINMUX_DATA(LCD_DATA8_PJ8_MARK, PJ8MD_010),
-	PINMUX_DATA(PINT0_PJ_MARK, PJ8MD_011),
-	PINMUX_DATA(PWM2A_MARK, PJ8MD_100),
-	PINMUX_DATA(CTS5_MARK, PJ8MD_101),
-
-	PINMUX_DATA(PJ7_DATA, PJ7MD_000),
-	PINMUX_DATA(DV_DATA7_MARK, PJ7MD_001),
-	PINMUX_DATA(LCD_DATA7_PJ7_MARK, PJ7MD_010),
-	PINMUX_DATA(SD_D2_MARK, PJ7MD_011),
-	PINMUX_DATA(PWM1H_MARK, PJ7MD_100),
-
-	PINMUX_DATA(PJ6_DATA, PJ6MD_000),
-	PINMUX_DATA(DV_DATA6_MARK, PJ6MD_001),
-	PINMUX_DATA(LCD_DATA6_PJ6_MARK, PJ6MD_010),
-	PINMUX_DATA(SD_D3_MARK, PJ6MD_011),
-	PINMUX_DATA(PWM1G_MARK, PJ6MD_100),
-
-	PINMUX_DATA(PJ5_DATA, PJ5MD_000),
-	PINMUX_DATA(DV_DATA5_MARK, PJ5MD_001),
-	PINMUX_DATA(LCD_DATA5_PJ5_MARK, PJ5MD_010),
-	PINMUX_DATA(SD_CMD_MARK, PJ5MD_011),
-	PINMUX_DATA(PWM1F_MARK, PJ5MD_100),
-
-	PINMUX_DATA(PJ4_DATA, PJ4MD_000),
-	PINMUX_DATA(DV_DATA4_MARK, PJ4MD_001),
-	PINMUX_DATA(LCD_DATA4_PJ4_MARK, PJ4MD_010),
-	PINMUX_DATA(SD_CLK_MARK, PJ4MD_011),
-	PINMUX_DATA(PWM1E_MARK, PJ4MD_100),
-
-	PINMUX_DATA(PJ3_DATA, PJ3MD_000),
-	PINMUX_DATA(DV_DATA3_MARK, PJ3MD_001),
-	PINMUX_DATA(LCD_DATA3_PJ3_MARK, PJ3MD_010),
-	PINMUX_DATA(SD_D0_MARK, PJ3MD_011),
-	PINMUX_DATA(PWM1D_MARK, PJ3MD_100),
-
-	PINMUX_DATA(PJ2_DATA, PJ2MD_000),
-	PINMUX_DATA(DV_DATA2_MARK, PJ2MD_001),
-	PINMUX_DATA(LCD_DATA2_PJ2_MARK, PJ2MD_010),
-	PINMUX_DATA(SD_D1_MARK, PJ2MD_011),
-	PINMUX_DATA(PWM1C_MARK, PJ2MD_100),
-
-	PINMUX_DATA(PJ1_DATA, PJ1MD_000),
-	PINMUX_DATA(DV_DATA1_MARK, PJ1MD_001),
-	PINMUX_DATA(LCD_DATA1_PJ1_MARK, PJ1MD_010),
-	PINMUX_DATA(SD_WP_MARK, PJ1MD_011),
-	PINMUX_DATA(PWM1B_MARK, PJ1MD_100),
-
-	PINMUX_DATA(PJ0_DATA, PJ0MD_000),
-	PINMUX_DATA(DV_DATA0_MARK, PJ0MD_001),
-	PINMUX_DATA(LCD_DATA0_PJ0_MARK, PJ0MD_010),
-	PINMUX_DATA(SD_CD_MARK, PJ0MD_011),
-	PINMUX_DATA(PWM1A_MARK, PJ0MD_100),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	/* Port A */
-	PINMUX_GPIO(PA1),
-	PINMUX_GPIO(PA0),
-
-	/* Port B */
-	PINMUX_GPIO(PB22),
-	PINMUX_GPIO(PB21),
-	PINMUX_GPIO(PB20),
-	PINMUX_GPIO(PB19),
-	PINMUX_GPIO(PB18),
-	PINMUX_GPIO(PB17),
-	PINMUX_GPIO(PB16),
-	PINMUX_GPIO(PB15),
-	PINMUX_GPIO(PB14),
-	PINMUX_GPIO(PB13),
-	PINMUX_GPIO(PB12),
-	PINMUX_GPIO(PB11),
-	PINMUX_GPIO(PB10),
-	PINMUX_GPIO(PB9),
-	PINMUX_GPIO(PB8),
-	PINMUX_GPIO(PB7),
-	PINMUX_GPIO(PB6),
-	PINMUX_GPIO(PB5),
-	PINMUX_GPIO(PB4),
-	PINMUX_GPIO(PB3),
-	PINMUX_GPIO(PB2),
-	PINMUX_GPIO(PB1),
-
-	/* Port C */
-	PINMUX_GPIO(PC8),
-	PINMUX_GPIO(PC7),
-	PINMUX_GPIO(PC6),
-	PINMUX_GPIO(PC5),
-	PINMUX_GPIO(PC4),
-	PINMUX_GPIO(PC3),
-	PINMUX_GPIO(PC2),
-	PINMUX_GPIO(PC1),
-	PINMUX_GPIO(PC0),
-
-	/* Port D */
-	PINMUX_GPIO(PD15),
-	PINMUX_GPIO(PD14),
-	PINMUX_GPIO(PD13),
-	PINMUX_GPIO(PD12),
-	PINMUX_GPIO(PD11),
-	PINMUX_GPIO(PD10),
-	PINMUX_GPIO(PD9),
-	PINMUX_GPIO(PD8),
-	PINMUX_GPIO(PD7),
-	PINMUX_GPIO(PD6),
-	PINMUX_GPIO(PD5),
-	PINMUX_GPIO(PD4),
-	PINMUX_GPIO(PD3),
-	PINMUX_GPIO(PD2),
-	PINMUX_GPIO(PD1),
-	PINMUX_GPIO(PD0),
-
-	/* Port E */
-	PINMUX_GPIO(PE7),
-	PINMUX_GPIO(PE6),
-	PINMUX_GPIO(PE5),
-	PINMUX_GPIO(PE4),
-	PINMUX_GPIO(PE3),
-	PINMUX_GPIO(PE2),
-	PINMUX_GPIO(PE1),
-	PINMUX_GPIO(PE0),
-
-	/* Port F */
-	PINMUX_GPIO(PF23),
-	PINMUX_GPIO(PF22),
-	PINMUX_GPIO(PF21),
-	PINMUX_GPIO(PF20),
-	PINMUX_GPIO(PF19),
-	PINMUX_GPIO(PF18),
-	PINMUX_GPIO(PF17),
-	PINMUX_GPIO(PF16),
-	PINMUX_GPIO(PF15),
-	PINMUX_GPIO(PF14),
-	PINMUX_GPIO(PF13),
-	PINMUX_GPIO(PF12),
-	PINMUX_GPIO(PF11),
-	PINMUX_GPIO(PF10),
-	PINMUX_GPIO(PF9),
-	PINMUX_GPIO(PF8),
-	PINMUX_GPIO(PF7),
-	PINMUX_GPIO(PF6),
-	PINMUX_GPIO(PF5),
-	PINMUX_GPIO(PF4),
-	PINMUX_GPIO(PF3),
-	PINMUX_GPIO(PF2),
-	PINMUX_GPIO(PF1),
-	PINMUX_GPIO(PF0),
-
-	/* Port G */
-	PINMUX_GPIO(PG27),
-	PINMUX_GPIO(PG26),
-	PINMUX_GPIO(PG25),
-	PINMUX_GPIO(PG24),
-	PINMUX_GPIO(PG23),
-	PINMUX_GPIO(PG22),
-	PINMUX_GPIO(PG21),
-	PINMUX_GPIO(PG20),
-	PINMUX_GPIO(PG19),
-	PINMUX_GPIO(PG18),
-	PINMUX_GPIO(PG17),
-	PINMUX_GPIO(PG16),
-	PINMUX_GPIO(PG15),
-	PINMUX_GPIO(PG14),
-	PINMUX_GPIO(PG13),
-	PINMUX_GPIO(PG12),
-	PINMUX_GPIO(PG11),
-	PINMUX_GPIO(PG10),
-	PINMUX_GPIO(PG9),
-	PINMUX_GPIO(PG8),
-	PINMUX_GPIO(PG7),
-	PINMUX_GPIO(PG6),
-	PINMUX_GPIO(PG5),
-	PINMUX_GPIO(PG4),
-	PINMUX_GPIO(PG3),
-	PINMUX_GPIO(PG2),
-	PINMUX_GPIO(PG1),
-	PINMUX_GPIO(PG0),
-
-	/* Port H - Port H does not have a Data Register */
-
-	/* Port I - not on device */
-
-	/* Port J */
-	PINMUX_GPIO(PJ31),
-	PINMUX_GPIO(PJ30),
-	PINMUX_GPIO(PJ29),
-	PINMUX_GPIO(PJ28),
-	PINMUX_GPIO(PJ27),
-	PINMUX_GPIO(PJ26),
-	PINMUX_GPIO(PJ25),
-	PINMUX_GPIO(PJ24),
-	PINMUX_GPIO(PJ23),
-	PINMUX_GPIO(PJ22),
-	PINMUX_GPIO(PJ21),
-	PINMUX_GPIO(PJ20),
-	PINMUX_GPIO(PJ19),
-	PINMUX_GPIO(PJ18),
-	PINMUX_GPIO(PJ17),
-	PINMUX_GPIO(PJ16),
-	PINMUX_GPIO(PJ15),
-	PINMUX_GPIO(PJ14),
-	PINMUX_GPIO(PJ13),
-	PINMUX_GPIO(PJ12),
-	PINMUX_GPIO(PJ11),
-	PINMUX_GPIO(PJ10),
-	PINMUX_GPIO(PJ9),
-	PINMUX_GPIO(PJ8),
-	PINMUX_GPIO(PJ7),
-	PINMUX_GPIO(PJ6),
-	PINMUX_GPIO(PJ5),
-	PINMUX_GPIO(PJ4),
-	PINMUX_GPIO(PJ3),
-	PINMUX_GPIO(PJ2),
-	PINMUX_GPIO(PJ1),
-	PINMUX_GPIO(PJ0),
-};
-
-#define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-	/* INTC */
-	GPIO_FN(IRQ7_PG),
-	GPIO_FN(IRQ6_PG),
-	GPIO_FN(IRQ5_PG),
-	GPIO_FN(IRQ4_PG),
-	GPIO_FN(IRQ3_PG),
-	GPIO_FN(IRQ2_PG),
-	GPIO_FN(IRQ1_PG),
-	GPIO_FN(IRQ0_PG),
-	GPIO_FN(IRQ7_PF),
-	GPIO_FN(IRQ6_PF),
-	GPIO_FN(IRQ5_PF),
-	GPIO_FN(IRQ4_PF),
-	GPIO_FN(IRQ3_PJ),
-	GPIO_FN(IRQ2_PJ),
-	GPIO_FN(IRQ1_PJ),
-	GPIO_FN(IRQ0_PJ),
-	GPIO_FN(IRQ1_PC),
-	GPIO_FN(IRQ0_PC),
-
-	GPIO_FN(PINT7_PG),
-	GPIO_FN(PINT6_PG),
-	GPIO_FN(PINT5_PG),
-	GPIO_FN(PINT4_PG),
-	GPIO_FN(PINT3_PG),
-	GPIO_FN(PINT2_PG),
-	GPIO_FN(PINT1_PG),
-	GPIO_FN(PINT0_PG),
-	GPIO_FN(PINT7_PH),
-	GPIO_FN(PINT6_PH),
-	GPIO_FN(PINT5_PH),
-	GPIO_FN(PINT4_PH),
-	GPIO_FN(PINT3_PH),
-	GPIO_FN(PINT2_PH),
-	GPIO_FN(PINT1_PH),
-	GPIO_FN(PINT0_PH),
-	GPIO_FN(PINT7_PJ),
-	GPIO_FN(PINT6_PJ),
-	GPIO_FN(PINT5_PJ),
-	GPIO_FN(PINT4_PJ),
-	GPIO_FN(PINT3_PJ),
-	GPIO_FN(PINT2_PJ),
-	GPIO_FN(PINT1_PJ),
-	GPIO_FN(PINT0_PJ),
-
-	/* WDT */
-	GPIO_FN(WDTOVF),
-
-	/* CAN */
-	GPIO_FN(CTX2),
-	GPIO_FN(CRX2),
-	GPIO_FN(CTX1),
-	GPIO_FN(CRX1),
-	GPIO_FN(CTX0),
-	GPIO_FN(CRX0),
-	GPIO_FN(CTX0_CTX1),
-	GPIO_FN(CRX0_CRX1),
-	GPIO_FN(CTX0_CTX1_CTX2),
-	GPIO_FN(CRX0_CRX1_CRX2),
-	GPIO_FN(CTX2_PJ21),
-	GPIO_FN(CRX2_PJ20),
-	GPIO_FN(CTX1_PJ23),
-	GPIO_FN(CRX1_PJ22),
-	GPIO_FN(CTX0_CTX1_PJ23),
-	GPIO_FN(CRX0_CRX1_PJ22),
-	GPIO_FN(CTX0_CTX1_CTX2_PJ21),
-	GPIO_FN(CRX0_CRX1_CRX2_PJ20),
-
-	/* DMAC */
-	GPIO_FN(TEND0),
-	GPIO_FN(DACK0),
-	GPIO_FN(DREQ0),
-	GPIO_FN(TEND1),
-	GPIO_FN(DACK1),
-	GPIO_FN(DREQ1),
-
-	/* ADC */
-	GPIO_FN(ADTRG),
-
-	/* BSCh */
-	GPIO_FN(A25),
-	GPIO_FN(A24),
-	GPIO_FN(A23),
-	GPIO_FN(A22),
-	GPIO_FN(A21),
-	GPIO_FN(A20),
-	GPIO_FN(A19),
-	GPIO_FN(A18),
-	GPIO_FN(A17),
-	GPIO_FN(A16),
-	GPIO_FN(A15),
-	GPIO_FN(A14),
-	GPIO_FN(A13),
-	GPIO_FN(A12),
-	GPIO_FN(A11),
-	GPIO_FN(A10),
-	GPIO_FN(A9),
-	GPIO_FN(A8),
-	GPIO_FN(A7),
-	GPIO_FN(A6),
-	GPIO_FN(A5),
-	GPIO_FN(A4),
-	GPIO_FN(A3),
-	GPIO_FN(A2),
-	GPIO_FN(A1),
-	GPIO_FN(A0),
-
-	GPIO_FN(D15),
-	GPIO_FN(D14),
-	GPIO_FN(D13),
-	GPIO_FN(D12),
-	GPIO_FN(D11),
-	GPIO_FN(D10),
-	GPIO_FN(D9),
-	GPIO_FN(D8),
-	GPIO_FN(D7),
-	GPIO_FN(D6),
-	GPIO_FN(D5),
-	GPIO_FN(D4),
-	GPIO_FN(D3),
-	GPIO_FN(D2),
-	GPIO_FN(D1),
-	GPIO_FN(D0),
-
-	GPIO_FN(BS),
-	GPIO_FN(CS4),
-	GPIO_FN(CS3),
-	GPIO_FN(CS2),
-	GPIO_FN(CS1),
-	GPIO_FN(CS0),
-	GPIO_FN(CS5CE1A),
-	GPIO_FN(CE2A),
-	GPIO_FN(CE2B),
-	GPIO_FN(RD),
-	GPIO_FN(RDWR),
-	GPIO_FN(WE3ICIOWRAHDQMUU),
-	GPIO_FN(WE2ICIORDDQMUL),
-	GPIO_FN(WE1DQMUWE),
-	GPIO_FN(WE0DQML),
-	GPIO_FN(RAS),
-	GPIO_FN(CAS),
-	GPIO_FN(CKE),
-	GPIO_FN(WAIT),
-	GPIO_FN(BREQ),
-	GPIO_FN(BACK),
-	GPIO_FN(IOIS16),
-
-	/* TMU */
-	GPIO_FN(TIOC4D),
-	GPIO_FN(TIOC4C),
-	GPIO_FN(TIOC4B),
-	GPIO_FN(TIOC4A),
-	GPIO_FN(TIOC3D),
-	GPIO_FN(TIOC3C),
-	GPIO_FN(TIOC3B),
-	GPIO_FN(TIOC3A),
-	GPIO_FN(TIOC2B),
-	GPIO_FN(TIOC1B),
-	GPIO_FN(TIOC2A),
-	GPIO_FN(TIOC1A),
-	GPIO_FN(TIOC0D),
-	GPIO_FN(TIOC0C),
-	GPIO_FN(TIOC0B),
-	GPIO_FN(TIOC0A),
-	GPIO_FN(TCLKD),
-	GPIO_FN(TCLKC),
-	GPIO_FN(TCLKB),
-	GPIO_FN(TCLKA),
-
-	/* SCIF */
-	GPIO_FN(SCK0),
-	GPIO_FN(TXD0),
-	GPIO_FN(RXD0),
-	GPIO_FN(SCK1),
-	GPIO_FN(TXD1),
-	GPIO_FN(RXD1),
-	GPIO_FN(RTS1),
-	GPIO_FN(CTS1),
-	GPIO_FN(SCK2),
-	GPIO_FN(TXD2),
-	GPIO_FN(RXD2),
-	GPIO_FN(SCK3),
-	GPIO_FN(TXD3),
-	GPIO_FN(RXD3),
-	GPIO_FN(SCK4),
-	GPIO_FN(TXD4),
-	GPIO_FN(RXD4),
-	GPIO_FN(SCK5),
-	GPIO_FN(TXD5),
-	GPIO_FN(RXD5),
-	GPIO_FN(RTS5),
-	GPIO_FN(CTS5),
-	GPIO_FN(SCK6),
-	GPIO_FN(TXD6),
-	GPIO_FN(RXD6),
-	GPIO_FN(SCK7),
-	GPIO_FN(TXD7),
-	GPIO_FN(RXD7),
-	GPIO_FN(RTS7),
-	GPIO_FN(CTS7),
-
-	/* RSPI */
-	GPIO_FN(RSPCK0_PJ16),
-	GPIO_FN(SSL00_PJ17),
-	GPIO_FN(MOSI0_PJ18),
-	GPIO_FN(MISO0_PJ19),
-	GPIO_FN(RSPCK0_PB17),
-	GPIO_FN(SSL00_PB18),
-	GPIO_FN(MOSI0_PB19),
-	GPIO_FN(MISO0_PB20),
-	GPIO_FN(RSPCK1),
-	GPIO_FN(MOSI1),
-	GPIO_FN(MISO1),
-	GPIO_FN(SSL10),
-
-	/* IIC3 */
-	GPIO_FN(SCL0),
-	GPIO_FN(SCL1),
-	GPIO_FN(SCL2),
-	GPIO_FN(SDA0),
-	GPIO_FN(SDA1),
-	GPIO_FN(SDA2),
-
-	/* SSI */
-	GPIO_FN(SSISCK0),
-	GPIO_FN(SSIWS0),
-	GPIO_FN(SSITXD0),
-	GPIO_FN(SSIRXD0),
-	GPIO_FN(SSIWS1),
-	GPIO_FN(SSIWS2),
-	GPIO_FN(SSIWS3),
-	GPIO_FN(SSISCK1),
-	GPIO_FN(SSISCK2),
-	GPIO_FN(SSISCK3),
-	GPIO_FN(SSIDATA1),
-	GPIO_FN(SSIDATA2),
-	GPIO_FN(SSIDATA3),
-	GPIO_FN(AUDIO_CLK),
-	GPIO_FN(AUDIO_XOUT),
-
-	/* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
-	GPIO_FN(SIOFTXD),
-	GPIO_FN(SIOFRXD),
-	GPIO_FN(SIOFSYNC),
-	GPIO_FN(SIOFSCK),
-
-	/* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
-	GPIO_FN(SPDIF_IN),
-	GPIO_FN(SPDIF_OUT),
-
-	/* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
-	GPIO_FN(FCE),
-	GPIO_FN(FRB),
-
-	/* VDC3 */
-	GPIO_FN(DV_CLK),
-	GPIO_FN(DV_VSYNC),
-	GPIO_FN(DV_HSYNC),
-
-	GPIO_FN(DV_DATA23),
-	GPIO_FN(DV_DATA22),
-	GPIO_FN(DV_DATA21),
-	GPIO_FN(DV_DATA20),
-	GPIO_FN(DV_DATA19),
-	GPIO_FN(DV_DATA18),
-	GPIO_FN(DV_DATA17),
-	GPIO_FN(DV_DATA16),
-	GPIO_FN(DV_DATA15),
-	GPIO_FN(DV_DATA14),
-	GPIO_FN(DV_DATA13),
-	GPIO_FN(DV_DATA12),
-	GPIO_FN(DV_DATA11),
-	GPIO_FN(DV_DATA10),
-	GPIO_FN(DV_DATA9),
-	GPIO_FN(DV_DATA8),
-	GPIO_FN(DV_DATA7),
-	GPIO_FN(DV_DATA6),
-	GPIO_FN(DV_DATA5),
-	GPIO_FN(DV_DATA4),
-	GPIO_FN(DV_DATA3),
-	GPIO_FN(DV_DATA2),
-	GPIO_FN(DV_DATA1),
-	GPIO_FN(DV_DATA0),
-
-	GPIO_FN(LCD_CLK),
-	GPIO_FN(LCD_EXTCLK),
-	GPIO_FN(LCD_VSYNC),
-	GPIO_FN(LCD_HSYNC),
-	GPIO_FN(LCD_DE),
-
-	GPIO_FN(LCD_DATA23_PG23),
-	GPIO_FN(LCD_DATA22_PG22),
-	GPIO_FN(LCD_DATA21_PG21),
-	GPIO_FN(LCD_DATA20_PG20),
-	GPIO_FN(LCD_DATA19_PG19),
-	GPIO_FN(LCD_DATA18_PG18),
-	GPIO_FN(LCD_DATA17_PG17),
-	GPIO_FN(LCD_DATA16_PG16),
-	GPIO_FN(LCD_DATA15_PG15),
-	GPIO_FN(LCD_DATA14_PG14),
-	GPIO_FN(LCD_DATA13_PG13),
-	GPIO_FN(LCD_DATA12_PG12),
-	GPIO_FN(LCD_DATA11_PG11),
-	GPIO_FN(LCD_DATA10_PG10),
-	GPIO_FN(LCD_DATA9_PG9),
-	GPIO_FN(LCD_DATA8_PG8),
-	GPIO_FN(LCD_DATA7_PG7),
-	GPIO_FN(LCD_DATA6_PG6),
-	GPIO_FN(LCD_DATA5_PG5),
-	GPIO_FN(LCD_DATA4_PG4),
-	GPIO_FN(LCD_DATA3_PG3),
-	GPIO_FN(LCD_DATA2_PG2),
-	GPIO_FN(LCD_DATA1_PG1),
-	GPIO_FN(LCD_DATA0_PG0),
-
-	GPIO_FN(LCD_DATA23_PJ23),
-	GPIO_FN(LCD_DATA22_PJ22),
-	GPIO_FN(LCD_DATA21_PJ21),
-	GPIO_FN(LCD_DATA20_PJ20),
-	GPIO_FN(LCD_DATA19_PJ19),
-	GPIO_FN(LCD_DATA18_PJ18),
-	GPIO_FN(LCD_DATA17_PJ17),
-	GPIO_FN(LCD_DATA16_PJ16),
-	GPIO_FN(LCD_DATA15_PJ15),
-	GPIO_FN(LCD_DATA14_PJ14),
-	GPIO_FN(LCD_DATA13_PJ13),
-	GPIO_FN(LCD_DATA12_PJ12),
-	GPIO_FN(LCD_DATA11_PJ11),
-	GPIO_FN(LCD_DATA10_PJ10),
-	GPIO_FN(LCD_DATA9_PJ9),
-	GPIO_FN(LCD_DATA8_PJ8),
-	GPIO_FN(LCD_DATA7_PJ7),
-	GPIO_FN(LCD_DATA6_PJ6),
-	GPIO_FN(LCD_DATA5_PJ5),
-	GPIO_FN(LCD_DATA4_PJ4),
-	GPIO_FN(LCD_DATA3_PJ3),
-	GPIO_FN(LCD_DATA2_PJ2),
-	GPIO_FN(LCD_DATA1_PJ1),
-	GPIO_FN(LCD_DATA0_PJ0),
-
-	GPIO_FN(LCD_M_DISP),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	/* "name" addr register_size Field_Width */
-
-	/* where Field_Width is 1 for single mode registers or 4 for upto 16
-	   mode registers and modes are described in assending order [0..16] */
-
-	{ PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, PA1_IN, PA1_OUT,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, PA0_IN, PA0_OUT ))
-	},
-	{ PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB22MD_000, PB22MD_001, PB22MD_010, PB22MD_011,
-		PB22MD_100, PB22MD_101, PB22MD_110, PB22MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB21MD_00, PB21MD_01, PB21MD_10, PB21MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB20MD_000, PB20MD_001, PB20MD_010, PB20MD_011,
-		PB20MD_100, PB20MD_101, PB20MD_110, PB20MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PBCR4", 0xfffe3826, 16, 4, GROUP(
-		PB19MD_000, PB19MD_001, PB19MD_010, PB19MD_011,
-		PB19MD_100, PB19MD_101, PB19MD_110, PB19MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB18MD_000, PB18MD_001, PB18MD_010, PB18MD_011,
-		PB18MD_100, PB18MD_101, PB18MD_110, PB18MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB17MD_000, PB17MD_001, PB17MD_010, PB17MD_011,
-		PB17MD_100, PB17MD_101, PB17MD_110, PB17MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB16MD_000, PB16MD_001, PB16MD_010, PB16MD_011,
-		PB16MD_100, PB16MD_101, PB16MD_110, PB16MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PBCR3", 0xfffe3828, 16, 4, GROUP(
-		PB15MD_000, PB15MD_001, PB15MD_010, PB15MD_011,
-		PB15MD_100, PB15MD_101, PB15MD_110, PB15MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB14MD_000, PB14MD_001, PB14MD_010, PB14MD_011,
-		PB14MD_100, PB14MD_101, PB14MD_110, PB14MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB13MD_000, PB13MD_001, PB13MD_010, PB13MD_011,
-		PB13MD_100, PB13MD_101, PB13MD_110, PB13MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PBCR2", 0xfffe382a, 16, 4, GROUP(
-		PB11MD_00, PB11MD_01, PB11MD_10, PB11MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB10MD_00, PB10MD_01, PB10MD_10, PB10MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB9MD_00, PB9MD_01, PB9MD_10, PB9MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB8MD_00, PB8MD_01, PB8MD_10, PB8MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PBCR1", 0xfffe382c, 16, 4, GROUP(
-		PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4, GROUP(
-		PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB2MD_00, PB2MD_01, PB2MD_10, PB2MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PB1MD_00, PB1MD_01, PB1MD_10, PB1MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0,
-		PB22_IN, PB22_OUT,
-		PB21_IN, PB21_OUT,
-		PB20_IN, PB20_OUT,
-		PB19_IN, PB19_OUT,
-		PB18_IN, PB18_OUT,
-		PB17_IN, PB17_OUT,
-		PB16_IN, PB16_OUT ))
-	},
-	{ PINMUX_CFG_REG("PBIOR0", 0xfffe3832, 16, 1, GROUP(
-		PB15_IN, PB15_OUT,
-		PB14_IN, PB14_OUT,
-		PB13_IN, PB13_OUT,
-		PB12_IN, PB12_OUT,
-		PB11_IN, PB11_OUT,
-		PB10_IN, PB10_OUT,
-		PB9_IN, PB9_OUT,
-		PB8_IN, PB8_OUT,
-		PB7_IN, PB7_OUT,
-		PB6_IN, PB6_OUT,
-		PB5_IN, PB5_OUT,
-		PB4_IN, PB4_OUT,
-		PB3_IN, PB3_OUT,
-		PB2_IN, PB2_OUT,
-		PB1_IN, PB1_OUT,
-		0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PC8MD_000, PC8MD_001, PC8MD_010, PC8MD_011,
-		PC8MD_100, PC8MD_101, PC8MD_110, PC8MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PCCR1", 0xfffe384c, 16, 4, GROUP(
-		PC7MD_000, PC7MD_001, PC7MD_010, PC7MD_011,
-		PC7MD_100, PC7MD_101, PC7MD_110, PC7MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PC6MD_000, PC6MD_001, PC6MD_010, PC6MD_011,
-		PC6MD_100, PC6MD_101, PC6MD_110, PC6MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PC5MD_000, PC5MD_001, PC5MD_010, PC5MD_011,
-		PC5MD_100, PC5MD_101, PC5MD_110, PC5MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PC4MD_00, PC4MD_01, PC4MD_10, PC4MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PCCR0", 0xfffe384e, 16, 4, GROUP(
-		PC3MD_00, PC3MD_01, PC3MD_10, PC3MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PC2MD_00, PC2MD_01, PC2MD_10, PC2MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PC1MD_0, PC1MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PC0MD_0, PC0MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PCIOR0", 0xfffe3852, 16, 1, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		PC8_IN, PC8_OUT,
-		PC7_IN, PC7_OUT,
-		PC6_IN, PC6_OUT,
-		PC5_IN, PC5_OUT,
-		PC4_IN, PC4_OUT,
-		PC3_IN, PC3_OUT,
-		PC2_IN, PC2_OUT,
-		PC1_IN, PC1_OUT,
-		PC0_IN, PC0_OUT ))
-	},
-
-	{ PINMUX_CFG_REG("PDCR3", 0xfffe3868, 16, 4, GROUP(
-		PD15MD_00, PD15MD_01, PD15MD_10, PD15MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD14MD_00, PD14MD_01, PD14MD_10, PD14MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD13MD_00, PD13MD_01, PD13MD_10, PD13MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD12MD_00, PD12MD_01, PD12MD_10, PD12MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PDCR2", 0xfffe386a, 16, 4, GROUP(
-		PD11MD_00, PD11MD_01, PD11MD_10, PD11MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD10MD_00, PD10MD_01, PD10MD_10, PD10MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD9MD_00, PD9MD_01, PD9MD_10, PD9MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD8MD_00, PD8MD_01, PD8MD_10, PD8MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PDCR1", 0xfffe386c, 16, 4, GROUP(
-		PD7MD_00, PD7MD_01, PD7MD_10, PD7MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD6MD_00, PD6MD_01, PD6MD_10, PD6MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD5MD_00, PD5MD_01, PD5MD_10, PD5MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD4MD_00, PD4MD_01, PD4MD_10, PD4MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PDCR0", 0xfffe386e, 16, 4, GROUP(
-		PD3MD_00, PD3MD_01, PD3MD_10, PD3MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD2MD_00, PD2MD_01, PD2MD_10, PD2MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD1MD_00, PD1MD_01, PD1MD_10, PD1MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PD0MD_00, PD0MD_01, PD0MD_10, PD0MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PDIOR0", 0xfffe3872, 16, 1, GROUP(
-		PD15_IN, PD15_OUT,
-		PD14_IN, PD14_OUT,
-		PD13_IN, PD13_OUT,
-		PD12_IN, PD12_OUT,
-		PD11_IN, PD11_OUT,
-		PD10_IN, PD10_OUT,
-		PD9_IN, PD9_OUT,
-		PD8_IN, PD8_OUT,
-		PD7_IN, PD7_OUT,
-		PD6_IN, PD6_OUT,
-		PD5_IN, PD5_OUT,
-		PD4_IN, PD4_OUT,
-		PD3_IN, PD3_OUT,
-		PD2_IN, PD2_OUT,
-		PD1_IN, PD1_OUT,
-		PD0_IN, PD0_OUT ))
-	},
-
-	{ PINMUX_CFG_REG("PECR1", 0xfffe388c, 16, 4, GROUP(
-		PE7MD_00, PE7MD_01, PE7MD_10, PE7MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PE6MD_00, PE6MD_01, PE6MD_10, PE6MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PE5MD_00, PE5MD_01, PE5MD_10, PE5MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PE4MD_00, PE4MD_01, PE4MD_10, PE4MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PECR0", 0xfffe388e, 16, 4, GROUP(
-		PE3MD_000, PE3MD_001, PE3MD_010, PE3MD_011,
-		PE3MD_100, PE3MD_101, PE3MD_110, PE3MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PE2MD_000, PE2MD_001, PE2MD_010, PE2MD_011,
-		PE2MD_100, PE2MD_101, PE2MD_110, PE2MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PE1MD_000, PE1MD_001, PE1MD_010, PE1MD_011,
-		PE1MD_100, PE1MD_101, PE1MD_110, PE1MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PEIOR0", 0xfffe3892, 16, 1, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PE7_IN, PE7_OUT,
-		PE6_IN, PE6_OUT,
-		PE5_IN, PE5_OUT,
-		PE4_IN, PE4_OUT,
-		PE3_IN, PE3_OUT,
-		PE2_IN, PE2_OUT,
-		PE1_IN, PE1_OUT,
-		PE0_IN, PE0_OUT ))
-	},
-
-	{ PINMUX_CFG_REG("PFCR6", 0xfffe38a2, 16, 4, GROUP(
-		PF23MD_000, PF23MD_001, PF23MD_010, PF23MD_011,
-		PF23MD_100, PF23MD_101, PF23MD_110, PF23MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF22MD_000, PF22MD_001, PF22MD_010, PF22MD_011,
-		PF22MD_100, PF22MD_101, PF22MD_110, PF22MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF21MD_000, PF21MD_001, PF21MD_010, PF21MD_011,
-		PF21MD_100, PF21MD_101, PF21MD_110, PF21MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF20MD_000, PF20MD_001, PF20MD_010, PF20MD_011,
-		PF20MD_100, PF20MD_101, PF20MD_110, PF20MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PFCR5", 0xfffe38a4, 16, 4, GROUP(
-		PF19MD_000, PF19MD_001, PF19MD_010, PF19MD_011,
-		PF19MD_100, PF19MD_101, PF19MD_110, PF19MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF18MD_000, PF18MD_001, PF18MD_010, PF18MD_011,
-		PF18MD_100, PF18MD_101, PF18MD_110, PF18MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF17MD_000, PF17MD_001, PF17MD_010, PF17MD_011,
-		PF17MD_100, PF17MD_101, PF17MD_110, PF17MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF16MD_000, PF16MD_001, PF16MD_010, PF16MD_011,
-		PF16MD_100, PF16MD_101, PF16MD_110, PF16MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PFCR4", 0xfffe38a6, 16, 4, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF15MD_000, PF15MD_001, PF15MD_010, PF15MD_011,
-		PF15MD_100, PF15MD_101, PF15MD_110, PF15MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF14MD_000, PF14MD_001, PF14MD_010, PF14MD_011,
-		PF14MD_100, PF14MD_101, PF14MD_110, PF14MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF13MD_000, PF13MD_001, PF13MD_010, PF13MD_011,
-		PF13MD_100, PF13MD_101, PF13MD_110, PF13MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF12MD_000, PF12MD_001, PF12MD_010, PF12MD_011,
-		PF12MD_100, PF12MD_101, PF12MD_110, PF12MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PFCR2", 0xfffe38aa, 16, 4, GROUP(
-		PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011,
-		PF11MD_100, PF11MD_101, PF11MD_110, PF11MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF10MD_000, PF10MD_001, PF10MD_010, PF10MD_011,
-		PF10MD_100, PF10MD_101, PF10MD_110, PF10MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF9MD_000, PF9MD_001, PF9MD_010, PF9MD_011,
-		PF9MD_100, PF9MD_101, PF9MD_110, PF9MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF8MD_000, PF8MD_001, PF8MD_010, PF8MD_011,
-		PF8MD_100, PF8MD_101, PF8MD_110, PF8MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PFCR1", 0xfffe38ac, 16, 4, GROUP(
-		PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011,
-		PF7MD_100, PF7MD_101, PF7MD_110, PF7MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF6MD_000, PF6MD_001, PF6MD_010, PF6MD_011,
-		PF6MD_100, PF6MD_101, PF6MD_110, PF6MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF5MD_000, PF5MD_001, PF5MD_010, PF5MD_011,
-		PF5MD_100, PF5MD_101, PF5MD_110, PF5MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011,
-		PF4MD_100, PF4MD_101, PF4MD_110, PF4MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PFCR0", 0xfffe38ae, 16, 4, GROUP(
-		PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011,
-		PF3MD_100, PF3MD_101, PF3MD_110, PF3MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF2MD_000, PF2MD_001, PF2MD_010, PF2MD_011,
-		PF2MD_100, PF2MD_101, PF2MD_110, PF2MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF1MD_000, PF1MD_001, PF1MD_010, PF1MD_011,
-		PF1MD_100, PF1MD_101, PF1MD_110, PF1MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PF0MD_000, PF0MD_001, PF0MD_010, PF0MD_011,
-		PF0MD_100, PF0MD_101, PF0MD_110, PF0MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PFIOR1", 0xfffe38b0, 16, 1, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PF23_IN, PF23_OUT,
-		PF22_IN, PF22_OUT,
-		PF21_IN, PF21_OUT,
-		PF20_IN, PF20_OUT,
-		PF19_IN, PF19_OUT,
-		PF18_IN, PF18_OUT,
-		PF17_IN, PF17_OUT,
-		PF16_IN, PF16_OUT ))
-	},
-	{ PINMUX_CFG_REG("PFIOR0", 0xfffe38b2, 16, 1, GROUP(
-		PF15_IN, PF15_OUT,
-		PF14_IN, PF14_OUT,
-		PF13_IN, PF13_OUT,
-		PF12_IN, PF12_OUT,
-		PF11_IN, PF11_OUT,
-		PF10_IN, PF10_OUT,
-		PF9_IN, PF9_OUT,
-		PF8_IN, PF8_OUT,
-		PF7_IN, PF7_OUT,
-		PF6_IN, PF6_OUT,
-		PF5_IN, PF5_OUT,
-		PF4_IN, PF4_OUT,
-		PF3_IN, PF3_OUT,
-		PF2_IN, PF2_OUT,
-		PF1_IN, PF1_OUT,
-		PF0_IN, PF0_OUT ))
-	},
-
-	{ PINMUX_CFG_REG("PGCR6", 0xfffe38c2, 16, 4, GROUP(
-		PG27MD_00, PG27MD_01, PG27MD_10, PG27MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PG26MD_00, PG26MD_01, PG26MD_10, PG26MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PG25MD_00, PG25MD_01, PG25MD_10, PG25MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PGCR5", 0xfffe38c4, 16, 4, GROUP(
-		PG23MD_000, PG23MD_001, PG23MD_010, PG23MD_011,
-		PG23MD_100, PG23MD_101, PG23MD_110, PG23MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PG22MD_000, PG22MD_001, PG22MD_010, PG22MD_011,
-		PG22MD_100, PG22MD_101, PG22MD_110, PG22MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PG21MD_000, PG21MD_001, PG21MD_010, PG21MD_011,
-		PG21MD_100, PG21MD_101, PG21MD_110, PG21MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011,
-		PG20MD_100, PG20MD_101, PG20MD_110, PG20MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PGCR4", 0xfffe38c6, 16, 4, GROUP(
-		PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011,
-		PG19MD_100, PG19MD_101, PG19MD_110, PG19MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PG18MD_000, PG18MD_001, PG18MD_010, PG18MD_011,
-		PG18MD_100, PG18MD_101, PG18MD_110, PG18MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PG17MD_00, PG17MD_01, PG17MD_10, PG17MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PG16MD_00, PG16MD_01, PG16MD_10, PG16MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PGCR3", 0xfffe38c8, 16, 4, GROUP(
-		PG15MD_00, PG15MD_01, PG15MD_10, PG15MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PG14MD_00, PG14MD_01, PG14MD_10, PG14MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PG13MD_00, PG13MD_01, PG13MD_10, PG13MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PG12MD_00, PG12MD_01, PG12MD_10, PG12MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PGCR2", 0xfffe38ca, 16, 4, GROUP(
-		PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011,
-		PG11MD_100, PG11MD_101, PG11MD_110, PG11MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PG10MD_000, PG10MD_001, PG10MD_010, PG10MD_011,
-		PG10MD_100, PG10MD_101, PG10MD_110, PG10MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PG9MD_000, PG9MD_001, PG9MD_010, PG9MD_011,
-		PG9MD_100, PG9MD_101, PG9MD_110, PG9MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011,
-		PG8MD_100, PG8MD_101, PG8MD_110, PG8MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PGCR1", 0xfffe38cc, 16, 4, GROUP(
-		PG7MD_000, PG7MD_001, PG7MD_010, PG7MD_011,
-		PG7MD_100, PG7MD_101, PG7MD_110, PG7MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PG6MD_000, PG6MD_001, PG6MD_010, PG6MD_011,
-		PG6MD_100, PG6MD_101, PG6MD_110, PG6MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PG5MD_000, PG5MD_001, PG5MD_010, PG5MD_011,
-		PG5MD_100, PG5MD_101, PG5MD_110, PG5MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PG4MD_000, PG4MD_001, PG4MD_010, PG4MD_011,
-		PG4MD_100, PG4MD_101, PG4MD_110, PG4MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PGCR0", 0xfffe38ce, 16, 4, GROUP(
-		PG3MD_000, PG3MD_001, PG3MD_010, PG3MD_011,
-		PG3MD_100, PG3MD_101, PG3MD_110, PG3MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PG2MD_000, PG2MD_001, PG2MD_010, PG2MD_011,
-		PG2MD_100, PG2MD_101, PG2MD_110, PG2MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PG1MD_000, PG1MD_001, PG1MD_010, PG1MD_011,
-		PG1MD_100, PG1MD_101, PG1MD_110, PG1MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011,
-		PG0MD_100, PG0MD_101, PG0MD_110, PG0MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PGIOR1", 0xfffe38d0, 16, 1, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PG27_IN, PG27_OUT,
-		PG26_IN, PG26_OUT,
-		PG25_IN, PG25_OUT,
-		PG24_IN, PG24_OUT,
-		PG23_IN, PG23_OUT,
-		PG22_IN, PG22_OUT,
-		PG21_IN, PG21_OUT,
-		PG20_IN, PG20_OUT,
-		PG19_IN, PG19_OUT,
-		PG18_IN, PG18_OUT,
-		PG17_IN, PG17_OUT,
-		PG16_IN, PG16_OUT ))
-	},
-	{ PINMUX_CFG_REG("PGIOR0", 0xfffe38d2, 16, 1, GROUP(
-		PG15_IN, PG15_OUT,
-		PG14_IN, PG14_OUT,
-		PG13_IN, PG13_OUT,
-		PG12_IN, PG12_OUT,
-		PG11_IN, PG11_OUT,
-		PG10_IN, PG10_OUT,
-		PG9_IN, PG9_OUT,
-		PG8_IN, PG8_OUT,
-		PG7_IN, PG7_OUT,
-		PG6_IN, PG6_OUT,
-		PG5_IN, PG5_OUT,
-		PG4_IN, PG4_OUT,
-		PG3_IN, PG3_OUT,
-		PG2_IN, PG2_OUT,
-		PG1_IN, PG1_OUT,
-		PG0_IN, PG0_OUT ))
-	},
-
-	{ PINMUX_CFG_REG("PHCR1", 0xfffe38ec, 16, 4, GROUP(
-		PH7MD_00, PH7MD_01, PH7MD_10, PH7MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PH6MD_00, PH6MD_01, PH6MD_10, PH6MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PH5MD_00, PH5MD_01, PH5MD_10, PH5MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PH4MD_00, PH4MD_01, PH4MD_10, PH4MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PHCR0", 0xfffe38ee, 16, 4, GROUP(
-		PH3MD_00, PH3MD_01, PH3MD_10, PH3MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PH2MD_00, PH2MD_01, PH2MD_10, PH2MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PH1MD_00, PH1MD_01, PH1MD_10, PH1MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PH0MD_00, PH0MD_01, PH0MD_10, PH0MD_11, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PJCR7", 0xfffe3900, 16, 4, GROUP(
-		PJ31MD_0, PJ31MD_1, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ30MD_000, PJ30MD_001, PJ30MD_010, PJ30MD_011,
-		PJ30MD_100, PJ30MD_101, PJ30MD_110, PJ30MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ29MD_000, PJ29MD_001, PJ29MD_010, PJ29MD_011,
-		PJ29MD_100, PJ29MD_101, PJ29MD_110, PJ29MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ28MD_000, PJ28MD_001, PJ28MD_010, PJ28MD_011,
-		PJ28MD_100, PJ28MD_101, PJ28MD_110, PJ28MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PJCR6", 0xfffe3902, 16, 4, GROUP(
-		PJ27MD_000, PJ27MD_001, PJ27MD_010, PJ27MD_011,
-		PJ27MD_100, PJ27MD_101, PJ27MD_110, PJ27MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ26MD_000, PJ26MD_001, PJ26MD_010, PJ26MD_011,
-		PJ26MD_100, PJ26MD_101, PJ26MD_110, PJ26MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ25MD_000, PJ25MD_001, PJ25MD_010, PJ25MD_011,
-		PJ25MD_100, PJ25MD_101, PJ25MD_110, PJ25MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ24MD_000, PJ24MD_001, PJ24MD_010, PJ24MD_011,
-		PJ24MD_100, PJ24MD_101, PJ24MD_110, PJ24MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PJCR5", 0xfffe3904, 16, 4, GROUP(
-		PJ23MD_000, PJ23MD_001, PJ23MD_010, PJ23MD_011,
-		PJ23MD_100, PJ23MD_101, PJ23MD_110, PJ23MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ22MD_000, PJ22MD_001, PJ22MD_010, PJ22MD_011,
-		PJ22MD_100, PJ22MD_101, PJ22MD_110, PJ22MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ21MD_000, PJ21MD_001, PJ21MD_010, PJ21MD_011,
-		PJ21MD_100, PJ21MD_101, PJ21MD_110, PJ21MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ20MD_000, PJ20MD_001, PJ20MD_010, PJ20MD_011,
-		PJ20MD_100, PJ20MD_101, PJ20MD_110, PJ20MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PJCR4", 0xfffe3906, 16, 4, GROUP(
-		PJ19MD_000, PJ19MD_001, PJ19MD_010, PJ19MD_011,
-		PJ19MD_100, PJ19MD_101, PJ19MD_110, PJ19MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ18MD_000, PJ18MD_001, PJ18MD_010, PJ18MD_011,
-		PJ18MD_100, PJ18MD_101, PJ18MD_110, PJ18MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ17MD_000, PJ17MD_001, PJ17MD_010, PJ17MD_011,
-		PJ17MD_100, PJ17MD_101, PJ17MD_110, PJ17MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ16MD_000, PJ16MD_001, PJ16MD_010, PJ16MD_011,
-		PJ16MD_100, PJ16MD_101, PJ16MD_110, PJ16MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PJCR3", 0xfffe3908, 16, 4, GROUP(
-		PJ15MD_000, PJ15MD_001, PJ15MD_010, PJ15MD_011,
-		PJ15MD_100, PJ15MD_101, PJ15MD_110, PJ15MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ14MD_000, PJ14MD_001, PJ14MD_010, PJ14MD_011,
-		PJ14MD_100, PJ14MD_101, PJ14MD_110, PJ14MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ13MD_000, PJ13MD_001, PJ13MD_010, PJ13MD_011,
-		PJ13MD_100, PJ13MD_101, PJ13MD_110, PJ13MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ12MD_000, PJ12MD_001, PJ12MD_010, PJ12MD_011,
-		PJ12MD_100, PJ12MD_101, PJ12MD_110, PJ12MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PJCR2", 0xfffe390a, 16, 4, GROUP(
-		PJ11MD_000, PJ11MD_001, PJ11MD_010, PJ11MD_011,
-		PJ11MD_100, PJ11MD_101, PJ11MD_110, PJ11MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ10MD_000, PJ10MD_001, PJ10MD_010, PJ10MD_011,
-		PJ10MD_100, PJ10MD_101, PJ10MD_110, PJ10MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ9MD_000, PJ9MD_001, PJ9MD_010, PJ9MD_011,
-		PJ9MD_100, PJ9MD_101, PJ9MD_110, PJ9MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ8MD_000, PJ8MD_001, PJ8MD_010, PJ8MD_011,
-		PJ8MD_100, PJ8MD_101, PJ8MD_110, PJ8MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PJCR1", 0xfffe390c, 16, 4, GROUP(
-		PJ7MD_000, PJ7MD_001, PJ7MD_010, PJ7MD_011,
-		PJ7MD_100, PJ7MD_101, PJ7MD_110, PJ7MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ6MD_000, PJ6MD_001, PJ6MD_010, PJ6MD_011,
-		PJ6MD_100, PJ6MD_101, PJ6MD_110, PJ6MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ5MD_000, PJ5MD_001, PJ5MD_010, PJ5MD_011,
-		PJ5MD_100, PJ5MD_101, PJ5MD_110, PJ5MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ4MD_000, PJ4MD_001, PJ4MD_010, PJ4MD_011,
-		PJ4MD_100, PJ4MD_101, PJ4MD_110, PJ4MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PJCR0", 0xfffe390e, 16, 4, GROUP(
-		PJ3MD_000, PJ3MD_001, PJ3MD_010, PJ3MD_011,
-		PJ3MD_100, PJ3MD_101, PJ3MD_110, PJ3MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ2MD_000, PJ2MD_001, PJ2MD_010, PJ2MD_011,
-		PJ2MD_100, PJ2MD_101, PJ2MD_110, PJ2MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ1MD_000, PJ1MD_001, PJ1MD_010, PJ1MD_011,
-		PJ1MD_100, PJ1MD_101, PJ1MD_110, PJ1MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0,
-
-		PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011,
-		PJ0MD_100, PJ0MD_101, PJ0MD_110, PJ0MD_111,
-		0, 0, 0, 0, 0, 0, 0, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PJIOR1", 0xfffe3910, 16, 1, GROUP(
-		PJ31_IN, PJ31_OUT,
-		PJ30_IN, PJ30_OUT,
-		PJ29_IN, PJ29_OUT,
-		PJ28_IN, PJ28_OUT,
-		PJ27_IN, PJ27_OUT,
-		PJ26_IN, PJ26_OUT,
-		PJ25_IN, PJ25_OUT,
-		PJ24_IN, PJ24_OUT,
-		PJ23_IN, PJ23_OUT,
-		PJ22_IN, PJ22_OUT,
-		PJ21_IN, PJ21_OUT,
-		PJ20_IN, PJ20_OUT,
-		PJ19_IN, PJ19_OUT,
-		PJ18_IN, PJ18_OUT,
-		PJ17_IN, PJ17_OUT,
-		PJ16_IN, PJ16_OUT ))
-	},
-	{ PINMUX_CFG_REG("PJIOR0", 0xfffe3912, 16, 1, GROUP(
-		PJ15_IN, PJ15_OUT,
-		PJ14_IN, PJ14_OUT,
-		PJ13_IN, PJ13_OUT,
-		PJ12_IN, PJ12_OUT,
-		PJ11_IN, PJ11_OUT,
-		PJ10_IN, PJ10_OUT,
-		PJ9_IN, PJ9_OUT,
-		PJ8_IN, PJ8_OUT,
-		PJ7_IN, PJ7_OUT,
-		PJ6_IN, PJ6_OUT,
-		PJ5_IN, PJ5_OUT,
-		PJ4_IN, PJ4_OUT,
-		PJ3_IN, PJ3_OUT,
-		PJ2_IN, PJ2_OUT,
-		PJ1_IN, PJ1_OUT,
-		PJ0_IN, PJ0_OUT ))
-	},
-
-	{}
-};
-
-static const struct pinmux_data_reg pinmux_data_regs[] = {
-	{ PINMUX_DATA_REG("PADR0", 0xfffe3816, 16, GROUP(
-		0, 0, 0, 0, 0, 0, 0, PA1_DATA,
-		0, 0, 0, 0, 0, 0, 0, PA0_DATA ))
-	},
-
-	{ PINMUX_DATA_REG("PBDR1", 0xfffe3834, 16, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, PB22_DATA, PB21_DATA, PB20_DATA,
-		PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA ))
-	},
-	{ PINMUX_DATA_REG("PBDR0", 0xfffe3836, 16, GROUP(
-		PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA,
-		PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
-		PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
-		PB3_DATA, PB2_DATA, PB1_DATA, 0 ))
-	},
-
-	{ PINMUX_DATA_REG("PCDR0", 0xfffe3856, 16, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, PC8_DATA,
-		PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
-		PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
-	},
-
-	{ PINMUX_DATA_REG("PDDR0", 0xfffe3876, 16, GROUP(
-		PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
-		PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
-		PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
-		PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
-	},
-
-	{ PINMUX_DATA_REG("PEDR0", 0xfffe3896, 16, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
-		PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA ))
-	},
-
-	{ PINMUX_DATA_REG("PFDR1", 0xfffe38b4, 16, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA,
-		PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA ))
-	},
-	{ PINMUX_DATA_REG("PFDR0", 0xfffe38b6, 16, GROUP(
-		PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA,
-		PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
-		PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
-		PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
-	},
-
-	{ PINMUX_DATA_REG("PGDR1", 0xfffe38d4, 16, GROUP(
-		0, 0, 0, 0,
-		PG27_DATA, PG26_DATA, PG25_DATA, PG24_DATA,
-		PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA,
-		PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA ))
-	},
-	{ PINMUX_DATA_REG("PGDR0", 0xfffe38d6, 16, GROUP(
-		PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA,
-		PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA,
-		PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
-		PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA ))
-	},
-
-	{ PINMUX_DATA_REG("PJDR1", 0xfffe3914, 16, GROUP(
-		PJ31_DATA, PJ30_DATA, PJ29_DATA, PJ28_DATA,
-		PJ27_DATA, PJ26_DATA, PJ25_DATA, PJ24_DATA,
-		PJ23_DATA, PJ22_DATA, PJ21_DATA, PJ20_DATA,
-		PJ19_DATA, PJ18_DATA, PJ17_DATA, PJ16_DATA ))
-	},
-	{ PINMUX_DATA_REG("PJDR0", 0xfffe3916, 16, GROUP(
-		PJ15_DATA, PJ14_DATA, PJ13_DATA, PJ12_DATA,
-		PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA,
-		PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
-		PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA ))
-	},
-
-	{ }
-};
-
-const struct sh_pfc_soc_info sh7269_pinmux_info = {
-	.name = "sh7269_pfc",
-	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
-	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.func_gpios = pinmux_func_gpios,
-	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
-	.cfg_regs = pinmux_config_regs,
-	.data_regs = pinmux_data_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
deleted file mode 100644
index afabd95105d5..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ /dev/null
@@ -1,4413 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * sh73a0 processor support - PFC hardware block
- *
- * Copyright (C) 2010 Renesas Solutions Corp.
- * Copyright (C) 2010 NISHIMOTO Hiroki
- */
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/regulator/driver.h>
-#include <linux/regulator/machine.h>
-#include <linux/slab.h>
-
-#include "core.h"
-#include "sh_pfc.h"
-
-#define CPU_ALL_PORT(fn, pfx, sfx)					\
-	PORT_10(0,  fn, pfx, sfx), PORT_90(0, fn, pfx, sfx),		\
-	PORT_10(100, fn, pfx##10, sfx),					\
-	PORT_1(110, fn, pfx##110, sfx), PORT_1(111, fn, pfx##111, sfx),	\
-	PORT_1(112, fn, pfx##112, sfx), PORT_1(113, fn, pfx##113, sfx),	\
-	PORT_1(114, fn, pfx##114, sfx), PORT_1(115, fn, pfx##115, sfx),	\
-	PORT_1(116, fn, pfx##116, sfx), PORT_1(117, fn, pfx##117, sfx),	\
-	PORT_1(118, fn, pfx##118, sfx),					\
-	PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx),	\
-	PORT_10(130, fn, pfx##13, sfx), PORT_10(140, fn, pfx##14, sfx),	\
-	PORT_10(150, fn, pfx##15, sfx),					\
-	PORT_1(160, fn, pfx##160, sfx), PORT_1(161, fn, pfx##161, sfx),	\
-	PORT_1(162, fn, pfx##162, sfx), PORT_1(163, fn, pfx##163, sfx),	\
-	PORT_1(164, fn, pfx##164, sfx),					\
-	PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx),	\
-	PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx),	\
-	PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx),	\
-	PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx),	\
-	PORT_10(200, fn, pfx##20, sfx), PORT_10(210, fn, pfx##21, sfx),	\
-	PORT_10(220, fn, pfx##22, sfx), PORT_10(230, fn, pfx##23, sfx),	\
-	PORT_10(240, fn, pfx##24, sfx), PORT_10(250, fn, pfx##25, sfx),	\
-	PORT_10(260, fn, pfx##26, sfx), PORT_10(270, fn, pfx##27, sfx),	\
-	PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx),	\
-	PORT_1(282, fn, pfx##282, sfx),					\
-	PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx),	\
-	PORT_10(290, fn, pfx##29, sfx), PORT_10(300, fn, pfx##30, sfx)
-
-#define CPU_ALL_NOGP(fn)	\
-	PIN_NOGP(A11, "F26", fn)
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	PORT_ALL(DATA),			/* PORT0_DATA -> PORT309_DATA */
-	PINMUX_DATA_END,
-
-	PINMUX_INPUT_BEGIN,
-	PORT_ALL(IN),			/* PORT0_IN -> PORT309_IN */
-	PINMUX_INPUT_END,
-
-	PINMUX_OUTPUT_BEGIN,
-	PORT_ALL(OUT),			/* PORT0_OUT -> PORT309_OUT */
-	PINMUX_OUTPUT_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	PORT_ALL(FN_IN),		/* PORT0_FN_IN -> PORT309_FN_IN */
-	PORT_ALL(FN_OUT),		/* PORT0_FN_OUT -> PORT309_FN_OUT */
-	PORT_ALL(FN0),			/* PORT0_FN0 -> PORT309_FN0 */
-	PORT_ALL(FN1),			/* PORT0_FN1 -> PORT309_FN1 */
-	PORT_ALL(FN2),			/* PORT0_FN2 -> PORT309_FN2 */
-	PORT_ALL(FN3),			/* PORT0_FN3 -> PORT309_FN3 */
-	PORT_ALL(FN4),			/* PORT0_FN4 -> PORT309_FN4 */
-	PORT_ALL(FN5),			/* PORT0_FN5 -> PORT309_FN5 */
-	PORT_ALL(FN6),			/* PORT0_FN6 -> PORT309_FN6 */
-	PORT_ALL(FN7),			/* PORT0_FN7 -> PORT309_FN7 */
-
-	MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
-	MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
-	MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
-	MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
-	MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
-	MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
-	MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
-	MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
-	MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
-	MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
-	MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
-	MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
-	MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
-	MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
-	MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
-	MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
-	MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
-	MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
-	MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
-	MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
-	MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
-	MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
-	MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
-	MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
-	MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
-	MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
-	MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
-	MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
-	MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
-	MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
-	MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
-	MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
-	MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
-	MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
-	MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
-	MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
-	MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
-	MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
-	MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
-	MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
-	MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
-	MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-	/* Hardware manual Table 25-1 (Function 0-7) */
-	VBUS_0_MARK,
-	GPI0_MARK,
-	GPI1_MARK,
-	GPI2_MARK,
-	GPI3_MARK,
-	GPI4_MARK,
-	GPI5_MARK,
-	GPI6_MARK,
-	GPI7_MARK,
-	SCIFA7_RXD_MARK,
-	SCIFA7_CTS__MARK,
-	GPO7_MARK, MFG0_OUT2_MARK,
-	GPO6_MARK, MFG1_OUT2_MARK,
-	GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
-	SCIFA0_TXD_MARK,
-	SCIFA7_TXD_MARK,
-	SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
-	GPO0_MARK,
-	GPO1_MARK,
-	GPO2_MARK, STATUS0_MARK,
-	GPO3_MARK, STATUS1_MARK,
-	GPO4_MARK, STATUS2_MARK,
-	VINT_MARK,
-	TCKON_MARK,
-	XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
-	MFG0_OUT1_MARK, PORT27_IROUT_MARK,
-	XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
-	PORT28_TPU1TO1_MARK,
-	SIM_RST_MARK, PORT29_TPU1TO1_MARK,
-	SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
-	SIM_D_MARK, PORT31_IROUT_MARK,
-	SCIFA4_TXD_MARK,
-	SCIFA4_RXD_MARK, XWUP_MARK,
-	SCIFA4_RTS__MARK,
-	SCIFA4_CTS__MARK,
-	FSIBOBT_MARK, FSIBIBT_MARK,
-	FSIBOLR_MARK, FSIBILR_MARK,
-	FSIBOSLD_MARK,
-	FSIBISLD_MARK,
-	VACK_MARK,
-	XTAL1L_MARK,
-	SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
-	SCIFA0_RXD_MARK,
-	SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
-	FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
-	FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
-	FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
-	FSICISLD_MARK, FSIDISLD_MARK,
-	FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
-	FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
-
-	FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
-	FSIAOSLD_MARK, BBIF2_TXD2_MARK,
-	FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
-	PORT53_FSICSPDIF_MARK,
-	FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
-	FSICCK_MARK, FSICOMC_MARK,
-	FSIAISLD_MARK, TPU0TO0_MARK,
-	A0_MARK, BS__MARK,
-	A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
-	A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
-	A14_MARK, KEYOUT5_MARK,
-	A15_MARK, KEYOUT4_MARK,
-	A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
-	A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
-	A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
-	A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
-	A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
-	A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
-	A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
-	A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
-	A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
-	A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
-	A26_MARK, KEYIN6_MARK,
-	KEYIN7_MARK,
-	D0_NAF0_MARK,
-	D1_NAF1_MARK,
-	D2_NAF2_MARK,
-	D3_NAF3_MARK,
-	D4_NAF4_MARK,
-	D5_NAF5_MARK,
-	D6_NAF6_MARK,
-	D7_NAF7_MARK,
-	D8_NAF8_MARK,
-	D9_NAF9_MARK,
-	D10_NAF10_MARK,
-	D11_NAF11_MARK,
-	D12_NAF12_MARK,
-	D13_NAF13_MARK,
-	D14_NAF14_MARK,
-	D15_NAF15_MARK,
-	CS4__MARK,
-	CS5A__MARK, PORT91_RDWR_MARK,
-	CS5B__MARK, FCE1__MARK,
-	CS6B__MARK, DACK0_MARK,
-	FCE0__MARK, CS6A__MARK,
-	WAIT__MARK, DREQ0_MARK,
-	RD__FSC_MARK,
-	WE0__FWE_MARK, RDWR_FWE_MARK,
-	WE1__MARK,
-	FRB_MARK,
-	CKO_MARK,
-	NBRSTOUT__MARK,
-	NBRST__MARK,
-	BBIF2_TXD_MARK,
-	BBIF2_RXD_MARK,
-	BBIF2_SYNC_MARK,
-	BBIF2_SCK_MARK,
-	SCIFA3_CTS__MARK, MFG3_IN2_MARK,
-	SCIFA3_RXD_MARK, MFG3_IN1_MARK,
-	BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
-	SCIFA3_TXD_MARK,
-	HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
-	HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
-	HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
-	HSI_TX_READY_MARK, BBIF1_TXD_MARK,
-	HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
-	PORT115_I2C_SCL3_MARK,
-	HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
-	PORT116_I2C_SDA3_MARK,
-	HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
-	HSI_TX_FLAG_MARK,
-	VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
-
-	VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
-	VIO2_HD_MARK, LCD2D1_MARK,
-	VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
-	VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
-	PORT131_KEYOUT11_MARK, LCD2D11_MARK,
-	VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
-	PORT132_KEYOUT10_MARK, LCD2D12_MARK,
-	VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
-	VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
-	VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
-	VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
-	VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
-	VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
-	VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
-	VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
-	VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
-	VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
-	VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
-	VIO2_D5_MARK, LCD2D3_MARK,
-	VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
-	VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
-	PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
-	VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
-	LCD2D18_MARK,
-	VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
-	VIO_CKO_MARK,
-	A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
-	MFG0_IN2_MARK,
-	TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
-	TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
-	TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
-	SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
-	SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
-	SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
-	SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
-	DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
-	PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
-	PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
-	PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
-	PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
-	PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
-	LCDD0_MARK,
-	LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
-	LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
-	LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
-	LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
-	LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
-	LCDD6_MARK,
-	LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
-	LCDD8_MARK, D16_MARK,
-	LCDD9_MARK, D17_MARK,
-	LCDD10_MARK, D18_MARK,
-	LCDD11_MARK, D19_MARK,
-	LCDD12_MARK, D20_MARK,
-	LCDD13_MARK, D21_MARK,
-	LCDD14_MARK, D22_MARK,
-	LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
-	LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
-	LCDD17_MARK, D25_MARK,
-	LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
-	LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
-	LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
-	LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
-	LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
-	LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
-	LCDDCK_MARK, LCDWR__MARK,
-	LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
-	VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
-	LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
-	PORT218_VIO_CKOR_MARK,
-	LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
-	MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
-	LCDVSYN_MARK, LCDVSYN2_MARK,
-	LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
-	MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
-	LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
-	VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
-
-	SCIFA1_TXD_MARK, OVCN2_MARK,
-	EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
-	SCIFA1_RTS__MARK, IDIN_MARK,
-	SCIFA1_RXD_MARK,
-	SCIFA1_CTS__MARK, MFG1_IN1_MARK,
-	MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
-	MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
-	MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
-	MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
-	MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
-	MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
-	MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
-	MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
-	MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
-	MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
-	SCIFA6_TXD_MARK,
-	PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
-	PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
-	PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
-	PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
-	MSIOF2R_RXD_MARK,
-	PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
-	MSIOF2R_TXD_MARK,
-	PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
-	TPU1TO0_MARK,
-	PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
-	TPU3TO1_MARK,
-	PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
-	TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
-	PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
-	MSIOF2R_TSYNC_MARK,
-	SDHICLK0_MARK,
-	SDHICD0_MARK,
-	SDHID0_0_MARK,
-	SDHID0_1_MARK,
-	SDHID0_2_MARK,
-	SDHID0_3_MARK,
-	SDHICMD0_MARK,
-	SDHIWP0_MARK,
-	SDHICLK1_MARK,
-	SDHID1_0_MARK, TS_SPSYNC2_MARK,
-	SDHID1_1_MARK, TS_SDAT2_MARK,
-	SDHID1_2_MARK, TS_SDEN2_MARK,
-	SDHID1_3_MARK, TS_SCK2_MARK,
-	SDHICMD1_MARK,
-	SDHICLK2_MARK,
-	SDHID2_0_MARK, TS_SPSYNC4_MARK,
-	SDHID2_1_MARK, TS_SDAT4_MARK,
-	SDHID2_2_MARK, TS_SDEN4_MARK,
-	SDHID2_3_MARK, TS_SCK4_MARK,
-	SDHICMD2_MARK,
-	MMCCLK0_MARK,
-	MMCD0_0_MARK,
-	MMCD0_1_MARK,
-	MMCD0_2_MARK,
-	MMCD0_3_MARK,
-	MMCD0_4_MARK, TS_SPSYNC5_MARK,
-	MMCD0_5_MARK, TS_SDAT5_MARK,
-	MMCD0_6_MARK, TS_SDEN5_MARK,
-	MMCD0_7_MARK, TS_SCK5_MARK,
-	MMCCMD0_MARK,
-	RESETOUTS__MARK, EXTAL2OUT_MARK,
-	MCP_WAIT__MCP_FRB_MARK,
-	MCP_CKO_MARK, MMCCLK1_MARK,
-	MCP_D15_MCP_NAF15_MARK,
-	MCP_D14_MCP_NAF14_MARK,
-	MCP_D13_MCP_NAF13_MARK,
-	MCP_D12_MCP_NAF12_MARK,
-	MCP_D11_MCP_NAF11_MARK,
-	MCP_D10_MCP_NAF10_MARK,
-	MCP_D9_MCP_NAF9_MARK,
-	MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
-	MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
-
-	MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
-	MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
-	MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
-	MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
-	MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
-	MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
-	MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
-	MCP_NBRSTOUT__MARK,
-	MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
-
-	/* MSEL2 special cases */
-	TSIF2_TS_XX1_MARK,
-	TSIF2_TS_XX2_MARK,
-	TSIF2_TS_XX3_MARK,
-	TSIF2_TS_XX4_MARK,
-	TSIF2_TS_XX5_MARK,
-	TSIF1_TS_XX1_MARK,
-	TSIF1_TS_XX2_MARK,
-	TSIF1_TS_XX3_MARK,
-	TSIF1_TS_XX4_MARK,
-	TSIF1_TS_XX5_MARK,
-	TSIF0_TS_XX1_MARK,
-	TSIF0_TS_XX2_MARK,
-	TSIF0_TS_XX3_MARK,
-	TSIF0_TS_XX4_MARK,
-	TSIF0_TS_XX5_MARK,
-	MST1_TS_XX1_MARK,
-	MST1_TS_XX2_MARK,
-	MST1_TS_XX3_MARK,
-	MST1_TS_XX4_MARK,
-	MST1_TS_XX5_MARK,
-	MST0_TS_XX1_MARK,
-	MST0_TS_XX2_MARK,
-	MST0_TS_XX3_MARK,
-	MST0_TS_XX4_MARK,
-	MST0_TS_XX5_MARK,
-
-	/* MSEL3 special cases */
-	SDHI0_VCCQ_MC0_ON_MARK,
-	SDHI0_VCCQ_MC0_OFF_MARK,
-	DEBUG_MON_VIO_MARK,
-	DEBUG_MON_LCDD_MARK,
-	LCDC_LCDC0_MARK,
-	LCDC_LCDC1_MARK,
-
-	/* MSEL4 special cases */
-	IRQ9_MEM_INT_MARK,
-	IRQ9_MCP_INT_MARK,
-	A11_MARK,
-	KEYOUT8_MARK,
-	TPU4TO3_MARK,
-	RESETA_N_PU_ON_MARK,
-	RESETA_N_PU_OFF_MARK,
-	EDBGREQ_PD_MARK,
-	EDBGREQ_PU_MARK,
-
-	PINMUX_MARK_END,
-};
-
-static const u16 pinmux_data[] = {
-	/* specify valid pin states for each pin in GPIO mode */
-	PINMUX_DATA_ALL(),
-
-	/* Table 25-1 (Function 0-7) */
-	PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
-	PINMUX_DATA(GPI0_MARK, PORT1_FN1),
-	PINMUX_DATA(GPI1_MARK, PORT2_FN1),
-	PINMUX_DATA(GPI2_MARK, PORT3_FN1),
-	PINMUX_DATA(GPI3_MARK, PORT4_FN1),
-	PINMUX_DATA(GPI4_MARK, PORT5_FN1),
-	PINMUX_DATA(GPI5_MARK, PORT6_FN1),
-	PINMUX_DATA(GPI6_MARK, PORT7_FN1),
-	PINMUX_DATA(GPI7_MARK, PORT8_FN1),
-	PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
-	PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
-	PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
-	PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
-	PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
-	PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
-	PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
-	PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
-	PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
-	PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
-	PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
-	PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
-	PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
-	PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
-	PINMUX_DATA(GPO0_MARK, PORT20_FN1),
-	PINMUX_DATA(GPO1_MARK, PORT21_FN1),
-	PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
-	PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
-	PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
-	PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
-	PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
-	PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
-	PINMUX_DATA(VINT_MARK, PORT25_FN1),
-	PINMUX_DATA(TCKON_MARK, PORT26_FN1),
-	PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
-	PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
-		MSEL2CR_MSEL16_1), \
-	PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
-		MSEL2CR_MSEL18_1), \
-	PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
-	PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
-	PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
-	PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
-		MSEL2CR_MSEL16_1), \
-	PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
-		MSEL2CR_MSEL18_1), \
-	PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
-	PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
-	PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
-	PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
-	PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
-	PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
-	PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
-	PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
-	PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
-	PINMUX_DATA(XWUP_MARK, PORT33_FN3),
-	PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
-	PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
-	PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
-	PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
-	PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
-	PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
-	PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
-	PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
-	PINMUX_DATA(VACK_MARK, PORT40_FN1),
-	PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
-	PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
-	PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
-	PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
-	PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
-	PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
-	PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
-	PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
-	PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
-	PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
-	PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
-	PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
-	PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
-	PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
-	PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
-	PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
-	PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
-	PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
-	PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
-	PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
-	PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
-	PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
-	PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
-	PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
-	PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
-	PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
-
-	PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
-	PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
-	PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
-	PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
-	PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
-	PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
-	PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
-	PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
-	PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
-	PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
-	PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
-	PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
-	PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
-	PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
-	PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
-	PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
-	PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
-	PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
-	PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
-	PINMUX_DATA(A0_MARK, PORT57_FN1), \
-	PINMUX_DATA(BS__MARK, PORT57_FN2),
-	PINMUX_DATA(A12_MARK, PORT58_FN1), \
-	PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
-	PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
-	PINMUX_DATA(A13_MARK, PORT59_FN1), \
-	PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
-	PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
-	PINMUX_DATA(A14_MARK, PORT60_FN1), \
-	PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
-	PINMUX_DATA(A15_MARK, PORT61_FN1), \
-	PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
-	PINMUX_DATA(A16_MARK, PORT62_FN1), \
-	PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
-	PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
-	PINMUX_DATA(A17_MARK, PORT63_FN1), \
-	PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
-	PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
-	PINMUX_DATA(A18_MARK, PORT64_FN1), \
-	PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
-	PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
-	PINMUX_DATA(A19_MARK, PORT65_FN1), \
-	PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
-	PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
-	PINMUX_DATA(A20_MARK, PORT66_FN1), \
-	PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
-	PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
-	PINMUX_DATA(A21_MARK, PORT67_FN1), \
-	PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
-	PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
-	PINMUX_DATA(A22_MARK, PORT68_FN1), \
-	PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
-	PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
-	PINMUX_DATA(A23_MARK, PORT69_FN1), \
-	PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
-	PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
-	PINMUX_DATA(A24_MARK, PORT70_FN1), \
-	PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
-	PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
-	PINMUX_DATA(A25_MARK, PORT71_FN1), \
-	PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
-	PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
-	PINMUX_DATA(A26_MARK, PORT72_FN1), \
-	PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
-	PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
-	PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
-	PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
-	PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
-	PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
-	PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
-	PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
-	PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
-	PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
-	PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
-	PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
-	PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
-	PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
-	PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
-	PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
-	PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
-	PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
-	PINMUX_DATA(CS4__MARK, PORT90_FN1),
-	PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
-	PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
-	PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
-	PINMUX_DATA(FCE1__MARK, PORT92_FN2),
-	PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
-	PINMUX_DATA(DACK0_MARK, PORT93_FN4),
-	PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
-	PINMUX_DATA(CS6A__MARK, PORT94_FN2),
-	PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
-	PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
-	PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
-	PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
-	PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
-	PINMUX_DATA(WE1__MARK, PORT98_FN1),
-	PINMUX_DATA(FRB_MARK, PORT99_FN1),
-	PINMUX_DATA(CKO_MARK, PORT100_FN1),
-	PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
-	PINMUX_DATA(NBRST__MARK, PORT102_FN1),
-	PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
-	PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
-	PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
-	PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
-	PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
-	PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
-	PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
-	PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
-	PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
-	PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
-	PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
-	PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
-	PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
-	PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
-	PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
-	PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
-	PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
-	PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
-	PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
-	PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
-	PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
-	PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
-	PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
-	PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
-	PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
-	PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
-	PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
-	PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
-	PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
-	PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
-	PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
-	PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
-	PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
-	PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
-	PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
-	PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
-
-	PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
-	PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
-	PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
-	PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
-	PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
-	PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
-	PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
-		MSEL4CR_MSEL10_1), \
-	PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
-	PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
-	PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
-	PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
-	PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
-	PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
-	PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
-	PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
-	PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
-	PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
-	PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
-	PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
-	PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
-	PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
-	PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
-	PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
-	PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
-	PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
-	PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
-	PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
-	PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
-	PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
-	PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
-	PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
-	PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
-	PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
-	PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
-	PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
-	PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
-	PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
-	PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
-	PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
-	PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
-	PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
-	PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
-	PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
-	PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
-	PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
-	PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
-	PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
-	PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
-	PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
-	PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
-	PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
-	PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
-	PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
-	PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
-	PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
-	PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
-	PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
-	PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
-	PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
-	PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
-	PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
-	PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
-	PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
-	PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
-	PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
-	PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
-	PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
-	PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
-	PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
-	PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
-	PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
-	PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
-	PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
-	PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
-	PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
-	PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
-	PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
-	PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
-	PINMUX_DATA(A27_MARK, PORT149_FN1), \
-	PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
-	PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
-	PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
-	PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
-	PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
-	PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
-	PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
-	PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
-	PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
-	PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
-	PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
-	PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
-	PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
-	PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
-	PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
-	PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
-	PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
-	PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
-	PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
-		MSEL4CR_MSEL10_0),
-	PINMUX_DATA(DINT__MARK, PORT158_FN1), \
-	PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
-	PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
-	PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
-	PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
-	PINMUX_DATA(NMI_MARK, PORT159_FN3),
-	PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
-	PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
-	PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
-	PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
-	PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
-	PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
-	PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
-	PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
-	PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
-	PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
-	PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
-	PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
-		MSEL4CR_MSEL20_1), \
-	PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
-	PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
-	PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
-		MSEL4CR_MSEL20_1), \
-	PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
-	PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
-	PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
-		MSEL4CR_MSEL20_1), \
-	PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
-	PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
-	PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
-		MSEL4CR_MSEL20_1),
-	PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
-	PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
-		MSEL4CR_MSEL20_1), \
-	PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
-	PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
-	PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
-	PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
-	PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
-	PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
-	PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
-	PINMUX_DATA(D16_MARK, PORT200_FN6),
-	PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
-	PINMUX_DATA(D17_MARK, PORT201_FN6),
-	PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
-	PINMUX_DATA(D18_MARK, PORT202_FN6),
-	PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
-	PINMUX_DATA(D19_MARK, PORT203_FN6),
-	PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
-	PINMUX_DATA(D20_MARK, PORT204_FN6),
-	PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
-	PINMUX_DATA(D21_MARK, PORT205_FN6),
-	PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
-	PINMUX_DATA(D22_MARK, PORT206_FN6),
-	PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
-	PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
-	PINMUX_DATA(D23_MARK, PORT207_FN6),
-	PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
-	PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
-	PINMUX_DATA(D24_MARK, PORT208_FN6),
-	PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
-	PINMUX_DATA(D25_MARK, PORT209_FN6),
-	PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
-	PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
-	PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
-	PINMUX_DATA(D26_MARK, PORT210_FN6),
-	PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
-	PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
-	PINMUX_DATA(D27_MARK, PORT211_FN6),
-	PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
-	PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
-	PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
-	PINMUX_DATA(D28_MARK, PORT212_FN6),
-	PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
-	PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
-	PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
-	PINMUX_DATA(D29_MARK, PORT213_FN6),
-	PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
-	PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
-	PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
-	PINMUX_DATA(D30_MARK, PORT214_FN6),
-	PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
-	PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
-	PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
-	PINMUX_DATA(D31_MARK, PORT215_FN6),
-	PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
-	PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
-	PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
-	PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
-	PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
-	PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
-	PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
-		MSEL4CR_MSEL26_1), \
-	PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
-	PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
-	PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
-	PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
-	PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
-	PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
-	PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
-	PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
-	PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
-	PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
-	PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
-	PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
-		MSEL4CR_MSEL26_1), \
-	PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
-	PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
-	PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
-	PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
-	PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
-	PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
-	PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
-	PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
-	PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
-		MSEL4CR_MSEL26_1), \
-	PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
-	PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
-	PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
-	PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
-	PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
-	PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
-	PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
-		MSEL4CR_MSEL26_1), \
-	PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
-
-	PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
-	PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
-	PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
-	PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
-	PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
-	PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
-	PINMUX_DATA(IDIN_MARK, PORT227_FN4),
-	PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
-	PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
-	PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
-	PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
-	PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
-	PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
-	PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
-	PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
-	PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
-	PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
-	PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
-	PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
-	PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
-	PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
-		MSEL4CR_MSEL26_0), \
-	PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
-	PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
-	PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
-	PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
-		MSEL4CR_MSEL26_0), \
-	PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
-	PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
-	PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
-		MSEL2CR_MSEL16_0),
-	PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
-	PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
-		MSEL2CR_MSEL16_0),
-	PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
-	PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
-		MSEL4CR_MSEL26_0), \
-	PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
-	PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
-	PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
-		MSEL4CR_MSEL26_0), \
-	PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
-	PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
-	PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
-	PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
-	PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
-	PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
-	PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
-	PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
-	PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
-	PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
-	PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
-		MSEL4CR_MSEL20_0), \
-	PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
-	PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
-	PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
-	PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
-		MSEL4CR_MSEL20_0), \
-	PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
-	PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
-	PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
-	PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
-		MSEL4CR_MSEL20_0), \
-	PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
-	PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
-	PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
-	PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
-		MSEL4CR_MSEL20_0), \
-	PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
-	PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
-	PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
-	PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
-		MSEL4CR_MSEL20_0), \
-	PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
-	PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
-	PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
-	PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
-		MSEL2CR_MSEL18_0), \
-	PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
-	PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
-	PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
-	PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
-		MSEL2CR_MSEL18_0), \
-	PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
-	PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
-	PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
-	PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
-	PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
-	PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
-	PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
-	PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
-	PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
-	PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
-	PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
-	PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
-	PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
-	PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
-	PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
-	PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
-	PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
-	PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
-	PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
-	PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
-	PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
-	PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
-	PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
-	PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
-	PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
-	PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
-	PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
-	PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
-	PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
-	PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
-	PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
-	PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
-	PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
-	PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
-	PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0),
-	PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
-	PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0),
-	PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
-	PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0),
-	PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
-	PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0),
-	PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
-	PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
-	PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
-	PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
-	PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
-	PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
-	PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
-	PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
-	PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
-	PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
-	PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
-	PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
-	PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
-	PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
-	PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
-	PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
-	PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
-	PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
-
-	PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
-	PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
-	PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
-	PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
-	PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
-	PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
-	PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
-	PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
-	PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
-	PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
-	PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
-	PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
-	PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
-	PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
-	PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
-	PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
-	PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
-
-	/* MSEL2 special cases */
-	PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
-		MSEL2CR_MSEL12_0),
-	PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
-		MSEL2CR_MSEL12_1),
-	PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
-		MSEL2CR_MSEL12_0),
-	PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
-		MSEL2CR_MSEL12_1),
-	PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
-		MSEL2CR_MSEL12_0),
-	PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
-		MSEL2CR_MSEL9_0),
-	PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
-		MSEL2CR_MSEL9_1),
-	PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
-		MSEL2CR_MSEL9_0),
-	PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
-		MSEL2CR_MSEL9_1),
-	PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
-		MSEL2CR_MSEL9_0),
-	PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
-		MSEL2CR_MSEL6_0),
-	PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
-		MSEL2CR_MSEL6_1),
-	PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
-		MSEL2CR_MSEL6_0),
-	PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
-		MSEL2CR_MSEL6_1),
-	PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
-		MSEL2CR_MSEL6_0),
-	PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
-		MSEL2CR_MSEL3_0),
-	PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
-		MSEL2CR_MSEL3_1),
-	PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
-		MSEL2CR_MSEL3_0),
-	PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
-		MSEL2CR_MSEL3_1),
-	PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
-		MSEL2CR_MSEL3_0),
-	PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
-		MSEL2CR_MSEL0_0),
-	PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
-		MSEL2CR_MSEL0_1),
-	PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
-		MSEL2CR_MSEL0_0),
-	PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
-		MSEL2CR_MSEL0_1),
-	PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
-		MSEL2CR_MSEL0_0),
-
-	/* MSEL3 special cases */
-	PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
-	PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
-	PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
-	PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
-	PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
-	PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
-
-	/* MSEL4 special cases */
-	PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
-	PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
-	PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
-	PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
-	PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
-	PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
-	PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
-	PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
-	PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
-};
-
-#define __I		(SH_PFC_PIN_CFG_INPUT)
-#define __O		(SH_PFC_PIN_CFG_OUTPUT)
-#define __IO		(SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
-#define __PD		(SH_PFC_PIN_CFG_PULL_DOWN)
-#define __PU		(SH_PFC_PIN_CFG_PULL_UP)
-#define __PUD		(SH_PFC_PIN_CFG_PULL_UP_DOWN)
-
-#define SH73A0_PIN_I_PD(pin)		SH_PFC_PIN_CFG(pin, __I | __PD)
-#define SH73A0_PIN_I_PU(pin)		SH_PFC_PIN_CFG(pin, __I | __PU)
-#define SH73A0_PIN_I_PU_PD(pin)		SH_PFC_PIN_CFG(pin, __I | __PUD)
-#define SH73A0_PIN_IO(pin)		SH_PFC_PIN_CFG(pin, __IO)
-#define SH73A0_PIN_IO_PD(pin)		SH_PFC_PIN_CFG(pin, __IO | __PD)
-#define SH73A0_PIN_IO_PU(pin)		SH_PFC_PIN_CFG(pin, __IO | __PU)
-#define SH73A0_PIN_IO_PU_PD(pin)	SH_PFC_PIN_CFG(pin, __IO | __PUD)
-#define SH73A0_PIN_O(pin)		SH_PFC_PIN_CFG(pin, __O)
-
-/*
- * Pins not associated with a GPIO port.
- */
-enum {
-	PORT_ASSIGN_LAST(),
-	NOGP_ALL(),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	/* Table 25-1 (I/O and Pull U/D) */
-	SH73A0_PIN_I_PD(0),
-	SH73A0_PIN_I_PU(1),
-	SH73A0_PIN_I_PU(2),
-	SH73A0_PIN_I_PU(3),
-	SH73A0_PIN_I_PU(4),
-	SH73A0_PIN_I_PU(5),
-	SH73A0_PIN_I_PU(6),
-	SH73A0_PIN_I_PU(7),
-	SH73A0_PIN_I_PU(8),
-	SH73A0_PIN_I_PD(9),
-	SH73A0_PIN_I_PD(10),
-	SH73A0_PIN_I_PU_PD(11),
-	SH73A0_PIN_IO_PU_PD(12),
-	SH73A0_PIN_IO_PU_PD(13),
-	SH73A0_PIN_IO_PU_PD(14),
-	SH73A0_PIN_IO_PU_PD(15),
-	SH73A0_PIN_IO_PD(16),
-	SH73A0_PIN_IO_PD(17),
-	SH73A0_PIN_IO_PU(18),
-	SH73A0_PIN_IO_PU(19),
-	SH73A0_PIN_O(20),
-	SH73A0_PIN_O(21),
-	SH73A0_PIN_O(22),
-	SH73A0_PIN_O(23),
-	SH73A0_PIN_O(24),
-	SH73A0_PIN_I_PD(25),
-	SH73A0_PIN_I_PD(26),
-	SH73A0_PIN_IO_PU(27),
-	SH73A0_PIN_IO_PU(28),
-	SH73A0_PIN_IO_PD(29),
-	SH73A0_PIN_IO_PD(30),
-	SH73A0_PIN_IO_PU(31),
-	SH73A0_PIN_IO_PD(32),
-	SH73A0_PIN_I_PU_PD(33),
-	SH73A0_PIN_IO_PD(34),
-	SH73A0_PIN_I_PU_PD(35),
-	SH73A0_PIN_IO_PD(36),
-	SH73A0_PIN_IO(37),
-	SH73A0_PIN_O(38),
-	SH73A0_PIN_I_PU(39),
-	SH73A0_PIN_I_PU_PD(40),
-	SH73A0_PIN_O(41),
-	SH73A0_PIN_IO_PD(42),
-	SH73A0_PIN_IO_PU_PD(43),
-	SH73A0_PIN_IO_PU_PD(44),
-	SH73A0_PIN_IO_PD(45),
-	SH73A0_PIN_IO_PD(46),
-	SH73A0_PIN_IO_PD(47),
-	SH73A0_PIN_I_PD(48),
-	SH73A0_PIN_IO_PU_PD(49),
-	SH73A0_PIN_IO_PD(50),
-	SH73A0_PIN_IO_PD(51),
-	SH73A0_PIN_O(52),
-	SH73A0_PIN_IO_PU_PD(53),
-	SH73A0_PIN_IO_PU_PD(54),
-	SH73A0_PIN_IO_PD(55),
-	SH73A0_PIN_I_PU_PD(56),
-	SH73A0_PIN_IO(57),
-	SH73A0_PIN_IO(58),
-	SH73A0_PIN_IO(59),
-	SH73A0_PIN_IO(60),
-	SH73A0_PIN_IO(61),
-	SH73A0_PIN_IO_PD(62),
-	SH73A0_PIN_IO_PD(63),
-	SH73A0_PIN_IO_PU_PD(64),
-	SH73A0_PIN_IO_PD(65),
-	SH73A0_PIN_IO_PU_PD(66),
-	SH73A0_PIN_IO_PU_PD(67),
-	SH73A0_PIN_IO_PU_PD(68),
-	SH73A0_PIN_IO_PU_PD(69),
-	SH73A0_PIN_IO_PU_PD(70),
-	SH73A0_PIN_IO_PU_PD(71),
-	SH73A0_PIN_IO_PU_PD(72),
-	SH73A0_PIN_I_PU_PD(73),
-	SH73A0_PIN_IO_PU(74),
-	SH73A0_PIN_IO_PU(75),
-	SH73A0_PIN_IO_PU(76),
-	SH73A0_PIN_IO_PU(77),
-	SH73A0_PIN_IO_PU(78),
-	SH73A0_PIN_IO_PU(79),
-	SH73A0_PIN_IO_PU(80),
-	SH73A0_PIN_IO_PU(81),
-	SH73A0_PIN_IO_PU(82),
-	SH73A0_PIN_IO_PU(83),
-	SH73A0_PIN_IO_PU(84),
-	SH73A0_PIN_IO_PU(85),
-	SH73A0_PIN_IO_PU(86),
-	SH73A0_PIN_IO_PU(87),
-	SH73A0_PIN_IO_PU(88),
-	SH73A0_PIN_IO_PU(89),
-	SH73A0_PIN_O(90),
-	SH73A0_PIN_IO_PU(91),
-	SH73A0_PIN_O(92),
-	SH73A0_PIN_IO_PU(93),
-	SH73A0_PIN_O(94),
-	SH73A0_PIN_I_PU_PD(95),
-	SH73A0_PIN_IO(96),
-	SH73A0_PIN_IO(97),
-	SH73A0_PIN_IO(98),
-	SH73A0_PIN_I_PU(99),
-	SH73A0_PIN_O(100),
-	SH73A0_PIN_O(101),
-	SH73A0_PIN_I_PU(102),
-	SH73A0_PIN_IO_PD(103),
-	SH73A0_PIN_I_PU_PD(104),
-	SH73A0_PIN_I_PD(105),
-	SH73A0_PIN_I_PD(106),
-	SH73A0_PIN_I_PU_PD(107),
-	SH73A0_PIN_I_PU_PD(108),
-	SH73A0_PIN_IO_PD(109),
-	SH73A0_PIN_IO_PD(110),
-	SH73A0_PIN_IO_PU_PD(111),
-	SH73A0_PIN_IO_PU_PD(112),
-	SH73A0_PIN_IO_PU_PD(113),
-	SH73A0_PIN_IO_PD(114),
-	SH73A0_PIN_IO_PU(115),
-	SH73A0_PIN_IO_PU(116),
-	SH73A0_PIN_IO_PU_PD(117),
-	SH73A0_PIN_IO_PU_PD(118),
-	SH73A0_PIN_IO_PD(128),
-	SH73A0_PIN_IO_PD(129),
-	SH73A0_PIN_IO_PU_PD(130),
-	SH73A0_PIN_IO_PD(131),
-	SH73A0_PIN_IO_PD(132),
-	SH73A0_PIN_IO_PD(133),
-	SH73A0_PIN_IO_PU_PD(134),
-	SH73A0_PIN_IO_PU_PD(135),
-	SH73A0_PIN_IO_PU_PD(136),
-	SH73A0_PIN_IO_PU_PD(137),
-	SH73A0_PIN_IO_PD(138),
-	SH73A0_PIN_IO_PD(139),
-	SH73A0_PIN_IO_PD(140),
-	SH73A0_PIN_IO_PD(141),
-	SH73A0_PIN_IO_PD(142),
-	SH73A0_PIN_IO_PD(143),
-	SH73A0_PIN_IO_PU_PD(144),
-	SH73A0_PIN_IO_PD(145),
-	SH73A0_PIN_IO_PU_PD(146),
-	SH73A0_PIN_IO_PU_PD(147),
-	SH73A0_PIN_IO_PU_PD(148),
-	SH73A0_PIN_IO_PU_PD(149),
-	SH73A0_PIN_I_PU_PD(150),
-	SH73A0_PIN_IO_PU_PD(151),
-	SH73A0_PIN_IO_PU_PD(152),
-	SH73A0_PIN_IO_PD(153),
-	SH73A0_PIN_IO_PD(154),
-	SH73A0_PIN_I_PU_PD(155),
-	SH73A0_PIN_IO_PU_PD(156),
-	SH73A0_PIN_I_PD(157),
-	SH73A0_PIN_IO_PD(158),
-	SH73A0_PIN_IO_PU_PD(159),
-	SH73A0_PIN_IO_PU_PD(160),
-	SH73A0_PIN_I_PU_PD(161),
-	SH73A0_PIN_I_PU_PD(162),
-	SH73A0_PIN_IO_PU_PD(163),
-	SH73A0_PIN_I_PU_PD(164),
-	SH73A0_PIN_IO_PD(192),
-	SH73A0_PIN_IO_PU_PD(193),
-	SH73A0_PIN_IO_PD(194),
-	SH73A0_PIN_IO_PU_PD(195),
-	SH73A0_PIN_IO_PD(196),
-	SH73A0_PIN_IO_PD(197),
-	SH73A0_PIN_IO_PD(198),
-	SH73A0_PIN_IO_PD(199),
-	SH73A0_PIN_IO_PU_PD(200),
-	SH73A0_PIN_IO_PU_PD(201),
-	SH73A0_PIN_IO_PU_PD(202),
-	SH73A0_PIN_IO_PU_PD(203),
-	SH73A0_PIN_IO_PU_PD(204),
-	SH73A0_PIN_IO_PU_PD(205),
-	SH73A0_PIN_IO_PU_PD(206),
-	SH73A0_PIN_IO_PD(207),
-	SH73A0_PIN_IO_PD(208),
-	SH73A0_PIN_IO_PD(209),
-	SH73A0_PIN_IO_PD(210),
-	SH73A0_PIN_IO_PD(211),
-	SH73A0_PIN_IO_PD(212),
-	SH73A0_PIN_IO_PD(213),
-	SH73A0_PIN_IO_PU_PD(214),
-	SH73A0_PIN_IO_PU_PD(215),
-	SH73A0_PIN_IO_PD(216),
-	SH73A0_PIN_IO_PD(217),
-	SH73A0_PIN_O(218),
-	SH73A0_PIN_IO_PD(219),
-	SH73A0_PIN_IO_PD(220),
-	SH73A0_PIN_IO_PU_PD(221),
-	SH73A0_PIN_IO_PU_PD(222),
-	SH73A0_PIN_I_PU_PD(223),
-	SH73A0_PIN_I_PU_PD(224),
-	SH73A0_PIN_IO_PU_PD(225),
-	SH73A0_PIN_O(226),
-	SH73A0_PIN_IO_PU_PD(227),
-	SH73A0_PIN_I_PU_PD(228),
-	SH73A0_PIN_I_PD(229),
-	SH73A0_PIN_IO(230),
-	SH73A0_PIN_IO_PU_PD(231),
-	SH73A0_PIN_IO_PU_PD(232),
-	SH73A0_PIN_I_PU_PD(233),
-	SH73A0_PIN_IO_PU_PD(234),
-	SH73A0_PIN_IO_PU_PD(235),
-	SH73A0_PIN_IO_PU_PD(236),
-	SH73A0_PIN_IO_PD(237),
-	SH73A0_PIN_IO_PU_PD(238),
-	SH73A0_PIN_IO_PU_PD(239),
-	SH73A0_PIN_IO_PU_PD(240),
-	SH73A0_PIN_O(241),
-	SH73A0_PIN_I_PD(242),
-	SH73A0_PIN_IO_PU_PD(243),
-	SH73A0_PIN_IO_PU_PD(244),
-	SH73A0_PIN_IO_PU_PD(245),
-	SH73A0_PIN_IO_PU_PD(246),
-	SH73A0_PIN_IO_PU_PD(247),
-	SH73A0_PIN_IO_PU_PD(248),
-	SH73A0_PIN_IO_PU_PD(249),
-	SH73A0_PIN_IO_PU_PD(250),
-	SH73A0_PIN_IO_PU_PD(251),
-	SH73A0_PIN_IO_PU_PD(252),
-	SH73A0_PIN_IO_PU_PD(253),
-	SH73A0_PIN_IO_PU_PD(254),
-	SH73A0_PIN_IO_PU_PD(255),
-	SH73A0_PIN_IO_PU_PD(256),
-	SH73A0_PIN_IO_PU_PD(257),
-	SH73A0_PIN_IO_PU_PD(258),
-	SH73A0_PIN_IO_PU_PD(259),
-	SH73A0_PIN_IO_PU_PD(260),
-	SH73A0_PIN_IO_PU_PD(261),
-	SH73A0_PIN_IO_PU_PD(262),
-	SH73A0_PIN_IO_PU_PD(263),
-	SH73A0_PIN_IO_PU_PD(264),
-	SH73A0_PIN_IO_PU_PD(265),
-	SH73A0_PIN_IO_PU_PD(266),
-	SH73A0_PIN_IO_PU_PD(267),
-	SH73A0_PIN_IO_PU_PD(268),
-	SH73A0_PIN_IO_PU_PD(269),
-	SH73A0_PIN_IO_PU_PD(270),
-	SH73A0_PIN_IO_PU_PD(271),
-	SH73A0_PIN_IO_PU_PD(272),
-	SH73A0_PIN_IO_PU_PD(273),
-	SH73A0_PIN_IO_PU_PD(274),
-	SH73A0_PIN_IO_PU_PD(275),
-	SH73A0_PIN_IO_PU_PD(276),
-	SH73A0_PIN_IO_PU_PD(277),
-	SH73A0_PIN_IO_PU_PD(278),
-	SH73A0_PIN_IO_PU_PD(279),
-	SH73A0_PIN_IO_PU_PD(280),
-	SH73A0_PIN_O(281),
-	SH73A0_PIN_O(282),
-	SH73A0_PIN_I_PU(288),
-	SH73A0_PIN_IO_PU_PD(289),
-	SH73A0_PIN_IO_PU_PD(290),
-	SH73A0_PIN_IO_PU_PD(291),
-	SH73A0_PIN_IO_PU_PD(292),
-	SH73A0_PIN_IO_PU_PD(293),
-	SH73A0_PIN_IO_PU_PD(294),
-	SH73A0_PIN_IO_PU_PD(295),
-	SH73A0_PIN_IO_PU_PD(296),
-	SH73A0_PIN_IO_PU_PD(297),
-	SH73A0_PIN_IO_PU_PD(298),
-	SH73A0_PIN_IO_PU_PD(299),
-	SH73A0_PIN_IO_PU_PD(300),
-	SH73A0_PIN_IO_PU_PD(301),
-	SH73A0_PIN_IO_PU_PD(302),
-	SH73A0_PIN_IO_PU_PD(303),
-	SH73A0_PIN_IO_PU_PD(304),
-	SH73A0_PIN_IO_PU_PD(305),
-	SH73A0_PIN_O(306),
-	SH73A0_PIN_O(307),
-	SH73A0_PIN_I_PU(308),
-	SH73A0_PIN_O(309),
-
-	/* Pins not associated with a GPIO port */
-	PINMUX_NOGP_ALL(),
-};
-
-/* - BSC -------------------------------------------------------------------- */
-static const unsigned int bsc_data_0_7_pins[] = {
-	/* D[0:7] */
-	74, 75, 76, 77, 78, 79, 80, 81,
-};
-static const unsigned int bsc_data_0_7_mux[] = {
-	D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
-	D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
-};
-static const unsigned int bsc_data_8_15_pins[] = {
-	/* D[8:15] */
-	82, 83, 84, 85, 86, 87, 88, 89,
-};
-static const unsigned int bsc_data_8_15_mux[] = {
-	D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
-	D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
-};
-static const unsigned int bsc_cs4_pins[] = {
-	/* CS */
-	90,
-};
-static const unsigned int bsc_cs4_mux[] = {
-	CS4__MARK,
-};
-static const unsigned int bsc_cs5_a_pins[] = {
-	/* CS */
-	91,
-};
-static const unsigned int bsc_cs5_a_mux[] = {
-	CS5A__MARK,
-};
-static const unsigned int bsc_cs5_b_pins[] = {
-	/* CS */
-	92,
-};
-static const unsigned int bsc_cs5_b_mux[] = {
-	CS5B__MARK,
-};
-static const unsigned int bsc_cs6_a_pins[] = {
-	/* CS */
-	94,
-};
-static const unsigned int bsc_cs6_a_mux[] = {
-	CS6A__MARK,
-};
-static const unsigned int bsc_cs6_b_pins[] = {
-	/* CS */
-	93,
-};
-static const unsigned int bsc_cs6_b_mux[] = {
-	CS6B__MARK,
-};
-static const unsigned int bsc_rd_pins[] = {
-	/* RD */
-	96,
-};
-static const unsigned int bsc_rd_mux[] = {
-	RD__FSC_MARK,
-};
-static const unsigned int bsc_rdwr_0_pins[] = {
-	/* RDWR */
-	91,
-};
-static const unsigned int bsc_rdwr_0_mux[] = {
-	PORT91_RDWR_MARK,
-};
-static const unsigned int bsc_rdwr_1_pins[] = {
-	/* RDWR */
-	97,
-};
-static const unsigned int bsc_rdwr_1_mux[] = {
-	RDWR_FWE_MARK,
-};
-static const unsigned int bsc_rdwr_2_pins[] = {
-	/* RDWR */
-	149,
-};
-static const unsigned int bsc_rdwr_2_mux[] = {
-	PORT149_RDWR_MARK,
-};
-static const unsigned int bsc_we0_pins[] = {
-	/* WE0 */
-	97,
-};
-static const unsigned int bsc_we0_mux[] = {
-	WE0__FWE_MARK,
-};
-static const unsigned int bsc_we1_pins[] = {
-	/* WE1 */
-	98,
-};
-static const unsigned int bsc_we1_mux[] = {
-	WE1__MARK,
-};
-/* - FSIA ------------------------------------------------------------------- */
-static const unsigned int fsia_mclk_in_pins[] = {
-	/* CK */
-	49,
-};
-static const unsigned int fsia_mclk_in_mux[] = {
-	FSIACK_MARK,
-};
-static const unsigned int fsia_mclk_out_pins[] = {
-	/* OMC */
-	49,
-};
-static const unsigned int fsia_mclk_out_mux[] = {
-	FSIAOMC_MARK,
-};
-static const unsigned int fsia_sclk_in_pins[] = {
-	/* ILR, IBT */
-	50, 51,
-};
-static const unsigned int fsia_sclk_in_mux[] = {
-	FSIAILR_MARK, FSIAIBT_MARK,
-};
-static const unsigned int fsia_sclk_out_pins[] = {
-	/* OLR, OBT */
-	50, 51,
-};
-static const unsigned int fsia_sclk_out_mux[] = {
-	FSIAOLR_MARK, FSIAOBT_MARK,
-};
-static const unsigned int fsia_data_in_pins[] = {
-	/* ISLD */
-	55,
-};
-static const unsigned int fsia_data_in_mux[] = {
-	FSIAISLD_MARK,
-};
-static const unsigned int fsia_data_out_pins[] = {
-	/* OSLD */
-	52,
-};
-static const unsigned int fsia_data_out_mux[] = {
-	FSIAOSLD_MARK,
-};
-static const unsigned int fsia_spdif_pins[] = {
-	/* SPDIF */
-	53,
-};
-static const unsigned int fsia_spdif_mux[] = {
-	FSIASPDIF_MARK,
-};
-/* - FSIB ------------------------------------------------------------------- */
-static const unsigned int fsib_mclk_in_pins[] = {
-	/* CK */
-	54,
-};
-static const unsigned int fsib_mclk_in_mux[] = {
-	FSIBCK_MARK,
-};
-static const unsigned int fsib_mclk_out_pins[] = {
-	/* OMC */
-	54,
-};
-static const unsigned int fsib_mclk_out_mux[] = {
-	FSIBOMC_MARK,
-};
-static const unsigned int fsib_sclk_in_pins[] = {
-	/* ILR, IBT */
-	37, 36,
-};
-static const unsigned int fsib_sclk_in_mux[] = {
-	FSIBILR_MARK, FSIBIBT_MARK,
-};
-static const unsigned int fsib_sclk_out_pins[] = {
-	/* OLR, OBT */
-	37, 36,
-};
-static const unsigned int fsib_sclk_out_mux[] = {
-	FSIBOLR_MARK, FSIBOBT_MARK,
-};
-static const unsigned int fsib_data_in_pins[] = {
-	/* ISLD */
-	39,
-};
-static const unsigned int fsib_data_in_mux[] = {
-	FSIBISLD_MARK,
-};
-static const unsigned int fsib_data_out_pins[] = {
-	/* OSLD */
-	38,
-};
-static const unsigned int fsib_data_out_mux[] = {
-	FSIBOSLD_MARK,
-};
-static const unsigned int fsib_spdif_pins[] = {
-	/* SPDIF */
-	53,
-};
-static const unsigned int fsib_spdif_mux[] = {
-	FSIBSPDIF_MARK,
-};
-/* - FSIC ------------------------------------------------------------------- */
-static const unsigned int fsic_mclk_in_pins[] = {
-	/* CK */
-	54,
-};
-static const unsigned int fsic_mclk_in_mux[] = {
-	FSICCK_MARK,
-};
-static const unsigned int fsic_mclk_out_pins[] = {
-	/* OMC */
-	54,
-};
-static const unsigned int fsic_mclk_out_mux[] = {
-	FSICOMC_MARK,
-};
-static const unsigned int fsic_sclk_in_pins[] = {
-	/* ILR, IBT */
-	46, 45,
-};
-static const unsigned int fsic_sclk_in_mux[] = {
-	FSICILR_MARK, FSICIBT_MARK,
-};
-static const unsigned int fsic_sclk_out_pins[] = {
-	/* OLR, OBT */
-	46, 45,
-};
-static const unsigned int fsic_sclk_out_mux[] = {
-	FSICOLR_MARK, FSICOBT_MARK,
-};
-static const unsigned int fsic_data_in_pins[] = {
-	/* ISLD */
-	48,
-};
-static const unsigned int fsic_data_in_mux[] = {
-	FSICISLD_MARK,
-};
-static const unsigned int fsic_data_out_pins[] = {
-	/* OSLD, OSLDT1, OSLDT2, OSLDT3 */
-	47, 44, 42, 16,
-};
-static const unsigned int fsic_data_out_mux[] = {
-	FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK,
-};
-static const unsigned int fsic_spdif_0_pins[] = {
-	/* SPDIF */
-	53,
-};
-static const unsigned int fsic_spdif_0_mux[] = {
-	PORT53_FSICSPDIF_MARK,
-};
-static const unsigned int fsic_spdif_1_pins[] = {
-	/* SPDIF */
-	47,
-};
-static const unsigned int fsic_spdif_1_mux[] = {
-	PORT47_FSICSPDIF_MARK,
-};
-/* - FSID ------------------------------------------------------------------- */
-static const unsigned int fsid_sclk_in_pins[] = {
-	/* ILR, IBT */
-	46, 45,
-};
-static const unsigned int fsid_sclk_in_mux[] = {
-	FSIDILR_MARK, FSIDIBT_MARK,
-};
-static const unsigned int fsid_sclk_out_pins[] = {
-	/* OLR, OBT */
-	46, 45,
-};
-static const unsigned int fsid_sclk_out_mux[] = {
-	FSIDOLR_MARK, FSIDOBT_MARK,
-};
-static const unsigned int fsid_data_in_pins[] = {
-	/* ISLD */
-	48,
-};
-static const unsigned int fsid_data_in_mux[] = {
-	FSIDISLD_MARK,
-};
-/* - I2C2 ------------------------------------------------------------------- */
-static const unsigned int i2c2_0_pins[] = {
-	/* SCL, SDA */
-	237, 236,
-};
-static const unsigned int i2c2_0_mux[] = {
-	PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK,
-};
-static const unsigned int i2c2_1_pins[] = {
-	/* SCL, SDA */
-	27, 28,
-};
-static const unsigned int i2c2_1_mux[] = {
-	PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK,
-};
-static const unsigned int i2c2_2_pins[] = {
-	/* SCL, SDA */
-	115, 116,
-};
-static const unsigned int i2c2_2_mux[] = {
-	PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK,
-};
-/* - I2C3 ------------------------------------------------------------------- */
-static const unsigned int i2c3_0_pins[] = {
-	/* SCL, SDA */
-	248, 249,
-};
-static const unsigned int i2c3_0_mux[] = {
-	PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK,
-};
-static const unsigned int i2c3_1_pins[] = {
-	/* SCL, SDA */
-	27, 28,
-};
-static const unsigned int i2c3_1_mux[] = {
-	PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK,
-};
-static const unsigned int i2c3_2_pins[] = {
-	/* SCL, SDA */
-	115, 116,
-};
-static const unsigned int i2c3_2_mux[] = {
-	PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK,
-};
-/* - IrDA ------------------------------------------------------------------- */
-static const unsigned int irda_0_pins[] = {
-	/* OUT, IN, FIRSEL */
-	241, 242, 243,
-};
-static const unsigned int irda_0_mux[] = {
-	PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK,
-};
-static const unsigned int irda_1_pins[] = {
-	/* OUT, IN, FIRSEL */
-	49, 53, 54,
-};
-static const unsigned int irda_1_mux[] = {
-	PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK,
-};
-/* - KEYSC ------------------------------------------------------------------ */
-static const unsigned int keysc_in5_pins[] = {
-	/* KEYIN[0:4] */
-	66, 67, 68, 69, 70,
-};
-static const unsigned int keysc_in5_mux[] = {
-	KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
-	KEYIN4_MARK,
-};
-static const unsigned int keysc_in6_pins[] = {
-	/* KEYIN[0:5] */
-	66, 67, 68, 69, 70, 71,
-};
-static const unsigned int keysc_in6_mux[] = {
-	KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
-	KEYIN4_MARK, KEYIN5_MARK,
-};
-static const unsigned int keysc_in7_pins[] = {
-	/* KEYIN[0:6] */
-	66, 67, 68, 69, 70, 71, 72,
-};
-static const unsigned int keysc_in7_mux[] = {
-	KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
-	KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK,
-};
-static const unsigned int keysc_in8_pins[] = {
-	/* KEYIN[0:7] */
-	66, 67, 68, 69, 70, 71, 72, 73,
-};
-static const unsigned int keysc_in8_mux[] = {
-	KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
-	KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
-};
-static const unsigned int keysc_out04_pins[] = {
-	/* KEYOUT[0:4] */
-	65, 64, 63, 62, 61,
-};
-static const unsigned int keysc_out04_mux[] = {
-	KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK,
-};
-static const unsigned int keysc_out5_pins[] = {
-	/* KEYOUT5 */
-	60,
-};
-static const unsigned int keysc_out5_mux[] = {
-	KEYOUT5_MARK,
-};
-static const unsigned int keysc_out6_0_pins[] = {
-	/* KEYOUT6 */
-	59,
-};
-static const unsigned int keysc_out6_0_mux[] = {
-	PORT59_KEYOUT6_MARK,
-};
-static const unsigned int keysc_out6_1_pins[] = {
-	/* KEYOUT6 */
-	131,
-};
-static const unsigned int keysc_out6_1_mux[] = {
-	PORT131_KEYOUT6_MARK,
-};
-static const unsigned int keysc_out6_2_pins[] = {
-	/* KEYOUT6 */
-	143,
-};
-static const unsigned int keysc_out6_2_mux[] = {
-	PORT143_KEYOUT6_MARK,
-};
-static const unsigned int keysc_out7_0_pins[] = {
-	/* KEYOUT7 */
-	58,
-};
-static const unsigned int keysc_out7_0_mux[] = {
-	PORT58_KEYOUT7_MARK,
-};
-static const unsigned int keysc_out7_1_pins[] = {
-	/* KEYOUT7 */
-	132,
-};
-static const unsigned int keysc_out7_1_mux[] = {
-	PORT132_KEYOUT7_MARK,
-};
-static const unsigned int keysc_out7_2_pins[] = {
-	/* KEYOUT7 */
-	144,
-};
-static const unsigned int keysc_out7_2_mux[] = {
-	PORT144_KEYOUT7_MARK,
-};
-static const unsigned int keysc_out8_0_pins[] = {
-	/* KEYOUT8 */
-	PIN_A11,
-};
-static const unsigned int keysc_out8_0_mux[] = {
-	KEYOUT8_MARK,
-};
-static const unsigned int keysc_out8_1_pins[] = {
-	/* KEYOUT8 */
-	136,
-};
-static const unsigned int keysc_out8_1_mux[] = {
-	PORT136_KEYOUT8_MARK,
-};
-static const unsigned int keysc_out8_2_pins[] = {
-	/* KEYOUT8 */
-	138,
-};
-static const unsigned int keysc_out8_2_mux[] = {
-	PORT138_KEYOUT8_MARK,
-};
-static const unsigned int keysc_out9_0_pins[] = {
-	/* KEYOUT9 */
-	137,
-};
-static const unsigned int keysc_out9_0_mux[] = {
-	PORT137_KEYOUT9_MARK,
-};
-static const unsigned int keysc_out9_1_pins[] = {
-	/* KEYOUT9 */
-	139,
-};
-static const unsigned int keysc_out9_1_mux[] = {
-	PORT139_KEYOUT9_MARK,
-};
-static const unsigned int keysc_out9_2_pins[] = {
-	/* KEYOUT9 */
-	149,
-};
-static const unsigned int keysc_out9_2_mux[] = {
-	PORT149_KEYOUT9_MARK,
-};
-static const unsigned int keysc_out10_0_pins[] = {
-	/* KEYOUT10 */
-	132,
-};
-static const unsigned int keysc_out10_0_mux[] = {
-	PORT132_KEYOUT10_MARK,
-};
-static const unsigned int keysc_out10_1_pins[] = {
-	/* KEYOUT10 */
-	142,
-};
-static const unsigned int keysc_out10_1_mux[] = {
-	PORT142_KEYOUT10_MARK,
-};
-static const unsigned int keysc_out11_0_pins[] = {
-	/* KEYOUT11 */
-	131,
-};
-static const unsigned int keysc_out11_0_mux[] = {
-	PORT131_KEYOUT11_MARK,
-};
-static const unsigned int keysc_out11_1_pins[] = {
-	/* KEYOUT11 */
-	143,
-};
-static const unsigned int keysc_out11_1_mux[] = {
-	PORT143_KEYOUT11_MARK,
-};
-/* - LCD -------------------------------------------------------------------- */
-static const unsigned int lcd_data8_pins[] = {
-	/* D[0:7] */
-	192, 193, 194, 195, 196, 197, 198, 199,
-};
-static const unsigned int lcd_data8_mux[] = {
-	LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
-	LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
-};
-static const unsigned int lcd_data9_pins[] = {
-	/* D[0:8] */
-	192, 193, 194, 195, 196, 197, 198, 199,
-	200,
-};
-static const unsigned int lcd_data9_mux[] = {
-	LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
-	LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
-	LCDD8_MARK,
-};
-static const unsigned int lcd_data12_pins[] = {
-	/* D[0:11] */
-	192, 193, 194, 195, 196, 197, 198, 199,
-	200, 201, 202, 203,
-};
-static const unsigned int lcd_data12_mux[] = {
-	LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
-	LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
-	LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
-};
-static const unsigned int lcd_data16_pins[] = {
-	/* D[0:15] */
-	192, 193, 194, 195, 196, 197, 198, 199,
-	200, 201, 202, 203, 204, 205, 206, 207,
-};
-static const unsigned int lcd_data16_mux[] = {
-	LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
-	LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
-	LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
-	LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
-};
-static const unsigned int lcd_data18_pins[] = {
-	/* D[0:17] */
-	192, 193, 194, 195, 196, 197, 198, 199,
-	200, 201, 202, 203, 204, 205, 206, 207,
-	208, 209,
-};
-static const unsigned int lcd_data18_mux[] = {
-	LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
-	LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
-	LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
-	LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
-	LCDD16_MARK, LCDD17_MARK,
-};
-static const unsigned int lcd_data24_pins[] = {
-	/* D[0:23] */
-	192, 193, 194, 195, 196, 197, 198, 199,
-	200, 201, 202, 203, 204, 205, 206, 207,
-	208, 209, 210, 211, 212, 213, 214, 215
-};
-static const unsigned int lcd_data24_mux[] = {
-	LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
-	LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
-	LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
-	LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
-	LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
-	LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
-};
-static const unsigned int lcd_display_pins[] = {
-	/* DON */
-	222,
-};
-static const unsigned int lcd_display_mux[] = {
-	LCDDON_MARK,
-};
-static const unsigned int lcd_lclk_pins[] = {
-	/* LCLK */
-	221,
-};
-static const unsigned int lcd_lclk_mux[] = {
-	LCDLCLK_MARK,
-};
-static const unsigned int lcd_sync_pins[] = {
-	/* VSYN, HSYN, DCK, DISP */
-	220, 218, 216, 219,
-};
-static const unsigned int lcd_sync_mux[] = {
-	LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
-};
-static const unsigned int lcd_sys_pins[] = {
-	/* CS, WR, RD, RS */
-	218, 216, 217, 219,
-};
-static const unsigned int lcd_sys_mux[] = {
-	LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK,
-};
-/* - LCD2 ------------------------------------------------------------------- */
-static const unsigned int lcd2_data8_pins[] = {
-	/* D[0:7] */
-	128, 129, 142, 143, 144, 145, 138, 139,
-};
-static const unsigned int lcd2_data8_mux[] = {
-	LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
-	LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
-};
-static const unsigned int lcd2_data9_pins[] = {
-	/* D[0:8] */
-	128, 129, 142, 143, 144, 145, 138, 139,
-	140,
-};
-static const unsigned int lcd2_data9_mux[] = {
-	LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
-	LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
-	LCD2D8_MARK,
-};
-static const unsigned int lcd2_data12_pins[] = {
-	/* D[0:11] */
-	128, 129, 142, 143, 144, 145, 138, 139,
-	140, 141, 130, 131,
-};
-static const unsigned int lcd2_data12_mux[] = {
-	LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
-	LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
-	LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
-};
-static const unsigned int lcd2_data16_pins[] = {
-	/* D[0:15] */
-	128, 129, 142, 143, 144, 145, 138, 139,
-	140, 141, 130, 131, 132, 133, 134, 135,
-};
-static const unsigned int lcd2_data16_mux[] = {
-	LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
-	LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
-	LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
-	LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
-};
-static const unsigned int lcd2_data18_pins[] = {
-	/* D[0:17] */
-	128, 129, 142, 143, 144, 145, 138, 139,
-	140, 141, 130, 131, 132, 133, 134, 135,
-	136, 137,
-};
-static const unsigned int lcd2_data18_mux[] = {
-	LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
-	LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
-	LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
-	LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
-	LCD2D16_MARK, LCD2D17_MARK,
-};
-static const unsigned int lcd2_data24_pins[] = {
-	/* D[0:23] */
-	128, 129, 142, 143, 144, 145, 138, 139,
-	140, 141, 130, 131, 132, 133, 134, 135,
-	136, 137, 146, 147, 234, 235, 238, 239
-};
-static const unsigned int lcd2_data24_mux[] = {
-	LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
-	LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
-	LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
-	LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
-	LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK,
-	LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK,
-};
-static const unsigned int lcd2_sync_0_pins[] = {
-	/* VSYN, HSYN, DCK, DISP */
-	128, 129, 146, 145,
-};
-static const unsigned int lcd2_sync_0_mux[] = {
-	PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK,
-	LCD2DCK_MARK, PORT145_LCD2DISP_MARK,
-};
-static const unsigned int lcd2_sync_1_pins[] = {
-	/* VSYN, HSYN, DCK, DISP */
-	222, 221, 219, 217,
-};
-static const unsigned int lcd2_sync_1_mux[] = {
-	PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK,
-	LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK,
-};
-static const unsigned int lcd2_sys_0_pins[] = {
-	/* CS, WR, RD, RS */
-	129, 146, 147, 145,
-};
-static const unsigned int lcd2_sys_0_mux[] = {
-	PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK,
-	LCD2RD__MARK, PORT145_LCD2RS_MARK,
-};
-static const unsigned int lcd2_sys_1_pins[] = {
-	/* CS, WR, RD, RS */
-	221, 219, 147, 217,
-};
-static const unsigned int lcd2_sys_1_mux[] = {
-	PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK,
-	LCD2RD__MARK, PORT217_LCD2RS_MARK,
-};
-/* - MMCIF ------------------------------------------------------------------ */
-static const unsigned int mmc0_data1_0_pins[] = {
-	/* D[0] */
-	271,
-};
-static const unsigned int mmc0_data1_0_mux[] = {
-	MMCD0_0_MARK,
-};
-static const unsigned int mmc0_data4_0_pins[] = {
-	/* D[0:3] */
-	271, 272, 273, 274,
-};
-static const unsigned int mmc0_data4_0_mux[] = {
-	MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
-};
-static const unsigned int mmc0_data8_0_pins[] = {
-	/* D[0:7] */
-	271, 272, 273, 274, 275, 276, 277, 278,
-};
-static const unsigned int mmc0_data8_0_mux[] = {
-	MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
-	MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
-};
-static const unsigned int mmc0_ctrl_0_pins[] = {
-	/* CMD, CLK */
-	279, 270,
-};
-static const unsigned int mmc0_ctrl_0_mux[] = {
-	MMCCMD0_MARK, MMCCLK0_MARK,
-};
-
-static const unsigned int mmc0_data1_1_pins[] = {
-	/* D[0] */
-	305,
-};
-static const unsigned int mmc0_data1_1_mux[] = {
-	MMCD1_0_MARK,
-};
-static const unsigned int mmc0_data4_1_pins[] = {
-	/* D[0:3] */
-	305, 304, 303, 302,
-};
-static const unsigned int mmc0_data4_1_mux[] = {
-	MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
-};
-static const unsigned int mmc0_data8_1_pins[] = {
-	/* D[0:7] */
-	305, 304, 303, 302, 301, 300, 299, 298,
-};
-static const unsigned int mmc0_data8_1_mux[] = {
-	MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
-	MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
-};
-static const unsigned int mmc0_ctrl_1_pins[] = {
-	/* CMD, CLK */
-	297, 289,
-};
-static const unsigned int mmc0_ctrl_1_mux[] = {
-	MMCCMD1_MARK, MMCCLK1_MARK,
-};
-/* - MSIOF0 ----------------------------------------------------------------- */
-static const unsigned int msiof0_rsck_pins[] = {
-	/* RSCK */
-	66,
-};
-static const unsigned int msiof0_rsck_mux[] = {
-	MSIOF0_RSCK_MARK,
-};
-static const unsigned int msiof0_tsck_pins[] = {
-	/* TSCK */
-	64,
-};
-static const unsigned int msiof0_tsck_mux[] = {
-	MSIOF0_TSCK_MARK,
-};
-static const unsigned int msiof0_rsync_pins[] = {
-	/* RSYNC */
-	67,
-};
-static const unsigned int msiof0_rsync_mux[] = {
-	MSIOF0_RSYNC_MARK,
-};
-static const unsigned int msiof0_tsync_pins[] = {
-	/* TSYNC */
-	63,
-};
-static const unsigned int msiof0_tsync_mux[] = {
-	MSIOF0_TSYNC_MARK,
-};
-static const unsigned int msiof0_ss1_pins[] = {
-	/* SS1 */
-	62,
-};
-static const unsigned int msiof0_ss1_mux[] = {
-	MSIOF0_SS1_MARK,
-};
-static const unsigned int msiof0_ss2_pins[] = {
-	/* SS2 */
-	71,
-};
-static const unsigned int msiof0_ss2_mux[] = {
-	MSIOF0_SS2_MARK,
-};
-static const unsigned int msiof0_rxd_pins[] = {
-	/* RXD */
-	70,
-};
-static const unsigned int msiof0_rxd_mux[] = {
-	MSIOF0_RXD_MARK,
-};
-static const unsigned int msiof0_txd_pins[] = {
-	/* TXD */
-	65,
-};
-static const unsigned int msiof0_txd_mux[] = {
-	MSIOF0_TXD_MARK,
-};
-static const unsigned int msiof0_mck0_pins[] = {
-	/* MSCK0 */
-	68,
-};
-static const unsigned int msiof0_mck0_mux[] = {
-	MSIOF0_MCK0_MARK,
-};
-
-static const unsigned int msiof0_mck1_pins[] = {
-	/* MSCK1 */
-	69,
-};
-static const unsigned int msiof0_mck1_mux[] = {
-	MSIOF0_MCK1_MARK,
-};
-
-static const unsigned int msiof0l_rsck_pins[] = {
-	/* RSCK */
-	214,
-};
-static const unsigned int msiof0l_rsck_mux[] = {
-	MSIOF0L_RSCK_MARK,
-};
-static const unsigned int msiof0l_tsck_pins[] = {
-	/* TSCK */
-	219,
-};
-static const unsigned int msiof0l_tsck_mux[] = {
-	MSIOF0L_TSCK_MARK,
-};
-static const unsigned int msiof0l_rsync_pins[] = {
-	/* RSYNC */
-	215,
-};
-static const unsigned int msiof0l_rsync_mux[] = {
-	MSIOF0L_RSYNC_MARK,
-};
-static const unsigned int msiof0l_tsync_pins[] = {
-	/* TSYNC */
-	217,
-};
-static const unsigned int msiof0l_tsync_mux[] = {
-	MSIOF0L_TSYNC_MARK,
-};
-static const unsigned int msiof0l_ss1_a_pins[] = {
-	/* SS1 */
-	207,
-};
-static const unsigned int msiof0l_ss1_a_mux[] = {
-	PORT207_MSIOF0L_SS1_MARK,
-};
-static const unsigned int msiof0l_ss1_b_pins[] = {
-	/* SS1 */
-	210,
-};
-static const unsigned int msiof0l_ss1_b_mux[] = {
-	PORT210_MSIOF0L_SS1_MARK,
-};
-static const unsigned int msiof0l_ss2_a_pins[] = {
-	/* SS2 */
-	208,
-};
-static const unsigned int msiof0l_ss2_a_mux[] = {
-	PORT208_MSIOF0L_SS2_MARK,
-};
-static const unsigned int msiof0l_ss2_b_pins[] = {
-	/* SS2 */
-	211,
-};
-static const unsigned int msiof0l_ss2_b_mux[] = {
-	PORT211_MSIOF0L_SS2_MARK,
-};
-static const unsigned int msiof0l_rxd_pins[] = {
-	/* RXD */
-	221,
-};
-static const unsigned int msiof0l_rxd_mux[] = {
-	MSIOF0L_RXD_MARK,
-};
-static const unsigned int msiof0l_txd_pins[] = {
-	/* TXD */
-	222,
-};
-static const unsigned int msiof0l_txd_mux[] = {
-	MSIOF0L_TXD_MARK,
-};
-static const unsigned int msiof0l_mck0_pins[] = {
-	/* MSCK0 */
-	212,
-};
-static const unsigned int msiof0l_mck0_mux[] = {
-	MSIOF0L_MCK0_MARK,
-};
-static const unsigned int msiof0l_mck1_pins[] = {
-	/* MSCK1 */
-	213,
-};
-static const unsigned int msiof0l_mck1_mux[] = {
-	MSIOF0L_MCK1_MARK,
-};
-/* - MSIOF1 ----------------------------------------------------------------- */
-static const unsigned int msiof1_rsck_pins[] = {
-	/* RSCK */
-	234,
-};
-static const unsigned int msiof1_rsck_mux[] = {
-	MSIOF1_RSCK_MARK,
-};
-static const unsigned int msiof1_tsck_pins[] = {
-	/* TSCK */
-	232,
-};
-static const unsigned int msiof1_tsck_mux[] = {
-	MSIOF1_TSCK_MARK,
-};
-static const unsigned int msiof1_rsync_pins[] = {
-	/* RSYNC */
-	235,
-};
-static const unsigned int msiof1_rsync_mux[] = {
-	MSIOF1_RSYNC_MARK,
-};
-static const unsigned int msiof1_tsync_pins[] = {
-	/* TSYNC */
-	231,
-};
-static const unsigned int msiof1_tsync_mux[] = {
-	MSIOF1_TSYNC_MARK,
-};
-static const unsigned int msiof1_ss1_pins[] = {
-	/* SS1 */
-	238,
-};
-static const unsigned int msiof1_ss1_mux[] = {
-	MSIOF1_SS1_MARK,
-};
-static const unsigned int msiof1_ss2_pins[] = {
-	/* SS2 */
-	239,
-};
-static const unsigned int msiof1_ss2_mux[] = {
-	MSIOF1_SS2_MARK,
-};
-static const unsigned int msiof1_rxd_pins[] = {
-	/* RXD */
-	233,
-};
-static const unsigned int msiof1_rxd_mux[] = {
-	MSIOF1_RXD_MARK,
-};
-static const unsigned int msiof1_txd_pins[] = {
-	/* TXD */
-	230,
-};
-static const unsigned int msiof1_txd_mux[] = {
-	MSIOF1_TXD_MARK,
-};
-static const unsigned int msiof1_mck0_pins[] = {
-	/* MSCK0 */
-	236,
-};
-static const unsigned int msiof1_mck0_mux[] = {
-	MSIOF1_MCK0_MARK,
-};
-static const unsigned int msiof1_mck1_pins[] = {
-	/* MSCK1 */
-	237,
-};
-static const unsigned int msiof1_mck1_mux[] = {
-	MSIOF1_MCK1_MARK,
-};
-/* - MSIOF2 ----------------------------------------------------------------- */
-static const unsigned int msiof2_rsck_pins[] = {
-	/* RSCK */
-	151,
-};
-static const unsigned int msiof2_rsck_mux[] = {
-	MSIOF2_RSCK_MARK,
-};
-static const unsigned int msiof2_tsck_pins[] = {
-	/* TSCK */
-	135,
-};
-static const unsigned int msiof2_tsck_mux[] = {
-	MSIOF2_TSCK_MARK,
-};
-static const unsigned int msiof2_rsync_pins[] = {
-	/* RSYNC */
-	152,
-};
-static const unsigned int msiof2_rsync_mux[] = {
-	MSIOF2_RSYNC_MARK,
-};
-static const unsigned int msiof2_tsync_pins[] = {
-	/* TSYNC */
-	133,
-};
-static const unsigned int msiof2_tsync_mux[] = {
-	MSIOF2_TSYNC_MARK,
-};
-static const unsigned int msiof2_ss1_a_pins[] = {
-	/* SS1 */
-	131,
-};
-static const unsigned int msiof2_ss1_a_mux[] = {
-	PORT131_MSIOF2_SS1_MARK,
-};
-static const unsigned int msiof2_ss1_b_pins[] = {
-	/* SS1 */
-	153,
-};
-static const unsigned int msiof2_ss1_b_mux[] = {
-	PORT153_MSIOF2_SS1_MARK,
-};
-static const unsigned int msiof2_ss2_a_pins[] = {
-	/* SS2 */
-	132,
-};
-static const unsigned int msiof2_ss2_a_mux[] = {
-	PORT132_MSIOF2_SS2_MARK,
-};
-static const unsigned int msiof2_ss2_b_pins[] = {
-	/* SS2 */
-	156,
-};
-static const unsigned int msiof2_ss2_b_mux[] = {
-	PORT156_MSIOF2_SS2_MARK,
-};
-static const unsigned int msiof2_rxd_a_pins[] = {
-	/* RXD */
-	130,
-};
-static const unsigned int msiof2_rxd_a_mux[] = {
-	PORT130_MSIOF2_RXD_MARK,
-};
-static const unsigned int msiof2_rxd_b_pins[] = {
-	/* RXD */
-	157,
-};
-static const unsigned int msiof2_rxd_b_mux[] = {
-	PORT157_MSIOF2_RXD_MARK,
-};
-static const unsigned int msiof2_txd_pins[] = {
-	/* TXD */
-	134,
-};
-static const unsigned int msiof2_txd_mux[] = {
-	MSIOF2_TXD_MARK,
-};
-static const unsigned int msiof2_mck0_pins[] = {
-	/* MSCK0 */
-	154,
-};
-static const unsigned int msiof2_mck0_mux[] = {
-	MSIOF2_MCK0_MARK,
-};
-static const unsigned int msiof2_mck1_pins[] = {
-	/* MSCK1 */
-	155,
-};
-static const unsigned int msiof2_mck1_mux[] = {
-	MSIOF2_MCK1_MARK,
-};
-
-static const unsigned int msiof2r_tsck_pins[] = {
-	/* TSCK */
-	248,
-};
-static const unsigned int msiof2r_tsck_mux[] = {
-	MSIOF2R_TSCK_MARK,
-};
-static const unsigned int msiof2r_tsync_pins[] = {
-	/* TSYNC */
-	249,
-};
-static const unsigned int msiof2r_tsync_mux[] = {
-	MSIOF2R_TSYNC_MARK,
-};
-static const unsigned int msiof2r_rxd_pins[] = {
-	/* RXD */
-	244,
-};
-static const unsigned int msiof2r_rxd_mux[] = {
-	MSIOF2R_RXD_MARK,
-};
-static const unsigned int msiof2r_txd_pins[] = {
-	/* TXD */
-	245,
-};
-static const unsigned int msiof2r_txd_mux[] = {
-	MSIOF2R_TXD_MARK,
-};
-/* - MSIOF3 (Pin function name of MSIOF3 is named BBIF1) -------------------- */
-static const unsigned int msiof3_rsck_pins[] = {
-	/* RSCK */
-	115,
-};
-static const unsigned int msiof3_rsck_mux[] = {
-	BBIF1_RSCK_MARK,
-};
-static const unsigned int msiof3_tsck_pins[] = {
-	/* TSCK */
-	112,
-};
-static const unsigned int msiof3_tsck_mux[] = {
-	BBIF1_TSCK_MARK,
-};
-static const unsigned int msiof3_rsync_pins[] = {
-	/* RSYNC */
-	116,
-};
-static const unsigned int msiof3_rsync_mux[] = {
-	BBIF1_RSYNC_MARK,
-};
-static const unsigned int msiof3_tsync_pins[] = {
-	/* TSYNC */
-	113,
-};
-static const unsigned int msiof3_tsync_mux[] = {
-	BBIF1_TSYNC_MARK,
-};
-static const unsigned int msiof3_ss1_pins[] = {
-	/* SS1 */
-	117,
-};
-static const unsigned int msiof3_ss1_mux[] = {
-	BBIF1_SS1_MARK,
-};
-static const unsigned int msiof3_ss2_pins[] = {
-	/* SS2 */
-	109,
-};
-static const unsigned int msiof3_ss2_mux[] = {
-	BBIF1_SS2_MARK,
-};
-static const unsigned int msiof3_rxd_pins[] = {
-	/* RXD */
-	111,
-};
-static const unsigned int msiof3_rxd_mux[] = {
-	BBIF1_RXD_MARK,
-};
-static const unsigned int msiof3_txd_pins[] = {
-	/* TXD */
-	114,
-};
-static const unsigned int msiof3_txd_mux[] = {
-	BBIF1_TXD_MARK,
-};
-static const unsigned int msiof3_flow_pins[] = {
-	/* FLOW */
-	117,
-};
-static const unsigned int msiof3_flow_mux[] = {
-	BBIF1_FLOW_MARK,
-};
-
-/* - SCIFA0 ----------------------------------------------------------------- */
-static const unsigned int scifa0_data_pins[] = {
-	/* RXD, TXD */
-	43, 17,
-};
-static const unsigned int scifa0_data_mux[] = {
-	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
-};
-static const unsigned int scifa0_clk_pins[] = {
-	/* SCK */
-	16,
-};
-static const unsigned int scifa0_clk_mux[] = {
-	SCIFA0_SCK_MARK,
-};
-static const unsigned int scifa0_ctrl_pins[] = {
-	/* RTS, CTS */
-	42, 44,
-};
-static const unsigned int scifa0_ctrl_mux[] = {
-	SCIFA0_RTS__MARK, SCIFA0_CTS__MARK,
-};
-/* - SCIFA1 ----------------------------------------------------------------- */
-static const unsigned int scifa1_data_pins[] = {
-	/* RXD, TXD */
-	228, 225,
-};
-static const unsigned int scifa1_data_mux[] = {
-	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
-};
-static const unsigned int scifa1_clk_pins[] = {
-	/* SCK */
-	226,
-};
-static const unsigned int scifa1_clk_mux[] = {
-	SCIFA1_SCK_MARK,
-};
-static const unsigned int scifa1_ctrl_pins[] = {
-	/* RTS, CTS */
-	227, 229,
-};
-static const unsigned int scifa1_ctrl_mux[] = {
-	SCIFA1_RTS__MARK, SCIFA1_CTS__MARK,
-};
-/* - SCIFA2 ----------------------------------------------------------------- */
-static const unsigned int scifa2_data_0_pins[] = {
-	/* RXD, TXD */
-	155, 154,
-};
-static const unsigned int scifa2_data_0_mux[] = {
-	SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
-};
-static const unsigned int scifa2_clk_0_pins[] = {
-	/* SCK */
-	158,
-};
-static const unsigned int scifa2_clk_0_mux[] = {
-	SCIFA2_SCK1_MARK,
-};
-static const unsigned int scifa2_ctrl_0_pins[] = {
-	/* RTS, CTS */
-	156, 157,
-};
-static const unsigned int scifa2_ctrl_0_mux[] = {
-	SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK,
-};
-static const unsigned int scifa2_data_1_pins[] = {
-	/* RXD, TXD */
-	233, 230,
-};
-static const unsigned int scifa2_data_1_mux[] = {
-	SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK,
-};
-static const unsigned int scifa2_clk_1_pins[] = {
-	/* SCK */
-	232,
-};
-static const unsigned int scifa2_clk_1_mux[] = {
-	SCIFA2_SCK2_MARK,
-};
-static const unsigned int scifa2_ctrl_1_pins[] = {
-	/* RTS, CTS */
-	234, 231,
-};
-static const unsigned int scifa2_ctrl_1_mux[] = {
-	SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK,
-};
-/* - SCIFA3 ----------------------------------------------------------------- */
-static const unsigned int scifa3_data_pins[] = {
-	/* RXD, TXD */
-	108, 110,
-};
-static const unsigned int scifa3_data_mux[] = {
-	SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
-};
-static const unsigned int scifa3_ctrl_pins[] = {
-	/* RTS, CTS */
-	109, 107,
-};
-static const unsigned int scifa3_ctrl_mux[] = {
-	SCIFA3_RTS__MARK, SCIFA3_CTS__MARK,
-};
-/* - SCIFA4 ----------------------------------------------------------------- */
-static const unsigned int scifa4_data_pins[] = {
-	/* RXD, TXD */
-	33, 32,
-};
-static const unsigned int scifa4_data_mux[] = {
-	SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
-};
-static const unsigned int scifa4_ctrl_pins[] = {
-	/* RTS, CTS */
-	34, 35,
-};
-static const unsigned int scifa4_ctrl_mux[] = {
-	SCIFA4_RTS__MARK, SCIFA4_CTS__MARK,
-};
-/* - SCIFA5 ----------------------------------------------------------------- */
-static const unsigned int scifa5_data_0_pins[] = {
-	/* RXD, TXD */
-	246, 247,
-};
-static const unsigned int scifa5_data_0_mux[] = {
-	PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK,
-};
-static const unsigned int scifa5_clk_0_pins[] = {
-	/* SCK */
-	248,
-};
-static const unsigned int scifa5_clk_0_mux[] = {
-	PORT248_SCIFA5_SCK_MARK,
-};
-static const unsigned int scifa5_ctrl_0_pins[] = {
-	/* RTS, CTS */
-	245, 244,
-};
-static const unsigned int scifa5_ctrl_0_mux[] = {
-	PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK,
-};
-static const unsigned int scifa5_data_1_pins[] = {
-	/* RXD, TXD */
-	195, 196,
-};
-static const unsigned int scifa5_data_1_mux[] = {
-	PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK,
-};
-static const unsigned int scifa5_clk_1_pins[] = {
-	/* SCK */
-	197,
-};
-static const unsigned int scifa5_clk_1_mux[] = {
-	PORT197_SCIFA5_SCK_MARK,
-};
-static const unsigned int scifa5_ctrl_1_pins[] = {
-	/* RTS, CTS */
-	194, 193,
-};
-static const unsigned int scifa5_ctrl_1_mux[] = {
-	PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK,
-};
-static const unsigned int scifa5_data_2_pins[] = {
-	/* RXD, TXD */
-	162, 160,
-};
-static const unsigned int scifa5_data_2_mux[] = {
-	PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK,
-};
-static const unsigned int scifa5_clk_2_pins[] = {
-	/* SCK */
-	159,
-};
-static const unsigned int scifa5_clk_2_mux[] = {
-	PORT159_SCIFA5_SCK_MARK,
-};
-static const unsigned int scifa5_ctrl_2_pins[] = {
-	/* RTS, CTS */
-	163, 161,
-};
-static const unsigned int scifa5_ctrl_2_mux[] = {
-	PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK,
-};
-/* - SCIFA6 ----------------------------------------------------------------- */
-static const unsigned int scifa6_pins[] = {
-	/* TXD */
-	240,
-};
-static const unsigned int scifa6_mux[] = {
-	SCIFA6_TXD_MARK,
-};
-/* - SCIFA7 ----------------------------------------------------------------- */
-static const unsigned int scifa7_data_pins[] = {
-	/* RXD, TXD */
-	12, 18,
-};
-static const unsigned int scifa7_data_mux[] = {
-	SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
-};
-static const unsigned int scifa7_ctrl_pins[] = {
-	/* RTS, CTS */
-	19, 13,
-};
-static const unsigned int scifa7_ctrl_mux[] = {
-	SCIFA7_RTS__MARK, SCIFA7_CTS__MARK,
-};
-/* - SCIFB ------------------------------------------------------------------ */
-static const unsigned int scifb_data_0_pins[] = {
-	/* RXD, TXD */
-	162, 160,
-};
-static const unsigned int scifb_data_0_mux[] = {
-	PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK,
-};
-static const unsigned int scifb_clk_0_pins[] = {
-	/* SCK */
-	159,
-};
-static const unsigned int scifb_clk_0_mux[] = {
-	PORT159_SCIFB_SCK_MARK,
-};
-static const unsigned int scifb_ctrl_0_pins[] = {
-	/* RTS, CTS */
-	163, 161,
-};
-static const unsigned int scifb_ctrl_0_mux[] = {
-	PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK,
-};
-static const unsigned int scifb_data_1_pins[] = {
-	/* RXD, TXD */
-	246, 247,
-};
-static const unsigned int scifb_data_1_mux[] = {
-	PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK,
-};
-static const unsigned int scifb_clk_1_pins[] = {
-	/* SCK */
-	248,
-};
-static const unsigned int scifb_clk_1_mux[] = {
-	PORT248_SCIFB_SCK_MARK,
-};
-static const unsigned int scifb_ctrl_1_pins[] = {
-	/* RTS, CTS */
-	245, 244,
-};
-static const unsigned int scifb_ctrl_1_mux[] = {
-	PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK,
-};
-/* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
-	/* D0 */
-	252,
-};
-static const unsigned int sdhi0_data1_mux[] = {
-	SDHID0_0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
-	/* D[0:3] */
-	252, 253, 254, 255,
-};
-static const unsigned int sdhi0_data4_mux[] = {
-	SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
-};
-static const unsigned int sdhi0_ctrl_pins[] = {
-	/* CMD, CLK */
-	256, 250,
-};
-static const unsigned int sdhi0_ctrl_mux[] = {
-	SDHICMD0_MARK, SDHICLK0_MARK,
-};
-static const unsigned int sdhi0_cd_pins[] = {
-	/* CD */
-	251,
-};
-static const unsigned int sdhi0_cd_mux[] = {
-	SDHICD0_MARK,
-};
-static const unsigned int sdhi0_wp_pins[] = {
-	/* WP */
-	257,
-};
-static const unsigned int sdhi0_wp_mux[] = {
-	SDHIWP0_MARK,
-};
-/* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
-	/* D0 */
-	259,
-};
-static const unsigned int sdhi1_data1_mux[] = {
-	SDHID1_0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
-	/* D[0:3] */
-	259, 260, 261, 262,
-};
-static const unsigned int sdhi1_data4_mux[] = {
-	SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
-};
-static const unsigned int sdhi1_ctrl_pins[] = {
-	/* CMD, CLK */
-	263, 258,
-};
-static const unsigned int sdhi1_ctrl_mux[] = {
-	SDHICMD1_MARK, SDHICLK1_MARK,
-};
-/* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
-	/* D0 */
-	265,
-};
-static const unsigned int sdhi2_data1_mux[] = {
-	SDHID2_0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
-	/* D[0:3] */
-	265, 266, 267, 268,
-};
-static const unsigned int sdhi2_data4_mux[] = {
-	SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
-};
-static const unsigned int sdhi2_ctrl_pins[] = {
-	/* CMD, CLK */
-	269, 264,
-};
-static const unsigned int sdhi2_ctrl_mux[] = {
-	SDHICMD2_MARK, SDHICLK2_MARK,
-};
-/* - TPU0 ------------------------------------------------------------------- */
-static const unsigned int tpu0_to0_pins[] = {
-	/* TO */
-	55,
-};
-static const unsigned int tpu0_to0_mux[] = {
-	TPU0TO0_MARK,
-};
-static const unsigned int tpu0_to1_pins[] = {
-	/* TO */
-	59,
-};
-static const unsigned int tpu0_to1_mux[] = {
-	TPU0TO1_MARK,
-};
-static const unsigned int tpu0_to2_pins[] = {
-	/* TO */
-	140,
-};
-static const unsigned int tpu0_to2_mux[] = {
-	TPU0TO2_MARK,
-};
-static const unsigned int tpu0_to3_pins[] = {
-	/* TO */
-	141,
-};
-static const unsigned int tpu0_to3_mux[] = {
-	TPU0TO3_MARK,
-};
-/* - TPU1 ------------------------------------------------------------------- */
-static const unsigned int tpu1_to0_pins[] = {
-	/* TO */
-	246,
-};
-static const unsigned int tpu1_to0_mux[] = {
-	TPU1TO0_MARK,
-};
-static const unsigned int tpu1_to1_0_pins[] = {
-	/* TO */
-	28,
-};
-static const unsigned int tpu1_to1_0_mux[] = {
-	PORT28_TPU1TO1_MARK,
-};
-static const unsigned int tpu1_to1_1_pins[] = {
-	/* TO */
-	29,
-};
-static const unsigned int tpu1_to1_1_mux[] = {
-	PORT29_TPU1TO1_MARK,
-};
-static const unsigned int tpu1_to2_pins[] = {
-	/* TO */
-	153,
-};
-static const unsigned int tpu1_to2_mux[] = {
-	TPU1TO2_MARK,
-};
-static const unsigned int tpu1_to3_pins[] = {
-	/* TO */
-	145,
-};
-static const unsigned int tpu1_to3_mux[] = {
-	TPU1TO3_MARK,
-};
-/* - TPU2 ------------------------------------------------------------------- */
-static const unsigned int tpu2_to0_pins[] = {
-	/* TO */
-	248,
-};
-static const unsigned int tpu2_to0_mux[] = {
-	TPU2TO0_MARK,
-};
-static const unsigned int tpu2_to1_pins[] = {
-	/* TO */
-	197,
-};
-static const unsigned int tpu2_to1_mux[] = {
-	TPU2TO1_MARK,
-};
-static const unsigned int tpu2_to2_pins[] = {
-	/* TO */
-	50,
-};
-static const unsigned int tpu2_to2_mux[] = {
-	TPU2TO2_MARK,
-};
-static const unsigned int tpu2_to3_pins[] = {
-	/* TO */
-	51,
-};
-static const unsigned int tpu2_to3_mux[] = {
-	TPU2TO3_MARK,
-};
-/* - TPU3 ------------------------------------------------------------------- */
-static const unsigned int tpu3_to0_pins[] = {
-	/* TO */
-	163,
-};
-static const unsigned int tpu3_to0_mux[] = {
-	TPU3TO0_MARK,
-};
-static const unsigned int tpu3_to1_pins[] = {
-	/* TO */
-	247,
-};
-static const unsigned int tpu3_to1_mux[] = {
-	TPU3TO1_MARK,
-};
-static const unsigned int tpu3_to2_pins[] = {
-	/* TO */
-	54,
-};
-static const unsigned int tpu3_to2_mux[] = {
-	TPU3TO2_MARK,
-};
-static const unsigned int tpu3_to3_pins[] = {
-	/* TO */
-	53,
-};
-static const unsigned int tpu3_to3_mux[] = {
-	TPU3TO3_MARK,
-};
-/* - TPU4 ------------------------------------------------------------------- */
-static const unsigned int tpu4_to0_pins[] = {
-	/* TO */
-	241,
-};
-static const unsigned int tpu4_to0_mux[] = {
-	TPU4TO0_MARK,
-};
-static const unsigned int tpu4_to1_pins[] = {
-	/* TO */
-	199,
-};
-static const unsigned int tpu4_to1_mux[] = {
-	TPU4TO1_MARK,
-};
-static const unsigned int tpu4_to2_pins[] = {
-	/* TO */
-	58,
-};
-static const unsigned int tpu4_to2_mux[] = {
-	TPU4TO2_MARK,
-};
-static const unsigned int tpu4_to3_pins[] = {
-	/* TO */
-	PIN_A11,
-};
-static const unsigned int tpu4_to3_mux[] = {
-	TPU4TO3_MARK,
-};
-/* - USB -------------------------------------------------------------------- */
-static const unsigned int usb_vbus_pins[] = {
-	/* VBUS */
-	0,
-};
-static const unsigned int usb_vbus_mux[] = {
-	VBUS_0_MARK,
-};
-
-static const struct sh_pfc_pin_group pinmux_groups[] = {
-	SH_PFC_PIN_GROUP(bsc_data_0_7),
-	SH_PFC_PIN_GROUP(bsc_data_8_15),
-	SH_PFC_PIN_GROUP(bsc_cs4),
-	SH_PFC_PIN_GROUP(bsc_cs5_a),
-	SH_PFC_PIN_GROUP(bsc_cs5_b),
-	SH_PFC_PIN_GROUP(bsc_cs6_a),
-	SH_PFC_PIN_GROUP(bsc_cs6_b),
-	SH_PFC_PIN_GROUP(bsc_rd),
-	SH_PFC_PIN_GROUP(bsc_rdwr_0),
-	SH_PFC_PIN_GROUP(bsc_rdwr_1),
-	SH_PFC_PIN_GROUP(bsc_rdwr_2),
-	SH_PFC_PIN_GROUP(bsc_we0),
-	SH_PFC_PIN_GROUP(bsc_we1),
-	SH_PFC_PIN_GROUP(fsia_mclk_in),
-	SH_PFC_PIN_GROUP(fsia_mclk_out),
-	SH_PFC_PIN_GROUP(fsia_sclk_in),
-	SH_PFC_PIN_GROUP(fsia_sclk_out),
-	SH_PFC_PIN_GROUP(fsia_data_in),
-	SH_PFC_PIN_GROUP(fsia_data_out),
-	SH_PFC_PIN_GROUP(fsia_spdif),
-	SH_PFC_PIN_GROUP(fsib_mclk_in),
-	SH_PFC_PIN_GROUP(fsib_mclk_out),
-	SH_PFC_PIN_GROUP(fsib_sclk_in),
-	SH_PFC_PIN_GROUP(fsib_sclk_out),
-	SH_PFC_PIN_GROUP(fsib_data_in),
-	SH_PFC_PIN_GROUP(fsib_data_out),
-	SH_PFC_PIN_GROUP(fsib_spdif),
-	SH_PFC_PIN_GROUP(fsic_mclk_in),
-	SH_PFC_PIN_GROUP(fsic_mclk_out),
-	SH_PFC_PIN_GROUP(fsic_sclk_in),
-	SH_PFC_PIN_GROUP(fsic_sclk_out),
-	SH_PFC_PIN_GROUP(fsic_data_in),
-	SH_PFC_PIN_GROUP(fsic_data_out),
-	SH_PFC_PIN_GROUP(fsic_spdif_0),
-	SH_PFC_PIN_GROUP(fsic_spdif_1),
-	SH_PFC_PIN_GROUP(fsid_sclk_in),
-	SH_PFC_PIN_GROUP(fsid_sclk_out),
-	SH_PFC_PIN_GROUP(fsid_data_in),
-	SH_PFC_PIN_GROUP(i2c2_0),
-	SH_PFC_PIN_GROUP(i2c2_1),
-	SH_PFC_PIN_GROUP(i2c2_2),
-	SH_PFC_PIN_GROUP(i2c3_0),
-	SH_PFC_PIN_GROUP(i2c3_1),
-	SH_PFC_PIN_GROUP(i2c3_2),
-	SH_PFC_PIN_GROUP(irda_0),
-	SH_PFC_PIN_GROUP(irda_1),
-	SH_PFC_PIN_GROUP(keysc_in5),
-	SH_PFC_PIN_GROUP(keysc_in6),
-	SH_PFC_PIN_GROUP(keysc_in7),
-	SH_PFC_PIN_GROUP(keysc_in8),
-	SH_PFC_PIN_GROUP(keysc_out04),
-	SH_PFC_PIN_GROUP(keysc_out5),
-	SH_PFC_PIN_GROUP(keysc_out6_0),
-	SH_PFC_PIN_GROUP(keysc_out6_1),
-	SH_PFC_PIN_GROUP(keysc_out6_2),
-	SH_PFC_PIN_GROUP(keysc_out7_0),
-	SH_PFC_PIN_GROUP(keysc_out7_1),
-	SH_PFC_PIN_GROUP(keysc_out7_2),
-	SH_PFC_PIN_GROUP(keysc_out8_0),
-	SH_PFC_PIN_GROUP(keysc_out8_1),
-	SH_PFC_PIN_GROUP(keysc_out8_2),
-	SH_PFC_PIN_GROUP(keysc_out9_0),
-	SH_PFC_PIN_GROUP(keysc_out9_1),
-	SH_PFC_PIN_GROUP(keysc_out9_2),
-	SH_PFC_PIN_GROUP(keysc_out10_0),
-	SH_PFC_PIN_GROUP(keysc_out10_1),
-	SH_PFC_PIN_GROUP(keysc_out11_0),
-	SH_PFC_PIN_GROUP(keysc_out11_1),
-	SH_PFC_PIN_GROUP(lcd_data8),
-	SH_PFC_PIN_GROUP(lcd_data9),
-	SH_PFC_PIN_GROUP(lcd_data12),
-	SH_PFC_PIN_GROUP(lcd_data16),
-	SH_PFC_PIN_GROUP(lcd_data18),
-	SH_PFC_PIN_GROUP(lcd_data24),
-	SH_PFC_PIN_GROUP(lcd_display),
-	SH_PFC_PIN_GROUP(lcd_lclk),
-	SH_PFC_PIN_GROUP(lcd_sync),
-	SH_PFC_PIN_GROUP(lcd_sys),
-	SH_PFC_PIN_GROUP(lcd2_data8),
-	SH_PFC_PIN_GROUP(lcd2_data9),
-	SH_PFC_PIN_GROUP(lcd2_data12),
-	SH_PFC_PIN_GROUP(lcd2_data16),
-	SH_PFC_PIN_GROUP(lcd2_data18),
-	SH_PFC_PIN_GROUP(lcd2_data24),
-	SH_PFC_PIN_GROUP(lcd2_sync_0),
-	SH_PFC_PIN_GROUP(lcd2_sync_1),
-	SH_PFC_PIN_GROUP(lcd2_sys_0),
-	SH_PFC_PIN_GROUP(lcd2_sys_1),
-	SH_PFC_PIN_GROUP(mmc0_data1_0),
-	SH_PFC_PIN_GROUP(mmc0_data4_0),
-	SH_PFC_PIN_GROUP(mmc0_data8_0),
-	SH_PFC_PIN_GROUP(mmc0_ctrl_0),
-	SH_PFC_PIN_GROUP(mmc0_data1_1),
-	SH_PFC_PIN_GROUP(mmc0_data4_1),
-	SH_PFC_PIN_GROUP(mmc0_data8_1),
-	SH_PFC_PIN_GROUP(mmc0_ctrl_1),
-	SH_PFC_PIN_GROUP(msiof0_rsck),
-	SH_PFC_PIN_GROUP(msiof0_tsck),
-	SH_PFC_PIN_GROUP(msiof0_rsync),
-	SH_PFC_PIN_GROUP(msiof0_tsync),
-	SH_PFC_PIN_GROUP(msiof0_ss1),
-	SH_PFC_PIN_GROUP(msiof0_ss2),
-	SH_PFC_PIN_GROUP(msiof0_rxd),
-	SH_PFC_PIN_GROUP(msiof0_txd),
-	SH_PFC_PIN_GROUP(msiof0_mck0),
-	SH_PFC_PIN_GROUP(msiof0_mck1),
-	SH_PFC_PIN_GROUP(msiof0l_rsck),
-	SH_PFC_PIN_GROUP(msiof0l_tsck),
-	SH_PFC_PIN_GROUP(msiof0l_rsync),
-	SH_PFC_PIN_GROUP(msiof0l_tsync),
-	SH_PFC_PIN_GROUP(msiof0l_ss1_a),
-	SH_PFC_PIN_GROUP(msiof0l_ss1_b),
-	SH_PFC_PIN_GROUP(msiof0l_ss2_a),
-	SH_PFC_PIN_GROUP(msiof0l_ss2_b),
-	SH_PFC_PIN_GROUP(msiof0l_rxd),
-	SH_PFC_PIN_GROUP(msiof0l_txd),
-	SH_PFC_PIN_GROUP(msiof0l_mck0),
-	SH_PFC_PIN_GROUP(msiof0l_mck1),
-	SH_PFC_PIN_GROUP(msiof1_rsck),
-	SH_PFC_PIN_GROUP(msiof1_tsck),
-	SH_PFC_PIN_GROUP(msiof1_rsync),
-	SH_PFC_PIN_GROUP(msiof1_tsync),
-	SH_PFC_PIN_GROUP(msiof1_ss1),
-	SH_PFC_PIN_GROUP(msiof1_ss2),
-	SH_PFC_PIN_GROUP(msiof1_rxd),
-	SH_PFC_PIN_GROUP(msiof1_txd),
-	SH_PFC_PIN_GROUP(msiof1_mck0),
-	SH_PFC_PIN_GROUP(msiof1_mck1),
-	SH_PFC_PIN_GROUP(msiof2_rsck),
-	SH_PFC_PIN_GROUP(msiof2_tsck),
-	SH_PFC_PIN_GROUP(msiof2_rsync),
-	SH_PFC_PIN_GROUP(msiof2_tsync),
-	SH_PFC_PIN_GROUP(msiof2_ss1_a),
-	SH_PFC_PIN_GROUP(msiof2_ss1_b),
-	SH_PFC_PIN_GROUP(msiof2_ss2_a),
-	SH_PFC_PIN_GROUP(msiof2_ss2_b),
-	SH_PFC_PIN_GROUP(msiof2_rxd_a),
-	SH_PFC_PIN_GROUP(msiof2_rxd_b),
-	SH_PFC_PIN_GROUP(msiof2_txd),
-	SH_PFC_PIN_GROUP(msiof2_mck0),
-	SH_PFC_PIN_GROUP(msiof2_mck1),
-	SH_PFC_PIN_GROUP(msiof2r_tsck),
-	SH_PFC_PIN_GROUP(msiof2r_tsync),
-	SH_PFC_PIN_GROUP(msiof2r_rxd),
-	SH_PFC_PIN_GROUP(msiof2r_txd),
-	SH_PFC_PIN_GROUP(msiof3_rsck),
-	SH_PFC_PIN_GROUP(msiof3_tsck),
-	SH_PFC_PIN_GROUP(msiof3_rsync),
-	SH_PFC_PIN_GROUP(msiof3_tsync),
-	SH_PFC_PIN_GROUP(msiof3_ss1),
-	SH_PFC_PIN_GROUP(msiof3_ss2),
-	SH_PFC_PIN_GROUP(msiof3_rxd),
-	SH_PFC_PIN_GROUP(msiof3_txd),
-	SH_PFC_PIN_GROUP(msiof3_flow),
-	SH_PFC_PIN_GROUP(scifa0_data),
-	SH_PFC_PIN_GROUP(scifa0_clk),
-	SH_PFC_PIN_GROUP(scifa0_ctrl),
-	SH_PFC_PIN_GROUP(scifa1_data),
-	SH_PFC_PIN_GROUP(scifa1_clk),
-	SH_PFC_PIN_GROUP(scifa1_ctrl),
-	SH_PFC_PIN_GROUP(scifa2_data_0),
-	SH_PFC_PIN_GROUP(scifa2_clk_0),
-	SH_PFC_PIN_GROUP(scifa2_ctrl_0),
-	SH_PFC_PIN_GROUP(scifa2_data_1),
-	SH_PFC_PIN_GROUP(scifa2_clk_1),
-	SH_PFC_PIN_GROUP(scifa2_ctrl_1),
-	SH_PFC_PIN_GROUP(scifa3_data),
-	SH_PFC_PIN_GROUP(scifa3_ctrl),
-	SH_PFC_PIN_GROUP(scifa4_data),
-	SH_PFC_PIN_GROUP(scifa4_ctrl),
-	SH_PFC_PIN_GROUP(scifa5_data_0),
-	SH_PFC_PIN_GROUP(scifa5_clk_0),
-	SH_PFC_PIN_GROUP(scifa5_ctrl_0),
-	SH_PFC_PIN_GROUP(scifa5_data_1),
-	SH_PFC_PIN_GROUP(scifa5_clk_1),
-	SH_PFC_PIN_GROUP(scifa5_ctrl_1),
-	SH_PFC_PIN_GROUP(scifa5_data_2),
-	SH_PFC_PIN_GROUP(scifa5_clk_2),
-	SH_PFC_PIN_GROUP(scifa5_ctrl_2),
-	SH_PFC_PIN_GROUP(scifa6),
-	SH_PFC_PIN_GROUP(scifa7_data),
-	SH_PFC_PIN_GROUP(scifa7_ctrl),
-	SH_PFC_PIN_GROUP(scifb_data_0),
-	SH_PFC_PIN_GROUP(scifb_clk_0),
-	SH_PFC_PIN_GROUP(scifb_ctrl_0),
-	SH_PFC_PIN_GROUP(scifb_data_1),
-	SH_PFC_PIN_GROUP(scifb_clk_1),
-	SH_PFC_PIN_GROUP(scifb_ctrl_1),
-	SH_PFC_PIN_GROUP(sdhi0_data1),
-	SH_PFC_PIN_GROUP(sdhi0_data4),
-	SH_PFC_PIN_GROUP(sdhi0_ctrl),
-	SH_PFC_PIN_GROUP(sdhi0_cd),
-	SH_PFC_PIN_GROUP(sdhi0_wp),
-	SH_PFC_PIN_GROUP(sdhi1_data1),
-	SH_PFC_PIN_GROUP(sdhi1_data4),
-	SH_PFC_PIN_GROUP(sdhi1_ctrl),
-	SH_PFC_PIN_GROUP(sdhi2_data1),
-	SH_PFC_PIN_GROUP(sdhi2_data4),
-	SH_PFC_PIN_GROUP(sdhi2_ctrl),
-	SH_PFC_PIN_GROUP(tpu0_to0),
-	SH_PFC_PIN_GROUP(tpu0_to1),
-	SH_PFC_PIN_GROUP(tpu0_to2),
-	SH_PFC_PIN_GROUP(tpu0_to3),
-	SH_PFC_PIN_GROUP(tpu1_to0),
-	SH_PFC_PIN_GROUP(tpu1_to1_0),
-	SH_PFC_PIN_GROUP(tpu1_to1_1),
-	SH_PFC_PIN_GROUP(tpu1_to2),
-	SH_PFC_PIN_GROUP(tpu1_to3),
-	SH_PFC_PIN_GROUP(tpu2_to0),
-	SH_PFC_PIN_GROUP(tpu2_to1),
-	SH_PFC_PIN_GROUP(tpu2_to2),
-	SH_PFC_PIN_GROUP(tpu2_to3),
-	SH_PFC_PIN_GROUP(tpu3_to0),
-	SH_PFC_PIN_GROUP(tpu3_to1),
-	SH_PFC_PIN_GROUP(tpu3_to2),
-	SH_PFC_PIN_GROUP(tpu3_to3),
-	SH_PFC_PIN_GROUP(tpu4_to0),
-	SH_PFC_PIN_GROUP(tpu4_to1),
-	SH_PFC_PIN_GROUP(tpu4_to2),
-	SH_PFC_PIN_GROUP(tpu4_to3),
-	SH_PFC_PIN_GROUP(usb_vbus),
-};
-
-static const char * const bsc_groups[] = {
-	"bsc_data_0_7",
-	"bsc_data_8_15",
-	"bsc_cs4",
-	"bsc_cs5_a",
-	"bsc_cs5_b",
-	"bsc_cs6_a",
-	"bsc_cs6_b",
-	"bsc_rd",
-	"bsc_rdwr_0",
-	"bsc_rdwr_1",
-	"bsc_rdwr_2",
-	"bsc_we0",
-	"bsc_we1",
-};
-
-static const char * const fsia_groups[] = {
-	"fsia_mclk_in",
-	"fsia_mclk_out",
-	"fsia_sclk_in",
-	"fsia_sclk_out",
-	"fsia_data_in",
-	"fsia_data_out",
-	"fsia_spdif",
-};
-
-static const char * const fsib_groups[] = {
-	"fsib_mclk_in",
-	"fsib_mclk_out",
-	"fsib_sclk_in",
-	"fsib_sclk_out",
-	"fsib_data_in",
-	"fsib_data_out",
-	"fsib_spdif",
-};
-
-static const char * const fsic_groups[] = {
-	"fsic_mclk_in",
-	"fsic_mclk_out",
-	"fsic_sclk_in",
-	"fsic_sclk_out",
-	"fsic_data_in",
-	"fsic_data_out",
-	"fsic_spdif_0",
-	"fsic_spdif_1",
-};
-
-static const char * const fsid_groups[] = {
-	"fsid_sclk_in",
-	"fsid_sclk_out",
-	"fsid_data_in",
-};
-
-static const char * const i2c2_groups[] = {
-	"i2c2_0",
-	"i2c2_1",
-	"i2c2_2",
-};
-
-static const char * const i2c3_groups[] = {
-	"i2c3_0",
-	"i2c3_1",
-	"i2c3_2",
-};
-
-static const char * const irda_groups[] = {
-	"irda_0",
-	"irda_1",
-};
-
-static const char * const keysc_groups[] = {
-	"keysc_in5",
-	"keysc_in6",
-	"keysc_in7",
-	"keysc_in8",
-	"keysc_out04",
-	"keysc_out5",
-	"keysc_out6_0",
-	"keysc_out6_1",
-	"keysc_out6_2",
-	"keysc_out7_0",
-	"keysc_out7_1",
-	"keysc_out7_2",
-	"keysc_out8_0",
-	"keysc_out8_1",
-	"keysc_out8_2",
-	"keysc_out9_0",
-	"keysc_out9_1",
-	"keysc_out9_2",
-	"keysc_out10_0",
-	"keysc_out10_1",
-	"keysc_out11_0",
-	"keysc_out11_1",
-};
-
-static const char * const lcd_groups[] = {
-	"lcd_data8",
-	"lcd_data9",
-	"lcd_data12",
-	"lcd_data16",
-	"lcd_data18",
-	"lcd_data24",
-	"lcd_display",
-	"lcd_lclk",
-	"lcd_sync",
-	"lcd_sys",
-};
-
-static const char * const lcd2_groups[] = {
-	"lcd2_data8",
-	"lcd2_data9",
-	"lcd2_data12",
-	"lcd2_data16",
-	"lcd2_data18",
-	"lcd2_data24",
-	"lcd2_sync_0",
-	"lcd2_sync_1",
-	"lcd2_sys_0",
-	"lcd2_sys_1",
-};
-
-static const char * const mmc0_groups[] = {
-	"mmc0_data1_0",
-	"mmc0_data4_0",
-	"mmc0_data8_0",
-	"mmc0_ctrl_0",
-	"mmc0_data1_1",
-	"mmc0_data4_1",
-	"mmc0_data8_1",
-	"mmc0_ctrl_1",
-};
-
-static const char * const msiof0_groups[] = {
-	"msiof0_rsck",
-	"msiof0_tsck",
-	"msiof0_rsync",
-	"msiof0_tsync",
-	"msiof0_ss1",
-	"msiof0_ss2",
-	"msiof0_rxd",
-	"msiof0_txd",
-	"msiof0_mck0",
-	"msiof0_mck1",
-	"msiof0l_rsck",
-	"msiof0l_tsck",
-	"msiof0l_rsync",
-	"msiof0l_tsync",
-	"msiof0l_ss1_a",
-	"msiof0l_ss1_b",
-	"msiof0l_ss2_a",
-	"msiof0l_ss2_b",
-	"msiof0l_rxd",
-	"msiof0l_txd",
-	"msiof0l_mck0",
-	"msiof0l_mck1",
-};
-
-static const char * const msiof1_groups[] = {
-	"msiof1_rsck",
-	"msiof1_tsck",
-	"msiof1_rsync",
-	"msiof1_tsync",
-	"msiof1_ss1",
-	"msiof1_ss2",
-	"msiof1_rxd",
-	"msiof1_txd",
-	"msiof1_mck0",
-	"msiof1_mck1",
-};
-
-static const char * const msiof2_groups[] = {
-	"msiof2_rsck",
-	"msiof2_tsck",
-	"msiof2_rsync",
-	"msiof2_tsync",
-	"msiof2_ss1_a",
-	"msiof2_ss1_b",
-	"msiof2_ss2_a",
-	"msiof2_ss2_b",
-	"msiof2_rxd_a",
-	"msiof2_rxd_b",
-	"msiof2_txd",
-	"msiof2_mck0",
-	"msiof2_mck1",
-	"msiof2r_tsck",
-	"msiof2r_tsync",
-	"msiof2r_rxd",
-	"msiof2r_txd",
-};
-
-static const char * const msiof3_groups[] = {
-	"msiof3_rsck",
-	"msiof3_tsck",
-	"msiof3_rsync",
-	"msiof3_tsync",
-	"msiof3_ss1",
-	"msiof3_ss2",
-	"msiof3_rxd",
-	"msiof3_txd",
-	"msiof3_flow",
-};
-
-static const char * const scifa0_groups[] = {
-	"scifa0_data",
-	"scifa0_clk",
-	"scifa0_ctrl",
-};
-
-static const char * const scifa1_groups[] = {
-	"scifa1_data",
-	"scifa1_clk",
-	"scifa1_ctrl",
-};
-
-static const char * const scifa2_groups[] = {
-	"scifa2_data_0",
-	"scifa2_clk_0",
-	"scifa2_ctrl_0",
-	"scifa2_data_1",
-	"scifa2_clk_1",
-	"scifa2_ctrl_1",
-};
-
-static const char * const scifa3_groups[] = {
-	"scifa3_data",
-	"scifa3_ctrl",
-};
-
-static const char * const scifa4_groups[] = {
-	"scifa4_data",
-	"scifa4_ctrl",
-};
-
-static const char * const scifa5_groups[] = {
-	"scifa5_data_0",
-	"scifa5_clk_0",
-	"scifa5_ctrl_0",
-	"scifa5_data_1",
-	"scifa5_clk_1",
-	"scifa5_ctrl_1",
-	"scifa5_data_2",
-	"scifa5_clk_2",
-	"scifa5_ctrl_2",
-};
-
-static const char * const scifa6_groups[] = {
-	"scifa6",
-};
-
-static const char * const scifa7_groups[] = {
-	"scifa7_data",
-	"scifa7_ctrl",
-};
-
-static const char * const scifb_groups[] = {
-	"scifb_data_0",
-	"scifb_clk_0",
-	"scifb_ctrl_0",
-	"scifb_data_1",
-	"scifb_clk_1",
-	"scifb_ctrl_1",
-};
-
-static const char * const sdhi0_groups[] = {
-	"sdhi0_data1",
-	"sdhi0_data4",
-	"sdhi0_ctrl",
-	"sdhi0_cd",
-	"sdhi0_wp",
-};
-
-static const char * const sdhi1_groups[] = {
-	"sdhi1_data1",
-	"sdhi1_data4",
-	"sdhi1_ctrl",
-};
-
-static const char * const sdhi2_groups[] = {
-	"sdhi2_data1",
-	"sdhi2_data4",
-	"sdhi2_ctrl",
-};
-
-static const char * const usb_groups[] = {
-	"usb_vbus",
-};
-
-static const char * const tpu0_groups[] = {
-	"tpu0_to0",
-	"tpu0_to1",
-	"tpu0_to2",
-	"tpu0_to3",
-};
-
-static const char * const tpu1_groups[] = {
-	"tpu1_to0",
-	"tpu1_to1_0",
-	"tpu1_to1_1",
-	"tpu1_to2",
-	"tpu1_to3",
-};
-
-static const char * const tpu2_groups[] = {
-	"tpu2_to0",
-	"tpu2_to1",
-	"tpu2_to2",
-	"tpu2_to3",
-};
-
-static const char * const tpu3_groups[] = {
-	"tpu3_to0",
-	"tpu3_to1",
-	"tpu3_to2",
-	"tpu3_to3",
-};
-
-static const char * const tpu4_groups[] = {
-	"tpu4_to0",
-	"tpu4_to1",
-	"tpu4_to2",
-	"tpu4_to3",
-};
-
-static const struct sh_pfc_function pinmux_functions[] = {
-	SH_PFC_FUNCTION(bsc),
-	SH_PFC_FUNCTION(fsia),
-	SH_PFC_FUNCTION(fsib),
-	SH_PFC_FUNCTION(fsic),
-	SH_PFC_FUNCTION(fsid),
-	SH_PFC_FUNCTION(i2c2),
-	SH_PFC_FUNCTION(i2c3),
-	SH_PFC_FUNCTION(irda),
-	SH_PFC_FUNCTION(keysc),
-	SH_PFC_FUNCTION(lcd),
-	SH_PFC_FUNCTION(lcd2),
-	SH_PFC_FUNCTION(mmc0),
-	SH_PFC_FUNCTION(msiof0),
-	SH_PFC_FUNCTION(msiof1),
-	SH_PFC_FUNCTION(msiof2),
-	SH_PFC_FUNCTION(msiof3),
-	SH_PFC_FUNCTION(scifa0),
-	SH_PFC_FUNCTION(scifa1),
-	SH_PFC_FUNCTION(scifa2),
-	SH_PFC_FUNCTION(scifa3),
-	SH_PFC_FUNCTION(scifa4),
-	SH_PFC_FUNCTION(scifa5),
-	SH_PFC_FUNCTION(scifa6),
-	SH_PFC_FUNCTION(scifa7),
-	SH_PFC_FUNCTION(scifb),
-	SH_PFC_FUNCTION(sdhi0),
-	SH_PFC_FUNCTION(sdhi1),
-	SH_PFC_FUNCTION(sdhi2),
-	SH_PFC_FUNCTION(tpu0),
-	SH_PFC_FUNCTION(tpu1),
-	SH_PFC_FUNCTION(tpu2),
-	SH_PFC_FUNCTION(tpu3),
-	SH_PFC_FUNCTION(tpu4),
-	SH_PFC_FUNCTION(usb),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	PORTCR(0, 0xe6050000), /* PORT0CR */
-	PORTCR(1, 0xe6050001), /* PORT1CR */
-	PORTCR(2, 0xe6050002), /* PORT2CR */
-	PORTCR(3, 0xe6050003), /* PORT3CR */
-	PORTCR(4, 0xe6050004), /* PORT4CR */
-	PORTCR(5, 0xe6050005), /* PORT5CR */
-	PORTCR(6, 0xe6050006), /* PORT6CR */
-	PORTCR(7, 0xe6050007), /* PORT7CR */
-	PORTCR(8, 0xe6050008), /* PORT8CR */
-	PORTCR(9, 0xe6050009), /* PORT9CR */
-
-	PORTCR(10, 0xe605000a), /* PORT10CR */
-	PORTCR(11, 0xe605000b), /* PORT11CR */
-	PORTCR(12, 0xe605000c), /* PORT12CR */
-	PORTCR(13, 0xe605000d), /* PORT13CR */
-	PORTCR(14, 0xe605000e), /* PORT14CR */
-	PORTCR(15, 0xe605000f), /* PORT15CR */
-	PORTCR(16, 0xe6050010), /* PORT16CR */
-	PORTCR(17, 0xe6050011), /* PORT17CR */
-	PORTCR(18, 0xe6050012), /* PORT18CR */
-	PORTCR(19, 0xe6050013), /* PORT19CR */
-
-	PORTCR(20, 0xe6050014), /* PORT20CR */
-	PORTCR(21, 0xe6050015), /* PORT21CR */
-	PORTCR(22, 0xe6050016), /* PORT22CR */
-	PORTCR(23, 0xe6050017), /* PORT23CR */
-	PORTCR(24, 0xe6050018), /* PORT24CR */
-	PORTCR(25, 0xe6050019), /* PORT25CR */
-	PORTCR(26, 0xe605001a), /* PORT26CR */
-	PORTCR(27, 0xe605001b), /* PORT27CR */
-	PORTCR(28, 0xe605001c), /* PORT28CR */
-	PORTCR(29, 0xe605001d), /* PORT29CR */
-
-	PORTCR(30, 0xe605001e), /* PORT30CR */
-	PORTCR(31, 0xe605001f), /* PORT31CR */
-	PORTCR(32, 0xe6051020), /* PORT32CR */
-	PORTCR(33, 0xe6051021), /* PORT33CR */
-	PORTCR(34, 0xe6051022), /* PORT34CR */
-	PORTCR(35, 0xe6051023), /* PORT35CR */
-	PORTCR(36, 0xe6051024), /* PORT36CR */
-	PORTCR(37, 0xe6051025), /* PORT37CR */
-	PORTCR(38, 0xe6051026), /* PORT38CR */
-	PORTCR(39, 0xe6051027), /* PORT39CR */
-
-	PORTCR(40, 0xe6051028), /* PORT40CR */
-	PORTCR(41, 0xe6051029), /* PORT41CR */
-	PORTCR(42, 0xe605102a), /* PORT42CR */
-	PORTCR(43, 0xe605102b), /* PORT43CR */
-	PORTCR(44, 0xe605102c), /* PORT44CR */
-	PORTCR(45, 0xe605102d), /* PORT45CR */
-	PORTCR(46, 0xe605102e), /* PORT46CR */
-	PORTCR(47, 0xe605102f), /* PORT47CR */
-	PORTCR(48, 0xe6051030), /* PORT48CR */
-	PORTCR(49, 0xe6051031), /* PORT49CR */
-
-	PORTCR(50, 0xe6051032), /* PORT50CR */
-	PORTCR(51, 0xe6051033), /* PORT51CR */
-	PORTCR(52, 0xe6051034), /* PORT52CR */
-	PORTCR(53, 0xe6051035), /* PORT53CR */
-	PORTCR(54, 0xe6051036), /* PORT54CR */
-	PORTCR(55, 0xe6051037), /* PORT55CR */
-	PORTCR(56, 0xe6051038), /* PORT56CR */
-	PORTCR(57, 0xe6051039), /* PORT57CR */
-	PORTCR(58, 0xe605103a), /* PORT58CR */
-	PORTCR(59, 0xe605103b), /* PORT59CR */
-
-	PORTCR(60, 0xe605103c), /* PORT60CR */
-	PORTCR(61, 0xe605103d), /* PORT61CR */
-	PORTCR(62, 0xe605103e), /* PORT62CR */
-	PORTCR(63, 0xe605103f), /* PORT63CR */
-	PORTCR(64, 0xe6051040), /* PORT64CR */
-	PORTCR(65, 0xe6051041), /* PORT65CR */
-	PORTCR(66, 0xe6051042), /* PORT66CR */
-	PORTCR(67, 0xe6051043), /* PORT67CR */
-	PORTCR(68, 0xe6051044), /* PORT68CR */
-	PORTCR(69, 0xe6051045), /* PORT69CR */
-
-	PORTCR(70, 0xe6051046), /* PORT70CR */
-	PORTCR(71, 0xe6051047), /* PORT71CR */
-	PORTCR(72, 0xe6051048), /* PORT72CR */
-	PORTCR(73, 0xe6051049), /* PORT73CR */
-	PORTCR(74, 0xe605104a), /* PORT74CR */
-	PORTCR(75, 0xe605104b), /* PORT75CR */
-	PORTCR(76, 0xe605104c), /* PORT76CR */
-	PORTCR(77, 0xe605104d), /* PORT77CR */
-	PORTCR(78, 0xe605104e), /* PORT78CR */
-	PORTCR(79, 0xe605104f), /* PORT79CR */
-
-	PORTCR(80, 0xe6051050), /* PORT80CR */
-	PORTCR(81, 0xe6051051), /* PORT81CR */
-	PORTCR(82, 0xe6051052), /* PORT82CR */
-	PORTCR(83, 0xe6051053), /* PORT83CR */
-	PORTCR(84, 0xe6051054), /* PORT84CR */
-	PORTCR(85, 0xe6051055), /* PORT85CR */
-	PORTCR(86, 0xe6051056), /* PORT86CR */
-	PORTCR(87, 0xe6051057), /* PORT87CR */
-	PORTCR(88, 0xe6051058), /* PORT88CR */
-	PORTCR(89, 0xe6051059), /* PORT89CR */
-
-	PORTCR(90, 0xe605105a), /* PORT90CR */
-	PORTCR(91, 0xe605105b), /* PORT91CR */
-	PORTCR(92, 0xe605105c), /* PORT92CR */
-	PORTCR(93, 0xe605105d), /* PORT93CR */
-	PORTCR(94, 0xe605105e), /* PORT94CR */
-	PORTCR(95, 0xe605105f), /* PORT95CR */
-	PORTCR(96, 0xe6052060), /* PORT96CR */
-	PORTCR(97, 0xe6052061), /* PORT97CR */
-	PORTCR(98, 0xe6052062), /* PORT98CR */
-	PORTCR(99, 0xe6052063), /* PORT99CR */
-
-	PORTCR(100, 0xe6052064), /* PORT100CR */
-	PORTCR(101, 0xe6052065), /* PORT101CR */
-	PORTCR(102, 0xe6052066), /* PORT102CR */
-	PORTCR(103, 0xe6052067), /* PORT103CR */
-	PORTCR(104, 0xe6052068), /* PORT104CR */
-	PORTCR(105, 0xe6052069), /* PORT105CR */
-	PORTCR(106, 0xe605206a), /* PORT106CR */
-	PORTCR(107, 0xe605206b), /* PORT107CR */
-	PORTCR(108, 0xe605206c), /* PORT108CR */
-	PORTCR(109, 0xe605206d), /* PORT109CR */
-
-	PORTCR(110, 0xe605206e), /* PORT110CR */
-	PORTCR(111, 0xe605206f), /* PORT111CR */
-	PORTCR(112, 0xe6052070), /* PORT112CR */
-	PORTCR(113, 0xe6052071), /* PORT113CR */
-	PORTCR(114, 0xe6052072), /* PORT114CR */
-	PORTCR(115, 0xe6052073), /* PORT115CR */
-	PORTCR(116, 0xe6052074), /* PORT116CR */
-	PORTCR(117, 0xe6052075), /* PORT117CR */
-	PORTCR(118, 0xe6052076), /* PORT118CR */
-
-	PORTCR(128, 0xe6052080), /* PORT128CR */
-	PORTCR(129, 0xe6052081), /* PORT129CR */
-
-	PORTCR(130, 0xe6052082), /* PORT130CR */
-	PORTCR(131, 0xe6052083), /* PORT131CR */
-	PORTCR(132, 0xe6052084), /* PORT132CR */
-	PORTCR(133, 0xe6052085), /* PORT133CR */
-	PORTCR(134, 0xe6052086), /* PORT134CR */
-	PORTCR(135, 0xe6052087), /* PORT135CR */
-	PORTCR(136, 0xe6052088), /* PORT136CR */
-	PORTCR(137, 0xe6052089), /* PORT137CR */
-	PORTCR(138, 0xe605208a), /* PORT138CR */
-	PORTCR(139, 0xe605208b), /* PORT139CR */
-
-	PORTCR(140, 0xe605208c), /* PORT140CR */
-	PORTCR(141, 0xe605208d), /* PORT141CR */
-	PORTCR(142, 0xe605208e), /* PORT142CR */
-	PORTCR(143, 0xe605208f), /* PORT143CR */
-	PORTCR(144, 0xe6052090), /* PORT144CR */
-	PORTCR(145, 0xe6052091), /* PORT145CR */
-	PORTCR(146, 0xe6052092), /* PORT146CR */
-	PORTCR(147, 0xe6052093), /* PORT147CR */
-	PORTCR(148, 0xe6052094), /* PORT148CR */
-	PORTCR(149, 0xe6052095), /* PORT149CR */
-
-	PORTCR(150, 0xe6052096), /* PORT150CR */
-	PORTCR(151, 0xe6052097), /* PORT151CR */
-	PORTCR(152, 0xe6052098), /* PORT152CR */
-	PORTCR(153, 0xe6052099), /* PORT153CR */
-	PORTCR(154, 0xe605209a), /* PORT154CR */
-	PORTCR(155, 0xe605209b), /* PORT155CR */
-	PORTCR(156, 0xe605209c), /* PORT156CR */
-	PORTCR(157, 0xe605209d), /* PORT157CR */
-	PORTCR(158, 0xe605209e), /* PORT158CR */
-	PORTCR(159, 0xe605209f), /* PORT159CR */
-
-	PORTCR(160, 0xe60520a0), /* PORT160CR */
-	PORTCR(161, 0xe60520a1), /* PORT161CR */
-	PORTCR(162, 0xe60520a2), /* PORT162CR */
-	PORTCR(163, 0xe60520a3), /* PORT163CR */
-	PORTCR(164, 0xe60520a4), /* PORT164CR */
-
-	PORTCR(192, 0xe60520c0), /* PORT192CR */
-	PORTCR(193, 0xe60520c1), /* PORT193CR */
-	PORTCR(194, 0xe60520c2), /* PORT194CR */
-	PORTCR(195, 0xe60520c3), /* PORT195CR */
-	PORTCR(196, 0xe60520c4), /* PORT196CR */
-	PORTCR(197, 0xe60520c5), /* PORT197CR */
-	PORTCR(198, 0xe60520c6), /* PORT198CR */
-	PORTCR(199, 0xe60520c7), /* PORT199CR */
-
-	PORTCR(200, 0xe60520c8), /* PORT200CR */
-	PORTCR(201, 0xe60520c9), /* PORT201CR */
-	PORTCR(202, 0xe60520ca), /* PORT202CR */
-	PORTCR(203, 0xe60520cb), /* PORT203CR */
-	PORTCR(204, 0xe60520cc), /* PORT204CR */
-	PORTCR(205, 0xe60520cd), /* PORT205CR */
-	PORTCR(206, 0xe60520ce), /* PORT206CR */
-	PORTCR(207, 0xe60520cf), /* PORT207CR */
-	PORTCR(208, 0xe60520d0), /* PORT208CR */
-	PORTCR(209, 0xe60520d1), /* PORT209CR */
-
-	PORTCR(210, 0xe60520d2), /* PORT210CR */
-	PORTCR(211, 0xe60520d3), /* PORT211CR */
-	PORTCR(212, 0xe60520d4), /* PORT212CR */
-	PORTCR(213, 0xe60520d5), /* PORT213CR */
-	PORTCR(214, 0xe60520d6), /* PORT214CR */
-	PORTCR(215, 0xe60520d7), /* PORT215CR */
-	PORTCR(216, 0xe60520d8), /* PORT216CR */
-	PORTCR(217, 0xe60520d9), /* PORT217CR */
-	PORTCR(218, 0xe60520da), /* PORT218CR */
-	PORTCR(219, 0xe60520db), /* PORT219CR */
-
-	PORTCR(220, 0xe60520dc), /* PORT220CR */
-	PORTCR(221, 0xe60520dd), /* PORT221CR */
-	PORTCR(222, 0xe60520de), /* PORT222CR */
-	PORTCR(223, 0xe60520df), /* PORT223CR */
-	PORTCR(224, 0xe60530e0), /* PORT224CR */
-	PORTCR(225, 0xe60530e1), /* PORT225CR */
-	PORTCR(226, 0xe60530e2), /* PORT226CR */
-	PORTCR(227, 0xe60530e3), /* PORT227CR */
-	PORTCR(228, 0xe60530e4), /* PORT228CR */
-	PORTCR(229, 0xe60530e5), /* PORT229CR */
-
-	PORTCR(230, 0xe60530e6), /* PORT230CR */
-	PORTCR(231, 0xe60530e7), /* PORT231CR */
-	PORTCR(232, 0xe60530e8), /* PORT232CR */
-	PORTCR(233, 0xe60530e9), /* PORT233CR */
-	PORTCR(234, 0xe60530ea), /* PORT234CR */
-	PORTCR(235, 0xe60530eb), /* PORT235CR */
-	PORTCR(236, 0xe60530ec), /* PORT236CR */
-	PORTCR(237, 0xe60530ed), /* PORT237CR */
-	PORTCR(238, 0xe60530ee), /* PORT238CR */
-	PORTCR(239, 0xe60530ef), /* PORT239CR */
-
-	PORTCR(240, 0xe60530f0), /* PORT240CR */
-	PORTCR(241, 0xe60530f1), /* PORT241CR */
-	PORTCR(242, 0xe60530f2), /* PORT242CR */
-	PORTCR(243, 0xe60530f3), /* PORT243CR */
-	PORTCR(244, 0xe60530f4), /* PORT244CR */
-	PORTCR(245, 0xe60530f5), /* PORT245CR */
-	PORTCR(246, 0xe60530f6), /* PORT246CR */
-	PORTCR(247, 0xe60530f7), /* PORT247CR */
-	PORTCR(248, 0xe60530f8), /* PORT248CR */
-	PORTCR(249, 0xe60530f9), /* PORT249CR */
-
-	PORTCR(250, 0xe60530fa), /* PORT250CR */
-	PORTCR(251, 0xe60530fb), /* PORT251CR */
-	PORTCR(252, 0xe60530fc), /* PORT252CR */
-	PORTCR(253, 0xe60530fd), /* PORT253CR */
-	PORTCR(254, 0xe60530fe), /* PORT254CR */
-	PORTCR(255, 0xe60530ff), /* PORT255CR */
-	PORTCR(256, 0xe6053100), /* PORT256CR */
-	PORTCR(257, 0xe6053101), /* PORT257CR */
-	PORTCR(258, 0xe6053102), /* PORT258CR */
-	PORTCR(259, 0xe6053103), /* PORT259CR */
-
-	PORTCR(260, 0xe6053104), /* PORT260CR */
-	PORTCR(261, 0xe6053105), /* PORT261CR */
-	PORTCR(262, 0xe6053106), /* PORT262CR */
-	PORTCR(263, 0xe6053107), /* PORT263CR */
-	PORTCR(264, 0xe6053108), /* PORT264CR */
-	PORTCR(265, 0xe6053109), /* PORT265CR */
-	PORTCR(266, 0xe605310a), /* PORT266CR */
-	PORTCR(267, 0xe605310b), /* PORT267CR */
-	PORTCR(268, 0xe605310c), /* PORT268CR */
-	PORTCR(269, 0xe605310d), /* PORT269CR */
-
-	PORTCR(270, 0xe605310e), /* PORT270CR */
-	PORTCR(271, 0xe605310f), /* PORT271CR */
-	PORTCR(272, 0xe6053110), /* PORT272CR */
-	PORTCR(273, 0xe6053111), /* PORT273CR */
-	PORTCR(274, 0xe6053112), /* PORT274CR */
-	PORTCR(275, 0xe6053113), /* PORT275CR */
-	PORTCR(276, 0xe6053114), /* PORT276CR */
-	PORTCR(277, 0xe6053115), /* PORT277CR */
-	PORTCR(278, 0xe6053116), /* PORT278CR */
-	PORTCR(279, 0xe6053117), /* PORT279CR */
-
-	PORTCR(280, 0xe6053118), /* PORT280CR */
-	PORTCR(281, 0xe6053119), /* PORT281CR */
-	PORTCR(282, 0xe605311a), /* PORT282CR */
-
-	PORTCR(288, 0xe6052120), /* PORT288CR */
-	PORTCR(289, 0xe6052121), /* PORT289CR */
-
-	PORTCR(290, 0xe6052122), /* PORT290CR */
-	PORTCR(291, 0xe6052123), /* PORT291CR */
-	PORTCR(292, 0xe6052124), /* PORT292CR */
-	PORTCR(293, 0xe6052125), /* PORT293CR */
-	PORTCR(294, 0xe6052126), /* PORT294CR */
-	PORTCR(295, 0xe6052127), /* PORT295CR */
-	PORTCR(296, 0xe6052128), /* PORT296CR */
-	PORTCR(297, 0xe6052129), /* PORT297CR */
-	PORTCR(298, 0xe605212a), /* PORT298CR */
-	PORTCR(299, 0xe605212b), /* PORT299CR */
-
-	PORTCR(300, 0xe605212c), /* PORT300CR */
-	PORTCR(301, 0xe605212d), /* PORT301CR */
-	PORTCR(302, 0xe605212e), /* PORT302CR */
-	PORTCR(303, 0xe605212f), /* PORT303CR */
-	PORTCR(304, 0xe6052130), /* PORT304CR */
-	PORTCR(305, 0xe6052131), /* PORT305CR */
-	PORTCR(306, 0xe6052132), /* PORT306CR */
-	PORTCR(307, 0xe6052133), /* PORT307CR */
-	PORTCR(308, 0xe6052134), /* PORT308CR */
-	PORTCR(309, 0xe6052135), /* PORT309CR */
-
-	{ PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1, GROUP(
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
-			MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
-			MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
-			MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
-			0, 0,
-			MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
-			MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
-			MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
-			MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
-			MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
-			MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
-			MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
-			MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
-			MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
-			MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
-			MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
-			MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
-			MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
-			MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
-			MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
-		))
-	},
-	{ PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1, GROUP(
-			0, 0,
-			0, 0,
-			0, 0,
-			MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			0, 0,
-			MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
-			0, 0,
-			0, 0,
-			0, 0,
-			MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
-			0, 0,
-			MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
-			0, 0,
-			0, 0,
-			MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
-			0, 0,
-			0, 0,
-			0, 0,
-			MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
-			0, 0,
-			0, 0,
-		))
-	},
-	{ PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1, GROUP(
-			0, 0,
-			0, 0,
-			MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
-			0, 0,
-			MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
-			MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
-			0, 0,
-			0, 0,
-			0, 0,
-			MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
-			MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
-			MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
-			MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
-			0, 0,
-			0, 0,
-			0, 0,
-			MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
-			0, 0,
-			MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
-			MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
-			MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
-			MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
-			MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
-			MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
-			MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
-			0, 0,
-			0, 0,
-			MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
-			0, 0,
-			0, 0,
-			MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
-			0, 0,
-		))
-	},
-	{ },
-};
-
-static const struct pinmux_data_reg pinmux_data_regs[] = {
-	{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32, GROUP(
-			PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
-			PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
-			PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
-			PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
-			PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
-			PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
-			PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
-			PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32, GROUP(
-			PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
-			PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
-			PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
-			PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
-			PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
-			PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
-			PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
-			PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA ))
-	},
-	{ PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32, GROUP(
-			PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
-			PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
-			PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
-			PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
-			PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
-			PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
-			PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
-			PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA ))
-	},
-	{ PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32, GROUP(
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
-			PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
-			PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
-			PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
-			PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
-			PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA ))
-	},
-	{ PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32, GROUP(
-			PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
-			PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
-			PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
-			PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
-			PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
-			PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
-			PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
-			PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA ))
-	},
-	{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32, GROUP(
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, 0, 0, PORT164_DATA,
-			PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA ))
-	},
-	{ PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32, GROUP(
-			PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
-			PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
-			PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
-			PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
-			PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
-			PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
-			PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
-			PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA ))
-	},
-	{ PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32, GROUP(
-			PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
-			PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
-			PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
-			PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
-			PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
-			PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
-			PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
-			PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA ))
-	},
-	{ PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32, GROUP(
-			0, 0, 0, 0,
-			0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
-			PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
-			PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
-			PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
-			PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
-			PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
-			PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA ))
-	},
-	{ PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32, GROUP(
-			0, 0, 0, 0,
-			0, 0, 0, 0,
-			0, 0, PORT309_DATA, PORT308_DATA,
-			PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
-			PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
-			PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
-			PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
-			PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA ))
-	},
-	{ },
-};
-
-static const struct pinmux_irq pinmux_irqs[] = {
-	PINMUX_IRQ(11),		/* IRQ0 */
-	PINMUX_IRQ(10),		/* IRQ1 */
-	PINMUX_IRQ(149),	/* IRQ2 */
-	PINMUX_IRQ(224),	/* IRQ3 */
-	PINMUX_IRQ(159),	/* IRQ4 */
-	PINMUX_IRQ(227),	/* IRQ5 */
-	PINMUX_IRQ(147),	/* IRQ6 */
-	PINMUX_IRQ(150),	/* IRQ7 */
-	PINMUX_IRQ(223),	/* IRQ8 */
-	PINMUX_IRQ(56, 308),	/* IRQ9 */
-	PINMUX_IRQ(54),		/* IRQ10 */
-	PINMUX_IRQ(238),	/* IRQ11 */
-	PINMUX_IRQ(156),	/* IRQ12 */
-	PINMUX_IRQ(239),	/* IRQ13 */
-	PINMUX_IRQ(251),	/* IRQ14 */
-	PINMUX_IRQ(0),		/* IRQ15 */
-	PINMUX_IRQ(249),	/* IRQ16 */
-	PINMUX_IRQ(234),	/* IRQ17 */
-	PINMUX_IRQ(13),		/* IRQ18 */
-	PINMUX_IRQ(9),		/* IRQ19 */
-	PINMUX_IRQ(14),		/* IRQ20 */
-	PINMUX_IRQ(15),		/* IRQ21 */
-	PINMUX_IRQ(40),		/* IRQ22 */
-	PINMUX_IRQ(53),		/* IRQ23 */
-	PINMUX_IRQ(118),	/* IRQ24 */
-	PINMUX_IRQ(164),	/* IRQ25 */
-	PINMUX_IRQ(115),	/* IRQ26 */
-	PINMUX_IRQ(116),	/* IRQ27 */
-	PINMUX_IRQ(117),	/* IRQ28 */
-	PINMUX_IRQ(28),		/* IRQ29 */
-	PINMUX_IRQ(27),		/* IRQ30 */
-	PINMUX_IRQ(26),		/* IRQ31 */
-};
-
-/* -----------------------------------------------------------------------------
- * VCCQ MC0 regulator
- */
-
-static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
-{
-	struct sh_pfc *pfc = reg->reg_data;
-	void __iomem *addr = pfc->windows[1].virt + 4;
-	unsigned long flags;
-	u32 value;
-
-	spin_lock_irqsave(&pfc->lock, flags);
-
-	value = ioread32(addr);
-
-	if (enable)
-		value |= BIT(28);
-	else
-		value &= ~BIT(28);
-
-	iowrite32(value, addr);
-
-	spin_unlock_irqrestore(&pfc->lock, flags);
-}
-
-static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg)
-{
-	sh73a0_vccq_mc0_endisable(reg, true);
-	return 0;
-}
-
-static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg)
-{
-	sh73a0_vccq_mc0_endisable(reg, false);
-	return 0;
-}
-
-static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
-{
-	struct sh_pfc *pfc = reg->reg_data;
-	void __iomem *addr = pfc->windows[1].virt + 4;
-	unsigned long flags;
-	u32 value;
-
-	spin_lock_irqsave(&pfc->lock, flags);
-	value = ioread32(addr);
-	spin_unlock_irqrestore(&pfc->lock, flags);
-
-	return !!(value & BIT(28));
-}
-
-static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg)
-{
-	return 3300000;
-}
-
-static struct regulator_ops sh73a0_vccq_mc0_ops = {
-	.enable = sh73a0_vccq_mc0_enable,
-	.disable = sh73a0_vccq_mc0_disable,
-	.is_enabled = sh73a0_vccq_mc0_is_enabled,
-	.get_voltage = sh73a0_vccq_mc0_get_voltage,
-};
-
-static const struct regulator_desc sh73a0_vccq_mc0_desc = {
-	.owner = THIS_MODULE,
-	.name = "vccq_mc0",
-	.type = REGULATOR_VOLTAGE,
-	.ops = &sh73a0_vccq_mc0_ops,
-};
-
-static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = {
-	REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
-	REGULATOR_SUPPLY("vqmmc", "ee100000.sdhi"),
-};
-
-static const struct regulator_init_data sh73a0_vccq_mc0_init_data = {
-	.constraints = {
-		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
-	},
-	.num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers),
-	.consumer_supplies = sh73a0_vccq_mc0_consumers,
-};
-
-/* -----------------------------------------------------------------------------
- * Pin bias
- */
-
-#define PORTnCR_PULMD_OFF	(0 << 6)
-#define PORTnCR_PULMD_DOWN	(2 << 6)
-#define PORTnCR_PULMD_UP	(3 << 6)
-#define PORTnCR_PULMD_MASK	(3 << 6)
-
-static const unsigned int sh73a0_portcr_offsets[] = {
-	0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000,
-	0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000,
-};
-
-static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
-{
-	void __iomem *addr = pfc->windows->virt
-			   + sh73a0_portcr_offsets[pin >> 5] + pin;
-	u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
-
-	switch (value) {
-	case PORTnCR_PULMD_UP:
-		return PIN_CONFIG_BIAS_PULL_UP;
-	case PORTnCR_PULMD_DOWN:
-		return PIN_CONFIG_BIAS_PULL_DOWN;
-	case PORTnCR_PULMD_OFF:
-	default:
-		return PIN_CONFIG_BIAS_DISABLE;
-	}
-}
-
-static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
-				   unsigned int bias)
-{
-	void __iomem *addr = pfc->windows->virt
-			   + sh73a0_portcr_offsets[pin >> 5] + pin;
-	u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
-
-	switch (bias) {
-	case PIN_CONFIG_BIAS_PULL_UP:
-		value |= PORTnCR_PULMD_UP;
-		break;
-	case PIN_CONFIG_BIAS_PULL_DOWN:
-		value |= PORTnCR_PULMD_DOWN;
-		break;
-	}
-
-	iowrite8(value, addr);
-}
-
-/* -----------------------------------------------------------------------------
- * SoC information
- */
-
-static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
-{
-	struct regulator_config cfg = { };
-	struct regulator_dev *vccq;
-	int ret;
-
-	cfg.dev = pfc->dev;
-	cfg.init_data = &sh73a0_vccq_mc0_init_data;
-	cfg.driver_data = pfc;
-
-	vccq = devm_regulator_register(pfc->dev, &sh73a0_vccq_mc0_desc, &cfg);
-	if (IS_ERR(vccq)) {
-		ret = PTR_ERR(vccq);
-		dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
-			ret);
-		return ret;
-	}
-
-	return 0;
-}
-
-static const struct sh_pfc_soc_operations sh73a0_pfc_ops = {
-	.init = sh73a0_pinmux_soc_init,
-	.get_bias = sh73a0_pinmux_get_bias,
-	.set_bias = sh73a0_pinmux_set_bias,
-};
-
-const struct sh_pfc_soc_info sh73a0_pinmux_info = {
-	.name = "sh73a0_pfc",
-	.ops = &sh73a0_pfc_ops,
-
-	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups,
-	.nr_groups = ARRAY_SIZE(pinmux_groups),
-	.functions = pinmux_functions,
-	.nr_functions = ARRAY_SIZE(pinmux_functions),
-
-	.cfg_regs = pinmux_config_regs,
-	.data_regs = pinmux_data_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-
-	.gpio_irq = pinmux_irqs,
-	.gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
deleted file mode 100644
index 37bcae6b3208..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c
+++ /dev/null
@@ -1,1203 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * SH7720 Pinmux
- *
- *  Copyright (C) 2008  Magnus Damm
- */
-
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <cpu/sh7720.h>
-
-#include "sh_pfc.h"
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
-	PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA,
-	PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
-	PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA,
-	PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
-	PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA,
-	PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
-	PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA,
-	PTE6_DATA, PTE5_DATA, PTE4_DATA,
-	PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA,
-	PTF6_DATA, PTF5_DATA, PTF4_DATA,
-	PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA,
-	PTG6_DATA, PTG5_DATA, PTG4_DATA,
-	PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA,
-	PTH6_DATA, PTH5_DATA, PTH4_DATA,
-	PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
-	PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
-	PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA,
-	PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
-	PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, PTL3_DATA,
-	PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
-	PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
-	PTP4_DATA, PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA,
-	PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
-	PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
-	PTS4_DATA, PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
-	PTT4_DATA, PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
-	PTU4_DATA, PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
-	PTV4_DATA, PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA,
-	PINMUX_DATA_END,
-
-	PINMUX_INPUT_BEGIN,
-	PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN,
-	PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN,
-	PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN,
-	PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN,
-	PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN,
-	PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN,
-	PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN,
-	PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN,
-	PTE6_IN, PTE5_IN, PTE4_IN,
-	PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN,
-	PTF6_IN, PTF5_IN, PTF4_IN,
-	PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN,
-	PTG6_IN, PTG5_IN, PTG4_IN,
-	PTG3_IN, PTG2_IN, PTG1_IN, PTG0_IN,
-	PTH6_IN, PTH5_IN, PTH4_IN,
-	PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN,
-	PTJ6_IN, PTJ5_IN, PTJ4_IN,
-	PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN,
-	PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN,
-	PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN, PTL3_IN,
-	PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN,
-	PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
-	PTP4_IN, PTP3_IN, PTP2_IN, PTP1_IN, PTP0_IN,
-	PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN,
-	PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN,
-	PTS4_IN, PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN,
-	PTT4_IN, PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN,
-	PTU4_IN, PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
-	PTV4_IN, PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
-	PINMUX_INPUT_END,
-
-	PINMUX_OUTPUT_BEGIN,
-	PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT,
-	PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT,
-	PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
-	PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT,
-	PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT,
-	PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT,
-	PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT,
-	PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT,
-	PTE4_OUT, PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT,
-	PTF0_OUT,
-	PTG6_OUT, PTG5_OUT, PTG4_OUT,
-	PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT,
-	PTH6_OUT, PTH5_OUT, PTH4_OUT,
-	PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
-	PTJ6_OUT, PTJ5_OUT, PTJ4_OUT,
-	PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT,
-	PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT,
-	PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT, PTL3_OUT,
-	PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT,
-	PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
-	PTP4_OUT, PTP3_OUT, PTP2_OUT, PTP1_OUT, PTP0_OUT,
-	PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT,
-	PTR3_OUT, PTR2_OUT, PTR1_OUT, PTR0_OUT,
-	PTS4_OUT, PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT,
-	PTT4_OUT, PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT,
-	PTU4_OUT, PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT,
-	PTV4_OUT, PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT,
-	PINMUX_OUTPUT_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN,
-	PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN,
-	PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN,
-	PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN,
-	PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN,
-	PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN,
-	PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN,
-	PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN,
-	PTE6_FN, PTE5_FN, PTE4_FN,
-	PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN,
-	PTF6_FN, PTF5_FN, PTF4_FN,
-	PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN,
-	PTG6_FN, PTG5_FN, PTG4_FN,
-	PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN,
-	PTH6_FN, PTH5_FN, PTH4_FN,
-	PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN,
-	PTJ6_FN, PTJ5_FN, PTJ4_FN,
-	PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN,
-	PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN,
-	PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN, PTL3_FN,
-	PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN,
-	PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN,
-	PTP4_FN, PTP3_FN, PTP2_FN, PTP1_FN, PTP0_FN,
-	PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN,
-	PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN,
-	PTS4_FN, PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN,
-	PTT4_FN, PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN,
-	PTU4_FN, PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN,
-	PTV4_FN, PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN,
-
-	PSELA_1_0_00, PSELA_1_0_01, PSELA_1_0_10,
-	PSELA_3_2_00, PSELA_3_2_01, PSELA_3_2_10, PSELA_3_2_11,
-	PSELA_5_4_00, PSELA_5_4_01, PSELA_5_4_10, PSELA_5_4_11,
-	PSELA_7_6_00, PSELA_7_6_01, PSELA_7_6_10,
-	PSELA_9_8_00, PSELA_9_8_01, PSELA_9_8_10,
-	PSELA_11_10_00, PSELA_11_10_01, PSELA_11_10_10,
-	PSELA_13_12_00, PSELA_13_12_10,
-	PSELA_15_14_00, PSELA_15_14_10,
-	PSELB_9_8_00, PSELB_9_8_11,
-	PSELB_11_10_00, PSELB_11_10_01, PSELB_11_10_10, PSELB_11_10_11,
-	PSELB_13_12_00, PSELB_13_12_01, PSELB_13_12_10, PSELB_13_12_11,
-	PSELB_15_14_00, PSELB_15_14_11,
-	PSELC_9_8_00, PSELC_9_8_10,
-	PSELC_11_10_00, PSELC_11_10_10,
-	PSELC_13_12_00,	PSELC_13_12_01,	PSELC_13_12_10,
-	PSELC_15_14_00,	PSELC_15_14_01,	PSELC_15_14_10,
-	PSELD_1_0_00, PSELD_1_0_10,
-	PSELD_11_10_00,	PSELD_11_10_01,
-	PSELD_15_14_00,	PSELD_15_14_01,	PSELD_15_14_10,
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-	D31_MARK, D30_MARK, D29_MARK, D28_MARK,
-	D27_MARK, D26_MARK, D25_MARK, D24_MARK,
-	D23_MARK, D22_MARK, D21_MARK, D20_MARK,
-	D19_MARK, D18_MARK, D17_MARK, D16_MARK,
-	IOIS16_MARK, RAS_MARK, CAS_MARK, CKE_MARK,
-	CS5B_CE1A_MARK, CS6B_CE1B_MARK,
-	A25_MARK, A24_MARK, A23_MARK, A22_MARK,
-	A21_MARK, A20_MARK, A19_MARK, A0_MARK,
-	REFOUT_MARK, IRQOUT_MARK,
-	LCD_DATA15_MARK, LCD_DATA14_MARK,
-	LCD_DATA13_MARK, LCD_DATA12_MARK,
-	LCD_DATA11_MARK, LCD_DATA10_MARK,
-	LCD_DATA9_MARK, LCD_DATA8_MARK,
-	LCD_DATA7_MARK, LCD_DATA6_MARK,
-	LCD_DATA5_MARK, LCD_DATA4_MARK,
-	LCD_DATA3_MARK, LCD_DATA2_MARK,
-	LCD_DATA1_MARK, LCD_DATA0_MARK,
-	LCD_M_DISP_MARK,
-	LCD_CL1_MARK, LCD_CL2_MARK,
-	LCD_DON_MARK, LCD_FLM_MARK,
-	LCD_VEPWC_MARK, LCD_VCPWC_MARK,
-	AFE_RXIN_MARK, AFE_RDET_MARK,
-	AFE_FS_MARK, AFE_TXOUT_MARK,
-	AFE_SCLK_MARK, AFE_RLYCNT_MARK,
-	AFE_HC1_MARK,
-	IIC_SCL_MARK, IIC_SDA_MARK,
-	DA1_MARK, DA0_MARK,
-	AN3_MARK, AN2_MARK, AN1_MARK, AN0_MARK, ADTRG_MARK,
-	USB1D_RCV_MARK, USB1D_TXSE0_MARK,
-	USB1D_TXDPLS_MARK, USB1D_DMNS_MARK,
-	USB1D_DPLS_MARK, USB1D_SPEED_MARK,
-	USB1D_TXENL_MARK,
-	USB2_PWR_EN_MARK, USB1_PWR_EN_USBF_UPLUP_MARK, USB1D_SUSPEND_MARK,
-	IRQ5_MARK, IRQ4_MARK,
-	IRQ3_IRL3_MARK, IRQ2_IRL2_MARK,
-	IRQ1_IRL1_MARK, IRQ0_IRL0_MARK,
-	PCC_REG_MARK, PCC_DRV_MARK,
-	PCC_BVD2_MARK, PCC_BVD1_MARK,
-	PCC_CD2_MARK, PCC_CD1_MARK,
-	PCC_RESET_MARK, PCC_RDY_MARK,
-	PCC_VS2_MARK, PCC_VS1_MARK,
-	AUDATA3_MARK, AUDATA2_MARK, AUDATA1_MARK, AUDATA0_MARK,
-	AUDCK_MARK, AUDSYNC_MARK, ASEBRKAK_MARK, TRST_MARK,
-	TMS_MARK, TDO_MARK, TDI_MARK, TCK_MARK,
-	DACK1_MARK, DREQ1_MARK, DACK0_MARK, DREQ0_MARK,
-	TEND1_MARK, TEND0_MARK,
-	SIOF0_SYNC_MARK, SIOF0_MCLK_MARK,
-	SIOF0_TXD_MARK, SIOF0_RXD_MARK,
-	SIOF0_SCK_MARK,
-	SIOF1_SYNC_MARK, SIOF1_MCLK_MARK,
-	SIOF1_TXD_MARK, SIOF1_RXD_MARK,
-	SIOF1_SCK_MARK,
-	SCIF0_TXD_MARK, SCIF0_RXD_MARK,
-	SCIF0_RTS_MARK, SCIF0_CTS_MARK, SCIF0_SCK_MARK,
-	SCIF1_TXD_MARK, SCIF1_RXD_MARK,
-	SCIF1_RTS_MARK, SCIF1_CTS_MARK, SCIF1_SCK_MARK,
-	TPU_TO1_MARK, TPU_TO0_MARK,
-	TPU_TI3B_MARK, TPU_TI3A_MARK,
-	TPU_TI2B_MARK, TPU_TI2A_MARK,
-	TPU_TO3_MARK, TPU_TO2_MARK,
-	SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK,
-	MMC_DAT_MARK, MMC_CMD_MARK,
-	MMC_CLK_MARK, MMC_VDDON_MARK,
-	MMC_ODMOD_MARK,
-	STATUS0_MARK, STATUS1_MARK,
-	PINMUX_MARK_END,
-};
-
-static const u16 pinmux_data[] = {
-	/* PTA GPIO */
-	PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
-	PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
-	PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT),
-	PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT),
-	PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT),
-	PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT),
-	PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT),
-	PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT),
-
-	/* PTB GPIO */
-	PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT),
-	PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT),
-	PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT),
-	PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT),
-	PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT),
-	PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT),
-	PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT),
-	PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT),
-
-	/* PTC GPIO */
-	PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT),
-	PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT),
-	PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT),
-	PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT),
-	PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT),
-	PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT),
-	PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT),
-	PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT),
-
-	/* PTD GPIO */
-	PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT),
-	PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT),
-	PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT),
-	PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT),
-	PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT),
-	PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT),
-	PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT),
-	PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT),
-
-	/* PTE GPIO */
-	PINMUX_DATA(PTE6_DATA, PTE6_IN),
-	PINMUX_DATA(PTE5_DATA, PTE5_IN),
-	PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT),
-	PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT),
-	PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT),
-	PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT),
-	PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT),
-
-	/* PTF GPIO */
-	PINMUX_DATA(PTF6_DATA, PTF6_IN),
-	PINMUX_DATA(PTF5_DATA, PTF5_IN),
-	PINMUX_DATA(PTF4_DATA, PTF4_IN),
-	PINMUX_DATA(PTF3_DATA, PTF3_IN),
-	PINMUX_DATA(PTF2_DATA, PTF2_IN),
-	PINMUX_DATA(PTF1_DATA, PTF1_IN),
-	PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT),
-
-	/* PTG GPIO */
-	PINMUX_DATA(PTG6_DATA, PTG6_IN, PTG6_OUT),
-	PINMUX_DATA(PTG5_DATA, PTG5_IN, PTG5_OUT),
-	PINMUX_DATA(PTG4_DATA, PTG4_IN, PTG4_OUT),
-	PINMUX_DATA(PTG3_DATA, PTG3_IN, PTG3_OUT),
-	PINMUX_DATA(PTG2_DATA, PTG2_IN, PTG2_OUT),
-	PINMUX_DATA(PTG1_DATA, PTG1_IN, PTG1_OUT),
-	PINMUX_DATA(PTG0_DATA, PTG0_IN, PTG0_OUT),
-
-	/* PTH GPIO */
-	PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT),
-	PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT),
-	PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT),
-	PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT),
-	PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT),
-	PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT),
-	PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT),
-
-	/* PTJ GPIO */
-	PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT),
-	PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT),
-	PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT),
-	PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT),
-	PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT),
-	PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT),
-	PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT),
-
-	/* PTK GPIO */
-	PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT),
-	PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT),
-	PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT),
-	PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT),
-
-	/* PTL GPIO */
-	PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT),
-	PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT),
-	PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT),
-	PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT),
-	PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT),
-
-	/* PTM GPIO */
-	PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT),
-	PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT),
-	PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT),
-	PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT),
-	PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT),
-	PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT),
-	PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT),
-	PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT),
-
-	/* PTP GPIO */
-	PINMUX_DATA(PTP4_DATA, PTP4_IN, PTP4_OUT),
-	PINMUX_DATA(PTP3_DATA, PTP3_IN, PTP3_OUT),
-	PINMUX_DATA(PTP2_DATA, PTP2_IN, PTP2_OUT),
-	PINMUX_DATA(PTP1_DATA, PTP1_IN, PTP1_OUT),
-	PINMUX_DATA(PTP0_DATA, PTP0_IN, PTP0_OUT),
-
-	/* PTR GPIO */
-	PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT),
-	PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT),
-	PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT),
-	PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT),
-	PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_OUT),
-	PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_OUT),
-	PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT),
-	PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT),
-
-	/* PTS GPIO */
-	PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT),
-	PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT),
-	PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT),
-	PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT),
-	PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT),
-
-	/* PTT GPIO */
-	PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT),
-	PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT),
-	PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT),
-	PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT),
-	PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT),
-
-	/* PTU GPIO */
-	PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT),
-	PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT),
-	PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT),
-	PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT),
-	PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT),
-
-	/* PTV GPIO */
-	PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT),
-	PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT),
-	PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT),
-	PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT),
-	PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT),
-
-	/* PTA FN */
-	PINMUX_DATA(D23_MARK, PTA7_FN),
-	PINMUX_DATA(D22_MARK, PTA6_FN),
-	PINMUX_DATA(D21_MARK, PTA5_FN),
-	PINMUX_DATA(D20_MARK, PTA4_FN),
-	PINMUX_DATA(D19_MARK, PTA3_FN),
-	PINMUX_DATA(D18_MARK, PTA2_FN),
-	PINMUX_DATA(D17_MARK, PTA1_FN),
-	PINMUX_DATA(D16_MARK, PTA0_FN),
-
-	/* PTB FN */
-	PINMUX_DATA(D31_MARK, PTB7_FN),
-	PINMUX_DATA(D30_MARK, PTB6_FN),
-	PINMUX_DATA(D29_MARK, PTB5_FN),
-	PINMUX_DATA(D28_MARK, PTB4_FN),
-	PINMUX_DATA(D27_MARK, PTB3_FN),
-	PINMUX_DATA(D26_MARK, PTB2_FN),
-	PINMUX_DATA(D25_MARK, PTB1_FN),
-	PINMUX_DATA(D24_MARK, PTB0_FN),
-
-	/* PTC FN */
-	PINMUX_DATA(LCD_DATA7_MARK, PTC7_FN),
-	PINMUX_DATA(LCD_DATA6_MARK, PTC6_FN),
-	PINMUX_DATA(LCD_DATA5_MARK, PTC5_FN),
-	PINMUX_DATA(LCD_DATA4_MARK, PTC4_FN),
-	PINMUX_DATA(LCD_DATA3_MARK, PTC3_FN),
-	PINMUX_DATA(LCD_DATA2_MARK, PTC2_FN),
-	PINMUX_DATA(LCD_DATA1_MARK, PTC1_FN),
-	PINMUX_DATA(LCD_DATA0_MARK, PTC0_FN),
-
-	/* PTD FN */
-	PINMUX_DATA(LCD_DATA15_MARK, PTD7_FN),
-	PINMUX_DATA(LCD_DATA14_MARK, PTD6_FN),
-	PINMUX_DATA(LCD_DATA13_MARK, PTD5_FN),
-	PINMUX_DATA(LCD_DATA12_MARK, PTD4_FN),
-	PINMUX_DATA(LCD_DATA11_MARK, PTD3_FN),
-	PINMUX_DATA(LCD_DATA10_MARK, PTD2_FN),
-	PINMUX_DATA(LCD_DATA9_MARK, PTD1_FN),
-	PINMUX_DATA(LCD_DATA8_MARK, PTD0_FN),
-
-	/* PTE FN */
-	PINMUX_DATA(IIC_SCL_MARK, PSELB_9_8_00, PTE6_FN),
-	PINMUX_DATA(AFE_RXIN_MARK, PSELB_9_8_11, PTE6_FN),
-	PINMUX_DATA(IIC_SDA_MARK, PSELB_9_8_00, PTE5_FN),
-	PINMUX_DATA(AFE_RDET_MARK, PSELB_9_8_11, PTE5_FN),
-	PINMUX_DATA(LCD_M_DISP_MARK, PTE4_FN),
-	PINMUX_DATA(LCD_CL1_MARK, PTE3_FN),
-	PINMUX_DATA(LCD_CL2_MARK, PTE2_FN),
-	PINMUX_DATA(LCD_DON_MARK, PTE1_FN),
-	PINMUX_DATA(LCD_FLM_MARK, PTE0_FN),
-
-	/* PTF FN */
-	PINMUX_DATA(DA1_MARK, PTF6_FN),
-	PINMUX_DATA(DA0_MARK, PTF5_FN),
-	PINMUX_DATA(AN3_MARK, PTF4_FN),
-	PINMUX_DATA(AN2_MARK, PTF3_FN),
-	PINMUX_DATA(AN1_MARK, PTF2_FN),
-	PINMUX_DATA(AN0_MARK, PTF1_FN),
-	PINMUX_DATA(ADTRG_MARK, PTF0_FN),
-
-	/* PTG FN */
-	PINMUX_DATA(USB1D_RCV_MARK, PSELA_3_2_00, PTG6_FN),
-	PINMUX_DATA(AFE_FS_MARK, PSELA_3_2_01, PTG6_FN),
-	PINMUX_DATA(PCC_REG_MARK, PSELA_3_2_10, PTG6_FN),
-	PINMUX_DATA(IRQ5_MARK, PSELA_3_2_11, PTG6_FN),
-	PINMUX_DATA(USB1D_TXSE0_MARK, PSELA_5_4_00, PTG5_FN),
-	PINMUX_DATA(AFE_TXOUT_MARK, PSELA_5_4_01, PTG5_FN),
-	PINMUX_DATA(PCC_DRV_MARK, PSELA_5_4_10, PTG5_FN),
-	PINMUX_DATA(IRQ4_MARK, PSELA_5_4_11, PTG5_FN),
-	PINMUX_DATA(USB1D_TXDPLS_MARK, PSELA_7_6_00, PTG4_FN),
-	PINMUX_DATA(AFE_SCLK_MARK, PSELA_7_6_01, PTG4_FN),
-	PINMUX_DATA(IOIS16_MARK, PSELA_7_6_10, PTG4_FN),
-	PINMUX_DATA(USB1D_DMNS_MARK, PSELA_9_8_00, PTG3_FN),
-	PINMUX_DATA(AFE_RLYCNT_MARK, PSELA_9_8_01, PTG3_FN),
-	PINMUX_DATA(PCC_BVD2_MARK, PSELA_9_8_10, PTG3_FN),
-	PINMUX_DATA(USB1D_DPLS_MARK, PSELA_11_10_00, PTG2_FN),
-	PINMUX_DATA(AFE_HC1_MARK, PSELA_11_10_01, PTG2_FN),
-	PINMUX_DATA(PCC_BVD1_MARK, PSELA_11_10_10, PTG2_FN),
-	PINMUX_DATA(USB1D_SPEED_MARK, PSELA_13_12_00, PTG1_FN),
-	PINMUX_DATA(PCC_CD2_MARK, PSELA_13_12_10, PTG1_FN),
-	PINMUX_DATA(USB1D_TXENL_MARK, PSELA_15_14_00, PTG0_FN),
-	PINMUX_DATA(PCC_CD1_MARK, PSELA_15_14_10, PTG0_FN),
-
-	/* PTH FN */
-	PINMUX_DATA(RAS_MARK, PTH6_FN),
-	PINMUX_DATA(CAS_MARK, PTH5_FN),
-	PINMUX_DATA(CKE_MARK, PTH4_FN),
-	PINMUX_DATA(STATUS1_MARK, PTH3_FN),
-	PINMUX_DATA(STATUS0_MARK, PTH2_FN),
-	PINMUX_DATA(USB2_PWR_EN_MARK, PTH1_FN),
-	PINMUX_DATA(USB1_PWR_EN_USBF_UPLUP_MARK, PTH0_FN),
-
-	/* PTJ FN */
-	PINMUX_DATA(AUDCK_MARK, PTJ6_FN),
-	PINMUX_DATA(ASEBRKAK_MARK, PTJ5_FN),
-	PINMUX_DATA(AUDATA3_MARK, PTJ4_FN),
-	PINMUX_DATA(AUDATA2_MARK, PTJ3_FN),
-	PINMUX_DATA(AUDATA1_MARK, PTJ2_FN),
-	PINMUX_DATA(AUDATA0_MARK, PTJ1_FN),
-	PINMUX_DATA(AUDSYNC_MARK, PTJ0_FN),
-
-	/* PTK FN */
-	PINMUX_DATA(PCC_RESET_MARK, PTK3_FN),
-	PINMUX_DATA(PCC_RDY_MARK, PTK2_FN),
-	PINMUX_DATA(PCC_VS2_MARK, PTK1_FN),
-	PINMUX_DATA(PCC_VS1_MARK, PTK0_FN),
-
-	/* PTL FN */
-	PINMUX_DATA(TRST_MARK, PTL7_FN),
-	PINMUX_DATA(TMS_MARK, PTL6_FN),
-	PINMUX_DATA(TDO_MARK, PTL5_FN),
-	PINMUX_DATA(TDI_MARK, PTL4_FN),
-	PINMUX_DATA(TCK_MARK, PTL3_FN),
-
-	/* PTM FN */
-	PINMUX_DATA(DREQ1_MARK, PTM7_FN),
-	PINMUX_DATA(DREQ0_MARK, PTM6_FN),
-	PINMUX_DATA(DACK1_MARK, PTM5_FN),
-	PINMUX_DATA(DACK0_MARK, PTM4_FN),
-	PINMUX_DATA(TEND1_MARK, PTM3_FN),
-	PINMUX_DATA(TEND0_MARK, PTM2_FN),
-	PINMUX_DATA(CS5B_CE1A_MARK, PTM1_FN),
-	PINMUX_DATA(CS6B_CE1B_MARK, PTM0_FN),
-
-	/* PTP FN */
-	PINMUX_DATA(USB1D_SUSPEND_MARK, PSELA_1_0_00, PTP4_FN),
-	PINMUX_DATA(REFOUT_MARK, PSELA_1_0_01, PTP4_FN),
-	PINMUX_DATA(IRQOUT_MARK, PSELA_1_0_10, PTP4_FN),
-	PINMUX_DATA(IRQ3_IRL3_MARK, PTP3_FN),
-	PINMUX_DATA(IRQ2_IRL2_MARK, PTP2_FN),
-	PINMUX_DATA(IRQ1_IRL1_MARK, PTP1_FN),
-	PINMUX_DATA(IRQ0_IRL0_MARK, PTP0_FN),
-
-	/* PTR FN */
-	PINMUX_DATA(A25_MARK, PTR7_FN),
-	PINMUX_DATA(A24_MARK, PTR6_FN),
-	PINMUX_DATA(A23_MARK, PTR5_FN),
-	PINMUX_DATA(A22_MARK, PTR4_FN),
-	PINMUX_DATA(A21_MARK, PTR3_FN),
-	PINMUX_DATA(A20_MARK, PTR2_FN),
-	PINMUX_DATA(A19_MARK, PTR1_FN),
-	PINMUX_DATA(A0_MARK, PTR0_FN),
-
-	/* PTS FN */
-	PINMUX_DATA(SIOF0_SYNC_MARK, PTS4_FN),
-	PINMUX_DATA(SIOF0_MCLK_MARK, PTS3_FN),
-	PINMUX_DATA(SIOF0_TXD_MARK, PTS2_FN),
-	PINMUX_DATA(SIOF0_RXD_MARK, PTS1_FN),
-	PINMUX_DATA(SIOF0_SCK_MARK, PTS0_FN),
-
-	/* PTT FN */
-	PINMUX_DATA(SCIF0_CTS_MARK, PSELB_15_14_00, PTT4_FN),
-	PINMUX_DATA(TPU_TO1_MARK, PSELB_15_14_11, PTT4_FN),
-	PINMUX_DATA(SCIF0_RTS_MARK, PSELB_15_14_00, PTT3_FN),
-	PINMUX_DATA(TPU_TO0_MARK, PSELB_15_14_11, PTT3_FN),
-	PINMUX_DATA(SCIF0_TXD_MARK, PTT2_FN),
-	PINMUX_DATA(SCIF0_RXD_MARK, PTT1_FN),
-	PINMUX_DATA(SCIF0_SCK_MARK, PTT0_FN),
-
-	/* PTU FN */
-	PINMUX_DATA(SIOF1_SYNC_MARK, PTU4_FN),
-	PINMUX_DATA(SIOF1_MCLK_MARK, PSELD_11_10_00, PTU3_FN),
-	PINMUX_DATA(TPU_TI3B_MARK, PSELD_11_10_01, PTU3_FN),
-	PINMUX_DATA(SIOF1_TXD_MARK, PSELD_15_14_00, PTU2_FN),
-	PINMUX_DATA(TPU_TI3A_MARK, PSELD_15_14_01, PTU2_FN),
-	PINMUX_DATA(MMC_DAT_MARK, PSELD_15_14_10, PTU2_FN),
-	PINMUX_DATA(SIOF1_RXD_MARK, PSELC_13_12_00, PTU1_FN),
-	PINMUX_DATA(TPU_TI2B_MARK, PSELC_13_12_01, PTU1_FN),
-	PINMUX_DATA(MMC_CMD_MARK, PSELC_13_12_10, PTU1_FN),
-	PINMUX_DATA(SIOF1_SCK_MARK, PSELC_15_14_00, PTU0_FN),
-	PINMUX_DATA(TPU_TI2A_MARK, PSELC_15_14_01, PTU0_FN),
-	PINMUX_DATA(MMC_CLK_MARK, PSELC_15_14_10, PTU0_FN),
-
-	/* PTV FN */
-	PINMUX_DATA(SCIF1_CTS_MARK, PSELB_11_10_00, PTV4_FN),
-	PINMUX_DATA(TPU_TO3_MARK, PSELB_11_10_01, PTV4_FN),
-	PINMUX_DATA(MMC_VDDON_MARK, PSELB_11_10_10, PTV4_FN),
-	PINMUX_DATA(LCD_VEPWC_MARK, PSELB_11_10_11, PTV4_FN),
-	PINMUX_DATA(SCIF1_RTS_MARK, PSELB_13_12_00, PTV3_FN),
-	PINMUX_DATA(TPU_TO2_MARK, PSELB_13_12_01, PTV3_FN),
-	PINMUX_DATA(MMC_ODMOD_MARK, PSELB_13_12_10, PTV3_FN),
-	PINMUX_DATA(LCD_VCPWC_MARK, PSELB_13_12_11, PTV3_FN),
-	PINMUX_DATA(SCIF1_TXD_MARK, PSELC_9_8_00, PTV2_FN),
-	PINMUX_DATA(SIM_D_MARK, PSELC_9_8_10, PTV2_FN),
-	PINMUX_DATA(SCIF1_RXD_MARK, PSELC_11_10_00, PTV1_FN),
-	PINMUX_DATA(SIM_RST_MARK, PSELC_11_10_10, PTV1_FN),
-	PINMUX_DATA(SCIF1_SCK_MARK, PSELD_1_0_00, PTV0_FN),
-	PINMUX_DATA(SIM_CLK_MARK, PSELD_1_0_10, PTV0_FN),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	/* PTA */
-	PINMUX_GPIO(PTA7),
-	PINMUX_GPIO(PTA6),
-	PINMUX_GPIO(PTA5),
-	PINMUX_GPIO(PTA4),
-	PINMUX_GPIO(PTA3),
-	PINMUX_GPIO(PTA2),
-	PINMUX_GPIO(PTA1),
-	PINMUX_GPIO(PTA0),
-
-	/* PTB */
-	PINMUX_GPIO(PTB7),
-	PINMUX_GPIO(PTB6),
-	PINMUX_GPIO(PTB5),
-	PINMUX_GPIO(PTB4),
-	PINMUX_GPIO(PTB3),
-	PINMUX_GPIO(PTB2),
-	PINMUX_GPIO(PTB1),
-	PINMUX_GPIO(PTB0),
-
-	/* PTC */
-	PINMUX_GPIO(PTC7),
-	PINMUX_GPIO(PTC6),
-	PINMUX_GPIO(PTC5),
-	PINMUX_GPIO(PTC4),
-	PINMUX_GPIO(PTC3),
-	PINMUX_GPIO(PTC2),
-	PINMUX_GPIO(PTC1),
-	PINMUX_GPIO(PTC0),
-
-	/* PTD */
-	PINMUX_GPIO(PTD7),
-	PINMUX_GPIO(PTD6),
-	PINMUX_GPIO(PTD5),
-	PINMUX_GPIO(PTD4),
-	PINMUX_GPIO(PTD3),
-	PINMUX_GPIO(PTD2),
-	PINMUX_GPIO(PTD1),
-	PINMUX_GPIO(PTD0),
-
-	/* PTE */
-	PINMUX_GPIO(PTE6),
-	PINMUX_GPIO(PTE5),
-	PINMUX_GPIO(PTE4),
-	PINMUX_GPIO(PTE3),
-	PINMUX_GPIO(PTE2),
-	PINMUX_GPIO(PTE1),
-	PINMUX_GPIO(PTE0),
-
-	/* PTF */
-	PINMUX_GPIO(PTF6),
-	PINMUX_GPIO(PTF5),
-	PINMUX_GPIO(PTF4),
-	PINMUX_GPIO(PTF3),
-	PINMUX_GPIO(PTF2),
-	PINMUX_GPIO(PTF1),
-	PINMUX_GPIO(PTF0),
-
-	/* PTG */
-	PINMUX_GPIO(PTG6),
-	PINMUX_GPIO(PTG5),
-	PINMUX_GPIO(PTG4),
-	PINMUX_GPIO(PTG3),
-	PINMUX_GPIO(PTG2),
-	PINMUX_GPIO(PTG1),
-	PINMUX_GPIO(PTG0),
-
-	/* PTH */
-	PINMUX_GPIO(PTH6),
-	PINMUX_GPIO(PTH5),
-	PINMUX_GPIO(PTH4),
-	PINMUX_GPIO(PTH3),
-	PINMUX_GPIO(PTH2),
-	PINMUX_GPIO(PTH1),
-	PINMUX_GPIO(PTH0),
-
-	/* PTJ */
-	PINMUX_GPIO(PTJ6),
-	PINMUX_GPIO(PTJ5),
-	PINMUX_GPIO(PTJ4),
-	PINMUX_GPIO(PTJ3),
-	PINMUX_GPIO(PTJ2),
-	PINMUX_GPIO(PTJ1),
-	PINMUX_GPIO(PTJ0),
-
-	/* PTK */
-	PINMUX_GPIO(PTK3),
-	PINMUX_GPIO(PTK2),
-	PINMUX_GPIO(PTK1),
-	PINMUX_GPIO(PTK0),
-
-	/* PTL */
-	PINMUX_GPIO(PTL7),
-	PINMUX_GPIO(PTL6),
-	PINMUX_GPIO(PTL5),
-	PINMUX_GPIO(PTL4),
-	PINMUX_GPIO(PTL3),
-
-	/* PTM */
-	PINMUX_GPIO(PTM7),
-	PINMUX_GPIO(PTM6),
-	PINMUX_GPIO(PTM5),
-	PINMUX_GPIO(PTM4),
-	PINMUX_GPIO(PTM3),
-	PINMUX_GPIO(PTM2),
-	PINMUX_GPIO(PTM1),
-	PINMUX_GPIO(PTM0),
-
-	/* PTP */
-	PINMUX_GPIO(PTP4),
-	PINMUX_GPIO(PTP3),
-	PINMUX_GPIO(PTP2),
-	PINMUX_GPIO(PTP1),
-	PINMUX_GPIO(PTP0),
-
-	/* PTR */
-	PINMUX_GPIO(PTR7),
-	PINMUX_GPIO(PTR6),
-	PINMUX_GPIO(PTR5),
-	PINMUX_GPIO(PTR4),
-	PINMUX_GPIO(PTR3),
-	PINMUX_GPIO(PTR2),
-	PINMUX_GPIO(PTR1),
-	PINMUX_GPIO(PTR0),
-
-	/* PTS */
-	PINMUX_GPIO(PTS4),
-	PINMUX_GPIO(PTS3),
-	PINMUX_GPIO(PTS2),
-	PINMUX_GPIO(PTS1),
-	PINMUX_GPIO(PTS0),
-
-	/* PTT */
-	PINMUX_GPIO(PTT4),
-	PINMUX_GPIO(PTT3),
-	PINMUX_GPIO(PTT2),
-	PINMUX_GPIO(PTT1),
-	PINMUX_GPIO(PTT0),
-
-	/* PTU */
-	PINMUX_GPIO(PTU4),
-	PINMUX_GPIO(PTU3),
-	PINMUX_GPIO(PTU2),
-	PINMUX_GPIO(PTU1),
-	PINMUX_GPIO(PTU0),
-
-	/* PTV */
-	PINMUX_GPIO(PTV4),
-	PINMUX_GPIO(PTV3),
-	PINMUX_GPIO(PTV2),
-	PINMUX_GPIO(PTV1),
-	PINMUX_GPIO(PTV0),
-};
-
-#define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-	/* BSC */
-	GPIO_FN(D31),
-	GPIO_FN(D30),
-	GPIO_FN(D29),
-	GPIO_FN(D28),
-	GPIO_FN(D27),
-	GPIO_FN(D26),
-	GPIO_FN(D25),
-	GPIO_FN(D24),
-	GPIO_FN(D23),
-	GPIO_FN(D22),
-	GPIO_FN(D21),
-	GPIO_FN(D20),
-	GPIO_FN(D19),
-	GPIO_FN(D18),
-	GPIO_FN(D17),
-	GPIO_FN(D16),
-	GPIO_FN(IOIS16),
-	GPIO_FN(RAS),
-	GPIO_FN(CAS),
-	GPIO_FN(CKE),
-	GPIO_FN(CS5B_CE1A),
-	GPIO_FN(CS6B_CE1B),
-	GPIO_FN(A25),
-	GPIO_FN(A24),
-	GPIO_FN(A23),
-	GPIO_FN(A22),
-	GPIO_FN(A21),
-	GPIO_FN(A20),
-	GPIO_FN(A19),
-	GPIO_FN(A0),
-	GPIO_FN(REFOUT),
-	GPIO_FN(IRQOUT),
-
-	/* LCDC */
-	GPIO_FN(LCD_DATA15),
-	GPIO_FN(LCD_DATA14),
-	GPIO_FN(LCD_DATA13),
-	GPIO_FN(LCD_DATA12),
-	GPIO_FN(LCD_DATA11),
-	GPIO_FN(LCD_DATA10),
-	GPIO_FN(LCD_DATA9),
-	GPIO_FN(LCD_DATA8),
-	GPIO_FN(LCD_DATA7),
-	GPIO_FN(LCD_DATA6),
-	GPIO_FN(LCD_DATA5),
-	GPIO_FN(LCD_DATA4),
-	GPIO_FN(LCD_DATA3),
-	GPIO_FN(LCD_DATA2),
-	GPIO_FN(LCD_DATA1),
-	GPIO_FN(LCD_DATA0),
-	GPIO_FN(LCD_M_DISP),
-	GPIO_FN(LCD_CL1),
-	GPIO_FN(LCD_CL2),
-	GPIO_FN(LCD_DON),
-	GPIO_FN(LCD_FLM),
-	GPIO_FN(LCD_VEPWC),
-	GPIO_FN(LCD_VCPWC),
-
-	/* AFEIF */
-	GPIO_FN(AFE_RXIN),
-	GPIO_FN(AFE_RDET),
-	GPIO_FN(AFE_FS),
-	GPIO_FN(AFE_TXOUT),
-	GPIO_FN(AFE_SCLK),
-	GPIO_FN(AFE_RLYCNT),
-	GPIO_FN(AFE_HC1),
-
-	/* IIC */
-	GPIO_FN(IIC_SCL),
-	GPIO_FN(IIC_SDA),
-
-	/* DAC */
-	GPIO_FN(DA1),
-	GPIO_FN(DA0),
-
-	/* ADC */
-	GPIO_FN(AN3),
-	GPIO_FN(AN2),
-	GPIO_FN(AN1),
-	GPIO_FN(AN0),
-	GPIO_FN(ADTRG),
-
-	/* USB */
-	GPIO_FN(USB1D_RCV),
-	GPIO_FN(USB1D_TXSE0),
-	GPIO_FN(USB1D_TXDPLS),
-	GPIO_FN(USB1D_DMNS),
-	GPIO_FN(USB1D_DPLS),
-	GPIO_FN(USB1D_SPEED),
-	GPIO_FN(USB1D_TXENL),
-
-	GPIO_FN(USB2_PWR_EN),
-	GPIO_FN(USB1_PWR_EN_USBF_UPLUP),
-	GPIO_FN(USB1D_SUSPEND),
-
-	/* INTC */
-	GPIO_FN(IRQ5),
-	GPIO_FN(IRQ4),
-	GPIO_FN(IRQ3_IRL3),
-	GPIO_FN(IRQ2_IRL2),
-	GPIO_FN(IRQ1_IRL1),
-	GPIO_FN(IRQ0_IRL0),
-
-	/* PCC */
-	GPIO_FN(PCC_REG),
-	GPIO_FN(PCC_DRV),
-	GPIO_FN(PCC_BVD2),
-	GPIO_FN(PCC_BVD1),
-	GPIO_FN(PCC_CD2),
-	GPIO_FN(PCC_CD1),
-	GPIO_FN(PCC_RESET),
-	GPIO_FN(PCC_RDY),
-	GPIO_FN(PCC_VS2),
-	GPIO_FN(PCC_VS1),
-
-	/* HUDI */
-	GPIO_FN(AUDATA3),
-	GPIO_FN(AUDATA2),
-	GPIO_FN(AUDATA1),
-	GPIO_FN(AUDATA0),
-	GPIO_FN(AUDCK),
-	GPIO_FN(AUDSYNC),
-	GPIO_FN(ASEBRKAK),
-	GPIO_FN(TRST),
-	GPIO_FN(TMS),
-	GPIO_FN(TDO),
-	GPIO_FN(TDI),
-	GPIO_FN(TCK),
-
-	/* DMAC */
-	GPIO_FN(DACK1),
-	GPIO_FN(DREQ1),
-	GPIO_FN(DACK0),
-	GPIO_FN(DREQ0),
-	GPIO_FN(TEND1),
-	GPIO_FN(TEND0),
-
-	/* SIOF0 */
-	GPIO_FN(SIOF0_SYNC),
-	GPIO_FN(SIOF0_MCLK),
-	GPIO_FN(SIOF0_TXD),
-	GPIO_FN(SIOF0_RXD),
-	GPIO_FN(SIOF0_SCK),
-
-	/* SIOF1 */
-	GPIO_FN(SIOF1_SYNC),
-	GPIO_FN(SIOF1_MCLK),
-	GPIO_FN(SIOF1_TXD),
-	GPIO_FN(SIOF1_RXD),
-	GPIO_FN(SIOF1_SCK),
-
-	/* SCIF0 */
-	GPIO_FN(SCIF0_TXD),
-	GPIO_FN(SCIF0_RXD),
-	GPIO_FN(SCIF0_RTS),
-	GPIO_FN(SCIF0_CTS),
-	GPIO_FN(SCIF0_SCK),
-
-	/* SCIF1 */
-	GPIO_FN(SCIF1_TXD),
-	GPIO_FN(SCIF1_RXD),
-	GPIO_FN(SCIF1_RTS),
-	GPIO_FN(SCIF1_CTS),
-	GPIO_FN(SCIF1_SCK),
-
-	/* TPU */
-	GPIO_FN(TPU_TO1),
-	GPIO_FN(TPU_TO0),
-	GPIO_FN(TPU_TI3B),
-	GPIO_FN(TPU_TI3A),
-	GPIO_FN(TPU_TI2B),
-	GPIO_FN(TPU_TI2A),
-	GPIO_FN(TPU_TO3),
-	GPIO_FN(TPU_TO2),
-
-	/* SIM */
-	GPIO_FN(SIM_D),
-	GPIO_FN(SIM_CLK),
-	GPIO_FN(SIM_RST),
-
-	/* MMC */
-	GPIO_FN(MMC_DAT),
-	GPIO_FN(MMC_CMD),
-	GPIO_FN(MMC_CLK),
-	GPIO_FN(MMC_VDDON),
-	GPIO_FN(MMC_ODMOD),
-
-	/* SYSC */
-	GPIO_FN(STATUS0),
-	GPIO_FN(STATUS1),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2, GROUP(
-		PTA7_FN, PTA7_OUT, 0, PTA7_IN,
-		PTA6_FN, PTA6_OUT, 0, PTA6_IN,
-		PTA5_FN, PTA5_OUT, 0, PTA5_IN,
-		PTA4_FN, PTA4_OUT, 0, PTA4_IN,
-		PTA3_FN, PTA3_OUT, 0, PTA3_IN,
-		PTA2_FN, PTA2_OUT, 0, PTA2_IN,
-		PTA1_FN, PTA1_OUT, 0, PTA1_IN,
-		PTA0_FN, PTA0_OUT, 0, PTA0_IN ))
-	},
-	{ PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2, GROUP(
-		PTB7_FN, PTB7_OUT, 0, PTB7_IN,
-		PTB6_FN, PTB6_OUT, 0, PTB6_IN,
-		PTB5_FN, PTB5_OUT, 0, PTB5_IN,
-		PTB4_FN, PTB4_OUT, 0, PTB4_IN,
-		PTB3_FN, PTB3_OUT, 0, PTB3_IN,
-		PTB2_FN, PTB2_OUT, 0, PTB2_IN,
-		PTB1_FN, PTB1_OUT, 0, PTB1_IN,
-		PTB0_FN, PTB0_OUT, 0, PTB0_IN ))
-	},
-	{ PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2, GROUP(
-		PTC7_FN, PTC7_OUT, 0, PTC7_IN,
-		PTC6_FN, PTC6_OUT, 0, PTC6_IN,
-		PTC5_FN, PTC5_OUT, 0, PTC5_IN,
-		PTC4_FN, PTC4_OUT, 0, PTC4_IN,
-		PTC3_FN, PTC3_OUT, 0, PTC3_IN,
-		PTC2_FN, PTC2_OUT, 0, PTC2_IN,
-		PTC1_FN, PTC1_OUT, 0, PTC1_IN,
-		PTC0_FN, PTC0_OUT, 0, PTC0_IN ))
-	},
-	{ PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2, GROUP(
-		PTD7_FN, PTD7_OUT, 0, PTD7_IN,
-		PTD6_FN, PTD6_OUT, 0, PTD6_IN,
-		PTD5_FN, PTD5_OUT, 0, PTD5_IN,
-		PTD4_FN, PTD4_OUT, 0, PTD4_IN,
-		PTD3_FN, PTD3_OUT, 0, PTD3_IN,
-		PTD2_FN, PTD2_OUT, 0, PTD2_IN,
-		PTD1_FN, PTD1_OUT, 0, PTD1_IN,
-		PTD0_FN, PTD0_OUT, 0, PTD0_IN ))
-	},
-	{ PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2, GROUP(
-		0, 0, 0, 0,
-		PTE6_FN, 0, 0, PTE6_IN,
-		PTE5_FN, 0, 0, PTE5_IN,
-		PTE4_FN, PTE4_OUT, 0, PTE4_IN,
-		PTE3_FN, PTE3_OUT, 0, PTE3_IN,
-		PTE2_FN, PTE2_OUT, 0, PTE2_IN,
-		PTE1_FN, PTE1_OUT, 0, PTE1_IN,
-		PTE0_FN, PTE0_OUT, 0, PTE0_IN ))
-	},
-	{ PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2, GROUP(
-		0, 0, 0, 0,
-		PTF6_FN, 0, 0, PTF6_IN,
-		PTF5_FN, 0, 0, PTF5_IN,
-		PTF4_FN, 0, 0, PTF4_IN,
-		PTF3_FN, 0, 0, PTF3_IN,
-		PTF2_FN, 0, 0, PTF2_IN,
-		PTF1_FN, 0, 0, PTF1_IN,
-		PTF0_FN, 0, 0, PTF0_IN ))
-	},
-	{ PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2, GROUP(
-		0, 0, 0, 0,
-		PTG6_FN, PTG6_OUT, 0, PTG6_IN,
-		PTG5_FN, PTG5_OUT, 0, PTG5_IN,
-		PTG4_FN, PTG4_OUT, 0, PTG4_IN,
-		PTG3_FN, PTG3_OUT, 0, PTG3_IN,
-		PTG2_FN, PTG2_OUT, 0, PTG2_IN,
-		PTG1_FN, PTG1_OUT, 0, PTG1_IN,
-		PTG0_FN, PTG0_OUT, 0, PTG0_IN ))
-	},
-	{ PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2, GROUP(
-		0, 0, 0, 0,
-		PTH6_FN, PTH6_OUT, 0, PTH6_IN,
-		PTH5_FN, PTH5_OUT, 0, PTH5_IN,
-		PTH4_FN, PTH4_OUT, 0, PTH4_IN,
-		PTH3_FN, PTH3_OUT, 0, PTH3_IN,
-		PTH2_FN, PTH2_OUT, 0, PTH2_IN,
-		PTH1_FN, PTH1_OUT, 0, PTH1_IN,
-		PTH0_FN, PTH0_OUT, 0, PTH0_IN ))
-	},
-	{ PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2, GROUP(
-		0, 0, 0, 0,
-		PTJ6_FN, PTJ6_OUT, 0, PTJ6_IN,
-		PTJ5_FN, PTJ5_OUT, 0, PTJ5_IN,
-		PTJ4_FN, PTJ4_OUT, 0, PTJ4_IN,
-		PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN,
-		PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN,
-		PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN,
-		PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN ))
-	},
-	{ PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PTK3_FN, PTK3_OUT, 0, PTK3_IN,
-		PTK2_FN, PTK2_OUT, 0, PTK2_IN,
-		PTK1_FN, PTK1_OUT, 0, PTK1_IN,
-		PTK0_FN, PTK0_OUT, 0, PTK0_IN ))
-	},
-	{ PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2, GROUP(
-		PTL7_FN, PTL7_OUT, 0, PTL7_IN,
-		PTL6_FN, PTL6_OUT, 0, PTL6_IN,
-		PTL5_FN, PTL5_OUT, 0, PTL5_IN,
-		PTL4_FN, PTL4_OUT, 0, PTL4_IN,
-		PTL3_FN, PTL3_OUT, 0, PTL3_IN,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2, GROUP(
-		PTM7_FN, PTM7_OUT, 0, PTM7_IN,
-		PTM6_FN, PTM6_OUT, 0, PTM6_IN,
-		PTM5_FN, PTM5_OUT, 0, PTM5_IN,
-		PTM4_FN, PTM4_OUT, 0, PTM4_IN,
-		PTM3_FN, PTM3_OUT, 0, PTM3_IN,
-		PTM2_FN, PTM2_OUT, 0, PTM2_IN,
-		PTM1_FN, PTM1_OUT, 0, PTM1_IN,
-		PTM0_FN, PTM0_OUT, 0, PTM0_IN ))
-	},
-	{ PINMUX_CFG_REG("PPCR", 0xa4050118, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PTP4_FN, PTP4_OUT, 0, PTP4_IN,
-		PTP3_FN, PTP3_OUT, 0, PTP3_IN,
-		PTP2_FN, PTP2_OUT, 0, PTP2_IN,
-		PTP1_FN, PTP1_OUT, 0, PTP1_IN,
-		PTP0_FN, PTP0_OUT, 0, PTP0_IN ))
-	},
-	{ PINMUX_CFG_REG("PRCR", 0xa405011a, 16, 2, GROUP(
-		PTR7_FN, PTR7_OUT, 0, PTR7_IN,
-		PTR6_FN, PTR6_OUT, 0, PTR6_IN,
-		PTR5_FN, PTR5_OUT, 0, PTR5_IN,
-		PTR4_FN, PTR4_OUT, 0, PTR4_IN,
-		PTR3_FN, PTR3_OUT, 0, PTR3_IN,
-		PTR2_FN, PTR2_OUT, 0, PTR2_IN,
-		PTR1_FN, PTR1_OUT, 0, PTR1_IN,
-		PTR0_FN, PTR0_OUT, 0, PTR0_IN ))
-	},
-	{ PINMUX_CFG_REG("PSCR", 0xa405011c, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PTS4_FN, PTS4_OUT, 0, PTS4_IN,
-		PTS3_FN, PTS3_OUT, 0, PTS3_IN,
-		PTS2_FN, PTS2_OUT, 0, PTS2_IN,
-		PTS1_FN, PTS1_OUT, 0, PTS1_IN,
-		PTS0_FN, PTS0_OUT, 0, PTS0_IN ))
-	},
-	{ PINMUX_CFG_REG("PTCR", 0xa405011e, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PTT4_FN, PTT4_OUT, 0, PTT4_IN,
-		PTT3_FN, PTT3_OUT, 0, PTT3_IN,
-		PTT2_FN, PTT2_OUT, 0, PTT2_IN,
-		PTT1_FN, PTT1_OUT, 0, PTT1_IN,
-		PTT0_FN, PTT0_OUT, 0, PTT0_IN ))
-	},
-	{ PINMUX_CFG_REG("PUCR", 0xa4050120, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PTU4_FN, PTU4_OUT, 0, PTU4_IN,
-		PTU3_FN, PTU3_OUT, 0, PTU3_IN,
-		PTU2_FN, PTU2_OUT, 0, PTU2_IN,
-		PTU1_FN, PTU1_OUT, 0, PTU1_IN,
-		PTU0_FN, PTU0_OUT, 0, PTU0_IN ))
-	},
-	{ PINMUX_CFG_REG("PVCR", 0xa4050122, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PTV4_FN, PTV4_OUT, 0, PTV4_IN,
-		PTV3_FN, PTV3_OUT, 0, PTV3_IN,
-		PTV2_FN, PTV2_OUT, 0, PTV2_IN,
-		PTV1_FN, PTV1_OUT, 0, PTV1_IN,
-		PTV0_FN, PTV0_OUT, 0, PTV0_IN ))
-	},
-	{}
-};
-
-static const struct pinmux_data_reg pinmux_data_regs[] = {
-	{ PINMUX_DATA_REG("PADR", 0xa4050140, 8, GROUP(
-		PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
-		PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PBDR", 0xa4050142, 8, GROUP(
-		PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
-		PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PCDR", 0xa4050144, 8, GROUP(
-		PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
-		PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PDDR", 0xa4050126, 8, GROUP(
-		PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
-		PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PEDR", 0xa4050148, 8, GROUP(
-		0, PTE6_DATA, PTE5_DATA, PTE4_DATA,
-		PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PFDR", 0xa405014a, 8, GROUP(
-		0, PTF6_DATA, PTF5_DATA, PTF4_DATA,
-		PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PGDR", 0xa405014c, 8, GROUP(
-		0, PTG6_DATA, PTG5_DATA, PTG4_DATA,
-		PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PHDR", 0xa405014e, 8, GROUP(
-		0, PTH6_DATA, PTH5_DATA, PTH4_DATA,
-		PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PJDR", 0xa4050150, 8, GROUP(
-		0, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
-		PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PKDR", 0xa4050152, 8, GROUP(
-		0, 0, 0, 0,
-		PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PLDR", 0xa4050154, 8, GROUP(
-		PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
-		PTL3_DATA, 0, 0, 0 ))
-	},
-	{ PINMUX_DATA_REG("PMDR", 0xa4050156, 8, GROUP(
-		PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
-		PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PPDR", 0xa4050158, 8, GROUP(
-		0, 0, 0, PTP4_DATA,
-		PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PRDR", 0xa405015a, 8, GROUP(
-		PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
-		PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PSDR", 0xa405015c, 8, GROUP(
-		0, 0, 0, PTS4_DATA,
-		PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PTDR", 0xa405015e, 8, GROUP(
-		0, 0, 0, PTT4_DATA,
-		PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PUDR", 0xa4050160, 8, GROUP(
-		0, 0, 0, PTU4_DATA,
-		PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PVDR", 0xa4050162, 8, GROUP(
-		0, 0, 0, PTV4_DATA,
-		PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
-	},
-	{ },
-};
-
-const struct sh_pfc_soc_info sh7720_pinmux_info = {
-	.name = "sh7720_pfc",
-	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.func_gpios = pinmux_func_gpios,
-	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
-	.cfg_regs = pinmux_config_regs,
-	.data_regs = pinmux_data_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
deleted file mode 100644
index 95295be4e703..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c
+++ /dev/null
@@ -1,1747 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <cpu/sh7722.h>
-
-#include "sh_pfc.h"
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
-	PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA,
-	PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
-	PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA,
-	PTC7_DATA, PTC5_DATA, PTC4_DATA, PTC3_DATA, PTC2_DATA, PTC0_DATA,
-	PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
-	PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA,
-	PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA, PTE1_DATA, PTE0_DATA,
-	PTF6_DATA, PTF5_DATA, PTF4_DATA,
-	PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA,
-	PTG4_DATA, PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA,
-	PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
-	PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
-	PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ1_DATA, PTJ0_DATA,
-	PTK6_DATA, PTK5_DATA, PTK4_DATA,
-	PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
-	PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
-	PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA,
-	PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
-	PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
-	PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
-	PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA,
-	PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
-	PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA,
-	PTR4_DATA, PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
-	PTS4_DATA, PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
-	PTT4_DATA, PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
-	PTU4_DATA, PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
-	PTV4_DATA, PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA,
-	PTW6_DATA, PTW5_DATA, PTW4_DATA,
-	PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA,
-	PTX6_DATA, PTX5_DATA, PTX4_DATA,
-	PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA,
-	PTY6_DATA, PTY5_DATA, PTY4_DATA,
-	PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA,
-	PTZ5_DATA, PTZ4_DATA, PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA,
-	PINMUX_DATA_END,
-
-	PINMUX_INPUT_BEGIN,
-	PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN,
-	PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN,
-	PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN,
-	PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN,
-	PTC7_IN, PTC5_IN, PTC4_IN, PTC3_IN, PTC2_IN, PTC0_IN,
-	PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN, PTD3_IN, PTD2_IN, PTD1_IN,
-	PTE7_IN, PTE6_IN, PTE5_IN, PTE4_IN, PTE1_IN, PTE0_IN,
-	PTF6_IN, PTF5_IN, PTF4_IN, PTF3_IN, PTF2_IN, PTF1_IN,
-	PTH6_IN, PTH5_IN, PTH1_IN, PTH0_IN,
-	PTJ1_IN, PTJ0_IN,
-	PTK6_IN, PTK5_IN, PTK4_IN, PTK3_IN, PTK2_IN, PTK0_IN,
-	PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN,
-	PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN,
-	PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN,
-	PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
-	PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN,
-	PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN,
-	PTQ5_IN, PTQ4_IN, PTQ3_IN, PTQ2_IN, PTQ0_IN,
-	PTR2_IN,
-	PTS4_IN, PTS2_IN, PTS1_IN,
-	PTT4_IN, PTT3_IN, PTT2_IN, PTT1_IN,
-	PTU4_IN, PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
-	PTV4_IN, PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
-	PTW6_IN, PTW4_IN, PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN,
-	PTX6_IN, PTX5_IN, PTX4_IN, PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN,
-	PTY5_IN, PTY4_IN, PTY3_IN, PTY2_IN, PTY0_IN,
-	PTZ5_IN, PTZ4_IN, PTZ3_IN, PTZ2_IN, PTZ1_IN,
-	PINMUX_INPUT_END,
-
-	PINMUX_OUTPUT_BEGIN,
-	PTA7_OUT, PTA5_OUT,
-	PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
-	PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT,
-	PTC4_OUT, PTC3_OUT, PTC2_OUT, PTC0_OUT,
-	PTD6_OUT, PTD5_OUT, PTD4_OUT,
-	PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT,
-	PTE7_OUT, PTE6_OUT, PTE5_OUT, PTE4_OUT, PTE1_OUT, PTE0_OUT,
-	PTF6_OUT, PTF5_OUT, PTF4_OUT, PTF3_OUT, PTF2_OUT, PTF0_OUT,
-	PTG4_OUT, PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT,
-	PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT,
-	PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
-	PTJ7_OUT, PTJ6_OUT, PTJ5_OUT, PTJ1_OUT, PTJ0_OUT,
-	PTK6_OUT, PTK5_OUT, PTK4_OUT, PTK3_OUT, PTK1_OUT, PTK0_OUT,
-	PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT,
-	PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT,
-	PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT,
-	PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
-	PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT,
-	PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT,	PTQ6_OUT, PTQ5_OUT, PTQ4_OUT,
-	PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT,
-	PTR4_OUT, PTR3_OUT, PTR1_OUT, PTR0_OUT,
-	PTS3_OUT, PTS2_OUT, PTS0_OUT,
-	PTT4_OUT, PTT3_OUT, PTT2_OUT, PTT0_OUT,
-	PTU4_OUT, PTU3_OUT, PTU2_OUT, PTU0_OUT,
-	PTV4_OUT, PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT,
-	PTW5_OUT, PTW4_OUT, PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT,
-	PTX6_OUT, PTX5_OUT, PTX4_OUT, PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT,
-	PTY5_OUT, PTY4_OUT, PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT,
-	PINMUX_OUTPUT_END,
-
-	PINMUX_MARK_BEGIN,
-	SCIF0_TXD_MARK, SCIF0_RXD_MARK,
-	SCIF0_RTS_MARK, SCIF0_CTS_MARK, SCIF0_SCK_MARK,
-	SCIF1_TXD_MARK, SCIF1_RXD_MARK,
-	SCIF1_RTS_MARK, SCIF1_CTS_MARK, SCIF1_SCK_MARK,
-	SCIF2_TXD_MARK, SCIF2_RXD_MARK,
-	SCIF2_RTS_MARK, SCIF2_CTS_MARK, SCIF2_SCK_MARK,
-	SIOTXD_MARK, SIORXD_MARK,
-	SIOD_MARK, SIOSTRB0_MARK, SIOSTRB1_MARK,
-	SIOSCK_MARK, SIOMCK_MARK,
-	VIO_D15_MARK, VIO_D14_MARK, VIO_D13_MARK, VIO_D12_MARK,
-	VIO_D11_MARK, VIO_D10_MARK, VIO_D9_MARK, VIO_D8_MARK,
-	VIO_D7_MARK, VIO_D6_MARK, VIO_D5_MARK, VIO_D4_MARK,
-	VIO_D3_MARK, VIO_D2_MARK, VIO_D1_MARK, VIO_D0_MARK,
-	VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK, VIO_FLD_MARK,
-	VIO_CKO_MARK, VIO_STEX_MARK, VIO_STEM_MARK, VIO_VD2_MARK,
-	VIO_HD2_MARK, VIO_CLK2_MARK,
-	LCDD23_MARK, LCDD22_MARK, LCDD21_MARK, LCDD20_MARK,
-	LCDD19_MARK, LCDD18_MARK, LCDD17_MARK, LCDD16_MARK,
-	LCDD15_MARK, LCDD14_MARK, LCDD13_MARK, LCDD12_MARK,
-	LCDD11_MARK, LCDD10_MARK, LCDD9_MARK, LCDD8_MARK,
-	LCDD7_MARK, LCDD6_MARK, LCDD5_MARK, LCDD4_MARK,
-	LCDD3_MARK, LCDD2_MARK, LCDD1_MARK, LCDD0_MARK,
-	LCDLCLK_MARK, LCDDON_MARK, LCDVCPWC_MARK, LCDVEPWC_MARK,
-	LCDVSYN_MARK, LCDDCK_MARK, LCDHSYN_MARK, LCDDISP_MARK,
-	LCDRS_MARK, LCDCS_MARK, LCDWR_MARK, LCDRD_MARK,
-	LCDDON2_MARK, LCDVCPWC2_MARK, LCDVEPWC2_MARK, LCDVSYN2_MARK,
-	LCDCS2_MARK,
-	IOIS16_MARK, A25_MARK, A24_MARK, A23_MARK, A22_MARK,
-	BS_MARK, CS6B_CE1B_MARK, WAIT_MARK, CS6A_CE2B_MARK,
-	HPD63_MARK, HPD62_MARK, HPD61_MARK, HPD60_MARK,
-	HPD59_MARK, HPD58_MARK, HPD57_MARK, HPD56_MARK,
-	HPD55_MARK, HPD54_MARK, HPD53_MARK, HPD52_MARK,
-	HPD51_MARK, HPD50_MARK, HPD49_MARK, HPD48_MARK,
-	HPDQM7_MARK, HPDQM6_MARK, HPDQM5_MARK, HPDQM4_MARK,
-	IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK,
-	IRQ4_MARK, IRQ5_MARK, IRQ6_MARK, IRQ7_MARK,
-	SDHICD_MARK, SDHIWP_MARK, SDHID3_MARK, SDHID2_MARK,
-	SDHID1_MARK, SDHID0_MARK, SDHICMD_MARK, SDHICLK_MARK,
-	SIUAOLR_MARK, SIUAOBT_MARK, SIUAISLD_MARK, SIUAILR_MARK,
-	SIUAIBT_MARK, SIUAOSLD_MARK, SIUMCKA_MARK, SIUFCKA_MARK,
-	SIUBOLR_MARK, SIUBOBT_MARK, SIUBISLD_MARK, SIUBILR_MARK,
-	SIUBIBT_MARK, SIUBOSLD_MARK, SIUMCKB_MARK, SIUFCKB_MARK,
-	AUDSYNC_MARK, AUDATA3_MARK, AUDATA2_MARK, AUDATA1_MARK,	AUDATA0_MARK,
-	DACK_MARK, DREQ0_MARK,
-	DV_CLKI_MARK, DV_CLK_MARK, DV_HSYNC_MARK, DV_VSYNC_MARK,
-	DV_D15_MARK, DV_D14_MARK, DV_D13_MARK, DV_D12_MARK,
-	DV_D11_MARK, DV_D10_MARK, DV_D9_MARK, DV_D8_MARK,
-	DV_D7_MARK, DV_D6_MARK, DV_D5_MARK, DV_D4_MARK,
-	DV_D3_MARK, DV_D2_MARK, DV_D1_MARK, DV_D0_MARK,
-	STATUS0_MARK, PDSTATUS_MARK,
-	SIOF0_MCK_MARK, SIOF0_SCK_MARK,
-	SIOF0_SYNC_MARK, SIOF0_SS1_MARK, SIOF0_SS2_MARK,
-	SIOF0_TXD_MARK,	SIOF0_RXD_MARK,
-	SIOF1_MCK_MARK, SIOF1_SCK_MARK,
-	SIOF1_SYNC_MARK, SIOF1_SS1_MARK, SIOF1_SS2_MARK,
-	SIOF1_TXD_MARK, SIOF1_RXD_MARK,
-	SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK,
-	TS_SDAT_MARK, TS_SCK_MARK, TS_SDEN_MARK, TS_SPSYNC_MARK,
-	IRDA_IN_MARK, IRDA_OUT_MARK,
-	TPUTO_MARK,
-	FCE_MARK, NAF7_MARK, NAF6_MARK, NAF5_MARK, NAF4_MARK,
-	NAF3_MARK, NAF2_MARK, NAF1_MARK, NAF0_MARK, FCDE_MARK,
-	FOE_MARK, FSC_MARK, FWE_MARK, FRB_MARK,
-	KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, KEYIN4_MARK,
-	KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
-	KEYOUT4_IN6_MARK, KEYOUT5_IN5_MARK,
-	PINMUX_MARK_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	VIO_D7_SCIF1_SCK, VIO_D6_SCIF1_RXD, VIO_D5_SCIF1_TXD, VIO_D4,
-	VIO_D3, VIO_D2, VIO_D1, VIO_D0_LCDLCLK,
-	HPD55, HPD54, HPD53, HPD52, HPD51, HPD50, HPD49, HPD48,
-	IOIS16, HPDQM7, HPDQM6, HPDQM5, HPDQM4,
-	SDHICD, SDHIWP, SDHID3, IRQ2_SDHID2, SDHID1, SDHID0, SDHICMD, SDHICLK,
-	A25, A24, A23, A22, IRQ5, IRQ4_BS,
-	PTF6, SIOSCK_SIUBOBT, SIOSTRB1_SIUBOLR,
-	SIOSTRB0_SIUBIBT, SIOD_SIUBILR, SIORXD_SIUBISLD, SIOTXD_SIUBOSLD,
-	AUDSYNC, AUDATA3, AUDATA2, AUDATA1, AUDATA0,
-	LCDVCPWC_LCDVCPWC2, LCDVSYN2_DACK, LCDVSYN, LCDDISP_LCDRS,
-	LCDHSYN_LCDCS, LCDDON_LCDDON2, LCDD17_DV_HSYNC, LCDD16_DV_VSYNC,
-	STATUS0, PDSTATUS, IRQ1, IRQ0,
-	SIUAILR_SIOF1_SS2, SIUAIBT_SIOF1_SS1, SIUAOLR_SIOF1_SYNC,
-	SIUAOBT_SIOF1_SCK, SIUAISLD_SIOF1_RXD, SIUAOSLD_SIOF1_TXD, PTK0,
-	LCDD15_DV_D15, LCDD14_DV_D14, LCDD13_DV_D13, LCDD12_DV_D12,
-	LCDD11_DV_D11, LCDD10_DV_D10, LCDD9_DV_D9, LCDD8_DV_D8,
-	LCDD7_DV_D7, LCDD6_DV_D6, LCDD5_DV_D5, LCDD4_DV_D4,
-	LCDD3_DV_D3, LCDD2_DV_D2, LCDD1_DV_D1, LCDD0_DV_D0,
-	HPD63, HPD62, HPD61, HPD60, HPD59, HPD58, HPD57, HPD56,
-	SIOF0_SS2_SIM_RST, SIOF0_SS1_TS_SPSYNC, SIOF0_SYNC_TS_SDEN,
-	SIOF0_SCK_TS_SCK, PTQ2, PTQ1, PTQ0,
-	LCDRD, CS6B_CE1B_LCDCS2, WAIT, LCDDCK_LCDWR, LCDVEPWC_LCDVEPWC2,
-	SCIF0_CTS_SIUAISPD, SCIF0_RTS_SIUAOSPD,
-	SCIF0_SCK_TPUTO, SCIF0_RXD, SCIF0_TXD,
-	FOE_VIO_VD2, FWE, FSC, DREQ0, FCDE,
-	NAF2_VIO_D10, NAF1_VIO_D9, NAF0_VIO_D8,
-	FRB_VIO_CLK2, FCE_VIO_HD2,
-	NAF7_VIO_D15, NAF6_VIO_D14, NAF5_VIO_D13, NAF4_VIO_D12, NAF3_VIO_D11,
-	VIO_FLD_SCIF2_CTS, VIO_CKO_SCIF2_RTS, VIO_STEX_SCIF2_SCK,
-	VIO_STEM_SCIF2_TXD, VIO_HD_SCIF2_RXD,
-	VIO_VD_SCIF1_CTS, VIO_CLK_SCIF1_RTS,
-	CS6A_CE2B, LCDD23, LCDD22, LCDD21, LCDD20,
-	LCDD19_DV_CLKI, LCDD18_DV_CLK,
-	KEYOUT5_IN5, KEYOUT4_IN6, KEYOUT3, KEYOUT2, KEYOUT1, KEYOUT0,
-	KEYIN4_IRQ7, KEYIN3, KEYIN2, KEYIN1, KEYIN0_IRQ6,
-
-	PSA15_KEYIN0, PSA15_IRQ6, PSA14_KEYIN4, PSA14_IRQ7,
-	PSA9_IRQ4, PSA9_BS, PSA4_IRQ2, PSA4_SDHID2,
-	PSB15_SIOTXD, PSB15_SIUBOSLD, PSB14_SIORXD, PSB14_SIUBISLD,
-	PSB13_SIOD, PSB13_SIUBILR, PSB12_SIOSTRB0, PSB12_SIUBIBT,
-	PSB11_SIOSTRB1, PSB11_SIUBOLR, PSB10_SIOSCK, PSB10_SIUBOBT,
-	PSB9_SIOMCK, PSB9_SIUMCKB, PSB8_SIOF0_MCK, PSB8_IRQ3,
-	PSB7_SIOF0_TXD, PSB7_IRDA_OUT, PSB6_SIOF0_RXD, PSB6_IRDA_IN,
-	PSB5_SIOF0_SCK, PSB5_TS_SCK, PSB4_SIOF0_SYNC, PSB4_TS_SDEN,
-	PSB3_SIOF0_SS1, PSB3_TS_SPSYNC, PSB2_SIOF0_SS2, PSB2_SIM_RST,
-	PSB1_SIUMCKA, PSB1_SIOF1_MCK, PSB0_SIUAOSLD, PSB0_SIOF1_TXD,
-	PSC15_SIUAISLD, PSC15_SIOF1_RXD, PSC14_SIUAOBT, PSC14_SIOF1_SCK,
-	PSC13_SIUAOLR, PSC13_SIOF1_SYNC, PSC12_SIUAIBT, PSC12_SIOF1_SS1,
-	PSC11_SIUAILR, PSC11_SIOF1_SS2, PSC0_NAF, PSC0_VIO,
-	PSD13_VIO, PSD13_SCIF2, PSD12_VIO, PSD12_SCIF1,
-	PSD11_VIO, PSD11_SCIF1, PSD10_VIO_D0, PSD10_LCDLCLK,
-	PSD9_SIOMCK_SIUMCKB, PSD9_SIUFCKB, PSD8_SCIF0_SCK, PSD8_TPUTO,
-	PSD7_SCIF0_RTS, PSD7_SIUAOSPD, PSD6_SCIF0_CTS, PSD6_SIUAISPD,
-	PSD5_CS6B_CE1B, PSD5_LCDCS2,
-	PSD3_LCDVEPWC_LCDVCPWC, PSD3_LCDVEPWC2_LCDVCPWC2,
-	PSD2_LCDDON, PSD2_LCDDON2, PSD0_LCDD19_LCDD0, PSD0_DV,
-	PSE15_SIOF0_MCK_IRQ3, PSE15_SIM_D,
-	PSE14_SIOF0_TXD_IRDA_OUT, PSE14_SIM_CLK,
-	PSE13_SIOF0_RXD_IRDA_IN, PSE13_TS_SDAT, PSE12_LCDVSYN2, PSE12_DACK,
-	PSE11_SIUMCKA_SIOF1_MCK, PSE11_SIUFCKA,
-	PSE3_FLCTL, PSE3_VIO, PSE2_NAF2, PSE2_VIO_D10,
-	PSE1_NAF1, PSE1_VIO_D9, PSE0_NAF0, PSE0_VIO_D8,
-
-	HIZA14_KEYSC, HIZA14_HIZ,
-	HIZA10_NAF, HIZA10_HIZ,
-	HIZA9_VIO, HIZA9_HIZ,
-	HIZA8_LCDC, HIZA8_HIZ,
-	HIZA7_LCDC, HIZA7_HIZ,
-	HIZA6_LCDC, HIZA6_HIZ,
-	HIZB4_SIUA, HIZB4_HIZ,
-	HIZB1_VIO, HIZB1_HIZ,
-	HIZB0_VIO, HIZB0_HIZ,
-	HIZC15_IRQ7, HIZC15_HIZ,
-	HIZC14_IRQ6, HIZC14_HIZ,
-	HIZC13_IRQ5, HIZC13_HIZ,
-	HIZC12_IRQ4, HIZC12_HIZ,
-	HIZC11_IRQ3, HIZC11_HIZ,
-	HIZC10_IRQ2, HIZC10_HIZ,
-	HIZC9_IRQ1, HIZC9_HIZ,
-	HIZC8_IRQ0, HIZC8_HIZ,
-	MSELB9_VIO, MSELB9_VIO2,
-	MSELB8_RGB, MSELB8_SYS,
-	PINMUX_FUNCTION_END,
-};
-
-static const u16 pinmux_data[] = {
-	/* PTA */
-	PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
-	PINMUX_DATA(PTA6_DATA, PTA6_IN),
-	PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT),
-	PINMUX_DATA(PTA4_DATA, PTA4_IN),
-	PINMUX_DATA(PTA3_DATA, PTA3_IN),
-	PINMUX_DATA(PTA2_DATA, PTA2_IN),
-	PINMUX_DATA(PTA1_DATA, PTA1_IN),
-	PINMUX_DATA(PTA0_DATA, PTA0_IN),
-
-	/* PTB */
-	PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT),
-	PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT),
-	PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT),
-	PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT),
-	PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT),
-	PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT),
-	PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT),
-	PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT),
-
-	/* PTC */
-	PINMUX_DATA(PTC7_DATA, PTC7_IN),
-	PINMUX_DATA(PTC5_DATA, PTC5_IN),
-	PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT),
-	PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT),
-	PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT),
-	PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT),
-
-	/* PTD */
-	PINMUX_DATA(PTD7_DATA, PTD7_IN),
-	PINMUX_DATA(PTD6_DATA, PTD6_OUT, PTD6_IN),
-	PINMUX_DATA(PTD5_DATA, PTD5_OUT, PTD5_IN),
-	PINMUX_DATA(PTD4_DATA, PTD4_OUT, PTD4_IN),
-	PINMUX_DATA(PTD3_DATA, PTD3_OUT, PTD3_IN),
-	PINMUX_DATA(PTD2_DATA, PTD2_OUT, PTD2_IN),
-	PINMUX_DATA(PTD1_DATA, PTD1_OUT, PTD1_IN),
-	PINMUX_DATA(PTD0_DATA, PTD0_OUT),
-
-	/* PTE */
-	PINMUX_DATA(PTE7_DATA, PTE7_OUT, PTE7_IN),
-	PINMUX_DATA(PTE6_DATA, PTE6_OUT, PTE6_IN),
-	PINMUX_DATA(PTE5_DATA, PTE5_OUT, PTE5_IN),
-	PINMUX_DATA(PTE4_DATA, PTE4_OUT, PTE4_IN),
-	PINMUX_DATA(PTE1_DATA, PTE1_OUT, PTE1_IN),
-	PINMUX_DATA(PTE0_DATA, PTE0_OUT, PTE0_IN),
-
-	/* PTF */
-	PINMUX_DATA(PTF6_DATA, PTF6_OUT, PTF6_IN),
-	PINMUX_DATA(PTF5_DATA, PTF5_OUT, PTF5_IN),
-	PINMUX_DATA(PTF4_DATA, PTF4_OUT, PTF4_IN),
-	PINMUX_DATA(PTF3_DATA, PTF3_OUT, PTF3_IN),
-	PINMUX_DATA(PTF2_DATA, PTF2_OUT, PTF2_IN),
-	PINMUX_DATA(PTF1_DATA, PTF1_IN),
-	PINMUX_DATA(PTF0_DATA, PTF0_OUT),
-
-	/* PTG */
-	PINMUX_DATA(PTG4_DATA, PTG4_OUT),
-	PINMUX_DATA(PTG3_DATA, PTG3_OUT),
-	PINMUX_DATA(PTG2_DATA, PTG2_OUT),
-	PINMUX_DATA(PTG1_DATA, PTG1_OUT),
-	PINMUX_DATA(PTG0_DATA, PTG0_OUT),
-
-	/* PTH */
-	PINMUX_DATA(PTH7_DATA, PTH7_OUT),
-	PINMUX_DATA(PTH6_DATA, PTH6_OUT, PTH6_IN),
-	PINMUX_DATA(PTH5_DATA, PTH5_OUT, PTH5_IN),
-	PINMUX_DATA(PTH4_DATA, PTH4_OUT),
-	PINMUX_DATA(PTH3_DATA, PTH3_OUT),
-	PINMUX_DATA(PTH2_DATA, PTH2_OUT),
-	PINMUX_DATA(PTH1_DATA, PTH1_OUT, PTH1_IN),
-	PINMUX_DATA(PTH0_DATA, PTH0_OUT, PTH0_IN),
-
-	/* PTJ */
-	PINMUX_DATA(PTJ7_DATA, PTJ7_OUT),
-	PINMUX_DATA(PTJ6_DATA, PTJ6_OUT),
-	PINMUX_DATA(PTJ5_DATA, PTJ5_OUT),
-	PINMUX_DATA(PTJ1_DATA, PTJ1_OUT, PTJ1_IN),
-	PINMUX_DATA(PTJ0_DATA, PTJ0_OUT, PTJ0_IN),
-
-	/* PTK */
-	PINMUX_DATA(PTK6_DATA, PTK6_OUT, PTK6_IN),
-	PINMUX_DATA(PTK5_DATA, PTK5_OUT, PTK5_IN),
-	PINMUX_DATA(PTK4_DATA, PTK4_OUT, PTK4_IN),
-	PINMUX_DATA(PTK3_DATA, PTK3_OUT, PTK3_IN),
-	PINMUX_DATA(PTK2_DATA, PTK2_IN),
-	PINMUX_DATA(PTK1_DATA, PTK1_OUT),
-	PINMUX_DATA(PTK0_DATA, PTK0_OUT, PTK0_IN),
-
-	/* PTL */
-	PINMUX_DATA(PTL7_DATA, PTL7_OUT, PTL7_IN),
-	PINMUX_DATA(PTL6_DATA, PTL6_OUT, PTL6_IN),
-	PINMUX_DATA(PTL5_DATA, PTL5_OUT, PTL5_IN),
-	PINMUX_DATA(PTL4_DATA, PTL4_OUT, PTL4_IN),
-	PINMUX_DATA(PTL3_DATA, PTL3_OUT, PTL3_IN),
-	PINMUX_DATA(PTL2_DATA, PTL2_OUT, PTL2_IN),
-	PINMUX_DATA(PTL1_DATA, PTL1_OUT, PTL1_IN),
-	PINMUX_DATA(PTL0_DATA, PTL0_OUT, PTL0_IN),
-
-	/* PTM */
-	PINMUX_DATA(PTM7_DATA, PTM7_OUT, PTM7_IN),
-	PINMUX_DATA(PTM6_DATA, PTM6_OUT, PTM6_IN),
-	PINMUX_DATA(PTM5_DATA, PTM5_OUT, PTM5_IN),
-	PINMUX_DATA(PTM4_DATA, PTM4_OUT, PTM4_IN),
-	PINMUX_DATA(PTM3_DATA, PTM3_OUT, PTM3_IN),
-	PINMUX_DATA(PTM2_DATA, PTM2_OUT, PTM2_IN),
-	PINMUX_DATA(PTM1_DATA, PTM1_OUT, PTM1_IN),
-	PINMUX_DATA(PTM0_DATA, PTM0_OUT, PTM0_IN),
-
-	/* PTN */
-	PINMUX_DATA(PTN7_DATA, PTN7_OUT, PTN7_IN),
-	PINMUX_DATA(PTN6_DATA, PTN6_OUT, PTN6_IN),
-	PINMUX_DATA(PTN5_DATA, PTN5_OUT, PTN5_IN),
-	PINMUX_DATA(PTN4_DATA, PTN4_OUT, PTN4_IN),
-	PINMUX_DATA(PTN3_DATA, PTN3_OUT, PTN3_IN),
-	PINMUX_DATA(PTN2_DATA, PTN2_OUT, PTN2_IN),
-	PINMUX_DATA(PTN1_DATA, PTN1_OUT, PTN1_IN),
-	PINMUX_DATA(PTN0_DATA, PTN0_OUT, PTN0_IN),
-
-	/* PTQ */
-	PINMUX_DATA(PTQ6_DATA, PTQ6_OUT),
-	PINMUX_DATA(PTQ5_DATA, PTQ5_OUT, PTQ5_IN),
-	PINMUX_DATA(PTQ4_DATA, PTQ4_OUT, PTQ4_IN),
-	PINMUX_DATA(PTQ3_DATA, PTQ3_OUT, PTQ3_IN),
-	PINMUX_DATA(PTQ2_DATA, PTQ2_IN),
-	PINMUX_DATA(PTQ1_DATA, PTQ1_OUT),
-	PINMUX_DATA(PTQ0_DATA, PTQ0_OUT, PTQ0_IN),
-
-	/* PTR */
-	PINMUX_DATA(PTR4_DATA, PTR4_OUT),
-	PINMUX_DATA(PTR3_DATA, PTR3_OUT),
-	PINMUX_DATA(PTR2_DATA, PTR2_IN),
-	PINMUX_DATA(PTR1_DATA, PTR1_OUT),
-	PINMUX_DATA(PTR0_DATA, PTR0_OUT),
-
-	/* PTS */
-	PINMUX_DATA(PTS4_DATA, PTS4_IN),
-	PINMUX_DATA(PTS3_DATA, PTS3_OUT),
-	PINMUX_DATA(PTS2_DATA, PTS2_OUT, PTS2_IN),
-	PINMUX_DATA(PTS1_DATA, PTS1_IN),
-	PINMUX_DATA(PTS0_DATA, PTS0_OUT),
-
-	/* PTT */
-	PINMUX_DATA(PTT4_DATA, PTT4_OUT, PTT4_IN),
-	PINMUX_DATA(PTT3_DATA, PTT3_OUT, PTT3_IN),
-	PINMUX_DATA(PTT2_DATA, PTT2_OUT, PTT2_IN),
-	PINMUX_DATA(PTT1_DATA, PTT1_IN),
-	PINMUX_DATA(PTT0_DATA, PTT0_OUT),
-
-	/* PTU */
-	PINMUX_DATA(PTU4_DATA, PTU4_OUT, PTU4_IN),
-	PINMUX_DATA(PTU3_DATA, PTU3_OUT, PTU3_IN),
-	PINMUX_DATA(PTU2_DATA, PTU2_OUT, PTU2_IN),
-	PINMUX_DATA(PTU1_DATA, PTU1_IN),
-	PINMUX_DATA(PTU0_DATA, PTU0_OUT, PTU0_IN),
-
-	/* PTV */
-	PINMUX_DATA(PTV4_DATA, PTV4_OUT, PTV4_IN),
-	PINMUX_DATA(PTV3_DATA, PTV3_OUT, PTV3_IN),
-	PINMUX_DATA(PTV2_DATA, PTV2_OUT, PTV2_IN),
-	PINMUX_DATA(PTV1_DATA, PTV1_OUT, PTV1_IN),
-	PINMUX_DATA(PTV0_DATA, PTV0_OUT, PTV0_IN),
-
-	/* PTW */
-	PINMUX_DATA(PTW6_DATA, PTW6_IN),
-	PINMUX_DATA(PTW5_DATA, PTW5_OUT),
-	PINMUX_DATA(PTW4_DATA, PTW4_OUT, PTW4_IN),
-	PINMUX_DATA(PTW3_DATA, PTW3_OUT, PTW3_IN),
-	PINMUX_DATA(PTW2_DATA, PTW2_OUT, PTW2_IN),
-	PINMUX_DATA(PTW1_DATA, PTW1_OUT, PTW1_IN),
-	PINMUX_DATA(PTW0_DATA, PTW0_OUT, PTW0_IN),
-
-	/* PTX */
-	PINMUX_DATA(PTX6_DATA, PTX6_OUT, PTX6_IN),
-	PINMUX_DATA(PTX5_DATA, PTX5_OUT, PTX5_IN),
-	PINMUX_DATA(PTX4_DATA, PTX4_OUT, PTX4_IN),
-	PINMUX_DATA(PTX3_DATA, PTX3_OUT, PTX3_IN),
-	PINMUX_DATA(PTX2_DATA, PTX2_OUT, PTX2_IN),
-	PINMUX_DATA(PTX1_DATA, PTX1_OUT, PTX1_IN),
-	PINMUX_DATA(PTX0_DATA, PTX0_OUT, PTX0_IN),
-
-	/* PTY */
-	PINMUX_DATA(PTY5_DATA, PTY5_OUT, PTY5_IN),
-	PINMUX_DATA(PTY4_DATA, PTY4_OUT, PTY4_IN),
-	PINMUX_DATA(PTY3_DATA, PTY3_OUT, PTY3_IN),
-	PINMUX_DATA(PTY2_DATA, PTY2_OUT, PTY2_IN),
-	PINMUX_DATA(PTY1_DATA, PTY1_OUT),
-	PINMUX_DATA(PTY0_DATA, PTY0_OUT, PTY0_IN),
-
-	/* PTZ */
-	PINMUX_DATA(PTZ5_DATA, PTZ5_IN),
-	PINMUX_DATA(PTZ4_DATA, PTZ4_IN),
-	PINMUX_DATA(PTZ3_DATA, PTZ3_IN),
-	PINMUX_DATA(PTZ2_DATA, PTZ2_IN),
-	PINMUX_DATA(PTZ1_DATA, PTZ1_IN),
-
-	/* SCIF0 */
-	PINMUX_DATA(SCIF0_TXD_MARK, SCIF0_TXD),
-	PINMUX_DATA(SCIF0_RXD_MARK, SCIF0_RXD),
-	PINMUX_DATA(SCIF0_RTS_MARK, PSD7_SCIF0_RTS, SCIF0_RTS_SIUAOSPD),
-	PINMUX_DATA(SCIF0_CTS_MARK, PSD6_SCIF0_CTS, SCIF0_CTS_SIUAISPD),
-	PINMUX_DATA(SCIF0_SCK_MARK, PSD8_SCIF0_SCK, SCIF0_SCK_TPUTO),
-
-	/* SCIF1 */
-	PINMUX_DATA(SCIF1_TXD_MARK, PSD11_SCIF1, VIO_D5_SCIF1_TXD),
-	PINMUX_DATA(SCIF1_RXD_MARK, PSD11_SCIF1, VIO_D6_SCIF1_RXD),
-	PINMUX_DATA(SCIF1_RTS_MARK, PSD12_SCIF1, VIO_CLK_SCIF1_RTS),
-	PINMUX_DATA(SCIF1_CTS_MARK, PSD12_SCIF1, VIO_VD_SCIF1_CTS),
-	PINMUX_DATA(SCIF1_SCK_MARK, PSD11_SCIF1, VIO_D7_SCIF1_SCK),
-
-	/* SCIF2 */
-	PINMUX_DATA(SCIF2_TXD_MARK, PSD13_SCIF2, VIO_STEM_SCIF2_TXD),
-	PINMUX_DATA(SCIF2_RXD_MARK, PSD13_SCIF2, VIO_HD_SCIF2_RXD),
-	PINMUX_DATA(SCIF2_RTS_MARK, PSD13_SCIF2, VIO_CKO_SCIF2_RTS),
-	PINMUX_DATA(SCIF2_CTS_MARK, PSD13_SCIF2, VIO_FLD_SCIF2_CTS),
-	PINMUX_DATA(SCIF2_SCK_MARK, PSD13_SCIF2, VIO_STEX_SCIF2_SCK),
-
-	/* SIO */
-	PINMUX_DATA(SIOTXD_MARK, PSB15_SIOTXD, SIOTXD_SIUBOSLD),
-	PINMUX_DATA(SIORXD_MARK, PSB14_SIORXD, SIORXD_SIUBISLD),
-	PINMUX_DATA(SIOD_MARK, PSB13_SIOD, SIOD_SIUBILR),
-	PINMUX_DATA(SIOSTRB0_MARK, PSB12_SIOSTRB0, SIOSTRB0_SIUBIBT),
-	PINMUX_DATA(SIOSTRB1_MARK, PSB11_SIOSTRB1, SIOSTRB1_SIUBOLR),
-	PINMUX_DATA(SIOSCK_MARK, PSB10_SIOSCK, SIOSCK_SIUBOBT),
-	PINMUX_DATA(SIOMCK_MARK, PSD9_SIOMCK_SIUMCKB, PSB9_SIOMCK, PTF6),
-
-	/* CEU */
-	PINMUX_DATA(VIO_D15_MARK, PSC0_VIO, HIZA10_NAF, NAF7_VIO_D15),
-	PINMUX_DATA(VIO_D14_MARK, PSC0_VIO, HIZA10_NAF, NAF6_VIO_D14),
-	PINMUX_DATA(VIO_D13_MARK, PSC0_VIO, HIZA10_NAF, NAF5_VIO_D13),
-	PINMUX_DATA(VIO_D12_MARK, PSC0_VIO, HIZA10_NAF, NAF4_VIO_D12),
-	PINMUX_DATA(VIO_D11_MARK, PSC0_VIO, HIZA10_NAF, NAF3_VIO_D11),
-	PINMUX_DATA(VIO_D10_MARK, PSE2_VIO_D10, HIZB0_VIO, NAF2_VIO_D10),
-	PINMUX_DATA(VIO_D9_MARK, PSE1_VIO_D9, HIZB0_VIO, NAF1_VIO_D9),
-	PINMUX_DATA(VIO_D8_MARK, PSE0_VIO_D8, HIZB0_VIO, NAF0_VIO_D8),
-	PINMUX_DATA(VIO_D7_MARK, PSD11_VIO, VIO_D7_SCIF1_SCK),
-	PINMUX_DATA(VIO_D6_MARK, PSD11_VIO, VIO_D6_SCIF1_RXD),
-	PINMUX_DATA(VIO_D5_MARK, PSD11_VIO, VIO_D5_SCIF1_TXD),
-	PINMUX_DATA(VIO_D4_MARK, VIO_D4),
-	PINMUX_DATA(VIO_D3_MARK, VIO_D3),
-	PINMUX_DATA(VIO_D2_MARK, VIO_D2),
-	PINMUX_DATA(VIO_D1_MARK, VIO_D1),
-	PINMUX_DATA(VIO_D0_MARK, PSD10_VIO_D0, VIO_D0_LCDLCLK),
-	PINMUX_DATA(VIO_CLK_MARK, PSD12_VIO, MSELB9_VIO, VIO_CLK_SCIF1_RTS),
-	PINMUX_DATA(VIO_VD_MARK, PSD12_VIO, MSELB9_VIO, VIO_VD_SCIF1_CTS),
-	PINMUX_DATA(VIO_HD_MARK, PSD13_VIO, MSELB9_VIO, VIO_HD_SCIF2_RXD),
-	PINMUX_DATA(VIO_FLD_MARK, PSD13_VIO, HIZA9_VIO, VIO_FLD_SCIF2_CTS),
-	PINMUX_DATA(VIO_CKO_MARK, PSD13_VIO, HIZA9_VIO, VIO_CKO_SCIF2_RTS),
-	PINMUX_DATA(VIO_STEX_MARK, PSD13_VIO, HIZA9_VIO, VIO_STEX_SCIF2_SCK),
-	PINMUX_DATA(VIO_STEM_MARK, PSD13_VIO, HIZA9_VIO, VIO_STEM_SCIF2_TXD),
-	PINMUX_DATA(VIO_VD2_MARK, PSE3_VIO, MSELB9_VIO2,
-		    HIZB0_VIO, FOE_VIO_VD2),
-	PINMUX_DATA(VIO_HD2_MARK, PSE3_VIO, MSELB9_VIO2,
-		    HIZB1_VIO, FCE_VIO_HD2),
-	PINMUX_DATA(VIO_CLK2_MARK, PSE3_VIO, MSELB9_VIO2,
-		    HIZB1_VIO, FRB_VIO_CLK2),
-
-	/* LCDC */
-	PINMUX_DATA(LCDD23_MARK, HIZA8_LCDC, LCDD23),
-	PINMUX_DATA(LCDD22_MARK, HIZA8_LCDC, LCDD22),
-	PINMUX_DATA(LCDD21_MARK, HIZA8_LCDC, LCDD21),
-	PINMUX_DATA(LCDD20_MARK, HIZA8_LCDC, LCDD20),
-	PINMUX_DATA(LCDD19_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD19_DV_CLKI),
-	PINMUX_DATA(LCDD18_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD18_DV_CLK),
-	PINMUX_DATA(LCDD17_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC,
-		    LCDD17_DV_HSYNC),
-	PINMUX_DATA(LCDD16_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC,
-		    LCDD16_DV_VSYNC),
-	PINMUX_DATA(LCDD15_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD15_DV_D15),
-	PINMUX_DATA(LCDD14_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD14_DV_D14),
-	PINMUX_DATA(LCDD13_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD13_DV_D13),
-	PINMUX_DATA(LCDD12_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD12_DV_D12),
-	PINMUX_DATA(LCDD11_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD11_DV_D11),
-	PINMUX_DATA(LCDD10_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD10_DV_D10),
-	PINMUX_DATA(LCDD9_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD9_DV_D9),
-	PINMUX_DATA(LCDD8_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD8_DV_D8),
-	PINMUX_DATA(LCDD7_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD7_DV_D7),
-	PINMUX_DATA(LCDD6_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD6_DV_D6),
-	PINMUX_DATA(LCDD5_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD5_DV_D5),
-	PINMUX_DATA(LCDD4_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD4_DV_D4),
-	PINMUX_DATA(LCDD3_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD3_DV_D3),
-	PINMUX_DATA(LCDD2_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD2_DV_D2),
-	PINMUX_DATA(LCDD1_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD1_DV_D1),
-	PINMUX_DATA(LCDD0_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD0_DV_D0),
-	PINMUX_DATA(LCDLCLK_MARK, PSD10_LCDLCLK, VIO_D0_LCDLCLK),
-	/* Main LCD */
-	PINMUX_DATA(LCDDON_MARK, PSD2_LCDDON, HIZA7_LCDC, LCDDON_LCDDON2),
-	PINMUX_DATA(LCDVCPWC_MARK, PSD3_LCDVEPWC_LCDVCPWC,
-		    HIZA6_LCDC, LCDVCPWC_LCDVCPWC2),
-	PINMUX_DATA(LCDVEPWC_MARK, PSD3_LCDVEPWC_LCDVCPWC,
-		    HIZA6_LCDC, LCDVEPWC_LCDVEPWC2),
-	PINMUX_DATA(LCDVSYN_MARK, HIZA7_LCDC, LCDVSYN),
-	/* Main LCD - RGB Mode */
-	PINMUX_DATA(LCDDCK_MARK, MSELB8_RGB, HIZA8_LCDC, LCDDCK_LCDWR),
-	PINMUX_DATA(LCDHSYN_MARK, MSELB8_RGB, HIZA7_LCDC, LCDHSYN_LCDCS),
-	PINMUX_DATA(LCDDISP_MARK, MSELB8_RGB, HIZA7_LCDC, LCDDISP_LCDRS),
-	/* Main LCD - SYS Mode */
-	PINMUX_DATA(LCDRS_MARK, MSELB8_SYS, HIZA7_LCDC, LCDDISP_LCDRS),
-	PINMUX_DATA(LCDCS_MARK, MSELB8_SYS, HIZA7_LCDC, LCDHSYN_LCDCS),
-	PINMUX_DATA(LCDWR_MARK, MSELB8_SYS, HIZA8_LCDC, LCDDCK_LCDWR),
-	PINMUX_DATA(LCDRD_MARK, HIZA7_LCDC, LCDRD),
-	/* Sub LCD - SYS Mode */
-	PINMUX_DATA(LCDDON2_MARK, PSD2_LCDDON2, HIZA7_LCDC, LCDDON_LCDDON2),
-	PINMUX_DATA(LCDVCPWC2_MARK, PSD3_LCDVEPWC2_LCDVCPWC2,
-		    HIZA6_LCDC, LCDVCPWC_LCDVCPWC2),
-	PINMUX_DATA(LCDVEPWC2_MARK, PSD3_LCDVEPWC2_LCDVCPWC2,
-		    HIZA6_LCDC, LCDVEPWC_LCDVEPWC2),
-	PINMUX_DATA(LCDVSYN2_MARK, PSE12_LCDVSYN2, HIZA8_LCDC, LCDVSYN2_DACK),
-	PINMUX_DATA(LCDCS2_MARK, PSD5_LCDCS2, CS6B_CE1B_LCDCS2),
-
-	/* BSC */
-	PINMUX_DATA(IOIS16_MARK, IOIS16),
-	PINMUX_DATA(A25_MARK, A25),
-	PINMUX_DATA(A24_MARK, A24),
-	PINMUX_DATA(A23_MARK, A23),
-	PINMUX_DATA(A22_MARK, A22),
-	PINMUX_DATA(BS_MARK, PSA9_BS, IRQ4_BS),
-	PINMUX_DATA(CS6B_CE1B_MARK, PSD5_CS6B_CE1B, CS6B_CE1B_LCDCS2),
-	PINMUX_DATA(WAIT_MARK, WAIT),
-	PINMUX_DATA(CS6A_CE2B_MARK, CS6A_CE2B),
-
-	/* SBSC */
-	PINMUX_DATA(HPD63_MARK, HPD63),
-	PINMUX_DATA(HPD62_MARK, HPD62),
-	PINMUX_DATA(HPD61_MARK, HPD61),
-	PINMUX_DATA(HPD60_MARK, HPD60),
-	PINMUX_DATA(HPD59_MARK, HPD59),
-	PINMUX_DATA(HPD58_MARK, HPD58),
-	PINMUX_DATA(HPD57_MARK, HPD57),
-	PINMUX_DATA(HPD56_MARK, HPD56),
-	PINMUX_DATA(HPD55_MARK, HPD55),
-	PINMUX_DATA(HPD54_MARK, HPD54),
-	PINMUX_DATA(HPD53_MARK, HPD53),
-	PINMUX_DATA(HPD52_MARK, HPD52),
-	PINMUX_DATA(HPD51_MARK, HPD51),
-	PINMUX_DATA(HPD50_MARK, HPD50),
-	PINMUX_DATA(HPD49_MARK, HPD49),
-	PINMUX_DATA(HPD48_MARK, HPD48),
-	PINMUX_DATA(HPDQM7_MARK, HPDQM7),
-	PINMUX_DATA(HPDQM6_MARK, HPDQM6),
-	PINMUX_DATA(HPDQM5_MARK, HPDQM5),
-	PINMUX_DATA(HPDQM4_MARK, HPDQM4),
-
-	/* IRQ */
-	PINMUX_DATA(IRQ0_MARK, HIZC8_IRQ0, IRQ0),
-	PINMUX_DATA(IRQ1_MARK, HIZC9_IRQ1, IRQ1),
-	PINMUX_DATA(IRQ2_MARK, PSA4_IRQ2, HIZC10_IRQ2, IRQ2_SDHID2),
-	PINMUX_DATA(IRQ3_MARK, PSE15_SIOF0_MCK_IRQ3, PSB8_IRQ3,
-		    HIZC11_IRQ3, PTQ0),
-	PINMUX_DATA(IRQ4_MARK, PSA9_IRQ4, HIZC12_IRQ4, IRQ4_BS),
-	PINMUX_DATA(IRQ5_MARK, HIZC13_IRQ5, IRQ5),
-	PINMUX_DATA(IRQ6_MARK, PSA15_IRQ6, HIZC14_IRQ6, KEYIN0_IRQ6),
-	PINMUX_DATA(IRQ7_MARK, PSA14_IRQ7, HIZC15_IRQ7, KEYIN4_IRQ7),
-
-	/* SDHI */
-	PINMUX_DATA(SDHICD_MARK, SDHICD),
-	PINMUX_DATA(SDHIWP_MARK, SDHIWP),
-	PINMUX_DATA(SDHID3_MARK, SDHID3),
-	PINMUX_DATA(SDHID2_MARK, PSA4_SDHID2, IRQ2_SDHID2),
-	PINMUX_DATA(SDHID1_MARK, SDHID1),
-	PINMUX_DATA(SDHID0_MARK, SDHID0),
-	PINMUX_DATA(SDHICMD_MARK, SDHICMD),
-	PINMUX_DATA(SDHICLK_MARK, SDHICLK),
-
-	/* SIU - Port A */
-	PINMUX_DATA(SIUAOLR_MARK, PSC13_SIUAOLR, HIZB4_SIUA, SIUAOLR_SIOF1_SYNC),
-	PINMUX_DATA(SIUAOBT_MARK, PSC14_SIUAOBT, HIZB4_SIUA, SIUAOBT_SIOF1_SCK),
-	PINMUX_DATA(SIUAISLD_MARK, PSC15_SIUAISLD, HIZB4_SIUA, SIUAISLD_SIOF1_RXD),
-	PINMUX_DATA(SIUAILR_MARK, PSC11_SIUAILR, HIZB4_SIUA, SIUAILR_SIOF1_SS2),
-	PINMUX_DATA(SIUAIBT_MARK, PSC12_SIUAIBT, HIZB4_SIUA, SIUAIBT_SIOF1_SS1),
-	PINMUX_DATA(SIUAOSLD_MARK, PSB0_SIUAOSLD, HIZB4_SIUA, SIUAOSLD_SIOF1_TXD),
-	PINMUX_DATA(SIUMCKA_MARK, PSE11_SIUMCKA_SIOF1_MCK, HIZB4_SIUA, PSB1_SIUMCKA, PTK0),
-	PINMUX_DATA(SIUFCKA_MARK, PSE11_SIUFCKA, HIZB4_SIUA, PTK0),
-
-	/* SIU - Port B */
-	PINMUX_DATA(SIUBOLR_MARK, PSB11_SIUBOLR, SIOSTRB1_SIUBOLR),
-	PINMUX_DATA(SIUBOBT_MARK, PSB10_SIUBOBT, SIOSCK_SIUBOBT),
-	PINMUX_DATA(SIUBISLD_MARK, PSB14_SIUBISLD, SIORXD_SIUBISLD),
-	PINMUX_DATA(SIUBILR_MARK, PSB13_SIUBILR, SIOD_SIUBILR),
-	PINMUX_DATA(SIUBIBT_MARK, PSB12_SIUBIBT, SIOSTRB0_SIUBIBT),
-	PINMUX_DATA(SIUBOSLD_MARK, PSB15_SIUBOSLD, SIOTXD_SIUBOSLD),
-	PINMUX_DATA(SIUMCKB_MARK, PSD9_SIOMCK_SIUMCKB, PSB9_SIUMCKB, PTF6),
-	PINMUX_DATA(SIUFCKB_MARK, PSD9_SIUFCKB, PTF6),
-
-	/* AUD */
-	PINMUX_DATA(AUDSYNC_MARK, AUDSYNC),
-	PINMUX_DATA(AUDATA3_MARK, AUDATA3),
-	PINMUX_DATA(AUDATA2_MARK, AUDATA2),
-	PINMUX_DATA(AUDATA1_MARK, AUDATA1),
-	PINMUX_DATA(AUDATA0_MARK, AUDATA0),
-
-	/* DMAC */
-	PINMUX_DATA(DACK_MARK, PSE12_DACK, LCDVSYN2_DACK),
-	PINMUX_DATA(DREQ0_MARK, DREQ0),
-
-	/* VOU */
-	PINMUX_DATA(DV_CLKI_MARK, PSD0_DV, LCDD19_DV_CLKI),
-	PINMUX_DATA(DV_CLK_MARK, PSD0_DV, LCDD18_DV_CLK),
-	PINMUX_DATA(DV_HSYNC_MARK, PSD0_DV, LCDD17_DV_HSYNC),
-	PINMUX_DATA(DV_VSYNC_MARK, PSD0_DV, LCDD16_DV_VSYNC),
-	PINMUX_DATA(DV_D15_MARK, PSD0_DV, LCDD15_DV_D15),
-	PINMUX_DATA(DV_D14_MARK, PSD0_DV, LCDD14_DV_D14),
-	PINMUX_DATA(DV_D13_MARK, PSD0_DV, LCDD13_DV_D13),
-	PINMUX_DATA(DV_D12_MARK, PSD0_DV, LCDD12_DV_D12),
-	PINMUX_DATA(DV_D11_MARK, PSD0_DV, LCDD11_DV_D11),
-	PINMUX_DATA(DV_D10_MARK, PSD0_DV, LCDD10_DV_D10),
-	PINMUX_DATA(DV_D9_MARK, PSD0_DV, LCDD9_DV_D9),
-	PINMUX_DATA(DV_D8_MARK, PSD0_DV, LCDD8_DV_D8),
-	PINMUX_DATA(DV_D7_MARK, PSD0_DV, LCDD7_DV_D7),
-	PINMUX_DATA(DV_D6_MARK, PSD0_DV, LCDD6_DV_D6),
-	PINMUX_DATA(DV_D5_MARK, PSD0_DV, LCDD5_DV_D5),
-	PINMUX_DATA(DV_D4_MARK, PSD0_DV, LCDD4_DV_D4),
-	PINMUX_DATA(DV_D3_MARK, PSD0_DV, LCDD3_DV_D3),
-	PINMUX_DATA(DV_D2_MARK, PSD0_DV, LCDD2_DV_D2),
-	PINMUX_DATA(DV_D1_MARK, PSD0_DV, LCDD1_DV_D1),
-	PINMUX_DATA(DV_D0_MARK, PSD0_DV, LCDD0_DV_D0),
-
-	/* CPG */
-	PINMUX_DATA(STATUS0_MARK, STATUS0),
-	PINMUX_DATA(PDSTATUS_MARK, PDSTATUS),
-
-	/* SIOF0 */
-	PINMUX_DATA(SIOF0_MCK_MARK, PSE15_SIOF0_MCK_IRQ3, PSB8_SIOF0_MCK, PTQ0),
-	PINMUX_DATA(SIOF0_SCK_MARK, PSB5_SIOF0_SCK, SIOF0_SCK_TS_SCK),
-	PINMUX_DATA(SIOF0_SYNC_MARK, PSB4_SIOF0_SYNC, SIOF0_SYNC_TS_SDEN),
-	PINMUX_DATA(SIOF0_SS1_MARK, PSB3_SIOF0_SS1, SIOF0_SS1_TS_SPSYNC),
-	PINMUX_DATA(SIOF0_SS2_MARK, PSB2_SIOF0_SS2, SIOF0_SS2_SIM_RST),
-	PINMUX_DATA(SIOF0_TXD_MARK, PSE14_SIOF0_TXD_IRDA_OUT,
-		    PSB7_SIOF0_TXD, PTQ1),
-	PINMUX_DATA(SIOF0_RXD_MARK, PSE13_SIOF0_RXD_IRDA_IN,
-		    PSB6_SIOF0_RXD, PTQ2),
-
-	/* SIOF1 */
-	PINMUX_DATA(SIOF1_MCK_MARK, PSE11_SIUMCKA_SIOF1_MCK,
-		    PSB1_SIOF1_MCK, PTK0),
-	PINMUX_DATA(SIOF1_SCK_MARK, PSC14_SIOF1_SCK, SIUAOBT_SIOF1_SCK),
-	PINMUX_DATA(SIOF1_SYNC_MARK, PSC13_SIOF1_SYNC, SIUAOLR_SIOF1_SYNC),
-	PINMUX_DATA(SIOF1_SS1_MARK, PSC12_SIOF1_SS1, SIUAIBT_SIOF1_SS1),
-	PINMUX_DATA(SIOF1_SS2_MARK, PSC11_SIOF1_SS2, SIUAILR_SIOF1_SS2),
-	PINMUX_DATA(SIOF1_TXD_MARK, PSB0_SIOF1_TXD, SIUAOSLD_SIOF1_TXD),
-	PINMUX_DATA(SIOF1_RXD_MARK, PSC15_SIOF1_RXD, SIUAISLD_SIOF1_RXD),
-
-	/* SIM */
-	PINMUX_DATA(SIM_D_MARK, PSE15_SIM_D, PTQ0),
-	PINMUX_DATA(SIM_CLK_MARK, PSE14_SIM_CLK, PTQ1),
-	PINMUX_DATA(SIM_RST_MARK, PSB2_SIM_RST, SIOF0_SS2_SIM_RST),
-
-	/* TSIF */
-	PINMUX_DATA(TS_SDAT_MARK, PSE13_TS_SDAT, PTQ2),
-	PINMUX_DATA(TS_SCK_MARK, PSB5_TS_SCK, SIOF0_SCK_TS_SCK),
-	PINMUX_DATA(TS_SDEN_MARK, PSB4_TS_SDEN, SIOF0_SYNC_TS_SDEN),
-	PINMUX_DATA(TS_SPSYNC_MARK, PSB3_TS_SPSYNC, SIOF0_SS1_TS_SPSYNC),
-
-	/* IRDA */
-	PINMUX_DATA(IRDA_IN_MARK, PSE13_SIOF0_RXD_IRDA_IN, PSB6_IRDA_IN, PTQ2),
-	PINMUX_DATA(IRDA_OUT_MARK, PSE14_SIOF0_TXD_IRDA_OUT,
-		    PSB7_IRDA_OUT, PTQ1),
-
-	/* TPU */
-	PINMUX_DATA(TPUTO_MARK, PSD8_TPUTO, SCIF0_SCK_TPUTO),
-
-	/* FLCTL */
-	PINMUX_DATA(FCE_MARK, PSE3_FLCTL, FCE_VIO_HD2),
-	PINMUX_DATA(NAF7_MARK, PSC0_NAF, HIZA10_NAF, NAF7_VIO_D15),
-	PINMUX_DATA(NAF6_MARK, PSC0_NAF, HIZA10_NAF, NAF6_VIO_D14),
-	PINMUX_DATA(NAF5_MARK, PSC0_NAF, HIZA10_NAF, NAF5_VIO_D13),
-	PINMUX_DATA(NAF4_MARK, PSC0_NAF, HIZA10_NAF, NAF4_VIO_D12),
-	PINMUX_DATA(NAF3_MARK, PSC0_NAF, HIZA10_NAF, NAF3_VIO_D11),
-	PINMUX_DATA(NAF2_MARK, PSE2_NAF2, HIZB0_VIO, NAF2_VIO_D10),
-	PINMUX_DATA(NAF1_MARK, PSE1_NAF1, HIZB0_VIO, NAF1_VIO_D9),
-	PINMUX_DATA(NAF0_MARK, PSE0_NAF0, HIZB0_VIO, NAF0_VIO_D8),
-	PINMUX_DATA(FCDE_MARK, FCDE),
-	PINMUX_DATA(FOE_MARK, PSE3_FLCTL, HIZB0_VIO, FOE_VIO_VD2),
-	PINMUX_DATA(FSC_MARK, FSC),
-	PINMUX_DATA(FWE_MARK, FWE),
-	PINMUX_DATA(FRB_MARK, PSE3_FLCTL, FRB_VIO_CLK2),
-
-	/* KEYSC */
-	PINMUX_DATA(KEYIN0_MARK, PSA15_KEYIN0, HIZC14_IRQ6, KEYIN0_IRQ6),
-	PINMUX_DATA(KEYIN1_MARK, HIZA14_KEYSC, KEYIN1),
-	PINMUX_DATA(KEYIN2_MARK, HIZA14_KEYSC, KEYIN2),
-	PINMUX_DATA(KEYIN3_MARK, HIZA14_KEYSC, KEYIN3),
-	PINMUX_DATA(KEYIN4_MARK, PSA14_KEYIN4, HIZC15_IRQ7, KEYIN4_IRQ7),
-	PINMUX_DATA(KEYOUT0_MARK, HIZA14_KEYSC, KEYOUT0),
-	PINMUX_DATA(KEYOUT1_MARK, HIZA14_KEYSC, KEYOUT1),
-	PINMUX_DATA(KEYOUT2_MARK, HIZA14_KEYSC, KEYOUT2),
-	PINMUX_DATA(KEYOUT3_MARK, HIZA14_KEYSC, KEYOUT3),
-	PINMUX_DATA(KEYOUT4_IN6_MARK, HIZA14_KEYSC, KEYOUT4_IN6),
-	PINMUX_DATA(KEYOUT5_IN5_MARK, HIZA14_KEYSC, KEYOUT5_IN5),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	/* PTA */
-	PINMUX_GPIO(PTA7),
-	PINMUX_GPIO(PTA6),
-	PINMUX_GPIO(PTA5),
-	PINMUX_GPIO(PTA4),
-	PINMUX_GPIO(PTA3),
-	PINMUX_GPIO(PTA2),
-	PINMUX_GPIO(PTA1),
-	PINMUX_GPIO(PTA0),
-
-	/* PTB */
-	PINMUX_GPIO(PTB7),
-	PINMUX_GPIO(PTB6),
-	PINMUX_GPIO(PTB5),
-	PINMUX_GPIO(PTB4),
-	PINMUX_GPIO(PTB3),
-	PINMUX_GPIO(PTB2),
-	PINMUX_GPIO(PTB1),
-	PINMUX_GPIO(PTB0),
-
-	/* PTC */
-	PINMUX_GPIO(PTC7),
-	PINMUX_GPIO(PTC5),
-	PINMUX_GPIO(PTC4),
-	PINMUX_GPIO(PTC3),
-	PINMUX_GPIO(PTC2),
-	PINMUX_GPIO(PTC0),
-
-	/* PTD */
-	PINMUX_GPIO(PTD7),
-	PINMUX_GPIO(PTD6),
-	PINMUX_GPIO(PTD5),
-	PINMUX_GPIO(PTD4),
-	PINMUX_GPIO(PTD3),
-	PINMUX_GPIO(PTD2),
-	PINMUX_GPIO(PTD1),
-	PINMUX_GPIO(PTD0),
-
-	/* PTE */
-	PINMUX_GPIO(PTE7),
-	PINMUX_GPIO(PTE6),
-	PINMUX_GPIO(PTE5),
-	PINMUX_GPIO(PTE4),
-	PINMUX_GPIO(PTE1),
-	PINMUX_GPIO(PTE0),
-
-	/* PTF */
-	PINMUX_GPIO(PTF6),
-	PINMUX_GPIO(PTF5),
-	PINMUX_GPIO(PTF4),
-	PINMUX_GPIO(PTF3),
-	PINMUX_GPIO(PTF2),
-	PINMUX_GPIO(PTF1),
-	PINMUX_GPIO(PTF0),
-
-	/* PTG */
-	PINMUX_GPIO(PTG4),
-	PINMUX_GPIO(PTG3),
-	PINMUX_GPIO(PTG2),
-	PINMUX_GPIO(PTG1),
-	PINMUX_GPIO(PTG0),
-
-	/* PTH */
-	PINMUX_GPIO(PTH7),
-	PINMUX_GPIO(PTH6),
-	PINMUX_GPIO(PTH5),
-	PINMUX_GPIO(PTH4),
-	PINMUX_GPIO(PTH3),
-	PINMUX_GPIO(PTH2),
-	PINMUX_GPIO(PTH1),
-	PINMUX_GPIO(PTH0),
-
-	/* PTJ */
-	PINMUX_GPIO(PTJ7),
-	PINMUX_GPIO(PTJ6),
-	PINMUX_GPIO(PTJ5),
-	PINMUX_GPIO(PTJ1),
-	PINMUX_GPIO(PTJ0),
-
-	/* PTK */
-	PINMUX_GPIO(PTK6),
-	PINMUX_GPIO(PTK5),
-	PINMUX_GPIO(PTK4),
-	PINMUX_GPIO(PTK3),
-	PINMUX_GPIO(PTK2),
-	PINMUX_GPIO(PTK1),
-	PINMUX_GPIO(PTK0),
-
-	/* PTL */
-	PINMUX_GPIO(PTL7),
-	PINMUX_GPIO(PTL6),
-	PINMUX_GPIO(PTL5),
-	PINMUX_GPIO(PTL4),
-	PINMUX_GPIO(PTL3),
-	PINMUX_GPIO(PTL2),
-	PINMUX_GPIO(PTL1),
-	PINMUX_GPIO(PTL0),
-
-	/* PTM */
-	PINMUX_GPIO(PTM7),
-	PINMUX_GPIO(PTM6),
-	PINMUX_GPIO(PTM5),
-	PINMUX_GPIO(PTM4),
-	PINMUX_GPIO(PTM3),
-	PINMUX_GPIO(PTM2),
-	PINMUX_GPIO(PTM1),
-	PINMUX_GPIO(PTM0),
-
-	/* PTN */
-	PINMUX_GPIO(PTN7),
-	PINMUX_GPIO(PTN6),
-	PINMUX_GPIO(PTN5),
-	PINMUX_GPIO(PTN4),
-	PINMUX_GPIO(PTN3),
-	PINMUX_GPIO(PTN2),
-	PINMUX_GPIO(PTN1),
-	PINMUX_GPIO(PTN0),
-
-	/* PTQ */
-	PINMUX_GPIO(PTQ6),
-	PINMUX_GPIO(PTQ5),
-	PINMUX_GPIO(PTQ4),
-	PINMUX_GPIO(PTQ3),
-	PINMUX_GPIO(PTQ2),
-	PINMUX_GPIO(PTQ1),
-	PINMUX_GPIO(PTQ0),
-
-	/* PTR */
-	PINMUX_GPIO(PTR4),
-	PINMUX_GPIO(PTR3),
-	PINMUX_GPIO(PTR2),
-	PINMUX_GPIO(PTR1),
-	PINMUX_GPIO(PTR0),
-
-	/* PTS */
-	PINMUX_GPIO(PTS4),
-	PINMUX_GPIO(PTS3),
-	PINMUX_GPIO(PTS2),
-	PINMUX_GPIO(PTS1),
-	PINMUX_GPIO(PTS0),
-
-	/* PTT */
-	PINMUX_GPIO(PTT4),
-	PINMUX_GPIO(PTT3),
-	PINMUX_GPIO(PTT2),
-	PINMUX_GPIO(PTT1),
-	PINMUX_GPIO(PTT0),
-
-	/* PTU */
-	PINMUX_GPIO(PTU4),
-	PINMUX_GPIO(PTU3),
-	PINMUX_GPIO(PTU2),
-	PINMUX_GPIO(PTU1),
-	PINMUX_GPIO(PTU0),
-
-	/* PTV */
-	PINMUX_GPIO(PTV4),
-	PINMUX_GPIO(PTV3),
-	PINMUX_GPIO(PTV2),
-	PINMUX_GPIO(PTV1),
-	PINMUX_GPIO(PTV0),
-
-	/* PTW */
-	PINMUX_GPIO(PTW6),
-	PINMUX_GPIO(PTW5),
-	PINMUX_GPIO(PTW4),
-	PINMUX_GPIO(PTW3),
-	PINMUX_GPIO(PTW2),
-	PINMUX_GPIO(PTW1),
-	PINMUX_GPIO(PTW0),
-
-	/* PTX */
-	PINMUX_GPIO(PTX6),
-	PINMUX_GPIO(PTX5),
-	PINMUX_GPIO(PTX4),
-	PINMUX_GPIO(PTX3),
-	PINMUX_GPIO(PTX2),
-	PINMUX_GPIO(PTX1),
-	PINMUX_GPIO(PTX0),
-
-	/* PTY */
-	PINMUX_GPIO(PTY5),
-	PINMUX_GPIO(PTY4),
-	PINMUX_GPIO(PTY3),
-	PINMUX_GPIO(PTY2),
-	PINMUX_GPIO(PTY1),
-	PINMUX_GPIO(PTY0),
-
-	/* PTZ */
-	PINMUX_GPIO(PTZ5),
-	PINMUX_GPIO(PTZ4),
-	PINMUX_GPIO(PTZ3),
-	PINMUX_GPIO(PTZ2),
-	PINMUX_GPIO(PTZ1),
-};
-
-#define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-	/* SCIF0 */
-	GPIO_FN(SCIF0_TXD),
-	GPIO_FN(SCIF0_RXD),
-	GPIO_FN(SCIF0_RTS),
-	GPIO_FN(SCIF0_CTS),
-	GPIO_FN(SCIF0_SCK),
-
-	/* SCIF1 */
-	GPIO_FN(SCIF1_TXD),
-	GPIO_FN(SCIF1_RXD),
-	GPIO_FN(SCIF1_RTS),
-	GPIO_FN(SCIF1_CTS),
-	GPIO_FN(SCIF1_SCK),
-
-	/* SCIF2 */
-	GPIO_FN(SCIF2_TXD),
-	GPIO_FN(SCIF2_RXD),
-	GPIO_FN(SCIF2_RTS),
-	GPIO_FN(SCIF2_CTS),
-	GPIO_FN(SCIF2_SCK),
-
-	/* SIO */
-	GPIO_FN(SIOTXD),
-	GPIO_FN(SIORXD),
-	GPIO_FN(SIOD),
-	GPIO_FN(SIOSTRB0),
-	GPIO_FN(SIOSTRB1),
-	GPIO_FN(SIOSCK),
-	GPIO_FN(SIOMCK),
-
-	/* CEU */
-	GPIO_FN(VIO_D15),
-	GPIO_FN(VIO_D14),
-	GPIO_FN(VIO_D13),
-	GPIO_FN(VIO_D12),
-	GPIO_FN(VIO_D11),
-	GPIO_FN(VIO_D10),
-	GPIO_FN(VIO_D9),
-	GPIO_FN(VIO_D8),
-	GPIO_FN(VIO_D7),
-	GPIO_FN(VIO_D6),
-	GPIO_FN(VIO_D5),
-	GPIO_FN(VIO_D4),
-	GPIO_FN(VIO_D3),
-	GPIO_FN(VIO_D2),
-	GPIO_FN(VIO_D1),
-	GPIO_FN(VIO_D0),
-	GPIO_FN(VIO_CLK),
-	GPIO_FN(VIO_VD),
-	GPIO_FN(VIO_HD),
-	GPIO_FN(VIO_FLD),
-	GPIO_FN(VIO_CKO),
-	GPIO_FN(VIO_STEX),
-	GPIO_FN(VIO_STEM),
-	GPIO_FN(VIO_VD2),
-	GPIO_FN(VIO_HD2),
-	GPIO_FN(VIO_CLK2),
-
-	/* LCDC */
-	GPIO_FN(LCDD23),
-	GPIO_FN(LCDD22),
-	GPIO_FN(LCDD21),
-	GPIO_FN(LCDD20),
-	GPIO_FN(LCDD19),
-	GPIO_FN(LCDD18),
-	GPIO_FN(LCDD17),
-	GPIO_FN(LCDD16),
-	GPIO_FN(LCDD15),
-	GPIO_FN(LCDD14),
-	GPIO_FN(LCDD13),
-	GPIO_FN(LCDD12),
-	GPIO_FN(LCDD11),
-	GPIO_FN(LCDD10),
-	GPIO_FN(LCDD9),
-	GPIO_FN(LCDD8),
-	GPIO_FN(LCDD7),
-	GPIO_FN(LCDD6),
-	GPIO_FN(LCDD5),
-	GPIO_FN(LCDD4),
-	GPIO_FN(LCDD3),
-	GPIO_FN(LCDD2),
-	GPIO_FN(LCDD1),
-	GPIO_FN(LCDD0),
-	GPIO_FN(LCDLCLK),
-	/* Main LCD */
-	GPIO_FN(LCDDON),
-	GPIO_FN(LCDVCPWC),
-	GPIO_FN(LCDVEPWC),
-	GPIO_FN(LCDVSYN),
-	/* Main LCD - RGB Mode */
-	GPIO_FN(LCDDCK),
-	GPIO_FN(LCDHSYN),
-	GPIO_FN(LCDDISP),
-	/* Main LCD - SYS Mode */
-	GPIO_FN(LCDRS),
-	GPIO_FN(LCDCS),
-	GPIO_FN(LCDWR),
-	GPIO_FN(LCDRD),
-	/* Sub LCD - SYS Mode */
-	GPIO_FN(LCDDON2),
-	GPIO_FN(LCDVCPWC2),
-	GPIO_FN(LCDVEPWC2),
-	GPIO_FN(LCDVSYN2),
-	GPIO_FN(LCDCS2),
-
-	/* BSC */
-	GPIO_FN(IOIS16),
-	GPIO_FN(A25),
-	GPIO_FN(A24),
-	GPIO_FN(A23),
-	GPIO_FN(A22),
-	GPIO_FN(BS),
-	GPIO_FN(CS6B_CE1B),
-	GPIO_FN(WAIT),
-	GPIO_FN(CS6A_CE2B),
-
-	/* SBSC */
-	GPIO_FN(HPD63),
-	GPIO_FN(HPD62),
-	GPIO_FN(HPD61),
-	GPIO_FN(HPD60),
-	GPIO_FN(HPD59),
-	GPIO_FN(HPD58),
-	GPIO_FN(HPD57),
-	GPIO_FN(HPD56),
-	GPIO_FN(HPD55),
-	GPIO_FN(HPD54),
-	GPIO_FN(HPD53),
-	GPIO_FN(HPD52),
-	GPIO_FN(HPD51),
-	GPIO_FN(HPD50),
-	GPIO_FN(HPD49),
-	GPIO_FN(HPD48),
-	GPIO_FN(HPDQM7),
-	GPIO_FN(HPDQM6),
-	GPIO_FN(HPDQM5),
-	GPIO_FN(HPDQM4),
-
-	/* IRQ */
-	GPIO_FN(IRQ0),
-	GPIO_FN(IRQ1),
-	GPIO_FN(IRQ2),
-	GPIO_FN(IRQ3),
-	GPIO_FN(IRQ4),
-	GPIO_FN(IRQ5),
-	GPIO_FN(IRQ6),
-	GPIO_FN(IRQ7),
-
-	/* SDHI */
-	GPIO_FN(SDHICD),
-	GPIO_FN(SDHIWP),
-	GPIO_FN(SDHID3),
-	GPIO_FN(SDHID2),
-	GPIO_FN(SDHID1),
-	GPIO_FN(SDHID0),
-	GPIO_FN(SDHICMD),
-	GPIO_FN(SDHICLK),
-
-	/* SIU - Port A */
-	GPIO_FN(SIUAOLR),
-	GPIO_FN(SIUAOBT),
-	GPIO_FN(SIUAISLD),
-	GPIO_FN(SIUAILR),
-	GPIO_FN(SIUAIBT),
-	GPIO_FN(SIUAOSLD),
-	GPIO_FN(SIUMCKA),
-	GPIO_FN(SIUFCKA),
-
-	/* SIU - Port B */
-	GPIO_FN(SIUBOLR),
-	GPIO_FN(SIUBOBT),
-	GPIO_FN(SIUBISLD),
-	GPIO_FN(SIUBILR),
-	GPIO_FN(SIUBIBT),
-	GPIO_FN(SIUBOSLD),
-	GPIO_FN(SIUMCKB),
-	GPIO_FN(SIUFCKB),
-
-	/* AUD */
-	GPIO_FN(AUDSYNC),
-	GPIO_FN(AUDATA3),
-	GPIO_FN(AUDATA2),
-	GPIO_FN(AUDATA1),
-	GPIO_FN(AUDATA0),
-
-	/* DMAC */
-	GPIO_FN(DACK),
-	GPIO_FN(DREQ0),
-
-	/* VOU */
-	GPIO_FN(DV_CLKI),
-	GPIO_FN(DV_CLK),
-	GPIO_FN(DV_HSYNC),
-	GPIO_FN(DV_VSYNC),
-	GPIO_FN(DV_D15),
-	GPIO_FN(DV_D14),
-	GPIO_FN(DV_D13),
-	GPIO_FN(DV_D12),
-	GPIO_FN(DV_D11),
-	GPIO_FN(DV_D10),
-	GPIO_FN(DV_D9),
-	GPIO_FN(DV_D8),
-	GPIO_FN(DV_D7),
-	GPIO_FN(DV_D6),
-	GPIO_FN(DV_D5),
-	GPIO_FN(DV_D4),
-	GPIO_FN(DV_D3),
-	GPIO_FN(DV_D2),
-	GPIO_FN(DV_D1),
-	GPIO_FN(DV_D0),
-
-	/* CPG */
-	GPIO_FN(STATUS0),
-	GPIO_FN(PDSTATUS),
-
-	/* SIOF0 */
-	GPIO_FN(SIOF0_MCK),
-	GPIO_FN(SIOF0_SCK),
-	GPIO_FN(SIOF0_SYNC),
-	GPIO_FN(SIOF0_SS1),
-	GPIO_FN(SIOF0_SS2),
-	GPIO_FN(SIOF0_TXD),
-	GPIO_FN(SIOF0_RXD),
-
-	/* SIOF1 */
-	GPIO_FN(SIOF1_MCK),
-	GPIO_FN(SIOF1_SCK),
-	GPIO_FN(SIOF1_SYNC),
-	GPIO_FN(SIOF1_SS1),
-	GPIO_FN(SIOF1_SS2),
-	GPIO_FN(SIOF1_TXD),
-	GPIO_FN(SIOF1_RXD),
-
-	/* SIM */
-	GPIO_FN(SIM_D),
-	GPIO_FN(SIM_CLK),
-	GPIO_FN(SIM_RST),
-
-	/* TSIF */
-	GPIO_FN(TS_SDAT),
-	GPIO_FN(TS_SCK),
-	GPIO_FN(TS_SDEN),
-	GPIO_FN(TS_SPSYNC),
-
-	/* IRDA */
-	GPIO_FN(IRDA_IN),
-	GPIO_FN(IRDA_OUT),
-
-	/* TPU */
-	GPIO_FN(TPUTO),
-
-	/* FLCTL */
-	GPIO_FN(FCE),
-	GPIO_FN(NAF7),
-	GPIO_FN(NAF6),
-	GPIO_FN(NAF5),
-	GPIO_FN(NAF4),
-	GPIO_FN(NAF3),
-	GPIO_FN(NAF2),
-	GPIO_FN(NAF1),
-	GPIO_FN(NAF0),
-	GPIO_FN(FCDE),
-	GPIO_FN(FOE),
-	GPIO_FN(FSC),
-	GPIO_FN(FWE),
-	GPIO_FN(FRB),
-
-	/* KEYSC */
-	GPIO_FN(KEYIN0),
-	GPIO_FN(KEYIN1),
-	GPIO_FN(KEYIN2),
-	GPIO_FN(KEYIN3),
-	GPIO_FN(KEYIN4),
-	GPIO_FN(KEYOUT0),
-	GPIO_FN(KEYOUT1),
-	GPIO_FN(KEYOUT2),
-	GPIO_FN(KEYOUT3),
-	GPIO_FN(KEYOUT4_IN6),
-	GPIO_FN(KEYOUT5_IN5),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2, GROUP(
-		VIO_D7_SCIF1_SCK, PTA7_OUT, 0, PTA7_IN,
-		VIO_D6_SCIF1_RXD, 0, 0, PTA6_IN,
-		VIO_D5_SCIF1_TXD, PTA5_OUT, 0, PTA5_IN,
-		VIO_D4, 0, 0, PTA4_IN,
-		VIO_D3, 0, 0, PTA3_IN,
-		VIO_D2, 0, 0, PTA2_IN,
-		VIO_D1, 0, 0, PTA1_IN,
-		VIO_D0_LCDLCLK, 0, 0, PTA0_IN ))
-	},
-	{ PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2, GROUP(
-		HPD55, PTB7_OUT, 0, PTB7_IN,
-		HPD54, PTB6_OUT, 0, PTB6_IN,
-		HPD53, PTB5_OUT, 0, PTB5_IN,
-		HPD52, PTB4_OUT, 0, PTB4_IN,
-		HPD51, PTB3_OUT, 0, PTB3_IN,
-		HPD50, PTB2_OUT, 0, PTB2_IN,
-		HPD49, PTB1_OUT, 0, PTB1_IN,
-		HPD48, PTB0_OUT, 0, PTB0_IN ))
-	},
-	{ PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2, GROUP(
-		0, 0, 0, PTC7_IN,
-		0, 0, 0, 0,
-		IOIS16, 0, 0, PTC5_IN,
-		HPDQM7, PTC4_OUT, 0, PTC4_IN,
-		HPDQM6, PTC3_OUT, 0, PTC3_IN,
-		HPDQM5, PTC2_OUT, 0, PTC2_IN,
-		0, 0, 0, 0,
-		HPDQM4, PTC0_OUT, 0, PTC0_IN ))
-	},
-	{ PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2, GROUP(
-		SDHICD, 0, 0, PTD7_IN,
-		SDHIWP, PTD6_OUT, 0, PTD6_IN,
-		SDHID3, PTD5_OUT, 0, PTD5_IN,
-		IRQ2_SDHID2, PTD4_OUT, 0, PTD4_IN,
-		SDHID1, PTD3_OUT, 0, PTD3_IN,
-		SDHID0, PTD2_OUT, 0, PTD2_IN,
-		SDHICMD, PTD1_OUT, 0, PTD1_IN,
-		SDHICLK, PTD0_OUT, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2, GROUP(
-		A25, PTE7_OUT, 0, PTE7_IN,
-		A24, PTE6_OUT, 0, PTE6_IN,
-		A23, PTE5_OUT, 0, PTE5_IN,
-		A22, PTE4_OUT, 0, PTE4_IN,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		IRQ5, PTE1_OUT, 0, PTE1_IN,
-		IRQ4_BS, PTE0_OUT, 0, PTE0_IN ))
-	},
-	{ PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2, GROUP(
-		0, 0, 0, 0,
-		PTF6, PTF6_OUT, 0, PTF6_IN,
-		SIOSCK_SIUBOBT, PTF5_OUT, 0, PTF5_IN,
-		SIOSTRB1_SIUBOLR, PTF4_OUT, 0, PTF4_IN,
-		SIOSTRB0_SIUBIBT, PTF3_OUT, 0, PTF3_IN,
-		SIOD_SIUBILR, PTF2_OUT, 0, PTF2_IN,
-		SIORXD_SIUBISLD, 0, 0, PTF1_IN,
-		SIOTXD_SIUBOSLD, PTF0_OUT, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		AUDSYNC, PTG4_OUT, 0, 0,
-		AUDATA3, PTG3_OUT, 0, 0,
-		AUDATA2, PTG2_OUT, 0, 0,
-		AUDATA1, PTG1_OUT, 0, 0,
-		AUDATA0, PTG0_OUT, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2, GROUP(
-		LCDVCPWC_LCDVCPWC2, PTH7_OUT, 0, 0,
-		LCDVSYN2_DACK, PTH6_OUT, 0, PTH6_IN,
-		LCDVSYN, PTH5_OUT, 0, PTH5_IN,
-		LCDDISP_LCDRS, PTH4_OUT, 0, 0,
-		LCDHSYN_LCDCS, PTH3_OUT, 0, 0,
-		LCDDON_LCDDON2, PTH2_OUT, 0, 0,
-		LCDD17_DV_HSYNC, PTH1_OUT, 0, PTH1_IN,
-		LCDD16_DV_VSYNC, PTH0_OUT, 0, PTH0_IN ))
-	},
-	{ PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2, GROUP(
-		STATUS0, PTJ7_OUT, 0, 0,
-		0, PTJ6_OUT, 0, 0,
-		PDSTATUS, PTJ5_OUT, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		IRQ1, PTJ1_OUT, 0, PTJ1_IN,
-		IRQ0, PTJ0_OUT, 0, PTJ0_IN ))
-	},
-	{ PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2, GROUP(
-		0, 0, 0, 0,
-		SIUAILR_SIOF1_SS2, PTK6_OUT, 0, PTK6_IN,
-		SIUAIBT_SIOF1_SS1, PTK5_OUT, 0, PTK5_IN,
-		SIUAOLR_SIOF1_SYNC, PTK4_OUT, 0, PTK4_IN,
-		SIUAOBT_SIOF1_SCK, PTK3_OUT, 0, PTK3_IN,
-		SIUAISLD_SIOF1_RXD, 0, 0, PTK2_IN,
-		SIUAOSLD_SIOF1_TXD, PTK1_OUT, 0, 0,
-		PTK0, PTK0_OUT, 0, PTK0_IN ))
-	},
-	{ PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2, GROUP(
-		LCDD15_DV_D15, PTL7_OUT, 0, PTL7_IN,
-		LCDD14_DV_D14, PTL6_OUT, 0, PTL6_IN,
-		LCDD13_DV_D13, PTL5_OUT, 0, PTL5_IN,
-		LCDD12_DV_D12, PTL4_OUT, 0, PTL4_IN,
-		LCDD11_DV_D11, PTL3_OUT, 0, PTL3_IN,
-		LCDD10_DV_D10, PTL2_OUT, 0, PTL2_IN,
-		LCDD9_DV_D9, PTL1_OUT, 0, PTL1_IN,
-		LCDD8_DV_D8, PTL0_OUT, 0, PTL0_IN ))
-	},
-	{ PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2, GROUP(
-		LCDD7_DV_D7, PTM7_OUT, 0, PTM7_IN,
-		LCDD6_DV_D6, PTM6_OUT, 0, PTM6_IN,
-		LCDD5_DV_D5, PTM5_OUT, 0, PTM5_IN,
-		LCDD4_DV_D4, PTM4_OUT, 0, PTM4_IN,
-		LCDD3_DV_D3, PTM3_OUT, 0, PTM3_IN,
-		LCDD2_DV_D2, PTM2_OUT, 0, PTM2_IN,
-		LCDD1_DV_D1, PTM1_OUT, 0, PTM1_IN,
-		LCDD0_DV_D0, PTM0_OUT, 0, PTM0_IN ))
-	},
-	{ PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2, GROUP(
-		HPD63, PTN7_OUT, 0, PTN7_IN,
-		HPD62, PTN6_OUT, 0, PTN6_IN,
-		HPD61, PTN5_OUT, 0, PTN5_IN,
-		HPD60, PTN4_OUT, 0, PTN4_IN,
-		HPD59, PTN3_OUT, 0, PTN3_IN,
-		HPD58, PTN2_OUT, 0, PTN2_IN,
-		HPD57, PTN1_OUT, 0, PTN1_IN,
-		HPD56, PTN0_OUT, 0, PTN0_IN ))
-	},
-	{ PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2, GROUP(
-		0, 0, 0, 0,
-		SIOF0_SS2_SIM_RST, PTQ6_OUT, 0, 0,
-		SIOF0_SS1_TS_SPSYNC, PTQ5_OUT, 0, PTQ5_IN,
-		SIOF0_SYNC_TS_SDEN, PTQ4_OUT, 0, PTQ4_IN,
-		SIOF0_SCK_TS_SCK, PTQ3_OUT, 0, PTQ3_IN,
-		PTQ2, 0, 0, PTQ2_IN,
-		PTQ1, PTQ1_OUT, 0, 0,
-		PTQ0, PTQ0_OUT, 0, PTQ0_IN ))
-	},
-	{ PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		LCDRD, PTR4_OUT, 0, 0,
-		CS6B_CE1B_LCDCS2, PTR3_OUT, 0, 0,
-		WAIT, 0, 0, PTR2_IN,
-		LCDDCK_LCDWR, PTR1_OUT, 0, 0,
-		LCDVEPWC_LCDVEPWC2, PTR0_OUT, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		SCIF0_CTS_SIUAISPD, 0, 0, PTS4_IN,
-		SCIF0_RTS_SIUAOSPD, PTS3_OUT, 0, 0,
-		SCIF0_SCK_TPUTO, PTS2_OUT, 0, PTS2_IN,
-		SCIF0_RXD, 0, 0, PTS1_IN,
-		SCIF0_TXD, PTS0_OUT, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		FOE_VIO_VD2, PTT4_OUT, 0, PTT4_IN,
-		FWE, PTT3_OUT, 0, PTT3_IN,
-		FSC, PTT2_OUT, 0, PTT2_IN,
-		DREQ0, 0, 0, PTT1_IN,
-		FCDE, PTT0_OUT, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		NAF2_VIO_D10, PTU4_OUT, 0, PTU4_IN,
-		NAF1_VIO_D9, PTU3_OUT, 0, PTU3_IN,
-		NAF0_VIO_D8, PTU2_OUT, 0, PTU2_IN,
-		FRB_VIO_CLK2, 0, 0, PTU1_IN,
-		FCE_VIO_HD2, PTU0_OUT, 0, PTU0_IN ))
-	},
-	{ PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		NAF7_VIO_D15, PTV4_OUT, 0, PTV4_IN,
-		NAF6_VIO_D14, PTV3_OUT, 0, PTV3_IN,
-		NAF5_VIO_D13, PTV2_OUT, 0, PTV2_IN,
-		NAF4_VIO_D12, PTV1_OUT, 0, PTV1_IN,
-		NAF3_VIO_D11, PTV0_OUT, 0, PTV0_IN ))
-	},
-	{ PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2, GROUP(
-		0, 0, 0, 0,
-		VIO_FLD_SCIF2_CTS, 0, 0, PTW6_IN,
-		VIO_CKO_SCIF2_RTS, PTW5_OUT, 0, 0,
-		VIO_STEX_SCIF2_SCK, PTW4_OUT, 0, PTW4_IN,
-		VIO_STEM_SCIF2_TXD, PTW3_OUT, 0, PTW3_IN,
-		VIO_HD_SCIF2_RXD, PTW2_OUT, 0, PTW2_IN,
-		VIO_VD_SCIF1_CTS, PTW1_OUT, 0, PTW1_IN,
-		VIO_CLK_SCIF1_RTS, PTW0_OUT, 0, PTW0_IN ))
-	},
-	{ PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2, GROUP(
-		0, 0, 0, 0,
-		CS6A_CE2B, PTX6_OUT, 0, PTX6_IN,
-		LCDD23, PTX5_OUT, 0, PTX5_IN,
-		LCDD22, PTX4_OUT, 0, PTX4_IN,
-		LCDD21, PTX3_OUT, 0, PTX3_IN,
-		LCDD20, PTX2_OUT, 0, PTX2_IN,
-		LCDD19_DV_CLKI, PTX1_OUT, 0, PTX1_IN,
-		LCDD18_DV_CLK, PTX0_OUT, 0, PTX0_IN ))
-	},
-	{ PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		KEYOUT5_IN5, PTY5_OUT, 0, PTY5_IN,
-		KEYOUT4_IN6, PTY4_OUT, 0, PTY4_IN,
-		KEYOUT3, PTY3_OUT, 0, PTY3_IN,
-		KEYOUT2, PTY2_OUT, 0, PTY2_IN,
-		KEYOUT1, PTY1_OUT, 0, 0,
-		KEYOUT0, PTY0_OUT, 0, PTY0_IN ))
-	},
-	{ PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		KEYIN4_IRQ7, 0, 0, PTZ5_IN,
-		KEYIN3, 0, 0, PTZ4_IN,
-		KEYIN2, 0, 0, PTZ3_IN,
-		KEYIN1, 0, 0, PTZ2_IN,
-		KEYIN0_IRQ6, 0, 0, PTZ1_IN,
-		0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1, GROUP(
-		PSA15_KEYIN0, PSA15_IRQ6,
-		PSA14_KEYIN4, PSA14_IRQ7,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		PSA9_IRQ4, PSA9_BS,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		PSA4_IRQ2, PSA4_SDHID2,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1, GROUP(
-		PSB15_SIOTXD, PSB15_SIUBOSLD,
-		PSB14_SIORXD, PSB14_SIUBISLD,
-		PSB13_SIOD, PSB13_SIUBILR,
-		PSB12_SIOSTRB0, PSB12_SIUBIBT,
-		PSB11_SIOSTRB1, PSB11_SIUBOLR,
-		PSB10_SIOSCK, PSB10_SIUBOBT,
-		PSB9_SIOMCK, PSB9_SIUMCKB,
-		PSB8_SIOF0_MCK, PSB8_IRQ3,
-		PSB7_SIOF0_TXD, PSB7_IRDA_OUT,
-		PSB6_SIOF0_RXD, PSB6_IRDA_IN,
-		PSB5_SIOF0_SCK, PSB5_TS_SCK,
-		PSB4_SIOF0_SYNC, PSB4_TS_SDEN,
-		PSB3_SIOF0_SS1, PSB3_TS_SPSYNC,
-		PSB2_SIOF0_SS2, PSB2_SIM_RST,
-		PSB1_SIUMCKA, PSB1_SIOF1_MCK,
-		PSB0_SIUAOSLD, PSB0_SIOF1_TXD ))
-	},
-	{ PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1, GROUP(
-		PSC15_SIUAISLD, PSC15_SIOF1_RXD,
-		PSC14_SIUAOBT, PSC14_SIOF1_SCK,
-		PSC13_SIUAOLR, PSC13_SIOF1_SYNC,
-		PSC12_SIUAIBT, PSC12_SIOF1_SS1,
-		PSC11_SIUAILR, PSC11_SIOF1_SS2,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		PSC0_NAF, PSC0_VIO ))
-	},
-	{ PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1, GROUP(
-		0, 0,
-		0, 0,
-		PSD13_VIO, PSD13_SCIF2,
-		PSD12_VIO, PSD12_SCIF1,
-		PSD11_VIO, PSD11_SCIF1,
-		PSD10_VIO_D0, PSD10_LCDLCLK,
-		PSD9_SIOMCK_SIUMCKB, PSD9_SIUFCKB,
-		PSD8_SCIF0_SCK, PSD8_TPUTO,
-		PSD7_SCIF0_RTS, PSD7_SIUAOSPD,
-		PSD6_SCIF0_CTS, PSD6_SIUAISPD,
-		PSD5_CS6B_CE1B, PSD5_LCDCS2,
-		0, 0,
-		PSD3_LCDVEPWC_LCDVCPWC, PSD3_LCDVEPWC2_LCDVCPWC2,
-		PSD2_LCDDON, PSD2_LCDDON2,
-		0, 0,
-		PSD0_LCDD19_LCDD0, PSD0_DV ))
-	},
-	{ PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1, GROUP(
-		PSE15_SIOF0_MCK_IRQ3, PSE15_SIM_D,
-		PSE14_SIOF0_TXD_IRDA_OUT, PSE14_SIM_CLK,
-		PSE13_SIOF0_RXD_IRDA_IN, PSE13_TS_SDAT,
-		PSE12_LCDVSYN2, PSE12_DACK,
-		PSE11_SIUMCKA_SIOF1_MCK, PSE11_SIUFCKA,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		PSE3_FLCTL, PSE3_VIO,
-		PSE2_NAF2, PSE2_VIO_D10,
-		PSE1_NAF1, PSE1_VIO_D9,
-		PSE0_NAF0, PSE0_VIO_D8 ))
-	},
-	{ PINMUX_CFG_REG("HIZCRA", 0xa4050158, 16, 1, GROUP(
-		0, 0,
-		HIZA14_KEYSC, HIZA14_HIZ,
-		0, 0,
-		0, 0,
-		0, 0,
-		HIZA10_NAF, HIZA10_HIZ,
-		HIZA9_VIO, HIZA9_HIZ,
-		HIZA8_LCDC, HIZA8_HIZ,
-		HIZA7_LCDC, HIZA7_HIZ,
-		HIZA6_LCDC, HIZA6_HIZ,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0 ))
-	},
-	{ PINMUX_CFG_REG("HIZCRB", 0xa405015a, 16, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		HIZB4_SIUA, HIZB4_HIZ,
-		0, 0,
-		0, 0,
-		HIZB1_VIO, HIZB1_HIZ,
-		HIZB0_VIO, HIZB0_HIZ ))
-	},
-	{ PINMUX_CFG_REG("HIZCRC", 0xa405015c, 16, 1, GROUP(
-		HIZC15_IRQ7, HIZC15_HIZ,
-		HIZC14_IRQ6, HIZC14_HIZ,
-		HIZC13_IRQ5, HIZC13_HIZ,
-		HIZC12_IRQ4, HIZC12_HIZ,
-		HIZC11_IRQ3, HIZC11_HIZ,
-		HIZC10_IRQ2, HIZC10_HIZ,
-		HIZC9_IRQ1, HIZC9_HIZ,
-		HIZC8_IRQ0, HIZC8_HIZ,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0 ))
-	},
-	{ PINMUX_CFG_REG("MSELCRB", 0xa4050182, 16, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		MSELB9_VIO, MSELB9_VIO2,
-		MSELB8_RGB, MSELB8_SYS,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0 ))
-	},
-	{}
-};
-
-static const struct pinmux_data_reg pinmux_data_regs[] = {
-	{ PINMUX_DATA_REG("PADR", 0xa4050120, 8, GROUP(
-		PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
-		PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PBDR", 0xa4050122, 8, GROUP(
-		PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
-		PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PCDR", 0xa4050124, 8, GROUP(
-		PTC7_DATA, 0, PTC5_DATA, PTC4_DATA,
-		PTC3_DATA, PTC2_DATA, 0, PTC0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PDDR", 0xa4050126, 8, GROUP(
-		PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
-		PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PEDR", 0xa4050128, 8, GROUP(
-		PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
-		0, 0, PTE1_DATA, PTE0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PFDR", 0xa405012a, 8, GROUP(
-		0, PTF6_DATA, PTF5_DATA, PTF4_DATA,
-		PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PGDR", 0xa405012c, 8, GROUP(
-		0, 0, 0, PTG4_DATA,
-		PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PHDR", 0xa405012e, 8, GROUP(
-		PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
-		PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PJDR", 0xa4050130, 8, GROUP(
-		PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, 0,
-		0, 0, PTJ1_DATA, PTJ0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PKDR", 0xa4050132, 8, GROUP(
-		0, PTK6_DATA, PTK5_DATA, PTK4_DATA,
-		PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PLDR", 0xa4050134, 8, GROUP(
-		PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
-		PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PMDR", 0xa4050136, 8, GROUP(
-		PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
-		PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PNDR", 0xa4050138, 8, GROUP(
-		PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
-		PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PQDR", 0xa405013a, 8, GROUP(
-		0, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
-		PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PRDR", 0xa405013c, 8, GROUP(
-		0, 0, 0, PTR4_DATA,
-		PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PSDR", 0xa405013e, 8, GROUP(
-		0, 0, 0, PTS4_DATA,
-		PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PTDR", 0xa4050160, 8, GROUP(
-		0, 0, 0, PTT4_DATA,
-		PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PUDR", 0xa4050162, 8, GROUP(
-		0, 0, 0, PTU4_DATA,
-		PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PVDR", 0xa4050164, 8, GROUP(
-		0, 0, 0, PTV4_DATA,
-		PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PWDR", 0xa4050166, 8, GROUP(
-		0, PTW6_DATA, PTW5_DATA, PTW4_DATA,
-		PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PXDR", 0xa4050168, 8, GROUP(
-		0, PTX6_DATA, PTX5_DATA, PTX4_DATA,
-		PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PYDR", 0xa405016a, 8, GROUP(
-		0, PTY6_DATA, PTY5_DATA, PTY4_DATA,
-		PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PZDR", 0xa405016c, 8, GROUP(
-		0, 0, PTZ5_DATA, PTZ4_DATA,
-		PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
-	},
-	{ },
-};
-
-const struct sh_pfc_soc_info sh7722_pinmux_info = {
-	.name = "sh7722_pfc",
-	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.func_gpios = pinmux_func_gpios,
-	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
-	.cfg_regs = pinmux_config_regs,
-	.data_regs = pinmux_data_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
deleted file mode 100644
index 6f08f527c010..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c
+++ /dev/null
@@ -1,1895 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * SH7723 Pinmux
- *
- *  Copyright (C) 2008  Magnus Damm
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <cpu/sh7723.h>
-
-#include "sh_pfc.h"
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
-	PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA,
-	PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
-	PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA,
-	PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
-	PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA,
-	PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
-	PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA,
-	PTE5_DATA, PTE4_DATA, PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA,
-	PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
-	PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA,
-	PTG5_DATA, PTG4_DATA, PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA,
-	PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
-	PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
-	PTJ7_DATA, PTJ5_DATA, PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA,
-	PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
-	PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
-	PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
-	PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA,
-	PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
-	PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
-	PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
-	PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA,
-	PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA,
-	PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
-	PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
-	PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
-	PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
-	PTT5_DATA, PTT4_DATA, PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
-	PTU5_DATA, PTU4_DATA, PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
-	PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
-	PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA,
-	PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
-	PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA,
-	PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
-	PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA,
-	PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
-	PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA,
-	PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
-	PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA,
-	PINMUX_DATA_END,
-
-	PINMUX_INPUT_BEGIN,
-	PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN,
-	PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN,
-	PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN,
-	PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN,
-	PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN,
-	PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN,
-	PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN,
-	PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN,
-	PTE5_IN, PTE4_IN, PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN,
-	PTF7_IN, PTF6_IN, PTF5_IN, PTF4_IN,
-	PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN,
-	PTH7_IN, PTH6_IN, PTH5_IN, PTH4_IN,
-	PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN,
-	PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN,
-	PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN,
-	PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN,
-	PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN,
-	PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN,
-	PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN,
-	PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
-	PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN,
-	PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN,
-	PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN,
-	PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN,
-	PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN,
-	PTS7_IN, PTS6_IN, PTS5_IN, PTS4_IN,
-	PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN,
-	PTT5_IN, PTT4_IN, PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN,
-	PTU5_IN, PTU4_IN, PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
-	PTV7_IN, PTV6_IN, PTV5_IN, PTV4_IN,
-	PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
-	PTW7_IN, PTW6_IN, PTW5_IN, PTW4_IN,
-	PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN,
-	PTX7_IN, PTX6_IN, PTX5_IN, PTX4_IN,
-	PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN,
-	PTY7_IN, PTY6_IN, PTY5_IN, PTY4_IN,
-	PTY3_IN, PTY2_IN, PTY1_IN, PTY0_IN,
-	PTZ7_IN, PTZ6_IN, PTZ5_IN, PTZ4_IN,
-	PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN,
-	PINMUX_INPUT_END,
-
-	PINMUX_OUTPUT_BEGIN,
-	PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT,
-	PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT,
-	PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
-	PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT,
-	PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT,
-	PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT,
-	PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT,
-	PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT,
-	PTE5_OUT, PTE4_OUT, PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT,
-	PTF7_OUT, PTF6_OUT, PTF5_OUT, PTF4_OUT,
-	PTF3_OUT, PTF2_OUT, PTF1_OUT, PTF0_OUT,
-	PTG5_OUT, PTG4_OUT, PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT,
-	PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT,
-	PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
-	PTJ7_OUT, PTJ5_OUT, PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT,
-	PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT,
-	PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT,
-	PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT,
-	PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT,
-	PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT,
-	PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
-	PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT,
-	PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT,
-	PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT,
-	PTR1_OUT, PTR0_OUT,
-	PTS7_OUT, PTS6_OUT, PTS5_OUT, PTS4_OUT,
-	PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT,
-	PTT5_OUT, PTT4_OUT, PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT,
-	PTU5_OUT, PTU4_OUT, PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT,
-	PTV7_OUT, PTV6_OUT, PTV5_OUT, PTV4_OUT,
-	PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT,
-	PTW7_OUT, PTW6_OUT, PTW5_OUT, PTW4_OUT,
-	PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT,
-	PTX7_OUT, PTX6_OUT, PTX5_OUT, PTX4_OUT,
-	PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT,
-	PTY7_OUT, PTY6_OUT, PTY5_OUT, PTY4_OUT,
-	PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT,
-	PTZ7_OUT, PTZ6_OUT, PTZ5_OUT, PTZ4_OUT,
-	PTZ3_OUT, PTZ2_OUT, PTZ1_OUT, PTZ0_OUT,
-	PINMUX_OUTPUT_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN,
-	PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN,
-	PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN,
-	PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN,
-	PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN,
-	PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN,
-	PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN,
-	PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN,
-	PTE5_FN, PTE4_FN, PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN,
-	PTF7_FN, PTF6_FN, PTF5_FN, PTF4_FN,
-	PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN,
-	PTG5_FN, PTG4_FN, PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN,
-	PTH7_FN, PTH6_FN, PTH5_FN, PTH4_FN,
-	PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN,
-	PTJ7_FN, PTJ5_FN, PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN,
-	PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN,
-	PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN,
-	PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN,
-	PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN,
-	PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN,
-	PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN,
-	PTN7_FN, PTN6_FN, PTN5_FN, PTN4_FN,
-	PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN,
-	PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN,
-	PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN,
-	PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN,
-	PTS7_FN, PTS6_FN, PTS5_FN, PTS4_FN,
-	PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN,
-	PTT5_FN, PTT4_FN, PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN,
-	PTU5_FN, PTU4_FN, PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN,
-	PTV7_FN, PTV6_FN, PTV5_FN, PTV4_FN,
-	PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN,
-	PTW7_FN, PTW6_FN, PTW5_FN, PTW4_FN,
-	PTW3_FN, PTW2_FN, PTW1_FN, PTW0_FN,
-	PTX7_FN, PTX6_FN, PTX5_FN, PTX4_FN,
-	PTX3_FN, PTX2_FN, PTX1_FN, PTX0_FN,
-	PTY7_FN, PTY6_FN, PTY5_FN, PTY4_FN,
-	PTY3_FN, PTY2_FN, PTY1_FN, PTY0_FN,
-	PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN,
-	PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN,
-
-
-	PSA15_PSA14_FN1, PSA15_PSA14_FN2,
-	PSA13_PSA12_FN1, PSA13_PSA12_FN2,
-	PSA11_PSA10_FN1, PSA11_PSA10_FN2,
-	PSA5_PSA4_FN1, PSA5_PSA4_FN2, PSA5_PSA4_FN3,
-	PSA3_PSA2_FN1, PSA3_PSA2_FN2,
-	PSB15_PSB14_FN1, PSB15_PSB14_FN2,
-	PSB13_PSB12_LCDC_RGB, PSB13_PSB12_LCDC_SYS,
-	PSB9_PSB8_FN1, PSB9_PSB8_FN2, PSB9_PSB8_FN3,
-	PSB7_PSB6_FN1, PSB7_PSB6_FN2,
-	PSB5_PSB4_FN1, PSB5_PSB4_FN2,
-	PSB3_PSB2_FN1, PSB3_PSB2_FN2,
-	PSC15_PSC14_FN1, PSC15_PSC14_FN2,
-	PSC13_PSC12_FN1, PSC13_PSC12_FN2,
-	PSC11_PSC10_FN1, PSC11_PSC10_FN2, PSC11_PSC10_FN3,
-	PSC9_PSC8_FN1, PSC9_PSC8_FN2,
-	PSC7_PSC6_FN1, PSC7_PSC6_FN2, PSC7_PSC6_FN3,
-	PSD15_PSD14_FN1, PSD15_PSD14_FN2,
-	PSD13_PSD12_FN1, PSD13_PSD12_FN2,
-	PSD11_PSD10_FN1, PSD11_PSD10_FN2, PSD11_PSD10_FN3,
-	PSD9_PSD8_FN1, PSD9_PSD8_FN2,
-	PSD7_PSD6_FN1, PSD7_PSD6_FN2,
-	PSD5_PSD4_FN1, PSD5_PSD4_FN2,
-	PSD3_PSD2_FN1, PSD3_PSD2_FN2,
-	PSD1_PSD0_FN1, PSD1_PSD0_FN2,
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-	SCIF0_PTT_TXD_MARK, SCIF0_PTT_RXD_MARK,
-	SCIF0_PTT_SCK_MARK, SCIF0_PTU_TXD_MARK,
-	SCIF0_PTU_RXD_MARK, SCIF0_PTU_SCK_MARK,
-
-	SCIF1_PTS_TXD_MARK, SCIF1_PTS_RXD_MARK,
-	SCIF1_PTS_SCK_MARK, SCIF1_PTV_TXD_MARK,
-	SCIF1_PTV_RXD_MARK, SCIF1_PTV_SCK_MARK,
-
-	SCIF2_PTT_TXD_MARK, SCIF2_PTT_RXD_MARK,
-	SCIF2_PTT_SCK_MARK, SCIF2_PTU_TXD_MARK,
-	SCIF2_PTU_RXD_MARK, SCIF2_PTU_SCK_MARK,
-
-	SCIF3_PTS_TXD_MARK, SCIF3_PTS_RXD_MARK,
-	SCIF3_PTS_SCK_MARK, SCIF3_PTS_RTS_MARK,
-	SCIF3_PTS_CTS_MARK, SCIF3_PTV_TXD_MARK,
-	SCIF3_PTV_RXD_MARK, SCIF3_PTV_SCK_MARK,
-	SCIF3_PTV_RTS_MARK, SCIF3_PTV_CTS_MARK,
-
-	SCIF4_PTE_TXD_MARK, SCIF4_PTE_RXD_MARK,
-	SCIF4_PTE_SCK_MARK, SCIF4_PTN_TXD_MARK,
-	SCIF4_PTN_RXD_MARK, SCIF4_PTN_SCK_MARK,
-
-	SCIF5_PTE_TXD_MARK, SCIF5_PTE_RXD_MARK,
-	SCIF5_PTE_SCK_MARK, SCIF5_PTN_TXD_MARK,
-	SCIF5_PTN_RXD_MARK, SCIF5_PTN_SCK_MARK,
-
-	VIO_D15_MARK, VIO_D14_MARK, VIO_D13_MARK, VIO_D12_MARK,
-	VIO_D11_MARK, VIO_D10_MARK, VIO_D9_MARK, VIO_D8_MARK,
-	VIO_D7_MARK, VIO_D6_MARK, VIO_D5_MARK, VIO_D4_MARK,
-	VIO_D3_MARK, VIO_D2_MARK, VIO_D1_MARK, VIO_D0_MARK,
-	VIO_FLD_MARK, VIO_CKO_MARK,
-	VIO_VD1_MARK, VIO_HD1_MARK, VIO_CLK1_MARK,
-	VIO_HD2_MARK, VIO_VD2_MARK, VIO_CLK2_MARK,
-
-	LCDD23_MARK, LCDD22_MARK, LCDD21_MARK, LCDD20_MARK,
-	LCDD19_MARK, LCDD18_MARK, LCDD17_MARK, LCDD16_MARK,
-	LCDD15_MARK, LCDD14_MARK, LCDD13_MARK, LCDD12_MARK,
-	LCDD11_MARK, LCDD10_MARK, LCDD9_MARK, LCDD8_MARK,
-	LCDD7_MARK, LCDD6_MARK, LCDD5_MARK, LCDD4_MARK,
-	LCDD3_MARK, LCDD2_MARK, LCDD1_MARK, LCDD0_MARK,
-	LCDDON_MARK, LCDVCPWC_MARK, LCDVEPWC_MARK,
-	LCDVSYN_MARK, LCDDCK_MARK, LCDHSYN_MARK, LCDDISP_MARK,
-	LCDRS_MARK, LCDCS_MARK, LCDWR_MARK, LCDRD_MARK,
-	LCDLCLK_PTR_MARK, LCDLCLK_PTW_MARK,
-
-	IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK,
-	IRQ4_MARK, IRQ5_MARK, IRQ6_MARK, IRQ7_MARK,
-
-	AUDATA3_MARK, AUDATA2_MARK, AUDATA1_MARK, AUDATA0_MARK,
-	AUDCK_MARK, AUDSYNC_MARK,
-
-	SDHI0CD_PTD_MARK, SDHI0WP_PTD_MARK,
-	SDHI0D3_PTD_MARK, SDHI0D2_PTD_MARK,
-	SDHI0D1_PTD_MARK, SDHI0D0_PTD_MARK,
-	SDHI0CMD_PTD_MARK, SDHI0CLK_PTD_MARK,
-
-	SDHI0CD_PTS_MARK, SDHI0WP_PTS_MARK,
-	SDHI0D3_PTS_MARK, SDHI0D2_PTS_MARK,
-	SDHI0D1_PTS_MARK, SDHI0D0_PTS_MARK,
-	SDHI0CMD_PTS_MARK, SDHI0CLK_PTS_MARK,
-
-	SDHI1CD_MARK, SDHI1WP_MARK, SDHI1D3_MARK, SDHI1D2_MARK,
-	SDHI1D1_MARK, SDHI1D0_MARK, SDHI1CMD_MARK, SDHI1CLK_MARK,
-
-	SIUAFCK_MARK, SIUAILR_MARK, SIUAIBT_MARK, SIUAISLD_MARK,
-	SIUAOLR_MARK, SIUAOBT_MARK, SIUAOSLD_MARK, SIUAMCK_MARK,
-	SIUAISPD_MARK, SIUAOSPD_MARK,
-
-	SIUBFCK_MARK, SIUBILR_MARK, SIUBIBT_MARK, SIUBISLD_MARK,
-	SIUBOLR_MARK, SIUBOBT_MARK, SIUBOSLD_MARK, SIUBMCK_MARK,
-
-	IRDA_IN_MARK, IRDA_OUT_MARK,
-
-	DV_CLKI_MARK, DV_CLK_MARK, DV_HSYNC_MARK, DV_VSYNC_MARK,
-	DV_D15_MARK, DV_D14_MARK, DV_D13_MARK, DV_D12_MARK,
-	DV_D11_MARK, DV_D10_MARK, DV_D9_MARK, DV_D8_MARK,
-	DV_D7_MARK, DV_D6_MARK, DV_D5_MARK, DV_D4_MARK,
-	DV_D3_MARK, DV_D2_MARK, DV_D1_MARK, DV_D0_MARK,
-
-	KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, KEYIN4_MARK,
-	KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
-	KEYOUT4_IN6_MARK, KEYOUT5_IN5_MARK,
-
-	MSIOF0_PTF_TXD_MARK, MSIOF0_PTF_RXD_MARK, MSIOF0_PTF_MCK_MARK,
-	MSIOF0_PTF_TSYNC_MARK, MSIOF0_PTF_TSCK_MARK, MSIOF0_PTF_RSYNC_MARK,
-	MSIOF0_PTF_RSCK_MARK, MSIOF0_PTF_SS1_MARK, MSIOF0_PTF_SS2_MARK,
-
-	MSIOF0_PTT_TXD_MARK, MSIOF0_PTT_RXD_MARK, MSIOF0_PTX_MCK_MARK,
-	MSIOF0_PTT_TSYNC_MARK, MSIOF0_PTT_TSCK_MARK, MSIOF0_PTT_RSYNC_MARK,
-	MSIOF0_PTT_RSCK_MARK, MSIOF0_PTT_SS1_MARK, MSIOF0_PTT_SS2_MARK,
-
-	MSIOF1_TXD_MARK, MSIOF1_RXD_MARK, MSIOF1_MCK_MARK,
-	MSIOF1_TSYNC_MARK, MSIOF1_TSCK_MARK, MSIOF1_RSYNC_MARK,
-	MSIOF1_RSCK_MARK, MSIOF1_SS1_MARK, MSIOF1_SS2_MARK,
-
-	TS0_SDAT_MARK, TS0_SCK_MARK, TS0_SDEN_MARK, TS0_SPSYNC_MARK,
-
-	FCE_MARK, NAF7_MARK, NAF6_MARK, NAF5_MARK, NAF4_MARK,
-	NAF3_MARK, NAF2_MARK, NAF1_MARK, NAF0_MARK, FCDE_MARK,
-	FOE_MARK, FSC_MARK, FWE_MARK, FRB_MARK,
-
-	DACK1_MARK, DREQ1_MARK, DACK0_MARK, DREQ0_MARK,
-
-	AN3_MARK, AN2_MARK, AN1_MARK, AN0_MARK, ADTRG_MARK,
-
-	STATUS0_MARK, PDSTATUS_MARK,
-
-	TPUTO3_MARK, TPUTO2_MARK, TPUTO1_MARK, TPUTO0_MARK,
-
-	D31_MARK, D30_MARK, D29_MARK, D28_MARK,
-	D27_MARK, D26_MARK, D25_MARK, D24_MARK,
-	D23_MARK, D22_MARK, D21_MARK, D20_MARK,
-	D19_MARK, D18_MARK, D17_MARK, D16_MARK,
-	IOIS16_MARK, WAIT_MARK, BS_MARK,
-	A25_MARK, A24_MARK, A23_MARK, A22_MARK,
-	CS6B_CE1B_MARK, CS6A_CE2B_MARK,
-	CS5B_CE1A_MARK, CS5A_CE2A_MARK,
-	WE3_ICIOWR_MARK, WE2_ICIORD_MARK,
-
-	IDED15_MARK, IDED14_MARK, IDED13_MARK, IDED12_MARK,
-	IDED11_MARK, IDED10_MARK, IDED9_MARK, IDED8_MARK,
-	IDED7_MARK, IDED6_MARK, IDED5_MARK, IDED4_MARK,
-	IDED3_MARK, IDED2_MARK, IDED1_MARK, IDED0_MARK,
-	DIRECTION_MARK, EXBUF_ENB_MARK, IDERST_MARK, IODACK_MARK,
-	IODREQ_MARK, IDEIORDY_MARK, IDEINT_MARK, IDEIOWR_MARK,
-	IDEIORD_MARK, IDECS1_MARK, IDECS0_MARK, IDEA2_MARK,
-	IDEA1_MARK, IDEA0_MARK,
-	PINMUX_MARK_END,
-};
-
-static const u16 pinmux_data[] = {
-	/* PTA GPIO */
-	PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
-	PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
-	PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT),
-	PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT),
-	PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT),
-	PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT),
-	PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT),
-	PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT),
-
-	/* PTB GPIO */
-	PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT),
-	PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT),
-	PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT),
-	PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT),
-	PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT),
-	PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT),
-	PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT),
-	PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT),
-
-	/* PTC GPIO */
-	PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT),
-	PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT),
-	PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT),
-	PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT),
-	PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT),
-	PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT),
-	PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT),
-	PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT),
-
-	/* PTD GPIO */
-	PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT),
-	PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT),
-	PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT),
-	PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT),
-	PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT),
-	PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT),
-	PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT),
-	PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT),
-
-	/* PTE GPIO */
-	PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT),
-	PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT),
-	PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT),
-	PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT),
-	PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT),
-	PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT),
-
-	/* PTF GPIO */
-	PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT),
-	PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT),
-	PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT),
-	PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT),
-	PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT),
-	PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT),
-	PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT),
-	PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT),
-
-	/* PTG GPIO */
-	PINMUX_DATA(PTG5_DATA, PTG5_OUT),
-	PINMUX_DATA(PTG4_DATA, PTG4_OUT),
-	PINMUX_DATA(PTG3_DATA, PTG3_OUT),
-	PINMUX_DATA(PTG2_DATA, PTG2_OUT),
-	PINMUX_DATA(PTG1_DATA, PTG1_OUT),
-	PINMUX_DATA(PTG0_DATA, PTG0_OUT),
-
-	/* PTH GPIO */
-	PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT),
-	PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT),
-	PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT),
-	PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT),
-	PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT),
-	PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT),
-	PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT),
-	PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT),
-
-	/* PTJ GPIO */
-	PINMUX_DATA(PTJ7_DATA, PTJ7_OUT),
-	PINMUX_DATA(PTJ5_DATA, PTJ5_OUT),
-	PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT),
-	PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT),
-	PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT),
-	PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT),
-
-	/* PTK GPIO */
-	PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT),
-	PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT),
-	PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT),
-	PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT),
-	PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT),
-	PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT),
-	PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT),
-	PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT),
-
-	/* PTL GPIO */
-	PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT),
-	PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT),
-	PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT),
-	PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT),
-	PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT),
-	PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT),
-	PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT),
-	PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT),
-
-	/* PTM GPIO */
-	PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT),
-	PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT),
-	PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT),
-	PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT),
-	PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT),
-	PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT),
-	PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT),
-	PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT),
-
-	/* PTN GPIO */
-	PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT),
-	PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT),
-	PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT),
-	PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT),
-	PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT),
-	PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT),
-	PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT),
-	PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT),
-
-	/* PTQ GPIO */
-	PINMUX_DATA(PTQ3_DATA, PTQ3_IN),
-	PINMUX_DATA(PTQ2_DATA, PTQ2_IN),
-	PINMUX_DATA(PTQ1_DATA, PTQ1_IN),
-	PINMUX_DATA(PTQ0_DATA, PTQ0_IN),
-
-	/* PTR GPIO */
-	PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT),
-	PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT),
-	PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT),
-	PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT),
-	PINMUX_DATA(PTR3_DATA, PTR3_IN),
-	PINMUX_DATA(PTR2_DATA, PTR2_IN),
-	PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT),
-	PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT),
-
-	/* PTS GPIO */
-	PINMUX_DATA(PTS7_DATA, PTS7_IN, PTS7_OUT),
-	PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT),
-	PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT),
-	PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT),
-	PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT),
-	PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT),
-	PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT),
-	PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT),
-
-	/* PTT GPIO */
-	PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT),
-	PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT),
-	PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT),
-	PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT),
-	PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT),
-	PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT),
-
-	/* PTU GPIO */
-	PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT),
-	PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT),
-	PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT),
-	PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT),
-	PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT),
-	PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT),
-
-	/* PTV GPIO */
-	PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT),
-	PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT),
-	PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT),
-	PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT),
-	PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT),
-	PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT),
-	PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT),
-	PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT),
-
-	/* PTW GPIO */
-	PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT),
-	PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT),
-	PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT),
-	PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT),
-	PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT),
-	PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT),
-	PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT),
-	PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT),
-
-	/* PTX GPIO */
-	PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT),
-	PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT),
-	PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT),
-	PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT),
-	PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT),
-	PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT),
-	PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT),
-	PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT),
-
-	/* PTY GPIO */
-	PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT),
-	PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT),
-	PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT),
-	PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT),
-	PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT),
-	PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT),
-	PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT),
-	PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT),
-
-	/* PTZ GPIO */
-	PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT),
-	PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT),
-	PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT),
-	PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT),
-	PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT),
-	PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT),
-	PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT),
-	PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT),
-
-	/* PTA FN */
-	PINMUX_DATA(D23_MARK, PSA15_PSA14_FN1, PTA7_FN),
-	PINMUX_DATA(KEYOUT2_MARK, PSA15_PSA14_FN2, PTA7_FN),
-	PINMUX_DATA(D22_MARK, PSA15_PSA14_FN1, PTA6_FN),
-	PINMUX_DATA(KEYOUT1_MARK, PSA15_PSA14_FN2, PTA6_FN),
-	PINMUX_DATA(D21_MARK, PSA15_PSA14_FN1, PTA5_FN),
-	PINMUX_DATA(KEYOUT0_MARK, PSA15_PSA14_FN2, PTA5_FN),
-	PINMUX_DATA(D20_MARK, PSA15_PSA14_FN1, PTA4_FN),
-	PINMUX_DATA(KEYIN4_MARK, PSA15_PSA14_FN2, PTA4_FN),
-	PINMUX_DATA(D19_MARK, PSA15_PSA14_FN1, PTA3_FN),
-	PINMUX_DATA(KEYIN3_MARK, PSA15_PSA14_FN2, PTA3_FN),
-	PINMUX_DATA(D18_MARK, PSA15_PSA14_FN1, PTA2_FN),
-	PINMUX_DATA(KEYIN2_MARK, PSA15_PSA14_FN2, PTA2_FN),
-	PINMUX_DATA(D17_MARK, PSA15_PSA14_FN1, PTA1_FN),
-	PINMUX_DATA(KEYIN1_MARK, PSA15_PSA14_FN2, PTA1_FN),
-	PINMUX_DATA(D16_MARK, PSA15_PSA14_FN1, PTA0_FN),
-	PINMUX_DATA(KEYIN0_MARK, PSA15_PSA14_FN2, PTA0_FN),
-
-	/* PTB FN */
-	PINMUX_DATA(D31_MARK, PTB7_FN),
-	PINMUX_DATA(D30_MARK, PTB6_FN),
-	PINMUX_DATA(D29_MARK, PTB5_FN),
-	PINMUX_DATA(D28_MARK, PTB4_FN),
-	PINMUX_DATA(D27_MARK, PTB3_FN),
-	PINMUX_DATA(D26_MARK, PSA15_PSA14_FN1, PTB2_FN),
-	PINMUX_DATA(KEYOUT5_IN5_MARK, PSA15_PSA14_FN2, PTB2_FN),
-	PINMUX_DATA(D25_MARK, PSA15_PSA14_FN1, PTB1_FN),
-	PINMUX_DATA(KEYOUT4_IN6_MARK, PSA15_PSA14_FN2, PTB1_FN),
-	PINMUX_DATA(D24_MARK, PSA15_PSA14_FN1, PTB0_FN),
-	PINMUX_DATA(KEYOUT3_MARK, PSA15_PSA14_FN2, PTB0_FN),
-
-	/* PTC FN */
-	PINMUX_DATA(IDED15_MARK, PSA11_PSA10_FN1, PTC7_FN),
-	PINMUX_DATA(SDHI1CD_MARK, PSA11_PSA10_FN2, PTC7_FN),
-	PINMUX_DATA(IDED14_MARK, PSA11_PSA10_FN1, PTC6_FN),
-	PINMUX_DATA(SDHI1WP_MARK, PSA11_PSA10_FN2, PTC6_FN),
-	PINMUX_DATA(IDED13_MARK, PSA11_PSA10_FN1, PTC5_FN),
-	PINMUX_DATA(SDHI1D3_MARK, PSA11_PSA10_FN2, PTC5_FN),
-	PINMUX_DATA(IDED12_MARK, PSA11_PSA10_FN1, PTC4_FN),
-	PINMUX_DATA(SDHI1D2_MARK, PSA11_PSA10_FN2, PTC4_FN),
-	PINMUX_DATA(IDED11_MARK, PSA11_PSA10_FN1, PTC3_FN),
-	PINMUX_DATA(SDHI1D1_MARK, PSA11_PSA10_FN2, PTC3_FN),
-	PINMUX_DATA(IDED10_MARK, PSA11_PSA10_FN1, PTC2_FN),
-	PINMUX_DATA(SDHI1D0_MARK, PSA11_PSA10_FN2, PTC2_FN),
-	PINMUX_DATA(IDED9_MARK, PSA11_PSA10_FN1, PTC1_FN),
-	PINMUX_DATA(SDHI1CMD_MARK, PSA11_PSA10_FN2, PTC1_FN),
-	PINMUX_DATA(IDED8_MARK, PSA11_PSA10_FN1, PTC0_FN),
-	PINMUX_DATA(SDHI1CLK_MARK, PSA11_PSA10_FN2, PTC0_FN),
-
-	/* PTD FN */
-	PINMUX_DATA(IDED7_MARK, PSA11_PSA10_FN1, PTD7_FN),
-	PINMUX_DATA(SDHI0CD_PTD_MARK, PSA11_PSA10_FN2, PTD7_FN),
-	PINMUX_DATA(IDED6_MARK, PSA11_PSA10_FN1, PTD6_FN),
-	PINMUX_DATA(SDHI0WP_PTD_MARK, PSA11_PSA10_FN2, PTD6_FN),
-	PINMUX_DATA(IDED5_MARK, PSA11_PSA10_FN1, PTD5_FN),
-	PINMUX_DATA(SDHI0D3_PTD_MARK, PSA11_PSA10_FN2, PTD5_FN),
-	PINMUX_DATA(IDED4_MARK, PSA11_PSA10_FN1, PTD4_FN),
-	PINMUX_DATA(SDHI0D2_PTD_MARK, PSA11_PSA10_FN2, PTD4_FN),
-	PINMUX_DATA(IDED3_MARK, PSA11_PSA10_FN1, PTD3_FN),
-	PINMUX_DATA(SDHI0D1_PTD_MARK, PSA11_PSA10_FN2, PTD3_FN),
-	PINMUX_DATA(IDED2_MARK, PSA11_PSA10_FN1, PTD2_FN),
-	PINMUX_DATA(SDHI0D0_PTD_MARK, PSA11_PSA10_FN2, PTD2_FN),
-	PINMUX_DATA(IDED1_MARK, PSA11_PSA10_FN1, PTD1_FN),
-	PINMUX_DATA(SDHI0CMD_PTD_MARK, PSA11_PSA10_FN2, PTD1_FN),
-	PINMUX_DATA(IDED0_MARK, PSA11_PSA10_FN1, PTD0_FN),
-	PINMUX_DATA(SDHI0CLK_PTD_MARK, PSA11_PSA10_FN2, PTD0_FN),
-
-	/* PTE FN */
-	PINMUX_DATA(DIRECTION_MARK, PSA11_PSA10_FN1, PTE5_FN),
-	PINMUX_DATA(SCIF5_PTE_SCK_MARK, PSA11_PSA10_FN2, PTE5_FN),
-	PINMUX_DATA(EXBUF_ENB_MARK, PSA11_PSA10_FN1, PTE4_FN),
-	PINMUX_DATA(SCIF5_PTE_RXD_MARK, PSA11_PSA10_FN2, PTE4_FN),
-	PINMUX_DATA(IDERST_MARK, PSA11_PSA10_FN1, PTE3_FN),
-	PINMUX_DATA(SCIF5_PTE_TXD_MARK, PSA11_PSA10_FN2, PTE3_FN),
-	PINMUX_DATA(IODACK_MARK, PSA11_PSA10_FN1, PTE2_FN),
-	PINMUX_DATA(SCIF4_PTE_SCK_MARK, PSA11_PSA10_FN2, PTE2_FN),
-	PINMUX_DATA(IODREQ_MARK, PSA11_PSA10_FN1, PTE1_FN),
-	PINMUX_DATA(SCIF4_PTE_RXD_MARK, PSA11_PSA10_FN2, PTE1_FN),
-	PINMUX_DATA(IDEIORDY_MARK, PSA11_PSA10_FN1, PTE0_FN),
-	PINMUX_DATA(SCIF4_PTE_TXD_MARK, PSA11_PSA10_FN2, PTE0_FN),
-
-	/* PTF FN */
-	PINMUX_DATA(IDEINT_MARK, PTF7_FN),
-	PINMUX_DATA(IDEIOWR_MARK, PSA5_PSA4_FN1, PTF6_FN),
-	PINMUX_DATA(MSIOF0_PTF_SS2_MARK, PSA5_PSA4_FN2, PTF6_FN),
-	PINMUX_DATA(MSIOF0_PTF_RSYNC_MARK, PSA5_PSA4_FN3, PTF6_FN),
-	PINMUX_DATA(IDEIORD_MARK, PSA5_PSA4_FN1, PTF5_FN),
-	PINMUX_DATA(MSIOF0_PTF_SS1_MARK, PSA5_PSA4_FN2, PTF5_FN),
-	PINMUX_DATA(MSIOF0_PTF_RSCK_MARK, PSA5_PSA4_FN3, PTF5_FN),
-	PINMUX_DATA(IDECS1_MARK, PSA11_PSA10_FN1, PTF4_FN),
-	PINMUX_DATA(MSIOF0_PTF_TSYNC_MARK, PSA11_PSA10_FN2, PTF4_FN),
-	PINMUX_DATA(IDECS0_MARK, PSA11_PSA10_FN1, PTF3_FN),
-	PINMUX_DATA(MSIOF0_PTF_TSCK_MARK, PSA11_PSA10_FN2, PTF3_FN),
-	PINMUX_DATA(IDEA2_MARK, PSA11_PSA10_FN1, PTF2_FN),
-	PINMUX_DATA(MSIOF0_PTF_RXD_MARK, PSA11_PSA10_FN2, PTF2_FN),
-	PINMUX_DATA(IDEA1_MARK, PSA11_PSA10_FN1, PTF1_FN),
-	PINMUX_DATA(MSIOF0_PTF_TXD_MARK, PSA11_PSA10_FN2, PTF1_FN),
-	PINMUX_DATA(IDEA0_MARK, PSA11_PSA10_FN1, PTF0_FN),
-	PINMUX_DATA(MSIOF0_PTF_MCK_MARK, PSA11_PSA10_FN2, PTF0_FN),
-
-	/* PTG FN */
-	PINMUX_DATA(AUDCK_MARK, PTG5_FN),
-	PINMUX_DATA(AUDSYNC_MARK, PTG4_FN),
-	PINMUX_DATA(AUDATA3_MARK, PSA3_PSA2_FN1, PTG3_FN),
-	PINMUX_DATA(TPUTO3_MARK, PSA3_PSA2_FN2, PTG3_FN),
-	PINMUX_DATA(AUDATA2_MARK, PSA3_PSA2_FN1, PTG2_FN),
-	PINMUX_DATA(TPUTO2_MARK, PSA3_PSA2_FN2, PTG2_FN),
-	PINMUX_DATA(AUDATA1_MARK, PSA3_PSA2_FN1, PTG1_FN),
-	PINMUX_DATA(TPUTO1_MARK, PSA3_PSA2_FN2, PTG1_FN),
-	PINMUX_DATA(AUDATA0_MARK, PSA3_PSA2_FN1, PTG0_FN),
-	PINMUX_DATA(TPUTO0_MARK, PSA3_PSA2_FN2, PTG0_FN),
-
-	/* PTG FN */
-	PINMUX_DATA(LCDVCPWC_MARK, PTH7_FN),
-	PINMUX_DATA(LCDRD_MARK, PSB15_PSB14_FN1, PTH6_FN),
-	PINMUX_DATA(DV_CLKI_MARK, PSB15_PSB14_FN2, PTH6_FN),
-	PINMUX_DATA(LCDVSYN_MARK, PSB15_PSB14_FN1, PTH5_FN),
-	PINMUX_DATA(DV_CLK_MARK, PSB15_PSB14_FN2, PTH5_FN),
-	PINMUX_DATA(LCDDISP_MARK, PSB13_PSB12_LCDC_RGB, PTH4_FN),
-	PINMUX_DATA(LCDRS_MARK, PSB13_PSB12_LCDC_SYS, PTH4_FN),
-	PINMUX_DATA(LCDHSYN_MARK, PSB13_PSB12_LCDC_RGB, PTH3_FN),
-	PINMUX_DATA(LCDCS_MARK, PSB13_PSB12_LCDC_SYS, PTH3_FN),
-	PINMUX_DATA(LCDDON_MARK, PTH2_FN),
-	PINMUX_DATA(LCDDCK_MARK, PSB13_PSB12_LCDC_RGB, PTH1_FN),
-	PINMUX_DATA(LCDWR_MARK, PSB13_PSB12_LCDC_SYS, PTH1_FN),
-	PINMUX_DATA(LCDVEPWC_MARK, PTH0_FN),
-
-	/* PTJ FN */
-	PINMUX_DATA(STATUS0_MARK, PTJ7_FN),
-	PINMUX_DATA(PDSTATUS_MARK, PTJ5_FN),
-	PINMUX_DATA(A25_MARK, PTJ3_FN),
-	PINMUX_DATA(A24_MARK, PTJ2_FN),
-	PINMUX_DATA(A23_MARK, PTJ1_FN),
-	PINMUX_DATA(A22_MARK, PTJ0_FN),
-
-	/* PTK FN */
-	PINMUX_DATA(SIUAFCK_MARK, PTK7_FN),
-	PINMUX_DATA(SIUAILR_MARK, PSB9_PSB8_FN1, PTK6_FN),
-	PINMUX_DATA(MSIOF1_SS2_MARK, PSB9_PSB8_FN2, PTK6_FN),
-	PINMUX_DATA(MSIOF1_RSYNC_MARK, PSB9_PSB8_FN3, PTK6_FN),
-	PINMUX_DATA(SIUAIBT_MARK, PSB9_PSB8_FN1, PTK5_FN),
-	PINMUX_DATA(MSIOF1_SS1_MARK, PSB9_PSB8_FN2, PTK5_FN),
-	PINMUX_DATA(MSIOF1_RSCK_MARK, PSB9_PSB8_FN3, PTK5_FN),
-	PINMUX_DATA(SIUAISLD_MARK, PSB7_PSB6_FN1, PTK4_FN),
-	PINMUX_DATA(MSIOF1_RXD_MARK, PSB7_PSB6_FN2, PTK4_FN),
-	PINMUX_DATA(SIUAOLR_MARK, PSB7_PSB6_FN1, PTK3_FN),
-	PINMUX_DATA(MSIOF1_TSYNC_MARK, PSB7_PSB6_FN2, PTK3_FN),
-	PINMUX_DATA(SIUAOBT_MARK, PSB7_PSB6_FN1, PTK2_FN),
-	PINMUX_DATA(MSIOF1_TSCK_MARK, PSB7_PSB6_FN2, PTK2_FN),
-	PINMUX_DATA(SIUAOSLD_MARK, PSB7_PSB6_FN1, PTK1_FN),
-	PINMUX_DATA(MSIOF1_RXD_MARK, PSB7_PSB6_FN2, PTK1_FN),
-	PINMUX_DATA(SIUAMCK_MARK, PSB7_PSB6_FN1, PTK0_FN),
-	PINMUX_DATA(MSIOF1_MCK_MARK, PSB7_PSB6_FN2, PTK0_FN),
-
-	/* PTL FN */
-	PINMUX_DATA(LCDD15_MARK, PSB5_PSB4_FN1, PTL7_FN),
-	PINMUX_DATA(DV_D15_MARK, PSB5_PSB4_FN2, PTL7_FN),
-	PINMUX_DATA(LCDD14_MARK, PSB5_PSB4_FN1, PTL6_FN),
-	PINMUX_DATA(DV_D14_MARK, PSB5_PSB4_FN2, PTL6_FN),
-	PINMUX_DATA(LCDD13_MARK, PSB5_PSB4_FN1, PTL5_FN),
-	PINMUX_DATA(DV_D13_MARK, PSB5_PSB4_FN2, PTL5_FN),
-	PINMUX_DATA(LCDD12_MARK, PSB5_PSB4_FN1, PTL4_FN),
-	PINMUX_DATA(DV_D12_MARK, PSB5_PSB4_FN2, PTL4_FN),
-	PINMUX_DATA(LCDD11_MARK, PSB5_PSB4_FN1, PTL3_FN),
-	PINMUX_DATA(DV_D11_MARK, PSB5_PSB4_FN2, PTL3_FN),
-	PINMUX_DATA(LCDD10_MARK, PSB5_PSB4_FN1, PTL2_FN),
-	PINMUX_DATA(DV_D10_MARK, PSB5_PSB4_FN2, PTL2_FN),
-	PINMUX_DATA(LCDD9_MARK, PSB5_PSB4_FN1, PTL1_FN),
-	PINMUX_DATA(DV_D9_MARK, PSB5_PSB4_FN2, PTL1_FN),
-	PINMUX_DATA(LCDD8_MARK, PSB5_PSB4_FN1, PTL0_FN),
-	PINMUX_DATA(DV_D8_MARK, PSB5_PSB4_FN2, PTL0_FN),
-
-	/* PTM FN */
-	PINMUX_DATA(LCDD7_MARK, PSB5_PSB4_FN1, PTM7_FN),
-	PINMUX_DATA(DV_D7_MARK, PSB5_PSB4_FN2, PTM7_FN),
-	PINMUX_DATA(LCDD6_MARK, PSB5_PSB4_FN1, PTM6_FN),
-	PINMUX_DATA(DV_D6_MARK, PSB5_PSB4_FN2, PTM6_FN),
-	PINMUX_DATA(LCDD5_MARK, PSB5_PSB4_FN1, PTM5_FN),
-	PINMUX_DATA(DV_D5_MARK, PSB5_PSB4_FN2, PTM5_FN),
-	PINMUX_DATA(LCDD4_MARK, PSB5_PSB4_FN1, PTM4_FN),
-	PINMUX_DATA(DV_D4_MARK, PSB5_PSB4_FN2, PTM4_FN),
-	PINMUX_DATA(LCDD3_MARK, PSB5_PSB4_FN1, PTM3_FN),
-	PINMUX_DATA(DV_D3_MARK, PSB5_PSB4_FN2, PTM3_FN),
-	PINMUX_DATA(LCDD2_MARK, PSB5_PSB4_FN1, PTM2_FN),
-	PINMUX_DATA(DV_D2_MARK, PSB5_PSB4_FN2, PTM2_FN),
-	PINMUX_DATA(LCDD1_MARK, PSB5_PSB4_FN1, PTM1_FN),
-	PINMUX_DATA(DV_D1_MARK, PSB5_PSB4_FN2, PTM1_FN),
-	PINMUX_DATA(LCDD0_MARK, PSB5_PSB4_FN1, PTM0_FN),
-	PINMUX_DATA(DV_D0_MARK, PSB5_PSB4_FN2, PTM0_FN),
-
-	/* PTN FN */
-	PINMUX_DATA(LCDD23_MARK, PSB3_PSB2_FN1, PTN7_FN),
-	PINMUX_DATA(SCIF5_PTN_SCK_MARK, PSB3_PSB2_FN2, PTN7_FN),
-	PINMUX_DATA(LCDD22_MARK, PSB3_PSB2_FN1, PTN6_FN),
-	PINMUX_DATA(SCIF5_PTN_RXD_MARK, PSB3_PSB2_FN2, PTN6_FN),
-	PINMUX_DATA(LCDD21_MARK, PSB3_PSB2_FN1, PTN5_FN),
-	PINMUX_DATA(SCIF5_PTN_TXD_MARK, PSB3_PSB2_FN2, PTN5_FN),
-	PINMUX_DATA(LCDD20_MARK, PSB3_PSB2_FN1, PTN4_FN),
-	PINMUX_DATA(SCIF4_PTN_SCK_MARK, PSB3_PSB2_FN2, PTN4_FN),
-	PINMUX_DATA(LCDD19_MARK, PSB3_PSB2_FN1, PTN3_FN),
-	PINMUX_DATA(SCIF4_PTN_RXD_MARK, PSB3_PSB2_FN2, PTN3_FN),
-	PINMUX_DATA(LCDD18_MARK, PSB3_PSB2_FN1, PTN2_FN),
-	PINMUX_DATA(SCIF4_PTN_TXD_MARK, PSB3_PSB2_FN2, PTN2_FN),
-	PINMUX_DATA(LCDD17_MARK, PSB5_PSB4_FN1, PTN1_FN),
-	PINMUX_DATA(DV_VSYNC_MARK, PSB5_PSB4_FN2, PTN1_FN),
-	PINMUX_DATA(LCDD16_MARK, PSB5_PSB4_FN1, PTN0_FN),
-	PINMUX_DATA(DV_HSYNC_MARK, PSB5_PSB4_FN2, PTN0_FN),
-
-	/* PTQ FN */
-	PINMUX_DATA(AN3_MARK, PTQ3_FN),
-	PINMUX_DATA(AN2_MARK, PTQ2_FN),
-	PINMUX_DATA(AN1_MARK, PTQ1_FN),
-	PINMUX_DATA(AN0_MARK, PTQ0_FN),
-
-	/* PTR FN */
-	PINMUX_DATA(CS6B_CE1B_MARK, PTR7_FN),
-	PINMUX_DATA(CS6A_CE2B_MARK, PTR6_FN),
-	PINMUX_DATA(CS5B_CE1A_MARK, PTR5_FN),
-	PINMUX_DATA(CS5A_CE2A_MARK, PTR4_FN),
-	PINMUX_DATA(IOIS16_MARK, PSA13_PSA12_FN1, PTR3_FN),
-	PINMUX_DATA(LCDLCLK_PTR_MARK, PSA13_PSA12_FN2, PTR3_FN),
-	PINMUX_DATA(WAIT_MARK, PTR2_FN),
-	PINMUX_DATA(WE3_ICIOWR_MARK, PTR1_FN),
-	PINMUX_DATA(WE2_ICIORD_MARK, PTR0_FN),
-
-	/* PTS FN */
-	PINMUX_DATA(SCIF1_PTS_SCK_MARK, PSC15_PSC14_FN1, PTS7_FN),
-	PINMUX_DATA(SDHI0CD_PTS_MARK, PSC15_PSC14_FN2, PTS7_FN),
-	PINMUX_DATA(SCIF1_PTS_RXD_MARK, PSC15_PSC14_FN1, PTS6_FN),
-	PINMUX_DATA(SDHI0WP_PTS_MARK, PSC15_PSC14_FN2, PTS6_FN),
-	PINMUX_DATA(SCIF1_PTS_TXD_MARK, PSC15_PSC14_FN1, PTS5_FN),
-	PINMUX_DATA(SDHI0D3_PTS_MARK, PSC15_PSC14_FN2, PTS5_FN),
-	PINMUX_DATA(SCIF3_PTS_CTS_MARK, PSC15_PSC14_FN1, PTS4_FN),
-	PINMUX_DATA(SDHI0D2_PTS_MARK, PSC15_PSC14_FN2, PTS4_FN),
-	PINMUX_DATA(SCIF3_PTS_RTS_MARK, PSC15_PSC14_FN1, PTS3_FN),
-	PINMUX_DATA(SDHI0D1_PTS_MARK, PSC15_PSC14_FN2, PTS3_FN),
-	PINMUX_DATA(SCIF3_PTS_SCK_MARK, PSC15_PSC14_FN1, PTS2_FN),
-	PINMUX_DATA(SDHI0D0_PTS_MARK, PSC15_PSC14_FN2, PTS2_FN),
-	PINMUX_DATA(SCIF3_PTS_RXD_MARK, PSC15_PSC14_FN1, PTS1_FN),
-	PINMUX_DATA(SDHI0CMD_PTS_MARK, PSC15_PSC14_FN2, PTS1_FN),
-	PINMUX_DATA(SCIF3_PTS_TXD_MARK, PSC15_PSC14_FN1, PTS0_FN),
-	PINMUX_DATA(SDHI0CLK_PTS_MARK, PSC15_PSC14_FN2, PTS0_FN),
-
-	/* PTT FN */
-	PINMUX_DATA(SCIF0_PTT_SCK_MARK, PSC13_PSC12_FN1, PTT5_FN),
-	PINMUX_DATA(MSIOF0_PTT_TSCK_MARK, PSC13_PSC12_FN2, PTT5_FN),
-	PINMUX_DATA(SCIF0_PTT_RXD_MARK, PSC13_PSC12_FN1, PTT4_FN),
-	PINMUX_DATA(MSIOF0_PTT_RXD_MARK, PSC13_PSC12_FN2, PTT4_FN),
-	PINMUX_DATA(SCIF0_PTT_TXD_MARK, PSC13_PSC12_FN1, PTT3_FN),
-	PINMUX_DATA(MSIOF0_PTT_TXD_MARK, PSC13_PSC12_FN2, PTT3_FN),
-	PINMUX_DATA(SCIF2_PTT_SCK_MARK, PSC11_PSC10_FN1, PTT2_FN),
-	PINMUX_DATA(MSIOF0_PTT_TSYNC_MARK, PSC11_PSC10_FN2, PTT2_FN),
-	PINMUX_DATA(SCIF2_PTT_RXD_MARK, PSC11_PSC10_FN1, PTT1_FN),
-	PINMUX_DATA(MSIOF0_PTT_SS1_MARK, PSC11_PSC10_FN2, PTT1_FN),
-	PINMUX_DATA(MSIOF0_PTT_RSCK_MARK, PSC11_PSC10_FN3, PTT1_FN),
-	PINMUX_DATA(SCIF2_PTT_TXD_MARK, PSC11_PSC10_FN1, PTT0_FN),
-	PINMUX_DATA(MSIOF0_PTT_SS2_MARK, PSC11_PSC10_FN2, PTT0_FN),
-	PINMUX_DATA(MSIOF0_PTT_RSYNC_MARK, PSC11_PSC10_FN3, PTT0_FN),
-
-	/* PTU FN */
-	PINMUX_DATA(FCDE_MARK, PSC9_PSC8_FN1, PTU5_FN),
-	PINMUX_DATA(SCIF0_PTU_SCK_MARK, PSC9_PSC8_FN2, PTU5_FN),
-	PINMUX_DATA(FSC_MARK, PSC9_PSC8_FN1, PTU4_FN),
-	PINMUX_DATA(SCIF0_PTU_RXD_MARK, PSC9_PSC8_FN2, PTU4_FN),
-	PINMUX_DATA(FWE_MARK, PSC9_PSC8_FN1, PTU3_FN),
-	PINMUX_DATA(SCIF0_PTU_TXD_MARK, PSC9_PSC8_FN2, PTU3_FN),
-	PINMUX_DATA(FOE_MARK, PSC7_PSC6_FN1, PTU2_FN),
-	PINMUX_DATA(SCIF2_PTU_SCK_MARK, PSC7_PSC6_FN2, PTU2_FN),
-	PINMUX_DATA(VIO_VD2_MARK, PSC7_PSC6_FN3, PTU2_FN),
-	PINMUX_DATA(FRB_MARK, PSC7_PSC6_FN1, PTU1_FN),
-	PINMUX_DATA(SCIF2_PTU_RXD_MARK, PSC7_PSC6_FN2, PTU1_FN),
-	PINMUX_DATA(VIO_CLK2_MARK, PSC7_PSC6_FN3, PTU1_FN),
-	PINMUX_DATA(FCE_MARK, PSC7_PSC6_FN1, PTU0_FN),
-	PINMUX_DATA(SCIF2_PTU_TXD_MARK, PSC7_PSC6_FN2, PTU0_FN),
-	PINMUX_DATA(VIO_HD2_MARK, PSC7_PSC6_FN3, PTU0_FN),
-
-	/* PTV FN */
-	PINMUX_DATA(NAF7_MARK, PSC7_PSC6_FN1, PTV7_FN),
-	PINMUX_DATA(SCIF1_PTV_SCK_MARK, PSC7_PSC6_FN2, PTV7_FN),
-	PINMUX_DATA(VIO_D15_MARK, PSC7_PSC6_FN3, PTV7_FN),
-	PINMUX_DATA(NAF6_MARK, PSC7_PSC6_FN1, PTV6_FN),
-	PINMUX_DATA(SCIF1_PTV_RXD_MARK, PSC7_PSC6_FN2, PTV6_FN),
-	PINMUX_DATA(VIO_D14_MARK, PSC7_PSC6_FN3, PTV6_FN),
-	PINMUX_DATA(NAF5_MARK, PSC7_PSC6_FN1, PTV5_FN),
-	PINMUX_DATA(SCIF1_PTV_TXD_MARK, PSC7_PSC6_FN2, PTV5_FN),
-	PINMUX_DATA(VIO_D13_MARK, PSC7_PSC6_FN3, PTV5_FN),
-	PINMUX_DATA(NAF4_MARK, PSC7_PSC6_FN1, PTV4_FN),
-	PINMUX_DATA(SCIF3_PTV_CTS_MARK, PSC7_PSC6_FN2, PTV4_FN),
-	PINMUX_DATA(VIO_D12_MARK, PSC7_PSC6_FN3, PTV4_FN),
-	PINMUX_DATA(NAF3_MARK, PSC7_PSC6_FN1, PTV3_FN),
-	PINMUX_DATA(SCIF3_PTV_RTS_MARK, PSC7_PSC6_FN2, PTV3_FN),
-	PINMUX_DATA(VIO_D11_MARK, PSC7_PSC6_FN3, PTV3_FN),
-	PINMUX_DATA(NAF2_MARK, PSC7_PSC6_FN1, PTV2_FN),
-	PINMUX_DATA(SCIF3_PTV_SCK_MARK, PSC7_PSC6_FN2, PTV2_FN),
-	PINMUX_DATA(VIO_D10_MARK, PSC7_PSC6_FN3, PTV2_FN),
-	PINMUX_DATA(NAF1_MARK, PSC7_PSC6_FN1, PTV1_FN),
-	PINMUX_DATA(SCIF3_PTV_RXD_MARK, PSC7_PSC6_FN2, PTV1_FN),
-	PINMUX_DATA(VIO_D9_MARK, PSC7_PSC6_FN3, PTV1_FN),
-	PINMUX_DATA(NAF0_MARK, PSC7_PSC6_FN1, PTV0_FN),
-	PINMUX_DATA(SCIF3_PTV_TXD_MARK, PSC7_PSC6_FN2, PTV0_FN),
-	PINMUX_DATA(VIO_D8_MARK, PSC7_PSC6_FN3, PTV0_FN),
-
-	/* PTW FN */
-	PINMUX_DATA(IRQ7_MARK, PTW7_FN),
-	PINMUX_DATA(IRQ6_MARK, PTW6_FN),
-	PINMUX_DATA(IRQ5_MARK, PTW5_FN),
-	PINMUX_DATA(IRQ4_MARK, PSD15_PSD14_FN1, PTW4_FN),
-	PINMUX_DATA(LCDLCLK_PTW_MARK, PSD15_PSD14_FN2, PTW4_FN),
-	PINMUX_DATA(IRQ3_MARK, PSD13_PSD12_FN1, PTW3_FN),
-	PINMUX_DATA(ADTRG_MARK, PSD13_PSD12_FN2, PTW3_FN),
-	PINMUX_DATA(IRQ2_MARK, PSD11_PSD10_FN1, PTW2_FN),
-	PINMUX_DATA(BS_MARK, PSD11_PSD10_FN2, PTW2_FN),
-	PINMUX_DATA(VIO_CKO_MARK, PSD11_PSD10_FN3, PTW2_FN),
-	PINMUX_DATA(IRQ1_MARK, PSD9_PSD8_FN1, PTW1_FN),
-	PINMUX_DATA(SIUAISPD_MARK, PSD9_PSD8_FN2, PTW1_FN),
-	PINMUX_DATA(IRQ0_MARK, PSD7_PSD6_FN1, PTW0_FN),
-	PINMUX_DATA(SIUAOSPD_MARK, PSD7_PSD6_FN2, PTW0_FN),
-
-	/* PTX FN */
-	PINMUX_DATA(DACK1_MARK, PTX7_FN),
-	PINMUX_DATA(DREQ1_MARK, PSD3_PSD2_FN1, PTX6_FN),
-	PINMUX_DATA(MSIOF0_PTX_MCK_MARK, PSD3_PSD2_FN2, PTX6_FN),
-	PINMUX_DATA(DACK1_MARK, PTX5_FN),
-	PINMUX_DATA(IRDA_OUT_MARK, PSD5_PSD4_FN2, PTX5_FN),
-	PINMUX_DATA(DREQ1_MARK, PTX4_FN),
-	PINMUX_DATA(IRDA_IN_MARK, PSD5_PSD4_FN2, PTX4_FN),
-	PINMUX_DATA(TS0_SDAT_MARK, PTX3_FN),
-	PINMUX_DATA(TS0_SCK_MARK, PTX2_FN),
-	PINMUX_DATA(TS0_SDEN_MARK, PTX1_FN),
-	PINMUX_DATA(TS0_SPSYNC_MARK, PTX0_FN),
-
-	/* PTY FN */
-	PINMUX_DATA(VIO_D7_MARK, PTY7_FN),
-	PINMUX_DATA(VIO_D6_MARK, PTY6_FN),
-	PINMUX_DATA(VIO_D5_MARK, PTY5_FN),
-	PINMUX_DATA(VIO_D4_MARK, PTY4_FN),
-	PINMUX_DATA(VIO_D3_MARK, PTY3_FN),
-	PINMUX_DATA(VIO_D2_MARK, PTY2_FN),
-	PINMUX_DATA(VIO_D1_MARK, PTY1_FN),
-	PINMUX_DATA(VIO_D0_MARK, PTY0_FN),
-
-	/* PTZ FN */
-	PINMUX_DATA(SIUBOBT_MARK, PTZ7_FN),
-	PINMUX_DATA(SIUBOLR_MARK, PTZ6_FN),
-	PINMUX_DATA(SIUBOSLD_MARK, PTZ5_FN),
-	PINMUX_DATA(SIUBMCK_MARK, PTZ4_FN),
-	PINMUX_DATA(VIO_FLD_MARK, PSD1_PSD0_FN1, PTZ3_FN),
-	PINMUX_DATA(SIUBFCK_MARK, PSD1_PSD0_FN2, PTZ3_FN),
-	PINMUX_DATA(VIO_HD1_MARK, PSD1_PSD0_FN1, PTZ2_FN),
-	PINMUX_DATA(SIUBILR_MARK, PSD1_PSD0_FN2, PTZ2_FN),
-	PINMUX_DATA(VIO_VD1_MARK, PSD1_PSD0_FN1, PTZ1_FN),
-	PINMUX_DATA(SIUBIBT_MARK, PSD1_PSD0_FN2, PTZ1_FN),
-	PINMUX_DATA(VIO_CLK1_MARK, PSD1_PSD0_FN1, PTZ0_FN),
-	PINMUX_DATA(SIUBISLD_MARK, PSD1_PSD0_FN2, PTZ0_FN),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	/* PTA */
-	PINMUX_GPIO(PTA7),
-	PINMUX_GPIO(PTA6),
-	PINMUX_GPIO(PTA5),
-	PINMUX_GPIO(PTA4),
-	PINMUX_GPIO(PTA3),
-	PINMUX_GPIO(PTA2),
-	PINMUX_GPIO(PTA1),
-	PINMUX_GPIO(PTA0),
-
-	/* PTB */
-	PINMUX_GPIO(PTB7),
-	PINMUX_GPIO(PTB6),
-	PINMUX_GPIO(PTB5),
-	PINMUX_GPIO(PTB4),
-	PINMUX_GPIO(PTB3),
-	PINMUX_GPIO(PTB2),
-	PINMUX_GPIO(PTB1),
-	PINMUX_GPIO(PTB0),
-
-	/* PTC */
-	PINMUX_GPIO(PTC7),
-	PINMUX_GPIO(PTC6),
-	PINMUX_GPIO(PTC5),
-	PINMUX_GPIO(PTC4),
-	PINMUX_GPIO(PTC3),
-	PINMUX_GPIO(PTC2),
-	PINMUX_GPIO(PTC1),
-	PINMUX_GPIO(PTC0),
-
-	/* PTD */
-	PINMUX_GPIO(PTD7),
-	PINMUX_GPIO(PTD6),
-	PINMUX_GPIO(PTD5),
-	PINMUX_GPIO(PTD4),
-	PINMUX_GPIO(PTD3),
-	PINMUX_GPIO(PTD2),
-	PINMUX_GPIO(PTD1),
-	PINMUX_GPIO(PTD0),
-
-	/* PTE */
-	PINMUX_GPIO(PTE5),
-	PINMUX_GPIO(PTE4),
-	PINMUX_GPIO(PTE3),
-	PINMUX_GPIO(PTE2),
-	PINMUX_GPIO(PTE1),
-	PINMUX_GPIO(PTE0),
-
-	/* PTF */
-	PINMUX_GPIO(PTF7),
-	PINMUX_GPIO(PTF6),
-	PINMUX_GPIO(PTF5),
-	PINMUX_GPIO(PTF4),
-	PINMUX_GPIO(PTF3),
-	PINMUX_GPIO(PTF2),
-	PINMUX_GPIO(PTF1),
-	PINMUX_GPIO(PTF0),
-
-	/* PTG */
-	PINMUX_GPIO(PTG5),
-	PINMUX_GPIO(PTG4),
-	PINMUX_GPIO(PTG3),
-	PINMUX_GPIO(PTG2),
-	PINMUX_GPIO(PTG1),
-	PINMUX_GPIO(PTG0),
-
-	/* PTH */
-	PINMUX_GPIO(PTH7),
-	PINMUX_GPIO(PTH6),
-	PINMUX_GPIO(PTH5),
-	PINMUX_GPIO(PTH4),
-	PINMUX_GPIO(PTH3),
-	PINMUX_GPIO(PTH2),
-	PINMUX_GPIO(PTH1),
-	PINMUX_GPIO(PTH0),
-
-	/* PTJ */
-	PINMUX_GPIO(PTJ7),
-	PINMUX_GPIO(PTJ5),
-	PINMUX_GPIO(PTJ3),
-	PINMUX_GPIO(PTJ2),
-	PINMUX_GPIO(PTJ1),
-	PINMUX_GPIO(PTJ0),
-
-	/* PTK */
-	PINMUX_GPIO(PTK7),
-	PINMUX_GPIO(PTK6),
-	PINMUX_GPIO(PTK5),
-	PINMUX_GPIO(PTK4),
-	PINMUX_GPIO(PTK3),
-	PINMUX_GPIO(PTK2),
-	PINMUX_GPIO(PTK1),
-	PINMUX_GPIO(PTK0),
-
-	/* PTL */
-	PINMUX_GPIO(PTL7),
-	PINMUX_GPIO(PTL6),
-	PINMUX_GPIO(PTL5),
-	PINMUX_GPIO(PTL4),
-	PINMUX_GPIO(PTL3),
-	PINMUX_GPIO(PTL2),
-	PINMUX_GPIO(PTL1),
-	PINMUX_GPIO(PTL0),
-
-	/* PTM */
-	PINMUX_GPIO(PTM7),
-	PINMUX_GPIO(PTM6),
-	PINMUX_GPIO(PTM5),
-	PINMUX_GPIO(PTM4),
-	PINMUX_GPIO(PTM3),
-	PINMUX_GPIO(PTM2),
-	PINMUX_GPIO(PTM1),
-	PINMUX_GPIO(PTM0),
-
-	/* PTN */
-	PINMUX_GPIO(PTN7),
-	PINMUX_GPIO(PTN6),
-	PINMUX_GPIO(PTN5),
-	PINMUX_GPIO(PTN4),
-	PINMUX_GPIO(PTN3),
-	PINMUX_GPIO(PTN2),
-	PINMUX_GPIO(PTN1),
-	PINMUX_GPIO(PTN0),
-
-	/* PTQ */
-	PINMUX_GPIO(PTQ3),
-	PINMUX_GPIO(PTQ2),
-	PINMUX_GPIO(PTQ1),
-	PINMUX_GPIO(PTQ0),
-
-	/* PTR */
-	PINMUX_GPIO(PTR7),
-	PINMUX_GPIO(PTR6),
-	PINMUX_GPIO(PTR5),
-	PINMUX_GPIO(PTR4),
-	PINMUX_GPIO(PTR3),
-	PINMUX_GPIO(PTR2),
-	PINMUX_GPIO(PTR1),
-	PINMUX_GPIO(PTR0),
-
-	/* PTS */
-	PINMUX_GPIO(PTS7),
-	PINMUX_GPIO(PTS6),
-	PINMUX_GPIO(PTS5),
-	PINMUX_GPIO(PTS4),
-	PINMUX_GPIO(PTS3),
-	PINMUX_GPIO(PTS2),
-	PINMUX_GPIO(PTS1),
-	PINMUX_GPIO(PTS0),
-
-	/* PTT */
-	PINMUX_GPIO(PTT5),
-	PINMUX_GPIO(PTT4),
-	PINMUX_GPIO(PTT3),
-	PINMUX_GPIO(PTT2),
-	PINMUX_GPIO(PTT1),
-	PINMUX_GPIO(PTT0),
-
-	/* PTU */
-	PINMUX_GPIO(PTU5),
-	PINMUX_GPIO(PTU4),
-	PINMUX_GPIO(PTU3),
-	PINMUX_GPIO(PTU2),
-	PINMUX_GPIO(PTU1),
-	PINMUX_GPIO(PTU0),
-
-	/* PTV */
-	PINMUX_GPIO(PTV7),
-	PINMUX_GPIO(PTV6),
-	PINMUX_GPIO(PTV5),
-	PINMUX_GPIO(PTV4),
-	PINMUX_GPIO(PTV3),
-	PINMUX_GPIO(PTV2),
-	PINMUX_GPIO(PTV1),
-	PINMUX_GPIO(PTV0),
-
-	/* PTW */
-	PINMUX_GPIO(PTW7),
-	PINMUX_GPIO(PTW6),
-	PINMUX_GPIO(PTW5),
-	PINMUX_GPIO(PTW4),
-	PINMUX_GPIO(PTW3),
-	PINMUX_GPIO(PTW2),
-	PINMUX_GPIO(PTW1),
-	PINMUX_GPIO(PTW0),
-
-	/* PTX */
-	PINMUX_GPIO(PTX7),
-	PINMUX_GPIO(PTX6),
-	PINMUX_GPIO(PTX5),
-	PINMUX_GPIO(PTX4),
-	PINMUX_GPIO(PTX3),
-	PINMUX_GPIO(PTX2),
-	PINMUX_GPIO(PTX1),
-	PINMUX_GPIO(PTX0),
-
-	/* PTY */
-	PINMUX_GPIO(PTY7),
-	PINMUX_GPIO(PTY6),
-	PINMUX_GPIO(PTY5),
-	PINMUX_GPIO(PTY4),
-	PINMUX_GPIO(PTY3),
-	PINMUX_GPIO(PTY2),
-	PINMUX_GPIO(PTY1),
-	PINMUX_GPIO(PTY0),
-
-	/* PTZ */
-	PINMUX_GPIO(PTZ7),
-	PINMUX_GPIO(PTZ6),
-	PINMUX_GPIO(PTZ5),
-	PINMUX_GPIO(PTZ4),
-	PINMUX_GPIO(PTZ3),
-	PINMUX_GPIO(PTZ2),
-	PINMUX_GPIO(PTZ1),
-	PINMUX_GPIO(PTZ0),
-};
-
-#define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-	/* SCIF0 */
-	GPIO_FN(SCIF0_PTT_TXD),
-	GPIO_FN(SCIF0_PTT_RXD),
-	GPIO_FN(SCIF0_PTT_SCK),
-	GPIO_FN(SCIF0_PTU_TXD),
-	GPIO_FN(SCIF0_PTU_RXD),
-	GPIO_FN(SCIF0_PTU_SCK),
-
-	/* SCIF1 */
-	GPIO_FN(SCIF1_PTS_TXD),
-	GPIO_FN(SCIF1_PTS_RXD),
-	GPIO_FN(SCIF1_PTS_SCK),
-	GPIO_FN(SCIF1_PTV_TXD),
-	GPIO_FN(SCIF1_PTV_RXD),
-	GPIO_FN(SCIF1_PTV_SCK),
-
-	/* SCIF2 */
-	GPIO_FN(SCIF2_PTT_TXD),
-	GPIO_FN(SCIF2_PTT_RXD),
-	GPIO_FN(SCIF2_PTT_SCK),
-	GPIO_FN(SCIF2_PTU_TXD),
-	GPIO_FN(SCIF2_PTU_RXD),
-	GPIO_FN(SCIF2_PTU_SCK),
-
-	/* SCIF3 */
-	GPIO_FN(SCIF3_PTS_TXD),
-	GPIO_FN(SCIF3_PTS_RXD),
-	GPIO_FN(SCIF3_PTS_SCK),
-	GPIO_FN(SCIF3_PTS_RTS),
-	GPIO_FN(SCIF3_PTS_CTS),
-	GPIO_FN(SCIF3_PTV_TXD),
-	GPIO_FN(SCIF3_PTV_RXD),
-	GPIO_FN(SCIF3_PTV_SCK),
-	GPIO_FN(SCIF3_PTV_RTS),
-	GPIO_FN(SCIF3_PTV_CTS),
-
-	/* SCIF4 */
-	GPIO_FN(SCIF4_PTE_TXD),
-	GPIO_FN(SCIF4_PTE_RXD),
-	GPIO_FN(SCIF4_PTE_SCK),
-	GPIO_FN(SCIF4_PTN_TXD),
-	GPIO_FN(SCIF4_PTN_RXD),
-	GPIO_FN(SCIF4_PTN_SCK),
-
-	/* SCIF5 */
-	GPIO_FN(SCIF5_PTE_TXD),
-	GPIO_FN(SCIF5_PTE_RXD),
-	GPIO_FN(SCIF5_PTE_SCK),
-	GPIO_FN(SCIF5_PTN_TXD),
-	GPIO_FN(SCIF5_PTN_RXD),
-	GPIO_FN(SCIF5_PTN_SCK),
-
-	/* CEU */
-	GPIO_FN(VIO_D15),
-	GPIO_FN(VIO_D14),
-	GPIO_FN(VIO_D13),
-	GPIO_FN(VIO_D12),
-	GPIO_FN(VIO_D11),
-	GPIO_FN(VIO_D10),
-	GPIO_FN(VIO_D9),
-	GPIO_FN(VIO_D8),
-	GPIO_FN(VIO_D7),
-	GPIO_FN(VIO_D6),
-	GPIO_FN(VIO_D5),
-	GPIO_FN(VIO_D4),
-	GPIO_FN(VIO_D3),
-	GPIO_FN(VIO_D2),
-	GPIO_FN(VIO_D1),
-	GPIO_FN(VIO_D0),
-	GPIO_FN(VIO_CLK1),
-	GPIO_FN(VIO_VD1),
-	GPIO_FN(VIO_HD1),
-	GPIO_FN(VIO_FLD),
-	GPIO_FN(VIO_CKO),
-	GPIO_FN(VIO_VD2),
-	GPIO_FN(VIO_HD2),
-	GPIO_FN(VIO_CLK2),
-
-	/* LCDC */
-	GPIO_FN(LCDD23),
-	GPIO_FN(LCDD22),
-	GPIO_FN(LCDD21),
-	GPIO_FN(LCDD20),
-	GPIO_FN(LCDD19),
-	GPIO_FN(LCDD18),
-	GPIO_FN(LCDD17),
-	GPIO_FN(LCDD16),
-	GPIO_FN(LCDD15),
-	GPIO_FN(LCDD14),
-	GPIO_FN(LCDD13),
-	GPIO_FN(LCDD12),
-	GPIO_FN(LCDD11),
-	GPIO_FN(LCDD10),
-	GPIO_FN(LCDD9),
-	GPIO_FN(LCDD8),
-	GPIO_FN(LCDD7),
-	GPIO_FN(LCDD6),
-	GPIO_FN(LCDD5),
-	GPIO_FN(LCDD4),
-	GPIO_FN(LCDD3),
-	GPIO_FN(LCDD2),
-	GPIO_FN(LCDD1),
-	GPIO_FN(LCDD0),
-	GPIO_FN(LCDLCLK_PTR),
-	GPIO_FN(LCDLCLK_PTW),
-	/* Main LCD */
-	GPIO_FN(LCDDON),
-	GPIO_FN(LCDVCPWC),
-	GPIO_FN(LCDVEPWC),
-	GPIO_FN(LCDVSYN),
-	/* Main LCD - RGB Mode */
-	GPIO_FN(LCDDCK),
-	GPIO_FN(LCDHSYN),
-	GPIO_FN(LCDDISP),
-	/* Main LCD - SYS Mode */
-	GPIO_FN(LCDRS),
-	GPIO_FN(LCDCS),
-	GPIO_FN(LCDWR),
-	GPIO_FN(LCDRD),
-
-	/* IRQ */
-	GPIO_FN(IRQ0),
-	GPIO_FN(IRQ1),
-	GPIO_FN(IRQ2),
-	GPIO_FN(IRQ3),
-	GPIO_FN(IRQ4),
-	GPIO_FN(IRQ5),
-	GPIO_FN(IRQ6),
-	GPIO_FN(IRQ7),
-
-	/* AUD */
-	GPIO_FN(AUDCK),
-	GPIO_FN(AUDSYNC),
-	GPIO_FN(AUDATA3),
-	GPIO_FN(AUDATA2),
-	GPIO_FN(AUDATA1),
-	GPIO_FN(AUDATA0),
-
-	/* SDHI0 (PTD) */
-	GPIO_FN(SDHI0CD_PTD),
-	GPIO_FN(SDHI0WP_PTD),
-	GPIO_FN(SDHI0D3_PTD),
-	GPIO_FN(SDHI0D2_PTD),
-	GPIO_FN(SDHI0D1_PTD),
-	GPIO_FN(SDHI0D0_PTD),
-	GPIO_FN(SDHI0CMD_PTD),
-	GPIO_FN(SDHI0CLK_PTD),
-
-	/* SDHI0 (PTS) */
-	GPIO_FN(SDHI0CD_PTS),
-	GPIO_FN(SDHI0WP_PTS),
-	GPIO_FN(SDHI0D3_PTS),
-	GPIO_FN(SDHI0D2_PTS),
-	GPIO_FN(SDHI0D1_PTS),
-	GPIO_FN(SDHI0D0_PTS),
-	GPIO_FN(SDHI0CMD_PTS),
-	GPIO_FN(SDHI0CLK_PTS),
-
-	/* SDHI1 */
-	GPIO_FN(SDHI1CD),
-	GPIO_FN(SDHI1WP),
-	GPIO_FN(SDHI1D3),
-	GPIO_FN(SDHI1D2),
-	GPIO_FN(SDHI1D1),
-	GPIO_FN(SDHI1D0),
-	GPIO_FN(SDHI1CMD),
-	GPIO_FN(SDHI1CLK),
-
-	/* SIUA */
-	GPIO_FN(SIUAFCK),
-	GPIO_FN(SIUAILR),
-	GPIO_FN(SIUAIBT),
-	GPIO_FN(SIUAISLD),
-	GPIO_FN(SIUAOLR),
-	GPIO_FN(SIUAOBT),
-	GPIO_FN(SIUAOSLD),
-	GPIO_FN(SIUAMCK),
-	GPIO_FN(SIUAISPD),
-	GPIO_FN(SIUAOSPD),
-
-	/* SIUB */
-	GPIO_FN(SIUBFCK),
-	GPIO_FN(SIUBILR),
-	GPIO_FN(SIUBIBT),
-	GPIO_FN(SIUBISLD),
-	GPIO_FN(SIUBOLR),
-	GPIO_FN(SIUBOBT),
-	GPIO_FN(SIUBOSLD),
-	GPIO_FN(SIUBMCK),
-
-	/* IRDA */
-	GPIO_FN(IRDA_IN),
-	GPIO_FN(IRDA_OUT),
-
-	/* VOU */
-	GPIO_FN(DV_CLKI),
-	GPIO_FN(DV_CLK),
-	GPIO_FN(DV_HSYNC),
-	GPIO_FN(DV_VSYNC),
-	GPIO_FN(DV_D15),
-	GPIO_FN(DV_D14),
-	GPIO_FN(DV_D13),
-	GPIO_FN(DV_D12),
-	GPIO_FN(DV_D11),
-	GPIO_FN(DV_D10),
-	GPIO_FN(DV_D9),
-	GPIO_FN(DV_D8),
-	GPIO_FN(DV_D7),
-	GPIO_FN(DV_D6),
-	GPIO_FN(DV_D5),
-	GPIO_FN(DV_D4),
-	GPIO_FN(DV_D3),
-	GPIO_FN(DV_D2),
-	GPIO_FN(DV_D1),
-	GPIO_FN(DV_D0),
-
-	/* KEYSC */
-	GPIO_FN(KEYIN0),
-	GPIO_FN(KEYIN1),
-	GPIO_FN(KEYIN2),
-	GPIO_FN(KEYIN3),
-	GPIO_FN(KEYIN4),
-	GPIO_FN(KEYOUT0),
-	GPIO_FN(KEYOUT1),
-	GPIO_FN(KEYOUT2),
-	GPIO_FN(KEYOUT3),
-	GPIO_FN(KEYOUT4_IN6),
-	GPIO_FN(KEYOUT5_IN5),
-
-	/* MSIOF0 (PTF) */
-	GPIO_FN(MSIOF0_PTF_TXD),
-	GPIO_FN(MSIOF0_PTF_RXD),
-	GPIO_FN(MSIOF0_PTF_MCK),
-	GPIO_FN(MSIOF0_PTF_TSYNC),
-	GPIO_FN(MSIOF0_PTF_TSCK),
-	GPIO_FN(MSIOF0_PTF_RSYNC),
-	GPIO_FN(MSIOF0_PTF_RSCK),
-	GPIO_FN(MSIOF0_PTF_SS1),
-	GPIO_FN(MSIOF0_PTF_SS2),
-
-	/* MSIOF0 (PTT+PTX) */
-	GPIO_FN(MSIOF0_PTT_TXD),
-	GPIO_FN(MSIOF0_PTT_RXD),
-	GPIO_FN(MSIOF0_PTX_MCK),
-	GPIO_FN(MSIOF0_PTT_TSYNC),
-	GPIO_FN(MSIOF0_PTT_TSCK),
-	GPIO_FN(MSIOF0_PTT_RSYNC),
-	GPIO_FN(MSIOF0_PTT_RSCK),
-	GPIO_FN(MSIOF0_PTT_SS1),
-	GPIO_FN(MSIOF0_PTT_SS2),
-
-	/* MSIOF1 */
-	GPIO_FN(MSIOF1_TXD),
-	GPIO_FN(MSIOF1_RXD),
-	GPIO_FN(MSIOF1_MCK),
-	GPIO_FN(MSIOF1_TSYNC),
-	GPIO_FN(MSIOF1_TSCK),
-	GPIO_FN(MSIOF1_RSYNC),
-	GPIO_FN(MSIOF1_RSCK),
-	GPIO_FN(MSIOF1_SS1),
-	GPIO_FN(MSIOF1_SS2),
-
-	/* TSIF */
-	GPIO_FN(TS0_SDAT),
-	GPIO_FN(TS0_SCK),
-	GPIO_FN(TS0_SDEN),
-	GPIO_FN(TS0_SPSYNC),
-
-	/* FLCTL */
-	GPIO_FN(FCE),
-	GPIO_FN(NAF7),
-	GPIO_FN(NAF6),
-	GPIO_FN(NAF5),
-	GPIO_FN(NAF4),
-	GPIO_FN(NAF3),
-	GPIO_FN(NAF2),
-	GPIO_FN(NAF1),
-	GPIO_FN(NAF0),
-	GPIO_FN(FCDE),
-	GPIO_FN(FOE),
-	GPIO_FN(FSC),
-	GPIO_FN(FWE),
-	GPIO_FN(FRB),
-
-	/* DMAC */
-	GPIO_FN(DACK1),
-	GPIO_FN(DREQ1),
-	GPIO_FN(DACK0),
-	GPIO_FN(DREQ0),
-
-	/* ADC */
-	GPIO_FN(AN3),
-	GPIO_FN(AN2),
-	GPIO_FN(AN1),
-	GPIO_FN(AN0),
-	GPIO_FN(ADTRG),
-
-	/* CPG */
-	GPIO_FN(STATUS0),
-	GPIO_FN(PDSTATUS),
-
-	/* TPU */
-	GPIO_FN(TPUTO0),
-	GPIO_FN(TPUTO1),
-	GPIO_FN(TPUTO2),
-	GPIO_FN(TPUTO3),
-
-	/* BSC */
-	GPIO_FN(D31),
-	GPIO_FN(D30),
-	GPIO_FN(D29),
-	GPIO_FN(D28),
-	GPIO_FN(D27),
-	GPIO_FN(D26),
-	GPIO_FN(D25),
-	GPIO_FN(D24),
-	GPIO_FN(D23),
-	GPIO_FN(D22),
-	GPIO_FN(D21),
-	GPIO_FN(D20),
-	GPIO_FN(D19),
-	GPIO_FN(D18),
-	GPIO_FN(D17),
-	GPIO_FN(D16),
-	GPIO_FN(IOIS16),
-	GPIO_FN(WAIT),
-	GPIO_FN(BS),
-	GPIO_FN(A25),
-	GPIO_FN(A24),
-	GPIO_FN(A23),
-	GPIO_FN(A22),
-	GPIO_FN(CS6B_CE1B),
-	GPIO_FN(CS6A_CE2B),
-	GPIO_FN(CS5B_CE1A),
-	GPIO_FN(CS5A_CE2A),
-	GPIO_FN(WE3_ICIOWR),
-	GPIO_FN(WE2_ICIORD),
-
-	/* ATAPI */
-	GPIO_FN(IDED15),
-	GPIO_FN(IDED14),
-	GPIO_FN(IDED13),
-	GPIO_FN(IDED12),
-	GPIO_FN(IDED11),
-	GPIO_FN(IDED10),
-	GPIO_FN(IDED9),
-	GPIO_FN(IDED8),
-	GPIO_FN(IDED7),
-	GPIO_FN(IDED6),
-	GPIO_FN(IDED5),
-	GPIO_FN(IDED4),
-	GPIO_FN(IDED3),
-	GPIO_FN(IDED2),
-	GPIO_FN(IDED1),
-	GPIO_FN(IDED0),
-	GPIO_FN(DIRECTION),
-	GPIO_FN(EXBUF_ENB),
-	GPIO_FN(IDERST),
-	GPIO_FN(IODACK),
-	GPIO_FN(IODREQ),
-	GPIO_FN(IDEIORDY),
-	GPIO_FN(IDEINT),
-	GPIO_FN(IDEIOWR),
-	GPIO_FN(IDEIORD),
-	GPIO_FN(IDECS1),
-	GPIO_FN(IDECS0),
-	GPIO_FN(IDEA2),
-	GPIO_FN(IDEA1),
-	GPIO_FN(IDEA0),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2, GROUP(
-		PTA7_FN, PTA7_OUT, 0, PTA7_IN,
-		PTA6_FN, PTA6_OUT, 0, PTA6_IN,
-		PTA5_FN, PTA5_OUT, 0, PTA5_IN,
-		PTA4_FN, PTA4_OUT, 0, PTA4_IN,
-		PTA3_FN, PTA3_OUT, 0, PTA3_IN,
-		PTA2_FN, PTA2_OUT, 0, PTA2_IN,
-		PTA1_FN, PTA1_OUT, 0, PTA1_IN,
-		PTA0_FN, PTA0_OUT, 0, PTA0_IN ))
-	},
-	{ PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2, GROUP(
-		PTB7_FN, PTB7_OUT, 0, PTB7_IN,
-		PTB6_FN, PTB6_OUT, 0, PTB6_IN,
-		PTB5_FN, PTB5_OUT, 0, PTB5_IN,
-		PTB4_FN, PTB4_OUT, 0, PTB4_IN,
-		PTB3_FN, PTB3_OUT, 0, PTB3_IN,
-		PTB2_FN, PTB2_OUT, 0, PTB2_IN,
-		PTB1_FN, PTB1_OUT, 0, PTB1_IN,
-		PTB0_FN, PTB0_OUT, 0, PTB0_IN ))
-	},
-	{ PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2, GROUP(
-		PTC7_FN, PTC7_OUT, 0, PTC7_IN,
-		PTC6_FN, PTC6_OUT, 0, PTC6_IN,
-		PTC5_FN, PTC5_OUT, 0, PTC5_IN,
-		PTC4_FN, PTC4_OUT, 0, PTC4_IN,
-		PTC3_FN, PTC3_OUT, 0, PTC3_IN,
-		PTC2_FN, PTC2_OUT, 0, PTC2_IN,
-		PTC1_FN, PTC1_OUT, 0, PTC1_IN,
-		PTC0_FN, PTC0_OUT, 0, PTC0_IN ))
-	},
-	{ PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2, GROUP(
-		PTD7_FN, PTD7_OUT, 0, PTD7_IN,
-		PTD6_FN, PTD6_OUT, 0, PTD6_IN,
-		PTD5_FN, PTD5_OUT, 0, PTD5_IN,
-		PTD4_FN, PTD4_OUT, 0, PTD4_IN,
-		PTD3_FN, PTD3_OUT, 0, PTD3_IN,
-		PTD2_FN, PTD2_OUT, 0, PTD2_IN,
-		PTD1_FN, PTD1_OUT, 0, PTD1_IN,
-		PTD0_FN, PTD0_OUT, 0, PTD0_IN ))
-	},
-	{ PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PTE5_FN, PTE5_OUT, 0, PTE5_IN,
-		PTE4_FN, PTE4_OUT, 0, PTE4_IN,
-		PTE3_FN, PTE3_OUT, 0, PTE3_IN,
-		PTE2_FN, PTE2_OUT, 0, PTE2_IN,
-		PTE1_FN, PTE1_OUT, 0, PTE1_IN,
-		PTE0_FN, PTE0_OUT, 0, PTE0_IN ))
-	},
-	{ PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2, GROUP(
-		PTF7_FN, PTF7_OUT, 0, PTF7_IN,
-		PTF6_FN, PTF6_OUT, 0, PTF6_IN,
-		PTF5_FN, PTF5_OUT, 0, PTF5_IN,
-		PTF4_FN, PTF4_OUT, 0, PTF4_IN,
-		PTF3_FN, PTF3_OUT, 0, PTF3_IN,
-		PTF2_FN, PTF2_OUT, 0, PTF2_IN,
-		PTF1_FN, PTF1_OUT, 0, PTF1_IN,
-		PTF0_FN, PTF0_OUT, 0, PTF0_IN ))
-	},
-	{ PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PTG5_FN, PTG5_OUT, 0, 0,
-		PTG4_FN, PTG4_OUT, 0, 0,
-		PTG3_FN, PTG3_OUT, 0, 0,
-		PTG2_FN, PTG2_OUT, 0, 0,
-		PTG1_FN, PTG1_OUT, 0, 0,
-		PTG0_FN, PTG0_OUT, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2, GROUP(
-		PTH7_FN, PTH7_OUT, 0, PTH7_IN,
-		PTH6_FN, PTH6_OUT, 0, PTH6_IN,
-		PTH5_FN, PTH5_OUT, 0, PTH5_IN,
-		PTH4_FN, PTH4_OUT, 0, PTH4_IN,
-		PTH3_FN, PTH3_OUT, 0, PTH3_IN,
-		PTH2_FN, PTH2_OUT, 0, PTH2_IN,
-		PTH1_FN, PTH1_OUT, 0, PTH1_IN,
-		PTH0_FN, PTH0_OUT, 0, PTH0_IN ))
-	},
-	{ PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2, GROUP(
-		PTJ7_FN, PTJ7_OUT, 0, 0,
-		0, 0, 0, 0,
-		PTJ5_FN, PTJ5_OUT, 0, 0,
-		0, 0, 0, 0,
-		PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN,
-		PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN,
-		PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN,
-		PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN ))
-	},
-	{ PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2, GROUP(
-		PTK7_FN, PTK7_OUT, 0, PTK7_IN,
-		PTK6_FN, PTK6_OUT, 0, PTK6_IN,
-		PTK5_FN, PTK5_OUT, 0, PTK5_IN,
-		PTK4_FN, PTK4_OUT, 0, PTK4_IN,
-		PTK3_FN, PTK3_OUT, 0, PTK3_IN,
-		PTK2_FN, PTK2_OUT, 0, PTK2_IN,
-		PTK1_FN, PTK1_OUT, 0, PTK1_IN,
-		PTK0_FN, PTK0_OUT, 0, PTK0_IN ))
-	},
-	{ PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2, GROUP(
-		PTL7_FN, PTL7_OUT, 0, PTL7_IN,
-		PTL6_FN, PTL6_OUT, 0, PTL6_IN,
-		PTL5_FN, PTL5_OUT, 0, PTL5_IN,
-		PTL4_FN, PTL4_OUT, 0, PTL4_IN,
-		PTL3_FN, PTL3_OUT, 0, PTL3_IN,
-		PTL2_FN, PTL2_OUT, 0, PTL2_IN,
-		PTL1_FN, PTL1_OUT, 0, PTL1_IN,
-		PTL0_FN, PTL0_OUT, 0, PTL0_IN ))
-	},
-	{ PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2, GROUP(
-		PTM7_FN, PTM7_OUT, 0, PTM7_IN,
-		PTM6_FN, PTM6_OUT, 0, PTM6_IN,
-		PTM5_FN, PTM5_OUT, 0, PTM5_IN,
-		PTM4_FN, PTM4_OUT, 0, PTM4_IN,
-		PTM3_FN, PTM3_OUT, 0, PTM3_IN,
-		PTM2_FN, PTM2_OUT, 0, PTM2_IN,
-		PTM1_FN, PTM1_OUT, 0, PTM1_IN,
-		PTM0_FN, PTM0_OUT, 0, PTM0_IN ))
-	},
-	{ PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2, GROUP(
-		PTN7_FN, PTN7_OUT, 0, PTN7_IN,
-		PTN6_FN, PTN6_OUT, 0, PTN6_IN,
-		PTN5_FN, PTN5_OUT, 0, PTN5_IN,
-		PTN4_FN, PTN4_OUT, 0, PTN4_IN,
-		PTN3_FN, PTN3_OUT, 0, PTN3_IN,
-		PTN2_FN, PTN2_OUT, 0, PTN2_IN,
-		PTN1_FN, PTN1_OUT, 0, PTN1_IN,
-		PTN0_FN, PTN0_OUT, 0, PTN0_IN ))
-	},
-	{ PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PTQ3_FN, 0, 0, PTQ3_IN,
-		PTQ2_FN, 0, 0, PTQ2_IN,
-		PTQ1_FN, 0, 0, PTQ1_IN,
-		PTQ0_FN, 0, 0, PTQ0_IN ))
-	},
-	{ PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2, GROUP(
-		PTR7_FN, PTR7_OUT, 0, PTR7_IN,
-		PTR6_FN, PTR6_OUT, 0, PTR6_IN,
-		PTR5_FN, PTR5_OUT, 0, PTR5_IN,
-		PTR4_FN, PTR4_OUT, 0, PTR4_IN,
-		PTR3_FN, 0, 0, PTR3_IN,
-		PTR2_FN, 0, 0, PTR2_IN,
-		PTR1_FN, PTR1_OUT, 0, PTR1_IN,
-		PTR0_FN, PTR0_OUT, 0, PTR0_IN ))
-	},
-	{ PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2, GROUP(
-		PTS7_FN, PTS7_OUT, 0, PTS7_IN,
-		PTS6_FN, PTS6_OUT, 0, PTS6_IN,
-		PTS5_FN, PTS5_OUT, 0, PTS5_IN,
-		PTS4_FN, PTS4_OUT, 0, PTS4_IN,
-		PTS3_FN, PTS3_OUT, 0, PTS3_IN,
-		PTS2_FN, PTS2_OUT, 0, PTS2_IN,
-		PTS1_FN, PTS1_OUT, 0, PTS1_IN,
-		PTS0_FN, PTS0_OUT, 0, PTS0_IN ))
-	},
-	{ PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PTT5_FN, PTT5_OUT, 0, PTT5_IN,
-		PTT4_FN, PTT4_OUT, 0, PTT4_IN,
-		PTT3_FN, PTT3_OUT, 0, PTT3_IN,
-		PTT2_FN, PTT2_OUT, 0, PTT2_IN,
-		PTT1_FN, PTT1_OUT, 0, PTT1_IN,
-		PTT0_FN, PTT0_OUT, 0, PTT0_IN ))
-	},
-	{ PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PTU5_FN, PTU5_OUT, 0, PTU5_IN,
-		PTU4_FN, PTU4_OUT, 0, PTU4_IN,
-		PTU3_FN, PTU3_OUT, 0, PTU3_IN,
-		PTU2_FN, PTU2_OUT, 0, PTU2_IN,
-		PTU1_FN, PTU1_OUT, 0, PTU1_IN,
-		PTU0_FN, PTU0_OUT, 0, PTU0_IN ))
-	},
-	{ PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2, GROUP(
-		PTV7_FN, PTV7_OUT, 0, PTV7_IN,
-		PTV6_FN, PTV6_OUT, 0, PTV6_IN,
-		PTV5_FN, PTV5_OUT, 0, PTV5_IN,
-		PTV4_FN, PTV4_OUT, 0, PTV4_IN,
-		PTV3_FN, PTV3_OUT, 0, PTV3_IN,
-		PTV2_FN, PTV2_OUT, 0, PTV2_IN,
-		PTV1_FN, PTV1_OUT, 0, PTV1_IN,
-		PTV0_FN, PTV0_OUT, 0, PTV0_IN ))
-	},
-	{ PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2, GROUP(
-		PTW7_FN, PTW7_OUT, 0, PTW7_IN,
-		PTW6_FN, PTW6_OUT, 0, PTW6_IN,
-		PTW5_FN, PTW5_OUT, 0, PTW5_IN,
-		PTW4_FN, PTW4_OUT, 0, PTW4_IN,
-		PTW3_FN, PTW3_OUT, 0, PTW3_IN,
-		PTW2_FN, PTW2_OUT, 0, PTW2_IN,
-		PTW1_FN, PTW1_OUT, 0, PTW1_IN,
-		PTW0_FN, PTW0_OUT, 0, PTW0_IN ))
-	},
-	{ PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2, GROUP(
-		PTX7_FN, PTX7_OUT, 0, PTX7_IN,
-		PTX6_FN, PTX6_OUT, 0, PTX6_IN,
-		PTX5_FN, PTX5_OUT, 0, PTX5_IN,
-		PTX4_FN, PTX4_OUT, 0, PTX4_IN,
-		PTX3_FN, PTX3_OUT, 0, PTX3_IN,
-		PTX2_FN, PTX2_OUT, 0, PTX2_IN,
-		PTX1_FN, PTX1_OUT, 0, PTX1_IN,
-		PTX0_FN, PTX0_OUT, 0, PTX0_IN ))
-	},
-	{ PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2, GROUP(
-		PTY7_FN, PTY7_OUT, 0, PTY7_IN,
-		PTY6_FN, PTY6_OUT, 0, PTY6_IN,
-		PTY5_FN, PTY5_OUT, 0, PTY5_IN,
-		PTY4_FN, PTY4_OUT, 0, PTY4_IN,
-		PTY3_FN, PTY3_OUT, 0, PTY3_IN,
-		PTY2_FN, PTY2_OUT, 0, PTY2_IN,
-		PTY1_FN, PTY1_OUT, 0, PTY1_IN,
-		PTY0_FN, PTY0_OUT, 0, PTY0_IN ))
-	},
-	{ PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2, GROUP(
-		PTZ7_FN, PTZ7_OUT, 0, PTZ7_IN,
-		PTZ6_FN, PTZ6_OUT, 0, PTZ6_IN,
-		PTZ5_FN, PTZ5_OUT, 0, PTZ5_IN,
-		PTZ4_FN, PTZ4_OUT, 0, PTZ4_IN,
-		PTZ3_FN, PTZ3_OUT, 0, PTZ3_IN,
-		PTZ2_FN, PTZ2_OUT, 0, PTZ2_IN,
-		PTZ1_FN, PTZ1_OUT, 0, PTZ1_IN,
-		PTZ0_FN, PTZ0_OUT, 0, PTZ0_IN ))
-	},
-	{ PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 2, GROUP(
-		PSA15_PSA14_FN1, PSA15_PSA14_FN2, 0, 0,
-		PSA13_PSA12_FN1, PSA13_PSA12_FN2, 0, 0,
-		PSA11_PSA10_FN1, PSA11_PSA10_FN2, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PSA5_PSA4_FN1, PSA5_PSA4_FN2, PSA5_PSA4_FN3, 0,
-		PSA3_PSA2_FN1, PSA3_PSA2_FN2, 0, 0,
-		0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 2, GROUP(
-		PSB15_PSB14_FN1, PSB15_PSB14_FN2, 0, 0,
-		PSB13_PSB12_LCDC_RGB, PSB13_PSB12_LCDC_SYS, 0, 0,
-		0, 0, 0, 0,
-		PSB9_PSB8_FN1, PSB9_PSB8_FN2, PSB9_PSB8_FN3, 0,
-		PSB7_PSB6_FN1, PSB7_PSB6_FN2, 0, 0,
-		PSB5_PSB4_FN1, PSB5_PSB4_FN2, 0, 0,
-		PSB3_PSB2_FN1, PSB3_PSB2_FN2, 0, 0,
-		0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 2, GROUP(
-		PSC15_PSC14_FN1, PSC15_PSC14_FN2, 0, 0,
-		PSC13_PSC12_FN1, PSC13_PSC12_FN2, 0, 0,
-		PSC11_PSC10_FN1, PSC11_PSC10_FN2, PSC11_PSC10_FN3, 0,
-		PSC9_PSC8_FN1, PSC9_PSC8_FN2, 0, 0,
-		PSC7_PSC6_FN1, PSC7_PSC6_FN2, PSC7_PSC6_FN3, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 2, GROUP(
-		PSD15_PSD14_FN1, PSD15_PSD14_FN2, 0, 0,
-		PSD13_PSD12_FN1, PSD13_PSD12_FN2, 0, 0,
-		PSD11_PSD10_FN1, PSD11_PSD10_FN2, PSD11_PSD10_FN3, 0,
-		PSD9_PSD8_FN1, PSD9_PSD8_FN2, 0, 0,
-		PSD7_PSD6_FN1, PSD7_PSD6_FN2, 0, 0,
-		PSD5_PSD4_FN1, PSD5_PSD4_FN2, 0, 0,
-		PSD3_PSD2_FN1, PSD3_PSD2_FN2, 0, 0,
-		PSD1_PSD0_FN1, PSD1_PSD0_FN2, 0, 0 ))
-	},
-	{}
-};
-
-static const struct pinmux_data_reg pinmux_data_regs[] = {
-	{ PINMUX_DATA_REG("PADR", 0xa4050120, 8, GROUP(
-		PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
-		PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PBDR", 0xa4050122, 8, GROUP(
-		PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
-		PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PCDR", 0xa4050124, 8, GROUP(
-		PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
-		PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PDDR", 0xa4050126, 8, GROUP(
-		PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
-		PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PEDR", 0xa4050128, 8, GROUP(
-		0, 0, PTE5_DATA, PTE4_DATA,
-		PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PFDR", 0xa405012a, 8, GROUP(
-		PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
-		PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PGDR", 0xa405012c, 8, GROUP(
-		0, 0, PTG5_DATA, PTG4_DATA,
-		PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PHDR", 0xa405012e, 8, GROUP(
-		PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
-		PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PJDR", 0xa4050130, 8, GROUP(
-		PTJ7_DATA, 0, PTJ5_DATA, 0,
-		PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PKDR", 0xa4050132, 8, GROUP(
-		PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
-		PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PLDR", 0xa4050134, 8, GROUP(
-		PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
-		PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PMDR", 0xa4050136, 8, GROUP(
-		PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
-		PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PNDR", 0xa4050138, 8, GROUP(
-		PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
-		PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PQDR", 0xa405013a, 8, GROUP(
-		0, 0, 0, 0,
-		PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PRDR", 0xa405013c, 8, GROUP(
-		PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
-		PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PSDR", 0xa405013e, 8, GROUP(
-		PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
-		PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PTDR", 0xa4050160, 8, GROUP(
-		0, 0, PTT5_DATA, PTT4_DATA,
-		PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PUDR", 0xa4050162, 8, GROUP(
-		0, 0, PTU5_DATA, PTU4_DATA,
-		PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PVDR", 0xa4050164, 8, GROUP(
-		PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
-		PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PWDR", 0xa4050166, 8, GROUP(
-		PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
-		PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PXDR", 0xa4050168, 8, GROUP(
-		PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
-		PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PYDR", 0xa405016a, 8, GROUP(
-		PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
-		PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PZDR", 0xa405016c, 8, GROUP(
-		PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
-		PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
-	},
-	{ },
-};
-
-const struct sh_pfc_soc_info sh7723_pinmux_info = {
-	.name = "sh7723_pfc",
-	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.func_gpios = pinmux_func_gpios,
-	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
-	.cfg_regs = pinmux_config_regs,
-	.data_regs = pinmux_data_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
deleted file mode 100644
index 7a18afecda2c..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c
+++ /dev/null
@@ -1,2177 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * SH7724 Pinmux
- *
- * Copyright (C) 2009 Renesas Solutions Corp.
- *
- * Kuninori Morimoto <morimoto.kuninori@renesas.com>
- *
- * Based on SH7723 Pinmux
- *  Copyright (C) 2008  Magnus Damm
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <cpu/sh7724.h>
-
-#include "sh_pfc.h"
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
-	PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA,
-	PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
-	PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA,
-	PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
-	PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA,
-	PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
-	PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA,
-	PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
-	PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA,
-	PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
-	PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA,
-			      PTG5_DATA, PTG4_DATA,
-	PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA,
-	PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
-	PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
-	PTJ7_DATA, PTJ6_DATA, PTJ5_DATA,
-	PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA,
-	PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
-	PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
-	PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
-	PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA,
-	PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
-	PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
-	PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
-	PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA,
-	PTQ7_DATA, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
-	PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA,
-	PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
-	PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
-		   PTS6_DATA, PTS5_DATA, PTS4_DATA,
-	PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
-	PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
-	PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
-	PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
-	PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
-	PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
-	PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA,
-	PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
-	PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA,
-	PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
-	PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA,
-	PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
-	PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA,
-	PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
-	PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA,
-	PINMUX_DATA_END,
-
-	PINMUX_INPUT_BEGIN,
-	PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN,
-	PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN,
-	PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN,
-	PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN,
-	PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN,
-	PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN,
-	PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN,
-	PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN,
-	PTE7_IN, PTE6_IN, PTE5_IN, PTE4_IN,
-	PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN,
-	PTF7_IN, PTF6_IN, PTF5_IN, PTF4_IN,
-	PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN,
-	PTH7_IN, PTH6_IN, PTH5_IN, PTH4_IN,
-	PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN,
-	PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN,
-	PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN,
-	PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN,
-	PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN,
-	PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN,
-	PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN,
-	PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
-	PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN,
-	PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN,
-	PTQ7_IN, PTQ6_IN, PTQ5_IN, PTQ4_IN,
-	PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN,
-	PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN,
-	PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN,
-		 PTS6_IN, PTS5_IN, PTS4_IN,
-	PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN,
-	PTT7_IN, PTT6_IN, PTT5_IN, PTT4_IN,
-	PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN,
-	PTU7_IN, PTU6_IN, PTU5_IN, PTU4_IN,
-	PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
-	PTV7_IN, PTV6_IN, PTV5_IN, PTV4_IN,
-	PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
-	PTW7_IN, PTW6_IN, PTW5_IN, PTW4_IN,
-	PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN,
-	PTX7_IN, PTX6_IN, PTX5_IN, PTX4_IN,
-	PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN,
-	PTY7_IN, PTY6_IN, PTY5_IN, PTY4_IN,
-	PTY3_IN, PTY2_IN, PTY1_IN, PTY0_IN,
-	PTZ7_IN, PTZ6_IN, PTZ5_IN, PTZ4_IN,
-	PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN,
-	PINMUX_INPUT_END,
-
-	PINMUX_OUTPUT_BEGIN,
-	PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT,
-	PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT,
-	PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
-	PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT,
-	PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT,
-	PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT,
-	PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT,
-	PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT,
-	PTE7_OUT, PTE6_OUT, PTE5_OUT, PTE4_OUT,
-	PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT,
-	PTF7_OUT, PTF6_OUT, PTF5_OUT, PTF4_OUT,
-	PTF3_OUT, PTF2_OUT, PTF1_OUT, PTF0_OUT,
-			    PTG5_OUT, PTG4_OUT,
-	PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT,
-	PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT,
-	PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
-	PTJ7_OUT, PTJ6_OUT, PTJ5_OUT,
-	PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT,
-	PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT,
-	PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT,
-	PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT,
-	PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT,
-	PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT,
-	PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
-	PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT,
-	PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT,
-	PTQ7_OUT, PTQ6_OUT, PTQ5_OUT, PTQ4_OUT,
-	PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT,
-	PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT,
-			    PTR1_OUT, PTR0_OUT,
-		  PTS6_OUT, PTS5_OUT, PTS4_OUT,
-	PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT,
-	PTT7_OUT, PTT6_OUT, PTT5_OUT, PTT4_OUT,
-	PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT,
-	PTU7_OUT, PTU6_OUT, PTU5_OUT, PTU4_OUT,
-	PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT,
-	PTV7_OUT, PTV6_OUT, PTV5_OUT, PTV4_OUT,
-	PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT,
-	PTW7_OUT, PTW6_OUT, PTW5_OUT, PTW4_OUT,
-	PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT,
-	PTX7_OUT, PTX6_OUT, PTX5_OUT, PTX4_OUT,
-	PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT,
-	PTY7_OUT, PTY6_OUT, PTY5_OUT, PTY4_OUT,
-	PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT,
-	PTZ7_OUT, PTZ6_OUT, PTZ5_OUT, PTZ4_OUT,
-	PTZ3_OUT, PTZ2_OUT, PTZ1_OUT, PTZ0_OUT,
-	PINMUX_OUTPUT_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN,
-	PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN,
-	PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN,
-	PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN,
-	PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN,
-	PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN,
-	PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN,
-	PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN,
-	PTE7_FN, PTE6_FN, PTE5_FN, PTE4_FN,
-	PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN,
-	PTF7_FN, PTF6_FN, PTF5_FN, PTF4_FN,
-	PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN,
-			  PTG5_FN, PTG4_FN,
-	PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN,
-	PTH7_FN, PTH6_FN, PTH5_FN, PTH4_FN,
-	PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN,
-	PTJ7_FN, PTJ6_FN, PTJ5_FN,
-	PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN,
-	PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN,
-	PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN,
-	PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN,
-	PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN,
-	PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN,
-	PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN,
-	PTN7_FN, PTN6_FN, PTN5_FN, PTN4_FN,
-	PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN,
-	PTQ7_FN, PTQ6_FN, PTQ5_FN, PTQ4_FN,
-	PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN,
-	PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN,
-	PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN,
-		 PTS6_FN, PTS5_FN, PTS4_FN,
-	PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN,
-	PTT7_FN, PTT6_FN, PTT5_FN, PTT4_FN,
-	PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN,
-	PTU7_FN, PTU6_FN, PTU5_FN, PTU4_FN,
-	PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN,
-	PTV7_FN, PTV6_FN, PTV5_FN, PTV4_FN,
-	PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN,
-	PTW7_FN, PTW6_FN, PTW5_FN, PTW4_FN,
-	PTW3_FN, PTW2_FN, PTW1_FN, PTW0_FN,
-	PTX7_FN, PTX6_FN, PTX5_FN, PTX4_FN,
-	PTX3_FN, PTX2_FN, PTX1_FN, PTX0_FN,
-	PTY7_FN, PTY6_FN, PTY5_FN, PTY4_FN,
-	PTY3_FN, PTY2_FN, PTY1_FN, PTY0_FN,
-	PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN,
-	PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN,
-
-
-	PSA15_0, PSA15_1,
-	PSA14_0, PSA14_1,
-	PSA13_0, PSA13_1,
-	PSA12_0, PSA12_1,
-	PSA10_0, PSA10_1,
-	PSA9_0,  PSA9_1,
-	PSA8_0,  PSA8_1,
-	PSA7_0,  PSA7_1,
-	PSA6_0,  PSA6_1,
-	PSA5_0,  PSA5_1,
-	PSA3_0,  PSA3_1,
-	PSA2_0,  PSA2_1,
-	PSA1_0,  PSA1_1,
-	PSA0_0,  PSA0_1,
-
-	PSB14_0, PSB14_1,
-	PSB13_0, PSB13_1,
-	PSB12_0, PSB12_1,
-	PSB11_0, PSB11_1,
-	PSB10_0, PSB10_1,
-	PSB9_0,  PSB9_1,
-	PSB8_0,  PSB8_1,
-	PSB7_0,  PSB7_1,
-	PSB6_0,  PSB6_1,
-	PSB5_0,  PSB5_1,
-	PSB4_0,  PSB4_1,
-	PSB3_0,  PSB3_1,
-	PSB2_0,  PSB2_1,
-	PSB1_0,  PSB1_1,
-	PSB0_0,  PSB0_1,
-
-	PSC15_0, PSC15_1,
-	PSC14_0, PSC14_1,
-	PSC13_0, PSC13_1,
-	PSC12_0, PSC12_1,
-	PSC11_0, PSC11_1,
-	PSC10_0, PSC10_1,
-	PSC9_0,  PSC9_1,
-	PSC8_0,  PSC8_1,
-	PSC7_0,  PSC7_1,
-	PSC6_0,  PSC6_1,
-	PSC5_0,  PSC5_1,
-	PSC4_0,  PSC4_1,
-	PSC2_0,  PSC2_1,
-	PSC1_0,  PSC1_1,
-	PSC0_0,  PSC0_1,
-
-	PSD15_0, PSD15_1,
-	PSD14_0, PSD14_1,
-	PSD13_0, PSD13_1,
-	PSD12_0, PSD12_1,
-	PSD11_0, PSD11_1,
-	PSD10_0, PSD10_1,
-	PSD9_0,  PSD9_1,
-	PSD8_0,  PSD8_1,
-	PSD7_0,  PSD7_1,
-	PSD6_0,  PSD6_1,
-	PSD5_0,  PSD5_1,
-	PSD4_0,  PSD4_1,
-	PSD3_0,  PSD3_1,
-	PSD2_0,  PSD2_1,
-	PSD1_0,  PSD1_1,
-	PSD0_0,  PSD0_1,
-
-	PSE15_0, PSE15_1,
-	PSE14_0, PSE14_1,
-	PSE13_0, PSE13_1,
-	PSE12_0, PSE12_1,
-	PSE11_0, PSE11_1,
-	PSE10_0, PSE10_1,
-	PSE9_0,  PSE9_1,
-	PSE8_0,  PSE8_1,
-	PSE7_0,  PSE7_1,
-	PSE6_0,  PSE6_1,
-	PSE5_0,  PSE5_1,
-	PSE4_0,  PSE4_1,
-	PSE3_0,  PSE3_1,
-	PSE2_0,  PSE2_1,
-	PSE1_0,  PSE1_1,
-	PSE0_0,  PSE0_1,
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-	/*PTA*/
-	D23_MARK,	KEYOUT2_MARK,		IDED15_MARK,
-	D22_MARK,	KEYOUT1_MARK,		IDED14_MARK,
-	D21_MARK,	KEYOUT0_MARK,		IDED13_MARK,
-	D20_MARK,	KEYIN4_MARK,		IDED12_MARK,
-	D19_MARK,	KEYIN3_MARK,		IDED11_MARK,
-	D18_MARK,	KEYIN2_MARK,		IDED10_MARK,
-	D17_MARK,	KEYIN1_MARK,		IDED9_MARK,
-	D16_MARK,	KEYIN0_MARK,		IDED8_MARK,
-
-	/*PTB*/
-	D31_MARK,	TPUTO1_MARK,		IDEA1_MARK,
-	D30_MARK,	TPUTO0_MARK,		IDEA0_MARK,
-	D29_MARK,				IODREQ_MARK,
-	D28_MARK,				IDECS0_MARK,
-	D27_MARK,				IDECS1_MARK,
-	D26_MARK,	KEYOUT5_IN5_MARK,	IDEIORD_MARK,
-	D25_MARK,	KEYOUT4_IN6_MARK,	IDEIOWR_MARK,
-	D24_MARK,	KEYOUT3_MARK,		IDEINT_MARK,
-
-	/*PTC*/
-	LCDD7_MARK,
-	LCDD6_MARK,
-	LCDD5_MARK,
-	LCDD4_MARK,
-	LCDD3_MARK,
-	LCDD2_MARK,
-	LCDD1_MARK,
-	LCDD0_MARK,
-
-	/*PTD*/
-	LCDD15_MARK,
-	LCDD14_MARK,
-	LCDD13_MARK,
-	LCDD12_MARK,
-	LCDD11_MARK,
-	LCDD10_MARK,
-	LCDD9_MARK,
-	LCDD8_MARK,
-
-	/*PTE*/
-	FSIMCKB_MARK,
-	FSIMCKA_MARK,
-	LCDD21_MARK,	SCIF2_L_TXD_MARK,
-	LCDD20_MARK,	SCIF4_SCK_MARK,
-	LCDD19_MARK,	SCIF4_RXD_MARK,
-	LCDD18_MARK,	SCIF4_TXD_MARK,
-	LCDD17_MARK,
-	LCDD16_MARK,
-
-	/*PTF*/
-	LCDVSYN_MARK,
-	LCDDISP_MARK,	LCDRS_MARK,
-	LCDHSYN_MARK,	LCDCS_MARK,
-	LCDDON_MARK,
-	LCDDCK_MARK,	LCDWR_MARK,
-	LCDVEPWC_MARK,	SCIF0_TXD_MARK,
-	LCDD23_MARK,	SCIF2_L_SCK_MARK,
-	LCDD22_MARK,	SCIF2_L_RXD_MARK,
-
-	/*PTG*/
-	AUDCK_MARK,
-	AUDSYNC_MARK,
-	AUDATA3_MARK,
-	AUDATA2_MARK,
-	AUDATA1_MARK,
-	AUDATA0_MARK,
-
-	/*PTH*/
-	VIO0_VD_MARK,
-	VIO0_CLK_MARK,
-	VIO0_D7_MARK,
-	VIO0_D6_MARK,
-	VIO0_D5_MARK,
-	VIO0_D4_MARK,
-	VIO0_D3_MARK,
-	VIO0_D2_MARK,
-
-	/*PTJ*/
-	PDSTATUS_MARK,
-	STATUS2_MARK,
-	STATUS0_MARK,
-	A25_MARK,		BS_MARK,
-	A24_MARK,
-	A23_MARK,
-	A22_MARK,
-
-	/*PTK*/
-	VIO1_D5_MARK,	VIO0_D13_MARK,	IDED5_MARK,
-	VIO1_D4_MARK,	VIO0_D12_MARK,	IDED4_MARK,
-	VIO1_D3_MARK,	VIO0_D11_MARK,	IDED3_MARK,
-	VIO1_D2_MARK,	VIO0_D10_MARK,	IDED2_MARK,
-	VIO1_D1_MARK,	VIO0_D9_MARK,	IDED1_MARK,
-	VIO1_D0_MARK,	VIO0_D8_MARK,	IDED0_MARK,
-	VIO0_FLD_MARK,
-	VIO0_HD_MARK,
-
-	/*PTL*/
-	DV_D5_MARK,	SCIF3_V_SCK_MARK,	RMII_RXD0_MARK,
-	DV_D4_MARK,	SCIF3_V_RXD_MARK,	RMII_RXD1_MARK,
-	DV_D3_MARK,	SCIF3_V_TXD_MARK,	RMII_REF_CLK_MARK,
-	DV_D2_MARK,	SCIF1_SCK_MARK,		RMII_TX_EN_MARK,
-	DV_D1_MARK,	SCIF1_RXD_MARK,		RMII_TXD0_MARK,
-	DV_D0_MARK,	SCIF1_TXD_MARK,		RMII_TXD1_MARK,
-	DV_D15_MARK,
-	DV_D14_MARK,	MSIOF0_MCK_MARK,
-
-	/*PTM*/
-	DV_D13_MARK,	MSIOF0_TSCK_MARK,
-	DV_D12_MARK,	MSIOF0_RXD_MARK,
-	DV_D11_MARK,	MSIOF0_TXD_MARK,
-	DV_D10_MARK,	MSIOF0_TSYNC_MARK,
-	DV_D9_MARK,	MSIOF0_SS1_MARK,	MSIOF0_RSCK_MARK,
-	DV_D8_MARK,	MSIOF0_SS2_MARK,	MSIOF0_RSYNC_MARK,
-	LCDVCPWC_MARK,	SCIF0_RXD_MARK,
-	LCDRD_MARK,	SCIF0_SCK_MARK,
-
-	/*PTN*/
-	VIO0_D1_MARK,
-	VIO0_D0_MARK,
-	DV_CLKI_MARK,
-	DV_CLK_MARK,	SCIF2_V_SCK_MARK,
-	DV_VSYNC_MARK,	SCIF2_V_RXD_MARK,
-	DV_HSYNC_MARK,	SCIF2_V_TXD_MARK,
-	DV_D7_MARK,	SCIF3_V_CTS_MARK,	RMII_RX_ER_MARK,
-	DV_D6_MARK,	SCIF3_V_RTS_MARK,	RMII_CRS_DV_MARK,
-
-	/*PTQ*/
-	D7_MARK,
-	D6_MARK,
-	D5_MARK,
-	D4_MARK,
-	D3_MARK,
-	D2_MARK,
-	D1_MARK,
-	D0_MARK,
-
-	/*PTR*/
-	CS6B_CE1B_MARK,
-	CS6A_CE2B_MARK,
-	CS5B_CE1A_MARK,
-	CS5A_CE2A_MARK,
-	IOIS16_MARK,		LCDLCLK_MARK,
-	WAIT_MARK,
-	WE3_ICIOWR_MARK,	TPUTO3_MARK,	TPUTI3_MARK,
-	WE2_ICIORD_MARK,	TPUTO2_MARK,	IDEA2_MARK,
-
-	/*PTS*/
-	VIO_CKO_MARK,
-	VIO1_FLD_MARK,	TPUTI2_MARK,		IDEIORDY_MARK,
-	VIO1_HD_MARK,	SCIF5_SCK_MARK,
-	VIO1_VD_MARK,	SCIF5_RXD_MARK,
-	VIO1_CLK_MARK,	SCIF5_TXD_MARK,
-	VIO1_D7_MARK,	VIO0_D15_MARK,		IDED7_MARK,
-	VIO1_D6_MARK,	VIO0_D14_MARK,		IDED6_MARK,
-
-	/*PTT*/
-	D15_MARK,
-	D14_MARK,
-	D13_MARK,
-	D12_MARK,
-	D11_MARK,
-	D10_MARK,
-	D9_MARK,
-	D8_MARK,
-
-	/*PTU*/
-	DMAC_DACK0_MARK,
-	DMAC_DREQ0_MARK,
-	FSIOASD_MARK,
-	FSIIABCK_MARK,
-	FSIIALRCK_MARK,
-	FSIOABCK_MARK,
-	FSIOALRCK_MARK,
-	CLKAUDIOAO_MARK,
-
-	/*PTV*/
-	FSIIBSD_MARK,		MSIOF1_SS2_MARK,	MSIOF1_RSYNC_MARK,
-	FSIOBSD_MARK,		MSIOF1_SS1_MARK,	MSIOF1_RSCK_MARK,
-	FSIIBBCK_MARK,		MSIOF1_RXD_MARK,
-	FSIIBLRCK_MARK,		MSIOF1_TSYNC_MARK,
-	FSIOBBCK_MARK,		MSIOF1_TSCK_MARK,
-	FSIOBLRCK_MARK,		MSIOF1_TXD_MARK,
-	CLKAUDIOBO_MARK,	MSIOF1_MCK_MARK,
-	FSIIASD_MARK,
-
-	/*PTW*/
-	MMC_D7_MARK,		SDHI1CD_MARK,		IODACK_MARK,
-	MMC_D6_MARK,		SDHI1WP_MARK,		IDERST_MARK,
-	MMC_D5_MARK,		SDHI1D3_MARK,		EXBUF_ENB_MARK,
-	MMC_D4_MARK,		SDHI1D2_MARK,		DIRECTION_MARK,
-	MMC_D3_MARK,		SDHI1D1_MARK,
-	MMC_D2_MARK,		SDHI1D0_MARK,
-	MMC_D1_MARK,		SDHI1CMD_MARK,
-	MMC_D0_MARK,		SDHI1CLK_MARK,
-
-	/*PTX*/
-	DMAC_DACK1_MARK,	IRDA_OUT_MARK,
-	DMAC_DREQ1_MARK,	IRDA_IN_MARK,
-	TSIF_TS0_SDAT_MARK,				LNKSTA_MARK,
-	TSIF_TS0_SCK_MARK,				MDIO_MARK,
-	TSIF_TS0_SDEN_MARK,				MDC_MARK,
-	TSIF_TS0_SPSYNC_MARK,
-	MMC_CLK_MARK,
-	MMC_CMD_MARK,
-
-	/*PTY*/
-	SDHI0CD_MARK,
-	SDHI0WP_MARK,
-	SDHI0D3_MARK,
-	SDHI0D2_MARK,
-	SDHI0D1_MARK,
-	SDHI0D0_MARK,
-	SDHI0CMD_MARK,
-	SDHI0CLK_MARK,
-
-	/*PTZ*/
-	INTC_IRQ7_MARK,		SCIF3_I_CTS_MARK,
-	INTC_IRQ6_MARK,		SCIF3_I_RTS_MARK,
-	INTC_IRQ5_MARK,		SCIF3_I_SCK_MARK,
-	INTC_IRQ4_MARK,		SCIF3_I_RXD_MARK,
-	INTC_IRQ3_MARK,		SCIF3_I_TXD_MARK,
-	INTC_IRQ2_MARK,
-	INTC_IRQ1_MARK,
-	INTC_IRQ0_MARK,
-	PINMUX_MARK_END,
-};
-
-static const u16 pinmux_data[] = {
-	/* PTA GPIO */
-	PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
-	PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
-	PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT),
-	PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT),
-	PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT),
-	PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT),
-	PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT),
-	PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT),
-
-	/* PTB GPIO */
-	PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT),
-	PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT),
-	PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT),
-	PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT),
-	PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT),
-	PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT),
-	PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT),
-	PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT),
-
-	/* PTC GPIO */
-	PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT),
-	PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT),
-	PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT),
-	PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT),
-	PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT),
-	PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT),
-	PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT),
-	PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT),
-
-	/* PTD GPIO */
-	PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT),
-	PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT),
-	PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT),
-	PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT),
-	PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT),
-	PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT),
-	PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT),
-	PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT),
-
-	/* PTE GPIO */
-	PINMUX_DATA(PTE7_DATA, PTE7_IN, PTE7_OUT),
-	PINMUX_DATA(PTE6_DATA, PTE6_IN, PTE6_OUT),
-	PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT),
-	PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT),
-	PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT),
-	PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT),
-	PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT),
-	PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT),
-
-	/* PTF GPIO */
-	PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT),
-	PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT),
-	PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT),
-	PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT),
-	PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT),
-	PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT),
-	PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT),
-	PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT),
-
-	/* PTG GPIO */
-	PINMUX_DATA(PTG5_DATA, PTG5_OUT),
-	PINMUX_DATA(PTG4_DATA, PTG4_OUT),
-	PINMUX_DATA(PTG3_DATA, PTG3_OUT),
-	PINMUX_DATA(PTG2_DATA, PTG2_OUT),
-	PINMUX_DATA(PTG1_DATA, PTG1_OUT),
-	PINMUX_DATA(PTG0_DATA, PTG0_OUT),
-
-	/* PTH GPIO */
-	PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT),
-	PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT),
-	PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT),
-	PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT),
-	PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT),
-	PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT),
-	PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT),
-	PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT),
-
-	/* PTJ GPIO */
-	PINMUX_DATA(PTJ7_DATA, PTJ7_OUT),
-	PINMUX_DATA(PTJ6_DATA, PTJ6_OUT),
-	PINMUX_DATA(PTJ5_DATA, PTJ5_OUT),
-	PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT),
-	PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT),
-	PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT),
-	PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT),
-
-	/* PTK GPIO */
-	PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT),
-	PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT),
-	PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT),
-	PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT),
-	PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT),
-	PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT),
-	PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT),
-	PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT),
-
-	/* PTL GPIO */
-	PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT),
-	PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT),
-	PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT),
-	PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT),
-	PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT),
-	PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT),
-	PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT),
-	PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT),
-
-	/* PTM GPIO */
-	PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT),
-	PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT),
-	PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT),
-	PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT),
-	PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT),
-	PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT),
-	PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT),
-	PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT),
-
-	/* PTN GPIO */
-	PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT),
-	PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT),
-	PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT),
-	PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT),
-	PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT),
-	PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT),
-	PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT),
-	PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT),
-
-	/* PTQ GPIO */
-	PINMUX_DATA(PTQ7_DATA, PTQ7_IN, PTQ7_OUT),
-	PINMUX_DATA(PTQ6_DATA, PTQ6_IN, PTQ6_OUT),
-	PINMUX_DATA(PTQ5_DATA, PTQ5_IN, PTQ5_OUT),
-	PINMUX_DATA(PTQ4_DATA, PTQ4_IN, PTQ4_OUT),
-	PINMUX_DATA(PTQ3_DATA, PTQ3_IN, PTQ3_OUT),
-	PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_OUT),
-	PINMUX_DATA(PTQ1_DATA, PTQ1_IN, PTQ1_OUT),
-	PINMUX_DATA(PTQ0_DATA, PTQ0_IN, PTQ0_OUT),
-
-	/* PTR GPIO */
-	PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT),
-	PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT),
-	PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT),
-	PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT),
-	PINMUX_DATA(PTR3_DATA, PTR3_IN),
-	PINMUX_DATA(PTR2_DATA, PTR2_IN),
-	PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT),
-	PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT),
-
-	/* PTS GPIO */
-	PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT),
-	PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT),
-	PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT),
-	PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT),
-	PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT),
-	PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT),
-	PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT),
-
-	/* PTT GPIO */
-	PINMUX_DATA(PTT7_DATA, PTT7_IN, PTT7_OUT),
-	PINMUX_DATA(PTT6_DATA, PTT6_IN, PTT6_OUT),
-	PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT),
-	PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT),
-	PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT),
-	PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT),
-	PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT),
-	PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT),
-
-	/* PTU GPIO */
-	PINMUX_DATA(PTU7_DATA, PTU7_IN, PTU7_OUT),
-	PINMUX_DATA(PTU6_DATA, PTU6_IN, PTU6_OUT),
-	PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT),
-	PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT),
-	PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT),
-	PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT),
-	PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT),
-	PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT),
-
-	/* PTV GPIO */
-	PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT),
-	PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT),
-	PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT),
-	PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT),
-	PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT),
-	PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT),
-	PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT),
-	PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT),
-
-	/* PTW GPIO */
-	PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT),
-	PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT),
-	PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT),
-	PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT),
-	PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT),
-	PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT),
-	PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT),
-	PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT),
-
-	/* PTX GPIO */
-	PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT),
-	PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT),
-	PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT),
-	PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT),
-	PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT),
-	PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT),
-	PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT),
-	PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT),
-
-	/* PTY GPIO */
-	PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT),
-	PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT),
-	PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT),
-	PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT),
-	PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT),
-	PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT),
-	PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT),
-	PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT),
-
-	/* PTZ GPIO */
-	PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT),
-	PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT),
-	PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT),
-	PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT),
-	PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT),
-	PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT),
-	PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT),
-	PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT),
-
-	/* PTA FN */
-	PINMUX_DATA(D23_MARK,	PSA15_0, PSA14_0, PTA7_FN),
-	PINMUX_DATA(D22_MARK,	PSA15_0, PSA14_0, PTA6_FN),
-	PINMUX_DATA(D21_MARK,	PSA15_0, PSA14_0, PTA5_FN),
-	PINMUX_DATA(D20_MARK,	PSA15_0, PSA14_0, PTA4_FN),
-	PINMUX_DATA(D19_MARK,	PSA15_0, PSA14_0, PTA3_FN),
-	PINMUX_DATA(D18_MARK,	PSA15_0, PSA14_0, PTA2_FN),
-	PINMUX_DATA(D17_MARK,	PSA15_0, PSA14_0, PTA1_FN),
-	PINMUX_DATA(D16_MARK,	PSA15_0, PSA14_0, PTA0_FN),
-
-	PINMUX_DATA(KEYOUT2_MARK,	PSA15_0, PSA14_1, PTA7_FN),
-	PINMUX_DATA(KEYOUT1_MARK,	PSA15_0, PSA14_1, PTA6_FN),
-	PINMUX_DATA(KEYOUT0_MARK,	PSA15_0, PSA14_1, PTA5_FN),
-	PINMUX_DATA(KEYIN4_MARK,	PSA15_0, PSA14_1, PTA4_FN),
-	PINMUX_DATA(KEYIN3_MARK,	PSA15_0, PSA14_1, PTA3_FN),
-	PINMUX_DATA(KEYIN2_MARK,	PSA15_0, PSA14_1, PTA2_FN),
-	PINMUX_DATA(KEYIN1_MARK,	PSA15_0, PSA14_1, PTA1_FN),
-	PINMUX_DATA(KEYIN0_MARK,	PSA15_0, PSA14_1, PTA0_FN),
-
-	PINMUX_DATA(IDED15_MARK,	PSA15_1, PSA14_0, PTA7_FN),
-	PINMUX_DATA(IDED14_MARK,	PSA15_1, PSA14_0, PTA6_FN),
-	PINMUX_DATA(IDED13_MARK,	PSA15_1, PSA14_0, PTA5_FN),
-	PINMUX_DATA(IDED12_MARK,	PSA15_1, PSA14_0, PTA4_FN),
-	PINMUX_DATA(IDED11_MARK,	PSA15_1, PSA14_0, PTA3_FN),
-	PINMUX_DATA(IDED10_MARK,	PSA15_1, PSA14_0, PTA2_FN),
-	PINMUX_DATA(IDED9_MARK,		PSA15_1, PSA14_0, PTA1_FN),
-	PINMUX_DATA(IDED8_MARK,		PSA15_1, PSA14_0, PTA0_FN),
-
-	/* PTB FN */
-	PINMUX_DATA(D31_MARK,		PSE15_0, PSE14_0, PTB7_FN),
-	PINMUX_DATA(D30_MARK,		PSE15_0, PSE14_0, PTB6_FN),
-	PINMUX_DATA(D29_MARK,		PSE11_0,          PTB5_FN),
-	PINMUX_DATA(D28_MARK,		PSE11_0,          PTB4_FN),
-	PINMUX_DATA(D27_MARK,		PSE11_0,          PTB3_FN),
-	PINMUX_DATA(D26_MARK,		PSA15_0, PSA14_0, PTB2_FN),
-	PINMUX_DATA(D25_MARK,		PSA15_0, PSA14_0, PTB1_FN),
-	PINMUX_DATA(D24_MARK,		PSA15_0, PSA14_0, PTB0_FN),
-
-	PINMUX_DATA(IDEA1_MARK,		PSE15_1, PSE14_0, PTB7_FN),
-	PINMUX_DATA(IDEA0_MARK,		PSE15_1, PSE14_0, PTB6_FN),
-	PINMUX_DATA(IODREQ_MARK,	PSE11_1,          PTB5_FN),
-	PINMUX_DATA(IDECS0_MARK,	PSE11_1,          PTB4_FN),
-	PINMUX_DATA(IDECS1_MARK,	PSE11_1,          PTB3_FN),
-	PINMUX_DATA(IDEIORD_MARK,	PSA15_1, PSA14_0, PTB2_FN),
-	PINMUX_DATA(IDEIOWR_MARK,	PSA15_1, PSA14_0, PTB1_FN),
-	PINMUX_DATA(IDEINT_MARK,	PSA15_1, PSA14_0, PTB0_FN),
-
-	PINMUX_DATA(TPUTO1_MARK,	PSE15_0, PSE14_1, PTB7_FN),
-	PINMUX_DATA(TPUTO0_MARK,	PSE15_0, PSE14_1, PTB6_FN),
-
-	PINMUX_DATA(KEYOUT5_IN5_MARK,	PSA15_0, PSA14_1, PTB2_FN),
-	PINMUX_DATA(KEYOUT4_IN6_MARK,	PSA15_0, PSA14_1, PTB1_FN),
-	PINMUX_DATA(KEYOUT3_MARK,	PSA15_0, PSA14_1, PTB0_FN),
-
-	/* PTC FN */
-	PINMUX_DATA(LCDD7_MARK, PSD5_0, PTC7_FN),
-	PINMUX_DATA(LCDD6_MARK, PSD5_0, PTC6_FN),
-	PINMUX_DATA(LCDD5_MARK, PSD5_0, PTC5_FN),
-	PINMUX_DATA(LCDD4_MARK, PSD5_0, PTC4_FN),
-	PINMUX_DATA(LCDD3_MARK, PSD5_0, PTC3_FN),
-	PINMUX_DATA(LCDD2_MARK, PSD5_0, PTC2_FN),
-	PINMUX_DATA(LCDD1_MARK, PSD5_0, PTC1_FN),
-	PINMUX_DATA(LCDD0_MARK, PSD5_0, PTC0_FN),
-
-	/* PTD FN */
-	PINMUX_DATA(LCDD15_MARK, PSD5_0, PTD7_FN),
-	PINMUX_DATA(LCDD14_MARK, PSD5_0, PTD6_FN),
-	PINMUX_DATA(LCDD13_MARK, PSD5_0, PTD5_FN),
-	PINMUX_DATA(LCDD12_MARK, PSD5_0, PTD4_FN),
-	PINMUX_DATA(LCDD11_MARK, PSD5_0, PTD3_FN),
-	PINMUX_DATA(LCDD10_MARK, PSD5_0, PTD2_FN),
-	PINMUX_DATA(LCDD9_MARK,  PSD5_0, PTD1_FN),
-	PINMUX_DATA(LCDD8_MARK,  PSD5_0, PTD0_FN),
-
-	/* PTE FN */
-	PINMUX_DATA(FSIMCKB_MARK, PTE7_FN),
-	PINMUX_DATA(FSIMCKA_MARK, PTE6_FN),
-
-	PINMUX_DATA(LCDD21_MARK,	PSC5_0, PSC4_0, PTE5_FN),
-	PINMUX_DATA(LCDD20_MARK,	PSD3_0, PSD2_0, PTE4_FN),
-	PINMUX_DATA(LCDD19_MARK,	PSA3_0, PSA2_0, PTE3_FN),
-	PINMUX_DATA(LCDD18_MARK,	PSA3_0, PSA2_0, PTE2_FN),
-	PINMUX_DATA(LCDD17_MARK,	PSD5_0,         PTE1_FN),
-	PINMUX_DATA(LCDD16_MARK,	PSD5_0,         PTE0_FN),
-
-	PINMUX_DATA(SCIF2_L_TXD_MARK,	PSC5_0, PSC4_1, PTE5_FN),
-	PINMUX_DATA(SCIF4_SCK_MARK,	PSD3_0, PSD2_1, PTE4_FN),
-	PINMUX_DATA(SCIF4_RXD_MARK,	PSA3_0, PSA2_1, PTE3_FN),
-	PINMUX_DATA(SCIF4_TXD_MARK,	PSA3_0, PSA2_1, PTE2_FN),
-
-	/* PTF FN */
-	PINMUX_DATA(LCDVSYN_MARK,	PSD8_0,          PTF7_FN),
-	PINMUX_DATA(LCDDISP_MARK,	PSD10_0, PSD9_0, PTF6_FN),
-	PINMUX_DATA(LCDHSYN_MARK,	PSD10_0, PSD9_0, PTF5_FN),
-	PINMUX_DATA(LCDDON_MARK,	PSD8_0,          PTF4_FN),
-	PINMUX_DATA(LCDDCK_MARK,	PSD10_0, PSD9_0, PTF3_FN),
-	PINMUX_DATA(LCDVEPWC_MARK,	PSA6_0,          PTF2_FN),
-	PINMUX_DATA(LCDD23_MARK,	PSC7_0,  PSC6_0, PTF1_FN),
-	PINMUX_DATA(LCDD22_MARK,	PSC5_0,  PSC4_0, PTF0_FN),
-
-	PINMUX_DATA(LCDRS_MARK,		PSD10_0, PSD9_1, PTF6_FN),
-	PINMUX_DATA(LCDCS_MARK,		PSD10_0, PSD9_1, PTF5_FN),
-	PINMUX_DATA(LCDWR_MARK,		PSD10_0, PSD9_1, PTF3_FN),
-
-	PINMUX_DATA(SCIF0_TXD_MARK,	PSA6_1,          PTF2_FN),
-	PINMUX_DATA(SCIF2_L_SCK_MARK,	PSC7_0,  PSC6_1, PTF1_FN),
-	PINMUX_DATA(SCIF2_L_RXD_MARK,	PSC5_0,  PSC4_1, PTF0_FN),
-
-	/* PTG FN */
-	PINMUX_DATA(AUDCK_MARK,   PTG5_FN),
-	PINMUX_DATA(AUDSYNC_MARK, PTG4_FN),
-	PINMUX_DATA(AUDATA3_MARK, PTG3_FN),
-	PINMUX_DATA(AUDATA2_MARK, PTG2_FN),
-	PINMUX_DATA(AUDATA1_MARK, PTG1_FN),
-	PINMUX_DATA(AUDATA0_MARK, PTG0_FN),
-
-	/* PTH FN */
-	PINMUX_DATA(VIO0_VD_MARK,  PTH7_FN),
-	PINMUX_DATA(VIO0_CLK_MARK, PTH6_FN),
-	PINMUX_DATA(VIO0_D7_MARK,  PTH5_FN),
-	PINMUX_DATA(VIO0_D6_MARK,  PTH4_FN),
-	PINMUX_DATA(VIO0_D5_MARK,  PTH3_FN),
-	PINMUX_DATA(VIO0_D4_MARK,  PTH2_FN),
-	PINMUX_DATA(VIO0_D3_MARK,  PTH1_FN),
-	PINMUX_DATA(VIO0_D2_MARK,  PTH0_FN),
-
-	/* PTJ FN */
-	PINMUX_DATA(PDSTATUS_MARK,	PTJ7_FN),
-	PINMUX_DATA(STATUS2_MARK,	PTJ6_FN),
-	PINMUX_DATA(STATUS0_MARK,	PTJ5_FN),
-	PINMUX_DATA(A25_MARK,		PSA8_0, PTJ3_FN),
-	PINMUX_DATA(BS_MARK,		PSA8_1, PTJ3_FN),
-	PINMUX_DATA(A24_MARK,		PTJ2_FN),
-	PINMUX_DATA(A23_MARK,		PTJ1_FN),
-	PINMUX_DATA(A22_MARK,		PTJ0_FN),
-
-	/* PTK FN */
-	PINMUX_DATA(VIO1_D5_MARK,	PSB7_0, PSB6_0, PTK7_FN),
-	PINMUX_DATA(VIO1_D4_MARK,	PSB7_0, PSB6_0, PTK6_FN),
-	PINMUX_DATA(VIO1_D3_MARK,	PSB7_0, PSB6_0, PTK5_FN),
-	PINMUX_DATA(VIO1_D2_MARK,	PSB7_0, PSB6_0, PTK4_FN),
-	PINMUX_DATA(VIO1_D1_MARK,	PSB7_0, PSB6_0, PTK3_FN),
-	PINMUX_DATA(VIO1_D0_MARK,	PSB7_0, PSB6_0, PTK2_FN),
-
-	PINMUX_DATA(VIO0_D13_MARK,	PSB7_0, PSB6_1, PTK7_FN),
-	PINMUX_DATA(VIO0_D12_MARK,	PSB7_0, PSB6_1, PTK6_FN),
-	PINMUX_DATA(VIO0_D11_MARK,	PSB7_0, PSB6_1, PTK5_FN),
-	PINMUX_DATA(VIO0_D10_MARK,	PSB7_0, PSB6_1, PTK4_FN),
-	PINMUX_DATA(VIO0_D9_MARK,	PSB7_0, PSB6_1, PTK3_FN),
-	PINMUX_DATA(VIO0_D8_MARK,	PSB7_0, PSB6_1, PTK2_FN),
-
-	PINMUX_DATA(IDED5_MARK,		PSB7_1, PSB6_0, PTK7_FN),
-	PINMUX_DATA(IDED4_MARK,		PSB7_1, PSB6_0, PTK6_FN),
-	PINMUX_DATA(IDED3_MARK,		PSB7_1, PSB6_0, PTK5_FN),
-	PINMUX_DATA(IDED2_MARK,		PSB7_1, PSB6_0, PTK4_FN),
-	PINMUX_DATA(IDED1_MARK,		PSB7_1, PSB6_0, PTK3_FN),
-	PINMUX_DATA(IDED0_MARK,		PSB7_1, PSB6_0, PTK2_FN),
-
-	PINMUX_DATA(VIO0_FLD_MARK,	PTK1_FN),
-	PINMUX_DATA(VIO0_HD_MARK,	PTK0_FN),
-
-	/* PTL FN */
-	PINMUX_DATA(DV_D5_MARK,		PSB9_0, PSB8_0, PTL7_FN),
-	PINMUX_DATA(DV_D4_MARK,		PSB9_0, PSB8_0, PTL6_FN),
-	PINMUX_DATA(DV_D3_MARK,		PSE7_0, PSE6_0, PTL5_FN),
-	PINMUX_DATA(DV_D2_MARK,		PSC9_0, PSC8_0, PTL4_FN),
-	PINMUX_DATA(DV_D1_MARK,		PSC9_0, PSC8_0, PTL3_FN),
-	PINMUX_DATA(DV_D0_MARK,		PSC9_0, PSC8_0, PTL2_FN),
-	PINMUX_DATA(DV_D15_MARK,	PSD4_0,         PTL1_FN),
-	PINMUX_DATA(DV_D14_MARK,	PSE5_0, PSE4_0, PTL0_FN),
-
-	PINMUX_DATA(SCIF3_V_SCK_MARK,	PSB9_0, PSB8_1, PTL7_FN),
-	PINMUX_DATA(SCIF3_V_RXD_MARK,	PSB9_0, PSB8_1, PTL6_FN),
-	PINMUX_DATA(SCIF3_V_TXD_MARK,	PSE7_0, PSE6_1, PTL5_FN),
-	PINMUX_DATA(SCIF1_SCK_MARK,	PSC9_0, PSC8_1, PTL4_FN),
-	PINMUX_DATA(SCIF1_RXD_MARK,	PSC9_0, PSC8_1, PTL3_FN),
-	PINMUX_DATA(SCIF1_TXD_MARK,	PSC9_0, PSC8_1, PTL2_FN),
-
-	PINMUX_DATA(RMII_RXD0_MARK,	PSB9_1, PSB8_0, PTL7_FN),
-	PINMUX_DATA(RMII_RXD1_MARK,	PSB9_1, PSB8_0, PTL6_FN),
-	PINMUX_DATA(RMII_REF_CLK_MARK,	PSE7_1, PSE6_0, PTL5_FN),
-	PINMUX_DATA(RMII_TX_EN_MARK,	PSC9_1, PSC8_0, PTL4_FN),
-	PINMUX_DATA(RMII_TXD0_MARK,	PSC9_1, PSC8_0, PTL3_FN),
-	PINMUX_DATA(RMII_TXD1_MARK,	PSC9_1, PSC8_0, PTL2_FN),
-
-	PINMUX_DATA(MSIOF0_MCK_MARK,	PSE5_0, PSE4_1, PTL0_FN),
-
-	/* PTM FN */
-	PINMUX_DATA(DV_D13_MARK,	PSC13_0, PSC12_0, PTM7_FN),
-	PINMUX_DATA(DV_D12_MARK,	PSC13_0, PSC12_0, PTM6_FN),
-	PINMUX_DATA(DV_D11_MARK,	PSC13_0, PSC12_0, PTM5_FN),
-	PINMUX_DATA(DV_D10_MARK,	PSC13_0, PSC12_0, PTM4_FN),
-	PINMUX_DATA(DV_D9_MARK,		PSC11_0, PSC10_0, PTM3_FN),
-	PINMUX_DATA(DV_D8_MARK,		PSC11_0, PSC10_0, PTM2_FN),
-
-	PINMUX_DATA(MSIOF0_TSCK_MARK,	PSC13_0, PSC12_1, PTM7_FN),
-	PINMUX_DATA(MSIOF0_RXD_MARK,	PSC13_0, PSC12_1, PTM6_FN),
-	PINMUX_DATA(MSIOF0_TXD_MARK,	PSC13_0, PSC12_1, PTM5_FN),
-	PINMUX_DATA(MSIOF0_TSYNC_MARK,	PSC13_0, PSC12_1, PTM4_FN),
-	PINMUX_DATA(MSIOF0_SS1_MARK,	PSC11_0, PSC10_1, PTM3_FN),
-	PINMUX_DATA(MSIOF0_RSCK_MARK,	PSC11_1, PSC10_0, PTM3_FN),
-	PINMUX_DATA(MSIOF0_SS2_MARK,	PSC11_0, PSC10_1, PTM2_FN),
-	PINMUX_DATA(MSIOF0_RSYNC_MARK,	PSC11_1, PSC10_0, PTM2_FN),
-
-	PINMUX_DATA(LCDVCPWC_MARK,	PSA6_0, PTM1_FN),
-	PINMUX_DATA(LCDRD_MARK,		PSA7_0, PTM0_FN),
-
-	PINMUX_DATA(SCIF0_RXD_MARK,	PSA6_1, PTM1_FN),
-	PINMUX_DATA(SCIF0_SCK_MARK,	PSA7_1, PTM0_FN),
-
-	/* PTN FN */
-	PINMUX_DATA(VIO0_D1_MARK,	PTN7_FN),
-	PINMUX_DATA(VIO0_D0_MARK,	PTN6_FN),
-
-	PINMUX_DATA(DV_CLKI_MARK,	PSD11_0,          PTN5_FN),
-	PINMUX_DATA(DV_CLK_MARK,	PSD13_0, PSD12_0, PTN4_FN),
-	PINMUX_DATA(DV_VSYNC_MARK,	PSD15_0, PSD14_0, PTN3_FN),
-	PINMUX_DATA(DV_HSYNC_MARK,	PSB5_0,  PSB4_0,  PTN2_FN),
-	PINMUX_DATA(DV_D7_MARK,		PSB3_0,  PSB2_0,  PTN1_FN),
-	PINMUX_DATA(DV_D6_MARK,		PSB1_0,  PSB0_0,  PTN0_FN),
-
-	PINMUX_DATA(SCIF2_V_SCK_MARK,	PSD13_0, PSD12_1, PTN4_FN),
-	PINMUX_DATA(SCIF2_V_RXD_MARK,	PSD15_0, PSD14_1, PTN3_FN),
-	PINMUX_DATA(SCIF2_V_TXD_MARK,	PSB5_0,  PSB4_1,  PTN2_FN),
-	PINMUX_DATA(SCIF3_V_CTS_MARK,	PSB3_0,  PSB2_1,  PTN1_FN),
-	PINMUX_DATA(SCIF3_V_RTS_MARK,	PSB1_0,  PSB0_1,  PTN0_FN),
-
-	PINMUX_DATA(RMII_RX_ER_MARK,	PSB3_1, PSB2_0, PTN1_FN),
-	PINMUX_DATA(RMII_CRS_DV_MARK,	PSB1_1, PSB0_0, PTN0_FN),
-
-	/* PTQ FN */
-	PINMUX_DATA(D7_MARK, PTQ7_FN),
-	PINMUX_DATA(D6_MARK, PTQ6_FN),
-	PINMUX_DATA(D5_MARK, PTQ5_FN),
-	PINMUX_DATA(D4_MARK, PTQ4_FN),
-	PINMUX_DATA(D3_MARK, PTQ3_FN),
-	PINMUX_DATA(D2_MARK, PTQ2_FN),
-	PINMUX_DATA(D1_MARK, PTQ1_FN),
-	PINMUX_DATA(D0_MARK, PTQ0_FN),
-
-	/* PTR FN */
-	PINMUX_DATA(CS6B_CE1B_MARK,	                PTR7_FN),
-	PINMUX_DATA(CS6A_CE2B_MARK,	                PTR6_FN),
-	PINMUX_DATA(CS5B_CE1A_MARK,	                PTR5_FN),
-	PINMUX_DATA(CS5A_CE2A_MARK,	                PTR4_FN),
-	PINMUX_DATA(IOIS16_MARK,	PSA5_0,         PTR3_FN),
-	PINMUX_DATA(WAIT_MARK,		                PTR2_FN),
-	PINMUX_DATA(WE3_ICIOWR_MARK,	PSA1_0, PSA0_0, PTR1_FN),
-	PINMUX_DATA(WE2_ICIORD_MARK,	PSD1_0, PSD0_0, PTR0_FN),
-
-	PINMUX_DATA(LCDLCLK_MARK,	PSA5_1,         PTR3_FN),
-
-	PINMUX_DATA(IDEA2_MARK,		PSD1_1, PSD0_0, PTR0_FN),
-
-	PINMUX_DATA(TPUTO3_MARK,	PSA1_0, PSA0_1, PTR1_FN),
-	PINMUX_DATA(TPUTI3_MARK,	PSA1_1, PSA0_0, PTR1_FN),
-	PINMUX_DATA(TPUTO2_MARK,	PSD1_0, PSD0_1, PTR0_FN),
-
-	/* PTS FN */
-	PINMUX_DATA(VIO_CKO_MARK,	PTS6_FN),
-
-	PINMUX_DATA(TPUTI2_MARK,	PSE9_0, PSE8_1, PTS5_FN),
-
-	PINMUX_DATA(IDEIORDY_MARK,	PSE9_1, PSE8_0, PTS5_FN),
-
-	PINMUX_DATA(VIO1_FLD_MARK,	PSE9_0, PSE8_0, PTS5_FN),
-	PINMUX_DATA(VIO1_HD_MARK,	PSA10_0,        PTS4_FN),
-	PINMUX_DATA(VIO1_VD_MARK,	PSA9_0,         PTS3_FN),
-	PINMUX_DATA(VIO1_CLK_MARK,	PSA9_0,         PTS2_FN),
-	PINMUX_DATA(VIO1_D7_MARK,	PSB7_0, PSB6_0, PTS1_FN),
-	PINMUX_DATA(VIO1_D6_MARK,	PSB7_0, PSB6_0, PTS0_FN),
-
-	PINMUX_DATA(SCIF5_SCK_MARK,	PSA10_1, PTS4_FN),
-	PINMUX_DATA(SCIF5_RXD_MARK,	PSA9_1,  PTS3_FN),
-	PINMUX_DATA(SCIF5_TXD_MARK,	PSA9_1,  PTS2_FN),
-
-	PINMUX_DATA(VIO0_D15_MARK,	PSB7_0, PSB6_1, PTS1_FN),
-	PINMUX_DATA(VIO0_D14_MARK,	PSB7_0, PSB6_1, PTS0_FN),
-
-	PINMUX_DATA(IDED7_MARK,		PSB7_1, PSB6_0, PTS1_FN),
-	PINMUX_DATA(IDED6_MARK,		PSB7_1, PSB6_0, PTS0_FN),
-
-	/* PTT FN */
-	PINMUX_DATA(D15_MARK, PTT7_FN),
-	PINMUX_DATA(D14_MARK, PTT6_FN),
-	PINMUX_DATA(D13_MARK, PTT5_FN),
-	PINMUX_DATA(D12_MARK, PTT4_FN),
-	PINMUX_DATA(D11_MARK, PTT3_FN),
-	PINMUX_DATA(D10_MARK, PTT2_FN),
-	PINMUX_DATA(D9_MARK,  PTT1_FN),
-	PINMUX_DATA(D8_MARK,  PTT0_FN),
-
-	/* PTU FN */
-	PINMUX_DATA(DMAC_DACK0_MARK, PTU7_FN),
-	PINMUX_DATA(DMAC_DREQ0_MARK, PTU6_FN),
-
-	PINMUX_DATA(FSIOASD_MARK,	PSE1_0, PTU5_FN),
-	PINMUX_DATA(FSIIABCK_MARK,	PSE1_0, PTU4_FN),
-	PINMUX_DATA(FSIIALRCK_MARK,	PSE1_0, PTU3_FN),
-	PINMUX_DATA(FSIOABCK_MARK,	PSE1_0, PTU2_FN),
-	PINMUX_DATA(FSIOALRCK_MARK,	PSE1_0, PTU1_FN),
-	PINMUX_DATA(CLKAUDIOAO_MARK,	PSE0_0, PTU0_FN),
-
-	/* PTV FN */
-	PINMUX_DATA(FSIIBSD_MARK,	PSD7_0,  PSD6_0,  PTV7_FN),
-	PINMUX_DATA(FSIOBSD_MARK,	PSD7_0,  PSD6_0,  PTV6_FN),
-	PINMUX_DATA(FSIIBBCK_MARK,	PSC15_0, PSC14_0, PTV5_FN),
-	PINMUX_DATA(FSIIBLRCK_MARK,	PSC15_0, PSC14_0, PTV4_FN),
-	PINMUX_DATA(FSIOBBCK_MARK,	PSC15_0, PSC14_0, PTV3_FN),
-	PINMUX_DATA(FSIOBLRCK_MARK,	PSC15_0, PSC14_0, PTV2_FN),
-	PINMUX_DATA(CLKAUDIOBO_MARK,	PSE3_0,  PSE2_0,  PTV1_FN),
-	PINMUX_DATA(FSIIASD_MARK,	PSE10_0,          PTV0_FN),
-
-	PINMUX_DATA(MSIOF1_SS2_MARK,	PSD7_0,  PSD6_1,  PTV7_FN),
-	PINMUX_DATA(MSIOF1_RSYNC_MARK,	PSD7_1,  PSD6_0,  PTV7_FN),
-	PINMUX_DATA(MSIOF1_SS1_MARK,	PSD7_0,  PSD6_1,  PTV6_FN),
-	PINMUX_DATA(MSIOF1_RSCK_MARK,	PSD7_1,  PSD6_0,  PTV6_FN),
-	PINMUX_DATA(MSIOF1_RXD_MARK,	PSC15_0, PSC14_1, PTV5_FN),
-	PINMUX_DATA(MSIOF1_TSYNC_MARK,	PSC15_0, PSC14_1, PTV4_FN),
-	PINMUX_DATA(MSIOF1_TSCK_MARK,	PSC15_0, PSC14_1, PTV3_FN),
-	PINMUX_DATA(MSIOF1_TXD_MARK,	PSC15_0, PSC14_1, PTV2_FN),
-	PINMUX_DATA(MSIOF1_MCK_MARK,	PSE3_0,  PSE2_1,  PTV1_FN),
-
-	/* PTW FN */
-	PINMUX_DATA(MMC_D7_MARK,	PSE13_0, PSE12_0, PTW7_FN),
-	PINMUX_DATA(MMC_D6_MARK,	PSE13_0, PSE12_0, PTW6_FN),
-	PINMUX_DATA(MMC_D5_MARK,	PSE13_0, PSE12_0, PTW5_FN),
-	PINMUX_DATA(MMC_D4_MARK,	PSE13_0, PSE12_0, PTW4_FN),
-	PINMUX_DATA(MMC_D3_MARK,	PSA13_0,          PTW3_FN),
-	PINMUX_DATA(MMC_D2_MARK,	PSA13_0,          PTW2_FN),
-	PINMUX_DATA(MMC_D1_MARK,	PSA13_0,          PTW1_FN),
-	PINMUX_DATA(MMC_D0_MARK,	PSA13_0,          PTW0_FN),
-
-	PINMUX_DATA(SDHI1CD_MARK,	PSE13_0, PSE12_1, PTW7_FN),
-	PINMUX_DATA(SDHI1WP_MARK,	PSE13_0, PSE12_1, PTW6_FN),
-	PINMUX_DATA(SDHI1D3_MARK,	PSE13_0, PSE12_1, PTW5_FN),
-	PINMUX_DATA(SDHI1D2_MARK,	PSE13_0, PSE12_1, PTW4_FN),
-	PINMUX_DATA(SDHI1D1_MARK,	PSA13_1,          PTW3_FN),
-	PINMUX_DATA(SDHI1D0_MARK,	PSA13_1,          PTW2_FN),
-	PINMUX_DATA(SDHI1CMD_MARK,	PSA13_1,          PTW1_FN),
-	PINMUX_DATA(SDHI1CLK_MARK,	PSA13_1,          PTW0_FN),
-
-	PINMUX_DATA(IODACK_MARK,	PSE13_1, PSE12_0, PTW7_FN),
-	PINMUX_DATA(IDERST_MARK,	PSE13_1, PSE12_0, PTW6_FN),
-	PINMUX_DATA(EXBUF_ENB_MARK,	PSE13_1, PSE12_0, PTW5_FN),
-	PINMUX_DATA(DIRECTION_MARK,	PSE13_1, PSE12_0, PTW4_FN),
-
-	/* PTX FN */
-	PINMUX_DATA(DMAC_DACK1_MARK,	PSA12_0, PTX7_FN),
-	PINMUX_DATA(DMAC_DREQ1_MARK,	PSA12_0, PTX6_FN),
-
-	PINMUX_DATA(IRDA_OUT_MARK,	PSA12_1, PTX7_FN),
-	PINMUX_DATA(IRDA_IN_MARK,	PSA12_1, PTX6_FN),
-
-	PINMUX_DATA(TSIF_TS0_SDAT_MARK,	PSC0_0, PTX5_FN),
-	PINMUX_DATA(TSIF_TS0_SCK_MARK,	PSC1_0, PTX4_FN),
-	PINMUX_DATA(TSIF_TS0_SDEN_MARK,	PSC2_0, PTX3_FN),
-	PINMUX_DATA(TSIF_TS0_SPSYNC_MARK,       PTX2_FN),
-
-	PINMUX_DATA(LNKSTA_MARK,	PSC0_1, PTX5_FN),
-	PINMUX_DATA(MDIO_MARK,		PSC1_1, PTX4_FN),
-	PINMUX_DATA(MDC_MARK,		PSC2_1, PTX3_FN),
-
-	PINMUX_DATA(MMC_CLK_MARK, PTX1_FN),
-	PINMUX_DATA(MMC_CMD_MARK, PTX0_FN),
-
-	/* PTY FN */
-	PINMUX_DATA(SDHI0CD_MARK,  PTY7_FN),
-	PINMUX_DATA(SDHI0WP_MARK,  PTY6_FN),
-	PINMUX_DATA(SDHI0D3_MARK,  PTY5_FN),
-	PINMUX_DATA(SDHI0D2_MARK,  PTY4_FN),
-	PINMUX_DATA(SDHI0D1_MARK,  PTY3_FN),
-	PINMUX_DATA(SDHI0D0_MARK,  PTY2_FN),
-	PINMUX_DATA(SDHI0CMD_MARK, PTY1_FN),
-	PINMUX_DATA(SDHI0CLK_MARK, PTY0_FN),
-
-	/* PTZ FN */
-	PINMUX_DATA(INTC_IRQ7_MARK,	PSB10_0, PTZ7_FN),
-	PINMUX_DATA(INTC_IRQ6_MARK,	PSB11_0, PTZ6_FN),
-	PINMUX_DATA(INTC_IRQ5_MARK,	PSB12_0, PTZ5_FN),
-	PINMUX_DATA(INTC_IRQ4_MARK,	PSB13_0, PTZ4_FN),
-	PINMUX_DATA(INTC_IRQ3_MARK,	PSB14_0, PTZ3_FN),
-	PINMUX_DATA(INTC_IRQ2_MARK,	         PTZ2_FN),
-	PINMUX_DATA(INTC_IRQ1_MARK,	         PTZ1_FN),
-	PINMUX_DATA(INTC_IRQ0_MARK,	         PTZ0_FN),
-
-	PINMUX_DATA(SCIF3_I_CTS_MARK,	PSB10_1, PTZ7_FN),
-	PINMUX_DATA(SCIF3_I_RTS_MARK,	PSB11_1, PTZ6_FN),
-	PINMUX_DATA(SCIF3_I_SCK_MARK,	PSB12_1, PTZ5_FN),
-	PINMUX_DATA(SCIF3_I_RXD_MARK,	PSB13_1, PTZ4_FN),
-	PINMUX_DATA(SCIF3_I_TXD_MARK,	PSB14_1, PTZ3_FN),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	/* PTA */
-	PINMUX_GPIO(PTA7),
-	PINMUX_GPIO(PTA6),
-	PINMUX_GPIO(PTA5),
-	PINMUX_GPIO(PTA4),
-	PINMUX_GPIO(PTA3),
-	PINMUX_GPIO(PTA2),
-	PINMUX_GPIO(PTA1),
-	PINMUX_GPIO(PTA0),
-
-	/* PTB */
-	PINMUX_GPIO(PTB7),
-	PINMUX_GPIO(PTB6),
-	PINMUX_GPIO(PTB5),
-	PINMUX_GPIO(PTB4),
-	PINMUX_GPIO(PTB3),
-	PINMUX_GPIO(PTB2),
-	PINMUX_GPIO(PTB1),
-	PINMUX_GPIO(PTB0),
-
-	/* PTC */
-	PINMUX_GPIO(PTC7),
-	PINMUX_GPIO(PTC6),
-	PINMUX_GPIO(PTC5),
-	PINMUX_GPIO(PTC4),
-	PINMUX_GPIO(PTC3),
-	PINMUX_GPIO(PTC2),
-	PINMUX_GPIO(PTC1),
-	PINMUX_GPIO(PTC0),
-
-	/* PTD */
-	PINMUX_GPIO(PTD7),
-	PINMUX_GPIO(PTD6),
-	PINMUX_GPIO(PTD5),
-	PINMUX_GPIO(PTD4),
-	PINMUX_GPIO(PTD3),
-	PINMUX_GPIO(PTD2),
-	PINMUX_GPIO(PTD1),
-	PINMUX_GPIO(PTD0),
-
-	/* PTE */
-	PINMUX_GPIO(PTE7),
-	PINMUX_GPIO(PTE6),
-	PINMUX_GPIO(PTE5),
-	PINMUX_GPIO(PTE4),
-	PINMUX_GPIO(PTE3),
-	PINMUX_GPIO(PTE2),
-	PINMUX_GPIO(PTE1),
-	PINMUX_GPIO(PTE0),
-
-	/* PTF */
-	PINMUX_GPIO(PTF7),
-	PINMUX_GPIO(PTF6),
-	PINMUX_GPIO(PTF5),
-	PINMUX_GPIO(PTF4),
-	PINMUX_GPIO(PTF3),
-	PINMUX_GPIO(PTF2),
-	PINMUX_GPIO(PTF1),
-	PINMUX_GPIO(PTF0),
-
-	/* PTG */
-	PINMUX_GPIO(PTG5),
-	PINMUX_GPIO(PTG4),
-	PINMUX_GPIO(PTG3),
-	PINMUX_GPIO(PTG2),
-	PINMUX_GPIO(PTG1),
-	PINMUX_GPIO(PTG0),
-
-	/* PTH */
-	PINMUX_GPIO(PTH7),
-	PINMUX_GPIO(PTH6),
-	PINMUX_GPIO(PTH5),
-	PINMUX_GPIO(PTH4),
-	PINMUX_GPIO(PTH3),
-	PINMUX_GPIO(PTH2),
-	PINMUX_GPIO(PTH1),
-	PINMUX_GPIO(PTH0),
-
-	/* PTJ */
-	PINMUX_GPIO(PTJ7),
-	PINMUX_GPIO(PTJ6),
-	PINMUX_GPIO(PTJ5),
-	PINMUX_GPIO(PTJ3),
-	PINMUX_GPIO(PTJ2),
-	PINMUX_GPIO(PTJ1),
-	PINMUX_GPIO(PTJ0),
-
-	/* PTK */
-	PINMUX_GPIO(PTK7),
-	PINMUX_GPIO(PTK6),
-	PINMUX_GPIO(PTK5),
-	PINMUX_GPIO(PTK4),
-	PINMUX_GPIO(PTK3),
-	PINMUX_GPIO(PTK2),
-	PINMUX_GPIO(PTK1),
-	PINMUX_GPIO(PTK0),
-
-	/* PTL */
-	PINMUX_GPIO(PTL7),
-	PINMUX_GPIO(PTL6),
-	PINMUX_GPIO(PTL5),
-	PINMUX_GPIO(PTL4),
-	PINMUX_GPIO(PTL3),
-	PINMUX_GPIO(PTL2),
-	PINMUX_GPIO(PTL1),
-	PINMUX_GPIO(PTL0),
-
-	/* PTM */
-	PINMUX_GPIO(PTM7),
-	PINMUX_GPIO(PTM6),
-	PINMUX_GPIO(PTM5),
-	PINMUX_GPIO(PTM4),
-	PINMUX_GPIO(PTM3),
-	PINMUX_GPIO(PTM2),
-	PINMUX_GPIO(PTM1),
-	PINMUX_GPIO(PTM0),
-
-	/* PTN */
-	PINMUX_GPIO(PTN7),
-	PINMUX_GPIO(PTN6),
-	PINMUX_GPIO(PTN5),
-	PINMUX_GPIO(PTN4),
-	PINMUX_GPIO(PTN3),
-	PINMUX_GPIO(PTN2),
-	PINMUX_GPIO(PTN1),
-	PINMUX_GPIO(PTN0),
-
-	/* PTQ */
-	PINMUX_GPIO(PTQ7),
-	PINMUX_GPIO(PTQ6),
-	PINMUX_GPIO(PTQ5),
-	PINMUX_GPIO(PTQ4),
-	PINMUX_GPIO(PTQ3),
-	PINMUX_GPIO(PTQ2),
-	PINMUX_GPIO(PTQ1),
-	PINMUX_GPIO(PTQ0),
-
-	/* PTR */
-	PINMUX_GPIO(PTR7),
-	PINMUX_GPIO(PTR6),
-	PINMUX_GPIO(PTR5),
-	PINMUX_GPIO(PTR4),
-	PINMUX_GPIO(PTR3),
-	PINMUX_GPIO(PTR2),
-	PINMUX_GPIO(PTR1),
-	PINMUX_GPIO(PTR0),
-
-	/* PTS */
-	PINMUX_GPIO(PTS6),
-	PINMUX_GPIO(PTS5),
-	PINMUX_GPIO(PTS4),
-	PINMUX_GPIO(PTS3),
-	PINMUX_GPIO(PTS2),
-	PINMUX_GPIO(PTS1),
-	PINMUX_GPIO(PTS0),
-
-	/* PTT */
-	PINMUX_GPIO(PTT7),
-	PINMUX_GPIO(PTT6),
-	PINMUX_GPIO(PTT5),
-	PINMUX_GPIO(PTT4),
-	PINMUX_GPIO(PTT3),
-	PINMUX_GPIO(PTT2),
-	PINMUX_GPIO(PTT1),
-	PINMUX_GPIO(PTT0),
-
-	/* PTU */
-	PINMUX_GPIO(PTU7),
-	PINMUX_GPIO(PTU6),
-	PINMUX_GPIO(PTU5),
-	PINMUX_GPIO(PTU4),
-	PINMUX_GPIO(PTU3),
-	PINMUX_GPIO(PTU2),
-	PINMUX_GPIO(PTU1),
-	PINMUX_GPIO(PTU0),
-
-	/* PTV */
-	PINMUX_GPIO(PTV7),
-	PINMUX_GPIO(PTV6),
-	PINMUX_GPIO(PTV5),
-	PINMUX_GPIO(PTV4),
-	PINMUX_GPIO(PTV3),
-	PINMUX_GPIO(PTV2),
-	PINMUX_GPIO(PTV1),
-	PINMUX_GPIO(PTV0),
-
-	/* PTW */
-	PINMUX_GPIO(PTW7),
-	PINMUX_GPIO(PTW6),
-	PINMUX_GPIO(PTW5),
-	PINMUX_GPIO(PTW4),
-	PINMUX_GPIO(PTW3),
-	PINMUX_GPIO(PTW2),
-	PINMUX_GPIO(PTW1),
-	PINMUX_GPIO(PTW0),
-
-	/* PTX */
-	PINMUX_GPIO(PTX7),
-	PINMUX_GPIO(PTX6),
-	PINMUX_GPIO(PTX5),
-	PINMUX_GPIO(PTX4),
-	PINMUX_GPIO(PTX3),
-	PINMUX_GPIO(PTX2),
-	PINMUX_GPIO(PTX1),
-	PINMUX_GPIO(PTX0),
-
-	/* PTY */
-	PINMUX_GPIO(PTY7),
-	PINMUX_GPIO(PTY6),
-	PINMUX_GPIO(PTY5),
-	PINMUX_GPIO(PTY4),
-	PINMUX_GPIO(PTY3),
-	PINMUX_GPIO(PTY2),
-	PINMUX_GPIO(PTY1),
-	PINMUX_GPIO(PTY0),
-
-	/* PTZ */
-	PINMUX_GPIO(PTZ7),
-	PINMUX_GPIO(PTZ6),
-	PINMUX_GPIO(PTZ5),
-	PINMUX_GPIO(PTZ4),
-	PINMUX_GPIO(PTZ3),
-	PINMUX_GPIO(PTZ2),
-	PINMUX_GPIO(PTZ1),
-	PINMUX_GPIO(PTZ0),
-};
-
-#define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-	/* BSC */
-	GPIO_FN(D31),
-	GPIO_FN(D30),
-	GPIO_FN(D29),
-	GPIO_FN(D28),
-	GPIO_FN(D27),
-	GPIO_FN(D26),
-	GPIO_FN(D25),
-	GPIO_FN(D24),
-	GPIO_FN(D23),
-	GPIO_FN(D22),
-	GPIO_FN(D21),
-	GPIO_FN(D20),
-	GPIO_FN(D19),
-	GPIO_FN(D18),
-	GPIO_FN(D17),
-	GPIO_FN(D16),
-	GPIO_FN(D15),
-	GPIO_FN(D14),
-	GPIO_FN(D13),
-	GPIO_FN(D12),
-	GPIO_FN(D11),
-	GPIO_FN(D10),
-	GPIO_FN(D9),
-	GPIO_FN(D8),
-	GPIO_FN(D7),
-	GPIO_FN(D6),
-	GPIO_FN(D5),
-	GPIO_FN(D4),
-	GPIO_FN(D3),
-	GPIO_FN(D2),
-	GPIO_FN(D1),
-	GPIO_FN(D0),
-	GPIO_FN(A25),
-	GPIO_FN(A24),
-	GPIO_FN(A23),
-	GPIO_FN(A22),
-	GPIO_FN(CS6B_CE1B),
-	GPIO_FN(CS6A_CE2B),
-	GPIO_FN(CS5B_CE1A),
-	GPIO_FN(CS5A_CE2A),
-	GPIO_FN(WE3_ICIOWR),
-	GPIO_FN(WE2_ICIORD),
-	GPIO_FN(IOIS16),
-	GPIO_FN(WAIT),
-	GPIO_FN(BS),
-
-	/* KEYSC */
-	GPIO_FN(KEYOUT5_IN5),
-	GPIO_FN(KEYOUT4_IN6),
-	GPIO_FN(KEYIN4),
-	GPIO_FN(KEYIN3),
-	GPIO_FN(KEYIN2),
-	GPIO_FN(KEYIN1),
-	GPIO_FN(KEYIN0),
-	GPIO_FN(KEYOUT3),
-	GPIO_FN(KEYOUT2),
-	GPIO_FN(KEYOUT1),
-	GPIO_FN(KEYOUT0),
-
-	/* ATAPI */
-	GPIO_FN(IDED15),
-	GPIO_FN(IDED14),
-	GPIO_FN(IDED13),
-	GPIO_FN(IDED12),
-	GPIO_FN(IDED11),
-	GPIO_FN(IDED10),
-	GPIO_FN(IDED9),
-	GPIO_FN(IDED8),
-	GPIO_FN(IDED7),
-	GPIO_FN(IDED6),
-	GPIO_FN(IDED5),
-	GPIO_FN(IDED4),
-	GPIO_FN(IDED3),
-	GPIO_FN(IDED2),
-	GPIO_FN(IDED1),
-	GPIO_FN(IDED0),
-	GPIO_FN(IDEA2),
-	GPIO_FN(IDEA1),
-	GPIO_FN(IDEA0),
-	GPIO_FN(IDEIOWR),
-	GPIO_FN(IODREQ),
-	GPIO_FN(IDECS0),
-	GPIO_FN(IDECS1),
-	GPIO_FN(IDEIORD),
-	GPIO_FN(DIRECTION),
-	GPIO_FN(EXBUF_ENB),
-	GPIO_FN(IDERST),
-	GPIO_FN(IODACK),
-	GPIO_FN(IDEINT),
-	GPIO_FN(IDEIORDY),
-
-	/* TPU */
-	GPIO_FN(TPUTO3),
-	GPIO_FN(TPUTO2),
-	GPIO_FN(TPUTO1),
-	GPIO_FN(TPUTO0),
-	GPIO_FN(TPUTI3),
-	GPIO_FN(TPUTI2),
-
-	/* LCDC */
-	GPIO_FN(LCDD23),
-	GPIO_FN(LCDD22),
-	GPIO_FN(LCDD21),
-	GPIO_FN(LCDD20),
-	GPIO_FN(LCDD19),
-	GPIO_FN(LCDD18),
-	GPIO_FN(LCDD17),
-	GPIO_FN(LCDD16),
-	GPIO_FN(LCDD15),
-	GPIO_FN(LCDD14),
-	GPIO_FN(LCDD13),
-	GPIO_FN(LCDD12),
-	GPIO_FN(LCDD11),
-	GPIO_FN(LCDD10),
-	GPIO_FN(LCDD9),
-	GPIO_FN(LCDD8),
-	GPIO_FN(LCDD7),
-	GPIO_FN(LCDD6),
-	GPIO_FN(LCDD5),
-	GPIO_FN(LCDD4),
-	GPIO_FN(LCDD3),
-	GPIO_FN(LCDD2),
-	GPIO_FN(LCDD1),
-	GPIO_FN(LCDD0),
-	GPIO_FN(LCDVSYN),
-	GPIO_FN(LCDDISP),
-	GPIO_FN(LCDRS),
-	GPIO_FN(LCDHSYN),
-	GPIO_FN(LCDCS),
-	GPIO_FN(LCDDON),
-	GPIO_FN(LCDDCK),
-	GPIO_FN(LCDWR),
-	GPIO_FN(LCDVEPWC),
-	GPIO_FN(LCDVCPWC),
-	GPIO_FN(LCDRD),
-	GPIO_FN(LCDLCLK),
-
-	/* SCIF0 */
-	GPIO_FN(SCIF0_TXD),
-	GPIO_FN(SCIF0_RXD),
-	GPIO_FN(SCIF0_SCK),
-
-	/* SCIF1 */
-	GPIO_FN(SCIF1_SCK),
-	GPIO_FN(SCIF1_RXD),
-	GPIO_FN(SCIF1_TXD),
-
-	/* SCIF2 */
-	GPIO_FN(SCIF2_L_TXD),
-	GPIO_FN(SCIF2_L_SCK),
-	GPIO_FN(SCIF2_L_RXD),
-	GPIO_FN(SCIF2_V_TXD),
-	GPIO_FN(SCIF2_V_SCK),
-	GPIO_FN(SCIF2_V_RXD),
-
-	/* SCIF3 */
-	GPIO_FN(SCIF3_V_SCK),
-	GPIO_FN(SCIF3_V_RXD),
-	GPIO_FN(SCIF3_V_TXD),
-	GPIO_FN(SCIF3_V_CTS),
-	GPIO_FN(SCIF3_V_RTS),
-	GPIO_FN(SCIF3_I_SCK),
-	GPIO_FN(SCIF3_I_RXD),
-	GPIO_FN(SCIF3_I_TXD),
-	GPIO_FN(SCIF3_I_CTS),
-	GPIO_FN(SCIF3_I_RTS),
-
-	/* SCIF4 */
-	GPIO_FN(SCIF4_SCK),
-	GPIO_FN(SCIF4_RXD),
-	GPIO_FN(SCIF4_TXD),
-
-	/* SCIF5 */
-	GPIO_FN(SCIF5_SCK),
-	GPIO_FN(SCIF5_RXD),
-	GPIO_FN(SCIF5_TXD),
-
-	/* FSI */
-	GPIO_FN(FSIMCKB),
-	GPIO_FN(FSIMCKA),
-	GPIO_FN(FSIOASD),
-	GPIO_FN(FSIIABCK),
-	GPIO_FN(FSIIALRCK),
-	GPIO_FN(FSIOABCK),
-	GPIO_FN(FSIOALRCK),
-	GPIO_FN(CLKAUDIOAO),
-	GPIO_FN(FSIIBSD),
-	GPIO_FN(FSIOBSD),
-	GPIO_FN(FSIIBBCK),
-	GPIO_FN(FSIIBLRCK),
-	GPIO_FN(FSIOBBCK),
-	GPIO_FN(FSIOBLRCK),
-	GPIO_FN(CLKAUDIOBO),
-	GPIO_FN(FSIIASD),
-
-	/* AUD */
-	GPIO_FN(AUDCK),
-	GPIO_FN(AUDSYNC),
-	GPIO_FN(AUDATA3),
-	GPIO_FN(AUDATA2),
-	GPIO_FN(AUDATA1),
-	GPIO_FN(AUDATA0),
-
-	/* VIO */
-	GPIO_FN(VIO_CKO),
-
-	/* VIO0 */
-	GPIO_FN(VIO0_D15),
-	GPIO_FN(VIO0_D14),
-	GPIO_FN(VIO0_D13),
-	GPIO_FN(VIO0_D12),
-	GPIO_FN(VIO0_D11),
-	GPIO_FN(VIO0_D10),
-	GPIO_FN(VIO0_D9),
-	GPIO_FN(VIO0_D8),
-	GPIO_FN(VIO0_D7),
-	GPIO_FN(VIO0_D6),
-	GPIO_FN(VIO0_D5),
-	GPIO_FN(VIO0_D4),
-	GPIO_FN(VIO0_D3),
-	GPIO_FN(VIO0_D2),
-	GPIO_FN(VIO0_D1),
-	GPIO_FN(VIO0_D0),
-	GPIO_FN(VIO0_VD),
-	GPIO_FN(VIO0_CLK),
-	GPIO_FN(VIO0_FLD),
-	GPIO_FN(VIO0_HD),
-
-	/* VIO1 */
-	GPIO_FN(VIO1_D7),
-	GPIO_FN(VIO1_D6),
-	GPIO_FN(VIO1_D5),
-	GPIO_FN(VIO1_D4),
-	GPIO_FN(VIO1_D3),
-	GPIO_FN(VIO1_D2),
-	GPIO_FN(VIO1_D1),
-	GPIO_FN(VIO1_D0),
-	GPIO_FN(VIO1_FLD),
-	GPIO_FN(VIO1_HD),
-	GPIO_FN(VIO1_VD),
-	GPIO_FN(VIO1_CLK),
-
-	/* Eth */
-	GPIO_FN(RMII_RXD0),
-	GPIO_FN(RMII_RXD1),
-	GPIO_FN(RMII_TXD0),
-	GPIO_FN(RMII_TXD1),
-	GPIO_FN(RMII_REF_CLK),
-	GPIO_FN(RMII_TX_EN),
-	GPIO_FN(RMII_RX_ER),
-	GPIO_FN(RMII_CRS_DV),
-	GPIO_FN(LNKSTA),
-	GPIO_FN(MDIO),
-	GPIO_FN(MDC),
-
-	/* System */
-	GPIO_FN(PDSTATUS),
-	GPIO_FN(STATUS2),
-	GPIO_FN(STATUS0),
-
-	/* VOU */
-	GPIO_FN(DV_D15),
-	GPIO_FN(DV_D14),
-	GPIO_FN(DV_D13),
-	GPIO_FN(DV_D12),
-	GPIO_FN(DV_D11),
-	GPIO_FN(DV_D10),
-	GPIO_FN(DV_D9),
-	GPIO_FN(DV_D8),
-	GPIO_FN(DV_D7),
-	GPIO_FN(DV_D6),
-	GPIO_FN(DV_D5),
-	GPIO_FN(DV_D4),
-	GPIO_FN(DV_D3),
-	GPIO_FN(DV_D2),
-	GPIO_FN(DV_D1),
-	GPIO_FN(DV_D0),
-	GPIO_FN(DV_CLKI),
-	GPIO_FN(DV_CLK),
-	GPIO_FN(DV_VSYNC),
-	GPIO_FN(DV_HSYNC),
-
-	/* MSIOF0 */
-	GPIO_FN(MSIOF0_RXD),
-	GPIO_FN(MSIOF0_TXD),
-	GPIO_FN(MSIOF0_MCK),
-	GPIO_FN(MSIOF0_TSCK),
-	GPIO_FN(MSIOF0_SS1),
-	GPIO_FN(MSIOF0_SS2),
-	GPIO_FN(MSIOF0_TSYNC),
-	GPIO_FN(MSIOF0_RSCK),
-	GPIO_FN(MSIOF0_RSYNC),
-
-	/* MSIOF1 */
-	GPIO_FN(MSIOF1_RXD),
-	GPIO_FN(MSIOF1_TXD),
-	GPIO_FN(MSIOF1_MCK),
-	GPIO_FN(MSIOF1_TSCK),
-	GPIO_FN(MSIOF1_SS1),
-	GPIO_FN(MSIOF1_SS2),
-	GPIO_FN(MSIOF1_TSYNC),
-	GPIO_FN(MSIOF1_RSCK),
-	GPIO_FN(MSIOF1_RSYNC),
-
-	/* DMAC */
-	GPIO_FN(DMAC_DACK0),
-	GPIO_FN(DMAC_DREQ0),
-	GPIO_FN(DMAC_DACK1),
-	GPIO_FN(DMAC_DREQ1),
-
-	/* SDHI0 */
-	GPIO_FN(SDHI0CD),
-	GPIO_FN(SDHI0WP),
-	GPIO_FN(SDHI0CMD),
-	GPIO_FN(SDHI0CLK),
-	GPIO_FN(SDHI0D3),
-	GPIO_FN(SDHI0D2),
-	GPIO_FN(SDHI0D1),
-	GPIO_FN(SDHI0D0),
-
-	/* SDHI1 */
-	GPIO_FN(SDHI1CD),
-	GPIO_FN(SDHI1WP),
-	GPIO_FN(SDHI1CMD),
-	GPIO_FN(SDHI1CLK),
-	GPIO_FN(SDHI1D3),
-	GPIO_FN(SDHI1D2),
-	GPIO_FN(SDHI1D1),
-	GPIO_FN(SDHI1D0),
-
-	/* MMC */
-	GPIO_FN(MMC_D7),
-	GPIO_FN(MMC_D6),
-	GPIO_FN(MMC_D5),
-	GPIO_FN(MMC_D4),
-	GPIO_FN(MMC_D3),
-	GPIO_FN(MMC_D2),
-	GPIO_FN(MMC_D1),
-	GPIO_FN(MMC_D0),
-	GPIO_FN(MMC_CLK),
-	GPIO_FN(MMC_CMD),
-
-	/* IrDA */
-	GPIO_FN(IRDA_OUT),
-	GPIO_FN(IRDA_IN),
-
-	/* TSIF */
-	GPIO_FN(TSIF_TS0_SDAT),
-	GPIO_FN(TSIF_TS0_SCK),
-	GPIO_FN(TSIF_TS0_SDEN),
-	GPIO_FN(TSIF_TS0_SPSYNC),
-
-	/* IRQ */
-	GPIO_FN(INTC_IRQ7),
-	GPIO_FN(INTC_IRQ6),
-	GPIO_FN(INTC_IRQ5),
-	GPIO_FN(INTC_IRQ4),
-	GPIO_FN(INTC_IRQ3),
-	GPIO_FN(INTC_IRQ2),
-	GPIO_FN(INTC_IRQ1),
-	GPIO_FN(INTC_IRQ0),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2, GROUP(
-		PTA7_FN, PTA7_OUT, 0, PTA7_IN,
-		PTA6_FN, PTA6_OUT, 0, PTA6_IN,
-		PTA5_FN, PTA5_OUT, 0, PTA5_IN,
-		PTA4_FN, PTA4_OUT, 0, PTA4_IN,
-		PTA3_FN, PTA3_OUT, 0, PTA3_IN,
-		PTA2_FN, PTA2_OUT, 0, PTA2_IN,
-		PTA1_FN, PTA1_OUT, 0, PTA1_IN,
-		PTA0_FN, PTA0_OUT, 0, PTA0_IN ))
-	},
-	{ PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2, GROUP(
-		PTB7_FN, PTB7_OUT, 0, PTB7_IN,
-		PTB6_FN, PTB6_OUT, 0, PTB6_IN,
-		PTB5_FN, PTB5_OUT, 0, PTB5_IN,
-		PTB4_FN, PTB4_OUT, 0, PTB4_IN,
-		PTB3_FN, PTB3_OUT, 0, PTB3_IN,
-		PTB2_FN, PTB2_OUT, 0, PTB2_IN,
-		PTB1_FN, PTB1_OUT, 0, PTB1_IN,
-		PTB0_FN, PTB0_OUT, 0, PTB0_IN ))
-	},
-	{ PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2, GROUP(
-		PTC7_FN, PTC7_OUT, 0, PTC7_IN,
-		PTC6_FN, PTC6_OUT, 0, PTC6_IN,
-		PTC5_FN, PTC5_OUT, 0, PTC5_IN,
-		PTC4_FN, PTC4_OUT, 0, PTC4_IN,
-		PTC3_FN, PTC3_OUT, 0, PTC3_IN,
-		PTC2_FN, PTC2_OUT, 0, PTC2_IN,
-		PTC1_FN, PTC1_OUT, 0, PTC1_IN,
-		PTC0_FN, PTC0_OUT, 0, PTC0_IN ))
-	},
-	{ PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2, GROUP(
-		PTD7_FN, PTD7_OUT, 0, PTD7_IN,
-		PTD6_FN, PTD6_OUT, 0, PTD6_IN,
-		PTD5_FN, PTD5_OUT, 0, PTD5_IN,
-		PTD4_FN, PTD4_OUT, 0, PTD4_IN,
-		PTD3_FN, PTD3_OUT, 0, PTD3_IN,
-		PTD2_FN, PTD2_OUT, 0, PTD2_IN,
-		PTD1_FN, PTD1_OUT, 0, PTD1_IN,
-		PTD0_FN, PTD0_OUT, 0, PTD0_IN ))
-	},
-	{ PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2, GROUP(
-		PTE7_FN, PTE7_OUT, 0, PTE7_IN,
-		PTE6_FN, PTE6_OUT, 0, PTE6_IN,
-		PTE5_FN, PTE5_OUT, 0, PTE5_IN,
-		PTE4_FN, PTE4_OUT, 0, PTE4_IN,
-		PTE3_FN, PTE3_OUT, 0, PTE3_IN,
-		PTE2_FN, PTE2_OUT, 0, PTE2_IN,
-		PTE1_FN, PTE1_OUT, 0, PTE1_IN,
-		PTE0_FN, PTE0_OUT, 0, PTE0_IN ))
-	},
-	{ PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2, GROUP(
-		PTF7_FN, PTF7_OUT, 0, PTF7_IN,
-		PTF6_FN, PTF6_OUT, 0, PTF6_IN,
-		PTF5_FN, PTF5_OUT, 0, PTF5_IN,
-		PTF4_FN, PTF4_OUT, 0, PTF4_IN,
-		PTF3_FN, PTF3_OUT, 0, PTF3_IN,
-		PTF2_FN, PTF2_OUT, 0, PTF2_IN,
-		PTF1_FN, PTF1_OUT, 0, PTF1_IN,
-		PTF0_FN, PTF0_OUT, 0, PTF0_IN ))
-	},
-	{ PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PTG5_FN, PTG5_OUT, 0, 0,
-		PTG4_FN, PTG4_OUT, 0, 0,
-		PTG3_FN, PTG3_OUT, 0, 0,
-		PTG2_FN, PTG2_OUT, 0, 0,
-		PTG1_FN, PTG1_OUT, 0, 0,
-		PTG0_FN, PTG0_OUT, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2, GROUP(
-		PTH7_FN, PTH7_OUT, 0, PTH7_IN,
-		PTH6_FN, PTH6_OUT, 0, PTH6_IN,
-		PTH5_FN, PTH5_OUT, 0, PTH5_IN,
-		PTH4_FN, PTH4_OUT, 0, PTH4_IN,
-		PTH3_FN, PTH3_OUT, 0, PTH3_IN,
-		PTH2_FN, PTH2_OUT, 0, PTH2_IN,
-		PTH1_FN, PTH1_OUT, 0, PTH1_IN,
-		PTH0_FN, PTH0_OUT, 0, PTH0_IN ))
-	},
-	{ PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2, GROUP(
-		PTJ7_FN, PTJ7_OUT, 0, 0,
-		PTJ6_FN, PTJ6_OUT, 0, 0,
-		PTJ5_FN, PTJ5_OUT, 0, 0,
-		0, 0, 0, 0,
-		PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN,
-		PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN,
-		PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN,
-		PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN ))
-	},
-	{ PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2, GROUP(
-		PTK7_FN, PTK7_OUT, 0, PTK7_IN,
-		PTK6_FN, PTK6_OUT, 0, PTK6_IN,
-		PTK5_FN, PTK5_OUT, 0, PTK5_IN,
-		PTK4_FN, PTK4_OUT, 0, PTK4_IN,
-		PTK3_FN, PTK3_OUT, 0, PTK3_IN,
-		PTK2_FN, PTK2_OUT, 0, PTK2_IN,
-		PTK1_FN, PTK1_OUT, 0, PTK1_IN,
-		PTK0_FN, PTK0_OUT, 0, PTK0_IN ))
-	},
-	{ PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2, GROUP(
-		PTL7_FN, PTL7_OUT, 0, PTL7_IN,
-		PTL6_FN, PTL6_OUT, 0, PTL6_IN,
-		PTL5_FN, PTL5_OUT, 0, PTL5_IN,
-		PTL4_FN, PTL4_OUT, 0, PTL4_IN,
-		PTL3_FN, PTL3_OUT, 0, PTL3_IN,
-		PTL2_FN, PTL2_OUT, 0, PTL2_IN,
-		PTL1_FN, PTL1_OUT, 0, PTL1_IN,
-		PTL0_FN, PTL0_OUT, 0, PTL0_IN ))
-	},
-	{ PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2, GROUP(
-		PTM7_FN, PTM7_OUT, 0, PTM7_IN,
-		PTM6_FN, PTM6_OUT, 0, PTM6_IN,
-		PTM5_FN, PTM5_OUT, 0, PTM5_IN,
-		PTM4_FN, PTM4_OUT, 0, PTM4_IN,
-		PTM3_FN, PTM3_OUT, 0, PTM3_IN,
-		PTM2_FN, PTM2_OUT, 0, PTM2_IN,
-		PTM1_FN, PTM1_OUT, 0, PTM1_IN,
-		PTM0_FN, PTM0_OUT, 0, PTM0_IN ))
-	},
-	{ PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2, GROUP(
-		PTN7_FN, PTN7_OUT, 0, PTN7_IN,
-		PTN6_FN, PTN6_OUT, 0, PTN6_IN,
-		PTN5_FN, PTN5_OUT, 0, PTN5_IN,
-		PTN4_FN, PTN4_OUT, 0, PTN4_IN,
-		PTN3_FN, PTN3_OUT, 0, PTN3_IN,
-		PTN2_FN, PTN2_OUT, 0, PTN2_IN,
-		PTN1_FN, PTN1_OUT, 0, PTN1_IN,
-		PTN0_FN, PTN0_OUT, 0, PTN0_IN ))
-	},
-	{ PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2, GROUP(
-		PTQ7_FN, PTQ7_OUT, 0, PTQ7_IN,
-		PTQ6_FN, PTQ6_OUT, 0, PTQ6_IN,
-		PTQ5_FN, PTQ5_OUT, 0, PTQ5_IN,
-		PTQ4_FN, PTQ4_OUT, 0, PTQ4_IN,
-		PTQ3_FN, PTQ3_OUT, 0, PTQ3_IN,
-		PTQ2_FN, PTQ2_OUT, 0, PTQ2_IN,
-		PTQ1_FN, PTQ1_OUT, 0, PTQ1_IN,
-		PTQ0_FN, PTQ0_OUT, 0, PTQ0_IN ))
-	},
-	{ PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2, GROUP(
-		PTR7_FN, PTR7_OUT, 0, PTR7_IN,
-		PTR6_FN, PTR6_OUT, 0, PTR6_IN,
-		PTR5_FN, PTR5_OUT, 0, PTR5_IN,
-		PTR4_FN, PTR4_OUT, 0, PTR4_IN,
-		PTR3_FN, 0,        0, PTR3_IN,
-		PTR2_FN, 0,        0, PTR2_IN,
-		PTR1_FN, PTR1_OUT, 0, PTR1_IN,
-		PTR0_FN, PTR0_OUT, 0, PTR0_IN ))
-	},
-	{ PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2, GROUP(
-		0, 0, 0, 0,
-		PTS6_FN, PTS6_OUT, 0, PTS6_IN,
-		PTS5_FN, PTS5_OUT, 0, PTS5_IN,
-		PTS4_FN, PTS4_OUT, 0, PTS4_IN,
-		PTS3_FN, PTS3_OUT, 0, PTS3_IN,
-		PTS2_FN, PTS2_OUT, 0, PTS2_IN,
-		PTS1_FN, PTS1_OUT, 0, PTS1_IN,
-		PTS0_FN, PTS0_OUT, 0, PTS0_IN ))
-	},
-	{ PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2, GROUP(
-		PTT7_FN, PTT7_OUT, 0, PTT7_IN,
-		PTT6_FN, PTT6_OUT, 0, PTT6_IN,
-		PTT5_FN, PTT5_OUT, 0, PTT5_IN,
-		PTT4_FN, PTT4_OUT, 0, PTT4_IN,
-		PTT3_FN, PTT3_OUT, 0, PTT3_IN,
-		PTT2_FN, PTT2_OUT, 0, PTT2_IN,
-		PTT1_FN, PTT1_OUT, 0, PTT1_IN,
-		PTT0_FN, PTT0_OUT, 0, PTT0_IN ))
-	},
-	{ PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2, GROUP(
-		PTU7_FN, PTU7_OUT, 0, PTU7_IN,
-		PTU6_FN, PTU6_OUT, 0, PTU6_IN,
-		PTU5_FN, PTU5_OUT, 0, PTU5_IN,
-		PTU4_FN, PTU4_OUT, 0, PTU4_IN,
-		PTU3_FN, PTU3_OUT, 0, PTU3_IN,
-		PTU2_FN, PTU2_OUT, 0, PTU2_IN,
-		PTU1_FN, PTU1_OUT, 0, PTU1_IN,
-		PTU0_FN, PTU0_OUT, 0, PTU0_IN ))
-	},
-	{ PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2, GROUP(
-		PTV7_FN, PTV7_OUT, 0, PTV7_IN,
-		PTV6_FN, PTV6_OUT, 0, PTV6_IN,
-		PTV5_FN, PTV5_OUT, 0, PTV5_IN,
-		PTV4_FN, PTV4_OUT, 0, PTV4_IN,
-		PTV3_FN, PTV3_OUT, 0, PTV3_IN,
-		PTV2_FN, PTV2_OUT, 0, PTV2_IN,
-		PTV1_FN, PTV1_OUT, 0, PTV1_IN,
-		PTV0_FN, PTV0_OUT, 0, PTV0_IN ))
-	},
-	{ PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2, GROUP(
-		PTW7_FN, PTW7_OUT, 0, PTW7_IN,
-		PTW6_FN, PTW6_OUT, 0, PTW6_IN,
-		PTW5_FN, PTW5_OUT, 0, PTW5_IN,
-		PTW4_FN, PTW4_OUT, 0, PTW4_IN,
-		PTW3_FN, PTW3_OUT, 0, PTW3_IN,
-		PTW2_FN, PTW2_OUT, 0, PTW2_IN,
-		PTW1_FN, PTW1_OUT, 0, PTW1_IN,
-		PTW0_FN, PTW0_OUT, 0, PTW0_IN ))
-	},
-	{ PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2, GROUP(
-		PTX7_FN, PTX7_OUT, 0, PTX7_IN,
-		PTX6_FN, PTX6_OUT, 0, PTX6_IN,
-		PTX5_FN, PTX5_OUT, 0, PTX5_IN,
-		PTX4_FN, PTX4_OUT, 0, PTX4_IN,
-		PTX3_FN, PTX3_OUT, 0, PTX3_IN,
-		PTX2_FN, PTX2_OUT, 0, PTX2_IN,
-		PTX1_FN, PTX1_OUT, 0, PTX1_IN,
-		PTX0_FN, PTX0_OUT, 0, PTX0_IN ))
-	},
-	{ PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2, GROUP(
-		PTY7_FN, PTY7_OUT, 0, PTY7_IN,
-		PTY6_FN, PTY6_OUT, 0, PTY6_IN,
-		PTY5_FN, PTY5_OUT, 0, PTY5_IN,
-		PTY4_FN, PTY4_OUT, 0, PTY4_IN,
-		PTY3_FN, PTY3_OUT, 0, PTY3_IN,
-		PTY2_FN, PTY2_OUT, 0, PTY2_IN,
-		PTY1_FN, PTY1_OUT, 0, PTY1_IN,
-		PTY0_FN, PTY0_OUT, 0, PTY0_IN ))
-	},
-	{ PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2, GROUP(
-		PTZ7_FN, PTZ7_OUT, 0, PTZ7_IN,
-		PTZ6_FN, PTZ6_OUT, 0, PTZ6_IN,
-		PTZ5_FN, PTZ5_OUT, 0, PTZ5_IN,
-		PTZ4_FN, PTZ4_OUT, 0, PTZ4_IN,
-		PTZ3_FN, PTZ3_OUT, 0, PTZ3_IN,
-		PTZ2_FN, PTZ2_OUT, 0, PTZ2_IN,
-		PTZ1_FN, PTZ1_OUT, 0, PTZ1_IN,
-		PTZ0_FN, PTZ0_OUT, 0, PTZ0_IN ))
-	},
-	{ PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1, GROUP(
-		PSA15_0, PSA15_1,
-		PSA14_0, PSA14_1,
-		PSA13_0, PSA13_1,
-		PSA12_0, PSA12_1,
-		0, 0,
-		PSA10_0, PSA10_1,
-		PSA9_0,  PSA9_1,
-		PSA8_0,  PSA8_1,
-		PSA7_0,  PSA7_1,
-		PSA6_0,  PSA6_1,
-		PSA5_0,  PSA5_1,
-		0, 0,
-		PSA3_0,  PSA3_1,
-		PSA2_0,  PSA2_1,
-		PSA1_0,  PSA1_1,
-		PSA0_0,  PSA0_1))
-	},
-	{ PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1, GROUP(
-		0, 0,
-		PSB14_0, PSB14_1,
-		PSB13_0, PSB13_1,
-		PSB12_0, PSB12_1,
-		PSB11_0, PSB11_1,
-		PSB10_0, PSB10_1,
-		PSB9_0,  PSB9_1,
-		PSB8_0,  PSB8_1,
-		PSB7_0,  PSB7_1,
-		PSB6_0,  PSB6_1,
-		PSB5_0,  PSB5_1,
-		PSB4_0,  PSB4_1,
-		PSB3_0,  PSB3_1,
-		PSB2_0,  PSB2_1,
-		PSB1_0,  PSB1_1,
-		PSB0_0,  PSB0_1))
-	},
-	{ PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1, GROUP(
-		PSC15_0, PSC15_1,
-		PSC14_0, PSC14_1,
-		PSC13_0, PSC13_1,
-		PSC12_0, PSC12_1,
-		PSC11_0, PSC11_1,
-		PSC10_0, PSC10_1,
-		PSC9_0,  PSC9_1,
-		PSC8_0,  PSC8_1,
-		PSC7_0,  PSC7_1,
-		PSC6_0,  PSC6_1,
-		PSC5_0,  PSC5_1,
-		PSC4_0,  PSC4_1,
-		0, 0,
-		PSC2_0,  PSC2_1,
-		PSC1_0,  PSC1_1,
-		PSC0_0,  PSC0_1))
-	},
-	{ PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1, GROUP(
-		PSD15_0, PSD15_1,
-		PSD14_0, PSD14_1,
-		PSD13_0, PSD13_1,
-		PSD12_0, PSD12_1,
-		PSD11_0, PSD11_1,
-		PSD10_0, PSD10_1,
-		PSD9_0,  PSD9_1,
-		PSD8_0,  PSD8_1,
-		PSD7_0,  PSD7_1,
-		PSD6_0,  PSD6_1,
-		PSD5_0,  PSD5_1,
-		PSD4_0,  PSD4_1,
-		PSD3_0,  PSD3_1,
-		PSD2_0,  PSD2_1,
-		PSD1_0,  PSD1_1,
-		PSD0_0,  PSD0_1))
-	},
-	{ PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1, GROUP(
-		PSE15_0, PSE15_1,
-		PSE14_0, PSE14_1,
-		PSE13_0, PSE13_1,
-		PSE12_0, PSE12_1,
-		PSE11_0, PSE11_1,
-		PSE10_0, PSE10_1,
-		PSE9_0,  PSE9_1,
-		PSE8_0,  PSE8_1,
-		PSE7_0,  PSE7_1,
-		PSE6_0,  PSE6_1,
-		PSE5_0,  PSE5_1,
-		PSE4_0,  PSE4_1,
-		PSE3_0,  PSE3_1,
-		PSE2_0,  PSE2_1,
-		PSE1_0,  PSE1_1,
-		PSE0_0,  PSE0_1))
-	},
-	{}
-};
-
-static const struct pinmux_data_reg pinmux_data_regs[] = {
-	{ PINMUX_DATA_REG("PADR", 0xa4050120, 8, GROUP(
-		PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
-		PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PBDR", 0xa4050122, 8, GROUP(
-		PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
-		PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PCDR", 0xa4050124, 8, GROUP(
-		PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
-		PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PDDR", 0xa4050126, 8, GROUP(
-		PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
-		PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PEDR", 0xa4050128, 8, GROUP(
-		PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
-		PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PFDR", 0xa405012a, 8, GROUP(
-		PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
-		PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PGDR", 0xa405012c, 8, GROUP(
-		0,         0,         PTG5_DATA, PTG4_DATA,
-		PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PHDR", 0xa405012e, 8, GROUP(
-		PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
-		PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PJDR", 0xa4050130, 8, GROUP(
-		PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, 0,
-		PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PKDR", 0xa4050132, 8, GROUP(
-		PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
-		PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PLDR", 0xa4050134, 8, GROUP(
-		PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
-		PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PMDR", 0xa4050136, 8, GROUP(
-		PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
-		PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PNDR", 0xa4050138, 8, GROUP(
-		PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
-		PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PQDR", 0xa405013a, 8, GROUP(
-		PTQ7_DATA, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
-		PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PRDR", 0xa405013c, 8, GROUP(
-		PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
-		PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PSDR", 0xa405013e, 8, GROUP(
-		0,         PTS6_DATA, PTS5_DATA, PTS4_DATA,
-		PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PTDR", 0xa4050160, 8, GROUP(
-		PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
-		PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PUDR", 0xa4050162, 8, GROUP(
-		PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
-		PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PVDR", 0xa4050164, 8, GROUP(
-		PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
-		PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PWDR", 0xa4050166, 8, GROUP(
-		PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
-		PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PXDR", 0xa4050168, 8, GROUP(
-		PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
-		PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PYDR", 0xa405016a, 8, GROUP(
-		PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
-		PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PZDR", 0xa405016c, 8, GROUP(
-		PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
-		PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
-	},
-	{ },
-};
-
-const struct sh_pfc_soc_info sh7724_pinmux_info = {
-	.name = "sh7724_pfc",
-	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.func_gpios = pinmux_func_gpios,
-	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
-	.cfg_regs = pinmux_config_regs,
-	.data_regs = pinmux_data_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
deleted file mode 100644
index dbc36079c381..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c
+++ /dev/null
@@ -1,2462 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * SH7734 processor support - PFC hardware block
- *
- * Copyright (C) 2012  Renesas Solutions Corp.
- * Copyright (C) 2012  Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <cpu/sh7734.h>
-
-#include "sh_pfc.h"
-
-#define CPU_ALL_GP(fn, sfx)						\
-	PORT_GP_32(0, fn, sfx),						\
-	PORT_GP_32(1, fn, sfx),						\
-	PORT_GP_32(2, fn, sfx),						\
-	PORT_GP_32(3, fn, sfx),						\
-	PORT_GP_32(4, fn, sfx),						\
-	PORT_GP_12(5, fn, sfx)
-
-#undef _GP_DATA
-#define _GP_DATA(bank, pin, name, sfx, cfg)				\
-	PINMUX_DATA(name##_DATA, name##_FN, name##_IN, name##_OUT)
-
-#define _GP_INOUTSEL(bank, pin, name, sfx, cfg)	name##_IN, name##_OUT
-#define _GP_INDT(bank, pin, name, sfx, cfg)	name##_DATA
-#define GP_INOUTSEL(bank)	PORT_GP_32_REV(bank, _GP_INOUTSEL, unused)
-#define GP_INDT(bank)		PORT_GP_32_REV(bank, _GP_INDT, unused)
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	GP_ALL(DATA), /* GP_0_0_DATA -> GP_5_11_DATA */
-	PINMUX_DATA_END,
-
-	PINMUX_INPUT_BEGIN,
-	GP_ALL(IN), /* GP_0_0_IN -> GP_5_11_IN */
-	PINMUX_INPUT_END,
-
-	PINMUX_OUTPUT_BEGIN,
-	GP_ALL(OUT), /* GP_0_0_OUT -> GP_5_11_OUT */
-	PINMUX_OUTPUT_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	GP_ALL(FN), /* GP_0_0_FN -> GP_5_11_FN */
-
-	/* GPSR0 */
-	FN_IP1_9_8, FN_IP1_11_10, FN_IP1_13_12, FN_IP1_15_14,
-	FN_IP0_7_6, FN_IP0_9_8, FN_IP0_11_10, FN_IP0_13_12,
-	FN_IP0_15_14, FN_IP0_17_16, FN_IP0_19_18, FN_IP0_21_20,
-	FN_IP0_23_22, FN_IP0_25_24, FN_IP0_27_26, FN_IP0_29_28,
-	FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4,
-	FN_IP1_7_6, FN_IP11_28, FN_IP0_1_0, FN_IP0_3_2,
-	FN_IP0_5_4, FN_IP1_17_16, FN_IP1_19_18, FN_IP1_22_20,
-	FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0,
-
-	/* GPSR1 */
-	FN_IP3_20, FN_IP3_29_27, FN_IP11_20_19, FN_IP11_22_21,
-	FN_IP2_16_14, FN_IP2_19_17, FN_IP2_22_20, FN_IP2_24_23,
-	FN_IP2_27_25, FN_IP2_30_28, FN_IP3_1_0, FN_CLKOUT,
-	FN_BS, FN_CS0, FN_IP3_2, FN_EX_CS0,
-	FN_IP3_5_3, FN_IP3_8_6, FN_IP3_11_9, FN_IP3_14_12,
-	FN_IP3_17_15, FN_RD, FN_IP3_19_18, FN_WE0,
-	FN_WE1, FN_IP2_4_3, FN_IP3_23_21, FN_IP3_26_24,
-	FN_IP2_7_5, FN_IP2_10_8, FN_IP2_13_11, FN_IP11_25_23,
-
-	/* GPSR2 */
-	FN_IP11_6_4, FN_IP11_9_7, FN_IP11_11_10, FN_IP4_2_0,
-	FN_IP8_29_28, FN_IP11_27_26, FN_IP8_22_20, FN_IP8_25_23,
-	FN_IP11_12, FN_IP8_27_26, FN_IP4_5_3, FN_IP4_8_6,
-	FN_IP4_11_9, FN_IP4_14_12, FN_IP4_17_15, FN_IP4_19_18,
-	FN_IP4_21_20, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
-	FN_IP4_29_28, FN_IP4_31_30, FN_IP5_2_0, FN_IP5_5_3,
-	FN_IP5_8_6, FN_IP5_11_9, FN_IP5_14_12, FN_IP5_17_15,
-	FN_IP5_20_18, FN_IP5_22_21, FN_IP5_24_23, FN_IP5_26_25,
-
-	/* GPSR3 */
-	FN_IP6_2_0, FN_IP6_5_3, FN_IP6_7_6, FN_IP6_9_8,
-	FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_17_16,
-	FN_IP6_20_18, FN_IP6_23_21, FN_IP7_2_0, FN_IP7_5_3,
-	FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15,
-	FN_IP7_20_18, FN_IP7_23_21, FN_IP7_26_24, FN_IP7_28_27,
-	FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
-	FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12,
-	FN_IP8_15_14, FN_IP8_17_16, FN_IP8_19_18, FN_IP9_1_0,
-
-	/* GPSR4 */
-	FN_IP9_19_18, FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24,
-	FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14, FN_IP9_17_16,
-	FN_IP9_3_2, FN_IP9_5_4, FN_IP9_7_6, FN_IP9_9_8,
-	FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
-	FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_15,
-	FN_IP10_18_16, FN_IP10_21_19, FN_IP11_0, FN_IP11_1,
-	FN_SCL0, FN_IP11_2, FN_PENC0, FN_IP11_15_13, /* Need check*/
-	FN_USB_OVC0, FN_IP11_18_16,
-	FN_IP10_22, FN_IP10_24_23,
-
-	/* GPSR5 */
-	FN_IP10_25, FN_IP11_3, FN_IRQ2_B, FN_IRQ3_B,
-	FN_IP10_27_26, /* 10 */
-	FN_IP10_29_28, /* 11 */
-
-	/* IPSR0 */
-	FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A, FN_TIOC3D_C,
-	FN_A14, FN_LCD_DATA14_A, FN_TIOC3C_C,
-	FN_A13, FN_LCD_DATA13_A, FN_TIOC3B_C,
-	FN_A12, FN_LCD_DATA12_A, FN_TIOC3A_C,
-	FN_A11, FN_ST0_D7, FN_LCD_DATA11_A, FN_TIOC2B_C,
-	FN_A10, FN_ST0_D6, FN_LCD_DATA10_A, FN_TIOC2A_C,
-	FN_A9, FN_ST0_D5, FN_LCD_DATA9_A, FN_TIOC1B_C,
-	FN_A8, FN_ST0_D4, FN_LCD_DATA8_A, FN_TIOC1A_C,
-	FN_A7, FN_ST0_D3, FN_LCD_DATA7_A, FN_TIOC0D_C,
-	FN_A6, FN_ST0_D2, FN_LCD_DATA6_A, FN_TIOC0C_C,
-	FN_A5, FN_ST0_D1, FN_LCD_DATA5_A, FN_TIOC0B_C,
-	FN_A4, FN_ST0_D0, FN_LCD_DATA4_A, FN_TIOC0A_C,
-	FN_A3, FN_ST0_VLD, FN_LCD_DATA3_A, FN_TCLKD_C,
-	FN_A2, FN_ST0_SYC, FN_LCD_DATA2_A, FN_TCLKC_C,
-	FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C,
-	FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C,
-
-	/* IPSR1 */
-	FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6, FN_FD3_A,
-	FN_D2, FN_SD0_DAT2_A, FN_MMC_D2_A, FN_ST1_D5, FN_FD2_A,
-	FN_D1, FN_SD0_DAT1_A, FN_MMC_D1_A, FN_ST1_D4, FN_FD1_A,
-	FN_D0, FN_SD0_DAT0_A, FN_MMC_D0_A, FN_ST1_D3, FN_FD0_A,
-	FN_A25, FN_TX2_D, FN_ST1_D2,
-	FN_A24, FN_RX2_D, FN_ST1_D1,
-	FN_A23, FN_ST1_D0, FN_LCD_M_DISP_A,
-	FN_A22, FN_ST1_VLD, FN_LCD_VEPWC_A,
-	FN_A21, FN_ST1_SYC, FN_LCD_VCPWC_A,
-	FN_A20, FN_ST1_REQ, FN_LCD_FLM_A,
-	FN_A19, FN_ST1_CLKIN, FN_LCD_CLK_A,	FN_TIOC4D_C,
-	FN_A18, FN_ST1_PWM, FN_LCD_CL2_A, FN_TIOC4C_C,
-	FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A,	FN_TIOC4B_C,
-	FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C,
-
-	/* IPSR2 */
-	FN_D14, FN_TX2_B, FN_FSE_A, FN_ET0_TX_CLK_B,
-	FN_D13, FN_RX2_B, FN_FRB_A,	FN_ET0_ETXD6_B,
-	FN_D12, FN_FWE_A, FN_ET0_ETXD5_B,
-	FN_D11, FN_RSPI_MISO_A, FN_QMI_QIO1_A, FN_FRE_A,
-		FN_ET0_ETXD3_B,
-	FN_D10, FN_RSPI_MOSI_A, FN_QMO_QIO0_A, FN_FALE_A,
-		FN_ET0_ETXD2_B,
-	FN_D9, FN_SD0_CMD_A, FN_MMC_CMD_A, FN_QIO3_A, FN_FCLE_A,
-		FN_ET0_ETXD1_B,
-	FN_D8, FN_SD0_CLK_A, FN_MMC_CLK_A, FN_QIO2_A, FN_FCE_A,
-		FN_ET0_GTX_CLK_B,
-	FN_D7, FN_RSPI_SSL_A, FN_MMC_D7_A, FN_QSSL_A, FN_FD7_A,
-	FN_D6, FN_RSPI_RSPCK_A, FN_MMC_D6_A, FN_QSPCLK_A, FN_FD6_A,
-	FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A,
-	FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7, FN_FD4_A,
-
-	/* IPSR3 */
-	FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A, FN_ET0_ETXD7,
-	FN_EX_WAIT2, FN_SD1_DAT1_A, FN_DACK2, FN_CAN1_RX_C,
-		FN_ET0_MAGIC_C, FN_ET0_ETXD6_A,
-	FN_EX_WAIT1, FN_SD1_DAT0_A, FN_DREQ2, FN_CAN1_TX_C,
-		FN_ET0_LINK_C, FN_ET0_ETXD5_A,
-	FN_EX_WAIT0, FN_TCLK1_B,
-	FN_RD_WR, FN_TCLK0, FN_CAN_CLK_B, FN_ET0_ETXD4,
-	FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B, FN_ET0_ETXD3_A,
-	FN_EX_CS4, FN_SD1_WP_A, FN_ATAWR, FN_QMI_QIO1_B, FN_ET0_ETXD2_A,
-	FN_EX_CS3, FN_SD1_CD_A, FN_ATARD, FN_QMO_QIO0_B, FN_ET0_ETXD1_A,
-	FN_EX_CS2, FN_TX3_B, FN_ATACS1, FN_QSPCLK_B, FN_ET0_GTX_CLK_A,
-	FN_EX_CS1, FN_RX3_B, FN_ATACS0, FN_QIO2_B, FN_ET0_ETXD0,
-	FN_CS1_A26, FN_QIO3_B,
-	FN_D15, FN_SCK2_B,
-
-	/* IPSR4 */
-	FN_SCK2_A, FN_VI0_G3,
-	FN_RTS1_B, FN_VI0_G2,
-	FN_CTS1_B, FN_VI0_DATA7_VI0_G1,
-	FN_TX1_B, FN_VI0_DATA6_VI0_G0, FN_ET0_PHY_INT_A,
-	FN_RX1_B, FN_VI0_DATA5_VI0_B5, FN_ET0_MAGIC_A,
-	FN_SCK1_B, FN_VI0_DATA4_VI0_B4, FN_ET0_LINK_A,
-	FN_RTS0_B, FN_VI0_DATA3_VI0_B3, FN_ET0_MDIO_A,
-	FN_CTS0_B, FN_VI0_DATA2_VI0_B2, FN_RMII0_MDIO_A, FN_ET0_MDC,
-	FN_HTX0_A, FN_TX1_A, FN_VI0_DATA1_VI0_B1, FN_RMII0_MDC_A, FN_ET0_COL,
-	FN_HRX0_A, FN_RX1_A, FN_VI0_DATA0_VI0_B0, FN_RMII0_CRS_DV_A, FN_ET0_CRS,
-	FN_HSCK0_A, FN_SCK1_A, FN_VI0_VSYNC, FN_RMII0_RX_ER_A, FN_ET0_RX_ER,
-	FN_HRTS0_A, FN_RTS1_A, FN_VI0_HSYNC, FN_RMII0_TXD_EN_A, FN_ET0_RX_DV,
-	FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A, FN_ET0_ERXD7,
-
-	/* IPSR5 */
-	FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, FN_ET0_RX_CLK_B,
-	FN_SD2_CMD_A, FN_TX2_A, FN_VI0_G5, FN_ET0_ERXD2_B,
-	FN_SD2_DAT0_A, FN_RX3_A, FN_VI0_R0, FN_ET0_ERXD3_B,
-	FN_SD2_DAT1_A, FN_TX3_A, FN_VI0_R1, FN_ET0_MDIO_B,
-	FN_SD2_DAT2_A, FN_RX4_A, FN_VI0_R2, FN_ET0_LINK_B,
-	FN_SD2_DAT3_A, FN_TX4_A, FN_VI0_R3, FN_ET0_MAGIC_B,
-	FN_SD2_CD_A, FN_RX5_A, FN_VI0_R4, FN_ET0_PHY_INT_B,
-	FN_SD2_WP_A, FN_TX5_A, FN_VI0_R5,
-	FN_REF125CK, FN_ADTRG, FN_RX5_C,
-	FN_REF50CK, FN_CTS1_E, FN_HCTS0_D,
-
-	/* IPSR6 */
-	FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A, FN_TCLKA_A, FN_HIFD00,
-	FN_DU0_DR1, FN_SCK0_B, FN_HTX0_D, FN_IERX_A, FN_TCLKB_A, FN_HIFD01,
-	FN_DU0_DR2, FN_RX0_B, FN_TCLKC_A, FN_HIFD02,
-	FN_DU0_DR3, FN_TX0_B, FN_TCLKD_A, FN_HIFD03,
-	FN_DU0_DR4, FN_CTS0_C, FN_TIOC0A_A, FN_HIFD04,
-	FN_DU0_DR5, FN_RTS0_C, FN_TIOC0B_A, FN_HIFD05,
-	FN_DU0_DR6, FN_SCK1_C, FN_TIOC0C_A, FN_HIFD06,
-	FN_DU0_DR7, FN_RX1_C, FN_TIOC0D_A, FN_HIFD07,
-	FN_DU0_DG0, FN_TX1_C, FN_HSCK0_D, FN_IECLK_A, FN_TIOC1A_A, FN_HIFD08,
-	FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A, FN_HIFD09,
-
-	/* IPSR7 */
-	FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A, FN_HIFD10,
-	FN_DU0_DG3, FN_SCK2_C, FN_RMII0_MDIO_B, FN_TIOC2B_A, FN_HIFD11,
-	FN_DU0_DG4, FN_RX2_C, FN_RMII0_CRS_DV_B, FN_TIOC3A_A, FN_HIFD12,
-	FN_DU0_DG5, FN_TX2_C, FN_RMII0_RX_ER_B, FN_TIOC3B_A, FN_HIFD13,
-	FN_DU0_DG6, FN_RX3_C, FN_RMII0_RXD0_B, FN_TIOC3C_A, FN_HIFD14,
-	FN_DU0_DG7, FN_TX3_C, FN_RMII0_RXD1_B, FN_TIOC3D_A, FN_HIFD15,
-	FN_DU0_DB0, FN_RX4_C, FN_RMII0_TXD_EN_B, FN_TIOC4A_A, FN_HIFCS,
-	FN_DU0_DB1, FN_TX4_C, FN_RMII0_TXD0_B, FN_TIOC4B_A, FN_HIFRS,
-	FN_DU0_DB2, FN_RX5_B, FN_RMII0_TXD1_B, FN_TIOC4C_A, FN_HIFWR,
-	FN_DU0_DB3, FN_TX5_B, FN_TIOC4D_A, FN_HIFRD,
-	FN_DU0_DB4, FN_HIFINT,
-
-	/* IPSR8 */
-	FN_DU0_DB5, FN_HIFDREQ,
-	FN_DU0_DB6, FN_HIFRDY,
-	FN_DU0_DB7, FN_SSI_SCK0_B, FN_HIFEBL_B,
-	FN_DU0_DOTCLKIN, FN_HSPI_CS0_C, FN_SSI_WS0_B,
-	FN_DU0_DOTCLKOUT, FN_HSPI_CLK0_C, FN_SSI_SDATA0_B,
-	FN_DU0_EXHSYNC_DU0_HSYNC, FN_HSPI_TX0_C, FN_SSI_SCK1_B,
-	FN_DU0_EXVSYNC_DU0_VSYNC, FN_HSPI_RX0_C, FN_SSI_WS1_B,
-	FN_DU0_EXODDF_DU0_ODDF, FN_CAN0_RX_B, FN_HSCK0_B, FN_SSI_SDATA1_B,
-	FN_DU0_DISP, FN_CAN0_TX_B, FN_HRX0_B, FN_AUDIO_CLKA_B,
-	FN_DU0_CDE, FN_HTX0_B, FN_AUDIO_CLKB_B, FN_LCD_VCPWC_B,
-	FN_IRQ0_A, FN_HSPI_TX_B, FN_RX3_E, FN_ET0_ERXD0,
-	FN_IRQ1_A, FN_HSPI_RX_B, FN_TX3_E, FN_ET0_ERXD1,
-	FN_IRQ2_A, FN_CTS0_A, FN_HCTS0_B, FN_ET0_ERXD2_A,
-	FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A,
-
-	/* IPSR9 */
-	FN_VI1_CLK_A, FN_FD0_B, FN_LCD_DATA0_B,
-	FN_VI1_0_A, FN_FD1_B, FN_LCD_DATA1_B,
-	FN_VI1_1_A, FN_FD2_B, FN_LCD_DATA2_B,
-	FN_VI1_2_A, FN_FD3_B, FN_LCD_DATA3_B,
-	FN_VI1_3_A, FN_FD4_B, FN_LCD_DATA4_B,
-	FN_VI1_4_A, FN_FD5_B, FN_LCD_DATA5_B,
-	FN_VI1_5_A, FN_FD6_B, FN_LCD_DATA6_B,
-	FN_VI1_6_A, FN_FD7_B, FN_LCD_DATA7_B,
-	FN_VI1_7_A, FN_FCE_B, FN_LCD_DATA8_B,
-	FN_SSI_SCK0_A, FN_TIOC1A_B, FN_LCD_DATA9_B,
-	FN_SSI_WS0_A, FN_TIOC1B_B, FN_LCD_DATA10_B,
-	FN_SSI_SDATA0_A, FN_VI1_0_B, FN_TIOC2A_B, FN_LCD_DATA11_B,
-	FN_SSI_SCK1_A, FN_VI1_1_B, FN_TIOC2B_B, FN_LCD_DATA12_B,
-	FN_SSI_WS1_A, FN_VI1_2_B, FN_LCD_DATA13_B,
-	FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B,
-
-	/* IPSR10 */
-	FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B, FN_LCD_DATA15_B,
-	FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B, FN_LCD_DON_B,
-	FN_SSI_SDATA2, FN_VI1_6_B, FN_HRX0_C, FN_FRE_B, FN_LCD_CL1_B,
-	FN_SSI_SDATA3, FN_VI1_7_B, FN_HTX0_C, FN_FWE_B, FN_LCD_CL2_B,
-	FN_AUDIO_CLKA_A, FN_VI1_CLK_B, FN_SCK1_D, FN_IECLK_B, FN_LCD_FLM_B,
-	FN_AUDIO_CLKB_A, FN_LCD_CLK_B,
-	FN_AUDIO_CLKC, FN_SCK1_E, FN_HCTS0_C, FN_FRB_B, FN_LCD_VEPWC_B,
-	FN_AUDIO_CLKOUT, FN_TX1_E, FN_HRTS0_C, FN_FSE_B, FN_LCD_M_DISP_B,
-	FN_CAN_CLK_A, FN_RX4_D,
-	FN_CAN0_TX_A, FN_TX4_D, FN_MLB_CLK,
-	FN_CAN1_RX_A, FN_IRQ1_B,
-	FN_CAN0_RX_A, FN_IRQ0_B, FN_MLB_SIG,
-	FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT,
-
-	/* IPSR11 */
-	FN_SCL1, FN_SCIF_CLK_C,
-	FN_SDA1, FN_RX1_E,
-	FN_SDA0, FN_HIFEBL_A,
-	FN_SDSELF, FN_RTS1_E,
-	FN_SCIF_CLK_A, FN_HSPI_CLK_A, FN_VI0_CLK, FN_RMII0_TXD0_A, FN_ET0_ERXD4,
-	FN_SCK0_A, FN_HSPI_CS_A, FN_VI0_CLKENB, FN_RMII0_TXD1_A, FN_ET0_ERXD5,
-	FN_RX0_A, FN_HSPI_RX_A, FN_RMII0_RXD0_A, FN_ET0_ERXD6,
-	FN_TX0_A, FN_HSPI_TX_A,
-	FN_PENC1, FN_TX3_D, FN_CAN1_TX_B, FN_TX5_D, FN_IETX_B,
-	FN_USB_OVC1, FN_RX3_D, FN_CAN1_RX_B, FN_RX5_D, FN_IERX_B,
-	FN_DREQ0, FN_SD1_CLK_A, FN_ET0_TX_EN,
-	FN_DACK0, FN_SD1_DAT3_A, FN_ET0_TX_ER,
-	FN_DREQ1, FN_HSPI_CLK_B, FN_RX4_B, FN_ET0_PHY_INT_C, FN_ET0_TX_CLK_A,
-	FN_DACK1, FN_HSPI_CS_B, FN_TX4_B, FN_ET0_RX_CLK_A,
-	FN_PRESETOUT, FN_ST_CLKOUT,
-
-	/* MOD_SEL1 */
-	FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
-	FN_SEL_RQSPI_0, FN_SEL_RQSPI_1,
-	FN_SEL_VIN1_0, FN_SEL_VIN1_1,
-	FN_SEL_HIF_0, FN_SEL_HIF_1,
-	FN_SEL_RSPI_0, FN_SEL_RSPI_1,
-	FN_SEL_LCDC_0, FN_SEL_LCDC_1,
-	FN_SEL_ET0_CTL_0, FN_SEL_ET0_CTL_1, FN_SEL_ET0_CTL_2,
-	FN_SEL_ET0_0, FN_SEL_ET0_1,
-	FN_SEL_RMII_0, FN_SEL_RMII_1,
-	FN_SEL_TMU_0, FN_SEL_TMU_1,
-	FN_SEL_HSPI_0, FN_SEL_HSPI_1, FN_SEL_HSPI_2,
-	FN_SEL_HSCIF_0, FN_SEL_HSCIF_1, FN_SEL_HSCIF_2, FN_SEL_HSCIF_3,
-	FN_SEL_RCAN_CLK_0, FN_SEL_RCAN_CLK_1,
-	FN_SEL_RCAN1_0, FN_SEL_RCAN1_1, FN_SEL_RCAN1_2,
-	FN_SEL_RCAN0_0, FN_SEL_RCAN0_1,
-	FN_SEL_SDHI2_0, FN_SEL_SDHI2_1,
-	FN_SEL_SDHI1_0, FN_SEL_SDHI1_1,
-	FN_SEL_SDHI0_0, FN_SEL_SDHI0_1,
-	FN_SEL_SSI1_0, FN_SEL_SSI1_1,
-	FN_SEL_SSI0_0, FN_SEL_SSI0_1,
-	FN_SEL_AUDIO_CLKB_0, FN_SEL_AUDIO_CLKB_1,
-	FN_SEL_AUDIO_CLKA_0, FN_SEL_AUDIO_CLKA_1,
-	FN_SEL_FLCTL_0, FN_SEL_FLCTL_1,
-	FN_SEL_MMC_0, FN_SEL_MMC_1,
-	FN_SEL_INTC_0, FN_SEL_INTC_1,
-
-	/* MOD_SEL2 */
-	FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1,
-	FN_SEL_MTU2_CH4_0, FN_SEL_MTU2_CH4_1,
-	FN_SEL_MTU2_CH3_0, FN_SEL_MTU2_CH3_1,
-	FN_SEL_MTU2_CH2_0, FN_SEL_MTU2_CH2_1, FN_SEL_MTU2_CH2_2,
-	FN_SEL_MTU2_CH1_0, FN_SEL_MTU2_CH1_1, FN_SEL_MTU2_CH1_2,
-	FN_SEL_MTU2_CH0_0, FN_SEL_MTU2_CH0_1,
-	FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
-	FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
-	FN_SEL_SCIF4_0, FN_SEL_SCIF4_1,
-	FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
-	FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
-		FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
-	FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
-		FN_SEL_SCIF2_3,
-	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
-		FN_SEL_SCIF1_3, FN_SEL_SCIF1_4,
-	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
-	FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2,
-
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-
-	CLKOUT_MARK, BS_MARK, CS0_MARK, EX_CS0_MARK, RD_MARK,
-	WE0_MARK, WE1_MARK,
-
-	SCL0_MARK, PENC0_MARK, USB_OVC0_MARK,
-
-	IRQ2_B_MARK, IRQ3_B_MARK,
-
-	/* IPSR0 */
-	A15_MARK, ST0_VCO_CLKIN_MARK, LCD_DATA15_A_MARK, TIOC3D_C_MARK,
-	A14_MARK, LCD_DATA14_A_MARK, TIOC3C_C_MARK,
-	A13_MARK, LCD_DATA13_A_MARK, TIOC3B_C_MARK,
-	A12_MARK, LCD_DATA12_A_MARK, TIOC3A_C_MARK,
-	A11_MARK, ST0_D7_MARK, LCD_DATA11_A_MARK, TIOC2B_C_MARK,
-	A10_MARK, ST0_D6_MARK, LCD_DATA10_A_MARK, TIOC2A_C_MARK,
-	A9_MARK, ST0_D5_MARK, LCD_DATA9_A_MARK, TIOC1B_C_MARK,
-	A8_MARK, ST0_D4_MARK, LCD_DATA8_A_MARK, TIOC1A_C_MARK,
-	A7_MARK, ST0_D3_MARK, LCD_DATA7_A_MARK, TIOC0D_C_MARK,
-	A6_MARK, ST0_D2_MARK, LCD_DATA6_A_MARK, TIOC0C_C_MARK,
-	A5_MARK, ST0_D1_MARK, LCD_DATA5_A_MARK, TIOC0B_C_MARK,
-	A4_MARK, ST0_D0_MARK, LCD_DATA4_A_MARK, TIOC0A_C_MARK,
-	A3_MARK, ST0_VLD_MARK, LCD_DATA3_A_MARK, TCLKD_C_MARK,
-	A2_MARK, ST0_SYC_MARK, LCD_DATA2_A_MARK, TCLKC_C_MARK,
-	A1_MARK, ST0_REQ_MARK, LCD_DATA1_A_MARK, TCLKB_C_MARK,
-	A0_MARK, ST0_CLKIN_MARK, LCD_DATA0_A_MARK, TCLKA_C_MARK,
-
-	/* IPSR1 */
-	D3_MARK, SD0_DAT3_A_MARK, MMC_D3_A_MARK, ST1_D6_MARK, FD3_A_MARK,
-	D2_MARK, SD0_DAT2_A_MARK, MMC_D2_A_MARK, ST1_D5_MARK, FD2_A_MARK,
-	D1_MARK, SD0_DAT1_A_MARK, MMC_D1_A_MARK, ST1_D4_MARK, FD1_A_MARK,
-	D0_MARK, SD0_DAT0_A_MARK, MMC_D0_A_MARK, ST1_D3_MARK, FD0_A_MARK,
-	A25_MARK, TX2_D_MARK, ST1_D2_MARK,
-	A24_MARK, RX2_D_MARK, ST1_D1_MARK,
-	A23_MARK, ST1_D0_MARK, LCD_M_DISP_A_MARK,
-	A22_MARK, ST1_VLD_MARK, LCD_VEPWC_A_MARK,
-	A21_MARK, ST1_SYC_MARK, LCD_VCPWC_A_MARK,
-	A20_MARK, ST1_REQ_MARK, LCD_FLM_A_MARK,
-	A19_MARK, ST1_CLKIN_MARK, LCD_CLK_A_MARK,	TIOC4D_C_MARK,
-	A18_MARK, ST1_PWM_MARK, LCD_CL2_A_MARK, TIOC4C_C_MARK,
-	A17_MARK, ST1_VCO_CLKIN_MARK, LCD_CL1_A_MARK, TIOC4B_C_MARK,
-	A16_MARK, ST0_PWM_MARK, LCD_DON_A_MARK, TIOC4A_C_MARK,
-
-	/* IPSR2 */
-	D14_MARK, TX2_B_MARK, FSE_A_MARK, ET0_TX_CLK_B_MARK,
-	D13_MARK, RX2_B_MARK, FRB_A_MARK, ET0_ETXD6_B_MARK,
-	D12_MARK, FWE_A_MARK, ET0_ETXD5_B_MARK,
-	D11_MARK, RSPI_MISO_A_MARK, QMI_QIO1_A_MARK, FRE_A_MARK,
-		ET0_ETXD3_B_MARK,
-	D10_MARK, RSPI_MOSI_A_MARK, QMO_QIO0_A_MARK, FALE_A_MARK,
-		ET0_ETXD2_B_MARK,
-	D9_MARK, SD0_CMD_A_MARK, MMC_CMD_A_MARK, QIO3_A_MARK,
-		FCLE_A_MARK, ET0_ETXD1_B_MARK,
-	D8_MARK, SD0_CLK_A_MARK, MMC_CLK_A_MARK, QIO2_A_MARK,
-		FCE_A_MARK, ET0_GTX_CLK_B_MARK,
-	D7_MARK, RSPI_SSL_A_MARK, MMC_D7_A_MARK, QSSL_A_MARK,
-		FD7_A_MARK,
-	D6_MARK, RSPI_RSPCK_A_MARK, MMC_D6_A_MARK, QSPCLK_A_MARK,
-		FD6_A_MARK,
-	D5_MARK, SD0_WP_A_MARK, MMC_D5_A_MARK, FD5_A_MARK,
-	D4_MARK, SD0_CD_A_MARK, MMC_D4_A_MARK, ST1_D7_MARK,
-		FD4_A_MARK,
-
-	/* IPSR3 */
-	DRACK0_MARK, SD1_DAT2_A_MARK, ATAG_MARK, TCLK1_A_MARK, ET0_ETXD7_MARK,
-	EX_WAIT2_MARK, SD1_DAT1_A_MARK, DACK2_MARK, CAN1_RX_C_MARK,
-		ET0_MAGIC_C_MARK, ET0_ETXD6_A_MARK,
-	EX_WAIT1_MARK, SD1_DAT0_A_MARK, DREQ2_MARK, CAN1_TX_C_MARK,
-		ET0_LINK_C_MARK, ET0_ETXD5_A_MARK,
-	EX_WAIT0_MARK, TCLK1_B_MARK,
-	RD_WR_MARK, TCLK0_MARK, CAN_CLK_B_MARK, ET0_ETXD4_MARK,
-	EX_CS5_MARK, SD1_CMD_A_MARK, ATADIR_MARK, QSSL_B_MARK,
-		ET0_ETXD3_A_MARK,
-	EX_CS4_MARK, SD1_WP_A_MARK, ATAWR_MARK, QMI_QIO1_B_MARK,
-		ET0_ETXD2_A_MARK,
-	EX_CS3_MARK, SD1_CD_A_MARK, ATARD_MARK, QMO_QIO0_B_MARK,
-		ET0_ETXD1_A_MARK,
-	EX_CS2_MARK, TX3_B_MARK, ATACS1_MARK, QSPCLK_B_MARK,
-		ET0_GTX_CLK_A_MARK,
-	EX_CS1_MARK, RX3_B_MARK, ATACS0_MARK, QIO2_B_MARK,
-		ET0_ETXD0_MARK,
-	CS1_A26_MARK, QIO3_B_MARK,
-	D15_MARK, SCK2_B_MARK,
-
-	/* IPSR4 */
-	SCK2_A_MARK, VI0_G3_MARK,
-	RTS1_B_MARK, VI0_G2_MARK,
-	CTS1_B_MARK, VI0_DATA7_VI0_G1_MARK,
-	TX1_B_MARK, VI0_DATA6_VI0_G0_MARK, ET0_PHY_INT_A_MARK,
-	RX1_B_MARK, VI0_DATA5_VI0_B5_MARK, ET0_MAGIC_A_MARK,
-	SCK1_B_MARK, VI0_DATA4_VI0_B4_MARK, ET0_LINK_A_MARK,
-	RTS0_B_MARK, VI0_DATA3_VI0_B3_MARK, ET0_MDIO_A_MARK,
-	CTS0_B_MARK, VI0_DATA2_VI0_B2_MARK, RMII0_MDIO_A_MARK,
-		ET0_MDC_MARK,
-	HTX0_A_MARK, TX1_A_MARK, VI0_DATA1_VI0_B1_MARK,
-		RMII0_MDC_A_MARK, ET0_COL_MARK,
-	HRX0_A_MARK, RX1_A_MARK, VI0_DATA0_VI0_B0_MARK,
-		RMII0_CRS_DV_A_MARK, ET0_CRS_MARK,
-	HSCK0_A_MARK, SCK1_A_MARK, VI0_VSYNC_MARK,
-		RMII0_RX_ER_A_MARK, ET0_RX_ER_MARK,
-	HRTS0_A_MARK, RTS1_A_MARK, VI0_HSYNC_MARK,
-		RMII0_TXD_EN_A_MARK, ET0_RX_DV_MARK,
-	HCTS0_A_MARK, CTS1_A_MARK, VI0_FIELD_MARK,
-		RMII0_RXD1_A_MARK, ET0_ERXD7_MARK,
-
-	/* IPSR5 */
-	SD2_CLK_A_MARK, RX2_A_MARK, VI0_G4_MARK, ET0_RX_CLK_B_MARK,
-	SD2_CMD_A_MARK, TX2_A_MARK, VI0_G5_MARK, ET0_ERXD2_B_MARK,
-	SD2_DAT0_A_MARK, RX3_A_MARK, VI0_R0_MARK, ET0_ERXD3_B_MARK,
-	SD2_DAT1_A_MARK, TX3_A_MARK, VI0_R1_MARK, ET0_MDIO_B_MARK,
-	SD2_DAT2_A_MARK, RX4_A_MARK, VI0_R2_MARK, ET0_LINK_B_MARK,
-	SD2_DAT3_A_MARK, TX4_A_MARK, VI0_R3_MARK, ET0_MAGIC_B_MARK,
-	SD2_CD_A_MARK, RX5_A_MARK, VI0_R4_MARK, ET0_PHY_INT_B_MARK,
-	SD2_WP_A_MARK, TX5_A_MARK, VI0_R5_MARK,
-	REF125CK_MARK, ADTRG_MARK, RX5_C_MARK,
-	REF50CK_MARK, CTS1_E_MARK, HCTS0_D_MARK,
-
-	/* IPSR6 */
-	DU0_DR0_MARK, SCIF_CLK_B_MARK, HRX0_D_MARK, IETX_A_MARK,
-		TCLKA_A_MARK, HIFD00_MARK,
-	DU0_DR1_MARK, SCK0_B_MARK, HTX0_D_MARK, IERX_A_MARK,
-		TCLKB_A_MARK, HIFD01_MARK,
-	DU0_DR2_MARK, RX0_B_MARK, TCLKC_A_MARK, HIFD02_MARK,
-	DU0_DR3_MARK, TX0_B_MARK, TCLKD_A_MARK, HIFD03_MARK,
-	DU0_DR4_MARK, CTS0_C_MARK, TIOC0A_A_MARK, HIFD04_MARK,
-	DU0_DR5_MARK, RTS0_C_MARK, TIOC0B_A_MARK, HIFD05_MARK,
-	DU0_DR6_MARK, SCK1_C_MARK, TIOC0C_A_MARK, HIFD06_MARK,
-	DU0_DR7_MARK, RX1_C_MARK, TIOC0D_A_MARK, HIFD07_MARK,
-	DU0_DG0_MARK, TX1_C_MARK, HSCK0_D_MARK, IECLK_A_MARK,
-		TIOC1A_A_MARK, HIFD08_MARK,
-	DU0_DG1_MARK, CTS1_C_MARK, HRTS0_D_MARK, TIOC1B_A_MARK,
-		HIFD09_MARK,
-
-	/* IPSR7 */
-	DU0_DG2_MARK, RTS1_C_MARK, RMII0_MDC_B_MARK, TIOC2A_A_MARK,
-		HIFD10_MARK,
-	DU0_DG3_MARK, SCK2_C_MARK, RMII0_MDIO_B_MARK, TIOC2B_A_MARK,
-		HIFD11_MARK,
-	DU0_DG4_MARK, RX2_C_MARK, RMII0_CRS_DV_B_MARK, TIOC3A_A_MARK,
-		HIFD12_MARK,
-	DU0_DG5_MARK, TX2_C_MARK, RMII0_RX_ER_B_MARK, TIOC3B_A_MARK,
-		HIFD13_MARK,
-	DU0_DG6_MARK, RX3_C_MARK, RMII0_RXD0_B_MARK, TIOC3C_A_MARK,
-		HIFD14_MARK,
-	DU0_DG7_MARK, TX3_C_MARK, RMII0_RXD1_B_MARK, TIOC3D_A_MARK,
-		HIFD15_MARK,
-	DU0_DB0_MARK, RX4_C_MARK, RMII0_TXD_EN_B_MARK, TIOC4A_A_MARK,
-		HIFCS_MARK,
-	DU0_DB1_MARK, TX4_C_MARK, RMII0_TXD0_B_MARK, TIOC4B_A_MARK,
-		HIFRS_MARK,
-	DU0_DB2_MARK, RX5_B_MARK, RMII0_TXD1_B_MARK, TIOC4C_A_MARK,
-		HIFWR_MARK,
-	DU0_DB3_MARK, TX5_B_MARK, TIOC4D_A_MARK, HIFRD_MARK,
-	DU0_DB4_MARK, HIFINT_MARK,
-
-	/* IPSR8 */
-	DU0_DB5_MARK, HIFDREQ_MARK,
-	DU0_DB6_MARK, HIFRDY_MARK,
-	DU0_DB7_MARK, SSI_SCK0_B_MARK, HIFEBL_B_MARK,
-	DU0_DOTCLKIN_MARK, HSPI_CS0_C_MARK, SSI_WS0_B_MARK,
-	DU0_DOTCLKOUT_MARK, HSPI_CLK0_C_MARK, SSI_SDATA0_B_MARK,
-	DU0_EXHSYNC_DU0_HSYNC_MARK, HSPI_TX0_C_MARK, SSI_SCK1_B_MARK,
-	DU0_EXVSYNC_DU0_VSYNC_MARK, HSPI_RX0_C_MARK, SSI_WS1_B_MARK,
-	DU0_EXODDF_DU0_ODDF_MARK, CAN0_RX_B_MARK, HSCK0_B_MARK,
-		SSI_SDATA1_B_MARK,
-	DU0_DISP_MARK, CAN0_TX_B_MARK, HRX0_B_MARK, AUDIO_CLKA_B_MARK,
-	DU0_CDE_MARK, HTX0_B_MARK, AUDIO_CLKB_B_MARK, LCD_VCPWC_B_MARK,
-	IRQ0_A_MARK, HSPI_TX_B_MARK, RX3_E_MARK, ET0_ERXD0_MARK,
-	IRQ1_A_MARK, HSPI_RX_B_MARK, TX3_E_MARK, ET0_ERXD1_MARK,
-	IRQ2_A_MARK, CTS0_A_MARK, HCTS0_B_MARK, ET0_ERXD2_A_MARK,
-	IRQ3_A_MARK, RTS0_A_MARK, HRTS0_B_MARK, ET0_ERXD3_A_MARK,
-
-	/* IPSR9 */
-	VI1_CLK_A_MARK, FD0_B_MARK, LCD_DATA0_B_MARK,
-	VI1_0_A_MARK, FD1_B_MARK, LCD_DATA1_B_MARK,
-	VI1_1_A_MARK, FD2_B_MARK, LCD_DATA2_B_MARK,
-	VI1_2_A_MARK, FD3_B_MARK, LCD_DATA3_B_MARK,
-	VI1_3_A_MARK, FD4_B_MARK, LCD_DATA4_B_MARK,
-	VI1_4_A_MARK, FD5_B_MARK, LCD_DATA5_B_MARK,
-	VI1_5_A_MARK, FD6_B_MARK, LCD_DATA6_B_MARK,
-	VI1_6_A_MARK, FD7_B_MARK, LCD_DATA7_B_MARK,
-	VI1_7_A_MARK, FCE_B_MARK, LCD_DATA8_B_MARK,
-	SSI_SCK0_A_MARK, TIOC1A_B_MARK, LCD_DATA9_B_MARK,
-	SSI_WS0_A_MARK, TIOC1B_B_MARK, LCD_DATA10_B_MARK,
-	SSI_SDATA0_A_MARK, VI1_0_B_MARK, TIOC2A_B_MARK, LCD_DATA11_B_MARK,
-	SSI_SCK1_A_MARK, VI1_1_B_MARK, TIOC2B_B_MARK, LCD_DATA12_B_MARK,
-	SSI_WS1_A_MARK, VI1_2_B_MARK, LCD_DATA13_B_MARK,
-	SSI_SDATA1_A_MARK, VI1_3_B_MARK, LCD_DATA14_B_MARK,
-
-	/* IPSR10 */
-	SSI_SCK23_MARK, VI1_4_B_MARK, RX1_D_MARK, FCLE_B_MARK,
-		LCD_DATA15_B_MARK,
-	SSI_WS23_MARK, VI1_5_B_MARK, TX1_D_MARK, HSCK0_C_MARK,
-		FALE_B_MARK, LCD_DON_B_MARK,
-	SSI_SDATA2_MARK, VI1_6_B_MARK, HRX0_C_MARK, FRE_B_MARK,
-		LCD_CL1_B_MARK,
-	SSI_SDATA3_MARK, VI1_7_B_MARK, HTX0_C_MARK, FWE_B_MARK,
-		LCD_CL2_B_MARK,
-	AUDIO_CLKA_A_MARK, VI1_CLK_B_MARK, SCK1_D_MARK, IECLK_B_MARK,
-		LCD_FLM_B_MARK,
-	AUDIO_CLKB_A_MARK, LCD_CLK_B_MARK,
-	AUDIO_CLKC_MARK, SCK1_E_MARK, HCTS0_C_MARK, FRB_B_MARK,
-		LCD_VEPWC_B_MARK,
-	AUDIO_CLKOUT_MARK, TX1_E_MARK, HRTS0_C_MARK, FSE_B_MARK,
-		LCD_M_DISP_B_MARK,
-	CAN_CLK_A_MARK, RX4_D_MARK,
-	CAN0_TX_A_MARK, TX4_D_MARK, MLB_CLK_MARK,
-	CAN1_RX_A_MARK, IRQ1_B_MARK,
-	CAN0_RX_A_MARK, IRQ0_B_MARK, MLB_SIG_MARK,
-	CAN1_TX_A_MARK, TX5_C_MARK, MLB_DAT_MARK,
-
-	/* IPSR11 */
-	SCL1_MARK, SCIF_CLK_C_MARK,
-	SDA1_MARK, RX1_E_MARK,
-	SDA0_MARK, HIFEBL_A_MARK,
-	SDSELF_MARK, RTS1_E_MARK,
-	SCIF_CLK_A_MARK, HSPI_CLK_A_MARK, VI0_CLK_MARK, RMII0_TXD0_A_MARK,
-		ET0_ERXD4_MARK,
-	SCK0_A_MARK, HSPI_CS_A_MARK, VI0_CLKENB_MARK, RMII0_TXD1_A_MARK,
-		ET0_ERXD5_MARK,
-	RX0_A_MARK, HSPI_RX_A_MARK, RMII0_RXD0_A_MARK, ET0_ERXD6_MARK,
-	TX0_A_MARK, HSPI_TX_A_MARK,
-	PENC1_MARK, TX3_D_MARK, CAN1_TX_B_MARK, TX5_D_MARK,
-		IETX_B_MARK,
-	USB_OVC1_MARK, RX3_D_MARK, CAN1_RX_B_MARK, RX5_D_MARK,
-		IERX_B_MARK,
-	DREQ0_MARK, SD1_CLK_A_MARK, ET0_TX_EN_MARK,
-	DACK0_MARK, SD1_DAT3_A_MARK, ET0_TX_ER_MARK,
-	DREQ1_MARK, HSPI_CLK_B_MARK, RX4_B_MARK, ET0_PHY_INT_C_MARK,
-		ET0_TX_CLK_A_MARK,
-	DACK1_MARK, HSPI_CS_B_MARK, TX4_B_MARK, ET0_RX_CLK_A_MARK,
-	PRESETOUT_MARK, ST_CLKOUT_MARK,
-
-	PINMUX_MARK_END,
-};
-
-static const u16 pinmux_data[] = {
-	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
-
-	PINMUX_SINGLE(CLKOUT),
-	PINMUX_SINGLE(BS),
-	PINMUX_SINGLE(CS0),
-	PINMUX_SINGLE(EX_CS0),
-	PINMUX_SINGLE(RD),
-	PINMUX_SINGLE(WE0),
-	PINMUX_SINGLE(WE1),
-	PINMUX_SINGLE(SCL0),
-	PINMUX_SINGLE(PENC0),
-	PINMUX_SINGLE(USB_OVC0),
-	PINMUX_SINGLE(IRQ2_B),
-	PINMUX_SINGLE(IRQ3_B),
-
-	/* IPSR0 */
-	PINMUX_IPSR_GPSR(IP0_1_0, A0),
-	PINMUX_IPSR_GPSR(IP0_1_0, ST0_CLKIN),
-	PINMUX_IPSR_MSEL(IP0_1_0, LCD_DATA0_A, SEL_LCDC_0),
-	PINMUX_IPSR_MSEL(IP0_1_0, TCLKA_C, SEL_MTU2_CLK_1),
-
-	PINMUX_IPSR_GPSR(IP0_3_2, A1),
-	PINMUX_IPSR_GPSR(IP0_3_2, ST0_REQ),
-	PINMUX_IPSR_MSEL(IP0_3_2, LCD_DATA1_A, SEL_LCDC_0),
-	PINMUX_IPSR_MSEL(IP0_3_2, TCLKB_C, SEL_MTU2_CLK_1),
-
-	PINMUX_IPSR_GPSR(IP0_5_4, A2),
-	PINMUX_IPSR_GPSR(IP0_5_4, ST0_SYC),
-	PINMUX_IPSR_MSEL(IP0_5_4, LCD_DATA2_A, SEL_LCDC_0),
-	PINMUX_IPSR_MSEL(IP0_5_4, TCLKC_C, SEL_MTU2_CLK_1),
-
-	PINMUX_IPSR_GPSR(IP0_7_6, A3),
-	PINMUX_IPSR_GPSR(IP0_7_6, ST0_VLD),
-	PINMUX_IPSR_MSEL(IP0_7_6, LCD_DATA3_A, SEL_LCDC_0),
-	PINMUX_IPSR_MSEL(IP0_7_6, TCLKD_C, SEL_MTU2_CLK_1),
-
-	PINMUX_IPSR_GPSR(IP0_9_8, A4),
-	PINMUX_IPSR_GPSR(IP0_9_8, ST0_D0),
-	PINMUX_IPSR_MSEL(IP0_9_8, LCD_DATA4_A, SEL_LCDC_0),
-	PINMUX_IPSR_MSEL(IP0_9_8, TIOC0A_C, SEL_MTU2_CH0_1),
-
-	PINMUX_IPSR_GPSR(IP0_11_10, A5),
-	PINMUX_IPSR_GPSR(IP0_11_10, ST0_D1),
-	PINMUX_IPSR_MSEL(IP0_11_10, LCD_DATA5_A, SEL_LCDC_0),
-	PINMUX_IPSR_MSEL(IP0_11_10, TIOC0B_C, SEL_MTU2_CH0_1),
-
-	PINMUX_IPSR_GPSR(IP0_13_12, A6),
-	PINMUX_IPSR_GPSR(IP0_13_12, ST0_D2),
-	PINMUX_IPSR_MSEL(IP0_13_12, LCD_DATA6_A, SEL_LCDC_0),
-	PINMUX_IPSR_MSEL(IP0_13_12, TIOC0C_C, SEL_MTU2_CH0_1),
-
-	PINMUX_IPSR_GPSR(IP0_15_14, A7),
-	PINMUX_IPSR_GPSR(IP0_15_14, ST0_D3),
-	PINMUX_IPSR_MSEL(IP0_15_14, LCD_DATA7_A, SEL_LCDC_0),
-	PINMUX_IPSR_MSEL(IP0_15_14, TIOC0D_C, SEL_MTU2_CH0_1),
-
-	PINMUX_IPSR_GPSR(IP0_17_16, A8),
-	PINMUX_IPSR_GPSR(IP0_17_16, ST0_D4),
-	PINMUX_IPSR_MSEL(IP0_17_16, LCD_DATA8_A, SEL_LCDC_0),
-	PINMUX_IPSR_MSEL(IP0_17_16, TIOC1A_C, SEL_MTU2_CH1_2),
-
-	PINMUX_IPSR_GPSR(IP0_19_18, A9),
-	PINMUX_IPSR_GPSR(IP0_19_18, ST0_D5),
-	PINMUX_IPSR_MSEL(IP0_19_18, LCD_DATA9_A, SEL_LCDC_0),
-	PINMUX_IPSR_MSEL(IP0_19_18, TIOC1B_C, SEL_MTU2_CH1_2),
-
-	PINMUX_IPSR_GPSR(IP0_21_20, A10),
-	PINMUX_IPSR_GPSR(IP0_21_20, ST0_D6),
-	PINMUX_IPSR_MSEL(IP0_21_20, LCD_DATA10_A, SEL_LCDC_0),
-	PINMUX_IPSR_MSEL(IP0_21_20, TIOC2A_C, SEL_MTU2_CH2_2),
-
-	PINMUX_IPSR_GPSR(IP0_23_22, A11),
-	PINMUX_IPSR_GPSR(IP0_23_22, ST0_D7),
-	PINMUX_IPSR_MSEL(IP0_23_22, LCD_DATA11_A, SEL_LCDC_0),
-	PINMUX_IPSR_MSEL(IP0_23_22, TIOC2B_C, SEL_MTU2_CH2_2),
-
-	PINMUX_IPSR_GPSR(IP0_25_24, A12),
-	PINMUX_IPSR_MSEL(IP0_25_24, LCD_DATA12_A, SEL_LCDC_0),
-	PINMUX_IPSR_MSEL(IP0_25_24, TIOC3A_C, SEL_MTU2_CH3_1),
-
-	PINMUX_IPSR_GPSR(IP0_27_26, A13),
-	PINMUX_IPSR_MSEL(IP0_27_26, LCD_DATA13_A, SEL_LCDC_0),
-	PINMUX_IPSR_MSEL(IP0_27_26, TIOC3B_C, SEL_MTU2_CH3_1),
-
-	PINMUX_IPSR_GPSR(IP0_29_28, A14),
-	PINMUX_IPSR_MSEL(IP0_29_28, LCD_DATA14_A, SEL_LCDC_0),
-	PINMUX_IPSR_MSEL(IP0_29_28, TIOC3C_C, SEL_MTU2_CH3_1),
-
-	PINMUX_IPSR_GPSR(IP0_31_30, A15),
-	PINMUX_IPSR_GPSR(IP0_31_30, ST0_VCO_CLKIN),
-	PINMUX_IPSR_MSEL(IP0_31_30, LCD_DATA15_A, SEL_LCDC_0),
-	PINMUX_IPSR_MSEL(IP0_31_30, TIOC3D_C, SEL_MTU2_CH3_1),
-
-
-	/* IPSR1 */
-	PINMUX_IPSR_GPSR(IP1_1_0, A16),
-	PINMUX_IPSR_GPSR(IP1_1_0, ST0_PWM),
-	PINMUX_IPSR_MSEL(IP1_1_0, LCD_DON_A, SEL_LCDC_0),
-	PINMUX_IPSR_MSEL(IP1_1_0, TIOC4A_C, SEL_MTU2_CH4_1),
-
-	PINMUX_IPSR_GPSR(IP1_3_2, A17),
-	PINMUX_IPSR_GPSR(IP1_3_2, ST1_VCO_CLKIN),
-	PINMUX_IPSR_MSEL(IP1_3_2, LCD_CL1_A, SEL_LCDC_0),
-	PINMUX_IPSR_MSEL(IP1_3_2, TIOC4B_C, SEL_MTU2_CH4_1),
-
-	PINMUX_IPSR_GPSR(IP1_5_4, A18),
-	PINMUX_IPSR_GPSR(IP1_5_4, ST1_PWM),
-	PINMUX_IPSR_MSEL(IP1_5_4, LCD_CL2_A, SEL_LCDC_0),
-	PINMUX_IPSR_MSEL(IP1_5_4, TIOC4C_C, SEL_MTU2_CH4_1),
-
-	PINMUX_IPSR_GPSR(IP1_7_6, A19),
-	PINMUX_IPSR_GPSR(IP1_7_6, ST1_CLKIN),
-	PINMUX_IPSR_MSEL(IP1_7_6, LCD_CLK_A, SEL_LCDC_0),
-	PINMUX_IPSR_MSEL(IP1_7_6, TIOC4D_C, SEL_MTU2_CH4_1),
-
-	PINMUX_IPSR_GPSR(IP1_9_8, A20),
-	PINMUX_IPSR_GPSR(IP1_9_8, ST1_REQ),
-	PINMUX_IPSR_MSEL(IP1_9_8, LCD_FLM_A, SEL_LCDC_0),
-
-	PINMUX_IPSR_GPSR(IP1_11_10, A21),
-	PINMUX_IPSR_GPSR(IP1_11_10, ST1_SYC),
-	PINMUX_IPSR_MSEL(IP1_11_10, LCD_VCPWC_A, SEL_LCDC_0),
-
-	PINMUX_IPSR_GPSR(IP1_13_12, A22),
-	PINMUX_IPSR_GPSR(IP1_13_12, ST1_VLD),
-	PINMUX_IPSR_MSEL(IP1_13_12, LCD_VEPWC_A, SEL_LCDC_0),
-
-	PINMUX_IPSR_GPSR(IP1_15_14, A23),
-	PINMUX_IPSR_GPSR(IP1_15_14, ST1_D0),
-	PINMUX_IPSR_MSEL(IP1_15_14, LCD_M_DISP_A, SEL_LCDC_0),
-
-	PINMUX_IPSR_GPSR(IP1_17_16, A24),
-	PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3),
-	PINMUX_IPSR_GPSR(IP1_17_16, ST1_D1),
-
-	PINMUX_IPSR_GPSR(IP1_19_18, A25),
-	PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3),
-	PINMUX_IPSR_GPSR(IP1_17_16, ST1_D2),
-
-	PINMUX_IPSR_GPSR(IP1_22_20, D0),
-	PINMUX_IPSR_MSEL(IP1_22_20, SD0_DAT0_A, SEL_SDHI0_0),
-	PINMUX_IPSR_MSEL(IP1_22_20, MMC_D0_A, SEL_MMC_0),
-	PINMUX_IPSR_GPSR(IP1_22_20, ST1_D3),
-	PINMUX_IPSR_MSEL(IP1_22_20, FD0_A, SEL_FLCTL_0),
-
-	PINMUX_IPSR_GPSR(IP1_25_23, D1),
-	PINMUX_IPSR_MSEL(IP1_25_23, SD0_DAT0_A, SEL_SDHI0_0),
-	PINMUX_IPSR_MSEL(IP1_25_23, MMC_D1_A, SEL_MMC_0),
-	PINMUX_IPSR_GPSR(IP1_25_23, ST1_D4),
-	PINMUX_IPSR_MSEL(IP1_25_23, FD1_A, SEL_FLCTL_0),
-
-	PINMUX_IPSR_GPSR(IP1_28_26, D2),
-	PINMUX_IPSR_MSEL(IP1_28_26, SD0_DAT0_A, SEL_SDHI0_0),
-	PINMUX_IPSR_MSEL(IP1_28_26, MMC_D2_A, SEL_MMC_0),
-	PINMUX_IPSR_GPSR(IP1_28_26, ST1_D5),
-	PINMUX_IPSR_MSEL(IP1_28_26, FD2_A, SEL_FLCTL_0),
-
-	PINMUX_IPSR_GPSR(IP1_31_29, D3),
-	PINMUX_IPSR_MSEL(IP1_31_29, SD0_DAT0_A, SEL_SDHI0_0),
-	PINMUX_IPSR_MSEL(IP1_31_29, MMC_D3_A, SEL_MMC_0),
-	PINMUX_IPSR_GPSR(IP1_31_29, ST1_D6),
-	PINMUX_IPSR_MSEL(IP1_31_29, FD3_A, SEL_FLCTL_0),
-
-	/* IPSR2 */
-	PINMUX_IPSR_GPSR(IP2_2_0, D4),
-	PINMUX_IPSR_MSEL(IP2_2_0, SD0_CD_A, SEL_SDHI0_0),
-	PINMUX_IPSR_MSEL(IP2_2_0, MMC_D4_A, SEL_MMC_0),
-	PINMUX_IPSR_GPSR(IP2_2_0, ST1_D7),
-	PINMUX_IPSR_MSEL(IP2_2_0, FD4_A, SEL_FLCTL_0),
-
-	PINMUX_IPSR_GPSR(IP2_4_3, D5),
-	PINMUX_IPSR_MSEL(IP2_4_3, SD0_WP_A, SEL_SDHI0_0),
-	PINMUX_IPSR_MSEL(IP2_4_3, MMC_D5_A, SEL_MMC_0),
-	PINMUX_IPSR_MSEL(IP2_4_3, FD5_A, SEL_FLCTL_0),
-
-	PINMUX_IPSR_GPSR(IP2_7_5, D6),
-	PINMUX_IPSR_MSEL(IP2_7_5, RSPI_RSPCK_A, SEL_RSPI_0),
-	PINMUX_IPSR_MSEL(IP2_7_5, MMC_D6_A, SEL_MMC_0),
-	PINMUX_IPSR_MSEL(IP2_7_5, QSPCLK_A, SEL_RQSPI_0),
-	PINMUX_IPSR_MSEL(IP2_7_5, FD6_A, SEL_FLCTL_0),
-
-	PINMUX_IPSR_GPSR(IP2_10_8, D7),
-	PINMUX_IPSR_MSEL(IP2_10_8, RSPI_SSL_A, SEL_RSPI_0),
-	PINMUX_IPSR_MSEL(IP2_10_8, MMC_D7_A, SEL_MMC_0),
-	PINMUX_IPSR_MSEL(IP2_10_8, QSSL_A, SEL_RQSPI_0),
-	PINMUX_IPSR_MSEL(IP2_10_8, FD7_A, SEL_FLCTL_0),
-
-	PINMUX_IPSR_GPSR(IP2_13_11, D8),
-	PINMUX_IPSR_MSEL(IP2_13_11, SD0_CLK_A, SEL_SDHI0_0),
-	PINMUX_IPSR_MSEL(IP2_13_11, MMC_CLK_A, SEL_MMC_0),
-	PINMUX_IPSR_MSEL(IP2_13_11, QIO2_A, SEL_RQSPI_0),
-	PINMUX_IPSR_MSEL(IP2_13_11, FCE_A, SEL_FLCTL_0),
-	PINMUX_IPSR_MSEL(IP2_13_11, ET0_GTX_CLK_B, SEL_ET0_1),
-
-	PINMUX_IPSR_GPSR(IP2_16_14, D9),
-	PINMUX_IPSR_MSEL(IP2_16_14, SD0_CMD_A, SEL_SDHI0_0),
-	PINMUX_IPSR_MSEL(IP2_16_14, MMC_CMD_A, SEL_MMC_0),
-	PINMUX_IPSR_MSEL(IP2_16_14, QIO3_A, SEL_RQSPI_0),
-	PINMUX_IPSR_MSEL(IP2_16_14, FCLE_A, SEL_FLCTL_0),
-	PINMUX_IPSR_MSEL(IP2_16_14, ET0_ETXD1_B, SEL_ET0_1),
-
-	PINMUX_IPSR_GPSR(IP2_19_17, D10),
-	PINMUX_IPSR_MSEL(IP2_19_17, RSPI_MOSI_A, SEL_RSPI_0),
-	PINMUX_IPSR_MSEL(IP2_19_17, QMO_QIO0_A, SEL_RQSPI_0),
-	PINMUX_IPSR_MSEL(IP2_19_17, FALE_A, SEL_FLCTL_0),
-	PINMUX_IPSR_MSEL(IP2_19_17, ET0_ETXD2_B, SEL_ET0_1),
-
-	PINMUX_IPSR_GPSR(IP2_22_20, D11),
-	PINMUX_IPSR_MSEL(IP2_22_20, RSPI_MISO_A, SEL_RSPI_0),
-	PINMUX_IPSR_MSEL(IP2_22_20, QMI_QIO1_A, SEL_RQSPI_0),
-	PINMUX_IPSR_MSEL(IP2_22_20, FRE_A, SEL_FLCTL_0),
-
-	PINMUX_IPSR_GPSR(IP2_24_23, D12),
-	PINMUX_IPSR_MSEL(IP2_24_23, FWE_A, SEL_FLCTL_0),
-	PINMUX_IPSR_MSEL(IP2_24_23, ET0_ETXD5_B, SEL_ET0_1),
-
-	PINMUX_IPSR_GPSR(IP2_27_25, D13),
-	PINMUX_IPSR_MSEL(IP2_27_25, RX2_B, SEL_SCIF2_1),
-	PINMUX_IPSR_MSEL(IP2_27_25, FRB_A, SEL_FLCTL_0),
-	PINMUX_IPSR_MSEL(IP2_27_25, ET0_ETXD6_B, SEL_ET0_1),
-
-	PINMUX_IPSR_GPSR(IP2_30_28, D14),
-	PINMUX_IPSR_MSEL(IP2_30_28, TX2_B, SEL_SCIF2_1),
-	PINMUX_IPSR_MSEL(IP2_30_28, FSE_A, SEL_FLCTL_0),
-	PINMUX_IPSR_MSEL(IP2_30_28, ET0_TX_CLK_B, SEL_ET0_1),
-
-	/* IPSR3 */
-	PINMUX_IPSR_GPSR(IP3_1_0, D15),
-	PINMUX_IPSR_MSEL(IP3_1_0, SCK2_B, SEL_SCIF2_1),
-
-	PINMUX_IPSR_GPSR(IP3_2, CS1_A26),
-	PINMUX_IPSR_MSEL(IP3_2, QIO3_B, SEL_RQSPI_1),
-
-	PINMUX_IPSR_GPSR(IP3_5_3, EX_CS1),
-	PINMUX_IPSR_MSEL(IP3_5_3, RX3_B, SEL_SCIF2_1),
-	PINMUX_IPSR_GPSR(IP3_5_3, ATACS0),
-	PINMUX_IPSR_MSEL(IP3_5_3, QIO2_B, SEL_RQSPI_1),
-	PINMUX_IPSR_GPSR(IP3_5_3, ET0_ETXD0),
-
-	PINMUX_IPSR_GPSR(IP3_8_6, EX_CS2),
-	PINMUX_IPSR_MSEL(IP3_8_6, TX3_B, SEL_SCIF3_1),
-	PINMUX_IPSR_GPSR(IP3_8_6, ATACS1),
-	PINMUX_IPSR_MSEL(IP3_8_6, QSPCLK_B, SEL_RQSPI_1),
-	PINMUX_IPSR_MSEL(IP3_8_6, ET0_GTX_CLK_A, SEL_ET0_0),
-
-	PINMUX_IPSR_GPSR(IP3_11_9, EX_CS3),
-	PINMUX_IPSR_MSEL(IP3_11_9, SD1_CD_A, SEL_SDHI1_0),
-	PINMUX_IPSR_GPSR(IP3_11_9, ATARD),
-	PINMUX_IPSR_MSEL(IP3_11_9, QMO_QIO0_B, SEL_RQSPI_1),
-	PINMUX_IPSR_MSEL(IP3_11_9, ET0_ETXD1_A, SEL_ET0_0),
-
-	PINMUX_IPSR_GPSR(IP3_14_12, EX_CS4),
-	PINMUX_IPSR_MSEL(IP3_14_12, SD1_WP_A, SEL_SDHI1_0),
-	PINMUX_IPSR_GPSR(IP3_14_12, ATAWR),
-	PINMUX_IPSR_MSEL(IP3_14_12, QMI_QIO1_B, SEL_RQSPI_1),
-	PINMUX_IPSR_MSEL(IP3_14_12, ET0_ETXD2_A, SEL_ET0_0),
-
-	PINMUX_IPSR_GPSR(IP3_17_15, EX_CS5),
-	PINMUX_IPSR_MSEL(IP3_17_15, SD1_CMD_A, SEL_SDHI1_0),
-	PINMUX_IPSR_GPSR(IP3_17_15, ATADIR),
-	PINMUX_IPSR_MSEL(IP3_17_15, QSSL_B, SEL_RQSPI_1),
-	PINMUX_IPSR_MSEL(IP3_17_15, ET0_ETXD3_A, SEL_ET0_0),
-
-	PINMUX_IPSR_GPSR(IP3_19_18, RD_WR),
-	PINMUX_IPSR_GPSR(IP3_19_18, TCLK0),
-	PINMUX_IPSR_MSEL(IP3_19_18, CAN_CLK_B, SEL_RCAN_CLK_1),
-	PINMUX_IPSR_GPSR(IP3_19_18, ET0_ETXD4),
-
-	PINMUX_IPSR_GPSR(IP3_20, EX_WAIT0),
-	PINMUX_IPSR_MSEL(IP3_20, TCLK1_B, SEL_TMU_1),
-
-	PINMUX_IPSR_GPSR(IP3_23_21, EX_WAIT1),
-	PINMUX_IPSR_MSEL(IP3_23_21, SD1_DAT0_A, SEL_SDHI1_0),
-	PINMUX_IPSR_GPSR(IP3_23_21, DREQ2),
-	PINMUX_IPSR_MSEL(IP3_23_21, CAN1_TX_C, SEL_RCAN1_2),
-	PINMUX_IPSR_MSEL(IP3_23_21, ET0_LINK_C, SEL_ET0_CTL_2),
-	PINMUX_IPSR_MSEL(IP3_23_21, ET0_ETXD5_A, SEL_ET0_0),
-
-	PINMUX_IPSR_GPSR(IP3_26_24, EX_WAIT2),
-	PINMUX_IPSR_MSEL(IP3_26_24, SD1_DAT1_A, SEL_SDHI1_0),
-	PINMUX_IPSR_GPSR(IP3_26_24, DACK2),
-	PINMUX_IPSR_MSEL(IP3_26_24, CAN1_RX_C, SEL_RCAN1_2),
-	PINMUX_IPSR_MSEL(IP3_26_24, ET0_MAGIC_C, SEL_ET0_CTL_2),
-	PINMUX_IPSR_MSEL(IP3_26_24, ET0_ETXD6_A, SEL_ET0_0),
-
-	PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
-	PINMUX_IPSR_MSEL(IP3_29_27, SD1_DAT2_A, SEL_SDHI1_0),
-	PINMUX_IPSR_GPSR(IP3_29_27, ATAG),
-	PINMUX_IPSR_MSEL(IP3_29_27, TCLK1_A, SEL_TMU_0),
-	PINMUX_IPSR_GPSR(IP3_29_27, ET0_ETXD7),
-
-	/* IPSR4 */
-	PINMUX_IPSR_MSEL(IP4_2_0, HCTS0_A, SEL_HSCIF_0),
-	PINMUX_IPSR_MSEL(IP4_2_0, CTS1_A, SEL_SCIF1_0),
-	PINMUX_IPSR_GPSR(IP4_2_0, VI0_FIELD),
-	PINMUX_IPSR_MSEL(IP4_2_0, RMII0_RXD1_A, SEL_RMII_0),
-	PINMUX_IPSR_GPSR(IP4_2_0, ET0_ERXD7),
-
-	PINMUX_IPSR_MSEL(IP4_5_3, HRTS0_A, SEL_HSCIF_0),
-	PINMUX_IPSR_MSEL(IP4_5_3, RTS1_A, SEL_SCIF1_0),
-	PINMUX_IPSR_GPSR(IP4_5_3, VI0_HSYNC),
-	PINMUX_IPSR_MSEL(IP4_5_3, RMII0_TXD_EN_A, SEL_RMII_0),
-	PINMUX_IPSR_GPSR(IP4_5_3, ET0_RX_DV),
-
-	PINMUX_IPSR_MSEL(IP4_8_6, HSCK0_A, SEL_HSCIF_0),
-	PINMUX_IPSR_MSEL(IP4_8_6, SCK1_A, SEL_SCIF1_0),
-	PINMUX_IPSR_GPSR(IP4_8_6, VI0_VSYNC),
-	PINMUX_IPSR_MSEL(IP4_8_6, RMII0_RX_ER_A, SEL_RMII_0),
-	PINMUX_IPSR_GPSR(IP4_8_6, ET0_RX_ER),
-
-	PINMUX_IPSR_MSEL(IP4_11_9, HRX0_A, SEL_HSCIF_0),
-	PINMUX_IPSR_MSEL(IP4_11_9, RX1_A, SEL_SCIF1_0),
-	PINMUX_IPSR_GPSR(IP4_11_9, VI0_DATA0_VI0_B0),
-	PINMUX_IPSR_MSEL(IP4_11_9, RMII0_CRS_DV_A, SEL_RMII_0),
-	PINMUX_IPSR_GPSR(IP4_11_9, ET0_CRS),
-
-	PINMUX_IPSR_MSEL(IP4_14_12, HTX0_A, SEL_HSCIF_0),
-	PINMUX_IPSR_MSEL(IP4_14_12, TX1_A, SEL_SCIF1_0),
-	PINMUX_IPSR_GPSR(IP4_14_12, VI0_DATA1_VI0_B1),
-	PINMUX_IPSR_MSEL(IP4_14_12, RMII0_MDC_A, SEL_RMII_0),
-	PINMUX_IPSR_GPSR(IP4_14_12, ET0_COL),
-
-	PINMUX_IPSR_MSEL(IP4_17_15, CTS0_B, SEL_SCIF0_1),
-	PINMUX_IPSR_GPSR(IP4_17_15, VI0_DATA2_VI0_B2),
-	PINMUX_IPSR_MSEL(IP4_17_15, RMII0_MDIO_A, SEL_RMII_0),
-	PINMUX_IPSR_GPSR(IP4_17_15, ET0_MDC),
-
-	PINMUX_IPSR_MSEL(IP4_19_18, RTS0_B, SEL_SCIF0_1),
-	PINMUX_IPSR_GPSR(IP4_19_18, VI0_DATA3_VI0_B3),
-	PINMUX_IPSR_MSEL(IP4_19_18, ET0_MDIO_A, SEL_ET0_0),
-
-	PINMUX_IPSR_MSEL(IP4_21_20, SCK1_B, SEL_SCIF1_1),
-	PINMUX_IPSR_GPSR(IP4_21_20, VI0_DATA4_VI0_B4),
-	PINMUX_IPSR_MSEL(IP4_21_20, ET0_LINK_A, SEL_ET0_CTL_0),
-
-	PINMUX_IPSR_MSEL(IP4_23_22, RX1_B, SEL_SCIF1_1),
-	PINMUX_IPSR_GPSR(IP4_23_22, VI0_DATA5_VI0_B5),
-	PINMUX_IPSR_MSEL(IP4_23_22, ET0_MAGIC_A, SEL_ET0_CTL_0),
-
-	PINMUX_IPSR_MSEL(IP4_25_24, TX1_B, SEL_SCIF1_1),
-	PINMUX_IPSR_GPSR(IP4_25_24, VI0_DATA6_VI0_G0),
-	PINMUX_IPSR_MSEL(IP4_25_24, ET0_PHY_INT_A, SEL_ET0_CTL_0),
-
-	PINMUX_IPSR_MSEL(IP4_27_26, CTS1_B, SEL_SCIF1_1),
-	PINMUX_IPSR_GPSR(IP4_27_26, VI0_DATA7_VI0_G1),
-
-	PINMUX_IPSR_MSEL(IP4_29_28, RTS1_B, SEL_SCIF1_1),
-	PINMUX_IPSR_GPSR(IP4_29_28, VI0_G2),
-
-	PINMUX_IPSR_MSEL(IP4_31_30, SCK2_A, SEL_SCIF2_0),
-	PINMUX_IPSR_GPSR(IP4_31_30, VI0_G3),
-
-	/* IPSR5 */
-	PINMUX_IPSR_MSEL(IP5_2_0, SD2_CLK_A, SEL_SDHI2_0),
-	PINMUX_IPSR_MSEL(IP5_2_0, RX2_A, SEL_SCIF2_0),
-	PINMUX_IPSR_GPSR(IP5_2_0, VI0_G4),
-	PINMUX_IPSR_MSEL(IP5_2_0, ET0_RX_CLK_B, SEL_ET0_1),
-
-	PINMUX_IPSR_MSEL(IP5_5_3, SD2_CMD_A, SEL_SDHI2_0),
-	PINMUX_IPSR_MSEL(IP5_5_3, TX2_A, SEL_SCIF2_0),
-	PINMUX_IPSR_GPSR(IP5_5_3, VI0_G5),
-	PINMUX_IPSR_MSEL(IP5_5_3, ET0_ERXD2_B, SEL_ET0_1),
-
-	PINMUX_IPSR_MSEL(IP5_8_6, SD2_DAT0_A, SEL_SDHI2_0),
-	PINMUX_IPSR_MSEL(IP5_8_6, RX3_A, SEL_SCIF3_0),
-	PINMUX_IPSR_GPSR(IP4_8_6, VI0_R0),
-	PINMUX_IPSR_MSEL(IP4_8_6, ET0_ERXD2_B, SEL_ET0_1),
-
-	PINMUX_IPSR_MSEL(IP5_11_9, SD2_DAT1_A, SEL_SDHI2_0),
-	PINMUX_IPSR_MSEL(IP5_11_9, TX3_A, SEL_SCIF3_0),
-	PINMUX_IPSR_GPSR(IP5_11_9, VI0_R1),
-	PINMUX_IPSR_MSEL(IP5_11_9, ET0_MDIO_B, SEL_ET0_1),
-
-	PINMUX_IPSR_MSEL(IP5_14_12, SD2_DAT2_A, SEL_SDHI2_0),
-	PINMUX_IPSR_MSEL(IP5_14_12, RX4_A, SEL_SCIF4_0),
-	PINMUX_IPSR_GPSR(IP5_14_12, VI0_R2),
-	PINMUX_IPSR_MSEL(IP5_14_12, ET0_LINK_B, SEL_ET0_CTL_1),
-
-	PINMUX_IPSR_MSEL(IP5_17_15, SD2_DAT3_A, SEL_SDHI2_0),
-	PINMUX_IPSR_MSEL(IP5_17_15, TX4_A, SEL_SCIF4_0),
-	PINMUX_IPSR_GPSR(IP5_17_15, VI0_R3),
-	PINMUX_IPSR_MSEL(IP5_17_15, ET0_MAGIC_B, SEL_ET0_CTL_1),
-
-	PINMUX_IPSR_MSEL(IP5_20_18, SD2_CD_A, SEL_SDHI2_0),
-	PINMUX_IPSR_MSEL(IP5_20_18, RX5_A, SEL_SCIF5_0),
-	PINMUX_IPSR_GPSR(IP5_20_18, VI0_R4),
-	PINMUX_IPSR_MSEL(IP5_20_18, ET0_PHY_INT_B, SEL_ET0_CTL_1),
-
-	PINMUX_IPSR_MSEL(IP5_22_21, SD2_WP_A, SEL_SDHI2_0),
-	PINMUX_IPSR_MSEL(IP5_22_21, TX5_A, SEL_SCIF5_0),
-	PINMUX_IPSR_GPSR(IP5_22_21, VI0_R5),
-
-	PINMUX_IPSR_GPSR(IP5_24_23, REF125CK),
-	PINMUX_IPSR_GPSR(IP5_24_23, ADTRG),
-	PINMUX_IPSR_MSEL(IP5_24_23, RX5_C, SEL_SCIF5_2),
-	PINMUX_IPSR_GPSR(IP5_26_25, REF50CK),
-	PINMUX_IPSR_MSEL(IP5_26_25, CTS1_E, SEL_SCIF1_3),
-	PINMUX_IPSR_MSEL(IP5_26_25, HCTS0_D, SEL_HSCIF_3),
-
-	/* IPSR6 */
-	PINMUX_IPSR_GPSR(IP6_2_0, DU0_DR0),
-	PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK_B, SEL_SCIF_CLK_1),
-	PINMUX_IPSR_MSEL(IP6_2_0, HRX0_D, SEL_HSCIF_3),
-	PINMUX_IPSR_MSEL(IP6_2_0, IETX_A, SEL_IEBUS_0),
-	PINMUX_IPSR_MSEL(IP6_2_0, TCLKA_A, SEL_MTU2_CLK_0),
-	PINMUX_IPSR_GPSR(IP6_2_0, HIFD00),
-
-	PINMUX_IPSR_GPSR(IP6_5_3, DU0_DR1),
-	PINMUX_IPSR_MSEL(IP6_5_3, SCK0_B, SEL_SCIF0_1),
-	PINMUX_IPSR_MSEL(IP6_5_3, HTX0_D, SEL_HSCIF_3),
-	PINMUX_IPSR_MSEL(IP6_5_3, IERX_A, SEL_IEBUS_0),
-	PINMUX_IPSR_MSEL(IP6_5_3, TCLKB_A, SEL_MTU2_CLK_0),
-	PINMUX_IPSR_GPSR(IP6_5_3, HIFD01),
-
-	PINMUX_IPSR_GPSR(IP6_7_6, DU0_DR2),
-	PINMUX_IPSR_MSEL(IP6_7_6, RX0_B, SEL_SCIF0_1),
-	PINMUX_IPSR_MSEL(IP6_7_6, TCLKC_A, SEL_MTU2_CLK_0),
-	PINMUX_IPSR_GPSR(IP6_7_6, HIFD02),
-
-	PINMUX_IPSR_GPSR(IP6_9_8, DU0_DR3),
-	PINMUX_IPSR_MSEL(IP6_9_8, TX0_B, SEL_SCIF0_1),
-	PINMUX_IPSR_MSEL(IP6_9_8, TCLKD_A, SEL_MTU2_CLK_0),
-	PINMUX_IPSR_GPSR(IP6_9_8, HIFD03),
-
-	PINMUX_IPSR_GPSR(IP6_11_10, DU0_DR4),
-	PINMUX_IPSR_MSEL(IP6_11_10, CTS0_C, SEL_SCIF0_2),
-	PINMUX_IPSR_MSEL(IP6_11_10, TIOC0A_A, SEL_MTU2_CH0_0),
-	PINMUX_IPSR_GPSR(IP6_11_10, HIFD04),
-
-	PINMUX_IPSR_GPSR(IP6_13_12, DU0_DR5),
-	PINMUX_IPSR_MSEL(IP6_13_12, RTS0_C, SEL_SCIF0_1),
-	PINMUX_IPSR_MSEL(IP6_13_12, TIOC0B_A, SEL_MTU2_CH0_0),
-	PINMUX_IPSR_GPSR(IP6_13_12, HIFD05),
-
-	PINMUX_IPSR_GPSR(IP6_15_14, DU0_DR6),
-	PINMUX_IPSR_MSEL(IP6_15_14, SCK1_C, SEL_SCIF1_2),
-	PINMUX_IPSR_MSEL(IP6_15_14, TIOC0C_A, SEL_MTU2_CH0_0),
-	PINMUX_IPSR_GPSR(IP6_15_14, HIFD06),
-
-	PINMUX_IPSR_GPSR(IP6_17_16, DU0_DR7),
-	PINMUX_IPSR_MSEL(IP6_17_16, RX1_C, SEL_SCIF1_2),
-	PINMUX_IPSR_MSEL(IP6_17_16, TIOC0D_A, SEL_MTU2_CH0_0),
-	PINMUX_IPSR_GPSR(IP6_17_16, HIFD07),
-
-	PINMUX_IPSR_GPSR(IP6_20_18, DU0_DG0),
-	PINMUX_IPSR_MSEL(IP6_20_18, TX1_C, SEL_SCIF1_2),
-	PINMUX_IPSR_MSEL(IP6_20_18, HSCK0_D, SEL_HSCIF_3),
-	PINMUX_IPSR_MSEL(IP6_20_18, IECLK_A, SEL_IEBUS_0),
-	PINMUX_IPSR_MSEL(IP6_20_18, TIOC1A_A, SEL_MTU2_CH1_0),
-	PINMUX_IPSR_GPSR(IP6_20_18, HIFD08),
-
-	PINMUX_IPSR_GPSR(IP6_23_21, DU0_DG1),
-	PINMUX_IPSR_MSEL(IP6_23_21, CTS1_C, SEL_SCIF1_2),
-	PINMUX_IPSR_MSEL(IP6_23_21, HRTS0_D, SEL_HSCIF_3),
-	PINMUX_IPSR_MSEL(IP6_23_21, TIOC1B_A, SEL_MTU2_CH1_0),
-	PINMUX_IPSR_GPSR(IP6_23_21, HIFD09),
-
-	/* IPSR7 */
-	PINMUX_IPSR_GPSR(IP7_2_0, DU0_DG2),
-	PINMUX_IPSR_MSEL(IP7_2_0, RTS1_C, SEL_SCIF1_2),
-	PINMUX_IPSR_MSEL(IP7_2_0, RMII0_MDC_B, SEL_RMII_1),
-	PINMUX_IPSR_MSEL(IP7_2_0, TIOC2A_A, SEL_MTU2_CH2_0),
-	PINMUX_IPSR_GPSR(IP7_2_0, HIFD10),
-
-	PINMUX_IPSR_GPSR(IP7_5_3, DU0_DG3),
-	PINMUX_IPSR_MSEL(IP7_5_3, SCK2_C, SEL_SCIF2_2),
-	PINMUX_IPSR_MSEL(IP7_5_3, RMII0_MDIO_B, SEL_RMII_1),
-	PINMUX_IPSR_MSEL(IP7_5_3, TIOC2B_A, SEL_MTU2_CH2_0),
-	PINMUX_IPSR_GPSR(IP7_5_3, HIFD11),
-
-	PINMUX_IPSR_GPSR(IP7_8_6, DU0_DG4),
-	PINMUX_IPSR_MSEL(IP7_8_6, RX2_C, SEL_SCIF2_2),
-	PINMUX_IPSR_MSEL(IP7_8_6, RMII0_CRS_DV_B, SEL_RMII_1),
-	PINMUX_IPSR_MSEL(IP7_8_6, TIOC3A_A, SEL_MTU2_CH3_0),
-	PINMUX_IPSR_GPSR(IP7_8_6, HIFD12),
-
-	PINMUX_IPSR_GPSR(IP7_11_9, DU0_DG5),
-	PINMUX_IPSR_MSEL(IP7_11_9, TX2_C, SEL_SCIF2_2),
-	PINMUX_IPSR_MSEL(IP7_11_9, RMII0_RX_ER_B, SEL_RMII_1),
-	PINMUX_IPSR_MSEL(IP7_11_9, TIOC3B_A, SEL_MTU2_CH3_0),
-	PINMUX_IPSR_GPSR(IP7_11_9, HIFD13),
-
-	PINMUX_IPSR_GPSR(IP7_14_12, DU0_DG6),
-	PINMUX_IPSR_MSEL(IP7_14_12, RX3_C, SEL_SCIF3_2),
-	PINMUX_IPSR_MSEL(IP7_14_12, RMII0_RXD0_B, SEL_RMII_1),
-	PINMUX_IPSR_MSEL(IP7_14_12, TIOC3C_A, SEL_MTU2_CH3_0),
-	PINMUX_IPSR_GPSR(IP7_14_12, HIFD14),
-
-	PINMUX_IPSR_GPSR(IP7_17_15, DU0_DG7),
-	PINMUX_IPSR_MSEL(IP7_17_15, TX3_C, SEL_SCIF3_2),
-	PINMUX_IPSR_MSEL(IP7_17_15, RMII0_RXD1_B, SEL_RMII_1),
-	PINMUX_IPSR_MSEL(IP7_17_15, TIOC3D_A, SEL_MTU2_CH3_0),
-	PINMUX_IPSR_GPSR(IP7_17_15, HIFD15),
-
-	PINMUX_IPSR_GPSR(IP7_20_18, DU0_DB0),
-	PINMUX_IPSR_MSEL(IP7_20_18, RX4_C, SEL_SCIF4_2),
-	PINMUX_IPSR_MSEL(IP7_20_18, RMII0_TXD_EN_B, SEL_RMII_1),
-	PINMUX_IPSR_MSEL(IP7_20_18, TIOC4A_A, SEL_MTU2_CH4_0),
-	PINMUX_IPSR_GPSR(IP7_20_18, HIFCS),
-
-	PINMUX_IPSR_GPSR(IP7_23_21, DU0_DB1),
-	PINMUX_IPSR_MSEL(IP7_23_21, TX4_C, SEL_SCIF4_2),
-	PINMUX_IPSR_MSEL(IP7_23_21, RMII0_TXD0_B, SEL_RMII_1),
-	PINMUX_IPSR_MSEL(IP7_23_21, TIOC4B_A, SEL_MTU2_CH4_0),
-	PINMUX_IPSR_GPSR(IP7_23_21, HIFWR),
-
-	PINMUX_IPSR_GPSR(IP7_26_24, DU0_DB2),
-	PINMUX_IPSR_MSEL(IP7_26_24, RX5_B, SEL_SCIF5_1),
-	PINMUX_IPSR_MSEL(IP7_26_24, RMII0_TXD1_B, SEL_RMII_1),
-	PINMUX_IPSR_MSEL(IP7_26_24, TIOC4C_A, SEL_MTU2_CH4_0),
-
-	PINMUX_IPSR_GPSR(IP7_28_27, DU0_DB3),
-	PINMUX_IPSR_MSEL(IP7_28_27, TX5_B, SEL_SCIF5_1),
-	PINMUX_IPSR_MSEL(IP7_28_27, TIOC4D_A, SEL_MTU2_CH4_0),
-	PINMUX_IPSR_GPSR(IP7_28_27, HIFRD),
-
-	PINMUX_IPSR_GPSR(IP7_30_29, DU0_DB4),
-	PINMUX_IPSR_GPSR(IP7_30_29, HIFINT),
-
-	/* IPSR8 */
-	PINMUX_IPSR_GPSR(IP8_1_0, DU0_DB5),
-	PINMUX_IPSR_GPSR(IP8_1_0, HIFDREQ),
-
-	PINMUX_IPSR_GPSR(IP8_3_2, DU0_DB6),
-	PINMUX_IPSR_GPSR(IP8_3_2, HIFRDY),
-
-	PINMUX_IPSR_GPSR(IP8_5_4, DU0_DB7),
-	PINMUX_IPSR_MSEL(IP8_5_4, SSI_SCK0_B, SEL_SSI0_1),
-	PINMUX_IPSR_MSEL(IP8_5_4, HIFEBL_B, SEL_HIF_1),
-
-	PINMUX_IPSR_GPSR(IP8_7_6, DU0_DOTCLKIN),
-	PINMUX_IPSR_MSEL(IP8_7_6, HSPI_CS0_C, SEL_HSPI_2),
-	PINMUX_IPSR_MSEL(IP8_7_6, SSI_WS0_B, SEL_SSI0_1),
-
-	PINMUX_IPSR_GPSR(IP8_9_8, DU0_DOTCLKOUT),
-	PINMUX_IPSR_MSEL(IP8_9_8, HSPI_CLK0_C, SEL_HSPI_2),
-	PINMUX_IPSR_MSEL(IP8_9_8, SSI_SDATA0_B, SEL_SSI0_1),
-
-	PINMUX_IPSR_GPSR(IP8_11_10, DU0_EXHSYNC_DU0_HSYNC),
-	PINMUX_IPSR_MSEL(IP8_11_10, HSPI_TX0_C, SEL_HSPI_2),
-	PINMUX_IPSR_MSEL(IP8_11_10, SSI_SCK1_B, SEL_SSI1_1),
-
-	PINMUX_IPSR_GPSR(IP8_13_12, DU0_EXVSYNC_DU0_VSYNC),
-	PINMUX_IPSR_MSEL(IP8_13_12, HSPI_RX0_C, SEL_HSPI_2),
-	PINMUX_IPSR_MSEL(IP8_13_12, SSI_WS1_B, SEL_SSI1_1),
-
-	PINMUX_IPSR_GPSR(IP8_15_14, DU0_EXODDF_DU0_ODDF),
-	PINMUX_IPSR_MSEL(IP8_15_14, CAN0_RX_B, SEL_RCAN0_1),
-	PINMUX_IPSR_MSEL(IP8_15_14, HSCK0_B, SEL_HSCIF_1),
-	PINMUX_IPSR_MSEL(IP8_15_14, SSI_SDATA1_B, SEL_SSI1_1),
-
-	PINMUX_IPSR_GPSR(IP8_17_16, DU0_DISP),
-	PINMUX_IPSR_MSEL(IP8_17_16, CAN0_TX_B, SEL_RCAN0_1),
-	PINMUX_IPSR_MSEL(IP8_17_16, HRX0_B, SEL_HSCIF_1),
-	PINMUX_IPSR_MSEL(IP8_17_16, AUDIO_CLKA_B, SEL_AUDIO_CLKA_1),
-
-	PINMUX_IPSR_GPSR(IP8_19_18, DU0_CDE),
-	PINMUX_IPSR_MSEL(IP8_19_18, HTX0_B, SEL_HSCIF_1),
-	PINMUX_IPSR_MSEL(IP8_19_18, AUDIO_CLKB_B, SEL_AUDIO_CLKB_1),
-	PINMUX_IPSR_MSEL(IP8_19_18, LCD_VCPWC_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_MSEL(IP8_22_20, IRQ0_A, SEL_INTC_0),
-	PINMUX_IPSR_MSEL(IP8_22_20, HSPI_TX_B, SEL_HSPI_1),
-	PINMUX_IPSR_MSEL(IP8_22_20, RX3_E, SEL_SCIF3_4),
-	PINMUX_IPSR_GPSR(IP8_22_20, ET0_ERXD0),
-
-	PINMUX_IPSR_MSEL(IP8_25_23, IRQ1_A, SEL_INTC_0),
-	PINMUX_IPSR_MSEL(IP8_25_23, HSPI_RX_B, SEL_HSPI_1),
-	PINMUX_IPSR_MSEL(IP8_25_23, TX3_E, SEL_SCIF3_4),
-	PINMUX_IPSR_GPSR(IP8_25_23, ET0_ERXD1),
-
-	PINMUX_IPSR_MSEL(IP8_27_26, IRQ2_A, SEL_INTC_0),
-	PINMUX_IPSR_MSEL(IP8_27_26, CTS0_A, SEL_SCIF0_0),
-	PINMUX_IPSR_MSEL(IP8_27_26, HCTS0_B, SEL_HSCIF_1),
-	PINMUX_IPSR_MSEL(IP8_27_26, ET0_ERXD2_A, SEL_ET0_0),
-
-	PINMUX_IPSR_MSEL(IP8_29_28, IRQ3_A, SEL_INTC_0),
-	PINMUX_IPSR_MSEL(IP8_29_28, RTS0_A, SEL_SCIF0_0),
-	PINMUX_IPSR_MSEL(IP8_29_28, HRTS0_B, SEL_HSCIF_1),
-	PINMUX_IPSR_MSEL(IP8_29_28, ET0_ERXD3_A, SEL_ET0_0),
-
-	/* IPSR9 */
-	PINMUX_IPSR_MSEL(IP9_1_0, VI1_CLK_A, SEL_VIN1_0),
-	PINMUX_IPSR_MSEL(IP9_1_0, FD0_B, SEL_FLCTL_1),
-	PINMUX_IPSR_MSEL(IP9_1_0, LCD_DATA0_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_MSEL(IP9_3_2, VI1_0_A, SEL_VIN1_0),
-	PINMUX_IPSR_MSEL(IP9_3_2, FD1_B, SEL_FLCTL_1),
-	PINMUX_IPSR_MSEL(IP9_3_2, LCD_DATA1_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_MSEL(IP9_5_4, VI1_1_A, SEL_VIN1_0),
-	PINMUX_IPSR_MSEL(IP9_5_4, FD2_B, SEL_FLCTL_1),
-	PINMUX_IPSR_MSEL(IP9_5_4, LCD_DATA2_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_MSEL(IP9_7_6, VI1_2_A, SEL_VIN1_0),
-	PINMUX_IPSR_MSEL(IP9_7_6, FD3_B, SEL_FLCTL_1),
-	PINMUX_IPSR_MSEL(IP9_7_6, LCD_DATA3_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_MSEL(IP9_9_8, VI1_3_A, SEL_VIN1_0),
-	PINMUX_IPSR_MSEL(IP9_9_8, FD4_B, SEL_FLCTL_1),
-	PINMUX_IPSR_MSEL(IP9_9_8, LCD_DATA4_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_MSEL(IP9_11_10, VI1_4_A, SEL_VIN1_0),
-	PINMUX_IPSR_MSEL(IP9_11_10, FD5_B, SEL_FLCTL_1),
-	PINMUX_IPSR_MSEL(IP9_11_10, LCD_DATA5_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_MSEL(IP9_13_12, VI1_5_A, SEL_VIN1_0),
-	PINMUX_IPSR_MSEL(IP9_13_12, FD6_B, SEL_FLCTL_1),
-	PINMUX_IPSR_MSEL(IP9_13_12, LCD_DATA6_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_MSEL(IP9_15_14, VI1_6_A, SEL_VIN1_0),
-	PINMUX_IPSR_MSEL(IP9_15_14, FD7_B, SEL_FLCTL_1),
-	PINMUX_IPSR_MSEL(IP9_15_14, LCD_DATA7_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_MSEL(IP9_17_16, VI1_7_A, SEL_VIN1_0),
-	PINMUX_IPSR_MSEL(IP9_17_16, FCE_B, SEL_FLCTL_1),
-	PINMUX_IPSR_MSEL(IP9_17_16, LCD_DATA8_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_MSEL(IP9_19_18, SSI_SCK0_A, SEL_SSI0_0),
-	PINMUX_IPSR_MSEL(IP9_19_18, TIOC1A_B, SEL_MTU2_CH1_1),
-	PINMUX_IPSR_MSEL(IP9_19_18, LCD_DATA9_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_MSEL(IP9_21_20, SSI_WS0_A, SEL_SSI0_0),
-	PINMUX_IPSR_MSEL(IP9_21_20, TIOC1B_B, SEL_MTU2_CH1_1),
-	PINMUX_IPSR_MSEL(IP9_21_20, LCD_DATA10_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_MSEL(IP9_23_22, SSI_SDATA0_A, SEL_SSI0_0),
-	PINMUX_IPSR_MSEL(IP9_23_22, VI1_0_B, SEL_VIN1_1),
-	PINMUX_IPSR_MSEL(IP9_23_22, TIOC2A_B, SEL_MTU2_CH2_1),
-	PINMUX_IPSR_MSEL(IP9_23_22, LCD_DATA11_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_MSEL(IP9_25_24, SSI_SCK1_A, SEL_SSI1_0),
-	PINMUX_IPSR_MSEL(IP9_25_24, VI1_1_B, SEL_VIN1_1),
-	PINMUX_IPSR_MSEL(IP9_25_24, TIOC2B_B, SEL_MTU2_CH2_1),
-	PINMUX_IPSR_MSEL(IP9_25_24, LCD_DATA12_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_MSEL(IP9_27_26, SSI_WS1_A, SEL_SSI1_0),
-	PINMUX_IPSR_MSEL(IP9_27_26, VI1_2_B, SEL_VIN1_1),
-	PINMUX_IPSR_MSEL(IP9_27_26, LCD_DATA13_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_MSEL(IP9_29_28, SSI_SDATA1_A, SEL_SSI1_0),
-	PINMUX_IPSR_MSEL(IP9_29_28, VI1_3_B, SEL_VIN1_1),
-	PINMUX_IPSR_MSEL(IP9_29_28, LCD_DATA14_B, SEL_LCDC_1),
-
-	/* IPSE10 */
-	PINMUX_IPSR_GPSR(IP10_2_0, SSI_SCK23),
-	PINMUX_IPSR_MSEL(IP10_2_0, VI1_4_B, SEL_VIN1_1),
-	PINMUX_IPSR_MSEL(IP10_2_0, RX1_D, SEL_SCIF1_3),
-	PINMUX_IPSR_MSEL(IP10_2_0, FCLE_B, SEL_FLCTL_1),
-	PINMUX_IPSR_MSEL(IP10_2_0, LCD_DATA15_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_GPSR(IP10_5_3, SSI_WS23),
-	PINMUX_IPSR_MSEL(IP10_5_3, VI1_5_B, SEL_VIN1_1),
-	PINMUX_IPSR_MSEL(IP10_5_3, TX1_D, SEL_SCIF1_3),
-	PINMUX_IPSR_MSEL(IP10_5_3, HSCK0_C, SEL_HSCIF_2),
-	PINMUX_IPSR_MSEL(IP10_5_3, FALE_B, SEL_FLCTL_1),
-	PINMUX_IPSR_MSEL(IP10_5_3, LCD_DON_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_GPSR(IP10_8_6, SSI_SDATA2),
-	PINMUX_IPSR_MSEL(IP10_8_6, VI1_6_B, SEL_VIN1_1),
-	PINMUX_IPSR_MSEL(IP10_8_6, HRX0_C, SEL_HSCIF_2),
-	PINMUX_IPSR_MSEL(IP10_8_6, FRE_B, SEL_FLCTL_1),
-	PINMUX_IPSR_MSEL(IP10_8_6, LCD_CL1_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_GPSR(IP10_11_9, SSI_SDATA3),
-	PINMUX_IPSR_MSEL(IP10_11_9, VI1_7_B, SEL_VIN1_1),
-	PINMUX_IPSR_MSEL(IP10_11_9, HTX0_C, SEL_HSCIF_2),
-	PINMUX_IPSR_MSEL(IP10_11_9, FWE_B, SEL_FLCTL_1),
-	PINMUX_IPSR_MSEL(IP10_11_9, LCD_CL2_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_MSEL(IP10_14_12, AUDIO_CLKA_A, SEL_AUDIO_CLKA_0),
-	PINMUX_IPSR_MSEL(IP10_14_12, VI1_CLK_B, SEL_VIN1_1),
-	PINMUX_IPSR_MSEL(IP10_14_12, SCK1_D, SEL_SCIF1_3),
-	PINMUX_IPSR_MSEL(IP10_14_12, IECLK_B, SEL_IEBUS_1),
-	PINMUX_IPSR_MSEL(IP10_14_12, LCD_FLM_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_MSEL(IP10_15, AUDIO_CLKB_A, SEL_AUDIO_CLKB_0),
-	PINMUX_IPSR_MSEL(IP10_15, LCD_CLK_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_GPSR(IP10_18_16, AUDIO_CLKC),
-	PINMUX_IPSR_MSEL(IP10_18_16, SCK1_E, SEL_SCIF1_4),
-	PINMUX_IPSR_MSEL(IP10_18_16, HCTS0_C, SEL_HSCIF_2),
-	PINMUX_IPSR_MSEL(IP10_18_16, FRB_B, SEL_FLCTL_1),
-	PINMUX_IPSR_MSEL(IP10_18_16, LCD_VEPWC_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_GPSR(IP10_21_19, AUDIO_CLKOUT),
-	PINMUX_IPSR_MSEL(IP10_21_19, TX1_E, SEL_SCIF1_4),
-	PINMUX_IPSR_MSEL(IP10_21_19, HRTS0_C, SEL_HSCIF_2),
-	PINMUX_IPSR_MSEL(IP10_21_19, FSE_B, SEL_FLCTL_1),
-	PINMUX_IPSR_MSEL(IP10_21_19, LCD_M_DISP_B, SEL_LCDC_1),
-
-	PINMUX_IPSR_MSEL(IP10_22, CAN_CLK_A, SEL_RCAN_CLK_0),
-	PINMUX_IPSR_MSEL(IP10_22, RX4_D, SEL_SCIF4_3),
-
-	PINMUX_IPSR_MSEL(IP10_24_23, CAN0_TX_A, SEL_RCAN0_0),
-	PINMUX_IPSR_MSEL(IP10_24_23, TX4_D, SEL_SCIF4_3),
-	PINMUX_IPSR_GPSR(IP10_24_23, MLB_CLK),
-
-	PINMUX_IPSR_MSEL(IP10_25, CAN1_RX_A, SEL_RCAN1_0),
-	PINMUX_IPSR_MSEL(IP10_25, IRQ1_B, SEL_INTC_1),
-
-	PINMUX_IPSR_MSEL(IP10_27_26, CAN0_RX_A, SEL_RCAN0_0),
-	PINMUX_IPSR_MSEL(IP10_27_26, IRQ0_B, SEL_INTC_1),
-	PINMUX_IPSR_GPSR(IP10_27_26, MLB_SIG),
-
-	PINMUX_IPSR_MSEL(IP10_29_28, CAN1_TX_A, SEL_RCAN1_0),
-	PINMUX_IPSR_MSEL(IP10_29_28, TX5_C, SEL_SCIF1_2),
-	PINMUX_IPSR_GPSR(IP10_29_28, MLB_DAT),
-
-	/* IPSR11 */
-	PINMUX_IPSR_GPSR(IP11_0, SCL1),
-	PINMUX_IPSR_MSEL(IP11_0, SCIF_CLK_C, SEL_SCIF_CLK_2),
-
-	PINMUX_IPSR_GPSR(IP11_1, SDA1),
-	PINMUX_IPSR_MSEL(IP11_0, RX1_E, SEL_SCIF1_4),
-
-	PINMUX_IPSR_GPSR(IP11_2, SDA0),
-	PINMUX_IPSR_MSEL(IP11_2, HIFEBL_A, SEL_HIF_0),
-
-	PINMUX_IPSR_GPSR(IP11_3, SDSELF),
-	PINMUX_IPSR_MSEL(IP11_3, RTS1_E, SEL_SCIF1_3),
-
-	PINMUX_IPSR_MSEL(IP11_6_4, SCIF_CLK_A, SEL_SCIF_CLK_0),
-	PINMUX_IPSR_MSEL(IP11_6_4, HSPI_CLK_A, SEL_HSPI_0),
-	PINMUX_IPSR_GPSR(IP11_6_4, VI0_CLK),
-	PINMUX_IPSR_MSEL(IP11_6_4, RMII0_TXD0_A, SEL_RMII_0),
-	PINMUX_IPSR_GPSR(IP11_6_4, ET0_ERXD4),
-
-	PINMUX_IPSR_MSEL(IP11_9_7, SCK0_A, SEL_SCIF0_0),
-	PINMUX_IPSR_MSEL(IP11_9_7, HSPI_CS_A, SEL_HSPI_0),
-	PINMUX_IPSR_GPSR(IP11_9_7, VI0_CLKENB),
-	PINMUX_IPSR_MSEL(IP11_9_7, RMII0_TXD1_A, SEL_RMII_0),
-	PINMUX_IPSR_GPSR(IP11_9_7, ET0_ERXD5),
-
-	PINMUX_IPSR_MSEL(IP11_11_10, RX0_A, SEL_SCIF0_0),
-	PINMUX_IPSR_MSEL(IP11_11_10, HSPI_RX_A, SEL_HSPI_0),
-	PINMUX_IPSR_MSEL(IP11_11_10, RMII0_RXD0_A, SEL_RMII_0),
-	PINMUX_IPSR_GPSR(IP11_11_10, ET0_ERXD6),
-
-	PINMUX_IPSR_MSEL(IP11_12, TX0_A, SEL_SCIF0_0),
-	PINMUX_IPSR_MSEL(IP11_12, HSPI_TX_A, SEL_HSPI_0),
-
-	PINMUX_IPSR_GPSR(IP11_15_13, PENC1),
-	PINMUX_IPSR_MSEL(IP11_15_13, TX3_D, SEL_SCIF3_3),
-	PINMUX_IPSR_MSEL(IP11_15_13, CAN1_TX_B,  SEL_RCAN1_1),
-	PINMUX_IPSR_MSEL(IP11_15_13, TX5_D, SEL_SCIF5_3),
-	PINMUX_IPSR_MSEL(IP11_15_13, IETX_B, SEL_IEBUS_1),
-
-	PINMUX_IPSR_GPSR(IP11_18_16, USB_OVC1),
-	PINMUX_IPSR_MSEL(IP11_18_16, RX3_D, SEL_SCIF3_3),
-	PINMUX_IPSR_MSEL(IP11_18_16, CAN1_RX_B, SEL_RCAN1_1),
-	PINMUX_IPSR_MSEL(IP11_18_16, RX5_D, SEL_SCIF5_3),
-	PINMUX_IPSR_MSEL(IP11_18_16, IERX_B, SEL_IEBUS_1),
-
-	PINMUX_IPSR_GPSR(IP11_20_19, DREQ0),
-	PINMUX_IPSR_MSEL(IP11_20_19, SD1_CLK_A, SEL_SDHI1_0),
-	PINMUX_IPSR_GPSR(IP11_20_19, ET0_TX_EN),
-
-	PINMUX_IPSR_GPSR(IP11_22_21, DACK0),
-	PINMUX_IPSR_MSEL(IP11_22_21, SD1_DAT3_A, SEL_SDHI1_0),
-	PINMUX_IPSR_GPSR(IP11_22_21, ET0_TX_ER),
-
-	PINMUX_IPSR_GPSR(IP11_25_23, DREQ1),
-	PINMUX_IPSR_MSEL(IP11_25_23, HSPI_CLK_B, SEL_HSPI_1),
-	PINMUX_IPSR_MSEL(IP11_25_23, RX4_B, SEL_SCIF4_1),
-	PINMUX_IPSR_MSEL(IP11_25_23, ET0_PHY_INT_C, SEL_ET0_CTL_0),
-	PINMUX_IPSR_MSEL(IP11_25_23, ET0_TX_CLK_A, SEL_ET0_0),
-
-	PINMUX_IPSR_GPSR(IP11_27_26, DACK1),
-	PINMUX_IPSR_MSEL(IP11_27_26, HSPI_CS_B, SEL_HSPI_1),
-	PINMUX_IPSR_MSEL(IP11_27_26, TX4_B, SEL_SCIF3_1),
-	PINMUX_IPSR_MSEL(IP11_27_26, ET0_RX_CLK_A, SEL_ET0_0),
-
-	PINMUX_IPSR_GPSR(IP11_28, PRESETOUT),
-	PINMUX_IPSR_GPSR(IP11_28, ST_CLKOUT),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	PINMUX_GPIO_GP_ALL(),
-};
-
-#define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-	GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0),
-	GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1),
-	GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0),
-	GPIO_FN(IRQ2_B), GPIO_FN(IRQ3_B),
-
-	/* IPSR0 */
-	GPIO_FN(A0), GPIO_FN(ST0_CLKIN), GPIO_FN(LCD_DATA0_A),
-	GPIO_FN(TCLKA_C),
-	GPIO_FN(A1), GPIO_FN(ST0_REQ), GPIO_FN(LCD_DATA1_A),
-	GPIO_FN(TCLKB_C),
-	GPIO_FN(A2), GPIO_FN(ST0_SYC), GPIO_FN(LCD_DATA2_A),
-	GPIO_FN(TCLKC_C),
-	GPIO_FN(A3), GPIO_FN(ST0_VLD), GPIO_FN(LCD_DATA3_A),
-	GPIO_FN(TCLKD_C),
-	GPIO_FN(A4), GPIO_FN(ST0_D0), GPIO_FN(LCD_DATA4_A),
-	GPIO_FN(TIOC0A_C),
-	GPIO_FN(A5), GPIO_FN(ST0_D1), GPIO_FN(LCD_DATA5_A),
-	GPIO_FN(TIOC0B_C),
-	GPIO_FN(A6), GPIO_FN(ST0_D2), GPIO_FN(LCD_DATA6_A),
-	GPIO_FN(TIOC0C_C),
-	GPIO_FN(A7), GPIO_FN(ST0_D3), GPIO_FN(LCD_DATA7_A),
-	GPIO_FN(TIOC0D_C),
-	GPIO_FN(A8), GPIO_FN(ST0_D4), GPIO_FN(LCD_DATA8_A),
-	GPIO_FN(TIOC1A_C),
-	GPIO_FN(A9), GPIO_FN(ST0_D5), GPIO_FN(LCD_DATA9_A),
-	GPIO_FN(TIOC1B_C),
-	GPIO_FN(A10), GPIO_FN(ST0_D6), GPIO_FN(LCD_DATA10_A),
-	GPIO_FN(TIOC2A_C),
-	GPIO_FN(A11), GPIO_FN(ST0_D7), GPIO_FN(LCD_DATA11_A),
-	GPIO_FN(TIOC2B_C),
-	GPIO_FN(A12), GPIO_FN(LCD_DATA12_A), GPIO_FN(TIOC3A_C),
-	GPIO_FN(A13), GPIO_FN(LCD_DATA13_A), GPIO_FN(TIOC3B_C),
-	GPIO_FN(A14), GPIO_FN(LCD_DATA14_A), GPIO_FN(TIOC3C_C),
-	GPIO_FN(A15), GPIO_FN(ST0_VCO_CLKIN), GPIO_FN(LCD_DATA15_A),
-	GPIO_FN(TIOC3D_C),
-
-	/* IPSR1 */
-	GPIO_FN(A16), GPIO_FN(ST0_PWM), GPIO_FN(LCD_DON_A),
-	GPIO_FN(TIOC4A_C),
-	GPIO_FN(A17), GPIO_FN(ST1_VCO_CLKIN), GPIO_FN(LCD_CL1_A),
-	GPIO_FN(TIOC4B_C),
-	GPIO_FN(A18), GPIO_FN(ST1_PWM), GPIO_FN(LCD_CL2_A),
-	GPIO_FN(TIOC4C_C),
-	GPIO_FN(A19), GPIO_FN(ST1_CLKIN), GPIO_FN(LCD_CLK_A),
-	GPIO_FN(TIOC4D_C),
-	GPIO_FN(A20), GPIO_FN(ST1_REQ), GPIO_FN(LCD_FLM_A),
-	GPIO_FN(A21), GPIO_FN(ST1_SYC), GPIO_FN(LCD_VCPWC_A),
-	GPIO_FN(A22), GPIO_FN(ST1_VLD), GPIO_FN(LCD_VEPWC_A),
-	GPIO_FN(A23), GPIO_FN(ST1_D0), GPIO_FN(LCD_M_DISP_A),
-	GPIO_FN(A24), GPIO_FN(RX2_D), GPIO_FN(ST1_D1),
-	GPIO_FN(A25), GPIO_FN(TX2_D), GPIO_FN(ST1_D2),
-	GPIO_FN(D0), GPIO_FN(SD0_DAT0_A), GPIO_FN(MMC_D0_A),
-	GPIO_FN(ST1_D3), GPIO_FN(FD0_A),
-	GPIO_FN(D1), GPIO_FN(SD0_DAT1_A), GPIO_FN(MMC_D1_A),
-	GPIO_FN(ST1_D4), GPIO_FN(FD1_A),
-	GPIO_FN(D2), GPIO_FN(SD0_DAT2_A), GPIO_FN(MMC_D2_A),
-	GPIO_FN(ST1_D5), GPIO_FN(FD2_A),
-	GPIO_FN(D3), GPIO_FN(SD0_DAT3_A), GPIO_FN(MMC_D3_A),
-	GPIO_FN(ST1_D6), GPIO_FN(FD3_A),
-
-	/* IPSR2 */
-	GPIO_FN(D4), GPIO_FN(SD0_CD_A), GPIO_FN(MMC_D4_A), GPIO_FN(ST1_D7),
-	GPIO_FN(FD4_A),
-	GPIO_FN(D5), GPIO_FN(SD0_WP_A), GPIO_FN(MMC_D5_A), GPIO_FN(FD5_A),
-	GPIO_FN(D6), GPIO_FN(RSPI_RSPCK_A), GPIO_FN(MMC_D6_A),
-		GPIO_FN(QSPCLK_A),
-	GPIO_FN(FD6_A),
-	GPIO_FN(D7), GPIO_FN(RSPI_SSL_A), GPIO_FN(MMC_D7_A), GPIO_FN(QSSL_A),
-	GPIO_FN(FD7_A),
-	GPIO_FN(D8), GPIO_FN(SD0_CLK_A), GPIO_FN(MMC_CLK_A), GPIO_FN(QIO2_A),
-	GPIO_FN(FCE_A), GPIO_FN(ET0_GTX_CLK_B),
-	GPIO_FN(D9), GPIO_FN(SD0_CMD_A), GPIO_FN(MMC_CMD_A), GPIO_FN(QIO3_A),
-	GPIO_FN(FCLE_A), GPIO_FN(ET0_ETXD1_B),
-	GPIO_FN(D10), GPIO_FN(RSPI_MOSI_A), GPIO_FN(QMO_QIO0_A),
-		GPIO_FN(FALE_A), GPIO_FN(ET0_ETXD2_B),
-	GPIO_FN(D11), GPIO_FN(RSPI_MISO_A), GPIO_FN(QMI_QIO1_A), GPIO_FN(FRE_A),
-		GPIO_FN(ET0_ETXD3_B),
-	GPIO_FN(D12), GPIO_FN(FWE_A), GPIO_FN(ET0_ETXD5_B),
-	GPIO_FN(D13), GPIO_FN(RX2_B), GPIO_FN(FRB_A), GPIO_FN(ET0_ETXD6_B),
-	GPIO_FN(D14), GPIO_FN(TX2_B), GPIO_FN(FSE_A), GPIO_FN(ET0_TX_CLK_B),
-
-	/* IPSR3 */
-	GPIO_FN(D15), GPIO_FN(SCK2_B),
-	GPIO_FN(CS1_A26), GPIO_FN(QIO3_B),
-	GPIO_FN(EX_CS1), GPIO_FN(RX3_B), GPIO_FN(ATACS0), GPIO_FN(QIO2_B),
-	GPIO_FN(ET0_ETXD0),
-	GPIO_FN(EX_CS2), GPIO_FN(TX3_B), GPIO_FN(ATACS1), GPIO_FN(QSPCLK_B),
-	GPIO_FN(ET0_GTX_CLK_A),
-	GPIO_FN(EX_CS3), GPIO_FN(SD1_CD_A), GPIO_FN(ATARD), GPIO_FN(QMO_QIO0_B),
-	GPIO_FN(ET0_ETXD1_A),
-	GPIO_FN(EX_CS4), GPIO_FN(SD1_WP_A), GPIO_FN(ATAWR), GPIO_FN(QMI_QIO1_B),
-	GPIO_FN(ET0_ETXD2_A),
-	GPIO_FN(EX_CS5), GPIO_FN(SD1_CMD_A), GPIO_FN(ATADIR), GPIO_FN(QSSL_B),
-	GPIO_FN(ET0_ETXD3_A),
-	GPIO_FN(RD_WR), GPIO_FN(TCLK0), GPIO_FN(CAN_CLK_B), GPIO_FN(ET0_ETXD4),
-	GPIO_FN(EX_WAIT0), GPIO_FN(TCLK1_B),
-	GPIO_FN(EX_WAIT1), GPIO_FN(SD1_DAT0_A), GPIO_FN(DREQ2),
-		GPIO_FN(CAN1_TX_C), GPIO_FN(ET0_LINK_C), GPIO_FN(ET0_ETXD5_A),
-	GPIO_FN(EX_WAIT2), GPIO_FN(SD1_DAT1_A), GPIO_FN(DACK2),
-		GPIO_FN(CAN1_RX_C), GPIO_FN(ET0_MAGIC_C), GPIO_FN(ET0_ETXD6_A),
-	GPIO_FN(DRACK0), GPIO_FN(SD1_DAT2_A), GPIO_FN(ATAG), GPIO_FN(TCLK1_A),
-	GPIO_FN(ET0_ETXD7),
-
-	/* IPSR4 */
-	GPIO_FN(HCTS0_A), GPIO_FN(CTS1_A), GPIO_FN(VI0_FIELD),
-		GPIO_FN(RMII0_RXD1_A), GPIO_FN(ET0_ERXD7),
-	GPIO_FN(HRTS0_A), GPIO_FN(RTS1_A), GPIO_FN(VI0_HSYNC),
-		GPIO_FN(RMII0_TXD_EN_A), GPIO_FN(ET0_RX_DV),
-	GPIO_FN(HSCK0_A), GPIO_FN(SCK1_A), GPIO_FN(VI0_VSYNC),
-		GPIO_FN(RMII0_RX_ER_A), GPIO_FN(ET0_RX_ER),
-	GPIO_FN(HRX0_A), GPIO_FN(RX1_A), GPIO_FN(VI0_DATA0_VI0_B0),
-		GPIO_FN(RMII0_CRS_DV_A), GPIO_FN(ET0_CRS),
-	GPIO_FN(HTX0_A), GPIO_FN(TX1_A), GPIO_FN(VI0_DATA1_VI0_B1),
-		GPIO_FN(RMII0_MDC_A), GPIO_FN(ET0_COL),
-	GPIO_FN(CTS0_B), GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(RMII0_MDIO_A),
-		GPIO_FN(ET0_MDC),
-	GPIO_FN(RTS0_B), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(ET0_MDIO_A),
-	GPIO_FN(SCK1_B), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(ET0_LINK_A),
-	GPIO_FN(RX1_B), GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(ET0_MAGIC_A),
-	GPIO_FN(TX1_B), GPIO_FN(VI0_DATA6_VI0_G0), GPIO_FN(ET0_PHY_INT_A),
-	GPIO_FN(CTS1_B), GPIO_FN(VI0_DATA7_VI0_G1),
-	GPIO_FN(RTS1_B), GPIO_FN(VI0_G2),
-	GPIO_FN(SCK2_A), GPIO_FN(VI0_G3),
-
-	/* IPSR5 */
-	GPIO_FN(REF50CK), GPIO_FN(CTS1_E), GPIO_FN(HCTS0_D),
-	GPIO_FN(REF125CK), GPIO_FN(ADTRG), GPIO_FN(RX5_C),
-	GPIO_FN(SD2_WP_A), GPIO_FN(TX5_A), GPIO_FN(VI0_R5),
-	GPIO_FN(SD2_CD_A), GPIO_FN(RX5_A), GPIO_FN(VI0_R4),
-		GPIO_FN(ET0_PHY_INT_B),
-	GPIO_FN(SD2_DAT3_A), GPIO_FN(TX4_A), GPIO_FN(VI0_R3),
-		GPIO_FN(ET0_MAGIC_B),
-	GPIO_FN(SD2_DAT2_A), GPIO_FN(RX4_A), GPIO_FN(VI0_R2),
-		GPIO_FN(ET0_LINK_B),
-	GPIO_FN(SD2_DAT1_A), GPIO_FN(TX3_A), GPIO_FN(VI0_R1),
-		GPIO_FN(ET0_MDIO_B),
-	GPIO_FN(SD2_DAT0_A), GPIO_FN(RX3_A), GPIO_FN(VI0_R0),
-		GPIO_FN(ET0_ERXD3_B),
-	GPIO_FN(SD2_CMD_A), GPIO_FN(TX2_A), GPIO_FN(VI0_G5),
-		GPIO_FN(ET0_ERXD2_B),
-	GPIO_FN(SD2_CLK_A), GPIO_FN(RX2_A), GPIO_FN(VI0_G4),
-		GPIO_FN(ET0_RX_CLK_B),
-
-	/* IPSR6 */
-	GPIO_FN(DU0_DG1), GPIO_FN(CTS1_C), GPIO_FN(HRTS0_D),
-		GPIO_FN(TIOC1B_A), GPIO_FN(HIFD09),
-	GPIO_FN(DU0_DG0), GPIO_FN(TX1_C), GPIO_FN(HSCK0_D),
-		GPIO_FN(IECLK_A), GPIO_FN(TIOC1A_A), GPIO_FN(HIFD08),
-	GPIO_FN(DU0_DR7), GPIO_FN(RX1_C), GPIO_FN(TIOC0D_A),
-		GPIO_FN(HIFD07),
-	GPIO_FN(DU0_DR6), GPIO_FN(SCK1_C), GPIO_FN(TIOC0C_A),
-		GPIO_FN(HIFD06),
-	GPIO_FN(DU0_DR5), GPIO_FN(RTS0_C), GPIO_FN(TIOC0B_A),
-		GPIO_FN(HIFD05),
-	GPIO_FN(DU0_DR4), GPIO_FN(CTS0_C), GPIO_FN(TIOC0A_A),
-		GPIO_FN(HIFD04),
-	GPIO_FN(DU0_DR3), GPIO_FN(TX0_B), GPIO_FN(TCLKD_A), GPIO_FN(HIFD03),
-	GPIO_FN(DU0_DR2), GPIO_FN(RX0_B), GPIO_FN(TCLKC_A), GPIO_FN(HIFD02),
-	GPIO_FN(DU0_DR1), GPIO_FN(SCK0_B), GPIO_FN(HTX0_D),
-		GPIO_FN(IERX_A), GPIO_FN(TCLKB_A), GPIO_FN(HIFD01),
-	GPIO_FN(DU0_DR0), GPIO_FN(SCIF_CLK_B), GPIO_FN(HRX0_D),
-		GPIO_FN(IETX_A), GPIO_FN(TCLKA_A), GPIO_FN(HIFD00),
-
-	/* IPSR7 */
-	GPIO_FN(DU0_DB4), GPIO_FN(HIFINT),
-	GPIO_FN(DU0_DB3), GPIO_FN(TX5_B), GPIO_FN(TIOC4D_A), GPIO_FN(HIFRD),
-	GPIO_FN(DU0_DB2), GPIO_FN(RX5_B), GPIO_FN(RMII0_TXD1_B),
-		GPIO_FN(TIOC4C_A), GPIO_FN(HIFWR),
-	GPIO_FN(DU0_DB1), GPIO_FN(TX4_C), GPIO_FN(RMII0_TXD0_B),
-		GPIO_FN(TIOC4B_A), GPIO_FN(HIFRS),
-	GPIO_FN(DU0_DB0), GPIO_FN(RX4_C), GPIO_FN(RMII0_TXD_EN_B),
-		GPIO_FN(TIOC4A_A), GPIO_FN(HIFCS),
-	GPIO_FN(DU0_DG7), GPIO_FN(TX3_C), GPIO_FN(RMII0_RXD1_B),
-		GPIO_FN(TIOC3D_A), GPIO_FN(HIFD15),
-	GPIO_FN(DU0_DG6), GPIO_FN(RX3_C), GPIO_FN(RMII0_RXD0_B),
-		GPIO_FN(TIOC3C_A), GPIO_FN(HIFD14),
-	GPIO_FN(DU0_DG5), GPIO_FN(TX2_C), GPIO_FN(RMII0_RX_ER_B),
-		GPIO_FN(TIOC3B_A), GPIO_FN(HIFD13),
-	GPIO_FN(DU0_DG4), GPIO_FN(RX2_C), GPIO_FN(RMII0_CRS_DV_B),
-		GPIO_FN(TIOC3A_A), GPIO_FN(HIFD12),
-	GPIO_FN(DU0_DG3), GPIO_FN(SCK2_C), GPIO_FN(RMII0_MDIO_B),
-		GPIO_FN(TIOC2B_A), GPIO_FN(HIFD11),
-	GPIO_FN(DU0_DG2), GPIO_FN(RTS1_C), GPIO_FN(RMII0_MDC_B),
-		GPIO_FN(TIOC2A_A), GPIO_FN(HIFD10),
-
-	/* IPSR8 */
-	GPIO_FN(IRQ3_A), GPIO_FN(RTS0_A), GPIO_FN(HRTS0_B),
-		GPIO_FN(ET0_ERXD3_A),
-	GPIO_FN(IRQ2_A), GPIO_FN(CTS0_A), GPIO_FN(HCTS0_B),
-		GPIO_FN(ET0_ERXD2_A),
-	GPIO_FN(IRQ1_A), GPIO_FN(HSPI_RX_B), GPIO_FN(TX3_E),
-		GPIO_FN(ET0_ERXD1),
-	GPIO_FN(IRQ0_A), GPIO_FN(HSPI_TX_B), GPIO_FN(RX3_E),
-		GPIO_FN(ET0_ERXD0),
-	GPIO_FN(DU0_CDE), GPIO_FN(HTX0_B), GPIO_FN(AUDIO_CLKB_B),
-		GPIO_FN(LCD_VCPWC_B),
-	GPIO_FN(DU0_DISP), GPIO_FN(CAN0_TX_B), GPIO_FN(HRX0_B),
-		GPIO_FN(AUDIO_CLKA_B),
-	GPIO_FN(DU0_EXODDF_DU0_ODDF), GPIO_FN(CAN0_RX_B), GPIO_FN(HSCK0_B),
-		GPIO_FN(SSI_SDATA1_B),
-	GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(HSPI_RX0_C),
-		GPIO_FN(SSI_WS1_B),
-	GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(HSPI_TX0_C),
-		GPIO_FN(SSI_SCK1_B),
-	GPIO_FN(DU0_DOTCLKOUT), GPIO_FN(HSPI_CLK0_C),
-		GPIO_FN(SSI_SDATA0_B),
-	GPIO_FN(DU0_DOTCLKIN), GPIO_FN(HSPI_CS0_C),
-		GPIO_FN(SSI_WS0_B),
-	GPIO_FN(DU0_DB7), GPIO_FN(SSI_SCK0_B), GPIO_FN(HIFEBL_B),
-	GPIO_FN(DU0_DB6), GPIO_FN(HIFRDY),
-	GPIO_FN(DU0_DB5), GPIO_FN(HIFDREQ),
-
-	/* IPSR9 */
-	GPIO_FN(SSI_SDATA1_A), GPIO_FN(VI1_3_B), GPIO_FN(LCD_DATA14_B),
-	GPIO_FN(SSI_WS1_A), GPIO_FN(VI1_2_B), GPIO_FN(LCD_DATA13_B),
-	GPIO_FN(SSI_SCK1_A), GPIO_FN(VI1_1_B), GPIO_FN(TIOC2B_B),
-		GPIO_FN(LCD_DATA12_B),
-	GPIO_FN(SSI_SDATA0_A), GPIO_FN(VI1_0_B), GPIO_FN(TIOC2A_B),
-		GPIO_FN(LCD_DATA11_B),
-	GPIO_FN(SSI_WS0_A), GPIO_FN(TIOC1B_B), GPIO_FN(LCD_DATA10_B),
-	GPIO_FN(SSI_SCK0_A), GPIO_FN(TIOC1A_B), GPIO_FN(LCD_DATA9_B),
-	GPIO_FN(VI1_7_A), GPIO_FN(FCE_B), GPIO_FN(LCD_DATA8_B),
-	GPIO_FN(VI1_6_A), GPIO_FN(FD7_B), GPIO_FN(LCD_DATA7_B),
-	GPIO_FN(VI1_5_A), GPIO_FN(FD6_B), GPIO_FN(LCD_DATA6_B),
-	GPIO_FN(VI1_4_A), GPIO_FN(FD5_B), GPIO_FN(LCD_DATA5_B),
-	GPIO_FN(VI1_3_A), GPIO_FN(FD4_B), GPIO_FN(LCD_DATA4_B),
-	GPIO_FN(VI1_2_A), GPIO_FN(FD3_B), GPIO_FN(LCD_DATA3_B),
-	GPIO_FN(VI1_1_A), GPIO_FN(FD2_B), GPIO_FN(LCD_DATA2_B),
-	GPIO_FN(VI1_0_A), GPIO_FN(FD1_B), GPIO_FN(LCD_DATA1_B),
-	GPIO_FN(VI1_CLK_A), GPIO_FN(FD0_B), GPIO_FN(LCD_DATA0_B),
-
-	/* IPSR10 */
-	GPIO_FN(CAN1_TX_A), GPIO_FN(TX5_C), GPIO_FN(MLB_DAT),
-	GPIO_FN(CAN0_RX_A), GPIO_FN(IRQ0_B), GPIO_FN(MLB_SIG),
-	GPIO_FN(CAN1_RX_A), GPIO_FN(IRQ1_B),
-	GPIO_FN(CAN0_TX_A), GPIO_FN(TX4_D), GPIO_FN(MLB_CLK),
-	GPIO_FN(CAN_CLK_A), GPIO_FN(RX4_D),
-	GPIO_FN(AUDIO_CLKOUT), GPIO_FN(TX1_E), GPIO_FN(HRTS0_C),
-		GPIO_FN(FSE_B), GPIO_FN(LCD_M_DISP_B),
-	GPIO_FN(AUDIO_CLKC), GPIO_FN(SCK1_E), GPIO_FN(HCTS0_C),
-		GPIO_FN(FRB_B), GPIO_FN(LCD_VEPWC_B),
-	GPIO_FN(AUDIO_CLKB_A), GPIO_FN(LCD_CLK_B),
-	GPIO_FN(AUDIO_CLKA_A), GPIO_FN(VI1_CLK_B), GPIO_FN(SCK1_D),
-		GPIO_FN(IECLK_B), GPIO_FN(LCD_FLM_B),
-	GPIO_FN(SSI_SDATA3), GPIO_FN(VI1_7_B), GPIO_FN(HTX0_C),
-		GPIO_FN(FWE_B), GPIO_FN(LCD_CL2_B),
-	GPIO_FN(SSI_SDATA2), GPIO_FN(VI1_6_B), GPIO_FN(HRX0_C),
-		GPIO_FN(FRE_B), GPIO_FN(LCD_CL1_B),
-	GPIO_FN(SSI_WS23), GPIO_FN(VI1_5_B), GPIO_FN(TX1_D),
-		GPIO_FN(HSCK0_C), GPIO_FN(FALE_B), GPIO_FN(LCD_DON_B),
-	GPIO_FN(SSI_SCK23), GPIO_FN(VI1_4_B), GPIO_FN(RX1_D),
-		GPIO_FN(FCLE_B), GPIO_FN(LCD_DATA15_B),
-
-	/* IPSR11 */
-	GPIO_FN(PRESETOUT), GPIO_FN(ST_CLKOUT),
-	GPIO_FN(DACK1), GPIO_FN(HSPI_CS_B), GPIO_FN(TX4_B),
-		GPIO_FN(ET0_RX_CLK_A),
-	GPIO_FN(DREQ1), GPIO_FN(HSPI_CLK_B), GPIO_FN(RX4_B),
-		GPIO_FN(ET0_PHY_INT_C), GPIO_FN(ET0_TX_CLK_A),
-	GPIO_FN(DACK0), GPIO_FN(SD1_DAT3_A), GPIO_FN(ET0_TX_ER),
-	GPIO_FN(DREQ0), GPIO_FN(SD1_CLK_A), GPIO_FN(ET0_TX_EN),
-	GPIO_FN(USB_OVC1), GPIO_FN(RX3_D), GPIO_FN(CAN1_RX_B),
-		GPIO_FN(RX5_D), GPIO_FN(IERX_B),
-	GPIO_FN(PENC1), GPIO_FN(TX3_D), GPIO_FN(CAN1_TX_B),
-		GPIO_FN(TX5_D), GPIO_FN(IETX_B),
-	GPIO_FN(TX0_A), GPIO_FN(HSPI_TX_A),
-	GPIO_FN(RX0_A), GPIO_FN(HSPI_RX_A), GPIO_FN(RMII0_RXD0_A),
-		GPIO_FN(ET0_ERXD6),
-	GPIO_FN(SCK0_A), GPIO_FN(HSPI_CS_A), GPIO_FN(VI0_CLKENB),
-		GPIO_FN(RMII0_TXD1_A), GPIO_FN(ET0_ERXD5),
-	GPIO_FN(SCIF_CLK_A), GPIO_FN(HSPI_CLK_A), GPIO_FN(VI0_CLK),
-		GPIO_FN(RMII0_TXD0_A), GPIO_FN(ET0_ERXD4),
-	GPIO_FN(SDSELF), GPIO_FN(RTS1_E),
-	GPIO_FN(SDA0), GPIO_FN(HIFEBL_A),
-	GPIO_FN(SDA1), GPIO_FN(RX1_E),
-	GPIO_FN(SCL1), GPIO_FN(SCIF_CLK_C),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	{ PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1, GROUP(
-		GP_0_31_FN, FN_IP2_2_0,
-		GP_0_30_FN, FN_IP1_31_29,
-		GP_0_29_FN, FN_IP1_28_26,
-		GP_0_28_FN, FN_IP1_25_23,
-		GP_0_27_FN, FN_IP1_22_20,
-		GP_0_26_FN, FN_IP1_19_18,
-		GP_0_25_FN, FN_IP1_17_16,
-		GP_0_24_FN, FN_IP0_5_4,
-		GP_0_23_FN, FN_IP0_3_2,
-		GP_0_22_FN, FN_IP0_1_0,
-		GP_0_21_FN, FN_IP11_28,
-		GP_0_20_FN, FN_IP1_7_6,
-		GP_0_19_FN, FN_IP1_5_4,
-		GP_0_18_FN, FN_IP1_3_2,
-		GP_0_17_FN, FN_IP1_1_0,
-		GP_0_16_FN, FN_IP0_31_30,
-		GP_0_15_FN, FN_IP0_29_28,
-		GP_0_14_FN, FN_IP0_27_26,
-		GP_0_13_FN, FN_IP0_25_24,
-		GP_0_12_FN, FN_IP0_23_22,
-		GP_0_11_FN, FN_IP0_21_20,
-		GP_0_10_FN, FN_IP0_19_18,
-		GP_0_9_FN, FN_IP0_17_16,
-		GP_0_8_FN, FN_IP0_15_14,
-		GP_0_7_FN, FN_IP0_13_12,
-		GP_0_6_FN, FN_IP0_11_10,
-		GP_0_5_FN, FN_IP0_9_8,
-		GP_0_4_FN, FN_IP0_7_6,
-		GP_0_3_FN, FN_IP1_15_14,
-		GP_0_2_FN, FN_IP1_13_12,
-		GP_0_1_FN, FN_IP1_11_10,
-		GP_0_0_FN, FN_IP1_9_8 ))
-	},
-	{ PINMUX_CFG_REG("GPSR1", 0xFFFC0008, 32, 1, GROUP(
-		GP_1_31_FN, FN_IP11_25_23,
-		GP_1_30_FN, FN_IP2_13_11,
-		GP_1_29_FN, FN_IP2_10_8,
-		GP_1_28_FN, FN_IP2_7_5,
-		GP_1_27_FN, FN_IP3_26_24,
-		GP_1_26_FN, FN_IP3_23_21,
-		GP_1_25_FN, FN_IP2_4_3,
-		GP_1_24_FN, FN_WE1,
-		GP_1_23_FN, FN_WE0,
-		GP_1_22_FN, FN_IP3_19_18,
-		GP_1_21_FN, FN_RD,
-		GP_1_20_FN, FN_IP3_17_15,
-		GP_1_19_FN, FN_IP3_14_12,
-		GP_1_18_FN, FN_IP3_11_9,
-		GP_1_17_FN, FN_IP3_8_6,
-		GP_1_16_FN, FN_IP3_5_3,
-		GP_1_15_FN, FN_EX_CS0,
-		GP_1_14_FN, FN_IP3_2,
-		GP_1_13_FN, FN_CS0,
-		GP_1_12_FN, FN_BS,
-		GP_1_11_FN, FN_CLKOUT,
-		GP_1_10_FN, FN_IP3_1_0,
-		GP_1_9_FN, FN_IP2_30_28,
-		GP_1_8_FN, FN_IP2_27_25,
-		GP_1_7_FN, FN_IP2_24_23,
-		GP_1_6_FN, FN_IP2_22_20,
-		GP_1_5_FN, FN_IP2_19_17,
-		GP_1_4_FN, FN_IP2_16_14,
-		GP_1_3_FN, FN_IP11_22_21,
-		GP_1_2_FN, FN_IP11_20_19,
-		GP_1_1_FN, FN_IP3_29_27,
-		GP_1_0_FN, FN_IP3_20 ))
-	},
-	{ PINMUX_CFG_REG("GPSR2", 0xFFFC000C, 32, 1, GROUP(
-		GP_2_31_FN, FN_IP4_31_30,
-		GP_2_30_FN, FN_IP5_2_0,
-		GP_2_29_FN, FN_IP5_5_3,
-		GP_2_28_FN, FN_IP5_8_6,
-		GP_2_27_FN, FN_IP5_11_9,
-		GP_2_26_FN, FN_IP5_14_12,
-		GP_2_25_FN, FN_IP5_17_15,
-		GP_2_24_FN, FN_IP5_20_18,
-		GP_2_23_FN, FN_IP5_22_21,
-		GP_2_22_FN, FN_IP5_24_23,
-		GP_2_21_FN, FN_IP5_26_25,
-		GP_2_20_FN, FN_IP4_29_28,
-		GP_2_19_FN, FN_IP4_27_26,
-		GP_2_18_FN, FN_IP4_25_24,
-		GP_2_17_FN, FN_IP4_23_22,
-		GP_2_16_FN, FN_IP4_21_20,
-		GP_2_15_FN, FN_IP4_19_18,
-		GP_2_14_FN, FN_IP4_17_15,
-		GP_2_13_FN, FN_IP4_14_12,
-		GP_2_12_FN, FN_IP4_11_9,
-		GP_2_11_FN, FN_IP4_8_6,
-		GP_2_10_FN, FN_IP4_5_3,
-		GP_2_9_FN, FN_IP8_27_26,
-		GP_2_8_FN, FN_IP11_12,
-		GP_2_7_FN, FN_IP8_25_23,
-		GP_2_6_FN, FN_IP8_22_20,
-		GP_2_5_FN, FN_IP11_27_26,
-		GP_2_4_FN, FN_IP8_29_28,
-		GP_2_3_FN, FN_IP4_2_0,
-		GP_2_2_FN, FN_IP11_11_10,
-		GP_2_1_FN, FN_IP11_9_7,
-		GP_2_0_FN, FN_IP11_6_4 ))
-	},
-	{ PINMUX_CFG_REG("GPSR3", 0xFFFC0010, 32, 1, GROUP(
-		GP_3_31_FN, FN_IP9_1_0,
-		GP_3_30_FN, FN_IP8_19_18,
-		GP_3_29_FN, FN_IP8_17_16,
-		GP_3_28_FN, FN_IP8_15_14,
-		GP_3_27_FN, FN_IP8_13_12,
-		GP_3_26_FN, FN_IP8_11_10,
-		GP_3_25_FN, FN_IP8_9_8,
-		GP_3_24_FN, FN_IP8_7_6,
-		GP_3_23_FN, FN_IP8_5_4,
-		GP_3_22_FN, FN_IP8_3_2,
-		GP_3_21_FN, FN_IP8_1_0,
-		GP_3_20_FN, FN_IP7_30_29,
-		GP_3_19_FN, FN_IP7_28_27,
-		GP_3_18_FN, FN_IP7_26_24,
-		GP_3_17_FN, FN_IP7_23_21,
-		GP_3_16_FN, FN_IP7_20_18,
-		GP_3_15_FN, FN_IP7_17_15,
-		GP_3_14_FN, FN_IP7_14_12,
-		GP_3_13_FN, FN_IP7_11_9,
-		GP_3_12_FN, FN_IP7_8_6,
-		GP_3_11_FN, FN_IP7_5_3,
-		GP_3_10_FN, FN_IP7_2_0,
-		GP_3_9_FN, FN_IP6_23_21,
-		GP_3_8_FN, FN_IP6_20_18,
-		GP_3_7_FN, FN_IP6_17_16,
-		GP_3_6_FN, FN_IP6_15_14,
-		GP_3_5_FN, FN_IP6_13_12,
-		GP_3_4_FN, FN_IP6_11_10,
-		GP_3_3_FN, FN_IP6_9_8,
-		GP_3_2_FN, FN_IP6_7_6,
-		GP_3_1_FN, FN_IP6_5_3,
-		GP_3_0_FN, FN_IP6_2_0 ))
-	},
-
-	{ PINMUX_CFG_REG("GPSR4", 0xFFFC0014, 32, 1, GROUP(
-		GP_4_31_FN, FN_IP10_24_23,
-		GP_4_30_FN, FN_IP10_22,
-		GP_4_29_FN, FN_IP11_18_16,
-		GP_4_28_FN, FN_USB_OVC0,
-		GP_4_27_FN, FN_IP11_15_13,
-		GP_4_26_FN, FN_PENC0,
-		GP_4_25_FN, FN_IP11_2,
-		GP_4_24_FN, FN_SCL0,
-		GP_4_23_FN, FN_IP11_1,
-		GP_4_22_FN, FN_IP11_0,
-		GP_4_21_FN, FN_IP10_21_19,
-		GP_4_20_FN, FN_IP10_18_16,
-		GP_4_19_FN, FN_IP10_15,
-		GP_4_18_FN, FN_IP10_14_12,
-		GP_4_17_FN, FN_IP10_11_9,
-		GP_4_16_FN, FN_IP10_8_6,
-		GP_4_15_FN, FN_IP10_5_3,
-		GP_4_14_FN, FN_IP10_2_0,
-		GP_4_13_FN, FN_IP9_29_28,
-		GP_4_12_FN, FN_IP9_27_26,
-		GP_4_11_FN, FN_IP9_9_8,
-		GP_4_10_FN, FN_IP9_7_6,
-		GP_4_9_FN, FN_IP9_5_4,
-		GP_4_8_FN, FN_IP9_3_2,
-		GP_4_7_FN, FN_IP9_17_16,
-		GP_4_6_FN, FN_IP9_15_14,
-		GP_4_5_FN, FN_IP9_13_12,
-		GP_4_4_FN, FN_IP9_11_10,
-		GP_4_3_FN, FN_IP9_25_24,
-		GP_4_2_FN, FN_IP9_23_22,
-		GP_4_1_FN, FN_IP9_21_20,
-		GP_4_0_FN, FN_IP9_19_18 ))
-	},
-	{ PINMUX_CFG_REG("GPSR5", 0xFFFC0018, 32, 1, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 28 */
-		0, 0, 0, 0, 0, 0, 0, 0, /* 27 - 24 */
-		0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 20 */
-		0, 0, 0, 0, 0, 0, 0, 0, /* 19 - 16 */
-		0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */
-		GP_5_11_FN, FN_IP10_29_28,
-		GP_5_10_FN, FN_IP10_27_26,
-		0, 0, 0, 0, 0, 0, 0, 0, /* 9 - 6 */
-		0, 0, 0, 0, /* 5, 4 */
-		GP_5_3_FN, FN_IRQ3_B,
-		GP_5_2_FN, FN_IRQ2_B,
-		GP_5_1_FN, FN_IP11_3,
-		GP_5_0_FN, FN_IP10_25 ))
-	},
-
-	{ PINMUX_CFG_REG_VAR("IPSR0", 0xFFFC001C, 32,
-			GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2),
-			GROUP(
-		/* IP0_31_30 [2] */
-		FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A,
-			FN_TIOC3D_C,
-		/* IP0_29_28 [2] */
-		FN_A14, FN_LCD_DATA14_A, FN_TIOC3C_C, 0,
-		/* IP0_27_26 [2] */
-		FN_A13, FN_LCD_DATA13_A, FN_TIOC3B_C, 0,
-		/* IP0_25_24 [2] */
-		FN_A12, FN_LCD_DATA12_A, FN_TIOC3A_C, 0,
-		/* IP0_23_22 [2] */
-		FN_A11, FN_ST0_D7, FN_LCD_DATA11_A, FN_TIOC2B_C,
-		/* IP0_21_20 [2] */
-		FN_A10, FN_ST0_D6, FN_LCD_DATA10_A, FN_TIOC2A_C,
-		/* IP0_19_18 [2] */
-		FN_A9, FN_ST0_D5, FN_LCD_DATA9_A, FN_TIOC1B_C,
-		/* IP0_17_16 [2] */
-		FN_A8, FN_ST0_D4, FN_LCD_DATA8_A, FN_TIOC1A_C,
-		/* IP0_15_14 [2] */
-		FN_A7, FN_ST0_D3, FN_LCD_DATA7_A, FN_TIOC0D_C,
-		/* IP0_13_12 [2] */
-		FN_A6, FN_ST0_D2, FN_LCD_DATA6_A, FN_TIOC0C_C,
-		/* IP0_11_10 [2] */
-		FN_A5, FN_ST0_D1, FN_LCD_DATA5_A, FN_TIOC0B_C,
-		/* IP0_9_8 [2] */
-		FN_A4, FN_ST0_D0, FN_LCD_DATA4_A, FN_TIOC0A_C,
-		/* IP0_7_6 [2] */
-		FN_A3, FN_ST0_VLD, FN_LCD_DATA3_A, FN_TCLKD_C,
-		/* IP0_5_4 [2] */
-		FN_A2, FN_ST0_SYC, FN_LCD_DATA2_A, FN_TCLKC_C,
-		/* IP0_3_2 [2] */
-		FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C,
-		/* IP0_1_0 [2] */
-		FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR1", 0xFFFC0020, 32,
-			GROUP(3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2),
-			GROUP(
-		/* IP1_31_29 [3] */
-		FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6,
-			FN_FD3_A, 0, 0, 0,
-		/* IP1_28_26 [3] */
-		FN_D2, FN_SD0_DAT2_A, FN_MMC_D2_A, FN_ST1_D5,
-			FN_FD2_A, 0, 0, 0,
-		/* IP1_25_23 [3] */
-		FN_D1, FN_SD0_DAT1_A, FN_MMC_D1_A, FN_ST1_D4,
-			FN_FD1_A, 0, 0, 0,
-		/* IP1_22_20 [3] */
-		FN_D0, FN_SD0_DAT0_A, FN_MMC_D0_A, FN_ST1_D3,
-			FN_FD0_A, 0, 0, 0,
-		/* IP1_19_18 [2] */
-		FN_A25, FN_TX2_D, FN_ST1_D2, 0,
-		/* IP1_17_16 [2] */
-		FN_A24, FN_RX2_D, FN_ST1_D1, 0,
-		/* IP1_15_14 [2] */
-		FN_A23, FN_ST1_D0, FN_LCD_M_DISP_A, 0,
-		/* IP1_13_12 [2] */
-		FN_A22, FN_ST1_VLD, FN_LCD_VEPWC_A, 0,
-		/* IP1_11_10 [2] */
-		FN_A21, FN_ST1_SYC, FN_LCD_VCPWC_A, 0,
-		/* IP1_9_8 [2] */
-		FN_A20, FN_ST1_REQ, FN_LCD_FLM_A, 0,
-		/* IP1_7_6 [2] */
-		FN_A19, FN_ST1_CLKIN, FN_LCD_CLK_A,	FN_TIOC4D_C,
-		/* IP1_5_4 [2] */
-		FN_A18, FN_ST1_PWM, FN_LCD_CL2_A, FN_TIOC4C_C,
-		/* IP1_3_2 [2] */
-		FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A,	FN_TIOC4B_C,
-		/* IP1_1_0 [2] */
-		FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32,
-			     GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 3, 2, 3),
-			     GROUP(
-		/* IP2_31 [1] */
-		0, 0,
-		/* IP2_30_28 [3] */
-		FN_D14, FN_TX2_B, 0, FN_FSE_A,
-			FN_ET0_TX_CLK_B, 0, 0, 0,
-		/* IP2_27_25 [3] */
-		FN_D13, FN_RX2_B, 0, FN_FRB_A,
-			FN_ET0_ETXD6_B, 0, 0, 0,
-		/* IP2_24_23 [2] */
-		FN_D12, 0, FN_FWE_A, FN_ET0_ETXD5_B,
-		/* IP2_22_20 [3] */
-		FN_D11, FN_RSPI_MISO_A, 0, FN_QMI_QIO1_A,
-			FN_FRE_A, FN_ET0_ETXD3_B, 0, 0,
-		/* IP2_19_17 [3] */
-		FN_D10, FN_RSPI_MOSI_A, 0, FN_QMO_QIO0_A,
-			FN_FALE_A, FN_ET0_ETXD2_B, 0, 0,
-		/* IP2_16_14 [3] */
-		FN_D9, FN_SD0_CMD_A, FN_MMC_CMD_A, FN_QIO3_A,
-			FN_FCLE_A, FN_ET0_ETXD1_B, 0, 0,
-		/* IP2_13_11 [3] */
-		FN_D8, FN_SD0_CLK_A, FN_MMC_CLK_A, FN_QIO2_A,
-			FN_FCE_A, FN_ET0_GTX_CLK_B, 0, 0,
-		/* IP2_10_8 [3] */
-		FN_D7, FN_RSPI_SSL_A, FN_MMC_D7_A, FN_QSSL_A,
-			FN_FD7_A, 0, 0, 0,
-		/* IP2_7_5 [3] */
-		FN_D6, FN_RSPI_RSPCK_A, FN_MMC_D6_A, FN_QSPCLK_A,
-			FN_FD6_A, 0, 0, 0,
-		/* IP2_4_3 [2] */
-		FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A,
-		/* IP2_2_0 [3] */
-		FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7,
-			FN_FD4_A, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32,
-			     GROUP(2, 3, 3, 3, 1, 2, 3, 3, 3, 3, 3, 1, 2),
-			     GROUP(
-	    /* IP3_31_30 [2] */
-		0, 0, 0, 0,
-	    /* IP3_29_27 [3] */
-		FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A,
-		FN_ET0_ETXD7, 0, 0, 0,
-	    /* IP3_26_24 [3] */
-		FN_EX_WAIT2, FN_SD1_DAT1_A, FN_DACK2, FN_CAN1_RX_C,
-		FN_ET0_MAGIC_C, FN_ET0_ETXD6_A, 0, 0,
-	    /* IP3_23_21 [3] */
-		FN_EX_WAIT1, FN_SD1_DAT0_A, FN_DREQ2, FN_CAN1_TX_C,
-		FN_ET0_LINK_C, FN_ET0_ETXD5_A, 0, 0,
-	    /* IP3_20 [1] */
-		FN_EX_WAIT0, FN_TCLK1_B,
-	    /* IP3_19_18 [2] */
-		FN_RD_WR, FN_TCLK0, FN_CAN_CLK_B, FN_ET0_ETXD4,
-	    /* IP3_17_15 [3] */
-		FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B,
-		FN_ET0_ETXD3_A, 0, 0, 0,
-	    /* IP3_14_12 [3] */
-		FN_EX_CS4, FN_SD1_WP_A, FN_ATAWR, FN_QMI_QIO1_B,
-		FN_ET0_ETXD2_A, 0, 0, 0,
-	    /* IP3_11_9 [3] */
-		FN_EX_CS3, FN_SD1_CD_A, FN_ATARD, FN_QMO_QIO0_B,
-		FN_ET0_ETXD1_A, 0, 0, 0,
-	    /* IP3_8_6 [3] */
-		FN_EX_CS2, FN_TX3_B, FN_ATACS1, FN_QSPCLK_B,
-		FN_ET0_GTX_CLK_A, 0, 0, 0,
-	    /* IP3_5_3 [3] */
-		FN_EX_CS1, FN_RX3_B, FN_ATACS0, FN_QIO2_B,
-		FN_ET0_ETXD0, 0, 0, 0,
-	    /* IP3_2 [1] */
-		FN_CS1_A26, FN_QIO3_B,
-	    /* IP3_1_0 [2] */
-		FN_D15, FN_SCK2_B, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR4", 0xFFFC002C, 32,
-			     GROUP(2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3),
-			     GROUP(
-	    /* IP4_31_30 [2] */
-		0, FN_SCK2_A, FN_VI0_G3, 0,
-	    /* IP4_29_28 [2] */
-		0, FN_RTS1_B, FN_VI0_G2, 0,
-	    /* IP4_27_26 [2] */
-		0, FN_CTS1_B, FN_VI0_DATA7_VI0_G1, 0,
-	    /* IP4_25_24 [2] */
-		0, FN_TX1_B, FN_VI0_DATA6_VI0_G0, FN_ET0_PHY_INT_A,
-	    /* IP4_23_22 [2] */
-		0, FN_RX1_B, FN_VI0_DATA5_VI0_B5, FN_ET0_MAGIC_A,
-	    /* IP4_21_20 [2] */
-		0, FN_SCK1_B, FN_VI0_DATA4_VI0_B4, FN_ET0_LINK_A,
-	    /* IP4_19_18 [2] */
-		0, FN_RTS0_B, FN_VI0_DATA3_VI0_B3, FN_ET0_MDIO_A,
-	    /* IP4_17_15 [3] */
-		0, FN_CTS0_B, FN_VI0_DATA2_VI0_B2, FN_RMII0_MDIO_A,
-			FN_ET0_MDC, 0, 0, 0,
-	    /* IP4_14_12 [3] */
-		FN_HTX0_A, FN_TX1_A, FN_VI0_DATA1_VI0_B1, FN_RMII0_MDC_A,
-			FN_ET0_COL, 0, 0, 0,
-	    /* IP4_11_9 [3] */
-		FN_HRX0_A, FN_RX1_A, FN_VI0_DATA0_VI0_B0, FN_RMII0_CRS_DV_A,
-			FN_ET0_CRS, 0, 0, 0,
-	    /* IP4_8_6 [3] */
-		FN_HSCK0_A, FN_SCK1_A, FN_VI0_VSYNC, FN_RMII0_RX_ER_A,
-			FN_ET0_RX_ER, 0, 0, 0,
-	    /* IP4_5_3 [3] */
-		FN_HRTS0_A, FN_RTS1_A, FN_VI0_HSYNC, FN_RMII0_TXD_EN_A,
-			FN_ET0_RX_DV, 0, 0, 0,
-	    /* IP4_2_0 [3] */
-		FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A,
-			FN_ET0_ERXD7, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32,
-			     GROUP(1, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3,
-				   3, 3, 3),
-			     GROUP(
-	    /* IP5_31 [1] */
-	    0, 0,
-	    /* IP5_30 [1] */
-	    0, 0,
-	    /* IP5_29 [1] */
-	    0, 0,
-	    /* IP5_28 [1] */
-	    0, 0,
-	    /* IP5_27 [1] */
-	    0, 0,
-	    /* IP5_26_25 [2] */
-		FN_REF50CK, FN_CTS1_E, FN_HCTS0_D, 0,
-	    /* IP5_24_23 [2] */
-		FN_REF125CK, FN_ADTRG, FN_RX5_C, 0,
-	    /* IP5_22_21 [2] */
-		FN_SD2_WP_A, FN_TX5_A, FN_VI0_R5, 0,
-	    /* IP5_20_18 [3] */
-		FN_SD2_CD_A, FN_RX5_A, FN_VI0_R4, 0,
-		0, 0, 0, FN_ET0_PHY_INT_B,
-	    /* IP5_17_15 [3] */
-		FN_SD2_DAT3_A, FN_TX4_A, FN_VI0_R3, 0,
-		0, 0, 0, FN_ET0_MAGIC_B,
-	    /* IP5_14_12 [3] */
-		FN_SD2_DAT2_A, FN_RX4_A, FN_VI0_R2, 0,
-		0, 0, 0, FN_ET0_LINK_B,
-	    /* IP5_11_9 [3] */
-		FN_SD2_DAT1_A, FN_TX3_A, FN_VI0_R1, 0,
-		0, 0, 0, FN_ET0_MDIO_B,
-	    /* IP5_8_6 [3] */
-		FN_SD2_DAT0_A, FN_RX3_A, FN_VI0_R0, 0,
-		0, 0, 0, FN_ET0_ERXD3_B,
-	    /* IP5_5_3 [3] */
-		FN_SD2_CMD_A, FN_TX2_A, FN_VI0_G5, 0,
-		0, 0, 0, FN_ET0_ERXD2_B,
-	    /* IP5_2_0 [3] */
-		FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, 0,
-		FN_ET0_RX_CLK_B, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32,
-			     GROUP(1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 2, 2,
-				   2, 2, 2, 2, 3, 3),
-			     GROUP(
-	    /* IP5_31 [1] */
-	    0, 0,
-	    /* IP6_30 [1] */
-	    0, 0,
-	    /* IP6_29 [1] */
-	    0, 0,
-	    /* IP6_28 [1] */
-	    0, 0,
-	    /* IP6_27 [1] */
-	    0, 0,
-	    /* IP6_26 [1] */
-	    0, 0,
-	    /* IP6_25 [1] */
-	    0, 0,
-	    /* IP6_24 [1] */
-	    0, 0,
-	    /* IP6_23_21 [3] */
-		FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A,
-		FN_HIFD09, 0, 0, 0,
-	    /* IP6_20_18 [3] */
-		FN_DU0_DG0, FN_TX1_C, FN_HSCK0_D, FN_IECLK_A,
-		FN_TIOC1A_A, FN_HIFD08, 0, 0,
-	    /* IP6_17_16 [2] */
-		FN_DU0_DR7, FN_RX1_C, FN_TIOC0D_A, FN_HIFD07,
-	    /* IP6_15_14 [2] */
-		FN_DU0_DR6, FN_SCK1_C, FN_TIOC0C_A, FN_HIFD06,
-	    /* IP6_13_12 [2] */
-		FN_DU0_DR5, FN_RTS0_C, FN_TIOC0B_A, FN_HIFD05,
-	    /* IP6_11_10 [2] */
-		FN_DU0_DR4, FN_CTS0_C, FN_TIOC0A_A, FN_HIFD04,
-	    /* IP6_9_8 [2] */
-		FN_DU0_DR3, FN_TX0_B, FN_TCLKD_A, FN_HIFD03,
-	    /* IP6_7_6 [2] */
-		FN_DU0_DR2, FN_RX0_B, FN_TCLKC_A, FN_HIFD02,
-	    /* IP6_5_3 [3] */
-		FN_DU0_DR1, FN_SCK0_B, FN_HTX0_D, FN_IERX_A,
-		FN_TCLKB_A, FN_HIFD01, 0, 0,
-	    /* IP6_2_0 [3] */
-		FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A,
-		FN_TCLKA_A, FN_HIFD00, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32,
-			     GROUP(1, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3),
-			     GROUP(
-	    /* IP7_31 [1] */
-	    0, 0,
-	    /* IP7_30_29 [2] */
-		FN_DU0_DB4, 0, FN_HIFINT, 0,
-	    /* IP7_28_27 [2] */
-		FN_DU0_DB3, FN_TX5_B, FN_TIOC4D_A, FN_HIFRD,
-	    /* IP7_26_24 [3] */
-		FN_DU0_DB2, FN_RX5_B, FN_RMII0_TXD1_B, FN_TIOC4C_A,
-		FN_HIFWR, 0, 0, 0,
-	    /* IP7_23_21 [3] */
-		FN_DU0_DB1, FN_TX4_C, FN_RMII0_TXD0_B, FN_TIOC4B_A,
-		FN_HIFRS, 0, 0, 0,
-	    /* IP7_20_18 [3] */
-		FN_DU0_DB0, FN_RX4_C, FN_RMII0_TXD_EN_B, FN_TIOC4A_A,
-		FN_HIFCS, 0, 0, 0,
-	    /* IP7_17_15 [3] */
-		FN_DU0_DG7, FN_TX3_C, FN_RMII0_RXD1_B, FN_TIOC3D_A,
-		FN_HIFD15, 0, 0, 0,
-	    /* IP7_14_12 [3] */
-		FN_DU0_DG6, FN_RX3_C, FN_RMII0_RXD0_B, FN_TIOC3C_A,
-		FN_HIFD14, 0, 0, 0,
-	    /* IP7_11_9 [3] */
-		FN_DU0_DG5, FN_TX2_C, FN_RMII0_RX_ER_B, FN_TIOC3B_A,
-		FN_HIFD13, 0, 0, 0,
-	    /* IP7_8_6 [3] */
-		FN_DU0_DG4, FN_RX2_C, FN_RMII0_CRS_DV_B, FN_TIOC3A_A,
-		FN_HIFD12, 0, 0, 0,
-	    /* IP7_5_3 [3] */
-		FN_DU0_DG3, FN_SCK2_C, FN_RMII0_MDIO_B, FN_TIOC2B_A,
-		FN_HIFD11, 0, 0, 0,
-	    /* IP7_2_0 [3] */
-		FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A,
-		FN_HIFD10, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32,
-			     GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 2,
-				   2, 2, 2),
-			     GROUP(
-	    /* IP9_31_30 [2] */
-	    0, 0, 0, 0,
-	    /* IP8_29_28 [2] */
-		FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A,
-	    /* IP8_27_26 [2] */
-		FN_IRQ2_A, FN_CTS0_A, FN_HCTS0_B, FN_ET0_ERXD2_A,
-	    /* IP8_25_23 [3] */
-		FN_IRQ1_A, 0, FN_HSPI_RX_B, FN_TX3_E,
-			FN_ET0_ERXD1, 0, 0, 0,
-	    /* IP8_22_20 [3] */
-		FN_IRQ0_A, 0, FN_HSPI_TX_B, FN_RX3_E,
-			FN_ET0_ERXD0, 0, 0, 0,
-	    /* IP8_19_18 [2] */
-		FN_DU0_CDE, FN_HTX0_B, FN_AUDIO_CLKB_B, FN_LCD_VCPWC_B,
-	    /* IP8_17_16 [2] */
-		FN_DU0_DISP, FN_CAN0_TX_B, FN_HRX0_B, FN_AUDIO_CLKA_B,
-	    /* IP8_15_14 [2] */
-		FN_DU0_EXODDF_DU0_ODDF, FN_CAN0_RX_B, FN_HSCK0_B,
-			FN_SSI_SDATA1_B,
-	    /* IP8_13_12 [2] */
-		FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_HSPI_RX0_C, FN_SSI_WS1_B,
-	    /* IP8_11_10 [2] */
-		FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_HSPI_TX0_C, FN_SSI_SCK1_B,
-	    /* IP8_9_8 [2] */
-		FN_DU0_DOTCLKOUT, 0, FN_HSPI_CLK0_C, FN_SSI_SDATA0_B,
-	    /* IP8_7_6 [2] */
-		FN_DU0_DOTCLKIN, 0, FN_HSPI_CS0_C, FN_SSI_WS0_B,
-	    /* IP8_5_4 [2] */
-		FN_DU0_DB7, 0, FN_SSI_SCK0_B, FN_HIFEBL_B,
-	    /* IP8_3_2 [2] */
-		FN_DU0_DB6, 0, FN_HIFRDY, 0,
-	    /* IP8_1_0 [2] */
-		FN_DU0_DB5, 0, FN_HIFDREQ, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR9", 0xFFFC0040, 32,
-			     GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-				   2, 2, 2, 2),
-			     GROUP(
-	    /* IP9_31_30 [2] */
-	    0, 0, 0, 0,
-	    /* IP9_29_28 [2] */
-		FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B, 0,
-	    /* IP9_27_26 [2] */
-		FN_SSI_WS1_A, FN_VI1_2_B, FN_LCD_DATA13_B, 0,
-	    /* IP9_25_24 [2] */
-		FN_SSI_SCK1_A, FN_VI1_1_B, FN_TIOC2B_B, FN_LCD_DATA12_B,
-	    /* IP9_23_22 [2] */
-		FN_SSI_SDATA0_A, FN_VI1_0_B, FN_TIOC2A_B, FN_LCD_DATA11_B,
-	    /* IP9_21_20 [2] */
-		FN_SSI_WS0_A, FN_TIOC1B_B, FN_LCD_DATA10_B, 0,
-	    /* IP9_19_18 [2] */
-		FN_SSI_SCK0_A, FN_TIOC1A_B, FN_LCD_DATA9_B, 0,
-	    /* IP9_17_16 [2] */
-		FN_VI1_7_A, FN_FCE_B, FN_LCD_DATA8_B, 0,
-	    /* IP9_15_14 [2] */
-		FN_VI1_6_A, 0, FN_FD7_B, FN_LCD_DATA7_B,
-	    /* IP9_13_12 [2] */
-		FN_VI1_5_A, 0, FN_FD6_B, FN_LCD_DATA6_B,
-	    /* IP9_11_10 [2] */
-		FN_VI1_4_A, 0, FN_FD5_B, FN_LCD_DATA5_B,
-	    /* IP9_9_8 [2] */
-		FN_VI1_3_A, 0, FN_FD4_B, FN_LCD_DATA4_B,
-	    /* IP9_7_6 [2] */
-		FN_VI1_2_A, 0, FN_FD3_B, FN_LCD_DATA3_B,
-	    /* IP9_5_4 [2] */
-		FN_VI1_1_A, 0, FN_FD2_B, FN_LCD_DATA2_B,
-	    /* IP9_3_2 [2] */
-		FN_VI1_0_A, 0, FN_FD1_B, FN_LCD_DATA1_B,
-	    /* IP9_1_0 [2] */
-		FN_VI1_CLK_A, 0, FN_FD0_B, FN_LCD_DATA0_B ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR10", 0xFFFC0044, 32,
-			     GROUP(2, 2, 2, 1, 2, 1, 3, 3, 1, 3, 3, 3, 3, 3),
-			     GROUP(
-	    /* IP9_31_30 [2] */
-	    0, 0, 0, 0,
-	    /* IP10_29_28 [2] */
-		FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT, 0,
-	    /* IP10_27_26 [2] */
-		FN_CAN0_RX_A, FN_IRQ0_B, FN_MLB_SIG, 0,
-	    /* IP10_25 [1] */
-		FN_CAN1_RX_A, FN_IRQ1_B,
-	    /* IP10_24_23 [2] */
-		FN_CAN0_TX_A, FN_TX4_D, FN_MLB_CLK, 0,
-	    /* IP10_22 [1] */
-		FN_CAN_CLK_A, FN_RX4_D,
-	    /* IP10_21_19 [3] */
-		FN_AUDIO_CLKOUT, FN_TX1_E, 0, FN_HRTS0_C, FN_FSE_B,
-		FN_LCD_M_DISP_B, 0, 0,
-	    /* IP10_18_16 [3] */
-		FN_AUDIO_CLKC, FN_SCK1_E, 0, FN_HCTS0_C, FN_FRB_B,
-		FN_LCD_VEPWC_B, 0, 0,
-	    /* IP10_15 [1] */
-		FN_AUDIO_CLKB_A, FN_LCD_CLK_B,
-	    /* IP10_14_12 [3] */
-		FN_AUDIO_CLKA_A, FN_VI1_CLK_B, FN_SCK1_D, FN_IECLK_B,
-		FN_LCD_FLM_B, 0, 0, 0,
-	    /* IP10_11_9 [3] */
-		FN_SSI_SDATA3, FN_VI1_7_B, 0, FN_HTX0_C, FN_FWE_B,
-		FN_LCD_CL2_B, 0, 0,
-	    /* IP10_8_6 [3] */
-		FN_SSI_SDATA2, FN_VI1_6_B, 0, FN_HRX0_C, FN_FRE_B,
-		FN_LCD_CL1_B, 0, 0,
-	    /* IP10_5_3 [3] */
-		FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B,
-		FN_LCD_DON_B, 0, 0,
-	    /* IP10_2_0 [3] */
-		FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B,
-		FN_LCD_DATA15_B, 0, 0, 0 ))
-	},
-	{ PINMUX_CFG_REG_VAR("IPSR11", 0xFFFC0048, 32,
-			     GROUP(3, 1, 2, 3, 2, 2, 3, 3, 1, 2, 3, 3,
-				   1, 1, 1, 1),
-			     GROUP(
-	    /* IP11_31_29 [3] */
-	    0, 0, 0, 0, 0, 0, 0, 0,
-	    /* IP11_28 [1] */
-		FN_PRESETOUT, FN_ST_CLKOUT,
-	    /* IP11_27_26 [2] */
-		FN_DACK1, FN_HSPI_CS_B, FN_TX4_B, FN_ET0_RX_CLK_A,
-	    /* IP11_25_23 [3] */
-		FN_DREQ1, FN_HSPI_CLK_B, FN_RX4_B, FN_ET0_PHY_INT_C,
-		FN_ET0_TX_CLK_A, 0, 0, 0,
-	    /* IP11_22_21 [2] */
-		FN_DACK0, FN_SD1_DAT3_A, FN_ET0_TX_ER, 0,
-	    /* IP11_20_19 [2] */
-		FN_DREQ0, FN_SD1_CLK_A, FN_ET0_TX_EN, 0,
-	    /* IP11_18_16 [3] */
-		FN_USB_OVC1, FN_RX3_D, FN_CAN1_RX_B, FN_RX5_D,
-		FN_IERX_B, 0, 0, 0,
-	    /* IP11_15_13 [3] */
-		FN_PENC1, FN_TX3_D, FN_CAN1_TX_B, FN_TX5_D,
-		FN_IETX_B, 0, 0, 0,
-	    /* IP11_12 [1] */
-		FN_TX0_A, FN_HSPI_TX_A,
-	    /* IP11_11_10 [2] */
-		FN_RX0_A, FN_HSPI_RX_A, FN_RMII0_RXD0_A, FN_ET0_ERXD6,
-	    /* IP11_9_7 [3] */
-		FN_SCK0_A, FN_HSPI_CS_A, FN_VI0_CLKENB, FN_RMII0_TXD1_A,
-		FN_ET0_ERXD5, 0, 0, 0,
-	    /* IP11_6_4 [3] */
-		FN_SCIF_CLK_A, FN_HSPI_CLK_A, FN_VI0_CLK, FN_RMII0_TXD0_A,
-		FN_ET0_ERXD4, 0, 0, 0,
-	    /* IP11_3 [1] */
-		FN_SDSELF, FN_RTS1_E,
-	    /* IP11_2 [1] */
-		FN_SDA0, FN_HIFEBL_A,
-	    /* IP11_1 [1] */
-		FN_SDA1, FN_RX1_E,
-	    /* IP11_0 [1] */
-		FN_SCL1, FN_SCIF_CLK_C ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xFFFC004C, 32,
-			     GROUP(3, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 2,
-				   2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
-			     GROUP(
-		/* SEL1_31_29 [3] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* SEL1_28 [1] */
-		FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
-		/* SEL1_27 [1] */
-		FN_SEL_RQSPI_0, FN_SEL_RQSPI_1,
-		/* SEL1_26 [1] */
-		FN_SEL_VIN1_0, FN_SEL_VIN1_1,
-		/* SEL1_25 [1] */
-		FN_SEL_HIF_0, FN_SEL_HIF_1,
-		/* SEL1_24 [1] */
-		FN_SEL_RSPI_0, FN_SEL_RSPI_1,
-		/* SEL1_23 [1] */
-		FN_SEL_LCDC_0, FN_SEL_LCDC_1,
-		/* SEL1_22_21 [2] */
-		FN_SEL_ET0_CTL_0, FN_SEL_ET0_CTL_1, FN_SEL_ET0_CTL_2, 0,
-		/* SEL1_20 [1] */
-		FN_SEL_ET0_0, FN_SEL_ET0_1,
-		/* SEL1_19 [1] */
-		FN_SEL_RMII_0, FN_SEL_RMII_1,
-		/* SEL1_18 [1] */
-		FN_SEL_TMU_0, FN_SEL_TMU_1,
-		/* SEL1_17_16 [2] */
-		FN_SEL_HSPI_0, FN_SEL_HSPI_1, FN_SEL_HSPI_2, 0,
-		/* SEL1_15_14 [2] */
-		FN_SEL_HSCIF_0, FN_SEL_HSCIF_1, FN_SEL_HSCIF_2, FN_SEL_HSCIF_3,
-		/* SEL1_13 [1] */
-		FN_SEL_RCAN_CLK_0, FN_SEL_RCAN_CLK_1,
-		/* SEL1_12_11 [2] */
-		FN_SEL_RCAN1_0, FN_SEL_RCAN1_1, FN_SEL_RCAN1_2, 0,
-		/* SEL1_10 [1] */
-		FN_SEL_RCAN0_0, FN_SEL_RCAN0_1,
-		/* SEL1_9 [1] */
-		FN_SEL_SDHI2_0, FN_SEL_SDHI2_1,
-		/* SEL1_8 [1] */
-		FN_SEL_SDHI1_0, FN_SEL_SDHI1_1,
-		/* SEL1_7 [1] */
-		FN_SEL_SDHI0_0, FN_SEL_SDHI0_1,
-		/* SEL1_6 [1] */
-		FN_SEL_SSI1_0, FN_SEL_SSI1_1,
-		/* SEL1_5 [1] */
-		FN_SEL_SSI0_0, FN_SEL_SSI0_1,
-		/* SEL1_4 [1] */
-		FN_SEL_AUDIO_CLKB_0, FN_SEL_AUDIO_CLKB_1,
-		/* SEL1_3 [1] */
-		FN_SEL_AUDIO_CLKA_0, FN_SEL_AUDIO_CLKA_1,
-		/* SEL1_2 [1] */
-		FN_SEL_FLCTL_0, FN_SEL_FLCTL_1,
-		/* SEL1_1 [1] */
-		FN_SEL_MMC_0, FN_SEL_MMC_1,
-		/* SEL1_0 [1] */
-		FN_SEL_INTC_0, FN_SEL_INTC_1 ))
-	},
-	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xFFFC0050, 32,
-			     GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
-				   2, 1, 2, 2, 3, 2, 3, 2, 2),
-			     GROUP(
-		/* SEL2_31 [1] */
-		0, 0,
-		/* SEL2_30 [1] */
-		0, 0,
-		/* SEL2_29 [1] */
-		0, 0,
-		/* SEL2_28 [1] */
-		0, 0,
-		/* SEL2_27 [1] */
-		0, 0,
-		/* SEL2_26 [1] */
-		0, 0,
-		/* SEL2_25 [1] */
-		0, 0,
-		/* SEL2_24 [1] */
-		0, 0,
-		/* SEL2_23 [1] */
-		FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1,
-		/* SEL2_22 [1] */
-		FN_SEL_MTU2_CH4_0, FN_SEL_MTU2_CH4_1,
-		/* SEL2_21 [1] */
-		FN_SEL_MTU2_CH3_0, FN_SEL_MTU2_CH3_1,
-		/* SEL2_20_19 [2] */
-		FN_SEL_MTU2_CH2_0, FN_SEL_MTU2_CH2_1, FN_SEL_MTU2_CH2_2, 0,
-		/* SEL2_18_17 [2] */
-		FN_SEL_MTU2_CH1_0, FN_SEL_MTU2_CH1_1, FN_SEL_MTU2_CH1_2, 0,
-		/* SEL2_16 [1] */
-		FN_SEL_MTU2_CH0_0, FN_SEL_MTU2_CH0_1,
-		/* SEL2_15_14 [2] */
-		FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
-		/* SEL2_13_12 [2] */
-		FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
-		/* SEL2_11_9 [3] */
-		FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
-		FN_SEL_SCIF3_4, 0, 0, 0,
-		/* SEL2_8_7 [2] */
-		FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
-		/* SEL2_6_4 [3] */
-		FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
-			FN_SEL_SCIF1_4, 0, 0, 0,
-		/* SEL2_3_2 [2] */
-		FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, 0,
-		/* SEL2_1_0 [2] */
-		FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2, 0  ))
-	},
-	/* GPIO 0 - 5*/
-	{ PINMUX_CFG_REG("INOUTSEL0", 0xFFC40004, 32, 1, GROUP(GP_INOUTSEL(0)))
-	},
-	{ PINMUX_CFG_REG("INOUTSEL1", 0xFFC41004, 32, 1, GROUP(GP_INOUTSEL(1)))
-	},
-	{ PINMUX_CFG_REG("INOUTSEL2", 0xFFC42004, 32, 1, GROUP(GP_INOUTSEL(2)))
-	},
-	{ PINMUX_CFG_REG("INOUTSEL3", 0xFFC43004, 32, 1, GROUP(GP_INOUTSEL(3)))
-	},
-	{ PINMUX_CFG_REG("INOUTSEL4", 0xFFC44004, 32, 1, GROUP(GP_INOUTSEL(4)))
-	},
-	{ PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 24 */
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 16 */
-		0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */
-		GP_5_11_IN, GP_5_11_OUT,
-		GP_5_10_IN, GP_5_10_OUT,
-		GP_5_9_IN, GP_5_9_OUT,
-		GP_5_8_IN, GP_5_8_OUT,
-		GP_5_7_IN, GP_5_7_OUT,
-		GP_5_6_IN, GP_5_6_OUT,
-		GP_5_5_IN, GP_5_5_OUT,
-		GP_5_4_IN, GP_5_4_OUT,
-		GP_5_3_IN, GP_5_3_OUT,
-		GP_5_2_IN, GP_5_2_OUT,
-		GP_5_1_IN, GP_5_1_OUT,
-		GP_5_0_IN, GP_5_0_OUT ))
-	},
-	{ },
-};
-
-static const struct pinmux_data_reg pinmux_data_regs[] = {
-	/* GPIO 0 - 5*/
-	{ PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32, GROUP(GP_INDT(0))) },
-	{ PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32, GROUP(GP_INDT(1))) },
-	{ PINMUX_DATA_REG("INDT2", 0xFFC4200C, 32, GROUP(GP_INDT(2))) },
-	{ PINMUX_DATA_REG("INDT3", 0xFFC4300C, 32, GROUP(GP_INDT(3))) },
-	{ PINMUX_DATA_REG("INDT4", 0xFFC4400C, 32, GROUP(GP_INDT(4))) },
-	{ PINMUX_DATA_REG("INDT5", 0xFFC4500C, 32, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0,
-		GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
-		GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
-		GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA ))
-	},
-	{ },
-};
-
-const struct sh_pfc_soc_info sh7734_pinmux_info = {
-	.name = "sh7734_pfc",
-
-	.unlock_reg = 0xFFFC0000,
-
-	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.func_gpios = pinmux_func_gpios,
-	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
-	.cfg_regs = pinmux_config_regs,
-	.data_regs = pinmux_data_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
deleted file mode 100644
index 064e987b09cb..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c
+++ /dev/null
@@ -1,2239 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * SH7757 (B0 step) Pinmux
- *
- *  Copyright (C) 2009-2010  Renesas Solutions Corp.
- *
- *  Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * Based on SH7723 Pinmux
- *  Copyright (C) 2008  Magnus Damm
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <cpu/sh7757.h>
-
-#include "sh_pfc.h"
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
-	PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA,
-	PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
-	PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA,
-	PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
-	PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA,
-	PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
-	PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA,
-	PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
-	PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA,
-	PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
-	PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA,
-	PTG7_DATA, PTG6_DATA, PTG5_DATA, PTG4_DATA,
-	PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA,
-	PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
-	PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
-	PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA,
-	PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA,
-		   PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
-	PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA,
-	PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
-	PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
-		   PTL6_DATA, PTL5_DATA, PTL4_DATA,
-	PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA,
-	PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
-	PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
-		   PTN6_DATA, PTN5_DATA, PTN4_DATA,
-	PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA,
-	PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA,
-	PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA,
-	PTP7_DATA, PTP6_DATA, PTP5_DATA, PTP4_DATA,
-	PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA,
-		   PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
-	PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA,
-	PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
-	PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
-	PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
-	PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
-	PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
-	PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
-	PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
-	PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
-	PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
-	PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA,
-	PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
-	PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA,
-	PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
-	PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA,
-	PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
-	PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA,
-	PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
-	PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA,
-	PINMUX_DATA_END,
-
-	PINMUX_INPUT_BEGIN,
-	PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN,
-	PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN,
-	PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN,
-	PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN,
-	PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN,
-	PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN,
-	PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN,
-	PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN,
-	PTE7_IN, PTE6_IN, PTE5_IN, PTE4_IN,
-	PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN,
-	PTF7_IN, PTF6_IN, PTF5_IN, PTF4_IN,
-	PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN,
-	PTG7_IN, PTG6_IN, PTG5_IN, PTG4_IN,
-	PTG3_IN, PTG2_IN, PTG1_IN, PTG0_IN,
-	PTH7_IN, PTH6_IN, PTH5_IN, PTH4_IN,
-	PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN,
-	PTI7_IN, PTI6_IN, PTI5_IN, PTI4_IN,
-	PTI3_IN, PTI2_IN, PTI1_IN, PTI0_IN,
-		 PTJ6_IN, PTJ5_IN, PTJ4_IN,
-	PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN,
-	PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN,
-	PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN,
-		 PTL6_IN, PTL5_IN, PTL4_IN,
-	PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN,
-	PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN,
-	PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
-		 PTN6_IN, PTN5_IN, PTN4_IN,
-	PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN,
-	PTO7_IN, PTO6_IN, PTO5_IN, PTO4_IN,
-	PTO3_IN, PTO2_IN, PTO1_IN, PTO0_IN,
-	PTP7_IN, PTP6_IN, PTP5_IN, PTP4_IN,
-	PTP3_IN, PTP2_IN, PTP1_IN, PTP0_IN,
-		 PTQ6_IN, PTQ5_IN, PTQ4_IN,
-	PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN,
-	PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN,
-	PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN,
-	PTS7_IN, PTS6_IN, PTS5_IN, PTS4_IN,
-	PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN,
-	PTT7_IN, PTT6_IN, PTT5_IN, PTT4_IN,
-	PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN,
-	PTU7_IN, PTU6_IN, PTU5_IN, PTU4_IN,
-	PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
-	PTV7_IN, PTV6_IN, PTV5_IN, PTV4_IN,
-	PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
-	PTW7_IN, PTW6_IN, PTW5_IN, PTW4_IN,
-	PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN,
-	PTX7_IN, PTX6_IN, PTX5_IN, PTX4_IN,
-	PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN,
-	PTY7_IN, PTY6_IN, PTY5_IN, PTY4_IN,
-	PTY3_IN, PTY2_IN, PTY1_IN, PTY0_IN,
-	PTZ7_IN, PTZ6_IN, PTZ5_IN, PTZ4_IN,
-	PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN,
-	PINMUX_INPUT_END,
-
-	PINMUX_OUTPUT_BEGIN,
-	PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT,
-	PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT,
-	PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
-	PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT,
-	PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT,
-	PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT,
-	PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT,
-	PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT,
-	PTE7_OUT, PTE6_OUT, PTE5_OUT, PTE4_OUT,
-	PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT,
-	PTF7_OUT, PTF6_OUT, PTF5_OUT, PTF4_OUT,
-	PTF3_OUT, PTF2_OUT, PTF1_OUT, PTF0_OUT,
-	PTG7_OUT, PTG6_OUT, PTG5_OUT, PTG4_OUT,
-	PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT,
-	PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT,
-	PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
-	PTI7_OUT, PTI6_OUT, PTI5_OUT, PTI4_OUT,
-	PTI3_OUT, PTI2_OUT, PTI1_OUT, PTI0_OUT,
-		  PTJ6_OUT, PTJ5_OUT, PTJ4_OUT,
-	PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT,
-	PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT,
-	PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT,
-		  PTL6_OUT, PTL5_OUT, PTL4_OUT,
-	PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT,
-	PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT,
-	PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
-		  PTN6_OUT, PTN5_OUT, PTN4_OUT,
-	PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT,
-	PTO7_OUT, PTO6_OUT, PTO5_OUT, PTO4_OUT,
-	PTO3_OUT, PTO2_OUT, PTO1_OUT, PTO0_OUT,
-	PTP7_OUT, PTP6_OUT, PTP5_OUT, PTP4_OUT,
-	PTP3_OUT, PTP2_OUT, PTP1_OUT, PTP0_OUT,
-		  PTQ6_OUT, PTQ5_OUT, PTQ4_OUT,
-	PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT,
-	PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT,
-	PTR3_OUT, PTR2_OUT, PTR1_OUT, PTR0_OUT,
-	PTS7_OUT, PTS6_OUT, PTS5_OUT, PTS4_OUT,
-	PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT,
-	PTT7_OUT, PTT6_OUT, PTT5_OUT, PTT4_OUT,
-	PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT,
-	PTU7_OUT, PTU6_OUT, PTU5_OUT, PTU4_OUT,
-	PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT,
-	PTV7_OUT, PTV6_OUT, PTV5_OUT, PTV4_OUT,
-	PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT,
-	PTW7_OUT, PTW6_OUT, PTW5_OUT, PTW4_OUT,
-	PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT,
-	PTX7_OUT, PTX6_OUT, PTX5_OUT, PTX4_OUT,
-	PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT,
-	PTY7_OUT, PTY6_OUT, PTY5_OUT, PTY4_OUT,
-	PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT,
-	PTZ7_OUT, PTZ6_OUT, PTZ5_OUT, PTZ4_OUT,
-	PTZ3_OUT, PTZ2_OUT, PTZ1_OUT, PTZ0_OUT,
-	PINMUX_OUTPUT_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN,
-	PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN,
-	PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN,
-	PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN,
-	PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN,
-	PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN,
-	PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN,
-	PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN,
-	PTE7_FN, PTE6_FN, PTE5_FN, PTE4_FN,
-	PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN,
-	PTF7_FN, PTF6_FN, PTF5_FN, PTF4_FN,
-	PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN,
-	PTG7_FN, PTG6_FN, PTG5_FN, PTG4_FN,
-	PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN,
-	PTH7_FN, PTH6_FN, PTH5_FN, PTH4_FN,
-	PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN,
-	PTI7_FN, PTI6_FN, PTI5_FN, PTI4_FN,
-	PTI3_FN, PTI2_FN, PTI1_FN, PTI0_FN,
-		 PTJ6_FN, PTJ5_FN, PTJ4_FN,
-	PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN,
-	PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN,
-	PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN,
-		 PTL6_FN, PTL5_FN, PTL4_FN,
-	PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN,
-	PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN,
-	PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN,
-		 PTN6_FN, PTN5_FN, PTN4_FN,
-	PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN,
-	PTO7_FN, PTO6_FN, PTO5_FN, PTO4_FN,
-	PTO3_FN, PTO2_FN, PTO1_FN, PTO0_FN,
-	PTP7_FN, PTP6_FN, PTP5_FN, PTP4_FN,
-	PTP3_FN, PTP2_FN, PTP1_FN, PTP0_FN,
-		 PTQ6_FN, PTQ5_FN, PTQ4_FN,
-	PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN,
-	PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN,
-	PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN,
-	PTS7_FN, PTS6_FN, PTS5_FN, PTS4_FN,
-	PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN,
-	PTT7_FN, PTT6_FN, PTT5_FN, PTT4_FN,
-	PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN,
-	PTU7_FN, PTU6_FN, PTU5_FN, PTU4_FN,
-	PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN,
-	PTV7_FN, PTV6_FN, PTV5_FN, PTV4_FN,
-	PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN,
-	PTW7_FN, PTW6_FN, PTW5_FN, PTW4_FN,
-	PTW3_FN, PTW2_FN, PTW1_FN, PTW0_FN,
-	PTX7_FN, PTX6_FN, PTX5_FN, PTX4_FN,
-	PTX3_FN, PTX2_FN, PTX1_FN, PTX0_FN,
-	PTY7_FN, PTY6_FN, PTY5_FN, PTY4_FN,
-	PTY3_FN, PTY2_FN, PTY1_FN, PTY0_FN,
-	PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN,
-	PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN,
-
-	PS0_15_FN1, PS0_15_FN2,
-	PS0_14_FN1, PS0_14_FN2,
-	PS0_13_FN1, PS0_13_FN2,
-	PS0_12_FN1, PS0_12_FN2,
-	PS0_11_FN1, PS0_11_FN2,
-	PS0_10_FN1, PS0_10_FN2,
-	PS0_9_FN1, PS0_9_FN2,
-	PS0_8_FN1, PS0_8_FN2,
-	PS0_7_FN1, PS0_7_FN2,
-	PS0_6_FN1, PS0_6_FN2,
-	PS0_5_FN1, PS0_5_FN2,
-	PS0_4_FN1, PS0_4_FN2,
-	PS0_3_FN1, PS0_3_FN2,
-	PS0_2_FN1, PS0_2_FN2,
-
-	PS1_10_FN1, PS1_10_FN2,
-	PS1_9_FN1, PS1_9_FN2,
-	PS1_8_FN1, PS1_8_FN2,
-	PS1_2_FN1, PS1_2_FN2,
-
-	PS2_13_FN1, PS2_13_FN2,
-	PS2_12_FN1, PS2_12_FN2,
-	PS2_7_FN1, PS2_7_FN2,
-	PS2_6_FN1, PS2_6_FN2,
-	PS2_5_FN1, PS2_5_FN2,
-	PS2_4_FN1, PS2_4_FN2,
-	PS2_2_FN1, PS2_2_FN2,
-
-	PS3_15_FN1, PS3_15_FN2,
-	PS3_14_FN1, PS3_14_FN2,
-	PS3_13_FN1, PS3_13_FN2,
-	PS3_12_FN1, PS3_12_FN2,
-	PS3_11_FN1, PS3_11_FN2,
-	PS3_10_FN1, PS3_10_FN2,
-	PS3_9_FN1, PS3_9_FN2,
-	PS3_8_FN1, PS3_8_FN2,
-	PS3_7_FN1, PS3_7_FN2,
-	PS3_2_FN1, PS3_2_FN2,
-	PS3_1_FN1, PS3_1_FN2,
-
-	PS4_14_FN1, PS4_14_FN2,
-	PS4_13_FN1, PS4_13_FN2,
-	PS4_12_FN1, PS4_12_FN2,
-	PS4_10_FN1, PS4_10_FN2,
-	PS4_9_FN1, PS4_9_FN2,
-	PS4_8_FN1, PS4_8_FN2,
-	PS4_4_FN1, PS4_4_FN2,
-	PS4_3_FN1, PS4_3_FN2,
-	PS4_2_FN1, PS4_2_FN2,
-	PS4_1_FN1, PS4_1_FN2,
-	PS4_0_FN1, PS4_0_FN2,
-
-	PS5_11_FN1, PS5_11_FN2,
-	PS5_10_FN1, PS5_10_FN2,
-	PS5_9_FN1, PS5_9_FN2,
-	PS5_8_FN1, PS5_8_FN2,
-	PS5_7_FN1, PS5_7_FN2,
-	PS5_6_FN1, PS5_6_FN2,
-	PS5_5_FN1, PS5_5_FN2,
-	PS5_4_FN1, PS5_4_FN2,
-	PS5_3_FN1, PS5_3_FN2,
-	PS5_2_FN1, PS5_2_FN2,
-
-	PS6_15_FN1, PS6_15_FN2,
-	PS6_14_FN1, PS6_14_FN2,
-	PS6_13_FN1, PS6_13_FN2,
-	PS6_12_FN1, PS6_12_FN2,
-	PS6_11_FN1, PS6_11_FN2,
-	PS6_10_FN1, PS6_10_FN2,
-	PS6_9_FN1, PS6_9_FN2,
-	PS6_8_FN1, PS6_8_FN2,
-	PS6_7_FN1, PS6_7_FN2,
-	PS6_6_FN1, PS6_6_FN2,
-	PS6_5_FN1, PS6_5_FN2,
-	PS6_4_FN1, PS6_4_FN2,
-	PS6_3_FN1, PS6_3_FN2,
-	PS6_2_FN1, PS6_2_FN2,
-	PS6_1_FN1, PS6_1_FN2,
-	PS6_0_FN1, PS6_0_FN2,
-
-	PS7_15_FN1, PS7_15_FN2,
-	PS7_14_FN1, PS7_14_FN2,
-	PS7_13_FN1, PS7_13_FN2,
-	PS7_12_FN1, PS7_12_FN2,
-	PS7_11_FN1, PS7_11_FN2,
-	PS7_10_FN1, PS7_10_FN2,
-	PS7_9_FN1, PS7_9_FN2,
-	PS7_8_FN1, PS7_8_FN2,
-	PS7_7_FN1, PS7_7_FN2,
-	PS7_6_FN1, PS7_6_FN2,
-	PS7_5_FN1, PS7_5_FN2,
-	PS7_4_FN1, PS7_4_FN2,
-
-	PS8_15_FN1, PS8_15_FN2,
-	PS8_14_FN1, PS8_14_FN2,
-	PS8_13_FN1, PS8_13_FN2,
-	PS8_12_FN1, PS8_12_FN2,
-	PS8_11_FN1, PS8_11_FN2,
-	PS8_10_FN1, PS8_10_FN2,
-	PS8_9_FN1, PS8_9_FN2,
-	PS8_8_FN1, PS8_8_FN2,
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-	/* PTA (mobule: LBSC, RGMII) */
-	BS_MARK,	RDWR_MARK,	WE1_MARK,	RDY_MARK,
-	ET0_MDC_MARK,	ET0_MDIO_MARK,	ET1_MDC_MARK,	ET1_MDIO_MARK,
-
-	/* PTB (mobule: INTC, ONFI, TMU) */
-	IRQ15_MARK,	IRQ14_MARK,	IRQ13_MARK,	IRQ12_MARK,
-	IRQ11_MARK,	IRQ10_MARK,	IRQ9_MARK,	IRQ8_MARK,
-	ON_NRE_MARK,	ON_NWE_MARK,	ON_NWP_MARK,	ON_NCE0_MARK,
-	ON_R_B0_MARK,	ON_ALE_MARK,	ON_CLE_MARK,	TCLK_MARK,
-
-	/* PTC (mobule: IRQ, PWMU) */
-	IRQ7_MARK,	IRQ6_MARK,	IRQ5_MARK,	IRQ4_MARK,
-	IRQ3_MARK,	IRQ2_MARK,	IRQ1_MARK,	IRQ0_MARK,
-	PWMU0_MARK,	PWMU1_MARK,	PWMU2_MARK,	PWMU3_MARK,
-	PWMU4_MARK,	PWMU5_MARK,
-
-	/* PTD (mobule: SPI0, DMAC) */
-	SP0_MOSI_MARK,	SP0_MISO_MARK,	SP0_SCK_MARK,	SP0_SCK_FB_MARK,
-	SP0_SS0_MARK,	SP0_SS1_MARK,	SP0_SS2_MARK,	SP0_SS3_MARK,
-	DREQ0_MARK,	DACK0_MARK,	TEND0_MARK,
-
-	/* PTE (mobule: RMII) */
-	RMII0_CRS_DV_MARK,	RMII0_TXD1_MARK,
-	RMII0_TXD0_MARK,	RMII0_TXEN_MARK,
-	RMII0_REFCLK_MARK,	RMII0_RXD1_MARK,
-	RMII0_RXD0_MARK,	RMII0_RX_ER_MARK,
-
-	/* PTF (mobule: RMII, SerMux) */
-	RMII1_CRS_DV_MARK,	RMII1_TXD1_MARK,
-	RMII1_TXD0_MARK,	RMII1_TXEN_MARK,
-	RMII1_REFCLK_MARK,	RMII1_RXD1_MARK,
-	RMII1_RXD0_MARK,	RMII1_RX_ER_MARK,
-	RAC_RI_MARK,
-
-	/* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
-	BOOTFMS_MARK,	BOOTWP_MARK,	A25_MARK,	A24_MARK,
-	SERIRQ_MARK,	WDTOVF_MARK,	LPCPD_MARK,	LDRQ_MARK,
-	MMCCLK_MARK,	MMCCMD_MARK,
-
-	/* PTH (mobule: SPI1, LPC, DMAC, ADC) */
-	SP1_MOSI_MARK,	SP1_MISO_MARK,	SP1_SCK_MARK,	SP1_SCK_FB_MARK,
-	SP1_SS0_MARK,	SP1_SS1_MARK,	WP_MARK,	FMS0_MARK,
-	TEND1_MARK,	DREQ1_MARK,	DACK1_MARK,	ADTRG1_MARK,
-	ADTRG0_MARK,
-
-	/* PTI (mobule: LBSC, SDHI) */
-	D15_MARK,	D14_MARK,	D13_MARK,	D12_MARK,
-	D11_MARK,	D10_MARK,	D9_MARK,	D8_MARK,
-	SD_WP_MARK,	SD_CD_MARK,	SD_CLK_MARK,	SD_CMD_MARK,
-	SD_D3_MARK,	SD_D2_MARK,	SD_D1_MARK,	SD_D0_MARK,
-
-	/* PTJ (mobule: SCIF234) */
-	RTS3_MARK,	CTS3_MARK,	TXD3_MARK,	RXD3_MARK,
-	RTS4_MARK,	RXD4_MARK,	TXD4_MARK,
-
-	/* PTK (mobule: SERMUX, LBSC, SCIF) */
-	COM2_TXD_MARK,	COM2_RXD_MARK,	COM2_RTS_MARK,	COM2_CTS_MARK,
-	COM2_DTR_MARK,	COM2_DSR_MARK,	COM2_DCD_MARK,	CLKOUT_MARK,
-	SCK2_MARK,	SCK4_MARK,	SCK3_MARK,
-
-	/* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */
-	RAC_RXD_MARK,	RAC_RTS_MARK,	RAC_CTS_MARK,	RAC_DTR_MARK,
-	RAC_DSR_MARK,	RAC_DCD_MARK,	RAC_TXD_MARK,	RXD2_MARK,
-	CS5_MARK,	CS6_MARK,	AUDSYNC_MARK,	AUDCK_MARK,
-	TXD2_MARK,
-
-	/* PTM (mobule: LBSC, IIC) */
-	CS4_MARK,	RD_MARK,	WE0_MARK,	CS0_MARK,
-	SDA6_MARK,	SCL6_MARK,	SDA7_MARK,	SCL7_MARK,
-
-	/* PTN (mobule: USB, JMC, SGPIO, WDT) */
-	VBUS_EN_MARK,	VBUS_OC_MARK,	JMCTCK_MARK,	JMCTMS_MARK,
-	JMCTDO_MARK,	JMCTDI_MARK,	JMCTRST_MARK,
-	SGPIO1_CLK_MARK,	SGPIO1_LOAD_MARK,	SGPIO1_DI_MARK,
-	SGPIO1_DO_MARK,		SUB_CLKIN_MARK,
-
-	/* PTO (mobule: SGPIO, SerMux) */
-	SGPIO0_CLK_MARK,	SGPIO0_LOAD_MARK,	SGPIO0_DI_MARK,
-	SGPIO0_DO_MARK,		SGPIO2_CLK_MARK,	SGPIO2_LOAD_MARK,
-	SGPIO2_DI_MARK,		SGPIO2_DO_MARK,
-	COM1_TXD_MARK,	COM1_RXD_MARK,	COM1_RTS_MARK,	COM1_CTS_MARK,
-
-	/* PTQ (mobule: LPC) */
-	LAD3_MARK,	LAD2_MARK,	LAD1_MARK,	LAD0_MARK,
-	LFRAME_MARK,	LRESET_MARK,	LCLK_MARK,
-
-	/* PTR (mobule: GRA, IIC) */
-	DDC3_MARK,	DDC2_MARK,	SDA2_MARK,	SCL2_MARK,
-	SDA1_MARK,	SCL1_MARK,	SDA0_MARK,	SCL0_MARK,
-	SDA8_MARK,	SCL8_MARK,
-
-	/* PTS (mobule: GRA, IIC) */
-	DDC1_MARK,	DDC0_MARK,	SDA5_MARK,	SCL5_MARK,
-	SDA4_MARK,	SCL4_MARK,	SDA3_MARK,	SCL3_MARK,
-	SDA9_MARK,	SCL9_MARK,
-
-	/* PTT (mobule: PWMX, AUD) */
-	PWMX7_MARK,	PWMX6_MARK,	PWMX5_MARK,	PWMX4_MARK,
-	PWMX3_MARK,	PWMX2_MARK,	PWMX1_MARK,	PWMX0_MARK,
-	AUDATA3_MARK,	AUDATA2_MARK,	AUDATA1_MARK,	AUDATA0_MARK,
-	STATUS1_MARK,	STATUS0_MARK,
-
-	/* PTU (mobule: LPC, APM) */
-	LGPIO7_MARK,	LGPIO6_MARK,	LGPIO5_MARK,	LGPIO4_MARK,
-	LGPIO3_MARK,	LGPIO2_MARK,	LGPIO1_MARK,	LGPIO0_MARK,
-	APMONCTL_O_MARK,	APMPWBTOUT_O_MARK,	APMSCI_O_MARK,
-	APMVDDON_MARK,	APMSLPBTN_MARK,	APMPWRBTN_MARK,	APMS5N_MARK,
-	APMS3N_MARK,
-
-	/* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */
-	A23_MARK,	A22_MARK,	A21_MARK,	A20_MARK,
-	A19_MARK,	A18_MARK,	A17_MARK,	A16_MARK,
-	COM2_RI_MARK,		R_SPI_MOSI_MARK,	R_SPI_MISO_MARK,
-	R_SPI_RSPCK_MARK,	R_SPI_SSL0_MARK,	R_SPI_SSL1_MARK,
-	EVENT7_MARK,	EVENT6_MARK,	VBIOS_DI_MARK,	VBIOS_DO_MARK,
-	VBIOS_CLK_MARK,	VBIOS_CS_MARK,
-
-	/* PTW (mobule: LBSC, EVC, SCIF) */
-	A15_MARK,	A14_MARK,	A13_MARK,	A12_MARK,
-	A11_MARK,	A10_MARK,	A9_MARK,	A8_MARK,
-	EVENT5_MARK,	EVENT4_MARK,	EVENT3_MARK,	EVENT2_MARK,
-	EVENT1_MARK,	EVENT0_MARK,	CTS4_MARK,	CTS2_MARK,
-
-	/* PTX (mobule: LBSC, SCIF, SIM) */
-	A7_MARK,	A6_MARK,	A5_MARK,	A4_MARK,
-	A3_MARK,	A2_MARK,	A1_MARK,	A0_MARK,
-	RTS2_MARK,	SIM_D_MARK,	SIM_CLK_MARK,	SIM_RST_MARK,
-
-	/* PTY (mobule: LBSC) */
-	D7_MARK,	D6_MARK,	D5_MARK,	D4_MARK,
-	D3_MARK,	D2_MARK,	D1_MARK,	D0_MARK,
-
-	/* PTZ (mobule: eMMC, ONFI) */
-	MMCDAT7_MARK,	MMCDAT6_MARK,	MMCDAT5_MARK,	MMCDAT4_MARK,
-	MMCDAT3_MARK,	MMCDAT2_MARK,	MMCDAT1_MARK,	MMCDAT0_MARK,
-	ON_DQ7_MARK,	ON_DQ6_MARK,	ON_DQ5_MARK,	ON_DQ4_MARK,
-	ON_DQ3_MARK,	ON_DQ2_MARK,	ON_DQ1_MARK,	ON_DQ0_MARK,
-
-	PINMUX_MARK_END,
-};
-
-static const u16 pinmux_data[] = {
-	/* PTA GPIO */
-	PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
-	PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
-	PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT),
-	PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT),
-	PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT),
-	PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT),
-	PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT),
-	PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT),
-
-	/* PTB GPIO */
-	PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT),
-	PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT),
-	PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT),
-	PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT),
-	PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT),
-	PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT),
-	PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT),
-	PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT),
-
-	/* PTC GPIO */
-	PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT),
-	PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT),
-	PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT),
-	PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT),
-	PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT),
-	PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT),
-	PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT),
-	PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT),
-
-	/* PTD GPIO */
-	PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT),
-	PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT),
-	PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT),
-	PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT),
-	PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT),
-	PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT),
-	PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT),
-	PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT),
-
-	/* PTE GPIO */
-	PINMUX_DATA(PTE7_DATA, PTE7_IN, PTE7_OUT),
-	PINMUX_DATA(PTE6_DATA, PTE6_IN, PTE6_OUT),
-	PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT),
-	PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT),
-	PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT),
-	PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT),
-	PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT),
-	PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT),
-
-	/* PTF GPIO */
-	PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT),
-	PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT),
-	PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT),
-	PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT),
-	PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT),
-	PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT),
-	PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT),
-	PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT),
-
-	/* PTG GPIO */
-	PINMUX_DATA(PTG7_DATA, PTG7_IN, PTG7_OUT),
-	PINMUX_DATA(PTG6_DATA, PTG6_IN, PTG6_OUT),
-	PINMUX_DATA(PTG5_DATA, PTG5_IN, PTG5_OUT),
-	PINMUX_DATA(PTG4_DATA, PTG4_IN, PTG4_OUT),
-	PINMUX_DATA(PTG3_DATA, PTG3_IN, PTG3_OUT),
-	PINMUX_DATA(PTG2_DATA, PTG2_IN, PTG2_OUT),
-	PINMUX_DATA(PTG1_DATA, PTG1_IN, PTG1_OUT),
-	PINMUX_DATA(PTG0_DATA, PTG0_IN, PTG0_OUT),
-
-	/* PTH GPIO */
-	PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT),
-	PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT),
-	PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT),
-	PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT),
-	PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT),
-	PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT),
-	PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT),
-	PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT),
-
-	/* PTI GPIO */
-	PINMUX_DATA(PTI7_DATA, PTI7_IN, PTI7_OUT),
-	PINMUX_DATA(PTI6_DATA, PTI6_IN, PTI6_OUT),
-	PINMUX_DATA(PTI5_DATA, PTI5_IN, PTI5_OUT),
-	PINMUX_DATA(PTI4_DATA, PTI4_IN, PTI4_OUT),
-	PINMUX_DATA(PTI3_DATA, PTI3_IN, PTI3_OUT),
-	PINMUX_DATA(PTI2_DATA, PTI2_IN, PTI2_OUT),
-	PINMUX_DATA(PTI1_DATA, PTI1_IN, PTI1_OUT),
-	PINMUX_DATA(PTI0_DATA, PTI0_IN, PTI0_OUT),
-
-	/* PTJ GPIO */
-	PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT),
-	PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT),
-	PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT),
-	PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT),
-	PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT),
-	PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT),
-	PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT),
-
-	/* PTK GPIO */
-	PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT),
-	PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT),
-	PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT),
-	PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT),
-	PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT),
-	PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT),
-	PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT),
-	PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT),
-
-	/* PTL GPIO */
-	PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT),
-	PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT),
-	PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT),
-	PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT),
-	PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT),
-	PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT),
-	PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT),
-
-	/* PTM GPIO */
-	PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT),
-	PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT),
-	PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT),
-	PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT),
-	PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT),
-	PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT),
-	PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT),
-
-	/* PTN GPIO */
-	PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT),
-	PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT),
-	PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT),
-	PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT),
-	PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT),
-	PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT),
-	PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT),
-
-	/* PTO GPIO */
-	PINMUX_DATA(PTO7_DATA, PTO7_IN, PTO7_OUT),
-	PINMUX_DATA(PTO6_DATA, PTO6_IN, PTO6_OUT),
-	PINMUX_DATA(PTO5_DATA, PTO5_IN, PTO5_OUT),
-	PINMUX_DATA(PTO4_DATA, PTO4_IN, PTO4_OUT),
-	PINMUX_DATA(PTO3_DATA, PTO3_IN, PTO3_OUT),
-	PINMUX_DATA(PTO2_DATA, PTO2_IN, PTO2_OUT),
-	PINMUX_DATA(PTO1_DATA, PTO1_IN, PTO1_OUT),
-	PINMUX_DATA(PTO0_DATA, PTO0_IN, PTO0_OUT),
-
-	/* PTQ GPIO */
-	PINMUX_DATA(PTQ6_DATA, PTQ6_IN, PTQ6_OUT),
-	PINMUX_DATA(PTQ5_DATA, PTQ5_IN, PTQ5_OUT),
-	PINMUX_DATA(PTQ4_DATA, PTQ4_IN, PTQ4_OUT),
-	PINMUX_DATA(PTQ3_DATA, PTQ3_IN, PTQ3_OUT),
-	PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_OUT),
-	PINMUX_DATA(PTQ1_DATA, PTQ1_IN, PTQ1_OUT),
-	PINMUX_DATA(PTQ0_DATA, PTQ0_IN, PTQ0_OUT),
-
-	/* PTR GPIO */
-	PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT),
-	PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT),
-	PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT),
-	PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT),
-	PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_OUT),
-	PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_OUT),
-	PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT),
-	PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT),
-
-	/* PTS GPIO */
-	PINMUX_DATA(PTS7_DATA, PTS7_IN, PTS7_OUT),
-	PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT),
-	PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT),
-	PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT),
-	PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT),
-	PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT),
-	PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT),
-	PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT),
-
-	/* PTT GPIO */
-	PINMUX_DATA(PTT7_DATA, PTT7_IN, PTT7_OUT),
-	PINMUX_DATA(PTT6_DATA, PTT6_IN, PTT6_OUT),
-	PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT),
-	PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT),
-	PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT),
-	PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT),
-	PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT),
-	PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT),
-
-	/* PTU GPIO */
-	PINMUX_DATA(PTU7_DATA, PTU7_IN, PTU7_OUT),
-	PINMUX_DATA(PTU6_DATA, PTU6_IN, PTU6_OUT),
-	PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT),
-	PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT),
-	PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT),
-	PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT),
-	PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT),
-	PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT),
-
-	/* PTV GPIO */
-	PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT),
-	PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT),
-	PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT),
-	PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT),
-	PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT),
-	PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT),
-	PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT),
-	PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT),
-
-	/* PTW GPIO */
-	PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT),
-	PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT),
-	PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT),
-	PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT),
-	PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT),
-	PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT),
-	PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT),
-	PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT),
-
-	/* PTX GPIO */
-	PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT),
-	PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT),
-	PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT),
-	PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT),
-	PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT),
-	PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT),
-	PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT),
-	PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT),
-
-	/* PTY GPIO */
-	PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT),
-	PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT),
-	PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT),
-	PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT),
-	PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT),
-	PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT),
-	PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT),
-	PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT),
-
-	/* PTZ GPIO */
-	PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT),
-	PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT),
-	PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT),
-	PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT),
-	PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT),
-	PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT),
-	PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT),
-	PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT),
-
-	/* PTA FN */
-	PINMUX_DATA(BS_MARK, PTA7_FN),
-	PINMUX_DATA(RDWR_MARK, PTA6_FN),
-	PINMUX_DATA(WE1_MARK, PTA5_FN),
-	PINMUX_DATA(RDY_MARK, PTA4_FN),
-	PINMUX_DATA(ET0_MDC_MARK, PTA3_FN),
-	PINMUX_DATA(ET0_MDIO_MARK, PTA2_FN),
-	PINMUX_DATA(ET1_MDC_MARK, PTA1_FN),
-	PINMUX_DATA(ET1_MDIO_MARK, PTA0_FN),
-
-	/* PTB FN */
-	PINMUX_DATA(IRQ15_MARK, PS0_15_FN1, PTB7_FN),
-	PINMUX_DATA(ON_NRE_MARK, PS0_15_FN2, PTB7_FN),
-	PINMUX_DATA(IRQ14_MARK, PS0_14_FN1, PTB6_FN),
-	PINMUX_DATA(ON_NWE_MARK, PS0_14_FN2, PTB6_FN),
-	PINMUX_DATA(IRQ13_MARK, PS0_13_FN1, PTB5_FN),
-	PINMUX_DATA(ON_NWP_MARK, PS0_13_FN2, PTB5_FN),
-	PINMUX_DATA(IRQ12_MARK, PS0_12_FN1, PTB4_FN),
-	PINMUX_DATA(ON_NCE0_MARK, PS0_12_FN2, PTB4_FN),
-	PINMUX_DATA(IRQ11_MARK, PS0_11_FN1, PTB3_FN),
-	PINMUX_DATA(ON_R_B0_MARK, PS0_11_FN2, PTB3_FN),
-	PINMUX_DATA(IRQ10_MARK, PS0_10_FN1, PTB2_FN),
-	PINMUX_DATA(ON_ALE_MARK, PS0_10_FN2, PTB2_FN),
-	PINMUX_DATA(IRQ9_MARK, PS0_9_FN1, PTB1_FN),
-	PINMUX_DATA(ON_CLE_MARK, PS0_9_FN2, PTB1_FN),
-	PINMUX_DATA(IRQ8_MARK, PS0_8_FN1, PTB0_FN),
-	PINMUX_DATA(TCLK_MARK, PS0_8_FN2, PTB0_FN),
-
-	/* PTC FN */
-	PINMUX_DATA(IRQ7_MARK, PS0_7_FN1, PTC7_FN),
-	PINMUX_DATA(PWMU0_MARK, PS0_7_FN2, PTC7_FN),
-	PINMUX_DATA(IRQ6_MARK, PS0_6_FN1, PTC6_FN),
-	PINMUX_DATA(PWMU1_MARK, PS0_6_FN2, PTC6_FN),
-	PINMUX_DATA(IRQ5_MARK, PS0_5_FN1, PTC5_FN),
-	PINMUX_DATA(PWMU2_MARK, PS0_5_FN2, PTC5_FN),
-	PINMUX_DATA(IRQ4_MARK, PS0_4_FN1, PTC5_FN),
-	PINMUX_DATA(PWMU3_MARK, PS0_4_FN2, PTC4_FN),
-	PINMUX_DATA(IRQ3_MARK, PS0_3_FN1, PTC3_FN),
-	PINMUX_DATA(PWMU4_MARK, PS0_3_FN2, PTC3_FN),
-	PINMUX_DATA(IRQ2_MARK, PS0_2_FN1, PTC2_FN),
-	PINMUX_DATA(PWMU5_MARK, PS0_2_FN2, PTC2_FN),
-	PINMUX_DATA(IRQ1_MARK, PTC1_FN),
-	PINMUX_DATA(IRQ0_MARK, PTC0_FN),
-
-	/* PTD FN */
-	PINMUX_DATA(SP0_MOSI_MARK, PTD7_FN),
-	PINMUX_DATA(SP0_MISO_MARK, PTD6_FN),
-	PINMUX_DATA(SP0_SCK_MARK, PTD5_FN),
-	PINMUX_DATA(SP0_SCK_FB_MARK, PTD4_FN),
-	PINMUX_DATA(SP0_SS0_MARK, PTD3_FN),
-	PINMUX_DATA(SP0_SS1_MARK, PS1_10_FN1, PTD2_FN),
-	PINMUX_DATA(DREQ0_MARK, PS1_10_FN2, PTD2_FN),
-	PINMUX_DATA(SP0_SS2_MARK, PS1_9_FN1, PTD1_FN),
-	PINMUX_DATA(DACK0_MARK, PS1_9_FN2, PTD1_FN),
-	PINMUX_DATA(SP0_SS3_MARK, PS1_8_FN1, PTD0_FN),
-	PINMUX_DATA(TEND0_MARK, PS1_8_FN2, PTD0_FN),
-
-	/* PTE FN */
-	PINMUX_DATA(RMII0_CRS_DV_MARK, PTE7_FN),
-	PINMUX_DATA(RMII0_TXD1_MARK, PTE6_FN),
-	PINMUX_DATA(RMII0_TXD0_MARK, PTE5_FN),
-	PINMUX_DATA(RMII0_TXEN_MARK, PTE4_FN),
-	PINMUX_DATA(RMII0_REFCLK_MARK, PTE3_FN),
-	PINMUX_DATA(RMII0_RXD1_MARK, PTE2_FN),
-	PINMUX_DATA(RMII0_RXD0_MARK, PTE1_FN),
-	PINMUX_DATA(RMII0_RX_ER_MARK, PTE0_FN),
-
-	/* PTF FN */
-	PINMUX_DATA(RMII1_CRS_DV_MARK, PTF7_FN),
-	PINMUX_DATA(RMII1_TXD1_MARK, PTF6_FN),
-	PINMUX_DATA(RMII1_TXD0_MARK, PTF5_FN),
-	PINMUX_DATA(RMII1_TXEN_MARK, PTF4_FN),
-	PINMUX_DATA(RMII1_REFCLK_MARK, PTF3_FN),
-	PINMUX_DATA(RMII1_RXD1_MARK, PS1_2_FN1, PTF2_FN),
-	PINMUX_DATA(RAC_RI_MARK, PS1_2_FN2, PTF2_FN),
-	PINMUX_DATA(RMII1_RXD0_MARK, PTF1_FN),
-	PINMUX_DATA(RMII1_RX_ER_MARK, PTF0_FN),
-
-	/* PTG FN */
-	PINMUX_DATA(BOOTFMS_MARK, PTG7_FN),
-	PINMUX_DATA(BOOTWP_MARK, PTG6_FN),
-	PINMUX_DATA(A25_MARK, PS2_13_FN1, PTG5_FN),
-	PINMUX_DATA(MMCCLK_MARK, PS2_13_FN2, PTG5_FN),
-	PINMUX_DATA(A24_MARK, PS2_12_FN1, PTG4_FN),
-	PINMUX_DATA(MMCCMD_MARK, PS2_12_FN2, PTG4_FN),
-	PINMUX_DATA(SERIRQ_MARK, PTG3_FN),
-	PINMUX_DATA(WDTOVF_MARK, PTG2_FN),
-	PINMUX_DATA(LPCPD_MARK, PTG1_FN),
-	PINMUX_DATA(LDRQ_MARK, PTG0_FN),
-
-	/* PTH FN */
-	PINMUX_DATA(SP1_MOSI_MARK, PS2_7_FN1, PTH7_FN),
-	PINMUX_DATA(TEND1_MARK, PS2_7_FN2, PTH7_FN),
-	PINMUX_DATA(SP1_MISO_MARK, PS2_6_FN1, PTH6_FN),
-	PINMUX_DATA(DREQ1_MARK, PS2_6_FN2, PTH6_FN),
-	PINMUX_DATA(SP1_SCK_MARK, PS2_5_FN1, PTH5_FN),
-	PINMUX_DATA(DACK1_MARK, PS2_5_FN2, PTH5_FN),
-	PINMUX_DATA(SP1_SCK_FB_MARK, PS2_4_FN1, PTH4_FN),
-	PINMUX_DATA(ADTRG1_MARK, PS2_4_FN2, PTH4_FN),
-	PINMUX_DATA(SP1_SS0_MARK, PTH3_FN),
-	PINMUX_DATA(SP1_SS1_MARK, PS2_2_FN1, PTH2_FN),
-	PINMUX_DATA(ADTRG0_MARK, PS2_2_FN2, PTH2_FN),
-	PINMUX_DATA(WP_MARK, PTH1_FN),
-	PINMUX_DATA(FMS0_MARK, PTH0_FN),
-
-	/* PTI FN */
-	PINMUX_DATA(D15_MARK, PS3_15_FN1, PTI7_FN),
-	PINMUX_DATA(SD_WP_MARK, PS3_15_FN2, PTI7_FN),
-	PINMUX_DATA(D14_MARK, PS3_14_FN1, PTI6_FN),
-	PINMUX_DATA(SD_CD_MARK, PS3_14_FN2, PTI6_FN),
-	PINMUX_DATA(D13_MARK, PS3_13_FN1, PTI5_FN),
-	PINMUX_DATA(SD_CLK_MARK, PS3_13_FN2, PTI5_FN),
-	PINMUX_DATA(D12_MARK, PS3_12_FN1, PTI4_FN),
-	PINMUX_DATA(SD_CMD_MARK, PS3_12_FN2, PTI4_FN),
-	PINMUX_DATA(D11_MARK, PS3_11_FN1, PTI3_FN),
-	PINMUX_DATA(SD_D3_MARK, PS3_11_FN2, PTI3_FN),
-	PINMUX_DATA(D10_MARK, PS3_10_FN1, PTI2_FN),
-	PINMUX_DATA(SD_D2_MARK, PS3_10_FN2, PTI2_FN),
-	PINMUX_DATA(D9_MARK, PS3_9_FN1, PTI1_FN),
-	PINMUX_DATA(SD_D1_MARK, PS3_9_FN2, PTI1_FN),
-	PINMUX_DATA(D8_MARK, PS3_8_FN1, PTI0_FN),
-	PINMUX_DATA(SD_D0_MARK, PS3_8_FN2, PTI0_FN),
-
-	/* PTJ FN */
-	PINMUX_DATA(RTS3_MARK, PTJ6_FN),
-	PINMUX_DATA(CTS3_MARK, PTJ5_FN),
-	PINMUX_DATA(TXD3_MARK, PTJ4_FN),
-	PINMUX_DATA(RXD3_MARK, PTJ3_FN),
-	PINMUX_DATA(RTS4_MARK, PTJ2_FN),
-	PINMUX_DATA(RXD4_MARK, PTJ1_FN),
-	PINMUX_DATA(TXD4_MARK, PTJ0_FN),
-
-	/* PTK FN */
-	PINMUX_DATA(COM2_TXD_MARK, PS3_7_FN1, PTK7_FN),
-	PINMUX_DATA(SCK2_MARK, PS3_7_FN2, PTK7_FN),
-	PINMUX_DATA(COM2_RXD_MARK, PTK6_FN),
-	PINMUX_DATA(COM2_RTS_MARK, PTK5_FN),
-	PINMUX_DATA(COM2_CTS_MARK, PTK4_FN),
-	PINMUX_DATA(COM2_DTR_MARK, PTK3_FN),
-	PINMUX_DATA(COM2_DSR_MARK, PS3_2_FN1, PTK2_FN),
-	PINMUX_DATA(SCK4_MARK, PS3_2_FN2, PTK2_FN),
-	PINMUX_DATA(COM2_DCD_MARK, PS3_1_FN1, PTK1_FN),
-	PINMUX_DATA(SCK3_MARK, PS3_1_FN2, PTK1_FN),
-	PINMUX_DATA(CLKOUT_MARK, PTK0_FN),
-
-	/* PTL FN */
-	PINMUX_DATA(RAC_RXD_MARK, PS4_14_FN1, PTL6_FN),
-	PINMUX_DATA(RXD2_MARK, PS4_14_FN2, PTL6_FN),
-	PINMUX_DATA(RAC_RTS_MARK, PS4_13_FN1, PTL5_FN),
-	PINMUX_DATA(CS5_MARK, PS4_13_FN2, PTL5_FN),
-	PINMUX_DATA(RAC_CTS_MARK, PS4_12_FN1, PTL4_FN),
-	PINMUX_DATA(CS6_MARK, PS4_12_FN2, PTL4_FN),
-	PINMUX_DATA(RAC_DTR_MARK, PTL3_FN),
-	PINMUX_DATA(RAC_DSR_MARK, PS4_10_FN1, PTL2_FN),
-	PINMUX_DATA(AUDSYNC_MARK, PS4_10_FN2, PTL2_FN),
-	PINMUX_DATA(RAC_DCD_MARK, PS4_9_FN1, PTL1_FN),
-	PINMUX_DATA(AUDCK_MARK, PS4_9_FN2, PTL1_FN),
-	PINMUX_DATA(RAC_TXD_MARK, PS4_8_FN1, PTL0_FN),
-	PINMUX_DATA(TXD2_MARK, PS4_8_FN1, PTL0_FN),
-
-	/* PTM FN */
-	PINMUX_DATA(CS4_MARK, PTM7_FN),
-	PINMUX_DATA(RD_MARK, PTM6_FN),
-	PINMUX_DATA(WE0_MARK, PTM7_FN),
-	PINMUX_DATA(CS0_MARK, PTM4_FN),
-	PINMUX_DATA(SDA6_MARK, PTM3_FN),
-	PINMUX_DATA(SCL6_MARK, PTM2_FN),
-	PINMUX_DATA(SDA7_MARK, PTM1_FN),
-	PINMUX_DATA(SCL7_MARK, PTM0_FN),
-
-	/* PTN FN */
-	PINMUX_DATA(VBUS_EN_MARK, PTN6_FN),
-	PINMUX_DATA(VBUS_OC_MARK, PTN5_FN),
-	PINMUX_DATA(JMCTCK_MARK, PS4_4_FN1, PTN4_FN),
-	PINMUX_DATA(SGPIO1_CLK_MARK, PS4_4_FN2, PTN4_FN),
-	PINMUX_DATA(JMCTMS_MARK, PS4_3_FN1, PTN5_FN),
-	PINMUX_DATA(SGPIO1_LOAD_MARK, PS4_3_FN2, PTN5_FN),
-	PINMUX_DATA(JMCTDO_MARK, PS4_2_FN1, PTN2_FN),
-	PINMUX_DATA(SGPIO1_DO_MARK, PS4_2_FN2, PTN2_FN),
-	PINMUX_DATA(JMCTDI_MARK, PS4_1_FN1, PTN1_FN),
-	PINMUX_DATA(SGPIO1_DI_MARK, PS4_1_FN2, PTN1_FN),
-	PINMUX_DATA(JMCTRST_MARK, PS4_0_FN1, PTN0_FN),
-	PINMUX_DATA(SUB_CLKIN_MARK, PS4_0_FN2, PTN0_FN),
-
-	/* PTO FN */
-	PINMUX_DATA(SGPIO0_CLK_MARK, PTO7_FN),
-	PINMUX_DATA(SGPIO0_LOAD_MARK, PTO6_FN),
-	PINMUX_DATA(SGPIO0_DI_MARK, PTO5_FN),
-	PINMUX_DATA(SGPIO0_DO_MARK, PTO4_FN),
-	PINMUX_DATA(SGPIO2_CLK_MARK, PS5_11_FN1, PTO3_FN),
-	PINMUX_DATA(COM1_TXD_MARK, PS5_11_FN2, PTO3_FN),
-	PINMUX_DATA(SGPIO2_LOAD_MARK, PS5_10_FN1, PTO2_FN),
-	PINMUX_DATA(COM1_RXD_MARK, PS5_10_FN2, PTO2_FN),
-	PINMUX_DATA(SGPIO2_DI_MARK, PS5_9_FN1, PTO1_FN),
-	PINMUX_DATA(COM1_RTS_MARK, PS5_9_FN2, PTO1_FN),
-	PINMUX_DATA(SGPIO2_DO_MARK, PS5_8_FN1, PTO0_FN),
-	PINMUX_DATA(COM1_CTS_MARK, PS5_8_FN2, PTO0_FN),
-
-	/* PTP FN */
-
-	/* PTQ FN */
-	PINMUX_DATA(LAD3_MARK, PTQ6_FN),
-	PINMUX_DATA(LAD2_MARK, PTQ5_FN),
-	PINMUX_DATA(LAD1_MARK, PTQ4_FN),
-	PINMUX_DATA(LAD0_MARK, PTQ3_FN),
-	PINMUX_DATA(LFRAME_MARK, PTQ2_FN),
-	PINMUX_DATA(LRESET_MARK, PTQ1_FN),
-	PINMUX_DATA(LCLK_MARK, PTQ0_FN),
-
-	/* PTR FN */
-	PINMUX_DATA(SDA8_MARK, PTR7_FN),	/* DDC3? */
-	PINMUX_DATA(SCL8_MARK, PTR6_FN),	/* DDC2? */
-	PINMUX_DATA(SDA2_MARK, PTR5_FN),
-	PINMUX_DATA(SCL2_MARK, PTR4_FN),
-	PINMUX_DATA(SDA1_MARK, PTR3_FN),
-	PINMUX_DATA(SCL1_MARK, PTR2_FN),
-	PINMUX_DATA(SDA0_MARK, PTR1_FN),
-	PINMUX_DATA(SCL0_MARK, PTR0_FN),
-
-	/* PTS FN */
-	PINMUX_DATA(SDA9_MARK, PTS7_FN),	/* DDC1? */
-	PINMUX_DATA(SCL9_MARK, PTS6_FN),	/* DDC0? */
-	PINMUX_DATA(SDA5_MARK, PTS5_FN),
-	PINMUX_DATA(SCL5_MARK, PTS4_FN),
-	PINMUX_DATA(SDA4_MARK, PTS3_FN),
-	PINMUX_DATA(SCL4_MARK, PTS2_FN),
-	PINMUX_DATA(SDA3_MARK, PTS1_FN),
-	PINMUX_DATA(SCL3_MARK, PTS0_FN),
-
-	/* PTT FN */
-	PINMUX_DATA(PWMX7_MARK, PS5_7_FN1, PTT7_FN),
-	PINMUX_DATA(AUDATA3_MARK, PS5_7_FN2, PTT7_FN),
-	PINMUX_DATA(PWMX6_MARK, PS5_6_FN1, PTT6_FN),
-	PINMUX_DATA(AUDATA2_MARK, PS5_6_FN2, PTT6_FN),
-	PINMUX_DATA(PWMX5_MARK, PS5_5_FN1, PTT5_FN),
-	PINMUX_DATA(AUDATA1_MARK, PS5_5_FN2, PTT5_FN),
-	PINMUX_DATA(PWMX4_MARK, PS5_4_FN1, PTT4_FN),
-	PINMUX_DATA(AUDATA0_MARK, PS5_4_FN2, PTT4_FN),
-	PINMUX_DATA(PWMX3_MARK, PS5_3_FN1, PTT3_FN),
-	PINMUX_DATA(STATUS1_MARK, PS5_3_FN2, PTT3_FN),
-	PINMUX_DATA(PWMX2_MARK, PS5_2_FN1, PTT2_FN),
-	PINMUX_DATA(STATUS0_MARK, PS5_2_FN2, PTT2_FN),
-	PINMUX_DATA(PWMX1_MARK, PTT1_FN),
-	PINMUX_DATA(PWMX0_MARK, PTT0_FN),
-
-	/* PTU FN */
-	PINMUX_DATA(LGPIO7_MARK, PS6_15_FN1, PTU7_FN),
-	PINMUX_DATA(APMONCTL_O_MARK, PS6_15_FN2, PTU7_FN),
-	PINMUX_DATA(LGPIO6_MARK, PS6_14_FN1, PTU6_FN),
-	PINMUX_DATA(APMPWBTOUT_O_MARK, PS6_14_FN2, PTU6_FN),
-	PINMUX_DATA(LGPIO5_MARK, PS6_13_FN1, PTU5_FN),
-	PINMUX_DATA(APMSCI_O_MARK, PS6_13_FN2, PTU5_FN),
-	PINMUX_DATA(LGPIO4_MARK, PS6_12_FN1, PTU4_FN),
-	PINMUX_DATA(APMVDDON_MARK, PS6_12_FN2, PTU4_FN),
-	PINMUX_DATA(LGPIO3_MARK, PS6_11_FN1, PTU3_FN),
-	PINMUX_DATA(APMSLPBTN_MARK, PS6_11_FN2, PTU3_FN),
-	PINMUX_DATA(LGPIO2_MARK, PS6_10_FN1, PTU2_FN),
-	PINMUX_DATA(APMPWRBTN_MARK, PS6_10_FN2, PTU2_FN),
-	PINMUX_DATA(LGPIO1_MARK, PS6_9_FN1, PTU1_FN),
-	PINMUX_DATA(APMS5N_MARK, PS6_9_FN2, PTU1_FN),
-	PINMUX_DATA(LGPIO0_MARK, PS6_8_FN1, PTU0_FN),
-	PINMUX_DATA(APMS3N_MARK, PS6_8_FN2, PTU0_FN),
-
-	/* PTV FN */
-	PINMUX_DATA(A23_MARK, PS6_7_FN1, PTV7_FN),
-	PINMUX_DATA(COM2_RI_MARK, PS6_7_FN2, PTV7_FN),
-	PINMUX_DATA(A22_MARK, PS6_6_FN1, PTV6_FN),
-	PINMUX_DATA(R_SPI_MOSI_MARK, PS6_6_FN2, PTV6_FN),
-	PINMUX_DATA(A21_MARK, PS6_5_FN1, PTV5_FN),
-	PINMUX_DATA(R_SPI_MISO_MARK, PS6_5_FN2, PTV5_FN),
-	PINMUX_DATA(A20_MARK, PS6_4_FN1, PTV4_FN),
-	PINMUX_DATA(R_SPI_RSPCK_MARK, PS6_4_FN2, PTV4_FN),
-	PINMUX_DATA(A19_MARK, PS6_3_FN1, PTV3_FN),
-	PINMUX_DATA(R_SPI_SSL0_MARK, PS6_3_FN2, PTV3_FN),
-	PINMUX_DATA(A18_MARK, PS6_2_FN1, PTV2_FN),
-	PINMUX_DATA(R_SPI_SSL1_MARK, PS6_2_FN2, PTV2_FN),
-	PINMUX_DATA(A17_MARK, PS6_1_FN1, PTV1_FN),
-	PINMUX_DATA(EVENT7_MARK, PS6_1_FN2, PTV1_FN),
-	PINMUX_DATA(A16_MARK, PS6_0_FN1, PTV0_FN),
-	PINMUX_DATA(EVENT6_MARK, PS6_0_FN1, PTV0_FN),
-
-	/* PTW FN */
-	PINMUX_DATA(A15_MARK, PS7_15_FN1, PTW7_FN),
-	PINMUX_DATA(EVENT5_MARK, PS7_15_FN2, PTW7_FN),
-	PINMUX_DATA(A14_MARK, PS7_14_FN1, PTW6_FN),
-	PINMUX_DATA(EVENT4_MARK, PS7_14_FN2, PTW6_FN),
-	PINMUX_DATA(A13_MARK, PS7_13_FN1, PTW5_FN),
-	PINMUX_DATA(EVENT3_MARK, PS7_13_FN2, PTW5_FN),
-	PINMUX_DATA(A12_MARK, PS7_12_FN1, PTW4_FN),
-	PINMUX_DATA(EVENT2_MARK, PS7_12_FN2, PTW4_FN),
-	PINMUX_DATA(A11_MARK, PS7_11_FN1, PTW3_FN),
-	PINMUX_DATA(EVENT1_MARK, PS7_11_FN2, PTW3_FN),
-	PINMUX_DATA(A10_MARK, PS7_10_FN1, PTW2_FN),
-	PINMUX_DATA(EVENT0_MARK, PS7_10_FN2, PTW2_FN),
-	PINMUX_DATA(A9_MARK, PS7_9_FN1, PTW1_FN),
-	PINMUX_DATA(CTS4_MARK, PS7_9_FN2, PTW1_FN),
-	PINMUX_DATA(A8_MARK, PS7_8_FN1, PTW0_FN),
-	PINMUX_DATA(CTS2_MARK, PS7_8_FN2, PTW0_FN),
-
-	/* PTX FN */
-	PINMUX_DATA(A7_MARK, PS7_7_FN1, PTX7_FN),
-	PINMUX_DATA(RTS2_MARK, PS7_7_FN2, PTX7_FN),
-	PINMUX_DATA(A6_MARK, PS7_6_FN1, PTX6_FN),
-	PINMUX_DATA(SIM_D_MARK, PS7_6_FN2, PTX6_FN),
-	PINMUX_DATA(A5_MARK, PS7_5_FN1, PTX5_FN),
-	PINMUX_DATA(SIM_CLK_MARK, PS7_5_FN2, PTX5_FN),
-	PINMUX_DATA(A4_MARK, PS7_4_FN1, PTX4_FN),
-	PINMUX_DATA(SIM_RST_MARK, PS7_4_FN2, PTX4_FN),
-	PINMUX_DATA(A3_MARK, PTX3_FN),
-	PINMUX_DATA(A2_MARK, PTX2_FN),
-	PINMUX_DATA(A1_MARK, PTX1_FN),
-	PINMUX_DATA(A0_MARK, PTX0_FN),
-
-	/* PTY FN */
-	PINMUX_DATA(D7_MARK, PTY7_FN),
-	PINMUX_DATA(D6_MARK, PTY6_FN),
-	PINMUX_DATA(D5_MARK, PTY5_FN),
-	PINMUX_DATA(D4_MARK, PTY4_FN),
-	PINMUX_DATA(D3_MARK, PTY3_FN),
-	PINMUX_DATA(D2_MARK, PTY2_FN),
-	PINMUX_DATA(D1_MARK, PTY1_FN),
-	PINMUX_DATA(D0_MARK, PTY0_FN),
-
-	/* PTZ FN */
-	PINMUX_DATA(MMCDAT7_MARK, PS8_15_FN1, PTZ7_FN),
-	PINMUX_DATA(ON_DQ7_MARK, PS8_15_FN2, PTZ7_FN),
-	PINMUX_DATA(MMCDAT6_MARK, PS8_14_FN1, PTZ6_FN),
-	PINMUX_DATA(ON_DQ6_MARK, PS8_14_FN2, PTZ6_FN),
-	PINMUX_DATA(MMCDAT5_MARK, PS8_13_FN1, PTZ5_FN),
-	PINMUX_DATA(ON_DQ5_MARK, PS8_13_FN2, PTZ5_FN),
-	PINMUX_DATA(MMCDAT4_MARK, PS8_12_FN1, PTZ4_FN),
-	PINMUX_DATA(ON_DQ4_MARK, PS8_12_FN2, PTZ4_FN),
-	PINMUX_DATA(MMCDAT3_MARK, PS8_11_FN1, PTZ3_FN),
-	PINMUX_DATA(ON_DQ3_MARK, PS8_11_FN2, PTZ3_FN),
-	PINMUX_DATA(MMCDAT2_MARK, PS8_10_FN1, PTZ2_FN),
-	PINMUX_DATA(ON_DQ2_MARK, PS8_10_FN2, PTZ2_FN),
-	PINMUX_DATA(MMCDAT1_MARK, PS8_9_FN1, PTZ1_FN),
-	PINMUX_DATA(ON_DQ1_MARK, PS8_9_FN2, PTZ1_FN),
-	PINMUX_DATA(MMCDAT0_MARK, PS8_8_FN1, PTZ0_FN),
-	PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	/* PTA */
-	PINMUX_GPIO(PTA7),
-	PINMUX_GPIO(PTA6),
-	PINMUX_GPIO(PTA5),
-	PINMUX_GPIO(PTA4),
-	PINMUX_GPIO(PTA3),
-	PINMUX_GPIO(PTA2),
-	PINMUX_GPIO(PTA1),
-	PINMUX_GPIO(PTA0),
-
-	/* PTB */
-	PINMUX_GPIO(PTB7),
-	PINMUX_GPIO(PTB6),
-	PINMUX_GPIO(PTB5),
-	PINMUX_GPIO(PTB4),
-	PINMUX_GPIO(PTB3),
-	PINMUX_GPIO(PTB2),
-	PINMUX_GPIO(PTB1),
-	PINMUX_GPIO(PTB0),
-
-	/* PTC */
-	PINMUX_GPIO(PTC7),
-	PINMUX_GPIO(PTC6),
-	PINMUX_GPIO(PTC5),
-	PINMUX_GPIO(PTC4),
-	PINMUX_GPIO(PTC3),
-	PINMUX_GPIO(PTC2),
-	PINMUX_GPIO(PTC1),
-	PINMUX_GPIO(PTC0),
-
-	/* PTD */
-	PINMUX_GPIO(PTD7),
-	PINMUX_GPIO(PTD6),
-	PINMUX_GPIO(PTD5),
-	PINMUX_GPIO(PTD4),
-	PINMUX_GPIO(PTD3),
-	PINMUX_GPIO(PTD2),
-	PINMUX_GPIO(PTD1),
-	PINMUX_GPIO(PTD0),
-
-	/* PTE */
-	PINMUX_GPIO(PTE7),
-	PINMUX_GPIO(PTE6),
-	PINMUX_GPIO(PTE5),
-	PINMUX_GPIO(PTE4),
-	PINMUX_GPIO(PTE3),
-	PINMUX_GPIO(PTE2),
-	PINMUX_GPIO(PTE1),
-	PINMUX_GPIO(PTE0),
-
-	/* PTF */
-	PINMUX_GPIO(PTF7),
-	PINMUX_GPIO(PTF6),
-	PINMUX_GPIO(PTF5),
-	PINMUX_GPIO(PTF4),
-	PINMUX_GPIO(PTF3),
-	PINMUX_GPIO(PTF2),
-	PINMUX_GPIO(PTF1),
-	PINMUX_GPIO(PTF0),
-
-	/* PTG */
-	PINMUX_GPIO(PTG7),
-	PINMUX_GPIO(PTG6),
-	PINMUX_GPIO(PTG5),
-	PINMUX_GPIO(PTG4),
-	PINMUX_GPIO(PTG3),
-	PINMUX_GPIO(PTG2),
-	PINMUX_GPIO(PTG1),
-	PINMUX_GPIO(PTG0),
-
-	/* PTH */
-	PINMUX_GPIO(PTH7),
-	PINMUX_GPIO(PTH6),
-	PINMUX_GPIO(PTH5),
-	PINMUX_GPIO(PTH4),
-	PINMUX_GPIO(PTH3),
-	PINMUX_GPIO(PTH2),
-	PINMUX_GPIO(PTH1),
-	PINMUX_GPIO(PTH0),
-
-	/* PTI */
-	PINMUX_GPIO(PTI7),
-	PINMUX_GPIO(PTI6),
-	PINMUX_GPIO(PTI5),
-	PINMUX_GPIO(PTI4),
-	PINMUX_GPIO(PTI3),
-	PINMUX_GPIO(PTI2),
-	PINMUX_GPIO(PTI1),
-	PINMUX_GPIO(PTI0),
-
-	/* PTJ */
-	PINMUX_GPIO(PTJ6),
-	PINMUX_GPIO(PTJ5),
-	PINMUX_GPIO(PTJ4),
-	PINMUX_GPIO(PTJ3),
-	PINMUX_GPIO(PTJ2),
-	PINMUX_GPIO(PTJ1),
-	PINMUX_GPIO(PTJ0),
-
-	/* PTK */
-	PINMUX_GPIO(PTK7),
-	PINMUX_GPIO(PTK6),
-	PINMUX_GPIO(PTK5),
-	PINMUX_GPIO(PTK4),
-	PINMUX_GPIO(PTK3),
-	PINMUX_GPIO(PTK2),
-	PINMUX_GPIO(PTK1),
-	PINMUX_GPIO(PTK0),
-
-	/* PTL */
-	PINMUX_GPIO(PTL6),
-	PINMUX_GPIO(PTL5),
-	PINMUX_GPIO(PTL4),
-	PINMUX_GPIO(PTL3),
-	PINMUX_GPIO(PTL2),
-	PINMUX_GPIO(PTL1),
-	PINMUX_GPIO(PTL0),
-
-	/* PTM */
-	PINMUX_GPIO(PTM7),
-	PINMUX_GPIO(PTM6),
-	PINMUX_GPIO(PTM5),
-	PINMUX_GPIO(PTM4),
-	PINMUX_GPIO(PTM3),
-	PINMUX_GPIO(PTM2),
-	PINMUX_GPIO(PTM1),
-	PINMUX_GPIO(PTM0),
-
-	/* PTN */
-	PINMUX_GPIO(PTN6),
-	PINMUX_GPIO(PTN5),
-	PINMUX_GPIO(PTN4),
-	PINMUX_GPIO(PTN3),
-	PINMUX_GPIO(PTN2),
-	PINMUX_GPIO(PTN1),
-	PINMUX_GPIO(PTN0),
-
-	/* PTO */
-	PINMUX_GPIO(PTO7),
-	PINMUX_GPIO(PTO6),
-	PINMUX_GPIO(PTO5),
-	PINMUX_GPIO(PTO4),
-	PINMUX_GPIO(PTO3),
-	PINMUX_GPIO(PTO2),
-	PINMUX_GPIO(PTO1),
-	PINMUX_GPIO(PTO0),
-
-	/* PTP */
-	PINMUX_GPIO(PTP7),
-	PINMUX_GPIO(PTP6),
-	PINMUX_GPIO(PTP5),
-	PINMUX_GPIO(PTP4),
-	PINMUX_GPIO(PTP3),
-	PINMUX_GPIO(PTP2),
-	PINMUX_GPIO(PTP1),
-	PINMUX_GPIO(PTP0),
-
-	/* PTQ */
-	PINMUX_GPIO(PTQ6),
-	PINMUX_GPIO(PTQ5),
-	PINMUX_GPIO(PTQ4),
-	PINMUX_GPIO(PTQ3),
-	PINMUX_GPIO(PTQ2),
-	PINMUX_GPIO(PTQ1),
-	PINMUX_GPIO(PTQ0),
-
-	/* PTR */
-	PINMUX_GPIO(PTR7),
-	PINMUX_GPIO(PTR6),
-	PINMUX_GPIO(PTR5),
-	PINMUX_GPIO(PTR4),
-	PINMUX_GPIO(PTR3),
-	PINMUX_GPIO(PTR2),
-	PINMUX_GPIO(PTR1),
-	PINMUX_GPIO(PTR0),
-
-	/* PTS */
-	PINMUX_GPIO(PTS7),
-	PINMUX_GPIO(PTS6),
-	PINMUX_GPIO(PTS5),
-	PINMUX_GPIO(PTS4),
-	PINMUX_GPIO(PTS3),
-	PINMUX_GPIO(PTS2),
-	PINMUX_GPIO(PTS1),
-	PINMUX_GPIO(PTS0),
-
-	/* PTT */
-	PINMUX_GPIO(PTT7),
-	PINMUX_GPIO(PTT6),
-	PINMUX_GPIO(PTT5),
-	PINMUX_GPIO(PTT4),
-	PINMUX_GPIO(PTT3),
-	PINMUX_GPIO(PTT2),
-	PINMUX_GPIO(PTT1),
-	PINMUX_GPIO(PTT0),
-
-	/* PTU */
-	PINMUX_GPIO(PTU7),
-	PINMUX_GPIO(PTU6),
-	PINMUX_GPIO(PTU5),
-	PINMUX_GPIO(PTU4),
-	PINMUX_GPIO(PTU3),
-	PINMUX_GPIO(PTU2),
-	PINMUX_GPIO(PTU1),
-	PINMUX_GPIO(PTU0),
-
-	/* PTV */
-	PINMUX_GPIO(PTV7),
-	PINMUX_GPIO(PTV6),
-	PINMUX_GPIO(PTV5),
-	PINMUX_GPIO(PTV4),
-	PINMUX_GPIO(PTV3),
-	PINMUX_GPIO(PTV2),
-	PINMUX_GPIO(PTV1),
-	PINMUX_GPIO(PTV0),
-
-	/* PTW */
-	PINMUX_GPIO(PTW7),
-	PINMUX_GPIO(PTW6),
-	PINMUX_GPIO(PTW5),
-	PINMUX_GPIO(PTW4),
-	PINMUX_GPIO(PTW3),
-	PINMUX_GPIO(PTW2),
-	PINMUX_GPIO(PTW1),
-	PINMUX_GPIO(PTW0),
-
-	/* PTX */
-	PINMUX_GPIO(PTX7),
-	PINMUX_GPIO(PTX6),
-	PINMUX_GPIO(PTX5),
-	PINMUX_GPIO(PTX4),
-	PINMUX_GPIO(PTX3),
-	PINMUX_GPIO(PTX2),
-	PINMUX_GPIO(PTX1),
-	PINMUX_GPIO(PTX0),
-
-	/* PTY */
-	PINMUX_GPIO(PTY7),
-	PINMUX_GPIO(PTY6),
-	PINMUX_GPIO(PTY5),
-	PINMUX_GPIO(PTY4),
-	PINMUX_GPIO(PTY3),
-	PINMUX_GPIO(PTY2),
-	PINMUX_GPIO(PTY1),
-	PINMUX_GPIO(PTY0),
-
-	/* PTZ */
-	PINMUX_GPIO(PTZ7),
-	PINMUX_GPIO(PTZ6),
-	PINMUX_GPIO(PTZ5),
-	PINMUX_GPIO(PTZ4),
-	PINMUX_GPIO(PTZ3),
-	PINMUX_GPIO(PTZ2),
-	PINMUX_GPIO(PTZ1),
-	PINMUX_GPIO(PTZ0),
-};
-
-#define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-	/* PTA (mobule: LBSC, RGMII) */
-	GPIO_FN(BS),
-	GPIO_FN(RDWR),
-	GPIO_FN(WE1),
-	GPIO_FN(RDY),
-	GPIO_FN(ET0_MDC),
-	GPIO_FN(ET0_MDIO),
-	GPIO_FN(ET1_MDC),
-	GPIO_FN(ET1_MDIO),
-
-	/* PTB (mobule: INTC, ONFI, TMU) */
-	GPIO_FN(IRQ15),
-	GPIO_FN(IRQ14),
-	GPIO_FN(IRQ13),
-	GPIO_FN(IRQ12),
-	GPIO_FN(IRQ11),
-	GPIO_FN(IRQ10),
-	GPIO_FN(IRQ9),
-	GPIO_FN(IRQ8),
-	GPIO_FN(ON_NRE),
-	GPIO_FN(ON_NWE),
-	GPIO_FN(ON_NWP),
-	GPIO_FN(ON_NCE0),
-	GPIO_FN(ON_R_B0),
-	GPIO_FN(ON_ALE),
-	GPIO_FN(ON_CLE),
-	GPIO_FN(TCLK),
-
-	/* PTC (mobule: IRQ, PWMU) */
-	GPIO_FN(IRQ7),
-	GPIO_FN(IRQ6),
-	GPIO_FN(IRQ5),
-	GPIO_FN(IRQ4),
-	GPIO_FN(IRQ3),
-	GPIO_FN(IRQ2),
-	GPIO_FN(IRQ1),
-	GPIO_FN(IRQ0),
-	GPIO_FN(PWMU0),
-	GPIO_FN(PWMU1),
-	GPIO_FN(PWMU2),
-	GPIO_FN(PWMU3),
-	GPIO_FN(PWMU4),
-	GPIO_FN(PWMU5),
-
-	/* PTD (mobule: SPI0, DMAC) */
-	GPIO_FN(SP0_MOSI),
-	GPIO_FN(SP0_MISO),
-	GPIO_FN(SP0_SCK),
-	GPIO_FN(SP0_SCK_FB),
-	GPIO_FN(SP0_SS0),
-	GPIO_FN(SP0_SS1),
-	GPIO_FN(SP0_SS2),
-	GPIO_FN(SP0_SS3),
-	GPIO_FN(DREQ0),
-	GPIO_FN(DACK0),
-	GPIO_FN(TEND0),
-
-	/* PTE (mobule: RMII) */
-	GPIO_FN(RMII0_CRS_DV),
-	GPIO_FN(RMII0_TXD1),
-	GPIO_FN(RMII0_TXD0),
-	GPIO_FN(RMII0_TXEN),
-	GPIO_FN(RMII0_REFCLK),
-	GPIO_FN(RMII0_RXD1),
-	GPIO_FN(RMII0_RXD0),
-	GPIO_FN(RMII0_RX_ER),
-
-	/* PTF (mobule: RMII, SerMux) */
-	GPIO_FN(RMII1_CRS_DV),
-	GPIO_FN(RMII1_TXD1),
-	GPIO_FN(RMII1_TXD0),
-	GPIO_FN(RMII1_TXEN),
-	GPIO_FN(RMII1_REFCLK),
-	GPIO_FN(RMII1_RXD1),
-	GPIO_FN(RMII1_RXD0),
-	GPIO_FN(RMII1_RX_ER),
-	GPIO_FN(RAC_RI),
-
-	/* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
-	GPIO_FN(BOOTFMS),
-	GPIO_FN(BOOTWP),
-	GPIO_FN(A25),
-	GPIO_FN(A24),
-	GPIO_FN(SERIRQ),
-	GPIO_FN(WDTOVF),
-	GPIO_FN(LPCPD),
-	GPIO_FN(LDRQ),
-	GPIO_FN(MMCCLK),
-	GPIO_FN(MMCCMD),
-
-	/* PTH (mobule: SPI1, LPC, DMAC, ADC) */
-	GPIO_FN(SP1_MOSI),
-	GPIO_FN(SP1_MISO),
-	GPIO_FN(SP1_SCK),
-	GPIO_FN(SP1_SCK_FB),
-	GPIO_FN(SP1_SS0),
-	GPIO_FN(SP1_SS1),
-	GPIO_FN(WP),
-	GPIO_FN(FMS0),
-	GPIO_FN(TEND1),
-	GPIO_FN(DREQ1),
-	GPIO_FN(DACK1),
-	GPIO_FN(ADTRG1),
-	GPIO_FN(ADTRG0),
-
-	/* PTI (mobule: LBSC, SDHI) */
-	GPIO_FN(D15),
-	GPIO_FN(D14),
-	GPIO_FN(D13),
-	GPIO_FN(D12),
-	GPIO_FN(D11),
-	GPIO_FN(D10),
-	GPIO_FN(D9),
-	GPIO_FN(D8),
-	GPIO_FN(SD_WP),
-	GPIO_FN(SD_CD),
-	GPIO_FN(SD_CLK),
-	GPIO_FN(SD_CMD),
-	GPIO_FN(SD_D3),
-	GPIO_FN(SD_D2),
-	GPIO_FN(SD_D1),
-	GPIO_FN(SD_D0),
-
-	/* PTJ (mobule: SCIF234, SERMUX) */
-	GPIO_FN(RTS3),
-	GPIO_FN(CTS3),
-	GPIO_FN(TXD3),
-	GPIO_FN(RXD3),
-	GPIO_FN(RTS4),
-	GPIO_FN(RXD4),
-	GPIO_FN(TXD4),
-
-	/* PTK (mobule: SERMUX, LBSC, SCIF) */
-	GPIO_FN(COM2_TXD),
-	GPIO_FN(COM2_RXD),
-	GPIO_FN(COM2_RTS),
-	GPIO_FN(COM2_CTS),
-	GPIO_FN(COM2_DTR),
-	GPIO_FN(COM2_DSR),
-	GPIO_FN(COM2_DCD),
-	GPIO_FN(CLKOUT),
-	GPIO_FN(SCK2),
-	GPIO_FN(SCK4),
-	GPIO_FN(SCK3),
-
-	/* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */
-	GPIO_FN(RAC_RXD),
-	GPIO_FN(RAC_RTS),
-	GPIO_FN(RAC_CTS),
-	GPIO_FN(RAC_DTR),
-	GPIO_FN(RAC_DSR),
-	GPIO_FN(RAC_DCD),
-	GPIO_FN(RAC_TXD),
-	GPIO_FN(RXD2),
-	GPIO_FN(CS5),
-	GPIO_FN(CS6),
-	GPIO_FN(AUDSYNC),
-	GPIO_FN(AUDCK),
-	GPIO_FN(TXD2),
-
-	/* PTM (mobule: LBSC, IIC) */
-	GPIO_FN(CS4),
-	GPIO_FN(RD),
-	GPIO_FN(WE0),
-	GPIO_FN(CS0),
-	GPIO_FN(SDA6),
-	GPIO_FN(SCL6),
-	GPIO_FN(SDA7),
-	GPIO_FN(SCL7),
-
-	/* PTN (mobule: USB, JMC, SGPIO, WDT) */
-	GPIO_FN(VBUS_EN),
-	GPIO_FN(VBUS_OC),
-	GPIO_FN(JMCTCK),
-	GPIO_FN(JMCTMS),
-	GPIO_FN(JMCTDO),
-	GPIO_FN(JMCTDI),
-	GPIO_FN(JMCTRST),
-	GPIO_FN(SGPIO1_CLK),
-	GPIO_FN(SGPIO1_LOAD),
-	GPIO_FN(SGPIO1_DI),
-	GPIO_FN(SGPIO1_DO),
-	GPIO_FN(SUB_CLKIN),
-
-	/* PTO (mobule: SGPIO, SerMux) */
-	GPIO_FN(SGPIO0_CLK),
-	GPIO_FN(SGPIO0_LOAD),
-	GPIO_FN(SGPIO0_DI),
-	GPIO_FN(SGPIO0_DO),
-	GPIO_FN(SGPIO2_CLK),
-	GPIO_FN(SGPIO2_LOAD),
-	GPIO_FN(SGPIO2_DI),
-	GPIO_FN(SGPIO2_DO),
-	GPIO_FN(COM1_TXD),
-	GPIO_FN(COM1_RXD),
-	GPIO_FN(COM1_RTS),
-	GPIO_FN(COM1_CTS),
-
-	/* PTP (mobule: EVC, ADC) */
-
-	/* PTQ (mobule: LPC) */
-	GPIO_FN(LAD3),
-	GPIO_FN(LAD2),
-	GPIO_FN(LAD1),
-	GPIO_FN(LAD0),
-	GPIO_FN(LFRAME),
-	GPIO_FN(LRESET),
-	GPIO_FN(LCLK),
-
-	/* PTR (mobule: GRA, IIC) */
-	GPIO_FN(DDC3),
-	GPIO_FN(DDC2),
-	GPIO_FN(SDA8),
-	GPIO_FN(SCL8),
-	GPIO_FN(SDA2),
-	GPIO_FN(SCL2),
-	GPIO_FN(SDA1),
-	GPIO_FN(SCL1),
-	GPIO_FN(SDA0),
-	GPIO_FN(SCL0),
-
-	/* PTS (mobule: GRA, IIC) */
-	GPIO_FN(DDC1),
-	GPIO_FN(DDC0),
-	GPIO_FN(SDA9),
-	GPIO_FN(SCL9),
-	GPIO_FN(SDA5),
-	GPIO_FN(SCL5),
-	GPIO_FN(SDA4),
-	GPIO_FN(SCL4),
-	GPIO_FN(SDA3),
-	GPIO_FN(SCL3),
-
-	/* PTT (mobule: PWMX, AUD) */
-	GPIO_FN(PWMX7),
-	GPIO_FN(PWMX6),
-	GPIO_FN(PWMX5),
-	GPIO_FN(PWMX4),
-	GPIO_FN(PWMX3),
-	GPIO_FN(PWMX2),
-	GPIO_FN(PWMX1),
-	GPIO_FN(PWMX0),
-	GPIO_FN(AUDATA3),
-	GPIO_FN(AUDATA2),
-	GPIO_FN(AUDATA1),
-	GPIO_FN(AUDATA0),
-	GPIO_FN(STATUS1),
-	GPIO_FN(STATUS0),
-
-	/* PTU (mobule: LPC, APM) */
-	GPIO_FN(LGPIO7),
-	GPIO_FN(LGPIO6),
-	GPIO_FN(LGPIO5),
-	GPIO_FN(LGPIO4),
-	GPIO_FN(LGPIO3),
-	GPIO_FN(LGPIO2),
-	GPIO_FN(LGPIO1),
-	GPIO_FN(LGPIO0),
-	GPIO_FN(APMONCTL_O),
-	GPIO_FN(APMPWBTOUT_O),
-	GPIO_FN(APMSCI_O),
-	GPIO_FN(APMVDDON),
-	GPIO_FN(APMSLPBTN),
-	GPIO_FN(APMPWRBTN),
-	GPIO_FN(APMS5N),
-	GPIO_FN(APMS3N),
-
-	/* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */
-	GPIO_FN(A23),
-	GPIO_FN(A22),
-	GPIO_FN(A21),
-	GPIO_FN(A20),
-	GPIO_FN(A19),
-	GPIO_FN(A18),
-	GPIO_FN(A17),
-	GPIO_FN(A16),
-	GPIO_FN(COM2_RI),
-	GPIO_FN(R_SPI_MOSI),
-	GPIO_FN(R_SPI_MISO),
-	GPIO_FN(R_SPI_RSPCK),
-	GPIO_FN(R_SPI_SSL0),
-	GPIO_FN(R_SPI_SSL1),
-	GPIO_FN(EVENT7),
-	GPIO_FN(EVENT6),
-	GPIO_FN(VBIOS_DI),
-	GPIO_FN(VBIOS_DO),
-	GPIO_FN(VBIOS_CLK),
-	GPIO_FN(VBIOS_CS),
-
-	/* PTW (mobule: LBSC, EVC, SCIF) */
-	GPIO_FN(A15),
-	GPIO_FN(A14),
-	GPIO_FN(A13),
-	GPIO_FN(A12),
-	GPIO_FN(A11),
-	GPIO_FN(A10),
-	GPIO_FN(A9),
-	GPIO_FN(A8),
-	GPIO_FN(EVENT5),
-	GPIO_FN(EVENT4),
-	GPIO_FN(EVENT3),
-	GPIO_FN(EVENT2),
-	GPIO_FN(EVENT1),
-	GPIO_FN(EVENT0),
-	GPIO_FN(CTS4),
-	GPIO_FN(CTS2),
-
-	/* PTX (mobule: LBSC) */
-	GPIO_FN(A7),
-	GPIO_FN(A6),
-	GPIO_FN(A5),
-	GPIO_FN(A4),
-	GPIO_FN(A3),
-	GPIO_FN(A2),
-	GPIO_FN(A1),
-	GPIO_FN(A0),
-	GPIO_FN(RTS2),
-	GPIO_FN(SIM_D),
-	GPIO_FN(SIM_CLK),
-	GPIO_FN(SIM_RST),
-
-	/* PTY (mobule: LBSC) */
-	GPIO_FN(D7),
-	GPIO_FN(D6),
-	GPIO_FN(D5),
-	GPIO_FN(D4),
-	GPIO_FN(D3),
-	GPIO_FN(D2),
-	GPIO_FN(D1),
-	GPIO_FN(D0),
-
-	/* PTZ (mobule: eMMC, ONFI) */
-	GPIO_FN(MMCDAT7),
-	GPIO_FN(MMCDAT6),
-	GPIO_FN(MMCDAT5),
-	GPIO_FN(MMCDAT4),
-	GPIO_FN(MMCDAT3),
-	GPIO_FN(MMCDAT2),
-	GPIO_FN(MMCDAT1),
-	GPIO_FN(MMCDAT0),
-	GPIO_FN(ON_DQ7),
-	GPIO_FN(ON_DQ6),
-	GPIO_FN(ON_DQ5),
-	GPIO_FN(ON_DQ4),
-	GPIO_FN(ON_DQ3),
-	GPIO_FN(ON_DQ2),
-	GPIO_FN(ON_DQ1),
-	GPIO_FN(ON_DQ0),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	{ PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2, GROUP(
-		PTA7_FN, PTA7_OUT, PTA7_IN, 0,
-		PTA6_FN, PTA6_OUT, PTA6_IN, 0,
-		PTA5_FN, PTA5_OUT, PTA5_IN, 0,
-		PTA4_FN, PTA4_OUT, PTA4_IN, 0,
-		PTA3_FN, PTA3_OUT, PTA3_IN, 0,
-		PTA2_FN, PTA2_OUT, PTA2_IN, 0,
-		PTA1_FN, PTA1_OUT, PTA1_IN, 0,
-		PTA0_FN, PTA0_OUT, PTA0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2, GROUP(
-		PTB7_FN, PTB7_OUT, PTB7_IN, 0,
-		PTB6_FN, PTB6_OUT, PTB6_IN, 0,
-		PTB5_FN, PTB5_OUT, PTB5_IN, 0,
-		PTB4_FN, PTB4_OUT, PTB4_IN, 0,
-		PTB3_FN, PTB3_OUT, PTB3_IN, 0,
-		PTB2_FN, PTB2_OUT, PTB2_IN, 0,
-		PTB1_FN, PTB1_OUT, PTB1_IN, 0,
-		PTB0_FN, PTB0_OUT, PTB0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PCCR", 0xffec0004, 16, 2, GROUP(
-		PTC7_FN, PTC7_OUT, PTC7_IN, 0,
-		PTC6_FN, PTC6_OUT, PTC6_IN, 0,
-		PTC5_FN, PTC5_OUT, PTC5_IN, 0,
-		PTC4_FN, PTC4_OUT, PTC4_IN, 0,
-		PTC3_FN, PTC3_OUT, PTC3_IN, 0,
-		PTC2_FN, PTC2_OUT, PTC2_IN, 0,
-		PTC1_FN, PTC1_OUT, PTC1_IN, 0,
-		PTC0_FN, PTC0_OUT, PTC0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2, GROUP(
-		PTD7_FN, PTD7_OUT, PTD7_IN, 0,
-		PTD6_FN, PTD6_OUT, PTD6_IN, 0,
-		PTD5_FN, PTD5_OUT, PTD5_IN, 0,
-		PTD4_FN, PTD4_OUT, PTD4_IN, 0,
-		PTD3_FN, PTD3_OUT, PTD3_IN, 0,
-		PTD2_FN, PTD2_OUT, PTD2_IN, 0,
-		PTD1_FN, PTD1_OUT, PTD1_IN, 0,
-		PTD0_FN, PTD0_OUT, PTD0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2, GROUP(
-		PTE7_FN, PTE7_OUT, PTE7_IN, 0,
-		PTE6_FN, PTE6_OUT, PTE6_IN, 0,
-		PTE5_FN, PTE5_OUT, PTE5_IN, 0,
-		PTE4_FN, PTE4_OUT, PTE4_IN, 0,
-		PTE3_FN, PTE3_OUT, PTE3_IN, 0,
-		PTE2_FN, PTE2_OUT, PTE2_IN, 0,
-		PTE1_FN, PTE1_OUT, PTE1_IN, 0,
-		PTE0_FN, PTE0_OUT, PTE0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2, GROUP(
-		PTF7_FN, PTF7_OUT, PTF7_IN, 0,
-		PTF6_FN, PTF6_OUT, PTF6_IN, 0,
-		PTF5_FN, PTF5_OUT, PTF5_IN, 0,
-		PTF4_FN, PTF4_OUT, PTF4_IN, 0,
-		PTF3_FN, PTF3_OUT, PTF3_IN, 0,
-		PTF2_FN, PTF2_OUT, PTF2_IN, 0,
-		PTF1_FN, PTF1_OUT, PTF1_IN, 0,
-		PTF0_FN, PTF0_OUT, PTF0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2, GROUP(
-		PTG7_FN, PTG7_OUT, PTG7_IN, 0,
-		PTG6_FN, PTG6_OUT, PTG6_IN, 0,
-		PTG5_FN, PTG5_OUT, PTG5_IN, 0,
-		PTG4_FN, PTG4_OUT, PTG4_IN, 0,
-		PTG3_FN, PTG3_OUT, PTG3_IN, 0,
-		PTG2_FN, PTG2_OUT, PTG2_IN, 0,
-		PTG1_FN, PTG1_OUT, PTG1_IN, 0,
-		PTG0_FN, PTG0_OUT, PTG0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2, GROUP(
-		PTH7_FN, PTH7_OUT, PTH7_IN, 0,
-		PTH6_FN, PTH6_OUT, PTH6_IN, 0,
-		PTH5_FN, PTH5_OUT, PTH5_IN, 0,
-		PTH4_FN, PTH4_OUT, PTH4_IN, 0,
-		PTH3_FN, PTH3_OUT, PTH3_IN, 0,
-		PTH2_FN, PTH2_OUT, PTH2_IN, 0,
-		PTH1_FN, PTH1_OUT, PTH1_IN, 0,
-		PTH0_FN, PTH0_OUT, PTH0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2, GROUP(
-		PTI7_FN, PTI7_OUT, PTI7_IN, 0,
-		PTI6_FN, PTI6_OUT, PTI6_IN, 0,
-		PTI5_FN, PTI5_OUT, PTI5_IN, 0,
-		PTI4_FN, PTI4_OUT, PTI4_IN, 0,
-		PTI3_FN, PTI3_OUT, PTI3_IN, 0,
-		PTI2_FN, PTI2_OUT, PTI2_IN, 0,
-		PTI1_FN, PTI1_OUT, PTI1_IN, 0,
-		PTI0_FN, PTI0_OUT, PTI0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2, GROUP(
-		0, 0, 0, 0,	/* reserved: always set 1 */
-		PTJ6_FN, PTJ6_OUT, PTJ6_IN, 0,
-		PTJ5_FN, PTJ5_OUT, PTJ5_IN, 0,
-		PTJ4_FN, PTJ4_OUT, PTJ4_IN, 0,
-		PTJ3_FN, PTJ3_OUT, PTJ3_IN, 0,
-		PTJ2_FN, PTJ2_OUT, PTJ2_IN, 0,
-		PTJ1_FN, PTJ1_OUT, PTJ1_IN, 0,
-		PTJ0_FN, PTJ0_OUT, PTJ0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PKCR", 0xffec0014, 16, 2, GROUP(
-		PTK7_FN, PTK7_OUT, PTK7_IN, 0,
-		PTK6_FN, PTK6_OUT, PTK6_IN, 0,
-		PTK5_FN, PTK5_OUT, PTK5_IN, 0,
-		PTK4_FN, PTK4_OUT, PTK4_IN, 0,
-		PTK3_FN, PTK3_OUT, PTK3_IN, 0,
-		PTK2_FN, PTK2_OUT, PTK2_IN, 0,
-		PTK1_FN, PTK1_OUT, PTK1_IN, 0,
-		PTK0_FN, PTK0_OUT, PTK0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PLCR", 0xffec0016, 16, 2, GROUP(
-		0, 0, 0, 0,	/* reserved: always set 1 */
-		PTL6_FN, PTL6_OUT, PTL6_IN, 0,
-		PTL5_FN, PTL5_OUT, PTL5_IN, 0,
-		PTL4_FN, PTL4_OUT, PTL4_IN, 0,
-		PTL3_FN, PTL3_OUT, PTL3_IN, 0,
-		PTL2_FN, PTL2_OUT, PTL2_IN, 0,
-		PTL1_FN, PTL1_OUT, PTL1_IN, 0,
-		PTL0_FN, PTL0_OUT, PTL0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PMCR", 0xffec0018, 16, 2, GROUP(
-		PTM7_FN, PTM7_OUT, PTM7_IN, 0,
-		PTM6_FN, PTM6_OUT, PTM6_IN, 0,
-		PTM5_FN, PTM5_OUT, PTM5_IN, 0,
-		PTM4_FN, PTM4_OUT, PTM4_IN, 0,
-		PTM3_FN, PTM3_OUT, PTM3_IN, 0,
-		PTM2_FN, PTM2_OUT, PTM2_IN, 0,
-		PTM1_FN, PTM1_OUT, PTM1_IN, 0,
-		PTM0_FN, PTM0_OUT, PTM0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PNCR", 0xffec001a, 16, 2, GROUP(
-		0, 0, 0, 0,	/* reserved: always set 1 */
-		PTN6_FN, PTN6_OUT, PTN6_IN, 0,
-		PTN5_FN, PTN5_OUT, PTN5_IN, 0,
-		PTN4_FN, PTN4_OUT, PTN4_IN, 0,
-		PTN3_FN, PTN3_OUT, PTN3_IN, 0,
-		PTN2_FN, PTN2_OUT, PTN2_IN, 0,
-		PTN1_FN, PTN1_OUT, PTN1_IN, 0,
-		PTN0_FN, PTN0_OUT, PTN0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("POCR", 0xffec001c, 16, 2, GROUP(
-		PTO7_FN, PTO7_OUT, PTO7_IN, 0,
-		PTO6_FN, PTO6_OUT, PTO6_IN, 0,
-		PTO5_FN, PTO5_OUT, PTO5_IN, 0,
-		PTO4_FN, PTO4_OUT, PTO4_IN, 0,
-		PTO3_FN, PTO3_OUT, PTO3_IN, 0,
-		PTO2_FN, PTO2_OUT, PTO2_IN, 0,
-		PTO1_FN, PTO1_OUT, PTO1_IN, 0,
-		PTO0_FN, PTO0_OUT, PTO0_IN, 0 ))
-	},
-#if 0	/* FIXME: Remove it? */
-	{ PINMUX_CFG_REG("PPCR", 0xffec001e, 16, 2, GROUP(
-		0, 0, 0, 0,	/* reserved: always set 1 */
-		PTP6_FN, PTP6_OUT, PTP6_IN, 0,
-		PTP5_FN, PTP5_OUT, PTP5_IN, 0,
-		PTP4_FN, PTP4_OUT, PTP4_IN, 0,
-		PTP3_FN, PTP3_OUT, PTP3_IN, 0,
-		PTP2_FN, PTP2_OUT, PTP2_IN, 0,
-		PTP1_FN, PTP1_OUT, PTP1_IN, 0,
-		PTP0_FN, PTP0_OUT, PTP0_IN, 0 ))
-	},
-#endif
-	{ PINMUX_CFG_REG("PQCR", 0xffec0020, 16, 2, GROUP(
-		0, 0, 0, 0,	/* reserved: always set 1 */
-		PTQ6_FN, PTQ6_OUT, PTQ6_IN, 0,
-		PTQ5_FN, PTQ5_OUT, PTQ5_IN, 0,
-		PTQ4_FN, PTQ4_OUT, PTQ4_IN, 0,
-		PTQ3_FN, PTQ3_OUT, PTQ3_IN, 0,
-		PTQ2_FN, PTQ2_OUT, PTQ2_IN, 0,
-		PTQ1_FN, PTQ1_OUT, PTQ1_IN, 0,
-		PTQ0_FN, PTQ0_OUT, PTQ0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PRCR", 0xffec0022, 16, 2, GROUP(
-		PTR7_FN, PTR7_OUT, PTR7_IN, 0,
-		PTR6_FN, PTR6_OUT, PTR6_IN, 0,
-		PTR5_FN, PTR5_OUT, PTR5_IN, 0,
-		PTR4_FN, PTR4_OUT, PTR4_IN, 0,
-		PTR3_FN, PTR3_OUT, PTR3_IN, 0,
-		PTR2_FN, PTR2_OUT, PTR2_IN, 0,
-		PTR1_FN, PTR1_OUT, PTR1_IN, 0,
-		PTR0_FN, PTR0_OUT, PTR0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PSCR", 0xffec0024, 16, 2, GROUP(
-		PTS7_FN, PTS7_OUT, PTS7_IN, 0,
-		PTS6_FN, PTS6_OUT, PTS6_IN, 0,
-		PTS5_FN, PTS5_OUT, PTS5_IN, 0,
-		PTS4_FN, PTS4_OUT, PTS4_IN, 0,
-		PTS3_FN, PTS3_OUT, PTS3_IN, 0,
-		PTS2_FN, PTS2_OUT, PTS2_IN, 0,
-		PTS1_FN, PTS1_OUT, PTS1_IN, 0,
-		PTS0_FN, PTS0_OUT, PTS0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PTCR", 0xffec0026, 16, 2, GROUP(
-		PTT7_FN, PTT7_OUT, PTT7_IN, 0,
-		PTT6_FN, PTT6_OUT, PTT6_IN, 0,
-		PTT5_FN, PTT5_OUT, PTT5_IN, 0,
-		PTT4_FN, PTT4_OUT, PTT4_IN, 0,
-		PTT3_FN, PTT3_OUT, PTT3_IN, 0,
-		PTT2_FN, PTT2_OUT, PTT2_IN, 0,
-		PTT1_FN, PTT1_OUT, PTT1_IN, 0,
-		PTT0_FN, PTT0_OUT, PTT0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PUCR", 0xffec0028, 16, 2, GROUP(
-		PTU7_FN, PTU7_OUT, PTU7_IN, 0,
-		PTU6_FN, PTU6_OUT, PTU6_IN, 0,
-		PTU5_FN, PTU5_OUT, PTU5_IN, 0,
-		PTU4_FN, PTU4_OUT, PTU4_IN, 0,
-		PTU3_FN, PTU3_OUT, PTU3_IN, 0,
-		PTU2_FN, PTU2_OUT, PTU2_IN, 0,
-		PTU1_FN, PTU1_OUT, PTU1_IN, 0,
-		PTU0_FN, PTU0_OUT, PTU0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PVCR", 0xffec002a, 16, 2, GROUP(
-		PTV7_FN, PTV7_OUT, PTV7_IN, 0,
-		PTV6_FN, PTV6_OUT, PTV6_IN, 0,
-		PTV5_FN, PTV5_OUT, PTV5_IN, 0,
-		PTV4_FN, PTV4_OUT, PTV4_IN, 0,
-		PTV3_FN, PTV3_OUT, PTV3_IN, 0,
-		PTV2_FN, PTV2_OUT, PTV2_IN, 0,
-		PTV1_FN, PTV1_OUT, PTV1_IN, 0,
-		PTV0_FN, PTV0_OUT, PTV0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PWCR", 0xffec002c, 16, 2, GROUP(
-		PTW7_FN, PTW7_OUT, PTW7_IN, 0,
-		PTW6_FN, PTW6_OUT, PTW6_IN, 0,
-		PTW5_FN, PTW5_OUT, PTW5_IN, 0,
-		PTW4_FN, PTW4_OUT, PTW4_IN, 0,
-		PTW3_FN, PTW3_OUT, PTW3_IN, 0,
-		PTW2_FN, PTW2_OUT, PTW2_IN, 0,
-		PTW1_FN, PTW1_OUT, PTW1_IN, 0,
-		PTW0_FN, PTW0_OUT, PTW0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PXCR", 0xffec002e, 16, 2, GROUP(
-		PTX7_FN, PTX7_OUT, PTX7_IN, 0,
-		PTX6_FN, PTX6_OUT, PTX6_IN, 0,
-		PTX5_FN, PTX5_OUT, PTX5_IN, 0,
-		PTX4_FN, PTX4_OUT, PTX4_IN, 0,
-		PTX3_FN, PTX3_OUT, PTX3_IN, 0,
-		PTX2_FN, PTX2_OUT, PTX2_IN, 0,
-		PTX1_FN, PTX1_OUT, PTX1_IN, 0,
-		PTX0_FN, PTX0_OUT, PTX0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PYCR", 0xffec0030, 16, 2, GROUP(
-		PTY7_FN, PTY7_OUT, PTY7_IN, 0,
-		PTY6_FN, PTY6_OUT, PTY6_IN, 0,
-		PTY5_FN, PTY5_OUT, PTY5_IN, 0,
-		PTY4_FN, PTY4_OUT, PTY4_IN, 0,
-		PTY3_FN, PTY3_OUT, PTY3_IN, 0,
-		PTY2_FN, PTY2_OUT, PTY2_IN, 0,
-		PTY1_FN, PTY1_OUT, PTY1_IN, 0,
-		PTY0_FN, PTY0_OUT, PTY0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PZCR", 0xffec0032, 16, 2, GROUP(
-		PTZ7_FN, PTZ7_OUT, PTZ7_IN, 0,
-		PTZ6_FN, PTZ6_OUT, PTZ6_IN, 0,
-		PTZ5_FN, PTZ5_OUT, PTZ5_IN, 0,
-		PTZ4_FN, PTZ4_OUT, PTZ4_IN, 0,
-		PTZ3_FN, PTZ3_OUT, PTZ3_IN, 0,
-		PTZ2_FN, PTZ2_OUT, PTZ2_IN, 0,
-		PTZ1_FN, PTZ1_OUT, PTZ1_IN, 0,
-		PTZ0_FN, PTZ0_OUT, PTZ0_IN, 0 ))
-	},
-
-	{ PINMUX_CFG_REG("PSEL0", 0xffec0070, 16, 1, GROUP(
-		PS0_15_FN1, PS0_15_FN2,
-		PS0_14_FN1, PS0_14_FN2,
-		PS0_13_FN1, PS0_13_FN2,
-		PS0_12_FN1, PS0_12_FN2,
-		PS0_11_FN1, PS0_11_FN2,
-		PS0_10_FN1, PS0_10_FN2,
-		PS0_9_FN1, PS0_9_FN2,
-		PS0_8_FN1, PS0_8_FN2,
-		PS0_7_FN1, PS0_7_FN2,
-		PS0_6_FN1, PS0_6_FN2,
-		PS0_5_FN1, PS0_5_FN2,
-		PS0_4_FN1, PS0_4_FN2,
-		PS0_3_FN1, PS0_3_FN2,
-		PS0_2_FN1, PS0_2_FN2,
-		0, 0,
-		0, 0, ))
-	},
-	{ PINMUX_CFG_REG("PSEL1", 0xffec0072, 16, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		PS1_10_FN1, PS1_10_FN2,
-		PS1_9_FN1, PS1_9_FN2,
-		PS1_8_FN1, PS1_8_FN2,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		PS1_2_FN1, PS1_2_FN2,
-		0, 0,
-		0, 0, ))
-	},
-	{ PINMUX_CFG_REG("PSEL2", 0xffec0074, 16, 1, GROUP(
-		0, 0,
-		0, 0,
-		PS2_13_FN1, PS2_13_FN2,
-		PS2_12_FN1, PS2_12_FN2,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		PS2_7_FN1, PS2_7_FN2,
-		PS2_6_FN1, PS2_6_FN2,
-		PS2_5_FN1, PS2_5_FN2,
-		PS2_4_FN1, PS2_4_FN2,
-		0, 0,
-		PS2_2_FN1, PS2_2_FN2,
-		0, 0,
-		0, 0, ))
-	},
-	{ PINMUX_CFG_REG("PSEL3", 0xffec0076, 16, 1, GROUP(
-		PS3_15_FN1, PS3_15_FN2,
-		PS3_14_FN1, PS3_14_FN2,
-		PS3_13_FN1, PS3_13_FN2,
-		PS3_12_FN1, PS3_12_FN2,
-		PS3_11_FN1, PS3_11_FN2,
-		PS3_10_FN1, PS3_10_FN2,
-		PS3_9_FN1, PS3_9_FN2,
-		PS3_8_FN1, PS3_8_FN2,
-		PS3_7_FN1, PS3_7_FN2,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		PS3_2_FN1, PS3_2_FN2,
-		PS3_1_FN1, PS3_1_FN2,
-		0, 0, ))
-	},
-
-	{ PINMUX_CFG_REG("PSEL4", 0xffec0078, 16, 1, GROUP(
-		0, 0,
-		PS4_14_FN1, PS4_14_FN2,
-		PS4_13_FN1, PS4_13_FN2,
-		PS4_12_FN1, PS4_12_FN2,
-		0, 0,
-		PS4_10_FN1, PS4_10_FN2,
-		PS4_9_FN1, PS4_9_FN2,
-		PS4_8_FN1, PS4_8_FN2,
-		0, 0,
-		0, 0,
-		0, 0,
-		PS4_4_FN1, PS4_4_FN2,
-		PS4_3_FN1, PS4_3_FN2,
-		PS4_2_FN1, PS4_2_FN2,
-		PS4_1_FN1, PS4_1_FN2,
-		PS4_0_FN1, PS4_0_FN2, ))
-	},
-	{ PINMUX_CFG_REG("PSEL5", 0xffec007a, 16, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		PS5_11_FN1, PS5_11_FN2,
-		PS5_10_FN1, PS5_10_FN2,
-		PS5_9_FN1, PS5_9_FN2,
-		PS5_8_FN1, PS5_8_FN2,
-		PS5_7_FN1, PS5_7_FN2,
-		PS5_6_FN1, PS5_6_FN2,
-		PS5_5_FN1, PS5_5_FN2,
-		PS5_4_FN1, PS5_4_FN2,
-		PS5_3_FN1, PS5_3_FN2,
-		PS5_2_FN1, PS5_2_FN2,
-		0, 0,
-		0, 0, ))
-	},
-	{ PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1, GROUP(
-		PS6_15_FN1, PS6_15_FN2,
-		PS6_14_FN1, PS6_14_FN2,
-		PS6_13_FN1, PS6_13_FN2,
-		PS6_12_FN1, PS6_12_FN2,
-		PS6_11_FN1, PS6_11_FN2,
-		PS6_10_FN1, PS6_10_FN2,
-		PS6_9_FN1, PS6_9_FN2,
-		PS6_8_FN1, PS6_8_FN2,
-		PS6_7_FN1, PS6_7_FN2,
-		PS6_6_FN1, PS6_6_FN2,
-		PS6_5_FN1, PS6_5_FN2,
-		PS6_4_FN1, PS6_4_FN2,
-		PS6_3_FN1, PS6_3_FN2,
-		PS6_2_FN1, PS6_2_FN2,
-		PS6_1_FN1, PS6_1_FN2,
-		PS6_0_FN1, PS6_0_FN2, ))
-	},
-	{ PINMUX_CFG_REG("PSEL7", 0xffec0082, 16, 1, GROUP(
-		PS7_15_FN1, PS7_15_FN2,
-		PS7_14_FN1, PS7_14_FN2,
-		PS7_13_FN1, PS7_13_FN2,
-		PS7_12_FN1, PS7_12_FN2,
-		PS7_11_FN1, PS7_11_FN2,
-		PS7_10_FN1, PS7_10_FN2,
-		PS7_9_FN1, PS7_9_FN2,
-		PS7_8_FN1, PS7_8_FN2,
-		PS7_7_FN1, PS7_7_FN2,
-		PS7_6_FN1, PS7_6_FN2,
-		PS7_5_FN1, PS7_5_FN2,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0, ))
-	},
-	{ PINMUX_CFG_REG("PSEL8", 0xffec0084, 16, 1, GROUP(
-		PS8_15_FN1, PS8_15_FN2,
-		PS8_14_FN1, PS8_14_FN2,
-		PS8_13_FN1, PS8_13_FN2,
-		PS8_12_FN1, PS8_12_FN2,
-		PS8_11_FN1, PS8_11_FN2,
-		PS8_10_FN1, PS8_10_FN2,
-		PS8_9_FN1, PS8_9_FN2,
-		PS8_8_FN1, PS8_8_FN2,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0, ))
-	},
-	{}
-};
-
-static const struct pinmux_data_reg pinmux_data_regs[] = {
-	{ PINMUX_DATA_REG("PADR", 0xffec0034, 8, GROUP(
-		PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
-		PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PBDR", 0xffec0036, 8, GROUP(
-		PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
-		PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PCDR", 0xffec0038, 8, GROUP(
-		PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
-		PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PDDR", 0xffec003a, 8, GROUP(
-		PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
-		PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PEDR", 0xffec003c, 8, GROUP(
-		PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
-		PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PFDR", 0xffec003e, 8, GROUP(
-		PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
-		PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PGDR", 0xffec0040, 8, GROUP(
-		PTG7_DATA, PTG6_DATA, PTG5_DATA, PTG4_DATA,
-		PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PHDR", 0xffec0042, 8, GROUP(
-		PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
-		PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PIDR", 0xffec0044, 8, GROUP(
-		PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA,
-		PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PJDR", 0xffec0046, 8, GROUP(
-		0, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
-		PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PKDR", 0xffec0048, 8, GROUP(
-		PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
-		PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PLDR", 0xffec004a, 8, GROUP(
-		0, PTL6_DATA, PTL5_DATA, PTL4_DATA,
-		PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PMDR", 0xffec004c, 8, GROUP(
-		PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
-		PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PNDR", 0xffec004e, 8, GROUP(
-		0, PTN6_DATA, PTN5_DATA, PTN4_DATA,
-		PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PODR", 0xffec0050, 8, GROUP(
-		PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA,
-		PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PPDR", 0xffec0052, 8, GROUP(
-		PTP7_DATA, PTP6_DATA, PTP5_DATA, PTP4_DATA,
-		PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PQDR", 0xffec0054, 8, GROUP(
-		0, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
-		PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PRDR", 0xffec0056, 8, GROUP(
-		PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
-		PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PSDR", 0xffec0058, 8, GROUP(
-		PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
-		PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PTDR", 0xffec005a, 8, GROUP(
-		PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
-		PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PUDR", 0xffec005c, 8, GROUP(
-		PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
-		PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PVDR", 0xffec005e, 8, GROUP(
-		PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
-		PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PWDR", 0xffec0060, 8, GROUP(
-		PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
-		PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PXDR", 0xffec0062, 8, GROUP(
-		PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
-		PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PYDR", 0xffec0064, 8, GROUP(
-		PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
-		PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PZDR", 0xffec0066, 8, GROUP(
-		PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
-		PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
-	},
-	{ },
-};
-
-const struct sh_pfc_soc_info sh7757_pinmux_info = {
-	.name = "sh7757_pfc",
-	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.func_gpios = pinmux_func_gpios,
-	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
-	.cfg_regs = pinmux_config_regs,
-	.data_regs = pinmux_data_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
deleted file mode 100644
index c4c1e288c53e..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c
+++ /dev/null
@@ -1,1271 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * SH7785 Pinmux
- *
- *  Copyright (C) 2008  Magnus Damm
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <cpu/sh7785.h>
-
-#include "sh_pfc.h"
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
-	PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
-	PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
-	PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
-	PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
-	PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
-	PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
-	PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
-	PE5_DATA, PE4_DATA, PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
-	PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
-	PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
-	PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
-	PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
-	PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
-	PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
-	PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
-	PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA,
-	PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
-	PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA,
-	PL7_DATA, PL6_DATA, PL5_DATA, PL4_DATA,
-	PL3_DATA, PL2_DATA, PL1_DATA, PL0_DATA,
-	PM1_DATA, PM0_DATA,
-	PN7_DATA, PN6_DATA, PN5_DATA, PN4_DATA,
-	PN3_DATA, PN2_DATA, PN1_DATA, PN0_DATA,
-	PP5_DATA, PP4_DATA, PP3_DATA, PP2_DATA, PP1_DATA, PP0_DATA,
-	PQ4_DATA, PQ3_DATA, PQ2_DATA, PQ1_DATA, PQ0_DATA,
-	PR3_DATA, PR2_DATA, PR1_DATA, PR0_DATA,
-	PINMUX_DATA_END,
-
-	PINMUX_INPUT_BEGIN,
-	PA7_IN, PA6_IN, PA5_IN, PA4_IN,
-	PA3_IN, PA2_IN, PA1_IN, PA0_IN,
-	PB7_IN, PB6_IN, PB5_IN, PB4_IN,
-	PB3_IN, PB2_IN, PB1_IN, PB0_IN,
-	PC7_IN, PC6_IN, PC5_IN, PC4_IN,
-	PC3_IN, PC2_IN, PC1_IN, PC0_IN,
-	PD7_IN, PD6_IN, PD5_IN, PD4_IN,
-	PD3_IN, PD2_IN, PD1_IN, PD0_IN,
-	PE5_IN, PE4_IN, PE3_IN, PE2_IN, PE1_IN, PE0_IN,
-	PF7_IN, PF6_IN, PF5_IN, PF4_IN,
-	PF3_IN, PF2_IN, PF1_IN, PF0_IN,
-	PG7_IN, PG6_IN, PG5_IN, PG4_IN,
-	PG3_IN, PG2_IN, PG1_IN, PG0_IN,
-	PH7_IN, PH6_IN, PH5_IN, PH4_IN,
-	PH3_IN, PH2_IN, PH1_IN, PH0_IN,
-	PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
-	PJ3_IN, PJ2_IN, PJ1_IN, PJ0_IN,
-	PK7_IN, PK6_IN, PK5_IN, PK4_IN,
-	PK3_IN, PK2_IN, PK1_IN, PK0_IN,
-	PL7_IN, PL6_IN, PL5_IN, PL4_IN,
-	PL3_IN, PL2_IN, PL1_IN, PL0_IN,
-	PM1_IN, PM0_IN,
-	PN7_IN, PN6_IN, PN5_IN, PN4_IN,
-	PN3_IN, PN2_IN, PN1_IN, PN0_IN,
-	PP5_IN, PP4_IN, PP3_IN, PP2_IN, PP1_IN, PP0_IN,
-	PQ4_IN, PQ3_IN, PQ2_IN, PQ1_IN, PQ0_IN,
-	PR3_IN, PR2_IN, PR1_IN, PR0_IN,
-	PINMUX_INPUT_END,
-
-	PINMUX_OUTPUT_BEGIN,
-	PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
-	PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
-	PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
-	PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
-	PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
-	PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
-	PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
-	PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
-	PE5_OUT, PE4_OUT, PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
-	PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
-	PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
-	PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT,
-	PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT,
-	PH7_OUT, PH6_OUT, PH5_OUT, PH4_OUT,
-	PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
-	PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
-	PJ3_OUT, PJ2_OUT, PJ1_OUT, PJ0_OUT,
-	PK7_OUT, PK6_OUT, PK5_OUT, PK4_OUT,
-	PK3_OUT, PK2_OUT, PK1_OUT, PK0_OUT,
-	PL7_OUT, PL6_OUT, PL5_OUT, PL4_OUT,
-	PL3_OUT, PL2_OUT, PL1_OUT, PL0_OUT,
-	PM1_OUT, PM0_OUT,
-	PN7_OUT, PN6_OUT, PN5_OUT, PN4_OUT,
-	PN3_OUT, PN2_OUT, PN1_OUT, PN0_OUT,
-	PP5_OUT, PP4_OUT, PP3_OUT, PP2_OUT, PP1_OUT, PP0_OUT,
-	PQ4_OUT, PQ3_OUT, PQ2_OUT, PQ1_OUT, PQ0_OUT,
-	PR3_OUT, PR2_OUT, PR1_OUT, PR0_OUT,
-	PINMUX_OUTPUT_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	PA7_FN, PA6_FN, PA5_FN, PA4_FN,
-	PA3_FN, PA2_FN, PA1_FN, PA0_FN,
-	PB7_FN, PB6_FN, PB5_FN, PB4_FN,
-	PB3_FN, PB2_FN, PB1_FN, PB0_FN,
-	PC7_FN, PC6_FN, PC5_FN, PC4_FN,
-	PC3_FN, PC2_FN, PC1_FN, PC0_FN,
-	PD7_FN, PD6_FN, PD5_FN, PD4_FN,
-	PD3_FN, PD2_FN, PD1_FN, PD0_FN,
-	PE5_FN, PE4_FN, PE3_FN, PE2_FN, PE1_FN, PE0_FN,
-	PF7_FN, PF6_FN, PF5_FN, PF4_FN,
-	PF3_FN, PF2_FN, PF1_FN, PF0_FN,
-	PG7_FN, PG6_FN, PG5_FN, PG4_FN,
-	PG3_FN, PG2_FN, PG1_FN, PG0_FN,
-	PH7_FN, PH6_FN, PH5_FN, PH4_FN,
-	PH3_FN, PH2_FN, PH1_FN, PH0_FN,
-	PJ7_FN, PJ6_FN, PJ5_FN, PJ4_FN,
-	PJ3_FN, PJ2_FN, PJ1_FN, PJ0_FN,
-	PK7_FN, PK6_FN, PK5_FN, PK4_FN,
-	PK3_FN, PK2_FN, PK1_FN, PK0_FN,
-	PL7_FN, PL6_FN, PL5_FN, PL4_FN,
-	PL3_FN, PL2_FN, PL1_FN, PL0_FN,
-	PM1_FN, PM0_FN,
-	PN7_FN, PN6_FN, PN5_FN, PN4_FN,
-	PN3_FN, PN2_FN, PN1_FN, PN0_FN,
-	PP5_FN, PP4_FN, PP3_FN, PP2_FN, PP1_FN, PP0_FN,
-	PQ4_FN, PQ3_FN, PQ2_FN, PQ1_FN, PQ0_FN,
-	PR3_FN, PR2_FN, PR1_FN, PR0_FN,
-	P1MSEL15_0, P1MSEL15_1,
-	P1MSEL14_0, P1MSEL14_1,
-	P1MSEL13_0, P1MSEL13_1,
-	P1MSEL12_0, P1MSEL12_1,
-	P1MSEL11_0, P1MSEL11_1,
-	P1MSEL10_0, P1MSEL10_1,
-	P1MSEL9_0, P1MSEL9_1,
-	P1MSEL8_0, P1MSEL8_1,
-	P1MSEL7_0, P1MSEL7_1,
-	P1MSEL6_0, P1MSEL6_1,
-	P1MSEL5_0,
-	P1MSEL4_0, P1MSEL4_1,
-	P1MSEL3_0, P1MSEL3_1,
-	P1MSEL2_0, P1MSEL2_1,
-	P1MSEL1_0, P1MSEL1_1,
-	P1MSEL0_0, P1MSEL0_1,
-	P2MSEL2_0, P2MSEL2_1,
-	P2MSEL1_0, P2MSEL1_1,
-	P2MSEL0_0, P2MSEL0_1,
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-	D63_AD31_MARK,
-	D62_AD30_MARK,
-	D61_AD29_MARK,
-	D60_AD28_MARK,
-	D59_AD27_MARK,
-	D58_AD26_MARK,
-	D57_AD25_MARK,
-	D56_AD24_MARK,
-	D55_AD23_MARK,
-	D54_AD22_MARK,
-	D53_AD21_MARK,
-	D52_AD20_MARK,
-	D51_AD19_MARK,
-	D50_AD18_MARK,
-	D49_AD17_DB5_MARK,
-	D48_AD16_DB4_MARK,
-	D47_AD15_DB3_MARK,
-	D46_AD14_DB2_MARK,
-	D45_AD13_DB1_MARK,
-	D44_AD12_DB0_MARK,
-	D43_AD11_DG5_MARK,
-	D42_AD10_DG4_MARK,
-	D41_AD9_DG3_MARK,
-	D40_AD8_DG2_MARK,
-	D39_AD7_DG1_MARK,
-	D38_AD6_DG0_MARK,
-	D37_AD5_DR5_MARK,
-	D36_AD4_DR4_MARK,
-	D35_AD3_DR3_MARK,
-	D34_AD2_DR2_MARK,
-	D33_AD1_DR1_MARK,
-	D32_AD0_DR0_MARK,
-	REQ1_MARK,
-	REQ2_MARK,
-	REQ3_MARK,
-	GNT1_MARK,
-	GNT2_MARK,
-	GNT3_MARK,
-	MMCCLK_MARK,
-	D31_MARK,
-	D30_MARK,
-	D29_MARK,
-	D28_MARK,
-	D27_MARK,
-	D26_MARK,
-	D25_MARK,
-	D24_MARK,
-	D23_MARK,
-	D22_MARK,
-	D21_MARK,
-	D20_MARK,
-	D19_MARK,
-	D18_MARK,
-	D17_MARK,
-	D16_MARK,
-	SCIF1_SCK_MARK,
-	SCIF1_RXD_MARK,
-	SCIF1_TXD_MARK,
-	SCIF0_CTS_MARK,
-	INTD_MARK,
-	FCE_MARK,
-	SCIF0_RTS_MARK,
-	HSPI_CS_MARK,
-	FSE_MARK,
-	SCIF0_SCK_MARK,
-	HSPI_CLK_MARK,
-	FRE_MARK,
-	SCIF0_RXD_MARK,
-	HSPI_RX_MARK,
-	FRB_MARK,
-	SCIF0_TXD_MARK,
-	HSPI_TX_MARK,
-	FWE_MARK,
-	SCIF5_TXD_MARK,
-	HAC1_SYNC_MARK,
-	SSI1_WS_MARK,
-	SIOF_TXD_PJ_MARK,
-	HAC0_SDOUT_MARK,
-	SSI0_SDATA_MARK,
-	SIOF_RXD_PJ_MARK,
-	HAC0_SDIN_MARK,
-	SSI0_SCK_MARK,
-	SIOF_SYNC_PJ_MARK,
-	HAC0_SYNC_MARK,
-	SSI0_WS_MARK,
-	SIOF_MCLK_PJ_MARK,
-	HAC_RES_MARK,
-	SIOF_SCK_PJ_MARK,
-	HAC0_BITCLK_MARK,
-	SSI0_CLK_MARK,
-	HAC1_BITCLK_MARK,
-	SSI1_CLK_MARK,
-	TCLK_MARK,
-	IOIS16_MARK,
-	STATUS0_MARK,
-	DRAK0_PK3_MARK,
-	STATUS1_MARK,
-	DRAK1_PK2_MARK,
-	DACK2_MARK,
-	SCIF2_TXD_MARK,
-	MMCCMD_MARK,
-	SIOF_TXD_PK_MARK,
-	DACK3_MARK,
-	SCIF2_SCK_MARK,
-	MMCDAT_MARK,
-	SIOF_SCK_PK_MARK,
-	DREQ0_MARK,
-	DREQ1_MARK,
-	DRAK0_PK1_MARK,
-	DRAK1_PK0_MARK,
-	DREQ2_MARK,
-	INTB_MARK,
-	DREQ3_MARK,
-	INTC_MARK,
-	DRAK2_MARK,
-	CE2A_MARK,
-	IRL4_MARK,
-	FD4_MARK,
-	IRL5_MARK,
-	FD5_MARK,
-	IRL6_MARK,
-	FD6_MARK,
-	IRL7_MARK,
-	FD7_MARK,
-	DRAK3_MARK,
-	CE2B_MARK,
-	BREQ_BSACK_MARK,
-	BACK_BSREQ_MARK,
-	SCIF5_RXD_MARK,
-	HAC1_SDIN_MARK,
-	SSI1_SCK_MARK,
-	SCIF5_SCK_MARK,
-	HAC1_SDOUT_MARK,
-	SSI1_SDATA_MARK,
-	SCIF3_TXD_MARK,
-	FCLE_MARK,
-	SCIF3_RXD_MARK,
-	FALE_MARK,
-	SCIF3_SCK_MARK,
-	FD0_MARK,
-	SCIF4_TXD_MARK,
-	FD1_MARK,
-	SCIF4_RXD_MARK,
-	FD2_MARK,
-	SCIF4_SCK_MARK,
-	FD3_MARK,
-	DEVSEL_DCLKOUT_MARK,
-	STOP_CDE_MARK,
-	LOCK_ODDF_MARK,
-	TRDY_DISPL_MARK,
-	IRDY_HSYNC_MARK,
-	PCIFRAME_VSYNC_MARK,
-	INTA_MARK,
-	GNT0_GNTIN_MARK,
-	REQ0_REQOUT_MARK,
-	PERR_MARK,
-	SERR_MARK,
-	WE7_CBE3_MARK,
-	WE6_CBE2_MARK,
-	WE5_CBE1_MARK,
-	WE4_CBE0_MARK,
-	SCIF2_RXD_MARK,
-	SIOF_RXD_MARK,
-	MRESETOUT_MARK,
-	IRQOUT_MARK,
-	PINMUX_MARK_END,
-};
-
-static const u16 pinmux_data[] = {
-	/* PA GPIO */
-	PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT),
-	PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT),
-	PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT),
-	PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT),
-	PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT),
-	PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT),
-	PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT),
-	PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT),
-
-	/* PB GPIO */
-	PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT),
-	PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT),
-	PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT),
-	PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT),
-	PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT),
-	PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT),
-	PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT),
-	PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT),
-
-	/* PC GPIO */
-	PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT),
-	PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT),
-	PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT),
-	PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT),
-	PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT),
-	PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT),
-	PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT),
-	PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT),
-
-	/* PD GPIO */
-	PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT),
-	PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT),
-	PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT),
-	PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT),
-	PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT),
-	PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT),
-	PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT),
-	PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT),
-
-	/* PE GPIO */
-	PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT),
-	PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT),
-	PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT),
-	PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT),
-	PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT),
-	PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT),
-
-	/* PF GPIO */
-	PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT),
-	PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT),
-	PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT),
-	PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT),
-	PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT),
-	PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT),
-	PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT),
-	PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT),
-
-	/* PG GPIO */
-	PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT),
-	PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT),
-	PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT),
-	PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT),
-	PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT),
-	PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT),
-	PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT),
-	PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT),
-
-	/* PH GPIO */
-	PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT),
-	PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT),
-	PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT),
-	PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT),
-	PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT),
-	PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT),
-	PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT),
-	PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT),
-
-	/* PJ GPIO */
-	PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT),
-	PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT),
-	PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT),
-	PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT),
-	PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT),
-	PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT),
-	PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT),
-	PINMUX_DATA(PJ0_DATA, PJ0_IN, PJ0_OUT),
-
-	/* PK GPIO */
-	PINMUX_DATA(PK7_DATA, PK7_IN, PK7_OUT),
-	PINMUX_DATA(PK6_DATA, PK6_IN, PK6_OUT),
-	PINMUX_DATA(PK5_DATA, PK5_IN, PK5_OUT),
-	PINMUX_DATA(PK4_DATA, PK4_IN, PK4_OUT),
-	PINMUX_DATA(PK3_DATA, PK3_IN, PK3_OUT),
-	PINMUX_DATA(PK2_DATA, PK2_IN, PK2_OUT),
-	PINMUX_DATA(PK1_DATA, PK1_IN, PK1_OUT),
-	PINMUX_DATA(PK0_DATA, PK0_IN, PK0_OUT),
-
-	/* PL GPIO */
-	PINMUX_DATA(PL7_DATA, PL7_IN, PL7_OUT),
-	PINMUX_DATA(PL6_DATA, PL6_IN, PL6_OUT),
-	PINMUX_DATA(PL5_DATA, PL5_IN, PL5_OUT),
-	PINMUX_DATA(PL4_DATA, PL4_IN, PL4_OUT),
-	PINMUX_DATA(PL3_DATA, PL3_IN, PL3_OUT),
-	PINMUX_DATA(PL2_DATA, PL2_IN, PL2_OUT),
-	PINMUX_DATA(PL1_DATA, PL1_IN, PL1_OUT),
-	PINMUX_DATA(PL0_DATA, PL0_IN, PL0_OUT),
-
-	/* PM GPIO */
-	PINMUX_DATA(PM1_DATA, PM1_IN, PM1_OUT),
-	PINMUX_DATA(PM0_DATA, PM0_IN, PM0_OUT),
-
-	/* PN GPIO */
-	PINMUX_DATA(PN7_DATA, PN7_IN, PN7_OUT),
-	PINMUX_DATA(PN6_DATA, PN6_IN, PN6_OUT),
-	PINMUX_DATA(PN5_DATA, PN5_IN, PN5_OUT),
-	PINMUX_DATA(PN4_DATA, PN4_IN, PN4_OUT),
-	PINMUX_DATA(PN3_DATA, PN3_IN, PN3_OUT),
-	PINMUX_DATA(PN2_DATA, PN2_IN, PN2_OUT),
-	PINMUX_DATA(PN1_DATA, PN1_IN, PN1_OUT),
-	PINMUX_DATA(PN0_DATA, PN0_IN, PN0_OUT),
-
-	/* PP GPIO */
-	PINMUX_DATA(PP5_DATA, PP5_IN, PP5_OUT),
-	PINMUX_DATA(PP4_DATA, PP4_IN, PP4_OUT),
-	PINMUX_DATA(PP3_DATA, PP3_IN, PP3_OUT),
-	PINMUX_DATA(PP2_DATA, PP2_IN, PP2_OUT),
-	PINMUX_DATA(PP1_DATA, PP1_IN, PP1_OUT),
-	PINMUX_DATA(PP0_DATA, PP0_IN, PP0_OUT),
-
-	/* PQ GPIO */
-	PINMUX_DATA(PQ4_DATA, PQ4_IN, PQ4_OUT),
-	PINMUX_DATA(PQ3_DATA, PQ3_IN, PQ3_OUT),
-	PINMUX_DATA(PQ2_DATA, PQ2_IN, PQ2_OUT),
-	PINMUX_DATA(PQ1_DATA, PQ1_IN, PQ1_OUT),
-	PINMUX_DATA(PQ0_DATA, PQ0_IN, PQ0_OUT),
-
-	/* PR GPIO */
-	PINMUX_DATA(PR3_DATA, PR3_IN, PR3_OUT),
-	PINMUX_DATA(PR2_DATA, PR2_IN, PR2_OUT),
-	PINMUX_DATA(PR1_DATA, PR1_IN, PR1_OUT),
-	PINMUX_DATA(PR0_DATA, PR0_IN, PR0_OUT),
-
-	/* PA FN */
-	PINMUX_DATA(D63_AD31_MARK, PA7_FN),
-	PINMUX_DATA(D62_AD30_MARK, PA6_FN),
-	PINMUX_DATA(D61_AD29_MARK, PA5_FN),
-	PINMUX_DATA(D60_AD28_MARK, PA4_FN),
-	PINMUX_DATA(D59_AD27_MARK, PA3_FN),
-	PINMUX_DATA(D58_AD26_MARK, PA2_FN),
-	PINMUX_DATA(D57_AD25_MARK, PA1_FN),
-	PINMUX_DATA(D56_AD24_MARK, PA0_FN),
-
-	/* PB FN */
-	PINMUX_DATA(D55_AD23_MARK, PB7_FN),
-	PINMUX_DATA(D54_AD22_MARK, PB6_FN),
-	PINMUX_DATA(D53_AD21_MARK, PB5_FN),
-	PINMUX_DATA(D52_AD20_MARK, PB4_FN),
-	PINMUX_DATA(D51_AD19_MARK, PB3_FN),
-	PINMUX_DATA(D50_AD18_MARK, PB2_FN),
-	PINMUX_DATA(D49_AD17_DB5_MARK, PB1_FN),
-	PINMUX_DATA(D48_AD16_DB4_MARK, PB0_FN),
-
-	/* PC FN */
-	PINMUX_DATA(D47_AD15_DB3_MARK, PC7_FN),
-	PINMUX_DATA(D46_AD14_DB2_MARK, PC6_FN),
-	PINMUX_DATA(D45_AD13_DB1_MARK, PC5_FN),
-	PINMUX_DATA(D44_AD12_DB0_MARK, PC4_FN),
-	PINMUX_DATA(D43_AD11_DG5_MARK, PC3_FN),
-	PINMUX_DATA(D42_AD10_DG4_MARK, PC2_FN),
-	PINMUX_DATA(D41_AD9_DG3_MARK, PC1_FN),
-	PINMUX_DATA(D40_AD8_DG2_MARK, PC0_FN),
-
-	/* PD FN */
-	PINMUX_DATA(D39_AD7_DG1_MARK, PD7_FN),
-	PINMUX_DATA(D38_AD6_DG0_MARK, PD6_FN),
-	PINMUX_DATA(D37_AD5_DR5_MARK, PD5_FN),
-	PINMUX_DATA(D36_AD4_DR4_MARK, PD4_FN),
-	PINMUX_DATA(D35_AD3_DR3_MARK, PD3_FN),
-	PINMUX_DATA(D34_AD2_DR2_MARK, PD2_FN),
-	PINMUX_DATA(D33_AD1_DR1_MARK, PD1_FN),
-	PINMUX_DATA(D32_AD0_DR0_MARK, PD0_FN),
-
-	/* PE FN */
-	PINMUX_DATA(REQ1_MARK, PE5_FN),
-	PINMUX_DATA(REQ2_MARK, PE4_FN),
-	PINMUX_DATA(REQ3_MARK, P2MSEL0_0, PE3_FN),
-	PINMUX_DATA(GNT1_MARK, PE2_FN),
-	PINMUX_DATA(GNT2_MARK, PE1_FN),
-	PINMUX_DATA(GNT3_MARK, P2MSEL0_0, PE0_FN),
-	PINMUX_DATA(MMCCLK_MARK, P2MSEL0_1, PE0_FN),
-
-	/* PF FN */
-	PINMUX_DATA(D31_MARK, PF7_FN),
-	PINMUX_DATA(D30_MARK, PF6_FN),
-	PINMUX_DATA(D29_MARK, PF5_FN),
-	PINMUX_DATA(D28_MARK, PF4_FN),
-	PINMUX_DATA(D27_MARK, PF3_FN),
-	PINMUX_DATA(D26_MARK, PF2_FN),
-	PINMUX_DATA(D25_MARK, PF1_FN),
-	PINMUX_DATA(D24_MARK, PF0_FN),
-
-	/* PF FN */
-	PINMUX_DATA(D23_MARK, PG7_FN),
-	PINMUX_DATA(D22_MARK, PG6_FN),
-	PINMUX_DATA(D21_MARK, PG5_FN),
-	PINMUX_DATA(D20_MARK, PG4_FN),
-	PINMUX_DATA(D19_MARK, PG3_FN),
-	PINMUX_DATA(D18_MARK, PG2_FN),
-	PINMUX_DATA(D17_MARK, PG1_FN),
-	PINMUX_DATA(D16_MARK, PG0_FN),
-
-	/* PH FN */
-	PINMUX_DATA(SCIF1_SCK_MARK, PH7_FN),
-	PINMUX_DATA(SCIF1_RXD_MARK, PH6_FN),
-	PINMUX_DATA(SCIF1_TXD_MARK, PH5_FN),
-	PINMUX_DATA(SCIF0_CTS_MARK, PH4_FN),
-	PINMUX_DATA(INTD_MARK, P1MSEL7_1, PH4_FN),
-	PINMUX_DATA(FCE_MARK, P1MSEL8_1, P1MSEL7_0, PH4_FN),
-	PINMUX_DATA(SCIF0_RTS_MARK, P1MSEL8_0, P1MSEL7_0, PH3_FN),
-	PINMUX_DATA(HSPI_CS_MARK, P1MSEL8_0, P1MSEL7_1, PH3_FN),
-	PINMUX_DATA(FSE_MARK, P1MSEL8_1, P1MSEL7_0, PH3_FN),
-	PINMUX_DATA(SCIF0_SCK_MARK, P1MSEL8_0, P1MSEL7_0, PH2_FN),
-	PINMUX_DATA(HSPI_CLK_MARK, P1MSEL8_0, P1MSEL7_1, PH2_FN),
-	PINMUX_DATA(FRE_MARK, P1MSEL8_1, P1MSEL7_0, PH2_FN),
-	PINMUX_DATA(SCIF0_RXD_MARK, P1MSEL8_0, P1MSEL7_0, PH1_FN),
-	PINMUX_DATA(HSPI_RX_MARK, P1MSEL8_0, P1MSEL7_1, PH1_FN),
-	PINMUX_DATA(FRB_MARK, P1MSEL8_1, P1MSEL7_0, PH1_FN),
-	PINMUX_DATA(SCIF0_TXD_MARK, P1MSEL8_0, P1MSEL7_0, PH0_FN),
-	PINMUX_DATA(HSPI_TX_MARK, P1MSEL8_0, P1MSEL7_1, PH0_FN),
-	PINMUX_DATA(FWE_MARK, P1MSEL8_1, P1MSEL7_0, PH0_FN),
-
-	/* PJ FN */
-	PINMUX_DATA(SCIF5_TXD_MARK, P1MSEL2_0, P1MSEL1_0, PJ7_FN),
-	PINMUX_DATA(HAC1_SYNC_MARK, P1MSEL2_0, P1MSEL1_1, PJ7_FN),
-	PINMUX_DATA(SSI1_WS_MARK, P1MSEL2_1, P1MSEL1_0, PJ7_FN),
-	PINMUX_DATA(SIOF_TXD_PJ_MARK, P2MSEL1_0, P1MSEL4_0, P1MSEL3_0, PJ6_FN),
-	PINMUX_DATA(HAC0_SDOUT_MARK, P1MSEL4_0, P1MSEL3_1, PJ6_FN),
-	PINMUX_DATA(SSI0_SDATA_MARK, P1MSEL4_1, P1MSEL3_0, PJ6_FN),
-	PINMUX_DATA(SIOF_RXD_PJ_MARK, P2MSEL1_0, P1MSEL4_0, P1MSEL3_0, PJ5_FN),
-	PINMUX_DATA(HAC0_SDIN_MARK, P1MSEL4_0, P1MSEL3_1, PJ5_FN),
-	PINMUX_DATA(SSI0_SCK_MARK, P1MSEL4_1, P1MSEL3_0, PJ5_FN),
-	PINMUX_DATA(SIOF_SYNC_PJ_MARK, P2MSEL1_0, P1MSEL4_0, P1MSEL3_0, PJ4_FN),
-	PINMUX_DATA(HAC0_SYNC_MARK, P1MSEL4_0, P1MSEL3_1, PJ4_FN),
-	PINMUX_DATA(SSI0_WS_MARK, P1MSEL4_1, P1MSEL3_0, PJ4_FN),
-	PINMUX_DATA(SIOF_MCLK_PJ_MARK, P2MSEL1_0, P1MSEL4_0, P1MSEL3_0, PJ3_FN),
-	PINMUX_DATA(HAC_RES_MARK, P1MSEL4_0, P1MSEL3_1, PJ3_FN),
-	PINMUX_DATA(SIOF_SCK_PJ_MARK, P2MSEL1_0, P1MSEL4_0, P1MSEL3_0, PJ2_FN),
-	PINMUX_DATA(HAC0_BITCLK_MARK, P1MSEL4_0, P1MSEL3_1, PJ2_FN),
-	PINMUX_DATA(SSI0_CLK_MARK, P1MSEL4_1, P1MSEL3_0, PJ2_FN),
-	PINMUX_DATA(HAC1_BITCLK_MARK, P1MSEL2_0, PJ1_FN),
-	PINMUX_DATA(SSI1_CLK_MARK, P1MSEL2_1, P1MSEL1_0, PJ1_FN),
-	PINMUX_DATA(TCLK_MARK, P1MSEL9_0, PJ0_FN),
-	PINMUX_DATA(IOIS16_MARK, P1MSEL9_1, PJ0_FN),
-
-	/* PK FN */
-	PINMUX_DATA(STATUS0_MARK, P1MSEL15_0, PK7_FN),
-	PINMUX_DATA(DRAK0_PK3_MARK, P1MSEL15_1, PK7_FN),
-	PINMUX_DATA(STATUS1_MARK, P1MSEL15_0, PK6_FN),
-	PINMUX_DATA(DRAK1_PK2_MARK, P1MSEL15_1, PK6_FN),
-	PINMUX_DATA(DACK2_MARK, P1MSEL12_0, P1MSEL11_0, PK5_FN),
-	PINMUX_DATA(SCIF2_TXD_MARK, P1MSEL12_1, P1MSEL11_0, PK5_FN),
-	PINMUX_DATA(MMCCMD_MARK, P1MSEL12_1, P1MSEL11_1, PK5_FN),
-	PINMUX_DATA(SIOF_TXD_PK_MARK, P2MSEL1_1,
-		    P1MSEL12_0, P1MSEL11_1, PK5_FN),
-	PINMUX_DATA(DACK3_MARK, P1MSEL12_0, P1MSEL11_0, PK4_FN),
-	PINMUX_DATA(SCIF2_SCK_MARK, P1MSEL12_1, P1MSEL11_0, PK4_FN),
-	PINMUX_DATA(MMCDAT_MARK, P1MSEL12_1, P1MSEL11_1, PK4_FN),
-	PINMUX_DATA(SIOF_SCK_PK_MARK, P2MSEL1_1,
-		    P1MSEL12_0, P1MSEL11_1, PK4_FN),
-	PINMUX_DATA(DREQ0_MARK, PK3_FN),
-	PINMUX_DATA(DREQ1_MARK, PK2_FN),
-	PINMUX_DATA(DRAK0_PK1_MARK, PK1_FN),
-	PINMUX_DATA(DRAK1_PK0_MARK, PK0_FN),
-
-	/* PL FN */
-	PINMUX_DATA(DREQ2_MARK, P1MSEL13_0, PL7_FN),
-	PINMUX_DATA(INTB_MARK, P1MSEL13_1, PL7_FN),
-	PINMUX_DATA(DREQ3_MARK, P1MSEL13_0, PL6_FN),
-	PINMUX_DATA(INTC_MARK, P1MSEL13_1, PL6_FN),
-	PINMUX_DATA(DRAK2_MARK, P1MSEL10_0, PL5_FN),
-	PINMUX_DATA(CE2A_MARK, P1MSEL10_1, PL5_FN),
-	PINMUX_DATA(IRL4_MARK, P1MSEL14_0, PL4_FN),
-	PINMUX_DATA(FD4_MARK, P1MSEL14_1, PL4_FN),
-	PINMUX_DATA(IRL5_MARK, P1MSEL14_0, PL3_FN),
-	PINMUX_DATA(FD5_MARK, P1MSEL14_1, PL3_FN),
-	PINMUX_DATA(IRL6_MARK, P1MSEL14_0, PL2_FN),
-	PINMUX_DATA(FD6_MARK, P1MSEL14_1, PL2_FN),
-	PINMUX_DATA(IRL7_MARK, P1MSEL14_0, PL1_FN),
-	PINMUX_DATA(FD7_MARK, P1MSEL14_1, PL1_FN),
-	PINMUX_DATA(DRAK3_MARK, P1MSEL10_0, PL0_FN),
-	PINMUX_DATA(CE2B_MARK, P1MSEL10_1, PL0_FN),
-
-	/* PM FN */
-	PINMUX_DATA(BREQ_BSACK_MARK, PM1_FN),
-	PINMUX_DATA(BACK_BSREQ_MARK, PM0_FN),
-
-	/* PN FN */
-	PINMUX_DATA(SCIF5_RXD_MARK, P1MSEL2_0, P1MSEL1_0, PN7_FN),
-	PINMUX_DATA(HAC1_SDIN_MARK, P1MSEL2_0, P1MSEL1_1, PN7_FN),
-	PINMUX_DATA(SSI1_SCK_MARK, P1MSEL2_1, P1MSEL1_0, PN7_FN),
-	PINMUX_DATA(SCIF5_SCK_MARK, P1MSEL2_0, P1MSEL1_0, PN6_FN),
-	PINMUX_DATA(HAC1_SDOUT_MARK, P1MSEL2_0, P1MSEL1_1, PN6_FN),
-	PINMUX_DATA(SSI1_SDATA_MARK, P1MSEL2_1, P1MSEL1_0, PN6_FN),
-	PINMUX_DATA(SCIF3_TXD_MARK, P1MSEL0_0, PN5_FN),
-	PINMUX_DATA(FCLE_MARK, P1MSEL0_1, PN5_FN),
-	PINMUX_DATA(SCIF3_RXD_MARK, P1MSEL0_0, PN4_FN),
-	PINMUX_DATA(FALE_MARK, P1MSEL0_1, PN4_FN),
-	PINMUX_DATA(SCIF3_SCK_MARK, P1MSEL0_0, PN3_FN),
-	PINMUX_DATA(FD0_MARK, P1MSEL0_1, PN3_FN),
-	PINMUX_DATA(SCIF4_TXD_MARK, P1MSEL0_0, PN2_FN),
-	PINMUX_DATA(FD1_MARK, P1MSEL0_1, PN2_FN),
-	PINMUX_DATA(SCIF4_RXD_MARK, P1MSEL0_0, PN1_FN),
-	PINMUX_DATA(FD2_MARK, P1MSEL0_1, PN1_FN),
-	PINMUX_DATA(SCIF4_SCK_MARK, P1MSEL0_0, PN0_FN),
-	PINMUX_DATA(FD3_MARK, P1MSEL0_1, PN0_FN),
-
-	/* PP FN */
-	PINMUX_DATA(DEVSEL_DCLKOUT_MARK, PP5_FN),
-	PINMUX_DATA(STOP_CDE_MARK, PP4_FN),
-	PINMUX_DATA(LOCK_ODDF_MARK, PP3_FN),
-	PINMUX_DATA(TRDY_DISPL_MARK, PP2_FN),
-	PINMUX_DATA(IRDY_HSYNC_MARK, PP1_FN),
-	PINMUX_DATA(PCIFRAME_VSYNC_MARK, PP0_FN),
-
-	/* PQ FN */
-	PINMUX_DATA(INTA_MARK, PQ4_FN),
-	PINMUX_DATA(GNT0_GNTIN_MARK, PQ3_FN),
-	PINMUX_DATA(REQ0_REQOUT_MARK, PQ2_FN),
-	PINMUX_DATA(PERR_MARK, PQ1_FN),
-	PINMUX_DATA(SERR_MARK, PQ0_FN),
-
-	/* PR FN */
-	PINMUX_DATA(WE7_CBE3_MARK, PR3_FN),
-	PINMUX_DATA(WE6_CBE2_MARK, PR2_FN),
-	PINMUX_DATA(WE5_CBE1_MARK, PR1_FN),
-	PINMUX_DATA(WE4_CBE0_MARK, PR0_FN),
-
-	/* MISC FN */
-	PINMUX_DATA(SCIF2_RXD_MARK, P1MSEL6_0, P1MSEL5_0),
-	PINMUX_DATA(SIOF_RXD_MARK, P2MSEL1_1, P1MSEL6_1, P1MSEL5_0),
-	PINMUX_DATA(MRESETOUT_MARK, P2MSEL2_0),
-	PINMUX_DATA(IRQOUT_MARK, P2MSEL2_1),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	/* PA */
-	PINMUX_GPIO(PA7),
-	PINMUX_GPIO(PA6),
-	PINMUX_GPIO(PA5),
-	PINMUX_GPIO(PA4),
-	PINMUX_GPIO(PA3),
-	PINMUX_GPIO(PA2),
-	PINMUX_GPIO(PA1),
-	PINMUX_GPIO(PA0),
-
-	/* PB */
-	PINMUX_GPIO(PB7),
-	PINMUX_GPIO(PB6),
-	PINMUX_GPIO(PB5),
-	PINMUX_GPIO(PB4),
-	PINMUX_GPIO(PB3),
-	PINMUX_GPIO(PB2),
-	PINMUX_GPIO(PB1),
-	PINMUX_GPIO(PB0),
-
-	/* PC */
-	PINMUX_GPIO(PC7),
-	PINMUX_GPIO(PC6),
-	PINMUX_GPIO(PC5),
-	PINMUX_GPIO(PC4),
-	PINMUX_GPIO(PC3),
-	PINMUX_GPIO(PC2),
-	PINMUX_GPIO(PC1),
-	PINMUX_GPIO(PC0),
-
-	/* PD */
-	PINMUX_GPIO(PD7),
-	PINMUX_GPIO(PD6),
-	PINMUX_GPIO(PD5),
-	PINMUX_GPIO(PD4),
-	PINMUX_GPIO(PD3),
-	PINMUX_GPIO(PD2),
-	PINMUX_GPIO(PD1),
-	PINMUX_GPIO(PD0),
-
-	/* PE */
-	PINMUX_GPIO(PE5),
-	PINMUX_GPIO(PE4),
-	PINMUX_GPIO(PE3),
-	PINMUX_GPIO(PE2),
-	PINMUX_GPIO(PE1),
-	PINMUX_GPIO(PE0),
-
-	/* PF */
-	PINMUX_GPIO(PF7),
-	PINMUX_GPIO(PF6),
-	PINMUX_GPIO(PF5),
-	PINMUX_GPIO(PF4),
-	PINMUX_GPIO(PF3),
-	PINMUX_GPIO(PF2),
-	PINMUX_GPIO(PF1),
-	PINMUX_GPIO(PF0),
-
-	/* PG */
-	PINMUX_GPIO(PG7),
-	PINMUX_GPIO(PG6),
-	PINMUX_GPIO(PG5),
-	PINMUX_GPIO(PG4),
-	PINMUX_GPIO(PG3),
-	PINMUX_GPIO(PG2),
-	PINMUX_GPIO(PG1),
-	PINMUX_GPIO(PG0),
-
-	/* PH */
-	PINMUX_GPIO(PH7),
-	PINMUX_GPIO(PH6),
-	PINMUX_GPIO(PH5),
-	PINMUX_GPIO(PH4),
-	PINMUX_GPIO(PH3),
-	PINMUX_GPIO(PH2),
-	PINMUX_GPIO(PH1),
-	PINMUX_GPIO(PH0),
-
-	/* PJ */
-	PINMUX_GPIO(PJ7),
-	PINMUX_GPIO(PJ6),
-	PINMUX_GPIO(PJ5),
-	PINMUX_GPIO(PJ4),
-	PINMUX_GPIO(PJ3),
-	PINMUX_GPIO(PJ2),
-	PINMUX_GPIO(PJ1),
-	PINMUX_GPIO(PJ0),
-
-	/* PK */
-	PINMUX_GPIO(PK7),
-	PINMUX_GPIO(PK6),
-	PINMUX_GPIO(PK5),
-	PINMUX_GPIO(PK4),
-	PINMUX_GPIO(PK3),
-	PINMUX_GPIO(PK2),
-	PINMUX_GPIO(PK1),
-	PINMUX_GPIO(PK0),
-
-	/* PL */
-	PINMUX_GPIO(PL7),
-	PINMUX_GPIO(PL6),
-	PINMUX_GPIO(PL5),
-	PINMUX_GPIO(PL4),
-	PINMUX_GPIO(PL3),
-	PINMUX_GPIO(PL2),
-	PINMUX_GPIO(PL1),
-	PINMUX_GPIO(PL0),
-
-	/* PM */
-	PINMUX_GPIO(PM1),
-	PINMUX_GPIO(PM0),
-
-	/* PN */
-	PINMUX_GPIO(PN7),
-	PINMUX_GPIO(PN6),
-	PINMUX_GPIO(PN5),
-	PINMUX_GPIO(PN4),
-	PINMUX_GPIO(PN3),
-	PINMUX_GPIO(PN2),
-	PINMUX_GPIO(PN1),
-	PINMUX_GPIO(PN0),
-
-	/* PP */
-	PINMUX_GPIO(PP5),
-	PINMUX_GPIO(PP4),
-	PINMUX_GPIO(PP3),
-	PINMUX_GPIO(PP2),
-	PINMUX_GPIO(PP1),
-	PINMUX_GPIO(PP0),
-
-	/* PQ */
-	PINMUX_GPIO(PQ4),
-	PINMUX_GPIO(PQ3),
-	PINMUX_GPIO(PQ2),
-	PINMUX_GPIO(PQ1),
-	PINMUX_GPIO(PQ0),
-
-	/* PR */
-	PINMUX_GPIO(PR3),
-	PINMUX_GPIO(PR2),
-	PINMUX_GPIO(PR1),
-	PINMUX_GPIO(PR0),
-};
-
-#define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-	/* FN */
-	GPIO_FN(D63_AD31),
-	GPIO_FN(D62_AD30),
-	GPIO_FN(D61_AD29),
-	GPIO_FN(D60_AD28),
-	GPIO_FN(D59_AD27),
-	GPIO_FN(D58_AD26),
-	GPIO_FN(D57_AD25),
-	GPIO_FN(D56_AD24),
-	GPIO_FN(D55_AD23),
-	GPIO_FN(D54_AD22),
-	GPIO_FN(D53_AD21),
-	GPIO_FN(D52_AD20),
-	GPIO_FN(D51_AD19),
-	GPIO_FN(D50_AD18),
-	GPIO_FN(D49_AD17_DB5),
-	GPIO_FN(D48_AD16_DB4),
-	GPIO_FN(D47_AD15_DB3),
-	GPIO_FN(D46_AD14_DB2),
-	GPIO_FN(D45_AD13_DB1),
-	GPIO_FN(D44_AD12_DB0),
-	GPIO_FN(D43_AD11_DG5),
-	GPIO_FN(D42_AD10_DG4),
-	GPIO_FN(D41_AD9_DG3),
-	GPIO_FN(D40_AD8_DG2),
-	GPIO_FN(D39_AD7_DG1),
-	GPIO_FN(D38_AD6_DG0),
-	GPIO_FN(D37_AD5_DR5),
-	GPIO_FN(D36_AD4_DR4),
-	GPIO_FN(D35_AD3_DR3),
-	GPIO_FN(D34_AD2_DR2),
-	GPIO_FN(D33_AD1_DR1),
-	GPIO_FN(D32_AD0_DR0),
-	GPIO_FN(REQ1),
-	GPIO_FN(REQ2),
-	GPIO_FN(REQ3),
-	GPIO_FN(GNT1),
-	GPIO_FN(GNT2),
-	GPIO_FN(GNT3),
-	GPIO_FN(MMCCLK),
-	GPIO_FN(D31),
-	GPIO_FN(D30),
-	GPIO_FN(D29),
-	GPIO_FN(D28),
-	GPIO_FN(D27),
-	GPIO_FN(D26),
-	GPIO_FN(D25),
-	GPIO_FN(D24),
-	GPIO_FN(D23),
-	GPIO_FN(D22),
-	GPIO_FN(D21),
-	GPIO_FN(D20),
-	GPIO_FN(D19),
-	GPIO_FN(D18),
-	GPIO_FN(D17),
-	GPIO_FN(D16),
-	GPIO_FN(SCIF1_SCK),
-	GPIO_FN(SCIF1_RXD),
-	GPIO_FN(SCIF1_TXD),
-	GPIO_FN(SCIF0_CTS),
-	GPIO_FN(INTD),
-	GPIO_FN(FCE),
-	GPIO_FN(SCIF0_RTS),
-	GPIO_FN(HSPI_CS),
-	GPIO_FN(FSE),
-	GPIO_FN(SCIF0_SCK),
-	GPIO_FN(HSPI_CLK),
-	GPIO_FN(FRE),
-	GPIO_FN(SCIF0_RXD),
-	GPIO_FN(HSPI_RX),
-	GPIO_FN(FRB),
-	GPIO_FN(SCIF0_TXD),
-	GPIO_FN(HSPI_TX),
-	GPIO_FN(FWE),
-	GPIO_FN(SCIF5_TXD),
-	GPIO_FN(HAC1_SYNC),
-	GPIO_FN(SSI1_WS),
-	GPIO_FN(SIOF_TXD_PJ),
-	GPIO_FN(HAC0_SDOUT),
-	GPIO_FN(SSI0_SDATA),
-	GPIO_FN(SIOF_RXD_PJ),
-	GPIO_FN(HAC0_SDIN),
-	GPIO_FN(SSI0_SCK),
-	GPIO_FN(SIOF_SYNC_PJ),
-	GPIO_FN(HAC0_SYNC),
-	GPIO_FN(SSI0_WS),
-	GPIO_FN(SIOF_MCLK_PJ),
-	GPIO_FN(HAC_RES),
-	GPIO_FN(SIOF_SCK_PJ),
-	GPIO_FN(HAC0_BITCLK),
-	GPIO_FN(SSI0_CLK),
-	GPIO_FN(HAC1_BITCLK),
-	GPIO_FN(SSI1_CLK),
-	GPIO_FN(TCLK),
-	GPIO_FN(IOIS16),
-	GPIO_FN(STATUS0),
-	GPIO_FN(DRAK0_PK3),
-	GPIO_FN(STATUS1),
-	GPIO_FN(DRAK1_PK2),
-	GPIO_FN(DACK2),
-	GPIO_FN(SCIF2_TXD),
-	GPIO_FN(MMCCMD),
-	GPIO_FN(SIOF_TXD_PK),
-	GPIO_FN(DACK3),
-	GPIO_FN(SCIF2_SCK),
-	GPIO_FN(MMCDAT),
-	GPIO_FN(SIOF_SCK_PK),
-	GPIO_FN(DREQ0),
-	GPIO_FN(DREQ1),
-	GPIO_FN(DRAK0_PK1),
-	GPIO_FN(DRAK1_PK0),
-	GPIO_FN(DREQ2),
-	GPIO_FN(INTB),
-	GPIO_FN(DREQ3),
-	GPIO_FN(INTC),
-	GPIO_FN(DRAK2),
-	GPIO_FN(CE2A),
-	GPIO_FN(IRL4),
-	GPIO_FN(FD4),
-	GPIO_FN(IRL5),
-	GPIO_FN(FD5),
-	GPIO_FN(IRL6),
-	GPIO_FN(FD6),
-	GPIO_FN(IRL7),
-	GPIO_FN(FD7),
-	GPIO_FN(DRAK3),
-	GPIO_FN(CE2B),
-	GPIO_FN(BREQ_BSACK),
-	GPIO_FN(BACK_BSREQ),
-	GPIO_FN(SCIF5_RXD),
-	GPIO_FN(HAC1_SDIN),
-	GPIO_FN(SSI1_SCK),
-	GPIO_FN(SCIF5_SCK),
-	GPIO_FN(HAC1_SDOUT),
-	GPIO_FN(SSI1_SDATA),
-	GPIO_FN(SCIF3_TXD),
-	GPIO_FN(FCLE),
-	GPIO_FN(SCIF3_RXD),
-	GPIO_FN(FALE),
-	GPIO_FN(SCIF3_SCK),
-	GPIO_FN(FD0),
-	GPIO_FN(SCIF4_TXD),
-	GPIO_FN(FD1),
-	GPIO_FN(SCIF4_RXD),
-	GPIO_FN(FD2),
-	GPIO_FN(SCIF4_SCK),
-	GPIO_FN(FD3),
-	GPIO_FN(DEVSEL_DCLKOUT),
-	GPIO_FN(STOP_CDE),
-	GPIO_FN(LOCK_ODDF),
-	GPIO_FN(TRDY_DISPL),
-	GPIO_FN(IRDY_HSYNC),
-	GPIO_FN(PCIFRAME_VSYNC),
-	GPIO_FN(INTA),
-	GPIO_FN(GNT0_GNTIN),
-	GPIO_FN(REQ0_REQOUT),
-	GPIO_FN(PERR),
-	GPIO_FN(SERR),
-	GPIO_FN(WE7_CBE3),
-	GPIO_FN(WE6_CBE2),
-	GPIO_FN(WE5_CBE1),
-	GPIO_FN(WE4_CBE0),
-	GPIO_FN(SCIF2_RXD),
-	GPIO_FN(SIOF_RXD),
-	GPIO_FN(MRESETOUT),
-	GPIO_FN(IRQOUT),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	{ PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2, GROUP(
-		PA7_FN, PA7_OUT, PA7_IN, 0,
-		PA6_FN, PA6_OUT, PA6_IN, 0,
-		PA5_FN, PA5_OUT, PA5_IN, 0,
-		PA4_FN, PA4_OUT, PA4_IN, 0,
-		PA3_FN, PA3_OUT, PA3_IN, 0,
-		PA2_FN, PA2_OUT, PA2_IN, 0,
-		PA1_FN, PA1_OUT, PA1_IN, 0,
-		PA0_FN, PA0_OUT, PA0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PBCR", 0xffe70002, 16, 2, GROUP(
-		PB7_FN, PB7_OUT, PB7_IN, 0,
-		PB6_FN, PB6_OUT, PB6_IN, 0,
-		PB5_FN, PB5_OUT, PB5_IN, 0,
-		PB4_FN, PB4_OUT, PB4_IN, 0,
-		PB3_FN, PB3_OUT, PB3_IN, 0,
-		PB2_FN, PB2_OUT, PB2_IN, 0,
-		PB1_FN, PB1_OUT, PB1_IN, 0,
-		PB0_FN, PB0_OUT, PB0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PCCR", 0xffe70004, 16, 2, GROUP(
-		PC7_FN, PC7_OUT, PC7_IN, 0,
-		PC6_FN, PC6_OUT, PC6_IN, 0,
-		PC5_FN, PC5_OUT, PC5_IN, 0,
-		PC4_FN, PC4_OUT, PC4_IN, 0,
-		PC3_FN, PC3_OUT, PC3_IN, 0,
-		PC2_FN, PC2_OUT, PC2_IN, 0,
-		PC1_FN, PC1_OUT, PC1_IN, 0,
-		PC0_FN, PC0_OUT, PC0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PDCR", 0xffe70006, 16, 2, GROUP(
-		PD7_FN, PD7_OUT, PD7_IN, 0,
-		PD6_FN, PD6_OUT, PD6_IN, 0,
-		PD5_FN, PD5_OUT, PD5_IN, 0,
-		PD4_FN, PD4_OUT, PD4_IN, 0,
-		PD3_FN, PD3_OUT, PD3_IN, 0,
-		PD2_FN, PD2_OUT, PD2_IN, 0,
-		PD1_FN, PD1_OUT, PD1_IN, 0,
-		PD0_FN, PD0_OUT, PD0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PECR", 0xffe70008, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PE5_FN, PE5_OUT, PE5_IN, 0,
-		PE4_FN, PE4_OUT, PE4_IN, 0,
-		PE3_FN, PE3_OUT, PE3_IN, 0,
-		PE2_FN, PE2_OUT, PE2_IN, 0,
-		PE1_FN, PE1_OUT, PE1_IN, 0,
-		PE0_FN, PE0_OUT, PE0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PFCR", 0xffe7000a, 16, 2, GROUP(
-		PF7_FN, PF7_OUT, PF7_IN, 0,
-		PF6_FN, PF6_OUT, PF6_IN, 0,
-		PF5_FN, PF5_OUT, PF5_IN, 0,
-		PF4_FN, PF4_OUT, PF4_IN, 0,
-		PF3_FN, PF3_OUT, PF3_IN, 0,
-		PF2_FN, PF2_OUT, PF2_IN, 0,
-		PF1_FN, PF1_OUT, PF1_IN, 0,
-		PF0_FN, PF0_OUT, PF0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PGCR", 0xffe7000c, 16, 2, GROUP(
-		PG7_FN, PG7_OUT, PG7_IN, 0,
-		PG6_FN, PG6_OUT, PG6_IN, 0,
-		PG5_FN, PG5_OUT, PG5_IN, 0,
-		PG4_FN, PG4_OUT, PG4_IN, 0,
-		PG3_FN, PG3_OUT, PG3_IN, 0,
-		PG2_FN, PG2_OUT, PG2_IN, 0,
-		PG1_FN, PG1_OUT, PG1_IN, 0,
-		PG0_FN, PG0_OUT, PG0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PHCR", 0xffe7000e, 16, 2, GROUP(
-		PH7_FN, PH7_OUT, PH7_IN, 0,
-		PH6_FN, PH6_OUT, PH6_IN, 0,
-		PH5_FN, PH5_OUT, PH5_IN, 0,
-		PH4_FN, PH4_OUT, PH4_IN, 0,
-		PH3_FN, PH3_OUT, PH3_IN, 0,
-		PH2_FN, PH2_OUT, PH2_IN, 0,
-		PH1_FN, PH1_OUT, PH1_IN, 0,
-		PH0_FN, PH0_OUT, PH0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PJCR", 0xffe70010, 16, 2, GROUP(
-		PJ7_FN, PJ7_OUT, PJ7_IN, 0,
-		PJ6_FN, PJ6_OUT, PJ6_IN, 0,
-		PJ5_FN, PJ5_OUT, PJ5_IN, 0,
-		PJ4_FN, PJ4_OUT, PJ4_IN, 0,
-		PJ3_FN, PJ3_OUT, PJ3_IN, 0,
-		PJ2_FN, PJ2_OUT, PJ2_IN, 0,
-		PJ1_FN, PJ1_OUT, PJ1_IN, 0,
-		PJ0_FN, PJ0_OUT, PJ0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PKCR", 0xffe70012, 16, 2, GROUP(
-		PK7_FN, PK7_OUT, PK7_IN, 0,
-		PK6_FN, PK6_OUT, PK6_IN, 0,
-		PK5_FN, PK5_OUT, PK5_IN, 0,
-		PK4_FN, PK4_OUT, PK4_IN, 0,
-		PK3_FN, PK3_OUT, PK3_IN, 0,
-		PK2_FN, PK2_OUT, PK2_IN, 0,
-		PK1_FN, PK1_OUT, PK1_IN, 0,
-		PK0_FN, PK0_OUT, PK0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PLCR", 0xffe70014, 16, 2, GROUP(
-		PL7_FN, PL7_OUT, PL7_IN, 0,
-		PL6_FN, PL6_OUT, PL6_IN, 0,
-		PL5_FN, PL5_OUT, PL5_IN, 0,
-		PL4_FN, PL4_OUT, PL4_IN, 0,
-		PL3_FN, PL3_OUT, PL3_IN, 0,
-		PL2_FN, PL2_OUT, PL2_IN, 0,
-		PL1_FN, PL1_OUT, PL1_IN, 0,
-		PL0_FN, PL0_OUT, PL0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PMCR", 0xffe70016, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PM1_FN, PM1_OUT, PM1_IN, 0,
-		PM0_FN, PM0_OUT, PM0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PNCR", 0xffe70018, 16, 2, GROUP(
-		PN7_FN, PN7_OUT, PN7_IN, 0,
-		PN6_FN, PN6_OUT, PN6_IN, 0,
-		PN5_FN, PN5_OUT, PN5_IN, 0,
-		PN4_FN, PN4_OUT, PN4_IN, 0,
-		PN3_FN, PN3_OUT, PN3_IN, 0,
-		PN2_FN, PN2_OUT, PN2_IN, 0,
-		PN1_FN, PN1_OUT, PN1_IN, 0,
-		PN0_FN, PN0_OUT, PN0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PPCR", 0xffe7001a, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PP5_FN, PP5_OUT, PP5_IN, 0,
-		PP4_FN, PP4_OUT, PP4_IN, 0,
-		PP3_FN, PP3_OUT, PP3_IN, 0,
-		PP2_FN, PP2_OUT, PP2_IN, 0,
-		PP1_FN, PP1_OUT, PP1_IN, 0,
-		PP0_FN, PP0_OUT, PP0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PQCR", 0xffe7001c, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PQ4_FN, PQ4_OUT, PQ4_IN, 0,
-		PQ3_FN, PQ3_OUT, PQ3_IN, 0,
-		PQ2_FN, PQ2_OUT, PQ2_IN, 0,
-		PQ1_FN, PQ1_OUT, PQ1_IN, 0,
-		PQ0_FN, PQ0_OUT, PQ0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PRCR", 0xffe7001e, 16, 2, GROUP(
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PR3_FN, PR3_OUT, PR3_IN, 0,
-		PR2_FN, PR2_OUT, PR2_IN, 0,
-		PR1_FN, PR1_OUT, PR1_IN, 0,
-		PR0_FN, PR0_OUT, PR0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("P1MSELR", 0xffe70080, 16, 1, GROUP(
-		P1MSEL15_0, P1MSEL15_1,
-		P1MSEL14_0, P1MSEL14_1,
-		P1MSEL13_0, P1MSEL13_1,
-		P1MSEL12_0, P1MSEL12_1,
-		P1MSEL11_0, P1MSEL11_1,
-		P1MSEL10_0, P1MSEL10_1,
-		P1MSEL9_0, P1MSEL9_1,
-		P1MSEL8_0, P1MSEL8_1,
-		P1MSEL7_0, P1MSEL7_1,
-		P1MSEL6_0, P1MSEL6_1,
-		P1MSEL5_0, 0,
-		P1MSEL4_0, P1MSEL4_1,
-		P1MSEL3_0, P1MSEL3_1,
-		P1MSEL2_0, P1MSEL2_1,
-		P1MSEL1_0, P1MSEL1_1,
-		P1MSEL0_0, P1MSEL0_1 ))
-	},
-	{ PINMUX_CFG_REG("P2MSELR", 0xffe70082, 16, 1, GROUP(
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		P2MSEL2_0, P2MSEL2_1,
-		P2MSEL1_0, P2MSEL1_1,
-		P2MSEL0_0, P2MSEL0_1 ))
-	},
-	{}
-};
-
-static const struct pinmux_data_reg pinmux_data_regs[] = {
-	{ PINMUX_DATA_REG("PADR", 0xffe70020, 8, GROUP(
-		PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
-		PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PBDR", 0xffe70022, 8, GROUP(
-		PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
-		PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PCDR", 0xffe70024, 8, GROUP(
-		PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
-		PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PDDR", 0xffe70026, 8, GROUP(
-		PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
-		PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PEDR", 0xffe70028, 8, GROUP(
-		0, 0, PE5_DATA, PE4_DATA,
-		PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PFDR", 0xffe7002a, 8, GROUP(
-		PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
-		PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PGDR", 0xffe7002c, 8, GROUP(
-		PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
-		PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PHDR", 0xffe7002e, 8, GROUP(
-		PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
-		PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PJDR", 0xffe70030, 8, GROUP(
-		PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
-		PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PKDR", 0xffe70032, 8, GROUP(
-		PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
-		PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PLDR", 0xffe70034, 8, GROUP(
-		PL7_DATA, PL6_DATA, PL5_DATA, PL4_DATA,
-		PL3_DATA, PL2_DATA, PL1_DATA, PL0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PMDR", 0xffe70036, 8, GROUP(
-		0, 0, 0, 0,
-		0, 0, PM1_DATA, PM0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PNDR", 0xffe70038, 8, GROUP(
-		PN7_DATA, PN6_DATA, PN5_DATA, PN4_DATA,
-		PN3_DATA, PN2_DATA, PN1_DATA, PN0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PPDR", 0xffe7003a, 8, GROUP(
-		0, 0, PP5_DATA, PP4_DATA,
-		PP3_DATA, PP2_DATA, PP1_DATA, PP0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PQDR", 0xffe7003c, 8, GROUP(
-		0, 0, 0, PQ4_DATA,
-		PQ3_DATA, PQ2_DATA, PQ1_DATA, PQ0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PRDR", 0xffe7003e, 8, GROUP(
-		0, 0, 0, 0,
-		PR3_DATA, PR2_DATA, PR1_DATA, PR0_DATA ))
-	},
-	{ },
-};
-
-const struct sh_pfc_soc_info sh7785_pinmux_info = {
-	.name = "sh7785_pfc",
-	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.func_gpios = pinmux_func_gpios,
-	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
-	.cfg_regs = pinmux_config_regs,
-	.data_regs = pinmux_data_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
deleted file mode 100644
index b8a098cd7721..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c
+++ /dev/null
@@ -1,815 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * SH7786 Pinmux
- *
- * Copyright (C) 2008, 2009  Renesas Solutions Corp.
- * Kuninori Morimoto <morimoto.kuninori@renesas.com>
- *
- *  Based on SH7785 pinmux
- *
- *  Copyright (C) 2008  Magnus Damm
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <cpu/sh7786.h>
-
-#include "sh_pfc.h"
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
-	PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
-	PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
-	PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
-	PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
-	PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
-	PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
-	PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
-	PE7_DATA, PE6_DATA,
-	PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
-	PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
-	PG7_DATA, PG6_DATA, PG5_DATA,
-	PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
-	PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
-	PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
-	PJ3_DATA, PJ2_DATA, PJ1_DATA,
-	PINMUX_DATA_END,
-
-	PINMUX_INPUT_BEGIN,
-	PA7_IN, PA6_IN, PA5_IN, PA4_IN,
-	PA3_IN, PA2_IN, PA1_IN, PA0_IN,
-	PB7_IN, PB6_IN, PB5_IN, PB4_IN,
-	PB3_IN, PB2_IN, PB1_IN, PB0_IN,
-	PC7_IN, PC6_IN, PC5_IN, PC4_IN,
-	PC3_IN, PC2_IN, PC1_IN, PC0_IN,
-	PD7_IN, PD6_IN, PD5_IN, PD4_IN,
-	PD3_IN, PD2_IN, PD1_IN, PD0_IN,
-	PE7_IN, PE6_IN,
-	PF7_IN, PF6_IN, PF5_IN, PF4_IN,
-	PF3_IN, PF2_IN, PF1_IN, PF0_IN,
-	PG7_IN, PG6_IN, PG5_IN,
-	PH7_IN, PH6_IN, PH5_IN, PH4_IN,
-	PH3_IN, PH2_IN, PH1_IN, PH0_IN,
-	PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
-	PJ3_IN, PJ2_IN, PJ1_IN,
-	PINMUX_INPUT_END,
-
-	PINMUX_OUTPUT_BEGIN,
-	PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
-	PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
-	PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
-	PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
-	PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
-	PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
-	PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
-	PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
-	PE7_OUT, PE6_OUT,
-	PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
-	PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
-	PG7_OUT, PG6_OUT, PG5_OUT,
-	PH7_OUT, PH6_OUT, PH5_OUT, PH4_OUT,
-	PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
-	PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
-	PJ3_OUT, PJ2_OUT, PJ1_OUT,
-	PINMUX_OUTPUT_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	PA7_FN, PA6_FN, PA5_FN, PA4_FN,
-	PA3_FN, PA2_FN, PA1_FN, PA0_FN,
-	PB7_FN, PB6_FN, PB5_FN, PB4_FN,
-	PB3_FN, PB2_FN, PB1_FN, PB0_FN,
-	PC7_FN, PC6_FN, PC5_FN, PC4_FN,
-	PC3_FN, PC2_FN, PC1_FN, PC0_FN,
-	PD7_FN, PD6_FN, PD5_FN, PD4_FN,
-	PD3_FN, PD2_FN, PD1_FN, PD0_FN,
-	PE7_FN, PE6_FN,
-	PF7_FN, PF6_FN, PF5_FN, PF4_FN,
-	PF3_FN, PF2_FN, PF1_FN, PF0_FN,
-	PG7_FN, PG6_FN, PG5_FN,
-	PH7_FN, PH6_FN, PH5_FN, PH4_FN,
-	PH3_FN, PH2_FN, PH1_FN, PH0_FN,
-	PJ7_FN, PJ6_FN, PJ5_FN, PJ4_FN,
-	PJ3_FN, PJ2_FN, PJ1_FN,
-	P1MSEL14_0, P1MSEL14_1,
-	P1MSEL13_0, P1MSEL13_1,
-	P1MSEL12_0, P1MSEL12_1,
-	P1MSEL11_0, P1MSEL11_1,
-	P1MSEL10_0, P1MSEL10_1,
-	P1MSEL9_0, P1MSEL9_1,
-	P1MSEL8_0, P1MSEL8_1,
-	P1MSEL7_0, P1MSEL7_1,
-	P1MSEL6_0, P1MSEL6_1,
-	P1MSEL5_0, P1MSEL5_1,
-	P1MSEL4_0, P1MSEL4_1,
-	P1MSEL3_0, P1MSEL3_1,
-	P1MSEL2_0, P1MSEL2_1,
-	P1MSEL1_0, P1MSEL1_1,
-	P1MSEL0_0, P1MSEL0_1,
-
-	P2MSEL15_0, P2MSEL15_1,
-	P2MSEL14_0, P2MSEL14_1,
-	P2MSEL13_0, P2MSEL13_1,
-	P2MSEL12_0, P2MSEL12_1,
-	P2MSEL11_0, P2MSEL11_1,
-	P2MSEL10_0, P2MSEL10_1,
-	P2MSEL9_0, P2MSEL9_1,
-	P2MSEL8_0, P2MSEL8_1,
-	P2MSEL7_0, P2MSEL7_1,
-	P2MSEL6_0, P2MSEL6_1,
-	P2MSEL5_0, P2MSEL5_1,
-	P2MSEL4_0, P2MSEL4_1,
-	P2MSEL3_0, P2MSEL3_1,
-	P2MSEL2_0, P2MSEL2_1,
-	P2MSEL1_0, P2MSEL1_1,
-	P2MSEL0_0, P2MSEL0_1,
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-	DCLKIN_MARK, DCLKOUT_MARK, ODDF_MARK,
-	VSYNC_MARK, HSYNC_MARK, CDE_MARK, DISP_MARK,
-	DR0_MARK, DR1_MARK, DR2_MARK, DR3_MARK, DR4_MARK, DR5_MARK,
-	DG0_MARK, DG1_MARK, DG2_MARK, DG3_MARK, DG4_MARK, DG5_MARK,
-	DB0_MARK, DB1_MARK, DB2_MARK, DB3_MARK, DB4_MARK, DB5_MARK,
-	ETH_MAGIC_MARK, ETH_LINK_MARK, ETH_TX_ER_MARK, ETH_TX_EN_MARK,
-	ETH_MDIO_MARK, ETH_RX_CLK_MARK, ETH_MDC_MARK, ETH_COL_MARK,
-	ETH_TX_CLK_MARK, ETH_CRS_MARK, ETH_RX_DV_MARK, ETH_RX_ER_MARK,
-	ETH_TXD3_MARK, ETH_TXD2_MARK, ETH_TXD1_MARK, ETH_TXD0_MARK,
-	ETH_RXD3_MARK, ETH_RXD2_MARK, ETH_RXD1_MARK, ETH_RXD0_MARK,
-	HSPI_CLK_MARK, HSPI_CS_MARK, HSPI_RX_MARK, HSPI_TX_MARK,
-	SCIF0_CTS_MARK, SCIF0_RTS_MARK,
-	SCIF0_SCK_MARK, SCIF0_RXD_MARK, SCIF0_TXD_MARK,
-	SCIF1_SCK_MARK, SCIF1_RXD_MARK, SCIF1_TXD_MARK,
-	SCIF3_SCK_MARK, SCIF3_RXD_MARK, SCIF3_TXD_MARK,
-	SCIF4_SCK_MARK, SCIF4_RXD_MARK, SCIF4_TXD_MARK,
-	SCIF5_SCK_MARK, SCIF5_RXD_MARK, SCIF5_TXD_MARK,
-	BREQ_MARK, IOIS16_MARK, CE2B_MARK, CE2A_MARK, BACK_MARK,
-	FALE_MARK, FRB_MARK, FSTATUS_MARK,
-	FSE_MARK, FCLE_MARK,
-	DACK0_MARK, DACK1_MARK, DACK2_MARK, DACK3_MARK,
-	DREQ0_MARK, DREQ1_MARK, DREQ2_MARK, DREQ3_MARK,
-	DRAK0_MARK, DRAK1_MARK, DRAK2_MARK, DRAK3_MARK,
-	USB_OVC1_MARK, USB_OVC0_MARK,
-	USB_PENC1_MARK, USB_PENC0_MARK,
-	HAC_RES_MARK,
-	HAC1_SDOUT_MARK, HAC1_SDIN_MARK, HAC1_SYNC_MARK, HAC1_BITCLK_MARK,
-	HAC0_SDOUT_MARK, HAC0_SDIN_MARK, HAC0_SYNC_MARK, HAC0_BITCLK_MARK,
-	SSI0_SDATA_MARK, SSI0_SCK_MARK, SSI0_WS_MARK, SSI0_CLK_MARK,
-	SSI1_SDATA_MARK, SSI1_SCK_MARK, SSI1_WS_MARK, SSI1_CLK_MARK,
-	SSI2_SDATA_MARK, SSI2_SCK_MARK, SSI2_WS_MARK,
-	SSI3_SDATA_MARK, SSI3_SCK_MARK, SSI3_WS_MARK,
-	SDIF1CMD_MARK, SDIF1CD_MARK, SDIF1WP_MARK, SDIF1CLK_MARK,
-	SDIF1D3_MARK, SDIF1D2_MARK, SDIF1D1_MARK, SDIF1D0_MARK,
-	SDIF0CMD_MARK, SDIF0CD_MARK, SDIF0WP_MARK, SDIF0CLK_MARK,
-	SDIF0D3_MARK, SDIF0D2_MARK, SDIF0D1_MARK, SDIF0D0_MARK,
-	TCLK_MARK,
-	IRL7_MARK, IRL6_MARK, IRL5_MARK, IRL4_MARK,
-	PINMUX_MARK_END,
-};
-
-static const u16 pinmux_data[] = {
-	/* PA GPIO */
-	PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT),
-	PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT),
-	PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT),
-	PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT),
-	PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT),
-	PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT),
-	PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT),
-	PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT),
-
-	/* PB GPIO */
-	PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT),
-	PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT),
-	PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT),
-	PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT),
-	PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT),
-	PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT),
-	PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT),
-	PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT),
-
-	/* PC GPIO */
-	PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT),
-	PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT),
-	PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT),
-	PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT),
-	PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT),
-	PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT),
-	PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT),
-	PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT),
-
-	/* PD GPIO */
-	PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT),
-	PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT),
-	PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT),
-	PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT),
-	PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT),
-	PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT),
-	PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT),
-	PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT),
-
-	/* PE GPIO */
-	PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT),
-	PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT),
-
-	/* PF GPIO */
-	PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT),
-	PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT),
-	PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT),
-	PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT),
-	PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT),
-	PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT),
-	PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT),
-	PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT),
-
-	/* PG GPIO */
-	PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT),
-	PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT),
-	PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT),
-
-	/* PH GPIO */
-	PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT),
-	PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT),
-	PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT),
-	PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT),
-	PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT),
-	PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT),
-	PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT),
-	PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT),
-
-	/* PJ GPIO */
-	PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT),
-	PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT),
-	PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT),
-	PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT),
-	PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT),
-	PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT),
-	PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT),
-
-	/* PA FN */
-	PINMUX_DATA(CDE_MARK,		P1MSEL2_0, PA7_FN),
-	PINMUX_DATA(DISP_MARK,		P1MSEL2_0, PA6_FN),
-	PINMUX_DATA(DR5_MARK,		P1MSEL2_0, PA5_FN),
-	PINMUX_DATA(DR4_MARK,		P1MSEL2_0, PA4_FN),
-	PINMUX_DATA(DR3_MARK,		P1MSEL2_0, PA3_FN),
-	PINMUX_DATA(DR2_MARK,		P1MSEL2_0, PA2_FN),
-	PINMUX_DATA(DR1_MARK,		P1MSEL2_0, PA1_FN),
-	PINMUX_DATA(DR0_MARK,		P1MSEL2_0, PA0_FN),
-	PINMUX_DATA(ETH_MAGIC_MARK,	P1MSEL2_1, PA7_FN),
-	PINMUX_DATA(ETH_LINK_MARK,	P1MSEL2_1, PA6_FN),
-	PINMUX_DATA(ETH_TX_ER_MARK,	P1MSEL2_1, PA5_FN),
-	PINMUX_DATA(ETH_TX_EN_MARK,	P1MSEL2_1, PA4_FN),
-	PINMUX_DATA(ETH_TXD3_MARK,	P1MSEL2_1, PA3_FN),
-	PINMUX_DATA(ETH_TXD2_MARK,	P1MSEL2_1, PA2_FN),
-	PINMUX_DATA(ETH_TXD1_MARK,	P1MSEL2_1, PA1_FN),
-	PINMUX_DATA(ETH_TXD0_MARK,	P1MSEL2_1, PA0_FN),
-
-	/* PB FN */
-	PINMUX_DATA(VSYNC_MARK,		P1MSEL3_0, PB7_FN),
-	PINMUX_DATA(ODDF_MARK,		P1MSEL3_0, PB6_FN),
-	PINMUX_DATA(DG5_MARK,		P1MSEL2_0, PB5_FN),
-	PINMUX_DATA(DG4_MARK,		P1MSEL2_0, PB4_FN),
-	PINMUX_DATA(DG3_MARK,		P1MSEL2_0, PB3_FN),
-	PINMUX_DATA(DG2_MARK,		P1MSEL2_0, PB2_FN),
-	PINMUX_DATA(DG1_MARK,		P1MSEL2_0, PB1_FN),
-	PINMUX_DATA(DG0_MARK,		P1MSEL2_0, PB0_FN),
-	PINMUX_DATA(HSPI_CLK_MARK,	P1MSEL3_1, PB7_FN),
-	PINMUX_DATA(HSPI_CS_MARK,	P1MSEL3_1, PB6_FN),
-	PINMUX_DATA(ETH_MDIO_MARK,	P1MSEL2_1, PB5_FN),
-	PINMUX_DATA(ETH_RX_CLK_MARK,	P1MSEL2_1, PB4_FN),
-	PINMUX_DATA(ETH_MDC_MARK,	P1MSEL2_1, PB3_FN),
-	PINMUX_DATA(ETH_COL_MARK,	P1MSEL2_1, PB2_FN),
-	PINMUX_DATA(ETH_TX_CLK_MARK,	P1MSEL2_1, PB1_FN),
-	PINMUX_DATA(ETH_CRS_MARK,	P1MSEL2_1, PB0_FN),
-
-	/* PC FN */
-	PINMUX_DATA(DCLKIN_MARK,	P1MSEL3_0, PC7_FN),
-	PINMUX_DATA(HSYNC_MARK,		P1MSEL3_0, PC6_FN),
-	PINMUX_DATA(DB5_MARK,		P1MSEL2_0, PC5_FN),
-	PINMUX_DATA(DB4_MARK,		P1MSEL2_0, PC4_FN),
-	PINMUX_DATA(DB3_MARK,		P1MSEL2_0, PC3_FN),
-	PINMUX_DATA(DB2_MARK,		P1MSEL2_0, PC2_FN),
-	PINMUX_DATA(DB1_MARK,		P1MSEL2_0, PC1_FN),
-	PINMUX_DATA(DB0_MARK,		P1MSEL2_0, PC0_FN),
-
-	PINMUX_DATA(HSPI_RX_MARK,	P1MSEL3_1, PC7_FN),
-	PINMUX_DATA(HSPI_TX_MARK,	P1MSEL3_1, PC6_FN),
-	PINMUX_DATA(ETH_RXD3_MARK,	P1MSEL2_1, PC5_FN),
-	PINMUX_DATA(ETH_RXD2_MARK,	P1MSEL2_1, PC4_FN),
-	PINMUX_DATA(ETH_RXD1_MARK,	P1MSEL2_1, PC3_FN),
-	PINMUX_DATA(ETH_RXD0_MARK,	P1MSEL2_1, PC2_FN),
-	PINMUX_DATA(ETH_RX_DV_MARK,	P1MSEL2_1, PC1_FN),
-	PINMUX_DATA(ETH_RX_ER_MARK,	P1MSEL2_1, PC0_FN),
-
-	/* PD FN */
-	PINMUX_DATA(DCLKOUT_MARK,	PD7_FN),
-	PINMUX_DATA(SCIF1_SCK_MARK,	PD6_FN),
-	PINMUX_DATA(SCIF1_RXD_MARK,	PD5_FN),
-	PINMUX_DATA(SCIF1_TXD_MARK,	PD4_FN),
-	PINMUX_DATA(DACK1_MARK,		P1MSEL13_1, P1MSEL12_0, PD3_FN),
-	PINMUX_DATA(BACK_MARK,		P1MSEL13_0, P1MSEL12_1, PD3_FN),
-	PINMUX_DATA(FALE_MARK,		P1MSEL13_0, P1MSEL12_0, PD3_FN),
-	PINMUX_DATA(DACK0_MARK,		P1MSEL14_1, PD2_FN),
-	PINMUX_DATA(FCLE_MARK,		P1MSEL14_0, PD2_FN),
-	PINMUX_DATA(DREQ1_MARK,		P1MSEL10_0, P1MSEL9_1, PD1_FN),
-	PINMUX_DATA(BREQ_MARK,		P1MSEL10_1, P1MSEL9_0, PD1_FN),
-	PINMUX_DATA(USB_OVC1_MARK,	P1MSEL10_0, P1MSEL9_0, PD1_FN),
-	PINMUX_DATA(DREQ0_MARK,		P1MSEL11_1, PD0_FN),
-	PINMUX_DATA(USB_OVC0_MARK,	P1MSEL11_0, PD0_FN),
-
-	/* PE FN */
-	PINMUX_DATA(USB_PENC1_MARK,	PE7_FN),
-	PINMUX_DATA(USB_PENC0_MARK,	PE6_FN),
-
-	/* PF FN */
-	PINMUX_DATA(HAC1_SDOUT_MARK,	P2MSEL15_0, P2MSEL14_0, PF7_FN),
-	PINMUX_DATA(HAC1_SDIN_MARK,	P2MSEL15_0, P2MSEL14_0, PF6_FN),
-	PINMUX_DATA(HAC1_SYNC_MARK,	P2MSEL15_0, P2MSEL14_0, PF5_FN),
-	PINMUX_DATA(HAC1_BITCLK_MARK,	P2MSEL15_0, P2MSEL14_0, PF4_FN),
-	PINMUX_DATA(HAC0_SDOUT_MARK,	P2MSEL13_0, P2MSEL12_0, PF3_FN),
-	PINMUX_DATA(HAC0_SDIN_MARK,	P2MSEL13_0, P2MSEL12_0, PF2_FN),
-	PINMUX_DATA(HAC0_SYNC_MARK,	P2MSEL13_0, P2MSEL12_0, PF1_FN),
-	PINMUX_DATA(HAC0_BITCLK_MARK,	P2MSEL13_0, P2MSEL12_0, PF0_FN),
-	PINMUX_DATA(SSI1_SDATA_MARK,	P2MSEL15_0, P2MSEL14_1, PF7_FN),
-	PINMUX_DATA(SSI1_SCK_MARK,	P2MSEL15_0, P2MSEL14_1, PF6_FN),
-	PINMUX_DATA(SSI1_WS_MARK,	P2MSEL15_0, P2MSEL14_1, PF5_FN),
-	PINMUX_DATA(SSI1_CLK_MARK,	P2MSEL15_0, P2MSEL14_1, PF4_FN),
-	PINMUX_DATA(SSI0_SDATA_MARK,	P2MSEL13_0, P2MSEL12_1, PF3_FN),
-	PINMUX_DATA(SSI0_SCK_MARK,	P2MSEL13_0, P2MSEL12_1, PF2_FN),
-	PINMUX_DATA(SSI0_WS_MARK,	P2MSEL13_0, P2MSEL12_1, PF1_FN),
-	PINMUX_DATA(SSI0_CLK_MARK,	P2MSEL13_0, P2MSEL12_1, PF0_FN),
-	PINMUX_DATA(SDIF1CMD_MARK,	P2MSEL15_1, P2MSEL14_0, PF7_FN),
-	PINMUX_DATA(SDIF1CD_MARK,	P2MSEL15_1, P2MSEL14_0, PF6_FN),
-	PINMUX_DATA(SDIF1WP_MARK,	P2MSEL15_1, P2MSEL14_0, PF5_FN),
-	PINMUX_DATA(SDIF1CLK_MARK,	P2MSEL15_1, P2MSEL14_0, PF4_FN),
-	PINMUX_DATA(SDIF1D3_MARK,	P2MSEL13_1, P2MSEL12_0, PF3_FN),
-	PINMUX_DATA(SDIF1D2_MARK,	P2MSEL13_1, P2MSEL12_0, PF2_FN),
-	PINMUX_DATA(SDIF1D1_MARK,	P2MSEL13_1, P2MSEL12_0, PF1_FN),
-	PINMUX_DATA(SDIF1D0_MARK,	P2MSEL13_1, P2MSEL12_0, PF0_FN),
-
-	/* PG FN */
-	PINMUX_DATA(SCIF3_SCK_MARK,	P1MSEL8_0, PG7_FN),
-	PINMUX_DATA(SSI2_SDATA_MARK,	P1MSEL8_1, PG7_FN),
-	PINMUX_DATA(SCIF3_RXD_MARK,	P1MSEL7_0, P1MSEL6_0, PG6_FN),
-	PINMUX_DATA(SSI2_SCK_MARK,	P1MSEL7_1, P1MSEL6_0, PG6_FN),
-	PINMUX_DATA(TCLK_MARK,		P1MSEL7_0, P1MSEL6_1, PG6_FN),
-	PINMUX_DATA(SCIF3_TXD_MARK,	P1MSEL5_0, P1MSEL4_0, PG5_FN),
-	PINMUX_DATA(SSI2_WS_MARK,	P1MSEL5_1, P1MSEL4_0, PG5_FN),
-	PINMUX_DATA(HAC_RES_MARK,	P1MSEL5_0, P1MSEL4_1, PG5_FN),
-
-	/* PH FN */
-	PINMUX_DATA(DACK3_MARK,		P2MSEL4_0, PH7_FN),
-	PINMUX_DATA(SDIF0CMD_MARK,	P2MSEL4_1, PH7_FN),
-	PINMUX_DATA(DACK2_MARK,		P2MSEL4_0, PH6_FN),
-	PINMUX_DATA(SDIF0CD_MARK,	P2MSEL4_1, PH6_FN),
-	PINMUX_DATA(DREQ3_MARK,		P2MSEL4_0, PH5_FN),
-	PINMUX_DATA(SDIF0WP_MARK,	P2MSEL4_1, PH5_FN),
-	PINMUX_DATA(DREQ2_MARK,		P2MSEL3_0, P2MSEL2_1, PH4_FN),
-	PINMUX_DATA(SDIF0CLK_MARK,	P2MSEL3_1, P2MSEL2_0, PH4_FN),
-	PINMUX_DATA(SCIF0_CTS_MARK,	P2MSEL3_0, P2MSEL2_0, PH4_FN),
-	PINMUX_DATA(SDIF0D3_MARK,	P2MSEL1_1, P2MSEL0_0, PH3_FN),
-	PINMUX_DATA(SCIF0_RTS_MARK,	P2MSEL1_0, P2MSEL0_0, PH3_FN),
-	PINMUX_DATA(IRL7_MARK,		P2MSEL1_0, P2MSEL0_1, PH3_FN),
-	PINMUX_DATA(SDIF0D2_MARK,	P2MSEL1_1, P2MSEL0_0, PH2_FN),
-	PINMUX_DATA(SCIF0_SCK_MARK,	P2MSEL1_0, P2MSEL0_0, PH2_FN),
-	PINMUX_DATA(IRL6_MARK,		P2MSEL1_0, P2MSEL0_1, PH2_FN),
-	PINMUX_DATA(SDIF0D1_MARK,	P2MSEL1_1, P2MSEL0_0, PH1_FN),
-	PINMUX_DATA(SCIF0_RXD_MARK,	P2MSEL1_0, P2MSEL0_0, PH1_FN),
-	PINMUX_DATA(IRL5_MARK,		P2MSEL1_0, P2MSEL0_1, PH1_FN),
-	PINMUX_DATA(SDIF0D0_MARK,	P2MSEL1_1, P2MSEL0_0, PH0_FN),
-	PINMUX_DATA(SCIF0_TXD_MARK,	P2MSEL1_0, P2MSEL0_0, PH0_FN),
-	PINMUX_DATA(IRL4_MARK,		P2MSEL1_0, P2MSEL0_1, PH0_FN),
-
-	/* PJ FN */
-	PINMUX_DATA(SCIF5_SCK_MARK,	P2MSEL11_1, PJ7_FN),
-	PINMUX_DATA(FRB_MARK,		P2MSEL11_0, PJ7_FN),
-	PINMUX_DATA(SCIF5_RXD_MARK,	P2MSEL10_0, PJ6_FN),
-	PINMUX_DATA(IOIS16_MARK,	P2MSEL10_1, PJ6_FN),
-	PINMUX_DATA(SCIF5_TXD_MARK,	P2MSEL10_0, PJ5_FN),
-	PINMUX_DATA(CE2B_MARK,		P2MSEL10_1, PJ5_FN),
-	PINMUX_DATA(DRAK3_MARK,		P2MSEL7_0, PJ4_FN),
-	PINMUX_DATA(CE2A_MARK,		P2MSEL7_1, PJ4_FN),
-	PINMUX_DATA(SCIF4_SCK_MARK,	P2MSEL9_0, P2MSEL8_0, PJ3_FN),
-	PINMUX_DATA(DRAK2_MARK,		P2MSEL9_0, P2MSEL8_1, PJ3_FN),
-	PINMUX_DATA(SSI3_WS_MARK,	P2MSEL9_1, P2MSEL8_0, PJ3_FN),
-	PINMUX_DATA(SCIF4_RXD_MARK,	P2MSEL6_1, P2MSEL5_0, PJ2_FN),
-	PINMUX_DATA(DRAK1_MARK,		P2MSEL6_0, P2MSEL5_1, PJ2_FN),
-	PINMUX_DATA(FSTATUS_MARK,	P2MSEL6_0, P2MSEL5_0, PJ2_FN),
-	PINMUX_DATA(SSI3_SDATA_MARK,	P2MSEL6_1, P2MSEL5_1, PJ2_FN),
-	PINMUX_DATA(SCIF4_TXD_MARK,	P2MSEL6_1, P2MSEL5_0, PJ1_FN),
-	PINMUX_DATA(DRAK0_MARK,		P2MSEL6_0, P2MSEL5_1, PJ1_FN),
-	PINMUX_DATA(FSE_MARK,		P2MSEL6_0, P2MSEL5_0, PJ1_FN),
-	PINMUX_DATA(SSI3_SCK_MARK,	P2MSEL6_1, P2MSEL5_1, PJ1_FN),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	/* PA */
-	PINMUX_GPIO(PA7),
-	PINMUX_GPIO(PA6),
-	PINMUX_GPIO(PA5),
-	PINMUX_GPIO(PA4),
-	PINMUX_GPIO(PA3),
-	PINMUX_GPIO(PA2),
-	PINMUX_GPIO(PA1),
-	PINMUX_GPIO(PA0),
-
-	/* PB */
-	PINMUX_GPIO(PB7),
-	PINMUX_GPIO(PB6),
-	PINMUX_GPIO(PB5),
-	PINMUX_GPIO(PB4),
-	PINMUX_GPIO(PB3),
-	PINMUX_GPIO(PB2),
-	PINMUX_GPIO(PB1),
-	PINMUX_GPIO(PB0),
-
-	/* PC */
-	PINMUX_GPIO(PC7),
-	PINMUX_GPIO(PC6),
-	PINMUX_GPIO(PC5),
-	PINMUX_GPIO(PC4),
-	PINMUX_GPIO(PC3),
-	PINMUX_GPIO(PC2),
-	PINMUX_GPIO(PC1),
-	PINMUX_GPIO(PC0),
-
-	/* PD */
-	PINMUX_GPIO(PD7),
-	PINMUX_GPIO(PD6),
-	PINMUX_GPIO(PD5),
-	PINMUX_GPIO(PD4),
-	PINMUX_GPIO(PD3),
-	PINMUX_GPIO(PD2),
-	PINMUX_GPIO(PD1),
-	PINMUX_GPIO(PD0),
-
-	/* PE */
-	PINMUX_GPIO(PE7),
-	PINMUX_GPIO(PE6),
-
-	/* PF */
-	PINMUX_GPIO(PF7),
-	PINMUX_GPIO(PF6),
-	PINMUX_GPIO(PF5),
-	PINMUX_GPIO(PF4),
-	PINMUX_GPIO(PF3),
-	PINMUX_GPIO(PF2),
-	PINMUX_GPIO(PF1),
-	PINMUX_GPIO(PF0),
-
-	/* PG */
-	PINMUX_GPIO(PG7),
-	PINMUX_GPIO(PG6),
-	PINMUX_GPIO(PG5),
-
-	/* PH */
-	PINMUX_GPIO(PH7),
-	PINMUX_GPIO(PH6),
-	PINMUX_GPIO(PH5),
-	PINMUX_GPIO(PH4),
-	PINMUX_GPIO(PH3),
-	PINMUX_GPIO(PH2),
-	PINMUX_GPIO(PH1),
-	PINMUX_GPIO(PH0),
-
-	/* PJ */
-	PINMUX_GPIO(PJ7),
-	PINMUX_GPIO(PJ6),
-	PINMUX_GPIO(PJ5),
-	PINMUX_GPIO(PJ4),
-	PINMUX_GPIO(PJ3),
-	PINMUX_GPIO(PJ2),
-	PINMUX_GPIO(PJ1),
-};
-
-#define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-	/* FN */
-	GPIO_FN(CDE),
-	GPIO_FN(ETH_MAGIC),
-	GPIO_FN(DISP),
-	GPIO_FN(ETH_LINK),
-	GPIO_FN(DR5),
-	GPIO_FN(ETH_TX_ER),
-	GPIO_FN(DR4),
-	GPIO_FN(ETH_TX_EN),
-	GPIO_FN(DR3),
-	GPIO_FN(ETH_TXD3),
-	GPIO_FN(DR2),
-	GPIO_FN(ETH_TXD2),
-	GPIO_FN(DR1),
-	GPIO_FN(ETH_TXD1),
-	GPIO_FN(DR0),
-	GPIO_FN(ETH_TXD0),
-	GPIO_FN(VSYNC),
-	GPIO_FN(HSPI_CLK),
-	GPIO_FN(ODDF),
-	GPIO_FN(HSPI_CS),
-	GPIO_FN(DG5),
-	GPIO_FN(ETH_MDIO),
-	GPIO_FN(DG4),
-	GPIO_FN(ETH_RX_CLK),
-	GPIO_FN(DG3),
-	GPIO_FN(ETH_MDC),
-	GPIO_FN(DG2),
-	GPIO_FN(ETH_COL),
-	GPIO_FN(DG1),
-	GPIO_FN(ETH_TX_CLK),
-	GPIO_FN(DG0),
-	GPIO_FN(ETH_CRS),
-	GPIO_FN(DCLKIN),
-	GPIO_FN(HSPI_RX),
-	GPIO_FN(HSYNC),
-	GPIO_FN(HSPI_TX),
-	GPIO_FN(DB5),
-	GPIO_FN(ETH_RXD3),
-	GPIO_FN(DB4),
-	GPIO_FN(ETH_RXD2),
-	GPIO_FN(DB3),
-	GPIO_FN(ETH_RXD1),
-	GPIO_FN(DB2),
-	GPIO_FN(ETH_RXD0),
-	GPIO_FN(DB1),
-	GPIO_FN(ETH_RX_DV),
-	GPIO_FN(DB0),
-	GPIO_FN(ETH_RX_ER),
-	GPIO_FN(DCLKOUT),
-	GPIO_FN(SCIF1_SCK),
-	GPIO_FN(SCIF1_RXD),
-	GPIO_FN(SCIF1_TXD),
-	GPIO_FN(DACK1),
-	GPIO_FN(BACK),
-	GPIO_FN(FALE),
-	GPIO_FN(DACK0),
-	GPIO_FN(FCLE),
-	GPIO_FN(DREQ1),
-	GPIO_FN(BREQ),
-	GPIO_FN(USB_OVC1),
-	GPIO_FN(DREQ0),
-	GPIO_FN(USB_OVC0),
-	GPIO_FN(USB_PENC1),
-	GPIO_FN(USB_PENC0),
-	GPIO_FN(HAC1_SDOUT),
-	GPIO_FN(SSI1_SDATA),
-	GPIO_FN(SDIF1CMD),
-	GPIO_FN(HAC1_SDIN),
-	GPIO_FN(SSI1_SCK),
-	GPIO_FN(SDIF1CD),
-	GPIO_FN(HAC1_SYNC),
-	GPIO_FN(SSI1_WS),
-	GPIO_FN(SDIF1WP),
-	GPIO_FN(HAC1_BITCLK),
-	GPIO_FN(SSI1_CLK),
-	GPIO_FN(SDIF1CLK),
-	GPIO_FN(HAC0_SDOUT),
-	GPIO_FN(SSI0_SDATA),
-	GPIO_FN(SDIF1D3),
-	GPIO_FN(HAC0_SDIN),
-	GPIO_FN(SSI0_SCK),
-	GPIO_FN(SDIF1D2),
-	GPIO_FN(HAC0_SYNC),
-	GPIO_FN(SSI0_WS),
-	GPIO_FN(SDIF1D1),
-	GPIO_FN(HAC0_BITCLK),
-	GPIO_FN(SSI0_CLK),
-	GPIO_FN(SDIF1D0),
-	GPIO_FN(SCIF3_SCK),
-	GPIO_FN(SSI2_SDATA),
-	GPIO_FN(SCIF3_RXD),
-	GPIO_FN(TCLK),
-	GPIO_FN(SSI2_SCK),
-	GPIO_FN(SCIF3_TXD),
-	GPIO_FN(HAC_RES),
-	GPIO_FN(SSI2_WS),
-	GPIO_FN(DACK3),
-	GPIO_FN(SDIF0CMD),
-	GPIO_FN(DACK2),
-	GPIO_FN(SDIF0CD),
-	GPIO_FN(DREQ3),
-	GPIO_FN(SDIF0WP),
-	GPIO_FN(SCIF0_CTS),
-	GPIO_FN(DREQ2),
-	GPIO_FN(SDIF0CLK),
-	GPIO_FN(SCIF0_RTS),
-	GPIO_FN(IRL7),
-	GPIO_FN(SDIF0D3),
-	GPIO_FN(SCIF0_SCK),
-	GPIO_FN(IRL6),
-	GPIO_FN(SDIF0D2),
-	GPIO_FN(SCIF0_RXD),
-	GPIO_FN(IRL5),
-	GPIO_FN(SDIF0D1),
-	GPIO_FN(SCIF0_TXD),
-	GPIO_FN(IRL4),
-	GPIO_FN(SDIF0D0),
-	GPIO_FN(SCIF5_SCK),
-	GPIO_FN(FRB),
-	GPIO_FN(SCIF5_RXD),
-	GPIO_FN(IOIS16),
-	GPIO_FN(SCIF5_TXD),
-	GPIO_FN(CE2B),
-	GPIO_FN(DRAK3),
-	GPIO_FN(CE2A),
-	GPIO_FN(SCIF4_SCK),
-	GPIO_FN(DRAK2),
-	GPIO_FN(SSI3_WS),
-	GPIO_FN(SCIF4_RXD),
-	GPIO_FN(DRAK1),
-	GPIO_FN(SSI3_SDATA),
-	GPIO_FN(FSTATUS),
-	GPIO_FN(SCIF4_TXD),
-	GPIO_FN(DRAK0),
-	GPIO_FN(SSI3_SCK),
-	GPIO_FN(FSE),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	{ PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2, GROUP(
-		PA7_FN, PA7_OUT, PA7_IN, 0,
-		PA6_FN, PA6_OUT, PA6_IN, 0,
-		PA5_FN, PA5_OUT, PA5_IN, 0,
-		PA4_FN, PA4_OUT, PA4_IN, 0,
-		PA3_FN, PA3_OUT, PA3_IN, 0,
-		PA2_FN, PA2_OUT, PA2_IN, 0,
-		PA1_FN, PA1_OUT, PA1_IN, 0,
-		PA0_FN, PA0_OUT, PA0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2, GROUP(
-		PB7_FN, PB7_OUT, PB7_IN, 0,
-		PB6_FN, PB6_OUT, PB6_IN, 0,
-		PB5_FN, PB5_OUT, PB5_IN, 0,
-		PB4_FN, PB4_OUT, PB4_IN, 0,
-		PB3_FN, PB3_OUT, PB3_IN, 0,
-		PB2_FN, PB2_OUT, PB2_IN, 0,
-		PB1_FN, PB1_OUT, PB1_IN, 0,
-		PB0_FN, PB0_OUT, PB0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2, GROUP(
-		PC7_FN, PC7_OUT, PC7_IN, 0,
-		PC6_FN, PC6_OUT, PC6_IN, 0,
-		PC5_FN, PC5_OUT, PC5_IN, 0,
-		PC4_FN, PC4_OUT, PC4_IN, 0,
-		PC3_FN, PC3_OUT, PC3_IN, 0,
-		PC2_FN, PC2_OUT, PC2_IN, 0,
-		PC1_FN, PC1_OUT, PC1_IN, 0,
-		PC0_FN, PC0_OUT, PC0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2, GROUP(
-		PD7_FN, PD7_OUT, PD7_IN, 0,
-		PD6_FN, PD6_OUT, PD6_IN, 0,
-		PD5_FN, PD5_OUT, PD5_IN, 0,
-		PD4_FN, PD4_OUT, PD4_IN, 0,
-		PD3_FN, PD3_OUT, PD3_IN, 0,
-		PD2_FN, PD2_OUT, PD2_IN, 0,
-		PD1_FN, PD1_OUT, PD1_IN, 0,
-		PD0_FN, PD0_OUT, PD0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2, GROUP(
-		PE7_FN, PE7_OUT, PE7_IN, 0,
-		PE6_FN, PE6_OUT, PE6_IN, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2, GROUP(
-		PF7_FN, PF7_OUT, PF7_IN, 0,
-		PF6_FN, PF6_OUT, PF6_IN, 0,
-		PF5_FN, PF5_OUT, PF5_IN, 0,
-		PF4_FN, PF4_OUT, PF4_IN, 0,
-		PF3_FN, PF3_OUT, PF3_IN, 0,
-		PF2_FN, PF2_OUT, PF2_IN, 0,
-		PF1_FN, PF1_OUT, PF1_IN, 0,
-		PF0_FN, PF0_OUT, PF0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2, GROUP(
-		PG7_FN, PG7_OUT, PG7_IN, 0,
-		PG6_FN, PG6_OUT, PG6_IN, 0,
-		PG5_FN, PG5_OUT, PG5_IN, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2, GROUP(
-		PH7_FN, PH7_OUT, PH7_IN, 0,
-		PH6_FN, PH6_OUT, PH6_IN, 0,
-		PH5_FN, PH5_OUT, PH5_IN, 0,
-		PH4_FN, PH4_OUT, PH4_IN, 0,
-		PH3_FN, PH3_OUT, PH3_IN, 0,
-		PH2_FN, PH2_OUT, PH2_IN, 0,
-		PH1_FN, PH1_OUT, PH1_IN, 0,
-		PH0_FN, PH0_OUT, PH0_IN, 0 ))
-	},
-	{ PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2, GROUP(
-		PJ7_FN, PJ7_OUT, PJ7_IN, 0,
-		PJ6_FN, PJ6_OUT, PJ6_IN, 0,
-		PJ5_FN, PJ5_OUT, PJ5_IN, 0,
-		PJ4_FN, PJ4_OUT, PJ4_IN, 0,
-		PJ3_FN, PJ3_OUT, PJ3_IN, 0,
-		PJ2_FN, PJ2_OUT, PJ2_IN, 0,
-		PJ1_FN, PJ1_OUT, PJ1_IN, 0,
-		0, 0, 0, 0, ))
-	},
-	{ PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1, GROUP(
-		0, 0,
-		P1MSEL14_0, P1MSEL14_1,
-		P1MSEL13_0, P1MSEL13_1,
-		P1MSEL12_0, P1MSEL12_1,
-		P1MSEL11_0, P1MSEL11_1,
-		P1MSEL10_0, P1MSEL10_1,
-		P1MSEL9_0,  P1MSEL9_1,
-		P1MSEL8_0,  P1MSEL8_1,
-		P1MSEL7_0,  P1MSEL7_1,
-		P1MSEL6_0,  P1MSEL6_1,
-		P1MSEL5_0,  P1MSEL5_1,
-		P1MSEL4_0,  P1MSEL4_1,
-		P1MSEL3_0,  P1MSEL3_1,
-		P1MSEL2_0,  P1MSEL2_1,
-		P1MSEL1_0,  P1MSEL1_1,
-		P1MSEL0_0,  P1MSEL0_1 ))
-	},
-	{ PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1, GROUP(
-		P2MSEL15_0, P2MSEL15_1,
-		P2MSEL14_0, P2MSEL14_1,
-		P2MSEL13_0, P2MSEL13_1,
-		P2MSEL12_0, P2MSEL12_1,
-		P2MSEL11_0, P2MSEL11_1,
-		P2MSEL10_0, P2MSEL10_1,
-		P2MSEL9_0,  P2MSEL9_1,
-		P2MSEL8_0,  P2MSEL8_1,
-		P2MSEL7_0,  P2MSEL7_1,
-		P2MSEL6_0,  P2MSEL6_1,
-		P2MSEL5_0,  P2MSEL5_1,
-		P2MSEL4_0,  P2MSEL4_1,
-		P2MSEL3_0,  P2MSEL3_1,
-		P2MSEL2_0,  P2MSEL2_1,
-		P2MSEL1_0,  P2MSEL1_1,
-		P2MSEL0_0,  P2MSEL0_1 ))
-	},
-	{}
-};
-
-static const struct pinmux_data_reg pinmux_data_regs[] = {
-	{ PINMUX_DATA_REG("PADR", 0xffcc0020, 8, GROUP(
-		PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
-		PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PBDR", 0xffcc0022, 8, GROUP(
-		PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
-		PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PCDR", 0xffcc0024, 8, GROUP(
-		PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
-		PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PDDR", 0xffcc0026, 8, GROUP(
-		PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
-		PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PEDR", 0xffcc0028, 8, GROUP(
-		PE7_DATA, PE6_DATA,
-		0, 0, 0, 0, 0, 0 ))
-	},
-	{ PINMUX_DATA_REG("PFDR", 0xffcc002a, 8, GROUP(
-		PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
-		PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PGDR", 0xffcc002c, 8, GROUP(
-		PG7_DATA, PG6_DATA, PG5_DATA, 0,
-		0, 0, 0, 0 ))
-	},
-	{ PINMUX_DATA_REG("PHDR", 0xffcc002e, 8, GROUP(
-		PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
-		PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA ))
-	},
-	{ PINMUX_DATA_REG("PJDR", 0xffcc0030, 8, GROUP(
-		PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
-		PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 ))
-	},
-	{ },
-};
-
-const struct sh_pfc_soc_info sh7786_pinmux_info = {
-	.name = "sh7786_pfc",
-	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.func_gpios = pinmux_func_gpios,
-	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
-	.cfg_regs = pinmux_config_regs,
-	.data_regs = pinmux_data_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c
deleted file mode 100644
index 22e812850964..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-shx3.c
+++ /dev/null
@@ -1,558 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * SH-X3 prototype CPU pinmux
- *
- * Copyright (C) 2010  Paul Mundt
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <cpu/shx3.h>
-
-#include "sh_pfc.h"
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	PINMUX_DATA_BEGIN,
-	PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
-	PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
-	PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
-	PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
-	PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
-	PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
-	PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
-	PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
-	PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
-	PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
-	PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
-	PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
-	PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
-	PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
-
-	PH5_DATA, PH4_DATA,
-	PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
-	PINMUX_DATA_END,
-
-	PINMUX_INPUT_BEGIN,
-	PA7_IN, PA6_IN, PA5_IN, PA4_IN,
-	PA3_IN, PA2_IN, PA1_IN, PA0_IN,
-	PB7_IN, PB6_IN, PB5_IN, PB4_IN,
-	PB3_IN, PB2_IN, PB1_IN, PB0_IN,
-	PC7_IN, PC6_IN, PC5_IN, PC4_IN,
-	PC3_IN, PC2_IN, PC1_IN, PC0_IN,
-	PD7_IN, PD6_IN, PD5_IN, PD4_IN,
-	PD3_IN, PD2_IN, PD1_IN, PD0_IN,
-	PE7_IN, PE6_IN, PE5_IN, PE4_IN,
-	PE3_IN, PE2_IN, PE1_IN, PE0_IN,
-	PF7_IN, PF6_IN, PF5_IN, PF4_IN,
-	PF3_IN, PF2_IN, PF1_IN, PF0_IN,
-	PG7_IN, PG6_IN, PG5_IN, PG4_IN,
-	PG3_IN, PG2_IN, PG1_IN, PG0_IN,
-
-	PH5_IN, PH4_IN,
-	PH3_IN, PH2_IN, PH1_IN, PH0_IN,
-	PINMUX_INPUT_END,
-
-	PINMUX_OUTPUT_BEGIN,
-	PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
-	PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
-	PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
-	PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
-	PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
-	PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
-	PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
-	PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
-	PE7_OUT, PE6_OUT, PE5_OUT, PE4_OUT,
-	PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
-	PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
-	PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
-	PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT,
-	PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT,
-
-	PH5_OUT, PH4_OUT,
-	PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
-	PINMUX_OUTPUT_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	PA7_FN, PA6_FN, PA5_FN, PA4_FN,
-	PA3_FN, PA2_FN, PA1_FN, PA0_FN,
-	PB7_FN, PB6_FN, PB5_FN, PB4_FN,
-	PB3_FN, PB2_FN, PB1_FN, PB0_FN,
-	PC7_FN, PC6_FN, PC5_FN, PC4_FN,
-	PC3_FN, PC2_FN, PC1_FN, PC0_FN,
-	PD7_FN, PD6_FN, PD5_FN, PD4_FN,
-	PD3_FN, PD2_FN, PD1_FN, PD0_FN,
-	PE7_FN, PE6_FN, PE5_FN, PE4_FN,
-	PE3_FN, PE2_FN, PE1_FN, PE0_FN,
-	PF7_FN, PF6_FN, PF5_FN, PF4_FN,
-	PF3_FN, PF2_FN, PF1_FN, PF0_FN,
-	PG7_FN, PG6_FN, PG5_FN, PG4_FN,
-	PG3_FN, PG2_FN, PG1_FN, PG0_FN,
-
-	PH5_FN, PH4_FN,
-	PH3_FN, PH2_FN, PH1_FN, PH0_FN,
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-
-	D31_MARK, D30_MARK, D29_MARK, D28_MARK, D27_MARK, D26_MARK,
-	D25_MARK, D24_MARK, D23_MARK, D22_MARK, D21_MARK, D20_MARK,
-	D19_MARK, D18_MARK, D17_MARK, D16_MARK,
-
-	BACK_MARK, BREQ_MARK,
-	WE3_MARK, WE2_MARK,
-	CS6_MARK, CS5_MARK, CS4_MARK,
-	CLKOUTENB_MARK,
-
-	DACK3_MARK, DACK2_MARK, DACK1_MARK, DACK0_MARK,
-	DREQ3_MARK, DREQ2_MARK, DREQ1_MARK, DREQ0_MARK,
-
-	IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK,
-
-	DRAK3_MARK, DRAK2_MARK, DRAK1_MARK, DRAK0_MARK,
-
-	SCK3_MARK, SCK2_MARK, SCK1_MARK, SCK0_MARK,
-	IRL3_MARK, IRL2_MARK, IRL1_MARK, IRL0_MARK,
-	TXD3_MARK, TXD2_MARK, TXD1_MARK, TXD0_MARK,
-	RXD3_MARK, RXD2_MARK, RXD1_MARK, RXD0_MARK,
-
-	CE2B_MARK, CE2A_MARK, IOIS16_MARK,
-	STATUS1_MARK, STATUS0_MARK,
-
-	IRQOUT_MARK,
-
-	PINMUX_MARK_END,
-};
-
-static const u16 pinmux_data[] = {
-	/* PA GPIO */
-	PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT),
-	PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT),
-	PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT),
-	PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT),
-	PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT),
-	PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT),
-	PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT),
-	PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT),
-
-	/* PB GPIO */
-	PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT),
-	PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT),
-	PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT),
-	PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT),
-	PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT),
-	PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT),
-	PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT),
-	PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT),
-
-	/* PC GPIO */
-	PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT),
-	PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT),
-	PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT),
-	PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT),
-	PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT),
-	PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT),
-	PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT),
-	PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT),
-
-	/* PD GPIO */
-	PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT),
-	PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT),
-	PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT),
-	PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT),
-	PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT),
-	PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT),
-	PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT),
-	PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT),
-
-	/* PE GPIO */
-	PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT),
-	PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT),
-	PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT),
-	PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT),
-	PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT),
-	PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT),
-	PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT),
-	PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT),
-
-	/* PF GPIO */
-	PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT),
-	PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT),
-	PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT),
-	PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT),
-	PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT),
-	PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT),
-	PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT),
-	PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT),
-
-	/* PG GPIO */
-	PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT),
-	PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT),
-	PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT),
-	PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT),
-	PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT),
-	PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT),
-	PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT),
-	PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT),
-
-	/* PH GPIO */
-	PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT),
-	PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT),
-	PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT),
-	PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT),
-	PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT),
-	PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT),
-
-	/* PA FN */
-	PINMUX_DATA(D31_MARK, PA7_FN),
-	PINMUX_DATA(D30_MARK, PA6_FN),
-	PINMUX_DATA(D29_MARK, PA5_FN),
-	PINMUX_DATA(D28_MARK, PA4_FN),
-	PINMUX_DATA(D27_MARK, PA3_FN),
-	PINMUX_DATA(D26_MARK, PA2_FN),
-	PINMUX_DATA(D25_MARK, PA1_FN),
-	PINMUX_DATA(D24_MARK, PA0_FN),
-
-	/* PB FN */
-	PINMUX_DATA(D23_MARK, PB7_FN),
-	PINMUX_DATA(D22_MARK, PB6_FN),
-	PINMUX_DATA(D21_MARK, PB5_FN),
-	PINMUX_DATA(D20_MARK, PB4_FN),
-	PINMUX_DATA(D19_MARK, PB3_FN),
-	PINMUX_DATA(D18_MARK, PB2_FN),
-	PINMUX_DATA(D17_MARK, PB1_FN),
-	PINMUX_DATA(D16_MARK, PB0_FN),
-
-	/* PC FN */
-	PINMUX_DATA(BACK_MARK,		PC7_FN),
-	PINMUX_DATA(BREQ_MARK,		PC6_FN),
-	PINMUX_DATA(WE3_MARK,		PC5_FN),
-	PINMUX_DATA(WE2_MARK,		PC4_FN),
-	PINMUX_DATA(CS6_MARK,		PC3_FN),
-	PINMUX_DATA(CS5_MARK,		PC2_FN),
-	PINMUX_DATA(CS4_MARK,		PC1_FN),
-	PINMUX_DATA(CLKOUTENB_MARK,	PC0_FN),
-
-	/* PD FN */
-	PINMUX_DATA(DACK3_MARK,	PD7_FN),
-	PINMUX_DATA(DACK2_MARK, PD6_FN),
-	PINMUX_DATA(DACK1_MARK, PD5_FN),
-	PINMUX_DATA(DACK0_MARK, PD4_FN),
-	PINMUX_DATA(DREQ3_MARK, PD3_FN),
-	PINMUX_DATA(DREQ2_MARK, PD2_FN),
-	PINMUX_DATA(DREQ1_MARK, PD1_FN),
-	PINMUX_DATA(DREQ0_MARK, PD0_FN),
-
-	/* PE FN */
-	PINMUX_DATA(IRQ3_MARK,	PE7_FN),
-	PINMUX_DATA(IRQ2_MARK,	PE6_FN),
-	PINMUX_DATA(IRQ1_MARK,	PE5_FN),
-	PINMUX_DATA(IRQ0_MARK,	PE4_FN),
-	PINMUX_DATA(DRAK3_MARK, PE3_FN),
-	PINMUX_DATA(DRAK2_MARK, PE2_FN),
-	PINMUX_DATA(DRAK1_MARK, PE1_FN),
-	PINMUX_DATA(DRAK0_MARK, PE0_FN),
-
-	/* PF FN */
-	PINMUX_DATA(SCK3_MARK, PF7_FN),
-	PINMUX_DATA(SCK2_MARK, PF6_FN),
-	PINMUX_DATA(SCK1_MARK, PF5_FN),
-	PINMUX_DATA(SCK0_MARK, PF4_FN),
-	PINMUX_DATA(IRL3_MARK, PF3_FN),
-	PINMUX_DATA(IRL2_MARK, PF2_FN),
-	PINMUX_DATA(IRL1_MARK, PF1_FN),
-	PINMUX_DATA(IRL0_MARK, PF0_FN),
-
-	/* PG FN */
-	PINMUX_DATA(TXD3_MARK, PG7_FN),
-	PINMUX_DATA(TXD2_MARK, PG6_FN),
-	PINMUX_DATA(TXD1_MARK, PG5_FN),
-	PINMUX_DATA(TXD0_MARK, PG4_FN),
-	PINMUX_DATA(RXD3_MARK, PG3_FN),
-	PINMUX_DATA(RXD2_MARK, PG2_FN),
-	PINMUX_DATA(RXD1_MARK, PG1_FN),
-	PINMUX_DATA(RXD0_MARK, PG0_FN),
-
-	/* PH FN */
-	PINMUX_DATA(CE2B_MARK,		PH5_FN),
-	PINMUX_DATA(CE2A_MARK,		PH4_FN),
-	PINMUX_DATA(IOIS16_MARK,	PH3_FN),
-	PINMUX_DATA(STATUS1_MARK,	PH2_FN),
-	PINMUX_DATA(STATUS0_MARK,	PH1_FN),
-	PINMUX_DATA(IRQOUT_MARK,	PH0_FN),
-};
-
-static const struct sh_pfc_pin pinmux_pins[] = {
-	/* PA */
-	PINMUX_GPIO(PA7),
-	PINMUX_GPIO(PA6),
-	PINMUX_GPIO(PA5),
-	PINMUX_GPIO(PA4),
-	PINMUX_GPIO(PA3),
-	PINMUX_GPIO(PA2),
-	PINMUX_GPIO(PA1),
-	PINMUX_GPIO(PA0),
-
-	/* PB */
-	PINMUX_GPIO(PB7),
-	PINMUX_GPIO(PB6),
-	PINMUX_GPIO(PB5),
-	PINMUX_GPIO(PB4),
-	PINMUX_GPIO(PB3),
-	PINMUX_GPIO(PB2),
-	PINMUX_GPIO(PB1),
-	PINMUX_GPIO(PB0),
-
-	/* PC */
-	PINMUX_GPIO(PC7),
-	PINMUX_GPIO(PC6),
-	PINMUX_GPIO(PC5),
-	PINMUX_GPIO(PC4),
-	PINMUX_GPIO(PC3),
-	PINMUX_GPIO(PC2),
-	PINMUX_GPIO(PC1),
-	PINMUX_GPIO(PC0),
-
-	/* PD */
-	PINMUX_GPIO(PD7),
-	PINMUX_GPIO(PD6),
-	PINMUX_GPIO(PD5),
-	PINMUX_GPIO(PD4),
-	PINMUX_GPIO(PD3),
-	PINMUX_GPIO(PD2),
-	PINMUX_GPIO(PD1),
-	PINMUX_GPIO(PD0),
-
-	/* PE */
-	PINMUX_GPIO(PE7),
-	PINMUX_GPIO(PE6),
-	PINMUX_GPIO(PE5),
-	PINMUX_GPIO(PE4),
-	PINMUX_GPIO(PE3),
-	PINMUX_GPIO(PE2),
-	PINMUX_GPIO(PE1),
-	PINMUX_GPIO(PE0),
-
-	/* PF */
-	PINMUX_GPIO(PF7),
-	PINMUX_GPIO(PF6),
-	PINMUX_GPIO(PF5),
-	PINMUX_GPIO(PF4),
-	PINMUX_GPIO(PF3),
-	PINMUX_GPIO(PF2),
-	PINMUX_GPIO(PF1),
-	PINMUX_GPIO(PF0),
-
-	/* PG */
-	PINMUX_GPIO(PG7),
-	PINMUX_GPIO(PG6),
-	PINMUX_GPIO(PG5),
-	PINMUX_GPIO(PG4),
-	PINMUX_GPIO(PG3),
-	PINMUX_GPIO(PG2),
-	PINMUX_GPIO(PG1),
-	PINMUX_GPIO(PG0),
-
-	/* PH */
-	PINMUX_GPIO(PH5),
-	PINMUX_GPIO(PH4),
-	PINMUX_GPIO(PH3),
-	PINMUX_GPIO(PH2),
-	PINMUX_GPIO(PH1),
-	PINMUX_GPIO(PH0),
-};
-
-#define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-	/* FN */
-	GPIO_FN(D31),
-	GPIO_FN(D30),
-	GPIO_FN(D29),
-	GPIO_FN(D28),
-	GPIO_FN(D27),
-	GPIO_FN(D26),
-	GPIO_FN(D25),
-	GPIO_FN(D24),
-	GPIO_FN(D23),
-	GPIO_FN(D22),
-	GPIO_FN(D21),
-	GPIO_FN(D20),
-	GPIO_FN(D19),
-	GPIO_FN(D18),
-	GPIO_FN(D17),
-	GPIO_FN(D16),
-	GPIO_FN(BACK),
-	GPIO_FN(BREQ),
-	GPIO_FN(WE3),
-	GPIO_FN(WE2),
-	GPIO_FN(CS6),
-	GPIO_FN(CS5),
-	GPIO_FN(CS4),
-	GPIO_FN(CLKOUTENB),
-	GPIO_FN(DACK3),
-	GPIO_FN(DACK2),
-	GPIO_FN(DACK1),
-	GPIO_FN(DACK0),
-	GPIO_FN(DREQ3),
-	GPIO_FN(DREQ2),
-	GPIO_FN(DREQ1),
-	GPIO_FN(DREQ0),
-	GPIO_FN(IRQ3),
-	GPIO_FN(IRQ2),
-	GPIO_FN(IRQ1),
-	GPIO_FN(IRQ0),
-	GPIO_FN(DRAK3),
-	GPIO_FN(DRAK2),
-	GPIO_FN(DRAK1),
-	GPIO_FN(DRAK0),
-	GPIO_FN(SCK3),
-	GPIO_FN(SCK2),
-	GPIO_FN(SCK1),
-	GPIO_FN(SCK0),
-	GPIO_FN(IRL3),
-	GPIO_FN(IRL2),
-	GPIO_FN(IRL1),
-	GPIO_FN(IRL0),
-	GPIO_FN(TXD3),
-	GPIO_FN(TXD2),
-	GPIO_FN(TXD1),
-	GPIO_FN(TXD0),
-	GPIO_FN(RXD3),
-	GPIO_FN(RXD2),
-	GPIO_FN(RXD1),
-	GPIO_FN(RXD0),
-	GPIO_FN(CE2B),
-	GPIO_FN(CE2A),
-	GPIO_FN(IOIS16),
-	GPIO_FN(STATUS1),
-	GPIO_FN(STATUS0),
-	GPIO_FN(IRQOUT),
-};
-
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-	{ PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2, GROUP(
-		PA7_FN, PA7_OUT, PA7_IN, 0,
-		PA6_FN, PA6_OUT, PA6_IN, 0,
-		PA5_FN, PA5_OUT, PA5_IN, 0,
-		PA4_FN, PA4_OUT, PA4_IN, 0,
-		PA3_FN, PA3_OUT, PA3_IN, 0,
-		PA2_FN, PA2_OUT, PA2_IN, 0,
-		PA1_FN, PA1_OUT, PA1_IN, 0,
-		PA0_FN, PA0_OUT, PA0_IN, 0,
-		PB7_FN, PB7_OUT, PB7_IN, 0,
-		PB6_FN, PB6_OUT, PB6_IN, 0,
-		PB5_FN, PB5_OUT, PB5_IN, 0,
-		PB4_FN, PB4_OUT, PB4_IN, 0,
-		PB3_FN, PB3_OUT, PB3_IN, 0,
-		PB2_FN, PB2_OUT, PB2_IN, 0,
-		PB1_FN, PB1_OUT, PB1_IN, 0,
-		PB0_FN, PB0_OUT, PB0_IN, 0, ))
-	},
-	{ PINMUX_CFG_REG("PCDCR", 0xffc70004, 32, 2, GROUP(
-		PC7_FN, PC7_OUT, PC7_IN, 0,
-		PC6_FN, PC6_OUT, PC6_IN, 0,
-		PC5_FN, PC5_OUT, PC5_IN, 0,
-		PC4_FN, PC4_OUT, PC4_IN, 0,
-		PC3_FN, PC3_OUT, PC3_IN, 0,
-		PC2_FN, PC2_OUT, PC2_IN, 0,
-		PC1_FN, PC1_OUT, PC1_IN, 0,
-		PC0_FN, PC0_OUT, PC0_IN, 0,
-		PD7_FN, PD7_OUT, PD7_IN, 0,
-		PD6_FN, PD6_OUT, PD6_IN, 0,
-		PD5_FN, PD5_OUT, PD5_IN, 0,
-		PD4_FN, PD4_OUT, PD4_IN, 0,
-		PD3_FN, PD3_OUT, PD3_IN, 0,
-		PD2_FN, PD2_OUT, PD2_IN, 0,
-		PD1_FN, PD1_OUT, PD1_IN, 0,
-		PD0_FN, PD0_OUT, PD0_IN, 0, ))
-	},
-	{ PINMUX_CFG_REG("PEFCR", 0xffc70008, 32, 2, GROUP(
-		PE7_FN, PE7_OUT, PE7_IN, 0,
-		PE6_FN, PE6_OUT, PE6_IN, 0,
-		PE5_FN, PE5_OUT, PE5_IN, 0,
-		PE4_FN, PE4_OUT, PE4_IN, 0,
-		PE3_FN, PE3_OUT, PE3_IN, 0,
-		PE2_FN, PE2_OUT, PE2_IN, 0,
-		PE1_FN, PE1_OUT, PE1_IN, 0,
-		PE0_FN, PE0_OUT, PE0_IN, 0,
-		PF7_FN, PF7_OUT, PF7_IN, 0,
-		PF6_FN, PF6_OUT, PF6_IN, 0,
-		PF5_FN, PF5_OUT, PF5_IN, 0,
-		PF4_FN, PF4_OUT, PF4_IN, 0,
-		PF3_FN, PF3_OUT, PF3_IN, 0,
-		PF2_FN, PF2_OUT, PF2_IN, 0,
-		PF1_FN, PF1_OUT, PF1_IN, 0,
-		PF0_FN, PF0_OUT, PF0_IN, 0, ))
-	},
-	{ PINMUX_CFG_REG("PGHCR", 0xffc7000c, 32, 2, GROUP(
-		PG7_FN, PG7_OUT, PG7_IN, 0,
-		PG6_FN, PG6_OUT, PG6_IN, 0,
-		PG5_FN, PG5_OUT, PG5_IN, 0,
-		PG4_FN, PG4_OUT, PG4_IN, 0,
-		PG3_FN, PG3_OUT, PG3_IN, 0,
-		PG2_FN, PG2_OUT, PG2_IN, 0,
-		PG1_FN, PG1_OUT, PG1_IN, 0,
-		PG0_FN, PG0_OUT, PG0_IN, 0,
-		0, 0, 0, 0,
-		0, 0, 0, 0,
-		PH5_FN, PH5_OUT, PH5_IN, 0,
-		PH4_FN, PH4_OUT, PH4_IN, 0,
-		PH3_FN, PH3_OUT, PH3_IN, 0,
-		PH2_FN, PH2_OUT, PH2_IN, 0,
-		PH1_FN, PH1_OUT, PH1_IN, 0,
-		PH0_FN, PH0_OUT, PH0_IN, 0, ))
-	},
-	{ },
-};
-
-static const struct pinmux_data_reg pinmux_data_regs[] = {
-	{ PINMUX_DATA_REG("PABDR", 0xffc70010, 32, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
-		PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
-		PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, ))
-	},
-	{ PINMUX_DATA_REG("PCDDR", 0xffc70014, 32, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
-		PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
-		PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, ))
-	},
-	{ PINMUX_DATA_REG("PEFDR", 0xffc70018, 32, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
-		PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
-		PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, ))
-	},
-	{ PINMUX_DATA_REG("PGHDR", 0xffc7001c, 32, GROUP(
-		0, 0, 0, 0, 0, 0, 0, 0,
-		PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
-		PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, PH5_DATA, PH4_DATA,
-		PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, ))
-	},
-	{ },
-};
-
-const struct sh_pfc_soc_info shx3_pinmux_info = {
-	.name		= "shx3_pfc",
-	.input		= { PINMUX_INPUT_BEGIN,	   PINMUX_INPUT_END },
-	.output		= { PINMUX_OUTPUT_BEGIN,   PINMUX_OUTPUT_END },
-	.function	= { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-	.pins		= pinmux_pins,
-	.nr_pins	= ARRAY_SIZE(pinmux_pins),
-	.func_gpios	= pinmux_func_gpios,
-	.nr_func_gpios	= ARRAY_SIZE(pinmux_func_gpios),
-	.pinmux_data	= pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-	.cfg_regs	= pinmux_config_regs,
-	.data_regs	= pinmux_data_regs,
-};
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
deleted file mode 100644
index 212a4a9c3a8f..000000000000
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ /dev/null
@@ -1,832 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * SuperH Pin Function Controller pinmux support.
- *
- * Copyright (C) 2012  Paul Mundt
- */
-
-#define DRV_NAME "sh-pfc"
-
-#include <linux/device.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-
-#include "core.h"
-#include "../core.h"
-#include "../pinconf.h"
-
-struct sh_pfc_pin_config {
-	unsigned int mux_mark;
-	bool mux_set;
-	bool gpio_enabled;
-};
-
-struct sh_pfc_pinctrl {
-	struct pinctrl_dev *pctl;
-	struct pinctrl_desc pctl_desc;
-
-	struct sh_pfc *pfc;
-
-	struct pinctrl_pin_desc *pins;
-	struct sh_pfc_pin_config *configs;
-
-	const char *func_prop_name;
-	const char *groups_prop_name;
-	const char *pins_prop_name;
-};
-
-static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
-{
-	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
-
-	return pmx->pfc->info->nr_groups;
-}
-
-static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
-					 unsigned selector)
-{
-	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
-
-	return pmx->pfc->info->groups[selector].name;
-}
-
-static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
-				 const unsigned **pins, unsigned *num_pins)
-{
-	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
-
-	*pins = pmx->pfc->info->groups[selector].pins;
-	*num_pins = pmx->pfc->info->groups[selector].nr_pins;
-
-	return 0;
-}
-
-static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
-				unsigned offset)
-{
-	seq_puts(s, DRV_NAME);
-}
-
-#ifdef CONFIG_OF
-static int sh_pfc_map_add_config(struct pinctrl_map *map,
-				 const char *group_or_pin,
-				 enum pinctrl_map_type type,
-				 unsigned long *configs,
-				 unsigned int num_configs)
-{
-	unsigned long *cfgs;
-
-	cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
-		       GFP_KERNEL);
-	if (cfgs == NULL)
-		return -ENOMEM;
-
-	map->type = type;
-	map->data.configs.group_or_pin = group_or_pin;
-	map->data.configs.configs = cfgs;
-	map->data.configs.num_configs = num_configs;
-
-	return 0;
-}
-
-static int sh_pfc_dt_subnode_to_map(struct pinctrl_dev *pctldev,
-				    struct device_node *np,
-				    struct pinctrl_map **map,
-				    unsigned int *num_maps, unsigned int *index)
-{
-	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
-	struct device *dev = pmx->pfc->dev;
-	struct pinctrl_map *maps = *map;
-	unsigned int nmaps = *num_maps;
-	unsigned int idx = *index;
-	unsigned int num_configs;
-	const char *function = NULL;
-	unsigned long *configs;
-	struct property *prop;
-	unsigned int num_groups;
-	unsigned int num_pins;
-	const char *group;
-	const char *pin;
-	int ret;
-
-	/* Support both the old Renesas-specific properties and the new standard
-	 * properties. Mixing old and new properties isn't allowed, neither
-	 * inside a subnode nor across subnodes.
-	 */
-	if (!pmx->func_prop_name) {
-		if (of_find_property(np, "groups", NULL) ||
-		    of_find_property(np, "pins", NULL)) {
-			pmx->func_prop_name = "function";
-			pmx->groups_prop_name = "groups";
-			pmx->pins_prop_name = "pins";
-		} else {
-			pmx->func_prop_name = "renesas,function";
-			pmx->groups_prop_name = "renesas,groups";
-			pmx->pins_prop_name = "renesas,pins";
-		}
-	}
-
-	/* Parse the function and configuration properties. At least a function
-	 * or one configuration must be specified.
-	 */
-	ret = of_property_read_string(np, pmx->func_prop_name, &function);
-	if (ret < 0 && ret != -EINVAL) {
-		dev_err(dev, "Invalid function in DT\n");
-		return ret;
-	}
-
-	ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
-	if (ret < 0)
-		return ret;
-
-	if (!function && num_configs == 0) {
-		dev_err(dev,
-			"DT node must contain at least a function or config\n");
-		ret = -ENODEV;
-		goto done;
-	}
-
-	/* Count the number of pins and groups and reallocate mappings. */
-	ret = of_property_count_strings(np, pmx->pins_prop_name);
-	if (ret == -EINVAL) {
-		num_pins = 0;
-	} else if (ret < 0) {
-		dev_err(dev, "Invalid pins list in DT\n");
-		goto done;
-	} else {
-		num_pins = ret;
-	}
-
-	ret = of_property_count_strings(np, pmx->groups_prop_name);
-	if (ret == -EINVAL) {
-		num_groups = 0;
-	} else if (ret < 0) {
-		dev_err(dev, "Invalid pin groups list in DT\n");
-		goto done;
-	} else {
-		num_groups = ret;
-	}
-
-	if (!num_pins && !num_groups) {
-		dev_err(dev, "No pin or group provided in DT node\n");
-		ret = -ENODEV;
-		goto done;
-	}
-
-	if (function)
-		nmaps += num_groups;
-	if (configs)
-		nmaps += num_pins + num_groups;
-
-	maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL);
-	if (maps == NULL) {
-		ret = -ENOMEM;
-		goto done;
-	}
-
-	*map = maps;
-	*num_maps = nmaps;
-
-	/* Iterate over pins and groups and create the mappings. */
-	of_property_for_each_string(np, pmx->groups_prop_name, prop, group) {
-		if (function) {
-			maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
-			maps[idx].data.mux.group = group;
-			maps[idx].data.mux.function = function;
-			idx++;
-		}
-
-		if (configs) {
-			ret = sh_pfc_map_add_config(&maps[idx], group,
-						    PIN_MAP_TYPE_CONFIGS_GROUP,
-						    configs, num_configs);
-			if (ret < 0)
-				goto done;
-
-			idx++;
-		}
-	}
-
-	if (!configs) {
-		ret = 0;
-		goto done;
-	}
-
-	of_property_for_each_string(np, pmx->pins_prop_name, prop, pin) {
-		ret = sh_pfc_map_add_config(&maps[idx], pin,
-					    PIN_MAP_TYPE_CONFIGS_PIN,
-					    configs, num_configs);
-		if (ret < 0)
-			goto done;
-
-		idx++;
-	}
-
-done:
-	*index = idx;
-	kfree(configs);
-	return ret;
-}
-
-static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev,
-			       struct pinctrl_map *map, unsigned num_maps)
-{
-	unsigned int i;
-
-	if (map == NULL)
-		return;
-
-	for (i = 0; i < num_maps; ++i) {
-		if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
-		    map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
-			kfree(map[i].data.configs.configs);
-	}
-
-	kfree(map);
-}
-
-static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
-				 struct device_node *np,
-				 struct pinctrl_map **map, unsigned *num_maps)
-{
-	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
-	struct device *dev = pmx->pfc->dev;
-	struct device_node *child;
-	unsigned int index;
-	int ret;
-
-	*map = NULL;
-	*num_maps = 0;
-	index = 0;
-
-	for_each_child_of_node(np, child) {
-		ret = sh_pfc_dt_subnode_to_map(pctldev, child, map, num_maps,
-					       &index);
-		if (ret < 0) {
-			of_node_put(child);
-			goto done;
-		}
-	}
-
-	/* If no mapping has been found in child nodes try the config node. */
-	if (*num_maps == 0) {
-		ret = sh_pfc_dt_subnode_to_map(pctldev, np, map, num_maps,
-					       &index);
-		if (ret < 0)
-			goto done;
-	}
-
-	if (*num_maps)
-		return 0;
-
-	dev_err(dev, "no mapping found in node %pOF\n", np);
-	ret = -EINVAL;
-
-done:
-	if (ret < 0)
-		sh_pfc_dt_free_map(pctldev, *map, *num_maps);
-
-	return ret;
-}
-#endif /* CONFIG_OF */
-
-static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
-	.get_groups_count	= sh_pfc_get_groups_count,
-	.get_group_name		= sh_pfc_get_group_name,
-	.get_group_pins		= sh_pfc_get_group_pins,
-	.pin_dbg_show		= sh_pfc_pin_dbg_show,
-#ifdef CONFIG_OF
-	.dt_node_to_map		= sh_pfc_dt_node_to_map,
-	.dt_free_map		= sh_pfc_dt_free_map,
-#endif
-};
-
-static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
-{
-	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
-
-	return pmx->pfc->info->nr_functions;
-}
-
-static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
-					    unsigned selector)
-{
-	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
-
-	return pmx->pfc->info->functions[selector].name;
-}
-
-static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
-				      unsigned selector,
-				      const char * const **groups,
-				      unsigned * const num_groups)
-{
-	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
-
-	*groups = pmx->pfc->info->functions[selector].groups;
-	*num_groups = pmx->pfc->info->functions[selector].nr_groups;
-
-	return 0;
-}
-
-static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
-			       unsigned group)
-{
-	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
-	struct sh_pfc *pfc = pmx->pfc;
-	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
-	unsigned long flags;
-	unsigned int i;
-	int ret = 0;
-
-	dev_dbg(pctldev->dev, "Configuring pin group %s\n", grp->name);
-
-	spin_lock_irqsave(&pfc->lock, flags);
-
-	for (i = 0; i < grp->nr_pins; ++i) {
-		int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
-		struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
-
-		/*
-		 * This driver cannot manage both gpio and mux when the gpio
-		 * pin is already enabled. So, this function fails.
-		 */
-		if (cfg->gpio_enabled) {
-			ret = -EBUSY;
-			goto done;
-		}
-
-		ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
-		if (ret < 0)
-			goto done;
-	}
-
-	/* All group pins are configured, mark the pins as mux_set */
-	for (i = 0; i < grp->nr_pins; ++i) {
-		int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
-		struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
-
-		cfg->mux_set = true;
-		cfg->mux_mark = grp->mux[i];
-	}
-
-done:
-	spin_unlock_irqrestore(&pfc->lock, flags);
-	return ret;
-}
-
-static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
-				      struct pinctrl_gpio_range *range,
-				      unsigned offset)
-{
-	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
-	struct sh_pfc *pfc = pmx->pfc;
-	int idx = sh_pfc_get_pin_index(pfc, offset);
-	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
-	unsigned long flags;
-	int ret;
-
-	spin_lock_irqsave(&pfc->lock, flags);
-
-	if (!pfc->gpio) {
-		/* If GPIOs are handled externally the pin mux type need to be
-		 * set to GPIO here.
-		 */
-		const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
-
-		ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
-		if (ret < 0)
-			goto done;
-	}
-
-	cfg->gpio_enabled = true;
-
-	ret = 0;
-
-done:
-	spin_unlock_irqrestore(&pfc->lock, flags);
-
-	return ret;
-}
-
-static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
-				     struct pinctrl_gpio_range *range,
-				     unsigned offset)
-{
-	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
-	struct sh_pfc *pfc = pmx->pfc;
-	int idx = sh_pfc_get_pin_index(pfc, offset);
-	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
-	unsigned long flags;
-
-	spin_lock_irqsave(&pfc->lock, flags);
-	cfg->gpio_enabled = false;
-	/* If mux is already set, this configures it here */
-	if (cfg->mux_set)
-		sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION);
-	spin_unlock_irqrestore(&pfc->lock, flags);
-}
-
-static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
-				     struct pinctrl_gpio_range *range,
-				     unsigned offset, bool input)
-{
-	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
-	struct sh_pfc *pfc = pmx->pfc;
-	int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
-	int idx = sh_pfc_get_pin_index(pfc, offset);
-	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
-	unsigned long flags;
-	unsigned int dir;
-	int ret;
-
-	/* Check if the requested direction is supported by the pin. Not all SoC
-	 * provide pin config data, so perform the check conditionally.
-	 */
-	if (pin->configs) {
-		dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT;
-		if (!(pin->configs & dir))
-			return -EINVAL;
-	}
-
-	spin_lock_irqsave(&pfc->lock, flags);
-
-	ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
-	if (ret < 0)
-		goto done;
-
-done:
-	spin_unlock_irqrestore(&pfc->lock, flags);
-	return ret;
-}
-
-static const struct pinmux_ops sh_pfc_pinmux_ops = {
-	.get_functions_count	= sh_pfc_get_functions_count,
-	.get_function_name	= sh_pfc_get_function_name,
-	.get_function_groups	= sh_pfc_get_function_groups,
-	.set_mux		= sh_pfc_func_set_mux,
-	.gpio_request_enable	= sh_pfc_gpio_request_enable,
-	.gpio_disable_free	= sh_pfc_gpio_disable_free,
-	.gpio_set_direction	= sh_pfc_gpio_set_direction,
-};
-
-static u32 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc,
-		unsigned int pin, unsigned int *offset, unsigned int *size)
-{
-	const struct pinmux_drive_reg_field *field;
-	const struct pinmux_drive_reg *reg;
-	unsigned int i;
-
-	for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
-		for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
-			field = &reg->fields[i];
-
-			if (field->size && field->pin == pin) {
-				*offset = field->offset;
-				*size = field->size;
-
-				return reg->reg;
-			}
-		}
-	}
-
-	return 0;
-}
-
-static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc,
-					     unsigned int pin)
-{
-	unsigned long flags;
-	unsigned int offset;
-	unsigned int size;
-	u32 reg;
-	u32 val;
-
-	reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
-	if (!reg)
-		return -EINVAL;
-
-	spin_lock_irqsave(&pfc->lock, flags);
-	val = sh_pfc_read(pfc, reg);
-	spin_unlock_irqrestore(&pfc->lock, flags);
-
-	val = (val >> offset) & GENMASK(size - 1, 0);
-
-	/* Convert the value to mA based on a full drive strength value of 24mA.
-	 * We can make the full value configurable later if needed.
-	 */
-	return (val + 1) * (size == 2 ? 6 : 3);
-}
-
-static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
-					     unsigned int pin, u16 strength)
-{
-	unsigned long flags;
-	unsigned int offset;
-	unsigned int size;
-	unsigned int step;
-	u32 reg;
-	u32 val;
-
-	reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
-	if (!reg)
-		return -EINVAL;
-
-	step = size == 2 ? 6 : 3;
-
-	if (strength < step || strength > 24)
-		return -EINVAL;
-
-	/* Convert the value from mA based on a full drive strength value of
-	 * 24mA. We can make the full value configurable later if needed.
-	 */
-	strength = strength / step - 1;
-
-	spin_lock_irqsave(&pfc->lock, flags);
-
-	val = sh_pfc_read(pfc, reg);
-	val &= ~GENMASK(offset + size - 1, offset);
-	val |= strength << offset;
-
-	sh_pfc_write(pfc, reg, val);
-
-	spin_unlock_irqrestore(&pfc->lock, flags);
-
-	return 0;
-}
-
-/* Check whether the requested parameter is supported for a pin. */
-static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
-				    enum pin_config_param param)
-{
-	int idx = sh_pfc_get_pin_index(pfc, _pin);
-	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
-
-	switch (param) {
-	case PIN_CONFIG_BIAS_DISABLE:
-		return pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN;
-
-	case PIN_CONFIG_BIAS_PULL_UP:
-		return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
-
-	case PIN_CONFIG_BIAS_PULL_DOWN:
-		return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
-
-	case PIN_CONFIG_DRIVE_STRENGTH:
-		return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
-
-	case PIN_CONFIG_POWER_SOURCE:
-		return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
-
-	default:
-		return false;
-	}
-}
-
-static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
-			      unsigned long *config)
-{
-	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
-	struct sh_pfc *pfc = pmx->pfc;
-	enum pin_config_param param = pinconf_to_config_param(*config);
-	unsigned long flags;
-	unsigned int arg;
-
-	if (!sh_pfc_pinconf_validate(pfc, _pin, param))
-		return -ENOTSUPP;
-
-	switch (param) {
-	case PIN_CONFIG_BIAS_DISABLE:
-	case PIN_CONFIG_BIAS_PULL_UP:
-	case PIN_CONFIG_BIAS_PULL_DOWN: {
-		unsigned int bias;
-
-		if (!pfc->info->ops || !pfc->info->ops->get_bias)
-			return -ENOTSUPP;
-
-		spin_lock_irqsave(&pfc->lock, flags);
-		bias = pfc->info->ops->get_bias(pfc, _pin);
-		spin_unlock_irqrestore(&pfc->lock, flags);
-
-		if (bias != param)
-			return -EINVAL;
-
-		arg = 0;
-		break;
-	}
-
-	case PIN_CONFIG_DRIVE_STRENGTH: {
-		int ret;
-
-		ret = sh_pfc_pinconf_get_drive_strength(pfc, _pin);
-		if (ret < 0)
-			return ret;
-
-		arg = ret;
-		break;
-	}
-
-	case PIN_CONFIG_POWER_SOURCE: {
-		u32 pocctrl, val;
-		int bit;
-
-		if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
-			return -ENOTSUPP;
-
-		bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
-		if (WARN(bit < 0, "invalid pin %#x", _pin))
-			return bit;
-
-		spin_lock_irqsave(&pfc->lock, flags);
-		val = sh_pfc_read(pfc, pocctrl);
-		spin_unlock_irqrestore(&pfc->lock, flags);
-
-		arg = (val & BIT(bit)) ? 3300 : 1800;
-		break;
-	}
-
-	default:
-		return -ENOTSUPP;
-	}
-
-	*config = pinconf_to_config_packed(param, arg);
-	return 0;
-}
-
-static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
-			      unsigned long *configs, unsigned num_configs)
-{
-	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
-	struct sh_pfc *pfc = pmx->pfc;
-	enum pin_config_param param;
-	unsigned long flags;
-	unsigned int i;
-
-	for (i = 0; i < num_configs; i++) {
-		param = pinconf_to_config_param(configs[i]);
-
-		if (!sh_pfc_pinconf_validate(pfc, _pin, param))
-			return -ENOTSUPP;
-
-		switch (param) {
-		case PIN_CONFIG_BIAS_PULL_UP:
-		case PIN_CONFIG_BIAS_PULL_DOWN:
-		case PIN_CONFIG_BIAS_DISABLE:
-			if (!pfc->info->ops || !pfc->info->ops->set_bias)
-				return -ENOTSUPP;
-
-			spin_lock_irqsave(&pfc->lock, flags);
-			pfc->info->ops->set_bias(pfc, _pin, param);
-			spin_unlock_irqrestore(&pfc->lock, flags);
-
-			break;
-
-		case PIN_CONFIG_DRIVE_STRENGTH: {
-			unsigned int arg =
-				pinconf_to_config_argument(configs[i]);
-			int ret;
-
-			ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
-			if (ret < 0)
-				return ret;
-
-			break;
-		}
-
-		case PIN_CONFIG_POWER_SOURCE: {
-			unsigned int mV = pinconf_to_config_argument(configs[i]);
-			u32 pocctrl, val;
-			int bit;
-
-			if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
-				return -ENOTSUPP;
-
-			bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
-			if (WARN(bit < 0, "invalid pin %#x", _pin))
-				return bit;
-
-			if (mV != 1800 && mV != 3300)
-				return -EINVAL;
-
-			spin_lock_irqsave(&pfc->lock, flags);
-			val = sh_pfc_read(pfc, pocctrl);
-			if (mV == 3300)
-				val |= BIT(bit);
-			else
-				val &= ~BIT(bit);
-			sh_pfc_write(pfc, pocctrl, val);
-			spin_unlock_irqrestore(&pfc->lock, flags);
-
-			break;
-		}
-
-		default:
-			return -ENOTSUPP;
-		}
-	} /* for each config */
-
-	return 0;
-}
-
-static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
-				    unsigned long *configs,
-				    unsigned num_configs)
-{
-	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
-	const unsigned int *pins;
-	unsigned int num_pins;
-	unsigned int i, ret;
-
-	pins = pmx->pfc->info->groups[group].pins;
-	num_pins = pmx->pfc->info->groups[group].nr_pins;
-
-	for (i = 0; i < num_pins; ++i) {
-		ret = sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
-static const struct pinconf_ops sh_pfc_pinconf_ops = {
-	.is_generic			= true,
-	.pin_config_get			= sh_pfc_pinconf_get,
-	.pin_config_set			= sh_pfc_pinconf_set,
-	.pin_config_group_set		= sh_pfc_pinconf_group_set,
-	.pin_config_config_dbg_show	= pinconf_generic_dump_config,
-};
-
-/* PFC ranges -> pinctrl pin descs */
-static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
-{
-	unsigned int i;
-
-	/* Allocate and initialize the pins and configs arrays. */
-	pmx->pins = devm_kcalloc(pfc->dev,
-				 pfc->info->nr_pins, sizeof(*pmx->pins),
-				 GFP_KERNEL);
-	if (unlikely(!pmx->pins))
-		return -ENOMEM;
-
-	pmx->configs = devm_kcalloc(pfc->dev,
-				    pfc->info->nr_pins, sizeof(*pmx->configs),
-				    GFP_KERNEL);
-	if (unlikely(!pmx->configs))
-		return -ENOMEM;
-
-	for (i = 0; i < pfc->info->nr_pins; ++i) {
-		const struct sh_pfc_pin *info = &pfc->info->pins[i];
-		struct pinctrl_pin_desc *pin = &pmx->pins[i];
-
-		/* If the pin number is equal to -1 all pins are considered */
-		pin->number = info->pin != (u16)-1 ? info->pin : i;
-		pin->name = info->name;
-	}
-
-	return 0;
-}
-
-int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
-{
-	struct sh_pfc_pinctrl *pmx;
-	int ret;
-
-	pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
-	if (unlikely(!pmx))
-		return -ENOMEM;
-
-	pmx->pfc = pfc;
-
-	ret = sh_pfc_map_pins(pfc, pmx);
-	if (ret < 0)
-		return ret;
-
-	pmx->pctl_desc.name = DRV_NAME;
-	pmx->pctl_desc.owner = THIS_MODULE;
-	pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
-	pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
-	pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
-	pmx->pctl_desc.pins = pmx->pins;
-	pmx->pctl_desc.npins = pfc->info->nr_pins;
-
-	ret = devm_pinctrl_register_and_init(pfc->dev, &pmx->pctl_desc, pmx,
-					     &pmx->pctl);
-	if (ret) {
-		dev_err(pfc->dev, "could not register: %i\n", ret);
-
-		return ret;
-	}
-
-	return pinctrl_enable(pmx->pctl);
-}
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
deleted file mode 100644
index d57e633e99c0..000000000000
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ /dev/null
@@ -1,754 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * SuperH Pin Function Controller Support
- *
- * Copyright (c) 2008 Magnus Damm
- */
-
-#ifndef __SH_PFC_H
-#define __SH_PFC_H
-
-#include <linux/bug.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/spinlock.h>
-#include <linux/stringify.h>
-
-enum {
-	PINMUX_TYPE_NONE,
-	PINMUX_TYPE_FUNCTION,
-	PINMUX_TYPE_GPIO,
-	PINMUX_TYPE_OUTPUT,
-	PINMUX_TYPE_INPUT,
-};
-
-#define SH_PFC_PIN_NONE			U16_MAX
-
-#define SH_PFC_PIN_CFG_INPUT		(1 << 0)
-#define SH_PFC_PIN_CFG_OUTPUT		(1 << 1)
-#define SH_PFC_PIN_CFG_PULL_UP		(1 << 2)
-#define SH_PFC_PIN_CFG_PULL_DOWN	(1 << 3)
-#define SH_PFC_PIN_CFG_PULL_UP_DOWN	(SH_PFC_PIN_CFG_PULL_UP | \
-					 SH_PFC_PIN_CFG_PULL_DOWN)
-#define SH_PFC_PIN_CFG_IO_VOLTAGE	(1 << 4)
-#define SH_PFC_PIN_CFG_DRIVE_STRENGTH	(1 << 5)
-#define SH_PFC_PIN_CFG_NO_GPIO		(1 << 31)
-
-struct sh_pfc_pin {
-	u16 pin;
-	u16 enum_id;
-	const char *name;
-	unsigned int configs;
-};
-
-#define SH_PFC_PIN_GROUP_ALIAS(alias, n)		\
-	{						\
-		.name = #alias,				\
-		.pins = n##_pins,			\
-		.mux = n##_mux,				\
-		.nr_pins = ARRAY_SIZE(n##_pins) +	\
-		BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \
-	}
-#define SH_PFC_PIN_GROUP(n)	SH_PFC_PIN_GROUP_ALIAS(n, n)
-
-struct sh_pfc_pin_group {
-	const char *name;
-	const unsigned int *pins;
-	const unsigned int *mux;
-	unsigned int nr_pins;
-};
-
-/*
- * Using union vin_data{,12,16} saves memory occupied by the VIN data pins.
- * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
- * in this case. It accepts an optional 'version' argument used when the
- * same group can appear on a different set of pins.
- */
-#define VIN_DATA_PIN_GROUP(n, s, ...)					\
-	{								\
-		.name = #n#s#__VA_ARGS__,				\
-		.pins = n##__VA_ARGS__##_pins.data##s,			\
-		.mux = n##__VA_ARGS__##_mux.data##s,			\
-		.nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s),	\
-	}
-
-union vin_data12 {
-	unsigned int data12[12];
-	unsigned int data10[10];
-	unsigned int data8[8];
-};
-
-union vin_data16 {
-	unsigned int data16[16];
-	unsigned int data12[12];
-	unsigned int data10[10];
-	unsigned int data8[8];
-};
-
-union vin_data {
-	unsigned int data24[24];
-	unsigned int data20[20];
-	unsigned int data16[16];
-	unsigned int data12[12];
-	unsigned int data10[10];
-	unsigned int data8[8];
-	unsigned int data4[4];
-};
-
-#define SH_PFC_FUNCTION(n)				\
-	{						\
-		.name = #n,				\
-		.groups = n##_groups,			\
-		.nr_groups = ARRAY_SIZE(n##_groups),	\
-	}
-
-struct sh_pfc_function {
-	const char *name;
-	const char * const *groups;
-	unsigned int nr_groups;
-};
-
-struct pinmux_func {
-	u16 enum_id;
-	const char *name;
-};
-
-struct pinmux_cfg_reg {
-	u32 reg;
-	u8 reg_width, field_width;
-#ifdef DEBUG
-	u16 nr_enum_ids;	/* for variable width regs only */
-#define SET_NR_ENUM_IDS(n)	.nr_enum_ids = n,
-#else
-#define SET_NR_ENUM_IDS(n)
-#endif
-	const u16 *enum_ids;
-	const u8 *var_field_width;
-};
-
-#define GROUP(...)	__VA_ARGS__
-
-/*
- * Describe a config register consisting of several fields of the same width
- *   - name: Register name (unused, for documentation purposes only)
- *   - r: Physical register address
- *   - r_width: Width of the register (in bits)
- *   - f_width: Width of the fixed-width register fields (in bits)
- *   - ids: For each register field (from left to right, i.e. MSB to LSB),
- *          2^f_width enum IDs must be specified, one for each possible
- *          combination of the register field bit values, all wrapped using
- *          the GROUP() macro.
- */
-#define PINMUX_CFG_REG(name, r, r_width, f_width, ids)			\
-	.reg = r, .reg_width = r_width,					\
-	.field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) +	\
-	BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
-			  (r_width / f_width) * (1 << f_width)),	\
-	.enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])	\
-		{ ids }
-
-/*
- * Describe a config register consisting of several fields of different widths
- *   - name: Register name (unused, for documentation purposes only)
- *   - r: Physical register address
- *   - r_width: Width of the register (in bits)
- *   - f_widths: List of widths of the register fields (in bits), from left
- *               to right (i.e. MSB to LSB), wrapped using the GROUP() macro.
- *   - ids: For each register field (from left to right, i.e. MSB to LSB),
- *          2^f_widths[i] enum IDs must be specified, one for each possible
- *          combination of the register field bit values, all wrapped using
- *          the GROUP() macro.
- */
-#define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids)		\
-	.reg = r, .reg_width = r_width,					\
-	.var_field_width = (const u8 []) { f_widths, 0 },		\
-	SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16))	\
-	.enum_ids = (const u16 []) { ids }
-
-struct pinmux_drive_reg_field {
-	u16 pin;
-	u8 offset;
-	u8 size;
-};
-
-struct pinmux_drive_reg {
-	u32 reg;
-	const struct pinmux_drive_reg_field fields[8];
-};
-
-#define PINMUX_DRIVE_REG(name, r) \
-	.reg = r, \
-	.fields =
-
-struct pinmux_bias_reg {
-	u32 puen;		/* Pull-enable or pull-up control register */
-	u32 pud;		/* Pull-up/down control register (optional) */
-	const u16 pins[32];
-};
-
-#define PINMUX_BIAS_REG(name1, r1, name2, r2) \
-	.puen = r1,	\
-	.pud = r2,	\
-	.pins =
-
-struct pinmux_ioctrl_reg {
-	u32 reg;
-};
-
-struct pinmux_data_reg {
-	u32 reg;
-	u8 reg_width;
-	const u16 *enum_ids;
-};
-
-/*
- * Describe a data register
- *   - name: Register name (unused, for documentation purposes only)
- *   - r: Physical register address
- *   - r_width: Width of the register (in bits)
- *   - ids: For each register bit (from left to right, i.e. MSB to LSB), one
- *          enum ID must be specified, all wrapped using the GROUP() macro.
- */
-#define PINMUX_DATA_REG(name, r, r_width, ids)				\
-	.reg = r, .reg_width = r_width +				\
-	BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
-			  r_width),					\
-	.enum_ids = (const u16 [r_width]) { ids }
-
-struct pinmux_irq {
-	const short *gpios;
-};
-
-/*
- * Describe the mapping from GPIOs to a single IRQ
- *   - ids...: List of GPIOs that are mapped to the same IRQ
- */
-#define PINMUX_IRQ(ids...)			   \
-	{ .gpios = (const short []) { ids, -1 } }
-
-struct pinmux_range {
-	u16 begin;
-	u16 end;
-	u16 force;
-};
-
-struct sh_pfc_window {
-	phys_addr_t phys;
-	void __iomem *virt;
-	unsigned long size;
-};
-
-struct sh_pfc_pin_range;
-
-struct sh_pfc {
-	struct device *dev;
-	const struct sh_pfc_soc_info *info;
-	spinlock_t lock;
-
-	unsigned int num_windows;
-	struct sh_pfc_window *windows;
-	unsigned int num_irqs;
-	unsigned int *irqs;
-
-	struct sh_pfc_pin_range *ranges;
-	unsigned int nr_ranges;
-
-	unsigned int nr_gpio_pins;
-
-	struct sh_pfc_chip *gpio;
-	u32 *saved_regs;
-};
-
-struct sh_pfc_soc_operations {
-	int (*init)(struct sh_pfc *pfc);
-	unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
-	void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
-			 unsigned int bias);
-	int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
-};
-
-struct sh_pfc_soc_info {
-	const char *name;
-	const struct sh_pfc_soc_operations *ops;
-
-	struct pinmux_range input;
-	struct pinmux_range output;
-	struct pinmux_range function;
-
-	const struct sh_pfc_pin *pins;
-	unsigned int nr_pins;
-	const struct sh_pfc_pin_group *groups;
-	unsigned int nr_groups;
-	const struct sh_pfc_function *functions;
-	unsigned int nr_functions;
-
-#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
-	const struct pinmux_func *func_gpios;
-	unsigned int nr_func_gpios;
-#endif
-
-	const struct pinmux_cfg_reg *cfg_regs;
-	const struct pinmux_drive_reg *drive_regs;
-	const struct pinmux_bias_reg *bias_regs;
-	const struct pinmux_ioctrl_reg *ioctrl_regs;
-	const struct pinmux_data_reg *data_regs;
-
-	const u16 *pinmux_data;
-	unsigned int pinmux_data_size;
-
-	const struct pinmux_irq *gpio_irq;
-	unsigned int gpio_irq_size;
-
-	u32 unlock_reg;
-};
-
-extern const struct sh_pfc_soc_info emev2_pinmux_info;
-extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
-extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
-extern const struct sh_pfc_soc_info r8a7743_pinmux_info;
-extern const struct sh_pfc_soc_info r8a7744_pinmux_info;
-extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
-extern const struct sh_pfc_soc_info r8a77470_pinmux_info;
-extern const struct sh_pfc_soc_info r8a774a1_pinmux_info;
-extern const struct sh_pfc_soc_info r8a774b1_pinmux_info;
-extern const struct sh_pfc_soc_info r8a774c0_pinmux_info;
-extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
-extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
-extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
-extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
-extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
-extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
-extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
-extern const struct sh_pfc_soc_info r8a77950_pinmux_info __weak;
-extern const struct sh_pfc_soc_info r8a77951_pinmux_info __weak;
-extern const struct sh_pfc_soc_info r8a77960_pinmux_info;
-extern const struct sh_pfc_soc_info r8a77961_pinmux_info;
-extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
-extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
-extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
-extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
-extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
-extern const struct sh_pfc_soc_info sh7203_pinmux_info;
-extern const struct sh_pfc_soc_info sh7264_pinmux_info;
-extern const struct sh_pfc_soc_info sh7269_pinmux_info;
-extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
-extern const struct sh_pfc_soc_info sh7720_pinmux_info;
-extern const struct sh_pfc_soc_info sh7722_pinmux_info;
-extern const struct sh_pfc_soc_info sh7723_pinmux_info;
-extern const struct sh_pfc_soc_info sh7724_pinmux_info;
-extern const struct sh_pfc_soc_info sh7734_pinmux_info;
-extern const struct sh_pfc_soc_info sh7757_pinmux_info;
-extern const struct sh_pfc_soc_info sh7785_pinmux_info;
-extern const struct sh_pfc_soc_info sh7786_pinmux_info;
-extern const struct sh_pfc_soc_info shx3_pinmux_info;
-
-/* -----------------------------------------------------------------------------
- * Helper macros to create pin and port lists
- */
-
-/*
- * sh_pfc_soc_info pinmux_data array macros
- */
-
-/*
- * Describe generic pinmux data
- *   - data_or_mark: *_DATA or *_MARK enum ID
- *   - ids...: List of enum IDs to associate with data_or_mark
- */
-#define PINMUX_DATA(data_or_mark, ids...)	data_or_mark, ids, 0
-
-/*
- * Describe a pinmux configuration without GPIO function that needs
- * configuration in a Peripheral Function Select Register (IPSR)
- *   - ipsr: IPSR field (unused, for documentation purposes only)
- *   - fn: Function name, referring to a field in the IPSR
- */
-#define PINMUX_IPSR_NOGP(ipsr, fn)					\
-	PINMUX_DATA(fn##_MARK, FN_##fn)
-
-/*
- * Describe a pinmux configuration with GPIO function that needs configuration
- * in both a Peripheral Function Select Register (IPSR) and in a
- * GPIO/Peripheral Function Select Register (GPSR)
- *   - ipsr: IPSR field
- *   - fn: Function name, also referring to the IPSR field
- */
-#define PINMUX_IPSR_GPSR(ipsr, fn)					\
-	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
-
-/*
- * Describe a pinmux configuration without GPIO function that needs
- * configuration in a Peripheral Function Select Register (IPSR), and where the
- * pinmux function has a representation in a Module Select Register (MOD_SEL).
- *   - ipsr: IPSR field (unused, for documentation purposes only)
- *   - fn: Function name, also referring to the IPSR field
- *   - msel: Module selector
- */
-#define PINMUX_IPSR_NOGM(ipsr, fn, msel)				\
-	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
-
-/*
- * Describe a pinmux configuration with GPIO function where the pinmux function
- * has no representation in a Peripheral Function Select Register (IPSR), but
- * instead solely depends on a group selection.
- *   - gpsr: GPSR field
- *   - fn: Function name, also referring to the GPSR field
- *   - gsel: Group selector
- */
-#define PINMUX_IPSR_NOFN(gpsr, fn, gsel)				\
-	PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
-
-/*
- * Describe a pinmux configuration with GPIO function that needs configuration
- * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
- * Function Select Register (GPSR), and where the pinmux function has a
- * representation in a Module Select Register (MOD_SEL).
- *   - ipsr: IPSR field
- *   - fn: Function name, also referring to the IPSR field
- *   - msel: Module selector
- */
-#define PINMUX_IPSR_MSEL(ipsr, fn, msel)				\
-	PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
-
-/*
- * Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with
- * an additional select register that controls physical multiplexing
- * with another pin.
- *   - ipsr: IPSR field
- *   - fn: Function name, also referring to the IPSR field
- *   - psel: Physical multiplexing selector
- *   - msel: Module selector
- */
-#define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \
-	PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr)
-
-/*
- * Describe a pinmux configuration in which a pin is physically multiplexed
- * with other pins.
- *   - ipsr: IPSR field
- *   - fn: Function name
- *   - psel: Physical multiplexing selector
- */
-#define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
-	PINMUX_DATA(fn##_MARK, FN_##psel, FN_##ipsr)
-
-/*
- * Describe a pinmux configuration for a single-function pin with GPIO
- * capability.
- *   - fn: Function name
- */
-#define PINMUX_SINGLE(fn)						\
-	PINMUX_DATA(fn##_MARK, FN_##fn)
-
-/*
- * GP port style (32 ports banks)
- */
-
-#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg)				\
-	fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
-#define PORT_GP_1(bank, pin, fn, sfx)	PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
-
-#define PORT_GP_CFG_4(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_1(bank, 0,  fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 1,  fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 2,  fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 3,  fn, sfx, cfg)
-#define PORT_GP_4(bank, fn, sfx)	PORT_GP_CFG_4(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_6(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_4(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 4,  fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 5,  fn, sfx, cfg)
-#define PORT_GP_6(bank, fn, sfx)	PORT_GP_CFG_6(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_8(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_6(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 6,  fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 7,  fn, sfx, cfg)
-#define PORT_GP_8(bank, fn, sfx)	PORT_GP_CFG_8(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_9(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_8(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 8,  fn, sfx, cfg)
-#define PORT_GP_9(bank, fn, sfx)	PORT_GP_CFG_9(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_10(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_9(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 9,  fn, sfx, cfg)
-#define PORT_GP_10(bank, fn, sfx)	PORT_GP_CFG_10(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_11(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_10(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)
-#define PORT_GP_11(bank, fn, sfx)	PORT_GP_CFG_11(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_12(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_11(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
-#define PORT_GP_12(bank, fn, sfx)	PORT_GP_CFG_12(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_14(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_12(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 12, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
-#define PORT_GP_14(bank, fn, sfx)	PORT_GP_CFG_14(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_15(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_14(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
-#define PORT_GP_15(bank, fn, sfx)	PORT_GP_CFG_15(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_16(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_15(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
-#define PORT_GP_16(bank, fn, sfx)	PORT_GP_CFG_16(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_17(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_16(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
-#define PORT_GP_17(bank, fn, sfx)	PORT_GP_CFG_17(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_18(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_17(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
-#define PORT_GP_18(bank, fn, sfx)	PORT_GP_CFG_18(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_20(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_18(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 18, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
-#define PORT_GP_20(bank, fn, sfx)	PORT_GP_CFG_20(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_21(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_20(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
-#define PORT_GP_21(bank, fn, sfx)	PORT_GP_CFG_21(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_22(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_21(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
-#define PORT_GP_22(bank, fn, sfx)	PORT_GP_CFG_22(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_23(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_22(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
-#define PORT_GP_23(bank, fn, sfx)	PORT_GP_CFG_23(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_24(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_23(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
-#define PORT_GP_24(bank, fn, sfx)	PORT_GP_CFG_24(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_25(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_24(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 24, fn, sfx, cfg)
-#define PORT_GP_25(bank, fn, sfx)	PORT_GP_CFG_25(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_26(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_25(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
-#define PORT_GP_26(bank, fn, sfx)	PORT_GP_CFG_26(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_27(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_26(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 26, fn, sfx, cfg)
-#define PORT_GP_27(bank, fn, sfx)	PORT_GP_CFG_27(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_28(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_27(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
-#define PORT_GP_28(bank, fn, sfx)	PORT_GP_CFG_28(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_29(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_28(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
-#define PORT_GP_29(bank, fn, sfx)	PORT_GP_CFG_29(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_30(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_29(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
-#define PORT_GP_30(bank, fn, sfx)	PORT_GP_CFG_30(bank, fn, sfx, 0)
-
-#define PORT_GP_CFG_32(bank, fn, sfx, cfg)				\
-	PORT_GP_CFG_30(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 30, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
-#define PORT_GP_32(bank, fn, sfx)	PORT_GP_CFG_32(bank, fn, sfx, 0)
-
-#define PORT_GP_32_REV(bank, fn, sfx)					\
-	PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),	\
-	PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),	\
-	PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),	\
-	PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),	\
-	PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),	\
-	PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),	\
-	PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),	\
-	PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),	\
-	PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),	\
-	PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),	\
-	PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),	\
-	PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),	\
-	PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),	\
-	PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),	\
-	PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),	\
-	PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)
-
-/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
-#define _GP_ALL(bank, pin, name, sfx, cfg)	name##_##sfx
-#define GP_ALL(str)			CPU_ALL_GP(_GP_ALL, str)
-
-/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
-#define _GP_GPIO(bank, _pin, _name, sfx, cfg)				\
-	{								\
-		.pin = (bank * 32) + _pin,				\
-		.name = __stringify(_name),				\
-		.enum_id = _name##_DATA,				\
-		.configs = cfg,						\
-	}
-#define PINMUX_GPIO_GP_ALL()		CPU_ALL_GP(_GP_GPIO, unused)
-
-/* PINMUX_DATA_GP_ALL -  Expand to a list of name_DATA, name_FN marks */
-#define _GP_DATA(bank, pin, name, sfx, cfg)	PINMUX_DATA(name##_DATA, name##_FN)
-#define PINMUX_DATA_GP_ALL()		CPU_ALL_GP(_GP_DATA, unused)
-
-/*
- * GP_ASSIGN_LAST() - Expand to an enum definition for the last GP pin
- *
- * The largest GP pin index is obtained by taking the size of a union,
- * containing one array per GP pin, sized by the corresponding pin index.
- * As the fields in the CPU_ALL_GP() macro definition are separated by commas,
- * while the members of a union must be terminated by semicolons, the commas
- * are absorbed by wrapping them inside dummy attributes.
- */
-#define _GP_ENTRY(bank, pin, name, sfx, cfg)				\
-	deprecated)); char name[(bank * 32) + pin] __attribute__((deprecated
-#define GP_ASSIGN_LAST()						\
-	GP_LAST = sizeof(union {					\
-		char dummy[0] __attribute__((deprecated,		\
-		CPU_ALL_GP(_GP_ENTRY, unused),				\
-		deprecated));						\
-	})
-
-/*
- * PORT style (linear pin space)
- */
-
-#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
-
-#define PORT_10(pn, fn, pfx, sfx)					  \
-	PORT_1(pn,   fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx),	  \
-	PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx),	  \
-	PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx),	  \
-	PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx),	  \
-	PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
-
-#define PORT_90(pn, fn, pfx, sfx)					  \
-	PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
-	PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
-	PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
-	PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
-	PORT_10(pn+90, fn, pfx##9, sfx)
-
-/* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
-#define _PORT_ALL(pn, pfx, sfx)		pfx##_##sfx
-#define PORT_ALL(str)			CPU_ALL_PORT(_PORT_ALL, PORT, str)
-
-/* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
-#define PINMUX_GPIO(_pin)						\
-	[GPIO_##_pin] = {						\
-		.pin = (u16)-1,						\
-		.name = __stringify(GPIO_##_pin),			\
-		.enum_id = _pin##_DATA,					\
-	}
-
-/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
-#define SH_PFC_PIN_CFG(_pin, cfgs)					\
-	{								\
-		.pin = _pin,						\
-		.name = __stringify(PORT##_pin),			\
-		.enum_id = PORT##_pin##_DATA,				\
-		.configs = cfgs,					\
-	}
-
-/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
- *		     PORT_name_OUT, PORT_name_IN marks
- */
-#define _PORT_DATA(pn, pfx, sfx)					\
-	PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0,			\
-		    PORT##pfx##_OUT, PORT##pfx##_IN)
-#define PINMUX_DATA_ALL()		CPU_ALL_PORT(_PORT_DATA, , unused)
-
-/*
- * PORT_ASSIGN_LAST() - Expand to an enum definition for the last PORT pin
- *
- * The largest PORT pin index is obtained by taking the size of a union,
- * containing one array per PORT pin, sized by the corresponding pin index.
- * As the fields in the CPU_ALL_PORT() macro definition are separated by
- * commas, while the members of a union must be terminated by semicolons, the
- * commas are absorbed by wrapping them inside dummy attributes.
- */
-#define _PORT_ENTRY(pn, pfx, sfx)					\
-	deprecated)); char pfx[pn] __attribute__((deprecated
-#define PORT_ASSIGN_LAST()						\
-	PORT_LAST = sizeof(union {					\
-		char dummy[0] __attribute__((deprecated,		\
-		CPU_ALL_PORT(_PORT_ENTRY, PORT, unused),		\
-		deprecated));						\
-	})
-
-/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
-#define PINMUX_GPIO_FN(gpio, base, data_or_mark)			\
-	[gpio - (base)] = {						\
-		.name = __stringify(gpio),				\
-		.enum_id = data_or_mark,				\
-	}
-#define GPIO_FN(str)							\
-	PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
-
-/*
- * Pins not associated with a GPIO port
- */
-
-#define PIN_NOGP_CFG(pin, name, fn, cfg)	fn(pin, name, cfg)
-#define PIN_NOGP(pin, name, fn)			fn(pin, name, 0)
-
-/* NOGP_ALL - Expand to a list of PIN_id */
-#define _NOGP_ALL(pin, name, cfg)		PIN_##pin
-#define NOGP_ALL()				CPU_ALL_NOGP(_NOGP_ALL)
-
-/* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */
-#define _NOGP_PINMUX(_pin, _name, cfg)					\
-	{								\
-		.pin = PIN_##_pin,					\
-		.name = "PIN_" _name,					\
-		.configs = SH_PFC_PIN_CFG_NO_GPIO | cfg,		\
-	}
-#define PINMUX_NOGP_ALL()		CPU_ALL_NOGP(_NOGP_PINMUX)
-
-/*
- * PORTnCR helper macro for SH-Mobile/R-Mobile
- */
-#define PORTCR(nr, reg)							\
-	{								\
-		PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8,		\
-				   GROUP(2, 2, 1, 3),			\
-				   GROUP(				\
-			/* PULMD[1:0], handled by .set_bias() */	\
-			0, 0, 0, 0,					\
-			/* IE and OE */					\
-			0, PORT##nr##_OUT, PORT##nr##_IN, 0,		\
-			/* SEC, not supported */			\
-			0, 0,						\
-			/* PTMD[2:0] */					\
-			PORT##nr##_FN0, PORT##nr##_FN1,			\
-			PORT##nr##_FN2, PORT##nr##_FN3,			\
-			PORT##nr##_FN4, PORT##nr##_FN5,			\
-			PORT##nr##_FN6, PORT##nr##_FN7			\
-		))							\
-	}
-
-/*
- * GPIO number helper macro for R-Car
- */
-#define RCAR_GP_PIN(bank, pin)		(((bank) * 32) + (pin))
-
-#endif /* __SH_PFC_H */