diff options
Diffstat (limited to 'drivers/scsi')
| -rw-r--r-- | drivers/scsi/device_handler/scsi_dh_rdac.c | 2 | ||||
| -rw-r--r-- | drivers/scsi/lpfc/lpfc_hw.h | 8 | ||||
| -rw-r--r-- | drivers/scsi/qla2xxx/qla_isr.c | 4 |
3 files changed, 7 insertions, 7 deletions
diff --git a/drivers/scsi/device_handler/scsi_dh_rdac.c b/drivers/scsi/device_handler/scsi_dh_rdac.c index e7fc70d6b478..2e7c136bb805 100644 --- a/drivers/scsi/device_handler/scsi_dh_rdac.c +++ b/drivers/scsi/device_handler/scsi_dh_rdac.c @@ -35,7 +35,7 @@ * mode page were taken from the LSI RDAC 2.4 GPL'd * driver, and then converted to Linux conventions. */ -#define RDAC_QUIESCENCE_TIME 20; +#define RDAC_QUIESCENCE_TIME 20 /* * Page Codes */ diff --git a/drivers/scsi/lpfc/lpfc_hw.h b/drivers/scsi/lpfc/lpfc_hw.h index 9059524cf225..ab4c4d651d0c 100644 --- a/drivers/scsi/lpfc/lpfc_hw.h +++ b/drivers/scsi/lpfc/lpfc_hw.h @@ -2955,18 +2955,18 @@ typedef struct _SLI2_RDSC { typedef struct _PCB { #ifdef __BIG_ENDIAN_BITFIELD uint32_t type:8; -#define TYPE_NATIVE_SLI2 0x01; +#define TYPE_NATIVE_SLI2 0x01 uint32_t feature:8; -#define FEATURE_INITIAL_SLI2 0x01; +#define FEATURE_INITIAL_SLI2 0x01 uint32_t rsvd:12; uint32_t maxRing:4; #else /* __LITTLE_ENDIAN_BITFIELD */ uint32_t maxRing:4; uint32_t rsvd:12; uint32_t feature:8; -#define FEATURE_INITIAL_SLI2 0x01; +#define FEATURE_INITIAL_SLI2 0x01 uint32_t type:8; -#define TYPE_NATIVE_SLI2 0x01; +#define TYPE_NATIVE_SLI2 0x01 #endif uint32_t mailBoxSize; diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c index 1b60a95adb50..ae8e298746ba 100644 --- a/drivers/scsi/qla2xxx/qla_isr.c +++ b/drivers/scsi/qla2xxx/qla_isr.c @@ -63,7 +63,7 @@ qla2100_intr_handler(int irq, void *dev_id) /* * Issue a "HARD" reset in order for the RISC interrupt - * bit to be cleared. Schedule a big hammmer to get + * bit to be cleared. Schedule a big hammer to get * out of the RISC PAUSED state. */ WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); @@ -169,7 +169,7 @@ qla2300_intr_handler(int irq, void *dev_id) /* * Issue a "HARD" reset in order for the RISC * interrupt bit to be cleared. Schedule a big - * hammmer to get out of the RISC PAUSED state. + * hammer to get out of the RISC PAUSED state. */ WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); RD_REG_WORD(®->hccr); |