diff options
Diffstat (limited to 'drivers/staging/ccree/ssi_driver.h')
| -rw-r--r-- | drivers/staging/ccree/ssi_driver.h | 84 |
1 files changed, 30 insertions, 54 deletions
diff --git a/drivers/staging/ccree/ssi_driver.h b/drivers/staging/ccree/ssi_driver.h index 891958b99634..c1ed61f1a202 100644 --- a/drivers/staging/ccree/ssi_driver.h +++ b/drivers/staging/ccree/ssi_driver.h @@ -1,21 +1,21 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ /* \file ssi_driver.h - ARM CryptoCell Linux Crypto Driver + * ARM CryptoCell Linux Crypto Driver */ #ifndef __SSI_DRIVER_H__ @@ -36,29 +36,27 @@ #include <crypto/authenc.h> #include <crypto/hash.h> #include <linux/version.h> - -#ifndef INT32_MAX /* Missing in Linux kernel */ -#define INT32_MAX 0x7FFFFFFFL -#endif +#include <linux/clk.h> /* Registers definitions from shared/hw/ree_include */ #include "dx_reg_base_host.h" #include "dx_host.h" -#define DX_CC_HOST_VIRT /* must be defined before including dx_cc_regs.h */ -#include "cc_hw_queue_defs.h" #include "cc_regs.h" #include "dx_reg_common.h" #include "cc_hal.h" -#include "ssi_sram_mgr.h" #define CC_SUPPORT_SHA DX_DEV_SHA_MAX #include "cc_crypto_ctx.h" #include "ssi_sysfs.h" #include "hash_defs.h" #include "ssi_fips_local.h" +#include "cc_hw_queue_defs.h" +#include "ssi_sram_mgr.h" #define DRV_MODULE_VERSION "3.0" #define SSI_DEV_NAME_STR "cc715ree" +#define CC_COHERENT_CACHE_PARAMS 0xEEE + #define SSI_CC_HAS_AES_CCM 1 #define SSI_CC_HAS_AES_GCM 1 #define SSI_CC_HAS_AES_XTS 1 @@ -89,12 +87,13 @@ /* Definitions for HW descriptors DIN/DOUT fields */ #define NS_BIT 1 #define AXI_ID 0 -/* AXI_ID is not actually the AXI ID of the transaction but the value of AXI_ID - field in the HW descriptor. The DMA engine +8 that value. */ +/* AXI_ID is not actually the AXI ID of the transaction but the value of AXI_ID + * field in the HW descriptor. The DMA engine +8 that value. + */ /* Logging macros */ #define SSI_LOG(level, format, ...) \ - printk(level "cc715ree::%s: " format , __func__, ##__VA_ARGS__) + printk(level "cc715ree::%s: " format, __func__, ##__VA_ARGS__) #define SSI_LOG_ERR(format, ...) SSI_LOG(KERN_ERR, format, ##__VA_ARGS__) #define SSI_LOG_WARNING(format, ...) SSI_LOG(KERN_WARNING, format, ##__VA_ARGS__) #define SSI_LOG_NOTICE(format, ...) SSI_LOG(KERN_NOTICE, format, ##__VA_ARGS__) @@ -108,21 +107,18 @@ #define MIN(a, b) (((a) < (b)) ? (a) : (b)) #define MAX(a, b) (((a) > (b)) ? (a) : (b)) -#define SSI_MAX_IVGEN_DMA_ADDRESSES 3 +#define SSI_MAX_IVGEN_DMA_ADDRESSES 3 struct ssi_crypto_req { void (*user_cb)(struct device *dev, void *req, void __iomem *cc_base); void *user_arg; - dma_addr_t ivgen_dma_addr[SSI_MAX_IVGEN_DMA_ADDRESSES]; /* For the first 'ivgen_dma_addr_len' addresses of this array, - generated IV would be placed in it by send_request(). - Same generated IV for all addresses! */ + dma_addr_t ivgen_dma_addr[SSI_MAX_IVGEN_DMA_ADDRESSES]; + /* For the first 'ivgen_dma_addr_len' addresses of this array, + * generated IV would be placed in it by send_request(). + * Same generated IV for all addresses! + */ unsigned int ivgen_dma_addr_len; /* Amount of 'ivgen_dma_addr' elements to be filled. */ unsigned int ivgen_size; /* The generated IV size required, 8/16 B allowed. */ struct completion seq_compl; /* request completion */ -#ifdef ENABLE_CYCLE_COUNT - enum stat_op op_type; - cycles_t submit_cycle; - bool is_monitored_p; -#endif }; /** @@ -136,15 +132,13 @@ struct ssi_drvdata { struct resource *res_mem; struct resource *res_irq; void __iomem *cc_base; -#ifdef DX_BASE_ENV_REGS - void __iomem *env_base; /* ARM CryptoCell development FPGAs only */ -#endif unsigned int irq; - uint32_t irq_mask; - uint32_t fw_ver; + u32 irq_mask; + u32 fw_ver; /* Calibration time of start/stop - * monitor descriptors */ - uint32_t monitor_null_cycles; + * monitor descriptors + */ + u32 monitor_null_cycles; struct platform_device *plat_dev; ssi_sram_addr_t mlli_sram_addr; struct completion icache_setup_completion; @@ -156,12 +150,9 @@ struct ssi_drvdata { void *fips_handle; void *ivgen_handle; void *sram_mgr_handle; - -#ifdef ENABLE_CYCLE_COUNT - cycles_t isr_exit_cycles; /* Save for isr-to-tasklet latency */ -#endif - uint32_t inflight_counter; - + u32 inflight_counter; + struct clk *clk; + bool coherent; }; struct ssi_crypto_alg { @@ -189,7 +180,6 @@ struct ssi_alg_template { int cipher_mode; int flow_mode; /* Note: currently, refers to the cipher mode only. */ int auth_mode; - bool synchronous; struct ssi_drvdata *drvdata; }; @@ -199,30 +189,16 @@ struct async_gen_req_ctx { }; #ifdef DX_DUMP_BYTES -void dump_byte_array(const char *name, const uint8_t *the_array, unsigned long size); +void dump_byte_array(const char *name, const u8 *the_array, unsigned long size); #else #define dump_byte_array(name, array, size) do { \ } while (0); #endif -#ifdef ENABLE_CYCLE_COUNT -#define DECL_CYCLE_COUNT_RESOURCES cycles_t _last_cycles_read -#define START_CYCLE_COUNT() do { _last_cycles_read = get_cycles(); } while (0) -#define END_CYCLE_COUNT(_stat_op_type, _stat_phase) update_host_stat(_stat_op_type, _stat_phase, get_cycles() - _last_cycles_read) -#define GET_START_CYCLE_COUNT() _last_cycles_read -#define START_CYCLE_COUNT_AT(_var) do { _var = get_cycles(); } while(0) -#define END_CYCLE_COUNT_AT(_var, _stat_op_type, _stat_phase) update_host_stat(_stat_op_type, _stat_phase, get_cycles() - _var) -#else -#define DECL_CYCLE_COUNT_RESOURCES -#define START_CYCLE_COUNT() do { } while (0) -#define END_CYCLE_COUNT(_stat_op_type, _stat_phase) do { } while (0) -#define GET_START_CYCLE_COUNT() 0 -#define START_CYCLE_COUNT_AT(_var) do { } while (0) -#define END_CYCLE_COUNT_AT(_var, _stat_op_type, _stat_phase) do { } while (0) -#endif /*ENABLE_CYCLE_COUNT*/ - int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe); void fini_cc_regs(struct ssi_drvdata *drvdata); +int cc_clk_on(struct ssi_drvdata *drvdata); +void cc_clk_off(struct ssi_drvdata *drvdata); #endif /*__SSI_DRIVER_H__*/ |