diff options
Diffstat (limited to 'drivers/staging/comedi/drivers/dmm32at.c')
| -rw-r--r-- | drivers/staging/comedi/drivers/dmm32at.c | 702 |
1 files changed, 274 insertions, 428 deletions
diff --git a/drivers/staging/comedi/drivers/dmm32at.c b/drivers/staging/comedi/drivers/dmm32at.c index 7215e09305cf..6df298a99cc6 100644 --- a/drivers/staging/comedi/drivers/dmm32at.c +++ b/drivers/staging/comedi/drivers/dmm32at.c @@ -1,125 +1,139 @@ /* - comedi/drivers/dmm32at.c - Diamond Systems mm32at code for a Comedi driver - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 2000 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * dmm32at.c + * Diamond Systems Diamond-MM-32-AT Comedi driver + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 2000 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + /* -Driver: dmm32at -Description: Diamond Systems mm32at driver. -Devices: -Author: Perry J. Piplani <perry.j.piplani@nasa.gov> -Updated: Fri Jun 4 09:13:24 CDT 2004 -Status: experimental - -This driver is for the Diamond Systems MM-32-AT board -http://www.diamondsystems.com/products/diamondmm32at It is being used -on serveral projects inside NASA, without problems so far. For analog -input commands, TRIG_EXT is not yet supported at all.. - -Configuration Options: - comedi_config /dev/comedi0 dmm32at baseaddr,irq -*/ + * Driver: dmm32at + * Description: Diamond Systems Diamond-MM-32-AT + * Devices: (Diamond Systems) Diamond-MM-32-AT [dmm32at] + * Author: Perry J. Piplani <perry.j.piplani@nasa.gov> + * Updated: Fri Jun 4 09:13:24 CDT 2004 + * Status: experimental + * + * Configuration Options: + * comedi_config /dev/comedi0 dmm32at baseaddr,irq + * + * This driver is for the Diamond Systems MM-32-AT board + * http://www.diamondsystems.com/products/diamondmm32at + * + * It is being used on serveral projects inside NASA, without + * problems so far. For analog input commands, TRIG_EXT is not + * yet supported. + */ #include <linux/module.h> #include <linux/delay.h> #include <linux/interrupt.h> #include "../comedidev.h" +#include "8255.h" #include "comedi_fc.h" /* Board register addresses */ -#define DMM32AT_CONV 0x00 -#define DMM32AT_AILSB 0x00 -#define DMM32AT_AUXDOUT 0x01 -#define DMM32AT_AIMSB 0x01 -#define DMM32AT_AILOW 0x02 -#define DMM32AT_AIHIGH 0x03 - -#define DMM32AT_DACSTAT 0x04 -#define DMM32AT_DACLSB_REG 0x04 -#define DMM32AT_DACMSB_REG 0x05 -#define DMM32AT_DACMSB_CHAN(x) ((x) << 6) - -#define DMM32AT_FIFOCNTRL 0x07 -#define DMM32AT_FIFOSTAT 0x07 - -#define DMM32AT_CNTRL 0x08 -#define DMM32AT_AISTAT 0x08 - -#define DMM32AT_INTCLOCK 0x09 - -#define DMM32AT_CNTRDIO 0x0a - -#define DMM32AT_AICONF 0x0b -#define DMM32AT_AIRBACK 0x0b +#define DMM32AT_AI_START_CONV_REG 0x00 +#define DMM32AT_AI_LSB_REG 0x00 +#define DMM32AT_AUX_DOUT_REG 0x01 +#define DMM32AT_AUX_DOUT2 (1 << 2) /* J3.42 - OUT2 (OUT2EN) */ +#define DMM32AT_AUX_DOUT1 (1 << 1) /* J3.43 */ +#define DMM32AT_AUX_DOUT0 (1 << 0) /* J3.44 - OUT0 (OUT0EN) */ +#define DMM32AT_AI_MSB_REG 0x01 +#define DMM32AT_AI_LO_CHAN_REG 0x02 +#define DMM32AT_AI_HI_CHAN_REG 0x03 +#define DMM32AT_AUX_DI_REG 0x04 +#define DMM32AT_AUX_DI_DACBUSY (1 << 7) +#define DMM32AT_AUX_DI_CALBUSY (1 << 6) +#define DMM32AT_AUX_DI3 (1 << 3) /* J3.45 - ADCLK (CLKSEL) */ +#define DMM32AT_AUX_DI2 (1 << 2) /* J3.46 - GATE12 (GT12EN) */ +#define DMM32AT_AUX_DI1 (1 << 1) /* J3.47 - GATE0 (GT0EN) */ +#define DMM32AT_AUX_DI0 (1 << 0) /* J3.48 - CLK0 (SRC0) */ +#define DMM32AT_AO_LSB_REG 0x04 +#define DMM32AT_AO_MSB_REG 0x05 +#define DMM32AT_AO_MSB_DACH(x) ((x) << 6) +#define DMM32AT_FIFO_DEPTH_REG 0x06 +#define DMM32AT_FIFO_CTRL_REG 0x07 +#define DMM32AT_FIFO_CTRL_FIFOEN (1 << 3) +#define DMM32AT_FIFO_CTRL_SCANEN (1 << 2) +#define DMM32AT_FIFO_CTRL_FIFORST (1 << 1) +#define DMM32AT_FIFO_STATUS_REG 0x07 +#define DMM32AT_FIFO_STATUS_EF (1 << 7) +#define DMM32AT_FIFO_STATUS_HF (1 << 6) +#define DMM32AT_FIFO_STATUS_FF (1 << 5) +#define DMM32AT_FIFO_STATUS_OVF (1 << 4) +#define DMM32AT_FIFO_STATUS_FIFOEN (1 << 3) +#define DMM32AT_FIFO_STATUS_SCANEN (1 << 2) +#define DMM32AT_FIFO_STATUS_PAGE_MASK (3 << 0) +#define DMM32AT_CTRL_REG 0x08 +#define DMM32AT_CTRL_RESETA (1 << 5) +#define DMM32AT_CTRL_RESETD (1 << 4) +#define DMM32AT_CTRL_INTRST (1 << 3) +#define DMM32AT_CTRL_PAGE_8254 (0 << 0) +#define DMM32AT_CTRL_PAGE_8255 (1 << 0) +#define DMM32AT_CTRL_PAGE_CALIB (3 << 0) +#define DMM32AT_AI_STATUS_REG 0x08 +#define DMM32AT_AI_STATUS_STS (1 << 7) +#define DMM32AT_AI_STATUS_SD1 (1 << 6) +#define DMM32AT_AI_STATUS_SD0 (1 << 5) +#define DMM32AT_AI_STATUS_ADCH_MASK (0x1f << 0) +#define DMM32AT_INTCLK_REG 0x09 +#define DMM32AT_INTCLK_ADINT (1 << 7) +#define DMM32AT_INTCLK_DINT (1 << 6) +#define DMM32AT_INTCLK_TINT (1 << 5) +#define DMM32AT_INTCLK_CLKEN (1 << 1) /* 1=see below 0=software */ +#define DMM32AT_INTCLK_CLKSEL (1 << 0) /* 1=OUT2 0=EXTCLK */ +#define DMM32AT_CTRDIO_CFG_REG 0x0a +#define DMM32AT_CTRDIO_CFG_FREQ12 (1 << 7) /* CLK12 1=100KHz 0=10MHz */ +#define DMM32AT_CTRDIO_CFG_FREQ0 (1 << 6) /* CLK0 1=10KHz 0=10MHz */ +#define DMM32AT_CTRDIO_CFG_OUT2EN (1 << 5) /* J3.42 1=OUT2 is DOUT2 */ +#define DMM32AT_CTRDIO_CFG_OUT0EN (1 << 4) /* J3,44 1=OUT0 is DOUT0 */ +#define DMM32AT_CTRDIO_CFG_GT0EN (1 << 2) /* J3.47 1=DIN1 is GATE0 */ +#define DMM32AT_CTRDIO_CFG_SRC0 (1 << 1) /* CLK0 is 0=FREQ0 1=J3.48 */ +#define DMM32AT_CTRDIO_CFG_GT12EN (1 << 0) /* J3.46 1=DIN2 is GATE12 */ +#define DMM32AT_AI_CFG_REG 0x0b +#define DMM32AT_AI_CFG_SCINT_20US (0 << 4) +#define DMM32AT_AI_CFG_SCINT_15US (1 << 4) +#define DMM32AT_AI_CFG_SCINT_10US (2 << 4) +#define DMM32AT_AI_CFG_SCINT_5US (3 << 4) +#define DMM32AT_AI_CFG_RANGE (1 << 3) /* 0=5V 1=10V */ +#define DMM32AT_AI_CFG_ADBU (1 << 2) /* 0=bipolar 1=unipolar */ +#define DMM32AT_AI_CFG_GAIN(x) ((x) << 0) +#define DMM32AT_AI_READBACK_REG 0x0b +#define DMM32AT_AI_READBACK_WAIT (1 << 7) /* DMM32AT_AI_STATUS_STS */ +#define DMM32AT_AI_READBACK_RANGE (1 << 3) +#define DMM32AT_AI_READBACK_ADBU (1 << 2) +#define DMM32AT_AI_READBACK_GAIN_MASK (3 << 0) #define DMM32AT_CLK1 0x0d #define DMM32AT_CLK2 0x0e #define DMM32AT_CLKCT 0x0f -#define DMM32AT_DIOA 0x0c -#define DMM32AT_DIOB 0x0d -#define DMM32AT_DIOC 0x0e -#define DMM32AT_DIOCONF 0x0f +#define DMM32AT_8255_IOBASE 0x0c /* Page 1 registers */ /* Board register values. */ -/* DMM32AT_DACSTAT 0x04 */ -#define DMM32AT_DACBUSY 0x80 - -/* DMM32AT_FIFOCNTRL 0x07 */ -#define DMM32AT_FIFORESET 0x02 -#define DMM32AT_SCANENABLE 0x04 - -/* DMM32AT_CNTRL 0x08 */ -#define DMM32AT_RESET 0x20 -#define DMM32AT_INTRESET 0x08 -#define DMM32AT_CLKACC 0x00 -#define DMM32AT_DIOACC 0x01 - -/* DMM32AT_AISTAT 0x08 */ -#define DMM32AT_STATUS 0x80 - -/* DMM32AT_INTCLOCK 0x09 */ -#define DMM32AT_ADINT 0x80 -#define DMM32AT_CLKSEL 0x03 - -/* DMM32AT_CNTRDIO 0x0a */ -#define DMM32AT_FREQ12 0x80 - -/* DMM32AT_AICONF 0x0b */ +/* DMM32AT_AI_CFG_REG 0x0b */ #define DMM32AT_RANGE_U10 0x0c #define DMM32AT_RANGE_U5 0x0d #define DMM32AT_RANGE_B10 0x08 #define DMM32AT_RANGE_B5 0x00 -#define DMM32AT_SCINT_20 0x00 -#define DMM32AT_SCINT_15 0x10 -#define DMM32AT_SCINT_10 0x20 -#define DMM32AT_SCINT_5 0x30 /* DMM32AT_CLKCT 0x0f */ #define DMM32AT_CLKCT1 0x56 /* mode3 counter 1 - write low byte only */ #define DMM32AT_CLKCT2 0xb6 /* mode3 counter 2 - write high and low byte */ -/* DMM32AT_DIOCONF 0x0f */ -#define DMM32AT_DIENABLE 0x80 -#define DMM32AT_DIRA 0x10 -#define DMM32AT_DIRB 0x02 -#define DMM32AT_DIRCL 0x01 -#define DMM32AT_DIRCH 0x08 - /* board AI ranges in comedi structure */ static const struct comedi_lrange dmm32at_airanges = { 4, { @@ -150,12 +164,36 @@ static const struct comedi_lrange dmm32at_aoranges = { } }; -struct dmm32at_private { - int data; - int ai_inuse; - unsigned int ai_scans_left; - unsigned char dio_config; -}; +static void dmm32at_ai_set_chanspec(struct comedi_device *dev, + struct comedi_subdevice *s, + unsigned int chanspec, int nchan) +{ + unsigned int chan = CR_CHAN(chanspec); + unsigned int range = CR_RANGE(chanspec); + unsigned int last_chan = (chan + nchan - 1) % s->n_chan; + + outb(DMM32AT_FIFO_CTRL_FIFORST, dev->iobase + DMM32AT_FIFO_CTRL_REG); + + if (nchan > 1) + outb(DMM32AT_FIFO_CTRL_SCANEN, + dev->iobase + DMM32AT_FIFO_CTRL_REG); + + outb(chan, dev->iobase + DMM32AT_AI_LO_CHAN_REG); + outb(last_chan, dev->iobase + DMM32AT_AI_HI_CHAN_REG); + outb(dmm32at_rangebits[range], dev->iobase + DMM32AT_AI_CFG_REG); +} + +static unsigned int dmm32at_ai_get_sample(struct comedi_device *dev, + struct comedi_subdevice *s) +{ + unsigned int val; + + val = inb(dev->iobase + DMM32AT_AI_LSB_REG); + val |= (inb(dev->iobase + DMM32AT_AI_MSB_REG) << 8); + + /* munge two's complement value to offset binary */ + return comedi_offset_munge(s, val); +} static int dmm32at_ai_status(struct comedi_device *dev, struct comedi_subdevice *s, @@ -165,75 +203,39 @@ static int dmm32at_ai_status(struct comedi_device *dev, unsigned char status; status = inb(dev->iobase + context); - if ((status & DMM32AT_STATUS) == 0) + if ((status & DMM32AT_AI_STATUS_STS) == 0) return 0; return -EBUSY; } -static int dmm32at_ai_rinsn(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) +static int dmm32at_ai_insn_read(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) { - int n; - unsigned int d; - unsigned short msb, lsb; - unsigned char chan; - int range; int ret; + int i; - /* get the channel and range number */ - - chan = CR_CHAN(insn->chanspec) & (s->n_chan - 1); - range = CR_RANGE(insn->chanspec); - - /* zero scan and fifo control and reset fifo */ - outb(DMM32AT_FIFORESET, dev->iobase + DMM32AT_FIFOCNTRL); - - /* write the ai channel range regs */ - outb(chan, dev->iobase + DMM32AT_AILOW); - outb(chan, dev->iobase + DMM32AT_AIHIGH); - /* set the range bits */ - outb(dmm32at_rangebits[range], dev->iobase + DMM32AT_AICONF); + dmm32at_ai_set_chanspec(dev, s, insn->chanspec, 1); /* wait for circuit to settle */ - ret = comedi_timeout(dev, s, insn, dmm32at_ai_status, DMM32AT_AIRBACK); + ret = comedi_timeout(dev, s, insn, dmm32at_ai_status, + DMM32AT_AI_READBACK_REG); if (ret) return ret; - /* convert n samples */ - for (n = 0; n < insn->n; n++) { - /* trigger conversion */ - outb(0xff, dev->iobase + DMM32AT_CONV); + for (i = 0; i < insn->n; i++) { + outb(0xff, dev->iobase + DMM32AT_AI_START_CONV_REG); - /* wait for conversion to end */ ret = comedi_timeout(dev, s, insn, dmm32at_ai_status, - DMM32AT_AISTAT); + DMM32AT_AI_STATUS_REG); if (ret) return ret; - /* read data */ - lsb = inb(dev->iobase + DMM32AT_AILSB); - msb = inb(dev->iobase + DMM32AT_AIMSB); - - /* invert sign bit to make range unsigned, this is an - idiosyncrasy of the diamond board, it return - conversions as a signed value, i.e. -32768 to - 32767, flipping the bit and interpreting it as - signed gives you a range of 0 to 65535 which is - used by comedi */ - d = ((msb ^ 0x0080) << 8) + lsb; - - data[n] = d; + data[i] = dmm32at_ai_get_sample(dev, s); } - /* return the number of samples read/written */ - return n; -} - -static int dmm32at_ns_to_timer(unsigned int *ns, unsigned int flags) -{ - /* trivial timer */ - return *ns; + return insn->n; } static int dmm32at_ai_check_chanlist(struct comedi_device *dev, @@ -273,10 +275,8 @@ static int dmm32at_ai_cmdtest(struct comedi_device *dev, /* Step 1 : check if triggers are trivially valid */ err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW); - err |= cfc_check_trigger_src(&cmd->scan_begin_src, - TRIG_TIMER /*| TRIG_EXT */); - err |= cfc_check_trigger_src(&cmd->convert_src, - TRIG_TIMER /*| TRIG_EXT */); + err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_TIMER); + err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER); err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); @@ -285,8 +285,6 @@ static int dmm32at_ai_cmdtest(struct comedi_device *dev, /* Step 2a : make sure trigger sources are unique */ - err |= cfc_check_trigger_is_unique(cmd->scan_begin_src); - err |= cfc_check_trigger_is_unique(cmd->convert_src); err |= cfc_check_trigger_is_unique(cmd->stop_src); /* Step 2b : and mutually compatible */ @@ -298,67 +296,32 @@ static int dmm32at_ai_cmdtest(struct comedi_device *dev, err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0); -#define MAX_SCAN_SPEED 1000000 /* in nanoseconds */ -#define MIN_SCAN_SPEED 1000000000 /* in nanoseconds */ - - if (cmd->scan_begin_src == TRIG_TIMER) { - err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, - MAX_SCAN_SPEED); - err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, - MIN_SCAN_SPEED); - } else { - /* external trigger */ - /* should be level/edge, hi/lo specification here */ - /* should specify multiple external triggers */ - err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9); - } + err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, 1000000); + err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 1000000000); - if (cmd->convert_src == TRIG_TIMER) { - if (cmd->convert_arg >= 17500) - cmd->convert_arg = 20000; - else if (cmd->convert_arg >= 12500) - cmd->convert_arg = 15000; - else if (cmd->convert_arg >= 7500) - cmd->convert_arg = 10000; - else - cmd->convert_arg = 5000; - } else { - /* external trigger */ - /* see above */ - err |= cfc_check_trigger_arg_max(&cmd->convert_arg, 9); - } + if (cmd->convert_arg >= 17500) + cmd->convert_arg = 20000; + else if (cmd->convert_arg >= 12500) + cmd->convert_arg = 15000; + else if (cmd->convert_arg >= 7500) + cmd->convert_arg = 10000; + else + cmd->convert_arg = 5000; err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len); - if (cmd->stop_src == TRIG_COUNT) { - err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0xfffffff0); + if (cmd->stop_src == TRIG_COUNT) err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1); - } else { - /* TRIG_NONE */ + else /* TRIG_NONE */ err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0); - } if (err) return 3; - /* step 4: fix up any arguments */ + /* Step 4: fix up any arguments */ - if (cmd->scan_begin_src == TRIG_TIMER) { - arg = cmd->scan_begin_arg; - dmm32at_ns_to_timer(&arg, cmd->flags); - err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, arg); - } - if (cmd->convert_src == TRIG_TIMER) { - arg = cmd->convert_arg; - dmm32at_ns_to_timer(&arg, cmd->flags); - err |= cfc_check_trigger_arg_is(&cmd->convert_arg, arg); - - if (cmd->scan_begin_src == TRIG_TIMER) { - arg = cmd->convert_arg * cmd->scan_end_arg; - err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, - arg); - } - } + arg = cmd->convert_arg * cmd->scan_end_arg; + err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, arg); if (err) return 4; @@ -384,11 +347,11 @@ static void dmm32at_setaitimer(struct comedi_device *dev, unsigned int nansec) hi2 = (both2 & 0xff00) >> 8; lo2 = both2 & 0x00ff; - /* set the counter frequency to 10mhz */ - outb(0, dev->iobase + DMM32AT_CNTRDIO); + /* set counter clocks to 10MHz, disable all aux dio */ + outb(0, dev->iobase + DMM32AT_CTRDIO_CFG_REG); /* get access to the clock regs */ - outb(DMM32AT_CLKACC, dev->iobase + DMM32AT_CNTRL); + outb(DMM32AT_CTRL_PAGE_8254, dev->iobase + DMM32AT_CTRL_REG); /* write the counter 1 control word and low byte to counter */ outb(DMM32AT_CLKCT1, dev->iobase + DMM32AT_CLKCT); @@ -400,65 +363,37 @@ static void dmm32at_setaitimer(struct comedi_device *dev, unsigned int nansec) outb(hi2, dev->iobase + DMM32AT_CLK2); /* enable the ai conversion interrupt and the clock to start scans */ - outb(DMM32AT_ADINT | DMM32AT_CLKSEL, dev->iobase + DMM32AT_INTCLOCK); + outb(DMM32AT_INTCLK_ADINT | + DMM32AT_INTCLK_CLKEN | DMM32AT_INTCLK_CLKSEL, + dev->iobase + DMM32AT_INTCLK_REG); } static int dmm32at_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) { - struct dmm32at_private *devpriv = dev->private; struct comedi_cmd *cmd = &s->async->cmd; - int range; - unsigned char chanlo, chanhi; int ret; - if (!cmd->chanlist) - return -EINVAL; - - /* get the channel list and range */ - chanlo = CR_CHAN(cmd->chanlist[0]) & (s->n_chan - 1); - chanhi = chanlo + cmd->chanlist_len - 1; - if (chanhi >= s->n_chan) - return -EINVAL; - range = CR_RANGE(cmd->chanlist[0]); - - /* reset fifo */ - outb(DMM32AT_FIFORESET, dev->iobase + DMM32AT_FIFOCNTRL); - - /* set scan enable */ - outb(DMM32AT_SCANENABLE, dev->iobase + DMM32AT_FIFOCNTRL); - - /* write the ai channel range regs */ - outb(chanlo, dev->iobase + DMM32AT_AILOW); - outb(chanhi, dev->iobase + DMM32AT_AIHIGH); - - /* set the range bits */ - outb(dmm32at_rangebits[range], dev->iobase + DMM32AT_AICONF); + dmm32at_ai_set_chanspec(dev, s, cmd->chanlist[0], cmd->chanlist_len); /* reset the interrupt just in case */ - outb(DMM32AT_INTRESET, dev->iobase + DMM32AT_CNTRL); - - if (cmd->stop_src == TRIG_COUNT) - devpriv->ai_scans_left = cmd->stop_arg; - else { /* TRIG_NONE */ - devpriv->ai_scans_left = 0xffffffff; /* indicates TRIG_NONE to - * isr */ - } + outb(DMM32AT_CTRL_INTRST, dev->iobase + DMM32AT_CTRL_REG); /* * wait for circuit to settle * we don't have the 'insn' here but it's not needed */ - ret = comedi_timeout(dev, s, NULL, dmm32at_ai_status, DMM32AT_AIRBACK); + ret = comedi_timeout(dev, s, NULL, dmm32at_ai_status, + DMM32AT_AI_READBACK_REG); if (ret) return ret; - if (devpriv->ai_scans_left > 1) { + if (cmd->stop_src == TRIG_NONE || cmd->stop_arg > 1) { /* start the clock and enable the interrupts */ dmm32at_setaitimer(dev, cmd->scan_begin_arg); } else { /* start the interrups and initiate a single scan */ - outb(DMM32AT_ADINT, dev->iobase + DMM32AT_INTCLOCK); - outb(0xff, dev->iobase + DMM32AT_CONV); + outb(DMM32AT_INTCLK_ADINT, dev->iobase + DMM32AT_INTCLK_REG); + outb(0xff, dev->iobase + DMM32AT_AI_START_CONV_REG); } return 0; @@ -468,19 +403,16 @@ static int dmm32at_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) static int dmm32at_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s) { - struct dmm32at_private *devpriv = dev->private; - - devpriv->ai_scans_left = 1; + /* disable further interrupts and clocks */ + outb(0x0, dev->iobase + DMM32AT_INTCLK_REG); return 0; } static irqreturn_t dmm32at_isr(int irq, void *d) { struct comedi_device *dev = d; - struct dmm32at_private *devpriv = dev->private; unsigned char intstat; - unsigned int samp; - unsigned short msb, lsb; + unsigned int val; int i; if (!dev->attached) { @@ -488,38 +420,26 @@ static irqreturn_t dmm32at_isr(int irq, void *d) return IRQ_HANDLED; } - intstat = inb(dev->iobase + DMM32AT_INTCLOCK); + intstat = inb(dev->iobase + DMM32AT_INTCLK_REG); - if (intstat & DMM32AT_ADINT) { + if (intstat & DMM32AT_INTCLK_ADINT) { struct comedi_subdevice *s = dev->read_subdev; struct comedi_cmd *cmd = &s->async->cmd; for (i = 0; i < cmd->chanlist_len; i++) { - /* read data */ - lsb = inb(dev->iobase + DMM32AT_AILSB); - msb = inb(dev->iobase + DMM32AT_AIMSB); - - /* invert sign bit to make range unsigned */ - samp = ((msb ^ 0x0080) << 8) + lsb; - comedi_buf_put(s, samp); + val = dmm32at_ai_get_sample(dev, s); + comedi_buf_write_samples(s, &val, 1); } - if (devpriv->ai_scans_left != 0xffffffff) { /* TRIG_COUNT */ - devpriv->ai_scans_left--; - if (devpriv->ai_scans_left == 0) { - /* disable further interrupts and clocks */ - outb(0x0, dev->iobase + DMM32AT_INTCLOCK); - /* set the buffer to be flushed with an EOF */ - s->async->events |= COMEDI_CB_EOA; - } + if (cmd->stop_src == TRIG_COUNT && + s->async->scans_done >= cmd->stop_arg) + s->async->events |= COMEDI_CB_EOA; - } - /* flush the buffer */ - comedi_event(dev, s); + comedi_handle_events(dev, s); } /* reset the interrupt */ - outb(DMM32AT_INTRESET, dev->iobase + DMM32AT_CNTRL); + outb(DMM32AT_CTRL_INTRST, dev->iobase + DMM32AT_CTRL_REG); return IRQ_HANDLED; } @@ -530,8 +450,8 @@ static int dmm32at_ao_eoc(struct comedi_device *dev, { unsigned char status; - status = inb(dev->iobase + DMM32AT_DACSTAT); - if ((status & DMM32AT_DACBUSY) == 0) + status = inb(dev->iobase + DMM32AT_AUX_DI_REG); + if ((status & DMM32AT_AUX_DI_DACBUSY) == 0) return 0; return -EBUSY; } @@ -549,9 +469,9 @@ static int dmm32at_ao_insn_write(struct comedi_device *dev, int ret; /* write LSB then MSB + chan to load DAC */ - outb(val & 0xff, dev->iobase + DMM32AT_DACLSB_REG); - outb((val >> 8) | DMM32AT_DACMSB_CHAN(chan), - dev->iobase + DMM32AT_DACMSB_REG); + outb(val & 0xff, dev->iobase + DMM32AT_AO_LSB_REG); + outb((val >> 8) | DMM32AT_AO_MSB_DACH(chan), + dev->iobase + DMM32AT_AO_MSB_REG); /* wait for circuit to settle */ ret = comedi_timeout(dev, s, insn, dmm32at_ao_eoc, 0); @@ -559,7 +479,7 @@ static int dmm32at_ao_insn_write(struct comedi_device *dev, return ret; /* dummy read to update DAC */ - inb(dev->iobase + DMM32AT_DACMSB_REG); + inb(dev->iobase + DMM32AT_AO_MSB_REG); s->readback[chan] = val; } @@ -567,136 +487,82 @@ static int dmm32at_ao_insn_write(struct comedi_device *dev, return insn->n; } -static int dmm32at_dio_insn_bits(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, - unsigned int *data) -{ - struct dmm32at_private *devpriv = dev->private; - unsigned int mask; - unsigned int val; - - mask = comedi_dio_update_state(s, data); - if (mask) { - /* get access to the DIO regs */ - outb(DMM32AT_DIOACC, dev->iobase + DMM32AT_CNTRL); - - /* if either part of dio is set for output */ - if (((devpriv->dio_config & DMM32AT_DIRCL) == 0) || - ((devpriv->dio_config & DMM32AT_DIRCH) == 0)) { - val = (s->state & 0x00ff0000) >> 16; - outb(val, dev->iobase + DMM32AT_DIOC); - } - if ((devpriv->dio_config & DMM32AT_DIRB) == 0) { - val = (s->state & 0x0000ff00) >> 8; - outb(val, dev->iobase + DMM32AT_DIOB); - } - if ((devpriv->dio_config & DMM32AT_DIRA) == 0) { - val = (s->state & 0x000000ff); - outb(val, dev->iobase + DMM32AT_DIOA); - } - } - - val = inb(dev->iobase + DMM32AT_DIOA); - val |= inb(dev->iobase + DMM32AT_DIOB) << 8; - val |= inb(dev->iobase + DMM32AT_DIOC) << 16; - s->state = val; - - data[1] = val; - - return insn->n; -} - -static int dmm32at_dio_insn_config(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, - unsigned int *data) +static int dmm32at_8255_io(struct comedi_device *dev, + int dir, int port, int data, unsigned long regbase) { - struct dmm32at_private *devpriv = dev->private; - unsigned int chan = CR_CHAN(insn->chanspec); - unsigned int mask; - unsigned char chanbit; - int ret; - - if (chan < 8) { - mask = 0x0000ff; - chanbit = DMM32AT_DIRA; - } else if (chan < 16) { - mask = 0x00ff00; - chanbit = DMM32AT_DIRB; - } else if (chan < 20) { - mask = 0x0f0000; - chanbit = DMM32AT_DIRCL; - } else { - mask = 0xf00000; - chanbit = DMM32AT_DIRCH; - } - - ret = comedi_dio_insn_config(dev, s, insn, data, mask); - if (ret) - return ret; - - if (data[0] == INSN_CONFIG_DIO_OUTPUT) - devpriv->dio_config &= ~chanbit; - else - devpriv->dio_config |= chanbit; /* get access to the DIO regs */ - outb(DMM32AT_DIOACC, dev->iobase + DMM32AT_CNTRL); - /* set the DIO's to the new configuration setting */ - outb(devpriv->dio_config, dev->iobase + DMM32AT_DIOCONF); + outb(DMM32AT_CTRL_PAGE_8255, dev->iobase + DMM32AT_CTRL_REG); - return insn->n; + if (dir) { + outb(data, dev->iobase + regbase + port); + return 0; + } + return inb(dev->iobase + regbase + port); } -static int dmm32at_attach(struct comedi_device *dev, - struct comedi_devconfig *it) +/* Make sure the board is there and put it to a known state */ +static int dmm32at_reset(struct comedi_device *dev) { - struct dmm32at_private *devpriv; - int ret; - struct comedi_subdevice *s; unsigned char aihi, ailo, fifostat, aistat, intstat, airback; - ret = comedi_request_region(dev, it->options[0], 0x10); - if (ret) - return ret; - - /* the following just makes sure the board is there and gets - it to a known state */ - /* reset the board */ - outb(DMM32AT_RESET, dev->iobase + DMM32AT_CNTRL); + outb(DMM32AT_CTRL_RESETA, dev->iobase + DMM32AT_CTRL_REG); /* allow a millisecond to reset */ udelay(1000); /* zero scan and fifo control */ - outb(0x0, dev->iobase + DMM32AT_FIFOCNTRL); + outb(0x0, dev->iobase + DMM32AT_FIFO_CTRL_REG); /* zero interrupt and clock control */ - outb(0x0, dev->iobase + DMM32AT_INTCLOCK); + outb(0x0, dev->iobase + DMM32AT_INTCLK_REG); /* write a test channel range, the high 3 bits should drop */ - outb(0x80, dev->iobase + DMM32AT_AILOW); - outb(0xff, dev->iobase + DMM32AT_AIHIGH); + outb(0x80, dev->iobase + DMM32AT_AI_LO_CHAN_REG); + outb(0xff, dev->iobase + DMM32AT_AI_HI_CHAN_REG); /* set the range at 10v unipolar */ - outb(DMM32AT_RANGE_U10, dev->iobase + DMM32AT_AICONF); + outb(DMM32AT_RANGE_U10, dev->iobase + DMM32AT_AI_CFG_REG); /* should take 10 us to settle, here's a hundred */ udelay(100); /* read back the values */ - ailo = inb(dev->iobase + DMM32AT_AILOW); - aihi = inb(dev->iobase + DMM32AT_AIHIGH); - fifostat = inb(dev->iobase + DMM32AT_FIFOSTAT); - aistat = inb(dev->iobase + DMM32AT_AISTAT); - intstat = inb(dev->iobase + DMM32AT_INTCLOCK); - airback = inb(dev->iobase + DMM32AT_AIRBACK); - - if ((ailo != 0x00) || (aihi != 0x1f) || (fifostat != 0x80) || - (aistat != 0x60 || (intstat != 0x00) || airback != 0x0c)) { - dev_err(dev->class_dev, "board detection failed\n"); + ailo = inb(dev->iobase + DMM32AT_AI_LO_CHAN_REG); + aihi = inb(dev->iobase + DMM32AT_AI_HI_CHAN_REG); + fifostat = inb(dev->iobase + DMM32AT_FIFO_STATUS_REG); + aistat = inb(dev->iobase + DMM32AT_AI_STATUS_REG); + intstat = inb(dev->iobase + DMM32AT_INTCLK_REG); + airback = inb(dev->iobase + DMM32AT_AI_READBACK_REG); + + /* + * NOTE: The (DMM32AT_AI_STATUS_SD1 | DMM32AT_AI_STATUS_SD0) + * test makes this driver only work if the board is configured + * with all A/D channels set for single-ended operation. + */ + if (ailo != 0x00 || aihi != 0x1f || + fifostat != DMM32AT_FIFO_STATUS_EF || + aistat != (DMM32AT_AI_STATUS_SD1 | DMM32AT_AI_STATUS_SD0) || + intstat != 0x00 || airback != 0x0c) return -EIO; + + return 0; +} + +static int dmm32at_attach(struct comedi_device *dev, + struct comedi_devconfig *it) +{ + struct comedi_subdevice *s; + int ret; + + ret = comedi_request_region(dev, it->options[0], 0x10); + if (ret) + return ret; + + ret = dmm32at_reset(dev); + if (ret) { + dev_err(dev->class_dev, "board detection failed\n"); + return ret; } if (it->options[1]) { @@ -706,65 +572,45 @@ static int dmm32at_attach(struct comedi_device *dev, dev->irq = it->options[1]; } - devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); - if (!devpriv) - return -ENOMEM; - ret = comedi_alloc_subdevices(dev, 3); if (ret) return ret; + /* Analog Input subdevice */ s = &dev->subdevices[0]; - /* analog input subdevice */ - s->type = COMEDI_SUBD_AI; - /* we support single-ended (ground) and differential */ - s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DIFF; - s->n_chan = 32; - s->maxdata = 0xffff; - s->range_table = &dmm32at_airanges; - s->insn_read = dmm32at_ai_rinsn; + s->type = COMEDI_SUBD_AI; + s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DIFF; + s->n_chan = 32; + s->maxdata = 0xffff; + s->range_table = &dmm32at_airanges; + s->insn_read = dmm32at_ai_insn_read; if (dev->irq) { dev->read_subdev = s; - s->subdev_flags |= SDF_CMD_READ; - s->len_chanlist = 32; - s->do_cmd = dmm32at_ai_cmd; - s->do_cmdtest = dmm32at_ai_cmdtest; - s->cancel = dmm32at_ai_cancel; + s->subdev_flags |= SDF_CMD_READ; + s->len_chanlist = s->n_chan; + s->do_cmd = dmm32at_ai_cmd; + s->do_cmdtest = dmm32at_ai_cmdtest; + s->cancel = dmm32at_ai_cancel; } + /* Analog Output subdevice */ s = &dev->subdevices[1]; - /* analog output subdevice */ - s->type = COMEDI_SUBD_AO; - s->subdev_flags = SDF_WRITABLE; - s->n_chan = 4; - s->maxdata = 0x0fff; - s->range_table = &dmm32at_aoranges; - s->insn_write = dmm32at_ao_insn_write; - s->insn_read = comedi_readback_insn_read; + s->type = COMEDI_SUBD_AO; + s->subdev_flags = SDF_WRITABLE; + s->n_chan = 4; + s->maxdata = 0x0fff; + s->range_table = &dmm32at_aoranges; + s->insn_write = dmm32at_ao_insn_write; ret = comedi_alloc_subdev_readback(s); if (ret) return ret; + /* Digital I/O subdevice */ s = &dev->subdevices[2]; - /* digital i/o subdevice */ - - /* get access to the DIO regs */ - outb(DMM32AT_DIOACC, dev->iobase + DMM32AT_CNTRL); - /* set the DIO's to the defualt input setting */ - devpriv->dio_config = DMM32AT_DIRA | DMM32AT_DIRB | - DMM32AT_DIRCL | DMM32AT_DIRCH | DMM32AT_DIENABLE; - outb(devpriv->dio_config, dev->iobase + DMM32AT_DIOCONF); - - /* set up the subdevice */ - s->type = COMEDI_SUBD_DIO; - s->subdev_flags = SDF_READABLE | SDF_WRITABLE; - s->n_chan = 24; - s->maxdata = 1; - s->state = 0; - s->range_table = &range_digital; - s->insn_bits = dmm32at_dio_insn_bits; - s->insn_config = dmm32at_dio_insn_config; + ret = subdev_8255_init(dev, s, dmm32at_8255_io, DMM32AT_8255_IOBASE); + if (ret) + return ret; return 0; } @@ -778,5 +624,5 @@ static struct comedi_driver dmm32at_driver = { module_comedi_driver(dmm32at_driver); MODULE_AUTHOR("Comedi http://www.comedi.org"); -MODULE_DESCRIPTION("Comedi low-level driver"); +MODULE_DESCRIPTION("Comedi: Diamond Systems Diamond-MM-32-AT"); MODULE_LICENSE("GPL"); |