diff options
Diffstat (limited to 'drivers/staging/comedi/drivers/plx9080.h')
| -rw-r--r-- | drivers/staging/comedi/drivers/plx9080.h | 80 |
1 files changed, 40 insertions, 40 deletions
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h index a5a1a6808c5d..9231ba802030 100644 --- a/drivers/staging/comedi/drivers/plx9080.h +++ b/drivers/staging/comedi/drivers/plx9080.h @@ -27,7 +27,7 @@ #ifndef __COMEDI_PLX9080_H #define __COMEDI_PLX9080_H -// descriptor block used for chained dma transfers +/* descriptor block used for chained dma transfers */ struct plx_dma_desc { volatile uint32_t pci_start_addr; volatile uint32_t local_start_addr; @@ -52,14 +52,14 @@ struct plx_dma_desc { #define LRNG_ANY32 0x00000000 /* Locate anywhere in 32 bit */ #define LRNG_LT1MB 0x00000002 /* Locate in 1st meg */ #define LRNG_ANY64 0x00000004 /* Locate anywhere in 64 bit */ -#define LRNG_MEM_MASK 0xfffffff0 // bits that specify range for memory io -#define LRNG_IO_MASK 0xfffffffa // bits that specify range for normal io +#define LRNG_MEM_MASK 0xfffffff0 /* bits that specify range for memory io */ +#define LRNG_IO_MASK 0xfffffffa /* bits that specify range for normal io */ #define PLX_LAS0MAP_REG 0x0004 /* L, Local Addr Space 0 Remap Register */ #define PLX_LAS1MAP_REG 0x00f4 /* L, Local Addr Space 1 Remap Register */ #define LMAP_EN 0x00000001 /* Enable slave decode */ -#define LMAP_MEM_MASK 0xfffffff0 // bits that specify decode for memory io -#define LMAP_IO_MASK 0xfffffffa // bits that specify decode bits for normal io +#define LMAP_MEM_MASK 0xfffffff0 /* bits that specify decode for memory io */ +#define LMAP_IO_MASK 0xfffffffa /* bits that specify decode bits for normal io */ /* Mode/Arbitration Register. */ @@ -169,7 +169,7 @@ enum bigend_bits { #define ICS_AERR 0x00000001 /* Assert LSERR on ABORT */ #define ICS_PERR 0x00000002 /* Assert LSERR on Parity Error */ #define ICS_SERR 0x00000004 /* Generate PCI SERR# */ -#define ICS_MBIE 0x00000008 // mailbox interrupt enable +#define ICS_MBIE 0x00000008 /* mailbox interrupt enable */ #define ICS_PIE 0x00000100 /* PCI Interrupt Enable */ #define ICS_PDIE 0x00000200 /* PCI Doorbell Interrupt Enable */ #define ICS_PAIE 0x00000400 /* PCI Abort Interrupt Enable */ @@ -190,7 +190,7 @@ enum bigend_bits { #define ICS_TA_DMA0 0x02000000 /* Target Abort - DMA #0 */ #define ICS_TA_DMA1 0x04000000 /* Target Abort - DMA #1 */ #define ICS_TA_RA 0x08000000 /* Target Abort - Retry Timeout */ -#define ICS_MBIA(x) (0x10000000 << ((x) & 0x3)) // mailbox x is active +#define ICS_MBIA(x) (0x10000000 << ((x) & 0x3)) /* mailbox x is active */ #define PLX_CONTROL_REG 0x006C /* L, EEPROM Cntl & PCI Cmd Codes */ #define CTL_RDMA 0x0000000E /* DMA Read Command */ @@ -208,51 +208,51 @@ enum bigend_bits { #define CTL_RESET 0x40000000 /* !! Adapter Reset !! */ #define CTL_READY 0x80000000 /* Local Init Done */ -#define PLX_ID_REG 0x70 // hard-coded plx vendor and device ids +#define PLX_ID_REG 0x70 /* hard-coded plx vendor and device ids */ -#define PLX_REVISION_REG 0x74 // silicon revision +#define PLX_REVISION_REG 0x74 /* silicon revision */ -#define PLX_DMA0_MODE_REG 0x80 // dma channel 0 mode register -#define PLX_DMA1_MODE_REG 0x94 // dma channel 0 mode register +#define PLX_DMA0_MODE_REG 0x80 /* dma channel 0 mode register */ +#define PLX_DMA1_MODE_REG 0x94 /* dma channel 0 mode register */ #define PLX_LOCAL_BUS_16_WIDE_BITS 0x1 #define PLX_LOCAL_BUS_32_WIDE_BITS 0x3 #define PLX_LOCAL_BUS_WIDTH_MASK 0x3 -#define PLX_DMA_EN_READYIN_BIT 0x40 // enable ready in input -#define PLX_EN_BTERM_BIT 0x80 // enable BTERM# input -#define PLX_DMA_LOCAL_BURST_EN_BIT 0x100 // enable local burst mode -#define PLX_EN_CHAIN_BIT 0x200 // enables chaining -#define PLX_EN_DMA_DONE_INTR_BIT 0x400 // enables interrupt on dma done -#define PLX_LOCAL_ADDR_CONST_BIT 0x800 // hold local address constant (don't increment) -#define PLX_DEMAND_MODE_BIT 0x1000 // enables demand-mode for dma transfer +#define PLX_DMA_EN_READYIN_BIT 0x40 /* enable ready in input */ +#define PLX_EN_BTERM_BIT 0x80 /* enable BTERM# input */ +#define PLX_DMA_LOCAL_BURST_EN_BIT 0x100 /* enable local burst mode */ +#define PLX_EN_CHAIN_BIT 0x200 /* enables chaining */ +#define PLX_EN_DMA_DONE_INTR_BIT 0x400 /* enables interrupt on dma done */ +#define PLX_LOCAL_ADDR_CONST_BIT 0x800 /* hold local address constant (don't increment) */ +#define PLX_DEMAND_MODE_BIT 0x1000 /* enables demand-mode for dma transfer */ #define PLX_EOT_ENABLE_BIT 0x4000 #define PLX_STOP_MODE_BIT 0x8000 -#define PLX_DMA_INTR_PCI_BIT 0x20000 // routes dma interrupt to pci bus (instead of local bus) +#define PLX_DMA_INTR_PCI_BIT 0x20000 /* routes dma interrupt to pci bus (instead of local bus) */ -#define PLX_DMA0_PCI_ADDRESS_REG 0x84 // pci address that dma transfers start at +#define PLX_DMA0_PCI_ADDRESS_REG 0x84 /* pci address that dma transfers start at */ #define PLX_DMA1_PCI_ADDRESS_REG 0x98 -#define PLX_DMA0_LOCAL_ADDRESS_REG 0x88 // local address that dma transfers start at +#define PLX_DMA0_LOCAL_ADDRESS_REG 0x88 /* local address that dma transfers start at */ #define PLX_DMA1_LOCAL_ADDRESS_REG 0x9c -#define PLX_DMA0_TRANSFER_SIZE_REG 0x8c // number of bytes to transfer (first 23 bits) +#define PLX_DMA0_TRANSFER_SIZE_REG 0x8c /* number of bytes to transfer (first 23 bits) */ #define PLX_DMA1_TRANSFER_SIZE_REG 0xa0 -#define PLX_DMA0_DESCRIPTOR_REG 0x90 // descriptor pointer register +#define PLX_DMA0_DESCRIPTOR_REG 0x90 /* descriptor pointer register */ #define PLX_DMA1_DESCRIPTOR_REG 0xa4 -#define PLX_DESC_IN_PCI_BIT 0x1 // descriptor is located in pci space (not local space) -#define PLX_END_OF_CHAIN_BIT 0x2 // end of chain bit -#define PLX_INTR_TERM_COUNT 0x4 // interrupt when this descriptor's transfer is finished -#define PLX_XFER_LOCAL_TO_PCI 0x8 // transfer from local to pci bus (not pci to local) +#define PLX_DESC_IN_PCI_BIT 0x1 /* descriptor is located in pci space (not local space) */ +#define PLX_END_OF_CHAIN_BIT 0x2 /* end of chain bit */ +#define PLX_INTR_TERM_COUNT 0x4 /* interrupt when this descriptor's transfer is finished */ +#define PLX_XFER_LOCAL_TO_PCI 0x8 /* transfer from local to pci bus (not pci to local) */ -#define PLX_DMA0_CS_REG 0xa8 // command status register +#define PLX_DMA0_CS_REG 0xa8 /* command status register */ #define PLX_DMA1_CS_REG 0xa9 -#define PLX_DMA_EN_BIT 0x1 // enable dma channel -#define PLX_DMA_START_BIT 0x2 // start dma transfer -#define PLX_DMA_ABORT_BIT 0x4 // abort dma transfer -#define PLX_CLEAR_DMA_INTR_BIT 0x8 // clear dma interrupt -#define PLX_DMA_DONE_BIT 0x10 // transfer done status bit +#define PLX_DMA_EN_BIT 0x1 /* enable dma channel */ +#define PLX_DMA_START_BIT 0x2 /* start dma transfer */ +#define PLX_DMA_ABORT_BIT 0x4 /* abort dma transfer */ +#define PLX_CLEAR_DMA_INTR_BIT 0x8 /* clear dma interrupt */ +#define PLX_DMA_DONE_BIT 0x10 /* transfer done status bit */ -#define PLX_DMA0_THRESHOLD_REG 0xb0 // command status register +#define PLX_DMA0_THRESHOLD_REG 0xb0 /* command status register */ /* * Accesses near the end of memory can cause the PLX chip @@ -392,12 +392,12 @@ static inline int plx9080_abort_dma(void *iobase, unsigned int channel) else dma_cs_addr = iobase + PLX_DMA0_CS_REG; - // abort dma transfer if necessary + /* abort dma transfer if necessary */ dma_status = readb(dma_cs_addr); - if ((dma_status & PLX_DMA_EN_BIT) == 0) { + if ((dma_status & PLX_DMA_EN_BIT) == 0) return 0; - } - // wait to make sure done bit is zero + + /* wait to make sure done bit is zero */ for (i = 0; (dma_status & PLX_DMA_DONE_BIT) && i < timeout; i++) { comedi_udelay(1); dma_status = readb(dma_cs_addr); @@ -408,9 +408,9 @@ static inline int plx9080_abort_dma(void *iobase, unsigned int channel) channel); return -ETIMEDOUT; } - // disable and abort channel + /* disable and abort channel */ writeb(PLX_DMA_ABORT_BIT, dma_cs_addr); - // wait for dma done bit + /* wait for dma done bit */ dma_status = readb(dma_cs_addr); for (i = 0; (dma_status & PLX_DMA_DONE_BIT) == 0 && i < timeout; i++) { comedi_udelay(1); |