diff options
Diffstat (limited to 'drivers/staging/comedi/drivers')
47 files changed, 3409 insertions, 4009 deletions
diff --git a/drivers/staging/comedi/drivers/8255.c b/drivers/staging/comedi/drivers/8255.c index ba89321df65d..b79d3764a8a0 100644 --- a/drivers/staging/comedi/drivers/8255.c +++ b/drivers/staging/comedi/drivers/8255.c @@ -53,221 +53,6 @@ #include "8255.h" -struct subdev_8255_private { - unsigned long regbase; - int (*io)(struct comedi_device *, int, int, int, unsigned long); -}; - -static int subdev_8255_io(struct comedi_device *dev, - int dir, int port, int data, unsigned long regbase) -{ - if (dir) { - outb(data, dev->iobase + regbase + port); - return 0; - } - return inb(dev->iobase + regbase + port); -} - -static int subdev_8255_mmio(struct comedi_device *dev, - int dir, int port, int data, unsigned long regbase) -{ - if (dir) { - writeb(data, dev->mmio + regbase + port); - return 0; - } - return readb(dev->mmio + regbase + port); -} - -static int subdev_8255_insn(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, - unsigned int *data) -{ - struct subdev_8255_private *spriv = s->private; - unsigned long regbase = spriv->regbase; - unsigned int mask; - unsigned int v; - - mask = comedi_dio_update_state(s, data); - if (mask) { - if (mask & 0xff) - spriv->io(dev, 1, I8255_DATA_A_REG, - s->state & 0xff, regbase); - if (mask & 0xff00) - spriv->io(dev, 1, I8255_DATA_B_REG, - (s->state >> 8) & 0xff, regbase); - if (mask & 0xff0000) - spriv->io(dev, 1, I8255_DATA_C_REG, - (s->state >> 16) & 0xff, regbase); - } - - v = spriv->io(dev, 0, I8255_DATA_A_REG, 0, regbase); - v |= (spriv->io(dev, 0, I8255_DATA_B_REG, 0, regbase) << 8); - v |= (spriv->io(dev, 0, I8255_DATA_C_REG, 0, regbase) << 16); - - data[1] = v; - - return insn->n; -} - -static void subdev_8255_do_config(struct comedi_device *dev, - struct comedi_subdevice *s) -{ - struct subdev_8255_private *spriv = s->private; - unsigned long regbase = spriv->regbase; - int config; - - config = I8255_CTRL_CW; - /* 1 in io_bits indicates output, 1 in config indicates input */ - if (!(s->io_bits & 0x0000ff)) - config |= I8255_CTRL_A_IO; - if (!(s->io_bits & 0x00ff00)) - config |= I8255_CTRL_B_IO; - if (!(s->io_bits & 0x0f0000)) - config |= I8255_CTRL_C_LO_IO; - if (!(s->io_bits & 0xf00000)) - config |= I8255_CTRL_C_HI_IO; - - spriv->io(dev, 1, I8255_CTRL_REG, config, regbase); -} - -static int subdev_8255_insn_config(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, - unsigned int *data) -{ - unsigned int chan = CR_CHAN(insn->chanspec); - unsigned int mask; - int ret; - - if (chan < 8) - mask = 0x0000ff; - else if (chan < 16) - mask = 0x00ff00; - else if (chan < 20) - mask = 0x0f0000; - else - mask = 0xf00000; - - ret = comedi_dio_insn_config(dev, s, insn, data, mask); - if (ret) - return ret; - - subdev_8255_do_config(dev, s); - - return insn->n; -} - -static int __subdev_8255_init(struct comedi_device *dev, - struct comedi_subdevice *s, - int (*io)(struct comedi_device *, - int, int, int, unsigned long), - unsigned long regbase, - bool is_mmio) -{ - struct subdev_8255_private *spriv; - - spriv = comedi_alloc_spriv(s, sizeof(*spriv)); - if (!spriv) - return -ENOMEM; - - if (io) - spriv->io = io; - else if (is_mmio) - spriv->io = subdev_8255_mmio; - else - spriv->io = subdev_8255_io; - spriv->regbase = regbase; - - s->type = COMEDI_SUBD_DIO; - s->subdev_flags = SDF_READABLE | SDF_WRITABLE; - s->n_chan = 24; - s->range_table = &range_digital; - s->maxdata = 1; - s->insn_bits = subdev_8255_insn; - s->insn_config = subdev_8255_insn_config; - - subdev_8255_do_config(dev, s); - - return 0; -} - -/** - * subdev_8255_init - initialize DIO subdevice for driving I/O mapped 8255 - * @dev: comedi device owning subdevice - * @s: comedi subdevice to initialize - * @io: (optional) register I/O call-back function - * @regbase: offset of 8255 registers from dev->iobase, or call-back context - * - * Initializes a comedi subdevice as a DIO subdevice driving an 8255 chip. - * - * If the optional I/O call-back function is provided, its prototype is of - * the following form: - * - * int my_8255_callback(struct comedi_device *dev, - * struct comedi_subdevice *s, int dir, int port, - * int data, unsigned long regbase); - * - * where 'dev', 's', and 'regbase' match the values passed to this function, - * 'port' is the 8255 port number 0 to 3 (including the control port), 'dir' - * is the direction (0 for read, 1 for write) and 'data' is the value to be - * written. It should return 0 if writing or the value read if reading. - * - * If the optional I/O call-back function is not provided, an internal - * call-back function is used which uses consecutive I/O port addresses - * starting at dev->iobase + regbase. - * - * Return: -ENOMEM if failed to allocate memory, zero on success. - */ -int subdev_8255_init(struct comedi_device *dev, struct comedi_subdevice *s, - int (*io)(struct comedi_device *, - int, int, int, unsigned long), - unsigned long regbase) -{ - return __subdev_8255_init(dev, s, io, regbase, false); -} -EXPORT_SYMBOL_GPL(subdev_8255_init); - -/** - * subdev_8255_mm_init - initialize DIO subdevice for driving mmio-mapped 8255 - * @dev: comedi device owning subdevice - * @s: comedi subdevice to initialize - * @io: (optional) register I/O call-back function - * @regbase: offset of 8255 registers from dev->mmio, or call-back context - * - * Initializes a comedi subdevice as a DIO subdevice driving an 8255 chip. - * - * If the optional I/O call-back function is provided, its prototype is of - * the following form: - * - * int my_8255_callback(struct comedi_device *dev, - * struct comedi_subdevice *s, int dir, int port, - * int data, unsigned long regbase); - * - * where 'dev', 's', and 'regbase' match the values passed to this function, - * 'port' is the 8255 port number 0 to 3 (including the control port), 'dir' - * is the direction (0 for read, 1 for write) and 'data' is the value to be - * written. It should return 0 if writing or the value read if reading. - * - * If the optional I/O call-back function is not provided, an internal - * call-back function is used which uses consecutive MMIO virtual addresses - * starting at dev->mmio + regbase. - * - * Return: -ENOMEM if failed to allocate memory, zero on success. - */ -int subdev_8255_mm_init(struct comedi_device *dev, struct comedi_subdevice *s, - int (*io)(struct comedi_device *, - int, int, int, unsigned long), - unsigned long regbase) -{ - return __subdev_8255_init(dev, s, io, regbase, true); -} -EXPORT_SYMBOL_GPL(subdev_8255_mm_init); - -/* - * Start of the 8255 standalone device - */ - static int dev_8255_attach(struct comedi_device *dev, struct comedi_devconfig *it) { @@ -306,8 +91,15 @@ static int dev_8255_attach(struct comedi_device *dev, s->type = COMEDI_SUBD_UNUSED; } else { ret = subdev_8255_init(dev, s, NULL, iobase); - if (ret) + if (ret) { + /* + * Release the I/O port region here, as the + * "detach" handler cannot find it. + */ + release_region(iobase, I8255_SIZE); + s->type = COMEDI_SUBD_UNUSED; return ret; + } } } @@ -317,14 +109,14 @@ static int dev_8255_attach(struct comedi_device *dev, static void dev_8255_detach(struct comedi_device *dev) { struct comedi_subdevice *s; - struct subdev_8255_private *spriv; int i; for (i = 0; i < dev->n_subdevices; i++) { s = &dev->subdevices[i]; if (s->type != COMEDI_SUBD_UNUSED) { - spriv = s->private; - release_region(spriv->regbase, I8255_SIZE); + unsigned long regbase = subdev_8255_regbase(s); + + release_region(regbase, I8255_SIZE); } } } @@ -338,5 +130,5 @@ static struct comedi_driver dev_8255_driver = { module_comedi_driver(dev_8255_driver); MODULE_AUTHOR("Comedi http://www.comedi.org"); -MODULE_DESCRIPTION("Comedi low-level driver"); +MODULE_DESCRIPTION("Comedi driver for standalone 8255 devices"); MODULE_LICENSE("GPL"); diff --git a/drivers/staging/comedi/drivers/8255.h b/drivers/staging/comedi/drivers/8255.h index 934b940ebd3c..41823de69b77 100644 --- a/drivers/staging/comedi/drivers/8255.h +++ b/drivers/staging/comedi/drivers/8255.h @@ -19,8 +19,6 @@ #ifndef _8255_H #define _8255_H -#include "../comedidev.h" - #define I8255_SIZE 0x04 #define I8255_DATA_A_REG 0x00 @@ -35,14 +33,19 @@ #define I8255_CTRL_A_MODE(x) ((x) << 5) #define I8255_CTRL_CW (1 << 7) -int subdev_8255_init(struct comedi_device *, struct comedi_subdevice *, - int (*io)(struct comedi_device *, - int, int, int, unsigned long), +struct comedi_device; +struct comedi_subdevice; + +int subdev_8255_init(struct comedi_device *dev, struct comedi_subdevice *s, + int (*io)(struct comedi_device *dev, int dir, int port, + int data, unsigned long regbase), unsigned long regbase); -int subdev_8255_mm_init(struct comedi_device *, struct comedi_subdevice *, - int (*io)(struct comedi_device *, - int, int, int, unsigned long), +int subdev_8255_mm_init(struct comedi_device *dev, struct comedi_subdevice *s, + int (*io)(struct comedi_device *dev, int dir, int port, + int data, unsigned long regbase), unsigned long regbase); +unsigned long subdev_8255_regbase(struct comedi_subdevice *s); + #endif diff --git a/drivers/staging/comedi/drivers/Makefile b/drivers/staging/comedi/drivers/Makefile index d6d834006015..5764dc9a6893 100644 --- a/drivers/staging/comedi/drivers/Makefile +++ b/drivers/staging/comedi/drivers/Makefile @@ -139,7 +139,8 @@ obj-$(CONFIG_COMEDI_NI_TIOCMD) += ni_tiocmd.o obj-$(CONFIG_COMEDI_NI_LABPC) += ni_labpc_common.o obj-$(CONFIG_COMEDI_NI_LABPC_ISADMA) += ni_labpc_isadma.o -obj-$(CONFIG_COMEDI_8255) += 8255.o +obj-$(CONFIG_COMEDI_8255) += comedi_8255.o +obj-$(CONFIG_COMEDI_8255_SA) += 8255.o obj-$(CONFIG_COMEDI_AMPLC_DIO200) += amplc_dio200_common.o obj-$(CONFIG_COMEDI_AMPLC_PC236) += amplc_pc236_common.o obj-$(CONFIG_COMEDI_DAS08) += das08.o diff --git a/drivers/staging/comedi/drivers/addi_apci_1516.c b/drivers/staging/comedi/drivers/addi_apci_1516.c index 9c516d1fe896..f1f8b1c422a7 100644 --- a/drivers/staging/comedi/drivers/addi_apci_1516.c +++ b/drivers/staging/comedi/drivers/addi_apci_1516.c @@ -100,10 +100,10 @@ static int apci1516_do_insn_bits(struct comedi_device *dev, static int apci1516_reset(struct comedi_device *dev) { - const struct apci1516_boardinfo *this_board = dev->board_ptr; + const struct apci1516_boardinfo *board = dev->board_ptr; struct apci1516_private *devpriv = dev->private; - if (!this_board->has_wdog) + if (!board->has_wdog) return 0; outw(0x0, dev->iobase + APCI1516_DO_REG); @@ -117,17 +117,17 @@ static int apci1516_auto_attach(struct comedi_device *dev, unsigned long context) { struct pci_dev *pcidev = comedi_to_pci_dev(dev); - const struct apci1516_boardinfo *this_board = NULL; + const struct apci1516_boardinfo *board = NULL; struct apci1516_private *devpriv; struct comedi_subdevice *s; int ret; if (context < ARRAY_SIZE(apci1516_boardtypes)) - this_board = &apci1516_boardtypes[context]; - if (!this_board) + board = &apci1516_boardtypes[context]; + if (!board) return -ENODEV; - dev->board_ptr = this_board; - dev->board_name = this_board->name; + dev->board_ptr = board; + dev->board_name = board->name; devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); if (!devpriv) @@ -146,10 +146,10 @@ static int apci1516_auto_attach(struct comedi_device *dev, /* Initialize the digital input subdevice */ s = &dev->subdevices[0]; - if (this_board->di_nchan) { + if (board->di_nchan) { s->type = COMEDI_SUBD_DI; s->subdev_flags = SDF_READABLE; - s->n_chan = this_board->di_nchan; + s->n_chan = board->di_nchan; s->maxdata = 1; s->range_table = &range_digital; s->insn_bits = apci1516_di_insn_bits; @@ -159,10 +159,10 @@ static int apci1516_auto_attach(struct comedi_device *dev, /* Initialize the digital output subdevice */ s = &dev->subdevices[1]; - if (this_board->do_nchan) { + if (board->do_nchan) { s->type = COMEDI_SUBD_DO; s->subdev_flags = SDF_WRITABLE; - s->n_chan = this_board->do_nchan; + s->n_chan = board->do_nchan; s->maxdata = 1; s->range_table = &range_digital; s->insn_bits = apci1516_do_insn_bits; @@ -172,7 +172,7 @@ static int apci1516_auto_attach(struct comedi_device *dev, /* Initialize the watchdog subdevice */ s = &dev->subdevices[2]; - if (this_board->has_wdog) { + if (board->has_wdog) { ret = addi_watchdog_init(s, devpriv->wdog_iobase); if (ret) return ret; diff --git a/drivers/staging/comedi/drivers/addi_apci_3120.c b/drivers/staging/comedi/drivers/addi_apci_3120.c index 95dc64bfec73..5bfd43d5c889 100644 --- a/drivers/staging/comedi/drivers/addi_apci_3120.c +++ b/drivers/staging/comedi/drivers/addi_apci_3120.c @@ -977,18 +977,18 @@ static int apci3120_auto_attach(struct comedi_device *dev, unsigned long context) { struct pci_dev *pcidev = comedi_to_pci_dev(dev); - const struct apci3120_board *this_board = NULL; + const struct apci3120_board *board = NULL; struct apci3120_private *devpriv; struct comedi_subdevice *s; unsigned int status; int ret; if (context < ARRAY_SIZE(apci3120_boardtypes)) - this_board = &apci3120_boardtypes[context]; - if (!this_board) + board = &apci3120_boardtypes[context]; + if (!board) return -ENODEV; - dev->board_ptr = this_board; - dev->board_name = this_board->name; + dev->board_ptr = board; + dev->board_name = board->name; devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); if (!devpriv) @@ -1031,7 +1031,7 @@ static int apci3120_auto_attach(struct comedi_device *dev, s->type = COMEDI_SUBD_AI; s->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_GROUND | SDF_DIFF; s->n_chan = 16; - s->maxdata = this_board->ai_is_16bit ? 0xffff : 0x0fff; + s->maxdata = board->ai_is_16bit ? 0xffff : 0x0fff; s->range_table = &apci3120_ai_range; s->insn_read = apci3120_ai_insn_read; if (dev->irq) { @@ -1045,7 +1045,7 @@ static int apci3120_auto_attach(struct comedi_device *dev, /* Analog Output subdevice */ s = &dev->subdevices[1]; - if (this_board->has_ao) { + if (board->has_ao) { s->type = COMEDI_SUBD_AO; s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON; s->n_chan = 8; diff --git a/drivers/staging/comedi/drivers/addi_watchdog.h b/drivers/staging/comedi/drivers/addi_watchdog.h index 83b47befa4d1..3f8e7388bbca 100644 --- a/drivers/staging/comedi/drivers/addi_watchdog.h +++ b/drivers/staging/comedi/drivers/addi_watchdog.h @@ -1,7 +1,7 @@ #ifndef _ADDI_WATCHDOG_H #define _ADDI_WATCHDOG_H -#include "../comedidev.h" +struct comedi_subdevice; void addi_watchdog_reset(unsigned long iobase); int addi_watchdog_init(struct comedi_subdevice *, unsigned long iobase); diff --git a/drivers/staging/comedi/drivers/adv_pci1724.c b/drivers/staging/comedi/drivers/adv_pci1724.c index f7a7dab013db..9677111f9ab2 100644 --- a/drivers/staging/comedi/drivers/adv_pci1724.c +++ b/drivers/staging/comedi/drivers/adv_pci1724.c @@ -180,11 +180,7 @@ static int adv_pci1724_auto_attach(struct comedi_device *dev, s->insn_write = adv_pci1724_insn_write; s->private = (void *)PCI1724_DAC_CTRL_MODE_GAIN; - ret = comedi_alloc_subdev_readback(s); - if (ret) - return ret; - - return 0; + return comedi_alloc_subdev_readback(s); } static struct comedi_driver adv_pci1724_driver = { diff --git a/drivers/staging/comedi/drivers/adv_pci_dio.c b/drivers/staging/comedi/drivers/adv_pci_dio.c index 456e87013063..f1b3c5aa8d79 100644 --- a/drivers/staging/comedi/drivers/adv_pci_dio.c +++ b/drivers/staging/comedi/drivers/adv_pci_dio.c @@ -732,9 +732,9 @@ static int pci1760_reset(struct comedi_device *dev) */ static int pci_dio_reset(struct comedi_device *dev) { - const struct dio_boardtype *this_board = dev->board_ptr; + const struct dio_boardtype *board = dev->board_ptr; - switch (this_board->cardtype) { + switch (board->cardtype) { case TYPE_PCI1730: outb(0, dev->iobase + PCI1730_DO); /* clear outputs */ outb(0, dev->iobase + PCI1730_DO + 1); @@ -887,7 +887,7 @@ static int pci_dio_add_di(struct comedi_device *dev, struct comedi_subdevice *s, const struct diosubd_data *d) { - const struct dio_boardtype *this_board = dev->board_ptr; + const struct dio_boardtype *board = dev->board_ptr; s->type = COMEDI_SUBD_DI; s->subdev_flags = SDF_READABLE | d->specflags; @@ -897,7 +897,7 @@ static int pci_dio_add_di(struct comedi_device *dev, s->maxdata = 1; s->len_chanlist = d->chans; s->range_table = &range_digital; - switch (this_board->io_access) { + switch (board->io_access) { case IO_8b: s->insn_bits = pci_dio_insn_bits_di_b; break; @@ -917,7 +917,7 @@ static int pci_dio_add_do(struct comedi_device *dev, struct comedi_subdevice *s, const struct diosubd_data *d) { - const struct dio_boardtype *this_board = dev->board_ptr; + const struct dio_boardtype *board = dev->board_ptr; s->type = COMEDI_SUBD_DO; s->subdev_flags = SDF_WRITABLE; @@ -928,7 +928,7 @@ static int pci_dio_add_do(struct comedi_device *dev, s->len_chanlist = d->chans; s->range_table = &range_digital; s->state = 0; - switch (this_board->io_access) { + switch (board->io_access) { case IO_8b: s->insn_bits = pci_dio_insn_bits_do_b; break; @@ -978,17 +978,17 @@ static int pci_dio_auto_attach(struct comedi_device *dev, unsigned long context) { struct pci_dev *pcidev = comedi_to_pci_dev(dev); - const struct dio_boardtype *this_board = NULL; + const struct dio_boardtype *board = NULL; struct pci_dio_private *devpriv; struct comedi_subdevice *s; int ret, subdev, i, j; if (context < ARRAY_SIZE(boardtypes)) - this_board = &boardtypes[context]; - if (!this_board) + board = &boardtypes[context]; + if (!board) return -ENODEV; - dev->board_ptr = this_board; - dev->board_name = this_board->name; + dev->board_ptr = board; + dev->board_name = board->name; devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); if (!devpriv) @@ -997,50 +997,50 @@ static int pci_dio_auto_attach(struct comedi_device *dev, ret = comedi_pci_enable(dev); if (ret) return ret; - dev->iobase = pci_resource_start(pcidev, this_board->main_pci_region); + dev->iobase = pci_resource_start(pcidev, board->main_pci_region); - ret = comedi_alloc_subdevices(dev, this_board->nsubdevs); + ret = comedi_alloc_subdevices(dev, board->nsubdevs); if (ret) return ret; subdev = 0; for (i = 0; i < MAX_DI_SUBDEVS; i++) - if (this_board->sdi[i].chans) { + if (board->sdi[i].chans) { s = &dev->subdevices[subdev]; - pci_dio_add_di(dev, s, &this_board->sdi[i]); + pci_dio_add_di(dev, s, &board->sdi[i]); subdev++; } for (i = 0; i < MAX_DO_SUBDEVS; i++) - if (this_board->sdo[i].chans) { + if (board->sdo[i].chans) { s = &dev->subdevices[subdev]; - pci_dio_add_do(dev, s, &this_board->sdo[i]); + pci_dio_add_do(dev, s, &board->sdo[i]); subdev++; } for (i = 0; i < MAX_DIO_SUBDEVG; i++) - for (j = 0; j < this_board->sdio[i].regs; j++) { + for (j = 0; j < board->sdio[i].regs; j++) { s = &dev->subdevices[subdev]; ret = subdev_8255_init(dev, s, NULL, - this_board->sdio[i].addr + + board->sdio[i].addr + j * I8255_SIZE); if (ret) return ret; subdev++; } - if (this_board->boardid.chans) { + if (board->boardid.chans) { s = &dev->subdevices[subdev]; s->type = COMEDI_SUBD_DI; - pci_dio_add_di(dev, s, &this_board->boardid); + pci_dio_add_di(dev, s, &board->boardid); subdev++; } - if (this_board->timer_regbase) { + if (board->timer_regbase) { s = &dev->subdevices[subdev]; dev->pacer = comedi_8254_init(dev->iobase + - this_board->timer_regbase, + board->timer_regbase, 0, I8254_IO8, 0); if (!dev->pacer) return -ENOMEM; @@ -1050,7 +1050,7 @@ static int pci_dio_auto_attach(struct comedi_device *dev, subdev++; } - if (this_board->cardtype == TYPE_PCI1760) + if (board->cardtype == TYPE_PCI1760) pci1760_attach(dev); pci_dio_reset(dev); diff --git a/drivers/staging/comedi/drivers/amplc_dio200.c b/drivers/staging/comedi/drivers/amplc_dio200.c index 4fe118380218..f5cfa71a90c6 100644 --- a/drivers/staging/comedi/drivers/amplc_dio200.c +++ b/drivers/staging/comedi/drivers/amplc_dio200.c @@ -1,23 +1,24 @@ /* - comedi/drivers/amplc_dio200.c - - Driver for Amplicon PC212E, PC214E, PC215E, PC218E, PC272E. - - Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/> - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. + * comedi/drivers/amplc_dio200.c + * + * Driver for Amplicon PC212E, PC214E, PC215E, PC218E, PC272E. + * + * Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/> + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ /* * Driver: amplc_dio200 * Description: Amplicon 200 Series ISA Digital I/O diff --git a/drivers/staging/comedi/drivers/amplc_dio200.h b/drivers/staging/comedi/drivers/amplc_dio200.h index d6d6a265c461..53fb86d59fc3 100644 --- a/drivers/staging/comedi/drivers/amplc_dio200.h +++ b/drivers/staging/comedi/drivers/amplc_dio200.h @@ -1,28 +1,32 @@ /* - comedi/drivers/amplc_dio.h - - Header for amplc_dio200.c, amplc_dio200_common.c and - amplc_dio200_pci.c. - - Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/> - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * comedi/drivers/amplc_dio.h + * + * Header for amplc_dio200.c, amplc_dio200_common.c and + * amplc_dio200_pci.c. + * + * Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/> + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ #ifndef AMPLC_DIO200_H_INCLUDED #define AMPLC_DIO200_H_INCLUDED +#include <linux/types.h> + +struct comedi_device; + /* * Subdevice types. */ diff --git a/drivers/staging/comedi/drivers/amplc_dio200_common.c b/drivers/staging/comedi/drivers/amplc_dio200_common.c index d15a3dc1216a..d1539e798ffd 100644 --- a/drivers/staging/comedi/drivers/amplc_dio200_common.c +++ b/drivers/staging/comedi/drivers/amplc_dio200_common.c @@ -1,23 +1,23 @@ /* - comedi/drivers/amplc_dio200_common.c - - Common support code for "amplc_dio200" and "amplc_dio200_pci". - - Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/> - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * comedi/drivers/amplc_dio200_common.c + * + * Common support code for "amplc_dio200" and "amplc_dio200_pci". + * + * Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/> + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ #include <linux/module.h> #include <linux/interrupt.h> @@ -337,9 +337,10 @@ static int dio200_handle_read_intr(struct comedi_device *dev, * interested in (just in case there's a race * condition). */ - if (triggered & subpriv->enabled_isns) + if (triggered & subpriv->enabled_isns) { /* Collect scan data. */ dio200_read_scan_intr(dev, s, triggered); + } } } spin_unlock_irqrestore(&subpriv->spinlock, flags); @@ -576,12 +577,13 @@ static int dio200_subdev_8254_init(struct comedi_device *dev, regshift = 0; } - if (dev->mmio) + if (dev->mmio) { i8254 = comedi_8254_mm_init(dev->mmio + offset, 0, I8254_IO8, regshift); - else + } else { i8254 = comedi_8254_init(dev->iobase + offset, 0, I8254_IO8, regshift); + } if (!i8254) return -ENOMEM; @@ -593,10 +595,10 @@ static int dio200_subdev_8254_init(struct comedi_device *dev, * There could be multiple timers so this driver does not * use dev->pacer to save the i8254 pointer. Instead, * comedi_8254_subdevice_init() saved the i8254 pointer in - * s->private. Set the runflag bit so that the core will - * automatically free it when the driver is detached. + * s->private. Mark the subdevice as having private data + * to be automatically freed when the device is detached. */ - s->runflags |= COMEDI_SRF_FREE_SPRIV; + comedi_set_spriv_auto_free(s); /* Initialize channels. */ if (board->has_clk_gat_sce) { @@ -641,15 +643,18 @@ static int dio200_subdev_8255_bits(struct comedi_device *dev, mask = comedi_dio_update_state(s, data); if (mask) { - if (mask & 0xff) + if (mask & 0xff) { dio200_write8(dev, subpriv->ofs + I8255_DATA_A_REG, s->state & 0xff); - if (mask & 0xff00) + } + if (mask & 0xff00) { dio200_write8(dev, subpriv->ofs + I8255_DATA_B_REG, (s->state >> 8) & 0xff); - if (mask & 0xff0000) + } + if (mask & 0xff0000) { dio200_write8(dev, subpriv->ofs + I8255_DATA_C_REG, (s->state >> 16) & 0xff); + } } val = dio200_read8(dev, subpriv->ofs + I8255_DATA_A_REG); diff --git a/drivers/staging/comedi/drivers/amplc_dio200_pci.c b/drivers/staging/comedi/drivers/amplc_dio200_pci.c index d9850c917163..2598e6e7d47d 100644 --- a/drivers/staging/comedi/drivers/amplc_dio200_pci.c +++ b/drivers/staging/comedi/drivers/amplc_dio200_pci.c @@ -1,22 +1,23 @@ /* comedi/drivers/amplc_dio200_pci.c + * + * Driver for Amplicon PCI215, PCI272, PCIe215, PCIe236, PCIe296. + * + * Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/> + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ - Driver for Amplicon PCI215, PCI272, PCIe215, PCIe236, PCIe296. - - Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/> - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ /* * Driver: amplc_dio200_pci * Description: Amplicon 200 Series PCI Digital I/O diff --git a/drivers/staging/comedi/drivers/amplc_pc236_common.c b/drivers/staging/comedi/drivers/amplc_pc236_common.c index 245f932a75a8..0c02d3245679 100644 --- a/drivers/staging/comedi/drivers/amplc_pc236_common.c +++ b/drivers/staging/comedi/drivers/amplc_pc236_common.c @@ -28,14 +28,14 @@ static void pc236_intr_update(struct comedi_device *dev, bool enable) { - const struct pc236_board *thisboard = dev->board_ptr; + const struct pc236_board *board = dev->board_ptr; struct pc236_private *devpriv = dev->private; unsigned long flags; spin_lock_irqsave(&dev->spinlock, flags); devpriv->enable_irq = enable; - if (thisboard->intr_update_cb) - thisboard->intr_update_cb(dev, enable); + if (board->intr_update_cb) + board->intr_update_cb(dev, enable); spin_unlock_irqrestore(&dev->spinlock, flags); } @@ -48,15 +48,15 @@ static void pc236_intr_update(struct comedi_device *dev, bool enable) */ static bool pc236_intr_check(struct comedi_device *dev) { - const struct pc236_board *thisboard = dev->board_ptr; + const struct pc236_board *board = dev->board_ptr; struct pc236_private *devpriv = dev->private; bool retval = false; unsigned long flags; spin_lock_irqsave(&dev->spinlock, flags); if (devpriv->enable_irq) { - if (thisboard->intr_chk_clr_cb) - retval = thisboard->intr_chk_clr_cb(dev); + if (board->intr_chk_clr_cb) + retval = board->intr_chk_clr_cb(dev); else retval = true; } diff --git a/drivers/staging/comedi/drivers/amplc_pci224.c b/drivers/staging/comedi/drivers/amplc_pci224.c index 08a91854837a..b2f7679a0116 100644 --- a/drivers/staging/comedi/drivers/amplc_pci224.c +++ b/drivers/staging/comedi/drivers/amplc_pci224.c @@ -385,14 +385,14 @@ static void pci224_ao_set_data(struct comedi_device *dev, int chan, int range, unsigned int data) { - const struct pci224_board *thisboard = dev->board_ptr; + const struct pci224_board *board = dev->board_ptr; struct pci224_private *devpriv = dev->private; unsigned short mangled; /* Enable the channel. */ outw(1 << chan, dev->iobase + PCI224_DACCEN); /* Set range and reset FIFO. */ - devpriv->daccon = COMBINE(devpriv->daccon, thisboard->ao_hwrange[range], + devpriv->daccon = COMBINE(devpriv->daccon, board->ao_hwrange[range], PCI224_DACCON_POLAR_MASK | PCI224_DACCON_VREF_MASK); outw(devpriv->daccon | PCI224_DACCON_FIFORESET, @@ -402,7 +402,7 @@ pci224_ao_set_data(struct comedi_device *dev, int chan, int range, * - bipolar: 16-bit 2's complement * - unipolar: 16-bit unsigned */ - mangled = (unsigned short)data << (16 - thisboard->ao_bits); + mangled = (unsigned short)data << (16 - board->ao_bits); if ((devpriv->daccon & PCI224_DACCON_POLAR_MASK) == PCI224_DACCON_POLAR_BI) { mangled ^= 0x8000; @@ -620,12 +620,12 @@ static int pci224_ao_check_chanlist(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_cmd *cmd) { - const struct pci224_board *thisboard = dev->board_ptr; + const struct pci224_board *board = dev->board_ptr; unsigned int range_check_0; unsigned int chan_mask = 0; int i; - range_check_0 = thisboard->ao_range_check[CR_RANGE(cmd->chanlist[0])]; + range_check_0 = board->ao_range_check[CR_RANGE(cmd->chanlist[0])]; for (i = 0; i < cmd->chanlist_len; i++) { unsigned int chan = CR_CHAN(cmd->chanlist[i]); @@ -637,7 +637,7 @@ static int pci224_ao_check_chanlist(struct comedi_device *dev, } chan_mask |= 1 << chan; - if (thisboard->ao_range_check[CR_RANGE(cmd->chanlist[i])] != + if (board->ao_range_check[CR_RANGE(cmd->chanlist[i])] != range_check_0) { dev_dbg(dev->class_dev, "%s: entries in chanlist have incompatible ranges\n", @@ -826,7 +826,7 @@ static void pci224_ao_start_pacer(struct comedi_device *dev, static int pci224_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) { - const struct pci224_board *thisboard = dev->board_ptr; + const struct pci224_board *board = dev->board_ptr; struct pci224_private *devpriv = dev->private; struct comedi_cmd *cmd = &s->async->cmd; int range; @@ -869,7 +869,7 @@ static int pci224_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) */ devpriv->daccon = COMBINE(devpriv->daccon, - thisboard->ao_hwrange[range] | PCI224_DACCON_TRIG_NONE | + board->ao_hwrange[range] | PCI224_DACCON_TRIG_NONE | PCI224_DACCON_FIFOINTR_NHALF, PCI224_DACCON_POLAR_MASK | PCI224_DACCON_VREF_MASK | PCI224_DACCON_TRIG_MASK | PCI224_DACCON_FIFOINTR_MASK); @@ -911,7 +911,7 @@ static void pci224_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s, void *data, unsigned int num_bytes, unsigned int chan_index) { - const struct pci224_board *thisboard = dev->board_ptr; + const struct pci224_board *board = dev->board_ptr; struct comedi_cmd *cmd = &s->async->cmd; unsigned short *array = data; unsigned int length = num_bytes / sizeof(*array); @@ -920,9 +920,9 @@ pci224_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s, unsigned int i; /* The hardware expects 16-bit numbers. */ - shift = 16 - thisboard->ao_bits; + shift = 16 - board->ao_bits; /* Channels will be all bipolar or all unipolar. */ - if ((thisboard->ao_hwrange[CR_RANGE(cmd->chanlist[0])] & + if ((board->ao_hwrange[CR_RANGE(cmd->chanlist[0])] & PCI224_DACCON_POLAR_MASK) == PCI224_DACCON_POLAR_UNI) { /* Unipolar */ offset = 0; @@ -988,21 +988,21 @@ static int pci224_auto_attach(struct comedi_device *dev, unsigned long context_model) { struct pci_dev *pci_dev = comedi_to_pci_dev(dev); - const struct pci224_board *thisboard = NULL; + const struct pci224_board *board = NULL; struct pci224_private *devpriv; struct comedi_subdevice *s; unsigned int irq; int ret; if (context_model < ARRAY_SIZE(pci224_boards)) - thisboard = &pci224_boards[context_model]; - if (!thisboard || !thisboard->name) { + board = &pci224_boards[context_model]; + if (!board || !board->name) { dev_err(dev->class_dev, "amplc_pci224: BUG! cannot determine board type!\n"); return -EINVAL; } - dev->board_ptr = thisboard; - dev->board_name = thisboard->name; + dev->board_ptr = board; + dev->board_name = board->name; dev_info(dev->class_dev, "amplc_pci224: attach pci %s - %s\n", pci_name(pci_dev), dev->board_name); @@ -1023,13 +1023,13 @@ pci224_auto_attach(struct comedi_device *dev, unsigned long context_model) /* Allocate buffer to hold values for AO channel scan. */ devpriv->ao_scan_vals = kmalloc(sizeof(devpriv->ao_scan_vals[0]) * - thisboard->ao_chans, GFP_KERNEL); + board->ao_chans, GFP_KERNEL); if (!devpriv->ao_scan_vals) return -ENOMEM; /* Allocate buffer to hold AO channel scan order. */ devpriv->ao_scan_order = kmalloc(sizeof(devpriv->ao_scan_order[0]) * - thisboard->ao_chans, GFP_KERNEL); + board->ao_chans, GFP_KERNEL); if (!devpriv->ao_scan_order) return -ENOMEM; @@ -1059,9 +1059,9 @@ pci224_auto_attach(struct comedi_device *dev, unsigned long context_model) /* Analog output subdevice. */ s->type = COMEDI_SUBD_AO; s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_CMD_WRITE; - s->n_chan = thisboard->ao_chans; - s->maxdata = (1 << thisboard->ao_bits) - 1; - s->range_table = thisboard->ao_range; + s->n_chan = board->ao_chans; + s->maxdata = (1 << board->ao_bits) - 1; + s->range_table = board->ao_range; s->insn_write = pci224_ao_insn_write; s->len_chanlist = s->n_chan; dev->write_subdev = s; diff --git a/drivers/staging/comedi/drivers/amplc_pci230.c b/drivers/staging/comedi/drivers/amplc_pci230.c index 20d592002557..5c5c4e2ec3d5 100644 --- a/drivers/staging/comedi/drivers/amplc_pci230.c +++ b/drivers/staging/comedi/drivers/amplc_pci230.c @@ -528,7 +528,7 @@ static const struct comedi_lrange pci230_ao_range = { static unsigned short pci230_ai_read(struct comedi_device *dev) { - const struct pci230_board *thisboard = dev->board_ptr; + const struct pci230_board *board = dev->board_ptr; struct pci230_private *devpriv = dev->private; unsigned short data; @@ -543,21 +543,21 @@ static unsigned short pci230_ai_read(struct comedi_device *dev) */ if (devpriv->ai_bipolar) data ^= 0x8000; - data >>= (16 - thisboard->ai_bits); + data >>= (16 - board->ai_bits); return data; } static unsigned short pci230_ao_mangle_datum(struct comedi_device *dev, unsigned short datum) { - const struct pci230_board *thisboard = dev->board_ptr; + const struct pci230_board *board = dev->board_ptr; struct pci230_private *devpriv = dev->private; /* * PCI230 is 12 bit - stored in upper bits of 16 bit register (lower * four bits reserved for expansion). PCI230+ is also 12 bit AO. */ - datum <<= (16 - thisboard->ao_bits); + datum <<= (16 - board->ao_bits); /* * If a bipolar range was specified, mangle it * (straight binary->twos complement). @@ -877,7 +877,7 @@ static int pci230_ao_check_chanlist(struct comedi_device *dev, static int pci230_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_cmd *cmd) { - const struct pci230_board *thisboard = dev->board_ptr; + const struct pci230_board *board = dev->board_ptr; struct pci230_private *devpriv = dev->private; int err = 0; unsigned int tmp; @@ -887,14 +887,14 @@ static int pci230_ao_cmdtest(struct comedi_device *dev, err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT); tmp = TRIG_TIMER | TRIG_INT; - if (thisboard->min_hwver > 0 && devpriv->hwver >= 2) { + if (board->min_hwver > 0 && devpriv->hwver >= 2) { /* * For PCI230+ hardware version 2 onwards, allow external * trigger from EXTTRIG/EXTCONVCLK input (PCI230+ pin 25). * * FIXME: The permitted scan_begin_src values shouldn't depend * on devpriv->hwver (the detected card's actual hardware - * version). They should only depend on thisboard->min_hwver + * version). They should only depend on board->min_hwver * (the static capabilities of the configured card). To fix * it, a new card model, e.g. "pci230+2" would have to be * defined with min_hwver set to 2. It doesn't seem worth it @@ -1500,7 +1500,7 @@ static int pci230_ai_check_chanlist(struct comedi_device *dev, static int pci230_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_cmd *cmd) { - const struct pci230_board *thisboard = dev->board_ptr; + const struct pci230_board *board = dev->board_ptr; struct pci230_private *devpriv = dev->private; int err = 0; unsigned int tmp; @@ -1510,7 +1510,7 @@ static int pci230_ai_cmdtest(struct comedi_device *dev, err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT); tmp = TRIG_FOLLOW | TRIG_TIMER | TRIG_INT; - if (thisboard->have_dio || thisboard->min_hwver > 0) { + if (board->have_dio || board->min_hwver > 0) { /* * Unfortunately, we cannot trigger a scan off an external * source on the PCI260 board, since it uses the PPIC0 (DIO) @@ -2011,17 +2011,17 @@ static void pci230_handle_ai(struct comedi_device *dev, struct comedi_cmd *cmd = &async->cmd; unsigned int status_fifo; unsigned int i; - unsigned int todo; + unsigned int nsamples; unsigned int fifoamount; unsigned short val; /* Determine number of samples to read. */ - todo = comedi_nsamples_left(s, PCI230_ADC_FIFOLEVEL_HALFFULL); - if (todo == 0) + nsamples = comedi_nsamples_left(s, PCI230_ADC_FIFOLEVEL_HALFFULL); + if (nsamples == 0) return; fifoamount = 0; - for (i = 0; i < todo; i++) { + for (i = 0; i < nsamples; i++) { if (fifoamount == 0) { /* Read FIFO state. */ status_fifo = inw(devpriv->daqio + PCI230_ADCCON); @@ -2364,7 +2364,7 @@ static int pci230_auto_attach(struct comedi_device *dev, unsigned long context_unused) { struct pci_dev *pci_dev = comedi_to_pci_dev(dev); - const struct pci230_board *thisboard; + const struct pci230_board *board; struct pci230_private *devpriv; struct comedi_subdevice *s; int rc; @@ -2381,14 +2381,14 @@ static int pci230_auto_attach(struct comedi_device *dev, spin_lock_init(&devpriv->ai_stop_spinlock); spin_lock_init(&devpriv->ao_stop_spinlock); - dev->board_ptr = pci230_find_pci_board(pci_dev); - if (!dev->board_ptr) { + board = pci230_find_pci_board(pci_dev); + if (!board) { dev_err(dev->class_dev, "amplc_pci230: BUG! cannot determine board type!\n"); return -EINVAL; } - thisboard = dev->board_ptr; - dev->board_name = thisboard->name; + dev->board_ptr = board; + dev->board_name = board->name; rc = comedi_pci_enable(dev); if (rc) @@ -2414,15 +2414,15 @@ static int pci230_auto_attach(struct comedi_device *dev, unsigned short extfunc = 0; devpriv->hwver = inw(devpriv->daqio + PCI230P_HWVER); - if (devpriv->hwver < thisboard->min_hwver) { + if (devpriv->hwver < board->min_hwver) { dev_err(dev->class_dev, "%s - bad hardware version - got %u, need %u\n", dev->board_name, devpriv->hwver, - thisboard->min_hwver); + board->min_hwver); return -EIO; } if (devpriv->hwver > 0) { - if (!thisboard->have_dio) { + if (!board->have_dio) { /* * No DIO ports. Route counters' external gates * to the EXTTRIG signal (PCI260+ pin 17). @@ -2432,7 +2432,7 @@ static int pci230_auto_attach(struct comedi_device *dev, */ extfunc |= PCI230P_EXTFUNC_GAT_EXTTRIG; } - if (thisboard->ao_bits && devpriv->hwver >= 2) { + if (board->ao_bits && devpriv->hwver >= 2) { /* Enable DAC FIFO functionality. */ extfunc |= PCI230P2_EXTFUNC_DACFIFO; } @@ -2484,7 +2484,7 @@ static int pci230_auto_attach(struct comedi_device *dev, s->type = COMEDI_SUBD_AI; s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_GROUND; s->n_chan = 16; - s->maxdata = (1 << thisboard->ai_bits) - 1; + s->maxdata = (1 << board->ai_bits) - 1; s->range_table = &pci230_ai_range; s->insn_read = pci230_ai_insn_read; s->len_chanlist = 256; /* but there are restrictions. */ @@ -2498,11 +2498,11 @@ static int pci230_auto_attach(struct comedi_device *dev, s = &dev->subdevices[1]; /* analog output subdevice */ - if (thisboard->ao_bits) { + if (board->ao_bits) { s->type = COMEDI_SUBD_AO; s->subdev_flags = SDF_WRITABLE | SDF_GROUND; s->n_chan = 2; - s->maxdata = (1 << thisboard->ao_bits) - 1; + s->maxdata = (1 << board->ao_bits) - 1; s->range_table = &pci230_ao_range; s->insn_write = pci230_ao_insn_write; s->len_chanlist = 2; @@ -2523,7 +2523,7 @@ static int pci230_auto_attach(struct comedi_device *dev, s = &dev->subdevices[2]; /* digital i/o subdevice */ - if (thisboard->have_dio) { + if (board->have_dio) { rc = subdev_8255_init(dev, s, NULL, PCI230_PPI_X_BASE); if (rc) return rc; diff --git a/drivers/staging/comedi/drivers/cb_pcidas.c b/drivers/staging/comedi/drivers/cb_pcidas.c index e3591a5824fe..b43e836575fd 100644 --- a/drivers/staging/comedi/drivers/cb_pcidas.c +++ b/drivers/staging/comedi/drivers/cb_pcidas.c @@ -705,9 +705,9 @@ static int trimpot_8402_write(struct comedi_device *dev, unsigned int channel, static void cb_pcidas_trimpot_write(struct comedi_device *dev, unsigned int chan, unsigned int val) { - const struct cb_pcidas_board *thisboard = dev->board_ptr; + const struct cb_pcidas_board *board = dev->board_ptr; - switch (thisboard->trimpot) { + switch (board->trimpot) { case AD7376: trimpot_7376_write(dev, val); break; @@ -770,7 +770,7 @@ static int cb_pcidas_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_cmd *cmd) { - const struct cb_pcidas_board *thisboard = dev->board_ptr; + const struct cb_pcidas_board *board = dev->board_ptr; int err = 0; unsigned int arg; @@ -821,7 +821,7 @@ static int cb_pcidas_ai_cmdtest(struct comedi_device *dev, ~(CR_EDGE | CR_INVERT)); err |= -EINVAL; } - if (!thisboard->is_1602 && (cmd->start_arg & CR_INVERT)) { + if (!board->is_1602 && (cmd->start_arg & CR_INVERT)) { cmd->start_arg &= (CR_FLAGS_MASK & ~CR_INVERT); err |= -EINVAL; } @@ -830,13 +830,13 @@ static int cb_pcidas_ai_cmdtest(struct comedi_device *dev, if (cmd->scan_begin_src == TRIG_TIMER) { err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg, - thisboard->ai_speed * + board->ai_speed * cmd->chanlist_len); } if (cmd->convert_src == TRIG_TIMER) { err |= comedi_check_trigger_arg_min(&cmd->convert_arg, - thisboard->ai_speed); + board->ai_speed); } err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, @@ -879,7 +879,7 @@ static int cb_pcidas_ai_cmdtest(struct comedi_device *dev, static int cb_pcidas_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) { - const struct cb_pcidas_board *thisboard = dev->board_ptr; + const struct cb_pcidas_board *board = dev->board_ptr; struct cb_pcidas_private *devpriv = dev->private; struct comedi_async *async = s->async; struct comedi_cmd *cmd = &async->cmd; @@ -945,7 +945,7 @@ static int cb_pcidas_ai_cmd(struct comedi_device *dev, bits |= SW_TRIGGER; } else { /* TRIG_EXT */ bits |= EXT_TRIGGER | TGEN | XTRCL; - if (thisboard->is_1602) { + if (board->is_1602) { if (cmd->start_arg & CR_INVERT) bits |= TGPOL; if (cmd->start_arg & CR_EDGE) @@ -982,7 +982,7 @@ static int cb_pcidas_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_cmd *cmd) { - const struct cb_pcidas_board *thisboard = dev->board_ptr; + const struct cb_pcidas_board *board = dev->board_ptr; struct cb_pcidas_private *devpriv = dev->private; int err = 0; @@ -1014,7 +1014,7 @@ static int cb_pcidas_ao_cmdtest(struct comedi_device *dev, if (cmd->scan_begin_src == TRIG_TIMER) { err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg, - thisboard->ao_scan_speed); + board->ao_scan_speed); } err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, @@ -1090,7 +1090,7 @@ static int cb_pcidas_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, unsigned int trig_num) { - const struct cb_pcidas_board *thisboard = dev->board_ptr; + const struct cb_pcidas_board *board = dev->board_ptr; struct cb_pcidas_private *devpriv = dev->private; struct comedi_async *async = s->async; struct comedi_cmd *cmd = &async->cmd; @@ -1099,7 +1099,7 @@ static int cb_pcidas_ao_inttrig(struct comedi_device *dev, if (trig_num != cmd->start_arg) return -EINVAL; - cb_pcidas_ao_load_fifo(dev, s, thisboard->fifo_size); + cb_pcidas_ao_load_fifo(dev, s, board->fifo_size); /* enable dac half-full and empty interrupts */ spin_lock_irqsave(&dev->spinlock, flags); @@ -1197,7 +1197,7 @@ static int cb_pcidas_ao_cancel(struct comedi_device *dev, static void handle_ao_interrupt(struct comedi_device *dev, unsigned int status) { - const struct cb_pcidas_board *thisboard = dev->board_ptr; + const struct cb_pcidas_board *board = dev->board_ptr; struct cb_pcidas_private *devpriv = dev->private; struct comedi_subdevice *s = dev->write_subdev; struct comedi_async *async = s->async; @@ -1220,7 +1220,7 @@ static void handle_ao_interrupt(struct comedi_device *dev, unsigned int status) } } } else if (status & DAHFI) { - cb_pcidas_ao_load_fifo(dev, s, thisboard->fifo_size / 2); + cb_pcidas_ao_load_fifo(dev, s, board->fifo_size / 2); /* clear half-full interrupt latch */ spin_lock_irqsave(&dev->spinlock, flags); @@ -1235,13 +1235,13 @@ static void handle_ao_interrupt(struct comedi_device *dev, unsigned int status) static irqreturn_t cb_pcidas_interrupt(int irq, void *d) { struct comedi_device *dev = (struct comedi_device *)d; - const struct cb_pcidas_board *thisboard = dev->board_ptr; + const struct cb_pcidas_board *board = dev->board_ptr; struct cb_pcidas_private *devpriv = dev->private; struct comedi_subdevice *s = dev->read_subdev; struct comedi_async *async; struct comedi_cmd *cmd; int status, s5933_status; - int half_fifo = thisboard->fifo_size / 2; + int half_fifo = board->fifo_size / 2; unsigned int num_samples, i; static const int timeout = 10000; unsigned long flags; @@ -1338,18 +1338,18 @@ static int cb_pcidas_auto_attach(struct comedi_device *dev, unsigned long context) { struct pci_dev *pcidev = comedi_to_pci_dev(dev); - const struct cb_pcidas_board *thisboard = NULL; + const struct cb_pcidas_board *board = NULL; struct cb_pcidas_private *devpriv; struct comedi_subdevice *s; int i; int ret; if (context < ARRAY_SIZE(cb_pcidas_boards)) - thisboard = &cb_pcidas_boards[context]; - if (!thisboard) + board = &cb_pcidas_boards[context]; + if (!board) return -ENODEV; - dev->board_ptr = thisboard; - dev->board_name = thisboard->name; + dev->board_ptr = board; + dev->board_name = board->name; devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); if (!devpriv) @@ -1363,7 +1363,7 @@ static int cb_pcidas_auto_attach(struct comedi_device *dev, devpriv->control_status = pci_resource_start(pcidev, 1); devpriv->adc_fifo = pci_resource_start(pcidev, 2); dev->iobase = pci_resource_start(pcidev, 3); - if (thisboard->ao_nchan) + if (board->ao_nchan) devpriv->ao_registers = pci_resource_start(pcidev, 4); /* disable and clear interrupts on amcc s5933 */ @@ -1400,10 +1400,10 @@ static int cb_pcidas_auto_attach(struct comedi_device *dev, s->type = COMEDI_SUBD_AI; s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DIFF | SDF_CMD_READ; /* WARNING: Number of inputs in differential mode is ignored */ - s->n_chan = thisboard->ai_nchan; - s->len_chanlist = thisboard->ai_nchan; - s->maxdata = (1 << thisboard->ai_bits) - 1; - s->range_table = thisboard->ranges; + s->n_chan = board->ai_nchan; + s->len_chanlist = board->ai_nchan; + s->maxdata = (1 << board->ai_bits) - 1; + s->range_table = board->ranges; s->insn_read = cb_pcidas_ai_rinsn; s->insn_config = ai_config_insn; s->do_cmd = cb_pcidas_ai_cmd; @@ -1412,15 +1412,15 @@ static int cb_pcidas_auto_attach(struct comedi_device *dev, /* analog output subdevice */ s = &dev->subdevices[1]; - if (thisboard->ao_nchan) { + if (board->ao_nchan) { s->type = COMEDI_SUBD_AO; s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND; - s->n_chan = thisboard->ao_nchan; + s->n_chan = board->ao_nchan; /* * analog out resolution is the same as * analog input resolution, so use ai_bits */ - s->maxdata = (1 << thisboard->ai_bits) - 1; + s->maxdata = (1 << board->ai_bits) - 1; s->range_table = &cb_pcidas_ao_ranges; /* default to no fifo (*insn_write) */ s->insn_write = cb_pcidas_ao_nofifo_winsn; @@ -1429,7 +1429,7 @@ static int cb_pcidas_auto_attach(struct comedi_device *dev, if (ret) return ret; - if (thisboard->has_ao_fifo) { + if (board->has_ao_fifo) { dev->write_subdev = s; s->subdev_flags |= SDF_CMD_WRITE; /* use fifo (*insn_write) instead */ @@ -1477,7 +1477,7 @@ static int cb_pcidas_auto_attach(struct comedi_device *dev, s = &dev->subdevices[5]; s->type = COMEDI_SUBD_CALIB; s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; - if (thisboard->trimpot == AD7376) { + if (board->trimpot == AD7376) { s->n_chan = NUM_CHANNELS_7376; s->maxdata = 0x7f; } else { @@ -1497,7 +1497,7 @@ static int cb_pcidas_auto_attach(struct comedi_device *dev, /* dac08 caldac */ s = &dev->subdevices[6]; - if (thisboard->has_dac08) { + if (board->has_dac08) { s->type = COMEDI_SUBD_CALIB; s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; s->n_chan = NUM_CHANNELS_DAC08; diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c b/drivers/staging/comedi/drivers/cb_pcidas64.c index a94c33c3d962..d33b8fe872a7 100644 --- a/drivers/staging/comedi/drivers/cb_pcidas64.c +++ b/drivers/staging/comedi/drivers/cb_pcidas64.c @@ -155,8 +155,10 @@ static inline unsigned int dac_msb_4020_reg(unsigned int channel) } enum read_only_registers { - /* hardware status register, - * reading this apparently clears pending interrupts as well */ + /* + * hardware status register, + * reading this apparently clears pending interrupts as well + */ HW_STATUS_REG = 0x0, PIPE1_READ_REG = 0x4, ADC_READ_PNTR_REG = 0x8, @@ -243,7 +245,8 @@ enum adc_control0_contents { ADC_SOFT_GATE_BITS = 0x1, /* software gate */ ADC_EXT_GATE_BITS = 0x2, /* external digital gate */ ADC_ANALOG_GATE_BITS = 0x3, /* analog level gate */ - ADC_GATE_LEVEL_BIT = 0x4, /* level-sensitive gate (for digital) */ + /* level-sensitive gate (for digital) */ + ADC_GATE_LEVEL_BIT = 0x4, ADC_GATE_POLARITY_BIT = 0x8, /* gate active low */ ADC_START_TRIG_SOFT_BITS = 0x10, ADC_START_TRIG_EXT_BITS = 0x20, @@ -300,7 +303,8 @@ enum calibration_contents { CAL_GAIN_BIT = 0x800, }; -/* calibration sources for 6025 are: +/* + * calibration sources for 6025 are: * 0 : ground * 1 : 10V * 2 : 5V @@ -660,8 +664,10 @@ static const struct hw_fifo_info ai_fifo_60xx = { .fifo_size_reg_mask = 0x7f, }; -/* maximum number of dma transfers we will chain together into a ring - * (and the maximum number of dma buffers we maintain) */ +/* + * maximum number of dma transfers we will chain together into a ring + * (and the maximum number of dma buffers we maintain) + */ #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE) #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE) #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE) @@ -1100,10 +1106,10 @@ static const struct pcidas64_board pcidas64_boards[] = { static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev, int use_differential) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; - if ((thisboard->layout == LAYOUT_64XX && !use_differential) || - (thisboard->layout == LAYOUT_60XX && use_differential)) + if ((board->layout == LAYOUT_64XX && !use_differential) || + (board->layout == LAYOUT_60XX && use_differential)) return ADC_SE_DIFF_BIT; return 0; @@ -1176,17 +1182,17 @@ struct pcidas64_private { static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev, unsigned int range_index) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; - return thisboard->ai_range_code[range_index] << 8; + return board->ai_range_code[range_index] << 8; } static unsigned int hw_revision(const struct comedi_device *dev, uint16_t hw_status_bits) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; - if (thisboard->layout == LAYOUT_4020) + if (board->layout == LAYOUT_4020) return (hw_status_bits >> 13) & 0x7; return (hw_status_bits >> 12) & 0xf; @@ -1196,8 +1202,8 @@ static void set_dac_range_bits(struct comedi_device *dev, uint16_t *bits, unsigned int channel, unsigned int range) { - const struct pcidas64_board *thisboard = dev->board_ptr; - unsigned int code = thisboard->ao_range_code[range]; + const struct pcidas64_board *board = dev->board_ptr; + unsigned int code = board->ao_range_code[range]; if (channel > 1) dev_err(dev->class_dev, "bug! bad channel?\n"); @@ -1253,18 +1259,20 @@ static void disable_ai_interrupts(struct comedi_device *dev) static void enable_ai_interrupts(struct comedi_device *dev, const struct comedi_cmd *cmd) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; struct pcidas64_private *devpriv = dev->private; uint32_t bits; unsigned long flags; bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT | EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT; - /* Use pio transfer and interrupt on end of conversion - * if CMDF_WAKE_EOS flag is set. */ + /* + * Use pio transfer and interrupt on end of conversion + * if CMDF_WAKE_EOS flag is set. + */ if (cmd->flags & CMDF_WAKE_EOS) { /* 4020 doesn't support pio transfers except for fifo dregs */ - if (thisboard->layout != LAYOUT_4020) + if (board->layout != LAYOUT_4020) bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT; } spin_lock_irqsave(&dev->spinlock, flags); @@ -1277,7 +1285,7 @@ static void enable_ai_interrupts(struct comedi_device *dev, /* initialize plx9080 chip */ static void init_plx9080(struct comedi_device *dev) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; struct pcidas64_private *devpriv = dev->private; uint32_t bits; void __iomem *plx_iobase = devpriv->plx9080_iobase; @@ -1318,12 +1326,12 @@ static void init_plx9080(struct comedi_device *dev) /* enable local burst mode */ bits |= PLX_DMA_LOCAL_BURST_EN_BIT; /* 4020 uses 32 bit dma */ - if (thisboard->layout == LAYOUT_4020) + if (board->layout == LAYOUT_4020) bits |= PLX_LOCAL_BUS_32_WIDE_BITS; else /* localspace0 bus is 16 bits wide */ bits |= PLX_LOCAL_BUS_16_WIDE_BITS; writel(bits, plx_iobase + PLX_DMA1_MODE_REG); - if (ao_cmd_is_supported(thisboard)) + if (ao_cmd_is_supported(board)) writel(bits, plx_iobase + PLX_DMA0_MODE_REG); /* enable interrupts on plx 9080 */ @@ -1355,10 +1363,10 @@ static void disable_ai_pacing(struct comedi_device *dev) static int set_ai_fifo_segment_length(struct comedi_device *dev, unsigned int num_entries) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; struct pcidas64_private *devpriv = dev->private; static const int increment_size = 0x100; - const struct hw_fifo_info *const fifo = thisboard->ai_fifo; + const struct hw_fifo_info *const fifo = board->ai_fifo; unsigned int num_increments; uint16_t bits; @@ -1381,13 +1389,15 @@ static int set_ai_fifo_segment_length(struct comedi_device *dev, return devpriv->ai_fifo_segment_length; } -/* adjusts the size of hardware fifo (which determines block size for dma xfers) */ +/* + * adjusts the size of hardware fifo (which determines block size for dma xfers) + */ static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; unsigned int num_fifo_entries; int retval; - const struct hw_fifo_info *const fifo = thisboard->ai_fifo; + const struct hw_fifo_info *const fifo = board->ai_fifo; num_fifo_entries = num_samples / fifo->sample_packing_ratio; @@ -1405,25 +1415,27 @@ static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples) /* query length of fifo */ static unsigned int ai_fifo_size(struct comedi_device *dev) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; struct pcidas64_private *devpriv = dev->private; return devpriv->ai_fifo_segment_length * - thisboard->ai_fifo->num_segments * - thisboard->ai_fifo->sample_packing_ratio; + board->ai_fifo->num_segments * + board->ai_fifo->sample_packing_ratio; } static void init_stc_registers(struct comedi_device *dev) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; struct pcidas64_private *devpriv = dev->private; uint16_t bits; unsigned long flags; spin_lock_irqsave(&dev->spinlock, flags); - /* bit should be set for 6025, - * although docs say boards with <= 16 chans should be cleared XXX */ + /* + * bit should be set for 6025, + * although docs say boards with <= 16 chans should be cleared XXX + */ if (1) devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT; writew(devpriv->adc_control1_bits, @@ -1433,7 +1445,7 @@ static void init_stc_registers(struct comedi_device *dev) writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG); bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT; - if (thisboard->layout == LAYOUT_4020) + if (board->layout == LAYOUT_4020) bits |= INTERNAL_CLOCK_4020_BITS; devpriv->hw_config_bits |= bits; writew(devpriv->hw_config_bits, @@ -1446,8 +1458,7 @@ static void init_stc_registers(struct comedi_device *dev) /* set fifos to maximum size */ devpriv->fifo_size_bits |= DAC_FIFO_BITS; - set_ai_fifo_segment_length(dev, - thisboard->ai_fifo->max_segment_length); + set_ai_fifo_segment_length(dev, board->ai_fifo->max_segment_length); devpriv->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT; devpriv->intr_enable_bits = @@ -1461,13 +1472,13 @@ static void init_stc_registers(struct comedi_device *dev) static int alloc_and_init_dma_members(struct comedi_device *dev) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; struct pci_dev *pcidev = comedi_to_pci_dev(dev); struct pcidas64_private *devpriv = dev->private; int i; /* allocate pci dma buffers */ - for (i = 0; i < ai_dma_ring_count(thisboard); i++) { + for (i = 0; i < ai_dma_ring_count(board); i++) { devpriv->ai_buffer[i] = pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE, &devpriv->ai_buffer_bus_addr[i]); @@ -1475,7 +1486,7 @@ static int alloc_and_init_dma_members(struct comedi_device *dev) return -ENOMEM; } for (i = 0; i < AO_DMA_RING_COUNT; i++) { - if (ao_cmd_is_supported(thisboard)) { + if (ao_cmd_is_supported(board)) { devpriv->ao_buffer[i] = pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE, &devpriv-> @@ -1487,12 +1498,12 @@ static int alloc_and_init_dma_members(struct comedi_device *dev) /* allocate dma descriptors */ devpriv->ai_dma_desc = pci_alloc_consistent(pcidev, sizeof(struct plx_dma_desc) * - ai_dma_ring_count(thisboard), + ai_dma_ring_count(board), &devpriv->ai_dma_desc_bus_addr); if (!devpriv->ai_dma_desc) return -ENOMEM; - if (ao_cmd_is_supported(thisboard)) { + if (ao_cmd_is_supported(board)) { devpriv->ao_dma_desc = pci_alloc_consistent(pcidev, sizeof(struct plx_dma_desc) * @@ -1502,10 +1513,10 @@ static int alloc_and_init_dma_members(struct comedi_device *dev) return -ENOMEM; } /* initialize dma descriptors */ - for (i = 0; i < ai_dma_ring_count(thisboard); i++) { + for (i = 0; i < ai_dma_ring_count(board); i++) { devpriv->ai_dma_desc[i].pci_start_addr = cpu_to_le32(devpriv->ai_buffer_bus_addr[i]); - if (thisboard->layout == LAYOUT_4020) + if (board->layout == LAYOUT_4020) devpriv->ai_dma_desc[i].local_start_addr = cpu_to_le32(devpriv->local1_iobase + ADC_FIFO_REG); @@ -1516,12 +1527,12 @@ static int alloc_and_init_dma_members(struct comedi_device *dev) devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(0); devpriv->ai_dma_desc[i].next = cpu_to_le32((devpriv->ai_dma_desc_bus_addr + - ((i + 1) % ai_dma_ring_count(thisboard)) * + ((i + 1) % ai_dma_ring_count(board)) * sizeof(devpriv->ai_dma_desc[0])) | PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI); } - if (ao_cmd_is_supported(thisboard)) { + if (ao_cmd_is_supported(board)) { for (i = 0; i < AO_DMA_RING_COUNT; i++) { devpriv->ao_dma_desc[i].pci_start_addr = cpu_to_le32(devpriv->ao_buffer_bus_addr[i]); @@ -1542,7 +1553,7 @@ static int alloc_and_init_dma_members(struct comedi_device *dev) static void cb_pcidas64_free_dma(struct comedi_device *dev) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; struct pci_dev *pcidev = comedi_to_pci_dev(dev); struct pcidas64_private *devpriv = dev->private; int i; @@ -1551,7 +1562,7 @@ static void cb_pcidas64_free_dma(struct comedi_device *dev) return; /* free pci dma buffers */ - for (i = 0; i < ai_dma_ring_count(thisboard); i++) { + for (i = 0; i < ai_dma_ring_count(board); i++) { if (devpriv->ai_buffer[i]) pci_free_consistent(pcidev, DMA_BUFFER_SIZE, @@ -1569,7 +1580,7 @@ static void cb_pcidas64_free_dma(struct comedi_device *dev) if (devpriv->ai_dma_desc) pci_free_consistent(pcidev, sizeof(struct plx_dma_desc) * - ai_dma_ring_count(thisboard), + ai_dma_ring_count(board), devpriv->ai_dma_desc, devpriv->ai_dma_desc_bus_addr); if (devpriv->ao_dma_desc) @@ -1588,7 +1599,9 @@ static inline void warn_external_queue(struct comedi_device *dev) "Use internal AI channel queue (channels must be consecutive and use same range/aref)\n"); } -/* Their i2c requires a huge delay on setting clock or data high for some reason */ +/* + * their i2c requires a huge delay on setting clock or data high for some reason + */ static const int i2c_high_udelay = 1000; static const int i2c_low_udelay = 10; @@ -1684,8 +1697,10 @@ static void i2c_write(struct comedi_device *dev, unsigned int address, uint8_t bitstream; static const int read_bit = 0x1; - /* XXX need mutex to prevent simultaneous attempts to access - * eeprom and i2c bus */ + /* + * XXX need mutex to prevent simultaneous attempts to access + * eeprom and i2c bus + */ /* make sure we dont send anything to eeprom */ devpriv->plx_control_bits &= ~CTL_EE_CS; @@ -1720,12 +1735,12 @@ static int cb_pcidas64_ai_eoc(struct comedi_device *dev, struct comedi_insn *insn, unsigned long context) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; struct pcidas64_private *devpriv = dev->private; unsigned int status; status = readw(devpriv->main_iobase + HW_STATUS_REG); - if (thisboard->layout == LAYOUT_4020) { + if (board->layout == LAYOUT_4020) { status = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG); if (status) return 0; @@ -1739,7 +1754,7 @@ static int cb_pcidas64_ai_eoc(struct comedi_device *dev, static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; struct pcidas64_private *devpriv = dev->private; unsigned int bits = 0, n; unsigned int channel, range, aref; @@ -1763,7 +1778,7 @@ static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, devpriv->main_iobase + ADC_CONTROL1_REG); spin_unlock_irqrestore(&dev->spinlock, flags); - if (thisboard->layout != LAYOUT_4020) { + if (board->layout != LAYOUT_4020) { /* use internal queue */ devpriv->hw_config_bits &= ~EXT_QUEUE_BIT; writew(devpriv->hw_config_bits, @@ -1773,18 +1788,22 @@ static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, if (insn->chanspec & CR_ALT_SOURCE) { unsigned int cal_en_bit; - if (thisboard->layout == LAYOUT_60XX) + if (board->layout == LAYOUT_60XX) cal_en_bit = CAL_EN_60XX_BIT; else cal_en_bit = CAL_EN_64XX_BIT; - /* select internal reference source to connect - * to channel 0 */ + /* + * select internal reference source to connect + * to channel 0 + */ writew(cal_en_bit | adc_src_bits(devpriv->calibration_source), devpriv->main_iobase + CALIBRATION_REG); } else { - /* make sure internal calibration source - * is turned off */ + /* + * make sure internal calibration source + * is turned off + */ writew(0, devpriv->main_iobase + CALIBRATION_REG); } /* load internal queue */ @@ -1816,8 +1835,10 @@ static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, devpriv->i2c_cal_range_bits |= attenuate_bit(channel); else devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel); - /* update calibration/range i2c register only if necessary, - * as it is very slow */ + /* + * update calibration/range i2c register only if necessary, + * as it is very slow + */ if (old_cal_range_bits != devpriv->i2c_cal_range_bits) { uint8_t i2c_data = devpriv->i2c_cal_range_bits; @@ -1825,10 +1846,12 @@ static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, sizeof(i2c_data)); } - /* 4020 manual asks that sample interval register to be set + /* + * 4020 manual asks that sample interval register to be set * before writing to convert register. * Using somewhat arbitrary setting of 4 master clock ticks - * = 0.1 usec */ + * = 0.1 usec + */ writew(0, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG); writew(2, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG); } @@ -1846,7 +1869,7 @@ static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, if (ret) return ret; - if (thisboard->layout == LAYOUT_4020) + if (board->layout == LAYOUT_4020) data[n] = readl(dev->mmio + ADC_FIFO_REG) & 0xffff; else data[n] = readw(devpriv->main_iobase + PIPE1_READ_REG); @@ -1858,12 +1881,12 @@ static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, static int ai_config_calibration_source(struct comedi_device *dev, unsigned int *data) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; struct pcidas64_private *devpriv = dev->private; unsigned int source = data[1]; int num_calibration_sources; - if (thisboard->layout == LAYOUT_60XX) + if (board->layout == LAYOUT_60XX) num_calibration_sources = 16; else num_calibration_sources = 8; @@ -1880,9 +1903,9 @@ static int ai_config_calibration_source(struct comedi_device *dev, static int ai_config_block_size(struct comedi_device *dev, unsigned int *data) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; int fifo_size; - const struct hw_fifo_info *const fifo = thisboard->ai_fifo; + const struct hw_fifo_info *const fifo = board->ai_fifo; unsigned int block_size, requested_block_size; int retval; @@ -1933,9 +1956,9 @@ static int ai_config_master_clock_4020(struct comedi_device *dev, /* XXX could add support for 60xx series */ static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; - switch (thisboard->layout) { + switch (board->layout) { case LAYOUT_4020: return ai_config_master_clock_4020(dev, data); default: @@ -1963,9 +1986,11 @@ static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s, return -EINVAL; } -/* Gets nearest achievable timing given master clock speed, does not +/* + * Gets nearest achievable timing given master clock speed, does not * take into account possible minimum/maximum divisor values. Used - * by other timing checking functions. */ + * by other timing checking functions. + */ static unsigned int get_divisor(unsigned int ns, unsigned int flags) { unsigned int divisor; @@ -1985,13 +2010,15 @@ static unsigned int get_divisor(unsigned int ns, unsigned int flags) return divisor; } -/* utility function that rounds desired timing to an achievable time, and +/* + * utility function that rounds desired timing to an achievable time, and * sets cmd members appropriately. - * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number + * adc paces conversions from master clock by dividing by (x + 3) where x is + * 24 bit number */ static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; unsigned long long convert_divisor = 0; unsigned int scan_divisor; static const int min_convert_divisor = 3; @@ -2001,7 +2028,7 @@ static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd) unsigned long long max_scan_divisor, min_scan_divisor; if (cmd->convert_src == TRIG_TIMER) { - if (thisboard->layout == LAYOUT_4020) { + if (board->layout == LAYOUT_4020) { cmd->convert_arg = 0; } else { convert_divisor = get_divisor(cmd->convert_arg, @@ -2078,7 +2105,7 @@ static int cb_pcidas64_ai_check_chanlist(struct comedi_device *dev, static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_cmd *cmd) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; int err = 0; unsigned int tmp_arg, tmp_arg2; unsigned int triggers; @@ -2088,14 +2115,14 @@ static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT); triggers = TRIG_TIMER; - if (thisboard->layout == LAYOUT_4020) + if (board->layout == LAYOUT_4020) triggers |= TRIG_OTHER; else triggers |= TRIG_FOLLOW; err |= comedi_check_trigger_src(&cmd->scan_begin_src, triggers); triggers = TRIG_TIMER; - if (thisboard->layout == LAYOUT_4020) + if (board->layout == LAYOUT_4020) triggers |= TRIG_NOW; else triggers |= TRIG_EXT; @@ -2137,13 +2164,12 @@ static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, } if (cmd->convert_src == TRIG_TIMER) { - if (thisboard->layout == LAYOUT_4020) { + if (board->layout == LAYOUT_4020) { err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0); } else { err |= comedi_check_trigger_arg_min(&cmd->convert_arg, - thisboard-> - ai_speed); + board->ai_speed); /* * if scans are timed faster than conversion rate * allows @@ -2231,12 +2257,12 @@ static void setup_sample_counters(struct comedi_device *dev, static inline unsigned int dma_transfer_size(struct comedi_device *dev) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; struct pcidas64_private *devpriv = dev->private; unsigned int num_samples; num_samples = devpriv->ai_fifo_segment_length * - thisboard->ai_fifo->sample_packing_ratio; + board->ai_fifo->sample_packing_ratio; if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t)) num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t); @@ -2318,9 +2344,9 @@ static void select_master_clock_4020(struct comedi_device *dev, static void select_master_clock(struct comedi_device *dev, const struct comedi_cmd *cmd) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; - switch (thisboard->layout) { + switch (board->layout) { case LAYOUT_4020: select_master_clock_4020(dev, cmd); break; @@ -2350,7 +2376,7 @@ static inline void dma_start_sync(struct comedi_device *dev, static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; struct pcidas64_private *devpriv = dev->private; uint32_t convert_counter = 0, scan_counter = 0; @@ -2358,7 +2384,7 @@ static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd) select_master_clock(dev, cmd); - if (thisboard->layout == LAYOUT_4020) { + if (board->layout == LAYOUT_4020) { convert_counter = ai_convert_counter_4020(dev, cmd); } else { convert_counter = ai_convert_counter_6xxx(dev, cmd); @@ -2399,12 +2425,12 @@ static int use_internal_queue_6xxx(const struct comedi_cmd *cmd) static int setup_channel_queue(struct comedi_device *dev, const struct comedi_cmd *cmd) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; struct pcidas64_private *devpriv = dev->private; unsigned short bits; int i; - if (thisboard->layout != LAYOUT_4020) { + if (board->layout != LAYOUT_4020) { if (use_internal_queue_6xxx(cmd)) { devpriv->hw_config_bits &= ~EXT_QUEUE_BIT; writew(devpriv->hw_config_bits, @@ -2468,8 +2494,10 @@ static int setup_channel_queue(struct comedi_device *dev, devpriv->main_iobase + ADC_QUEUE_FIFO_REG); } - /* doing a queue clear is not specified in board docs, - * but required for reliable operation */ + /* + * doing a queue clear is not specified in board docs, + * but required for reliable operation + */ writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG); /* prime queue holding register */ writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG); @@ -2492,8 +2520,10 @@ static int setup_channel_queue(struct comedi_device *dev, devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel); } - /* update calibration/range i2c register only if necessary, - * as it is very slow */ + /* + * update calibration/range i2c register only if necessary, + * as it is very slow + */ if (old_cal_range_bits != devpriv->i2c_cal_range_bits) { uint8_t i2c_data = devpriv->i2c_cal_range_bits; @@ -2510,11 +2540,13 @@ static inline void load_first_dma_descriptor(struct comedi_device *dev, { struct pcidas64_private *devpriv = dev->private; - /* The transfer size, pci address, and local address registers + /* + * The transfer size, pci address, and local address registers * are supposedly unused during chained dma, * but I have found that left over values from last operation * occasionally cause problems with transfer of first dma - * block. Initializing them to zero seems to fix the problem. */ + * block. Initializing them to zero seems to fix the problem. + */ if (dma_channel) { writel(0, devpriv->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG); @@ -2536,7 +2568,7 @@ static inline void load_first_dma_descriptor(struct comedi_device *dev, static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; struct pcidas64_private *devpriv = dev->private; struct comedi_async *async = s->async; struct comedi_cmd *cmd = &async->cmd; @@ -2565,7 +2597,7 @@ static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) /* set mode, allow conversions through software gate */ devpriv->adc_control1_bits |= ADC_SW_GATE_BIT; devpriv->adc_control1_bits &= ~ADC_DITHER_BIT; - if (thisboard->layout != LAYOUT_4020) { + if (board->layout != LAYOUT_4020) { devpriv->adc_control1_bits &= ~ADC_MODE_MASK; if (cmd->convert_src == TRIG_EXT) /* good old mode 13 */ @@ -2595,11 +2627,11 @@ static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG); if ((cmd->flags & CMDF_WAKE_EOS) == 0 || - thisboard->layout == LAYOUT_4020) { + board->layout == LAYOUT_4020) { devpriv->ai_dma_index = 0; /* set dma transfer size */ - for (i = 0; i < ai_dma_ring_count(thisboard); i++) + for (i = 0; i < ai_dma_ring_count(board); i++) devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(dma_transfer_size(dev) * sizeof(uint16_t)); @@ -2614,7 +2646,7 @@ static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) dma_start_sync(dev, 1); } - if (thisboard->layout == LAYOUT_4020) { + if (board->layout == LAYOUT_4020) { /* set source for external triggers */ bits = 0; if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg)) @@ -2669,15 +2701,19 @@ static void pio_drain_ai_fifo_16(struct comedi_device *dev) 0x7fff; write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff; - /* Get most significant bits (grey code). + /* + * Get most significant bits (grey code). * Different boards use different code so use a scheme * that doesn't depend on encoding. This read must * occur after reading least significant 15 bits to avoid race - * with fifo switching to next segment. */ + * with fifo switching to next segment. + */ prepost_bits = readw(devpriv->main_iobase + PREPOST_REG); - /* if read and write pointers are not on the same fifo segment, - * read to the end of the read segment */ + /* + * if read and write pointers are not on the same fifo segment, + * read to the end of the read segment + */ read_segment = adc_upper_read_ptr_code(prepost_bits); write_segment = adc_upper_write_ptr_code(prepost_bits); @@ -2706,7 +2742,8 @@ static void pio_drain_ai_fifo_16(struct comedi_device *dev) } while (read_segment != write_segment); } -/* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of +/* + * Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of * pointers. The pci-4020 hardware only supports dma transfers (it only * supports the use of pio for draining the last remaining points from the * fifo when a data acquisition operation has completed). @@ -2744,9 +2781,9 @@ static void pio_drain_ai_fifo_32(struct comedi_device *dev) /* empty fifo */ static void pio_drain_ai_fifo(struct comedi_device *dev) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; - if (thisboard->layout == LAYOUT_4020) + if (board->layout == LAYOUT_4020) pio_drain_ai_fifo_32(dev); else pio_drain_ai_fifo_16(dev); @@ -2754,7 +2791,7 @@ static void pio_drain_ai_fifo(struct comedi_device *dev) static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; struct pcidas64_private *devpriv = dev->private; struct comedi_subdevice *s = dev->read_subdev; uint32_t next_transfer_addr; @@ -2775,24 +2812,26 @@ static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel) devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] || next_transfer_addr >= devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] + - DMA_BUFFER_SIZE) && j < ai_dma_ring_count(thisboard); j++) { + DMA_BUFFER_SIZE) && j < ai_dma_ring_count(board); j++) { /* transfer data from dma buffer to comedi buffer */ num_samples = comedi_nsamples_left(s, dma_transfer_size(dev)); comedi_buf_write_samples(s, devpriv->ai_buffer[devpriv->ai_dma_index], num_samples); devpriv->ai_dma_index = (devpriv->ai_dma_index + 1) % - ai_dma_ring_count(thisboard); + ai_dma_ring_count(board); } - /* XXX check for dma ring buffer overrun - * (use end-of-chain bit to mark last unused buffer) */ + /* + * XXX check for dma ring buffer overrun + * (use end-of-chain bit to mark last unused buffer) + */ } static void handle_ai_interrupt(struct comedi_device *dev, unsigned short status, unsigned int plx_status) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; struct pcidas64_private *devpriv = dev->private; struct comedi_subdevice *s = dev->read_subdev; struct comedi_async *async = s->async; @@ -2821,7 +2860,7 @@ static void handle_ai_interrupt(struct comedi_device *dev, if ((status & ADC_DONE_BIT) || ((cmd->flags & CMDF_WAKE_EOS) && (status & ADC_INTR_PENDING_BIT) && - (thisboard->layout != LAYOUT_4020))) { + (board->layout != LAYOUT_4020))) { spin_lock_irqsave(&dev->spinlock, flags); if (devpriv->ai_cmd_running) { spin_unlock_irqrestore(&dev->spinlock, flags); @@ -2933,8 +2972,10 @@ static unsigned int load_ao_dma_buffer(struct comedi_device *dev, next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next); next_bits |= PLX_END_OF_CHAIN_BIT; devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits); - /* clear end of chain bit on previous buffer now that we have set it - * for the last buffer */ + /* + * clear end of chain bit on previous buffer now that we have set it + * for the last buffer + */ next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next); next_bits &= ~PLX_END_OF_CHAIN_BIT; devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits); @@ -3027,9 +3068,11 @@ static irqreturn_t handle_interrupt(int irq, void *d) plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG); status = readw(devpriv->main_iobase + HW_STATUS_REG); - /* an interrupt before all the postconfig stuff gets done could + /* + * an interrupt before all the postconfig stuff gets done could * cause a NULL dereference if we continue through the - * interrupt handler */ + * interrupt handler + */ if (!dev->attached) return IRQ_HANDLED; @@ -3068,7 +3111,7 @@ static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s) static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; struct pcidas64_private *devpriv = dev->private; int chan = CR_CHAN(insn->chanspec); int range = CR_RANGE(insn->chanspec); @@ -3082,7 +3125,7 @@ static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, devpriv->main_iobase + DAC_CONTROL1_REG); /* write to channel */ - if (thisboard->layout == LAYOUT_4020) { + if (board->layout == LAYOUT_4020) { writew(data[0] & 0xff, devpriv->main_iobase + dac_lsb_4020_reg(chan)); writew((data[0] >> 8) & 0xf, @@ -3189,8 +3232,10 @@ static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd) unsigned int nbytes; int i; - /* clear queue pointer too, since external queue has - * weird interactions with ao fifo */ + /* + * clear queue pointer too, since external queue has + * weird interactions with ao fifo + */ writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG); writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG); @@ -3223,11 +3268,11 @@ static inline int external_ai_queue_in_use(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_cmd *cmd) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; if (s->busy) return 0; - if (thisboard->layout == LAYOUT_4020) + if (board->layout == LAYOUT_4020) return 0; else if (use_internal_queue_6xxx(cmd)) return 0; @@ -3306,7 +3351,7 @@ static int cb_pcidas64_ao_check_chanlist(struct comedi_device *dev, static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_cmd *cmd) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; int err = 0; unsigned int tmp_arg; @@ -3344,7 +3389,7 @@ static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, if (cmd->scan_begin_src == TRIG_TIMER) { err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg, - thisboard->ao_scan_speed); + board->ao_scan_speed); if (get_ao_divisor(cmd->scan_begin_arg, cmd->flags) > max_counter_value) { cmd->scan_begin_arg = (max_counter_value + 2) * @@ -3459,7 +3504,8 @@ static int dio_60xx_wbits(struct comedi_device *dev, return insn->n; } -/* pci-6025 8800 caldac: +/* + * pci-6025 8800 caldac: * address 0 == dac channel 0 offset * address 1 == dac channel 0 gain * address 2 == dac channel 1 offset @@ -3469,7 +3515,8 @@ static int dio_60xx_wbits(struct comedi_device *dev, * address 6 == coarse adc gain * address 7 == fine adc gain */ -/* pci-6402/16 uses all 8 channels for dac: +/* + * pci-6402/16 uses all 8 channels for dac: * address 0 == dac channel 0 fine gain * address 1 == dac channel 0 coarse gain * address 2 == dac channel 0 coarse offset @@ -3478,7 +3525,7 @@ static int dio_60xx_wbits(struct comedi_device *dev, * address 5 == dac channel 1 coarse gain * address 6 == dac channel 0 fine offset * address 7 == dac channel 1 fine offset -*/ + */ static int caldac_8800_write(struct comedi_device *dev, unsigned int address, uint8_t value) @@ -3575,9 +3622,9 @@ static int caldac_i2c_write(struct comedi_device *dev, static void caldac_write(struct comedi_device *dev, unsigned int channel, unsigned int value) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; - switch (thisboard->layout) { + switch (board->layout) { case LAYOUT_60XX: case LAYOUT_64XX: caldac_8800_write(dev, channel, value); @@ -3738,11 +3785,12 @@ static int eeprom_read_insn(struct comedi_device *dev, return 1; } -/* Allocate and initialize the subdevice structures. +/* + * Allocate and initialize the subdevice structures. */ static int setup_subdevices(struct comedi_device *dev) { - const struct pcidas64_board *thisboard = dev->board_ptr; + const struct pcidas64_board *board = dev->board_ptr; struct pcidas64_private *devpriv = dev->private; struct comedi_subdevice *s; int i; @@ -3757,24 +3805,26 @@ static int setup_subdevices(struct comedi_device *dev) dev->read_subdev = s; s->type = COMEDI_SUBD_AI; s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ; - if (thisboard->layout == LAYOUT_60XX) + if (board->layout == LAYOUT_60XX) s->subdev_flags |= SDF_COMMON | SDF_DIFF; - else if (thisboard->layout == LAYOUT_64XX) + else if (board->layout == LAYOUT_64XX) s->subdev_flags |= SDF_DIFF; /* XXX Number of inputs in differential mode is ignored */ - s->n_chan = thisboard->ai_se_chans; + s->n_chan = board->ai_se_chans; s->len_chanlist = 0x2000; - s->maxdata = (1 << thisboard->ai_bits) - 1; - s->range_table = thisboard->ai_range_table; + s->maxdata = (1 << board->ai_bits) - 1; + s->range_table = board->ai_range_table; s->insn_read = ai_rinsn; s->insn_config = ai_config_insn; s->do_cmd = ai_cmd; s->do_cmdtest = ai_cmdtest; s->cancel = ai_cancel; - if (thisboard->layout == LAYOUT_4020) { + if (board->layout == LAYOUT_4020) { uint8_t data; - /* set adc to read from inputs - * (not internal calibration sources) */ + /* + * set adc to read from inputs + * (not internal calibration sources) + */ devpriv->i2c_cal_range_bits = adc_src_4020_bits(4); /* set channels to +-5 volt input ranges */ for (i = 0; i < s->n_chan; i++) @@ -3785,24 +3835,24 @@ static int setup_subdevices(struct comedi_device *dev) /* analog output subdevice */ s = &dev->subdevices[1]; - if (thisboard->ao_nchan) { + if (board->ao_nchan) { s->type = COMEDI_SUBD_AO; s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND | SDF_CMD_WRITE; - s->n_chan = thisboard->ao_nchan; - s->maxdata = (1 << thisboard->ao_bits) - 1; - s->range_table = thisboard->ao_range_table; + s->n_chan = board->ao_nchan; + s->maxdata = (1 << board->ao_bits) - 1; + s->range_table = board->ao_range_table; s->insn_write = ao_winsn; ret = comedi_alloc_subdev_readback(s); if (ret) return ret; - if (ao_cmd_is_supported(thisboard)) { + if (ao_cmd_is_supported(board)) { dev->write_subdev = s; s->do_cmdtest = ao_cmdtest; s->do_cmd = ao_cmd; - s->len_chanlist = thisboard->ao_nchan; + s->len_chanlist = board->ao_nchan; s->cancel = ao_cancel; } } else { @@ -3811,7 +3861,7 @@ static int setup_subdevices(struct comedi_device *dev) /* digital input */ s = &dev->subdevices[2]; - if (thisboard->layout == LAYOUT_64XX) { + if (board->layout == LAYOUT_64XX) { s->type = COMEDI_SUBD_DI; s->subdev_flags = SDF_READABLE; s->n_chan = 4; @@ -3823,7 +3873,7 @@ static int setup_subdevices(struct comedi_device *dev) } /* digital output */ - if (thisboard->layout == LAYOUT_64XX) { + if (board->layout == LAYOUT_64XX) { s = &dev->subdevices[3]; s->type = COMEDI_SUBD_DO; s->subdev_flags = SDF_WRITABLE; @@ -3837,8 +3887,8 @@ static int setup_subdevices(struct comedi_device *dev) /* 8255 */ s = &dev->subdevices[4]; - if (thisboard->has_8255) { - if (thisboard->layout == LAYOUT_4020) { + if (board->has_8255) { + if (board->layout == LAYOUT_4020) { ret = subdev_8255_init(dev, s, dio_callback_4020, I8255_4020_REG); } else { @@ -3853,7 +3903,7 @@ static int setup_subdevices(struct comedi_device *dev) /* 8 channel dio for 60xx */ s = &dev->subdevices[5]; - if (thisboard->layout == LAYOUT_60XX) { + if (board->layout == LAYOUT_60XX) { s->type = COMEDI_SUBD_DIO; s->subdev_flags = SDF_WRITABLE | SDF_READABLE; s->n_chan = 8; @@ -3870,7 +3920,7 @@ static int setup_subdevices(struct comedi_device *dev) s->type = COMEDI_SUBD_CALIB; s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; s->n_chan = 8; - if (thisboard->layout == LAYOUT_4020) + if (board->layout == LAYOUT_4020) s->maxdata = 0xfff; else s->maxdata = 0xff; @@ -3887,7 +3937,7 @@ static int setup_subdevices(struct comedi_device *dev) /* 2 channel ad8402 potentiometer */ s = &dev->subdevices[7]; - if (thisboard->layout == LAYOUT_64XX) { + if (board->layout == LAYOUT_64XX) { s->type = COMEDI_SUBD_CALIB; s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; s->n_chan = 2; @@ -3929,16 +3979,16 @@ static int auto_attach(struct comedi_device *dev, unsigned long context) { struct pci_dev *pcidev = comedi_to_pci_dev(dev); - const struct pcidas64_board *thisboard = NULL; + const struct pcidas64_board *board = NULL; struct pcidas64_private *devpriv; uint32_t local_range, local_decode; int retval; if (context < ARRAY_SIZE(pcidas64_boards)) - thisboard = &pcidas64_boards[context]; - if (!thisboard) + board = &pcidas64_boards[context]; + if (!board) return -ENODEV; - dev->board_ptr = thisboard; + dev->board_ptr = board; devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); if (!devpriv) @@ -3950,7 +4000,7 @@ static int auto_attach(struct comedi_device *dev, pci_set_master(pcidev); /* Initialize dev->board_name */ - dev->board_name = thisboard->name; + dev->board_name = board->name; devpriv->main_phys_iobase = pci_resource_start(pcidev, 2); devpriv->dio_counter_phys_iobase = pci_resource_start(pcidev, 3); diff --git a/drivers/staging/comedi/drivers/cb_pcidda.c b/drivers/staging/comedi/drivers/cb_pcidda.c index 30c9e27d1ed9..b00a36a5cb36 100644 --- a/drivers/staging/comedi/drivers/cb_pcidda.c +++ b/drivers/staging/comedi/drivers/cb_pcidda.c @@ -335,18 +335,18 @@ static int cb_pcidda_auto_attach(struct comedi_device *dev, unsigned long context) { struct pci_dev *pcidev = comedi_to_pci_dev(dev); - const struct cb_pcidda_board *thisboard = NULL; + const struct cb_pcidda_board *board = NULL; struct cb_pcidda_private *devpriv; struct comedi_subdevice *s; int i; int ret; if (context < ARRAY_SIZE(cb_pcidda_boards)) - thisboard = &cb_pcidda_boards[context]; - if (!thisboard) + board = &cb_pcidda_boards[context]; + if (!board) return -ENODEV; - dev->board_ptr = thisboard; - dev->board_name = thisboard->name; + dev->board_ptr = board; + dev->board_name = board->name; devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); if (!devpriv) @@ -366,8 +366,8 @@ static int cb_pcidda_auto_attach(struct comedi_device *dev, /* analog output subdevice */ s->type = COMEDI_SUBD_AO; s->subdev_flags = SDF_WRITABLE; - s->n_chan = thisboard->ao_chans; - s->maxdata = (1 << thisboard->ao_bits) - 1; + s->n_chan = board->ao_chans; + s->maxdata = (1 << board->ao_bits) - 1; s->range_table = &cb_pcidda_ranges; s->insn_write = cb_pcidda_ao_insn_write; @@ -384,7 +384,7 @@ static int cb_pcidda_auto_attach(struct comedi_device *dev, devpriv->eeprom_data[i] = cb_pcidda_read_eeprom(dev, i); /* set calibrations dacs */ - for (i = 0; i < thisboard->ao_chans; i++) + for (i = 0; i < board->ao_chans; i++) cb_pcidda_calibrate(dev, i, devpriv->ao_range[i]); return 0; diff --git a/drivers/staging/comedi/drivers/cb_pcimdas.c b/drivers/staging/comedi/drivers/cb_pcimdas.c index c458e5010a74..4ebf5aae5019 100644 --- a/drivers/staging/comedi/drivers/cb_pcimdas.c +++ b/drivers/staging/comedi/drivers/cb_pcimdas.c @@ -243,7 +243,7 @@ static int cb_pcimdas_ao_insn_write(struct comedi_device *dev, return insn->n; } -static int cb_pcimdas_di_insn_read(struct comedi_device *dev, +static int cb_pcimdas_di_insn_bits(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data) @@ -258,7 +258,7 @@ static int cb_pcimdas_di_insn_read(struct comedi_device *dev, return insn->n; } -static int cb_pcimdas_do_insn_write(struct comedi_device *dev, +static int cb_pcimdas_do_insn_bits(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data) @@ -424,7 +424,7 @@ static int cb_pcimdas_auto_attach(struct comedi_device *dev, s->n_chan = 4; s->maxdata = 1; s->range_table = &range_digital; - s->insn_read = cb_pcimdas_di_insn_read; + s->insn_bits = cb_pcimdas_di_insn_bits; /* Digital Output subdevice (main connector) */ s = &dev->subdevices[4]; @@ -433,7 +433,7 @@ static int cb_pcimdas_auto_attach(struct comedi_device *dev, s->n_chan = 4; s->maxdata = 1; s->range_table = &range_digital; - s->insn_write = cb_pcimdas_do_insn_write; + s->insn_bits = cb_pcimdas_do_insn_bits; /* Counter subdevice (8254) */ s = &dev->subdevices[5]; diff --git a/drivers/staging/comedi/drivers/cb_pcimdda.c b/drivers/staging/comedi/drivers/cb_pcimdda.c index a4781dbbdd82..19210d89f2b2 100644 --- a/drivers/staging/comedi/drivers/cb_pcimdda.c +++ b/drivers/staging/comedi/drivers/cb_pcimdda.c @@ -164,11 +164,7 @@ static int cb_pcimdda_auto_attach(struct comedi_device *dev, s = &dev->subdevices[1]; /* digital i/o subdevice */ - ret = subdev_8255_init(dev, s, NULL, PCIMDDA_8255_BASE_REG); - if (ret) - return ret; - - return 0; + return subdev_8255_init(dev, s, NULL, PCIMDDA_8255_BASE_REG); } static struct comedi_driver cb_pcimdda_driver = { diff --git a/drivers/staging/comedi/drivers/comedi_8254.h b/drivers/staging/comedi/drivers/comedi_8254.h index d89f6d94f8aa..f4610ead6172 100644 --- a/drivers/staging/comedi/drivers/comedi_8254.h +++ b/drivers/staging/comedi/drivers/comedi_8254.h @@ -20,6 +20,12 @@ #ifndef _COMEDI_8254_H #define _COMEDI_8254_H +#include <linux/types.h> + +struct comedi_device; +struct comedi_insn; +struct comedi_subdevice; + /* * Common oscillator base values in nanoseconds */ diff --git a/drivers/staging/comedi/drivers/comedi_8255.c b/drivers/staging/comedi/drivers/comedi_8255.c new file mode 100644 index 000000000000..b2441efc61cc --- /dev/null +++ b/drivers/staging/comedi/drivers/comedi_8255.c @@ -0,0 +1,285 @@ +/* + * comedi_8255.c + * Generic 8255 digital I/O support + * + * Split from the Comedi "8255" driver module. + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 1998 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Module: comedi_8255 + * Description: Generic 8255 support + * Author: ds + * Updated: Fri, 22 May 2015 12:14:17 +0000 + * Status: works + * + * This module is not used directly by end-users. Rather, it is used by + * other drivers to provide support for an 8255 "Programmable Peripheral + * Interface" (PPI) chip. + * + * The classic in digital I/O. The 8255 appears in Comedi as a single + * digital I/O subdevice with 24 channels. The channel 0 corresponds to + * the 8255's port A, bit 0; channel 23 corresponds to port C, bit 7. + * Direction configuration is done in blocks, with channels 0-7, 8-15, + * 16-19, and 20-23 making up the 4 blocks. The only 8255 mode + * supported is mode 0. + */ + +#include <linux/module.h> +#include "../comedidev.h" + +#include "8255.h" + +struct subdev_8255_private { + unsigned long regbase; + int (*io)(struct comedi_device *dev, int dir, int port, int data, + unsigned long regbase); +}; + +static int subdev_8255_io(struct comedi_device *dev, + int dir, int port, int data, unsigned long regbase) +{ + if (dir) { + outb(data, dev->iobase + regbase + port); + return 0; + } + return inb(dev->iobase + regbase + port); +} + +static int subdev_8255_mmio(struct comedi_device *dev, + int dir, int port, int data, unsigned long regbase) +{ + if (dir) { + writeb(data, dev->mmio + regbase + port); + return 0; + } + return readb(dev->mmio + regbase + port); +} + +static int subdev_8255_insn(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) +{ + struct subdev_8255_private *spriv = s->private; + unsigned long regbase = spriv->regbase; + unsigned int mask; + unsigned int v; + + mask = comedi_dio_update_state(s, data); + if (mask) { + if (mask & 0xff) + spriv->io(dev, 1, I8255_DATA_A_REG, + s->state & 0xff, regbase); + if (mask & 0xff00) + spriv->io(dev, 1, I8255_DATA_B_REG, + (s->state >> 8) & 0xff, regbase); + if (mask & 0xff0000) + spriv->io(dev, 1, I8255_DATA_C_REG, + (s->state >> 16) & 0xff, regbase); + } + + v = spriv->io(dev, 0, I8255_DATA_A_REG, 0, regbase); + v |= (spriv->io(dev, 0, I8255_DATA_B_REG, 0, regbase) << 8); + v |= (spriv->io(dev, 0, I8255_DATA_C_REG, 0, regbase) << 16); + + data[1] = v; + + return insn->n; +} + +static void subdev_8255_do_config(struct comedi_device *dev, + struct comedi_subdevice *s) +{ + struct subdev_8255_private *spriv = s->private; + unsigned long regbase = spriv->regbase; + int config; + + config = I8255_CTRL_CW; + /* 1 in io_bits indicates output, 1 in config indicates input */ + if (!(s->io_bits & 0x0000ff)) + config |= I8255_CTRL_A_IO; + if (!(s->io_bits & 0x00ff00)) + config |= I8255_CTRL_B_IO; + if (!(s->io_bits & 0x0f0000)) + config |= I8255_CTRL_C_LO_IO; + if (!(s->io_bits & 0xf00000)) + config |= I8255_CTRL_C_HI_IO; + + spriv->io(dev, 1, I8255_CTRL_REG, config, regbase); +} + +static int subdev_8255_insn_config(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) +{ + unsigned int chan = CR_CHAN(insn->chanspec); + unsigned int mask; + int ret; + + if (chan < 8) + mask = 0x0000ff; + else if (chan < 16) + mask = 0x00ff00; + else if (chan < 20) + mask = 0x0f0000; + else + mask = 0xf00000; + + ret = comedi_dio_insn_config(dev, s, insn, data, mask); + if (ret) + return ret; + + subdev_8255_do_config(dev, s); + + return insn->n; +} + +static int __subdev_8255_init(struct comedi_device *dev, + struct comedi_subdevice *s, + int (*io)(struct comedi_device *dev, + int dir, int port, int data, + unsigned long regbase), + unsigned long regbase, + bool is_mmio) +{ + struct subdev_8255_private *spriv; + + spriv = comedi_alloc_spriv(s, sizeof(*spriv)); + if (!spriv) + return -ENOMEM; + + if (io) + spriv->io = io; + else if (is_mmio) + spriv->io = subdev_8255_mmio; + else + spriv->io = subdev_8255_io; + spriv->regbase = regbase; + + s->type = COMEDI_SUBD_DIO; + s->subdev_flags = SDF_READABLE | SDF_WRITABLE; + s->n_chan = 24; + s->range_table = &range_digital; + s->maxdata = 1; + s->insn_bits = subdev_8255_insn; + s->insn_config = subdev_8255_insn_config; + + subdev_8255_do_config(dev, s); + + return 0; +} + +/** + * subdev_8255_init - initialize DIO subdevice for driving I/O mapped 8255 + * @dev: comedi device owning subdevice + * @s: comedi subdevice to initialize + * @io: (optional) register I/O call-back function + * @regbase: offset of 8255 registers from dev->iobase, or call-back context + * + * Initializes a comedi subdevice as a DIO subdevice driving an 8255 chip. + * + * If the optional I/O call-back function is provided, its prototype is of + * the following form: + * + * int my_8255_callback(struct comedi_device *dev, int dir, int port, + * int data, unsigned long regbase); + * + * where 'dev', and 'regbase' match the values passed to this function, + * 'port' is the 8255 port number 0 to 3 (including the control port), 'dir' + * is the direction (0 for read, 1 for write) and 'data' is the value to be + * written. It should return 0 if writing or the value read if reading. + * + * If the optional I/O call-back function is not provided, an internal + * call-back function is used which uses consecutive I/O port addresses + * starting at dev->iobase + regbase. + * + * Return: -ENOMEM if failed to allocate memory, zero on success. + */ +int subdev_8255_init(struct comedi_device *dev, struct comedi_subdevice *s, + int (*io)(struct comedi_device *dev, int dir, int port, + int data, unsigned long regbase), + unsigned long regbase) +{ + return __subdev_8255_init(dev, s, io, regbase, false); +} +EXPORT_SYMBOL_GPL(subdev_8255_init); + +/** + * subdev_8255_mm_init - initialize DIO subdevice for driving mmio-mapped 8255 + * @dev: comedi device owning subdevice + * @s: comedi subdevice to initialize + * @io: (optional) register I/O call-back function + * @regbase: offset of 8255 registers from dev->mmio, or call-back context + * + * Initializes a comedi subdevice as a DIO subdevice driving an 8255 chip. + * + * If the optional I/O call-back function is provided, its prototype is of + * the following form: + * + * int my_8255_callback(struct comedi_device *dev, int dir, int port, + * int data, unsigned long regbase); + * + * where 'dev', and 'regbase' match the values passed to this function, + * 'port' is the 8255 port number 0 to 3 (including the control port), 'dir' + * is the direction (0 for read, 1 for write) and 'data' is the value to be + * written. It should return 0 if writing or the value read if reading. + * + * If the optional I/O call-back function is not provided, an internal + * call-back function is used which uses consecutive MMIO virtual addresses + * starting at dev->mmio + regbase. + * + * Return: -ENOMEM if failed to allocate memory, zero on success. + */ +int subdev_8255_mm_init(struct comedi_device *dev, struct comedi_subdevice *s, + int (*io)(struct comedi_device *dev, int dir, int port, + int data, unsigned long regbase), + unsigned long regbase) +{ + return __subdev_8255_init(dev, s, io, regbase, true); +} +EXPORT_SYMBOL_GPL(subdev_8255_mm_init); + +/** + * subdev_8255_regbase - get offset of 8255 registers or call-back context + * @s: comedi subdevice + * + * Returns the 'regbase' parameter that was previously passed to to + * subdev_8255_init() or subdev_8255_mm_init() to set up the subdevice. + * Only valid if the subdevice was set up successfully. + */ +unsigned long subdev_8255_regbase(struct comedi_subdevice *s) +{ + struct subdev_8255_private *spriv = s->private; + + return spriv->regbase; +} +EXPORT_SYMBOL_GPL(subdev_8255_regbase); + +static int __init comedi_8255_module_init(void) +{ + return 0; +} +module_init(comedi_8255_module_init); + +static void __exit comedi_8255_module_exit(void) +{ +} +module_exit(comedi_8255_module_exit); + +MODULE_AUTHOR("Comedi http://www.comedi.org"); +MODULE_DESCRIPTION("Comedi: Generic 8255 digital I/O support"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/comedi/drivers/comedi_bond.c b/drivers/staging/comedi/drivers/comedi_bond.c index 96db0c2686a1..50b76eccb7d7 100644 --- a/drivers/staging/comedi/drivers/comedi_bond.c +++ b/drivers/staging/comedi/drivers/comedi_bond.c @@ -101,7 +101,8 @@ static int bonding_dio_insn_bits(struct comedi_device *dev, b_chans = bdev->nchans - base_chan; if (b_chans > n_left) b_chans = n_left; - b_mask = (1U << b_chans) - 1; + b_mask = (b_chans < 32) ? ((1 << b_chans) - 1) + : 0xffffffff; b_write_mask = (write_mask >> n_done) & b_mask; b_data_bits = (data_bits >> n_done) & b_mask; /* Read/Write the new digital lines. */ diff --git a/drivers/staging/comedi/drivers/comedi_isadma.h b/drivers/staging/comedi/drivers/comedi_isadma.h index c7c524faf595..2fb6573ba9e4 100644 --- a/drivers/staging/comedi/drivers/comedi_isadma.h +++ b/drivers/staging/comedi/drivers/comedi_isadma.h @@ -16,6 +16,10 @@ #ifndef _COMEDI_ISADMA_H #define _COMEDI_ISADMA_H +#include <linux/types.h> + +struct comedi_device; + /* * These are used to avoid issues when <asm/dma.h> and the DMA_MODE_ * defines are not available. diff --git a/drivers/staging/comedi/drivers/daqboard2000.c b/drivers/staging/comedi/drivers/daqboard2000.c index f97d18d92255..611b0a3ef5d7 100644 --- a/drivers/staging/comedi/drivers/daqboard2000.c +++ b/drivers/staging/comedi/drivers/daqboard2000.c @@ -1,105 +1,105 @@ /* - comedi/drivers/daqboard2000.c - hardware driver for IOtech DAQboard/2000 - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 1999 Anders Blomdell <anders.blomdell@control.lth.se> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. + * comedi/drivers/daqboard2000.c + * hardware driver for IOtech DAQboard/2000 + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 1999 Anders Blomdell <anders.blomdell@control.lth.se> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ /* -Driver: daqboard2000 -Description: IOTech DAQBoard/2000 -Author: Anders Blomdell <anders.blomdell@control.lth.se> -Status: works -Updated: Mon, 14 Apr 2008 15:28:52 +0100 -Devices: [IOTech] DAQBoard/2000 (daqboard2000) - -Much of the functionality of this driver was determined from reading -the source code for the Windows driver. - -The FPGA on the board requires fimware, which is available from -http://www.comedi.org in the comedi_nonfree_firmware tarball. - -Configuration options: not applicable, uses PCI auto config -*/ + * Driver: daqboard2000 + * Description: IOTech DAQBoard/2000 + * Author: Anders Blomdell <anders.blomdell@control.lth.se> + * Status: works + * Updated: Mon, 14 Apr 2008 15:28:52 +0100 + * Devices: [IOTech] DAQBoard/2000 (daqboard2000) + * + * Much of the functionality of this driver was determined from reading + * the source code for the Windows driver. + * + * The FPGA on the board requires fimware, which is available from + * http://www.comedi.org in the comedi_nonfree_firmware tarball. + * + * Configuration options: not applicable, uses PCI auto config + */ /* - This card was obviously never intended to leave the Windows world, - since it lacked all kind of hardware documentation (except for cable - pinouts, plug and pray has something to catch up with yet). - - With some help from our swedish distributor, we got the Windows sourcecode - for the card, and here are the findings so far. - - 1. A good document that describes the PCI interface chip is 9080db-106.pdf - available from http://www.plxtech.com/products/io/pci9080 - - 2. The initialization done so far is: - a. program the FPGA (windows code sans a lot of error messages) - b. - - 3. Analog out seems to work OK with DAC's disabled, if DAC's are enabled, - you have to output values to all enabled DAC's until result appears, I - guess that it has something to do with pacer clocks, but the source - gives me no clues. I'll keep it simple so far. - - 4. Analog in. - Each channel in the scanlist seems to be controlled by four - control words: - - Word0: - +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - ! | | | ! | | | ! | | | ! | | | ! - +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - - Word1: - +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - ! | | | ! | | | ! | | | ! | | | ! - +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - | | | | | | | - +------+------+ | | | | +-- Digital input (??) - | | | | +---- 10 us settling time - | | | +------ Suspend acquisition (last to scan) - | | +-------- Simultaneous sample and hold - | +---------- Signed data format - +------------------------- Correction offset low - - Word2: - +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - ! | | | ! | | | ! | | | ! | | | ! - +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - | | | | | | | | | | - +-----+ +--+--+ +++ +++ +--+--+ - | | | | +----- Expansion channel - | | | +----------- Expansion gain - | | +--------------- Channel (low) - | +--------------------- Correction offset high - +----------------------------- Correction gain low - Word3: - +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - ! | | | ! | | | ! | | | ! | | | ! - +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - | | | | | | | | | - +------+------+ | | +-+-+ | | +-- Low bank enable - | | | | | +---- High bank enable - | | | | +------ Hi/low select - | | | +---------- Gain (1,?,2,4,8,16,32,64) - | | +-------------- differential/single ended - | +---------------- Unipolar - +------------------------- Correction gain high - - 999. The card seems to have an incredible amount of capabilities, but - trying to reverse engineer them from the Windows source is beyond my - patience. - + * This card was obviously never intended to leave the Windows world, + * since it lacked all kind of hardware documentation (except for cable + * pinouts, plug and pray has something to catch up with yet). + * + * With some help from our swedish distributor, we got the Windows sourcecode + * for the card, and here are the findings so far. + * + * 1. A good document that describes the PCI interface chip is 9080db-106.pdf + * available from http://www.plxtech.com/products/io/pci9080 + * + * 2. The initialization done so far is: + * a. program the FPGA (windows code sans a lot of error messages) + * b. + * + * 3. Analog out seems to work OK with DAC's disabled, if DAC's are enabled, + * you have to output values to all enabled DAC's until result appears, I + * guess that it has something to do with pacer clocks, but the source + * gives me no clues. I'll keep it simple so far. + * + * 4. Analog in. + * Each channel in the scanlist seems to be controlled by four + * control words: + * + * Word0: + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * ! | | | ! | | | ! | | | ! | | | ! + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * + * Word1: + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * ! | | | ! | | | ! | | | ! | | | ! + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | | | | | | | + * +------+------+ | | | | +-- Digital input (??) + * | | | | +---- 10 us settling time + * | | | +------ Suspend acquisition (last to scan) + * | | +-------- Simultaneous sample and hold + * | +---------- Signed data format + * +------------------------- Correction offset low + * + * Word2: + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * ! | | | ! | | | ! | | | ! | | | ! + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | | | | | | | | | | + * +-----+ +--+--+ +++ +++ +--+--+ + * | | | | +----- Expansion channel + * | | | +----------- Expansion gain + * | | +--------------- Channel (low) + * | +--------------------- Correction offset high + * +----------------------------- Correction gain low + * Word3: + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * ! | | | ! | | | ! | | | ! | | | ! + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | | | | | | | | | + * +------+------+ | | +-+-+ | | +-- Low bank enable + * | | | | | +---- High bank enable + * | | | | +------ Hi/low select + * | | | +---------- Gain (1,?,2,4,8,16,32,64) + * | | +-------------- differential/single ended + * | +---------------- Unipolar + * +------------------------- Correction gain high + * + * 999. The card seems to have an incredible amount of capabilities, but + * trying to reverse engineer them from the Windows source is beyond my + * patience. + * */ #include <linux/module.h> diff --git a/drivers/staging/comedi/drivers/das08.c b/drivers/staging/comedi/drivers/das08.c index 73f4c8dbbde3..3d8fc6ad44df 100644 --- a/drivers/staging/comedi/drivers/das08.c +++ b/drivers/staging/comedi/drivers/das08.c @@ -1,21 +1,21 @@ /* - * comedi/drivers/das08.c - * comedi module for common DAS08 support (used by ISA/PCI/PCMCIA drivers) + * comedi/drivers/das08.c + * comedi module for common DAS08 support (used by ISA/PCI/PCMCIA drivers) * - * COMEDI - Linux Control and Measurement Device Interface - * Copyright (C) 2000 David A. Schleef <ds@schleef.org> - * Copyright (C) 2001,2002,2003 Frank Mori Hess <fmhess@users.sourceforge.net> - * Copyright (C) 2004 Salvador E. Tropea <set@users.sf.net> <set@ieee.org> + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 2000 David A. Schleef <ds@schleef.org> + * Copyright (C) 2001,2002,2003 Frank Mori Hess <fmhess@users.sourceforge.net> + * Copyright (C) 2004 Salvador E. Tropea <set@users.sf.net> <set@ieee.org> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #include <linux/module.h> @@ -27,85 +27,74 @@ #include "das08.h" /* - cio-das08.pdf - - "isa-das08" - - 0 a/d bits 0-3 start 8 bit - 1 a/d bits 4-11 start 12 bit - 2 eoc, ip1-3, irq, mux op1-4, inte, mux - 3 unused unused - 4567 8254 - 89ab 8255 - - requires hard-wiring for async ai - -*/ - -#define DAS08_LSB 0 -#define DAS08_MSB 1 -#define DAS08_TRIG_12BIT 1 -#define DAS08_STATUS 2 -#define DAS08_EOC (1<<7) -#define DAS08_IRQ (1<<3) -#define DAS08_IP(x) (((x)>>4)&0x7) -#define DAS08_CONTROL 2 -#define DAS08_MUX_MASK 0x7 -#define DAS08_MUX(x) ((x) & DAS08_MUX_MASK) -#define DAS08_INTE (1<<3) -#define DAS08_DO_MASK 0xf0 -#define DAS08_OP(x) (((x) << 4) & DAS08_DO_MASK) - + * Data format of DAS08_AI_LSB_REG and DAS08_AI_MSB_REG depends on + * 'ai_encoding' member of board structure: + * + * das08_encode12 : DATA[11..4] = MSB[7..0], DATA[3..0] = LSB[7..4]. + * das08_pcm_encode12 : DATA[11..8] = MSB[3..0], DATA[7..9] = LSB[7..0]. + * das08_encode16 : SIGN = MSB[7], MAGNITUDE[14..8] = MSB[6..0], + * MAGNITUDE[7..0] = LSB[7..0]. + * SIGN==0 for negative input, SIGN==1 for positive input. + * Note: when read a second time after conversion + * complete, MSB[7] is an "over-range" bit. + */ +#define DAS08_AI_LSB_REG 0x00 /* (R) AI least significant bits */ +#define DAS08_AI_MSB_REG 0x01 /* (R) AI most significant bits */ +#define DAS08_AI_TRIG_REG 0x01 /* (W) AI software trigger */ +#define DAS08_STATUS_REG 0x02 /* (R) status */ +#define DAS08_STATUS_AI_BUSY BIT(7) /* AI conversion in progress */ /* - cio-das08jr.pdf - - "das08/jr-ao" - - 0 a/d bits 0-3 unused - 1 a/d bits 4-11 start 12 bit - 2 eoc, mux mux - 3 di do - 4 unused ao0_lsb - 5 unused ao0_msb - 6 unused ao1_lsb - 7 unused ao1_msb - -*/ - -#define DAS08JR_DIO 3 -#define DAS08JR_AO_LSB(x) ((x) ? 6 : 4) -#define DAS08JR_AO_MSB(x) ((x) ? 7 : 5) + * The IRQ status bit is set to 1 by a rising edge on the external interrupt + * input (which may be jumpered to the pacer output). It is cleared by + * setting the INTE control bit to 0. Not present on "JR" boards. + */ +#define DAS08_STATUS_IRQ BIT(3) /* latched interrupt input */ +/* digital inputs (not "JR" boards) */ +#define DAS08_STATUS_DI(x) (((x) & 0x70) >> 4) +#define DAS08_CONTROL_REG 0x02 /* (W) control */ +/* + * Note: The AI multiplexor channel can also be read from status register using + * the same mask. + */ +#define DAS08_CONTROL_MUX_MASK 0x7 /* multiplexor channel mask */ +#define DAS08_CONTROL_MUX(x) ((x) & DAS08_CONTROL_MUX_MASK) /* mux channel */ +#define DAS08_CONTROL_INTE BIT(3) /* interrupt enable (not "JR" boards) */ +#define DAS08_CONTROL_DO_MASK 0xf0 /* digital outputs mask (not "JR") */ +/* digital outputs (not "JR" boards) */ +#define DAS08_CONTROL_DO(x) (((x) << 4) & DAS08_CONTROL_DO_MASK) +/* + * (R/W) programmable AI gain ("PGx" and "AOx" boards): + * + bits 3..0 (R/W) show/set the gain for the current AI mux channel + * + bits 6..4 (R) show the current AI mux channel + * + bit 7 (R) not unused + */ +#define DAS08_GAIN_REG 0x03 + +#define DAS08JR_DI_REG 0x03 /* (R) digital inputs ("JR" boards) */ +#define DAS08JR_DO_REG 0x03 /* (W) digital outputs ("JR" boards) */ +/* (W) analog output l.s.b. registers for 2 channels ("JR" boards) */ +#define DAS08JR_AO_LSB_REG(x) ((x) ? 0x06 : 0x04) +/* (W) analog output m.s.b. registers for 2 channels ("JR" boards) */ +#define DAS08JR_AO_MSB_REG(x) ((x) ? 0x07 : 0x05) +/* + * (R) update analog outputs ("JR" boards set for simultaneous output) + * (same register as digital inputs) + */ +#define DAS08JR_AO_UPDATE_REG 0x03 +/* (W) analog output l.s.b. registers for 2 channels ("AOx" boards) */ +#define DAS08AOX_AO_LSB_REG(x) ((x) ? 0x0a : 0x08) +/* (W) analog output m.s.b. registers for 2 channels ("AOx" boards) */ +#define DAS08AOX_AO_MSB_REG(x) ((x) ? 0x0b : 0x09) /* - cio-das08_aox.pdf - - "das08-aoh" - "das08-aol" - "das08-aom" - - 0 a/d bits 0-3 start 8 bit - 1 a/d bits 4-11 start 12 bit - 2 eoc, ip1-3, irq, mux op1-4, inte, mux - 3 mux, gain status gain control - 4567 8254 - 8 unused ao0_lsb - 9 unused ao0_msb - a unused ao1_lsb - b unused ao1_msb - 89ab - cdef 8255 -*/ - -#define DAS08AO_GAIN_CONTROL 3 -#define DAS08AO_GAIN_STATUS 3 - -#define DAS08AO_AO_LSB(x) ((x) ? 0xa : 8) -#define DAS08AO_AO_MSB(x) ((x) ? 0xb : 9) -#define DAS08AO_AO_UPDATE 8 + * (R) update analog outputs ("AOx" boards set for simultaneous output) + * (any of the analog output registers could be used for this) + */ +#define DAS08AOX_AO_UPDATE_REG 0x08 /* gainlist same as _pgx_ below */ -static const struct comedi_lrange range_das08_pgl = { +static const struct comedi_lrange das08_pgl_ai_range = { 9, { BIP_RANGE(10), BIP_RANGE(5), @@ -119,7 +108,7 @@ static const struct comedi_lrange range_das08_pgl = { } }; -static const struct comedi_lrange range_das08_pgh = { +static const struct comedi_lrange das08_pgh_ai_range = { 12, { BIP_RANGE(10), BIP_RANGE(5), @@ -136,7 +125,7 @@ static const struct comedi_lrange range_das08_pgh = { } }; -static const struct comedi_lrange range_das08_pgm = { +static const struct comedi_lrange das08_pgm_ai_range = { 9, { BIP_RANGE(10), BIP_RANGE(5), @@ -148,42 +137,28 @@ static const struct comedi_lrange range_das08_pgm = { UNI_RANGE(0.1), UNI_RANGE(0.01) } -}; /* - cio-das08jr.pdf - - "das08/jr-ao" - - 0 a/d bits 0-3 unused - 1 a/d bits 4-11 start 12 bit - 2 eoc, mux mux - 3 di do - 4 unused ao0_lsb - 5 unused ao0_msb - 6 unused ao1_lsb - 7 unused ao1_msb - - */ +}; static const struct comedi_lrange *const das08_ai_lranges[] = { - &range_unknown, - &range_bipolar5, - &range_das08_pgh, - &range_das08_pgl, - &range_das08_pgm, + [das08_pg_none] = &range_unknown, + [das08_bipolar5] = &range_bipolar5, + [das08_pgh] = &das08_pgh_ai_range, + [das08_pgl] = &das08_pgl_ai_range, + [das08_pgm] = &das08_pgm_ai_range, }; -static const int das08_pgh_gainlist[] = { +static const int das08_pgh_ai_gainlist[] = { 8, 0, 10, 2, 12, 4, 14, 6, 1, 3, 5, 7 }; -static const int das08_pgl_gainlist[] = { 8, 0, 2, 4, 6, 1, 3, 5, 7 }; -static const int das08_pgm_gainlist[] = { 8, 0, 10, 12, 14, 9, 11, 13, 15 }; - -static const int *const das08_gainlists[] = { - NULL, - NULL, - das08_pgh_gainlist, - das08_pgl_gainlist, - das08_pgm_gainlist, +static const int das08_pgl_ai_gainlist[] = { 8, 0, 2, 4, 6, 1, 3, 5, 7 }; +static const int das08_pgm_ai_gainlist[] = { 8, 0, 10, 12, 14, 9, 11, 13, 15 }; + +static const int *const das08_ai_gainlists[] = { + [das08_pg_none] = NULL, + [das08_bipolar5] = NULL, + [das08_pgh] = das08_pgh_ai_gainlist, + [das08_pgl] = das08_pgl_ai_gainlist, + [das08_pgm] = das08_pgm_ai_gainlist, }; static int das08_ai_eoc(struct comedi_device *dev, @@ -193,16 +168,17 @@ static int das08_ai_eoc(struct comedi_device *dev, { unsigned int status; - status = inb(dev->iobase + DAS08_STATUS); - if ((status & DAS08_EOC) == 0) + status = inb(dev->iobase + DAS08_STATUS_REG); + if ((status & DAS08_STATUS_AI_BUSY) == 0) return 0; return -EBUSY; } -static int das08_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) +static int das08_ai_insn_read(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, unsigned int *data) { - const struct das08_board_struct *thisboard = dev->board_ptr; + const struct das08_board_struct *board = dev->board_ptr; struct das08_private_struct *devpriv = dev->private; int n; int chan; @@ -214,49 +190,64 @@ static int das08_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, range = CR_RANGE(insn->chanspec); /* clear crap */ - inb(dev->iobase + DAS08_LSB); - inb(dev->iobase + DAS08_MSB); + inb(dev->iobase + DAS08_AI_LSB_REG); + inb(dev->iobase + DAS08_AI_MSB_REG); /* set multiplexer */ - /* lock to prevent race with digital output */ + /* lock to prevent race with digital output */ spin_lock(&dev->spinlock); - devpriv->do_mux_bits &= ~DAS08_MUX_MASK; - devpriv->do_mux_bits |= DAS08_MUX(chan); - outb(devpriv->do_mux_bits, dev->iobase + DAS08_CONTROL); + devpriv->do_mux_bits &= ~DAS08_CONTROL_MUX_MASK; + devpriv->do_mux_bits |= DAS08_CONTROL_MUX(chan); + outb(devpriv->do_mux_bits, dev->iobase + DAS08_CONTROL_REG); spin_unlock(&dev->spinlock); - if (s->range_table->length > 1) { + if (devpriv->pg_gainlist) { /* set gain/range */ range = CR_RANGE(insn->chanspec); outb(devpriv->pg_gainlist[range], - dev->iobase + DAS08AO_GAIN_CONTROL); + dev->iobase + DAS08_GAIN_REG); } for (n = 0; n < insn->n; n++) { /* clear over-range bits for 16-bit boards */ - if (thisboard->ai_nbits == 16) - if (inb(dev->iobase + DAS08_MSB) & 0x80) + if (board->ai_nbits == 16) + if (inb(dev->iobase + DAS08_AI_MSB_REG) & 0x80) dev_info(dev->class_dev, "over-range\n"); /* trigger conversion */ - outb_p(0, dev->iobase + DAS08_TRIG_12BIT); + outb_p(0, dev->iobase + DAS08_AI_TRIG_REG); ret = comedi_timeout(dev, s, insn, das08_ai_eoc, 0); if (ret) return ret; - msb = inb(dev->iobase + DAS08_MSB); - lsb = inb(dev->iobase + DAS08_LSB); - if (thisboard->ai_encoding == das08_encode12) { + msb = inb(dev->iobase + DAS08_AI_MSB_REG); + lsb = inb(dev->iobase + DAS08_AI_LSB_REG); + if (board->ai_encoding == das08_encode12) { data[n] = (lsb >> 4) | (msb << 4); - } else if (thisboard->ai_encoding == das08_pcm_encode12) { + } else if (board->ai_encoding == das08_pcm_encode12) { data[n] = (msb << 8) + lsb; - } else if (thisboard->ai_encoding == das08_encode16) { - /* FPOS 16-bit boards are sign-magnitude */ + } else if (board->ai_encoding == das08_encode16) { + /* + * "JR" 16-bit boards are sign-magnitude. + * + * XXX The manual seems to imply that 0 is full-scale + * negative and 65535 is full-scale positive, but the + * original COMEDI patch to add support for the + * DAS08/JR/16 and DAS08/JR/16-AO boards have it + * encoded as sign-magnitude. Assume the original + * COMEDI code is correct for now. + */ + unsigned int magnitude = lsb | ((msb & 0x7f) << 8); + + /* + * MSB bit 7 is 0 for negative, 1 for positive voltage. + * COMEDI 16-bit bipolar data value for 0V is 0x8000. + */ if (msb & 0x80) - data[n] = (1 << 15) | lsb | ((msb & 0x7f) << 8); + data[n] = (1 << 15) + magnitude; else - data[n] = (1 << 15) - (lsb | (msb & 0x7f) << 8); + data[n] = (1 << 15) - magnitude; } else { dev_err(dev->class_dev, "bug! unknown ai encoding\n"); return -1; @@ -266,28 +257,28 @@ static int das08_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, return n; } -static int das08_di_rbits(struct comedi_device *dev, struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) +static int das08_di_insn_bits(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, unsigned int *data) { data[0] = 0; - data[1] = DAS08_IP(inb(dev->iobase + DAS08_STATUS)); + data[1] = DAS08_STATUS_DI(inb(dev->iobase + DAS08_STATUS_REG)); return insn->n; } -static int das08_do_wbits(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, - unsigned int *data) +static int das08_do_insn_bits(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, unsigned int *data) { struct das08_private_struct *devpriv = dev->private; if (comedi_dio_update_state(s, data)) { /* prevent race with setting of analog input mux */ spin_lock(&dev->spinlock); - devpriv->do_mux_bits &= ~DAS08_DO_MASK; - devpriv->do_mux_bits |= DAS08_OP(s->state); - outb(devpriv->do_mux_bits, dev->iobase + DAS08_CONTROL); + devpriv->do_mux_bits &= ~DAS08_CONTROL_DO_MASK; + devpriv->do_mux_bits |= DAS08_CONTROL_DO(s->state); + outb(devpriv->do_mux_bits, dev->iobase + DAS08_CONTROL_REG); spin_unlock(&dev->spinlock); } @@ -296,23 +287,22 @@ static int das08_do_wbits(struct comedi_device *dev, return insn->n; } -static int das08jr_di_rbits(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) +static int das08jr_di_insn_bits(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, unsigned int *data) { data[0] = 0; - data[1] = inb(dev->iobase + DAS08JR_DIO); + data[1] = inb(dev->iobase + DAS08JR_DI_REG); return insn->n; } -static int das08jr_do_wbits(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, - unsigned int *data) +static int das08jr_do_insn_bits(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, unsigned int *data) { if (comedi_dio_update_state(s, data)) - outb(s->state, dev->iobase + DAS08JR_DIO); + outb(s->state, dev->iobase + DAS08JR_DO_REG); data[1] = s->state; @@ -322,22 +312,22 @@ static int das08jr_do_wbits(struct comedi_device *dev, static void das08_ao_set_data(struct comedi_device *dev, unsigned int chan, unsigned int data) { - const struct das08_board_struct *thisboard = dev->board_ptr; + const struct das08_board_struct *board = dev->board_ptr; unsigned char lsb; unsigned char msb; lsb = data & 0xff; msb = (data >> 8) & 0xff; - if (thisboard->is_jr) { - outb(lsb, dev->iobase + DAS08JR_AO_LSB(chan)); - outb(msb, dev->iobase + DAS08JR_AO_MSB(chan)); + if (board->is_jr) { + outb(lsb, dev->iobase + DAS08JR_AO_LSB_REG(chan)); + outb(msb, dev->iobase + DAS08JR_AO_MSB_REG(chan)); /* load DACs */ - inb(dev->iobase + DAS08JR_DIO); + inb(dev->iobase + DAS08JR_AO_UPDATE_REG); } else { - outb(lsb, dev->iobase + DAS08AO_AO_LSB(chan)); - outb(msb, dev->iobase + DAS08AO_AO_MSB(chan)); + outb(lsb, dev->iobase + DAS08AOX_AO_LSB_REG(chan)); + outb(msb, dev->iobase + DAS08AOX_AO_MSB_REG(chan)); /* load DACs */ - inb(dev->iobase + DAS08AO_AO_UPDATE); + inb(dev->iobase + DAS08AOX_AO_UPDATE_REG); } } @@ -361,7 +351,7 @@ static int das08_ao_insn_write(struct comedi_device *dev, int das08_common_attach(struct comedi_device *dev, unsigned long iobase) { - const struct das08_board_struct *thisboard = dev->board_ptr; + const struct das08_board_struct *board = dev->board_ptr; struct das08_private_struct *devpriv = dev->private; struct comedi_subdevice *s; int ret; @@ -369,7 +359,7 @@ int das08_common_attach(struct comedi_device *dev, unsigned long iobase) dev->iobase = iobase; - dev->board_name = thisboard->name; + dev->board_name = board->name; ret = comedi_alloc_subdevices(dev, 6); if (ret) @@ -377,30 +367,31 @@ int das08_common_attach(struct comedi_device *dev, unsigned long iobase) s = &dev->subdevices[0]; /* ai */ - if (thisboard->ai_nbits) { + if (board->ai_nbits) { s->type = COMEDI_SUBD_AI; - /* XXX some boards actually have differential + /* + * XXX some boards actually have differential * inputs instead of single ended. * The driver does nothing with arefs though, * so it's no big deal. */ s->subdev_flags = SDF_READABLE | SDF_GROUND; s->n_chan = 8; - s->maxdata = (1 << thisboard->ai_nbits) - 1; - s->range_table = das08_ai_lranges[thisboard->ai_pg]; - s->insn_read = das08_ai_rinsn; - devpriv->pg_gainlist = das08_gainlists[thisboard->ai_pg]; + s->maxdata = (1 << board->ai_nbits) - 1; + s->range_table = das08_ai_lranges[board->ai_pg]; + s->insn_read = das08_ai_insn_read; + devpriv->pg_gainlist = das08_ai_gainlists[board->ai_pg]; } else { s->type = COMEDI_SUBD_UNUSED; } s = &dev->subdevices[1]; /* ao */ - if (thisboard->ao_nbits) { + if (board->ao_nbits) { s->type = COMEDI_SUBD_AO; s->subdev_flags = SDF_WRITABLE; s->n_chan = 2; - s->maxdata = (1 << thisboard->ao_nbits) - 1; + s->maxdata = (1 << board->ao_nbits) - 1; s->range_table = &range_bipolar5; s->insn_write = das08_ao_insn_write; @@ -419,36 +410,36 @@ int das08_common_attach(struct comedi_device *dev, unsigned long iobase) s = &dev->subdevices[2]; /* di */ - if (thisboard->di_nchan) { + if (board->di_nchan) { s->type = COMEDI_SUBD_DI; s->subdev_flags = SDF_READABLE; - s->n_chan = thisboard->di_nchan; + s->n_chan = board->di_nchan; s->maxdata = 1; s->range_table = &range_digital; - s->insn_bits = - thisboard->is_jr ? das08jr_di_rbits : das08_di_rbits; + s->insn_bits = board->is_jr ? das08jr_di_insn_bits : + das08_di_insn_bits; } else { s->type = COMEDI_SUBD_UNUSED; } s = &dev->subdevices[3]; /* do */ - if (thisboard->do_nchan) { + if (board->do_nchan) { s->type = COMEDI_SUBD_DO; s->subdev_flags = SDF_WRITABLE; - s->n_chan = thisboard->do_nchan; + s->n_chan = board->do_nchan; s->maxdata = 1; s->range_table = &range_digital; - s->insn_bits = - thisboard->is_jr ? das08jr_do_wbits : das08_do_wbits; + s->insn_bits = board->is_jr ? das08jr_do_insn_bits : + das08_do_insn_bits; } else { s->type = COMEDI_SUBD_UNUSED; } s = &dev->subdevices[4]; /* 8255 */ - if (thisboard->i8255_offset != 0) { - ret = subdev_8255_init(dev, s, NULL, thisboard->i8255_offset); + if (board->i8255_offset != 0) { + ret = subdev_8255_init(dev, s, NULL, board->i8255_offset); if (ret) return ret; } else { @@ -457,9 +448,8 @@ int das08_common_attach(struct comedi_device *dev, unsigned long iobase) /* Counter subdevice (8254) */ s = &dev->subdevices[5]; - if (thisboard->i8254_offset) { - dev->pacer = comedi_8254_init(dev->iobase + - thisboard->i8254_offset, + if (board->i8254_offset) { + dev->pacer = comedi_8254_init(dev->iobase + board->i8254_offset, 0, I8254_IO8, 0); if (!dev->pacer) return -ENOMEM; @@ -485,5 +475,5 @@ static void __exit das08_exit(void) module_exit(das08_exit); MODULE_AUTHOR("Comedi http://www.comedi.org"); -MODULE_DESCRIPTION("Comedi low-level driver"); +MODULE_DESCRIPTION("Comedi common DAS08 support module"); MODULE_LICENSE("GPL"); diff --git a/drivers/staging/comedi/drivers/das08.h b/drivers/staging/comedi/drivers/das08.h index f86167da5895..d27044cb7158 100644 --- a/drivers/staging/comedi/drivers/das08.h +++ b/drivers/staging/comedi/drivers/das08.h @@ -1,28 +1,33 @@ /* - das08.h - - Header for das08.c and das08_cs.c - - Copyright (C) 2003 Frank Mori Hess <fmhess@users.sourceforge.net> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * das08.h + * + * Header for common DAS08 support (used by ISA/PCI/PCMCIA drivers) + * + * Copyright (C) 2003 Frank Mori Hess <fmhess@users.sourceforge.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ #ifndef _DAS08_H #define _DAS08_H +#include <linux/types.h> + +struct comedi_device; + /* different ways ai data is encoded in first two registers */ enum das08_ai_encoding { das08_encode12, das08_encode16, das08_pcm_encode12 }; -enum das08_lrange { das08_pg_none, das08_bipolar5, das08_pgh, das08_pgl, - das08_pgm +/* types of ai range table used by different boards */ +enum das08_lrange { + das08_pg_none, das08_bipolar5, das08_pgh, das08_pgl, das08_pgm }; struct das08_board_struct { @@ -36,13 +41,12 @@ struct das08_board_struct { unsigned int do_nchan; unsigned int i8255_offset; unsigned int i8254_offset; - unsigned int iosize; /* number of ioports used */ + unsigned int iosize; /* number of ioports used */ }; struct das08_private_struct { - unsigned int do_mux_bits; /* bits for do/mux register on boards - * without separate do register - */ + /* bits for do/mux register on boards without separate do register */ + unsigned int do_mux_bits; const unsigned int *pg_gainlist; }; diff --git a/drivers/staging/comedi/drivers/das08_isa.c b/drivers/staging/comedi/drivers/das08_isa.c index 2d9a31dab552..cdefc99b6db3 100644 --- a/drivers/staging/comedi/drivers/das08_isa.c +++ b/drivers/staging/comedi/drivers/das08_isa.c @@ -168,7 +168,7 @@ static const struct das08_board_struct das08_isa_boards[] = { static int das08_isa_attach(struct comedi_device *dev, struct comedi_devconfig *it) { - const struct das08_board_struct *thisboard = dev->board_ptr; + const struct das08_board_struct *board = dev->board_ptr; struct das08_private_struct *devpriv; int ret; @@ -176,7 +176,7 @@ static int das08_isa_attach(struct comedi_device *dev, if (!devpriv) return -ENOMEM; - ret = comedi_request_region(dev, it->options[0], thisboard->iosize); + ret = comedi_request_region(dev, it->options[0], board->iosize); if (ret) return ret; diff --git a/drivers/staging/comedi/drivers/das16m1.c b/drivers/staging/comedi/drivers/das16m1.c index 1adf6a71a9f3..a18a8878bdb8 100644 --- a/drivers/staging/comedi/drivers/das16m1.c +++ b/drivers/staging/comedi/drivers/das16m1.c @@ -46,8 +46,8 @@ list has 2 or more channels in it, then two conditions must be satisfied: (2) - the list must have an even number of entries. Options: - [0] - base io address - [1] - irq (optional, but you probably want it) + [0] - base io address + [1] - irq (optional, but you probably want it) irq can be omitted, although the cmd interface will not work without it. */ diff --git a/drivers/staging/comedi/drivers/das1800.c b/drivers/staging/comedi/drivers/das1800.c index 53baf37cd21a..bfa42620a3f6 100644 --- a/drivers/staging/comedi/drivers/das1800.c +++ b/drivers/staging/comedi/drivers/das1800.c @@ -444,9 +444,9 @@ static const struct comedi_lrange range_ao_2 = { static inline uint16_t munge_bipolar_sample(const struct comedi_device *dev, uint16_t sample) { - const struct das1800_board *thisboard = dev->board_ptr; + const struct das1800_board *board = dev->board_ptr; - sample += 1 << (thisboard->resolution - 1); + sample += 1 << (board->resolution - 1); return sample; } @@ -725,7 +725,7 @@ static int das1800_ai_do_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_cmd *cmd) { - const struct das1800_board *thisboard = dev->board_ptr; + const struct das1800_board *board = dev->board_ptr; int err = 0; unsigned int arg; @@ -765,7 +765,7 @@ static int das1800_ai_do_cmdtest(struct comedi_device *dev, if (cmd->convert_src == TRIG_TIMER) { err |= comedi_check_trigger_arg_min(&cmd->convert_arg, - thisboard->ai_speed); + board->ai_speed); } err |= comedi_check_trigger_arg_min(&cmd->chanlist_len, 1); @@ -1048,7 +1048,7 @@ static int das1800_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data) { - const struct das1800_board *thisboard = dev->board_ptr; + const struct das1800_board *board = dev->board_ptr; int i, n; int chan, range, aref, chan_range; int timeout = 1000; @@ -1098,7 +1098,7 @@ static int das1800_ai_rinsn(struct comedi_device *dev, dpnt = inw(dev->iobase + DAS1800_FIFO); /* shift data to offset binary for bipolar ranges */ if ((conv_flags & UB) == 0) - dpnt += 1 << (thisboard->resolution - 1); + dpnt += 1 << (board->resolution - 1); data[n] = dpnt; } exit: @@ -1112,16 +1112,16 @@ static int das1800_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data) { - const struct das1800_board *thisboard = dev->board_ptr; + const struct das1800_board *board = dev->board_ptr; struct das1800_private *devpriv = dev->private; int chan = CR_CHAN(insn->chanspec); /* int range = CR_RANGE(insn->chanspec); */ - int update_chan = thisboard->ao_n_chan - 1; + int update_chan = board->ao_n_chan - 1; unsigned short output; unsigned long irq_flags; /* card expects two's complement data */ - output = data[0] - (1 << (thisboard->resolution - 1)); + output = data[0] - (1 << (board->resolution - 1)); /* if the write is to the 'update' channel, we need to remember its value */ if (chan == update_chan) devpriv->ao_update_bits = output; @@ -1216,72 +1216,76 @@ static void das1800_free_dma(struct comedi_device *dev) comedi_isadma_free(devpriv->dma); } -static int das1800_probe(struct comedi_device *dev) +static const struct das1800_board *das1800_probe(struct comedi_device *dev) { const struct das1800_board *board = dev->board_ptr; - int index; + int index = board ? board - das1800_boards : -EINVAL; int id; - /* calc the offset to the boardinfo that was found by the core */ - index = board - das1800_boards; - - /* verify that the board id matches the boardinfo */ + /* + * The dev->board_ptr will be set by comedi_device_attach() if the + * board name provided by the user matches a board->name in this + * driver. If so, this function sanity checks the id to verify that + * the board is correct. + * + * If the dev->board_ptr is not set, the user is trying to attach + * an unspecified board to this driver. In this case the id is used + * to 'probe' for the correct dev->board_ptr. + */ id = (inb(dev->iobase + DAS1800_DIGITAL) >> 4) & 0xf; switch (id) { case 0x3: if (index == das1801st_da || index == das1802st_da || index == das1701st_da || index == das1702st_da) - return index; + return board; index = das1801st; break; case 0x4: if (index == das1802hr_da || index == das1702hr_da) - return index; + return board; index = das1802hr; break; case 0x5: if (index == das1801ao || index == das1802ao || index == das1701ao || index == das1702ao) - return index; + return board; index = das1801ao; break; case 0x6: if (index == das1802hr || index == das1702hr) - return index; + return board; index = das1802hr; break; case 0x7: if (index == das1801st || index == das1802st || index == das1701st || index == das1702st) - return index; + return board; index = das1801st; break; case 0x8: if (index == das1801hc || index == das1802hc) - return index; + return board; index = das1801hc; - break; default: dev_err(dev->class_dev, "Board model: probe returned 0x%x (unknown, please report)\n", id); - break; + return NULL; } dev_err(dev->class_dev, "Board model (probed, not recommended): %s series\n", das1800_boards[index].name); - return index; + return &das1800_boards[index]; } static int das1800_attach(struct comedi_device *dev, struct comedi_devconfig *it) { - const struct das1800_board *thisboard; + const struct das1800_board *board; struct das1800_private *devpriv; struct comedi_subdevice *s; unsigned int irq = it->options[1]; - int board; int ret; devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); @@ -1293,17 +1297,15 @@ static int das1800_attach(struct comedi_device *dev, return ret; board = das1800_probe(dev); - if (board < 0) { + if (!board) { dev_err(dev->class_dev, "unable to determine board type\n"); return -ENODEV; } - - dev->board_ptr = das1800_boards + board; - thisboard = dev->board_ptr; - dev->board_name = thisboard->name; + dev->board_ptr = board; + dev->board_name = board->name; /* if it is an 'ao' board with fancy analog out then we need extra io ports */ - if (thisboard->ao_ability == 2) { + if (board->ao_ability == 2) { unsigned long iobase2 = dev->iobase + IOBASE2; ret = __comedi_request_region(dev, iobase2, DAS1800_SIZE); @@ -1363,11 +1365,11 @@ static int das1800_attach(struct comedi_device *dev, s = &dev->subdevices[0]; s->type = COMEDI_SUBD_AI; s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_GROUND; - if (thisboard->common) + if (board->common) s->subdev_flags |= SDF_COMMON; - s->n_chan = thisboard->qram_len; - s->maxdata = (1 << thisboard->resolution) - 1; - s->range_table = thisboard->range_ai; + s->n_chan = board->qram_len; + s->maxdata = (1 << board->resolution) - 1; + s->range_table = board->range_ai; s->insn_read = das1800_ai_rinsn; if (dev->irq) { dev->read_subdev = s; @@ -1381,11 +1383,11 @@ static int das1800_attach(struct comedi_device *dev, /* analog out */ s = &dev->subdevices[1]; - if (thisboard->ao_ability == 1) { + if (board->ao_ability == 1) { s->type = COMEDI_SUBD_AO; s->subdev_flags = SDF_WRITABLE; - s->n_chan = thisboard->ao_n_chan; - s->maxdata = (1 << thisboard->resolution) - 1; + s->n_chan = board->ao_n_chan; + s->maxdata = (1 << board->resolution) - 1; s->range_table = &range_bipolar10; s->insn_write = das1800_ao_winsn; } else { @@ -1405,7 +1407,7 @@ static int das1800_attach(struct comedi_device *dev, s = &dev->subdevices[3]; s->type = COMEDI_SUBD_DO; s->subdev_flags = SDF_WRITABLE; - s->n_chan = thisboard->do_n_chan; + s->n_chan = board->do_n_chan; s->maxdata = 1; s->range_table = &range_digital; s->insn_bits = das1800_do_wbits; @@ -1416,9 +1418,9 @@ static int das1800_attach(struct comedi_device *dev, outb(0, dev->iobase + DAS1800_DIGITAL); /* initialize analog out channels */ - if (thisboard->ao_ability == 1) { + if (board->ao_ability == 1) { /* select 'update' dac channel for baseAddress + 0x0 */ - outb(DAC(thisboard->ao_n_chan - 1), + outb(DAC(board->ao_n_chan - 1), dev->iobase + DAS1800_SELECT); outw(devpriv->ao_update_bits, dev->iobase + DAS1800_DAC); } diff --git a/drivers/staging/comedi/drivers/das800.c b/drivers/staging/comedi/drivers/das800.c index 39d304a1259f..b02f12201cf7 100644 --- a/drivers/staging/comedi/drivers/das800.c +++ b/drivers/staging/comedi/drivers/das800.c @@ -240,13 +240,13 @@ static unsigned das800_ind_read(struct comedi_device *dev, unsigned reg) static void das800_enable(struct comedi_device *dev) { - const struct das800_board *thisboard = dev->board_ptr; + const struct das800_board *board = dev->board_ptr; struct das800_private *devpriv = dev->private; unsigned long irq_flags; spin_lock_irqsave(&dev->spinlock, irq_flags); /* enable fifo-half full interrupts for cio-das802/16 */ - if (thisboard->resolution == 16) + if (board->resolution == 16) outb(CIO_ENHF, dev->iobase + DAS800_GAIN); /* enable hardware triggering */ das800_ind_write(dev, CONV_HCEN, CONV_CONTROL); @@ -303,7 +303,7 @@ static int das800_ai_do_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_cmd *cmd) { - const struct das800_board *thisboard = dev->board_ptr; + const struct das800_board *board = dev->board_ptr; int err = 0; /* Step 1 : check if triggers are trivially valid */ @@ -335,7 +335,7 @@ static int das800_ai_do_cmdtest(struct comedi_device *dev, if (cmd->convert_src == TRIG_TIMER) { err |= comedi_check_trigger_arg_min(&cmd->convert_arg, - thisboard->ai_speed); + board->ai_speed); } err |= comedi_check_trigger_arg_min(&cmd->chanlist_len, 1); @@ -375,7 +375,7 @@ static int das800_ai_do_cmdtest(struct comedi_device *dev, static int das800_ai_do_cmd(struct comedi_device *dev, struct comedi_subdevice *s) { - const struct das800_board *thisboard = dev->board_ptr; + const struct das800_board *board = dev->board_ptr; struct comedi_async *async = s->async; struct comedi_cmd *cmd = &async->cmd; unsigned int gain = CR_RANGE(cmd->chanlist[0]); @@ -393,7 +393,7 @@ static int das800_ai_do_cmd(struct comedi_device *dev, spin_unlock_irqrestore(&dev->spinlock, irq_flags); /* set gain */ - if (thisboard->resolution == 12 && gain > 0) + if (board->resolution == 12 && gain > 0) gain += 0x7; gain &= 0xf; outb(gain, dev->iobase + DAS800_GAIN); @@ -604,54 +604,62 @@ static int das800_do_insn_bits(struct comedi_device *dev, return insn->n; } -static int das800_probe(struct comedi_device *dev) +static const struct das800_board *das800_probe(struct comedi_device *dev) { - const struct das800_board *thisboard = dev->board_ptr; - int board = thisboard ? thisboard - das800_boards : -EINVAL; + const struct das800_board *board = dev->board_ptr; + int index = board ? board - das800_boards : -EINVAL; int id_bits; unsigned long irq_flags; + /* + * The dev->board_ptr will be set by comedi_device_attach() if the + * board name provided by the user matches a board->name in this + * driver. If so, this function sanity checks the id_bits to verify + * that the board is correct. + * + * If the dev->board_ptr is not set, the user is trying to attach + * an unspecified board to this driver. In this case the id_bits + * are used to 'probe' for the correct dev->board_ptr. + */ spin_lock_irqsave(&dev->spinlock, irq_flags); id_bits = das800_ind_read(dev, ID) & 0x3; spin_unlock_irqrestore(&dev->spinlock, irq_flags); switch (id_bits) { case 0x0: - if (board == BOARD_DAS800 || board == BOARD_CIODAS800) - break; - dev_dbg(dev->class_dev, "Board model (probed): DAS-800\n"); - board = BOARD_DAS800; + if (index == BOARD_DAS800 || index == BOARD_CIODAS800) + return board; + index = BOARD_DAS800; break; case 0x2: - if (board == BOARD_DAS801 || board == BOARD_CIODAS801) - break; - dev_dbg(dev->class_dev, "Board model (probed): DAS-801\n"); - board = BOARD_DAS801; + if (index == BOARD_DAS801 || index == BOARD_CIODAS801) + return board; + index = BOARD_DAS801; break; case 0x3: - if (board == BOARD_DAS802 || board == BOARD_CIODAS802 || - board == BOARD_CIODAS80216) - break; - dev_dbg(dev->class_dev, "Board model (probed): DAS-802\n"); - board = BOARD_DAS802; + if (index == BOARD_DAS802 || index == BOARD_CIODAS802 || + index == BOARD_CIODAS80216) + return board; + index = BOARD_DAS802; break; default: dev_dbg(dev->class_dev, "Board model: 0x%x (unknown)\n", id_bits); - board = -EINVAL; - break; + return NULL; } - return board; + dev_dbg(dev->class_dev, "Board model (probed): %s series\n", + das800_boards[index].name); + + return &das800_boards[index]; } static int das800_attach(struct comedi_device *dev, struct comedi_devconfig *it) { - const struct das800_board *thisboard; + const struct das800_board *board; struct das800_private *devpriv; struct comedi_subdevice *s; unsigned int irq = it->options[1]; unsigned long irq_flags; - int board; int ret; devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); @@ -663,13 +671,10 @@ static int das800_attach(struct comedi_device *dev, struct comedi_devconfig *it) return ret; board = das800_probe(dev); - if (board < 0) { - dev_dbg(dev->class_dev, "unable to determine board type\n"); + if (!board) return -ENODEV; - } - dev->board_ptr = das800_boards + board; - thisboard = dev->board_ptr; - dev->board_name = thisboard->name; + dev->board_ptr = board; + dev->board_name = board->name; if (irq > 1 && irq <= 7) { ret = request_irq(irq, das800_interrupt, 0, dev->board_name, @@ -693,8 +698,8 @@ static int das800_attach(struct comedi_device *dev, struct comedi_devconfig *it) s->type = COMEDI_SUBD_AI; s->subdev_flags = SDF_READABLE | SDF_GROUND; s->n_chan = 8; - s->maxdata = (1 << thisboard->resolution) - 1; - s->range_table = thisboard->ai_range; + s->maxdata = (1 << board->resolution) - 1; + s->range_table = board->ai_range; s->insn_read = das800_ai_insn_read; if (dev->irq) { s->subdev_flags |= SDF_CMD_READ; diff --git a/drivers/staging/comedi/drivers/dt3000.c b/drivers/staging/comedi/drivers/dt3000.c index 031282c82f43..8c4f284d1919 100644 --- a/drivers/staging/comedi/drivers/dt3000.c +++ b/drivers/staging/comedi/drivers/dt3000.c @@ -400,7 +400,7 @@ static int dt3k_ns_to_timer(unsigned int timer_base, unsigned int *nanosec, static int dt3k_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_cmd *cmd) { - const struct dt3k_boardtype *this_board = dev->board_ptr; + const struct dt3k_boardtype *board = dev->board_ptr; int err = 0; unsigned int arg; @@ -424,14 +424,14 @@ static int dt3k_ai_cmdtest(struct comedi_device *dev, if (cmd->scan_begin_src == TRIG_TIMER) { err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg, - this_board->ai_speed); + board->ai_speed); err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 100 * 16 * 65535); } if (cmd->convert_src == TRIG_TIMER) { err |= comedi_check_trigger_arg_min(&cmd->convert_arg, - this_board->ai_speed); + board->ai_speed); err |= comedi_check_trigger_arg_max(&cmd->convert_arg, 50 * 16 * 65535); } @@ -635,17 +635,17 @@ static int dt3000_auto_attach(struct comedi_device *dev, unsigned long context) { struct pci_dev *pcidev = comedi_to_pci_dev(dev); - const struct dt3k_boardtype *this_board = NULL; + const struct dt3k_boardtype *board = NULL; struct dt3k_private *devpriv; struct comedi_subdevice *s; int ret = 0; if (context < ARRAY_SIZE(dt3k_boardtypes)) - this_board = &dt3k_boardtypes[context]; - if (!this_board) + board = &dt3k_boardtypes[context]; + if (!board) return -ENODEV; - dev->board_ptr = this_board; - dev->board_name = this_board->name; + dev->board_ptr = board; + dev->board_name = board->name; devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); if (!devpriv) @@ -674,9 +674,9 @@ static int dt3000_auto_attach(struct comedi_device *dev, /* ai subdevice */ s->type = COMEDI_SUBD_AI; s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DIFF; - s->n_chan = this_board->adchan; + s->n_chan = board->adchan; s->insn_read = dt3k_ai_insn; - s->maxdata = (1 << this_board->adbits) - 1; + s->maxdata = (1 << board->adbits) - 1; s->range_table = &range_dt3000_ai; /* XXX */ if (dev->irq) { dev->read_subdev = s; @@ -692,7 +692,7 @@ static int dt3000_auto_attach(struct comedi_device *dev, s->type = COMEDI_SUBD_AO; s->subdev_flags = SDF_WRITABLE; s->n_chan = 2; - s->maxdata = (1 << this_board->dabits) - 1; + s->maxdata = (1 << board->dabits) - 1; s->len_chanlist = 1; s->range_table = &range_bipolar10; s->insn_write = dt3k_ao_insn_write; diff --git a/drivers/staging/comedi/drivers/gsc_hpdi.c b/drivers/staging/comedi/drivers/gsc_hpdi.c index 3cb6409c4f01..e9296182236e 100644 --- a/drivers/staging/comedi/drivers/gsc_hpdi.c +++ b/drivers/staging/comedi/drivers/gsc_hpdi.c @@ -52,45 +52,45 @@ * PCI BAR2 Register map (dev->mmio) */ #define FIRMWARE_REV_REG 0x00 -#define FEATURES_REG_PRESENT_BIT (1 << 15) +#define FEATURES_REG_PRESENT_BIT BIT(15) #define BOARD_CONTROL_REG 0x04 -#define BOARD_RESET_BIT (1 << 0) -#define TX_FIFO_RESET_BIT (1 << 1) -#define RX_FIFO_RESET_BIT (1 << 2) -#define TX_ENABLE_BIT (1 << 4) -#define RX_ENABLE_BIT (1 << 5) -#define DEMAND_DMA_DIRECTION_TX_BIT (1 << 6) /* ch 0 only */ -#define LINE_VALID_ON_STATUS_VALID_BIT (1 << 7) -#define START_TX_BIT (1 << 8) -#define CABLE_THROTTLE_ENABLE_BIT (1 << 9) -#define TEST_MODE_ENABLE_BIT (1 << 31) +#define BOARD_RESET_BIT BIT(0) +#define TX_FIFO_RESET_BIT BIT(1) +#define RX_FIFO_RESET_BIT BIT(2) +#define TX_ENABLE_BIT BIT(4) +#define RX_ENABLE_BIT BIT(5) +#define DEMAND_DMA_DIRECTION_TX_BIT BIT(6) /* ch 0 only */ +#define LINE_VALID_ON_STATUS_VALID_BIT BIT(7) +#define START_TX_BIT BIT(8) +#define CABLE_THROTTLE_ENABLE_BIT BIT(9) +#define TEST_MODE_ENABLE_BIT BIT(31) #define BOARD_STATUS_REG 0x08 #define COMMAND_LINE_STATUS_MASK (0x7f << 0) -#define TX_IN_PROGRESS_BIT (1 << 7) -#define TX_NOT_EMPTY_BIT (1 << 8) -#define TX_NOT_ALMOST_EMPTY_BIT (1 << 9) -#define TX_NOT_ALMOST_FULL_BIT (1 << 10) -#define TX_NOT_FULL_BIT (1 << 11) -#define RX_NOT_EMPTY_BIT (1 << 12) -#define RX_NOT_ALMOST_EMPTY_BIT (1 << 13) -#define RX_NOT_ALMOST_FULL_BIT (1 << 14) -#define RX_NOT_FULL_BIT (1 << 15) -#define BOARD_JUMPER0_INSTALLED_BIT (1 << 16) -#define BOARD_JUMPER1_INSTALLED_BIT (1 << 17) -#define TX_OVERRUN_BIT (1 << 21) -#define RX_UNDERRUN_BIT (1 << 22) -#define RX_OVERRUN_BIT (1 << 23) +#define TX_IN_PROGRESS_BIT BIT(7) +#define TX_NOT_EMPTY_BIT BIT(8) +#define TX_NOT_ALMOST_EMPTY_BIT BIT(9) +#define TX_NOT_ALMOST_FULL_BIT BIT(10) +#define TX_NOT_FULL_BIT BIT(11) +#define RX_NOT_EMPTY_BIT BIT(12) +#define RX_NOT_ALMOST_EMPTY_BIT BIT(13) +#define RX_NOT_ALMOST_FULL_BIT BIT(14) +#define RX_NOT_FULL_BIT BIT(15) +#define BOARD_JUMPER0_INSTALLED_BIT BIT(16) +#define BOARD_JUMPER1_INSTALLED_BIT BIT(17) +#define TX_OVERRUN_BIT BIT(21) +#define RX_UNDERRUN_BIT BIT(22) +#define RX_OVERRUN_BIT BIT(23) #define TX_PROG_ALMOST_REG 0x0c #define RX_PROG_ALMOST_REG 0x10 #define ALMOST_EMPTY_BITS(x) (((x) & 0xffff) << 0) #define ALMOST_FULL_BITS(x) (((x) & 0xff) << 16) #define FEATURES_REG 0x14 -#define FIFO_SIZE_PRESENT_BIT (1 << 0) -#define FIFO_WORDS_PRESENT_BIT (1 << 1) -#define LEVEL_EDGE_INTERRUPTS_PRESENT_BIT (1 << 2) -#define GPIO_SUPPORTED_BIT (1 << 3) -#define PLX_DMA_CH1_SUPPORTED_BIT (1 << 4) -#define OVERRUN_UNDERRUN_SUPPORTED_BIT (1 << 5) +#define FIFO_SIZE_PRESENT_BIT BIT(0) +#define FIFO_WORDS_PRESENT_BIT BIT(1) +#define LEVEL_EDGE_INTERRUPTS_PRESENT_BIT BIT(2) +#define GPIO_SUPPORTED_BIT BIT(3) +#define PLX_DMA_CH1_SUPPORTED_BIT BIT(4) +#define OVERRUN_UNDERRUN_SUPPORTED_BIT BIT(5) #define FIFO_REG 0x18 #define TX_STATUS_COUNT_REG 0x1c #define TX_LINE_VALID_COUNT_REG 0x20, @@ -98,16 +98,16 @@ #define RX_STATUS_COUNT_REG 0x28 #define RX_LINE_COUNT_REG 0x2c #define INTERRUPT_CONTROL_REG 0x30 -#define FRAME_VALID_START_INTR (1 << 0) -#define FRAME_VALID_END_INTR (1 << 1) -#define TX_FIFO_EMPTY_INTR (1 << 8) -#define TX_FIFO_ALMOST_EMPTY_INTR (1 << 9) -#define TX_FIFO_ALMOST_FULL_INTR (1 << 10) -#define TX_FIFO_FULL_INTR (1 << 11) -#define RX_EMPTY_INTR (1 << 12) -#define RX_ALMOST_EMPTY_INTR (1 << 13) -#define RX_ALMOST_FULL_INTR (1 << 14) -#define RX_FULL_INTR (1 << 15) +#define FRAME_VALID_START_INTR BIT(0) +#define FRAME_VALID_END_INTR BIT(1) +#define TX_FIFO_EMPTY_INTR BIT(8) +#define TX_FIFO_ALMOST_EMPTY_INTR BIT(9) +#define TX_FIFO_ALMOST_FULL_INTR BIT(10) +#define TX_FIFO_FULL_INTR BIT(11) +#define RX_EMPTY_INTR BIT(12) +#define RX_ALMOST_EMPTY_INTR BIT(13) +#define RX_ALMOST_FULL_INTR BIT(14) +#define RX_FULL_INTR BIT(15) #define INTERRUPT_STATUS_REG 0x34 #define TX_CLOCK_DIVIDER_REG 0x38 #define TX_FIFO_SIZE_REG 0x40 @@ -123,34 +123,15 @@ #define NUM_DMA_BUFFERS 4 #define NUM_DMA_DESCRIPTORS 256 -struct hpdi_board { - const char *name; - int device_id; - int subdevice_id; -}; - -static const struct hpdi_board hpdi_boards[] = { - { - .name = "pci-hpdi32", - .device_id = PCI_DEVICE_ID_PLX_9080, - .subdevice_id = 0x2400, - }, -#if 0 - { - .name = "pxi-hpdi32", - .device_id = 0x9656, - .subdevice_id = 0x2705, - }, -#endif -}; - struct hpdi_private { void __iomem *plx9080_mmio; - uint32_t *dio_buffer[NUM_DMA_BUFFERS]; /* dma buffers */ + uint32_t *dio_buffer[NUM_DMA_BUFFERS]; /* dma buffers */ /* physical addresses of dma buffers */ dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS]; - /* array of dma descriptors read by plx9080, allocated to get proper - * alignment */ + /* + * array of dma descriptors read by plx9080, allocated to get proper + * alignment + */ struct plx_dma_desc *dma_desc; /* physical address of dma descriptor array */ dma_addr_t dma_desc_phys_addr; @@ -202,7 +183,7 @@ static void gsc_hpdi_drain_dma(struct comedi_device *dev, unsigned int channel) devpriv->dma_desc_index = idx; } - /* XXX check for buffer overrun somehow */ + /* XXX check for buffer overrun somehow */ } static irqreturn_t gsc_hpdi_interrupt(int irq, void *d) @@ -230,10 +211,11 @@ static irqreturn_t gsc_hpdi_interrupt(int irq, void *d) if (hpdi_intr_status) writel(hpdi_intr_status, dev->mmio + INTERRUPT_STATUS_REG); - /* spin lock makes sure no one else changes plx dma control reg */ + /* spin lock makes sure no one else changes plx dma control reg */ spin_lock_irqsave(&dev->spinlock, flags); dma0_status = readb(devpriv->plx9080_mmio + PLX_DMA0_CS_REG); - if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */ + if (plx_status & ICS_DMA0_A) { + /* dma chan 0 interrupt */ writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT, devpriv->plx9080_mmio + PLX_DMA0_CS_REG); @@ -242,17 +224,19 @@ static irqreturn_t gsc_hpdi_interrupt(int irq, void *d) } spin_unlock_irqrestore(&dev->spinlock, flags); - /* spin lock makes sure no one else changes plx dma control reg */ + /* spin lock makes sure no one else changes plx dma control reg */ spin_lock_irqsave(&dev->spinlock, flags); dma1_status = readb(devpriv->plx9080_mmio + PLX_DMA1_CS_REG); - if (plx_status & ICS_DMA1_A) { /* XXX *//* dma chan 1 interrupt */ + if (plx_status & ICS_DMA1_A) { + /* XXX */ /* dma chan 1 interrupt */ writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT, devpriv->plx9080_mmio + PLX_DMA1_CS_REG); } spin_unlock_irqrestore(&dev->spinlock, flags); - /* clear possible plx9080 interrupt sources */ - if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */ + /* clear possible plx9080 interrupt sources */ + if (plx_status & ICS_LDIA) { + /* clear local doorbell interrupt */ plx_bits = readl(devpriv->plx9080_mmio + PLX_DBR_OUT_REG); writel(plx_bits, devpriv->plx9080_mmio + PLX_DBR_OUT_REG); } @@ -280,7 +264,7 @@ static void gsc_hpdi_abort_dma(struct comedi_device *dev, unsigned int channel) struct hpdi_private *devpriv = dev->private; unsigned long flags; - /* spinlock for plx dma control/status reg */ + /* spinlock for plx dma control/status reg */ spin_lock_irqsave(&dev->spinlock, flags); plx9080_abort_dma(devpriv->plx9080_mmio, channel); @@ -536,7 +520,7 @@ static int gsc_hpdi_init(struct comedi_device *dev) /* wait 10usec after reset before accessing fifos */ writel(BOARD_RESET_BIT, dev->mmio + BOARD_CONTROL_REG); - udelay(10); + usleep_range(10, 1000); writel(ALMOST_EMPTY_BITS(32) | ALMOST_FULL_BITS(32), dev->mmio + RX_PROG_ALMOST_REG); @@ -550,7 +534,7 @@ static int gsc_hpdi_init(struct comedi_device *dev) writel(0, dev->mmio + INTERRUPT_CONTROL_REG); - /* enable interrupts */ + /* enable interrupts */ plx_intcsr_bits = ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE | ICS_DMA0_E; @@ -577,57 +561,42 @@ static void gsc_hpdi_init_plx9080(struct comedi_device *dev) gsc_hpdi_abort_dma(dev, 0); gsc_hpdi_abort_dma(dev, 1); - /* configure dma0 mode */ + /* configure dma0 mode */ bits = 0; - /* enable ready input */ + /* enable ready input */ bits |= PLX_DMA_EN_READYIN_BIT; - /* enable dma chaining */ + /* enable dma chaining */ bits |= PLX_EN_CHAIN_BIT; - /* enable interrupt on dma done - * (probably don't need this, since chain never finishes) */ + /* + * enable interrupt on dma done + * (probably don't need this, since chain never finishes) + */ bits |= PLX_EN_DMA_DONE_INTR_BIT; - /* don't increment local address during transfers - * (we are transferring from a fixed fifo register) */ + /* + * don't increment local address during transfers + * (we are transferring from a fixed fifo register) + */ bits |= PLX_LOCAL_ADDR_CONST_BIT; - /* route dma interrupt to pci bus */ + /* route dma interrupt to pci bus */ bits |= PLX_DMA_INTR_PCI_BIT; - /* enable demand mode */ + /* enable demand mode */ bits |= PLX_DEMAND_MODE_BIT; - /* enable local burst mode */ + /* enable local burst mode */ bits |= PLX_DMA_LOCAL_BURST_EN_BIT; bits |= PLX_LOCAL_BUS_32_WIDE_BITS; writel(bits, plx_iobase + PLX_DMA0_MODE_REG); } -static const struct hpdi_board *gsc_hpdi_find_board(struct pci_dev *pcidev) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(hpdi_boards); i++) - if (pcidev->device == hpdi_boards[i].device_id && - pcidev->subsystem_device == hpdi_boards[i].subdevice_id) - return &hpdi_boards[i]; - return NULL; -} - static int gsc_hpdi_auto_attach(struct comedi_device *dev, unsigned long context_unused) { struct pci_dev *pcidev = comedi_to_pci_dev(dev); - const struct hpdi_board *thisboard; struct hpdi_private *devpriv; struct comedi_subdevice *s; int i; int retval; - thisboard = gsc_hpdi_find_board(pcidev); - if (!thisboard) { - dev_err(dev->class_dev, "gsc_hpdi: pci %s not supported\n", - pci_name(pcidev)); - return -EINVAL; - } - dev->board_ptr = thisboard; - dev->board_name = thisboard->name; + dev->board_name = "pci-hpdi32"; devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); if (!devpriv) @@ -647,7 +616,7 @@ static int gsc_hpdi_auto_attach(struct comedi_device *dev, gsc_hpdi_init_plx9080(dev); - /* get irq */ + /* get irq */ if (request_irq(pcidev->irq, gsc_hpdi_interrupt, IRQF_SHARED, dev->board_name, dev)) { dev_warn(dev->class_dev, @@ -658,13 +627,13 @@ static int gsc_hpdi_auto_attach(struct comedi_device *dev, dev_dbg(dev->class_dev, " irq %u\n", dev->irq); - /* allocate pci dma buffers */ + /* allocate pci dma buffers */ for (i = 0; i < NUM_DMA_BUFFERS; i++) { devpriv->dio_buffer[i] = pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE, &devpriv->dio_buffer_phys_addr[i]); } - /* allocate dma descriptors */ + /* allocate dma descriptors */ devpriv->dma_desc = pci_alloc_consistent(pcidev, sizeof(struct plx_dma_desc) * NUM_DMA_DESCRIPTORS, @@ -733,8 +702,8 @@ static int gsc_hpdi_pci_probe(struct pci_dev *dev, } static const struct pci_device_id gsc_hpdi_pci_table[] = { - { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, PCI_VENDOR_ID_PLX, - 0x2400, 0, 0, 0}, + { PCI_DEVICE_SUB(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, + PCI_VENDOR_ID_PLX, 0x2400) }, { 0 } }; MODULE_DEVICE_TABLE(pci, gsc_hpdi_pci_table); @@ -748,5 +717,5 @@ static struct pci_driver gsc_hpdi_pci_driver = { module_comedi_pci_driver(gsc_hpdi_driver, gsc_hpdi_pci_driver); MODULE_AUTHOR("Comedi http://www.comedi.org"); -MODULE_DESCRIPTION("Comedi low-level driver"); +MODULE_DESCRIPTION("Comedi driver for General Standards PCI-HPDI32/PMC-HPDI32"); MODULE_LICENSE("GPL"); diff --git a/drivers/staging/comedi/drivers/me4000.c b/drivers/staging/comedi/drivers/me4000.c index 7a8c27dd7154..a8f3ca48784b 100644 --- a/drivers/staging/comedi/drivers/me4000.c +++ b/drivers/staging/comedi/drivers/me4000.c @@ -453,7 +453,7 @@ static int me4000_ai_insn_read(struct comedi_device *dev, struct comedi_subdevice *subdevice, struct comedi_insn *insn, unsigned int *data) { - const struct me4000_board *thisboard = dev->board_ptr; + const struct me4000_board *board = dev->board_ptr; int chan = CR_CHAN(insn->chanspec); int rang = CR_RANGE(insn->chanspec); int aref = CR_AREF(insn->chanspec); @@ -491,7 +491,7 @@ static int me4000_ai_insn_read(struct comedi_device *dev, switch (aref) { case AREF_GROUND: case AREF_COMMON: - if (chan >= thisboard->ai_nchan) { + if (chan >= board->ai_nchan) { dev_err(dev->class_dev, "Analog input is not available\n"); return -EINVAL; @@ -506,7 +506,7 @@ static int me4000_ai_insn_read(struct comedi_device *dev, return -EINVAL; } - if (chan >= thisboard->ai_diff_nchan) { + if (chan >= board->ai_diff_nchan) { dev_err(dev->class_dev, "Analog input is not available\n"); return -EINVAL; @@ -1252,17 +1252,17 @@ static int me4000_auto_attach(struct comedi_device *dev, unsigned long context) { struct pci_dev *pcidev = comedi_to_pci_dev(dev); - const struct me4000_board *thisboard = NULL; + const struct me4000_board *board = NULL; struct me4000_info *info; struct comedi_subdevice *s; int result; if (context < ARRAY_SIZE(me4000_boards)) - thisboard = &me4000_boards[context]; - if (!thisboard) + board = &me4000_boards[context]; + if (!board) return -ENODEV; - dev->board_ptr = thisboard; - dev->board_name = thisboard->name; + dev->board_ptr = board; + dev->board_name = board->name; info = comedi_alloc_devpriv(dev, sizeof(*info)); if (!info) @@ -1301,11 +1301,11 @@ static int me4000_auto_attach(struct comedi_device *dev, s = &dev->subdevices[0]; - if (thisboard->ai_nchan) { + if (board->ai_nchan) { s->type = COMEDI_SUBD_AI; s->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_GROUND | SDF_DIFF; - s->n_chan = thisboard->ai_nchan; + s->n_chan = board->ai_nchan; s->maxdata = 0xFFFF; /* 16 bit ADC */ s->len_chanlist = ME4000_AI_CHANNEL_LIST_COUNT; s->range_table = &me4000_ai_range; @@ -1328,10 +1328,10 @@ static int me4000_auto_attach(struct comedi_device *dev, s = &dev->subdevices[1]; - if (thisboard->ao_nchan) { + if (board->ao_nchan) { s->type = COMEDI_SUBD_AO; s->subdev_flags = SDF_WRITABLE | SDF_COMMON | SDF_GROUND; - s->n_chan = thisboard->ao_nchan; + s->n_chan = board->ao_nchan; s->maxdata = 0xFFFF; /* 16 bit DAC */ s->range_table = &range_bipolar10; s->insn_write = me4000_ao_insn_write; @@ -1349,10 +1349,10 @@ static int me4000_auto_attach(struct comedi_device *dev, s = &dev->subdevices[2]; - if (thisboard->dio_nchan) { + if (board->dio_nchan) { s->type = COMEDI_SUBD_DIO; s->subdev_flags = SDF_READABLE | SDF_WRITABLE; - s->n_chan = thisboard->dio_nchan; + s->n_chan = board->dio_nchan; s->maxdata = 1; s->range_table = &range_digital; s->insn_bits = me4000_dio_insn_bits; @@ -1373,7 +1373,7 @@ static int me4000_auto_attach(struct comedi_device *dev, /* Counter subdevice (8254) */ s = &dev->subdevices[3]; - if (thisboard->has_counter) { + if (board->has_counter) { unsigned long timer_base = pci_resource_start(pcidev, 3); if (!timer_base) diff --git a/drivers/staging/comedi/drivers/me_daq.c b/drivers/staging/comedi/drivers/me_daq.c index d78e9195fbce..9ea1ba4b1b6f 100644 --- a/drivers/staging/comedi/drivers/me_daq.c +++ b/drivers/staging/comedi/drivers/me_daq.c @@ -173,8 +173,7 @@ struct me_private_data { static inline void sleep(unsigned sec) { - __set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(sec * HZ); + schedule_timeout_interruptible(sec * HZ); } static int me_dio_insn_config(struct comedi_device *dev, diff --git a/drivers/staging/comedi/drivers/mite.c b/drivers/staging/comedi/drivers/mite.c index e43a0c8323c1..fa7ae2c04556 100644 --- a/drivers/staging/comedi/drivers/mite.c +++ b/drivers/staging/comedi/drivers/mite.c @@ -1,52 +1,51 @@ /* - comedi/drivers/mite.c - Hardware driver for NI Mite PCI interface chip - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * comedi/drivers/mite.c + * Hardware driver for NI Mite PCI interface chip + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ /* - The PCI-MIO E series driver was originally written by - Tomasz Motylewski <...>, and ported to comedi by ds. - - References for specifications: - - 321747b.pdf Register Level Programmer Manual (obsolete) - 321747c.pdf Register Level Programmer Manual (new) - DAQ-STC reference manual - - Other possibly relevant info: - - 320517c.pdf User manual (obsolete) - 320517f.pdf User manual (new) - 320889a.pdf delete - 320906c.pdf maximum signal ratings - 321066a.pdf about 16x - 321791a.pdf discontinuation of at-mio-16e-10 rev. c - 321808a.pdf about at-mio-16e-10 rev P - 321837a.pdf discontinuation of at-mio-16de-10 rev d - 321838a.pdf about at-mio-16de-10 rev N - - ISSUES: - -*/ - -/* #define USE_KMALLOC */ + * The PCI-MIO E series driver was originally written by + * Tomasz Motylewski <...>, and ported to comedi by ds. + * + * References for specifications: + * + * 321747b.pdf Register Level Programmer Manual (obsolete) + * 321747c.pdf Register Level Programmer Manual (new) + * DAQ-STC reference manual + * + * Other possibly relevant info: + * + * 320517c.pdf User manual (obsolete) + * 320517f.pdf User manual (new) + * 320889a.pdf delete + * 320906c.pdf maximum signal ratings + * 321066a.pdf about 16x + * 321791a.pdf discontinuation of at-mio-16e-10 rev. c + * 321808a.pdf about at-mio-16e-10 rev P + * 321837a.pdf discontinuation of at-mio-16de-10 rev d + * 321838a.pdf about at-mio-16de-10 rev N + * + * ISSUES: + * + */ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include <linux/module.h> +#include <linux/slab.h> #include "../comedi_pci.h" @@ -132,7 +131,7 @@ int mite_setup2(struct comedi_device *dev, mite->mite_io_addr + MITE_IODWBSR); } /* - * make sure dma bursts work. I got this from running a bus analyzer + * Make sure dma bursts work. I got this from running a bus analyzer * on a pxi-6281 and a pxi-6713. 6713 powered up with register value * of 0x61f and bursts worked. 6281 powered up with register value of * 0x1f and bursts didn't work. The NI windows driver reads the @@ -224,7 +223,8 @@ struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite, unsigned long flags; struct mite_channel *channel = NULL; - /* spin lock so mite_release_channel can be called safely + /* + * spin lock so mite_release_channel can be called safely * from interrupts */ spin_lock_irqsave(&mite->lock, flags); @@ -246,15 +246,15 @@ void mite_release_channel(struct mite_channel *mite_chan) struct mite_struct *mite = mite_chan->mite; unsigned long flags; - /* spin lock to prevent races with mite_request_channel */ + /* spin lock to prevent races with mite_request_channel */ spin_lock_irqsave(&mite->lock, flags); if (mite->channel_allocated[mite_chan->channel]) { mite_dma_disarm(mite_chan); mite_dma_reset(mite_chan); - /* - * disable all channel's interrupts (do it after disarm/reset so - * MITE_CHCR reg isn't changed while dma is still active!) - */ + /* + * disable all channel's interrupts (do it after disarm/reset so + * MITE_CHCR reg isn't changed while dma is still active!) + */ writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE | @@ -286,7 +286,7 @@ void mite_dma_arm(struct mite_channel *mite_chan) writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); mmiowb(); spin_unlock_irqrestore(&mite->lock, flags); -/* mite_dma_tcr(mite, channel); */ + /* mite_dma_tcr(mite, channel); */ } EXPORT_SYMBOL_GPL(mite_dma_arm); @@ -529,8 +529,10 @@ int mite_sync_input_dma(struct mite_channel *mite_chan, } count = nbytes - async->buf_write_count; - /* it's possible count will be negative due to - * conservative value returned by mite_bytes_written_to_memory_lb */ + /* + * it's possible count will be negative due to conservative value + * returned by mite_bytes_written_to_memory_lb + */ if (count <= 0) return 0; @@ -551,7 +553,7 @@ int mite_sync_output_dma(struct mite_channel *mite_chan, u32 nbytes_ub, nbytes_lb; int count; - /* read alloc as much as we can */ + /* read alloc as much as we can */ comedi_buf_read_alloc(s, async->prealloc_bufsz); nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan); if (cmd->stop_src == TRIG_COUNT && (int)(nbytes_lb - stop_count) > 0) @@ -622,5 +624,5 @@ module_init(mite_module_init); module_exit(mite_module_exit); MODULE_AUTHOR("Comedi http://www.comedi.org"); -MODULE_DESCRIPTION("Comedi low-level driver"); +MODULE_DESCRIPTION("Comedi helper for NI Mite PCI interface chip"); MODULE_LICENSE("GPL"); diff --git a/drivers/staging/comedi/drivers/mite.h b/drivers/staging/comedi/drivers/mite.h index b3ca7fc3a31e..c32d4e4ddccc 100644 --- a/drivers/staging/comedi/drivers/mite.h +++ b/drivers/staging/comedi/drivers/mite.h @@ -1,32 +1,35 @@ /* - module/mite.h - Hardware driver for NI Mite PCI interface chip - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 1999 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * module/mite.h + * Hardware driver for NI Mite PCI interface chip + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 1999 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ #ifndef _MITE_H_ #define _MITE_H_ +#include <linux/io.h> #include <linux/log2.h> -#include <linux/slab.h> -#include "../comedi_pci.h" - -#define PCIMIO_COMPAT +#include <linux/spinlock.h> #define MAX_MITE_DMA_CHANNELS 8 +struct comedi_device; +struct comedi_subdevice; +struct device; +struct pci_dev; + struct mite_dma_descriptor { __le32 count; __le32 addr; @@ -74,16 +77,13 @@ static inline int mite_setup(struct comedi_device *dev, void mite_detach(struct mite_struct *mite); struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite); void mite_free_ring(struct mite_dma_descriptor_ring *ring); -struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite, - struct - mite_dma_descriptor_ring - *ring, unsigned min_channel, - unsigned max_channel); -static inline struct mite_channel *mite_request_channel(struct mite_struct - *mite, - struct - mite_dma_descriptor_ring - *ring) +struct mite_channel * +mite_request_channel_in_range(struct mite_struct *mite, + struct mite_dma_descriptor_ring *ring, + unsigned min_channel, unsigned max_channel); +static inline struct mite_channel * +mite_request_channel(struct mite_struct *mite, + struct mite_dma_descriptor_ring *ring) { return mite_request_channel_in_range(mite, ring, 0, mite->num_channels - 1); @@ -112,12 +112,14 @@ int mite_buf_change(struct mite_dma_descriptor_ring *ring, struct comedi_subdevice *s); enum mite_registers { - /* The bits 0x90180700 in MITE_UNKNOWN_DMA_BURST_REG can be - written and read back. The bits 0x1f always read as 1. - The rest always read as zero. */ + /* + * The bits 0x90180700 in MITE_UNKNOWN_DMA_BURST_REG can be + * written and read back. The bits 0x1f always read as 1. + * The rest always read as zero. + */ MITE_UNKNOWN_DMA_BURST_REG = 0x28, MITE_IODWBSR = 0xc0, /* IO Device Window Base Size Register */ - MITE_IODWBSR_1 = 0xc4, /* IO Device Window Base Size Register 1 */ + MITE_IODWBSR_1 = 0xc4, /* IO Device Window Base Size Register 1 */ MITE_IODWCR_1 = 0xf4, MITE_PCI_CONFIG_OFFSET = 0x300, MITE_CSIGR = 0x460 /* chip signature */ @@ -143,7 +145,7 @@ enum mite_registers { #define MITE_FCR(x) (0x40 + MITE_CHAN(x)) /* fifo count */ enum MITE_IODWBSR_bits { - WENAB = 0x80, /* window enable */ + WENAB = 0x80, /* window enable */ }; static inline unsigned MITE_IODWBSR_1_WSIZE_bits(unsigned size) @@ -166,27 +168,27 @@ static inline int mite_csigr_version(u32 csigr_bits) }; static inline int mite_csigr_type(u32 csigr_bits) -{ /* original mite = 0, minimite = 1 */ +{ /* original mite = 0, minimite = 1 */ return (csigr_bits >> 4) & 0xf; }; static inline int mite_csigr_mmode(u32 csigr_bits) -{ /* mite mode, minimite = 1 */ +{ /* mite mode, minimite = 1 */ return (csigr_bits >> 8) & 0x3; }; static inline int mite_csigr_imode(u32 csigr_bits) -{ /* cpu port interface mode, pci = 0x3 */ +{ /* cpu port interface mode, pci = 0x3 */ return (csigr_bits >> 12) & 0x3; }; static inline int mite_csigr_dmac(u32 csigr_bits) -{ /* number of dma channels */ +{ /* number of dma channels */ return (csigr_bits >> 16) & 0xf; }; static inline int mite_csigr_wpdep(u32 csigr_bits) -{ /* write post fifo depth */ +{ /* write post fifo depth */ unsigned int wpdep_bits = (csigr_bits >> 20) & 0x7; return (wpdep_bits) ? (1 << (wpdep_bits - 1)) : 0; @@ -198,7 +200,7 @@ static inline int mite_csigr_wins(u32 csigr_bits) }; static inline int mite_csigr_iowins(u32 csigr_bits) -{ /* number of io windows */ +{ /* number of io windows */ return (csigr_bits >> 29) & 0x7; }; @@ -280,6 +282,7 @@ enum ConfigRegister_bits { CR_PORTMXI = (3 << 6), CR_AMDEVICE = (1 << 0), }; + static inline int CR_REQS(int source) { return (source & 0x7) << 16; @@ -287,8 +290,7 @@ static inline int CR_REQS(int source) static inline int CR_REQSDRQ(unsigned drq_line) { - /* This also works on m-series when - using channels (drq_line) 4 or 5. */ + /* This also works on m-series when using channels (drq_line) 4 or 5. */ return CR_REQS((drq_line & 0x3) | 0x4); } diff --git a/drivers/staging/comedi/drivers/ni_670x.c b/drivers/staging/comedi/drivers/ni_670x.c index 13c6ccb1fdea..f4c580f65a89 100644 --- a/drivers/staging/comedi/drivers/ni_670x.c +++ b/drivers/staging/comedi/drivers/ni_670x.c @@ -172,18 +172,18 @@ static int ni_670x_auto_attach(struct comedi_device *dev, unsigned long context) { struct pci_dev *pcidev = comedi_to_pci_dev(dev); - const struct ni_670x_board *thisboard = NULL; + const struct ni_670x_board *board = NULL; struct ni_670x_private *devpriv; struct comedi_subdevice *s; int ret; int i; if (context < ARRAY_SIZE(ni_670x_boards)) - thisboard = &ni_670x_boards[context]; - if (!thisboard) + board = &ni_670x_boards[context]; + if (!board) return -ENODEV; - dev->board_ptr = thisboard; - dev->board_name = thisboard->name; + dev->board_ptr = board; + dev->board_name = board->name; ret = comedi_pci_enable(dev); if (ret) @@ -209,7 +209,7 @@ static int ni_670x_auto_attach(struct comedi_device *dev, /* analog output subdevice */ s->type = COMEDI_SUBD_AO; s->subdev_flags = SDF_WRITABLE; - s->n_chan = thisboard->ao_chans; + s->n_chan = board->ao_chans; s->maxdata = 0xffff; if (s->n_chan == 32) { const struct comedi_lrange **range_table_list; diff --git a/drivers/staging/comedi/drivers/ni_at_a2150.c b/drivers/staging/comedi/drivers/ni_at_a2150.c index 3a972d1538ab..9b444f8c4e33 100644 --- a/drivers/staging/comedi/drivers/ni_at_a2150.c +++ b/drivers/staging/comedi/drivers/ni_at_a2150.c @@ -106,7 +106,7 @@ TRIG_WAKE_EOS #define IRQ_LVL_BITS(x) (((x) & 0xf) << 4) /* sets irq level */ #define FIFO_INTR_EN_BIT 0x100 /* enable fifo interrupts */ #define FIFO_INTR_FHF_BIT 0x200 /* interrupt fifo half full */ -#define DMA_INTR_EN_BIT 0x800 /* enable interrupt on dma terminal count */ +#define DMA_INTR_EN_BIT 0x800 /* enable interrupt on dma terminal count */ #define DMA_DEM_EN_BIT 0x1000 /* enables demand mode dma */ #define I8253_BASE_REG 0x14 @@ -264,7 +264,7 @@ static int a2150_cancel(struct comedi_device *dev, struct comedi_subdevice *s) static int a2150_get_timing(struct comedi_device *dev, unsigned int *period, unsigned int flags) { - const struct a2150_board *thisboard = dev->board_ptr; + const struct a2150_board *board = dev->board_ptr; struct a2150_private *devpriv = dev->private; int lub, glb, temp; int lub_divisor_shift, lub_index, glb_divisor_shift, glb_index; @@ -273,10 +273,10 @@ static int a2150_get_timing(struct comedi_device *dev, unsigned int *period, /* initialize greatest lower and least upper bounds */ lub_divisor_shift = 3; lub_index = 0; - lub = thisboard->clock[lub_index] * (1 << lub_divisor_shift); + lub = board->clock[lub_index] * (1 << lub_divisor_shift); glb_divisor_shift = 0; - glb_index = thisboard->num_clocks - 1; - glb = thisboard->clock[glb_index] * (1 << glb_divisor_shift); + glb_index = board->num_clocks - 1; + glb = board->clock[glb_index] * (1 << glb_divisor_shift); /* make sure period is in available range */ if (*period < glb) @@ -287,9 +287,9 @@ static int a2150_get_timing(struct comedi_device *dev, unsigned int *period, /* we can multiply period by 1, 2, 4, or 8, using (1 << i) */ for (i = 0; i < 4; i++) { /* there are a maximum of 4 master clocks */ - for (j = 0; j < thisboard->num_clocks; j++) { + for (j = 0; j < board->num_clocks; j++) { /* temp is the period in nanosec we are evaluating */ - temp = thisboard->clock[j] * (1 << i); + temp = board->clock[j] * (1 << i); /* if it is the best match yet */ if (temp < lub && temp >= *period) { lub_divisor_shift = i; @@ -413,7 +413,7 @@ static int a2150_ai_check_chanlist(struct comedi_device *dev, static int a2150_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_cmd *cmd) { - const struct a2150_board *thisboard = dev->board_ptr; + const struct a2150_board *board = dev->board_ptr; int err = 0; unsigned int arg; @@ -444,7 +444,7 @@ static int a2150_ai_cmdtest(struct comedi_device *dev, if (cmd->convert_src == TRIG_TIMER) { err |= comedi_check_trigger_arg_min(&cmd->convert_arg, - thisboard->ai_speed); + board->ai_speed); } err |= comedi_check_trigger_arg_min(&cmd->chanlist_len, 1); @@ -687,17 +687,19 @@ static void a2150_free_dma(struct comedi_device *dev) comedi_isadma_free(devpriv->dma); } -/* probes board type, returns offset */ -static int a2150_probe(struct comedi_device *dev) +static const struct a2150_board *a2150_probe(struct comedi_device *dev) { - int status = inw(dev->iobase + STATUS_REG); + int id = ID_BITS(inw(dev->iobase + STATUS_REG)); - return ID_BITS(status); + if (id >= ARRAY_SIZE(a2150_boards)) + return NULL; + + return &a2150_boards[id]; } static int a2150_attach(struct comedi_device *dev, struct comedi_devconfig *it) { - const struct a2150_board *thisboard; + const struct a2150_board *board; struct a2150_private *devpriv; struct comedi_subdevice *s; static const int timeout = 2000; @@ -712,13 +714,11 @@ static int a2150_attach(struct comedi_device *dev, struct comedi_devconfig *it) if (ret) return ret; - i = a2150_probe(dev); - if (i >= ARRAY_SIZE(a2150_boards)) + board = a2150_probe(dev); + if (!board) return -ENODEV; - - dev->board_ptr = a2150_boards + i; - thisboard = dev->board_ptr; - dev->board_name = thisboard->name; + dev->board_ptr = board; + dev->board_name = board->name; /* an IRQ and DMA are required to support async commands */ a2150_alloc_irq_and_dma(dev, it); diff --git a/drivers/staging/comedi/drivers/ni_atmio.c b/drivers/staging/comedi/drivers/ni_atmio.c index 1304b06980a6..95435b81aa55 100644 --- a/drivers/staging/comedi/drivers/ni_atmio.c +++ b/drivers/staging/comedi/drivers/ni_atmio.c @@ -274,14 +274,16 @@ static int ni_isapnp_find_board(struct pnp_dev **dev) return 0; } -static int ni_getboardtype(struct comedi_device *dev) +static const struct ni_board_struct *ni_atmio_probe(struct comedi_device *dev) { int device_id = ni_read_eeprom(dev, 511); int i; for (i = 0; i < ARRAY_SIZE(ni_boards); i++) { - if (ni_boards[i].device_id == device_id) - return i; + const struct ni_board_struct *board = &ni_boards[i]; + + if (board->device_id == device_id) + return board; } if (device_id == 255) dev_err(dev->class_dev, "can't find board\n"); @@ -292,17 +294,16 @@ static int ni_getboardtype(struct comedi_device *dev) dev_err(dev->class_dev, "unknown device ID %d -- contact author\n", device_id); - return -1; + return NULL; } static int ni_atmio_attach(struct comedi_device *dev, struct comedi_devconfig *it) { - const struct ni_board_struct *boardtype; + const struct ni_board_struct *board; struct pnp_dev *isapnp_dev; int ret; unsigned long iobase; - int board; unsigned int irq; ret = ni_alloc_private(dev); @@ -326,15 +327,11 @@ static int ni_atmio_attach(struct comedi_device *dev, if (ret) return ret; - /* get board type */ - - board = ni_getboardtype(dev); - if (board < 0) - return -EIO; - - dev->board_ptr = ni_boards + board; - boardtype = dev->board_ptr; - dev->board_name = boardtype->name; + board = ni_atmio_probe(dev); + if (!board) + return -ENODEV; + dev->board_ptr = board; + dev->board_name = board->name; /* irq stuff */ diff --git a/drivers/staging/comedi/drivers/ni_mio_common.c b/drivers/staging/comedi/drivers/ni_mio_common.c index c66affd993aa..6cc304a4c59b 100644 --- a/drivers/staging/comedi/drivers/ni_mio_common.c +++ b/drivers/staging/comedi/drivers/ni_mio_common.c @@ -60,7 +60,6 @@ /* A timeout count */ #define NI_TIMEOUT 1000 -static const unsigned old_RTSI_clock_channel = 7; /* Note: this table must match the ai_gain_* definitions */ static const short ni_gainlkup[][16] = { @@ -308,262 +307,154 @@ static uint8_t ni_readb(struct comedi_device *dev, int reg) * windowed STC registers to the m series register offsets. */ -static void m_series_stc_writel(struct comedi_device *dev, - uint32_t data, int reg) +struct mio_regmap { + unsigned int mio_reg; + int size; +}; + +static const struct mio_regmap m_series_stc_write_regmap[] = { + [NISTC_INTA_ACK_REG] = { 0x104, 2 }, + [NISTC_INTB_ACK_REG] = { 0x106, 2 }, + [NISTC_AI_CMD2_REG] = { 0x108, 2 }, + [NISTC_AO_CMD2_REG] = { 0x10a, 2 }, + [NISTC_G0_CMD_REG] = { 0x10c, 2 }, + [NISTC_G1_CMD_REG] = { 0x10e, 2 }, + [NISTC_AI_CMD1_REG] = { 0x110, 2 }, + [NISTC_AO_CMD1_REG] = { 0x112, 2 }, + /* + * NISTC_DIO_OUT_REG maps to: + * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 } + */ + [NISTC_DIO_OUT_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */ + [NISTC_DIO_CTRL_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */ + [NISTC_AI_MODE1_REG] = { 0x118, 2 }, + [NISTC_AI_MODE2_REG] = { 0x11a, 2 }, + [NISTC_AI_SI_LOADA_REG] = { 0x11c, 4 }, + [NISTC_AI_SI_LOADB_REG] = { 0x120, 4 }, + [NISTC_AI_SC_LOADA_REG] = { 0x124, 4 }, + [NISTC_AI_SC_LOADB_REG] = { 0x128, 4 }, + [NISTC_AI_SI2_LOADA_REG] = { 0x12c, 4 }, + [NISTC_AI_SI2_LOADB_REG] = { 0x130, 4 }, + [NISTC_G0_MODE_REG] = { 0x134, 2 }, + [NISTC_G1_MODE_REG] = { 0x136, 2 }, + [NISTC_G0_LOADA_REG] = { 0x138, 4 }, + [NISTC_G0_LOADB_REG] = { 0x13c, 4 }, + [NISTC_G1_LOADA_REG] = { 0x140, 4 }, + [NISTC_G1_LOADB_REG] = { 0x144, 4 }, + [NISTC_G0_INPUT_SEL_REG] = { 0x148, 2 }, + [NISTC_G1_INPUT_SEL_REG] = { 0x14a, 2 }, + [NISTC_AO_MODE1_REG] = { 0x14c, 2 }, + [NISTC_AO_MODE2_REG] = { 0x14e, 2 }, + [NISTC_AO_UI_LOADA_REG] = { 0x150, 4 }, + [NISTC_AO_UI_LOADB_REG] = { 0x154, 4 }, + [NISTC_AO_BC_LOADA_REG] = { 0x158, 4 }, + [NISTC_AO_BC_LOADB_REG] = { 0x15c, 4 }, + [NISTC_AO_UC_LOADA_REG] = { 0x160, 4 }, + [NISTC_AO_UC_LOADB_REG] = { 0x164, 4 }, + [NISTC_CLK_FOUT_REG] = { 0x170, 2 }, + [NISTC_IO_BIDIR_PIN_REG] = { 0x172, 2 }, + [NISTC_RTSI_TRIG_DIR_REG] = { 0x174, 2 }, + [NISTC_INT_CTRL_REG] = { 0x176, 2 }, + [NISTC_AI_OUT_CTRL_REG] = { 0x178, 2 }, + [NISTC_ATRIG_ETC_REG] = { 0x17a, 2 }, + [NISTC_AI_START_STOP_REG] = { 0x17c, 2 }, + [NISTC_AI_TRIG_SEL_REG] = { 0x17e, 2 }, + [NISTC_AI_DIV_LOADA_REG] = { 0x180, 4 }, + [NISTC_AO_START_SEL_REG] = { 0x184, 2 }, + [NISTC_AO_TRIG_SEL_REG] = { 0x186, 2 }, + [NISTC_G0_AUTOINC_REG] = { 0x188, 2 }, + [NISTC_G1_AUTOINC_REG] = { 0x18a, 2 }, + [NISTC_AO_MODE3_REG] = { 0x18c, 2 }, + [NISTC_RESET_REG] = { 0x190, 2 }, + [NISTC_INTA_ENA_REG] = { 0x192, 2 }, + [NISTC_INTA2_ENA_REG] = { 0, 0 }, /* E-Series only */ + [NISTC_INTB_ENA_REG] = { 0x196, 2 }, + [NISTC_INTB2_ENA_REG] = { 0, 0 }, /* E-Series only */ + [NISTC_AI_PERSONAL_REG] = { 0x19a, 2 }, + [NISTC_AO_PERSONAL_REG] = { 0x19c, 2 }, + [NISTC_RTSI_TRIGA_OUT_REG] = { 0x19e, 2 }, + [NISTC_RTSI_TRIGB_OUT_REG] = { 0x1a0, 2 }, + [NISTC_RTSI_BOARD_REG] = { 0, 0 }, /* Unknown */ + [NISTC_CFG_MEM_CLR_REG] = { 0x1a4, 2 }, + [NISTC_ADC_FIFO_CLR_REG] = { 0x1a6, 2 }, + [NISTC_DAC_FIFO_CLR_REG] = { 0x1a8, 2 }, + [NISTC_AO_OUT_CTRL_REG] = { 0x1ac, 2 }, + [NISTC_AI_MODE3_REG] = { 0x1ae, 2 }, +}; + +static void m_series_stc_write(struct comedi_device *dev, + unsigned int data, unsigned int reg) { - unsigned offset; + const struct mio_regmap *regmap; - switch (reg) { - case AI_SC_Load_A_Registers: - offset = M_Offset_AI_SC_Load_A; - break; - case AI_SI_Load_A_Registers: - offset = M_Offset_AI_SI_Load_A; - break; - case AO_BC_Load_A_Register: - offset = M_Offset_AO_BC_Load_A; - break; - case AO_UC_Load_A_Register: - offset = M_Offset_AO_UC_Load_A; - break; - case AO_UI_Load_A_Register: - offset = M_Offset_AO_UI_Load_A; - break; - case G_Load_A_Register(0): - offset = M_Offset_G0_Load_A; - break; - case G_Load_A_Register(1): - offset = M_Offset_G1_Load_A; - break; - case G_Load_B_Register(0): - offset = M_Offset_G0_Load_B; - break; - case G_Load_B_Register(1): - offset = M_Offset_G1_Load_B; - break; - default: - dev_warn(dev->class_dev, - "%s: bug! unhandled register=0x%x in switch\n", + if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) { + regmap = &m_series_stc_write_regmap[reg]; + } else { + dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n", __func__, reg); return; } - ni_writel(dev, data, offset); -} -static void m_series_stc_writew(struct comedi_device *dev, - uint16_t data, int reg) -{ - unsigned offset; - - switch (reg) { - case ADC_FIFO_Clear: - offset = M_Offset_AI_FIFO_Clear; - break; - case AI_Command_1_Register: - offset = M_Offset_AI_Command_1; - break; - case AI_Command_2_Register: - offset = M_Offset_AI_Command_2; - break; - case AI_Mode_1_Register: - offset = M_Offset_AI_Mode_1; - break; - case AI_Mode_2_Register: - offset = M_Offset_AI_Mode_2; - break; - case AI_Mode_3_Register: - offset = M_Offset_AI_Mode_3; - break; - case AI_Output_Control_Register: - offset = M_Offset_AI_Output_Control; - break; - case AI_Personal_Register: - offset = M_Offset_AI_Personal; - break; - case AI_SI2_Load_A_Register: - /* this is a 32 bit register on m series boards */ - ni_writel(dev, data, M_Offset_AI_SI2_Load_A); - return; - case AI_SI2_Load_B_Register: - /* this is a 32 bit register on m series boards */ - ni_writel(dev, data, M_Offset_AI_SI2_Load_B); - return; - case AI_START_STOP_Select_Register: - offset = M_Offset_AI_START_STOP_Select; - break; - case AI_Trigger_Select_Register: - offset = M_Offset_AI_Trigger_Select; - break; - case Analog_Trigger_Etc_Register: - offset = M_Offset_Analog_Trigger_Etc; - break; - case AO_Command_1_Register: - offset = M_Offset_AO_Command_1; - break; - case AO_Command_2_Register: - offset = M_Offset_AO_Command_2; - break; - case AO_Mode_1_Register: - offset = M_Offset_AO_Mode_1; - break; - case AO_Mode_2_Register: - offset = M_Offset_AO_Mode_2; - break; - case AO_Mode_3_Register: - offset = M_Offset_AO_Mode_3; - break; - case AO_Output_Control_Register: - offset = M_Offset_AO_Output_Control; - break; - case AO_Personal_Register: - offset = M_Offset_AO_Personal; - break; - case AO_Start_Select_Register: - offset = M_Offset_AO_Start_Select; - break; - case AO_Trigger_Select_Register: - offset = M_Offset_AO_Trigger_Select; - break; - case Clock_and_FOUT_Register: - offset = M_Offset_Clock_and_FOUT; - break; - case Configuration_Memory_Clear: - offset = M_Offset_Configuration_Memory_Clear; - break; - case DAC_FIFO_Clear: - offset = M_Offset_AO_FIFO_Clear; - break; - case DIO_Control_Register: - dev_dbg(dev->class_dev, - "%s: FIXME: register 0x%x does not map cleanly on to m-series boards\n", - __func__, reg); - return; - case G_Autoincrement_Register(0): - offset = M_Offset_G0_Autoincrement; - break; - case G_Autoincrement_Register(1): - offset = M_Offset_G1_Autoincrement; - break; - case G_Command_Register(0): - offset = M_Offset_G0_Command; - break; - case G_Command_Register(1): - offset = M_Offset_G1_Command; - break; - case G_Input_Select_Register(0): - offset = M_Offset_G0_Input_Select; - break; - case G_Input_Select_Register(1): - offset = M_Offset_G1_Input_Select; - break; - case G_Mode_Register(0): - offset = M_Offset_G0_Mode; - break; - case G_Mode_Register(1): - offset = M_Offset_G1_Mode; - break; - case Interrupt_A_Ack_Register: - offset = M_Offset_Interrupt_A_Ack; - break; - case Interrupt_A_Enable_Register: - offset = M_Offset_Interrupt_A_Enable; - break; - case Interrupt_B_Ack_Register: - offset = M_Offset_Interrupt_B_Ack; - break; - case Interrupt_B_Enable_Register: - offset = M_Offset_Interrupt_B_Enable; - break; - case Interrupt_Control_Register: - offset = M_Offset_Interrupt_Control; - break; - case IO_Bidirection_Pin_Register: - offset = M_Offset_IO_Bidirection_Pin; - break; - case Joint_Reset_Register: - offset = M_Offset_Joint_Reset; - break; - case RTSI_Trig_A_Output_Register: - offset = M_Offset_RTSI_Trig_A_Output; - break; - case RTSI_Trig_B_Output_Register: - offset = M_Offset_RTSI_Trig_B_Output; + switch (regmap->size) { + case 4: + ni_writel(dev, data, regmap->mio_reg); break; - case RTSI_Trig_Direction_Register: - offset = M_Offset_RTSI_Trig_Direction; + case 2: + ni_writew(dev, data, regmap->mio_reg); break; - /* - * FIXME: DIO_Output_Register (16 bit reg) is replaced by - * M_Offset_Static_Digital_Output (32 bit) and - * M_Offset_SCXI_Serial_Data_Out (8 bit) - */ default: - dev_warn(dev->class_dev, - "%s: bug! unhandled register=0x%x in switch\n", + dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n", __func__, reg); - return; + break; } - ni_writew(dev, data, offset); } -static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg) +static const struct mio_regmap m_series_stc_read_regmap[] = { + [NISTC_AI_STATUS1_REG] = { 0x104, 2 }, + [NISTC_AO_STATUS1_REG] = { 0x106, 2 }, + [NISTC_G01_STATUS_REG] = { 0x108, 2 }, + [NISTC_AI_STATUS2_REG] = { 0, 0 }, /* Unknown */ + [NISTC_AO_STATUS2_REG] = { 0x10c, 2 }, + [NISTC_DIO_IN_REG] = { 0, 0 }, /* Unknown */ + [NISTC_G0_HW_SAVE_REG] = { 0x110, 4 }, + [NISTC_G1_HW_SAVE_REG] = { 0x114, 4 }, + [NISTC_G0_SAVE_REG] = { 0x118, 4 }, + [NISTC_G1_SAVE_REG] = { 0x11c, 4 }, + [NISTC_AO_UI_SAVE_REG] = { 0x120, 4 }, + [NISTC_AO_BC_SAVE_REG] = { 0x124, 4 }, + [NISTC_AO_UC_SAVE_REG] = { 0x128, 4 }, + [NISTC_STATUS1_REG] = { 0x136, 2 }, + [NISTC_DIO_SERIAL_IN_REG] = { 0x009, 1 }, + [NISTC_STATUS2_REG] = { 0x13a, 2 }, + [NISTC_AI_SI_SAVE_REG] = { 0x180, 4 }, + [NISTC_AI_SC_SAVE_REG] = { 0x184, 4 }, +}; + +static unsigned int m_series_stc_read(struct comedi_device *dev, + unsigned int reg) { - unsigned offset; + const struct mio_regmap *regmap; - switch (reg) { - case G_HW_Save_Register(0): - offset = M_Offset_G0_HW_Save; - break; - case G_HW_Save_Register(1): - offset = M_Offset_G1_HW_Save; - break; - case G_Save_Register(0): - offset = M_Offset_G0_Save; - break; - case G_Save_Register(1): - offset = M_Offset_G1_Save; - break; - default: - dev_warn(dev->class_dev, - "%s: bug! unhandled register=0x%x in switch\n", + if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) { + regmap = &m_series_stc_read_regmap[reg]; + } else { + dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n", __func__, reg); return 0; } - return ni_readl(dev, offset); -} -static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg) -{ - unsigned offset; - - switch (reg) { - case AI_Status_1_Register: - offset = M_Offset_AI_Status_1; - break; - case AO_Status_1_Register: - offset = M_Offset_AO_Status_1; - break; - case AO_Status_2_Register: - offset = M_Offset_AO_Status_2; - break; - case DIO_Serial_Input_Register: - return ni_readb(dev, M_Offset_SCXI_Serial_Data_In); - case Joint_Status_1_Register: - offset = M_Offset_Joint_Status_1; - break; - case Joint_Status_2_Register: - offset = M_Offset_Joint_Status_2; - break; - case G_Status_Register: - offset = M_Offset_G01_Status; - break; + switch (regmap->size) { + case 4: + return ni_readl(dev, regmap->mio_reg); + case 2: + return ni_readw(dev, regmap->mio_reg); + case 1: + return ni_readb(dev, regmap->mio_reg); default: - dev_warn(dev->class_dev, - "%s: bug! unhandled register=0x%x in switch\n", + dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n", __func__, reg); return 0; } - return ni_readw(dev, offset); } static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg) @@ -572,14 +463,14 @@ static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg) unsigned long flags; if (devpriv->is_m_series) { - m_series_stc_writew(dev, data, reg); + m_series_stc_write(dev, data, reg); } else { spin_lock_irqsave(&devpriv->window_lock, flags); if (!devpriv->mite && reg < 8) { ni_writew(dev, data, reg * 2); } else { - ni_writew(dev, reg, Window_Address); - ni_writew(dev, data, Window_Data); + ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG); + ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG); } spin_unlock_irqrestore(&devpriv->window_lock, flags); } @@ -590,7 +481,7 @@ static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg) struct ni_private *devpriv = dev->private; if (devpriv->is_m_series) { - m_series_stc_writel(dev, data, reg); + m_series_stc_write(dev, data, reg); } else { ni_stc_writew(dev, data >> 16, reg); ni_stc_writew(dev, data & 0xffff, reg + 1); @@ -604,14 +495,14 @@ static uint16_t ni_stc_readw(struct comedi_device *dev, int reg) uint16_t val; if (devpriv->is_m_series) { - val = m_series_stc_readw(dev, reg); + val = m_series_stc_read(dev, reg); } else { spin_lock_irqsave(&devpriv->window_lock, flags); if (!devpriv->mite && reg < 8) { val = ni_readw(dev, reg * 2); } else { - ni_writew(dev, reg, Window_Address); - val = ni_readw(dev, Window_Data); + ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG); + val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG); } spin_unlock_irqrestore(&devpriv->window_lock, flags); } @@ -624,7 +515,7 @@ static uint32_t ni_stc_readl(struct comedi_device *dev, int reg) uint32_t val; if (devpriv->is_m_series) { - val = m_series_stc_readl(dev, reg); + val = m_series_stc_read(dev, reg); } else { val = ni_stc_readw(dev, reg) << 16; val |= ni_stc_readw(dev, reg + 1); @@ -640,33 +531,30 @@ static inline void ni_set_bitfield(struct comedi_device *dev, int reg, spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags); switch (reg) { - case Interrupt_A_Enable_Register: + case NISTC_INTA_ENA_REG: devpriv->int_a_enable_reg &= ~bit_mask; devpriv->int_a_enable_reg |= bit_values & bit_mask; - ni_stc_writew(dev, devpriv->int_a_enable_reg, - Interrupt_A_Enable_Register); + ni_stc_writew(dev, devpriv->int_a_enable_reg, reg); break; - case Interrupt_B_Enable_Register: + case NISTC_INTB_ENA_REG: devpriv->int_b_enable_reg &= ~bit_mask; devpriv->int_b_enable_reg |= bit_values & bit_mask; - ni_stc_writew(dev, devpriv->int_b_enable_reg, - Interrupt_B_Enable_Register); + ni_stc_writew(dev, devpriv->int_b_enable_reg, reg); break; - case IO_Bidirection_Pin_Register: + case NISTC_IO_BIDIR_PIN_REG: devpriv->io_bidirection_pin_reg &= ~bit_mask; devpriv->io_bidirection_pin_reg |= bit_values & bit_mask; - ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, - IO_Bidirection_Pin_Register); + ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg); break; - case AI_AO_Select: + case NI_E_DMA_AI_AO_SEL_REG: devpriv->ai_ao_select_reg &= ~bit_mask; devpriv->ai_ao_select_reg |= bit_values & bit_mask; - ni_writeb(dev, devpriv->ai_ao_select_reg, AI_AO_Select); + ni_writeb(dev, devpriv->ai_ao_select_reg, reg); break; - case G0_G1_Select: + case NI_E_DMA_G0_G1_SEL_REG: devpriv->g0_g1_select_reg &= ~bit_mask; devpriv->g0_g1_select_reg |= bit_values & bit_mask; - ni_writeb(dev, devpriv->g0_g1_select_reg, G0_G1_Select); + ni_writeb(dev, devpriv->g0_g1_select_reg, reg); break; default: dev_err(dev->class_dev, "called with invalid register %d\n", @@ -679,48 +567,55 @@ static inline void ni_set_bitfield(struct comedi_device *dev, int reg, #ifdef PCIDMA /* DMA channel setup */ +static inline unsigned ni_stc_dma_channel_select_bitfield(unsigned channel) +{ + if (channel < 4) + return 1 << channel; + if (channel == 4) + return 0x3; + if (channel == 5) + return 0x5; + BUG(); + return 0; +} /* negative channel means no channel */ static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel) { - unsigned bitfield; + unsigned bits = 0; if (channel >= 0) - bitfield = - (ni_stc_dma_channel_select_bitfield(channel) << - AI_DMA_Select_Shift) & AI_DMA_Select_Mask; - else - bitfield = 0; - ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield); + bits = ni_stc_dma_channel_select_bitfield(channel); + + ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, + NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits)); } /* negative channel means no channel */ static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel) { - unsigned bitfield; + unsigned bits = 0; if (channel >= 0) - bitfield = - (ni_stc_dma_channel_select_bitfield(channel) << - AO_DMA_Select_Shift) & AO_DMA_Select_Mask; - else - bitfield = 0; - ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield); + bits = ni_stc_dma_channel_select_bitfield(channel); + + ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, + NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits)); } -/* negative mite_channel means no channel */ +/* negative channel means no channel */ static inline void ni_set_gpct_dma_channel(struct comedi_device *dev, unsigned gpct_index, - int mite_channel) + int channel) { - unsigned bitfield; + unsigned bits = 0; - if (mite_channel >= 0) - bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel); - else - bitfield = 0; - ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index), - bitfield); + if (channel >= 0) + bits = ni_stc_dma_channel_select_bitfield(channel); + + ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG, + NI_E_DMA_G0_G1_SEL_MASK(gpct_index), + NI_E_DMA_G0_G1_SEL(gpct_index, bits)); } /* negative mite_channel means no channel */ @@ -729,18 +624,21 @@ static inline void ni_set_cdo_dma_channel(struct comedi_device *dev, { struct ni_private *devpriv = dev->private; unsigned long flags; + unsigned bits; spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags); - devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask; + devpriv->cdio_dma_select_reg &= ~NI_M_CDIO_DMA_SEL_CDO_MASK; if (mite_channel >= 0) { - /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits, - under the assumption the cdio dma selection works just like ai/ao/gpct. - Definitely works for dma channels 0 and 1. */ - devpriv->cdio_dma_select_reg |= - (ni_stc_dma_channel_select_bitfield(mite_channel) << - CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask; - } - ni_writeb(dev, devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select); + /* + * XXX just guessing ni_stc_dma_channel_select_bitfield() + * returns the right bits, under the assumption the cdio dma + * selection works just like ai/ao/gpct. + * Definitely works for dma channels 0 and 1. + */ + bits = ni_stc_dma_channel_select_bitfield(mite_channel); + devpriv->cdio_dma_select_reg |= NI_M_CDIO_DMA_SEL_CDO(bits); + } + ni_writeb(dev, devpriv->cdio_dma_select_reg, NI_M_CDIO_DMA_SEL_REG); mmiowb(); spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); } @@ -795,7 +693,6 @@ static int ni_request_gpct_mite_channel(struct comedi_device *dev, unsigned long flags; struct mite_channel *mite_chan; - BUG_ON(gpct_index >= NUM_GPCT); spin_lock_irqsave(&devpriv->mite_channel_lock, flags); BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan); mite_chan = @@ -879,7 +776,6 @@ static void ni_release_gpct_mite_channel(struct comedi_device *dev, struct ni_private *devpriv = dev->private; unsigned long flags; - BUG_ON(gpct_index >= NUM_GPCT); spin_lock_irqsave(&devpriv->mite_channel_lock, flags); if (devpriv->counter_dev->counters[gpct_index].mite_chan) { struct mite_channel *mite_chan = @@ -927,13 +823,13 @@ static void ni_e_series_enable_second_irq(struct comedi_device *dev, * dma requests for their counters */ if (gpct_index == 0) { - reg = Second_IRQ_A_Enable_Register; + reg = NISTC_INTA2_ENA_REG; if (enable) - val = G0_Gate_Second_Irq_Enable; + val = NISTC_INTA_ENA_G0_GATE; } else { - reg = Second_IRQ_B_Enable_Register; + reg = NISTC_INTB2_ENA_REG; if (enable) - val = G1_Gate_Second_Irq_Enable; + val = NISTC_INTB_ENA_G1_GATE; } ni_stc_writew(dev, val, reg); } @@ -947,30 +843,30 @@ static void ni_clear_ai_fifo(struct comedi_device *dev) if (devpriv->is_6143) { /* Flush the 6143 data FIFO */ - ni_writel(dev, 0x10, AIFIFO_Control_6143); - ni_writel(dev, 0x00, AIFIFO_Control_6143); + ni_writel(dev, 0x10, NI6143_AI_FIFO_CTRL_REG); + ni_writel(dev, 0x00, NI6143_AI_FIFO_CTRL_REG); /* Wait for complete */ for (i = 0; i < timeout; i++) { - if (!(ni_readl(dev, AIFIFO_Status_6143) & 0x10)) + if (!(ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x10)) break; udelay(1); } if (i == timeout) dev_err(dev->class_dev, "FIFO flush timeout\n"); } else { - ni_stc_writew(dev, 1, ADC_FIFO_Clear); + ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG); if (devpriv->is_625x) { - ni_writeb(dev, 0, M_Offset_Static_AI_Control(0)); - ni_writeb(dev, 1, M_Offset_Static_AI_Control(0)); + ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0)); + ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0)); #if 0 /* the NI example code does 3 convert pulses for 625x boards, but that appears to be wrong in practice. */ - ni_stc_writew(dev, AI_CONVERT_Pulse, - AI_Command_1_Register); - ni_stc_writew(dev, AI_CONVERT_Pulse, - AI_Command_1_Register); - ni_stc_writew(dev, AI_CONVERT_Pulse, - AI_Command_1_Register); + ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, + NISTC_AI_CMD1_REG); + ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, + NISTC_AI_CMD1_REG); + ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, + NISTC_AI_CMD1_REG); #endif } } @@ -983,8 +879,8 @@ static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data, unsigned long flags; spin_lock_irqsave(&devpriv->window_lock, flags); - ni_writew(dev, addr, AO_Window_Address_611x); - ni_writew(dev, data, AO_Window_Data_611x); + ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG); + ni_writew(dev, data, NI611X_AO_WINDOW_DATA_REG); spin_unlock_irqrestore(&devpriv->window_lock, flags); } @@ -995,8 +891,8 @@ static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data, unsigned long flags; spin_lock_irqsave(&devpriv->window_lock, flags); - ni_writew(dev, addr, AO_Window_Address_611x); - ni_writel(dev, data, AO_Window_Data_611x); + ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG); + ni_writel(dev, data, NI611X_AO_WINDOW_DATA_REG); spin_unlock_irqrestore(&devpriv->window_lock, flags); } @@ -1007,8 +903,8 @@ static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr) unsigned short data; spin_lock_irqsave(&devpriv->window_lock, flags); - ni_writew(dev, addr, AO_Window_Address_611x); - data = ni_readw(dev, AO_Window_Data_611x); + ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG); + data = ni_readw(dev, NI611X_AO_WINDOW_DATA_REG); spin_unlock_irqrestore(&devpriv->window_lock, flags); return data; } @@ -1059,8 +955,8 @@ static int ni_ai_drain_dma(struct comedi_device *dev) spin_lock_irqsave(&devpriv->mite_channel_lock, flags); if (devpriv->ai_mite_chan) { for (i = 0; i < timeout; i++) { - if ((ni_stc_readw(dev, AI_Status_1_Register) & - AI_FIFO_Empty_St) + if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & + NISTC_AI_STATUS1_FIFO_E) && mite_bytes_in_transit(devpriv->ai_mite_chan) == 0) break; @@ -1071,7 +967,7 @@ static int ni_ai_drain_dma(struct comedi_device *dev) dev_err(dev->class_dev, "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n", mite_bytes_in_transit(devpriv->ai_mite_chan), - ni_stc_readw(dev, AI_Status_1_Register)); + ni_stc_readw(dev, NISTC_AI_STATUS1_REG)); retval = -1; } } @@ -1103,8 +999,8 @@ static int ni_ao_wait_for_dma_load(struct comedi_device *dev) for (i = 0; i < timeout; i++) { unsigned short b_status; - b_status = ni_stc_readw(dev, AO_Status_1_Register); - if (b_status & AO_FIFO_Half_Full_St) + b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG); + if (b_status & NISTC_AO_STATUS1_FIFO_HF) break; /* if we poll too often, the pci bus activity seems to slow the dma transfer down */ @@ -1139,9 +1035,9 @@ static void ni_ao_fifo_load(struct comedi_device *dev, i++; packed_data |= (d << 16) & 0xffff0000; } - ni_writel(dev, packed_data, DAC_FIFO_Data_611x); + ni_writel(dev, packed_data, NI611X_AO_FIFO_DATA_REG); } else { - ni_writew(dev, d, DAC_FIFO_Data); + ni_writew(dev, d, NI_E_AO_FIFO_DATA_REG); } } } @@ -1193,9 +1089,9 @@ static int ni_ao_prep_fifo(struct comedi_device *dev, unsigned int nsamples; /* reset fifo */ - ni_stc_writew(dev, 1, DAC_FIFO_Clear); + ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG); if (devpriv->is_6xxx) - ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x); + ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG); /* load some data */ nbytes = comedi_buf_read_n_available(s); @@ -1222,7 +1118,7 @@ static void ni_ai_fifo_read(struct comedi_device *dev, if (devpriv->is_611x) { for (i = 0; i < n / 2; i++) { - dl = ni_readl(dev, ADC_FIFO_Data_611x); + dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG); /* This may get the hi/lo data in the wrong order */ data = (dl >> 16) & 0xffff; comedi_buf_write_samples(s, &data, 1); @@ -1231,14 +1127,14 @@ static void ni_ai_fifo_read(struct comedi_device *dev, } /* Check if there's a single sample stuck in the FIFO */ if (n % 2) { - dl = ni_readl(dev, ADC_FIFO_Data_611x); + dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG); data = dl & 0xffff; comedi_buf_write_samples(s, &data, 1); } } else if (devpriv->is_6143) { /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */ for (i = 0; i < n / 2; i++) { - dl = ni_readl(dev, AIFIFO_Data_6143); + dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG); data = (dl >> 16) & 0xffff; comedi_buf_write_samples(s, &data, 1); @@ -1248,8 +1144,8 @@ static void ni_ai_fifo_read(struct comedi_device *dev, if (n % 2) { /* Assume there is a single sample stuck in the FIFO */ /* Get stranded sample into FIFO */ - ni_writel(dev, 0x01, AIFIFO_Control_6143); - dl = ni_readl(dev, AIFIFO_Data_6143); + ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG); + dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG); data = (dl >> 16) & 0xffff; comedi_buf_write_samples(s, &data, 1); } @@ -1263,7 +1159,7 @@ static void ni_ai_fifo_read(struct comedi_device *dev, } for (i = 0; i < n; i++) { devpriv->ai_fifo_buffer[i] = - ni_readw(dev, ADC_FIFO_Data_Register); + ni_readw(dev, NI_E_AI_FIFO_DATA_REG); } comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n); } @@ -1294,9 +1190,9 @@ static void ni_handle_fifo_dregs(struct comedi_device *dev) int i; if (devpriv->is_611x) { - while ((ni_stc_readw(dev, AI_Status_1_Register) & - AI_FIFO_Empty_St) == 0) { - dl = ni_readl(dev, ADC_FIFO_Data_611x); + while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & + NISTC_AI_STATUS1_FIFO_E) == 0) { + dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG); /* This may get the hi/lo data in the wrong order */ data = dl >> 16; @@ -1306,8 +1202,8 @@ static void ni_handle_fifo_dregs(struct comedi_device *dev) } } else if (devpriv->is_6143) { i = 0; - while (ni_readl(dev, AIFIFO_Status_6143) & 0x04) { - dl = ni_readl(dev, AIFIFO_Data_6143); + while (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x04) { + dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG); /* This may get the hi/lo data in the wrong order */ data = dl >> 16; @@ -1317,29 +1213,29 @@ static void ni_handle_fifo_dregs(struct comedi_device *dev) i += 2; } /* Check if stranded sample is present */ - if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) { + if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) { /* Get stranded sample into FIFO */ - ni_writel(dev, 0x01, AIFIFO_Control_6143); - dl = ni_readl(dev, AIFIFO_Data_6143); + ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG); + dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG); data = (dl >> 16) & 0xffff; comedi_buf_write_samples(s, &data, 1); } } else { - fifo_empty = ni_stc_readw(dev, AI_Status_1_Register) & - AI_FIFO_Empty_St; + fifo_empty = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & + NISTC_AI_STATUS1_FIFO_E; while (fifo_empty == 0) { for (i = 0; i < sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0]); i++) { fifo_empty = ni_stc_readw(dev, - AI_Status_1_Register) & - AI_FIFO_Empty_St; + NISTC_AI_STATUS1_REG) & + NISTC_AI_STATUS1_FIFO_E; if (fifo_empty) break; devpriv->ai_fifo_buffer[i] = - ni_readw(dev, ADC_FIFO_Data_Register); + ni_readw(dev, NI_E_AI_FIFO_DATA_REG); } comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i); } @@ -1357,8 +1253,8 @@ static void get_last_sample_611x(struct comedi_device *dev) return; /* Check if there's a single sample stuck in the FIFO */ - if (ni_readb(dev, XXX_Status) & 0x80) { - dl = ni_readl(dev, ADC_FIFO_Data_611x); + if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) { + dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG); data = dl & 0xffff; comedi_buf_write_samples(s, &data, 1); } @@ -1375,10 +1271,10 @@ static void get_last_sample_6143(struct comedi_device *dev) return; /* Check if there's a single sample stuck in the FIFO */ - if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) { + if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) { /* Get stranded sample into FIFO */ - ni_writel(dev, 0x01, AIFIFO_Control_6143); - dl = ni_readl(dev, AIFIFO_Data_6143); + ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG); + dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG); /* This may get the hi/lo data in the wrong order */ data = (dl >> 16) & 0xffff; @@ -1420,8 +1316,8 @@ static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s) s->async->events |= COMEDI_CB_EOS; #endif } - /* handle special case of single scan using AI_End_On_End_Of_Scan */ - if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) + /* handle special case of single scan */ + if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS) shutdown_ai_command(dev); } @@ -1444,17 +1340,16 @@ static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status) { unsigned short ack = 0; - if (a_status & AI_SC_TC_St) - ack |= AI_SC_TC_Interrupt_Ack; - if (a_status & AI_START1_St) - ack |= AI_START1_Interrupt_Ack; - if (a_status & AI_START_St) - ack |= AI_START_Interrupt_Ack; - if (a_status & AI_STOP_St) - /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */ - ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */; + if (a_status & NISTC_AI_STATUS1_SC_TC) + ack |= NISTC_INTA_ACK_AI_SC_TC; + if (a_status & NISTC_AI_STATUS1_START1) + ack |= NISTC_INTA_ACK_AI_START1; + if (a_status & NISTC_AI_STATUS1_START) + ack |= NISTC_INTA_ACK_AI_START; + if (a_status & NISTC_AI_STATUS1_STOP) + ack |= NISTC_INTA_ACK_AI_STOP; if (ack) - ni_stc_writew(dev, ack, Interrupt_A_Ack_Register); + ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG); } static void handle_a_interrupt(struct comedi_device *dev, unsigned short status, @@ -1483,8 +1378,8 @@ static void handle_a_interrupt(struct comedi_device *dev, unsigned short status, #endif /* test for all uncommon interrupt events at the same time */ - if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St | - AI_SC_TC_St | AI_START1_St)) { + if (status & (NISTC_AI_STATUS1_ERR | + NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) { if (status == 0xffff) { dev_err(dev->class_dev, "Card removed?\n"); /* we probably aren't even running a command now, @@ -1495,41 +1390,40 @@ static void handle_a_interrupt(struct comedi_device *dev, unsigned short status, } return; } - if (status & (AI_Overrun_St | AI_Overflow_St | - AI_SC_TC_Error_St)) { + if (status & NISTC_AI_STATUS1_ERR) { dev_err(dev->class_dev, "ai error a_status=%04x\n", status); shutdown_ai_command(dev); s->async->events |= COMEDI_CB_ERROR; - if (status & (AI_Overrun_St | AI_Overflow_St)) + if (status & NISTC_AI_STATUS1_OVER) s->async->events |= COMEDI_CB_OVERFLOW; comedi_handle_events(dev, s); return; } - if (status & AI_SC_TC_St) { + if (status & NISTC_AI_STATUS1_SC_TC) { if (cmd->stop_src == TRIG_COUNT) shutdown_ai_command(dev); } } #ifndef PCIDMA - if (status & AI_FIFO_Half_Full_St) { + if (status & NISTC_AI_STATUS1_FIFO_HF) { int i; static const int timeout = 10; /* pcmcia cards (at least 6036) seem to stop producing interrupts if we *fail to get the fifo less than half full, so loop to be sure.*/ for (i = 0; i < timeout; ++i) { ni_handle_fifo_half_full(dev); - if ((ni_stc_readw(dev, AI_Status_1_Register) & - AI_FIFO_Half_Full_St) == 0) + if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & + NISTC_AI_STATUS1_FIFO_HF) == 0) break; } } #endif /* !PCIDMA */ - if ((status & AI_STOP_St)) + if (status & NISTC_AI_STATUS1_STOP) ni_handle_eos(dev, s); comedi_handle_events(dev, s); @@ -1539,22 +1433,22 @@ static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status) { unsigned short ack = 0; - if (b_status & AO_BC_TC_St) - ack |= AO_BC_TC_Interrupt_Ack; - if (b_status & AO_Overrun_St) - ack |= AO_Error_Interrupt_Ack; - if (b_status & AO_START_St) - ack |= AO_START_Interrupt_Ack; - if (b_status & AO_START1_St) - ack |= AO_START1_Interrupt_Ack; - if (b_status & AO_UC_TC_St) - ack |= AO_UC_TC_Interrupt_Ack; - if (b_status & AO_UI2_TC_St) - ack |= AO_UI2_TC_Interrupt_Ack; - if (b_status & AO_UPDATE_St) - ack |= AO_UPDATE_Interrupt_Ack; + if (b_status & NISTC_AO_STATUS1_BC_TC) + ack |= NISTC_INTB_ACK_AO_BC_TC; + if (b_status & NISTC_AO_STATUS1_OVERRUN) + ack |= NISTC_INTB_ACK_AO_ERR; + if (b_status & NISTC_AO_STATUS1_START) + ack |= NISTC_INTB_ACK_AO_START; + if (b_status & NISTC_AO_STATUS1_START1) + ack |= NISTC_INTB_ACK_AO_START1; + if (b_status & NISTC_AO_STATUS1_UC_TC) + ack |= NISTC_INTB_ACK_AO_UC_TC; + if (b_status & NISTC_AO_STATUS1_UI2_TC) + ack |= NISTC_INTB_ACK_AO_UI2_TC; + if (b_status & NISTC_AO_STATUS1_UPDATE) + ack |= NISTC_INTB_ACK_AO_UPDATE; if (ack) - ni_stc_writew(dev, ack, Interrupt_B_Ack_Register); + ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG); } static void handle_b_interrupt(struct comedi_device *dev, @@ -1583,26 +1477,26 @@ static void handle_b_interrupt(struct comedi_device *dev, if (b_status == 0xffff) return; - if (b_status & AO_Overrun_St) { + if (b_status & NISTC_AO_STATUS1_OVERRUN) { dev_err(dev->class_dev, "AO FIFO underrun status=0x%04x status2=0x%04x\n", - b_status, ni_stc_readw(dev, AO_Status_2_Register)); + b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG)); s->async->events |= COMEDI_CB_OVERFLOW; } - if (b_status & AO_BC_TC_St) + if (b_status & NISTC_AO_STATUS1_BC_TC) s->async->events |= COMEDI_CB_EOA; #ifndef PCIDMA - if (b_status & AO_FIFO_Request_St) { + if (b_status & NISTC_AO_STATUS1_FIFO_REQ) { int ret; ret = ni_ao_fifo_half_empty(dev, s); if (!ret) { dev_err(dev->class_dev, "AO buffer underrun\n"); - ni_set_bits(dev, Interrupt_B_Enable_Register, - AO_FIFO_Interrupt_Enable | - AO_Error_Interrupt_Enable, 0); + ni_set_bits(dev, NISTC_INTB_ENA_REG, + NISTC_INTB_ENA_AO_FIFO | + NISTC_INTB_ENA_AO_ERR, 0); s->async->events |= COMEDI_CB_OVERFLOW; } } @@ -1718,101 +1612,65 @@ static int ni_ao_setup_MITE_dma(struct comedi_device *dev) static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s) { struct ni_private *devpriv = dev->private; + unsigned ai_personal; + unsigned ai_out_ctrl; ni_release_ai_mite_channel(dev); /* ai configuration */ - ni_stc_writew(dev, AI_Configuration_Start | AI_Reset, - Joint_Reset_Register); + ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI, + NISTC_RESET_REG); - ni_set_bits(dev, Interrupt_A_Enable_Register, - AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable | - AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable | - AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable | - AI_FIFO_Interrupt_Enable, 0); + ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0); ni_clear_ai_fifo(dev); if (!devpriv->is_6143) - ni_writeb(dev, 0, Misc_Command); - - ni_stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */ - ni_stc_writew(dev, AI_Start_Stop | AI_Mode_1_Reserved - /*| AI_Trigger_Once */, - AI_Mode_1_Register); - ni_stc_writew(dev, 0x0000, AI_Mode_2_Register); + ni_writeb(dev, NI_E_MISC_CMD_EXT_ATRIG, NI_E_MISC_CMD_REG); + + ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG); + ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP | + NISTC_AI_MODE1_RSVD + /*| NISTC_AI_MODE1_TRIGGER_ONCE */, + NISTC_AI_MODE1_REG); + ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG); /* generate FIFO interrupts on non-empty */ - ni_stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register); + ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE, + NISTC_AI_MODE3_REG); + + ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW | + NISTC_AI_PERSONAL_SOC_POLARITY | + NISTC_AI_PERSONAL_LOCALMUX_CLK_PW; + ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) | + NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) | + NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) | + NISTC_AI_OUT_CTRL_SC_TC_SEL(3); if (devpriv->is_611x) { - ni_stc_writew(dev, - AI_SHIFTIN_Pulse_Width | - AI_SOC_Polarity | - AI_LOCALMUX_CLK_Pulse_Width, - AI_Personal_Register); - ni_stc_writew(dev, - AI_SCAN_IN_PROG_Output_Select(3) | - AI_EXTMUX_CLK_Output_Select(0) | - AI_LOCALMUX_CLK_Output_Select(2) | - AI_SC_TC_Output_Select(3) | - AI_CONVERT_Output_Select - (AI_CONVERT_Output_Enable_High), - AI_Output_Control_Register); + ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH; } else if (devpriv->is_6143) { - ni_stc_writew(dev, AI_SHIFTIN_Pulse_Width | - AI_SOC_Polarity | - AI_LOCALMUX_CLK_Pulse_Width, - AI_Personal_Register); - ni_stc_writew(dev, - AI_SCAN_IN_PROG_Output_Select(3) | - AI_EXTMUX_CLK_Output_Select(0) | - AI_LOCALMUX_CLK_Output_Select(2) | - AI_SC_TC_Output_Select(3) | - AI_CONVERT_Output_Select - (AI_CONVERT_Output_Enable_Low), - AI_Output_Control_Register); + ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW; } else { - unsigned ai_output_control_bits; - - ni_stc_writew(dev, - AI_SHIFTIN_Pulse_Width | - AI_SOC_Polarity | - AI_CONVERT_Pulse_Width | - AI_LOCALMUX_CLK_Pulse_Width, - AI_Personal_Register); - ai_output_control_bits = - AI_SCAN_IN_PROG_Output_Select(3) | - AI_EXTMUX_CLK_Output_Select(0) | - AI_LOCALMUX_CLK_Output_Select(2) | - AI_SC_TC_Output_Select(3); + ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW; if (devpriv->is_622x) - ai_output_control_bits |= - AI_CONVERT_Output_Select - (AI_CONVERT_Output_Enable_High); + ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH; else - ai_output_control_bits |= - AI_CONVERT_Output_Select - (AI_CONVERT_Output_Enable_Low); - ni_stc_writew(dev, ai_output_control_bits, - AI_Output_Control_Register); + ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW; } + ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG); + ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG); + /* the following registers should not be changed, because there * are no backup registers in devpriv. If you want to change * any of these, add a backup register and other appropriate code: - * AI_Mode_1_Register - * AI_Mode_3_Register - * AI_Personal_Register - * AI_Output_Control_Register + * NISTC_AI_MODE1_REG + * NISTC_AI_MODE3_REG + * NISTC_AI_PERSONAL_REG + * NISTC_AI_OUT_CTRL_REG */ - ni_stc_writew(dev, - AI_SC_TC_Error_Confirm | - AI_START_Interrupt_Ack | - AI_START2_Interrupt_Ack | - AI_START1_Interrupt_Ack | - AI_SC_TC_Interrupt_Ack | - AI_Error_Interrupt_Ack | - AI_STOP_Interrupt_Ack, - Interrupt_A_Ack_Register); /* clear interrupts */ - - ni_stc_writew(dev, AI_Configuration_End, Joint_Reset_Register); + + /* clear interrupts */ + ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG); + + ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG); return 0; } @@ -1839,11 +1697,11 @@ static void ni_prime_channelgain_list(struct comedi_device *dev) { int i; - ni_stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register); + ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG); for (i = 0; i < NI_TIMEOUT; ++i) { - if (!(ni_stc_readw(dev, AI_Status_1_Register) & - AI_FIFO_Empty_St)) { - ni_stc_writew(dev, 1, ADC_FIFO_Clear); + if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & + NISTC_AI_STATUS1_FIFO_E)) { + ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG); return; } udelay(1); @@ -1862,7 +1720,7 @@ static void ni_m_series_load_channelgain_list(struct comedi_device *dev, unsigned int dither; unsigned range_code; - ni_stc_writew(dev, 1, Configuration_Memory_Clear); + ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG); if ((list[0] & CR_ALT_SOURCE)) { unsigned bypass_bits; @@ -1871,22 +1729,17 @@ static void ni_m_series_load_channelgain_list(struct comedi_device *dev, range = CR_RANGE(list[0]); range_code = ni_gainlkup[board->gainlkup][range]; dither = (list[0] & CR_ALT_FILTER) != 0; - bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit; - bypass_bits |= chan; - bypass_bits |= - (devpriv->ai_calib_source) & - (MSeries_AI_Bypass_Cal_Sel_Pos_Mask | - MSeries_AI_Bypass_Cal_Sel_Neg_Mask | - MSeries_AI_Bypass_Mode_Mux_Mask | - MSeries_AO_Bypass_AO_Cal_Sel_Mask); - bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code); + bypass_bits = NI_M_CFG_BYPASS_FIFO | + NI_M_CFG_BYPASS_AI_CHAN(chan) | + NI_M_CFG_BYPASS_AI_GAIN(range_code) | + devpriv->ai_calib_source; if (dither) - bypass_bits |= MSeries_AI_Bypass_Dither_Bit; + bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER; /* don't use 2's complement encoding */ - bypass_bits |= MSeries_AI_Bypass_Polarity_Bit; - ni_writel(dev, bypass_bits, M_Offset_AI_Config_FIFO_Bypass); + bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY; + ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG); } else { - ni_writel(dev, 0, M_Offset_AI_Config_FIFO_Bypass); + ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG); } for (i = 0; i < n_chan; i++) { unsigned config_bits = 0; @@ -1900,31 +1753,27 @@ static void ni_m_series_load_channelgain_list(struct comedi_device *dev, devpriv->ai_offset[i] = 0; switch (aref) { case AREF_DIFF: - config_bits |= - MSeries_AI_Config_Channel_Type_Differential_Bits; + config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF; break; case AREF_COMMON: - config_bits |= - MSeries_AI_Config_Channel_Type_Common_Ref_Bits; + config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON; break; case AREF_GROUND: - config_bits |= - MSeries_AI_Config_Channel_Type_Ground_Ref_Bits; + config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND; break; case AREF_OTHER: break; } - config_bits |= MSeries_AI_Config_Channel_Bits(chan); - config_bits |= - MSeries_AI_Config_Bank_Bits(board->reg_type, chan); - config_bits |= MSeries_AI_Config_Gain_Bits(range_code); + config_bits |= NI_M_AI_CFG_CHAN_SEL(chan); + config_bits |= NI_M_AI_CFG_BANK_SEL(chan); + config_bits |= NI_M_AI_CFG_GAIN(range_code); if (i == n_chan - 1) - config_bits |= MSeries_AI_Config_Last_Channel_Bit; + config_bits |= NI_M_AI_CFG_LAST_CHAN; if (dither) - config_bits |= MSeries_AI_Config_Dither_Bit; + config_bits |= NI_M_AI_CFG_DITHER; /* don't use 2's complement encoding */ - config_bits |= MSeries_AI_Config_Polarity_Bit; - ni_writew(dev, config_bits, M_Offset_AI_Config_FIFO_Data); + config_bits |= NI_M_AI_CFG_POLARITY; + ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG); } ni_prime_channelgain_list(dev); } @@ -1986,7 +1835,7 @@ static void ni_load_channelgain_list(struct comedi_device *dev, devpriv->changain_state = 0; } - ni_stc_writew(dev, 1, Configuration_Memory_Clear); + ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG); /* Set up Calibration mode if required */ if (devpriv->is_6143) { @@ -1994,20 +1843,20 @@ static void ni_load_channelgain_list(struct comedi_device *dev, && !devpriv->ai_calib_source_enabled) { /* Strobe Relay enable bit */ ni_writew(dev, devpriv->ai_calib_source | - Calibration_Channel_6143_RelayOn, - Calibration_Channel_6143); + NI6143_CALIB_CHAN_RELAY_ON, + NI6143_CALIB_CHAN_REG); ni_writew(dev, devpriv->ai_calib_source, - Calibration_Channel_6143); + NI6143_CALIB_CHAN_REG); devpriv->ai_calib_source_enabled = 1; msleep_interruptible(100); /* Allow relays to change */ } else if (!(list[0] & CR_ALT_SOURCE) && devpriv->ai_calib_source_enabled) { /* Strobe Relay disable bit */ ni_writew(dev, devpriv->ai_calib_source | - Calibration_Channel_6143_RelayOff, - Calibration_Channel_6143); + NI6143_CALIB_CHAN_RELAY_OFF, + NI6143_CALIB_CHAN_REG); ni_writew(dev, devpriv->ai_calib_source, - Calibration_Channel_6143); + NI6143_CALIB_CHAN_REG); devpriv->ai_calib_source_enabled = 0; msleep_interruptible(100); /* Allow relays to change */ } @@ -2033,7 +1882,7 @@ static void ni_load_channelgain_list(struct comedi_device *dev, if ((list[i] & CR_ALT_SOURCE)) { if (devpriv->is_611x) ni_writew(dev, CR_CHAN(list[i]) & 0x0003, - Calibration_Channel_Select_611x); + NI611X_CALIB_CHAN_SEL_REG); } else { if (devpriv->is_611x) aref = AREF_DIFF; @@ -2041,30 +1890,31 @@ static void ni_load_channelgain_list(struct comedi_device *dev, aref = AREF_OTHER; switch (aref) { case AREF_DIFF: - hi |= AI_DIFFERENTIAL; + hi |= NI_E_AI_CFG_HI_TYPE_DIFF; break; case AREF_COMMON: - hi |= AI_COMMON; + hi |= NI_E_AI_CFG_HI_TYPE_COMMON; break; case AREF_GROUND: - hi |= AI_GROUND; + hi |= NI_E_AI_CFG_HI_TYPE_GROUND; break; case AREF_OTHER: break; } } - hi |= AI_CONFIG_CHANNEL(chan); + hi |= NI_E_AI_CFG_HI_CHAN(chan); - ni_writew(dev, hi, Configuration_Memory_High); + ni_writew(dev, hi, NI_E_AI_CFG_HI_REG); if (!devpriv->is_6143) { - lo = range; + lo = NI_E_AI_CFG_LO_GAIN(range); + if (i == n_chan - 1) - lo |= AI_LAST_CHANNEL; + lo |= NI_E_AI_CFG_LO_LAST_CHAN; if (dither) - lo |= AI_DITHER; + lo |= NI_E_AI_CFG_LO_DITHER; - ni_writew(dev, lo, Configuration_Memory_Low); + ni_writew(dev, lo, NI_E_AI_CFG_LO_REG); } } @@ -2092,25 +1942,27 @@ static int ni_ai_insn_read(struct comedi_device *dev, signbits = devpriv->ai_offset[0]; if (devpriv->is_611x) { for (n = 0; n < num_adc_stages_611x; n++) { - ni_stc_writew(dev, AI_CONVERT_Pulse, - AI_Command_1_Register); + ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, + NISTC_AI_CMD1_REG); udelay(1); } for (n = 0; n < insn->n; n++) { - ni_stc_writew(dev, AI_CONVERT_Pulse, - AI_Command_1_Register); + ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, + NISTC_AI_CMD1_REG); /* The 611x has screwy 32-bit FIFOs. */ d = 0; for (i = 0; i < NI_TIMEOUT; i++) { - if (ni_readb(dev, XXX_Status) & 0x80) { - d = ni_readl(dev, ADC_FIFO_Data_611x); + if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) { + d = ni_readl(dev, + NI611X_AI_FIFO_DATA_REG); d >>= 16; d &= 0xffff; break; } - if (!(ni_stc_readw(dev, AI_Status_1_Register) & - AI_FIFO_Empty_St)) { - d = ni_readl(dev, ADC_FIFO_Data_611x); + if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & + NISTC_AI_STATUS1_FIFO_E)) { + d = ni_readl(dev, + NI611X_AI_FIFO_DATA_REG); d &= 0xffff; break; } @@ -2124,17 +1976,19 @@ static int ni_ai_insn_read(struct comedi_device *dev, } } else if (devpriv->is_6143) { for (n = 0; n < insn->n; n++) { - ni_stc_writew(dev, AI_CONVERT_Pulse, - AI_Command_1_Register); + ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, + NISTC_AI_CMD1_REG); /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */ dl = 0; for (i = 0; i < NI_TIMEOUT; i++) { - if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) { + if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & + 0x01) { /* Get stranded sample into FIFO */ ni_writel(dev, 0x01, - AIFIFO_Control_6143); - dl = ni_readl(dev, AIFIFO_Data_6143); + NI6143_AI_FIFO_CTRL_REG); + dl = ni_readl(dev, + NI6143_AI_FIFO_DATA_REG); break; } } @@ -2146,11 +2000,11 @@ static int ni_ai_insn_read(struct comedi_device *dev, } } else { for (n = 0; n < insn->n; n++) { - ni_stc_writew(dev, AI_CONVERT_Pulse, - AI_Command_1_Register); + ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, + NISTC_AI_CMD1_REG); for (i = 0; i < NI_TIMEOUT; i++) { - if (!(ni_stc_readw(dev, AI_Status_1_Register) & - AI_FIFO_Empty_St)) + if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & + NISTC_AI_STATUS1_FIFO_E)) break; } if (i == NI_TIMEOUT) { @@ -2158,11 +2012,11 @@ static int ni_ai_insn_read(struct comedi_device *dev, return -ETIME; } if (devpriv->is_m_series) { - dl = ni_readl(dev, M_Offset_AI_FIFO_Data); + dl = ni_readl(dev, NI_M_AI_FIFO_DATA_REG); dl &= mask; data[n] = dl; } else { - d = ni_readw(dev, ADC_FIFO_Data_Register); + d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG); d += signbits; /* subtle: needs to be short addition */ data[n] = d; } @@ -2374,8 +2228,8 @@ static int ni_ai_inttrig(struct comedi_device *dev, if (trig_num != cmd->start_arg) return -EINVAL; - ni_stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2, - AI_Command_2_Register); + ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2, + NISTC_AI_CMD2_REG); s->async->inttrig = NULL; return 1; @@ -2391,6 +2245,7 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) int start_stop_select = 0; unsigned int stop_count; int interrupt_a_enable = 0; + unsigned ai_trig; if (dev->irq == 0) { dev_err(dev->class_dev, "cannot run command without an irq\n"); @@ -2401,51 +2256,47 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist); /* start configuration */ - ni_stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register); + ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG); /* disable analog triggering for now, since it * interferes with the use of pfi0 */ - devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable; - ni_stc_writew(dev, devpriv->an_trig_etc_reg, - Analog_Trigger_Etc_Register); + devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA; + ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG); + ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC; switch (cmd->start_src) { case TRIG_INT: case TRIG_NOW: - ni_stc_writew(dev, - AI_START2_Select(0) | - AI_START1_Sync | AI_START1_Edge | - AI_START1_Select(0), - AI_Trigger_Select_Register); + ai_trig |= NISTC_AI_TRIG_START1_EDGE | + NISTC_AI_TRIG_START1_SEL(0); break; case TRIG_EXT: - { - int chan = CR_CHAN(cmd->start_arg); - unsigned int bits = AI_START2_Select(0) | - AI_START1_Sync | AI_START1_Select(chan + 1); - - if (cmd->start_arg & CR_INVERT) - bits |= AI_START1_Polarity; - if (cmd->start_arg & CR_EDGE) - bits |= AI_START1_Edge; - ni_stc_writew(dev, bits, AI_Trigger_Select_Register); - break; - } + ai_trig |= NISTC_AI_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) + + 1); + + if (cmd->start_arg & CR_INVERT) + ai_trig |= NISTC_AI_TRIG_START1_POLARITY; + if (cmd->start_arg & CR_EDGE) + ai_trig |= NISTC_AI_TRIG_START1_EDGE; + break; } + ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG); - mode2 &= ~AI_Pre_Trigger; - mode2 &= ~AI_SC_Initial_Load_Source; - mode2 &= ~AI_SC_Reload_Mode; - ni_stc_writew(dev, mode2, AI_Mode_2_Register); + mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER; + mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC; + mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE; + ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG); if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) { - start_stop_select |= AI_STOP_Polarity; - start_stop_select |= AI_STOP_Select(31); /* logic low */ - start_stop_select |= AI_STOP_Sync; + /* logic low */ + start_stop_select |= NISTC_AI_STOP_POLARITY | + NISTC_AI_STOP_SEL(31) | + NISTC_AI_STOP_SYNC; } else { - start_stop_select |= AI_STOP_Select(19); /* ai configuration memory */ + /* ai configuration memory */ + start_stop_select |= NISTC_AI_STOP_SEL(19); } - ni_stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register); + ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG); devpriv->ai_cmd2 = 0; switch (cmd->stop_src) { @@ -2457,80 +2308,80 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) stop_count += num_adc_stages_611x; } /* stage number of scans */ - ni_stc_writel(dev, stop_count, AI_SC_Load_A_Registers); + ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG); - mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once; - ni_stc_writew(dev, mode1, AI_Mode_1_Register); + mode1 |= NISTC_AI_MODE1_START_STOP | + NISTC_AI_MODE1_RSVD | + NISTC_AI_MODE1_TRIGGER_ONCE; + ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG); /* load SC (Scan Count) */ - ni_stc_writew(dev, AI_SC_Load, AI_Command_1_Register); + ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG); if (stop_count == 0) { - devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan; - interrupt_a_enable |= AI_STOP_Interrupt_Enable; + devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS; + interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP; /* this is required to get the last sample for chanlist_len > 1, not sure why */ if (cmd->chanlist_len > 1) - start_stop_select |= - AI_STOP_Polarity | AI_STOP_Edge; + start_stop_select |= NISTC_AI_STOP_POLARITY | + NISTC_AI_STOP_EDGE; } break; case TRIG_NONE: /* stage number of scans */ - ni_stc_writel(dev, 0, AI_SC_Load_A_Registers); + ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG); - mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous; - ni_stc_writew(dev, mode1, AI_Mode_1_Register); + mode1 |= NISTC_AI_MODE1_START_STOP | + NISTC_AI_MODE1_RSVD | + NISTC_AI_MODE1_CONTINUOUS; + ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG); /* load SC (Scan Count) */ - ni_stc_writew(dev, AI_SC_Load, AI_Command_1_Register); + ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG); break; } switch (cmd->scan_begin_src) { case TRIG_TIMER: /* - stop bits for non 611x boards - AI_SI_Special_Trigger_Delay=0 - AI_Pre_Trigger=0 - AI_START_STOP_Select_Register: - AI_START_Polarity=0 (?) rising edge - AI_START_Edge=1 edge triggered - AI_START_Sync=1 (?) - AI_START_Select=0 SI_TC - AI_STOP_Polarity=0 rising edge - AI_STOP_Edge=0 level - AI_STOP_Sync=1 - AI_STOP_Select=19 external pin (configuration mem) + * stop bits for non 611x boards + * NISTC_AI_MODE3_SI_TRIG_DELAY=0 + * NISTC_AI_MODE2_PRE_TRIGGER=0 + * NISTC_AI_START_STOP_REG: + * NISTC_AI_START_POLARITY=0 (?) rising edge + * NISTC_AI_START_EDGE=1 edge triggered + * NISTC_AI_START_SYNC=1 (?) + * NISTC_AI_START_SEL=0 SI_TC + * NISTC_AI_STOP_POLARITY=0 rising edge + * NISTC_AI_STOP_EDGE=0 level + * NISTC_AI_STOP_SYNC=1 + * NISTC_AI_STOP_SEL=19 external pin (configuration mem) */ - start_stop_select |= AI_START_Edge | AI_START_Sync; - ni_stc_writew(dev, start_stop_select, - AI_START_STOP_Select_Register); + start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC; + ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG); - mode2 |= AI_SI_Reload_Mode(0); - /* AI_SI_Initial_Load_Source=A */ - mode2 &= ~AI_SI_Initial_Load_Source; - /* mode2 |= AI_SC_Reload_Mode; */ - ni_stc_writew(dev, mode2, AI_Mode_2_Register); + mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC; /* A */ + mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0); + /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */ + ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG); /* load SI */ timer = ni_ns_to_timer(dev, cmd->scan_begin_arg, CMDF_ROUND_NEAREST); - ni_stc_writel(dev, timer, AI_SI_Load_A_Registers); - ni_stc_writew(dev, AI_SI_Load, AI_Command_1_Register); + ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG); + ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG); break; case TRIG_EXT: if (cmd->scan_begin_arg & CR_EDGE) - start_stop_select |= AI_START_Edge; - /* AI_START_Polarity==1 is falling edge */ - if (cmd->scan_begin_arg & CR_INVERT) - start_stop_select |= AI_START_Polarity; + start_stop_select |= NISTC_AI_START_EDGE; + if (cmd->scan_begin_arg & CR_INVERT) /* falling edge */ + start_stop_select |= NISTC_AI_START_POLARITY; if (cmd->scan_begin_src != cmd->convert_src || (cmd->scan_begin_arg & ~CR_EDGE) != (cmd->convert_arg & ~CR_EDGE)) - start_stop_select |= AI_START_Sync; + start_stop_select |= NISTC_AI_START_SYNC; start_stop_select |= - AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg)); - ni_stc_writew(dev, start_stop_select, - AI_START_STOP_Select_Register); + NISTC_AI_START_SEL(1 + CR_CHAN(cmd->scan_begin_arg)); + ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG); break; } @@ -2543,46 +2394,43 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) timer = ni_ns_to_timer(dev, cmd->convert_arg, CMDF_ROUND_NEAREST); /* 0,0 does not work */ - ni_stc_writew(dev, 1, AI_SI2_Load_A_Register); - ni_stc_writew(dev, timer, AI_SI2_Load_B_Register); + ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG); + ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG); - /* AI_SI2_Reload_Mode = alternate */ - /* AI_SI2_Initial_Load_Source = A */ - mode2 &= ~AI_SI2_Initial_Load_Source; - mode2 |= AI_SI2_Reload_Mode; - ni_stc_writew(dev, mode2, AI_Mode_2_Register); + mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* A */ + mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */ + ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG); - /* AI_SI2_Load */ - ni_stc_writew(dev, AI_SI2_Load, AI_Command_1_Register); + ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG); - mode2 |= AI_SI2_Reload_Mode; /* alternate */ - mode2 |= AI_SI2_Initial_Load_Source; /* B */ - - ni_stc_writew(dev, mode2, AI_Mode_2_Register); + mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* B */ + mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */ + ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG); break; case TRIG_EXT: - mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg); + mode1 |= NISTC_AI_MODE1_CONVERT_SRC(1 + cmd->convert_arg); if ((cmd->convert_arg & CR_INVERT) == 0) - mode1 |= AI_CONVERT_Source_Polarity; - ni_stc_writew(dev, mode1, AI_Mode_1_Register); + mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY; + ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG); - mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable; - ni_stc_writew(dev, mode2, AI_Mode_2_Register); + mode2 |= NISTC_AI_MODE2_SC_GATE_ENA | + NISTC_AI_MODE2_START_STOP_GATE_ENA; + ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG); break; } if (dev->irq) { /* interrupt on FIFO, errors, SC_TC */ - interrupt_a_enable |= AI_Error_Interrupt_Enable | - AI_SC_TC_Interrupt_Enable; + interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR | + NISTC_INTA_ENA_AI_SC_TC; #ifndef PCIDMA - interrupt_a_enable |= AI_FIFO_Interrupt_Enable; + interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO; #endif - if (cmd->flags & CMDF_WAKE_EOS - || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) { + if ((cmd->flags & CMDF_WAKE_EOS) || + (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) { /* wake on end-of-scan */ devpriv->aimode = AIMODE_SCAN; } else { @@ -2593,66 +2441,60 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) case AIMODE_HALF_FULL: /*generate FIFO interrupts and DMA requests on half-full */ #ifdef PCIDMA - ni_stc_writew(dev, AI_FIFO_Mode_HF_to_E, - AI_Mode_3_Register); + ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E, + NISTC_AI_MODE3_REG); #else - ni_stc_writew(dev, AI_FIFO_Mode_HF, - AI_Mode_3_Register); + ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF, + NISTC_AI_MODE3_REG); #endif break; case AIMODE_SAMPLE: /*generate FIFO interrupts on non-empty */ - ni_stc_writew(dev, AI_FIFO_Mode_NE, - AI_Mode_3_Register); + ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE, + NISTC_AI_MODE3_REG); break; case AIMODE_SCAN: #ifdef PCIDMA - ni_stc_writew(dev, AI_FIFO_Mode_NE, - AI_Mode_3_Register); + ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE, + NISTC_AI_MODE3_REG); #else - ni_stc_writew(dev, AI_FIFO_Mode_HF, - AI_Mode_3_Register); + ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF, + NISTC_AI_MODE3_REG); #endif - interrupt_a_enable |= AI_STOP_Interrupt_Enable; + interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP; break; default: break; } /* clear interrupts */ - ni_stc_writew(dev, - AI_Error_Interrupt_Ack | - AI_STOP_Interrupt_Ack | - AI_START_Interrupt_Ack | - AI_START2_Interrupt_Ack | - AI_START1_Interrupt_Ack | - AI_SC_TC_Interrupt_Ack | - AI_SC_TC_Error_Confirm, - Interrupt_A_Ack_Register); - - ni_set_bits(dev, Interrupt_A_Enable_Register, - interrupt_a_enable, 1); + ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG); + + ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1); } else { /* interrupt on nothing */ - ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0); + ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0); /* XXX start polling if necessary */ } /* end configuration */ - ni_stc_writew(dev, AI_Configuration_End, Joint_Reset_Register); + ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG); switch (cmd->scan_begin_src) { case TRIG_TIMER: - ni_stc_writew(dev, - AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm, - AI_Command_1_Register); + ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM | + NISTC_AI_CMD1_SI_ARM | + NISTC_AI_CMD1_DIV_ARM | + NISTC_AI_CMD1_SC_ARM, + NISTC_AI_CMD1_REG); break; case TRIG_EXT: - /* XXX AI_SI_Arm? */ - ni_stc_writew(dev, - AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm, - AI_Command_1_Register); + ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM | + NISTC_AI_CMD1_SI_ARM | /* XXX ? */ + NISTC_AI_CMD1_DIV_ARM | + NISTC_AI_CMD1_SC_ARM, + NISTC_AI_CMD1_REG); break; } @@ -2666,9 +2508,9 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) #endif if (cmd->start_src == TRIG_NOW) { - /* AI_START1_Pulse */ - ni_stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2, - AI_Command_2_Register); + ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | + devpriv->ai_cmd2, + NISTC_AI_CMD2_REG); s->async->inttrig = NULL; } else if (cmd->start_src == TRIG_EXT) { s->async->inttrig = NULL; @@ -2691,12 +2533,8 @@ static int ni_ai_insn_config(struct comedi_device *dev, switch (data[0]) { case INSN_CONFIG_ALT_SOURCE: if (devpriv->is_m_series) { - if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask | - MSeries_AI_Bypass_Cal_Sel_Neg_Mask | - MSeries_AI_Bypass_Mode_Mux_Mask | - MSeries_AO_Bypass_AO_Cal_Sel_Mask)) { + if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK) return -EINVAL; - } devpriv->ai_calib_source = data[1]; } else if (devpriv->is_6143) { unsigned int calib_source; @@ -2704,7 +2542,7 @@ static int ni_ai_insn_config(struct comedi_device *dev, calib_source = data[1] & 0xf; devpriv->ai_calib_source = calib_source; - ni_writew(dev, calib_source, Calibration_Channel_6143); + ni_writew(dev, calib_source, NI6143_CALIB_CHAN_REG); } else { unsigned int calib_source; unsigned int calib_source_adjust; @@ -2717,7 +2555,7 @@ static int ni_ai_insn_config(struct comedi_device *dev, devpriv->ai_calib_source = calib_source; if (devpriv->is_611x) { ni_writeb(dev, calib_source_adjust, - Cal_Gain_Select_611x); + NI611X_CAL_GAIN_SEL_REG); } } return 2; @@ -2771,10 +2609,10 @@ static int ni_m_series_ao_config_chanlist(struct comedi_device *dev, if (timed) { for (i = 0; i < s->n_chan; ++i) { - devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit; + devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED; ni_writeb(dev, devpriv->ao_conf[i], - M_Offset_AO_Config_Bank(i)); - ni_writeb(dev, 0xf, M_Offset_AO_Waveform_Order(i)); + NI_M_AO_CFG_BANK_REG(i)); + ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i)); } } for (i = 0; i < n_chans; i++) { @@ -2787,24 +2625,22 @@ static int ni_m_series_ao_config_chanlist(struct comedi_device *dev, conf = 0; switch (krange->max - krange->min) { case 20000000: - conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits; - ni_writeb(dev, 0, - M_Offset_AO_Reference_Attenuation(chan)); + conf |= NI_M_AO_CFG_BANK_REF_INT_10V; + ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan)); break; case 10000000: - conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits; - ni_writeb(dev, 0, - M_Offset_AO_Reference_Attenuation(chan)); + conf |= NI_M_AO_CFG_BANK_REF_INT_5V; + ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan)); break; case 4000000: - conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits; - ni_writeb(dev, MSeries_Attenuate_x5_Bit, - M_Offset_AO_Reference_Attenuation(chan)); + conf |= NI_M_AO_CFG_BANK_REF_INT_10V; + ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5, + NI_M_AO_REF_ATTENUATION_REG(chan)); break; case 2000000: - conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits; - ni_writeb(dev, MSeries_Attenuate_x5_Bit, - M_Offset_AO_Reference_Attenuation(chan)); + conf |= NI_M_AO_CFG_BANK_REF_INT_5V; + ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5, + NI_M_AO_REF_ATTENUATION_REG(chan)); break; default: dev_err(dev->class_dev, @@ -2813,10 +2649,10 @@ static int ni_m_series_ao_config_chanlist(struct comedi_device *dev, } switch (krange->max + krange->min) { case 0: - conf |= MSeries_AO_DAC_Offset_0V_Bits; + conf |= NI_M_AO_CFG_BANK_OFFSET_0V; break; case 10000000: - conf |= MSeries_AO_DAC_Offset_5V_Bits; + conf |= NI_M_AO_CFG_BANK_OFFSET_5V; break; default: dev_err(dev->class_dev, @@ -2824,10 +2660,10 @@ static int ni_m_series_ao_config_chanlist(struct comedi_device *dev, break; } if (timed) - conf |= MSeries_AO_Update_Timed_Bit; - ni_writeb(dev, conf, M_Offset_AO_Config_Bank(chan)); + conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED; + ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan)); devpriv->ao_conf[chan] = conf; - ni_writeb(dev, i, M_Offset_AO_Waveform_Order(chan)); + ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan)); } return invert; } @@ -2847,27 +2683,27 @@ static int ni_old_ao_config_chanlist(struct comedi_device *dev, for (i = 0; i < n_chans; i++) { chan = CR_CHAN(chanspec[i]); range = CR_RANGE(chanspec[i]); - conf = AO_Channel(chan); + conf = NI_E_AO_DACSEL(chan); if (comedi_range_is_bipolar(s, range)) { - conf |= AO_Bipolar; + conf |= NI_E_AO_CFG_BIP; invert = (s->maxdata + 1) >> 1; } else { invert = 0; } if (comedi_range_is_external(s, range)) - conf |= AO_Ext_Ref; + conf |= NI_E_AO_EXT_REF; /* not all boards can deglitch, but this shouldn't hurt */ if (chanspec[i] & CR_DEGLITCH) - conf |= AO_Deglitch; + conf |= NI_E_AO_DEGLITCH; /* analog reference */ /* AREF_OTHER connects AO ground to AI ground, i think */ - conf |= (CR_AREF(chanspec[i]) == - AREF_OTHER) ? AO_Ground_Ref : 0; + if (CR_AREF(chanspec[i]) == AREF_OTHER) + conf |= NI_E_AO_GROUND_REF; - ni_writew(dev, conf, AO_Configuration); + ni_writew(dev, conf, NI_E_AO_CFG_REG); devpriv->ao_conf[chan] = conf; } return invert; @@ -2899,13 +2735,13 @@ static int ni_ao_insn_write(struct comedi_device *dev, int i; if (devpriv->is_6xxx) { - ni_ao_win_outw(dev, 1 << chan, AO_Immediate_671x); + ni_ao_win_outw(dev, 1 << chan, NI671X_AO_IMMEDIATE_REG); - reg = DACx_Direct_Data_671x(chan); + reg = NI671X_DAC_DIRECT_DATA_REG(chan); } else if (devpriv->is_m_series) { - reg = M_Offset_DAC_Direct_Data(chan); + reg = NI_M_DAC_DIRECT_DATA_REG(chan); } else { - reg = (chan) ? DAC1_Direct_Data : DAC0_Direct_Data; + reg = NI_E_DAC_DIRECT_DATA_REG(chan); } ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0); @@ -2995,13 +2831,13 @@ static int ni_ao_inttrig(struct comedi_device *dev, multiple times) */ s->async->inttrig = NULL; - ni_set_bits(dev, Interrupt_B_Enable_Register, - AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0); - interrupt_b_bits = AO_Error_Interrupt_Enable; + ni_set_bits(dev, NISTC_INTB_ENA_REG, + NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0); + interrupt_b_bits = NISTC_INTB_ENA_AO_ERR; #ifdef PCIDMA - ni_stc_writew(dev, 1, DAC_FIFO_Clear); + ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG); if (devpriv->is_6xxx) - ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x); + ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG); ret = ni_ao_setup_MITE_dma(dev); if (ret) return ret; @@ -3013,17 +2849,17 @@ static int ni_ao_inttrig(struct comedi_device *dev, if (ret == 0) return -EPIPE; - interrupt_b_bits |= AO_FIFO_Interrupt_Enable; + interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO; #endif - ni_stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE, - AO_Mode_3_Register); - ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); + ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE, + NISTC_AO_MODE3_REG); + ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG); /* wait for DACs to be loaded */ for (i = 0; i < timeout; i++) { udelay(1); - if ((ni_stc_readw(dev, Joint_Status_2_Register) & - AO_TMRDACWRs_In_Progress_St) == 0) + if ((ni_stc_readw(dev, NISTC_STATUS2_REG) & + NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS) == 0) break; } if (i == timeout) { @@ -3035,17 +2871,20 @@ static int ni_ao_inttrig(struct comedi_device *dev, * stc manual says we are need to clear error interrupt after * AO_TMRDACWRs_In_Progress_St clears */ - ni_stc_writew(dev, AO_Error_Interrupt_Ack, Interrupt_B_Ack_Register); + ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG); - ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1); + ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1); - ni_stc_writew(dev, devpriv->ao_cmd1 | - AO_UI_Arm | AO_UC_Arm | AO_BC_Arm | - AO_DAC1_Update_Mode | AO_DAC0_Update_Mode, - AO_Command_1_Register); + ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM | + NISTC_AO_CMD1_UC_ARM | + NISTC_AO_CMD1_BC_ARM | + NISTC_AO_CMD1_DAC1_UPDATE_MODE | + NISTC_AO_CMD1_DAC0_UPDATE_MODE | + devpriv->ao_cmd1, + NISTC_AO_CMD1_REG); - ni_stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse, - AO_Command_2_Register); + ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2, + NISTC_AO_CMD2_REG); return 0; } @@ -3058,18 +2897,20 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) int bits; int i; unsigned trigvar; + unsigned val; if (dev->irq == 0) { dev_err(dev->class_dev, "cannot run command without an irq\n"); return -EIO; } - ni_stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register); + ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG); - ni_stc_writew(dev, AO_Disarm, AO_Command_1_Register); + ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG); if (devpriv->is_6xxx) { - ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x); + ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG, + NI611X_AO_MISC_REG); bits = 0; for (i = 0; i < cmd->chanlist_len; i++) { @@ -3077,172 +2918,186 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) chan = CR_CHAN(cmd->chanlist[i]); bits |= 1 << chan; - ni_ao_win_outw(dev, chan, AO_Waveform_Generation_611x); + ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG); } - ni_ao_win_outw(dev, bits, AO_Timed_611x); + ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG); } ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1); if (cmd->stop_src == TRIG_NONE) { - devpriv->ao_mode1 |= AO_Continuous; - devpriv->ao_mode1 &= ~AO_Trigger_Once; + devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS; + devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE; } else { - devpriv->ao_mode1 &= ~AO_Continuous; - devpriv->ao_mode1 |= AO_Trigger_Once; + devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS; + devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE; } - ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); + ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); + + val = devpriv->ao_trigger_select; switch (cmd->start_src) { case TRIG_INT: case TRIG_NOW: - devpriv->ao_trigger_select &= - ~(AO_START1_Polarity | AO_START1_Select(-1)); - devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync; - ni_stc_writew(dev, devpriv->ao_trigger_select, - AO_Trigger_Select_Register); + val &= ~(NISTC_AO_TRIG_START1_POLARITY | + NISTC_AO_TRIG_START1_SEL_MASK); + val |= NISTC_AO_TRIG_START1_EDGE | + NISTC_AO_TRIG_START1_SYNC; break; case TRIG_EXT: - devpriv->ao_trigger_select = - AO_START1_Select(CR_CHAN(cmd->start_arg) + 1); - if (cmd->start_arg & CR_INVERT) - devpriv->ao_trigger_select |= AO_START1_Polarity; /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */ - if (cmd->start_arg & CR_EDGE) - devpriv->ao_trigger_select |= AO_START1_Edge; /* 0=edge detection disabled, 1=enabled */ + val = NISTC_AO_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) + 1); + if (cmd->start_arg & CR_INVERT) { + /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */ + val |= NISTC_AO_TRIG_START1_POLARITY; + } + if (cmd->start_arg & CR_EDGE) { + /* 0=edge detection disabled, 1=enabled */ + val |= NISTC_AO_TRIG_START1_EDGE; + } ni_stc_writew(dev, devpriv->ao_trigger_select, - AO_Trigger_Select_Register); + NISTC_AO_TRIG_SEL_REG); break; default: BUG(); break; } - devpriv->ao_mode3 &= ~AO_Trigger_Length; - ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); + devpriv->ao_trigger_select = val; + ni_stc_writew(dev, devpriv->ao_trigger_select, NISTC_AO_TRIG_SEL_REG); + + devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN; + ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG); - ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); - devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source; - ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); + ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); + devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC; + ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG); if (cmd->stop_src == TRIG_NONE) - ni_stc_writel(dev, 0xffffff, AO_BC_Load_A_Register); + ni_stc_writel(dev, 0xffffff, NISTC_AO_BC_LOADA_REG); else - ni_stc_writel(dev, 0, AO_BC_Load_A_Register); - ni_stc_writew(dev, AO_BC_Load, AO_Command_1_Register); - devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source; - ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); + ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG); + ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG); + devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC; + ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG); switch (cmd->stop_src) { case TRIG_COUNT: if (devpriv->is_m_series) { /* this is how the NI example code does it for m-series boards, verified correct with 6259 */ ni_stc_writel(dev, cmd->stop_arg - 1, - AO_UC_Load_A_Register); - ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register); + NISTC_AO_UC_LOADA_REG); + ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, + NISTC_AO_CMD1_REG); } else { ni_stc_writel(dev, cmd->stop_arg, - AO_UC_Load_A_Register); - ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register); + NISTC_AO_UC_LOADA_REG); + ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, + NISTC_AO_CMD1_REG); ni_stc_writel(dev, cmd->stop_arg - 1, - AO_UC_Load_A_Register); + NISTC_AO_UC_LOADA_REG); } break; case TRIG_NONE: - ni_stc_writel(dev, 0xffffff, AO_UC_Load_A_Register); - ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register); - ni_stc_writel(dev, 0xffffff, AO_UC_Load_A_Register); + ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG); + ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG); + ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG); break; default: - ni_stc_writel(dev, 0, AO_UC_Load_A_Register); - ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register); - ni_stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register); + ni_stc_writel(dev, 0, NISTC_AO_UC_LOADA_REG); + ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG); + ni_stc_writel(dev, cmd->stop_arg, NISTC_AO_UC_LOADA_REG); } - devpriv->ao_mode1 &= - ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity | - AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity); + devpriv->ao_mode1 &= ~(NISTC_AO_MODE1_UPDATE_SRC_MASK | + NISTC_AO_MODE1_UI_SRC_MASK | + NISTC_AO_MODE1_UPDATE_SRC_POLARITY | + NISTC_AO_MODE1_UI_SRC_POLARITY); switch (cmd->scan_begin_src) { case TRIG_TIMER: - devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable; + devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA; trigvar = ni_ns_to_timer(dev, cmd->scan_begin_arg, CMDF_ROUND_NEAREST); - ni_stc_writel(dev, 1, AO_UI_Load_A_Register); - ni_stc_writew(dev, AO_UI_Load, AO_Command_1_Register); - ni_stc_writel(dev, trigvar, AO_UI_Load_A_Register); + ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG); + ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG); + ni_stc_writel(dev, trigvar, NISTC_AO_UI_LOADA_REG); break; case TRIG_EXT: devpriv->ao_mode1 |= - AO_UPDATE_Source_Select(cmd->scan_begin_arg); + NISTC_AO_MODE1_UPDATE_SRC(cmd->scan_begin_arg); if (cmd->scan_begin_arg & CR_INVERT) - devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity; - devpriv->ao_cmd2 |= AO_BC_Gate_Enable; + devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY; + devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA; break; default: BUG(); break; } - ni_stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register); - ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); - devpriv->ao_mode2 &= - ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source); - ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); + ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG); + ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); + devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) | + NISTC_AO_MODE2_UI_INIT_LOAD_SRC); + ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG); if (cmd->scan_end_arg > 1) { - devpriv->ao_mode1 |= AO_Multiple_Channels; + devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN; ni_stc_writew(dev, - AO_Number_Of_Channels(cmd->scan_end_arg - 1) | - AO_UPDATE_Output_Select(AO_Update_Output_High_Z), - AO_Output_Control_Register); + NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1) | + NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ, + NISTC_AO_OUT_CTRL_REG); } else { unsigned bits; - devpriv->ao_mode1 &= ~AO_Multiple_Channels; - bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z); + devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN; + bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ; if (devpriv->is_m_series || devpriv->is_6xxx) { - bits |= AO_Number_Of_Channels(0); + bits |= NISTC_AO_OUT_CTRL_CHANS(0); } else { bits |= - AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0])); + NISTC_AO_OUT_CTRL_CHANS(CR_CHAN(cmd->chanlist[0])); } - ni_stc_writew(dev, bits, AO_Output_Control_Register); + ni_stc_writew(dev, bits, NISTC_AO_OUT_CTRL_REG); } - ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); + ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); - ni_stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode, - AO_Command_1_Register); + ni_stc_writew(dev, NISTC_AO_CMD1_DAC1_UPDATE_MODE | + NISTC_AO_CMD1_DAC0_UPDATE_MODE, + NISTC_AO_CMD1_REG); - devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error; - ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); + devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR; + ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG); - devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask; + devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK; #ifdef PCIDMA - devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F; + devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F; #else - devpriv->ao_mode2 |= AO_FIFO_Mode_HF; + devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF; #endif - devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable; - ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); + devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA; + ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG); - bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width | - AO_TMRDACWR_Pulse_Width; + bits = NISTC_AO_PERSONAL_BC_SRC_SEL | + NISTC_AO_PERSONAL_UPDATE_PW | + NISTC_AO_PERSONAL_TMRDACWR_PW; if (board->ao_fifo_depth) - bits |= AO_FIFO_Enable; + bits |= NISTC_AO_PERSONAL_FIFO_ENA; else - bits |= AO_DMA_PIO_Control; + bits |= NISTC_AO_PERSONAL_DMA_PIO_CTRL; #if 0 - /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281, - verified with bus analyzer. */ + /* + * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit + * for 6281, verified with bus analyzer. + */ if (devpriv->is_m_series) - bits |= AO_Number_Of_DAC_Packages; + bits |= NISTC_AO_PERSONAL_NUM_DAC; #endif - ni_stc_writew(dev, bits, AO_Personal_Register); + ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG); /* enable sending of ao dma requests */ - ni_stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register); + ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG); - ni_stc_writew(dev, AO_Configuration_End, Joint_Reset_Register); + ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG); if (cmd->stop_src == TRIG_COUNT) { - ni_stc_writew(dev, AO_BC_TC_Interrupt_Ack, - Interrupt_B_Ack_Register); - ni_set_bits(dev, Interrupt_B_Enable_Register, - AO_BC_TC_Interrupt_Enable, 1); + ni_stc_writew(dev, NISTC_INTB_ACK_AO_BC_TC, + NISTC_INTB_ACK_REG); + ni_set_bits(dev, NISTC_INTB_ENA_REG, + NISTC_INTB_ENA_AO_BC_TC, 1); } s->async->inttrig = ni_ao_inttrig; @@ -3339,41 +3194,44 @@ static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s) ni_release_ao_mite_channel(dev); - ni_stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register); - ni_stc_writew(dev, AO_Disarm, AO_Command_1_Register); - ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0); - ni_stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register); - ni_stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register); - ni_stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width | - AO_TMRDACWR_Pulse_Width, AO_Personal_Register); - ni_stc_writew(dev, 0, AO_Output_Control_Register); - ni_stc_writew(dev, 0, AO_Start_Select_Register); + ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG); + ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG); + ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0); + ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG); + ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG); + ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL | + NISTC_AO_PERSONAL_UPDATE_PW | + NISTC_AO_PERSONAL_TMRDACWR_PW, + NISTC_AO_PERSONAL_REG); + ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG); + ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG); devpriv->ao_cmd1 = 0; - ni_stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register); + ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG); devpriv->ao_cmd2 = 0; - ni_stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register); + ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG); devpriv->ao_mode1 = 0; - ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); + ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); devpriv->ao_mode2 = 0; - ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); + ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG); if (devpriv->is_m_series) - devpriv->ao_mode3 = AO_Last_Gate_Disable; + devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE; else devpriv->ao_mode3 = 0; - ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); + ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG); devpriv->ao_trigger_select = 0; ni_stc_writew(dev, devpriv->ao_trigger_select, - AO_Trigger_Select_Register); + NISTC_AO_TRIG_SEL_REG); if (devpriv->is_6xxx) { unsigned immediate_bits = 0; unsigned i; for (i = 0; i < s->n_chan; ++i) immediate_bits |= 1 << i; - ni_ao_win_outw(dev, immediate_bits, AO_Immediate_671x); - ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x); + ni_ao_win_outw(dev, immediate_bits, NI671X_AO_IMMEDIATE_REG); + ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG, + NI611X_AO_MISC_REG); } - ni_stc_writew(dev, AO_Configuration_End, Joint_Reset_Register); + ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG); return 0; } @@ -3392,9 +3250,9 @@ static int ni_dio_insn_config(struct comedi_device *dev, if (ret) return ret; - devpriv->dio_control &= ~DIO_Pins_Dir_Mask; - devpriv->dio_control |= DIO_Pins_Dir(s->io_bits); - ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register); + devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK; + devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits); + ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); return insn->n; } @@ -3407,16 +3265,17 @@ static int ni_dio_insn_bits(struct comedi_device *dev, struct ni_private *devpriv = dev->private; /* Make sure we're not using the serial part of the dio */ - if ((data[0] & (DIO_SDIN | DIO_SDOUT)) && devpriv->serial_interval_ns) + if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) && + devpriv->serial_interval_ns) return -EBUSY; if (comedi_dio_update_state(s, data)) { - devpriv->dio_output &= ~DIO_Parallel_Data_Mask; - devpriv->dio_output |= DIO_Parallel_Data_Out(s->state); - ni_stc_writew(dev, devpriv->dio_output, DIO_Output_Register); + devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK; + devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state); + ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG); } - data[1] = ni_stc_readw(dev, DIO_Parallel_Input_Register); + data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG); return insn->n; } @@ -3432,7 +3291,7 @@ static int ni_m_series_dio_insn_config(struct comedi_device *dev, if (ret) return ret; - ni_writel(dev, s->io_bits, M_Offset_DIO_Direction); + ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG); return insn->n; } @@ -3443,9 +3302,9 @@ static int ni_m_series_dio_insn_bits(struct comedi_device *dev, unsigned int *data) { if (comedi_dio_update_state(s, data)) - ni_writel(dev, s->state, M_Offset_Static_Digital_Output); + ni_writel(dev, s->state, NI_M_DIO_REG); - data[1] = ni_readl(dev, M_Offset_Static_Digital_Input); + data[1] = ni_readl(dev, NI_M_DIO_REG); return insn->n; } @@ -3491,7 +3350,7 @@ static int ni_cdio_cmdtest(struct comedi_device *dev, err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); tmp = cmd->scan_begin_arg; - tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT); + tmp &= CR_PACK_FLAGS(NI_M_CDO_MODE_SAMPLE_SRC_MASK, 0, 0, CR_INVERT); if (tmp != cmd->scan_begin_arg) err |= -EINVAL; @@ -3550,13 +3409,14 @@ static int ni_cdo_inttrig(struct comedi_device *dev, if (retval < 0) return retval; #endif -/* -* XXX not sure what interrupt C group does -* ni_writeb(dev, Interrupt_Group_C_Enable_Bit, -* M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo -*/ + /* + * XXX not sure what interrupt C group does + * wait for dma to fill output fifo + * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG); + */ for (i = 0; i < timeout; ++i) { - if (ni_readl(dev, M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit) + if (ni_readl(dev, NI_M_CDIO_STATUS_REG) & + NI_M_CDIO_STATUS_CDO_FIFO_FULL) break; udelay(10); } @@ -3565,36 +3425,30 @@ static int ni_cdo_inttrig(struct comedi_device *dev, s->cancel(dev, s); return -EIO; } - ni_writel(dev, CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit | - CDO_Empty_FIFO_Interrupt_Enable_Set_Bit, - M_Offset_CDIO_Command); + ni_writel(dev, NI_M_CDO_CMD_ARM | + NI_M_CDO_CMD_ERR_INT_ENA_SET | + NI_M_CDO_CMD_F_E_INT_ENA_SET, + NI_M_CDIO_CMD_REG); return retval; } static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s) { const struct comedi_cmd *cmd = &s->async->cmd; - unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit; + unsigned cdo_mode_bits; int retval; - ni_writel(dev, CDO_Reset_Bit, M_Offset_CDIO_Command); - switch (cmd->scan_begin_src) { - case TRIG_EXT: - cdo_mode_bits |= - CR_CHAN(cmd->scan_begin_arg) & - CDO_Sample_Source_Select_Mask; - break; - default: - BUG(); - break; - } + ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG); + cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE | + NI_M_CDO_MODE_HALT_ON_ERROR | + NI_M_CDO_MODE_SAMPLE_SRC(CR_CHAN(cmd->scan_begin_arg)); if (cmd->scan_begin_arg & CR_INVERT) - cdo_mode_bits |= CDO_Polarity_Bit; - ni_writel(dev, cdo_mode_bits, M_Offset_CDO_Mode); + cdo_mode_bits |= NI_M_CDO_MODE_POLARITY; + ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG); if (s->io_bits) { - ni_writel(dev, s->state, M_Offset_CDO_FIFO_Data); - ni_writel(dev, CDO_SW_Update_Bit, M_Offset_CDIO_Command); - ni_writel(dev, s->io_bits, M_Offset_CDO_Mask_Enable); + ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG); + ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG); + ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG); } else { dev_err(dev->class_dev, "attempted to run digital output command with no lines configured as outputs\n"); @@ -3611,15 +3465,16 @@ static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s) static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s) { - ni_writel(dev, CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit | - CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit | - CDO_FIFO_Request_Interrupt_Enable_Clear_Bit, - M_Offset_CDIO_Command); -/* -* XXX not sure what interrupt C group does ni_writeb(dev, 0, -* M_Offset_Interrupt_C_Enable); -*/ - ni_writel(dev, 0, M_Offset_CDO_Mask_Enable); + ni_writel(dev, NI_M_CDO_CMD_DISARM | + NI_M_CDO_CMD_ERR_INT_ENA_CLR | + NI_M_CDO_CMD_F_E_INT_ENA_CLR | + NI_M_CDO_CMD_F_REQ_INT_ENA_CLR, + NI_M_CDIO_CMD_REG); + /* + * XXX not sure what interrupt C group does + * ni_writeb(dev, 0, NI_M_INTC_ENA_REG); + */ + ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG); ni_release_cdo_mite_channel(dev); return 0; } @@ -3650,16 +3505,16 @@ static void handle_cdio_interrupt(struct comedi_device *dev) spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); #endif - cdio_status = ni_readl(dev, M_Offset_CDIO_Status); - if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) { + cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG); + if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) { /* XXX just guessing this is needed and does something useful */ - ni_writel(dev, CDO_Error_Interrupt_Confirm_Bit, - M_Offset_CDIO_Command); + ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM, + NI_M_CDIO_CMD_REG); s->async->events |= COMEDI_CB_OVERFLOW; } - if (cdio_status & CDO_FIFO_Empty_Bit) { - ni_writel(dev, CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit, - M_Offset_CDIO_Command); + if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) { + ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR, + NI_M_CDIO_CMD_REG); /* s->async->events |= COMEDI_CB_EOA; */ } comedi_handle_events(dev, s); @@ -3674,23 +3529,23 @@ static int ni_serial_hw_readwrite8(struct comedi_device *dev, unsigned int status1; int err = 0, count = 20; - devpriv->dio_output &= ~DIO_Serial_Data_Mask; - devpriv->dio_output |= DIO_Serial_Data_Out(data_out); - ni_stc_writew(dev, devpriv->dio_output, DIO_Output_Register); + devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK; + devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out); + ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG); - status1 = ni_stc_readw(dev, Joint_Status_1_Register); - if (status1 & DIO_Serial_IO_In_Progress_St) { + status1 = ni_stc_readw(dev, NISTC_STATUS1_REG); + if (status1 & NISTC_STATUS1_SERIO_IN_PROG) { err = -EBUSY; goto Error; } - devpriv->dio_control |= DIO_HW_Serial_Start; - ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register); - devpriv->dio_control &= ~DIO_HW_Serial_Start; + devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START; + ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); + devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START; /* Wait until STC says we're done, but don't loop infinitely. */ - while ((status1 = ni_stc_readw(dev, Joint_Status_1_Register)) & - DIO_Serial_IO_In_Progress_St) { + while ((status1 = ni_stc_readw(dev, NISTC_STATUS1_REG)) & + NISTC_STATUS1_SERIO_IN_PROG) { /* Delay one bit per loop */ udelay((devpriv->serial_interval_ns + 999) / 1000); if (--count < 0) { @@ -3701,15 +3556,17 @@ static int ni_serial_hw_readwrite8(struct comedi_device *dev, } } - /* Delay for last bit. This delay is absolutely necessary, because - DIO_Serial_IO_In_Progress_St goes high one bit too early. */ + /* + * Delay for last bit. This delay is absolutely necessary, because + * NISTC_STATUS1_SERIO_IN_PROG goes high one bit too early. + */ udelay((devpriv->serial_interval_ns + 999) / 1000); if (data_in) - *data_in = ni_stc_readw(dev, DIO_Serial_Input_Register); + *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG); Error: - ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register); + ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); return err; } @@ -3729,25 +3586,25 @@ static int ni_serial_sw_readwrite8(struct comedi_device *dev, /* Output current bit; note that we cannot touch s->state because it is a per-subdevice field, and serial is a separate subdevice from DIO. */ - devpriv->dio_output &= ~DIO_SDOUT; + devpriv->dio_output &= ~NISTC_DIO_SDOUT; if (data_out & mask) - devpriv->dio_output |= DIO_SDOUT; - ni_stc_writew(dev, devpriv->dio_output, DIO_Output_Register); + devpriv->dio_output |= NISTC_DIO_SDOUT; + ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG); /* Assert SDCLK (active low, inverted), wait for half of the delay, deassert SDCLK, and wait for the other half. */ - devpriv->dio_control |= DIO_Software_Serial_Control; - ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register); + devpriv->dio_control |= NISTC_DIO_SDCLK; + ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); udelay((devpriv->serial_interval_ns + 999) / 2000); - devpriv->dio_control &= ~DIO_Software_Serial_Control; - ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register); + devpriv->dio_control &= ~NISTC_DIO_SDCLK; + ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); udelay((devpriv->serial_interval_ns + 999) / 2000); /* Input current bit */ - if (ni_stc_readw(dev, DIO_Parallel_Input_Register) & DIO_SDIN) + if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN) input |= mask; } @@ -3763,6 +3620,7 @@ static int ni_serial_insn_config(struct comedi_device *dev, unsigned int *data) { struct ni_private *devpriv = dev->private; + unsigned clk_fout = devpriv->clock_and_fout; int err = insn->n; unsigned char byte_out, byte_in = 0; @@ -3772,49 +3630,49 @@ static int ni_serial_insn_config(struct comedi_device *dev, switch (data[0]) { case INSN_CONFIG_SERIAL_CLOCK: devpriv->serial_hw_mode = 1; - devpriv->dio_control |= DIO_HW_Serial_Enable; + devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA; if (data[1] == SERIAL_DISABLED) { devpriv->serial_hw_mode = 0; - devpriv->dio_control &= ~(DIO_HW_Serial_Enable | - DIO_Software_Serial_Control); + devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA | + NISTC_DIO_SDCLK); data[1] = SERIAL_DISABLED; devpriv->serial_interval_ns = data[1]; } else if (data[1] <= SERIAL_600NS) { /* Warning: this clock speed is too fast to reliably control SCXI. */ - devpriv->dio_control &= ~DIO_HW_Serial_Timebase; - devpriv->clock_and_fout |= Slow_Internal_Timebase; - devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2; + devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE; + clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE; + clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2; data[1] = SERIAL_600NS; devpriv->serial_interval_ns = data[1]; } else if (data[1] <= SERIAL_1_2US) { - devpriv->dio_control &= ~DIO_HW_Serial_Timebase; - devpriv->clock_and_fout |= Slow_Internal_Timebase | - DIO_Serial_Out_Divide_By_2; + devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE; + clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE | + NISTC_CLK_FOUT_DIO_SER_OUT_DIV2; data[1] = SERIAL_1_2US; devpriv->serial_interval_ns = data[1]; } else if (data[1] <= SERIAL_10US) { - devpriv->dio_control |= DIO_HW_Serial_Timebase; - devpriv->clock_and_fout |= Slow_Internal_Timebase | - DIO_Serial_Out_Divide_By_2; - /* Note: DIO_Serial_Out_Divide_By_2 only affects + devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE; + clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE | + NISTC_CLK_FOUT_DIO_SER_OUT_DIV2; + /* Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects 600ns/1.2us. If you turn divide_by_2 off with the slow clock, you will still get 10us, except then all your delays are wrong. */ data[1] = SERIAL_10US; devpriv->serial_interval_ns = data[1]; } else { - devpriv->dio_control &= ~(DIO_HW_Serial_Enable | - DIO_Software_Serial_Control); + devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA | + NISTC_DIO_SDCLK); devpriv->serial_hw_mode = 0; data[1] = (data[1] / 1000) * 1000; devpriv->serial_interval_ns = data[1]; } + devpriv->clock_and_fout = clk_fout; - ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register); - ni_stc_writew(dev, devpriv->clock_and_fout, - Clock_and_FOUT_Register); + ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); + ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); return 1; case INSN_CONFIG_BIDIRECTIONAL_DATA: @@ -3850,141 +3708,91 @@ static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s) int i; for (i = 0; i < s->n_chan; i++) { - ni_ao_win_outw(dev, AO_Channel(i) | 0x0, - AO_Configuration_2_67xx); - } - ni_ao_win_outw(dev, 0x0, AO_Later_Single_Point_Updates); -} + ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0, + NI67XX_AO_CFG2_REG); + } + ni_ao_win_outw(dev, 0x0, NI67XX_AO_SP_UPDATES_REG); +} + +static const struct mio_regmap ni_gpct_to_stc_regmap[] = { + [NITIO_G0_AUTO_INC] = { NISTC_G0_AUTOINC_REG, 2 }, + [NITIO_G1_AUTO_INC] = { NISTC_G1_AUTOINC_REG, 2 }, + [NITIO_G0_CMD] = { NISTC_G0_CMD_REG, 2 }, + [NITIO_G1_CMD] = { NISTC_G1_CMD_REG, 2 }, + [NITIO_G0_HW_SAVE] = { NISTC_G0_HW_SAVE_REG, 4 }, + [NITIO_G1_HW_SAVE] = { NISTC_G1_HW_SAVE_REG, 4 }, + [NITIO_G0_SW_SAVE] = { NISTC_G0_SAVE_REG, 4 }, + [NITIO_G1_SW_SAVE] = { NISTC_G1_SAVE_REG, 4 }, + [NITIO_G0_MODE] = { NISTC_G0_MODE_REG, 2 }, + [NITIO_G1_MODE] = { NISTC_G1_MODE_REG, 2 }, + [NITIO_G0_LOADA] = { NISTC_G0_LOADA_REG, 4 }, + [NITIO_G1_LOADA] = { NISTC_G1_LOADA_REG, 4 }, + [NITIO_G0_LOADB] = { NISTC_G0_LOADB_REG, 4 }, + [NITIO_G1_LOADB] = { NISTC_G1_LOADB_REG, 4 }, + [NITIO_G0_INPUT_SEL] = { NISTC_G0_INPUT_SEL_REG, 2 }, + [NITIO_G1_INPUT_SEL] = { NISTC_G1_INPUT_SEL_REG, 2 }, + [NITIO_G0_CNT_MODE] = { 0x1b0, 2 }, /* M-Series only */ + [NITIO_G1_CNT_MODE] = { 0x1b2, 2 }, /* M-Series only */ + [NITIO_G0_GATE2] = { 0x1b4, 2 }, /* M-Series only */ + [NITIO_G1_GATE2] = { 0x1b6, 2 }, /* M-Series only */ + [NITIO_G01_STATUS] = { NISTC_G01_STATUS_REG, 2 }, + [NITIO_G01_RESET] = { NISTC_RESET_REG, 2 }, + [NITIO_G01_STATUS1] = { NISTC_STATUS1_REG, 2 }, + [NITIO_G01_STATUS2] = { NISTC_STATUS2_REG, 2 }, + [NITIO_G0_DMA_CFG] = { 0x1b8, 2 }, /* M-Series only */ + [NITIO_G1_DMA_CFG] = { 0x1ba, 2 }, /* M-Series only */ + [NITIO_G0_DMA_STATUS] = { 0x1b8, 2 }, /* M-Series only */ + [NITIO_G1_DMA_STATUS] = { 0x1ba, 2 }, /* M-Series only */ + [NITIO_G0_ABZ] = { 0x1c0, 2 }, /* M-Series only */ + [NITIO_G1_ABZ] = { 0x1c2, 2 }, /* M-Series only */ + [NITIO_G0_INT_ACK] = { NISTC_INTA_ACK_REG, 2 }, + [NITIO_G1_INT_ACK] = { NISTC_INTB_ACK_REG, 2 }, + [NITIO_G0_STATUS] = { NISTC_AI_STATUS1_REG, 2 }, + [NITIO_G1_STATUS] = { NISTC_AO_STATUS1_REG, 2 }, + [NITIO_G0_INT_ENA] = { NISTC_INTA_ENA_REG, 2 }, + [NITIO_G1_INT_ENA] = { NISTC_INTB_ENA_REG, 2 }, +}; -static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg) +static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev, + enum ni_gpct_register reg) { - unsigned stc_register; + const struct mio_regmap *regmap; - switch (reg) { - case NITIO_G0_AUTO_INC: - stc_register = G_Autoincrement_Register(0); - break; - case NITIO_G1_AUTO_INC: - stc_register = G_Autoincrement_Register(1); - break; - case NITIO_G0_CMD: - stc_register = G_Command_Register(0); - break; - case NITIO_G1_CMD: - stc_register = G_Command_Register(1); - break; - case NITIO_G0_HW_SAVE: - stc_register = G_HW_Save_Register(0); - break; - case NITIO_G1_HW_SAVE: - stc_register = G_HW_Save_Register(1); - break; - case NITIO_G0_SW_SAVE: - stc_register = G_Save_Register(0); - break; - case NITIO_G1_SW_SAVE: - stc_register = G_Save_Register(1); - break; - case NITIO_G0_MODE: - stc_register = G_Mode_Register(0); - break; - case NITIO_G1_MODE: - stc_register = G_Mode_Register(1); - break; - case NITIO_G0_LOADA: - stc_register = G_Load_A_Register(0); - break; - case NITIO_G1_LOADA: - stc_register = G_Load_A_Register(1); - break; - case NITIO_G0_LOADB: - stc_register = G_Load_B_Register(0); - break; - case NITIO_G1_LOADB: - stc_register = G_Load_B_Register(1); - break; - case NITIO_G0_INPUT_SEL: - stc_register = G_Input_Select_Register(0); - break; - case NITIO_G1_INPUT_SEL: - stc_register = G_Input_Select_Register(1); - break; - case NITIO_G01_STATUS: - stc_register = G_Status_Register; - break; - case NITIO_G01_RESET: - stc_register = Joint_Reset_Register; - break; - case NITIO_G01_STATUS1: - stc_register = Joint_Status_1_Register; - break; - case NITIO_G01_STATUS2: - stc_register = Joint_Status_2_Register; - break; - case NITIO_G0_INT_ACK: - stc_register = Interrupt_A_Ack_Register; - break; - case NITIO_G1_INT_ACK: - stc_register = Interrupt_B_Ack_Register; - break; - case NITIO_G0_STATUS: - stc_register = AI_Status_1_Register; - break; - case NITIO_G1_STATUS: - stc_register = AO_Status_1_Register; - break; - case NITIO_G0_INT_ENA: - stc_register = Interrupt_A_Enable_Register; - break; - case NITIO_G1_INT_ENA: - stc_register = Interrupt_B_Enable_Register; - break; - default: - pr_err("%s: unhandled register 0x%x in switch.\n", - __func__, reg); - BUG(); + if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) { + regmap = &ni_gpct_to_stc_regmap[reg]; + } else { + dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n", + __func__, reg); return 0; } - return stc_register; + + return regmap->mio_reg; } static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, enum ni_gpct_register reg) { struct comedi_device *dev = counter->counter_dev->dev; - unsigned stc_register; - /* bits in the join reset register which are relevant to counters */ - static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset; + unsigned int stc_register = ni_gpct_to_stc_register(dev, reg); static const unsigned gpct_interrupt_a_enable_mask = - G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable; + NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC; static const unsigned gpct_interrupt_b_enable_mask = - G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable; + NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC; + + if (stc_register == 0) + return; switch (reg) { - /* m-series-only registers */ + /* m-series only registers */ case NITIO_G0_CNT_MODE: - ni_writew(dev, bits, M_Offset_G0_Counting_Mode); - break; case NITIO_G1_CNT_MODE: - ni_writew(dev, bits, M_Offset_G1_Counting_Mode); - break; case NITIO_G0_GATE2: - ni_writew(dev, bits, M_Offset_G0_Second_Gate); - break; case NITIO_G1_GATE2: - ni_writew(dev, bits, M_Offset_G1_Second_Gate); - break; case NITIO_G0_DMA_CFG: - ni_writew(dev, bits, M_Offset_G0_DMA_Config); - break; case NITIO_G1_DMA_CFG: - ni_writew(dev, bits, M_Offset_G1_DMA_Config); - break; case NITIO_G0_ABZ: - ni_writew(dev, bits, M_Offset_G0_MSeries_ABZ); - break; case NITIO_G1_ABZ: - ni_writew(dev, bits, M_Offset_G1_MSeries_ABZ); + ni_writew(dev, bits, stc_register); break; /* 32 bit registers */ @@ -3992,26 +3800,24 @@ static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, case NITIO_G1_LOADA: case NITIO_G0_LOADB: case NITIO_G1_LOADB: - stc_register = ni_gpct_to_stc_register(reg); ni_stc_writel(dev, bits, stc_register); break; /* 16 bit registers */ case NITIO_G0_INT_ENA: BUG_ON(bits & ~gpct_interrupt_a_enable_mask); - ni_set_bitfield(dev, Interrupt_A_Enable_Register, + ni_set_bitfield(dev, stc_register, gpct_interrupt_a_enable_mask, bits); break; case NITIO_G1_INT_ENA: BUG_ON(bits & ~gpct_interrupt_b_enable_mask); - ni_set_bitfield(dev, Interrupt_B_Enable_Register, + ni_set_bitfield(dev, stc_register, gpct_interrupt_b_enable_mask, bits); break; case NITIO_G01_RESET: - BUG_ON(bits & ~gpct_joint_reset_mask); + BUG_ON(bits & ~(NISTC_RESET_G0 | NISTC_RESET_G1)); /* fall-through */ default: - stc_register = ni_gpct_to_stc_register(reg); ni_stc_writew(dev, bits, stc_register); } } @@ -4020,29 +3826,28 @@ static unsigned ni_gpct_read_register(struct ni_gpct *counter, enum ni_gpct_register reg) { struct comedi_device *dev = counter->counter_dev->dev; - unsigned stc_register; + unsigned int stc_register = ni_gpct_to_stc_register(dev, reg); + + if (stc_register == 0) + return 0; switch (reg) { /* m-series only registers */ case NITIO_G0_DMA_STATUS: - return ni_readw(dev, M_Offset_G0_DMA_Status); case NITIO_G1_DMA_STATUS: - return ni_readw(dev, M_Offset_G1_DMA_Status); + return ni_readw(dev, stc_register); /* 32 bit registers */ case NITIO_G0_HW_SAVE: case NITIO_G1_HW_SAVE: case NITIO_G0_SW_SAVE: case NITIO_G1_SW_SAVE: - stc_register = ni_gpct_to_stc_register(reg); return ni_stc_readl(dev, stc_register); /* 16 bit registers */ default: - stc_register = ni_gpct_to_stc_register(reg); return ni_stc_readw(dev, stc_register); } - return 0; } static int ni_freq_out_insn_read(struct comedi_device *dev, @@ -4051,7 +3856,7 @@ static int ni_freq_out_insn_read(struct comedi_device *dev, unsigned int *data) { struct ni_private *devpriv = dev->private; - unsigned int val = devpriv->clock_and_fout & FOUT_Divider_mask; + unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout); int i; for (i = 0; i < insn->n; i++) @@ -4068,17 +3873,17 @@ static int ni_freq_out_insn_write(struct comedi_device *dev, struct ni_private *devpriv = dev->private; if (insn->n) { - devpriv->clock_and_fout &= ~FOUT_Enable; - ni_stc_writew(dev, devpriv->clock_and_fout, - Clock_and_FOUT_Register); - devpriv->clock_and_fout &= ~FOUT_Divider_mask; + unsigned int val = data[insn->n - 1]; + + devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA; + ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); + devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK; /* use the last data value to set the fout divider */ - devpriv->clock_and_fout |= FOUT_Divider(data[insn->n - 1]); + devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val); - devpriv->clock_and_fout |= FOUT_Enable; - ni_stc_writew(dev, devpriv->clock_and_fout, - Clock_and_FOUT_Register); + devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA; + ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); } return insn->n; } @@ -4094,19 +3899,18 @@ static int ni_freq_out_insn_config(struct comedi_device *dev, case INSN_CONFIG_SET_CLOCK_SRC: switch (data[1]) { case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC: - devpriv->clock_and_fout &= ~FOUT_Timebase_Select; + devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL; break; case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC: - devpriv->clock_and_fout |= FOUT_Timebase_Select; + devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL; break; default: return -EINVAL; } - ni_stc_writew(dev, devpriv->clock_and_fout, - Clock_and_FOUT_Register); + ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); break; case INSN_CONFIG_GET_CLOCK_SRC: - if (devpriv->clock_and_fout & FOUT_Timebase_Select) { + if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) { data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC; data[2] = TIMEBASE_2_NS; } else { @@ -4190,9 +3994,9 @@ static int ni_m_series_pwm_config(struct comedi_device *dev, data[4] = down_count * devpriv->clock_ns; return -EAGAIN; } - ni_writel(dev, MSeries_Cal_PWM_High_Time_Bits(up_count) | - MSeries_Cal_PWM_Low_Time_Bits(down_count), - M_Offset_Cal_PWM); + ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) | + NI_M_CAL_PWM_LOW_TIME(down_count), + NI_M_CAL_PWM_REG); devpriv->pwm_up_count = up_count; devpriv->pwm_down_count = down_count; return 5; @@ -4254,9 +4058,9 @@ static int ni_6143_pwm_config(struct comedi_device *dev, data[4] = down_count * devpriv->clock_ns; return -EAGAIN; } - ni_writel(dev, up_count, Calibration_HighTime_6143); + ni_writel(dev, up_count, NI6143_CALIB_HI_TIME_REG); devpriv->pwm_up_count = up_count; - ni_writel(dev, down_count, Calibration_LowTime_6143); + ni_writel(dev, down_count, NI6143_CALIB_LO_TIME_REG); devpriv->pwm_down_count = down_count; return 5; case INSN_CONFIG_GET_PWM_OUTPUT: @@ -4336,6 +4140,7 @@ static void ni_write_caldac(struct comedi_device *dev, int addr, int val) const struct ni_board_struct *board = dev->board_ptr; struct ni_private *devpriv = dev->private; unsigned int loadbit = 0, bits = 0, bit, bitstring = 0; + unsigned int cmd; int i; int type; @@ -4349,22 +4154,26 @@ static void ni_write_caldac(struct comedi_device *dev, int addr, int val) break; if (addr < caldacs[type].n_chans) { bits = caldacs[type].packbits(addr, val, &bitstring); - loadbit = SerDacLd(i); + loadbit = NI_E_SERIAL_CMD_DAC_LD(i); break; } addr -= caldacs[type].n_chans; } + /* bits will be 0 if there is no caldac for the given addr */ + if (bits == 0) + return; + for (bit = 1 << (bits - 1); bit; bit >>= 1) { - ni_writeb(dev, ((bit & bitstring) ? 0x02 : 0), Serial_Command); + cmd = (bit & bitstring) ? NI_E_SERIAL_CMD_SDATA : 0; + ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG); udelay(1); - ni_writeb(dev, 1 | ((bit & bitstring) ? 0x02 : 0), - Serial_Command); + ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG); udelay(1); } - ni_writeb(dev, loadbit, Serial_Command); + ni_writeb(dev, loadbit, NI_E_SERIAL_CMD_REG); udelay(1); - ni_writeb(dev, 0, Serial_Command); + ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG); } static int ni_calib_insn_write(struct comedi_device *dev, @@ -4446,24 +4255,30 @@ static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s) static int ni_read_eeprom(struct comedi_device *dev, int addr) { + unsigned int cmd = NI_E_SERIAL_CMD_EEPROM_CS; int bit; int bitstring; bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff); - ni_writeb(dev, 0x04, Serial_Command); + ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG); for (bit = 0x8000; bit; bit >>= 1) { - ni_writeb(dev, 0x04 | ((bit & bitstring) ? 0x02 : 0), - Serial_Command); - ni_writeb(dev, 0x05 | ((bit & bitstring) ? 0x02 : 0), - Serial_Command); + if (bit & bitstring) + cmd |= NI_E_SERIAL_CMD_SDATA; + else + cmd &= ~NI_E_SERIAL_CMD_SDATA; + + ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG); + ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG); } + cmd = NI_E_SERIAL_CMD_EEPROM_CS; bitstring = 0; for (bit = 0x80; bit; bit >>= 1) { - ni_writeb(dev, 0x04, Serial_Command); - ni_writeb(dev, 0x05, Serial_Command); - bitstring |= ((ni_readb(dev, XXX_Status) & PROMOUT) ? bit : 0); + ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG); + ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG); + if (ni_readb(dev, NI_E_STATUS_REG) & NI_E_STATUS_PROMOUT) + bitstring |= bit; } - ni_writeb(dev, 0x00, Serial_Command); + ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG); return bitstring; } @@ -4537,7 +4352,7 @@ static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev, struct ni_private *devpriv = dev->private; const unsigned array_offset = chan / 3; - return MSeries_PFI_Output_Select_Source(chan, + return NI_M_PFI_OUT_SEL_TO_SRC(chan, devpriv->pfi_output_select_reg[array_offset]); } @@ -4545,19 +4360,17 @@ static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan, unsigned source) { struct ni_private *devpriv = dev->private; - unsigned pfi_reg_index; - unsigned array_offset; + unsigned index = chan / 3; + unsigned short val = devpriv->pfi_output_select_reg[index]; if ((source & 0x1f) != source) return -EINVAL; - pfi_reg_index = 1 + chan / 3; - array_offset = pfi_reg_index - 1; - devpriv->pfi_output_select_reg[array_offset] &= - ~MSeries_PFI_Output_Select_Mask(chan); - devpriv->pfi_output_select_reg[array_offset] |= - MSeries_PFI_Output_Select_Bits(chan, source); - ni_writew(dev, devpriv->pfi_output_select_reg[array_offset], - M_Offset_PFI_Output_Select(pfi_reg_index)); + + val &= ~NI_M_PFI_OUT_SEL_MASK(chan); + val |= NI_M_PFI_OUT_SEL(chan, source); + ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index)); + devpriv->pfi_output_select_reg[index] = val; + return 2; } @@ -4590,10 +4403,10 @@ static int ni_config_filter(struct comedi_device *dev, if (!devpriv->is_m_series) return -ENOTSUPP; - bits = ni_readl(dev, M_Offset_PFI_Filter); - bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel); - bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter); - ni_writel(dev, bits, M_Offset_PFI_Filter); + bits = ni_readl(dev, NI_M_PFI_FILTER_REG); + bits &= ~NI_M_PFI_FILTER_SEL_MASK(pfi_channel); + bits |= NI_M_PFI_FILTER_SEL(pfi_channel, filter); + ni_writel(dev, bits, NI_M_PFI_FILTER_REG); return 0; } @@ -4612,10 +4425,10 @@ static int ni_pfi_insn_config(struct comedi_device *dev, switch (data[0]) { case COMEDI_OUTPUT: - ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1); + ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 1); break; case COMEDI_INPUT: - ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0); + ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 0); break; case INSN_CONFIG_DIO_QUERY: data[1] = @@ -4646,9 +4459,9 @@ static int ni_pfi_insn_bits(struct comedi_device *dev, return -ENOTSUPP; if (comedi_dio_update_state(s, data)) - ni_writew(dev, s->state, M_Offset_PFI_DO); + ni_writew(dev, s->state, NI_M_PFI_DO_REG); - data[1] = ni_readw(dev, M_Offset_PFI_DI); + data[1] = ni_readw(dev, NI_M_PFI_DI_REG); return insn->n; } @@ -4660,8 +4473,8 @@ static int cs5529_wait_for_idle(struct comedi_device *dev) int i; for (i = 0; i < timeout; i++) { - status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx); - if ((status & CSS_ADC_BUSY) == 0) + status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG); + if ((status & NI67XX_CAL_STATUS_BUSY) == 0) break; set_current_state(TASK_INTERRUPTIBLE); if (schedule_timeout(1)) @@ -4679,13 +4492,14 @@ static void cs5529_command(struct comedi_device *dev, unsigned short value) static const int timeout = 100; int i; - ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx); + ni_ao_win_outw(dev, value, NI67XX_CAL_CMD_REG); /* give time for command to start being serially clocked into cs5529. - * this insures that the CSS_ADC_BUSY bit will get properly + * this insures that the NI67XX_CAL_STATUS_BUSY bit will get properly * set before we exit this function. */ for (i = 0; i < timeout; i++) { - if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY)) + if (ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG) & + NI67XX_CAL_STATUS_BUSY) break; udelay(1); } @@ -4700,25 +4514,25 @@ static int cs5529_do_conversion(struct comedi_device *dev, int retval; unsigned short status; - cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION); + cs5529_command(dev, CS5529_CMD_CB | CS5529_CMD_SINGLE_CONV); retval = cs5529_wait_for_idle(dev); if (retval) { dev_err(dev->class_dev, "timeout or signal in cs5529_do_conversion()\n"); return -ETIME; } - status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx); - if (status & CSS_OSC_DETECT) { + status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG); + if (status & NI67XX_CAL_STATUS_OSC_DETECT) { dev_err(dev->class_dev, "cs5529 conversion error, status CSS_OSC_DETECT\n"); return -EIO; } - if (status & CSS_OVERRANGE) { + if (status & NI67XX_CAL_STATUS_OVERRANGE) { dev_err(dev->class_dev, "cs5529 conversion error, overrange (ignoring)\n"); } if (data) { - *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx); + *data = ni_ao_win_inw(dev, NI67XX_CAL_DATA_REG); /* cs5529 returns 16 bit signed data in bipolar mode */ *data ^= (1 << 15); } @@ -4742,7 +4556,7 @@ static int cs5529_ai_insn_read(struct comedi_device *dev, channel_select = INTERNAL_REF; else channel_select = CR_CHAN(insn->chanspec); - ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx); + ni_ao_win_outw(dev, channel_select, NI67XX_AO_CAL_CHAN_SEL_REG); for (n = 0; n < insn->n; n++) { retval = cs5529_do_conversion(dev, &sample); @@ -4756,12 +4570,10 @@ static int cs5529_ai_insn_read(struct comedi_device *dev, static void cs5529_config_write(struct comedi_device *dev, unsigned int value, unsigned int reg_select_bits) { - ni_ao_win_outw(dev, ((value >> 16) & 0xff), - CAL_ADC_Config_Data_High_Word_67xx); - ni_ao_win_outw(dev, (value & 0xffff), - CAL_ADC_Config_Data_Low_Word_67xx); - reg_select_bits &= CSCMD_REGISTER_SELECT_MASK; - cs5529_command(dev, CSCMD_COMMAND | reg_select_bits); + ni_ao_win_outw(dev, (value >> 16) & 0xff, NI67XX_CAL_CFG_HI_REG); + ni_ao_win_outw(dev, value & 0xffff, NI67XX_CAL_CFG_LO_REG); + reg_select_bits &= CS5529_CMD_REG_MASK; + cs5529_command(dev, CS5529_CMD_CB | reg_select_bits); if (cs5529_wait_for_idle(dev)) dev_err(dev->class_dev, "timeout or signal in %s\n", __func__); @@ -4769,20 +4581,20 @@ static void cs5529_config_write(struct comedi_device *dev, unsigned int value, static int init_cs5529(struct comedi_device *dev) { - unsigned int config_bits = - CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES; + unsigned int config_bits = CS5529_CFG_PORT_FLAG | + CS5529_CFG_WORD_RATE_2180; #if 1 /* do self-calibration */ - cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN, - CSCMD_CONFIG_REGISTER); + cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_BOTH_SELF, + CS5529_CFG_REG); /* need to force a conversion for calibration to run */ cs5529_do_conversion(dev, NULL); #else /* force gain calibration to 1 */ - cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER); - cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET, - CSCMD_CONFIG_REGISTER); + cs5529_config_write(dev, 0x400000, CS5529_GAIN_REG); + cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_OFFSET_SELF, + CS5529_CFG_REG); if (cs5529_wait_for_idle(dev)) dev_err(dev->class_dev, "timeout or signal in %s\n", __func__); @@ -4801,10 +4613,8 @@ static int ni_mseries_get_pll_parameters(unsigned reference_period_ns, { unsigned div; unsigned best_div = 1; - static const unsigned max_div = 0x10; unsigned mult; unsigned best_mult = 1; - static const unsigned max_mult = 0x100; static const unsigned pico_per_nano = 1000; const unsigned reference_picosec = reference_period_ns * pico_per_nano; @@ -4814,8 +4624,8 @@ static int ni_mseries_get_pll_parameters(unsigned reference_period_ns, static const unsigned fudge_factor_80_to_20Mhz = 4; int best_period_picosec = 0; - for (div = 1; div <= max_div; ++div) { - for (mult = 1; mult <= max_mult; ++mult) { + for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) { + for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) { unsigned new_period_ps = (reference_picosec * div) / mult; if (abs(new_period_ps - target_picosec) < @@ -4847,6 +4657,7 @@ static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, unsigned pll_control_bits; unsigned freq_divider; unsigned freq_multiplier; + unsigned rtsi; unsigned i; int retval; @@ -4859,42 +4670,31 @@ static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, __func__, min_period_ns, max_period_ns); return -EINVAL; } - devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit; + devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK; ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, - RTSI_Trig_Direction_Register); - pll_control_bits = - MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits; - devpriv->clock_and_fout2 |= - MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit; - devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask; + NISTC_RTSI_TRIG_DIR_REG); + pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ; + devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL | + NI_M_CLK_FOUT2_TIMEBASE3_PLL; + devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK; switch (source) { case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK: - devpriv->clock_and_fout2 |= - MSeries_PLL_In_Source_Select_Star_Trigger_Bits; + devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR; break; case NI_MIO_PLL_PXI10_CLOCK: /* pxi clock is 10MHz */ - devpriv->clock_and_fout2 |= - MSeries_PLL_In_Source_Select_PXI_Clock10; + devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10; break; default: - { - unsigned rtsi_channel; - static const unsigned max_rtsi_channel = 7; - - for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel; - ++rtsi_channel) { - if (source == - NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) { - devpriv->clock_and_fout2 |= - MSeries_PLL_In_Source_Select_RTSI_Bits - (rtsi_channel); - break; - } + for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) { + if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) { + devpriv->clock_and_fout2 |= + NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi); + break; } - if (rtsi_channel > max_rtsi_channel) - return -EINVAL; } + if (rtsi > NI_M_MAX_RTSI_CHAN) + return -EINVAL; break; } retval = ni_mseries_get_pll_parameters(period_ns, @@ -4907,16 +4707,15 @@ static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, return retval; } - ni_writew(dev, devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2); - pll_control_bits |= - MSeries_PLL_Divisor_Bits(freq_divider) | - MSeries_PLL_Multiplier_Bits(freq_multiplier); + ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG); + pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) | + NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier); - ni_writew(dev, pll_control_bits, M_Offset_PLL_Control); + ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG); devpriv->clock_source = source; /* it seems to typically take a few hundred microseconds for PLL to lock */ for (i = 0; i < timeout; ++i) { - if (ni_readw(dev, M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) + if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED) break; udelay(1); } @@ -4935,17 +4734,17 @@ static int ni_set_master_clock(struct comedi_device *dev, struct ni_private *devpriv = dev->private; if (source == NI_MIO_INTERNAL_CLOCK) { - devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit; + devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK; ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, - RTSI_Trig_Direction_Register); + NISTC_RTSI_TRIG_DIR_REG); devpriv->clock_ns = TIMEBASE_1_NS; if (devpriv->is_m_series) { devpriv->clock_and_fout2 &= - ~(MSeries_Timebase1_Select_Bit | - MSeries_Timebase3_Select_Bit); + ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL | + NI_M_CLK_FOUT2_TIMEBASE3_PLL); ni_writew(dev, devpriv->clock_and_fout2, - M_Offset_Clock_and_Fout2); - ni_writew(dev, 0, M_Offset_PLL_Control); + NI_M_CLK_FOUT2_REG); + ni_writew(dev, 0, NI_M_PLL_CTRL_REG); } devpriv->clock_source = source; } else { @@ -4955,10 +4754,10 @@ static int ni_set_master_clock(struct comedi_device *dev, } else { if (source == NI_MIO_RTSI_CLOCK) { devpriv->rtsi_trig_direction_reg |= - Use_RTSI_Clock_Bit; + NISTC_RTSI_TRIG_USE_CLK; ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, - RTSI_Trig_Direction_Register); + NISTC_RTSI_TRIG_DIR_REG); if (period_ns == 0) { dev_err(dev->class_dev, "we don't handle an unspecified clock period correctly yet, returning error\n"); @@ -4974,26 +4773,19 @@ static int ni_set_master_clock(struct comedi_device *dev, return 3; } -static unsigned num_configurable_rtsi_channels(struct comedi_device *dev) -{ - struct ni_private *devpriv = dev->private; - - return (devpriv->is_m_series) ? 8 : 7; -} - static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan, unsigned source) { struct ni_private *devpriv = dev->private; - if (chan >= num_configurable_rtsi_channels(dev)) { - if (chan == old_RTSI_clock_channel) { + if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) { + if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) { if (source == NI_RTSI_OUTPUT_RTSI_OSC) return 1; dev_err(dev->class_dev, "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n", - __func__, chan, old_RTSI_clock_channel); + __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN); return 0; } return 0; @@ -5017,24 +4809,22 @@ static int ni_valid_rtsi_output_source(struct comedi_device *dev, } static int ni_set_rtsi_routing(struct comedi_device *dev, - unsigned chan, unsigned source) + unsigned chan, unsigned src) { struct ni_private *devpriv = dev->private; - if (ni_valid_rtsi_output_source(dev, chan, source) == 0) + if (ni_valid_rtsi_output_source(dev, chan, src) == 0) return -EINVAL; if (chan < 4) { - devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan); - devpriv->rtsi_trig_a_output_reg |= - RTSI_Trig_Output_Bits(chan, source); + devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan); + devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src); ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg, - RTSI_Trig_A_Output_Register); + NISTC_RTSI_TRIGA_OUT_REG); } else if (chan < 8) { - devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan); - devpriv->rtsi_trig_b_output_reg |= - RTSI_Trig_Output_Bits(chan, source); + devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan); + devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src); ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg, - RTSI_Trig_B_Output_Register); + NISTC_RTSI_TRIGB_OUT_REG); } return 2; } @@ -5044,13 +4834,13 @@ static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan) struct ni_private *devpriv = dev->private; if (chan < 4) { - return RTSI_Trig_Output_Source(chan, - devpriv->rtsi_trig_a_output_reg); - } else if (chan < num_configurable_rtsi_channels(dev)) { - return RTSI_Trig_Output_Source(chan, - devpriv->rtsi_trig_b_output_reg); + return NISTC_RTSI_TRIG_TO_SRC(chan, + devpriv->rtsi_trig_a_output_reg); + } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) { + return NISTC_RTSI_TRIG_TO_SRC(chan, + devpriv->rtsi_trig_b_output_reg); } else { - if (chan == old_RTSI_clock_channel) + if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) return NI_RTSI_OUTPUT_RTSI_OSC; dev_err(dev->class_dev, "bug! should never get here?\n"); return 0; @@ -5064,42 +4854,43 @@ static int ni_rtsi_insn_config(struct comedi_device *dev, { struct ni_private *devpriv = dev->private; unsigned int chan = CR_CHAN(insn->chanspec); + unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series); switch (data[0]) { case INSN_CONFIG_DIO_OUTPUT: - if (chan < num_configurable_rtsi_channels(dev)) { + if (chan < max_chan) { devpriv->rtsi_trig_direction_reg |= - RTSI_Output_Bit(chan, devpriv->is_m_series); - } else if (chan == old_RTSI_clock_channel) { + NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series); + } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) { devpriv->rtsi_trig_direction_reg |= - Drive_RTSI_Clock_Bit; + NISTC_RTSI_TRIG_DRV_CLK; } ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, - RTSI_Trig_Direction_Register); + NISTC_RTSI_TRIG_DIR_REG); break; case INSN_CONFIG_DIO_INPUT: - if (chan < num_configurable_rtsi_channels(dev)) { + if (chan < max_chan) { devpriv->rtsi_trig_direction_reg &= - ~RTSI_Output_Bit(chan, devpriv->is_m_series); - } else if (chan == old_RTSI_clock_channel) { + ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series); + } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) { devpriv->rtsi_trig_direction_reg &= - ~Drive_RTSI_Clock_Bit; + ~NISTC_RTSI_TRIG_DRV_CLK; } ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, - RTSI_Trig_Direction_Register); + NISTC_RTSI_TRIG_DIR_REG); break; case INSN_CONFIG_DIO_QUERY: - if (chan < num_configurable_rtsi_channels(dev)) { + if (chan < max_chan) { data[1] = (devpriv->rtsi_trig_direction_reg & - RTSI_Output_Bit(chan, devpriv->is_m_series)) + NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series)) ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT; - } else if (chan == old_RTSI_clock_channel) { - data[1] = - (devpriv->rtsi_trig_direction_reg & - Drive_RTSI_Clock_Bit) - ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT; + } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) { + data[1] = (devpriv->rtsi_trig_direction_reg & + NISTC_RTSI_TRIG_DRV_CLK) + ? INSN_CONFIG_DIO_OUTPUT + : INSN_CONFIG_DIO_INPUT; } return 2; case INSN_CONFIG_SET_CLOCK_SRC: @@ -5135,37 +4926,37 @@ static void ni_rtsi_init(struct comedi_device *dev) /* Initialises the RTSI bus signal switch to a default state */ + /* + * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears + * to have no effect, at least on pxi-6281, which always uses + * 20MHz rtsi clock frequency + */ + devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ; /* Set clock mode to internal */ - devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit; if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n"); /* default internal lines routing to RTSI bus lines */ devpriv->rtsi_trig_a_output_reg = - RTSI_Trig_Output_Bits(0, - NI_RTSI_OUTPUT_ADR_START1) | - RTSI_Trig_Output_Bits(1, - NI_RTSI_OUTPUT_ADR_START2) | - RTSI_Trig_Output_Bits(2, - NI_RTSI_OUTPUT_SCLKG) | - RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN); + NISTC_RTSI_TRIG(0, NI_RTSI_OUTPUT_ADR_START1) | + NISTC_RTSI_TRIG(1, NI_RTSI_OUTPUT_ADR_START2) | + NISTC_RTSI_TRIG(2, NI_RTSI_OUTPUT_SCLKG) | + NISTC_RTSI_TRIG(3, NI_RTSI_OUTPUT_DACUPDN); ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg, - RTSI_Trig_A_Output_Register); + NISTC_RTSI_TRIGA_OUT_REG); devpriv->rtsi_trig_b_output_reg = - RTSI_Trig_Output_Bits(4, - NI_RTSI_OUTPUT_DA_START1) | - RTSI_Trig_Output_Bits(5, - NI_RTSI_OUTPUT_G_SRC0) | - RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0); + NISTC_RTSI_TRIG(4, NI_RTSI_OUTPUT_DA_START1) | + NISTC_RTSI_TRIG(5, NI_RTSI_OUTPUT_G_SRC0) | + NISTC_RTSI_TRIG(6, NI_RTSI_OUTPUT_G_GATE0); if (devpriv->is_m_series) devpriv->rtsi_trig_b_output_reg |= - RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC); + NISTC_RTSI_TRIG(7, NI_RTSI_OUTPUT_RTSI_OSC); ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg, - RTSI_Trig_B_Output_Register); + NISTC_RTSI_TRIGB_OUT_REG); -/* -* Sets the source and direction of the 4 on board lines -* ni_stc_writew(dev, 0x0000, RTSI_Board_Register); -*/ + /* + * Sets the source and direction of the 4 on board lines + * ni_stc_writew(dev, 0, NISTC_RTSI_BOARD_REG); + */ } #ifdef PCIDMA @@ -5199,88 +4990,6 @@ static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s) } #endif -#if 0 -/* - * Read the GPCTs current value. - */ -static int GPCT_G_Watch(struct comedi_device *dev, int chan) -{ - unsigned int hi1, hi2, lo; - - devpriv->gpct_command[chan] &= ~G_Save_Trace; - ni_stc_writew(dev, devpriv->gpct_command[chan], - G_Command_Register(chan)); - - devpriv->gpct_command[chan] |= G_Save_Trace; - ni_stc_writew(dev, devpriv->gpct_command[chan], - G_Command_Register(chan)); - - /* This procedure is used because the two registers cannot - * be read atomically. */ - do { - hi1 = ni_stc_readw(dev, G_Save_Register_High(chan)); - lo = ni_stc_readw(dev, G_Save_Register_Low(chan)); - hi2 = ni_stc_readw(dev, G_Save_Register_High(chan)); - } while (hi1 != hi2); - - return (hi1 << 16) | lo; -} - -static void GPCT_Reset(struct comedi_device *dev, int chan) -{ - int temp_ack_reg = 0; - - devpriv->gpct_cur_operation[chan] = GPCT_RESET; - - switch (chan) { - case 0: - ni_stc_writew(dev, G0_Reset, Joint_Reset_Register); - ni_set_bits(dev, Interrupt_A_Enable_Register, - G0_TC_Interrupt_Enable, 0); - ni_set_bits(dev, Interrupt_A_Enable_Register, - G0_Gate_Interrupt_Enable, 0); - temp_ack_reg |= G0_Gate_Error_Confirm; - temp_ack_reg |= G0_TC_Error_Confirm; - temp_ack_reg |= G0_TC_Interrupt_Ack; - temp_ack_reg |= G0_Gate_Interrupt_Ack; - ni_stc_writew(dev, temp_ack_reg, Interrupt_A_Ack_Register); - - /* problem...this interferes with the other ctr... */ - devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable; - ni_stc_writew(dev, devpriv->an_trig_etc_reg, - Analog_Trigger_Etc_Register); - break; - case 1: - ni_stc_writew(dev, G1_Reset, Joint_Reset_Register); - ni_set_bits(dev, Interrupt_B_Enable_Register, - G1_TC_Interrupt_Enable, 0); - ni_set_bits(dev, Interrupt_B_Enable_Register, - G0_Gate_Interrupt_Enable, 0); - temp_ack_reg |= G1_Gate_Error_Confirm; - temp_ack_reg |= G1_TC_Error_Confirm; - temp_ack_reg |= G1_TC_Interrupt_Ack; - temp_ack_reg |= G1_Gate_Interrupt_Ack; - ni_stc_writew(dev, temp_ack_reg, Interrupt_B_Ack_Register); - - devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable; - ni_stc_writew(dev, devpriv->an_trig_etc_reg, - Analog_Trigger_Etc_Register); - break; - } - - devpriv->gpct_mode[chan] = 0; - devpriv->gpct_input_select[chan] = 0; - devpriv->gpct_command[chan] = 0; - - devpriv->gpct_command[chan] |= G_Synchronized_Gate; - - ni_stc_writew(dev, devpriv->gpct_mode[chan], G_Mode_Register(chan)); - ni_stc_writew(dev, devpriv->gpct_input_select[chan], - G_Input_Select_Register(chan)); - ni_stc_writew(dev, 0, G_Autoincrement_Register(chan)); -} -#endif - static irqreturn_t ni_E_interrupt(int irq, void *d) { struct comedi_device *dev = d; @@ -5300,8 +5009,8 @@ static irqreturn_t ni_E_interrupt(int irq, void *d) /* lock to avoid race with comedi_poll */ spin_lock_irqsave(&dev->spinlock, flags); - a_status = ni_stc_readw(dev, AI_Status_1_Register); - b_status = ni_stc_readw(dev, AO_Status_1_Register); + a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG); + b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG); #ifdef PCIDMA if (mite) { struct ni_private *devpriv = dev->private; @@ -5329,9 +5038,9 @@ static irqreturn_t ni_E_interrupt(int irq, void *d) #endif ack_a_interrupt(dev, a_status); ack_b_interrupt(dev, b_status); - if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT)) + if ((a_status & NISTC_AI_STATUS1_INTA) || (ai_mite_status & CHSR_INT)) handle_a_interrupt(dev, a_status, ai_mite_status); - if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT)) + if ((b_status & NISTC_AO_STATUS1_INTB) || (ao_mite_status & CHSR_INT)) handle_b_interrupt(dev, b_status, ao_mite_status); handle_gpct_interrupt(dev, 0); handle_gpct_interrupt(dev, 1); @@ -5371,16 +5080,16 @@ static int ni_E_init(struct comedi_device *dev, } /* initialize clock dividers */ - devpriv->clock_and_fout = Slow_Internal_Time_Divide_By_2 | - Slow_Internal_Timebase | - Clock_To_Board_Divide_By_2 | - Clock_To_Board; + devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 | + NISTC_CLK_FOUT_SLOW_TIMEBASE | + NISTC_CLK_FOUT_TO_BOARD_DIV2 | + NISTC_CLK_FOUT_TO_BOARD; if (!devpriv->is_6xxx) { /* BEAM is this needed for PCI-6143 ?? */ - devpriv->clock_and_fout |= (AI_Output_Divide_By_2 | - AO_Output_Divide_By_2); + devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 | + NISTC_CLK_FOUT_AO_OUT_DIV2); } - ni_stc_writew(dev, devpriv->clock_and_fout, Clock_and_FOUT_Register); + ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES); if (ret) @@ -5489,22 +5198,24 @@ static int ni_E_init(struct comedi_device *dev, } /* reset DIO and set all channels to inputs */ - ni_writel(dev, CDO_Reset_Bit | CDI_Reset_Bit, - M_Offset_CDIO_Command); - ni_writel(dev, s->io_bits, M_Offset_DIO_Direction); + ni_writel(dev, NI_M_CDO_CMD_RESET | + NI_M_CDI_CMD_RESET, + NI_M_CDIO_CMD_REG); + ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG); } else { s->insn_bits = ni_dio_insn_bits; s->insn_config = ni_dio_insn_config; /* set all channels to inputs */ - devpriv->dio_control = DIO_Pins_Dir(s->io_bits); - ni_writew(dev, devpriv->dio_control, DIO_Control_Register); + devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits); + ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); } /* 8255 device */ s = &dev->subdevices[NI_8255_DIO_SUBDEV]; if (board->has_8255) { - ret = subdev_8255_init(dev, s, ni_8255_callback, Port_A); + ret = subdev_8255_init(dev, s, ni_8255_callback, + NI_E_8255_BASE); if (ret) return ret; } else { @@ -5525,7 +5236,7 @@ static int ni_E_init(struct comedi_device *dev, /* internal PWM output used for AI nonlinearity calibration */ s->insn_config = ni_m_series_pwm_config; - ni_writel(dev, 0x0, M_Offset_Cal_PWM); + ni_writel(dev, 0x0, NI_M_CAL_PWM_REG); } else if (devpriv->is_6143) { /* internal PWM output used for AI nonlinearity calibration */ s->insn_config = ni_6143_pwm_config; @@ -5560,17 +5271,17 @@ static int ni_E_init(struct comedi_device *dev, s->n_chan = 16; s->insn_bits = ni_pfi_insn_bits; - ni_writew(dev, s->state, M_Offset_PFI_DO); + ni_writew(dev, s->state, NI_M_PFI_DO_REG); for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) { ni_writew(dev, devpriv->pfi_output_select_reg[i], - M_Offset_PFI_Output_Select(i + 1)); + NI_M_PFI_OUT_SEL_REG(i)); } } else { s->n_chan = 10; } s->insn_config = ni_pfi_insn_config; - ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0); + ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0); /* cs5529 calibration adc */ s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV]; @@ -5663,30 +5374,31 @@ static int ni_E_init(struct comedi_device *dev, if (dev->irq) { ni_stc_writew(dev, - (irq_polarity ? Interrupt_Output_Polarity : 0) | - (Interrupt_Output_On_3_Pins & 0) | - Interrupt_A_Enable | Interrupt_B_Enable | - Interrupt_A_Output_Select(interrupt_pin) | - Interrupt_B_Output_Select(interrupt_pin), - Interrupt_Control_Register); + (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) | + (NISTC_INT_CTRL_3PIN_INT & 0) | + NISTC_INT_CTRL_INTA_ENA | + NISTC_INT_CTRL_INTB_ENA | + NISTC_INT_CTRL_INTA_SEL(interrupt_pin) | + NISTC_INT_CTRL_INTB_SEL(interrupt_pin), + NISTC_INT_CTRL_REG); } /* DMA setup */ - ni_writeb(dev, devpriv->ai_ao_select_reg, AI_AO_Select); - ni_writeb(dev, devpriv->g0_g1_select_reg, G0_G1_Select); + ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG); + ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG); if (devpriv->is_6xxx) { - ni_writeb(dev, 0, Magic_611x); + ni_writeb(dev, 0, NI611X_MAGIC_REG); } else if (devpriv->is_m_series) { int channel; for (channel = 0; channel < board->n_aochan; ++channel) { ni_writeb(dev, 0xf, - M_Offset_AO_Waveform_Order(channel)); + NI_M_AO_WAVEFORM_ORDER_REG(channel)); ni_writeb(dev, 0x0, - M_Offset_AO_Reference_Attenuation(channel)); + NI_M_AO_REF_ATTENUATION_REG(channel)); } - ni_writeb(dev, 0x0, M_Offset_AO_Calibration); + ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG); } return 0; diff --git a/drivers/staging/comedi/drivers/ni_pcimio.c b/drivers/staging/comedi/drivers/ni_pcimio.c index 1481f71a31b1..30a5a75d1fe7 100644 --- a/drivers/staging/comedi/drivers/ni_pcimio.c +++ b/drivers/staging/comedi/drivers/ni_pcimio.c @@ -1085,26 +1085,25 @@ static void init_6143(struct comedi_device *dev) struct ni_private *devpriv = dev->private; /* Disable interrupts */ - ni_stc_writew(dev, 0, Interrupt_Control_Register); + ni_stc_writew(dev, 0, NISTC_INT_CTRL_REG); /* Initialise 6143 AI specific bits */ /* Set G0,G1 DMA mode to E series version */ - ni_writeb(dev, 0x00, Magic_6143); + ni_writeb(dev, 0x00, NI6143_MAGIC_REG); /* Set EOCMode, ADCMode and pipelinedelay */ - ni_writeb(dev, 0x80, PipelineDelay_6143); + ni_writeb(dev, 0x80, NI6143_PIPELINE_DELAY_REG); /* Set EOC Delay */ - ni_writeb(dev, 0x00, EOC_Set_6143); + ni_writeb(dev, 0x00, NI6143_EOC_SET_REG); /* Set the FIFO half full level */ - ni_writel(dev, board->ai_fifo_depth / 2, AIFIFO_Flag_6143); + ni_writel(dev, board->ai_fifo_depth / 2, NI6143_AI_FIFO_FLAG_REG); /* Strobe Relay disable bit */ devpriv->ai_calib_source_enabled = 0; - ni_writew(dev, devpriv->ai_calib_source | - Calibration_Channel_6143_RelayOff, - Calibration_Channel_6143); - ni_writew(dev, devpriv->ai_calib_source, Calibration_Channel_6143); + ni_writew(dev, devpriv->ai_calib_source | NI6143_CALIB_CHAN_RELAY_OFF, + NI6143_CALIB_CHAN_REG); + ni_writew(dev, devpriv->ai_calib_source, NI6143_CALIB_CHAN_REG); } static void pcimio_detach(struct comedi_device *dev) diff --git a/drivers/staging/comedi/drivers/ni_stc.h b/drivers/staging/comedi/drivers/ni_stc.h index bd69c3f0acdc..1d5af25b92a8 100644 --- a/drivers/staging/comedi/drivers/ni_stc.h +++ b/drivers/staging/comedi/drivers/ni_stc.h @@ -26,884 +26,907 @@ #include "ni_tio.h" -#define _bit15 0x8000 -#define _bit14 0x4000 -#define _bit13 0x2000 -#define _bit12 0x1000 -#define _bit11 0x0800 -#define _bit10 0x0400 -#define _bit9 0x0200 -#define _bit8 0x0100 -#define _bit7 0x0080 -#define _bit6 0x0040 -#define _bit5 0x0020 -#define _bit4 0x0010 -#define _bit3 0x0008 -#define _bit2 0x0004 -#define _bit1 0x0002 -#define _bit0 0x0001 - -#define NUM_PFI_OUTPUT_SELECT_REGS 6 - -/* Registers in the National Instruments DAQ-STC chip */ - -#define Interrupt_A_Ack_Register 2 -#define G0_Gate_Interrupt_Ack _bit15 -#define G0_TC_Interrupt_Ack _bit14 -#define AI_Error_Interrupt_Ack _bit13 -#define AI_STOP_Interrupt_Ack _bit12 -#define AI_START_Interrupt_Ack _bit11 -#define AI_START2_Interrupt_Ack _bit10 -#define AI_START1_Interrupt_Ack _bit9 -#define AI_SC_TC_Interrupt_Ack _bit8 -#define AI_SC_TC_Error_Confirm _bit7 -#define G0_TC_Error_Confirm _bit6 -#define G0_Gate_Error_Confirm _bit5 - -#define AI_Status_1_Register 2 -#define Interrupt_A_St 0x8000 -#define AI_FIFO_Full_St 0x4000 -#define AI_FIFO_Half_Full_St 0x2000 -#define AI_FIFO_Empty_St 0x1000 -#define AI_Overrun_St 0x0800 -#define AI_Overflow_St 0x0400 -#define AI_SC_TC_Error_St 0x0200 -#define AI_START2_St 0x0100 -#define AI_START1_St 0x0080 -#define AI_SC_TC_St 0x0040 -#define AI_START_St 0x0020 -#define AI_STOP_St 0x0010 -#define G0_TC_St 0x0008 -#define G0_Gate_Interrupt_St 0x0004 -#define AI_FIFO_Request_St 0x0002 -#define Pass_Thru_0_Interrupt_St 0x0001 - -#define AI_Status_2_Register 5 - -#define Interrupt_B_Ack_Register 3 -enum Interrupt_B_Ack_Bits { - G1_Gate_Error_Confirm = _bit1, - G1_TC_Error_Confirm = _bit2, - AO_BC_TC_Trigger_Error_Confirm = _bit3, - AO_BC_TC_Error_Confirm = _bit4, - AO_UI2_TC_Error_Confrim = _bit5, - AO_UI2_TC_Interrupt_Ack = _bit6, - AO_UC_TC_Interrupt_Ack = _bit7, - AO_BC_TC_Interrupt_Ack = _bit8, - AO_START1_Interrupt_Ack = _bit9, - AO_UPDATE_Interrupt_Ack = _bit10, - AO_START_Interrupt_Ack = _bit11, - AO_STOP_Interrupt_Ack = _bit12, - AO_Error_Interrupt_Ack = _bit13, - G1_TC_Interrupt_Ack = _bit14, - G1_Gate_Interrupt_Ack = _bit15 -}; - -#define AO_Status_1_Register 3 -#define Interrupt_B_St _bit15 -#define AO_FIFO_Full_St _bit14 -#define AO_FIFO_Half_Full_St _bit13 -#define AO_FIFO_Empty_St _bit12 -#define AO_BC_TC_Error_St _bit11 -#define AO_START_St _bit10 -#define AO_Overrun_St _bit9 -#define AO_START1_St _bit8 -#define AO_BC_TC_St _bit7 -#define AO_UC_TC_St _bit6 -#define AO_UPDATE_St _bit5 -#define AO_UI2_TC_St _bit4 -#define G1_TC_St _bit3 -#define G1_Gate_Interrupt_St _bit2 -#define AO_FIFO_Request_St _bit1 -#define Pass_Thru_1_Interrupt_St _bit0 - -#define AI_Command_2_Register 4 -#define AI_End_On_SC_TC _bit15 -#define AI_End_On_End_Of_Scan _bit14 -#define AI_START1_Disable _bit11 -#define AI_SC_Save_Trace _bit10 -#define AI_SI_Switch_Load_On_SC_TC _bit9 -#define AI_SI_Switch_Load_On_STOP _bit8 -#define AI_SI_Switch_Load_On_TC _bit7 -#define AI_SC_Switch_Load_On_TC _bit4 -#define AI_STOP_Pulse _bit3 -#define AI_START_Pulse _bit2 -#define AI_START2_Pulse _bit1 -#define AI_START1_Pulse _bit0 - -#define AO_Command_2_Register 5 -#define AO_End_On_BC_TC(x) (((x) & 0x3) << 14) -#define AO_Start_Stop_Gate_Enable _bit13 -#define AO_UC_Save_Trace _bit12 -#define AO_BC_Gate_Enable _bit11 -#define AO_BC_Save_Trace _bit10 -#define AO_UI_Switch_Load_On_BC_TC _bit9 -#define AO_UI_Switch_Load_On_Stop _bit8 -#define AO_UI_Switch_Load_On_TC _bit7 -#define AO_UC_Switch_Load_On_BC_TC _bit6 -#define AO_UC_Switch_Load_On_TC _bit5 -#define AO_BC_Switch_Load_On_TC _bit4 -#define AO_Mute_B _bit3 -#define AO_Mute_A _bit2 -#define AO_UPDATE2_Pulse _bit1 -#define AO_START1_Pulse _bit0 - -#define AO_Status_2_Register 6 - -#define DIO_Parallel_Input_Register 7 - -#define AI_Command_1_Register 8 -#define AI_Analog_Trigger_Reset _bit14 -#define AI_Disarm _bit13 -#define AI_SI2_Arm _bit12 -#define AI_SI2_Load _bit11 -#define AI_SI_Arm _bit10 -#define AI_SI_Load _bit9 -#define AI_DIV_Arm _bit8 -#define AI_DIV_Load _bit7 -#define AI_SC_Arm _bit6 -#define AI_SC_Load _bit5 -#define AI_SCAN_IN_PROG_Pulse _bit4 -#define AI_EXTMUX_CLK_Pulse _bit3 -#define AI_LOCALMUX_CLK_Pulse _bit2 -#define AI_SC_TC_Pulse _bit1 -#define AI_CONVERT_Pulse _bit0 - -#define AO_Command_1_Register 9 -#define AO_Analog_Trigger_Reset _bit15 -#define AO_START_Pulse _bit14 -#define AO_Disarm _bit13 -#define AO_UI2_Arm_Disarm _bit12 -#define AO_UI2_Load _bit11 -#define AO_UI_Arm _bit10 -#define AO_UI_Load _bit9 -#define AO_UC_Arm _bit8 -#define AO_UC_Load _bit7 -#define AO_BC_Arm _bit6 -#define AO_BC_Load _bit5 -#define AO_DAC1_Update_Mode _bit4 -#define AO_LDAC1_Source_Select _bit3 -#define AO_DAC0_Update_Mode _bit2 -#define AO_LDAC0_Source_Select _bit1 -#define AO_UPDATE_Pulse _bit0 - -#define DIO_Output_Register 10 -#define DIO_Parallel_Data_Out(a) ((a)&0xff) -#define DIO_Parallel_Data_Mask 0xff -#define DIO_SDOUT _bit0 -#define DIO_SDIN _bit4 -#define DIO_Serial_Data_Out(a) (((a)&0xff)<<8) -#define DIO_Serial_Data_Mask 0xff00 - -#define DIO_Control_Register 11 -#define DIO_Software_Serial_Control _bit11 -#define DIO_HW_Serial_Timebase _bit10 -#define DIO_HW_Serial_Enable _bit9 -#define DIO_HW_Serial_Start _bit8 -#define DIO_Pins_Dir(a) ((a)&0xff) -#define DIO_Pins_Dir_Mask 0xff - -#define AI_Mode_1_Register 12 -#define AI_CONVERT_Source_Select(a) (((a) & 0x1f) << 11) -#define AI_SI_Source_select(a) (((a) & 0x1f) << 6) -#define AI_CONVERT_Source_Polarity _bit5 -#define AI_SI_Source_Polarity _bit4 -#define AI_Start_Stop _bit3 -#define AI_Mode_1_Reserved _bit2 -#define AI_Continuous _bit1 -#define AI_Trigger_Once _bit0 - -#define AI_Mode_2_Register 13 -#define AI_SC_Gate_Enable _bit15 -#define AI_Start_Stop_Gate_Enable _bit14 -#define AI_Pre_Trigger _bit13 -#define AI_External_MUX_Present _bit12 -#define AI_SI2_Initial_Load_Source _bit9 -#define AI_SI2_Reload_Mode _bit8 -#define AI_SI_Initial_Load_Source _bit7 -#define AI_SI_Reload_Mode(a) (((a) & 0x7)<<4) -#define AI_SI_Write_Switch _bit3 -#define AI_SC_Initial_Load_Source _bit2 -#define AI_SC_Reload_Mode _bit1 -#define AI_SC_Write_Switch _bit0 - -#define AI_SI_Load_A_Registers 14 -#define AI_SI_Load_B_Registers 16 -#define AI_SC_Load_A_Registers 18 -#define AI_SC_Load_B_Registers 20 -#define AI_SI_Save_Registers 64 -#define AI_SC_Save_Registers 66 - -#define AI_SI2_Load_A_Register 23 -#define AI_SI2_Load_B_Register 25 - -#define Joint_Status_1_Register 27 -#define DIO_Serial_IO_In_Progress_St _bit12 - -#define DIO_Serial_Input_Register 28 -#define Joint_Status_2_Register 29 -enum Joint_Status_2_Bits { - AO_TMRDACWRs_In_Progress_St = 0x20, -}; - -#define AO_Mode_1_Register 38 -#define AO_UPDATE_Source_Select(x) (((x)&0x1f)<<11) -#define AO_UI_Source_Select(x) (((x)&0x1f)<<6) -#define AO_Multiple_Channels _bit5 -#define AO_UPDATE_Source_Polarity _bit4 -#define AO_UI_Source_Polarity _bit3 -#define AO_UC_Switch_Load_Every_TC _bit2 -#define AO_Continuous _bit1 -#define AO_Trigger_Once _bit0 - -#define AO_Mode_2_Register 39 -#define AO_FIFO_Mode_Mask (0x3 << 14) -enum AO_FIFO_Mode_Bits { - AO_FIFO_Mode_HF_to_F = (3 << 14), - AO_FIFO_Mode_F = (2 << 14), - AO_FIFO_Mode_HF = (1 << 14), - AO_FIFO_Mode_E = (0 << 14), -}; -#define AO_FIFO_Retransmit_Enable _bit13 -#define AO_START1_Disable _bit12 -#define AO_UC_Initial_Load_Source _bit11 -#define AO_UC_Write_Switch _bit10 -#define AO_UI2_Initial_Load_Source _bit9 -#define AO_UI2_Reload_Mode _bit8 -#define AO_UI_Initial_Load_Source _bit7 -#define AO_UI_Reload_Mode(x) (((x) & 0x7) << 4) -#define AO_UI_Write_Switch _bit3 -#define AO_BC_Initial_Load_Source _bit2 -#define AO_BC_Reload_Mode _bit1 -#define AO_BC_Write_Switch _bit0 - -#define AO_UI_Load_A_Register 40 -#define AO_UI_Load_A_Register_High 40 -#define AO_UI_Load_A_Register_Low 41 -#define AO_UI_Load_B_Register 42 -#define AO_UI_Save_Registers 16 -#define AO_BC_Load_A_Register 44 -#define AO_BC_Load_A_Register_High 44 -#define AO_BC_Load_A_Register_Low 45 -#define AO_BC_Load_B_Register 46 -#define AO_BC_Load_B_Register_High 46 -#define AO_BC_Load_B_Register_Low 47 -#define AO_BC_Save_Registers 18 -#define AO_UC_Load_A_Register 48 -#define AO_UC_Load_A_Register_High 48 -#define AO_UC_Load_A_Register_Low 49 -#define AO_UC_Load_B_Register 50 -#define AO_UC_Save_Registers 20 - -#define Clock_and_FOUT_Register 56 -enum Clock_and_FOUT_bits { - FOUT_Enable = _bit15, - FOUT_Timebase_Select = _bit14, - DIO_Serial_Out_Divide_By_2 = _bit13, - Slow_Internal_Time_Divide_By_2 = _bit12, - Slow_Internal_Timebase = _bit11, - G_Source_Divide_By_2 = _bit10, - Clock_To_Board_Divide_By_2 = _bit9, - Clock_To_Board = _bit8, - AI_Output_Divide_By_2 = _bit7, - AI_Source_Divide_By_2 = _bit6, - AO_Output_Divide_By_2 = _bit5, - AO_Source_Divide_By_2 = _bit4, - FOUT_Divider_mask = 0xf -}; -static inline unsigned FOUT_Divider(unsigned divider) -{ - return divider & FOUT_Divider_mask; -} - -#define IO_Bidirection_Pin_Register 57 -#define RTSI_Trig_Direction_Register 58 -enum RTSI_Trig_Direction_Bits { - Drive_RTSI_Clock_Bit = 0x1, - Use_RTSI_Clock_Bit = 0x2, -}; -static inline unsigned RTSI_Output_Bit(unsigned channel, int is_mseries) -{ - unsigned max_channel; - unsigned base_bit_shift; - if (is_mseries) { - base_bit_shift = 8; - max_channel = 7; - } else { - base_bit_shift = 9; - max_channel = 6; - } - if (channel > max_channel) { - pr_err("%s: bug, invalid RTSI_channel=%i\n", __func__, channel); - return 0; - } - return 1 << (base_bit_shift + channel); -} - -#define Interrupt_Control_Register 59 -#define Interrupt_B_Enable _bit15 -#define Interrupt_B_Output_Select(x) ((x)<<12) -#define Interrupt_A_Enable _bit11 -#define Interrupt_A_Output_Select(x) ((x)<<8) -#define Pass_Thru_0_Interrupt_Polarity _bit3 -#define Pass_Thru_1_Interrupt_Polarity _bit2 -#define Interrupt_Output_On_3_Pins _bit1 -#define Interrupt_Output_Polarity _bit0 - -#define AI_Output_Control_Register 60 -#define AI_START_Output_Select _bit10 -#define AI_SCAN_IN_PROG_Output_Select(x) (((x) & 0x3) << 8) -#define AI_EXTMUX_CLK_Output_Select(x) (((x) & 0x3) << 6) -#define AI_LOCALMUX_CLK_Output_Select(x) ((x)<<4) -#define AI_SC_TC_Output_Select(x) ((x)<<2) -enum ai_convert_output_selection { - AI_CONVERT_Output_High_Z = 0, - AI_CONVERT_Output_Ground = 1, - AI_CONVERT_Output_Enable_Low = 2, - AI_CONVERT_Output_Enable_High = 3 -}; -static unsigned AI_CONVERT_Output_Select(enum ai_convert_output_selection - selection) -{ - return selection & 0x3; -} - -#define AI_START_STOP_Select_Register 62 -#define AI_START_Polarity _bit15 -#define AI_STOP_Polarity _bit14 -#define AI_STOP_Sync _bit13 -#define AI_STOP_Edge _bit12 -#define AI_STOP_Select(a) (((a) & 0x1f)<<7) -#define AI_START_Sync _bit6 -#define AI_START_Edge _bit5 -#define AI_START_Select(a) ((a) & 0x1f) - -#define AI_Trigger_Select_Register 63 -#define AI_START1_Polarity _bit15 -#define AI_START2_Polarity _bit14 -#define AI_START2_Sync _bit13 -#define AI_START2_Edge _bit12 -#define AI_START2_Select(a) (((a) & 0x1f) << 7) -#define AI_START1_Sync _bit6 -#define AI_START1_Edge _bit5 -#define AI_START1_Select(a) ((a) & 0x1f) - -#define AI_DIV_Load_A_Register 64 - -#define AO_Start_Select_Register 66 -#define AO_UI2_Software_Gate _bit15 -#define AO_UI2_External_Gate_Polarity _bit14 -#define AO_START_Polarity _bit13 -#define AO_AOFREQ_Enable _bit12 -#define AO_UI2_External_Gate_Select(a) (((a) & 0x1f) << 7) -#define AO_START_Sync _bit6 -#define AO_START_Edge _bit5 -#define AO_START_Select(a) ((a) & 0x1f) - -#define AO_Trigger_Select_Register 67 -#define AO_UI2_External_Gate_Enable _bit15 -#define AO_Delayed_START1 _bit14 -#define AO_START1_Polarity _bit13 -#define AO_UI2_Source_Polarity _bit12 -#define AO_UI2_Source_Select(x) (((x)&0x1f)<<7) -#define AO_START1_Sync _bit6 -#define AO_START1_Edge _bit5 -#define AO_START1_Select(x) (((x)&0x1f)<<0) - -#define AO_Mode_3_Register 70 -#define AO_UI2_Switch_Load_Next_TC _bit13 -#define AO_UC_Switch_Load_Every_BC_TC _bit12 -#define AO_Trigger_Length _bit11 -#define AO_Stop_On_Overrun_Error _bit5 -#define AO_Stop_On_BC_TC_Trigger_Error _bit4 -#define AO_Stop_On_BC_TC_Error _bit3 -#define AO_Not_An_UPDATE _bit2 -#define AO_Software_Gate _bit1 -#define AO_Last_Gate_Disable _bit0 /* M Series only */ - -#define Joint_Reset_Register 72 -#define Software_Reset _bit11 -#define AO_Configuration_End _bit9 -#define AI_Configuration_End _bit8 -#define AO_Configuration_Start _bit5 -#define AI_Configuration_Start _bit4 -#define G1_Reset _bit3 -#define G0_Reset _bit2 -#define AO_Reset _bit1 -#define AI_Reset _bit0 - -#define Interrupt_A_Enable_Register 73 -#define Pass_Thru_0_Interrupt_Enable _bit9 -#define G0_Gate_Interrupt_Enable _bit8 -#define AI_FIFO_Interrupt_Enable _bit7 -#define G0_TC_Interrupt_Enable _bit6 -#define AI_Error_Interrupt_Enable _bit5 -#define AI_STOP_Interrupt_Enable _bit4 -#define AI_START_Interrupt_Enable _bit3 -#define AI_START2_Interrupt_Enable _bit2 -#define AI_START1_Interrupt_Enable _bit1 -#define AI_SC_TC_Interrupt_Enable _bit0 - -#define Interrupt_B_Enable_Register 75 -#define Pass_Thru_1_Interrupt_Enable _bit11 -#define G1_Gate_Interrupt_Enable _bit10 -#define G1_TC_Interrupt_Enable _bit9 -#define AO_FIFO_Interrupt_Enable _bit8 -#define AO_UI2_TC_Interrupt_Enable _bit7 -#define AO_UC_TC_Interrupt_Enable _bit6 -#define AO_Error_Interrupt_Enable _bit5 -#define AO_STOP_Interrupt_Enable _bit4 -#define AO_START_Interrupt_Enable _bit3 -#define AO_UPDATE_Interrupt_Enable _bit2 -#define AO_START1_Interrupt_Enable _bit1 -#define AO_BC_TC_Interrupt_Enable _bit0 - -#define Second_IRQ_A_Enable_Register 74 -enum Second_IRQ_A_Enable_Bits { - AI_SC_TC_Second_Irq_Enable = _bit0, - AI_START1_Second_Irq_Enable = _bit1, - AI_START2_Second_Irq_Enable = _bit2, - AI_START_Second_Irq_Enable = _bit3, - AI_STOP_Second_Irq_Enable = _bit4, - AI_Error_Second_Irq_Enable = _bit5, - G0_TC_Second_Irq_Enable = _bit6, - AI_FIFO_Second_Irq_Enable = _bit7, - G0_Gate_Second_Irq_Enable = _bit8, - Pass_Thru_0_Second_Irq_Enable = _bit9 -}; +/* + * Registers in the National Instruments DAQ-STC chip + */ + +#define NISTC_INTA_ACK_REG 2 +#define NISTC_INTA_ACK_G0_GATE BIT(15) +#define NISTC_INTA_ACK_G0_TC BIT(14) +#define NISTC_INTA_ACK_AI_ERR BIT(13) +#define NISTC_INTA_ACK_AI_STOP BIT(12) +#define NISTC_INTA_ACK_AI_START BIT(11) +#define NISTC_INTA_ACK_AI_START2 BIT(10) +#define NISTC_INTA_ACK_AI_START1 BIT(9) +#define NISTC_INTA_ACK_AI_SC_TC BIT(8) +#define NISTC_INTA_ACK_AI_SC_TC_ERR BIT(7) +#define NISTC_INTA_ACK_G0_TC_ERR BIT(6) +#define NISTC_INTA_ACK_G0_GATE_ERR BIT(5) +#define NISTC_INTA_ACK_AI_ALL (NISTC_INTA_ACK_AI_ERR | \ + NISTC_INTA_ACK_AI_STOP | \ + NISTC_INTA_ACK_AI_START | \ + NISTC_INTA_ACK_AI_START2 | \ + NISTC_INTA_ACK_AI_START1 | \ + NISTC_INTA_ACK_AI_SC_TC | \ + NISTC_INTA_ACK_AI_SC_TC_ERR) + +#define NISTC_INTB_ACK_REG 3 +#define NISTC_INTB_ACK_G1_GATE BIT(15) +#define NISTC_INTB_ACK_G1_TC BIT(14) +#define NISTC_INTB_ACK_AO_ERR BIT(13) +#define NISTC_INTB_ACK_AO_STOP BIT(12) +#define NISTC_INTB_ACK_AO_START BIT(11) +#define NISTC_INTB_ACK_AO_UPDATE BIT(10) +#define NISTC_INTB_ACK_AO_START1 BIT(9) +#define NISTC_INTB_ACK_AO_BC_TC BIT(8) +#define NISTC_INTB_ACK_AO_UC_TC BIT(7) +#define NISTC_INTB_ACK_AO_UI2_TC BIT(6) +#define NISTC_INTB_ACK_AO_UI2_TC_ERR BIT(5) +#define NISTC_INTB_ACK_AO_BC_TC_ERR BIT(4) +#define NISTC_INTB_ACK_AO_BC_TC_TRIG_ERR BIT(3) +#define NISTC_INTB_ACK_G1_TC_ERR BIT(2) +#define NISTC_INTB_ACK_G1_GATE_ERR BIT(1) +#define NISTC_INTB_ACK_AO_ALL (NISTC_INTB_ACK_AO_ERR | \ + NISTC_INTB_ACK_AO_STOP | \ + NISTC_INTB_ACK_AO_START | \ + NISTC_INTB_ACK_AO_UPDATE | \ + NISTC_INTB_ACK_AO_START1 | \ + NISTC_INTB_ACK_AO_BC_TC | \ + NISTC_INTB_ACK_AO_UC_TC | \ + NISTC_INTB_ACK_AO_BC_TC_ERR | \ + NISTC_INTB_ACK_AO_BC_TC_TRIG_ERR) + +#define NISTC_AI_CMD2_REG 4 +#define NISTC_AI_CMD2_END_ON_SC_TC BIT(15) +#define NISTC_AI_CMD2_END_ON_EOS BIT(14) +#define NISTC_AI_CMD2_START1_DISABLE BIT(11) +#define NISTC_AI_CMD2_SC_SAVE_TRACE BIT(10) +#define NISTC_AI_CMD2_SI_SW_ON_SC_TC BIT(9) +#define NISTC_AI_CMD2_SI_SW_ON_STOP BIT(8) +#define NISTC_AI_CMD2_SI_SW_ON_TC BIT(7) +#define NISTC_AI_CMD2_SC_SW_ON_TC BIT(4) +#define NISTC_AI_CMD2_STOP_PULSE BIT(3) +#define NISTC_AI_CMD2_START_PULSE BIT(2) +#define NISTC_AI_CMD2_START2_PULSE BIT(1) +#define NISTC_AI_CMD2_START1_PULSE BIT(0) + +#define NISTC_AO_CMD2_REG 5 +#define NISTC_AO_CMD2_END_ON_BC_TC(x) (((x) & 0x3) << 14) +#define NISTC_AO_CMD2_START_STOP_GATE_ENA BIT(13) +#define NISTC_AO_CMD2_UC_SAVE_TRACE BIT(12) +#define NISTC_AO_CMD2_BC_GATE_ENA BIT(11) +#define NISTC_AO_CMD2_BC_SAVE_TRACE BIT(10) +#define NISTC_AO_CMD2_UI_SW_ON_BC_TC BIT(9) +#define NISTC_AO_CMD2_UI_SW_ON_STOP BIT(8) +#define NISTC_AO_CMD2_UI_SW_ON_TC BIT(7) +#define NISTC_AO_CMD2_UC_SW_ON_BC_TC BIT(6) +#define NISTC_AO_CMD2_UC_SW_ON_TC BIT(5) +#define NISTC_AO_CMD2_BC_SW_ON_TC BIT(4) +#define NISTC_AO_CMD2_MUTE_B BIT(3) +#define NISTC_AO_CMD2_MUTE_A BIT(2) +#define NISTC_AO_CMD2_UPDATE2_PULSE BIT(1) +#define NISTC_AO_CMD2_START1_PULSE BIT(0) + +#define NISTC_G0_CMD_REG 6 +#define NISTC_G1_CMD_REG 7 + +#define NISTC_AI_CMD1_REG 8 +#define NISTC_AI_CMD1_ATRIG_RESET BIT(14) +#define NISTC_AI_CMD1_DISARM BIT(13) +#define NISTC_AI_CMD1_SI2_ARM BIT(12) +#define NISTC_AI_CMD1_SI2_LOAD BIT(11) +#define NISTC_AI_CMD1_SI_ARM BIT(10) +#define NISTC_AI_CMD1_SI_LOAD BIT(9) +#define NISTC_AI_CMD1_DIV_ARM BIT(8) +#define NISTC_AI_CMD1_DIV_LOAD BIT(7) +#define NISTC_AI_CMD1_SC_ARM BIT(6) +#define NISTC_AI_CMD1_SC_LOAD BIT(5) +#define NISTC_AI_CMD1_SCAN_IN_PROG_PULSE BIT(4) +#define NISTC_AI_CMD1_EXTMUX_CLK_PULSE BIT(3) +#define NISTC_AI_CMD1_LOCALMUX_CLK_PULSE BIT(2) +#define NISTC_AI_CMD1_SC_TC_PULSE BIT(1) +#define NISTC_AI_CMD1_CONVERT_PULSE BIT(0) + +#define NISTC_AO_CMD1_REG 9 +#define NISTC_AO_CMD1_ATRIG_RESET BIT(15) +#define NISTC_AO_CMD1_START_PULSE BIT(14) +#define NISTC_AO_CMD1_DISARM BIT(13) +#define NISTC_AO_CMD1_UI2_ARM_DISARM BIT(12) +#define NISTC_AO_CMD1_UI2_LOAD BIT(11) +#define NISTC_AO_CMD1_UI_ARM BIT(10) +#define NISTC_AO_CMD1_UI_LOAD BIT(9) +#define NISTC_AO_CMD1_UC_ARM BIT(8) +#define NISTC_AO_CMD1_UC_LOAD BIT(7) +#define NISTC_AO_CMD1_BC_ARM BIT(6) +#define NISTC_AO_CMD1_BC_LOAD BIT(5) +#define NISTC_AO_CMD1_DAC1_UPDATE_MODE BIT(4) +#define NISTC_AO_CMD1_LDAC1_SRC_SEL BIT(3) +#define NISTC_AO_CMD1_DAC0_UPDATE_MODE BIT(2) +#define NISTC_AO_CMD1_LDAC0_SRC_SEL BIT(1) +#define NISTC_AO_CMD1_UPDATE_PULSE BIT(0) + +#define NISTC_DIO_OUT_REG 10 +#define NISTC_DIO_OUT_SERIAL(x) (((x) & 0xff) << 8) +#define NISTC_DIO_OUT_SERIAL_MASK NISTC_DIO_OUT_SERIAL(0xff) +#define NISTC_DIO_OUT_PARALLEL(x) ((x) & 0xff) +#define NISTC_DIO_OUT_PARALLEL_MASK NISTC_DIO_OUT_PARALLEL(0xff) +#define NISTC_DIO_SDIN BIT(4) +#define NISTC_DIO_SDOUT BIT(0) + +#define NISTC_DIO_CTRL_REG 11 +#define NISTC_DIO_SDCLK BIT(11) +#define NISTC_DIO_CTRL_HW_SER_TIMEBASE BIT(10) +#define NISTC_DIO_CTRL_HW_SER_ENA BIT(9) +#define NISTC_DIO_CTRL_HW_SER_START BIT(8) +#define NISTC_DIO_CTRL_DIR(x) ((x) & 0xff) +#define NISTC_DIO_CTRL_DIR_MASK NISTC_DIO_CTRL_DIR(0xff) + +#define NISTC_AI_MODE1_REG 12 +#define NISTC_AI_MODE1_CONVERT_SRC(x) (((x) & 0x1f) << 11) +#define NISTC_AI_MODE1_SI_SRC(x) (((x) & 0x1f) << 6) +#define NISTC_AI_MODE1_CONVERT_POLARITY BIT(5) +#define NISTC_AI_MODE1_SI_POLARITY BIT(4) +#define NISTC_AI_MODE1_START_STOP BIT(3) +#define NISTC_AI_MODE1_RSVD BIT(2) +#define NISTC_AI_MODE1_CONTINUOUS BIT(1) +#define NISTC_AI_MODE1_TRIGGER_ONCE BIT(0) + +#define NISTC_AI_MODE2_REG 13 +#define NISTC_AI_MODE2_SC_GATE_ENA BIT(15) +#define NISTC_AI_MODE2_START_STOP_GATE_ENA BIT(14) +#define NISTC_AI_MODE2_PRE_TRIGGER BIT(13) +#define NISTC_AI_MODE2_EXTMUX_PRESENT BIT(12) +#define NISTC_AI_MODE2_SI2_INIT_LOAD_SRC BIT(9) +#define NISTC_AI_MODE2_SI2_RELOAD_MODE BIT(8) +#define NISTC_AI_MODE2_SI_INIT_LOAD_SRC BIT(7) +#define NISTC_AI_MODE2_SI_RELOAD_MODE(x) (((x) & 0x7) << 4) +#define NISTC_AI_MODE2_SI_WR_SWITCH BIT(3) +#define NISTC_AI_MODE2_SC_INIT_LOAD_SRC BIT(2) +#define NISTC_AI_MODE2_SC_RELOAD_MODE BIT(1) +#define NISTC_AI_MODE2_SC_WR_SWITCH BIT(0) + +#define NISTC_AI_SI_LOADA_REG 14 +#define NISTC_AI_SI_LOADB_REG 16 +#define NISTC_AI_SC_LOADA_REG 18 +#define NISTC_AI_SC_LOADB_REG 20 +#define NISTC_AI_SI2_LOADA_REG 23 +#define NISTC_AI_SI2_LOADB_REG 25 + +#define NISTC_G0_MODE_REG 26 +#define NISTC_G1_MODE_REG 27 +#define NISTC_G0_LOADA_REG 28 +#define NISTC_G0_LOADB_REG 30 +#define NISTC_G1_LOADA_REG 32 +#define NISTC_G1_LOADB_REG 34 +#define NISTC_G0_INPUT_SEL_REG 36 +#define NISTC_G1_INPUT_SEL_REG 37 + +#define NISTC_AO_MODE1_REG 38 +#define NISTC_AO_MODE1_UPDATE_SRC(x) (((x) & 0x1f) << 11) +#define NISTC_AO_MODE1_UPDATE_SRC_MASK NISTC_AO_MODE1_UPDATE_SRC(0x1f) +#define NISTC_AO_MODE1_UI_SRC(x) (((x) & 0x1f) << 6) +#define NISTC_AO_MODE1_UI_SRC_MASK NISTC_AO_MODE1_UI_SRC(0x1f) +#define NISTC_AO_MODE1_MULTI_CHAN BIT(5) +#define NISTC_AO_MODE1_UPDATE_SRC_POLARITY BIT(4) +#define NISTC_AO_MODE1_UI_SRC_POLARITY BIT(3) +#define NISTC_AO_MODE1_UC_SW_EVERY_TC BIT(2) +#define NISTC_AO_MODE1_CONTINUOUS BIT(1) +#define NISTC_AO_MODE1_TRIGGER_ONCE BIT(0) + +#define NISTC_AO_MODE2_REG 39 +#define NISTC_AO_MODE2_FIFO_MODE(x) (((x) & 0x3) << 14) +#define NISTC_AO_MODE2_FIFO_MODE_MASK NISTC_AO_MODE2_FIFO_MODE(3) +#define NISTC_AO_MODE2_FIFO_MODE_E NISTC_AO_MODE2_FIFO_MODE(0) +#define NISTC_AO_MODE2_FIFO_MODE_HF NISTC_AO_MODE2_FIFO_MODE(1) +#define NISTC_AO_MODE2_FIFO_MODE_F NISTC_AO_MODE2_FIFO_MODE(2) +#define NISTC_AO_MODE2_FIFO_MODE_HF_F NISTC_AO_MODE2_FIFO_MODE(3) +#define NISTC_AO_MODE2_FIFO_REXMIT_ENA BIT(13) +#define NISTC_AO_MODE2_START1_DISABLE BIT(12) +#define NISTC_AO_MODE2_UC_INIT_LOAD_SRC BIT(11) +#define NISTC_AO_MODE2_UC_WR_SWITCH BIT(10) +#define NISTC_AO_MODE2_UI2_INIT_LOAD_SRC BIT(9) +#define NISTC_AO_MODE2_UI2_RELOAD_MODE BIT(8) +#define NISTC_AO_MODE2_UI_INIT_LOAD_SRC BIT(7) +#define NISTC_AO_MODE2_UI_RELOAD_MODE(x) (((x) & 0x7) << 4) +#define NISTC_AO_MODE2_UI_WR_SWITCH BIT(3) +#define NISTC_AO_MODE2_BC_INIT_LOAD_SRC BIT(2) +#define NISTC_AO_MODE2_BC_RELOAD_MODE BIT(1) +#define NISTC_AO_MODE2_BC_WR_SWITCH BIT(0) + +#define NISTC_AO_UI_LOADA_REG 40 +#define NISTC_AO_UI_LOADB_REG 42 +#define NISTC_AO_BC_LOADA_REG 44 +#define NISTC_AO_BC_LOADB_REG 46 +#define NISTC_AO_UC_LOADA_REG 48 +#define NISTC_AO_UC_LOADB_REG 50 + +#define NISTC_CLK_FOUT_REG 56 +#define NISTC_CLK_FOUT_ENA BIT(15) +#define NISTC_CLK_FOUT_TIMEBASE_SEL BIT(14) +#define NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 BIT(13) +#define NISTC_CLK_FOUT_SLOW_DIV2 BIT(12) +#define NISTC_CLK_FOUT_SLOW_TIMEBASE BIT(11) +#define NISTC_CLK_FOUT_G_SRC_DIV2 BIT(10) +#define NISTC_CLK_FOUT_TO_BOARD_DIV2 BIT(9) +#define NISTC_CLK_FOUT_TO_BOARD BIT(8) +#define NISTC_CLK_FOUT_AI_OUT_DIV2 BIT(7) +#define NISTC_CLK_FOUT_AI_SRC_DIV2 BIT(6) +#define NISTC_CLK_FOUT_AO_OUT_DIV2 BIT(5) +#define NISTC_CLK_FOUT_AO_SRC_DIV2 BIT(4) +#define NISTC_CLK_FOUT_DIVIDER(x) (((x) & 0xf) << 0) +#define NISTC_CLK_FOUT_TO_DIVIDER(x) (((x) >> 0) & 0xf) +#define NISTC_CLK_FOUT_DIVIDER_MASK NISTC_CLK_FOUT_DIVIDER(0xf) + +#define NISTC_IO_BIDIR_PIN_REG 57 + +#define NISTC_RTSI_TRIG_DIR_REG 58 +#define NISTC_RTSI_TRIG_OLD_CLK_CHAN 7 +#define NISTC_RTSI_TRIG_NUM_CHAN(_m) ((_m) ? 8 : 7) +#define NISTC_RTSI_TRIG_DIR(_c, _m) ((_m) ? BIT(8 + (_c)) : BIT(7 + (_c))) +#define NISTC_RTSI_TRIG_USE_CLK BIT(1) +#define NISTC_RTSI_TRIG_DRV_CLK BIT(0) + +#define NISTC_INT_CTRL_REG 59 +#define NISTC_INT_CTRL_INTB_ENA BIT(15) +#define NISTC_INT_CTRL_INTB_SEL(x) (((x) & 0x7) << 12) +#define NISTC_INT_CTRL_INTA_ENA BIT(11) +#define NISTC_INT_CTRL_INTA_SEL(x) (((x) & 0x7) << 8) +#define NISTC_INT_CTRL_PASSTHRU0_POL BIT(3) +#define NISTC_INT_CTRL_PASSTHRU1_POL BIT(2) +#define NISTC_INT_CTRL_3PIN_INT BIT(1) +#define NISTC_INT_CTRL_INT_POL BIT(0) + +#define NISTC_AI_OUT_CTRL_REG 60 +#define NISTC_AI_OUT_CTRL_START_SEL BIT(10) +#define NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(x) (((x) & 0x3) << 8) +#define NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(x) (((x) & 0x3) << 6) +#define NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(x) (((x) & 0x3) << 4) +#define NISTC_AI_OUT_CTRL_SC_TC_SEL(x) (((x) & 0x3) << 2) +#define NISTC_AI_OUT_CTRL_CONVERT_SEL(x) (((x) & 0x3) << 0) +#define NISTC_AI_OUT_CTRL_CONVERT_HIGH_Z NISTC_AI_OUT_CTRL_CONVERT_SEL(0) +#define NISTC_AI_OUT_CTRL_CONVERT_GND NISTC_AI_OUT_CTRL_CONVERT_SEL(1) +#define NISTC_AI_OUT_CTRL_CONVERT_LOW NISTC_AI_OUT_CTRL_CONVERT_SEL(2) +#define NISTC_AI_OUT_CTRL_CONVERT_HIGH NISTC_AI_OUT_CTRL_CONVERT_SEL(3) + +#define NISTC_ATRIG_ETC_REG 61 +#define NISTC_ATRIG_ETC_GPFO_1_ENA BIT(15) +#define NISTC_ATRIG_ETC_GPFO_0_ENA BIT(14) +#define NISTC_ATRIG_ETC_GPFO_0_SEL(x) (((x) & 0x3) << 11) +#define NISTC_ATRIG_ETC_GPFO_1_SEL BIT(7) +#define NISTC_ATRIG_ETC_DRV BIT(4) +#define NISTC_ATRIG_ETC_ENA BIT(3) +#define NISTC_ATRIG_ETC_MODE(x) (((x) & 0x7) << 0) + +#define NISTC_AI_START_STOP_REG 62 +#define NISTC_AI_START_POLARITY BIT(15) +#define NISTC_AI_STOP_POLARITY BIT(14) +#define NISTC_AI_STOP_SYNC BIT(13) +#define NISTC_AI_STOP_EDGE BIT(12) +#define NISTC_AI_STOP_SEL(x) (((x) & 0x1f) << 7) +#define NISTC_AI_START_SYNC BIT(6) +#define NISTC_AI_START_EDGE BIT(5) +#define NISTC_AI_START_SEL(x) (((x) & 0x1f) << 0) + +#define NISTC_AI_TRIG_SEL_REG 63 +#define NISTC_AI_TRIG_START1_POLARITY BIT(15) +#define NISTC_AI_TRIG_START2_POLARITY BIT(14) +#define NISTC_AI_TRIG_START2_SYNC BIT(13) +#define NISTC_AI_TRIG_START2_EDGE BIT(12) +#define NISTC_AI_TRIG_START2_SEL(x) (((x) & 0x1f) << 7) +#define NISTC_AI_TRIG_START1_SYNC BIT(6) +#define NISTC_AI_TRIG_START1_EDGE BIT(5) +#define NISTC_AI_TRIG_START1_SEL(x) (((x) & 0x1f) << 0) + +#define NISTC_AI_DIV_LOADA_REG 64 + +#define NISTC_AO_START_SEL_REG 66 +#define NISTC_AO_START_UI2_SW_GATE BIT(15) +#define NISTC_AO_START_UI2_EXT_GATE_POL BIT(14) +#define NISTC_AO_START_POLARITY BIT(13) +#define NISTC_AO_START_AOFREQ_ENA BIT(12) +#define NISTC_AO_START_UI2_EXT_GATE_SEL(x) (((x) & 0x1f) << 7) +#define NISTC_AO_START_SYNC BIT(6) +#define NISTC_AO_START_EDGE BIT(5) +#define NISTC_AO_START_SEL(x) (((x) & 0x1f) << 0) + +#define NISTC_AO_TRIG_SEL_REG 67 +#define NISTC_AO_TRIG_UI2_EXT_GATE_ENA BIT(15) +#define NISTC_AO_TRIG_DELAYED_START1 BIT(14) +#define NISTC_AO_TRIG_START1_POLARITY BIT(13) +#define NISTC_AO_TRIG_UI2_SRC_POLARITY BIT(12) +#define NISTC_AO_TRIG_UI2_SRC_SEL(x) (((x) & 0x1f) << 7) +#define NISTC_AO_TRIG_START1_SYNC BIT(6) +#define NISTC_AO_TRIG_START1_EDGE BIT(5) +#define NISTC_AO_TRIG_START1_SEL(x) (((x) & 0x1f) << 0) +#define NISTC_AO_TRIG_START1_SEL_MASK NISTC_AO_TRIG_START1_SEL(0x1f) + +#define NISTC_G0_AUTOINC_REG 68 +#define NISTC_G1_AUTOINC_REG 69 + +#define NISTC_AO_MODE3_REG 70 +#define NISTC_AO_MODE3_UI2_SW_NEXT_TC BIT(13) +#define NISTC_AO_MODE3_UC_SW_EVERY_BC_TC BIT(12) +#define NISTC_AO_MODE3_TRIG_LEN BIT(11) +#define NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR BIT(5) +#define NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR BIT(4) +#define NISTC_AO_MODE3_STOP_ON_BC_TC_ERR BIT(3) +#define NISTC_AO_MODE3_NOT_AN_UPDATE BIT(2) +#define NISTC_AO_MODE3_SW_GATE BIT(1) +#define NISTC_AO_MODE3_LAST_GATE_DISABLE BIT(0) /* M-Series only */ + +#define NISTC_RESET_REG 72 +#define NISTC_RESET_SOFTWARE BIT(11) +#define NISTC_RESET_AO_CFG_END BIT(9) +#define NISTC_RESET_AI_CFG_END BIT(8) +#define NISTC_RESET_AO_CFG_START BIT(5) +#define NISTC_RESET_AI_CFG_START BIT(4) +#define NISTC_RESET_G1 BIT(3) +#define NISTC_RESET_G0 BIT(2) +#define NISTC_RESET_AO BIT(1) +#define NISTC_RESET_AI BIT(0) + +#define NISTC_INTA_ENA_REG 73 +#define NISTC_INTA2_ENA_REG 74 +#define NISTC_INTA_ENA_PASSTHRU0 BIT(9) +#define NISTC_INTA_ENA_G0_GATE BIT(8) +#define NISTC_INTA_ENA_AI_FIFO BIT(7) +#define NISTC_INTA_ENA_G0_TC BIT(6) +#define NISTC_INTA_ENA_AI_ERR BIT(5) +#define NISTC_INTA_ENA_AI_STOP BIT(4) +#define NISTC_INTA_ENA_AI_START BIT(3) +#define NISTC_INTA_ENA_AI_START2 BIT(2) +#define NISTC_INTA_ENA_AI_START1 BIT(1) +#define NISTC_INTA_ENA_AI_SC_TC BIT(0) +#define NISTC_INTA_ENA_AI_MASK (NISTC_INTA_ENA_AI_FIFO | \ + NISTC_INTA_ENA_AI_ERR | \ + NISTC_INTA_ENA_AI_STOP | \ + NISTC_INTA_ENA_AI_START | \ + NISTC_INTA_ENA_AI_START2 | \ + NISTC_INTA_ENA_AI_START1 | \ + NISTC_INTA_ENA_AI_SC_TC) + +#define NISTC_INTB_ENA_REG 75 +#define NISTC_INTB2_ENA_REG 76 +#define NISTC_INTB_ENA_PASSTHRU1 BIT(11) +#define NISTC_INTB_ENA_G1_GATE BIT(10) +#define NISTC_INTB_ENA_G1_TC BIT(9) +#define NISTC_INTB_ENA_AO_FIFO BIT(8) +#define NISTC_INTB_ENA_AO_UI2_TC BIT(7) +#define NISTC_INTB_ENA_AO_UC_TC BIT(6) +#define NISTC_INTB_ENA_AO_ERR BIT(5) +#define NISTC_INTB_ENA_AO_STOP BIT(4) +#define NISTC_INTB_ENA_AO_START BIT(3) +#define NISTC_INTB_ENA_AO_UPDATE BIT(2) +#define NISTC_INTB_ENA_AO_START1 BIT(1) +#define NISTC_INTB_ENA_AO_BC_TC BIT(0) + +#define NISTC_AI_PERSONAL_REG 77 +#define NISTC_AI_PERSONAL_SHIFTIN_PW BIT(15) +#define NISTC_AI_PERSONAL_EOC_POLARITY BIT(14) +#define NISTC_AI_PERSONAL_SOC_POLARITY BIT(13) +#define NISTC_AI_PERSONAL_SHIFTIN_POL BIT(12) +#define NISTC_AI_PERSONAL_CONVERT_TIMEBASE BIT(11) +#define NISTC_AI_PERSONAL_CONVERT_PW BIT(10) +#define NISTC_AI_PERSONAL_CONVERT_ORIG_PULSE BIT(9) +#define NISTC_AI_PERSONAL_FIFO_FLAGS_POL BIT(8) +#define NISTC_AI_PERSONAL_OVERRUN_MODE BIT(7) +#define NISTC_AI_PERSONAL_EXTMUX_CLK_PW BIT(6) +#define NISTC_AI_PERSONAL_LOCALMUX_CLK_PW BIT(5) +#define NISTC_AI_PERSONAL_AIFREQ_POL BIT(4) + +#define NISTC_AO_PERSONAL_REG 78 +#define NISTC_AO_PERSONAL_MULTI_DACS BIT(15) /* M-Series only */ +#define NISTC_AO_PERSONAL_NUM_DAC BIT(14) /* 1:single; 0:dual */ +#define NISTC_AO_PERSONAL_FAST_CPU BIT(13) /* M-Series reserved */ +#define NISTC_AO_PERSONAL_TMRDACWR_PW BIT(12) +#define NISTC_AO_PERSONAL_FIFO_FLAGS_POL BIT(11) /* M-Series reserved */ +#define NISTC_AO_PERSONAL_FIFO_ENA BIT(10) +#define NISTC_AO_PERSONAL_AOFREQ_POL BIT(9) /* M-Series reserved */ +#define NISTC_AO_PERSONAL_DMA_PIO_CTRL BIT(8) /* M-Series reserved */ +#define NISTC_AO_PERSONAL_UPDATE_ORIG_PULSE BIT(7) +#define NISTC_AO_PERSONAL_UPDATE_TIMEBASE BIT(6) +#define NISTC_AO_PERSONAL_UPDATE_PW BIT(5) +#define NISTC_AO_PERSONAL_BC_SRC_SEL BIT(4) +#define NISTC_AO_PERSONAL_INTERVAL_BUFFER_MODE BIT(3) + +#define NISTC_RTSI_TRIGA_OUT_REG 79 +#define NISTC_RTSI_TRIGB_OUT_REG 80 +#define NISTC_RTSI_TRIGB_SUB_SEL1 BIT(15) /* not for M-Series */ +#define NISTC_RTSI_TRIG(_c, _s) (((_s) & 0xf) << (((_c) % 4) * 4)) +#define NISTC_RTSI_TRIG_MASK(_c) NISTC_RTSI_TRIG((_c), 0xf) +#define NISTC_RTSI_TRIG_TO_SRC(_c, _b) (((_b) >> (((_c) % 4) * 4)) & 0xf) + +#define NISTC_RTSI_BOARD_REG 81 + +#define NISTC_CFG_MEM_CLR_REG 82 +#define NISTC_ADC_FIFO_CLR_REG 83 +#define NISTC_DAC_FIFO_CLR_REG 84 +#define NISTC_WR_STROBE3_REG 85 + +#define NISTC_AO_OUT_CTRL_REG 86 +#define NISTC_AO_OUT_CTRL_EXT_GATE_ENA BIT(15) +#define NISTC_AO_OUT_CTRL_EXT_GATE_SEL(x) (((x) & 0x1f) << 10) +#define NISTC_AO_OUT_CTRL_CHANS(x) (((x) & 0xf) << 6) +#define NISTC_AO_OUT_CTRL_UPDATE2_SEL(x) (((x) & 0x3) << 4) +#define NISTC_AO_OUT_CTRL_EXT_GATE_POL BIT(3) +#define NISTC_AO_OUT_CTRL_UPDATE2_TOGGLE BIT(2) +#define NISTC_AO_OUT_CTRL_UPDATE_SEL(x) (((x) & 0x3) << 0) +#define NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ NISTC_AO_OUT_CTRL_UPDATE_SEL(0) +#define NISTC_AO_OUT_CTRL_UPDATE_SEL_GND NISTC_AO_OUT_CTRL_UPDATE_SEL(1) +#define NISTC_AO_OUT_CTRL_UPDATE_SEL_LOW NISTC_AO_OUT_CTRL_UPDATE_SEL(2) +#define NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGH NISTC_AO_OUT_CTRL_UPDATE_SEL(3) + +#define NISTC_AI_MODE3_REG 87 +#define NISTC_AI_MODE3_TRIG_LEN BIT(15) +#define NISTC_AI_MODE3_DELAY_START BIT(14) +#define NISTC_AI_MODE3_SOFTWARE_GATE BIT(13) +#define NISTC_AI_MODE3_SI_TRIG_DELAY BIT(12) +#define NISTC_AI_MODE3_SI2_SRC_SEL BIT(11) +#define NISTC_AI_MODE3_DELAYED_START2 BIT(10) +#define NISTC_AI_MODE3_DELAYED_START1 BIT(9) +#define NISTC_AI_MODE3_EXT_GATE_MODE BIT(8) +#define NISTC_AI_MODE3_FIFO_MODE(x) (((x) & 0x3) << 6) +#define NISTC_AI_MODE3_FIFO_MODE_NE NISTC_AI_MODE3_FIFO_MODE(0) +#define NISTC_AI_MODE3_FIFO_MODE_HF NISTC_AI_MODE3_FIFO_MODE(1) +#define NISTC_AI_MODE3_FIFO_MODE_F NISTC_AI_MODE3_FIFO_MODE(2) +#define NISTC_AI_MODE3_FIFO_MODE_HF_E NISTC_AI_MODE3_FIFO_MODE(3) +#define NISTC_AI_MODE3_EXT_GATE_POL BIT(5) +#define NISTC_AI_MODE3_EXT_GATE_SEL(x) (((x) & 0x1f) << 0) + +#define NISTC_AI_STATUS1_REG 2 +#define NISTC_AI_STATUS1_INTA BIT(15) +#define NISTC_AI_STATUS1_FIFO_F BIT(14) +#define NISTC_AI_STATUS1_FIFO_HF BIT(13) +#define NISTC_AI_STATUS1_FIFO_E BIT(12) +#define NISTC_AI_STATUS1_OVERRUN BIT(11) +#define NISTC_AI_STATUS1_OVERFLOW BIT(10) +#define NISTC_AI_STATUS1_SC_TC_ERR BIT(9) +#define NISTC_AI_STATUS1_OVER (NISTC_AI_STATUS1_OVERRUN | \ + NISTC_AI_STATUS1_OVERFLOW) +#define NISTC_AI_STATUS1_ERR (NISTC_AI_STATUS1_OVER | \ + NISTC_AI_STATUS1_SC_TC_ERR) +#define NISTC_AI_STATUS1_START2 BIT(8) +#define NISTC_AI_STATUS1_START1 BIT(7) +#define NISTC_AI_STATUS1_SC_TC BIT(6) +#define NISTC_AI_STATUS1_START BIT(5) +#define NISTC_AI_STATUS1_STOP BIT(4) +#define NISTC_AI_STATUS1_G0_TC BIT(3) +#define NISTC_AI_STATUS1_G0_GATE BIT(2) +#define NISTC_AI_STATUS1_FIFO_REQ BIT(1) +#define NISTC_AI_STATUS1_PASSTHRU0 BIT(0) + +#define NISTC_AO_STATUS1_REG 3 +#define NISTC_AO_STATUS1_INTB BIT(15) +#define NISTC_AO_STATUS1_FIFO_F BIT(14) +#define NISTC_AO_STATUS1_FIFO_HF BIT(13) +#define NISTC_AO_STATUS1_FIFO_E BIT(12) +#define NISTC_AO_STATUS1_BC_TC_ERR BIT(11) +#define NISTC_AO_STATUS1_START BIT(10) +#define NISTC_AO_STATUS1_OVERRUN BIT(9) +#define NISTC_AO_STATUS1_START1 BIT(8) +#define NISTC_AO_STATUS1_BC_TC BIT(7) +#define NISTC_AO_STATUS1_UC_TC BIT(6) +#define NISTC_AO_STATUS1_UPDATE BIT(5) +#define NISTC_AO_STATUS1_UI2_TC BIT(4) +#define NISTC_AO_STATUS1_G1_TC BIT(3) +#define NISTC_AO_STATUS1_G1_GATE BIT(2) +#define NISTC_AO_STATUS1_FIFO_REQ BIT(1) +#define NISTC_AO_STATUS1_PASSTHRU1 BIT(0) + +#define NISTC_G01_STATUS_REG 4 + +#define NISTC_AI_STATUS2_REG 5 + +#define NISTC_AO_STATUS2_REG 6 + +#define NISTC_DIO_IN_REG 7 + +#define NISTC_G0_HW_SAVE_REG 8 +#define NISTC_G1_HW_SAVE_REG 10 + +#define NISTC_G0_SAVE_REG 12 +#define NISTC_G1_SAVE_REG 14 + +#define NISTC_AO_UI_SAVE_REG 16 +#define NISTC_AO_BC_SAVE_REG 18 +#define NISTC_AO_UC_SAVE_REG 20 + +#define NISTC_STATUS1_REG 27 +#define NISTC_STATUS1_SERIO_IN_PROG BIT(12) + +#define NISTC_DIO_SERIAL_IN_REG 28 + +#define NISTC_STATUS2_REG 29 +#define NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS BIT(5) + +#define NISTC_AI_SI_SAVE_REG 64 +#define NISTC_AI_SC_SAVE_REG 66 -#define Second_IRQ_B_Enable_Register 76 -enum Second_IRQ_B_Enable_Bits { - AO_BC_TC_Second_Irq_Enable = _bit0, - AO_START1_Second_Irq_Enable = _bit1, - AO_UPDATE_Second_Irq_Enable = _bit2, - AO_START_Second_Irq_Enable = _bit3, - AO_STOP_Second_Irq_Enable = _bit4, - AO_Error_Second_Irq_Enable = _bit5, - AO_UC_TC_Second_Irq_Enable = _bit6, - AO_UI2_TC_Second_Irq_Enable = _bit7, - AO_FIFO_Second_Irq_Enable = _bit8, - G1_TC_Second_Irq_Enable = _bit9, - G1_Gate_Second_Irq_Enable = _bit10, - Pass_Thru_1_Second_Irq_Enable = _bit11 -}; +/* + * PCI E Series Registers + */ +#define NI_E_STC_WINDOW_ADDR_REG 0x00 /* rw16 */ +#define NI_E_STC_WINDOW_DATA_REG 0x02 /* rw16 */ + +#define NI_E_STATUS_REG 0x01 /* r8 */ +#define NI_E_STATUS_AI_FIFO_LOWER_NE BIT(3) +#define NI_E_STATUS_PROMOUT BIT(0) + +#define NI_E_DMA_AI_AO_SEL_REG 0x09 /* w8 */ +#define NI_E_DMA_AI_SEL(x) (((x) & 0xf) << 0) +#define NI_E_DMA_AI_SEL_MASK NI_E_DMA_AI_SEL(0xf) +#define NI_E_DMA_AO_SEL(x) (((x) & 0xf) << 4) +#define NI_E_DMA_AO_SEL_MASK NI_E_DMA_AO_SEL(0xf) + +#define NI_E_DMA_G0_G1_SEL_REG 0x0b /* w8 */ +#define NI_E_DMA_G0_G1_SEL(_g, _c) (((_c) & 0xf) << ((_g) * 4)) +#define NI_E_DMA_G0_G1_SEL_MASK(_g) NI_E_DMA_G0_G1_SEL((_g), 0xf) + +#define NI_E_SERIAL_CMD_REG 0x0d /* w8 */ +#define NI_E_SERIAL_CMD_DAC_LD(x) BIT(3 + (x)) +#define NI_E_SERIAL_CMD_EEPROM_CS BIT(2) +#define NI_E_SERIAL_CMD_SDATA BIT(1) +#define NI_E_SERIAL_CMD_SCLK BIT(0) + +#define NI_E_MISC_CMD_REG 0x0f /* w8 */ +#define NI_E_MISC_CMD_INTEXT_ATRIG(x) (((x) & 0x1) << 7) +#define NI_E_MISC_CMD_EXT_ATRIG NI_E_MISC_CMD_INTEXT_ATRIG(0) +#define NI_E_MISC_CMD_INT_ATRIG NI_E_MISC_CMD_INTEXT_ATRIG(1) + +#define NI_E_AI_CFG_LO_REG 0x10 /* w16 */ +#define NI_E_AI_CFG_LO_LAST_CHAN BIT(15) +#define NI_E_AI_CFG_LO_GEN_TRIG BIT(12) +#define NI_E_AI_CFG_LO_DITHER BIT(9) +#define NI_E_AI_CFG_LO_UNI BIT(8) +#define NI_E_AI_CFG_LO_GAIN(x) ((x) << 0) + +#define NI_E_AI_CFG_HI_REG 0x12 /* w16 */ +#define NI_E_AI_CFG_HI_TYPE(x) (((x) & 0x7) << 12) +#define NI_E_AI_CFG_HI_TYPE_DIFF NI_E_AI_CFG_HI_TYPE(1) +#define NI_E_AI_CFG_HI_TYPE_COMMON NI_E_AI_CFG_HI_TYPE(2) +#define NI_E_AI_CFG_HI_TYPE_GROUND NI_E_AI_CFG_HI_TYPE(3) +#define NI_E_AI_CFG_HI_AC_COUPLE BIT(11) +#define NI_E_AI_CFG_HI_CHAN(x) (((x) & 0x3f) << 0) + +#define NI_E_AO_CFG_REG 0x16 /* w16 */ +#define NI_E_AO_DACSEL(x) ((x) << 8) +#define NI_E_AO_GROUND_REF BIT(3) +#define NI_E_AO_EXT_REF BIT(2) +#define NI_E_AO_DEGLITCH BIT(1) +#define NI_E_AO_CFG_BIP BIT(0) + +#define NI_E_DAC_DIRECT_DATA_REG(x) (0x18 + ((x) * 2)) /* w16 */ + +#define NI_E_8255_BASE 0x19 /* rw8 */ + +#define NI_E_AI_FIFO_DATA_REG 0x1c /* r16 */ + +#define NI_E_AO_FIFO_DATA_REG 0x1e /* w16 */ -#define AI_Personal_Register 77 -#define AI_SHIFTIN_Pulse_Width _bit15 -#define AI_EOC_Polarity _bit14 -#define AI_SOC_Polarity _bit13 -#define AI_SHIFTIN_Polarity _bit12 -#define AI_CONVERT_Pulse_Timebase _bit11 -#define AI_CONVERT_Pulse_Width _bit10 -#define AI_CONVERT_Original_Pulse _bit9 -#define AI_FIFO_Flags_Polarity _bit8 -#define AI_Overrun_Mode _bit7 -#define AI_EXTMUX_CLK_Pulse_Width _bit6 -#define AI_LOCALMUX_CLK_Pulse_Width _bit5 -#define AI_AIFREQ_Polarity _bit4 - -#define AO_Personal_Register 78 -enum AO_Personal_Bits { - AO_Interval_Buffer_Mode = 1 << 3, - AO_BC_Source_Select = 1 << 4, - AO_UPDATE_Pulse_Width = 1 << 5, - AO_UPDATE_Pulse_Timebase = 1 << 6, - AO_UPDATE_Original_Pulse = 1 << 7, - AO_DMA_PIO_Control = 1 << 8, /* M Series: reserved */ - AO_AOFREQ_Polarity = 1 << 9, /* M Series: reserved */ - AO_FIFO_Enable = 1 << 10, - AO_FIFO_Flags_Polarity = 1 << 11, /* M Series: reserved */ - AO_TMRDACWR_Pulse_Width = 1 << 12, - AO_Fast_CPU = 1 << 13, /* M Series: reserved */ - AO_Number_Of_DAC_Packages = 1 << 14, /* 1 for "single" mode, 0 for "dual" */ - AO_Multiple_DACS_Per_Package = 1 << 15 /* m-series only */ -}; -#define RTSI_Trig_A_Output_Register 79 -#define RTSI_Trig_B_Output_Register 80 -enum RTSI_Trig_B_Output_Bits { - RTSI_Sub_Selection_1_Bit = 0x8000 /* not for m-series */ -}; -static inline unsigned RTSI_Trig_Output_Bits(unsigned rtsi_channel, - unsigned source) -{ - return (source & 0xf) << ((rtsi_channel % 4) * 4); -}; +/* + * 611x registers (these boards differ from the e-series) + */ +#define NI611X_MAGIC_REG 0x19 /* w8 (new) */ +#define NI611X_CALIB_CHAN_SEL_REG 0x1a /* w16 (new) */ +#define NI611X_AI_FIFO_DATA_REG 0x1c /* r32 (incompatible) */ +#define NI611X_AI_FIFO_OFFSET_LOAD_REG 0x05 /* r8 (new) */ +#define NI611X_AO_FIFO_DATA_REG 0x14 /* w32 (incompatible) */ +#define NI611X_CAL_GAIN_SEL_REG 0x05 /* w8 (new) */ + +#define NI611X_AO_WINDOW_ADDR_REG 0x18 +#define NI611X_AO_WINDOW_DATA_REG 0x1e -static inline unsigned RTSI_Trig_Output_Mask(unsigned rtsi_channel) -{ - return 0xf << ((rtsi_channel % 4) * 4); -}; +/* + * 6143 registers + */ +#define NI6143_MAGIC_REG 0x19 /* w8 */ +#define NI6143_DMA_G0_G1_SEL_REG 0x0b /* w8 */ +#define NI6143_PIPELINE_DELAY_REG 0x1f /* w8 */ +#define NI6143_EOC_SET_REG 0x1d /* w8 */ +#define NI6143_DMA_AI_SEL_REG 0x09 /* w8 */ +#define NI6143_AI_FIFO_DATA_REG 0x8c /* r32 */ +#define NI6143_AI_FIFO_FLAG_REG 0x84 /* w32 */ +#define NI6143_AI_FIFO_CTRL_REG 0x88 /* w32 */ +#define NI6143_AI_FIFO_STATUS_REG 0x88 /* r32 */ +#define NI6143_AI_FIFO_DMA_THRESH_REG 0x90 /* w32 */ +#define NI6143_AI_FIFO_WORDS_AVAIL_REG 0x94 /* w32 */ + +#define NI6143_CALIB_CHAN_REG 0x42 /* w16 */ +#define NI6143_CALIB_CHAN_RELAY_ON BIT(15) +#define NI6143_CALIB_CHAN_RELAY_OFF BIT(14) +#define NI6143_CALIB_CHAN(x) (((x) & 0xf) << 0) +#define NI6143_CALIB_CHAN_GND_GND NI6143_CALIB_CHAN(0) /* Offset Cal */ +#define NI6143_CALIB_CHAN_2V5_GND NI6143_CALIB_CHAN(2) /* 2.5V ref */ +#define NI6143_CALIB_CHAN_PWM_GND NI6143_CALIB_CHAN(5) /* +-5V Self Cal */ +#define NI6143_CALIB_CHAN_2V5_PWM NI6143_CALIB_CHAN(10) /* PWM Cal */ +#define NI6143_CALIB_CHAN_PWM_PWM NI6143_CALIB_CHAN(13) /* CMRR */ +#define NI6143_CALIB_CHAN_GND_PWM NI6143_CALIB_CHAN(14) /* PWM Cal */ +#define NI6143_CALIB_LO_TIME_REG 0x20 /* w16 */ +#define NI6143_CALIB_HI_TIME_REG 0x22 /* w16 */ +#define NI6143_RELAY_COUNTER_LOAD_REG 0x4c /* w32 */ +#define NI6143_SIGNATURE_REG 0x50 /* w32 */ +#define NI6143_RELEASE_DATE_REG 0x54 /* w32 */ +#define NI6143_RELEASE_OLDEST_DATE_REG 0x58 /* w32 */ -/* inverse to RTSI_Trig_Output_Bits() */ -static inline unsigned RTSI_Trig_Output_Source(unsigned rtsi_channel, - unsigned bits) -{ - return (bits >> ((rtsi_channel % 4) * 4)) & 0xf; -}; +/* + * 671x, 611x windowed ao registers + */ +#define NI671X_DAC_DIRECT_DATA_REG(x) (0x00 + (x)) /* w16 */ +#define NI611X_AO_TIMED_REG 0x10 /* w16 */ +#define NI671X_AO_IMMEDIATE_REG 0x11 /* w16 */ +#define NI611X_AO_FIFO_OFFSET_LOAD_REG 0x13 /* w32 */ +#define NI67XX_AO_SP_UPDATES_REG 0x14 /* w16 */ +#define NI611X_AO_WAVEFORM_GEN_REG 0x15 /* w16 */ +#define NI611X_AO_MISC_REG 0x16 /* w16 */ +#define NI611X_AO_MISC_CLEAR_WG BIT(0) +#define NI67XX_AO_CAL_CHAN_SEL_REG 0x17 /* w16 */ +#define NI67XX_AO_CFG2_REG 0x18 /* w16 */ +#define NI67XX_CAL_CMD_REG 0x19 /* w16 */ +#define NI67XX_CAL_STATUS_REG 0x1a /* r8 */ +#define NI67XX_CAL_STATUS_BUSY BIT(0) +#define NI67XX_CAL_STATUS_OSC_DETECT BIT(1) +#define NI67XX_CAL_STATUS_OVERRANGE BIT(2) +#define NI67XX_CAL_DATA_REG 0x1b /* r16 */ +#define NI67XX_CAL_CFG_HI_REG 0x1c /* rw16 */ +#define NI67XX_CAL_CFG_LO_REG 0x1d /* rw16 */ + +#define CS5529_CMD_CB BIT(7) +#define CS5529_CMD_SINGLE_CONV BIT(6) +#define CS5529_CMD_CONT_CONV BIT(5) +#define CS5529_CMD_READ BIT(4) +#define CS5529_CMD_REG(x) (((x) & 0x7) << 1) +#define CS5529_CMD_REG_MASK CS5529_CMD_REG(7) +#define CS5529_CMD_PWR_SAVE BIT(0) + +#define CS5529_OFFSET_REG CS5529_CMD_REG(0) +#define CS5529_GAIN_REG CS5529_CMD_REG(1) +#define CS5529_CONV_DATA_REG CS5529_CMD_REG(3) +#define CS5529_SETUP_REG CS5529_CMD_REG(4) + +#define CS5529_CFG_REG CS5529_CMD_REG(2) +#define CS5529_CFG_AOUT(x) BIT(22 + (x)) +#define CS5529_CFG_DOUT(x) BIT(18 + (x)) +#define CS5529_CFG_LOW_PWR_MODE BIT(16) +#define CS5529_CFG_WORD_RATE(x) (((x) & 0x7) << 13) +#define CS5529_CFG_WORD_RATE_MASK CS5529_CFG_WORD_RATE(0x7) +#define CS5529_CFG_WORD_RATE_2180 CS5529_CFG_WORD_RATE(0) +#define CS5529_CFG_WORD_RATE_1092 CS5529_CFG_WORD_RATE(1) +#define CS5529_CFG_WORD_RATE_532 CS5529_CFG_WORD_RATE(2) +#define CS5529_CFG_WORD_RATE_388 CS5529_CFG_WORD_RATE(3) +#define CS5529_CFG_WORD_RATE_324 CS5529_CFG_WORD_RATE(4) +#define CS5529_CFG_WORD_RATE_17444 CS5529_CFG_WORD_RATE(5) +#define CS5529_CFG_WORD_RATE_8724 CS5529_CFG_WORD_RATE(6) +#define CS5529_CFG_WORD_RATE_4364 CS5529_CFG_WORD_RATE(7) +#define CS5529_CFG_UNIPOLAR BIT(12) +#define CS5529_CFG_RESET BIT(7) +#define CS5529_CFG_RESET_VALID BIT(6) +#define CS5529_CFG_PORT_FLAG BIT(5) +#define CS5529_CFG_PWR_SAVE_SEL BIT(4) +#define CS5529_CFG_DONE_FLAG BIT(3) +#define CS5529_CFG_CALIB(x) (((x) & 0x7) << 0) +#define CS5529_CFG_CALIB_NONE CS5529_CFG_CALIB(0) +#define CS5529_CFG_CALIB_OFFSET_SELF CS5529_CFG_CALIB(1) +#define CS5529_CFG_CALIB_GAIN_SELF CS5529_CFG_CALIB(2) +#define CS5529_CFG_CALIB_BOTH_SELF CS5529_CFG_CALIB(3) +#define CS5529_CFG_CALIB_OFFSET_SYS CS5529_CFG_CALIB(5) +#define CS5529_CFG_CALIB_GAIN_SYS CS5529_CFG_CALIB(6) -#define RTSI_Board_Register 81 -#define Write_Strobe_0_Register 82 -#define Write_Strobe_1_Register 83 -#define Write_Strobe_2_Register 84 -#define Write_Strobe_3_Register 85 - -#define AO_Output_Control_Register 86 -#define AO_External_Gate_Enable _bit15 -#define AO_External_Gate_Select(x) (((x)&0x1f)<<10) -#define AO_Number_Of_Channels(x) (((x)&0xf)<<6) -#define AO_UPDATE2_Output_Select(x) (((x)&0x3)<<4) -#define AO_External_Gate_Polarity _bit3 -#define AO_UPDATE2_Output_Toggle _bit2 -enum ao_update_output_selection { - AO_Update_Output_High_Z = 0, - AO_Update_Output_Ground = 1, - AO_Update_Output_Enable_Low = 2, - AO_Update_Output_Enable_High = 3 -}; -static unsigned AO_UPDATE_Output_Select(enum ao_update_output_selection - selection) -{ - return selection & 0x3; -} - -#define AI_Mode_3_Register 87 -#define AI_Trigger_Length _bit15 -#define AI_Delay_START _bit14 -#define AI_Software_Gate _bit13 -#define AI_SI_Special_Trigger_Delay _bit12 -#define AI_SI2_Source_Select _bit11 -#define AI_Delayed_START2 _bit10 -#define AI_Delayed_START1 _bit9 -#define AI_External_Gate_Mode _bit8 -#define AI_FIFO_Mode_HF_to_E (3<<6) -#define AI_FIFO_Mode_F (2<<6) -#define AI_FIFO_Mode_HF (1<<6) -#define AI_FIFO_Mode_NE (0<<6) -#define AI_External_Gate_Polarity _bit5 -#define AI_External_Gate_Select(a) ((a) & 0x1f) - -#define G_Autoincrement_Register(a) (68+(a)) -#define G_Command_Register(a) (6+(a)) -#define G_HW_Save_Register(a) (8+(a)*2) -#define G_HW_Save_Register_High(a) (8+(a)*2) -#define G_HW_Save_Register_Low(a) (9+(a)*2) -#define G_Input_Select_Register(a) (36+(a)) -#define G_Load_A_Register(a) (28+(a)*4) -#define G_Load_A_Register_High(a) (28+(a)*4) -#define G_Load_A_Register_Low(a) (29+(a)*4) -#define G_Load_B_Register(a) (30+(a)*4) -#define G_Load_B_Register_High(a) (30+(a)*4) -#define G_Load_B_Register_Low(a) (31+(a)*4) -#define G_Mode_Register(a) (26+(a)) -#define G_Save_Register(a) (12+(a)*2) -#define G_Save_Register_High(a) (12+(a)*2) -#define G_Save_Register_Low(a) (13+(a)*2) -#define G_Status_Register 4 -#define Analog_Trigger_Etc_Register 61 - -/* command register */ -#define G_Disarm_Copy _bit15 /* strobe */ -#define G_Save_Trace_Copy _bit14 -#define G_Arm_Copy _bit13 /* strobe */ -#define G_Bank_Switch_Start _bit10 /* strobe */ -#define G_Little_Big_Endian _bit9 -#define G_Synchronized_Gate _bit8 -#define G_Write_Switch _bit7 -#define G_Up_Down(a) (((a)&0x03)<<5) -#define G_Disarm _bit4 /* strobe */ -#define G_Analog_Trigger_Reset _bit3 /* strobe */ -#define G_Save_Trace _bit1 -#define G_Arm _bit0 /* strobe */ - -/*channel agnostic names for the command register #defines */ -#define G_Bank_Switch_Enable _bit12 -#define G_Bank_Switch_Mode _bit11 -#define G_Load _bit2 /* strobe */ - -/* input select register */ -#define G_Gate_Select(a) (((a)&0x1f)<<7) -#define G_Source_Select(a) (((a)&0x1f)<<2) -#define G_Write_Acknowledges_Irq _bit1 -#define G_Read_Acknowledges_Irq _bit0 - -/* same input select register, but with channel agnostic names */ -#define G_Source_Polarity _bit15 -#define G_Output_Polarity _bit14 -#define G_OR_Gate _bit13 -#define G_Gate_Select_Load_Source _bit12 - -/* mode register */ -#define G_Loading_On_TC _bit12 -#define G_Output_Mode(a) (((a)&0x03)<<8) -#define G_Trigger_Mode_For_Edge_Gate(a) (((a)&0x03)<<3) -#define G_Gating_Mode(a) (((a)&0x03)<<0) - -/* same input mode register, but with channel agnostic names */ -#define G_Load_Source_Select _bit7 -#define G_Reload_Source_Switching _bit15 -#define G_Loading_On_Gate _bit14 -#define G_Gate_Polarity _bit13 - -#define G_Counting_Once(a) (((a)&0x03)<<10) -#define G_Stop_Mode(a) (((a)&0x03)<<5) -#define G_Gate_On_Both_Edges _bit2 - -/* G_Status_Register */ -#define G1_Gate_Error_St _bit15 -#define G0_Gate_Error_St _bit14 -#define G1_TC_Error_St _bit13 -#define G0_TC_Error_St _bit12 -#define G1_No_Load_Between_Gates_St _bit11 -#define G0_No_Load_Between_Gates_St _bit10 -#define G1_Armed_St _bit9 -#define G0_Armed_St _bit8 -#define G1_Stale_Data_St _bit7 -#define G0_Stale_Data_St _bit6 -#define G1_Next_Load_Source_St _bit5 -#define G0_Next_Load_Source_St _bit4 -#define G1_Counting_St _bit3 -#define G0_Counting_St _bit2 -#define G1_Save_St _bit1 -#define G0_Save_St _bit0 - -/* general purpose counter timer */ -#define G_Autoincrement(a) ((a)<<0) - -/*Analog_Trigger_Etc_Register*/ -#define Analog_Trigger_Mode(x) ((x) & 0x7) -#define Analog_Trigger_Enable _bit3 -#define Analog_Trigger_Drive _bit4 -#define GPFO_1_Output_Select _bit7 -#define GPFO_0_Output_Select(a) ((a)<<11) -#define GPFO_0_Output_Enable _bit14 -#define GPFO_1_Output_Enable _bit15 - -/* Additional windowed registers unique to E series */ - -/* 16 bit registers shadowed from DAQ-STC */ -#define Window_Address 0x00 -#define Window_Data 0x02 - -#define Configuration_Memory_Clear 82 -#define ADC_FIFO_Clear 83 -#define DAC_FIFO_Clear 84 - -/* i/o port offsets */ - -/* 8 bit registers */ -#define XXX_Status 0x01 -enum XXX_Status_Bits { - PROMOUT = 0x1, - AI_FIFO_LOWER_NOT_EMPTY = 0x8, -}; -#define Serial_Command 0x0d -#define Misc_Command 0x0f -#define Port_A 0x19 -#define Port_B 0x1b -#define Port_C 0x1d -#define Configuration 0x1f -#define Strobes 0x01 -#define Channel_A_Mode 0x03 -#define Channel_B_Mode 0x05 -#define Channel_C_Mode 0x07 -#define AI_AO_Select 0x09 -enum AI_AO_Select_Bits { - AI_DMA_Select_Shift = 0, - AI_DMA_Select_Mask = 0xf, - AO_DMA_Select_Shift = 4, - AO_DMA_Select_Mask = 0xf << AO_DMA_Select_Shift -}; -#define G0_G1_Select 0x0b -static inline unsigned ni_stc_dma_channel_select_bitfield(unsigned channel) -{ - if (channel < 4) - return 1 << channel; - if (channel == 4) - return 0x3; - if (channel == 5) - return 0x5; - BUG(); - return 0; -} - -static inline unsigned GPCT_DMA_Select_Bits(unsigned gpct_index, - unsigned mite_channel) -{ - BUG_ON(gpct_index > 1); - return ni_stc_dma_channel_select_bitfield(mite_channel) << (4 * - gpct_index); -} - -static inline unsigned GPCT_DMA_Select_Mask(unsigned gpct_index) -{ - BUG_ON(gpct_index > 1); - return 0xf << (4 * gpct_index); -} - -/* 16 bit registers */ - -#define Configuration_Memory_Low 0x10 -enum Configuration_Memory_Low_Bits { - AI_DITHER = 0x200, - AI_LAST_CHANNEL = 0x8000, -}; -#define Configuration_Memory_High 0x12 -enum Configuration_Memory_High_Bits { - AI_AC_COUPLE = 0x800, - AI_DIFFERENTIAL = 0x1000, - AI_COMMON = 0x2000, - AI_GROUND = 0x3000, -}; -static inline unsigned int AI_CONFIG_CHANNEL(unsigned int channel) -{ - return channel & 0x3f; -} - -#define ADC_FIFO_Data_Register 0x1c - -#define AO_Configuration 0x16 -#define AO_Bipolar _bit0 -#define AO_Deglitch _bit1 -#define AO_Ext_Ref _bit2 -#define AO_Ground_Ref _bit3 -#define AO_Channel(x) ((x) << 8) - -#define DAC_FIFO_Data 0x1e -#define DAC0_Direct_Data 0x18 -#define DAC1_Direct_Data 0x1a - -/* 611x registers (these boards differ from the e-series) */ - -#define Magic_611x 0x19 /* w8 (new) */ -#define Calibration_Channel_Select_611x 0x1a /* w16 (new) */ -#define ADC_FIFO_Data_611x 0x1c /* r32 (incompatible) */ -#define AI_FIFO_Offset_Load_611x 0x05 /* r8 (new) */ -#define DAC_FIFO_Data_611x 0x14 /* w32 (incompatible) */ -#define Cal_Gain_Select_611x 0x05 /* w8 (new) */ - -#define AO_Window_Address_611x 0x18 -#define AO_Window_Data_611x 0x1e - -/* 6143 registers */ -#define Magic_6143 0x19 /* w8 */ -#define G0G1_DMA_Select_6143 0x0B /* w8 */ -#define PipelineDelay_6143 0x1f /* w8 */ -#define EOC_Set_6143 0x1D /* w8 */ -#define AIDMA_Select_6143 0x09 /* w8 */ -#define AIFIFO_Data_6143 0x8C /* w32 */ -#define AIFIFO_Flag_6143 0x84 /* w32 */ -#define AIFIFO_Control_6143 0x88 /* w32 */ -#define AIFIFO_Status_6143 0x88 /* w32 */ -#define AIFIFO_DMAThreshold_6143 0x90 /* w32 */ -#define AIFIFO_Words_Available_6143 0x94 /* w32 */ - -#define Calibration_Channel_6143 0x42 /* w16 */ -#define Calibration_LowTime_6143 0x20 /* w16 */ -#define Calibration_HighTime_6143 0x22 /* w16 */ -#define Relay_Counter_Load_Val__6143 0x4C /* w32 */ -#define Signature_6143 0x50 /* w32 */ -#define Release_Date_6143 0x54 /* w32 */ -#define Release_Oldest_Date_6143 0x58 /* w32 */ - -#define Calibration_Channel_6143_RelayOn 0x8000 /* Calibration relay switch On */ -#define Calibration_Channel_6143_RelayOff 0x4000 /* Calibration relay switch Off */ -#define Calibration_Channel_Gnd_Gnd 0x00 /* Offset Calibration */ -#define Calibration_Channel_2v5_Gnd 0x02 /* 2.5V Reference */ -#define Calibration_Channel_Pwm_Gnd 0x05 /* +/- 5V Self Cal */ -#define Calibration_Channel_2v5_Pwm 0x0a /* PWM Calibration */ -#define Calibration_Channel_Pwm_Pwm 0x0d /* CMRR */ -#define Calibration_Channel_Gnd_Pwm 0x0e /* PWM Calibration */ - -/* 671x, 611x registers */ - -/* 671xi, 611x windowed ao registers */ -enum windowed_regs_67xx_61xx { - AO_Immediate_671x = 0x11, /* W 16 */ - AO_Timed_611x = 0x10, /* W 16 */ - AO_FIFO_Offset_Load_611x = 0x13, /* W32 */ - AO_Later_Single_Point_Updates = 0x14, /* W 16 */ - AO_Waveform_Generation_611x = 0x15, /* W 16 */ - AO_Misc_611x = 0x16, /* W 16 */ - AO_Calibration_Channel_Select_67xx = 0x17, /* W 16 */ - AO_Configuration_2_67xx = 0x18, /* W 16 */ - CAL_ADC_Command_67xx = 0x19, /* W 8 */ - CAL_ADC_Status_67xx = 0x1a, /* R 8 */ - CAL_ADC_Data_67xx = 0x1b, /* R 16 */ - CAL_ADC_Config_Data_High_Word_67xx = 0x1c, /* RW 16 */ - CAL_ADC_Config_Data_Low_Word_67xx = 0x1d, /* RW 16 */ +/* + * M-Series specific registers not handled by the DAQ-STC and GPCT register + * remapping. + */ +#define NI_M_CDIO_DMA_SEL_REG 0x007 +#define NI_M_CDIO_DMA_SEL_CDO(x) (((x) & 0xf) << 4) +#define NI_M_CDIO_DMA_SEL_CDO_MASK NI_M_CDIO_DMA_SEL_CDO(0xf) +#define NI_M_CDIO_DMA_SEL_CDI(x) (((x) & 0xf) << 0) +#define NI_M_CDIO_DMA_SEL_CDI_MASK NI_M_CDIO_DMA_SEL_CDI(0xf) +#define NI_M_SCXI_STATUS_REG 0x007 +#define NI_M_AI_AO_SEL_REG 0x009 +#define NI_M_G0_G1_SEL_REG 0x00b +#define NI_M_MISC_CMD_REG 0x00f +#define NI_M_SCXI_SER_DO_REG 0x011 +#define NI_M_SCXI_CTRL_REG 0x013 +#define NI_M_SCXI_OUT_ENA_REG 0x015 +#define NI_M_AI_FIFO_DATA_REG 0x01c +#define NI_M_DIO_REG 0x024 +#define NI_M_DIO_DIR_REG 0x028 +#define NI_M_CAL_PWM_REG 0x040 +#define NI_M_CAL_PWM_HIGH_TIME(x) (((x) & 0xffff) << 16) +#define NI_M_CAL_PWM_LOW_TIME(x) (((x) & 0xffff) << 0) +#define NI_M_GEN_PWM_REG(x) (0x044 + ((x) * 2)) +#define NI_M_AI_CFG_FIFO_DATA_REG 0x05e +#define NI_M_AI_CFG_LAST_CHAN BIT(14) +#define NI_M_AI_CFG_DITHER BIT(13) +#define NI_M_AI_CFG_POLARITY BIT(12) +#define NI_M_AI_CFG_GAIN(x) (((x) & 0x7) << 9) +#define NI_M_AI_CFG_CHAN_TYPE(x) (((x) & 0x7) << 6) +#define NI_M_AI_CFG_CHAN_TYPE_MASK NI_M_AI_CFG_CHAN_TYPE(7) +#define NI_M_AI_CFG_CHAN_TYPE_CALIB NI_M_AI_CFG_CHAN_TYPE(0) +#define NI_M_AI_CFG_CHAN_TYPE_DIFF NI_M_AI_CFG_CHAN_TYPE(1) +#define NI_M_AI_CFG_CHAN_TYPE_COMMON NI_M_AI_CFG_CHAN_TYPE(2) +#define NI_M_AI_CFG_CHAN_TYPE_GROUND NI_M_AI_CFG_CHAN_TYPE(3) +#define NI_M_AI_CFG_CHAN_TYPE_AUX NI_M_AI_CFG_CHAN_TYPE(5) +#define NI_M_AI_CFG_CHAN_TYPE_GHOST NI_M_AI_CFG_CHAN_TYPE(7) +#define NI_M_AI_CFG_BANK_SEL(x) ((((x) & 0x40) << 4) | ((x) & 0x30)) +#define NI_M_AI_CFG_CHAN_SEL(x) (((x) & 0xf) << 0) +#define NI_M_INTC_ENA_REG 0x088 +#define NI_M_INTC_ENA BIT(0) +#define NI_M_INTC_STATUS_REG 0x088 +#define NI_M_INTC_STATUS BIT(0) +#define NI_M_ATRIG_CTRL_REG 0x08c +#define NI_M_AO_SER_INT_ENA_REG 0x0a0 +#define NI_M_AO_SER_INT_ACK_REG 0x0a1 +#define NI_M_AO_SER_INT_STATUS_REG 0x0a1 +#define NI_M_AO_CALIB_REG 0x0a3 +#define NI_M_AO_FIFO_DATA_REG 0x0a4 +#define NI_M_PFI_FILTER_REG 0x0b0 +#define NI_M_PFI_FILTER_SEL(_c, _f) (((_f) & 0x3) << ((_c) * 2)) +#define NI_M_PFI_FILTER_SEL_MASK(_c) NI_M_PFI_FILTER_SEL((_c), 0x3) +#define NI_M_RTSI_FILTER_REG 0x0b4 +#define NI_M_SCXI_LEGACY_COMPAT_REG 0x0bc +#define NI_M_DAC_DIRECT_DATA_REG(x) (0x0c0 + ((x) * 4)) +#define NI_M_AO_WAVEFORM_ORDER_REG(x) (0x0c2 + ((x) * 4)) +#define NI_M_AO_CFG_BANK_REG(x) (0x0c3 + ((x) * 4)) +#define NI_M_AO_CFG_BANK_BIPOLAR BIT(7) +#define NI_M_AO_CFG_BANK_UPDATE_TIMED BIT(6) +#define NI_M_AO_CFG_BANK_REF(x) (((x) & 0x7) << 3) +#define NI_M_AO_CFG_BANK_REF_MASK NI_M_AO_CFG_BANK_REF(7) +#define NI_M_AO_CFG_BANK_REF_INT_10V NI_M_AO_CFG_BANK_REF(0) +#define NI_M_AO_CFG_BANK_REF_INT_5V NI_M_AO_CFG_BANK_REF(1) +#define NI_M_AO_CFG_BANK_OFFSET(x) (((x) & 0x7) << 0) +#define NI_M_AO_CFG_BANK_OFFSET_MASK NI_M_AO_CFG_BANK_OFFSET(7) +#define NI_M_AO_CFG_BANK_OFFSET_0V NI_M_AO_CFG_BANK_OFFSET(0) +#define NI_M_AO_CFG_BANK_OFFSET_5V NI_M_AO_CFG_BANK_OFFSET(1) +#define NI_M_RTSI_SHARED_MUX_REG 0x1a2 +#define NI_M_CLK_FOUT2_REG 0x1c4 +#define NI_M_CLK_FOUT2_RTSI_10MHZ BIT(7) +#define NI_M_CLK_FOUT2_TIMEBASE3_PLL BIT(6) +#define NI_M_CLK_FOUT2_TIMEBASE1_PLL BIT(5) +#define NI_M_CLK_FOUT2_PLL_SRC(x) (((x) & 0x1f) << 0) +#define NI_M_CLK_FOUT2_PLL_SRC_MASK NI_M_CLK_FOUT2_PLL_SRC(0x1f) +#define NI_M_MAX_RTSI_CHAN 7 +#define NI_M_CLK_FOUT2_PLL_SRC_RTSI(x) (((x) == NI_M_MAX_RTSI_CHAN) \ + ? NI_M_CLK_FOUT2_PLL_SRC(0x1b) \ + : NI_M_CLK_FOUT2_PLL_SRC(0xb + (x))) +#define NI_M_CLK_FOUT2_PLL_SRC_STAR NI_M_CLK_FOUT2_PLL_SRC(0x14) +#define NI_M_CLK_FOUT2_PLL_SRC_PXI10 NI_M_CLK_FOUT2_PLL_SRC(0x1d) +#define NI_M_PLL_CTRL_REG 0x1c6 +#define NI_M_PLL_CTRL_VCO_MODE(x) (((x) & 0x3) << 13) +#define NI_M_PLL_CTRL_VCO_MODE_200_325MHZ NI_M_PLL_CTRL_VCO_MODE(0) +#define NI_M_PLL_CTRL_VCO_MODE_175_225MHZ NI_M_PLL_CTRL_VCO_MODE(1) +#define NI_M_PLL_CTRL_VCO_MODE_100_225MHZ NI_M_PLL_CTRL_VCO_MODE(2) +#define NI_M_PLL_CTRL_VCO_MODE_75_150MHZ NI_M_PLL_CTRL_VCO_MODE(3) +#define NI_M_PLL_CTRL_ENA BIT(12) +#define NI_M_PLL_MAX_DIVISOR 0x10 +#define NI_M_PLL_CTRL_DIVISOR(x) (((x) & 0xf) << 8) +#define NI_M_PLL_MAX_MULTIPLIER 0x100 +#define NI_M_PLL_CTRL_MULTIPLIER(x) (((x) & 0xff) << 0) +#define NI_M_PLL_STATUS_REG 0x1c8 +#define NI_M_PLL_STATUS_LOCKED BIT(0) +#define NI_M_PFI_OUT_SEL_REG(x) (0x1d0 + ((x) * 2)) +#define NI_M_PFI_CHAN(_c) (((_c) % 3) * 5) +#define NI_M_PFI_OUT_SEL(_c, _s) (((_s) & 0x1f) << NI_M_PFI_CHAN(_c)) +#define NI_M_PFI_OUT_SEL_MASK(_c) (0x1f << NI_M_PFI_CHAN(_c)) +#define NI_M_PFI_OUT_SEL_TO_SRC(_c, _b) (((_b) >> NI_M_PFI_CHAN(_c)) & 0x1f) +#define NI_M_PFI_DI_REG 0x1dc +#define NI_M_PFI_DO_REG 0x1de +#define NI_M_CFG_BYPASS_FIFO_REG 0x218 +#define NI_M_CFG_BYPASS_FIFO BIT(31) +#define NI_M_CFG_BYPASS_AI_POLARITY BIT(22) +#define NI_M_CFG_BYPASS_AI_DITHER BIT(21) +#define NI_M_CFG_BYPASS_AI_GAIN(x) (((x) & 0x7) << 18) +#define NI_M_CFG_BYPASS_AO_CAL(x) (((x) & 0xf) << 15) +#define NI_M_CFG_BYPASS_AO_CAL_MASK NI_M_CFG_BYPASS_AO_CAL(0xf) +#define NI_M_CFG_BYPASS_AI_MODE_MUX(x) (((x) & 0x3) << 13) +#define NI_M_CFG_BYPASS_AI_MODE_MUX_MASK NI_M_CFG_BYPASS_AI_MODE_MUX(3) +#define NI_M_CFG_BYPASS_AI_CAL_NEG(x) (((x) & 0x7) << 10) +#define NI_M_CFG_BYPASS_AI_CAL_NEG_MASK NI_M_CFG_BYPASS_AI_CAL_NEG(7) +#define NI_M_CFG_BYPASS_AI_CAL_POS(x) (((x) & 0x7) << 7) +#define NI_M_CFG_BYPASS_AI_CAL_POS_MASK NI_M_CFG_BYPASS_AI_CAL_POS(7) +#define NI_M_CFG_BYPASS_AI_CAL_MASK (NI_M_CFG_BYPASS_AI_CAL_POS_MASK | \ + NI_M_CFG_BYPASS_AI_CAL_NEG_MASK | \ + NI_M_CFG_BYPASS_AI_MODE_MUX_MASK | \ + NI_M_CFG_BYPASS_AO_CAL_MASK) +#define NI_M_CFG_BYPASS_AI_BANK(x) (((x) & 0xf) << 3) +#define NI_M_CFG_BYPASS_AI_BANK_MASK NI_M_CFG_BYPASS_AI_BANK(0xf) +#define NI_M_CFG_BYPASS_AI_CHAN(x) (((x) & 0x7) << 0) +#define NI_M_CFG_BYPASS_AI_CHAN_MASK NI_M_CFG_BYPASS_AI_CHAN(7) +#define NI_M_SCXI_DIO_ENA_REG 0x21c +#define NI_M_CDI_FIFO_DATA_REG 0x220 +#define NI_M_CDO_FIFO_DATA_REG 0x220 +#define NI_M_CDIO_STATUS_REG 0x224 +#define NI_M_CDIO_STATUS_CDI_OVERFLOW BIT(20) +#define NI_M_CDIO_STATUS_CDI_OVERRUN BIT(19) +#define NI_M_CDIO_STATUS_CDI_ERROR (NI_M_CDIO_STATUS_CDI_OVERFLOW | \ + NI_M_CDIO_STATUS_CDI_OVERRUN) +#define NI_M_CDIO_STATUS_CDI_FIFO_REQ BIT(18) +#define NI_M_CDIO_STATUS_CDI_FIFO_FULL BIT(17) +#define NI_M_CDIO_STATUS_CDI_FIFO_EMPTY BIT(16) +#define NI_M_CDIO_STATUS_CDO_UNDERFLOW BIT(4) +#define NI_M_CDIO_STATUS_CDO_OVERRUN BIT(3) +#define NI_M_CDIO_STATUS_CDO_ERROR (NI_M_CDIO_STATUS_CDO_UNDERFLOW | \ + NI_M_CDIO_STATUS_CDO_OVERRUN) +#define NI_M_CDIO_STATUS_CDO_FIFO_REQ BIT(2) +#define NI_M_CDIO_STATUS_CDO_FIFO_FULL BIT(1) +#define NI_M_CDIO_STATUS_CDO_FIFO_EMPTY BIT(0) +#define NI_M_CDIO_CMD_REG 0x224 +#define NI_M_CDI_CMD_SW_UPDATE BIT(20) +#define NI_M_CDO_CMD_SW_UPDATE BIT(19) +#define NI_M_CDO_CMD_F_E_INT_ENA_CLR BIT(17) +#define NI_M_CDO_CMD_F_E_INT_ENA_SET BIT(16) +#define NI_M_CDI_CMD_ERR_INT_CONFIRM BIT(15) +#define NI_M_CDO_CMD_ERR_INT_CONFIRM BIT(14) +#define NI_M_CDI_CMD_F_REQ_INT_ENA_CLR BIT(13) +#define NI_M_CDI_CMD_F_REQ_INT_ENA_SET BIT(12) +#define NI_M_CDO_CMD_F_REQ_INT_ENA_CLR BIT(11) +#define NI_M_CDO_CMD_F_REQ_INT_ENA_SET BIT(10) +#define NI_M_CDI_CMD_ERR_INT_ENA_CLR BIT(9) +#define NI_M_CDI_CMD_ERR_INT_ENA_SET BIT(8) +#define NI_M_CDO_CMD_ERR_INT_ENA_CLR BIT(7) +#define NI_M_CDO_CMD_ERR_INT_ENA_SET BIT(6) +#define NI_M_CDI_CMD_RESET BIT(5) +#define NI_M_CDO_CMD_RESET BIT(4) +#define NI_M_CDI_CMD_ARM BIT(3) +#define NI_M_CDI_CMD_DISARM BIT(2) +#define NI_M_CDO_CMD_ARM BIT(1) +#define NI_M_CDO_CMD_DISARM BIT(0) +#define NI_M_CDI_MODE_REG 0x228 +#define NI_M_CDI_MODE_DATA_LANE(x) (((x) & 0x3) << 12) +#define NI_M_CDI_MODE_DATA_LANE_MASK NI_M_CDI_MODE_DATA_LANE(3) +#define NI_M_CDI_MODE_DATA_LANE_0_15 NI_M_CDI_MODE_DATA_LANE(0) +#define NI_M_CDI_MODE_DATA_LANE_16_31 NI_M_CDI_MODE_DATA_LANE(1) +#define NI_M_CDI_MODE_DATA_LANE_0_7 NI_M_CDI_MODE_DATA_LANE(0) +#define NI_M_CDI_MODE_DATA_LANE_8_15 NI_M_CDI_MODE_DATA_LANE(1) +#define NI_M_CDI_MODE_DATA_LANE_16_23 NI_M_CDI_MODE_DATA_LANE(2) +#define NI_M_CDI_MODE_DATA_LANE_24_31 NI_M_CDI_MODE_DATA_LANE(3) +#define NI_M_CDI_MODE_FIFO_MODE BIT(11) +#define NI_M_CDI_MODE_POLARITY BIT(10) +#define NI_M_CDI_MODE_HALT_ON_ERROR BIT(9) +#define NI_M_CDI_MODE_SAMPLE_SRC(x) (((x) & 0x3f) << 0) +#define NI_M_CDI_MODE_SAMPLE_SRC_MASK NI_M_CDI_MODE_SAMPLE_SRC(0x3f) +#define NI_M_CDO_MODE_REG 0x22c +#define NI_M_CDO_MODE_DATA_LANE(x) (((x) & 0x3) << 12) +#define NI_M_CDO_MODE_DATA_LANE_MASK NI_M_CDO_MODE_DATA_LANE(3) +#define NI_M_CDO_MODE_DATA_LANE_0_15 NI_M_CDO_MODE_DATA_LANE(0) +#define NI_M_CDO_MODE_DATA_LANE_16_31 NI_M_CDO_MODE_DATA_LANE(1) +#define NI_M_CDO_MODE_DATA_LANE_0_7 NI_M_CDO_MODE_DATA_LANE(0) +#define NI_M_CDO_MODE_DATA_LANE_8_15 NI_M_CDO_MODE_DATA_LANE(1) +#define NI_M_CDO_MODE_DATA_LANE_16_23 NI_M_CDO_MODE_DATA_LANE(2) +#define NI_M_CDO_MODE_DATA_LANE_24_31 NI_M_CDO_MODE_DATA_LANE(3) +#define NI_M_CDO_MODE_FIFO_MODE BIT(11) +#define NI_M_CDO_MODE_POLARITY BIT(10) +#define NI_M_CDO_MODE_HALT_ON_ERROR BIT(9) +#define NI_M_CDO_MODE_RETRANSMIT BIT(8) +#define NI_M_CDO_MODE_SAMPLE_SRC(x) (((x) & 0x3f) << 0) +#define NI_M_CDO_MODE_SAMPLE_SRC_MASK NI_M_CDO_MODE_SAMPLE_SRC(0x3f) +#define NI_M_CDI_MASK_ENA_REG 0x230 +#define NI_M_CDO_MASK_ENA_REG 0x234 +#define NI_M_STATIC_AI_CTRL_REG(x) ((x) ? (0x260 + (x)) : 0x064) +#define NI_M_AO_REF_ATTENUATION_REG(x) (0x264 + (x)) +#define NI_M_AO_REF_ATTENUATION_X5 BIT(0) + +enum { + ai_gain_16 = 0, + ai_gain_8, + ai_gain_14, + ai_gain_4, + ai_gain_611x, + ai_gain_622x, + ai_gain_628x, + ai_gain_6143 }; -static inline unsigned int DACx_Direct_Data_671x(int channel) -{ - return channel; -} -enum AO_Misc_611x_Bits { - CLEAR_WG = 1, +enum caldac_enum { + caldac_none = 0, + mb88341, + dac8800, + dac8043, + ad8522, + ad8804, + ad8842, + ad8804_debug }; -enum cs5529_configuration_bits { - CSCFG_CAL_CONTROL_MASK = 0x7, - CSCFG_SELF_CAL_OFFSET = 0x1, - CSCFG_SELF_CAL_GAIN = 0x2, - CSCFG_SELF_CAL_OFFSET_GAIN = 0x3, - CSCFG_SYSTEM_CAL_OFFSET = 0x5, - CSCFG_SYSTEM_CAL_GAIN = 0x6, - CSCFG_DONE = 1 << 3, - CSCFG_POWER_SAVE_SELECT = 1 << 4, - CSCFG_PORT_MODE = 1 << 5, - CSCFG_RESET_VALID = 1 << 6, - CSCFG_RESET = 1 << 7, - CSCFG_UNIPOLAR = 1 << 12, - CSCFG_WORD_RATE_2180_CYCLES = 0x0 << 13, - CSCFG_WORD_RATE_1092_CYCLES = 0x1 << 13, - CSCFG_WORD_RATE_532_CYCLES = 0x2 << 13, - CSCFG_WORD_RATE_388_CYCLES = 0x3 << 13, - CSCFG_WORD_RATE_324_CYCLES = 0x4 << 13, - CSCFG_WORD_RATE_17444_CYCLES = 0x5 << 13, - CSCFG_WORD_RATE_8724_CYCLES = 0x6 << 13, - CSCFG_WORD_RATE_4364_CYCLES = 0x7 << 13, - CSCFG_WORD_RATE_MASK = 0x7 << 13, - CSCFG_LOW_POWER = 1 << 16, -}; -static inline unsigned int CS5529_CONFIG_DOUT(int output) -{ - return 1 << (18 + output); -} - -static inline unsigned int CS5529_CONFIG_AOUT(int output) -{ - return 1 << (22 + output); -} - -enum cs5529_command_bits { - CSCMD_POWER_SAVE = 0x1, - CSCMD_REGISTER_SELECT_MASK = 0xe, - CSCMD_OFFSET_REGISTER = 0x0, - CSCMD_GAIN_REGISTER = 0x2, - CSCMD_CONFIG_REGISTER = 0x4, - CSCMD_READ = 0x10, - CSCMD_CONTINUOUS_CONVERSIONS = 0x20, - CSCMD_SINGLE_CONVERSION = 0x40, - CSCMD_COMMAND = 0x80, -}; -enum cs5529_status_bits { - CSS_ADC_BUSY = 0x1, - CSS_OSC_DETECT = 0x2, /* indicates adc error */ - CSS_OVERRANGE = 0x4, -}; -#define SerDacLd(x) (0x08<<(x)) - -/* - This is stuff unique to the NI E series drivers, - but I thought I'd put it here anyway. -*/ -enum { ai_gain_16 = - 0, ai_gain_8, ai_gain_14, ai_gain_4, ai_gain_611x, ai_gain_622x, - ai_gain_628x, ai_gain_6143 -}; -enum caldac_enum { caldac_none = 0, mb88341, dac8800, dac8043, ad8522, - ad8804, ad8842, ad8804_debug -}; enum ni_reg_type { ni_reg_normal = 0x0, ni_reg_611x = 0x1, @@ -918,467 +941,6 @@ enum ni_reg_type { ni_reg_6143 = 0x20 }; -static const struct comedi_lrange range_ni_E_ao_ext; - -enum m_series_register_offsets { - M_Offset_CDIO_DMA_Select = 0x7, /* write */ - M_Offset_SCXI_Status = 0x7, /* read */ - M_Offset_AI_AO_Select = 0x9, /* write, same offset as e-series */ - M_Offset_SCXI_Serial_Data_In = 0x9, /* read */ - M_Offset_G0_G1_Select = 0xb, /* write, same offset as e-series */ - M_Offset_Misc_Command = 0xf, - M_Offset_SCXI_Serial_Data_Out = 0x11, - M_Offset_SCXI_Control = 0x13, - M_Offset_SCXI_Output_Enable = 0x15, - M_Offset_AI_FIFO_Data = 0x1c, - M_Offset_Static_Digital_Output = 0x24, /* write */ - M_Offset_Static_Digital_Input = 0x24, /* read */ - M_Offset_DIO_Direction = 0x28, - M_Offset_Cal_PWM = 0x40, - M_Offset_AI_Config_FIFO_Data = 0x5e, - M_Offset_Interrupt_C_Enable = 0x88, /* write */ - M_Offset_Interrupt_C_Status = 0x88, /* read */ - M_Offset_Analog_Trigger_Control = 0x8c, - M_Offset_AO_Serial_Interrupt_Enable = 0xa0, - M_Offset_AO_Serial_Interrupt_Ack = 0xa1, /* write */ - M_Offset_AO_Serial_Interrupt_Status = 0xa1, /* read */ - M_Offset_AO_Calibration = 0xa3, - M_Offset_AO_FIFO_Data = 0xa4, - M_Offset_PFI_Filter = 0xb0, - M_Offset_RTSI_Filter = 0xb4, - M_Offset_SCXI_Legacy_Compatibility = 0xbc, - M_Offset_Interrupt_A_Ack = 0x104, /* write */ - M_Offset_AI_Status_1 = 0x104, /* read */ - M_Offset_Interrupt_B_Ack = 0x106, /* write */ - M_Offset_AO_Status_1 = 0x106, /* read */ - M_Offset_AI_Command_2 = 0x108, /* write */ - M_Offset_G01_Status = 0x108, /* read */ - M_Offset_AO_Command_2 = 0x10a, - M_Offset_AO_Status_2 = 0x10c, /* read */ - M_Offset_G0_Command = 0x10c, /* write */ - M_Offset_G1_Command = 0x10e, /* write */ - M_Offset_G0_HW_Save = 0x110, - M_Offset_G0_HW_Save_High = 0x110, - M_Offset_AI_Command_1 = 0x110, - M_Offset_G0_HW_Save_Low = 0x112, - M_Offset_AO_Command_1 = 0x112, - M_Offset_G1_HW_Save = 0x114, - M_Offset_G1_HW_Save_High = 0x114, - M_Offset_G1_HW_Save_Low = 0x116, - M_Offset_AI_Mode_1 = 0x118, - M_Offset_G0_Save = 0x118, - M_Offset_G0_Save_High = 0x118, - M_Offset_AI_Mode_2 = 0x11a, - M_Offset_G0_Save_Low = 0x11a, - M_Offset_AI_SI_Load_A = 0x11c, - M_Offset_G1_Save = 0x11c, - M_Offset_G1_Save_High = 0x11c, - M_Offset_G1_Save_Low = 0x11e, - M_Offset_AI_SI_Load_B = 0x120, /* write */ - M_Offset_AO_UI_Save = 0x120, /* read */ - M_Offset_AI_SC_Load_A = 0x124, /* write */ - M_Offset_AO_BC_Save = 0x124, /* read */ - M_Offset_AI_SC_Load_B = 0x128, /* write */ - M_Offset_AO_UC_Save = 0x128, /* read */ - M_Offset_AI_SI2_Load_A = 0x12c, - M_Offset_AI_SI2_Load_B = 0x130, - M_Offset_G0_Mode = 0x134, - M_Offset_G1_Mode = 0x136, /* write */ - M_Offset_Joint_Status_1 = 0x136, /* read */ - M_Offset_G0_Load_A = 0x138, - M_Offset_Joint_Status_2 = 0x13a, - M_Offset_G0_Load_B = 0x13c, - M_Offset_G1_Load_A = 0x140, - M_Offset_G1_Load_B = 0x144, - M_Offset_G0_Input_Select = 0x148, - M_Offset_G1_Input_Select = 0x14a, - M_Offset_AO_Mode_1 = 0x14c, - M_Offset_AO_Mode_2 = 0x14e, - M_Offset_AO_UI_Load_A = 0x150, - M_Offset_AO_UI_Load_B = 0x154, - M_Offset_AO_BC_Load_A = 0x158, - M_Offset_AO_BC_Load_B = 0x15c, - M_Offset_AO_UC_Load_A = 0x160, - M_Offset_AO_UC_Load_B = 0x164, - M_Offset_Clock_and_FOUT = 0x170, - M_Offset_IO_Bidirection_Pin = 0x172, - M_Offset_RTSI_Trig_Direction = 0x174, - M_Offset_Interrupt_Control = 0x176, - M_Offset_AI_Output_Control = 0x178, - M_Offset_Analog_Trigger_Etc = 0x17a, - M_Offset_AI_START_STOP_Select = 0x17c, - M_Offset_AI_Trigger_Select = 0x17e, - M_Offset_AI_SI_Save = 0x180, /* read */ - M_Offset_AI_DIV_Load_A = 0x180, /* write */ - M_Offset_AI_SC_Save = 0x184, /* read */ - M_Offset_AO_Start_Select = 0x184, /* write */ - M_Offset_AO_Trigger_Select = 0x186, - M_Offset_AO_Mode_3 = 0x18c, - M_Offset_G0_Autoincrement = 0x188, - M_Offset_G1_Autoincrement = 0x18a, - M_Offset_Joint_Reset = 0x190, - M_Offset_Interrupt_A_Enable = 0x192, - M_Offset_Interrupt_B_Enable = 0x196, - M_Offset_AI_Personal = 0x19a, - M_Offset_AO_Personal = 0x19c, - M_Offset_RTSI_Trig_A_Output = 0x19e, - M_Offset_RTSI_Trig_B_Output = 0x1a0, - M_Offset_RTSI_Shared_MUX = 0x1a2, - M_Offset_AO_Output_Control = 0x1ac, - M_Offset_AI_Mode_3 = 0x1ae, - M_Offset_Configuration_Memory_Clear = 0x1a4, - M_Offset_AI_FIFO_Clear = 0x1a6, - M_Offset_AO_FIFO_Clear = 0x1a8, - M_Offset_G0_Counting_Mode = 0x1b0, - M_Offset_G1_Counting_Mode = 0x1b2, - M_Offset_G0_Second_Gate = 0x1b4, - M_Offset_G1_Second_Gate = 0x1b6, - M_Offset_G0_DMA_Config = 0x1b8, /* write */ - M_Offset_G0_DMA_Status = 0x1b8, /* read */ - M_Offset_G1_DMA_Config = 0x1ba, /* write */ - M_Offset_G1_DMA_Status = 0x1ba, /* read */ - M_Offset_G0_MSeries_ABZ = 0x1c0, - M_Offset_G1_MSeries_ABZ = 0x1c2, - M_Offset_Clock_and_Fout2 = 0x1c4, - M_Offset_PLL_Control = 0x1c6, - M_Offset_PLL_Status = 0x1c8, - M_Offset_PFI_Output_Select_1 = 0x1d0, - M_Offset_PFI_Output_Select_2 = 0x1d2, - M_Offset_PFI_Output_Select_3 = 0x1d4, - M_Offset_PFI_Output_Select_4 = 0x1d6, - M_Offset_PFI_Output_Select_5 = 0x1d8, - M_Offset_PFI_Output_Select_6 = 0x1da, - M_Offset_PFI_DI = 0x1dc, - M_Offset_PFI_DO = 0x1de, - M_Offset_AI_Config_FIFO_Bypass = 0x218, - M_Offset_SCXI_DIO_Enable = 0x21c, - M_Offset_CDI_FIFO_Data = 0x220, /* read */ - M_Offset_CDO_FIFO_Data = 0x220, /* write */ - M_Offset_CDIO_Status = 0x224, /* read */ - M_Offset_CDIO_Command = 0x224, /* write */ - M_Offset_CDI_Mode = 0x228, - M_Offset_CDO_Mode = 0x22c, - M_Offset_CDI_Mask_Enable = 0x230, - M_Offset_CDO_Mask_Enable = 0x234, -}; -static inline int M_Offset_AO_Waveform_Order(int channel) -{ - return 0xc2 + 0x4 * channel; -}; - -static inline int M_Offset_AO_Config_Bank(int channel) -{ - return 0xc3 + 0x4 * channel; -}; - -static inline int M_Offset_DAC_Direct_Data(int channel) -{ - return 0xc0 + 0x4 * channel; -} - -static inline int M_Offset_Gen_PWM(int channel) -{ - return 0x44 + 0x2 * channel; -} - -static inline int M_Offset_Static_AI_Control(int i) -{ - int offset[] = { - 0x64, - 0x261, - 0x262, - 0x263, - }; - if (((unsigned)i) >= ARRAY_SIZE(offset)) { - pr_err("%s: invalid channel=%i\n", __func__, i); - return offset[0]; - } - return offset[i]; -}; - -static inline int M_Offset_AO_Reference_Attenuation(int channel) -{ - int offset[] = { - 0x264, - 0x265, - 0x266, - 0x267 - }; - if (((unsigned)channel) >= ARRAY_SIZE(offset)) { - pr_err("%s: invalid channel=%i\n", __func__, channel); - return offset[0]; - } - return offset[channel]; -}; - -static inline unsigned M_Offset_PFI_Output_Select(unsigned n) -{ - if (n < 1 || n > NUM_PFI_OUTPUT_SELECT_REGS) { - pr_err("%s: invalid pfi output select register=%i\n", - __func__, n); - return M_Offset_PFI_Output_Select_1; - } - return M_Offset_PFI_Output_Select_1 + (n - 1) * 2; -} - -enum MSeries_AI_Config_FIFO_Data_Bits { - MSeries_AI_Config_Channel_Type_Mask = 0x7 << 6, - MSeries_AI_Config_Channel_Type_Calibration_Bits = 0x0, - MSeries_AI_Config_Channel_Type_Differential_Bits = 0x1 << 6, - MSeries_AI_Config_Channel_Type_Common_Ref_Bits = 0x2 << 6, - MSeries_AI_Config_Channel_Type_Ground_Ref_Bits = 0x3 << 6, - MSeries_AI_Config_Channel_Type_Aux_Bits = 0x5 << 6, - MSeries_AI_Config_Channel_Type_Ghost_Bits = 0x7 << 6, - MSeries_AI_Config_Polarity_Bit = 0x1000, /* 0 for 2's complement encoding */ - MSeries_AI_Config_Dither_Bit = 0x2000, - MSeries_AI_Config_Last_Channel_Bit = 0x4000, -}; -static inline unsigned MSeries_AI_Config_Channel_Bits(unsigned channel) -{ - return channel & 0xf; -} - -static inline unsigned MSeries_AI_Config_Bank_Bits(enum ni_reg_type reg_type, - unsigned channel) -{ - unsigned bits = channel & 0x30; - if (reg_type == ni_reg_622x) { - if (channel & 0x40) - bits |= 0x400; - } - return bits; -} - -static inline unsigned MSeries_AI_Config_Gain_Bits(unsigned range) -{ - return (range & 0x7) << 9; -} - -enum MSeries_Clock_and_Fout2_Bits { - MSeries_PLL_In_Source_Select_RTSI0_Bits = 0xb, - MSeries_PLL_In_Source_Select_Star_Trigger_Bits = 0x14, - MSeries_PLL_In_Source_Select_RTSI7_Bits = 0x1b, - MSeries_PLL_In_Source_Select_PXI_Clock10 = 0x1d, - MSeries_PLL_In_Source_Select_Mask = 0x1f, - MSeries_Timebase1_Select_Bit = 0x20, /* use PLL for timebase 1 */ - MSeries_Timebase3_Select_Bit = 0x40, /* use PLL for timebase 3 */ - /* use 10MHz instead of 20MHz for RTSI clock frequency. Appears - to have no effect, at least on pxi-6281, which always uses - 20MHz rtsi clock frequency */ - MSeries_RTSI_10MHz_Bit = 0x80 -}; -static inline unsigned MSeries_PLL_In_Source_Select_RTSI_Bits(unsigned - RTSI_channel) -{ - if (RTSI_channel > 7) { - pr_err("%s: bug, invalid RTSI_channel=%i\n", __func__, - RTSI_channel); - return 0; - } - if (RTSI_channel == 7) - return MSeries_PLL_In_Source_Select_RTSI7_Bits; - else - return MSeries_PLL_In_Source_Select_RTSI0_Bits + RTSI_channel; -} - -enum MSeries_PLL_Control_Bits { - MSeries_PLL_Enable_Bit = 0x1000, - MSeries_PLL_VCO_Mode_200_325MHz_Bits = 0x0, - MSeries_PLL_VCO_Mode_175_225MHz_Bits = 0x2000, - MSeries_PLL_VCO_Mode_100_225MHz_Bits = 0x4000, - MSeries_PLL_VCO_Mode_75_150MHz_Bits = 0x6000, -}; -static inline unsigned MSeries_PLL_Divisor_Bits(unsigned divisor) -{ - static const unsigned max_divisor = 0x10; - if (divisor < 1 || divisor > max_divisor) { - pr_err("%s: bug, invalid divisor=%i\n", __func__, divisor); - return 0; - } - return (divisor & 0xf) << 8; -} - -static inline unsigned MSeries_PLL_Multiplier_Bits(unsigned multiplier) -{ - static const unsigned max_multiplier = 0x100; - if (multiplier < 1 || multiplier > max_multiplier) { - pr_err("%s: bug, invalid multiplier=%i\n", __func__, - multiplier); - return 0; - } - return multiplier & 0xff; -} - -enum MSeries_PLL_Status { - MSeries_PLL_Locked_Bit = 0x1 -}; - -enum MSeries_AI_Config_FIFO_Bypass_Bits { - MSeries_AI_Bypass_Channel_Mask = 0x7, - MSeries_AI_Bypass_Bank_Mask = 0x78, - MSeries_AI_Bypass_Cal_Sel_Pos_Mask = 0x380, - MSeries_AI_Bypass_Cal_Sel_Neg_Mask = 0x1c00, - MSeries_AI_Bypass_Mode_Mux_Mask = 0x6000, - MSeries_AO_Bypass_AO_Cal_Sel_Mask = 0x38000, - MSeries_AI_Bypass_Gain_Mask = 0x1c0000, - MSeries_AI_Bypass_Dither_Bit = 0x200000, - MSeries_AI_Bypass_Polarity_Bit = 0x400000, /* 0 for 2's complement encoding */ - MSeries_AI_Bypass_Config_FIFO_Bit = 0x80000000 -}; -static inline unsigned MSeries_AI_Bypass_Cal_Sel_Pos_Bits(int - calibration_source) -{ - return (calibration_source << 7) & MSeries_AI_Bypass_Cal_Sel_Pos_Mask; -} - -static inline unsigned MSeries_AI_Bypass_Cal_Sel_Neg_Bits(int - calibration_source) -{ - return (calibration_source << 10) & MSeries_AI_Bypass_Cal_Sel_Pos_Mask; -} - -static inline unsigned MSeries_AI_Bypass_Gain_Bits(int gain) -{ - return (gain << 18) & MSeries_AI_Bypass_Gain_Mask; -} - -enum MSeries_AO_Config_Bank_Bits { - MSeries_AO_DAC_Offset_Select_Mask = 0x7, - MSeries_AO_DAC_Offset_0V_Bits = 0x0, - MSeries_AO_DAC_Offset_5V_Bits = 0x1, - MSeries_AO_DAC_Reference_Mask = 0x38, - MSeries_AO_DAC_Reference_10V_Internal_Bits = 0x0, - MSeries_AO_DAC_Reference_5V_Internal_Bits = 0x8, - MSeries_AO_Update_Timed_Bit = 0x40, - MSeries_AO_Bipolar_Bit = 0x80 /* turns on 2's complement encoding */ -}; - -enum MSeries_AO_Reference_Attenuation_Bits { - MSeries_Attenuate_x5_Bit = 0x1 -}; - -static inline unsigned MSeries_Cal_PWM_High_Time_Bits(unsigned count) -{ - return (count << 16) & 0xffff0000; -} - -static inline unsigned MSeries_Cal_PWM_Low_Time_Bits(unsigned count) -{ - return count & 0xffff; -} - -static inline unsigned MSeries_PFI_Output_Select_Mask(unsigned channel) -{ - return 0x1f << (channel % 3) * 5; -}; - -static inline unsigned MSeries_PFI_Output_Select_Bits(unsigned channel, - unsigned source) -{ - return (source & 0x1f) << ((channel % 3) * 5); -}; - -/* inverse to MSeries_PFI_Output_Select_Bits */ -static inline unsigned MSeries_PFI_Output_Select_Source(unsigned channel, - unsigned bits) -{ - return (bits >> ((channel % 3) * 5)) & 0x1f; -}; - -static inline unsigned MSeries_PFI_Filter_Select_Mask(unsigned channel) -{ - return 0x3 << (channel * 2); -} - -static inline unsigned MSeries_PFI_Filter_Select_Bits(unsigned channel, - unsigned filter) -{ - return (filter << (channel * - 2)) & MSeries_PFI_Filter_Select_Mask(channel); -} - -enum CDIO_DMA_Select_Bits { - CDI_DMA_Select_Shift = 0, - CDI_DMA_Select_Mask = 0xf, - CDO_DMA_Select_Shift = 4, - CDO_DMA_Select_Mask = 0xf << CDO_DMA_Select_Shift -}; - -enum CDIO_Status_Bits { - CDO_FIFO_Empty_Bit = 0x1, - CDO_FIFO_Full_Bit = 0x2, - CDO_FIFO_Request_Bit = 0x4, - CDO_Overrun_Bit = 0x8, - CDO_Underflow_Bit = 0x10, - CDI_FIFO_Empty_Bit = 0x10000, - CDI_FIFO_Full_Bit = 0x20000, - CDI_FIFO_Request_Bit = 0x40000, - CDI_Overrun_Bit = 0x80000, - CDI_Overflow_Bit = 0x100000 -}; - -enum CDIO_Command_Bits { - CDO_Disarm_Bit = 0x1, - CDO_Arm_Bit = 0x2, - CDI_Disarm_Bit = 0x4, - CDI_Arm_Bit = 0x8, - CDO_Reset_Bit = 0x10, - CDI_Reset_Bit = 0x20, - CDO_Error_Interrupt_Enable_Set_Bit = 0x40, - CDO_Error_Interrupt_Enable_Clear_Bit = 0x80, - CDI_Error_Interrupt_Enable_Set_Bit = 0x100, - CDI_Error_Interrupt_Enable_Clear_Bit = 0x200, - CDO_FIFO_Request_Interrupt_Enable_Set_Bit = 0x400, - CDO_FIFO_Request_Interrupt_Enable_Clear_Bit = 0x800, - CDI_FIFO_Request_Interrupt_Enable_Set_Bit = 0x1000, - CDI_FIFO_Request_Interrupt_Enable_Clear_Bit = 0x2000, - CDO_Error_Interrupt_Confirm_Bit = 0x4000, - CDI_Error_Interrupt_Confirm_Bit = 0x8000, - CDO_Empty_FIFO_Interrupt_Enable_Set_Bit = 0x10000, - CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit = 0x20000, - CDO_SW_Update_Bit = 0x80000, - CDI_SW_Update_Bit = 0x100000 -}; - -enum CDI_Mode_Bits { - CDI_Sample_Source_Select_Mask = 0x3f, - CDI_Halt_On_Error_Bit = 0x200, - CDI_Polarity_Bit = 0x400, /* sample clock on falling edge */ - CDI_FIFO_Mode_Bit = 0x800, /* set for half full mode, clear for not empty mode */ - CDI_Data_Lane_Mask = 0x3000, /* data lanes specify which dio channels map to byte or word accesses to the dio fifos */ - CDI_Data_Lane_0_15_Bits = 0x0, - CDI_Data_Lane_16_31_Bits = 0x1000, - CDI_Data_Lane_0_7_Bits = 0x0, - CDI_Data_Lane_8_15_Bits = 0x1000, - CDI_Data_Lane_16_23_Bits = 0x2000, - CDI_Data_Lane_24_31_Bits = 0x3000 -}; - -enum CDO_Mode_Bits { - CDO_Sample_Source_Select_Mask = 0x3f, - CDO_Retransmit_Bit = 0x100, - CDO_Halt_On_Error_Bit = 0x200, - CDO_Polarity_Bit = 0x400, /* sample clock on falling edge */ - CDO_FIFO_Mode_Bit = 0x800, /* set for half full mode, clear for not full mode */ - CDO_Data_Lane_Mask = 0x3000, /* data lanes specify which dio channels map to byte or word accesses to the dio fifos */ - CDO_Data_Lane_0_15_Bits = 0x0, - CDO_Data_Lane_16_31_Bits = 0x1000, - CDO_Data_Lane_0_7_Bits = 0x0, - CDO_Data_Lane_8_15_Bits = 0x1000, - CDO_Data_Lane_16_23_Bits = 0x2000, - CDO_Data_Lane_24_31_Bits = 0x3000 -}; - -enum Interrupt_C_Enable_Bits { - Interrupt_Group_C_Enable_Bit = 0x1 -}; - -enum Interrupt_C_Status_Bits { - Interrupt_Group_C_Status_Bit = 0x1 -}; - -#define M_SERIES_EEPROM_SIZE 1024 - struct ni_board_struct { const char *name; int device_id; @@ -1405,9 +967,13 @@ struct ni_board_struct { enum caldac_enum caldac[3]; }; -#define MAX_N_CALDACS 34 -#define MAX_N_AO_CHAN 8 -#define NUM_GPCT 2 +#define MAX_N_CALDACS 34 +#define MAX_N_AO_CHAN 8 +#define NUM_GPCT 2 + +#define NUM_PFI_OUTPUT_SELECT_REGS 6 + +#define M_SERIES_EEPROM_SIZE 1024 struct ni_private { unsigned short dio_output; @@ -1415,8 +981,11 @@ struct ni_private { int aimode; unsigned int ai_calib_source; unsigned int ai_calib_source_enabled; + /* protects access to windowed registers */ spinlock_t window_lock; + /* protects interrupt/dma register access */ spinlock_t soft_reg_copy_lock; + /* protects mite DMA channel request/release */ spinlock_t mite_channel_lock; int changain_state; @@ -1488,4 +1057,6 @@ struct ni_private { unsigned int is_6713:1; }; +static const struct comedi_lrange range_ni_E_ao_ext; + #endif /* _COMEDI_NI_STC_H */ diff --git a/drivers/staging/comedi/drivers/pcl812.c b/drivers/staging/comedi/drivers/pcl812.c index 03a3fd6cd918..48f6cdf440b9 100644 --- a/drivers/staging/comedi/drivers/pcl812.c +++ b/drivers/staging/comedi/drivers/pcl812.c @@ -507,11 +507,11 @@ static const struct pcl812_board boardtypes[] = { struct pcl812_private { struct comedi_isadma *dma; - unsigned char range_correction; /* =1 we must add 1 to range number */ + unsigned char range_correction; /* =1 we must add 1 to range number */ unsigned int last_ai_chanspec; - unsigned char mode_reg_int; /* there is stored INT number for some card */ - unsigned int ai_poll_ptr; /* how many sampes transfer poll */ - unsigned int max_812_ai_mode0_rangewait; /* setling time for gain */ + unsigned char mode_reg_int; /* stored INT number for some cards */ + unsigned int ai_poll_ptr; /* how many samples transfer poll */ + unsigned int max_812_ai_mode0_rangewait; /* settling time for gain */ unsigned int use_diff:1; unsigned int use_mpc508:1; unsigned int use_ext_trg:1; @@ -1155,7 +1155,7 @@ static int pcl812_attach(struct comedi_device *dev, struct comedi_devconfig *it) /* we need an IRQ to do DMA on channel 3 or 1 */ if (dev->irq && board->has_dma) - pcl812_alloc_dma(dev, it->options[2]); + pcl812_alloc_dma(dev, it->options[2]); /* differential analog inputs? */ switch (board->board_type) { diff --git a/drivers/staging/comedi/drivers/pcl816.c b/drivers/staging/comedi/drivers/pcl816.c index 1ccb2f19f4be..781b321587dc 100644 --- a/drivers/staging/comedi/drivers/pcl816.c +++ b/drivers/staging/comedi/drivers/pcl816.c @@ -323,7 +323,7 @@ static int check_channel_list(struct comedi_device *dev, /* check whole chanlist */ for (i = 0, segpos = 0; i < chanlen; i++) { - if (chanlist[i] != chansegment[i % seglen]) { + if (chanlist[i] != chansegment[i % seglen]) { dev_dbg(dev->class_dev, "bad channel or range number! chanlist[%i]=%d,%d,%d and not %d,%d,%d!\n", i, CR_CHAN(chansegment[i]), diff --git a/drivers/staging/comedi/drivers/serial2002.c b/drivers/staging/comedi/drivers/serial2002.c index 304ebff119ee..83da162deb52 100644 --- a/drivers/staging/comedi/drivers/serial2002.c +++ b/drivers/staging/comedi/drivers/serial2002.c @@ -373,7 +373,7 @@ static int serial2002_setup_subdevice(struct comedi_subdevice *s, if (cfg[j].kind == kind) { if (mapping) mapping[chan] = j; - if (range) { + if (range && range_table_list) { range[j].length = 1; range[j].range.min = cfg[j].min; range[j].range.max = cfg[j].max; diff --git a/drivers/staging/comedi/drivers/vmk80xx.c b/drivers/staging/comedi/drivers/vmk80xx.c index a0906685e27f..3af075aa3946 100644 --- a/drivers/staging/comedi/drivers/vmk80xx.c +++ b/drivers/staging/comedi/drivers/vmk80xx.c @@ -700,7 +700,7 @@ static int vmk80xx_alloc_usb_buffers(struct comedi_device *dev) static int vmk80xx_init_subdevices(struct comedi_device *dev) { - const struct vmk80xx_board *boardinfo = dev->board_ptr; + const struct vmk80xx_board *board = dev->board_ptr; struct vmk80xx_private *devpriv = dev->private; struct comedi_subdevice *s; int n_subd; @@ -722,18 +722,18 @@ static int vmk80xx_init_subdevices(struct comedi_device *dev) s = &dev->subdevices[0]; s->type = COMEDI_SUBD_AI; s->subdev_flags = SDF_READABLE | SDF_GROUND; - s->n_chan = boardinfo->ai_nchans; - s->maxdata = boardinfo->ai_maxdata; - s->range_table = boardinfo->range; + s->n_chan = board->ai_nchans; + s->maxdata = board->ai_maxdata; + s->range_table = board->range; s->insn_read = vmk80xx_ai_insn_read; /* Analog output subdevice */ s = &dev->subdevices[1]; s->type = COMEDI_SUBD_AO; s->subdev_flags = SDF_WRITABLE | SDF_GROUND; - s->n_chan = boardinfo->ao_nchans; + s->n_chan = board->ao_nchans; s->maxdata = 0x00ff; - s->range_table = boardinfo->range; + s->range_table = board->range; s->insn_write = vmk80xx_ao_insn_write; if (devpriv->model == VMK8061_MODEL) { s->subdev_flags |= SDF_READABLE; @@ -744,7 +744,7 @@ static int vmk80xx_init_subdevices(struct comedi_device *dev) s = &dev->subdevices[2]; s->type = COMEDI_SUBD_DI; s->subdev_flags = SDF_READABLE; - s->n_chan = boardinfo->di_nchans; + s->n_chan = board->di_nchans; s->maxdata = 1; s->range_table = &range_digital; s->insn_bits = vmk80xx_di_insn_bits; @@ -763,7 +763,7 @@ static int vmk80xx_init_subdevices(struct comedi_device *dev) s->type = COMEDI_SUBD_COUNTER; s->subdev_flags = SDF_READABLE; s->n_chan = 2; - s->maxdata = boardinfo->cnt_maxdata; + s->maxdata = board->cnt_maxdata; s->insn_read = vmk80xx_cnt_insn_read; s->insn_config = vmk80xx_cnt_insn_config; if (devpriv->model == VMK8055_MODEL) { @@ -776,8 +776,8 @@ static int vmk80xx_init_subdevices(struct comedi_device *dev) s = &dev->subdevices[5]; s->type = COMEDI_SUBD_PWM; s->subdev_flags = SDF_READABLE | SDF_WRITABLE; - s->n_chan = boardinfo->pwm_nchans; - s->maxdata = boardinfo->pwm_maxdata; + s->n_chan = board->pwm_nchans; + s->maxdata = board->pwm_maxdata; s->insn_read = vmk80xx_pwm_insn_read; s->insn_write = vmk80xx_pwm_insn_write; } @@ -791,19 +791,22 @@ static int vmk80xx_auto_attach(struct comedi_device *dev, unsigned long context) { struct usb_interface *intf = comedi_to_usb_interface(dev); - const struct vmk80xx_board *boardinfo; + const struct vmk80xx_board *board = NULL; struct vmk80xx_private *devpriv; int ret; - boardinfo = &vmk80xx_boardinfo[context]; - dev->board_ptr = boardinfo; - dev->board_name = boardinfo->name; + if (context < ARRAY_SIZE(vmk80xx_boardinfo)) + board = &vmk80xx_boardinfo[context]; + if (!board) + return -ENODEV; + dev->board_ptr = board; + dev->board_name = board->name; devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); if (!devpriv) return -ENOMEM; - devpriv->model = boardinfo->model; + devpriv->model = board->model; ret = vmk80xx_find_usb_endpoints(dev); if (ret) |