diff options
Diffstat (limited to 'drivers/staging/et131x/et1310_address_map.h')
| -rw-r--r-- | drivers/staging/et131x/et1310_address_map.h | 617 |
1 files changed, 174 insertions, 443 deletions
diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index e715e4dcb523..ea746ba41faf 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -149,7 +149,7 @@ * GLOBAL Module of JAGCore Address Mapping * Located at address 0x0000 */ -typedef struct _GLOBAL_t { /* Location: */ +struct global_regs { /* Location: */ u32 txq_start_addr; /* 0x0000 */ u32 txq_end_addr; /* 0x0004 */ u32 rxq_start_addr; /* 0x0008 */ @@ -165,9 +165,7 @@ typedef struct _GLOBAL_t { /* Location: */ u32 msi_config; /* 0x0030 */ u32 loopback; /* 0x0034 */ u32 watchdog_timer; /* 0x0038 */ -} GLOBAL_t, *PGLOBAL_t; - -/* END OF GLOBAL REGISTER ADDRESS MAP */ +}; /* START OF TXDMA REGISTER ADDRESS MAP */ @@ -255,7 +253,7 @@ extern inline void add_12bit(u32 *v, int n) * Tx DMA Module of JAGCore Address Mapping * Located at address 0x1000 */ -typedef struct _TXDMA_t { /* Location: */ +struct txdma_regs { /* Location: */ u32 csr; /* 0x1000 */ u32 pr_base_hi; /* 0x1004 */ u32 pr_base_lo; /* 0x1008 */ @@ -282,7 +280,7 @@ typedef struct _TXDMA_t { /* Location: */ u32 DroppedTLPCount; /* 0x105c */ u32 NewServiceComplete; /* 0x1060 */ u32 EthernetPacketCount; /* 0x1064 */ -} TXDMA_t, *PTXDMA_t; +}; /* END OF TXDMA REGISTER ADDRESS MAP */ @@ -292,45 +290,25 @@ typedef struct _TXDMA_t { /* Location: */ /* * structure for control status reg in rxdma address map * Located at address 0x2000 + * + * CSR + * 0: halt + * 1-3: tc + * 4: fbr_big_endian + * 5: psr_big_endian + * 6: pkt_big_endian + * 7: dma_big_endian + * 8-9: fbr0_size + * 10: fbr0_enable + * 11-12: fbr1_size + * 13: fbr1_enable + * 14: unused + * 15: pkt_drop_disable + * 16: pkt_done_flush + * 17: halt_status + * 18-31: unused */ -typedef union _RXDMA_CSR_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused2:14; /* bits 18-31 */ - u32 halt_status:1; /* bit 17 */ - u32 pkt_done_flush:1; /* bit 16 */ - u32 pkt_drop_disable:1; /* bit 15 */ - u32 unused1:1; /* bit 14 */ - u32 fbr1_enable:1; /* bit 13 */ - u32 fbr1_size:2; /* bits 11-12 */ - u32 fbr0_enable:1; /* bit 10 */ - u32 fbr0_size:2; /* bits 8-9 */ - u32 dma_big_endian:1; /* bit 7 */ - u32 pkt_big_endian:1; /* bit 6 */ - u32 psr_big_endian:1; /* bit 5 */ - u32 fbr_big_endian:1; /* bit 4 */ - u32 tc:3; /* bits 1-3 */ - u32 halt:1; /* bit 0 */ -#else - u32 halt:1; /* bit 0 */ - u32 tc:3; /* bits 1-3 */ - u32 fbr_big_endian:1; /* bit 4 */ - u32 psr_big_endian:1; /* bit 5 */ - u32 pkt_big_endian:1; /* bit 6 */ - u32 dma_big_endian:1; /* bit 7 */ - u32 fbr0_size:2; /* bits 8-9 */ - u32 fbr0_enable:1; /* bit 10 */ - u32 fbr1_size:2; /* bits 11-12 */ - u32 fbr1_enable:1; /* bit 13 */ - u32 unused1:1; /* bit 14 */ - u32 pkt_drop_disable:1; /* bit 15 */ - u32 pkt_done_flush:1; /* bit 16 */ - u32 halt_status:1; /* bit 17 */ - u32 unused2:14; /* bits 18-31 */ -#endif - } bits; -} RXDMA_CSR_t, *PRXDMA_CSR_t; + /* * structure for dma writeback lo reg in rxdma address map @@ -451,18 +429,6 @@ typedef union _RXDMA_CSR_t { * 31-10: unused * 9-0: fbr ndesc */ -typedef union _RXDMA_FBR_NUM_DES_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused:22; /* bits 10-31 */ - u32 fbr_ndesc:10; /* bits 0-9 */ -#else - u32 fbr_ndesc:10; /* bits 0-9 */ - u32 unused:22; /* bits 10-31 */ -#endif - } bits; -} RXDMA_FBR_NUM_DES_t, *PRXDMA_FBR_NUM_DES_t; /* * structure for free buffer ring 0 available offset reg in rxdma address map @@ -532,8 +498,8 @@ typedef union _RXDMA_FBR_NUM_DES_t { * Rx DMA Module of JAGCore Address Mapping * Located at address 0x2000 */ -typedef struct _RXDMA_t { /* Location: */ - RXDMA_CSR_t csr; /* 0x2000 */ +struct rxdma_regs { /* Location: */ + u32 csr; /* 0x2000 */ u32 dma_wb_base_lo; /* 0x2004 */ u32 dma_wb_base_hi; /* 0x2008 */ u32 num_pkt_done; /* 0x200C */ @@ -562,7 +528,7 @@ typedef struct _RXDMA_t { /* Location: */ u32 fbr1_full_offset; /* 0x2068 */ u32 fbr1_rd_index; /* 0x206C */ u32 fbr1_min_des; /* 0x2070 */ -} RXDMA_t, *PRXDMA_t; +}; /* END OF RXDMA REGISTER ADDRESS MAP */ @@ -572,33 +538,18 @@ typedef struct _RXDMA_t { /* Location: */ /* * structure for control reg in txmac address map * located at address 0x3000 + * + * bits + * 31-8: unused + * 7: cklseg_disable + * 6: ckbcnt_disable + * 5: cksegnum + * 4: async_disable + * 3: fc_disable + * 2: mcif_disable + * 1: mif_disable + * 0: txmac_en */ -typedef union _TXMAC_CTL_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused:24; /* bits 8-31 */ - u32 cklseg_diable:1; /* bit 7 */ - u32 ckbcnt_disable:1; /* bit 6 */ - u32 cksegnum:1; /* bit 5 */ - u32 async_disable:1; /* bit 4 */ - u32 fc_disable:1; /* bit 3 */ - u32 mcif_disable:1; /* bit 2 */ - u32 mif_disable:1; /* bit 1 */ - u32 txmac_en:1; /* bit 0 */ -#else - u32 txmac_en:1; /* bit 0 */ - u32 mif_disable:1; /* bit 1 mac interface */ - u32 mcif_disable:1; /* bit 2 mem. contr. interface */ - u32 fc_disable:1; /* bit 3 */ - u32 async_disable:1; /* bit 4 */ - u32 cksegnum:1; /* bit 5 */ - u32 ckbcnt_disable:1; /* bit 6 */ - u32 cklseg_diable:1; /* bit 7 */ - u32 unused:24; /* bits 8-31 */ -#endif - } bits; -} TXMAC_CTL_t, *PTXMAC_CTL_t; /* * structure for shadow pointer reg in txmac address map @@ -612,23 +563,12 @@ typedef union _TXMAC_CTL_t { /* * structure for error count reg in txmac address map * located at address 0x3008 + * + * 31-12: unused + * 11-8: reserved + * 7-4: txq_underrun + * 3-0: fifo_underrun */ -typedef union _TXMAC_ERR_CNT_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused:20; /* bits 12-31 */ - u32 reserved:4; /* bits 8-11 */ - u32 txq_underrun:4; /* bits 4-7 */ - u32 fifo_underrun:4; /* bits 0-3 */ -#else - u32 fifo_underrun:4; /* bits 0-3 */ - u32 txq_underrun:4; /* bits 4-7 */ - u32 reserved:4; /* bits 8-11 */ - u32 unused:20; /* bits 12-31 */ -#endif - } bits; -} TXMAC_ERR_CNT_t, *PTXMAC_ERR_CNT_t; /* * structure for max fill reg in txmac address map @@ -657,64 +597,32 @@ typedef union _TXMAC_ERR_CNT_t { /* * structure for error reg in txmac address map * located at address 0x3018 + * + * 31-9: unused + * 8: fifo_underrun + * 7-6: unused + * 5: ctrl2_err + * 4: txq_underrun + * 3: bcnt_err + * 2: lseg_err + * 1: segnum_err + * 0: seg0_err */ -typedef union _TXMAC_ERR_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused2:23; /* bits 9-31 */ - u32 fifo_underrun:1; /* bit 8 */ - u32 unused1:2; /* bits 6-7 */ - u32 ctrl2_err:1; /* bit 5 */ - u32 txq_underrun:1; /* bit 4 */ - u32 bcnt_err:1; /* bit 3 */ - u32 lseg_err:1; /* bit 2 */ - u32 segnum_err:1; /* bit 1 */ - u32 seg0_err:1; /* bit 0 */ -#else - u32 seg0_err:1; /* bit 0 */ - u32 segnum_err:1; /* bit 1 */ - u32 lseg_err:1; /* bit 2 */ - u32 bcnt_err:1; /* bit 3 */ - u32 txq_underrun:1; /* bit 4 */ - u32 ctrl2_err:1; /* bit 5 */ - u32 unused1:2; /* bits 6-7 */ - u32 fifo_underrun:1; /* bit 8 */ - u32 unused2:23; /* bits 9-31 */ -#endif - } bits; -} TXMAC_ERR_t, *PTXMAC_ERR_t; /* * structure for error interrupt reg in txmac address map * located at address 0x301C + * + * 31-9: unused + * 8: fifo_underrun + * 7-6: unused + * 5: ctrl2_err + * 4: txq_underrun + * 3: bcnt_err + * 2: lseg_err + * 1: segnum_err + * 0: seg0_err */ -typedef union _TXMAC_ERR_INT_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused2:23; /* bits 9-31 */ - u32 fifo_underrun:1; /* bit 8 */ - u32 unused1:2; /* bits 6-7 */ - u32 ctrl2_err:1; /* bit 5 */ - u32 txq_underrun:1; /* bit 4 */ - u32 bcnt_err:1; /* bit 3 */ - u32 lseg_err:1; /* bit 2 */ - u32 segnum_err:1; /* bit 1 */ - u32 seg0_err:1; /* bit 0 */ -#else - u32 seg0_err:1; /* bit 0 */ - u32 segnum_err:1; /* bit 1 */ - u32 lseg_err:1; /* bit 2 */ - u32 bcnt_err:1; /* bit 3 */ - u32 txq_underrun:1; /* bit 4 */ - u32 ctrl2_err:1; /* bit 5 */ - u32 unused1:2; /* bits 6-7 */ - u32 fifo_underrun:1; /* bit 8 */ - u32 unused2:23; /* bits 9-31 */ -#endif - } bits; -} TXMAC_ERR_INT_t, *PTXMAC_ERR_INT_t; /* * structure for error interrupt reg in txmac address map @@ -728,17 +636,17 @@ typedef union _TXMAC_ERR_INT_t { /* * Tx MAC Module of JAGCore Address Mapping */ -typedef struct _TXMAC_t { /* Location: */ - TXMAC_CTL_t ctl; /* 0x3000 */ +struct txmac_regs { /* Location: */ + u32 ctl; /* 0x3000 */ u32 shadow_ptr; /* 0x3004 */ - TXMAC_ERR_CNT_t err_cnt; /* 0x3008 */ + u32 err_cnt; /* 0x3008 */ u32 max_fill; /* 0x300C */ u32 cf_param; /* 0x3010 */ u32 tx_test; /* 0x3014 */ - TXMAC_ERR_t err; /* 0x3018 */ - TXMAC_ERR_INT_t err_int; /* 0x301C */ + u32 err; /* 0x3018 */ + u32 err_int; /* 0x301C */ u32 bp_ctrl; /* 0x3020 */ -} TXMAC_t, *PTXMAC_t; +}; /* END OF TXMAC REGISTER ADDRESS MAP */ @@ -747,106 +655,47 @@ typedef struct _TXMAC_t { /* Location: */ /* * structure for rxmac control reg in rxmac address map * located at address 0x4000 + * + * 31-7: reserved + * 6: rxmac_int_disable + * 5: async_disable + * 4: mif_disable + * 3: wol_disable + * 2: pkt_filter_disable + * 1: mcif_disable + * 0: rxmac_en */ -typedef union _RXMAC_CTRL_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserved:25; /* bits 7-31 */ - u32 rxmac_int_disable:1; /* bit 6 */ - u32 async_disable:1; /* bit 5 */ - u32 mif_disable:1; /* bit 4 */ - u32 wol_disable:1; /* bit 3 */ - u32 pkt_filter_disable:1; /* bit 2 */ - u32 mcif_disable:1; /* bit 1 */ - u32 rxmac_en:1; /* bit 0 */ -#else - u32 rxmac_en:1; /* bit 0 */ - u32 mcif_disable:1; /* bit 1 */ - u32 pkt_filter_disable:1; /* bit 2 */ - u32 wol_disable:1; /* bit 3 */ - u32 mif_disable:1; /* bit 4 */ - u32 async_disable:1; /* bit 5 */ - u32 rxmac_int_disable:1; /* bit 6 */ - u32 reserved:25; /* bits 7-31 */ -#endif - } bits; -} RXMAC_CTRL_t, *PRXMAC_CTRL_t; /* * structure for Wake On Lan Control and CRC 0 reg in rxmac address map * located at address 0x4004 + * 31-16: crc + * 15-12: reserved + * 11: ignore_pp + * 10: ignore_mp + * 9: clr_intr + * 8: ignore_link_chg + * 7: ignore_uni + * 6: ignore_multi + * 5: ignore_broad + * 4-0: valid_crc 4-0 */ -typedef union _RXMAC_WOL_CTL_CRC0_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 crc0:16; /* bits 16-31 */ - u32 reserve:4; /* bits 12-15 */ - u32 ignore_pp:1; /* bit 11 */ - u32 ignore_mp:1; /* bit 10 */ - u32 clr_intr:1; /* bit 9 */ - u32 ignore_link_chg:1; /* bit 8 */ - u32 ignore_uni:1; /* bit 7 */ - u32 ignore_multi:1; /* bit 6 */ - u32 ignore_broad:1; /* bit 5 */ - u32 valid_crc4:1; /* bit 4 */ - u32 valid_crc3:1; /* bit 3 */ - u32 valid_crc2:1; /* bit 2 */ - u32 valid_crc1:1; /* bit 1 */ - u32 valid_crc0:1; /* bit 0 */ -#else - u32 valid_crc0:1; /* bit 0 */ - u32 valid_crc1:1; /* bit 1 */ - u32 valid_crc2:1; /* bit 2 */ - u32 valid_crc3:1; /* bit 3 */ - u32 valid_crc4:1; /* bit 4 */ - u32 ignore_broad:1; /* bit 5 */ - u32 ignore_multi:1; /* bit 6 */ - u32 ignore_uni:1; /* bit 7 */ - u32 ignore_link_chg:1; /* bit 8 */ - u32 clr_intr:1; /* bit 9 */ - u32 ignore_mp:1; /* bit 10 */ - u32 ignore_pp:1; /* bit 11 */ - u32 reserve:4; /* bits 12-15 */ - u32 crc0:16; /* bits 16-31 */ -#endif - } bits; -} RXMAC_WOL_CTL_CRC0_t, *PRXMAC_WOL_CTL_CRC0_t; /* * structure for CRC 1 and CRC 2 reg in rxmac address map * located at address 0x4008 + * + * 31-16: crc2 + * 15-0: crc1 */ -typedef union _RXMAC_WOL_CRC12_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 crc2:16; /* bits 16-31 */ - u32 crc1:16; /* bits 0-15 */ -#else - u32 crc1:16; /* bits 0-15 */ - u32 crc2:16; /* bits 16-31 */ -#endif - } bits; -} RXMAC_WOL_CRC12_t, *PRXMAC_WOL_CRC12_t; /* * structure for CRC 3 and CRC 4 reg in rxmac address map * located at address 0x400C + * + * 31-16: crc4 + * 15-0: crc3 */ -typedef union _RXMAC_WOL_CRC34_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 crc4:16; /* bits 16-31 */ - u32 crc3:16; /* bits 0-15 */ -#else - u32 crc3:16; /* bits 0-15 */ - u32 crc4:16; /* bits 16-31 */ -#endif - } bits; -} RXMAC_WOL_CRC34_t, *PRXMAC_WOL_CRC34_t; /* * structure for Wake On Lan Source Address Lo reg in rxmac address map @@ -966,164 +815,84 @@ typedef union _RXMAC_UNI_PF_ADDR3_t { /* * structure for Packet Filter Control reg in rxmac address map * located at address 0x4084 + * + * 31-23: unused + * 22-16: min_pkt_size + * 15-4: unused + * 3: filter_frag_en + * 2: filter_uni_en + * 1: filter_multi_en + * 0: filter_broad_en */ -typedef union _RXMAC_PF_CTRL_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused2:9; /* bits 23-31 */ - u32 min_pkt_size:7; /* bits 16-22 */ - u32 unused1:12; /* bits 4-15 */ - u32 filter_frag_en:1; /* bit 3 */ - u32 filter_uni_en:1; /* bit 2 */ - u32 filter_multi_en:1; /* bit 1 */ - u32 filter_broad_en:1; /* bit 0 */ -#else - u32 filter_broad_en:1; /* bit 0 */ - u32 filter_multi_en:1; /* bit 1 */ - u32 filter_uni_en:1; /* bit 2 */ - u32 filter_frag_en:1; /* bit 3 */ - u32 unused1:12; /* bits 4-15 */ - u32 min_pkt_size:7; /* bits 16-22 */ - u32 unused2:9; /* bits 23-31 */ -#endif - } bits; -} RXMAC_PF_CTRL_t, *PRXMAC_PF_CTRL_t; /* * structure for Memory Controller Interface Control Max Segment reg in rxmac * address map. Located at address 0x4088 + * + * 31-10: reserved + * 9-2: max_size + * 1: fc_en + * 0: seg_en */ -typedef union _RXMAC_MCIF_CTRL_MAX_SEG_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserved:22; /* bits 10-31 */ - u32 max_size:8; /* bits 2-9 */ - u32 fc_en:1; /* bit 1 */ - u32 seg_en:1; /* bit 0 */ -#else - u32 seg_en:1; /* bit 0 */ - u32 fc_en:1; /* bit 1 */ - u32 max_size:8; /* bits 2-9 */ - u32 reserved:22; /* bits 10-31 */ -#endif - } bits; -} RXMAC_MCIF_CTRL_MAX_SEG_t, *PRXMAC_MCIF_CTRL_MAX_SEG_t; /* * structure for Memory Controller Interface Water Mark reg in rxmac address * map. Located at address 0x408C + * + * 31-26: unused + * 25-16: mark_hi + * 15-10: unused + * 9-0: mark_lo */ -typedef union _RXMAC_MCIF_WATER_MARK_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserved2:6; /* bits 26-31 */ - u32 mark_hi:10; /* bits 16-25 */ - u32 reserved1:6; /* bits 10-15 */ - u32 mark_lo:10; /* bits 0-9 */ -#else - u32 mark_lo:10; /* bits 0-9 */ - u32 reserved1:6; /* bits 10-15 */ - u32 mark_hi:10; /* bits 16-25 */ - u32 reserved2:6; /* bits 26-31 */ -#endif - } bits; -} RXMAC_MCIF_WATER_MARK_t, *PRXMAC_MCIF_WATER_MARK_t; /* * structure for Rx Queue Dialog reg in rxmac address map. * located at address 0x4090 + * + * 31-26: reserved + * 25-16: rd_ptr + * 15-10: reserved + * 9-0: wr_ptr */ -typedef union _RXMAC_RXQ_DIAG_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserved2:6; /* bits 26-31 */ - u32 rd_ptr:10; /* bits 16-25 */ - u32 reserved1:6; /* bits 10-15 */ - u32 wr_ptr:10; /* bits 0-9 */ -#else - u32 wr_ptr:10; /* bits 0-9 */ - u32 reserved1:6; /* bits 10-15 */ - u32 rd_ptr:10; /* bits 16-25 */ - u32 reserved2:6; /* bits 26-31 */ -#endif - } bits; -} RXMAC_RXQ_DIAG_t, *PRXMAC_RXQ_DIAG_t; /* * structure for space availiable reg in rxmac address map. * located at address 0x4094 + * + * 31-17: reserved + * 16: space_avail_en + * 15-10: reserved + * 9-0: space_avail */ -typedef union _RXMAC_SPACE_AVAIL_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserved2:15; /* bits 17-31 */ - u32 space_avail_en:1; /* bit 16 */ - u32 reserved1:6; /* bits 10-15 */ - u32 space_avail:10; /* bits 0-9 */ -#else - u32 space_avail:10; /* bits 0-9 */ - u32 reserved1:6; /* bits 10-15 */ - u32 space_avail_en:1; /* bit 16 */ - u32 reserved2:15; /* bits 17-31 */ -#endif - } bits; -} RXMAC_SPACE_AVAIL_t, *PRXMAC_SPACE_AVAIL_t; /* * structure for management interface reg in rxmac address map. * located at address 0x4098 + * + * 31-18: reserved + * 17: drop_pkt_en + * 16-0: drop_pkt_mask */ -typedef union _RXMAC_MIF_CTL_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserve:14; /* bits 18-31 */ - u32 drop_pkt_en:1; /* bit 17 */ - u32 drop_pkt_mask:17; /* bits 0-16 */ -#else - u32 drop_pkt_mask:17; /* bits 0-16 */ - u32 drop_pkt_en:1; /* bit 17 */ - u32 reserve:14; /* bits 18-31 */ -#endif - } bits; -} RXMAC_MIF_CTL_t, *PRXMAC_MIF_CTL_t; /* * structure for Error reg in rxmac address map. * located at address 0x409C + * + * 31-4: unused + * 3: mif + * 2: async + * 1: pkt_filter + * 0: mcif */ -typedef union _RXMAC_ERROR_REG_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserve:28; /* bits 4-31 */ - u32 mif:1; /* bit 3 */ - u32 async:1; /* bit 2 */ - u32 pkt_filter:1; /* bit 1 */ - u32 mcif:1; /* bit 0 */ -#else - u32 mcif:1; /* bit 0 */ - u32 pkt_filter:1; /* bit 1 */ - u32 async:1; /* bit 2 */ - u32 mif:1; /* bit 3 */ - u32 reserve:28; /* bits 4-31 */ -#endif - } bits; -} RXMAC_ERROR_REG_t, *PRXMAC_ERROR_REG_t; /* * Rx MAC Module of JAGCore Address Mapping */ typedef struct _RXMAC_t { /* Location: */ - RXMAC_CTRL_t ctrl; /* 0x4000 */ - RXMAC_WOL_CTL_CRC0_t crc0; /* 0x4004 */ - RXMAC_WOL_CRC12_t crc12; /* 0x4008 */ - RXMAC_WOL_CRC34_t crc34; /* 0x400C */ + u32 ctrl; /* 0x4000 */ + u32 crc0; /* 0x4004 */ + u32 crc12; /* 0x4008 */ + u32 crc34; /* 0x400C */ RXMAC_WOL_SA_LO_t sa_lo; /* 0x4010 */ RXMAC_WOL_SA_HI_t sa_hi; /* 0x4014 */ u32 mask0_word0; /* 0x4018 */ @@ -1153,17 +922,17 @@ typedef struct _RXMAC_t { /* Location: */ u32 multi_hash2; /* 0x4078 */ u32 multi_hash3; /* 0x407C */ u32 multi_hash4; /* 0x4080 */ - RXMAC_PF_CTRL_t pf_ctrl; /* 0x4084 */ - RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg; /* 0x4088 */ - RXMAC_MCIF_WATER_MARK_t mcif_water_mark; /* 0x408C */ - RXMAC_RXQ_DIAG_t rxq_diag; /* 0x4090 */ - RXMAC_SPACE_AVAIL_t space_avail; /* 0x4094 */ - - RXMAC_MIF_CTL_t mif_ctrl; /* 0x4098 */ - RXMAC_ERROR_REG_t err_reg; /* 0x409C */ + u32 pf_ctrl; /* 0x4084 */ + u32 mcif_ctrl_max_seg; /* 0x4088 */ + u32 mcif_water_mark; /* 0x408C */ + u32 rxq_diag; /* 0x4090 */ + u32 space_avail; /* 0x4094 */ + + u32 mif_ctrl; /* 0x4098 */ + u32 err_reg; /* 0x409C */ } RXMAC_t, *PRXMAC_t; -/* END OF TXMAC REGISTER ADDRESS MAP */ +/* END OF RXMAC REGISTER ADDRESS MAP */ /* START OF MAC REGISTER ADDRESS MAP */ @@ -1337,37 +1106,19 @@ typedef struct _RXMAC_t { /* Location: */ /* * structure for Interface Status reg in mac address map. * located at address 0x503C + * + * 31-10: reserved + * 9: excess_defer + * 8: clash + * 7: phy_jabber + * 6: phy_link_ok + * 5: phy_full_duplex + * 4: phy_speed + * 3: pe100x_link_fail + * 2: pe10t_loss_carrier + * 1: pe10t_sqe_error + * 0: pe10t_jabber */ -typedef union _MAC_IF_STAT_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserved:22; /* bits 10-31 */ - u32 excess_defer:1; /* bit 9 */ - u32 clash:1; /* bit 8 */ - u32 phy_jabber:1; /* bit 7 */ - u32 phy_link_ok:1; /* bit 6 */ - u32 phy_full_duplex:1; /* bit 5 */ - u32 phy_speed:1; /* bit 4 */ - u32 pe100x_link_fail:1; /* bit 3 */ - u32 pe10t_loss_carrie:1; /* bit 2 */ - u32 pe10t_sqe_error:1; /* bit 1 */ - u32 pe10t_jabber:1; /* bit 0 */ -#else - u32 pe10t_jabber:1; /* bit 0 */ - u32 pe10t_sqe_error:1; /* bit 1 */ - u32 pe10t_loss_carrie:1; /* bit 2 */ - u32 pe100x_link_fail:1; /* bit 3 */ - u32 phy_speed:1; /* bit 4 */ - u32 phy_full_duplex:1; /* bit 5 */ - u32 phy_link_ok:1; /* bit 6 */ - u32 phy_jabber:1; /* bit 7 */ - u32 clash:1; /* bit 8 */ - u32 excess_defer:1; /* bit 9 */ - u32 reserved:22; /* bits 10-31 */ -#endif - } bits; -} MAC_IF_STAT_t, *PMAC_IF_STAT_t; /* * structure for Mac Station Address, Part 1 reg in mac address map. @@ -1428,7 +1179,7 @@ typedef struct _MAC_t { /* Location: */ u32 mii_mgmt_stat; /* 0x5030 */ u32 mii_mgmt_indicator; /* 0x5034 */ u32 if_ctrl; /* 0x5038 */ - MAC_IF_STAT_t if_stat; /* 0x503C */ + u32 if_stat; /* 0x503C */ MAC_STATION_ADDR1_t station_addr_1; /* 0x5040 */ MAC_STATION_ADDR2_t station_addr_2; /* 0x5044 */ } MAC_t, *PMAC_t; @@ -1498,8 +1249,9 @@ typedef struct _MAC_t { /* Location: */ /* * MAC STATS Module of JAGCore Address Mapping */ -typedef struct _MAC_STAT_t { /* Location: */ - u32 pad[32]; /* 0x6000 - 607C */ +struct macstat_regs +{ /* Location: */ + u32 pad[32]; /* 0x6000 - 607C */ /* Tx/Rx 0-64 Byte Frame Counter */ u32 TR64; /* 0x6080 */ @@ -1644,7 +1396,7 @@ typedef struct _MAC_STAT_t { /* Location: */ /* Carry Register Two Mask Register */ u32 Carry2M; /* 0x613C */ -} MAC_STAT_t, *PMAC_STAT_t; +}; /* END OF MAC STAT REGISTER ADDRESS MAP */ @@ -1682,70 +1434,49 @@ typedef struct _MAC_STAT_t { /* Location: */ /* * Memory Control Module of JAGCore Address Mapping */ -typedef struct _MMC_t { /* Location: */ +struct mmc_regs { /* Location: */ u32 mmc_ctrl; /* 0x7000 */ u32 sram_access; /* 0x7004 */ u32 sram_word1; /* 0x7008 */ u32 sram_word2; /* 0x700C */ u32 sram_word3; /* 0x7010 */ u32 sram_word4; /* 0x7014 */ -} MMC_t, *PMMC_t; +}; /* END OF MMC REGISTER ADDRESS MAP */ -/* START OF EXP ROM REGISTER ADDRESS MAP */ - -/* - * Expansion ROM Module of JAGCore Address Mapping - */ - -/* Take this out until it is not empty */ -#if 0 -typedef struct _EXP_ROM_t { - -} EXP_ROM_t, *PEXP_ROM_t; -#endif - -/* END OF EXP ROM REGISTER ADDRESS MAP */ - - /* * JAGCore Address Mapping */ typedef struct _ADDRESS_MAP_t { - GLOBAL_t global; + struct global_regs global; /* unused section of global address map */ - u8 unused_global[4096 - sizeof(GLOBAL_t)]; - TXDMA_t txdma; + u8 unused_global[4096 - sizeof(struct global_regs)]; + struct txdma_regs txdma; /* unused section of txdma address map */ - u8 unused_txdma[4096 - sizeof(TXDMA_t)]; - RXDMA_t rxdma; + u8 unused_txdma[4096 - sizeof(struct txdma_regs)]; + struct rxdma_regs rxdma; /* unused section of rxdma address map */ - u8 unused_rxdma[4096 - sizeof(RXDMA_t)]; - TXMAC_t txmac; + u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)]; + struct txmac_regs txmac; /* unused section of txmac address map */ - u8 unused_txmac[4096 - sizeof(TXMAC_t)]; + u8 unused_txmac[4096 - sizeof(struct txmac_regs)]; RXMAC_t rxmac; /* unused section of rxmac address map */ u8 unused_rxmac[4096 - sizeof(RXMAC_t)]; MAC_t mac; /* unused section of mac address map */ u8 unused_mac[4096 - sizeof(MAC_t)]; - MAC_STAT_t macStat; + struct macstat_regs macstat; /* unused section of mac stat address map */ - u8 unused_mac_stat[4096 - sizeof(MAC_STAT_t)]; - MMC_t mmc; + u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)]; + struct mmc_regs mmc; /* unused section of mmc address map */ - u8 unused_mmc[4096 - sizeof(MMC_t)]; + u8 unused_mmc[4096 - sizeof(struct mmc_regs)]; /* unused section of address map */ u8 unused_[1015808]; -/* Take this out until it is not empty */ -#if 0 - EXP_ROM_t exp_rom; -#endif - u8 unused_exp_rom[4096]; /* MGS-size TBD */ u8 unused__[524288]; /* unused section of address map */ } ADDRESS_MAP_t, *PADDRESS_MAP_t; |