diff options
Diffstat (limited to 'drivers/staging/media/zoran/zr36060.h')
| -rw-r--r-- | drivers/staging/media/zoran/zr36060.h | 66 |
1 files changed, 33 insertions, 33 deletions
diff --git a/drivers/staging/media/zoran/zr36060.h b/drivers/staging/media/zoran/zr36060.h index 9289a9921c03..d2cdc26bf625 100644 --- a/drivers/staging/media/zoran/zr36060.h +++ b/drivers/staging/media/zoran/zr36060.h @@ -124,35 +124,35 @@ struct zr36060 { /* ZR36060 LOAD register bits */ -#define ZR060_LOAD_Load BIT(7) -#define ZR060_LOAD_SyncRst BIT(0) +#define ZR060_LOAD_LOAD BIT(7) +#define ZR060_LOAD_SYNC_RST BIT(0) /* ZR36060 Code FIFO Status register bits */ -#define ZR060_CFSR_Busy BIT(7) -#define ZR060_CFSR_CBusy BIT(2) +#define ZR060_CFSR_BUSY BIT(7) +#define ZR060_CFSR_C_BUSY BIT(2) #define ZR060_CFSR_CFIFO (3 << 0) /* ZR36060 Code Interface register */ -#define ZR060_CIR_Code16 BIT(7) -#define ZR060_CIR_Endian BIT(6) +#define ZR060_CIR_CODE16 BIT(7) +#define ZR060_CIR_ENDIAN BIT(6) #define ZR060_CIR_CFIS BIT(2) -#define ZR060_CIR_CodeMstr BIT(0) +#define ZR060_CIR_CODE_MSTR BIT(0) /* ZR36060 Codec Mode register */ -#define ZR060_CMR_Comp BIT(7) +#define ZR060_CMR_COMP BIT(7) #define ZR060_CMR_ATP BIT(6) -#define ZR060_CMR_Pass2 BIT(5) +#define ZR060_CMR_PASS2 BIT(5) #define ZR060_CMR_TLM BIT(4) #define ZR060_CMR_BRB BIT(2) #define ZR060_CMR_FSF BIT(1) /* ZR36060 Markers Enable register */ -#define ZR060_MER_App BIT(7) -#define ZR060_MER_Com BIT(6) +#define ZR060_MER_APP BIT(7) +#define ZR060_MER_COM BIT(6) #define ZR060_MER_DRI BIT(5) #define ZR060_MER_DQT BIT(4) #define ZR060_MER_DHT BIT(3) @@ -161,41 +161,41 @@ struct zr36060 { #define ZR060_IMR_EOAV BIT(3) #define ZR060_IMR_EOI BIT(2) -#define ZR060_IMR_End BIT(1) -#define ZR060_IMR_DataErr BIT(0) +#define ZR060_IMR_END BIT(1) +#define ZR060_IMR_DATA_ERR BIT(0) /* ZR36060 Interrupt Status register */ -#define ZR060_ISR_ProCnt (3 << 6) +#define ZR060_ISR_PRO_CNT (3 << 6) #define ZR060_ISR_EOAV BIT(3) #define ZR060_ISR_EOI BIT(2) -#define ZR060_ISR_End BIT(1) -#define ZR060_ISR_DataErr BIT(0) +#define ZR060_ISR_END BIT(1) +#define ZR060_ISR_DATA_ERR BIT(0) /* ZR36060 Video Control register */ -#define ZR060_VCR_Video8 BIT(7) -#define ZR060_VCR_Range BIT(6) -#define ZR060_VCR_FIDet BIT(3) -#define ZR060_VCR_FIVedge BIT(2) -#define ZR060_VCR_FIExt BIT(1) -#define ZR060_VCR_SyncMstr BIT(0) +#define ZR060_VCR_VIDEO8 BIT(7) +#define ZR060_VCR_RANGE BIT(6) +#define ZR060_VCR_FI_DET BIT(3) +#define ZR060_VCR_FI_VEDGE BIT(2) +#define ZR060_VCR_FI_EXT BIT(1) +#define ZR060_VCR_SYNC_MSTR BIT(0) /* ZR36060 Video Polarity register */ -#define ZR060_VPR_VCLKPol BIT(7) -#define ZR060_VPR_PValPol BIT(6) -#define ZR060_VPR_PoePol BIT(5) -#define ZR060_VPR_SImgPol BIT(4) -#define ZR060_VPR_BLPol BIT(3) -#define ZR060_VPR_FIPol BIT(2) -#define ZR060_VPR_HSPol BIT(1) -#define ZR060_VPR_VSPol BIT(0) +#define ZR060_VPR_VCLK_POL BIT(7) +#define ZR060_VPR_P_VAL_POL BIT(6) +#define ZR060_VPR_POE_POL BIT(5) +#define ZR060_VPR_S_IMG_POL BIT(4) +#define ZR060_VPR_BL_POL BIT(3) +#define ZR060_VPR_FI_POL BIT(2) +#define ZR060_VPR_HS_POL BIT(1) +#define ZR060_VPR_VS_POL BIT(0) /* ZR36060 Scaling register */ -#define ZR060_SR_VScale BIT(2) -#define ZR060_SR_HScale2 BIT(0) -#define ZR060_SR_HScale4 (2 << 0) +#define ZR060_SR_V_SCALE BIT(2) +#define ZR060_SR_H_SCALE2 BIT(0) +#define ZR060_SR_H_SCALE4 (2 << 0) #endif /*fndef ZR36060_H */ |