diff options
Diffstat (limited to 'drivers/staging/mt7621-mmc/sd.c')
| -rw-r--r-- | drivers/staging/mt7621-mmc/sd.c | 584 |
1 files changed, 260 insertions, 324 deletions
diff --git a/drivers/staging/mt7621-mmc/sd.c b/drivers/staging/mt7621-mmc/sd.c index 648a2dd1436e..04d23cc7cd4a 100644 --- a/drivers/staging/mt7621-mmc/sd.c +++ b/drivers/staging/mt7621-mmc/sd.c @@ -50,15 +50,11 @@ #include "dbg.h" #include "mt6575_sd.h" -//#define IRQ_SDC 14 //MT7620 /*FIXME*/ #ifdef CONFIG_SOC_MT7621 #define RALINK_SYSCTL_BASE 0xbe000000 -#define RALINK_MSDC_BASE 0xbe130000 #else #define RALINK_SYSCTL_BASE 0xb0000000 -#define RALINK_MSDC_BASE 0xb0130000 #endif -#define IRQ_SDC 22 /*FIXME*/ #define DRV_NAME "mtk-sd" @@ -91,10 +87,8 @@ #define MAX_GPD_NUM (1 + 1) /* one null gpd */ #define MAX_BD_NUM (1024) -#define MAX_BD_PER_GPD (MAX_BD_NUM) #define MAX_HW_SGMTS (MAX_BD_NUM) -#define MAX_PHY_SGMTS (MAX_BD_NUM) #define MAX_SGMT_SZ (MAX_DMA_CNT) #define MAX_REQ_SZ (MAX_SGMT_SZ * 8) @@ -147,59 +141,37 @@ static int msdc_rsp[] = { 7, /* RESP_R1b */ }; -#define msdc_txfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16) -#define msdc_rxfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) >> 0) -#define msdc_fifo_write32(v) sdr_write32(MSDC_TXDATA, (v)) -#define msdc_fifo_write8(v) sdr_write8(MSDC_TXDATA, (v)) -#define msdc_fifo_read32() sdr_read32(MSDC_RXDATA) -#define msdc_fifo_read8() sdr_read8(MSDC_RXDATA) - -#define msdc_dma_on() sdr_clr_bits(MSDC_CFG, MSDC_CFG_PIO) - -#define msdc_retry(expr, retry, cnt) \ - do { \ - int backup = cnt; \ - while (retry) { \ - if (!(expr)) \ - break; \ - if (cnt-- == 0) { \ - retry--; mdelay(1); cnt = backup; \ - } \ - } \ - WARN_ON(retry == 0); \ - } while (0) +#define msdc_dma_on() sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO) static void msdc_reset_hw(struct msdc_host *host) { - void __iomem *base = host->base; - - sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); - while (sdr_read32(MSDC_CFG) & MSDC_CFG_RST) + sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); + while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) cpu_relax(); } #define msdc_clr_int() \ do { \ - volatile u32 val = sdr_read32(MSDC_INT); \ - sdr_write32(MSDC_INT, val); \ + volatile u32 val = readl(host->base + MSDC_INT); \ + writel(val, host->base + MSDC_INT); \ } while (0) -#define msdc_clr_fifo() \ - do { \ - int retry = 3, cnt = 1000; \ - sdr_set_bits(MSDC_FIFOCS, MSDC_FIFOCS_CLR); \ - msdc_retry(sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_CLR, retry, cnt); \ - } while (0) +static void msdc_clr_fifo(struct msdc_host *host) +{ + sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); + while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) + cpu_relax(); +} #define msdc_irq_save(val) \ do { \ - val = sdr_read32(MSDC_INTEN); \ - sdr_clr_bits(MSDC_INTEN, val); \ + val = readl(host->base + MSDC_INTEN); \ + sdr_clr_bits(host->base + MSDC_INTEN, val); \ } while (0) #define msdc_irq_restore(val) \ do { \ - sdr_set_bits(MSDC_INTEN, val); \ + sdr_set_bits(host->base + MSDC_INTEN, val); \ } while (0) /* clock source for host: global */ @@ -237,19 +209,15 @@ static u32 hclks[] = {50000000}; /* +/- by chhung */ (void)hwPowerDown(MT65XX_POWER_LDO_VMCH, "SD"); \ } while (0) -#define sdc_is_busy() (sdr_read32(SDC_STS) & SDC_STS_SDCBUSY) -#define sdc_is_cmd_busy() (sdr_read32(SDC_STS) & SDC_STS_CMDBUSY) +#define sdc_is_busy() (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) +#define sdc_is_cmd_busy() (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) #define sdc_send_cmd(cmd, arg) \ do { \ - sdr_write32(SDC_ARG, (arg)); \ - sdr_write32(SDC_CMD, (cmd)); \ + writel((arg), host->base + SDC_ARG); \ + writel((cmd), host->base + SDC_CMD); \ } while (0) -// can modify to read h/w register. -//#define is_card_present(h) ((sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1); -#define is_card_present(h) (((struct msdc_host *)(h))->card_inserted) - /* +++ by chhung */ #ifndef __ASSEMBLY__ #define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) @@ -404,7 +372,6 @@ static void msdc_dump_io_resp(struct msdc_host *host, u32 resp) static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) { - void __iomem *base = host->base; u32 timeout, clk_ns; host->timeout_ns = ns; @@ -416,7 +383,7 @@ static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) timeout = timeout > 1 ? timeout - 1 : 0; timeout = timeout > 255 ? 255 : timeout; - sdr_set_field(SDC_CFG, SDC_CFG_DTOC, timeout); + sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); N_MSG(OPS, "Set read data timeout: %dns %dclks -> %d x 65536 cycles", ns, clks, timeout + 1); @@ -426,14 +393,13 @@ static void msdc_tasklet_card(struct work_struct *work) { struct msdc_host *host = (struct msdc_host *)container_of(work, struct msdc_host, card_delaywork.work); - void __iomem *base = host->base; u32 inserted; u32 status = 0; //u32 change = 0; spin_lock(&host->lock); - status = sdr_read32(MSDC_PS); + status = readl(host->base + MSDC_PS); if (cd_active_low) inserted = (status & MSDC_PS_CDSTS) ? 0 : 1; else @@ -471,19 +437,18 @@ static u8 clk_src_bit[4] = { static void msdc_select_clksrc(struct msdc_host *host, unsigned char clksrc) { u32 val; - void __iomem *base = host->base; BUG_ON(clksrc > 3); INIT_MSG("set clock source to <%d>", clksrc); - val = sdr_read32(MSDC_CLKSRC_REG); - if (sdr_read32(MSDC_ECO_VER) >= 4) { + val = readl(host->base + MSDC_CLKSRC_REG); + if (readl(host->base + MSDC_ECO_VER) >= 4) { val &= ~(0x3 << clk_src_bit[host->id]); val |= clksrc << clk_src_bit[host->id]; } else { val &= ~0x3; val |= clksrc; } - sdr_write32(MSDC_CLKSRC_REG, val); + writel(val, host->base + MSDC_CLKSRC_REG); host->hclk = hclks[clksrc]; host->hw->clk_src = clksrc; @@ -493,7 +458,6 @@ static void msdc_select_clksrc(struct msdc_host *host, unsigned char clksrc) static void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz) { //struct msdc_hw *hw = host->hw; - void __iomem *base = host->base; u32 mode; u32 flags; u32 div; @@ -534,11 +498,11 @@ static void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz) } /* set clock mode and divisor */ - sdr_set_field(MSDC_CFG, MSDC_CFG_CKMOD, mode); - sdr_set_field(MSDC_CFG, MSDC_CFG_CKDIV, div); + sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, mode); + sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKDIV, div); /* wait clock stable */ - while (!(sdr_read32(MSDC_CFG) & MSDC_CFG_CKSTB)) + while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) cpu_relax(); host->sclk = sclk; @@ -555,13 +519,12 @@ static void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz) /* Fix me. when need to abort */ static void msdc_abort_data(struct msdc_host *host) { - void __iomem *base = host->base; struct mmc_command *stop = host->mrq->stop; ERR_MSG("Need to Abort."); msdc_reset_hw(host); - msdc_clr_fifo(); + msdc_clr_fifo(host); msdc_clr_int(); // need to check FIFO count 0 ? @@ -580,7 +543,6 @@ static void msdc_abort_data(struct msdc_host *host) static void msdc_pin_config(struct msdc_host *host, int mode) { struct msdc_hw *hw = host->hw; - void __iomem *base = host->base; int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN; /* Config WP pin */ @@ -593,27 +555,27 @@ static void msdc_pin_config(struct msdc_host *host, int mode) case MSDC_PIN_PULL_UP: //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 1); /* Check & FIXME */ //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */ - sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 1); - sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0); - sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 1); - sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0); + sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 1); + sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0); + sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 1); + sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0); break; case MSDC_PIN_PULL_DOWN: //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */ //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 1); /* Check & FIXME */ - sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0); - sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 1); - sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0); - sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 1); + sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0); + sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 1); + sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0); + sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 1); break; case MSDC_PIN_PULL_NONE: default: //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */ //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */ - sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0); - sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0); - sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0); - sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0); + sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0); + sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0); + sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0); + sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0); break; } @@ -624,7 +586,6 @@ static void msdc_pin_config(struct msdc_host *host, int mode) void msdc_pin_reset(struct msdc_host *host, int mode) { struct msdc_hw *hw = (struct msdc_hw *)host->hw; - void __iomem *base = host->base; int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN; /* Config reset pin */ @@ -633,9 +594,9 @@ void msdc_pin_reset(struct msdc_host *host, int mode) hw->config_gpio_pin(MSDC_RST_PIN, pull); if (mode == MSDC_PIN_PULL_UP) - sdr_clr_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST); + sdr_clr_bits(host->base + EMMC_IOCON, EMMC_IOCON_BOOTRST); else - sdr_set_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST); + sdr_set_bits(host->base + EMMC_IOCON, EMMC_IOCON_BOOTRST); } } @@ -744,30 +705,12 @@ static void msdc_pm(pm_message_t state, void *data) } #endif -/*--------------------------------------------------------------------------*/ -/* mmc_host_ops members */ -/*--------------------------------------------------------------------------*/ -static unsigned int msdc_command_start(struct msdc_host *host, - struct mmc_command *cmd, - int tune, /* not used */ - unsigned long timeout) +static inline u32 msdc_cmd_find_resp(struct mmc_command *cmd) { - void __iomem *base = host->base; u32 opcode = cmd->opcode; - u32 rawcmd; - u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | - MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | - MSDC_INT_ACMD19_DONE; - u32 resp; - unsigned long tmo; - /* Protocol layer does not provide response type, but our hardware needs - * to know exact type, not just size! - */ - if (opcode == MMC_SEND_OP_COND || opcode == SD_APP_OP_COND) { - resp = RESP_R3; - } else if (opcode == MMC_SET_RELATIVE_ADDR) { + if (opcode == MMC_SET_RELATIVE_ADDR) { resp = (mmc_cmd_type(cmd) == MMC_CMD_BCR) ? RESP_R6 : RESP_R1; } else if (opcode == MMC_FAST_IO) { resp = RESP_R4; @@ -800,6 +743,30 @@ static unsigned int msdc_command_start(struct msdc_host *host, } } + return resp; +} + +/*--------------------------------------------------------------------------*/ +/* mmc_host_ops members */ +/*--------------------------------------------------------------------------*/ +static unsigned int msdc_command_start(struct msdc_host *host, + struct mmc_command *cmd, + unsigned long timeout) +{ + u32 opcode = cmd->opcode; + u32 rawcmd; + u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | + MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | + MSDC_INT_ACMD19_DONE; + + u32 resp; + unsigned long tmo; + + /* Protocol layer does not provide response type, but our hardware needs + * to know exact type, not just size! + */ + resp = msdc_cmd_find_resp(cmd); + cmd->error = 0; /* rawcmd : * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | @@ -870,7 +837,7 @@ static unsigned int msdc_command_start(struct msdc_host *host, init_completion(&host->cmd_done); - sdr_set_bits(MSDC_INTEN, wints); + sdr_set_bits(host->base + MSDC_INTEN, wints); sdc_send_cmd(rawcmd, cmd->arg); end: @@ -883,19 +850,15 @@ static unsigned int msdc_command_resp(struct msdc_host *host, unsigned long timeout) __must_hold(&host->lock) { - void __iomem *base = host->base; u32 opcode = cmd->opcode; //u32 rawcmd; - u32 resp; u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | MSDC_INT_ACMD19_DONE; - resp = host->cmd_rsp; - BUG_ON(in_interrupt()); //init_completion(&host->cmd_done); - //sdr_set_bits(MSDC_INTEN, wints); + //sdr_set_bits(host->base + MSDC_INTEN, wints); spin_unlock(&host->lock); if (!wait_for_completion_timeout(&host->cmd_done, 10 * timeout)) { @@ -905,7 +868,7 @@ static unsigned int msdc_command_resp(struct msdc_host *host, } spin_lock(&host->lock); - sdr_clr_bits(MSDC_INTEN, wints); + sdr_clr_bits(host->base + MSDC_INTEN, wints); host->cmd = NULL; //end: @@ -950,12 +913,13 @@ static unsigned int msdc_command_resp(struct msdc_host *host, /* memory card CRC */ if (host->hw->flags & MSDC_REMOVABLE && cmd->error == -EIO) { - if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */ + /* check if has data phase */ + if (readl(host->base + SDC_CMD) & 0x1800) { msdc_abort_data(host); } else { /* do basic: reset*/ msdc_reset_hw(host); - msdc_clr_fifo(); + msdc_clr_fifo(host); msdc_clr_int(); } cmd->error = msdc_tune_cmdrsp(host, cmd); @@ -963,7 +927,7 @@ static unsigned int msdc_command_resp(struct msdc_host *host, // check DAT0 /* if (resp == RESP_R1B) { - while ((sdr_read32(MSDC_PS) & 0x10000) != 0x10000); + while ((readl(host->base + MSDC_PS) & 0x10000) != 0x10000); } */ /* CMD12 Error Handle */ @@ -975,7 +939,7 @@ static unsigned int msdc_do_command(struct msdc_host *host, int tune, unsigned long timeout) { - if (msdc_command_start(host, cmd, tune, timeout)) + if (msdc_command_start(host, cmd, timeout)) goto end; if (msdc_command_resp(host, cmd, tune, timeout)) @@ -991,9 +955,7 @@ end: // DMA resume / start / stop static void msdc_dma_resume(struct msdc_host *host) { - void __iomem *base = host->base; - - sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_RESUME, 1); + sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_RESUME, 1); N_MSG(DMA, "DMA resume"); } @@ -1001,31 +963,29 @@ static void msdc_dma_resume(struct msdc_host *host) static void msdc_dma_start(struct msdc_host *host) { - void __iomem *base = host->base; u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR; - sdr_set_bits(MSDC_INTEN, wints); + sdr_set_bits(host->base + MSDC_INTEN, wints); //dsb(); /* --- by chhung */ - sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); + sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); N_MSG(DMA, "DMA start"); } static void msdc_dma_stop(struct msdc_host *host) { - void __iomem *base = host->base; //u32 retries=500; u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR; - N_MSG(DMA, "DMA status: 0x%.8x", sdr_read32(MSDC_DMA_CFG)); - //while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS); + N_MSG(DMA, "DMA status: 0x%.8x", readl(host->base + MSDC_DMA_CFG)); + //while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS); - sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1); - while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) + sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1); + while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) ; //dsb(); /* --- by chhung */ - sdr_clr_bits(MSDC_INTEN, wints); /* Not just xfer_comp */ + sdr_clr_bits(host->base + MSDC_INTEN, wints); /* Not just xfer_comp */ N_MSG(DMA, "DMA stop"); } @@ -1040,97 +1000,54 @@ static u8 msdc_dma_calcs(u8 *buf, u32 len) return 0xFF - (u8)sum; } -/* gpd bd setup + dma registers */ -static void msdc_dma_config(struct msdc_host *host, struct msdc_dma *dma) +static void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, + struct scatterlist *sg_cmd, unsigned int sglen) { - void __iomem *base = host->base; - //u32 i, j, num, bdlen, arg, xfersz; - u32 j, num; struct scatterlist *sg; struct gpd *gpd; struct bd *bd; + u32 j; - switch (dma->mode) { - case MSDC_MODE_DMA_BASIC: - BUG_ON(host->xfer_size > 65535); - BUG_ON(dma->sglen != 1); - sdr_write32(MSDC_DMA_SA, PHYSADDR(sg_dma_address(sg))); - sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_LASTBUF, 1); -//#if defined (CONFIG_RALINK_MT7620) - if (ralink_soc == MT762X_SOC_MT7620A) - sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_XFERSZ, sg_dma_len(sg)); -//#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) - else - sdr_write32((void __iomem *)(RALINK_MSDC_BASE + 0xa8), sg_dma_len(sg)); -//#endif - sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, - MSDC_BRUST_64B); - sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 0); - break; - case MSDC_MODE_DMA_DESC: - - /* calculate the required number of gpd */ - num = (dma->sglen + MAX_BD_PER_GPD - 1) / MAX_BD_PER_GPD; - BUG_ON(num != 1); - - gpd = dma->gpd; - bd = dma->bd; - - /* modify gpd*/ - //gpd->intr = 0; - gpd->hwo = 1; /* hw will clear it */ - gpd->bdp = 1; - gpd->chksum = 0; /* need to clear first. */ - gpd->chksum = msdc_dma_calcs((u8 *)gpd, 16); - - /* modify bd*/ - for_each_sg(dma->sg, sg, dma->sglen, j) { - bd[j].blkpad = 0; - bd[j].dwpad = 0; - bd[j].ptr = (void *)sg_dma_address(sg); - bd[j].buflen = sg_dma_len(sg); - - if (j == dma->sglen - 1) - bd[j].eol = 1; /* the last bd */ - else - bd[j].eol = 0; - - bd[j].chksum = 0; /* checksume need to clear first */ - bd[j].chksum = msdc_dma_calcs((u8 *)(&bd[j]), 16); - } + BUG_ON(sglen > MAX_BD_NUM); /* not support currently */ - sdr_set_field(MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); - sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, - MSDC_BRUST_64B); - sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1); + N_MSG(DMA, "DMA sglen<%d> xfersz<%d>", sglen, host->xfer_size); - sdr_write32(MSDC_DMA_SA, PHYSADDR((u32)dma->gpd_addr)); - break; - - default: - break; - } + gpd = dma->gpd; + bd = dma->bd; - N_MSG(DMA, "DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL)); - N_MSG(DMA, "DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG)); - N_MSG(DMA, "DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA)); + /* modify gpd*/ + //gpd->intr = 0; + gpd->hwo = 1; /* hw will clear it */ + gpd->bdp = 1; + gpd->chksum = 0; /* need to clear first. */ + gpd->chksum = msdc_dma_calcs((u8 *)gpd, 16); -} + /* modify bd*/ + for_each_sg(sg_cmd, sg, sglen, j) { + bd[j].blkpad = 0; + bd[j].dwpad = 0; + bd[j].ptr = (void *)sg_dma_address(sg); + bd[j].buflen = sg_dma_len(sg); -static void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, - struct scatterlist *sg, unsigned int sglen) -{ - BUG_ON(sglen > MAX_BD_NUM); /* not support currently */ + if (j == sglen - 1) + bd[j].eol = 1; /* the last bd */ + else + bd[j].eol = 0; - dma->sg = sg; - dma->sglen = sglen; + bd[j].chksum = 0; /* checksume need to clear first */ + bd[j].chksum = msdc_dma_calcs((u8 *)(&bd[j]), 16); + } - dma->mode = MSDC_MODE_DMA_DESC; + sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); + sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, + MSDC_BRUST_64B); + sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1); - N_MSG(DMA, "DMA mode<%d> sglen<%d> xfersz<%d>", dma->mode, dma->sglen, - host->xfer_size); + writel(PHYSADDR((u32)dma->gpd_addr), host->base + MSDC_DMA_SA); - msdc_dma_config(host, dma); + N_MSG(DMA, "DMA_CTRL = 0x%x", readl(host->base + MSDC_DMA_CTRL)); + N_MSG(DMA, "DMA_CFG = 0x%x", readl(host->base + MSDC_DMA_CFG)); + N_MSG(DMA, "DMA_SA = 0x%x", readl(host->base + MSDC_DMA_SA)); } static int msdc_do_request(struct mmc_host *mmc, struct mmc_request *mrq) @@ -1139,7 +1056,6 @@ static int msdc_do_request(struct mmc_host *mmc, struct mmc_request *mrq) struct msdc_host *host = mmc_priv(mmc); struct mmc_command *cmd; struct mmc_data *data; - void __iomem *base = host->base; //u32 intsts = 0; int read = 1, send_type = 0; @@ -1182,14 +1098,14 @@ static int msdc_do_request(struct mmc_host *mmc, struct mmc_request *mrq) } } - sdr_write32(SDC_BLK_NUM, data->blocks); - //msdc_clr_fifo(); /* no need */ + writel(data->blocks, host->base + SDC_BLK_NUM); + //msdc_clr_fifo(host); /* no need */ msdc_dma_on(); /* enable DMA mode first!! */ init_completion(&host->xfer_done); /* start the command first*/ - if (msdc_command_start(host, cmd, 1, CMD_TIMEOUT) != 0) + if (msdc_command_start(host, cmd, CMD_TIMEOUT) != 0) goto done; data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, @@ -1210,14 +1126,18 @@ static int msdc_do_request(struct mmc_host *mmc, struct mmc_request *mrq) spin_unlock(&host->lock); if (!wait_for_completion_timeout(&host->xfer_done, DAT_TIMEOUT)) { ERR_MSG("XXX CMD<%d> wait xfer_done<%d> timeout!!", cmd->opcode, data->blocks * data->blksz); - ERR_MSG(" DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA)); - ERR_MSG(" DMA_CA = 0x%x", sdr_read32(MSDC_DMA_CA)); - ERR_MSG(" DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL)); - ERR_MSG(" DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG)); + ERR_MSG(" DMA_SA = 0x%x", + readl(host->base + MSDC_DMA_SA)); + ERR_MSG(" DMA_CA = 0x%x", + readl(host->base + MSDC_DMA_CA)); + ERR_MSG(" DMA_CTRL = 0x%x", + readl(host->base + MSDC_DMA_CTRL)); + ERR_MSG(" DMA_CFG = 0x%x", + readl(host->base + MSDC_DMA_CFG)); data->error = -ETIMEDOUT; msdc_reset_hw(host); - msdc_clr_fifo(); + msdc_clr_fifo(host); msdc_clr_int(); } spin_lock(&host->lock); @@ -1311,7 +1231,6 @@ static int msdc_app_cmd(struct mmc_host *mmc, struct msdc_host *host) static int msdc_tune_cmdrsp(struct msdc_host *host, struct mmc_command *cmd) { int result = -1; - void __iomem *base = host->base; u32 rsmpl, cur_rsmpl, orig_rsmpl; u32 rrdly, cur_rrdly = 0xffffffff, orig_rrdly; u32 skip = 1; @@ -1322,8 +1241,9 @@ static int msdc_tune_cmdrsp(struct msdc_host *host, struct mmc_command *cmd) ==========================*/ // save the previous tune result - sdr_get_field(MSDC_IOCON, MSDC_IOCON_RSPL, &orig_rsmpl); - sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, &orig_rrdly); + sdr_get_field(host->base + MSDC_IOCON, MSDC_IOCON_RSPL, &orig_rsmpl); + sdr_get_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, + &orig_rrdly); rrdly = 0; do { @@ -1334,7 +1254,8 @@ static int msdc_tune_cmdrsp(struct msdc_host *host, struct mmc_command *cmd) skip = 0; continue; } - sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, cur_rsmpl); + sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_RSPL, + cur_rsmpl); if (host->app_cmd) { result = msdc_app_cmd(host->mmc, host); @@ -1356,14 +1277,15 @@ static int msdc_tune_cmdrsp(struct msdc_host *host, struct mmc_command *cmd) } /* should be EIO */ - if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */ + /* check if has data phase */ + if (readl(host->base + SDC_CMD) & 0x1800) msdc_abort_data(host); - } } /* Lv2: PAD_CMD_RESP_RXDLY[26:22] */ cur_rrdly = (orig_rrdly + rrdly + 1) % 32; - sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, cur_rrdly); + sdr_set_field(host->base + MSDC_PAD_TUNE, + MSDC_PAD_TUNE_CMDRRDLY, cur_rrdly); } while (++rrdly < 32); return result; @@ -1373,7 +1295,6 @@ static int msdc_tune_cmdrsp(struct msdc_host *host, struct mmc_command *cmd) static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq) { struct msdc_host *host = mmc_priv(mmc); - void __iomem *base = host->base; u32 ddr = 0; u32 dcrc = 0; u32 rxdly, cur_rxdly0, cur_rxdly1; @@ -1385,10 +1306,10 @@ static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq) int result = -1; u32 skip = 1; - sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, &orig_dsmpl); + sdr_get_field(host->base + MSDC_IOCON, MSDC_IOCON_DSPL, &orig_dsmpl); /* Tune Method 2. */ - sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1); + sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 1); rxdly = 0; do { @@ -1398,7 +1319,8 @@ static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq) skip = 0; continue; } - sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl); + sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DSPL, + cur_dsmpl); if (host->app_cmd) { result = msdc_app_cmd(host->mmc, host); @@ -1409,14 +1331,15 @@ static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq) } result = msdc_do_request(mmc, mrq); - sdr_get_field(SDC_DCRC_STS, + sdr_get_field(host->base + SDC_DCRC_STS, SDC_DCRC_STS_POS | SDC_DCRC_STS_NEG, &dcrc); /* RO */ if (!ddr) dcrc &= ~SDC_DCRC_STS_NEG; ERR_MSG("TUNE_BREAD<%s> dcrc<0x%x> DATRDDLY0/1<0x%x><0x%x> dsmpl<0x%x>", (result == 0 && dcrc == 0) ? "PASS" : "FAIL", dcrc, - sdr_read32(MSDC_DAT_RDDLY0), sdr_read32(MSDC_DAT_RDDLY1), cur_dsmpl); + readl(host->base + MSDC_DAT_RDDLY0), + readl(host->base + MSDC_DAT_RDDLY1), cur_dsmpl); /* Fix me: result is 0, but dcrc is still exist */ if (result == 0 && dcrc == 0) { @@ -1432,11 +1355,11 @@ static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq) } } - cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0); - cur_rxdly1 = sdr_read32(MSDC_DAT_RDDLY1); + cur_rxdly0 = readl(host->base + MSDC_DAT_RDDLY0); + cur_rxdly1 = readl(host->base + MSDC_DAT_RDDLY1); /* E1 ECO. YD: Reverse */ - if (sdr_read32(MSDC_ECO_VER) >= 4) { + if (readl(host->base + MSDC_ECO_VER) >= 4) { orig_dat0 = (cur_rxdly0 >> 24) & 0x1F; orig_dat1 = (cur_rxdly0 >> 16) & 0x1F; orig_dat2 = (cur_rxdly0 >> 8) & 0x1F; @@ -1475,8 +1398,8 @@ static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq) cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0); cur_rxdly1 = (cur_dat4 << 24) | (cur_dat5 << 16) | (cur_dat6 << 8) | (cur_dat7 << 0); - sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0); - sdr_write32(MSDC_DAT_RDDLY1, cur_rxdly1); + writel(cur_rxdly0, host->base + MSDC_DAT_RDDLY0); + writel(cur_rxdly1, host->base + MSDC_DAT_RDDLY1); } while (++rxdly < 32); @@ -1487,7 +1410,6 @@ done: static int msdc_tune_bwrite(struct mmc_host *mmc, struct mmc_request *mrq) { struct msdc_host *host = mmc_priv(mmc); - void __iomem *base = host->base; u32 wrrdly, cur_wrrdly = 0xffffffff, orig_wrrdly; u32 dsmpl, cur_dsmpl, orig_dsmpl; @@ -1499,15 +1421,16 @@ static int msdc_tune_bwrite(struct mmc_host *mmc, struct mmc_request *mrq) // MSDC_IOCON_DDR50CKD need to check. [Fix me] - sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, &orig_wrrdly); - sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, &orig_dsmpl); + sdr_get_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, + &orig_wrrdly); + sdr_get_field(host->base + MSDC_IOCON, MSDC_IOCON_DSPL, &orig_dsmpl); /* Tune Method 2. just DAT0 */ - sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1); - cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0); + sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 1); + cur_rxdly0 = readl(host->base + MSDC_DAT_RDDLY0); /* E1 ECO. YD: Reverse */ - if (sdr_read32(MSDC_ECO_VER) >= 4) { + if (readl(host->base + MSDC_ECO_VER) >= 4) { orig_dat0 = (cur_rxdly0 >> 24) & 0x1F; orig_dat1 = (cur_rxdly0 >> 16) & 0x1F; orig_dat2 = (cur_rxdly0 >> 8) & 0x1F; @@ -1529,7 +1452,8 @@ static int msdc_tune_bwrite(struct mmc_host *mmc, struct mmc_request *mrq) skip = 0; continue; } - sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl); + sdr_set_field(host->base + MSDC_IOCON, + MSDC_IOCON_DSPL, cur_dsmpl); if (host->app_cmd) { result = msdc_app_cmd(host->mmc, host); @@ -1556,7 +1480,8 @@ static int msdc_tune_bwrite(struct mmc_host *mmc, struct mmc_request *mrq) } } cur_wrrdly = (orig_wrrdly + wrrdly + 1) % 32; - sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, cur_wrrdly); + sdr_set_field(host->base + MSDC_PAD_TUNE, + MSDC_PAD_TUNE_DATWRDLY, cur_wrrdly); } while (++wrrdly < 32); cur_dat0 = (orig_dat0 + rxdly) % 32; /* only adjust bit-1 for crc */ @@ -1565,7 +1490,7 @@ static int msdc_tune_bwrite(struct mmc_host *mmc, struct mmc_request *mrq) cur_dat3 = orig_dat3; cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0); - sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0); + writel(cur_rxdly0, host->base + MSDC_DAT_RDDLY0); } while (++rxdly < 32); done: @@ -1620,12 +1545,10 @@ static int msdc_check_busy(struct mmc_host *mmc, struct msdc_host *host) static int msdc_tune_request(struct mmc_host *mmc, struct mmc_request *mrq) { struct msdc_host *host = mmc_priv(mmc); - struct mmc_command *cmd; struct mmc_data *data; //u32 base = host->base; int ret = 0, read; - cmd = mrq->cmd; data = mrq->cmd->data; read = data->flags & MMC_DATA_READ ? 1 : 0; @@ -1717,8 +1640,7 @@ static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) /* called by ops.set_ios */ static void msdc_set_buswidth(struct msdc_host *host, u32 width) { - void __iomem *base = host->base; - u32 val = sdr_read32(SDC_CFG); + u32 val = readl(host->base + SDC_CFG); val &= ~SDC_CFG_BUSWIDTH; @@ -1736,7 +1658,7 @@ static void msdc_set_buswidth(struct msdc_host *host, u32 width) break; } - sdr_write32(SDC_CFG, val); + writel(val, host->base + SDC_CFG); N_MSG(CFG, "Bus Width = %d", width); } @@ -1745,7 +1667,6 @@ static void msdc_set_buswidth(struct msdc_host *host, u32 width) static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { struct msdc_host *host = mmc_priv(mmc); - void __iomem *base = host->base; u32 ddr = 0; #ifdef MT6575_SD_DEBUG @@ -1791,18 +1712,23 @@ static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) if (ios->clock > 25000000) { //if (!(host->hw->flags & MSDC_REMOVABLE)) { INIT_MSG("SD data latch edge<%d>", MSDC_SMPL_FALLING); - sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, + sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_RSPL, MSDC_SMPL_FALLING); - sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, + sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DSPL, MSDC_SMPL_FALLING); //} /* for tuning debug */ } else { /* default value */ - sdr_write32(MSDC_IOCON, 0x00000000); - // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000); - sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward - sdr_write32(MSDC_DAT_RDDLY1, 0x00000000); - // sdr_write32(MSDC_PAD_TUNE, 0x00000000); - sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward + writel(0x00000000, host->base + MSDC_IOCON); + // writel(0x00000000, host->base + MSDC_DAT_RDDLY0); + + // for MT7620 E2 and afterward + writel(0x10101010, host->base + MSDC_DAT_RDDLY0); + + writel(0x00000000, host->base + MSDC_DAT_RDDLY1); + // writel(0x00000000, host->base + MSDC_PAD_TUNE); + + // for MT7620 E2 and afterward + writel(0x84101010, host->base + MSDC_PAD_TUNE); } msdc_set_mclk(host, ddr, ios->clock); } @@ -1812,13 +1738,12 @@ static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) static int msdc_ops_get_ro(struct mmc_host *mmc) { struct msdc_host *host = mmc_priv(mmc); - void __iomem *base = host->base; unsigned long flags; int ro = 0; if (host->hw->flags & MSDC_WP_PIN_EN) { /* set for card */ spin_lock_irqsave(&host->lock, flags); - ro = (sdr_read32(MSDC_PS) >> 31); + ro = (readl(host->base + MSDC_PS) >> 31); spin_unlock_irqrestore(&host->lock, flags); } return ro; @@ -1828,7 +1753,6 @@ static int msdc_ops_get_ro(struct mmc_host *mmc) static int msdc_ops_get_cd(struct mmc_host *mmc) { struct msdc_host *host = mmc_priv(mmc); - void __iomem *base = host->base; unsigned long flags; int present = 1; @@ -1852,10 +1776,11 @@ static int msdc_ops_get_cd(struct mmc_host *mmc) present = host->card_inserted; /* why not read from H/W: Fix me*/ #else // CD + present = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; if (cd_active_low) - present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1; + present = present ? 0 : 1; else - present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 1 : 0; + present = present ? 1 : 0; host->card_inserted = present; #endif spin_unlock_irqrestore(&host->lock, flags); @@ -1882,17 +1807,16 @@ static irqreturn_t msdc_irq(int irq, void *dev_id) struct msdc_host *host = (struct msdc_host *)dev_id; struct mmc_data *data = host->data; struct mmc_command *cmd = host->cmd; - void __iomem *base = host->base; u32 cmdsts = MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | MSDC_INT_CMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | MSDC_INT_ACMDRDY | MSDC_INT_ACMD19_DONE; u32 datsts = MSDC_INT_DATCRCERR | MSDC_INT_DATTMO; - u32 intsts = sdr_read32(MSDC_INT); - u32 inten = sdr_read32(MSDC_INTEN); inten &= intsts; + u32 intsts = readl(host->base + MSDC_INT); + u32 inten = readl(host->base + MSDC_INTEN); inten &= intsts; - sdr_write32(MSDC_INT, intsts); /* clear interrupts */ + writel(intsts, host->base + MSDC_INT); /* clear interrupts */ /* MSG will cause fatal error */ /* card change interrupt */ @@ -1920,18 +1844,18 @@ static irqreturn_t msdc_irq(int irq, void *dev_id) if (intsts & datsts) { /* do basic reset, or stop command will sdc_busy */ msdc_reset_hw(host); - msdc_clr_fifo(); + msdc_clr_fifo(host); msdc_clr_int(); if (intsts & MSDC_INT_DATTMO) { IRQ_MSG("XXX CMD<%d> MSDC_INT_DATTMO", host->mrq->cmd->opcode); data->error = -ETIMEDOUT; } else if (intsts & MSDC_INT_DATCRCERR) { - IRQ_MSG("XXX CMD<%d> MSDC_INT_DATCRCERR, SDC_DCRC_STS<0x%x>", host->mrq->cmd->opcode, sdr_read32(SDC_DCRC_STS)); + IRQ_MSG("XXX CMD<%d> MSDC_INT_DATCRCERR, SDC_DCRC_STS<0x%x>", host->mrq->cmd->opcode, readl(host->base + SDC_DCRC_STS)); data->error = -EIO; } - //if(sdr_read32(MSDC_INTEN) & MSDC_INT_XFER_COMPL) { + //if(readl(MSDC_INTEN) & MSDC_INT_XFER_COMPL) { complete(&host->xfer_done); /* Read CRC come fast, XFER_COMPL not enabled */ } } @@ -1946,14 +1870,16 @@ static irqreturn_t msdc_irq(int irq, void *dev_id) case RESP_NONE: break; case RESP_R2: - *rsp++ = sdr_read32(SDC_RESP3); *rsp++ = sdr_read32(SDC_RESP2); - *rsp++ = sdr_read32(SDC_RESP1); *rsp++ = sdr_read32(SDC_RESP0); + *rsp++ = readl(host->base + SDC_RESP3); + *rsp++ = readl(host->base + SDC_RESP2); + *rsp++ = readl(host->base + SDC_RESP1); + *rsp++ = readl(host->base + SDC_RESP0); break; default: /* Response types 1, 3, 4, 5, 6, 7(1b) */ if ((intsts & MSDC_INT_ACMDRDY) || (intsts & MSDC_INT_ACMD19_DONE)) - *rsp = sdr_read32(SDC_ACMD_RESP); + *rsp = readl(host->base + SDC_ACMD_RESP); else - *rsp = sdr_read32(SDC_RESP0); + *rsp = readl(host->base + SDC_RESP0); break; } } else if ((intsts & MSDC_INT_RSPCRCERR) || (intsts & MSDC_INT_ACMDCRCERR)) { @@ -1969,7 +1895,7 @@ static irqreturn_t msdc_irq(int irq, void *dev_id) IRQ_MSG("XXX CMD<%d> MSDC_INT_CMDTMO", cmd->opcode); cmd->error = -ETIMEDOUT; msdc_reset_hw(host); - msdc_clr_fifo(); + msdc_clr_fifo(host); msdc_clr_int(); } complete(&host->cmd_done); @@ -1977,7 +1903,8 @@ static irqreturn_t msdc_irq(int irq, void *dev_id) /* mmc irq interrupts */ if (intsts & MSDC_INT_MMCIRQ) - printk(KERN_INFO "msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\r\n", host->id, sdr_read32(SDC_CSTS)); + printk(KERN_INFO "msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\r\n", + host->id, readl(host->base + SDC_CSTS)); #ifdef MT6575_SD_DEBUG { @@ -2017,7 +1944,6 @@ static irqreturn_t msdc_irq(int irq, void *dev_id) static void msdc_enable_cd_irq(struct msdc_host *host, int enable) { struct msdc_hw *hw = host->hw; - void __iomem *base = host->base; /* for sdio, not set */ if ((hw->flags & MSDC_CD_PIN_EN) == 0) { @@ -2026,9 +1952,9 @@ static void msdc_enable_cd_irq(struct msdc_host *host, int enable) if (hw->config_gpio_pin) hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN); */ - sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN); - sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC); - sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP); + sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); + sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); + sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); return; } @@ -2044,17 +1970,20 @@ static void msdc_enable_cd_irq(struct msdc_host *host, int enable) if (hw->config_gpio_pin) /* NULL */ hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_UP); - sdr_set_field(MSDC_PS, MSDC_PS_CDDEBOUNCE, DEFAULT_DEBOUNCE); - sdr_set_bits(MSDC_PS, MSDC_PS_CDEN); - sdr_set_bits(MSDC_INTEN, MSDC_INTEN_CDSC); - sdr_set_bits(SDC_CFG, SDC_CFG_INSWKUP); /* not in document! Fix me */ + sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, + DEFAULT_DEBOUNCE); + sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); + sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); + + /* not in document! Fix me */ + sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); } else { if (hw->config_gpio_pin) /* NULL */ hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN); - sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP); - sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN); - sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC); + sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); + sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); + sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); /* Here decreases a reference count to core power since card * detection circuit is shutdown. @@ -2066,7 +1995,6 @@ static void msdc_enable_cd_irq(struct msdc_host *host, int enable) /* called by msdc_drv_probe */ static void msdc_init_hw(struct msdc_host *host) { - void __iomem *base = host->base; /* Power on */ #if 0 /* --- by chhung */ @@ -2077,41 +2005,51 @@ static void msdc_init_hw(struct msdc_host *host) msdc_vdd_on(host); #endif /* end of --- */ /* Configure to MMC/SD mode */ - sdr_set_field(MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC); + sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC); /* Reset */ msdc_reset_hw(host); - msdc_clr_fifo(); + msdc_clr_fifo(host); /* Disable card detection */ - sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN); + sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); /* Disable and clear all interrupts */ - sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN)); - sdr_write32(MSDC_INT, sdr_read32(MSDC_INT)); + sdr_clr_bits(host->base + MSDC_INTEN, readl(host->base + MSDC_INTEN)); + writel(readl(host->base + MSDC_INT), host->base + MSDC_INT); #if 1 /* reset tuning parameter */ - sdr_write32(MSDC_PAD_CTL0, 0x00090000); - sdr_write32(MSDC_PAD_CTL1, 0x000A0000); - sdr_write32(MSDC_PAD_CTL2, 0x000A0000); - // sdr_write32(MSDC_PAD_TUNE, 0x00000000); - sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward - // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000); - sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward - sdr_write32(MSDC_DAT_RDDLY1, 0x00000000); - sdr_write32(MSDC_IOCON, 0x00000000); + writel(0x00090000, host->base + MSDC_PAD_CTL0); + writel(0x000A0000, host->base + MSDC_PAD_CTL1); + writel(0x000A0000, host->base + MSDC_PAD_CTL2); + // writel( 0x00000000, host->base + MSDC_PAD_TUNE); + + // for MT7620 E2 and afterward + writel(0x84101010, host->base + MSDC_PAD_TUNE); + + // writel(0x00000000, host->base + MSDC_DAT_RDDLY0); + + // for MT7620 E2 and afterward + writel(0x10101010, host->base + MSDC_DAT_RDDLY0); + + writel(0x00000000, host->base + MSDC_DAT_RDDLY1); + writel(0x00000000, host->base + MSDC_IOCON); #if 0 // use MT7620 default value: 0x403c004f - sdr_write32(MSDC_PATCH_BIT0, 0x003C000F); /* bit0 modified: Rx Data Clock Source: 1 -> 2.0*/ + /* bit0 modified: Rx Data Clock Source: 1 -> 2.0*/ + writel(0x003C000F, host->base + MSDC_PATCH_BIT0); #endif - if (sdr_read32(MSDC_ECO_VER) >= 4) { + if (readl(host->base + MSDC_ECO_VER) >= 4) { if (host->id == 1) { - sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_WRDAT_CRCS, 1); - sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMD_RSP, 1); + sdr_set_field(host->base + MSDC_PATCH_BIT1, + MSDC_PATCH_BIT1_WRDAT_CRCS, 1); + sdr_set_field(host->base + MSDC_PATCH_BIT1, + MSDC_PATCH_BIT1_CMD_RSP, 1); /* internal clock: latch read data */ - sdr_set_bits(MSDC_PATCH_BIT0, MSDC_PATCH_BIT_CKGEN_CK); + sdr_set_bits(host->base + MSDC_PATCH_BIT0, + MSDC_PATCH_BIT_CKGEN_CK); } } #endif @@ -2120,40 +2058,40 @@ static void msdc_init_hw(struct msdc_host *host) pre-loader,uboot,kernel drivers. and SDC_CFG.SDIO_INT_DET_EN will be only set when kernel driver wants to use SDIO bus interrupt */ /* Configure to enable SDIO mode. it's must otherwise sdio cmd5 failed */ - sdr_set_bits(SDC_CFG, SDC_CFG_SDIO); + sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); /* disable detect SDIO device interupt function */ - sdr_clr_bits(SDC_CFG, SDC_CFG_SDIOIDE); + sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); /* eneable SMT for glitch filter */ - sdr_set_bits(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKSMT); - sdr_set_bits(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDSMT); - sdr_set_bits(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATSMT); + sdr_set_bits(host->base + MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKSMT); + sdr_set_bits(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDSMT); + sdr_set_bits(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATSMT); #if 1 /* set clk, cmd, dat pad driving */ - sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 4); - sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 4); - sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 4); - sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 4); - sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 4); - sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 4); + sdr_set_field(host->base + MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 4); + sdr_set_field(host->base + MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 4); + sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 4); + sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 4); + sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 4); + sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 4); #else - sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 0); - sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 0); - sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 0); - sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 0); - sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 0); - sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 0); + sdr_set_field(host->base + MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 0); + sdr_set_field(host->base + MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 0); + sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 0); + sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 0); + sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 0); + sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 0); #endif /* set sampling edge */ /* write crc timeout detection */ - sdr_set_field(MSDC_PATCH_BIT0, 1 << 30, 1); + sdr_set_field(host->base + MSDC_PATCH_BIT0, 1 << 30, 1); /* Configure to default data timeout */ - sdr_set_field(SDC_CFG, SDC_CFG_DTOC, DEFAULT_DTOC); + sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, DEFAULT_DTOC); msdc_set_buswidth(host, MMC_BUS_WIDTH_1); @@ -2163,11 +2101,9 @@ static void msdc_init_hw(struct msdc_host *host) /* called by msdc_drv_remove */ static void msdc_deinit_hw(struct msdc_host *host) { - void __iomem *base = host->base; - /* Disable and clear all interrupts */ - sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN)); - sdr_write32(MSDC_INT, sdr_read32(MSDC_INT)); + sdr_clr_bits(host->base + MSDC_INTEN, readl(host->base + MSDC_INTEN)); + writel(readl(host->base + MSDC_INT), host->base + MSDC_INT); /* Disable card detection */ msdc_enable_cd_irq(host, 0); @@ -2429,8 +2365,8 @@ static int __init mt_msdc_init(void) // Set the pins for sdxc to sdxc mode //FIXME: this should be done by pinctl and not by the sd driver - reg = sdr_read32((void __iomem *)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3 << 18); - sdr_write32((void __iomem *)(RALINK_SYSCTL_BASE + 0x60), reg); + reg = readl((void __iomem *)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3 << 18); + writel(reg, (void __iomem *)(RALINK_SYSCTL_BASE + 0x60)); ret = platform_driver_register(&mt_msdc_driver); if (ret) { |