diff options
Diffstat (limited to 'drivers/staging/mt7621-pci/pci-mt7621.c')
| -rw-r--r-- | drivers/staging/mt7621-pci/pci-mt7621.c | 827 |
1 files changed, 425 insertions, 402 deletions
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index 17f2105ec698..a49e2795af6b 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /************************************************************************** * * BRIEF MODULE DESCRIPTION @@ -39,431 +40,290 @@ ************************************************************************** */ -#include <linux/types.h> -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/slab.h> -#include <linux/version.h> -#include <asm/pci.h> -#include <asm/io.h> -#include <asm/mips-cm.h> -#include <linux/init.h> -#include <linux/module.h> +#include <linux/bitops.h> +#include <linux/clk.h> #include <linux/delay.h> +#include <linux/module.h> #include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> #include <linux/of_pci.h> +#include <linux/of_platform.h> +#include <linux/pci.h> #include <linux/platform_device.h> - +#include <linux/reset.h> +#include <mt7621.h> #include <ralink_regs.h> +#include "../../pci/pci.h" + /* * These functions and structures provide the BIOS scan and mapping of the PCI * devices. */ -#define RALINK_PCIE0_CLK_EN (1<<24) -#define RALINK_PCIE1_CLK_EN (1<<25) -#define RALINK_PCIE2_CLK_EN (1<<26) +#define RALINK_PCIE0_CLK_EN BIT(24) +#define RALINK_PCIE1_CLK_EN BIT(25) +#define RALINK_PCIE2_CLK_EN BIT(26) #define RALINK_PCI_CONFIG_ADDR 0x20 -#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24 -#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028) -#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C) -#define RALINK_PCIE0_RST (1<<24) -#define RALINK_PCIE1_RST (1<<25) -#define RALINK_PCIE2_RST (1<<26) -#define RALINK_SYSCTL_BASE 0xBE000000 - -#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000) -#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C) -#define RALINK_PCI_BASE 0xBE140000 - -#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000) +#define RALINK_PCI_CONFIG_DATA 0x24 +#define RALINK_PCI_MEMBASE 0x28 +#define RALINK_PCI_IOBASE 0x2C +#define RALINK_PCIE0_RST BIT(24) +#define RALINK_PCIE1_RST BIT(25) +#define RALINK_PCIE2_RST BIT(26) + +#define RALINK_PCI_PCICFG_ADDR 0x0000 +#define RALINK_PCI_PCIMSK_ADDR 0x000C + #define RT6855_PCIE0_OFFSET 0x2000 #define RT6855_PCIE1_OFFSET 0x3000 #define RT6855_PCIE2_OFFSET 0x4000 -#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010) -#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018) -#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030) -#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034) -#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038) -#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050) -#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060) -#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064) - -#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010) -#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018) -#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030) -#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034) -#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038) -#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050) -#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060) -#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064) - -#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010) -#define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018) -#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030) -#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034) -#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038) -#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050) -#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060) -#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064) - -#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000) -#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000) - -#define MV_WRITE(ofs, data) \ - *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data) -#define MV_READ(ofs, data) \ - *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs))) -#define MV_READ_DATA(ofs) \ - le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs))) - -#define MV_WRITE_16(ofs, data) \ - *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data) -#define MV_READ_16(ofs, data) \ - *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs))) - -#define MV_WRITE_8(ofs, data) \ - *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data -#define MV_READ_8(ofs, data) \ - *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) +#define RALINK_PCI_BAR0SETUP_ADDR 0x0010 +#define RALINK_PCI_IMBASEBAR0_ADDR 0x0018 +#define RALINK_PCI_ID 0x0030 +#define RALINK_PCI_CLASS 0x0034 +#define RALINK_PCI_SUBID 0x0038 +#define RALINK_PCI_STATUS 0x0050 + +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET 0x9000 +#define RALINK_PCIEPHY_P2_CTL_OFFSET 0xA000 #define RALINK_PCI_MM_MAP_BASE 0x60000000 #define RALINK_PCI_IO_MAP_BASE 0x1e160000 -#define RALINK_SYSTEM_CONTROL_BASE 0xbe000000 - #define ASSERT_SYSRST_PCIE(val) \ do { \ - if (*(unsigned int *)(0xbe00000c) == 0x00030101) \ - RALINK_RSTCTRL |= val; \ + if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101) \ + rt_sysc_m32(0, val, RALINK_RSTCTRL); \ else \ - RALINK_RSTCTRL &= ~val; \ - } while(0) + rt_sysc_m32(val, 0, RALINK_RSTCTRL); \ + } while (0) #define DEASSERT_SYSRST_PCIE(val) \ do { \ - if (*(unsigned int *)(0xbe00000c) == 0x00030101) \ - RALINK_RSTCTRL &= ~val; \ + if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101) \ + rt_sysc_m32(val, 0, RALINK_RSTCTRL); \ else \ - RALINK_RSTCTRL |= val; \ - } while(0) -#define RALINK_SYSCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14) -#define RALINK_CLKCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30) -#define RALINK_RSTCTRL *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34) -#define RALINK_GPIOMODE *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x60) -#define RALINK_PCIE_CLK_GEN *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c) -#define RALINK_PCIE_CLK_GEN1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x80) -#define PPLL_CFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x9c) -#define PPLL_DRV *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0xa0) -//RALINK_SYSCFG1 bit -#define RALINK_PCI_HOST_MODE_EN (1<<7) -#define RALINK_PCIE_RC_MODE_EN (1<<8) + rt_sysc_m32(0, val, RALINK_RSTCTRL); \ + } while (0) + +#define RALINK_CLKCFG1 0x30 +#define RALINK_RSTCTRL 0x34 +#define RALINK_GPIOMODE 0x60 +#define RALINK_PCIE_CLK_GEN 0x7c +#define RALINK_PCIE_CLK_GEN1 0x80 //RALINK_RSTCTRL bit -#define RALINK_PCIE_RST (1<<23) -#define RALINK_PCI_RST (1<<24) +#define RALINK_PCIE_RST BIT(23) +#define RALINK_PCI_RST BIT(24) //RALINK_CLKCFG1 bit -#define RALINK_PCI_CLK_EN (1<<19) -#define RALINK_PCIE_CLK_EN (1<<21) -//RALINK_GPIOMODE bit -#define PCI_SLOTx2 (1<<11) -#define PCI_SLOTx1 (2<<11) -//MTK PCIE PLL bit -#define PDRV_SW_SET (1<<31) -#define LC_CKDRVPD_ (1<<19) +#define RALINK_PCI_CLK_EN BIT(19) +#define RALINK_PCIE_CLK_EN BIT(21) #define MEMORY_BASE 0x0 static int pcie_link_status = 0; -#define PCI_ACCESS_READ_1 0 -#define PCI_ACCESS_READ_2 1 -#define PCI_ACCESS_READ_4 2 -#define PCI_ACCESS_WRITE_1 3 -#define PCI_ACCESS_WRITE_2 4 -#define PCI_ACCESS_WRITE_4 5 - -static int config_access(unsigned char access_type, struct pci_bus *bus, - unsigned int devfn, unsigned int where, u32 * data) -{ - unsigned int slot = PCI_SLOT(devfn); - u8 func = PCI_FUNC(devfn); - uint32_t address_reg, data_reg; - unsigned int address; - - address_reg = RALINK_PCI_CONFIG_ADDR; - data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG; - - address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) | - (func << 8) | (where & 0xfc) | 0x80000000; - MV_WRITE(address_reg, address); - - switch(access_type) { - case PCI_ACCESS_WRITE_1: - MV_WRITE_8(data_reg+(where&0x3), *data); - break; - case PCI_ACCESS_WRITE_2: - MV_WRITE_16(data_reg+(where&0x3), *data); - break; - case PCI_ACCESS_WRITE_4: - MV_WRITE(data_reg, *data); - break; - case PCI_ACCESS_READ_1: - MV_READ_8( data_reg+(where&0x3), data); - break; - case PCI_ACCESS_READ_2: - MV_READ_16(data_reg+(where&0x3), data); - break; - case PCI_ACCESS_READ_4: - MV_READ(data_reg, data); - break; - default: - printk("no specify access type\n"); - break; - } - return 0; -} - -static int -read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val) -{ - return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val); -} +/** + * struct mt7621_pcie_port - PCIe port information + * @base: IO mapped register base + * @list: port list + * @pcie: pointer to PCIe host info + * @reset: pointer to port reset control + */ +struct mt7621_pcie_port { + void __iomem *base; + struct list_head list; + struct mt7621_pcie *pcie; + struct reset_control *reset; +}; -static int -read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val) -{ - return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val); -} +/** + * struct mt7621_pcie - PCIe host information + * @base: IO Mapped Register Base + * @io: IO resource + * @mem: non-prefetchable memory resource + * @busn: bus range + * @offset: IO / Memory offset + * @dev: Pointer to PCIe device + * @ports: pointer to PCIe port information + */ +struct mt7621_pcie { + void __iomem *base; + struct device *dev; + struct resource io; + struct resource mem; + struct resource busn; + struct { + resource_size_t mem; + resource_size_t io; + } offset; + struct list_head ports; +}; -static int -read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val) +static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg) { - return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val); + return readl(pcie->base + reg); } -static int -write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val) +static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg) { - if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val)) - return -1; - - return PCIBIOS_SUCCESSFUL; + writel(val, pcie->base + reg); } -static int -write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val) +static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot, + unsigned int func, unsigned int where) { - if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val)) - return -1; - - return PCIBIOS_SUCCESSFUL; + return (((where & 0xF00) >> 8) << 24) | (bus << 16) | (slot << 11) | + (func << 8) | (where & 0xfc) | 0x80000000; } -static int -write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val) +static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus, + unsigned int devfn, int where) { - if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val)) - return -1; - - return PCIBIOS_SUCCESSFUL; -} + struct mt7621_pcie *pcie = bus->sysdata; + u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), where); -static int -pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val) -{ - switch (size) { - case 1: - return read_config_byte(bus, devfn, where, (u8 *) val); - case 2: - return read_config_word(bus, devfn, where, (u16 *) val); - default: - return read_config_dword(bus, devfn, where, val); - } -} + writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR); -static int -pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) -{ - switch (size) { - case 1: - return write_config_byte(bus, devfn, where, (u8) val); - case 2: - return write_config_word(bus, devfn, where, (u16) val); - default: - return write_config_dword(bus, devfn, where, val); - } + return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3); } -struct pci_ops mt7621_pci_ops= { - .read = pci_config_read, - .write = pci_config_write, -}; - -static struct resource mt7621_res_pci_mem1; -static struct resource mt7621_res_pci_io1; -static struct pci_controller mt7621_controller = { - .pci_ops = &mt7621_pci_ops, - .mem_resource = &mt7621_res_pci_mem1, - .io_resource = &mt7621_res_pci_io1, +struct pci_ops mt7621_pci_ops = { + .map_bus = mt7621_pcie_map_bus, + .read = pci_generic_config_read, + .write = pci_generic_config_write, }; -static void -read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val) +static u32 +read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) { - unsigned int address_reg, data_reg, address; - - address_reg = RALINK_PCI_CONFIG_ADDR; - data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG; - address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ; - MV_WRITE(address_reg, address); - MV_READ(data_reg, val); - return; -} + u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg); -static void -write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val) -{ - unsigned int address_reg, data_reg, address; - - address_reg = RALINK_PCI_CONFIG_ADDR; - data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG; - address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ; - MV_WRITE(address_reg, address); - MV_WRITE(data_reg, val); - return; + pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); + return pcie_read(pcie, RALINK_PCI_CONFIG_DATA); } -int -pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +static void +write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val) { - u16 cmd; - u32 val; - int irq; - - if (dev->bus->number == 0) { - write_config(0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE); - read_config(0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val); - printk("BAR0 at slot %d = %x\n", slot, val); - } + u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg); - pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14 - pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10 - pci_read_config_word(dev, PCI_COMMAND, &cmd); - cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; - pci_write_config_word(dev, PCI_COMMAND, cmd); - - irq = of_irq_parse_and_map_pci(dev, slot, pin); - - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); - return irq; + pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); + pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA); } void -set_pcie_phy(u32 *addr, int start_b, int bits, int val) +set_pcie_phy(struct mt7621_pcie *pcie, u32 offset, + int start_b, int bits, int val) { - *(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b); - *(unsigned int *)(addr) |= val << start_b; + u32 reg = pcie_read(pcie, offset); + + reg &= ~(((1 << bits) - 1) << start_b); + reg |= val << start_b; + pcie_write(pcie, reg, offset); } void -bypass_pipe_rst(void) +bypass_pipe_rst(struct mt7621_pcie *pcie) { /* PCIe Port 0 */ - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4] + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4] /* PCIe Port 1 */ - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01); // rg_pe1_pipe_rst_b - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4] + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01); // rg_pe1_pipe_rst_b + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4] /* PCIe Port 2 */ - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4] + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4] } void -set_phy_for_ssc(void) +set_phy_for_ssc(struct mt7621_pcie *pcie) { - unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10)); + unsigned long reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); reg = (reg >> 6) & 0x7; /* Set PCIe Port0 & Port1 PHY to disable SSC */ /* Debug Xtal Type */ - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable - if(reg <= 5 && reg >= 3) { // 40MHz Xtal - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode) + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable + if (reg <= 5 && reg >= 3) { // 40MHz Xtal + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode) printk("***** Xtal 40MHz *****\n"); } else { // 25MHz | 20MHz Xtal - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode) + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode) if (reg >= 6) { printk("***** Xtal 25MHz *****\n"); - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode) - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0, 31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode) + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0, 16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial } else { printk("***** Xtal 20MHz *****\n"); } } - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN - if(reg <= 5 && reg >= 3) { // 40MHz Xtal - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN + if (reg <= 5 && reg >= 3) { // 40MHz Xtal + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv } /* Enable PHY and disable force mode */ - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control + set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control /* Set PCIe Port2 PHY to disable SSC */ /* Debug Xtal Type */ - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable - if(reg <= 5 && reg >= 3) { // 40MHz Xtal - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode) + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable + if (reg <= 5 && reg >= 3) { // 40MHz Xtal + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode) } else { // 25MHz | 20MHz Xtal - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode) + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode) if (reg >= 6) { // 25MHz Xtal - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode) - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0, 31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode) + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0, 16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial } } - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN - if(reg <= 5 && reg >= 3) { // 40MHz Xtal - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN + if (reg <= 5 && reg >= 3) { // 40MHz Xtal + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv } /* Enable PHY and disable force mode */ - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable + set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control } -void setup_cm_memory_region(struct resource *mem_resource) +static void setup_cm_memory_region(struct resource *mem_resource) { resource_size_t mask; + if (mips_cps_numiocu(0)) { /* FIXME: hardware doesn't accept mask values with 1s after * 0s (e.g. 0xffef), so it would be great to warn if that's @@ -478,14 +338,142 @@ void setup_cm_memory_region(struct resource *mem_resource) } } +static int mt7621_pci_parse_request_of_pci_ranges(struct mt7621_pcie *pcie) +{ + struct device *dev = pcie->dev; + struct device_node *node = dev->of_node; + struct of_pci_range_parser parser; + struct of_pci_range range; + int err; + + if (of_pci_range_parser_init(&parser, node)) { + dev_err(dev, "missing \"ranges\" property\n"); + return -EINVAL; + } + + for_each_of_pci_range(&parser, &range) { + struct resource *res = NULL; + + switch (range.flags & IORESOURCE_TYPE_BITS) { + case IORESOURCE_IO: + ioremap(range.cpu_addr, range.size); + res = &pcie->io; + pcie->offset.io = 0x00000000UL; + break; + case IORESOURCE_MEM: + res = &pcie->mem; + pcie->offset.mem = 0x00000000UL; + break; + } + + if (res != NULL) + of_pci_range_to_resource(&range, node, res); + } + + err = of_pci_parse_bus_range(node, &pcie->busn); + if (err < 0) { + dev_err(dev, "failed to parse bus ranges property: %d\n", err); + pcie->busn.name = node->name; + pcie->busn.start = 0; + pcie->busn.end = 0xff; + pcie->busn.flags = IORESOURCE_BUS; + } + + return 0; +} + +static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie) +{ + struct device *dev = pcie->dev; + struct device_node *node = dev->of_node; + struct resource regs; + const char *type; + int err; + + type = of_get_property(node, "device_type", NULL); + if (!type || strcmp(type, "pci") != 0) { + dev_err(dev, "invalid \"device_type\" %s\n", type); + return -EINVAL; + } + + err = of_address_to_resource(node, 0, ®s); + if (err) { + dev_err(dev, "missing \"reg\" property\n"); + return err; + } + + pcie->base = devm_ioremap_resource(dev, ®s); + if (IS_ERR(pcie->base)) + return PTR_ERR(pcie->base); + + return 0; +} + +static int mt7621_pcie_request_resources(struct mt7621_pcie *pcie, + struct list_head *res) +{ + struct device *dev = pcie->dev; + int err; + + pci_add_resource_offset(res, &pcie->io, pcie->offset.io); + pci_add_resource_offset(res, &pcie->mem, pcie->offset.mem); + pci_add_resource(res, &pcie->busn); + + err = devm_request_pci_bus_resources(dev, res); + if (err < 0) + return err; + + return 0; +} + +static int mt7621_pcie_register_host(struct pci_host_bridge *host, + struct list_head *res) +{ + struct mt7621_pcie *pcie = pci_host_bridge_priv(host); + + list_splice_init(res, &host->windows); + host->busnr = pcie->busn.start; + host->dev.parent = pcie->dev; + host->ops = &mt7621_pci_ops; + host->map_irq = of_irq_parse_and_map_pci; + host->swizzle_irq = pci_common_swizzle; + host->sysdata = pcie; + + return pci_host_probe(host); +} + static int mt7621_pci_probe(struct platform_device *pdev) { - unsigned long val = 0; + struct device *dev = &pdev->dev; + struct mt7621_pcie *pcie; + struct pci_host_bridge *bridge; + int err; + u32 val = 0; + LIST_HEAD(res); + + if (!dev->of_node) + return -ENODEV; + + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); + if (!bridge) + return -ENODEV; + + pcie = pci_host_bridge_priv(bridge); + pcie->dev = dev; + platform_set_drvdata(pdev, pcie); + INIT_LIST_HEAD(&pcie->ports); + + err = mt7621_pcie_parse_dt(pcie); + if (err) { + dev_err(dev, "Parsing DT failed\n"); + return err; + } + /* set resources limits */ iomem_resource.start = 0; - iomem_resource.end= ~0; - ioport_resource.start= 0; - ioport_resource.end = ~0; + iomem_resource.end = ~0UL; /* no limit */ + ioport_resource.start = 0; + ioport_resource.end = ~0UL; /* no limit */ val = RALINK_PCIE0_RST; val |= RALINK_PCIE1_RST; @@ -509,62 +497,66 @@ static int mt7621_pci_probe(struct platform_device *pdev) DEASSERT_SYSRST_PCIE(val); if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2 - bypass_pipe_rst(); - set_phy_for_ssc(); + bypass_pipe_rst(pcie); + set_phy_for_ssc(pcie); - read_config(0, 0, 0, 0x70c, &val); + val = read_config(pcie, 0, 0x70c); printk("Port 0 N_FTS = %x\n", (unsigned int)val); - read_config(0, 1, 0, 0x70c, &val); + val = read_config(pcie, 1, 0x70c); printk("Port 1 N_FTS = %x\n", (unsigned int)val); - read_config(0, 2, 0, 0x70c, &val); + val = read_config(pcie, 2, 0x70c); printk("Port 2 N_FTS = %x\n", (unsigned int)val); - RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST); - RALINK_SYSCFG1 &= ~(0x30); - RALINK_SYSCFG1 |= (2<<4); - RALINK_PCIE_CLK_GEN &= 0x7fffffff; - RALINK_PCIE_CLK_GEN1 &= 0x80ffffff; - RALINK_PCIE_CLK_GEN1 |= 0xa << 24; - RALINK_PCIE_CLK_GEN |= 0x80000000; + rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL); + rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1); + + rt_sysc_m32(0x80000000, 0, RALINK_PCIE_CLK_GEN); + rt_sysc_m32(0x7f000000, 0xa << 24, RALINK_PCIE_CLK_GEN1); + rt_sysc_m32(0, 0x80000000, RALINK_PCIE_CLK_GEN); + mdelay(50); - RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST); + rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL); /* Use GPIO control instead of PERST_N */ *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // set DATA mdelay(1000); - if(( RALINK_PCI0_STATUS & 0x1) == 0) - { + if ((pcie_read(pcie, RT6855_PCIE0_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) { printk("PCIE0 no card, disable it(RST&CLK)\n"); ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST); - RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN); + rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1); pcie_link_status &= ~(1<<0); } else { pcie_link_status |= 1<<0; - RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt + val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR); + val |= (1<<20); // enable pcie1 interrupt + pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR); } - if(( RALINK_PCI1_STATUS & 0x1) == 0) - { + if ((pcie_read(pcie, RT6855_PCIE1_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) { printk("PCIE1 no card, disable it(RST&CLK)\n"); ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST); - RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN); + rt_sysc_m32(RALINK_PCIE1_CLK_EN, 0, RALINK_CLKCFG1); pcie_link_status &= ~(1<<1); } else { pcie_link_status |= 1<<1; - RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt + val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR); + val |= (1<<21); // enable pcie1 interrupt + pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR); } - if (( RALINK_PCI2_STATUS & 0x1) == 0) { + if ((pcie_read(pcie, RT6855_PCIE2_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) { printk("PCIE2 no card, disable it(RST&CLK)\n"); ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST); - RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE2_CLK_EN); + rt_sysc_m32(RALINK_PCIE2_CLK_EN, 0, RALINK_CLKCFG1); pcie_link_status &= ~(1<<2); } else { pcie_link_status |= 1<<2; - RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt + val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR); + val |= (1<<22); // enable pcie2 interrupt + pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR); } if (pcie_link_status == 0) @@ -581,29 +573,37 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num 3'b110 1 0 x 3'b111 2 1 0 */ - switch(pcie_link_status) { + switch (pcie_link_status) { case 2: - RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000; - RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0 - RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1 + val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); + val &= ~0x00ff0000; + val |= 0x1 << 16; // port 0 + val |= 0x0 << 20; // port 1 + pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); break; case 4: - RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000; - RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0 - RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1 - RALINK_PCI_PCICFG_ADDR |= 0x0 << 24; //port2 + val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); + val &= ~0x0fff0000; + val |= 0x1 << 16; //port0 + val |= 0x2 << 20; //port1 + val |= 0x0 << 24; //port2 + pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); break; case 5: - RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000; - RALINK_PCI_PCICFG_ADDR |= 0x0 << 16; //port0 - RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1 - RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2 + val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); + val &= ~0x0fff0000; + val |= 0x0 << 16; //port0 + val |= 0x2 << 20; //port1 + val |= 0x1 << 24; //port2 + pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); break; case 6: - RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000; - RALINK_PCI_PCICFG_ADDR |= 0x2 << 16; //port0 - RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1 - RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2 + val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); + val &= ~0x0fff0000; + val |= 0x2 << 16; //port0 + val |= 0x0 << 20; //port1 + val |= 0x1 << 24; //port2 + pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); break; } @@ -612,68 +612,91 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num ioport_resource.end = mt7621_res_pci_io1.end; */ - RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE; - RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE; + pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE); + pcie_write(pcie, RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE); //PCIe0 - if((pcie_link_status & 0x1) != 0) { - RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE - RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE; - RALINK_PCI0_CLASS = 0x06040001; + if ((pcie_link_status & 0x1) != 0) { + /* open 7FFF:2G; ENABLE */ + pcie_write(pcie, 0x7FFF0001, + RT6855_PCIE0_OFFSET + RALINK_PCI_BAR0SETUP_ADDR); + pcie_write(pcie, MEMORY_BASE, + RT6855_PCIE0_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR); + pcie_write(pcie, 0x06040001, + RT6855_PCIE0_OFFSET + RALINK_PCI_CLASS); printk("PCIE0 enabled\n"); } //PCIe1 if ((pcie_link_status & 0x2) != 0) { - RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE - RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE; - RALINK_PCI1_CLASS = 0x06040001; + /* open 7FFF:2G; ENABLE */ + pcie_write(pcie, 0x7FFF0001, + RT6855_PCIE1_OFFSET + RALINK_PCI_BAR0SETUP_ADDR); + pcie_write(pcie, MEMORY_BASE, + RT6855_PCIE1_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR); + pcie_write(pcie, 0x06040001, + RT6855_PCIE1_OFFSET + RALINK_PCI_CLASS); printk("PCIE1 enabled\n"); } //PCIe2 if ((pcie_link_status & 0x4) != 0) { - RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE - RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE; - RALINK_PCI2_CLASS = 0x06040001; + /* open 7FFF:2G; ENABLE */ + pcie_write(pcie, 0x7FFF0001, + RT6855_PCIE2_OFFSET + RALINK_PCI_BAR0SETUP_ADDR); + pcie_write(pcie, MEMORY_BASE, + RT6855_PCIE2_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR); + pcie_write(pcie, 0x06040001, + RT6855_PCIE2_OFFSET + RALINK_PCI_CLASS); printk("PCIE2 enabled\n"); } - switch(pcie_link_status) { + switch (pcie_link_status) { case 7: - read_config(0, 2, 0, 0x4, &val); - write_config(0, 2, 0, 0x4, val|0x4); - read_config(0, 2, 0, 0x70c, &val); + val = read_config(pcie, 2, 0x4); + write_config(pcie, 2, 0x4, val|0x4); + val = read_config(pcie, 2, 0x70c); val &= ~(0xff)<<8; val |= 0x50<<8; - write_config(0, 2, 0, 0x70c, val); + write_config(pcie, 2, 0x70c, val); case 3: case 5: case 6: - read_config(0, 1, 0, 0x4, &val); - write_config(0, 1, 0, 0x4, val|0x4); - read_config(0, 1, 0, 0x70c, &val); + val = read_config(pcie, 1, 0x4); + write_config(pcie, 1, 0x4, val|0x4); + val = read_config(pcie, 1, 0x70c); val &= ~(0xff)<<8; val |= 0x50<<8; - write_config(0, 1, 0, 0x70c, val); + write_config(pcie, 1, 0x70c, val); default: - read_config(0, 0, 0, 0x4, &val); - write_config(0, 0, 0, 0x4, val|0x4); //bus master enable - read_config(0, 0, 0, 0x70c, &val); + val = read_config(pcie, 0, 0x4); + write_config(pcie, 0, 0x4, val|0x4); //bus master enable + val = read_config(pcie, 0, 0x70c); val &= ~(0xff)<<8; val |= 0x50<<8; - write_config(0, 0, 0, 0x70c, val); + write_config(pcie, 0, 0x70c, val); } - pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node); - setup_cm_memory_region(mt7621_controller.mem_resource); - register_pci_controller(&mt7621_controller); - return 0; + err = mt7621_pci_parse_request_of_pci_ranges(pcie); + if (err) { + dev_err(dev, "Error requesting pci resources from ranges"); + return err; + } -} + setup_cm_memory_region(&pcie->mem); + + err = mt7621_pcie_request_resources(pcie, &res); + if (err) { + dev_err(dev, "Error requesting resources\n"); + return err; + } + + err = mt7621_pcie_register_host(bridge, &res); + if (err) { + dev_err(dev, "Error registering host\n"); + return err; + } -int pcibios_plat_dev_init(struct pci_dev *dev) -{ return 0; } |