diff options
Diffstat (limited to 'drivers/staging/otus/hal')
21 files changed, 26908 insertions, 0 deletions
diff --git a/drivers/staging/otus/hal/hpDKfwu.c b/drivers/staging/otus/hal/hpDKfwu.c new file mode 100644 index 000000000000..144c62dc8da2 --- /dev/null +++ b/drivers/staging/otus/hal/hpDKfwu.c @@ -0,0 +1,832 @@ +/* + * Copyright (c) 2007-2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include "../80211core/cprecomp.h" + +const u32_t zcDKFwImage[] = { +0x0009000B, 0x4F222FE6, 0xDE3E7FFC, 0xE114D73E, +0x1E13D43E, 0x1E4C470B, 0x0009B017, 0x956EE600, +0xC84060E2, 0x2F028F03, 0x8FF93652, 0xD4387601, +0x4E0BDE38, 0xD4380009, 0x00094E0B, 0x4E0BD437, +0x7F040009, 0xA0364F26, 0x4F226EF6, 0x410BD134, +0xD4340009, 0x0009440B, 0x450BD533, 0xD7330009, +0xD233E1FF, 0x2712611D, 0xD4325029, 0xE1FFCB01, +0x1209E501, 0x12112212, 0xD52F2452, 0xD22F9740, +0xE7002572, 0xD42FD12E, 0x2270D62F, 0x2172E201, +0x26202420, 0xE4FFD62D, 0xE6002641, 0xE104D52C, +0x6063666D, 0x626D7601, 0x32124000, 0x05458FF8, +0x000B4F26, 0xEAC80009, 0xDB266AAC, 0xDD27DC26, +0xD828DE27, 0x4C0BE901, 0x4D0B0009, 0x4E0B0009, +0x60B20009, 0x89078801, 0x6242D423, 0x890332A6, +0x6050D522, 0x8BEE8801, 0x2B92D41F, 0x26686642, +0x480B89E9, 0xD51D0009, 0xAFE4E200, 0x27102520, +0x00000FA0, 0x001C001C, 0x00200ED4, 0x0000B38E, +0x00202F90, 0x00201356, 0x00202F9C, 0x00202FB4, +0x00201314, 0x00201412, 0x00200EF8, 0x001C3510, +0x001C3624, 0x001E212C, 0x00202F00, 0x00202A9C, +0x00202F08, 0x00202F14, 0x00202F20, 0x00202F22, +0x00202F26, 0x001C1028, 0x00201220, 0x0020294C, +0x00201D10, 0x00201EC8, 0x00203220, 0x00202F24, +0x2FB62F96, 0x2FD62FC6, 0x4F222FE6, 0xDE947F80, +0x61E0E024, 0x0F14D493, 0x710161E3, 0xD7926210, +0x470BE028, 0xD5910F24, 0x0009450B, 0x6D032008, +0x1F0B8F11, 0xD48FDC8E, 0xDD8F67C0, 0x657C4D0B, +0xDD8FD18E, 0x6B9C6910, 0x420862B3, 0x32B84208, +0x3D2C4208, 0xE0281FDB, 0xE58004FC, 0x604C66E2, +0x3050655C, 0x2D628F13, 0x01FCE024, 0x641CE500, +0x625DDE84, 0x8B013243, 0x0009A39E, 0x6753655D, +0x607037EC, 0x39DC6953, 0xAFF27501, 0x20088094, +0xE0248B13, 0xE50001FC, 0xA009DE7A, 0x655D641C, +0x32EC6253, 0x6C536B22, 0x3CDC67B2, 0x75041C71, +0x3243625D, 0xA37F8BF3, 0x88012D10, 0xE0248B16, +0xE40001FC, 0x671C2D40, 0x624DDE6E, 0x8B013273, +0x0009A372, 0x6CE3644D, 0x7C046943, 0x39EC6B43, +0x65923BCC, 0x74086DB2, 0x25D2AFEF, 0x8B198804, +0x01FCE024, 0x2D70E700, 0x1FD86D1C, 0x627DDE61, +0x8B0132D3, 0x0009A358, 0x6B73677D, 0x3BEC61E3, +0x710464B2, 0x3C1C6C73, 0x694265C2, 0x29597708, +0x2492AFED, 0x8B188805, 0x01FCE024, 0x2D40E400, +0xDE54671C, 0x3273624D, 0xA33D8B01, 0x644D0009, +0x6BE36D43, 0x65D23DEC, 0x61437B04, 0x6C1231BC, +0x74086952, 0xAFED29CB, 0x88312592, 0xDE4A8B20, +0x65E6DB4A, 0x61E6DC4A, 0x67E2D94A, 0x62E27E04, +0x1FEC7EE8, 0x7E0464E2, 0x6EE21FED, 0x5BFD2BE0, +0x60B27B04, 0xC9011FBE, 0x6BB22C00, 0x29B04B09, +0xDC412F26, 0x66134C0B, 0xE2007F04, 0x2D20A30C, +0x8B218830, 0xD939DE38, 0xE06465E6, 0x720462E3, +0x672666E2, 0x6E23DC36, 0x62227EE8, 0x6BE261E6, +0x29B01FEF, 0x7E040F16, 0xC90160E2, 0x6EE22C00, +0x4E09DC30, 0x2F262CE0, 0xD130E068, 0x04FE410B, +0xE2007F04, 0x2D20A2E8, 0x8B058833, 0x4E0BDE2C, +0xE1000009, 0x2D10A2E0, 0x89018828, 0x0009A106, +0xE143DE20, 0xE04062E1, 0x3217622D, 0x0FE68F04, +0x6023E240, 0x262106FE, 0x8B013217, 0x0009A0EF, +0x02FEE040, 0x8521E401, 0x8B013046, 0x0009A0E7, +0xE501E040, 0x2D5007FE, 0x6471B2C7, 0x09FEE040, +0x6291E143, 0x652DE068, 0x8D6B3517, 0xE6400F56, +0x8B273563, 0xE048E600, 0xE11A0F65, 0x72C0A031, +0x00117800, 0x00202FB8, 0x00201356, 0x00202480, +0x00202F1A, 0x00202FBC, 0x002013A2, 0x00202F19, +0x00202B40, 0x00117804, 0x00117810, 0x00202F15, +0x00202F16, 0x00202F17, 0x00200B84, 0x00200BD8, +0x00200BD4, 0x41216153, 0x41214121, 0x41214121, +0x45214521, 0x60534521, 0x6603C903, 0x0F65E048, +0xE0077118, 0xE0442209, 0x641D0F25, 0x65F3E04C, +0x0F46B314, 0x04FDE048, 0x0BFDE044, 0x61BD674D, +0x41084708, 0x0F16E050, 0xD2936073, 0x420B09FE, +0x6C07E00F, 0x607329C9, 0xE0400F96, 0x65F30EFE, +0x6D0D85E2, 0x01FEE050, 0x60D3420B, 0x6073290B, +0xE04C0F96, 0x04FEB2D9, 0x06FEE040, 0x6261E068, +0x0F56652D, 0x3563E640, 0xE000894E, 0x602381F8, +0x4008C903, 0x6B034000, 0xE0546103, 0xE0580FB6, +0xECFFDD7D, 0x6CCC0FF6, 0x0FD6E06C, 0x4D0B60C3, +0x42216253, 0x42214221, 0x64234221, 0x324C4200, +0xE05C6E07, 0x45214200, 0xE0400FE6, 0x0BFE4521, +0xC9036053, 0x30FC4008, 0x6D037B06, 0x85F81F05, +0x6C2D1FB7, 0x1FC66E03, 0x0FC6E060, 0x05FEE058, +0x64C3B2B4, 0x33FCE354, 0x563262D2, 0x22696132, +0x67B42D22, 0x490B5936, 0x220B607C, 0x05FEE058, +0x64C32D22, 0x7E01B289, 0xE70662ED, 0x8FE33273, +0xE0407C01, 0x626106FE, 0x06FEE040, 0x85614200, +0x302C760C, 0x6103701B, 0x64F3E500, 0x7501E704, +0x6B5D6966, 0x24923B73, 0x74048FF9, 0xB26C65F3, +0xE040641D, 0xB20506FE, 0xA1DD6461, 0xD44F0009, +0xE201D74F, 0x2D20470B, 0x0009A1D6, 0x8B078829, +0xEC00DE4C, 0x61E22DC0, 0x641DB1D7, 0x0009A1CC, +0x622CE281, 0x8B013020, 0x0009A118, 0x06FCE028, +0xE682626C, 0x3260666C, 0xA0EE8B01, 0xE6830009, +0x3260666C, 0xA0DC8B01, 0xE6900009, 0x3260666C, +0xA0D08B01, 0xE6910009, 0x3260666C, 0xA0B98B01, +0xE6B00009, 0x3260666C, 0xA07F8B01, 0xE6BB0009, +0x3260666C, 0xE6928920, 0x3260666C, 0xE4008B14, +0xEB04D531, 0x52516652, 0x8B073620, 0x624D7401, +0x8FF732B7, 0xE6007508, 0x52FBA002, 0xE60152FB, +0xE6041261, 0x2260A188, 0xD229D428, 0xD4296542, +0x0009420B, 0x0009A180, 0xE100E670, 0x601336FC, +0xE0248162, 0x0BFCD21F, 0x6BBC6722, 0x26727BFC, +0xEB0416B2, 0x06FEE078, 0x3263621D, 0xA16B8B01, +0xDE1D0009, 0x31EC611D, 0xD41C6E12, 0x410BD114, +0xE0700009, 0x450BD51A, 0xD41A04FE, 0x420BD210, +0xD2170009, 0x64E3420B, 0xD60DD417, 0x0009460B, +0x05FEE070, 0x01FDE074, 0x611DE600, 0x6253351C, +0x326C666D, 0x22E07601, 0x32B3626D, 0x4E198FF7, +0xE0747104, 0x0F15AFCE, 0x002029F8, 0x00202FDC, +0x00201356, 0x00117804, 0x00202B10, 0x00117800, +0x002013A2, 0x00203014, 0x00117808, 0x00202FF4, +0x0020139A, 0x00203008, 0x00203010, 0x02FCE024, +0x672CE07C, 0xEC000F76, 0xE07CEB04, 0x62CD07FE, +0x8B013273, 0x0009A118, 0x6CCDD7B9, 0x357C65C3, +0x62C37704, 0xD4B7327C, 0x6D52D7B7, 0x6E22470B, +0x470BD7B6, 0xD4B664D3, 0x420BD2B3, 0xD2B30009, +0x64E3420B, 0xD6B0D4B3, 0x0009460B, 0x67D3E600, +0x376C666D, 0x626D7601, 0x27E032B3, 0x4E198FF7, +0x7C08AFD3, 0x6212D1A6, 0x2228622C, 0xD2AA8B04, +0x0009420B, 0x0009A003, 0x420BD2A8, 0x56FB0009, +0xA0E1E200, 0xB1A62620, 0x56FB0009, 0xA0DBE200, +0x52FB2620, 0xE500D69A, 0x65622250, 0x7604D2A0, +0x62622252, 0xA0CFD69F, 0x56FB2620, 0x2610E124, +0x5217D19D, 0x52181621, 0x52191622, 0x521A1623, +0x551B1624, 0x1655E200, 0x1656551C, 0x1657551D, +0x1658551E, 0x1659551F, 0x11281127, 0x112A1129, +0x112C112B, 0x112E112D, 0x112FA0AE, 0xD68FD18E, +0x6262E040, 0x76046512, 0x2152352C, 0x55116266, +0x1151352C, 0x62626563, 0x75085612, 0x1162362C, +0x56136252, 0x362C75EC, 0x62521163, 0x75105614, +0x1164362C, 0x62526653, 0x76105515, 0x1155352C, +0x56166262, 0x362CD57E, 0x62561166, 0x362C5617, +0x66531167, 0x55186252, 0x352C7604, 0x62661158, +0x352C5519, 0x65631159, 0x561A6262, 0x362C7504, +0x6252116A, 0x7504561B, 0x116B362C, 0x561C6256, +0x116C362C, 0x561D6256, 0x116D362C, 0x62526653, +0x7604551E, 0x115E352C, 0x561F6262, 0x362CD569, +0x6252116F, 0x7594061E, 0x0166362C, 0x6653E044, +0x051E6252, 0x352C7644, 0xE0480156, 0x061E6262, +0x0166362C, 0xE054D660, 0x051E6262, 0x352C4229, +0x76040156, 0xE0586262, 0x4229061E, 0x0166362C, +0xE23856FB, 0xE0442620, 0xE048021E, 0x62121621, +0x55111622, 0x1653E200, 0x16545512, 0x16555515, +0x16565513, 0x16575516, 0xE040051E, 0x051E1658, +0x1659E050, 0x165A5514, 0xE04C051E, 0x051E165B, +0x165CE054, 0xE058051E, 0x051E165D, 0x165EE044, +0xE0480126, 0x11212122, 0x11251122, 0x11261123, +0xE0400126, 0xE0500126, 0x01261124, 0x0126E04C, +0x0126E054, 0x0126E058, 0x3F3C9358, 0x6EF64F26, +0x6CF66DF6, 0x000B6BF6, 0x4F2269F6, 0xE240614D, +0x89143123, 0x3127E21F, 0x8B09D734, 0xD434614D, +0xE00171E0, 0x5671440B, 0x26596507, 0x1761A007, +0xE001D42F, 0x6672440B, 0x26596507, 0x4F262762, +0x0009000B, 0x614D4F22, 0x3123E240, 0xE21F8912, +0xD7263127, 0x614D8B08, 0x5671D225, 0x420B71E0, +0x260BE001, 0x1761A006, 0x6672D221, 0xE001420B, +0x2762260B, 0x000B4F26, 0xE6400009, 0x46284618, +0x6252D51C, 0x89FC2268, 0x0009000B, 0x4618E680, +0xD5184628, 0x22686252, 0x000B89FC, 0xA0010009, +0x7201E200, 0x8BFC3242, 0x0009000B, 0x00000080, +0x00117804, 0x00202FF4, 0x00201356, 0x0020139A, +0x00203008, 0x00203010, 0x00200C38, 0x00200C12, +0x00202F00, 0x00202F14, 0x00202AA4, 0x001C36A0, +0x001C3CA0, 0x001C36F4, 0x001C3B88, 0x001C3704, +0x002029F8, 0x001C373C, 0x4618E680, 0xD52F4628, +0x22686252, 0x000B8BFC, 0x2FE60009, 0x7FFC4F22, +0xBFF16E53, 0x61E22F42, 0xE280D629, 0x54E11615, +0x16464218, 0x422855E2, 0x57E31657, 0x16786EF2, +0x26E22E2B, 0x4F267F04, 0x6EF6AFA8, 0x2FD62FC6, +0x4F222FE6, 0x6C53DD1E, 0x6E43BFD6, 0x2DE2BF95, +0x0009BFD2, 0x2C1251D5, 0x1C4154D6, 0x1C5255D7, +0x1C6356D8, 0x6EF64F26, 0x000B6DF6, 0x61636CF6, +0xA004E600, 0x62564109, 0x24227601, 0x36127404, +0x000B8BF9, 0x4F220009, 0xD10FD40E, 0x0009410B, +0xD40FD20E, 0xE5056022, 0x2202CB20, 0xD50D2452, +0x450BE700, 0xD70C2472, 0x0009470B, 0xE601D10B, +0x2162D20B, 0x4F264618, 0x2262000B, 0x001C3700, +0x001C370C, 0x00203028, 0x00201356, 0x001C3500, +0x001D4004, 0x002013CC, 0x00200EF8, 0x001E212C, +0x001C3D30, 0x0009A1A9, 0x2FE62FD6, 0xDD8F4F22, +0xA0049EA7, 0xD48E0009, 0x420BD28E, 0x62D265D2, +0x8BF822E8, 0x0009A004, 0xD28AD48B, 0x55D1420B, +0x22E852D1, 0xA0048BF8, 0xD4880009, 0x420BD285, +0x52D255D2, 0x8BF822E8, 0x0009A004, 0xD281D484, +0x55D3420B, 0x22E852D3, 0xA0048BF8, 0xD4810009, +0x420BD27C, 0x52D455D4, 0x8BF822E8, 0x6EF64F26, +0x6DF6000B, 0x2FD62FC6, 0x4F222FE6, 0x6E636D73, +0x6C53B018, 0x64C357F4, 0xB05465E3, 0xB06A66D3, +0xB09A0009, 0xB09E0009, 0xB0A20009, 0xB0BE0009, +0xB0C10009, 0xB1240009, 0x4F260009, 0x6DF66EF6, +0x6CF6A023, 0x3412D16C, 0xD66C0529, 0x2650D76C, +0x2742000B, 0x0009A014, 0x2FD62FC6, 0x4F222FE6, +0x6E636D73, 0x6C53BFEE, 0x64C357F4, 0xB02A65E3, +0xB10666D3, 0x4F260009, 0x6DF66EF6, 0x6CF6A005, +0xE603D260, 0x000B4618, 0xD25E2262, 0x000BE600, +0x4F222262, 0xE40ABF7E, 0x0009BF7E, 0xE104D25A, +0xE5004118, 0x2212E40A, 0x2252BF74, 0x6072D757, +0x4F26CB20, 0x2702000B, 0xD1554F22, 0xE400410B, +0x452BD554, 0x2FE64F26, 0x6E63D153, 0x44186612, +0x45289210, 0x26294408, 0x44084500, 0x4400265B, +0x4708264B, 0x47082162, 0x27EBD14C, 0x000B2172, +0x03F06EF6, 0x2FE61FFF, 0xDE494F22, 0xE40AE101, +0x2E12BF48, 0x726C62E3, 0xE401E100, 0x22122212, +0x22122212, 0x22122212, 0xE7302242, 0xE40AE503, +0x22122212, 0x22122212, 0x22122212, 0x22122212, +0x22122212, 0x22122212, 0x22522272, 0x22122212, +0x22122212, 0x22122212, 0x22122212, 0x121ABF22, +0x2E62E600, 0x000B4F26, 0xD2326EF6, 0xE441E101, +0x000B2212, 0xD1302242, 0xE605D430, 0x000B2162, +0xD52F2462, 0x6050D22F, 0x8B0E8801, 0x6040D42E, +0x8B078801, 0x9626D52D, 0x88016050, 0x96238B0C, +0x0009A00A, 0xA0079621, 0xE6000009, 0x2262D426, +0x88016040, 0xE6048B00, 0xAEF3E40A, 0xD2242262, +0xE40AE601, 0x2262AEEE, 0x2FC62FB6, 0x2FE62FD6, +0xDC204F22, 0x60C2ED00, 0xCB01EB64, 0x60C22C02, +0xA041C901, 0x03C46E03, 0x034003D4, 0x001C3B88, +0x0020302C, 0x002013A2, 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0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x544F0D0A, 0x46205355, 0x00003A57, 0x20636544, +0x32203231, 0x20373030, 0x333A3132, 0x34323A36, +0x00000000, 0x00000D0A, 0x00000043, 0x42707372, +0x3D206675, 0x554E203D, 0x202C4C4C, 0x6E49677A, +0x4E497274, 0x6D754E51, 0x0000003D, 0x61766E49, +0x2064696C, 0x72657375, 0x20726F20, 0x2079656B, +0x00214449, 0x52504545, 0x57204D4F, 0x65746972, +0x6461202C, 0x003D7264, 0x6C617620, 0x0000003D, +0x00000A0D, 0x6E6B6E55, 0x206E776F, 0x6D6D6F63, +0x3D646E61, 0x00000000, 0x000A0D52, 0x203A3051, +0x00000020, 0x203A3151, 0x00000020, 0x203A3251, +0x00000020, 0x203A3351, 0x00000020, 0x203A3451, +0x00000020, 0x61437748, 0x7262696C, 0x6F697461, +0x6620206E, 0x0A6C6961, 0x0000000D, 0x73696F4E, +0x61432065, 0x7262696C, 0x6F697461, 0x6166206E, +0x21216C69, 0x00000D0A, 0x00000072, 0x00205220, +0x00000D0A, 0x62735576, 0x7473725F, 0x00000A0D, +0x62735576, 0x7375735F, 0x646E6570, 0x00000A0D, +0x62735576, 0x7365725F, 0x000A0D6D, 0x00000042, +0x72746E49, 0x6D652051, 0x2C797470, 0x49677A20, +0x4972746E, 0x754E514E, 0x00003D6D, 0x654C7245, +0x0000006E, 0x00000049, 0x20746F4E, 0x756F6E65, +0x49206867, 0x4220514E, 0x0A0D6675, 0x00000000, +0x000000FF, 0x00020001, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x010E010D, 0x00020003, 0x01090108, 0x0002010A, +0x02000003, 0x02020201, 0x02040203, 0x02060205, +0x02020200, 0x02040203, 0x020C0207, 0x020E020D, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x010E010D, 0x00FF010F, 0x01090108, 0x010B010A, +0x020000FF, 0x02020201, 0x02040203, 0x02060205, +0x02020200, 0x02040203, 0x020C020B, 0x020E020D, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00205220, 0x00000046, 0x00000059, 0x73204142, +0x003D7165, 0x49544120, 0x0000204D, 0x00000000, +0x00000000, 0x002E0209, 0x80000101, 0x000409FA, +0x00FF0400, 0x05070000, 0x02000201, 0x82050700, +0x00020002, 0x03830507, 0x07010040, 0x40020405, +0x02090000, 0x0101002E, 0x09FA8000, 0x04000004, +0x000000FF, 0x02010507, 0x07000040, 0x40028205, +0x05070000, 0x00400383, 0x04050701, 0x00004002, +0x00000000, 0x00000000, 0x07090000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, }; + +const u32_t zcDKFwImageSize=12988; diff --git a/drivers/staging/otus/hal/hpani.c b/drivers/staging/otus/hal/hpani.c new file mode 100644 index 000000000000..ba95b5d012a4 --- /dev/null +++ b/drivers/staging/otus/hal/hpani.c @@ -0,0 +1,732 @@ +/* + * Copyright (c) 2007-2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include "../80211core/cprecomp.h" +#include "hpani.h" +#include "hpusb.h" + + +extern u16_t zfDelayWriteInternalReg(zdev_t* dev, u32_t addr, u32_t val); +extern u16_t zfFlushDelayWrite(zdev_t* dev); + +/* + * Anti noise immunity support. We track phy errors and react + * to excessive errors by adjusting the noise immunity parameters. + */ + +/****************************************************************************** + * + * New Ani Algorithm for Station side only + * + *****************************************************************************/ + +#define ZM_HAL_NOISE_IMMUNE_MAX 4 /* Max noise immunity level */ +#define ZM_HAL_SPUR_IMMUNE_MAX 7 /* Max spur immunity level */ +#define ZM_HAL_FIRST_STEP_MAX 2 /* Max first step level */ + +#define ZM_HAL_ANI_OFDM_TRIG_HIGH 500 +#define ZM_HAL_ANI_OFDM_TRIG_LOW 200 +#define ZM_HAL_ANI_CCK_TRIG_HIGH 200 +#define ZM_HAL_ANI_CCK_TRIG_LOW 100 +#define ZM_HAL_ANI_NOISE_IMMUNE_LVL 4 +#define ZM_HAL_ANI_USE_OFDM_WEAK_SIG TRUE +#define ZM_HAL_ANI_CCK_WEAK_SIG_THR FALSE +#define ZM_HAL_ANI_SPUR_IMMUNE_LVL 7 +#define ZM_HAL_ANI_FIRSTEP_LVL 0 +#define ZM_HAL_ANI_RSSI_THR_HIGH 40 +#define ZM_HAL_ANI_RSSI_THR_LOW 7 +#define ZM_HAL_ANI_PERIOD 100 + +#define ZM_HAL_EP_RND(x, mul) \ + ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) + +s32_t BEACON_RSSI(zdev_t* dev) +{ + s32_t rssi; + + zmw_get_wlan_dev(dev); + + struct zsHpPriv *HpPriv = (struct zsHpPriv*)wd->hpPrivate; + + rssi = ZM_HAL_EP_RND(HpPriv->stats.ast_nodestats.ns_avgbrssi, ZM_HAL_RSSI_EP_MULTIPLIER); + + return rssi; +} + +/* + * Setup ANI handling. Sets all thresholds and levels to default level AND + * resets the channel statistics + */ + +void zfHpAniAttach(zdev_t* dev) +{ +#define N(a) (sizeof(a) / sizeof(a[0])) + u32_t i; + + zmw_get_wlan_dev(dev); + + struct zsHpPriv *HpPriv = (struct zsHpPriv*)wd->hpPrivate; + + const int totalSizeDesired[] = { -55, -55, -55, -55, -62 }; + const int coarseHigh[] = { -14, -14, -14, -14, -12 }; + const int coarseLow[] = { -64, -64, -64, -64, -70 }; + const int firpwr[] = { -78, -78, -78, -78, -80 }; + + for (i = 0; i < 5; i++) + { + HpPriv->totalSizeDesired[i] = totalSizeDesired[i]; + HpPriv->coarseHigh[i] = coarseHigh[i]; + HpPriv->coarseLow[i] = coarseLow[i]; + HpPriv->firpwr[i] = firpwr[i]; + } + + /* owl has phy counters */ + HpPriv->hasHwPhyCounters = 1; + + memset((char *)&HpPriv->ani, 0, sizeof(HpPriv->ani)); + for (i = 0; i < N(wd->regulationTable.allowChannel); i++) + { + /* New ANI stuff */ + HpPriv->ani[i].ofdmTrigHigh = ZM_HAL_ANI_OFDM_TRIG_HIGH; + HpPriv->ani[i].ofdmTrigLow = ZM_HAL_ANI_OFDM_TRIG_LOW; + HpPriv->ani[i].cckTrigHigh = ZM_HAL_ANI_CCK_TRIG_HIGH; + HpPriv->ani[i].cckTrigLow = ZM_HAL_ANI_CCK_TRIG_LOW; + HpPriv->ani[i].rssiThrHigh = ZM_HAL_ANI_RSSI_THR_HIGH; + HpPriv->ani[i].rssiThrLow = ZM_HAL_ANI_RSSI_THR_LOW; + HpPriv->ani[i].ofdmWeakSigDetectOff = !ZM_HAL_ANI_USE_OFDM_WEAK_SIG; + HpPriv->ani[i].cckWeakSigThreshold = ZM_HAL_ANI_CCK_WEAK_SIG_THR; + HpPriv->ani[i].spurImmunityLevel = ZM_HAL_ANI_SPUR_IMMUNE_LVL; + HpPriv->ani[i].firstepLevel = ZM_HAL_ANI_FIRSTEP_LVL; + if (HpPriv->hasHwPhyCounters) + { + HpPriv->ani[i].ofdmPhyErrBase = 0;//AR_PHY_COUNTMAX - ZM_HAL_ANI_OFDM_TRIG_HIGH; + HpPriv->ani[i].cckPhyErrBase = 0;//AR_PHY_COUNTMAX - ZM_HAL_ANI_CCK_TRIG_HIGH; + } + } + if (HpPriv->hasHwPhyCounters) + { + //zm_debug_msg2("Setting OfdmErrBase = 0x", HpPriv->ani[0].ofdmPhyErrBase); + //zm_debug_msg2("Setting cckErrBase = 0x", HpPriv->ani[0].cckPhyErrBase); + //OS_REG_WRITE(ah, AR_PHY_ERR_1, HpPriv->ani[0].ofdmPhyErrBase); + //OS_REG_WRITE(ah, AR_PHY_ERR_2, HpPriv->ani[0].cckPhyErrBase); + } + HpPriv->aniPeriod = ZM_HAL_ANI_PERIOD; + //if (ath_hal_enableANI) + HpPriv->procPhyErr |= ZM_HAL_PROCESS_ANI; + + HpPriv->stats.ast_nodestats.ns_avgbrssi = ZM_RSSI_DUMMY_MARKER; + HpPriv->stats.ast_nodestats.ns_avgrssi = ZM_RSSI_DUMMY_MARKER; + HpPriv->stats.ast_nodestats.ns_avgtxrssi = ZM_RSSI_DUMMY_MARKER; +#undef N +} + +/* + * Control Adaptive Noise Immunity Parameters + */ +u8_t zfHpAniControl(zdev_t* dev, ZM_HAL_ANI_CMD cmd, int param) +{ +#define N(a) (sizeof(a)/sizeof(a[0])) + typedef s32_t TABLE[]; + + zmw_get_wlan_dev(dev); + + struct zsHpPriv *HpPriv = (struct zsHpPriv*)wd->hpPrivate; + + struct zsAniState *aniState = HpPriv->curani; + + switch (cmd) + { + case ZM_HAL_ANI_NOISE_IMMUNITY_LEVEL: + { + u32_t level = param; + + if (level >= N(HpPriv->totalSizeDesired)) + { + zm_debug_msg1("level out of range, desired level : ", level); + zm_debug_msg1("max level : ", N(HpPriv->totalSizeDesired)); + return FALSE; + } + + zfDelayWriteInternalReg(dev, AR_PHY_DESIRED_SZ, + (HpPriv->regPHYDesiredSZ & ~AR_PHY_DESIRED_SZ_TOT_DES) + | ((HpPriv->totalSizeDesired[level] << AR_PHY_DESIRED_SZ_TOT_DES_S) + & AR_PHY_DESIRED_SZ_TOT_DES)); + zfDelayWriteInternalReg(dev, AR_PHY_AGC_CTL1, + (HpPriv->regPHYAgcCtl1 & ~AR_PHY_AGC_CTL1_COARSE_LOW) + | ((HpPriv->coarseLow[level] << AR_PHY_AGC_CTL1_COARSE_LOW_S) + & AR_PHY_AGC_CTL1_COARSE_LOW)); + zfDelayWriteInternalReg(dev, AR_PHY_AGC_CTL1, + (HpPriv->regPHYAgcCtl1 & ~AR_PHY_AGC_CTL1_COARSE_HIGH) + | ((HpPriv->coarseHigh[level] << AR_PHY_AGC_CTL1_COARSE_HIGH_S) + & AR_PHY_AGC_CTL1_COARSE_HIGH)); + zfDelayWriteInternalReg(dev, AR_PHY_FIND_SIG, + (HpPriv->regPHYFindSig & ~AR_PHY_FIND_SIG_FIRPWR) + | ((HpPriv->firpwr[level] << AR_PHY_FIND_SIG_FIRPWR_S) + & AR_PHY_FIND_SIG_FIRPWR)); + zfFlushDelayWrite(dev); + + if (level > aniState->noiseImmunityLevel) + HpPriv->stats.ast_ani_niup++; + else if (level < aniState->noiseImmunityLevel) + HpPriv->stats.ast_ani_nidown++; + aniState->noiseImmunityLevel = (u8_t)level; + break; + } + case ZM_HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION: + { + const TABLE m1ThreshLow = { 127, 50 }; + const TABLE m2ThreshLow = { 127, 40 }; + const TABLE m1Thresh = { 127, 0x4d }; + const TABLE m2Thresh = { 127, 0x40 }; + const TABLE m2CountThr = { 31, 16 }; + const TABLE m2CountThrLow = { 63, 48 }; + u32_t on = param ? 1 : 0; + + zfDelayWriteInternalReg(dev, AR_PHY_SFCORR_LOW, + (HpPriv->regPHYSfcorrLow & ~AR_PHY_SFCORR_LOW_M1_THRESH_LOW) + | ((m1ThreshLow[on] << AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S) + & AR_PHY_SFCORR_LOW_M1_THRESH_LOW)); + zfDelayWriteInternalReg(dev, AR_PHY_SFCORR_LOW, + (HpPriv->regPHYSfcorrLow & ~AR_PHY_SFCORR_LOW_M2_THRESH_LOW) + | ((m2ThreshLow[on] << AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S) + & AR_PHY_SFCORR_LOW_M2_THRESH_LOW)); + zfDelayWriteInternalReg(dev, AR_PHY_SFCORR, + (HpPriv->regPHYSfcorr & ~AR_PHY_SFCORR_M1_THRESH) + | ((m1Thresh[on] << AR_PHY_SFCORR_M1_THRESH_S) + & AR_PHY_SFCORR_M1_THRESH)); + zfDelayWriteInternalReg(dev, AR_PHY_SFCORR, + (HpPriv->regPHYSfcorr & ~AR_PHY_SFCORR_M2_THRESH) + | ((m2Thresh[on] << AR_PHY_SFCORR_M2_THRESH_S) + & AR_PHY_SFCORR_M2_THRESH)); + zfDelayWriteInternalReg(dev, AR_PHY_SFCORR, + (HpPriv->regPHYSfcorr & ~AR_PHY_SFCORR_M2COUNT_THR) + | ((m2CountThr[on] << AR_PHY_SFCORR_M2COUNT_THR_S) + & AR_PHY_SFCORR_M2COUNT_THR)); + zfDelayWriteInternalReg(dev, AR_PHY_SFCORR_LOW, + (HpPriv->regPHYSfcorrLow & ~AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW) + | ((m2CountThrLow[on] << AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S) + & AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW)); + + if (on) + { + zfDelayWriteInternalReg(dev, AR_PHY_SFCORR_LOW, + HpPriv->regPHYSfcorrLow | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); + } + else + { + zfDelayWriteInternalReg(dev, AR_PHY_SFCORR_LOW, + HpPriv->regPHYSfcorrLow & ~AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); + } + zfFlushDelayWrite(dev); + if (!on != aniState->ofdmWeakSigDetectOff) + { + if (on) + HpPriv->stats.ast_ani_ofdmon++; + else + HpPriv->stats.ast_ani_ofdmoff++; + aniState->ofdmWeakSigDetectOff = !on; + } + break; + } + case ZM_HAL_ANI_CCK_WEAK_SIGNAL_THR: + { + const TABLE weakSigThrCck = { 8, 6 }; + u32_t high = param ? 1 : 0; + + zfDelayWriteInternalReg(dev, AR_PHY_CCK_DETECT, + (HpPriv->regPHYCckDetect & ~AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK) + | ((weakSigThrCck[high] << AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S) + & AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK)); + zfFlushDelayWrite(dev); + if (high != aniState->cckWeakSigThreshold) + { + if (high) + HpPriv->stats.ast_ani_cckhigh++; + else + HpPriv->stats.ast_ani_ccklow++; + aniState->cckWeakSigThreshold = (u8_t)high; + } + break; + } + case ZM_HAL_ANI_FIRSTEP_LEVEL: + { + const TABLE firstep = { 0, 4, 8 }; + u32_t level = param; + + if (level >= N(firstep)) + { + zm_debug_msg1("level out of range, desired level : ", level); + zm_debug_msg1("max level : ", N(firstep)); + return FALSE; + } + zfDelayWriteInternalReg(dev, AR_PHY_FIND_SIG, + (HpPriv->regPHYFindSig & ~AR_PHY_FIND_SIG_FIRSTEP) + | ((firstep[level] << AR_PHY_FIND_SIG_FIRSTEP_S) + & AR_PHY_FIND_SIG_FIRSTEP)); + zfFlushDelayWrite(dev); + if (level > aniState->firstepLevel) + HpPriv->stats.ast_ani_stepup++; + else if (level < aniState->firstepLevel) + HpPriv->stats.ast_ani_stepdown++; + aniState->firstepLevel = (u8_t)level; + break; + } + case ZM_HAL_ANI_SPUR_IMMUNITY_LEVEL: + { + const TABLE cycpwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }; + u32_t level = param; + + if (level >= N(cycpwrThr1)) + { + zm_debug_msg1("level out of range, desired level : ", level); + zm_debug_msg1("max level : ", N(cycpwrThr1)); + return FALSE; + } + zfDelayWriteInternalReg(dev, AR_PHY_TIMING5, + (HpPriv->regPHYTiming5 & ~AR_PHY_TIMING5_CYCPWR_THR1) + | ((cycpwrThr1[level] << AR_PHY_TIMING5_CYCPWR_THR1_S) + & AR_PHY_TIMING5_CYCPWR_THR1)); + zfFlushDelayWrite(dev); + if (level > aniState->spurImmunityLevel) + HpPriv->stats.ast_ani_spurup++; + else if (level < aniState->spurImmunityLevel) + HpPriv->stats.ast_ani_spurdown++; + aniState->spurImmunityLevel = (u8_t)level; + break; + } + case ZM_HAL_ANI_PRESENT: + break; +#ifdef AH_PRIVATE_DIAG + case ZM_HAL_ANI_MODE: + if (param == 0) + { + HpPriv->procPhyErr &= ~ZM_HAL_PROCESS_ANI; + /* Turn off HW counters if we have them */ + zfHpAniDetach(dev); + //zfHpSetRxFilter(dev, zfHpGetRxFilter(dev) &~ HAL_RX_FILTER_PHYERR); + } + else + { /* normal/auto mode */ + HpPriv->procPhyErr |= ZM_HAL_PROCESS_ANI; + if (HpPriv->hasHwPhyCounters) + { + //zfHpSetRxFilter(dev, zfHpGetRxFilter(dev) &~ HAL_RX_FILTER_PHYERR); + } + else + { + //zfHpSetRxFilter(dev, zfHpGetRxFilter(dev) | HAL_RX_FILTER_PHYERR); + } + } + break; + case ZM_HAL_ANI_PHYERR_RESET: + HpPriv->stats.ast_ani_ofdmerrs = 0; + HpPriv->stats.ast_ani_cckerrs = 0; + break; +#endif /* AH_PRIVATE_DIAG */ + default: + zm_debug_msg1("invalid cmd ", cmd); + return FALSE; + } + return TRUE; +#undef N +} + +void zfHpAniRestart(zdev_t* dev) +{ + struct zsAniState *aniState; + + zmw_get_wlan_dev(dev); + + struct zsHpPriv *HpPriv = (struct zsHpPriv*)wd->hpPrivate; + + aniState = HpPriv->curani; + + aniState->listenTime = 0; + if (HpPriv->hasHwPhyCounters) + { + //if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) + //{ + // aniState->ofdmPhyErrBase = 0; + // zm_debug_msg0("OFDM Trigger is too high for hw counters"); + //} + //else + // aniState->ofdmPhyErrBase = AR_PHY_COUNTMAX - aniState->ofdmTrigHigh; + //if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) + //{ + // aniState->cckPhyErrBase = 0; + // zm_debug_msg0("CCK Trigger is too high for hw counters"); + //} + //else + // aniState->cckPhyErrBase = AR_PHY_COUNTMAX - aniState->cckTrigHigh; + //zm_debug_msg2("Writing ofdmbase = 0x", aniState->ofdmPhyErrBase); + //zm_debug_msg2("Writing cckbase = 0x", aniState->cckPhyErrBase); + //OS_REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase); + //OS_REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase); + //OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); + //OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); + aniState->ofdmPhyErrBase = 0; + aniState->cckPhyErrBase = 0; + } + aniState->ofdmPhyErrCount = 0; + aniState->cckPhyErrCount = 0; +} + +void zfHpAniOfdmErrTrigger(zdev_t* dev) +{ + struct zsAniState *aniState; + s32_t rssi; + + zmw_get_wlan_dev(dev); + + struct zsHpPriv *HpPriv = (struct zsHpPriv*)wd->hpPrivate; + + //HALASSERT(chan != NULL); + + if ((HpPriv->procPhyErr & ZM_HAL_PROCESS_ANI) == 0) + return; + + aniState = HpPriv->curani; + /* First, raise noise immunity level, up to max */ + if (aniState->noiseImmunityLevel < ZM_HAL_NOISE_IMMUNE_MAX) + { + zfHpAniControl(dev, ZM_HAL_ANI_NOISE_IMMUNITY_LEVEL, aniState->noiseImmunityLevel + 1); + return; + } + /* then, raise spur immunity level, up to max */ + if (aniState->spurImmunityLevel < ZM_HAL_SPUR_IMMUNE_MAX) + { + zfHpAniControl(dev, ZM_HAL_ANI_SPUR_IMMUNITY_LEVEL, aniState->spurImmunityLevel + 1); + return; + } + rssi = BEACON_RSSI(dev); + if (rssi > aniState->rssiThrHigh) + { + /* + * Beacon rssi is high, can turn off ofdm weak sig detect. + */ + if (!aniState->ofdmWeakSigDetectOff) + { + zfHpAniControl(dev, ZM_HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, FALSE); + zfHpAniControl(dev, ZM_HAL_ANI_SPUR_IMMUNITY_LEVEL, 0); + return; + } + /* + * If weak sig detect is already off, as last resort, raise + * first step level + */ + if (aniState->firstepLevel < ZM_HAL_FIRST_STEP_MAX) + { + zfHpAniControl(dev, ZM_HAL_ANI_FIRSTEP_LEVEL, aniState->firstepLevel + 1); + return; + } + } + else if (rssi > aniState->rssiThrLow) + { + /* + * Beacon rssi in mid range, need ofdm weak signal detect, + * but we can raise firststepLevel + */ + if (aniState->ofdmWeakSigDetectOff) + zfHpAniControl(dev, ZM_HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, TRUE); + if (aniState->firstepLevel < ZM_HAL_FIRST_STEP_MAX) + zfHpAniControl(dev, ZM_HAL_ANI_FIRSTEP_LEVEL, aniState->firstepLevel + 1); + return; + } + else + { + /* + * Beacon rssi is low, if in 11b/g mode, turn off ofdm + * weak sign detction and zero firstepLevel to maximize + * CCK sensitivity + */ + if (wd->frequency < 3000) + { + if (!aniState->ofdmWeakSigDetectOff) + zfHpAniControl(dev, ZM_HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, FALSE); + if (aniState->firstepLevel > 0) + zfHpAniControl(dev, ZM_HAL_ANI_FIRSTEP_LEVEL, 0); + return; + } + } +} + +void zfHpAniCckErrTrigger(zdev_t* dev) +{ + struct zsAniState *aniState; + s32_t rssi; + + zmw_get_wlan_dev(dev); + + struct zsHpPriv *HpPriv = (struct zsHpPriv*)wd->hpPrivate; + + //HALASSERT(chan != NULL); + + if ((HpPriv->procPhyErr & ZM_HAL_PROCESS_ANI) == 0) + return; + + /* first, raise noise immunity level, up to max */ + aniState = HpPriv->curani; + if (aniState->noiseImmunityLevel < ZM_HAL_NOISE_IMMUNE_MAX) + { + zfHpAniControl(dev, ZM_HAL_ANI_NOISE_IMMUNITY_LEVEL, + aniState->noiseImmunityLevel + 1); + return; + } + rssi = BEACON_RSSI(dev); + if (rssi > aniState->rssiThrLow) + { + /* + * Beacon signal in mid and high range, raise firsteplevel. + */ + if (aniState->firstepLevel < ZM_HAL_FIRST_STEP_MAX) + zfHpAniControl(dev, ZM_HAL_ANI_FIRSTEP_LEVEL, aniState->firstepLevel + 1); + } + else + { + /* + * Beacon rssi is low, zero firstepLevel to maximize + * CCK sensitivity. + */ + if (wd->frequency < 3000) + { + if (aniState->firstepLevel > 0) + zfHpAniControl(dev, ZM_HAL_ANI_FIRSTEP_LEVEL, 0); + } + } +} + +void zfHpAniLowerImmunity(zdev_t* dev) +{ + struct zsAniState *aniState; + s32_t rssi; + + zmw_get_wlan_dev(dev); + + struct zsHpPriv *HpPriv = (struct zsHpPriv*)wd->hpPrivate; + + aniState = HpPriv->curani; + + rssi = BEACON_RSSI(dev); + if (rssi > aniState->rssiThrHigh) + { + /* + * Beacon signal is high, leave ofdm weak signal detection off + * or it may oscillate. Let it fall through. + */ + } + else if (rssi > aniState->rssiThrLow) + { + /* + * Beacon rssi in mid range, turn on ofdm weak signal + * detection or lower first step level. + */ + if (aniState->ofdmWeakSigDetectOff) + { + zfHpAniControl(dev, ZM_HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, TRUE); + return; + } + if (aniState->firstepLevel > 0) + { + zfHpAniControl(dev, ZM_HAL_ANI_FIRSTEP_LEVEL, aniState->firstepLevel - 1); + return; + } + } + else + { + /* + * Beacon rssi is low, reduce first step level. + */ + if (aniState->firstepLevel > 0) + { + zfHpAniControl(dev, ZM_HAL_ANI_FIRSTEP_LEVEL, aniState->firstepLevel - 1); + return; + } + } + /* then lower spur immunity level, down to zero */ + if (aniState->spurImmunityLevel > 0) + { + zfHpAniControl(dev, ZM_HAL_ANI_SPUR_IMMUNITY_LEVEL, aniState->spurImmunityLevel - 1); + return; + } + /* + * if all else fails, lower noise immunity level down to a min value + * zero for now + */ + if (aniState->noiseImmunityLevel > 0) + { + zfHpAniControl(dev, ZM_HAL_ANI_NOISE_IMMUNITY_LEVEL, aniState->noiseImmunityLevel - 1); + return; + } +} + +#define CLOCK_RATE 44000 /* XXX use mac_usec or similar */ +/* convert HW counter values to ms using 11g clock rate, goo9d enough + for 11a and Turbo */ + +/* + * Return an approximation of the time spent ``listening'' by + * deducting the cycles spent tx'ing and rx'ing from the total + * cycle count since our last call. A return value <0 indicates + * an invalid/inconsistent time. + */ +s32_t zfHpAniGetListenTime(zdev_t* dev) +{ + struct zsAniState *aniState; + u32_t txFrameCount, rxFrameCount, cycleCount; + s32_t listenTime; + + zmw_get_wlan_dev(dev); + + struct zsHpPriv *HpPriv = (struct zsHpPriv*)wd->hpPrivate; + + txFrameCount = 0;//OS_REG_READ(ah, AR_TFCNT); + rxFrameCount = 0;//OS_REG_READ(ah, AR_RFCNT); + cycleCount = 0;//OS_REG_READ(ah, AR_CCCNT); + + aniState = HpPriv->curani; + if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) + { + /* + * Cycle counter wrap (or initial call); it's not possible + * to accurately calculate a value because the registers + * right shift rather than wrap--so punt and return 0. + */ + listenTime = 0; + HpPriv->stats.ast_ani_lzero++; + } + else + { + s32_t ccdelta = cycleCount - aniState->cycleCount; + s32_t rfdelta = rxFrameCount - aniState->rxFrameCount; + s32_t tfdelta = txFrameCount - aniState->txFrameCount; + listenTime = (ccdelta - rfdelta - tfdelta) / CLOCK_RATE; + } + aniState->cycleCount = cycleCount; + aniState->txFrameCount = txFrameCount; + aniState->rxFrameCount = rxFrameCount; + return listenTime; +} + +/* + * Do periodic processing. This routine is called from the + * driver's rx interrupt handler after processing frames. + */ +void zfHpAniArPoll(zdev_t* dev, u32_t listenTime, u32_t phyCnt1, u32_t phyCnt2) +{ + struct zsAniState *aniState; + //s32_t listenTime; + + zmw_get_wlan_dev(dev); + + struct zsHpPriv *HpPriv = (struct zsHpPriv*)wd->hpPrivate; + + /* + * Since we're called from end of rx tasklet, we also check for + * AR processing now + */ + + aniState = HpPriv->curani; + //HpPriv->stats.ast_nodestats = *stats; /* XXX optimize? */ + + //listenTime = zfHpAniGetListenTime(dev); + //if (listenTime < 0) + //{ + // HpPriv->stats.ast_ani_lneg++; + // /* restart ANI period if listenTime is invalid */ + // zfHpAniRestart(dev); + // return; + //} + /* XXX beware of overflow? */ + aniState->listenTime += listenTime; + + if (HpPriv->hasHwPhyCounters) + { + //u32_t phyCnt1, phyCnt2; + u32_t ofdmPhyErrCnt, cckPhyErrCnt; + + /* NB: these are not reset-on-read */ + //phyCnt1 = 0;//OS_REG_READ(ah, AR_PHY_ERR_1); + //phyCnt2 = 0;//OS_REG_READ(ah, AR_PHY_ERR_2); + /* XXX sometimes zero, why? */ + //if (phyCnt1 < aniState->ofdmPhyErrBase || + // phyCnt2 < aniState->cckPhyErrBase) + //{ + // if (phyCnt1 < aniState->ofdmPhyErrBase) + // { + // zm_debug_msg2("phyCnt1 = 0x", phyCnt1); + // zm_debug_msg2("resetting counter value to 0x", aniState->ofdmPhyErrBase); + // //OS_REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase); + // //OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); + // } + // if (phyCnt2 < aniState->cckPhyErrBase) + // { + // zm_debug_msg2("phyCnt2 = 0x", phyCnt2); + // zm_debug_msg2("resetting counter value to 0x", aniState->cckPhyErrBase); + // //OS_REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase); + // //OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); + // } + // return; /* XXX */ + //} + /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */ + //ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; + //HpPriv->stats.ast_ani_ofdmerrs += ofdmPhyErrCnt - aniState->ofdmPhyErrCount; + //aniState->ofdmPhyErrCount = ofdmPhyErrCnt; + ofdmPhyErrCnt = phyCnt1; + HpPriv->stats.ast_ani_ofdmerrs += ofdmPhyErrCnt; + aniState->ofdmPhyErrCount += ofdmPhyErrCnt; + + //cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; + //HpPriv->stats.ast_ani_cckerrs += cckPhyErrCnt - aniState->cckPhyErrCount; + //aniState->cckPhyErrCount = cckPhyErrCnt; + cckPhyErrCnt = phyCnt2; + HpPriv->stats.ast_ani_cckerrs += cckPhyErrCnt; + aniState->cckPhyErrCount += cckPhyErrCnt; + } + /* + * If ani is not enabled, return after we've collected + * statistics + */ + if ((HpPriv->procPhyErr & ZM_HAL_PROCESS_ANI) == 0) + return; + if (aniState->listenTime > 5 * HpPriv->aniPeriod) + { + /* + * Check to see if need to lower immunity if + * 5 aniPeriods have passed + */ + if (aniState->ofdmPhyErrCount <= aniState->listenTime * + aniState->ofdmTrigLow/1000 && + aniState->cckPhyErrCount <= aniState->listenTime * + aniState->cckTrigLow/1000) + zfHpAniLowerImmunity(dev); + zfHpAniRestart(dev); + } + else if (aniState->listenTime > HpPriv->aniPeriod) + { + /* check to see if need to raise immunity */ + if (aniState->ofdmPhyErrCount > aniState->listenTime * + aniState->ofdmTrigHigh / 1000) + { + zfHpAniOfdmErrTrigger(dev); + zfHpAniRestart(dev); + } + else if (aniState->cckPhyErrCount > aniState->listenTime * + aniState->cckTrigHigh / 1000) + { + zfHpAniCckErrTrigger(dev); + zfHpAniRestart(dev); + } + } +} diff --git a/drivers/staging/otus/hal/hpani.h b/drivers/staging/otus/hal/hpani.h new file mode 100644 index 000000000000..96e69af3c685 --- /dev/null +++ b/drivers/staging/otus/hal/hpani.h @@ -0,0 +1,420 @@ +/* + * Copyright (c) 2007-2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include "../80211core/cprecomp.h" + +typedef struct { + u32_t ackrcv_bad; + u32_t rts_bad; + u32_t rts_good; + u32_t fcs_bad; + u32_t beacons; +} ZM_HAL_MIB_STATS; + +/* + * Per-node statistics maintained by the driver for use in + * optimizing signal quality and other operational aspects. + */ +typedef struct { + u32_t ns_avgbrssi; /* average beacon rssi */ + u32_t ns_avgrssi; /* average data rssi */ + u32_t ns_avgtxrssi; /* average tx rssi */ +} ZM_HAL_NODE_STATS; + +#define ZM_HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ + +struct zsAniStats { + u32_t ast_ani_niup; /* ANI increased noise immunity */ + u32_t ast_ani_nidown; /* ANI decreased noise immunity */ + u32_t ast_ani_spurup; /* ANI increased spur immunity */ + u32_t ast_ani_spurdown;/* ANI descreased spur immunity */ + u32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ + u32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ + u32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ + u32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ + u32_t ast_ani_stepup; /* ANI increased first step level */ + u32_t ast_ani_stepdown;/* ANI decreased first step level */ + u32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ + u32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ + u32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ + u32_t ast_ani_lzero; /* ANI listen time forced to zero */ + u32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ + ZM_HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ + ZM_HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ +}; + +/* + * Per-channel ANI state private to the driver. + */ +struct zsAniState { + ZM_HAL_CHANNEL c; + u8_t noiseImmunityLevel; + u8_t spurImmunityLevel; + u8_t firstepLevel; + u8_t ofdmWeakSigDetectOff; + u8_t cckWeakSigThreshold; + + /* Thresholds */ + u32_t listenTime; + u32_t ofdmTrigHigh; + u32_t ofdmTrigLow; + s32_t cckTrigHigh; + s32_t cckTrigLow; + s32_t rssiThrLow; + s32_t rssiThrHigh; + + u32_t noiseFloor; /* The current noise floor */ + u32_t txFrameCount; /* Last txFrameCount */ + u32_t rxFrameCount; /* Last rx Frame count */ + u32_t cycleCount; /* Last cycleCount (can detect wrap-around) */ + u32_t ofdmPhyErrCount;/* OFDM err count since last reset */ + u32_t cckPhyErrCount; /* CCK err count since last reset */ + u32_t ofdmPhyErrBase; /* Base value for ofdm err counter */ + u32_t cckPhyErrBase; /* Base value for cck err counters */ + s16_t pktRssi[2]; /* Average rssi of pkts for 2 antennas */ + s16_t ofdmErrRssi[2]; /* Average rssi of ofdm phy errs for 2 ant */ + s16_t cckErrRssi[2]; /* Average rssi of cck phy errs for 2 ant */ +}; + +typedef enum { + ZM_HAL_ANI_PRESENT, /* is ANI support present */ + ZM_HAL_ANI_NOISE_IMMUNITY_LEVEL, /* set level */ + ZM_HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, /* enable/disable */ + ZM_HAL_ANI_CCK_WEAK_SIGNAL_THR, /* enable/disable */ + ZM_HAL_ANI_FIRSTEP_LEVEL, /* set level */ + ZM_HAL_ANI_SPUR_IMMUNITY_LEVEL, /* set level */ + ZM_HAL_ANI_MODE, /* 0 => manual, 1 => auto */ + ZM_HAL_ANI_PHYERR_RESET, /* reset phy error stats */ +} ZM_HAL_ANI_CMD; + +#define AR_PHY_COUNTMAX (3 << 22) // Max counted before intr +#define ZM_HAL_PROCESS_ANI 0x00000001 /* ANI state setup */ +#define ZM_RSSI_DUMMY_MARKER 0x127 + +/* PHY registers in ar5416, related base and register offsets + may need to be changed in otus BB */ +#define AR_PHY_BASE 0x1C5800 /* base address of phy regs */ +#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) + +#define AR_PHY_TEST 0x1C5800 /* PHY test control */ +#define PHY_AGC_CLR 0x10000000 /* disable AGC to A2 */ +#define RFSILENT_BB 0x00002000 /* shush bb */ + +#define AR_PHY_TURBO 0x1C5804 /* frame control register */ +#define AR_PHY_FC_TURBO_MODE 0x00000001 /* Set turbo mode bits */ +#define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */ +#define AR_PHY_FC_DYN2040_EN 0x00000004 /* Enable dyn 20/40 mode */ +#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */ +#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/ +#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */ +#define AR_PHY_FC_HT_EN 0x00000040 /* ht enable */ +#define AR_PHY_FC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */ +#define AR_PHY_FC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */ +#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */ + +#define AR_PHY_TIMING2 0x1C5810 /* Timing Control 2 */ +#define AR_PHY_TIMING2_USE_FORCE 0x00001000 +#define AR_PHY_TIMING2_FORCE_VAL 0x00000fff + +#define AR_PHY_TIMING3 0x1C5814 /* Timing control 3 */ +#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000 +#define AR_PHY_TIMING3_DSC_MAN_S 17 +#define AR_PHY_TIMING3_DSC_EXP 0x0001E000 +#define AR_PHY_TIMING3_DSC_EXP_S 13 + +#define AR_PHY_CHIP_ID 0x1C5818 /* PHY chip revision ID */ +#define AR_PHY_CHIP_ID_REV_0 0x80 /* 5416 Rev 0 (owl 1.0) BB */ +#define AR_PHY_CHIP_ID_REV_1 0x81 /* 5416 Rev 1 (owl 2.0) BB */ + +#define AR_PHY_ACTIVE 0x1C581C /* activation register */ +#define AR_PHY_ACTIVE_EN 0x00000001 /* Activate PHY chips */ +#define AR_PHY_ACTIVE_DIS 0x00000000 /* Deactivate PHY chips */ + +#define AR_PHY_RF_CTL2 0x1C5824 +#define AR_PHY_TX_END_DATA_START 0x000000FF +#define AR_PHY_TX_END_DATA_START_S 0 +#define AR_PHY_TX_END_PA_ON 0x0000FF00 +#define AR_PHY_TX_END_PA_ON_S 8 + + +#define AR_PHY_RF_CTL3 0x1C5828 +#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000 +#define AR_PHY_TX_END_TO_A2_RX_ON_S 16 + +#define AR_PHY_ADC_CTL 0x1C582C +#define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003 +#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0 +#define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000 +#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000 /* BB Rev 4.2+ only */ +#define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000 /* BB Rev 4.2+ only */ +#define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000 +#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16 + +#define AR_PHY_ADC_SERIAL_CTL 0x1C5830 +#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000 +#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001 + +#define AR_PHY_RF_CTL4 0x1C5834 +#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000 +#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24 +#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000 +#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16 +#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00 +#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8 +#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF +#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0 + +#define AR_PHY_SETTLING 0x1C5844 +#define AR_PHY_SETTLING_SWITCH 0x00003F80 +#define AR_PHY_SETTLING_SWITCH_S 7 + +#define AR_PHY_RXGAIN 0x1C5848 +#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000 +#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12 +#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000 +#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18 + +#define AR_PHY_DESIRED_SZ 0x1C5850 +#define AR_PHY_DESIRED_SZ_ADC 0x000000FF +#define AR_PHY_DESIRED_SZ_ADC_S 0 +#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00 +#define AR_PHY_DESIRED_SZ_PGA_S 8 +#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000 +#define AR_PHY_DESIRED_SZ_TOT_DES_S 20 + +#define AR_PHY_FIND_SIG 0x1C5858 +#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000 +#define AR_PHY_FIND_SIG_FIRSTEP_S 12 +#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000 +#define AR_PHY_FIND_SIG_FIRPWR_S 18 + +#define AR_PHY_AGC_CTL1 0x1C585C +#define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80 +#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7 +#define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000 +#define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15 + +#define AR_PHY_AGC_CONTROL 0x1C5860 /* chip calibration and noise floor setting */ +#define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */ +#define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calculation */ + +#define AR_PHY_CCA 0x1C5864 +#define AR_PHY_MINCCA_PWR 0x1FF00000 +#define AR_PHY_MINCCA_PWR_S 19 +#define AR_PHY_CCA_THRESH62 0x0007F000 +#define AR_PHY_CCA_THRESH62_S 12 + +#define AR_PHY_SFCORR_LOW 0x1C586C +#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21 + +#define AR_PHY_SFCORR 0x1C5868 +#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F +#define AR_PHY_SFCORR_M2COUNT_THR_S 0 +#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000 +#define AR_PHY_SFCORR_M1_THRESH_S 17 +#define AR_PHY_SFCORR_M2_THRESH 0x7F000000 +#define AR_PHY_SFCORR_M2_THRESH_S 24 + +#define AR_PHY_SLEEP_CTR_CONTROL 0x1C5870 +#define AR_PHY_SLEEP_CTR_LIMIT 0x1C5874 +#define AR_PHY_SLEEP_SCAL 0x1C5878 + +#define AR_PHY_PLL_CTL 0x1C587c /* PLL control register */ +#define AR_PHY_PLL_CTL_40 0xaa /* 40 MHz */ +#define AR_PHY_PLL_CTL_40_5413 0x04 +#define AR_PHY_PLL_CTL_44 0xab /* 44 MHz for 11b, 11g */ +#define AR_PHY_PLL_CTL_44_2133 0xeb /* 44 MHz for 11b, 11g */ +#define AR_PHY_PLL_CTL_40_2133 0xea /* 40 MHz for 11a, turbos */ + +#define AR_PHY_RX_DELAY 0x1C5914 /* analog pow-on time (100ns) */ +#define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */ + +#define AR_PHY_TIMING_CTRL4 0x1C5920 /* timing control */ +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F /* Mask for kcos_theta-1 for q correction */ +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 /* shift for Q_COFF */ +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0 /* Mask for sin_theta for i correction */ +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 /* Shift for sin_theta for i correction */ +#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800 /* enable IQ correction */ +#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000 /* Mask for max number of samples (logarithmic) */ +#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 /* Shift for max number of samples */ +#define AR_PHY_TIMING_CTRL4_DO_IQCAL 0x10000 /* perform IQ calibration */ + +#define AR_PHY_TIMING5 0x1C5924 +#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE +#define AR_PHY_TIMING5_CYCPWR_THR1_S 1 + +#define AR_PHY_POWER_TX_RATE1 0x1C5934 +#define AR_PHY_POWER_TX_RATE2 0x1C5938 +#define AR_PHY_POWER_TX_RATE_MAX 0x1C593c +#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040 + +#define AR_PHY_FRAME_CTL 0x1C5944 +#define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038 +#define AR_PHY_FRAME_CTL_TX_CLIP_S 3 + +#define AR_PHY_TXPWRADJ 0x1C594C /* BB Rev 4.2+ only */ +#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0 +#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6 +#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000 +#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18 + +#define AR_PHY_RADAR_0 0x1C5954 /* radar detection settings */ +#define AR_PHY_RADAR_0_ENA 0x00000001 /* Enable radar detection */ +#define AR_PHY_RADAR_0_INBAND 0x0000003e /* Inband pulse threshold */ +#define AR_PHY_RADAR_0_INBAND_S 1 +#define AR_PHY_RADAR_0_PRSSI 0x00000FC0 /* Pulse rssi threshold */ +#define AR_PHY_RADAR_0_PRSSI_S 6 +#define AR_PHY_RADAR_0_HEIGHT 0x0003F000 /* Pulse height threshold */ +#define AR_PHY_RADAR_0_HEIGHT_S 12 +#define AR_PHY_RADAR_0_RRSSI 0x00FC0000 /* Radar rssi threshold */ +#define AR_PHY_RADAR_0_RRSSI_S 18 +#define AR_PHY_RADAR_0_FIRPWR 0x7F000000 /* Radar firpwr threshold */ +#define AR_PHY_RADAR_0_FIRPWR_S 24 + +#define AR_PHY_SWITCH_CHAIN_0 0x1C5960 +#define AR_PHY_SWITCH_COM 0x1C5964 + +#define AR_PHY_SIGMA_DELTA 0x1C596C /* AR5312 only */ +#define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003 +#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0 +#define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8 +#define AR_PHY_SIGMA_DELTA_FILT2_S 3 +#define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00 +#define AR_PHY_SIGMA_DELTA_FILT1_S 8 +#define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000 +#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13 + +#define AR_PHY_RESTART 0x1C5970 /* restart */ +#define AR_PHY_RESTART_DIV_GC 0x001C0000 /* bb_ant_fast_div_gc_limit */ +#define AR_PHY_RESTART_DIV_GC_S 18 + +#define AR_PHY_RFBUS_REQ 0x1C597C +#define AR_PHY_RFBUS_REQ_EN 0x00000001 + +#define AR_PHY_RX_CHAINMASK 0x1C59a4 + +#define AR_PHY_EXT_CCA 0x1C59bc +#define AR_PHY_EXT_MINCCA_PWR 0xFF800000 +#define AR_PHY_EXT_MINCCA_PWR_S 23 + +#define AR_PHY_HALFGI 0x1C59D0 /* Timing control 3 */ +#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0 +#define AR_PHY_HALFGI_DSC_MAN_S 4 +#define AR_PHY_HALFGI_DSC_EXP 0x0000000F +#define AR_PHY_HALFGI_DSC_EXP_S 0 + +#define AR_PHY_HEAVY_CLIP_ENABLE 0x1C59E0 + +#define AR_PHY_M_SLEEP 0x1C59f0 /* sleep control registers */ +#define AR_PHY_REFCLKDLY 0x1C59f4 +#define AR_PHY_REFCLKPD 0x1C59f8 + +/* PHY IQ calibration results */ +#define AR_PHY_IQCAL_RES_PWR_MEAS_I 0x1C5C10 /* power measurement for I */ +#define AR_PHY_IQCAL_RES_PWR_MEAS_Q 0x1C5C14 /* power measurement for Q */ +#define AR_PHY_IQCAL_RES_IQ_CORR_MEAS 0x1C5C18 /* IQ correlation measurement */ + +#define AR_PHY_CURRENT_RSSI 0x1C5C1c /* rssi of current frame rx'd */ + +#define AR_PHY_RFBUS_GRANT 0x1C5C20 +#define AR_PHY_RFBUS_GRANT_EN 0x00000001 + +#define AR_PHY_MODE 0x1C6200 /* Mode register */ +#define AR_PHY_MODE_AR2133 0x08 /* AR2133 */ +#define AR_PHY_MODE_AR5111 0x00 /* AR5111/AR2111 */ +#define AR_PHY_MODE_AR5112 0x08 /* AR5112*/ +#define AR_PHY_MODE_DYNAMIC 0x04 /* dynamic CCK/OFDM mode */ +#define AR_PHY_MODE_RF2GHZ 0x02 /* 2.4 GHz */ +#define AR_PHY_MODE_RF5GHZ 0x00 /* 5 GHz */ +#define AR_PHY_MODE_CCK 0x01 /* CCK */ +#define AR_PHY_MODE_OFDM 0x00 /* OFDM */ + +#define AR_PHY_CCK_TX_CTRL 0x1C6204 +#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010 + +#define AR_PHY_CCK_DETECT 0x1C6208 +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 // [12:6] settling time for antenna switch +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 +#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000 + +#define AR_PHY_GAIN_2GHZ 0x1C620C +#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000 +#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18 +#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00 +#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10 +#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F +#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0 + +#define AR_PHY_CCK_RXCTRL4 0x1C621C +#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000 +#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19 + +#define AR_PHY_DAG_CTRLCCK 0x1C6228 +#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 /* BB Rev 4.2+ only */ +#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00 /* BB Rev 4.2+ only */ +#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10 /* BB Rev 4.2+ only */ + +#define AR_PHY_POWER_TX_RATE3 0x1C6234 +#define AR_PHY_POWER_TX_RATE4 0x1C6238 + +#define AR_PHY_SCRM_SEQ_XR 0x1C623C +#define AR_PHY_HEADER_DETECT_XR 0x1C6240 +#define AR_PHY_CHIRP_DETECTED_XR 0x1C6244 +#define AR_PHY_BLUETOOTH 0x1C6254 + +#define AR_PHY_TPCRG1 0x1C6258 /* ar2413 power control */ +#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000 +#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14 + +#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000 +#define AR_PHY_TPCRG1_PD_GAIN_1_S 16 +#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000 +#define AR_PHY_TPCRG1_PD_GAIN_2_S 18 +#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000 +#define AR_PHY_TPCRG1_PD_GAIN_3_S 20 +// + +#define AR_PHY_ANALOG_SWAP 0xa268 +#define AR_PHY_SWAP_ALT_CHAIN 0x00000040 + +#define AR_PHY_TPCRG5 0x1C626C /* ar2413 power control */ +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22 + +#define AR_PHY_POWER_TX_RATE5 0x1C638C +#define AR_PHY_POWER_TX_RATE6 0x1C6390 + +#define AR_PHY_CAL_CHAINMASK 0x1C639C + +#define AR_PHY_POWER_TX_SUB 0x1C63C8 +#define AR_PHY_POWER_TX_RATE7 0x1C63CC +#define AR_PHY_POWER_TX_RATE8 0x1C63D0 +#define AR_PHY_POWER_TX_RATE9 0x1C63D4 diff --git a/drivers/staging/otus/hal/hpfw2.c b/drivers/staging/otus/hal/hpfw2.c new file mode 100644 index 000000000000..baceb0299765 --- /dev/null +++ b/drivers/staging/otus/hal/hpfw2.c @@ -0,0 +1,1018 @@ +/* + * Copyright (c) 2007-2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include "../80211core/cprecomp.h" + +const u32_t zcP2FwImage[] = { +0x0009000B, 0x4F222FE6, 0xDE947FFC, 0xE114D594, +0x1E13D494, 0x67521E4C, 0xD494D693, 0x37402769, +0x62528F06, 0x7201D692, 0x60602522, 0x2600C93F, +0xD7906152, 0x2512611D, 0x264B6652, 0x2562470B, +0x0009B00D, 0xE60095AC, 0xC84060E2, 0x2F028F03, +0x8FF93652, 0x7F047601, 0xA05A4F26, 0x4F226EF6, +0x410BD185, 0xD4850009, 0x0009440B, 0x450BD584, +0xD7840009, 0xD284E1FF, 0x2712611D, 0xD4835029, +0xE1FFCB01, 0x1209E501, 0x12112212, 0xE7202452, +0x4718D57F, 0x2572D27F, 0xD17FE700, 0xD680D47F, +0xE2012270, 0x24702172, 0xD67E2620, 0x2641E4FF, +0xD57DE600, 0x666DE104, 0x76016063, 0x4000626D, +0x8FF83212, 0xD5790545, 0x2520E201, 0xD279D778, +0x2710E100, 0xE5802212, 0x655C6613, 0x666DD476, +0x76046763, 0x374C626D, 0x8FF83253, 0xD4732712, +0xD573E101, 0xD6732410, 0x2542E400, 0xE03AE501, +0xD272D771, 0xE0390654, 0x27110654, 0x000B4F26, +0x7FC82211, 0xD76FD16E, 0xDC70DB6F, 0xD271DE70, +0xD572D471, 0x1F12D672, 0x1F76710C, 0x1FB877FC, +0x1FEA1FC9, 0x72041F2B, 0xDE6FDC6E, 0x1F13EB10, +0x1F511F44, 0x1F771F65, 0xD86C1F2C, 0xDD6DD96C, +0xD26DEA00, 0x89003A22, 0xD1587A01, 0x88016010, +0x56F98B03, 0x4218E201, 0xD1682622, 0x0009410B, +0x440BD467, 0xD5670009, 0x0009450B, 0x6010D14C, +0x8B108801, 0xE650D14B, 0x46186212, 0x8B083266, +0x56FAD147, 0x2120E200, 0xCB016062, 0x2602A003, +0x72012710, 0x60822122, 0x89098801, 0xE2C8D15A, +0x622C6612, 0x89033626, 0x6010D158, 0x8BC88801, +0x51F76792, 0x217252F6, 0xD6555191, 0x55FB2212, +0x52FC6462, 0x55612542, 0x2252E400, 0x61436643, +0x05DE6013, 0x36CC4608, 0x02DE2652, 0xC9036021, +0x8B028801, 0x720162E2, 0x74012E22, 0x36B3664C, +0x71048FEE, 0x66C2D147, 0x45286512, 0x265B4518, +0x60822C62, 0x89018801, 0x0009A168, 0x6272D742, +0x8B132228, 0xD726D541, 0x6552D441, 0x51436672, +0x316C365C, 0x27622668, 0x14138D05, 0x6262D63D, +0xB1A57201, 0xD61E2622, 0x2622E200, 0x52916692, +0x8B013620, 0x0009A144, 0x6061A06E, 0x001C001C, +0x001D4020, 0x0000B38E, 0xFFFF0000, 0x12340000, +0x001E1015, 0x00201278, 0x002018A0, 0x00201922, +0x0020128C, 0x001C3510, 0x001C3624, 0x001E212C, +0x0020397C, 0x00203514, 0x00203984, 0x00203990, +0x0020399C, 0x002039F8, 0x002039FC, 0x002039A4, +0x002039A5, 0x002039A8, 0x00117700, 0x00203A12, +0x00203578, 0x001142D8, 0x00203A14, 0x00203A16, +0x001C3D30, 0x00117718, 0x001C3D00, 0x001C1000, +0x001C36F8, 0x00117734, 0x001C3684, 0x00117710, +0x001C3520, 0x00117600, 0x00117740, 0x001C1028, +0x0020358C, 0x002039AC, 0x7FFFFFFF, 0x00201734, +0x002032BE, 0x002022E8, 0x00203DC0, 0x002039FA, +0x00203584, 0x002039EC, 0x001C3D2C, 0x001C36B0, +0x0020351C, 0x0011775C, 0x8801C90F, 0xA0CF8901, +0xD17C0009, 0x36206212, 0xD47B8904, 0x2421E200, +0x2162A0CC, 0x6211D179, 0x89012228, 0x0009A0C3, +0xE202D775, 0x75016571, 0x3123615D, 0x27518D02, +0x0009A0BC, 0xD27255F2, 0x62226052, 0x40094019, +0xC90F4009, 0x8F19880A, 0x52F31F2D, 0x40196022, +0x40094009, 0x8808C90F, 0xA0A78901, 0x60630009, +0x51F255F8, 0xE701CB01, 0x2502D263, 0xE1002172, +0x2211D564, 0x74016452, 0x2542A098, 0x8B3F8805, +0x602252F3, 0x40094019, 0xC90F4009, 0x8B168802, +0xE5FFD45D, 0x655D6742, 0x8B102758, 0x6272D75B, +0x8B0C3260, 0x55F257F8, 0x2762E101, 0xD5522512, +0xD757E400, 0x62722541, 0xA0777201, 0x52F32722, +0x40196022, 0x40094009, 0x8805C90F, 0x31B38B6E, +0xD5508B6C, 0x615257F4, 0x7101E240, 0x64722512, +0x1F4DD14D, 0x42182419, 0x8B033420, 0x6262D64B, +0x26227201, 0xE200D640, 0x2621B0AA, 0x0009A056, +0x3123E220, 0x88038B52, 0x52F38B1E, 0x40196022, +0x40094009, 0x8803C90F, 0xD7418B16, 0x647251F4, +0x7401D23D, 0x65122742, 0x1F5DE640, 0x46182529, +0x8B033560, 0x6262D63B, 0x26227201, 0xE200D62E, +0x2621B086, 0x0009A010, 0xD738D137, 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0x61432065, 0x7262696C, +0x6F697461, 0x6166206E, 0x6F206C69, 0x6974206E, +0x0D0A656D, 0x00000000, 0x00000072, 0x00205220, +0x62735576, 0x7473725F, 0x00000A0D, 0x62735576, +0x7375735F, 0x646E6570, 0x00000A0D, 0x62735576, +0x7365725F, 0x000A0D6D, 0x00000044, 0x44387570, +0x72637365, 0x6F747069, 0x3D584572, 0x00000000, +0x00000047, 0x72746E49, 0x6D652051, 0x2C797470, +0x49677A20, 0x4972746E, 0x754E514E, 0x00003D6D, +0x654C7245, 0x0000006E, 0x20746F4E, 0x756F6E65, +0x49206867, 0x4220514E, 0x0A0D6675, 0x00000000, +0x000000FF, 0x00020001, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x010E010D, 0x00020003, 0x01090108, 0x0002010A, +0x02000003, 0x02020201, 0x02040203, 0x02060205, +0x02020200, 0x02040203, 0x020C020B, 0x020E020D, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x000000FF, 0x00020001, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x010E010D, 0x00020003, 0x01090108, 0x0002010A, +0x00030003, 0x02020201, 0x02040203, 0x02060205, +0x02020200, 0x02040203, 0x020C020B, 0x020E020D, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x010E010D, 0x00FF010F, 0x01090108, 0x010B010A, +0x0200010F, 0x02020201, 0x02040203, 0x02060205, +0x02020200, 0x02040203, 0x020C020B, 0x020E020D, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x010E010D, 0x00FF010F, 0x01090108, 0x010B010A, +0x010F010F, 0x02020201, 0x02040203, 0x02060205, +0x02020200, 0x02040203, 0x020C020B, 0x020E020D, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00205220, 0x00000046, 0x00000059, 0x73204142, +0x003D7165, 0x49544120, 0x0000204D, 0x00000000, +0x00000000, 0x002E0209, 0x80000101, 0x000409FA, +0x00FF0400, 0x05070000, 0x02000201, 0x82050700, +0x00020002, 0x03830507, 0x07010040, 0x40030405, +0x02090100, 0x0101002E, 0x09FA8000, 0x04000004, +0x000000FF, 0x02010507, 0x07000040, 0x40028205, +0x05070000, 0x00400383, 0x04050701, 0x00004002, +0x00000000, 0x00000000, 0x07090000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, }; + +const u32_t zcP2FwImageSize=15964; diff --git a/drivers/staging/otus/hal/hpfwbu.c b/drivers/staging/otus/hal/hpfwbu.c new file mode 100644 index 000000000000..f60f57ed887a --- /dev/null +++ b/drivers/staging/otus/hal/hpfwbu.c @@ -0,0 +1,5269 @@ +/* + * Copyright (c) 2007-2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include "../80211core/cprecomp.h" + +const u32_t zcFwBufImage[] = { +0x3A4BCF18, 0xF44C076E, 0xF59452EA, 0x451BA755, +0x140AC87A, 0xC07EE942, 0x3EF978AB, 0xF5B03DC6, +0xB70080F0, 0xA89064EA, 0x54E2C1D6, 0xEB047DF4, +0x1798390C, 0x00350624, 0x35B3ECF0, 0x59F2FABF, +0xAF9D248E, 0xF9BDB9F0, 0xD05C8B47, 0xC08B5A16, +0x990093C7, 0xD335A160, 0x1C04942C, 0xBF6E7A88, +0xFD232B0F, 0x5C224387, 0xBF1E156C, 0xF24F2A27, +0xFF56421D, 0xB213037C, 0x2BA67BA0, 0x4950CF8A, +0x05F00F25, 0xA5E82085, 0x74168A0C, 0x2F2AB30B, +0xC80C57EE, 0xB6BDF570, 0x89BC5A99, 0x7F3B5A67, +0xF6C943B8, 0x0C9C9201, 0xE8383747, 0x0C9A72D6, +0xE0520704, 0xA66D7F30, 0xE444A434, 0xE0C94AB7, +0x8DD7751C, 0x1A659464, 0x6C9ABA4F, 0x792F2D2D, +0x5936F66B, 0x061E580E, 0x59903F6C, 0x1FBFB8A0, +0xCC822EFE, 0x4B030CAF, 0xB62457C9, 0x27E9BF15, +0xB113A487, 0xFA0FC915, 0x447B184A, 0x5330CD51, +0x00BCC622, 0xF30DE149, 0xFF718E1C, 0x7B5D2861, +0xDBCA573E, 0xFB0D7BF9, 0xE1CFBAAC, 0xF99D4583, +0x4BA7498A, 0x7CAEA7EB, 0xBA958E32, 0x36C530FF, +0x8F88CA99, 0xF93CABC2, 0x8E47EF11, 0xFB0EED6F, +0x5B3668A1, 0x9D63ADDE, 0xA0EEAB8C, 0x084915F1, +0xFACAAA27, 0x209638FE, 0x1CED9EFF, 0xEEBD2335, +0x38C6F424, 0x2D1F3D7E, 0x976E8106, 0xBE087AD2, +0x32194845, 0x756066DB, 0xC70E3165, 0xC568DCB1, +0x3212E4E1, 0xB5D991AD, 0x07C3CEF8, 0xDB4ABB38, +0x1574C232, 0xF8C792BC, 0x14E62DBE, 0x5A48E7DC, +0xEFDC5407, 0xC45B4017, 0x3B814E89, 0xF0936466, +0x89491B2B, 0x9A359A41, 0x82287675, 0xA0F338D3, +0x523FDD3C, 0x4E40B795, 0x458ADAA4, 0xED812957, +0x7ADC73BC, 0x6FD7DB78, 0x2740FC04, 0x6392AEA3, +0x185ABCEA, 0x6B50ABC3, 0x3681F07F, 0xC840F8CE, +0x5733E7EC, 0x0805FA71, 0x0B34530A, 0x8CB3D033, +0x81451551, 0x53B0B4EC, 0x908646D0, 0x10A3E642, +0xF358DC34, 0xC1FA570C, 0x2B1284B0, 0x592322BB, +0x9D587783, 0xE7D77988, 0xE1BE5D7B, 0x44B93E23, +0xF8BE94A2, 0x506DC723, 0x6E0A7D09, 0x3FB1046F, +0xDB3A166F, 0x9CB7D6A0, 0xE278DE6D, 0x88459334, +0xB52BA3C9, 0x284740A2, 0x04D30792, 0x944D79CA, +0x1D050EA9, 0xA404DB1B, 0x99526023, 0xBACE24E7, +0xB9F20704, 0x284E6432, 0x47A593D1, 0x95F8DFCB, +0x220C9167, 0x8FAABBBC, 0x93D34E8C, 0xCE077138, +0x4FC18081, 0xE76DD7E5, 0x67465F6C, 0x7A479D77, +0x74D61F82, 0x00559214, 0x2F66E42E, 0x8742A96B, +0x62063950, 0xA2DBFAE5, 0x368B966F, 0xAB5FCCE1, +0xCB4023B1, 0x1E7AF542, 0x05953E30, 0x8CA51CFC, +0x2216547D, 0x29D562D4, 0xE9C9F8EE, 0xA90505C9, +0x088D0EEB, 0xD7A290FA, 0x95E5B567, 0x53FAD3C0, +0xB89FC625, 0x69A7519B, 0x3687C7EF, 0x7188CB55, +0xCE5DB97E, 0xA260574A, 0xD453D173, 0x145D970B, +0x12112CC6, 0x399839E0, 0x29C55BEB, 0xE467C71F, +0x10B3C9D4, 0x8F1C9662, 0xF207A826, 0xE0245600, +0x688B1812, 0x5A483031, 0x7048380A, 0x78E3D5BB, +0x1951533D, 0x8FA5D8E3, 0xC5BE500D, 0x71DB5B2B, +0xA17AA000, 0x408C9BE8, 0x161E12F5, 0xB1C38C45, +0x22A88F05, 0xDE3F4405, 0x5078ADBB, 0xCE1BF1A6, +0xB7A75B04, 0x6B8364E8, 0x0CE32E3E, 0x9BF65504, +0x28C18157, 0x78359AC6, 0x617BF202, 0x1E76FA09, +0x0F8E61A8, 0x6D02F0D5, 0x80356459, 0x79CEFAE7, +0x7D00F155, 0x5C1C0128, 0xC75CA073, 0x32816090, +0x9FF78DFC, 0x848D269C, 0xF811B314, 0xA86920FC, +0x6F885D01, 0xACFE6525, 0xC726074D, 0xFED68599, +0xF1D5C76A, 0x8799E5F5, 0xF85F5171, 0xD8DE2D3B, +0xE7DD8E75, 0x43F8614A, 0x0684FC8D, 0x9683B8C8, +0x74BE786B, 0x2514762D, 0x7D866682, 0xE711FE1F, +0x0DE9E273, 0x12F53167, 0x4FA3A7FE, 0x2A00EB61, +0xB3984A28, 0x4319F2B0, 0x42BA0CA2, 0x848771B6, +0x995E945E, 0xD41115F5, 0x43D9834B, 0x54EEDC36, +0x5C3C5407, 0x671B540E, 0xDCF18948, 0x150ED973, +0x2D4922DE, 0xF93CA17D, 0xB24A76E5, 0xD1C01C22, +0xF2963DD6, 0x3B860066, 0x08EF0EA4, 0x609B60CC, +0xE2E901FA, 0x25BE9B93, 0xDF96D9BC, 0x86D415DF, +0x75CCF6BB, 0x882D54B2, 0x7976E9AF, 0x88A0B178, +0x5ADE5A55, 0x8A8C0112, 0xD896755A, 0xCB6789B3, +0x8B63AE2F, 0x2545036C, 0xE4655B94, 0x20959977, +0x29DFB4D1, 0xCDAAEBF4, 0x1C07EC05, 0x5A6F607D, +0x88A9B31D, 0x118C74D2, 0x000BB065, 0x75C46712, +0xEF1A58BD, 0x50ECA262, 0xCCE393B9, 0x6EDB92E8, +0x700EF517, 0xBF6CF4AD, 0x57456DC0, 0xF629517C, +0x40331F8B, 0xC10A454D, 0x6CCB02CF, 0x9BF11B1C, +0xE0871437, 0x23623585, 0xF519F09C, 0x4DB2AFC8, +0x88FCBD7B, 0xB512FE8D, 0xDE445894, 0x078AD03C, +0x44375FB0, 0x0BABEDB1, 0x40D5E8E1, 0x13F20A86, +0xF1406303, 0x7205C322, 0x3FC43779, 0x7A60D510, +0x14469E04, 0xF4E77873, 0x2EAD7ECE, 0xA135D6EA, +0x3F4C4B30, 0x21488077, 0x69F64F1C, 0xEEF4876E, +0x63610C0B, 0xB7B24C5C, 0x324A76FE, 0x0CF651D3, +0x9460F0B1, 0x81A83230, 0x0839CFF9, 0x70722F04, +0xC278FB3B, 0x5DD1BDA4, 0x1E4B3DBA, 0xAE161A93, +0x9E1033C3, 0xD938FCEC, 0xDA2B2F93, 0x28CD82EA, +0x14AD1FAF, 0xE4EC9CB8, 0xE770AFDF, 0xEFB12898, +0x500BE181, 0x602625C5, 0xF160631B, 0x78D3643F, +0x4E13ED37, 0x647BB223, 0xCF18D75C, 0xF477F94C, +0x786ECB89, 0xB3ED21F8, 0x1BEF3916, 0x240FB35A, +0x5C69B7D9, 0x8E96290A, 0xD40DC98C, 0xD1370291, +0x5870021E, 0x3F7CF23F, 0xFD4A6ADA, 0x36482457, +0x926600AF, 0xDC8618BC, 0x67D3779F, 0x3422830C, +0x87A41FBA, 0xCA0AFF53, 0x63BC45F3, 0x520BBBAE, +0xEDE2E031, 0xB6FA9450, 0x258CA712, 0xD709C4E4, +0x617709B2, 0xAACE0B41, 0x363DBF55, 0x701D6583, +0x39F3C885, 0x7CD6297B, 0x078FE13B, 0xA398DABF, +0xDB97C514, 0x039102E3, 0x5CA545AF, 0x9298BA18, +0xD18DAF86, 0x3D70EEA2, 0x5266AD68, 0xB04945B5, +0x402DDA5B, 0x01DC6CD1, 0x93AC5053, 0x08DF9EA9, +0x485EBE97, 0xA5D05853, 0x6CBEE910, 0xD485F4E2, +0x8F201D07, 0xEFC384A3, 0x7272AFBE, 0xC0B41FD7, +0x8E54A971, 0xA7F9E0F7, 0xC21700B4, 0xC24A4ED0, +0x5419EACF, 0xBC2D8FB1, 0x2C5B5AFF, 0x0345274C, +0xC41DF47A, 0x37658AFF, 0x24CF3BE7, 0xA3086248, +0xF82B5928, 0xB49A9B04, 0xD4105AEF, 0x444EBE8D, +0x348368DF, 0xDC77A7A0, 0x68D37E0D, 0xD2EB54EE, +0xDDAC8C33, 0xE5C93C79, 0xE4706ABF, 0x17536EFD, +0x6C2B2B16, 0x038AA806, 0xDAD42458, 0xAE1D76A1, +0xCC8DE95C, 0x1BA20647, 0x0521068C, 0x306FBE44, +0x4E29D881, 0xD2A14D53, 0xA155853E, 0x44500CC4, +0xFC4466B7, 0x5AACD51D, 0x506D3A73, 0x3F61E0FE, +0x58F11F9D, 0xC92A2CAD, 0xD9A4F86B, 0x1FA747B1, +0x77DEC5D2, 0xDFAB369A, 0xD471EA01, 0x724502DA, +0x618CE21A, 0x52388BEB, 0x2E8A4CC5, 0x58332211, +0x3FCC46E1, 0x501210E2, 0xE9D51D1A, 0x37237B55, +0x8CE3E2F1, 0x6B2E98CC, 0xB56A11E5, 0x8819036B, +0xA6AA2F27, 0xB0124A0E, 0x92F17364, 0xD4A89238, +0x0507E337, 0x8ED95DEC, 0x9C014BA8, 0xBA5B11C6, +0x9C15D38C, 0x52596C98, 0x9330DD3D, 0xD6147570, +0x21701F1B, 0x5A2385F1, 0xE2F38C6C, 0xB3E94698, +0x2F9C63FA, 0x7E0234D8, 0x4CDD3288, 0xE1969B5F, +0x853B3C1D, 0xF61465A7, 0xF281C419, 0x46C5F072, +0x9F1722DD, 0x64F2A994, 0x86AEE8A8, 0x55895E17, +0x6047D1AC, 0x3375A934, 0x336BEACA, 0x90791174, +0x4DACC4D2, 0x24253860, 0x2A7876FB, 0x9DBDF98D, +0xD5BCE182, 0x67EB5F70, 0xCC06BA38, 0xE8F78715, +0xFEB0EB44, 0xE9776E03, 0x892A0898, 0x7A070650, +0x6D04DDC4, 0x99A5B7EA, 0x3B416BB6, 0xDADCE834, +0xB3B03278, 0xDB73B70E, 0xB0F0224E, 0x538A4AF9, +0xD25D6A37, 0x8F627FB0, 0x11ED9387, 0xB8C88457, +0x0CF320CA, 0xA20E62A2, 0x1DACDD4A, 0xAB84575D, +0x740DAF75, 0xAB9DB955, 0xFF787314, 0xA680B8E3, +0xC976D38E, 0x1FD38F4D, 0x0AEB6633, 0xB69A03DF, +0xB6CA8610, 0x106354C2, 0xC37D48C8, 0x3E5EED54, +0x534CC9BA, 0xE37DFFAD, 0x9F69EB05, 0xF67217EE, +0x50180B3D, 0xCC61C127, 0xC3598D73, 0xE5C00F01, +0xFFE9B111, 0x5E23EA2F, 0xF6C45DCE, 0x44585E39, +0xB02C6004, 0x37233902, 0x4F374C0D, 0x34288898, +0xE274937D, 0xC81D472C, 0x17A43151, 0x2638F7D3, +0x5304E5B5, 0xD5CE5EDE, 0x357FA7B3, 0xFBE27986, +0x64E65D1F, 0xC28D1237, 0xA73D9AB3, 0x124CA6C8, +0x770D7415, 0x5788C32C, 0x18DEFC00, 0xB3B2B06A, +0x55CC86A0, 0x8D929309, 0x84AB381A, 0x9DEFE8DD, +0x26C742C8, 0x952BAC34, 0x0A3B140F, 0x82A9304B, +0x52CEC9F4, 0x47DF4D08, 0x15A116D8, 0x7B890B18, +0xC87BEF1A, 0xB59601B6, 0xD37BFB28, 0x5D9F564D, +0xFB002F8D, 0xE7602E57, 0xE429C852, 0x9C0A8C75, +0xE02611DC, 0x8A1C9861, 0x7495D6DE, 0xCA059710, +0xAE5969B8, 0xE5B2CBDC, 0xA49F6EC1, 0x85D2A553, +0xE4719B0F, 0x40F68BBC, 0x092E24B5, 0x7B132678, +0xD70C17E1, 0x309E6AA1, 0xE009657F, 0xA7238C7A, +0xE0575D78, 0x1D6980E7, 0xEFCDD368, 0x19F08D93, +0xFAC03B85, 0x51BADA8F, 0x037DF839, 0x8F4D29F4, +0x1DC8A913, 0x50C55402, 0xDEE578F0, 0x2BA1C091, +0x9ACA567E, 0xA8FFECFA, 0xA3C05D12, 0xF18C6283, +0xEAAE6662, 0xB4DC6A79, 0xCEC5E782, 0x93A2E384, +0x8F8A5E6F, 0xCA8379D5, 0x81BCD49E, 0x5FCE174B, +0xD1543A5B, 0x845D635F, 0xD53125B9, 0x3B2121AE, +0xF8ECDD01, 0xF84D2D11, 0x6579BC21, 0x5C2DC220, +0x9EC1A688, 0x1148D831, 0x6C087799, 0x58944357, +0x56F79FC6, 0x6B689B55, 0x740B5FD1, 0x9F7BFB5F, +0x6B2F3E2D, 0x10E09273, 0x2E9E3213, 0xF3436AA0, +0x14A9F681, 0x9087D3CE, 0x68D0430B, 0x9FAFE3EF, +0xD45B8C61, 0xB982724A, 0x04448D7F, 0x8712E47A, +0x2C188D15, 0x9C3F06CC, 0x6343B130, 0x56C6765C, +0xF657BC9A, 0x15F1E973, 0x47E71181, 0x8639F5D7, +0xC1F3FDD5, 0xDC522441, 0x56BB2908, 0xAA48AEC6, +0xEC04087A, 0x8D375875, 0xE2941F88, 0xED31CC72, +0x09BD8794, 0x4C81D5C1, 0x1CC96D9C, 0x98A89022, +0xAA362C57, 0x924D583D, 0x270430E6, 0x0FD4040A, +0xAF561155, 0x38DCD1CF, 0xE861D2AC, 0x24A2EF3C, +0x2B7E3868, 0x13DA6C12, 0x69202EB6, 0x4A5FEC66, +0x185417A9, 0x3C92EFF4, 0x949842E6, 0x02115D93, +0xAD1726FF, 0x4E093D7D, 0xC3E41B9C, 0x27BBC1C1, +0x4FFA49C7, 0x6C63D24C, 0x84255444, 0x282C3BA2, +0x3D679D86, 0x03B410B1, 0x64DB454C, 0x535499D4, +0x25B421A1, 0x7E68C8FE, 0x0477E3B9, 0xCEFB087D, +0x9E59B89C, 0xBB787559, 0x1A550EE4, 0x078B48AB, +0x73A865FE, 0xD7227471, 0x3A864049, 0xE5EE3A1D, +0x201BC19D, 0xEB8DAE2C, 0x0E2AB31D, 0xCDAC2D79, +0xDAAB08B1, 0x63ECD4F2, 0xC00F9716, 0xD415C6BB, +0x8C20C39F, 0xDED8F5A2, 0x1D6A4190, 0x3D319167, +0x56B3A26B, 0x0547BF52, 0xA056924F, 0x4DAA539A, +0x557241D1, 0x42C9124E, 0x18723323, 0x6AD6E7EC, +0x8E039337, 0xF6FDDD65, 0x5F3525F9, 0xC0AD9704, +0x810EF049, 0xCE022EE0, 0x41CE7E52, 0x8E172A44, +0x648808E2, 0xC7FF6896, 0x2AD0985C, 0x304B9631, +0xD21EA39B, 0x279F5089, 0xCDB5C390, 0x21716A40, +0x5E34B278, 0x39475D72, 0xBA4F4DB1, 0x8B25818F, +0xE6E466F4, 0xC4A09DF8, 0x59F18AC7, 0x887AB5FE, +0xEEA4BA42, 0x17371DA8, 0xA82193D1, 0x6DC30EF7, +0xDEB9D349, 0x2B3271D4, 0x1FE83836, 0xEC755A29, +0x05F07FCD, 0xC331D3AE, 0xC6208B76, 0x497FF280, +0x4C579C5A, 0x22B71F94, 0x30FD620B, 0x31B71AE3, +0xDF7D1A41, 0xF041ACA5, 0x9533261B, 0x3262D291, +0x060E9672, 0x7D191A55, 0x6D0F0945, 0xF8C7777C, +0x1C173808, 0x78308E77, 0xC1EEAD3B, 0x059CCD9D, +0xA8FDBE19, 0xE47630FA, 0x88A49DE5, 0x03347DAB, +0x4F31F969, 0xF9C62B12, 0x93AB126F, 0x8A7A3BFB, +0x82591545, 0x2A1A2131, 0x1DEBB134, 0x449E28DD, +0xFA7E0248, 0xC1E3A5BC, 0x1747E097, 0x4C69AA5C, +0x1FD71B4B, 0xAC64CA6C, 0x5545F9F9, 0x5E5886F2, +0x243DBA6C, 0x495BE163, 0x4ECF5A6C, 0x430C9019, +0x89A980FA, 0x528945AE, 0x00CE6936, 0x9F9A73B2, +0x9E59DC6B, 0xD57740CD, 0x0E0CB735, 0xB1202BE3, +0xAA26C2A9, 0x267A77A6, 0x3FA12CF0, 0x4587C0AF, +0x354ED831, 0xFFD8BD8E, 0x56CC0F26, 0x75717AE3, +0x51B10674, 0x3E33EC26, 0x26CE80DB, 0x5C4A9140, +0x017F6C2F, 0xF9038D9A, 0x0A22C29F, 0xBA1F7C8D, +0x125CC934, 0x6CF66BFF, 0x48C13DCD, 0x63FC3D81, +0x258C181D, 0x1A4C3DDD, 0x2E24BECC, 0x7C86A9ED, +0x5BD1989C, 0x57CE595C, 0xDF291AFE, 0xEAF00887, +0xD8DD4259, 0xDF67331E, 0x50D0CE88, 0x1FD090AE, +0x632DA5F0, 0x95272A5B, 0x31172F25, 0x547FD7DF, +0xAFBE11D9, 0x97189DFC, 0xC4881191, 0x1C92365D, +0x843DEFDE, 0xCF0A399B, 0xCF327CAF, 0xDDAF0BCE, +0x03AA7A2E, 0x411A8664, 0x6CCF7CD9, 0x61097EF5, +0x07F3941E, 0x5BC3EB75, 0x2791945F, 0xBEBB526E, +0x18631A34, 0x25FEBF10, 0x419834CF, 0xF642D176, +0x372FFF10, 0x2A1BEA1B, 0x400FF345, 0x257A234A, +0x9F15E99D, 0xE06AA1DB, 0x3A0DB315, 0x2BA30D99, +0x0E9E831E, 0x1B25EE41, 0x8DB30E70, 0x9FBA6D64, +0xAB8AA5E3, 0x5A96177A, 0x6BE03535, 0x97E37DCE, +0xACA24F26, 0x5F0096F7, 0x5D02722F, 0xAF8F3EC7, +0xA6824151, 0x70FAD406, 0xDEBA8513, 0x99C63E34, +0x1CC4A3DF, 0x7F756508, 0xB7386527, 0x647C7FB8, +0x43F1F4DF, 0xC7E4EC18, 0x302BA109, 0xD5E9175B, +0x82856F77, 0x0F6D45D9, 0x95AE28B9, 0xE63385C3, +0x8FB26619, 0xBD99F298, 0xC884B948, 0x0B596FF1, +0xE061C3F9, 0xBC2F9A81, 0xC488CD91, 0x372EF590, +0x3DA1BFE5, 0x10DE037B, 0x7210B4DC, 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0x56342562, 0x752C6543, +0x55332562, 0x72306243, 0x55352252, 0x72346243, +0x56362252, 0x24627438, 0x1341E400, 0x17412742, +0x17451742, 0x17461743, 0x23421342, 0x13441744, +0x13451343, 0x1346000B, 0xD510E124, 0x51572410, +0x52581411, 0x57591422, 0x515A1473, 0x525B1414, +0x575C1425, 0x525D1476, 0x1427E700, 0x1468565E, +0x1469565F, 0x15781577, 0x157A1579, 0x157C157B, +0x157E157D, 0x157F000B, 0x001C369C, 0x0020351C, +0x00203578, 0x001C3CA0, 0x001C36F4, 0x001C3B88, +0x6E726157, 0x21676E69, 0x69685420, 0x6F642073, +0x656C676E, 0x746F6E20, 0x65656220, 0x6163206E, +0x7262696C, 0x64657461, 0x0000000A, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, 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0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +const u32_t zcFwBufImageSize=83968; diff --git a/drivers/staging/otus/hal/hpfwspiu.c b/drivers/staging/otus/hal/hpfwspiu.c new file mode 100644 index 000000000000..eda7ff5e573c --- /dev/null +++ b/drivers/staging/otus/hal/hpfwspiu.c @@ -0,0 +1,655 @@ +/* + * Copyright (c) 2007-2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include "../80211core/cprecomp.h" + +const u32_t zcFwImageSPI[]={ +0x0009000B, 0x4F222FE6, 0xB0187FFC, 0xE6000009, +0x943DD520, 0xC8406052, 0x2F028F03, 0x8FF93642, +0xD41D7601, 0x4E0BDE1D, 0xD41D0009, 0x00094E0B, +0x4E0BD41C, 0x7F040009, 0xA0214F26, 0x4F226EF6, +0xE205D119, 0x2122E400, 0x92222142, 0x8BFD4210, +0x450BD516, 0xD6160009, 0x0009460B, 0xE5FFD715, +0x2752655D, 0xE1FFD714, 0xD4145079, 0x1709CB01, +0x17112712, 0x2412E101, 0x4F26D411, 0x2410000B, +0xDE11DD10, 0x00094D0B, 0x00094E0B, 0x0009AFFA, +0x03E82710, 0x001C001C, 0x00116594, 0x00114EBE, +0x001165A4, 0x001165BC, 0x001D4004, 0x00114FA0, +0x00114378, 0x001C3510, 0x001C3624, 0x001E212C, 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0x001164F5, 0x001164F4, 0x001164F6, +0x0011611C, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x544F0D0A, 0x53205355, 0x46204950, +0x00003A57, 0x2074634F, 0x32203220, 0x20373030, +0x333A3831, 0x36343A32, 0x00000000, 0x00000D0A, +0x42707372, 0x3D206675, 0x554E203D, 0x202C4C4C, +0x6E49677A, 0x4E497274, 0x6D754E51, 0x0000003D, +0x52504545, 0x57204D4F, 0x65746972, 0x6461202C, +0x003D7264, 0x6C617620, 0x0000003D, 0x00000A0D, +0x5A205746, 0x4D435F4D, 0x4C465F44, 0x5F485341, +0x53415245, 0x000A0D45, 0x5A205746, 0x4D435F4D, +0x4C465F44, 0x5F485341, 0x534B4843, 0x0A0D4D55, +0x00000000, 0x2D495053, 0x72646461, 0x0000003D, +0x2D495053, 0x676E656C, 0x003D6874, 0x2D495053, +0x736B6863, 0x003D6D75, 0x5A205746, 0x4D435F4D, +0x4C465F44, 0x5F485341, 0x44414552, 0x00000A0D, +0x61202072, 0x3D726464, 0x00000000, 0x72202020, +0x75427073, 0x00003D66, 0x6E6B6E55, 0x206E776F, +0x6D6D6F63, 0x3D646E61, 0x00000000, 0x00000072, +0x00205220, 0x00000D0A, 0x62735576, 0x7473725F, +0x00000A0D, 0x62735576, 0x7375735F, 0x646E6570, +0x00000A0D, 0x62735576, 0x7365725F, 0x000A0D6D, +0x72746E49, 0x6D652051, 0x2C797470, 0x49677A20, +0x4972746E, 0x754E514E, 0x00003D6D, 0x654C7245, +0x0000006E, 0x20746F4E, 0x756F6E65, 0x49206867, +0x4220514E, 0x0A0D6675, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x002E0209, 0x80000101, +0x000409FA, 0x00FF0400, 0x05070000, 0x02000201, +0x82050700, 0x00020002, 0x03830507, 0x07010040, +0x40020405, 0x02090000, 0x0101002E, 0x09FA8000, +0x04000004, 0x000000FF, 0x02010507, 0x07000040, +0x40028205, 0x05070000, 0x00400383, 0x04050701, +0x00004002, 0x00000000, 0x00000000, 0x07090000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, }; + +const u32_t zcFwImageSPISize=10156; diff --git a/drivers/staging/otus/hal/hpfwu.c b/drivers/staging/otus/hal/hpfwu.c new file mode 100644 index 000000000000..2b77cbacc6d6 --- /dev/null +++ b/drivers/staging/otus/hal/hpfwu.c @@ -0,0 +1,1017 @@ +/* + * Copyright (c) 2007-2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include "cprecomp.h" + +const u32_t zcFwImage[] = { +0x0009000B, 0x4F222FE6, 0xDE947FFC, 0xE114D594, +0x1E13D494, 0x67521E4C, 0xD494D693, 0x37402769, +0x62528F06, 0x7201D692, 0x60602522, 0x2600C93F, +0xD7906152, 0x2512611D, 0x264B6652, 0x2562470B, +0x0009B017, 0xE60095AC, 0xC84060E2, 0x2F028F03, +0x8FF93652, 0xD4887601, 0x4E0BDE88, 0xD4880009, +0x00094E0B, 0x4E0BD487, 0x7F040009, 0xA0524F26, +0x4F226EF6, 0x410BD184, 0xD4840009, 0x0009440B, +0x450BD583, 0xD7830009, 0xD283E1FF, 0x2712611D, +0xD4825029, 0xE1FFCB01, 0x1209E501, 0x12112212, +0xE7202452, 0x4718D57E, 0x2572D27E, 0xD17EE700, +0xD67FD47E, 0xE2012270, 0x24702172, 0xD67D2620, +0x2641E4FF, 0xD57CE600, 0x666DE104, 0x76016063, +0x4000626D, 0x8FF83212, 0xD5780545, 0x2520E201, +0xD278D777, 0xE480E100, 0x22122710, 0x6613D576, +0x666D644C, 0x76046763, 0x375C626D, 0x8FF83243, +0xD5722712, 0xD273D772, 0xE400E101, 0x27102511, +0x000B4F26, 0x7FCC2242, 0xD170D56F, 0xD271DB70, +0x1F51D471, 0xD6717508, 0x1F12D771, 0x1F55710C, +0x1FB975FC, 0x72041F2A, 0x1F13EB10, 0x1F561F44, +0x1F781F67, 0xD86B1F2B, 0xDD6CD96B, 0xDC6CEA00, +0xD26DDE6C, 0x89003A22, 0xD15D7A01, 0x88016010, +0x56F88B03, 0x4218E201, 0xD1682622, 0x0009410B, +0x440BD467, 0xD5670009, 0x0009450B, 0x6010D150, +0x8B108801, 0xE650D14F, 0x46186212, 0x8B083266, +0x56F9D14B, 0x2120E200, 0xCB016062, 0x2602A003, +0x72012710, 0x60822122, 0x89098801, 0xE2C8D15A, +0x622C6612, 0x89033626, 0x6010D158, 0x8BC88801, +0x51F66792, 0x217252F5, 0xD6555191, 0x55FA2212, +0x52FB6462, 0x55612542, 0x2252E400, 0x61436643, +0x05DE6013, 0x36CC4608, 0x07DE2652, 0xC9036071, +0x8B028801, 0x720162E2, 0x74012E22, 0x36B3664C, +0x71048FEE, 0x66C2D147, 0x45286512, 0x265B4518, +0x60822C62, 0x89018801, 0x0009A168, 0x6272D742, +0x8B132228, 0xD42BD741, 0x6772D541, 0x51536242, +0x312C327C, 0x24222228, 0x15138D05, 0x6262D63D, +0xB1627201, 0xD6232622, 0x2622E200, 0x52916692, +0x8B013620, 0x0009A144, 0x6061A06E, 0x001C001C, +0x001D4020, 0x0000B38E, 0xFFFF0000, 0x12340000, +0x001E1015, 0x00201274, 0x002039F4, 0x002018A2, +0x00203A00, 0x00203A18, 0x00201860, 0x0020196C, +0x00201288, 0x001C3510, 0x001C3624, 0x001E212C, +0x002038F4, 0x0020348C, 0x002038FC, 0x00203908, +0x00203914, 0x00203970, 0x00203974, 0x0020391C, +0x0020391D, 0x00203920, 0x00117700, 0x0020398C, +0x0020398A, 0x002034F0, 0x00117710, 0x001C3D30, +0x001C36F8, 0x00117734, 0x001C3684, 0x001C3D00, +0x001C1000, 0x001C1028, 0x00203504, 0x00203924, +0x00117600, 0x00117740, 0x7FFFFFFF, 0x00201730, +0x0020332A, 0x00202334, 0x00203DA4, 0x00203972, +0x002034FC, 0x00203964, 0x001C3D2C, 0x001C36B0, +0x00203494, 0x0011775C, 0x8801C90F, 0xA0CF8901, +0xD1960009, 0x36206212, 0xD4958904, 0x2421E200, +0x2162A0CC, 0x6211D193, 0x89012228, 0x0009A0C3, +0xE202D78F, 0x75016571, 0x3123615D, 0x27518D02, +0x0009A0BC, 0xD28C57F2, 0x62226072, 0x40094019, +0xC90F4009, 0x8F19880A, 0x52F31F2C, 0x40196022, +0x40094009, 0x8808C90F, 0xA0A78901, 0x60630009, +0xCB0154F7, 0xD27E55F2, 0xE7012402, 0xD47FE100, +0x22112572, 0x72016242, 0x2422A098, 0x8B3F8805, +0x602252F3, 0x40094019, 0xC90F4009, 0x8B168802, +0xE4FFD577, 0x644D6752, 0x8B102748, 0x6272D775, +0x8B0C3260, 0x51F255F7, 0xD26DE701, 0x21722562, +0xD571E100, 0x64522211, 0xA0777401, 0x52F32542, +0x40196022, 0x40094009, 0x8805C90F, 0x31B38B6E, +0xD26A8B6C, 0x672254F4, 0x7701D569, 0x61422272, +0x1F1CE640, 0x46182159, 0x8B033160, 0x6262D665, +0x26227201, 0xE200D65A, 0x2621B067, 0x0009A056, +0x3123E220, 0x88038B52, 0x52F38B1E, 0x40196022, +0x40094009, 0x8803C90F, 0xD25B8B16, 0x672254F4, +0x7701D557, 0x61422272, 0x1F1CE640, 0x46182159, +0x8B033160, 0x6262D655, 0x26227201, 0xE200D648, +0x2621B043, 0x0009A010, 0xD452D551, 0xD2446752, +0xE1007701, 0x25723A46, 0x22118F06, 0xEA00D64E, +0x72016262, 0x2622B031, 0x2FB2D54C, 0x95736652, +0xD44A5BF1, 0x36205241, 0x60618910, 0x8B01C803, +0x2B22E201, 0x8FF54510, 0x57F15664, 0x6272E1F0, +0x41284118, 0x2722221B, 0x6BF2A008, 0x6BF2A006, +0xE200D62F, 0xD12F2621, 0x2121E200, 0xD13CE201, +0x66122822, 0x8B012668, 0x0009AE2B, 0x450BD539, +0xD1390009, 0xAE24E600, 0x2F862160, 0x2FA62F96, +0x2FC62FB6, 0x2FE62FD6, 0x7FF44F22, 0xDE34D133, +0x54116212, 0x1F4167E2, 0x2F22D432, 0xD5321F72, +0xD2326743, 0x58417794, 0x69425A42, 0x5B166C72, +0x60526D22, 0xCB20E600, 0xE5402502, 0x626D7601, +0x8BFB3253, 0x55F162F2, 0x11512122, 0xD62855F2, +0x14812E52, 0x249214A2, 0x27C2D426, 0x26D211B6, +0xDA256742, 0xE801D925, 0x490B2A72, 0xE2011A8C, +0x1A2C4218, 0x4F267F0C, 0x6DF66EF6, 0x6BF66CF6, +0x69F66AF6, 0x68F6000B, 0x000007D1, 0x00203984, +0x00203988, 0x0020398E, 0x001C3DC0, 0x0011772C, +0x001C3B88, 0x0020396C, 0x0011773C, 0x00117744, +0x0000F000, 0x00117764, 0x00117748, 0x00117768, +0x0011776C, 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+0xC8016063, 0xDB5ED15D, 0x967D8901, 0xE6002C6B, +0x666C67CD, 0x40006063, 0x622D021D, 0x8D0E3270, +0x60436403, 0xE9FF021D, 0x8B013290, 0x01C5A007, +0x626C7601, 0x3292E904, 0x646C8BEB, 0x60434400, +0xD15004BD, 0x0B457401, 0x669D6911, 0x89073670, +0x602D6211, 0x890388FF, 0xE201DB4B, 0x2B2021C1, +0xECFC8551, 0x815120C9, 0xCB016051, 0xDC472501, +0x64A34C0B, 0x51F366F2, 0x85EF2612, 0x54F2D244, +0x650D420B, 0x0009ADE7, 0xE500DC42, 0x420B2C52, +0x4E0B64A3, 0x54036403, 0x85446E03, 0x6703E908, +0x65034918, 0x27998541, 0xDB323790, 0x8F0BD932, +0x6013610D, 0x8B07C820, 0xC9486053, 0x8B038808, +0xE501BD4D, 0x0009A005, 0x2128D233, 0xBD468901, +0x64B3E500, 0x490B65E3, 0xADBCEC01, 0x85F22DC2, +0x7001EE04, 0x31E7610D, 0x8D0281F2, 0xADA97A08, +0x7F140009, 0x6EF64F26, 0x6CF66DF6, 0x6AF66BF6, +0x000B69F6, 0xF7FF68F6, 0x2FE68000, 0xD2234F22, +0x60E36E22, 0x8D02C840, 0xBBF922E2, 0xE2400009, +0x2E284218, 0xBC048901, 0x60E30009, 0x8905C810, +0xD21CD41B, 0x0009420B, 0x0009BC03, 0xC80560E3, +0xBD6D8901, 0x60E30009, 0x8902C802, 0xAC004F26, +0x4F266EF6, 0x6EF6000B, 0x001C3D3C, 0x00117760, +0x002014A0, 0x0020166C, 0x00203494, 0x00203DA4, +0x00203908, 0x002034FC, 0x002014CC, 0x00203974, +0x0020397C, 0x00203970, 0x00203972, 0x00201530, +0x002018EE, 0x00203994, 0x00008000, 0x001C3510, +0x00203D98, 0x002018A2, 0x080A0C0E, 0x00020406, +0x1A1C1E20, 0x12141618, 0x2E303234, 0x26282A2C, +0x3A3C3E40, 0x6C625648, 0x41112F26, 0xE2208F18, +0x890B3123, 0x321CD204, 0xD1026220, 0x412B312C, +0x00090009, 0x00203412, 0x002033C8, 0x000BE000, +0x400062F6, 0x40004000, 0x40004000, 0x40004000, +0x62F6000B, 0x40004000, 0x40004000, 0x40004000, +0x40184000, 0x62F6000B, 0x40004000, 0x40004000, +0x40004000, 0x40284000, 0x62F6000B, 0x40004000, +0x40184000, 0x000B4028, 0xC90F62F6, 0x40054005, +0x40054005, 0x62F6000B, 0x4005C907, 0x40054005, +0x62F6000B, 0x4005C903, 0x000B4005, 0xC90162F6, +0x000B4005, 0x000062F6, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x544F0D0A, 0x46205355, 0x00003A57, +0x206C754A, 0x32203120, 0x20383030, 0x323A3132, +0x34333A38, 0x00000000, 0x00000D0A, 0x00000043, +0x42707372, 0x3D206675, 0x554E203D, 0x202C4C4C, +0x6E49677A, 0x4E497274, 0x6D754E51, 0x0000003D, +0x61766E49, 0x2064696C, 0x72657375, 0x20726F20, +0x2079656B, 0x00214449, 0x52504545, 0x57204D4F, +0x65746972, 0x6461202C, 0x003D7264, 0x6C617620, +0x0000003D, 0x00000A0D, 0x435F4D5A, 0x465F444D, +0x4C445F57, 0x494E495F, 0x00000054, 0x6E6B6E55, +0x206E776F, 0x6D6D6F63, 0x3D646E61, 0x00000000, +0x203A3051, 0x00000020, 0x203A3151, 0x00000020, +0x203A3251, 0x00000020, 0x203A3351, 0x00000020, +0x203A3451, 0x00000020, 0x2B434741, 0x73696F4E, +0x61432065, 0x7262696C, 0x6F697461, 0x6166206E, +0x6F206C69, 0x6974206E, 0x0D0A656D, 0x00000000, +0x00000072, 0x00205220, 0x00000D0A, 0x62735576, +0x7473725F, 0x00000A0D, 0x62735576, 0x7375735F, +0x646E6570, 0x00000A0D, 0x62735576, 0x7365725F, +0x000A0D6D, 0x00000044, 0x44387570, 0x72637365, +0x6F747069, 0x3D584572, 0x00000000, 0x00000047, +0x00000042, 0x72746E49, 0x6D652051, 0x2C797470, +0x49677A20, 0x4972746E, 0x754E514E, 0x00003D6D, +0x654C7245, 0x0000006E, 0x00000049, 0x20746F4E, +0x756F6E65, 0x49206867, 0x4220514E, 0x0A0D6675, +0x00000000, 0x000000FF, 0x00020001, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x010E010D, 0x00020003, 0x01090108, +0x0002010A, 0x02000003, 0x02020201, 0x02040203, +0x02060205, 0x02020200, 0x02040203, 0x020C020B, +0x020E020D, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x000000FF, 0x00020001, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x010E010D, 0x00020003, 0x01090108, +0x0002010A, 0x00030003, 0x02020201, 0x02040203, +0x02060205, 0x02020200, 0x02040203, 0x020C020B, +0x020E020D, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x010E010D, 0x00FF010F, 0x01090108, +0x010B010A, 0x0200010F, 0x02020201, 0x02040203, +0x02060205, 0x02020200, 0x02040203, 0x020C020B, +0x020E020D, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x010E010D, 0x00FF010F, 0x01090108, +0x010B010A, 0x010F010F, 0x02020201, 0x02040203, +0x02060205, 0x02020200, 0x02040203, 0x020C020B, +0x020E020D, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00205220, 0x00000046, 0x00000059, +0x73204142, 0x003D7165, 0x49544120, 0x0000204D, +0x00000000, 0x00000000, 0x002E0209, 0x80000101, +0x000409FA, 0x00FF0400, 0x05070000, 0x02000201, +0x82050700, 0x00020002, 0x03830507, 0x07010040, +0x40030405, 0x02090100, 0x0101002E, 0x09FA8000, +0x04000004, 0x000000FF, 0x02010507, 0x07000040, +0x40028205, 0x05070000, 0x00400383, 0x04050701, +0x00004002, 0x00000000, 0x00000000, 0x07090000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +const u32_t zcFwImageSize=15936; diff --git a/drivers/staging/otus/hal/hpfwu.c.drv_ba_resend b/drivers/staging/otus/hal/hpfwu.c.drv_ba_resend new file mode 100644 index 000000000000..7f5bcff57b59 --- /dev/null +++ b/drivers/staging/otus/hal/hpfwu.c.drv_ba_resend @@ -0,0 +1,742 @@ +/* + * Copyright (c) 2007-2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include "cprecomp.h" + +const u32_t zcFwImage[] = { +0x0009000B, 0x4F222FE6, 0xDE297FFC, 0xE114D729, +0x1E13D429, 0x1E4C470B, 0x0009B018, 0xA0039545, +0x3652E600, 0x76018D04, 0xC84060E2, 0x2F028DF9, +0xDE23D422, 0x00094E0B, 0x4E0BD422, 0xD4220009, +0x00094E0B, 0x4F267F04, 0x6EF6A024, 0xD11F4F22, +0x0009410B, 0x440BD41E, 0xD51E0009, 0x0009450B, +0xE1FFD71D, 0xD21D611D, 0x50292712, 0xCB01D41C, +0xE501E1FF, 0x22121209, 0x24521211, 0xD61AD519, +0xE2009714, 0xD4192572, 0xD6192620, 0x4F262422, +0x2622000B, 0xDD18DC17, 0x4C0BDE18, 0x4D0B0009, +0x4E0B0009, 0xAFF80009, 0x27100009, 0x00000640, +0x001C001C, 0x00200BC4, 0x0000B38E, 0x002029F8, +0x00200F72, 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0xE40284F4, 0xBF007090, 0xE6406503, +0xBF01E402, 0xE640E500, 0xBF0EE402, 0xE640E500, +0xBF16E402, 0xE5FEE500, 0x6053655C, 0xBEE3E403, +0xE51380F8, 0xE40EBEE6, 0xE40E84F8, 0xBEE67085, +0xE5006503, 0xBEE7E640, 0xE500E403, 0xBEF4E640, +0xE500E403, 0xBEFCE640, 0xE5FFE403, 0x6053655C, +0xBEC9E404, 0xE40F80FC, 0xE504BECC, 0xE40F84FC, +0xBECC7083, 0xE5016503, 0xBECDE640, 0xE501E404, +0xBEDAE640, 0xE501E404, 0xE404E640, 0xAEE07F10, +0x7F104F26, 0x000B4F26, 0x00000009, 0x001E1030, +0x001E1080, 0x001E1090, 0x001E103F, 0x001E103E, +0x002029DA, 0x002029DC, 0x002029DE, 0xD21DD11C, +0x66206010, 0x676C7001, 0x3700C90F, 0xE5008D13, +0x67106210, 0x7701622C, 0x64232170, 0xD6166010, +0x44084408, 0x3428C90F, 0x62602100, 0x7201D513, +0x44082620, 0x000B354C, 0xD10F6053, 0x25586510, +0xE6008D13, 0xD60DD40B, 0x655C6540, 0x47086753, +0x37584708, 0x47086540, 0x24507501, 0x367C6040, +0x2400C90F, 0x72FF6210, 0x000B2120, 0x00006063, +0x002029AF, 0x002029AE, 0x002029B0, 0x002025D4, +0x7FFC4F22, 0xE680D19D, 0x666C6212, 0xD29C2F22, +0x67F36563, 0x420B7542, 0x7F04E404, 0x000B4F26, +0xE6800009, 0xD296666C, 0xE7006563, 0x422B7540, +0xE6806473, 0xD292666C, 0xE7006563, 0x422B7543, +0x2FB66473, 0x2FD62FC6, 0x4F222FE6, 0x4D18ED01, +0xDB8DDC8C, 0x65C252C1, 0x89203520, 0xC9036051, +0x891C8801, 0xD189DE87, 0x64E3410B, 0x85036503, +0x670D66B2, 0x89073762, 0xD286D485, 0x0009420B, +0xE701D185, 0x2172AFE6, 0xDE8464E3, 0x00094E0B, +0xD484D683, 0x410BD184, 0xAFDB26D2, 0x4F260009, +0x6DF66EF6, 0x000B6CF6, 0x4F226BF6, 0x85467FF4, +0x2F01E681, 0x666C8547, 0x854881F1, 0x81F2D270, +0x67F38542, 0x854381F3, 0x81F4E40C, 0x65636053, +0x420B81F5, 0x7F0C7540, 0x000B4F26, 0x2F860009, +0x2FA62F96, 0x2FC62FB6, 0x2FE62FD6, 0x7FF44F22, +0xDC6EE200, 0x2F21A136, 0xDD6D6A13, 0xE0014A08, +0x4D0BD96C, 0x3A9C4A00, 0x1F917930, 0x66C21F02, +0x362052C1, 0xA1218B01, 0x60610009, 0x8801C903, +0xA11B8B01, 0x85610009, 0x8977C801, 0x85D25D63, +0xC9036603, 0x85D36403, 0x6053650D, 0x40214021, +0x4500C93F, 0x322A6103, 0x6053252D, 0xC901E210, +0xD9553123, 0x6E038D21, 0x4408D757, 0x44086570, +0x44006213, 0x25584200, 0x342C8F0E, 0x6043D253, +0x60E3072D, 0x4B196B7D, 0x658E68B9, 0x285D8801, +0x6B7C8F0B, 0x6B13A009, 0x6043D24D, 0x61ED0E2D, +0x68194119, 0x287D678E, 0xD14A6BEC, 0x22286212, +0xEBFF8901, 0xEEFF6BBC, 0x6EEC65BD, 0x8B0F35E0, +0x4D0BDD36, 0x540364C3, 0xBF76E502, 0xD4426D03, +0x410BD136, 0xD74165D3, 0xD441EE01, 0x27E2A01D, +0x26E9EEFC, 0x81D26063, 0x914E85D3, 0x81D32019, +0x450885D2, 0x81D2208B, 0xE20885D3, 0x81D3205B, +0x421885D4, 0x81D4202B, 0x854164C2, 0x814120E9, +0xD43465C2, 0xCB016051, 0x490B2501, 0x60C20009, +0x52F256F1, 0x2A02CB01, 0x2622AF79, 0x420BD21B, +0x5E0364C3, 0x85E16D03, 0x6053650D, 0x897BC820, +0x6210D129, 0x8B112228, 0xD72785EF, 0x4221620D, +0x42214221, 0xE501D625, 0x27504221, 0xD725D924, +0x2621D425, 0x2960E600, 0x24612762, 0x852162C2, +0x8B43C802, 0xD912D71E, 0xE0016270, 0x612C490B, +0x6692D91C, 0xA03E260B, 0x7E032962, 0x001C3D9C, +0x00201A3C, 0x002025CC, 0x00202994, 0x00200D42, +0x00202594, 0x00200DC4, 0x001E2130, 0x00200D60, +0x001C3D30, 0x00202C28, 0x00200F72, 0x002025A4, +0x0020248C, 0x001C3D00, 0x00202C3C, 0x00202B28, +0x00202BA8, 0x002029A8, 0x0020259C, 0x001E212C, +0x00202C2C, 0x00202C30, 0x00202D10, 0x002029EE, +0x002029EC, 0x002029F0, 0x002029F4, 0xE04CD139, +0x7201021E, 0xD9380126, 0x6290D438, 0x72016541, +0x29207501, 0x85E12451, 0x4618E640, 0x891D2068, +0xD934D733, 0x665D6171, 0x6592D733, 0x641D470B, +0xE200DE32, 0x2E20A012, 0xE90885E4, 0x49186203, +0x32902299, 0xE5018B04, 0x64E3BEB7, 0x0009A006, +0x2598D92B, 0xE5008902, 0x64E3BEAF, 0xD22AD429, +0x65D3420B, 0xEE01D729, 0x27E2AED9, 0x7C0862F1, +0x2F217201, 0xEE0462F1, 0x31E7612D, 0xAEC38901, +0x7F0C0009, 0x6EF64F26, 0x6CF66DF6, 0x6AF66BF6, +0x000B69F6, 0x2FE668F6, 0xD21D4F22, 0x60E36E22, +0x8D02C840, 0xBE3322E2, 0xE2400009, 0x2E284218, +0xBE3E8901, 0x60E30009, 0x8905C810, 0xD216D415, +0x0009420B, 0x0009BE3D, 0xC80560E3, 0xBE8E8901, +0x60E30009, 0x8902C802, 0xAE3A4F26, 0x4F266EF6, +0x6EF6000B, 0x00202538, 0x002029EC, 0x002029F4, +0x002029EE, 0x002029F0, 0x00201AA0, 0x00202D10, +0x00008000, 0x0020259C, 0x00200D60, 0x001E212C, +0x001C3510, 0x00202C34, 0x00200F72, 0x080A0C0E, +0x00020406, 0x1A1C1E20, 0x12141618, 0x2E303234, +0x26282A2C, 0x3A3C3E40, 0x6C625648, 0x41112F26, +0xE2208F18, 0x890B3123, 0x321CD204, 0xD1026220, +0x412B312C, 0x00090009, 0x002024B6, 0x0020246C, +0x000BE000, 0x400062F6, 0x40004000, 0x40004000, +0x40004000, 0x62F6000B, 0x40004000, 0x40004000, +0x40004000, 0x40184000, 0x62F6000B, 0x40004000, +0x40004000, 0x40004000, 0x40284000, 0x62F6000B, +0x40004000, 0x40184000, 0x000B4028, 0xC90F62F6, +0x40054005, 0x40054005, 0x62F6000B, 0x4005C907, +0x40054005, 0x62F6000B, 0x4005C903, 0x000B4005, +0xC90162F6, 0x000B4005, 0x000062F6, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x544F0D0A, 0x46205355, +0x00003A57, 0x2079614D, 0x32203033, 0x20373030, +0x333A3231, 0x38313A37, 0x00000000, 0x00000D0A, +0x00000043, 0x42707372, 0x3D206675, 0x554E203D, +0x202C4C4C, 0x6E49677A, 0x4E497274, 0x6D754E51, +0x0000003D, 0x61766E49, 0x2064696C, 0x72657375, +0x20726F20, 0x2079656B, 0x00214449, 0x52504545, +0x57204D4F, 0x65746972, 0x6461202C, 0x003D7264, +0x6C617620, 0x0000003D, 0x00000A0D, 0x6E6B6E55, +0x206E776F, 0x6D6D6F63, 0x3D646E61, 0x00000000, +0x61437748, 0x7262696C, 0x6F697461, 0x6620206E, +0x0A6C6961, 0x0000000D, 0x73696F4E, 0x61432065, +0x7262696C, 0x6F697461, 0x6166206E, 0x21216C69, +0x00000D0A, 0x00000D0A, 0x62735576, 0x7473725F, +0x00000A0D, 0x62735576, 0x7375735F, 0x646E6570, +0x00000A0D, 0x62735576, 0x7365725F, 0x000A0D6D, +0x00000042, 0x72746E49, 0x6D652051, 0x2C797470, +0x49677A20, 0x4972746E, 0x754E514E, 0x00003D6D, +0x20746F4E, 0x756F6E65, 0x49206867, 0x4220514E, +0x0A0D6675, 0x00000000, 0x000000FF, 0x00020001, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x010E010D, 0x00020003, +0x01090108, 0x0002010A, 0x00030002, 0x02020201, +0x02040203, 0x02060205, 0x02080207, 0x020A0209, +0x020C020B, 0x020E020D, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x010E010D, 0x00FF010F, +0x01090108, 0x010B010A, 0x00030002, 0x02020201, +0x02040203, 0x02060205, 0x02080207, 0x020A0209, +0x020C020B, 0x020E020D, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00205220, 0x00000046, +0x00000059, 0x49544120, 0x0000204D, 0x00000000, +0x02000112, 0x40FFFFFF, 0x91700CF3, 0x20104890, +0x02090100, 0x0101002E, 0x09FA8000, 0x04000004, +0x000000FF, 0x02010507, 0x07000200, 0x00028205, +0x05070002, 0x00400383, 0x04050701, 0x01004003, +0x002E0209, 0x80000101, 0x000409FA, 0x00FF0400, +0x05070000, 0x00400201, 0x82050700, 0x00004002, +0x03830507, 0x07010040, 0x40030405, 0x03040100, +0x030C0409, 0x0079005A, 0x00410044, 0x03180053, +0x00530055, 0x00320042, 0x0030002E, 0x00570020, +0x0041004C, 0x0000004E, 0x00000000, 0x00000000, +0x00000709, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, }; + +const u32_t zcFwImageSize=11540; diff --git a/drivers/staging/otus/hal/hpfwu_2k.c b/drivers/staging/otus/hal/hpfwu_2k.c new file mode 100644 index 000000000000..94e2caca5369 --- /dev/null +++ b/drivers/staging/otus/hal/hpfwu_2k.c @@ -0,0 +1,1016 @@ +/* + * Copyright (c) 2007-2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include "cprecomp.h" + +const u32_t zcFwImage[] = { +0x0009000B, 0x4F222FE6, 0xDE947FFC, 0xE114D594, +0x1E13D494, 0x67521E4C, 0xD494D693, 0x37402769, +0x62528F06, 0x7201D692, 0x60602522, 0x2600C93F, +0xD7906152, 0x2512611D, 0x264B6652, 0x2562470B, +0x0009B017, 0xE60095AC, 0xC84060E2, 0x2F028F03, +0x8FF93652, 0xD4887601, 0x4E0BDE88, 0xD4880009, +0x00094E0B, 0x4E0BD487, 0x7F040009, 0xA0524F26, +0x4F226EF6, 0x410BD184, 0xD4840009, 0x0009440B, +0x450BD583, 0xD7830009, 0xD283E1FF, 0x2712611D, +0xD4825029, 0xE1FFCB01, 0x1209E501, 0x12112212, +0xE7202452, 0x4718D57E, 0x2572D27E, 0xD17EE700, +0xD67FD47E, 0xE2012270, 0x24702172, 0xD67D2620, +0x2641E4FF, 0xD57CE600, 0x666DE104, 0x76016063, +0x4000626D, 0x8FF83212, 0xD5780545, 0x2520E201, +0xD278D777, 0xE480E100, 0x22122710, 0x6613D576, +0x666D644C, 0x76046763, 0x375C626D, 0x8FF83243, +0xD5722712, 0xD273D772, 0xE400E101, 0x27102511, +0x000B4F26, 0x7FCC2242, 0xD170D56F, 0xD271DB70, +0x1F51D471, 0xD6717508, 0x1F12D771, 0x1F55710C, +0x1FB975FC, 0x72041F2A, 0x1F13EB10, 0x1F561F44, +0x1F781F67, 0xD86B1F2B, 0xDD6CD96B, 0xDC6CEA00, +0xD26DDE6C, 0x89003A22, 0xD15D7A01, 0x88016010, +0x56F88B03, 0x4218E201, 0xD1682622, 0x0009410B, +0x440BD467, 0xD5670009, 0x0009450B, 0x6010D150, +0x8B108801, 0xE650D14F, 0x46186212, 0x8B083266, +0x56F9D14B, 0x2120E200, 0xCB016062, 0x2602A003, +0x72012710, 0x60822122, 0x89098801, 0xE2C8D15A, +0x622C6612, 0x89033626, 0x6010D158, 0x8BC88801, +0x51F66792, 0x217252F5, 0xD6555191, 0x55FA2212, +0x52FB6462, 0x55612542, 0x2252E400, 0x61436643, +0x05DE6013, 0x36CC4608, 0x07DE2652, 0xC9036071, +0x8B028801, 0x720162E2, 0x74012E22, 0x36B3664C, +0x71048FEE, 0x66C2D147, 0x45286512, 0x265B4518, +0x60822C62, 0x89018801, 0x0009A168, 0x6272D742, +0x8B132228, 0xD42BD741, 0x6772D541, 0x51536242, +0x312C327C, 0x24222228, 0x15138D05, 0x6262D63D, +0xB1627201, 0xD6232622, 0x2622E200, 0x52916692, +0x8B013620, 0x0009A144, 0x6061A06E, 0x001C001C, +0x001D4020, 0x0000B38E, 0xFFFF0000, 0x12340000, +0x001E1015, 0x00201274, 0x002039EC, 0x002018A2, +0x002039F8, 0x00203A10, 0x00201860, 0x00201964, +0x00201288, 0x001C3510, 0x001C3624, 0x001E212C, +0x002038EC, 0x00203484, 0x002038F4, 0x00203900, +0x0020390C, 0x00203968, 0x0020396C, 0x00203914, +0x00203915, 0x00203918, 0x00117700, 0x00203984, +0x00203982, 0x002034E8, 0x00117710, 0x001C3D30, +0x001C36F8, 0x00117734, 0x001C3684, 0x001C3D00, +0x001C1000, 0x001C1028, 0x002034FC, 0x0020391C, +0x00117600, 0x00117740, 0x7FFFFFFF, 0x00201730, +0x00203322, 0x0020232C, 0x00203D9C, 0x0020396A, +0x002034F4, 0x0020395C, 0x001C3D2C, 0x001C36B0, +0x0020348C, 0x0011775C, 0x8801C90F, 0xA0CF8901, +0xD1960009, 0x36206212, 0xD4958904, 0x2421E200, +0x2162A0CC, 0x6211D193, 0x89012228, 0x0009A0C3, +0xE202D78F, 0x75016571, 0x3123615D, 0x27518D02, +0x0009A0BC, 0xD28C57F2, 0x62226072, 0x40094019, +0xC90F4009, 0x8F19880A, 0x52F31F2C, 0x40196022, +0x40094009, 0x8808C90F, 0xA0A78901, 0x60630009, +0xCB0154F7, 0xD27E55F2, 0xE7012402, 0xD47FE100, +0x22112572, 0x72016242, 0x2422A098, 0x8B3F8805, +0x602252F3, 0x40094019, 0xC90F4009, 0x8B168802, +0xE4FFD577, 0x644D6752, 0x8B102748, 0x6272D775, +0x8B0C3260, 0x51F255F7, 0xD26DE701, 0x21722562, +0xD571E100, 0x64522211, 0xA0777401, 0x52F32542, +0x40196022, 0x40094009, 0x8805C90F, 0x31B38B6E, +0xD26A8B6C, 0x672254F4, 0x7701D569, 0x61422272, +0x1F1CE640, 0x46182159, 0x8B033160, 0x6262D665, +0x26227201, 0xE200D65A, 0x2621B067, 0x0009A056, +0x3123E220, 0x88038B52, 0x52F38B1E, 0x40196022, +0x40094009, 0x8803C90F, 0xD25B8B16, 0x672254F4, +0x7701D557, 0x61422272, 0x1F1CE640, 0x46182159, +0x8B033160, 0x6262D655, 0x26227201, 0xE200D648, +0x2621B043, 0x0009A010, 0xD452D551, 0xD2446752, +0xE1007701, 0x25723A46, 0x22118F06, 0xEA00D64E, +0x72016262, 0x2622B031, 0x2FB2D54C, 0x95736652, +0xD44A5BF1, 0x36205241, 0x60618910, 0x8B01C803, +0x2B22E201, 0x8FF54510, 0x57F15664, 0x6272E1F0, +0x41284118, 0x2722221B, 0x6BF2A008, 0x6BF2A006, +0xE200D62F, 0xD12F2621, 0x2121E200, 0xD13CE201, +0x66122822, 0x8B012668, 0x0009AE2B, 0x450BD539, +0xD1390009, 0xAE24E600, 0x2F862160, 0x2FA62F96, +0x2FC62FB6, 0x2FE62FD6, 0x7FF44F22, 0xDE34D133, +0x54116212, 0x1F4167E2, 0x2F22D432, 0xD5321F72, +0xD2326743, 0x58417794, 0x69425A42, 0x5B166C72, +0x60526D22, 0xCB20E600, 0xE5402502, 0x626D7601, +0x8BFB3253, 0x55F162F2, 0x11512122, 0xD62855F2, +0x14812E52, 0x249214A2, 0x27C2D426, 0x26D211B6, +0xDA256742, 0xE801D925, 0x490B2A72, 0xE2011A8C, +0x1A2C4218, 0x4F267F0C, 0x6DF66EF6, 0x6BF66CF6, +0x69F66AF6, 0x68F6000B, 0x000007D1, 0x0020397C, +0x00203980, 0x00203986, 0x001C3DC0, 0x0011772C, +0x001C3B88, 0x00203964, 0x0011773C, 0x00117744, +0x0000F000, 0x00117764, 0x00117748, 0x00117768, +0x0011776C, 0x01FFFFFF, 0x0011774C, 0x002034F4, +0x00203D9C, 0x002024F0, 0x0020396A, 0x001C3B9C, +0x001C3D98, 0x001C3700, 0x001C3500, 0x001C5960, +0x001C8960, 0x002034FC, 0x001C3D00, 0x0020160C, +0x2F962F86, 0x2FB62FA6, 0x2FD62FC6, 0x4F222FE6, +0xDE957FAC, 0x61E0E014, 0x0F14D494, 0x710161E3, +0xE0186210, 0xD2920F24, 0x0009420B, 0x450BD591, +0x20080009, 0x8F126D03, 0xD28F1F07, 0x6720D48F, +0x657CDD8F, 0x470BD78F, 0xD18F0009, 0x619C6910, +0x46086613, 0x36184608, 0x3D6C4608, 0xE0181FD7, +0xE58004FC, 0x604C66E2, 0x3050655C, 0x2D628F15, +0x01FCE014, 0xDE85E500, 0x641CA008, 0x6753655D, +0x607037EC, 0x39DC6953, 0x80947501, 0x3243625D, +0xD67F8BF4, 0xA34EE200, 0x20082621, 0xE0148B13, +0xE40001FC, 0xA009DE79, 0x644D671C, 0x35EC6543, +0x69436652, 0x39DC6262, 0x74041921, 0x3273624D, +0xA3388BF3, 0x88012D10, 0xE0148B17, 0xE70001FC, +0x6D1C2D70, 0xDE6D1FD4, 0x32D3627D, 0xA32A8B01, +0x677D0009, 0x667365E3, 0x61737504, 0x315C36EC, +0x69126462, 0xAFEF7708, 0x88042492, 0xE0148B18, +0xE40001FC, 0x671C2D40, 0x624DDE60, 0x8B013273, +0x0009A311, 0x6943644D, 0x39EC62E3, 0x72046592, +0x3D2C6D43, 0x615266D2, 0x21697408, 0x2512AFED, +0x8B188805, 0x01FCE014, 0x2D40E400, 0xDE53671C, +0x3273624D, 0xA2F68B01, 0x644D0009, 0x62E36943, +0x659239EC, 0x6D437204, 0x66D23D2C, 0x74086152, +0xAFED216B, 0x88312512, 0xD44A8B3A, 0x6146D94A, +0x75046543, 0x67566442, 0x6E531F48, 0x65527E04, +0x7EE462E2, 0x7E0464E2, 0x6EE21FE9, 0x5EF929E0, +0x7E04D942, 0x1FEA60E2, 0x2900C901, 0xD9406EE2, +0x29E04E09, 0x2F562F26, 0x56FAD93E, 0x6513490B, +0xD13D7F08, 0xE71C6E0D, 0x1DE12D70, 0xDE3B6912, +0x64E21D92, 0x1D43D13A, 0xD23A6512, 0x67221D54, +0x1D75D239, 0x1D666622, 0x6262D638, 0x1D27A2AB, +0x8B398830, 0x6596D92B, 0x67926696, 0x61967904, +0x74E46493, 0x6E436992, 0x1F9B7E04, 0x1FEC6442, +0xD9256EE2, 0x5EFC29E0, 0x7E04D924, 0x1FED60E2, +0x2900C901, 0xD9226EE2, 0x29E04E09, 0x59FC7FFC, +0xDE272F92, 0x2F164E0B, 0xD41F7F08, 0xE21C610D, +0x1D112D20, 0xD2206442, 0xD41C1D42, 0x1D536542, +0x6752D51B, 0xD71B1D74, 0x1D156172, 0x1D666622, +0x6262D61A, 0x1D27A26F, 0x8B358833, 0x490BD919, +0xA268EE00, 0x00002DE0, 0x00117800, 0x00203A14, +0x002018A2, 0x00202AA4, 0x00203906, 0x00203A18, +0x0020352C, 0x002018EE, 0x00203905, 0x00117804, +0x00203984, 0x00117810, 0x00203901, 0x00203902, +0x00203903, 0x00200F64, 0x001C5864, 0x001C6864, +0x001C7864, 0x001C59BC, 0x001C69BC, 0x001C79BC, +0x00200FBC, 0x00200FB8, 0x89018828, 0x0009A0C0, +0xE643DEB5, 0x326662E1, 0x1FEE8F02, 0x2E21E240, +0x622D62E1, 0x8B013267, 0x0009A0AA, 0xE50185E1, +0x8B013056, 0x0009A0A4, 0x2D10E101, 0x64E1B225, +0xE64357FE, 0x652D6271, 0x89443567, 0x3563E640, +0xE6008B05, 0x0F65E040, 0xA00FE11A, 0x615372C0, +0x41214121, 0x41214121, 0x45214121, 0x45214521, +0xC9036053, 0xE0406603, 0x71180F65, 0x2209E007, +0x0F25E03C, 0xE044641D, 0xB2A365F3, 0xE33C0F46, +0x853233FC, 0x620DDE95, 0x42086031, 0x6023610D, +0x1323E944, 0x06FE4108, 0xE00F39FC, 0x13144E0B, +0x67075D91, 0x60D32679, 0x0F6654FE, 0x51928542, +0x600D4E0B, 0x60D3260B, 0x0F666492, 0x65F3B237, +0x696156FE, 0xE640659D, 0x89383563, 0xD78359FE, +0x79066591, 0xC9036053, 0x40004008, 0x61036203, +0x0F26E050, 0x470BE0FF, 0x6C07600C, 0x6603605D, +0x46214621, 0x46214621, 0x42006263, 0x4200326C, +0x40214021, 0x4008C903, 0x6D2D30FC, 0xE8006A03, +0xB25765F3, 0x6EA264D3, 0x2EC9E050, 0x66942AE2, +0xD76E01FE, 0x606C470B, 0x2AE22E0B, 0x64D365F3, +0x7801B1FD, 0xEE06628D, 0x8FE932E3, 0x5EFE7D01, +0x61E1E400, 0x410085E1, 0x66E3310C, 0x760C711B, +0xE70465F3, 0x68667401, 0x3A736A4D, 0x8FF92582, +0x65F37504, 0x641DB1E3, 0x64E1B1A4, 0x0009A17B, +0xD45B56F7, 0xEC01D25B, 0x26C0420B, 0x0009A173, +0x06FCE018, 0x8829606C, 0x58F78B08, 0xE400D252, +0x66222840, 0x646DB171, 0x0009A165, 0x666CE681, +0x89013060, 0x0009A0AC, 0xD550D14F, 0x62126A56, +0x212232AC, 0x54116C56, 0x34CC6253, 0x64521141, +0x72085812, 0xD44A384C, 0x68221182, 0x5A136C42, +0x3ACC3C8C, 0x11A324C2, 0x6C2272EC, 0x72105814, +0x118438CC, 0x5A156822, 0x11A53A8C, 0x6A227210, +0xD6405816, 0x118638AC, 0x52176C62, 0x112732CC, +0x5A185861, 0x11A83A8C, 0x5C195A62, 0x11C93CAC, +0x521A5C63, 0x112A32CC, 0x5A1B5864, 0x11AB3A8C, +0x5C1C5A65, 0x11CC3CAC, 0x521D5C66, 0x112D32CC, +0x5A1E5867, 0x11AE3A8C, 0x561F5A68, 0x36ACE840, +0x116FDA2D, 0x6CA2381C, 0x7A946682, 0x286236CC, +0x5C8162A2, 0x18C13C2C, 0x62A27A44, 0x362C5682, +0xD6261862, 0x5A856262, 0x3A2C4229, 0x760418A5, +0x56866262, 0x362C4229, 0x56F71866, 0x2620E238, +0x16C15C81, 0x16226212, 0xE2005C11, 0x551216C3, +0x55151654, 0x55131655, 0x55161656, 0x55821657, +0x65821658, 0x55141659, 0x5584165A, 0x5583165B, +0x5585165C, 0x5586165D, 0x1821165E, 0x11212122, +0x11251122, 0x11261123, 0x28221822, 0x18241124, +0x18251823, 0x1826A0C7, 0x00117804, 0x002033E0, +0x00203A38, 0x002018A2, 0x0020348C, 0x001C36A0, +0x002034E8, 0x001C3CA0, 0x001C36F4, 0x001C3B88, +0x666CE682, 0x8B203060, 0xEA2456F7, 0x26A0D194, +0x16C15C17, 0x16225218, 0x16835819, 0x16A45A1A, +0x16C55C1B, 0x1626521C, 0xE200581D, 0x551E1687, +0x551F1658, 0x11271659, 0x11291128, 0x112B112A, +0x112D112C, 0xA08E112E, 0xE683112F, 0x3060666C, +0x52F78B0B, 0xEA00D883, 0x658222A0, 0x7804DC82, +0x62822C52, 0xA07ED681, 0xE6902620, 0x3060666C, +0xDA7F8B06, 0x00094A0B, 0xE20056F7, 0x2620A073, +0x666CE691, 0x8B103060, 0x6222D276, 0x2228622C, +0xD2788904, 0x0009420B, 0x0009A003, 0x420BD276, +0x56F70009, 0xA05EE200, 0xE6922620, 0x3060666C, +0xE0188951, 0xE6B00BFC, 0x666C62BC, 0x8B2A3260, +0x02FCE014, 0x682CEA00, 0x62ADE904, 0x894A3283, +0x6AADDD64, 0x3CDC6CA3, 0x7D046EC2, 0xDB68D467, +0x32DC62A3, 0x4B0BDC67, 0x4C0B6D22, 0xD46664E3, +0x00094B0B, 0x64D34C0B, 0x4B0BD464, 0xE6000009, +0x666D6BE3, 0x76013B6C, 0x3293626D, 0x8FF72BD0, +0xAFDA4D19, 0xE6B57A08, 0x3260666C, 0xD45C8B13, +0x4B0BDB57, 0xD25B0009, 0x6022DB5B, 0xCB20E6FF, +0x2202666D, 0xDB592B62, 0xE014E200, 0x56F72B20, +0xA01002FC, 0xD4562620, 0x6542D256, 0x420BD456, +0xA0080009, 0xDB520009, 0x52B1E600, 0x622CDB53, +0x52F72B21, 0x7F542260, 0x6EF64F26, 0x6CF66DF6, +0x6AF66BF6, 0x000B69F6, 0x4F2268F6, 0xE240614D, +0x89143123, 0x3127E21F, 0x8B09D749, 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+0x02020201, 0x02040203, 0x02060205, 0x02020200, +0x02040203, 0x020C020B, 0x020E020D, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x010E010D, +0x00FF010F, 0x01090108, 0x010B010A, 0x0200010F, +0x02020201, 0x02040203, 0x02060205, 0x02020200, +0x02040203, 0x020C020B, 0x020E020D, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x010E010D, +0x00FF010F, 0x01090108, 0x010B010A, 0x010F010F, +0x02020201, 0x02040203, 0x02060205, 0x02020200, +0x02040203, 0x020C020B, 0x020E020D, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00205220, +0x00000046, 0x00000059, 0x73204142, 0x003D7165, +0x49544120, 0x0000204D, 0x00000000, 0x00000000, +0x002E0209, 0x80000101, 0x000409FA, 0x00FF0400, +0x05070000, 0x02000201, 0x82050700, 0x00020002, +0x03830507, 0x07010040, 0x40030405, 0x02090100, +0x0101002E, 0x09FA8000, 0x04000004, 0x000000FF, +0x02010507, 0x07000040, 0x40028205, 0x05070000, +0x00400383, 0x04050701, 0x00004002, 0x00000000, +0x00000000, 0x07090000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, }; + +const u32_t zcFwImageSize=15928; diff --git a/drivers/staging/otus/hal/hpfwu_BA.c b/drivers/staging/otus/hal/hpfwu_BA.c new file mode 100644 index 000000000000..0c741571f2b5 --- /dev/null +++ b/drivers/staging/otus/hal/hpfwu_BA.c @@ -0,0 +1,874 @@ +/* + * Copyright (c) 2007-2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include "cprecomp.h" + +const u32_t zcFwImage[] = { +0x0009000B, 0x4F222FE6, 0xDE917FFC, 0xE114D791, +0x1E13D491, 0x1E4C470B, 0x0009B017, 0x95C2E600, +0xC84060E2, 0x2F028F03, 0x8FF93652, 0xD48B7601, +0x4E0BDE8B, 0xD48B0009, 0x00094E0B, 0x4E0BD48A, +0x7F040009, 0xA0474F26, 0x4F226EF6, 0x410BD187, +0xD4870009, 0x0009440B, 0x450BD586, 0xD7860009, +0x611DE1FF, 0xD1852712, 0x6012E2FF, 0xCB01D484, +0x71DC2102, 0x71042122, 0x2122E501, 0xD5812452, +0xD2819792, 0xE7002572, 0xD481D180, 0x2270D681, +0x2172E201, 0x26202470, 0xE4FFD67F, 0xE6002641, +0xE104D57E, 0x6063666D, 0x626D7601, 0x32124000, +0x05458FF8, 0xE501D27A, 0xD17A2250, 0xD57BD47A, +0xE700E600, 0x25722470, 0x11622162, 0x11691166, +0x4F26116A, 0x116E000B, 0xD1757FC4, 0x2F12D875, +0xD476D175, 0xD577D676, 0x1F87D777, 0xD97778FC, +0x1F1BD277, 0x1F417104, 0x1F647404, 0x1F887604, +0x71F41F1C, 0x1F42E8C8, 0x1F651F53, 0x1F991F76, +0x1F1D1F2A, 0xDD6F688C, 0xDA70DE6F, 0xDC71DB70, +0x00094A0B, 0x00094B0B, 0x00094C0B, 0x6010D15E, +0x8B0F8801, 0xE950D15D, 0x49186212, 0x8B073296, +0x56FAD159, 0x2120E200, 0xCB016062, 0x2602A002, +0x21227201, 0x880160D2, 0xD1638907, 0x32866212, +0xD1628903, 0x88016010, 0x64E28BDA, 0x52F751F8, +0x55E12142, 0x2252D15E, 0x661254FB, 0x246259FC, +0x29725711, 0x880160D2, 0x66E28B53, 0x362052E1, +0x6061894C, 0x8801C90F, 0xD1568B48, 0x36206212, +0xA0438903, 0x27102162, 0xD5530FA0, 0x6651E710, +0x626D7601, 0x8F3C3273, 0x65F22561, 0x695251F2, +0x54F359F1, 0x679252F4, 0x61426512, 0x56F66922, +0x642252F5, 0xCB206062, 0xE6002602, 0x76011F1E, +0x626DE110, 0x32134118, 0x51FE8FF8, 0x267256F1, +0x56F457F2, 0x55F32752, 0x251257F5, 0x27422692, +0x51F969E2, 0x2192D43D, 0xE90161F2, 0x2192440B, +0x491865F2, 0xD9382592, 0xE200D539, 0x62512921, +0x720154FD, 0x622D2521, 0x2422A003, 0xE200D932, +0xE9012921, 0x2D92D12C, 0x26686612, 0xAF6F8B01, +0xD6300009, 0x0009460B, 0xE700D128, 0x2170AF68, +0x001C001C, 0x00200F7C, 0x0000B38E, 0x0020322C, +0x0020145E, 0x00203238, 0x00203250, 0x0020141C, +0x0020151C, 0x00200FA0, 0x001C3510, 0x001C3648, +0x001E212C, 0x00203188, 0x00202D24, 0x00203190, +0x0020319C, 0x002031A8, 0x002031B8, 0x002031BC, +0x002031B0, 0x00117708, 0x002031B1, 0x002031B4, +0x001C3D30, 0x00117718, 0x00117734, 0x001C3B9C, +0x001C3704, 0x001C3D98, 0x001C3500, 0x001C3D00, +0x001C36F8, 0x001C1028, 0x00202D98, 0x00201328, +0x00202C04, 0x00201E18, 0x002034BC, 0x002031BA, +0x00202D90, 0x002031CC, 0x002031D0, 0x00201276, +0x002031D2, 0x00201FD0, 0x2FB62F96, 0x2FD62FC6, +0x4F222FE6, 0xDE947F8C, 0x61E0E024, 0x0F14D493, +0x710161E3, 0xD7926210, 0x470BE028, 0xD5910F24, +0x0009450B, 0x6D032008, 0x1F0B8F11, 0xD48FDC8E, +0xDD8F67C0, 0x657C4D0B, 0xDD8FD18E, 0x6B9C6910, +0x420862B3, 0x32B84208, 0x3D2C4208, 0xE0281FDB, +0xE58004FC, 0x604C66E2, 0x3050655C, 0x2D628F13, +0x01FCE024, 0x641CE500, 0x625DDE84, 0x8B013243, +0x0009A33D, 0x6753655D, 0x607037EC, 0x39DC6953, +0xAFF27501, 0x20088094, 0xE0248B13, 0xE50001FC, +0xA009DE7A, 0x655D641C, 0x32EC6253, 0x6C536B22, +0x3CDC67B2, 0x75041C71, 0x3243625D, 0xA31E8BF3, +0x88012D10, 0xE0248B16, 0xE40001FC, 0x671C2D40, +0x624DDE6E, 0x8B013273, 0x0009A311, 0x6CE3644D, +0x7C046943, 0x39EC6B43, 0x65923BCC, 0x74086DB2, +0x25D2AFEF, 0x8B198804, 0x01FCE024, 0x2D70E700, +0x1FD86D1C, 0x627DDE61, 0x8B0132D3, 0x0009A2F7, +0x6B73677D, 0x3BEC61E3, 0x710464B2, 0x3C1C6C73, +0x694265C2, 0x29597708, 0x2492AFED, 0x8B188805, +0x01FCE024, 0x2D40E400, 0xDE54671C, 0x3273624D, +0xA2DC8B01, 0x644D0009, 0x6BE36D43, 0x65D23DEC, +0x61437B04, 0x6C1231BC, 0x74086952, 0xAFED29CB, +0x88312592, 0xDE4A8B20, 0x65E6DB4A, 0x61E6DC4A, +0x67E2D94A, 0x62E27E04, 0x1FEC7EE8, 0x7E0464E2, +0x6EE21FED, 0x5BFD2BE0, 0x60B27B04, 0xC9011FBE, +0x6BB22C00, 0x29B04B09, 0xDC412F26, 0x66134C0B, +0xE2007F04, 0x2D20A2AB, 0x8B218830, 0xD939DE38, +0xE06465E6, 0x720462E3, 0x672666E2, 0x6E23DC36, +0x62227EE8, 0x6BE261E6, 0x29B01FEF, 0x7E040F16, +0xC90160E2, 0x6EE22C00, 0x4E09DC30, 0x2F262CE0, +0xD130E068, 0x04FE410B, 0xE2007F04, 0x2D20A287, +0x8B058833, 0x4E0BDE2C, 0xE1000009, 0x2D10A27F, +0x89018828, 0x0009A106, 0xE143DE20, 0xE04062E1, +0x3217622D, 0x0FE68F04, 0x6023E240, 0x262106FE, +0x8B013217, 0x0009A0EF, 0x02FEE040, 0x8521E401, +0x8B013046, 0x0009A0E7, 0xE501E040, 0x2D5007FE, +0x6471B265, 0x09FEE040, 0x6291E143, 0x652DE068, +0x8D6B3517, 0xE6400F56, 0x8B273563, 0xE048E600, +0xE11A0F65, 0x72C0A031, 0x00117800, 0x00203254, +0x0020145E, 0x00202588, 0x002031A2, 0x00203258, +0x002014AA, 0x002031A1, 0x00202DC8, 0x00117804, +0x00117810, 0x0020319D, 0x0020319E, 0x0020319F, +0x00200C2C, 0x00200C80, 0x00200C7C, 0x41216153, +0x41214121, 0x41214121, 0x45214521, 0x60534521, +0x6603C903, 0x0F65E048, 0xE0077118, 0xE0442209, +0x641D0F25, 0x65F3E04C, 0x0F46B28C, 0x04FDE048, +0x0BFDE044, 0x61BD674D, 0x41084708, 0x0F16E050, +0xD29B6073, 0x420B09FE, 0x6C07E00F, 0x607329C9, +0xE0400F96, 0x65F30EFE, 0x6D0D85E2, 0x01FEE050, +0x60D3420B, 0x6073290B, 0xE04C0F96, 0x04FEB251, +0x06FEE040, 0x6261E068, 0x0F56652D, 0x3563E640, +0xE000894E, 0x602381F8, 0x4008C903, 0x6B034000, +0xE0546103, 0xE0580FB6, 0xECFFDD85, 0x6CCC0FF6, +0x0FD6E06C, 0x4D0B60C3, 0x42216253, 0x42214221, +0x64234221, 0x324C4200, 0xE05C6E07, 0x45214200, +0xE0400FE6, 0x0BFE4521, 0xC9036053, 0x30FC4008, +0x6D037B06, 0x85F81F05, 0x6C2D1FB7, 0x1FC66E03, +0x0FC6E060, 0x05FEE058, 0x64C3B22C, 0x33FCE354, +0x563262D2, 0x22696132, 0x67B42D22, 0x490B5936, +0x220B607C, 0x05FEE058, 0x64C32D22, 0x7E01B201, +0xE70662ED, 0x8FE33273, 0xE0407C01, 0x626106FE, +0x06FEE040, 0x85614200, 0x302C760C, 0x6103701B, +0x64F3E500, 0x7501E704, 0x6B5D6966, 0x24923B73, +0x74048FF9, 0xB1E465F3, 0xE040641D, 0xB1A306FE, +0xA17C6461, 0xD4570009, 0xE201D757, 0x2D20470B, +0x0009A175, 0x8B078829, 0xEC00DE54, 0x61E22DC0, +0x641DB175, 0x0009A16B, 0x622CE281, 0x8B013020, +0x0009A0B6, 0x06FCE028, 0xE682626C, 0x3260666C, +0x56FB8B20, 0x2610E124, 0x5217D149, 0x52181621, +0x52191622, 0x521A1623, 0x551B1624, 0x1655E200, +0x1656551C, 0x1657551D, 0x1658551E, 0x1659551F, +0x11281127, 0x112A1129, 0x112C112B, 0x112E112D, +0x112FA13D, 0x666CE683, 0x8B0B3260, 0xD63752FB, +0x2250E500, 0xD2376562, 0x22527604, 0xD6366262, +0x2620A12D, 0x666CE690, 0x8B033260, 0x0009B1C7, +0x0009A011, 0x666CE691, 0x8B103260, 0x6252D52B, +0x2228622C, 0xD22D8904, 0x0009420B, 0x0009A003, +0x420BD22B, 0x56FB0009, 0xA110E200, 0xE6B02620, +0x3260666C, 0xE0248B34, 0xE07002FC, 0x0F16612C, +0xEB04EC00, 0x01FEE070, 0x321362CD, 0xA0FE8B01, +0xD21A0009, 0x6DC36CCD, 0x72043D2C, 0x312C61C3, +0x6D126ED2, 0xD114D41B, 0x0009410B, 0x410BD11A, +0xD41A64E3, 0x420BD210, 0xD2170009, 0x64D3420B, +0xD60DD417, 0x0009460B, 0x61E3E600, 0x316C666D, +0x626D7601, 0x21D032B3, 0x4D198FF7, 0x7C08AFD2, +0xD211D410, 0xD4116542, 0x0009420B, 0x0009A0CF, +0x00202C80, 0x00203278, 0x0020145E, 0x00117804, +0x00202D2C, 0x00203188, 0x0020319C, 0x00200CBA, +0x00200CE0, 0x00203290, 0x002014A2, 0x002032A4, +0x002032AC, 0x00117800, 0x002014AA, 0x002032B0, +0xD5B5D1B4, 0x6252E040, 0x75046612, 0x2162362C, +0x56116256, 0x1161362C, 0x62526653, 0x76085512, +0x1152352C, 0x55136262, 0x352C76EC, 0x65631153, +0x56146262, 0x362C7510, 0x66531164, 0x55156252, +0x352C7610, 0x62621155, 0x362C5616, 0xD6A31166, +0x55176262, 0x352C7604, 0x62661157, 0x352C5518, +0x65631158, 0x56196262, 0x362C7504, 0x62561169, +0x362C561A, 0x6256116A, 0x362C561B, 0x6653116B, +0x551C6252, 0x352C7604, 0x6266115C, 0x352C551D, +0x6263115D, 0x551E6662, 0x356C7204, 0x6622115E, +0xD58F521F, 0x112F326C, 0x061E6252, 0x362C7594, +0xE0440166, 0x62526653, 0x7644051E, 0x0156352C, +0x6262E048, 0x362C061E, 0xD6860166, 0x6262E054, +0x4229051E, 0x0156352C, 0x62627604, 0x061EE058, +0x362C4229, 0x56FB0166, 0x2620E238, 0x021EE044, +0x1621E048, 0x16226212, 0x16235211, 0xE2005512, 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+0x81F4E40C, 0x65636053, 0x420B81F5, 0x7F0C7540, +0x000B4F26, 0x2F860009, 0x2FA62F96, 0x2FC62FB6, +0x2FE62FD6, 0x7FEC4F22, 0xE800D11A, 0xD4322F12, +0x1F416183, 0x6A13DB20, 0x4A08D630, 0xDE20E001, +0x4A00460B, 0x1F023AEC, 0x52B166B2, 0x8B013620, +0x0009A19B, 0xC9036061, 0x8B018801, 0x0009A195, +0xDE275263, 0x8B4F32E0, 0x420BD20D, 0xDE2564B3, +0xD70DD50E, 0xED01DC0B, 0x2E02E100, 0x27D02502, +0xAFE12C10, 0x00002E16, 0x001C3D9C, 0x00201F40, +0x0011779A, 0x001C3D30, 0x001D0104, 0x00202DC0, +0x00201162, 0x002031B1, 0x002031B0, 0x002031AC, +0x001C3B9C, 0x001C3500, 0x00202D98, 0x00201276, +0x001C3D00, 0x001C36F8, 0x00117708, 0x002031B4, +0x0011778C, 0x00117792, 0x00117788, 0x00201180, +0x00203188, 0x00202D88, 0x002011E4, 0x001E2130, +0x0020349C, 0x0020145E, 0x002034A8, 0x00202C80, +0x00117780, 0x0011770C, 0xC8018561, 0x5C63897A, +0x660385C2, 0x6403C903, 0x650D85C3, 0x40216053, +0xC93F4021, 0x6E034500, 0x252D322A, 0xE2106053, +0x3E23C901, 0x6D038D23, 0x4408D79D, 0x44086570, +0x440062E3, 0x25584200, 0x342C8F0F, 0x6043D299, +0x697D072D, 0x60994919, 0x201D610E, 0x60D381F6, +0x8F0C8801, 0xA00A697C, 0xD29369E3, 0x052D6043, +0x4219625D, 0x670E6029, 0x81F6207D, 0xD18F695C, +0x22286210, 0xE9FF8901, 0xEEFF699C, 0x6EEC659D, +0x8B0F35E0, 0x4C0BDC8A, 0x540364B3, 0xBF20E502, +0xD4886E03, 0x410BD188, 0xD78865E3, 0xD488ED01, +0x27D2A01E, 0x26E9EEFC, 0x81C26063, 0x97C585C3, +0x62032079, 0x450885F6, 0x6063260B, 0x81C2252B, +0x81C36053, 0xE10885C4, 0x201B4118, 0x62B281C4, +0x20E98521, 0x64B28121, 0xCB016041, 0xD4792401, +0x450BD579, 0x60B20009, 0x57F266F2, 0x2A02CB01, +0x2672AF22, 0xD26E8561, 0x8F02C802, 0xA09F64B3, +0x420B0009, 0xDC710009, 0x5E036503, 0x07CEE04C, +0x7701DD6F, 0x6CD20C76, 0x7C01D664, 0x6D602DC2, +0x89062DD8, 0xD264D463, 0xED01420B, 0xA07ED763, +0x625127D2, 0x4118E10F, 0x2219E402, 0x32404418, +0x85518B11, 0x20D9EDFC, 0x60518151, 0xCB017DE3, +0x85E12501, 0x20D9D65F, 0x460B81E1, 0x6CF264B3, +0xA06457F2, 0x6D512C72, 0x4D196DDD, 0x66DE6DD9, +0x7D012D6D, 0x610360DC, 0x88014118, 0x25118F45, +0x6462D653, 0x26427401, 0x660D85E3, 0x40216063, +0xC93F4021, 0x6D034600, 0x262D322A, 0xC8016063, +0xDC4ED14D, 0x964A8901, 0xE6002D6B, 0x0F64E010, +0xE01064DD, 0x607C07FC, 0x021D4000, 0x3240622D, +0x66038D12, 0x021D6063, 0x3270E7FF, 0xA00B8B01, +0xE01001D5, 0xE60402FC, 0x0F247201, 0x3262622C, +0x06FC8BE7, 0x4600666C, 0x01CD6063, 0x0C157101, +0x6711D13B, 0x3C406C7D, 0x62118907, 0x88FF602D, +0x21D18903, 0xE201DD37, 0x85512D20, 0x20D9EDFC, +0x60518151, 0xCB01D22F, 0x420B64B3, 0xE0102501, +0xD43102FC, 0xE001612C, 0x67F2440B, 0x85EF2702, +0x54F1D22E, 0x650D420B, 0x0009AE7E, 0x80007E03, +0x0009420B, 0x6E035403, 0xED088544, 0x20D94D18, +0x8B0330D0, 0xE501BE3D, 0x0009A007, 0xDD248541, +0x22D8620D, 0xBE348901, 0xD412E500, 0x420BD212, +0xD71265E3, 0xAE5FED01, 0x780127D2, 0xEE04618D, +0x8D0231E7, 0xAE4E7B08, 0x7F140009, 0x6EF64F26, +0x6CF66DF6, 0x6AF66BF6, 0x000B69F6, 0x000068F6, +0x002034B8, 0x0020339C, 0x0020341C, 0x0020319C, +0x00201162, 0x00202D90, 0x00201180, 0x001E212C, +0x002034A0, 0x002034A4, 0x0020145E, 0x00202D2C, +0x002034BC, 0x002011E4, 0x002031BC, 0x002031C4, +0x002031B8, 0x002031BA, 0x00202C80, 0x002014AA, +0x00008000, 0x4F222FE6, 0x6E22D212, 0xC84060E3, +0x22E28D02, 0x0009BCFA, 0x4218E240, 0x89012E28, +0x0009BD05, 0xC81060E3, 0xD40B8905, 0x420BD20B, +0xBD040009, 0x60E30009, 0x8901C805, 0x0009BDEB, +0xC80260E3, 0x4F268902, 0x6EF6AD01, 0x000B4F26, +0x00006EF6, 0x001C3510, 0x002034B0, 0x0020145E, +0x080A0C0E, 0x00020406, 0x1A1C1E20, 0x12141618, +0x2E303234, 0x26282A2C, 0x3A3C3E40, 0x6C625648, +0x41112F26, 0xE2208F18, 0x890B3123, 0x321CD204, +0xD1026220, 0x412B312C, 0x00090009, 0x00202CAA, +0x00202C60, 0x000BE000, 0x400062F6, 0x40004000, +0x40004000, 0x40004000, 0x62F6000B, 0x40004000, +0x40004000, 0x40004000, 0x40184000, 0x62F6000B, +0x40004000, 0x40004000, 0x40004000, 0x40284000, +0x62F6000B, 0x40004000, 0x40184000, 0x000B4028, +0xC90F62F6, 0x40054005, 0x40054005, 0x62F6000B, +0x4005C907, 0x40054005, 0x62F6000B, 0x4005C903, +0x000B4005, 0xC90162F6, 0x000B4005, 0x000062F6, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x544F0D0A, +0x46205355, 0x00003A57, 0x206C754A, 0x32203532, +0x20373030, 0x313A3132, 0x37323A32, 0x00000000, +0x00000D0A, 0x00000043, 0x42707372, 0x3D206675, +0x554E203D, 0x202C4C4C, 0x6E49677A, 0x4E497274, +0x6D754E51, 0x0000003D, 0x61766E49, 0x2064696C, +0x72657375, 0x20726F20, 0x2079656B, 0x00214449, +0x52504545, 0x57204D4F, 0x65746972, 0x6461202C, +0x003D7264, 0x6C617620, 0x0000003D, 0x00000A0D, +0x6E6B6E55, 0x206E776F, 0x6D6D6F63, 0x3D646E61, +0x00000000, 0x000A0D52, 0x203A3051, 0x00000020, +0x203A3151, 0x00000020, 0x203A3251, 0x00000020, +0x203A3351, 0x00000020, 0x203A3451, 0x00000020, +0x61437748, 0x7262696C, 0x6F697461, 0x6620206E, +0x0A6C6961, 0x0000000D, 0x73696F4E, 0x61432065, +0x7262696C, 0x6F697461, 0x6166206E, 0x21216C69, +0x00000D0A, 0x00000072, 0x00205220, 0x00000D0A, +0x62735576, 0x7473725F, 0x00000A0D, 0x62735576, +0x7375735F, 0x646E6570, 0x00000A0D, 0x62735576, +0x7365725F, 0x000A0D6D, 0x00000042, 0x72746E49, +0x6D652051, 0x2C797470, 0x49677A20, 0x4972746E, +0x754E514E, 0x00003D6D, 0x654C7245, 0x0000006E, +0x00000049, 0x20746F4E, 0x756F6E65, 0x49206867, +0x4220514E, 0x0A0D6675, 0x00000000, 0x000000FF, +0x00020001, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x010E010D, +0x00020003, 0x01090108, 0x0002010A, 0x02000003, +0x02020201, 0x02040203, 0x02060205, 0x02020200, +0x02040203, 0x020C0207, 0x020E020D, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x010E010D, +0x00FF010F, 0x01090108, 0x010B010A, 0x020000FF, +0x02020201, 0x02040203, 0x02060205, 0x02020200, +0x02040203, 0x020C020B, 0x020E020D, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00205220, +0x00000046, 0x00000059, 0x73204142, 0x003D7165, +0x49544120, 0x0000204D, 0x00000000, 0x00000000, +0x002E0209, 0x80000101, 0x000409FA, 0x00FF0400, +0x05070000, 0x02000201, 0x82050700, 0x00020002, +0x03830507, 0x07010040, 0x40020405, 0x02090000, +0x0101002E, 0x09FA8000, 0x04000004, 0x000000FF, +0x02010507, 0x07000040, 0x40028205, 0x05070000, +0x00400383, 0x04050701, 0x00004002, 0x00000000, +0x00000000, 0x07090000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, }; + +const u32_t zcFwImageSize=13656; diff --git a/drivers/staging/otus/hal/hpfwu_FB50_mdk.c b/drivers/staging/otus/hal/hpfwu_FB50_mdk.c new file mode 100644 index 000000000000..ed1736f945ab --- /dev/null +++ b/drivers/staging/otus/hal/hpfwu_FB50_mdk.c @@ -0,0 +1,721 @@ +/* + * Copyright (c) 2007-2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include "cprecomp.h" + +const u32_t zcFwImage[] = { +0x0009000B, 0x4F222FE6, 0xD2287FFC, 0x0009420B, +0x0009B019, 0x9446D526, 0xE600A003, 0x8D043642, +0x60527601, 0x8DF9C840, 0xD4222F02, 0x4E0BDE22, +0xD4220009, 0x00094E0B, 0x4E0BD421, 0x7F040009, +0xA0254F26, 0x4F226EF6, 0x410BD11E, 0xD41E0009, +0x0009440B, 0x450BD51D, 0xD71D0009, 0x611DE1FF, +0x2712D21C, 0xD41C5029, 0xE1FFCB01, 0x1209E501, +0x12112212, 0xD5192452, 0xD6199716, 0xE7002572, +0x2670D218, 0x2272D618, 0x4F26E201, 0x2622000B, +0xDD17DC16, 0x4C0BDE17, 0x4D0B0009, 0x4E0B0009, +0xAFF80009, 0x27100009, 0x00000640, 0x0020095A, +0x001C001C, 0x00202940, 0x00200E2A, 0x0020294C, +0x00202964, 0x00200CF0, 0x00200F26, 0x002009C4, +0x001C3510, 0x001C3624, 0x001E212C, 0x002028EC, +0x00202850, 0x002028F4, 0x00202900, 0x00200BEC, +0x00201FD4, 0x002017B8, 0x2FD62FC6, 0x4F222FE6, +0xDEA17FA4, 0x61E0E01C, 0x7D016DE3, 0x61D00F14, +0xD59FD49E, 0x450BE020, 0xE0200F14, 0xE78004FC, +0x604C66E2, 0x7D7F677C, 0x1F693070, 0x2D628F17, +0x01FCE01C, 0x641CE500, 0xD797DE96, 0x3243625D, +0xA21A8B01, 0x655D0009, 0x31EC6153, 0xE0286C10, +0x6D530FC4, 0x3D7C62CE, 0xAFEF2D20, 0x20087501, +0xE01C8B15, 0xE50001FC, 0xD78BDE8A, 0x641CA00A, +0x6C53655D, 0x66C23CEC, 0x66626253, 0x2262327C, +0x1F697504, 0x3243625D, 0xA1F68BF2, 0x88012D10, +0xE01C8B16, 0xE40001FC, 0x671C2D40, 0x624DDE7D, +0x8B013273, 0x0009A1E9, 0x62E3644D, 0x72046D43, +0x3DEC6143, 0x65D2312C, 0x74086C12, 0x25C2AFEF, +0x8B188804, 0x01FCE01C, 0x2D40E400, 0xDE71671C, +0x3273624D, 0xA1D08B01, 0x644D0009, 0x62E36D43, +0x65D23DEC, 0x61437204, 0x6612312C, 0x74086C52, +0xAFED2C69, 0x880525C2, 0xE01C8B18, 0xE40001FC, +0x671C2D40, 0x624DDE63, 0x8B013273, 0x0009A1B5, +0x6C43644D, 0x3CEC62E3, 0x720465C2, 0x3D2C6D43, +0x615266D2, 0x216B7408, 0x2512AFED, 0x8B138830, +0xE200DE58, 0x64E22D20, 0x8B042448, 0x420BD257, +0xA19A0009, 0x55E10009, 0x57E356E2, 0xDD545CE4, +0x2FC64D0B, 0x7F04A191, 0x89018828, 0x0009A0EA, +0xE143DE4C, 0x622D62E1, 0x8F033217, 0x56FB1FEB, +0x2621E240, 0x8B013217, 0x0009A0D5, 0xE1015EFB, +0x301685E1, 0xA0CE8B01, 0xE4010009, 0x2D4055FB, +0x6451B179, 0xE14357FB, 0xE0546271, 0x3517652D, +0x0F568D41, 0x3563E640, 0xE6008B05, 0x0F65E034, +0xA00FE11A, 0x615372C0, 0x41214121, 0x41214121, +0x45214121, 0x45214521, 0xC9036053, 0xE0346603, +0x71180F65, 0x2209E007, 0x641DE030, 0x0F2565F3, +0x1F4EB1F1, 0x04FDE034, 0x674DE030, 0x47080CFD, +0x607361CD, 0x4108D22B, 0xE00F0CFE, 0x1F1F420B, +0x2CD96D07, 0x5EFB6073, 0x85E20FC6, 0x420B51FF, +0x2C0B600D, 0x54FE6073, 0xB1BB0FC6, 0xE05465F3, +0x652D62E1, 0xE6400F56, 0x89623563, 0xE050E100, +0x60230F15, 0x4008C903, 0x6D034000, 0xE0406103, +0xE0440FD6, 0xD217EEFF, 0x6EEC0FF6, 0x0F26E058, +0x60E3420B, 0x42216253, 0x42214221, 0x66234221, +0x326C4200, 0x45214200, 0xE0486707, 0x0F764521, +0xC9036053, 0x40085CFB, 0x7C0630FC, 0x6E036D2D, +0x1FD51FC6, 0x1F04A02E, 0x00117D00, 0x00202968, +0x00200E2A, 0x00117D04, 0x00117D84, 0x00200700, +0x0020074C, 0x00202034, 0x0FD6E04C, 0x05FEE044, +0x64D3B189, 0x64E2E048, 0xE04006FE, 0x2E422469, +0x01FE67C4, 0x667CE058, 0x420B02FE, 0x240B6063, +0x05FEE044, 0xB15D2E42, 0xE05064D3, 0x7D0101FD, +0x0F157101, 0x02FDE050, 0x3262E606, 0x56FB8BDC, +0x55FB6261, 0x85514200, 0x302C750C, 0x6103701B, +0x64F3E600, 0xE704A004, 0x76016256, 0x74042422, +0x3273626D, 0x65F38BF8, 0x641DB13C, 0xB0D256FB, +0xA0AA6461, 0xD4880009, 0xE201D588, 0x2D20450B, +0x0009A0A3, 0x8B078829, 0xE200DE85, 0x66E22D20, +0x646DB0A1, 0x0009A099, 0x622CE281, 0x8B3D3020, +0xD680E738, 0xE0442D70, 0xE0480C6E, 0x6E621DC1, +0x51611DE2, 0x54621D13, 0x55651D44, 0x57631D55, +0x5C661D76, 0x0E6E1DC7, 0x1DE8E040, 0xE050016E, +0x54641D19, 0x056E1D4A, 0x1D5BE04C, 0xE054076E, +0x0C6E1D7C, 0x1DCDE058, 0xE044026E, 0xED001D2E, +0xE04806D6, 0x16D126D2, 0x16D516D2, 0x16D616D3, +0xE04006D6, 0xE05006D6, 0x06D616D4, 0x06D6E04C, +0x06D6E054, 0x06D6E058, 0x1F29A057, 0x622CE282, +0x89313020, 0x05FCE020, 0x625CE683, 0x3260666C, +0xD65D8B07, 0x2650E500, 0x52617680, 0xA044D65B, +0xE6902622, 0x3260666C, 0xD2578B16, 0xE500D658, +0x60622250, 0xCB20D257, 0xE6052602, 0xD6562262, +0x2252460B, 0x420BD255, 0xD2550009, 0x2262E601, +0x4618D254, 0x2262A029, 0xD254D453, 0xD4546542, +0x0009420B, 0x0009A021, 0xE524D647, 0xD5452650, +0x16215257, 0x16225258, 0x16235259, 0x1624525A, +0x1625525B, 0x1626525C, 0x1627525D, 0x1628525E, +0x1F29525F, 0xE2001629, 0x15281527, 0x152A1529, +0x152C152B, 0x152E152D, 0x7F5C152F, 0x6EF64F26, +0x000B6DF6, 0x4F226CF6, 0xE240614D, 0x89173123, +0x3127E21F, 0xD43B8908, 0xE001D53B, 0x6642450B, +0x26796707, 0x2462A00C, 0x3127E23F, 0xD7358908, +0x71E0D635, 0x460BE001, 0x62075571, 0x17512529, +0x000B4F26, 0x4F220009, 0xE240614D, 0x89153123, +0x3127E21F, 0xD42B8907, 0x6642D22B, 0xE001420B, +0xA00B260B, 0xE23F2462, 0x89073127, 0xD626D725, +0x71E05571, 0xE001460B, 0x1751250B, 0x000B4F26, +0xE6400009, 0x46284618, 0x6252D520, 0x89FC2268, +0x0009000B, 0x4618E680, 0xD51C4628, 0x22686252, +0x000B89FC, 0xA0010009, 0x7201E200, 0x8BFC3242, +0x0009000B, 0x4618E680, 0xD5154628, 0x22686252, +0x000B8BFC, 0x00000009, 0x0020296C, 0x00200E2A, +0x00117D04, 0x00202858, 0x00117D80, 0x002028EC, +0x001C3500, 0x001D4004, 0x00200F26, 0x002009C4, +0x001E212C, 0x001C3D28, 0x00117D00, 0x00200E8A, +0x00202984, 0x001C3704, 0x00202034, 0x001C373C, +0x001C3700, 0x4F222FE6, 0x6E537FFC, 0x2F42BFCA, +0xD61561E2, 0x1615E280, 0x421854E1, 0x55E21646, +0x16574228, 0x6EF257E3, 0x2E2B1678, 0x7F0426E2, +0xAFA74F26, 0x2FC66EF6, 0x2FE62FD6, 0xDD0A4F22, +0xBFAF6C53, 0xBF946E43, 0xBFAB2DE2, 0x51D50009, +0x54D62C12, 0x55D71C41, 0x56D81C52, 0x4F261C63, +0x6DF66EF6, 0x6CF6000B, 0x001C370C, 0x0009A0F8, +0xD19B4F22, 0xD49B9299, 0x2122B00D, 0x9795E605, +0xB0229595, 0xB0366463, 0xB03A0009, 0xB03D0009, +0xA06C0009, 0x4F124F26, 0xD1934F02, 0x94873145, +0x4609060A, 0x46094609, 0x00293646, 0xD78CD58F, +0x2500CA01, 0x4F062762, 0x4F16000B, 0xBFEA4F22, +0xB0230009, 0xA0520009, 0x2FE64F26, 0x6E63D188, +0x44186612, 0x4528926D, 0x26294408, 0x44084500, +0x4400265B, 0x4708264B, 0x47082162, 0x27EBD181, +0x000B2172, 0xD1806EF6, 0xE603D480, 0x000B2162, +0xD27F2462, 0xE40A9656, 0x2262AFB0, 0x2FC62FB6, +0x2FE62FD6, 0xDC7B4F22, 0x2C22E201, 0xBFA5E40A, +0x60C27C44, 0xCB01ED00, 0x60C22C02, 0xC901EB64, +0x6E03A008, 0x89073DB2, 0xE40160C2, 0xBF95C901, +0x7D016E03, 0x8BF52EE8, 0x8B033DB2, 0xD26FD46E, +0x0009420B, 0x4F26E40A, 0x6DF66EF6, 0xAF856CF6, +0x44116BF6, 0x604B8F01, 0x000B6043, 0x2F860009, +0x2FA62F96, 0x2FC62FB6, 0x2FE62FD6, 0x7FFC4F22, +0x6DA3EA00, 0xDC626BA3, 0x9914E864, 0x8B4E2BB8, +0x3AE3EE0A, 0x60C2894B, 0xCB02ED00, 0x62C22C02, +0x2F0260C2, 0xA010C902, 0x096C6E03, 0x5BB45288, +0x1FFF09B4, 0x01FF03C4, 0x89083D83, 0xE46460C2, +0xC9022F02, 0x6E03BF52, 0x2EE87D01, 0xD1518BF4, +0x54C1D551, 0x66526412, 0x6269EE01, 0x4220622F, +0x622F4219, 0x4E182299, 0x8D0322E8, 0xE4FF6423, +0x3428229A, 0x6572D749, 0x622F6259, 0x42194220, +0x2299622F, 0x8D0322E8, 0xE6FF6623, 0x3628229A, +0x3468BFA7, 0x30E2EE02, 0xAFB78901, 0xD240EB01, +0x6EECEEE6, 0xBF21E40A, 0xAFAF22E2, 0xEE0A7A01, +0x89013AE3, 0x8B033D83, 0xD234D43A, 0x0009420B, +0x4F267F04, 0x6DF66EF6, 0x6BF66CF6, 0x69F66AF6, +0x68F6000B, 0x5651D534, 0x46286052, 0x306C000B, +0x2FC62FB6, 0x2FE62FD6, 0x4F124F22, 0xBFF14F02, +0x6B036E43, 0xDD1CDC2D, 0x0009BFEC, 0x3C0530B8, +0x4609060A, 0x46014609, 0x020A3D65, 0x42094209, +0x32E24209, 0x4F068BF0, 0x4F264F16, 0x6DF66EF6, +0x000B6CF6, 0x2FE66BF6, 0xDE214F22, 0xE500E102, +0x2E12E403, 0x2E52BFD4, 0x4618E606, 0xE403E700, +0x2E722E62, 0xAFCB4F26, 0x4F226EF6, 0x0009BFEB, +0xE6E6D213, 0xE40A666C, 0x2262BFC2, 0x4F26AFE3, +0x002028F0, 0x0024CDE0, 0x10624DD3, 0x00202AF0, +0x001C5814, 0x001C59D0, 0x001C59A4, 0x001C639C, +0x001C5804, 0x001C581C, 0x00202998, 0x00200E2A, +0x001C5860, 0x001C6864, 0x001C59BC, 0x001C69BC, +0x001C947C, 0x002029B0, 0x001C1040, 0xCCCCCCCD, +0x001D4004, 0x2F962F86, 0x2FB62FA6, 0x2FD62FC6, +0x4F222FE6, 0xE4007FE4, 0x4528E510, 0x67436C43, +0xE107A00F, 0x6043644D, 0x0F564008, 0xEE0060C3, +0x815125C1, 0x81538152, 0x157315E2, 0x751415E4, +0x624D7401, 0x8BED3213, 0xDA6F51F1, 0x1A1154F2, +0xD16E2A12, 0x57F455F3, 0x6DF258F5, 0x1141D96C, +0x11532142, 0x11751152, 0x11871174, 0x52F61186, +0x19D1D668, 0xD86829D2, 0xDA68E950, 0x1621EBB4, +0x6BBC2622, 0xA0214908, 0x6EEDEE00, 0x61E36DE3, +0x41084D08, 0x31EC3DEC, 0x41084D08, 0x60C33D8C, +0xE7904108, 0x81D12DC1, 0x41086093, 0x81D2677C, +0x31AC60C3, 0x3472E200, 0x1DD281D3, 0xD4551D13, +0x1D248D01, 0xB03AD450, 0x7E0165D3, 0x34B264ED, +0xD14D8BDB, 0x6512DB52, 0x4529D24D, 0x64121B51, +0x674DD14A, 0x67222B72, 0x4729D64E, 0x69221B73, +0x689D2FD2, 0x69121B82, 0x5A122692, 0x5B1416A2, +0x16B4DA44, 0x16C65C16, 0x16EA6EA2, 0x4F267F1C, +0x6DF66EF6, 0x6BF66CF6, 0x69F66AF6, 0x68F6000B, +0x60616642, 0x8D04C803, 0x6061E500, 0x8802C903, +0x52628B03, 0x51246563, 0x000B2412, 0x2FD66053, +0x4F222FE6, 0x6E537FEC, 0xE5506253, 0xE4006D43, +0xA0014508, 0x5224E101, 0x22116043, 0x81238121, +0x81226053, 0x362056E2, 0xD22F8BF5, 0x64F316E4, +0x420BE614, 0x65E165E3, 0x2549E4FC, 0x61F12E51, +0x214965F3, 0x54D12F11, 0x410BD127, 0x57D1E614, +0xCB016071, 0x1DE12701, 0x4F267F14, 0x000B6EF6, +0x2FD66DF6, 0x4F222FE6, 0x6E537FEC, 0xE5FC6653, +0x60616D43, 0xCB012059, 0x52E22601, 0x8B063260, +0x51E212E4, 0x8B0431E0, 0xA00252D1, 0xAFF01E22, +0xD2155664, 0xE61464F3, 0x65E3420B, 0xE1FC67E1, +0x2E712719, 0x54D167F1, 0xD10F2719, 0xE61465F3, +0x2F71410B, 0x602152D1, 0x2201CB01, 0x7F141DE1, +0x6EF64F26, 0x6DF6000B, 0x002028BC, 0x002028C4, +0x002028B4, 0x002028E4, 0x0010008C, 0x00100EC0, +0x001E2108, 0x001C3D00, 0x00202194, 0x2FC62FB6, +0x2FE62FD6, 0xD6314F22, 0x60D36D62, 0x894DC803, +0xDB30DC2F, 0x0009A02C, 0xC9036061, 0x892B8801, +0xD22DD42B, 0x0009420B, 0x65035603, 0xC8208561, +0xE0508903, 0x720102BE, 0x85620B26, 0x4000600D, +0x4000366A, 0x40004624, 0x206D4624, 0xD423C903, +0x40086E03, 0xD1224000, 0x340C410B, 0x61E3D521, +0xD721E001, 0x450BD221, 0x64E37E30, 0x2702420B, +0x66C252C1, 0x8BCF3620, 0x4E18EE01, 0xA011DB1C, +0x6061EC75, 0x8801C903, 0xD4198910, 0x460BD612, +0xD4180009, 0x470BD718, 0xD2136503, 0x64C3D113, +0x22E2410B, 0x66B252B1, 0x8BEA3620, 0xC80460D3, +0xD2128906, 0x6EF64F26, 0x6CF66DF6, 0x6BF6422B, +0x6EF64F26, 0x6CF66DF6, 0x6BF6000B, 0x001E2100, +0x002028BC, 0x00202858, 0x00200AE0, 0x002028C4, +0x00200B62, 0x00202034, 0x001C3D30, 0x00200DF0, +0x002028B4, 0x002028E4, 0x00200AFE, 0x002000F8, +0xE601D237, 0x1265D537, 0x000B2252, 0xD6361266, +0x88016062, 0xE1018B62, 0xD5342612, 0x5451D134, +0xE0406212, 0x2122324C, 0x54115752, 0x1141347C, +0x57125453, 0x1172374C, 0x52135755, 0x1123327C, +0x56146452, 0x1164364C, 0x54155754, 0x1145347C, +0x56165458, 0x1166364C, 0x6762D626, 0x327C5217, +0x57611127, 0x327C5218, 0x57621128, 0x327C5219, +0x57631129, 0x347C541A, 0x5764114A, 0x347C541B, +0x5765114B, 0x347C541C, 0x5266114C, 0x372C571D, +0x5267117D, 0x342C541E, 0x5268114E, 0x362C561F, +0xD615116F, 0x041E6262, 0x342C7694, 0xE0440146, +0x061E6262, 0x0166362C, 0x525CE048, 0xD60F051E, +0x0156352C, 0xE0546262, 0x4229051E, 0x0156352C, +0xE0585561, 0x4529061E, 0x0166365C, 0x0009000B, +0x001C1010, 0x0000C34F, 0x001C1028, 0x001C369C, +0x00202858, 0x001C3CA0, 0x001C36F4, 0x001C3B88, +0xD62F7FFC, 0x2642644C, 0xC8205066, 0x2F028DFC, +0x7F04000B, 0x2FD62FC6, 0x4F222FE6, 0x6D436C53, +0xEE00A004, 0x7E0164D4, 0x644CBFEA, 0x8BF93EC2, +0x6EF64F26, 0x000B6DF6, 0xA0016CF6, 0x76016643, +0x22286260, 0x36488BFB, 0x6563AFE4, 0x2FB62F96, +0x2FD62FC6, 0x4F222FE6, 0xEC1CED08, 0xDB196E53, +0x61C3E90A, 0x60434B0B, 0x3092C90F, 0x66038D02, +0x7630A001, 0x4D107637, 0x7E012E60, 0x7CFC8FF1, +0x8058E000, 0x6EF64F26, 0x6CF66DF6, 0x000B6BF6, +0x000B69F6, 0x000BE000, 0x2FE6E000, 0x7FEC4F22, +0x6E436253, 0xBFD165F3, 0xBFC66423, 0xBFC464E3, +0xD40564F3, 0x0009BFC1, 0x4F267F14, 0x6EF6000B, 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+0x8974C801, 0xEE105163, 0xDC638512, 0xC9036603, +0x85136403, 0x4021600D, 0xC93F4021, 0x8D2030E3, +0xD7696503, 0x62704408, 0x44004408, 0x22284500, +0x345C8F0C, 0x6043D265, 0x625D052D, 0x60294219, +0x207D670E, 0x605C81F6, 0x81F8A00B, 0x6043D260, +0x685D052D, 0x60894819, 0x209D690E, 0x605C81F6, +0xD75C81F8, 0x22286272, 0xE0FF8902, 0x81F8600C, +0xEEFF85F8, 0x6EEC650D, 0x8B0F35E0, 0x4E0BDE45, +0x540364B3, 0xBF7BE502, 0xD4536803, 0x410BD147, +0xD7526583, 0xD452E901, 0x2792A020, 0x26E9EEFC, +0x81126063, 0x946E8513, 0x81132049, 0x45088512, +0x62036953, 0xE50885F6, 0x8112202B, 0x45188513, +0x8113209B, 0xD4478514, 0x8114205B, 0x851161B2, +0x811120E9, 0x602162B2, 0x2201CB01, 0x00094C0B, +0x56F160B2, 0xCB0152F2, 0xAF7C2A02, 0x85612622, +0xC802DC3A, 0xD938D227, 0x8D0FD82C, 0x420B64B3, +0x65030009, 0x480B6493, 0xE8015E03, 0x85EF2C82, +0x650DD635, 0x64D3460B, 0x0009AF65, 0x0009420B, +0x6E035403, 0xE5088544, 0x45186103, 0x31502159, +0xBF258B03, 0xA007E501, 0x85410009, 0x620DD52B, +0x89012258, 0xE500BF1C, 0x480B6493, 0xD42865E3, +0xE801D611, 0x2C82460B, 0x0009AF45, 0x7B0862F1, +0x2F217201, 0xEE0362F1, 0x31E7612D, 0xAF2E8901, +0x7F140009, 0x6EF64F26, 0x6CF66DF6, 0x6AF66BF6, +0x000B69F6, 0xFE0368F6, 0x002018B8, 0x002028E4, +0x002028EC, 0x00200AE0, 0x00200E2A, 0x002028B4, +0x00200B62, 0x001E2130, 0x00202AD4, 0x00200AFE, +0x001C3D30, 0x00202AD8, 0x002028C4, 0x00202034, +0x001C3D00, 0x00202AE4, 0x00202AF0, 0x002029D4, +0x00202A54, 0x00202900, 0x002028BC, 0x001E212C, +0x00202ADC, 0x00202AE0, 0x00200E8A, 0x00008000, +0x00202AEC, 0x4F222FE6, 0x6E22D20D, 0xC84060E3, +0x22E28D02, 0x0009BE7A, 0x4218E240, 0x89012E28, +0x0009BE76, 0xC80560E3, 0xBECB8901, 0x60E30009, +0x8902C802, 0xAE734F26, 0x4F266EF6, 0x6EF6000B, +0x001C3510, 0x080A0C0E, 0x00020406, 0x1A1C1E20, +0x12141618, 0x2E303234, 0x26282A2C, 0x3A3C3E40, +0x6C625648, 0x41112F26, 0xE2208F18, 0x890B3123, +0x321CD204, 0xD1026220, 0x412B312C, 0x00090009, +0x0020205E, 0x00202014, 0x000BE000, 0x400062F6, +0x40004000, 0x40004000, 0x40004000, 0x62F6000B, +0x40004000, 0x40004000, 0x40004000, 0x40184000, +0x62F6000B, 0x40004000, 0x40004000, 0x40004000, +0x40284000, 0x62F6000B, 0x40004000, 0x40184000, +0x000B4028, 0xC90F62F6, 0x40054005, 0x40054005, +0x62F6000B, 0x4005C907, 0x40054005, 0x62F6000B, +0x4005C903, 0x000B4005, 0xC90162F6, 0x000B4005, +0x000062F6, 0x080A0C0E, 0x00020406, 0x1A1C1E20, +0x12141618, 0x2E303234, 0x26282A2C, 0x3A3C3E40, +0x6C625648, 0x41112F26, 0xE2208F18, 0x890B3123, +0x321CD204, 0xD1026220, 0x412B312C, 0x00090009, +0x0020211E, 0x002020D4, 0x000BE000, 0x400162F6, +0x40014001, 0x40014001, 0x40014001, 0x62F6000B, +0x40014001, 0x40014001, 0x40014001, 0x40194001, +0x62F6000B, 0x40014001, 0x40014001, 0x40014001, +0x40294001, 0x62F6000B, 0x40014001, 0x40194001, +0x000B4029, 0x400462F6, 0x40044004, 0xC90F4004, +0x62F6000B, 0x40044004, 0xC9074004, 0x62F6000B, +0x40044004, 0x000BC903, 0x400462F6, 0x000BC901, +0x000062F6, 0x3622E218, 0x67438F12, 0x0009A004, +0x76FF6254, 0x74012420, 0xC8036053, 0x60438BF8, +0x8902C803, 0x422BD22B, 0xD22B0009, 0x0009422B, +0x2FE66473, 0x8D4A3450, 0x27786763, 0x62438947, +0x227B225B, 0xC9016023, 0x8D203452, 0x2EE86E03, +0x60238B15, 0x8B08C803, 0x47096643, 0x47106256, +0x8FFB2622, 0xA0327604, 0x47010009, 0x61436673, +0x46106255, 0x8FFB2121, 0xA0287102, 0x66430009, +0x47106254, 0x8FFB2620, 0xA0207601, 0x61430009, +0x2EE8357C, 0x8F15317C, 0x60236653, 0x8B07C803, +0x76FC4709, 0x47106262, 0x21268FFB, 0x0009A00F, +0x65634701, 0x75FE6673, 0x46106251, 0x21258FFB, +0x0009A005, 0x626076FF, 0x8FFB4710, 0x60432124, +0x6EF6000B, 0x00202306, 0x002027B2, 0xE21E2FE6, +0x67633626, 0x8D1B6153, 0x3E106E43, 0x3E128916, +0x65E38908, 0x3672E600, 0x62148910, 0x25207601, +0x7501AFF9, 0x317C64E3, 0x6513347C, 0xE600A004, +0x625075FF, 0x24247601, 0x8BF93672, 0x60E3A011, +0x890831E2, 0x327C6213, 0x8B0432E6, 0x651364E3, +0xA0086673, 0xD28F6EF6, 0x651364E3, 0x422B6673, +0x000B6EF6, 0xE2046EF6, 0x67433622, 0x8F10356C, +0xA004346C, 0x75FF0009, 0x76FF6250, 0x60532424, +0x8BF8C803, 0xC8036043, 0xA1058901, 0xA2770009, +0xA2990009, 0x2FB60009, 0x2FD62FC6, 0x7FE42FE6, +0x6C636043, 0x66521F62, 0xC9037504, 0x1F516E53, +0x45086503, 0xE1FC6D43, 0x2D194500, 0x1F732558, +0x1F651F44, 0x2FD28D0B, 0x88086053, 0x88108923, +0x8818895B, 0xA0898B01, 0xA0BD0009, 0x62630009, +0x2D22E600, 0x7CFC7D04, 0xEB10A00D, 0xE60064E6, +0x7CF065E6, 0x62E261E6, 0x1D512D42, 0x1D231D12, +0x7E047D10, 0x3CB21FE1, 0x1F6589F0, 0x2FD21FC2, +0xA0A11FE6, 0x64D21FD4, 0x44286263, 0x44294418, +0x42184419, 0x4629242B, 0x2D424619, 0x65637D04, +0xA0217CFD, 0x67E6EB10, 0x62E67CF0, 0x64E66673, +0x256B4618, 0x2D5261E2, 0x65234729, 0x45184719, +0x4229275B, 0x42191D71, 0x47186743, 0x4429227B, +0x44196713, 0x247B4718, 0x1D431D22, 0x41194129, +0x65137D10, 0x1FE17E04, 0x89DC3CB2, 0x1FE67EFF, +0x1FC21F55, 0xA0672FD2, 0x6CF21FD4, 0x66C257F5, +0x46286273, 0x42284629, 0x2C62262B, 0x7C045DF2, +0x7DFE4729, 0xA01CEB10, 0x65E65EF1, 0x66E66273, +0x47286753, 0x6763227B, 0x452961E6, 0x257B4728, +0x2C2264E6, 0x65131C51, 0x45284629, 0x1C62265B, +0x41296643, 0x216B4628, 0x44291C13, 0x67437C10, +0x3DB27DF0, 0x1FD289E1, 0x7EFEA034, 0x51F56CF2, +0x621366C2, 0x42284618, 0x42184619, 0x2C62262B, +0x7C045DF2, 0x7DFF4119, 0xA01FEB10, 0x65E65EF1, +0x64E67DF0, 0x42286253, 0x421867E6, 0x66E6212B, +0x61432C12, 0x45194128, 0x251B4118, 0x65731C51, +0x44194528, 0x245B4518, 0x64631C42, 0x47194428, +0x274B4418, 0x46191C73, 0x61637C10, 0x89DE3DB2, +0x7EFD1FD2, 0x1FC41FE6, 0x5DF2E704, 0xA00D5EF6, +0x62E451F4, 0x66E47DFC, 0x65E464E4, 0x71012120, +0x71012160, 0x71012140, 0x71012150, 0x89F03D72, +0x66D357F3, 0x641365E3, 0x6EF67F1C, 0x6CF66DF6, +0x6BF6A190, 0x00202194, 0x2FC62FB6, 0x2FE62FD6, +0x60437FE4, 0x6C63C903, 0x66031F62, 0x460875FC, +0x61526E43, 0x4600E2FC, 0x26682E29, 0x1F441F73, +0x1F516D53, 0x8D0B1F15, 0x60632FE2, 0x891F8808, +0x89538810, 0x8B018818, 0x0009A081, 0x0009A0B9, +0xEB10A00D, 0x52D37DF0, 0x54D156D2, 0x2E1665D2, +0x2E662E26, 0x2E427EFC, 0x1FD16153, 0x3CB27CF0, +0x7D0489F0, 0x1F151FD6, 0x2FE21FC2, 0x1FE4A0A1, +0x621366E2, 0x42294619, 0x42194618, 0x2E62262B, +0x7CFF4118, 0xEB10A021, 0x54D37DF0, 0x624357D2, +0x42194229, 0x55D1212B, 0x2E1666D2, 0x41296173, +0x41194418, 0x2E46241B, 0x44296453, 0x44194718, +0x2E76274B, 0x47296763, 0x47194518, 0x257B7EFC, +0x46182E52, 0x1FD16163, 0x3CB27CF0, 0x7D0389DC, +0x1F151FD6, 0x2FE21FC2, 0x1FE4A06B, 0x57F56EF2, +0x627366E2, 0x46284629, 0x262B4229, 0x2E625CF2, +0x7CFE4728, 0xA01BEB10, 0x7DF05DF1, 0x55D251D3, +0x46296613, 0x54D1276B, 0x2E7662D2, 0x41286753, +0x217B4729, 0x61432E16, 0x41294528, 0x2E56251B, +0x44286523, 0x245B4529, 0x42282E46, 0x7CF06723, +0x89E23CB2, 0x1FD67D02, 0xA03A1FC2, 0x67F21FE4, +0x657251F5, 0x45296213, 0x45284519, 0x42194518, +0x5CF2252B, 0x41282752, 0x7CFD4118, 0xA022EB10, +0x7DF05DF1, 0x54D256D3, 0x45196563, 0x52D14628, +0x4618215B, 0x6ED26543, 0x45192716, 0x265B4428, +0x65436163, 0x45186423, 0x42284419, 0x4218254B, +0x271664E3, 0x44196623, 0x264B2756, 0x4E282766, +0x61E34E18, 0x3CB27CF0, 0x7D0189DB, 0x1FC21FD6, +0xE7041F74, 0x51F45DF2, 0x5EF6A00D, 0x84E27EFC, +0x620364E0, 0x7DFC84E1, 0x84E36503, 0x21646603, +0x21542124, 0x3D722144, 0x57F389F0, 0x641366D3, +0x7F1C65E3, 0x6DF66EF6, 0xA09D6CF6, 0x2F866BF6, +0x2FA62F96, 0x2FC62FB6, 0x2FE62FD6, 0x614374E0, +0x6A636873, 0x6B56E920, 0x6C567AE0, 0x6D567120, +0x6E563A92, 0x64566756, 0x62566656, 0x11C121B2, +0x11E311D2, 0x11451174, 0x8DEC1166, 0x71201127, +0x6613A004, 0x7AFF6254, 0x76012620, 0x8BF92AA8, +0x6EF66083, 0x6CF66DF6, 0x6AF66BF6, 0x000B69F6, +0x2F8668F6, 0x2FA62F96, 0x2FC62FB6, 0x2FE62FD6, +0x6A636873, 0x75E0E920, 0x56565257, 0x57545155, +0x5D525E53, 0x6B525C51, 0x24662426, 0x24762416, +0x7AE024E6, 0x24C624D6, 0x8DEC3A92, 0x66A324B6, +0x6EF66783, 0x6CF66DF6, 0x6AF66BF6, 0xA04369F6, +0x2FE668F6, 0xC8046063, 0x8D046E63, 0x62166153, +0x24227EFC, 0x60E37404, 0x8908C818, 0x71046513, +0x62526616, 0x24227EF8, 0xAFF41461, 0xE2047408, +0x65133E22, 0x66E38D02, 0x6EF6A01C, 0x6EF6AF87, +0xC8046063, 0x61638D04, 0x625275FC, 0x242671FC, +0xC8186013, 0x75F88906, 0x66525251, 0x24662426, +0x71F8AFF6, 0x3122E204, 0x66138F02, 0x0009AFA1, +0x0009A00A, 0x0009A004, 0x76FF6254, 0x74012420, +0x8BF92668, 0x6073000B, 0x0009A004, 0x625075FF, +0x242476FF, 0x8BF92668, 0x6073000B, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x544F0D0A, 0x46205355, 0x00003A57, 0x2072614D, +0x32203232, 0x20373030, 0x353A3731, 0x37333A32, +0x00000000, 0x00000D0A, 0x00000043, 0x61766E49, +0x2064696C, 0x72657375, 0x20726F20, 0x2079656B, +0x00214449, 0x6E6B6E55, 0x206E776F, 0x6D6D6F63, +0x3D646E61, 0x00000000, 0x61437748, 0x7262696C, +0x6F697461, 0x6620206E, 0x0A6C6961, 0x0000000D, +0x73696F4E, 0x61432065, 0x7262696C, 0x6F697461, +0x6166206E, 0x21216C69, 0x00000D0A, 0x00000D0A, +0x00000042, 0x000000FF, 0x00020001, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x010E010D, 0x00020003, 0x01090108, +0x0002010A, 0x00030002, 0x02020201, 0x02040203, +0x02060205, 0x02080207, 0x020A0209, 0x020C020B, +0x020E020D, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x010E010D, 0x00FF010F, 0x01090108, +0x010B010A, 0x00030002, 0x02020201, 0x02040203, +0x02060205, 0x02080207, 0x020A0209, 0x020C020B, +0x020E020D, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00000072, 0x00205220, 0x00000046, +0x00000059, 0x73204142, 0x003D7165, 0x00000074, +0x00000000, 0x02000112, 0x40FFFFFF, 0x12210ACE, +0x20104890, 0x02090100, 0x0101002E, 0x09FA8000, +0x04000004, 0x000000FF, 0x02010507, 0x07000200, +0x00028205, 0x05070002, 0x00400383, 0x04050701, +0x01004003, 0x002E0209, 0x80000101, 0x000409FA, +0x00FF0400, 0x05070000, 0x00400201, 0x82050700, +0x00004002, 0x03830507, 0x07010040, 0x40030405, +0x03040100, 0x030C0409, 0x0079005A, 0x00410044, +0x03180053, 0x00530055, 0x00320042, 0x0030002E, +0x00570020, 0x0041004C, 0x0000004E, 0x00000000, +0x00000000, 0x00000709, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, }; + +const u32_t zcFwImageSize=11204; diff --git a/drivers/staging/otus/hal/hpfwu_OTUS_RC.c b/drivers/staging/otus/hal/hpfwu_OTUS_RC.c new file mode 100644 index 000000000000..089d3e0ad853 --- /dev/null +++ b/drivers/staging/otus/hal/hpfwu_OTUS_RC.c @@ -0,0 +1,715 @@ +/* + * Copyright (c) 2007-2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include "cprecomp.h" + +const u32_t zcFwImage[] = { +0x0009000B, 0x4F222FE6, 0xDE287FFC, 0xE114D728, +0x1E13D428, 0x1E4C470B, 0x0009B018, 0xA0039543, +0x3652E600, 0x76018D04, 0xC84060E2, 0x2F028DF9, +0xDE22D421, 0x00094E0B, 0x4E0BD421, 0xD4210009, +0x00094E0B, 0x4F267F04, 0x6EF6A022, 0xD11E4F22, +0x0009410B, 0x440BD41D, 0xD51D0009, 0x0009450B, +0xE1FFD71C, 0xD21C611D, 0x50292712, 0xCB01E1FF, +0xD61BD41A, 0x22121209, 0xE5011211, 0x2452E200, +0xD5182622, 0x970FD618, 0x4F262572, 0x2620000B, +0xDD17DC16, 0x4C0BDE17, 0x4D0B0009, 0x4E0B0009, +0xAFF80009, 0x27100009, 0x00000640, 0x001C001C, +0x002008EA, 0x0000B38E, 0x002028DC, 0x00200DA6, +0x002028E8, 0x00202900, 0x00200C6C, 0x00200EA2, +0x00200940, 0x001C3510, 0x001C3624, 0x001E212C, +0x00202894, 0x0020288C, 0x002027F0, 0x00200B68, +0x00201F74, 0x00201734, 0x2FD62FC6, 0x4F222FE6, +0xDEA17FA4, 0x61E0E01C, 0x7D016DE3, 0x61D00F14, +0xD59FD49E, 0x450BE020, 0xE0200F14, 0xE78004FC, +0x604C66E2, 0x7D7F677C, 0x1F693070, 0x2D628F17, +0x01FCE01C, 0x641CE500, 0xD797DE96, 0x3243625D, +0xA21A8B01, 0x655D0009, 0x31EC6153, 0xE0286C10, +0x6D530FC4, 0x3D7C62CE, 0xAFEF2D20, 0x20087501, +0xE01C8B15, 0xE50001FC, 0xD78BDE8A, 0x641CA00A, +0x6C53655D, 0x66C23CEC, 0x66626253, 0x2262327C, +0x1F697504, 0x3243625D, 0xA1F68BF2, 0x88012D10, +0xE01C8B16, 0xE40001FC, 0x671C2D40, 0x624DDE7D, +0x8B013273, 0x0009A1E9, 0x62E3644D, 0x72046D43, +0x3DEC6143, 0x65D2312C, 0x74086C12, 0x25C2AFEF, +0x8B188804, 0x01FCE01C, 0x2D40E400, 0xDE71671C, +0x3273624D, 0xA1D08B01, 0x644D0009, 0x62E36D43, +0x65D23DEC, 0x61437204, 0x6612312C, 0x74086C52, +0xAFED2C69, 0x880525C2, 0xE01C8B18, 0xE40001FC, +0x671C2D40, 0x624DDE63, 0x8B013273, 0x0009A1B5, +0x6C43644D, 0x3CEC62E3, 0x720465C2, 0x3D2C6D43, +0x615266D2, 0x216B7408, 0x2512AFED, 0x8B138830, +0xE200DE58, 0x64E22D20, 0x8B042448, 0x420BD257, +0xA19A0009, 0x55E10009, 0x57E356E2, 0xDD545CE4, +0x2FC64D0B, 0x7F04A191, 0x89018828, 0x0009A0EA, +0xE143DE4C, 0x622D62E1, 0x8F033217, 0x56FB1FEB, +0x2621E240, 0x8B013217, 0x0009A0D5, 0xE1015EFB, +0x301685E1, 0xA0CE8B01, 0xE4010009, 0x2D4055FB, +0x6451B179, 0xE14357FB, 0xE0546271, 0x3517652D, +0x0F568D41, 0x3563E640, 0xE6008B05, 0x0F65E034, +0xA00FE11A, 0x615372C0, 0x41214121, 0x41214121, +0x45214121, 0x45214521, 0xC9036053, 0xE0346603, +0x71180F65, 0x2209E007, 0x641DE030, 0x0F2565F3, +0x1F4EB1F1, 0x04FDE034, 0x674DE030, 0x47080CFD, +0x607361CD, 0x4108D22B, 0xE00F0CFE, 0x1F1F420B, +0x2CD96D07, 0x5EFB6073, 0x85E20FC6, 0x420B51FF, +0x2C0B600D, 0x54FE6073, 0xB1BB0FC6, 0xE05465F3, +0x652D62E1, 0xE6400F56, 0x89623563, 0xE050E100, +0x60230F15, 0x4008C903, 0x6D034000, 0xE0406103, +0xE0440FD6, 0xD217EEFF, 0x6EEC0FF6, 0x0F26E058, +0x60E3420B, 0x42216253, 0x42214221, 0x66234221, +0x326C4200, 0x45214200, 0xE0486707, 0x0F764521, +0xC9036053, 0x40085CFB, 0x7C0630FC, 0x6E036D2D, +0x1FD51FC6, 0x1F04A02E, 0x00117D00, 0x00202904, +0x00200DA6, 0x00117D04, 0x00117D84, 0x00200700, +0x0020074C, 0x00201FD4, 0x0FD6E04C, 0x05FEE044, +0x64D3B189, 0x64E2E048, 0xE04006FE, 0x2E422469, +0x01FE67C4, 0x667CE058, 0x420B02FE, 0x240B6063, +0x05FEE044, 0xB15D2E42, 0xE05064D3, 0x7D0101FD, +0x0F157101, 0x02FDE050, 0x3262E606, 0x56FB8BDC, +0x55FB6261, 0x85514200, 0x302C750C, 0x6103701B, +0x64F3E600, 0xE704A004, 0x76016256, 0x74042422, +0x3273626D, 0x65F38BF8, 0x641DB13C, 0xB0D256FB, +0xA0AA6461, 0xD4880009, 0xE201D588, 0x2D20450B, +0x0009A0A3, 0x8B078829, 0xE200DE85, 0x66E22D20, +0x646DB0A1, 0x0009A099, 0x622CE281, 0x8B3D3020, +0xD680E738, 0xE0442D70, 0xE0480C6E, 0x6E621DC1, +0x51611DE2, 0x54621D13, 0x55651D44, 0x57631D55, +0x5C661D76, 0x0E6E1DC7, 0x1DE8E040, 0xE050016E, +0x54641D19, 0x056E1D4A, 0x1D5BE04C, 0xE054076E, +0x0C6E1D7C, 0x1DCDE058, 0xE044026E, 0xED001D2E, +0xE04806D6, 0x16D126D2, 0x16D516D2, 0x16D616D3, +0xE04006D6, 0xE05006D6, 0x06D616D4, 0x06D6E04C, +0x06D6E054, 0x06D6E058, 0x1F29A057, 0x622CE282, +0x89313020, 0x05FCE020, 0x625CE683, 0x3260666C, +0xD65D8B07, 0x2650E500, 0x52617680, 0xA044D65B, +0xE6902622, 0x3260666C, 0xD2578B16, 0xE500D658, +0x60622250, 0xCB20D257, 0xE6052602, 0xD6562262, +0x2252460B, 0x420BD255, 0xD2550009, 0x2262E601, +0x4618D254, 0x2262A029, 0xD254D453, 0xD4546542, +0x0009420B, 0x0009A021, 0xE524D647, 0xD5452650, +0x16215257, 0x16225258, 0x16235259, 0x1624525A, +0x1625525B, 0x1626525C, 0x1627525D, 0x1628525E, +0x1F29525F, 0xE2001629, 0x15281527, 0x152A1529, +0x152C152B, 0x152E152D, 0x7F5C152F, 0x6EF64F26, +0x000B6DF6, 0x4F226CF6, 0xE240614D, 0x89173123, +0x3127E21F, 0xD43B8908, 0xE001D53B, 0x6642450B, +0x26796707, 0x2462A00C, 0x3127E23F, 0xD7358908, +0x71E0D635, 0x460BE001, 0x62075571, 0x17512529, +0x000B4F26, 0x4F220009, 0xE240614D, 0x89153123, +0x3127E21F, 0xD42B8907, 0x6642D22B, 0xE001420B, +0xA00B260B, 0xE23F2462, 0x89073127, 0xD626D725, +0x71E05571, 0xE001460B, 0x1751250B, 0x000B4F26, +0xE6400009, 0x46284618, 0x6252D520, 0x89FC2268, +0x0009000B, 0x4618E680, 0xD51C4628, 0x22686252, +0x000B89FC, 0xA0010009, 0x7201E200, 0x8BFC3242, +0x0009000B, 0x4618E680, 0xD5154628, 0x22686252, +0x000B8BFC, 0x00000009, 0x00202908, 0x00200DA6, +0x00117D04, 0x002027F8, 0x00117D80, 0x0020288C, +0x001C3500, 0x001D4004, 0x00200EA2, 0x00200940, +0x001E212C, 0x001C3D28, 0x00117D00, 0x00200E06, +0x00202920, 0x001C3704, 0x00201FD4, 0x001C373C, +0x001C3700, 0x4F222FE6, 0x6E537FFC, 0x2F42BFCA, +0xD61561E2, 0x1615E280, 0x421854E1, 0x55E21646, +0x16574228, 0x6EF257E3, 0x2E2B1678, 0x7F0426E2, +0xAFA74F26, 0x2FC66EF6, 0x2FE62FD6, 0xDD0A4F22, +0xBFAF6C53, 0xBF946E43, 0xBFAB2DE2, 0x51D50009, +0x54D62C12, 0x55D71C41, 0x56D81C52, 0x4F261C63, +0x6DF66EF6, 0x6CF6000B, 0x001C370C, 0x0009A0C0, +0xD17B4F22, 0xD47B92B6, 0x2122B00D, 0x97B2E605, +0xB02295B2, 0xB0366463, 0xB0360009, 0xB0390009, +0xA0680009, 0x4F124F26, 0xD1734F02, 0x94A43145, +0x4609060A, 0x46094609, 0x00293646, 0xD76CD56F, +0x2500CA01, 0x4F062762, 0x4F16000B, 0xBFEA4F22, +0xB01F0009, 0xA04E0009, 0x2FE64F26, 0x6E63D168, +0x44186612, 0x4528928A, 0x26294408, 0x44084500, +0x4400265B, 0x4708264B, 0x47082162, 0x27EBD161, +0x000B2172, 0x000B6EF6, 0xD25F0009, 0xE40A9677, +0x2262AFB4, 0x2FC62FB6, 0x2FE62FD6, 0xDC5B4F22, +0x2C22E201, 0xBFA9E40A, 0x60C27C44, 0xCB01ED00, +0x60C22C02, 0xC901EB64, 0x6E03A008, 0x89073DB2, +0xE40160C2, 0xBF99C901, 0x7D016E03, 0x8BF52EE8, +0x8B033DB2, 0xD24FD44E, 0x0009420B, 0x4F26E40A, +0x6DF66EF6, 0xAF896CF6, 0x44116BF6, 0x604B8F01, +0x000B6043, 0x2FB60009, 0x2FD62FC6, 0x4F222FE6, +0xDC457FFC, 0x60C2ED00, 0xCB02EB64, 0x60C22C02, +0xC9022F02, 0x6E03A009, 0x89083DB3, 0xE46460C2, +0xC9022F02, 0x6E03BF6A, 0x2EE87D01, 0xD73B8BF4, +0x617251C1, 0xDE3BDC3A, 0xD23CD13B, 0x64C23DB3, +0x651264E2, 0x65228F09, 0xD232D439, 0x4F267F04, +0x6DF66EF6, 0x422B6CF6, 0x7F046BF6, 0x6EF64F26, +0x6CF66DF6, 0x6BF6000B, 0x5651D532, 0x46286052, +0x306C000B, 0x5288096C, 0x09B45BB4, 0x03C41FFF, +0x2FC62FB6, 0x2FE62FD6, 0x4F124F22, 0xBFEB4F02, +0x6B036E43, 0xDD18DC28, 0x0009BFE6, 0x3C0530B8, +0x4609060A, 0x46014609, 0x020A3D65, 0x42094209, +0x32E24209, 0x4F068BF0, 0x4F264F16, 0x6DF66EF6, +0x000B6CF6, 0x2FE66BF6, 0xDE1C4F22, 0xE500E102, +0x2E12E403, 0x2E52BFD4, 0x4618E606, 0xE403E700, +0x2E722E62, 0xAFCB4F26, 0x000B6EF6, 0x00000009, +0x00202890, 0x0024CDE0, 0x10624DD3, 0x00202A8C, +0x001C5814, 0x001C59D0, 0x001C5804, 0x001C581C, +0x00202934, 0x00200DA6, 0x001C5860, 0x001C6864, +0x001C7864, 0x001C59BC, 0x001C69BC, 0x001C79BC, +0x0020294C, 0x001C1040, 0xCCCCCCCD, 0x001D4004, +0x2F962F86, 0x2FB62FA6, 0x2FD62FC6, 0x4F222FE6, +0xE4007FE4, 0x4528E510, 0x67436C43, 0xE107A00F, +0x6043644D, 0x0F564008, 0xEE0060C3, 0x815125C1, +0x81538152, 0x157315E2, 0x751415E4, 0x624D7401, +0x8BED3213, 0xDA6F51F1, 0x1A1154F2, 0xD16E2A12, +0x57F455F3, 0x6DF258F5, 0x1141D96C, 0x11532142, +0x11751152, 0x11871174, 0x52F61186, 0x19D1D668, +0xD86829D2, 0xDA68E950, 0x1621EBB4, 0x6BBC2622, +0xA0214908, 0x6EEDEE00, 0x61E36DE3, 0x41084D08, +0x31EC3DEC, 0x41084D08, 0x60C33D8C, 0xE7904108, +0x81D12DC1, 0x41086093, 0x81D2677C, 0x31AC60C3, +0x3472E200, 0x1DD281D3, 0xD4551D13, 0x1D248D01, +0xB03AD450, 0x7E0165D3, 0x34B264ED, 0xD14D8BDB, +0x6512DB52, 0x4529D24D, 0x64121B51, 0x674DD14A, +0x67222B72, 0x4729D64E, 0x69221B73, 0x689D2FD2, +0x69121B82, 0x5A122692, 0x5B1416A2, 0x16B4DA44, +0x16C65C16, 0x16EA6EA2, 0x4F267F1C, 0x6DF66EF6, +0x6BF66CF6, 0x69F66AF6, 0x68F6000B, 0x60616642, +0x8D04C803, 0x6061E500, 0x8802C903, 0x52628B03, +0x51246563, 0x000B2412, 0x2FD66053, 0x4F222FE6, +0x6E537FEC, 0xE5506253, 0xE4006D43, 0xA0014508, +0x5224E101, 0x22116043, 0x81238121, 0x81226053, +0x362056E2, 0xD22F8BF5, 0x64F316E4, 0x420BE614, +0x65E165E3, 0x2549E4FC, 0x61F12E51, 0x214965F3, +0x54D12F11, 0x410BD127, 0x57D1E614, 0xCB016071, +0x1DE12701, 0x4F267F14, 0x000B6EF6, 0x2FD66DF6, +0x4F222FE6, 0x6E537FEC, 0xE5FC6653, 0x60616D43, +0xCB012059, 0x52E22601, 0x8B063260, 0x51E212E4, +0x8B0431E0, 0xA00252D1, 0xAFF01E22, 0xD2155664, +0xE61464F3, 0x65E3420B, 0xE1FC67E1, 0x2E712719, +0x54D167F1, 0xD10F2719, 0xE61465F3, 0x2F71410B, +0x602152D1, 0x2201CB01, 0x7F141DE1, 0x6EF64F26, +0x6DF6000B, 0x0020285C, 0x00202864, 0x00202854, +0x00202884, 0x0010008C, 0x00100EC0, 0x001E2108, +0x001C3D00, 0x00202134, 0x2FC62FB6, 0x2FE62FD6, +0xD6314F22, 0x60D36D62, 0x894DC803, 0xDB30DC2F, +0x0009A02C, 0xC9036061, 0x892B8801, 0xD22DD42B, +0x0009420B, 0x65035603, 0xC8208561, 0xE0508903, +0x720102BE, 0x85620B26, 0x4000600D, 0x4000366A, +0x40004624, 0x206D4624, 0xD423C903, 0x40086E03, +0xD1224000, 0x340C410B, 0x61E3D521, 0xD721E001, +0x450BD221, 0x64E37E30, 0x2702420B, 0x66C252C1, +0x8BCF3620, 0x4E18EE01, 0xA011DB1C, 0x6061EC75, +0x8801C903, 0xD4198910, 0x460BD612, 0xD4180009, +0x470BD718, 0xD2136503, 0x64C3D113, 0x22E2410B, +0x66B252B1, 0x8BEA3620, 0xC80460D3, 0xD2128906, +0x6EF64F26, 0x6CF66DF6, 0x6BF6422B, 0x6EF64F26, +0x6CF66DF6, 0x6BF6000B, 0x001E2100, 0x0020285C, +0x002027F8, 0x00200A5C, 0x00202864, 0x00200ADE, +0x00201FD4, 0x001C3D30, 0x00200D6C, 0x00202854, +0x00202884, 0x00200A7A, 0x002000F8, 0xE601D237, +0x1265D537, 0x000B2252, 0xD6361266, 0x88016062, +0xE1018B62, 0xD5342612, 0x5451D134, 0xE0406212, +0x2122324C, 0x54115752, 0x1141347C, 0x57125453, +0x1172374C, 0x52135755, 0x1123327C, 0x56146452, +0x1164364C, 0x54155754, 0x1145347C, 0x56165458, +0x1166364C, 0x6762D626, 0x327C5217, 0x57611127, +0x327C5218, 0x57621128, 0x327C5219, 0x57631129, +0x347C541A, 0x5764114A, 0x347C541B, 0x5765114B, +0x347C541C, 0x5266114C, 0x372C571D, 0x5267117D, +0x342C541E, 0x5268114E, 0x362C561F, 0xD615116F, +0x041E6262, 0x342C7694, 0xE0440146, 0x061E6262, +0x0166362C, 0x525CE048, 0xD60F051E, 0x0156352C, +0xE0546262, 0x4229051E, 0x0156352C, 0xE0585561, +0x4529061E, 0x0166365C, 0x0009000B, 0x001C1010, +0x0000C34F, 0x001C1028, 0x001C369C, 0x002027F8, +0x001C3CA0, 0x001C36F4, 0x001C3B88, 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+0x27E2A01D, 0x26E9EEFC, 0x81126063, 0x97888513, +0x20794208, 0x85128113, 0x8112208B, 0x202B8513, +0x85148113, 0x4218E208, 0x8114202B, 0x854164C2, +0x814120E9, 0xD45165C2, 0xCB016051, 0x4A0B2501, +0x60C20009, 0x52F356F2, 0x2B02CB01, 0x2622AF8B, +0xD2378561, 0x8D2EC802, 0x420B64C3, 0xD6480009, +0x5E036503, 0x076EE04C, 0x7701D146, 0x60120676, +0x8B058801, 0xEA0C85E1, 0x20AB4A18, 0x81E1A007, +0x88026012, 0x85E18B03, 0x20A9EADF, 0x855181E1, +0x20A9EAFC, 0x60518151, 0xCB01DA28, 0x4A0B64C3, +0x56F22501, 0xD73851F3, 0x85EF2612, 0x470B64D3, +0xAF58650D, 0x420B0009, 0x54030009, 0x85446E03, +0x4A18EA08, 0x30A020A9, 0x8B03DA1A, 0xE501BF16, +0x0009A007, 0xD62D8541, 0x2268620D, 0xBF0D8901, +0xD423E500, 0x420BD218, 0xD72265E3, 0xEE01D428, +0x27E24A0B, 0x0009AF37, 0x68F26083, 0x780181F2, +0x618D7C08, 0x31E7EE03, 0xAF1D8901, 0x7F100009, +0x6EF64F26, 0x6CF66DF6, 0x6AF66BF6, 0x000B69F6, +0xFE0368F6, 0x00201834, 0x00202884, 0x0020288C, +0x00200A5C, 0x00200DA6, 0x00202854, 0x00200ADE, +0x001E2130, 0x00202A70, 0x00200A7A, 0x001C3D30, +0x00202A74, 0x00202864, 0x00201FD4, 0x001C3D00, +0x00202A80, 0x00202A8C, 0x00202970, 0x002029F0, +0x0020285C, 0x001E212C, 0x00202A78, 0x00202A7C, +0x002027F8, 0x002027F4, 0x00200E06, 0x00008000, +0x00202A88, 0x4F222FE6, 0x6E22D20D, 0xC84060E3, +0x22E28D02, 0x0009BE68, 0x4218E240, 0x89012E28, +0x0009BE64, 0xC80560E3, 0xBEB98901, 0x60E30009, +0x8902C802, 0xAE614F26, 0x4F266EF6, 0x6EF6000B, +0x001C3510, 0x080A0C0E, 0x00020406, 0x1A1C1E20, +0x12141618, 0x2E303234, 0x26282A2C, 0x3A3C3E40, +0x6C625648, 0x41112F26, 0xE2208F18, 0x890B3123, +0x321CD204, 0xD1026220, 0x412B312C, 0x00090009, +0x00201FFE, 0x00201FB4, 0x000BE000, 0x400062F6, +0x40004000, 0x40004000, 0x40004000, 0x62F6000B, +0x40004000, 0x40004000, 0x40004000, 0x40184000, +0x62F6000B, 0x40004000, 0x40004000, 0x40004000, +0x40284000, 0x62F6000B, 0x40004000, 0x40184000, +0x000B4028, 0xC90F62F6, 0x40054005, 0x40054005, +0x62F6000B, 0x4005C907, 0x40054005, 0x62F6000B, +0x4005C903, 0x000B4005, 0xC90162F6, 0x000B4005, +0x000062F6, 0x080A0C0E, 0x00020406, 0x1A1C1E20, +0x12141618, 0x2E303234, 0x26282A2C, 0x3A3C3E40, +0x6C625648, 0x41112F26, 0xE2208F18, 0x890B3123, +0x321CD204, 0xD1026220, 0x412B312C, 0x00090009, +0x002020BE, 0x00202074, 0x000BE000, 0x400162F6, +0x40014001, 0x40014001, 0x40014001, 0x62F6000B, +0x40014001, 0x40014001, 0x40014001, 0x40194001, +0x62F6000B, 0x40014001, 0x40014001, 0x40014001, +0x40294001, 0x62F6000B, 0x40014001, 0x40194001, +0x000B4029, 0x400462F6, 0x40044004, 0xC90F4004, +0x62F6000B, 0x40044004, 0xC9074004, 0x62F6000B, +0x40044004, 0x000BC903, 0x400462F6, 0x000BC901, +0x000062F6, 0x3622E218, 0x67438F12, 0x0009A004, +0x76FF6254, 0x74012420, 0xC8036053, 0x60438BF8, +0x8902C803, 0x422BD22B, 0xD22B0009, 0x0009422B, +0x2FE66473, 0x8D4A3450, 0x27786763, 0x62438947, +0x227B225B, 0xC9016023, 0x8D203452, 0x2EE86E03, +0x60238B15, 0x8B08C803, 0x47096643, 0x47106256, +0x8FFB2622, 0xA0327604, 0x47010009, 0x61436673, +0x46106255, 0x8FFB2121, 0xA0287102, 0x66430009, +0x47106254, 0x8FFB2620, 0xA0207601, 0x61430009, +0x2EE8357C, 0x8F15317C, 0x60236653, 0x8B07C803, +0x76FC4709, 0x47106262, 0x21268FFB, 0x0009A00F, +0x65634701, 0x75FE6673, 0x46106251, 0x21258FFB, +0x0009A005, 0x626076FF, 0x8FFB4710, 0x60432124, +0x6EF6000B, 0x002022A6, 0x00202752, 0xE21E2FE6, +0x67633626, 0x8D1B6153, 0x3E106E43, 0x3E128916, +0x65E38908, 0x3672E600, 0x62148910, 0x25207601, +0x7501AFF9, 0x317C64E3, 0x6513347C, 0xE600A004, +0x625075FF, 0x24247601, 0x8BF93672, 0x60E3A011, +0x890831E2, 0x327C6213, 0x8B0432E6, 0x651364E3, +0xA0086673, 0xD28F6EF6, 0x651364E3, 0x422B6673, +0x000B6EF6, 0xE2046EF6, 0x67433622, 0x8F10356C, +0xA004346C, 0x75FF0009, 0x76FF6250, 0x60532424, +0x8BF8C803, 0xC8036043, 0xA1058901, 0xA2770009, +0xA2990009, 0x2FB60009, 0x2FD62FC6, 0x7FE42FE6, +0x6C636043, 0x66521F62, 0xC9037504, 0x1F516E53, +0x45086503, 0xE1FC6D43, 0x2D194500, 0x1F732558, +0x1F651F44, 0x2FD28D0B, 0x88086053, 0x88108923, +0x8818895B, 0xA0898B01, 0xA0BD0009, 0x62630009, +0x2D22E600, 0x7CFC7D04, 0xEB10A00D, 0xE60064E6, +0x7CF065E6, 0x62E261E6, 0x1D512D42, 0x1D231D12, +0x7E047D10, 0x3CB21FE1, 0x1F6589F0, 0x2FD21FC2, +0xA0A11FE6, 0x64D21FD4, 0x44286263, 0x44294418, +0x42184419, 0x4629242B, 0x2D424619, 0x65637D04, +0xA0217CFD, 0x67E6EB10, 0x62E67CF0, 0x64E66673, +0x256B4618, 0x2D5261E2, 0x65234729, 0x45184719, +0x4229275B, 0x42191D71, 0x47186743, 0x4429227B, +0x44196713, 0x247B4718, 0x1D431D22, 0x41194129, +0x65137D10, 0x1FE17E04, 0x89DC3CB2, 0x1FE67EFF, +0x1FC21F55, 0xA0672FD2, 0x6CF21FD4, 0x66C257F5, +0x46286273, 0x42284629, 0x2C62262B, 0x7C045DF2, +0x7DFE4729, 0xA01CEB10, 0x65E65EF1, 0x66E66273, +0x47286753, 0x6763227B, 0x452961E6, 0x257B4728, +0x2C2264E6, 0x65131C51, 0x45284629, 0x1C62265B, +0x41296643, 0x216B4628, 0x44291C13, 0x67437C10, +0x3DB27DF0, 0x1FD289E1, 0x7EFEA034, 0x51F56CF2, +0x621366C2, 0x42284618, 0x42184619, 0x2C62262B, +0x7C045DF2, 0x7DFF4119, 0xA01FEB10, 0x65E65EF1, +0x64E67DF0, 0x42286253, 0x421867E6, 0x66E6212B, +0x61432C12, 0x45194128, 0x251B4118, 0x65731C51, +0x44194528, 0x245B4518, 0x64631C42, 0x47194428, +0x274B4418, 0x46191C73, 0x61637C10, 0x89DE3DB2, +0x7EFD1FD2, 0x1FC41FE6, 0x5DF2E704, 0xA00D5EF6, +0x62E451F4, 0x66E47DFC, 0x65E464E4, 0x71012120, +0x71012160, 0x71012140, 0x71012150, 0x89F03D72, +0x66D357F3, 0x641365E3, 0x6EF67F1C, 0x6CF66DF6, +0x6BF6A190, 0x00202134, 0x2FC62FB6, 0x2FE62FD6, +0x60437FE4, 0x6C63C903, 0x66031F62, 0x460875FC, +0x61526E43, 0x4600E2FC, 0x26682E29, 0x1F441F73, +0x1F516D53, 0x8D0B1F15, 0x60632FE2, 0x891F8808, +0x89538810, 0x8B018818, 0x0009A081, 0x0009A0B9, +0xEB10A00D, 0x52D37DF0, 0x54D156D2, 0x2E1665D2, +0x2E662E26, 0x2E427EFC, 0x1FD16153, 0x3CB27CF0, +0x7D0489F0, 0x1F151FD6, 0x2FE21FC2, 0x1FE4A0A1, +0x621366E2, 0x42294619, 0x42194618, 0x2E62262B, +0x7CFF4118, 0xEB10A021, 0x54D37DF0, 0x624357D2, +0x42194229, 0x55D1212B, 0x2E1666D2, 0x41296173, +0x41194418, 0x2E46241B, 0x44296453, 0x44194718, +0x2E76274B, 0x47296763, 0x47194518, 0x257B7EFC, +0x46182E52, 0x1FD16163, 0x3CB27CF0, 0x7D0389DC, +0x1F151FD6, 0x2FE21FC2, 0x1FE4A06B, 0x57F56EF2, +0x627366E2, 0x46284629, 0x262B4229, 0x2E625CF2, +0x7CFE4728, 0xA01BEB10, 0x7DF05DF1, 0x55D251D3, +0x46296613, 0x54D1276B, 0x2E7662D2, 0x41286753, +0x217B4729, 0x61432E16, 0x41294528, 0x2E56251B, +0x44286523, 0x245B4529, 0x42282E46, 0x7CF06723, +0x89E23CB2, 0x1FD67D02, 0xA03A1FC2, 0x67F21FE4, +0x657251F5, 0x45296213, 0x45284519, 0x42194518, +0x5CF2252B, 0x41282752, 0x7CFD4118, 0xA022EB10, +0x7DF05DF1, 0x54D256D3, 0x45196563, 0x52D14628, +0x4618215B, 0x6ED26543, 0x45192716, 0x265B4428, +0x65436163, 0x45186423, 0x42284419, 0x4218254B, +0x271664E3, 0x44196623, 0x264B2756, 0x4E282766, +0x61E34E18, 0x3CB27CF0, 0x7D0189DB, 0x1FC21FD6, +0xE7041F74, 0x51F45DF2, 0x5EF6A00D, 0x84E27EFC, +0x620364E0, 0x7DFC84E1, 0x84E36503, 0x21646603, +0x21542124, 0x3D722144, 0x57F389F0, 0x641366D3, +0x7F1C65E3, 0x6DF66EF6, 0xA09D6CF6, 0x2F866BF6, +0x2FA62F96, 0x2FC62FB6, 0x2FE62FD6, 0x614374E0, +0x6A636873, 0x6B56E920, 0x6C567AE0, 0x6D567120, +0x6E563A92, 0x64566756, 0x62566656, 0x11C121B2, +0x11E311D2, 0x11451174, 0x8DEC1166, 0x71201127, +0x6613A004, 0x7AFF6254, 0x76012620, 0x8BF92AA8, +0x6EF66083, 0x6CF66DF6, 0x6AF66BF6, 0x000B69F6, +0x2F8668F6, 0x2FA62F96, 0x2FC62FB6, 0x2FE62FD6, +0x6A636873, 0x75E0E920, 0x56565257, 0x57545155, +0x5D525E53, 0x6B525C51, 0x24662426, 0x24762416, +0x7AE024E6, 0x24C624D6, 0x8DEC3A92, 0x66A324B6, +0x6EF66783, 0x6CF66DF6, 0x6AF66BF6, 0xA04369F6, +0x2FE668F6, 0xC8046063, 0x8D046E63, 0x62166153, +0x24227EFC, 0x60E37404, 0x8908C818, 0x71046513, +0x62526616, 0x24227EF8, 0xAFF41461, 0xE2047408, +0x65133E22, 0x66E38D02, 0x6EF6A01C, 0x6EF6AF87, +0xC8046063, 0x61638D04, 0x625275FC, 0x242671FC, +0xC8186013, 0x75F88906, 0x66525251, 0x24662426, +0x71F8AFF6, 0x3122E204, 0x66138F02, 0x0009AFA1, +0x0009A00A, 0x0009A004, 0x76FF6254, 0x74012420, +0x8BF92668, 0x6073000B, 0x0009A004, 0x625075FF, +0x242476FF, 0x8BF92668, 0x6073000B, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x544F0D0A, +0x46205355, 0x00003A57, 0x2072614D, 0x32203232, +0x20373030, 0x353A3431, 0x33353A34, 0x00000000, +0x00000D0A, 0x00000043, 0x61766E49, 0x2064696C, +0x72657375, 0x20726F20, 0x2079656B, 0x00214449, +0x6E6B6E55, 0x206E776F, 0x6D6D6F63, 0x3D646E61, +0x00000000, 0x61437748, 0x7262696C, 0x6F697461, +0x6620206E, 0x0A6C6961, 0x0000000D, 0x73696F4E, +0x61432065, 0x7262696C, 0x6F697461, 0x6166206E, +0x21216C69, 0x00000D0A, 0x00000D0A, 0x00000042, +0x000000FF, 0x00020001, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x010E010D, 0x00020003, 0x01090108, 0x0002010A, +0x00030002, 0x02020201, 0x02040203, 0x02060205, +0x02080207, 0x020A0209, 0x020C020B, 0x020E020D, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x010E010D, 0x00FF010F, 0x01090108, 0x010B010A, +0x00030002, 0x02020201, 0x02040203, 0x02060205, +0x02080207, 0x020A0209, 0x020C020B, 0x020E020D, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00000072, 0x00205220, 0x00000046, 0x00000059, +0x73204142, 0x003D7165, 0x00000074, 0x00000000, +0x02000112, 0x40FFFFFF, 0x12210ACE, 0x20104890, +0x02090100, 0x0101002E, 0x09FA8000, 0x04000004, +0x000000FF, 0x02010507, 0x07000200, 0x00028205, +0x05070002, 0x00400383, 0x04050701, 0x01004003, +0x002E0209, 0x80000101, 0x000409FA, 0x00FF0400, +0x05070000, 0x00400201, 0x82050700, 0x00004002, +0x03830507, 0x07010040, 0x40030405, 0x03040100, +0x030C0409, 0x0079005A, 0x00410044, 0x03180053, +0x00530055, 0x00320042, 0x0030002E, 0x00570020, +0x0041004C, 0x0000004E, 0x00000000, 0x00000000, +0x00000709, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +const u32_t zcFwImageSize=11104; diff --git a/drivers/staging/otus/hal/hpfwu_txstream.c b/drivers/staging/otus/hal/hpfwu_txstream.c new file mode 100644 index 000000000000..2b77cbacc6d6 --- /dev/null +++ b/drivers/staging/otus/hal/hpfwu_txstream.c @@ -0,0 +1,1017 @@ +/* + * Copyright (c) 2007-2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include "cprecomp.h" + +const u32_t zcFwImage[] = { +0x0009000B, 0x4F222FE6, 0xDE947FFC, 0xE114D594, +0x1E13D494, 0x67521E4C, 0xD494D693, 0x37402769, +0x62528F06, 0x7201D692, 0x60602522, 0x2600C93F, +0xD7906152, 0x2512611D, 0x264B6652, 0x2562470B, +0x0009B017, 0xE60095AC, 0xC84060E2, 0x2F028F03, +0x8FF93652, 0xD4887601, 0x4E0BDE88, 0xD4880009, +0x00094E0B, 0x4E0BD487, 0x7F040009, 0xA0524F26, +0x4F226EF6, 0x410BD184, 0xD4840009, 0x0009440B, +0x450BD583, 0xD7830009, 0xD283E1FF, 0x2712611D, +0xD4825029, 0xE1FFCB01, 0x1209E501, 0x12112212, +0xE7202452, 0x4718D57E, 0x2572D27E, 0xD17EE700, +0xD67FD47E, 0xE2012270, 0x24702172, 0xD67D2620, +0x2641E4FF, 0xD57CE600, 0x666DE104, 0x76016063, +0x4000626D, 0x8FF83212, 0xD5780545, 0x2520E201, +0xD278D777, 0xE480E100, 0x22122710, 0x6613D576, +0x666D644C, 0x76046763, 0x375C626D, 0x8FF83243, +0xD5722712, 0xD273D772, 0xE400E101, 0x27102511, +0x000B4F26, 0x7FCC2242, 0xD170D56F, 0xD271DB70, +0x1F51D471, 0xD6717508, 0x1F12D771, 0x1F55710C, +0x1FB975FC, 0x72041F2A, 0x1F13EB10, 0x1F561F44, +0x1F781F67, 0xD86B1F2B, 0xDD6CD96B, 0xDC6CEA00, +0xD26DDE6C, 0x89003A22, 0xD15D7A01, 0x88016010, +0x56F88B03, 0x4218E201, 0xD1682622, 0x0009410B, +0x440BD467, 0xD5670009, 0x0009450B, 0x6010D150, +0x8B108801, 0xE650D14F, 0x46186212, 0x8B083266, +0x56F9D14B, 0x2120E200, 0xCB016062, 0x2602A003, +0x72012710, 0x60822122, 0x89098801, 0xE2C8D15A, +0x622C6612, 0x89033626, 0x6010D158, 0x8BC88801, +0x51F66792, 0x217252F5, 0xD6555191, 0x55FA2212, +0x52FB6462, 0x55612542, 0x2252E400, 0x61436643, +0x05DE6013, 0x36CC4608, 0x07DE2652, 0xC9036071, +0x8B028801, 0x720162E2, 0x74012E22, 0x36B3664C, +0x71048FEE, 0x66C2D147, 0x45286512, 0x265B4518, +0x60822C62, 0x89018801, 0x0009A168, 0x6272D742, +0x8B132228, 0xD42BD741, 0x6772D541, 0x51536242, +0x312C327C, 0x24222228, 0x15138D05, 0x6262D63D, +0xB1627201, 0xD6232622, 0x2622E200, 0x52916692, +0x8B013620, 0x0009A144, 0x6061A06E, 0x001C001C, +0x001D4020, 0x0000B38E, 0xFFFF0000, 0x12340000, +0x001E1015, 0x00201274, 0x002039F4, 0x002018A2, +0x00203A00, 0x00203A18, 0x00201860, 0x0020196C, +0x00201288, 0x001C3510, 0x001C3624, 0x001E212C, +0x002038F4, 0x0020348C, 0x002038FC, 0x00203908, +0x00203914, 0x00203970, 0x00203974, 0x0020391C, +0x0020391D, 0x00203920, 0x00117700, 0x0020398C, +0x0020398A, 0x002034F0, 0x00117710, 0x001C3D30, +0x001C36F8, 0x00117734, 0x001C3684, 0x001C3D00, +0x001C1000, 0x001C1028, 0x00203504, 0x00203924, +0x00117600, 0x00117740, 0x7FFFFFFF, 0x00201730, +0x0020332A, 0x00202334, 0x00203DA4, 0x00203972, +0x002034FC, 0x00203964, 0x001C3D2C, 0x001C36B0, +0x00203494, 0x0011775C, 0x8801C90F, 0xA0CF8901, +0xD1960009, 0x36206212, 0xD4958904, 0x2421E200, +0x2162A0CC, 0x6211D193, 0x89012228, 0x0009A0C3, +0xE202D78F, 0x75016571, 0x3123615D, 0x27518D02, +0x0009A0BC, 0xD28C57F2, 0x62226072, 0x40094019, +0xC90F4009, 0x8F19880A, 0x52F31F2C, 0x40196022, +0x40094009, 0x8808C90F, 0xA0A78901, 0x60630009, +0xCB0154F7, 0xD27E55F2, 0xE7012402, 0xD47FE100, +0x22112572, 0x72016242, 0x2422A098, 0x8B3F8805, +0x602252F3, 0x40094019, 0xC90F4009, 0x8B168802, +0xE4FFD577, 0x644D6752, 0x8B102748, 0x6272D775, +0x8B0C3260, 0x51F255F7, 0xD26DE701, 0x21722562, +0xD571E100, 0x64522211, 0xA0777401, 0x52F32542, +0x40196022, 0x40094009, 0x8805C90F, 0x31B38B6E, +0xD26A8B6C, 0x672254F4, 0x7701D569, 0x61422272, +0x1F1CE640, 0x46182159, 0x8B033160, 0x6262D665, +0x26227201, 0xE200D65A, 0x2621B067, 0x0009A056, +0x3123E220, 0x88038B52, 0x52F38B1E, 0x40196022, +0x40094009, 0x8803C90F, 0xD25B8B16, 0x672254F4, +0x7701D557, 0x61422272, 0x1F1CE640, 0x46182159, +0x8B033160, 0x6262D655, 0x26227201, 0xE200D648, +0x2621B043, 0x0009A010, 0xD452D551, 0xD2446752, +0xE1007701, 0x25723A46, 0x22118F06, 0xEA00D64E, +0x72016262, 0x2622B031, 0x2FB2D54C, 0x95736652, +0xD44A5BF1, 0x36205241, 0x60618910, 0x8B01C803, +0x2B22E201, 0x8FF54510, 0x57F15664, 0x6272E1F0, +0x41284118, 0x2722221B, 0x6BF2A008, 0x6BF2A006, +0xE200D62F, 0xD12F2621, 0x2121E200, 0xD13CE201, +0x66122822, 0x8B012668, 0x0009AE2B, 0x450BD539, +0xD1390009, 0xAE24E600, 0x2F862160, 0x2FA62F96, +0x2FC62FB6, 0x2FE62FD6, 0x7FF44F22, 0xDE34D133, +0x54116212, 0x1F4167E2, 0x2F22D432, 0xD5321F72, +0xD2326743, 0x58417794, 0x69425A42, 0x5B166C72, +0x60526D22, 0xCB20E600, 0xE5402502, 0x626D7601, +0x8BFB3253, 0x55F162F2, 0x11512122, 0xD62855F2, +0x14812E52, 0x249214A2, 0x27C2D426, 0x26D211B6, +0xDA256742, 0xE801D925, 0x490B2A72, 0xE2011A8C, +0x1A2C4218, 0x4F267F0C, 0x6DF66EF6, 0x6BF66CF6, +0x69F66AF6, 0x68F6000B, 0x000007D1, 0x00203984, +0x00203988, 0x0020398E, 0x001C3DC0, 0x0011772C, +0x001C3B88, 0x0020396C, 0x0011773C, 0x00117744, +0x0000F000, 0x00117764, 0x00117748, 0x00117768, +0x0011776C, 0x01FFFFFF, 0x0011774C, 0x002034FC, +0x00203DA4, 0x002024F8, 0x00203972, 0x001C3B9C, +0x001C3D98, 0x001C3700, 0x001C3500, 0x001C5960, +0x001C8960, 0x00203504, 0x001C3D00, 0x0020160C, +0x2F962F86, 0x2FB62FA6, 0x2FD62FC6, 0x4F222FE6, +0xDE957FAC, 0x61E0E014, 0x0F14D494, 0x710161E3, +0xE0186210, 0xD2920F24, 0x0009420B, 0x450BD591, +0x20080009, 0x8F126D03, 0xD28F1F07, 0x6720D48F, +0x657CDD8F, 0x470BD78F, 0xD18F0009, 0x619C6910, +0x46086613, 0x36184608, 0x3D6C4608, 0xE0181FD7, +0xE58004FC, 0x604C66E2, 0x3050655C, 0x2D628F15, +0x01FCE014, 0xDE85E500, 0x641CA008, 0x6753655D, +0x607037EC, 0x39DC6953, 0x80947501, 0x3243625D, +0xD67F8BF4, 0xA34EE200, 0x20082621, 0xE0148B13, +0xE40001FC, 0xA009DE79, 0x644D671C, 0x35EC6543, +0x69436652, 0x39DC6262, 0x74041921, 0x3273624D, +0xA3388BF3, 0x88012D10, 0xE0148B17, 0xE70001FC, +0x6D1C2D70, 0xDE6D1FD4, 0x32D3627D, 0xA32A8B01, +0x677D0009, 0x667365E3, 0x61737504, 0x315C36EC, +0x69126462, 0xAFEF7708, 0x88042492, 0xE0148B18, +0xE40001FC, 0x671C2D40, 0x624DDE60, 0x8B013273, +0x0009A311, 0x6943644D, 0x39EC62E3, 0x72046592, +0x3D2C6D43, 0x615266D2, 0x21697408, 0x2512AFED, +0x8B188805, 0x01FCE014, 0x2D40E400, 0xDE53671C, +0x3273624D, 0xA2F68B01, 0x644D0009, 0x62E36943, +0x659239EC, 0x6D437204, 0x66D23D2C, 0x74086152, +0xAFED216B, 0x88312512, 0xD44A8B3A, 0x6146D94A, +0x75046543, 0x67566442, 0x6E531F48, 0x65527E04, +0x7EE462E2, 0x7E0464E2, 0x6EE21FE9, 0x5EF929E0, +0x7E04D942, 0x1FEA60E2, 0x2900C901, 0xD9406EE2, +0x29E04E09, 0x2F562F26, 0x56FAD93E, 0x6513490B, +0xD13D7F08, 0xE71C6E0D, 0x1DE12D70, 0xDE3B6912, +0x64E21D92, 0x1D43D13A, 0xD23A6512, 0x67221D54, +0x1D75D239, 0x1D666622, 0x6262D638, 0x1D27A2AB, +0x8B398830, 0x6596D92B, 0x67926696, 0x61967904, +0x74E46493, 0x6E436992, 0x1F9B7E04, 0x1FEC6442, +0xD9256EE2, 0x5EFC29E0, 0x7E04D924, 0x1FED60E2, +0x2900C901, 0xD9226EE2, 0x29E04E09, 0x59FC7FFC, +0xDE272F92, 0x2F164E0B, 0xD41F7F08, 0xE21C610D, +0x1D112D20, 0xD2206442, 0xD41C1D42, 0x1D536542, +0x6752D51B, 0xD71B1D74, 0x1D156172, 0x1D666622, +0x6262D61A, 0x1D27A26F, 0x8B358833, 0x490BD919, +0xA268EE00, 0x00002DE0, 0x00117800, 0x00203A1C, +0x002018A2, 0x00202AAC, 0x0020390E, 0x00203A20, +0x00203534, 0x002018EE, 0x0020390D, 0x00117804, +0x0020398C, 0x00117810, 0x00203909, 0x0020390A, +0x0020390B, 0x00200F64, 0x001C5864, 0x001C6864, +0x001C7864, 0x001C59BC, 0x001C69BC, 0x001C79BC, +0x00200FBC, 0x00200FB8, 0x89018828, 0x0009A0C0, +0xE643DEB5, 0x326662E1, 0x1FEE8F02, 0x2E21E240, +0x622D62E1, 0x8B013267, 0x0009A0AA, 0xE50185E1, +0x8B013056, 0x0009A0A4, 0x2D10E101, 0x64E1B225, +0xE64357FE, 0x652D6271, 0x89443567, 0x3563E640, +0xE6008B05, 0x0F65E040, 0xA00FE11A, 0x615372C0, +0x41214121, 0x41214121, 0x45214121, 0x45214521, +0xC9036053, 0xE0406603, 0x71180F65, 0x2209E007, +0x0F25E03C, 0xE044641D, 0xB2A365F3, 0xE33C0F46, +0x853233FC, 0x620DDE95, 0x42086031, 0x6023610D, +0x1323E944, 0x06FE4108, 0xE00F39FC, 0x13144E0B, +0x67075D91, 0x60D32679, 0x0F6654FE, 0x51928542, +0x600D4E0B, 0x60D3260B, 0x0F666492, 0x65F3B237, +0x696156FE, 0xE640659D, 0x89383563, 0xD78359FE, +0x79066591, 0xC9036053, 0x40004008, 0x61036203, +0x0F26E050, 0x470BE0FF, 0x6C07600C, 0x6603605D, +0x46214621, 0x46214621, 0x42006263, 0x4200326C, +0x40214021, 0x4008C903, 0x6D2D30FC, 0xE8006A03, +0xB25765F3, 0x6EA264D3, 0x2EC9E050, 0x66942AE2, +0xD76E01FE, 0x606C470B, 0x2AE22E0B, 0x64D365F3, +0x7801B1FD, 0xEE06628D, 0x8FE932E3, 0x5EFE7D01, +0x61E1E400, 0x410085E1, 0x66E3310C, 0x760C711B, +0xE70465F3, 0x68667401, 0x3A736A4D, 0x8FF92582, +0x65F37504, 0x641DB1E3, 0x64E1B1A4, 0x0009A17B, +0xD45B56F7, 0xEC01D25B, 0x26C0420B, 0x0009A173, +0x06FCE018, 0x8829606C, 0x58F78B08, 0xE400D252, +0x66222840, 0x646DB171, 0x0009A165, 0x666CE681, +0x89013060, 0x0009A0AC, 0xD550D14F, 0x62126A56, +0x212232AC, 0x54116C56, 0x34CC6253, 0x64521141, +0x72085812, 0xD44A384C, 0x68221182, 0x5A136C42, +0x3ACC3C8C, 0x11A324C2, 0x6C2272EC, 0x72105814, +0x118438CC, 0x5A156822, 0x11A53A8C, 0x6A227210, +0xD6405816, 0x118638AC, 0x52176C62, 0x112732CC, +0x5A185861, 0x11A83A8C, 0x5C195A62, 0x11C93CAC, +0x521A5C63, 0x112A32CC, 0x5A1B5864, 0x11AB3A8C, +0x5C1C5A65, 0x11CC3CAC, 0x521D5C66, 0x112D32CC, +0x5A1E5867, 0x11AE3A8C, 0x561F5A68, 0x36ACE840, +0x116FDA2D, 0x6CA2381C, 0x7A946682, 0x286236CC, +0x5C8162A2, 0x18C13C2C, 0x62A27A44, 0x362C5682, +0xD6261862, 0x5A856262, 0x3A2C4229, 0x760418A5, +0x56866262, 0x362C4229, 0x56F71866, 0x2620E238, +0x16C15C81, 0x16226212, 0xE2005C11, 0x551216C3, +0x55151654, 0x55131655, 0x55161656, 0x55821657, +0x65821658, 0x55141659, 0x5584165A, 0x5583165B, +0x5585165C, 0x5586165D, 0x1821165E, 0x11212122, +0x11251122, 0x11261123, 0x28221822, 0x18241124, +0x18251823, 0x1826A0C7, 0x00117804, 0x002033E8, +0x00203A40, 0x002018A2, 0x00203494, 0x001C36A0, +0x002034F0, 0x001C3CA0, 0x001C36F4, 0x001C3B88, +0x666CE682, 0x8B203060, 0xEA2456F7, 0x26A0D194, +0x16C15C17, 0x16225218, 0x16835819, 0x16A45A1A, +0x16C55C1B, 0x1626521C, 0xE200581D, 0x551E1687, +0x551F1658, 0x11271659, 0x11291128, 0x112B112A, +0x112D112C, 0xA08E112E, 0xE683112F, 0x3060666C, +0x52F78B0B, 0xEA00D883, 0x658222A0, 0x7804DC82, +0x62822C52, 0xA07ED681, 0xE6902620, 0x3060666C, +0xDA7F8B06, 0x00094A0B, 0xE20056F7, 0x2620A073, +0x666CE691, 0x8B103060, 0x6222D276, 0x2228622C, +0xD2788904, 0x0009420B, 0x0009A003, 0x420BD276, +0x56F70009, 0xA05EE200, 0xE6922620, 0x3060666C, +0xE0188951, 0xE6B00BFC, 0x666C62BC, 0x8B2A3260, +0x02FCE014, 0x682CEA00, 0x62ADE904, 0x894A3283, +0x6AADDD64, 0x3CDC6CA3, 0x7D046EC2, 0xDB68D467, +0x32DC62A3, 0x4B0BDC67, 0x4C0B6D22, 0xD46664E3, +0x00094B0B, 0x64D34C0B, 0x4B0BD464, 0xE6000009, +0x666D6BE3, 0x76013B6C, 0x3293626D, 0x8FF72BD0, +0xAFDA4D19, 0xE6B57A08, 0x3260666C, 0xD45C8B13, +0x4B0BDB57, 0xD25B0009, 0x6022DB5B, 0xCB20E6FF, +0x2202666D, 0xDB592B62, 0xE014E200, 0x56F72B20, +0xA01002FC, 0xD4562620, 0x6542D256, 0x420BD456, +0xA0080009, 0xDB520009, 0x52B1E600, 0x622CDB53, +0x52F72B21, 0x7F542260, 0x6EF64F26, 0x6CF66DF6, +0x6AF66BF6, 0x000B69F6, 0x4F2268F6, 0xE240614D, +0x89143123, 0x3127E21F, 0x8B09D749, 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+0x0002010A, 0x00030003, 0x02020201, 0x02040203, +0x02060205, 0x02020200, 0x02040203, 0x020C020B, +0x020E020D, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x010E010D, 0x00FF010F, 0x01090108, +0x010B010A, 0x0200010F, 0x02020201, 0x02040203, +0x02060205, 0x02020200, 0x02040203, 0x020C020B, +0x020E020D, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x010E010D, 0x00FF010F, 0x01090108, +0x010B010A, 0x010F010F, 0x02020201, 0x02040203, +0x02060205, 0x02020200, 0x02040203, 0x020C020B, +0x020E020D, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, +0x00FF00FF, 0x00205220, 0x00000046, 0x00000059, +0x73204142, 0x003D7165, 0x49544120, 0x0000204D, +0x00000000, 0x00000000, 0x002E0209, 0x80000101, +0x000409FA, 0x00FF0400, 0x05070000, 0x02000201, +0x82050700, 0x00020002, 0x03830507, 0x07010040, +0x40030405, 0x02090100, 0x0101002E, 0x09FA8000, +0x04000004, 0x000000FF, 0x02010507, 0x07000040, +0x40028205, 0x05070000, 0x00400383, 0x04050701, +0x00004002, 0x00000000, 0x00000000, 0x07090000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +const u32_t zcFwImageSize=15936; diff --git a/drivers/staging/otus/hal/hpfwuinit.c b/drivers/staging/otus/hal/hpfwuinit.c new file mode 100644 index 000000000000..ed80ffafaffc --- /dev/null +++ b/drivers/staging/otus/hal/hpfwuinit.c @@ -0,0 +1,240 @@ +/* + * Copyright (c) 2007-2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include "../80211core/cprecomp.h" + +const u32_t zcFwImage[] = { +0x0009000B, 0x7FFC4F22, 0xD695D494, 0x0009460B, +0xD494E570, 0x4518B01E, 0x89042008, 0xD690D492, +0x462B7F04, 0xB0124F26, 0xD2900009, 0x420BD490, +0xE6000009, 0x949AD58F, 0xC8406052, 0x2F028F03, +0x8FF93642, 0x7F047601, 0x000B4F26, 0xD28A0009, +0x0009422B, 0x2FD62FC6, 0x4F222FE6, 0xD6877FEC, +0x626061F3, 0x2F208461, 0x846280F1, 0x80F27110, +0x6D438463, 0x846480F3, 0x80F46413, 0x6C538465, +0x846680F5, 0x80F6E500, 0xD77D8467, 0x846880F7, +0x80F8EE04, 0x80F98469, 0x80FA846A, 0x80FB846B, +0x80FC846C, 0x80FD846D, 0x80FE846E, 0x80FF846F, +0x6653655C, 0x7501367C, 0x665C6260, 0x242036E3, +0x74018FF6, 0x66F32F16, 0xE7107604, 0xB00D65C3, +0x6E0364D3, 0xD46B7F04, 0x420BD26B, 0x60E36503, +0x4F267F14, 0x6DF66EF6, 0x6CF6000B, 0x2FB62FA6, +0x2FD62FC6, 0x4F222FE6, 0x3F3C933A, 0x4108E141, +0x31FCE200, 0x11733526, 0x21521162, 0x11418D02, +0xE0FFA098, 0x4A18EA01, 0x262066F3, 0x32A27201, +0x76018FFB, 0x6BE3EE00, 0xE0446CF3, 0x00FE4008, +0x450BD556, 0x660361B3, 0x4008E043, 0x6DC004FE, +0x014C6063, 0x31EC3EDC, 0x60E36E1C, 0x7B0107FC, +0x2C703BA2, 0x8FE80FD4, 0xE0427C01, 0xEB004008, +0x70FC07FE, 0x6EB36CB3, 0xA0200AFE, 0x2710EDFF, +0x7C01FEE0, 0x60C36CCC, 0x657002FC, 0x6BBC3B2C, +0x01FC60B3, 0x0F1460C3, 0x0F2460B3, 0x04FC60C3, +0x342C7E01, 0x01FC604C, 0x251A62D3, 0xD43C225A, +0x2750602C, 0x064E4008, 0x2D6A4D19, 0x3EA27701, +0x66D78BDF, 0x4018E001, 0x0F646563, 0x70014519, +0x0F544629, 0x0F647001, 0x70014619, 0x90420F64, +0xE0450EFE, 0xEA014008, 0xE0460FF6, 0x4A184008, +0xED0067F3, 0x0FF637AC, 0x0FF67004, 0xE345E104, +0x7C014308, 0x6CCC33FC, 0x60C36432, 0x5531024C, +0x6BBC3B2C, 0x045C60B3, 0x60C35A32, 0x60B30A44, +0x60C30F24, 0x6A7006FC, 0x606C362C, 0x66E005FC, +0x6A5C64AC, 0x626C24AA, 0x89053420, 0x4D084D08, +0xCB0460D3, 0x600BA006, 0x7D014110, 0x8FD67701, +0xE0007E01, 0x3F3C9308, 0x6EF64F26, 0x6CF66DF6, +0x000B6BF6, 0x01386AF6, 0x00000120, 0x00200D54, +0x002002BE, 0x00102800, 0x00200D64, 0x0010F00A, +0x0010F000, 0x001C001C, 0x00103252, 0x00200DA0, +0x0010FFFC, 0x00200D7C, 0x0020032C, 0x00200370, +0x00200954, 0x0009000B, 0x2FD62FC6, 0x4F222FE6, +0x6D436C53, 0xEE00A004, 0x7E0164D4, 0x644CBFF2, +0x8BF93EC2, 0x6EF64F26, 0x000B6DF6, 0xE5006CF6, +0x6643A002, 0x76017501, 0x22286260, 0xAFE38BFA, +0x2FE60009, 0x75076253, 0xE1086753, 0x6043EE0A, +0x4409C90F, 0x650330E2, 0x8D014409, 0xE630E637, +0x4110365C, 0x8FF22760, 0xE00077FF, 0x000B8028, +0x4F226EF6, 0xBFE47FEC, 0xBFD865F3, 0x7F1464F3, +0x000B4F26, 0x4F22E000, 0xBFDA7FEC, 0x64F365F3, +0x7406BFCD, 0x4F267F14, 0xE000000B, 0x4F222FE6, +0x62537FEC, 0x65F36E43, 0x6423BFCB, 0x64E3BFBF, +0x64F3BFBD, 0xBFBAD403, 0x7F140009, 0x000B4F26, +0x00006EF6, 0x00200DB0, 0x89004011, 0x4111600B, +0x4F228906, 0x611BB004, 0x000B4F26, 0x0009600B, +0x620D2F26, 0x8F413020, 0x40180019, 0x8B0D3016, +0x31043104, 0x31043104, 0x31043104, 0x31043104, +0x890062F6, 0x4119310C, 0x6013000B, 0x41296219, +0x20084018, 0x31048927, 0x31043104, 0x31043104, +0x31043104, 0x31043104, 0x31043104, 0x31043104, +0x31043104, 0x61193104, 0x3204221D, 0x32043204, +0x32043204, 0x32043204, 0x32043204, 0x32043204, +0x32043204, 0x32043204, 0x89003204, 0x4229320C, +0x000B6023, 0xE00062F6, 0x62F6000B, 0x42286213, +0x42244129, 0x42243104, 0x42243104, 0x42243104, +0x42243104, 0x42243104, 0x42243104, 0x42243104, +0x42243104, 0x42243104, 0x42243104, 0x42243104, +0x42243104, 0x42243104, 0x42243104, 0x42243104, +0x89003104, 0x6013310C, 0x62F6000B, 0x2F262F16, +0x51F552F3, 0x52F22129, 0x52F41210, 0x212951F6, +0x121152F2, 0x000B62F6, 0x000061F6, 0x51F32F16, +0x310050F1, 0x51F48B02, 0x310050F2, 0x000B0029, +0x000061F6, 0x51F32F16, 0x310050F1, 0x51F48B06, +0x310050F2, 0xCA010029, 0x61F6000B, 0x000BE001, +0x000061F6, 0x50F0000B, 0x2F262F16, 0xE10052F2, +0x12001211, 0x000B62F6, 0x000061F6, 0x2F162F06, +0x8B264115, 0x3103E040, 0x2F26892B, 0x52F62F36, +0xE02053F5, 0x8B053103, 0xE3006233, 0x89093100, +0x3108A002, 0x8B0F2338, 0xD0064F22, 0x6023400B, +0x4F266203, 0x112151F4, 0x63F61130, 0x61F662F6, +0x60F6000B, 0x002007F4, 0x4100C709, 0x0123011D, +0x51F20009, 0x110150F4, 0x110050F3, 0x000B61F6, +0x51F260F6, 0x1101E000, 0x61F61100, 0x60F6000B, +0x01300000, 0x0128012C, 0x01200124, 0x0118011C, +0x0106010A, 0x00FE0102, 0x00E200E6, 0x00DA00DE, +0x00CC00D0, 0x00C400C8, 0x00A800AC, 0x00A000A4, +0x008C0090, 0x00840088, 0x0066006A, 0x005E0062, +0x42244300, 0x42244300, 0x42244300, 0x43286133, +0x43084318, 0x42284308, 0x42084218, 0x41094208, +0xAFAF4109, 0x4300221B, 0x43004224, 0x43004224, +0x61334224, 0x43184328, 0x42184228, 0xAFA14119, +0x4300221B, 0x43004224, 0x43004224, 0x61334224, +0x43084328, 0x42284308, 0x42084208, 0x41094119, +0xAF8F4109, 0x4300221B, 0x43004224, 0x43004224, +0x61334224, 0x212D4328, 0x6213AF84, 0x42244300, +0x42244300, 0x42244300, 0x43186133, 0x43084308, +0x42084218, 0x41294208, 0x41094109, 0x221BAF72, +0x42244300, 0x42244300, 0x42244300, 0x43186133, +0x41294218, 0xAF654119, 0x4300221B, 0x43004224, +0x43004224, 0x43004224, 0x43004224, 0x43004224, +0x43004224, 0x4224AF56, 0x2F162F06, 0x8B264115, +0x3103E040, 0x2F26892B, 0x52F62F36, 0xE02053F5, +0x8B053103, 0xE2006323, 0x89093100, 0x3108A002, +0x8B0F2228, 0xD0064F22, 0x6033400B, 0x4F266303, +0x112151F4, 0x63F61130, 0x61F662F6, 0x60F6000B, +0x002008B4, 0x4100C709, 0x0123011D, 0x51F20009, +0x110150F4, 0x110050F3, 0x000B61F6, 0x51F260F6, +0x1101E000, 0x61F61100, 0x60F6000B, 0x012E0000, +0x0126012A, 0x011E0122, 0x0116011A, 0x01040108, +0x00FC0100, 0x00E000E4, 0x00D800DC, 0x00CC00D0, +0x00C400C8, 0x00A800AC, 0x00A000A4, 0x008C0090, +0x00840088, 0x0066006A, 0x005E0062, 0x43254201, +0x43254201, 0x43254201, 0x42296123, 0x42094219, +0x43294209, 0x43094319, 0x41084309, 0xAFAF4108, +0x4201231B, 0x42014325, 0x42014325, 0x61234325, +0x42194229, 0x43194329, 0xAFA14118, 0x4201231B, +0x42014325, 0x42014325, 0x61234325, 0x42094229, +0x43294209, 0x43094309, 0x41084118, 0xAF8F4108, +0x4201231B, 0x42014325, 0x42014325, 0x61234325, +0xAF854229, 0x4201231D, 0x42014325, 0x42014325, +0x61234325, 0x42094219, 0x43194209, 0x43094309, +0x41084128, 0xAF734108, 0x4201231B, 0x42014325, +0x42014325, 0x61234325, 0x43194219, 0x41184128, +0x231BAF66, 0x43254201, 0x43254201, 0x43254201, +0x43254201, 0x43254201, 0x43254201, 0xAF574201, +0x00004325, 0x080A0C0E, 0x00020406, 0x1A1C1E20, +0x12141618, 0x2E303234, 0x26282A2C, 0x3A3C3E40, +0x6C625648, 0x41112F26, 0xE2208F18, 0x890B3123, +0x321CD204, 0xD1026220, 0x412B312C, 0x00090009, +0x0020081E, 0x002007D4, 0x000BE000, 0x400062F6, +0x40004000, 0x40004000, 0x40004000, 0x62F6000B, +0x40004000, 0x40004000, 0x40004000, 0x40184000, +0x62F6000B, 0x40004000, 0x40004000, 0x40004000, +0x40284000, 0x62F6000B, 0x40004000, 0x40184000, +0x000B4028, 0xC90F62F6, 0x40054005, 0x40054005, +0x62F6000B, 0x4005C907, 0x40054005, 0x62F6000B, +0x4005C903, 0x000B4005, 0xC90162F6, 0x000B4005, +0x000062F6, 0x080A0C0E, 0x00020406, 0x1A1C1E20, +0x12141618, 0x2E303234, 0x26282A2C, 0x3A3C3E40, +0x6C625648, 0x41112F26, 0xE2208F18, 0x890B3123, +0x321CD204, 0xD1026220, 0x412B312C, 0x00090009, +0x002008DE, 0x00200894, 0x000BE000, 0x400162F6, +0x40014001, 0x40014001, 0x40014001, 0x62F6000B, +0x40014001, 0x40014001, 0x40014001, 0x40194001, +0x62F6000B, 0x40014001, 0x40014001, 0x40014001, +0x40294001, 0x62F6000B, 0x40014001, 0x40194001, +0x000B4029, 0x400462F6, 0x40044004, 0xC90F4004, +0x62F6000B, 0x40044004, 0xC9074004, 0x62F6000B, +0x40044004, 0x000BC903, 0x400462F6, 0x000BC901, +0x000062F6, 0x00000000, 0x77073096, 0xEE0E612C, +0x990951BA, 0x076DC419, 0x706AF48F, 0xE963A535, +0x9E6495A3, 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, +0x97D2D988, 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, +0x90BF1D91, 0x1DB71064, 0x6AB020F2, 0xF3B97148, +0x84BE41DE, 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, +0x83D385C7, 0x136C9856, 0x646BA8C0, 0xFD62F97A, +0x8A65C9EC, 0x14015C4F, 0x63066CD9, 0xFA0F3D63, +0x8D080DF5, 0x3B6E20C8, 0x4C69105E, 0xD56041E4, +0xA2677172, 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, +0xA50AB56B, 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, +0xACBCF940, 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, +0xABD13D59, 0x26D930AC, 0x51DE003A, 0xC8D75180, +0xBFD06116, 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, +0xB8BDA50F, 0x2802B89E, 0x5F058808, 0xC60CD9B2, +0xB10BE924, 0x2F6F7C87, 0x58684C11, 0xC1611DAB, +0xB6662D3D, 0x76DC4190, 0x01DB7106, 0x98D220BC, +0xEFD5102A, 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, +0xE8B8D433, 0x7807C9A2, 0x0F00F934, 0x9609A88E, +0xE10E9818, 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, +0xE6635C01, 0x6B6B51F4, 0x1C6C6162, 0x856530D8, +0xF262004E, 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, +0xF50FC457, 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, +0xFCB9887C, 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, +0xFBD44C65, 0x4DB26158, 0x3AB551CE, 0xA3BC0074, +0xD4BB30E2, 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, +0xD3D6F4FB, 0x4369E96A, 0x346ED9FC, 0xAD678846, +0xDA60B8D0, 0x44042D73, 0x33031DE5, 0xAA0A4C5F, +0xDD0D7CC9, 0x5005713C, 0x270241AA, 0xBE0B1010, +0xC90C2086, 0x5768B525, 0x206F85B3, 0xB966D409, +0xCE61E49F, 0x5EDEF90E, 0x29D9C998, 0xB0D09822, +0xC7D7A8B4, 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, +0xC0BA6CAD, 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, +0x74B1D29A, 0xEAD54739, 0x9DD277AF, 0x04DB2615, +0x73DC1683, 0xE3630B12, 0x94643B84, 0x0D6D6A3E, +0x7A6A5AA8, 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, +0x7D079EB1, 0xF00F9344, 0x8708A3D2, 0x1E01F268, +0x6906C2FE, 0xF762575D, 0x806567CB, 0x196C3671, +0x6E6B06E7, 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, +0x67DD4ACC, 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, +0x60B08ED5, 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, +0x4FDFF252, 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, +0x48B2364B, 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, +0x41047A60, 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, +0x4669BE79, 0xCB61B38C, 0xBC66831A, 0x256FD2A0, +0x5268E236, 0xCC0C7795, 0xBB0B4703, 0x220216B9, +0x5505262F, 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, +0x5CB36A04, 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, +0x5BDEAE1D, 0x9B64C2B0, 0xEC63F226, 0x756AA39C, +0x026D930A, 0x9C0906A9, 0xEB0E363F, 0x72076785, +0x05005713, 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, +0x0CB61B38, 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, +0x0BDBDF21, 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, +0x1FDA836E, 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, +0x18B74777, 0x88085AE6, 0xFF0F6A70, 0x66063BCA, +0x11010B5C, 0x8F659EFF, 0xF862AE69, 0x616BFFD3, +0x166CCF45, 0xA00AE278, 0xD70DD2EE, 0x4E048354, +0x3903B3C2, 0xA7672661, 0xD06016F7, 0x4969474D, +0x3E6E77DB, 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, +0x37D83BF0, 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, +0x30B5FFE9, 0xBDBDF21C, 0xCABAC28A, 0x53B39330, +0x24B4A3A6, 0xBAD03605, 0xCDD70693, 0x54DE5729, +0x23D967BF, 0xB3667A2E, 0xC4614AB8, 0x5D681B02, +0x2A6F2B94, 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, +0x2D02EF8D, 0x544F0D0A, 0x50205355, 0x20312D48, +0x003A5746, 0x72636564, 0x69747079, 0x65206E6F, +0x726F7272, 0x0A0D2121, 0x00000000, 0x6564667A, +0x70797263, 0x65725F74, 0x616C7567, 0x79726F74, +0x6261745F, 0x7220656C, 0x203D7465, 0x00000000, +0x45485441, 0x38731652, 0x89ACFF91, 0xEE55D178, +0xEE000D0A, }; + +const u32_t zcFwImageSize=3508; diff --git a/drivers/staging/otus/hal/hpmain.c b/drivers/staging/otus/hal/hpmain.c new file mode 100644 index 000000000000..2e65c466aae8 --- /dev/null +++ b/drivers/staging/otus/hal/hpmain.c @@ -0,0 +1,4643 @@ +/* + * Copyright (c) 2007-2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include "../80211core/cprecomp.h" +#include "hpani.h" +#include "hpusb.h" +#include "otus.ini" + +extern const u32_t zcFwImage[]; +extern const u32_t zcFwImageSize; +extern const u32_t zcDKFwImage[]; +extern const u32_t zcDKFwImageSize; +extern const u32_t zcFwImageSPI[]; +extern const u32_t zcFwImageSPISize; + +#ifdef ZM_OTUS_LINUX_PHASE_2 +extern const u32_t zcFwBufImage[]; +extern const u32_t zcFwBufImageSize; +extern const u32_t zcP2FwImage[]; +extern const u32_t zcP2FwImageSize; +#endif +extern void zfInitCmdQueue(zdev_t* dev); +extern u16_t zfIssueCmd(zdev_t* dev, u32_t* cmd, u16_t cmdLen, + u16_t src, u8_t* buf); +extern void zfIdlRsp(zdev_t* dev, u32_t* rsp, u16_t rspLen); +extern u16_t zfDelayWriteInternalReg(zdev_t* dev, u32_t addr, u32_t val); +extern u16_t zfFlushDelayWrite(zdev_t* dev); +extern void zfUsbInit(zdev_t* dev); +extern u16_t zfFirmwareDownload(zdev_t* dev, u32_t* fw, u32_t len, u32_t offset); +extern u16_t zfFirmwareDownloadNotJump(zdev_t* dev, u32_t* fw, u32_t len, u32_t offset); +extern void zfUsbFree(zdev_t* dev); +extern u16_t zfCwmIsExtChanBusy(u32_t ctlBusy, u32_t extBusy); +extern void zfCoreCwmBusy(zdev_t* dev, u16_t busy); + +/* Prototypes */ +void zfInitRf(zdev_t* dev, u32_t frequency); +void zfInitPhy(zdev_t* dev, u32_t frequency, u8_t bw40); +void zfInitMac(zdev_t* dev); + +void zfSetPowerCalTable(zdev_t* dev, u32_t frequency, u8_t bw40, u8_t extOffset); +void zfInitPowerCal(zdev_t* dev); + +#ifdef ZM_DRV_INIT_USB_MODE +void zfInitUsbMode(zdev_t* dev); +u16_t zfHpUsbReset(zdev_t* dev); +#endif + +/* Bank 0 1 2 3 5 6 7 */ +void zfSetRfRegs(zdev_t* dev, u32_t frequency); +/* Bank 4 */ +void zfSetBank4AndPowerTable(zdev_t* dev, u32_t frequency, u8_t bw40, + u8_t extOffset); +/* Get param for turnoffdyn */ +void zfGetHwTurnOffdynParam(zdev_t* dev, + u32_t frequency, u8_t bw40, u8_t extOffset, + int* delta_slope_coeff_exp, + int* delta_slope_coeff_man, + int* delta_slope_coeff_exp_shgi, + int* delta_slope_coeff_man_shgi); + +void zfSelAdcClk(zdev_t* dev, u8_t bw40, u32_t frequency); +u32_t zfHpEchoCommand(zdev_t* dev, u32_t value); + + + +#define zm_hp_priv(x) (((struct zsHpPriv*)wd->hpPrivate)->x) +struct zsHpPriv zgHpPriv; + +#define ZM_FIRMWARE_WLAN_ADDR 0x200000 +#define ZM_FIRMWARE_SPI_ADDR 0x114000 +/* 0: real chip 1: FPGA test */ +#define ZM_FPGA_PHY 0 + +#define reg_write(addr, val) zfDelayWriteInternalReg(dev, addr+0x1bc000, val) +#define zm_min(A, B) ((A>B)? B:A) + + +/******************** Intialization ********************/ +u16_t zfHpInit(zdev_t* dev, u32_t frequency) +{ + u16_t ret; + zmw_get_wlan_dev(dev); + + /* Initializa HAL Plus private variables */ + wd->hpPrivate = &zgHpPriv; + + ((struct zsHpPriv*)wd->hpPrivate)->halCapability = ZM_HP_CAP_11N; + + ((struct zsHpPriv*)wd->hpPrivate)->hwFrequency = 0; + ((struct zsHpPriv*)wd->hpPrivate)->hwBw40 = 0; + ((struct zsHpPriv*)wd->hpPrivate)->hwExtOffset = 0; + + ((struct zsHpPriv*)wd->hpPrivate)->disableDfsCh = 0; + + ((struct zsHpPriv*)wd->hpPrivate)->ledMode[0] = 1; + ((struct zsHpPriv*)wd->hpPrivate)->ledMode[1] = 1; + ((struct zsHpPriv*)wd->hpPrivate)->strongRSSI = 0; + ((struct zsHpPriv*)wd->hpPrivate)->rxStrongRSSI = 0; + + ((struct zsHpPriv*)wd->hpPrivate)->slotType = 1; + ((struct zsHpPriv*)wd->hpPrivate)->aggPktNum = 0x10000a; + + ((struct zsHpPriv*)wd->hpPrivate)->eepromImageIndex = 0; + + + ((struct zsHpPriv*)wd->hpPrivate)->eepromImageRdReq = 0; +#ifdef ZM_OTUS_RX_STREAM_MODE + ((struct zsHpPriv*)wd->hpPrivate)->remainBuf = NULL; + ((struct zsHpPriv*)wd->hpPrivate)->usbRxRemainLen = 0; + ((struct zsHpPriv*)wd->hpPrivate)->usbRxPktLen = 0; + ((struct zsHpPriv*)wd->hpPrivate)->usbRxPadLen = 0; + ((struct zsHpPriv*)wd->hpPrivate)->usbRxTransferLen = 0; +#endif + + ((struct zsHpPriv*)wd->hpPrivate)->enableBBHeavyClip = 1; + ((struct zsHpPriv*)wd->hpPrivate)->hwBBHeavyClip = 1; // force enable 8107 + ((struct zsHpPriv*)wd->hpPrivate)->doBBHeavyClip = 0; + ((struct zsHpPriv*)wd->hpPrivate)->setValueHeavyClip = 0; + + + /* Initialize driver core */ + zfInitCmdQueue(dev); + + /* Initialize USB */ + zfUsbInit(dev); + +#if ZM_SW_LOOP_BACK != 1 + + /* TODO : [Download FW] */ + if (wd->modeMDKEnable) + { + /* download the MDK firmware */ + if ((ret = zfFirmwareDownload(dev, (u32_t*)zcDKFwImage, + (u32_t)zcDKFwImageSize, ZM_FIRMWARE_WLAN_ADDR)) != ZM_SUCCESS) + { + /* TODO : exception handling */ + //return 1; + } + } + else + { + #ifndef ZM_OTUS_LINUX_PHASE_2 + /* donwload the normal frimware */ + if ((ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage, + (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR)) != ZM_SUCCESS) + { + /* TODO : exception handling */ + //return 1; + } + #else + + // 1-PH fw: ReadMac() store some global variable + if ((ret = zfFirmwareDownloadNotJump(dev, (u32_t*)zcFwBufImage, + (u32_t)zcFwBufImageSize, 0x102800)) != ZM_SUCCESS) + { + DbgPrint("Dl zcFwBufImage failed!"); + } + + zfwSleep(dev, 1000); + + if ((ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage, + (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR)) != ZM_SUCCESS) + { + DbgPrint("Dl zcFwBufImage failed!"); + } + #endif + } +#endif + +#ifdef ZM_DRV_INIT_USB_MODE + /* Init USB Mode */ + zfInitUsbMode(dev); + + /* Do the USB Reset */ + zfHpUsbReset(dev); +#endif + +/* Register setting */ +/* ZM_DRIVER_MODEL_TYPE_MDK + * 1=>for MDK, disable init RF, PHY, and MAC, + * 0=>normal init + */ +//#if ((ZM_SW_LOOP_BACK != 1) && (ZM_DRIVER_MODEL_TYPE_MDK !=1)) +#if ZM_SW_LOOP_BACK != 1 + if(!wd->modeMDKEnable) + { + /* Init MAC */ + zfInitMac(dev); + + #if ZM_FW_LOOP_BACK != 1 + /* Init PHY */ + zfInitPhy(dev, frequency, 0); + + /* Init RF */ + zfInitRf(dev, frequency); + + #if ZM_FPGA_PHY == 0 + /* BringUp issue */ + //zfDelayWriteInternalReg(dev, 0x9800+0x1bc000, 0x10000007); + //zfFlushDelayWrite(dev); + #endif + + #endif /* end of ZM_FW_LOOP_BACK != 1 */ + } +#endif /* end of ((ZM_SW_LOOP_BACK != 1) && (ZM_DRIVER_MODEL_TYPE_MDK !=1)) */ + + zfHpEchoCommand(dev, 0xAABBCCDD); + + return 0; +} + + +u16_t zfHpReinit(zdev_t* dev, u32_t frequency) +{ + u16_t ret; + zmw_get_wlan_dev(dev); + + ((struct zsHpPriv*)wd->hpPrivate)->halReInit = 1; + + ((struct zsHpPriv*)wd->hpPrivate)->strongRSSI = 0; + ((struct zsHpPriv*)wd->hpPrivate)->rxStrongRSSI = 0; + +#ifdef ZM_OTUS_RX_STREAM_MODE + if (((struct zsHpPriv*)wd->hpPrivate)->remainBuf != NULL) + { + zfwBufFree(dev, ((struct zsHpPriv*)wd->hpPrivate)->remainBuf, 0); + } + ((struct zsHpPriv*)wd->hpPrivate)->remainBuf = NULL; + ((struct zsHpPriv*)wd->hpPrivate)->usbRxRemainLen = 0; + ((struct zsHpPriv*)wd->hpPrivate)->usbRxPktLen = 0; + ((struct zsHpPriv*)wd->hpPrivate)->usbRxPadLen = 0; + ((struct zsHpPriv*)wd->hpPrivate)->usbRxTransferLen = 0; +#endif + + zfInitCmdQueue(dev); + zfCoreReinit(dev); + + #ifndef ZM_OTUS_LINUX_PHASE_2 + /* Download firmware */ + if ((ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage, + (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR)) != ZM_SUCCESS) + { + /* TODO : exception handling */ + //return 1; + } + #else + if ((ret = zfFirmwareDownload(dev, (u32_t*)zcP2FwImage, + (u32_t)zcP2FwImageSize, ZM_FIRMWARE_WLAN_ADDR)) != ZM_SUCCESS) + { + /* TODO : exception handling */ + //return 1; + } + #endif + +#ifdef ZM_DRV_INIT_USB_MODE + /* Init USB Mode */ + zfInitUsbMode(dev); + + /* Do the USB Reset */ + zfHpUsbReset(dev); +#endif + + /* Init MAC */ + zfInitMac(dev); + + /* Init PHY */ + zfInitPhy(dev, frequency, 0); + /* Init RF */ + zfInitRf(dev, frequency); + + #if ZM_FPGA_PHY == 0 + /* BringUp issue */ + //zfDelayWriteInternalReg(dev, 0x9800+0x1bc000, 0x10000007); + //zfFlushDelayWrite(dev); + #endif + + zfHpEchoCommand(dev, 0xAABBCCDD); + + return 0; +} + + +u16_t zfHpRelease(zdev_t* dev) +{ + /* Free USB resource */ + zfUsbFree(dev); + + return 0; +} + +/* MDK mode setting for dontRetransmit */ +void zfHpConfigFM(zdev_t* dev, u32_t RxMaxSize, u32_t DontRetransmit) +{ + u32_t cmd[3]; + u16_t ret; + + cmd[0] = 8 | (ZM_CMD_CONFIG << 8); + cmd[1] = RxMaxSize; /* zgRxMaxSize */ + cmd[2] = DontRetransmit; /* zgDontRetransmit */ + + ret = zfIssueCmd(dev, cmd, 12, ZM_OID_INTERNAL_WRITE, 0); +} + +const u8_t zcXpdToPd[16] = +{ + /* 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF */ + 0x2, 0x2, 0x2, 0x1, 0x2, 0x2, 0x6, 0x2, 0x2, 0x3, 0x7, 0x2, 0xB, 0x2, 0x2, 0x2 +}; + +/******************** RF and PHY ********************/ + +void zfInitPhy(zdev_t* dev, u32_t frequency, u8_t bw40) +{ + u16_t i, j, k; + u16_t entries; + u16_t modesIndex = 0; + u16_t freqIndex = 0; + u32_t tmp, tmp1; + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv=wd->hpPrivate; + u32_t eepromBoardData[15][6] = { + /* Register A-20 A-20/40 G-20/40 G-20 G-Turbo */ + {0x9964, 0, 0, 0, 0, 0}, + {0x9960, 0, 0, 0, 0, 0}, + {0xb960, 0, 0, 0, 0, 0}, + {0x9844, 0, 0, 0, 0, 0}, + {0x9850, 0, 0, 0, 0, 0}, + {0x9834, 0, 0, 0, 0, 0}, + {0x9828, 0, 0, 0, 0, 0}, + {0xc864, 0, 0, 0, 0, 0}, + {0x9848, 0, 0, 0, 0, 0}, + {0xb848, 0, 0, 0, 0, 0}, + {0xa20c, 0, 0, 0, 0, 0}, + {0xc20c, 0, 0, 0, 0, 0}, + {0x9920, 0, 0, 0, 0, 0}, + {0xb920, 0, 0, 0, 0, 0}, + {0xa258, 0, 0, 0, 0, 0}, + }; + + /* #1 Save the initial value of the related RIFS register settings */ + //((struct zsHpPriv*)wd->hpPrivate)->isInitialPhy++; + + /* + * Setup the indices for the next set of register array writes + * PHY mode is static20 / 2040 + * Frequency is 2.4GHz (B) / 5GHz (A) + */ + if ( frequency > ZM_CH_G_14 ) + { + /* 5GHz */ + freqIndex = 1; + if (bw40) + { + modesIndex = 2; + zm_debug_msg0("init ar5416Modes in 2: A-20/40"); + } + else + { + modesIndex = 1; + zm_debug_msg0("init ar5416Modes in 1: A-20"); + } + } + else + { + /* 2.4GHz */ + freqIndex = 2; + if (bw40) + { + modesIndex = 3; + zm_debug_msg0("init ar5416Modes in 3: G-20/40"); + } + else + { + modesIndex = 4; + zm_debug_msg0("init ar5416Modes in 4: G-20"); + } + } + + +#if ZM_FPGA_PHY == 1 + /* Starting External Hainan Register Initialization */ + /* TODO: */ + + zfwSleep(dev, 10); +#endif + + /* + *Set correct Baseband to analog shift setting to access analog chips. + */ + //reg_write(PHY_BASE, 0x00000007); +// reg_write(0x9800, 0x00000007); + + /* + * Write addac shifts + */ + // do this in firmware + + + + /* Zeroize board data */ + for (j=0; j<15; j++) + { + for (k=1; k<=4; k++) + { + eepromBoardData[j][k] = 0; + } + } + /* + * Register setting by mode + */ + + entries = sizeof(ar5416Modes) / sizeof(*ar5416Modes); + zm_msg1_scan(ZM_LV_2, "Modes register setting entries=", entries); + for (i=0; i<entries; i++) + { +#if 0 + if ( ((struct zsHpPriv*)wd->hpPrivate)->hwNotFirstInit && (ar5416Modes[i][0] == 0xa27c) ) + { + /* Force disable CR671 bit20 / 7823 */ + /* The bug has to do with the polarity of the pdadc offset calibration. There */ + /* is an initial calibration that is OK, and there is a continuous */ + /* calibration that updates the pddac with the wrong polarity. Fortunately */ + /* the second loop can be disabled with a bit called en_pd_dc_offset_thr. */ + + reg_write(ar5416Modes[i][0], (ar5416Modes[i][modesIndex]& 0xffefffff) ); + ((struct zsHpPriv*)wd->hpPrivate)->hwNotFirstInit = 1; + } + else + { +#endif + /* FirstTime Init or not 0xa27c(CR671) */ + reg_write(ar5416Modes[i][0], ar5416Modes[i][modesIndex]); +// } + /* Initialize board data */ + for (j=0; j<15; j++) + { + if (ar5416Modes[i][0] == eepromBoardData[j][0]) + { + for (k=1; k<=4; k++) + { + eepromBoardData[j][k] = ar5416Modes[i][k]; + } + } + } + /* #1 Save the initial value of the related RIFS register settings */ + //if( ((struct zsHpPriv*)wd->hpPrivate)->isInitialPhy == 1 ) + { + switch(ar5416Modes[i][0]) + { + case 0x9850 : + ((struct zsHpPriv*)wd->hpPrivate)->initDesiredSigSize = ar5416Modes[i][modesIndex]; + break; + case 0x985c : + ((struct zsHpPriv*)wd->hpPrivate)->initAGC = ar5416Modes[i][modesIndex]; + break; + case 0x9860 : + ((struct zsHpPriv*)wd->hpPrivate)->initAgcControl = ar5416Modes[i][modesIndex]; + break; + case 0x9918 : + ((struct zsHpPriv*)wd->hpPrivate)->initSearchStartDelay = ar5416Modes[i][modesIndex]; + break; + case 0x99ec : + ((struct zsHpPriv*)wd->hpPrivate)->initRIFSSearchParams = ar5416Modes[i][modesIndex]; + break; + case 0xa388 : + ((struct zsHpPriv*)wd->hpPrivate)->initFastChannelChangeControl = ar5416Modes[i][modesIndex]; + default : + break; + } + } + } +#if 0 + zfFlushDelayWrite(dev); + + /* + * Common Register setting + */ + entries = sizeof(ar5416Common) / sizeof(*ar5416Common); + for (i=0; i<entries; i++) + { + reg_write(ar5416Common[i][0], ar5416Common[i][1]); + } + zfFlushDelayWrite(dev); + + /* + * RF Gain setting by freqIndex + */ + entries = sizeof(ar5416BB_RfGain) / sizeof(*ar5416BB_RfGain); + for (i=0; i<entries; i++) + { + reg_write(ar5416BB_RfGain[i][0], ar5416BB_RfGain[i][freqIndex]); + } + zfFlushDelayWrite(dev); + + /* + * Moved ar5416InitChainMask() here to ensure the swap bit is set before + * the pdadc table is written. Swap must occur before any radio dependent + * replicated register access. The pdadc curve addressing in particular + * depends on the consistent setting of the swap bit. + */ + //ar5416InitChainMask(pDev); + + /* Setup the transmit power values. */ + // TODO +#endif + + /* Update 5G board data */ + //Ant control common + tmp = hpPriv->eepromImage[0x100+0x144*2/4]; + eepromBoardData[0][1] = tmp; + eepromBoardData[0][2] = tmp; + //Ant control chain 0 + tmp = hpPriv->eepromImage[0x100+0x140*2/4]; + eepromBoardData[1][1] = tmp; + eepromBoardData[1][2] = tmp; + //Ant control chain 2 + tmp = hpPriv->eepromImage[0x100+0x142*2/4]; + eepromBoardData[2][1] = tmp; + eepromBoardData[2][2] = tmp; + //SwSettle + tmp = hpPriv->eepromImage[0x100+0x146*2/4]; + tmp = (tmp >> 16) & 0x7f; + eepromBoardData[3][1] &= (~((u32_t)0x3f80)); + eepromBoardData[3][1] |= (tmp << 7); +#if 0 + //swSettleHt40 + tmp = hpPriv->eepromImage[0x100+0x158*2/4]; + tmp = (tmp) & 0x7f; + eepromBoardData[3][2] &= (~((u32_t)0x3f80)); + eepromBoardData[3][2] |= (tmp << 7); +#endif + //adcDesired, pdaDesired + tmp = hpPriv->eepromImage[0x100+0x148*2/4]; + tmp = (tmp >> 24); + tmp1 = hpPriv->eepromImage[0x100+0x14a*2/4]; + tmp1 = tmp1 & 0xff; + tmp = tmp + (tmp1<<8); + eepromBoardData[4][1] &= (~((u32_t)0xffff)); + eepromBoardData[4][1] |= tmp; + eepromBoardData[4][2] &= (~((u32_t)0xffff)); + eepromBoardData[4][2] |= tmp; + //TxEndToXpaOff, TxFrameToXpaOn + tmp = hpPriv->eepromImage[0x100+0x14a*2/4]; + tmp = (tmp >> 24) & 0xff; + tmp1 = hpPriv->eepromImage[0x100+0x14c*2/4]; + tmp1 = (tmp1 >> 8) & 0xff; + tmp = (tmp<<24) + (tmp<<16) + (tmp1<<8) + tmp1; + eepromBoardData[5][1] = tmp; + eepromBoardData[5][2] = tmp; + //TxEnaToRxOm + tmp = hpPriv->eepromImage[0x100+0x14c*2/4] & 0xff; + eepromBoardData[6][1] &= (~((u32_t)0xff0000)); + eepromBoardData[6][1] |= (tmp<<16); + eepromBoardData[6][2] &= (~((u32_t)0xff0000)); + eepromBoardData[6][2] |= (tmp<<16); + //Thresh62 + tmp = hpPriv->eepromImage[0x100+0x14c*2/4]; + tmp = (tmp >> 16) & 0x7f; + eepromBoardData[7][1] &= (~((u32_t)0x7f000)); + eepromBoardData[7][1] |= (tmp<<12); + eepromBoardData[7][2] &= (~((u32_t)0x7f000)); + eepromBoardData[7][2] |= (tmp<<12); + //TxRxAtten chain_0 + tmp = hpPriv->eepromImage[0x100+0x146*2/4]; + tmp = (tmp >> 24) & 0x3f; + eepromBoardData[8][1] &= (~((u32_t)0x3f000)); + eepromBoardData[8][1] |= (tmp<<12); + eepromBoardData[8][2] &= (~((u32_t)0x3f000)); + eepromBoardData[8][2] |= (tmp<<12); + //TxRxAtten chain_2 + tmp = hpPriv->eepromImage[0x100+0x148*2/4] & 0x3f; + eepromBoardData[9][1] &= (~((u32_t)0x3f000)); + eepromBoardData[9][1] |= (tmp<<12); + eepromBoardData[9][2] &= (~((u32_t)0x3f000)); + eepromBoardData[9][2] |= (tmp<<12); + //TxRxMargin chain_0 + tmp = hpPriv->eepromImage[0x100+0x148*2/4]; + tmp = (tmp >> 8) & 0x3f; + eepromBoardData[10][1] &= (~((u32_t)0xfc0000)); + eepromBoardData[10][1] |= (tmp<<18); + eepromBoardData[10][2] &= (~((u32_t)0xfc0000)); + eepromBoardData[10][2] |= (tmp<<18); + //TxRxMargin chain_2 + tmp = hpPriv->eepromImage[0x100+0x148*2/4]; + tmp = (tmp >> 16) & 0x3f; + eepromBoardData[11][1] &= (~((u32_t)0xfc0000)); + eepromBoardData[11][1] |= (tmp<<18); + eepromBoardData[11][2] &= (~((u32_t)0xfc0000)); + eepromBoardData[11][2] |= (tmp<<18); + //iqCall chain_0, iqCallQ chain_0 + tmp = hpPriv->eepromImage[0x100+0x14e*2/4]; + tmp = (tmp >> 24) & 0x3f; + tmp1 = hpPriv->eepromImage[0x100+0x150*2/4]; + tmp1 = (tmp1 >> 8) & 0x1f; + tmp = (tmp<<5) + tmp1; + eepromBoardData[12][1] &= (~((u32_t)0x7ff)); + eepromBoardData[12][1] |= (tmp); + eepromBoardData[12][2] &= (~((u32_t)0x7ff)); + eepromBoardData[12][2] |= (tmp); + //iqCall chain_2, iqCallQ chain_2 + tmp = hpPriv->eepromImage[0x100+0x150*2/4]; + tmp = tmp & 0x3f; + tmp1 = hpPriv->eepromImage[0x100+0x150*2/4]; + tmp1 = (tmp1 >> 16) & 0x1f; + tmp = (tmp<<5) + tmp1; + eepromBoardData[13][1] &= (~((u32_t)0x7ff)); + eepromBoardData[13][1] |= (tmp); + eepromBoardData[13][2] &= (~((u32_t)0x7ff)); + eepromBoardData[13][2] |= (tmp); + //bsw_Margin chain_0 + tmp = hpPriv->eepromImage[0x100+0x156*2/4]; + tmp = (tmp >> 16) & 0xf; + eepromBoardData[10][1] &= (~((u32_t)0x3c00)); + eepromBoardData[10][1] |= (tmp << 10); + eepromBoardData[10][2] &= (~((u32_t)0x3c00)); + eepromBoardData[10][2] |= (tmp << 10); + //xpd gain mask + tmp = hpPriv->eepromImage[0x100+0x14e*2/4]; + tmp = (tmp >> 8) & 0xf; + eepromBoardData[14][1] &= (~((u32_t)0xf0000)); + eepromBoardData[14][1] |= (zcXpdToPd[tmp] << 16); + eepromBoardData[14][2] &= (~((u32_t)0xf0000)); + eepromBoardData[14][2] |= (zcXpdToPd[tmp] << 16); +#if 0 + //bsw_Atten chain_0 + tmp = hpPriv->eepromImage[0x100+0x156*2/4]; + tmp = (tmp) & 0x1f; + eepromBoardData[10][1] &= (~((u32_t)0x1f)); + eepromBoardData[10][1] |= (tmp); + eepromBoardData[10][2] &= (~((u32_t)0x1f)); + eepromBoardData[10][2] |= (tmp); + //bsw_Margin chain_2 + tmp = hpPriv->eepromImage[0x100+0x156*2/4]; + tmp = (tmp >> 24) & 0xf; + eepromBoardData[11][1] &= (~((u32_t)0x3c00)); + eepromBoardData[11][1] |= (tmp << 10); + eepromBoardData[11][2] &= (~((u32_t)0x3c00)); + eepromBoardData[11][2] |= (tmp << 10); + //bsw_Atten chain_2 + tmp = hpPriv->eepromImage[0x100+0x156*2/4]; + tmp = (tmp >> 8) & 0x1f; + eepromBoardData[11][1] &= (~((u32_t)0x1f)); + eepromBoardData[11][1] |= (tmp); + eepromBoardData[11][2] &= (~((u32_t)0x1f)); + eepromBoardData[11][2] |= (tmp); +#endif + + /* Update 2.4G board data */ + //Ant control common + tmp = hpPriv->eepromImage[0x100+0x170*2/4]; + tmp = tmp >> 24; + tmp1 = hpPriv->eepromImage[0x100+0x172*2/4]; + tmp = tmp + (tmp1 << 8); + eepromBoardData[0][3] = tmp; + eepromBoardData[0][4] = tmp; + //Ant control chain 0 + tmp = hpPriv->eepromImage[0x100+0x16c*2/4]; + tmp = tmp >> 24; + tmp1 = hpPriv->eepromImage[0x100+0x16e*2/4]; + tmp = tmp + (tmp1 << 8); + eepromBoardData[1][3] = tmp; + eepromBoardData[1][4] = tmp; + //Ant control chain 2 + tmp = hpPriv->eepromImage[0x100+0x16e*2/4]; + tmp = tmp >> 24; + tmp1 = hpPriv->eepromImage[0x100+0x170*2/4]; + tmp = tmp + (tmp1 << 8); + eepromBoardData[2][3] = tmp; + eepromBoardData[2][4] = tmp; + //SwSettle + tmp = hpPriv->eepromImage[0x100+0x174*2/4]; + tmp = (tmp >> 8) & 0x7f; + eepromBoardData[3][4] &= (~((u32_t)0x3f80)); + eepromBoardData[3][4] |= (tmp << 7); +#if 0 + //swSettleHt40 + tmp = hpPriv->eepromImage[0x100+0x184*2/4]; + tmp = (tmp >> 24) & 0x7f; + eepromBoardData[3][3] &= (~((u32_t)0x3f80)); + eepromBoardData[3][3] |= (tmp << 7); +#endif + //adcDesired, pdaDesired + tmp = hpPriv->eepromImage[0x100+0x176*2/4]; + tmp = (tmp >> 16) & 0xff; + tmp1 = hpPriv->eepromImage[0x100+0x176*2/4]; + tmp1 = tmp1 >> 24; + tmp = tmp + (tmp1<<8); + eepromBoardData[4][3] &= (~((u32_t)0xffff)); + eepromBoardData[4][3] |= tmp; + eepromBoardData[4][4] &= (~((u32_t)0xffff)); + eepromBoardData[4][4] |= tmp; + //TxEndToXpaOff, TxFrameToXpaOn + tmp = hpPriv->eepromImage[0x100+0x178*2/4]; + tmp = (tmp >> 16) & 0xff; + tmp1 = hpPriv->eepromImage[0x100+0x17a*2/4]; + tmp1 = tmp1 & 0xff; + tmp = (tmp << 24) + (tmp << 16) + (tmp1 << 8) + tmp1; + eepromBoardData[5][3] = tmp; + eepromBoardData[5][4] = tmp; + //TxEnaToRxOm + tmp = hpPriv->eepromImage[0x100+0x178*2/4]; + tmp = (tmp >> 24); + eepromBoardData[6][3] &= (~((u32_t)0xff0000)); + eepromBoardData[6][3] |= (tmp<<16); + eepromBoardData[6][4] &= (~((u32_t)0xff0000)); + eepromBoardData[6][4] |= (tmp<<16); + //Thresh62 + tmp = hpPriv->eepromImage[0x100+0x17a*2/4]; + tmp = (tmp >> 8) & 0x7f; + eepromBoardData[7][3] &= (~((u32_t)0x7f000)); + eepromBoardData[7][3] |= (tmp<<12); + eepromBoardData[7][4] &= (~((u32_t)0x7f000)); + eepromBoardData[7][4] |= (tmp<<12); + //TxRxAtten chain_0 + tmp = hpPriv->eepromImage[0x100+0x174*2/4]; + tmp = (tmp >> 16) & 0x3f; + eepromBoardData[8][3] &= (~((u32_t)0x3f000)); + eepromBoardData[8][3] |= (tmp<<12); + eepromBoardData[8][4] &= (~((u32_t)0x3f000)); + eepromBoardData[8][4] |= (tmp<<12); + //TxRxAtten chain_2 + tmp = hpPriv->eepromImage[0x100+0x174*2/4]; + tmp = (tmp >> 24) & 0x3f; + eepromBoardData[9][3] &= (~((u32_t)0x3f000)); + eepromBoardData[9][3] |= (tmp<<12); + eepromBoardData[9][4] &= (~((u32_t)0x3f000)); + eepromBoardData[9][4] |= (tmp<<12); + //TxRxMargin chain_0 + tmp = hpPriv->eepromImage[0x100+0x176*2/4]; + tmp = (tmp) & 0x3f; + eepromBoardData[10][3] &= (~((u32_t)0xfc0000)); + eepromBoardData[10][3] |= (tmp<<18); + eepromBoardData[10][4] &= (~((u32_t)0xfc0000)); + eepromBoardData[10][4] |= (tmp<<18); + //TxRxMargin chain_2 + tmp = hpPriv->eepromImage[0x100+0x176*2/4]; + tmp = (tmp >> 8) & 0x3f; + eepromBoardData[11][3] &= (~((u32_t)0xfc0000)); + eepromBoardData[11][3] |= (tmp<<18); + eepromBoardData[11][4] &= (~((u32_t)0xfc0000)); + eepromBoardData[11][4] |= (tmp<<18); + //iqCall chain_0, iqCallQ chain_0 + tmp = hpPriv->eepromImage[0x100+0x17c*2/4]; + tmp = (tmp >> 16) & 0x3f; + tmp1 = hpPriv->eepromImage[0x100+0x17e*2/4]; + tmp1 = (tmp1) & 0x1f; + tmp = (tmp<<5) + tmp1; + eepromBoardData[12][3] &= (~((u32_t)0x7ff)); + eepromBoardData[12][3] |= (tmp); + eepromBoardData[12][4] &= (~((u32_t)0x7ff)); + eepromBoardData[12][4] |= (tmp); + //iqCall chain_2, iqCallQ chain_2 + tmp = hpPriv->eepromImage[0x100+0x17c*2/4]; + tmp = (tmp>>24) & 0x3f; + tmp1 = hpPriv->eepromImage[0x100+0x17e*2/4]; + tmp1 = (tmp1 >> 8) & 0x1f; + tmp = (tmp<<5) + tmp1; + eepromBoardData[13][3] &= (~((u32_t)0x7ff)); + eepromBoardData[13][3] |= (tmp); + eepromBoardData[13][4] &= (~((u32_t)0x7ff)); + eepromBoardData[13][4] |= (tmp); + //xpd gain mask + tmp = hpPriv->eepromImage[0x100+0x17c*2/4]; + tmp = tmp & 0xf; + DbgPrint("xpd=0x%x, pd=0x%x\n", tmp, zcXpdToPd[tmp]); + eepromBoardData[14][3] &= (~((u32_t)0xf0000)); + eepromBoardData[14][3] |= (zcXpdToPd[tmp] << 16); + eepromBoardData[14][4] &= (~((u32_t)0xf0000)); + eepromBoardData[14][4] |= (zcXpdToPd[tmp] << 16); +#if 0 + //bsw_Margin chain_0 + tmp = hpPriv->eepromImage[0x100+0x184*2/4]; + tmp = (tmp >> 8) & 0xf; + eepromBoardData[10][3] &= (~((u32_t)0x3c00)); + eepromBoardData[10][3] |= (tmp << 10); + eepromBoardData[10][4] &= (~((u32_t)0x3c00)); + eepromBoardData[10][4] |= (tmp << 10); + //bsw_Atten chain_0 + tmp = hpPriv->eepromImage[0x100+0x182*2/4]; + tmp = (tmp>>24) & 0x1f; + eepromBoardData[10][3] &= (~((u32_t)0x1f)); + eepromBoardData[10][3] |= (tmp); + eepromBoardData[10][4] &= (~((u32_t)0x1f)); + eepromBoardData[10][4] |= (tmp); + //bsw_Margin chain_2 + tmp = hpPriv->eepromImage[0x100+0x184*2/4]; + tmp = (tmp >> 16) & 0xf; + eepromBoardData[11][3] &= (~((u32_t)0x3c00)); + eepromBoardData[11][3] |= (tmp << 10); + eepromBoardData[11][4] &= (~((u32_t)0x3c00)); + eepromBoardData[11][4] |= (tmp << 10); + //bsw_Atten chain_2 + tmp = hpPriv->eepromImage[0x100+0x184*2/4]; + tmp = (tmp) & 0x1f; + eepromBoardData[11][3] &= (~((u32_t)0x1f)); + eepromBoardData[11][3] |= (tmp); + eepromBoardData[11][4] &= (~((u32_t)0x1f)); + eepromBoardData[11][4] |= (tmp); +#endif + +#if 0 + for (j=0; j<14; j++) + { + DbgPrint("%04x, %08x, %08x, %08x, %08x\n", eepromBoardData[j][0], eepromBoardData[j][1], eepromBoardData[j][2], eepromBoardData[j][3], eepromBoardData[j][4]); + } +#endif + + if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE + { + /* Update board data to registers */ + for (j=0; j<15; j++) + { + reg_write(eepromBoardData[j][0], eepromBoardData[j][modesIndex]); + + /* #1 Save the initial value of the related RIFS register settings */ + //if( ((struct zsHpPriv*)wd->hpPrivate)->isInitialPhy == 1 ) + { + switch(eepromBoardData[j][0]) + { + case 0x9850 : + ((struct zsHpPriv*)wd->hpPrivate)->initDesiredSigSize = eepromBoardData[j][modesIndex]; + break; + case 0x985c : + ((struct zsHpPriv*)wd->hpPrivate)->initAGC = eepromBoardData[j][modesIndex]; + break; + case 0x9860 : + ((struct zsHpPriv*)wd->hpPrivate)->initAgcControl = eepromBoardData[j][modesIndex]; + break; + case 0x9918 : + ((struct zsHpPriv*)wd->hpPrivate)->initSearchStartDelay = eepromBoardData[j][modesIndex]; + break; + case 0x99ec : + ((struct zsHpPriv*)wd->hpPrivate)->initRIFSSearchParams = eepromBoardData[j][modesIndex]; + break; + case 0xa388 : + ((struct zsHpPriv*)wd->hpPrivate)->initFastChannelChangeControl = eepromBoardData[j][modesIndex]; + default : + break; + } + } + } + } /* if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE */ + + + /* Bringup issue : force tx gain */ + //reg_write(0xa258, 0x0cc65381); + //reg_write(0xa274, 0x0a1a7c15); + zfInitPowerCal(dev); + + if(frequency > ZM_CH_G_14) + { + zfDelayWriteInternalReg(dev, 0x1d4014, 0x5143); + } + else + { + zfDelayWriteInternalReg(dev, 0x1d4014, 0x5163); + } + + zfFlushDelayWrite(dev); +} + + +void zfInitRf(zdev_t* dev, u32_t frequency) +{ + u32_t cmd[8]; + u16_t ret; + int delta_slope_coeff_exp; + int delta_slope_coeff_man; + int delta_slope_coeff_exp_shgi; + int delta_slope_coeff_man_shgi; + + zmw_get_wlan_dev(dev); + + zm_debug_msg1(" initRf frequency = ", frequency); + + if (frequency == 0) + { + frequency = 2412; + } + + /* Bank 0 1 2 3 5 6 7 */ + zfSetRfRegs(dev, frequency); + /* Bank 4 */ + zfSetBank4AndPowerTable(dev, frequency, 0, 0); + + /* stroe frequency */ + ((struct zsHpPriv*)wd->hpPrivate)->hwFrequency = (u16_t)frequency; + + zfGetHwTurnOffdynParam(dev, + frequency, 0, 0, + &delta_slope_coeff_exp, + &delta_slope_coeff_man, + &delta_slope_coeff_exp_shgi, + &delta_slope_coeff_man_shgi); + + /* related functions */ + frequency = frequency*1000; + cmd[0] = 28 | (ZM_CMD_RF_INIT << 8); + cmd[1] = frequency; + cmd[2] = 0;//((struct zsHpPriv*)wd->hpPrivate)->hw_DYNAMIC_HT2040_EN; + cmd[3] = 1;//((wd->ExtOffset << 2) | ((struct zsHpPriv*)wd->hpPrivate)->hw_HT_ENABLE); + cmd[4] = delta_slope_coeff_exp; + cmd[5] = delta_slope_coeff_man; + cmd[6] = delta_slope_coeff_exp_shgi; + cmd[7] = delta_slope_coeff_man_shgi; + + ret = zfIssueCmd(dev, cmd, 32, ZM_OID_INTERNAL_WRITE, 0); + + // delay temporarily, wait for new PHY and RF + zfwSleep(dev, 1000); +} + +int tn(int exp) +{ + int i; + int tmp = 1; + for(i=0; i<exp; i++) + tmp = tmp*2; + + return tmp; +} + +/*int zfFloor(double indata) +{ + if(indata<0) + return (int)indata-1; + else + return (int)indata; +} +*/ +u32_t reverse_bits(u32_t chan_sel) +{ + /* reverse_bits */ + u32_t chansel = 0; + u8_t i; + + for (i=0; i<8; i++) + chansel |= ((chan_sel>>(7-i) & 0x1) << i); + return chansel; +} + +/* Bank 0 1 2 3 5 6 7 */ +void zfSetRfRegs(zdev_t* dev, u32_t frequency) +{ + u16_t entries; + u16_t freqIndex = 0; + u16_t i; + + //zmw_get_wlan_dev(dev); + + if ( frequency > ZM_CH_G_14 ) + { + /* 5G */ + freqIndex = 1; + zm_msg0_scan(ZM_LV_2, "Set to 5GHz"); + + } + else + { + /* 2.4G */ + freqIndex = 2; + zm_msg0_scan(ZM_LV_2, "Set to 2.4GHz"); + } + +#if 1 + entries = sizeof(otusBank) / sizeof(*otusBank); + for (i=0; i<entries; i++) + { + reg_write(otusBank[i][0], otusBank[i][freqIndex]); + } +#else + /* Bank0 */ + entries = sizeof(ar5416Bank0) / sizeof(*ar5416Bank0); + for (i=0; i<entries; i++) + { + reg_write(ar5416Bank0[i][0], ar5416Bank0[i][1]); + } + /* Bank1 */ + entries = sizeof(ar5416Bank1) / sizeof(*ar5416Bank1); + for (i=0; i<entries; i++) + { + reg_write(ar5416Bank1[i][0], ar5416Bank1[i][1]); + } + /* Bank2 */ + entries = sizeof(ar5416Bank2) / sizeof(*ar5416Bank2); + for (i=0; i<entries; i++) + { + reg_write(ar5416Bank2[i][0], ar5416Bank2[i][1]); + } + /* Bank3 */ + entries = sizeof(ar5416Bank3) / sizeof(*ar5416Bank3); + for (i=0; i<entries; i++) + { + reg_write(ar5416Bank3[i][0], ar5416Bank3[i][freqIndex]); + } + /* Bank5 */ + reg_write (0x98b0, 0x00000013); + reg_write (0x98e4, 0x00000002); + /* Bank6 */ + entries = sizeof(ar5416Bank6) / sizeof(*ar5416Bank6); + for (i=0; i<entries; i++) + { + reg_write(ar5416Bank6[i][0], ar5416Bank6[i][freqIndex]); + } + /* Bank7 */ + entries = sizeof(ar5416Bank7) / sizeof(*ar5416Bank7); + for (i=0; i<entries; i++) + { + reg_write(ar5416Bank7[i][0], ar5416Bank7[i][1]); + } +#endif + + zfFlushDelayWrite(dev); +} + +/* Bank 4 */ +void zfSetBank4AndPowerTable(zdev_t* dev, u32_t frequency, u8_t bw40, + u8_t extOffset) +{ + u32_t chup = 1; + u32_t bmode_LF_synth_freq = 0; + u32_t amode_refsel_1 = 0; + u32_t amode_refsel_0 = 1; + u32_t addr2 = 1; + u32_t addr1 = 0; + u32_t addr0 = 0; + + u32_t d1; + u32_t d0; + u32_t tmp_0; + u32_t tmp_1; + u32_t data0; + u32_t data1; + + u8_t chansel; + u8_t chan_sel; + u32_t temp_chan_sel; + + u16_t i; + + zmw_get_wlan_dev(dev); + + + /* if enable 802.11h, need to record curent channel index in channel array */ + if (wd->sta.DFSEnable) + { + for (i = 0; i < wd->regulationTable.allowChannelCnt; i++) + { + if (wd->regulationTable.allowChannel[i].channel == frequency) + break; + } + wd->regulationTable.CurChIndex = i; + } + + if (bw40 == 1) + { + if (extOffset == 1) + { + frequency += 10; + } + else + { + frequency -= 10; + } + + } + + + if ( frequency > 3000 ) + { + if ( frequency % 10 ) + { + /* 5M */ + chan_sel = (u8_t)((frequency - 4800)/5); + chan_sel = (u8_t)(chan_sel & 0xff); + chansel = (u8_t)reverse_bits(chan_sel); + } + else + { + /* 10M : improve Tx EVM */ + chan_sel = (u8_t)((frequency - 4800)/10); + chan_sel = (u8_t)(chan_sel & 0xff)<<1; + chansel = (u8_t)reverse_bits(chan_sel); + + amode_refsel_1 = 1; + amode_refsel_0 = 0; + } + } + else + { + //temp_chan_sel = (((frequency - 672)*2) - 3040)/10; + if (frequency == 2484) + { + temp_chan_sel = 10 + (frequency - 2274)/5 ; + bmode_LF_synth_freq = 1; + } + else + { + temp_chan_sel = 16 + (frequency - 2272)/5 ; + bmode_LF_synth_freq = 0; + } + chan_sel = (u8_t)(temp_chan_sel << 2) & 0xff; + chansel = (u8_t)reverse_bits(chan_sel); + } + + d1 = chansel; //# 8 bits of chan + d0 = addr0<<7 | addr1<<6 | addr2<<5 + | amode_refsel_0<<3 | amode_refsel_1<<2 + | bmode_LF_synth_freq<<1 | chup; + + tmp_0 = d0 & 0x1f; //# 5-1 + tmp_1 = d1 & 0x1f; //# 5-1 + data0 = tmp_1<<5 | tmp_0; + + tmp_0 = d0>>5 & 0x7; //# 8-6 + tmp_1 = d1>>5 & 0x7; //# 8-6 + data1 = tmp_1<<5 | tmp_0; + + /* Bank4 */ + reg_write (0x9800+(0x2c<<2), data0); + reg_write (0x9800+(0x3a<<2), data1); + //zm_debug_msg1("0x9800+(0x2c<<2 = ", data0); + //zm_debug_msg1("0x9800+(0x3a<<2 = ", data1); + + + zfFlushDelayWrite(dev); + + zfwSleep(dev, 10); + + return; +} + + +struct zsPhyFreqPara +{ + u32_t coeff_exp; + u32_t coeff_man; + u32_t coeff_exp_shgi; + u32_t coeff_man_shgi; +}; + +struct zsPhyFreqTable +{ + u32_t frequency; + struct zsPhyFreqPara FpgaDynamicHT; + struct zsPhyFreqPara FpgaStaticHT; + struct zsPhyFreqPara ChipST20Mhz; + struct zsPhyFreqPara Chip2040Mhz; + struct zsPhyFreqPara Chip2040ExtAbove; +}; + +const struct zsPhyFreqTable zgPhyFreqCoeff[] = +{ +/*Index freq FPGA DYNAMIC_HT2040_EN FPGA STATIC_HT20 Real Chip static20MHz Real Chip 2040MHz Real Chip 2040Mhz */ + /* fclk = 10.8 21.6 40 ext below 40 ext above 40 */ +/* 0 */ {2412, {5, 23476, 5, 21128}, {4, 23476, 4, 21128}, {3, 21737, 3, 19563}, {3, 21827, 3, 19644}, {3, 21647, 3, 19482}}, +/* 1 */ {2417, {5, 23427, 5, 21084}, {4, 23427, 4, 21084}, {3, 21692, 3, 19523}, {3, 21782, 3, 19604}, {3, 21602, 3, 19442}}, +/* 2 */ {2422, {5, 23379, 5, 21041}, {4, 23379, 4, 21041}, {3, 21647, 3, 19482}, {3, 21737, 3, 19563}, {3, 21558, 3, 19402}}, +/* 3 */ {2427, {5, 23330, 5, 20997}, {4, 23330, 4, 20997}, {3, 21602, 3, 19442}, {3, 21692, 3, 19523}, {3, 21514, 3, 19362}}, +/* 4 */ {2432, {5, 23283, 5, 20954}, {4, 23283, 4, 20954}, {3, 21558, 3, 19402}, {3, 21647, 3, 19482}, {3, 21470, 3, 19323}}, +/* 5 */ {2437, {5, 23235, 5, 20911}, {4, 23235, 4, 20911}, {3, 21514, 3, 19362}, {3, 21602, 3, 19442}, {3, 21426, 3, 19283}}, +/* 6 */ {2442, {5, 23187, 5, 20868}, {4, 23187, 4, 20868}, {3, 21470, 3, 19323}, {3, 21558, 3, 19402}, {3, 21382, 3, 19244}}, +/* 7 */ {2447, {5, 23140, 5, 20826}, {4, 23140, 4, 20826}, {3, 21426, 3, 19283}, {3, 21514, 3, 19362}, {3, 21339, 3, 19205}}, +/* 8 */ {2452, {5, 23093, 5, 20783}, {4, 23093, 4, 20783}, {3, 21382, 3, 19244}, {3, 21470, 3, 19323}, {3, 21295, 3, 19166}}, +/* 9 */ {2457, {5, 23046, 5, 20741}, {4, 23046, 4, 20741}, {3, 21339, 3, 19205}, {3, 21426, 3, 19283}, {3, 21252, 3, 19127}}, +/* 10 */ {2462, {5, 22999, 5, 20699}, {4, 22999, 4, 20699}, {3, 21295, 3, 19166}, {3, 21382, 3, 19244}, {3, 21209, 3, 19088}}, +/* 11 */ {2467, {5, 22952, 5, 20657}, {4, 22952, 4, 20657}, {3, 21252, 3, 19127}, {3, 21339, 3, 19205}, {3, 21166, 3, 19050}}, +/* 12 */ {2472, {5, 22906, 5, 20615}, {4, 22906, 4, 20615}, {3, 21209, 3, 19088}, {3, 21295, 3, 19166}, {3, 21124, 3, 19011}}, +/* 13 */ {2484, {5, 22795, 5, 20516}, {4, 22795, 4, 20516}, {3, 21107, 3, 18996}, {3, 21192, 3, 19073}, {3, 21022, 3, 18920}}, +/* 14 */ {4920, {6, 23018, 6, 20716}, {5, 23018, 5, 20716}, {4, 21313, 4, 19181}, {4, 21356, 4, 19220}, {4, 21269, 4, 19142}}, +/* 15 */ {4940, {6, 22924, 6, 20632}, {5, 22924, 5, 20632}, {4, 21226, 4, 19104}, {4, 21269, 4, 19142}, {4, 21183, 4, 19065}}, +/* 16 */ {4960, {6, 22832, 6, 20549}, {5, 22832, 5, 20549}, {4, 21141, 4, 19027}, {4, 21183, 4, 19065}, {4, 21098, 4, 18988}}, +/* 17 */ {4980, {6, 22740, 6, 20466}, {5, 22740, 5, 20466}, {4, 21056, 4, 18950}, {4, 21098, 4, 18988}, {4, 21014, 4, 18912}}, +/* 18 */ {5040, {6, 22469, 6, 20223}, {5, 22469, 5, 20223}, {4, 20805, 4, 18725}, {4, 20846, 4, 18762}, {4, 20764, 4, 18687}}, +/* 19 */ {5060, {6, 22381, 6, 20143}, {5, 22381, 5, 20143}, {4, 20723, 4, 18651}, {4, 20764, 4, 18687}, {4, 20682, 4, 18614}}, +/* 20 */ {5080, {6, 22293, 6, 20063}, {5, 22293, 5, 20063}, {4, 20641, 4, 18577}, {4, 20682, 4, 18614}, {4, 20601, 4, 18541}}, +/* 21 */ {5180, {6, 21862, 6, 19676}, {5, 21862, 5, 19676}, {4, 20243, 4, 18219}, {4, 20282, 4, 18254}, {4, 20204, 4, 18183}}, +/* 22 */ {5200, {6, 21778, 6, 19600}, {5, 21778, 5, 19600}, {4, 20165, 4, 18148}, {4, 20204, 4, 18183}, {4, 20126, 4, 18114}}, +/* 23 */ {5220, {6, 21695, 6, 19525}, {5, 21695, 5, 19525}, {4, 20088, 4, 18079}, {4, 20126, 4, 18114}, {4, 20049, 4, 18044}}, +/* 24 */ {5240, {6, 21612, 6, 19451}, {5, 21612, 5, 19451}, {4, 20011, 4, 18010}, {4, 20049, 4, 18044}, {4, 19973, 4, 17976}}, +/* 25 */ {5260, {6, 21530, 6, 19377}, {5, 21530, 5, 19377}, {4, 19935, 4, 17941}, {4, 19973, 4, 17976}, {4, 19897, 4, 17907}}, +/* 26 */ {5280, {6, 21448, 6, 19303}, {5, 21448, 5, 19303}, {4, 19859, 4, 17873}, {4, 19897, 4, 17907}, {4, 19822, 4, 17840}}, +/* 27 */ {5300, {6, 21367, 6, 19230}, {5, 21367, 5, 19230}, {4, 19784, 4, 17806}, {4, 19822, 4, 17840}, {4, 19747, 4, 17772}}, +/* 28 */ {5320, {6, 21287, 6, 19158}, {5, 21287, 5, 19158}, {4, 19710, 4, 17739}, {4, 19747, 4, 17772}, {4, 19673, 4, 17706}}, +/* 29 */ {5500, {6, 20590, 6, 18531}, {5, 20590, 5, 18531}, {4, 19065, 4, 17159}, {4, 19100, 4, 17190}, {4, 19030, 4, 17127}}, +/* 30 */ {5520, {6, 20516, 6, 18464}, {5, 20516, 5, 18464}, {4, 18996, 4, 17096}, {4, 19030, 4, 17127}, {4, 18962, 4, 17065}}, +/* 31 */ {5540, {6, 20442, 6, 18397}, {5, 20442, 5, 18397}, {4, 18927, 4, 17035}, {4, 18962, 4, 17065}, {4, 18893, 4, 17004}}, +/* 32 */ {5560, {6, 20368, 6, 18331}, {5, 20368, 5, 18331}, {4, 18859, 4, 16973}, {4, 18893, 4, 17004}, {4, 18825, 4, 16943}}, +/* 33 */ {5580, {6, 20295, 6, 18266}, {5, 20295, 5, 18266}, {4, 18792, 4, 16913}, {4, 18825, 4, 16943}, {4, 18758, 4, 16882}}, +/* 34 */ {5600, {6, 20223, 6, 18200}, {5, 20223, 5, 18200}, {4, 18725, 4, 16852}, {4, 18758, 4, 16882}, {4, 18691, 4, 16822}}, +/* 35 */ {5620, {6, 20151, 6, 18136}, {5, 20151, 5, 18136}, {4, 18658, 4, 16792}, {4, 18691, 4, 16822}, {4, 18625, 4, 16762}}, +/* 36 */ {5640, {6, 20079, 6, 18071}, {5, 20079, 5, 18071}, {4, 18592, 4, 16733}, {4, 18625, 4, 16762}, {4, 18559, 4, 16703}}, +/* 37 */ {5660, {6, 20008, 6, 18007}, {5, 20008, 5, 18007}, {4, 18526, 4, 16673}, {4, 18559, 4, 16703}, {4, 18493, 4, 16644}}, +/* 38 */ {5680, {6, 19938, 6, 17944}, {5, 19938, 5, 17944}, {4, 18461, 4, 16615}, {4, 18493, 4, 16644}, {4, 18428, 4, 16586}}, +/* 39 */ {5700, {6, 19868, 6, 17881}, {5, 19868, 5, 17881}, {4, 18396, 4, 16556}, {4, 18428, 4, 16586}, {4, 18364, 4, 16527}}, +/* 40 */ {5745, {6, 19712, 6, 17741}, {5, 19712, 5, 17741}, {4, 18252, 4, 16427}, {4, 18284, 4, 16455}, {4, 18220, 4, 16398}}, +/* 41 */ {5765, {6, 19644, 6, 17679}, {5, 19644, 5, 17679}, {4, 18189, 5, 32740}, {4, 18220, 4, 16398}, {4, 18157, 5, 32683}}, +/* 42 */ {5785, {6, 19576, 6, 17618}, {5, 19576, 5, 17618}, {4, 18126, 5, 32626}, {4, 18157, 5, 32683}, {4, 18094, 5, 32570}}, +/* 43 */ {5805, {6, 19508, 6, 17558}, {5, 19508, 5, 17558}, {4, 18063, 5, 32514}, {4, 18094, 5, 32570}, {4, 18032, 5, 32458}}, +/* 44 */ {5825, {6, 19441, 6, 17497}, {5, 19441, 5, 17497}, {4, 18001, 5, 32402}, {4, 18032, 5, 32458}, {4, 17970, 5, 32347}}, +/* 45 */ {5170, {6, 21904, 6, 19714}, {5, 21904, 5, 19714}, {4, 20282, 4, 18254}, {4, 20321, 4, 18289}, {4, 20243, 4, 18219}}, +/* 46 */ {5190, {6, 21820, 6, 19638}, {5, 21820, 5, 19638}, {4, 20204, 4, 18183}, {4, 20243, 4, 18219}, {4, 20165, 4, 18148}}, +/* 47 */ {5210, {6, 21736, 6, 19563}, {5, 21736, 5, 19563}, {4, 20126, 4, 18114}, {4, 20165, 4, 18148}, {4, 20088, 4, 18079}}, +/* 48 */ {5230, {6, 21653, 6, 19488}, {5, 21653, 5, 19488}, {4, 20049, 4, 18044}, {4, 20088, 4, 18079}, {4, 20011, 4, 18010}} +}; +/* to reduce search time, please modify this define if you add or delete channel in table */ +#define First5GChannelIndex 14 + +void zfGetHwTurnOffdynParam(zdev_t* dev, + u32_t frequency, u8_t bw40, u8_t extOffset, + int* delta_slope_coeff_exp, + int* delta_slope_coeff_man, + int* delta_slope_coeff_exp_shgi, + int* delta_slope_coeff_man_shgi) +{ + /* Get param for turnoffdyn */ + u16_t i, arraySize; + + //zmw_get_wlan_dev(dev); + + arraySize = sizeof(zgPhyFreqCoeff)/sizeof(struct zsPhyFreqTable); + if (frequency < 3000) + { + /* 2.4GHz Channel */ + for (i = 0; i < First5GChannelIndex; i++) + { + if (frequency == zgPhyFreqCoeff[i].frequency) + break; + } + + if (i < First5GChannelIndex) + { + } + else + { + zm_msg1_scan(ZM_LV_0, "Unsupported 2.4G frequency = ", frequency); + return; + } + } + else + { + /* 5GHz Channel */ + for (i = First5GChannelIndex; i < arraySize; i++) + { + if (frequency == zgPhyFreqCoeff[i].frequency) + break; + } + + if (i < arraySize) + { + } + else + { + zm_msg1_scan(ZM_LV_0, "Unsupported 5G frequency = ", frequency); + return; + } + } + + /* FPGA DYNAMIC_HT2040_EN fclk = 10.8 */ + /* FPGA STATIC_HT20_ fclk = 21.6 */ + /* Real Chip fclk = 40 */ + #if ZM_FPGA_PHY == 1 + //fclk = 10.8; + *delta_slope_coeff_exp = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_exp; + *delta_slope_coeff_man = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_man; + *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_exp_shgi; + *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_man_shgi; + #else + //fclk = 40; + if (bw40) + { + /* ht2040 */ + if (extOffset == 1) { + *delta_slope_coeff_exp = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_exp; + *delta_slope_coeff_man = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_man; + *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_exp_shgi; + *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_man_shgi; + } + else { + *delta_slope_coeff_exp = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_exp; + *delta_slope_coeff_man = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_man; + *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_exp_shgi; + *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_man_shgi; + } + } + else + { + /* static 20 */ + *delta_slope_coeff_exp = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_exp; + *delta_slope_coeff_man = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_man; + *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_exp_shgi; + *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_man_shgi; + } + #endif +} + +/* Main routin frequency setting function */ +/* If 2.4G/5G switch, PHY need resetting BB and RF for band switch */ +/* Do the setting switch in zfSendFrequencyCmd() */ +void zfHpSetFrequencyEx(zdev_t* dev, u32_t frequency, u8_t bw40, + u8_t extOffset, u8_t initRF) +{ + u32_t cmd[9]; + u32_t cmdB[3]; + u16_t ret; + u8_t old_band; + u8_t new_band; + u32_t checkLoopCount; + u32_t tmpValue; + + int delta_slope_coeff_exp; + int delta_slope_coeff_man; + int delta_slope_coeff_exp_shgi; + int delta_slope_coeff_man_shgi; + + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv = wd->hpPrivate; + + zm_msg1_scan(ZM_LV_1, "Frequency = ", frequency); + zm_msg1_scan(ZM_LV_1, "bw40 = ", bw40); + zm_msg1_scan(ZM_LV_1, "extOffset = ", extOffset); + + if ( hpPriv->coldResetNeedFreq ) + { + hpPriv->coldResetNeedFreq = 0; + initRF = 2; + zm_debug_msg0("zfHpSetFrequencyEx: Do ColdReset "); + } + if ( hpPriv->isSiteSurvey == 2 ) + { + /* wait time for AGC and noise calibration : not in sitesurvey and connected */ + checkLoopCount = 2000; /* 2000*100 = 200ms */ + } + else + { + /* wait time for AGC and noise calibration : in sitesurvey */ + checkLoopCount = 1000; /* 1000*100 = 100ms */ + } + + hpPriv->latestFrequency = frequency; + hpPriv->latestBw40 = bw40; + hpPriv->latestExtOffset = extOffset; + + if ((hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_GENERAL) || + (hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_WPA2PSK)) + { + if ( frequency <= ZM_CH_G_14 ) + { + /* workaround for 11g Ad Hoc beacon distribution */ + zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, 0x7f0007); + //zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_AIFS, 0x1c04901c); + } + } + + /* AHB, DAC, ADC clock selection by static20/ht2040 */ + zfSelAdcClk(dev, bw40, frequency); + + /* clear bb_heavy_clip_enable */ + reg_write(0x99e0, 0x200); + zfFlushDelayWrite(dev); + + /* Set CTS/RTS rate */ + if ( frequency > ZM_CH_G_14 ) + { + //zfHpSetRTSCTSRate(dev, 0x10b010b); /* OFDM 6M */ + new_band = 1; + } + else + { + //zfHpSetRTSCTSRate(dev, 0x30003); /* CCK 11M */ + new_band = 0; + } + + if (((struct zsHpPriv*)wd->hpPrivate)->hwFrequency > ZM_CH_G_14) + old_band = 1; + else + old_band = 0; + + //Workaround for 2.4GHz only device + if ((hpPriv->OpFlags & 0x1) == 0) + { + if ((((struct zsHpPriv*)wd->hpPrivate)->hwFrequency == ZM_CH_G_1) && (frequency == ZM_CH_G_2)) + { + /* Force to do band switching */ + old_band = 1; + } + } + + /* Notify channel switch to firmware */ + /* TX/RX must be stopped by now */ + cmd[0] = 0 | (ZM_CMD_FREQ_STRAT << 8); + ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, 0); + + if ((initRF != 0) || (new_band != old_band) + || (((struct zsHpPriv*)wd->hpPrivate)->hwBw40 != bw40)) + { + /* band switch */ + zm_msg0_scan(ZM_LV_1, "=====band switch====="); + + if (initRF == 2 ) + { + //Cold reset BB/ADDA + zfDelayWriteInternalReg(dev, 0x1d4004, 0x800); + zfFlushDelayWrite(dev); + zm_msg0_scan(ZM_LV_1, "Do cold reset BB/ADDA"); + } + else + { + //Warm reset BB/ADDA + zfDelayWriteInternalReg(dev, 0x1d4004, 0x400); + zfFlushDelayWrite(dev); + } + + /* reset workaround state to default */ + hpPriv->rxStrongRSSI = 0; + hpPriv->strongRSSI = 0; + + zfDelayWriteInternalReg(dev, 0x1d4004, 0x0); + zfFlushDelayWrite(dev); + + zfInitPhy(dev, frequency, bw40); + +// zfiCheckRifs(dev); + + /* Bank 0 1 2 3 5 6 7 */ + zfSetRfRegs(dev, frequency); + /* Bank 4 */ + zfSetBank4AndPowerTable(dev, frequency, bw40, extOffset); + + cmd[0] = 32 | (ZM_CMD_RF_INIT << 8); + } + else //((new_band == old_band) && !initRF) + { + /* same band */ + + /* Force disable CR671 bit20 / 7823 */ + /* The bug has to do with the polarity of the pdadc offset calibration. There */ + /* is an initial calibration that is OK, and there is a continuous */ + /* calibration that updates the pddac with the wrong polarity. Fortunately */ + /* the second loop can be disabled with a bit called en_pd_dc_offset_thr. */ +#if 0 + cmdB[0] = 8 | (ZM_CMD_BITAND << 8);; + cmdB[1] = (0xa27c + 0x1bc000); + cmdB[2] = 0xffefffff; + ret = zfIssueCmd(dev, cmdB, 12, ZM_OID_INTERNAL_WRITE, 0); +#endif + + /* Bank 4 */ + zfSetBank4AndPowerTable(dev, frequency, bw40, extOffset); + + + cmd[0] = 32 | (ZM_CMD_FREQUENCY << 8); + } + + /* Compatibility for new layout UB83 */ + /* Setting code at CR1 here move from the func:zfHwHTEnable() in firmware */ + if (((struct zsHpPriv*)wd->hpPrivate)->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM) + { + /* UB83 : one stream */ + tmpValue = 0; + } + else + { + /* UB81, UB82 : two stream */ + tmpValue = 0x100; + } + + if (1) //if (((struct zsHpPriv*)wd->hpPrivate)->hw_HT_ENABLE == 1) + { + if (bw40 == 1) + { + if (extOffset == 1) { + reg_write(0x9804, tmpValue | 0x2d4); //3d4 for real + } + else { + reg_write(0x9804, tmpValue | 0x2c4); //3c4 for real + } + //# Dyn HT2040.Refer to Reg 1. + //#[3]:single length (4us) 1st HT long training symbol; use Walsh spatial spreading for 2 chains 2 streams TX + //#[c]:allow short GI for HT40 packets; enable HT detection. + //#[4]:enable 20/40 MHz channel detection. + } + else + { + reg_write(0x9804, tmpValue | 0x240); + //# Static HT20 + //#[3]:single length (4us) 1st HT long training symbol; use Walsh spatial spreading for 2 chains 2 streams TX + //#[4]:Otus don't allow short GI for HT20 packets yet; enable HT detection. + //#[0]:disable 20/40 MHz channel detection. + } + } + else + { + reg_write(0x9804, 0x0); + //# Legacy;# Direct Mapping for each chain. + //#Be modified by Oligo to add dynanic for legacy. + if (bw40 == 1) + { + reg_write(0x9804, 0x4); //# Dyn Legacy .Refer to reg 1. + } + else + { + reg_write(0x9804, 0x0); //# Static Legacy + } + } + zfFlushDelayWrite(dev); + /* end of ub83 compatibility */ + + /* Set Power, TPC, Gain table... */ + zfSetPowerCalTable(dev, frequency, bw40, extOffset); + + + /* store frequency */ + ((struct zsHpPriv*)wd->hpPrivate)->hwFrequency = (u16_t)frequency; + ((struct zsHpPriv*)wd->hpPrivate)->hwBw40 = bw40; + ((struct zsHpPriv*)wd->hpPrivate)->hwExtOffset = extOffset; + + zfGetHwTurnOffdynParam(dev, + frequency, bw40, extOffset, + &delta_slope_coeff_exp, + &delta_slope_coeff_man, + &delta_slope_coeff_exp_shgi, + &delta_slope_coeff_man_shgi); + + /* related functions */ + frequency = frequency*1000; + /* len[36] : type[0x30] : seq[?] */ +// cmd[0] = 28 | (ZM_CMD_FREQUENCY << 8); + cmd[1] = frequency; + cmd[2] = bw40;//((struct zsHpPriv*)wd->hpPrivate)->hw_DYNAMIC_HT2040_EN; + cmd[3] = (extOffset<<2)|0x1;//((wd->ExtOffset << 2) | ((struct zsHpPriv*)wd->hpPrivate)->hw_HT_ENABLE); + cmd[4] = delta_slope_coeff_exp; + cmd[5] = delta_slope_coeff_man; + cmd[6] = delta_slope_coeff_exp_shgi; + cmd[7] = delta_slope_coeff_man_shgi; + cmd[8] = checkLoopCount; + + ret = zfIssueCmd(dev, cmd, 36, ZM_CMD_SET_FREQUENCY, 0); + + // delay temporarily, wait for new PHY and RF + //zfwSleep(dev, 1000); +} + + +/******************** Key ********************/ + +u16_t zfHpResetKeyCache(zdev_t* dev) +{ + u8_t i; + u32_t key[4] = {0, 0, 0, 0}; + + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv=wd->hpPrivate; + + for(i=0;i<4;i++) + { + zfHpSetDefaultKey(dev, i, ZM_WEP64, key, NULL); + } + zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_L, 0x00); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_H, 0x00); + zfFlushDelayWrite(dev); + + hpPriv->camRollCallTable = (u64_t) 0; + + return 0; +} + + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfSetKey */ +/* Set key. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* */ +/* OUTPUTS */ +/* 0 : success */ +/* other : fail */ +/* */ +/* AUTHOR */ +/* Stephen Chen ZyDAS Technology Corporation 2006.1 */ +/* */ +/************************************************************************/ +/* ! please use zfCoreSetKey() in 80211Core for SetKey */ +u32_t zfHpSetKey(zdev_t* dev, u8_t user, u8_t keyId, u8_t type, + u16_t* mac, u32_t* key) +{ + u32_t cmd[(ZM_MAX_CMD_SIZE/4)]; + u16_t ret; + u16_t i; + + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv=wd->hpPrivate; + +#if 0 /* remove to zfCoreSetKey() */ + zmw_declare_for_critical_section(); + + zmw_enter_critical_section(dev); + wd->sta.flagKeyChanging++; + zm_debug_msg1(" zfHpSetKey++++ ", wd->sta.flagKeyChanging); + zmw_leave_critical_section(dev); +#endif + + cmd[0] = 0x0000281C; + cmd[1] = ((u32_t)keyId<<16) + (u32_t)user; + cmd[2] = ((u32_t)mac[0]<<16) + (u32_t)type; + cmd[3] = ((u32_t)mac[2]<<16) + ((u32_t)mac[1]); + + for (i=0; i<4; i++) + { + cmd[4+i] = key[i]; + } + + if (user < 64) + { + hpPriv->camRollCallTable |= ((u64_t) 1) << user; + } + + //ret = zfIssueCmd(dev, cmd, 32, ZM_OID_INTERNAL_WRITE, NULL); + ret = zfIssueCmd(dev, cmd, 32, ZM_CMD_SET_KEY, NULL); + return ret; +} + + +u32_t zfHpSetApPairwiseKey(zdev_t* dev, u16_t* staMacAddr, u8_t type, + u32_t* key, u32_t* micKey, u16_t staAid) +{ + if ((staAid!=0) && (staAid<64)) + { + zfHpSetKey(dev, (staAid-1), 0, type, staMacAddr, key); + if ((type == ZM_TKIP) +#ifdef ZM_ENABLE_CENC + || (type == ZM_CENC) +#endif //ZM_ENABLE_CENC + ) + zfHpSetKey(dev, (staAid-1), 1, type, staMacAddr, micKey); + return 0; + } + return 1; +} + +u32_t zfHpSetApGroupKey(zdev_t* dev, u16_t* apMacAddr, u8_t type, + u32_t* key, u32_t* micKey, u16_t vapId) +{ + zfHpSetKey(dev, ZM_USER_KEY_DEFAULT - 1 - vapId, 0, type, apMacAddr, key); // 6D18 modify from 0 to 1 ?? + if ((type == ZM_TKIP) +#ifdef ZM_ENABLE_CENC + || (type == ZM_CENC) +#endif //ZM_ENABLE_CENC + ) + zfHpSetKey(dev, ZM_USER_KEY_DEFAULT - 1 - vapId, 1, type, apMacAddr, micKey); + return 0; +} + +u32_t zfHpSetDefaultKey(zdev_t* dev, u8_t keyId, u8_t type, u32_t* key, u32_t* micKey) +{ + u16_t macAddr[3] = {0, 0, 0}; + + #ifdef ZM_ENABLE_IBSS_WPA2PSK + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv = wd->hpPrivate; + + if ( hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_WPA2PSK ) + { /* If not wpa2psk , use traditional */ + /* Because the bug of chip , defaultkey should follow the key map rule in register 700 */ + if ( keyId == 0 ) + zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 0, type, macAddr, key); + else + zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 1, type, macAddr, key); + } + else + zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 0, type, macAddr, key); + #else + zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 0, type, macAddr, key); + #endif + if ((type == ZM_TKIP) + +#ifdef ZM_ENABLE_CENC + || (type == ZM_CENC) +#endif //ZM_ENABLE_CENC + ) + { + zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 1, type, macAddr, micKey); + } + + return 0; +} + +u32_t zfHpSetPerUserKey(zdev_t* dev, u8_t user, u8_t keyId, u8_t* mac, u8_t type, u32_t* key, u32_t* micKey) +{ +#ifdef ZM_ENABLE_IBSS_WPA2PSK + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv = wd->hpPrivate; + + if ( hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_WPA2PSK ) + { /* If not wpa2psk , use traditional */ + if(keyId) + { /* Set Group Key */ + zfHpSetKey(dev, user, 1, type, (u16_t *)mac, key); + } + else if(keyId == 0) + { /* Set Pairwise Key */ + zfHpSetKey(dev, user, 0, type, (u16_t *)mac, key); + } + } + else + { + zfHpSetKey(dev, user, keyId, type, (u16_t *)mac, key); + } +#else + zfHpSetKey(dev, user, keyId, type, (u16_t *)mac, key); +#endif + + if ((type == ZM_TKIP) +#ifdef ZM_ENABLE_CENC + || (type == ZM_CENC) +#endif //ZM_ENABLE_CENC + ) + { + zfHpSetKey(dev, user, keyId + 1, type, (u16_t *)mac, micKey); + } + return 0; +} + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfHpRemoveKey */ +/* Remove key. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* */ +/* OUTPUTS */ +/* 0 : success */ +/* other : fail */ +/* */ +/* AUTHOR */ +/* Yuan-Gu Wei ZyDAS Technology Corporation 2006.6 */ +/* */ +/************************************************************************/ +u16_t zfHpRemoveKey(zdev_t* dev, u16_t user) +{ + u32_t cmd[(ZM_MAX_CMD_SIZE/4)]; + u16_t ret = 0; + + cmd[0] = 0x00002904; + cmd[1] = (u32_t)user; + + ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, NULL); + return ret; +} + + + +/******************** DMA ********************/ +u16_t zfHpStartRecv(zdev_t* dev) +{ + zfDelayWriteInternalReg(dev, 0x1c3d30, 0x100); + zfFlushDelayWrite(dev); + + return 0; +} + +u16_t zfHpStopRecv(zdev_t* dev) +{ + return 0; +} + + +/******************** MAC ********************/ +void zfInitMac(zdev_t* dev) +{ + /* ACK extension register */ + // jhlee temp : change value 0x2c -> 0x40 + // honda resolve short preamble problem : 0x40 -> 0x75 + zfDelayWriteInternalReg(dev, ZM_MAC_REG_ACK_EXTENSION, 0x40); // 0x28 -> 0x2c 6522:yflee + + /* TxQ0/1/2/3 Retry MAX=2 => transmit 3 times and degrade rate for retry */ + /* PB42 AP crash issue: */ + /* Workaround the crash issue by CTS/RTS, set retry max to zero for */ + /* workaround tx underrun which enable CTS/RTS */ + zfDelayWriteInternalReg(dev, ZM_MAC_REG_RETRY_MAX, 0); // 0x11111 => 0 + + /* use hardware MIC check */ + zfDelayWriteInternalReg(dev, ZM_MAC_REG_SNIFFER, 0x2000000); + + /* Set Rx threshold to 1600 */ +#if ZM_LARGEPAYLOAD_TEST == 1 + zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_THRESHOLD, 0xc4000); +#else + #ifndef ZM_DISABLE_AMSDU8K_SUPPORT + /* The maximum A-MSDU length is 3839/7935 */ + zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_THRESHOLD, 0xc1f80); + #else + zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_THRESHOLD, 0xc0f80); + #endif +#endif + + //zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x10A); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_PE_DELAY, 0x70); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_SLOT_TIME, 9<<10); + + /* CF-END mode */ + zfDelayWriteInternalReg(dev, 0x1c3b2c, 0x19000000); + + //NAV protects ACK only (in TXOP) + zfDelayWriteInternalReg(dev, 0x1c3b38, 0x201); + + + /* Set Beacon PHY CTRL's TPC to 0x7, TA1=1 */ + /* OTUS set AM to 0x1 */ + zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_HT1, 0x8000170); + + /* TODO : wep backoff protection 0x63c */ + zfDelayWriteInternalReg(dev, ZM_MAC_REG_BACKOFF_PROTECT, 0x105); + + /* AGG test code*/ + /* Aggregation MAX number and timeout */ + zfDelayWriteInternalReg(dev, 0x1c3b9c, 0x10000a); + /* Filter any control frames, BAR is bit 24 */ + zfDelayWriteInternalReg(dev, 0x1c368c, 0x0500ffff); + /* Enable deaggregator */ + zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1); + + /* Basic rate */ + zfDelayWriteInternalReg(dev, ZM_MAC_REG_BASIC_RATE, 0x150f); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_MANDATORY_RATE, 0x150f); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_RTS_CTS_RATE, 0x10b01bb); + + /* MIMO resposne control */ + zfDelayWriteInternalReg(dev, 0x1c3694, 0x4003C1E);/* bit 26~28 otus-AM */ + + /* Enable LED0 and LED1 */ + zfDelayWriteInternalReg(dev, 0x1d0100, 0x3); + zfDelayWriteInternalReg(dev, 0x1d0104, 0x3); + + /* switch MAC to OTUS interface */ + zfDelayWriteInternalReg(dev, 0x1c3600, 0x3); + + /* RXMAC A-MPDU length threshold */ + zfDelayWriteInternalReg(dev, 0x1c3c50, 0xffff); + + /* Phy register read timeout */ + zfDelayWriteInternalReg(dev, 0x1c3680, 0xf00008); + + /* Disable Rx TimeOut : workaround for BB. + * OTUS would interrupt the rx frame that sent by OWL TxUnderRun + * because OTUS rx timeout behavior, then OTUS would not ack the BA for + * this AMPDU from OWL. + * Fix by Perry Hwang. 2007/05/10. + * 0x1c362c : Rx timeout value : bit 27~16 + */ + zfDelayWriteInternalReg(dev, 0x1c362c, 0x0); + + //Set USB Rx stream mode MAX packet number to 2 + // Max packet number = *0x1e1110 + 1 + zfDelayWriteInternalReg(dev, 0x1e1110, 0x4); + //Set USB Rx stream mode timeout to 10us + zfDelayWriteInternalReg(dev, 0x1e1114, 0x80); + + //Set CPU clock frequency to 88/80MHz + zfDelayWriteInternalReg(dev, 0x1D4008, 0x73); + + //Set WLAN DMA interrupt mode : generate int per packet + zfDelayWriteInternalReg(dev, 0x1c3d7c, 0x110011); + + /* 7807 */ + /* enable func : Reset FIFO1 and FIFO2 when queue-gnt is low */ + /* 0x1c3bb0 Bit2 */ + /* Disable SwReset in firmware for TxHang, enable reset FIFO func. */ + zfDelayWriteInternalReg(dev, 0x1c3bb0, 0x4); + + /* Disables the CF_END frame */ + zfDelayWriteInternalReg(dev, ZM_MAC_REG_TXOP_NOT_ENOUGH_INDICATION, 0x141E0F48); + + /* Disable the SW Decrypt*/ + zfDelayWriteInternalReg(dev, 0x1c3678, 0x70); + zfFlushDelayWrite(dev); + //--------------------- + + /* Set TxQs CWMIN, CWMAX, AIFS and TXO to WME STA default. */ + zfUpdateDefaultQosParameter(dev, 0); + + //zfSelAdcClk(dev, 0); + + return; +} + + +u16_t zfHpSetSnifferMode(zdev_t* dev, u16_t on) +{ + if (on != 0) + { + zfDelayWriteInternalReg(dev, ZM_MAC_REG_SNIFFER, 0x2000001); + } + else + { + zfDelayWriteInternalReg(dev, ZM_MAC_REG_SNIFFER, 0x2000000); + } + zfFlushDelayWrite(dev); + return 0; +} + + +u16_t zfHpSetApStaMode(zdev_t* dev, u8_t mode) +{ + zmw_get_wlan_dev(dev); + + struct zsHpPriv* hpPriv = wd->hpPrivate; + hpPriv->dot11Mode = mode; + + switch(mode) + { + case ZM_HAL_80211_MODE_AP: + zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f0000a1); + zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1); + break; + + case ZM_HAL_80211_MODE_STA: + zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f000002); + zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1); + break; + + case ZM_HAL_80211_MODE_IBSS_GENERAL: + zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f000000); + zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1); + break; + + case ZM_HAL_80211_MODE_IBSS_WPA2PSK: + zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f0000e0); + zfDelayWriteInternalReg(dev, 0x1c3c40, 0x41); // for multiple ( > 2 ) stations IBSS network + break; + + default: + goto skip; + } + + zfFlushDelayWrite(dev); + +skip: + return 0; +} + + +u16_t zfHpSetBssid(zdev_t* dev, u8_t* bssidSrc) +{ + u32_t address; + u16_t *bssid = (u16_t *)bssidSrc; + + address = bssid[0] + (((u32_t)bssid[1]) << 16); + zfDelayWriteInternalReg(dev, 0x1c3618, address); + + address = (u32_t)bssid[2]; + zfDelayWriteInternalReg(dev, 0x1c361C, address); + zfFlushDelayWrite(dev); + return 0; +} + + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfHpUpdateQosParameter */ +/* Update TxQs CWMIN, CWMAX, AIFS and TXOP. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* cwminTbl : CWMIN parameter for TxQs */ +/* cwmaxTbl : CWMAX parameter for TxQs */ +/* aifsTbl: AIFS parameter for TxQs */ +/* txopTbl : TXOP parameter for TxQs */ +/* */ +/* OUTPUTS */ +/* none */ +/* */ +/* AUTHOR */ +/* Stephen ZyDAS Technology Corporation 2006.6 */ +/* */ +/************************************************************************/ +u8_t zfHpUpdateQosParameter(zdev_t* dev, u16_t* cwminTbl, u16_t* cwmaxTbl, + u16_t* aifsTbl, u16_t* txopTbl) +{ + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv = wd->hpPrivate; + + zm_msg0_mm(ZM_LV_0, "zfHalUpdateQosParameter()"); + + /* Note : Do not change cwmin for Q0 in Ad Hoc mode */ + /* otherwise driver will fail in Wifi beacon distribution */ + if (hpPriv->dot11Mode == ZM_HAL_80211_MODE_STA) + { +#if 0 //Restore CWmin to improve down link throughput + //cheating in BE traffic + if (wd->sta.EnableHT == 1) + { + //cheating in BE traffic + cwminTbl[0] = 7;//15; + } +#endif + cwmaxTbl[0] = 127;//1023; + aifsTbl[0] = 2*9+10;//3 * 9 + 10; + } + + /* CWMIN and CWMAX */ + zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, cwminTbl[0] + + ((u32_t)cwmaxTbl[0]<<16)); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_CW, cwminTbl[1] + + ((u32_t)cwmaxTbl[1]<<16)); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC2_CW, cwminTbl[2] + + ((u32_t)cwmaxTbl[2]<<16)); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC3_CW, cwminTbl[3] + + ((u32_t)cwmaxTbl[3]<<16)); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC4_CW, cwminTbl[4] + + ((u32_t)cwmaxTbl[4]<<16)); + + /* AIFS */ + zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_AIFS, aifsTbl[0] + +((u32_t)aifsTbl[0]<<12)+((u32_t)aifsTbl[0]<<24)); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC3_AC2_AIFS, (aifsTbl[0]>>8) + +((u32_t)aifsTbl[0]<<4)+((u32_t)aifsTbl[0]<<16)); + + /* TXOP */ + zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, txopTbl[0] + + ((u32_t)txopTbl[1]<<16)); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC3_AC2_TXOP, txopTbl[2] + + ((u32_t)txopTbl[3]<<16)); + + zfFlushDelayWrite(dev); + + hpPriv->txop[0] = txopTbl[0]; + hpPriv->txop[1] = txopTbl[1]; + hpPriv->txop[2] = txopTbl[2]; + hpPriv->txop[3] = txopTbl[3]; + hpPriv->cwmin[0] = cwminTbl[0]; + hpPriv->cwmax[0] = cwmaxTbl[0]; + hpPriv->cwmin[1] = cwminTbl[1]; + hpPriv->cwmax[1] = cwmaxTbl[1]; + + return 0; +} + + +void zfHpSetAtimWindow(zdev_t* dev, u16_t atimWin) +{ + zm_msg1_mm(ZM_LV_0, "Set ATIM window to ", atimWin); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_ATIM_WINDOW, atimWin); + zfFlushDelayWrite(dev); +} + + +void zfHpSetBasicRateSet(zdev_t* dev, u16_t bRateBasic, u16_t gRateBasic) +{ + zfDelayWriteInternalReg(dev, ZM_MAC_REG_BASIC_RATE, bRateBasic + | ((u16_t)gRateBasic<<8)); + zfFlushDelayWrite(dev); +} + + +/* HT40 send by OFDM 6M */ +/* otherwise use reg 0x638 */ +void zfHpSetRTSCTSRate(zdev_t* dev, u32_t rate) +{ + zfDelayWriteInternalReg(dev, ZM_MAC_REG_RTS_CTS_RATE, rate); + zfFlushDelayWrite(dev); +} + +void zfHpSetMacAddress(zdev_t* dev, u16_t* macAddr, u16_t macAddrId) +{ + if (macAddrId == 0) + { + zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_L, + (((u32_t)macAddr[1])<<16) | macAddr[0]); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_H, macAddr[2]); + } + else if (macAddrId <= 7) + { + zfDelayWriteInternalReg(dev, ZM_MAC_REG_ACK_TABLE+((macAddrId-1)*8), + macAddr[0] + ((u32_t)macAddr[1]<<16)); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_ACK_TABLE+((macAddrId-1)*8)+4, + macAddr[2]); + } + zfFlushDelayWrite(dev); +} + +void zfHpSetMulticastList(zdev_t* dev, u8_t size, u8_t* pList, u8_t bAllMulticast) +{ + struct zsMulticastAddr* pMacList = (struct zsMulticastAddr*) pList; + u8_t i; + u32_t value; + u32_t swRegMulHashValueH, swRegMulHashValueL; + + swRegMulHashValueH = 0x80000000; + swRegMulHashValueL = 0; + + if ( bAllMulticast ) + { + swRegMulHashValueH = swRegMulHashValueL = ~0; + } + else + { + for(i=0; i<size; i++) + { + value = pMacList[i].addr[5] >> 2; + + if ( value < 32 ) + { + swRegMulHashValueL |= (1 << value); + } + else + { + swRegMulHashValueH |= (1 << (value-32)); + } + } + } + + zfDelayWriteInternalReg(dev, ZM_MAC_REG_GROUP_HASH_TBL_L, + swRegMulHashValueL); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_GROUP_HASH_TBL_H, + swRegMulHashValueH); + zfFlushDelayWrite(dev); + return; +} + +/******************** Beacon ********************/ +void zfHpEnableBeacon(zdev_t* dev, u16_t mode, u16_t bcnInterval, u16_t dtim, u8_t enableAtim) +{ + u32_t value; + + zmw_get_wlan_dev(dev); + + /* Beacon Ready */ + zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_CTRL, 0); + /* Beacon DMA buffer address */ + zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_ADDR, ZM_BEACON_BUFFER_ADDRESS); + + value = bcnInterval; + + value |= (((u32_t) dtim) << 16); + + if (mode == ZM_MODE_AP) + { + + value |= 0x1000000; + } + else if (mode == ZM_MODE_IBSS) + { + value |= 0x2000000; + + if ( enableAtim ) + { + value |= 0x4000000; + } + ((struct zsHpPriv*)wd->hpPrivate)->ibssBcnEnabled = 1; + ((struct zsHpPriv*)wd->hpPrivate)->ibssBcnInterval = value; + } + zfDelayWriteInternalReg(dev, ZM_MAC_REG_PRETBTT, (bcnInterval-6)<<16); + + /* Beacon period and beacon enable */ + zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, value); + zfFlushDelayWrite(dev); +} + +void zfHpDisableBeacon(zdev_t* dev) +{ + zmw_get_wlan_dev(dev); + + ((struct zsHpPriv*)wd->hpPrivate)->ibssBcnEnabled = 0; + + zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, 0); + zfFlushDelayWrite(dev); +} + +void zfHpLedCtrl(zdev_t* dev, u16_t ledId, u8_t mode) +{ + u16_t state; + zmw_get_wlan_dev(dev); + + //zm_debug_msg1("LED ID=", ledId); + //zm_debug_msg1("LED mode=", mode); + if (ledId < 2) + { + if (((struct zsHpPriv*)wd->hpPrivate)->ledMode[ledId] != mode) + { + ((struct zsHpPriv*)wd->hpPrivate)->ledMode[ledId] = mode; + + state = ((struct zsHpPriv*)wd->hpPrivate)->ledMode[0] + | (((struct zsHpPriv*)wd->hpPrivate)->ledMode[1]<<1); + zfDelayWriteInternalReg(dev, 0x1d0104, state); + zfFlushDelayWrite(dev); + //zm_debug_msg0("Update LED"); + } + } +} + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfHpResetTxRx */ +/* Reset Tx and Rx Desc. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* */ +/* OUTPUTS */ +/* 0 : success */ +/* other : fail */ +/* */ +/* AUTHOR */ +/* Chao-Wen Yang ZyDAS Technology Corporation 2007.3 */ +/* */ +/************************************************************************/ +u16_t zfHpUsbReset(zdev_t* dev) +{ + u32_t cmd[(ZM_MAX_CMD_SIZE/4)]; + u16_t ret = 0; + + //zm_debug_msg0("CWY - Reset Tx and Rx"); + + cmd[0] = 0 | (ZM_CMD_RESET << 8); + + ret = zfIssueCmd(dev, cmd, 4, ZM_OID_INTERNAL_WRITE, NULL); + return ret; +} + +u16_t zfHpDKReset(zdev_t* dev, u8_t flag) +{ + u32_t cmd[(ZM_MAX_CMD_SIZE/4)]; + u16_t ret = 0; + + //zm_debug_msg0("CWY - Reset Tx and Rx"); + + cmd[0] = 4 | (ZM_CMD_DKRESET << 8); + cmd[1] = flag; + + ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, NULL); + return ret; +} + +u32_t zfHpCwmUpdate(zdev_t* dev) +{ + //u32_t cmd[3]; + //u16_t ret; + // + //cmd[0] = 0x00000008; + //cmd[1] = 0x1c36e8; + //cmd[2] = 0x1c36ec; + // + //ret = zfIssueCmd(dev, cmd, 12, ZM_CWM_READ, 0); + //return ret; + zmw_get_wlan_dev(dev); + + struct zsHpPriv* hpPriv=wd->hpPrivate; + + zfCoreCwmBusy(dev, zfCwmIsExtChanBusy(hpPriv->ctlBusy, hpPriv->extBusy)); + + hpPriv->ctlBusy = 0; + hpPriv->extBusy = 0; + + return 0; +} + +u32_t zfHpAniUpdate(zdev_t* dev) +{ + u32_t cmd[5]; + u16_t ret; + + cmd[0] = 0x00000010; + cmd[1] = 0x1c36e8; + cmd[2] = 0x1c36ec; + cmd[3] = 0x1c3cb4; + cmd[4] = 0x1c3cb8; + + ret = zfIssueCmd(dev, cmd, 20, ZM_ANI_READ, 0); + return ret; +} + +/* + * Update Beacon RSSI in ANI + */ +u32_t zfHpAniUpdateRssi(zdev_t* dev, u8_t rssi) +{ + zmw_get_wlan_dev(dev); + + struct zsHpPriv* hpPriv=wd->hpPrivate; + + hpPriv->stats.ast_nodestats.ns_avgbrssi = rssi; + + return 0; +} + +#define ZM_SEEPROM_MAC_ADDRESS_OFFSET (0x1400 + (0x106<<1)) +#define ZM_SEEPROM_REGDOMAIN_OFFSET (0x1400 + (0x104<<1)) +#define ZM_SEEPROM_VERISON_OFFSET (0x1400 + (0x102<<1)) +#define ZM_SEEPROM_HARDWARE_TYPE_OFFSET (0x1374) +#define ZM_SEEPROM_HW_HEAVY_CLIP (0x161c) + +u32_t zfHpGetMacAddress(zdev_t* dev) +{ + u32_t cmd[7]; + u16_t ret; + + cmd[0] = 0x00000000 | 24; + cmd[1] = ZM_SEEPROM_MAC_ADDRESS_OFFSET; + cmd[2] = ZM_SEEPROM_MAC_ADDRESS_OFFSET+4; + cmd[3] = ZM_SEEPROM_REGDOMAIN_OFFSET; + cmd[4] = ZM_SEEPROM_VERISON_OFFSET; + cmd[5] = ZM_SEEPROM_HARDWARE_TYPE_OFFSET; + cmd[6] = ZM_SEEPROM_HW_HEAVY_CLIP; + + ret = zfIssueCmd(dev, cmd, 28, ZM_MAC_READ, 0); + return ret; +} + +u32_t zfHpGetTransmitPower(zdev_t* dev) +{ + zmw_get_wlan_dev(dev); + + struct zsHpPriv* hpPriv = wd->hpPrivate; + u16_t tpc = 0; + + if (hpPriv->hwFrequency < 3000) { + tpc = hpPriv->tPow2x2g[0] & 0x3f; + wd->maxTxPower2 &= 0x3f; + tpc = (tpc > wd->maxTxPower2)? wd->maxTxPower2 : tpc; + } else { + tpc = hpPriv->tPow2x5g[0] & 0x3f; + wd->maxTxPower5 &= 0x3f; + tpc = (tpc > wd->maxTxPower5)? wd->maxTxPower5 : tpc; + } + + return tpc; +} + +u8_t zfHpGetMinTxPower(zdev_t* dev) +{ + zmw_get_wlan_dev(dev); + + struct zsHpPriv* hpPriv = wd->hpPrivate; + u8_t tpc = 0; + + if (hpPriv->hwFrequency < 3000) + { + if(wd->BandWidth40) + { + //40M + tpc = (hpPriv->tPow2x2gHt40[7]&0x3f); + } + else + { + //20M + tpc = (hpPriv->tPow2x2gHt20[7]&0x3f); + } + } + else + { + if(wd->BandWidth40) + { + //40M + tpc = (hpPriv->tPow2x5gHt40[7]&0x3f); + } + else + { + //20M + tpc = (hpPriv->tPow2x5gHt20[7]&0x3f); + } + } + + return tpc; +} + +u8_t zfHpGetMaxTxPower(zdev_t* dev) +{ + zmw_get_wlan_dev(dev); + + struct zsHpPriv* hpPriv = wd->hpPrivate; + u8_t tpc = 0; + + if (hpPriv->hwFrequency < 3000) + { + tpc = (hpPriv->tPow2xCck[0]&0x3f); + } + else + { + tpc =(hpPriv->tPow2x5g[0]&0x3f); + } + + return tpc; +} + +u32_t zfHpLoadEEPROMFromFW(zdev_t* dev) +{ + u32_t cmd[16]; + u32_t ret=0, i, j; + zmw_get_wlan_dev(dev); + + i = ((struct zsHpPriv*)wd->hpPrivate)->eepromImageRdReq; + + cmd[0] = ZM_HAL_MAX_EEPROM_PRQ*4; + + for (j=0; j<ZM_HAL_MAX_EEPROM_PRQ; j++) + { + cmd[j+1] = 0x1000 + (((i*ZM_HAL_MAX_EEPROM_PRQ) + j)*4); + } + + ret = zfIssueCmd(dev, cmd, (ZM_HAL_MAX_EEPROM_PRQ+1)*4, ZM_EEPROM_READ, 0); + + return ret; +} + +void zfHpHeartBeat(zdev_t* dev) +{ + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv=wd->hpPrivate; + u8_t polluted = 0; + u8_t ackTpc; + + /* Workaround : Make OTUS fire more beacon in ad hoc mode in 2.4GHz */ + if (hpPriv->ibssBcnEnabled != 0) + { + if (hpPriv->hwFrequency <= ZM_CH_G_14) + { + if ((wd->tick % 10) == 0) + { + if ((wd->tick % 40) == 0) + { + zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, hpPriv->ibssBcnInterval-1); + polluted = 1; + } + else + { + zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, hpPriv->ibssBcnInterval); + polluted = 1; + } + } + } + } + + if ((wd->tick & 0x3f) == 0x25) + { + /* Workaround for beacon stuck after SW reset */ + if (hpPriv->ibssBcnEnabled != 0) + { + zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_ADDR, ZM_BEACON_BUFFER_ADDRESS); + polluted = 1; + } + + //DbgPrint("hpPriv->aggMaxDurationBE=%d", hpPriv->aggMaxDurationBE); + //DbgPrint("wd->sta.avgSizeOfReceivePackets=%d", wd->sta.avgSizeOfReceivePackets); + if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE ) + && (zfStaIsConnected(dev)) + && (wd->sta.EnableHT == 1) //11n mode + && (wd->BandWidth40 == 1) //40MHz mode + && (wd->sta.enableDrvBA ==0) //Marvel AP + && (hpPriv->aggMaxDurationBE > 2000) //BE TXOP > 2ms + && (wd->sta.avgSizeOfReceivePackets > 1420)) + { + zfDelayWriteInternalReg(dev, 0x1c3b9c, 0x8000a); + polluted = 1; + } + else + { + zfDelayWriteInternalReg(dev, 0x1c3b9c, hpPriv->aggPktNum); + polluted = 1; + } + + if (wd->dynamicSIFSEnable == 0) + { + if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE ) + && (zfStaIsConnected(dev)) + && (wd->sta.EnableHT == 1) //11n mode + && (wd->BandWidth40 == 0) //20MHz mode + && (wd->sta.enableDrvBA ==0)) //Marvel AP + { + zfDelayWriteInternalReg(dev, 0x1c3698, 0x5144000); + polluted = 1; + } + else + { + zfDelayWriteInternalReg(dev, 0x1c3698, 0xA144000); + polluted = 1; + } + } + else + { + if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE ) + && (zfStaIsConnected(dev)) + && (wd->sta.EnableHT == 1) //11n mode + && (wd->sta.athOwlAp == 1)) //Atheros AP + { + if (hpPriv->retransmissionEvent) + { + switch(hpPriv->latestSIFS) + { + case 0: + hpPriv->latestSIFS = 1; + zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0x8144000); + break; + case 1: + hpPriv->latestSIFS = 2; + zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000); + break; + case 2: + hpPriv->latestSIFS = 3; + zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xc144000); + break; + case 3: + hpPriv->latestSIFS = 0; + zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000); + break; + default: + hpPriv->latestSIFS = 0; + zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000); + break; + } + polluted = 1; + zm_debug_msg1("##### Correct Tx retransmission issue #####, ", hpPriv->latestSIFS); + hpPriv->retransmissionEvent = 0; + } + } + else + { + hpPriv->latestSIFS = 0; + hpPriv->retransmissionEvent = 0; + zfDelayWriteInternalReg(dev, 0x1c3698, 0xA144000); + polluted = 1; + } + } + + if ((wd->sta.bScheduleScan == FALSE) && (wd->sta.bChannelScan == FALSE)) + { +#define ZM_SIGNAL_THRESHOLD 66 + if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE ) + && (zfStaIsConnected(dev)) + && (wd->SignalStrength > ZM_SIGNAL_THRESHOLD)) + { + /* remove state handle, always rewrite register setting */ + //if (hpPriv->strongRSSI == 0) + { + hpPriv->strongRSSI = 1; + /* Strong RSSI, set ACK to one Tx stream and lower Tx power 7dbm */ + if (hpPriv->currentAckRtsTpc > (14+10)) + { + ackTpc = hpPriv->currentAckRtsTpc - 14; + } + else + { + ackTpc = 10; + } + zfDelayWriteInternalReg(dev, 0x1c3694, ((ackTpc) << 20) | (0x1<<26)); + zfDelayWriteInternalReg(dev, 0x1c3bb4, ((ackTpc) << 5 ) | (0x1<<11) | + ((ackTpc) << 21) | (0x1<<27) ); + polluted = 1; + } + } + else + { + /* remove state handle, always rewrite register setting */ + //if (hpPriv->strongRSSI == 1) + { + hpPriv->strongRSSI = 0; + if (hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM) + { + zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->currentAckRtsTpc&0x3f) << 20) | (0x1<<26)); + zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->currentAckRtsTpc&0x3f) << 5 ) | (0x1<<11) | + ((hpPriv->currentAckRtsTpc&0x3f) << 21) | (0x1<<27) ); + } + else + { + zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->currentAckRtsTpc&0x3f) << 20) | (0x5<<26)); + zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->currentAckRtsTpc&0x3f) << 5 ) | (0x5<<11) | + ((hpPriv->currentAckRtsTpc&0x3f) << 21) | (0x5<<27) ); + } + polluted = 1; + } + } +#undef ZM_SIGNAL_THRESHOLD + } + + if ((hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM) == 0) + { + if ((wd->sta.bScheduleScan == FALSE) && (wd->sta.bChannelScan == FALSE)) + { + #define ZM_RX_SIGNAL_THRESHOLD_H 71 + #define ZM_RX_SIGNAL_THRESHOLD_L 66 + u8_t rxSignalThresholdH = ZM_RX_SIGNAL_THRESHOLD_H; + u8_t rxSignalThresholdL = ZM_RX_SIGNAL_THRESHOLD_L; + #undef ZM_RX_SIGNAL_THRESHOLD_H + #undef ZM_RX_SIGNAL_THRESHOLD_L + + if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE ) + && (zfStaIsConnected(dev)) + && (wd->SignalStrength > rxSignalThresholdH) + )//&& (hpPriv->rxStrongRSSI == 0)) + { + hpPriv->rxStrongRSSI = 1; + //zfDelayWriteInternalReg(dev, 0x1c5964, 0x1220); + //zfDelayWriteInternalReg(dev, 0x1c5960, 0x900); + //zfDelayWriteInternalReg(dev, 0x1c6960, 0x900); + //zfDelayWriteInternalReg(dev, 0x1c7960, 0x900); + if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE + { + if (hpPriv->hwFrequency <= ZM_CH_G_14) + { + zfDelayWriteInternalReg(dev, 0x1c8960, 0x900); + } + else + { + zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b49); + } + } + else + { + zfDelayWriteInternalReg(dev, 0x1c8960, 0x0900); + } + polluted = 1; + } + else if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE ) + && (zfStaIsConnected(dev)) + && (wd->SignalStrength > rxSignalThresholdL) + )//&& (hpPriv->rxStrongRSSI == 1)) + { + //Do nothing to prevent frequently Rx switching + } + else + { + /* remove state handle, always rewrite register setting */ + //if (hpPriv->rxStrongRSSI == 1) + { + hpPriv->rxStrongRSSI = 0; + //zfDelayWriteInternalReg(dev, 0x1c5964, 0x1120); + //zfDelayWriteInternalReg(dev, 0x1c5960, 0x9b40); + //zfDelayWriteInternalReg(dev, 0x1c6960, 0x9b40); + //zfDelayWriteInternalReg(dev, 0x1c7960, 0x9b40); + if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE + { + if (hpPriv->hwFrequency <= ZM_CH_G_14) + { + zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b49); + } + else + { + zfDelayWriteInternalReg(dev, 0x1c8960, 0x0900); + } + } + else + { + zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b40); + } + polluted = 1; + } + } + + } + } + + if (hpPriv->usbAcSendBytes[3] > (hpPriv->usbAcSendBytes[0]*2)) + { + zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, hpPriv->txop[3]); + polluted = 1; + } + else if (hpPriv->usbAcSendBytes[2] > (hpPriv->usbAcSendBytes[0]*2)) + { + zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, hpPriv->txop[2]); + polluted = 1; + } + else if (hpPriv->usbAcSendBytes[1] > (hpPriv->usbAcSendBytes[0]*2)) + { + zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, hpPriv->cwmin[1]+((u32_t)hpPriv->cwmax[1]<<16)); + polluted = 1; + } + else + { + if (hpPriv->slotType == 1) + { + if ((wd->sta.enableDrvBA ==0) //Marvel AP + && (hpPriv->aggMaxDurationBE > 2000)) //BE TXOP > 2ms + { + zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, (hpPriv->cwmin[0]/2)+((u32_t)hpPriv->cwmax[0]<<16)); + } + else + { + zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, hpPriv->cwmin[0]+((u32_t)hpPriv->cwmax[0]<<16)); + } + polluted = 1; + } + else + { + /* Compensation for 20us slot time */ + //zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, 58+((u32_t)hpPriv->cwmax[0]<<16)); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, hpPriv->cwmin[0]+((u32_t)hpPriv->cwmax[0]<<16)); + polluted = 1; + } + + if ((wd->sta.SWEncryptEnable & (ZM_SW_TKIP_ENCRY_EN|ZM_SW_WEP_ENCRY_EN)) == 0) + { + zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, hpPriv->txop[0]); + polluted = 1; + } + else + { + zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, 0x30); + polluted = 1; + } + + } + hpPriv->usbAcSendBytes[3] = 0; + hpPriv->usbAcSendBytes[2] = 0; + hpPriv->usbAcSendBytes[1] = 0; + hpPriv->usbAcSendBytes[0] = 0; + } + + if (polluted == 1) + { + zfFlushDelayWrite(dev); + } + + return; +} + +/* + * 0x1d4008 : AHB, DAC, ADC clock selection + * bit1~0 AHB_CLK : AHB clock selection, + * 00 : OSC 40MHz; + * 01 : 20MHz in A mode, 22MHz in G mode; + * 10 : 40MHz in A mode, 44MHz in G mode; + * 11 : 80MHz in A mode, 88MHz in G mode. + * bit3~2 CLK_SEL : Select the clock source of clk160 in ADDAC. + * 00 : PLL divider's output; + * 01 : PLL divider's output divided by 2; + * 10 : PLL divider's output divided by 4; + * 11 : REFCLK from XTALOSCPAD. + */ +void zfSelAdcClk(zdev_t* dev, u8_t bw40, u32_t frequency) +{ + if(bw40 == 1) + { + //zfDelayWriteInternalReg(dev, 0x1D4008, 0x73); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x10A); + zfFlushDelayWrite(dev); + } + else + { + //zfDelayWriteInternalReg(dev, 0x1D4008, 0x70); + if ( frequency <= ZM_CH_G_14 ) + { + zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x105); + } + else + { + zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x104); + } + zfFlushDelayWrite(dev); + } +} + +u32_t zfHpEchoCommand(zdev_t* dev, u32_t value) +{ + u32_t cmd[2]; + u16_t ret; + + cmd[0] = 0x00008004; + cmd[1] = value; + + ret = zfIssueCmd(dev, cmd, 8, ZM_CMD_ECHO, NULL); + return ret; +} + +#ifdef ZM_DRV_INIT_USB_MODE + +#define ZM_USB_US_STREAM_MODE 0x00000000 +#define ZM_USB_US_PACKET_MODE 0x00000008 +#define ZM_USB_DS_ENABLE 0x00000001 +#define ZM_USB_US_ENABLE 0x00000002 + +#define ZM_USB_RX_STREAM_4K 0x00000000 +#define ZM_USB_RX_STREAM_8K 0x00000010 +#define ZM_USB_RX_STREAM_16K 0x00000020 +#define ZM_USB_RX_STREAM_32K 0x00000030 + +#define ZM_USB_TX_STREAM_MODE 0x00000040 + +#define ZM_USB_MODE_CTRL_REG 0x001E1108 + +void zfInitUsbMode(zdev_t* dev) +{ + u32_t mode; + zmw_get_wlan_dev(dev); + + /* TODO: Set USB mode by reading registery */ + mode = ZM_USB_DS_ENABLE | ZM_USB_US_ENABLE | ZM_USB_US_PACKET_MODE; + + zfDelayWriteInternalReg(dev, ZM_USB_MODE_CTRL_REG, mode); + zfFlushDelayWrite(dev); +} +#endif + +void zfDumpEepBandEdges(struct ar5416Eeprom* eepromImage); +void zfPrintTargetPower2G(u8_t* tPow2xCck, u8_t* tPow2x2g, u8_t* tPow2x2gHt20, u8_t* tPow2x2gHt40); +void zfPrintTargetPower5G(u8_t* tPow2x5g, u8_t* tPow2x5gHt20, u8_t* tPow2x5gHt40); + + +s32_t zfInterpolateFunc(s32_t x, s32_t x1, s32_t y1, s32_t x2, s32_t y2) +{ + s32_t y; + + if (y2 == y1) + { + y = y1; + } + else if (x == x1) + { + y = y1; + } + else if (x == x2) + { + y = y2; + } + else if (x2 != x1) + { + y = y1 + (((y2-y1) * (x-x1))/(x2-x1)); + } + else + { + y = y1; + } + + return y; +} + +//#define ZM_ENABLE_TPC_WINDOWS_DEBUG +//#define ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG + +/* the tx power offset workaround for ART vs NDIS/MDK */ +#define HALTX_POWER_OFFSET 0 + +u8_t zfInterpolateFuncX(u8_t x, u8_t x1, u8_t y1, u8_t x2, u8_t y2) +{ + s32_t y; + s32_t inc; + + #define ZM_MULTIPLIER 8 + y = zfInterpolateFunc((s32_t)x<<ZM_MULTIPLIER, + (s32_t)x1<<ZM_MULTIPLIER, + (s32_t)y1<<ZM_MULTIPLIER, + (s32_t)x2<<ZM_MULTIPLIER, + (s32_t)y2<<ZM_MULTIPLIER); + + inc = (y & (1<<(ZM_MULTIPLIER-1))) >> (ZM_MULTIPLIER-1); + y = (y >> ZM_MULTIPLIER) + inc; + #undef ZM_MULTIPLIER + + return (u8_t)y; +} + +u8_t zfGetInterpolatedValue(u8_t x, u8_t* x_array, u8_t* y_array) +{ + s32_t y; + u16_t xIndex; + + if (x <= x_array[1]) + { + xIndex = 0; + } + else if (x <= x_array[2]) + { + xIndex = 1; + } + else if (x <= x_array[3]) + { + xIndex = 2; + } + else //(x > x_array[3]) + { + xIndex = 3; + } + + y = zfInterpolateFuncX(x, + x_array[xIndex], + y_array[xIndex], + x_array[xIndex+1], + y_array[xIndex+1]); + + return (u8_t)y; +} + +u8_t zfFindFreqIndex(u8_t f, u8_t* fArray, u8_t fArraySize) +{ + u8_t i; +#ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + DbgPrint("f=%d ", f); + for (i=0; i<fArraySize; i++) + { + DbgPrint("%d ", fArray[i]); + } + DbgPrint("\n"); +#endif + i=fArraySize-2; + while(1) + { + if (f >= fArray[i]) + { + return i; + } + if (i!=0) + { + i--; + } + else + { + return 0; + } + } +} + + + + +void zfInitPowerCal(zdev_t* dev) +{ + //Program PHY Tx power relatives registers +#define zm_write_phy_reg(cr, val) reg_write((cr*4)+0x9800, val) + + zm_write_phy_reg(79, 0x7f); + zm_write_phy_reg(77, 0x3f3f3f3f); + zm_write_phy_reg(78, 0x3f3f3f3f); + zm_write_phy_reg(653, 0x3f3f3f3f); + zm_write_phy_reg(654, 0x3f3f3f3f); + zm_write_phy_reg(739, 0x3f3f3f3f); + zm_write_phy_reg(740, 0x3f3f3f3f); + zm_write_phy_reg(755, 0x3f3f3f3f); + zm_write_phy_reg(756, 0x3f3f3f3f); + zm_write_phy_reg(757, 0x3f3f3f3f); + +#undef zm_write_phy_reg +} + + + +void zfPrintTp(u8_t* pwr0, u8_t* vpd0, u8_t* pwr1, u8_t* vpd1) +{ + #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + DbgPrint("pwr0 : %d, %d, %d, %d ,%d\n", pwr0[0], pwr0[1], pwr0[2], pwr0[3], pwr0[4]); + DbgPrint("vpd0 : %d, %d, %d, %d ,%d\n", vpd0[0], vpd0[1], vpd0[2], vpd0[3], vpd0[4]); + DbgPrint("pwr1 : %d, %d, %d, %d ,%d\n", pwr1[0], pwr1[1], pwr1[2], pwr1[3], pwr1[4]); + DbgPrint("vpd1 : %d, %d, %d, %d ,%d\n", vpd1[0], vpd1[1], vpd1[2], vpd1[3], vpd1[4]); + #endif +} + + +/* + * To find CTL index(0~23) + * return 24(AR5416_NUM_CTLS)=>no desired index found + */ +u8_t zfFindCtlEdgesIndex(zdev_t* dev, u8_t desired_CtlIndex) +{ + u8_t i; + struct zsHpPriv* hpPriv; + struct ar5416Eeprom* eepromImage; + + zmw_get_wlan_dev(dev); + + hpPriv = wd->hpPrivate; + + eepromImage = (struct ar5416Eeprom*)&(hpPriv->eepromImage[(1024+512)/4]); + + //for (i = 0; (i < AR5416_NUM_CTLS) && eepromImage->ctlIndex[i]; i++) + for (i = 0; i < AR5416_NUM_CTLS; i++) + { + if(desired_CtlIndex == eepromImage->ctlIndex[i]) + break; + } + return i; +} + +/************************************************************************** + * fbin2freq + * + * Get channel value from binary representation held in eeprom + * RETURNS: the frequency in MHz + */ +u32_t +fbin2freq(u8_t fbin, u8_t is2GHz) +{ + /* + * Reserved value 0xFF provides an empty definition both as + * an fbin and as a frequency - do not convert + */ + if (fbin == AR5416_BCHAN_UNUSED) { + return fbin; + } + + return (u32_t)((is2GHz==1) ? (2300 + fbin) : (4800 + 5 * fbin)); +} + + +u8_t zfGetMaxEdgePower(zdev_t* dev, CAL_CTL_EDGES *pCtlEdges, u32_t freq) +{ + u8_t i; + u8_t maxEdgePower; + u8_t is2GHz; + struct zsHpPriv* hpPriv; + struct ar5416Eeprom* eepromImage; + + zmw_get_wlan_dev(dev); + + hpPriv = wd->hpPrivate; + + eepromImage = (struct ar5416Eeprom*)&(hpPriv->eepromImage[(1024+512)/4]); + + if(freq > ZM_CH_G_14) + is2GHz = 0; + else + is2GHz = 1; + + maxEdgePower = AR5416_MAX_RATE_POWER; + + /* Get the edge power */ + for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pCtlEdges[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) + { + /* + * If there's an exact channel match or an inband flag set + * on the lower channel use the given rdEdgePower + */ + if (freq == fbin2freq(pCtlEdges[i].bChannel, is2GHz)) + { + maxEdgePower = pCtlEdges[i].tPower; + #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG + zm_dbg(("zfGetMaxEdgePower index i = %d \n", i)); + #endif + break; + } + else if ((i > 0) && (freq < fbin2freq(pCtlEdges[i].bChannel, is2GHz))) + { + if (fbin2freq(pCtlEdges[i - 1].bChannel, is2GHz) < freq && pCtlEdges[i - 1].flag) + { + maxEdgePower = pCtlEdges[i - 1].tPower; + #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG + zm_dbg(("zfGetMaxEdgePower index i-1 = %d \n", i-1)); + #endif + } + /* Leave loop - no more affecting edges possible in this monotonic increasing list */ + break; + } + + } + + if( i == AR5416_NUM_BAND_EDGES ) + { + if (freq > fbin2freq(pCtlEdges[i - 1].bChannel, is2GHz) && pCtlEdges[i - 1].flag) + { + maxEdgePower = pCtlEdges[i - 1].tPower; + #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG + zm_dbg(("zfGetMaxEdgePower index=>i-1 = %d \n", i-1)); + #endif + } + } + + zm_assert(maxEdgePower > 0); + + #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG + if ( maxEdgePower == AR5416_MAX_RATE_POWER ) + { + zm_dbg(("zfGetMaxEdgePower = %d !!!\n", AR5416_MAX_RATE_POWER)); + } + #endif + return maxEdgePower; +} + +u32_t zfAdjustHT40FreqOffset(zdev_t* dev, u32_t frequency, u8_t bw40, u8_t extOffset) +{ + u32_t newFreq = frequency; + + if (bw40 == 1) + { + if (extOffset == 1) + { + newFreq += 10; + } + else + { + newFreq -= 10; + } + } + return newFreq; +} + +u32_t zfHpCheckDoHeavyClip(zdev_t* dev, u32_t freq, CAL_CTL_EDGES *pCtlEdges, u8_t bw40) +{ + u32_t ret = 0; + u8_t i; + u8_t is2GHz; + struct zsHpPriv* hpPriv; + + zmw_get_wlan_dev(dev); + + hpPriv = wd->hpPrivate; + + if(freq > ZM_CH_G_14) + is2GHz = 0; + else + is2GHz = 1; + + /* HT40 force enable heavy clip */ + if (bw40) + { + ret |= 0xf0; + } +#if 1 + /* HT20 : frequency bandedge */ + for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pCtlEdges[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) + { + if (freq == fbin2freq(pCtlEdges[i].bChannel, is2GHz)) + { + if (pCtlEdges[i].flag == 0) + { + ret |= 0xf; + } + break; + } + } +#endif + + return ret; +} + + +void zfSetPowerCalTable(zdev_t* dev, u32_t frequency, u8_t bw40, u8_t extOffset) +{ + struct ar5416Eeprom* eepromImage; + u8_t pwr0[5]; + u8_t pwr1[5]; + u8_t vpd0[5]; + u8_t vpd1[5]; + u8_t vpd_chain1[128]; + u8_t vpd_chain3[128]; + u16_t boundary1 = 18; //CR 667 + u16_t powerTxMax = 63; //CR 79 + u8_t i; + struct zsHpPriv* hpPriv; + u8_t fbin; + u8_t index, max2gIndex, max5gIndex; + u8_t chain0pwrPdg0[5]; + u8_t chain0vpdPdg0[5]; + u8_t chain0pwrPdg1[5]; + u8_t chain0vpdPdg1[5]; + u8_t chain2pwrPdg0[5]; + u8_t chain2vpdPdg0[5]; + u8_t chain2pwrPdg1[5]; + u8_t chain2vpdPdg1[5]; + u8_t fbinArray[8]; + + /* 4 CTL */ + u8_t ctl_i; + u8_t desired_CtlIndex; + + u8_t ctlEdgesMaxPowerCCK = AR5416_MAX_RATE_POWER; + u8_t ctlEdgesMaxPower2G = AR5416_MAX_RATE_POWER; + u8_t ctlEdgesMaxPower2GHT20 = AR5416_MAX_RATE_POWER; + u8_t ctlEdgesMaxPower2GHT40 = AR5416_MAX_RATE_POWER; + u8_t ctlEdgesMaxPower5G = AR5416_MAX_RATE_POWER; + u8_t ctlEdgesMaxPower5GHT20 = AR5416_MAX_RATE_POWER; + u8_t ctlEdgesMaxPower5GHT40 = AR5416_MAX_RATE_POWER; + + u8_t ctlOffset; + + zmw_get_wlan_dev(dev); + + hpPriv = wd->hpPrivate; + + eepromImage = (struct ar5416Eeprom*)&(hpPriv->eepromImage[(1024+512)/4]); + + // Check the total bytes of the EEPROM structure to see the dongle have been calibrated or not. + if (eepromImage->baseEepHeader.length == 0xffff) + { + #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG + zm_dbg(("Warning! This dongle not been calibrated\n")); + #endif + return; + } + + #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + DbgPrint("-----zfSetPowerCalTable : frequency=%d-----\n", frequency); + #endif + /* TODO : 1. boundary1 and powerTxMax should be refered to CR667 and CR79 */ + /* in otus.ini file */ + + #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + /* 2. Interpolate pwr and vpd test points from frequency */ + DbgPrint("calFreqPier5G : %d, %d, %d, %d ,%d, %d, %d, %d\n", + eepromImage->calFreqPier5G[0]*5+4800, + eepromImage->calFreqPier5G[1]*5+4800, + eepromImage->calFreqPier5G[2]*5+4800, + eepromImage->calFreqPier5G[3]*5+4800, + eepromImage->calFreqPier5G[4]*5+4800, + eepromImage->calFreqPier5G[5]*5+4800, + eepromImage->calFreqPier5G[6]*5+4800, + eepromImage->calFreqPier5G[7]*5+4800 + ); + DbgPrint("calFreqPier2G : %d, %d, %d, %d\n", + eepromImage->calFreqPier2G[0]+2300, + eepromImage->calFreqPier2G[1]+2300, + eepromImage->calFreqPier2G[2]+2300, + eepromImage->calFreqPier2G[3]+2300 + ); + #endif + if (frequency < 3000) + { + for (i=0; i<4; i++) + { + if (eepromImage->calFreqPier2G[i] == 0xff) + { + break; + } + } + max2gIndex = i; + #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + DbgPrint("max2gIndex : %d\n", max2gIndex); + #endif + fbin = (u8_t)(frequency - 2300); + index = zfFindFreqIndex(fbin, eepromImage->calFreqPier2G, max2gIndex); + #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + DbgPrint("2G index : %d\n", index); + DbgPrint("chain 0 index\n"); + #endif + zfPrintTp(&eepromImage->calPierData2G[0][index].pwrPdg[0][0], + &eepromImage->calPierData2G[0][index].vpdPdg[0][0], + &eepromImage->calPierData2G[0][index].pwrPdg[1][0], + &eepromImage->calPierData2G[0][index].vpdPdg[1][0] + ); + #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + DbgPrint("chain 0 index+1\n"); + #endif + zfPrintTp(&eepromImage->calPierData2G[0][index+1].pwrPdg[0][0], + &eepromImage->calPierData2G[0][index+1].vpdPdg[0][0], + &eepromImage->calPierData2G[0][index+1].pwrPdg[1][0], + &eepromImage->calPierData2G[0][index+1].vpdPdg[1][0] + ); + + for (i=0; i<5; i++) + { + chain0pwrPdg0[i] = zfInterpolateFuncX(fbin, + eepromImage->calFreqPier2G[index], + eepromImage->calPierData2G[0][index].pwrPdg[0][i], + eepromImage->calFreqPier2G[index+1], + eepromImage->calPierData2G[0][index+1].pwrPdg[0][i] + ); + chain0vpdPdg0[i] = zfInterpolateFuncX(fbin, + eepromImage->calFreqPier2G[index], + eepromImage->calPierData2G[0][index].vpdPdg[0][i], + eepromImage->calFreqPier2G[index+1], + eepromImage->calPierData2G[0][index+1].vpdPdg[0][i] + ); + chain0pwrPdg1[i] = zfInterpolateFuncX(fbin, + eepromImage->calFreqPier2G[index], + eepromImage->calPierData2G[0][index].pwrPdg[1][i], + eepromImage->calFreqPier2G[index+1], + eepromImage->calPierData2G[0][index+1].pwrPdg[1][i] + ); + chain0vpdPdg1[i] = zfInterpolateFuncX(fbin, + eepromImage->calFreqPier2G[index], + eepromImage->calPierData2G[0][index].vpdPdg[1][i], + eepromImage->calFreqPier2G[index+1], + eepromImage->calPierData2G[0][index+1].vpdPdg[1][i] + ); + + chain2pwrPdg0[i] = zfInterpolateFuncX(fbin, + eepromImage->calFreqPier2G[index], + eepromImage->calPierData2G[1][index].pwrPdg[0][i], + eepromImage->calFreqPier2G[index+1], + eepromImage->calPierData2G[1][index+1].pwrPdg[0][i] + ); + chain2vpdPdg0[i] = zfInterpolateFuncX(fbin, + eepromImage->calFreqPier2G[index], + eepromImage->calPierData2G[1][index].vpdPdg[0][i], + eepromImage->calFreqPier2G[index+1], + eepromImage->calPierData2G[1][index+1].vpdPdg[0][i] + ); + chain2pwrPdg1[i] = zfInterpolateFuncX(fbin, + eepromImage->calFreqPier2G[index], + eepromImage->calPierData2G[1][index].pwrPdg[1][i], + eepromImage->calFreqPier2G[index+1], + eepromImage->calPierData2G[1][index+1].pwrPdg[1][i] + ); + chain2vpdPdg1[i] = zfInterpolateFuncX(fbin, + eepromImage->calFreqPier2G[index], + eepromImage->calPierData2G[1][index].vpdPdg[1][i], + eepromImage->calFreqPier2G[index+1], + eepromImage->calPierData2G[1][index+1].vpdPdg[1][i] + ); + } + } + else + { + for (i=0; i<8; i++) + { + if (eepromImage->calFreqPier5G[i] == 0xff) + { + break; + } + } + max5gIndex = i; + #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + DbgPrint("max5gIndex : %d\n", max5gIndex); + #endif + fbin = (u8_t)((frequency - 4800)/5); + index = zfFindFreqIndex(fbin, eepromImage->calFreqPier5G, max5gIndex); + #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + DbgPrint("5G index : %d\n", index); + #endif + + for (i=0; i<5; i++) + { + chain0pwrPdg0[i] = zfInterpolateFuncX(fbin, + eepromImage->calFreqPier5G[index], + eepromImage->calPierData5G[0][index].pwrPdg[0][i], + eepromImage->calFreqPier5G[index+1], + eepromImage->calPierData5G[0][index+1].pwrPdg[0][i] + ); + chain0vpdPdg0[i] = zfInterpolateFuncX(fbin, + eepromImage->calFreqPier5G[index], + eepromImage->calPierData5G[0][index].vpdPdg[0][i], + eepromImage->calFreqPier5G[index+1], + eepromImage->calPierData5G[0][index+1].vpdPdg[0][i] + ); + chain0pwrPdg1[i] = zfInterpolateFuncX(fbin, + eepromImage->calFreqPier5G[index], + eepromImage->calPierData5G[0][index].pwrPdg[1][i], + eepromImage->calFreqPier5G[index+1], + eepromImage->calPierData5G[0][index+1].pwrPdg[1][i] + ); + chain0vpdPdg1[i] = zfInterpolateFuncX(fbin, + eepromImage->calFreqPier5G[index], + eepromImage->calPierData5G[0][index].vpdPdg[1][i], + eepromImage->calFreqPier5G[index+1], + eepromImage->calPierData5G[0][index+1].vpdPdg[1][i] + ); + + chain2pwrPdg0[i] = zfInterpolateFuncX(fbin, + eepromImage->calFreqPier5G[index], + eepromImage->calPierData5G[1][index].pwrPdg[0][i], + eepromImage->calFreqPier5G[index+1], + eepromImage->calPierData5G[1][index+1].pwrPdg[0][i] + ); + chain2vpdPdg0[i] = zfInterpolateFuncX(fbin, + eepromImage->calFreqPier5G[index], + eepromImage->calPierData5G[1][index].vpdPdg[0][i], + eepromImage->calFreqPier5G[index+1], + eepromImage->calPierData5G[1][index+1].vpdPdg[0][i] + ); + chain2pwrPdg1[i] = zfInterpolateFuncX(fbin, + eepromImage->calFreqPier5G[index], + eepromImage->calPierData5G[1][index].pwrPdg[1][i], + eepromImage->calFreqPier5G[index+1], + eepromImage->calPierData5G[1][index+1].pwrPdg[1][i] + ); + chain2vpdPdg1[i] = zfInterpolateFuncX(fbin, + eepromImage->calFreqPier5G[index], + eepromImage->calPierData5G[1][index].vpdPdg[1][i], + eepromImage->calFreqPier5G[index+1], + eepromImage->calPierData5G[1][index+1].vpdPdg[1][i] + ); + } + + } + + + /* Chain 1 */ + /* Get pwr and vpd test points from frequency */ + for (i=0; i<5; i++) + { + pwr0[i] = chain0pwrPdg0[i]>>1; + vpd0[i] = chain0vpdPdg0[i]; + pwr1[i] = chain0pwrPdg1[i]>>1; + vpd1[i] = chain0vpdPdg1[i]; + } + #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + DbgPrint("Test Points\n"); + DbgPrint("pwr0 : %d, %d, %d, %d ,%d\n", pwr0[0], pwr0[1], pwr0[2], pwr0[3], pwr0[4]); + DbgPrint("vpd0 : %d, %d, %d, %d ,%d\n", vpd0[0], vpd0[1], vpd0[2], vpd0[3], vpd0[4]); + DbgPrint("pwr1 : %d, %d, %d, %d ,%d\n", pwr1[0], pwr1[1], pwr1[2], pwr1[3], pwr1[4]); + DbgPrint("vpd1 : %d, %d, %d, %d ,%d\n", vpd1[0], vpd1[1], vpd1[2], vpd1[3], vpd1[4]); + #endif + /* Generate the vpd arrays */ + for (i=0; i<boundary1+1+6; i++) + { + vpd_chain1[i] = zfGetInterpolatedValue(i, &pwr0[0], &vpd0[0]); + } + for (; i<powerTxMax+1+6+6; i++) + { + vpd_chain1[i] = zfGetInterpolatedValue(i-6-6, &pwr1[0], &vpd1[0]); + } + #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + DbgPrint("vpd_chain1\n"); + for (i=0; i<powerTxMax+1+6+6; i+=10) + { + DbgPrint("%d, %d, %d, %d ,%d, %d, %d, %d, %d, %d\n", + vpd_chain1[i+0], vpd_chain1[i+1], vpd_chain1[i+2], vpd_chain1[i+3], vpd_chain1[i+4], + vpd_chain1[i+5], vpd_chain1[i+6], vpd_chain1[i+7], vpd_chain1[i+8], vpd_chain1[i+9]); + } + #endif + /* Write PHY regs 672-703 */ + for (i=0; i<128; i+=4) + { + u32_t regAddr = 0x9800 + (672 * 4); + u32_t val; + + val = ((u32_t)vpd_chain1[i+3]<<24) | + ((u32_t)vpd_chain1[i+2]<<16) | + ((u32_t)vpd_chain1[i+1]<<8) | + ((u32_t)vpd_chain1[i]); + + #ifndef ZM_OTUS_LINUX_PHASE_2 + reg_write(regAddr + i, val); /* CR672 */ + #endif + } + + /* Chain 2 */ + /* Get pwr and vpd test points from frequency */ + for (i=0; i<5; i++) + { + pwr0[i] = chain2pwrPdg0[i]>>1; + vpd0[i] = chain2vpdPdg0[i]; + pwr1[i] = chain2pwrPdg1[i]>>1; + vpd1[i] = chain2vpdPdg1[i]; + } + #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + DbgPrint("Test Points\n"); + DbgPrint("pwr0 : %d, %d, %d, %d ,%d\n", pwr0[0], pwr0[1], pwr0[2], pwr0[3], pwr0[4]); + DbgPrint("vpd0 : %d, %d, %d, %d ,%d\n", vpd0[0], vpd0[1], vpd0[2], vpd0[3], vpd0[4]); + DbgPrint("pwr1 : %d, %d, %d, %d ,%d\n", pwr1[0], pwr1[1], pwr1[2], pwr1[3], pwr1[4]); + DbgPrint("vpd1 : %d, %d, %d, %d ,%d\n", vpd1[0], vpd1[1], vpd1[2], vpd1[3], vpd1[4]); + #endif + /* Generate the vpd arrays */ + for (i=0; i<boundary1+1+6; i++) + { + vpd_chain3[i] = zfGetInterpolatedValue(i, &pwr0[0], &vpd0[0]); + } + for (; i<powerTxMax+1+6+6; i++) + { + vpd_chain3[i] = zfGetInterpolatedValue(i-6-6, &pwr1[0], &vpd1[0]); + } + #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + DbgPrint("vpd_chain3\n"); + for (i=0; i<powerTxMax+1+6+6; i+=10) + { + DbgPrint("%d, %d, %d, %d ,%d, %d, %d, %d, %d, %d\n", + vpd_chain3[i+0], vpd_chain3[i+1], vpd_chain3[i+2], vpd_chain3[i+3], vpd_chain3[i+4], + vpd_chain3[i+5], vpd_chain3[i+6], vpd_chain3[i+7], vpd_chain3[i+8], vpd_chain3[i+9]); + } + #endif + + /* Write PHY regs 672-703 + 0x1000 */ + for (i=0; i<128; i+=4) + { + u32_t regAddr = 0x9800 + (672 * 4) + 0x1000; + u32_t val; + + val = ((u32_t)vpd_chain3[i+3]<<24) | + ((u32_t)vpd_chain3[i+2]<<16) | + ((u32_t)vpd_chain3[i+1]<<8) | + ((u32_t)vpd_chain3[i]); + + #ifndef ZM_OTUS_LINUX_PHASE_2 + reg_write(regAddr + i, val); /* CR672 */ + #endif + } + + zfFlushDelayWrite(dev); + + /* 3. Generate target power table */ + if (frequency < 3000) + { + for (i=0; i<3; i++) + { + if (eepromImage->calTargetPowerCck[i].bChannel != 0xff) + { + fbinArray[i] = eepromImage->calTargetPowerCck[i].bChannel; + } + else + { + break; + } + + } + index = zfFindFreqIndex(fbin, fbinArray, i); + #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + DbgPrint("CCK index=%d\n", index); + #endif + for (i=0; i<4; i++) + { + hpPriv->tPow2xCck[i] = zfInterpolateFuncX(fbin, + eepromImage->calTargetPowerCck[index].bChannel, + eepromImage->calTargetPowerCck[index].tPow2x[i], + eepromImage->calTargetPowerCck[index+1].bChannel, + eepromImage->calTargetPowerCck[index+1].tPow2x[i] + ); + } + + for (i=0; i<4; i++) + { + if (eepromImage->calTargetPower2G[i].bChannel != 0xff) + { + fbinArray[i] = eepromImage->calTargetPower2G[i].bChannel; + } + else + { + break; + } + + } + index = zfFindFreqIndex(fbin, fbinArray, i); + #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + DbgPrint("2G index=%d\n", index); + #endif + for (i=0; i<4; i++) + { + hpPriv->tPow2x2g[i] = zfInterpolateFuncX(fbin, + eepromImage->calTargetPower2G[index].bChannel, + eepromImage->calTargetPower2G[index].tPow2x[i], + eepromImage->calTargetPower2G[index+1].bChannel, + eepromImage->calTargetPower2G[index+1].tPow2x[i] + ); + } + + for (i=0; i<4; i++) + { + if (eepromImage->calTargetPower2GHT20[i].bChannel != 0xff) + { + fbinArray[i] = eepromImage->calTargetPower2GHT20[i].bChannel; + } + else + { + break; + } + + } + index = zfFindFreqIndex(fbin, fbinArray, i); + #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + DbgPrint("2G HT20 index=%d\n", index); + #endif + for (i=0; i<8; i++) + { + hpPriv->tPow2x2gHt20[i] = zfInterpolateFuncX(fbin, + eepromImage->calTargetPower2GHT20[index].bChannel, + eepromImage->calTargetPower2GHT20[index].tPow2x[i], + eepromImage->calTargetPower2GHT20[index+1].bChannel, + eepromImage->calTargetPower2GHT20[index+1].tPow2x[i] + ); + } + + for (i=0; i<4; i++) + { + if (eepromImage->calTargetPower2GHT40[i].bChannel != 0xff) + { + fbinArray[i] = eepromImage->calTargetPower2GHT40[i].bChannel; + } + else + { + break; + } + + } + index = zfFindFreqIndex( (u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset), fbinArray, i); + #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + DbgPrint("2G HT40 index=%d\n", index); + #endif + for (i=0; i<8; i++) + { + hpPriv->tPow2x2gHt40[i] = zfInterpolateFuncX( + (u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset), + eepromImage->calTargetPower2GHT40[index].bChannel, + eepromImage->calTargetPower2GHT40[index].tPow2x[i], + eepromImage->calTargetPower2GHT40[index+1].bChannel, + eepromImage->calTargetPower2GHT40[index+1].tPow2x[i] + ); + } + + zfPrintTargetPower2G(hpPriv->tPow2xCck, + hpPriv->tPow2x2g, + hpPriv->tPow2x2gHt20, + hpPriv->tPow2x2gHt40); + } + else + { + /* 5G */ + for (i=0; i<8; i++) + { + if (eepromImage->calTargetPower5G[i].bChannel != 0xff) + { + fbinArray[i] = eepromImage->calTargetPower5G[i].bChannel; + } + else + { + break; + } + + } + index = zfFindFreqIndex(fbin, fbinArray, i); + #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + DbgPrint("5G index=%d\n", index); + #endif + for (i=0; i<4; i++) + { + hpPriv->tPow2x5g[i] = zfInterpolateFuncX(fbin, + eepromImage->calTargetPower5G[index].bChannel, + eepromImage->calTargetPower5G[index].tPow2x[i], + eepromImage->calTargetPower5G[index+1].bChannel, + eepromImage->calTargetPower5G[index+1].tPow2x[i] + ); + } + + for (i=0; i<8; i++) + { + if (eepromImage->calTargetPower5GHT20[i].bChannel != 0xff) + { + fbinArray[i] = eepromImage->calTargetPower5GHT20[i].bChannel; + } + else + { + break; + } + + } + index = zfFindFreqIndex(fbin, fbinArray, i); + #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + DbgPrint("5G HT20 index=%d\n", index); + #endif + for (i=0; i<8; i++) + { + hpPriv->tPow2x5gHt20[i] = zfInterpolateFuncX(fbin, + eepromImage->calTargetPower5GHT20[index].bChannel, + eepromImage->calTargetPower5GHT20[index].tPow2x[i], + eepromImage->calTargetPower5GHT20[index+1].bChannel, + eepromImage->calTargetPower5GHT20[index+1].tPow2x[i] + ); + } + + for (i=0; i<8; i++) + { + if (eepromImage->calTargetPower5GHT40[i].bChannel != 0xff) + { + fbinArray[i] = eepromImage->calTargetPower5GHT40[i].bChannel; + } + else + { + break; + } + + } + index = zfFindFreqIndex((u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset), fbinArray, i); + #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + DbgPrint("5G HT40 index=%d\n", index); + #endif + for (i=0; i<8; i++) + { + hpPriv->tPow2x5gHt40[i] = zfInterpolateFuncX( + (u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset), + eepromImage->calTargetPower5GHT40[index].bChannel, + eepromImage->calTargetPower5GHT40[index].tPow2x[i], + eepromImage->calTargetPower5GHT40[index+1].bChannel, + eepromImage->calTargetPower5GHT40[index+1].tPow2x[i] + ); + } + + zfPrintTargetPower5G( + hpPriv->tPow2x5g, + hpPriv->tPow2x5gHt20, + hpPriv->tPow2x5gHt40); + } + + + + /* 4. CTL */ + /* + * 4.1 Get the bandedges tx power by frequency + * 2.4G we get ctlEdgesMaxPowerCCK + * ctlEdgesMaxPower2G + * ctlEdgesMaxPower2GHT20 + * ctlEdgesMaxPower2GHT40 + * 5G we get ctlEdgesMaxPower5G + * ctlEdgesMaxPower5GHT20 + * ctlEdgesMaxPower5GHT40 + * 4.2 Update (3.) target power table by 4.1 + * 4.3 Tx power offset for ART - NDIS/MDK + * 4.4 Write MAC reg 0x694 for ACK's TPC + * + */ + + //zfDumpEepBandEdges(eepromImage); + + /* get the cfg from Eeprom: regionCode => RegulatoryDomain : 0x10-FFC 0x30-eu 0x40-jap */ + desired_CtlIndex = zfHpGetRegulatoryDomain(dev); + if ((desired_CtlIndex == 0x30) || (desired_CtlIndex == 0x40) || (desired_CtlIndex == 0x0)) + { + /* skip CTL and heavy clip */ + hpPriv->enableBBHeavyClip = 0; + #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG + zm_dbg(("RegulatoryDomain = 0, skip CTL and heavy clip\n")); + #endif + } + else + { + hpPriv->enableBBHeavyClip = 1; + + if (desired_CtlIndex == 0xff) + { + /* desired index not found */ + desired_CtlIndex = 0x10; + } + + /* first part : 2.4G */ + if (frequency <= ZM_CH_G_14) + { + /* 2.4G - CTL_11B */ + ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11B); + if(ctl_i<AR5416_NUM_CTLS) + { + ctlEdgesMaxPowerCCK = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency); + } + #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG + zm_dbg(("CTL_11B ctl_i = %d\n", ctl_i)); + #endif + + /* 2.4G - CTL_11G */ + ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11G); + if(ctl_i<AR5416_NUM_CTLS) + { + ctlEdgesMaxPower2G = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency); + } + #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG + zm_dbg(("CTL_11G ctl_i = %d\n", ctl_i)); + #endif + + /* 2.4G - CTL_2GHT20 */ + ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_2GHT20); + if(ctl_i<AR5416_NUM_CTLS) + { + ctlEdgesMaxPower2GHT20 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency); + } + else + { + /* workaround for no data in Eeprom, replace by normal 2G */ + ctlEdgesMaxPower2GHT20 = ctlEdgesMaxPower2G; + } + #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG + zm_dbg(("CTL_2GHT20 ctl_i = %d\n", ctl_i)); + #endif + + /* 2.4G - CTL_2GHT40 */ + ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_2GHT40); + if(ctl_i<AR5416_NUM_CTLS) + { + ctlEdgesMaxPower2GHT40 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], + zfAdjustHT40FreqOffset(dev, frequency, bw40, extOffset)); + } + else + { + /* workaround for no data in Eeprom, replace by normal 2G */ + ctlEdgesMaxPower2GHT40 = ctlEdgesMaxPower2G; + } + #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG + zm_dbg(("CTL_2GHT40 ctl_i = %d\n", ctl_i)); + #endif + + + /* 7a17 : */ + /* Max power (dBm) for channel range when using DFS define by madwifi*/ + for (i=0; i<wd->regulationTable.allowChannelCnt; i++) + { + if (wd->regulationTable.allowChannel[i].channel == frequency) + { + if (zfHpIsDfsChannel(dev, (u16_t)frequency)) + { + zm_debug_msg1("frequency use DFS -- ", frequency); + ctlEdgesMaxPowerCCK = zm_min(ctlEdgesMaxPowerCCK, wd->regulationTable.allowChannel[i].maxRegTxPower*2); + ctlEdgesMaxPower2G = zm_min(ctlEdgesMaxPower2G, wd->regulationTable.allowChannel[i].maxRegTxPower*2); + ctlEdgesMaxPower2GHT20 = zm_min(ctlEdgesMaxPower2GHT20, wd->regulationTable.allowChannel[i].maxRegTxPower*2); + ctlEdgesMaxPower2GHT40 = zm_min(ctlEdgesMaxPower2GHT40, wd->regulationTable.allowChannel[i].maxRegTxPower*2); + } + break; + } + } + + /* Apply ctl mode to correct target power set */ + #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG + zm_debug_msg1("ctlEdgesMaxPowerCCK = ", ctlEdgesMaxPowerCCK); + zm_debug_msg1("ctlEdgesMaxPower2G = ", ctlEdgesMaxPower2G); + zm_debug_msg1("ctlEdgesMaxPower2GHT20 = ", ctlEdgesMaxPower2GHT20); + zm_debug_msg1("ctlEdgesMaxPower2GHT40 = ", ctlEdgesMaxPower2GHT40); + #endif + for (i=0; i<4; i++) + { + hpPriv->tPow2xCck[i] = zm_min(hpPriv->tPow2xCck[i], ctlEdgesMaxPowerCCK) + HALTX_POWER_OFFSET; + } + hpPriv->tPow2x2g24HeavyClipOffset = 0; + if (hpPriv->enableBBHeavyClip) + { + ctlOffset = 2; + } + else + { + ctlOffset = 0; + } + for (i=0; i<4; i++) + { + if (((frequency == 2412) || (frequency == 2462))) + { + if (i != 0) + { + hpPriv->tPow2x2g[i] = zm_min(hpPriv->tPow2x2g[i], ctlEdgesMaxPower2G-ctlOffset) + HALTX_POWER_OFFSET; + } + else + { + hpPriv->tPow2x2g[i] = zm_min(hpPriv->tPow2x2g[i], ctlEdgesMaxPower2G) + HALTX_POWER_OFFSET; + if (hpPriv->tPow2x2g[i] > (ctlEdgesMaxPower2G-ctlOffset)) + { + hpPriv->tPow2x2g24HeavyClipOffset = hpPriv->tPow2x2g[i] - (ctlEdgesMaxPower2G-ctlOffset); + } + } + } + else + { + hpPriv->tPow2x2g[i] = zm_min(hpPriv->tPow2x2g[i], ctlEdgesMaxPower2G) + HALTX_POWER_OFFSET; + } + } + for (i=0; i<8; i++) + { + if (((frequency == 2412) || (frequency == 2462)) && (i>=3)) + { + hpPriv->tPow2x2gHt20[i] = zm_min(hpPriv->tPow2x2gHt20[i], ctlEdgesMaxPower2GHT20-ctlOffset) + HALTX_POWER_OFFSET; + } + else + { + hpPriv->tPow2x2gHt20[i] = zm_min(hpPriv->tPow2x2gHt20[i], ctlEdgesMaxPower2GHT20) + HALTX_POWER_OFFSET; + } + } + for (i=0; i<8; i++) + { + if ((frequency == 2412) && (i>=3)) + { + hpPriv->tPow2x2gHt40[i] = zm_min(hpPriv->tPow2x2gHt40[i], ctlEdgesMaxPower2GHT40-ctlOffset) + HALTX_POWER_OFFSET; + } + else if ((frequency == 2462) && (i>=3)) + { + hpPriv->tPow2x2gHt40[i] = zm_min(hpPriv->tPow2x2gHt40[i], ctlEdgesMaxPower2GHT40-(ctlOffset*2)) + HALTX_POWER_OFFSET; + } + else + { + hpPriv->tPow2x2gHt40[i] = zm_min(hpPriv->tPow2x2gHt40[i], ctlEdgesMaxPower2GHT40) + HALTX_POWER_OFFSET; + } + } + } + else + { + /* 5G - CTL_11A */ + ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11A); + if(ctl_i<AR5416_NUM_CTLS) + { + ctlEdgesMaxPower5G = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency); + } + #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG + zm_dbg(("CTL_11A ctl_i = %d\n", ctl_i)); + #endif + + /* 5G - CTL_5GHT20 */ + ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_5GHT20); + if(ctl_i<AR5416_NUM_CTLS) + { + ctlEdgesMaxPower5GHT20 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency); + } + else + { + /* workaround for no data in Eeprom, replace by normal 5G */ + ctlEdgesMaxPower5GHT20 = ctlEdgesMaxPower5G; + } + #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG + zm_dbg(("CTL_5GHT20 ctl_i = %d\n", ctl_i)); + #endif + + /* 5G - CTL_5GHT40 */ + ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_5GHT40); + if(ctl_i<AR5416_NUM_CTLS) + { + ctlEdgesMaxPower5GHT40 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], + zfAdjustHT40FreqOffset(dev, frequency, bw40, extOffset)); + } + else + { + /* workaround for no data in Eeprom, replace by normal 5G */ + ctlEdgesMaxPower5GHT40 = ctlEdgesMaxPower5G; + } + #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG + zm_dbg(("CTL_5GHT40 ctl_i = %d\n", ctl_i)); + #endif + + /* 7a17 : */ + /* Max power (dBm) for channel range when using DFS define by madwifi*/ + for (i=0; i<wd->regulationTable.allowChannelCnt; i++) + { + if (wd->regulationTable.allowChannel[i].channel == frequency) + { + if (zfHpIsDfsChannel(dev, (u16_t)frequency)) + { + zm_debug_msg1("frequency use DFS -- ", frequency); + ctlEdgesMaxPower5G = zm_min(ctlEdgesMaxPower5G, wd->regulationTable.allowChannel[i].maxRegTxPower*2); + ctlEdgesMaxPower5GHT20 = zm_min(ctlEdgesMaxPower5GHT20, wd->regulationTable.allowChannel[i].maxRegTxPower*2); + ctlEdgesMaxPower5GHT40 = zm_min(ctlEdgesMaxPower5GHT40, wd->regulationTable.allowChannel[i].maxRegTxPower*2); + } + break; + } + } + + + /* Apply ctl mode to correct target power set */ + #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG + zm_debug_msg1("ctlEdgesMaxPower5G = ", ctlEdgesMaxPower5G); + zm_debug_msg1("ctlEdgesMaxPower5GHT20 = ", ctlEdgesMaxPower5GHT20); + zm_debug_msg1("ctlEdgesMaxPower5GHT40 = ", ctlEdgesMaxPower5GHT40); + #endif + for (i=0; i<4; i++) + { + hpPriv->tPow2x5g[i] = zm_min(hpPriv->tPow2x5g[i], ctlEdgesMaxPower5G) + HALTX_POWER_OFFSET; + } + for (i=0; i<8; i++) + { + hpPriv->tPow2x5gHt20[i] = zm_min(hpPriv->tPow2x5gHt20[i], ctlEdgesMaxPower5GHT20) + HALTX_POWER_OFFSET; + } + for (i=0; i<8; i++) + { + hpPriv->tPow2x5gHt40[i] = zm_min(hpPriv->tPow2x5gHt40[i], ctlEdgesMaxPower5GHT40) + HALTX_POWER_OFFSET; + } + + }/* end of bandedges of 5G */ + }/* end of if ((desired_CtlIndex = zfHpGetRegulatoryDomain(dev)) == 0) */ + + /* workaround */ + /* 5. BB heavy clip */ + /* only 2.4G do heavy clip */ + if (hpPriv->enableBBHeavyClip && hpPriv->hwBBHeavyClip && (frequency <= ZM_CH_G_14)) + { + if (frequency <= ZM_CH_G_14) + { + ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11G); + } + else + { + ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11A); + } + + hpPriv->setValueHeavyClip = zfHpCheckDoHeavyClip(dev, frequency, eepromImage->ctlData[ctl_i].ctlEdges[1], bw40); + + if (hpPriv->setValueHeavyClip) + { + hpPriv->doBBHeavyClip = 1; + } + else + { + hpPriv->doBBHeavyClip = 0; + } + #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG + zm_dbg(("zfHpCheckDoHeavyClip ret = %02x, doBBHeavyClip = %d\n", + hpPriv->setValueHeavyClip, hpPriv->doBBHeavyClip)); + #endif + + if (hpPriv->doBBHeavyClip) + { + if (hpPriv->setValueHeavyClip & 0xf0) + { + hpPriv->tPow2x2gHt40[0] -= 1; + hpPriv->tPow2x2gHt40[1] -= 1; + hpPriv->tPow2x2gHt40[2] -= 1; + } + + if (hpPriv->setValueHeavyClip & 0xf) + { + hpPriv->tPow2x2gHt20[0] += 1; + hpPriv->tPow2x2gHt20[1] += 1; + hpPriv->tPow2x2gHt20[2] += 1; + } + } + } + else + { + hpPriv->doBBHeavyClip = 0; + hpPriv->setValueHeavyClip = 0; + } + + /* Final : write MAC register for some ctrl frame Tx power */ + /* first part : 2.4G */ + if (frequency <= ZM_CH_G_14) + { + /* Write MAC reg 0x694 for ACK's TPC */ + /* Write MAC reg 0xbb4 RTS and SF-CTS frame power control */ + /* Always use two stream for low legacy rate */ + #if 0 + //if (hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM) + //{ + zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x2g[0]&0x3f) << 20) | (0x1<<26)); + zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x2g[0]&0x3f) << 5 ) | (0x1<<11) | + ((hpPriv->tPow2x2g[0]&0x3f) << 21) | (0x1<<27) ); + //} + #endif + #if 1 + //else + { + #ifndef ZM_OTUS_LINUX_PHASE_2 + zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x2g[0]&0x3f) << 20) | (0x5<<26)); + zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x2g[0]&0x3f) << 5 ) | (0x5<<11) | + ((hpPriv->tPow2x2g[0]&0x3f) << 21) | (0x5<<27) ); + #endif + hpPriv->currentAckRtsTpc = hpPriv->tPow2x2g[0]; + } + #endif + zfFlushDelayWrite(dev); + + zfPrintTargetPower2G(hpPriv->tPow2xCck, + hpPriv->tPow2x2g, + hpPriv->tPow2x2gHt20, + hpPriv->tPow2x2gHt40); + } + else + { + /* Write MAC reg 0x694 for ACK's TPC */ + /* Write MAC reg 0xbb4 RTS and SF-CTS frame power control */ + /* Always use two stream for low legacy rate */ + if (hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM) + { + #ifndef ZM_OTUS_LINUX_PHASE_2 + zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x5g[0]&0x3f) << 20) | (0x1<<26)); + zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x5g[0]&0x3f) << 5 ) | (0x1<<11) | + ((hpPriv->tPow2x5g[0]&0x3f) << 21) | (0x1<<27) ); + #endif + } + else + { + #ifndef ZM_OTUS_LINUX_PHASE_2 + zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x5g[0]&0x3f) << 20) | (0x5<<26)); + zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x5g[0]&0x3f) << 5 ) | (0x5<<11) | + ((hpPriv->tPow2x5g[0]&0x3f) << 21) | (0x5<<27) ); + #endif + hpPriv->currentAckRtsTpc = hpPriv->tPow2x2g[0]; + } + + + zfFlushDelayWrite(dev); + + zfPrintTargetPower5G( + hpPriv->tPow2x5g, + hpPriv->tPow2x5gHt20, + hpPriv->tPow2x5gHt40); + }/* end of bandedges of 5G */ + +} + +void zfDumpEepBandEdges(struct ar5416Eeprom* eepromImage) +{ + #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG + u8_t i, j, k; + +#if 0 + zm_dbg(("\n === BandEdges index dump ==== \n")); + + for (i = 0; i < AR5416_NUM_CTLS; i++) + { + zm_dbg(("%02x ", eepromImage->ctlIndex[i])); + } + + zm_dbg(("\n === BandEdges data dump ==== \n")); + + for (i = 0; i < AR5416_NUM_CTLS; i++) + { + for (j = 0; j < 2; j++) + { + for(k = 0; k < AR5416_NUM_BAND_EDGES; k++) + { + u8_t *pdata = (u8_t*)&(eepromImage->ctlData[i].ctlEdges[j][k]); + zm_dbg(("(%02x %02x)", pdata[0], pdata[1])); + } + zm_dbg(("\n")); + } + } +#else + zm_dbg(("\n === BandEdges index dump ==== \n")); + for (i = 0; i < 24; i+=8) + { + zm_dbg(("%02x %02x %02x %02x %02x %02x %02x %02x", + eepromImage->ctlIndex[i+0], eepromImage->ctlIndex[i+1], eepromImage->ctlIndex[i+2], eepromImage->ctlIndex[i+3], + eepromImage->ctlIndex[i+4], eepromImage->ctlIndex[i+5], eepromImage->ctlIndex[i+6], eepromImage->ctlIndex[i+7] + )); + } + + zm_dbg(("\n === BandEdges data dump ==== \n")); + + for (i = 0; i < AR5416_NUM_CTLS; i++) + { + for (j = 0; j < 2; j++) + { + u8_t *pdata = (u8_t*)&(eepromImage->ctlData[i].ctlEdges[j]); + zm_dbg(("(%03d %02x) (%03d %02x) (%03d %02x) (%03d %02x) \n", + pdata[0], pdata[1], pdata[2], pdata[3], + pdata[4], pdata[5], pdata[6], pdata[7] + )); + zm_dbg(("(%03d %02x) (%03d %02x) (%03d %02x) (%03d %02x) \n", + pdata[8], pdata[9], pdata[10], pdata[11], + pdata[12], pdata[13], pdata[14], pdata[15] + )); + } + } +#endif + #endif +} + +void zfPrintTargetPower2G(u8_t* tPow2xCck, u8_t* tPow2x2g, u8_t* tPow2x2gHt20, u8_t* tPow2x2gHt40) +{ + //#ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG + DbgPrint("targetPwr CCK : %d, %d, %d, %d\n", + tPow2xCck[0], + tPow2xCck[1], + tPow2xCck[2], + tPow2xCck[3] + ); + DbgPrint("targetPwr 2G : %d, %d, %d, %d\n", + tPow2x2g[0], + tPow2x2g[1], + tPow2x2g[2], + tPow2x2g[3] + ); + DbgPrint("targetPwr 2GHT20 : %d, %d, %d, %d, %d, %d, %d, %d\n", + tPow2x2gHt20[0], + tPow2x2gHt20[1], + tPow2x2gHt20[2], + tPow2x2gHt20[3], + tPow2x2gHt20[4], + tPow2x2gHt20[5], + tPow2x2gHt20[6], + tPow2x2gHt20[7] + ); + DbgPrint("targetPwr 2GHT40 : %d, %d, %d, %d, %d, %d, %d, %d\n", + tPow2x2gHt40[0], + tPow2x2gHt40[1], + tPow2x2gHt40[2], + tPow2x2gHt40[3], + tPow2x2gHt40[4], + tPow2x2gHt40[5], + tPow2x2gHt40[6], + tPow2x2gHt40[7] + ); + #endif + return; +} + +void zfPrintTargetPower5G(u8_t* tPow2x5g, u8_t* tPow2x5gHt20, u8_t* tPow2x5gHt40) +{ + //#ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG + #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG + DbgPrint("targetPwr 5G : %d, %d, %d, %d\n", + tPow2x5g[0], + tPow2x5g[1], + tPow2x5g[2], + tPow2x5g[3] + ); + DbgPrint("targetPwr 5GHT20 : %d, %d, %d, %d, %d, %d, %d, %d\n", + tPow2x5gHt20[0], + tPow2x5gHt20[1], + tPow2x5gHt20[2], + tPow2x5gHt20[3], + tPow2x5gHt20[4], + tPow2x5gHt20[5], + tPow2x5gHt20[6], + tPow2x5gHt20[7] + ); + DbgPrint("targetPwr 5GHT40 : %d, %d, %d, %d, %d, %d, %d, %d\n", + tPow2x5gHt40[0], + tPow2x5gHt40[1], + tPow2x5gHt40[2], + tPow2x5gHt40[3], + tPow2x5gHt40[4], + tPow2x5gHt40[5], + tPow2x5gHt40[6], + tPow2x5gHt40[7] + ); + #endif + return; +} + +void zfHpPowerSaveSetMode(zdev_t* dev, u8_t staMode, u8_t psMode, u16_t bcnInterval) +{ + if ( staMode == 0 ) + { + if ( psMode == 0 ) + { + // Turn off pre-TBTT interrupt + zfDelayWriteInternalReg(dev, ZM_MAC_REG_PRETBTT, 0); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, 0); + zfFlushDelayWrite(dev); + } + else + { + // Turn on pre-TBTT interrupt + zfDelayWriteInternalReg(dev, ZM_MAC_REG_PRETBTT, (bcnInterval-6)<<16); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, bcnInterval); + zfFlushDelayWrite(dev); + } + } +} + +void zfHpPowerSaveSetState(zdev_t* dev, u8_t psState) +{ + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv = wd->hpPrivate; + + //DbgPrint("INTO zfHpPowerSaveSetState"); + + if ( psState == 0 ) //power up + { + //DbgPrint("zfHpPowerSaveSetState Wake up from PS\n"); + reg_write(0x982C, 0x0000a000); //wake up ADDAC + reg_write(0x9808, 0x0); //enable all agc gain and offset updates to a2 + //# bank 3 + if (((struct zsHpPriv*)wd->hpPrivate)->hwFrequency <= ZM_CH_G_14) + { + /* 11g */ + //reg_write (0x98f0, 0x01c00018); + reg_write (0x98f0, 0x01c20098);//syn_on+RX_ON + } + else + { + /* 11a */ + //reg_write (0x98f0, 0x01400018); + reg_write (0x98f0, 0x01420098);//syn_on+RX_ON + } + + ////#bank 5 + //reg_write(0x98b0, 0x00000013); + //reg_write(0x98e4, 0x00000002); + + + zfFlushDelayWrite(dev); + } + else //power down + { + //DbgPrint("zfHpPowerSaveSetState Go to PS\n"); + //reg_write(0x982C, 0xa000a000); + reg_write(0x9808, 0x8000000); //disable all agc gain and offset updates to a2 + reg_write(0x982C, 0xa000a000); //power down ADDAC + //# bank 3 + if (((struct zsHpPriv*)wd->hpPrivate)->hwFrequency <= ZM_CH_G_14) + { + /* 11g */ + reg_write (0x98f0, 0x00c00018);//syn_off+RX_off + } + else + { + /* 11a */ + reg_write (0x98f0, 0x00400018);//syn_off+RX_off + } + + ////#bank 5 + //reg_write(0x98b0, 0x000e0013); + //reg_write(0x98e4, 0x00018002); + + + zfFlushDelayWrite(dev); + } +} + +void zfHpSetAggPktNum(zdev_t* dev, u32_t num) +{ + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv = wd->hpPrivate; + + num = (num << 16) | (0xa); + + hpPriv->aggPktNum = num; + + //aggregation number will be update in HAL heart beat + //zfDelayWriteInternalReg(dev, 0x1c3b9c, num); + //zfFlushDelayWrite(dev); +} + +void zfHpSetMPDUDensity(zdev_t* dev, u8_t density) +{ + u32_t value; + + if (density > ZM_MPDU_DENSITY_8US) + { + return; + } + + /* Default value in this register */ + value = 0x140A00 | density; + + zfDelayWriteInternalReg(dev, 0x1c3ba0, value); + zfFlushDelayWrite(dev); + return; +} + +void zfHpSetSlotTime(zdev_t* dev, u8_t type) +{ + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv = wd->hpPrivate; + + if (type == 0) + { + //normal slot = 20us + hpPriv->slotType = 0; + } + else //if (type == 1) + { + //short slot = 9us + hpPriv->slotType = 1; + } + + return; +} + +void zfHpSetSlotTimeRegister(zdev_t* dev, u8_t type) +{ + if(type == 0) + { + //normal slot = 20us + zfDelayWriteInternalReg(dev, ZM_MAC_REG_SLOT_TIME, 20<<10); + } + else + { + //short slot = 9us + zfDelayWriteInternalReg(dev, ZM_MAC_REG_SLOT_TIME, 9<<10); + } +} + +void zfHpSetRifs(zdev_t* dev, u8_t ht_enable, u8_t ht2040, u8_t g_mode) +{ + zfDelayWriteInternalReg(dev, 0x1c6388, 0x0c000000); + + zfDelayWriteInternalReg(dev, 0x1c59ec, 0x0cc80caa); + + if (ht_enable) + { + if (ht2040) + { + zfDelayWriteInternalReg(dev, 0x1c5918, 40); + } + else + { + zfDelayWriteInternalReg(dev, 0x1c5918, 20); + } + } + + if (g_mode) + { + zfDelayWriteInternalReg(dev, 0x1c5850, 0xec08b4e2); + zfDelayWriteInternalReg(dev, 0x1c585c, 0x313a5d5e); + } + else + { + zfDelayWriteInternalReg(dev, 0x1c5850, 0xede8b4e0); + zfDelayWriteInternalReg(dev, 0x1c585c, 0x3139605e); + } + + zfFlushDelayWrite(dev); + return; +} + +void zfHpBeginSiteSurvey(zdev_t* dev, u8_t status) +{ + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv=wd->hpPrivate; + + if ( status == 1 ) + { // Connected + hpPriv->isSiteSurvey = 1; + } + else + { // Not connected + hpPriv->isSiteSurvey = 0; + } + + /* reset workaround state to default */ +// if (hpPriv->rxStrongRSSI == 1) + { + hpPriv->rxStrongRSSI = 0; + if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE + { + if (hpPriv->hwFrequency <= ZM_CH_G_14) + { + zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b49); + } + else + { + zfDelayWriteInternalReg(dev, 0x1c8960, 0x0900); + } + } + else + { + zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b40); + } + zfFlushDelayWrite(dev); + } +// if (hpPriv->strongRSSI == 1) + { + hpPriv->strongRSSI = 0; + zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->currentAckRtsTpc&0x3f) << 20) | (0x5<<26)); + zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->currentAckRtsTpc&0x3f) << 5 ) | (0x5<<11) | + ((hpPriv->currentAckRtsTpc&0x3f) << 21) | (0x5<<27) ); + zfFlushDelayWrite(dev); + } +} + +void zfHpFinishSiteSurvey(zdev_t* dev, u8_t status) +{ + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv=wd->hpPrivate; + + zmw_declare_for_critical_section(); + + zmw_enter_critical_section(dev); + if ( status == 1 ) + { + hpPriv->isSiteSurvey = 2; + } + else + { + hpPriv->isSiteSurvey = 0; + } + zmw_leave_critical_section(dev); +} + +u16_t zfFwRetry(zdev_t* dev, u8_t enable) +{ + u32_t cmd[(ZM_MAX_CMD_SIZE/4)]; + u16_t ret = 0; + + cmd[0] = 4 | (0x92 << 8); + cmd[1] = (enable == 1) ? 0x01 : 0x00; + + ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, NULL); + return ret; +} + +u16_t zfHpEnableHwRetry(zdev_t* dev) +{ + u16_t ret; + + ret = zfFwRetry(dev, 0); + + zfDelayWriteInternalReg(dev, 0x1c3b28, 0x33333); + zfFlushDelayWrite(dev); + + return ret; +} + +u16_t zfHpDisableHwRetry(zdev_t* dev) +{ + u16_t ret; + + ret = zfFwRetry(dev, 1); + + zfDelayWriteInternalReg(dev, 0x1c3b28, 0x00000); + zfFlushDelayWrite(dev); + + return ret; +} + +/* Download SPI Fw */ +#define ZM_FIRMWARE_WLAN 0 +#define ZM_FIRMWARE_SPI_FLASH 1 + + +u16_t zfHpFirmwareDownload(zdev_t* dev, u8_t fwType) +{ + u16_t ret = ZM_SUCCESS; + + if (fwType == ZM_FIRMWARE_WLAN) + { + ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage, + (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR); + } + else if (fwType == ZM_FIRMWARE_SPI_FLASH) + { + ret = zfFirmwareDownload(dev, (u32_t*)zcFwImageSPI, + (u32_t)zcFwImageSPISize, ZM_FIRMWARE_SPI_ADDR); + } + else + { + zm_debug_msg1("Unknown firmware type = ", fwType); + ret = ZM_ERR_FIRMWARE_WRONG_TYPE; + } + + return ret; +} + +/* Enable software decryption */ +void zfHpSWDecrypt(zdev_t* dev, u8_t enable) +{ + u32_t value = 0x70; + + /* Bit 4 for enable software decryption */ + if (enable == 1) + { + value = 0x78; + } + + zfDelayWriteInternalReg(dev, 0x1c3678, value); + zfFlushDelayWrite(dev); +} + +/* Enable software encryption */ +void zfHpSWEncrypt(zdev_t* dev, u8_t enable) +{ + /* Because encryption by software or hardware is judged by driver in Otus, + we don't need to do anything in the HAL layer. + */ +} + +u32_t zfHpCapability(zdev_t* dev) +{ + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv=wd->hpPrivate; + + return hpPriv->halCapability; +} + +void zfHpSetRollCallTable(zdev_t* dev) +{ + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv=wd->hpPrivate; + + if (hpPriv->camRollCallTable != (u64_t) 0) + { + zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_L, (u32_t)(hpPriv->camRollCallTable & 0xffffffff)); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_H, (u32_t)((hpPriv->camRollCallTable >> 32) & 0xffffffff)); + zfFlushDelayWrite(dev); + } +} + +void zfHpSetTTSIFSTime(zdev_t* dev, u8_t sifs_time) +{ + u32_t reg_value = 0; + zmw_get_wlan_dev(dev); + + sifs_time &= 0x3f; + reg_value = 0x14400b | (((u32_t)sifs_time)<<24); + + zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, reg_value); + zfFlushDelayWrite(dev); +} + +/* #3 Enable RIFS function if the RIFS pattern matched ! */ +void zfHpEnableRifs(zdev_t* dev, u8_t mode24g, u8_t modeHt, u8_t modeHt2040) +{ + + /* # Enable Reset TDOMAIN + * $rddata = &$phyreg_read(0x9800+(738<<2)); + * $wrdata = $rddata | (0x1 << 26) | (0x1 << 27); + * &$phyreg_write(0x9800+(738<<2), $wrdata); + */ + reg_write (0x9800+(738<<2), 0x08000000 | (0x1 << 26) | (0x1 << 27)); + //reg_write (0x9800+(738<<2), 0x08000000 | (0x1 << 26)); + + /* # reg 123: heavy clip factor, xr / RIFS search parameters */ + reg_write (0x99ec, 0x0cc80caa); + + /* # Reduce Search Start Delay for RIFS */ + if (modeHt == 1) /* ($HT_ENABLE == 1) */ + { + if (modeHt2040 == 0x1) /* ($DYNAMIC_HT2040_EN == 0x1) */ + { + reg_write(0x9800+(70<<2), 40);/*40*/ + } + else + { + reg_write(0x9800+(70<<2), 20); + if(mode24g == 0x0) + { + /* $rddata = &$phyreg_read(0x9800+(24<<2));#0x9860;0x1c5860 + *$wrdata = ($rddata & 0xffffffc7) | (0x4 << 3); + * &$phyreg_write(0x9800+(24<<2), $wrdata); + */ + reg_write(0x9800+(24<<2), (0x0004dd10 & 0xffffffc7) | (0x4 << 3)); + } + } + } + + if (mode24g == 0x1) + { + reg_write(0x9850, 0xece8b4e4);/*org*/ + //reg_write(0x9850, 0xece8b4e2); + reg_write(0x985c, 0x313a5d5e); + } + else + { + reg_write(0x9850, 0xede8b4e4); + reg_write(0x985c, 0x3139605e); + } + + zfFlushDelayWrite(dev); + + return; +} + +/* #4 Disable RIFS function if the RIFS timer is timeout ! */ +void zfHpDisableRifs(zdev_t* dev) +{ + zmw_get_wlan_dev(dev); + + /* Disable RIFS function is to store these HW register initial value while the device plug-in and + re-write to these register if the RIFS function is disabled */ + + // reg : 9850 + reg_write(0x9850, ((struct zsHpPriv*)wd->hpPrivate)->initDesiredSigSize); + + // reg : 985c + reg_write(0x985c, ((struct zsHpPriv*)wd->hpPrivate)->initAGC); + + // reg : 9860 + reg_write(0x9800+(24<<2), ((struct zsHpPriv*)wd->hpPrivate)->initAgcControl); + + // reg : 9918 + reg_write(0x9800+(70<<2), ((struct zsHpPriv*)wd->hpPrivate)->initSearchStartDelay); + + // reg : 991c + reg_write (0x99ec, ((struct zsHpPriv*)wd->hpPrivate)->initRIFSSearchParams); + + // reg : a388 + reg_write (0x9800+(738<<2), ((struct zsHpPriv*)wd->hpPrivate)->initFastChannelChangeControl); + + zfFlushDelayWrite(dev); + + return; +} diff --git a/drivers/staging/otus/hal/hpreg.c b/drivers/staging/otus/hal/hpreg.c new file mode 100644 index 000000000000..3cfeba8620f6 --- /dev/null +++ b/drivers/staging/otus/hal/hpreg.c @@ -0,0 +1,2481 @@ +/* + * Copyright (c) 2000-2005 ZyDAS Technology Corporation + * Copyright (c) 2007-2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +/* */ +/* Module Name : hpreg.c */ +/* */ +/* Abstract */ +/* This module contains Regulatory Table and related function. */ +/* */ +/* NOTES */ +/* None */ +/* */ +/************************************************************************/ +#include "../80211core/cprecomp.h" +#include "hpani.h" +#include "hpreg.h" +#include "hpusb.h" + +/* used throughout this file... */ +#define N(a) (sizeof (a) / sizeof (a[0])) + +#define HAL_MODE_11A_TURBO HAL_MODE_108A +#define HAL_MODE_11G_TURBO HAL_MODE_108G + +#if 0 +enum { + /* test groups */ + FCC = 0x10, + MKK = 0x40, + ETSI = 0x30, + SD_NO_CTL = 0xe0, + NO_CTL = 0xff, + /* test modes */ + CTL_MODE_M = 0x0f, + CTL_11A = 0, + CTL_11B = 1, + CTL_11G = 2, + CTL_TURBO = 3, + CTL_108G = 4, + CTL_2GHT20 = 5, + CTL_5GHT20 = 6, + CTL_2GHT40 = 7, + CTL_5GHT40 = 8 +}; +#endif + +/* + * The following are flags for different requirements per reg domain. + * These requirements are either inhereted from the reg domain pair or + * from the unitary reg domain if the reg domain pair flags value is + * 0 + */ + +enum { + NO_REQ = 0x00000000, + DISALLOW_ADHOC_11A = 0x00000001, + DISALLOW_ADHOC_11A_TURB = 0x00000002, + NEED_NFC = 0x00000004, + + ADHOC_PER_11D = 0x00000008, /* Start Ad-Hoc mode */ + ADHOC_NO_11A = 0x00000010, + + PUBLIC_SAFETY_DOMAIN = 0x00000020, /* public safety domain */ + LIMIT_FRAME_4MS = 0x00000040, /* 4msec limit on the frame length */ +}; + +#define MKK5GHZ_FLAG1 (DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS) +#define MKK5GHZ_FLAG2 (DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS) + +typedef enum { + DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ + DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ + DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ +} HAL_DFS_DOMAIN; + +/* + * Used to set the RegDomain bitmask which chooses which frequency + * band specs are used. + */ + +#define BMLEN 2 /* Use 2 64 bit uint for channel bitmask + NB: Must agree with macro below (BM) */ +#define BMZERO {(u64_t) 0, (u64_t) 0} /* BMLEN zeros */ + +#if 0 + +#define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi, _fj, _fk, _fl) \ + {((((_fa >= 0) && (_fa < 64)) ? (((u64_t) 1) << _fa) : (u64_t) 0) | \ + (((_fb >= 0) && (_fb < 64)) ? (((u64_t) 1) << _fb) : (u64_t) 0) | \ + (((_fc >= 0) && (_fc < 64)) ? (((u64_t) 1) << _fc) : (u64_t) 0) | \ + (((_fd >= 0) && (_fd < 64)) ? (((u64_t) 1) << _fd) : (u64_t) 0) | \ + (((_fe >= 0) && (_fe < 64)) ? (((u64_t) 1) << _fe) : (u64_t) 0) | \ + (((_ff >= 0) && (_ff < 64)) ? (((u64_t) 1) << _ff) : (u64_t) 0) | \ + (((_fg >= 0) && (_fg < 64)) ? (((u64_t) 1) << _fg) : (u64_t) 0) | \ + (((_fh >= 0) && (_fh < 64)) ? (((u64_t) 1) << _fh) : (u64_t) 0) | \ + (((_fi >= 0) && (_fi < 64)) ? (((u64_t) 1) << _fi) : (u64_t) 0) | \ + (((_fj >= 0) && (_fj < 64)) ? (((u64_t) 1) << _fj) : (u64_t) 0) | \ + (((_fk >= 0) && (_fk < 64)) ? (((u64_t) 1) << _fk) : (u64_t) 0) | \ + (((_fl >= 0) && (_fl < 64)) ? (((u64_t) 1) << _fl) : (u64_t) 0) | \ + ((((_fa > 63) && (_fa < 128)) ? (((u64_t) 1) << (_fa - 64)) : (u64_t) 0) | \ + (((_fb > 63) && (_fb < 128)) ? (((u64_t) 1) << (_fb - 64)) : (u64_t) 0) | \ + (((_fc > 63) && (_fc < 128)) ? (((u64_t) 1) << (_fc - 64)) : (u64_t) 0) | \ + (((_fd > 63) && (_fd < 128)) ? (((u64_t) 1) << (_fd - 64)) : (u64_t) 0) | \ + (((_fe > 63) && (_fe < 128)) ? (((u64_t) 1) << (_fe - 64)) : (u64_t) 0) | \ + (((_ff > 63) && (_ff < 128)) ? (((u64_t) 1) << (_ff - 64)) : (u64_t) 0) | \ + (((_fg > 63) && (_fg < 128)) ? (((u64_t) 1) << (_fg - 64)) : (u64_t) 0) | \ + (((_fh > 63) && (_fh < 128)) ? (((u64_t) 1) << (_fh - 64)) : (u64_t) 0) | \ + (((_fi > 63) && (_fi < 128)) ? (((u64_t) 1) << (_fi - 64)) : (u64_t) 0) | \ + (((_fj > 63) && (_fj < 128)) ? (((u64_t) 1) << (_fj - 64)) : (u64_t) 0) | \ + (((_fk > 63) && (_fk < 128)) ? (((u64_t) 1) << (_fk - 64)) : (u64_t) 0) | \ + (((_fl > 63) && (_fl < 128)) ? (((u64_t) 1) << (_fl - 64)) : (u64_t) 0)))} + +#else + +#define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi, _fj, _fk, _fl) \ + {((((_fa >= 0) && (_fa < 64)) ? (((u64_t) 1) << (_fa&0x3f)) : (u64_t) 0) | \ + (((_fb >= 0) && (_fb < 64)) ? (((u64_t) 1) << (_fb&0x3f)) : (u64_t) 0) | \ + (((_fc >= 0) && (_fc < 64)) ? (((u64_t) 1) << (_fc&0x3f)) : (u64_t) 0) | \ + (((_fd >= 0) && (_fd < 64)) ? (((u64_t) 1) << (_fd&0x3f)) : (u64_t) 0) | \ + (((_fe >= 0) && (_fe < 64)) ? (((u64_t) 1) << (_fe&0x3f)) : (u64_t) 0) | \ + (((_ff >= 0) && (_ff < 64)) ? (((u64_t) 1) << (_ff&0x3f)) : (u64_t) 0) | \ + (((_fg >= 0) && (_fg < 64)) ? (((u64_t) 1) << (_fg&0x3f)) : (u64_t) 0) | \ + (((_fh >= 0) && (_fh < 64)) ? (((u64_t) 1) << (_fh&0x3f)) : (u64_t) 0) | \ + (((_fi >= 0) && (_fi < 64)) ? (((u64_t) 1) << (_fi&0x3f)) : (u64_t) 0) | \ + (((_fj >= 0) && (_fj < 64)) ? (((u64_t) 1) << (_fj&0x3f)) : (u64_t) 0) | \ + (((_fk >= 0) && (_fk < 64)) ? (((u64_t) 1) << (_fk&0x3f)) : (u64_t) 0) | \ + (((_fl >= 0) && (_fl < 64)) ? (((u64_t) 1) << (_fl&0x3f)) : (u64_t) 0) | \ + ((((_fa > 63) && (_fa < 128)) ? (((u64_t) 1) << ((_fa - 64)&0x3f)) : (u64_t) 0) | \ + (((_fb > 63) && (_fb < 128)) ? (((u64_t) 1) << ((_fb - 64)&0x3f)) : (u64_t) 0) | \ + (((_fc > 63) && (_fc < 128)) ? (((u64_t) 1) << ((_fc - 64)&0x3f)) : (u64_t) 0) | \ + (((_fd > 63) && (_fd < 128)) ? (((u64_t) 1) << ((_fd - 64)&0x3f)) : (u64_t) 0) | \ + (((_fe > 63) && (_fe < 128)) ? (((u64_t) 1) << ((_fe - 64)&0x3f)) : (u64_t) 0) | \ + (((_ff > 63) && (_ff < 128)) ? (((u64_t) 1) << ((_ff - 64)&0x3f)) : (u64_t) 0) | \ + (((_fg > 63) && (_fg < 128)) ? (((u64_t) 1) << ((_fg - 64)&0x3f)) : (u64_t) 0) | \ + (((_fh > 63) && (_fh < 128)) ? (((u64_t) 1) << ((_fh - 64)&0x3f)) : (u64_t) 0) | \ + (((_fi > 63) && (_fi < 128)) ? (((u64_t) 1) << ((_fi - 64)&0x3f)) : (u64_t) 0) | \ + (((_fj > 63) && (_fj < 128)) ? (((u64_t) 1) << ((_fj - 64)&0x3f)) : (u64_t) 0) | \ + (((_fk > 63) && (_fk < 128)) ? (((u64_t) 1) << ((_fk - 64)&0x3f)) : (u64_t) 0) | \ + (((_fl > 63) && (_fl < 128)) ? (((u64_t) 1) << ((_fl - 64)&0x3f)) : (u64_t) 0)))} + +#endif + +/* Mask to check whether a domain is a multidomain or a single + domain */ + +#define MULTI_DOMAIN_MASK 0xFF00 + + +/* + * The following describe the bit masks for different passive scan + * capability/requirements per regdomain. + */ +#define NO_PSCAN 0x0ULL +#define PSCAN_FCC 0x0000000000000001ULL +#define PSCAN_FCC_T 0x0000000000000002ULL +#define PSCAN_ETSI 0x0000000000000004ULL +#define PSCAN_MKK1 0x0000000000000008ULL +#define PSCAN_MKK2 0x0000000000000010ULL +#define PSCAN_MKKA 0x0000000000000020ULL +#define PSCAN_MKKA_G 0x0000000000000040ULL +#define PSCAN_ETSIA 0x0000000000000080ULL +#define PSCAN_ETSIB 0x0000000000000100ULL +#define PSCAN_ETSIC 0x0000000000000200ULL +#define PSCAN_WWR 0x0000000000000400ULL +#define PSCAN_MKKA1 0x0000000000000800ULL +#define PSCAN_MKKA1_G 0x0000000000001000ULL +#define PSCAN_MKKA2 0x0000000000002000ULL +#define PSCAN_MKKA2_G 0x0000000000004000ULL +#define PSCAN_MKK3 0x0000000000008000ULL +#define PSCAN_DEFER 0x7FFFFFFFFFFFFFFFULL +#define IS_ECM_CHAN 0x8000000000000000ULL + +/* + * THE following table is the mapping of regdomain pairs specified by + * an 8 bit regdomain value to the individual unitary reg domains + */ + +typedef struct reg_dmn_pair_mapping { + u16_t regDmnEnum; /* 16 bit reg domain pair */ + u16_t regDmn5GHz; /* 5GHz reg domain */ + u16_t regDmn2GHz; /* 2GHz reg domain */ + u32_t flags5GHz; /* Requirements flags (AdHoc + disallow, noise floor cal needed, + etc) */ + u32_t flags2GHz; /* Requirements flags (AdHoc + disallow, noise floor cal needed, + etc) */ + u64_t pscanMask; /* Passive Scan flags which + can override unitary domain + passive scan flags. This + value is used as a mask on + the unitary flags*/ + u16_t singleCC; /* Country code of single country if + a one-on-one mapping exists */ +} REG_DMN_PAIR_MAPPING; + +static REG_DMN_PAIR_MAPPING regDomainPairs[] = { + {NO_ENUMRD, FCC2, DEBUG_REG_DMN, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {NULL1_WORLD, NULL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {NULL1_ETSIB, NULL1, ETSIB, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {NULL1_ETSIC, NULL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + + {FCC2_FCCA, FCC2, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {FCC2_WORLD, FCC2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {FCC2_ETSIC, FCC2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {FCC3_FCCA, FCC3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {FCC3_WORLD, FCC3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {FCC4_FCCA, FCC4, FCCA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, + {FCC5_FCCA, FCC5, FCCA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, + {FCC6_FCCA, FCC6, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {FCC6_WORLD, FCC6, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + + {ETSI1_WORLD, ETSI1, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, + {ETSI2_WORLD, ETSI2, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, + {ETSI3_WORLD, ETSI3, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, + {ETSI4_WORLD, ETSI4, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, + {ETSI5_WORLD, ETSI5, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, + {ETSI6_WORLD, ETSI6, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, + + {ETSI3_ETSIA, ETSI3, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, + {FRANCE_RES, ETSI3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + + {FCC1_WORLD, FCC1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {FCC1_FCCA, FCC1, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {APL1_WORLD, APL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {APL2_WORLD, APL2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {APL3_WORLD, APL3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {APL4_WORLD, APL4, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {APL5_WORLD, APL5, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {APL6_WORLD, APL6, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {APL8_WORLD, APL8, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {APL9_WORLD, APL9, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + + {APL3_FCCA, APL3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {APL1_ETSIC, APL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {APL2_ETSIC, APL2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {APL2_FCCA, APL2, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {APL2_APLD, APL2, APLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, + {APL7_FCCA, APL7, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + + {MKK1_MKKA, MKK1, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA, CTRY_JAPAN }, + {MKK1_MKKB, MKK1, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN1 }, + {MKK1_FCCA, MKK1, FCCA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN2 }, + {MKK1_MKKA1, MKK1, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN4 }, + {MKK1_MKKA2, MKK1, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN5 }, + {MKK1_MKKC, MKK1, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN6 }, + + /* MKK2 */ + {MKK2_MKKA, MKK2, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK2 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN3 }, + + /* MKK3 */ + {MKK3_MKKA, MKK3, MKKA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN25 }, + {MKK3_MKKB, MKK3, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN7 }, + {MKK3_MKKA1, MKK3, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN26 }, + {MKK3_MKKA2, MKK3, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN8 }, + {MKK3_MKKC, MKK3, MKKC, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN9 }, + {MKK3_FCCA, MKK3, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN27 }, + + /* MKK4 */ + {MKK4_MKKB, MKK4, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN10 }, + {MKK4_MKKA1, MKK4, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN28 }, + {MKK4_MKKA2, MKK4, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3 |PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN11 }, + {MKK4_MKKC, MKK4, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3, CTRY_JAPAN12 }, + {MKK4_FCCA, MKK4, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN29 }, + {MKK4_MKKA, MKK4, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA, CTRY_JAPAN36 }, + + /* MKK5 */ + {MKK5_MKKB, MKK5, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN13 }, + {MKK5_MKKA2, MKK5, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN14 }, + {MKK5_MKKC, MKK5, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3, CTRY_JAPAN15 }, + + /* MKK6 */ + {MKK6_MKKB, MKK6, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN16 }, + {MKK6_MKKA2, MKK6, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN17 }, + {MKK6_MKKC, MKK6, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN18 }, + {MKK6_MKKA1, MKK6, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN30 }, + {MKK6_FCCA, MKK6, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN31 }, + + /* MKK7 */ + {MKK7_MKKB, MKK7, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN19 }, + {MKK7_MKKA, MKK7, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN20 }, + {MKK7_MKKC, MKK7, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3, CTRY_JAPAN21 }, + {MKK7_MKKA1, MKK7, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN32 }, + {MKK7_FCCA, MKK7, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN33 }, + + /* MKK8 */ + {MKK8_MKKB, MKK8, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN22 }, + {MKK8_MKKA2, MKK8, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN23 }, + {MKK8_MKKC, MKK8, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 , CTRY_JAPAN24 }, + + /* MKK9 */ + {MKK9_MKKA, MKK9, MKKA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN34 }, + {MKK9_FCCA, MKK9, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN37 }, + {MKK9_MKKA1, MKK9, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN38 }, + {MKK9_MKKC, MKK9, MKKC, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN39 }, + {MKK9_MKKA2, MKK9, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN40 }, + + /* MKK10 */ + {MKK10_MKKA, MKK10, MKKA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN35 }, + {MKK10_FCCA, MKK10, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN41 }, + {MKK10_MKKA1, MKK10, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN42 }, + {MKK10_MKKC, MKK10, MKKC, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN43 }, + {MKK10_MKKA2, MKK10, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN44 }, + + /* MKK11 */ + {MKK11_MKKA, MKK11, MKKA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN45 }, + {MKK11_FCCA, MKK11, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN46 }, + {MKK11_MKKA1, MKK11, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN47 }, + {MKK11_MKKC, MKK11, MKKC, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN48 }, + {MKK11_MKKA2, MKK11, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN49 }, + + /* MKK12 */ + {MKK12_MKKA, MKK12, MKKA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN50 }, + {MKK12_FCCA, MKK12, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN51 }, + {MKK12_MKKA1, MKK12, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN52 }, + {MKK12_MKKC, MKK12, MKKC, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN53 }, + {MKK12_MKKA2, MKK12, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN54 }, + + + /* These are super domains */ + {WOR0_WORLD, WOR0_WORLD, WOR0_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {WOR1_WORLD, WOR1_WORLD, WOR1_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, + {WOR2_WORLD, WOR2_WORLD, WOR2_WORLD, DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, + {WOR3_WORLD, WOR3_WORLD, WOR3_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {WOR4_WORLD, WOR4_WORLD, WOR4_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, + {WOR5_ETSIC, WOR5_ETSIC, WOR5_ETSIC, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, + {WOR01_WORLD, WOR01_WORLD, WOR01_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {WOR02_WORLD, WOR02_WORLD, WOR02_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {EU1_WORLD, EU1_WORLD, EU1_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {WOR9_WORLD, WOR9_WORLD, WOR9_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, + {WORA_WORLD, WORA_WORLD, WORA_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, +}; + +/* + * The following table is the master list for all different freqeuncy + * bands with the complete matrix of all possible flags and settings + * for each band if it is used in ANY reg domain. + */ + +#define DEF_REGDMN FCC1_FCCA +#define DEF_DMN_5 FCC1 +#define DEF_DMN_2 FCCA +#define COUNTRY_ERD_FLAG 0x8000 +#define WORLDWIDE_ROAMING_FLAG 0x4000 +#define SUPER_DOMAIN_MASK 0x0fff +#define COUNTRY_CODE_MASK 0x03ff +#define CF_INTERFERENCE (CHANNEL_CW_INT | CHANNEL_RADAR_INT) +#define CHANNEL_14 (2484) /* 802.11g operation is not permitted on channel 14 */ +#define IS_11G_CH14(_ch,_cf) \ + (((_ch) == CHANNEL_14) && ((_cf) == CHANNEL_G)) + +#define YES TRUE +#define NO FALSE + +enum { + CTRY_DEBUG = 0x1ff, /* debug country code */ + CTRY_DEFAULT = 0 /* default country code */ +}; + +typedef struct { + HAL_CTRY_CODE countryCode; + HAL_REG_DOMAIN regDmnEnum; + const char* isoName; + const char* name; + HAL_BOOL allow11g; + HAL_BOOL allow11aTurbo; + HAL_BOOL allow11gTurbo; + HAL_BOOL allow11na; /* HT-40 allowed in 5GHz? */ + HAL_BOOL allow11ng; /* HT-40 allowed in 2GHz? */ + u16_t outdoorChanStart; +} COUNTRY_CODE_TO_ENUM_RD; + +static COUNTRY_CODE_TO_ENUM_RD allCountries[] = { + {CTRY_DEBUG, NO_ENUMRD, "DB", "DEBUG", YES, YES, YES, YES, YES, 7000 }, + {CTRY_DEFAULT, DEF_REGDMN, "NA", "NO_COUNTRY_SET", YES, YES, YES, YES, YES, 7000 }, + {CTRY_ALBANIA, NULL1_WORLD, "AL", "ALBANIA", YES, NO, YES, NO, YES, 7000 }, + {CTRY_ALGERIA, NULL1_WORLD, "DZ", "ALGERIA", YES, NO, YES, NO, YES, 7000 }, + {CTRY_ARGENTINA, APL3_WORLD, "AR", "ARGENTINA", YES, NO, NO, NO, NO, 7000 }, + {CTRY_ARMENIA, ETSI4_WORLD, "AM", "ARMENIA", YES, NO, YES, NO, YES, 7000 }, + {CTRY_AUSTRALIA, FCC6_WORLD, "AU", "AUSTRALIA", YES, YES, YES, YES, YES, 7000 }, + {CTRY_AUSTRIA, ETSI2_WORLD, "AT", "AUSTRIA", YES, NO, YES, YES, YES, 7000 }, + {CTRY_AZERBAIJAN, ETSI4_WORLD, "AZ", "AZERBAIJAN", YES, YES, YES, YES, YES, 7000 }, + {CTRY_BAHRAIN, APL6_WORLD, "BH", "BAHRAIN", YES, NO, YES, NO, YES, 7000 }, + {CTRY_BELARUS, ETSI1_WORLD, "BY", "BELARUS", YES, NO, YES, YES, YES, 7000 }, + {CTRY_BELGIUM, ETSI1_WORLD, "BE", "BELGIUM", YES, NO, YES, YES, YES, 7000 }, + {CTRY_BELIZE, APL1_ETSIC, "BZ", "BELIZE", YES, YES, YES, YES, YES, 7000 }, + {CTRY_BOLIVIA, APL1_ETSIC, "BO", "BOLVIA", YES, YES, YES, YES, YES, 7000 }, + {CTRY_BRAZIL, FCC3_WORLD, "BR", "BRAZIL", NO, NO, NO, NO, NO, 7000 }, + {CTRY_BRUNEI_DARUSSALAM,APL1_WORLD,"BN", "BRUNEI DARUSSALAM", YES, YES, YES, YES, YES, 7000 }, + {CTRY_BULGARIA, ETSI6_WORLD, "BG", "BULGARIA", YES, NO, YES, YES, YES, 7000 }, + {CTRY_CANADA, FCC6_FCCA, "CA", "CANADA", YES, YES, YES, YES, YES, 7000 }, + {CTRY_CHILE, APL6_WORLD, "CL", "CHILE", YES, YES, YES, YES, YES, 7000 }, + {CTRY_CHINA, APL1_WORLD, "CN", "CHINA", YES, YES, YES, YES, YES, 7000 }, + {CTRY_COLOMBIA, FCC1_FCCA, "CO", "COLOMBIA", YES, NO, YES, NO, YES, 7000 }, + {CTRY_COSTA_RICA, FCC1_WORLD, "CR", "COSTA RICA", YES, NO, YES, NO, YES, 7000 }, + {CTRY_CROATIA, ETSI3_WORLD, "HR", "CROATIA", YES, NO, YES, NO, YES, 7000 }, + {CTRY_CYPRUS, ETSI3_WORLD, "CY", "CYPRUS", YES, YES, YES, YES, YES, 7000 }, + {CTRY_CZECH, ETSI3_WORLD, "CZ", "CZECH REPUBLIC", YES, NO, YES, YES, YES, 7000 }, + {CTRY_DENMARK, ETSI1_WORLD, "DK", "DENMARK", YES, NO, YES, YES, YES, 7000 }, + {CTRY_DOMINICAN_REPUBLIC,FCC1_FCCA,"DO", "DOMINICAN REPUBLIC", YES, YES, YES, YES, YES, 7000 }, + {CTRY_ECUADOR, FCC1_WORLD, "EC", "ECUADOR", YES, NO, NO, NO, YES, 7000 }, + {CTRY_EGYPT, ETSI3_WORLD, "EG", "EGYPT", YES, NO, YES, NO, YES, 7000 }, + {CTRY_EL_SALVADOR, FCC1_WORLD, "SV", "EL SALVADOR", YES, NO, YES, NO, YES, 7000 }, + {CTRY_ESTONIA, ETSI1_WORLD, "EE", "ESTONIA", YES, NO, YES, YES, YES, 7000 }, + {CTRY_FINLAND, ETSI1_WORLD, "FI", "FINLAND", YES, NO, YES, YES, YES, 7000 }, + {CTRY_FRANCE, ETSI1_WORLD, "FR", "FRANCE", YES, NO, YES, YES, YES, 7000 }, + {CTRY_FRANCE2, ETSI3_WORLD, "F2", "FRANCE_RES", YES, NO, YES, YES, YES, 7000 }, + {CTRY_GEORGIA, ETSI4_WORLD, "GE", "GEORGIA", YES, YES, YES, YES, YES, 7000 }, + {CTRY_GERMANY, ETSI1_WORLD, "DE", "GERMANY", YES, NO, YES, YES, YES, 7000 }, + {CTRY_GREECE, ETSI1_WORLD, "GR", "GREECE", YES, NO, YES, YES, YES, 7000 }, + {CTRY_GUATEMALA, FCC1_FCCA, "GT", "GUATEMALA", YES, YES, YES, YES, YES, 7000 }, + {CTRY_HONDURAS, NULL1_WORLD, "HN", "HONDURAS", YES, NO, YES, NO, YES, 7000 }, + {CTRY_HONG_KONG, FCC2_WORLD, "HK", "HONG KONG", YES, YES, YES, YES, YES, 7000 }, + {CTRY_HUNGARY, ETSI4_WORLD, "HU", "HUNGARY", YES, NO, YES, YES, YES, 7000 }, + {CTRY_ICELAND, ETSI1_WORLD, "IS", "ICELAND", YES, NO, YES, YES, YES, 7000 }, + {CTRY_INDIA, APL6_WORLD, "IN", "INDIA", YES, NO, YES, NO, YES, 7000 }, + {CTRY_INDONESIA, APL1_WORLD, "ID", "INDONESIA", YES, NO, YES, NO, YES, 7000 }, + {CTRY_IRAN, APL1_WORLD, "IR", "IRAN", YES, YES, YES, YES, YES, 7000 }, + {CTRY_IRELAND, ETSI1_WORLD, "IE", "IRELAND", YES, NO, YES, YES, YES, 7000 }, + {CTRY_ISRAEL, ETSI3_WORLD, "IL", "ISRAEL", YES, NO, YES, NO, YES, 7000 }, + {CTRY_ISRAEL2, NULL1_ETSIB, "ISR","ISRAEL_RES", YES, NO, YES, NO, YES, 7000 }, + {CTRY_ITALY, ETSI1_WORLD, "IT", "ITALY", YES, NO, YES, YES, YES, 7000 }, + {CTRY_JAMAICA, ETSI1_WORLD, "JM", "JAMAICA", YES, NO, YES, YES, YES, 7000 }, + {CTRY_JAPAN, MKK1_MKKA, "JP", "JAPAN", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN1, MKK1_MKKB, "J1", "JAPAN1", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN2, MKK1_FCCA, "J2", "JAPAN2", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN3, MKK2_MKKA, "J3", "JAPAN3", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN4, MKK1_MKKA1, "J4", "JAPAN4", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN5, MKK1_MKKA2, "J5", "JAPAN5", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN6, MKK1_MKKC, "J6", "JAPAN6", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN7, MKK3_MKKB, "J7", "JAPAN7", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN8, MKK3_MKKA2, "J8", "JAPAN8", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN9, MKK3_MKKC, "J9", "JAPAN9", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN10, MKK4_MKKB, "J10", "JAPAN10", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN11, MKK4_MKKA2, "J11", "JAPAN11", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN12, MKK4_MKKC, "J12", "JAPAN12", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN13, MKK5_MKKB, "J13", "JAPAN13", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN14, MKK5_MKKA2, "J14", "JAPAN14", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN15, MKK5_MKKC, "J15", "JAPAN15", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN16, MKK6_MKKB, "J16", "JAPAN16", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN17, MKK6_MKKA2, "J17", "JAPAN17", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN18, MKK6_MKKC, "J18", "JAPAN18", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN19, MKK7_MKKB, "J19", "JAPAN19", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN20, MKK7_MKKA, "J20", "JAPAN20", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN21, MKK7_MKKC, "J21", "JAPAN21", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN22, MKK8_MKKB, "J22", "JAPAN22", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN23, MKK8_MKKA2, "J23", "JAPAN23", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN24, MKK8_MKKC, "J24", "JAPAN24", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN25, MKK3_MKKA, "J25", "JAPAN25", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN26, MKK3_MKKA1, "J26", "JAPAN26", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN27, MKK3_FCCA, "J27", "JAPAN27", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN28, MKK4_MKKA1, "J28", "JAPAN28", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN29, MKK4_FCCA, "J29", "JAPAN29", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN30, MKK6_MKKA1, "J30", "JAPAN30", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN31, MKK6_FCCA, "J31", "JAPAN31", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN32, MKK7_MKKA1, "J32", "JAPAN32", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN33, MKK7_FCCA, "J33", "JAPAN33", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN34, MKK9_MKKA, "J34", "JAPAN34", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN35, MKK10_MKKA, "J35", "JAPAN35", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN36, MKK4_MKKA, "J36", "JAPAN36", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN37, MKK9_FCCA, "J37", "JAPAN37", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN38, MKK9_MKKA1, "J38", "JAPAN38", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN39, MKK9_MKKC, "J39", "JAPAN39", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN40, MKK10_MKKA2, "J40", "JAPAN40", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN41, MKK10_FCCA, "J41", "JAPAN41", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN42, MKK10_MKKA1, "J42", "JAPAN42", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN43, MKK10_MKKC, "J43", "JAPAN43", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN44, MKK10_MKKA2, "J44", "JAPAN44", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN45, MKK11_MKKA, "J45", "JAPAN45", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN46, MKK11_FCCA, "J46", "JAPAN46", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN47, MKK11_MKKA1, "J47", "JAPAN47", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN48, MKK11_MKKC, "J48", "JAPAN48", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN49, MKK11_MKKA2, "J49", "JAPAN49", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN50, MKK12_MKKA, "J50", "JAPAN50", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN51, MKK12_FCCA, "J51", "JAPAN51", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN52, MKK12_MKKA1, "J52", "JAPAN52", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN53, MKK12_MKKC, "J53", "JAPAN53", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JAPAN54, MKK12_MKKA2, "J54", "JAPAN54", YES, NO, NO, NO, NO, 7000 }, + {CTRY_JORDAN, ETSI2_WORLD, "JO", "JORDAN", YES, NO, YES, NO, YES, 7000 }, + {CTRY_KAZAKHSTAN, NULL1_WORLD, "KZ", "KAZAKHSTAN", YES, NO, YES, NO, YES, 7000 }, + {CTRY_KOREA_NORTH, APL9_WORLD, "KP", "NORTH KOREA", YES, NO, NO, YES, YES, 7000 }, + {CTRY_KOREA_ROC, APL9_WORLD, "KR", "KOREA REPUBLIC", YES, NO, NO, NO, NO, 7000 }, + {CTRY_KOREA_ROC2, APL2_APLD, "K2", "KOREA REPUBLIC2",YES, NO, NO, NO, NO, 7000 }, + {CTRY_KOREA_ROC3, APL9_WORLD, "K3", "KOREA REPUBLIC3",YES, NO, NO, NO, NO, 7000 }, + {CTRY_KUWAIT, NULL1_WORLD, "KW", "KUWAIT", YES, NO, YES, NO, YES, 7000 }, + {CTRY_LATVIA, ETSI1_WORLD, "LV", "LATVIA", YES, NO, YES, YES, YES, 7000 }, + {CTRY_LEBANON, NULL1_WORLD, "LB", "LEBANON", YES, NO, YES, NO, YES, 7000 }, + {CTRY_LIECHTENSTEIN,ETSI1_WORLD, "LI", "LIECHTENSTEIN", YES, NO, YES, YES, YES, 7000 }, + {CTRY_LITHUANIA, ETSI1_WORLD, "LT", "LITHUANIA", YES, NO, YES, YES, YES, 7000 }, + {CTRY_LUXEMBOURG, ETSI1_WORLD, "LU", "LUXEMBOURG", YES, NO, YES, YES, YES, 7000 }, + {CTRY_MACAU, FCC2_WORLD, "MO", "MACAU", YES, YES, YES, YES, YES, 7000 }, + {CTRY_MACEDONIA, NULL1_WORLD, "MK", "MACEDONIA", YES, NO, YES, NO, YES, 7000 }, + {CTRY_MALAYSIA, APL8_WORLD, "MY", "MALAYSIA", NO, NO, NO, NO, NO, 7000 }, + {CTRY_MALTA, ETSI1_WORLD, "MT", "MALTA", YES, NO, YES, YES, YES, 7000 }, + {CTRY_MEXICO, FCC1_FCCA, "MX", "MEXICO", YES, YES, YES, YES, YES, 7000 }, + {CTRY_MONACO, ETSI4_WORLD, "MC", "MONACO", YES, YES, YES, YES, YES, 7000 }, + {CTRY_MOROCCO, NULL1_WORLD, "MA", "MOROCCO", YES, NO, YES, NO, YES, 7000 }, + {CTRY_NETHERLANDS, ETSI1_WORLD, "NL", "NETHERLANDS", YES, NO, YES, YES, YES, 7000 }, + {CTRY_NETHERLANDS_ANT, ETSI1_WORLD, "AN", "NETHERLANDS-ANTILLES", YES, NO, YES, YES, YES, 7000 }, + {CTRY_NEW_ZEALAND, FCC2_ETSIC, "NZ", "NEW ZEALAND", YES, NO, YES, NO, YES, 7000 }, + {CTRY_NORWAY, ETSI1_WORLD, "NO", "NORWAY", YES, NO, YES, YES, YES, 7000 }, + {CTRY_OMAN, APL6_WORLD, "OM", "OMAN", YES, NO, YES, NO, YES, 7000 }, + {CTRY_PAKISTAN, NULL1_WORLD, "PK", "PAKISTAN", YES, NO, YES, NO, YES, 7000 }, + {CTRY_PANAMA, FCC1_FCCA, "PA", "PANAMA", YES, YES, YES, YES, YES, 7000 }, + {CTRY_PERU, APL1_WORLD, "PE", "PERU", YES, NO, YES, NO, YES, 7000 }, + {CTRY_PHILIPPINES, APL1_WORLD, "PH", "PHILIPPINES", YES, YES, YES, YES, YES, 7000 }, + {CTRY_POLAND, ETSI1_WORLD, "PL", "POLAND", YES, NO, YES, YES, YES, 7000 }, + {CTRY_PORTUGAL, ETSI1_WORLD, "PT", "PORTUGAL", YES, NO, YES, YES, YES, 7000 }, + {CTRY_PUERTO_RICO, FCC1_FCCA, "PR", "PUERTO RICO", YES, YES, YES, YES, YES, 7000 }, + {CTRY_QATAR, NULL1_WORLD, "QA", "QATAR", YES, NO, YES, NO, YES, 7000 }, + {CTRY_ROMANIA, NULL1_WORLD, "RO", "ROMANIA", YES, NO, YES, NO, YES, 7000 }, + {CTRY_RUSSIA, NULL1_WORLD, "RU", "RUSSIA", YES, NO, YES, NO, YES, 7000 }, + {CTRY_SAUDI_ARABIA,NULL1_WORLD, "SA", "SAUDI ARABIA", YES, NO, YES, NO, YES, 7000 }, + {CTRY_SERBIA_MONT, ETSI1_WORLD, "CS", "SERBIA & MONTENEGRO", YES, NO, YES, YES, YES, 7000 }, + {CTRY_SINGAPORE, APL6_WORLD, "SG", "SINGAPORE", YES, YES, YES, YES, YES, 7000 }, + {CTRY_SLOVAKIA, ETSI1_WORLD, "SK", "SLOVAK REPUBLIC",YES, NO, YES, YES, YES, 7000 }, + {CTRY_SLOVENIA, ETSI1_WORLD, "SI", "SLOVENIA", YES, NO, YES, YES, YES, 7000 }, + {CTRY_SOUTH_AFRICA,FCC3_WORLD, "ZA", "SOUTH AFRICA", YES, NO, YES, NO, YES, 7000 }, + {CTRY_SPAIN, ETSI1_WORLD, "ES", "SPAIN", YES, NO, YES, YES, YES, 7000 }, + {CTRY_SRILANKA, FCC3_WORLD, "LK", "SRI LANKA", YES, NO, YES, NO, YES, 7000 }, + {CTRY_SWEDEN, ETSI1_WORLD, "SE", "SWEDEN", YES, NO, YES, YES, YES, 7000 }, + {CTRY_SWITZERLAND, ETSI1_WORLD, "CH", "SWITZERLAND", YES, NO, YES, YES, YES, 7000 }, + {CTRY_SYRIA, NULL1_WORLD, "SY", "SYRIA", YES, NO, YES, NO, YES, 7000 }, + {CTRY_TAIWAN, APL3_FCCA, "TW", "TAIWAN", YES, YES, YES, YES, YES, 7000 }, + {CTRY_THAILAND, NULL1_WORLD, "TH", "THAILAND", YES, NO, YES, NO, YES, 7000 }, + {CTRY_TRINIDAD_Y_TOBAGO,ETSI4_WORLD,"TT", "TRINIDAD & TOBAGO", YES, NO, YES, NO, YES, 7000 }, + {CTRY_TUNISIA, ETSI3_WORLD, "TN", "TUNISIA", YES, NO, YES, NO, YES, 7000 }, + {CTRY_TURKEY, ETSI3_WORLD, "TR", "TURKEY", YES, NO, YES, NO, YES, 7000 }, + {CTRY_UKRAINE, NULL1_WORLD, "UA", "UKRAINE", YES, NO, YES, NO, YES, 7000 }, + {CTRY_UAE, NULL1_WORLD, "AE", "UNITED ARAB EMIRATES", YES, NO, YES, NO, YES, 7000 }, + {CTRY_UNITED_KINGDOM, ETSI1_WORLD,"GB", "UNITED KINGDOM", YES, NO, YES, NO, YES, 7000 }, + {CTRY_UNITED_STATES, FCC3_FCCA, "US", "UNITED STATES", YES, YES, YES, YES, YES, 5825 }, + {CTRY_UNITED_STATES_FCC49, FCC4_FCCA, "PS", "UNITED STATES (PUBLIC SAFETY)", YES, YES, YES, YES, YES, 7000 }, + {CTRY_URUGUAY, FCC1_WORLD, "UY", "URUGUAY", YES, NO, YES, NO, YES, 7000 }, + {CTRY_UZBEKISTAN, FCC3_FCCA, "UZ", "UZBEKISTAN", YES, YES, YES, YES, YES, 7000 }, + {CTRY_VENEZUELA, APL2_ETSIC, "VE", "VENEZUELA", YES, NO, YES, NO, YES, 7000 }, + {CTRY_VIET_NAM, NULL1_WORLD, "VN", "VIET NAM", YES, NO, YES, NO, YES, 7000 }, + {CTRY_YEMEN, NULL1_WORLD, "YE", "YEMEN", YES, NO, YES, NO, YES, 7000 }, + {CTRY_ZIMBABWE, NULL1_WORLD, "ZW", "ZIMBABWE", YES, NO, YES, NO, YES, 7000 } +}; + +typedef struct RegDmnFreqBand { + u16_t lowChannel; /* Low channel center in MHz */ + u16_t highChannel; /* High Channel center in MHz */ + u8_t powerDfs; /* Max power (dBm) for channel + range when using DFS */ + u8_t antennaMax; /* Max allowed antenna gain */ + u8_t channelBW; /* Bandwidth of the channel */ + u8_t channelSep; /* Channel separation within + the band */ + u64_t useDfs; /* Use DFS in the RegDomain + if corresponding bit is set */ + u64_t usePassScan; /* Use Passive Scan in the RegDomain + if corresponding bit is set */ + u8_t regClassId; /* Regulatory class id */ + u8_t useExtChanDfs; /* Regulatory class id */ +} REG_DMN_FREQ_BAND; + +/* Bit masks for DFS per regdomain */ + +enum { + NO_DFS = 0x0000000000000000ULL, + DFS_FCC3 = 0x0000000000000001ULL, + DFS_ETSI = 0x0000000000000002ULL, + DFS_MKK4 = 0x0000000000000004ULL, +}; + +/* The table of frequency bands is indexed by a bitmask. The ordering + * must be consistent with the enum below. When adding a new + * frequency band, be sure to match the location in the enum with the + * comments + */ + +/* + * 5GHz 11A channel tags + */ + +enum { + F1_4915_4925, + F1_4935_4945, + F1_4920_4980, + F1_4942_4987, + F1_4945_4985, + F1_4950_4980, + F1_5035_5040, + F1_5040_5080, + F1_5055_5055, + + F1_5120_5240, + + F1_5170_5230, + F2_5170_5230, + + F1_5180_5240, + F2_5180_5240, + F3_5180_5240, + F4_5180_5240, + F5_5180_5240, + F6_5180_5240, + F7_5180_5240, + + F1_5180_5320, + + F1_5240_5280, + + F1_5260_5280, + + F1_5260_5320, + F2_5260_5320, + F3_5260_5320, + F4_5260_5320, + F5_5260_5320, + F6_5260_5320, + F7_5260_5320, + + F1_5260_5700, + + F1_5280_5320, + + F1_5500_5580, + + F1_5500_5620, + + F1_5500_5700, + F2_5500_5700, + F3_5500_5700, + F4_5500_5700, + + F1_5660_5700, + + F1_5745_5805, + F2_5745_5805, + F3_5745_5805, + + F1_5745_5825, + F2_5745_5825, + F3_5745_5825, + F4_5745_5825, + F5_5745_5825, + F6_5745_5825, + + W1_4920_4980, + W1_5040_5080, + W1_5170_5230, + W1_5180_5240, + W1_5260_5320, + W1_5745_5825, + W1_5500_5700, + W2_5260_5320, + W2_5180_5240, + W2_5825_5825, +}; + +static REG_DMN_FREQ_BAND regDmn5GhzFreq[] = { + { 4915, 4925, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 16, 0 }, /* F1_4915_4925 */ + { 4935, 4945, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 16, 0 }, /* F1_4935_4945 */ + { 4920, 4980, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 7, 0 }, /* F1_4920_4980 */ + { 4942, 4987, 27, 6, 5, 5, DFS_FCC3, PSCAN_FCC, 0, 0 }, /* F1_4942_4987 */ + { 4945, 4985, 30, 6, 10, 5, DFS_FCC3, PSCAN_FCC, 0, 0 }, /* F1_4945_4985 */ + { 4950, 4980, 33, 6, 20, 5, DFS_FCC3, PSCAN_FCC, 0, 0 }, /* F1_4950_4980 */ + { 5035, 5040, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 12, 0 }, /* F1_5035_5040 */ + { 5040, 5080, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 2, 0 }, /* F1_5040_5080 */ + { 5055, 5055, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 12, 0 }, /* F1_5055_5055 */ + + { 5120, 5240, 5, 6, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F1_5120_5240 */ + + { 5170, 5230, 23, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1, 0 }, /* F1_5170_5230 */ + { 5170, 5230, 20, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1, 0 }, /* F2_5170_5230 */ + + { 5180, 5240, 15, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F1_5180_5240 */ + { 5180, 5240, 17, 6, 20, 20, NO_DFS, PSCAN_FCC, 1, 0 }, /* F2_5180_5240 */ + { 5180, 5240, 18, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F3_5180_5240 */ + { 5180, 5240, 20, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F4_5180_5240 */ + { 5180, 5240, 23, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F5_5180_5240 */ + { 5180, 5240, 23, 6, 20, 20, NO_DFS, PSCAN_FCC, 0, 0 }, /* F6_5180_5240 */ + { 5180, 5240, 23, 6, 20, 20, NO_DFS, NO_PSCAN, 0 }, /* F7_5180_5240 */ + + { 5180, 5320, 20, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0, 0 }, /* F1_5180_5320 */ + + { 5240, 5280, 23, 0, 20, 20, DFS_FCC3, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F1_5240_5280 */ + + { 5260, 5280, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F1_5260_5280 */ + + { 5260, 5320, 18, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F1_5260_5320 */ + + { 5260, 5320, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_FCC | PSCAN_ETSI | PSCAN_MKK3 , 0, 0 }, + /* F2_5260_5320 */ + + { 5260, 5320, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2, 0 }, /* F3_5260_5320 */ + { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2, 0 }, /* F4_5260_5320 */ + { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 0, 0 }, /* F5_5260_5320 */ + { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F6_5260_5320 */ + { 5260, 5320, 17, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0, 0 }, /* F7_5260_5320 */ + + { 5260, 5700, 5, 6, 20, 20, DFS_FCC3 | DFS_ETSI, NO_PSCAN, 0, 0 }, /* F1_5260_5700 */ + + { 5280, 5320, 17, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 0, 0 }, /* F1_5280_5320 */ + + { 5500, 5580, 23, 6, 20, 20, DFS_FCC3, PSCAN_FCC, 0}, /* F1_5500_5580 */ + + { 5500, 5620, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0, 0 }, /* F1_5500_5620 */ + + { 5500, 5700, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 4, 0 }, /* F1_5500_5700 */ + { 5500, 5700, 27, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F2_5500_5700 */ + { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F3_5500_5700 */ + { 5500, 5700, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_MKK3 | PSCAN_FCC, 0, 0 }, + /* F4_5500_5700 */ + + { 5660, 5700, 23, 6, 20, 20, DFS_FCC3, PSCAN_FCC, 0}, /* F1_5660_5700 */ + + { 5745, 5805, 23, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F1_5745_5805 */ + { 5745, 5805, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F2_5745_5805 */ + { 5745, 5805, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0, 0 }, /* F3_5745_5805 */ + { 5745, 5825, 5, 6, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F1_5745_5825 */ + { 5745, 5825, 17, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F2_5745_5825 */ + { 5745, 5825, 20, 0, 20, 20, DFS_ETSI, NO_PSCAN, 0, 0 }, /* F3_5745_5825 */ + { 5745, 5825, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F4_5745_5825 */ + { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 3, 0 }, /* F5_5745_5825 */ + { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F6_5745_5825 */ + + /* + * Below are the world roaming channels + * All WWR domains have no power limit, instead use the card's CTL + * or max power settings. + */ + { 4920, 4980, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0, 0 }, /* W1_4920_4980 */ + { 5040, 5080, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 }, /* W1_5040_5080 */ + { 5170, 5230, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0 }, /* W1_5170_5230 */ + { 5180, 5240, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0 }, /* W1_5180_5240 */ + { 5260, 5320, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0 }, /* W1_5260_5320 */ + { 5745, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0, 0 }, /* W1_5745_5825 */ + { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0 }, /* W1_5500_5700 */ + { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* W2_5260_5320 */ + { 5180, 5240, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* W2_5180_5240 */ + { 5825, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0, 0 }, /* W2_5825_5825 */ +}; +/* + * 5GHz Turbo (dynamic & static) tags + */ + +enum { + T1_5130_5210, + T1_5250_5330, + T1_5370_5490, + T1_5530_5650, + + T1_5150_5190, + T1_5230_5310, + T1_5350_5470, + T1_5510_5670, + + T1_5200_5240, + T2_5200_5240, + T1_5210_5210, + T2_5210_5210, + + T1_5280_5280, + T2_5280_5280, + T1_5250_5250, + T1_5290_5290, + T1_5250_5290, + T2_5250_5290, + + T1_5540_5660, + T1_5760_5800, + T2_5760_5800, + + T1_5765_5805, + + WT1_5210_5250, + WT1_5290_5290, + WT1_5540_5660, + WT1_5760_5800, +}; + +static REG_DMN_FREQ_BAND regDmn5GhzTurboFreq[] = { + { 5130, 5210, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5130_5210 */ + { 5250, 5330, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0, 0}, /* T1_5250_5330 */ + { 5370, 5490, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5370_5490 */ + { 5530, 5650, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0, 0}, /* T1_5530_5650 */ + + { 5150, 5190, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5150_5190 */ + { 5230, 5310, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0, 0}, /* T1_5230_5310 */ + { 5350, 5470, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5350_5470 */ + { 5510, 5670, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0, 0}, /* T1_5510_5670 */ + + { 5200, 5240, 17, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5200_5240 */ + { 5200, 5240, 23, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T2_5200_5240 */ + { 5210, 5210, 17, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5210_5210 */ + { 5210, 5210, 23, 0, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T2_5210_5210 */ + + { 5280, 5280, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0, 0}, /* T1_5280_5280 */ + { 5280, 5280, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0, 0}, /* T2_5280_5280 */ + { 5250, 5250, 17, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0, 0}, /* T1_5250_5250 */ + { 5290, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0, 0}, /* T1_5290_5290 */ + { 5250, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0, 0}, /* T1_5250_5290 */ + { 5250, 5290, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0, 0}, /* T2_5250_5290 */ + + { 5540, 5660, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0, 0}, /* T1_5540_5660 */ + { 5760, 5800, 20, 0, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5760_5800 */ + { 5760, 5800, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T2_5760_5800 */ + + { 5765, 5805, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5765_5805 */ + + /* + * Below are the WWR frequencies + */ + + { 5210, 5250, 15, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0}, /* WT1_5210_5250 */ + { 5290, 5290, 18, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0}, /* WT1_5290_5290 */ + { 5540, 5660, 20, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0}, /* WT1_5540_5660 */ + { 5760, 5800, 20, 0, 40, 40, NO_DFS, PSCAN_WWR, 0, 0}, /* WT1_5760_5800 */ +}; + +/* + * 2GHz 11b channel tags + */ +enum { + F1_2312_2372, + F2_2312_2372, + + F1_2412_2472, + F2_2412_2472, + F3_2412_2472, + + F1_2412_2462, + F2_2412_2462, + + F1_2432_2442, + + F1_2457_2472, + + F1_2467_2472, + + F1_2484_2484, + F2_2484_2484, + + F1_2512_2732, + + W1_2312_2372, + W1_2412_2412, + W1_2417_2432, + W1_2437_2442, + W1_2447_2457, + W1_2462_2462, + W1_2467_2467, + W2_2467_2467, + W1_2472_2472, + W2_2472_2472, + W1_2484_2484, + W2_2484_2484, +}; + +static REG_DMN_FREQ_BAND regDmn2GhzFreq[] = { + { 2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F1_2312_2372 */ + { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F2_2312_2372 */ + + { 2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F1_2412_2472 */ + { 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 0, 0}, /* F2_2412_2472 */ + { 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F3_2412_2472 */ + + { 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F1_2412_2462 */ + { 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 0, 0}, /* F2_2412_2462 */ + { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F1_2432_2442 */ + + { 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F1_2457_2472 */ + + { 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 0, 0}, /* F1_2467_2472 */ + + { 2484, 2484, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F1_2484_2484 */ + { 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA | PSCAN_MKKA1 | PSCAN_MKKA2, 0, 0}, /* F2_2484_2484 */ + + { 2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F1_2512_2732 */ + + /* + * WWR have powers opened up to 20dBm. Limits should often come from CTL/Max powers + */ + + { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* W1_2312_2372 */ + { 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* W1_2412_2412 */ + { 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* W1_2417_2432 */ + { 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* W1_2437_2442 */ + { 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* W1_2447_2457 */ + { 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* W1_2462_2462 */ + { 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0, 0}, /* W1_2467_2467 */ + { 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0, 0}, /* W2_2467_2467 */ + { 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0, 0}, /* W1_2472_2472 */ + { 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0, 0}, /* W2_2472_2472 */ + { 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0, 0}, /* W1_2484_2484 */ + { 2484, 2484, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0, 0}, /* W2_2484_2484 */ +}; + + +/* + * 2GHz 11g channel tags + */ + +enum { + G1_2312_2372, + G2_2312_2372, + + G1_2412_2472, + G2_2412_2472, + G3_2412_2472, + + G1_2412_2462, + G2_2412_2462, + + G1_2432_2442, + + G1_2457_2472, + + G1_2512_2732, + + G1_2467_2472 , + + WG1_2312_2372, + WG1_2412_2412, + WG1_2417_2432, + WG1_2437_2442, + WG1_2447_2457, + WG1_2462_2462, + WG1_2467_2467, + WG2_2467_2467, + WG1_2472_2472, + WG2_2472_2472, + +}; +static REG_DMN_FREQ_BAND regDmn2Ghz11gFreq[] = { + { 2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2312_2372 */ + { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G2_2312_2372 */ + + { 2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2412_2472 */ + { 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G, 0, 0}, /* G2_2412_2472 */ + { 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G3_2412_2472 */ + + { 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2412_2462 */ + { 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G, 0, 0}, /* G2_2412_2462 */ + { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2432_2442 */ + + { 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2457_2472 */ + + { 2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2512_2732 */ + + { 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 0, 0 }, /* G1_2467_2472 */ + + /* + * WWR open up the power to 20dBm + */ + + { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2312_2372 */ + { 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2412_2412 */ + { 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2417_2432 */ + { 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2437_2442 */ + { 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2447_2457 */ + { 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2462_2462 */ + { 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0, 0}, /* WG1_2467_2467 */ + { 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0, 0}, /* WG2_2467_2467 */ + { 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0, 0}, /* WG1_2472_2472 */ + { 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0, 0}, /* WG2_2472_2472 */ +}; +/* + * 2GHz Dynamic turbo tags + */ + +enum { + T1_2312_2372, + T1_2437_2437, + T2_2437_2437, + T3_2437_2437, + T1_2512_2732 +}; + +static REG_DMN_FREQ_BAND regDmn2Ghz11gTurboFreq[] = { + { 2312, 2372, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_2312_2372 */ + { 2437, 2437, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_2437_2437 */ + { 2437, 2437, 20, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T2_2437_2437 */ + { 2437, 2437, 18, 6, 40, 40, NO_DFS, PSCAN_WWR, 0, 0}, /* T3_2437_2437 */ + { 2512, 2732, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_2512_2732 */ +}; + + + +/* + * 2GHz 11n frequency tags + */ +enum { + NG1_2422_2452, + NG2_2422_2452, + NG3_2422_2452, + + NG_DEMO_ALL_CHANNELS, +}; + +static REG_DMN_FREQ_BAND regDmn2Ghz11ngFreq[] = { + { 2422, 2452, 20, 0, 40, 5, NO_DFS, NO_PSCAN, 0, 0}, /* NG1_2422_2452 */ + { 2422, 2452, 27, 0, 40, 5, NO_DFS, NO_PSCAN, 0, 0}, /* NG2_2422_2452 */ + { 2422, 2452, 30, 0, 40, 5, NO_DFS, NO_PSCAN, 0, 0}, /* NG3_2422_2452 */ + + { 2312, 2732, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* NG_DEMO_ALL_CHANNELS */ +}; + + +/* + * 5GHz 11n frequency tags + */ +enum { + NA1_5190_5230, + NA2_5190_5230, + NA3_5190_5230, + NA4_5190_5230, + NA5_5190_5230, + + NA1_5270_5270, + + NA1_5270_5310, + NA2_5270_5310, + NA3_5270_5310, + NA4_5270_5310, + + NA1_5310_5310, + + NA1_5510_5630, + + NA1_5510_5670, + NA2_5510_5670, + NA3_5510_5670, + + NA1_5755_5795, + NA2_5755_5795, + NA3_5755_5795, + NA4_5755_5795, + NA5_5755_5795, + + NA1_5795_5795, + + NA_DEMO_ALL_CHANNELS, +}; + +static REG_DMN_FREQ_BAND regDmn5Ghz11naFreq[] = { + /* + * ToDo: This table needs to be completely populated with 5GHz 11n properties + */ + { 5190, 5230, 15, 0, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA1_5190_5230 */ + { 5190, 5230, 17, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA2_5190_5230 */ + { 5190, 5230, 18, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA3_5190_5230 */ + { 5190, 5230, 20, 0, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA4_5190_5230 */ + { 5190, 5230, 23, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA5_5190_5230 */ + + { 5270, 5270, 23, 6, 40, 40, DFS_FCC3|DFS_ETSI, NO_PSCAN, 0, 1}, /* NA1_5270_5270 */ + + { 5270, 5310, 18, 6, 40, 40, DFS_FCC3|DFS_ETSI, NO_PSCAN, 0, 1}, /* NA1_5270_5310 */ + { 5270, 5310, 20, 0, 40, 40, DFS_FCC3|DFS_ETSI|DFS_MKK4, NO_PSCAN, 0, 1}, /* NA2_5270_5310 */ + { 5270, 5310, 23, 6, 40, 40, DFS_FCC3|DFS_ETSI, NO_PSCAN, 0, 1}, /* NA3_5270_5310 */ + { 5270, 5310, 30, 6, 40, 40, DFS_FCC3|DFS_ETSI, NO_PSCAN, 0, 1}, /* NA4_5270_5310 */ + + { 5310, 5310, 17, 6, 40, 40, DFS_FCC3|DFS_ETSI, NO_PSCAN, 0, 1}, /* NA1_5310_5310 */ + + { 5510, 5630, 30, 6, 40, 40, DFS_FCC3|DFS_ETSI, NO_PSCAN, 0, 1}, /* NA1_5510_5630 */ + + { 5510, 5670, 20, 6, 40, 40, DFS_FCC3|DFS_ETSI|DFS_MKK4, NO_PSCAN, 0, 1}, /* NA1_5510_5670 */ + { 5510, 5670, 27, 0, 40, 40, DFS_FCC3|DFS_ETSI, NO_PSCAN, 0, 1}, /* NA2_5510_5670 */ + { 5510, 5670, 30, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0, 1}, /* NA3_5510_5670 */ + + { 5755, 5795, 17, 0, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA1_5755_5795 */ + { 5755, 5795, 20, 6, 40, 40, DFS_ETSI, NO_PSCAN, 0, 0}, /* NA2_5755_5795 */ + { 5755, 5795, 23, 0, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA3_5755_5795 */ + { 5755, 5795, 30, 0, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA4_5755_5795 */ + { 5755, 5795, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA5_5755_5795 */ + + { 5795, 5795, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA1_5795_5795 */ + + { 4920, 6100, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA_DEMO_ALL_CHANNELS */ +}; + +typedef struct regDomain { + u16_t regDmnEnum; /* value from EnumRd table */ + u8_t conformanceTestLimit; + u64_t dfsMask; /* DFS bitmask for 5Ghz tables */ + u64_t pscan; /* Bitmask for passive scan */ + u32_t flags; /* Requirement flags (AdHoc disallow, noise + floor cal needed, etc) */ + u64_t chan11a[BMLEN];/* 128 bit bitmask for channel/band + selection */ + u64_t chan11a_turbo[BMLEN];/* 128 bit bitmask for channel/band + selection */ + u64_t chan11a_dyn_turbo[BMLEN]; /* 128 bit bitmask for channel/band + selection */ + u64_t chan11b[BMLEN];/* 128 bit bitmask for channel/band + selection */ + u64_t chan11g[BMLEN];/* 128 bit bitmask for channel/band + selection */ + u64_t chan11g_turbo[BMLEN];/* 128 bit bitmask for channel/band + selection */ + u64_t chan11ng[BMLEN];/* 128 bit bitmask for 11n in 2GHz */ + u64_t chan11na[BMLEN];/* 128 bit bitmask for 11n in 5GHz */ +} REG_DOMAIN; + +static REG_DOMAIN regDomains[] = { + + {DEBUG_REG_DMN, FCC, NO_DFS, NO_PSCAN, NO_REQ, + BM(F1_5120_5240, F1_5260_5700, F1_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BM(T1_5130_5210, T1_5250_5330, T1_5370_5490, T1_5530_5650, T1_5150_5190, T1_5230_5310, T1_5350_5470, T1_5510_5670, -1, -1, -1, -1), + BM(T1_5200_5240, T1_5280_5280, T1_5540_5660, T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1), + BM(F1_2312_2372, F1_2412_2472, F1_2484_2484, F1_2512_2732, -1, -1, -1, -1, -1, -1, -1, -1), + BM(G1_2312_2372, G1_2412_2472, G1_2512_2732, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BM(T1_2312_2372, T1_2437_2437, T1_2512_2732, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BM(NG_DEMO_ALL_CHANNELS, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BM(NA_DEMO_ALL_CHANNELS, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + {APL1, ETSI, NO_DFS, NO_PSCAN, NO_REQ, + BM(F4_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + {APL2, ETSI, NO_DFS, NO_PSCAN, NO_REQ, + BM(F1_5745_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA3_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + {APL3, FCC, NO_DFS, NO_PSCAN, NO_REQ, + BM(F1_5280_5320, F2_5745_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA1_5310_5310, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + {APL4, ETSI, NO_DFS, NO_PSCAN, NO_REQ, + BM(F4_5180_5240, F3_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA4_5190_5230, NA2_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + {APL5, ETSI, NO_DFS, NO_PSCAN, NO_REQ, + BM(F2_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA1_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + {APL6, ETSI, DFS_ETSI, PSCAN_FCC_T | PSCAN_FCC , NO_REQ, + BM(F4_5180_5240, F2_5260_5320, F3_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BM(T2_5210_5210, T1_5250_5290, T1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA4_5190_5230, NA2_5270_5310, NA2_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + {APL7, FCC, NO_DFS, PSCAN_FCC_T | PSCAN_FCC , NO_REQ, + BM(F7_5260_5320, F4_5500_5700, F3_5745_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA1_5310_5310, NA2_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + {APL8, ETSI, NO_DFS, NO_PSCAN, DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB, + BM(F6_5260_5320, F4_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA4_5270_5310, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + {APL9, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB, + BM(F1_5180_5320, F1_5500_5620, F3_5745_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA4_5190_5230, NA2_5270_5310, NA1_5510_5630, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1)}, + + {ETSI1, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, + BM(W2_5180_5240, F2_5260_5320, F2_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA4_5190_5230, NA2_5270_5310, NA2_5510_5670, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + {ETSI2, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, + BM(F3_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA3_5190_5230, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + {ETSI3, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, + BM(W2_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA4_5190_5230, NA2_5270_5310, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + {ETSI4, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, + BM(F3_5180_5240, F1_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA3_5190_5230, NA1_5270_5310, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + {ETSI5, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, + BM(F1_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA1_5190_5230, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + {ETSI6, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, + BM(F5_5180_5240, F1_5260_5280, F3_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA5_5190_5230, NA1_5270_5270, NA3_5510_5670, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + {FCC1, FCC, NO_DFS, NO_PSCAN, NO_REQ, + BM(F2_5180_5240, F4_5260_5320, F5_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BM(T1_5210_5210, T2_5250_5290, T2_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BM(T1_5200_5240, T1_5280_5280, T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA2_5190_5230, NA3_5270_5310, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + {FCC2, FCC, NO_DFS, NO_PSCAN, NO_REQ, + BM(F6_5180_5240, F5_5260_5320, F6_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BM(-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BM(T2_5200_5240, T1_5280_5280, T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA5_5190_5230, NA3_5270_5310, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + {FCC3, FCC, DFS_FCC3, PSCAN_FCC | PSCAN_FCC_T, NO_REQ, + BM(F2_5180_5240, F3_5260_5320, F1_5500_5700, F5_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1), + BM(T1_5210_5210, T1_5250_5250, T1_5290_5290, T2_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1), + BM(T1_5200_5240, T2_5280_5280, T1_5540_5660, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA2_5190_5230, NA2_5270_5310, NA3_5510_5670, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1)}, + + {FCC4, FCC, DFS_FCC3, PSCAN_FCC | PSCAN_FCC_T, NO_REQ, + BM(F1_4942_4987, F1_4945_4985, F1_4950_4980, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO}, + + {FCC5, FCC, NO_DFS, NO_PSCAN, NO_REQ, + BM(F2_5180_5240, F5_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA2_5190_5230, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + {FCC6, FCC, DFS_FCC3, PSCAN_FCC, NO_REQ, + BM(F7_5180_5240, F5_5260_5320, F1_5500_5580, F1_5660_5700, F6_5745_5825, -1, -1, -1, -1, -1, -1, -1), + BM(-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BM(T2_5200_5240, T1_5280_5280, T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA5_5190_5230, NA5_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + {MKK1, MKK, NO_DFS, PSCAN_MKK1, DISALLOW_ADHOC_11A_TURB, + BM(F1_5170_5230, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO}, + + {MKK2, MKK, NO_DFS, PSCAN_MKK2, DISALLOW_ADHOC_11A_TURB, + BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, F1_5055_5055, F1_5040_5080, F1_5170_5230, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO}, + + /* UNI-1 even */ + {MKK3, MKK, NO_DFS, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, + BM(F4_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA4_5190_5230, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + /* UNI-1 even + UNI-2 */ + {MKK4, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, + BM(F4_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA4_5190_5230, NA2_5270_5310, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + /* UNI-1 even + UNI-2 + mid-band */ + {MKK5, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, + BM(F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA4_5190_5230, NA2_5270_5310, NA1_5510_5670, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + /* UNI-1 odd + even */ + {MKK6, MKK, DFS_MKK4, PSCAN_MKK1, DISALLOW_ADHOC_11A_TURB, + BM(F2_5170_5230, F4_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA4_5190_5230, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + /* UNI-1 odd + UNI-1 even + UNI-2 */ + {MKK7, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3 , DISALLOW_ADHOC_11A_TURB, + BM(F2_5170_5230, F4_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA4_5190_5230, NA2_5270_5310, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + /* UNI-1 odd + UNI-1 even + UNI-2 + mid-band */ + {MKK8, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3 , DISALLOW_ADHOC_11A_TURB, + BM(F2_5170_5230, F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BM(NA4_5190_5230, NA2_5270_5310, NA1_5510_5670, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, + + /* UNI-1 even + 4.9 GHZ */ + {MKK9, MKK, NO_DFS, NO_PSCAN, DISALLOW_ADHOC_11A_TURB, + BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, F1_5055_5055, F1_5040_5080, F4_5180_5240, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO}, + + /* UNI-1 even + UNI-2 + 4.9 GHZ */ + {MKK10, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, + BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, F1_5055_5055, F1_5040_5080, F4_5180_5240, F2_5260_5320, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO}, + + /* UNI-1 even + UNI-2 + 4.9 GHZ + mid-band */ + {MKK11, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, + BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, F1_5055_5055, F1_5040_5080, F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO}, + + /* UNI-1 even + UNI-1 odd + UNI-2 + 4.9 GHZ + mid-band */ + {MKK12, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, + BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, F1_5055_5055, F1_5040_5080, F1_5170_5230, F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1), + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO}, + + /* Defined here to use when 2G channels are authorised for country K2 */ + {APLD, NO_CTL, NO_DFS, NO_PSCAN, NO_REQ, + BMZERO, + BMZERO, + BMZERO, + BM(F2_2312_2372,F2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BM(G2_2312_2372,G2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BMZERO}, + + {ETSIA, NO_CTL, NO_DFS, PSCAN_ETSIA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, + BMZERO, + BMZERO, + BMZERO, + BM(F1_2457_2472,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BM(G1_2457_2472,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BM(T2_2437_2437,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO}, + + {ETSIB, ETSI, NO_DFS, PSCAN_ETSIB, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, + BMZERO, + BMZERO, + BMZERO, + BM(F1_2432_2442,-1,-1,-1,-1,-1,-1,-1, -1, -1, -1, -1), + BM(G1_2432_2442,-1,-1,-1,-1,-1,-1,-1, -1, -1, -1, -1), + BM(T2_2437_2437,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO}, + + {ETSIC, ETSI, NO_DFS, PSCAN_ETSIC, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, + BMZERO, + BMZERO, + BMZERO, + BM(F3_2412_2472,-1,-1,-1,-1,-1,-1,-1, -1, -1, -1, -1), + BM(G3_2412_2472,-1,-1,-1,-1,-1,-1,-1, -1, -1, -1, -1), + BM(T2_2437_2437,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO}, + + {FCCA, FCC, NO_DFS, NO_PSCAN, NO_REQ, + BMZERO, + BMZERO, + BMZERO, + BM(F1_2412_2462,-1,-1,-1,-1,-1,-1,-1, -1, -1, -1, -1), + BM(G1_2412_2462,-1,-1,-1,-1,-1,-1,-1, -1, -1, -1, -1), + BM(T2_2437_2437,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BM(NG2_2422_2452,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO}, + + {MKKA, MKK, NO_DFS, PSCAN_MKKA | PSCAN_MKKA_G | PSCAN_MKKA1 | PSCAN_MKKA1_G | PSCAN_MKKA2 | PSCAN_MKKA2_G, DISALLOW_ADHOC_11A_TURB, + BMZERO, + BMZERO, + BMZERO, + BM(F2_2412_2462, F1_2467_2472, F2_2484_2484, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BM(G2_2412_2462, G1_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BM(T2_2437_2437,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BM(NG1_2422_2452,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO}, + + {MKKC, MKK, NO_DFS, NO_PSCAN, NO_REQ, + BMZERO, + BMZERO, + BMZERO, + BM(F2_2412_2472,-1,-1,-1,-1,-1,-1,-1, -1, -1, -1, -1), + BM(G2_2412_2472,-1,-1,-1,-1,-1,-1,-1, -1, -1, -1, -1), + BM(T2_2437_2437,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BM(NG1_2422_2452,-1,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO}, + + {WORLD, ETSI, NO_DFS, NO_PSCAN, NO_REQ, + BMZERO, + BMZERO, + BMZERO, + BM(F2_2412_2472,-1,-1,-1,-1,-1,-1,-1, -1, -1, -1, -1), + BM(G2_2412_2472,-1,-1,-1,-1,-1,-1,-1, -1, -1, -1, -1), + BM(T2_2437_2437,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BM(NG1_2422_2452,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO}, + + {WOR0_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D, + BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1), + BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BM(W1_2412_2412,W1_2437_2442,W1_2462_2462,W1_2472_2472,W1_2417_2432, W1_2447_2457, W1_2467_2467, W1_2484_2484, -1, -1, -1, -1), + BM(WG1_2412_2412,WG1_2437_2442,WG1_2462_2462,WG1_2472_2472,WG1_2417_2432,WG1_2447_2457,WG1_2467_2467, -1, -1, -1, -1, -1), + BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO}, + + {WOR01_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D, + BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1), + BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2417_2432, W1_2447_2457, -1, -1, -1, -1, -1, -1, -1), + BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2417_2432, WG1_2447_2457, -1, -1, -1, -1, -1, -1, -1), + BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO}, + + {WOR02_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D, + BM(W1_5260_5320, W1_5180_5240,W1_5170_5230,W1_5745_5825,W1_5500_5700, -1, -1, -1, -1, -1, -1, -1), + BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BM(W1_2412_2412,W1_2437_2442,W1_2462_2462, W1_2472_2472,W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1), + BM(WG1_2412_2412,WG1_2437_2442,WG1_2462_2462, WG1_2472_2472,WG1_2417_2432, WG1_2447_2457, WG1_2467_2467, -1, -1, -1, -1, -1), + BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO}, + + {EU1_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D, + BM(W1_5260_5320, W1_5180_5240,W1_5170_5230,W1_5745_5825,W1_5500_5700, -1, -1, -1, -1, -1, -1, -1), + BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BM(W1_2412_2412,W1_2437_2442,W1_2462_2462, W2_2472_2472,W1_2417_2432, W1_2447_2457, W2_2467_2467, -1, -1, -1, -1, -1), + BM(WG1_2412_2412,WG1_2437_2442,WG1_2462_2462, WG2_2472_2472,WG1_2417_2432, WG1_2447_2457, WG2_2467_2467, -1, -1, -1, -1, -1), + BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO}, + + {WOR1_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, + BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BM(W1_2412_2412,W1_2437_2442,W1_2462_2462,W1_2472_2472,W1_2417_2432, W1_2447_2457, W1_2467_2467, W1_2484_2484, -1, -1, -1, -1), + BM(WG1_2412_2412,WG1_2437_2442,WG1_2462_2462,WG1_2472_2472,WG1_2417_2432,WG1_2447_2457,WG1_2467_2467, -1, -1, -1, -1, -1), + BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO}, + + {WOR2_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, + BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1), + BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BM(W1_2412_2412,W1_2437_2442,W1_2462_2462,W1_2472_2472,W1_2417_2432, W1_2447_2457, W1_2467_2467, W1_2484_2484, -1, -1, -1, -1), + BM(WG1_2412_2412,WG1_2437_2442,WG1_2462_2462,WG1_2472_2472,WG1_2417_2432,WG1_2447_2457,WG1_2467_2467, -1, -1, -1, -1, -1), + BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO}, + + {WOR3_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D, + BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1), + BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BM(W1_2412_2412,W1_2437_2442,W1_2462_2462,W1_2472_2472,W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1), + BM(WG1_2412_2412,WG1_2437_2442,WG1_2462_2462,WG1_2472_2472,WG1_2417_2432,WG1_2447_2457,WG1_2467_2467,-1, -1, -1, -1, -1), + BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO}, + + {WOR4_WORLD, NO_CTL, DFS_FCC3, PSCAN_WWR, ADHOC_NO_11A, + BM(W2_5260_5320, W2_5180_5240, F2_5745_5805, W2_5825_5825, -1, -1, -1, -1, -1, -1, -1, -1), + BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BM(W1_2412_2412,W1_2437_2442,W1_2462_2462, W1_2417_2432,W1_2447_2457,-1, -1, -1, -1, -1, -1, -1), + BM(WG1_2412_2412,WG1_2437_2442,WG1_2462_2462, WG1_2417_2432,WG1_2447_2457,-1, -1, -1, -1, -1, -1, -1), + BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO}, + + {WOR5_ETSIC, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, + BM(W1_5260_5320, W2_5180_5240, F6_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W2_2472_2472, W1_2417_2432, W1_2447_2457, W2_2467_2467, -1, -1, -1, -1, -1), + BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2472_2472, WG1_2417_2432, WG1_2447_2457, WG1_2467_2467, -1, -1, -1, -1, -1), + BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO}, + + {WOR9_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, + BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1), + BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2417_2432, W1_2447_2457, -1, -1, -1, -1, -1, -1, -1), + BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2417_2432, WG1_2447_2457, -1, -1, -1, -1, -1, -1, -1), + BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO}, + + {WORA_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, + BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO, + BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1), + BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2472_2472, WG1_2417_2432, WG1_2447_2457, WG1_2467_2467, -1, -1, -1, -1, -1), + BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), + BMZERO, + BMZERO}, + + {NULL1, NO_CTL, NO_DFS, NO_PSCAN, NO_REQ, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO, + BMZERO}, +}; + +struct cmode { + u16_t mode; + u32_t flags; +}; + +static const struct cmode modes[] = { + { HAL_MODE_TURBO, CHANNEL_ST}, /* TURBO means 11a Static Turbo */ + { HAL_MODE_11A, CHANNEL_A}, + { HAL_MODE_11B, CHANNEL_B}, + { HAL_MODE_11G, CHANNEL_G}, + { HAL_MODE_11G_TURBO, CHANNEL_108G}, + { HAL_MODE_11A_TURBO, CHANNEL_108A}, + { HAL_MODE_11NA, CHANNEL_A_HT40}, + { HAL_MODE_11NA, CHANNEL_A_HT20}, + { HAL_MODE_11NG, CHANNEL_G_HT40}, + { HAL_MODE_11NG, CHANNEL_G_HT20}, +}; + +/* + * Return the Wireless Mode Regulatory Domain based + * on the country code and the wireless mode. + */ +u8_t GetWmRD(u16_t regionCode, u16_t channelFlag, REG_DOMAIN *rd) +{ + s16_t i, found, regDmn; + u64_t flags=NO_REQ; + REG_DMN_PAIR_MAPPING *regPair=NULL; + + for (i=0, found=0; (i<N(regDomainPairs))&&(!found); i++) + { + if (regDomainPairs[i].regDmnEnum == regionCode) + { + regPair = ®DomainPairs[i]; + found = 1; + } + } + if (!found) + { + zm_debug_msg1("Failed to find reg domain pair ", regionCode); + return FALSE; + } + + if (channelFlag & ZM_REG_FLAG_CHANNEL_2GHZ) + { + regDmn = regPair->regDmn2GHz; + flags = regPair->flags2GHz; + } + else + { + regDmn = regPair->regDmn5GHz; + flags = regPair->flags5GHz; + } + + /* + * We either started with a unitary reg domain or we've found the + * unitary reg domain of the pair + */ + + for (i=0;i<N(regDomains); i++) + { + if (regDomains[i].regDmnEnum == regDmn) + { + if (rd != NULL) + { + zfMemoryCopy((u8_t *)rd, (u8_t *)®Domains[i], + sizeof(REG_DOMAIN)); + } + } + } + rd->pscan &= regPair->pscanMask; + rd->flags = (u32_t)flags; + return TRUE; +} + +/* + * Test to see if the bitmask array is all zeros + */ +u8_t isChanBitMaskZero(u64_t *bitmask) +{ + u16_t i; + + for (i=0; i<BMLEN; i++) { + if (bitmask[i] != 0) + return FALSE; + } + return TRUE; +} + +u8_t IS_BIT_SET(u32_t bit, u64_t *bitmask) +{ + u32_t byteOffset, bitnum; + u64_t val; + + byteOffset = bit/64; + bitnum = bit - byteOffset*64; + val = ((u64_t) 1) << bitnum; + if (bitmask[byteOffset] & val) + return TRUE; + else + return FALSE; +} + + +void zfHpGetRegulationTable(zdev_t* dev, u16_t regionCode, u16_t c_lo, u16_t c_hi) +{ + REG_DOMAIN rd5GHz, rd2GHz; + const struct cmode *cm; + s16_t next=0,b; + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv=wd->hpPrivate; + + zmw_declare_for_critical_section(); + + if (!GetWmRD(regionCode, ~ZM_REG_FLAG_CHANNEL_2GHZ, &rd5GHz)) + { + zm_debug_msg1("couldn't find unitary 5GHz reg domain for Region Code ", regionCode); + return; + } + if (!GetWmRD(regionCode, ZM_REG_FLAG_CHANNEL_2GHZ, &rd2GHz)) + { + zm_debug_msg1("couldn't find unitary 2GHz reg domain for Region Code ", regionCode); + return; + } + if (wd->regulationTable.regionCode == regionCode) + { + zm_debug_msg1("current region code is the same with Region Code ", regionCode); + return; + } + else + { + wd->regulationTable.regionCode = regionCode; + } + + next = 0; + + zmw_enter_critical_section(dev); + + for (cm = modes; cm < &modes[N(modes)]; cm++) + { + u16_t c; + u64_t *channelBM=NULL; + REG_DOMAIN *rd=NULL; + REG_DMN_FREQ_BAND *fband=NULL,*freqs=NULL; + + switch (cm->mode) + { + case HAL_MODE_TURBO: + //we don't have turbo mode so we disable it + //zm_debug_msg0("CWY - HAL_MODE_TURBO"); + channelBM = NULL; + //rd = &rd5GHz; + //channelBM = rd->chan11a_turbo; + //freqs = ®Dmn5GhzTurboFreq[0]; + //ctl = rd->conformanceTestLimit | CTL_TURBO; + break; + case HAL_MODE_11A: + if ((hpPriv->OpFlags & 0x1) != 0) + { + rd = &rd5GHz; + channelBM = rd->chan11a; + freqs = ®Dmn5GhzFreq[0]; + c_lo = 4920; //from channel 184 + c_hi = 5825; //to channel 165 + //ctl = rd->conformanceTestLimit; + //zm_debug_msg2("CWY - HAL_MODE_11A, channelBM = 0x", *channelBM); + } + //else + { + //channelBM = NULL; + } + break; + case HAL_MODE_11B: + //Disable 11B mode because it only has difference with 11G in PowerDFS Data, + //and we don't use this now. + //zm_debug_msg0("CWY - HAL_MODE_11B"); + channelBM = NULL; + //rd = &rd2GHz; + //channelBM = rd->chan11b; + //freqs = ®Dmn2GhzFreq[0]; + //ctl = rd->conformanceTestLimit | CTL_11B; + //zm_debug_msg2("CWY - HAL_MODE_11B, channelBM = 0x", *channelBM); + break; + case HAL_MODE_11G: + if ((hpPriv->OpFlags & 0x2) != 0) + { + rd = &rd2GHz; + channelBM = rd->chan11g; + freqs = ®Dmn2Ghz11gFreq[0]; + c_lo = 2412; //from channel 1 + //c_hi = 2462; //to channel 11 + c_hi = 2472; //to channel 13 + //ctl = rd->conformanceTestLimit | CTL_11G; + //zm_debug_msg2("CWY - HAL_MODE_11G, channelBM = 0x", *channelBM); + } + //else + { + //channelBM = NULL; + } + break; + case HAL_MODE_11G_TURBO: + //we don't have turbo mode so we disable it + //zm_debug_msg0("CWY - HAL_MODE_11G_TURBO"); + channelBM = NULL; + //rd = &rd2GHz; + //channelBM = rd->chan11g_turbo; + //freqs = ®Dmn2Ghz11gTurboFreq[0]; + //ctl = rd->conformanceTestLimit | CTL_108G; + break; + case HAL_MODE_11A_TURBO: + //we don't have turbo mode so we disable it + //zm_debug_msg0("CWY - HAL_MODE_11A_TURBO"); + channelBM = NULL; + //rd = &rd5GHz; + //channelBM = rd->chan11a_dyn_turbo; + //freqs = ®Dmn5GhzTurboFreq[0]; + //ctl = rd->conformanceTestLimit | CTL_108G; + break; + default: + zm_debug_msg1("Unkonwn HAL mode ", cm->mode); + continue; + } + if (channelBM == NULL) + { + //zm_debug_msg0("CWY - channelBM is NULL"); + continue; + } + if (isChanBitMaskZero(channelBM)) + { + //zm_debug_msg0("CWY - BitMask is Zero"); + continue; + } + + // RAY:Is it ok?? + if (freqs == NULL ) + { + continue; + } + + for (b=0;b<64*BMLEN; b++) + { + if (IS_BIT_SET(b,channelBM)) + { + fband = &freqs[b]; + + //zm_debug_msg1("CWY - lowChannel = ", fband->lowChannel); + //zm_debug_msg1("CWY - highChannel = ", fband->highChannel); + //zm_debug_msg1("CWY - channelSep = ", fband->channelSep); + for (c=fband->lowChannel; c <= fband->highChannel; + c += fband->channelSep) + { + ZM_HAL_CHANNEL icv; + + //Disable all DFS channel + if ((hpPriv->disableDfsCh==0) || (!(fband->useDfs & rd->dfsMask))) + { + if( fband->channelBW < 20 ) + { + /**************************************************************/ + /* */ + /* Temporary discard channel that BW < 20MHz (5 or 10MHz) */ + /* Our architecture does not implemnt it !!! */ + /* */ + /**************************************************************/ + continue; + } + if ((c >= c_lo) && (c <= c_hi)) + { + icv.channel = c; + icv.channelFlags = cm->flags; + icv.maxRegTxPower = fband->powerDfs; + if (fband->usePassScan & rd->pscan) + icv.channelFlags |= ZM_REG_FLAG_CHANNEL_PASSIVE; + else + icv.channelFlags &= ~ZM_REG_FLAG_CHANNEL_PASSIVE; + if (fband->useDfs & rd->dfsMask) + icv.privFlags = ZM_REG_FLAG_CHANNEL_DFS; + else + icv.privFlags = 0; + + /* For now disable radar for FCC3 */ + if (fband->useDfs & rd->dfsMask & DFS_FCC3) + { + icv.privFlags &= ~ZM_REG_FLAG_CHANNEL_DFS; + icv.privFlags |= ZM_REG_FLAG_CHANNEL_DFS_CLEAR; + } + + if(rd->flags & LIMIT_FRAME_4MS) + icv.privFlags |= ZM_REG_FLAG_CHANNEL_DFS_CLEAR; + + icv.minTxPower = 0; + icv.maxTxPower = 0; + + zm_assert(next < 60); + + wd->regulationTable.allowChannel[next++] = icv; + } + } + } + } + } + } + wd->regulationTable.allowChannelCnt = next; + + #if 0 + { + /* debug print */ + u32_t i; + DbgPrint("\n-------------------------------------------\n"); + DbgPrint("zfHpGetRegulationTable print all channel info regincode = 0x%x\n", wd->regulationTable.regionCode); + DbgPrint("index channel channelFlags maxRegTxPower privFlags useDFS\n"); + + for (i=0; i<wd->regulationTable.allowChannelCnt; i++) + { + DbgPrint("%02d %d %04x %02d %x %x\n", + i, + wd->regulationTable.allowChannel[i].channel, + wd->regulationTable.allowChannel[i].channelFlags, + wd->regulationTable.allowChannel[i].maxRegTxPower, + wd->regulationTable.allowChannel[i].privFlags, + wd->regulationTable.allowChannel[i].privFlags & ZM_REG_FLAG_CHANNEL_DFS); + } + } + #endif + + zmw_leave_critical_section(dev); +} + +void zfHpGetRegulationTablefromRegionCode(zdev_t* dev, u16_t regionCode) +{ + u16_t c_lo = 2000, c_hi = 6000; //default channel is all enable + u8_t isoName[3] = {'N', 'A', 0}; + + zfCoreSetIsoName(dev, isoName); + + zfHpGetRegulationTable(dev, regionCode, c_lo, c_hi); +} + +void zfHpGetRegulationTablefromCountry(zdev_t* dev, u16_t CountryCode) +{ + u16_t i; + u16_t c_lo = 2000, c_hi = 6000; //default channel is all enable + u16_t RegDomain; + + zmw_get_wlan_dev(dev); + + zmw_declare_for_critical_section(); + + for (i = 0; i < N(allCountries); i++) + { + if (CountryCode == allCountries[i].countryCode) + { + RegDomain = allCountries[i].regDmnEnum; + + // read the ACU country code from EEPROM + zfCoreSetIsoName(dev, (u8_t*)allCountries[i].isoName); + + //zm_debug_msg_s("CWY - Country Name = ", allCountries[i].name); + + if (wd->regulationTable.regionCode != RegDomain) + { + //zm_debug_msg0("CWY - Change regulatory table"); + + zfHpGetRegulationTable(dev, RegDomain, c_lo, c_hi); + } + return; + } + } + zm_debug_msg1("Invalid CountryCode = ", CountryCode); +} + +u8_t zfHpGetRegulationTablefromISO(zdev_t* dev, u8_t *countryInfo, u8_t length) +{ + u16_t i; + u16_t RegDomain; + u16_t c_lo = 2000, c_hi = 6000; //default channel is all enable + //u8_t strLen = 2; + + zmw_get_wlan_dev(dev); + + zmw_declare_for_critical_section(); + + if (countryInfo[4] != 0x20) + { // with (I)ndoor/(O)utdoor info + //strLen = 3; + } + //zm_debug_msg_s("Desired iso name = ", isoName); + for (i = 0; i < N(allCountries); i++) + { + //zm_debug_msg_s("Current iso name = ", allCountries[i].isoName); + if (zfMemoryIsEqual((u8_t *)allCountries[i].isoName, (u8_t *)&countryInfo[2], length-1)) + { + //DbgPrint("Set current iso name = %s\n", allCountries[i].isoName); + //zm_debug_msg0("iso name hit!!"); + + RegDomain = allCountries[i].regDmnEnum; + + if (wd->regulationTable.regionCode != RegDomain) + { + zfHpGetRegulationTable(dev, RegDomain, c_lo, c_hi); + } + + //while (index < (countryInfo[1]+2)) + //{ + // if (countryInfo[index] <= 14) + // { + // /* calculate 2.4GHz low boundary channel frequency */ + // ch = countryInfo[index]; + // if ( ch == 14 ) + // c_lo = ZM_CH_G_14; + // else + // c_lo = ZM_CH_G_1 + (ch - 1) * 5; + // /* calculate 2.4GHz high boundary channel frequency */ + // ch = countryInfo[index] + countryInfo[index + 1] - 1; + // if ( ch == 14 ) + // c_hi = ZM_CH_G_14; + // else + // c_hi = ZM_CH_G_1 + (ch - 1) * 5; + // } + // else + // { + // /* calculate 5GHz low boundary channel frequency */ + // ch = countryInfo[index]; + // if ( (ch >= 184)&&(ch <= 196) ) + // c_lo = 4000 + ch*5; + // else + // c_lo = 5000 + ch*5; + // /* calculate 5GHz high boundary channel frequency */ + // ch = countryInfo[index] + countryInfo[index + 1] - 1; + // if ( (ch >= 184)&&(ch <= 196) ) + // c_hi = 4000 + ch*5; + // else + // c_hi = 5000 + ch*5; + // } + // + // zfHpGetRegulationTable(dev, RegDomain, c_lo, c_hi); + // + // index+=3; + //} + + return 0; + } + } + //zm_debug_msg_s("Invalid iso name = ", &countryInfo[2]); + return 1; +} + +const char* zfHpGetisoNamefromregionCode(zdev_t* dev, u16_t regionCode) +{ + u16_t i; + + for (i = 0; i < N(allCountries); i++) + { + if (allCountries[i].regDmnEnum == regionCode) + { + return allCountries[i].isoName; + } + } + /* no matching item, return default */ + return allCountries[0].isoName; +} + +u16_t zfHpGetRegionCodeFromIsoName(zdev_t* dev, u8_t *countryIsoName) +{ + u16_t i; + u16_t regionCode; + + /* if no matching item, return default */ + regionCode = DEF_REGDMN; + + for (i = 0; i < N(allCountries); i++) + { + if (zfMemoryIsEqual((u8_t *)allCountries[i].isoName, countryIsoName, 2)) + { + regionCode = allCountries[i].regDmnEnum; + break; + } + } + + return regionCode; +} + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfHpDeleteAllowChannel */ +/* Delete Allow Channel. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* freq : frequency */ +/* */ +/* OUTPUTS */ +/* 0 : success */ +/* other : fail */ +/* */ +/* AUTHOR */ +/* Chao-Wen Yang ZyDAS Technology Corporation 2007.3 */ +/* */ +/************************************************************************/ +u16_t zfHpDeleteAllowChannel(zdev_t* dev, u16_t freq) +{ + u16_t i, bandIndex = 0; + u16_t dfs5GBand[][2] = {{5150, 5240}, {5260, 5350}, {5450, 5700}, {5725, 5825}}; + + zmw_get_wlan_dev(dev); + /* Find which band does this frequency belong */ + for (i = 0; i < 4; i++) + { + if ((freq >= dfs5GBand[i][0]) && (freq <= dfs5GBand[i][1])) + bandIndex = i + 1; + } + + if (bandIndex == 0) + { + /* 2.4G, don't care */ + return 0; + } + else + { + bandIndex--; + } + /* Set all channels in this band to passive scan */ + for (i = 0; i < wd->regulationTable.allowChannelCnt; i++) + { + if ((wd->regulationTable.allowChannel[i].channel >= dfs5GBand[bandIndex][0]) && + (wd->regulationTable.allowChannel[i].channel <= dfs5GBand[bandIndex][1])) + { + /* if channel is not passive, set it to be passive and mark it */ + if ((wd->regulationTable.allowChannel[i].channelFlags & + ZM_REG_FLAG_CHANNEL_PASSIVE) == 0) + { + wd->regulationTable.allowChannel[i].channelFlags |= + (ZM_REG_FLAG_CHANNEL_PASSIVE | ZM_REG_FLAG_CHANNEL_CSA); + } + } + } + + return 0; +} + +u16_t zfHpAddAllowChannel(zdev_t* dev, u16_t freq) +{ + u16_t i, j, arrayIndex; + + zmw_get_wlan_dev(dev); + + for (i = 0; i < wd->regulationTable.allowChannelCnt; i++) + { + if (wd->regulationTable.allowChannel[i].channel == freq) + break; + } + + if ( i == wd->regulationTable.allowChannelCnt) + { + for (j = 0; j < wd->regulationTable.allowChannelCnt; j++) + { + if (wd->regulationTable.allowChannel[j].channel > freq) + break; + } + + //zm_debug_msg1("CWY - add frequency = ", freq); + //zm_debug_msg1("CWY - channel array index = ", j); + + arrayIndex = j; + + if (arrayIndex < wd->regulationTable.allowChannelCnt) + { + for (j = wd->regulationTable.allowChannelCnt; j > arrayIndex; j--) + wd->regulationTable.allowChannel[j] = wd->regulationTable.allowChannel[j - 1]; + } + wd->regulationTable.allowChannel[arrayIndex].channel = freq; + + wd->regulationTable.allowChannelCnt++; + } + + return 0; +} + +u16_t zfHpIsDfsChannelNCS(zdev_t* dev, u16_t freq) +{ + u8_t flag = ZM_REG_FLAG_CHANNEL_DFS; + u16_t i; + zmw_get_wlan_dev(dev); + + for (i = 0; i < wd->regulationTable.allowChannelCnt; i++) + { + //DbgPrint("DFS:freq=%d, chan=%d", freq, wd->regulationTable.allowChannel[i].channel); + if (wd->regulationTable.allowChannel[i].channel == freq) + { + flag = wd->regulationTable.allowChannel[i].privFlags; + break; + } + } + + return (flag & (ZM_REG_FLAG_CHANNEL_DFS|ZM_REG_FLAG_CHANNEL_DFS_CLEAR)); +} + +u16_t zfHpIsDfsChannel(zdev_t* dev, u16_t freq) +{ + u8_t flag = ZM_REG_FLAG_CHANNEL_DFS; + u16_t i; + zmw_get_wlan_dev(dev); + + zmw_declare_for_critical_section(); + + zmw_enter_critical_section(dev); + + for (i = 0; i < wd->regulationTable.allowChannelCnt; i++) + { + //DbgPrint("DFS:freq=%d, chan=%d", freq, wd->regulationTable.allowChannel[i].channel); + if (wd->regulationTable.allowChannel[i].channel == freq) + { + flag = wd->regulationTable.allowChannel[i].privFlags; + break; + } + } + + zmw_leave_critical_section(dev); + + return (flag & (ZM_REG_FLAG_CHANNEL_DFS|ZM_REG_FLAG_CHANNEL_DFS_CLEAR)); +} + +u16_t zfHpIsAllowedChannel(zdev_t* dev, u16_t freq) +{ + u16_t i; + zmw_get_wlan_dev(dev); + + for (i = 0; i < wd->regulationTable.allowChannelCnt; i++) + { + if (wd->regulationTable.allowChannel[i].channel == freq) + { + return 1; + } + } + + return 0; +} + +u16_t zfHpFindFirstNonDfsChannel(zdev_t* dev, u16_t aBand) +{ + u16_t chan = 2412; + u16_t i; + zmw_get_wlan_dev(dev); + + zmw_declare_for_critical_section(); + + zmw_enter_critical_section(dev); + + for (i = 0; i < wd->regulationTable.allowChannelCnt; i++) + { + if ((wd->regulationTable.allowChannel[i].privFlags & ZM_REG_FLAG_CHANNEL_DFS) != 0) + { + if (aBand) + { + if (wd->regulationTable.allowChannel[i].channel > 3000) + { + chan = wd->regulationTable.allowChannel[i].channel; + break; + } + } + else + { + if (wd->regulationTable.allowChannel[i].channel < 3000) + { + chan = wd->regulationTable.allowChannel[i].channel; + break; + } + } + } + } + + zmw_leave_critical_section(dev); + + return chan; +} + + +/* porting from ACU */ +/* save RegulatoryDomain in hpriv */ +u8_t zfHpGetRegulatoryDomain(zdev_t* dev) +{ + zmw_get_wlan_dev(dev); + + switch (wd->regulationTable.regionCode) + { + case NO_ENUMRD: + return 0; + break; + case FCC1_FCCA: + case FCC1_WORLD: + case FCC4_FCCA: + case FCC5_FCCA: + case FCC2_WORLD: + case FCC2_ETSIC: + case FCC3_FCCA: + case FCC3_WORLD: + case FCC1: + case FCC2: + case FCC3: + case FCC4: + case FCC5: + case FCCA: + return 0x10;//WG_AMERICAS DOT11_REG_DOMAIN_FCC United States + break; + + case FCC2_FCCA: + return 0x20;//DOT11_REG_DOMAIN_DOC Canada + break; + + case ETSI1_WORLD: + case ETSI3_ETSIA: + case ETSI2_WORLD: + case ETSI3_WORLD: + case ETSI4_WORLD: + case ETSI4_ETSIC: + case ETSI5_WORLD: + case ETSI6_WORLD: + case ETSI_RESERVED: + case ETSI1: + case ETSI2: + case ETSI3: + case ETSI4: + case ETSI5: + case ETSI6: + case ETSIA: + case ETSIB: + case ETSIC: + return 0x30;//WG_EMEA DOT11_REG_DOMAIN_ETSI Most of Europe + break; + + case MKK1_MKKA: + case MKK1_MKKB: + case MKK2_MKKA: + case MKK1_FCCA: + case MKK1_MKKA1: + case MKK1_MKKA2: + case MKK1_MKKC: + case MKK3_MKKB: + case MKK3_MKKA2: + case MKK3_MKKC: + case MKK4_MKKB: + case MKK4_MKKA2: + case MKK4_MKKC: + case MKK5_MKKB: + case MKK5_MKKA2: + case MKK5_MKKC: + case MKK6_MKKB: + case MKK6_MKKA2: + case MKK6_MKKC: + case MKK7_MKKB: + case MKK7_MKKA: + case MKK7_MKKC: + case MKK8_MKKB: + case MKK8_MKKA2: + case MKK8_MKKC: + case MKK6_MKKA1: + case MKK6_FCCA: + case MKK7_MKKA1: + case MKK7_FCCA: + case MKK9_FCCA: + case MKK9_MKKA1: + case MKK9_MKKC: + case MKK9_MKKA2: + case MKK10_FCCA: + case MKK10_MKKA1: + case MKK10_MKKC: + case MKK10_MKKA2: + case MKK11_MKKA: + case MKK11_FCCA: + case MKK11_MKKA1: + case MKK11_MKKC: + case MKK11_MKKA2: + case MKK12_MKKA: + case MKK12_FCCA: + case MKK12_MKKA1: + case MKK12_MKKC: + case MKK12_MKKA2: + case MKK3_MKKA: + case MKK3_MKKA1: + case MKK3_FCCA: + case MKK4_MKKA: + case MKK4_MKKA1: + case MKK4_FCCA: + case MKK9_MKKA: + case MKK10_MKKA: + case MKK1: + case MKK2: + case MKK3: + case MKK4: + case MKK5: + case MKK6: + case MKK7: + case MKK8: + case MKK9: + case MKK10: + case MKK11: + case MKK12: + case MKKA: + case MKKC: + return 0x40;//WG_JAPAN DOT11_REG_DOMAIN_MKK Japan + break; + + default: + break; + } + return 0xFF;// Didn't input RegDmn by mean to distinguish by customer + +} + + +void zfHpDisableDfsChannel(zdev_t* dev, u8_t disableFlag) +{ + zmw_get_wlan_dev(dev); + + struct zsHpPriv* hpPriv=wd->hpPrivate; + hpPriv->disableDfsCh = disableFlag; + return; +} diff --git a/drivers/staging/otus/hal/hpreg.h b/drivers/staging/otus/hal/hpreg.h new file mode 100644 index 000000000000..6f8c73fd42cc --- /dev/null +++ b/drivers/staging/otus/hal/hpreg.h @@ -0,0 +1,524 @@ +/* + * Copyright (c) 2000-2005 ZyDAS Technology Corporation + * Copyright (c) 2007-2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +/* Module Name : hpreg.h */ +/* */ +/* Abstract */ +/* This module contains Regulatory Table definitions. */ +/* */ +/* NOTES */ +/* None */ +/* */ +/************************************************************************/ + +#ifndef _HPREG_H +#define _HPREG_H + +typedef u16_t HAL_CTRY_CODE; /* country code */ +typedef u16_t HAL_REG_DOMAIN; /* regulatory domain code */ +typedef enum { + AH_FALSE = 0, /* NB: lots of code assumes false is zero */ + AH_TRUE = 1, +} HAL_BOOL; + + +/* + * Country/Region Codes from MS WINNLS.H + * Numbering from ISO 3166 + */ +enum CountryCode { + CTRY_ALBANIA = 8, /* Albania */ + CTRY_ALGERIA = 12, /* Algeria */ + CTRY_ARGENTINA = 32, /* Argentina */ + CTRY_ARMENIA = 51, /* Armenia */ + CTRY_AUSTRALIA = 36, /* Australia */ + CTRY_AUSTRIA = 40, /* Austria */ + CTRY_AZERBAIJAN = 31, /* Azerbaijan */ + CTRY_BAHRAIN = 48, /* Bahrain */ + CTRY_BELARUS = 112, /* Belarus */ + CTRY_BELGIUM = 56, /* Belgium */ + CTRY_BELIZE = 84, /* Belize */ + CTRY_BOLIVIA = 68, /* Bolivia */ + CTRY_BOSNIA = 70, /* Bosnia */ + CTRY_BRAZIL = 76, /* Brazil */ + CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */ + CTRY_BULGARIA = 100, /* Bulgaria */ + CTRY_CANADA = 124, /* Canada */ + CTRY_CHILE = 152, /* Chile */ + CTRY_CHINA = 156, /* People's Republic of China */ + CTRY_COLOMBIA = 170, /* Colombia */ + CTRY_COSTA_RICA = 188, /* Costa Rica */ + CTRY_CROATIA = 191, /* Croatia */ + CTRY_CYPRUS = 196, /* Cyprus */ + CTRY_CZECH = 203, /* Czech Republic */ + CTRY_DENMARK = 208, /* Denmark */ + CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */ + CTRY_ECUADOR = 218, /* Ecuador */ + CTRY_EGYPT = 818, /* Egypt */ + CTRY_EL_SALVADOR = 222, /* El Salvador */ + CTRY_ESTONIA = 233, /* Estonia */ + CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */ + CTRY_FINLAND = 246, /* Finland */ + CTRY_FRANCE = 250, /* France */ + CTRY_FRANCE2 = 255, /* France2 */ + CTRY_GEORGIA = 268, /* Georgia */ + CTRY_GERMANY = 276, /* Germany */ + CTRY_GREECE = 300, /* Greece */ + CTRY_GUATEMALA = 320, /* Guatemala */ + CTRY_HONDURAS = 340, /* Honduras */ + CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */ + CTRY_HUNGARY = 348, /* Hungary */ + CTRY_ICELAND = 352, /* Iceland */ + CTRY_INDIA = 356, /* India */ + CTRY_INDONESIA = 360, /* Indonesia */ + CTRY_IRAN = 364, /* Iran */ + CTRY_IRAQ = 368, /* Iraq */ + CTRY_IRELAND = 372, /* Ireland */ + CTRY_ISRAEL = 376, /* Israel */ + CTRY_ISRAEL2 = 377, /* Israel2 */ + CTRY_ITALY = 380, /* Italy */ + CTRY_JAMAICA = 388, /* Jamaica */ + CTRY_JAPAN = 392, /* Japan */ + CTRY_JAPAN1 = 393, /* Japan (JP1) */ + CTRY_JAPAN2 = 394, /* Japan (JP0) */ + CTRY_JAPAN3 = 395, /* Japan (JP1-1) */ + CTRY_JAPAN4 = 396, /* Japan (JE1) */ + CTRY_JAPAN5 = 397, /* Japan (JE2) */ + CTRY_JAPAN6 = 399, /* Japan (JP6) */ + + CTRY_JAPAN7 = 4007, /* Japan (J7) */ + CTRY_JAPAN8 = 4008, /* Japan (J8) */ + CTRY_JAPAN9 = 4009, /* Japan (J9) */ + + CTRY_JAPAN10 = 4010, /* Japan (J10) */ + CTRY_JAPAN11 = 4011, /* Japan (J11) */ + CTRY_JAPAN12 = 4012, /* Japan (J12) */ + + CTRY_JAPAN13 = 4013, /* Japan (J13) */ + CTRY_JAPAN14 = 4014, /* Japan (J14) */ + CTRY_JAPAN15 = 4015, /* Japan (J15) */ + + CTRY_JAPAN16 = 4016, /* Japan (J16) */ + CTRY_JAPAN17 = 4017, /* Japan (J17) */ + CTRY_JAPAN18 = 4018, /* Japan (J18) */ + + CTRY_JAPAN19 = 4019, /* Japan (J19) */ + CTRY_JAPAN20 = 4020, /* Japan (J20) */ + CTRY_JAPAN21 = 4021, /* Japan (J21) */ + + CTRY_JAPAN22 = 4022, /* Japan (J22) */ + CTRY_JAPAN23 = 4023, /* Japan (J23) */ + CTRY_JAPAN24 = 4024, /* Japan (J24) */ + + CTRY_JAPAN25 = 4025, /* Japan (J25) */ + CTRY_JAPAN26 = 4026, /* Japan (J26) */ + CTRY_JAPAN27 = 4027, /* Japan (J27) */ + + CTRY_JAPAN28 = 4028, /* Japan (J28) */ + CTRY_JAPAN29 = 4029, /* Japan (J29) */ + CTRY_JAPAN30 = 4030, /* Japan (J30) */ + + CTRY_JAPAN31 = 4031, /* Japan (J31) */ + CTRY_JAPAN32 = 4032, /* Japan (J32) */ + CTRY_JAPAN33 = 4033, /* Japan (J33) */ + + CTRY_JAPAN34 = 4034, /* Japan (J34) */ + CTRY_JAPAN35 = 4035, /* Japan (J35) */ + CTRY_JAPAN36 = 4036, /* Japan (J36) */ + + CTRY_JAPAN37 = 4037, /* Japan (J37) */ + CTRY_JAPAN38 = 4038, /* Japan (J38) */ + CTRY_JAPAN39 = 4039, /* Japan (J39) */ + + CTRY_JAPAN40 = 4040, /* Japan (J40) */ + CTRY_JAPAN41 = 4041, /* Japan (J41) */ + CTRY_JAPAN42 = 4042, /* Japan (J42) */ + CTRY_JAPAN43 = 4043, /* Japan (J43) */ + CTRY_JAPAN44 = 4044, /* Japan (J44) */ + CTRY_JAPAN45 = 4045, /* Japan (J45) */ + CTRY_JAPAN46 = 4046, /* Japan (J46) */ + CTRY_JAPAN47 = 4047, /* Japan (J47) */ + CTRY_JAPAN48 = 4048, /* Japan (J48) */ + CTRY_JAPAN49 = 4049, /* Japan (J49) */ + + CTRY_JAPAN50 = 4050, /* Japan (J50) */ + CTRY_JAPAN51 = 4051, /* Japan (J51) */ + CTRY_JAPAN52 = 4052, /* Japan (J52) */ + CTRY_JAPAN53 = 4053, /* Japan (J53) */ + CTRY_JAPAN54 = 4054, /* Japan (J54) */ + + CTRY_JORDAN = 400, /* Jordan */ + CTRY_KAZAKHSTAN = 398, /* Kazakhstan */ + CTRY_KENYA = 404, /* Kenya */ + CTRY_KOREA_NORTH = 408, /* North Korea */ + CTRY_KOREA_ROC = 410, /* South Korea */ + CTRY_KOREA_ROC2 = 411, /* South Korea */ + CTRY_KOREA_ROC3 = 412, /* South Korea */ + CTRY_KUWAIT = 414, /* Kuwait */ + CTRY_LATVIA = 428, /* Latvia */ + CTRY_LEBANON = 422, /* Lebanon */ + CTRY_LIBYA = 434, /* Libya */ + CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */ + CTRY_LITHUANIA = 440, /* Lithuania */ + CTRY_LUXEMBOURG = 442, /* Luxembourg */ + CTRY_MACAU = 446, /* Macau */ + CTRY_MACEDONIA = 807, /* the Former Yugoslav Republic of Macedonia */ + CTRY_MALAYSIA = 458, /* Malaysia */ + CTRY_MALTA = 470, /* Malta */ + CTRY_MEXICO = 484, /* Mexico */ + CTRY_MONACO = 492, /* Principality of Monaco */ + CTRY_MOROCCO = 504, /* Morocco */ + CTRY_NETHERLANDS = 528, /* Netherlands */ + CTRY_NETHERLANDS_ANT = 530, /* Netherlands-Antellis */ + CTRY_NEW_ZEALAND = 554, /* New Zealand */ + CTRY_NICARAGUA = 558, /* Nicaragua */ + CTRY_NORWAY = 578, /* Norway */ + CTRY_OMAN = 512, /* Oman */ + CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */ + CTRY_PANAMA = 591, /* Panama */ + CTRY_PARAGUAY = 600, /* Paraguay */ + CTRY_PERU = 604, /* Peru */ + CTRY_PHILIPPINES = 608, /* Republic of the Philippines */ + CTRY_POLAND = 616, /* Poland */ + CTRY_PORTUGAL = 620, /* Portugal */ + CTRY_PUERTO_RICO = 630, /* Puerto Rico */ + CTRY_QATAR = 634, /* Qatar */ + CTRY_ROMANIA = 642, /* Romania */ + CTRY_RUSSIA = 643, /* Russia */ + CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */ + CTRY_SERBIA_MONT = 891, /* Serbia and Montenegro */ + CTRY_SINGAPORE = 702, /* Singapore */ + CTRY_SLOVAKIA = 703, /* Slovak Republic */ + CTRY_SLOVENIA = 705, /* Slovenia */ + CTRY_SOUTH_AFRICA = 710, /* South Africa */ + CTRY_SPAIN = 724, /* Spain */ + CTRY_SRILANKA = 144, /* Srilanka */ + CTRY_SWEDEN = 752, /* Sweden */ + CTRY_SWITZERLAND = 756, /* Switzerland */ + CTRY_SYRIA = 760, /* Syria */ + CTRY_TAIWAN = 158, /* Taiwan */ + CTRY_THAILAND = 764, /* Thailand */ + CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */ + CTRY_TUNISIA = 788, /* Tunisia */ + CTRY_TURKEY = 792, /* Turkey */ + CTRY_UAE = 784, /* U.A.E. */ + CTRY_UKRAINE = 804, /* Ukraine */ + CTRY_UNITED_KINGDOM = 826, /* United Kingdom */ + CTRY_UNITED_STATES = 840, /* United States */ + CTRY_UNITED_STATES_FCC49 = 842, /* United States (Public Safety)*/ + CTRY_URUGUAY = 858, /* Uruguay */ + CTRY_UZBEKISTAN = 860, /* Uzbekistan */ + CTRY_VENEZUELA = 862, /* Venezuela */ + CTRY_VIET_NAM = 704, /* Viet Nam */ + CTRY_YEMEN = 887, /* Yemen */ + CTRY_ZIMBABWE = 716 /* Zimbabwe */ +}; + +/* Enumerated Regulatory Domain Information 8 bit values indicate that + * the regdomain is really a pair of unitary regdomains. 12 bit values + * are the real unitary regdomains and are the only ones which have the + * frequency bitmasks and flags set. + */ +enum EnumRd { + /* + * The following regulatory domain definitions are + * found in the EEPROM. Each regulatory domain + * can operate in either a 5GHz or 2.4GHz wireless mode or + * both 5GHz and 2.4GHz wireless modes. + * In general, the value holds no special + * meaning and is used to decode into either specific + * 2.4GHz or 5GHz wireless mode for that particular + * regulatory domain. + */ + NO_ENUMRD = 0x00, + NULL1_WORLD = 0x03, /* For 11b-only countries (no 11a allowed) */ + NULL1_ETSIB = 0x07, /* Israel */ + NULL1_ETSIC = 0x08, + FCC1_FCCA = 0x10, /* USA */ + FCC1_WORLD = 0x11, /* Hong Kong */ + FCC4_FCCA = 0x12, /* USA - Public Safety */ + FCC5_FCCA = 0x13, /* USA - with no DFS (UNII-1 + UNII-3 only) */ + FCC6_FCCA = 0x14, /* Canada */ + + FCC2_FCCA = 0x20, /* Canada */ + FCC2_WORLD = 0x21, /* Australia & HK */ + FCC2_ETSIC = 0x22, + FCC6_WORLD = 0x23, /* Australia */ + + FRANCE_RES = 0x31, /* Legacy France for OEM */ + FCC3_FCCA = 0x3A, /* USA & Canada w/5470 band, 11h, DFS enabled */ + FCC3_WORLD = 0x3B, /* USA & Canada w/5470 band, 11h, DFS enabled */ + + ETSI1_WORLD = 0x37, + ETSI3_ETSIA = 0x32, /* France (optional) */ + ETSI2_WORLD = 0x35, /* Hungary & others */ + ETSI3_WORLD = 0x36, /* France & others */ + ETSI4_WORLD = 0x30, + ETSI4_ETSIC = 0x38, + ETSI5_WORLD = 0x39, + ETSI6_WORLD = 0x34, /* Bulgaria */ + ETSI_RESERVED = 0x33, /* Reserved (Do not used) */ + + MKK1_MKKA = 0x40, /* Japan (JP1) */ + MKK1_MKKB = 0x41, /* Japan (JP0) */ + APL4_WORLD = 0x42, /* Singapore */ + MKK2_MKKA = 0x43, /* Japan with 4.9G channels */ + APL_RESERVED = 0x44, /* Reserved (Do not used) */ + APL2_WORLD = 0x45, /* Korea */ + APL2_APLC = 0x46, + APL3_WORLD = 0x47, + MKK1_FCCA = 0x48, /* Japan (JP1-1) */ + APL2_APLD = 0x49, /* Korea with 2.3G channels */ + MKK1_MKKA1 = 0x4A, /* Japan (JE1) */ + MKK1_MKKA2 = 0x4B, /* Japan (JE2) */ + MKK1_MKKC = 0x4C, /* Japan (MKK1_MKKA,except Ch14) */ + + APL3_FCCA = 0x50, + APL1_WORLD = 0x52, /* Latin America */ + APL1_FCCA = 0x53, + APL1_APLA = 0x54, + APL1_ETSIC = 0x55, + APL2_ETSIC = 0x56, /* Venezuela */ + APL2_FCCA = 0x57, /* new Latin America */ + APL5_WORLD = 0x58, /* Chile */ + APL6_WORLD = 0x5B, /* Singapore */ + APL7_FCCA = 0x5C, /* Taiwan 5.47 Band */ + APL8_WORLD = 0x5D, /* Malaysia 5GHz */ + APL9_WORLD = 0x5E, /* Korea 5GHz */ + + /* + * World mode SKUs + */ + WOR0_WORLD = 0x60, /* World0 (WO0 SKU) */ + WOR1_WORLD = 0x61, /* World1 (WO1 SKU) */ + WOR2_WORLD = 0x62, /* World2 (WO2 SKU) */ + WOR3_WORLD = 0x63, /* World3 (WO3 SKU) */ + WOR4_WORLD = 0x64, /* World4 (WO4 SKU) */ + WOR5_ETSIC = 0x65, /* World5 (WO5 SKU) */ + + WOR01_WORLD = 0x66, /* World0-1 (WW0-1 SKU) */ + WOR02_WORLD = 0x67, /* World0-2 (WW0-2 SKU) */ + EU1_WORLD = 0x68, /* Same as World0-2 (WW0-2 SKU), except active scan ch1-13. No ch14 */ + + WOR9_WORLD = 0x69, /* World9 (WO9 SKU) */ + WORA_WORLD = 0x6A, /* WorldA (WOA SKU) */ + + MKK3_MKKB = 0x80, /* Japan UNI-1 even + MKKB */ + MKK3_MKKA2 = 0x81, /* Japan UNI-1 even + MKKA2 */ + MKK3_MKKC = 0x82, /* Japan UNI-1 even + MKKC */ + + MKK4_MKKB = 0x83, /* Japan UNI-1 even + UNI-2 + MKKB */ + MKK4_MKKA2 = 0x84, /* Japan UNI-1 even + UNI-2 + MKKA2 */ + MKK4_MKKC = 0x85, /* Japan UNI-1 even + UNI-2 + MKKC */ + + MKK5_MKKB = 0x86, /* Japan UNI-1 even + UNI-2 + mid-band + MKKB */ + MKK5_MKKA2 = 0x87, /* Japan UNI-1 even + UNI-2 + mid-band + MKKA2 */ + MKK5_MKKC = 0x88, /* Japan UNI-1 even + UNI-2 + mid-band + MKKC */ + + MKK6_MKKB = 0x89, /* Japan UNI-1 even + UNI-1 odd MKKB */ + MKK6_MKKA2 = 0x8A, /* Japan UNI-1 even + UNI-1 odd + MKKA2 */ + MKK6_MKKC = 0x8B, /* Japan UNI-1 even + UNI-1 odd + MKKC */ + + MKK7_MKKB = 0x8C, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + MKKB */ + MKK7_MKKA = 0x8D, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + MKKA2 */ + MKK7_MKKC = 0x8E, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + MKKC */ + + MKK8_MKKB = 0x8F, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + MKKB */ + MKK8_MKKA2 = 0x90, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + MKKA2 */ + MKK8_MKKC = 0x91, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + MKKC */ + + MKK6_MKKA1 = 0xF8, /* Japan UNI-1 even + UNI-1 odd + MKKA1 */ + MKK6_FCCA = 0xF9, /* Japan UNI-1 even + UNI-1 odd + FCCA */ + MKK7_MKKA1 = 0xFA, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + MKKA1 */ + MKK7_FCCA = 0xFB, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + FCCA */ + MKK9_FCCA = 0xFC, /* Japan UNI-1 even + 4.9GHz + FCCA */ + MKK9_MKKA1 = 0xFD, /* Japan UNI-1 even + 4.9GHz + MKKA1 */ + MKK9_MKKC = 0xFE, /* Japan UNI-1 even + 4.9GHz + MKKC */ + MKK9_MKKA2 = 0xFF, /* Japan UNI-1 even + 4.9GHz + MKKA2 */ + + MKK10_FCCA = 0xD0, /* Japan UNI-1 even + UNI-2 + 4.9GHz + FCCA */ + MKK10_MKKA1 = 0xD1, /* Japan UNI-1 even + UNI-2 + 4.9GHz + MKKA1 */ + MKK10_MKKC = 0xD2, /* Japan UNI-1 even + UNI-2 + 4.9GHz + MKKC */ + MKK10_MKKA2 = 0xD3, /* Japan UNI-1 even + UNI-2 + 4.9GHz + MKKA2 */ + + MKK11_MKKA = 0xD4, /* Japan UNI-1 even + UNI-2 + Midband + 4.9GHz + MKKA */ + MKK11_FCCA = 0xD5, /* Japan UNI-1 even + UNI-2 + Midband + 4.9GHz + FCCA */ + MKK11_MKKA1 = 0xD6, /* Japan UNI-1 even + UNI-2 + Midband + 4.9GHz + MKKA1 */ + MKK11_MKKC = 0xD7, /* Japan UNI-1 even + UNI-2 + Midband + 4.9GHz + MKKC */ + MKK11_MKKA2 = 0xD8, /* Japan UNI-1 even + UNI-2 + Midband + 4.9GHz + MKKA2 */ + + MKK12_MKKA = 0xD9, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + Midband + 4.9GHz + MKKA */ + MKK12_FCCA = 0xDA, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + Midband + 4.9GHz + FCCA */ + MKK12_MKKA1 = 0xDB, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + Midband + 4.9GHz + MKKA1 */ + MKK12_MKKC = 0xDC, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + Midband + 4.9GHz + MKKC */ + MKK12_MKKA2 = 0xDD, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + Midband + 4.9GHz + MKKA2 */ + + /* Following definitions are used only by s/w to map old + * Japan SKUs. + */ + MKK3_MKKA = 0xF0, /* Japan UNI-1 even + MKKA */ + MKK3_MKKA1 = 0xF1, /* Japan UNI-1 even + MKKA1 */ + MKK3_FCCA = 0xF2, /* Japan UNI-1 even + FCCA */ + MKK4_MKKA = 0xF3, /* Japan UNI-1 even + UNI-2 + MKKA */ + MKK4_MKKA1 = 0xF4, /* Japan UNI-1 even + UNI-2 + MKKA1 */ + MKK4_FCCA = 0xF5, /* Japan UNI-1 even + UNI-2 + FCCA */ + MKK9_MKKA = 0xF6, /* Japan UNI-1 even + 4.9GHz + MKKA*/ + MKK10_MKKA = 0xF7, /* Japan UNI-1 even + UNI-2 + 4.9GHz + MKKA */ + + /* + * Regulator domains ending in a number (e.g. APL1, + * MK1, ETSI4, etc) apply to 5GHz channel and power + * information. Regulator domains ending in a letter + * (e.g. APLA, FCCA, etc) apply to 2.4GHz channel and + * power information. + */ + APL1 = 0x0150, /* LAT & Asia */ + APL2 = 0x0250, /* LAT & Asia */ + APL3 = 0x0350, /* Taiwan */ + APL4 = 0x0450, /* Jordan */ + APL5 = 0x0550, /* Chile */ + APL6 = 0x0650, /* Singapore */ + APL7 = 0x0750, /* Taiwan Middle */ + APL8 = 0x0850, /* Malaysia */ + APL9 = 0x0950, /* Korea (South) ROC 3 */ + + ETSI1 = 0x0130, /* Europe & others */ + ETSI2 = 0x0230, /* Europe & others */ + ETSI3 = 0x0330, /* Europe & others */ + ETSI4 = 0x0430, /* Europe & others */ + ETSI5 = 0x0530, /* Europe & others */ + ETSI6 = 0x0630, /* Europe & others */ + ETSIA = 0x0A30, /* France */ + ETSIB = 0x0B30, /* Israel */ + ETSIC = 0x0C30, /* Latin America */ + + FCC1 = 0x0110, /* US & others */ + FCC2 = 0x0120, /* Canada, Australia & New Zealand */ + FCC3 = 0x0160, /* US w/new middle band & DFS */ + FCC4 = 0x0165, /* US Public Safety */ + FCC5 = 0x0510, /* US no DFS */ + FCC6 = 0x0610, /* Canada & Australia */ + + FCCA = 0x0A10, + + APLD = 0x0D50, /* South Korea */ + + MKK1 = 0x0140, /* Japan (UNI-1 odd)*/ + MKK2 = 0x0240, /* Japan (4.9 GHz + UNI-1 odd) */ + MKK3 = 0x0340, /* Japan (UNI-1 even) */ + MKK4 = 0x0440, /* Japan (UNI-1 even + UNI-2) */ + MKK5 = 0x0540, /* Japan (UNI-1 even + UNI-2 + mid-band) */ + MKK6 = 0x0640, /* Japan (UNI-1 odd + UNI-1 even) */ + MKK7 = 0x0740, /* Japan (UNI-1 odd + UNI-1 even + UNI-2 */ + MKK8 = 0x0840, /* Japan (UNI-1 odd + UNI-1 even + UNI-2 + mid-band) */ + MKK9 = 0x0940, /* Japan (UNI-1 even + 4.9 GHZ) */ + MKK10 = 0x0B40, /* Japan (UNI-1 even + UNI-2 + 4.9 GHZ) */ + MKK11 = 0x1140, /* Japan (UNI-1 even + UNI-2 + mid-band + 4.9 GHZ) */ + MKK12 = 0x1240, /* Japan (UNI-1 even + UNI-1 odd + UNI-2 + mid-band + 4.9 GHZ) */ + MKKA = 0x0A40, /* Japan */ + MKKC = 0x0A50, + + NULL1 = 0x0198, + WORLD = 0x0199, + DEBUG_REG_DMN = 0x01ff, +}; + +/* channelFlags */ +#define ZM_REG_FLAG_CHANNEL_CW_INT 0x0002 /* CW interference detected on channel */ +#define ZM_REG_FLAG_CHANNEL_TURBO 0x0010 /* Turbo Channel */ +#define ZM_REG_FLAG_CHANNEL_CCK 0x0020 /* CCK channel */ +#define ZM_REG_FLAG_CHANNEL_OFDM 0x0040 /* OFDM channel */ +#define ZM_REG_FLAG_CHANNEL_2GHZ 0x0080 /* 2 GHz spectrum channel. */ +#define ZM_REG_FLAG_CHANNEL_5GHZ 0x0100 /* 5 GHz spectrum channel */ +#define ZM_REG_FLAG_CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed in the channel */ +#define ZM_REG_FLAG_CHANNEL_DYN 0x0400 /* dynamic CCK-OFDM channel */ +#define ZM_REG_FLAG_CHANNEL_XR 0x0800 /* XR channel */ +#define ZM_REG_FLAG_CHANNEL_CSA 0x1000 /* Channel by CSA(Channel Switch Announcement) */ +#define ZM_REG_FLAG_CHANNEL_STURBO 0x2000 /* Static turbo, no 11a-only usage */ +#define ZM_REG_FLAG_CHANNEL_HALF 0x4000 /* Half rate channel */ +#define ZM_REG_FLAG_CHANNEL_QUARTER 0x8000 /* Quarter rate channel */ + +/* channelFlags */ +#define CHANNEL_CW_INT 0x0002 /* CW interference detected on channel */ +#define CHANNEL_TURBO 0x0010 /* Turbo Channel */ +#define CHANNEL_CCK 0x0020 /* CCK channel */ +#define CHANNEL_OFDM 0x0040 /* OFDM channel */ +#define CHANNEL_2GHZ 0x0080 /* 2 GHz spectrum channel. */ +#define CHANNEL_5GHZ 0x0100 /* 5 GHz spectrum channel */ +#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed in the channel */ +#define CHANNEL_DYN 0x0400 /* dynamic CCK-OFDM channel */ +#define CHANNEL_XR 0x0800 /* XR channel */ +#define CHANNEL_STURBO 0x2000 /* Static turbo, no 11a-only usage */ +#define CHANNEL_HALF 0x4000 /* Half rate channel */ +#define CHANNEL_QUARTER 0x8000 /* Quarter rate channel */ +#define CHANNEL_HT20 0x10000 /* HT20 channel */ +#define CHANNEL_HT40 0x20000 /* HT40 channel */ +#define CHANNEL_HT40U 0x40000 /* control channel can be upper channel */ +#define CHANNEL_HT40L 0x80000 /* control channel can be lower channel */ + +/* privFlags */ +#define ZM_REG_FLAG_CHANNEL_INTERFERENCE 0x01 /* Software use: channel interference + used for as AR as well as RADAR + interference detection */ +#define ZM_REG_FLAG_CHANNEL_DFS 0x02 /* DFS required on channel */ +#define ZM_REG_FLAG_CHANNEL_4MS_LIMIT 0x04 /* 4msec packet limit on this channel */ +#define ZM_REG_FLAG_CHANNEL_DFS_CLEAR 0x08 /* if channel has been checked for DFS */ + +#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) +#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) +#define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM) +#ifdef notdef +#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_DYN) +#else +#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) +#endif +#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) +#define CHANNEL_ST (CHANNEL_T|CHANNEL_STURBO) +#define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) +#define CHANNEL_108A CHANNEL_T +#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) +#define CHANNEL_G_HT (CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_HT20) +#define CHANNEL_A_HT (CHANNEL_5GHZ | CHANNEL_OFDM | CHANNEL_HT20) + +#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) +#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) +#define CHANNEL_G_HT40 (CHANNEL_2GHZ|CHANNEL_HT20|CHANNEL_HT40) +#define CHANNEL_A_HT40 (CHANNEL_5GHZ|CHANNEL_HT20|CHANNEL_HT40) +#define CHANNEL_ALL \ + (CHANNEL_OFDM|CHANNEL_CCK| CHANNEL_2GHZ | CHANNEL_5GHZ | CHANNEL_TURBO | CHANNEL_HT20 | CHANNEL_HT40) +#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO) + +enum { + HAL_MODE_11A = 0x001, /* 11a channels */ + HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ + HAL_MODE_11B = 0x004, /* 11b channels */ + HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ +#ifdef notdef + HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ +#else + HAL_MODE_11G = 0x008, /* XXX historical */ +#endif + HAL_MODE_108G = 0x020, /* 11a+Turbo channels */ + HAL_MODE_108A = 0x040, /* 11g+Turbo channels */ + HAL_MODE_XR = 0x100, /* XR channels */ + HAL_MODE_11A_HALF_RATE = 0x200, /* 11A half rate channels */ + HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11A quarter rate channels */ + HAL_MODE_11NG = 0x4000, /* 11ng channels */ + HAL_MODE_11NA = 0x8000, /* 11na channels */ + HAL_MODE_ALL = 0xffff +}; + +#endif /* #ifndef _HPREG_H */ diff --git a/drivers/staging/otus/hal/hprw.c b/drivers/staging/otus/hal/hprw.c new file mode 100644 index 000000000000..db7d49576456 --- /dev/null +++ b/drivers/staging/otus/hal/hprw.c @@ -0,0 +1,1557 @@ +/* + * Copyright (c) 2007-2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include "../80211core/cprecomp.h" +#include "hpani.h" +#include "hpusb.h" +#include "hpreg.h" +#include "../80211core/ratectrl.h" + +extern void zfIdlCmd(zdev_t* dev, u32_t* cmd, u16_t cmdLen); + +extern void zfCoreCwmBusy(zdev_t* dev, u16_t busy); +u16_t zfDelayWriteInternalReg(zdev_t* dev, u32_t addr, u32_t val); +u16_t zfFlushDelayWrite(zdev_t* dev); + +//#define zm_hp_priv(x) struct zsHpPriv* hpPriv=zgWlanDev.hpPrivate; + +void zfInitCmdQueue(zdev_t* dev) +{ + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv = (struct zsHpPriv*)(wd->hpPrivate); + + zmw_declare_for_critical_section(); + + zmw_enter_critical_section(dev); +#ifdef ZM_XP_USB_MULTCMD + hpPriv->cmdTail = hpPriv->cmdHead = hpPriv->cmdSend = 0; +#else + hpPriv->cmdTail = hpPriv->cmdHead = 0; +#endif + hpPriv->cmdPending = 0; + hpPriv->cmd.delayWcmdCount = 0; + zmw_leave_critical_section(dev); +} + +u16_t zfPutCmd(zdev_t* dev, u32_t* cmd, u16_t cmdLen, u16_t src, u8_t* buf) +{ + u16_t i; + + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv=wd->hpPrivate; + + /* Make sure command length < ZM_MAX_CMD_SIZE */ + zm_assert(cmdLen <= ZM_MAX_CMD_SIZE); + /* Make sure command queue not full */ + //zm_assert(((hpPriv->cmdTail+1) & (ZM_CMD_QUEUE_SIZE-1)) != hpPriv->cmdHead); + if (((hpPriv->cmdTail+1) & (ZM_CMD_QUEUE_SIZE-1)) == hpPriv->cmdHead ) { + zm_debug_msg0("CMD queue full!!"); + return 0; + } + + hpPriv->cmdQ[hpPriv->cmdTail].cmdLen = cmdLen; + hpPriv->cmdQ[hpPriv->cmdTail].src = src; + hpPriv->cmdQ[hpPriv->cmdTail].buf = buf; + for (i=0; i<(cmdLen>>2); i++) + { + hpPriv->cmdQ[hpPriv->cmdTail].cmd[i] = cmd[i]; + } + + hpPriv->cmdTail = (hpPriv->cmdTail+1) & (ZM_CMD_QUEUE_SIZE-1); + + return 0; +} + +u16_t zfGetCmd(zdev_t* dev, u32_t* cmd, u16_t* cmdLen, u16_t* src, u8_t** buf) +{ + u16_t i; + + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv=wd->hpPrivate; + + if (hpPriv->cmdTail == hpPriv->cmdHead) + { + return 3; + } + + *cmdLen = hpPriv->cmdQ[hpPriv->cmdHead].cmdLen; + *src = hpPriv->cmdQ[hpPriv->cmdHead].src; + *buf = hpPriv->cmdQ[hpPriv->cmdHead].buf; + for (i=0; i<((*cmdLen)>>2); i++) + { + cmd[i] = hpPriv->cmdQ[hpPriv->cmdHead].cmd[i]; + } + + hpPriv->cmdHead = (hpPriv->cmdHead+1) & (ZM_CMD_QUEUE_SIZE-1); + + return 0; +} + +#ifdef ZM_XP_USB_MULTCMD +void zfSendCmdEx(zdev_t* dev) +{ + u32_t ncmd[ZM_MAX_CMD_SIZE/4]; + u16_t ncmdLen = 0; + u16_t cmdFlag = 0; + u16_t i; + + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv=wd->hpPrivate; + + zmw_declare_for_critical_section(); + + zmw_enter_critical_section(dev); + + if (hpPriv->cmdPending == 0) + { + if (hpPriv->cmdTail != hpPriv->cmdSend) + { + cmdFlag = 1; + /* Get queueing command */ + ncmdLen= hpPriv->cmdQ[hpPriv->cmdSend].cmdLen; + for (i=0; i<(ncmdLen>>2); i++) + { + ncmd[i] = hpPriv->cmdQ[hpPriv->cmdSend].cmd[i]; + } + hpPriv->cmdSend = (hpPriv->cmdSend+1) & (ZM_CMD_QUEUE_SIZE-1); + + hpPriv->cmdPending = 1; + } + } + + zmw_leave_critical_section(dev); + + if ((cmdFlag == 1)) + { + zfIdlCmd(dev, ncmd, ncmdLen); + } +} + +void zfiSendCmdComp(zdev_t* dev) +{ + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv=wd->hpPrivate; + + zmw_declare_for_critical_section(); + + zmw_enter_critical_section(dev); + hpPriv->cmdPending = 0; + zmw_leave_critical_section(dev); + + zfSendCmdEx(dev); +} +#endif + +u16_t zfIssueCmd(zdev_t* dev, u32_t* cmd, u16_t cmdLen, u16_t src, u8_t* buf) +{ + u16_t cmdFlag = 0; + u16_t ret; + + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv=wd->hpPrivate; + + zmw_declare_for_critical_section(); + + zm_msg2_mm(ZM_LV_1, "cmdLen=", cmdLen); + + zmw_enter_critical_section(dev); + +#ifdef ZM_XP_USB_MULTCMD + ret = zfPutCmd(dev, cmd, cmdLen, src, buf); + zmw_leave_critical_section(dev); + + if (ret != 0) + { + return 1; + } + + zfSendCmdEx(dev); +#else + if (hpPriv->cmdPending == 0) + { + hpPriv->cmdPending = 1; + cmdFlag = 1; + } + ret = zfPutCmd(dev, cmd, cmdLen, src, buf); + + zmw_leave_critical_section(dev); + + if (ret != 0) + { + return 1; + } + + if (cmdFlag == 1) + { + zfIdlCmd(dev, cmd, cmdLen); + } +#endif + return 0; +} + +void zfIdlRsp(zdev_t* dev, u32_t* rsp, u16_t rspLen) +{ + u32_t cmd[ZM_MAX_CMD_SIZE/4]; + u16_t cmdLen; + u16_t src; + u8_t* buf; + u32_t ncmd[ZM_MAX_CMD_SIZE/4]; + u16_t ncmdLen = 0; + u16_t ret; + u16_t cmdFlag = 0; + u16_t i; + s32_t nf; + s32_t noisefloor[4]; + + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv=wd->hpPrivate; + + + zmw_declare_for_critical_section(); + + zmw_enter_critical_section(dev); + + ret = zfGetCmd(dev, cmd, &cmdLen, &src, &buf); + #if 0 + zm_assert(ret == 0); + #else + if (ret != 0) + { + zm_debug_msg0("Error IdlRsp because none cmd!!\n"); + #ifndef ZM_XP_USB_MULTCMD + zmw_leave_critical_section(dev); + return; + #endif + } + #endif +#ifdef ZM_XP_USB_MULTCMD + zmw_leave_critical_section(dev); +#else + if (hpPriv->cmdTail != hpPriv->cmdHead) + { + cmdFlag = 1; + /* Get queueing command */ + ncmdLen= hpPriv->cmdQ[hpPriv->cmdHead].cmdLen; + for (i=0; i<(ncmdLen>>2); i++) + { + ncmd[i] = hpPriv->cmdQ[hpPriv->cmdHead].cmd[i]; + } + } + else + { + hpPriv->cmdPending = 0; + } + + zmw_leave_critical_section(dev); + + if (cmdFlag == 1) + { + zfIdlCmd(dev, ncmd, ncmdLen); + } +#endif + if (src == ZM_OID_READ) + { + ZM_PERFORMANCE_REG(dev, 0x11772c, rsp[1]); + zfwDbgReadRegDone(dev, cmd[1], rsp[1]); + } + else if (src == ZM_OID_FLASH_CHKSUM) + { + zfwDbgGetFlashChkSumDone(dev, rsp+1); + } + else if (src == ZM_OID_FLASH_READ) + { + u32_t datalen; + u16_t i; + + datalen = (rsp[0] & 255); + + zfwDbgReadFlashDone(dev, cmd[1], rsp+1, datalen); + } + else if (src == ZM_OID_FLASH_PROGRAM) + { + /* Non do */ + } + else if (src == ZM_OID_WRITE) + { + zfwDbgWriteRegDone(dev, cmd[1], cmd[2]); + } + else if (src == ZM_OID_TALLY) + { + zfCollectHWTally(dev, rsp, 0); + } + else if (src == ZM_OID_TALLY_APD) + { + zfCollectHWTally(dev, rsp, 1); + zfwDbgReadTallyDone(dev); +#ifdef ZM_ENABLE_BA_RATECTRL + zfRateCtrlAggrSta(dev); +#endif + } + else if (src == ZM_OID_DKTX_STATUS) + { + zm_debug_msg0("src = zm_OID_DKTX_STATUS"); + zfwDbgQueryHwTxBusyDone(dev, rsp[1]); + } + else if (src == ZM_CMD_SET_FREQUENCY) + { + +//#ifdef ZM_OTUS_ENABLE_RETRY_FREQ_CHANGE +#if 0 + zm_debug_msg1("Retry Set Frequency = ", rsp[1]); + + #if 1 + // Read the Noise Floor value ! + nf = ((rsp[2]>>19) & 0x1ff); + if ((nf & 0x100) != 0x0) + { + noisefloor[0] = 0 - ((nf ^ 0x1ff) + 1); + } + else + { + noisefloor[0] = nf; + } + + zm_debug_msg1("Noise Floor[1] = ", noisefloor[0]); + + nf = ((rsp[3]>>19) & 0x1ff); + if ((nf & 0x100) != 0x0) + { + noisefloor[1] = 0 - ((nf ^ 0x1ff) + 1); + } + else + { + noisefloor[1] = nf; + } + + zm_debug_msg1("Noise Floor[2] = ", noisefloor[1]); + zm_debug_msg1("Is Site Survey = ", hpPriv->isSiteSurvey); + #endif + + if ( (rsp[1] && hpPriv->freqRetryCounter == 0) || + (((noisefloor[0]>-60)||(noisefloor[1]>-60)) && hpPriv->freqRetryCounter==0) || + ((abs(noisefloor[0]-noisefloor[1])>=9) && hpPriv->freqRetryCounter==0) ) + { + zm_debug_msg0("Retry to issue the frequency change command"); + + if ( hpPriv->recordFreqRetryCounter == 1 ) + { + zm_debug_msg0("Cold Reset"); + + zfHpSetFrequencyEx(dev, hpPriv->latestFrequency, + hpPriv->latestBw40, + hpPriv->latestExtOffset, + 2); + + if ( hpPriv->isSiteSurvey != 2 ) + { + hpPriv->freqRetryCounter++; + } + hpPriv->recordFreqRetryCounter = 0; + } + else + { + zfHpSetFrequencyEx(dev, hpPriv->latestFrequency, + hpPriv->latestBw40, + hpPriv->latestExtOffset, + 0); + } + hpPriv->recordFreqRetryCounter++; + } + else +#endif + +/* ret: Bit0: AGC calibration 0=>finish 1=>unfinish */ +/* Bit1: Noise calibration 0=>finish 1=>unfinish */ +/* Bit2: Noise calibration finish, but NF value unexcepted => 1 */ + if ( (rsp[1] & 0x1) || (rsp[1] & 0x4) ) + { + zm_debug_msg1("Set Frequency fail : ret = ", rsp[1]); + + /* 1. AGC Calibration fail */ + /* 2. Noise Calibration finish but error NoiseFloor value */ + /* and not in sitesurvey, try more twice */ + if ( hpPriv->isSiteSurvey == 2 ) + { + if ( hpPriv->recordFreqRetryCounter < 2 ) + { + /* cold reset */ + zfHpSetFrequencyEx(dev, hpPriv->latestFrequency, + hpPriv->latestBw40, + hpPriv->latestExtOffset, + 2); + hpPriv->recordFreqRetryCounter++; + zm_debug_msg1("Retry to issue the frequency change command(cold reset) counter = ", hpPriv->recordFreqRetryCounter); + } + else + { + /* Fail : we would not accept this result! */ + zm_debug_msg0("\n\n\n\n Fail twice cold reset \n\n\n\n"); + hpPriv->coldResetNeedFreq = 0; + hpPriv->recordFreqRetryCounter = 0; + zfCoreSetFrequencyComplete(dev); + } + } + else + { + /* in sitesurvey, coldreset in next channel */ + hpPriv->coldResetNeedFreq = 1; + hpPriv->recordFreqRetryCounter = 0; + zfCoreSetFrequencyComplete(dev); + } + } + else if (rsp[1] & 0x2) + { + zm_debug_msg1("Set Frequency fail 2 : ret = ", rsp[1]); + + /* Noise Calibration un-finish */ + /* and not in sitesurvey, try more once */ + if ( hpPriv->isSiteSurvey == 2 ) + { + if ( hpPriv->recordFreqRetryCounter < 1 ) + { + /* cold reset */ + zfHpSetFrequencyEx(dev, hpPriv->latestFrequency, + hpPriv->latestBw40, + hpPriv->latestExtOffset, + 2); + hpPriv->recordFreqRetryCounter++; + zm_debug_msg1("2 Retry to issue the frequency change command(cold reset) counter = ", hpPriv->recordFreqRetryCounter); + } + else + { + /* Fail : we would not accept this result! */ + zm_debug_msg0("\n\n\n\n 2 Fail twice cold reset \n\n\n\n"); + hpPriv->coldResetNeedFreq = 0; + hpPriv->recordFreqRetryCounter = 0; + zfCoreSetFrequencyComplete(dev); + } + } + else + { + /* in sitesurvey, skip this frequency */ + hpPriv->coldResetNeedFreq = 0; + hpPriv->recordFreqRetryCounter = 0; + zfCoreSetFrequencyComplete(dev); + } + } + //else if (rsp[1] & 0x4) + //{ + // zm_debug_msg1("Set Frequency fail 3 : ret = ", rsp[1]); + // hpPriv->coldResetNeedFreq = 0; + // hpPriv->recordFreqRetryCounter = 0; + // zfCoreSetFrequencyComplete(dev); + //} + else + { + //hpPriv->freqRetryCounter = 0; + zm_debug_msg2(" return complete, ret = ", rsp[1]); + + /* set bb_heavy_clip_enable */ + if (hpPriv->enableBBHeavyClip && hpPriv->hwBBHeavyClip && + hpPriv->doBBHeavyClip) + { + u32_t setValue = 0x200; + + setValue |= hpPriv->setValueHeavyClip; + + //zm_dbg(("Do heavy clip setValue = %d\n", setValue)); + + zfDelayWriteInternalReg(dev, 0x99e0+0x1bc000, setValue); + zfFlushDelayWrite(dev); + } + + hpPriv->coldResetNeedFreq = 0; + hpPriv->recordFreqRetryCounter = 0; + zfCoreSetFrequencyComplete(dev); + } + + #if 1 + // Read the Noise Floor value ! + nf = ((rsp[2]>>19) & 0x1ff); + if ((nf & 0x100) != 0x0) + { + noisefloor[0] = 0 - ((nf ^ 0x1ff) + 1); + } + else + { + noisefloor[0] = nf; + } + + //zm_debug_msg1("Noise Floor[1] = ", noisefloor[0]); + + nf = ((rsp[3]>>19) & 0x1ff); + if ((nf & 0x100) != 0x0) + { + noisefloor[1] = 0 - ((nf ^ 0x1ff) + 1); + } + else + { + noisefloor[1] = nf; + } + + //zm_debug_msg1("Noise Floor[2] = ", noisefloor[1]); + + nf = ((rsp[5]>>23) & 0x1ff); + if ((nf & 0x100) != 0x0) + { + noisefloor[2] = 0 - ((nf ^ 0x1ff) + 1); + } + else + { + noisefloor[2] = nf; + } + + //zm_debug_msg1("Noise Floor ext[1] = ", noisefloor[2]); + + nf = ((rsp[6]>>23) & 0x1ff); + if ((nf & 0x100) != 0x0) + { + noisefloor[3] = 0 - ((nf ^ 0x1ff) + 1); + } + else + { + noisefloor[3] = nf; + } + + //zm_debug_msg1("Noise Floor ext[2] = ", noisefloor[3]); + + //zm_debug_msg1("Is Site Survey = ", hpPriv->isSiteSurvey); + #endif + } + else if (src == ZM_CMD_SET_KEY) + { + zfCoreSetKeyComplete(dev); + } + else if (src == ZM_CWM_READ) + { + zm_msg2_mm(ZM_LV_0, "CWM rsp[1]=", rsp[1]); + zm_msg2_mm(ZM_LV_0, "CWM rsp[2]=", rsp[2]); + zfCoreCwmBusy(dev, zfCwmIsExtChanBusy(rsp[1], rsp[2])); + } + else if (src == ZM_MAC_READ) + { + /* rsp[1] = ZM_SEEPROM_MAC_ADDRESS_OFFSET; */ + /* rsp[2] = ZM_SEEPROM_MAC_ADDRESS_OFFSET+4; */ + /* rsp[3] = ZM_SEEPROM_REGDOMAIN_OFFSET; */ + /* rsp[4] = ZM_SEEPROM_VERISON_OFFSET; */ + /* rsp[5] = ZM_SEEPROM_HARDWARE_TYPE_OFFSET; */ + /* rsp[6] = ZM_SEEPROM_HW_HEAVY_CLIP; */ + + u8_t addr[6], CCS, WWR; + u16_t CountryDomainCode; + + /* BB heavy clip */ + //hpPriv->eepromHeavyClipFlag = (u8_t)((rsp[6]>>24) & 0xff); // force enable 8107 + //zm_msg2_mm(ZM_LV_0, "eepromHeavyClipFlag", hpPriv->eepromHeavyClipFlag); + #if 0 + if (hpPriv->hwBBHeavyClip) + { + zm_msg0_mm(ZM_LV_0, "enable BB Heavy Clip"); + } + else + { + zm_msg0_mm(ZM_LV_0, "Not enable BB Heavy Clip"); + } + #endif + zm_msg2_mm(ZM_LV_0, "MAC rsp[1]=", rsp[1]); + zm_msg2_mm(ZM_LV_0, "MAC rsp[2]=", rsp[2]); + + addr[0] = (u8_t)(rsp[1] & 0xff); + addr[1] = (u8_t)((rsp[1]>>8) & 0xff); + addr[2] = (u8_t)((rsp[1]>>16) & 0xff); + addr[3] = (u8_t)((rsp[1]>>24) & 0xff); + addr[4] = (u8_t)(rsp[2] & 0xff); + addr[5] = (u8_t)((rsp[2]>>8) & 0xff); +/*#ifdef ZM_FB50 + addr[0] = (u8_t)(0 & 0xff); + addr[1] = (u8_t)(3 & 0xff); + addr[2] = (u8_t)(127 & 0xff); + addr[3] = (u8_t)(0 & 0xff); + addr[4] = (u8_t)(9 & 0xff); + addr[5] = (u8_t)(11 & 0xff); +#endif*/ + + zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_L, + ((((u32_t)addr[3])<<24) | (((u32_t)addr[2])<<16) | (((u32_t)addr[1])<<8) | addr[0])); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_H, + ((((u32_t)addr[5])<<8) | addr[4])); + zfFlushDelayWrite(dev); + + wd->ledStruct.ledMode[0] = (u16_t)(rsp[5]&0xffff); + wd->ledStruct.ledMode[1] = (u16_t)(rsp[5]>>16); + zm_msg2_mm(ZM_LV_0, "ledMode[0]=", wd->ledStruct.ledMode[0]); + zm_msg2_mm(ZM_LV_0, "ledMode[1]=", wd->ledStruct.ledMode[1]); + + /* Regulatory Related Setting */ + zm_msg2_mm(ZM_LV_0, "RegDomain rsp=", rsp[3]); + zm_msg2_mm(ZM_LV_0, "OpFlags+EepMisc=", rsp[4]); + hpPriv->OpFlags = (u8_t)((rsp[4]>>16) & 0xff); + if ((rsp[2] >> 24) == 0x1) //Tx mask == 0x1 + { + zm_msg0_mm(ZM_LV_0, "OTUS 1x2"); + hpPriv->halCapability |= ZM_HP_CAP_11N_ONE_TX_STREAM; + } + else + { + zm_msg0_mm(ZM_LV_0, "OTUS 2x2"); + } + if (hpPriv->OpFlags & 0x1) + { + hpPriv->halCapability |= ZM_HP_CAP_5G; + } + if (hpPriv->OpFlags & 0x2) + { + hpPriv->halCapability |= ZM_HP_CAP_2G; + } + + + CCS = (u8_t)((rsp[3] & 0x8000) >> 15); + WWR = (u8_t)((rsp[3] & 0x4000) >> 14); + CountryDomainCode = (u16_t)(rsp[3] & 0x3FFF); + + if (rsp[3] != 0xffffffff) + { + if (CCS) + { + //zm_debug_msg0("CWY - Get Regulation Table from Country Code"); + zfHpGetRegulationTablefromCountry(dev, CountryDomainCode); + } + else + { + //zm_debug_msg0("CWY - Get Regulation Table from Reg Domain"); + zfHpGetRegulationTablefromRegionCode(dev, CountryDomainCode); + } + if (WWR) + { + //zm_debug_msg0("CWY - Enable 802.11d"); + /* below line shall be unmarked after A band is ready */ + //zfiWlanSetDot11DMode(dev, 1); + } + } + else + { + zfHpGetRegulationTablefromRegionCode(dev, NO_ENUMRD); + } + + zfCoreMacAddressNotify(dev, addr); + + } + else if (src == ZM_EEPROM_READ) + { +#if 0 + u8_t addr[6], CCS, WWR; + u16_t CountryDomainCode; +#endif + for (i=0; i<ZM_HAL_MAX_EEPROM_PRQ; i++) + { + if (hpPriv->eepromImageIndex < 1024) + { + hpPriv->eepromImage[hpPriv->eepromImageIndex++] = rsp[i+1]; + } + } + + if (hpPriv->eepromImageIndex == (ZM_HAL_MAX_EEPROM_REQ*ZM_HAL_MAX_EEPROM_PRQ)) + { + #if 0 + for (i=0; i<1024; i++) + { + zm_msg2_mm(ZM_LV_0, "index=", i); + zm_msg2_mm(ZM_LV_0, "eepromImage=", hpPriv->eepromImage[i]); + } + #endif + zm_msg2_mm(ZM_LV_0, "MAC [1]=", hpPriv->eepromImage[0x20c/4]); + zm_msg2_mm(ZM_LV_0, "MAC [2]=", hpPriv->eepromImage[0x210/4]); +#if 0 + addr[0] = (u8_t)(hpPriv->eepromImage[0x20c/4] & 0xff); + addr[1] = (u8_t)((hpPriv->eepromImage[0x20c/4]>>8) & 0xff); + addr[2] = (u8_t)((hpPriv->eepromImage[0x20c/4]>>16) & 0xff); + addr[3] = (u8_t)((hpPriv->eepromImage[0x20c/4]>>24) & 0xff); + addr[4] = (u8_t)(hpPriv->eepromImage[0x210/4] & 0xff); + addr[5] = (u8_t)((hpPriv->eepromImage[0x210/4]>>8) & 0xff); + + zfCoreMacAddressNotify(dev, addr); + + zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_L, + ((((u32_t)addr[3])<<24) | (((u32_t)addr[2])<<16) | (((u32_t)addr[1])<<8) | addr[0])); + zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_H, + ((((u32_t)addr[5])<<8) | addr[4])); + zfFlushDelayWrite(dev); + + /* Regulatory Related Setting */ + zm_msg2_mm(ZM_LV_0, "RegDomain =", hpPriv->eepromImage[0x208/4]); + CCS = (u8_t)((hpPriv->eepromImage[0x208/4] & 0x8000) >> 15); + WWR = (u8_t)((hpPriv->eepromImage[0x208/4] & 0x4000) >> 14); + /* below line shall be unmarked after A band is ready */ + //CountryDomainCode = (u16_t)(hpPriv->eepromImage[0x208/4] & 0x3FFF); + CountryDomainCode = 8; + if (CCS) + { + //zm_debug_msg0("CWY - Get Regulation Table from Country Code"); + zfHpGetRegulationTablefromCountry(dev, CountryDomainCode); + } + else + { + //zm_debug_msg0("CWY - Get Regulation Table from Reg Domain"); + zfHpGetRegulationTablefromRegionCode(dev, CountryDomainCode); + } + if (WWR) + { + //zm_debug_msg0("CWY - Enable 802.11d"); + /* below line shall be unmarked after A band is ready */ + //zfiWlanSetDot11DMode(dev, 1); + } +#endif + zfCoreHalInitComplete(dev); + } + else + { + hpPriv->eepromImageRdReq++; + zfHpLoadEEPROMFromFW(dev); + } + } + else if (src == ZM_EEPROM_WRITE) + { + zfwDbgWriteEepromDone(dev, cmd[1], cmd[2]); + } + else if (src == ZM_ANI_READ) + { + u32_t cycleTime, ctlClear; + + zm_msg2_mm(ZM_LV_0, "ANI rsp[1]=", rsp[1]); + zm_msg2_mm(ZM_LV_0, "ANI rsp[2]=", rsp[2]); + zm_msg2_mm(ZM_LV_0, "ANI rsp[3]=", rsp[3]); + zm_msg2_mm(ZM_LV_0, "ANI rsp[4]=", rsp[4]); + + hpPriv->ctlBusy += rsp[1]; + hpPriv->extBusy += rsp[2]; + + cycleTime = 100000; //100 miniseconds + + if (cycleTime > rsp[1]) + { + ctlClear = (cycleTime - rsp[1]) / 100; + } + else + { + ctlClear = 0; + } + if (wd->aniEnable) + zfHpAniArPoll(dev, ctlClear, rsp[3], rsp[4]); + } + else if (src == ZM_CMD_ECHO) + { + if ( ((struct zsHpPriv*)wd->hpPrivate)->halReInit ) + { + zfCoreHalInitComplete(dev); + ((struct zsHpPriv*)wd->hpPrivate)->halReInit = 0; + } + else + { + zfHpLoadEEPROMFromFW(dev); + } + } + else if (src == ZM_OID_FW_DL_INIT) + { + zfwDbgDownloadFwInitDone(dev); + } + return; +} + + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfWriteRegInternalReg */ +/* Write on chip internal register immediately. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* addr : register address */ +/* val : value */ +/* */ +/* OUTPUTS */ +/* 0 : success */ +/* other : fail */ +/* */ +/* AUTHOR */ +/* Stephen Chen ZyDAS Technology Corporation 2005.11 */ +/* */ +/************************************************************************/ +u32_t zfWriteRegInternalReg(zdev_t* dev, u32_t addr, u32_t val) +{ + u32_t cmd[3]; + u16_t ret; + + cmd[0] = 0x00000108; + cmd[1] = addr; + cmd[2] = val; + + ret = zfIssueCmd(dev, cmd, 12, ZM_OID_INTERNAL_WRITE, NULL); + return ret; +} + + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfDelayWriteInternalReg */ +/* Write on chip internal register, write operation may be */ +/* postponed to form a multiple write command. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* addr : register address */ +/* val : value */ +/* */ +/* OUTPUTS */ +/* 0 : command been postponed */ +/* 1 : commands been executed */ +/* */ +/* AUTHOR */ +/* Stephen Chen ZyDAS Technology Corporation 2005.11 */ +/* */ +/************************************************************************/ +u16_t zfDelayWriteInternalReg(zdev_t* dev, u32_t addr, u32_t val) +{ + u32_t cmd[(ZM_MAX_CMD_SIZE/4)]; + u16_t i; + u16_t ret; + + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv=wd->hpPrivate; + + zmw_declare_for_critical_section(); + + /* enter critical section */ + zmw_enter_critical_section(dev); + + /* Store command to global buffer */ + hpPriv->cmd.delayWcmdAddr[hpPriv->cmd.delayWcmdCount] = addr; + hpPriv->cmd.delayWcmdVal[hpPriv->cmd.delayWcmdCount++] = val; + + /* If pending command reach size limit */ + if ((hpPriv->cmd.delayWcmdCount) >= ((ZM_MAX_CMD_SIZE - 4) >> 3)) + { + cmd[0] = 0x00000100 + (hpPriv->cmd.delayWcmdCount<<3); + + /* copy command to cmd buffer */ + for (i=0; i<hpPriv->cmd.delayWcmdCount; i++) + { + cmd[1+(i<<1)] = hpPriv->cmd.delayWcmdAddr[i]; + cmd[2+(i<<1)] = hpPriv->cmd.delayWcmdVal[i]; + } + /* reset pending command */ + hpPriv->cmd.delayWcmdCount = 0; + + /* leave critical section */ + zmw_leave_critical_section(dev); + + /* issue write command */ + ret = zfIssueCmd(dev, cmd, 4+(i<<3), ZM_OID_INTERNAL_WRITE, NULL); + + return 1; + } + else + { + /* leave critical section */ + zmw_leave_critical_section(dev); + + return 0; + } +} + + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfFlushDelayWrite */ +/* Flush pending write command. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* */ +/* OUTPUTS */ +/* 0 : no pending command */ +/* 1 : commands been executed */ +/* */ +/* AUTHOR */ +/* Stephen Chen ZyDAS Technology Corporation 2005.11 */ +/* */ +/************************************************************************/ +u16_t zfFlushDelayWrite(zdev_t* dev) +{ + u32_t cmd[(ZM_MAX_CMD_SIZE/4)]; + u16_t i; + u16_t ret; + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv=wd->hpPrivate; + + zmw_declare_for_critical_section(); + + /* enter critical section */ + zmw_enter_critical_section(dev); + + /* If there is pending command */ + if (hpPriv->cmd.delayWcmdCount > 0) + { + cmd[0] = 0x00000100 + (hpPriv->cmd.delayWcmdCount<<3); + + /* copy command to cmd buffer */ + for (i=0; i<hpPriv->cmd.delayWcmdCount; i++) + { + cmd[1+(i<<1)] = hpPriv->cmd.delayWcmdAddr[i]; + cmd[2+(i<<1)] = hpPriv->cmd.delayWcmdVal[i]; + } + /* reset pending command */ + hpPriv->cmd.delayWcmdCount = 0; + + /* leave critical section */ + zmw_leave_critical_section(dev); + + /* issue write command */ + ret = zfIssueCmd(dev, cmd, 4+(i<<3), ZM_OID_INTERNAL_WRITE, NULL); + + return 1; + } + else + { + /* leave critical section */ + zmw_leave_critical_section(dev); + + return 0; + } +} + + +u32_t zfiDbgDelayWriteReg(zdev_t* dev, u32_t addr, u32_t val) +{ + zfDelayWriteInternalReg(dev, addr, val); + return 0; +} + +u32_t zfiDbgFlushDelayWrite(zdev_t* dev) +{ + zfFlushDelayWrite(dev); + return 0; +} + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfiDbgWriteReg */ +/* Write register. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* addr : register address */ +/* val : value */ +/* */ +/* OUTPUTS */ +/* 0 : success */ +/* other : fail */ +/* */ +/* AUTHOR */ +/* Stephen Chen ZyDAS Technology Corporation 2005.10 */ +/* */ +/************************************************************************/ +u32_t zfiDbgWriteReg(zdev_t* dev, u32_t addr, u32_t val) +{ + u32_t cmd[3]; + u16_t ret; + + cmd[0] = 0x00000108; + cmd[1] = addr; + cmd[2] = val; + + ret = zfIssueCmd(dev, cmd, 12, ZM_OID_WRITE, 0); + return ret; +} +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfiDbgWriteFlash */ +/* Write flash. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* addr : register address */ +/* val : value */ +/* */ +/* OUTPUTS */ +/* 0 : success */ +/* other : fail */ +/* */ +/* AUTHOR */ +/* Yjsung ZyDAS Technology Corporation 2007.02 */ +/* */ +/************************************************************************/ +u32_t zfiDbgWriteFlash(zdev_t* dev, u32_t addr, u32_t val) +{ + u32_t cmd[3]; + u16_t ret; + + //cmd[0] = 0x0000B008; + /* len[0] : type[0xB0] : seq[?] */ + cmd[0] = 8 | (ZM_CMD_WFLASH << 8); + cmd[1] = addr; + cmd[2] = val; + + ret = zfIssueCmd(dev, cmd, 12, ZM_OID_WRITE, 0); + return ret; +} + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfiDbgWriteEeprom */ +/* Write EEPROM. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* addr : register address */ +/* val : value */ +/* */ +/* OUTPUTS */ +/* 0 : success */ +/* other : fail */ +/* */ +/* AUTHOR */ +/* Paul ZyDAS Technology Corporation 2007.06 */ +/* */ +/************************************************************************/ +u32_t zfiDbgWriteEeprom(zdev_t* dev, u32_t addr, u32_t val) +{ + u32_t cmd[3]; + u16_t ret; + + //cmd[0] = 0x0000B008; + /* len[0] : type[0xB0] : seq[?] */ + cmd[0] = 8 | (ZM_CMD_WREEPROM << 8); + cmd[1] = addr; + cmd[2] = val; + + ret = zfIssueCmd(dev, cmd, 12, ZM_EEPROM_WRITE, 0); + return ret; +} + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfiDbgBlockWriteEeprom */ +/* Block Write Eeprom. */ +/* */ +/* p.s: now,it will write 16 bytes register data per block (N=4) */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* addr : register address */ +/* buf : input data buffer pointer */ +/* */ +/* OUTPUTS */ +/* 0 : success */ +/* other : fail */ +/* */ +/* AUTHOR */ +/* Paul ZyDAS Technology Corporation 2007.06 */ +/* */ +/************************************************************************/ +//#define N buflen/4 +//#define SIZE (2*N+1) + +u32_t zfiDbgBlockWriteEeprom(zdev_t* dev, u32_t addr, u32_t* buf) +{ + u32_t cmd[9]; //2N+1 + u16_t ret,i; + + //cmd[0] = 0x0000B008; + /* len[0] : type[0xB0] : seq[?] */ + + //cmd[0] = (8*N) | (ZM_CMD_WFLASH << 8); + cmd[0] = 32 | (ZM_CMD_WREEPROM << 8); //8N + + for (i=0; i<4; i++) // i<N + { + cmd[(2*i)+1] = addr+(4*i); + cmd[(2*i)+2] = *(buf+i); + } + + ret = zfIssueCmd(dev, cmd, 36, ZM_EEPROM_WRITE, 0); //8N+4 + + // added for EEPROMUpdate, wait a moment for prevent cmd queue full! + //zfwSleep(dev, 1); + + return ret; +} + + +/* write EEPROM with wrlen : wrlen must be 4*n */ +/* command format : cmd_info(4) + addr(4) + eeprom(wrlen) */ +u32_t zfiDbgBlockWriteEeprom_v2(zdev_t* dev, u32_t addr, u32_t* buf, u32_t wrlen) +{ + u32_t cmd[16]; + u16_t ret,i; + + /* len[0] : type[0xB0] : seq[?] */ + /* len = addr(4) + eeprom_block(wrlen) */ + cmd[0] = (wrlen+4) | (ZM_CMD_MEM_WREEPROM << 8); + cmd[1] = addr; + + for (i=0; i<(wrlen/4); i++) // i<wrlen/4 + { + cmd[2+i] = *(buf+i); + } + /* cmd_info(4) + addr(4) + eeprom(wrlen) */ + ret = zfIssueCmd(dev, cmd, (u16_t)(wrlen+8), ZM_EEPROM_WRITE, 0); + + return ret; +} + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfDbgOpenEeprom */ +/* Open EEPROM. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* */ +/* OUTPUTS */ +/* */ +/* AUTHOR */ +/* Paul ZyDAS Technology Corporation 2007.06 */ +/* */ +/************************************************************************/ +void zfDbgOpenEeprom(zdev_t* dev) +{ + // unlock EEPROM + zfDelayWriteInternalReg(dev, 0x1D1400, 0x12345678); + zfDelayWriteInternalReg(dev, 0x1D1404, 0x55aa00ff); + zfDelayWriteInternalReg(dev, 0x1D1408, 0x13579ace); + zfDelayWriteInternalReg(dev, 0x1D1414, 0x0); + zfFlushDelayWrite(dev); +} + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfDbgCloseEeprom */ +/* Close EEPROM. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* */ +/* OUTPUTS */ +/* */ +/* AUTHOR */ +/* Paul ZyDAS Technology Corporation 2007.05 */ +/* */ +/************************************************************************/ +void zfDbgCloseEeprom(zdev_t* dev) +{ + // lock EEPROM + zfDelayWriteInternalReg(dev, 0x1D1400, 0x87654321); + //zfDelayWriteInternalReg(dev, 0x1D1404, 0xffffffff); + //zfDelayWriteInternalReg(dev, 0x1D1408, 0xffffffff); + //zfDelayWriteInternalReg(dev, 0x1D1414, 0x100); + zfFlushDelayWrite(dev); +} +#if 0 +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfiSeriallyWriteEeprom */ +/* Write EEPROM Serially. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* addr : start address of writing EEPROM */ +/* buf : input data buffer */ +/* buflen : size of input data buffer */ +/* (length of data write into EEPROM) */ +/* */ +/* OUTPUTS */ +/* */ +/* */ +/* */ +/* AUTHOR */ +/* Paul ZyDAS Technology Corporation 2007.06 */ +/* */ +/************************************************************************/ +u32_t zfiSeriallyWriteEeprom(zdev_t* dev, u32_t addr, u32_t* buf, u32_t buflen) +{ + u32_t count; + u16_t i,ret,blocksize; + u8_t temp[2]; + + // per 4 bytes = 1 count + count = buflen/4; + + // Open EEPROM + zfDbgOpenEeprom(dev); + + // Write EEPROM + for (i=0; i<count; i++) + { + if (zfwWriteEeprom(dev, (addr+(4*i)), *(buf+i), 0) != 0) + { + // Update failed, Close EEPROM + zm_debug_msg0("zfwWriteEeprom failed \n"); + zfDbgCloseEeprom(dev); + return 1; + } + } + + // Close EEPROM + zfDbgCloseEeprom(dev); + return 0; +} +#endif +#if 0 +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfiSeriallyBlockWriteEeprom */ +/* Block Write EEPROM Serially. */ +/* (BlockWrite: per 16bytes write EEPROM once) */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* addr : register address */ +/* buf : input data buffer */ +/* buflen : access data size of buf */ +/* */ +/* OUTPUTS */ +/* 0 : success */ +/* other : fail */ +/* */ +/* AUTHOR */ +/* Paul ZyDAS Technology Corporation 2007.05 */ +/* */ +/************************************************************************/ +u32_t zfiSeriallyBlockWriteEeprom(zdev_t* dev, u32_t addr, u32_t* buf, u32_t buflen) +{ + u32_t count; + u16_t i,ret,blocksize; + u8_t temp[2]; + + // per 4 bytes = 1 count + count = buflen/4; + + // Open EEPROM + zfDbgOpenEeprom(dev); + + // Write EEPROM + // EEPROM Write start address from: 0x1000!? + // per 16bytes(N=4) block write EEPROM once + for (i=0; i<(count/4); i++) // count/N + { + //zfiDbgBlockWriteEeprom(dev, (addr+(4*N*i)), buf+(N*i)); + //zfiDbgBlockWriteEeprom(dev, (addr+(16*i)), buf+(4*i)); + if (zfwBlockWriteEeprom(dev, (addr+(16*i)), buf+(4*i), 0) != 0) + { + zm_debug_msg0("zfiDbgBlockWriteEeprom failed \n"); + // Close EEPROM + zfDbgCloseEeprom(dev); + return 1; + } + } + + // Close EEPROM + zfDbgCloseEeprom(dev); + return 0; +} +#endif +#if 0 +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfiDbgDumpEeprom */ +/* Dump EEPROM. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* addr : start address of dumping EEPROM */ +/* datalen : length of access EEPROM data */ +/* buf : point of buffer, the buffer saved dump data */ +/* */ +/* OUTPUTS */ +/* 0 : success */ +/* other : fail */ +/* */ +/* AUTHOR */ +/* Paul ZyDAS Technology Corporation 2007.06 */ +/* */ +/************************************************************************/ +u32_t zfiDbgDumpEeprom(zdev_t* dev, u32_t addr, u32_t datalen, u32_t* buf) +{ + u32_t count; + u16_t i,ret; + + count = datalen/4; + + // over EEPROM length + if(datalen > 0x2000) + { + return 1; + } + + for(i=0; i<count; i++) + { + buf[i] = zfwReadEeprom(dev, addr+(4*i)); + } + + return 0; +} +#endif +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfiDbgReadReg */ +/* Read register. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* addr : register address */ +/* */ +/* OUTPUTS */ +/* 0 : success */ +/* other : fail */ +/* */ +/* AUTHOR */ +/* Stephen Chen ZyDAS Technology Corporation 2005.10 */ +/* */ +/************************************************************************/ +u32_t zfiDbgReadReg(zdev_t* dev, u32_t addr) +{ + u32_t cmd[2]; + u16_t ret; + + cmd[0] = 0x00000004; + cmd[1] = addr; + + ret = zfIssueCmd(dev, cmd, 8, ZM_OID_READ, 0); + return ret; +} + + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfiDbgReadTally */ +/* Read register. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* */ +/* OUTPUTS */ +/* 0 : success */ +/* other : fail */ +/* */ +/* AUTHOR */ +/* Stephen Chen ZyDAS Technology Corporation 2005.10 */ +/* */ +/************************************************************************/ +u32_t zfiDbgReadTally(zdev_t* dev) +{ + u32_t cmd[1]; + u16_t ret; + zmw_get_wlan_dev(dev); + + if ( ((struct zsHpPriv*)wd->hpPrivate)->halReInit ) + { + return 1; + } + + /* len[0] : type[0x81] : seq[?] */ + cmd[0] = 0 | (ZM_CMD_TALLY << 8); + ret = zfIssueCmd(dev, cmd, 4, ZM_OID_TALLY, 0); + + /* len[0] : type[0x82] : seq[?] */ + cmd[0] = 0 | (ZM_CMD_TALLY_APD << 8); + ret = zfIssueCmd(dev, cmd, 4, ZM_OID_TALLY_APD, 0); + + return ret; +} + + +u32_t zfiDbgSetIFSynthesizer(zdev_t* dev, u32_t value) +{ + u32_t cmd[2]; + u16_t ret; + + /* len[4] : type[0x32] : seq[?] */ + cmd[0] = 0x4 | (ZM_OID_SYNTH << 8); + cmd[1] = value; + + ret = zfIssueCmd(dev, cmd, 8, ZM_OID_SYNTH, 0); + return ret; +} + +u32_t zfiDbgQueryHwTxBusy(zdev_t* dev) +{ + u32_t cmd[1]; + u16_t ret; + + /* len[4] : type[0xC0] : seq[?] */ + cmd[0] = 0 | (ZM_CMD_DKTX_STATUS << 8); + + ret = zfIssueCmd(dev, cmd, 4, ZM_OID_DKTX_STATUS, 0); + return ret; +} + +//Paul++ +#if 0 +u16_t zfHpBlockEraseFlash(zdev_t *dev, u32_t addr) +{ + u32_t cmd[(ZM_MAX_CMD_SIZE/4)]; + u16_t ret; + + cmd[0] = 0x00000004 | (ZM_CMD_FLASH_ERASE << 8); + cmd[1] = addr; + + ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, NULL); + return ret; +} +#endif + +#if 0 +u16_t zfiDbgProgramFlash(zdev_t *dev, u32_t offset, u32_t len, u32_t *data) +{ + u32_t cmd[(ZM_MAX_CMD_SIZE/4)]; + u16_t ret; + u16_t i; + + + cmd[0] = (ZM_CMD_FLASH_PROG << 8) | ((len+8) & 0xff); + cmd[1] = offset; + cmd[2] = len; + + for (i = 0; i < (len >> 2); i++) + { + cmd[3+i] = data[i]; + } + + ret = zfIssueCmd(dev, cmd, 12, ZM_OID_FLASH_PROGRAM, NULL); + + return ret; +} +#endif + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfiDbgChipEraseFlash */ +/* Chip Erase Flash. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* */ +/* OUTPUTS */ +/* 0 : success */ +/* other : fail */ +/* */ +/* AUTHOR */ +/* Paul Atheros Technology Corporation 2007.09 */ +/* */ +/************************************************************************/ +u16_t zfiDbgChipEraseFlash(zdev_t *dev) +{ + u32_t cmd[(ZM_MAX_CMD_SIZE/4)]; + u16_t ret; + + cmd[0] = 0x00000000 | (ZM_CMD_FLASH_ERASE << 8); + + ret = zfIssueCmd(dev, cmd, 4, ZM_OID_INTERNAL_WRITE, NULL); + return ret; +} +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfiDbgGetFlashCheckSum */ +/* Get FlashCheckSum. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* addr : Start address of getchksum */ +/* len : total lenth of calculate getchksum */ +/* */ +/* OUTPUTS */ +/* 0 : success */ +/* other : fail */ +/* */ +/* AUTHOR */ +/* Paul Atheros Technology Corporation 2007.08 */ +/* */ +/************************************************************************/ +u32_t zfiDbgGetFlashCheckSum(zdev_t *dev, u32_t addr, u32_t len) +{ + u32_t cmd[(ZM_MAX_CMD_SIZE/4)]; + u32_t ret; + + cmd[0] = 0x00000008 | (ZM_CMD_FLASH_CHKSUM << 8); + cmd[1] = addr; + cmd[2] = len; + + ret = zfIssueCmd(dev, cmd, 12, ZM_OID_FLASH_CHKSUM, NULL); + + return ret; +} + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfiDbgReadFlash */ +/* Read Flash. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* addr : Start address of read flash */ +/* len : total lenth of read flash data */ +/* */ +/* OUTPUTS */ +/* 0 : success */ +/* other : fail */ +/* */ +/* AUTHOR */ +/* Paul Atheros Technology Corporation 2007.09 */ +/* */ +/************************************************************************/ +u32_t zfiDbgReadFlash(zdev_t *dev, u32_t addr, u32_t len) +{ + u32_t cmd[(ZM_MAX_CMD_SIZE/4)]; + u32_t ret; + + cmd[0] = len | (ZM_CMD_FLASH_READ << 8); + cmd[1] = addr; + + ret = zfIssueCmd(dev, cmd, 8, ZM_OID_FLASH_READ, NULL); + return ret; +} + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfiDownloadFwSet */ +/* Before Download FW, */ +/* Command FW to Software reset and close watch dog control. */ +/* */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* */ +/* OUTPUTS */ +/* 0 : success */ +/* other : fail */ +/* */ +/* AUTHOR */ +/* Paul Atheros Technology Corporation 2007.09 */ +/* */ +/************************************************************************/ +u32_t zfiDownloadFwSet(zdev_t *dev) +{ +//softwarereset +//close watch dog + u32_t cmd[(ZM_MAX_CMD_SIZE/4)]; + u32_t ret; + + cmd[0] = 0x00000008 | (ZM_CMD_FW_DL_INIT << 8); + + ret = zfIssueCmd(dev, cmd, 12, ZM_OID_FW_DL_INIT, NULL); + + return ret; +} +//Paul-- diff --git a/drivers/staging/otus/hal/hpusb.c b/drivers/staging/otus/hal/hpusb.c new file mode 100644 index 000000000000..4b76de93fff0 --- /dev/null +++ b/drivers/staging/otus/hal/hpusb.c @@ -0,0 +1,1584 @@ +/* + * Copyright (c) 2000-2005 ZyDAS Technology Corporation + * Copyright (c) 2007-2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +/* */ +/* Module Name : ud.c */ +/* */ +/* Abstract */ +/* This module contains USB descriptor functions. */ +/* */ +/* NOTES */ +/* None */ +/* */ +/************************************************************************/ +#include "../80211core/cprecomp.h" +#include "hpani.h" +#include "hpusb.h" + +extern void zfwUsbCmd(zdev_t* dev, u8_t endpt, u32_t* cmd, u16_t cmdLen); + +extern void zfIdlRsp(zdev_t* dev, u32_t* rsp, u16_t rspLen); +extern u16_t zfDelayWriteInternalReg(zdev_t* dev, u32_t addr, u32_t val); +extern u16_t zfFlushDelayWrite(zdev_t* dev); + + +#define USB_ENDPOINT_TX_INDEX 1 +#define USB_ENDPOINT_RX_INDEX 2 +#define USB_ENDPOINT_INT_INDEX 3 +#define USB_ENDPOINT_CMD_INDEX 4 + +void zfIdlCmd(zdev_t* dev, u32_t* cmd, u16_t cmdLen) +{ +#if ZM_SW_LOOP_BACK != 1 + zfwUsbCmd(dev, USB_ENDPOINT_CMD_INDEX, cmd, cmdLen); +#endif + + return; +} + + +/* zfAdjustCtrlSetting: fit OUTS format */ +/* convert MIMO2 to OUTS */ +void zfAdjustCtrlSetting(zdev_t* dev, u16_t* header, zbuf_t* buf) +{ + /* MIMO2 => OUTS FB-50 */ + /* length not change, only modify format */ + + u32_t oldMT; + u32_t oldMCS; + + u32_t phyCtrl; + u32_t oldPhyCtrl; + + u16_t tpc = 0; + + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv=wd->hpPrivate; + + /* mm */ + if (header == NULL) + { + oldPhyCtrl = zmw_buf_readh(dev, buf, 4) | ((u32_t)zmw_buf_readh(dev, buf, 6) << 16); + } + else + { + oldPhyCtrl = header[2] | ((u32_t)header[3] <<16); + } + + phyCtrl = 0; + + + /* MT : Bit[1~0] */ + oldMT = oldPhyCtrl&0x3; + phyCtrl |= oldMT; + if ( oldMT == 0x3 ) /* DL-OFDM (Duplicate Legacy OFDM) */ + phyCtrl |= 0x1; + + + /* PT : Bit[2] HT PT: 0 Mixed mode 1 Green field */ + phyCtrl |= (oldPhyCtrl&0x4); + + /* Bandwidth control : Bit[4~3] */ + if ( oldPhyCtrl&0x800000 ) /* Bit23 : 40M */ + { + #if 0 + if (oldMT == 0x3) /* DL-OFDM */ + phyCtrl |= (0x3<<3); /* 40M duplicate */ + else + phyCtrl |= (0x2<<3); /* 40M shared */ + #else + if (oldMT == 0x2 && ((struct zsHpPriv*)wd->hpPrivate)->hwBw40) + { + phyCtrl |= (0x2<<3); /* 40M shared */ + } + #endif + } + else { + oldPhyCtrl &= ~0x80000000; + } + + /* MCS : Bit[24~18] */ + oldMCS = (oldPhyCtrl&0x7f0000)>>16; /* Bit[22~16] */ + phyCtrl |= (oldMCS<<18); + + /* Short GI : Bit[31]*/ + phyCtrl |= (oldPhyCtrl&0x80000000); + + /* AM : Antenna mask */ + //if ((oldMT == 2) && (oldMCS > 7)) + if (hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM) + { + phyCtrl |= (0x1<<15); + } + else + { + /* HT Tx 2 chain */ + /* OFDM 6M/9M/12M/18M/24M Tx 2 chain */ + /* OFDM 36M/48M/54M/ Tx 1 chain */ + /* CCK Tx 2 chain */ + if ((oldMT == 2) || (oldMT == 3)) + { + phyCtrl |= (0x5<<15); + } + else if (oldMT == 1) + { + if ((oldMCS == 0xb) || (oldMCS == 0xf) || + (oldMCS == 0xa) || (oldMCS == 0xe) || + (oldMCS == 0x9)) //6M/9M/12M/18M/24M + { + phyCtrl |= (0x5<<15); + } + else + { + phyCtrl |= (0x1<<15); + } + } + else //(oldMT==0) + { + phyCtrl |= (0x5<<15); + } + } + //else + // phyCtrl |= (0x1<<15); + + /* TPC */ + /* TODO : accelerating these code */ + if (hpPriv->hwFrequency < 3000) + { + if (oldMT == 0) + { + /* CCK */ + tpc = (hpPriv->tPow2xCck[oldMCS]&0x3f); + } + else if (oldMT == 1) + { + /* OFDM */ + if (oldMCS == 0xc) + { + tpc = (hpPriv->tPow2x2g[3]&0x3f); + } + else if (oldMCS == 0x8) + { + tpc = (hpPriv->tPow2x2g[2]&0x3f); + } + else if (oldMCS == 0xd) + { + tpc = (hpPriv->tPow2x2g[1]&0x3f); + } + else if (oldMCS == 0x9) + { + tpc = ((hpPriv->tPow2x2g[0]-hpPriv->tPow2x2g24HeavyClipOffset)&0x3f); + } + else + { + tpc = (hpPriv->tPow2x2g[0]&0x3f); + } + } + else if (oldMT == 2) + { + if ( oldPhyCtrl&0x800000 ) /* Bit23 : 40M */ + { + /* HT 40 */ + tpc = (hpPriv->tPow2x2gHt40[oldMCS&0x7]&0x3f); + } + else + { + /* HT 20 */ + tpc = (hpPriv->tPow2x2gHt20[oldMCS&0x7]&0x3f); + } + } + } + else //5GHz + { + if (oldMT == 1) + { + /* OFDM */ + if (oldMCS == 0xc) + { + tpc = (hpPriv->tPow2x5g[3]&0x3f); + } + else if (oldMCS == 0x8) + { + tpc = (hpPriv->tPow2x5g[2]&0x3f); + } + else if (oldMCS == 0xd) + { + tpc = (hpPriv->tPow2x5g[1]&0x3f); + } + else + { + tpc = (hpPriv->tPow2x5g[0]&0x3f); + } + } + else if (oldMT == 2) + { + if ( oldPhyCtrl&0x800000 ) /* Bit23 : 40M */ + { + /* HT 40 */ + tpc = (hpPriv->tPow2x5gHt40[oldMCS&0x7]&0x3f); + } + else + { + /* HT 20 */ + tpc = (hpPriv->tPow2x5gHt20[oldMCS&0x7]&0x3f); + } + } + } + + /* Tx power adjust for HT40 */ + /* HT40 +1dBm */ + if ((oldMT==2) && (oldPhyCtrl&0x800000) ) + { + tpc += 2; + } + tpc &= 0x3f; + + /* Evl force tx TPC */ + if(wd->forceTxTPC) + { + tpc = (u16_t)(wd->forceTxTPC & 0x3f); + } + + if (hpPriv->hwFrequency < 3000) { + wd->maxTxPower2 &= 0x3f; + tpc = (tpc > wd->maxTxPower2)? wd->maxTxPower2 : tpc; + } else { + wd->maxTxPower5 &= 0x3f; + tpc = (tpc > wd->maxTxPower5)? wd->maxTxPower5 : tpc; + } + + +#define ZM_MIN_TPC 5 +#define ZM_TPC_OFFSET 5 +#define ZM_SIGNAL_THRESHOLD 56 + if ((wd->sta.bScheduleScan == FALSE) && (wd->sta.bChannelScan == FALSE)) + { + if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE ) + && (zfStaIsConnected(dev)) + && (wd->SignalStrength > ZM_SIGNAL_THRESHOLD)) + { + if (tpc > ((ZM_MIN_TPC+ZM_TPC_OFFSET)*2)) + { + tpc -= (ZM_TPC_OFFSET*2); + } + else if (tpc > (ZM_MIN_TPC*2)) + { + tpc = (ZM_MIN_TPC*2); + } + } + } +#undef ZM_MIN_TPC +#undef ZM_TPC_OFFSET +#undef ZM_SIGNAL_THRESHOLD + + #ifndef ZM_OTUS_LINUX_PHASE_2 + phyCtrl |= (tpc & 0x3f) << 9; + #endif + + /* Set bits[8:6]BF-MCS for heavy clip */ + if ((phyCtrl&0x3) == 2) + { + phyCtrl |= ((phyCtrl >> 12) & 0x1c0); + } + + /* PHY control */ + if (header == NULL) + { + zmw_buf_writeh(dev, buf, 4, (u16_t) (phyCtrl&0xffff)); + zmw_buf_writeh(dev, buf, 6, (u16_t) (phyCtrl>>16)); + } + else + { + //PHY control L + header[2] = (u16_t) (phyCtrl&0xffff); + //PHY control H + header[3] = (u16_t) (phyCtrl>>16); + } + + zm_msg2_tx(ZM_LV_2, "old phy ctrl = ", oldPhyCtrl); + zm_msg2_tx(ZM_LV_2, "new phy ctrl = ", phyCtrl); + //DbgPrint("old phy ctrl =%08x \n", oldPhyCtrl); + //DbgPrint("new phy ctrl =%08x \n", phyCtrl); +} + + +#define EXTRA_INFO_LEN 24 //RSSI(7) + EVM(12) + PHY(1) + MACStatus(4) +u16_t zfHpSend(zdev_t* dev, u16_t* header, u16_t headerLen, + u16_t* snap, u16_t snapLen, + u16_t* tail, u16_t tailLen, zbuf_t* buf, u16_t offset, + u16_t bufType, u8_t ac, u8_t keyIdx) +{ +#if ZM_SW_LOOP_BACK == 1 + zbuf_t *rxbuf; + u8_t *puRxBuf; + u8_t *pHdr; + u8_t *psnap; + u16_t plcplen = 12; + u16_t i; + u16_t swlpOffset; +#endif /* #if ZM_SW_LOOP_BACK == 1 */ + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv=wd->hpPrivate; + + zm_msg1_tx(ZM_LV_1, "zfHpSend(), len = ", 12 + headerLen-8 + snapLen + zfwBufGetSize(dev, buf) + 4 + 8); + + /* Adjust ctrl setting : 6N14 yjsung */ + zfAdjustCtrlSetting(dev, header, buf); + +#if ZM_SW_LOOP_BACK != 1 + hpPriv->usbSendBytes += zfwBufGetSize(dev, buf); + hpPriv->usbAcSendBytes[ac&0x3] += zfwBufGetSize(dev, buf); + + /* Submit USB Out Urb */ + zfwUsbSend(dev, USB_ENDPOINT_TX_INDEX, (u8_t *)header, headerLen, + (u8_t *)snap, snapLen, (u8_t *)tail, tailLen, buf, offset); +#endif + +#if ZM_SW_LOOP_BACK == 1 + + rxbuf = zfwBufAllocate(dev, plcplen + headerLen-8 + snapLen + (zfwBufGetSize(dev, buf)-offset) + 4 + EXTRA_INFO_LEN); + pHdr = (u8_t *) header+8; + psnap = (u8_t *) snap; + + zmw_enter_critical_section(dev); + /* software loop back */ + /* Copy WLAN header and packet buffer */ + swlpOffset = plcplen; + + for(i = 0; i < headerLen-8; i++) + { + zmw_rx_buf_writeb(dev, rxbuf, swlpOffset+i, pHdr[i]); + } + + swlpOffset += headerLen-8; + + /* Copy SNAP header */ + for(i = 0; i < snapLen; i++) + { + zmw_rx_buf_writeb(dev, rxbuf, swlpOffset+i, psnap[i]); + } + + swlpOffset += snapLen; + + /* Copy body from tx buf to rxbuf */ + for(i = 0; i < (zfwBufGetSize(dev, buf)-offset); i++) + { + u8_t value = zmw_rx_buf_readb(dev, buf, i+offset); + zmw_rx_buf_writeb(dev, rxbuf, swlpOffset+i, value); + } + + /* total length = PLCP + MacHeader + Payload + FCS + RXstatus */ + /* 12 + headerLen-8 + snapLen + buf length + 4 + 8 */ + zfwSetBufSetSize(dev, rxbuf, swlpOffset + (zfwBufGetSize(dev, buf)-offset) + 4 + EXTRA_INFO_LEN ); + + zmw_leave_critical_section(dev); + + zfwBufFree(dev, buf, 0); + + //zfwDumpBuf(dev, rxbuf); + //------------------------------------------------- + + //zfCoreRecv(dev, rxbuf); + +#endif /* #if ZM_SW_LOOP_BACK */ + + return ZM_SUCCESS; +} + +/* Report moniter Hal rx information about rssi, evm, bandwidth, SG etc */ +void zfHpQueryMonHalRxInfo(zdev_t* dev, u8_t *monHalRxInfo) +{ + zmw_get_wlan_dev(dev); + zfMemoryCopy(monHalRxInfo, + (u8_t*)&(((struct zsHpPriv*)wd->hpPrivate)->halRxInfo), + sizeof(struct zsHalRxInfo)); +} + + +u8_t zfIsDataFrame(zdev_t* dev, zbuf_t* buf) +{ + u8_t frameType; + u8_t mpduInd; + + mpduInd = zmw_rx_buf_readb(dev, buf, zfwBufGetSize(dev, buf)-1); + + /* sinlge or First */ + if ((mpduInd & 0x30) == 0x00 || (mpduInd & 0x30) == 0x20) + { + frameType = zmw_rx_buf_readb(dev, buf, 12); + } + else + { + frameType = zmw_rx_buf_readb(dev, buf, 0); + } + + if((frameType & 0xf) == ZM_WLAN_DATA_FRAME) + return 1; + else + return 0; +} + +u32_t zfcConvertRateOFDM(zdev_t* dev, zbuf_t* buf) +{ + // What's the default value?? + u32_t MCS = 0; + + switch(zmw_rx_buf_readb(dev, buf, 0)& 0xf) + { + case 0xb: + MCS = 0x4; + break; + case 0xf: + MCS = 0x5; + break; + case 0xa: + MCS = 0x6; + break; + case 0xe: + MCS = 0x7; + break; + case 0x9: + MCS = 0x8; + break; + case 0xd: + MCS = 0x9; + break; + case 0x8: + MCS = 0xa; + break; + case 0xc: + MCS = 0xb; + break; + } + return MCS; +} + +u16_t zfHpGetPayloadLen(zdev_t* dev, + zbuf_t* buf, + u16_t len, + u16_t plcpHdrLen, + u32_t *rxMT, + u32_t *rxMCS, + u32_t *rxBW, + u32_t *rxSG + ) +{ + u8_t modulation,mpduInd; + u16_t low, high, msb; + s16_t payloadLen = 0; + + zmw_get_wlan_dev(dev); + + mpduInd = zmw_rx_buf_readb(dev, buf, len-1); + modulation = zmw_rx_buf_readb(dev, buf, (len-1)) & 0x3; + *rxMT = modulation; + + //zm_debug_msg1(" modulation= ", modulation); + switch (modulation) { + case 0: /* CCK Mode */ + low = zmw_rx_buf_readb(dev, buf, 2); + high = zmw_rx_buf_readb(dev, buf, 3); + payloadLen = (low | high << 8) - 4; + if (wd->enableHALDbgInfo) + { + *rxMCS = zmw_rx_buf_readb(dev, buf, 0); + *rxBW = 0; + *rxSG = 0; + } + break; + case 1: /* Legacy-OFDM mode */ + low = zmw_rx_buf_readb(dev, buf, 0) >> 5; + high = zmw_rx_buf_readb(dev, buf, 1); + msb = zmw_rx_buf_readb(dev, buf, 2) & 0x1; + payloadLen = (low | (high << 3) | (msb << 11)) - 4; + if (wd->enableHALDbgInfo) + { + *rxMCS = zfcConvertRateOFDM(dev, buf); + *rxBW = 0; + *rxSG = 0; + } + break; + case 2: /* HT OFDM mode */ + //zm_debug_msg1("aggregation= ", (zmw_rx_buf_readb(dev, buf, 6) >> 3) &0x1 ); + if ((mpduInd & 0x30) == 0x00 || (mpduInd & 0x30) == 0x10) //single or last mpdu + payloadLen = len - 24 - 4 - plcpHdrLen; // - rxStatus - fcs + else { + payloadLen = len - 4 - 4 - plcpHdrLen; // - rxStatus - fcs + //zm_debug_msg1("first or middle mpdu, plcpHdrLen= ", plcpHdrLen); + } + if (wd->enableHALDbgInfo) + { + *rxMCS = zmw_rx_buf_readb(dev, buf, 3) & 0x7f; + *rxBW = (zmw_rx_buf_readb(dev, buf, 3) >> 7) & 0x1; + *rxSG = (zmw_rx_buf_readb(dev, buf, 6) >> 7) & 0x1; + } + break; + default: + break; + + } + /* return the payload length - FCS */ + if (payloadLen < 0) payloadLen = 0; + return payloadLen; +} + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfiUsbRecv */ +/* Callback function for USB IN Transfer. */ +/* */ +/* INPUTS */ +/* dev: device pointer */ +/* */ +/* OUTPUTS */ +/* None */ +/* */ +/* AUTHOR */ +/* Yuan-Gu Wei ZyDAS Technology Corporation 2005.10 */ +/* */ +/************************************************************************/ +#define ZM_INT_USE_EP2 1 +#define ZM_INT_USE_EP2_HEADER_SIZE 12 + +#if ZM_INT_USE_EP2 == 1 +void zfiUsbRegIn(zdev_t* dev, u32_t* rsp, u16_t rspLen); +#endif + +#ifdef ZM_OTUS_RX_STREAM_MODE +void zfiUsbRecvPerPkt(zdev_t *dev, zbuf_t *buf) +#else +void zfiUsbRecv(zdev_t *dev, zbuf_t *buf) +#endif +{ + + +#if ZM_FW_LOOP_BACK != 1 + u8_t mpduInd; + u16_t plcpHdrLen; + u16_t crcPlusRxStatusLen; + u16_t len, payloadLen=0; + u16_t i; //CWYang(+) + struct zsAdditionInfo addInfo; + u32_t rxMT; + u32_t rxMCS; + u32_t rxBW; + u32_t rxSG; + zmw_get_wlan_dev(dev); + struct zsHpPriv* hpPriv=wd->hpPrivate; + + //zm_msg0_rx(ZM_LV_0, "zfiUsbRecv()"); + +#if ZM_INT_USE_EP2 == 1 + + for (i=0; i<(ZM_INT_USE_EP2_HEADER_SIZE>>1); i++) + { + if (zmw_rx_buf_readh(dev, buf, i*2) != 0xffff) + break; + } + + if (i==(ZM_INT_USE_EP2_HEADER_SIZE>>1)) + { + u32_t rsp[ZM_USB_MAX_EPINT_BUFFER/4]; + u16_t rspLen; + u32_t rspi; + u8_t* pdst = (u8_t*)rsp; + + /* Interrupt Rsp */ + rspLen = (u16_t) zfwBufGetSize(dev, buf)-ZM_INT_USE_EP2_HEADER_SIZE; + + if (rspLen > 60) + { + zm_debug_msg1("Get error len by EP2 = \n", rspLen); + /* free USB buf */ + zfwBufFree(dev, buf, 0); + return; + } + + for (rspi=0; rspi<rspLen; rspi++) + { + *pdst = zmw_rx_buf_readb(dev, buf, rspi+ZM_INT_USE_EP2_HEADER_SIZE); + pdst++; + } + + //if (adapter->zfcbUsbRegIn) + // adapter->zfcbUsbRegIn(adapter, rsp, rspLen); + zfiUsbRegIn(dev, rsp, rspLen); + + /* free USB buf */ + zfwBufFree(dev, buf, 0); + return; + } +#endif /* end of #if ZM_INT_USE_EP2 == 1 */ + + ZM_PERFORMANCE_RX_MPDU(dev, buf); + + if (wd->swSniffer) + { + /* airopeek: Report everything up */ + if (wd->zfcbRecv80211 != NULL) + { + wd->zfcbRecv80211(dev, buf, NULL); + } + } + + /* Read the last byte */ + len = zfwBufGetSize(dev, buf); + mpduInd = zmw_rx_buf_readb(dev, buf, len-1); + + /* First MPDU */ + if((mpduInd & 0x30) == 0x20) + { + u16_t duration; + if (zmw_rx_buf_readb(dev, buf, 36) == 0) //AC = BE + { + duration = zmw_rx_buf_readh(dev, buf, 14); + if (duration > hpPriv->aggMaxDurationBE) + { + hpPriv->aggMaxDurationBE = duration; + } + else + { + if (hpPriv->aggMaxDurationBE > 10) + { + hpPriv->aggMaxDurationBE--; + } + } + //DbgPrint("aggMaxDurationBE=%d", hpPriv->aggMaxDurationBE); + } + } + +#if 1 + /* First MPDU or Single MPDU */ + if(((mpduInd & 0x30) == 0x00) || ((mpduInd & 0x30) == 0x20)) + //if ((mpduInd & 0x10) == 0x00) + { + plcpHdrLen = 12; // PLCP header length + } + else + { + if (zmw_rx_buf_readh(dev, buf, 4) == wd->macAddr[0] && + zmw_rx_buf_readh(dev, buf, 6) == wd->macAddr[1] && + zmw_rx_buf_readh(dev, buf, 8) == wd->macAddr[2]) { + plcpHdrLen = 0; + } + else if (zmw_rx_buf_readh(dev, buf, 16) == wd->macAddr[0] && + zmw_rx_buf_readh(dev, buf, 18) == wd->macAddr[1] && + zmw_rx_buf_readh(dev, buf, 20) == wd->macAddr[2]){ + plcpHdrLen = 12; + } + else { + plcpHdrLen = 0; + } + } + + /* Last MPDU or Single MPDU */ + if ((mpduInd & 0x30) == 0x00 || (mpduInd & 0x30) == 0x10) + { + crcPlusRxStatusLen = EXTRA_INFO_LEN + 4; // Extra bytes + FCS + } + else + { + crcPlusRxStatusLen = 4 + 4; // Extra 4 bytes + FCS + } +#else + plcpHdrLen = 12; + crcPlusRxStatusLen = EXTRA_INFO_LEN + 4; // Extra bytes + FCS +#endif + + if (len < (plcpHdrLen+10+crcPlusRxStatusLen)) + { + zm_msg1_rx(ZM_LV_0, "Invalid Rx length=", len); + //zfwDumpBuf(dev, buf); + + zfwBufFree(dev, buf, 0); + return; + } + + /* display RSSI combined */ + /* + * ¢z¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢s¢w¢w¢w¢w¢w¢w¢w¢w¢s¢w¢w¢w¢w¢w¢w¢s¢w¢w¢w¢w¢w¢w¢s¢w¢w¢w¢w¢w¢w¢w¢w¢w¢s¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢{ + * ¢x PLCP Header ¢x MPDU ¢x RSSI ¢x EVM ¢x PHY Err ¢x MAC Status ¢x + * ¢u¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢q¢w¢w¢w¢w¢w¢w¢w¢w¢q¢w¢w¢w¢w¢w¢w¢q¢w¢w¢w¢w¢w¢w¢q¢w¢w¢w¢w¢w¢w¢w¢w¢w¢q¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢t + * ¢x 12 ¢x n ¢x 7 ¢x 12 ¢x 1 ¢x 4 ¢x + * ¢|¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢r¢w¢w¢w¢w¢w¢w¢w¢w¢r¢w¢w¢w¢w¢w¢w¢r¢w¢w¢w¢w¢w¢w¢r¢w¢w¢w¢w¢w¢w¢w¢w¢w¢r¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢} + * RSSI filed (From BB and MAC just pass them to host) + * Byte1: RSSI for antenna 0. + * Byte2: RSSI for antenna 1. + * Byte3: RSSI for antenna 2. + * Byte4: RSSI for antenna 0 extension. + * Byte5: RSSI for antenna 1 extension. + * Byte6: RSSI for antenna 2 extension. + * Byte7: RSSI for antenna combined. + */ + + //zm_debug_msg1(" recv RSSI = ", zmw_rx_buf_readb(dev, buf, (len-1)-17)); + + payloadLen = zfHpGetPayloadLen(dev, buf, len, plcpHdrLen, &rxMT, &rxMCS, &rxBW, &rxSG); + + /* Hal Rx info */ + /* First MPDU or Single MPDU */ + if(((mpduInd & 0x30) == 0x00) || ((mpduInd & 0x30) == 0x20)) + { + if (wd->enableHALDbgInfo && zfIsDataFrame(dev, buf)) + { + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRxDataMT = rxMT; + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRxDataMCS = rxMCS; + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRxDataBW = rxBW; + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRxDataSG = rxSG; + } + } + + if ((plcpHdrLen + payloadLen) > len) { + zm_msg1_rx(ZM_LV_0, "Invalid payload length=", payloadLen); + zfwBufFree(dev, buf, 0); + return; + } + + //Store Rx Tail Infomation before Remove--CWYang(+) + +#if 0 + for (i = 0; i < crcPlusRxStatusLen-4; i++) + { + addInfo.Tail.Byte[i] = + zmw_rx_buf_readb(dev, buf, len - crcPlusRxStatusLen + 4 + i); + } +#else +/* +* Brief format of OUTS chip +* ¢z¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢s¢w¢w¢w¢w¢w¢w¢w¢w¢s¢w¢w¢w¢w¢w¢w¢s¢w¢w¢w¢w¢w¢w¢s¢w¢w¢w¢w¢w¢w¢w¢w¢w¢s¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢{ +* ¢x PLCP Header ¢x MPDU ¢x RSSI ¢x EVM ¢x PHY Err ¢x MAC Status ¢x +* ¢u¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢q¢w¢w¢w¢w¢w¢w¢w¢w¢q¢w¢w¢w¢w¢w¢w¢q¢w¢w¢w¢w¢w¢w¢q¢w¢w¢w¢w¢w¢w¢w¢w¢w¢q¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢t +* ¢x 12 ¢x n ¢x 7 ¢x 12 ¢x 1 ¢x 4 ¢x +* ¢|¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢r¢w¢w¢w¢w¢w¢w¢w¢w¢r¢w¢w¢w¢w¢w¢w¢r¢w¢w¢w¢w¢w¢w¢r¢w¢w¢w¢w¢w¢w¢w¢w¢w¢r¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢} +* RSSI: +* Byte 1 antenna 0 +* Byte 2 antenna 1 +* Byte 3 antenna 2 +* Byte 4 antenna 0 extension +* Byte 5 antenna 1 extension +* Byte 6 antenna 2 extension +* Byte 7 antenna combined +* EVM: +* Byte 1 Stream 0 pilot 0 +* Byte 2 Stream 0 pilot 1 +* Byte 3 Stream 0 pilot 2 +* Byte 4 Stream 0 pilot 3 +* Byte 5 Stream 0 pilot 4 +* Byte 6 Stream 0 pilot 5 +* Byte 7 Stream 1 pilot 0 +* Byte 8 Stream 1 pilot 1 +* Byte 9 Stream 1 pilot 2 +* Byte 10 Stream 1 pilot 3 +* Byte 11 Stream 1 pilot 4 +* Byte 12 Stream 1 pilot 5 +*/ + + /* Fill the Tail information */ + /* Last MPDU or Single MPDU */ + if ((mpduInd & 0x30) == 0x00 || (mpduInd & 0x30) == 0x10) + { +#define ZM_RX_RSSI_COMPENSATION 27 + u8_t zm_rx_rssi_compensation = ZM_RX_RSSI_COMPENSATION; + + /* RSSI information */ + addInfo.Tail.Data.SignalStrength1 = zmw_rx_buf_readb(dev, buf, + (len-1) - 17) + ((hpPriv->rxStrongRSSI == 1)?zm_rx_rssi_compensation:0); +#undef ZM_RX_RSSI_COMPENSATION + + /* EVM */ + + /* TODO: for RD/BB debug message */ + /* save current rx hw infomration, report to DrvCore/Application */ + if (wd->enableHALDbgInfo && zfIsDataFrame(dev, buf)) + { + u8_t trssi; + for (i=0; i<7; i++) + { + trssi = zmw_rx_buf_readb(dev, buf, (len-1) - 23 + i); + if (trssi&0x80) + { + trssi = ((~((u8_t)trssi) & 0x7f) + 1) & 0x7f; + } + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRSSI[i] = trssi; + + } + if (rxMT==2) + { + //if (rxBW) + //{ + for (i=0; i<12; i++) + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRxEVM[i] = + zmw_rx_buf_readb(dev, buf, (len-1) - 16 + i); + //} + //else + //{ + // for (i=0; i<4; i++) + // ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRxEVM[i] = + // zmw_rx_buf_readb(dev, buf, (len-1) - 16 + i); + //} + } + + #if 0 + /* print */ + zm_dbg(("MT(%d) MCS(%d) BW(%d) SG(%d) RSSI:%d,%d,%d,%d,%d,%d,%d EVM:(%d,%d,%d,%d,%d,%d)(%d,%d,%d,%d,%d,%d)\n", + rxMT, + rxMCS, + rxBW, + rxSG, + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRSSI[0], + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRSSI[1], + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRSSI[2], + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRSSI[3], + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRSSI[4], + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRSSI[5], + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRSSI[6], + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRxEVM[0], + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRxEVM[1], + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRxEVM[2], + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRxEVM[3], + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRxEVM[4], + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRxEVM[5], + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRxEVM[6], + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRxEVM[7], + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRxEVM[8], + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRxEVM[9], + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRxEVM[10], + ((struct zsHpPriv*)wd->hpPrivate)->halRxInfo.currentRxEVM[11] + )); + #endif + } /* if (wd->enableHALDbgInfo && zfIsDataFrame(dev, buf)) */ + + } + else + { + /* Mid or First aggregate frame without phy rx information */ + addInfo.Tail.Data.SignalStrength1 = 0; + } + + addInfo.Tail.Data.SignalStrength2 = 0; + addInfo.Tail.Data.SignalStrength3 = 0; + addInfo.Tail.Data.SignalQuality = 0; + + addInfo.Tail.Data.SAIndex = zmw_rx_buf_readb(dev, buf, len - 4); + addInfo.Tail.Data.DAIndex = zmw_rx_buf_readb(dev, buf, len - 3); + addInfo.Tail.Data.ErrorIndication = zmw_rx_buf_readb(dev, buf, len - 2); + addInfo.Tail.Data.RxMacStatus = zmw_rx_buf_readb(dev, buf, len - 1); + +#endif + /* Remove CRC and Rx Status */ + zfwBufSetSize(dev, buf, (len-crcPlusRxStatusLen)); + //zfwBufSetSize(dev, buf, payloadLen + plcpHdrLen); /* payloadLen + PLCP 12 - FCS 4*/ + + //Store PLCP Header Infomation before Remove--CWYang(+) + if (plcpHdrLen != 0) + { + for (i = 0; i < plcpHdrLen; i++) + { + addInfo.PlcpHeader[i] = zmw_rx_buf_readb(dev, buf, i); + } + } + else + { + addInfo.PlcpHeader[0] = 0; + } + /* Remove PLCP header */ + zfwBufRemoveHead(dev, buf, plcpHdrLen); + + /* handle 802.11 frame */ + zfCoreRecv(dev, buf, &addInfo); + +#else + /* Firmware loopback: Rx frame = Tx frame */ + /* convert Rx frame to fit receive frame format */ + zbuf_t *new_buf; + u8_t ctrl_offset = 8; + u8_t PLCP_Len = 12; + u8_t data; + u8_t i; + + + /* Tx: | ctrl_setting | Mac hdr | data | */ + /* 8 24 x */ + + /* Rx: | PLCP | Mac hdr | data | FCS | Rxstatus | */ + /* 12 24 x 4 8 */ + + /* new allocate a rx format size buf */ + new_buf = zfwBufAllocate(dev, zfwBufGetSize(dev, buf)-8+12+4+EXTRA_INFO_LEN); + + for (i=0; i<zfwBufGetSize(dev, buf)-ctrl_offset; i++) + { + data = zmw_rx_buf_readb(dev, buf, ctrl_offset+i); + zmw_rx_buf_writeb(dev, new_buf, PLCP_Len+i, data); + } + + zfwBufSetSize(dev, new_buf, zfwBufGetSize(dev, buf)-8+12+4+EXTRA_INFO_LEN); + + zfwBufFree(dev, buf, 0); + + /* receive the new_buf */ + //zfCoreRecv(dev, new_buf); + +#endif + +} + +#ifdef ZM_OTUS_RX_STREAM_MODE +void zfiUsbRecv(zdev_t *dev, zbuf_t *buf) +{ + u16_t index = 0; + u16_t chkIdx; + u32_t status = 0; + u16_t ii; + zbuf_t *newBuf; + zbuf_t *rxBufPool[8]; + u16_t rxBufPoolIndex = 0; + struct zsHpPriv *halPriv; + u8_t *srcBufPtr; + u32_t bufferLength; + u16_t usbRxRemainLen; + u16_t usbRxPktLen; + + zmw_get_wlan_dev(dev); + + halPriv = (struct zsHpPriv*)wd->hpPrivate; + srcBufPtr = zmw_buf_get_buffer(dev, buf); + + bufferLength = zfwBufGetSize(dev, buf); + + /* Zero Length Transfer */ + if (!bufferLength) + { + zfwBufFree(dev, buf, 0); + return; + } + + usbRxRemainLen = halPriv->usbRxRemainLen; + usbRxPktLen = halPriv->usbRxTransferLen; + + /* Check whether there is any data in the last transfer */ + if (usbRxRemainLen != 0 ) + { + zbuf_t *remainBufPtr = halPriv->remainBuf; + u8_t* BufPtr = NULL; + + if ( remainBufPtr != NULL ) + { + BufPtr = zmw_buf_get_buffer(dev, remainBufPtr); + } + + index = usbRxRemainLen; + usbRxRemainLen -= halPriv->usbRxPadLen; + + /* Copy data */ + if ( BufPtr != NULL ) + { + zfwMemoryCopy(&(BufPtr[usbRxPktLen]), srcBufPtr, usbRxRemainLen); + } + + usbRxPktLen += usbRxRemainLen; + halPriv->usbRxRemainLen = 0; + + if ( remainBufPtr != NULL ) + { + zfwBufSetSize(dev, remainBufPtr, usbRxPktLen); + rxBufPool[rxBufPoolIndex++] = remainBufPtr; + } + halPriv->remainBuf = NULL; + } + + //zm_debug_msg1("length: %d\n", (int)pUsbRxTransfer->pRxUrb->UrbBulkOrInterruptTransfer.TransferBufferLength); + + bufferLength = zfwBufGetSize(dev, buf); +//printk("bufferLength %d\n", bufferLength); + while(index < bufferLength) + { + u16_t pktLen; + u16_t pktTag; + //u8_t *ptr = (u8_t*)((struct zsBuffer*)pUsbRxTransfer->buf)->data; + u8_t *ptr = srcBufPtr; + + /* Retrieve packet length and tag */ + pktLen = ptr[index] + (ptr[index+1] << 8); + pktTag = ptr[index+2] + (ptr[index+3] << 8); + + if (pktTag == ZM_USB_STREAM_MODE_TAG) + { + u16_t padLen; + + zm_assert(pktLen < ZM_WLAN_MAX_RX_SIZE); + + //printk("Get a packet, pktLen: 0x%04x\n", pktLen); + #if 0 + /* Dump data */ + for (ii = index; ii < pkt_len+4;) + { + DbgPrint("0x%02x ", + (zmw_rx_buf_readb(adapter, pUsbRxTransfer->buf, ii) & 0xff)); + + if ((++ii % 16) == 0) + DbgPrint("\n"); + } + + DbgPrint("\n"); + #endif + + /* Calcuate the padding length, in the current design, + the length should be padded to 4 byte boundray. */ + padLen = ZM_USB_STREAM_MODE_TAG_LEN - (pktLen & 0x3); + + if(padLen == ZM_USB_STREAM_MODE_TAG_LEN) + padLen = 0; + + chkIdx = index; + index = index + ZM_USB_STREAM_MODE_TAG_LEN + pktLen + padLen; + + if (chkIdx > ZM_MAX_USB_IN_TRANSFER_SIZE) + { + zm_debug_msg1("chkIdx is too large, chkIdx: %d\n", chkIdx); + zm_assert(0); + status = 1; + break; + } + + if (index > ZM_MAX_USB_IN_TRANSFER_SIZE) + { + //struct zsBuffer* BufPtr; + //struct zsBuffer* UsbBufPtr; + u8_t *BufPtr; + u8_t *UsbBufPtr; + + halPriv->usbRxRemainLen = index - ZM_MAX_USB_IN_TRANSFER_SIZE; // - padLen; + halPriv->usbRxTransferLen = ZM_MAX_USB_IN_TRANSFER_SIZE - + chkIdx - ZM_USB_STREAM_MODE_TAG_LEN; + halPriv->usbRxPadLen = padLen; + //check_index = index; + + if (halPriv->usbRxTransferLen > ZM_WLAN_MAX_RX_SIZE) + { + zm_debug_msg1("check_len is too large, chk_len: %d\n", + halPriv->usbRxTransferLen); + status = 1; + break; + } + + /* Allocate a skb buffer */ + newBuf = zfwBufAllocate(dev, ZM_WLAN_MAX_RX_SIZE); + + if ( newBuf != NULL ) + { + BufPtr = zmw_buf_get_buffer(dev, newBuf); + UsbBufPtr = srcBufPtr; + + /* Copy the buffer */ + zfwMemoryCopy(BufPtr, &(UsbBufPtr[chkIdx+ZM_USB_STREAM_MODE_TAG_LEN]), halPriv->usbRxTransferLen); + + /* Record the buffer pointer */ + halPriv->remainBuf = newBuf; + } + } + else + { + u8_t* BufPtr; + u8_t* UsbBufPtr; + + /* Allocate a skb buffer */ + newBuf = zfwBufAllocate(dev, ZM_WLAN_MAX_RX_SIZE); + if ( newBuf != NULL ) + { + BufPtr = zmw_buf_get_buffer(dev, newBuf); + UsbBufPtr = srcBufPtr; + + /* Copy the buffer */ + zfwMemoryCopy(BufPtr, &(UsbBufPtr[chkIdx+ZM_USB_STREAM_MODE_TAG_LEN]), pktLen); + + zfwBufSetSize(dev, newBuf, pktLen); + rxBufPool[rxBufPoolIndex++] = newBuf; + } + } + } + else + { + u16_t i; + + DbgPrint("Can't find tag, pkt_len: 0x%04x, tag: 0x%04x\n", + pktLen, pktTag); + + #if 0 + for(i = 0; i < 32; i++) + { + DbgPrint("%02x ", buf->data[index-16+i]); + + if ((i & 0xf) == 0xf) + DbgPrint("\n"); + } + #endif + + break; + } + } + + /* Free buffer */ + //zfwBufFree(adapter, pUsbRxTransfer->buf, 0); + zfwBufFree(dev, buf, 0); + + for(ii = 0; ii < rxBufPoolIndex; ii++) + { + zfiUsbRecvPerPkt(dev, rxBufPool[ii]); + } +} +#endif + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfUsbInit */ +/* Initialize USB resource. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* */ +/* OUTPUTS */ +/* None */ +/* */ +/* AUTHOR */ +/* Stephen Chen ZyDAS Technology Corporation 2005.12 */ +/* */ +/************************************************************************/ +void zfUsbInit(zdev_t* dev) +{ + /* Initialize Rx & INT endpoint for receiving data & interrupt */ + zfwUsbEnableRxEpt(dev, USB_ENDPOINT_RX_INDEX); + zfwUsbEnableIntEpt(dev, USB_ENDPOINT_INT_INDEX); + + return; +} + + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfUsbFree */ +/* Free PCI resource. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* */ +/* OUTPUTS */ +/* None */ +/* */ +/* AUTHOR */ +/* Stephen Chen ZyDAS Technology Corporation 2005.12 */ +/* */ +/************************************************************************/ +void zfUsbFree(zdev_t* dev) +{ + struct zsHpPriv *halPriv; + + zmw_get_wlan_dev(dev); + + halPriv = (struct zsHpPriv*)wd->hpPrivate; + +#ifdef ZM_OTUS_RX_STREAM_MODE + if ( halPriv->remainBuf != NULL ) + { + zfwBufFree(dev, halPriv->remainBuf, 0); + } +#endif + + return; +} + +void zfHpSendBeacon(zdev_t* dev, zbuf_t* buf, u16_t len) +{ + u32_t hw, lw; + u16_t i; + zmw_get_wlan_dev(dev); + + /* Write to beacon buffer (ZM_BEACON_BUFFER_ADDRESS) */ + for (i = 0; i<len; i+=4) + { + lw = zmw_tx_buf_readh(dev, buf, i); + hw = zmw_tx_buf_readh(dev, buf, i+2); + + zfDelayWriteInternalReg(dev, ZM_BEACON_BUFFER_ADDRESS+i, (hw<<16)+lw); + } + + /* Beacon PCLP header */ + if (((struct zsHpPriv*)wd->hpPrivate)->hwFrequency < 3000) + { + zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PLCP, ((len+4)<<(3+16))+0x0400); + } + else + { + zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PLCP, ((len+4)<<(16))+0x001b); + } + + /* Beacon length (include CRC32) */ + zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_LENGTH, len+4); + + /* Beacon Ready */ + zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_CTRL, 1); + zfFlushDelayWrite(dev); + + /* Free beacon buf */ + zfwBufFree(dev, buf, 0); + + return; +} + + +#define ZM_STATUS_TX_COMP 0x00 +#define ZM_STATUS_RETRY_COMP 0x01 +#define ZM_STATUS_TX_FAILED 0x02 +void zfiUsbRegIn(zdev_t* dev, u32_t* rsp, u16_t rspLen) +{ + //u8_t len, type, i; + u8_t type; + u8_t *u8rsp; + u16_t status; + u32_t bitmap; + zmw_get_wlan_dev(dev); + + zm_msg0_mm(ZM_LV_3, "zfiUsbRegIn()"); + + u8rsp = (u8_t *)rsp; + + //len = *u8rsp; + type = *(u8rsp+1); + u8rsp = u8rsp+4; + + + /* Interrupt event */ + if ((type & 0xC0) == 0xC0) + { + if (type == 0xC0) + { + zfCoreEvent(dev, 0, u8rsp); + + } + else if (type == 0xC1) + { +#if 0 + { + u16_t i; + DbgPrint("rspLen=%d\n", rspLen); + for (i=0; i<(rspLen/4); i++) + { + DbgPrint("rsp[%d]=0x%lx\n", i, rsp[i]); + } + } +#endif + status = (u16_t)(rsp[3] >> 16); + + ////6789 + rsp[8] = rsp[8] >> 2 | (rsp[9] & 0x1) << 6; + switch (status) + { + case ZM_STATUS_RETRY_COMP : + zfCoreEvent(dev, 1, u8rsp); + break; + case ZM_STATUS_TX_FAILED : + zfCoreEvent(dev, 2, u8rsp); + break; + case ZM_STATUS_TX_COMP : + zfCoreEvent(dev, 3, u8rsp); + break; + } + } + else if (type == 0xC2) + { + zfBeaconCfgInterrupt(dev, u8rsp); + } + else if (type == 0xC3) + { + zfEndOfAtimWindowInterrupt(dev); + } + else if (type == 0xC4) + { +#if 0 + { + u16_t i; + DbgPrint("0xC2:rspLen=%d\n", rspLen); + for (i=0; i<(rspLen/4); i++) + { + DbgPrint("0xC2:rsp[%d]=0x%lx\n", i, rsp[i]); + } + } +#endif + bitmap = (rsp[1] >> 16) + ((rsp[2] & 0xFFFF) << 16 ); + //zfBawCore(dev, (u16_t)rsp[1] & 0xFFFF, bitmap, (u16_t)(rsp[2] >> 16) & 0xFF); + } + else if (type == 0xC5) + { + u16_t i; +#if 0 + + for (i=0; i<(rspLen/4); i++) { + DbgPrint("0xC5:rsp[%d]=0x%lx\n", i, rsp[i]); + } +#endif + for (i=1; i<(rspLen/4); i++) { + u8rsp = (u8_t *)(rsp+i); + //DbgPrint("0xC5:rsp[%d]=0x%lx\n", i, ((u32_t*)u8rsp)[0]); + zfCoreEvent(dev, 4, u8rsp); + } + } + else if (type == 0xC6) + { + zm_debug_msg0("\n\n WatchDog interrupt!!! : 0xC6 \n\n"); + if (wd->zfcbHwWatchDogNotify != NULL) + { + wd->zfcbHwWatchDogNotify(dev); + } + } + else if (type == 0xC8) + { + //PZSW_ADAPTER adapter; + + // for SPI flash program chk Flag + zfwDbgProgrameFlashChkDone(dev); + } + else if (type == 0xC9) + { + struct zsHpPriv* hpPriv=wd->hpPrivate; + + zm_debug_msg0("##### Tx retransmission 5 times event #####"); + + /* correct tx retransmission issue */ + hpPriv->retransmissionEvent = 1; + } + } + else + { + zfIdlRsp(dev, rsp, rspLen); + } +} + + +#define ZM_PROGRAM_RAM_ADDR 0x200000 //0x1000 //0x700000 +#define FIRMWARE_DOWNLOAD 0x30 +#define FIRMWARE_DOWNLOAD_COMP 0x31 +#define FIRMWARE_CONFIRM 0x32 + +u16_t zfFirmwareDownload(zdev_t* dev, u32_t* fw, u32_t len, u32_t offset) +{ + u16_t ret = ZM_SUCCESS; + u32_t uCodeOfst = offset; + u8_t *image, *ptr; + u32_t result; + + image = (u8_t*) fw; + ptr = image; + + while (len > 0) + { + u32_t translen = (len > 4096) ? 4096 : len; + + result = zfwUsbSubmitControl(dev, FIRMWARE_DOWNLOAD, + (u16_t) (uCodeOfst >> 8), + 0, image, translen); + + if (result != ZM_SUCCESS) + { + zm_msg0_init(ZM_LV_0, "FIRMWARE_DOWNLOAD failed"); + ret = 1; + goto exit; + } + + len -= translen; + image += translen; + uCodeOfst += translen; // in Word (16 bit) + + result = 0; + } + + /* If download firmware success, issue a command to firmware */ + if (ret == 0) + { + result = zfwUsbSubmitControl(dev, FIRMWARE_DOWNLOAD_COMP, + 0, 0, NULL, 0); + + if (result != ZM_SUCCESS) + { + zm_msg0_init(ZM_LV_0, "FIRMWARE_DOWNLOAD_COMP failed"); + ret = 1; + goto exit; + } + } + +#if 0 + /* PCI code */ + /* Wait for firmware ready */ + result = zfwUsbSubmitControl(dev, FIRMWARE_CONFIRM, USB_DIR_IN | 0x40, + 0, 0, &ret_value, sizeof(ret_value), HZ); + + if (result != 0) + { + zm_msg0_init(ZM_LV_0, "Can't receive firmware ready: ", result); + ret = 1; + } +#endif + +exit: + + return ret; + +} + +u16_t zfFirmwareDownloadNotJump(zdev_t* dev, u32_t* fw, u32_t len, u32_t offset) +{ + u16_t ret = ZM_SUCCESS; + u32_t uCodeOfst = offset; + u8_t *image, *ptr; + u32_t result; + + image = (u8_t*) fw; + ptr = image; + + while (len > 0) + { + u32_t translen = (len > 4096) ? 4096 : len; + + result = zfwUsbSubmitControl(dev, FIRMWARE_DOWNLOAD, + (u16_t) (uCodeOfst >> 8), + 0, image, translen); + + if (result != ZM_SUCCESS) + { + zm_msg0_init(ZM_LV_0, "FIRMWARE_DOWNLOAD failed"); + ret = 1; + goto exit; + } + + len -= translen; + image += translen; + uCodeOfst += translen; // in Word (16 bit) + + result = 0; + } + +exit: + + return ret; + +} + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfIdlGetFreeTxdCount */ +/* Get free PCI PCI TxD count. */ +/* */ +/* INPUTS */ +/* dev : device pointer */ +/* */ +/* OUTPUTS */ +/* None */ +/* */ +/* AUTHOR */ +/* Stephen ZyDAS Technology Corporation 2006.6 */ +/* */ +/************************************************************************/ +u32_t zfHpGetFreeTxdCount(zdev_t* dev) +{ + return zfwUsbGetFreeTxQSize(dev); +} + +u32_t zfHpGetMaxTxdCount(zdev_t* dev) +{ + //return 8; + return zfwUsbGetMaxTxQSize(dev); +} + +void zfiUsbRegOutComplete(zdev_t* dev) +{ + return; +} + +extern void zfPushVtxq(zdev_t* dev); + +void zfiUsbOutComplete(zdev_t* dev, zbuf_t *buf, u8_t status, u8_t *hdr) { +#ifndef ZM_ENABLE_AGGREGATION + if (buf) { + zfwBufFree(dev, buf, 0); + } +#else + #ifdef ZM_BYPASS_AGGR_SCHEDULING + //Simply free the buf since BA retransmission is done in the firmware + if (buf) + { + zfwBufFree(dev, buf, 0); + } + zfPushVtxq(dev); + #else + zmw_get_wlan_dev(dev); + + #ifdef ZM_ENABLE_FW_BA_RETRANSMISSION + //Simply free the buf since BA retransmission is done in the firmware + if (buf) + { + zfwBufFree(dev, buf, 0); + } + #else + u8_t agg; + u16_t frameType; + + if(!hdr && buf) { + zfwBufFree(dev, buf, 0); + //zm_debug_msg0("buf Free due to hdr == NULL"); + return; + } + + if(hdr && buf) { + frameType = hdr[8] & 0xf; + agg = (u8_t)(hdr[2] >> 5 ) & 0x1; + //zm_debug_msg1("AGG=", agg); + + if (!status) { + if (agg) { + //delete buf in ba fail queue?? + //not ganna happen? + } + else { + zfwBufFree(dev, buf, 0); + } + } + else { + if (agg) { + //don't do anything + //zfwBufFree(dev, buf, 0); + } + else { + zfwBufFree(dev, buf, 0); + } + } + } + #endif + + if (wd->state != ZM_WLAN_STATE_ENABLED) { + return; + } + + if( (wd->wlanMode == ZM_MODE_AP) || + (wd->wlanMode == ZM_MODE_INFRASTRUCTURE && wd->sta.EnableHT) || + (wd->wlanMode == ZM_MODE_PSEUDO) ) { + zfAggTxScheduler(dev, 0); + } + #endif +#endif + + return; + +} + diff --git a/drivers/staging/otus/hal/hpusb.h b/drivers/staging/otus/hal/hpusb.h new file mode 100644 index 000000000000..35a0c5668cea --- /dev/null +++ b/drivers/staging/otus/hal/hpusb.h @@ -0,0 +1,437 @@ +/* + * Copyright (c) 2000-2005 ZyDAS Technology Corporation + * Copyright (c) 2007-2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +/* Module Name : ud_defs.h */ +/* */ +/* Abstract */ +/* This module contains USB data structure definitions. */ +/* */ +/* NOTES */ +/* None */ +/* */ +/************************************************************************/ + +#ifndef _HPUSB_H +#define _HPUSB_H + +#define ZM_OTUS_ENABLE_RETRY_FREQ_CHANGE +#define ZM_BEACON_BUFFER_ADDRESS 0x117900 + +#define ZM_MAX_CMD_SIZE 64 +#define ZM_HAL_MAX_EEPROM_REQ 510 +#define ZM_HAL_MAX_EEPROM_PRQ 2 + +/* For USB STREAM mode */ +#ifdef ZM_DISABLE_AMSDU8K_SUPPORT +#define ZM_MAX_USB_IN_TRANSFER_SIZE 4096 +#else +#define ZM_MAX_USB_IN_TRANSFER_SIZE 8192 +#endif +#define ZM_USB_STREAM_MODE_TAG_LEN 4 +#define ZM_USB_STREAM_MODE_TAG 0x4e00 +#define ZM_USB_MAX_EPINT_BUFFER 64 + +struct zsCmdQ +{ + u16_t src; + u16_t cmdLen; + u8_t* buf; + u32_t cmd[ZM_MAX_CMD_SIZE/4]; +}; + +struct zsCommand +{ + u16_t delayWcmdCount; + u32_t delayWcmdAddr[(ZM_CMD_QUEUE_SIZE-4)/4]; + u32_t delayWcmdVal[(ZM_CMD_QUEUE_SIZE-4)/4]; +}; + +struct zsHalRxInfo +{ + u32_t currentRSSI[7]; /* RSSI combined */ + u32_t currentRxEVM[14]; + u32_t currentRxDataMT; + u32_t currentRxDataMCS; + u32_t currentRxDataBW; + u32_t currentRxDataSG; +}; + +struct zsHpPriv +{ + u16_t hwFrequency; + u8_t hwBw40; + u8_t hwExtOffset; + + u8_t disableDfsCh; + + u32_t halCapability; + + /* Fortunately the second loop can be disabled with a bit */ + /* called en_pd_dc_offset_thr */ + u8_t hwNotFirstInit; + + /* command queue */ + u16_t cmdHead; + u16_t cmdTail; +#ifdef ZM_XP_USB_MULTCMD + u16_t cmdSend; // Used for Mult send USB cmd +#endif + struct zsCmdQ cmdQ[ZM_CMD_QUEUE_SIZE]; + u16_t cmdPending; + struct zsCommand cmd; /* buffer for delayed commands */ + u8_t ledMode[2]; + u32_t ctlBusy; + u32_t extBusy; + + /* + * ANI & Radar support. + */ + u32_t procPhyErr; /* Process Phy errs */ + u8_t hasHwPhyCounters; /* Hardware has phy counters */ + u32_t aniPeriod; /* ani update list period */ + struct zsAniStats stats; /* various statistics */ + struct zsAniState *curani; /* cached last reference */ + struct zsAniState ani[50]; /* per-channel state */ + + /* + * Ani tables that change between the 5416 and 5312. + * These get set at attach time. + * XXX don't belong here + * XXX need better explanation + */ + s32_t totalSizeDesired[5]; + s32_t coarseHigh[5]; + s32_t coarseLow[5]; + s32_t firpwr[5]; + + /* + * ANI related PHY register value. + */ + u32_t regPHYDesiredSZ; + u32_t regPHYFindSig; + u32_t regPHYAgcCtl1; + u32_t regPHYSfcorr; + u32_t regPHYSfcorrLow; + u32_t regPHYTiming5; + u32_t regPHYCckDetect; + + u32_t eepromImage[1024]; + u32_t eepromImageIndex; + u32_t eepromImageRdReq; + + u8_t halReInit; + + u8_t OpFlags; + + u8_t tPow2xCck[4]; + u8_t tPow2x2g[4]; + u8_t tPow2x2g24HeavyClipOffset; + u8_t tPow2x2gHt20[8]; + u8_t tPow2x2gHt40[8]; + u8_t tPow2x5g[4]; + u8_t tPow2x5gHt20[8]; + u8_t tPow2x5gHt40[8]; + + /* hwBBHeavyClip : used compatibility */ + /* 0 : dongle not support. */ + /* !0: support heavy clip. */ + u8_t hwBBHeavyClip; + u8_t enableBBHeavyClip; /* 0=>force disable 1=>enable */ + u8_t doBBHeavyClip; /* set 1 if heavy clip need by each frequency switch */ + u32_t setValueHeavyClip; /* save setting value for heavy clip when completed routine */ + + /* + * Rxdata RSSI, EVM, Rate etc... + */ + struct zsHalRxInfo halRxInfo; + + u32_t usbSendBytes; + u32_t usbAcSendBytes[4]; + + u16_t aggMaxDurationBE; + u32_t aggPktNum; + + u16_t txop[4]; + u16_t cwmin[4]; + u16_t cwmax[4]; + u8_t strongRSSI; + u8_t rxStrongRSSI; + + u8_t slotType; //0->20us, 1=>9us + +#ifdef ZM_OTUS_RX_STREAM_MODE + u16_t usbRxRemainLen; + u16_t usbRxPktLen; + u16_t usbRxPadLen; + u16_t usbRxTransferLen; + zbuf_t *remainBuf; +#endif + + u8_t dot11Mode; + + u8_t ibssBcnEnabled; + u32_t ibssBcnInterval; + + // For re-issue the frequency change command + u32_t latestFrequency; + u8_t latestBw40; + u8_t latestExtOffset; + u8_t freqRetryCounter; + + u8_t recordFreqRetryCounter; + u8_t isSiteSurvey; + u8_t coldResetNeedFreq; + + u64_t camRollCallTable; + u8_t currentAckRtsTpc; + + /* #1 Save the initial value of the related RIFS register settings */ + //u32_t isInitialPhy; + u32_t initDesiredSigSize; + u32_t initAGC; + u32_t initAgcControl; + u32_t initSearchStartDelay; + u32_t initRIFSSearchParams; + u32_t initFastChannelChangeControl; + + /* Dynamic SIFS for retransmission event */ + u8_t retransmissionEvent; + u8_t latestSIFS; +}; + +extern u32_t zfHpLoadEEPROMFromFW(zdev_t* dev); + + +typedef u8_t A_UINT8; +typedef s8_t A_INT8; +typedef u16_t A_UINT16; +typedef u32_t A_UINT32; +#define __ATTRIB_PACK + +#pragma pack (push, 1) + +#define AR5416_EEP_VER 0xE +#define AR5416_EEP_VER_MINOR_MASK 0xFFF +#define AR5416_EEP_NO_BACK_VER 0x1 +#define AR5416_EEP_MINOR_VER_2 0x2 // Adds modal params txFrameToPaOn, txFrametoDataStart, ht40PowerInc +#define AR5416_EEP_MINOR_VER_3 0x3 // Adds modal params bswAtten, bswMargin, swSettle and base OpFlags for HT20/40 Disable + +// 16-bit offset location start of calibration struct +#define AR5416_EEP_START_LOC 256 +#define AR5416_NUM_5G_CAL_PIERS 8 +#define AR5416_NUM_2G_CAL_PIERS 4 +#define AR5416_NUM_5G_20_TARGET_POWERS 8 +#define AR5416_NUM_5G_40_TARGET_POWERS 8 +#define AR5416_NUM_2G_CCK_TARGET_POWERS 3 +#define AR5416_NUM_2G_20_TARGET_POWERS 4 +#define AR5416_NUM_2G_40_TARGET_POWERS 4 +#define AR5416_NUM_CTLS 24 +#define AR5416_NUM_BAND_EDGES 8 +#define AR5416_NUM_PD_GAINS 4 +#define AR5416_PD_GAINS_IN_MASK 4 +#define AR5416_PD_GAIN_ICEPTS 5 +#define AR5416_EEPROM_MODAL_SPURS 5 +#define AR5416_MAX_RATE_POWER 63 +#define AR5416_NUM_PDADC_VALUES 128 +#define AR5416_NUM_RATES 16 +#define AR5416_BCHAN_UNUSED 0xFF +#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 +#define AR5416_OPFLAGS_11A 0x01 +#define AR5416_OPFLAGS_11G 0x02 +#define AR5416_OPFLAGS_5G_HT40 0x04 +#define AR5416_OPFLAGS_2G_HT40 0x08 +#define AR5416_OPFLAGS_5G_HT20 0x10 +#define AR5416_OPFLAGS_2G_HT20 0x20 +#define AR5416_EEPMISC_BIG_ENDIAN 0x01 +#define FREQ2FBIN(x,y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) +#define AR5416_MAX_CHAINS 2 +#define AR5416_ANT_16S 25 + +#define AR5416_NUM_ANT_CHAIN_FIELDS 7 +#define AR5416_NUM_ANT_COMMON_FIELDS 4 +#define AR5416_SIZE_ANT_CHAIN_FIELD 3 +#define AR5416_SIZE_ANT_COMMON_FIELD 4 +#define AR5416_ANT_CHAIN_MASK 0x7 +#define AR5416_ANT_COMMON_MASK 0xf +#define AR5416_CHAIN_0_IDX 0 +#define AR5416_CHAIN_1_IDX 1 +#define AR5416_CHAIN_2_IDX 2 + + +/* Capabilities Enum */ +typedef enum { + EEPCAP_COMPRESS_DIS = 0x0001, + EEPCAP_AES_DIS = 0x0002, + EEPCAP_FASTFRAME_DIS = 0x0004, + EEPCAP_BURST_DIS = 0x0008, + EEPCAP_MAXQCU_M = 0x01F0, + EEPCAP_MAXQCU_S = 4, + EEPCAP_HEAVY_CLIP_EN = 0x0200, + EEPCAP_KC_ENTRIES_M = 0xF000, + EEPCAP_KC_ENTRIES_S = 12, +} EEPROM_CAPABILITIES; + +typedef enum Ar5416_Rates { + rate6mb, rate9mb, rate12mb, rate18mb, + rate24mb, rate36mb, rate48mb, rate54mb, + rate1l, rate2l, rate2s, rate5_5l, + rate5_5s, rate11l, rate11s, rateXr, + rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, + rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, + rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, + rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, + rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, + Ar5416RateSize +} AR5416_RATES; + +typedef struct eepFlags { + A_UINT8 opFlags; + A_UINT8 eepMisc; +} __ATTRIB_PACK EEP_FLAGS; + +#define AR5416_CHECKSUM_LOCATION (AR5416_EEP_START_LOC + 1) +typedef struct BaseEepHeader { + A_UINT16 length; + A_UINT16 checksum; + A_UINT16 version; + EEP_FLAGS opCapFlags; + A_UINT16 regDmn[2]; + A_UINT8 macAddr[6]; + A_UINT8 rxMask; + A_UINT8 txMask; + A_UINT16 rfSilent; + A_UINT16 blueToothOptions; + A_UINT16 deviceCap; + A_UINT32 binBuildNumber; + A_UINT8 deviceType; + A_UINT8 futureBase[33]; +} __ATTRIB_PACK BASE_EEP_HEADER; // 64 B + +typedef struct spurChanStruct { + A_UINT16 spurChan; + A_UINT8 spurRangeLow; + A_UINT8 spurRangeHigh; +} __ATTRIB_PACK SPUR_CHAN; + +typedef struct ModalEepHeader { + A_UINT32 antCtrlChain[AR5416_MAX_CHAINS]; // 12 + A_UINT32 antCtrlCommon; // 4 + A_INT8 antennaGainCh[AR5416_MAX_CHAINS]; // 3 + A_UINT8 switchSettling; // 1 + A_UINT8 txRxAttenCh[AR5416_MAX_CHAINS]; // 3 + A_UINT8 rxTxMarginCh[AR5416_MAX_CHAINS]; // 3 + A_INT8 adcDesiredSize; // 1 + A_INT8 pgaDesiredSize; // 1 + A_UINT8 xlnaGainCh[AR5416_MAX_CHAINS]; // 3 + A_UINT8 txEndToXpaOff; // 1 + A_UINT8 txEndToRxOn; // 1 + A_UINT8 txFrameToXpaOn; // 1 + A_UINT8 thresh62; // 1 + A_INT8 noiseFloorThreshCh[AR5416_MAX_CHAINS]; // 3 + A_UINT8 xpdGain; // 1 + A_UINT8 xpd; // 1 + A_INT8 iqCalICh[AR5416_MAX_CHAINS]; // 1 + A_INT8 iqCalQCh[AR5416_MAX_CHAINS]; // 1 + A_UINT8 pdGainOverlap; // 1 + A_UINT8 ob; // 1 + A_UINT8 db; // 1 + A_UINT8 xpaBiasLvl; // 1 + A_UINT8 pwrDecreaseFor2Chain; // 1 + A_UINT8 pwrDecreaseFor3Chain; // 1 -> 48 B + A_UINT8 txFrameToDataStart; // 1 + A_UINT8 txFrameToPaOn; // 1 + A_UINT8 ht40PowerIncForPdadc; // 1 + A_UINT8 bswAtten[AR5416_MAX_CHAINS]; // 3 + A_UINT8 bswMargin[AR5416_MAX_CHAINS]; // 3 + A_UINT8 swSettleHt40; // 1 + A_UINT8 futureModal[22]; // + SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS]; // 20 B +} __ATTRIB_PACK MODAL_EEP_HEADER; // == 100 B + +typedef struct calDataPerFreq { + A_UINT8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; + A_UINT8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; +} __ATTRIB_PACK CAL_DATA_PER_FREQ; + +typedef struct CalTargetPowerLegacy { + A_UINT8 bChannel; + A_UINT8 tPow2x[4]; +} __ATTRIB_PACK CAL_TARGET_POWER_LEG; + +typedef struct CalTargetPowerHt { + A_UINT8 bChannel; + A_UINT8 tPow2x[8]; +} __ATTRIB_PACK CAL_TARGET_POWER_HT; + +#if defined(ARCH_BIG_ENDIAN) || defined(BIG_ENDIAN) +typedef struct CalCtlEdges { + A_UINT8 bChannel; + A_UINT8 flag :2, + tPower :6; +} __ATTRIB_PACK CAL_CTL_EDGES; +#else +typedef struct CalCtlEdges { + A_UINT8 bChannel; + A_UINT8 tPower :6, + flag :2; +} __ATTRIB_PACK CAL_CTL_EDGES; +#endif + +typedef struct CalCtlData { + CAL_CTL_EDGES ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; +} __ATTRIB_PACK CAL_CTL_DATA; + +typedef struct ar5416Eeprom { + BASE_EEP_HEADER baseEepHeader; // 64 B + A_UINT8 custData[64]; // 64 B + MODAL_EEP_HEADER modalHeader[2]; // 200 B + A_UINT8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; + A_UINT8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; + CAL_DATA_PER_FREQ calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS]; + CAL_DATA_PER_FREQ calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]; + CAL_TARGET_POWER_LEG calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS]; + CAL_TARGET_POWER_HT calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; + CAL_TARGET_POWER_HT calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; + CAL_TARGET_POWER_LEG calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; + CAL_TARGET_POWER_LEG calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS]; + CAL_TARGET_POWER_HT calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; + CAL_TARGET_POWER_HT calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; + A_UINT8 ctlIndex[AR5416_NUM_CTLS]; + CAL_CTL_DATA ctlData[AR5416_NUM_CTLS]; + A_UINT8 padding; +} __ATTRIB_PACK AR5416_EEPROM; + +#pragma pack (pop) + +typedef enum ConformanceTestLimits { + FCC = 0x10, + MKK = 0x40, + ETSI = 0x30, + SD_NO_CTL = 0xE0, + NO_CTL = 0xFF, + CTL_MODE_M = 0xF, + CTL_11A = 0, + CTL_11B = 1, + CTL_11G = 2, + CTL_TURBO = 3, + CTL_108G = 4, + CTL_2GHT20 = 5, + CTL_5GHT20 = 6, + CTL_2GHT40 = 7, + CTL_5GHT40 = 8, +} ATH_CTLS; + +#endif /* #ifndef _HPUSB_H */ diff --git a/drivers/staging/otus/hal/otus.ini b/drivers/staging/otus/hal/otus.ini new file mode 100644 index 000000000000..34efeb6c285b --- /dev/null +++ b/drivers/staging/otus/hal/otus.ini @@ -0,0 +1,414 @@ +/* 8602 : update mismatch register between NDIS and ART */ +static const u32_t ar5416Modes[][6] = { +/* Register A-20 A-20/40 G-20/40 G-20 G-Turbo */ + {0x9800, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0}, + {0x9804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0}, + {0x9808, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x980c, 0xad848e19, 0xad848e19, 0xad848e19, 0xad848e19, 0}, + {0x9810, 0x7d14e000, 0x7d14e000, 0x7d14e000, 0x7d14e000, 0}, + {0x9814, 0x9c0a9f6b, 0x9c0a9f6b, 0x9c0a9f6b, 0x9c0a9f6b, 0}, + {0x9818, 0x00000090, 0x00000090, 0x00000090, 0x00000090, 0}, + {0x981c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0}, + {0x9824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0}, + {0x9828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0}, + {0x982c, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, 0}, + {0x9830, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0}, + {0x9838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0}, + {0x983c, 0x00200400, 0x00200400, 0x00200400, 0x00200400, 0}, + {0x9840, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e, 0}, + {0x9844, 0x1372161e, 0x13721c1e, 0x13721c24, 0x137216a4, 0}, + {0x9848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0}, + {0x984c, 0x1284233c, 0x1284233c, 0x1284233c, 0x1284233c, 0}, + {0x9850, 0x6c48b4e4, 0x6c48b4e4, 0x6c48b0e4, 0x6c48b0e4, 0}, + {0x9854, 0x00000859, 0x00000859, 0x00000859, 0x00000859, 0}, + {0x9858, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0}, + {0x985c, 0x31395c5e, 0x31395c5e, 0x31395c5e, 0x31395c5e, 0}, + {0x9860, 0x0004dd10, 0x0004dd10, 0x0004dd20, 0x0004dd20, 0}, + {0x9868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0}, + {0x986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0}, + {0x9900, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9904, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9908, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x990c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0}, + {0x9918, 0x00000118, 0x00000230, 0x00000268, 0x00000134, 0}, + {0x991c, 0x10000fff, 0x10000fff, 0x10000fff, 0x10000fff, 0}, + {0x9920, 0x0510081c, 0x0510081c, 0x0510001c, 0x0510001c, 0}, + {0x9924, 0xd0058a15, 0xd0058a15, 0xd0058a15, 0xd0058a15, 0}, + {0x9928, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0}, + {0x992c, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0}, + {0x9934, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0}, + {0x9938, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0}, + {0x993c, 0x0000007f, 0x0000007f, 0x0000007f, 0x0000007f, 0}, + {0x9944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0}, + {0x9948, 0x9280b212, 0x9280b212, 0x9280b212, 0x9280b212, 0}, + {0x994c, 0x00020028, 0x00020028, 0x00020028, 0x00020028, 0}, + {0x9954, 0x5d50e188, 0x5d50e188, 0x5d50e188, 0x5d50e188, 0}, + {0x9958, 0x00081fff, 0x00081fff, 0x00081fff, 0x00081fff, 0}, + {0x9960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0}, + {0x9964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0}, + {0x9970, 0x190fb515, 0x190fb515, 0x190fb515, 0x190fb515, 0}, + {0x9974, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9978, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0}, + {0x997c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9980, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9984, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9988, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x998c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9990, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9994, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9998, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x999c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x99a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x99a4, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0}, + {0x99a8, 0x001fff00, 0x001fff00, 0x001fff00, 0x001fff00, 0}, + {0x99ac, 0x006f00c4, 0x006f00c4, 0x006f00c4, 0x006f00c4, 0}, + {0x99b0, 0x03051000, 0x03051000, 0x03051000, 0x03051000, 0}, + {0x99b4, 0x00000820, 0x00000820, 0x00000820, 0x00000820, 0}, + {0x99c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0}, + {0x99c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0}, + {0x99c8, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0}, + {0x99cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0}, + {0x99d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0}, + {0x99d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x99d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x99dc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x99e0, 0x00000200, 0x00000200, 0x00000200, 0x00000200, 0}, + {0x99e4, 0x64646464, 0x64646464, 0x64646464, 0x64646464, 0}, + {0x99e8, 0x3c787878, 0x3c787878, 0x3c787878, 0x3c787878, 0}, + {0x99ec, 0x000000aa, 0x000000aa, 0x000000aa, 0x000000aa, 0}, + {0x99f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x99fc, 0x00001042, 0x00001042, 0x00001042, 0x00001042, 0}, + {0x9a00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9a04, 0x00000040, 0x00000040, 0x00000040, 0x00000040, 0}, + {0x9a08, 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0}, + {0x9a0c, 0x000001a1, 0x000001a1, 0x00000141, 0x00000141, 0}, + {0x9a10, 0x000001e1, 0x000001e1, 0x00000181, 0x00000181, 0}, + {0x9a14, 0x00000021, 0x00000021, 0x000001c1, 0x000001c1, 0}, + {0x9a18, 0x00000061, 0x00000061, 0x00000001, 0x00000001, 0}, + {0x9a1c, 0x00000168, 0x00000168, 0x00000041, 0x00000041, 0}, + {0x9a20, 0x000001a8, 0x000001a8, 0x000001a8, 0x000001a8, 0}, + {0x9a24, 0x000001e8, 0x000001e8, 0x000001e8, 0x000001e8, 0}, + {0x9a28, 0x00000028, 0x00000028, 0x00000028, 0x00000028, 0}, + {0x9a2c, 0x00000068, 0x00000068, 0x00000068, 0x00000068, 0}, + {0x9a30, 0x00000189, 0x00000189, 0x000000a8, 0x000000a8, 0}, + {0x9a34, 0x000001c9, 0x000001c9, 0x00000169, 0x00000169, 0}, + {0x9a38, 0x00000009, 0x00000009, 0x000001a9, 0x000001a9, 0}, + {0x9a3c, 0x00000049, 0x00000049, 0x000001e9, 0x000001e9, 0}, + {0x9a40, 0x00000089, 0x00000089, 0x00000029, 0x00000029, 0}, + {0x9a44, 0x00000170, 0x00000170, 0x00000069, 0x00000069, 0}, + {0x9a48, 0x000001b0, 0x000001b0, 0x00000190, 0x00000190, 0}, + {0x9a4c, 0x000001f0, 0x000001f0, 0x000001d0, 0x000001d0, 0}, + {0x9a50, 0x00000030, 0x00000030, 0x00000010, 0x00000010, 0}, + {0x9a54, 0x00000070, 0x00000070, 0x00000050, 0x00000050, 0}, + {0x9a58, 0x00000191, 0x00000191, 0x00000090, 0x00000090, 0}, + {0x9a5c, 0x000001d1, 0x000001d1, 0x00000151, 0x00000151, 0}, + {0x9a60, 0x00000011, 0x00000011, 0x00000191, 0x00000191, 0}, + {0x9a64, 0x00000051, 0x00000051, 0x000001d1, 0x000001d1, 0}, + {0x9a68, 0x00000091, 0x00000091, 0x00000011, 0x00000011, 0}, + {0x9a6c, 0x000001b8, 0x000001b8, 0x00000051, 0x00000051, 0}, + {0x9a70, 0x000001f8, 0x000001f8, 0x00000198, 0x00000198, 0}, + {0x9a74, 0x00000038, 0x00000038, 0x000001d8, 0x000001d8, 0}, + {0x9a78, 0x00000078, 0x00000078, 0x00000018, 0x00000018, 0}, + {0x9a7c, 0x00000199, 0x00000199, 0x00000058, 0x00000058, 0}, + {0x9a80, 0x000001d9, 0x000001d9, 0x00000098, 0x00000098, 0}, + {0x9a84, 0x00000019, 0x00000019, 0x00000159, 0x00000159, 0}, + {0x9a88, 0x00000059, 0x00000059, 0x00000199, 0x00000199, 0}, + {0x9a8c, 0x00000099, 0x00000099, 0x000001d9, 0x000001d9, 0}, + {0x9a90, 0x000000d9, 0x000000d9, 0x00000019, 0x00000019, 0}, + {0x9a94, 0x000000f9, 0x000000f9, 0x00000059, 0x00000059, 0}, + {0x9a98, 0x000000f9, 0x000000f9, 0x00000099, 0x00000099, 0}, + {0x9a9c, 0x000000f9, 0x000000f9, 0x000000d9, 0x000000d9, 0}, + {0x9aa0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9aa4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9aa8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9aac, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9ab0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9ab4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9ab8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9abc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9ac0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9ac4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9ac8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9acc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9ad0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9ad4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9ad8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9adc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9ae0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9ae4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9ae8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9aec, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9af0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9af4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9af8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9afc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0}, + {0x9b00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9b04, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0}, + {0x9b08, 0x00000002, 0x00000002, 0x00000002, 0x00000002, 0}, + {0x9b0c, 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0}, + {0x9b10, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0}, + {0x9b14, 0x00000005, 0x00000005, 0x00000005, 0x00000005, 0}, + {0x9b18, 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0}, + {0x9b1c, 0x00000009, 0x00000009, 0x00000009, 0x00000009, 0}, + {0x9b20, 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a, 0}, + {0x9b24, 0x0000000b, 0x0000000b, 0x0000000b, 0x0000000b, 0}, + {0x9b28, 0x0000000c, 0x0000000c, 0x0000000c, 0x0000000c, 0}, + {0x9b2c, 0x0000000d, 0x0000000d, 0x0000000d, 0x0000000d, 0}, + {0x9b30, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0}, + {0x9b34, 0x00000011, 0x00000011, 0x00000011, 0x00000011, 0}, + {0x9b38, 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0}, + {0x9b3c, 0x00000013, 0x00000013, 0x00000013, 0x00000013, 0}, + {0x9b40, 0x00000014, 0x00000014, 0x00000014, 0x00000014, 0}, + {0x9b44, 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0}, + {0x9b48, 0x00000018, 0x00000018, 0x00000018, 0x00000018, 0}, + {0x9b4c, 0x00000019, 0x00000019, 0x00000019, 0x00000019, 0}, + {0x9b50, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0}, + {0x9b54, 0x0000001b, 0x0000001b, 0x0000001b, 0x0000001b, 0}, + {0x9b58, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c, 0}, + {0x9b5c, 0x0000001d, 0x0000001d, 0x0000001d, 0x0000001d, 0}, + {0x9b60, 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0}, + {0x9b64, 0x00000021, 0x00000021, 0x00000021, 0x00000021, 0}, + {0x9b68, 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0}, + {0x9b6c, 0x00000023, 0x00000023, 0x00000023, 0x00000023, 0}, + {0x9b70, 0x00000024, 0x00000024, 0x00000024, 0x00000024, 0}, + {0x9b74, 0x00000025, 0x00000025, 0x00000025, 0x00000025, 0}, + {0x9b78, 0x00000028, 0x00000028, 0x00000028, 0x00000028, 0}, + {0x9b7c, 0x00000029, 0x00000029, 0x00000029, 0x00000029, 0}, + {0x9b80, 0x0000002a, 0x0000002a, 0x0000002a, 0x0000002a, 0}, + {0x9b84, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b, 0}, + {0x9b88, 0x0000002c, 0x0000002c, 0x0000002c, 0x0000002c, 0}, + {0x9b8c, 0x0000002d, 0x0000002d, 0x0000002d, 0x0000002d, 0}, + {0x9b90, 0x00000030, 0x00000030, 0x00000030, 0x00000030, 0}, + {0x9b94, 0x00000031, 0x00000031, 0x00000031, 0x00000031, 0}, + {0x9b98, 0x00000032, 0x00000032, 0x00000032, 0x00000032, 0}, + {0x9b9c, 0x00000033, 0x00000033, 0x00000033, 0x00000033, 0}, + {0x9ba0, 0x00000034, 0x00000034, 0x00000034, 0x00000034, 0}, + {0x9ba4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0}, + {0x9ba8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0}, + {0x9bac, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0}, + {0x9bb0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0}, + {0x9bb4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0}, + {0x9bb8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0}, + {0x9bbc, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0}, + {0x9bc0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0}, + {0x9bc4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0}, + {0x9bc8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0}, + {0x9bcc, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0}, + {0x9bd0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0}, + {0x9bd4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0}, + {0x9bd8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0}, + {0x9bdc, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0}, + {0x9be0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0}, + {0x9be4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0}, + {0x9be8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0}, + {0x9bec, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0}, + {0x9bf0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0}, + {0x9bf4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0}, + {0x9bf8, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0}, + {0x9bfc, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0}, + {0x9c00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9c0c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9c10, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9c14, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9c18, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9c1c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9c20, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9c24, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9c28, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9c2c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9c30, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9c34, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9c38, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9c3c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9cf0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9cf4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9cf8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0x9cfc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa200, 0x00000008, 0x00000008, 0x0000000e, 0x0000000e, 0}, + {0xa204, 0x00000440, 0x00000440, 0x00000440, 0x00000440, 0}, + {0xa208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0}, + {0xa20c, 0x012e8160, 0x012e8160, 0x012a8160, 0x012a8160, 0}, + {0xa210, 0x40806333, 0x40806333, 0x40806333, 0x40806333, 0}, + {0xa214, 0x00106c10, 0x00106c10, 0x00106c10, 0x00106c10, 0}, + {0xa218, 0x009c4060, 0x009c4060, 0x009c4060, 0x009c4060, 0}, + {0xa21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0}, + {0xa220, 0x018830c6, 0x018830c6, 0x018830c6, 0x018830c6, 0}, + {0xa224, 0x00000400, 0x00000400, 0x00000400, 0x00000400, 0}, + {0xa228, 0x000009b5, 0x000009b5, 0x000009b5, 0x000009b5, 0}, + {0xa22c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa230, 0x00000108, 0x00000210, 0x00000210, 0x00000108, 0}, + {0xa234, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0}, + {0xa238, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0}, + {0xa23c, 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af, 0}, + {0xa240, 0x38490a20, 0x38490a20, 0x38490a20, 0x38490a20, 0}, + {0xa244, 0x00007bb6, 0x00007bb6, 0x00007bb6, 0x00007bb6, 0}, + {0xa248, 0x0fff3ffc, 0x0fff3ffc, 0x0fff3ffc, 0x0fff3ffc, 0}, + {0xa24c, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0}, + {0xa250, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, 0}, + {0xa254, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa258, 0x0cc75380, 0x0cc75380, 0x0cc75380, 0x0cc75380, 0}, + {0xa25c, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, 0}, + {0xa260, 0xdfa91f01, 0xdfa91f01, 0xdfa91f01, 0xdfa91f01, 0}, + {0xa264, 0x00418a11, 0x00418a11, 0x00418a11, 0x00418a11, 0}, + {0xa268, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa26c, 0x09249126, 0x09249126, 0x09249126, 0x09249126, 0}, + {0xa274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0}, + {0xa278, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0}, + {0xa27c, 0x051701ce, 0x051701ce, 0x051701ce, 0x051701ce, 0}, + {0xa300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0}, + {0xa304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0}, + {0xa308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0}, + {0xa30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0}, + {0xa310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0}, + {0xa314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0}, + {0xa318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0}, + {0xa31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0}, + {0xa320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0}, + {0xa324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0}, + {0xa328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0}, + {0xa32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa338, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa33c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa340, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa344, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa348, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0}, + {0xa34c, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0}, + {0xa350, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0}, + {0xa354, 0x0003ffff, 0x0003ffff, 0x0003ffff, 0x0003ffff, 0}, + {0xa358, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, 0}, + {0xa388, 0x08000000, 0x08000000, 0x08000000, 0x08000000, 0}, + {0xa38c, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0}, + {0xa390, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0}, + {0xa394, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0}, + {0xa398, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce, 0}, + {0xa39c, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0}, + {0xa3a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa3a4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa3a8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa3ac, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa3b0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa3b4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa3b8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa3bc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa3c0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa3c4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa3c8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa3cc, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0}, + {0xa3d0, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0}, + {0xa3d4, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0}, + {0xa3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0}, + {0xa3dc, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0}, + {0xa3e0, 0x000000c0, 0x000000c0, 0x000000c0, 0x000000c0, 0}, + {0xa848, 0x00180a65, 0x00180a65, 0x00180a68, 0x00180a68, 0}, + {0xa920, 0x0510001c, 0x0510001c, 0x0510001c, 0x0510001c, 0}, + {0xa960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0}, + {0xb20c, 0x012e8160, 0x012e8160, 0x012a8160, 0x012a8160, 0}, + {0xb26c, 0x09249126, 0x09249126, 0x09249126, 0x09249126, 0}, + {0xb848, 0x00180a65, 0x00180a65, 0x00180a68, 0x00180a68, 0}, + {0xb920, 0x0510001c, 0x0510001c, 0x0510001c, 0x0510001c, 0}, + {0xb960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0}, + {0xc20c, 0x012e8160, 0x012e8160, 0x012a8160, 0x012a8160, 0}, + {0xc26c, 0x09249126, 0x09249126, 0x09249126, 0x09249126, 0}, + //{0xc864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0}, + {0xc864, 0x0001c600, 0x0001c600, 0x0001c600, 0x0001c600, 0}, + {0xc95c, 0x004b6a8e, 0x004b6a8e, 0x004b6a8e, 0x004b6a8e, 0}, + {0xc968, 0x000003ce, 0x000003ce, 0x000003ce, 0x000003ce, 0}, + {0xc9bc, 0x00181400, 0x00181400, 0x00181400, 0x00181400, 0}, + {0xd270, 0x00820820, 0x00820820, 0x00820820, 0x00820820, 0}, + {0xd35c, 0x066c420f, 0x066c420f, 0x066c420f, 0x066c420f, 0}, + {0xd360, 0x0f282207, 0x0f282207, 0x0f282207, 0x0f282207, 0}, + {0xd364, 0x17601685, 0x17601685, 0x17601685, 0x17601685, 0}, + {0xd368, 0x1f801104, 0x1f801104, 0x1f801104, 0x1f801104, 0}, + {0xd36c, 0x37a00c03, 0x37a00c03, 0x37a00c03, 0x37a00c03, 0}, + {0xd370, 0x3fc40883, 0x3fc40883, 0x3fc40883, 0x3fc40883, 0}, + {0xd374, 0x57c00803, 0x57c00803, 0x57c00803, 0x57c00803, 0}, + {0xd378, 0x5fd80682, 0x5fd80682, 0x5fd80682, 0x5fd80682, 0}, + {0xd37c, 0x7fe00482, 0x7fe00482, 0x7fe00482, 0x7fe00482, 0}, + {0xd380, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, 0}, + {0xd384, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0} +}; + + +static const u32_t otusBank[][3] = { + //# bank 0 + {0x98b0, 0x1e5795e5, 0x1e5795e5}, + {0x98e0, 0x02008020, 0x02008020}, + //# bank 1 + {0x98b0, 0x02108421, 0x02108421}, + {0x98ec, 0x00000008, 0x00000008}, + //# bank 2 + {0x98b0, 0x0e73ff17, 0x0e73ff17}, + {0x98e0, 0x00000420, 0x00000420}, + //# bank 3 + {0x98f0, 0x01400018, 0x01c00018}, + //# bank 4 + {0x98b0, 0x000001a1, 0x000001a1}, + {0x98e8, 0x00000001, 0x00000001}, + //# bank 5 + {0x98b0, 0x00000013, 0x00000013}, + {0x98e4, 0x00000002, 0x00000002}, + //# bank 6 + {0x98b0, 0x00000000, 0x00000000}, + {0x98b0, 0x00000000, 0x00000000}, + {0x98b0, 0x00000000, 0x00000000}, + {0x98b0, 0x00000000, 0x00000000}, + {0x98b0, 0x00000000, 0x00000000}, + {0x98b0, 0x00004000, 0x00004000}, + {0x98b0, 0x00006c00, 0x00006c00}, + {0x98b0, 0x00002c00, 0x00002c00}, + {0x98b0, 0x00004800, 0x00004800}, + {0x98b0, 0x00004000, 0x00004000}, + {0x98b0, 0x00006000, 0x00006000}, + {0x98b0, 0x00001000, 0x00001000}, + {0x98b0, 0x00004000, 0x00004000}, + {0x98b0, 0x00007c00, 0x00007c00}, + {0x98b0, 0x00007c00, 0x00007c00}, + {0x98b0, 0x00007c00, 0x00007c00}, + {0x98b0, 0x00007c00, 0x00007c00}, + {0x98b0, 0x00007c00, 0x00007c00}, + {0x98b0, 0x00087c00, 0x00087c00}, + {0x98b0, 0x00007c00, 0x00007c00}, + {0x98b0, 0x00005400, 0x00005400}, + {0x98b0, 0x00000c00, 0x00000c00}, + {0x98b0, 0x00001800, 0x00001800}, + {0x98b0, 0x00007c00, 0x00007c00}, + {0x98b0, 0x00006c00, 0x00006c00}, + {0x98b0, 0x00006c00, 0x00006c00}, + {0x98b0, 0x00007c00, 0x00007c00}, + {0x98b0, 0x00002c00, 0x00002c00}, + {0x98b0, 0x00003c00, 0x00003c00}, + {0x98b0, 0x00003800, 0x00003800}, + {0x98b0, 0x00001c00, 0x00001c00}, + {0x98b0, 0x00000800, 0x00000800}, + {0x98b0, 0x00000408, 0x00000408}, + {0x98b0, 0x00004c15, 0x00004c15}, + {0x98b0, 0x00004188, 0x00004188}, + {0x98b0, 0x0000201e, 0x0000201e}, + {0x98b0, 0x00010408, 0x00010408}, + {0x98b0, 0x00000801, 0x00000801}, + {0x98b0, 0x00000c08, 0x00000c08}, + {0x98b0, 0x0000181e, 0x0000181e}, + {0x98b0, 0x00001016, 0x00001016}, + {0x98b0, 0x00002800, 0x00002800}, + {0x98b0, 0x00004010, 0x00004010}, + {0x98b0, 0x0000081c, 0x0000081c}, + {0x98b0, 0x00000115, 0x00000115}, + {0x98b0, 0x00000015, 0x00000015}, + {0x98b0, 0x00000066, 0x00000066}, + {0x98b0, 0x0000001c, 0x0000001c}, + {0x98b0, 0x00000000, 0x00000000}, + {0x98b0, 0x00000004, 0x00000004}, + {0x98b0, 0x00000015, 0x00000015}, + {0x98b0, 0x0000001f, 0x0000001f}, + {0x98e0, 0x00000000, 0x00000400}, + //# bank 7 + {0x98b0, 0x000000a0, 0x000000a0}, + {0x98b0, 0x00000000, 0x00000000}, + {0x98b0, 0x00000040, 0x00000040}, + {0x98f0, 0x0000001c, 0x0000001c} +}; |