diff options
Diffstat (limited to 'drivers/staging/qlge/qlge_main.c')
| -rw-r--r-- | drivers/staging/qlge/qlge_main.c | 1380 |
1 files changed, 706 insertions, 674 deletions
diff --git a/drivers/staging/qlge/qlge_main.c b/drivers/staging/qlge/qlge_main.c index e6b7baa12cd6..5516be3af898 100644 --- a/drivers/staging/qlge/qlge_main.c +++ b/drivers/staging/qlge/qlge_main.c @@ -42,6 +42,7 @@ #include <net/ip6_checksum.h> #include "qlge.h" +#include "qlge_devlink.h" char qlge_driver_name[] = DRV_NAME; const char qlge_driver_version[] = DRV_VERSION; @@ -89,16 +90,16 @@ static const struct pci_device_id qlge_pci_tbl[] = { MODULE_DEVICE_TABLE(pci, qlge_pci_tbl); -static int ql_wol(struct ql_adapter *); +static int qlge_wol(struct qlge_adapter *); static void qlge_set_multicast_list(struct net_device *); -static int ql_adapter_down(struct ql_adapter *); -static int ql_adapter_up(struct ql_adapter *); +static int qlge_adapter_down(struct qlge_adapter *); +static int qlge_adapter_up(struct qlge_adapter *); /* This hardware semaphore causes exclusive access to * resources shared between the NIC driver, MPI firmware, * FCOE firmware and the FC driver. */ -static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask) +static int qlge_sem_trylock(struct qlge_adapter *qdev, u32 sem_mask) { u32 sem_bits = 0; @@ -132,26 +133,26 @@ static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask) return -EINVAL; } - ql_write32(qdev, SEM, sem_bits | sem_mask); - return !(ql_read32(qdev, SEM) & sem_bits); + qlge_write32(qdev, SEM, sem_bits | sem_mask); + return !(qlge_read32(qdev, SEM) & sem_bits); } -int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask) +int qlge_sem_spinlock(struct qlge_adapter *qdev, u32 sem_mask) { unsigned int wait_count = 30; do { - if (!ql_sem_trylock(qdev, sem_mask)) + if (!qlge_sem_trylock(qdev, sem_mask)) return 0; udelay(100); } while (--wait_count); return -ETIMEDOUT; } -void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask) +void qlge_sem_unlock(struct qlge_adapter *qdev, u32 sem_mask) { - ql_write32(qdev, SEM, sem_mask); - ql_read32(qdev, SEM); /* flush */ + qlge_write32(qdev, SEM, sem_mask); + qlge_read32(qdev, SEM); /* flush */ } /* This function waits for a specific bit to come ready @@ -159,13 +160,13 @@ void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask) * process, but is also used in kernel thread API such as * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid. */ -int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit) +int qlge_wait_reg_rdy(struct qlge_adapter *qdev, u32 reg, u32 bit, u32 err_bit) { u32 temp; int count; for (count = 0; count < UDELAY_COUNT; count++) { - temp = ql_read32(qdev, reg); + temp = qlge_read32(qdev, reg); /* check for errors */ if (temp & err_bit) { @@ -186,13 +187,13 @@ int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit) /* The CFG register is used to download TX and RX control blocks * to the chip. This function waits for an operation to complete. */ -static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit) +static int qlge_wait_cfg(struct qlge_adapter *qdev, u32 bit) { int count; u32 temp; for (count = 0; count < UDELAY_COUNT; count++) { - temp = ql_read32(qdev, CFG); + temp = qlge_read32(qdev, CFG); if (temp & CFG_LE) return -EIO; if (!(temp & bit)) @@ -205,8 +206,8 @@ static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit) /* Used to issue init control blocks to hw. Maps control block, * sets address, triggers download, waits for completion. */ -int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit, - u16 q_id) +int qlge_write_cfg(struct qlge_adapter *qdev, void *ptr, int size, u32 bit, + u16 q_id) { u64 map; int status = 0; @@ -225,38 +226,38 @@ int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit, return -ENOMEM; } - status = ql_sem_spinlock(qdev, SEM_ICB_MASK); + status = qlge_sem_spinlock(qdev, SEM_ICB_MASK); if (status) goto lock_failed; - status = ql_wait_cfg(qdev, bit); + status = qlge_wait_cfg(qdev, bit); if (status) { netif_err(qdev, ifup, qdev->ndev, "Timed out waiting for CFG to come ready.\n"); goto exit; } - ql_write32(qdev, ICB_L, (u32)map); - ql_write32(qdev, ICB_H, (u32)(map >> 32)); + qlge_write32(qdev, ICB_L, (u32)map); + qlge_write32(qdev, ICB_H, (u32)(map >> 32)); mask = CFG_Q_MASK | (bit << 16); value = bit | (q_id << CFG_Q_SHIFT); - ql_write32(qdev, CFG, (mask | value)); + qlge_write32(qdev, CFG, (mask | value)); /* * Wait for the bit to clear after signaling hw. */ - status = ql_wait_cfg(qdev, bit); + status = qlge_wait_cfg(qdev, bit); exit: - ql_sem_unlock(qdev, SEM_ICB_MASK); /* does flush too */ + qlge_sem_unlock(qdev, SEM_ICB_MASK); /* does flush too */ lock_failed: dma_unmap_single(&qdev->pdev->dev, map, size, direction); return status; } /* Get a specific MAC address from the CAM. Used for debug and reg dump. */ -int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index, - u32 *value) +int qlge_get_mac_addr_reg(struct qlge_adapter *qdev, u32 type, u16 index, + u32 *value) { u32 offset = 0; int status; @@ -264,46 +265,46 @@ int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index, switch (type) { case MAC_ADDR_TYPE_MULTI_MAC: case MAC_ADDR_TYPE_CAM_MAC: { - status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); + status = qlge_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); if (status) break; - ql_write32(qdev, MAC_ADDR_IDX, - (offset++) | /* offset */ + qlge_write32(qdev, MAC_ADDR_IDX, + (offset++) | /* offset */ (index << MAC_ADDR_IDX_SHIFT) | /* index */ MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */ - status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MR, 0); + status = qlge_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MR, 0); if (status) break; - *value++ = ql_read32(qdev, MAC_ADDR_DATA); - status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); + *value++ = qlge_read32(qdev, MAC_ADDR_DATA); + status = qlge_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); if (status) break; - ql_write32(qdev, MAC_ADDR_IDX, - (offset++) | /* offset */ + qlge_write32(qdev, MAC_ADDR_IDX, + (offset++) | /* offset */ (index << MAC_ADDR_IDX_SHIFT) | /* index */ MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */ - status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MR, 0); + status = qlge_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MR, 0); if (status) break; - *value++ = ql_read32(qdev, MAC_ADDR_DATA); + *value++ = qlge_read32(qdev, MAC_ADDR_DATA); if (type == MAC_ADDR_TYPE_CAM_MAC) { - status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, - MAC_ADDR_MW, 0); + status = qlge_wait_reg_rdy(qdev, MAC_ADDR_IDX, + MAC_ADDR_MW, 0); if (status) break; - ql_write32(qdev, MAC_ADDR_IDX, - (offset++) | /* offset */ + qlge_write32(qdev, MAC_ADDR_IDX, + (offset++) | /* offset */ (index << MAC_ADDR_IDX_SHIFT) | /* index */ MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */ - status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, - MAC_ADDR_MR, 0); + status = qlge_wait_reg_rdy(qdev, MAC_ADDR_IDX, + MAC_ADDR_MR, 0); if (status) break; - *value++ = ql_read32(qdev, MAC_ADDR_DATA); + *value++ = qlge_read32(qdev, MAC_ADDR_DATA); } break; } @@ -320,8 +321,8 @@ int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index, /* Set up a MAC, multicast or VLAN address for the * inbound frame matching. */ -static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type, - u16 index) +static int qlge_set_mac_addr_reg(struct qlge_adapter *qdev, u8 *addr, u32 type, + u16 index) { u32 offset = 0; int status = 0; @@ -332,22 +333,22 @@ static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type, u32 lower = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | (addr[5]); - status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); + status = qlge_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); if (status) break; - ql_write32(qdev, MAC_ADDR_IDX, - (offset++) | (index << MAC_ADDR_IDX_SHIFT) | type | + qlge_write32(qdev, MAC_ADDR_IDX, + (offset++) | (index << MAC_ADDR_IDX_SHIFT) | type | MAC_ADDR_E); - ql_write32(qdev, MAC_ADDR_DATA, lower); - status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); + qlge_write32(qdev, MAC_ADDR_DATA, lower); + status = qlge_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); if (status) break; - ql_write32(qdev, MAC_ADDR_IDX, - (offset++) | (index << MAC_ADDR_IDX_SHIFT) | type | + qlge_write32(qdev, MAC_ADDR_IDX, + (offset++) | (index << MAC_ADDR_IDX_SHIFT) | type | MAC_ADDR_E); - ql_write32(qdev, MAC_ADDR_DATA, upper); - status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); + qlge_write32(qdev, MAC_ADDR_DATA, upper); + status = qlge_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); break; } case MAC_ADDR_TYPE_CAM_MAC: { @@ -355,27 +356,27 @@ static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type, u32 upper = (addr[0] << 8) | addr[1]; u32 lower = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | (addr[5]); - status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); + status = qlge_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); if (status) break; - ql_write32(qdev, MAC_ADDR_IDX, - (offset++) | /* offset */ + qlge_write32(qdev, MAC_ADDR_IDX, + (offset++) | /* offset */ (index << MAC_ADDR_IDX_SHIFT) | /* index */ type); /* type */ - ql_write32(qdev, MAC_ADDR_DATA, lower); - status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); + qlge_write32(qdev, MAC_ADDR_DATA, lower); + status = qlge_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); if (status) break; - ql_write32(qdev, MAC_ADDR_IDX, - (offset++) | /* offset */ + qlge_write32(qdev, MAC_ADDR_IDX, + (offset++) | /* offset */ (index << MAC_ADDR_IDX_SHIFT) | /* index */ type); /* type */ - ql_write32(qdev, MAC_ADDR_DATA, upper); - status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); + qlge_write32(qdev, MAC_ADDR_DATA, upper); + status = qlge_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); if (status) break; - ql_write32(qdev, MAC_ADDR_IDX, - (offset) | /* offset */ + qlge_write32(qdev, MAC_ADDR_IDX, + (offset) | /* offset */ (index << MAC_ADDR_IDX_SHIFT) | /* index */ type); /* type */ /* This field should also include the queue id @@ -388,7 +389,7 @@ static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type, if (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) cam_output |= CAM_OUT_RV; /* route to NIC core */ - ql_write32(qdev, MAC_ADDR_DATA, cam_output); + qlge_write32(qdev, MAC_ADDR_DATA, cam_output); break; } case MAC_ADDR_TYPE_VLAN: { @@ -398,11 +399,11 @@ static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type, * addressing. It's either MAC_ADDR_E on or off. * That's bit-27 we're talking about. */ - status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); + status = qlge_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); if (status) break; - ql_write32(qdev, MAC_ADDR_IDX, - offset | /* offset */ + qlge_write32(qdev, MAC_ADDR_IDX, + offset | /* offset */ (index << MAC_ADDR_IDX_SHIFT) | /* index */ type | /* type */ enable_bit); /* enable/disable */ @@ -421,7 +422,7 @@ static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type, * have to clear it to prevent wrong frame routing * especially in a bonding environment. */ -static int ql_set_mac_addr(struct ql_adapter *qdev, int set) +static int qlge_set_mac_addr(struct qlge_adapter *qdev, int set) { int status; char zero_mac_addr[ETH_ALEN]; @@ -437,50 +438,50 @@ static int ql_set_mac_addr(struct ql_adapter *qdev, int set) netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev, "Clearing MAC address\n"); } - status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); + status = qlge_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); if (status) return status; - status = ql_set_mac_addr_reg(qdev, (u8 *)addr, - MAC_ADDR_TYPE_CAM_MAC, - qdev->func * MAX_CQ); - ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK); + status = qlge_set_mac_addr_reg(qdev, (u8 *)addr, + MAC_ADDR_TYPE_CAM_MAC, + qdev->func * MAX_CQ); + qlge_sem_unlock(qdev, SEM_MAC_ADDR_MASK); if (status) netif_err(qdev, ifup, qdev->ndev, "Failed to init mac address.\n"); return status; } -void ql_link_on(struct ql_adapter *qdev) +void qlge_link_on(struct qlge_adapter *qdev) { netif_err(qdev, link, qdev->ndev, "Link is up.\n"); netif_carrier_on(qdev->ndev); - ql_set_mac_addr(qdev, 1); + qlge_set_mac_addr(qdev, 1); } -void ql_link_off(struct ql_adapter *qdev) +void qlge_link_off(struct qlge_adapter *qdev) { netif_err(qdev, link, qdev->ndev, "Link is down.\n"); netif_carrier_off(qdev->ndev); - ql_set_mac_addr(qdev, 0); + qlge_set_mac_addr(qdev, 0); } /* Get a specific frame routing value from the CAM. * Used for debug and reg dump. */ -int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value) +int qlge_get_routing_reg(struct qlge_adapter *qdev, u32 index, u32 *value) { int status = 0; - status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0); + status = qlge_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0); if (status) goto exit; - ql_write32(qdev, RT_IDX, - RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT)); - status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0); + qlge_write32(qdev, RT_IDX, + RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT)); + status = qlge_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0); if (status) goto exit; - *value = ql_read32(qdev, RT_DATA); + *value = qlge_read32(qdev, RT_DATA); exit: return status; } @@ -490,8 +491,8 @@ exit: * multicast/error frames to the default queue for slow handling, * and CAM hit/RSS frames to the fast handling queues. */ -static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask, - int enable) +static int qlge_set_routing_reg(struct qlge_adapter *qdev, u32 index, u32 mask, + int enable) { int status = -EINVAL; /* Return error if no mask match. */ u32 value = 0; @@ -577,50 +578,50 @@ static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask, } if (value) { - status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0); + status = qlge_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0); if (status) goto exit; value |= (enable ? RT_IDX_E : 0); - ql_write32(qdev, RT_IDX, value); - ql_write32(qdev, RT_DATA, enable ? mask : 0); + qlge_write32(qdev, RT_IDX, value); + qlge_write32(qdev, RT_DATA, enable ? mask : 0); } exit: return status; } -static void ql_enable_interrupts(struct ql_adapter *qdev) +static void qlge_enable_interrupts(struct qlge_adapter *qdev) { - ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI); + qlge_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI); } -static void ql_disable_interrupts(struct ql_adapter *qdev) +static void qlge_disable_interrupts(struct qlge_adapter *qdev) { - ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16)); + qlge_write32(qdev, INTR_EN, (INTR_EN_EI << 16)); } -static void ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr) +static void qlge_enable_completion_interrupt(struct qlge_adapter *qdev, u32 intr) { struct intr_context *ctx = &qdev->intr_context[intr]; - ql_write32(qdev, INTR_EN, ctx->intr_en_mask); + qlge_write32(qdev, INTR_EN, ctx->intr_en_mask); } -static void ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr) +static void qlge_disable_completion_interrupt(struct qlge_adapter *qdev, u32 intr) { struct intr_context *ctx = &qdev->intr_context[intr]; - ql_write32(qdev, INTR_EN, ctx->intr_dis_mask); + qlge_write32(qdev, INTR_EN, ctx->intr_dis_mask); } -static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev) +static void qlge_enable_all_completion_interrupts(struct qlge_adapter *qdev) { int i; for (i = 0; i < qdev->intr_count; i++) - ql_enable_completion_interrupt(qdev, i); + qlge_enable_completion_interrupt(qdev, i); } -static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str) +static int qlge_validate_flash(struct qlge_adapter *qdev, u32 size, const char *str) { int status, i; u16 csum = 0; @@ -642,31 +643,31 @@ static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str) return csum; } -static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data) +static int qlge_read_flash_word(struct qlge_adapter *qdev, int offset, __le32 *data) { int status = 0; /* wait for reg to come ready */ - status = ql_wait_reg_rdy(qdev, - FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR); + status = qlge_wait_reg_rdy(qdev, + FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR); if (status) goto exit; /* set up for reg read */ - ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset); + qlge_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset); /* wait for reg to come ready */ - status = ql_wait_reg_rdy(qdev, - FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR); + status = qlge_wait_reg_rdy(qdev, + FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR); if (status) goto exit; /* This data is stored on flash as an array of - * __le32. Since ql_read32() returns cpu endian + * __le32. Since qlge_read32() returns cpu endian * we need to swap it back. */ - *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA)); + *data = cpu_to_le32(qlge_read32(qdev, FLASH_DATA)); exit: return status; } -static int ql_get_8000_flash_params(struct ql_adapter *qdev) +static int qlge_get_8000_flash_params(struct qlge_adapter *qdev) { u32 i, size; int status; @@ -682,12 +683,12 @@ static int ql_get_8000_flash_params(struct ql_adapter *qdev) else offset = FUNC1_FLASH_OFFSET / sizeof(u32); - if (ql_sem_spinlock(qdev, SEM_FLASH_MASK)) + if (qlge_sem_spinlock(qdev, SEM_FLASH_MASK)) return -ETIMEDOUT; size = sizeof(struct flash_params_8000) / sizeof(u32); for (i = 0; i < size; i++, p++) { - status = ql_read_flash_word(qdev, i + offset, p); + status = qlge_read_flash_word(qdev, i + offset, p); if (status) { netif_err(qdev, ifup, qdev->ndev, "Error reading flash.\n"); @@ -695,8 +696,8 @@ static int ql_get_8000_flash_params(struct ql_adapter *qdev) } } - status = ql_validate_flash(qdev, - sizeof(struct flash_params_8000) / + status = qlge_validate_flash(qdev, + sizeof(struct flash_params_8000) / sizeof(u16), "8000"); if (status) { @@ -728,11 +729,11 @@ static int ql_get_8000_flash_params(struct ql_adapter *qdev) qdev->ndev->addr_len); exit: - ql_sem_unlock(qdev, SEM_FLASH_MASK); + qlge_sem_unlock(qdev, SEM_FLASH_MASK); return status; } -static int ql_get_8012_flash_params(struct ql_adapter *qdev) +static int qlge_get_8012_flash_params(struct qlge_adapter *qdev) { int i; int status; @@ -746,11 +747,11 @@ static int ql_get_8012_flash_params(struct ql_adapter *qdev) if (qdev->port) offset = size; - if (ql_sem_spinlock(qdev, SEM_FLASH_MASK)) + if (qlge_sem_spinlock(qdev, SEM_FLASH_MASK)) return -ETIMEDOUT; for (i = 0; i < size; i++, p++) { - status = ql_read_flash_word(qdev, i + offset, p); + status = qlge_read_flash_word(qdev, i + offset, p); if (status) { netif_err(qdev, ifup, qdev->ndev, "Error reading flash.\n"); @@ -758,10 +759,10 @@ static int ql_get_8012_flash_params(struct ql_adapter *qdev) } } - status = ql_validate_flash(qdev, - sizeof(struct flash_params_8012) / - sizeof(u16), - "8012"); + status = qlge_validate_flash(qdev, + sizeof(struct flash_params_8012) / + sizeof(u16), + "8012"); if (status) { netif_err(qdev, ifup, qdev->ndev, "Invalid flash.\n"); status = -EINVAL; @@ -778,7 +779,7 @@ static int ql_get_8012_flash_params(struct ql_adapter *qdev) qdev->ndev->addr_len); exit: - ql_sem_unlock(qdev, SEM_FLASH_MASK); + qlge_sem_unlock(qdev, SEM_FLASH_MASK); return status; } @@ -786,18 +787,18 @@ exit: * register pair. Each read/write requires us to wait for the ready * bit before reading/writing the data. */ -static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data) +static int qlge_write_xgmac_reg(struct qlge_adapter *qdev, u32 reg, u32 data) { int status; /* wait for reg to come ready */ - status = ql_wait_reg_rdy(qdev, - XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME); + status = qlge_wait_reg_rdy(qdev, + XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME); if (status) return status; /* write the data to the data reg */ - ql_write32(qdev, XGMAC_DATA, data); + qlge_write32(qdev, XGMAC_DATA, data); /* trigger the write */ - ql_write32(qdev, XGMAC_ADDR, reg); + qlge_write32(qdev, XGMAC_ADDR, reg); return status; } @@ -805,39 +806,39 @@ static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data) * register pair. Each read/write requires us to wait for the ready * bit before reading/writing the data. */ -int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data) +int qlge_read_xgmac_reg(struct qlge_adapter *qdev, u32 reg, u32 *data) { int status = 0; /* wait for reg to come ready */ - status = ql_wait_reg_rdy(qdev, - XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME); + status = qlge_wait_reg_rdy(qdev, + XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME); if (status) goto exit; /* set up for reg read */ - ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R); + qlge_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R); /* wait for reg to come ready */ - status = ql_wait_reg_rdy(qdev, - XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME); + status = qlge_wait_reg_rdy(qdev, + XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME); if (status) goto exit; /* get the data */ - *data = ql_read32(qdev, XGMAC_DATA); + *data = qlge_read32(qdev, XGMAC_DATA); exit: return status; } /* This is used for reading the 64-bit statistics regs. */ -int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data) +int qlge_read_xgmac_reg64(struct qlge_adapter *qdev, u32 reg, u64 *data) { int status = 0; u32 hi = 0; u32 lo = 0; - status = ql_read_xgmac_reg(qdev, reg, &lo); + status = qlge_read_xgmac_reg(qdev, reg, &lo); if (status) goto exit; - status = ql_read_xgmac_reg(qdev, reg + 4, &hi); + status = qlge_read_xgmac_reg(qdev, reg + 4, &hi); if (status) goto exit; @@ -847,17 +848,17 @@ exit: return status; } -static int ql_8000_port_initialize(struct ql_adapter *qdev) +static int qlge_8000_port_initialize(struct qlge_adapter *qdev) { int status; /* * Get MPI firmware version for driver banner * and ethool info. */ - status = ql_mb_about_fw(qdev); + status = qlge_mb_about_fw(qdev); if (status) goto exit; - status = ql_mb_get_fw_state(qdev); + status = qlge_mb_get_fw_state(qdev); if (status) goto exit; /* Wake up a worker to get/set the TX/RX frame sizes. */ @@ -872,18 +873,18 @@ exit: * This functionality may be done in the MPI firmware at a * later date. */ -static int ql_8012_port_initialize(struct ql_adapter *qdev) +static int qlge_8012_port_initialize(struct qlge_adapter *qdev) { int status = 0; u32 data; - if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) { + if (qlge_sem_trylock(qdev, qdev->xg_sem_mask)) { /* Another function has the semaphore, so * wait for the port init bit to come ready. */ netif_info(qdev, link, qdev->ndev, "Another function has the semaphore, so wait for the port init bit to come ready.\n"); - status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0); + status = qlge_wait_reg_rdy(qdev, STS, qdev->port_init, 0); if (status) { netif_crit(qdev, link, qdev->ndev, "Port initialize timed out.\n"); @@ -893,11 +894,11 @@ static int ql_8012_port_initialize(struct ql_adapter *qdev) netif_info(qdev, link, qdev->ndev, "Got xgmac semaphore!.\n"); /* Set the core reset. */ - status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data); + status = qlge_read_xgmac_reg(qdev, GLOBAL_CFG, &data); if (status) goto end; data |= GLOBAL_CFG_RESET; - status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data); + status = qlge_write_xgmac_reg(qdev, GLOBAL_CFG, data); if (status) goto end; @@ -906,48 +907,48 @@ static int ql_8012_port_initialize(struct ql_adapter *qdev) data |= GLOBAL_CFG_JUMBO; /* Turn on jumbo. */ data |= GLOBAL_CFG_TX_STAT_EN; data |= GLOBAL_CFG_RX_STAT_EN; - status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data); + status = qlge_write_xgmac_reg(qdev, GLOBAL_CFG, data); if (status) goto end; /* Enable transmitter, and clear it's reset. */ - status = ql_read_xgmac_reg(qdev, TX_CFG, &data); + status = qlge_read_xgmac_reg(qdev, TX_CFG, &data); if (status) goto end; data &= ~TX_CFG_RESET; /* Clear the TX MAC reset. */ data |= TX_CFG_EN; /* Enable the transmitter. */ - status = ql_write_xgmac_reg(qdev, TX_CFG, data); + status = qlge_write_xgmac_reg(qdev, TX_CFG, data); if (status) goto end; /* Enable receiver and clear it's reset. */ - status = ql_read_xgmac_reg(qdev, RX_CFG, &data); + status = qlge_read_xgmac_reg(qdev, RX_CFG, &data); if (status) goto end; data &= ~RX_CFG_RESET; /* Clear the RX MAC reset. */ data |= RX_CFG_EN; /* Enable the receiver. */ - status = ql_write_xgmac_reg(qdev, RX_CFG, data); + status = qlge_write_xgmac_reg(qdev, RX_CFG, data); if (status) goto end; /* Turn on jumbo. */ status = - ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16)); + qlge_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16)); if (status) goto end; status = - ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580); + qlge_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580); if (status) goto end; /* Signal to the world that the port is enabled. */ - ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init)); + qlge_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init)); end: - ql_sem_unlock(qdev, qdev->xg_sem_mask); + qlge_sem_unlock(qdev, qdev->xg_sem_mask); return status; } -static inline unsigned int ql_lbq_block_size(struct ql_adapter *qdev) +static inline unsigned int qlge_lbq_block_size(struct qlge_adapter *qdev) { return PAGE_SIZE << qdev->lbq_buf_order; } @@ -962,8 +963,8 @@ static struct qlge_bq_desc *qlge_get_curr_buf(struct qlge_bq *bq) return bq_desc; } -static struct qlge_bq_desc *ql_get_curr_lchunk(struct ql_adapter *qdev, - struct rx_ring *rx_ring) +static struct qlge_bq_desc *qlge_get_curr_lchunk(struct qlge_adapter *qdev, + struct rx_ring *rx_ring) { struct qlge_bq_desc *lbq_desc = qlge_get_curr_buf(&rx_ring->lbq); @@ -971,17 +972,17 @@ static struct qlge_bq_desc *ql_get_curr_lchunk(struct ql_adapter *qdev, qdev->lbq_buf_size, DMA_FROM_DEVICE); if ((lbq_desc->p.pg_chunk.offset + qdev->lbq_buf_size) == - ql_lbq_block_size(qdev)) { + qlge_lbq_block_size(qdev)) { /* last chunk of the master page */ dma_unmap_page(&qdev->pdev->dev, lbq_desc->dma_addr, - ql_lbq_block_size(qdev), DMA_FROM_DEVICE); + qlge_lbq_block_size(qdev), DMA_FROM_DEVICE); } return lbq_desc; } /* Update an rx ring index. */ -static void ql_update_cq(struct rx_ring *rx_ring) +static void qlge_update_cq(struct rx_ring *rx_ring) { rx_ring->cnsmr_idx++; rx_ring->curr_entry++; @@ -991,9 +992,9 @@ static void ql_update_cq(struct rx_ring *rx_ring) } } -static void ql_write_cq_idx(struct rx_ring *rx_ring) +static void qlge_write_cq_idx(struct rx_ring *rx_ring) { - ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg); + qlge_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg); } static const char * const bq_type_name[] = { @@ -1005,7 +1006,7 @@ static const char * const bq_type_name[] = { static int qlge_refill_sb(struct rx_ring *rx_ring, struct qlge_bq_desc *sbq_desc, gfp_t gfp) { - struct ql_adapter *qdev = rx_ring->qdev; + struct qlge_adapter *qdev = rx_ring->qdev; struct sk_buff *skb; if (sbq_desc->p.skb) @@ -1038,7 +1039,7 @@ static int qlge_refill_sb(struct rx_ring *rx_ring, static int qlge_refill_lb(struct rx_ring *rx_ring, struct qlge_bq_desc *lbq_desc, gfp_t gfp) { - struct ql_adapter *qdev = rx_ring->qdev; + struct qlge_adapter *qdev = rx_ring->qdev; struct qlge_page_chunk *master_chunk = &rx_ring->master_chunk; if (!master_chunk->page) { @@ -1049,7 +1050,7 @@ static int qlge_refill_lb(struct rx_ring *rx_ring, if (unlikely(!page)) return -ENOMEM; dma_addr = dma_map_page(&qdev->pdev->dev, page, 0, - ql_lbq_block_size(qdev), + qlge_lbq_block_size(qdev), DMA_FROM_DEVICE); if (dma_mapping_error(&qdev->pdev->dev, dma_addr)) { __free_pages(page, qdev->lbq_buf_order); @@ -1072,7 +1073,7 @@ static int qlge_refill_lb(struct rx_ring *rx_ring, * buffer get. */ master_chunk->offset += qdev->lbq_buf_size; - if (master_chunk->offset == ql_lbq_block_size(qdev)) { + if (master_chunk->offset == qlge_lbq_block_size(qdev)) { master_chunk->page = NULL; } else { master_chunk->va += qdev->lbq_buf_size; @@ -1086,7 +1087,7 @@ static int qlge_refill_lb(struct rx_ring *rx_ring, static int qlge_refill_bq(struct qlge_bq *bq, gfp_t gfp) { struct rx_ring *rx_ring = QLGE_BQ_CONTAINER(bq); - struct ql_adapter *qdev = rx_ring->qdev; + struct qlge_adapter *qdev = rx_ring->qdev; struct qlge_bq_desc *bq_desc; int refill_count; int retval; @@ -1132,7 +1133,7 @@ static int qlge_refill_bq(struct qlge_bq *bq, gfp_t gfp) "ring %u %s: updating prod idx = %d.\n", rx_ring->cq_id, bq_type_name[bq->type], i); - ql_write_db_reg(i, bq->prod_idx_db_reg); + qlge_write_db_reg(i, bq->prod_idx_db_reg); } bq->next_to_use = i; } @@ -1140,8 +1141,8 @@ static int qlge_refill_bq(struct qlge_bq *bq, gfp_t gfp) return retval; } -static void ql_update_buffer_queues(struct rx_ring *rx_ring, gfp_t gfp, - unsigned long delay) +static void qlge_update_buffer_queues(struct rx_ring *rx_ring, gfp_t gfp, + unsigned long delay) { bool sbq_fail, lbq_fail; @@ -1172,7 +1173,7 @@ static void qlge_slow_refill(struct work_struct *work) struct napi_struct *napi = &rx_ring->napi; napi_disable(napi); - ql_update_buffer_queues(rx_ring, GFP_KERNEL, HZ / 2); + qlge_update_buffer_queues(rx_ring, GFP_KERNEL, HZ / 2); napi_enable(napi); local_bh_disable(); @@ -1187,8 +1188,8 @@ static void qlge_slow_refill(struct work_struct *work) /* Unmaps tx buffers. Can be called from send() if a pci mapping * fails at some stage, or from the interrupt when a tx completes. */ -static void ql_unmap_send(struct ql_adapter *qdev, - struct tx_ring_desc *tx_ring_desc, int mapped) +static void qlge_unmap_send(struct qlge_adapter *qdev, + struct tx_ring_desc *tx_ring_desc, int mapped) { int i; @@ -1229,9 +1230,9 @@ static void ql_unmap_send(struct ql_adapter *qdev, /* Map the buffers for this transmit. This will return * NETDEV_TX_BUSY or NETDEV_TX_OK based on success. */ -static int ql_map_send(struct ql_adapter *qdev, - struct ob_mac_iocb_req *mac_iocb_ptr, - struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc) +static int qlge_map_send(struct qlge_adapter *qdev, + struct qlge_ob_mac_iocb_req *mac_iocb_ptr, + struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc) { int len = skb_headlen(skb); dma_addr_t map; @@ -1294,7 +1295,7 @@ static int ql_map_send(struct ql_adapter *qdev, */ /* Tack on the OAL in the eighth segment of IOCB. */ map = dma_map_single(&qdev->pdev->dev, &tx_ring_desc->oal, - sizeof(struct oal), + sizeof(struct qlge_oal), DMA_TO_DEVICE); err = dma_mapping_error(&qdev->pdev->dev, map); if (err) { @@ -1316,7 +1317,7 @@ static int ql_map_send(struct ql_adapter *qdev, dma_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map); dma_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, - sizeof(struct oal)); + sizeof(struct qlge_oal)); tbd = (struct tx_buf_desc *)&tx_ring_desc->oal; map_idx++; } @@ -1351,13 +1352,13 @@ map_error: * we pass in the number of frags that mapped successfully * so they can be umapped. */ - ql_unmap_send(qdev, tx_ring_desc, map_idx); + qlge_unmap_send(qdev, tx_ring_desc, map_idx); return NETDEV_TX_BUSY; } /* Categorizing receive firmware frame errors */ -static void ql_categorize_rx_err(struct ql_adapter *qdev, u8 rx_err, - struct rx_ring *rx_ring) +static void qlge_categorize_rx_err(struct qlge_adapter *qdev, u8 rx_err, + struct rx_ring *rx_ring) { struct nic_stats *stats = &qdev->nic_stats; @@ -1389,12 +1390,12 @@ static void ql_categorize_rx_err(struct ql_adapter *qdev, u8 rx_err, } /** - * ql_update_mac_hdr_len - helper routine to update the mac header length + * qlge_update_mac_hdr_len - helper routine to update the mac header length * based on vlan tags if present */ -static void ql_update_mac_hdr_len(struct ql_adapter *qdev, - struct ib_mac_iocb_rsp *ib_mac_rsp, - void *page, size_t *len) +static void qlge_update_mac_hdr_len(struct qlge_adapter *qdev, + struct qlge_ib_mac_iocb_rsp *ib_mac_rsp, + void *page, size_t *len) { u16 *tags; @@ -1412,18 +1413,18 @@ static void ql_update_mac_hdr_len(struct ql_adapter *qdev, } /* Process an inbound completion from an rx ring. */ -static void ql_process_mac_rx_gro_page(struct ql_adapter *qdev, - struct rx_ring *rx_ring, - struct ib_mac_iocb_rsp *ib_mac_rsp, - u32 length, u16 vlan_id) +static void qlge_process_mac_rx_gro_page(struct qlge_adapter *qdev, + struct rx_ring *rx_ring, + struct qlge_ib_mac_iocb_rsp *ib_mac_rsp, + u32 length, u16 vlan_id) { struct sk_buff *skb; - struct qlge_bq_desc *lbq_desc = ql_get_curr_lchunk(qdev, rx_ring); + struct qlge_bq_desc *lbq_desc = qlge_get_curr_lchunk(qdev, rx_ring); struct napi_struct *napi = &rx_ring->napi; /* Frame error, so drop the packet. */ if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) { - ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring); + qlge_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring); put_page(lbq_desc->p.pg_chunk.page); return; } @@ -1458,15 +1459,15 @@ static void ql_process_mac_rx_gro_page(struct ql_adapter *qdev, } /* Process an inbound completion from an rx ring. */ -static void ql_process_mac_rx_page(struct ql_adapter *qdev, - struct rx_ring *rx_ring, - struct ib_mac_iocb_rsp *ib_mac_rsp, - u32 length, u16 vlan_id) +static void qlge_process_mac_rx_page(struct qlge_adapter *qdev, + struct rx_ring *rx_ring, + struct qlge_ib_mac_iocb_rsp *ib_mac_rsp, + u32 length, u16 vlan_id) { struct net_device *ndev = qdev->ndev; struct sk_buff *skb = NULL; void *addr; - struct qlge_bq_desc *lbq_desc = ql_get_curr_lchunk(qdev, rx_ring); + struct qlge_bq_desc *lbq_desc = qlge_get_curr_lchunk(qdev, rx_ring); struct napi_struct *napi = &rx_ring->napi; size_t hlen = ETH_HLEN; @@ -1482,12 +1483,12 @@ static void ql_process_mac_rx_page(struct ql_adapter *qdev, /* Frame error, so drop the packet. */ if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) { - ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring); + qlge_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring); goto err_out; } /* Update the MAC header length*/ - ql_update_mac_hdr_len(qdev, ib_mac_rsp, addr, &hlen); + qlge_update_mac_hdr_len(qdev, ib_mac_rsp, addr, &hlen); /* The max framesize filter on this chip is set higher than * MTU since FCoE uses 2k frames. @@ -1521,12 +1522,12 @@ static void ql_process_mac_rx_page(struct ql_adapter *qdev, "TCP checksum done!\n"); skb->ip_summed = CHECKSUM_UNNECESSARY; } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) && - (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) { + (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) { /* Unfragmented ipv4 UDP frame. */ struct iphdr *iph = (struct iphdr *)((u8 *)addr + hlen); if (!(iph->frag_off & - htons(IP_MF | IP_OFFSET))) { + htons(IP_MF | IP_OFFSET))) { skb->ip_summed = CHECKSUM_UNNECESSARY; netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, @@ -1549,10 +1550,10 @@ err_out: } /* Process an inbound completion from an rx ring. */ -static void ql_process_mac_rx_skb(struct ql_adapter *qdev, - struct rx_ring *rx_ring, - struct ib_mac_iocb_rsp *ib_mac_rsp, - u32 length, u16 vlan_id) +static void qlge_process_mac_rx_skb(struct qlge_adapter *qdev, + struct rx_ring *rx_ring, + struct qlge_ib_mac_iocb_rsp *ib_mac_rsp, + u32 length, u16 vlan_id) { struct qlge_bq_desc *sbq_desc = qlge_get_curr_buf(&rx_ring->sbq); struct net_device *ndev = qdev->ndev; @@ -1576,14 +1577,14 @@ static void ql_process_mac_rx_skb(struct ql_adapter *qdev, /* Frame error, so drop the packet. */ if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) { - ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring); + qlge_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring); dev_kfree_skb_any(skb); return; } /* loopback self test for ethtool */ if (test_bit(QL_SELFTEST, &qdev->flags)) { - ql_check_lb_frame(qdev, skb); + qlge_check_lb_frame(qdev, skb); dev_kfree_skb_any(skb); return; } @@ -1628,12 +1629,12 @@ static void ql_process_mac_rx_skb(struct ql_adapter *qdev, "TCP checksum done!\n"); skb->ip_summed = CHECKSUM_UNNECESSARY; } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) && - (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) { + (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) { /* Unfragmented ipv4 UDP frame. */ struct iphdr *iph = (struct iphdr *)skb->data; if (!(iph->frag_off & - htons(IP_MF | IP_OFFSET))) { + htons(IP_MF | IP_OFFSET))) { skb->ip_summed = CHECKSUM_UNNECESSARY; netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, @@ -1651,7 +1652,7 @@ static void ql_process_mac_rx_skb(struct ql_adapter *qdev, netif_receive_skb(skb); } -static void ql_realign_skb(struct sk_buff *skb, int len) +static void qlge_realign_skb(struct sk_buff *skb, int len) { void *temp_addr = skb->data; @@ -1669,9 +1670,9 @@ static void ql_realign_skb(struct sk_buff *skb, int len) * completion. It will be rewritten for readability in the near * future, but for not it works well. */ -static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev, - struct rx_ring *rx_ring, - struct ib_mac_iocb_rsp *ib_mac_rsp) +static struct sk_buff *qlge_build_rx_skb(struct qlge_adapter *qdev, + struct rx_ring *rx_ring, + struct qlge_ib_mac_iocb_rsp *ib_mac_rsp) { u32 length = le32_to_cpu(ib_mac_rsp->data_len); u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len); @@ -1693,7 +1694,7 @@ static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev, dma_unmap_single(&qdev->pdev->dev, sbq_desc->dma_addr, SMALL_BUF_MAP_SIZE, DMA_FROM_DEVICE); skb = sbq_desc->p.skb; - ql_realign_skb(skb, hdr_len); + qlge_realign_skb(skb, hdr_len); skb_put(skb, hdr_len); sbq_desc->p.skb = NULL; } @@ -1731,7 +1732,7 @@ static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev, length); sbq_desc = qlge_get_curr_buf(&rx_ring->sbq); skb = sbq_desc->p.skb; - ql_realign_skb(skb, length); + qlge_realign_skb(skb, length); skb_put(skb, length); dma_unmap_single(&qdev->pdev->dev, sbq_desc->dma_addr, SMALL_BUF_MAP_SIZE, @@ -1748,7 +1749,7 @@ static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev, * chain it to the header buffer's skb and let * it rip. */ - lbq_desc = ql_get_curr_lchunk(qdev, rx_ring); + lbq_desc = qlge_get_curr_lchunk(qdev, rx_ring); netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, "Chaining page at offset = %d, for %d bytes to skb.\n", lbq_desc->p.pg_chunk.offset, length); @@ -1763,7 +1764,7 @@ static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev, * copy it to a new skb and let it go. This can happen with * jumbo mtu on a non-TCP/UDP frame. */ - lbq_desc = ql_get_curr_lchunk(qdev, rx_ring); + lbq_desc = qlge_get_curr_lchunk(qdev, rx_ring); skb = netdev_alloc_skb(qdev->ndev, length); if (!skb) { netif_printk(qdev, probe, KERN_DEBUG, qdev->ndev, @@ -1783,9 +1784,9 @@ static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev, skb->len += length; skb->data_len += length; skb->truesize += length; - ql_update_mac_hdr_len(qdev, ib_mac_rsp, - lbq_desc->p.pg_chunk.va, - &hlen); + qlge_update_mac_hdr_len(qdev, ib_mac_rsp, + lbq_desc->p.pg_chunk.va, + &hlen); __pskb_pull_tail(skb, hlen); } } else { @@ -1823,7 +1824,7 @@ static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev, skb_reserve(skb, NET_IP_ALIGN); } do { - lbq_desc = ql_get_curr_lchunk(qdev, rx_ring); + lbq_desc = qlge_get_curr_lchunk(qdev, rx_ring); size = min(length, qdev->lbq_buf_size); netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, @@ -1838,25 +1839,23 @@ static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev, length -= size; i++; } while (length > 0); - ql_update_mac_hdr_len(qdev, ib_mac_rsp, lbq_desc->p.pg_chunk.va, - &hlen); + qlge_update_mac_hdr_len(qdev, ib_mac_rsp, lbq_desc->p.pg_chunk.va, + &hlen); __pskb_pull_tail(skb, hlen); } return skb; } /* Process an inbound completion from an rx ring. */ -static void ql_process_mac_split_rx_intr(struct ql_adapter *qdev, - struct rx_ring *rx_ring, - struct ib_mac_iocb_rsp *ib_mac_rsp, - u16 vlan_id) +static void qlge_process_mac_split_rx_intr(struct qlge_adapter *qdev, + struct rx_ring *rx_ring, + struct qlge_ib_mac_iocb_rsp *ib_mac_rsp, + u16 vlan_id) { struct net_device *ndev = qdev->ndev; struct sk_buff *skb = NULL; - QL_DUMP_IB_MAC_RSP(qdev, ib_mac_rsp); - - skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp); + skb = qlge_build_rx_skb(qdev, rx_ring, ib_mac_rsp); if (unlikely(!skb)) { netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, "No skb available, drop packet.\n"); @@ -1866,7 +1865,7 @@ static void ql_process_mac_split_rx_intr(struct ql_adapter *qdev, /* Frame error, so drop the packet. */ if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) { - ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring); + qlge_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring); dev_kfree_skb_any(skb); return; } @@ -1882,7 +1881,7 @@ static void ql_process_mac_split_rx_intr(struct ql_adapter *qdev, /* loopback self test for ethtool */ if (test_bit(QL_SELFTEST, &qdev->flags)) { - ql_check_lb_frame(qdev, skb); + qlge_check_lb_frame(qdev, skb); dev_kfree_skb_any(skb); return; } @@ -1917,12 +1916,12 @@ static void ql_process_mac_split_rx_intr(struct ql_adapter *qdev, "TCP checksum done!\n"); skb->ip_summed = CHECKSUM_UNNECESSARY; } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) && - (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) { - /* Unfragmented ipv4 UDP frame. */ + (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) { + /* Unfragmented ipv4 UDP frame. */ struct iphdr *iph = (struct iphdr *)skb->data; if (!(iph->frag_off & - htons(IP_MF | IP_OFFSET))) { + htons(IP_MF | IP_OFFSET))) { skb->ip_summed = CHECKSUM_UNNECESSARY; netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, "TCP checksum done!\n"); @@ -1942,67 +1941,64 @@ static void ql_process_mac_split_rx_intr(struct ql_adapter *qdev, } /* Process an inbound completion from an rx ring. */ -static unsigned long ql_process_mac_rx_intr(struct ql_adapter *qdev, - struct rx_ring *rx_ring, - struct ib_mac_iocb_rsp *ib_mac_rsp) +static unsigned long qlge_process_mac_rx_intr(struct qlge_adapter *qdev, + struct rx_ring *rx_ring, + struct qlge_ib_mac_iocb_rsp *ib_mac_rsp) { u32 length = le32_to_cpu(ib_mac_rsp->data_len); u16 vlan_id = ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) && - (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)) ? - ((le16_to_cpu(ib_mac_rsp->vlan_id) & - IB_MAC_IOCB_RSP_VLAN_MASK)) : 0xffff; - - QL_DUMP_IB_MAC_RSP(qdev, ib_mac_rsp); + (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)) ? + ((le16_to_cpu(ib_mac_rsp->vlan_id) & + IB_MAC_IOCB_RSP_VLAN_MASK)) : 0xffff; if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV) { /* The data and headers are split into * separate buffers. */ - ql_process_mac_split_rx_intr(qdev, rx_ring, ib_mac_rsp, - vlan_id); + qlge_process_mac_split_rx_intr(qdev, rx_ring, ib_mac_rsp, + vlan_id); } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) { /* The data fit in a single small buffer. * Allocate a new skb, copy the data and * return the buffer to the free pool. */ - ql_process_mac_rx_skb(qdev, rx_ring, ib_mac_rsp, length, - vlan_id); + qlge_process_mac_rx_skb(qdev, rx_ring, ib_mac_rsp, length, + vlan_id); } else if ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) && - !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK) && - (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T)) { + !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK) && + (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T)) { /* TCP packet in a page chunk that's been checksummed. * Tack it on to our GRO skb and let it go. */ - ql_process_mac_rx_gro_page(qdev, rx_ring, ib_mac_rsp, length, - vlan_id); + qlge_process_mac_rx_gro_page(qdev, rx_ring, ib_mac_rsp, length, + vlan_id); } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) { /* Non-TCP packet in a page chunk. Allocate an * skb, tack it on frags, and send it up. */ - ql_process_mac_rx_page(qdev, rx_ring, ib_mac_rsp, length, - vlan_id); + qlge_process_mac_rx_page(qdev, rx_ring, ib_mac_rsp, length, + vlan_id); } else { /* Non-TCP/UDP large frames that span multiple buffers * can be processed corrrectly by the split frame logic. */ - ql_process_mac_split_rx_intr(qdev, rx_ring, ib_mac_rsp, - vlan_id); + qlge_process_mac_split_rx_intr(qdev, rx_ring, ib_mac_rsp, + vlan_id); } return (unsigned long)length; } /* Process an outbound completion from an rx ring. */ -static void ql_process_mac_tx_intr(struct ql_adapter *qdev, - struct ob_mac_iocb_rsp *mac_rsp) +static void qlge_process_mac_tx_intr(struct qlge_adapter *qdev, + struct qlge_ob_mac_iocb_rsp *mac_rsp) { struct tx_ring *tx_ring; struct tx_ring_desc *tx_ring_desc; - QL_DUMP_OB_MAC_RSP(qdev, mac_rsp); tx_ring = &qdev->tx_ring[mac_rsp->txq_idx]; tx_ring_desc = &tx_ring->q[mac_rsp->tid]; - ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt); + qlge_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt); tx_ring->tx_bytes += (tx_ring_desc->skb)->len; tx_ring->tx_packets++; dev_kfree_skb(tx_ring_desc->skb); @@ -2033,16 +2029,16 @@ static void ql_process_mac_tx_intr(struct ql_adapter *qdev, } /* Fire up a handler to reset the MPI processor. */ -void ql_queue_fw_error(struct ql_adapter *qdev) +void qlge_queue_fw_error(struct qlge_adapter *qdev) { - ql_link_off(qdev); + qlge_link_off(qdev); queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0); } -void ql_queue_asic_error(struct ql_adapter *qdev) +void qlge_queue_asic_error(struct qlge_adapter *qdev) { - ql_link_off(qdev); - ql_disable_interrupts(qdev); + qlge_link_off(qdev); + qlge_disable_interrupts(qdev); /* Clear adapter up bit to signal the recovery * process that it shouldn't kill the reset worker * thread @@ -2055,47 +2051,47 @@ void ql_queue_asic_error(struct ql_adapter *qdev) queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0); } -static void ql_process_chip_ae_intr(struct ql_adapter *qdev, - struct ib_ae_iocb_rsp *ib_ae_rsp) +static void qlge_process_chip_ae_intr(struct qlge_adapter *qdev, + struct qlge_ib_ae_iocb_rsp *ib_ae_rsp) { switch (ib_ae_rsp->event) { case MGMT_ERR_EVENT: netif_err(qdev, rx_err, qdev->ndev, "Management Processor Fatal Error.\n"); - ql_queue_fw_error(qdev); + qlge_queue_fw_error(qdev); return; case CAM_LOOKUP_ERR_EVENT: netdev_err(qdev->ndev, "Multiple CAM hits lookup occurred.\n"); netdev_err(qdev->ndev, "This event shouldn't occur.\n"); - ql_queue_asic_error(qdev); + qlge_queue_asic_error(qdev); return; case SOFT_ECC_ERROR_EVENT: netdev_err(qdev->ndev, "Soft ECC error detected.\n"); - ql_queue_asic_error(qdev); + qlge_queue_asic_error(qdev); break; case PCI_ERR_ANON_BUF_RD: netdev_err(qdev->ndev, "PCI error occurred when reading anonymous buffers from rx_ring %d.\n", ib_ae_rsp->q_id); - ql_queue_asic_error(qdev); + qlge_queue_asic_error(qdev); break; default: netif_err(qdev, drv, qdev->ndev, "Unexpected event %d.\n", ib_ae_rsp->event); - ql_queue_asic_error(qdev); + qlge_queue_asic_error(qdev); break; } } -static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring) +static int qlge_clean_outbound_rx_ring(struct rx_ring *rx_ring) { - struct ql_adapter *qdev = rx_ring->qdev; - u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg); - struct ob_mac_iocb_rsp *net_rsp = NULL; + struct qlge_adapter *qdev = rx_ring->qdev; + u32 prod = qlge_read_sh_reg(rx_ring->prod_idx_sh_reg); + struct qlge_ob_mac_iocb_rsp *net_rsp = NULL; int count = 0; struct tx_ring *tx_ring; @@ -2105,12 +2101,12 @@ static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring) "cq_id = %d, prod = %d, cnsmr = %d\n", rx_ring->cq_id, prod, rx_ring->cnsmr_idx); - net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry; + net_rsp = (struct qlge_ob_mac_iocb_rsp *)rx_ring->curr_entry; rmb(); switch (net_rsp->opcode) { case OPCODE_OB_MAC_TSO_IOCB: case OPCODE_OB_MAC_IOCB: - ql_process_mac_tx_intr(qdev, net_rsp); + qlge_process_mac_tx_intr(qdev, net_rsp); break; default: netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, @@ -2118,12 +2114,12 @@ static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring) net_rsp->opcode); } count++; - ql_update_cq(rx_ring); - prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg); + qlge_update_cq(rx_ring); + prod = qlge_read_sh_reg(rx_ring->prod_idx_sh_reg); } if (!net_rsp) return 0; - ql_write_cq_idx(rx_ring); + qlge_write_cq_idx(rx_ring); tx_ring = &qdev->tx_ring[net_rsp->txq_idx]; if (__netif_subqueue_stopped(qdev->ndev, tx_ring->wq_id)) { if ((atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4))) @@ -2137,11 +2133,11 @@ static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring) return count; } -static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget) +static int qlge_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget) { - struct ql_adapter *qdev = rx_ring->qdev; - u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg); - struct ql_net_rsp_iocb *net_rsp; + struct qlge_adapter *qdev = rx_ring->qdev; + u32 prod = qlge_read_sh_reg(rx_ring->prod_idx_sh_reg); + struct qlge_net_rsp_iocb *net_rsp; int count = 0; /* While there are entries in the completion queue. */ @@ -2154,14 +2150,14 @@ static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget) rmb(); switch (net_rsp->opcode) { case OPCODE_IB_MAC_IOCB: - ql_process_mac_rx_intr(qdev, rx_ring, - (struct ib_mac_iocb_rsp *) - net_rsp); + qlge_process_mac_rx_intr(qdev, rx_ring, + (struct qlge_ib_mac_iocb_rsp *) + net_rsp); break; case OPCODE_IB_AE_IOCB: - ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *) - net_rsp); + qlge_process_chip_ae_intr(qdev, (struct qlge_ib_ae_iocb_rsp *) + net_rsp); break; default: netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, @@ -2170,20 +2166,20 @@ static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget) break; } count++; - ql_update_cq(rx_ring); - prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg); + qlge_update_cq(rx_ring); + prod = qlge_read_sh_reg(rx_ring->prod_idx_sh_reg); if (count == budget) break; } - ql_update_buffer_queues(rx_ring, GFP_ATOMIC, 0); - ql_write_cq_idx(rx_ring); + qlge_update_buffer_queues(rx_ring, GFP_ATOMIC, 0); + qlge_write_cq_idx(rx_ring); return count; } -static int ql_napi_poll_msix(struct napi_struct *napi, int budget) +static int qlge_napi_poll_msix(struct napi_struct *napi, int budget) { struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi); - struct ql_adapter *qdev = rx_ring->qdev; + struct qlge_adapter *qdev = rx_ring->qdev; struct rx_ring *trx_ring; int i, work_done = 0; struct intr_context *ctx = &qdev->intr_context[rx_ring->cq_id]; @@ -2200,42 +2196,42 @@ static int ql_napi_poll_msix(struct napi_struct *napi, int budget) * it's not empty then service it. */ if ((ctx->irq_mask & (1 << trx_ring->cq_id)) && - (ql_read_sh_reg(trx_ring->prod_idx_sh_reg) != + (qlge_read_sh_reg(trx_ring->prod_idx_sh_reg) != trx_ring->cnsmr_idx)) { netif_printk(qdev, intr, KERN_DEBUG, qdev->ndev, "%s: Servicing TX completion ring %d.\n", __func__, trx_ring->cq_id); - ql_clean_outbound_rx_ring(trx_ring); + qlge_clean_outbound_rx_ring(trx_ring); } } /* * Now service the RSS ring if it's active. */ - if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != - rx_ring->cnsmr_idx) { + if (qlge_read_sh_reg(rx_ring->prod_idx_sh_reg) != + rx_ring->cnsmr_idx) { netif_printk(qdev, intr, KERN_DEBUG, qdev->ndev, "%s: Servicing RX completion ring %d.\n", __func__, rx_ring->cq_id); - work_done = ql_clean_inbound_rx_ring(rx_ring, budget); + work_done = qlge_clean_inbound_rx_ring(rx_ring, budget); } if (work_done < budget) { napi_complete_done(napi, work_done); - ql_enable_completion_interrupt(qdev, rx_ring->irq); + qlge_enable_completion_interrupt(qdev, rx_ring->irq); } return work_done; } static void qlge_vlan_mode(struct net_device *ndev, netdev_features_t features) { - struct ql_adapter *qdev = netdev_priv(ndev); + struct qlge_adapter *qdev = netdev_to_qdev(ndev); if (features & NETIF_F_HW_VLAN_CTAG_RX) { - ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK | - NIC_RCV_CFG_VLAN_MATCH_AND_NON); + qlge_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK | + NIC_RCV_CFG_VLAN_MATCH_AND_NON); } else { - ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK); + qlge_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK); } } @@ -2246,12 +2242,12 @@ static void qlge_vlan_mode(struct net_device *ndev, netdev_features_t features) static int qlge_update_hw_vlan_features(struct net_device *ndev, netdev_features_t features) { - struct ql_adapter *qdev = netdev_priv(ndev); - int status = 0; + struct qlge_adapter *qdev = netdev_to_qdev(ndev); bool need_restart = netif_running(ndev); + int status = 0; if (need_restart) { - status = ql_adapter_down(qdev); + status = qlge_adapter_down(qdev); if (status) { netif_err(qdev, link, qdev->ndev, "Failed to bring down the adapter\n"); @@ -2263,7 +2259,7 @@ static int qlge_update_hw_vlan_features(struct net_device *ndev, ndev->features = features; if (need_restart) { - status = ql_adapter_up(qdev); + status = qlge_adapter_up(qdev); if (status) { netif_err(qdev, link, qdev->ndev, "Failed to bring up the adapter\n"); @@ -2292,13 +2288,13 @@ static int qlge_set_features(struct net_device *ndev, return 0; } -static int __qlge_vlan_rx_add_vid(struct ql_adapter *qdev, u16 vid) +static int __qlge_vlan_rx_add_vid(struct qlge_adapter *qdev, u16 vid) { u32 enable_bit = MAC_ADDR_E; int err; - err = ql_set_mac_addr_reg(qdev, (u8 *)&enable_bit, - MAC_ADDR_TYPE_VLAN, vid); + err = qlge_set_mac_addr_reg(qdev, (u8 *)&enable_bit, + MAC_ADDR_TYPE_VLAN, vid); if (err) netif_err(qdev, ifup, qdev->ndev, "Failed to init vlan address.\n"); @@ -2307,29 +2303,29 @@ static int __qlge_vlan_rx_add_vid(struct ql_adapter *qdev, u16 vid) static int qlge_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) { - struct ql_adapter *qdev = netdev_priv(ndev); + struct qlge_adapter *qdev = netdev_to_qdev(ndev); int status; int err; - status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); + status = qlge_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); if (status) return status; err = __qlge_vlan_rx_add_vid(qdev, vid); set_bit(vid, qdev->active_vlans); - ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK); + qlge_sem_unlock(qdev, SEM_MAC_ADDR_MASK); return err; } -static int __qlge_vlan_rx_kill_vid(struct ql_adapter *qdev, u16 vid) +static int __qlge_vlan_rx_kill_vid(struct qlge_adapter *qdev, u16 vid) { u32 enable_bit = 0; int err; - err = ql_set_mac_addr_reg(qdev, (u8 *)&enable_bit, - MAC_ADDR_TYPE_VLAN, vid); + err = qlge_set_mac_addr_reg(qdev, (u8 *)&enable_bit, + MAC_ADDR_TYPE_VLAN, vid); if (err) netif_err(qdev, ifup, qdev->ndev, "Failed to clear vlan address.\n"); @@ -2338,35 +2334,35 @@ static int __qlge_vlan_rx_kill_vid(struct ql_adapter *qdev, u16 vid) static int qlge_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) { - struct ql_adapter *qdev = netdev_priv(ndev); + struct qlge_adapter *qdev = netdev_to_qdev(ndev); int status; int err; - status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); + status = qlge_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); if (status) return status; err = __qlge_vlan_rx_kill_vid(qdev, vid); clear_bit(vid, qdev->active_vlans); - ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK); + qlge_sem_unlock(qdev, SEM_MAC_ADDR_MASK); return err; } -static void qlge_restore_vlan(struct ql_adapter *qdev) +static void qlge_restore_vlan(struct qlge_adapter *qdev) { int status; u16 vid; - status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); + status = qlge_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); if (status) return; for_each_set_bit(vid, qdev->active_vlans, VLAN_N_VID) __qlge_vlan_rx_add_vid(qdev, vid); - ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK); + qlge_sem_unlock(qdev, SEM_MAC_ADDR_MASK); } /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */ @@ -2386,7 +2382,7 @@ static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id) static irqreturn_t qlge_isr(int irq, void *dev_id) { struct rx_ring *rx_ring = dev_id; - struct ql_adapter *qdev = rx_ring->qdev; + struct qlge_adapter *qdev = rx_ring->qdev; struct intr_context *intr_context = &qdev->intr_context[0]; u32 var; int work_done = 0; @@ -2398,18 +2394,18 @@ static irqreturn_t qlge_isr(int irq, void *dev_id) * enable it is not effective. */ if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) - ql_disable_completion_interrupt(qdev, 0); + qlge_disable_completion_interrupt(qdev, 0); - var = ql_read32(qdev, STS); + var = qlge_read32(qdev, STS); /* * Check for fatal error. */ if (var & STS_FE) { - ql_disable_completion_interrupt(qdev, 0); - ql_queue_asic_error(qdev); + qlge_disable_completion_interrupt(qdev, 0); + qlge_queue_asic_error(qdev); netdev_err(qdev->ndev, "Got fatal error, STS = %x.\n", var); - var = ql_read32(qdev, ERR_STS); + var = qlge_read32(qdev, ERR_STS); netdev_err(qdev->ndev, "Resetting chip. Error Status Register = 0x%x\n", var); return IRQ_HANDLED; } @@ -2418,14 +2414,14 @@ static irqreturn_t qlge_isr(int irq, void *dev_id) * Check MPI processor activity. */ if ((var & STS_PI) && - (ql_read32(qdev, INTR_MASK) & INTR_MASK_PI)) { + (qlge_read32(qdev, INTR_MASK) & INTR_MASK_PI)) { /* * We've got an async event or mailbox completion. * Handle it and clear the source of the interrupt. */ netif_err(qdev, intr, qdev->ndev, "Got MPI processor interrupt.\n"); - ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16)); + qlge_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16)); queue_delayed_work_on(smp_processor_id(), qdev->workqueue, &qdev->mpi_work, 0); work_done++; @@ -2436,7 +2432,7 @@ static irqreturn_t qlge_isr(int irq, void *dev_id) * pass. Compare it to the queues that this irq services * and call napi if there's a match. */ - var = ql_read32(qdev, ISR1); + var = qlge_read32(qdev, ISR1); if (var & intr_context->irq_mask) { netif_info(qdev, intr, qdev->ndev, "Waking handler for rx_ring[0].\n"); @@ -2449,13 +2445,13 @@ static irqreturn_t qlge_isr(int irq, void *dev_id) * systematically re-enable the interrupt if we didn't * schedule napi. */ - ql_enable_completion_interrupt(qdev, 0); + qlge_enable_completion_interrupt(qdev, 0); } return work_done ? IRQ_HANDLED : IRQ_NONE; } -static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr) +static int qlge_tso(struct sk_buff *skb, struct qlge_ob_mac_tso_iocb_req *mac_iocb_ptr) { if (skb_is_gso(skb)) { int err; @@ -2469,11 +2465,11 @@ static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr) mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC; mac_iocb_ptr->frame_len = cpu_to_le32((u32)skb->len); mac_iocb_ptr->total_hdrs_len = - cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb)); + cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb)); mac_iocb_ptr->net_trans_offset = - cpu_to_le16(skb_network_offset(skb) | - skb_transport_offset(skb) - << OB_MAC_TRANSPORT_HDR_SHIFT); + cpu_to_le16(skb_network_offset(skb) | + skb_transport_offset(skb) + << OB_MAC_TRANSPORT_HDR_SHIFT); mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size); mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO; if (likely(l3_proto == htons(ETH_P_IP))) { @@ -2488,17 +2484,17 @@ static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr) } else if (l3_proto == htons(ETH_P_IPV6)) { mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6; tcp_hdr(skb)->check = - ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, - &ipv6_hdr(skb)->daddr, - 0, IPPROTO_TCP, 0); + ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, + &ipv6_hdr(skb)->daddr, + 0, IPPROTO_TCP, 0); } return 1; } return 0; } -static void ql_hw_csum_setup(struct sk_buff *skb, - struct ob_mac_tso_iocb_req *mac_iocb_ptr) +static void qlge_hw_csum_setup(struct sk_buff *skb, + struct qlge_ob_mac_tso_iocb_req *mac_iocb_ptr) { int len; struct iphdr *iph = ip_hdr(skb); @@ -2508,7 +2504,7 @@ static void ql_hw_csum_setup(struct sk_buff *skb, mac_iocb_ptr->frame_len = cpu_to_le32((u32)skb->len); mac_iocb_ptr->net_trans_offset = cpu_to_le16(skb_network_offset(skb) | - skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT); + skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT); mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4; len = (ntohs(iph->tot_len) - (iph->ihl << 2)); @@ -2516,14 +2512,14 @@ static void ql_hw_csum_setup(struct sk_buff *skb, check = &(tcp_hdr(skb)->check); mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC; mac_iocb_ptr->total_hdrs_len = - cpu_to_le16(skb_transport_offset(skb) + - (tcp_hdr(skb)->doff << 2)); + cpu_to_le16(skb_transport_offset(skb) + + (tcp_hdr(skb)->doff << 2)); } else { check = &(udp_hdr(skb)->check); mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC; mac_iocb_ptr->total_hdrs_len = - cpu_to_le16(skb_transport_offset(skb) + - sizeof(struct udphdr)); + cpu_to_le16(skb_transport_offset(skb) + + sizeof(struct udphdr)); } *check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, len, iph->protocol, 0); @@ -2531,9 +2527,9 @@ static void ql_hw_csum_setup(struct sk_buff *skb, static netdev_tx_t qlge_send(struct sk_buff *skb, struct net_device *ndev) { + struct qlge_adapter *qdev = netdev_to_qdev(ndev); + struct qlge_ob_mac_iocb_req *mac_iocb_ptr; struct tx_ring_desc *tx_ring_desc; - struct ob_mac_iocb_req *mac_iocb_ptr; - struct ql_adapter *qdev = netdev_priv(ndev); int tso; struct tx_ring *tx_ring; u32 tx_ring_idx = (u32)skb->queue_mapping; @@ -2571,28 +2567,28 @@ static netdev_tx_t qlge_send(struct sk_buff *skb, struct net_device *ndev) mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V; mac_iocb_ptr->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb)); } - tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr); + tso = qlge_tso(skb, (struct qlge_ob_mac_tso_iocb_req *)mac_iocb_ptr); if (tso < 0) { dev_kfree_skb_any(skb); return NETDEV_TX_OK; } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) { - ql_hw_csum_setup(skb, - (struct ob_mac_tso_iocb_req *)mac_iocb_ptr); + qlge_hw_csum_setup(skb, + (struct qlge_ob_mac_tso_iocb_req *)mac_iocb_ptr); } - if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) != - NETDEV_TX_OK) { + if (qlge_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) != + NETDEV_TX_OK) { netif_err(qdev, tx_queued, qdev->ndev, "Could not map the segments.\n"); tx_ring->tx_errors++; return NETDEV_TX_BUSY; } - QL_DUMP_OB_MAC_IOCB(qdev, mac_iocb_ptr); + tx_ring->prod_idx++; if (tx_ring->prod_idx == tx_ring->wq_len) tx_ring->prod_idx = 0; wmb(); - ql_write_db_reg_relaxed(tx_ring->prod_idx, tx_ring->prod_idx_db_reg); + qlge_write_db_reg_relaxed(tx_ring->prod_idx, tx_ring->prod_idx_db_reg); netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev, "tx queued, slot %d, len %d\n", tx_ring->prod_idx, skb->len); @@ -2611,7 +2607,7 @@ static netdev_tx_t qlge_send(struct sk_buff *skb, struct net_device *ndev) return NETDEV_TX_OK; } -static void ql_free_shadow_space(struct ql_adapter *qdev) +static void qlge_free_shadow_space(struct qlge_adapter *qdev) { if (qdev->rx_ring_shadow_reg_area) { dma_free_coherent(&qdev->pdev->dev, @@ -2629,7 +2625,7 @@ static void ql_free_shadow_space(struct ql_adapter *qdev) } } -static int ql_alloc_shadow_space(struct ql_adapter *qdev) +static int qlge_alloc_shadow_space(struct qlge_adapter *qdev) { qdev->rx_ring_shadow_reg_area = dma_alloc_coherent(&qdev->pdev->dev, PAGE_SIZE, @@ -2658,11 +2654,11 @@ err_wqp_sh_area: return -ENOMEM; } -static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring) +static void qlge_init_tx_ring(struct qlge_adapter *qdev, struct tx_ring *tx_ring) { struct tx_ring_desc *tx_ring_desc; int i; - struct ob_mac_iocb_req *mac_iocb_ptr; + struct qlge_ob_mac_iocb_req *mac_iocb_ptr; mac_iocb_ptr = tx_ring->wq_base; tx_ring_desc = tx_ring->q; @@ -2676,8 +2672,8 @@ static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring) atomic_set(&tx_ring->tx_count, tx_ring->wq_len); } -static void ql_free_tx_resources(struct ql_adapter *qdev, - struct tx_ring *tx_ring) +static void qlge_free_tx_resources(struct qlge_adapter *qdev, + struct tx_ring *tx_ring) { if (tx_ring->wq_base) { dma_free_coherent(&qdev->pdev->dev, tx_ring->wq_size, @@ -2688,20 +2684,20 @@ static void ql_free_tx_resources(struct ql_adapter *qdev, tx_ring->q = NULL; } -static int ql_alloc_tx_resources(struct ql_adapter *qdev, - struct tx_ring *tx_ring) +static int qlge_alloc_tx_resources(struct qlge_adapter *qdev, + struct tx_ring *tx_ring) { tx_ring->wq_base = - dma_alloc_coherent(&qdev->pdev->dev, tx_ring->wq_size, - &tx_ring->wq_base_dma, GFP_ATOMIC); + dma_alloc_coherent(&qdev->pdev->dev, tx_ring->wq_size, + &tx_ring->wq_base_dma, GFP_ATOMIC); if (!tx_ring->wq_base || tx_ring->wq_base_dma & WQ_ADDR_ALIGN) goto pci_alloc_err; tx_ring->q = - kmalloc_array(tx_ring->wq_len, sizeof(struct tx_ring_desc), - GFP_KERNEL); + kmalloc_array(tx_ring->wq_len, sizeof(struct tx_ring_desc), + GFP_KERNEL); if (!tx_ring->q) goto err; @@ -2715,19 +2711,19 @@ pci_alloc_err: return -ENOMEM; } -static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring) +static void qlge_free_lbq_buffers(struct qlge_adapter *qdev, struct rx_ring *rx_ring) { struct qlge_bq *lbq = &rx_ring->lbq; unsigned int last_offset; - last_offset = ql_lbq_block_size(qdev) - qdev->lbq_buf_size; + last_offset = qlge_lbq_block_size(qdev) - qdev->lbq_buf_size; while (lbq->next_to_clean != lbq->next_to_use) { struct qlge_bq_desc *lbq_desc = &lbq->queue[lbq->next_to_clean]; if (lbq_desc->p.pg_chunk.offset == last_offset) dma_unmap_page(&qdev->pdev->dev, lbq_desc->dma_addr, - ql_lbq_block_size(qdev), + qlge_lbq_block_size(qdev), DMA_FROM_DEVICE); put_page(lbq_desc->p.pg_chunk.page); @@ -2736,13 +2732,13 @@ static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring if (rx_ring->master_chunk.page) { dma_unmap_page(&qdev->pdev->dev, rx_ring->chunk_dma_addr, - ql_lbq_block_size(qdev), DMA_FROM_DEVICE); + qlge_lbq_block_size(qdev), DMA_FROM_DEVICE); put_page(rx_ring->master_chunk.page); rx_ring->master_chunk.page = NULL; } } -static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring) +static void qlge_free_sbq_buffers(struct qlge_adapter *qdev, struct rx_ring *rx_ring) { int i; @@ -2767,7 +2763,7 @@ static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring /* Free all large and small rx buffers associated * with the completion queues for this device. */ -static void ql_free_rx_buffers(struct ql_adapter *qdev) +static void qlge_free_rx_buffers(struct qlge_adapter *qdev) { int i; @@ -2775,25 +2771,25 @@ static void ql_free_rx_buffers(struct ql_adapter *qdev) struct rx_ring *rx_ring = &qdev->rx_ring[i]; if (rx_ring->lbq.queue) - ql_free_lbq_buffers(qdev, rx_ring); + qlge_free_lbq_buffers(qdev, rx_ring); if (rx_ring->sbq.queue) - ql_free_sbq_buffers(qdev, rx_ring); + qlge_free_sbq_buffers(qdev, rx_ring); } } -static void ql_alloc_rx_buffers(struct ql_adapter *qdev) +static void qlge_alloc_rx_buffers(struct qlge_adapter *qdev) { int i; for (i = 0; i < qdev->rss_ring_count; i++) - ql_update_buffer_queues(&qdev->rx_ring[i], GFP_KERNEL, - HZ / 2); + qlge_update_buffer_queues(&qdev->rx_ring[i], GFP_KERNEL, + HZ / 2); } static int qlge_init_bq(struct qlge_bq *bq) { struct rx_ring *rx_ring = QLGE_BQ_CONTAINER(bq); - struct ql_adapter *qdev = rx_ring->qdev; + struct qlge_adapter *qdev = rx_ring->qdev; struct qlge_bq_desc *bq_desc; __le64 *buf_ptr; int i; @@ -2823,8 +2819,8 @@ static int qlge_init_bq(struct qlge_bq *bq) return 0; } -static void ql_free_rx_resources(struct ql_adapter *qdev, - struct rx_ring *rx_ring) +static void qlge_free_rx_resources(struct qlge_adapter *qdev, + struct rx_ring *rx_ring) { /* Free the small buffer queue. */ if (rx_ring->sbq.base) { @@ -2860,15 +2856,15 @@ static void ql_free_rx_resources(struct ql_adapter *qdev, /* Allocate queues and buffers for this completions queue based * on the values in the parameter structure. */ -static int ql_alloc_rx_resources(struct ql_adapter *qdev, - struct rx_ring *rx_ring) +static int qlge_alloc_rx_resources(struct qlge_adapter *qdev, + struct rx_ring *rx_ring) { /* * Allocate the completion queue for this rx_ring. */ rx_ring->cq_base = - dma_alloc_coherent(&qdev->pdev->dev, rx_ring->cq_size, - &rx_ring->cq_base_dma, GFP_ATOMIC); + dma_alloc_coherent(&qdev->pdev->dev, rx_ring->cq_size, + &rx_ring->cq_base_dma, GFP_ATOMIC); if (!rx_ring->cq_base) { netif_err(qdev, ifup, qdev->ndev, "rx_ring alloc failed.\n"); @@ -2877,14 +2873,14 @@ static int ql_alloc_rx_resources(struct ql_adapter *qdev, if (rx_ring->cq_id < qdev->rss_ring_count && (qlge_init_bq(&rx_ring->sbq) || qlge_init_bq(&rx_ring->lbq))) { - ql_free_rx_resources(qdev, rx_ring); + qlge_free_rx_resources(qdev, rx_ring); return -ENOMEM; } return 0; } -static void ql_tx_ring_clean(struct ql_adapter *qdev) +static void qlge_tx_ring_clean(struct qlge_adapter *qdev) { struct tx_ring *tx_ring; struct tx_ring_desc *tx_ring_desc; @@ -2903,8 +2899,8 @@ static void ql_tx_ring_clean(struct ql_adapter *qdev) "Freeing lost SKB %p, from queue %d, index %d.\n", tx_ring_desc->skb, j, tx_ring_desc->index); - ql_unmap_send(qdev, tx_ring_desc, - tx_ring_desc->map_cnt); + qlge_unmap_send(qdev, tx_ring_desc, + tx_ring_desc->map_cnt); dev_kfree_skb(tx_ring_desc->skb); tx_ring_desc->skb = NULL; } @@ -2912,27 +2908,27 @@ static void ql_tx_ring_clean(struct ql_adapter *qdev) } } -static void ql_free_mem_resources(struct ql_adapter *qdev) +static void qlge_free_mem_resources(struct qlge_adapter *qdev) { int i; for (i = 0; i < qdev->tx_ring_count; i++) - ql_free_tx_resources(qdev, &qdev->tx_ring[i]); + qlge_free_tx_resources(qdev, &qdev->tx_ring[i]); for (i = 0; i < qdev->rx_ring_count; i++) - ql_free_rx_resources(qdev, &qdev->rx_ring[i]); - ql_free_shadow_space(qdev); + qlge_free_rx_resources(qdev, &qdev->rx_ring[i]); + qlge_free_shadow_space(qdev); } -static int ql_alloc_mem_resources(struct ql_adapter *qdev) +static int qlge_alloc_mem_resources(struct qlge_adapter *qdev) { int i; /* Allocate space for our shadow registers and such. */ - if (ql_alloc_shadow_space(qdev)) + if (qlge_alloc_shadow_space(qdev)) return -ENOMEM; for (i = 0; i < qdev->rx_ring_count; i++) { - if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) { + if (qlge_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) { netif_err(qdev, ifup, qdev->ndev, "RX resource allocation failed.\n"); goto err_mem; @@ -2940,7 +2936,7 @@ static int ql_alloc_mem_resources(struct ql_adapter *qdev) } /* Allocate tx queue resources */ for (i = 0; i < qdev->tx_ring_count; i++) { - if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) { + if (qlge_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) { netif_err(qdev, ifup, qdev->ndev, "TX resource allocation failed.\n"); goto err_mem; @@ -2949,7 +2945,7 @@ static int ql_alloc_mem_resources(struct ql_adapter *qdev) return 0; err_mem: - ql_free_mem_resources(qdev); + qlge_free_mem_resources(qdev); return -ENOMEM; } @@ -2957,7 +2953,7 @@ err_mem: * The control block is defined as * "Completion Queue Initialization Control Block", or cqicb. */ -static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring) +static int qlge_start_rx_ring(struct qlge_adapter *qdev, struct rx_ring *rx_ring) { struct cqicb *cqicb = &rx_ring->cqicb; void *shadow_reg = qdev->rx_ring_shadow_reg_area + @@ -2965,7 +2961,7 @@ static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring) u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma + (rx_ring->cq_id * RX_RING_SHADOW_SPACE); void __iomem *doorbell_area = - qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id)); + qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id)); int err = 0; u64 tmp; __le64 *base_indirect_ptr; @@ -3012,8 +3008,8 @@ static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring) * Set up the control block load flags. */ cqicb->flags = FLAGS_LC | /* Load queue base address */ - FLAGS_LV | /* Load MSI-X vector */ - FLAGS_LI; /* Load irq delay values */ + FLAGS_LV | /* Load MSI-X vector */ + FLAGS_LI; /* Load irq delay values */ if (rx_ring->cq_id < qdev->rss_ring_count) { cqicb->flags |= FLAGS_LL; /* Load lbq values */ tmp = (u64)rx_ring->lbq.base_dma; @@ -3043,7 +3039,7 @@ static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring) page_entries++; } while (page_entries < MAX_DB_PAGES_PER_BQ(QLGE_BQ_LEN)); cqicb->sbq_addr = - cpu_to_le64(rx_ring->sbq.base_indirect_dma); + cpu_to_le64(rx_ring->sbq.base_indirect_dma); cqicb->sbq_buf_size = cpu_to_le16(SMALL_BUFFER_SIZE); cqicb->sbq_len = cpu_to_le16(QLGE_FIT16(QLGE_BQ_LEN)); rx_ring->sbq.next_to_use = 0; @@ -3053,7 +3049,7 @@ static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring) /* Inbound completion handling rx_rings run in * separate NAPI contexts. */ - netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix, + netif_napi_add(qdev->ndev, &rx_ring->napi, qlge_napi_poll_msix, 64); cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs); cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames); @@ -3061,8 +3057,8 @@ static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring) cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs); cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames); } - err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb), - CFG_LCQ, rx_ring->cq_id); + err = qlge_write_cfg(qdev, cqicb, sizeof(struct cqicb), + CFG_LCQ, rx_ring->cq_id); if (err) { netif_err(qdev, ifup, qdev->ndev, "Failed to load CQICB.\n"); return err; @@ -3070,15 +3066,15 @@ static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring) return err; } -static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring) +static int qlge_start_tx_ring(struct qlge_adapter *qdev, struct tx_ring *tx_ring) { struct wqicb *wqicb = (struct wqicb *)tx_ring; void __iomem *doorbell_area = - qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id); + qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id); void *shadow_reg = qdev->tx_ring_shadow_reg_area + - (tx_ring->wq_id * sizeof(u64)); + (tx_ring->wq_id * sizeof(u64)); u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma + - (tx_ring->wq_id * sizeof(u64)); + (tx_ring->wq_id * sizeof(u64)); int err = 0; /* @@ -3105,10 +3101,10 @@ static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring) wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma); - ql_init_tx_ring(qdev, tx_ring); + qlge_init_tx_ring(qdev, tx_ring); - err = ql_write_cfg(qdev, wqicb, sizeof(*wqicb), CFG_LRQ, - (u16)tx_ring->wq_id); + err = qlge_write_cfg(qdev, wqicb, sizeof(*wqicb), CFG_LRQ, + (u16)tx_ring->wq_id); if (err) { netif_err(qdev, ifup, qdev->ndev, "Failed to load tx_ring.\n"); return err; @@ -3116,7 +3112,7 @@ static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring) return err; } -static void ql_disable_msix(struct ql_adapter *qdev) +static void qlge_disable_msix(struct qlge_adapter *qdev) { if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) { pci_disable_msix(qdev->pdev); @@ -3133,7 +3129,7 @@ static void ql_disable_msix(struct ql_adapter *qdev) * stored in qdev->intr_count. If we don't get that * many then we reduce the count and try again. */ -static void ql_enable_msix(struct ql_adapter *qdev) +static void qlge_enable_msix(struct qlge_adapter *qdev) { int i, err; @@ -3186,7 +3182,7 @@ msi: "Running with legacy interrupts.\n"); } -/* Each vector services 1 RSS ring and and 1 or more +/* Each vector services 1 RSS ring and 1 or more * TX completion rings. This function loops through * the TX completion rings and assigns the vector that * will service it. An example would be if there are @@ -3195,7 +3191,7 @@ msi: * and TX completion rings 0,1,2 and 3. Vector 1 would * service RSS ring 1 and TX completion rings 4,5,6 and 7. */ -static void ql_set_tx_vect(struct ql_adapter *qdev) +static void qlge_set_tx_vect(struct qlge_adapter *qdev) { int i, j, vect; u32 tx_rings_per_vector = qdev->tx_ring_count / qdev->intr_count; @@ -3203,7 +3199,7 @@ static void ql_set_tx_vect(struct ql_adapter *qdev) if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) { /* Assign irq vectors to TX rx_rings.*/ for (vect = 0, j = 0, i = qdev->rss_ring_count; - i < qdev->rx_ring_count; i++) { + i < qdev->rx_ring_count; i++) { if (j == tx_rings_per_vector) { vect++; j = 0; @@ -3225,7 +3221,7 @@ static void ql_set_tx_vect(struct ql_adapter *qdev) * rings. This function sets up a bit mask per vector * that indicates which rings it services. */ -static void ql_set_irq_mask(struct ql_adapter *qdev, struct intr_context *ctx) +static void qlge_set_irq_mask(struct qlge_adapter *qdev, struct intr_context *ctx) { int j, vect = ctx->intr; u32 tx_rings_per_vector = qdev->tx_ring_count / qdev->intr_count; @@ -3240,8 +3236,8 @@ static void ql_set_irq_mask(struct ql_adapter *qdev, struct intr_context *ctx) */ for (j = 0; j < tx_rings_per_vector; j++) { ctx->irq_mask |= - (1 << qdev->rx_ring[qdev->rss_ring_count + - (vect * tx_rings_per_vector) + j].cq_id); + (1 << qdev->rx_ring[qdev->rss_ring_count + + (vect * tx_rings_per_vector) + j].cq_id); } } else { /* For single vector we just shift each queue's @@ -3258,7 +3254,7 @@ static void ql_set_irq_mask(struct ql_adapter *qdev, struct intr_context *ctx) * The intr_context structure is used to hook each vector * to possibly different handlers. */ -static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev) +static void qlge_resolve_queues_to_irqs(struct qlge_adapter *qdev) { int i = 0; struct intr_context *intr_context = &qdev->intr_context[0]; @@ -3275,23 +3271,23 @@ static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev) /* Set up this vector's bit-mask that indicates * which queues it services. */ - ql_set_irq_mask(qdev, intr_context); + qlge_set_irq_mask(qdev, intr_context); /* * We set up each vectors enable/disable/read bits so * there's no bit/mask calculations in the critical path. */ intr_context->intr_en_mask = - INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | - INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD - | i; + INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | + INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD + | i; intr_context->intr_dis_mask = - INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | - INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK | - INTR_EN_IHD | i; + INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | + INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK | + INTR_EN_IHD | i; intr_context->intr_read_mask = - INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | - INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD | - i; + INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | + INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD | + i; if (i == 0) { /* The first vector/queue handles * broadcast/multicast, fatal errors, @@ -3322,10 +3318,10 @@ static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev) * there's no bit/mask calculations in the critical path. */ intr_context->intr_en_mask = - INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE; + INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE; intr_context->intr_dis_mask = - INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | - INTR_EN_TYPE_DISABLE; + INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | + INTR_EN_TYPE_DISABLE; if (test_bit(QL_LEGACY_ENABLED, &qdev->flags)) { /* Experience shows that when using INTx interrupts, * the device does not always auto-mask INTR_EN_EN. @@ -3337,7 +3333,7 @@ static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev) intr_context->intr_dis_mask |= INTR_EN_EI << 16; } intr_context->intr_read_mask = - INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ; + INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ; /* * Single interrupt means one handler for all rings. */ @@ -3348,15 +3344,15 @@ static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev) * a single vector so it will service all RSS and * TX completion rings. */ - ql_set_irq_mask(qdev, intr_context); + qlge_set_irq_mask(qdev, intr_context); } /* Tell the TX completion rings which MSIx vector * they will be using. */ - ql_set_tx_vect(qdev); + qlge_set_tx_vect(qdev); } -static void ql_free_irq(struct ql_adapter *qdev) +static void qlge_free_irq(struct qlge_adapter *qdev) { int i; struct intr_context *intr_context = &qdev->intr_context[0]; @@ -3371,17 +3367,17 @@ static void ql_free_irq(struct ql_adapter *qdev) } } } - ql_disable_msix(qdev); + qlge_disable_msix(qdev); } -static int ql_request_irq(struct ql_adapter *qdev) +static int qlge_request_irq(struct qlge_adapter *qdev) { int i; int status = 0; struct pci_dev *pdev = qdev->pdev; struct intr_context *intr_context = &qdev->intr_context[0]; - ql_resolve_queues_to_irqs(qdev); + qlge_resolve_queues_to_irqs(qdev); for (i = 0; i < qdev->intr_count; i++, intr_context++) { if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) { @@ -3408,11 +3404,11 @@ static int ql_request_irq(struct ql_adapter *qdev) "%s: dev_id = 0x%p.\n", __func__, &qdev->rx_ring[0]); status = - request_irq(pdev->irq, qlge_isr, - test_bit(QL_MSI_ENABLED, &qdev->flags) - ? 0 - : IRQF_SHARED, - intr_context->name, &qdev->rx_ring[0]); + request_irq(pdev->irq, qlge_isr, + test_bit(QL_MSI_ENABLED, &qdev->flags) + ? 0 + : IRQF_SHARED, + intr_context->name, &qdev->rx_ring[0]); if (status) goto err_irq; @@ -3425,11 +3421,11 @@ static int ql_request_irq(struct ql_adapter *qdev) return status; err_irq: netif_err(qdev, ifup, qdev->ndev, "Failed to get the interrupts!!!\n"); - ql_free_irq(qdev); + qlge_free_irq(qdev); return status; } -static int ql_start_rss(struct ql_adapter *qdev) +static int qlge_start_rss(struct qlge_adapter *qdev) { static const u8 init_hash_seed[] = { 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, @@ -3459,7 +3455,7 @@ static int ql_start_rss(struct ql_adapter *qdev) memcpy((void *)&ricb->ipv6_hash_key[0], init_hash_seed, 40); memcpy((void *)&ricb->ipv4_hash_key[0], init_hash_seed, 16); - status = ql_write_cfg(qdev, ricb, sizeof(*ricb), CFG_LR, 0); + status = qlge_write_cfg(qdev, ricb, sizeof(*ricb), CFG_LR, 0); if (status) { netif_err(qdev, ifup, qdev->ndev, "Failed to load RICB.\n"); return status; @@ -3467,55 +3463,55 @@ static int ql_start_rss(struct ql_adapter *qdev) return status; } -static int ql_clear_routing_entries(struct ql_adapter *qdev) +static int qlge_clear_routing_entries(struct qlge_adapter *qdev) { int i, status = 0; - status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK); + status = qlge_sem_spinlock(qdev, SEM_RT_IDX_MASK); if (status) return status; /* Clear all the entries in the routing table. */ for (i = 0; i < 16; i++) { - status = ql_set_routing_reg(qdev, i, 0, 0); + status = qlge_set_routing_reg(qdev, i, 0, 0); if (status) { netif_err(qdev, ifup, qdev->ndev, "Failed to init routing register for CAM packets.\n"); break; } } - ql_sem_unlock(qdev, SEM_RT_IDX_MASK); + qlge_sem_unlock(qdev, SEM_RT_IDX_MASK); return status; } /* Initialize the frame-to-queue routing. */ -static int ql_route_initialize(struct ql_adapter *qdev) +static int qlge_route_initialize(struct qlge_adapter *qdev) { int status = 0; /* Clear all the entries in the routing table. */ - status = ql_clear_routing_entries(qdev); + status = qlge_clear_routing_entries(qdev); if (status) return status; - status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK); + status = qlge_sem_spinlock(qdev, SEM_RT_IDX_MASK); if (status) return status; - status = ql_set_routing_reg(qdev, RT_IDX_IP_CSUM_ERR_SLOT, - RT_IDX_IP_CSUM_ERR, 1); + status = qlge_set_routing_reg(qdev, RT_IDX_IP_CSUM_ERR_SLOT, + RT_IDX_IP_CSUM_ERR, 1); if (status) { netif_err(qdev, ifup, qdev->ndev, "Failed to init routing register for IP CSUM error packets.\n"); goto exit; } - status = ql_set_routing_reg(qdev, RT_IDX_TCP_UDP_CSUM_ERR_SLOT, - RT_IDX_TU_CSUM_ERR, 1); + status = qlge_set_routing_reg(qdev, RT_IDX_TCP_UDP_CSUM_ERR_SLOT, + RT_IDX_TU_CSUM_ERR, 1); if (status) { netif_err(qdev, ifup, qdev->ndev, "Failed to init routing register for TCP/UDP CSUM error packets.\n"); goto exit; } - status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1); + status = qlge_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1); if (status) { netif_err(qdev, ifup, qdev->ndev, "Failed to init routing register for broadcast packets.\n"); @@ -3525,8 +3521,8 @@ static int ql_route_initialize(struct ql_adapter *qdev) * routing block. */ if (qdev->rss_ring_count > 1) { - status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT, - RT_IDX_RSS_MATCH, 1); + status = qlge_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT, + RT_IDX_RSS_MATCH, 1); if (status) { netif_err(qdev, ifup, qdev->ndev, "Failed to init routing register for MATCH RSS packets.\n"); @@ -3534,17 +3530,17 @@ static int ql_route_initialize(struct ql_adapter *qdev) } } - status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT, - RT_IDX_CAM_HIT, 1); + status = qlge_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT, + RT_IDX_CAM_HIT, 1); if (status) netif_err(qdev, ifup, qdev->ndev, "Failed to init routing register for CAM packets.\n"); exit: - ql_sem_unlock(qdev, SEM_RT_IDX_MASK); + qlge_sem_unlock(qdev, SEM_RT_IDX_MASK); return status; } -int ql_cam_route_initialize(struct ql_adapter *qdev) +int qlge_cam_route_initialize(struct qlge_adapter *qdev) { int status, set; @@ -3552,22 +3548,22 @@ int ql_cam_route_initialize(struct ql_adapter *qdev) * determine if we are setting or clearing * the MAC address in the CAM. */ - set = ql_read32(qdev, STS); + set = qlge_read32(qdev, STS); set &= qdev->port_link_up; - status = ql_set_mac_addr(qdev, set); + status = qlge_set_mac_addr(qdev, set); if (status) { netif_err(qdev, ifup, qdev->ndev, "Failed to init mac address.\n"); return status; } - status = ql_route_initialize(qdev); + status = qlge_route_initialize(qdev); if (status) netif_err(qdev, ifup, qdev->ndev, "Failed to init routing table.\n"); return status; } -static int ql_adapter_initialize(struct ql_adapter *qdev) +static int qlge_adapter_initialize(struct qlge_adapter *qdev) { u32 value, mask; int i; @@ -3578,7 +3574,7 @@ static int ql_adapter_initialize(struct ql_adapter *qdev) */ value = SYS_EFE | SYS_FAE; mask = value << 16; - ql_write32(qdev, SYS, mask | value); + qlge_write32(qdev, SYS, mask | value); /* Set the default queue, and VLAN behavior. */ value = NIC_RCV_CFG_DFQ; @@ -3587,40 +3583,40 @@ static int ql_adapter_initialize(struct ql_adapter *qdev) value |= NIC_RCV_CFG_RV; mask |= (NIC_RCV_CFG_RV << 16); } - ql_write32(qdev, NIC_RCV_CFG, (mask | value)); + qlge_write32(qdev, NIC_RCV_CFG, (mask | value)); /* Set the MPI interrupt to enabled. */ - ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI); + qlge_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI); /* Enable the function, set pagesize, enable error checking. */ value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND | - FSC_EC | FSC_VM_PAGE_4K; + FSC_EC | FSC_VM_PAGE_4K; value |= SPLT_SETTING; /* Set/clear header splitting. */ mask = FSC_VM_PAGESIZE_MASK | - FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16); - ql_write32(qdev, FSC, mask | value); + FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16); + qlge_write32(qdev, FSC, mask | value); - ql_write32(qdev, SPLT_HDR, SPLT_LEN); + qlge_write32(qdev, SPLT_HDR, SPLT_LEN); /* Set RX packet routing to use port/pci function on which the * packet arrived on in addition to usual frame routing. * This is helpful on bonding where both interfaces can have * the same MAC address. */ - ql_write32(qdev, RST_FO, RST_FO_RR_MASK | RST_FO_RR_RCV_FUNC_CQ); + qlge_write32(qdev, RST_FO, RST_FO_RR_MASK | RST_FO_RR_RCV_FUNC_CQ); /* Reroute all packets to our Interface. * They may have been routed to MPI firmware * due to WOL. */ - value = ql_read32(qdev, MGMT_RCV_CFG); + value = qlge_read32(qdev, MGMT_RCV_CFG); value &= ~MGMT_RCV_CFG_RM; mask = 0xffff0000; /* Sticky reg needs clearing due to WOL. */ - ql_write32(qdev, MGMT_RCV_CFG, mask); - ql_write32(qdev, MGMT_RCV_CFG, mask | value); + qlge_write32(qdev, MGMT_RCV_CFG, mask); + qlge_write32(qdev, MGMT_RCV_CFG, mask | value); /* Default WOL is enable on Mezz cards */ if (qdev->pdev->subsystem_device == 0x0068 || @@ -3629,7 +3625,7 @@ static int ql_adapter_initialize(struct ql_adapter *qdev) /* Start up the rx queues. */ for (i = 0; i < qdev->rx_ring_count; i++) { - status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]); + status = qlge_start_rx_ring(qdev, &qdev->rx_ring[i]); if (status) { netif_err(qdev, ifup, qdev->ndev, "Failed to start rx ring[%d].\n", i); @@ -3641,7 +3637,7 @@ static int ql_adapter_initialize(struct ql_adapter *qdev) * then download a RICB to configure RSS. */ if (qdev->rss_ring_count > 1) { - status = ql_start_rss(qdev); + status = qlge_start_rss(qdev); if (status) { netif_err(qdev, ifup, qdev->ndev, "Failed to start RSS.\n"); return status; @@ -3650,7 +3646,7 @@ static int ql_adapter_initialize(struct ql_adapter *qdev) /* Start up the tx queues. */ for (i = 0; i < qdev->tx_ring_count; i++) { - status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]); + status = qlge_start_tx_ring(qdev, &qdev->tx_ring[i]); if (status) { netif_err(qdev, ifup, qdev->ndev, "Failed to start tx ring[%d].\n", i); @@ -3664,7 +3660,7 @@ static int ql_adapter_initialize(struct ql_adapter *qdev) netif_err(qdev, ifup, qdev->ndev, "Failed to start port.\n"); /* Set up the MAC address and frame routing filter. */ - status = ql_cam_route_initialize(qdev); + status = qlge_cam_route_initialize(qdev); if (status) { netif_err(qdev, ifup, qdev->ndev, "Failed to init CAM/Routing tables.\n"); @@ -3679,14 +3675,14 @@ static int ql_adapter_initialize(struct ql_adapter *qdev) } /* Issue soft reset to chip. */ -static int ql_adapter_reset(struct ql_adapter *qdev) +static int qlge_adapter_reset(struct qlge_adapter *qdev) { u32 value; int status = 0; unsigned long end_jiffies; /* Clear all the entries in the routing table. */ - status = ql_clear_routing_entries(qdev); + status = qlge_clear_routing_entries(qdev); if (status) { netif_err(qdev, ifup, qdev->ndev, "Failed to clear routing bits.\n"); return status; @@ -3697,19 +3693,19 @@ static int ql_adapter_reset(struct ql_adapter *qdev) */ if (!test_bit(QL_ASIC_RECOVERY, &qdev->flags)) { /* Stop management traffic. */ - ql_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_STOP); + qlge_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_STOP); /* Wait for the NIC and MGMNT FIFOs to empty. */ - ql_wait_fifo_empty(qdev); + qlge_wait_fifo_empty(qdev); } else { clear_bit(QL_ASIC_RECOVERY, &qdev->flags); } - ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR); + qlge_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR); end_jiffies = jiffies + usecs_to_jiffies(30); do { - value = ql_read32(qdev, RST_FO); + value = qlge_read32(qdev, RST_FO); if ((value & RST_FO_FR) == 0) break; cpu_relax(); @@ -3722,13 +3718,13 @@ static int ql_adapter_reset(struct ql_adapter *qdev) } /* Resume management traffic. */ - ql_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_RESUME); + qlge_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_RESUME); return status; } -static void ql_display_dev_info(struct net_device *ndev) +static void qlge_display_dev_info(struct net_device *ndev) { - struct ql_adapter *qdev = netdev_priv(ndev); + struct qlge_adapter *qdev = netdev_to_qdev(ndev); netif_info(qdev, probe, qdev->ndev, "Function #%d, Port %d, NIC Roll %d, NIC Rev = %d, XG Roll = %d, XG Rev = %d.\n", @@ -3742,7 +3738,7 @@ static void ql_display_dev_info(struct net_device *ndev) "MAC address %pM\n", ndev->dev_addr); } -static int ql_wol(struct ql_adapter *qdev) +static int qlge_wol(struct qlge_adapter *qdev) { int status = 0; u32 wol = MB_WOL_DISABLE; @@ -3755,7 +3751,7 @@ static int ql_wol(struct ql_adapter *qdev) */ if (qdev->wol & (WAKE_ARP | WAKE_MAGICSECURE | WAKE_PHY | WAKE_UCAST | - WAKE_MCAST | WAKE_BCAST)) { + WAKE_MCAST | WAKE_BCAST)) { netif_err(qdev, ifdown, qdev->ndev, "Unsupported WOL parameter. qdev->wol = 0x%x.\n", qdev->wol); @@ -3763,7 +3759,7 @@ static int ql_wol(struct ql_adapter *qdev) } if (qdev->wol & WAKE_MAGIC) { - status = ql_mb_wol_set_magic(qdev, 1); + status = qlge_mb_wol_set_magic(qdev, 1); if (status) { netif_err(qdev, ifdown, qdev->ndev, "Failed to set magic packet on %s.\n", @@ -3779,7 +3775,7 @@ static int ql_wol(struct ql_adapter *qdev) if (qdev->wol) { wol |= MB_WOL_MODE_ON; - status = ql_mb_wol_mode(qdev, wol); + status = qlge_mb_wol_mode(qdev, wol); netif_err(qdev, drv, qdev->ndev, "WOL %s (wol code 0x%x) on %s\n", (status == 0) ? "Successfully set" : "Failed", @@ -3789,7 +3785,7 @@ static int ql_wol(struct ql_adapter *qdev) return status; } -static void ql_cancel_all_work_sync(struct ql_adapter *qdev) +static void qlge_cancel_all_work_sync(struct qlge_adapter *qdev) { /* Don't kill the reset worker thread if we * are in the process of recovery. @@ -3799,58 +3795,57 @@ static void ql_cancel_all_work_sync(struct ql_adapter *qdev) cancel_delayed_work_sync(&qdev->mpi_reset_work); cancel_delayed_work_sync(&qdev->mpi_work); cancel_delayed_work_sync(&qdev->mpi_idc_work); - cancel_delayed_work_sync(&qdev->mpi_core_to_log); cancel_delayed_work_sync(&qdev->mpi_port_cfg_work); } -static int ql_adapter_down(struct ql_adapter *qdev) +static int qlge_adapter_down(struct qlge_adapter *qdev) { int i, status = 0; - ql_link_off(qdev); + qlge_link_off(qdev); - ql_cancel_all_work_sync(qdev); + qlge_cancel_all_work_sync(qdev); for (i = 0; i < qdev->rss_ring_count; i++) napi_disable(&qdev->rx_ring[i].napi); clear_bit(QL_ADAPTER_UP, &qdev->flags); - ql_disable_interrupts(qdev); + qlge_disable_interrupts(qdev); - ql_tx_ring_clean(qdev); + qlge_tx_ring_clean(qdev); /* Call netif_napi_del() from common point. - */ + */ for (i = 0; i < qdev->rss_ring_count; i++) netif_napi_del(&qdev->rx_ring[i].napi); - status = ql_adapter_reset(qdev); + status = qlge_adapter_reset(qdev); if (status) netif_err(qdev, ifdown, qdev->ndev, "reset(func #%d) FAILED!\n", qdev->func); - ql_free_rx_buffers(qdev); + qlge_free_rx_buffers(qdev); return status; } -static int ql_adapter_up(struct ql_adapter *qdev) +static int qlge_adapter_up(struct qlge_adapter *qdev) { int err = 0; - err = ql_adapter_initialize(qdev); + err = qlge_adapter_initialize(qdev); if (err) { netif_info(qdev, ifup, qdev->ndev, "Unable to initialize adapter.\n"); goto err_init; } set_bit(QL_ADAPTER_UP, &qdev->flags); - ql_alloc_rx_buffers(qdev); + qlge_alloc_rx_buffers(qdev); /* If the port is initialized and the * link is up the turn on the carrier. */ - if ((ql_read32(qdev, STS) & qdev->port_init) && - (ql_read32(qdev, STS) & qdev->port_link_up)) - ql_link_on(qdev); + if ((qlge_read32(qdev, STS) & qdev->port_init) && + (qlge_read32(qdev, STS) & qdev->port_link_up)) + qlge_link_on(qdev); /* Restore rx mode. */ clear_bit(QL_ALLMULTI, &qdev->flags); clear_bit(QL_PROMISCUOUS, &qdev->flags); @@ -3859,34 +3854,34 @@ static int ql_adapter_up(struct ql_adapter *qdev) /* Restore vlan setting. */ qlge_restore_vlan(qdev); - ql_enable_interrupts(qdev); - ql_enable_all_completion_interrupts(qdev); + qlge_enable_interrupts(qdev); + qlge_enable_all_completion_interrupts(qdev); netif_tx_start_all_queues(qdev->ndev); return 0; err_init: - ql_adapter_reset(qdev); + qlge_adapter_reset(qdev); return err; } -static void ql_release_adapter_resources(struct ql_adapter *qdev) +static void qlge_release_adapter_resources(struct qlge_adapter *qdev) { - ql_free_mem_resources(qdev); - ql_free_irq(qdev); + qlge_free_mem_resources(qdev); + qlge_free_irq(qdev); } -static int ql_get_adapter_resources(struct ql_adapter *qdev) +static int qlge_get_adapter_resources(struct qlge_adapter *qdev) { - if (ql_alloc_mem_resources(qdev)) { + if (qlge_alloc_mem_resources(qdev)) { netif_err(qdev, ifup, qdev->ndev, "Unable to allocate memory.\n"); return -ENOMEM; } - return ql_request_irq(qdev); + return qlge_request_irq(qdev); } static int qlge_close(struct net_device *ndev) { - struct ql_adapter *qdev = netdev_priv(ndev); + struct qlge_adapter *qdev = netdev_to_qdev(ndev); int i; /* If we hit pci_channel_io_perm_failure @@ -3910,12 +3905,12 @@ static int qlge_close(struct net_device *ndev) for (i = 0; i < qdev->rss_ring_count; i++) cancel_delayed_work_sync(&qdev->rx_ring[i].refill_work); - ql_adapter_down(qdev); - ql_release_adapter_resources(qdev); + qlge_adapter_down(qdev); + qlge_release_adapter_resources(qdev); return 0; } -static void qlge_set_lb_size(struct ql_adapter *qdev) +static void qlge_set_lb_size(struct qlge_adapter *qdev) { if (qdev->ndev->mtu <= 1500) qdev->lbq_buf_size = LARGE_BUFFER_MIN_SIZE; @@ -3924,22 +3919,22 @@ static void qlge_set_lb_size(struct ql_adapter *qdev) qdev->lbq_buf_order = get_order(qdev->lbq_buf_size); } -static int ql_configure_rings(struct ql_adapter *qdev) +static int qlge_configure_rings(struct qlge_adapter *qdev) { int i; struct rx_ring *rx_ring; struct tx_ring *tx_ring; - int cpu_cnt = min(MAX_CPUS, (int)num_online_cpus()); + int cpu_cnt = min_t(int, MAX_CPUS, num_online_cpus()); /* In a perfect world we have one RSS ring for each CPU * and each has it's own vector. To do that we ask for - * cpu_cnt vectors. ql_enable_msix() will adjust the + * cpu_cnt vectors. qlge_enable_msix() will adjust the * vector count to what we actually get. We then * allocate an RSS ring for each. * Essentially, we are doing min(cpu_count, msix_vector_count). */ qdev->intr_count = cpu_cnt; - ql_enable_msix(qdev); + qlge_enable_msix(qdev); /* Adjust the RSS ring count to the actual vector count. */ qdev->rss_ring_count = qdev->intr_count; qdev->tx_ring_count = cpu_cnt; @@ -3952,7 +3947,7 @@ static int ql_configure_rings(struct ql_adapter *qdev) tx_ring->wq_id = i; tx_ring->wq_len = qdev->tx_ring_size; tx_ring->wq_size = - tx_ring->wq_len * sizeof(struct ob_mac_iocb_req); + tx_ring->wq_len * sizeof(struct qlge_ob_mac_iocb_req); /* * The completion queue ID for the tx rings start @@ -3973,7 +3968,7 @@ static int ql_configure_rings(struct ql_adapter *qdev) */ rx_ring->cq_len = qdev->rx_ring_size; rx_ring->cq_size = - rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb); + rx_ring->cq_len * sizeof(struct qlge_net_rsp_iocb); rx_ring->lbq.type = QLGE_LB; rx_ring->sbq.type = QLGE_SB; INIT_DELAYED_WORK(&rx_ring->refill_work, @@ -3985,7 +3980,7 @@ static int ql_configure_rings(struct ql_adapter *qdev) /* outbound cq is same size as tx_ring it services. */ rx_ring->cq_len = qdev->tx_ring_size; rx_ring->cq_size = - rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb); + rx_ring->cq_len * sizeof(struct qlge_net_rsp_iocb); } } return 0; @@ -3993,34 +3988,34 @@ static int ql_configure_rings(struct ql_adapter *qdev) static int qlge_open(struct net_device *ndev) { + struct qlge_adapter *qdev = netdev_to_qdev(ndev); int err = 0; - struct ql_adapter *qdev = netdev_priv(ndev); - err = ql_adapter_reset(qdev); + err = qlge_adapter_reset(qdev); if (err) return err; qlge_set_lb_size(qdev); - err = ql_configure_rings(qdev); + err = qlge_configure_rings(qdev); if (err) return err; - err = ql_get_adapter_resources(qdev); + err = qlge_get_adapter_resources(qdev); if (err) goto error_up; - err = ql_adapter_up(qdev); + err = qlge_adapter_up(qdev); if (err) goto error_up; return err; error_up: - ql_release_adapter_resources(qdev); + qlge_release_adapter_resources(qdev); return err; } -static int ql_change_rx_buffers(struct ql_adapter *qdev) +static int qlge_change_rx_buffers(struct qlge_adapter *qdev) { int status; @@ -4041,13 +4036,13 @@ static int ql_change_rx_buffers(struct ql_adapter *qdev) } } - status = ql_adapter_down(qdev); + status = qlge_adapter_down(qdev); if (status) goto error; qlge_set_lb_size(qdev); - status = ql_adapter_up(qdev); + status = qlge_adapter_up(qdev); if (status) goto error; @@ -4062,7 +4057,7 @@ error: static int qlge_change_mtu(struct net_device *ndev, int new_mtu) { - struct ql_adapter *qdev = netdev_priv(ndev); + struct qlge_adapter *qdev = netdev_to_qdev(ndev); int status; if (ndev->mtu == 1500 && new_mtu == 9000) @@ -4080,7 +4075,7 @@ static int qlge_change_mtu(struct net_device *ndev, int new_mtu) if (!netif_running(qdev->ndev)) return 0; - status = ql_change_rx_buffers(qdev); + status = qlge_change_rx_buffers(qdev); if (status) { netif_err(qdev, ifup, qdev->ndev, "Changing MTU failed.\n"); @@ -4092,7 +4087,7 @@ static int qlge_change_mtu(struct net_device *ndev, int new_mtu) static struct net_device_stats *qlge_get_stats(struct net_device *ndev) { - struct ql_adapter *qdev = netdev_priv(ndev); + struct qlge_adapter *qdev = netdev_to_qdev(ndev); struct rx_ring *rx_ring = &qdev->rx_ring[0]; struct tx_ring *tx_ring = &qdev->tx_ring[0]; unsigned long pkts, mcast, dropped, errors, bytes; @@ -4128,11 +4123,11 @@ static struct net_device_stats *qlge_get_stats(struct net_device static void qlge_set_multicast_list(struct net_device *ndev) { - struct ql_adapter *qdev = netdev_priv(ndev); + struct qlge_adapter *qdev = netdev_to_qdev(ndev); struct netdev_hw_addr *ha; int i, status; - status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK); + status = qlge_sem_spinlock(qdev, SEM_RT_IDX_MASK); if (status) return; /* @@ -4141,7 +4136,7 @@ static void qlge_set_multicast_list(struct net_device *ndev) */ if (ndev->flags & IFF_PROMISC) { if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) { - if (ql_set_routing_reg + if (qlge_set_routing_reg (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) { netif_err(qdev, hw, qdev->ndev, "Failed to set promiscuous mode.\n"); @@ -4151,7 +4146,7 @@ static void qlge_set_multicast_list(struct net_device *ndev) } } else { if (test_bit(QL_PROMISCUOUS, &qdev->flags)) { - if (ql_set_routing_reg + if (qlge_set_routing_reg (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) { netif_err(qdev, hw, qdev->ndev, "Failed to clear promiscuous mode.\n"); @@ -4168,7 +4163,7 @@ static void qlge_set_multicast_list(struct net_device *ndev) if ((ndev->flags & IFF_ALLMULTI) || (netdev_mc_count(ndev) > MAX_MULTICAST_ENTRIES)) { if (!test_bit(QL_ALLMULTI, &qdev->flags)) { - if (ql_set_routing_reg + if (qlge_set_routing_reg (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) { netif_err(qdev, hw, qdev->ndev, "Failed to set all-multi mode.\n"); @@ -4178,7 +4173,7 @@ static void qlge_set_multicast_list(struct net_device *ndev) } } else { if (test_bit(QL_ALLMULTI, &qdev->flags)) { - if (ql_set_routing_reg + if (qlge_set_routing_reg (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) { netif_err(qdev, hw, qdev->ndev, "Failed to clear all-multi mode.\n"); @@ -4189,22 +4184,22 @@ static void qlge_set_multicast_list(struct net_device *ndev) } if (!netdev_mc_empty(ndev)) { - status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); + status = qlge_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); if (status) goto exit; i = 0; netdev_for_each_mc_addr(ha, ndev) { - if (ql_set_mac_addr_reg(qdev, (u8 *)ha->addr, - MAC_ADDR_TYPE_MULTI_MAC, i)) { + if (qlge_set_mac_addr_reg(qdev, (u8 *)ha->addr, + MAC_ADDR_TYPE_MULTI_MAC, i)) { netif_err(qdev, hw, qdev->ndev, "Failed to loadmulticast address.\n"); - ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK); + qlge_sem_unlock(qdev, SEM_MAC_ADDR_MASK); goto exit; } i++; } - ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK); - if (ql_set_routing_reg + qlge_sem_unlock(qdev, SEM_MAC_ADDR_MASK); + if (qlge_set_routing_reg (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) { netif_err(qdev, hw, qdev->ndev, "Failed to set multicast match mode.\n"); @@ -4213,12 +4208,12 @@ static void qlge_set_multicast_list(struct net_device *ndev) } } exit: - ql_sem_unlock(qdev, SEM_RT_IDX_MASK); + qlge_sem_unlock(qdev, SEM_RT_IDX_MASK); } static int qlge_set_mac_address(struct net_device *ndev, void *p) { - struct ql_adapter *qdev = netdev_priv(ndev); + struct qlge_adapter *qdev = netdev_to_qdev(ndev); struct sockaddr *addr = p; int status; @@ -4228,37 +4223,37 @@ static int qlge_set_mac_address(struct net_device *ndev, void *p) /* Update local copy of current mac address. */ memcpy(qdev->current_mac_addr, ndev->dev_addr, ndev->addr_len); - status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); + status = qlge_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); if (status) return status; - status = ql_set_mac_addr_reg(qdev, (u8 *)ndev->dev_addr, - MAC_ADDR_TYPE_CAM_MAC, - qdev->func * MAX_CQ); + status = qlge_set_mac_addr_reg(qdev, (u8 *)ndev->dev_addr, + MAC_ADDR_TYPE_CAM_MAC, + qdev->func * MAX_CQ); if (status) netif_err(qdev, hw, qdev->ndev, "Failed to load MAC address.\n"); - ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK); + qlge_sem_unlock(qdev, SEM_MAC_ADDR_MASK); return status; } static void qlge_tx_timeout(struct net_device *ndev, unsigned int txqueue) { - struct ql_adapter *qdev = netdev_priv(ndev); + struct qlge_adapter *qdev = netdev_to_qdev(ndev); - ql_queue_asic_error(qdev); + qlge_queue_asic_error(qdev); } -static void ql_asic_reset_work(struct work_struct *work) +static void qlge_asic_reset_work(struct work_struct *work) { - struct ql_adapter *qdev = - container_of(work, struct ql_adapter, asic_reset_work.work); + struct qlge_adapter *qdev = + container_of(work, struct qlge_adapter, asic_reset_work.work); int status; rtnl_lock(); - status = ql_adapter_down(qdev); + status = qlge_adapter_down(qdev); if (status) goto error; - status = ql_adapter_up(qdev); + status = qlge_adapter_up(qdev); if (status) goto error; @@ -4279,13 +4274,13 @@ error: } static const struct nic_operations qla8012_nic_ops = { - .get_flash = ql_get_8012_flash_params, - .port_initialize = ql_8012_port_initialize, + .get_flash = qlge_get_8012_flash_params, + .port_initialize = qlge_8012_port_initialize, }; static const struct nic_operations qla8000_nic_ops = { - .get_flash = ql_get_8000_flash_params, - .port_initialize = ql_8000_port_initialize, + .get_flash = qlge_get_8000_flash_params, + .port_initialize = qlge_8000_port_initialize, }; /* Find the pcie function number for the other NIC @@ -4295,21 +4290,21 @@ static const struct nic_operations qla8000_nic_ops = { * after a fatal firmware error, or doing a firmware * coredump. */ -static int ql_get_alt_pcie_func(struct ql_adapter *qdev) +static int qlge_get_alt_pcie_func(struct qlge_adapter *qdev) { int status = 0; u32 temp; u32 nic_func1, nic_func2; - status = ql_read_mpi_reg(qdev, MPI_TEST_FUNC_PORT_CFG, - &temp); + status = qlge_read_mpi_reg(qdev, MPI_TEST_FUNC_PORT_CFG, + &temp); if (status) return status; nic_func1 = ((temp >> MPI_TEST_NIC1_FUNC_SHIFT) & - MPI_TEST_NIC_FUNC_MASK); + MPI_TEST_NIC_FUNC_MASK); nic_func2 = ((temp >> MPI_TEST_NIC2_FUNC_SHIFT) & - MPI_TEST_NIC_FUNC_MASK); + MPI_TEST_NIC_FUNC_MASK); if (qdev->func == nic_func1) qdev->alt_func = nic_func2; @@ -4321,16 +4316,16 @@ static int ql_get_alt_pcie_func(struct ql_adapter *qdev) return status; } -static int ql_get_board_info(struct ql_adapter *qdev) +static int qlge_get_board_info(struct qlge_adapter *qdev) { int status; qdev->func = - (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT; + (qlge_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT; if (qdev->func > 3) return -EIO; - status = ql_get_alt_pcie_func(qdev); + status = qlge_get_alt_pcie_func(qdev); if (status) return status; @@ -4348,7 +4343,7 @@ static int ql_get_board_info(struct ql_adapter *qdev) qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI; qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO; } - qdev->chip_rev_id = ql_read32(qdev, REV_ID); + qdev->chip_rev_id = qlge_read32(qdev, REV_ID); qdev->device_id = qdev->pdev->device; if (qdev->device_id == QLGE_DEVICE_ID_8012) qdev->nic_ops = &qla8012_nic_ops; @@ -4357,10 +4352,9 @@ static int ql_get_board_info(struct ql_adapter *qdev) return status; } -static void ql_release_all(struct pci_dev *pdev) +static void qlge_release_all(struct pci_dev *pdev) { - struct net_device *ndev = pci_get_drvdata(pdev); - struct ql_adapter *qdev = netdev_priv(ndev); + struct qlge_adapter *qdev = pci_get_drvdata(pdev); if (qdev->workqueue) { destroy_workqueue(qdev->workqueue); @@ -4375,34 +4369,32 @@ static void ql_release_all(struct pci_dev *pdev) pci_release_regions(pdev); } -static int ql_init_device(struct pci_dev *pdev, struct net_device *ndev, - int cards_found) +static int qlge_init_device(struct pci_dev *pdev, struct qlge_adapter *qdev, + int cards_found) { - struct ql_adapter *qdev = netdev_priv(ndev); + struct net_device *ndev = qdev->ndev; int err = 0; - memset((void *)qdev, 0, sizeof(*qdev)); err = pci_enable_device(pdev); if (err) { dev_err(&pdev->dev, "PCI device enable failed.\n"); return err; } - qdev->ndev = ndev; qdev->pdev = pdev; - pci_set_drvdata(pdev, ndev); + pci_set_drvdata(pdev, qdev); /* Set PCIe read request size */ err = pcie_set_readrq(pdev, 4096); if (err) { dev_err(&pdev->dev, "Set readrq failed.\n"); - goto err_out1; + goto err_disable_pci; } err = pci_request_regions(pdev, DRV_NAME); if (err) { dev_err(&pdev->dev, "PCI region request failed.\n"); - return err; + goto err_disable_pci; } pci_set_master(pdev); @@ -4418,7 +4410,7 @@ static int ql_init_device(struct pci_dev *pdev, struct net_device *ndev, if (err) { dev_err(&pdev->dev, "No usable DMA configuration.\n"); - goto err_out2; + goto err_release_pci; } /* Set PCIe reset type for EEH to fundamental. */ @@ -4429,7 +4421,7 @@ static int ql_init_device(struct pci_dev *pdev, struct net_device *ndev, if (!qdev->reg_base) { dev_err(&pdev->dev, "Register mapping failed.\n"); err = -ENOMEM; - goto err_out2; + goto err_release_pci; } qdev->doorbell_area_size = pci_resource_len(pdev, 3); @@ -4438,24 +4430,24 @@ static int ql_init_device(struct pci_dev *pdev, struct net_device *ndev, if (!qdev->doorbell_area) { dev_err(&pdev->dev, "Doorbell register mapping failed.\n"); err = -ENOMEM; - goto err_out2; + goto err_iounmap_base; } - err = ql_get_board_info(qdev); + err = qlge_get_board_info(qdev); if (err) { dev_err(&pdev->dev, "Register access failed.\n"); err = -EIO; - goto err_out2; + goto err_iounmap_doorbell; } qdev->msg_enable = netif_msg_init(debug, default_msg); spin_lock_init(&qdev->stats_lock); if (qlge_mpi_coredump) { qdev->mpi_coredump = - vmalloc(sizeof(struct ql_mpi_coredump)); + vmalloc(sizeof(struct qlge_mpi_coredump)); if (!qdev->mpi_coredump) { err = -ENOMEM; - goto err_out2; + goto err_iounmap_doorbell; } if (qlge_force_coredump) set_bit(QL_FRC_COREDUMP, &qdev->flags); @@ -4464,7 +4456,7 @@ static int ql_init_device(struct pci_dev *pdev, struct net_device *ndev, err = qdev->nic_ops->get_flash(qdev); if (err) { dev_err(&pdev->dev, "Invalid FLASH.\n"); - goto err_out2; + goto err_free_mpi_coredump; } /* Keep local copy of current mac address. */ @@ -4487,15 +4479,14 @@ static int ql_init_device(struct pci_dev *pdev, struct net_device *ndev, ndev->name); if (!qdev->workqueue) { err = -ENOMEM; - goto err_out2; + goto err_free_mpi_coredump; } - INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work); - INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work); - INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work); - INIT_DELAYED_WORK(&qdev->mpi_port_cfg_work, ql_mpi_port_cfg_work); - INIT_DELAYED_WORK(&qdev->mpi_idc_work, ql_mpi_idc_work); - INIT_DELAYED_WORK(&qdev->mpi_core_to_log, ql_mpi_core_to_log); + INIT_DELAYED_WORK(&qdev->asic_reset_work, qlge_asic_reset_work); + INIT_DELAYED_WORK(&qdev->mpi_reset_work, qlge_mpi_reset_work); + INIT_DELAYED_WORK(&qdev->mpi_work, qlge_mpi_work); + INIT_DELAYED_WORK(&qdev->mpi_port_cfg_work, qlge_mpi_port_cfg_work); + INIT_DELAYED_WORK(&qdev->mpi_idc_work, qlge_mpi_idc_work); init_completion(&qdev->ide_completion); mutex_init(&qdev->mpi_mutex); @@ -4505,10 +4496,18 @@ static int ql_init_device(struct pci_dev *pdev, struct net_device *ndev, DRV_NAME, DRV_VERSION); } return 0; -err_out2: - ql_release_all(pdev); -err_out1: + +err_free_mpi_coredump: + vfree(qdev->mpi_coredump); +err_iounmap_doorbell: + iounmap(qdev->doorbell_area); +err_iounmap_base: + iounmap(qdev->reg_base); +err_release_pci: + pci_release_regions(pdev); +err_disable_pci: pci_disable_device(pdev); + return err; } @@ -4527,12 +4526,12 @@ static const struct net_device_ops qlge_netdev_ops = { .ndo_vlan_rx_kill_vid = qlge_vlan_rx_kill_vid, }; -static void ql_timer(struct timer_list *t) +static void qlge_timer(struct timer_list *t) { - struct ql_adapter *qdev = from_timer(qdev, t, timer); + struct qlge_adapter *qdev = from_timer(qdev, t, timer); u32 var = 0; - var = ql_read32(qdev, STS); + var = qlge_read32(qdev, STS); if (pci_channel_offline(qdev->pdev)) { netif_err(qdev, ifup, qdev->ndev, "EEH STS = 0x%.08x.\n", var); return; @@ -4541,36 +4540,47 @@ static void ql_timer(struct timer_list *t) mod_timer(&qdev->timer, jiffies + (5 * HZ)); } +static const struct devlink_ops qlge_devlink_ops; + static int qlge_probe(struct pci_dev *pdev, const struct pci_device_id *pci_entry) { + struct qlge_netdev_priv *ndev_priv; + struct qlge_adapter *qdev = NULL; struct net_device *ndev = NULL; - struct ql_adapter *qdev = NULL; + struct devlink *devlink; static int cards_found; int err = 0; - ndev = alloc_etherdev_mq(sizeof(struct ql_adapter), + devlink = devlink_alloc(&qlge_devlink_ops, sizeof(struct qlge_adapter)); + if (!devlink) + return -ENOMEM; + + qdev = devlink_priv(devlink); + + ndev = alloc_etherdev_mq(sizeof(struct qlge_netdev_priv), min(MAX_CPUS, netif_get_num_default_rss_queues())); if (!ndev) - return -ENOMEM; + goto devlink_free; - err = ql_init_device(pdev, ndev, cards_found); - if (err < 0) { - free_netdev(ndev); - return err; - } + ndev_priv = netdev_priv(ndev); + ndev_priv->qdev = qdev; + ndev_priv->ndev = ndev; + qdev->ndev = ndev; + err = qlge_init_device(pdev, qdev, cards_found); + if (err < 0) + goto netdev_free; - qdev = netdev_priv(ndev); SET_NETDEV_DEV(ndev, &pdev->dev); ndev->hw_features = NETIF_F_SG | - NETIF_F_IP_CSUM | - NETIF_F_TSO | - NETIF_F_TSO_ECN | - NETIF_F_HW_VLAN_CTAG_TX | - NETIF_F_HW_VLAN_CTAG_RX | - NETIF_F_HW_VLAN_CTAG_FILTER | - NETIF_F_RXCSUM; + NETIF_F_IP_CSUM | + NETIF_F_TSO | + NETIF_F_TSO_ECN | + NETIF_F_HW_VLAN_CTAG_TX | + NETIF_F_HW_VLAN_CTAG_RX | + NETIF_F_HW_VLAN_CTAG_FILTER | + NETIF_F_RXCSUM; ndev->features = ndev->hw_features; ndev->vlan_features = ndev->hw_features; /* vlan gets same features (except vlan filter) */ @@ -4601,51 +4611,67 @@ static int qlge_probe(struct pci_dev *pdev, err = register_netdev(ndev); if (err) { dev_err(&pdev->dev, "net device registration failed.\n"); - ql_release_all(pdev); + qlge_release_all(pdev); pci_disable_device(pdev); - free_netdev(ndev); - return err; + goto netdev_free; } + + err = devlink_register(devlink, &pdev->dev); + if (err) + goto netdev_free; + + qlge_health_create_reporters(qdev); /* Start up the timer to trigger EEH if * the bus goes dead */ - timer_setup(&qdev->timer, ql_timer, TIMER_DEFERRABLE); + timer_setup(&qdev->timer, qlge_timer, TIMER_DEFERRABLE); mod_timer(&qdev->timer, jiffies + (5 * HZ)); - ql_link_off(qdev); - ql_display_dev_info(ndev); + qlge_link_off(qdev); + qlge_display_dev_info(ndev); atomic_set(&qdev->lb_count, 0); cards_found++; return 0; + +netdev_free: + free_netdev(ndev); +devlink_free: + devlink_free(devlink); + + return err; } -netdev_tx_t ql_lb_send(struct sk_buff *skb, struct net_device *ndev) +netdev_tx_t qlge_lb_send(struct sk_buff *skb, struct net_device *ndev) { return qlge_send(skb, ndev); } -int ql_clean_lb_rx_ring(struct rx_ring *rx_ring, int budget) +int qlge_clean_lb_rx_ring(struct rx_ring *rx_ring, int budget) { - return ql_clean_inbound_rx_ring(rx_ring, budget); + return qlge_clean_inbound_rx_ring(rx_ring, budget); } static void qlge_remove(struct pci_dev *pdev) { - struct net_device *ndev = pci_get_drvdata(pdev); - struct ql_adapter *qdev = netdev_priv(ndev); + struct qlge_adapter *qdev = pci_get_drvdata(pdev); + struct net_device *ndev = qdev->ndev; + struct devlink *devlink = priv_to_devlink(qdev); del_timer_sync(&qdev->timer); - ql_cancel_all_work_sync(qdev); + qlge_cancel_all_work_sync(qdev); unregister_netdev(ndev); - ql_release_all(pdev); + qlge_release_all(pdev); pci_disable_device(pdev); + devlink_health_reporter_destroy(qdev->reporter); + devlink_unregister(devlink); + devlink_free(devlink); free_netdev(ndev); } /* Clean up resources without touching hardware. */ -static void ql_eeh_close(struct net_device *ndev) +static void qlge_eeh_close(struct net_device *ndev) { + struct qlge_adapter *qdev = netdev_to_qdev(ndev); int i; - struct ql_adapter *qdev = netdev_priv(ndev); if (netif_carrier_ok(ndev)) { netif_carrier_off(ndev); @@ -4653,15 +4679,15 @@ static void ql_eeh_close(struct net_device *ndev) } /* Disabling the timer */ - ql_cancel_all_work_sync(qdev); + qlge_cancel_all_work_sync(qdev); for (i = 0; i < qdev->rss_ring_count; i++) netif_napi_del(&qdev->rx_ring[i].napi); clear_bit(QL_ADAPTER_UP, &qdev->flags); - ql_tx_ring_clean(qdev); - ql_free_rx_buffers(qdev); - ql_release_adapter_resources(qdev); + qlge_tx_ring_clean(qdev); + qlge_free_rx_buffers(qdev); + qlge_release_adapter_resources(qdev); } /* @@ -4671,8 +4697,8 @@ static void ql_eeh_close(struct net_device *ndev) static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state) { - struct net_device *ndev = pci_get_drvdata(pdev); - struct ql_adapter *qdev = netdev_priv(ndev); + struct qlge_adapter *qdev = pci_get_drvdata(pdev); + struct net_device *ndev = qdev->ndev; switch (state) { case pci_channel_io_normal: @@ -4681,14 +4707,14 @@ static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev, netif_device_detach(ndev); del_timer_sync(&qdev->timer); if (netif_running(ndev)) - ql_eeh_close(ndev); + qlge_eeh_close(ndev); pci_disable_device(pdev); return PCI_ERS_RESULT_NEED_RESET; case pci_channel_io_perm_failure: dev_err(&pdev->dev, "%s: pci_channel_io_perm_failure.\n", __func__); del_timer_sync(&qdev->timer); - ql_eeh_close(ndev); + qlge_eeh_close(ndev); set_bit(QL_EEH_FATAL, &qdev->flags); return PCI_ERS_RESULT_DISCONNECT; } @@ -4705,8 +4731,7 @@ static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev, */ static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev) { - struct net_device *ndev = pci_get_drvdata(pdev); - struct ql_adapter *qdev = netdev_priv(ndev); + struct qlge_adapter *qdev = pci_get_drvdata(pdev); pdev->error_state = pci_channel_io_normal; @@ -4718,7 +4743,7 @@ static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev) } pci_set_master(pdev); - if (ql_adapter_reset(qdev)) { + if (qlge_adapter_reset(qdev)) { netif_err(qdev, drv, qdev->ndev, "reset FAILED!\n"); set_bit(QL_EEH_FATAL, &qdev->flags); return PCI_ERS_RESULT_DISCONNECT; @@ -4729,8 +4754,8 @@ static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev) static void qlge_io_resume(struct pci_dev *pdev) { - struct net_device *ndev = pci_get_drvdata(pdev); - struct ql_adapter *qdev = netdev_priv(ndev); + struct qlge_adapter *qdev = pci_get_drvdata(pdev); + struct net_device *ndev = qdev->ndev; int err = 0; if (netif_running(ndev)) { @@ -4756,36 +4781,43 @@ static const struct pci_error_handlers qlge_err_handler = { static int __maybe_unused qlge_suspend(struct device *dev_d) { - struct net_device *ndev = dev_get_drvdata(dev_d); - struct ql_adapter *qdev = netdev_priv(ndev); + struct pci_dev *pdev = to_pci_dev(dev_d); + struct qlge_adapter *qdev; + struct net_device *ndev; int err; + qdev = pci_get_drvdata(pdev); + ndev = qdev->ndev; netif_device_detach(ndev); del_timer_sync(&qdev->timer); if (netif_running(ndev)) { - err = ql_adapter_down(qdev); + err = qlge_adapter_down(qdev); if (!err) return err; } - ql_wol(qdev); + qlge_wol(qdev); return 0; } static int __maybe_unused qlge_resume(struct device *dev_d) { - struct net_device *ndev = dev_get_drvdata(dev_d); - struct ql_adapter *qdev = netdev_priv(ndev); + struct pci_dev *pdev = to_pci_dev(dev_d); + struct qlge_adapter *qdev; + struct net_device *ndev; int err; - pci_set_master(to_pci_dev(dev_d)); + qdev = pci_get_drvdata(pdev); + ndev = qdev->ndev; + + pci_set_master(pdev); device_wakeup_disable(dev_d); if (netif_running(ndev)) { - err = ql_adapter_up(qdev); + err = qlge_adapter_up(qdev); if (err) return err; } |