diff options
Diffstat (limited to 'drivers/staging/rtl8188eu/hal/odm_RegConfig8188E.c')
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/odm_RegConfig8188E.c | 62 |
1 files changed, 34 insertions, 28 deletions
diff --git a/drivers/staging/rtl8188eu/hal/odm_RegConfig8188E.c b/drivers/staging/rtl8188eu/hal/odm_RegConfig8188E.c index 18c0533fbd01..6193d9fafb98 100644 --- a/drivers/staging/rtl8188eu/hal/odm_RegConfig8188E.c +++ b/drivers/staging/rtl8188eu/hal/odm_RegConfig8188E.c @@ -21,25 +21,27 @@ #include "odm_precomp.h" void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, - u32 Data, enum ODM_RF_RADIO_PATH RF_PATH, + u32 Data, enum rf_radio_path RF_PATH, u32 RegAddr) { - if (Addr == 0xffe) { - ODM_sleep_ms(50); + struct adapter *adapter = pDM_Odm->Adapter; + + if (Addr == 0xffe) { + msleep(50); } else if (Addr == 0xfd) { - ODM_delay_ms(5); + mdelay(5); } else if (Addr == 0xfc) { - ODM_delay_ms(1); + mdelay(1); } else if (Addr == 0xfb) { - ODM_delay_us(50); + udelay(50); } else if (Addr == 0xfa) { - ODM_delay_us(5); + udelay(5); } else if (Addr == 0xf9) { - ODM_delay_us(1); + udelay(1); } else { - ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + PHY_SetRFReg(adapter, RF_PATH, RegAddr, bRFRegOffsetMask, Data); /* Add 1us delay between BB/RF register setting. */ - ODM_delay_us(1); + udelay(1); } } @@ -48,7 +50,7 @@ void odm_ConfigRF_RadioA_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Data u32 content = 0x1000; /* RF_Content: radioa_txt */ u32 maskforPhySet = (u32)(content&0xE000); - odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); + odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, RF_PATH_A, Addr|maskforPhySet); ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); } @@ -57,7 +59,7 @@ void odm_ConfigRF_RadioB_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Data u32 content = 0x1001; /* RF_Content: radiob_txt */ u32 maskforPhySet = (u32)(content&0xE000); - odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); + odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, RF_PATH_B, Addr|maskforPhySet); ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); } @@ -70,9 +72,11 @@ void odm_ConfigMAC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u8 Data) void odm_ConfigBB_AGC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data) { - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + struct adapter *adapter = pDM_Odm->Adapter; + + PHY_SetBBReg(adapter, Addr, Bitmask, Data); /* Add 1us delay between BB/RF register setting. */ - ODM_delay_us(1); + udelay(1); ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", @@ -83,17 +87,17 @@ void odm_ConfigBB_PHY_REG_PG_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data) { if (Addr == 0xfe) { - ODM_sleep_ms(50); + msleep(50); } else if (Addr == 0xfd) { - ODM_delay_ms(5); + mdelay(5); } else if (Addr == 0xfc) { - ODM_delay_ms(1); + mdelay(1); } else if (Addr == 0xfb) { - ODM_delay_us(50); + udelay(50); } else if (Addr == 0xfa) { - ODM_delay_us(5); + udelay(5); } else if (Addr == 0xf9) { - ODM_delay_us(1); + udelay(1); } else{ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> @@@@@@@ ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", @@ -104,25 +108,27 @@ void odm_ConfigBB_PHY_REG_PG_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, void odm_ConfigBB_PHY_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data) { + struct adapter *adapter = pDM_Odm->Adapter; + if (Addr == 0xfe) { - ODM_sleep_ms(50); + msleep(50); } else if (Addr == 0xfd) { - ODM_delay_ms(5); + mdelay(5); } else if (Addr == 0xfc) { - ODM_delay_ms(1); + mdelay(1); } else if (Addr == 0xfb) { - ODM_delay_us(50); + udelay(50); } else if (Addr == 0xfa) { - ODM_delay_us(5); + udelay(5); } else if (Addr == 0xf9) { - ODM_delay_us(1); + udelay(1); } else { if (Addr == 0xa24) pDM_Odm->RFCalibrateInfo.RegA24 = Data; - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + PHY_SetBBReg(adapter, Addr, Bitmask, Data); /* Add 1us delay between BB/RF register setting. */ - ODM_delay_us(1); + udelay(1); ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); |