diff options
Diffstat (limited to 'drivers/staging/rtl8188eu')
55 files changed, 3732 insertions, 5629 deletions
diff --git a/drivers/staging/rtl8188eu/Makefile b/drivers/staging/rtl8188eu/Makefile index aeebf9311f15..31ac15961a00 100644 --- a/drivers/staging/rtl8188eu/Makefile +++ b/drivers/staging/rtl8188eu/Makefile @@ -17,25 +17,23 @@ r8188eu-y := \ core/rtw_sta_mgt.o \ core/rtw_wlan_util.o \ core/rtw_xmit.o \ - hal/HalHWImg8188E_MAC.o \ - hal/HalHWImg8188E_BB.o \ - hal/HalHWImg8188E_RF.o \ - hal/HalPhyRf_8188e.o \ - hal/HalPwrSeqCmd.o \ - hal/Hal8188EPwrSeq.o \ + hal/fw.o \ + hal/mac_cfg.o \ + hal/bb_cfg.o \ + hal/rf_cfg.o \ + hal/pwrseqcmd.o \ + hal/pwrseq.o \ hal/Hal8188ERateAdaptive.o\ hal/hal_intf.o \ hal/hal_com.o \ hal/odm.o \ - hal/odm_debug.o \ hal/odm_HWConfig.o \ - hal/odm_RegConfig8188E.o\ hal/odm_RTL8188E.o \ hal/rtl8188e_cmd.o \ hal/rtl8188e_dm.o \ hal/rtl8188e_hal_init.o \ - hal/rtl8188e_phycfg.o \ - hal/rtl8188e_rf6052.o \ + hal/phy.o \ + hal/rf.o \ hal/rtl8188e_rxdesc.o \ hal/rtl8188e_xmit.o \ hal/rtl8188eu_led.o \ diff --git a/drivers/staging/rtl8188eu/core/rtw_cmd.c b/drivers/staging/rtl8188eu/core/rtw_cmd.c index 104b01fa0fad..9935e66935af 100644 --- a/drivers/staging/rtl8188eu/core/rtw_cmd.c +++ b/drivers/staging/rtl8188eu/core/rtw_cmd.c @@ -69,7 +69,7 @@ exit: return _SUCCESS; } -struct cmd_obj * rtw_dequeue_cmd(struct __queue *queue) +struct cmd_obj *rtw_dequeue_cmd(struct __queue *queue) { unsigned long irqL; struct cmd_obj *obj; @@ -98,6 +98,7 @@ static int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) (!pcmdpriv->padapter->registrypriv.usbss_enable)) { if (cmd_obj->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) { struct drvextra_cmd_parm *pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)cmd_obj->parmbuf; + if (pdrvextra_cmd_parm->ec_id == POWER_SAVING_CTRL_WK_CID) bAllow = true; } @@ -296,6 +297,7 @@ u8 rtw_sitesurvey_cmd(struct adapter *padapter, struct ndis_802_11_ssid *ssid, /* prepare ssid list */ if (ssid) { int i; + for (i = 0; i < ssid_num && i < RTW_SSID_SCAN_AMOUNT; i++) { if (ssid[i].SsidLength) { memcpy(&psurveyPara->ssid[i], &ssid[i], sizeof(struct ndis_802_11_ssid)); @@ -307,6 +309,7 @@ u8 rtw_sitesurvey_cmd(struct adapter *padapter, struct ndis_802_11_ssid *ssid, /* prepare channel list */ if (ch) { int i; + for (i = 0; i < ch_num && i < RTW_CHANNEL_SCAN_AMOUNT; i++) { if (ch[i].hw_value && !(ch[i].flags & RTW_IEEE80211_CHAN_DISABLED)) { memcpy(&psurveyPara->ch[i], &ch[i], sizeof(struct rtw_ieee80211_channel)); diff --git a/drivers/staging/rtl8188eu/core/rtw_efuse.c b/drivers/staging/rtl8188eu/core/rtw_efuse.c index 5b997b2b404a..7006088d1ad0 100644 --- a/drivers/staging/rtl8188eu/core/rtw_efuse.c +++ b/drivers/staging/rtl8188eu/core/rtw_efuse.c @@ -440,7 +440,7 @@ u8 Efuse_WordEnableDataWrite(struct adapter *pAdapter, u16 efuse_addr, u8 word_e return badworden; } -u16 Efuse_GetCurrentSize(struct adapter *pAdapter) +static u16 Efuse_GetCurrentSize(struct adapter *pAdapter) { int bContinual = true; u16 efuse_addr = 0; diff --git a/drivers/staging/rtl8188eu/core/rtw_iol.c b/drivers/staging/rtl8188eu/core/rtw_iol.c index 7796287be8f4..cdcf0eacc0e0 100644 --- a/drivers/staging/rtl8188eu/core/rtw_iol.c +++ b/drivers/staging/rtl8188eu/core/rtw_iol.c @@ -20,65 +20,6 @@ #include<rtw_iol.h> -struct xmit_frame *rtw_IOL_accquire_xmit_frame(struct adapter *adapter) -{ - struct xmit_frame *xmit_frame; - struct xmit_buf *xmitbuf; - struct pkt_attrib *pattrib; - struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); - - xmit_frame = rtw_alloc_xmitframe(pxmitpriv); - if (xmit_frame == NULL) { - DBG_88E("%s rtw_alloc_xmitframe return null\n", __func__); - goto exit; - } - - xmitbuf = rtw_alloc_xmitbuf(pxmitpriv); - if (xmitbuf == NULL) { - DBG_88E("%s rtw_alloc_xmitbuf return null\n", __func__); - rtw_free_xmitframe(pxmitpriv, xmit_frame); - xmit_frame = NULL; - goto exit; - } - - xmit_frame->frame_tag = MGNT_FRAMETAG; - xmit_frame->pxmitbuf = xmitbuf; - xmit_frame->buf_addr = xmitbuf->pbuf; - xmitbuf->priv_data = xmit_frame; - - pattrib = &xmit_frame->attrib; - update_mgntframe_attrib(adapter, pattrib); - pattrib->qsel = 0x10;/* Beacon */ - pattrib->subtype = WIFI_BEACON; - pattrib->pktlen = 0; - pattrib->last_txcmdsz = 0; -exit: - return xmit_frame; -} - -int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len) -{ - struct pkt_attrib *pattrib = &xmit_frame->attrib; - u16 buf_offset; - u32 ori_len; - - buf_offset = TXDESC_OFFSET; - ori_len = buf_offset+pattrib->pktlen; - - /* check if the io_buf can accommodate new cmds */ - if (ori_len + cmd_len + 8 > MAX_XMITBUF_SZ) { - DBG_88E("%s %u is large than MAX_XMITBUF_SZ:%u, can't accommodate new cmds\n", - __func__ , ori_len + cmd_len + 8, MAX_XMITBUF_SZ); - return _FAIL; - } - - memcpy(xmit_frame->buf_addr + buf_offset + pattrib->pktlen, IOL_cmds, cmd_len); - pattrib->pktlen += cmd_len; - pattrib->last_txcmdsz += cmd_len; - - return _SUCCESS; -} - bool rtw_IOL_applied(struct adapter *adapter) { if (1 == adapter->registrypriv.fw_iol) @@ -88,108 +29,3 @@ bool rtw_IOL_applied(struct adapter *adapter) return true; return false; } - -int rtw_IOL_exec_cmds_sync(struct adapter *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt) -{ - return rtw_hal_iol_cmd(adapter, xmit_frame, max_wating_ms, bndy_cnt); -} - -int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary) -{ - return _SUCCESS; -} - -int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, u8 mask) -{ - struct ioreg_cfg cmd = {8, IOREG_CMD_WB_REG, 0x0, 0x0, 0x0}; - - cmd.address = cpu_to_le16(addr); - cmd.data = cpu_to_le32(value); - - if (mask != 0xFF) { - cmd.length = 12; - cmd.mask = cpu_to_le32(mask); - } - return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length); -} - -int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, u32 mask) -{ - struct ioreg_cfg cmd = {8, IOREG_CMD_WD_REG, 0x0, 0x0, 0x0}; - - cmd.address = cpu_to_le16(addr); - cmd.data = cpu_to_le32(value); - - if (mask != 0xFFFFFFFF) { - cmd.length = 12; - cmd.mask = cpu_to_le32(mask); - } - return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length); -} - -int _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr, u32 value, u32 mask) -{ - struct ioreg_cfg cmd = {8, IOREG_CMD_W_RF, 0x0, 0x0, 0x0}; - - cmd.address = cpu_to_le16((rf_path<<8) | ((addr) & 0xFF)); - cmd.data = cpu_to_le32(value); - - if (mask != 0x000FFFFF) { - cmd.length = 12; - cmd.mask = cpu_to_le32(mask); - } - return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length); -} - -int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us) -{ - struct ioreg_cfg cmd = {4, IOREG_CMD_DELAY_US, 0x0, 0x0, 0x0}; - cmd.address = cpu_to_le16(us); - - return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 4); -} - -int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms) -{ - struct ioreg_cfg cmd = {4, IOREG_CMD_DELAY_US, 0x0, 0x0, 0x0}; - - cmd.address = cpu_to_le16(ms); - return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 4); -} - -int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame) -{ - struct ioreg_cfg cmd = {4, IOREG_CMD_END, cpu_to_le16(0xFFFF), cpu_to_le32(0xFF), 0x0}; - - return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 4); -} - -u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame) -{ - u8 is_cmd_bndy = false; - if (((pxmit_frame->attrib.pktlen+32)%256) + 8 >= 256) { - rtw_IOL_append_END_cmd(pxmit_frame); - pxmit_frame->attrib.pktlen = ((((pxmit_frame->attrib.pktlen+32)/256)+1)*256); - - pxmit_frame->attrib.last_txcmdsz = pxmit_frame->attrib.pktlen; - is_cmd_bndy = true; - } - return is_cmd_bndy; -} - -void rtw_IOL_cmd_buf_dump(struct adapter *Adapter, int buf_len, u8 *pbuf) -{ - int i; - int j = 1; - - pr_info("###### %s ######\n", __func__); - for (i = 0; i < buf_len; i++) { - printk("%02x-", *(pbuf+i)); - - if (j%32 == 0) - printk("\n"); - j++; - } - printk("\n"); - pr_info("=============ioreg_cmd len=%d===============\n", buf_len); -} diff --git a/drivers/staging/rtl8188eu/hal/HalHWImg8188E_MAC.c b/drivers/staging/rtl8188eu/hal/HalHWImg8188E_MAC.c deleted file mode 100644 index b49b5ab48b18..000000000000 --- a/drivers/staging/rtl8188eu/hal/HalHWImg8188E_MAC.c +++ /dev/null @@ -1,231 +0,0 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -#include "odm_precomp.h" -#include <rtw_iol.h> - -static bool Checkcondition(const u32 condition, const u32 hex) -{ - u32 _board = (hex & 0x000000FF); - u32 _interface = (hex & 0x0000FF00) >> 8; - u32 _platform = (hex & 0x00FF0000) >> 16; - u32 cond = condition; - - if (condition == 0xCDCDCDCD) - return true; - - cond = condition & 0x000000FF; - if ((_board == cond) && cond != 0x00) - return false; - - cond = condition & 0x0000FF00; - cond = cond >> 8; - if ((_interface & cond) == 0 && cond != 0x07) - return false; - - cond = condition & 0x00FF0000; - cond = cond >> 16; - if ((_platform & cond) == 0 && cond != 0x0F) - return false; - return true; -} - - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -static u32 array_MAC_REG_8188E[] = { - 0x026, 0x00000041, - 0x027, 0x00000035, - 0x428, 0x0000000A, - 0x429, 0x00000010, - 0x430, 0x00000000, - 0x431, 0x00000001, - 0x432, 0x00000002, - 0x433, 0x00000004, - 0x434, 0x00000005, - 0x435, 0x00000006, - 0x436, 0x00000007, - 0x437, 0x00000008, - 0x438, 0x00000000, - 0x439, 0x00000000, - 0x43A, 0x00000001, - 0x43B, 0x00000002, - 0x43C, 0x00000004, - 0x43D, 0x00000005, - 0x43E, 0x00000006, - 0x43F, 0x00000007, - 0x440, 0x0000005D, - 0x441, 0x00000001, - 0x442, 0x00000000, - 0x444, 0x00000015, - 0x445, 0x000000F0, - 0x446, 0x0000000F, - 0x447, 0x00000000, - 0x458, 0x00000041, - 0x459, 0x000000A8, - 0x45A, 0x00000072, - 0x45B, 0x000000B9, - 0x460, 0x00000066, - 0x461, 0x00000066, - 0x480, 0x00000008, - 0x4C8, 0x000000FF, - 0x4C9, 0x00000008, - 0x4CC, 0x000000FF, - 0x4CD, 0x000000FF, - 0x4CE, 0x00000001, - 0x4D3, 0x00000001, - 0x500, 0x00000026, - 0x501, 0x000000A2, - 0x502, 0x0000002F, - 0x503, 0x00000000, - 0x504, 0x00000028, - 0x505, 0x000000A3, - 0x506, 0x0000005E, - 0x507, 0x00000000, - 0x508, 0x0000002B, - 0x509, 0x000000A4, - 0x50A, 0x0000005E, - 0x50B, 0x00000000, - 0x50C, 0x0000004F, - 0x50D, 0x000000A4, - 0x50E, 0x00000000, - 0x50F, 0x00000000, - 0x512, 0x0000001C, - 0x514, 0x0000000A, - 0x516, 0x0000000A, - 0x525, 0x0000004F, - 0x550, 0x00000010, - 0x551, 0x00000010, - 0x559, 0x00000002, - 0x55D, 0x000000FF, - 0x605, 0x00000030, - 0x608, 0x0000000E, - 0x609, 0x0000002A, - 0x620, 0x000000FF, - 0x621, 0x000000FF, - 0x622, 0x000000FF, - 0x623, 0x000000FF, - 0x624, 0x000000FF, - 0x625, 0x000000FF, - 0x626, 0x000000FF, - 0x627, 0x000000FF, - 0x652, 0x00000020, - 0x63C, 0x0000000A, - 0x63D, 0x0000000A, - 0x63E, 0x0000000E, - 0x63F, 0x0000000E, - 0x640, 0x00000040, - 0x66E, 0x00000005, - 0x700, 0x00000021, - 0x701, 0x00000043, - 0x702, 0x00000065, - 0x703, 0x00000087, - 0x708, 0x00000021, - 0x709, 0x00000043, - 0x70A, 0x00000065, - 0x70B, 0x00000087, -}; - -enum HAL_STATUS ODM_ReadAndConfig_MAC_REG_8188E(struct odm_dm_struct *dm_odm) -{ - #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = array[i]; v2 = array[i+1]; } while (0) - - u32 hex = 0; - u32 i; - u8 platform = dm_odm->SupportPlatform; - u8 interface_val = dm_odm->SupportInterface; - u8 board = dm_odm->BoardType; - u32 array_len = sizeof(array_MAC_REG_8188E)/sizeof(u32); - u32 *array = array_MAC_REG_8188E; - bool biol = false; - - struct adapter *adapt = dm_odm->Adapter; - struct xmit_frame *pxmit_frame = NULL; - u8 bndy_cnt = 1; - enum HAL_STATUS rst = HAL_STATUS_SUCCESS; - hex += board; - hex += interface_val << 8; - hex += platform << 16; - hex += 0xFF000000; - - biol = rtw_IOL_applied(adapt); - - if (biol) { - pxmit_frame = rtw_IOL_accquire_xmit_frame(adapt); - if (pxmit_frame == NULL) { - pr_info("rtw_IOL_accquire_xmit_frame failed\n"); - return HAL_STATUS_FAILURE; - } - } - - for (i = 0; i < array_len; i += 2) { - u32 v1 = array[i]; - u32 v2 = array[i+1]; - - /* This (offset, data) pair meets the condition. */ - if (v1 < 0xCDCDCDCD) { - if (biol) { - if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) - bndy_cnt++; - rtw_IOL_append_WB_cmd(pxmit_frame, (u16)v1, (u8)v2, 0xFF); - } else { - odm_ConfigMAC_8188E(dm_odm, v1, (u8)v2); - } - continue; - } else { /* This line is the start line of branch. */ - if (!Checkcondition(array[i], hex)) { - /* Discard the following (offset, data) pairs. */ - READ_NEXT_PAIR(v1, v2, i); - while (v2 != 0xDEAD && - v2 != 0xCDEF && - v2 != 0xCDCD && i < array_len - 2) { - READ_NEXT_PAIR(v1, v2, i); - } - i -= 2; /* prevent from for-loop += 2 */ - } else { /* Configure matched pairs and skip to end of if-else. */ - READ_NEXT_PAIR(v1, v2, i); - while (v2 != 0xDEAD && - v2 != 0xCDEF && - v2 != 0xCDCD && i < array_len - 2) { - if (biol) { - if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) - bndy_cnt++; - rtw_IOL_append_WB_cmd(pxmit_frame, (u16)v1, (u8)v2, 0xFF); - } else { - odm_ConfigMAC_8188E(dm_odm, v1, (u8)v2); - } - - READ_NEXT_PAIR(v1, v2, i); - } - while (v2 != 0xDEAD && i < array_len - 2) - READ_NEXT_PAIR(v1, v2, i); - } - } - } - if (biol) { - if (!rtw_IOL_exec_cmds_sync(dm_odm->Adapter, pxmit_frame, 1000, bndy_cnt)) { - pr_info("~~~ MAC IOL_exec_cmds Failed !!!\n"); - rst = HAL_STATUS_FAILURE; - } - } - return rst; -} diff --git a/drivers/staging/rtl8188eu/hal/HalHWImg8188E_RF.c b/drivers/staging/rtl8188eu/hal/HalHWImg8188E_RF.c deleted file mode 100644 index 17c6411ce8ac..000000000000 --- a/drivers/staging/rtl8188eu/hal/HalHWImg8188E_RF.c +++ /dev/null @@ -1,269 +0,0 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -#include "odm_precomp.h" - -#include <rtw_iol.h> - -static bool CheckCondition(const u32 Condition, const u32 Hex) -{ - u32 _board = (Hex & 0x000000FF); - u32 _interface = (Hex & 0x0000FF00) >> 8; - u32 _platform = (Hex & 0x00FF0000) >> 16; - u32 cond = Condition; - - if (Condition == 0xCDCDCDCD) - return true; - - cond = Condition & 0x000000FF; - if ((_board == cond) && cond != 0x00) - return false; - - cond = Condition & 0x0000FF00; - cond = cond >> 8; - if ((_interface & cond) == 0 && cond != 0x07) - return false; - - cond = Condition & 0x00FF0000; - cond = cond >> 16; - if ((_platform & cond) == 0 && cond != 0x0F) - return false; - return true; -} - - -/****************************************************************************** -* RadioA_1T.TXT -******************************************************************************/ - -static u32 Array_RadioA_1T_8188E[] = { - 0x000, 0x00030000, - 0x008, 0x00084000, - 0x018, 0x00000407, - 0x019, 0x00000012, - 0x01E, 0x00080009, - 0x01F, 0x00000880, - 0x02F, 0x0001A060, - 0x03F, 0x00000000, - 0x042, 0x000060C0, - 0x057, 0x000D0000, - 0x058, 0x000BE180, - 0x067, 0x00001552, - 0x083, 0x00000000, - 0x0B0, 0x000FF8FC, - 0x0B1, 0x00054400, - 0x0B2, 0x000CCC19, - 0x0B4, 0x00043003, - 0x0B6, 0x0004953E, - 0x0B7, 0x0001C718, - 0x0B8, 0x000060FF, - 0x0B9, 0x00080001, - 0x0BA, 0x00040000, - 0x0BB, 0x00000400, - 0x0BF, 0x000C0000, - 0x0C2, 0x00002400, - 0x0C3, 0x00000009, - 0x0C4, 0x00040C91, - 0x0C5, 0x00099999, - 0x0C6, 0x000000A3, - 0x0C7, 0x00088820, - 0x0C8, 0x00076C06, - 0x0C9, 0x00000000, - 0x0CA, 0x00080000, - 0x0DF, 0x00000180, - 0x0EF, 0x000001A0, - 0x051, 0x0006B27D, - 0xFF0F041F, 0xABCD, - 0x052, 0x0007E4DD, - 0xCDCDCDCD, 0xCDCD, - 0x052, 0x0007E49D, - 0xFF0F041F, 0xDEAD, - 0x053, 0x00000073, - 0x056, 0x00051FF3, - 0x035, 0x00000086, - 0x035, 0x00000186, - 0x035, 0x00000286, - 0x036, 0x00001C25, - 0x036, 0x00009C25, - 0x036, 0x00011C25, - 0x036, 0x00019C25, - 0x0B6, 0x00048538, - 0x018, 0x00000C07, - 0x05A, 0x0004BD00, - 0x019, 0x000739D0, - 0x034, 0x0000ADF3, - 0x034, 0x00009DF0, - 0x034, 0x00008DED, - 0x034, 0x00007DEA, - 0x034, 0x00006DE7, - 0x034, 0x000054EE, - 0x034, 0x000044EB, - 0x034, 0x000034E8, - 0x034, 0x0000246B, - 0x034, 0x00001468, - 0x034, 0x0000006D, - 0x000, 0x00030159, - 0x084, 0x00068200, - 0x086, 0x000000CE, - 0x087, 0x00048A00, - 0x08E, 0x00065540, - 0x08F, 0x00088000, - 0x0EF, 0x000020A0, - 0x03B, 0x000F02B0, - 0x03B, 0x000EF7B0, - 0x03B, 0x000D4FB0, - 0x03B, 0x000CF060, - 0x03B, 0x000B0090, - 0x03B, 0x000A0080, - 0x03B, 0x00090080, - 0x03B, 0x0008F780, - 0x03B, 0x000722B0, - 0x03B, 0x0006F7B0, - 0x03B, 0x00054FB0, - 0x03B, 0x0004F060, - 0x03B, 0x00030090, - 0x03B, 0x00020080, - 0x03B, 0x00010080, - 0x03B, 0x0000F780, - 0x0EF, 0x000000A0, - 0x000, 0x00010159, - 0x018, 0x0000F407, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0x01F, 0x00080003, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0x01E, 0x00000001, - 0x01F, 0x00080000, - 0x000, 0x00033E60, -}; - -enum HAL_STATUS ODM_ReadAndConfig_RadioA_1T_8188E(struct odm_dm_struct *pDM_Odm) -{ - #define READ_NEXT_PAIR(v1, v2, i) do \ - { i += 2; v1 = Array[i]; \ - v2 = Array[i+1]; } while (0) - - u32 hex = 0; - u32 i = 0; - u8 platform = pDM_Odm->SupportPlatform; - u8 interfaceValue = pDM_Odm->SupportInterface; - u8 board = pDM_Odm->BoardType; - u32 ArrayLen = sizeof(Array_RadioA_1T_8188E)/sizeof(u32); - u32 *Array = Array_RadioA_1T_8188E; - bool biol = false; - struct adapter *Adapter = pDM_Odm->Adapter; - struct xmit_frame *pxmit_frame = NULL; - u8 bndy_cnt = 1; - enum HAL_STATUS rst = HAL_STATUS_SUCCESS; - - hex += board; - hex += interfaceValue << 8; - hex += platform << 16; - hex += 0xFF000000; - biol = rtw_IOL_applied(Adapter); - - if (biol) { - pxmit_frame = rtw_IOL_accquire_xmit_frame(Adapter); - if (pxmit_frame == NULL) { - pr_info("rtw_IOL_accquire_xmit_frame failed\n"); - return HAL_STATUS_FAILURE; - } - } - - for (i = 0; i < ArrayLen; i += 2) { - u32 v1 = Array[i]; - u32 v2 = Array[i+1]; - - /* This (offset, data) pair meets the condition. */ - if (v1 < 0xCDCDCDCD) { - if (biol) { - if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) - bndy_cnt++; - - if (v1 == 0xffe) - rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 50); - else if (v1 == 0xfd) - rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 5); - else if (v1 == 0xfc) - rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 1); - else if (v1 == 0xfb) - rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 50); - else if (v1 == 0xfa) - rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5); - else if (v1 == 0xf9) - rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 1); - else - rtw_IOL_append_WRF_cmd(pxmit_frame, RF_PATH_A, (u16)v1, v2, bRFRegOffsetMask); - } else { - odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2); - } - continue; - } else { /* This line is the start line of branch. */ - if (!CheckCondition(Array[i], hex)) { - /* Discard the following (offset, data) pairs. */ - READ_NEXT_PAIR(v1, v2, i); - while (v2 != 0xDEAD && - v2 != 0xCDEF && - v2 != 0xCDCD && i < ArrayLen - 2) - READ_NEXT_PAIR(v1, v2, i); - i -= 2; /* prevent from for-loop += 2 */ - } else { /* Configure matched pairs and skip to end of if-else. */ - READ_NEXT_PAIR(v1, v2, i); - while (v2 != 0xDEAD && - v2 != 0xCDEF && - v2 != 0xCDCD && i < ArrayLen - 2) { - if (biol) { - if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) - bndy_cnt++; - - if (v1 == 0xffe) - rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 50); - else if (v1 == 0xfd) - rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 5); - else if (v1 == 0xfc) - rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 1); - else if (v1 == 0xfb) - rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 50); - else if (v1 == 0xfa) - rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5); - else if (v1 == 0xf9) - rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 1); - else - rtw_IOL_append_WRF_cmd(pxmit_frame, RF_PATH_A, (u16)v1, v2, bRFRegOffsetMask); - } else { - odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2); - } - READ_NEXT_PAIR(v1, v2, i); - } - - while (v2 != 0xDEAD && i < ArrayLen - 2) - READ_NEXT_PAIR(v1, v2, i); - } - } - } - if (biol) { - if (!rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt)) { - rst = HAL_STATUS_FAILURE; - pr_info("~~~ IOL Config %s Failed !!!\n", __func__); - } - } - return rst; -} diff --git a/drivers/staging/rtl8188eu/hal/HalPhyRf_8188e.c b/drivers/staging/rtl8188eu/hal/HalPhyRf_8188e.c deleted file mode 100644 index d2bcc1640522..000000000000 --- a/drivers/staging/rtl8188eu/hal/HalPhyRf_8188e.c +++ /dev/null @@ -1,1467 +0,0 @@ -/* - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - */ - -#include "odm_precomp.h" - -/* 2010/04/25 MH Define the max tx power tracking tx agc power. */ -#define ODM_TXPWRTRACK_MAX_IDX_88E 6 - - -static u8 ODM_GetRightChnlPlaceforIQK(u8 chnl) -{ - u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = { - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, - 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, - 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, - 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, - 155, 157, 159, 161, 163, 165 - }; - u8 place = chnl; - - if (chnl > 14) { - for (place = 14; place < sizeof(channel_all); place++) { - if (channel_all[place] == chnl) - return place-13; - } - } - return 0; -} - -/* 3 Tx Power Tracking */ -/* - * Function: ODM_TxPwrTrackAdjust88E() - * - * Overview: 88E we can not write 0xc80/c94/c4c/ 0xa2x. Instead of write TX agc. - * No matter OFDM & CCK use the same method. - * - * Revised History: - * When Who Remark - * 04/23/2012 MHC Create Version 0. - * 04/23/2012 MHC Adjust TX agc directly not throughput BB digital. - * - */ -void ODM_TxPwrTrackAdjust88E(struct odm_dm_struct *dm_odm, u8 Type,/* 0 = OFDM, 1 = CCK */ - u8 *pDirection, /* 1 = +(increase) 2 = -(decrease) */ - u32 *pOutWriteVal /* Tx tracking CCK/OFDM BB swing index adjust */ - ) -{ - u8 pwr_value = 0; - /* Tx power tracking BB swing table. */ - /* The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */ - if (Type == 0) { /* For OFDM afjust */ - ODM_RT_TRACE(dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("BbSwingIdxOfdm = %d BbSwingFlagOfdm=%d\n", - dm_odm->BbSwingIdxOfdm, dm_odm->BbSwingFlagOfdm)); - - if (dm_odm->BbSwingIdxOfdm <= dm_odm->BbSwingIdxOfdmBase) { - *pDirection = 1; - pwr_value = (dm_odm->BbSwingIdxOfdmBase - dm_odm->BbSwingIdxOfdm); - } else { - *pDirection = 2; - pwr_value = (dm_odm->BbSwingIdxOfdm - dm_odm->BbSwingIdxOfdmBase); - } - - ODM_RT_TRACE(dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("BbSwingIdxOfdm = %d BbSwingFlagOfdm=%d\n", - dm_odm->BbSwingIdxOfdm, dm_odm->BbSwingFlagOfdm)); - } else if (Type == 1) { /* For CCK adjust. */ - ODM_RT_TRACE(dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("dm_odm->BbSwingIdxCck = %d dm_odm->BbSwingIdxCckBase = %d\n", - dm_odm->BbSwingIdxCck, dm_odm->BbSwingIdxCckBase)); - - if (dm_odm->BbSwingIdxCck <= dm_odm->BbSwingIdxCckBase) { - *pDirection = 1; - pwr_value = (dm_odm->BbSwingIdxCckBase - dm_odm->BbSwingIdxCck); - } else { - *pDirection = 2; - pwr_value = (dm_odm->BbSwingIdxCck - dm_odm->BbSwingIdxCckBase); - } - } - - /* */ - /* 2012/04/25 MH According to Ed/Luke.Lees estimate for EVM the max tx power tracking */ - /* need to be less than 6 power index for 88E. */ - /* */ - if (pwr_value >= ODM_TXPWRTRACK_MAX_IDX_88E && *pDirection == 1) - pwr_value = ODM_TXPWRTRACK_MAX_IDX_88E; - - *pOutWriteVal = pwr_value | (pwr_value<<8) | (pwr_value<<16) | (pwr_value<<24); -} /* ODM_TxPwrTrackAdjust88E */ - -/* - * Function: odm_TxPwrTrackSetPwr88E() - * - * Overview: 88E change all channel tx power accordign to flag. - * OFDM & CCK are all different. - */ -static void odm_TxPwrTrackSetPwr88E(struct odm_dm_struct *dm_odm) -{ - if (dm_odm->BbSwingFlagOfdm || dm_odm->BbSwingFlagCck) { - ODM_RT_TRACE(dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr88E CH=%d\n", *(dm_odm->pChannel))); - PHY_SetTxPowerLevel8188E(dm_odm->Adapter, *(dm_odm->pChannel)); - dm_odm->BbSwingFlagOfdm = false; - dm_odm->BbSwingFlagCck = false; - } -} /* odm_TxPwrTrackSetPwr88E */ - -void -odm_TXPowerTrackingCallback_ThermalMeter_8188E( - struct adapter *Adapter - ) -{ - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - u8 ThermalValue = 0, delta, delta_LCK, delta_IQK, offset; - u8 ThermalValue_AVG_count = 0; - u32 ThermalValue_AVG = 0; - s32 ele_A = 0, ele_D, TempCCk, X, value32; - s32 Y, ele_C = 0; - s8 OFDM_index[2], CCK_index = 0; - s8 OFDM_index_old[2] = {0, 0}, CCK_index_old = 0; - u32 i = 0, j = 0; - bool is2t = false; - - u8 OFDM_min_index = 6, rf; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */ - u8 Indexforchannel = 0/*GetRightChnlPlaceforIQK(pHalData->CurrentChannel)*/; - s8 OFDM_index_mapping[2][index_mapping_NUM_88E] = { - {0, 0, 2, 3, 4, 4, /* 2.4G, decrease power */ - 5, 6, 7, 7, 8, 9, - 10, 10, 11}, /* For lower temperature, 20120220 updated on 20120220. */ - {0, 0, -1, -2, -3, -4, /* 2.4G, increase power */ - -4, -4, -4, -5, -7, -8, - -9, -9, -10}, - }; - u8 Thermal_mapping[2][index_mapping_NUM_88E] = { - {0, 2, 4, 6, 8, 10, /* 2.4G, decrease power */ - 12, 14, 16, 18, 20, 22, - 24, 26, 27}, - {0, 2, 4, 6, 8, 10, /* 2.4G,, increase power */ - 12, 14, 16, 18, 20, 22, - 25, 25, 25}, - }; - struct odm_dm_struct *dm_odm = &pHalData->odmpriv; - - /* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */ - odm_TxPwrTrackSetPwr88E(dm_odm); - - dm_odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++; /* cosa add for debug */ - dm_odm->RFCalibrateInfo.bTXPowerTrackingInit = true; - - /* <Kordan> RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. */ - dm_odm->RFCalibrateInfo.RegA24 = 0x090e1317; - - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("===>dm_TXPowerTrackingCallback_ThermalMeter_8188E txpowercontrol %d\n", - dm_odm->RFCalibrateInfo.TxPowerTrackControl)); - - ThermalValue = (u8)PHY_QueryRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ - - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", - ThermalValue, dm_odm->RFCalibrateInfo.ThermalValue, pHalData->EEPROMThermalMeter)); - - if (is2t) - rf = 2; - else - rf = 1; - - if (ThermalValue) { - /* Query OFDM path A default setting */ - ele_D = PHY_QueryBBReg(Adapter, rOFDM0_XATxIQImbalance, bMaskDWord)&bMaskOFDM_D; - for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { /* find the index */ - if (ele_D == (OFDMSwingTable[i]&bMaskOFDM_D)) { - OFDM_index_old[0] = (u8)i; - dm_odm->BbSwingIdxOfdmBase = (u8)i; - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("Initial pathA ele_D reg0x%x = 0x%x, OFDM_index=0x%x\n", - rOFDM0_XATxIQImbalance, ele_D, OFDM_index_old[0])); - break; - } - } - - /* Query OFDM path B default setting */ - if (is2t) { - ele_D = PHY_QueryBBReg(Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord)&bMaskOFDM_D; - for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { /* find the index */ - if (ele_D == (OFDMSwingTable[i]&bMaskOFDM_D)) { - OFDM_index_old[1] = (u8)i; - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("Initial pathB ele_D reg0x%x = 0x%x, OFDM_index=0x%x\n", - rOFDM0_XBTxIQImbalance, ele_D, OFDM_index_old[1])); - break; - } - } - } - - /* Query CCK default setting From 0xa24 */ - TempCCk = dm_odm->RFCalibrateInfo.RegA24; - - for (i = 0; i < CCK_TABLE_SIZE; i++) { - if (dm_odm->RFCalibrateInfo.bCCKinCH14) { - if (memcmp(&TempCCk, &CCKSwingTable_Ch14[i][2], 4)) { - CCK_index_old = (u8)i; - dm_odm->BbSwingIdxCckBase = (u8)i; - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("Initial reg0x%x = 0x%x, CCK_index=0x%x, ch 14 %d\n", - rCCK0_TxFilter2, TempCCk, CCK_index_old, dm_odm->RFCalibrateInfo.bCCKinCH14)); - break; - } - } else { - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("RegA24: 0x%X, CCKSwingTable_Ch1_Ch13[%d][2]: CCKSwingTable_Ch1_Ch13[i][2]: 0x%X\n", - TempCCk, i, CCKSwingTable_Ch1_Ch13[i][2])); - if (memcmp(&TempCCk, &CCKSwingTable_Ch1_Ch13[i][2], 4)) { - CCK_index_old = (u8)i; - dm_odm->BbSwingIdxCckBase = (u8)i; - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("Initial reg0x%x = 0x%x, CCK_index=0x%x, ch14 %d\n", - rCCK0_TxFilter2, TempCCk, CCK_index_old, dm_odm->RFCalibrateInfo.bCCKinCH14)); - break; - } - } - } - - if (!dm_odm->RFCalibrateInfo.ThermalValue) { - dm_odm->RFCalibrateInfo.ThermalValue = pHalData->EEPROMThermalMeter; - dm_odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; - dm_odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; - - for (i = 0; i < rf; i++) - dm_odm->RFCalibrateInfo.OFDM_index[i] = OFDM_index_old[i]; - dm_odm->RFCalibrateInfo.CCK_index = CCK_index_old; - } - - if (dm_odm->RFCalibrateInfo.bReloadtxpowerindex) - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("reload ofdm index for band switch\n")); - - /* calculate average thermal meter */ - dm_odm->RFCalibrateInfo.ThermalValue_AVG[dm_odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue; - dm_odm->RFCalibrateInfo.ThermalValue_AVG_index++; - if (dm_odm->RFCalibrateInfo.ThermalValue_AVG_index == AVG_THERMAL_NUM_88E) - dm_odm->RFCalibrateInfo.ThermalValue_AVG_index = 0; - - for (i = 0; i < AVG_THERMAL_NUM_88E; i++) { - if (dm_odm->RFCalibrateInfo.ThermalValue_AVG[i]) { - ThermalValue_AVG += dm_odm->RFCalibrateInfo.ThermalValue_AVG[i]; - ThermalValue_AVG_count++; - } - } - - if (ThermalValue_AVG_count) { - ThermalValue = (u8)(ThermalValue_AVG / ThermalValue_AVG_count); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("AVG Thermal Meter = 0x%x\n", ThermalValue)); - } - - if (dm_odm->RFCalibrateInfo.bReloadtxpowerindex) { - delta = ThermalValue > pHalData->EEPROMThermalMeter ? - (ThermalValue - pHalData->EEPROMThermalMeter) : - (pHalData->EEPROMThermalMeter - ThermalValue); - dm_odm->RFCalibrateInfo.bReloadtxpowerindex = false; - dm_odm->RFCalibrateInfo.bDoneTxpower = false; - } else if (dm_odm->RFCalibrateInfo.bDoneTxpower) { - delta = (ThermalValue > dm_odm->RFCalibrateInfo.ThermalValue) ? - (ThermalValue - dm_odm->RFCalibrateInfo.ThermalValue) : - (dm_odm->RFCalibrateInfo.ThermalValue - ThermalValue); - } else { - delta = ThermalValue > pHalData->EEPROMThermalMeter ? - (ThermalValue - pHalData->EEPROMThermalMeter) : - (pHalData->EEPROMThermalMeter - ThermalValue); - } - delta_LCK = (ThermalValue > dm_odm->RFCalibrateInfo.ThermalValue_LCK) ? - (ThermalValue - dm_odm->RFCalibrateInfo.ThermalValue_LCK) : - (dm_odm->RFCalibrateInfo.ThermalValue_LCK - ThermalValue); - delta_IQK = (ThermalValue > dm_odm->RFCalibrateInfo.ThermalValue_IQK) ? - (ThermalValue - dm_odm->RFCalibrateInfo.ThermalValue_IQK) : - (dm_odm->RFCalibrateInfo.ThermalValue_IQK - ThermalValue); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x delta 0x%x delta_LCK 0x%x delta_IQK 0x%x\n", - ThermalValue, dm_odm->RFCalibrateInfo.ThermalValue, - pHalData->EEPROMThermalMeter, delta, delta_LCK, delta_IQK)); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("pre thermal meter LCK 0x%x pre thermal meter IQK 0x%x delta_LCK_bound 0x%x delta_IQK_bound 0x%x\n", - dm_odm->RFCalibrateInfo.ThermalValue_LCK, - dm_odm->RFCalibrateInfo.ThermalValue_IQK, - dm_odm->RFCalibrateInfo.Delta_LCK, - dm_odm->RFCalibrateInfo.Delta_IQK)); - - if ((delta_LCK >= 8)) { /* Delta temperature is equal to or larger than 20 centigrade. */ - dm_odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; - PHY_LCCalibrate_8188E(Adapter); - } - - if (delta > 0 && dm_odm->RFCalibrateInfo.TxPowerTrackControl) { - delta = ThermalValue > pHalData->EEPROMThermalMeter ? - (ThermalValue - pHalData->EEPROMThermalMeter) : - (pHalData->EEPROMThermalMeter - ThermalValue); - /* calculate new OFDM / CCK offset */ - if (ThermalValue > pHalData->EEPROMThermalMeter) - j = 1; - else - j = 0; - for (offset = 0; offset < index_mapping_NUM_88E; offset++) { - if (delta < Thermal_mapping[j][offset]) { - if (offset != 0) - offset--; - break; - } - } - if (offset >= index_mapping_NUM_88E) - offset = index_mapping_NUM_88E-1; - for (i = 0; i < rf; i++) - OFDM_index[i] = dm_odm->RFCalibrateInfo.OFDM_index[i] + OFDM_index_mapping[j][offset]; - CCK_index = dm_odm->RFCalibrateInfo.CCK_index + OFDM_index_mapping[j][offset]; - - if (is2t) { - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, CCK_index=0x%x\n", - dm_odm->RFCalibrateInfo.OFDM_index[0], - dm_odm->RFCalibrateInfo.OFDM_index[1], - dm_odm->RFCalibrateInfo.CCK_index)); - } else { - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("temp OFDM_A_index=0x%x, CCK_index=0x%x\n", - dm_odm->RFCalibrateInfo.OFDM_index[0], - dm_odm->RFCalibrateInfo.CCK_index)); - } - - for (i = 0; i < rf; i++) { - if (OFDM_index[i] > OFDM_TABLE_SIZE_92D-1) - OFDM_index[i] = OFDM_TABLE_SIZE_92D-1; - else if (OFDM_index[i] < OFDM_min_index) - OFDM_index[i] = OFDM_min_index; - } - - if (CCK_index > CCK_TABLE_SIZE-1) - CCK_index = CCK_TABLE_SIZE-1; - else if (CCK_index < 0) - CCK_index = 0; - - if (is2t) { - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("new OFDM_A_index=0x%x, OFDM_B_index=0x%x, CCK_index=0x%x\n", - OFDM_index[0], OFDM_index[1], CCK_index)); - } else { - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("new OFDM_A_index=0x%x, CCK_index=0x%x\n", - OFDM_index[0], CCK_index)); - } - - /* 2 temporarily remove bNOPG */ - /* Config by SwingTable */ - if (dm_odm->RFCalibrateInfo.TxPowerTrackControl) { - dm_odm->RFCalibrateInfo.bDoneTxpower = true; - - /* Adujst OFDM Ant_A according to IQK result */ - ele_D = (OFDMSwingTable[(u8)OFDM_index[0]] & 0xFFC00000)>>22; - X = dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][0]; - Y = dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][1]; - - /* Revse TX power table. */ - dm_odm->BbSwingIdxOfdm = (u8)OFDM_index[0]; - dm_odm->BbSwingIdxCck = (u8)CCK_index; - - if (dm_odm->BbSwingIdxOfdmCurrent != dm_odm->BbSwingIdxOfdm) { - dm_odm->BbSwingIdxOfdmCurrent = dm_odm->BbSwingIdxOfdm; - dm_odm->BbSwingFlagOfdm = true; - } - - if (dm_odm->BbSwingIdxCckCurrent != dm_odm->BbSwingIdxCck) { - dm_odm->BbSwingIdxCckCurrent = dm_odm->BbSwingIdxCck; - dm_odm->BbSwingFlagCck = true; - } - - if (X != 0) { - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - ele_A = ((X * ele_D)>>8)&0x000003FF; - - /* new element C = element D x Y */ - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - ele_C = ((Y * ele_D)>>8)&0x000003FF; - - /* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */ - /* to increase TX power. Otherwise, EVM will be bad. */ - } - - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("TxPwrTracking for path A: X=0x%x, Y=0x%x ele_A=0x%x ele_C=0x%x ele_D=0x%x 0xe94=0x%x 0xe9c=0x%x\n", - (u32)X, (u32)Y, (u32)ele_A, (u32)ele_C, (u32)ele_D, (u32)X, (u32)Y)); - - if (is2t) { - ele_D = (OFDMSwingTable[(u8)OFDM_index[1]] & 0xFFC00000)>>22; - - /* new element A = element D x X */ - X = dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][4]; - Y = dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][5]; - - if ((X != 0) && (*(dm_odm->pBandType) == ODM_BAND_2_4G)) { - if ((X & 0x00000200) != 0) /* consider minus */ - X = X | 0xFFFFFC00; - ele_A = ((X * ele_D)>>8)&0x000003FF; - - /* new element C = element D x Y */ - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - ele_C = ((Y * ele_D)>>8)&0x00003FF; - - /* wtite new elements A, C, D to regC88 and regC9C, element B is always 0 */ - value32 = (ele_D<<22) | ((ele_C&0x3F)<<16) | ele_A; - PHY_SetBBReg(Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C&0x000003C0)>>6; - PHY_SetBBReg(Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, value32); - - value32 = ((X * ele_D)>>7)&0x01; - PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT28, value32); - } else { - PHY_SetBBReg(Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable[(u8)OFDM_index[1]]); - PHY_SetBBReg(Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); - PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT28, 0x00); - } - - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("TxPwrTracking path B: X=0x%x, Y=0x%x ele_A=0x%x ele_C=0x%x ele_D=0x%x 0xeb4=0x%x 0xebc=0x%x\n", - (u32)X, (u32)Y, (u32)ele_A, - (u32)ele_C, (u32)ele_D, (u32)X, (u32)Y)); - } - - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n", - PHY_QueryBBReg(Adapter, 0xc80, bMaskDWord), PHY_QueryBBReg(Adapter, - 0xc94, bMaskDWord), PHY_QueryRFReg(Adapter, RF_PATH_A, 0x24, bRFRegOffsetMask))); - } - } - - if (delta_IQK >= 8) { /* Delta temperature is equal to or larger than 20 centigrade. */ - dm_odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; - PHY_IQCalibrate_8188E(Adapter, false); - } - /* update thermal meter value */ - if (dm_odm->RFCalibrateInfo.TxPowerTrackControl) - dm_odm->RFCalibrateInfo.ThermalValue = ThermalValue; - } - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n")); - dm_odm->RFCalibrateInfo.TXPowercount = 0; -} - -/* 1 7. IQK */ -#define MAX_TOLERANCE 5 - -static u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ -phy_PathA_IQK_8188E(struct adapter *adapt, bool configPathB) -{ - u32 regeac, regE94, regE9C, regEA4; - u8 result = 0x00; - struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt); - struct odm_dm_struct *dm_odm = &pHalData->odmpriv; - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); - - /* 1 Tx IQK */ - /* path-A IQK setting */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); - PHY_SetBBReg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); - PHY_SetBBReg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); - PHY_SetBBReg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x8214032a); - PHY_SetBBReg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160000); - - /* LO calibration setting */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - PHY_SetBBReg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); - - /* One shot, path A LOK & IQK */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - /* delay x ms */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); - /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */ - mdelay(IQK_DELAY_TIME_88E); - - /* Check failed */ - regeac = PHY_QueryBBReg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regeac)); - regE94 = PHY_QueryBBReg(adapt, rTx_Power_Before_IQK_A, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); - regE9C = PHY_QueryBBReg(adapt, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); - regEA4 = PHY_QueryBBReg(adapt, rRx_Power_Before_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); - - if (!(regeac & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42)) - result |= 0x01; - return result; -} - -static u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ -phy_PathA_RxIQK(struct adapter *adapt, bool configPathB) -{ - u32 regeac, regE94, regE9C, regEA4, u4tmp; - u8 result = 0x00; - struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt); - struct odm_dm_struct *dm_odm = &pHalData->odmpriv; - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); - - /* 1 Get TXIMR setting */ - /* modify RXIQK mode table */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); - PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000); - PHY_SetRFReg(adapt, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - PHY_SetRFReg(adapt, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - PHY_SetRFReg(adapt, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - PHY_SetRFReg(adapt, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B); - - /* PA,PAD off */ - PHY_SetRFReg(adapt, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980); - PHY_SetRFReg(adapt, RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000); - - PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000); - - /* IQK setting */ - PHY_SetBBReg(adapt, rTx_IQK, bMaskDWord, 0x01007c00); - PHY_SetBBReg(adapt, rRx_IQK, bMaskDWord, 0x81004800); - - /* path-A IQK setting */ - PHY_SetBBReg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); - PHY_SetBBReg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); - PHY_SetBBReg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); - PHY_SetBBReg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160000); - - /* LO calibration setting */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - PHY_SetBBReg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - /* One shot, path A LOK & IQK */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - /* delay x ms */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("Delay %d ms for One shot, path A LOK & IQK.\n", - IQK_DELAY_TIME_88E)); - mdelay(IQK_DELAY_TIME_88E); - - /* Check failed */ - regeac = PHY_QueryBBReg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("0xeac = 0x%x\n", regeac)); - regE94 = PHY_QueryBBReg(adapt, rTx_Power_Before_IQK_A, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("0xe94 = 0x%x\n", regE94)); - regE9C = PHY_QueryBBReg(adapt, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("0xe9c = 0x%x\n", regE9C)); - - if (!(regeac & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42)) - result |= 0x01; - else /* if Tx not OK, ignore Rx */ - return result; - - u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); - PHY_SetBBReg(adapt, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", PHY_QueryBBReg(adapt, rTx_IQK, bMaskDWord), u4tmp)); - - /* 1 RX IQK */ - /* modify RXIQK mode table */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); - PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000); - PHY_SetRFReg(adapt, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - PHY_SetRFReg(adapt, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - PHY_SetRFReg(adapt, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - PHY_SetRFReg(adapt, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa); - PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000); - - /* IQK setting */ - PHY_SetBBReg(adapt, rRx_IQK, bMaskDWord, 0x01004800); - - /* path-A IQK setting */ - PHY_SetBBReg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - PHY_SetBBReg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - PHY_SetBBReg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x82160c05); - PHY_SetBBReg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160c1f); - - /* LO calibration setting */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - PHY_SetBBReg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - /* One shot, path A LOK & IQK */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - /* delay x ms */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); - /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */ - mdelay(IQK_DELAY_TIME_88E); - - /* Check failed */ - regeac = PHY_QueryBBReg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regeac)); - regE94 = PHY_QueryBBReg(adapt, rTx_Power_Before_IQK_A, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); - regE9C = PHY_QueryBBReg(adapt, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); - regEA4 = PHY_QueryBBReg(adapt, rRx_Power_Before_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); - - /* reload RF 0xdf */ - PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000); - PHY_SetRFReg(adapt, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); - - if (!(regeac & BIT27) && /* if Tx is OK, check whether Rx is OK */ - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regeac & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); - - return result; -} - -static u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ -phy_PathB_IQK_8188E(struct adapter *adapt) -{ - u32 regeac, regeb4, regebc, regec4, regecc; - u8 result = 0x00; - struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt); - struct odm_dm_struct *dm_odm = &pHalData->odmpriv; - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); - - /* One shot, path B LOK & IQK */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - PHY_SetBBReg(adapt, rIQK_AGC_Cont, bMaskDWord, 0x00000002); - PHY_SetBBReg(adapt, rIQK_AGC_Cont, bMaskDWord, 0x00000000); - - /* delay x ms */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("Delay %d ms for One shot, path B LOK & IQK.\n", - IQK_DELAY_TIME_88E)); - mdelay(IQK_DELAY_TIME_88E); - - /* Check failed */ - regeac = PHY_QueryBBReg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("0xeac = 0x%x\n", regeac)); - regeb4 = PHY_QueryBBReg(adapt, rTx_Power_Before_IQK_B, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("0xeb4 = 0x%x\n", regeb4)); - regebc = PHY_QueryBBReg(adapt, rTx_Power_After_IQK_B, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("0xebc = 0x%x\n", regebc)); - regec4 = PHY_QueryBBReg(adapt, rRx_Power_Before_IQK_B_2, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("0xec4 = 0x%x\n", regec4)); - regecc = PHY_QueryBBReg(adapt, rRx_Power_After_IQK_B_2, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("0xecc = 0x%x\n", regecc)); - - if (!(regeac & BIT31) && - (((regeb4 & 0x03FF0000)>>16) != 0x142) && - (((regebc & 0x03FF0000)>>16) != 0x42)) - result |= 0x01; - else - return result; - - if (!(regeac & BIT30) && - (((regec4 & 0x03FF0000)>>16) != 0x132) && - (((regecc & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); - return result; -} - -static void patha_fill_iqk(struct adapter *adapt, bool iqkok, s32 result[][8], u8 final_candidate, bool txonly) -{ - u32 Oldval_0, X, TX0_A, reg; - s32 Y, TX0_C; - struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt); - struct odm_dm_struct *dm_odm = &pHalData->odmpriv; - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("Path A IQ Calibration %s !\n", - (iqkok) ? "Success" : "Failed")); - - if (final_candidate == 0xFF) { - return; - } else if (iqkok) { - Oldval_0 = (PHY_QueryBBReg(adapt, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][0]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX0_A = (X * Oldval_0) >> 8; - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", - X, TX0_A, Oldval_0)); - PHY_SetBBReg(adapt, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); - - PHY_SetBBReg(adapt, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0>>7) & 0x1)); - - Y = result[final_candidate][1]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - TX0_C = (Y * Oldval_0) >> 8; - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); - PHY_SetBBReg(adapt, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); - PHY_SetBBReg(adapt, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); - - PHY_SetBBReg(adapt, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0>>7) & 0x1)); - - if (txonly) { - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("patha_fill_iqk only Tx OK\n")); - return; - } - - reg = result[final_candidate][2]; - PHY_SetBBReg(adapt, rOFDM0_XARxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][3] & 0x3F; - PHY_SetBBReg(adapt, rOFDM0_XARxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][3] >> 6) & 0xF; - PHY_SetBBReg(adapt, rOFDM0_RxIQExtAnta, 0xF0000000, reg); - } -} - -static void pathb_fill_iqk(struct adapter *adapt, bool iqkok, s32 result[][8], u8 final_candidate, bool txonly) -{ - u32 Oldval_1, X, TX1_A, reg; - s32 Y, TX1_C; - struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt); - struct odm_dm_struct *dm_odm = &pHalData->odmpriv; - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("Path B IQ Calibration %s !\n", - (iqkok) ? "Success" : "Failed")); - - if (final_candidate == 0xFF) { - return; - } else if (iqkok) { - Oldval_1 = (PHY_QueryBBReg(adapt, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][4]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX1_A = (X * Oldval_1) >> 8; - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); - PHY_SetBBReg(adapt, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); - - PHY_SetBBReg(adapt, rOFDM0_ECCAThreshold, BIT(27), ((X * Oldval_1>>7) & 0x1)); - - Y = result[final_candidate][5]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - TX1_C = (Y * Oldval_1) >> 8; - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); - PHY_SetBBReg(adapt, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); - PHY_SetBBReg(adapt, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); - - PHY_SetBBReg(adapt, rOFDM0_ECCAThreshold, BIT(25), ((Y * Oldval_1>>7) & 0x1)); - - if (txonly) - return; - - reg = result[final_candidate][6]; - PHY_SetBBReg(adapt, rOFDM0_XBRxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][7] & 0x3F; - PHY_SetBBReg(adapt, rOFDM0_XBRxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][7] >> 6) & 0xF; - PHY_SetBBReg(adapt, rOFDM0_AGCRSSITable, 0x0000F000, reg); - } -} - -void _PHY_SaveADDARegisters(struct adapter *adapt, u32 *ADDAReg, u32 *ADDABackup, u32 RegisterNum) -{ - u32 i; - struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt); - struct odm_dm_struct *dm_odm = &pHalData->odmpriv; - - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); - for (i = 0; i < RegisterNum; i++) { - ADDABackup[i] = PHY_QueryBBReg(adapt, ADDAReg[i], bMaskDWord); - } -} - -static void _PHY_SaveMACRegisters( - struct adapter *adapt, - u32 *MACReg, - u32 *MACBackup - ) -{ - u32 i; - struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt); - struct odm_dm_struct *dm_odm = &pHalData->odmpriv; - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); - for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) { - MACBackup[i] = usb_read8(adapt, MACReg[i]); - } - MACBackup[i] = usb_read32(adapt, MACReg[i]); -} - -static void reload_adda_reg(struct adapter *adapt, u32 *ADDAReg, u32 *ADDABackup, u32 RegiesterNum) -{ - u32 i; - struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt); - struct odm_dm_struct *dm_odm = &pHalData->odmpriv; - - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); - for (i = 0; i < RegiesterNum; i++) - PHY_SetBBReg(adapt, ADDAReg[i], bMaskDWord, ADDABackup[i]); -} - -static void -_PHY_ReloadMACRegisters( - struct adapter *adapt, - u32 *MACReg, - u32 *MACBackup - ) -{ - u32 i; - struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt); - struct odm_dm_struct *dm_odm = &pHalData->odmpriv; - - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); - for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) { - usb_write8(adapt, MACReg[i], (u8)MACBackup[i]); - } - usb_write32(adapt, MACReg[i], MACBackup[i]); -} - -void -_PHY_PathADDAOn( - struct adapter *adapt, - u32 *ADDAReg, - bool isPathAOn, - bool is2t - ) -{ - u32 pathOn; - u32 i; - struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt); - struct odm_dm_struct *dm_odm = &pHalData->odmpriv; - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); - - pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4; - if (!is2t) { - pathOn = 0x0bdb25a0; - PHY_SetBBReg(adapt, ADDAReg[0], bMaskDWord, 0x0b1b25a0); - } else { - PHY_SetBBReg(adapt, ADDAReg[0], bMaskDWord, pathOn); - } - - for (i = 1; i < IQK_ADDA_REG_NUM; i++) - PHY_SetBBReg(adapt, ADDAReg[i], bMaskDWord, pathOn); -} - -void -_PHY_MACSettingCalibration( - struct adapter *adapt, - u32 *MACReg, - u32 *MACBackup - ) -{ - u32 i = 0; - struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt); - struct odm_dm_struct *dm_odm = &pHalData->odmpriv; - - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); - - usb_write8(adapt, MACReg[i], 0x3F); - - for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) { - usb_write8(adapt, MACReg[i], (u8)(MACBackup[i]&(~BIT3))); - } - usb_write8(adapt, MACReg[i], (u8)(MACBackup[i]&(~BIT5))); -} - -void -_PHY_PathAStandBy( - struct adapter *adapt - ) -{ - struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt); - struct odm_dm_struct *dm_odm = &pHalData->odmpriv; - - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); - - PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x0); - PHY_SetBBReg(adapt, 0x840, bMaskDWord, 0x00010000); - PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000); -} - -static void _PHY_PIModeSwitch( - struct adapter *adapt, - bool PIMode - ) -{ - u32 mode; - struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt); - struct odm_dm_struct *dm_odm = &pHalData->odmpriv; - - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); - - mode = PIMode ? 0x01000100 : 0x01000000; - PHY_SetBBReg(adapt, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); - PHY_SetBBReg(adapt, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); -} - -static bool phy_SimularityCompare_8188E( - struct adapter *adapt, - s32 resulta[][8], - u8 c1, - u8 c2 - ) -{ - u32 i, j, diff, sim_bitmap, bound = 0; - struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt); - struct odm_dm_struct *dm_odm = &pHalData->odmpriv; - u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */ - bool result = true; - bool is2t; - s32 tmp1 = 0, tmp2 = 0; - - if ((dm_odm->RFType == ODM_2T2R) || (dm_odm->RFType == ODM_2T3R) || (dm_odm->RFType == ODM_2T4R)) - is2t = true; - else - is2t = false; - - if (is2t) - bound = 8; - else - bound = 4; - - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8188E c1 %d c2 %d!!!\n", c1, c2)); - - sim_bitmap = 0; - - for (i = 0; i < bound; i++) { - if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { - if ((resulta[c1][i] & 0x00000200) != 0) - tmp1 = resulta[c1][i] | 0xFFFFFC00; - else - tmp1 = resulta[c1][i]; - - if ((resulta[c2][i] & 0x00000200) != 0) - tmp2 = resulta[c2][i] | 0xFFFFFC00; - else - tmp2 = resulta[c2][i]; - } else { - tmp1 = resulta[c1][i]; - tmp2 = resulta[c2][i]; - } - - diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); - - if (diff > MAX_TOLERANCE) { - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("IQK:phy_SimularityCompare_8188E differnece overflow index %d compare1 0x%x compare2 0x%x!!!\n", - i, resulta[c1][i], resulta[c2][i])); - - if ((i == 2 || i == 6) && !sim_bitmap) { - if (resulta[c1][i] + resulta[c1][i+1] == 0) - final_candidate[(i/4)] = c2; - else if (resulta[c2][i] + resulta[c2][i+1] == 0) - final_candidate[(i/4)] = c1; - else - sim_bitmap = sim_bitmap | (1<<i); - } else { - sim_bitmap = sim_bitmap | (1<<i); - } - } - } - - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8188E sim_bitmap %d !!!\n", sim_bitmap)); - - if (sim_bitmap == 0) { - for (i = 0; i < (bound/4); i++) { - if (final_candidate[i] != 0xFF) { - for (j = i*4; j < (i+1)*4-2; j++) - resulta[3][j] = resulta[final_candidate[i]][j]; - result = false; - } - } - return result; - } else { - if (!(sim_bitmap & 0x03)) { /* path A TX OK */ - for (i = 0; i < 2; i++) - resulta[3][i] = resulta[c1][i]; - } - if (!(sim_bitmap & 0x0c)) { /* path A RX OK */ - for (i = 2; i < 4; i++) - resulta[3][i] = resulta[c1][i]; - } - - if (!(sim_bitmap & 0x30)) { /* path B TX OK */ - for (i = 4; i < 6; i++) - resulta[3][i] = resulta[c1][i]; - } - - if (!(sim_bitmap & 0xc0)) { /* path B RX OK */ - for (i = 6; i < 8; i++) - resulta[3][i] = resulta[c1][i]; - } - return false; - } -} - -static void phy_IQCalibrate_8188E(struct adapter *adapt, s32 result[][8], u8 t, bool is2t) -{ - struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt); - struct odm_dm_struct *dm_odm = &pHalData->odmpriv; - u32 i; - u8 PathAOK, PathBOK; - u32 ADDA_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - u32 IQK_MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - /* since 92C & 92D have the different define in IQK_BB_REG */ - u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD - }; - - u32 retryCount = 9; - if (*(dm_odm->mp_mode) == 1) - retryCount = 9; - else - retryCount = 2; - /* Note: IQ calibration must be performed after loading */ - /* PHY_REG.txt , and radio_a, radio_b.txt */ - - if (t == 0) { - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2t ? "2T2R" : "1T1R"), t)); - - /* Save ADDA parameters, turn Path A ADDA on */ - _PHY_SaveADDARegisters(adapt, ADDA_REG, dm_odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters(adapt, IQK_MAC_REG, dm_odm->RFCalibrateInfo.IQK_MAC_backup); - _PHY_SaveADDARegisters(adapt, IQK_BB_REG_92C, dm_odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); - } - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2t ? "2T2R" : "1T1R"), t)); - - _PHY_PathADDAOn(adapt, ADDA_REG, true, is2t); - if (t == 0) - dm_odm->RFCalibrateInfo.bRfPiEnable = (u8)PHY_QueryBBReg(adapt, rFPGA0_XA_HSSIParameter1, BIT(8)); - - if (!dm_odm->RFCalibrateInfo.bRfPiEnable) { - /* Switch BB to PI mode to do IQ Calibration. */ - _PHY_PIModeSwitch(adapt, true); - } - - /* BB setting */ - PHY_SetBBReg(adapt, rFPGA0_RFMOD, BIT24, 0x00); - PHY_SetBBReg(adapt, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); - PHY_SetBBReg(adapt, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); - PHY_SetBBReg(adapt, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); - - PHY_SetBBReg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); - PHY_SetBBReg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); - PHY_SetBBReg(adapt, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); - PHY_SetBBReg(adapt, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); - - if (is2t) { - PHY_SetBBReg(adapt, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000); - PHY_SetBBReg(adapt, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000); - } - - /* MAC settings */ - _PHY_MACSettingCalibration(adapt, IQK_MAC_REG, dm_odm->RFCalibrateInfo.IQK_MAC_backup); - - /* Page B init */ - /* AP or IQK */ - PHY_SetBBReg(adapt, rConfig_AntA, bMaskDWord, 0x0f600000); - - if (is2t) - PHY_SetBBReg(adapt, rConfig_AntB, bMaskDWord, 0x0f600000); - - /* IQ calibration setting */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n")); - PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000); - PHY_SetBBReg(adapt, rTx_IQK, bMaskDWord, 0x01007c00); - PHY_SetBBReg(adapt, rRx_IQK, bMaskDWord, 0x81004800); - - for (i = 0; i < retryCount; i++) { - PathAOK = phy_PathA_IQK_8188E(adapt, is2t); - if (PathAOK == 0x01) { - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n")); - result[t][0] = (PHY_QueryBBReg(adapt, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (PHY_QueryBBReg(adapt, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - break; - } - } - - for (i = 0; i < retryCount; i++) { - PathAOK = phy_PathA_RxIQK(adapt, is2t); - if (PathAOK == 0x03) { - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); - result[t][2] = (PHY_QueryBBReg(adapt, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - result[t][3] = (PHY_QueryBBReg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - break; - } else { - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n")); - } - } - - if (0x00 == PathAOK) { - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); - } - - if (is2t) { - _PHY_PathAStandBy(adapt); - - /* Turn Path B ADDA on */ - _PHY_PathADDAOn(adapt, ADDA_REG, false, is2t); - - for (i = 0; i < retryCount; i++) { - PathBOK = phy_PathB_IQK_8188E(adapt); - if (PathBOK == 0x03) { - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK Success!!\n")); - result[t][4] = (PHY_QueryBBReg(adapt, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; - result[t][5] = (PHY_QueryBBReg(adapt, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; - result[t][6] = (PHY_QueryBBReg(adapt, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; - result[t][7] = (PHY_QueryBBReg(adapt, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; - break; - } else if (i == (retryCount - 1) && PathBOK == 0x01) { /* Tx IQK OK */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Only Tx IQK Success!!\n")); - result[t][4] = (PHY_QueryBBReg(adapt, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; - result[t][5] = (PHY_QueryBBReg(adapt, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; - } - } - - if (0x00 == PathBOK) { - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); - } - } - - /* Back to BB mode, load original value */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); - PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0); - - if (t != 0) { - if (!dm_odm->RFCalibrateInfo.bRfPiEnable) { - /* Switch back BB to SI mode after finish IQ Calibration. */ - _PHY_PIModeSwitch(adapt, false); - } - - /* Reload ADDA power saving parameters */ - reload_adda_reg(adapt, ADDA_REG, dm_odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - - /* Reload MAC parameters */ - _PHY_ReloadMACRegisters(adapt, IQK_MAC_REG, dm_odm->RFCalibrateInfo.IQK_MAC_backup); - - reload_adda_reg(adapt, IQK_BB_REG_92C, dm_odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); - - /* Restore RX initial gain */ - PHY_SetBBReg(adapt, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3); - if (is2t) - PHY_SetBBReg(adapt, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3); - - /* load 0xe30 IQC default value */ - PHY_SetBBReg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - PHY_SetBBReg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - } - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8188E() <==\n")); -} - -static void phy_LCCalibrate_8188E(struct adapter *adapt, bool is2t) -{ - u8 tmpreg; - u32 RF_Amode = 0, RF_Bmode = 0, LC_Cal; - - /* Check continuous TX and Packet TX */ - tmpreg = usb_read8(adapt, 0xd03); - - if ((tmpreg&0x70) != 0) /* Deal with contisuous TX case */ - usb_write8(adapt, 0xd03, tmpreg&0x8F); /* disable all continuous TX */ - else /* Deal with Packet TX case */ - usb_write8(adapt, REG_TXPAUSE, 0xFF); /* block all queues */ - - if ((tmpreg&0x70) != 0) { - /* 1. Read original RF mode */ - /* Path-A */ - RF_Amode = PHY_QueryRFReg(adapt, RF_PATH_A, RF_AC, bMask12Bits); - - /* Path-B */ - if (is2t) - RF_Bmode = PHY_QueryRFReg(adapt, RF_PATH_B, RF_AC, bMask12Bits); - - /* 2. Set RF mode = standby mode */ - /* Path-A */ - PHY_SetRFReg(adapt, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); - - /* Path-B */ - if (is2t) - PHY_SetRFReg(adapt, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); - } - - /* 3. Read RF reg18 */ - LC_Cal = PHY_QueryRFReg(adapt, RF_PATH_A, RF_CHNLBW, bMask12Bits); - - /* 4. Set LC calibration begin bit15 */ - PHY_SetRFReg(adapt, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); - - msleep(100); - - /* Restore original situation */ - if ((tmpreg&0x70) != 0) { - /* Deal with continuous TX case */ - /* Path-A */ - usb_write8(adapt, 0xd03, tmpreg); - PHY_SetRFReg(adapt, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); - - /* Path-B */ - if (is2t) - PHY_SetRFReg(adapt, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); - } else { - /* Deal with Packet TX case */ - usb_write8(adapt, REG_TXPAUSE, 0x00); - } -} - -void PHY_IQCalibrate_8188E(struct adapter *adapt, bool recovery) -{ - struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt); - struct odm_dm_struct *dm_odm = &pHalData->odmpriv; - s32 result[4][8]; /* last is final result */ - u8 i, final_candidate, Indexforchannel; - bool pathaok, pathbok; - s32 RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC; - bool is12simular, is13simular, is23simular; - bool singletone = false, carrier_sup = false; - u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, - rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, - rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, - rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, - rOFDM0_RxIQExtAnta}; - bool is2t; - - is2t = (dm_odm->RFType == ODM_2T2R) ? true : false; - - if (!(dm_odm->SupportAbility & ODM_RF_CALIBRATION)) - return; - - /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */ - if (singletone || carrier_sup) - return; - - if (recovery) { - ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8188E: Return due to recovery!\n")); - reload_adda_reg(adapt, IQK_BB_REG_92C, dm_odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); - return; - } - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); - - for (i = 0; i < 8; i++) { - result[0][i] = 0; - result[1][i] = 0; - result[2][i] = 0; - if ((i == 0) || (i == 2) || (i == 4) || (i == 6)) - result[3][i] = 0x100; - else - result[3][i] = 0; - } - final_candidate = 0xff; - pathaok = false; - pathbok = false; - is12simular = false; - is23simular = false; - is13simular = false; - - for (i = 0; i < 3; i++) { - phy_IQCalibrate_8188E(adapt, result, i, is2t); - - if (i == 1) { - is12simular = phy_SimularityCompare_8188E(adapt, result, 0, 1); - if (is12simular) { - final_candidate = 0; - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n", final_candidate)); - break; - } - } - - if (i == 2) { - is13simular = phy_SimularityCompare_8188E(adapt, result, 0, 2); - if (is13simular) { - final_candidate = 0; - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n", final_candidate)); - - break; - } - is23simular = phy_SimularityCompare_8188E(adapt, result, 1, 2); - if (is23simular) { - final_candidate = 1; - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n", final_candidate)); - } else { - final_candidate = 3; - } - } - } - - for (i = 0; i < 4; i++) { - RegE94 = result[i][0]; - RegE9C = result[i][1]; - RegEA4 = result[i][2]; - RegEAC = result[i][3]; - RegEB4 = result[i][4]; - RegEBC = result[i][5]; - RegEC4 = result[i][6]; - RegECC = result[i][7]; - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n", - RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - } - - if (final_candidate != 0xff) { - RegE94 = result[final_candidate][0]; - RegE9C = result[final_candidate][1]; - RegEA4 = result[final_candidate][2]; - RegEAC = result[final_candidate][3]; - RegEB4 = result[final_candidate][4]; - RegEBC = result[final_candidate][5]; - dm_odm->RFCalibrateInfo.RegE94 = RegE94; - dm_odm->RFCalibrateInfo.RegE9C = RegE9C; - dm_odm->RFCalibrateInfo.RegEB4 = RegEB4; - dm_odm->RFCalibrateInfo.RegEBC = RegEBC; - RegEC4 = result[final_candidate][6]; - RegECC = result[final_candidate][7]; - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("IQK: final_candidate is %x\n", final_candidate)); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n", - RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - pathaok = true; - pathbok = true; - } else { - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); - dm_odm->RFCalibrateInfo.RegE94 = 0x100; - dm_odm->RFCalibrateInfo.RegEB4 = 0x100; /* X default value */ - dm_odm->RFCalibrateInfo.RegE9C = 0x0; - dm_odm->RFCalibrateInfo.RegEBC = 0x0; /* Y default value */ - } - if (RegE94 != 0) - patha_fill_iqk(adapt, pathaok, result, final_candidate, (RegEA4 == 0)); - if (is2t) { - if (RegEB4 != 0) - pathb_fill_iqk(adapt, pathbok, result, final_candidate, (RegEC4 == 0)); - } - - Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); - -/* To Fix BSOD when final_candidate is 0xff */ -/* by sherry 20120321 */ - if (final_candidate < 4) { - for (i = 0; i < IQK_Matrix_REG_NUM; i++) - dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; - dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = true; - } - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); - - _PHY_SaveADDARegisters(adapt, IQK_BB_REG_92C, dm_odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); - - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); -} - -void PHY_LCCalibrate_8188E(struct adapter *adapt) -{ - bool singletone = false, carrier_sup = false; - u32 timeout = 2000, timecount = 0; - struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt); - struct odm_dm_struct *dm_odm = &pHalData->odmpriv; - - if (!(dm_odm->SupportAbility & ODM_RF_CALIBRATION)) - return; - /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */ - if (singletone || carrier_sup) - return; - - while (*(dm_odm->pbScanInProcess) && timecount < timeout) { - mdelay(50); - timecount += 50; - } - - dm_odm->RFCalibrateInfo.bLCKInProgress = true; - - if (dm_odm->RFType == ODM_2T2R) { - phy_LCCalibrate_8188E(adapt, true); - } else { - /* For 88C 1T1R */ - phy_LCCalibrate_8188E(adapt, false); - } - - dm_odm->RFCalibrateInfo.bLCKInProgress = false; - - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("LCK:Finish!!!interface %d\n", dm_odm->InterfaceIndex)); -} - -static void phy_setrfpathswitch_8188e(struct adapter *adapt, bool main, bool is2t) -{ - if (!adapt->hw_init_completed) { - u8 u1btmp; - u1btmp = usb_read8(adapt, REG_LEDCFG2) | BIT7; - usb_write8(adapt, REG_LEDCFG2, u1btmp); - PHY_SetBBReg(adapt, rFPGA0_XAB_RFParameter, BIT13, 0x01); - } - - if (is2t) { /* 92C */ - if (main) - PHY_SetBBReg(adapt, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); /* 92C_Path_A */ - else - PHY_SetBBReg(adapt, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); /* BT */ - } else { /* 88C */ - if (main) - PHY_SetBBReg(adapt, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2); /* Main */ - else - PHY_SetBBReg(adapt, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1); /* Aux */ - } -} - -void PHY_SetRFPathSwitch_8188E(struct adapter *adapt, bool main) -{ - struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt); - struct odm_dm_struct *dm_odm = &pHalData->odmpriv; - - if (dm_odm->RFType == ODM_2T2R) { - phy_setrfpathswitch_8188e(adapt, main, true); - } else { - /* For 88C 1T1R */ - phy_setrfpathswitch_8188e(adapt, main, false); - } -} diff --git a/drivers/staging/rtl8188eu/hal/HalHWImg8188E_BB.c b/drivers/staging/rtl8188eu/hal/bb_cfg.c index 787e8f1f97f9..80e8cc92c10a 100644 --- a/drivers/staging/rtl8188eu/hal/HalHWImg8188E_BB.c +++ b/drivers/staging/rtl8188eu/hal/bb_cfg.c @@ -20,7 +20,7 @@ #include "odm_precomp.h" -#include <rtw_iol.h> +#include <phy.h> #define read_next_pair(array, v1, v2, i) \ do { \ @@ -29,36 +29,8 @@ v2 = array[i+1]; \ } while (0) -static bool CheckCondition(const u32 condition, const u32 hex) -{ - u32 _board = (hex & 0x000000FF); - u32 _interface = (hex & 0x0000FF00) >> 8; - u32 _platform = (hex & 0x00FF0000) >> 16; - u32 cond = condition; - - if (condition == 0xCDCDCDCD) - return true; - - cond = condition & 0x000000FF; - if ((_board == cond) && cond != 0x00) - return false; - - cond = condition & 0x0000FF00; - cond = cond >> 8; - if ((_interface & cond) == 0 && cond != 0x07) - return false; - - cond = condition & 0x00FF0000; - cond = cond >> 16; - if ((_platform & cond) == 0 && cond != 0x0F) - return false; - return true; -} - -/****************************************************************************** -* AGC_TAB_1T.TXT -******************************************************************************/ +/* AGC_TAB_1T.TXT */ static u32 array_agc_tab_1t_8188e[] = { 0xC78, 0xFB000001, @@ -191,91 +163,25 @@ static u32 array_agc_tab_1t_8188e[] = { 0xC78, 0x407F0001, }; -enum HAL_STATUS ODM_ReadAndConfig_AGC_TAB_1T_8188E(struct odm_dm_struct *dm_odm) +static bool set_baseband_agc_config(struct adapter *adapt) { - u32 hex = 0; - u32 i = 0; - u8 platform = dm_odm->SupportPlatform; - u8 interfaceValue = dm_odm->SupportInterface; - u8 board = dm_odm->BoardType; - u32 arraylen = sizeof(array_agc_tab_1t_8188e)/sizeof(u32); - u32 *array = array_agc_tab_1t_8188e; - bool biol = false; - struct adapter *adapter = dm_odm->Adapter; - struct xmit_frame *pxmit_frame = NULL; - u8 bndy_cnt = 1; - enum HAL_STATUS rst = HAL_STATUS_SUCCESS; - - hex += board; - hex += interfaceValue << 8; - hex += platform << 16; - hex += 0xFF000000; - biol = rtw_IOL_applied(adapter); - - if (biol) { - pxmit_frame = rtw_IOL_accquire_xmit_frame(adapter); - if (pxmit_frame == NULL) { - pr_info("rtw_IOL_accquire_xmit_frame failed\n"); - return HAL_STATUS_FAILURE; - } - } + u32 i; + u32 arraylen = sizeof(array_agc_tab_1t_8188e)/sizeof(u32); + u32 *array = array_agc_tab_1t_8188e; for (i = 0; i < arraylen; i += 2) { u32 v1 = array[i]; u32 v2 = array[i+1]; - /* This (offset, data) pair meets the condition. */ - if (v1 < 0xCDCDCDCD) { - if (biol) { - if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) - bndy_cnt++; - rtw_IOL_append_WD_cmd(pxmit_frame, (u16)v1, v2, bMaskDWord); - } else { - odm_ConfigBB_AGC_8188E(dm_odm, v1, bMaskDWord, v2); - } - continue; - } else { - /* This line is the start line of branch. */ - if (!CheckCondition(array[i], hex)) { - /* Discard the following (offset, data) pairs. */ - read_next_pair(array, v1, v2, i); - while (v2 != 0xDEAD && - v2 != 0xCDEF && - v2 != 0xCDCD && i < arraylen - 2) - read_next_pair(array, v1, v2, i); - i -= 2; /* prevent from for-loop += 2 */ - } else { /* Configure matched pairs and skip to end of if-else. */ - read_next_pair(array, v1, v2, i); - while (v2 != 0xDEAD && - v2 != 0xCDEF && - v2 != 0xCDCD && i < arraylen - 2) { - if (biol) { - if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) - bndy_cnt++; - rtw_IOL_append_WD_cmd(pxmit_frame, (u16)v1, v2, bMaskDWord); - } else { - odm_ConfigBB_AGC_8188E(dm_odm, v1, bMaskDWord, v2); - } - read_next_pair(array, v1, v2, i); - } - - while (v2 != 0xDEAD && i < arraylen - 2) - read_next_pair(array, v1, v2, i); - } - } - } - if (biol) { - if (!rtw_IOL_exec_cmds_sync(dm_odm->Adapter, pxmit_frame, 1000, bndy_cnt)) { - printk("~~~ %s IOL_exec_cmds Failed !!!\n", __func__); - rst = HAL_STATUS_FAILURE; + if (v1 < 0xCDCDCDCD){ + phy_set_bb_reg(adapt, v1, bMaskDWord, v2); + udelay(1); } } - return rst; + return true; } -/****************************************************************************** -* PHY_REG_1T.TXT -******************************************************************************/ +/* PHY_REG_1T.TXT */ static u32 array_phy_reg_1t_8188e[] = { 0x800, 0x80040000, @@ -471,122 +377,44 @@ static u32 array_phy_reg_1t_8188e[] = { 0xF00, 0x00000300, }; -enum HAL_STATUS ODM_ReadAndConfig_PHY_REG_1T_8188E(struct odm_dm_struct *dm_odm) +static void rtl_bb_delay(struct adapter *adapt, u32 addr, u32 data) { - u32 hex = 0; - u32 i = 0; - u8 platform = dm_odm->SupportPlatform; - u8 interfaceValue = dm_odm->SupportInterface; - u8 board = dm_odm->BoardType; - u32 arraylen = sizeof(array_phy_reg_1t_8188e)/sizeof(u32); - u32 *array = array_phy_reg_1t_8188e; - bool biol = false; - struct adapter *adapter = dm_odm->Adapter; - struct xmit_frame *pxmit_frame = NULL; - u8 bndy_cnt = 1; - enum HAL_STATUS rst = HAL_STATUS_SUCCESS; - hex += board; - hex += interfaceValue << 8; - hex += platform << 16; - hex += 0xFF000000; - biol = rtw_IOL_applied(adapter); - - if (biol) { - pxmit_frame = rtw_IOL_accquire_xmit_frame(adapter); - if (pxmit_frame == NULL) { - pr_info("rtw_IOL_accquire_xmit_frame failed\n"); - return HAL_STATUS_FAILURE; - } + if (addr == 0xfe) { + msleep(50); + } else if (addr == 0xfd) { + mdelay(5); + } else if (addr == 0xfc) { + mdelay(1); + } else if (addr == 0xfb) { + udelay(50); + } else if (addr == 0xfa) { + udelay(5); + } else if (addr == 0xf9) { + udelay(1); + } else { + phy_set_bb_reg(adapt, addr, bMaskDWord, data); + /* Add 1us delay between BB/RF register setting. */ + udelay(1); } +} + +static bool set_baseband_phy_config(struct adapter *adapt) +{ + u32 i; + u32 arraylen = sizeof(array_phy_reg_1t_8188e)/sizeof(u32); + u32 *array = array_phy_reg_1t_8188e; for (i = 0; i < arraylen; i += 2) { u32 v1 = array[i]; u32 v2 = array[i+1]; - /* This (offset, data) pair meets the condition. */ - if (v1 < 0xCDCDCDCD) { - if (biol) { - if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) - bndy_cnt++; - if (v1 == 0xfe) { - rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 50); - } else if (v1 == 0xfd) { - rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 5); - } else if (v1 == 0xfc) { - rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 1); - } else if (v1 == 0xfb) { - rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 50); - } else if (v1 == 0xfa) { - rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5); - } else if (v1 == 0xf9) { - rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 1); - } else { - if (v1 == 0xa24) - dm_odm->RFCalibrateInfo.RegA24 = v2; - rtw_IOL_append_WD_cmd(pxmit_frame, (u16)v1, v2, bMaskDWord); - } - } else { - odm_ConfigBB_PHY_8188E(dm_odm, v1, bMaskDWord, v2); - } - continue; - } else { /* This line is the start line of branch. */ - if (!CheckCondition(array[i], hex)) { - /* Discard the following (offset, data) pairs. */ - read_next_pair(array, v1, v2, i); - while (v2 != 0xDEAD && - v2 != 0xCDEF && - v2 != 0xCDCD && i < arraylen - 2) - read_next_pair(array, v1, v2, i); - i -= 2; /* prevent from for-loop += 2 */ - } else { /* Configure matched pairs and skip to end of if-else. */ - read_next_pair(array, v1, v2, i); - while (v2 != 0xDEAD && - v2 != 0xCDEF && - v2 != 0xCDCD && i < arraylen - 2) { - if (biol) { - if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) - bndy_cnt++; - if (v1 == 0xfe) { - rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 50); - } else if (v1 == 0xfd) { - rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 5); - } else if (v1 == 0xfc) { - rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 1); - } else if (v1 == 0xfb) { - rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 50); - } else if (v1 == 0xfa) { - rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5); - } else if (v1 == 0xf9) { - rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 1); - } else{ - if (v1 == 0xa24) - dm_odm->RFCalibrateInfo.RegA24 = v2; - - rtw_IOL_append_WD_cmd(pxmit_frame, (u16)v1, v2, bMaskDWord); - } - } else { - odm_ConfigBB_PHY_8188E(dm_odm, v1, bMaskDWord, v2); - } - read_next_pair(array, v1, v2, i); - } - - while (v2 != 0xDEAD && i < arraylen - 2) - read_next_pair(array, v1, v2, i); - } - } + if (v1 < 0xCDCDCDCD) + rtl_bb_delay(adapt, v1, v2); } - if (biol) { - if (!rtw_IOL_exec_cmds_sync(dm_odm->Adapter, pxmit_frame, 1000, bndy_cnt)) { - rst = HAL_STATUS_FAILURE; - pr_info("~~~ IOL Config %s Failed !!!\n", __func__); - } - } - return rst; + return true; } -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ +/* PHY_REG_PG.TXT */ static u32 array_phy_reg_pg_8188e[] = { 0xE00, 0xFFFFFFFF, 0x06070809, @@ -680,42 +508,208 @@ static u32 array_phy_reg_pg_8188e[] = { }; -void ODM_ReadAndConfig_PHY_REG_PG_8188E(struct odm_dm_struct *dm_odm) +static void store_pwrindex_offset(struct adapter *Adapter, u32 regaddr, u32 bitmask, u32 data) { - u32 hex; - u32 i = 0; - u8 platform = dm_odm->SupportPlatform; - u8 interfaceValue = dm_odm->SupportInterface; - u8 board = dm_odm->BoardType; - u32 arraylen = sizeof(array_phy_reg_pg_8188e) / sizeof(u32); - u32 *array = array_phy_reg_pg_8188e; + struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter); + + if (regaddr == rTxAGC_A_Rate18_06) + hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][0] = data; + if (regaddr == rTxAGC_A_Rate54_24) + hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][1] = data; + if (regaddr == rTxAGC_A_CCK1_Mcs32) + hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][6] = data; + if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) + hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][7] = data; + if (regaddr == rTxAGC_A_Mcs03_Mcs00) + hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][2] = data; + if (regaddr == rTxAGC_A_Mcs07_Mcs04) + hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][3] = data; + if (regaddr == rTxAGC_A_Mcs11_Mcs08) + hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][4] = data; + if (regaddr == rTxAGC_A_Mcs15_Mcs12) { + hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][5] = data; + if (hal_data->rf_type == RF_1T1R) + hal_data->pwrGroupCnt++; + } + if (regaddr == rTxAGC_B_Rate18_06) + hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][8] = data; + if (regaddr == rTxAGC_B_Rate54_24) + hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][9] = data; + if (regaddr == rTxAGC_B_CCK1_55_Mcs32) + hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][14] = data; + if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) + hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][15] = data; + if (regaddr == rTxAGC_B_Mcs03_Mcs00) + hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][10] = data; + if (regaddr == rTxAGC_B_Mcs07_Mcs04) + hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][11] = data; + if (regaddr == rTxAGC_B_Mcs11_Mcs08) + hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][12] = data; + if (regaddr == rTxAGC_B_Mcs15_Mcs12) { + hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][13] = data; + if (hal_data->rf_type != RF_1T1R) + hal_data->pwrGroupCnt++; + } +} - hex = board + (interfaceValue << 8); - hex += (platform << 16) + 0xFF000000; +static void rtl_addr_delay(struct adapter *adapt, u32 addr, u32 bit_mask ,u32 data) +{ + if (addr == 0xfe) { + msleep(50); + } else if (addr == 0xfd) { + mdelay(5); + } else if (addr == 0xfc) { + mdelay(1); + } else if (addr == 0xfb) { + udelay(50); + } else if (addr == 0xfa) { + udelay(5); + } else if (addr == 0xf9) { + udelay(1); + } else{ + store_pwrindex_offset(adapt, addr, bit_mask, data); + } +} + +static bool config_bb_with_pgheader(struct adapter *adapt) +{ + u32 i = 0; + u32 arraylen = sizeof(array_phy_reg_pg_8188e) / sizeof(u32); + u32 *array = array_phy_reg_pg_8188e; for (i = 0; i < arraylen; i += 3) { u32 v1 = array[i]; u32 v2 = array[i+1]; u32 v3 = array[i+2]; - /* this line is a line of pure_body */ - if (v1 < 0xCDCDCDCD) { - odm_ConfigBB_PHY_REG_PG_8188E(dm_odm, v1, v2, v3); - continue; - } else { /* this line is the start of branch */ - if (!CheckCondition(array[i], hex)) { - /* don't need the hw_body */ - i += 2; /* skip the pair of expression */ - v1 = array[i]; - v2 = array[i+1]; - v3 = array[i+2]; - while (v2 != 0xDEAD) { - i += 3; - v1 = array[i]; - v2 = array[i+1]; - v3 = array[i+1]; - } - } - } + if (v1 < 0xCDCDCDCD) + rtl_addr_delay(adapt, v1, v2, v3); + } + return true; +} + +static void rtl88e_phy_init_bb_rf_register_definition(struct adapter *Adapter) +{ + struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter); + + hal_data->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; + hal_data->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; + hal_data->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; + hal_data->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; + + hal_data->PHYRegDef[RF_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; + hal_data->PHYRegDef[RF_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; + hal_data->PHYRegDef[RF_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; + hal_data->PHYRegDef[RF_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; + + hal_data->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; + hal_data->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; + + hal_data->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; + hal_data->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; + + hal_data->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; + hal_data->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; + + hal_data->PHYRegDef[RF_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; + hal_data->PHYRegDef[RF_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; + hal_data->PHYRegDef[RF_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; + hal_data->PHYRegDef[RF_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; + + hal_data->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; + hal_data->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; + hal_data->PHYRegDef[RF_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; + hal_data->PHYRegDef[RF_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; + + hal_data->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; + hal_data->PHYRegDef[RF_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; + + hal_data->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; + hal_data->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; + + hal_data->PHYRegDef[RF_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; + hal_data->PHYRegDef[RF_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; + hal_data->PHYRegDef[RF_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; + hal_data->PHYRegDef[RF_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; + + hal_data->PHYRegDef[RF_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; + hal_data->PHYRegDef[RF_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; + hal_data->PHYRegDef[RF_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; + hal_data->PHYRegDef[RF_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; + + hal_data->PHYRegDef[RF_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; + hal_data->PHYRegDef[RF_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; + hal_data->PHYRegDef[RF_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; + hal_data->PHYRegDef[RF_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; + + hal_data->PHYRegDef[RF_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; + hal_data->PHYRegDef[RF_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; + hal_data->PHYRegDef[RF_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; + hal_data->PHYRegDef[RF_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; + + hal_data->PHYRegDef[RF_PATH_A].rfRxAFE = rOFDM0_XARxAFE; + hal_data->PHYRegDef[RF_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; + hal_data->PHYRegDef[RF_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; + hal_data->PHYRegDef[RF_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; + + hal_data->PHYRegDef[RF_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; + hal_data->PHYRegDef[RF_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; + hal_data->PHYRegDef[RF_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; + hal_data->PHYRegDef[RF_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; + + hal_data->PHYRegDef[RF_PATH_A].rfTxAFE = rOFDM0_XATxAFE; + hal_data->PHYRegDef[RF_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; + hal_data->PHYRegDef[RF_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; + hal_data->PHYRegDef[RF_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; + + hal_data->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; + hal_data->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; + hal_data->PHYRegDef[RF_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; + hal_data->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; + + hal_data->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback; + hal_data->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback; +} + +static bool config_parafile(struct adapter *adapt) +{ + struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(adapt); + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + + set_baseband_phy_config(adapt); + + /* If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */ + if (!pEEPROM->bautoload_fail_flag) { + hal_data->pwrGroupCnt = 0; + config_bb_with_pgheader(adapt); } + set_baseband_agc_config(adapt); + return true; +} + +bool rtl88eu_phy_bb_config(struct adapter *adapt) +{ + int rtstatus = true; + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + u32 regval; + u8 crystal_cap; + + rtl88e_phy_init_bb_rf_register_definition(adapt); + + /* Enable BB and RF */ + regval = usb_read16(adapt, REG_SYS_FUNC_EN); + usb_write16(adapt, REG_SYS_FUNC_EN, (u16)(regval|BIT13|BIT0|BIT1)); + + usb_write8(adapt, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB); + + usb_write8(adapt, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB); + + /* Config BB and AGC */ + rtstatus = config_parafile(adapt); + + /* write 0x24[16:11] = 0x24[22:17] = crystal_cap */ + crystal_cap = hal_data->CrystalCap & 0x3F; + phy_set_bb_reg(adapt, REG_AFE_XTAL_CTRL, 0x7ff800, (crystal_cap | (crystal_cap << 6))); + + return rtstatus; } diff --git a/drivers/staging/rtl8188eu/hal/fw.c b/drivers/staging/rtl8188eu/hal/fw.c new file mode 100644 index 000000000000..17b7f3750547 --- /dev/null +++ b/drivers/staging/rtl8188eu/hal/fw.c @@ -0,0 +1,236 @@ +/****************************************************************************** + * + * Copyright(c) 2009-2013 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger <Larry.Finger@lwfinger.net> + * + *****************************************************************************/ + +#include "fw.h" +#include "drv_types.h" +#include "usb_ops_linux.h" +#include "rtl8188e_spec.h" +#include "rtl8188e_hal.h" + +#include <linux/firmware.h> +#include <linux/kmemleak.h> + +static void _rtl88e_enable_fw_download(struct adapter *adapt, bool enable) +{ + u8 tmp; + + if (enable) { + tmp = usb_read8(adapt, REG_MCUFWDL); + usb_write8(adapt, REG_MCUFWDL, tmp | 0x01); + + tmp = usb_read8(adapt, REG_MCUFWDL + 2); + usb_write8(adapt, REG_MCUFWDL + 2, tmp & 0xf7); + } else { + tmp = usb_read8(adapt, REG_MCUFWDL); + usb_write8(adapt, REG_MCUFWDL, tmp & 0xfe); + + usb_write8(adapt, REG_MCUFWDL + 1, 0x00); + } +} + +static void _rtl88e_fw_block_write(struct adapter *adapt, + const u8 *buffer, u32 size) +{ + u32 blk_sz = sizeof(u32); + u8 *buf_ptr = (u8 *)buffer; + u32 *pu4BytePtr = (u32 *)buffer; + u32 i, offset, blk_cnt, remain; + + blk_cnt = size / blk_sz; + remain = size % blk_sz; + + for (i = 0; i < blk_cnt; i++) { + offset = i * blk_sz; + usb_write32(adapt, (FW_8192C_START_ADDRESS + offset), + *(pu4BytePtr + i)); + } + + if (remain) { + offset = blk_cnt * blk_sz; + buf_ptr += offset; + for (i = 0; i < remain; i++) { + usb_write8(adapt, (FW_8192C_START_ADDRESS + + offset + i), *(buf_ptr + i)); + } + } +} + +static void _rtl88e_fill_dummy(u8 *pfwbuf, u32 *pfwlen) +{ + u32 fwlen = *pfwlen; + u8 remain = (u8) (fwlen % 4); + + remain = (remain == 0) ? 0 : (4 - remain); + + while (remain > 0) { + pfwbuf[fwlen] = 0; + fwlen++; + remain--; + } + + *pfwlen = fwlen; +} + +static void _rtl88e_fw_page_write(struct adapter *adapt, + u32 page, const u8 *buffer, u32 size) +{ + u8 value8; + u8 u8page = (u8) (page & 0x07); + + value8 = (usb_read8(adapt, REG_MCUFWDL + 2) & 0xF8) | u8page; + + usb_write8(adapt, (REG_MCUFWDL + 2), value8); + _rtl88e_fw_block_write(adapt, buffer, size); +} + +static void _rtl88e_write_fw(struct adapter *adapt, u8 *buffer, u32 size) +{ + u8 *buf_ptr = buffer; + u32 page_no, remain; + u32 page, offset; + + _rtl88e_fill_dummy(buf_ptr, &size); + + page_no = size / FW_8192C_PAGE_SIZE; + remain = size % FW_8192C_PAGE_SIZE; + + for (page = 0; page < page_no; page++) { + offset = page * FW_8192C_PAGE_SIZE; + _rtl88e_fw_page_write(adapt, page, (buf_ptr + offset), + FW_8192C_PAGE_SIZE); + } + + if (remain) { + offset = page_no * FW_8192C_PAGE_SIZE; + page = page_no; + _rtl88e_fw_page_write(adapt, page, (buf_ptr + offset), remain); + } +} + +static void rtl88e_firmware_selfreset(struct adapter *adapt) +{ + u8 u1b_tmp; + + u1b_tmp = usb_read8(adapt, REG_SYS_FUNC_EN+1); + usb_write8(adapt, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2)))); + usb_write8(adapt, REG_SYS_FUNC_EN+1, (u1b_tmp | BIT(2))); +} + +static int _rtl88e_fw_free_to_go(struct adapter *adapt) +{ + int err = -EIO; + u32 counter = 0; + u32 value32; + + do { + value32 = usb_read32(adapt, REG_MCUFWDL); + if (value32 & FWDL_ChkSum_rpt) + break; + } while (counter++ < POLLING_READY_TIMEOUT_COUNT); + + if (counter >= POLLING_READY_TIMEOUT_COUNT) { + goto exit; + } + + value32 = usb_read32(adapt, REG_MCUFWDL); + value32 |= MCUFWDL_RDY; + value32 &= ~WINTINI_RDY; + usb_write32(adapt, REG_MCUFWDL, value32); + + rtl88e_firmware_selfreset(adapt); + counter = 0; + + do { + value32 = usb_read32(adapt, REG_MCUFWDL); + if (value32 & WINTINI_RDY) { + err = 0; + goto exit; + } + + udelay(FW_8192C_POLLING_DELAY); + + } while (counter++ < POLLING_READY_TIMEOUT_COUNT); + +exit: + return err; +} + +int rtl88eu_download_fw(struct adapter *adapt) +{ + struct hal_data_8188e *rtlhal = GET_HAL_DATA(adapt); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapt); + struct device *device = dvobj_to_dev(dvobj); + const struct firmware *fw; + const char fw_name[] = "rtlwifi/rtl8188eufw.bin"; + struct rtl92c_firmware_header *pfwheader = NULL; + u8 *pfwdata; + u32 fwsize; + int err; + + if (request_firmware(&fw, fw_name, device)){ + dev_err(device, "Firmware %s not available\n", fw_name); + return -ENOENT; + } + + if (fw->size > FW_8188E_SIZE) { + dev_err(device,"Firmware size exceed 0x%X. Check it.\n", + FW_8188E_SIZE); + return -1; + } + + pfwdata = kzalloc(FW_8188E_SIZE, GFP_KERNEL); + if (!pfwdata) + return -ENOMEM; + + rtlhal->pfirmware = pfwdata; + memcpy(rtlhal->pfirmware, fw->data, fw->size); + rtlhal->fwsize = fw->size; + release_firmware(fw); + + fwsize = rtlhal->fwsize; + pfwheader = (struct rtl92c_firmware_header *)pfwdata; + + if (IS_FW_HEADER_EXIST(pfwheader)) { + pfwdata = pfwdata + 32; + fwsize = fwsize - 32; + } + + if (usb_read8(adapt, REG_MCUFWDL) & RAM_DL_SEL) { + usb_write8(adapt, REG_MCUFWDL, 0); + rtl88e_firmware_selfreset(adapt); + } + _rtl88e_enable_fw_download(adapt, true); + usb_write8(adapt, REG_MCUFWDL, usb_read8(adapt, REG_MCUFWDL) | FWDL_ChkSum_rpt); + _rtl88e_write_fw(adapt, pfwdata, fwsize); + _rtl88e_enable_fw_download(adapt, false); + + err = _rtl88e_fw_free_to_go(adapt); + + return err; +} diff --git a/drivers/staging/rtl8188eu/hal/hal_intf.c b/drivers/staging/rtl8188eu/hal/hal_intf.c index 2faa690f7e26..538a0f65d09c 100644 --- a/drivers/staging/rtl8188eu/hal/hal_intf.c +++ b/drivers/staging/rtl8188eu/hal/hal_intf.c @@ -256,22 +256,6 @@ void rtw_hal_add_ra_tid(struct adapter *adapt, u32 bitmap, u8 arg, rssi_level); } -u32 rtw_hal_read_bbreg(struct adapter *adapt, u32 regaddr, u32 bitmask) -{ - u32 data = 0; - - if (adapt->HalFunc.read_bbreg) - data = adapt->HalFunc.read_bbreg(adapt, regaddr, bitmask); - return data; -} - -void rtw_hal_write_bbreg(struct adapter *adapt, u32 regaddr, u32 bitmask, - u32 data) -{ - if (adapt->HalFunc.write_bbreg) - adapt->HalFunc.write_bbreg(adapt, regaddr, bitmask, data); -} - u32 rtw_hal_read_rfreg(struct adapter *adapt, enum rf_radio_path rfpath, u32 regaddr, u32 bitmask) { @@ -354,16 +338,6 @@ u8 rtw_hal_sreset_get_wifi_status(struct adapter *adapt) return status; } -int rtw_hal_iol_cmd(struct adapter *adapter, struct xmit_frame *xmit_frame, - u32 max_wating_ms, u32 bndy_cnt) -{ - if (adapter->HalFunc.IOL_exec_cmds_sync) - return adapter->HalFunc.IOL_exec_cmds_sync(adapter, xmit_frame, - max_wating_ms, - bndy_cnt); - return _FAIL; -} - void rtw_hal_notch_filter(struct adapter *adapter, bool enable) { if (adapter->HalFunc.hal_notch_filter) diff --git a/drivers/staging/rtl8188eu/hal/mac_cfg.c b/drivers/staging/rtl8188eu/hal/mac_cfg.c new file mode 100644 index 000000000000..c0e7fa938059 --- /dev/null +++ b/drivers/staging/rtl8188eu/hal/mac_cfg.c @@ -0,0 +1,134 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +#include "odm_precomp.h" +#include "phy.h" +#include <rtw_iol.h> + +/* MAC_REG.TXT */ + +static u32 array_MAC_REG_8188E[] = { + 0x026, 0x00000041, + 0x027, 0x00000035, + 0x428, 0x0000000A, + 0x429, 0x00000010, + 0x430, 0x00000000, + 0x431, 0x00000001, + 0x432, 0x00000002, + 0x433, 0x00000004, + 0x434, 0x00000005, + 0x435, 0x00000006, + 0x436, 0x00000007, + 0x437, 0x00000008, + 0x438, 0x00000000, + 0x439, 0x00000000, + 0x43A, 0x00000001, + 0x43B, 0x00000002, + 0x43C, 0x00000004, + 0x43D, 0x00000005, + 0x43E, 0x00000006, + 0x43F, 0x00000007, + 0x440, 0x0000005D, + 0x441, 0x00000001, + 0x442, 0x00000000, + 0x444, 0x00000015, + 0x445, 0x000000F0, + 0x446, 0x0000000F, + 0x447, 0x00000000, + 0x458, 0x00000041, + 0x459, 0x000000A8, + 0x45A, 0x00000072, + 0x45B, 0x000000B9, + 0x460, 0x00000066, + 0x461, 0x00000066, + 0x480, 0x00000008, + 0x4C8, 0x000000FF, + 0x4C9, 0x00000008, + 0x4CC, 0x000000FF, + 0x4CD, 0x000000FF, + 0x4CE, 0x00000001, + 0x4D3, 0x00000001, + 0x500, 0x00000026, + 0x501, 0x000000A2, + 0x502, 0x0000002F, + 0x503, 0x00000000, + 0x504, 0x00000028, + 0x505, 0x000000A3, + 0x506, 0x0000005E, + 0x507, 0x00000000, + 0x508, 0x0000002B, + 0x509, 0x000000A4, + 0x50A, 0x0000005E, + 0x50B, 0x00000000, + 0x50C, 0x0000004F, + 0x50D, 0x000000A4, + 0x50E, 0x00000000, + 0x50F, 0x00000000, + 0x512, 0x0000001C, + 0x514, 0x0000000A, + 0x516, 0x0000000A, + 0x525, 0x0000004F, + 0x550, 0x00000010, + 0x551, 0x00000010, + 0x559, 0x00000002, + 0x55D, 0x000000FF, + 0x605, 0x00000030, + 0x608, 0x0000000E, + 0x609, 0x0000002A, + 0x620, 0x000000FF, + 0x621, 0x000000FF, + 0x622, 0x000000FF, + 0x623, 0x000000FF, + 0x624, 0x000000FF, + 0x625, 0x000000FF, + 0x626, 0x000000FF, + 0x627, 0x000000FF, + 0x652, 0x00000020, + 0x63C, 0x0000000A, + 0x63D, 0x0000000A, + 0x63E, 0x0000000E, + 0x63F, 0x0000000E, + 0x640, 0x00000040, + 0x66E, 0x00000005, + 0x700, 0x00000021, + 0x701, 0x00000043, + 0x702, 0x00000065, + 0x703, 0x00000087, + 0x708, 0x00000021, + 0x709, 0x00000043, + 0x70A, 0x00000065, + 0x70B, 0x00000087, +}; + +bool rtl88eu_phy_mac_config(struct adapter *adapt) +{ + u32 i; + u32 arraylength; + u32 *ptrarray; + + arraylength = sizeof(array_MAC_REG_8188E)/sizeof(u32); + ptrarray = array_MAC_REG_8188E; + + for (i = 0; i < arraylength; i = i + 2) + usb_write8(adapt, ptrarray[i], (u8) ptrarray[i + 1]); + + usb_write8(adapt, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); + return true; +} diff --git a/drivers/staging/rtl8188eu/hal/odm.c b/drivers/staging/rtl8188eu/hal/odm.c index f8dcfdae0727..e4df83710ca6 100644 --- a/drivers/staging/rtl8188eu/hal/odm.c +++ b/drivers/staging/rtl8188eu/hal/odm.c @@ -21,7 +21,9 @@ /* include files */ #include "odm_precomp.h" +#include "phy.h" +u32 GlobalDebugLevel; static const u16 dB_Invert_Table[8][12] = { {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4}, {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16}, @@ -171,6 +173,13 @@ u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = { #define RxDefaultAnt1 0x65a9 #define RxDefaultAnt2 0x569a +void ODM_InitDebugSetting(struct odm_dm_struct *pDM_Odm) +{ + pDM_Odm->DebugLevel = ODM_DBG_TRACE; + + pDM_Odm->DebugComponents = 0; +} + /* 3 Export Interface */ /* 2011/09/21 MH Add to describe different team necessary resource allocate?? */ @@ -182,7 +191,6 @@ void ODM_DMInit(struct odm_dm_struct *pDM_Odm) odm_DIGInit(pDM_Odm); odm_RateAdaptiveMaskInit(pDM_Odm); - odm_PrimaryCCA_Init(pDM_Odm); /* Gary */ odm_DynamicTxPowerInit(pDM_Odm); odm_TXPowerTrackingInit(pDM_Odm); ODM_EdcaTurboInit(pDM_Odm); @@ -429,8 +437,8 @@ void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm) { struct adapter *adapter = pDM_Odm->Adapter; - pDM_Odm->bCckHighPower = (bool) PHY_QueryBBReg(adapter, 0x824, BIT9); - pDM_Odm->RFPathRxEnable = (u8) PHY_QueryBBReg(adapter, 0xc04, 0x0F); + pDM_Odm->bCckHighPower = (bool) phy_query_bb_reg(adapter, 0x824, BIT9); + pDM_Odm->RFPathRxEnable = (u8) phy_query_bb_reg(adapter, 0xc04, 0x0F); ODM_InitDebugSetting(pDM_Odm); } @@ -511,7 +519,7 @@ void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI) struct adapter *adapter = pDM_Odm->Adapter; if (pDM_DigTable->CurIGValue != CurrentIGI) { - PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N, CurrentIGI); + phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N, CurrentIGI); pDM_DigTable->CurIGValue = CurrentIGI; } } @@ -521,7 +529,7 @@ void odm_DIGInit(struct odm_dm_struct *pDM_Odm) struct adapter *adapter = pDM_Odm->Adapter; struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; - pDM_DigTable->CurIGValue = (u8) PHY_QueryBBReg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N); + pDM_DigTable->CurIGValue = (u8) phy_query_bb_reg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N); pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW; pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH; pDM_DigTable->FALowThresh = DM_false_ALARM_THRESH_LOW; @@ -733,39 +741,39 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) return; /* hold ofdm counter */ - PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */ - PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */ + phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */ + phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */ - ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord); + ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord); FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff); FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16); - ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord); + ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord); FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff); FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16); - ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord); + ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord); FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff); FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16); - ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord); + ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord); FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff); FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal + FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail + FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail; - ret_value = PHY_QueryBBReg(adapter, ODM_REG_SC_CNT_11N, bMaskDWord); + ret_value = phy_query_bb_reg(adapter, ODM_REG_SC_CNT_11N, bMaskDWord); FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff); FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16); /* hold cck counter */ - PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT12, 1); - PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT14, 1); + phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT12, 1); + phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT14, 1); - ret_value = PHY_QueryBBReg(adapter, ODM_REG_CCK_FA_LSB_11N, bMaskByte0); + ret_value = phy_query_bb_reg(adapter, ODM_REG_CCK_FA_LSB_11N, bMaskByte0); FalseAlmCnt->Cnt_Cck_fail = ret_value; - ret_value = PHY_QueryBBReg(adapter, ODM_REG_CCK_FA_MSB_11N, bMaskByte3); + ret_value = phy_query_bb_reg(adapter, ODM_REG_CCK_FA_MSB_11N, bMaskByte3); FalseAlmCnt->Cnt_Cck_fail += (ret_value & 0xff)<<8; - ret_value = PHY_QueryBBReg(adapter, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord); + ret_value = phy_query_bb_reg(adapter, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord); FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8); FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync + @@ -849,10 +857,10 @@ void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal) Rssi_Low_bound = 45; } if (pDM_PSTable->initialize == 0) { - pDM_PSTable->Reg874 = (PHY_QueryBBReg(adapter, 0x874, bMaskDWord)&0x1CC000)>>14; - pDM_PSTable->RegC70 = (PHY_QueryBBReg(adapter, 0xc70, bMaskDWord)&BIT3)>>3; - pDM_PSTable->Reg85C = (PHY_QueryBBReg(adapter, 0x85c, bMaskDWord)&0xFF000000)>>24; - pDM_PSTable->RegA74 = (PHY_QueryBBReg(adapter, 0xa74, bMaskDWord)&0xF000)>>12; + pDM_PSTable->Reg874 = (phy_query_bb_reg(adapter, 0x874, bMaskDWord)&0x1CC000)>>14; + pDM_PSTable->RegC70 = (phy_query_bb_reg(adapter, 0xc70, bMaskDWord)&BIT3)>>3; + pDM_PSTable->Reg85C = (phy_query_bb_reg(adapter, 0x85c, bMaskDWord)&0xFF000000)>>24; + pDM_PSTable->RegA74 = (phy_query_bb_reg(adapter, 0xa74, bMaskDWord)&0xF000)>>12; pDM_PSTable->initialize = 1; } @@ -878,19 +886,19 @@ void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal) if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) { if (pDM_PSTable->CurRFState == RF_Save) { - PHY_SetBBReg(adapter, 0x874 , 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */ - PHY_SetBBReg(adapter, 0xc70, BIT3, 0); /* RegC70[3]=1'b0 */ - PHY_SetBBReg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */ - PHY_SetBBReg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */ - PHY_SetBBReg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */ - PHY_SetBBReg(adapter, 0x818, BIT28, 0x0); /* Reg818[28]=1'b0 */ - PHY_SetBBReg(adapter, 0x818, BIT28, 0x1); /* Reg818[28]=1'b1 */ + phy_set_bb_reg(adapter, 0x874 , 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */ + phy_set_bb_reg(adapter, 0xc70, BIT3, 0); /* RegC70[3]=1'b0 */ + phy_set_bb_reg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */ + phy_set_bb_reg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */ + phy_set_bb_reg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */ + phy_set_bb_reg(adapter, 0x818, BIT28, 0x0); /* Reg818[28]=1'b0 */ + phy_set_bb_reg(adapter, 0x818, BIT28, 0x1); /* Reg818[28]=1'b1 */ } else { - PHY_SetBBReg(adapter, 0x874 , 0x1CC000, pDM_PSTable->Reg874); - PHY_SetBBReg(adapter, 0xc70, BIT3, pDM_PSTable->RegC70); - PHY_SetBBReg(adapter, 0x85c, 0xFF000000, pDM_PSTable->Reg85C); - PHY_SetBBReg(adapter, 0xa74, 0xF000, pDM_PSTable->RegA74); - PHY_SetBBReg(adapter, 0x818, BIT28, 0x0); + phy_set_bb_reg(adapter, 0x874 , 0x1CC000, pDM_PSTable->Reg874); + phy_set_bb_reg(adapter, 0xc70, BIT3, pDM_PSTable->RegC70); + phy_set_bb_reg(adapter, 0x85c, 0xFF000000, pDM_PSTable->Reg85C); + phy_set_bb_reg(adapter, 0xa74, 0xF000, pDM_PSTable->RegA74); + phy_set_bb_reg(adapter, 0x818, BIT28, 0x0); } pDM_PSTable->PreRFState = pDM_PSTable->CurRFState; } @@ -1235,12 +1243,12 @@ void odm_TXPowerTrackingCheckCE(struct odm_dm_struct *pDM_Odm) return; if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { /* at least delay 1 sec */ - PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); + phy_set_rf_reg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; return; } else { - odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter); + rtl88eu_dm_txpower_tracking_callback_thermalmeter(Adapter); pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; } } @@ -1256,7 +1264,7 @@ void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm) return; } - ODM_AntennaDiversityInit_88E(pDM_Odm); + rtl88eu_dm_antenna_div_init(pDM_Odm); } void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm) @@ -1266,7 +1274,7 @@ void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm) return; } - ODM_AntennaDiversity_88E(pDM_Odm); + rtl88eu_dm_antenna_diversity(pDM_Odm); } /* EDCA Turbo */ diff --git a/drivers/staging/rtl8188eu/hal/odm_HWConfig.c b/drivers/staging/rtl8188eu/hal/odm_HWConfig.c index f2e1d02b8ae3..4e4e21936e7c 100644 --- a/drivers/staging/rtl8188eu/hal/odm_HWConfig.c +++ b/drivers/staging/rtl8188eu/hal/odm_HWConfig.c @@ -315,7 +315,7 @@ static void odm_Process_RSSIForDM(struct odm_dm_struct *dm_odm, if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) { antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2<<2) | (pDM_FatTable->antsel_rx_keep_1<<1) | pDM_FatTable->antsel_rx_keep_0; - ODM_AntselStatistics_88E(dm_odm, antsel_tr_mux, pPktinfo->StationID, pPhyInfo->RxPWDBAll); + rtl88eu_dm_ant_sel_statistics(dm_odm, antsel_tr_mux, pPktinfo->StationID, pPhyInfo->RxPWDBAll); } } /* Smart Antenna Debug Message------------------ */ @@ -431,39 +431,3 @@ void ODM_PhyStatusQuery(struct odm_dm_struct *dm_odm, { ODM_PhyStatusQuery_92CSeries(dm_odm, pPhyInfo, pPhyStatus, pPktinfo); } - -enum HAL_STATUS ODM_ConfigRFWithHeaderFile(struct odm_dm_struct *dm_odm, - enum rf_radio_path content, - enum rf_radio_path rfpath) -{ - ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===>ODM_ConfigRFWithHeaderFile\n")); - if (rfpath == RF_PATH_A) - READ_AND_CONFIG(8188E, _RadioA_1T_); - ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_A:Rtl8188ERadioA_1TArray\n")); - ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_B:Rtl8188ERadioB_1TArray\n")); - - ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("ODM_ConfigRFWithHeaderFile: Radio No %x\n", rfpath)); - return HAL_STATUS_SUCCESS; -} - -enum HAL_STATUS ODM_ConfigBBWithHeaderFile(struct odm_dm_struct *dm_odm, - enum odm_bb_config_type config_tp) -{ - if (config_tp == CONFIG_BB_PHY_REG) { - READ_AND_CONFIG(8188E, _PHY_REG_1T_); - } else if (config_tp == CONFIG_BB_AGC_TAB) { - READ_AND_CONFIG(8188E, _AGC_TAB_1T_); - } else if (config_tp == CONFIG_BB_PHY_REG_PG) { - READ_AND_CONFIG(8188E, _PHY_REG_PG_); - ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, - (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8188EPHY_REG_PGArray\n")); - } - return HAL_STATUS_SUCCESS; -} - -enum HAL_STATUS ODM_ConfigMACWithHeaderFile(struct odm_dm_struct *dm_odm) -{ - u8 result = HAL_STATUS_SUCCESS; - result = READ_AND_CONFIG(8188E, _MAC_REG_); - return result; -} diff --git a/drivers/staging/rtl8188eu/hal/odm_RTL8188E.c b/drivers/staging/rtl8188eu/hal/odm_RTL8188E.c index a24d954e2732..5342af778eb0 100644 --- a/drivers/staging/rtl8188eu/hal/odm_RTL8188E.c +++ b/drivers/staging/rtl8188eu/hal/odm_RTL8188E.c @@ -19,87 +19,91 @@ ******************************************************************************/ #include "odm_precomp.h" +#include "phy.h" -static void odm_RX_HWAntDivInit(struct odm_dm_struct *dm_odm) +static void dm_rx_hw_antena_div_init(struct odm_dm_struct *dm_odm) { struct adapter *adapter = dm_odm->Adapter; - u32 value32; + u32 value32; if (*(dm_odm->mp_mode) == 1) { dm_odm->AntDivType = CGCS_RX_SW_ANTDIV; - PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); /* disable HW AntDiv */ - PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); /* 1:CG, 0:CS */ + phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); + phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); return; } - ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_RX_HWAntDivInit()\n")); /* MAC Setting */ - value32 = PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); - PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + value32 = phy_query_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); + phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, + value32|(BIT23|BIT25)); /* Pin Settings */ - PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */ - PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */ - PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 1); /* Regb2c[22]=1'b0 disable CS/CG switch */ - PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */ + phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0); + phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0); + phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 1); + phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); /* OFDM Settings */ - PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0); + phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, + 0x000000a0); /* CCK Settings */ - PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); /* Fix CCK PHY status report issue */ - PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); /* CCK complete HW AntDiv within 64 samples */ - ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT); - PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201); /* antenna mapping table */ + phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); + phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); + rtl88eu_dm_update_rx_idle_ant(dm_odm, MAIN_ANT); + phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201); } -static void odm_TRX_HWAntDivInit(struct odm_dm_struct *dm_odm) +static void dm_trx_hw_antenna_div_init(struct odm_dm_struct *dm_odm) { struct adapter *adapter = dm_odm->Adapter; u32 value32; if (*(dm_odm->mp_mode) == 1) { dm_odm->AntDivType = CGCS_RX_SW_ANTDIV; - PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); /* disable HW AntDiv */ - PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT5|BIT4|BIT3, 0); /* Default RX (0/1) */ + phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); + phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, + BIT5|BIT4|BIT3, 0); return; } - ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_TRX_HWAntDivInit()\n")); /* MAC Setting */ - value32 = PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); - PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + value32 = phy_query_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); + phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, + value32|(BIT23|BIT25)); /* Pin Settings */ - PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */ - PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */ - PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 0); /* Regb2c[22]=1'b0 disable CS/CG switch */ - PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */ + phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0); + phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0); + phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 0); + phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); /* OFDM Settings */ - PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0); + phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, + 0x000000a0); /* CCK Settings */ - PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); /* Fix CCK PHY status report issue */ - PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); /* CCK complete HW AntDiv within 64 samples */ + phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); + phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); /* Tx Settings */ - PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 0); /* Reg80c[21]=1'b0 from TX Reg */ - ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT); + phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 0); + rtl88eu_dm_update_rx_idle_ant(dm_odm, MAIN_ANT); /* antenna mapping table */ if (!dm_odm->bIsMPChip) { /* testchip */ - PHY_SetBBReg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT10|BIT9|BIT8, 1); /* Reg858[10:8]=3'b001 */ - PHY_SetBBReg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT13|BIT12|BIT11, 2); /* Reg858[13:11]=3'b010 */ + phy_set_bb_reg(adapter, ODM_REG_RX_DEFUALT_A_11N, + BIT10|BIT9|BIT8, 1); + phy_set_bb_reg(adapter, ODM_REG_RX_DEFUALT_A_11N, + BIT13|BIT12|BIT11, 2); } else { /* MPchip */ - PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, bMaskDWord, 0x0201); /* Reg914=3'b010, Reg915=3'b001 */ + phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, bMaskDWord, + 0x0201); } } -static void odm_FastAntTrainingInit(struct odm_dm_struct *dm_odm) +static void dm_fast_training_init(struct odm_dm_struct *dm_odm) { struct adapter *adapter = dm_odm->Adapter; - u32 value32, i; + u32 value32, i; struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; - u32 AntCombination = 2; - - ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_FastAntTrainingInit()\n")); + u32 AntCombination = 2; if (*(dm_odm->mp_mode) == 1) { - ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("dm_odm->AntDivType: %d\n", dm_odm->AntDivType)); return; } @@ -113,208 +117,206 @@ static void odm_FastAntTrainingInit(struct odm_dm_struct *dm_odm) dm_fat_tbl->FAT_State = FAT_NORMAL_STATE; /* MAC Setting */ - value32 = PHY_QueryBBReg(adapter, 0x4c, bMaskDWord); - PHY_SetBBReg(adapter, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ - value32 = PHY_QueryBBReg(adapter, 0x7B4, bMaskDWord); - PHY_SetBBReg(adapter, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */ + value32 = phy_query_bb_reg(adapter, 0x4c, bMaskDWord); + phy_set_bb_reg(adapter, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); + value32 = phy_query_bb_reg(adapter, 0x7B4, bMaskDWord); + phy_set_bb_reg(adapter, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); /* Match MAC ADDR */ - PHY_SetBBReg(adapter, 0x7b4, 0xFFFF, 0); - PHY_SetBBReg(adapter, 0x7b0, bMaskDWord, 0); + phy_set_bb_reg(adapter, 0x7b4, 0xFFFF, 0); + phy_set_bb_reg(adapter, 0x7b0, bMaskDWord, 0); - PHY_SetBBReg(adapter, 0x870, BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */ - PHY_SetBBReg(adapter, 0x864, BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */ - PHY_SetBBReg(adapter, 0xb2c, BIT22, 0); /* Regb2c[22]=1'b0 disable CS/CG switch */ - PHY_SetBBReg(adapter, 0xb2c, BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */ - PHY_SetBBReg(adapter, 0xca4, bMaskDWord, 0x000000a0); + phy_set_bb_reg(adapter, 0x870, BIT9|BIT8, 0); + phy_set_bb_reg(adapter, 0x864, BIT10, 0); + phy_set_bb_reg(adapter, 0xb2c, BIT22, 0); + phy_set_bb_reg(adapter, 0xb2c, BIT31, 1); + phy_set_bb_reg(adapter, 0xca4, bMaskDWord, 0x000000a0); /* antenna mapping table */ if (AntCombination == 2) { if (!dm_odm->bIsMPChip) { /* testchip */ - PHY_SetBBReg(adapter, 0x858, BIT10|BIT9|BIT8, 1); /* Reg858[10:8]=3'b001 */ - PHY_SetBBReg(adapter, 0x858, BIT13|BIT12|BIT11, 2); /* Reg858[13:11]=3'b010 */ + phy_set_bb_reg(adapter, 0x858, BIT10|BIT9|BIT8, 1); + phy_set_bb_reg(adapter, 0x858, BIT13|BIT12|BIT11, 2); } else { /* MPchip */ - PHY_SetBBReg(adapter, 0x914, bMaskByte0, 1); - PHY_SetBBReg(adapter, 0x914, bMaskByte1, 2); + phy_set_bb_reg(adapter, 0x914, bMaskByte0, 1); + phy_set_bb_reg(adapter, 0x914, bMaskByte1, 2); } } else if (AntCombination == 7) { if (!dm_odm->bIsMPChip) { /* testchip */ - PHY_SetBBReg(adapter, 0x858, BIT10|BIT9|BIT8, 0); /* Reg858[10:8]=3'b000 */ - PHY_SetBBReg(adapter, 0x858, BIT13|BIT12|BIT11, 1); /* Reg858[13:11]=3'b001 */ - PHY_SetBBReg(adapter, 0x878, BIT16, 0); - PHY_SetBBReg(adapter, 0x858, BIT15|BIT14, 2); /* Reg878[0],Reg858[14:15])=3'b010 */ - PHY_SetBBReg(adapter, 0x878, BIT19|BIT18|BIT17, 3);/* Reg878[3:1]=3b'011 */ - PHY_SetBBReg(adapter, 0x878, BIT22|BIT21|BIT20, 4);/* Reg878[6:4]=3b'100 */ - PHY_SetBBReg(adapter, 0x878, BIT25|BIT24|BIT23, 5);/* Reg878[9:7]=3b'101 */ - PHY_SetBBReg(adapter, 0x878, BIT28|BIT27|BIT26, 6);/* Reg878[12:10]=3b'110 */ - PHY_SetBBReg(adapter, 0x878, BIT31|BIT30|BIT29, 7);/* Reg878[15:13]=3b'111 */ + phy_set_bb_reg(adapter, 0x858, BIT10|BIT9|BIT8, 0); + phy_set_bb_reg(adapter, 0x858, BIT13|BIT12|BIT11, 1); + phy_set_bb_reg(adapter, 0x878, BIT16, 0); + phy_set_bb_reg(adapter, 0x858, BIT15|BIT14, 2); + phy_set_bb_reg(adapter, 0x878, BIT19|BIT18|BIT17, 3); + phy_set_bb_reg(adapter, 0x878, BIT22|BIT21|BIT20, 4); + phy_set_bb_reg(adapter, 0x878, BIT25|BIT24|BIT23, 5); + phy_set_bb_reg(adapter, 0x878, BIT28|BIT27|BIT26, 6); + phy_set_bb_reg(adapter, 0x878, BIT31|BIT30|BIT29, 7); } else { /* MPchip */ - PHY_SetBBReg(adapter, 0x914, bMaskByte0, 0); - PHY_SetBBReg(adapter, 0x914, bMaskByte1, 1); - PHY_SetBBReg(adapter, 0x914, bMaskByte2, 2); - PHY_SetBBReg(adapter, 0x914, bMaskByte3, 3); - PHY_SetBBReg(adapter, 0x918, bMaskByte0, 4); - PHY_SetBBReg(adapter, 0x918, bMaskByte1, 5); - PHY_SetBBReg(adapter, 0x918, bMaskByte2, 6); - PHY_SetBBReg(adapter, 0x918, bMaskByte3, 7); + phy_set_bb_reg(adapter, 0x914, bMaskByte0, 0); + phy_set_bb_reg(adapter, 0x914, bMaskByte1, 1); + phy_set_bb_reg(adapter, 0x914, bMaskByte2, 2); + phy_set_bb_reg(adapter, 0x914, bMaskByte3, 3); + phy_set_bb_reg(adapter, 0x918, bMaskByte0, 4); + phy_set_bb_reg(adapter, 0x918, bMaskByte1, 5); + phy_set_bb_reg(adapter, 0x918, bMaskByte2, 6); + phy_set_bb_reg(adapter, 0x918, bMaskByte3, 7); } } /* Default Ant Setting when no fast training */ - PHY_SetBBReg(adapter, 0x80c, BIT21, 1); /* Reg80c[21]=1'b1 from TX Info */ - PHY_SetBBReg(adapter, 0x864, BIT5|BIT4|BIT3, 0); /* Default RX */ - PHY_SetBBReg(adapter, 0x864, BIT8|BIT7|BIT6, 1); /* Optional RX */ + phy_set_bb_reg(adapter, 0x80c, BIT21, 1); + phy_set_bb_reg(adapter, 0x864, BIT5|BIT4|BIT3, 0); + phy_set_bb_reg(adapter, 0x864, BIT8|BIT7|BIT6, 1); /* Enter Traing state */ - PHY_SetBBReg(adapter, 0x864, BIT2|BIT1|BIT0, (AntCombination-1)); /* Reg864[2:0]=3'd6 ant combination=reg864[2:0]+1 */ - PHY_SetBBReg(adapter, 0xc50, BIT7, 1); /* RegC50[7]=1'b1 enable HW AntDiv */ + phy_set_bb_reg(adapter, 0x864, BIT2|BIT1|BIT0, (AntCombination-1)); + phy_set_bb_reg(adapter, 0xc50, BIT7, 1); } -void ODM_AntennaDiversityInit_88E(struct odm_dm_struct *dm_odm) +void rtl88eu_dm_antenna_div_init(struct odm_dm_struct *dm_odm) { - ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_odm->AntDivType=%d\n", dm_odm->AntDivType)); - ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_odm->bIsMPChip=%s\n", (dm_odm->bIsMPChip ? "true" : "false"))); - if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) - odm_RX_HWAntDivInit(dm_odm); + dm_rx_hw_antena_div_init(dm_odm); else if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) - odm_TRX_HWAntDivInit(dm_odm); + dm_trx_hw_antenna_div_init(dm_odm); else if (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV) - odm_FastAntTrainingInit(dm_odm); + dm_fast_training_init(dm_odm); } -void ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant) +void rtl88eu_dm_update_rx_idle_ant(struct odm_dm_struct *dm_odm, u8 ant) { struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; struct adapter *adapter = dm_odm->Adapter; - u32 DefaultAnt, OptionalAnt; - - if (dm_fat_tbl->RxIdleAnt != Ant) { - ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Update Rx Idle Ant\n")); - if (Ant == MAIN_ANT) { - DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX; - OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX; + u32 default_ant, optional_ant; + + if (dm_fat_tbl->RxIdleAnt != ant) { + if (ant == MAIN_ANT) { + default_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? + MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX; + optional_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? + AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX; } else { - DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX; - OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX; + default_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? + AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX; + optional_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? + MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX; } if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) { - PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT5|BIT4|BIT3, DefaultAnt); /* Default RX */ - PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT8|BIT7|BIT6, OptionalAnt); /* Optional RX */ - PHY_SetBBReg(adapter, ODM_REG_ANTSEL_CTRL_11N, BIT14|BIT13|BIT12, DefaultAnt); /* Default TX */ - PHY_SetBBReg(adapter, ODM_REG_RESP_TX_11N, BIT6|BIT7, DefaultAnt); /* Resp Tx */ + phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, + BIT5|BIT4|BIT3, default_ant); + phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, + BIT8|BIT7|BIT6, optional_ant); + phy_set_bb_reg(adapter, ODM_REG_ANTSEL_CTRL_11N, + BIT14|BIT13|BIT12, default_ant); + phy_set_bb_reg(adapter, ODM_REG_RESP_TX_11N, + BIT6|BIT7, default_ant); } else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) { - PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT5|BIT4|BIT3, DefaultAnt); /* Default RX */ - PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT8|BIT7|BIT6, OptionalAnt); /* Optional RX */ + phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, + BIT5|BIT4|BIT3, default_ant); + phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, + BIT8|BIT7|BIT6, optional_ant); } } - dm_fat_tbl->RxIdleAnt = Ant; - ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RxIdleAnt=%s\n", (Ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); - pr_info("RxIdleAnt=%s\n", (Ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + dm_fat_tbl->RxIdleAnt = ant; } -static void odm_UpdateTxAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant, u32 MacId) +static void update_tx_ant_88eu(struct odm_dm_struct *dm_odm, u8 ant, u32 mac_id) { struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; - u8 TargetAnt; + u8 target_ant; - if (Ant == MAIN_ANT) - TargetAnt = MAIN_ANT_CG_TRX; + if (ant == MAIN_ANT) + target_ant = MAIN_ANT_CG_TRX; else - TargetAnt = AUX_ANT_CG_TRX; - dm_fat_tbl->antsel_a[MacId] = TargetAnt&BIT0; - dm_fat_tbl->antsel_b[MacId] = (TargetAnt&BIT1)>>1; - dm_fat_tbl->antsel_c[MacId] = (TargetAnt&BIT2)>>2; - - ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("Tx from TxInfo, TargetAnt=%s\n", - (Ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); - ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("antsel_tr_mux=3'b%d%d%d\n", - dm_fat_tbl->antsel_c[MacId], dm_fat_tbl->antsel_b[MacId], dm_fat_tbl->antsel_a[MacId])); + target_ant = AUX_ANT_CG_TRX; + dm_fat_tbl->antsel_a[mac_id] = target_ant&BIT0; + dm_fat_tbl->antsel_b[mac_id] = (target_ant&BIT1)>>1; + dm_fat_tbl->antsel_c[mac_id] = (target_ant&BIT2)>>2; } -void ODM_SetTxAntByTxInfo_88E(struct odm_dm_struct *dm_odm, u8 *pDesc, u8 macId) +void rtl88eu_dm_set_tx_ant_by_tx_info(struct odm_dm_struct *dm_odm, + u8 *desc, u8 mac_id) { struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; - if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)) { - SET_TX_DESC_ANTSEL_A_88E(pDesc, dm_fat_tbl->antsel_a[macId]); - SET_TX_DESC_ANTSEL_B_88E(pDesc, dm_fat_tbl->antsel_b[macId]); - SET_TX_DESC_ANTSEL_C_88E(pDesc, dm_fat_tbl->antsel_c[macId]); + if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || + (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)) { + SET_TX_DESC_ANTSEL_A_88E(desc, dm_fat_tbl->antsel_a[mac_id]); + SET_TX_DESC_ANTSEL_B_88E(desc, dm_fat_tbl->antsel_b[mac_id]); + SET_TX_DESC_ANTSEL_C_88E(desc, dm_fat_tbl->antsel_c[mac_id]); } } -void ODM_AntselStatistics_88E(struct odm_dm_struct *dm_odm, u8 antsel_tr_mux, u32 MacId, u8 RxPWDBAll) +void rtl88eu_dm_ant_sel_statistics(struct odm_dm_struct *dm_odm, + u8 antsel_tr_mux, u32 mac_id, u8 rx_pwdb_all) { struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) { if (antsel_tr_mux == MAIN_ANT_CG_TRX) { - dm_fat_tbl->MainAnt_Sum[MacId] += RxPWDBAll; - dm_fat_tbl->MainAnt_Cnt[MacId]++; + dm_fat_tbl->MainAnt_Sum[mac_id] += rx_pwdb_all; + dm_fat_tbl->MainAnt_Cnt[mac_id]++; } else { - dm_fat_tbl->AuxAnt_Sum[MacId] += RxPWDBAll; - dm_fat_tbl->AuxAnt_Cnt[MacId]++; + dm_fat_tbl->AuxAnt_Sum[mac_id] += rx_pwdb_all; + dm_fat_tbl->AuxAnt_Cnt[mac_id]++; } } else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) { if (antsel_tr_mux == MAIN_ANT_CGCS_RX) { - dm_fat_tbl->MainAnt_Sum[MacId] += RxPWDBAll; - dm_fat_tbl->MainAnt_Cnt[MacId]++; + dm_fat_tbl->MainAnt_Sum[mac_id] += rx_pwdb_all; + dm_fat_tbl->MainAnt_Cnt[mac_id]++; } else { - dm_fat_tbl->AuxAnt_Sum[MacId] += RxPWDBAll; - dm_fat_tbl->AuxAnt_Cnt[MacId]++; + dm_fat_tbl->AuxAnt_Sum[mac_id] += rx_pwdb_all; + dm_fat_tbl->AuxAnt_Cnt[mac_id]++; } } } -static void odm_HWAntDiv(struct odm_dm_struct *dm_odm) +static void rtl88eu_dm_hw_ant_div(struct odm_dm_struct *dm_odm) { - u32 i, MinRSSI = 0xFF, AntDivMaxRSSI = 0, MaxRSSI = 0, LocalMinRSSI, LocalMaxRSSI; - u32 Main_RSSI, Aux_RSSI; - u8 RxIdleAnt = 0, TargetAnt = 7; struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; - struct rtw_dig *pDM_DigTable = &dm_odm->DM_DigTable; - struct sta_info *pEntry; + struct rtw_dig *dig_table = &dm_odm->DM_DigTable; + struct sta_info *entry; + u32 i, min_rssi = 0xFF, ant_div_max_rssi = 0, max_rssi = 0; + u32 local_min_rssi,local_max_rssi; + u32 main_rssi, aux_rssi; + u8 RxIdleAnt = 0, target_ant = 7; for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - pEntry = dm_odm->pODM_StaInfo[i]; - if (IS_STA_VALID(pEntry)) { + entry = dm_odm->pODM_StaInfo[i]; + if (IS_STA_VALID(entry)) { /* 2 Caculate RSSI per Antenna */ - Main_RSSI = (dm_fat_tbl->MainAnt_Cnt[i] != 0) ? (dm_fat_tbl->MainAnt_Sum[i]/dm_fat_tbl->MainAnt_Cnt[i]) : 0; - Aux_RSSI = (dm_fat_tbl->AuxAnt_Cnt[i] != 0) ? (dm_fat_tbl->AuxAnt_Sum[i]/dm_fat_tbl->AuxAnt_Cnt[i]) : 0; - TargetAnt = (Main_RSSI >= Aux_RSSI) ? MAIN_ANT : AUX_ANT; - ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("MacID=%d, MainAnt_Sum=%d, MainAnt_Cnt=%d\n", - i, dm_fat_tbl->MainAnt_Sum[i], - dm_fat_tbl->MainAnt_Cnt[i])); - ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("MacID=%d, AuxAnt_Sum=%d, AuxAnt_Cnt=%d\n", - i, dm_fat_tbl->AuxAnt_Sum[i], dm_fat_tbl->AuxAnt_Cnt[i])); - ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("MacID=%d, Main_RSSI= %d, Aux_RSSI= %d\n", - i, Main_RSSI, Aux_RSSI)); - /* 2 Select MaxRSSI for DIG */ - LocalMaxRSSI = (Main_RSSI > Aux_RSSI) ? Main_RSSI : Aux_RSSI; - if ((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40)) - AntDivMaxRSSI = LocalMaxRSSI; - if (LocalMaxRSSI > MaxRSSI) - MaxRSSI = LocalMaxRSSI; + main_rssi = (dm_fat_tbl->MainAnt_Cnt[i] != 0) ? + (dm_fat_tbl->MainAnt_Sum[i]/dm_fat_tbl->MainAnt_Cnt[i]) : 0; + aux_rssi = (dm_fat_tbl->AuxAnt_Cnt[i] != 0) ? + (dm_fat_tbl->AuxAnt_Sum[i]/dm_fat_tbl->AuxAnt_Cnt[i]) : 0; + target_ant = (main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT; + /* 2 Select max_rssi for DIG */ + local_max_rssi = (main_rssi > aux_rssi) ? + main_rssi : aux_rssi; + if ((local_max_rssi > ant_div_max_rssi) && + (local_max_rssi < 40)) + ant_div_max_rssi = local_max_rssi; + if (local_max_rssi > max_rssi) + max_rssi = local_max_rssi; /* 2 Select RX Idle Antenna */ - if ((dm_fat_tbl->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0)) - Main_RSSI = Aux_RSSI; - else if ((dm_fat_tbl->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0)) - Aux_RSSI = Main_RSSI; - - LocalMinRSSI = (Main_RSSI > Aux_RSSI) ? Aux_RSSI : Main_RSSI; - if (LocalMinRSSI < MinRSSI) { - MinRSSI = LocalMinRSSI; - RxIdleAnt = TargetAnt; + if ((dm_fat_tbl->RxIdleAnt == MAIN_ANT) && + (main_rssi == 0)) + main_rssi = aux_rssi; + else if ((dm_fat_tbl->RxIdleAnt == AUX_ANT) && + (aux_rssi == 0)) + aux_rssi = main_rssi; + + local_min_rssi = (main_rssi > aux_rssi) ? + aux_rssi : main_rssi; + if (local_min_rssi < min_rssi) { + min_rssi = local_min_rssi; + RxIdleAnt = target_ant; } /* 2 Select TRX Antenna */ if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) - odm_UpdateTxAnt_88E(dm_odm, TargetAnt, i); + update_tx_ant_88eu(dm_odm, target_ant, i); } dm_fat_tbl->MainAnt_Sum[i] = 0; dm_fat_tbl->AuxAnt_Sum[i] = 0; @@ -323,13 +325,13 @@ static void odm_HWAntDiv(struct odm_dm_struct *dm_odm) } /* 2 Set RX Idle Antenna */ - ODM_UpdateRxIdleAnt_88E(dm_odm, RxIdleAnt); + rtl88eu_dm_update_rx_idle_ant(dm_odm, RxIdleAnt); - pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI; - pDM_DigTable->RSSI_max = MaxRSSI; + dig_table->AntDiv_RSSI_max = ant_div_max_rssi; + dig_table->RSSI_max = max_rssi; } -void ODM_AntennaDiversity_88E(struct odm_dm_struct *dm_odm) +void rtl88eu_dm_antenna_diversity(struct odm_dm_struct *dm_odm) { struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; struct adapter *adapter = dm_odm->Adapter; @@ -337,42 +339,34 @@ void ODM_AntennaDiversity_88E(struct odm_dm_struct *dm_odm) if (!(dm_odm->SupportAbility & ODM_BB_ANT_DIV)) return; if (!dm_odm->bLinked) { - ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E(): No Link.\n")); + ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("ODM_AntennaDiversity_88E(): No Link.\n")); if (dm_fat_tbl->bBecomeLinked) { - ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn off HW AntDiv\n")); - PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); /* RegC50[7]=1'b1 enable HW AntDiv */ - PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 0); /* Enable CCK AntDiv */ + ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("Need to Turn off HW AntDiv\n")); + phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); + phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, + BIT15, 0); if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) - PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 0); /* Reg80c[21]=1'b0 from TX Reg */ + phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N, + BIT21, 0); dm_fat_tbl->bBecomeLinked = dm_odm->bLinked; } return; } else { if (!dm_fat_tbl->bBecomeLinked) { - ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn on HW AntDiv\n")); - /* Because HW AntDiv is disabled before Link, we enable HW AntDiv after link */ - PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT7, 1); /* RegC50[7]=1'b1 enable HW AntDiv */ - PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 1); /* Enable CCK AntDiv */ + ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("Need to Turn on HW AntDiv\n")); + phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 1); + phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, + BIT15, 1); if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) - PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 1); /* Reg80c[21]=1'b1 from TX Info */ + phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N, + BIT21, 1); dm_fat_tbl->bBecomeLinked = dm_odm->bLinked; } } - if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV)) - odm_HWAntDiv(dm_odm); -} - -/* 3============================================================ */ -/* 3 Dynamic Primary CCA */ -/* 3============================================================ */ - -void odm_PrimaryCCA_Init(struct odm_dm_struct *dm_odm) -{ - struct dyn_primary_cca *PrimaryCCA = &(dm_odm->DM_PriCCA); - - PrimaryCCA->DupRTS_flag = 0; - PrimaryCCA->intf_flag = 0; - PrimaryCCA->intf_type = 0; - PrimaryCCA->Monitor_flag = 0; - PrimaryCCA->PriCCA_flag = 0; + if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || + (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV)) + rtl88eu_dm_hw_ant_div(dm_odm); } diff --git a/drivers/staging/rtl8188eu/hal/odm_RegConfig8188E.c b/drivers/staging/rtl8188eu/hal/odm_RegConfig8188E.c deleted file mode 100644 index 4d4978bee51d..000000000000 --- a/drivers/staging/rtl8188eu/hal/odm_RegConfig8188E.c +++ /dev/null @@ -1,138 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "odm_precomp.h" - -void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, - u32 Data, enum rf_radio_path RF_PATH, - u32 RegAddr) -{ - struct adapter *adapter = pDM_Odm->Adapter; - - if (Addr == 0xffe) { - msleep(50); - } else if (Addr == 0xfd) { - mdelay(5); - } else if (Addr == 0xfc) { - mdelay(1); - } else if (Addr == 0xfb) { - udelay(50); - } else if (Addr == 0xfa) { - udelay(5); - } else if (Addr == 0xf9) { - udelay(1); - } else { - PHY_SetRFReg(adapter, RF_PATH, RegAddr, bRFRegOffsetMask, Data); - /* Add 1us delay between BB/RF register setting. */ - udelay(1); - } -} - -void odm_ConfigRF_RadioA_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Data) -{ - u32 content = 0x1000; /* RF_Content: radioa_txt */ - u32 maskforPhySet = (u32)(content&0xE000); - - odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, RF_PATH_A, Addr|maskforPhySet); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); -} - -void odm_ConfigRF_RadioB_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Data) -{ - u32 content = 0x1001; /* RF_Content: radiob_txt */ - u32 maskforPhySet = (u32)(content&0xE000); - - odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, RF_PATH_B, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); -} - -void odm_ConfigMAC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u8 Data) -{ - struct adapter *adapt = pDM_Odm->Adapter; - - usb_write8(adapt, Addr, Data); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); -} - -void odm_ConfigBB_AGC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data) -{ - struct adapter *adapter = pDM_Odm->Adapter; - - PHY_SetBBReg(adapter, Addr, Bitmask, Data); - /* Add 1us delay between BB/RF register setting. */ - udelay(1); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", - Addr, Data)); -} - -void odm_ConfigBB_PHY_REG_PG_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, - u32 Bitmask, u32 Data) -{ - if (Addr == 0xfe) { - msleep(50); - } else if (Addr == 0xfd) { - mdelay(5); - } else if (Addr == 0xfc) { - mdelay(1); - } else if (Addr == 0xfb) { - udelay(50); - } else if (Addr == 0xfa) { - udelay(5); - } else if (Addr == 0xf9) { - udelay(1); - } else{ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("===> @@@@@@@ ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", - Addr, Bitmask, Data)); - storePwrIndexDiffRateOffset(pDM_Odm->Adapter, Addr, Bitmask, Data); - } -} - -void odm_ConfigBB_PHY_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data) -{ - struct adapter *adapter = pDM_Odm->Adapter; - - if (Addr == 0xfe) { - msleep(50); - } else if (Addr == 0xfd) { - mdelay(5); - } else if (Addr == 0xfc) { - mdelay(1); - } else if (Addr == 0xfb) { - udelay(50); - } else if (Addr == 0xfa) { - udelay(5); - } else if (Addr == 0xf9) { - udelay(1); - } else { - if (Addr == 0xa24) - pDM_Odm->RFCalibrateInfo.RegA24 = Data; - PHY_SetBBReg(adapter, Addr, Bitmask, Data); - - /* Add 1us delay between BB/RF register setting. */ - udelay(1); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", - Addr, Data)); - } -} diff --git a/drivers/staging/rtl8188eu/hal/odm_debug.c b/drivers/staging/rtl8188eu/hal/odm_debug.c deleted file mode 100644 index 84caadd6c8e5..000000000000 --- a/drivers/staging/rtl8188eu/hal/odm_debug.c +++ /dev/null @@ -1,32 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -/* include files */ - -#include "odm_precomp.h" - -void ODM_InitDebugSetting(struct odm_dm_struct *pDM_Odm) -{ - pDM_Odm->DebugLevel = ODM_DBG_TRACE; - - pDM_Odm->DebugComponents = 0; -} - -u32 GlobalDebugLevel; diff --git a/drivers/staging/rtl8188eu/hal/phy.c b/drivers/staging/rtl8188eu/hal/phy.c new file mode 100644 index 000000000000..c4f7f358a81c --- /dev/null +++ b/drivers/staging/rtl8188eu/hal/phy.c @@ -0,0 +1,1570 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTL8188E_PHYCFG_C_ + +#include <osdep_service.h> +#include <drv_types.h> +#include <rtw_iol.h> +#include <rtl8188e_hal.h> +#include <rf.h> +#include <phy.h> + +#define MAX_PRECMD_CNT 16 +#define MAX_RFDEPENDCMD_CNT 16 +#define MAX_POSTCMD_CNT 16 + +#define MAX_DOZE_WAITING_TIMES_9x 64 + +static u32 cal_bit_shift(u32 bitmask) +{ + u32 i; + + for (i = 0; i <= 31; i++) { + if (((bitmask >> i) & 0x1) == 1) + break; + } + return i; +} + +u32 phy_query_bb_reg(struct adapter *adapt, u32 regaddr, u32 bitmask) +{ + u32 return_value = 0, original_value, bit_shift; + + original_value = usb_read32(adapt, regaddr); + bit_shift = cal_bit_shift(bitmask); + return_value = (original_value & bitmask) >> bit_shift; + return return_value; +} + +void phy_set_bb_reg(struct adapter *adapt, u32 regaddr, u32 bitmask, u32 data) +{ + u32 original_value, bit_shift; + + if (bitmask != bMaskDWord) { /* if not "double word" write */ + original_value = usb_read32(adapt, regaddr); + bit_shift = cal_bit_shift(bitmask); + data = ((original_value & (~bitmask)) | (data << bit_shift)); + } + + usb_write32(adapt, regaddr, data); +} + +static u32 rf_serial_read(struct adapter *adapt, + enum rf_radio_path rfpath, u32 offset) +{ + u32 ret = 0; + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + struct bb_reg_def *phyreg = &hal_data->PHYRegDef[rfpath]; + u32 newoffset; + u32 tmplong, tmplong2; + u8 rfpi_enable = 0; + + offset &= 0xff; + newoffset = offset; + + tmplong = phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter2, bMaskDWord); + if (rfpath == RF_PATH_A) + tmplong2 = tmplong; + else + tmplong2 = phy_query_bb_reg(adapt, phyreg->rfHSSIPara2, + bMaskDWord); + + tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | + (newoffset<<23) | bLSSIReadEdge; + + phy_set_bb_reg(adapt, rFPGA0_XA_HSSIParameter2, bMaskDWord, + tmplong&(~bLSSIReadEdge)); + udelay(10); + + phy_set_bb_reg(adapt, phyreg->rfHSSIPara2, bMaskDWord, tmplong2); + udelay(100); + + udelay(10); + + if (rfpath == RF_PATH_A) + rfpi_enable = (u8)phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, BIT8); + else if (rfpath == RF_PATH_B) + rfpi_enable = (u8)phy_query_bb_reg(adapt, rFPGA0_XB_HSSIParameter1, BIT8); + + if (rfpi_enable) + ret = phy_query_bb_reg(adapt, phyreg->rfLSSIReadBackPi, + bLSSIReadBackData); + else + ret = phy_query_bb_reg(adapt, phyreg->rfLSSIReadBack, + bLSSIReadBackData); + return ret; +} + +static void rf_serial_write(struct adapter *adapt, + enum rf_radio_path rfpath, u32 offset, + u32 data) +{ + u32 data_and_addr = 0; + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + struct bb_reg_def *phyreg = &hal_data->PHYRegDef[rfpath]; + u32 newoffset; + + newoffset = offset & 0xff; + data_and_addr = ((newoffset<<20) | (data&0x000fffff)) & 0x0fffffff; + phy_set_bb_reg(adapt, phyreg->rf3wireOffset, bMaskDWord, data_and_addr); +} + +u32 phy_query_rf_reg(struct adapter *adapt, enum rf_radio_path rf_path, + u32 reg_addr, u32 bit_mask) +{ + u32 original_value, readback_value, bit_shift; + + original_value = rf_serial_read(adapt, rf_path, reg_addr); + bit_shift = cal_bit_shift(bit_mask); + readback_value = (original_value & bit_mask) >> bit_shift; + return readback_value; +} + +void phy_set_rf_reg(struct adapter *adapt, enum rf_radio_path rf_path, + u32 reg_addr, u32 bit_mask, u32 data) +{ + u32 original_value, bit_shift; + + /* RF data is 12 bits only */ + if (bit_mask != bRFRegOffsetMask) { + original_value = rf_serial_read(adapt, rf_path, reg_addr); + bit_shift = cal_bit_shift(bit_mask); + data = ((original_value & (~bit_mask)) | (data << bit_shift)); + } + + rf_serial_write(adapt, rf_path, reg_addr, data); +} + +static void get_tx_power_index(struct adapter *adapt, u8 channel, u8 *cck_pwr, + u8 *ofdm_pwr, u8 *bw20_pwr, u8 *bw40_pwr) +{ + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + u8 index = (channel - 1); + u8 TxCount = 0, path_nums; + + if ((RF_1T2R == hal_data->rf_type) || (RF_1T1R == hal_data->rf_type)) + path_nums = 1; + else + path_nums = 2; + + for (TxCount = 0; TxCount < path_nums; TxCount++) { + if (TxCount == RF_PATH_A) { + cck_pwr[TxCount] = hal_data->Index24G_CCK_Base[TxCount][index]; + ofdm_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index]+ + hal_data->OFDM_24G_Diff[TxCount][RF_PATH_A]; + + bw20_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index]+ + hal_data->BW20_24G_Diff[TxCount][RF_PATH_A]; + bw40_pwr[TxCount] = hal_data->Index24G_BW40_Base[TxCount][index]; + } else if (TxCount == RF_PATH_B) { + cck_pwr[TxCount] = hal_data->Index24G_CCK_Base[TxCount][index]; + ofdm_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index]+ + hal_data->BW20_24G_Diff[RF_PATH_A][index]+ + hal_data->BW20_24G_Diff[TxCount][index]; + + bw20_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index]+ + hal_data->BW20_24G_Diff[TxCount][RF_PATH_A]+ + hal_data->BW20_24G_Diff[TxCount][index]; + bw40_pwr[TxCount] = hal_data->Index24G_BW40_Base[TxCount][index]; + } else if (TxCount == RF_PATH_C) { + cck_pwr[TxCount] = hal_data->Index24G_CCK_Base[TxCount][index]; + ofdm_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index]+ + hal_data->BW20_24G_Diff[RF_PATH_A][index]+ + hal_data->BW20_24G_Diff[RF_PATH_B][index]+ + hal_data->BW20_24G_Diff[TxCount][index]; + + bw20_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index]+ + hal_data->BW20_24G_Diff[RF_PATH_A][index]+ + hal_data->BW20_24G_Diff[RF_PATH_B][index]+ + hal_data->BW20_24G_Diff[TxCount][index]; + bw40_pwr[TxCount] = hal_data->Index24G_BW40_Base[TxCount][index]; + } else if (TxCount == RF_PATH_D) { + cck_pwr[TxCount] = hal_data->Index24G_CCK_Base[TxCount][index]; + ofdm_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index]+ + hal_data->BW20_24G_Diff[RF_PATH_A][index]+ + hal_data->BW20_24G_Diff[RF_PATH_B][index]+ + hal_data->BW20_24G_Diff[RF_PATH_C][index]+ + hal_data->BW20_24G_Diff[TxCount][index]; + + bw20_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index]+ + hal_data->BW20_24G_Diff[RF_PATH_A][index]+ + hal_data->BW20_24G_Diff[RF_PATH_B][index]+ + hal_data->BW20_24G_Diff[RF_PATH_C][index]+ + hal_data->BW20_24G_Diff[TxCount][index]; + bw40_pwr[TxCount] = hal_data->Index24G_BW40_Base[TxCount][index]; + } + } +} + +static void phy_power_index_check(struct adapter *adapt, u8 channel, + u8 *cck_pwr, u8 *ofdm_pwr, u8 *bw20_pwr, + u8 *bw40_pwr) +{ + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + + hal_data->CurrentCckTxPwrIdx = cck_pwr[0]; + hal_data->CurrentOfdm24GTxPwrIdx = ofdm_pwr[0]; + hal_data->CurrentBW2024GTxPwrIdx = bw20_pwr[0]; + hal_data->CurrentBW4024GTxPwrIdx = bw40_pwr[0]; +} + +void phy_set_tx_power_level(struct adapter *adapt, u8 channel) +{ + u8 cck_pwr[MAX_TX_COUNT] = {0}; + u8 ofdm_pwr[MAX_TX_COUNT] = {0};/* [0]:RF-A, [1]:RF-B */ + u8 bw20_pwr[MAX_TX_COUNT] = {0}; + u8 bw40_pwr[MAX_TX_COUNT] = {0}; + + get_tx_power_index(adapt, channel, &cck_pwr[0], &ofdm_pwr[0], + &bw20_pwr[0], &bw40_pwr[0]); + + phy_power_index_check(adapt, channel, &cck_pwr[0], &ofdm_pwr[0], + &bw20_pwr[0], &bw40_pwr[0]); + + rtl88eu_phy_rf6052_set_cck_txpower(adapt, &cck_pwr[0]); + rtl88eu_phy_rf6052_set_ofdm_txpower(adapt, &ofdm_pwr[0], &bw20_pwr[0], + &bw40_pwr[0], channel); +} + +static void phy_set_bw_mode_callback(struct adapter *adapt) +{ + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + u8 reg_bw_opmode; + u8 reg_prsr_rsc; + + if (hal_data->rf_chip == RF_PSEUDO_11N) + return; + + /* There is no 40MHz mode in RF_8225. */ + if (hal_data->rf_chip == RF_8225) + return; + + if (adapt->bDriverStopped) + return; + + /* Set MAC register */ + + reg_bw_opmode = usb_read8(adapt, REG_BWOPMODE); + reg_prsr_rsc = usb_read8(adapt, REG_RRSR+2); + + switch (hal_data->CurrentChannelBW) { + case HT_CHANNEL_WIDTH_20: + reg_bw_opmode |= BW_OPMODE_20MHZ; + usb_write8(adapt, REG_BWOPMODE, reg_bw_opmode); + break; + case HT_CHANNEL_WIDTH_40: + reg_bw_opmode &= ~BW_OPMODE_20MHZ; + usb_write8(adapt, REG_BWOPMODE, reg_bw_opmode); + reg_prsr_rsc = (reg_prsr_rsc&0x90) | + (hal_data->nCur40MhzPrimeSC<<5); + usb_write8(adapt, REG_RRSR+2, reg_prsr_rsc); + break; + default: + break; + } + + /* Set PHY related register */ + switch (hal_data->CurrentChannelBW) { + case HT_CHANNEL_WIDTH_20: + phy_set_bb_reg(adapt, rFPGA0_RFMOD, bRFMOD, 0x0); + phy_set_bb_reg(adapt, rFPGA1_RFMOD, bRFMOD, 0x0); + break; + case HT_CHANNEL_WIDTH_40: + phy_set_bb_reg(adapt, rFPGA0_RFMOD, bRFMOD, 0x1); + phy_set_bb_reg(adapt, rFPGA1_RFMOD, bRFMOD, 0x1); + /* Set Control channel to upper or lower. + * These settings are required only for 40MHz + */ + phy_set_bb_reg(adapt, rCCK0_System, bCCKSideBand, + (hal_data->nCur40MhzPrimeSC>>1)); + phy_set_bb_reg(adapt, rOFDM1_LSTF, 0xC00, + hal_data->nCur40MhzPrimeSC); + phy_set_bb_reg(adapt, 0x818, (BIT26 | BIT27), + (hal_data->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); + break; + default: + break; + } + + /* Set RF related register */ + switch (hal_data->rf_chip) { + case RF_8225: + break; + case RF_8256: + break; + case RF_8258: + break; + case RF_PSEUDO_11N: + break; + case RF_6052: + rtl88eu_phy_rf6052_set_bandwidth(adapt, hal_data->CurrentChannelBW); + break; + default: + break; + } +} + +void phy_set_bw_mode(struct adapter *adapt, enum ht_channel_width bandwidth, + unsigned char offset) +{ + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + enum ht_channel_width tmp_bw = hal_data->CurrentChannelBW; + + hal_data->CurrentChannelBW = bandwidth; + hal_data->nCur40MhzPrimeSC = offset; + + if ((!adapt->bDriverStopped) && (!adapt->bSurpriseRemoved)) + phy_set_bw_mode_callback(adapt); + else + hal_data->CurrentChannelBW = tmp_bw; +} + +static void phy_sw_chnl_callback(struct adapter *adapt, u8 channel) +{ + u8 rf_path; + u32 param1, param2; + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + + if (adapt->bNotifyChannelChange) + DBG_88E("[%s] ch = %d\n", __func__, channel); + + phy_set_tx_power_level(adapt, channel); + + param1 = RF_CHNLBW; + param2 = channel; + for (rf_path = 0; rf_path < hal_data->NumTotalRFPath; rf_path++) { + hal_data->RfRegChnlVal[rf_path] = (hal_data->RfRegChnlVal[rf_path] & + 0xfffffc00) | param2; + phy_set_rf_reg(adapt, (enum rf_radio_path)rf_path, param1, + bRFRegOffsetMask, hal_data->RfRegChnlVal[rf_path]); + } +} + +void phy_sw_chnl(struct adapter *adapt, u8 channel) +{ + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + u8 tmpchannel = hal_data->CurrentChannel; + bool result = true; + + if (hal_data->rf_chip == RF_PSEUDO_11N) + return; + + if (channel == 0) + channel = 1; + + hal_data->CurrentChannel = channel; + + if ((!adapt->bDriverStopped) && (!adapt->bSurpriseRemoved)) { + phy_sw_chnl_callback(adapt, channel); + + if (!result) + hal_data->CurrentChannel = tmpchannel; + + } else { + hal_data->CurrentChannel = tmpchannel; + } +} + +#define ODM_TXPWRTRACK_MAX_IDX_88E 6 + +static u8 get_right_chnl_for_iqk(u8 chnl) +{ + u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, + 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, + 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, + 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, + 155, 157, 159, 161, 163, 165 + }; + u8 place = chnl; + + if (chnl > 14) { + for (place = 14; place < sizeof(channel_all); place++) { + if (channel_all[place] == chnl) + return place-13; + } + } + return 0; +} + +void rtl88eu_dm_txpower_track_adjust(struct odm_dm_struct *dm_odm, u8 type, + u8 *direction, u32 *out_write_val) +{ + u8 pwr_value = 0; + /* Tx power tracking BB swing table. */ + if (type == 0) { /* For OFDM adjust */ + ODM_RT_TRACE(dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("BbSwingIdxOfdm = %d BbSwingFlagOfdm=%d\n", + dm_odm->BbSwingIdxOfdm, dm_odm->BbSwingFlagOfdm)); + + if (dm_odm->BbSwingIdxOfdm <= dm_odm->BbSwingIdxOfdmBase) { + *direction = 1; + pwr_value = (dm_odm->BbSwingIdxOfdmBase - + dm_odm->BbSwingIdxOfdm); + } else { + *direction = 2; + pwr_value = (dm_odm->BbSwingIdxOfdm - + dm_odm->BbSwingIdxOfdmBase); + } + + } else if (type == 1) { /* For CCK adjust. */ + ODM_RT_TRACE(dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("dm_odm->BbSwingIdxCck = %d dm_odm->BbSwingIdxCckBase = %d\n", + dm_odm->BbSwingIdxCck, dm_odm->BbSwingIdxCckBase)); + + if (dm_odm->BbSwingIdxCck <= dm_odm->BbSwingIdxCckBase) { + *direction = 1; + pwr_value = (dm_odm->BbSwingIdxCckBase - + dm_odm->BbSwingIdxCck); + } else { + *direction = 2; + pwr_value = (dm_odm->BbSwingIdxCck - + dm_odm->BbSwingIdxCckBase); + } + + } + + if (pwr_value >= ODM_TXPWRTRACK_MAX_IDX_88E && *direction == 1) + pwr_value = ODM_TXPWRTRACK_MAX_IDX_88E; + + *out_write_val = pwr_value | (pwr_value<<8) | (pwr_value<<16) | + (pwr_value<<24); +} + +static void dm_txpwr_track_setpwr(struct odm_dm_struct *dm_odm) +{ + if (dm_odm->BbSwingFlagOfdm || dm_odm->BbSwingFlagCck) { + ODM_RT_TRACE(dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("dm_txpwr_track_setpwr CH=%d\n", *(dm_odm->pChannel))); + phy_set_tx_power_level(dm_odm->Adapter, *(dm_odm->pChannel)); + dm_odm->BbSwingFlagOfdm = false; + dm_odm->BbSwingFlagCck = false; + } +} + +void rtl88eu_dm_txpower_tracking_callback_thermalmeter(struct adapter *adapt) +{ + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + u8 thermal_val = 0, delta, delta_lck, delta_iqk, offset; + u8 thermal_avg_count = 0; + u32 thermal_avg = 0; + s32 ele_a = 0, ele_d, temp_cck, x, value32; + s32 y, ele_c = 0; + s8 ofdm_index[2], cck_index = 0; + s8 ofdm_index_old[2] = {0, 0}, cck_index_old = 0; + u32 i = 0, j = 0; + bool is2t = false; + + u8 ofdm_min_index = 6, rf; /* OFDM BB Swing should be less than +3.0dB */ + u8 indexforchannel = 0; + s8 ofdm_index_mapping[2][index_mapping_NUM_88E] = { + /* 2.4G, decrease power */ + {0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11}, + /* 2.4G, increase power */ + {0, 0, -1, -2, -3, -4,-4, -4, -4, -5, -7, -8,-9, -9, -10}, + }; + u8 thermal_mapping[2][index_mapping_NUM_88E] = { + /* 2.4G, decrease power */ + {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 27}, + /* 2.4G, increase power */ + {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 25, 25, 25}, + }; + struct odm_dm_struct *dm_odm = &hal_data->odmpriv; + + dm_txpwr_track_setpwr(dm_odm); + + dm_odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++; + dm_odm->RFCalibrateInfo.bTXPowerTrackingInit = true; + + dm_odm->RFCalibrateInfo.RegA24 = 0x090e1317; + + thermal_val = (u8)phy_query_rf_reg(adapt, RF_PATH_A, + RF_T_METER_88E, 0xfc00); + + if (is2t) + rf = 2; + else + rf = 1; + + if (thermal_val) { + /* Query OFDM path A default setting */ + ele_d = phy_query_bb_reg(adapt, rOFDM0_XATxIQImbalance, bMaskDWord)&bMaskOFDM_D; + for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { + if (ele_d == (OFDMSwingTable[i]&bMaskOFDM_D)) { + ofdm_index_old[0] = (u8)i; + dm_odm->BbSwingIdxOfdmBase = (u8)i; + break; + } + } + + /* Query OFDM path B default setting */ + if (is2t) { + ele_d = phy_query_bb_reg(adapt, rOFDM0_XBTxIQImbalance, bMaskDWord)&bMaskOFDM_D; + for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { + if (ele_d == (OFDMSwingTable[i]&bMaskOFDM_D)) { + ofdm_index_old[1] = (u8)i; + break; + } + } + } + + /* Query CCK default setting From 0xa24 */ + temp_cck = dm_odm->RFCalibrateInfo.RegA24; + + for (i = 0; i < CCK_TABLE_SIZE; i++) { + if (dm_odm->RFCalibrateInfo.bCCKinCH14) { + if (memcmp(&temp_cck, &CCKSwingTable_Ch14[i][2], 4)) { + cck_index_old = (u8)i; + dm_odm->BbSwingIdxCckBase = (u8)i; + break; + } + } else { + if (memcmp(&temp_cck, &CCKSwingTable_Ch1_Ch13[i][2], 4)) { + cck_index_old = (u8)i; + dm_odm->BbSwingIdxCckBase = (u8)i; + break; + } + } + } + + if (!dm_odm->RFCalibrateInfo.ThermalValue) { + dm_odm->RFCalibrateInfo.ThermalValue = hal_data->EEPROMThermalMeter; + dm_odm->RFCalibrateInfo.ThermalValue_LCK = thermal_val; + dm_odm->RFCalibrateInfo.ThermalValue_IQK = thermal_val; + + for (i = 0; i < rf; i++) + dm_odm->RFCalibrateInfo.OFDM_index[i] = ofdm_index_old[i]; + dm_odm->RFCalibrateInfo.CCK_index = cck_index_old; + } + + /* calculate average thermal meter */ + dm_odm->RFCalibrateInfo.ThermalValue_AVG[dm_odm->RFCalibrateInfo.ThermalValue_AVG_index] = thermal_val; + dm_odm->RFCalibrateInfo.ThermalValue_AVG_index++; + if (dm_odm->RFCalibrateInfo.ThermalValue_AVG_index == AVG_THERMAL_NUM_88E) + dm_odm->RFCalibrateInfo.ThermalValue_AVG_index = 0; + + for (i = 0; i < AVG_THERMAL_NUM_88E; i++) { + if (dm_odm->RFCalibrateInfo.ThermalValue_AVG[i]) { + thermal_avg += dm_odm->RFCalibrateInfo.ThermalValue_AVG[i]; + thermal_avg_count++; + } + } + + if (thermal_avg_count) + thermal_val = (u8)(thermal_avg / thermal_avg_count); + + if (dm_odm->RFCalibrateInfo.bReloadtxpowerindex) { + delta = thermal_val > hal_data->EEPROMThermalMeter ? + (thermal_val - hal_data->EEPROMThermalMeter) : + (hal_data->EEPROMThermalMeter - thermal_val); + dm_odm->RFCalibrateInfo.bReloadtxpowerindex = false; + dm_odm->RFCalibrateInfo.bDoneTxpower = false; + } else if (dm_odm->RFCalibrateInfo.bDoneTxpower) { + delta = (thermal_val > dm_odm->RFCalibrateInfo.ThermalValue) ? + (thermal_val - dm_odm->RFCalibrateInfo.ThermalValue) : + (dm_odm->RFCalibrateInfo.ThermalValue - thermal_val); + } else { + delta = thermal_val > hal_data->EEPROMThermalMeter ? + (thermal_val - hal_data->EEPROMThermalMeter) : + (hal_data->EEPROMThermalMeter - thermal_val); + } + delta_lck = (thermal_val > dm_odm->RFCalibrateInfo.ThermalValue_LCK) ? + (thermal_val - dm_odm->RFCalibrateInfo.ThermalValue_LCK) : + (dm_odm->RFCalibrateInfo.ThermalValue_LCK - thermal_val); + delta_iqk = (thermal_val > dm_odm->RFCalibrateInfo.ThermalValue_IQK) ? + (thermal_val - dm_odm->RFCalibrateInfo.ThermalValue_IQK) : + (dm_odm->RFCalibrateInfo.ThermalValue_IQK - thermal_val); + + /* Delta temperature is equal to or larger than 20 centigrade.*/ + if ((delta_lck >= 8)) { + dm_odm->RFCalibrateInfo.ThermalValue_LCK = thermal_val; + rtl88eu_phy_lc_calibrate(adapt); + } + + if (delta > 0 && dm_odm->RFCalibrateInfo.TxPowerTrackControl) { + delta = thermal_val > hal_data->EEPROMThermalMeter ? + (thermal_val - hal_data->EEPROMThermalMeter) : + (hal_data->EEPROMThermalMeter - thermal_val); + /* calculate new OFDM / CCK offset */ + if (thermal_val > hal_data->EEPROMThermalMeter) + j = 1; + else + j = 0; + for (offset = 0; offset < index_mapping_NUM_88E; offset++) { + if (delta < thermal_mapping[j][offset]) { + if (offset != 0) + offset--; + break; + } + } + if (offset >= index_mapping_NUM_88E) + offset = index_mapping_NUM_88E-1; + for (i = 0; i < rf; i++) + ofdm_index[i] = dm_odm->RFCalibrateInfo.OFDM_index[i] + ofdm_index_mapping[j][offset]; + cck_index = dm_odm->RFCalibrateInfo.CCK_index + ofdm_index_mapping[j][offset]; + + for (i = 0; i < rf; i++) { + if (ofdm_index[i] > OFDM_TABLE_SIZE_92D-1) + ofdm_index[i] = OFDM_TABLE_SIZE_92D-1; + else if (ofdm_index[i] < ofdm_min_index) + ofdm_index[i] = ofdm_min_index; + } + + if (cck_index > CCK_TABLE_SIZE-1) + cck_index = CCK_TABLE_SIZE-1; + else if (cck_index < 0) + cck_index = 0; + + /* 2 temporarily remove bNOPG */ + /* Config by SwingTable */ + if (dm_odm->RFCalibrateInfo.TxPowerTrackControl) { + dm_odm->RFCalibrateInfo.bDoneTxpower = true; + + /* Adujst OFDM Ant_A according to IQK result */ + ele_d = (OFDMSwingTable[(u8)ofdm_index[0]] & 0xFFC00000)>>22; + x = dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[indexforchannel].Value[0][0]; + y = dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[indexforchannel].Value[0][1]; + + /* Revse TX power table. */ + dm_odm->BbSwingIdxOfdm = (u8)ofdm_index[0]; + dm_odm->BbSwingIdxCck = (u8)cck_index; + + if (dm_odm->BbSwingIdxOfdmCurrent != dm_odm->BbSwingIdxOfdm) { + dm_odm->BbSwingIdxOfdmCurrent = dm_odm->BbSwingIdxOfdm; + dm_odm->BbSwingFlagOfdm = true; + } + + if (dm_odm->BbSwingIdxCckCurrent != dm_odm->BbSwingIdxCck) { + dm_odm->BbSwingIdxCckCurrent = dm_odm->BbSwingIdxCck; + dm_odm->BbSwingFlagCck = true; + } + + if (x != 0) { + if ((x & 0x00000200) != 0) + x = x | 0xFFFFFC00; + ele_a = ((x * ele_d)>>8)&0x000003FF; + + /* new element C = element D x Y */ + if ((y & 0x00000200) != 0) + y = y | 0xFFFFFC00; + ele_c = ((y * ele_d)>>8)&0x000003FF; + + } + + if (is2t) { + ele_d = (OFDMSwingTable[(u8)ofdm_index[1]] & 0xFFC00000)>>22; + + /* new element A = element D x X */ + x = dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[indexforchannel].Value[0][4]; + y = dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[indexforchannel].Value[0][5]; + + if ((x != 0) && (*(dm_odm->pBandType) == ODM_BAND_2_4G)) { + if ((x & 0x00000200) != 0) /* consider minus */ + x = x | 0xFFFFFC00; + ele_a = ((x * ele_d)>>8)&0x000003FF; + + /* new element C = element D x Y */ + if ((y & 0x00000200) != 0) + y = y | 0xFFFFFC00; + ele_c = ((y * ele_d)>>8)&0x00003FF; + + /* wtite new elements A, C, D to regC88 and regC9C, element B is always 0 */ + value32 = (ele_d<<22) | ((ele_c&0x3F)<<16) | ele_a; + phy_set_bb_reg(adapt, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); + + value32 = (ele_c&0x000003C0)>>6; + phy_set_bb_reg(adapt, rOFDM0_XDTxAFE, bMaskH4Bits, value32); + + value32 = ((x * ele_d)>>7)&0x01; + phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT28, value32); + } else { + phy_set_bb_reg(adapt, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable[(u8)ofdm_index[1]]); + phy_set_bb_reg(adapt, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); + phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT28, 0x00); + } + + } + + } + } + + /* Delta temperature is equal to or larger than 20 centigrade.*/ + if (delta_iqk >= 8) { + dm_odm->RFCalibrateInfo.ThermalValue_IQK = thermal_val; + rtl88eu_phy_iq_calibrate(adapt, false); + } + /* update thermal meter value */ + if (dm_odm->RFCalibrateInfo.TxPowerTrackControl) + dm_odm->RFCalibrateInfo.ThermalValue = thermal_val; + } + dm_odm->RFCalibrateInfo.TXPowercount = 0; +} + +#define MAX_TOLERANCE 5 + +static u8 phy_path_a_iqk(struct adapter *adapt, bool config_pathb) +{ + u32 reg_eac, reg_e94, reg_e9c, reg_ea4; + u8 result = 0x00; + + /* 1 Tx IQK */ + /* path-A IQK setting */ + phy_set_bb_reg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); + phy_set_bb_reg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); + phy_set_bb_reg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x8214032a); + phy_set_bb_reg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160000); + + /* LO calibration setting */ + phy_set_bb_reg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + /* One shot, path A LOK & IQK */ + phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + mdelay(IQK_DELAY_TIME_88E); + + reg_eac = phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord); + reg_e94 = phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A, bMaskDWord); + reg_e9c = phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, bMaskDWord); + reg_ea4 = phy_query_bb_reg(adapt, rRx_Power_Before_IQK_A_2, bMaskDWord); + + if (!(reg_eac & BIT28) && + (((reg_e94 & 0x03FF0000)>>16) != 0x142) && + (((reg_e9c & 0x03FF0000)>>16) != 0x42)) + result |= 0x01; + return result; +} + +static u8 phy_path_a_rx_iqk(struct adapter *adapt, bool configPathB) +{ + u32 reg_eac, reg_e94, reg_e9c, reg_ea4, u4tmp; + u8 result = 0x00; + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + struct odm_dm_struct *dm_odm = &hal_data->odmpriv; + + /* 1 Get TXIMR setting */ + /* modify RXIQK mode table */ + phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000); + phy_set_rf_reg(adapt, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + phy_set_rf_reg(adapt, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + phy_set_rf_reg(adapt, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + phy_set_rf_reg(adapt, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B); + + /* PA,PAD off */ + phy_set_rf_reg(adapt, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980); + phy_set_rf_reg(adapt, RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000); + + phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000); + + /* IQK setting */ + phy_set_bb_reg(adapt, rTx_IQK, bMaskDWord, 0x01007c00); + phy_set_bb_reg(adapt, rRx_IQK, bMaskDWord, 0x81004800); + + /* path-A IQK setting */ + phy_set_bb_reg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); + phy_set_bb_reg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); + phy_set_bb_reg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); + phy_set_bb_reg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160000); + + /* LO calibration setting */ + phy_set_bb_reg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + /* One shot, path A LOK & IQK */ + phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + /* delay x ms */ + mdelay(IQK_DELAY_TIME_88E); + + /* Check failed */ + reg_eac = phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord); + reg_e94 = phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A, bMaskDWord); + reg_e9c = phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, bMaskDWord); + + if (!(reg_eac & BIT28) && + (((reg_e94 & 0x03FF0000)>>16) != 0x142) && + (((reg_e9c & 0x03FF0000)>>16) != 0x42)) + result |= 0x01; + else /* if Tx not OK, ignore Rx */ + return result; + + u4tmp = 0x80007C00 | (reg_e94&0x3FF0000) | ((reg_e9c&0x3FF0000) >> 16); + phy_set_bb_reg(adapt, rTx_IQK, bMaskDWord, u4tmp); + + /* 1 RX IQK */ + /* modify RXIQK mode table */ + ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("Path-A Rx IQK modify RXIQK mode table 2!\n")); + phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000); + phy_set_rf_reg(adapt, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + phy_set_rf_reg(adapt, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + phy_set_rf_reg(adapt, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + phy_set_rf_reg(adapt, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa); + phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000); + + /* IQK setting */ + phy_set_bb_reg(adapt, rRx_IQK, bMaskDWord, 0x01004800); + + /* path-A IQK setting */ + phy_set_bb_reg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + phy_set_bb_reg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + phy_set_bb_reg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x82160c05); + phy_set_bb_reg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160c1f); + + /* LO calibration setting */ + phy_set_bb_reg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + mdelay(IQK_DELAY_TIME_88E); + + /* Check failed */ + reg_eac = phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord); + reg_e94 = phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A, bMaskDWord); + reg_e9c = phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, bMaskDWord); + reg_ea4 = phy_query_bb_reg(adapt, rRx_Power_Before_IQK_A_2, bMaskDWord); + + /* reload RF 0xdf */ + phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000); + phy_set_rf_reg(adapt, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); + + if (!(reg_eac & BIT27) && /* if Tx is OK, check whether Rx is OK */ + (((reg_ea4 & 0x03FF0000)>>16) != 0x132) && + (((reg_eac & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("Path A Rx IQK fail!!\n")); + + return result; +} + +static u8 phy_path_b_iqk(struct adapter *adapt) +{ + u32 regeac, regeb4, regebc, regec4, regecc; + u8 result = 0x00; + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + struct odm_dm_struct *dm_odm = &hal_data->odmpriv; + + /* One shot, path B LOK & IQK */ + phy_set_bb_reg(adapt, rIQK_AGC_Cont, bMaskDWord, 0x00000002); + phy_set_bb_reg(adapt, rIQK_AGC_Cont, bMaskDWord, 0x00000000); + + mdelay(IQK_DELAY_TIME_88E); + + regeac = phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord); + regeb4 = phy_query_bb_reg(adapt, rTx_Power_Before_IQK_B, bMaskDWord); + regebc = phy_query_bb_reg(adapt, rTx_Power_After_IQK_B, bMaskDWord); + regec4 = phy_query_bb_reg(adapt, rRx_Power_Before_IQK_B_2, bMaskDWord); + regecc = phy_query_bb_reg(adapt, rRx_Power_After_IQK_B_2, bMaskDWord); + + if (!(regeac & BIT31) && + (((regeb4 & 0x03FF0000)>>16) != 0x142) && + (((regebc & 0x03FF0000)>>16) != 0x42)) + result |= 0x01; + else + return result; + + if (!(regeac & BIT30) && + (((regec4 & 0x03FF0000)>>16) != 0x132) && + (((regecc & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, + ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); + return result; +} + +static void patha_fill_iqk(struct adapter *adapt, bool iqkok, s32 result[][8], + u8 final_candidate, bool txonly) +{ + u32 oldval_0, x, tx0_a, reg; + s32 y, tx0_c; + + if (final_candidate == 0xFF) { + return; + } else if (iqkok) { + oldval_0 = (phy_query_bb_reg(adapt, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + x = result[final_candidate][0]; + if ((x & 0x00000200) != 0) + x = x | 0xFFFFFC00; + + tx0_a = (x * oldval_0) >> 8; + phy_set_bb_reg(adapt, rOFDM0_XATxIQImbalance, 0x3FF, tx0_a); + phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(31), + ((x * oldval_0>>7) & 0x1)); + + y = result[final_candidate][1]; + if ((y & 0x00000200) != 0) + y = y | 0xFFFFFC00; + + tx0_c = (y * oldval_0) >> 8; + phy_set_bb_reg(adapt, rOFDM0_XCTxAFE, 0xF0000000, + ((tx0_c&0x3C0)>>6)); + phy_set_bb_reg(adapt, rOFDM0_XATxIQImbalance, 0x003F0000, + (tx0_c&0x3F)); + phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(29), + ((y * oldval_0>>7) & 0x1)); + + if (txonly) + return; + + reg = result[final_candidate][2]; + phy_set_bb_reg(adapt, rOFDM0_XARxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][3] & 0x3F; + phy_set_bb_reg(adapt, rOFDM0_XARxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][3] >> 6) & 0xF; + phy_set_bb_reg(adapt, rOFDM0_RxIQExtAnta, 0xF0000000, reg); + } +} + +static void pathb_fill_iqk(struct adapter *adapt, bool iqkok, s32 result[][8], + u8 final_candidate, bool txonly) +{ + u32 oldval_1, x, tx1_a, reg; + s32 y, tx1_c; + + if (final_candidate == 0xFF) { + return; + } else if (iqkok) { + oldval_1 = (phy_query_bb_reg(adapt, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + x = result[final_candidate][4]; + if ((x & 0x00000200) != 0) + x = x | 0xFFFFFC00; + tx1_a = (x * oldval_1) >> 8; + phy_set_bb_reg(adapt, rOFDM0_XBTxIQImbalance, 0x3FF, tx1_a); + + phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(27), + ((x * oldval_1>>7) & 0x1)); + + y = result[final_candidate][5]; + if ((y & 0x00000200) != 0) + y = y | 0xFFFFFC00; + + tx1_c = (y * oldval_1) >> 8; + + phy_set_bb_reg(adapt, rOFDM0_XDTxAFE, 0xF0000000, + ((tx1_c&0x3C0)>>6)); + phy_set_bb_reg(adapt, rOFDM0_XBTxIQImbalance, 0x003F0000, + (tx1_c&0x3F)); + phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(25), + ((y * oldval_1>>7) & 0x1)); + + if (txonly) + return; + + reg = result[final_candidate][6]; + phy_set_bb_reg(adapt, rOFDM0_XBRxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][7] & 0x3F; + phy_set_bb_reg(adapt, rOFDM0_XBRxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][7] >> 6) & 0xF; + phy_set_bb_reg(adapt, rOFDM0_AGCRSSITable, 0x0000F000, reg); + } +} + +static void save_adda_registers(struct adapter *adapt, u32 *addareg, + u32 *backup, u32 register_num) +{ + u32 i; + + for (i = 0; i < register_num; i++) { + backup[i] = phy_query_bb_reg(adapt, addareg[i], bMaskDWord); + } +} + +static void save_mac_registers(struct adapter *adapt, u32 *mac_reg, + u32 *backup) +{ + u32 i; + + for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) { + backup[i] = usb_read8(adapt, mac_reg[i]); + } + backup[i] = usb_read32(adapt, mac_reg[i]); +} + +static void reload_adda_reg(struct adapter *adapt, u32 *adda_reg, + u32 *backup, u32 regiester_num) +{ + u32 i; + + for (i = 0; i < regiester_num; i++) + phy_set_bb_reg(adapt, adda_reg[i], bMaskDWord, backup[i]); +} + +static void reload_mac_registers(struct adapter *adapt, + u32 *mac_reg, u32 *backup) +{ + u32 i; + + for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) { + usb_write8(adapt, mac_reg[i], (u8)backup[i]); + } + usb_write32(adapt, mac_reg[i], backup[i]); +} + +static void path_adda_on(struct adapter *adapt, u32 *adda_reg, + bool is_path_a_on, bool is2t) +{ + u32 path_on; + u32 i; + + path_on = is_path_a_on ? 0x04db25a4 : 0x0b1b25a4; + if (!is2t) { + path_on = 0x0bdb25a0; + phy_set_bb_reg(adapt, adda_reg[0], bMaskDWord, 0x0b1b25a0); + } else { + phy_set_bb_reg(adapt, adda_reg[0], bMaskDWord, path_on); + } + + for (i = 1; i < IQK_ADDA_REG_NUM; i++) + phy_set_bb_reg(adapt, adda_reg[i], bMaskDWord, path_on); +} + +static void mac_setting_calibration(struct adapter *adapt, u32 *mac_reg, u32 *backup) +{ + u32 i = 0; + + usb_write8(adapt, mac_reg[i], 0x3F); + + for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) { + usb_write8(adapt, mac_reg[i], (u8)(backup[i]&(~BIT3))); + } + usb_write8(adapt, mac_reg[i], (u8)(backup[i]&(~BIT5))); +} + +static void path_a_standby(struct adapter *adapt) +{ + + phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x0); + phy_set_bb_reg(adapt, 0x840, bMaskDWord, 0x00010000); + phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000); +} + +static void pi_mode_switch(struct adapter *adapt, bool pi_mode) +{ + u32 mode; + + mode = pi_mode ? 0x01000100 : 0x01000000; + phy_set_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); + phy_set_bb_reg(adapt, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); +} + +static bool simularity_compare(struct adapter *adapt, s32 resulta[][8], + u8 c1, u8 c2) +{ + u32 i, j, diff, sim_bitmap, bound = 0; + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + struct odm_dm_struct *dm_odm = &hal_data->odmpriv; + u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */ + bool result = true; + bool is2t; + s32 tmp1 = 0, tmp2 = 0; + + if ((dm_odm->RFType == ODM_2T2R) || (dm_odm->RFType == ODM_2T3R) || + (dm_odm->RFType == ODM_2T4R)) + is2t = true; + else + is2t = false; + + if (is2t) + bound = 8; + else + bound = 4; + + sim_bitmap = 0; + + for (i = 0; i < bound; i++) { + if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { + if ((resulta[c1][i] & 0x00000200) != 0) + tmp1 = resulta[c1][i] | 0xFFFFFC00; + else + tmp1 = resulta[c1][i]; + + if ((resulta[c2][i] & 0x00000200) != 0) + tmp2 = resulta[c2][i] | 0xFFFFFC00; + else + tmp2 = resulta[c2][i]; + } else { + tmp1 = resulta[c1][i]; + tmp2 = resulta[c2][i]; + } + + diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); + + if (diff > MAX_TOLERANCE) { + if ((i == 2 || i == 6) && !sim_bitmap) { + if (resulta[c1][i] + resulta[c1][i+1] == 0) + final_candidate[(i/4)] = c2; + else if (resulta[c2][i] + resulta[c2][i+1] == 0) + final_candidate[(i/4)] = c1; + else + sim_bitmap = sim_bitmap | (1<<i); + } else { + sim_bitmap = sim_bitmap | (1<<i); + } + } + } + + if (sim_bitmap == 0) { + for (i = 0; i < (bound/4); i++) { + if (final_candidate[i] != 0xFF) { + for (j = i*4; j < (i+1)*4-2; j++) + resulta[3][j] = resulta[final_candidate[i]][j]; + result = false; + } + } + return result; + } else { + if (!(sim_bitmap & 0x03)) { /* path A TX OK */ + for (i = 0; i < 2; i++) + resulta[3][i] = resulta[c1][i]; + } + if (!(sim_bitmap & 0x0c)) { /* path A RX OK */ + for (i = 2; i < 4; i++) + resulta[3][i] = resulta[c1][i]; + } + + if (!(sim_bitmap & 0x30)) { /* path B TX OK */ + for (i = 4; i < 6; i++) + resulta[3][i] = resulta[c1][i]; + } + + if (!(sim_bitmap & 0xc0)) { /* path B RX OK */ + for (i = 6; i < 8; i++) + resulta[3][i] = resulta[c1][i]; + } + return false; + } +} + +static void phy_iq_calibrate(struct adapter *adapt, s32 result[][8], + u8 t, bool is2t) +{ + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + struct odm_dm_struct *dm_odm = &hal_data->odmpriv; + u32 i; + u8 path_a_ok, path_b_ok; + u32 adda_reg[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN}; + + u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + /* since 92C & 92D have the different define in IQK_BB_REG */ + u32 iqk_bb_reg_92c[IQK_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD}; + + u32 retry_count = 9; + if (*(dm_odm->mp_mode) == 1) + retry_count = 9; + else + retry_count = 2; + + if (t == 0) { + + /* Save ADDA parameters, turn Path A ADDA on */ + save_adda_registers(adapt, adda_reg, dm_odm->RFCalibrateInfo.ADDA_backup, + IQK_ADDA_REG_NUM); + save_mac_registers(adapt, iqk_mac_reg, + dm_odm->RFCalibrateInfo.IQK_MAC_backup); + save_adda_registers(adapt, iqk_bb_reg_92c, + dm_odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); + } + + path_adda_on(adapt, adda_reg, true, is2t); + if (t == 0) + dm_odm->RFCalibrateInfo.bRfPiEnable = (u8)phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, + BIT(8)); + + if (!dm_odm->RFCalibrateInfo.bRfPiEnable) { + /* Switch BB to PI mode to do IQ Calibration. */ + pi_mode_switch(adapt, true); + } + + /* BB setting */ + phy_set_bb_reg(adapt, rFPGA0_RFMOD, BIT24, 0x00); + phy_set_bb_reg(adapt, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); + phy_set_bb_reg(adapt, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); + phy_set_bb_reg(adapt, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); + + phy_set_bb_reg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); + phy_set_bb_reg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); + phy_set_bb_reg(adapt, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); + phy_set_bb_reg(adapt, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); + + if (is2t) { + phy_set_bb_reg(adapt, rFPGA0_XA_LSSIParameter, bMaskDWord, + 0x00010000); + phy_set_bb_reg(adapt, rFPGA0_XB_LSSIParameter, bMaskDWord, + 0x00010000); + } + + /* MAC settings */ + mac_setting_calibration(adapt, iqk_mac_reg, + dm_odm->RFCalibrateInfo.IQK_MAC_backup); + + /* Page B init */ + /* AP or IQK */ + phy_set_bb_reg(adapt, rConfig_AntA, bMaskDWord, 0x0f600000); + + if (is2t) + phy_set_bb_reg(adapt, rConfig_AntB, bMaskDWord, 0x0f600000); + + /* IQ calibration setting */ + phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000); + phy_set_bb_reg(adapt, rTx_IQK, bMaskDWord, 0x01007c00); + phy_set_bb_reg(adapt, rRx_IQK, bMaskDWord, 0x81004800); + + for (i = 0; i < retry_count; i++) { + path_a_ok = phy_path_a_iqk(adapt, is2t); + if (path_a_ok == 0x01) { + result[t][0] = (phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A, + bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, + bMaskDWord)&0x3FF0000)>>16; + break; + } + } + + for (i = 0; i < retry_count; i++) { + path_a_ok = phy_path_a_rx_iqk(adapt, is2t); + if (path_a_ok == 0x03) { + result[t][2] = (phy_query_bb_reg(adapt, rRx_Power_Before_IQK_A_2, + bMaskDWord)&0x3FF0000)>>16; + result[t][3] = (phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2, + bMaskDWord)&0x3FF0000)>>16; + break; + } else { + ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("Path A Rx IQK Fail!!\n")); + } + } + + if (0x00 == path_a_ok) { + ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("Path A IQK failed!!\n")); + } + + if (is2t) { + path_a_standby(adapt); + + /* Turn Path B ADDA on */ + path_adda_on(adapt, adda_reg, false, is2t); + + for (i = 0; i < retry_count; i++) { + path_b_ok = phy_path_b_iqk(adapt); + if (path_b_ok == 0x03) { + result[t][4] = (phy_query_bb_reg(adapt, rTx_Power_Before_IQK_B, + bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (phy_query_bb_reg(adapt, rTx_Power_After_IQK_B, + bMaskDWord)&0x3FF0000)>>16; + result[t][6] = (phy_query_bb_reg(adapt, rRx_Power_Before_IQK_B_2, + bMaskDWord)&0x3FF0000)>>16; + result[t][7] = (phy_query_bb_reg(adapt, rRx_Power_After_IQK_B_2, + bMaskDWord)&0x3FF0000)>>16; + break; + } else if (i == (retry_count - 1) && path_b_ok == 0x01) { /* Tx IQK OK */ + result[t][4] = (phy_query_bb_reg(adapt, rTx_Power_Before_IQK_B, + bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (phy_query_bb_reg(adapt, rTx_Power_After_IQK_B, + bMaskDWord)&0x3FF0000)>>16; + } + } + + if (0x00 == path_b_ok) { + ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("Path B IQK failed!!\n")); + } + } + + /* Back to BB mode, load original value */ + phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0); + + if (t != 0) { + if (!dm_odm->RFCalibrateInfo.bRfPiEnable) { + /* Switch back BB to SI mode after + * finish IQ Calibration. + */ + pi_mode_switch(adapt, false); + } + + /* Reload ADDA power saving parameters */ + reload_adda_reg(adapt, adda_reg, dm_odm->RFCalibrateInfo.ADDA_backup, + IQK_ADDA_REG_NUM); + + /* Reload MAC parameters */ + reload_mac_registers(adapt, iqk_mac_reg, + dm_odm->RFCalibrateInfo.IQK_MAC_backup); + + reload_adda_reg(adapt, iqk_bb_reg_92c, dm_odm->RFCalibrateInfo.IQK_BB_backup, + IQK_BB_REG_NUM); + + /* Restore RX initial gain */ + phy_set_bb_reg(adapt, rFPGA0_XA_LSSIParameter, + bMaskDWord, 0x00032ed3); + if (is2t) + phy_set_bb_reg(adapt, rFPGA0_XB_LSSIParameter, + bMaskDWord, 0x00032ed3); + + /* load 0xe30 IQC default value */ + phy_set_bb_reg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + phy_set_bb_reg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + } +} + +static void phy_lc_calibrate(struct adapter *adapt, bool is2t) +{ + u8 tmpreg; + u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal; + + /* Check continuous TX and Packet TX */ + tmpreg = usb_read8(adapt, 0xd03); + + if ((tmpreg&0x70) != 0) + usb_write8(adapt, 0xd03, tmpreg&0x8F); + else + usb_write8(adapt, REG_TXPAUSE, 0xFF); + + if ((tmpreg&0x70) != 0) { + /* 1. Read original RF mode */ + /* Path-A */ + rf_a_mode = phy_query_rf_reg(adapt, RF_PATH_A, RF_AC, + bMask12Bits); + + /* Path-B */ + if (is2t) + rf_b_mode = phy_query_rf_reg(adapt, RF_PATH_B, RF_AC, + bMask12Bits); + + /* 2. Set RF mode = standby mode */ + /* Path-A */ + phy_set_rf_reg(adapt, RF_PATH_A, RF_AC, bMask12Bits, + (rf_a_mode&0x8FFFF)|0x10000); + + /* Path-B */ + if (is2t) + phy_set_rf_reg(adapt, RF_PATH_B, RF_AC, bMask12Bits, + (rf_b_mode&0x8FFFF)|0x10000); + } + + /* 3. Read RF reg18 */ + lc_cal = phy_query_rf_reg(adapt, RF_PATH_A, RF_CHNLBW, bMask12Bits); + + /* 4. Set LC calibration begin bit15 */ + phy_set_rf_reg(adapt, RF_PATH_A, RF_CHNLBW, bMask12Bits, + lc_cal|0x08000); + + msleep(100); + + /* Restore original situation */ + if ((tmpreg&0x70) != 0) { + /* Deal with continuous TX case */ + /* Path-A */ + usb_write8(adapt, 0xd03, tmpreg); + phy_set_rf_reg(adapt, RF_PATH_A, RF_AC, bMask12Bits, rf_a_mode); + + /* Path-B */ + if (is2t) + phy_set_rf_reg(adapt, RF_PATH_B, RF_AC, bMask12Bits, + rf_b_mode); + } else { + /* Deal with Packet TX case */ + usb_write8(adapt, REG_TXPAUSE, 0x00); + } +} + +void rtl88eu_phy_iq_calibrate(struct adapter *adapt, bool recovery) +{ + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + struct odm_dm_struct *dm_odm = &hal_data->odmpriv; + s32 result[4][8]; + u8 i, final, chn_index; + bool pathaok, pathbok; + s32 reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, + reg_ecc; + bool is12simular, is13simular, is23simular; + bool singletone = false, carrier_sup = false; + u32 iqk_bb_reg_92c[IQK_BB_REG_NUM] = { + rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, + rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, + rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, + rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, + rOFDM0_RxIQExtAnta}; + bool is2t; + + is2t = (dm_odm->RFType == ODM_2T2R) ? true : false; + + if (!(dm_odm->SupportAbility & ODM_RF_CALIBRATION)) + return; + + if (singletone || carrier_sup) + return; + + if (recovery) { + ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("phy_iq_calibrate: Return due to recovery!\n")); + reload_adda_reg(adapt, iqk_bb_reg_92c, + dm_odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); + return; + } + + for (i = 0; i < 8; i++) { + result[0][i] = 0; + result[1][i] = 0; + result[2][i] = 0; + if ((i == 0) || (i == 2) || (i == 4) || (i == 6)) + result[3][i] = 0x100; + else + result[3][i] = 0; + } + final = 0xff; + pathaok = false; + pathbok = false; + is12simular = false; + is23simular = false; + is13simular = false; + + for (i = 0; i < 3; i++) { + phy_iq_calibrate(adapt, result, i, is2t); + + if (i == 1) { + is12simular = simularity_compare(adapt, result, 0, 1); + if (is12simular) { + final = 0; + break; + } + } + + if (i == 2) { + is13simular = simularity_compare(adapt, result, 0, 2); + if (is13simular) { + final = 0; + break; + } + is23simular = simularity_compare(adapt, result, 1, 2); + if (is23simular) + final = 1; + else + final = 3; + } + } + + for (i = 0; i < 4; i++) { + reg_e94 = result[i][0]; + reg_e9c = result[i][1]; + reg_ea4 = result[i][2]; + reg_eac = result[i][3]; + reg_eb4 = result[i][4]; + reg_ebc = result[i][5]; + reg_ec4 = result[i][6]; + reg_ecc = result[i][7]; + } + + if (final != 0xff) { + reg_e94 = result[final][0]; + reg_e9c = result[final][1]; + reg_ea4 = result[final][2]; + reg_eac = result[final][3]; + reg_eb4 = result[final][4]; + reg_ebc = result[final][5]; + dm_odm->RFCalibrateInfo.RegE94 = reg_e94; + dm_odm->RFCalibrateInfo.RegE9C = reg_e9c; + dm_odm->RFCalibrateInfo.RegEB4 = reg_eb4; + dm_odm->RFCalibrateInfo.RegEBC = reg_ebc; + reg_ec4 = result[final][6]; + reg_ecc = result[final][7]; + pathaok = true; + pathbok = true; + } else { + ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("IQK: FAIL use default value\n")); + dm_odm->RFCalibrateInfo.RegE94 = 0x100; + dm_odm->RFCalibrateInfo.RegEB4 = 0x100; + dm_odm->RFCalibrateInfo.RegE9C = 0x0; + dm_odm->RFCalibrateInfo.RegEBC = 0x0; + } + if (reg_e94 != 0) + patha_fill_iqk(adapt, pathaok, result, final, + (reg_ea4 == 0)); + if (is2t) { + if (reg_eb4 != 0) + pathb_fill_iqk(adapt, pathbok, result, final, + (reg_ec4 == 0)); + } + + chn_index = get_right_chnl_for_iqk(hal_data->CurrentChannel); + + if (final < 4) { + for (i = 0; i < IQK_Matrix_REG_NUM; i++) + dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[chn_index].Value[0][i] = result[final][i]; + dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[chn_index].bIQKDone = true; + } + + save_adda_registers(adapt, iqk_bb_reg_92c, + dm_odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +} + +void rtl88eu_phy_lc_calibrate(struct adapter *adapt) +{ + bool singletone = false, carrier_sup = false; + u32 timeout = 2000, timecount = 0; + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + struct odm_dm_struct *dm_odm = &hal_data->odmpriv; + + if (!(dm_odm->SupportAbility & ODM_RF_CALIBRATION)) + return; + if (singletone || carrier_sup) + return; + + while (*(dm_odm->pbScanInProcess) && timecount < timeout) { + mdelay(50); + timecount += 50; + } + + dm_odm->RFCalibrateInfo.bLCKInProgress = true; + + if (dm_odm->RFType == ODM_2T2R) { + phy_lc_calibrate(adapt, true); + } else { + /* For 88C 1T1R */ + phy_lc_calibrate(adapt, false); + } + + dm_odm->RFCalibrateInfo.bLCKInProgress = false; +} diff --git a/drivers/staging/rtl8188eu/hal/Hal8188EPwrSeq.c b/drivers/staging/rtl8188eu/hal/pwrseq.c index fc23bf159345..20dce42cee1d 100644 --- a/drivers/staging/rtl8188eu/hal/Hal8188EPwrSeq.c +++ b/drivers/staging/rtl8188eu/hal/pwrseq.c @@ -18,68 +18,84 @@ * ******************************************************************************/ -#include "Hal8188EPwrSeq.h" +#include "pwrseq.h" #include <rtl8188e_hal.h> /* drivers should parse below arrays and do the corresponding actions */ /* 3 Power on Array */ -struct wl_pwr_cfg rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS] = { +struct wl_pwr_cfg rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS + + RTL8188E_TRANS_END_STEPS] = { RTL8188E_TRANS_CARDEMU_TO_ACT RTL8188E_TRANS_END }; /* 3Radio off Array */ -struct wl_pwr_cfg rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_END_STEPS] = { +struct wl_pwr_cfg rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + + RTL8188E_TRANS_END_STEPS] = { RTL8188E_TRANS_ACT_TO_CARDEMU RTL8188E_TRANS_END }; /* 3Card Disable Array */ -struct wl_pwr_cfg rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS] = { - RTL8188E_TRANS_ACT_TO_CARDEMU - RTL8188E_TRANS_CARDEMU_TO_CARDDIS - RTL8188E_TRANS_END +struct wl_pwr_cfg rtl8188E_card_disable_flow + [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + + RTL8188E_TRANS_END_STEPS] = { + RTL8188E_TRANS_ACT_TO_CARDEMU + RTL8188E_TRANS_CARDEMU_TO_CARDDIS + RTL8188E_TRANS_END }; /* 3 Card Enable Array */ -struct wl_pwr_cfg rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS] = { - RTL8188E_TRANS_CARDDIS_TO_CARDEMU - RTL8188E_TRANS_CARDEMU_TO_ACT - RTL8188E_TRANS_END +struct wl_pwr_cfg rtl8188E_card_enable_flow + [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + + RTL8188E_TRANS_END_STEPS] = { + RTL8188E_TRANS_CARDDIS_TO_CARDEMU + RTL8188E_TRANS_CARDEMU_TO_ACT + RTL8188E_TRANS_END }; /* 3Suspend Array */ -struct wl_pwr_cfg rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188E_TRANS_END_STEPS] = { +struct wl_pwr_cfg rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + + RTL8188E_TRANS_END_STEPS] = { RTL8188E_TRANS_ACT_TO_CARDEMU RTL8188E_TRANS_CARDEMU_TO_SUS RTL8188E_TRANS_END }; /* 3 Resume Array */ -struct wl_pwr_cfg rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188E_TRANS_END_STEPS] = { +struct wl_pwr_cfg rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + + RTL8188E_TRANS_END_STEPS] = { RTL8188E_TRANS_SUS_TO_CARDEMU RTL8188E_TRANS_CARDEMU_TO_ACT RTL8188E_TRANS_END }; /* 3HWPDN Array */ -struct wl_pwr_cfg rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS] = { +struct wl_pwr_cfg rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + + RTL8188E_TRANS_END_STEPS] = { RTL8188E_TRANS_ACT_TO_CARDEMU RTL8188E_TRANS_CARDEMU_TO_PDN RTL8188E_TRANS_END }; /* 3 Enter LPS */ -struct wl_pwr_cfg rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS + RTL8188E_TRANS_END_STEPS] = { +struct wl_pwr_cfg rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS + + RTL8188E_TRANS_END_STEPS] = { /* FW behavior */ RTL8188E_TRANS_ACT_TO_LPS RTL8188E_TRANS_END }; /* 3 Leave LPS */ -struct wl_pwr_cfg rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS] = { +struct wl_pwr_cfg rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS + + RTL8188E_TRANS_END_STEPS] = { /* FW behavior */ RTL8188E_TRANS_LPS_TO_ACT RTL8188E_TRANS_END diff --git a/drivers/staging/rtl8188eu/hal/HalPwrSeqCmd.c b/drivers/staging/rtl8188eu/hal/pwrseqcmd.c index caca535ac17d..be0663e93f61 100644 --- a/drivers/staging/rtl8188eu/hal/HalPwrSeqCmd.c +++ b/drivers/staging/rtl8188eu/hal/pwrseqcmd.c @@ -15,36 +15,16 @@ * this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA * - * ******************************************************************************/ -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - HalPwrSeqCmd.c - -Abstract: - Implement HW Power sequence configuration CMD handling routine for Realtek devices. - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2011-10-26 Lucas Modify to be compatible with SD4-CE driver. - 2011-07-07 Roger Create. ---*/ - -#include <HalPwrSeqCmd.h> +#include <pwrseqcmd.h> #include <usb_ops_linux.h> -/* Description: */ -/* This routine deals with the Power Configuration CMDs parsing - * for RTL8723/RTL8188E Series IC. - * Assumption: - * We should follow specific format which was released from HW SD. +/* This routine deals with the Power Configuration CMDs parsing + * for RTL8723/RTL8188E Series IC. */ -u8 HalPwrSeqCmdParsing(struct adapter *padapter, u8 cut_vers, u8 fab_vers, - u8 ifacetype, struct wl_pwr_cfg pwrseqcmd[]) +u8 rtl88eu_pwrseqcmdparsing(struct adapter *padapter, u8 cut_vers, u8 fab_vers, + u8 ifacetype, struct wl_pwr_cfg pwrseqcmd[]) { struct wl_pwr_cfg pwrcfgcmd = {0}; u8 poll_bit = false; @@ -58,7 +38,9 @@ u8 HalPwrSeqCmdParsing(struct adapter *padapter, u8 cut_vers, u8 fab_vers, pwrcfgcmd = pwrseqcmd[aryidx]; RT_TRACE(_module_hal_init_c_ , _drv_info_, - ("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n", + ("rtl88eu_pwrseqcmdparsing: offset(%#x) cut_msk(%#x)" + "fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x)" + "msk(%#x) value(%#x)\n", GET_PWR_CFG_OFFSET(pwrcfgcmd), GET_PWR_CFG_CUT_MASK(pwrcfgcmd), GET_PWR_CFG_FAB_MASK(pwrcfgcmd), @@ -68,37 +50,42 @@ u8 HalPwrSeqCmdParsing(struct adapter *padapter, u8 cut_vers, u8 fab_vers, GET_PWR_CFG_MASK(pwrcfgcmd), GET_PWR_CFG_VALUE(pwrcfgcmd))); - /* 2 Only Handle the command whose FAB, CUT, and Interface are matched */ + /* Only Handle the command whose FAB, CUT, and Interface are matched */ if ((GET_PWR_CFG_FAB_MASK(pwrcfgcmd) & fab_vers) && (GET_PWR_CFG_CUT_MASK(pwrcfgcmd) & cut_vers) && (GET_PWR_CFG_INTF_MASK(pwrcfgcmd) & ifacetype)) { switch (GET_PWR_CFG_CMD(pwrcfgcmd)) { case PWR_CMD_READ: - RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n")); + RT_TRACE(_module_hal_init_c_, _drv_info_, + ("rtl88eu_pwrseqcmdparsing: PWR_CMD_READ\n")); break; case PWR_CMD_WRITE: - RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n")); + RT_TRACE(_module_hal_init_c_, _drv_info_, + ("rtl88eu_pwrseqcmdparsing: PWR_CMD_WRITE\n")); offset = GET_PWR_CFG_OFFSET(pwrcfgcmd); /* Read the value from system register */ value = usb_read8(padapter, offset); value &= ~(GET_PWR_CFG_MASK(pwrcfgcmd)); - value |= (GET_PWR_CFG_VALUE(pwrcfgcmd) & GET_PWR_CFG_MASK(pwrcfgcmd)); + value |= (GET_PWR_CFG_VALUE(pwrcfgcmd) & + GET_PWR_CFG_MASK(pwrcfgcmd)); /* Write the value back to system register */ usb_write8(padapter, offset, value); break; case PWR_CMD_POLLING: - RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n")); + RT_TRACE(_module_hal_init_c_, _drv_info_, + ("rtl88eu_pwrseqcmdparsing: PWR_CMD_POLLING\n")); poll_bit = false; offset = GET_PWR_CFG_OFFSET(pwrcfgcmd); do { - value = usb_read8(padapter, offset); - + value = usb_read8(padapter, offset); value &= GET_PWR_CFG_MASK(pwrcfgcmd); - if (value == (GET_PWR_CFG_VALUE(pwrcfgcmd) & GET_PWR_CFG_MASK(pwrcfgcmd))) + + if (value == (GET_PWR_CFG_VALUE(pwrcfgcmd) & + GET_PWR_CFG_MASK(pwrcfgcmd))) poll_bit = true; else udelay(10); @@ -110,19 +97,22 @@ u8 HalPwrSeqCmdParsing(struct adapter *padapter, u8 cut_vers, u8 fab_vers, } while (!poll_bit); break; case PWR_CMD_DELAY: - RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n")); + RT_TRACE(_module_hal_init_c_, _drv_info_, + ("rtl88eu_pwrseqcmdparsing: PWR_CMD_DELAY\n")); if (GET_PWR_CFG_VALUE(pwrcfgcmd) == PWRSEQ_DELAY_US) udelay(GET_PWR_CFG_OFFSET(pwrcfgcmd)); else udelay(GET_PWR_CFG_OFFSET(pwrcfgcmd)*1000); break; case PWR_CMD_END: - /* When this command is parsed, end the process */ - RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n")); + /* When this command is parsed, end the process */ + RT_TRACE(_module_hal_init_c_, _drv_info_, + ("rtl88eu_pwrseqcmdparsing: PWR_CMD_END\n")); return true; break; default: - RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n")); + RT_TRACE(_module_hal_init_c_, _drv_err_, + ("rtl88eu_pwrseqcmdparsing: Unknown CMD!!\n")); break; } } diff --git a/drivers/staging/rtl8188eu/hal/rf.c b/drivers/staging/rtl8188eu/hal/rf.c new file mode 100644 index 000000000000..c2fac34c8132 --- /dev/null +++ b/drivers/staging/rtl8188eu/hal/rf.c @@ -0,0 +1,318 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + ******************************************************************************/ + +#include <osdep_service.h> +#include <drv_types.h> +#include <phy.h> +#include <rf.h> +#include <rtl8188e_hal.h> + +void rtl88eu_phy_rf6052_set_bandwidth(struct adapter *adapt, + enum ht_channel_width bandwidth) +{ + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + + switch (bandwidth) { + case HT_CHANNEL_WIDTH_20: + hal_data->RfRegChnlVal[0] = ((hal_data->RfRegChnlVal[0] & + 0xfffff3ff) | BIT(10) | BIT(11)); + phy_set_rf_reg(adapt, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, + hal_data->RfRegChnlVal[0]); + break; + case HT_CHANNEL_WIDTH_40: + hal_data->RfRegChnlVal[0] = ((hal_data->RfRegChnlVal[0] & + 0xfffff3ff) | BIT(10)); + phy_set_rf_reg(adapt, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, + hal_data->RfRegChnlVal[0]); + break; + default: + break; + } +} + +void rtl88eu_phy_rf6052_set_cck_txpower(struct adapter *adapt, u8 *powerlevel) +{ + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + struct dm_priv *pdmpriv = &hal_data->dmpriv; + struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv; + u32 tx_agc[2] = {0, 0}, tmpval = 0, pwrtrac_value; + u8 idx1, idx2; + u8 *ptr; + u8 direction; + + + if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) { + tx_agc[RF_PATH_A] = 0x3f3f3f3f; + tx_agc[RF_PATH_B] = 0x3f3f3f3f; + for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) { + tx_agc[idx1] = powerlevel[idx1] | + (powerlevel[idx1]<<8) | + (powerlevel[idx1]<<16) | + (powerlevel[idx1]<<24); + if (tx_agc[idx1] > 0x20 && hal_data->ExternalPA) + tx_agc[idx1] = 0x20; + } + } else { + if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) { + tx_agc[RF_PATH_A] = 0x10101010; + tx_agc[RF_PATH_B] = 0x10101010; + } else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) { + tx_agc[RF_PATH_A] = 0x00000000; + tx_agc[RF_PATH_B] = 0x00000000; + } else { + for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) { + tx_agc[idx1] = powerlevel[idx1] | + (powerlevel[idx1]<<8) | + (powerlevel[idx1]<<16) | + (powerlevel[idx1]<<24); + } + if (hal_data->EEPROMRegulatory == 0) { + tmpval = hal_data->MCSTxPowerLevelOriginalOffset[0][6] + + (hal_data->MCSTxPowerLevelOriginalOffset[0][7]<<8); + tx_agc[RF_PATH_A] += tmpval; + + tmpval = hal_data->MCSTxPowerLevelOriginalOffset[0][14] + + (hal_data->MCSTxPowerLevelOriginalOffset[0][15]<<24); + tx_agc[RF_PATH_B] += tmpval; + } + } + } + for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) { + ptr = (u8 *)(&(tx_agc[idx1])); + for (idx2 = 0; idx2 < 4; idx2++) { + if (*ptr > RF6052_MAX_TX_PWR) + *ptr = RF6052_MAX_TX_PWR; + ptr++; + } + } + rtl88eu_dm_txpower_track_adjust(&hal_data->odmpriv, 1, &direction, + &pwrtrac_value); + + if (direction == 1) { + /* Increase TX power */ + tx_agc[0] += pwrtrac_value; + tx_agc[1] += pwrtrac_value; + } else if (direction == 2) { + /* Decrease TX power */ + tx_agc[0] -= pwrtrac_value; + tx_agc[1] -= pwrtrac_value; + } + + /* rf-A cck tx power */ + tmpval = tx_agc[RF_PATH_A]&0xff; + phy_set_bb_reg(adapt, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); + tmpval = tx_agc[RF_PATH_A]>>8; + phy_set_bb_reg(adapt, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); + + /* rf-B cck tx power */ + tmpval = tx_agc[RF_PATH_B]>>24; + phy_set_bb_reg(adapt, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval); + tmpval = tx_agc[RF_PATH_B]&0x00ffffff; + phy_set_bb_reg(adapt, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); +} + +/* powerbase0 for OFDM rates */ +/* powerbase1 for HT MCS rates */ +static void getpowerbase88e(struct adapter *adapt, u8 *pwr_level_ofdm, + u8 *pwr_level_bw20, u8 *pwr_level_bw40, + u8 channel,u32 *ofdmbase, u32 *mcs_base) +{ + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + u32 powerbase0, powerbase1; + u8 i, powerlevel[2]; + + for (i = 0; i < 2; i++) { + powerbase0 = pwr_level_ofdm[i]; + + powerbase0 = (powerbase0<<24) | (powerbase0<<16) | + (powerbase0<<8) | powerbase0; + *(ofdmbase+i) = powerbase0; + } + for (i = 0; i < hal_data->NumTotalRFPath; i++) { + /* Check HT20 to HT40 diff */ + if (hal_data->CurrentChannelBW == HT_CHANNEL_WIDTH_20) + powerlevel[i] = pwr_level_bw20[i]; + else + powerlevel[i] = pwr_level_bw40[i]; + powerbase1 = powerlevel[i]; + powerbase1 = (powerbase1<<24) | (powerbase1<<16) | + (powerbase1<<8) | powerbase1; + *(mcs_base+i) = powerbase1; + } +} +static void get_rx_power_val_by_reg(struct adapter *adapt, u8 channel, + u8 index, u32 *powerbase0, u32 *powerbase1, + u32 *out_val) +{ + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + struct dm_priv *pdmpriv = &hal_data->dmpriv; + u8 i, chnlGroup = 0, pwr_diff_limit[4], customer_pwr_limit; + s8 pwr_diff = 0; + u32 write_val, customer_limit, rf; + u8 regulatory = hal_data->EEPROMRegulatory; + + /* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */ + + for (rf = 0; rf < 2; rf++) { + u8 j = index + (rf ? 8 : 0); + + switch (regulatory) { + case 0: + chnlGroup = 0; + write_val = hal_data->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] + + ((index < 2) ? powerbase0[rf] : powerbase1[rf]); + break; + case 1: /* Realtek regulatory */ + /* increase power diff defined by Realtek for regulatory */ + if (hal_data->pwrGroupCnt == 1) + chnlGroup = 0; + if (hal_data->pwrGroupCnt >= hal_data->PGMaxGroup) { + if (channel < 3) + chnlGroup = 0; + else if (channel < 6) + chnlGroup = 1; + else if (channel < 9) + chnlGroup = 2; + else if (channel < 12) + chnlGroup = 3; + else if (channel < 14) + chnlGroup = 4; + else if (channel == 14) + chnlGroup = 5; + } + write_val = hal_data->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] + + ((index < 2) ? powerbase0[rf] : powerbase1[rf]); + break; + case 2: /* Better regulatory */ + /* don't increase any power diff */ + write_val = ((index < 2) ? powerbase0[rf] : powerbase1[rf]); + break; + case 3: /* Customer defined power diff. */ + /* increase power diff defined by customer. */ + chnlGroup = 0; + + if (index < 2) + pwr_diff = hal_data->TxPwrLegacyHtDiff[rf][channel-1]; + else if (hal_data->CurrentChannelBW == HT_CHANNEL_WIDTH_20) + pwr_diff = hal_data->TxPwrHt20Diff[rf][channel-1]; + + if (hal_data->CurrentChannelBW == HT_CHANNEL_WIDTH_40) + customer_pwr_limit = hal_data->PwrGroupHT40[rf][channel-1]; + else + customer_pwr_limit = hal_data->PwrGroupHT20[rf][channel-1]; + + if (pwr_diff >= customer_pwr_limit) + pwr_diff = 0; + else + pwr_diff = customer_pwr_limit - pwr_diff; + + for (i = 0; i < 4; i++) { + pwr_diff_limit[i] = (u8)((hal_data->MCSTxPowerLevelOriginalOffset[chnlGroup][j] & + (0x7f << (i * 8))) >> (i * 8)); + + if (pwr_diff_limit[i] > pwr_diff) + pwr_diff_limit[i] = pwr_diff; + } + customer_limit = (pwr_diff_limit[3]<<24) | + (pwr_diff_limit[2]<<16) | + (pwr_diff_limit[1]<<8) | + (pwr_diff_limit[0]); + write_val = customer_limit + ((index < 2) ? powerbase0[rf] : powerbase1[rf]); + break; + default: + chnlGroup = 0; + write_val = hal_data->MCSTxPowerLevelOriginalOffset[chnlGroup][j] + + ((index < 2) ? powerbase0[rf] : powerbase1[rf]); + break; + } +/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */ +/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */ +/* In the future, two mechanism shall be separated from each other and maintained independently. Thanks for Lanhsin's reminder. */ + /* 92d do not need this */ + if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) + write_val = 0x14141414; + else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) + write_val = 0x00000000; + + *(out_val+rf) = write_val; + } +} + +static void write_ofdm_pwr_reg(struct adapter *adapt, u8 index, u32 *pvalue) +{ + u16 regoffset_a[6] = { rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24, + rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04, + rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12 }; + u16 regoffset_b[6] = { rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24, + rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04, + rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12 }; + u8 i, rf, pwr_val[4]; + u32 write_val; + u16 regoffset; + + for (rf = 0; rf < 2; rf++) { + write_val = pvalue[rf]; + for (i = 0; i < 4; i++) { + pwr_val[i] = (u8)((write_val & (0x7f<<(i*8)))>>(i*8)); + if (pwr_val[i] > RF6052_MAX_TX_PWR) + pwr_val[i] = RF6052_MAX_TX_PWR; + } + write_val = (pwr_val[3]<<24) | (pwr_val[2]<<16) | + (pwr_val[1]<<8) | pwr_val[0]; + + if (rf == 0) + regoffset = regoffset_a[index]; + else + regoffset = regoffset_b[index]; + + phy_set_bb_reg(adapt, regoffset, bMaskDWord, write_val); + } +} + +void rtl88eu_phy_rf6052_set_ofdm_txpower(struct adapter *adapt, + u8 *pwr_level_ofdm, + u8 *pwr_level_bw20, + u8 *pwr_level_bw40, u8 channel) +{ + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + u32 write_val[2], powerbase0[2], powerbase1[2], pwrtrac_value; + u8 direction; + u8 index = 0; + + getpowerbase88e(adapt, pwr_level_ofdm, pwr_level_bw20, pwr_level_bw40, + channel, &powerbase0[0], &powerbase1[0]); + + rtl88eu_dm_txpower_track_adjust(&hal_data->odmpriv, 0, &direction, + &pwrtrac_value); + + for (index = 0; index < 6; index++) { + get_rx_power_val_by_reg(adapt, channel, index, + &powerbase0[0], &powerbase1[0], + &write_val[0]); + + if (direction == 1) { + write_val[0] += pwrtrac_value; + write_val[1] += pwrtrac_value; + } else if (direction == 2) { + write_val[0] -= pwrtrac_value; + write_val[1] -= pwrtrac_value; + } + write_ofdm_pwr_reg(adapt, index, &write_val[0]); + } +} diff --git a/drivers/staging/rtl8188eu/hal/rf_cfg.c b/drivers/staging/rtl8188eu/hal/rf_cfg.c new file mode 100644 index 000000000000..ddc2f55fe13f --- /dev/null +++ b/drivers/staging/rtl8188eu/hal/rf_cfg.c @@ -0,0 +1,320 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +#include "odm_precomp.h" + +#include <phy.h> + +static bool check_condition(struct adapter *adapt, const u32 condition) +{ + struct odm_dm_struct *odm = &GET_HAL_DATA(adapt)->odmpriv; + u32 _board = odm->BoardType; + u32 _platform = odm->SupportPlatform; + u32 _interface = odm->SupportInterface; + u32 cond = condition; + + if (condition == 0xCDCDCDCD) + return true; + + cond = condition & 0x000000FF; + if ((_board == cond) && cond != 0x00) + return false; + + cond = condition & 0x0000FF00; + cond = cond >> 8; + if ((_interface & cond) == 0 && cond != 0x07) + return false; + + cond = condition & 0x00FF0000; + cond = cond >> 16; + if ((_platform & cond) == 0 && cond != 0x0F) + return false; + return true; +} + +/* RadioA_1T.TXT */ + +static u32 Array_RadioA_1T_8188E[] = { + 0x000, 0x00030000, + 0x008, 0x00084000, + 0x018, 0x00000407, + 0x019, 0x00000012, + 0x01E, 0x00080009, + 0x01F, 0x00000880, + 0x02F, 0x0001A060, + 0x03F, 0x00000000, + 0x042, 0x000060C0, + 0x057, 0x000D0000, + 0x058, 0x000BE180, + 0x067, 0x00001552, + 0x083, 0x00000000, + 0x0B0, 0x000FF8FC, + 0x0B1, 0x00054400, + 0x0B2, 0x000CCC19, + 0x0B4, 0x00043003, + 0x0B6, 0x0004953E, + 0x0B7, 0x0001C718, + 0x0B8, 0x000060FF, + 0x0B9, 0x00080001, + 0x0BA, 0x00040000, + 0x0BB, 0x00000400, + 0x0BF, 0x000C0000, + 0x0C2, 0x00002400, + 0x0C3, 0x00000009, + 0x0C4, 0x00040C91, + 0x0C5, 0x00099999, + 0x0C6, 0x000000A3, + 0x0C7, 0x00088820, + 0x0C8, 0x00076C06, + 0x0C9, 0x00000000, + 0x0CA, 0x00080000, + 0x0DF, 0x00000180, + 0x0EF, 0x000001A0, + 0x051, 0x0006B27D, + 0xFF0F041F, 0xABCD, + 0x052, 0x0007E4DD, + 0xCDCDCDCD, 0xCDCD, + 0x052, 0x0007E49D, + 0xFF0F041F, 0xDEAD, + 0x053, 0x00000073, + 0x056, 0x00051FF3, + 0x035, 0x00000086, + 0x035, 0x00000186, + 0x035, 0x00000286, + 0x036, 0x00001C25, + 0x036, 0x00009C25, + 0x036, 0x00011C25, + 0x036, 0x00019C25, + 0x0B6, 0x00048538, + 0x018, 0x00000C07, + 0x05A, 0x0004BD00, + 0x019, 0x000739D0, + 0x034, 0x0000ADF3, + 0x034, 0x00009DF0, + 0x034, 0x00008DED, + 0x034, 0x00007DEA, + 0x034, 0x00006DE7, + 0x034, 0x000054EE, + 0x034, 0x000044EB, + 0x034, 0x000034E8, + 0x034, 0x0000246B, + 0x034, 0x00001468, + 0x034, 0x0000006D, + 0x000, 0x00030159, + 0x084, 0x00068200, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0x08E, 0x00065540, + 0x08F, 0x00088000, + 0x0EF, 0x000020A0, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0x000, 0x00010159, + 0x018, 0x0000F407, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x01F, 0x00080003, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x01E, 0x00000001, + 0x01F, 0x00080000, + 0x000, 0x00033E60, +}; + +#define READ_NEXT_PAIR(v1, v2, i) \ +do { \ + i += 2; v1 = array[i]; \ + v2 = array[i+1]; \ +} while (0) + +#define RFREG_OFFSET_MASK 0xfffff +#define B3WIREADDREAALENGTH 0x400 +#define B3WIREDATALENGTH 0x800 +#define BRFSI_RFENV 0x10 + +static void rtl_rfreg_delay(struct adapter *adapt, enum rf_radio_path rfpath,u32 addr, u32 mask, u32 data) +{ + if (addr == 0xfe) { + mdelay(50); + } else if (addr == 0xfd) { + mdelay(5); + } else if (addr == 0xfc) { + mdelay(1); + } else if (addr == 0xfb) { + udelay(50); + } else if (addr == 0xfa) { + udelay(5); + } else if (addr == 0xf9) { + udelay(1); + } else { + phy_set_rf_reg(adapt, rfpath, addr, mask, data); + udelay(1); + } +} + +static void rtl8188e_config_rf_reg(struct adapter *adapt, + u32 addr, u32 data) +{ + u32 content = 0x1000; /*RF Content: radio_a_txt*/ + u32 maskforphyset = (u32)(content & 0xE000); + + rtl_rfreg_delay(adapt, RF90_PATH_A, addr| maskforphyset, + RFREG_OFFSET_MASK, + data); +} + +static bool rtl88e_phy_config_rf_with_headerfile(struct adapter *adapt) +{ + u32 i; + u32 array_len = sizeof(Array_RadioA_1T_8188E)/sizeof(u32); + u32 *array = Array_RadioA_1T_8188E; + + for (i = 0; i < array_len; i += 2) { + u32 v1 = array[i]; + u32 v2 = array[i+1]; + + if (v1 < 0xCDCDCDCD) { + rtl8188e_config_rf_reg(adapt, v1, v2); + continue; + } else { + if (!check_condition(adapt, array[i])) { + READ_NEXT_PAIR(v1, v2, i); + while (v2 != 0xDEAD && v2 != 0xCDEF && + v2 != 0xCDCD && i < array_len - 2) + READ_NEXT_PAIR(v1, v2, i); + i -= 2; + } else { + READ_NEXT_PAIR(v1, v2, i); + while (v2 != 0xDEAD && v2 != 0xCDEF && + v2 != 0xCDCD && i < array_len - 2) { + rtl8188e_config_rf_reg(adapt, v1, v2); + READ_NEXT_PAIR(v1, v2, i); + } + + while (v2 != 0xDEAD && i < array_len - 2) + READ_NEXT_PAIR(v1, v2, i); + } + } + } + return true; +} + +static bool rf6052_conf_para(struct adapter *adapt) +{ + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + u32 u4val = 0; + u8 rfpath; + bool rtstatus = true; + struct bb_reg_def *pphyreg; + + for (rfpath = 0; rfpath < hal_data->NumTotalRFPath; rfpath++) { + pphyreg = &hal_data->PHYRegDef[rfpath]; + + switch (rfpath) { + case RF90_PATH_A: + case RF90_PATH_C: + u4val = phy_query_bb_reg(adapt, pphyreg->rfintfs, + BRFSI_RFENV); + break; + case RF90_PATH_B: + case RF90_PATH_D: + u4val = phy_query_bb_reg(adapt, pphyreg->rfintfs, + BRFSI_RFENV << 16); + break; + } + + phy_set_bb_reg(adapt, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); + udelay(1); + + phy_set_bb_reg(adapt, pphyreg->rfintfo, BRFSI_RFENV, 0x1); + udelay(1); + + phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, + B3WIREADDREAALENGTH, 0x0); + udelay(1); + + phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, + B3WIREDATALENGTH, 0x0); + udelay(1); + + switch (rfpath) { + case RF90_PATH_A: + rtstatus = rtl88e_phy_config_rf_with_headerfile(adapt); + break; + case RF90_PATH_B: + rtstatus = rtl88e_phy_config_rf_with_headerfile(adapt); + break; + case RF90_PATH_C: + break; + case RF90_PATH_D: + break; + } + + switch (rfpath) { + case RF90_PATH_A: + case RF90_PATH_C: + phy_set_bb_reg(adapt, pphyreg->rfintfs, + BRFSI_RFENV, u4val); + break; + case RF90_PATH_B: + case RF90_PATH_D: + phy_set_bb_reg(adapt, pphyreg->rfintfs, + BRFSI_RFENV << 16, u4val); + break; + } + + if (rtstatus != true) + return false; + } + + return rtstatus; +} + +static bool rtl88e_phy_rf6052_config(struct adapter *adapt) +{ + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + + if (hal_data->rf_type == RF_1T1R) + hal_data->NumTotalRFPath = 1; + else + hal_data->NumTotalRFPath = 2; + + return rf6052_conf_para(adapt); +} + +bool rtl88eu_phy_rf_config(struct adapter *adapt) +{ + return rtl88e_phy_rf6052_config(adapt); +} diff --git a/drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c b/drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c index fbf70f6a0151..d6fe5e6aa4f4 100644 --- a/drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c +++ b/drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c @@ -23,7 +23,7 @@ #include <linux/vmalloc.h> #include <drv_types.h> #include <rtw_efuse.h> - +#include <phy.h> #include <rtl8188e_hal.h> #include <rtw_iol.h> @@ -99,216 +99,8 @@ s32 rtl8188e_iol_efuse_patch(struct adapter *padapter) return result; } -static s32 iol_ioconfig(struct adapter *padapter, u8 iocfg_bndy) -{ - s32 rst = _SUCCESS; - - usb_write8(padapter, REG_TDECTRL+1, iocfg_bndy); - rst = iol_execute(padapter, CMD_IOCONFIG); - return rst; -} - -static int rtl8188e_IOL_exec_cmds_sync(struct adapter *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt) -{ - struct pkt_attrib *pattrib = &xmit_frame->attrib; - u8 i; - int ret = _FAIL; - - if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS) - goto exit; - if (rtw_usb_bulk_size_boundary(adapter, TXDESC_SIZE+pattrib->last_txcmdsz)) { - if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS) - goto exit; - } - - dump_mgntframe_and_wait(adapter, xmit_frame, max_wating_ms); - - iol_mode_enable(adapter, 1); - for (i = 0; i < bndy_cnt; i++) { - u8 page_no = 0; - page_no = i*2; - ret = iol_ioconfig(adapter, page_no); - if (ret != _SUCCESS) - break; - } - iol_mode_enable(adapter, 0); -exit: - /* restore BCN_HEAD */ - usb_write8(adapter, REG_TDECTRL+1, 0); - return ret; -} - -void rtw_IOL_cmd_tx_pkt_buf_dump(struct adapter *Adapter, int data_len) -{ - u32 fifo_data, reg_140; - u32 addr, rstatus, loop = 0; - u16 data_cnts = (data_len/8)+1; - u8 *pbuf = vzalloc(data_len+10); - DBG_88E("###### %s ######\n", __func__); - - usb_write8(Adapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT); - if (pbuf) { - for (addr = 0; addr < data_cnts; addr++) { - usb_write32(Adapter, 0x140, addr); - msleep(1); - loop = 0; - do { - rstatus = (reg_140 = usb_read32(Adapter, REG_PKTBUF_DBG_CTRL)&BIT24); - if (rstatus) { - fifo_data = usb_read32(Adapter, REG_PKTBUF_DBG_DATA_L); - memcpy(pbuf+(addr*8), &fifo_data, 4); - - fifo_data = usb_read32(Adapter, REG_PKTBUF_DBG_DATA_H); - memcpy(pbuf+(addr*8+4), &fifo_data, 4); - } - msleep(1); - } while (!rstatus && (loop++ < 10)); - } - rtw_IOL_cmd_buf_dump(Adapter, data_len, pbuf); - vfree(pbuf); - } - DBG_88E("###### %s ######\n", __func__); -} - -static void _FWDownloadEnable(struct adapter *padapter, bool enable) -{ - u8 tmp; - - if (enable) { - /* MCU firmware download enable. */ - tmp = usb_read8(padapter, REG_MCUFWDL); - usb_write8(padapter, REG_MCUFWDL, tmp | 0x01); - - /* 8051 reset */ - tmp = usb_read8(padapter, REG_MCUFWDL+2); - usb_write8(padapter, REG_MCUFWDL+2, tmp&0xf7); - } else { - /* MCU firmware download disable. */ - tmp = usb_read8(padapter, REG_MCUFWDL); - usb_write8(padapter, REG_MCUFWDL, tmp&0xfe); - - /* Reserved for fw extension. */ - usb_write8(padapter, REG_MCUFWDL+1, 0x00); - } -} - #define MAX_REG_BOLCK_SIZE 196 -static int _BlockWrite(struct adapter *padapter, void *buffer, u32 buffSize) -{ - int ret = _SUCCESS; - u32 blockSize_p1 = 4; /* (Default) Phase #1 : PCI muse use 4-byte write to download FW */ - u32 blockSize_p2 = 8; /* Phase #2 : Use 8-byte, if Phase#1 use big size to write FW. */ - u32 blockSize_p3 = 1; /* Phase #3 : Use 1-byte, the remnant of FW image. */ - u32 blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0; - u32 remainSize_p1 = 0, remainSize_p2 = 0; - u8 *bufferPtr = (u8 *)buffer; - u32 i = 0, offset = 0; - - blockSize_p1 = MAX_REG_BOLCK_SIZE; - - /* 3 Phase #1 */ - blockCount_p1 = buffSize / blockSize_p1; - remainSize_p1 = buffSize % blockSize_p1; - - if (blockCount_p1) { - RT_TRACE(_module_hal_init_c_, _drv_notice_, - ("_BlockWrite: [P1] buffSize(%d) blockSize_p1(%d) blockCount_p1(%d) remainSize_p1(%d)\n", - buffSize, blockSize_p1, blockCount_p1, remainSize_p1)); - } - - for (i = 0; i < blockCount_p1; i++) { - ret = usb_writeN(padapter, (FW_8188E_START_ADDRESS + i * blockSize_p1), blockSize_p1, (bufferPtr + i * blockSize_p1)); - if (ret == _FAIL) - goto exit; - } - - /* 3 Phase #2 */ - if (remainSize_p1) { - offset = blockCount_p1 * blockSize_p1; - - blockCount_p2 = remainSize_p1/blockSize_p2; - remainSize_p2 = remainSize_p1%blockSize_p2; - - if (blockCount_p2) { - RT_TRACE(_module_hal_init_c_, _drv_notice_, - ("_BlockWrite: [P2] buffSize_p2(%d) blockSize_p2(%d) blockCount_p2(%d) remainSize_p2(%d)\n", - (buffSize-offset), blockSize_p2 , blockCount_p2, remainSize_p2)); - } - - for (i = 0; i < blockCount_p2; i++) { - ret = usb_writeN(padapter, (FW_8188E_START_ADDRESS + offset + i*blockSize_p2), blockSize_p2, (bufferPtr + offset + i*blockSize_p2)); - - if (ret == _FAIL) - goto exit; - } - } - - /* 3 Phase #3 */ - if (remainSize_p2) { - offset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2); - - blockCount_p3 = remainSize_p2 / blockSize_p3; - - RT_TRACE(_module_hal_init_c_, _drv_notice_, - ("_BlockWrite: [P3] buffSize_p3(%d) blockSize_p3(%d) blockCount_p3(%d)\n", - (buffSize-offset), blockSize_p3, blockCount_p3)); - - for (i = 0; i < blockCount_p3; i++) { - ret = usb_write8(padapter, (FW_8188E_START_ADDRESS + offset + i), *(bufferPtr + offset + i)); - - if (ret == _FAIL) - goto exit; - } - } - -exit: - return ret; -} - -static int _PageWrite(struct adapter *padapter, u32 page, void *buffer, u32 size) -{ - u8 value8; - u8 u8Page = (u8)(page & 0x07); - - value8 = (usb_read8(padapter, REG_MCUFWDL+2) & 0xF8) | u8Page; - usb_write8(padapter, REG_MCUFWDL+2, value8); - - return _BlockWrite(padapter, buffer, size); -} - -static int _WriteFW(struct adapter *padapter, void *buffer, u32 size) -{ - /* Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. */ - /* We can remove _ReadChipVersion from ReadpadapterInfo8192C later. */ - int ret = _SUCCESS; - u32 pageNums, remainSize; - u32 page, offset; - u8 *bufferPtr = (u8 *)buffer; - - pageNums = size / MAX_PAGE_SIZE; - remainSize = size % MAX_PAGE_SIZE; - - for (page = 0; page < pageNums; page++) { - offset = page * MAX_PAGE_SIZE; - ret = _PageWrite(padapter, page, bufferPtr+offset, MAX_PAGE_SIZE); - - if (ret == _FAIL) - goto exit; - } - if (remainSize) { - offset = pageNums * MAX_PAGE_SIZE; - page = pageNums; - ret = _PageWrite(padapter, page, bufferPtr+offset, remainSize); - - if (ret == _FAIL) - goto exit; - } - RT_TRACE(_module_hal_init_c_, _drv_info_, ("_WriteFW Done- for Normal chip.\n")); -exit: - return ret; -} - void _8051Reset88E(struct adapter *padapter) { u8 u1bTmp; @@ -319,167 +111,6 @@ void _8051Reset88E(struct adapter *padapter) DBG_88E("=====> _8051Reset88E(): 8051 reset success .\n"); } -static s32 _FWFreeToGo(struct adapter *padapter) -{ - u32 counter = 0; - u32 value32; - - /* polling CheckSum report */ - do { - value32 = usb_read32(padapter, REG_MCUFWDL); - if (value32 & FWDL_ChkSum_rpt) - break; - } while (counter++ < POLLING_READY_TIMEOUT_COUNT); - - if (counter >= POLLING_READY_TIMEOUT_COUNT) { - DBG_88E("%s: chksum report fail! REG_MCUFWDL:0x%08x\n", __func__, value32); - return _FAIL; - } - DBG_88E("%s: Checksum report OK! REG_MCUFWDL:0x%08x\n", __func__, value32); - - value32 = usb_read32(padapter, REG_MCUFWDL); - value32 |= MCUFWDL_RDY; - value32 &= ~WINTINI_RDY; - usb_write32(padapter, REG_MCUFWDL, value32); - - _8051Reset88E(padapter); - - /* polling for FW ready */ - counter = 0; - do { - value32 = usb_read32(padapter, REG_MCUFWDL); - if (value32 & WINTINI_RDY) { - DBG_88E("%s: Polling FW ready success!! REG_MCUFWDL:0x%08x\n", __func__, value32); - return _SUCCESS; - } - udelay(5); - } while (counter++ < POLLING_READY_TIMEOUT_COUNT); - - DBG_88E("%s: Polling FW ready fail!! REG_MCUFWDL:0x%08x\n", __func__, value32); - return _FAIL; -} - -#define IS_FW_81xxC(padapter) (((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0) - -static int load_firmware(struct rt_firmware *pFirmware, struct device *device) -{ - int rtstatus = _SUCCESS; - const struct firmware *fw; - const char fw_name[] = "rtlwifi/rtl8188eufw.bin"; - - if (request_firmware(&fw, fw_name, device)) { - rtstatus = _FAIL; - goto exit; - } - if (!fw) { - pr_err("Firmware %s not available\n", fw_name); - rtstatus = _FAIL; - goto exit; - } - if (fw->size > FW_8188E_SIZE) { - rtstatus = _FAIL; - RT_TRACE(_module_hal_init_c_, _drv_err_, - ("Firmware size exceed 0x%X. Check it.\n", - FW_8188E_SIZE)); - goto exit; - } - - pFirmware->szFwBuffer = kzalloc(FW_8188E_SIZE, GFP_KERNEL); - if (!pFirmware->szFwBuffer) { - rtstatus = _FAIL; - goto exit; - } - memcpy(pFirmware->szFwBuffer, fw->data, fw->size); - pFirmware->ulFwLength = fw->size; - release_firmware(fw); - - DBG_88E_LEVEL(_drv_info_, - "+%s: !bUsedWoWLANFw, FmrmwareLen:%d+\n", __func__, - pFirmware->ulFwLength); -exit: - return rtstatus; -} - -s32 rtl8188e_FirmwareDownload(struct adapter *padapter) -{ - s32 rtStatus = _SUCCESS; - u8 writeFW_retry = 0; - u32 fwdl_start_time; - struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter); - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct device *device = dvobj_to_dev(dvobj); - struct rt_firmware_hdr *pFwHdr = NULL; - u8 *pFirmwareBuf; - u32 FirmwareLen; - static int log_version; - - RT_TRACE(_module_hal_init_c_, _drv_info_, ("+%s\n", __func__)); - if (!dvobj->firmware.szFwBuffer) - rtStatus = load_firmware(&dvobj->firmware, device); - if (rtStatus == _FAIL) { - dvobj->firmware.szFwBuffer = NULL; - goto Exit; - } - pFirmwareBuf = dvobj->firmware.szFwBuffer; - FirmwareLen = dvobj->firmware.ulFwLength; - - /* To Check Fw header. Added by tynli. 2009.12.04. */ - pFwHdr = (struct rt_firmware_hdr *)dvobj->firmware.szFwBuffer; - - pHalData->FirmwareVersion = le16_to_cpu(pFwHdr->Version); - pHalData->FirmwareSubVersion = pFwHdr->Subversion; - pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->Signature); - - if (!log_version++) - pr_info("%sFirmware Version %d, SubVersion %d, Signature 0x%x\n", - DRIVER_PREFIX, pHalData->FirmwareVersion, - pHalData->FirmwareSubVersion, pHalData->FirmwareSignature); - - if (IS_FW_HEADER_EXIST(pFwHdr)) { - /* Shift 32 bytes for FW header */ - pFirmwareBuf = pFirmwareBuf + 32; - FirmwareLen = FirmwareLen - 32; - } - - /* Suggested by Filen. If 8051 is running in RAM code, driver should inform Fw to reset by itself, */ - /* or it will cause download Fw fail. 2010.02.01. by tynli. */ - if (usb_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) { /* 8051 RAM code */ - usb_write8(padapter, REG_MCUFWDL, 0x00); - _8051Reset88E(padapter); - } - - _FWDownloadEnable(padapter, true); - fwdl_start_time = jiffies; - while (1) { - /* reset the FWDL chksum */ - usb_write8(padapter, REG_MCUFWDL, usb_read8(padapter, REG_MCUFWDL) | FWDL_ChkSum_rpt); - - rtStatus = _WriteFW(padapter, pFirmwareBuf, FirmwareLen); - - if (rtStatus == _SUCCESS || - (rtw_get_passing_time_ms(fwdl_start_time) > 500 && writeFW_retry++ >= 3)) - break; - - DBG_88E("%s writeFW_retry:%u, time after fwdl_start_time:%ums\n", - __func__, writeFW_retry, rtw_get_passing_time_ms(fwdl_start_time) - ); - } - _FWDownloadEnable(padapter, false); - if (_SUCCESS != rtStatus) { - DBG_88E("DL Firmware failed!\n"); - goto Exit; - } - - rtStatus = _FWFreeToGo(padapter); - if (_SUCCESS != rtStatus) { - DBG_88E("DL Firmware failed!\n"); - goto Exit; - } - RT_TRACE(_module_hal_init_c_, _drv_info_, ("Firmware is ready to run!\n")); -Exit: - return rtStatus; -} - void rtl8188e_InitializeFirmwareVars(struct adapter *padapter) { struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter); @@ -590,8 +221,8 @@ void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc) pHalFunc->read_chip_version = &rtl8188e_read_chip_version; - pHalFunc->set_bwmode_handler = &PHY_SetBWMode8188E; - pHalFunc->set_channel_handler = &PHY_SwChnl8188E; + pHalFunc->set_bwmode_handler = &phy_set_bw_mode; + pHalFunc->set_channel_handler = &phy_sw_chnl; pHalFunc->hal_dm_watchdog = &rtl8188e_HalDmWatchDog; @@ -599,18 +230,14 @@ void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc) pHalFunc->AntDivBeforeLinkHandler = &AntDivBeforeLink8188E; pHalFunc->AntDivCompareHandler = &AntDivCompare8188E; - pHalFunc->read_bbreg = &rtl8188e_PHY_QueryBBReg; - pHalFunc->write_bbreg = &rtl8188e_PHY_SetBBReg; - pHalFunc->read_rfreg = &rtl8188e_PHY_QueryRFReg; - pHalFunc->write_rfreg = &rtl8188e_PHY_SetRFReg; + pHalFunc->read_rfreg = &phy_query_rf_reg; + pHalFunc->write_rfreg = &phy_set_rf_reg; pHalFunc->sreset_init_value = &sreset_init_value; pHalFunc->sreset_get_wifi_status = &sreset_get_wifi_status; pHalFunc->SetHalODMVarHandler = &rtl8188e_SetHalODMVar; - pHalFunc->IOL_exec_cmds_sync = &rtl8188e_IOL_exec_cmds_sync; - pHalFunc->hal_notch_filter = &hal_notch_filter_8188e; } @@ -1077,21 +704,3 @@ void Hal_ReadThermalMeter_88E(struct adapter *Adapter, u8 *PROMContent, bool Aut } DBG_88E("ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter); } - -/* This function is used only for 92C to set REG_BCN_CTRL(0x550) register. */ -/* We just reserve the value of the register in variable pHalData->RegBcnCtrlVal and then operate */ -/* the value of the register via atomic operation. */ -/* This prevents from race condition when setting this register. */ -/* The value of pHalData->RegBcnCtrlVal is initialized in HwConfigureRTL8192CE() function. */ - -void SetBcnCtrlReg(struct adapter *padapter, u8 SetBits, u8 ClearBits) -{ - struct hal_data_8188e *pHalData; - - pHalData = GET_HAL_DATA(padapter); - - pHalData->RegBcnCtrlVal |= SetBits; - pHalData->RegBcnCtrlVal &= ~ClearBits; - - usb_write8(padapter, REG_BCN_CTRL, (u8)pHalData->RegBcnCtrlVal); -} diff --git a/drivers/staging/rtl8188eu/hal/rtl8188e_phycfg.c b/drivers/staging/rtl8188eu/hal/rtl8188e_phycfg.c deleted file mode 100644 index 9f016a5401d8..000000000000 --- a/drivers/staging/rtl8188eu/hal/rtl8188e_phycfg.c +++ /dev/null @@ -1,936 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#define _RTL8188E_PHYCFG_C_ - -#include <osdep_service.h> -#include <drv_types.h> -#include <rtw_iol.h> -#include <rtl8188e_hal.h> - -/*---------------------------Define Local Constant---------------------------*/ -/* Channel switch:The size of command tables for switch channel*/ -#define MAX_PRECMD_CNT 16 -#define MAX_RFDEPENDCMD_CNT 16 -#define MAX_POSTCMD_CNT 16 - -#define MAX_DOZE_WAITING_TIMES_9x 64 - -/*---------------------------Define Local Constant---------------------------*/ - - -/*------------------------Define global variable-----------------------------*/ - -/*------------------------Define local variable------------------------------*/ - - -/*--------------------Define export function prototype-----------------------*/ -/* Please refer to header file */ -/*--------------------Define export function prototype-----------------------*/ - -/*----------------------------Function Body----------------------------------*/ -/* */ -/* 1. BB register R/W API */ -/* */ - -/** -* Function: phy_CalculateBitShift -* -* OverView: Get shifted position of the BitMask -* -* Input: -* u32 BitMask, -* -* Output: none -* Return: u32 Return the shift bit bit position of the mask -*/ -static u32 phy_CalculateBitShift(u32 BitMask) -{ - u32 i; - - for (i = 0; i <= 31; i++) { - if (((BitMask>>i) & 0x1) == 1) - break; - } - return i; -} - -/** -* Function: PHY_QueryBBReg -* -* OverView: Read "sepcific bits" from BB register -* -* Input: -* struct adapter *Adapter, -* u32 RegAddr, The target address to be readback -* u32 BitMask The target bit position in the target address -* to be readback -* Output: None -* Return: u32 Data The readback register value -* Note: This function is equal to "GetRegSetting" in PHY programming guide -*/ -u32 -rtl8188e_PHY_QueryBBReg( - struct adapter *Adapter, - u32 RegAddr, - u32 BitMask - ) -{ - u32 ReturnValue = 0, OriginalValue, BitShift; - - OriginalValue = usb_read32(Adapter, RegAddr); - BitShift = phy_CalculateBitShift(BitMask); - ReturnValue = (OriginalValue & BitMask) >> BitShift; - return ReturnValue; -} - - -/** -* Function: PHY_SetBBReg -* -* OverView: Write "Specific bits" to BB register (page 8~) -* -* Input: -* struct adapter *Adapter, -* u32 RegAddr, The target address to be modified -* u32 BitMask The target bit position in the target address -* to be modified -* u32 Data The new register value in the target bit position -* of the target address -* -* Output: None -* Return: None -* Note: This function is equal to "PutRegSetting" in PHY programming guide -*/ - -void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data) -{ - u32 OriginalValue, BitShift; - - if (BitMask != bMaskDWord) { /* if not "double word" write */ - OriginalValue = usb_read32(Adapter, RegAddr); - BitShift = phy_CalculateBitShift(BitMask); - Data = ((OriginalValue & (~BitMask)) | (Data << BitShift)); - } - - usb_write32(Adapter, RegAddr, Data); -} - - -/* */ -/* 2. RF register R/W API */ -/* */ -/** -* Function: phy_RFSerialRead -* -* OverView: Read regster from RF chips -* -* Input: -* struct adapter *Adapter, -* enum rf_radio_path eRFPath, Radio path of A/B/C/D -* u32 Offset, The target address to be read -* -* Output: None -* Return: u32 reback value -* Note: Threre are three types of serial operations: -* 1. Software serial write -* 2. Hardware LSSI-Low Speed Serial Interface -* 3. Hardware HSSI-High speed -* serial write. Driver need to implement (1) and (2). -* This function is equal to the combination of RF_ReadReg() and RFLSSIRead() -*/ -static u32 -phy_RFSerialRead( - struct adapter *Adapter, - enum rf_radio_path eRFPath, - u32 Offset - ) -{ - u32 retValue = 0; - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - struct bb_reg_def *pPhyReg = &pHalData->PHYRegDef[eRFPath]; - u32 NewOffset; - u32 tmplong, tmplong2; - u8 RfPiEnable = 0; - /* */ - /* Make sure RF register offset is correct */ - /* */ - Offset &= 0xff; - - /* */ - /* Switch page for 8256 RF IC */ - /* */ - NewOffset = Offset; - - /* For 92S LSSI Read RFLSSIRead */ - /* For RF A/B write 0x824/82c(does not work in the future) */ - /* We must use 0x824 for RF A and B to execute read trigger */ - tmplong = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord); - if (eRFPath == RF_PATH_A) - tmplong2 = tmplong; - else - tmplong2 = PHY_QueryBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord); - - tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; /* T65 RF */ - - PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge)); - udelay(10);/* PlatformStallExecution(10); */ - - PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2); - udelay(100);/* PlatformStallExecution(100); */ - - udelay(10);/* PlatformStallExecution(10); */ - - if (eRFPath == RF_PATH_A) - RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT8); - else if (eRFPath == RF_PATH_B) - RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1, BIT8); - - if (RfPiEnable) { /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */ - retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData); - } else { /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */ - retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); - } - return retValue; -} - -/** -* Function: phy_RFSerialWrite -* -* OverView: Write data to RF register (page 8~) -* -* Input: -* struct adapter *Adapter, -* enum rf_radio_path eRFPath, Radio path of A/B/C/D -* u32 Offset, The target address to be read -* u32 Data The new register Data in the target bit position -* of the target to be read -* -* Output: None -* Return: None -* Note: Threre are three types of serial operations: -* 1. Software serial write -* 2. Hardware LSSI-Low Speed Serial Interface -* 3. Hardware HSSI-High speed -* serial write. Driver need to implement (1) and (2). -* This function is equal to the combination of RF_ReadReg() and RFLSSIRead() - * - * Note: For RF8256 only - * The total count of RTL8256(Zebra4) register is around 36 bit it only employs - * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10]) - * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration - * programming guide" for more details. - * Thus, we define a sub-finction for RTL8526 register address conversion - * =========================================================== - * Register Mode RegCTL[1] RegCTL[0] Note - * (Reg00[12]) (Reg00[10]) - * =========================================================== - * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf) - * ------------------------------------------------------------------ - * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf) - * ------------------------------------------------------------------ - * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) - * ------------------------------------------------------------------ - * - * 2008/09/02 MH Add 92S RF definition - * - * - * -*/ -static void -phy_RFSerialWrite( - struct adapter *Adapter, - enum rf_radio_path eRFPath, - u32 Offset, - u32 Data - ) -{ - u32 DataAndAddr = 0; - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - struct bb_reg_def *pPhyReg = &pHalData->PHYRegDef[eRFPath]; - u32 NewOffset; - - - /* 2009/06/17 MH We can not execute IO for power save or other accident mode. */ - - Offset &= 0xff; - - /* */ - /* Switch page for 8256 RF IC */ - /* */ - NewOffset = Offset; - - /* */ - /* Put write addr in [5:0] and write data in [31:16] */ - /* */ - DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; /* T65 RF */ - - /* */ - /* Write Operation */ - /* */ - PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); -} - -/** -* Function: PHY_QueryRFReg -* -* OverView: Query "Specific bits" to RF register (page 8~) -* -* Input: -* struct adapter *Adapter, -* enum rf_radio_path eRFPath, Radio path of A/B/C/D -* u32 RegAddr, The target address to be read -* u32 BitMask The target bit position in the target address -* to be read -* -* Output: None -* Return: u32 Readback value -* Note: This function is equal to "GetRFRegSetting" in PHY programming guide -*/ -u32 rtl8188e_PHY_QueryRFReg(struct adapter *Adapter, enum rf_radio_path eRFPath, - u32 RegAddr, u32 BitMask) -{ - u32 Original_Value, Readback_Value, BitShift; - - Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr); - - BitShift = phy_CalculateBitShift(BitMask); - Readback_Value = (Original_Value & BitMask) >> BitShift; - return Readback_Value; -} - -/** -* Function: PHY_SetRFReg -* -* OverView: Write "Specific bits" to RF register (page 8~) -* -* Input: -* struct adapter *Adapter, -* enum rf_radio_path eRFPath, Radio path of A/B/C/D -* u32 RegAddr, The target address to be modified -* u32 BitMask The target bit position in the target address -* to be modified -* u32 Data The new register Data in the target bit position -* of the target address -* -* Output: None -* Return: None -* Note: This function is equal to "PutRFRegSetting" in PHY programming guide -*/ -void -rtl8188e_PHY_SetRFReg( - struct adapter *Adapter, - enum rf_radio_path eRFPath, - u32 RegAddr, - u32 BitMask, - u32 Data - ) -{ - u32 Original_Value, BitShift; - - /* RF data is 12 bits only */ - if (BitMask != bRFRegOffsetMask) { - Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr); - BitShift = phy_CalculateBitShift(BitMask); - Data = ((Original_Value & (~BitMask)) | (Data << BitShift)); - } - - phy_RFSerialWrite(Adapter, eRFPath, RegAddr, Data); -} - -/* */ -/* 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. */ -/* */ - -/*----------------------------------------------------------------------------- - * Function: PHY_MACConfig8192C - * - * Overview: Condig MAC by header file or parameter file. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 08/12/2008 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -s32 PHY_MACConfig8188E(struct adapter *Adapter) -{ - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - int rtStatus = _SUCCESS; - - /* */ - /* Config MAC */ - /* */ - if (HAL_STATUS_FAILURE == ODM_ConfigMACWithHeaderFile(&pHalData->odmpriv)) - rtStatus = _FAIL; - - /* 2010.07.13 AMPDU aggregation number B */ - usb_write16(Adapter, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); - - return rtStatus; -} - -/** -* Function: phy_InitBBRFRegisterDefinition -* -* OverView: Initialize Register definition offset for Radio Path A/B/C/D -* -* Input: -* struct adapter *Adapter, -* -* Output: None -* Return: None -* Note: The initialization value is constant and it should never be changes -*/ -static void -phy_InitBBRFRegisterDefinition( - struct adapter *Adapter -) -{ - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - - /* RF Interface Sowrtware Control */ - pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */ - pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ - pHalData->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;/* 16 LSBs if read 32-bit from 0x874 */ - pHalData->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;/* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ - - /* RF Interface Readback Value */ - pHalData->PHYRegDef[RF_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; /* 16 LSBs if read 32-bit from 0x8E0 */ - pHalData->PHYRegDef[RF_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;/* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */ - pHalData->PHYRegDef[RF_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;/* 16 LSBs if read 32-bit from 0x8E4 */ - pHalData->PHYRegDef[RF_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;/* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */ - - /* RF Interface Output (and Enable) */ - pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */ - pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x864 */ - - /* RF Interface (Output and) Enable */ - pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ - pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ - - /* Addr of LSSI. Wirte RF register by driver */ - pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */ - pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; - - /* RF parameter */ - pHalData->PHYRegDef[RF_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; /* BB Band Select */ - pHalData->PHYRegDef[RF_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; - pHalData->PHYRegDef[RF_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; - pHalData->PHYRegDef[RF_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; - - /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ - pHalData->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */ - pHalData->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */ - pHalData->PHYRegDef[RF_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */ - pHalData->PHYRegDef[RF_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */ - - /* Tranceiver A~D HSSI Parameter-1 */ - pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; /* wire control parameter1 */ - pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; /* wire control parameter1 */ - - /* Tranceiver A~D HSSI Parameter-2 */ - pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /* wire control parameter2 */ - pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; /* wire control parameter2 */ - - /* RF switch Control */ - pHalData->PHYRegDef[RF_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; /* TR/Ant switch control */ - pHalData->PHYRegDef[RF_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; - pHalData->PHYRegDef[RF_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; - pHalData->PHYRegDef[RF_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; - - /* AGC control 1 */ - pHalData->PHYRegDef[RF_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; - pHalData->PHYRegDef[RF_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; - pHalData->PHYRegDef[RF_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; - pHalData->PHYRegDef[RF_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; - - /* AGC control 2 */ - pHalData->PHYRegDef[RF_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; - pHalData->PHYRegDef[RF_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; - pHalData->PHYRegDef[RF_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; - pHalData->PHYRegDef[RF_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; - - /* RX AFE control 1 */ - pHalData->PHYRegDef[RF_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; - pHalData->PHYRegDef[RF_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; - pHalData->PHYRegDef[RF_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; - pHalData->PHYRegDef[RF_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; - - /* RX AFE control 1 */ - pHalData->PHYRegDef[RF_PATH_A].rfRxAFE = rOFDM0_XARxAFE; - pHalData->PHYRegDef[RF_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; - pHalData->PHYRegDef[RF_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; - pHalData->PHYRegDef[RF_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; - - /* Tx AFE control 1 */ - pHalData->PHYRegDef[RF_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; - pHalData->PHYRegDef[RF_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; - pHalData->PHYRegDef[RF_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; - pHalData->PHYRegDef[RF_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; - - /* Tx AFE control 2 */ - pHalData->PHYRegDef[RF_PATH_A].rfTxAFE = rOFDM0_XATxAFE; - pHalData->PHYRegDef[RF_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; - pHalData->PHYRegDef[RF_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; - pHalData->PHYRegDef[RF_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; - - /* Tranceiver LSSI Readback SI mode */ - pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; - pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; - pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; - pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; - - /* Tranceiver LSSI Readback PI mode */ - pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback; - pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback; -} - -void storePwrIndexDiffRateOffset(struct adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data) -{ - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - - if (RegAddr == rTxAGC_A_Rate18_06) - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0] = Data; - if (RegAddr == rTxAGC_A_Rate54_24) - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1] = Data; - if (RegAddr == rTxAGC_A_CCK1_Mcs32) - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6] = Data; - if (RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0xffffff00) - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7] = Data; - if (RegAddr == rTxAGC_A_Mcs03_Mcs00) - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2] = Data; - if (RegAddr == rTxAGC_A_Mcs07_Mcs04) - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3] = Data; - if (RegAddr == rTxAGC_A_Mcs11_Mcs08) - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4] = Data; - if (RegAddr == rTxAGC_A_Mcs15_Mcs12) { - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5] = Data; - if (pHalData->rf_type == RF_1T1R) - pHalData->pwrGroupCnt++; - } - if (RegAddr == rTxAGC_B_Rate18_06) - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8] = Data; - if (RegAddr == rTxAGC_B_Rate54_24) - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9] = Data; - if (RegAddr == rTxAGC_B_CCK1_55_Mcs32) - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14] = Data; - if (RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0x000000ff) - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15] = Data; - if (RegAddr == rTxAGC_B_Mcs03_Mcs00) - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10] = Data; - if (RegAddr == rTxAGC_B_Mcs07_Mcs04) - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11] = Data; - if (RegAddr == rTxAGC_B_Mcs11_Mcs08) - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12] = Data; - if (RegAddr == rTxAGC_B_Mcs15_Mcs12) { - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13] = Data; - if (pHalData->rf_type != RF_1T1R) - pHalData->pwrGroupCnt++; - } -} - -static int phy_BB8188E_Config_ParaFile(struct adapter *Adapter) -{ - struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter); - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - int rtStatus = _SUCCESS; - - /* */ - /* 1. Read PHY_REG.TXT BB INIT!! */ - /* We will separate as 88C / 92C according to chip version */ - /* */ - if (HAL_STATUS_FAILURE == ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG)) - rtStatus = _FAIL; - if (rtStatus != _SUCCESS) - goto phy_BB8190_Config_ParaFile_Fail; - - /* 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */ - if (!pEEPROM->bautoload_fail_flag) { - pHalData->pwrGroupCnt = 0; - - if (HAL_STATUS_FAILURE == ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_PG)) - rtStatus = _FAIL; - } - - if (rtStatus != _SUCCESS) - goto phy_BB8190_Config_ParaFile_Fail; - - /* 3. BB AGC table Initialization */ - if (HAL_STATUS_FAILURE == ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB)) - rtStatus = _FAIL; - - if (rtStatus != _SUCCESS) - goto phy_BB8190_Config_ParaFile_Fail; - -phy_BB8190_Config_ParaFile_Fail: - - return rtStatus; -} - -int -PHY_BBConfig8188E( - struct adapter *Adapter - ) -{ - int rtStatus = _SUCCESS; - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - u32 RegVal; - u8 CrystalCap; - - phy_InitBBRFRegisterDefinition(Adapter); - - - /* Enable BB and RF */ - RegVal = usb_read16(Adapter, REG_SYS_FUNC_EN); - usb_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1)); - - /* 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF. */ - - usb_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB); - - usb_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB); - - /* Config BB and AGC */ - rtStatus = phy_BB8188E_Config_ParaFile(Adapter); - - /* write 0x24[16:11] = 0x24[22:17] = CrystalCap */ - CrystalCap = pHalData->CrystalCap & 0x3F; - PHY_SetBBReg(Adapter, REG_AFE_XTAL_CTRL, 0x7ff800, (CrystalCap | (CrystalCap << 6))); - - return rtStatus; -} - -int PHY_RFConfig8188E(struct adapter *Adapter) -{ - int rtStatus = _SUCCESS; - - /* RF config */ - rtStatus = PHY_RF6052_Config8188E(Adapter); - return rtStatus; -} - -static void getTxPowerIndex88E(struct adapter *Adapter, u8 channel, u8 *cckPowerLevel, - u8 *ofdmPowerLevel, u8 *BW20PowerLevel, - u8 *BW40PowerLevel) -{ - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - u8 index = (channel - 1); - u8 TxCount = 0, path_nums; - - if ((RF_1T2R == pHalData->rf_type) || (RF_1T1R == pHalData->rf_type)) - path_nums = 1; - else - path_nums = 2; - - for (TxCount = 0; TxCount < path_nums; TxCount++) { - if (TxCount == RF_PATH_A) { - /* 1. CCK */ - cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index]; - /* 2. OFDM */ - ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ - pHalData->OFDM_24G_Diff[TxCount][RF_PATH_A]; - /* 1. BW20 */ - BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ - pHalData->BW20_24G_Diff[TxCount][RF_PATH_A]; - /* 2. BW40 */ - BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index]; - } else if (TxCount == RF_PATH_B) { - /* 1. CCK */ - cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index]; - /* 2. OFDM */ - ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ - pHalData->BW20_24G_Diff[RF_PATH_A][index]+ - pHalData->BW20_24G_Diff[TxCount][index]; - /* 1. BW20 */ - BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ - pHalData->BW20_24G_Diff[TxCount][RF_PATH_A]+ - pHalData->BW20_24G_Diff[TxCount][index]; - /* 2. BW40 */ - BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index]; - } else if (TxCount == RF_PATH_C) { - /* 1. CCK */ - cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index]; - /* 2. OFDM */ - ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ - pHalData->BW20_24G_Diff[RF_PATH_A][index]+ - pHalData->BW20_24G_Diff[RF_PATH_B][index]+ - pHalData->BW20_24G_Diff[TxCount][index]; - /* 1. BW20 */ - BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ - pHalData->BW20_24G_Diff[RF_PATH_A][index]+ - pHalData->BW20_24G_Diff[RF_PATH_B][index]+ - pHalData->BW20_24G_Diff[TxCount][index]; - /* 2. BW40 */ - BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index]; - } else if (TxCount == RF_PATH_D) { - /* 1. CCK */ - cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index]; - /* 2. OFDM */ - ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ - pHalData->BW20_24G_Diff[RF_PATH_A][index]+ - pHalData->BW20_24G_Diff[RF_PATH_B][index]+ - pHalData->BW20_24G_Diff[RF_PATH_C][index]+ - pHalData->BW20_24G_Diff[TxCount][index]; - - /* 1. BW20 */ - BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ - pHalData->BW20_24G_Diff[RF_PATH_A][index]+ - pHalData->BW20_24G_Diff[RF_PATH_B][index]+ - pHalData->BW20_24G_Diff[RF_PATH_C][index]+ - pHalData->BW20_24G_Diff[TxCount][index]; - - /* 2. BW40 */ - BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index]; - } - } -} - -static void phy_PowerIndexCheck88E(struct adapter *Adapter, u8 channel, u8 *cckPowerLevel, - u8 *ofdmPowerLevel, u8 *BW20PowerLevel, u8 *BW40PowerLevel) -{ - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - - pHalData->CurrentCckTxPwrIdx = cckPowerLevel[0]; - pHalData->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0]; - pHalData->CurrentBW2024GTxPwrIdx = BW20PowerLevel[0]; - pHalData->CurrentBW4024GTxPwrIdx = BW40PowerLevel[0]; -} - -/*----------------------------------------------------------------------------- - * Function: SetTxPowerLevel8190() - * - * Overview: This function is export to "HalCommon" moudule - * We must consider RF path later!!!!!!! - * - * Input: struct adapter *Adapter - * u8 channel - * - * Output: NONE - * - * Return: NONE - * 2008/11/04 MHC We remove EEPROM_93C56. - * We need to move CCX relative code to independet file. - * 2009/01/21 MHC Support new EEPROM format from SD3 requirement. - * - *---------------------------------------------------------------------------*/ -void -PHY_SetTxPowerLevel8188E( - struct adapter *Adapter, - u8 channel - ) -{ - u8 cckPowerLevel[MAX_TX_COUNT] = {0}; - u8 ofdmPowerLevel[MAX_TX_COUNT] = {0};/* [0]:RF-A, [1]:RF-B */ - u8 BW20PowerLevel[MAX_TX_COUNT] = {0}; - u8 BW40PowerLevel[MAX_TX_COUNT] = {0}; - - getTxPowerIndex88E(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0], &BW20PowerLevel[0], &BW40PowerLevel[0]); - - phy_PowerIndexCheck88E(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0], &BW20PowerLevel[0], &BW40PowerLevel[0]); - - rtl8188e_PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]); - rtl8188e_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], &BW20PowerLevel[0], &BW40PowerLevel[0], channel); -} - -/*----------------------------------------------------------------------------- - * Function: PHY_SetBWModeCallback8192C() - * - * Overview: Timer callback function for SetSetBWMode - * - * Input: PRT_TIMER pTimer - * - * Output: NONE - * - * Return: NONE - * - * Note: (1) We do not take j mode into consideration now - * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run - * concurrently? - *---------------------------------------------------------------------------*/ -static void -_PHY_SetBWMode92C( - struct adapter *Adapter -) -{ - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - u8 regBwOpMode; - u8 regRRSR_RSC; - - if (pHalData->rf_chip == RF_PSEUDO_11N) - return; - - /* There is no 40MHz mode in RF_8225. */ - if (pHalData->rf_chip == RF_8225) - return; - - if (Adapter->bDriverStopped) - return; - - /* 3 */ - /* 3<1>Set MAC register */ - /* 3 */ - - regBwOpMode = usb_read8(Adapter, REG_BWOPMODE); - regRRSR_RSC = usb_read8(Adapter, REG_RRSR+2); - - switch (pHalData->CurrentChannelBW) { - case HT_CHANNEL_WIDTH_20: - regBwOpMode |= BW_OPMODE_20MHZ; - /* 2007/02/07 Mark by Emily because we have not verify whether this register works */ - usb_write8(Adapter, REG_BWOPMODE, regBwOpMode); - break; - case HT_CHANNEL_WIDTH_40: - regBwOpMode &= ~BW_OPMODE_20MHZ; - /* 2007/02/07 Mark by Emily because we have not verify whether this register works */ - usb_write8(Adapter, REG_BWOPMODE, regBwOpMode); - regRRSR_RSC = (regRRSR_RSC&0x90) | (pHalData->nCur40MhzPrimeSC<<5); - usb_write8(Adapter, REG_RRSR+2, regRRSR_RSC); - break; - default: - break; - } - - /* 3 */ - /* 3 <2>Set PHY related register */ - /* 3 */ - switch (pHalData->CurrentChannelBW) { - /* 20 MHz channel*/ - case HT_CHANNEL_WIDTH_20: - PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0); - PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0); - break; - /* 40 MHz channel*/ - case HT_CHANNEL_WIDTH_40: - PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1); - PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1); - /* Set Control channel to upper or lower. These settings are required only for 40MHz */ - PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1)); - PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC); - PHY_SetBBReg(Adapter, 0x818, (BIT26 | BIT27), - (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); - break; - default: - break; - } - /* Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 */ - - /* 3<3>Set RF related register */ - switch (pHalData->rf_chip) { - case RF_8225: - break; - case RF_8256: - /* Please implement this function in Hal8190PciPhy8256.c */ - break; - case RF_8258: - /* Please implement this function in Hal8190PciPhy8258.c */ - break; - case RF_PSEUDO_11N: - break; - case RF_6052: - rtl8188e_PHY_RF6052SetBandwidth(Adapter, pHalData->CurrentChannelBW); - break; - default: - break; - } -} - - /*----------------------------------------------------------------------------- - * Function: SetBWMode8190Pci() - * - * Overview: This function is export to "HalCommon" moudule - * - * Input: struct adapter *Adapter - * enum ht_channel_width Bandwidth 20M or 40M - * - * Output: NONE - * - * Return: NONE - * - * Note: We do not take j mode into consideration now - *---------------------------------------------------------------------------*/ -void PHY_SetBWMode8188E(struct adapter *Adapter, enum ht_channel_width Bandwidth, /* 20M or 40M */ - unsigned char Offset) /* Upper, Lower, or Don't care */ -{ - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - enum ht_channel_width tmpBW = pHalData->CurrentChannelBW; - - pHalData->CurrentChannelBW = Bandwidth; - - pHalData->nCur40MhzPrimeSC = Offset; - - if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) - _PHY_SetBWMode92C(Adapter); - else - pHalData->CurrentChannelBW = tmpBW; -} - -static void _PHY_SwChnl8192C(struct adapter *Adapter, u8 channel) -{ - u8 eRFPath; - u32 param1, param2; - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - - if (Adapter->bNotifyChannelChange) - DBG_88E("[%s] ch = %d\n", __func__, channel); - - /* s1. pre common command - CmdID_SetTxPowerLevel */ - PHY_SetTxPowerLevel8188E(Adapter, channel); - - /* s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel */ - param1 = RF_CHNLBW; - param2 = channel; - for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) { - pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2); - PHY_SetRFReg(Adapter, (enum rf_radio_path)eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]); - } -} - -void PHY_SwChnl8188E(struct adapter *Adapter, u8 channel) -{ - /* Call after initialization */ - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - u8 tmpchannel = pHalData->CurrentChannel; - bool bResult = true; - - if (pHalData->rf_chip == RF_PSEUDO_11N) - return; /* return immediately if it is peudo-phy */ - - if (channel == 0) - channel = 1; - - pHalData->CurrentChannel = channel; - - if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) { - _PHY_SwChnl8192C(Adapter, channel); - - if (bResult) - ; - else - pHalData->CurrentChannel = tmpchannel; - - } else { - pHalData->CurrentChannel = tmpchannel; - } -} diff --git a/drivers/staging/rtl8188eu/hal/rtl8188e_rf6052.c b/drivers/staging/rtl8188eu/hal/rtl8188e_rf6052.c deleted file mode 100644 index 8ce9d0e4eeff..000000000000 --- a/drivers/staging/rtl8188eu/hal/rtl8188e_rf6052.c +++ /dev/null @@ -1,527 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -/****************************************************************************** - * - * - * Module: rtl8192c_rf6052.c ( Source C File) - * - * Note: Provide RF 6052 series relative API. - * - * Function: - * - * Export: - * - * Abbrev: - * - * History: - * Data Who Remark - * - * 09/25/2008 MHC Create initial version. - * 11/05/2008 MHC Add API for tw power setting. - * - * -******************************************************************************/ - -#define _RTL8188E_RF6052_C_ - -#include <osdep_service.h> -#include <drv_types.h> - -#include <rtl8188e_hal.h> - -/*----------------------------------------------------------------------------- - * Function: PHY_RF6052SetBandwidth() - * - * Overview: This function is called by SetBWModeCallback8190Pci() only - * - * Input: struct adapter *Adapter - * WIRELESS_BANDWIDTH_E Bandwidth 20M or 40M - * - * Output: NONE - * - * Return: NONE - * - * Note: For RF type 0222D - *---------------------------------------------------------------------------*/ -void rtl8188e_PHY_RF6052SetBandwidth(struct adapter *Adapter, - enum ht_channel_width Bandwidth) -{ - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - - switch (Bandwidth) { - case HT_CHANNEL_WIDTH_20: - pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10) | BIT(11)); - PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); - break; - case HT_CHANNEL_WIDTH_40: - pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10)); - PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); - break; - default: - break; - } -} - -/*----------------------------------------------------------------------------- - * Function: PHY_RF6052SetCckTxPower - * - * Overview: - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 11/05/2008 MHC Simulate 8192series.. - * - *---------------------------------------------------------------------------*/ - -void -rtl8188e_PHY_RF6052SetCckTxPower( - struct adapter *Adapter, - u8 *pPowerlevel) -{ - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - struct dm_priv *pdmpriv = &pHalData->dmpriv; - struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; - u32 TxAGC[2] = {0, 0}, tmpval = 0, pwrtrac_value; - bool TurboScanOff = false; - u8 idx1, idx2; - u8 *ptr; - u8 direction; - /* FOR CE ,must disable turbo scan */ - TurboScanOff = true; - - - if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) { - TxAGC[RF_PATH_A] = 0x3f3f3f3f; - TxAGC[RF_PATH_B] = 0x3f3f3f3f; - - TurboScanOff = true;/* disable turbo scan */ - - if (TurboScanOff) { - for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) { - TxAGC[idx1] = - pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | - (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); - /* 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. */ - if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA) - TxAGC[idx1] = 0x20; - } - } - } else { - /* Driver dynamic Tx power shall not affect Tx power. - * It shall be determined by power training mechanism. -i * Currently, we cannot fully disable driver dynamic - * tx power mechanism because it is referenced by BT - * coexist mechanism. - * In the future, two mechanism shall be separated from - * each other and maintained independently. */ - if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) { - TxAGC[RF_PATH_A] = 0x10101010; - TxAGC[RF_PATH_B] = 0x10101010; - } else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) { - TxAGC[RF_PATH_A] = 0x00000000; - TxAGC[RF_PATH_B] = 0x00000000; - } else { - for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) { - TxAGC[idx1] = - pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | - (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); - } - if (pHalData->EEPROMRegulatory == 0) { - tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) + - (pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8); - TxAGC[RF_PATH_A] += tmpval; - - tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][14]) + - (pHalData->MCSTxPowerLevelOriginalOffset[0][15]<<24); - TxAGC[RF_PATH_B] += tmpval; - } - } - } - for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) { - ptr = (u8 *)(&(TxAGC[idx1])); - for (idx2 = 0; idx2 < 4; idx2++) { - if (*ptr > RF6052_MAX_TX_PWR) - *ptr = RF6052_MAX_TX_PWR; - ptr++; - } - } - ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 1, &direction, &pwrtrac_value); - - if (direction == 1) { - /* Increase TX power */ - TxAGC[0] += pwrtrac_value; - TxAGC[1] += pwrtrac_value; - } else if (direction == 2) { - /* Decrease TX power */ - TxAGC[0] -= pwrtrac_value; - TxAGC[1] -= pwrtrac_value; - } - - /* rf-A cck tx power */ - tmpval = TxAGC[RF_PATH_A]&0xff; - PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); - tmpval = TxAGC[RF_PATH_A]>>8; - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); - - /* rf-B cck tx power */ - tmpval = TxAGC[RF_PATH_B]>>24; - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval); - tmpval = TxAGC[RF_PATH_B]&0x00ffffff; - PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); -} /* PHY_RF6052SetCckTxPower */ - -/* */ -/* powerbase0 for OFDM rates */ -/* powerbase1 for HT MCS rates */ -/* */ -static void getpowerbase88e(struct adapter *Adapter, u8 *pPowerLevelOFDM, - u8 *pPowerLevelBW20, u8 *pPowerLevelBW40, u8 Channel, u32 *OfdmBase, u32 *MCSBase) -{ - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - u32 powerBase0, powerBase1; - u8 i, powerlevel[2]; - - for (i = 0; i < 2; i++) { - powerBase0 = pPowerLevelOFDM[i]; - - powerBase0 = (powerBase0<<24) | (powerBase0<<16) | (powerBase0<<8) | powerBase0; - *(OfdmBase+i) = powerBase0; - } - for (i = 0; i < pHalData->NumTotalRFPath; i++) { - /* Check HT20 to HT40 diff */ - if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) - powerlevel[i] = pPowerLevelBW20[i]; - else - powerlevel[i] = pPowerLevelBW40[i]; - powerBase1 = powerlevel[i]; - powerBase1 = (powerBase1<<24) | (powerBase1<<16) | (powerBase1<<8) | powerBase1; - *(MCSBase+i) = powerBase1; - } -} -static void get_rx_power_val_by_reg(struct adapter *Adapter, u8 Channel, - u8 index, u32 *powerBase0, u32 *powerBase1, - u32 *pOutWriteVal) -{ - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - struct dm_priv *pdmpriv = &pHalData->dmpriv; - u8 i, chnlGroup = 0, pwr_diff_limit[4], customer_pwr_limit; - s8 pwr_diff = 0; - u32 writeVal, customer_limit, rf; - u8 Regulatory = pHalData->EEPROMRegulatory; - - /* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */ - - for (rf = 0; rf < 2; rf++) { - switch (Regulatory) { - case 0: /* Realtek better performance */ - /* increase power diff defined by Realtek for large power */ - chnlGroup = 0; - writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] + - ((index < 2) ? powerBase0[rf] : powerBase1[rf]); - break; - case 1: /* Realtek regulatory */ - /* increase power diff defined by Realtek for regulatory */ - if (pHalData->pwrGroupCnt == 1) - chnlGroup = 0; - if (pHalData->pwrGroupCnt >= pHalData->PGMaxGroup) { - if (Channel < 3) /* Channel 1-2 */ - chnlGroup = 0; - else if (Channel < 6) /* Channel 3-5 */ - chnlGroup = 1; - else if (Channel < 9) /* Channel 6-8 */ - chnlGroup = 2; - else if (Channel < 12) /* Channel 9-11 */ - chnlGroup = 3; - else if (Channel < 14) /* Channel 12-13 */ - chnlGroup = 4; - else if (Channel == 14) /* Channel 14 */ - chnlGroup = 5; - } - writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] + - ((index < 2) ? powerBase0[rf] : powerBase1[rf]); - break; - case 2: /* Better regulatory */ - /* don't increase any power diff */ - writeVal = ((index < 2) ? powerBase0[rf] : powerBase1[rf]); - break; - case 3: /* Customer defined power diff. */ - /* increase power diff defined by customer. */ - chnlGroup = 0; - - if (index < 2) - pwr_diff = pHalData->TxPwrLegacyHtDiff[rf][Channel-1]; - else if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) - pwr_diff = pHalData->TxPwrHt20Diff[rf][Channel-1]; - - if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40) - customer_pwr_limit = pHalData->PwrGroupHT40[rf][Channel-1]; - else - customer_pwr_limit = pHalData->PwrGroupHT20[rf][Channel-1]; - - if (pwr_diff >= customer_pwr_limit) - pwr_diff = 0; - else - pwr_diff = customer_pwr_limit - pwr_diff; - - for (i = 0; i < 4; i++) { - pwr_diff_limit[i] = (u8)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)]&(0x7f<<(i*8)))>>(i*8)); - - if (pwr_diff_limit[i] > pwr_diff) - pwr_diff_limit[i] = pwr_diff; - } - customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) | - (pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]); - writeVal = customer_limit + ((index < 2) ? powerBase0[rf] : powerBase1[rf]); - break; - default: - chnlGroup = 0; - writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] + - ((index < 2) ? powerBase0[rf] : powerBase1[rf]); - break; - } -/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */ -/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */ -/* In the future, two mechanism shall be separated from each other and maintained independently. Thanks for Lanhsin's reminder. */ - /* 92d do not need this */ - if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) - writeVal = 0x14141414; - else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) - writeVal = 0x00000000; - - /* 20100628 Joseph: High power mode for BT-Coexist mechanism. */ - /* This mechanism is only applied when Driver-Highpower-Mechanism is OFF. */ - if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1) - writeVal = writeVal - 0x06060606; - else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2) - writeVal = writeVal; - *(pOutWriteVal+rf) = writeVal; - } -} -static void writeOFDMPowerReg88E(struct adapter *Adapter, u8 index, u32 *pValue) -{ - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - u16 regoffset_a[6] = { - rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24, - rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04, - rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12}; - u16 regoffset_b[6] = { - rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24, - rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04, - rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12}; - u8 i, rf, pwr_val[4]; - u32 writeVal; - u16 regoffset; - - for (rf = 0; rf < 2; rf++) { - writeVal = pValue[rf]; - for (i = 0; i < 4; i++) { - pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8)); - if (pwr_val[i] > RF6052_MAX_TX_PWR) - pwr_val[i] = RF6052_MAX_TX_PWR; - } - writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) | (pwr_val[1]<<8) | pwr_val[0]; - - if (rf == 0) - regoffset = regoffset_a[index]; - else - regoffset = regoffset_b[index]; - - PHY_SetBBReg(Adapter, regoffset, bMaskDWord, writeVal); - - /* 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */ - if (((pHalData->rf_type == RF_2T2R) && - (regoffset == rTxAGC_A_Mcs15_Mcs12 || regoffset == rTxAGC_B_Mcs15_Mcs12)) || - ((pHalData->rf_type != RF_2T2R) && - (regoffset == rTxAGC_A_Mcs07_Mcs04 || regoffset == rTxAGC_B_Mcs07_Mcs04))) { - writeVal = pwr_val[3]; - if (regoffset == rTxAGC_A_Mcs15_Mcs12 || regoffset == rTxAGC_A_Mcs07_Mcs04) - regoffset = 0xc90; - if (regoffset == rTxAGC_B_Mcs15_Mcs12 || regoffset == rTxAGC_B_Mcs07_Mcs04) - regoffset = 0xc98; - for (i = 0; i < 3; i++) { - if (i != 2) - writeVal = (writeVal > 8) ? (writeVal-8) : 0; - else - writeVal = (writeVal > 6) ? (writeVal-6) : 0; - usb_write8(Adapter, (u32)(regoffset+i), (u8)writeVal); - } - } - } -} - -/*----------------------------------------------------------------------------- - * Function: PHY_RF6052SetOFDMTxPower - * - * Overview: For legacy and HY OFDM, we must read EEPROM TX power index for - * different channel and read original value in TX power register area from - * 0xe00. We increase offset and original value to be correct tx pwr. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 11/05/2008 MHC Simulate 8192 series method. - * 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to - * A/B pwr difference or legacy/HT pwr diff. - * 2. We concern with path B legacy/HT OFDM difference. - * 01/22/2009 MHC Support new EPRO format from SD3. - * - *---------------------------------------------------------------------------*/ - -void -rtl8188e_PHY_RF6052SetOFDMTxPower( - struct adapter *Adapter, - u8 *pPowerLevelOFDM, - u8 *pPowerLevelBW20, - u8 *pPowerLevelBW40, - u8 Channel) -{ - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - u32 writeVal[2], powerBase0[2], powerBase1[2], pwrtrac_value; - u8 direction; - u8 index = 0; - - getpowerbase88e(Adapter, pPowerLevelOFDM, pPowerLevelBW20, pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]); - - /* 2012/04/23 MH According to power tracking value, we need to revise OFDM tx power. */ - /* This is ued to fix unstable power tracking mode. */ - ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 0, &direction, &pwrtrac_value); - - for (index = 0; index < 6; index++) { - get_rx_power_val_by_reg(Adapter, Channel, index, - &powerBase0[0], &powerBase1[0], - &writeVal[0]); - - if (direction == 1) { - writeVal[0] += pwrtrac_value; - writeVal[1] += pwrtrac_value; - } else if (direction == 2) { - writeVal[0] -= pwrtrac_value; - writeVal[1] -= pwrtrac_value; - } - writeOFDMPowerReg88E(Adapter, index, &writeVal[0]); - } -} - -static int phy_RF6052_Config_ParaFile(struct adapter *Adapter) -{ - struct bb_reg_def *pPhyReg; - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - u32 u4RegValue = 0; - u8 eRFPath; - int rtStatus = _SUCCESS; - - /* 3----------------------------------------------------------------- */ - /* 3 <2> Initialize RF */ - /* 3----------------------------------------------------------------- */ - for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) { - pPhyReg = &pHalData->PHYRegDef[eRFPath]; - - /*----Store original RFENV control type----*/ - switch (eRFPath) { - case RF_PATH_A: - case RF_PATH_C: - u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV); - break; - case RF_PATH_B: - case RF_PATH_D: - u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16); - break; - } - /*----Set RF_ENV enable----*/ - PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); - udelay(1);/* PlatformStallExecution(1); */ - - /*----Set RF_ENV output high----*/ - PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); - udelay(1);/* PlatformStallExecution(1); */ - - /* Set bit number of Address and Data for RF register */ - PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */ - udelay(1);/* PlatformStallExecution(1); */ - - PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */ - udelay(1);/* PlatformStallExecution(1); */ - - /*----Initialize RF fom connfiguration file----*/ - switch (eRFPath) { - case RF_PATH_A: - if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, (enum rf_radio_path)eRFPath, (enum rf_radio_path)eRFPath)) - rtStatus = _FAIL; - break; - case RF_PATH_B: - if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, (enum rf_radio_path)eRFPath, (enum rf_radio_path)eRFPath)) - rtStatus = _FAIL; - break; - case RF_PATH_C: - break; - case RF_PATH_D: - break; - } - /*----Restore RFENV control type----*/; - switch (eRFPath) { - case RF_PATH_A: - case RF_PATH_C: - PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); - break; - case RF_PATH_B: - case RF_PATH_D: - PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); - break; - } - if (rtStatus != _SUCCESS) - goto phy_RF6052_Config_ParaFile_Fail; - } - return rtStatus; - -phy_RF6052_Config_ParaFile_Fail: - return rtStatus; -} - -int PHY_RF6052_Config8188E(struct adapter *Adapter) -{ - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - int rtStatus = _SUCCESS; - - /* */ - /* Initialize general global value */ - /* */ - /* TODO: Extend RF_PATH_C and RF_PATH_D in the future */ - if (pHalData->rf_type == RF_1T1R) - pHalData->NumTotalRFPath = 1; - else - pHalData->NumTotalRFPath = 2; - - /* */ - /* Config BB and RF */ - /* */ - rtStatus = phy_RF6052_Config_ParaFile(Adapter); - return rtStatus; -} diff --git a/drivers/staging/rtl8188eu/hal/rtl8188e_xmit.c b/drivers/staging/rtl8188eu/hal/rtl8188e_xmit.c index 7ecbcf731ea9..7a4f754d86df 100644 --- a/drivers/staging/rtl8188eu/hal/rtl8188e_xmit.c +++ b/drivers/staging/rtl8188eu/hal/rtl8188e_xmit.c @@ -64,6 +64,7 @@ void _dbg_dump_tx_info(struct adapter *padapter, int frame_tag, { u8 dmp_txpkt; bool dump_txdesc = false; + rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DUMP_TXPKT, &(dmp_txpkt)); if (dmp_txpkt == 1) {/* dump txdesc for data frame */ diff --git a/drivers/staging/rtl8188eu/hal/rtl8188eu_recv.c b/drivers/staging/rtl8188eu/hal/rtl8188eu_recv.c index f25c87c63250..bc275b2a7d37 100644 --- a/drivers/staging/rtl8188eu/hal/rtl8188eu_recv.c +++ b/drivers/staging/rtl8188eu/hal/rtl8188eu_recv.c @@ -41,15 +41,16 @@ int rtl8188eu_init_recv_priv(struct adapter *padapter) /* init recv_buf */ _rtw_init_queue(&precvpriv->free_recv_buf_queue); - precvpriv->pallocated_recv_buf = kzalloc(NR_RECVBUFF * sizeof(struct recv_buf) + 4, GFP_KERNEL); + precvpriv->pallocated_recv_buf = + kzalloc(NR_RECVBUFF * sizeof(struct recv_buf), GFP_KERNEL); if (precvpriv->pallocated_recv_buf == NULL) { res = _FAIL; - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("alloc recv_buf fail!\n")); + RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, + ("alloc recv_buf fail!\n")); goto exit; } - memset(precvpriv->pallocated_recv_buf, 0, NR_RECVBUFF * sizeof(struct recv_buf) + 4); - precvpriv->precv_buf = (u8 *)N_BYTE_ALIGMENT((size_t)(precvpriv->pallocated_recv_buf), 4); + precvpriv->precv_buf = precvpriv->pallocated_recv_buf; precvbuf = (struct recv_buf *)precvpriv->precv_buf; @@ -66,20 +67,23 @@ int rtl8188eu_init_recv_priv(struct adapter *padapter) { int i; size_t tmpaddr = 0; - size_t alignment = 0; + size_t alignm = 0; struct sk_buff *pskb = NULL; skb_queue_head_init(&precvpriv->free_recv_skb_queue); for (i = 0; i < NR_PREALLOC_RECV_SKB; i++) { - pskb = __netdev_alloc_skb(padapter->pnetdev, MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, GFP_KERNEL); + pskb = __netdev_alloc_skb(padapter->pnetdev, + MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, + GFP_KERNEL); if (pskb) { pskb->dev = padapter->pnetdev; tmpaddr = (size_t)pskb->data; - alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1); - skb_reserve(pskb, (RECVBUFF_ALIGN_SZ - alignment)); + alignm = tmpaddr & (RECVBUFF_ALIGN_SZ-1); + skb_reserve(pskb, (RECVBUFF_ALIGN_SZ - alignm)); - skb_queue_tail(&precvpriv->free_recv_skb_queue, pskb); + skb_queue_tail(&precvpriv->free_recv_skb_queue, + pskb); } pskb = NULL; } @@ -109,7 +113,8 @@ void rtl8188eu_free_recv_priv(struct adapter *padapter) if (skb_queue_len(&precvpriv->free_recv_skb_queue)) - DBG_88E(KERN_WARNING "free_recv_skb_queue not empty, %d\n", skb_queue_len(&precvpriv->free_recv_skb_queue)); + DBG_88E(KERN_WARNING "free_recv_skb_queue not empty, %d\n", + skb_queue_len(&precvpriv->free_recv_skb_queue)); skb_queue_purge(&precvpriv->free_recv_skb_queue); } diff --git a/drivers/staging/rtl8188eu/hal/rtl8188eu_xmit.c b/drivers/staging/rtl8188eu/hal/rtl8188eu_xmit.c index 3494ac697456..be9eede6931d 100644 --- a/drivers/staging/rtl8188eu/hal/rtl8188eu_xmit.c +++ b/drivers/staging/rtl8188eu/hal/rtl8188eu_xmit.c @@ -336,7 +336,8 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz, u8 bag ptxdesc->txdw4 |= cpu_to_le32(HW_SSN); /* Hw set sequence number */ } - ODM_SetTxAntByTxInfo_88E(&haldata->odmpriv, pmem, pattrib->mac_id); + rtl88eu_dm_set_tx_ant_by_tx_info(&haldata->odmpriv, pmem, + pattrib->mac_id); rtl8188eu_cal_txdesc_chksum(ptxdesc); _dbg_dump_tx_info(adapt, pxmitframe->frame_tag, ptxdesc); diff --git a/drivers/staging/rtl8188eu/hal/usb_halinit.c b/drivers/staging/rtl8188eu/hal/usb_halinit.c index e18393317bdc..caf2ca3a47e7 100644 --- a/drivers/staging/rtl8188eu/hal/usb_halinit.c +++ b/drivers/staging/rtl8188eu/hal/usb_halinit.c @@ -22,15 +22,14 @@ #include <osdep_service.h> #include <drv_types.h> #include <rtw_efuse.h> - +#include <fw.h> #include <rtl8188e_hal.h> #include <rtl8188e_led.h> #include <rtw_iol.h> #include <usb_hal.h> +#include <phy.h> -#define HAL_MAC_ENABLE 1 #define HAL_BB_ENABLE 1 -#define HAL_RF_ENABLE 1 static void _ConfigNormalChipOutEP_8188E(struct adapter *adapt, u8 NumOutPipe) { @@ -108,7 +107,9 @@ static u32 rtl8188eu_InitPowerOn(struct adapter *adapt) if (haldata->bMacPwrCtrlOn) return _SUCCESS; - if (!HalPwrSeqCmdParsing(adapt, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_PWR_ON_FLOW)) { + if (!rtl88eu_pwrseqcmdparsing(adapt, PWR_CUT_ALL_MSK, + PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, + Rtl8188E_NIC_PWR_ON_FLOW)) { DBG_88E(KERN_ERR "%s: run power on flow fail\n", __func__); return _FAIL; } @@ -614,8 +615,8 @@ static void _BeaconFunctionEnable(struct adapter *Adapter, /* Set CCK and OFDM Block "ON" */ static void _BBTurnOnBlock(struct adapter *Adapter) { - PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1); - PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1); + phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1); + phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1); } enum { @@ -632,9 +633,9 @@ static void _InitAntenna_Selection(struct adapter *Adapter) DBG_88E("==> %s ....\n", __func__); usb_write32(Adapter, REG_LEDCFG0, usb_read32(Adapter, REG_LEDCFG0)|BIT23); - PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, BIT13, 0x01); + phy_set_bb_reg(Adapter, rFPGA0_XAB_RFParameter, BIT13, 0x01); - if (PHY_QueryBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A) + if (phy_query_bb_reg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A) haldata->CurAntenna = Antenna_A; else haldata->CurAntenna = Antenna_B; @@ -693,14 +694,14 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter) if (Adapter->pwrctrlpriv.bkeepfwalive) { if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) { - PHY_IQCalibrate_8188E(Adapter, true); + rtl88eu_phy_iq_calibrate(Adapter, true); } else { - PHY_IQCalibrate_8188E(Adapter, false); + rtl88eu_phy_iq_calibrate(Adapter, false); haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true; } ODM_TXPowerTrackingCheck(&haldata->odmpriv); - PHY_LCCalibrate_8188E(Adapter); + rtl88eu_phy_lc_calibrate(Adapter); goto exit; } @@ -744,9 +745,9 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter) Adapter->bFWReady = false; haldata->fw_ractrl = false; } else { - status = rtl8188e_FirmwareDownload(Adapter); + status = rtl88eu_download_fw(Adapter); - if (status != _SUCCESS) { + if (status) { DBG_88E("%s: Download Firmware failed!!\n", __func__); Adapter->bFWReady = false; haldata->fw_ractrl = false; @@ -759,35 +760,11 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter) } rtl8188e_InitializeFirmwareVars(Adapter); - HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC); -#if (HAL_MAC_ENABLE == 1) - status = PHY_MACConfig8188E(Adapter); - if (status == _FAIL) { - DBG_88E(" ### Failed to init MAC ......\n "); - goto exit; - } -#endif + rtl88eu_phy_mac_config(Adapter); - /* */ - /* d. Initialize BB related configurations. */ - /* */ - HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB); -#if (HAL_BB_ENABLE == 1) - status = PHY_BBConfig8188E(Adapter); - if (status == _FAIL) { - DBG_88E(" ### Failed to init BB ......\n "); - goto exit; - } -#endif + rtl88eu_phy_bb_config(Adapter); - HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF); -#if (HAL_RF_ENABLE == 1) - status = PHY_RFConfig8188E(Adapter); - if (status == _FAIL) { - DBG_88E(" ### Failed to init RF ......\n "); - goto exit; - } -#endif + rtl88eu_phy_rf_config(Adapter); HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH); status = rtl8188e_iol_efuse_patch(Adapter); @@ -843,8 +820,8 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter) usb_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ /* Keep RfRegChnlVal for later use. */ - haldata->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (enum rf_radio_path)0, RF_CHNLBW, bRFRegOffsetMask); - haldata->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (enum rf_radio_path)1, RF_CHNLBW, bRFRegOffsetMask); + haldata->RfRegChnlVal[0] = phy_query_rf_reg(Adapter, (enum rf_radio_path)0, RF_CHNLBW, bRFRegOffsetMask); + haldata->RfRegChnlVal[1] = phy_query_rf_reg(Adapter, (enum rf_radio_path)1, RF_CHNLBW, bRFRegOffsetMask); HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK); _BBTurnOnBlock(Adapter); @@ -854,7 +831,7 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY); HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11); /* 2010/12/17 MH We need to set TX power according to EFUSE content at first. */ - PHY_SetTxPowerLevel8188E(Adapter, haldata->CurrentChannel); + phy_set_tx_power_level(Adapter, haldata->CurrentChannel); /* Move by Neo for USB SS to below setp */ /* _RfPowerSave(Adapter); */ @@ -905,9 +882,9 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK); /* 2010/08/26 MH Merge from 8192CE. */ if (pwrctrlpriv->rf_pwrstate == rf_on) { if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) { - PHY_IQCalibrate_8188E(Adapter, true); + rtl88eu_phy_iq_calibrate(Adapter, true); } else { - PHY_IQCalibrate_8188E(Adapter, false); + rtl88eu_phy_iq_calibrate(Adapter, false); haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true; } @@ -916,7 +893,7 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK); ODM_TXPowerTrackingCheck(&haldata->odmpriv); HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK); - PHY_LCCalibrate_8188E(Adapter); + rtl88eu_phy_lc_calibrate(Adapter); } /* HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS); */ @@ -950,7 +927,9 @@ static void CardDisableRTL8188EU(struct adapter *Adapter) usb_write8(Adapter, REG_CR, 0x0); /* Run LPS WL RFOFF flow */ - HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_LPS_ENTER_FLOW); + rtl88eu_pwrseqcmdparsing(Adapter, PWR_CUT_ALL_MSK, + PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, + Rtl8188E_NIC_LPS_ENTER_FLOW); /* 2. 0x1F[7:0] = 0 turn off RF */ @@ -971,7 +950,9 @@ static void CardDisableRTL8188EU(struct adapter *Adapter) usb_write8(Adapter, REG_32K_CTRL, val8&(~BIT0)); /* Card disable power action flow */ - HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_DISABLE_FLOW); + rtl88eu_pwrseqcmdparsing(Adapter, PWR_CUT_ALL_MSK, + PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, + Rtl8188E_NIC_DISABLE_FLOW); /* Reset MCU IO Wrapper */ val8 = usb_read8(Adapter, REG_RSV_CTRL+1); @@ -1764,7 +1745,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val) /* switch antenna to Optimum_antenna */ if (haldata->CurAntenna != Optimum_antenna) { Ant = (Optimum_antenna == 2) ? MAIN_ANT : AUX_ANT; - ODM_UpdateRxIdleAnt_88E(&haldata->odmpriv, Ant); + rtl88eu_dm_update_rx_idle_ant(&haldata->odmpriv, Ant); haldata->CurAntenna = Optimum_antenna; } diff --git a/drivers/staging/rtl8188eu/include/Hal8188EPhyCfg.h b/drivers/staging/rtl8188eu/include/Hal8188EPhyCfg.h index 260ea6bf9e83..20e6b40fc35c 100644 --- a/drivers/staging/rtl8188eu/include/Hal8188EPhyCfg.h +++ b/drivers/staging/rtl8188eu/include/Hal8188EPhyCfg.h @@ -198,41 +198,15 @@ struct ant_sel_cck { /* */ /* BB and RF register read/write */ /* */ -u32 rtl8188e_PHY_QueryBBReg(struct adapter *adapter, u32 regaddr, u32 mask); -void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr, - u32 mask, u32 data); -u32 rtl8188e_PHY_QueryRFReg(struct adapter *adapter, enum rf_radio_path rfpath, - u32 regaddr, u32 mask); -void rtl8188e_PHY_SetRFReg(struct adapter *adapter, enum rf_radio_path rfpath, - u32 regaddr, u32 mask, u32 data); - -/* Initialization related function */ -/* MAC/BB/RF HAL config */ -int PHY_MACConfig8188E(struct adapter *adapter); -int PHY_BBConfig8188E(struct adapter *adapter); -int PHY_RFConfig8188E(struct adapter *adapter); - -/* RF config */ -int rtl8188e_PHY_ConfigRFWithParaFile(struct adapter *adapter, u8 *filename, - enum rf_radio_path rfpath); -int rtl8188e_PHY_ConfigRFWithHeaderFile(struct adapter *adapter, - enum rf_radio_path rfpath); /* Read initi reg value for tx power setting. */ void rtl8192c_PHY_GetHWRegOriginalValue(struct adapter *adapter); /* BB TX Power R/W */ void PHY_GetTxPowerLevel8188E(struct adapter *adapter, u32 *powerlevel); -void PHY_SetTxPowerLevel8188E(struct adapter *adapter, u8 channel); void PHY_ScanOperationBackup8188E(struct adapter *Adapter, u8 Operation); -/* Switch bandwidth for 8192S */ -void PHY_SetBWMode8188E(struct adapter *adapter, - enum ht_channel_width chnlwidth, unsigned char offset); - -/* channel switch related funciton */ -void PHY_SwChnl8188E(struct adapter *adapter, u8 channel); /* Call after initialization */ void ChkFwCmdIoDone(struct adapter *adapter); @@ -245,19 +219,8 @@ void PHY_EnableHostClkReq(struct adapter *adapter); bool SetAntennaConfig92C(struct adapter *adapter, u8 defaultant); -void storePwrIndexDiffRateOffset(struct adapter *adapter, u32 regaddr, - u32 mask, u32 data); /*--------------------------Exported Function prototype---------------------*/ -#define PHY_QueryBBReg(adapt, regaddr, mask) \ - rtl8188e_PHY_QueryBBReg((adapt), (regaddr), (mask)) -#define PHY_SetBBReg(adapt, regaddr, bitmask, data) \ - rtl8188e_PHY_SetBBReg((adapt), (regaddr), (bitmask), (data)) -#define PHY_QueryRFReg(adapt, rfpath, regaddr, bitmask) \ - rtl8188e_PHY_QueryRFReg((adapt), (rfpath), (regaddr), (bitmask)) -#define PHY_SetRFReg(adapt, rfpath, regaddr, bitmask, data) \ - rtl8188e_PHY_SetRFReg((adapt), (rfpath), (regaddr), (bitmask), (data)) - #define PHY_SetMacReg PHY_SetBBReg #define SIC_HW_SUPPORT 0 diff --git a/drivers/staging/rtl8188eu/include/Hal8188EPwrSeq.h b/drivers/staging/rtl8188eu/include/Hal8188EPwrSeq.h deleted file mode 100644 index aebf1d3aac3b..000000000000 --- a/drivers/staging/rtl8188eu/include/Hal8188EPwrSeq.h +++ /dev/null @@ -1,176 +0,0 @@ - -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL8188EPWRSEQ_H__ -#define __HAL8188EPWRSEQ_H__ - -#include "HalPwrSeqCmd.h" - -/* - Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd - There are 6 HW Power States: - 0: POFF--Power Off - 1: PDN--Power Down - 2: CARDEMU--Card Emulation - 3: ACT--Active Mode - 4: LPS--Low Power State - 5: SUS--Suspend - - The transision from different states are defined below - TRANS_CARDEMU_TO_ACT - TRANS_ACT_TO_CARDEMU - TRANS_CARDEMU_TO_SUS - TRANS_SUS_TO_CARDEMU - TRANS_CARDEMU_TO_PDN - TRANS_ACT_TO_LPS - TRANS_LPS_TO_ACT - - TRANS_END - - PWR SEQ Version: rtl8188E_PwrSeq_V09.h -*/ -#define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10 -#define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10 -#define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10 -#define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10 -#define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10 -#define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10 -#define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15 -#define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15 -#define RTL8188E_TRANS_END_STEPS 1 - - -#define RTL8188E_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0|BIT1, 0}, /* 0x02[1:0] = 0 reset BB*/ \ - {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, /* 0x04[15] = 0 disable HWPDN (control by DRV)*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, 0}, /*0x04[12:11] = 2b'00 disable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[8] = 1 polling until return 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0}, /*wait till 0x04[8] = 0*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*LDO normal mode*/ \ - {0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*SDIO Driving*/ \ - -#define RTL8188E_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \ - {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*LDO Sleep mode*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ - -#define RTL8188E_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01enable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT7}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \ - {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ - {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ - -#define RTL8188E_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ - -#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \ - {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \ - {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ - {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ - -#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ - -#define RTL8188E_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ - -#define RTL8188E_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ - -/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */ -#define RTL8188E_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here */ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ - {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ - {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \ - - -#define RTL8188E_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here */ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ - {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ - {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ - {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ - {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ - -#define RTL8188E_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \ - {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0}, /* */ - - -extern struct wl_pwr_cfg rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]; -extern struct wl_pwr_cfg rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS]; -extern struct wl_pwr_cfg rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]; -extern struct wl_pwr_cfg rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]; -extern struct wl_pwr_cfg rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]; -extern struct wl_pwr_cfg rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]; -extern struct wl_pwr_cfg rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]; -extern struct wl_pwr_cfg rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS]; -extern struct wl_pwr_cfg rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]; - -#endif /* __HAL8188EPWRSEQ_H__ */ diff --git a/drivers/staging/rtl8188eu/include/HalHWImg8188E_BB.h b/drivers/staging/rtl8188eu/include/HalHWImg8188E_BB.h deleted file mode 100644 index e57452104bfb..000000000000 --- a/drivers/staging/rtl8188eu/include/HalHWImg8188E_BB.h +++ /dev/null @@ -1,44 +0,0 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -#ifndef __INC_BB_8188E_HW_IMG_H -#define __INC_BB_8188E_HW_IMG_H - -/* static bool CheckCondition(const u32 Condition, const u32 Hex); */ - -/****************************************************************************** -* AGC_TAB_1T.TXT -******************************************************************************/ - -enum HAL_STATUS ODM_ReadAndConfig_AGC_TAB_1T_8188E(struct odm_dm_struct *odm); - -/****************************************************************************** -* PHY_REG_1T.TXT -******************************************************************************/ - -enum HAL_STATUS ODM_ReadAndConfig_PHY_REG_1T_8188E(struct odm_dm_struct *odm); - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -void ODM_ReadAndConfig_PHY_REG_PG_8188E(struct odm_dm_struct *dm_odm); - -#endif diff --git a/drivers/staging/rtl8188eu/include/HalHWImg8188E_MAC.h b/drivers/staging/rtl8188eu/include/HalHWImg8188E_MAC.h deleted file mode 100644 index acf78b94fddb..000000000000 --- a/drivers/staging/rtl8188eu/include/HalHWImg8188E_MAC.h +++ /dev/null @@ -1,30 +0,0 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -#ifndef __INC_MAC_8188E_HW_IMG_H -#define __INC_MAC_8188E_HW_IMG_H - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -enum HAL_STATUS ODM_ReadAndConfig_MAC_REG_8188E(struct odm_dm_struct *pDM_Odm); - -#endif /* end of HWIMG_SUPPORT */ diff --git a/drivers/staging/rtl8188eu/include/HalHWImg8188E_RF.h b/drivers/staging/rtl8188eu/include/HalHWImg8188E_RF.h deleted file mode 100644 index 8ecb40d26c70..000000000000 --- a/drivers/staging/rtl8188eu/include/HalHWImg8188E_RF.h +++ /dev/null @@ -1,30 +0,0 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -#ifndef __INC_RF_8188E_HW_IMG_H -#define __INC_RF_8188E_HW_IMG_H - -/****************************************************************************** - * RadioA_1T.TXT - ******************************************************************************/ - -enum HAL_STATUS ODM_ReadAndConfig_RadioA_1T_8188E(struct odm_dm_struct *odm); - -#endif /* end of HWIMG_SUPPORT */ diff --git a/drivers/staging/rtl8188eu/include/HalPhyRf_8188e.h b/drivers/staging/rtl8188eu/include/HalPhyRf_8188e.h deleted file mode 100644 index 90a26c119d97..000000000000 --- a/drivers/staging/rtl8188eu/include/HalPhyRf_8188e.h +++ /dev/null @@ -1,61 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8188E_H__ -#define __HAL_PHY_RF_8188E_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#define IQK_DELAY_TIME_88E 10 /* ms */ -#define index_mapping_NUM_88E 15 -#define AVG_THERMAL_NUM_88E 4 -#define ODM_TARGET_CHNL_NUM_2G_5G 59 - -void ODM_TxPwrTrackAdjust88E(struct odm_dm_struct *pDM_Odm, - u8 Type, /* 0 = OFDM, 1 = CCK */ - u8 *pDirection,/* 1 = +(incr) 2 = -(decr) */ - u32 *pOutWriteVal); /* Tx tracking CCK/OFDM BB - * swing index adjust */ - - -void odm_TXPowerTrackingCallback_ThermalMeter_8188E(struct adapter *Adapter); - - -/* 1 7. IQK */ - -void PHY_IQCalibrate_8188E(struct adapter *Adapter, bool ReCovery); - -/* LC calibrate */ -void PHY_LCCalibrate_8188E(struct adapter *pAdapter); - -/* AP calibrate */ -void PHY_DigitalPredistortion_8188E(struct adapter *pAdapter); - -void _PHY_SaveADDARegisters(struct adapter *pAdapter, u32 *ADDAReg, - u32 *ADDABackup, u32 RegisterNum); - -void _PHY_PathADDAOn(struct adapter *pAdapter, u32 *ADDAReg, - bool isPathAOn, bool is2T); - -void _PHY_MACSettingCalibration(struct adapter *pAdapter, u32 *MACReg, - u32 *MACBackup); - -void _PHY_PathAStandBy(struct adapter *pAdapter); - -#endif /* #ifndef __HAL_PHY_RF_8188E_H__ */ diff --git a/drivers/staging/rtl8188eu/include/HalPwrSeqCmd.h b/drivers/staging/rtl8188eu/include/HalPwrSeqCmd.h deleted file mode 100644 index d945784ed5d9..000000000000 --- a/drivers/staging/rtl8188eu/include/HalPwrSeqCmd.h +++ /dev/null @@ -1,128 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __HALPWRSEQCMD_H__ -#define __HALPWRSEQCMD_H__ - -#include <drv_types.h> - -/*---------------------------------------------*/ -/* 3 The value of cmd: 4 bits */ -/*---------------------------------------------*/ -#define PWR_CMD_READ 0x00 - /* offset: the read register offset */ - /* msk: the mask of the read value */ - /* value: N/A, left by 0 */ - /* note: dirver shall implement this function by read & msk */ - -#define PWR_CMD_WRITE 0x01 - /* offset: the read register offset */ - /* msk: the mask of the write bits */ - /* value: write value */ - /* note: driver shall implement this cmd by read & msk after write */ - -#define PWR_CMD_POLLING 0x02 - /* offset: the read register offset */ - /* msk: the mask of the polled value */ - /* value: the value to be polled, masked by the msd field. */ - /* note: driver shall implement this cmd by */ - /* do{ */ - /* if ( (Read(offset) & msk) == (value & msk) ) */ - /* break; */ - /* } while (not timeout); */ - -#define PWR_CMD_DELAY 0x03 - /* offset: the value to delay */ - /* msk: N/A */ - /* value: the unit of delay, 0: us, 1: ms */ - -#define PWR_CMD_END 0x04 - /* offset: N/A */ - /* msk: N/A */ - /* value: N/A */ - -/*---------------------------------------------*/ -/* 3 The value of base: 4 bits */ -/*---------------------------------------------*/ - /* define the base address of each block */ -#define PWR_BASEADDR_MAC 0x00 -#define PWR_BASEADDR_USB 0x01 -#define PWR_BASEADDR_PCIE 0x02 -#define PWR_BASEADDR_SDIO 0x03 - -/*---------------------------------------------*/ -/* 3 The value of interface_msk: 4 bits */ -/*---------------------------------------------*/ -#define PWR_INTF_SDIO_MSK BIT(0) -#define PWR_INTF_USB_MSK BIT(1) -#define PWR_INTF_PCI_MSK BIT(2) -#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) - -/*---------------------------------------------*/ -/* 3 The value of fab_msk: 4 bits */ -/*---------------------------------------------*/ -#define PWR_FAB_TSMC_MSK BIT(0) -#define PWR_FAB_UMC_MSK BIT(1) -#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) - -/*---------------------------------------------*/ -/* 3 The value of cut_msk: 8 bits */ -/*---------------------------------------------*/ -#define PWR_CUT_TESTCHIP_MSK BIT(0) -#define PWR_CUT_A_MSK BIT(1) -#define PWR_CUT_B_MSK BIT(2) -#define PWR_CUT_C_MSK BIT(3) -#define PWR_CUT_D_MSK BIT(4) -#define PWR_CUT_E_MSK BIT(5) -#define PWR_CUT_F_MSK BIT(6) -#define PWR_CUT_G_MSK BIT(7) -#define PWR_CUT_ALL_MSK 0xFF - - -enum pwrseq_cmd_delat_unit { - PWRSEQ_DELAY_US, - PWRSEQ_DELAY_MS, -}; - -struct wl_pwr_cfg { - u16 offset; - u8 cut_msk; - u8 fab_msk:4; - u8 interface_msk:4; - u8 base:4; - u8 cmd:4; - u8 msk; - u8 value; -}; - -#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset -#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk -#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk -#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk -#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base -#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd -#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk -#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value - - -/* Prototype of protected function. */ -u8 HalPwrSeqCmdParsing(struct adapter *padapter, u8 CutVersion, u8 FabVersion, - u8 InterfaceType, struct wl_pwr_cfg PwrCfgCmd[]); - -#endif diff --git a/drivers/staging/rtl8188eu/include/drv_types.h b/drivers/staging/rtl8188eu/include/drv_types.h index 8f42d48243f0..c81317906adc 100644 --- a/drivers/staging/rtl8188eu/include/drv_types.h +++ b/drivers/staging/rtl8188eu/include/drv_types.h @@ -141,15 +141,8 @@ struct registry_priv { #define MAX_CONTINUAL_URB_ERR 4 -struct rt_firmware { - u8 *szFwBuffer; - u32 ulFwLength; -}; - struct dvobj_priv { struct adapter *if1; - struct rt_firmware firmware; - /* For 92D, DMDP have 2 interface. */ u8 InterfaceNumber; u8 NumInterfaces; diff --git a/drivers/staging/rtl8188eu/include/fw.h b/drivers/staging/rtl8188eu/include/fw.h new file mode 100644 index 000000000000..7884d8f65763 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/fw.h @@ -0,0 +1,59 @@ +/****************************************************************************** + * + * Copyright(c) 2009-2013 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * Larry Finger <Larry.Finger@lwfinger.net> + * + *****************************************************************************/ +#include "drv_types.h" +#include <linux/types.h> + +#ifndef __RTL92C__FW__H__ +#define __RTL92C__FW__H__ + +#define FW_8192C_START_ADDRESS 0x1000 +#define FW_8192C_PAGE_SIZE 4096 +#define FW_8192C_POLLING_DELAY 5 + +struct rtl92c_firmware_header { + __le16 signature; + u8 category; + u8 function; + u16 version; + u8 subversion; + u8 rsvd1; + u8 month; + u8 date; + u8 hour; + u8 minute; + u16 ramcodesize; + u16 rsvd2; + u32 svnindex; + u32 rsvd3; + u32 rsvd4; + u32 rsvd5; +}; + +int rtl88eu_download_fw(struct adapter *adapt); + +#endif diff --git a/drivers/staging/rtl8188eu/include/hal_intf.h b/drivers/staging/rtl8188eu/include/hal_intf.h index 56d5c50bb734..9191993dd3f5 100644 --- a/drivers/staging/rtl8188eu/include/hal_intf.h +++ b/drivers/staging/rtl8188eu/include/hal_intf.h @@ -213,11 +213,6 @@ struct hal_ops { struct xmit_frame *pxmitframe); s32 (*mgnt_xmit)(struct adapter *padapter, struct xmit_frame *pmgntframe); - - u32 (*read_bbreg)(struct adapter *padapter, u32 RegAddr, - u32 BitMask); - void (*write_bbreg)(struct adapter *padapter, u32 RegAddr, - u32 BitMask, u32 Data); u32 (*read_rfreg)(struct adapter *padapter, enum rf_radio_path eRFPath, u32 RegAddr, u32 BitMask); @@ -228,10 +223,6 @@ struct hal_ops { void (*sreset_init_value)(struct adapter *padapter); u8 (*sreset_get_wifi_status)(struct adapter *padapter); - int (*IOL_exec_cmds_sync)(struct adapter *padapter, - struct xmit_frame *frame, u32 max_wait, - u32 bndy_cnt); - void (*hal_notch_filter)(struct adapter *adapter, bool enable); void (*hal_reset_security_engine)(struct adapter *adapter); }; @@ -307,9 +298,6 @@ void rtw_hal_clone_data(struct adapter *dst_adapt, void rtw_hal_bcn_related_reg_setting(struct adapter *padapter); -u32 rtw_hal_read_bbreg(struct adapter *padapter, u32 RegAddr, u32 BitMask); -void rtw_hal_write_bbreg(struct adapter *padapter, u32 RegAddr, u32 BitMask, - u32 Data); u32 rtw_hal_read_rfreg(struct adapter *padapter, enum rf_radio_path eRFPath, u32 RegAddr, u32 BitMask); void rtw_hal_write_rfreg(struct adapter *padapter, @@ -331,9 +319,6 @@ void rtw_hal_antdiv_rssi_compared(struct adapter *padapter, void rtw_hal_sreset_init(struct adapter *padapter); u8 rtw_hal_sreset_get_wifi_status(struct adapter *padapter); -int rtw_hal_iol_cmd(struct adapter *adapter, struct xmit_frame *xmit_frame, - u32 max_wating_ms, u32 bndy_cnt); - void rtw_hal_notch_filter(struct adapter *adapter, bool enable); void rtw_hal_reset_security_engine(struct adapter *adapter); diff --git a/drivers/staging/rtl8188eu/include/odm.h b/drivers/staging/rtl8188eu/include/odm.h index e83812f35ad6..525eb100cd15 100644 --- a/drivers/staging/rtl8188eu/include/odm.h +++ b/drivers/staging/rtl8188eu/include/odm.h @@ -164,14 +164,6 @@ struct false_alarm_stats { u32 Cnt_BW_LSC; /* Gary */ }; -struct dyn_primary_cca { - u8 PriCCA_flag; - u8 intf_flag; - u8 intf_type; - u8 DupRTS_flag; - u8 Monitor_flag; -}; - struct rx_hpc { u8 RXHP_flag; u8 PSD_func_trigger; @@ -867,7 +859,6 @@ struct odm_dm_struct { struct fast_ant_train DM_FatTable; struct rtw_dig DM_DigTable; struct rtl_ps DM_PSTable; - struct dyn_primary_cca DM_PriCCA; struct rx_hpc DM_RXHP_Table; struct false_alarm_stats FalseAlmCnt; struct false_alarm_stats FlaseAlmCntBuddyAdapter; diff --git a/drivers/staging/rtl8188eu/include/odm_HWConfig.h b/drivers/staging/rtl8188eu/include/odm_HWConfig.h index 49e7e163ba70..1de4e6399435 100644 --- a/drivers/staging/rtl8188eu/include/odm_HWConfig.h +++ b/drivers/staging/rtl8188eu/include/odm_HWConfig.h @@ -120,13 +120,7 @@ void ODM_MacStatusQuery(struct odm_dm_struct *pDM_Odm, bool bPacketToSelf, bool bPacketBeacon); -enum HAL_STATUS ODM_ConfigRFWithHeaderFile(struct odm_dm_struct *pDM_Odm, - enum rf_radio_path Content, - enum rf_radio_path eRFPath); - enum HAL_STATUS ODM_ConfigBBWithHeaderFile(struct odm_dm_struct *pDM_Odm, enum odm_bb_config_type ConfigType); -enum HAL_STATUS ODM_ConfigMACWithHeaderFile(struct odm_dm_struct *pDM_Odm); - #endif diff --git a/drivers/staging/rtl8188eu/include/odm_RTL8188E.h b/drivers/staging/rtl8188eu/include/odm_RTL8188E.h index 02ac78d326d2..14dce6c4b1bc 100644 --- a/drivers/staging/rtl8188eu/include/odm_RTL8188E.h +++ b/drivers/staging/rtl8188eu/include/odm_RTL8188E.h @@ -29,17 +29,17 @@ void ODM_DIG_LowerBound_88E(struct odm_dm_struct *pDM_Odm); -void ODM_AntennaDiversityInit_88E(struct odm_dm_struct *pDM_Odm); +void rtl88eu_dm_antenna_div_init(struct odm_dm_struct *dm_odm); -void ODM_AntennaDiversity_88E(struct odm_dm_struct *pDM_Odm); +void rtl88eu_dm_antenna_diversity(struct odm_dm_struct *dm_odm); -void ODM_SetTxAntByTxInfo_88E(struct odm_dm_struct *pDM_Odm, u8 *pDesc, - u8 macId); +void rtl88eu_dm_set_tx_ant_by_tx_info(struct odm_dm_struct *dm_odm, u8 *desc, + u8 mac_id); -void ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *pDM_Odm, u8 Ant); +void rtl88eu_dm_update_rx_idle_ant(struct odm_dm_struct *dm_odm, u8 ant); -void ODM_AntselStatistics_88E(struct odm_dm_struct *pDM_Odm, u8 antsel_tr_mux, - u32 MacId, u8 RxPWDBAll); +void rtl88eu_dm_ant_sel_statistics(struct odm_dm_struct *dm_odm, u8 antsel_tr_mux, + u32 mac_id, u8 rx_pwdb_all); void odm_FastAntTraining(struct odm_dm_struct *pDM_Odm); @@ -47,8 +47,6 @@ void odm_FastAntTrainingCallback(struct odm_dm_struct *pDM_Odm); void odm_FastAntTrainingWorkItemCallback(struct odm_dm_struct *pDM_Odm); -void odm_PrimaryCCA_Init(struct odm_dm_struct *pDM_Odm); - bool ODM_DynamicPrimaryCCA_DupRTS(struct odm_dm_struct *pDM_Odm); #endif diff --git a/drivers/staging/rtl8188eu/include/odm_RegConfig8188E.h b/drivers/staging/rtl8188eu/include/odm_RegConfig8188E.h deleted file mode 100644 index f2bf7a0d9867..000000000000 --- a/drivers/staging/rtl8188eu/include/odm_RegConfig8188E.h +++ /dev/null @@ -1,43 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_ODM_REGCONFIG_H_8188E -#define __INC_ODM_REGCONFIG_H_8188E - -void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Data, - enum rf_radio_path RF_PATH, u32 RegAddr); - -void odm_ConfigRF_RadioA_8188E(struct odm_dm_struct *pDM_Odm, - u32 Addr, u32 Data); - -void odm_ConfigRF_RadioB_8188E(struct odm_dm_struct *pDM_Odm, - u32 Addr, u32 Data); - -void odm_ConfigMAC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u8 Data); - -void odm_ConfigBB_AGC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, - u32 Bitmask, u32 Data); - -void odm_ConfigBB_PHY_REG_PG_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, - u32 Bitmask, u32 Data); - -void odm_ConfigBB_PHY_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, - u32 Bitmask, u32 Data); - -#endif diff --git a/drivers/staging/rtl8188eu/include/odm_RegDefine11AC.h b/drivers/staging/rtl8188eu/include/odm_RegDefine11AC.h deleted file mode 100644 index f08775c0dd8e..000000000000 --- a/drivers/staging/rtl8188eu/include/odm_RegDefine11AC.h +++ /dev/null @@ -1,54 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __ODM_REGDEFINE11AC_H__ -#define __ODM_REGDEFINE11AC_H__ - -/* 2 RF REG LIST */ - - - -/* 2 BB REG LIST */ -/* PAGE 8 */ -/* PAGE 9 */ -#define ODM_REG_OFDM_FA_RST_11AC 0x9A4 -/* PAGE A */ -#define ODM_REG_CCK_CCA_11AC 0xA0A -#define ODM_REG_CCK_FA_RST_11AC 0xA2C -#define ODM_REG_CCK_FA_11AC 0xA5C -/* PAGE C */ -#define ODM_REG_IGI_A_11AC 0xC50 -/* PAGE E */ -#define ODM_REG_IGI_B_11AC 0xE50 -/* PAGE F */ -#define ODM_REG_OFDM_FA_11AC 0xF48 - - -/* 2 MAC REG LIST */ - - - - -/* DIG Related */ -#define ODM_BIT_IGI_11AC 0xFFFFFFFF - - - -#endif diff --git a/drivers/staging/rtl8188eu/include/odm_precomp.h b/drivers/staging/rtl8188eu/include/odm_precomp.h index 0ab8254ce901..0f236da09277 100644 --- a/drivers/staging/rtl8188eu/include/odm_precomp.h +++ b/drivers/staging/rtl8188eu/include/odm_precomp.h @@ -37,20 +37,13 @@ #include "odm.h" #include "odm_HWConfig.h" #include "odm_debug.h" -#include "odm_RegDefine11AC.h" #include "odm_RegDefine11N.h" -#include "HalPhyRf_8188e.h"/* for IQK,LCK,Power-tracking */ #include "Hal8188ERateAdaptive.h"/* for RA,Power training */ #include "rtl8188e_hal.h" #include "odm_reg.h" -#include "HalHWImg8188E_MAC.h" -#include "HalHWImg8188E_RF.h" -#include "HalHWImg8188E_BB.h" - -#include "odm_RegConfig8188E.h" #include "odm_RTL8188E.h" void odm_CmnInfoHook_Debug(struct odm_dm_struct *pDM_Odm); diff --git a/drivers/staging/rtl8188eu/include/phy.h b/drivers/staging/rtl8188eu/include/phy.h new file mode 100644 index 000000000000..9a9ab82a8ed3 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/phy.h @@ -0,0 +1,30 @@ +#include <odm.h> + +#define IQK_DELAY_TIME_88E 10 +#define index_mapping_NUM_88E 15 +#define AVG_THERMAL_NUM_88E 4 +#define ODM_TARGET_CHNL_NUM_2G_5G 59 + +bool rtl88eu_phy_mac_config(struct adapter *adapt); +bool rtl88eu_phy_rf_config(struct adapter *adapt); +bool rtl88eu_phy_bb_config(struct adapter *adapt); + +u32 phy_query_bb_reg(struct adapter *adapt, u32 regaddr, u32 bitmask); +void phy_set_bb_reg(struct adapter *adapt, u32 regaddr, u32 bitmask, u32 data); +u32 phy_query_rf_reg(struct adapter *adapt, enum rf_radio_path rf_path, + u32 reg_addr, u32 bit_mask); +void phy_set_rf_reg(struct adapter *adapt, enum rf_radio_path rf_path, + u32 reg_addr, u32 bit_mask, u32 data); + +void phy_set_tx_power_level(struct adapter *adapt, u8 channel); + +void phy_set_bw_mode(struct adapter *adapt, enum ht_channel_width bandwidth, + unsigned char offset); +void phy_sw_chnl(struct adapter *adapt, u8 channel); + +void rtl88eu_dm_txpower_track_adjust(struct odm_dm_struct *dm_odm, + u8 type, u8 *dir, u32 *out_write); + +void rtl88eu_dm_txpower_tracking_callback_thermalmeter(struct adapter *adapt); +void rtl88eu_phy_iq_calibrate(struct adapter *adapter, bool recovery); +void rtl88eu_phy_lc_calibrate(struct adapter *adapter); diff --git a/drivers/staging/rtl8188eu/include/pwrseq.h b/drivers/staging/rtl8188eu/include/pwrseq.h new file mode 100644 index 000000000000..43db92dcb8b3 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/pwrseq.h @@ -0,0 +1,341 @@ + +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL8188EPWRSEQ_H__ +#define __HAL8188EPWRSEQ_H__ + +#include "pwrseqcmd.h" + +/* + Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd + There are 6 HW Power States: + 0: POFF--Power Off + 1: PDN--Power Down + 2: CARDEMU--Card Emulation + 3: ACT--Active Mode + 4: LPS--Low Power State + 5: SUS--Suspend + + The transision from different states are defined below + TRANS_CARDEMU_TO_ACT + TRANS_ACT_TO_CARDEMU + TRANS_CARDEMU_TO_SUS + TRANS_SUS_TO_CARDEMU + TRANS_CARDEMU_TO_PDN + TRANS_ACT_TO_LPS + TRANS_LPS_TO_ACT + + TRANS_END + + PWR SEQ Version: rtl8188E_PwrSeq_V09.h +*/ +#define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10 +#define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10 +#define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10 +#define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10 +#define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10 +#define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10 +#define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15 +#define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15 +#define RTL8188E_TRANS_END_STEPS 1 + + +#define RTL8188E_TRANS_CARDEMU_TO_ACT \ + /* format + * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value + * }, + * comment here + */ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1}, \ + /* wait till 0x04[17] = 1 power ready*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0|BIT1, 0}, \ + /* 0x02[1:0] = 0 reset BB*/ \ + {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, \ + /*0x24[23] = 2b'01 schmit trigger */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, \ + /* 0x04[15] = 0 disable HWPDN (control by DRV)*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, 0}, \ + /*0x04[12:11] = 2b'00 disable WL suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, \ + /*0x04[8] = 1 polling until return 0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0}, \ + /*wait till 0x04[8] = 0*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, \ + /*LDO normal mode*/ \ + {0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, \ + /*SDIO Driving*/ + +#define RTL8188E_TRANS_ACT_TO_CARDEMU \ + /* format + * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value + * }, + * comments here + */ \ + {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \ + /*0x1F[7:0] = 0 turn off RF*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, \ + /*LDO Sleep mode*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, \ + /*0x04[9] = 1 turn off MAC by HW state machine*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, \ + /*wait till 0x04[9] = 0 polling until return 0 to disable*/ + +#define RTL8188E_TRANS_CARDEMU_TO_SUS \ + /* format + * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, + * value }, + * comments here + */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ + PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ + PWR_CMD_WRITE, BIT3|BIT4, BIT3}, \ + /* 0x04[12:11] = 2b'01enable WL suspend */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, \ + /* 0x04[12:11] = 2b'11enable WL suspend for PCIe */ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ + PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ + PWR_CMD_WRITE, 0xFF, BIT7}, \ + /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\ + {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ + PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ + PWR_CMD_WRITE, BIT4, 0}, \ + /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ + {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ + PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ + PWR_CMD_WRITE, BIT4, BIT4}, \ + /*Set USB suspend enable local register 0xfe10[4]=1 */ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ + PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, \ + /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ + PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, \ + /*wait power state to suspend*/ + +#define RTL8188E_TRANS_SUS_TO_CARDEMU \ + /* format + * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, + * value }, + * comments here + */ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ + PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, \ + /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ + PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, \ + /*wait power state to suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, \ + /*0x04[12:11] = 2b'01enable WL suspend*/ + +#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \ + /* format + * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, + * value }, + * comments here + */ \ + {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, \ + /*0x24[23] = 2b'01 schmit trigger */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ + PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ + PWR_CMD_WRITE, BIT3|BIT4, BIT3}, \ + /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ + PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ + PWR_CMD_WRITE, 0xFF, 0}, \ + /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\ + {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ + PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ + PWR_CMD_WRITE, BIT4, 0}, \ + /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ + {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, \ + /*Set USB suspend enable local register 0xfe10[4]=1 */ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ + PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, \ + /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ + PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, \ + /*wait power state to suspend*/ + +#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \ + /* format + * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, + * value }, + * comments here + */ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ + PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, \ + /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ + PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, \ + /*wait power state to suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, \ + /*0x04[12:11] = 2b'01enable WL suspend*/ + +#define RTL8188E_TRANS_CARDEMU_TO_PDN \ + /* format + * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, + * value }, + * comments here + */ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, \ + /* 0x04[16] = 0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, \ + /* 0x04[15] = 1*/ + +#define RTL8188E_TRANS_PDN_TO_CARDEMU \ + /* format + * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, + * value }, + * comments here + */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, \ + /* 0x04[15] = 0*/ + +/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */ +#define RTL8188E_TRANS_ACT_TO_LPS \ + /* format + * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, + * value }, + * comments here + */ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ + {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \ + /*Should be zero if no packet is transmitting*/ \ + {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \ + /*Should be zero if no packet is transmitting*/ \ + {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \ + /*Should be zero if no packet is transmitting*/ \ + {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \ + /*Should be zero if no packet is transmitting*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, \ + /*CCK and OFDM are disabled,and clock are gated*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, \ + PWRSEQ_DELAY_US},/*Delay 1us*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/\ + {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, \ + /*Respond TxOK to scheduler*/ + + +#define RTL8188E_TRANS_LPS_TO_ACT \ + /* format + * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, + * value }, + * comments here + */ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ + PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \ + {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \ + {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, \ + /* 0x08[4] = 0 switch TSF to 40M */ \ + {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, \ + /* Polling 0x109[7]=0 TSF in 40M */ \ + {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, \ + /* 0x29[7:6] = 2b'00 enable BB clock */ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, \ + /* 0x101[1] = 1 */ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \ + /* 0x100[7:0] = 0xFF enable WMAC TRX */ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, \ + /* 0x02[1:0] = 2b'11 enable BB macro */ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ + +#define RTL8188E_TRANS_END \ + /* format + * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, + * value }, + * comments here + */ \ + {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, \ + PWR_CMD_END, 0, 0}, + + +extern struct wl_pwr_cfg rtl8188E_power_on_flow + [RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS]; +extern struct wl_pwr_cfg rtl8188E_radio_off_flow + [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_END_STEPS]; +extern struct wl_pwr_cfg rtl8188E_card_disable_flow + [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + + RTL8188E_TRANS_END_STEPS]; +extern struct wl_pwr_cfg rtl8188E_card_enable_flow + [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + + RTL8188E_TRANS_END_STEPS]; +extern struct wl_pwr_cfg rtl8188E_suspend_flow[ + RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + + RTL8188E_TRANS_END_STEPS]; +extern struct wl_pwr_cfg rtl8188E_resume_flow + [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + + RTL8188E_TRANS_END_STEPS]; +extern struct wl_pwr_cfg rtl8188E_hwpdn_flow + [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS]; +extern struct wl_pwr_cfg rtl8188E_enter_lps_flow + [RTL8188E_TRANS_ACT_TO_LPS_STEPS + RTL8188E_TRANS_END_STEPS]; +extern struct wl_pwr_cfg rtl8188E_leave_lps_flow + [RTL8188E_TRANS_LPS_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS]; + +#endif /* __HAL8188EPWRSEQ_H__ */ diff --git a/drivers/staging/rtl8188eu/include/pwrseqcmd.h b/drivers/staging/rtl8188eu/include/pwrseqcmd.h new file mode 100644 index 000000000000..980a49769157 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/pwrseqcmd.h @@ -0,0 +1,90 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HALPWRSEQCMD_H__ +#define __HALPWRSEQCMD_H__ + +#include <drv_types.h> + +/* The value of cmd: 4 bits */ +#define PWR_CMD_READ 0x00 +#define PWR_CMD_WRITE 0x01 +#define PWR_CMD_POLLING 0x02 +#define PWR_CMD_DELAY 0x03 +#define PWR_CMD_END 0x04 + +/* The value of base: 4 bits */ +/* define the base address of each block */ +#define PWR_BASEADDR_MAC 0x00 +#define PWR_BASEADDR_USB 0x01 +#define PWR_BASEADDR_PCIE 0x02 +#define PWR_BASEADDR_SDIO 0x03 + +/* The value of interface_msk: 4 bits */ +#define PWR_INTF_SDIO_MSK BIT(0) +#define PWR_INTF_USB_MSK BIT(1) +#define PWR_INTF_PCI_MSK BIT(2) +#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) + +/* The value of fab_msk: 4 bits */ +#define PWR_FAB_TSMC_MSK BIT(0) +#define PWR_FAB_UMC_MSK BIT(1) +#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) + +/* The value of cut_msk: 8 bits */ +#define PWR_CUT_TESTCHIP_MSK BIT(0) +#define PWR_CUT_A_MSK BIT(1) +#define PWR_CUT_B_MSK BIT(2) +#define PWR_CUT_C_MSK BIT(3) +#define PWR_CUT_D_MSK BIT(4) +#define PWR_CUT_E_MSK BIT(5) +#define PWR_CUT_F_MSK BIT(6) +#define PWR_CUT_G_MSK BIT(7) +#define PWR_CUT_ALL_MSK 0xFF + + +enum pwrseq_cmd_delat_unit { + PWRSEQ_DELAY_US, + PWRSEQ_DELAY_MS, +}; + +struct wl_pwr_cfg { + u16 offset; + u8 cut_msk; + u8 fab_msk:4; + u8 interface_msk:4; + u8 base:4; + u8 cmd:4; + u8 msk; + u8 value; +}; + +#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset +#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk +#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk +#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk +#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base +#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd +#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk +#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value + +u8 rtl88eu_pwrseqcmdparsing(struct adapter *padapter, u8 cut_vers, u8 fab_vers, + u8 ifacetype, struct wl_pwr_cfg pwrcfgCmd[]); + +#endif diff --git a/drivers/staging/rtl8188eu/include/rf.h b/drivers/staging/rtl8188eu/include/rf.h new file mode 100644 index 000000000000..98a5551f5ae7 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rf.h @@ -0,0 +1,11 @@ +#define RF6052_MAX_TX_PWR 0x3F +#define RF6052_MAX_REG 0x3F + +void rtl88eu_phy_rf6052_set_bandwidth(struct adapter *adapt, + enum ht_channel_width bandwidth); +void rtl88eu_phy_rf6052_set_cck_txpower(struct adapter *adapt, + u8 *powerlevel); +void rtl88eu_phy_rf6052_set_ofdm_txpower(struct adapter *adapt, + u8 *powerlevel_ofdm, + u8 *powerlevel_bw20, + u8 *powerlevel_bw40, u8 channel); diff --git a/drivers/staging/rtl8188eu/include/rtl8188e_hal.h b/drivers/staging/rtl8188eu/include/rtl8188e_hal.h index fb206538392e..42ab1d288bdc 100644 --- a/drivers/staging/rtl8188eu/include/rtl8188e_hal.h +++ b/drivers/staging/rtl8188eu/include/rtl8188e_hal.h @@ -25,12 +25,11 @@ #include "rtl8188e_spec.h" #include "Hal8188EPhyReg.h" #include "Hal8188EPhyCfg.h" -#include "rtl8188e_rf.h" #include "rtl8188e_dm.h" #include "rtl8188e_recv.h" #include "rtl8188e_xmit.h" #include "rtl8188e_cmd.h" -#include "Hal8188EPwrSeq.h" +#include "pwrseq.h" #include "rtw_efuse.h" #include "rtw_sreset.h" #include "odm_precomp.h" @@ -70,45 +69,10 @@ #define MAX_PAGE_SIZE 4096 /* @ page : 4k bytes */ #define IS_FW_HEADER_EXIST(_pFwHdr) \ - ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 || \ - (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 || \ - (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300 || \ - (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88E0) - -/* This structure must be careful with byte-ordering */ - -struct rt_firmware_hdr { - /* 8-byte alinment required */ - /* LONG WORD 0 ---- */ - __le16 Signature; /* 92C0: test chip; 92C, - * 88C0: test chip; 88C1: MP A-cut; - * 92C1: MP A-cut */ - u8 Category; /* AP/NIC and USB/PCI */ - u8 Function; /* Reserved for different FW function - * indcation, for further use when - * driver needs to download different - * FW for different conditions */ - __le16 Version; /* FW Version */ - u8 Subversion; /* FW Subversion, default 0x00 */ - u16 Rsvd1; - - /* LONG WORD 1 ---- */ - u8 Month; /* Release time Month field */ - u8 Date; /* Release time Date field */ - u8 Hour; /* Release time Hour field */ - u8 Minute; /* Release time Minute field */ - __le16 RamCodeSize; /* The size of RAM code */ - u8 Foundry; - u8 Rsvd2; - - /* LONG WORD 2 ---- */ - __le32 SvnIdx; /* The SVN entry index */ - u32 Rsvd3; - - /* LONG WORD 3 ---- */ - u32 Rsvd4; - u32 Rsvd5; -}; + ((le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x92C0 || \ + (le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x88C0 || \ + (le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x2300 || \ + (le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x88E0) #define DRIVER_EARLY_INT_TIME 0x05 #define BCN_DMA_ATIME_INT_TIME 0x02 @@ -242,7 +206,8 @@ struct hal_data_8188e { struct HAL_VERSION VersionID; enum rt_regulator_mode RegulatorMode; /* switching regulator or LDO */ u16 CustomerID; - + u8 *pfirmware; + u32 fwsize; u16 FirmwareVersion; u16 FirmwareVersionRev; u16 FirmwareSubVersion; @@ -419,7 +384,6 @@ struct hal_data_8188e { (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) /* rtl8188e_hal_init.c */ -s32 rtl8188e_FirmwareDownload(struct adapter *padapter); void _8051Reset88E(struct adapter *padapter); void rtl8188e_InitializeFirmwareVars(struct adapter *padapter); @@ -453,12 +417,10 @@ void Hal_ReadPowerSavingMode88E(struct adapter *pAdapter, u8 *hwinfo, void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc); /* register */ -void SetBcnCtrlReg(struct adapter *padapter, u8 SetBits, u8 ClearBits); void rtl8188e_start_thread(struct adapter *padapter); void rtl8188e_stop_thread(struct adapter *padapter); -void rtw_IOL_cmd_tx_pkt_buf_dump(struct adapter *Adapter, int len); s32 iol_execute(struct adapter *padapter, u8 control); void iol_mode_enable(struct adapter *padapter, u8 enable); s32 rtl8188e_iol_efuse_patch(struct adapter *padapter); diff --git a/drivers/staging/rtl8188eu/include/rtl8188e_rf.h b/drivers/staging/rtl8188eu/include/rtl8188e_rf.h deleted file mode 100644 index 10fc356e0209..000000000000 --- a/drivers/staging/rtl8188eu/include/rtl8188e_rf.h +++ /dev/null @@ -1,36 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8188E_RF_H__ -#define __RTL8188E_RF_H__ - -#define RF6052_MAX_TX_PWR 0x3F -#define RF6052_MAX_REG 0x3F -#define RF6052_MAX_PATH 2 - - -int PHY_RF6052_Config8188E(struct adapter *Adapter); -void rtl8188e_RF_ChangeTxPath(struct adapter *Adapter, u16 DataRate); -void rtl8188e_PHY_RF6052SetBandwidth(struct adapter *Adapter, - enum ht_channel_width Bandwidth); -void rtl8188e_PHY_RF6052SetCckTxPower(struct adapter *Adapter, u8 *level); -void rtl8188e_PHY_RF6052SetOFDMTxPower(struct adapter *Adapter, u8 *ofdm, - u8 *pwrbw20, u8 *pwrbw40, u8 channel); - -#endif/* __RTL8188E_RF_H__ */ diff --git a/drivers/staging/rtl8188eu/include/rtw_efuse.h b/drivers/staging/rtl8188eu/include/rtw_efuse.h index 720f9ea24d52..5660eed7196b 100644 --- a/drivers/staging/rtl8188eu/include/rtw_efuse.h +++ b/drivers/staging/rtl8188eu/include/rtw_efuse.h @@ -99,7 +99,6 @@ struct efuse_hal { u8 fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]; }; -u16 Efuse_GetCurrentSize(struct adapter *adapter); u8 Efuse_CalculateWordCnts(u8 word_en); void EFUSE_GetEfuseDefinition(struct adapter *adapt, u8 type, u8 type1, void *out); diff --git a/drivers/staging/rtl8188eu/include/rtw_iol.h b/drivers/staging/rtl8188eu/include/rtw_iol.h index 80bfd063dd8d..68aae7f0b02f 100644 --- a/drivers/staging/rtl8188eu/include/rtw_iol.h +++ b/drivers/staging/rtl8188eu/include/rtw_iol.h @@ -23,60 +23,6 @@ #include <osdep_service.h> #include <drv_types.h> -#define IOREG_CMD_END_LEN 4 - -struct ioreg_cfg { - u8 length; - u8 cmd_id; - __le16 address; - __le32 data; - __le32 mask; -}; - -enum ioreg_cmd { - IOREG_CMD_LLT = 0x01, - IOREG_CMD_REFUSE = 0x02, - IOREG_CMD_EFUSE_PATH = 0x03, - IOREG_CMD_WB_REG = 0x04, - IOREG_CMD_WW_REG = 0x05, - IOREG_CMD_WD_REG = 0x06, - IOREG_CMD_W_RF = 0x07, - IOREG_CMD_DELAY_US = 0x10, - IOREG_CMD_DELAY_MS = 0x11, - IOREG_CMD_END = 0xFF, -}; - -struct xmit_frame *rtw_IOL_accquire_xmit_frame(struct adapter *adapter); -int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, - u32 cmd_len); -int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary); -int rtw_IOL_exec_cmds_sync(struct adapter *adapter, - struct xmit_frame *xmit_frame, u32 max_wating_ms, - u32 bndy_cnt); bool rtw_IOL_applied(struct adapter *adapter); -int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us); -int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms); -int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame); - -void read_efuse_from_txpktbuf(struct adapter *adapter, int bcnhead, - u8 *content, u16 *size); - -int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, - u8 value, u8 mask); -int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, - u32 value, u32 mask); -int _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, - u16 addr, u32 value, u32 mask); -#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value, mask) \ - _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value) , (mask)) -#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value, mask) \ - _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value), (mask)) -#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value, mask) \ - _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value), (mask)) -#define rtw_IOL_append_WRF_cmd(xmit_frame, rf_path, addr, value, mask) \ - _rtw_IOL_append_WRF_cmd((xmit_frame), (rf_path), (addr), (value), (mask)) - -u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame); -void rtw_IOL_cmd_buf_dump(struct adapter *Adapter, int buf_len, u8 *pbuf); #endif /* __RTW_IOL_H_ */ diff --git a/drivers/staging/rtl8188eu/os_dep/os_intfs.c b/drivers/staging/rtl8188eu/os_dep/os_intfs.c index c7a44ab33d64..08a80f759b8d 100644 --- a/drivers/staging/rtl8188eu/os_dep/os_intfs.c +++ b/drivers/staging/rtl8188eu/os_dep/os_intfs.c @@ -26,6 +26,7 @@ #include <recv_osdep.h> #include <hal_intf.h> #include <rtw_ioctl.h> +#include <rtl8188e_hal.h> #include <usb_hal.h> @@ -1121,7 +1122,7 @@ int pm_netdev_open(struct net_device *pnetdev, u8 bnormal) int netdev_close(struct net_device *pnetdev) { struct adapter *padapter = (struct adapter *)rtw_netdev_priv(pnetdev); - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct hal_data_8188e *rtlhal = GET_HAL_DATA(padapter); RT_TRACE(_module_os_intfs_c_, _drv_info_, ("+88eu_drv - drv_close\n")); @@ -1154,8 +1155,8 @@ int netdev_close(struct net_device *pnetdev) rtw_led_control(padapter, LED_CTL_POWER_OFF); } - kfree(dvobj->firmware.szFwBuffer); - dvobj->firmware.szFwBuffer = NULL; + kfree(rtlhal->pfirmware); + rtlhal->pfirmware = NULL; RT_TRACE(_module_os_intfs_c_, _drv_info_, ("-88eu_drv - drv_close\n")); DBG_88E("-88eu_drv - drv_close, bup =%d\n", padapter->bup); diff --git a/drivers/staging/rtl8188eu/os_dep/rtw_android.c b/drivers/staging/rtl8188eu/os_dep/rtw_android.c index ca2736d60b62..d9d55d12fd5f 100644 --- a/drivers/staging/rtl8188eu/os_dep/rtw_android.c +++ b/drivers/staging/rtl8188eu/os_dep/rtw_android.c @@ -79,7 +79,7 @@ int rtw_android_cmdstr_to_num(char *cmdstr) { int cmd_num; for (cmd_num = 0; cmd_num < ANDROID_WIFI_CMD_MAX; cmd_num++) - if (0 == strnicmp(cmdstr , android_wifi_cmd_str[cmd_num], + if (0 == strncasecmp(cmdstr , android_wifi_cmd_str[cmd_num], strlen(android_wifi_cmd_str[cmd_num]))) break; return cmd_num; @@ -106,23 +106,18 @@ static int rtw_android_get_link_speed(struct net_device *net, char *command, int total_len) { struct adapter *padapter = (struct adapter *)rtw_netdev_priv(net); - int bytes_written; u16 link_speed; link_speed = rtw_get_cur_max_rate(padapter) / 10; - bytes_written = snprintf(command, total_len, "LinkSpeed %d", + return snprintf(command, total_len, "LinkSpeed %d", link_speed); - return bytes_written; } static int rtw_android_get_macaddr(struct net_device *net, char *command, int total_len) { - int bytes_written; - - bytes_written = snprintf(command, total_len, "Macaddr = %pM", + return snprintf(command, total_len, "Macaddr = %pM", net->dev_addr); - return bytes_written; } static int android_set_cntry(struct net_device *net, char *command, diff --git a/drivers/staging/rtl8188eu/os_dep/usb_intf.c b/drivers/staging/rtl8188eu/os_dep/usb_intf.c index b8676ac77b0c..407a318b09db 100644 --- a/drivers/staging/rtl8188eu/os_dep/usb_intf.c +++ b/drivers/staging/rtl8188eu/os_dep/usb_intf.c @@ -43,9 +43,11 @@ static struct usb_device_id rtw_usb_id_tbl[] = { {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x0179)}, /* 8188ETV */ /*=== Customer ID ===*/ /****** 8188EUS ********/ + {USB_DEVICE(0x056e, 0x4008)}, /* Elecom WDC-150SU2M */ {USB_DEVICE(0x07b8, 0x8179)}, /* Abocom - Abocom */ {USB_DEVICE(0x2001, 0x330F)}, /* DLink DWA-125 REV D1 */ {USB_DEVICE(0x2001, 0x3310)}, /* Dlink DWA-123 REV D1 */ + {USB_DEVICE(0x0df6, 0x0076)}, /* Sitecom N150 v2 */ {} /* Terminating entry */ }; |