diff options
Diffstat (limited to 'drivers/staging/rtl8192e/rtl8192e')
37 files changed, 23213 insertions, 0 deletions
diff --git a/drivers/staging/rtl8192e/rtl8192e/Kconfig b/drivers/staging/rtl8192e/rtl8192e/Kconfig new file mode 100644 index 000000000000..50e0d91a409a --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/Kconfig @@ -0,0 +1,9 @@ +config RTL8192E + tristate "RealTek RTL8192E Wireless LAN NIC driver" + depends on PCI && WLAN && RTLLIB + depends on m + select WIRELESS_EXT + select WEXT_PRIV + select CRYPTO + default N + ---help--- diff --git a/drivers/staging/rtl8192e/rtl8192e/Makefile b/drivers/staging/rtl8192e/rtl8192e/Makefile new file mode 100644 index 000000000000..313a92ec6833 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/Makefile @@ -0,0 +1,21 @@ +r8192e_pci-objs := \ + r8192E_dev.o \ + r8192E_phy.o \ + r8192E_firmware.o \ + r8192E_cmdpkt.o \ + r8192E_hwimg.o \ + r8190P_rtl8256.o \ + rtl_cam.o \ + rtl_core.o \ + rtl_debug.o \ + rtl_dm.o \ + rtl_eeprom.o \ + rtl_ethtool.o \ + rtl_pci.o \ + rtl_pm.o \ + rtl_ps.o \ + rtl_wx.o \ + +obj-$(CONFIG_RTL8192E) += r8192e_pci.o + +ccflags-y += -D__CHECK_ENDIAN__ diff --git a/drivers/staging/rtl8192e/rtl8192e/r8190P_def.h b/drivers/staging/rtl8192e/rtl8192e/r8190P_def.h new file mode 100644 index 000000000000..b7bb71fa9ecd --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/r8190P_def.h @@ -0,0 +1,410 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ + + +#ifndef R8190P_DEF_H +#define R8190P_DEF_H + +#include <linux/types.h> + +#define MAX_SILENT_RESET_RX_SLOT_NUM 10 + +#define RX_MPDU_QUEUE 0 +#define RX_CMD_QUEUE 1 + + +enum rtl819x_loopback { + RTL819X_NO_LOOPBACK = 0, + RTL819X_MAC_LOOPBACK = 1, + RTL819X_DMA_LOOPBACK = 2, + RTL819X_CCK_LOOPBACK = 3, +}; + + +#define RESET_DELAY_8185 20 + +#define RT_IBSS_INT_MASKS (IMR_BcnInt | IMR_BcnInt | IMR_TBDOK | IMR_TBDER) + +#define DESC90_RATE1M 0x00 +#define DESC90_RATE2M 0x01 +#define DESC90_RATE5_5M 0x02 +#define DESC90_RATE11M 0x03 +#define DESC90_RATE6M 0x04 +#define DESC90_RATE9M 0x05 +#define DESC90_RATE12M 0x06 +#define DESC90_RATE18M 0x07 +#define DESC90_RATE24M 0x08 +#define DESC90_RATE36M 0x09 +#define DESC90_RATE48M 0x0a +#define DESC90_RATE54M 0x0b +#define DESC90_RATEMCS0 0x00 +#define DESC90_RATEMCS1 0x01 +#define DESC90_RATEMCS2 0x02 +#define DESC90_RATEMCS3 0x03 +#define DESC90_RATEMCS4 0x04 +#define DESC90_RATEMCS5 0x05 +#define DESC90_RATEMCS6 0x06 +#define DESC90_RATEMCS7 0x07 +#define DESC90_RATEMCS8 0x08 +#define DESC90_RATEMCS9 0x09 +#define DESC90_RATEMCS10 0x0a +#define DESC90_RATEMCS11 0x0b +#define DESC90_RATEMCS12 0x0c +#define DESC90_RATEMCS13 0x0d +#define DESC90_RATEMCS14 0x0e +#define DESC90_RATEMCS15 0x0f +#define DESC90_RATEMCS32 0x20 + +#define SHORT_SLOT_TIME 9 +#define NON_SHORT_SLOT_TIME 20 + + +#define MAX_LINES_HWCONFIG_TXT 1000 +#define MAX_BYTES_LINE_HWCONFIG_TXT 128 + +#define SW_THREE_WIRE 0 +#define HW_THREE_WIRE 2 + +#define BT_DEMO_BOARD 0 +#define BT_QA_BOARD 1 +#define BT_FPGA 2 + +#define RX_SMOOTH 20 + +#define QSLT_BK 0x1 +#define QSLT_BE 0x0 +#define QSLT_VI 0x4 +#define QSLT_VO 0x6 +#define QSLT_BEACON 0x10 +#define QSLT_HIGH 0x11 +#define QSLT_MGNT 0x12 +#define QSLT_CMD 0x13 + +#define NUM_OF_FIRMWARE_QUEUE 10 +#define NUM_OF_PAGES_IN_FW 0x100 +#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x007 +#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x0aa +#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x024 +#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x007 +#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0 +#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x2 +#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x10 +#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0 +#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4 +#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xd + +#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM 0x026 +#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM 0x048 +#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM 0x048 +#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM 0x026 +#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM 0x00 + +#define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000 +#define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00 +#define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08 +#define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10 +#define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18 +#define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10 +#define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00 +#define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08 + +#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 +#define HAL_PRIME_CHNL_OFFSET_LOWER 1 +#define HAL_PRIME_CHNL_OFFSET_UPPER 2 + + +enum version_8190_loopback { + VERSION_8190_BD = 0x3, + VERSION_8190_BE +}; + +#define IC_VersionCut_C 0x2 +#define IC_VersionCut_D 0x3 +#define IC_VersionCut_E 0x4 + +enum rf_optype { + RF_OP_By_SW_3wire = 0, + RF_OP_By_FW, + RF_OP_MAX +}; + + +enum power_save_mode { + POWER_SAVE_MODE_ACTIVE, + POWER_SAVE_MODE_SAVE, +}; + +enum interface_select_8190pci { + INTF_SEL1_MINICARD = 0, + INTF_SEL0_PCIE = 1, + INTF_SEL2_RSV = 2, + INTF_SEL3_RSV = 3, +}; + +struct bb_reg_definition { + u32 rfintfs; + u32 rfintfi; + u32 rfintfo; + u32 rfintfe; + u32 rf3wireOffset; + u32 rfLSSI_Select; + u32 rfTxGainStage; + u32 rfHSSIPara1; + u32 rfHSSIPara2; + u32 rfSwitchControl; + u32 rfAGCControl1; + u32 rfAGCControl2; + u32 rfRxIQImbalance; + u32 rfRxAFE; + u32 rfTxIQImbalance; + u32 rfTxAFE; + u32 rfLSSIReadBack; + u32 rfLSSIReadBackPi; +}; + +struct tx_fwinfo { + u8 TxRate:7; + u8 CtsEnable:1; + u8 RtsRate:7; + u8 RtsEnable:1; + u8 TxHT:1; + u8 Short:1; + u8 TxBandwidth:1; + u8 TxSubCarrier:2; + u8 STBC:2; + u8 AllowAggregation:1; + u8 RtsHT:1; + u8 RtsShort:1; + u8 RtsBandwidth:1; + u8 RtsSubcarrier:2; + u8 RtsSTBC:2; + u8 EnableCPUDur:1; + + u32 RxMF:2; + u32 RxAMD:3; + u32 Reserved1:3; + u32 TxAGCOffset:4; + u32 TxAGCSign:1; + u32 Tx_INFO_RSVD:6; + u32 PacketID:13; +}; + +struct tx_fwinfo_8190pci { + u8 TxRate:7; + u8 CtsEnable:1; + u8 RtsRate:7; + u8 RtsEnable:1; + u8 TxHT:1; + u8 Short:1; + u8 TxBandwidth:1; + u8 TxSubCarrier:2; + u8 STBC:2; + u8 AllowAggregation:1; + u8 RtsHT:1; + u8 RtsShort:1; + u8 RtsBandwidth:1; + u8 RtsSubcarrier:2; + u8 RtsSTBC:2; + u8 EnableCPUDur:1; + + u32 RxMF:2; + u32 RxAMD:3; + u32 TxPerPktInfoFeedback:1; + u32 Reserved1:2; + u32 TxAGCOffset:4; + u32 TxAGCSign:1; + u32 RAW_TXD:1; + u32 Retry_Limit:4; + u32 Reserved2:1; + u32 PacketID:13; + + +}; + + +#define TX_DESC_SIZE 32 + +#define TX_DESC_CMD_SIZE 32 + + +#define TX_STATUS_DESC_SIZE 32 + +#define TX_FWINFO_SIZE 8 + + +#define RX_DESC_SIZE 16 + +#define RX_STATUS_DESC_SIZE 16 + +#define RX_DRIVER_INFO_SIZE 8 + +struct log_int_8190 { + u32 nIMR_COMDOK; + u32 nIMR_MGNTDOK; + u32 nIMR_HIGH; + u32 nIMR_VODOK; + u32 nIMR_VIDOK; + u32 nIMR_BEDOK; + u32 nIMR_BKDOK; + u32 nIMR_ROK; + u32 nIMR_RCOK; + u32 nIMR_TBDOK; + u32 nIMR_BDOK; + u32 nIMR_RXFOVW; +}; + +struct phy_ofdm_rx_status_rxsc_sgien_exintfflag { + u8 reserved:4; + u8 rxsc:2; + u8 sgi_en:1; + u8 ex_intf_flag:1; +}; + +struct phy_sts_ofdm_819xpci { + u8 trsw_gain_X[4]; + u8 pwdb_all; + u8 cfosho_X[4]; + u8 cfotail_X[4]; + u8 rxevm_X[2]; + u8 rxsnr_X[4]; + u8 pdsnr_X[2]; + u8 csi_current_X[2]; + u8 csi_target_X[2]; + u8 sigevm; + u8 max_ex_pwr; + u8 sgi_en; + u8 rxsc_sgien_exflg; +}; + +struct phy_sts_cck_819xpci { + u8 adc_pwdb_X[4]; + u8 sq_rpt; + u8 cck_agc_rpt; +}; + + +#define PHY_RSSI_SLID_WIN_MAX 100 +#define PHY_Beacon_RSSI_SLID_WIN_MAX 10 + +struct tx_desc { + u16 PktSize; + u8 Offset; + u8 Reserved1:3; + u8 CmdInit:1; + u8 LastSeg:1; + u8 FirstSeg:1; + u8 LINIP:1; + u8 OWN:1; + + u8 TxFWInfoSize; + u8 RATid:3; + u8 DISFB:1; + u8 USERATE:1; + u8 MOREFRAG:1; + u8 NoEnc:1; + u8 PIFS:1; + u8 QueueSelect:5; + u8 NoACM:1; + u8 Resv:2; + u8 SecCAMID:5; + u8 SecDescAssign:1; + u8 SecType:2; + + u16 TxBufferSize; + u8 PktId:7; + u8 Resv1:1; + u8 Reserved2; + + u32 TxBuffAddr; + + u32 NextDescAddress; + + u32 Reserved5; + u32 Reserved6; + u32 Reserved7; +}; + + +struct tx_desc_cmd { + u16 PktSize; + u8 Reserved1; + u8 CmdType:3; + u8 CmdInit:1; + u8 LastSeg:1; + u8 FirstSeg:1; + u8 LINIP:1; + u8 OWN:1; + + u16 ElementReport; + u16 Reserved2; + + u16 TxBufferSize; + u16 Reserved3; + + u32 TxBuffAddr; + u32 NextDescAddress; + u32 Reserved4; + u32 Reserved5; + u32 Reserved6; +}; + +struct rx_desc { + u16 Length:14; + u16 CRC32:1; + u16 ICV:1; + u8 RxDrvInfoSize; + u8 Shift:2; + u8 PHYStatus:1; + u8 SWDec:1; + u8 LastSeg:1; + u8 FirstSeg:1; + u8 EOR:1; + u8 OWN:1; + + u32 Reserved2; + + u32 Reserved3; + + u32 BufferAddress; + +}; + + +struct rx_fwinfo { + u16 Reserved1:12; + u16 PartAggr:1; + u16 FirstAGGR:1; + u16 Reserved2:2; + + u8 RxRate:7; + u8 RxHT:1; + + u8 BW:1; + u8 SPLCP:1; + u8 Reserved3:2; + u8 PAM:1; + u8 Mcast:1; + u8 Bcast:1; + u8 Reserved4:1; + + u32 TSFL; + +}; + +#endif diff --git a/drivers/staging/rtl8192e/rtl8192e/r8190P_rtl8256.c b/drivers/staging/rtl8192e/rtl8192e/r8190P_rtl8256.c new file mode 100644 index 000000000000..0da56c80f088 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/r8190P_rtl8256.c @@ -0,0 +1,306 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ + +#include "rtl_core.h" +#include "r8192E_phyreg.h" +#include "r8192E_phy.h" +#include "r8190P_rtl8256.h" + +void PHY_SetRF8256Bandwidth(struct net_device *dev, + enum ht_channel_width Bandwidth) +{ + u8 eRFPath; + struct r8192_priv *priv = rtllib_priv(dev); + + for (eRFPath = 0; eRFPath < priv->NumTotalRFPath; eRFPath++) { + if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) + continue; + + switch (Bandwidth) { + case HT_CHANNEL_WIDTH_20: + if (priv->card_8192_version == VERSION_8190_BD || + priv->card_8192_version == VERSION_8190_BE) { + rtl8192_phy_SetRFReg(dev, + (enum rf90_radio_path)eRFPath, + 0x0b, bMask12Bits, 0x100); + rtl8192_phy_SetRFReg(dev, + (enum rf90_radio_path)eRFPath, + 0x2c, bMask12Bits, 0x3d7); + rtl8192_phy_SetRFReg(dev, + (enum rf90_radio_path)eRFPath, + 0x0e, bMask12Bits, 0x021); + + } else { + RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): " + "unknown hardware version\n"); + } + + break; + case HT_CHANNEL_WIDTH_20_40: + if (priv->card_8192_version == VERSION_8190_BD || + priv->card_8192_version == VERSION_8190_BE) { + rtl8192_phy_SetRFReg(dev, + (enum rf90_radio_path)eRFPath, + 0x0b, bMask12Bits, 0x300); + rtl8192_phy_SetRFReg(dev, + (enum rf90_radio_path)eRFPath, + 0x2c, bMask12Bits, 0x3ff); + rtl8192_phy_SetRFReg(dev, + (enum rf90_radio_path)eRFPath, + 0x0e, bMask12Bits, 0x0e1); + + } else { + RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): " + "unknown hardware version\n"); + } + + + break; + default: + RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown " + "Bandwidth: %#X\n", Bandwidth); + break; + + } + } + return; +} + +bool PHY_RF8256_Config(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + bool rtStatus = true; + priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH; + rtStatus = phy_RF8256_Config_ParaFile(dev); + + return rtStatus; +} + +bool phy_RF8256_Config_ParaFile(struct net_device *dev) +{ + u32 u4RegValue = 0; + u8 eRFPath; + bool rtStatus = true; + struct bb_reg_definition *pPhyReg; + struct r8192_priv *priv = rtllib_priv(dev); + u32 RegOffSetToBeCheck = 0x3; + u32 RegValueToBeCheck = 0x7f1; + u32 RF3_Final_Value = 0; + u8 ConstRetryTimes = 5, RetryTimes = 5; + u8 ret = 0; + + for (eRFPath = (enum rf90_radio_path)RF90_PATH_A; + eRFPath < priv->NumTotalRFPath; eRFPath++) { + if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) + continue; + + pPhyReg = &priv->PHYRegDef[eRFPath]; + + + switch (eRFPath) { + case RF90_PATH_A: + case RF90_PATH_C: + u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, + bRFSI_RFENV); + break; + case RF90_PATH_B: + case RF90_PATH_D: + u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, + bRFSI_RFENV<<16); + break; + } + + rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); + + rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); + + rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, + b3WireAddressLength, 0x0); + rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, + b3WireDataLength, 0x0); + + rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path) eRFPath, 0x0, + bMask12Bits, 0xbf); + + rtStatus = rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, + (enum rf90_radio_path)eRFPath); + if (rtStatus != true) { + RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check " + "Radio[%d] Fail!!\n", eRFPath); + goto phy_RF8256_Config_ParaFile_Fail; + } + + RetryTimes = ConstRetryTimes; + RF3_Final_Value = 0; + switch (eRFPath) { + case RF90_PATH_A: + while (RF3_Final_Value != RegValueToBeCheck && + RetryTimes != 0) { + ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, + (enum rf90_radio_path)eRFPath); + RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, + (enum rf90_radio_path)eRFPath, + RegOffSetToBeCheck, + bMask12Bits); + RT_TRACE(COMP_RF, "RF %d %d register final " + "value: %x\n", eRFPath, + RegOffSetToBeCheck, RF3_Final_Value); + RetryTimes--; + } + break; + case RF90_PATH_B: + while (RF3_Final_Value != RegValueToBeCheck && + RetryTimes != 0) { + ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, + (enum rf90_radio_path)eRFPath); + RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, + (enum rf90_radio_path)eRFPath, + RegOffSetToBeCheck, + bMask12Bits); + RT_TRACE(COMP_RF, "RF %d %d register final " + "value: %x\n", eRFPath, + RegOffSetToBeCheck, RF3_Final_Value); + RetryTimes--; + } + break; + case RF90_PATH_C: + while (RF3_Final_Value != RegValueToBeCheck && + RetryTimes != 0) { + ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, + (enum rf90_radio_path)eRFPath); + RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, + (enum rf90_radio_path)eRFPath, + RegOffSetToBeCheck, + bMask12Bits); + RT_TRACE(COMP_RF, "RF %d %d register final " + "value: %x\n", eRFPath, + RegOffSetToBeCheck, RF3_Final_Value); + RetryTimes--; + } + break; + case RF90_PATH_D: + while (RF3_Final_Value != RegValueToBeCheck && + RetryTimes != 0) { + ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, + (enum rf90_radio_path)eRFPath); + RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, + (enum rf90_radio_path)eRFPath, + RegOffSetToBeCheck, bMask12Bits); + RT_TRACE(COMP_RF, "RF %d %d register final " + "value: %x\n", eRFPath, + RegOffSetToBeCheck, RF3_Final_Value); + RetryTimes--; + } + break; + } + + switch (eRFPath) { + case RF90_PATH_A: + case RF90_PATH_C: + rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, + u4RegValue); + break; + case RF90_PATH_B: + case RF90_PATH_D: + rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, + u4RegValue); + break; + } + + if (ret) { + RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():" + "Radio[%d] Fail!!", eRFPath); + goto phy_RF8256_Config_ParaFile_Fail; + } + + } + + RT_TRACE(COMP_PHY, "PHY Initialization Success\n") ; + return true; + +phy_RF8256_Config_ParaFile_Fail: + RT_TRACE(COMP_ERR, "PHY Initialization failed\n") ; + return false; +} + +void PHY_SetRF8256CCKTxPower(struct net_device *dev, u8 powerlevel) +{ + u32 TxAGC = 0; + struct r8192_priv *priv = rtllib_priv(dev); + + TxAGC = powerlevel; + if (priv->bDynamicTxLowPower == true) { + if (priv->CustomerID == RT_CID_819x_Netcore) + TxAGC = 0x22; + else + TxAGC += priv->CckPwEnl; + } + if (TxAGC > 0x24) + TxAGC = 0x24; + rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); +} + + +void PHY_SetRF8256OFDMTxPower(struct net_device *dev, u8 powerlevel) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u32 writeVal, powerBase0, powerBase1, writeVal_tmp; + u8 index = 0; + u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; + u8 byte0, byte1, byte2, byte3; + + powerBase0 = powerlevel + priv->LegacyHTTxPowerDiff; + powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) | + (powerBase0 << 8) | powerBase0; + powerBase1 = powerlevel; + powerBase1 = (powerBase1 << 24) | (powerBase1 << 16) | + (powerBase1 << 8) | powerBase1; + + for (index = 0; index < 6; index++) { + writeVal = (u32)(priv->MCSTxPowerLevelOriginalOffset[index] + + ((index < 2) ? powerBase0 : powerBase1)); + byte0 = (u8)(writeVal & 0x7f); + byte1 = (u8)((writeVal & 0x7f00)>>8); + byte2 = (u8)((writeVal & 0x7f0000)>>16); + byte3 = (u8)((writeVal & 0x7f000000)>>24); + if (byte0 > 0x24) + byte0 = 0x24; + if (byte1 > 0x24) + byte1 = 0x24; + if (byte2 > 0x24) + byte2 = 0x24; + if (byte3 > 0x24) + byte3 = 0x24; + + if (index == 3) { + writeVal_tmp = (byte3 << 24) | (byte2 << 16) | + (byte1 << 8) | byte0; + priv->Pwr_Track = writeVal_tmp; + } + + if (priv->bDynamicTxHighPower == true) + writeVal = 0x03030303; + else + writeVal = (byte3 << 24) | (byte2 << 16) | + (byte1 << 8) | byte0; + rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); + } + + return; +} diff --git a/drivers/staging/rtl8192e/rtl8192e/r8190P_rtl8256.h b/drivers/staging/rtl8192e/rtl8192e/r8190P_rtl8256.h new file mode 100644 index 000000000000..64e831d2f4e5 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/r8190P_rtl8256.h @@ -0,0 +1,31 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ + +#ifndef RTL8225H +#define RTL8225H + +#define RTL819X_TOTAL_RF_PATH 2 +extern void PHY_SetRF8256Bandwidth(struct net_device *dev, + enum ht_channel_width Bandwidth); +extern bool PHY_RF8256_Config(struct net_device *dev); +extern bool phy_RF8256_Config_ParaFile(struct net_device *dev); +extern void PHY_SetRF8256CCKTxPower(struct net_device *dev, u8 powerlevel); +extern void PHY_SetRF8256OFDMTxPower(struct net_device *dev, u8 powerlevel); + +#endif diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_cmdpkt.c b/drivers/staging/rtl8192e/rtl8192e/r8192E_cmdpkt.c new file mode 100644 index 000000000000..58d044ea5524 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_cmdpkt.c @@ -0,0 +1,418 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ + +#include "rtl_core.h" +#include "r8192E_hw.h" +#include "r8192E_cmdpkt.h" +/*---------------------------Define Local Constant---------------------------*/ +/* Debug constant*/ +#define CMPK_DEBOUNCE_CNT 1 +#define CMPK_PRINT(Address)\ +{\ + unsigned char i;\ + u32 temp[10];\ + \ + memcpy(temp, Address, 40);\ + for (i = 0; i < 40; i += 4)\ + printk(KERN_INFO "\r\n %08x", temp[i]);\ +} + +/*---------------------------Define functions---------------------------------*/ +bool cmpk_message_handle_tx( + struct net_device *dev, + u8 *code_virtual_address, + u32 packettype, + u32 buffer_len) +{ + + bool rt_status = true; + struct r8192_priv *priv = rtllib_priv(dev); + u16 frag_threshold; + u16 frag_length = 0, frag_offset = 0; + struct rt_firmware *pfirmware = priv->pFirmware; + struct sk_buff *skb; + unsigned char *seg_ptr; + struct cb_desc *tcb_desc; + u8 bLastIniPkt; + + struct tx_fwinfo_8190pci *pTxFwInfo = NULL; + + RT_TRACE(COMP_CMDPKT, "%s(),buffer_len is %d\n", __func__, buffer_len); + firmware_init_param(dev); + frag_threshold = pfirmware->cmdpacket_frag_thresold; + + do { + if ((buffer_len - frag_offset) > frag_threshold) { + frag_length = frag_threshold ; + bLastIniPkt = 0; + + } else { + frag_length = (u16)(buffer_len - frag_offset); + bLastIniPkt = 1; + } + + skb = dev_alloc_skb(frag_length + + priv->rtllib->tx_headroom + 4); + + if (skb == NULL) { + rt_status = false; + goto Failed; + } + + memcpy((unsigned char *)(skb->cb), &dev, sizeof(dev)); + tcb_desc = (struct cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); + tcb_desc->queue_index = TXCMD_QUEUE; + tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_NORMAL; + tcb_desc->bLastIniPkt = bLastIniPkt; + tcb_desc->pkt_size = frag_length; + + seg_ptr = skb_put(skb, priv->rtllib->tx_headroom); + pTxFwInfo = (struct tx_fwinfo_8190pci *)seg_ptr; + memset(pTxFwInfo, 0, sizeof(struct tx_fwinfo_8190pci)); + memset(pTxFwInfo, 0x12, 8); + + seg_ptr = skb_put(skb, frag_length); + memcpy(seg_ptr, code_virtual_address, (u32)frag_length); + + priv->rtllib->softmac_hard_start_xmit(skb, dev); + + code_virtual_address += frag_length; + frag_offset += frag_length; + + } while (frag_offset < buffer_len); + + write_nic_byte(dev, TPPoll, TPPoll_CQ); +Failed: + return rt_status; +} /* CMPK_Message_Handle_Tx */ + +static void +cmpk_count_txstatistic( + struct net_device *dev, + struct cmpk_txfb *pstx_fb) +{ + struct r8192_priv *priv = rtllib_priv(dev); +#ifdef ENABLE_PS + enum rt_rf_power_state rtState; + + pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, + (pu1Byte)(&rtState)); + + if (rtState == eRfOff) + return; +#endif + + if (pstx_fb->tok) { + priv->stats.txfeedbackok++; + priv->stats.txoktotal++; + priv->stats.txokbytestotal += pstx_fb->pkt_length; + priv->stats.txokinperiod++; + + if (pstx_fb->pkt_type == PACKET_MULTICAST) { + priv->stats.txmulticast++; + priv->stats.txbytesmulticast += pstx_fb->pkt_length; + } else if (pstx_fb->pkt_type == PACKET_BROADCAST) { + priv->stats.txbroadcast++; + priv->stats.txbytesbroadcast += pstx_fb->pkt_length; + } else { + priv->stats.txunicast++; + priv->stats.txbytesunicast += pstx_fb->pkt_length; + } + } else { + priv->stats.txfeedbackfail++; + priv->stats.txerrtotal++; + priv->stats.txerrbytestotal += pstx_fb->pkt_length; + + if (pstx_fb->pkt_type == PACKET_MULTICAST) + priv->stats.txerrmulticast++; + else if (pstx_fb->pkt_type == PACKET_BROADCAST) + priv->stats.txerrbroadcast++; + else + priv->stats.txerrunicast++; + } + + priv->stats.txretrycount += pstx_fb->retry_cnt; + priv->stats.txfeedbackretry += pstx_fb->retry_cnt; + +} /* cmpk_CountTxStatistic */ + + + +static void cmpk_handle_tx_feedback(struct net_device *dev, u8 *pmsg) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct cmpk_txfb rx_tx_fb; /* */ + + priv->stats.txfeedback++; + + + memcpy((u8 *)&rx_tx_fb, pmsg, sizeof(struct cmpk_txfb)); + cmpk_count_txstatistic(dev, &rx_tx_fb); + +} /* cmpk_Handle_Tx_Feedback */ + +static void cmdpkt_beacontimerinterrupt_819xusb(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u16 tx_rate; + + if ((priv->rtllib->current_network.mode == IEEE_A) || + (priv->rtllib->current_network.mode == IEEE_N_5G) || + ((priv->rtllib->current_network.mode == IEEE_N_24G) && + (!priv->rtllib->pHTInfo->bCurSuppCCK))) { + tx_rate = 60; + DMESG("send beacon frame tx rate is 6Mbpm\n"); + } else { + tx_rate = 10; + DMESG("send beacon frame tx rate is 1Mbpm\n"); + } + +} + +static void cmpk_handle_interrupt_status(struct net_device *dev, u8 *pmsg) +{ + struct cmpk_intr_sta rx_intr_status; /* */ + struct r8192_priv *priv = rtllib_priv(dev); + + DMESG("---> cmpk_Handle_Interrupt_Status()\n"); + + + rx_intr_status.length = pmsg[1]; + if (rx_intr_status.length != (sizeof(struct cmpk_intr_sta) - 2)) { + DMESG("cmpk_Handle_Interrupt_Status: wrong length!\n"); + return; + } + + + if (priv->rtllib->iw_mode == IW_MODE_ADHOC) { + rx_intr_status.interrupt_status = *((u32 *)(pmsg + 4)); + + DMESG("interrupt status = 0x%x\n", + rx_intr_status.interrupt_status); + + if (rx_intr_status.interrupt_status & ISR_TxBcnOk) { + priv->rtllib->bibsscoordinator = true; + priv->stats.txbeaconokint++; + } else if (rx_intr_status.interrupt_status & ISR_TxBcnErr) { + priv->rtllib->bibsscoordinator = false; + priv->stats.txbeaconerr++; + } + + if (rx_intr_status.interrupt_status & ISR_BcnTimerIntr) + cmdpkt_beacontimerinterrupt_819xusb(dev); + } + + DMESG("<---- cmpk_handle_interrupt_status()\n"); + +} /* cmpk_handle_interrupt_status */ + + +static void cmpk_handle_query_config_rx(struct net_device *dev, u8 *pmsg) +{ + cmpk_query_cfg_t rx_query_cfg; /* */ + + + rx_query_cfg.cfg_action = (pmsg[4] & 0x80000000)>>31; + rx_query_cfg.cfg_type = (pmsg[4] & 0x60) >> 5; + rx_query_cfg.cfg_size = (pmsg[4] & 0x18) >> 3; + rx_query_cfg.cfg_page = (pmsg[6] & 0x0F) >> 0; + rx_query_cfg.cfg_offset = pmsg[7]; + rx_query_cfg.value = (pmsg[8] << 24) | (pmsg[9] << 16) | + (pmsg[10] << 8) | (pmsg[11] << 0); + rx_query_cfg.mask = (pmsg[12] << 24) | (pmsg[13] << 16) | + (pmsg[14] << 8) | (pmsg[15] << 0); + +} /* cmpk_Handle_Query_Config_Rx */ + + +static void cmpk_count_tx_status(struct net_device *dev, + struct cmpk_tx_status *pstx_status) +{ + struct r8192_priv *priv = rtllib_priv(dev); + +#ifdef ENABLE_PS + + enum rt_rf_power_state rtstate; + + pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, + (pu1Byte)(&rtState)); + + if (rtState == eRfOff) + return; +#endif + + priv->stats.txfeedbackok += pstx_status->txok; + priv->stats.txoktotal += pstx_status->txok; + + priv->stats.txfeedbackfail += pstx_status->txfail; + priv->stats.txerrtotal += pstx_status->txfail; + + priv->stats.txretrycount += pstx_status->txretry; + priv->stats.txfeedbackretry += pstx_status->txretry; + + + priv->stats.txmulticast += pstx_status->txmcok; + priv->stats.txbroadcast += pstx_status->txbcok; + priv->stats.txunicast += pstx_status->txucok; + + priv->stats.txerrmulticast += pstx_status->txmcfail; + priv->stats.txerrbroadcast += pstx_status->txbcfail; + priv->stats.txerrunicast += pstx_status->txucfail; + + priv->stats.txbytesmulticast += pstx_status->txmclength; + priv->stats.txbytesbroadcast += pstx_status->txbclength; + priv->stats.txbytesunicast += pstx_status->txuclength; + + priv->stats.last_packet_rate = pstx_status->rate; +} /* cmpk_CountTxStatus */ + + + +static void cmpk_handle_tx_status(struct net_device *dev, u8 *pmsg) +{ + struct cmpk_tx_status rx_tx_sts; /* */ + + memcpy((void *)&rx_tx_sts, (void *)pmsg, sizeof(struct cmpk_tx_status)); + cmpk_count_tx_status(dev, &rx_tx_sts); +} + +static void cmpk_handle_tx_rate_history(struct net_device *dev, u8 *pmsg) +{ + struct cmpk_tx_rahis *ptxrate; + u8 i, j; + u16 length = sizeof(struct cmpk_tx_rahis); + u32 *ptemp; + struct r8192_priv *priv = rtllib_priv(dev); + + +#ifdef ENABLE_PS + pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, + (pu1Byte)(&rtState)); + + if (rtState == eRfOff) + return; +#endif + + ptemp = (u32 *)pmsg; + + for (i = 0; i < (length / 4); i++) { + u16 temp1, temp2; + + temp1 = ptemp[i] & 0x0000FFFF; + temp2 = ptemp[i] >> 16; + ptemp[i] = (temp1 << 16) | temp2; + } + + ptxrate = (struct cmpk_tx_rahis *)pmsg; + + if (ptxrate == NULL) + return; + + for (i = 0; i < 16; i++) { + if (i < 4) + priv->stats.txrate.cck[i] += ptxrate->cck[i]; + + if (i < 8) + priv->stats.txrate.ofdm[i] += ptxrate->ofdm[i]; + + for (j = 0; j < 4; j++) + priv->stats.txrate.ht_mcs[j][i] += + ptxrate->ht_mcs[j][i]; + } + +} + + +u32 cmpk_message_handle_rx(struct net_device *dev, + struct rtllib_rx_stats *pstats) +{ + struct r8192_priv *priv = rtllib_priv(dev); + int total_length; + u8 cmd_length, exe_cnt = 0; + u8 element_id; + u8 *pcmd_buff; + + RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx()\n"); + + if (pstats == NULL) { + /* Print error message. */ + /*RT_TRACE(COMP_SEND, DebugLevel, + ("\n\r[CMPK]-->Err queue id or pointer"));*/ + return 0; + } + + total_length = pstats->Length; + + pcmd_buff = pstats->virtual_address; + + element_id = pcmd_buff[0]; + + while (total_length > 0 || exe_cnt++ > 100) { + element_id = pcmd_buff[0]; + + switch (element_id) { + case RX_TX_FEEDBACK: + RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():" + "RX_TX_FEEDBACK\n"); + cmpk_handle_tx_feedback(dev, pcmd_buff); + cmd_length = CMPK_RX_TX_FB_SIZE; + break; + case RX_INTERRUPT_STATUS: + RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():" + "RX_INTERRUPT_STATUS\n"); + cmpk_handle_interrupt_status(dev, pcmd_buff); + cmd_length = sizeof(struct cmpk_intr_sta); + break; + case BOTH_QUERY_CONFIG: + RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():" + "BOTH_QUERY_CONFIG\n"); + cmpk_handle_query_config_rx(dev, pcmd_buff); + cmd_length = CMPK_BOTH_QUERY_CONFIG_SIZE; + break; + case RX_TX_STATUS: + RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():" + "RX_TX_STATUS\n"); + cmpk_handle_tx_status(dev, pcmd_buff); + cmd_length = CMPK_RX_TX_STS_SIZE; + break; + case RX_TX_PER_PKT_FEEDBACK: + RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():" + "RX_TX_PER_PKT_FEEDBACK\n"); + cmd_length = CMPK_RX_TX_FB_SIZE; + break; + case RX_TX_RATE_HISTORY: + RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():" + "RX_TX_HISTORY\n"); + cmpk_handle_tx_rate_history(dev, pcmd_buff); + cmd_length = CMPK_TX_RAHIS_SIZE; + break; + default: + + RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():" + "unknow CMD Element\n"); + return 1; + } + + priv->stats.rxcmdpkt[element_id]++; + + total_length -= cmd_length; + pcmd_buff += cmd_length; + } + return 1; +} diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_cmdpkt.h b/drivers/staging/rtl8192e/rtl8192e/r8192E_cmdpkt.h new file mode 100644 index 000000000000..23219e17e5a1 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_cmdpkt.h @@ -0,0 +1,159 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ +#ifndef R819XUSB_CMDPKT_H +#define R819XUSB_CMDPKT_H +#define CMPK_RX_TX_FB_SIZE sizeof(struct cmpk_txfb) +#define CMPK_TX_SET_CONFIG_SIZE sizeof(struct cmpk_set_cfg) +#define CMPK_BOTH_QUERY_CONFIG_SIZE sizeof(struct cmpk_set_cfg) +#define CMPK_RX_TX_STS_SIZE sizeof(struct cmpk_tx_status) +#define CMPK_RX_DBG_MSG_SIZE sizeof(struct cmpk_rx_dbginfo) +#define CMPK_TX_RAHIS_SIZE sizeof(struct cmpk_tx_rahis) + +#define ISR_TxBcnOk BIT27 +#define ISR_TxBcnErr BIT26 +#define ISR_BcnTimerIntr BIT13 + + +struct cmpk_txfb { + u8 element_id; + u8 length; + u8 TID:4; /* */ + u8 fail_reason:3; /* */ + u8 tok:1; + u8 reserve1:4; /* */ + u8 pkt_type:2; /* */ + u8 bandwidth:1; /* */ + u8 qos_pkt:1; /* */ + + u8 reserve2; /* */ + u8 retry_cnt; /* */ + u16 pkt_id; /* */ + + u16 seq_num; /* */ + u8 s_rate; + u8 f_rate; + + u8 s_rts_rate; /* */ + u8 f_rts_rate; /* */ + u16 pkt_length; /* */ + + u16 reserve3; /* */ + u16 duration; /* */ +}; + +struct cmpk_intr_sta { + u8 element_id; + u8 length; + u16 reserve; + u32 interrupt_status; +}; + + +struct cmpk_set_cfg { + u8 element_id; + u8 length; + u16 reserve1; + u8 cfg_reserve1:3; + u8 cfg_size:2; + u8 cfg_type:2; + u8 cfg_action:1; + u8 cfg_reserve2; + u8 cfg_page:4; + u8 cfg_reserve3:4; + u8 cfg_offset; + u32 value; + u32 mask; +}; + +#define cmpk_query_cfg_t struct cmpk_set_cfg + +struct cmpk_tx_status { + u16 reserve1; + u8 length; + u8 element_id; + + u16 txfail; + u16 txok; + + u16 txmcok; + u16 txretry; + + u16 txucok; + u16 txbcok; + + u16 txbcfail; + u16 txmcfail; + + u16 reserve2; + u16 txucfail; + + u32 txmclength; + u32 txbclength; + u32 txuclength; + + u16 reserve3_23; + u8 reserve3_1; + u8 rate; +} __packed; + +struct cmpk_rx_dbginfo { + u16 reserve1; + u8 length; + u8 element_id; + + +}; + +struct cmpk_tx_rahis { + u8 element_id; + u8 length; + u16 reserved1; + + u16 cck[4]; + + u16 ofdm[8]; + + + + + + u16 ht_mcs[4][16]; + +} __packed; + +enum cmpk_element { + RX_TX_FEEDBACK = 0, + RX_INTERRUPT_STATUS = 1, + TX_SET_CONFIG = 2, + BOTH_QUERY_CONFIG = 3, + RX_TX_STATUS = 4, + RX_DBGINFO_FEEDBACK = 5, + RX_TX_PER_PKT_FEEDBACK = 6, + RX_TX_RATE_HISTORY = 7, + RX_CMD_ELE_MAX +}; + +extern u32 cmpk_message_handle_rx(struct net_device *dev, + struct rtllib_rx_stats *pstats); +extern bool cmpk_message_handle_tx(struct net_device *dev, + u8 *codevirtualaddress, u32 packettype, + u32 buffer_len); + + +#endif diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c b/drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c new file mode 100644 index 000000000000..808aab6fa5ef --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c @@ -0,0 +1,2395 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * Based on the r8180 driver, which is: + * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ +#include "rtl_core.h" +#include "r8192E_phy.h" +#include "r8192E_phyreg.h" +#include "r8190P_rtl8256.h" +#include "r8192E_cmdpkt.h" +#include "rtl_dm.h" +#include "rtl_wx.h" + +extern int WDCAPARA_ADD[]; + +void rtl8192e_start_beacon(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + struct rtllib_network *net = &priv->rtllib->current_network; + u16 BcnTimeCfg = 0; + u16 BcnCW = 6; + u16 BcnIFS = 0xf; + + DMESG("Enabling beacon TX"); + rtl8192_irq_disable(dev); + + write_nic_word(dev, ATIMWND, 2); + + write_nic_word(dev, BCN_INTERVAL, net->beacon_interval); + write_nic_word(dev, BCN_DRV_EARLY_INT, 10); + write_nic_word(dev, BCN_DMATIME, 256); + + write_nic_byte(dev, BCN_ERR_THRESH, 100); + + BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT; + BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS; + write_nic_word(dev, BCN_TCFG, BcnTimeCfg); + rtl8192_irq_enable(dev); +} + +static void rtl8192e_update_msr(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u8 msr; + enum led_ctl_mode LedAction = LED_CTL_NO_LINK; + msr = read_nic_byte(dev, MSR); + msr &= ~MSR_LINK_MASK; + + switch (priv->rtllib->iw_mode) { + case IW_MODE_INFRA: + if (priv->rtllib->state == RTLLIB_LINKED) + msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT); + else + msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); + LedAction = LED_CTL_LINK; + break; + case IW_MODE_ADHOC: + if (priv->rtllib->state == RTLLIB_LINKED) + msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT); + else + msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); + break; + case IW_MODE_MASTER: + if (priv->rtllib->state == RTLLIB_LINKED) + msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT); + else + msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); + break; + default: + break; + } + + write_nic_byte(dev, MSR, msr); + if (priv->rtllib->LedControlHandler) + priv->rtllib->LedControlHandler(dev, LedAction); +} + +void rtl8192e_SetHwReg(struct net_device *dev, u8 variable, u8 *val) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + switch (variable) { + case HW_VAR_BSSID: + write_nic_dword(dev, BSSIDR, ((u32 *)(val))[0]); + write_nic_word(dev, BSSIDR+2, ((u16 *)(val+2))[0]); + break; + + case HW_VAR_MEDIA_STATUS: + { + enum rt_op_mode OpMode = *((enum rt_op_mode *)(val)); + enum led_ctl_mode LedAction = LED_CTL_NO_LINK; + u8 btMsr = read_nic_byte(dev, MSR); + + btMsr &= 0xfc; + + switch (OpMode) { + case RT_OP_MODE_INFRASTRUCTURE: + btMsr |= MSR_INFRA; + LedAction = LED_CTL_LINK; + break; + + case RT_OP_MODE_IBSS: + btMsr |= MSR_ADHOC; + break; + + case RT_OP_MODE_AP: + btMsr |= MSR_AP; + LedAction = LED_CTL_LINK; + break; + + default: + btMsr |= MSR_NOLINK; + break; + } + + write_nic_byte(dev, MSR, btMsr); + + } + break; + + case HW_VAR_CECHK_BSSID: + { + u32 RegRCR, Type; + + Type = ((u8 *)(val))[0]; + RegRCR = read_nic_dword(dev, RCR); + priv->ReceiveConfig = RegRCR; + + if (Type == true) + RegRCR |= (RCR_CBSSID); + else if (Type == false) + RegRCR &= (~RCR_CBSSID); + + write_nic_dword(dev, RCR, RegRCR); + priv->ReceiveConfig = RegRCR; + + } + break; + + case HW_VAR_SLOT_TIME: + + priv->slot_time = val[0]; + write_nic_byte(dev, SLOT_TIME, val[0]); + + break; + + case HW_VAR_ACK_PREAMBLE: + { + u32 regTmp; + priv->short_preamble = (bool)(*(u8 *)val); + regTmp = priv->basic_rate; + if (priv->short_preamble) + regTmp |= BRSR_AckShortPmb; + write_nic_dword(dev, RRSR, regTmp); + break; + } + + case HW_VAR_CPU_RST: + write_nic_dword(dev, CPU_GEN, ((u32 *)(val))[0]); + break; + + case HW_VAR_AC_PARAM: + { + u8 pAcParam = *((u8 *)val); + u32 eACI = pAcParam; + u8 u1bAIFS; + u32 u4bAcParam; + u8 mode = priv->rtllib->mode; + struct rtllib_qos_parameters *qos_parameters = + &priv->rtllib->current_network.qos_data.parameters; + + u1bAIFS = qos_parameters->aifs[pAcParam] * + ((mode&(IEEE_G|IEEE_N_24G)) ? 9 : 20) + aSifsTime; + + dm_init_edca_turbo(dev); + + u4bAcParam = ((((u32)(qos_parameters->tx_op_limit[pAcParam])) << + AC_PARAM_TXOP_LIMIT_OFFSET) | + (((u32)(qos_parameters->cw_max[pAcParam])) << + AC_PARAM_ECW_MAX_OFFSET) | + (((u32)(qos_parameters->cw_min[pAcParam])) << + AC_PARAM_ECW_MIN_OFFSET) | + (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET)); + + RT_TRACE(COMP_DBG, "%s():HW_VAR_AC_PARAM eACI:%x:%x\n", + __func__, eACI, u4bAcParam); + switch (eACI) { + case AC1_BK: + write_nic_dword(dev, EDCAPARA_BK, u4bAcParam); + break; + + case AC0_BE: + write_nic_dword(dev, EDCAPARA_BE, u4bAcParam); + break; + + case AC2_VI: + write_nic_dword(dev, EDCAPARA_VI, u4bAcParam); + break; + + case AC3_VO: + write_nic_dword(dev, EDCAPARA_VO, u4bAcParam); + break; + + default: + printk(KERN_INFO "SetHwReg8185(): invalid ACI: %d !\n", + eACI); + break; + } + priv->rtllib->SetHwRegHandler(dev, HW_VAR_ACM_CTRL, + (u8 *)(&pAcParam)); + break; + } + + case HW_VAR_ACM_CTRL: + { + struct rtllib_qos_parameters *qos_parameters = + &priv->rtllib->current_network.qos_data.parameters; + u8 pAcParam = *((u8 *)val); + u32 eACI = pAcParam; + union aci_aifsn *pAciAifsn = (union aci_aifsn *) & + (qos_parameters->aifs[0]); + u8 acm = pAciAifsn->f.acm; + u8 AcmCtrl = read_nic_byte(dev, AcmHwCtrl); + + RT_TRACE(COMP_DBG, "===========>%s():HW_VAR_ACM_CTRL:%x\n", + __func__, eACI); + AcmCtrl = AcmCtrl | ((priv->AcmMethod == 2) ? 0x0 : 0x1); + + if (acm) { + switch (eACI) { + case AC0_BE: + AcmCtrl |= AcmHw_BeqEn; + break; + + case AC2_VI: + AcmCtrl |= AcmHw_ViqEn; + break; + + case AC3_VO: + AcmCtrl |= AcmHw_VoqEn; + break; + + default: + RT_TRACE(COMP_QOS, "SetHwReg8185(): [HW_VAR_" + "ACM_CTRL] acm set failed: eACI is " + "%d\n", eACI); + break; + } + } else { + switch (eACI) { + case AC0_BE: + AcmCtrl &= (~AcmHw_BeqEn); + break; + + case AC2_VI: + AcmCtrl &= (~AcmHw_ViqEn); + break; + + case AC3_VO: + AcmCtrl &= (~AcmHw_BeqEn); + break; + + default: + break; + } + } + + RT_TRACE(COMP_QOS, "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write" + " 0x%X\n", AcmCtrl); + write_nic_byte(dev, AcmHwCtrl, AcmCtrl); + break; + } + + case HW_VAR_SIFS: + write_nic_byte(dev, SIFS, val[0]); + write_nic_byte(dev, SIFS+1, val[0]); + break; + + case HW_VAR_RF_TIMING: + { + u8 Rf_Timing = *((u8 *)val); + write_nic_byte(dev, rFPGA0_RFTiming1, Rf_Timing); + break; + } + + default: + break; + } + +} + +static void rtl8192_read_eeprom_info(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + u8 tempval; + u8 ICVer8192, ICVer8256; + u16 i, usValue, IC_Version; + u16 EEPROMId; + u8 bMac_Tmp_Addr[6] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01}; + RT_TRACE(COMP_INIT, "====> rtl8192_read_eeprom_info\n"); + + EEPROMId = eprom_read(dev, 0); + if (EEPROMId != RTL8190_EEPROM_ID) { + RT_TRACE(COMP_ERR, "EEPROM ID is invalid:%x, %x\n", + EEPROMId, RTL8190_EEPROM_ID); + priv->AutoloadFailFlag = true; + } else { + priv->AutoloadFailFlag = false; + } + + if (!priv->AutoloadFailFlag) { + priv->eeprom_vid = eprom_read(dev, (EEPROM_VID >> 1)); + priv->eeprom_did = eprom_read(dev, (EEPROM_DID >> 1)); + + usValue = eprom_read(dev, (u16)(EEPROM_Customer_ID>>1)) >> 8; + priv->eeprom_CustomerID = (u8)(usValue & 0xff); + usValue = eprom_read(dev, (EEPROM_ICVersion_ChannelPlan>>1)); + priv->eeprom_ChannelPlan = usValue&0xff; + IC_Version = ((usValue&0xff00)>>8); + + ICVer8192 = (IC_Version&0xf); + ICVer8256 = ((IC_Version&0xf0)>>4); + RT_TRACE(COMP_INIT, "\nICVer8192 = 0x%x\n", ICVer8192); + RT_TRACE(COMP_INIT, "\nICVer8256 = 0x%x\n", ICVer8256); + if (ICVer8192 == 0x2) { + if (ICVer8256 == 0x5) + priv->card_8192_version = VERSION_8190_BE; + } + switch (priv->card_8192_version) { + case VERSION_8190_BD: + case VERSION_8190_BE: + break; + default: + priv->card_8192_version = VERSION_8190_BD; + break; + } + RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n", + priv->card_8192_version); + } else { + priv->card_8192_version = VERSION_8190_BD; + priv->eeprom_vid = 0; + priv->eeprom_did = 0; + priv->eeprom_CustomerID = 0; + priv->eeprom_ChannelPlan = 0; + RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n", 0xff); + } + + RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid); + RT_TRACE(COMP_INIT, "EEPROM DID = 0x%4x\n", priv->eeprom_did); + RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", + priv->eeprom_CustomerID); + + if (!priv->AutoloadFailFlag) { + for (i = 0; i < 6; i += 2) { + usValue = eprom_read(dev, + (u16)((EEPROM_NODE_ADDRESS_BYTE_0 + i) >> 1)); + *(u16 *)(&dev->dev_addr[i]) = usValue; + } + } else { + memcpy(dev->dev_addr, bMac_Tmp_Addr, 6); + } + + RT_TRACE(COMP_INIT, "Permanent Address = %pM\n", + dev->dev_addr); + + if (priv->card_8192_version > VERSION_8190_BD) + priv->bTXPowerDataReadFromEEPORM = true; + else + priv->bTXPowerDataReadFromEEPORM = false; + + priv->rf_type = RTL819X_DEFAULT_RF_TYPE; + + if (priv->card_8192_version > VERSION_8190_BD) { + if (!priv->AutoloadFailFlag) { + tempval = (eprom_read(dev, (EEPROM_RFInd_PowerDiff >> + 1))) & 0xff; + priv->EEPROMLegacyHTTxPowerDiff = tempval & 0xf; + + if (tempval&0x80) + priv->rf_type = RF_1T2R; + else + priv->rf_type = RF_2T4R; + } else { + priv->EEPROMLegacyHTTxPowerDiff = 0x04; + } + RT_TRACE(COMP_INIT, "EEPROMLegacyHTTxPowerDiff = %d\n", + priv->EEPROMLegacyHTTxPowerDiff); + + if (!priv->AutoloadFailFlag) + priv->EEPROMThermalMeter = (u8)(((eprom_read(dev, + (EEPROM_ThermalMeter>>1))) & + 0xff00)>>8); + else + priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter; + RT_TRACE(COMP_INIT, "ThermalMeter = %d\n", + priv->EEPROMThermalMeter); + priv->TSSI_13dBm = priv->EEPROMThermalMeter * 100; + + if (priv->epromtype == EEPROM_93C46) { + if (!priv->AutoloadFailFlag) { + usValue = eprom_read(dev, + (EEPROM_TxPwDiff_CrystalCap >> 1)); + priv->EEPROMAntPwDiff = (usValue&0x0fff); + priv->EEPROMCrystalCap = (u8)((usValue & 0xf000) + >> 12); + } else { + priv->EEPROMAntPwDiff = + EEPROM_Default_AntTxPowerDiff; + priv->EEPROMCrystalCap = + EEPROM_Default_TxPwDiff_CrystalCap; + } + RT_TRACE(COMP_INIT, "EEPROMAntPwDiff = %d\n", + priv->EEPROMAntPwDiff); + RT_TRACE(COMP_INIT, "EEPROMCrystalCap = %d\n", + priv->EEPROMCrystalCap); + + for (i = 0; i < 14; i += 2) { + if (!priv->AutoloadFailFlag) + usValue = eprom_read(dev, + (u16)((EEPROM_TxPwIndex_CCK + + i) >> 1)); + else + usValue = EEPROM_Default_TxPower; + *((u16 *)(&priv->EEPROMTxPowerLevelCCK[i])) = + usValue; + RT_TRACE(COMP_INIT, "CCK Tx Power Level, Index" + " %d = 0x%02x\n", i, + priv->EEPROMTxPowerLevelCCK[i]); + RT_TRACE(COMP_INIT, "CCK Tx Power Level, Index" + " %d = 0x%02x\n", i+1, + priv->EEPROMTxPowerLevelCCK[i+1]); + } + for (i = 0; i < 14; i += 2) { + if (!priv->AutoloadFailFlag) + usValue = eprom_read(dev, + (u16)((EEPROM_TxPwIndex_OFDM_24G + + i) >> 1)); + else + usValue = EEPROM_Default_TxPower; + *((u16 *)(&priv->EEPROMTxPowerLevelOFDM24G[i])) + = usValue; + RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level," + " Index %d = 0x%02x\n", i, + priv->EEPROMTxPowerLevelOFDM24G[i]); + RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level," + " Index %d = 0x%02x\n", i + 1, + priv->EEPROMTxPowerLevelOFDM24G[i+1]); + } + } + if (priv->epromtype == EEPROM_93C46) { + for (i = 0; i < 14; i++) { + priv->TxPowerLevelCCK[i] = + priv->EEPROMTxPowerLevelCCK[i]; + priv->TxPowerLevelOFDM24G[i] = + priv->EEPROMTxPowerLevelOFDM24G[i]; + } + priv->LegacyHTTxPowerDiff = + priv->EEPROMLegacyHTTxPowerDiff; + priv->AntennaTxPwDiff[0] = (priv->EEPROMAntPwDiff & + 0xf); + priv->AntennaTxPwDiff[1] = ((priv->EEPROMAntPwDiff & + 0xf0)>>4); + priv->AntennaTxPwDiff[2] = ((priv->EEPROMAntPwDiff & + 0xf00)>>8); + priv->CrystalCap = priv->EEPROMCrystalCap; + priv->ThermalMeter[0] = (priv->EEPROMThermalMeter & + 0xf); + priv->ThermalMeter[1] = ((priv->EEPROMThermalMeter & + 0xf0)>>4); + } else if (priv->epromtype == EEPROM_93C56) { + + for (i = 0; i < 3; i++) { + priv->TxPowerLevelCCK_A[i] = + priv->EEPROMRfACCKChnl1TxPwLevel[0]; + priv->TxPowerLevelOFDM24G_A[i] = + priv->EEPROMRfAOfdmChnlTxPwLevel[0]; + priv->TxPowerLevelCCK_C[i] = + priv->EEPROMRfCCCKChnl1TxPwLevel[0]; + priv->TxPowerLevelOFDM24G_C[i] = + priv->EEPROMRfCOfdmChnlTxPwLevel[0]; + } + for (i = 3; i < 9; i++) { + priv->TxPowerLevelCCK_A[i] = + priv->EEPROMRfACCKChnl1TxPwLevel[1]; + priv->TxPowerLevelOFDM24G_A[i] = + priv->EEPROMRfAOfdmChnlTxPwLevel[1]; + priv->TxPowerLevelCCK_C[i] = + priv->EEPROMRfCCCKChnl1TxPwLevel[1]; + priv->TxPowerLevelOFDM24G_C[i] = + priv->EEPROMRfCOfdmChnlTxPwLevel[1]; + } + for (i = 9; i < 14; i++) { + priv->TxPowerLevelCCK_A[i] = + priv->EEPROMRfACCKChnl1TxPwLevel[2]; + priv->TxPowerLevelOFDM24G_A[i] = + priv->EEPROMRfAOfdmChnlTxPwLevel[2]; + priv->TxPowerLevelCCK_C[i] = + priv->EEPROMRfCCCKChnl1TxPwLevel[2]; + priv->TxPowerLevelOFDM24G_C[i] = + priv->EEPROMRfCOfdmChnlTxPwLevel[2]; + } + for (i = 0; i < 14; i++) + RT_TRACE(COMP_INIT, "priv->TxPowerLevelCCK_A" + "[%d] = 0x%x\n", i, + priv->TxPowerLevelCCK_A[i]); + for (i = 0; i < 14; i++) + RT_TRACE(COMP_INIT, "priv->TxPowerLevelOFDM" + "24G_A[%d] = 0x%x\n", i, + priv->TxPowerLevelOFDM24G_A[i]); + for (i = 0; i < 14; i++) + RT_TRACE(COMP_INIT, "priv->TxPowerLevelCCK_C" + "[%d] = 0x%x\n", i, + priv->TxPowerLevelCCK_C[i]); + for (i = 0; i < 14; i++) + RT_TRACE(COMP_INIT, "priv->TxPowerLevelOFDM" + "24G_C[%d] = 0x%x\n", i, + priv->TxPowerLevelOFDM24G_C[i]); + priv->LegacyHTTxPowerDiff = + priv->EEPROMLegacyHTTxPowerDiff; + priv->AntennaTxPwDiff[0] = 0; + priv->AntennaTxPwDiff[1] = 0; + priv->AntennaTxPwDiff[2] = 0; + priv->CrystalCap = priv->EEPROMCrystalCap; + priv->ThermalMeter[0] = (priv->EEPROMThermalMeter & + 0xf); + priv->ThermalMeter[1] = ((priv->EEPROMThermalMeter & + 0xf0)>>4); + } + } + + if (priv->rf_type == RF_1T2R) { + /* no matter what checkpatch says, the braces are needed */ + RT_TRACE(COMP_INIT, "\n1T2R config\n"); + } else if (priv->rf_type == RF_2T4R) { + RT_TRACE(COMP_INIT, "\n2T4R config\n"); + } + + init_rate_adaptive(dev); + + priv->rf_chip = RF_8256; + + if (priv->RegChannelPlan == 0xf) + priv->ChannelPlan = priv->eeprom_ChannelPlan; + else + priv->ChannelPlan = priv->RegChannelPlan; + + if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304) + priv->CustomerID = RT_CID_DLINK; + + switch (priv->eeprom_CustomerID) { + case EEPROM_CID_DEFAULT: + priv->CustomerID = RT_CID_DEFAULT; + break; + case EEPROM_CID_CAMEO: + priv->CustomerID = RT_CID_819x_CAMEO; + break; + case EEPROM_CID_RUNTOP: + priv->CustomerID = RT_CID_819x_RUNTOP; + break; + case EEPROM_CID_NetCore: + priv->CustomerID = RT_CID_819x_Netcore; + break; + case EEPROM_CID_TOSHIBA: + priv->CustomerID = RT_CID_TOSHIBA; + if (priv->eeprom_ChannelPlan&0x80) + priv->ChannelPlan = priv->eeprom_ChannelPlan&0x7f; + else + priv->ChannelPlan = 0x0; + RT_TRACE(COMP_INIT, "Toshiba ChannelPlan = 0x%x\n", + priv->ChannelPlan); + break; + case EEPROM_CID_Nettronix: + priv->ScanDelay = 100; + priv->CustomerID = RT_CID_Nettronix; + break; + case EEPROM_CID_Pronet: + priv->CustomerID = RT_CID_PRONET; + break; + case EEPROM_CID_DLINK: + priv->CustomerID = RT_CID_DLINK; + break; + + case EEPROM_CID_WHQL: + break; + default: + break; + } + + if (priv->ChannelPlan > CHANNEL_PLAN_LEN - 1) + priv->ChannelPlan = 0; + priv->ChannelPlan = COUNTRY_CODE_WORLD_WIDE_13; + + if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304) + priv->rtllib->bSupportRemoteWakeUp = true; + else + priv->rtllib->bSupportRemoteWakeUp = false; + + RT_TRACE(COMP_INIT, "RegChannelPlan(%d)\n", priv->RegChannelPlan); + RT_TRACE(COMP_INIT, "ChannelPlan = %d\n", priv->ChannelPlan); + RT_TRACE(COMP_TRACE, "<==== ReadAdapterInfo\n"); +} + +void rtl8192_get_eeprom_size(struct net_device *dev) +{ + u16 curCR; + struct r8192_priv *priv = rtllib_priv(dev); + + RT_TRACE(COMP_INIT, "===========>%s()\n", __func__); + curCR = read_nic_dword(dev, EPROM_CMD); + RT_TRACE(COMP_INIT, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD, + curCR); + priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EEPROM_93C56 : + EEPROM_93C46; + RT_TRACE(COMP_INIT, "<===========%s(), epromtype:%d\n", __func__, + priv->epromtype); + rtl8192_read_eeprom_info(dev); +} + +static void rtl8192_hwconfig(struct net_device *dev) +{ + u32 regRATR = 0, regRRSR = 0; + u8 regBwOpMode = 0, regTmp = 0; + struct r8192_priv *priv = rtllib_priv(dev); + + switch (priv->rtllib->mode) { + case WIRELESS_MODE_B: + regBwOpMode = BW_OPMODE_20MHZ; + regRATR = RATE_ALL_CCK; + regRRSR = RATE_ALL_CCK; + break; + case WIRELESS_MODE_A: + regBwOpMode = BW_OPMODE_5G | BW_OPMODE_20MHZ; + regRATR = RATE_ALL_OFDM_AG; + regRRSR = RATE_ALL_OFDM_AG; + break; + case WIRELESS_MODE_G: + regBwOpMode = BW_OPMODE_20MHZ; + regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + break; + case WIRELESS_MODE_AUTO: + case WIRELESS_MODE_N_24G: + regBwOpMode = BW_OPMODE_20MHZ; + regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | + RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; + regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + break; + case WIRELESS_MODE_N_5G: + regBwOpMode = BW_OPMODE_5G; + regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | + RATE_ALL_OFDM_2SS; + regRRSR = RATE_ALL_OFDM_AG; + break; + default: + regBwOpMode = BW_OPMODE_20MHZ; + regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + break; + } + + write_nic_byte(dev, BW_OPMODE, regBwOpMode); + { + u32 ratr_value = 0; + ratr_value = regRATR; + if (priv->rf_type == RF_1T2R) + ratr_value &= ~(RATE_ALL_OFDM_2SS); + write_nic_dword(dev, RATR0, ratr_value); + write_nic_byte(dev, UFWP, 1); + } + regTmp = read_nic_byte(dev, 0x313); + regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff); + write_nic_dword(dev, RRSR, regRRSR); + + write_nic_word(dev, RETRY_LIMIT, + priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT | + priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT); +} + +bool rtl8192_adapter_start(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u32 ulRegRead; + bool rtStatus = true; + u8 tmpvalue; + u8 ICVersion, SwitchingRegulatorOutput; + bool bfirmwareok = true; + u32 tmpRegA, tmpRegC, TempCCk; + int i = 0; + u32 retry_times = 0; + + RT_TRACE(COMP_INIT, "====>%s()\n", __func__); + priv->being_init_adapter = true; + +start: + rtl8192_pci_resetdescring(dev); + priv->Rf_Mode = RF_OP_By_SW_3wire; + if (priv->ResetProgress == RESET_TYPE_NORESET) { + write_nic_byte(dev, ANAPAR, 0x37); + mdelay(500); + } + priv->pFirmware->firmware_status = FW_STATUS_0_INIT; + + if (priv->RegRfOff == true) + priv->rtllib->eRFPowerState = eRfOff; + + ulRegRead = read_nic_dword(dev, CPU_GEN); + if (priv->pFirmware->firmware_status == FW_STATUS_0_INIT) + ulRegRead |= CPU_GEN_SYSTEM_RESET; + else if (priv->pFirmware->firmware_status == FW_STATUS_5_READY) + ulRegRead |= CPU_GEN_FIRMWARE_RESET; + else + RT_TRACE(COMP_ERR, "ERROR in %s(): undefined firmware state(%d)" + "\n", __func__, priv->pFirmware->firmware_status); + + write_nic_dword(dev, CPU_GEN, ulRegRead); + + ICVersion = read_nic_byte(dev, IC_VERRSION); + if (ICVersion >= 0x4) { + SwitchingRegulatorOutput = read_nic_byte(dev, SWREGULATOR); + if (SwitchingRegulatorOutput != 0xb8) { + write_nic_byte(dev, SWREGULATOR, 0xa8); + mdelay(1); + write_nic_byte(dev, SWREGULATOR, 0xb8); + } + } + RT_TRACE(COMP_INIT, "BB Config Start!\n"); + rtStatus = rtl8192_BBConfig(dev); + if (rtStatus != true) { + RT_TRACE(COMP_ERR, "BB Config failed\n"); + return rtStatus; + } + RT_TRACE(COMP_INIT, "BB Config Finished!\n"); + + priv->LoopbackMode = RTL819X_NO_LOOPBACK; + if (priv->ResetProgress == RESET_TYPE_NORESET) { + ulRegRead = read_nic_dword(dev, CPU_GEN); + if (priv->LoopbackMode == RTL819X_NO_LOOPBACK) + ulRegRead = ((ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) | + CPU_GEN_NO_LOOPBACK_SET); + else if (priv->LoopbackMode == RTL819X_MAC_LOOPBACK) + ulRegRead |= CPU_CCK_LOOPBACK; + else + RT_TRACE(COMP_ERR, "Serious error: wrong loopback" + " mode setting\n"); + + write_nic_dword(dev, CPU_GEN, ulRegRead); + + udelay(500); + } + rtl8192_hwconfig(dev); + write_nic_byte(dev, CMDR, CR_RE | CR_TE); + + write_nic_byte(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) | + (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT))); + write_nic_dword(dev, MAC0, ((u32 *)dev->dev_addr)[0]); + write_nic_word(dev, MAC4, ((u16 *)(dev->dev_addr + 4))[0]); + write_nic_dword(dev, RCR, priv->ReceiveConfig); + + write_nic_dword(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK << + RSVD_FW_QUEUE_PAGE_BK_SHIFT | + NUM_OF_PAGE_IN_FW_QUEUE_BE << + RSVD_FW_QUEUE_PAGE_BE_SHIFT | + NUM_OF_PAGE_IN_FW_QUEUE_VI << + RSVD_FW_QUEUE_PAGE_VI_SHIFT | + NUM_OF_PAGE_IN_FW_QUEUE_VO << + RSVD_FW_QUEUE_PAGE_VO_SHIFT); + write_nic_dword(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT << + RSVD_FW_QUEUE_PAGE_MGNT_SHIFT); + write_nic_dword(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW | + NUM_OF_PAGE_IN_FW_QUEUE_BCN << + RSVD_FW_QUEUE_PAGE_BCN_SHIFT| + NUM_OF_PAGE_IN_FW_QUEUE_PUB << + RSVD_FW_QUEUE_PAGE_PUB_SHIFT); + + rtl8192_tx_enable(dev); + rtl8192_rx_enable(dev); + ulRegRead = (0xFFF00000 & read_nic_dword(dev, RRSR)) | + RATE_ALL_OFDM_AG | RATE_ALL_CCK; + write_nic_dword(dev, RRSR, ulRegRead); + write_nic_dword(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK)); + + write_nic_byte(dev, ACK_TIMEOUT, 0x30); + + if (priv->ResetProgress == RESET_TYPE_NORESET) + rtl8192_SetWirelessMode(dev, priv->rtllib->mode); + CamResetAllEntry(dev); + { + u8 SECR_value = 0x0; + SECR_value |= SCR_TxEncEnable; + SECR_value |= SCR_RxDecEnable; + SECR_value |= SCR_NoSKMC; + write_nic_byte(dev, SECR, SECR_value); + } + write_nic_word(dev, ATIMWND, 2); + write_nic_word(dev, BCN_INTERVAL, 100); + { + int i; + for (i = 0; i < QOS_QUEUE_NUM; i++) + write_nic_dword(dev, WDCAPARA_ADD[i], 0x005e4332); + } + write_nic_byte(dev, 0xbe, 0xc0); + + rtl8192_phy_configmac(dev); + + if (priv->card_8192_version > (u8) VERSION_8190_BD) { + rtl8192_phy_getTxPower(dev); + rtl8192_phy_setTxPower(dev, priv->chan); + } + + tmpvalue = read_nic_byte(dev, IC_VERRSION); + priv->IC_Cut = tmpvalue; + RT_TRACE(COMP_INIT, "priv->IC_Cut= 0x%x\n", priv->IC_Cut); + if (priv->IC_Cut >= IC_VersionCut_D) { + if (priv->IC_Cut == IC_VersionCut_D) { + /* no matter what checkpatch says, braces are needed */ + RT_TRACE(COMP_INIT, "D-cut\n"); + } else if (priv->IC_Cut == IC_VersionCut_E) { + RT_TRACE(COMP_INIT, "E-cut\n"); + } + } else { + RT_TRACE(COMP_INIT, "Before C-cut\n"); + } + + RT_TRACE(COMP_INIT, "Load Firmware!\n"); + bfirmwareok = init_firmware(dev); + if (!bfirmwareok) { + if (retry_times < 10) { + retry_times++; + goto start; + } else { + rtStatus = false; + goto end; + } + } + RT_TRACE(COMP_INIT, "Load Firmware finished!\n"); + if (priv->ResetProgress == RESET_TYPE_NORESET) { + RT_TRACE(COMP_INIT, "RF Config Started!\n"); + rtStatus = rtl8192_phy_RFConfig(dev); + if (rtStatus != true) { + RT_TRACE(COMP_ERR, "RF Config failed\n"); + return rtStatus; + } + RT_TRACE(COMP_INIT, "RF Config Finished!\n"); + } + rtl8192_phy_updateInitGain(dev); + + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1); + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1); + + write_nic_byte(dev, 0x87, 0x0); + + if (priv->RegRfOff == true) { + RT_TRACE((COMP_INIT | COMP_RF | COMP_POWER), + "%s(): Turn off RF for RegRfOff ----------\n", + __func__); + MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_SW, true); + } else if (priv->rtllib->RfOffReason > RF_CHANGE_BY_PS) { + RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): Turn off RF for" + " RfOffReason(%d) ----------\n", __func__, + priv->rtllib->RfOffReason); + MgntActSet_RF_State(dev, eRfOff, priv->rtllib->RfOffReason, + true); + } else if (priv->rtllib->RfOffReason >= RF_CHANGE_BY_IPS) { + RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): Turn off RF for" + " RfOffReason(%d) ----------\n", __func__, + priv->rtllib->RfOffReason); + MgntActSet_RF_State(dev, eRfOff, priv->rtllib->RfOffReason, + true); + } else { + RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): RF-ON\n", + __func__); + priv->rtllib->eRFPowerState = eRfOn; + priv->rtllib->RfOffReason = 0; + } + + if (priv->rtllib->FwRWRF) + priv->Rf_Mode = RF_OP_By_FW; + else + priv->Rf_Mode = RF_OP_By_SW_3wire; + + if (priv->ResetProgress == RESET_TYPE_NORESET) { + dm_initialize_txpower_tracking(dev); + + if (priv->IC_Cut >= IC_VersionCut_D) { + tmpRegA = rtl8192_QueryBBReg(dev, + rOFDM0_XATxIQImbalance, bMaskDWord); + tmpRegC = rtl8192_QueryBBReg(dev, + rOFDM0_XCTxIQImbalance, bMaskDWord); + for (i = 0; i < TxBBGainTableLength; i++) { + if (tmpRegA == + priv->txbbgain_table[i].txbbgain_value) { + priv->rfa_txpowertrackingindex = (u8)i; + priv->rfa_txpowertrackingindex_real = + (u8)i; + priv->rfa_txpowertracking_default = + priv->rfa_txpowertrackingindex; + break; + } + } + + TempCCk = rtl8192_QueryBBReg(dev, + rCCK0_TxFilter1, bMaskByte2); + + for (i = 0; i < CCKTxBBGainTableLength; i++) { + if (TempCCk == priv->cck_txbbgain_table[i].ccktxbb_valuearray[0]) { + priv->CCKPresentAttentuation_20Mdefault = (u8)i; + break; + } + } + priv->CCKPresentAttentuation_40Mdefault = 0; + priv->CCKPresentAttentuation_difference = 0; + priv->CCKPresentAttentuation = + priv->CCKPresentAttentuation_20Mdefault; + RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpower" + "trackingindex_initial = %d\n", + priv->rfa_txpowertrackingindex); + RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpower" + "trackingindex_real__initial = %d\n", + priv->rfa_txpowertrackingindex_real); + RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresent" + "Attentuation_difference_initial = %d\n", + priv->CCKPresentAttentuation_difference); + RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresent" + "Attentuation_initial = %d\n", + priv->CCKPresentAttentuation); + priv->btxpower_tracking = false; + } + } + rtl8192_irq_enable(dev); +end: + priv->being_init_adapter = false; + return rtStatus; +} + +static void rtl8192_net_update(struct net_device *dev) +{ + + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_network *net; + u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf; + u16 rate_config = 0; + + net = &priv->rtllib->current_network; + rtl8192_config_rate(dev, &rate_config); + priv->dot11CurrentPreambleMode = PREAMBLE_AUTO; + priv->basic_rate = rate_config &= 0x15f; + write_nic_dword(dev, BSSIDR, ((u32 *)net->bssid)[0]); + write_nic_word(dev, BSSIDR+4, ((u16 *)net->bssid)[2]); + + if (priv->rtllib->iw_mode == IW_MODE_ADHOC) { + write_nic_word(dev, ATIMWND, 2); + write_nic_word(dev, BCN_DMATIME, 256); + write_nic_word(dev, BCN_INTERVAL, net->beacon_interval); + write_nic_word(dev, BCN_DRV_EARLY_INT, 10); + write_nic_byte(dev, BCN_ERR_THRESH, 100); + + BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT); + BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS; + + write_nic_word(dev, BCN_TCFG, BcnTimeCfg); + } +} + +void rtl8192_link_change(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + + if (!priv->up) + return; + + if (ieee->state == RTLLIB_LINKED) { + rtl8192_net_update(dev); + priv->ops->update_ratr_table(dev); + if ((KEY_TYPE_WEP40 == ieee->pairwise_key_type) || + (KEY_TYPE_WEP104 == ieee->pairwise_key_type)) + EnableHWSecurityConfig8192(dev); + } else { + write_nic_byte(dev, 0x173, 0); + } + rtl8192e_update_msr(dev); + + if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) { + u32 reg = 0; + reg = read_nic_dword(dev, RCR); + if (priv->rtllib->state == RTLLIB_LINKED) { + if (ieee->IntelPromiscuousModeInfo.bPromiscuousOn) + ; + else + priv->ReceiveConfig = reg |= RCR_CBSSID; + } else + priv->ReceiveConfig = reg &= ~RCR_CBSSID; + + write_nic_dword(dev, RCR, reg); + } +} + +void rtl8192_AllowAllDestAddr(struct net_device *dev, + bool bAllowAllDA, bool WriteIntoReg) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + if (bAllowAllDA) + priv->ReceiveConfig |= RCR_AAP; + else + priv->ReceiveConfig &= ~RCR_AAP; + + if (WriteIntoReg) + write_nic_dword(dev, RCR, priv->ReceiveConfig); +} + +static u8 MRateToHwRate8190Pci(u8 rate) +{ + u8 ret = DESC90_RATE1M; + + switch (rate) { + case MGN_1M: + ret = DESC90_RATE1M; + break; + case MGN_2M: + ret = DESC90_RATE2M; + break; + case MGN_5_5M: + ret = DESC90_RATE5_5M; + break; + case MGN_11M: + ret = DESC90_RATE11M; + break; + case MGN_6M: + ret = DESC90_RATE6M; + break; + case MGN_9M: + ret = DESC90_RATE9M; + break; + case MGN_12M: + ret = DESC90_RATE12M; + break; + case MGN_18M: + ret = DESC90_RATE18M; + break; + case MGN_24M: + ret = DESC90_RATE24M; + break; + case MGN_36M: + ret = DESC90_RATE36M; + break; + case MGN_48M: + ret = DESC90_RATE48M; + break; + case MGN_54M: + ret = DESC90_RATE54M; + break; + case MGN_MCS0: + ret = DESC90_RATEMCS0; + break; + case MGN_MCS1: + ret = DESC90_RATEMCS1; + break; + case MGN_MCS2: + ret = DESC90_RATEMCS2; + break; + case MGN_MCS3: + ret = DESC90_RATEMCS3; + break; + case MGN_MCS4: + ret = DESC90_RATEMCS4; + break; + case MGN_MCS5: + ret = DESC90_RATEMCS5; + break; + case MGN_MCS6: + ret = DESC90_RATEMCS6; + break; + case MGN_MCS7: + ret = DESC90_RATEMCS7; + break; + case MGN_MCS8: + ret = DESC90_RATEMCS8; + break; + case MGN_MCS9: + ret = DESC90_RATEMCS9; + break; + case MGN_MCS10: + ret = DESC90_RATEMCS10; + break; + case MGN_MCS11: + ret = DESC90_RATEMCS11; + break; + case MGN_MCS12: + ret = DESC90_RATEMCS12; + break; + case MGN_MCS13: + ret = DESC90_RATEMCS13; + break; + case MGN_MCS14: + ret = DESC90_RATEMCS14; + break; + case MGN_MCS15: + ret = DESC90_RATEMCS15; + break; + case (0x80|0x20): + ret = DESC90_RATEMCS32; + break; + default: + break; + } + return ret; +} + +static u8 rtl8192_MapHwQueueToFirmwareQueue(u8 QueueID, u8 priority) +{ + u8 QueueSelect = 0x0; + + switch (QueueID) { + case BE_QUEUE: + QueueSelect = QSLT_BE; + break; + + case BK_QUEUE: + QueueSelect = QSLT_BK; + break; + + case VO_QUEUE: + QueueSelect = QSLT_VO; + break; + + case VI_QUEUE: + QueueSelect = QSLT_VI; + break; + case MGNT_QUEUE: + QueueSelect = QSLT_MGNT; + break; + case BEACON_QUEUE: + QueueSelect = QSLT_BEACON; + break; + case TXCMD_QUEUE: + QueueSelect = QSLT_CMD; + break; + case HIGH_QUEUE: + QueueSelect = QSLT_HIGH; + break; + default: + RT_TRACE(COMP_ERR, "TransmitTCB(): Impossible Queue Selection:" + " %d\n", QueueID); + break; + } + return QueueSelect; +} + +void rtl8192_tx_fill_desc(struct net_device *dev, struct tx_desc *pdesc, + struct cb_desc *cb_desc, struct sk_buff *skb) +{ + struct r8192_priv *priv = rtllib_priv(dev); + dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len, + PCI_DMA_TODEVICE); + struct tx_fwinfo_8190pci *pTxFwInfo = NULL; + pTxFwInfo = (struct tx_fwinfo_8190pci *)skb->data; + memset(pTxFwInfo, 0, sizeof(struct tx_fwinfo_8190pci)); + pTxFwInfo->TxHT = (cb_desc->data_rate & 0x80) ? 1 : 0; + pTxFwInfo->TxRate = MRateToHwRate8190Pci((u8)cb_desc->data_rate); + pTxFwInfo->EnableCPUDur = cb_desc->bTxEnableFwCalcDur; + pTxFwInfo->Short = rtl8192_QueryIsShort(pTxFwInfo->TxHT, + pTxFwInfo->TxRate, + cb_desc); + + if (cb_desc->bAMPDUEnable) { + pTxFwInfo->AllowAggregation = 1; + pTxFwInfo->RxMF = cb_desc->ampdu_factor; + pTxFwInfo->RxAMD = cb_desc->ampdu_density; + } else { + pTxFwInfo->AllowAggregation = 0; + pTxFwInfo->RxMF = 0; + pTxFwInfo->RxAMD = 0; + } + + pTxFwInfo->RtsEnable = (cb_desc->bRTSEnable) ? 1 : 0; + pTxFwInfo->CtsEnable = (cb_desc->bCTSEnable) ? 1 : 0; + pTxFwInfo->RtsSTBC = (cb_desc->bRTSSTBC) ? 1 : 0; + pTxFwInfo->RtsHT = (cb_desc->rts_rate&0x80) ? 1 : 0; + pTxFwInfo->RtsRate = MRateToHwRate8190Pci((u8)cb_desc->rts_rate); + pTxFwInfo->RtsBandwidth = 0; + pTxFwInfo->RtsSubcarrier = cb_desc->RTSSC; + pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ? + (cb_desc->bRTSUseShortPreamble ? 1 : 0) : + (cb_desc->bRTSUseShortGI ? 1 : 0); + if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) { + if (cb_desc->bPacketBW) { + pTxFwInfo->TxBandwidth = 1; + pTxFwInfo->TxSubCarrier = 0; + } else { + pTxFwInfo->TxBandwidth = 0; + pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC; + } + } else { + pTxFwInfo->TxBandwidth = 0; + pTxFwInfo->TxSubCarrier = 0; + } + + memset((u8 *)pdesc, 0, 12); + pdesc->LINIP = 0; + pdesc->CmdInit = 1; + pdesc->Offset = sizeof(struct tx_fwinfo_8190pci) + 8; + pdesc->PktSize = (u16)skb->len-sizeof(struct tx_fwinfo_8190pci); + + pdesc->SecCAMID = 0; + pdesc->RATid = cb_desc->RATRIndex; + + + pdesc->NoEnc = 1; + pdesc->SecType = 0x0; + if (cb_desc->bHwSec) { + static u8 tmp; + if (!tmp) { + RT_TRACE(COMP_DBG, "==>================hw sec\n"); + tmp = 1; + } + switch (priv->rtllib->pairwise_key_type) { + case KEY_TYPE_WEP40: + case KEY_TYPE_WEP104: + pdesc->SecType = 0x1; + pdesc->NoEnc = 0; + break; + case KEY_TYPE_TKIP: + pdesc->SecType = 0x2; + pdesc->NoEnc = 0; + break; + case KEY_TYPE_CCMP: + pdesc->SecType = 0x3; + pdesc->NoEnc = 0; + break; + case KEY_TYPE_NA: + pdesc->SecType = 0x0; + pdesc->NoEnc = 1; + break; + } + } + + pdesc->PktId = 0x0; + + pdesc->QueueSelect = rtl8192_MapHwQueueToFirmwareQueue( + cb_desc->queue_index, + cb_desc->priority); + pdesc->TxFWInfoSize = sizeof(struct tx_fwinfo_8190pci); + + pdesc->DISFB = cb_desc->bTxDisableRateFallBack; + pdesc->USERATE = cb_desc->bTxUseDriverAssingedRate; + + pdesc->FirstSeg = 1; + pdesc->LastSeg = 1; + pdesc->TxBufferSize = skb->len; + + pdesc->TxBuffAddr = cpu_to_le32(mapping); +} + +void rtl8192_tx_fill_cmd_desc(struct net_device *dev, + struct tx_desc_cmd *entry, + struct cb_desc *cb_desc, struct sk_buff* skb) +{ + struct r8192_priv *priv = rtllib_priv(dev); + dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len, + PCI_DMA_TODEVICE); + + memset(entry, 0, 12); + entry->LINIP = cb_desc->bLastIniPkt; + entry->FirstSeg = 1; + entry->LastSeg = 1; + if (cb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) { + entry->CmdInit = DESC_PACKET_TYPE_INIT; + } else { + struct tx_desc * entry_tmp = (struct tx_desc *)entry; + entry_tmp->CmdInit = DESC_PACKET_TYPE_NORMAL; + entry_tmp->Offset = sizeof(struct tx_fwinfo_8190pci) + 8; + entry_tmp->PktSize = (u16)(cb_desc->pkt_size + + entry_tmp->Offset); + entry_tmp->QueueSelect = QSLT_CMD; + entry_tmp->TxFWInfoSize = 0x08; + entry_tmp->RATid = (u8)DESC_PACKET_TYPE_INIT; + } + entry->TxBufferSize = skb->len; + entry->TxBuffAddr = cpu_to_le32(mapping); + entry->OWN = 1; +} + +static u8 HwRateToMRate90(bool bIsHT, u8 rate) +{ + u8 ret_rate = 0x02; + + if (!bIsHT) { + switch (rate) { + case DESC90_RATE1M: + ret_rate = MGN_1M; + break; + case DESC90_RATE2M: + ret_rate = MGN_2M; + break; + case DESC90_RATE5_5M: + ret_rate = MGN_5_5M; + break; + case DESC90_RATE11M: + ret_rate = MGN_11M; + break; + case DESC90_RATE6M: + ret_rate = MGN_6M; + break; + case DESC90_RATE9M: + ret_rate = MGN_9M; + break; + case DESC90_RATE12M: + ret_rate = MGN_12M; + break; + case DESC90_RATE18M: + ret_rate = MGN_18M; + break; + case DESC90_RATE24M: + ret_rate = MGN_24M; + break; + case DESC90_RATE36M: + ret_rate = MGN_36M; + break; + case DESC90_RATE48M: + ret_rate = MGN_48M; + break; + case DESC90_RATE54M: + ret_rate = MGN_54M; + break; + + default: + RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported" + "Rate [%x], bIsHT = %d!!!\n", rate, bIsHT); + break; + } + + } else { + switch (rate) { + case DESC90_RATEMCS0: + ret_rate = MGN_MCS0; + break; + case DESC90_RATEMCS1: + ret_rate = MGN_MCS1; + break; + case DESC90_RATEMCS2: + ret_rate = MGN_MCS2; + break; + case DESC90_RATEMCS3: + ret_rate = MGN_MCS3; + break; + case DESC90_RATEMCS4: + ret_rate = MGN_MCS4; + break; + case DESC90_RATEMCS5: + ret_rate = MGN_MCS5; + break; + case DESC90_RATEMCS6: + ret_rate = MGN_MCS6; + break; + case DESC90_RATEMCS7: + ret_rate = MGN_MCS7; + break; + case DESC90_RATEMCS8: + ret_rate = MGN_MCS8; + break; + case DESC90_RATEMCS9: + ret_rate = MGN_MCS9; + break; + case DESC90_RATEMCS10: + ret_rate = MGN_MCS10; + break; + case DESC90_RATEMCS11: + ret_rate = MGN_MCS11; + break; + case DESC90_RATEMCS12: + ret_rate = MGN_MCS12; + break; + case DESC90_RATEMCS13: + ret_rate = MGN_MCS13; + break; + case DESC90_RATEMCS14: + ret_rate = MGN_MCS14; + break; + case DESC90_RATEMCS15: + ret_rate = MGN_MCS15; + break; + case DESC90_RATEMCS32: + ret_rate = (0x80|0x20); + break; + + default: + RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported " + "Rate [%x], bIsHT = %d!!!\n", rate, bIsHT); + break; + } + } + + return ret_rate; +} + +static long rtl8192_signal_scale_mapping(struct r8192_priv *priv, long currsig) +{ + long retsig; + + if (currsig >= 61 && currsig <= 100) + retsig = 90 + ((currsig - 60) / 4); + else if (currsig >= 41 && currsig <= 60) + retsig = 78 + ((currsig - 40) / 2); + else if (currsig >= 31 && currsig <= 40) + retsig = 66 + (currsig - 30); + else if (currsig >= 21 && currsig <= 30) + retsig = 54 + (currsig - 20); + else if (currsig >= 5 && currsig <= 20) + retsig = 42 + (((currsig - 5) * 2) / 3); + else if (currsig == 4) + retsig = 36; + else if (currsig == 3) + retsig = 27; + else if (currsig == 2) + retsig = 18; + else if (currsig == 1) + retsig = 9; + else + retsig = currsig; + + return retsig; +} + + +#define rx_hal_is_cck_rate(_pdrvinfo)\ + ((_pdrvinfo->RxRate == DESC90_RATE1M ||\ + _pdrvinfo->RxRate == DESC90_RATE2M ||\ + _pdrvinfo->RxRate == DESC90_RATE5_5M ||\ + _pdrvinfo->RxRate == DESC90_RATE11M) &&\ + !_pdrvinfo->RxHT) + +static void rtl8192_query_rxphystatus( + struct r8192_priv *priv, + struct rtllib_rx_stats *pstats, + struct rx_desc *pdesc, + struct rx_fwinfo *pdrvinfo, + struct rtllib_rx_stats *precord_stats, + bool bpacket_match_bssid, + bool bpacket_toself, + bool bPacketBeacon, + bool bToSelfBA + ) +{ + struct phy_sts_ofdm_819xpci *pofdm_buf; + struct phy_sts_cck_819xpci *pcck_buf; + struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *prxsc; + u8 *prxpkt; + u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg; + char rx_pwr[4], rx_pwr_all = 0; + char rx_snrX, rx_evmX; + u8 evm, pwdb_all; + u32 RSSI, total_rssi = 0; + u8 is_cck_rate = 0; + u8 rf_rx_num = 0; + static u8 check_reg824; + static u32 reg824_bit9; + + priv->stats.numqry_phystatus++; + + is_cck_rate = rx_hal_is_cck_rate(pdrvinfo); + memset(precord_stats, 0, sizeof(struct rtllib_rx_stats)); + pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID = + bpacket_match_bssid; + pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself; + pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate; + pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon; + pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA; + if (check_reg824 == 0) { + reg824_bit9 = rtl8192_QueryBBReg(priv->rtllib->dev, + rFPGA0_XA_HSSIParameter2, 0x200); + check_reg824 = 1; + } + + + prxpkt = (u8 *)pdrvinfo; + + prxpkt += sizeof(struct rx_fwinfo); + + pcck_buf = (struct phy_sts_cck_819xpci *)prxpkt; + pofdm_buf = (struct phy_sts_ofdm_819xpci *)prxpkt; + + pstats->RxMIMOSignalQuality[0] = -1; + pstats->RxMIMOSignalQuality[1] = -1; + precord_stats->RxMIMOSignalQuality[0] = -1; + precord_stats->RxMIMOSignalQuality[1] = -1; + + if (is_cck_rate) { + u8 report; + + priv->stats.numqry_phystatusCCK++; + if (!reg824_bit9) { + report = pcck_buf->cck_agc_rpt & 0xc0; + report = report>>6; + switch (report) { + case 0x3: + rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt & + 0x3e); + break; + case 0x2: + rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt & + 0x3e); + break; + case 0x1: + rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt & + 0x3e); + break; + case 0x0: + rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e); + break; + } + } else { + report = pcck_buf->cck_agc_rpt & 0x60; + report = report>>5; + switch (report) { + case 0x3: + rx_pwr_all = -35 - + ((pcck_buf->cck_agc_rpt & + 0x1f) << 1); + break; + case 0x2: + rx_pwr_all = -23 - + ((pcck_buf->cck_agc_rpt & + 0x1f) << 1); + break; + case 0x1: + rx_pwr_all = -11 - + ((pcck_buf->cck_agc_rpt & + 0x1f) << 1); + break; + case 0x0: + rx_pwr_all = -8 - + ((pcck_buf->cck_agc_rpt & + 0x1f) << 1); + break; + } + } + + pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all); + pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all; + pstats->RecvSignalPower = rx_pwr_all; + + if (bpacket_match_bssid) { + u8 sq; + + if (pstats->RxPWDBAll > 40) { + sq = 100; + } else { + sq = pcck_buf->sq_rpt; + + if (pcck_buf->sq_rpt > 64) + sq = 0; + else if (pcck_buf->sq_rpt < 20) + sq = 100; + else + sq = ((64-sq) * 100) / 44; + } + pstats->SignalQuality = sq; + precord_stats->SignalQuality = sq; + pstats->RxMIMOSignalQuality[0] = sq; + precord_stats->RxMIMOSignalQuality[0] = sq; + pstats->RxMIMOSignalQuality[1] = -1; + precord_stats->RxMIMOSignalQuality[1] = -1; + } + } else { + priv->stats.numqry_phystatusHT++; + for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) { + if (priv->brfpath_rxenable[i]) + rf_rx_num++; + + rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i] & 0x3F) * + 2) - 110; + + tmp_rxsnr = pofdm_buf->rxsnr_X[i]; + rx_snrX = (char)(tmp_rxsnr); + rx_snrX /= 2; + priv->stats.rxSNRdB[i] = (long)rx_snrX; + + RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]); + if (priv->brfpath_rxenable[i]) + total_rssi += RSSI; + + if (bpacket_match_bssid) { + pstats->RxMIMOSignalStrength[i] = (u8) RSSI; + precord_stats->RxMIMOSignalStrength[i] = + (u8) RSSI; + } + } + + + rx_pwr_all = (((pofdm_buf->pwdb_all) >> 1) & 0x7f) - 106; + pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all); + + pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all; + pstats->RxPower = precord_stats->RxPower = rx_pwr_all; + pstats->RecvSignalPower = rx_pwr_all; + if (pdrvinfo->RxHT && pdrvinfo->RxRate >= DESC90_RATEMCS8 && + pdrvinfo->RxRate <= DESC90_RATEMCS15) + max_spatial_stream = 2; + else + max_spatial_stream = 1; + + for (i = 0; i < max_spatial_stream; i++) { + tmp_rxevm = pofdm_buf->rxevm_X[i]; + rx_evmX = (char)(tmp_rxevm); + + rx_evmX /= 2; + + evm = rtl819x_evm_dbtopercentage(rx_evmX); + if (bpacket_match_bssid) { + if (i == 0) { + pstats->SignalQuality = (u8)(evm & + 0xff); + precord_stats->SignalQuality = (u8)(evm + & 0xff); + } + pstats->RxMIMOSignalQuality[i] = (u8)(evm & + 0xff); + precord_stats->RxMIMOSignalQuality[i] = (u8)(evm + & 0xff); + } + } + + + rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg; + prxsc = (struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *) + &rxsc_sgien_exflg; + if (pdrvinfo->BW) + priv->stats.received_bwtype[1+prxsc->rxsc]++; + else + priv->stats.received_bwtype[0]++; + } + + if (is_cck_rate) { + pstats->SignalStrength = precord_stats->SignalStrength = + (u8)(rtl8192_signal_scale_mapping(priv, + (long)pwdb_all)); + + } else { + if (rf_rx_num != 0) + pstats->SignalStrength = precord_stats->SignalStrength = + (u8)(rtl8192_signal_scale_mapping(priv, + (long)(total_rssi /= rf_rx_num))); + } +} + +static void rtl8192_process_phyinfo(struct r8192_priv *priv, u8 *buffer, + struct rtllib_rx_stats *prev_st, + struct rtllib_rx_stats *curr_st) +{ + bool bcheck = false; + u8 rfpath; + u32 ij, tmp_val; + static u32 slide_rssi_index, slide_rssi_statistics; + static u32 slide_evm_index, slide_evm_statistics; + static u32 last_rssi, last_evm; + static u32 slide_beacon_adc_pwdb_index; + static u32 slide_beacon_adc_pwdb_statistics; + static u32 last_beacon_adc_pwdb; + struct rtllib_hdr_3addr *hdr; + u16 sc; + unsigned int frag, seq; + + hdr = (struct rtllib_hdr_3addr *)buffer; + sc = le16_to_cpu(hdr->seq_ctl); + frag = WLAN_GET_SEQ_FRAG(sc); + seq = WLAN_GET_SEQ_SEQ(sc); + curr_st->Seq_Num = seq; + if (!prev_st->bIsAMPDU) + bcheck = true; + + if (slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) { + slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX; + last_rssi = priv->stats.slide_signal_strength[slide_rssi_index]; + priv->stats.slide_rssi_total -= last_rssi; + } + priv->stats.slide_rssi_total += prev_st->SignalStrength; + + priv->stats.slide_signal_strength[slide_rssi_index++] = + prev_st->SignalStrength; + if (slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX) + slide_rssi_index = 0; + + tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics; + priv->stats.signal_strength = rtl819x_translate_todbm(priv, + (u8)tmp_val); + curr_st->rssi = priv->stats.signal_strength; + if (!prev_st->bPacketMatchBSSID) { + if (!prev_st->bToSelfBA) + return; + } + + if (!bcheck) + return; + + rtl819x_process_cck_rxpathsel(priv, prev_st); + + priv->stats.num_process_phyinfo++; + if (!prev_st->bIsCCK && prev_st->bPacketToSelf) { + for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) { + if (!rtl8192_phy_CheckIsLegalRFPath(priv->rtllib->dev, + rfpath)) + continue; + RT_TRACE(COMP_DBG, "Jacken -> pPreviousstats->RxMIMO" + "SignalStrength[rfpath] = %d\n", + prev_st->RxMIMOSignalStrength[rfpath]); + if (priv->stats.rx_rssi_percentage[rfpath] == 0) { + priv->stats.rx_rssi_percentage[rfpath] = + prev_st->RxMIMOSignalStrength[rfpath]; + } + if (prev_st->RxMIMOSignalStrength[rfpath] > + priv->stats.rx_rssi_percentage[rfpath]) { + priv->stats.rx_rssi_percentage[rfpath] = + ((priv->stats.rx_rssi_percentage[rfpath] + * (RX_SMOOTH - 1)) + + (prev_st->RxMIMOSignalStrength + [rfpath])) / (RX_SMOOTH); + priv->stats.rx_rssi_percentage[rfpath] = + priv->stats.rx_rssi_percentage[rfpath] + + 1; + } else { + priv->stats.rx_rssi_percentage[rfpath] = + ((priv->stats.rx_rssi_percentage[rfpath] * + (RX_SMOOTH-1)) + + (prev_st->RxMIMOSignalStrength[rfpath])) / + (RX_SMOOTH); + } + RT_TRACE(COMP_DBG, "Jacken -> priv->RxStats.RxRSSI" + "Percentage[rfPath] = %d\n", + priv->stats.rx_rssi_percentage[rfpath]); + } + } + + + if (prev_st->bPacketBeacon) { + if (slide_beacon_adc_pwdb_statistics++ >= + PHY_Beacon_RSSI_SLID_WIN_MAX) { + slide_beacon_adc_pwdb_statistics = + PHY_Beacon_RSSI_SLID_WIN_MAX; + last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb + [slide_beacon_adc_pwdb_index]; + priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb; + } + priv->stats.Slide_Beacon_Total += prev_st->RxPWDBAll; + priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] = + prev_st->RxPWDBAll; + slide_beacon_adc_pwdb_index++; + if (slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX) + slide_beacon_adc_pwdb_index = 0; + prev_st->RxPWDBAll = priv->stats.Slide_Beacon_Total / + slide_beacon_adc_pwdb_statistics; + if (prev_st->RxPWDBAll >= 3) + prev_st->RxPWDBAll -= 3; + } + + RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n", + prev_st->bIsCCK ? "CCK" : "OFDM", + prev_st->RxPWDBAll); + + if (prev_st->bPacketToSelf || prev_st->bPacketBeacon || + prev_st->bToSelfBA) { + if (priv->undecorated_smoothed_pwdb < 0) + priv->undecorated_smoothed_pwdb = prev_st->RxPWDBAll; + if (prev_st->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) { + priv->undecorated_smoothed_pwdb = + (((priv->undecorated_smoothed_pwdb) * + (RX_SMOOTH-1)) + + (prev_st->RxPWDBAll)) / (RX_SMOOTH); + priv->undecorated_smoothed_pwdb = + priv->undecorated_smoothed_pwdb + 1; + } else { + priv->undecorated_smoothed_pwdb = + (((priv->undecorated_smoothed_pwdb) * + (RX_SMOOTH-1)) + + (prev_st->RxPWDBAll)) / (RX_SMOOTH); + } + rtl819x_update_rxsignalstatistics8190pci(priv, prev_st); + } + + if (prev_st->SignalQuality != 0) { + if (prev_st->bPacketToSelf || prev_st->bPacketBeacon || + prev_st->bToSelfBA) { + if (slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX) { + slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX; + last_evm = + priv->stats.slide_evm[slide_evm_index]; + priv->stats.slide_evm_total -= last_evm; + } + + priv->stats.slide_evm_total += prev_st->SignalQuality; + + priv->stats.slide_evm[slide_evm_index++] = + prev_st->SignalQuality; + if (slide_evm_index >= PHY_RSSI_SLID_WIN_MAX) + slide_evm_index = 0; + + tmp_val = priv->stats.slide_evm_total / + slide_evm_statistics; + priv->stats.signal_quality = tmp_val; + priv->stats.last_signal_strength_inpercent = tmp_val; + } + + if (prev_st->bPacketToSelf || + prev_st->bPacketBeacon || + prev_st->bToSelfBA) { + for (ij = 0; ij < 2; ij++) { + if (prev_st->RxMIMOSignalQuality[ij] != -1) { + if (priv->stats.rx_evm_percentage[ij] == 0) + priv->stats.rx_evm_percentage[ij] = + prev_st->RxMIMOSignalQuality[ij]; + priv->stats.rx_evm_percentage[ij] = + ((priv->stats.rx_evm_percentage[ij] * + (RX_SMOOTH - 1)) + + (prev_st->RxMIMOSignalQuality[ij])) / + (RX_SMOOTH); + } + } + } + } +} + +static void rtl8192_TranslateRxSignalStuff(struct net_device *dev, + struct sk_buff *skb, + struct rtllib_rx_stats *pstats, + struct rx_desc *pdesc, + struct rx_fwinfo *pdrvinfo) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + bool bpacket_match_bssid, bpacket_toself; + bool bPacketBeacon = false; + struct rtllib_hdr_3addr *hdr; + bool bToSelfBA = false; + static struct rtllib_rx_stats previous_stats; + u16 fc, type; + u8 *tmp_buf; + u8 *praddr; + + tmp_buf = skb->data + pstats->RxDrvInfoSize + pstats->RxBufShift; + + hdr = (struct rtllib_hdr_3addr *)tmp_buf; + fc = le16_to_cpu(hdr->frame_ctl); + type = WLAN_FC_GET_TYPE(fc); + praddr = hdr->addr1; + + bpacket_match_bssid = ((RTLLIB_FTYPE_CTL != type) && + (!compare_ether_addr(priv->rtllib-> + current_network.bssid, + (fc & RTLLIB_FCTL_TODS) ? hdr->addr1 : + (fc & RTLLIB_FCTL_FROMDS) ? hdr->addr2 : hdr->addr3)) + && (!pstats->bHwError) && (!pstats->bCRC) && (!pstats->bICV)); + bpacket_toself = bpacket_match_bssid && /* check this */ + (!compare_ether_addr(praddr, + priv->rtllib->dev->dev_addr)); + if (WLAN_FC_GET_FRAMETYPE(fc) == RTLLIB_STYPE_BEACON) + bPacketBeacon = true; + if (bpacket_match_bssid) + priv->stats.numpacket_matchbssid++; + if (bpacket_toself) + priv->stats.numpacket_toself++; + rtl8192_process_phyinfo(priv, tmp_buf, &previous_stats, pstats); + rtl8192_query_rxphystatus(priv, pstats, pdesc, pdrvinfo, + &previous_stats, bpacket_match_bssid, + bpacket_toself, bPacketBeacon, bToSelfBA); + rtl8192_record_rxdesc_forlateruse(pstats, &previous_stats); +} + +static void rtl8192_UpdateReceivedRateHistogramStatistics( + struct net_device *dev, + struct rtllib_rx_stats *pstats) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + u32 rcvType = 1; + u32 rateIndex; + u32 preamble_guardinterval; + + if (pstats->bCRC) + rcvType = 2; + else if (pstats->bICV) + rcvType = 3; + + if (pstats->bShortPreamble) + preamble_guardinterval = 1; + else + preamble_guardinterval = 0; + + switch (pstats->rate) { + case MGN_1M: + rateIndex = 0; + break; + case MGN_2M: + rateIndex = 1; + break; + case MGN_5_5M: + rateIndex = 2; + break; + case MGN_11M: + rateIndex = 3; + break; + case MGN_6M: + rateIndex = 4; + break; + case MGN_9M: + rateIndex = 5; + break; + case MGN_12M: + rateIndex = 6; + break; + case MGN_18M: + rateIndex = 7; + break; + case MGN_24M: + rateIndex = 8; + break; + case MGN_36M: + rateIndex = 9; + break; + case MGN_48M: + rateIndex = 10; + break; + case MGN_54M: + rateIndex = 11; + break; + case MGN_MCS0: + rateIndex = 12; + break; + case MGN_MCS1: + rateIndex = 13; + break; + case MGN_MCS2: + rateIndex = 14; + break; + case MGN_MCS3: + rateIndex = 15; + break; + case MGN_MCS4: + rateIndex = 16; + break; + case MGN_MCS5: + rateIndex = 17; + break; + case MGN_MCS6: + rateIndex = 18; + break; + case MGN_MCS7: + rateIndex = 19; + break; + case MGN_MCS8: + rateIndex = 20; + break; + case MGN_MCS9: + rateIndex = 21; + break; + case MGN_MCS10: + rateIndex = 22; + break; + case MGN_MCS11: + rateIndex = 23; + break; + case MGN_MCS12: + rateIndex = 24; + break; + case MGN_MCS13: + rateIndex = 25; + break; + case MGN_MCS14: + rateIndex = 26; + break; + case MGN_MCS15: + rateIndex = 27; + break; + default: + rateIndex = 28; + break; + } + priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++; + priv->stats.received_rate_histogram[0][rateIndex]++; + priv->stats.received_rate_histogram[rcvType][rateIndex]++; +} + +bool rtl8192_rx_query_status_desc(struct net_device *dev, + struct rtllib_rx_stats *stats, + struct rx_desc *pdesc, + struct sk_buff *skb) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + stats->bICV = pdesc->ICV; + stats->bCRC = pdesc->CRC32; + stats->bHwError = pdesc->CRC32 | pdesc->ICV; + + stats->Length = pdesc->Length; + if (stats->Length < 24) + stats->bHwError |= 1; + + if (stats->bHwError) { + stats->bShift = false; + + if (pdesc->CRC32) { + if (pdesc->Length < 500) + priv->stats.rxcrcerrmin++; + else if (pdesc->Length > 1000) + priv->stats.rxcrcerrmax++; + else + priv->stats.rxcrcerrmid++; + } + return false; + } else { + struct rx_fwinfo *pDrvInfo = NULL; + stats->RxDrvInfoSize = pdesc->RxDrvInfoSize; + stats->RxBufShift = ((pdesc->Shift)&0x03); + stats->Decrypted = !pdesc->SWDec; + + pDrvInfo = (struct rx_fwinfo *)(skb->data + stats->RxBufShift); + + stats->rate = HwRateToMRate90((bool)pDrvInfo->RxHT, + (u8)pDrvInfo->RxRate); + stats->bShortPreamble = pDrvInfo->SPLCP; + + rtl8192_UpdateReceivedRateHistogramStatistics(dev, stats); + + stats->bIsAMPDU = (pDrvInfo->PartAggr == 1); + stats->bFirstMPDU = (pDrvInfo->PartAggr == 1) && + (pDrvInfo->FirstAGGR == 1); + + stats->TimeStampLow = pDrvInfo->TSFL; + stats->TimeStampHigh = read_nic_dword(dev, TSFR+4); + + rtl819x_UpdateRxPktTimeStamp(dev, stats); + + if ((stats->RxBufShift + stats->RxDrvInfoSize) > 0) + stats->bShift = 1; + + stats->RxIs40MHzPacket = pDrvInfo->BW; + + rtl8192_TranslateRxSignalStuff(dev, skb, stats, pdesc, + pDrvInfo); + + if (pDrvInfo->FirstAGGR == 1 || pDrvInfo->PartAggr == 1) + RT_TRACE(COMP_RXDESC, "pDrvInfo->FirstAGGR = %d," + " pDrvInfo->PartAggr = %d\n", + pDrvInfo->FirstAGGR, pDrvInfo->PartAggr); + skb_trim(skb, skb->len - 4/*sCrcLng*/); + + + stats->packetlength = stats->Length-4; + stats->fraglength = stats->packetlength; + stats->fragoffset = 0; + stats->ntotalfrag = 1; + return true; + } +} + +void rtl8192_halt_adapter(struct net_device *dev, bool reset) +{ + struct r8192_priv *priv = rtllib_priv(dev); + int i; + u8 OpMode; + u8 u1bTmp; + u32 ulRegRead; + + OpMode = RT_OP_MODE_NO_LINK; + priv->rtllib->SetHwRegHandler(dev, HW_VAR_MEDIA_STATUS, &OpMode); + + if (!priv->rtllib->bSupportRemoteWakeUp) { + u1bTmp = 0x0; + write_nic_byte(dev, CMDR, u1bTmp); + } + + mdelay(20); + + if (!reset) { + mdelay(150); + + priv->bHwRfOffAction = 2; + + if (!priv->rtllib->bSupportRemoteWakeUp) { + PHY_SetRtl8192eRfOff(dev); + ulRegRead = read_nic_dword(dev, CPU_GEN); + ulRegRead |= CPU_GEN_SYSTEM_RESET; + write_nic_dword(dev, CPU_GEN, ulRegRead); + } else { + write_nic_dword(dev, WFCRC0, 0xffffffff); + write_nic_dword(dev, WFCRC1, 0xffffffff); + write_nic_dword(dev, WFCRC2, 0xffffffff); + + + write_nic_byte(dev, PMR, 0x5); + write_nic_byte(dev, MacBlkCtrl, 0xa); + } + } + + for (i = 0; i < MAX_QUEUE_SIZE; i++) + skb_queue_purge(&priv->rtllib->skb_waitQ[i]); + for (i = 0; i < MAX_QUEUE_SIZE; i++) + skb_queue_purge(&priv->rtllib->skb_aggQ[i]); + + skb_queue_purge(&priv->skb_queue); + return; +} + +void rtl8192_update_ratr_table(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + u8 *pMcsRate = ieee->dot11HTOperationalRateSet; + u32 ratr_value = 0; + u8 rate_index = 0; + + rtl8192_config_rate(dev, (u16 *)(&ratr_value)); + ratr_value |= (*(u16 *)(pMcsRate)) << 12; + switch (ieee->mode) { + case IEEE_A: + ratr_value &= 0x00000FF0; + break; + case IEEE_B: + ratr_value &= 0x0000000F; + break; + case IEEE_G: + case IEEE_G|IEEE_B: + ratr_value &= 0x00000FF7; + break; + case IEEE_N_24G: + case IEEE_N_5G: + if (ieee->pHTInfo->PeerMimoPs == 0) { + ratr_value &= 0x0007F007; + } else { + if (priv->rf_type == RF_1T2R) + ratr_value &= 0x000FF007; + else + ratr_value &= 0x0F81F007; + } + break; + default: + break; + } + ratr_value &= 0x0FFFFFFF; + if (ieee->pHTInfo->bCurTxBW40MHz && + ieee->pHTInfo->bCurShortGI40MHz) + ratr_value |= 0x80000000; + else if (!ieee->pHTInfo->bCurTxBW40MHz && + ieee->pHTInfo->bCurShortGI20MHz) + ratr_value |= 0x80000000; + write_nic_dword(dev, RATR0+rate_index*4, ratr_value); + write_nic_byte(dev, UFWP, 1); +} + +void +rtl8192_InitializeVariables(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + strcpy(priv->nick, "rtl8192E"); + + priv->rtllib->softmac_features = IEEE_SOFTMAC_SCAN | + IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ | + IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE /* | + IEEE_SOFTMAC_BEACONS*/; + + priv->rtllib->tx_headroom = sizeof(struct tx_fwinfo_8190pci); + + priv->ShortRetryLimit = 0x30; + priv->LongRetryLimit = 0x30; + + priv->EarlyRxThreshold = 7; + priv->pwrGroupCnt = 0; + + priv->bIgnoreSilentReset = false; + priv->enable_gpio0 = 0; + + priv->TransmitConfig = 0; + + priv->ReceiveConfig = RCR_ADD3 | + RCR_AMF | RCR_ADF | + RCR_AICV | + RCR_AB | RCR_AM | RCR_APM | + RCR_AAP | ((u32)7<<RCR_MXDMA_OFFSET) | + ((u32)7 << RCR_FIFO_OFFSET) | RCR_ONLYERLPKT; + + priv->irq_mask[0] = (u32)(IMR_ROK | IMR_VODOK | IMR_VIDOK | + IMR_BEDOK | IMR_BKDOK | IMR_HCCADOK | + IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK | + IMR_BDOK | IMR_RXCMDOK | IMR_TIMEOUT0 | + IMR_RDU | IMR_RXFOVW | IMR_TXFOVW | + IMR_BcnInt | IMR_TBDOK | IMR_TBDER); + + + priv->MidHighPwrTHR_L1 = 0x3B; + priv->MidHighPwrTHR_L2 = 0x40; + priv->PwrDomainProtect = false; + + priv->bfirst_after_down = 0; +} + +void rtl8192_EnableInterrupt(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + priv->irq_enabled = 1; + + write_nic_dword(dev, INTA_MASK, priv->irq_mask[0]); + +} + +void rtl8192_DisableInterrupt(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + + write_nic_dword(dev, INTA_MASK, 0); + + priv->irq_enabled = 0; +} + +void rtl8192_ClearInterrupt(struct net_device *dev) +{ + u32 tmp = 0; + tmp = read_nic_dword(dev, ISR); + write_nic_dword(dev, ISR, tmp); +} + + +void rtl8192_enable_rx(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + write_nic_dword(dev, RDQDA, priv->rx_ring_dma[RX_MPDU_QUEUE]); +} + +static const u32 TX_DESC_BASE[] = { + BKQDA, BEQDA, VIQDA, VOQDA, HCCAQDA, CQDA, MQDA, HQDA, BQDA +}; + +void rtl8192_enable_tx(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + u32 i; + + for (i = 0; i < MAX_TX_QUEUE_COUNT; i++) + write_nic_dword(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma); +} + + +void rtl8192_interrupt_recognized(struct net_device *dev, u32 *p_inta, + u32 *p_intb) +{ + *p_inta = read_nic_dword(dev, ISR); + write_nic_dword(dev, ISR, *p_inta); +} + +bool rtl8192_HalRxCheckStuck(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u16 RegRxCounter = read_nic_word(dev, 0x130); + bool bStuck = false; + static u8 rx_chk_cnt; + u32 SlotIndex = 0, TotalRxStuckCount = 0; + u8 i; + u8 SilentResetRxSoltNum = 4; + + RT_TRACE(COMP_RESET, "%s(): RegRxCounter is %d, RxCounter is %d\n", + __func__, RegRxCounter, priv->RxCounter); + + rx_chk_cnt++; + if (priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5)) { + rx_chk_cnt = 0; + } else if ((priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High + 5)) + && (((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) && + (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_40M)) + || ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) && + (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_20M)))) { + if (rx_chk_cnt < 2) + return bStuck; + else + rx_chk_cnt = 0; + } else if ((((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) && + (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_40M)) || + ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) && + (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_20M))) && + priv->undecorated_smoothed_pwdb >= VeryLowRSSI) { + if (rx_chk_cnt < 4) + return bStuck; + else + rx_chk_cnt = 0; + } else { + if (rx_chk_cnt < 8) + return bStuck; + else + rx_chk_cnt = 0; + } + + + SlotIndex = (priv->SilentResetRxSlotIndex++)%SilentResetRxSoltNum; + + if (priv->RxCounter == RegRxCounter) { + priv->SilentResetRxStuckEvent[SlotIndex] = 1; + + for (i = 0; i < SilentResetRxSoltNum; i++) + TotalRxStuckCount += priv->SilentResetRxStuckEvent[i]; + + if (TotalRxStuckCount == SilentResetRxSoltNum) { + bStuck = true; + for (i = 0; i < SilentResetRxSoltNum; i++) + TotalRxStuckCount += + priv->SilentResetRxStuckEvent[i]; + } + + + } else { + priv->SilentResetRxStuckEvent[SlotIndex] = 0; + } + + priv->RxCounter = RegRxCounter; + + return bStuck; +} + +bool rtl8192_HalTxCheckStuck(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + bool bStuck = false; + u16 RegTxCounter = read_nic_word(dev, 0x128); + + RT_TRACE(COMP_RESET, "%s():RegTxCounter is %d,TxCounter is %d\n", + __func__, RegTxCounter, priv->TxCounter); + + if (priv->TxCounter == RegTxCounter) + bStuck = true; + + priv->TxCounter = RegTxCounter; + + return bStuck; +} + +bool rtl8192_GetNmodeSupportBySecCfg(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + if (ieee->rtllib_ap_sec_type && + (ieee->rtllib_ap_sec_type(priv->rtllib)&(SEC_ALG_WEP | + SEC_ALG_TKIP))) { + return false; + } else { + return true; + } +} + +bool rtl8192_GetHalfNmodeSupportByAPs(struct net_device *dev) +{ + bool Reval; + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + + if (ieee->bHalfWirelessN24GMode == true) + Reval = true; + else + Reval = false; + + return Reval; +} + +u8 rtl8192_QueryIsShort(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc) +{ + u8 tmp_Short; + + tmp_Short = (TxHT == 1) ? ((tcb_desc->bUseShortGI) ? 1 : 0) : + ((tcb_desc->bUseShortPreamble) ? 1 : 0); + if (TxHT == 1 && TxRate != DESC90_RATEMCS15) + tmp_Short = 0; + + return tmp_Short; +} + +void ActUpdateChannelAccessSetting(struct net_device *dev, + enum wireless_mode WirelessMode, + struct channel_access_setting *ChnlAccessSetting) +{ + return; +} diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_dev.h b/drivers/staging/rtl8192e/rtl8192e/r8192E_dev.h new file mode 100644 index 000000000000..b9b3b52f9120 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_dev.h @@ -0,0 +1,62 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * Based on the r8180 driver, which is: + * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ +#ifndef _RTL8192E_H +#define _RTL8192E_H + +#include "r8190P_def.h" + +u8 rtl8192_QueryIsShort(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc); +bool rtl8192_GetHalfNmodeSupportByAPs(struct net_device *dev); +bool rtl8192_GetNmodeSupportBySecCfg(struct net_device *dev); +bool rtl8192_HalTxCheckStuck(struct net_device *dev); +bool rtl8192_HalRxCheckStuck(struct net_device *dev); +void rtl8192_interrupt_recognized(struct net_device *dev, u32 *p_inta, + u32 *p_intb); +void rtl8192_enable_rx(struct net_device *dev); +void rtl8192_enable_tx(struct net_device *dev); +void rtl8192_EnableInterrupt(struct net_device *dev); +void rtl8192_DisableInterrupt(struct net_device *dev); +void rtl8192_ClearInterrupt(struct net_device *dev); +void rtl8192_InitializeVariables(struct net_device *dev); +void rtl8192e_start_beacon(struct net_device *dev); +void rtl8192e_SetHwReg(struct net_device *dev, u8 variable, u8 *val); +void rtl8192_get_eeprom_size(struct net_device *dev); +bool rtl8192_adapter_start(struct net_device *dev); +void rtl8192_link_change(struct net_device *dev); +void rtl8192_AllowAllDestAddr(struct net_device *dev, bool bAllowAllDA, + bool WriteIntoReg); +void rtl8192_tx_fill_desc(struct net_device *dev, struct tx_desc *pdesc, + struct cb_desc *cb_desc, + struct sk_buff *skb); +void rtl8192_tx_fill_cmd_desc(struct net_device *dev, + struct tx_desc_cmd *entry, + struct cb_desc *cb_desc, struct sk_buff *skb); +bool rtl8192_rx_query_status_desc(struct net_device *dev, + struct rtllib_rx_stats *stats, + struct rx_desc *pdesc, + struct sk_buff *skb); +void rtl8192_halt_adapter(struct net_device *dev, bool reset); +void rtl8192_update_ratr_table(struct net_device *dev); +#endif diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_firmware.c b/drivers/staging/rtl8192e/rtl8192e/r8192E_firmware.c new file mode 100644 index 000000000000..37719859bdae --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_firmware.c @@ -0,0 +1,348 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ + +#include "rtl_core.h" +#include "r8192E_hw.h" +#include "r8192E_hwimg.h" +#include "r8192E_firmware.h" +#include <linux/firmware.h> + +void firmware_init_param(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rt_firmware *pfirmware = priv->pFirmware; + + pfirmware->cmdpacket_frag_thresold = GET_COMMAND_PACKET_FRAG_THRESHOLD( + MAX_TRANSMIT_BUFFER_SIZE); +} + +static bool fw_download_code(struct net_device *dev, u8 *code_virtual_address, + u32 buffer_len) +{ + struct r8192_priv *priv = rtllib_priv(dev); + bool rt_status = true; + u16 frag_threshold; + u16 frag_length, frag_offset = 0; + int i; + + struct rt_firmware *pfirmware = priv->pFirmware; + struct sk_buff *skb; + unsigned char *seg_ptr; + struct cb_desc *tcb_desc; + u8 bLastIniPkt; + + firmware_init_param(dev); + frag_threshold = pfirmware->cmdpacket_frag_thresold; + do { + if ((buffer_len - frag_offset) > frag_threshold) { + frag_length = frag_threshold ; + bLastIniPkt = 0; + + } else { + frag_length = buffer_len - frag_offset; + bLastIniPkt = 1; + + } + + skb = dev_alloc_skb(frag_length + 4); + memcpy((unsigned char *)(skb->cb), &dev, sizeof(dev)); + tcb_desc = (struct cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); + tcb_desc->queue_index = TXCMD_QUEUE; + tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_INIT; + tcb_desc->bLastIniPkt = bLastIniPkt; + + seg_ptr = skb->data; + for (i = 0; i < frag_length; i += 4) { + *seg_ptr++ = ((i+0) < frag_length) ? + code_virtual_address[i+3] : 0; + *seg_ptr++ = ((i+1) < frag_length) ? + code_virtual_address[i+2] : 0; + *seg_ptr++ = ((i+2) < frag_length) ? + code_virtual_address[i+1] : 0; + *seg_ptr++ = ((i+3) < frag_length) ? + code_virtual_address[i+0] : 0; + } + tcb_desc->txbuf_size = (u16)i; + skb_put(skb, i); + + if (!priv->rtllib->check_nic_enough_desc(dev, tcb_desc->queue_index) || + (!skb_queue_empty(&priv->rtllib->skb_waitQ[tcb_desc->queue_index])) || + (priv->rtllib->queue_stop)) { + RT_TRACE(COMP_FIRMWARE, "===================> tx " + "full!\n"); + skb_queue_tail(&priv->rtllib->skb_waitQ + [tcb_desc->queue_index], skb); + } else { + priv->rtllib->softmac_hard_start_xmit(skb, dev); + } + + code_virtual_address += frag_length; + frag_offset += frag_length; + + } while (frag_offset < buffer_len); + + write_nic_byte(dev, TPPoll, TPPoll_CQ); + + return rt_status; +} + +static bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev) +{ + bool rt_status = true; + u32 CPU_status = 0; + unsigned long timeout; + + timeout = jiffies + MSECS(200); + while (time_before(jiffies, timeout)) { + CPU_status = read_nic_dword(dev, CPU_GEN); + if (CPU_status & CPU_GEN_PUT_CODE_OK) + break; + mdelay(2); + } + + if (!(CPU_status&CPU_GEN_PUT_CODE_OK)) { + RT_TRACE(COMP_ERR, "Download Firmware: Put code fail!\n"); + goto CPUCheckMainCodeOKAndTurnOnCPU_Fail; + } else { + RT_TRACE(COMP_FIRMWARE, "Download Firmware: Put code ok!\n"); + } + + CPU_status = read_nic_dword(dev, CPU_GEN); + write_nic_byte(dev, CPU_GEN, + (u8)((CPU_status|CPU_GEN_PWR_STB_CPU)&0xff)); + mdelay(1); + + timeout = jiffies + MSECS(200); + while (time_before(jiffies, timeout)) { + CPU_status = read_nic_dword(dev, CPU_GEN); + if (CPU_status&CPU_GEN_BOOT_RDY) + break; + mdelay(2); + } + + if (!(CPU_status&CPU_GEN_BOOT_RDY)) + goto CPUCheckMainCodeOKAndTurnOnCPU_Fail; + else + RT_TRACE(COMP_FIRMWARE, "Download Firmware: Boot ready!\n"); + + return rt_status; + +CPUCheckMainCodeOKAndTurnOnCPU_Fail: + RT_TRACE(COMP_ERR, "ERR in %s()\n", __func__); + rt_status = false; + return rt_status; +} + +static bool CPUcheck_firmware_ready(struct net_device *dev) +{ + + bool rt_status = true; + u32 CPU_status = 0; + unsigned long timeout; + + timeout = jiffies + MSECS(20); + while (time_before(jiffies, timeout)) { + CPU_status = read_nic_dword(dev, CPU_GEN); + if (CPU_status&CPU_GEN_FIRM_RDY) + break; + mdelay(2); + } + + if (!(CPU_status&CPU_GEN_FIRM_RDY)) + goto CPUCheckFirmwareReady_Fail; + else + RT_TRACE(COMP_FIRMWARE, "Download Firmware: Firmware ready!\n"); + + return rt_status; + +CPUCheckFirmwareReady_Fail: + RT_TRACE(COMP_ERR, "ERR in %s()\n", __func__); + rt_status = false; + return rt_status; + +} + +static bool firmware_check_ready(struct net_device *dev, + u8 load_fw_status) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rt_firmware *pfirmware = priv->pFirmware; + bool rt_status = true; + + switch (load_fw_status) { + case FW_INIT_STEP0_BOOT: + pfirmware->firmware_status = FW_STATUS_1_MOVE_BOOT_CODE; + break; + + case FW_INIT_STEP1_MAIN: + pfirmware->firmware_status = FW_STATUS_2_MOVE_MAIN_CODE; + + rt_status = CPUcheck_maincodeok_turnonCPU(dev); + if (rt_status) + pfirmware->firmware_status = FW_STATUS_3_TURNON_CPU; + else + RT_TRACE(COMP_FIRMWARE, "CPUcheck_maincodeok_turnon" + "CPU fail!\n"); + + break; + + case FW_INIT_STEP2_DATA: + pfirmware->firmware_status = FW_STATUS_4_MOVE_DATA_CODE; + mdelay(1); + + rt_status = CPUcheck_firmware_ready(dev); + if (rt_status) + pfirmware->firmware_status = FW_STATUS_5_READY; + else + RT_TRACE(COMP_FIRMWARE, "CPUcheck_firmware_ready fail" + "(%d)!\n", rt_status); + + break; + default: + rt_status = false; + RT_TRACE(COMP_FIRMWARE, "Unknown firware status"); + break; + } + + return rt_status; +} + +bool init_firmware(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + bool rt_status = true; + + u8 *firmware_img_buf[3] = { &Rtl8192PciEFwBootArray[0], + &Rtl8192PciEFwMainArray[0], + &Rtl8192PciEFwDataArray[0]}; + + u32 firmware_img_len[3] = { sizeof(Rtl8192PciEFwBootArray), + sizeof(Rtl8192PciEFwMainArray), + sizeof(Rtl8192PciEFwDataArray)}; + u32 file_length = 0; + u8 *mapped_file = NULL; + u8 init_step = 0; + enum opt_rst_type rst_opt = OPT_SYSTEM_RESET; + enum firmware_init_step starting_state = FW_INIT_STEP0_BOOT; + + struct rt_firmware *pfirmware = priv->pFirmware; + + RT_TRACE(COMP_FIRMWARE, " PlatformInitFirmware()==>\n"); + + if (pfirmware->firmware_status == FW_STATUS_0_INIT) { + rst_opt = OPT_SYSTEM_RESET; + starting_state = FW_INIT_STEP0_BOOT; + + } else if (pfirmware->firmware_status == FW_STATUS_5_READY) { + rst_opt = OPT_FIRMWARE_RESET; + starting_state = FW_INIT_STEP2_DATA; + } else { + RT_TRACE(COMP_FIRMWARE, "PlatformInitFirmware: undefined" + " firmware state\n"); + } + + priv->firmware_source = FW_SOURCE_IMG_FILE; + for (init_step = starting_state; init_step <= FW_INIT_STEP2_DATA; + init_step++) { + if (rst_opt == OPT_SYSTEM_RESET) { + switch (priv->firmware_source) { + case FW_SOURCE_IMG_FILE: + { + if (pfirmware->firmware_buf_size[init_step] == 0) { + const char *fw_name[3] = { "RTL8192E/boot.img", + "RTL8192E/main.img", + "RTL8192E/data.img" + }; + const struct firmware *fw_entry; + int rc; + rc = request_firmware(&fw_entry, + fw_name[init_step], &priv->pdev->dev); + if (rc < 0) { + RT_TRACE(COMP_FIRMWARE, "request firm" + "ware fail!\n"); + goto download_firmware_fail; + } + if (fw_entry->size > + sizeof(pfirmware->firmware_buf[init_step])) { + RT_TRACE(COMP_FIRMWARE, "img file size " + "exceed the container struct " + "buffer fail!\n"); + goto download_firmware_fail; + } + + if (init_step != FW_INIT_STEP1_MAIN) { + memcpy(pfirmware->firmware_buf[init_step], + fw_entry->data, fw_entry->size); + pfirmware->firmware_buf_size[init_step] = + fw_entry->size; + + } else { + memset(pfirmware->firmware_buf[init_step], + 0, 128); + memcpy(&pfirmware->firmware_buf[init_step][128], + fw_entry->data, fw_entry->size); + pfirmware->firmware_buf_size[init_step] = + fw_entry->size + 128; + } + + if (rst_opt == OPT_SYSTEM_RESET) + release_firmware(fw_entry); + } + mapped_file = pfirmware->firmware_buf[init_step]; + file_length = pfirmware->firmware_buf_size[init_step]; + break; + } + case FW_SOURCE_HEADER_FILE: + mapped_file = firmware_img_buf[init_step]; + file_length = firmware_img_len[init_step]; + if (init_step == FW_INIT_STEP2_DATA) { + memcpy(pfirmware->firmware_buf[init_step], mapped_file, file_length); + pfirmware->firmware_buf_size[init_step] = file_length; + } + break; + + default: + break; + } + + + } else if (rst_opt == OPT_FIRMWARE_RESET) { + mapped_file = pfirmware->firmware_buf[init_step]; + file_length = pfirmware->firmware_buf_size[init_step]; + } + + rt_status = fw_download_code(dev, mapped_file, file_length); + if (rt_status != true) { + goto download_firmware_fail; + } + + if (!firmware_check_ready(dev, init_step)) { + goto download_firmware_fail; + } + } + + RT_TRACE(COMP_FIRMWARE, "Firmware Download Success\n"); + return rt_status; + +download_firmware_fail: + RT_TRACE(COMP_ERR, "ERR in %s()\n", __func__); + rt_status = false; + return rt_status; + +} diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_firmware.h b/drivers/staging/rtl8192e/rtl8192e/r8192E_firmware.h new file mode 100644 index 000000000000..caa878833106 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_firmware.h @@ -0,0 +1,73 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ +#ifndef __INC_FIRMWARE_H +#define __INC_FIRMWARE_H + +#define RTL8190_CPU_START_OFFSET 0x80 + +#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8) + +enum firmware_init_step { + FW_INIT_STEP0_BOOT = 0, + FW_INIT_STEP1_MAIN = 1, + FW_INIT_STEP2_DATA = 2, +}; + +enum opt_rst_type { + OPT_SYSTEM_RESET = 0, + OPT_FIRMWARE_RESET = 1, +}; + +enum desc_packet_type { + DESC_PACKET_TYPE_INIT = 0, + DESC_PACKET_TYPE_NORMAL = 1, +}; + +enum firmware_source { + FW_SOURCE_IMG_FILE = 0, + FW_SOURCE_HEADER_FILE = 1, +}; + +enum firmware_status { + FW_STATUS_0_INIT = 0, + FW_STATUS_1_MOVE_BOOT_CODE = 1, + FW_STATUS_2_MOVE_MAIN_CODE = 2, + FW_STATUS_3_TURNON_CPU = 3, + FW_STATUS_4_MOVE_DATA_CODE = 4, + FW_STATUS_5_READY = 5, +}; + +struct fw_seg_container { + u16 seg_size; + u8 *seg_ptr; +}; + +struct rt_firmware { + enum firmware_status firmware_status; + u16 cmdpacket_frag_thresold; +#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 +#define MAX_FW_INIT_STEP 3 + u8 firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE]; + u16 firmware_buf_size[MAX_FW_INIT_STEP]; +}; + +bool init_firmware(struct net_device *dev); +extern void firmware_init_param(struct net_device *dev); + +#endif diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_hw.h b/drivers/staging/rtl8192e/rtl8192e/r8192E_hw.h new file mode 100644 index 000000000000..43c3fb859d10 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_hw.h @@ -0,0 +1,453 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ + + +#ifndef R8180_HW +#define R8180_HW + +enum baseband_config { + BaseBand_Config_PHY_REG = 0, + BaseBand_Config_AGC_TAB = 1, +}; + +#define RTL8187_REQT_READ 0xc0 +#define RTL8187_REQT_WRITE 0x40 +#define RTL8187_REQ_GET_REGS 0x05 +#define RTL8187_REQ_SET_REGS 0x05 + +#define MAX_TX_URB 5 +#define MAX_RX_URB 16 +#define RX_URB_SIZE 9100 + +#define BB_ANTATTEN_CHAN14 0x0c +#define BB_ANTENNA_B 0x40 + +#define BB_HOST_BANG (1<<30) +#define BB_HOST_BANG_EN (1<<2) +#define BB_HOST_BANG_CLK (1<<1) +#define BB_HOST_BANG_RW (1<<3) +#define BB_HOST_BANG_DATA 1 + +#define RTL8190_EEPROM_ID 0x8129 +#define EEPROM_VID 0x02 +#define EEPROM_DID 0x04 +#define EEPROM_NODE_ADDRESS_BYTE_0 0x0C + +#define EEPROM_TxPowerDiff 0x1F + + +#define EEPROM_PwDiff 0x21 +#define EEPROM_CrystalCap 0x22 + + + +#define EEPROM_TxPwIndex_CCK_V1 0x29 +#define EEPROM_TxPwIndex_OFDM_24G_V1 0x2C +#define EEPROM_TxPwIndex_Ver 0x27 + +#define EEPROM_Default_TxPowerDiff 0x0 +#define EEPROM_Default_ThermalMeter 0x77 +#define EEPROM_Default_AntTxPowerDiff 0x0 +#define EEPROM_Default_TxPwDiff_CrystalCap 0x5 +#define EEPROM_Default_PwDiff 0x4 +#define EEPROM_Default_CrystalCap 0x5 +#define EEPROM_Default_TxPower 0x1010 +#define EEPROM_ICVersion_ChannelPlan 0x7C +#define EEPROM_Customer_ID 0x7B +#define EEPROM_RFInd_PowerDiff 0x28 +#define EEPROM_ThermalMeter 0x29 +#define EEPROM_TxPwDiff_CrystalCap 0x2A +#define EEPROM_TxPwIndex_CCK 0x2C +#define EEPROM_TxPwIndex_OFDM_24G 0x3A +#define EEPROM_Default_TxPowerLevel 0x10 +#define EEPROM_IC_VER 0x7d +#define EEPROM_CRC 0x7e + +#define EEPROM_CID_DEFAULT 0x0 +#define EEPROM_CID_CAMEO 0x1 +#define EEPROM_CID_RUNTOP 0x2 +#define EEPROM_CID_Senao 0x3 +#define EEPROM_CID_TOSHIBA 0x4 +#define EEPROM_CID_NetCore 0x5 +#define EEPROM_CID_Nettronix 0x6 +#define EEPROM_CID_Pronet 0x7 +#define EEPROM_CID_DLINK 0x8 +#define EEPROM_CID_WHQL 0xFE +enum _RTL8192Pci_HW { + MAC0 = 0x000, + MAC1 = 0x001, + MAC2 = 0x002, + MAC3 = 0x003, + MAC4 = 0x004, + MAC5 = 0x005, + PCIF = 0x009, +#define MXDMA2_16bytes 0x000 +#define MXDMA2_32bytes 0x001 +#define MXDMA2_64bytes 0x010 +#define MXDMA2_128bytes 0x011 +#define MXDMA2_256bytes 0x100 +#define MXDMA2_512bytes 0x101 +#define MXDMA2_1024bytes 0x110 +#define MXDMA2_NoLimit 0x7 + +#define MULRW_SHIFT 3 +#define MXDMA2_RX_SHIFT 4 +#define MXDMA2_TX_SHIFT 0 + PMR = 0x00c, + EPROM_CMD = 0x00e, +#define EPROM_CMD_RESERVED_MASK BIT5 +#define EPROM_CMD_9356SEL BIT4 +#define EPROM_CMD_OPERATING_MODE_SHIFT 6 +#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) +#define EPROM_CMD_CONFIG 0x3 +#define EPROM_CMD_NORMAL 0 +#define EPROM_CMD_LOAD 1 +#define EPROM_CMD_PROGRAM 2 +#define EPROM_CS_SHIFT 3 +#define EPROM_CK_SHIFT 2 +#define EPROM_W_SHIFT 1 +#define EPROM_R_SHIFT 0 + + AFR = 0x010, +#define AFR_CardBEn (1<<0) +#define AFR_CLKRUN_SEL (1<<1) +#define AFR_FuncRegEn (1<<2) + + ANAPAR = 0x17, +#define BB_GLOBAL_RESET_BIT 0x1 + BB_GLOBAL_RESET = 0x020, + BSSIDR = 0x02E, + CMDR = 0x037, +#define CR_RST 0x10 +#define CR_RE 0x08 +#define CR_TE 0x04 +#define CR_MulRW 0x01 + SIFS = 0x03E, + TCR = 0x040, + RCR = 0x044, +#define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \ + BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23) +#define RCR_ONLYERLPKT BIT31 +#define RCR_ENCS2 BIT30 +#define RCR_ENCS1 BIT29 +#define RCR_ENMBID BIT27 +#define RCR_ACKTXBW (BIT24|BIT25) +#define RCR_CBSSID BIT23 +#define RCR_APWRMGT BIT22 +#define RCR_ADD3 BIT21 +#define RCR_AMF BIT20 +#define RCR_ACF BIT19 +#define RCR_ADF BIT18 +#define RCR_RXFTH BIT13 +#define RCR_AICV BIT12 +#define RCR_ACRC32 BIT5 +#define RCR_AB BIT3 +#define RCR_AM BIT2 +#define RCR_APM BIT1 +#define RCR_AAP BIT0 +#define RCR_MXDMA_OFFSET 8 +#define RCR_FIFO_OFFSET 13 + SLOT_TIME = 0x049, + ACK_TIMEOUT = 0x04c, + PIFS_TIME = 0x04d, + USTIME = 0x04e, + EDCAPARA_BE = 0x050, + EDCAPARA_BK = 0x054, + EDCAPARA_VO = 0x058, + EDCAPARA_VI = 0x05C, +#define AC_PARAM_TXOP_LIMIT_OFFSET 16 +#define AC_PARAM_ECW_MAX_OFFSET 12 +#define AC_PARAM_ECW_MIN_OFFSET 8 +#define AC_PARAM_AIFS_OFFSET 0 + RFPC = 0x05F, + CWRR = 0x060, + BCN_TCFG = 0x062, +#define BCN_TCFG_CW_SHIFT 8 +#define BCN_TCFG_IFS 0 + BCN_INTERVAL = 0x070, + ATIMWND = 0x072, + BCN_DRV_EARLY_INT = 0x074, +#define BCN_DRV_EARLY_INT_SWBCN_SHIFT 8 +#define BCN_DRV_EARLY_INT_TIME_SHIFT 0 + BCN_DMATIME = 0x076, + BCN_ERR_THRESH = 0x078, + RWCAM = 0x0A0, +#define CAM_CM_SecCAMPolling BIT31 +#define CAM_CM_SecCAMClr BIT30 +#define CAM_CM_SecCAMWE BIT16 +#define CAM_VALID BIT15 +#define CAM_NOTVALID 0x0000 +#define CAM_USEDK BIT5 + +#define CAM_NONE 0x0 +#define CAM_WEP40 0x01 +#define CAM_TKIP 0x02 +#define CAM_AES 0x04 +#define CAM_WEP104 0x05 + +#define TOTAL_CAM_ENTRY 32 + +#define CAM_CONFIG_USEDK true +#define CAM_CONFIG_NO_USEDK false +#define CAM_WRITE BIT16 +#define CAM_READ 0x00000000 +#define CAM_POLLINIG BIT31 +#define SCR_UseDK 0x01 + WCAMI = 0x0A4, + RCAMO = 0x0A8, + SECR = 0x0B0, +#define SCR_TxUseDK BIT0 +#define SCR_RxUseDK BIT1 +#define SCR_TxEncEnable BIT2 +#define SCR_RxDecEnable BIT3 +#define SCR_SKByA2 BIT4 +#define SCR_NoSKMC BIT5 + SWREGULATOR = 0x0BD, + INTA_MASK = 0x0f4, +#define IMR8190_DISABLED 0x0 +#define IMR_ATIMEND BIT28 +#define IMR_TBDOK BIT27 +#define IMR_TBDER BIT26 +#define IMR_TXFOVW BIT15 +#define IMR_TIMEOUT0 BIT14 +#define IMR_BcnInt BIT13 +#define IMR_RXFOVW BIT12 +#define IMR_RDU BIT11 +#define IMR_RXCMDOK BIT10 +#define IMR_BDOK BIT9 +#define IMR_HIGHDOK BIT8 +#define IMR_COMDOK BIT7 +#define IMR_MGNTDOK BIT6 +#define IMR_HCCADOK BIT5 +#define IMR_BKDOK BIT4 +#define IMR_BEDOK BIT3 +#define IMR_VIDOK BIT2 +#define IMR_VODOK BIT1 +#define IMR_ROK BIT0 + ISR = 0x0f8, + TPPoll = 0x0fd, +#define TPPoll_BKQ BIT0 +#define TPPoll_BEQ BIT1 +#define TPPoll_VIQ BIT2 +#define TPPoll_VOQ BIT3 +#define TPPoll_BQ BIT4 +#define TPPoll_CQ BIT5 +#define TPPoll_MQ BIT6 +#define TPPoll_HQ BIT7 +#define TPPoll_HCCAQ BIT8 +#define TPPoll_StopBK BIT9 +#define TPPoll_StopBE BIT10 +#define TPPoll_StopVI BIT11 +#define TPPoll_StopVO BIT12 +#define TPPoll_StopMgt BIT13 +#define TPPoll_StopHigh BIT14 +#define TPPoll_StopHCCA BIT15 +#define TPPoll_SHIFT 8 + + PSR = 0x0ff, +#define PSR_GEN 0x0 +#define PSR_CPU 0x1 + CPU_GEN = 0x100, + BB_RESET = 0x101, +#define CPU_CCK_LOOPBACK 0x00030000 +#define CPU_GEN_SYSTEM_RESET 0x00000001 +#define CPU_GEN_FIRMWARE_RESET 0x00000008 +#define CPU_GEN_BOOT_RDY 0x00000010 +#define CPU_GEN_FIRM_RDY 0x00000020 +#define CPU_GEN_PUT_CODE_OK 0x00000080 +#define CPU_GEN_BB_RST 0x00000100 +#define CPU_GEN_PWR_STB_CPU 0x00000004 +#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF +#define CPU_GEN_NO_LOOPBACK_SET 0x00080000 +#define CPU_GEN_GPIO_UART 0x00007000 + + LED1Cfg = 0x154, + LED0Cfg = 0x155, + + AcmAvg = 0x170, + AcmHwCtrl = 0x171, +#define AcmHw_HwEn BIT0 +#define AcmHw_BeqEn BIT1 +#define AcmHw_ViqEn BIT2 +#define AcmHw_VoqEn BIT3 +#define AcmHw_BeqStatus BIT4 +#define AcmHw_ViqStatus BIT5 +#define AcmHw_VoqStatus BIT6 + AcmFwCtrl = 0x172, +#define AcmFw_BeqStatus BIT0 +#define AcmFw_ViqStatus BIT1 +#define AcmFw_VoqStatus BIT2 + VOAdmTime = 0x174, + VIAdmTime = 0x178, + BEAdmTime = 0x17C, + RQPN1 = 0x180, + RQPN2 = 0x184, + RQPN3 = 0x188, + QPRR = 0x1E0, + QPNR = 0x1F0, + BQDA = 0x200, + HQDA = 0x204, + CQDA = 0x208, + MQDA = 0x20C, + HCCAQDA = 0x210, + VOQDA = 0x214, + VIQDA = 0x218, + BEQDA = 0x21C, + BKQDA = 0x220, + RCQDA = 0x224, + RDQDA = 0x228, + + MAR0 = 0x240, + MAR4 = 0x244, + + CCX_PERIOD = 0x250, + CLM_RESULT = 0x251, + NHM_PERIOD = 0x252, + + NHM_THRESHOLD0 = 0x253, + NHM_THRESHOLD1 = 0x254, + NHM_THRESHOLD2 = 0x255, + NHM_THRESHOLD3 = 0x256, + NHM_THRESHOLD4 = 0x257, + NHM_THRESHOLD5 = 0x258, + NHM_THRESHOLD6 = 0x259, + + MCTRL = 0x25A, + + NHM_RPI_COUNTER0 = 0x264, + NHM_RPI_COUNTER1 = 0x265, + NHM_RPI_COUNTER2 = 0x266, + NHM_RPI_COUNTER3 = 0x267, + NHM_RPI_COUNTER4 = 0x268, + NHM_RPI_COUNTER5 = 0x269, + NHM_RPI_COUNTER6 = 0x26A, + NHM_RPI_COUNTER7 = 0x26B, + WFCRC0 = 0x2f0, + WFCRC1 = 0x2f4, + WFCRC2 = 0x2f8, + + BW_OPMODE = 0x300, +#define BW_OPMODE_11J BIT0 +#define BW_OPMODE_5G BIT1 +#define BW_OPMODE_20MHZ BIT2 + IC_VERRSION = 0x301, + MSR = 0x303, +#define MSR_LINK_MASK ((1<<0)|(1<<1)) +#define MSR_LINK_MANAGED 2 +#define MSR_LINK_NONE 0 +#define MSR_LINK_SHIFT 0 +#define MSR_LINK_ADHOC 1 +#define MSR_LINK_MASTER 3 +#define MSR_LINK_ENEDCA (1<<4) + +#define MSR_NOLINK 0x00 +#define MSR_ADHOC 0x01 +#define MSR_INFRA 0x02 +#define MSR_AP 0x03 + + RETRY_LIMIT = 0x304, +#define RETRY_LIMIT_SHORT_SHIFT 8 +#define RETRY_LIMIT_LONG_SHIFT 0 + TSFR = 0x308, + RRSR = 0x310, +#define RRSR_RSC_OFFSET 21 +#define RRSR_SHORT_OFFSET 23 +#define RRSR_RSC_DUPLICATE 0x600000 +#define RRSR_RSC_UPSUBCHNL 0x400000 +#define RRSR_RSC_LOWSUBCHNL 0x200000 +#define RRSR_SHORT 0x800000 +#define RRSR_1M BIT0 +#define RRSR_2M BIT1 +#define RRSR_5_5M BIT2 +#define RRSR_11M BIT3 +#define RRSR_6M BIT4 +#define RRSR_9M BIT5 +#define RRSR_12M BIT6 +#define RRSR_18M BIT7 +#define RRSR_24M BIT8 +#define RRSR_36M BIT9 +#define RRSR_48M BIT10 +#define RRSR_54M BIT11 +#define RRSR_MCS0 BIT12 +#define RRSR_MCS1 BIT13 +#define RRSR_MCS2 BIT14 +#define RRSR_MCS3 BIT15 +#define RRSR_MCS4 BIT16 +#define RRSR_MCS5 BIT17 +#define RRSR_MCS6 BIT18 +#define RRSR_MCS7 BIT19 +#define BRSR_AckShortPmb BIT23 + UFWP = 0x318, + RATR0 = 0x320, +#define RATR_1M 0x00000001 +#define RATR_2M 0x00000002 +#define RATR_55M 0x00000004 +#define RATR_11M 0x00000008 +#define RATR_6M 0x00000010 +#define RATR_9M 0x00000020 +#define RATR_12M 0x00000040 +#define RATR_18M 0x00000080 +#define RATR_24M 0x00000100 +#define RATR_36M 0x00000200 +#define RATR_48M 0x00000400 +#define RATR_54M 0x00000800 +#define RATR_MCS0 0x00001000 +#define RATR_MCS1 0x00002000 +#define RATR_MCS2 0x00004000 +#define RATR_MCS3 0x00008000 +#define RATR_MCS4 0x00010000 +#define RATR_MCS5 0x00020000 +#define RATR_MCS6 0x00040000 +#define RATR_MCS7 0x00080000 +#define RATR_MCS8 0x00100000 +#define RATR_MCS9 0x00200000 +#define RATR_MCS10 0x00400000 +#define RATR_MCS11 0x00800000 +#define RATR_MCS12 0x01000000 +#define RATR_MCS13 0x02000000 +#define RATR_MCS14 0x04000000 +#define RATR_MCS15 0x08000000 +#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M) +#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M | \ + RATR_24M | RATR_36M | RATR_48M | RATR_54M) +#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \ + RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \ + RATR_MCS6 | RATR_MCS7) +#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \ + RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \ + RATR_MCS14|RATR_MCS15) + + + DRIVER_RSSI = 0x32c, + MCS_TXAGC = 0x340, + CCK_TXAGC = 0x348, + MacBlkCtrl = 0x403, + +} +; + +#define GPI 0x108 +#define GPO 0x109 +#define GPE 0x10a + +#define HWSET_MAX_SIZE_92S 128 + +#define ANAPAR_FOR_8192PciE 0x17 + +#endif diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_hwimg.c b/drivers/staging/rtl8192e/rtl8192e/r8192E_hwimg.c new file mode 100644 index 000000000000..08e7dbb6694b --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_hwimg.c @@ -0,0 +1,3336 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ +/*Created on 2008/11/18, 3: 7*/ + +#include "r8192E_hwimg.h" + +u8 Rtl8192PciEFwBootArray[BootArrayLengthPciE] = { +0x10,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x3c,0x08,0xbf,0xc0,0x25,0x08,0x00,0x08, +0x3c,0x09,0xb0,0x03,0xad,0x28,0x00,0x20,0x40,0x80,0x68,0x00,0x00,0x00,0x00,0x00, +0x3c,0x0a,0xd0,0x00,0x40,0x8a,0x60,0x00,0x00,0x00,0x00,0x00,0x3c,0x08,0x80,0x01, +0x25,0x08,0xa8,0x04,0x24,0x09,0x00,0x01,0x3c,0x01,0x7f,0xff,0x34,0x21,0xff,0xff, +0x01,0x01,0x50,0x24,0x00,0x09,0x48,0x40,0x35,0x29,0x00,0x01,0x01,0x2a,0x10,0x2b, +0x14,0x40,0xff,0xfc,0x00,0x00,0x00,0x00,0x3c,0x0a,0x00,0x00,0x25,0x4a,0x00,0x00, +0x4c,0x8a,0x00,0x00,0x4c,0x89,0x08,0x00,0x00,0x00,0x00,0x00,0x3c,0x08,0x80,0x01, +0x25,0x08,0xa8,0x04,0x3c,0x01,0x80,0x00,0x01,0x21,0x48,0x25,0x3c,0x0a,0xbf,0xc0, +0x25,0x4a,0x00,0x7c,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,0xad,0x00,0x00,0x00, +0x21,0x08,0x00,0x04,0x01,0x09,0x10,0x2b,0x14,0x40,0xff,0xf8,0x00,0x00,0x00,0x00, +0x3c,0x08,0x80,0x01,0x25,0x08,0x7f,0xff,0x24,0x09,0x00,0x01,0x3c,0x01,0x7f,0xff, +0x34,0x21,0xff,0xff,0x01,0x01,0x50,0x24,0x00,0x09,0x48,0x40,0x35,0x29,0x00,0x01, +0x01,0x2a,0x10,0x2b,0x14,0x40,0xff,0xfc,0x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x01, +0x25,0x4a,0x00,0x00,0x3c,0x01,0x7f,0xff,0x34,0x21,0xff,0xff,0x01,0x41,0x50,0x24, +0x3c,0x09,0x00,0x01,0x35,0x29,0x7f,0xff,0x4c,0x8a,0x20,0x00,0x4c,0x89,0x28,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x08,0x04,0x10, +0x00,0x00,0x00,0x00,0x40,0x88,0xa0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x3c,0x08,0xbf,0xc0,0x00,0x00,0x00,0x00,0x8d,0x09,0x00,0x00,0x00,0x00,0x00,0x00, +0x3c,0x0a,0xbf,0xc0,0x25,0x4a,0x01,0x20,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20, +0x3c,0x08,0xb0,0x03,0x8d,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x35,0x29,0x00,0x10, +0xad,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x3c,0x08,0x80,0x00,0x25,0x08,0x4b,0x94, +0x01,0x00,0x00,0x08,0x00,0x00,0x00,0x00,}; + +u8 Rtl8192PciEFwMainArray[MainArrayLengthPciE] = { +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 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+0xa0,0x40,0x00,0x00,0x90,0x43,0x00,0x00,0x24,0x02,0x00,0x03,0x3c,0x05,0xb0,0x07, +0xa3,0xa3,0x00,0x00,0xa0,0xc2,0x00,0x00,0x90,0xc4,0x00,0x00,0x34,0xa5,0x00,0x10, +0x24,0x02,0x00,0x06,0x3c,0x03,0xb0,0x07,0xa3,0xa4,0x00,0x00,0x34,0x63,0x00,0x38, +0xa0,0xa2,0x00,0x00,0x90,0x64,0x00,0x00,0x3c,0x02,0xb0,0x07,0x34,0x42,0x00,0x20, +0xa3,0xa4,0x00,0x00,0xa0,0xa0,0x00,0x00,0x90,0xa3,0x00,0x00,0xaf,0x82,0xbf,0x30, +0xa3,0xa3,0x00,0x00,0xa0,0x40,0x00,0x00,0x90,0x43,0x00,0x00,0x03,0xe0,0x00,0x08, +0x27,0xbd,0x00,0x08,}; + +u8 Rtl8192PciEFwDataArray[DataArrayLengthPciE] = { +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x10,0x00,0x08,0x00, +0x02,0xe9,0x01,0x74,0x02,0xab,0x01,0xc7,0x01,0x55,0x00,0xe4,0x00,0xab,0x00,0x72, +0x00,0x55,0x00,0x4c,0x00,0x4c,0x00,0x4c,0x00,0x4c,0x00,0x4c,0x02,0x76,0x01,0x3b, +0x00,0xd2,0x00,0x9e,0x00,0x69,0x00,0x4f,0x00,0x46,0x00,0x3f,0x01,0x3b,0x00,0x9e, +0x00,0x69,0x00,0x4f,0x00,0x35,0x00,0x27,0x00,0x23,0x00,0x20,0x01,0x2f,0x00,0x98, +0x00,0x65,0x00,0x4c,0x00,0x33,0x00,0x26,0x00,0x22,0x00,0x1e,0x00,0x98,0x00,0x4c, +0x00,0x33,0x00,0x26,0x00,0x19,0x00,0x13,0x00,0x11,0x00,0x0f,0x02,0x39,0x01,0x1c, +0x00,0xbd,0x00,0x8e,0x00,0x5f,0x00,0x47,0x00,0x3f,0x00,0x39,0x01,0x1c,0x00,0x8e, +0x00,0x5f,0x00,0x47,0x00,0x2f,0x00,0x23,0x00,0x20,0x00,0x1c,0x01,0x11,0x00,0x89, +0x00,0x5b,0x00,0x44,0x00,0x2e,0x00,0x22,0x00,0x1e,0x00,0x1b,0x00,0x89,0x00,0x44, +0x00,0x2e,0x00,0x22,0x00,0x17,0x00,0x11,0x00,0x0f,0x00,0x0e,0x02,0xab,0x02,0xab, +0x02,0x66,0x02,0x66,0x07,0x06,0x06,0x06,0x05,0x06,0x07,0x08,0x04,0x06,0x07,0x08, +0x09,0x0a,0x0b,0x0b,0x49,0x6e,0x74,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x54,0x4c, +0x42,0x4d,0x4f,0x44,0x00,0x00,0x00,0x00,0x54,0x4c,0x42,0x4c,0x5f,0x64,0x61,0x74, +0x61,0x00,0x54,0x4c,0x42,0x53,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x64,0x45,0x4c, +0x5f,0x64,0x61,0x74,0x61,0x00,0x41,0x64,0x45,0x53,0x00,0x00,0x00,0x00,0x00,0x00, +0x45,0x78,0x63,0x43,0x6f,0x64,0x65,0x36,0x00,0x00,0x45,0x78,0x63,0x43,0x6f,0x64, +0x65,0x37,0x00,0x00,0x53,0x79,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x42,0x70, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x52,0x49,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x43,0x70,0x55,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x4f,0x76,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x01,0x0b,0x63, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x10,0x00,0x00,0x00,0x2c, +0x00,0x00,0x00,0x58,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x48,0x00,0x00,0x00,0x60, +0x00,0x00,0x00,0x90,0x00,0x00,0x00,0xc0,0x00,0x00,0x01,0x20,0x00,0x00,0x01,0x80, +0x00,0x00,0x01,0xb0,0x00,0x00,0x00,0x34,0x00,0x00,0x00,0x68,0x00,0x00,0x00,0x9c, +0x00,0x00,0x00,0xd0,0x00,0x00,0x01,0x38,0x00,0x00,0x01,0xa0,0x00,0x00,0x01,0xd4, +0x00,0x00,0x02,0x08,0x00,0x00,0x00,0x68,0x00,0x00,0x00,0xd0,0x00,0x00,0x01,0x38, +0x00,0x00,0x01,0xa0,0x00,0x00,0x02,0x6f,0x00,0x00,0x03,0x40,0x00,0x00,0x03,0xa8, +0x00,0x00,0x04,0x10,0x01,0x01,0x01,0x02,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04, +0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x02,0x03,0x03,0x04,0x05,0x06,0x07,0x08, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x07,0x6c,0x80,0x00,0x07,0x80, +0x80,0x00,0x07,0x80,0x80,0x00,0x07,0x70,0x80,0x00,0x07,0x70,0x80,0x00,0x07,0x94, +0x80,0x00,0x56,0xb0,0x80,0x00,0x57,0x08,0x80,0x00,0x57,0x30,0x80,0x00,0x58,0x28, +0x80,0x00,0x58,0xe0,0x80,0x00,0x59,0x88,0x80,0x00,0x59,0xfc,0x80,0x00,0x5b,0x08, +0x80,0x00,0x5b,0x40,0x80,0x00,0x5b,0x54,0x80,0x00,0x5b,0x68,0x80,0x00,0x5c,0x50, +0x80,0x00,0x5c,0x90,0x80,0x00,0x5d,0x44,0x80,0x00,0x5d,0x6c,0x80,0x00,0x56,0x70, +0x80,0x00,0x5d,0xbc,0x80,0x00,0x64,0x48,0x80,0x00,0x64,0xc0,0x80,0x00,0x64,0xcc, +0x80,0x00,0x64,0xd8,0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60, +0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60, +0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60, +0x80,0x00,0x64,0x60,0x80,0x00,0x64,0xe4,0x80,0x00,0x64,0xf0,0x80,0x00,0x64,0xfc, +0x80,0x00,0x87,0xa4,0x80,0x00,0x87,0xa4,0x80,0x00,0x87,0xa4,0x80,0x00,0x87,0xd8, +0x80,0x00,0x88,0x18,0x80,0x00,0x88,0x50,0x80,0x00,0x88,0x80,0x80,0x00,0x88,0xb0, +0x80,0x00,0x88,0xc4,0x80,0x00,0x89,0x2c,0x80,0x00,0x89,0x40,0x80,0x00,0x89,0x7c, +0x80,0x00,0x89,0x84,0x80,0x00,0x89,0xc0,0x80,0x00,0x89,0xd4,0x80,0x00,0x89,0xdc, +0x80,0x00,0x89,0xe4,0x80,0x00,0x89,0xe4,0x80,0x00,0x89,0xe4,0x80,0x00,0x89,0xe4, +0x80,0x00,0x8a,0x14,0x80,0x00,0x8a,0x28,0x80,0x00,0x8a,0x3c,0x80,0x00,0x86,0xe8, +0x80,0x00,0x8d,0x68,0x80,0x00,0x8d,0x68,0x80,0x00,0x8d,0x68,0x80,0x00,0x8d,0x9c, +0x80,0x00,0x8d,0xdc,0x80,0x00,0x8e,0x14,0x80,0x00,0x8e,0x44,0x80,0x00,0x8e,0x74, +0x80,0x00,0x8e,0x88,0x80,0x00,0x8e,0xf0,0x80,0x00,0x8f,0x04,0x80,0x00,0x8f,0x40, +0x80,0x00,0x8f,0x48,0x80,0x00,0x8f,0x84,0x80,0x00,0x8f,0x98,0x80,0x00,0x8f,0xa0, +0x80,0x00,0x8f,0xa8,0x80,0x00,0x8f,0xa8,0x80,0x00,0x8f,0xa8,0x80,0x00,0x8f,0xa8, +0x80,0x00,0x8f,0xd8,0x80,0x00,0x8f,0xec,0x80,0x00,0x90,0x00,0x80,0x00,0x8b,0x88, +}; + +u32 Rtl8192PciEPHY_REGArray[PHY_REGArrayLengthPciE] = {0x0,}; + +u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLengthPciE] = { + 0x800, 0x00000000, + 0x804, 0x00000001, + 0x808, 0x0000fc00, + 0x80c, 0x0000001c, + 0x810, 0x801010aa, + 0x814, 0x008514d0, + 0x818, 0x00000040, + 0x81c, 0x00000000, + 0x820, 0x00000004, + 0x824, 0x00690000, + 0x828, 0x00000004, + 0x82c, 0x00e90000, + 0x830, 0x00000004, + 0x834, 0x00690000, + 0x838, 0x00000004, + 0x83c, 0x00e90000, + 0x840, 0x00000000, + 0x844, 0x00000000, + 0x848, 0x00000000, + 0x84c, 0x00000000, + 0x850, 0x00000000, + 0x854, 0x00000000, + 0x858, 0x65a965a9, + 0x85c, 0x65a965a9, + 0x860, 0x001f0010, + 0x864, 0x007f0010, + 0x868, 0x001f0010, + 0x86c, 0x007f0010, + 0x870, 0x0f100f70, + 0x874, 0x0f100f70, + 0x878, 0x00000000, + 0x87c, 0x00000000, + 0x880, 0x6870e36c, + 0x884, 0xe3573600, + 0x888, 0x4260c340, + 0x88c, 0x0000ff00, + 0x890, 0x00000000, + 0x894, 0xfffffffe, + 0x898, 0x4c42382f, + 0x89c, 0x00656056, + 0x8b0, 0x00000000, + 0x8e0, 0x00000000, + 0x8e4, 0x00000000, + 0x900, 0x00000000, + 0x904, 0x00000023, + 0x908, 0x00000000, + 0x90c, 0x31121311, + 0xa00, 0x00d0c7d8, + 0xa04, 0x811f0008, + 0xa08, 0x80cd8300, + 0xa0c, 0x2e62740f, + 0xa10, 0x95009b78, + 0xa14, 0x11145008, + 0xa18, 0x00881117, + 0xa1c, 0x89140fa0, + 0xa20, 0x1a1b0000, + 0xa24, 0x090e1317, + 0xa28, 0x00000204, + 0xa2c, 0x00000000, + 0xc00, 0x00000040, + 0xc04, 0x00005433, + 0xc08, 0x000000e4, + 0xc0c, 0x6c6c6c6c, + 0xc10, 0x08800000, + 0xc14, 0x40000100, + 0xc18, 0x08000000, + 0xc1c, 0x40000100, + 0xc20, 0x08000000, + 0xc24, 0x40000100, + 0xc28, 0x08000000, + 0xc2c, 0x40000100, + 0xc30, 0x6de9ac44, + 0xc34, 0x465c52cd, + 0xc38, 0x497f5994, + 0xc3c, 0x0a969764, + 0xc40, 0x1f7c403f, + 0xc44, 0x000100b7, + 0xc48, 0xec020000, + 0xc4c, 0x00000300, + 0xc50, 0x69543420, + 0xc54, 0x433c0094, + 0xc58, 0x69543420, + 0xc5c, 0x433c0094, + 0xc60, 0x69543420, + 0xc64, 0x433c0094, + 0xc68, 0x69543420, + 0xc6c, 0x433c0094, + 0xc70, 0x2c7f000d, + 0xc74, 0x0186175b, + 0xc78, 0x0000001f, + 0xc7c, 0x00b91612, + 0xc80, 0x40000100, + 0xc84, 0x20000000, + 0xc88, 0x40000100, + 0xc8c, 0x20200000, + 0xc90, 0x40000100, + 0xc94, 0x00000000, + 0xc98, 0x40000100, + 0xc9c, 0x00000000, + 0xca0, 0x00492492, + 0xca4, 0x00000000, + 0xca8, 0x00000000, + 0xcac, 0x00000000, + 0xcb0, 0x00000000, + 0xcb4, 0x00000000, + 0xcb8, 0x00000000, + 0xcbc, 0x00492492, + 0xcc0, 0x00000000, + 0xcc4, 0x00000000, + 0xcc8, 0x00000000, + 0xccc, 0x00000000, + 0xcd0, 0x00000000, + 0xcd4, 0x00000000, + 0xcd8, 0x64b22427, + 0xcdc, 0x00766932, + 0xce0, 0x00222222, + 0xd00, 0x00000750, + 0xd04, 0x00000403, + 0xd08, 0x0000907f, + 0xd0c, 0x00000001, + 0xd10, 0xa0633333, + 0xd14, 0x33333c63, + 0xd18, 0x6a8f5b6b, + 0xd1c, 0x00000000, + 0xd20, 0x00000000, + 0xd24, 0x00000000, + 0xd28, 0x00000000, + 0xd2c, 0xcc979975, + 0xd30, 0x00000000, + 0xd34, 0x00000000, + 0xd38, 0x00000000, + 0xd3c, 0x00027293, + 0xd40, 0x00000000, + 0xd44, 0x00000000, + 0xd48, 0x00000000, + 0xd4c, 0x00000000, + 0xd50, 0x6437140a, + 0xd54, 0x024dbd02, + 0xd58, 0x00000000, + 0xd5c, 0x04032064, + 0xe00, 0x161a1a1a, + 0xe04, 0x12121416, + 0xe08, 0x00001800, + 0xe0c, 0x00000000, + 0xe10, 0x161a1a1a, + 0xe14, 0x12121416, + 0xe18, 0x161a1a1a, + 0xe1c, 0x12121416, +}; + +u32 Rtl8192PciERadioA_Array[RadioA_ArrayLengthPciE] = { + 0x019, 0x00000003, + 0x000, 0x000000bf, + 0x001, 0x00000ee0, + 0x002, 0x0000004c, + 0x003, 0x000007f1, + 0x004, 0x00000975, + 0x005, 0x00000c58, + 0x006, 0x00000ae6, + 0x007, 0x000000ca, + 0x008, 0x00000e1c, + 0x009, 0x000007f0, + 0x00a, 0x000009d0, + 0x00b, 0x000001ba, + 0x00c, 0x00000240, + 0x00e, 0x00000020, + 0x00f, 0x00000990, + 0x012, 0x00000806, + 0x014, 0x000005ab, + 0x015, 0x00000f80, + 0x016, 0x00000020, + 0x017, 0x00000597, + 0x018, 0x0000050a, + 0x01a, 0x00000f80, + 0x01b, 0x00000f5e, + 0x01c, 0x00000008, + 0x01d, 0x00000607, + 0x01e, 0x000006cc, + 0x01f, 0x00000000, + 0x020, 0x000001a5, + 0x01f, 0x00000001, + 0x020, 0x00000165, + 0x01f, 0x00000002, + 0x020, 0x000000c6, + 0x01f, 0x00000003, + 0x020, 0x00000086, + 0x01f, 0x00000004, + 0x020, 0x00000046, + 0x01f, 0x00000005, + 0x020, 0x000001e6, + 0x01f, 0x00000006, + 0x020, 0x000001a6, + 0x01f, 0x00000007, + 0x020, 0x00000166, + 0x01f, 0x00000008, + 0x020, 0x000000c7, + 0x01f, 0x00000009, + 0x020, 0x00000087, + 0x01f, 0x0000000a, + 0x020, 0x000000f7, + 0x01f, 0x0000000b, + 0x020, 0x000000d7, + 0x01f, 0x0000000c, + 0x020, 0x000000b7, + 0x01f, 0x0000000d, + 0x020, 0x00000097, + 0x01f, 0x0000000e, + 0x020, 0x00000077, + 0x01f, 0x0000000f, + 0x020, 0x00000057, + 0x01f, 0x00000010, + 0x020, 0x00000037, + 0x01f, 0x00000011, + 0x020, 0x000000fb, + 0x01f, 0x00000012, + 0x020, 0x000000db, + 0x01f, 0x00000013, + 0x020, 0x000000bb, + 0x01f, 0x00000014, + 0x020, 0x000000ff, + 0x01f, 0x00000015, + 0x020, 0x000000e3, + 0x01f, 0x00000016, + 0x020, 0x000000c3, + 0x01f, 0x00000017, + 0x020, 0x000000a3, + 0x01f, 0x00000018, + 0x020, 0x00000083, + 0x01f, 0x00000019, + 0x020, 0x00000063, + 0x01f, 0x0000001a, + 0x020, 0x00000043, + 0x01f, 0x0000001b, + 0x020, 0x00000023, + 0x01f, 0x0000001c, + 0x020, 0x00000003, + 0x01f, 0x0000001d, + 0x020, 0x000001e3, + 0x01f, 0x0000001e, + 0x020, 0x000001c3, + 0x01f, 0x0000001f, + 0x020, 0x000001a3, + 0x01f, 0x00000020, + 0x020, 0x00000183, + 0x01f, 0x00000021, + 0x020, 0x00000163, + 0x01f, 0x00000022, + 0x020, 0x00000143, + 0x01f, 0x00000023, + 0x020, 0x00000123, + 0x01f, 0x00000024, + 0x020, 0x00000103, + 0x023, 0x00000203, + 0x024, 0x00000100, + 0x00b, 0x000001ba, + 0x02c, 0x000003d7, + 0x02d, 0x00000ff0, + 0x000, 0x00000037, + 0x004, 0x00000160, + 0x007, 0x00000080, + 0x002, 0x0000088d, + 0x0fe, 0x00000000, + 0x0fe, 0x00000000, + 0x016, 0x00000200, + 0x016, 0x00000380, + 0x016, 0x00000020, + 0x016, 0x000001a0, + 0x000, 0x000000bf, + 0x00d, 0x0000001f, + 0x00d, 0x00000c9f, + 0x002, 0x0000004d, + 0x000, 0x00000cbf, + 0x004, 0x00000975, + 0x007, 0x00000700, +}; + +u32 Rtl8192PciERadioB_Array[RadioB_ArrayLengthPciE] = { + 0x019, 0x00000003, + 0x000, 0x000000bf, + 0x001, 0x000006e0, + 0x002, 0x0000004c, + 0x003, 0x000007f1, + 0x004, 0x00000975, + 0x005, 0x00000c58, + 0x006, 0x00000ae6, + 0x007, 0x000000ca, + 0x008, 0x00000e1c, + 0x000, 0x000000b7, + 0x00a, 0x00000850, + 0x000, 0x000000bf, + 0x00b, 0x000001ba, + 0x00c, 0x00000240, + 0x00e, 0x00000020, + 0x015, 0x00000f80, + 0x016, 0x00000020, + 0x017, 0x00000597, + 0x018, 0x0000050a, + 0x01a, 0x00000e00, + 0x01b, 0x00000f5e, + 0x01d, 0x00000607, + 0x01e, 0x000006cc, + 0x00b, 0x000001ba, + 0x023, 0x00000203, + 0x024, 0x00000100, + 0x000, 0x00000037, + 0x004, 0x00000160, + 0x016, 0x00000200, + 0x016, 0x00000380, + 0x016, 0x00000020, + 0x016, 0x000001a0, + 0x00d, 0x00000ccc, + 0x000, 0x000000bf, + 0x002, 0x0000004d, + 0x000, 0x00000cbf, + 0x004, 0x00000975, + 0x007, 0x00000700, +}; + +u32 Rtl8192PciERadioC_Array[RadioC_ArrayLengthPciE] = { + 0x0, }; + +u32 Rtl8192PciERadioD_Array[RadioD_ArrayLengthPciE] = { + 0x0, }; + +u32 Rtl8192PciEMACPHY_Array[] = { + 0x03c, 0xffff0000, 0x00000f0f, + 0x340, 0xffffffff, 0x161a1a1a, + 0x344, 0xffffffff, 0x12121416, + 0x348, 0x0000ffff, 0x00001818, + 0x12c, 0xffffffff, 0x04000802, + 0x318, 0x00000fff, 0x00000100, +}; + +u32 Rtl8192PciEMACPHY_Array_PG[] = { + 0x03c, 0xffff0000, 0x00000f0f, + 0xe00, 0xffffffff, 0x06090909, + 0xe04, 0xffffffff, 0x00030306, + 0xe08, 0x0000ff00, 0x00000000, + 0xe10, 0xffffffff, 0x0a0c0d0f, + 0xe14, 0xffffffff, 0x06070809, + 0xe18, 0xffffffff, 0x0a0c0d0f, + 0xe1c, 0xffffffff, 0x06070809, + 0x12c, 0xffffffff, 0x04000802, + 0x318, 0x00000fff, 0x00000800, +}; + +u32 Rtl8192PciEAGCTAB_Array[AGCTAB_ArrayLengthPciE] = { + 0xc78, 0x7d000001, + 0xc78, 0x7d010001, + 0xc78, 0x7d020001, + 0xc78, 0x7d030001, + 0xc78, 0x7d040001, + 0xc78, 0x7d050001, + 0xc78, 0x7c060001, + 0xc78, 0x7b070001, + 0xc78, 0x7a080001, + 0xc78, 0x79090001, + 0xc78, 0x780a0001, + 0xc78, 0x770b0001, + 0xc78, 0x760c0001, + 0xc78, 0x750d0001, + 0xc78, 0x740e0001, + 0xc78, 0x730f0001, + 0xc78, 0x72100001, + 0xc78, 0x71110001, + 0xc78, 0x70120001, + 0xc78, 0x6f130001, + 0xc78, 0x6e140001, + 0xc78, 0x6d150001, + 0xc78, 0x6c160001, + 0xc78, 0x6b170001, + 0xc78, 0x6a180001, + 0xc78, 0x69190001, + 0xc78, 0x681a0001, + 0xc78, 0x671b0001, + 0xc78, 0x661c0001, + 0xc78, 0x651d0001, + 0xc78, 0x641e0001, + 0xc78, 0x491f0001, + 0xc78, 0x48200001, + 0xc78, 0x47210001, + 0xc78, 0x46220001, + 0xc78, 0x45230001, + 0xc78, 0x44240001, + 0xc78, 0x43250001, + 0xc78, 0x28260001, + 0xc78, 0x27270001, + 0xc78, 0x26280001, + 0xc78, 0x25290001, + 0xc78, 0x242a0001, + 0xc78, 0x232b0001, + 0xc78, 0x222c0001, + 0xc78, 0x212d0001, + 0xc78, 0x202e0001, + 0xc78, 0x0a2f0001, + 0xc78, 0x08300001, + 0xc78, 0x06310001, + 0xc78, 0x05320001, + 0xc78, 0x04330001, + 0xc78, 0x03340001, + 0xc78, 0x02350001, + 0xc78, 0x01360001, + 0xc78, 0x00370001, + 0xc78, 0x00380001, + 0xc78, 0x00390001, + 0xc78, 0x003a0001, + 0xc78, 0x003b0001, + 0xc78, 0x003c0001, + 0xc78, 0x003d0001, + 0xc78, 0x003e0001, + 0xc78, 0x003f0001, + 0xc78, 0x7d400001, + 0xc78, 0x7d410001, + 0xc78, 0x7d420001, + 0xc78, 0x7d430001, + 0xc78, 0x7d440001, + 0xc78, 0x7d450001, + 0xc78, 0x7c460001, + 0xc78, 0x7b470001, + 0xc78, 0x7a480001, + 0xc78, 0x79490001, + 0xc78, 0x784a0001, + 0xc78, 0x774b0001, + 0xc78, 0x764c0001, + 0xc78, 0x754d0001, + 0xc78, 0x744e0001, + 0xc78, 0x734f0001, + 0xc78, 0x72500001, + 0xc78, 0x71510001, + 0xc78, 0x70520001, + 0xc78, 0x6f530001, + 0xc78, 0x6e540001, + 0xc78, 0x6d550001, + 0xc78, 0x6c560001, + 0xc78, 0x6b570001, + 0xc78, 0x6a580001, + 0xc78, 0x69590001, + 0xc78, 0x685a0001, + 0xc78, 0x675b0001, + 0xc78, 0x665c0001, + 0xc78, 0x655d0001, + 0xc78, 0x645e0001, + 0xc78, 0x495f0001, + 0xc78, 0x48600001, + 0xc78, 0x47610001, + 0xc78, 0x46620001, + 0xc78, 0x45630001, + 0xc78, 0x44640001, + 0xc78, 0x43650001, + 0xc78, 0x28660001, + 0xc78, 0x27670001, + 0xc78, 0x26680001, + 0xc78, 0x25690001, + 0xc78, 0x246a0001, + 0xc78, 0x236b0001, + 0xc78, 0x226c0001, + 0xc78, 0x216d0001, + 0xc78, 0x206e0001, + 0xc78, 0x0a6f0001, + 0xc78, 0x08700001, + 0xc78, 0x06710001, + 0xc78, 0x05720001, + 0xc78, 0x04730001, + 0xc78, 0x03740001, + 0xc78, 0x02750001, + 0xc78, 0x01760001, + 0xc78, 0x00770001, + 0xc78, 0x00780001, + 0xc78, 0x00790001, + 0xc78, 0x007a0001, + 0xc78, 0x007b0001, + 0xc78, 0x007c0001, + 0xc78, 0x007d0001, + 0xc78, 0x007e0001, + 0xc78, 0x007f0001, + 0xc78, 0x2e00001e, + 0xc78, 0x2e01001e, + 0xc78, 0x2e02001e, + 0xc78, 0x2e03001e, + 0xc78, 0x2e04001e, + 0xc78, 0x2e05001e, + 0xc78, 0x3006001e, + 0xc78, 0x3407001e, + 0xc78, 0x3908001e, + 0xc78, 0x3c09001e, + 0xc78, 0x3f0a001e, + 0xc78, 0x420b001e, + 0xc78, 0x440c001e, + 0xc78, 0x450d001e, + 0xc78, 0x460e001e, + 0xc78, 0x460f001e, + 0xc78, 0x4710001e, + 0xc78, 0x4811001e, + 0xc78, 0x4912001e, + 0xc78, 0x4a13001e, + 0xc78, 0x4b14001e, + 0xc78, 0x4b15001e, + 0xc78, 0x4c16001e, + 0xc78, 0x4d17001e, + 0xc78, 0x4e18001e, + 0xc78, 0x4f19001e, + 0xc78, 0x4f1a001e, + 0xc78, 0x501b001e, + 0xc78, 0x511c001e, + 0xc78, 0x521d001e, + 0xc78, 0x521e001e, + 0xc78, 0x531f001e, + 0xc78, 0x5320001e, + 0xc78, 0x5421001e, + 0xc78, 0x5522001e, + 0xc78, 0x5523001e, + 0xc78, 0x5624001e, + 0xc78, 0x5725001e, + 0xc78, 0x5726001e, + 0xc78, 0x5827001e, + 0xc78, 0x5828001e, + 0xc78, 0x5929001e, + 0xc78, 0x592a001e, + 0xc78, 0x5a2b001e, + 0xc78, 0x5b2c001e, + 0xc78, 0x5c2d001e, + 0xc78, 0x5c2e001e, + 0xc78, 0x5d2f001e, + 0xc78, 0x5e30001e, + 0xc78, 0x5f31001e, + 0xc78, 0x6032001e, + 0xc78, 0x6033001e, + 0xc78, 0x6134001e, + 0xc78, 0x6235001e, + 0xc78, 0x6336001e, + 0xc78, 0x6437001e, + 0xc78, 0x6438001e, + 0xc78, 0x6539001e, + 0xc78, 0x663a001e, + 0xc78, 0x673b001e, + 0xc78, 0x673c001e, + 0xc78, 0x683d001e, + 0xc78, 0x693e001e, + 0xc78, 0x6a3f001e, +}; diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_hwimg.h b/drivers/staging/rtl8192e/rtl8192e/r8192E_hwimg.h new file mode 100644 index 000000000000..019836bb36c2 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_hwimg.h @@ -0,0 +1,51 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ +#ifndef __INC_HAL8192PciE_FW_IMG_H +#define __INC_HAL8192PciE_FW_IMG_H + +/*Created on 2008/11/18, 3: 7*/ + +#include <linux/types.h> + +#define BootArrayLengthPciE 344 +extern u8 Rtl8192PciEFwBootArray[BootArrayLengthPciE]; +#define MainArrayLengthPciE 43012 +extern u8 Rtl8192PciEFwMainArray[MainArrayLengthPciE]; +#define DataArrayLengthPciE 848 +extern u8 Rtl8192PciEFwDataArray[DataArrayLengthPciE]; +#define PHY_REGArrayLengthPciE 1 +extern u32 Rtl8192PciEPHY_REGArray[PHY_REGArrayLengthPciE]; +#define PHY_REG_1T2RArrayLengthPciE 296 +extern u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLengthPciE]; +#define RadioA_ArrayLengthPciE 246 +extern u32 Rtl8192PciERadioA_Array[RadioA_ArrayLengthPciE] ; +#define RadioB_ArrayLengthPciE 78 +extern u32 Rtl8192PciERadioB_Array[RadioB_ArrayLengthPciE] ; +#define RadioC_ArrayLengthPciE 2 +extern u32 Rtl8192PciERadioC_Array[RadioC_ArrayLengthPciE] ; +#define RadioD_ArrayLengthPciE 2 +extern u32 Rtl8192PciERadioD_Array[RadioD_ArrayLengthPciE] ; +#define MACPHY_ArrayLengthPciE 18 +extern u32 Rtl8192PciEMACPHY_Array[MACPHY_ArrayLengthPciE] ; +#define MACPHY_Array_PGLengthPciE 30 +extern u32 Rtl8192PciEMACPHY_Array_PG[MACPHY_Array_PGLengthPciE] ; +#define AGCTAB_ArrayLengthPciE 384 +extern u32 Rtl8192PciEAGCTAB_Array[AGCTAB_ArrayLengthPciE] ; + +#endif diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c b/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c new file mode 100644 index 000000000000..4db46a878b61 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c @@ -0,0 +1,1636 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ + +#include "rtl_core.h" +#include "r8192E_hw.h" +#include "r8192E_phyreg.h" +#include "r8190P_rtl8256.h" +#include "r8192E_phy.h" +#include "rtl_dm.h" + +#include "r8192E_hwimg.h" + +static u32 RF_CHANNEL_TABLE_ZEBRA[] = { + 0, + 0x085c, + 0x08dc, + 0x095c, + 0x09dc, + 0x0a5c, + 0x0adc, + 0x0b5c, + 0x0bdc, + 0x0c5c, + 0x0cdc, + 0x0d5c, + 0x0ddc, + 0x0e5c, + 0x0f72, +}; + +/*************************Define local function prototype**********************/ + +static u32 phy_FwRFSerialRead(struct net_device *dev, + enum rf90_radio_path eRFPath, + u32 Offset); +static void phy_FwRFSerialWrite(struct net_device *dev, + enum rf90_radio_path eRFPath, + u32 Offset, u32 Data); + +static u32 rtl8192_CalculateBitShift(u32 dwBitMask) +{ + u32 i; + for (i = 0; i <= 31; i++) { + if (((dwBitMask >> i) & 0x1) == 1) + break; + } + return i; +} + +u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath) +{ + u8 ret = 1; + struct r8192_priv *priv = rtllib_priv(dev); + if (priv->rf_type == RF_2T4R) + ret = 0; + else if (priv->rf_type == RF_1T2R) { + if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) + ret = 1; + else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) + ret = 0; + } + return ret; +} + +void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask, + u32 dwData) +{ + + u32 OriginalValue, BitShift, NewValue; + + if (dwBitMask != bMaskDWord) { + OriginalValue = read_nic_dword(dev, dwRegAddr); + BitShift = rtl8192_CalculateBitShift(dwBitMask); + NewValue = (((OriginalValue) & (~dwBitMask)) | + (dwData << BitShift)); + write_nic_dword(dev, dwRegAddr, NewValue); + } else + write_nic_dword(dev, dwRegAddr, dwData); + return; +} + +u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask) +{ + u32 Ret = 0, OriginalValue, BitShift; + + OriginalValue = read_nic_dword(dev, dwRegAddr); + BitShift = rtl8192_CalculateBitShift(dwBitMask); + Ret = (OriginalValue & dwBitMask) >> BitShift; + + return Ret; +} +static u32 rtl8192_phy_RFSerialRead(struct net_device *dev, + enum rf90_radio_path eRFPath, u32 Offset) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u32 ret = 0; + u32 NewOffset = 0; + struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; + Offset &= 0x3f; + + if (priv->rf_chip == RF_8256) { + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); + if (Offset >= 31) { + priv->RfReg0Value[eRFPath] |= 0x140; + rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath]<<16)); + NewOffset = Offset - 30; + } else if (Offset >= 16) { + priv->RfReg0Value[eRFPath] |= 0x100; + priv->RfReg0Value[eRFPath] &= (~0x40); + rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath]<<16)); + + NewOffset = Offset - 15; + } else + NewOffset = Offset; + } else { + RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need" + " to be 8256\n"); + NewOffset = Offset; + } + rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, + NewOffset); + rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); + rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); + + mdelay(1); + + ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, + bLSSIReadBackData); + + if (priv->rf_chip == RF_8256) { + priv->RfReg0Value[eRFPath] &= 0xebf; + + rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, + (priv->RfReg0Value[eRFPath] << 16)); + + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); + } + + + return ret; + +} + +static void rtl8192_phy_RFSerialWrite(struct net_device *dev, + enum rf90_radio_path eRFPath, u32 Offset, + u32 Data) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u32 DataAndAddr = 0, NewOffset = 0; + struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; + + Offset &= 0x3f; + if (priv->rf_chip == RF_8256) { + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); + + if (Offset >= 31) { + priv->RfReg0Value[eRFPath] |= 0x140; + rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath] << 16)); + NewOffset = Offset - 30; + } else if (Offset >= 16) { + priv->RfReg0Value[eRFPath] |= 0x100; + priv->RfReg0Value[eRFPath] &= (~0x40); + rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath] << 16)); + NewOffset = Offset - 15; + } else + NewOffset = Offset; + } else { + RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be" + " 8256\n"); + NewOffset = Offset; + } + + DataAndAddr = (Data<<16) | (NewOffset&0x3f); + + rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); + + if (Offset == 0x0) + priv->RfReg0Value[eRFPath] = Data; + + if (priv->rf_chip == RF_8256) { + if (Offset != 0) { + priv->RfReg0Value[eRFPath] &= 0xebf; + rtl8192_setBBreg( + dev, + pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath] << 16)); + } + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); + } + return; +} + +void rtl8192_phy_SetRFReg(struct net_device *dev, enum rf90_radio_path eRFPath, + u32 RegAddr, u32 BitMask, u32 Data) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u32 Original_Value, BitShift, New_Value; + + if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) + return; + if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter) + return; + + RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n"); + if (priv->Rf_Mode == RF_OP_By_FW) { + if (BitMask != bMask12Bits) { + Original_Value = phy_FwRFSerialRead(dev, eRFPath, + RegAddr); + BitShift = rtl8192_CalculateBitShift(BitMask); + New_Value = (((Original_Value) & (~BitMask)) | + (Data << BitShift)); + + phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value); + } else + phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data); + udelay(200); + + } else { + if (BitMask != bMask12Bits) { + Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, + RegAddr); + BitShift = rtl8192_CalculateBitShift(BitMask); + New_Value = (((Original_Value) & (~BitMask)) | + (Data << BitShift)); + + rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, + New_Value); + } else + rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data); + } + return; +} + +u32 rtl8192_phy_QueryRFReg(struct net_device *dev, enum rf90_radio_path eRFPath, + u32 RegAddr, u32 BitMask) +{ + u32 Original_Value, Readback_Value, BitShift; + struct r8192_priv *priv = rtllib_priv(dev); + if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) + return 0; + if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter) + return 0; + down(&priv->rf_sem); + if (priv->Rf_Mode == RF_OP_By_FW) { + Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); + udelay(200); + } else { + Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, + RegAddr); + } + BitShift = rtl8192_CalculateBitShift(BitMask); + Readback_Value = (Original_Value & BitMask) >> BitShift; + up(&priv->rf_sem); + return Readback_Value; +} + +static u32 phy_FwRFSerialRead(struct net_device *dev, + enum rf90_radio_path eRFPath, u32 Offset) +{ + u32 retValue = 0; + u32 Data = 0; + u8 time = 0; + Data |= ((Offset & 0xFF) << 12); + Data |= ((eRFPath & 0x3) << 20); + Data |= 0x80000000; + while (read_nic_dword(dev, QPNR)&0x80000000) { + if (time++ < 100) + udelay(10); + else + break; + } + write_nic_dword(dev, QPNR, Data); + while (read_nic_dword(dev, QPNR) & 0x80000000) { + if (time++ < 100) + udelay(10); + else + return 0; + } + retValue = read_nic_dword(dev, RF_DATA); + + return retValue; + +} /* phy_FwRFSerialRead */ + +static void phy_FwRFSerialWrite(struct net_device *dev, + enum rf90_radio_path eRFPath, + u32 Offset, u32 Data) +{ + u8 time = 0; + + Data |= ((Offset & 0xFF) << 12); + Data |= ((eRFPath & 0x3) << 20); + Data |= 0x400000; + Data |= 0x80000000; + + while (read_nic_dword(dev, QPNR) & 0x80000000) { + if (time++ < 100) + udelay(10); + else + break; + } + write_nic_dword(dev, QPNR, Data); + +} /* phy_FwRFSerialWrite */ + + +void rtl8192_phy_configmac(struct net_device *dev) +{ + u32 dwArrayLen = 0, i = 0; + u32 *pdwArray = NULL; + struct r8192_priv *priv = rtllib_priv(dev); + + if (priv->bTXPowerDataReadFromEEPORM) { + RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n"); + dwArrayLen = MACPHY_Array_PGLength; + pdwArray = Rtl819XMACPHY_Array_PG; + + } else { + RT_TRACE(COMP_PHY, "Read rtl819XMACPHY_Array\n"); + dwArrayLen = MACPHY_ArrayLength; + pdwArray = Rtl819XMACPHY_Array; + } + for (i = 0; i < dwArrayLen; i += 3) { + RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MAC" + "PHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n", + pdwArray[i], pdwArray[i+1], pdwArray[i+2]); + if (pdwArray[i] == 0x318) + pdwArray[i+2] = 0x00000800; + rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], + pdwArray[i+2]); + } + return; + +} + +void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType) +{ + int i; + u32 *Rtl819XPHY_REGArray_Table = NULL; + u32 *Rtl819XAGCTAB_Array_Table = NULL; + u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0; + struct r8192_priv *priv = rtllib_priv(dev); + + AGCTAB_ArrayLen = AGCTAB_ArrayLength; + Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array; + if (priv->rf_type == RF_2T4R) { + PHY_REGArrayLen = PHY_REGArrayLength; + Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray; + } else if (priv->rf_type == RF_1T2R) { + PHY_REGArrayLen = PHY_REG_1T2RArrayLength; + Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray; + } + + if (ConfigType == BaseBand_Config_PHY_REG) { + for (i = 0; i < PHY_REGArrayLen; i += 2) { + rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], + bMaskDWord, + Rtl819XPHY_REGArray_Table[i+1]); + RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray" + "[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n", + i, Rtl819XPHY_REGArray_Table[i], + Rtl819XPHY_REGArray_Table[i+1]); + } + } else if (ConfigType == BaseBand_Config_AGC_TAB) { + for (i = 0; i < AGCTAB_ArrayLen; i += 2) { + rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], + bMaskDWord, + Rtl819XAGCTAB_Array_Table[i+1]); + RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] " + "is %x rtl819XAGCTAB_Array[1] is %x\n", i, + Rtl819XAGCTAB_Array_Table[i], + Rtl819XAGCTAB_Array_Table[i+1]); + } + } + return; +} + +static void rtl8192_InitBBRFRegDef(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; + priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; + priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; + priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; + + priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; + priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; + priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; + priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; + + priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; + priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; + priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE; + priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE; + + priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; + priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; + priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE; + priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE; + + priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; + priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; + priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; + priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; + + priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; + priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; + priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; + priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; + + priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; + priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; + priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; + priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; + + priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; + priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; + priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; + priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; + + priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; + priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; + priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; + priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; + + priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; + priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; + priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; + priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; + + priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; + priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; + priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; + priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; + + priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; + priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; + priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; + priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; + + priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; + priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; + priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; + priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; + + priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; + priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; + priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; + priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; + + priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; + priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; + priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; + priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; + + priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; + priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; + priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; + priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; + + priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; + priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; + priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; + priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; + +} + +bool rtl8192_phy_checkBBAndRF(struct net_device *dev, + enum hw90_block CheckBlock, + enum rf90_radio_path eRFPath) +{ + bool ret = true; + u32 i, CheckTimes = 4, dwRegRead = 0; + u32 WriteAddr[4]; + u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; + + WriteAddr[HW90_BLOCK_MAC] = 0x100; + WriteAddr[HW90_BLOCK_PHY0] = 0x900; + WriteAddr[HW90_BLOCK_PHY1] = 0x800; + WriteAddr[HW90_BLOCK_RF] = 0x3; + RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__, + CheckBlock); + for (i = 0; i < CheckTimes; i++) { + switch (CheckBlock) { + case HW90_BLOCK_MAC: + RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write " + "0x100 here!"); + break; + + case HW90_BLOCK_PHY0: + case HW90_BLOCK_PHY1: + write_nic_dword(dev, WriteAddr[CheckBlock], + WriteData[i]); + dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]); + break; + + case HW90_BLOCK_RF: + WriteData[i] &= 0xfff; + rtl8192_phy_SetRFReg(dev, eRFPath, + WriteAddr[HW90_BLOCK_RF], + bMask12Bits, WriteData[i]); + mdelay(10); + dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, + WriteAddr[HW90_BLOCK_RF], + bMaskDWord); + mdelay(10); + break; + + default: + ret = false; + break; + } + + + if (dwRegRead != WriteData[i]) { + RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, " + "WriteData: %x\n", dwRegRead, WriteData[i]); + ret = false; + break; + } + } + + return ret; +} + +static bool rtl8192_BB_Config_ParaFile(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + bool rtStatus = true; + u8 bRegValue = 0, eCheckItem = 0; + u32 dwRegValue = 0; + + bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET); + write_nic_byte(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT)); + + dwRegValue = read_nic_dword(dev, CPU_GEN); + write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); + + for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0; + eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) { + rtStatus = rtl8192_phy_checkBBAndRF(dev, + (enum hw90_block)eCheckItem, + (enum rf90_radio_path)0); + if (rtStatus != true) { + RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():" + "Check PHY%d Fail!!\n", eCheckItem-1); + return rtStatus; + } + } + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); + rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG); + + dwRegValue = read_nic_dword(dev, CPU_GEN); + write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); + + rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB); + + if (priv->IC_Cut > VERSION_8190_BD) { + if (priv->rf_type == RF_2T4R) + dwRegValue = (priv->AntennaTxPwDiff[2]<<8 | + priv->AntennaTxPwDiff[1]<<4 | + priv->AntennaTxPwDiff[0]); + else + dwRegValue = 0x0; + rtl8192_setBBreg(dev, rFPGA0_TxGainStage, + (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue); + + + dwRegValue = priv->CrystalCap; + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, + dwRegValue); + } + + return rtStatus; +} +bool rtl8192_BBConfig(struct net_device *dev) +{ + bool rtStatus = true; + + rtl8192_InitBBRFRegDef(dev); + rtStatus = rtl8192_BB_Config_ParaFile(dev); + return rtStatus; +} + +void rtl8192_phy_getTxPower(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + priv->MCSTxPowerLevelOriginalOffset[0] = + read_nic_dword(dev, rTxAGC_Rate18_06); + priv->MCSTxPowerLevelOriginalOffset[1] = + read_nic_dword(dev, rTxAGC_Rate54_24); + priv->MCSTxPowerLevelOriginalOffset[2] = + read_nic_dword(dev, rTxAGC_Mcs03_Mcs00); + priv->MCSTxPowerLevelOriginalOffset[3] = + read_nic_dword(dev, rTxAGC_Mcs07_Mcs04); + priv->MCSTxPowerLevelOriginalOffset[4] = + read_nic_dword(dev, rTxAGC_Mcs11_Mcs08); + priv->MCSTxPowerLevelOriginalOffset[5] = + read_nic_dword(dev, rTxAGC_Mcs15_Mcs12); + + priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1); + priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1); + priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1); + priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1); + RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, " + "c60=0x%x, c68=0x%x)\n", + priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], + priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); + + priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3); + priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2); + RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n", + rOFDM0_RxDetector3, priv->framesync); + priv->SifsTime = read_nic_word(dev, SIFS); + return; +} + +void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u8 powerlevel = 0, powerlevelOFDM24G = 0; + char ant_pwr_diff; + u32 u4RegValue; + + if (priv->epromtype == EEPROM_93C46) { + powerlevel = priv->TxPowerLevelCCK[channel-1]; + powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; + } else if (priv->epromtype == EEPROM_93C56) { + if (priv->rf_type == RF_1T2R) { + powerlevel = priv->TxPowerLevelCCK_C[channel-1]; + powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1]; + } else if (priv->rf_type == RF_2T4R) { + powerlevel = priv->TxPowerLevelCCK_A[channel-1]; + powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1]; + + ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1] + - priv->TxPowerLevelOFDM24G_A[channel-1]; + + priv->RF_C_TxPwDiff = ant_pwr_diff; + + ant_pwr_diff &= 0xf; + + priv->AntennaTxPwDiff[2] = 0; + priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff); + priv->AntennaTxPwDiff[0] = 0; + + u4RegValue = (priv->AntennaTxPwDiff[2]<<8 | + priv->AntennaTxPwDiff[1]<<4 | + priv->AntennaTxPwDiff[0]); + + rtl8192_setBBreg(dev, rFPGA0_TxGainStage, + (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue); + } + } + switch (priv->rf_chip) { + case RF_8225: + break; + case RF_8256: + PHY_SetRF8256CCKTxPower(dev, powerlevel); + PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); + break; + case RF_8258: + break; + default: + RT_TRACE(COMP_ERR, "unknown rf chip in funtion %s()\n", + __func__); + break; + } + return; +} + +bool rtl8192_phy_RFConfig(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + bool rtStatus = true; + switch (priv->rf_chip) { + case RF_8225: + break; + case RF_8256: + rtStatus = PHY_RF8256_Config(dev); + break; + + case RF_8258: + break; + case RF_PSEUDO_11N: + break; + + default: + RT_TRACE(COMP_ERR, "error chip id\n"); + break; + } + return rtStatus; +} + +void rtl8192_phy_updateInitGain(struct net_device *dev) +{ + return; +} + +u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, + enum rf90_radio_path eRFPath) +{ + + int i; + u8 ret = 0; + + switch (eRFPath) { + case RF90_PATH_A: + for (i = 0; i < RadioA_ArrayLength; i += 2) { + if (Rtl819XRadioA_Array[i] == 0xfe) { + msleep(100); + continue; + } + rtl8192_phy_SetRFReg(dev, eRFPath, + Rtl819XRadioA_Array[i], + bMask12Bits, + Rtl819XRadioA_Array[i+1]); + + } + break; + case RF90_PATH_B: + for (i = 0; i < RadioB_ArrayLength; i += 2) { + if (Rtl819XRadioB_Array[i] == 0xfe) { + msleep(100); + continue; + } + rtl8192_phy_SetRFReg(dev, eRFPath, + Rtl819XRadioB_Array[i], + bMask12Bits, + Rtl819XRadioB_Array[i+1]); + + } + break; + case RF90_PATH_C: + for (i = 0; i < RadioC_ArrayLength; i += 2) { + if (Rtl819XRadioC_Array[i] == 0xfe) { + msleep(100); + continue; + } + rtl8192_phy_SetRFReg(dev, eRFPath, + Rtl819XRadioC_Array[i], + bMask12Bits, + Rtl819XRadioC_Array[i+1]); + + } + break; + case RF90_PATH_D: + for (i = 0; i < RadioD_ArrayLength; i += 2) { + if (Rtl819XRadioD_Array[i] == 0xfe) { + msleep(100); + continue; + } + rtl8192_phy_SetRFReg(dev, eRFPath, + Rtl819XRadioD_Array[i], bMask12Bits, + Rtl819XRadioD_Array[i+1]); + + } + break; + default: + break; + } + + return ret; + +} +static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; + u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; + + switch (priv->rf_chip) { + case RF_8225: + break; + + case RF_8256: + PHY_SetRF8256CCKTxPower(dev, powerlevel); + PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); + break; + + case RF_8258: + break; + default: + RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPower" + "Level()\n"); + break; + } + return; +} + +static u8 rtl8192_phy_SetSwChnlCmdArray(struct sw_chnl_cmd *CmdTable, + u32 CmdTableIdx, u32 CmdTableSz, + enum sw_chnl_cmd_id CmdID, + u32 Para1, u32 Para2, u32 msDelay) +{ + struct sw_chnl_cmd *pCmd; + + if (CmdTable == NULL) { + RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot " + "be NULL.\n"); + return false; + } + if (CmdTableIdx >= CmdTableSz) { + RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid" + " index, please check size of the table, CmdTableIdx:" + "%d, CmdTableSz:%d\n", + CmdTableIdx, CmdTableSz); + return false; + } + + pCmd = CmdTable + CmdTableIdx; + pCmd->CmdID = CmdID; + pCmd->Para1 = Para1; + pCmd->Para2 = Para2; + pCmd->msDelay = msDelay; + + return true; +} + +static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, + u8 *stage, u8 *step, u32 *delay) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + u32 PreCommonCmdCnt; + u32 PostCommonCmdCnt; + u32 RfDependCmdCnt; + struct sw_chnl_cmd *CurrentCmd = NULL; + u8 eRFPath; + + RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", + __func__, *stage, *step, channel); + + if (!IsLegalChannel(priv->rtllib, channel)) { + RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", + channel); + return true; + } + + { + PreCommonCmdCnt = 0; + rtl8192_phy_SetSwChnlCmdArray(ieee->PreCommonCmd, + PreCommonCmdCnt++, + MAX_PRECMD_CNT, CmdID_SetTxPowerLevel, + 0, 0, 0); + rtl8192_phy_SetSwChnlCmdArray(ieee->PreCommonCmd, + PreCommonCmdCnt++, + MAX_PRECMD_CNT, CmdID_End, 0, 0, 0); + + PostCommonCmdCnt = 0; + + rtl8192_phy_SetSwChnlCmdArray(ieee->PostCommonCmd, + PostCommonCmdCnt++, + MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0); + + RfDependCmdCnt = 0; + switch (priv->rf_chip) { + case RF_8225: + if (!(channel >= 1 && channel <= 14)) { + RT_TRACE(COMP_ERR, "illegal channel for Zebra " + "8225: %d\n", channel); + return false; + } + rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd, + RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, + CmdID_RF_WriteReg, rZebra1_Channel, + RF_CHANNEL_TABLE_ZEBRA[channel], 10); + rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd, + RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, + CmdID_End, 0, 0, 0); + break; + + case RF_8256: + if (!(channel >= 1 && channel <= 14)) { + RT_TRACE(COMP_ERR, "illegal channel for Zebra" + " 8256: %d\n", channel); + return false; + } + rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd, + RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, + CmdID_RF_WriteReg, rZebra1_Channel, channel, + 10); + rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd, + + RfDependCmdCnt++, + MAX_RFDEPENDCMD_CNT, + CmdID_End, 0, 0, 0); + break; + + case RF_8258: + break; + + default: + RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", + priv->rf_chip); + return false; + break; + } + + + do { + switch (*stage) { + case 0: + CurrentCmd = &ieee->PreCommonCmd[*step]; + break; + case 1: + CurrentCmd = &ieee->RfDependCmd[*step]; + break; + case 2: + CurrentCmd = &ieee->PostCommonCmd[*step]; + break; + } + + if (CurrentCmd && CurrentCmd->CmdID == CmdID_End) { + if ((*stage) == 2) { + return true; + } else { + (*stage)++; + (*step) = 0; + continue; + } + } + + if (!CurrentCmd) + continue; + switch (CurrentCmd->CmdID) { + case CmdID_SetTxPowerLevel: + if (priv->IC_Cut > (u8)VERSION_8190_BD) + rtl8192_SetTxPowerLevel(dev, channel); + break; + case CmdID_WritePortUlong: + write_nic_dword(dev, CurrentCmd->Para1, + CurrentCmd->Para2); + break; + case CmdID_WritePortUshort: + write_nic_word(dev, CurrentCmd->Para1, + (u16)CurrentCmd->Para2); + break; + case CmdID_WritePortUchar: + write_nic_byte(dev, CurrentCmd->Para1, + (u8)CurrentCmd->Para2); + break; + case CmdID_RF_WriteReg: + for (eRFPath = 0; eRFPath < + priv->NumTotalRFPath; eRFPath++) + rtl8192_phy_SetRFReg(dev, + (enum rf90_radio_path)eRFPath, + CurrentCmd->Para1, bMask12Bits, + CurrentCmd->Para2<<7); + break; + default: + break; + } + + break; + } while (true); + } /*for (Number of RF paths)*/ + + (*delay) = CurrentCmd->msDelay; + (*step)++; + return false; +} + +static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u32 delay = 0; + + while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage, + &priv->SwChnlStep, &delay)) { + if (delay > 0) + msleep(delay); + if (IS_NIC_DOWN(priv)) + break; + } +} +void rtl8192_SwChnl_WorkItem(struct net_device *dev) +{ + + struct r8192_priv *priv = rtllib_priv(dev); + + RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n"); + + RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__, + priv->chan, priv); + + rtl8192_phy_FinishSwChnlNow(dev , priv->chan); + + RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n"); +} + +u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel) +{ + struct r8192_priv *priv = rtllib_priv(dev); + RT_TRACE(COMP_PHY, "=====>%s()\n", __func__); + if (IS_NIC_DOWN(priv)) { + RT_TRACE(COMP_ERR, "%s(): ERR !! driver is not up\n", __func__); + return false; + } + if (priv->SwChnlInProgress) + return false; + + + switch (priv->rtllib->mode) { + case WIRELESS_MODE_A: + case WIRELESS_MODE_N_5G: + if (channel <= 14) { + RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14"); + return false; + } + break; + case WIRELESS_MODE_B: + if (channel > 14) { + RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14"); + return false; + } + break; + case WIRELESS_MODE_G: + case WIRELESS_MODE_N_24G: + if (channel > 14) { + RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14"); + return false; + } + break; + } + + priv->SwChnlInProgress = true; + if (channel == 0) + channel = 1; + + priv->chan = channel; + + priv->SwChnlStage = 0; + priv->SwChnlStep = 0; + + if (!IS_NIC_DOWN(priv)) + rtl8192_SwChnl_WorkItem(dev); + priv->SwChnlInProgress = false; + return true; +} + +static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + switch (priv->CurrentChannelBW) { + case HT_CHANNEL_WIDTH_20: + priv->CCKPresentAttentuation = + priv->CCKPresentAttentuation_20Mdefault + + priv->CCKPresentAttentuation_difference; + + if (priv->CCKPresentAttentuation > + (CCKTxBBGainTableLength-1)) + priv->CCKPresentAttentuation = + CCKTxBBGainTableLength-1; + if (priv->CCKPresentAttentuation < 0) + priv->CCKPresentAttentuation = 0; + + RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresent" + "Attentuation = %d\n", + priv->CCKPresentAttentuation); + + if (priv->rtllib->current_network.channel == 14 && + !priv->bcck_in_ch14) { + priv->bcck_in_ch14 = true; + dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + } else if (priv->rtllib->current_network.channel != + 14 && priv->bcck_in_ch14) { + priv->bcck_in_ch14 = false; + dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + } else { + dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + } + break; + + case HT_CHANNEL_WIDTH_20_40: + priv->CCKPresentAttentuation = + priv->CCKPresentAttentuation_40Mdefault + + priv->CCKPresentAttentuation_difference; + + RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresent" + "Attentuation = %d\n", + priv->CCKPresentAttentuation); + if (priv->CCKPresentAttentuation > + (CCKTxBBGainTableLength - 1)) + priv->CCKPresentAttentuation = + CCKTxBBGainTableLength-1; + if (priv->CCKPresentAttentuation < 0) + priv->CCKPresentAttentuation = 0; + + if (priv->rtllib->current_network.channel == 14 && + !priv->bcck_in_ch14) { + priv->bcck_in_ch14 = true; + dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + } else if (priv->rtllib->current_network.channel != 14 + && priv->bcck_in_ch14) { + priv->bcck_in_ch14 = false; + dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + } else { + dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + } + break; + } +} + +static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + if (priv->rtllib->current_network.channel == 14 && + !priv->bcck_in_ch14) + priv->bcck_in_ch14 = true; + else if (priv->rtllib->current_network.channel != 14 && + priv->bcck_in_ch14) + priv->bcck_in_ch14 = false; + + switch (priv->CurrentChannelBW) { + case HT_CHANNEL_WIDTH_20: + if (priv->Record_CCK_20Mindex == 0) + priv->Record_CCK_20Mindex = 6; + priv->CCK_index = priv->Record_CCK_20Mindex; + RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_" + "Switch_ThermalMeter(),CCK_index = %d\n", + priv->CCK_index); + break; + + case HT_CHANNEL_WIDTH_20_40: + priv->CCK_index = priv->Record_CCK_40Mindex; + RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_" + "Switch_ThermalMeter(), CCK_index = %d\n", + priv->CCK_index); + break; + } + dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); +} + +static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + if (priv->IC_Cut >= IC_VersionCut_D) + CCK_Tx_Power_Track_BW_Switch_TSSI(dev); + else + CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev); +} + +void rtl8192_SetBWModeWorkItem(struct net_device *dev) +{ + + struct r8192_priv *priv = rtllib_priv(dev); + u8 regBwOpMode; + + RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s " + "bandwidth\n", priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ? + "20MHz" : "40MHz") + + + if (priv->rf_chip == RF_PSEUDO_11N) { + priv->SetBWModeInProgress = false; + return; + } + if (IS_NIC_DOWN(priv)) { + RT_TRACE(COMP_ERR, "%s(): ERR!! driver is not up\n", __func__); + return; + } + regBwOpMode = read_nic_byte(dev, BW_OPMODE); + + switch (priv->CurrentChannelBW) { + case HT_CHANNEL_WIDTH_20: + regBwOpMode |= BW_OPMODE_20MHZ; + write_nic_byte(dev, BW_OPMODE, regBwOpMode); + break; + + case HT_CHANNEL_WIDTH_20_40: + regBwOpMode &= ~BW_OPMODE_20MHZ; + write_nic_byte(dev, BW_OPMODE, regBwOpMode); + break; + + default: + RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown " + "Bandwidth: %#X\n", priv->CurrentChannelBW); + break; + } + + switch (priv->CurrentChannelBW) { + case HT_CHANNEL_WIDTH_20: + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); + rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); + + if (!priv->btxpower_tracking) { + write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000); + write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317); + write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); + } else { + CCK_Tx_Power_Track_BW_Switch(dev); + } + + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); + + break; + case HT_CHANNEL_WIDTH_20_40: + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); + rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); + + if (!priv->btxpower_tracking) { + write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000); + write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e); + write_nic_dword(dev, rCCK0_DebugPort, 0x00000409); + } else { + CCK_Tx_Power_Track_BW_Switch(dev); + } + + rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, + (priv->nCur40MhzPrimeSC>>1)); + rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, + priv->nCur40MhzPrimeSC); + + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); + break; + default: + RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown " + "Bandwidth: %#X\n", priv->CurrentChannelBW); + break; + + } + + switch (priv->rf_chip) { + case RF_8225: + break; + + case RF_8256: + PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); + break; + + case RF_8258: + break; + + case RF_PSEUDO_11N: + break; + + default: + RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); + break; + } + + atomic_dec(&(priv->rtllib->atm_swbw)); + priv->SetBWModeInProgress = false; + + RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()"); +} + +void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth, + enum ht_extchnl_offset Offset) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + + if (priv->SetBWModeInProgress) + return; + + atomic_inc(&(priv->rtllib->atm_swbw)); + priv->SetBWModeInProgress = true; + + priv->CurrentChannelBW = Bandwidth; + + if (Offset == HT_EXTCHNL_OFFSET_LOWER) + priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; + else if (Offset == HT_EXTCHNL_OFFSET_UPPER) + priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; + else + priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + + rtl8192_SetBWModeWorkItem(dev); + +} + +void InitialGain819xPci(struct net_device *dev, u8 Operation) +{ +#define SCAN_RX_INITIAL_GAIN 0x17 +#define POWER_DETECTION_TH 0x08 + struct r8192_priv *priv = rtllib_priv(dev); + u32 BitMask; + u8 initial_gain; + + if (!IS_NIC_DOWN(priv)) { + switch (Operation) { + case IG_Backup: + RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial" + " gain.\n"); + initial_gain = SCAN_RX_INITIAL_GAIN; + BitMask = bMaskByte0; + if (dm_digtable.dig_algorithm == + DIG_ALGO_BY_FALSE_ALARM) + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); + priv->initgain_backup.xaagccore1 = + (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, + BitMask); + priv->initgain_backup.xbagccore1 = + (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, + BitMask); + priv->initgain_backup.xcagccore1 = + (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, + BitMask); + priv->initgain_backup.xdagccore1 = + (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, + BitMask); + BitMask = bMaskByte2; + priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, + rCCK0_CCA, BitMask); + + RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is" + " %x\n", priv->initgain_backup.xaagccore1); + RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is" + " %x\n", priv->initgain_backup.xbagccore1); + RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is" + " %x\n", priv->initgain_backup.xcagccore1); + RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is" + " %x\n", priv->initgain_backup.xdagccore1); + RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is" + " %x\n", priv->initgain_backup.cca); + + RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n", + initial_gain); + write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); + write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); + write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); + write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); + RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n", + POWER_DETECTION_TH); + write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); + break; + case IG_Restore: + RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial " + "gain.\n"); + BitMask = 0x7f; + if (dm_digtable.dig_algorithm == + DIG_ALGO_BY_FALSE_ALARM) + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); + + rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, + (u32)priv->initgain_backup.xaagccore1); + rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, + (u32)priv->initgain_backup.xbagccore1); + rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, + (u32)priv->initgain_backup.xcagccore1); + rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, + (u32)priv->initgain_backup.xdagccore1); + BitMask = bMaskByte2; + rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, + (u32)priv->initgain_backup.cca); + + RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50" + " is %x\n", priv->initgain_backup.xaagccore1); + RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58" + " is %x\n", priv->initgain_backup.xbagccore1); + RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60" + " is %x\n", priv->initgain_backup.xcagccore1); + RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68" + " is %x\n", priv->initgain_backup.xdagccore1); + RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a" + " is %x\n", priv->initgain_backup.cca); + + rtl8192_phy_setTxPower(dev, + priv->rtllib->current_network.channel); + + if (dm_digtable.dig_algorithm == + DIG_ALGO_BY_FALSE_ALARM) + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); + break; + default: + RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n"); + break; + } + } +} + +void PHY_SetRtl8192eRfOff(struct net_device *dev) +{ + + rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0); + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); + rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); + rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0); + write_nic_byte(dev, ANAPAR_FOR_8192PciE, 0x07); + +} + +static bool SetRFPowerState8190(struct net_device *dev, + enum rt_rf_power_state eRFPowerState) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *) + (&(priv->rtllib->PowerSaveControl)); + bool bResult = true; + u8 i = 0, QueueID = 0; + struct rtl8192_tx_ring *ring = NULL; + + if (priv->SetRFPowerStateInProgress == true) + return false; + RT_TRACE(COMP_PS, "===========> SetRFPowerState8190()!\n"); + priv->SetRFPowerStateInProgress = true; + + switch (priv->rf_chip) { + case RF_8256: + switch (eRFPowerState) { + case eRfOn: + RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn!\n"); + if ((priv->rtllib->eRFPowerState == eRfOff) && + RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) { + bool rtstatus = true; + u32 InitilizeCount = 3; + do { + InitilizeCount--; + priv->RegRfOff = false; + rtstatus = NicIFEnableNIC(dev); + } while ((rtstatus != true) && + (InitilizeCount > 0)); + + if (rtstatus != true) { + RT_TRACE(COMP_ERR, "%s():Initialize Ada" + "pter fail,return\n", + __func__); + priv->SetRFPowerStateInProgress = false; + return false; + } + + RT_CLEAR_PS_LEVEL(pPSC, + RT_RF_OFF_LEVL_HALT_NIC); + } else { + write_nic_byte(dev, ANAPAR, 0x37); + mdelay(1); + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, + 0x4, 0x1); + priv->bHwRfOffAction = 0; + + rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, + BIT4, 0x1); + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, + 0x300, 0x3); + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, + 0x18, 0x3); + rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, + 0x3); + rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, + 0x3); + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, + 0x60, 0x3); + + } + + break; + + case eRfSleep: + if (priv->rtllib->eRFPowerState == eRfOff) + break; + + + for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { + ring = &priv->tx_ring[QueueID]; + + if (skb_queue_len(&ring->queue) == 0) { + QueueID++; + continue; + } else { + RT_TRACE((COMP_POWER|COMP_RF), "eRf Off" + "/Sleep: %d times TcbBusyQueue" + "[%d] !=0 before doze!\n", + (i+1), QueueID); + udelay(10); + i++; + } + + if (i >= MAX_DOZE_WAITING_TIMES_9x) { + RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! " + "SetRFPowerState8190(): eRfOff" + ": %d times TcbBusyQueue[%d] " + "!= 0 !!!\n", + MAX_DOZE_WAITING_TIMES_9x, + QueueID); + break; + } + } + PHY_SetRtl8192eRfOff(dev); + break; + + case eRfOff: + RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOff/" + "Sleep !\n"); + + for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { + ring = &priv->tx_ring[QueueID]; + + if (skb_queue_len(&ring->queue) == 0) { + QueueID++; + continue; + } else { + RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d" + " times TcbBusyQueue[%d] !=0 b" + "efore doze!\n", (i+1), + QueueID); + udelay(10); + i++; + } + + if (i >= MAX_DOZE_WAITING_TIMES_9x) { + RT_TRACE(COMP_POWER, "\n\n\n SetZebra: " + "RFPowerState8185B(): eRfOff:" + " %d times TcbBusyQueue[%d] " + "!= 0 !!!\n", + MAX_DOZE_WAITING_TIMES_9x, + QueueID); + break; + } + } + + if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && + !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) { + NicIFDisableNIC(dev); + RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); + } else if (!(pPSC->RegRfPsLevel & + RT_RF_OFF_LEVL_HALT_NIC)) { + PHY_SetRtl8192eRfOff(dev); + } + + break; + + default: + bResult = false; + RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state" + " to set: 0x%X!!!\n", eRFPowerState); + break; + } + + break; + + default: + RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n"); + break; + } + + if (bResult) { + priv->rtllib->eRFPowerState = eRFPowerState; + + switch (priv->rf_chip) { + case RF_8256: + break; + + default: + RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown " + "RF type\n"); + break; + } + } + + priv->SetRFPowerStateInProgress = false; + RT_TRACE(COMP_PS, "<=========== SetRFPowerState8190() bResult = %d!\n", + bResult); + return bResult; +} + +bool SetRFPowerState(struct net_device *dev, + enum rt_rf_power_state eRFPowerState) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + bool bResult = false; + + RT_TRACE(COMP_PS, "---------> SetRFPowerState(): eRFPowerState(%d)\n", + eRFPowerState); + if (eRFPowerState == priv->rtllib->eRFPowerState && + priv->bHwRfOffAction == 0) { + RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): discard the " + "request for eRFPowerState(%d) is the same.\n", + eRFPowerState); + return bResult; + } + + bResult = SetRFPowerState8190(dev, eRFPowerState); + + RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): bResult(%d)\n", + bResult); + + return bResult; +} + +void PHY_ScanOperationBackup8192(struct net_device *dev, u8 Operation) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + if (priv->up) { + switch (Operation) { + case SCAN_OPT_BACKUP: + priv->rtllib->InitialGainHandler(dev, IG_Backup); + break; + + case SCAN_OPT_RESTORE: + priv->rtllib->InitialGainHandler(dev, IG_Restore); + break; + + default: + RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation.\n"); + break; + } + } + +} diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.h b/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.h new file mode 100644 index 000000000000..7318f8857af2 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.h @@ -0,0 +1,120 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ +#ifndef _R819XU_PHY_H +#define _R819XU_PHY_H + +#define MAX_DOZE_WAITING_TIMES_9x 64 + +#define AGCTAB_ArrayLength AGCTAB_ArrayLengthPciE +#define MACPHY_ArrayLength MACPHY_ArrayLengthPciE +#define RadioA_ArrayLength RadioA_ArrayLengthPciE +#define RadioB_ArrayLength RadioB_ArrayLengthPciE +#define MACPHY_Array_PGLength MACPHY_Array_PGLengthPciE +#define RadioC_ArrayLength RadioC_ArrayLengthPciE +#define RadioD_ArrayLength RadioD_ArrayLengthPciE +#define PHY_REGArrayLength PHY_REGArrayLengthPciE +#define PHY_REG_1T2RArrayLength PHY_REG_1T2RArrayLengthPciE + +#define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG +#define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array +#define Rtl819XRadioA_Array Rtl8192PciERadioA_Array +#define Rtl819XRadioB_Array Rtl8192PciERadioB_Array +#define Rtl819XRadioC_Array Rtl8192PciERadioC_Array +#define Rtl819XRadioD_Array Rtl8192PciERadioD_Array +#define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array +#define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray +#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray + +extern u32 rtl819XMACPHY_Array_PG[]; +extern u32 rtl819XPHY_REG_1T2RArray[]; +extern u32 rtl819XAGCTAB_Array[]; +extern u32 rtl819XRadioA_Array[]; +extern u32 rtl819XRadioB_Array[]; +extern u32 rtl819XRadioC_Array[]; +extern u32 rtl819XRadioD_Array[]; + +enum hw90_block { + HW90_BLOCK_MAC = 0, + HW90_BLOCK_PHY0 = 1, + HW90_BLOCK_PHY1 = 2, + HW90_BLOCK_RF = 3, + HW90_BLOCK_MAXIMUM = 4, +}; + +enum rf90_radio_path { + RF90_PATH_A = 0, + RF90_PATH_B = 1, + RF90_PATH_C = 2, + RF90_PATH_D = 3, + RF90_PATH_MAX +}; + +#define bMaskByte0 0xff +#define bMaskByte1 0xff00 +#define bMaskByte2 0xff0000 +#define bMaskByte3 0xff000000 +#define bMaskHWord 0xffff0000 +#define bMaskLWord 0x0000ffff +#define bMaskDWord 0xffffffff + +extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, + u32 eRFPath); +extern void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, + u32 dwBitMask, u32 dwData); +extern u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, + u32 dwBitMask); +extern void rtl8192_phy_SetRFReg(struct net_device *dev, + enum rf90_radio_path eRFPath, + u32 RegAddr, u32 BitMask, u32 Data); +extern u32 rtl8192_phy_QueryRFReg(struct net_device *dev, + enum rf90_radio_path eRFPath, + u32 RegAddr, u32 BitMask); +extern void rtl8192_phy_configmac(struct net_device *dev); +extern void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType); +extern bool rtl8192_phy_checkBBAndRF(struct net_device *dev, + enum hw90_block CheckBlock, + enum rf90_radio_path eRFPath); +extern bool rtl8192_BBConfig(struct net_device *dev); +extern void rtl8192_phy_getTxPower(struct net_device *dev); +extern void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel); +extern bool rtl8192_phy_RFConfig(struct net_device *dev); +extern void rtl8192_phy_updateInitGain(struct net_device *dev); +extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, + enum rf90_radio_path eRFPath); + +extern u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel); +extern void rtl8192_SetBWMode(struct net_device *dev, + enum ht_channel_width Bandwidth, + enum ht_extchnl_offset Offset); +extern void rtl8192_SwChnl_WorkItem(struct net_device *dev); +extern void rtl8192_SetBWModeWorkItem(struct net_device *dev); +extern void InitialGain819xPci(struct net_device *dev, u8 Operation); + +extern void PHY_SetRtl8192eRfOff(struct net_device *dev); + +bool +SetRFPowerState( + struct net_device *dev, + enum rt_rf_power_state eRFPowerState + ); +#define PHY_SetRFPowerState SetRFPowerState + +extern void PHY_ScanOperationBackup8192(struct net_device *dev, u8 Operation); + +#endif diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_phyreg.h b/drivers/staging/rtl8192e/rtl8192e/r8192E_phyreg.h new file mode 100644 index 000000000000..7899dd538dcd --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_phyreg.h @@ -0,0 +1,852 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ +#ifndef _R819XU_PHYREG_H +#define _R819XU_PHYREG_H + + +#define RF_DATA 0x1d4 + +#define rPMAC_Reset 0x100 +#define rPMAC_TxStart 0x104 +#define rPMAC_TxLegacySIG 0x108 +#define rPMAC_TxHTSIG1 0x10c +#define rPMAC_TxHTSIG2 0x110 +#define rPMAC_PHYDebug 0x114 +#define rPMAC_TxPacketNum 0x118 +#define rPMAC_TxIdle 0x11c +#define rPMAC_TxMACHeader0 0x120 +#define rPMAC_TxMACHeader1 0x124 +#define rPMAC_TxMACHeader2 0x128 +#define rPMAC_TxMACHeader3 0x12c +#define rPMAC_TxMACHeader4 0x130 +#define rPMAC_TxMACHeader5 0x134 +#define rPMAC_TxDataType 0x138 +#define rPMAC_TxRandomSeed 0x13c +#define rPMAC_CCKPLCPPreamble 0x140 +#define rPMAC_CCKPLCPHeader 0x144 +#define rPMAC_CCKCRC16 0x148 +#define rPMAC_OFDMRxCRC32OK 0x170 +#define rPMAC_OFDMRxCRC32Er 0x174 +#define rPMAC_OFDMRxParityEr 0x178 +#define rPMAC_OFDMRxCRC8Er 0x17c +#define rPMAC_CCKCRxRC16Er 0x180 +#define rPMAC_CCKCRxRC32Er 0x184 +#define rPMAC_CCKCRxRC32OK 0x188 +#define rPMAC_TxStatus 0x18c + +#define MCS_TXAGC 0x340 +#define CCK_TXAGC 0x348 + +/*---------------------0x400~0x4ff----------------------*/ +#define MacBlkCtrl 0x403 + +#define rFPGA0_RFMOD 0x800 +#define rFPGA0_TxInfo 0x804 +#define rFPGA0_PSDFunction 0x808 +#define rFPGA0_TxGainStage 0x80c +#define rFPGA0_RFTiming1 0x810 +#define rFPGA0_RFTiming2 0x814 +#define rFPGA0_XA_HSSIParameter1 0x820 +#define rFPGA0_XA_HSSIParameter2 0x824 +#define rFPGA0_XB_HSSIParameter1 0x828 +#define rFPGA0_XB_HSSIParameter2 0x82c +#define rFPGA0_XC_HSSIParameter1 0x830 +#define rFPGA0_XC_HSSIParameter2 0x834 +#define rFPGA0_XD_HSSIParameter1 0x838 +#define rFPGA0_XD_HSSIParameter2 0x83c +#define rFPGA0_XA_LSSIParameter 0x840 +#define rFPGA0_XB_LSSIParameter 0x844 +#define rFPGA0_XC_LSSIParameter 0x848 +#define rFPGA0_XD_LSSIParameter 0x84c +#define rFPGA0_RFWakeUpParameter 0x850 +#define rFPGA0_RFSleepUpParameter 0x854 +#define rFPGA0_XAB_SwitchControl 0x858 +#define rFPGA0_XCD_SwitchControl 0x85c +#define rFPGA0_XA_RFInterfaceOE 0x860 +#define rFPGA0_XB_RFInterfaceOE 0x864 +#define rFPGA0_XC_RFInterfaceOE 0x868 +#define rFPGA0_XD_RFInterfaceOE 0x86c +#define rFPGA0_XAB_RFInterfaceSW 0x870 +#define rFPGA0_XCD_RFInterfaceSW 0x874 +#define rFPGA0_XAB_RFParameter 0x878 +#define rFPGA0_XCD_RFParameter 0x87c +#define rFPGA0_AnalogParameter1 0x880 +#define rFPGA0_AnalogParameter2 0x884 +#define rFPGA0_AnalogParameter3 0x888 +#define rFPGA0_AnalogParameter4 0x88c +#define rFPGA0_XA_LSSIReadBack 0x8a0 +#define rFPGA0_XB_LSSIReadBack 0x8a4 +#define rFPGA0_XC_LSSIReadBack 0x8a8 +#define rFPGA0_XD_LSSIReadBack 0x8ac +#define rFPGA0_PSDReport 0x8b4 +#define rFPGA0_XAB_RFInterfaceRB 0x8e0 +#define rFPGA0_XCD_RFInterfaceRB 0x8e4 + +#define rFPGA1_RFMOD 0x900 +#define rFPGA1_TxBlock 0x904 +#define rFPGA1_DebugSelect 0x908 +#define rFPGA1_TxInfo 0x90c + +#define rCCK0_System 0xa00 +#define rCCK0_AFESetting 0xa04 +#define rCCK0_CCA 0xa08 +#define rCCK0_RxAGC1 0xa0c +#define rCCK0_RxAGC2 0xa10 +#define rCCK0_RxHP 0xa14 +#define rCCK0_DSPParameter1 0xa18 +#define rCCK0_DSPParameter2 0xa1c +#define rCCK0_TxFilter1 0xa20 +#define rCCK0_TxFilter2 0xa24 +#define rCCK0_DebugPort 0xa28 +#define rCCK0_FalseAlarmReport 0xa2c +#define rCCK0_TRSSIReport 0xa50 +#define rCCK0_RxReport 0xa54 +#define rCCK0_FACounterLower 0xa5c +#define rCCK0_FACounterUpper 0xa58 + +#define rOFDM0_LSTF 0xc00 +#define rOFDM0_TRxPathEnable 0xc04 +#define rOFDM0_TRMuxPar 0xc08 +#define rOFDM0_TRSWIsolation 0xc0c +#define rOFDM0_XARxAFE 0xc10 +#define rOFDM0_XARxIQImbalance 0xc14 +#define rOFDM0_XBRxAFE 0xc18 +#define rOFDM0_XBRxIQImbalance 0xc1c +#define rOFDM0_XCRxAFE 0xc20 +#define rOFDM0_XCRxIQImbalance 0xc24 +#define rOFDM0_XDRxAFE 0xc28 +#define rOFDM0_XDRxIQImbalance 0xc2c +#define rOFDM0_RxDetector1 0xc30 +#define rOFDM0_RxDetector2 0xc34 +#define rOFDM0_RxDetector3 0xc38 +#define rOFDM0_RxDetector4 0xc3c +#define rOFDM0_RxDSP 0xc40 +#define rOFDM0_CFOandDAGC 0xc44 +#define rOFDM0_CCADropThreshold 0xc48 +#define rOFDM0_ECCAThreshold 0xc4c +#define rOFDM0_XAAGCCore1 0xc50 +#define rOFDM0_XAAGCCore2 0xc54 +#define rOFDM0_XBAGCCore1 0xc58 +#define rOFDM0_XBAGCCore2 0xc5c +#define rOFDM0_XCAGCCore1 0xc60 +#define rOFDM0_XCAGCCore2 0xc64 +#define rOFDM0_XDAGCCore1 0xc68 +#define rOFDM0_XDAGCCore2 0xc6c +#define rOFDM0_AGCParameter1 0xc70 +#define rOFDM0_AGCParameter2 0xc74 +#define rOFDM0_AGCRSSITable 0xc78 +#define rOFDM0_HTSTFAGC 0xc7c +#define rOFDM0_XATxIQImbalance 0xc80 +#define rOFDM0_XATxAFE 0xc84 +#define rOFDM0_XBTxIQImbalance 0xc88 +#define rOFDM0_XBTxAFE 0xc8c +#define rOFDM0_XCTxIQImbalance 0xc90 +#define rOFDM0_XCTxAFE 0xc94 +#define rOFDM0_XDTxIQImbalance 0xc98 +#define rOFDM0_XDTxAFE 0xc9c +#define rOFDM0_RxHPParameter 0xce0 +#define rOFDM0_TxPseudoNoiseWgt 0xce4 +#define rOFDM0_FrameSync 0xcf0 +#define rOFDM0_DFSReport 0xcf4 +#define rOFDM0_TxCoeff1 0xca4 +#define rOFDM0_TxCoeff2 0xca8 +#define rOFDM0_TxCoeff3 0xcac +#define rOFDM0_TxCoeff4 0xcb0 +#define rOFDM0_TxCoeff5 0xcb4 +#define rOFDM0_TxCoeff6 0xcb8 + + +#define rOFDM1_LSTF 0xd00 +#define rOFDM1_TRxPathEnable 0xd04 +#define rOFDM1_CFO 0xd08 +#define rOFDM1_CSI1 0xd10 +#define rOFDM1_SBD 0xd14 +#define rOFDM1_CSI2 0xd18 +#define rOFDM1_CFOTracking 0xd2c +#define rOFDM1_TRxMesaure1 0xd34 +#define rOFDM1_IntfDet 0xd3c +#define rOFDM1_PseudoNoiseStateAB 0xd50 +#define rOFDM1_PseudoNoiseStateCD 0xd54 +#define rOFDM1_RxPseudoNoiseWgt 0xd58 +#define rOFDM_PHYCounter1 0xda0 +#define rOFDM_PHYCounter2 0xda4 +#define rOFDM_PHYCounter3 0xda8 +#define rOFDM_ShortCFOAB 0xdac +#define rOFDM_ShortCFOCD 0xdb0 +#define rOFDM_LongCFOAB 0xdb4 +#define rOFDM_LongCFOCD 0xdb8 +#define rOFDM_TailCFOAB 0xdbc +#define rOFDM_TailCFOCD 0xdc0 +#define rOFDM_PWMeasure1 0xdc4 +#define rOFDM_PWMeasure2 0xdc8 +#define rOFDM_BWReport 0xdcc +#define rOFDM_AGCReport 0xdd0 +#define rOFDM_RxSNR 0xdd4 +#define rOFDM_RxEVMCSI 0xdd8 +#define rOFDM_SIGReport 0xddc + +#define rTxAGC_Rate18_06 0xe00 +#define rTxAGC_Rate54_24 0xe04 +#define rTxAGC_CCK_Mcs32 0xe08 +#define rTxAGC_Mcs03_Mcs00 0xe10 +#define rTxAGC_Mcs07_Mcs04 0xe14 +#define rTxAGC_Mcs11_Mcs08 0xe18 +#define rTxAGC_Mcs15_Mcs12 0xe1c + + +#define rZebra1_HSSIEnable 0x0 +#define rZebra1_TRxEnable1 0x1 +#define rZebra1_TRxEnable2 0x2 +#define rZebra1_AGC 0x4 +#define rZebra1_ChargePump 0x5 +#define rZebra1_Channel 0x7 +#define rZebra1_TxGain 0x8 +#define rZebra1_TxLPF 0x9 +#define rZebra1_RxLPF 0xb +#define rZebra1_RxHPFCorner 0xc + +#define rGlobalCtrl 0 +#define rRTL8256_TxLPF 19 +#define rRTL8256_RxLPF 11 + +#define rRTL8258_TxLPF 0x11 +#define rRTL8258_RxLPF 0x13 +#define rRTL8258_RSSILPF 0xa + +#define bBBResetB 0x100 +#define bGlobalResetB 0x200 +#define bOFDMTxStart 0x4 +#define bCCKTxStart 0x8 +#define bCRC32Debug 0x100 +#define bPMACLoopback 0x10 +#define bTxLSIG 0xffffff +#define bOFDMTxRate 0xf +#define bOFDMTxReserved 0x10 +#define bOFDMTxLength 0x1ffe0 +#define bOFDMTxParity 0x20000 +#define bTxHTSIG1 0xffffff +#define bTxHTMCSRate 0x7f +#define bTxHTBW 0x80 +#define bTxHTLength 0xffff00 +#define bTxHTSIG2 0xffffff +#define bTxHTSmoothing 0x1 +#define bTxHTSounding 0x2 +#define bTxHTReserved 0x4 +#define bTxHTAggreation 0x8 +#define bTxHTSTBC 0x30 +#define bTxHTAdvanceCoding 0x40 +#define bTxHTShortGI 0x80 +#define bTxHTNumberHT_LTF 0x300 +#define bTxHTCRC8 0x3fc00 +#define bCounterReset 0x10000 +#define bNumOfOFDMTx 0xffff +#define bNumOfCCKTx 0xffff0000 +#define bTxIdleInterval 0xffff +#define bOFDMService 0xffff0000 +#define bTxMACHeader 0xffffffff +#define bTxDataInit 0xff +#define bTxHTMode 0x100 +#define bTxDataType 0x30000 +#define bTxRandomSeed 0xffffffff +#define bCCKTxPreamble 0x1 +#define bCCKTxSFD 0xffff0000 +#define bCCKTxSIG 0xff +#define bCCKTxService 0xff00 +#define bCCKLengthExt 0x8000 +#define bCCKTxLength 0xffff0000 +#define bCCKTxCRC16 0xffff +#define bCCKTxStatus 0x1 +#define bOFDMTxStatus 0x2 + +#define bRFMOD 0x1 +#define bJapanMode 0x2 +#define bCCKTxSC 0x30 +#define bCCKEn 0x1000000 +#define bOFDMEn 0x2000000 +#define bOFDMRxADCPhase 0x10000 +#define bOFDMTxDACPhase 0x40000 +#define bXATxAGC 0x3f +#define bXBTxAGC 0xf00 +#define bXCTxAGC 0xf000 +#define bXDTxAGC 0xf0000 +#define bPAStart 0xf0000000 +#define bTRStart 0x00f00000 +#define bRFStart 0x0000f000 +#define bBBStart 0x000000f0 +#define bBBCCKStart 0x0000000f +#define bPAEnd 0xf +#define bTREnd 0x0f000000 +#define bRFEnd 0x000f0000 +#define bCCAMask 0x000000f0 +#define bR2RCCAMask 0x00000f00 +#define bHSSI_R2TDelay 0xf8000000 +#define bHSSI_T2RDelay 0xf80000 +#define bContTxHSSI 0x400 +#define bIGFromCCK 0x200 +#define bAGCAddress 0x3f +#define bRxHPTx 0x7000 +#define bRxHPT2R 0x38000 +#define bRxHPCCKIni 0xc0000 +#define bAGCTxCode 0xc00000 +#define bAGCRxCode 0x300000 +#define b3WireDataLength 0x800 +#define b3WireAddressLength 0x400 +#define b3WireRFPowerDown 0x1 +#define b5GPAPEPolarity 0x40000000 +#define b2GPAPEPolarity 0x80000000 +#define bRFSW_TxDefaultAnt 0x3 +#define bRFSW_TxOptionAnt 0x30 +#define bRFSW_RxDefaultAnt 0x300 +#define bRFSW_RxOptionAnt 0x3000 +#define bRFSI_3WireData 0x1 +#define bRFSI_3WireClock 0x2 +#define bRFSI_3WireLoad 0x4 +#define bRFSI_3WireRW 0x8 +#define bRFSI_3Wire 0xf +#define bRFSI_RFENV 0x10 +#define bRFSI_TRSW 0x20 +#define bRFSI_TRSWB 0x40 +#define bRFSI_ANTSW 0x100 +#define bRFSI_ANTSWB 0x200 +#define bRFSI_PAPE 0x400 +#define bRFSI_PAPE5G 0x800 +#define bBandSelect 0x1 +#define bHTSIG2_GI 0x80 +#define bHTSIG2_Smoothing 0x01 +#define bHTSIG2_Sounding 0x02 +#define bHTSIG2_Aggreaton 0x08 +#define bHTSIG2_STBC 0x30 +#define bHTSIG2_AdvCoding 0x40 +#define bHTSIG2_NumOfHTLTF 0x300 +#define bHTSIG2_CRC8 0x3fc +#define bHTSIG1_MCS 0x7f +#define bHTSIG1_BandWidth 0x80 +#define bHTSIG1_HTLength 0xffff +#define bLSIG_Rate 0xf +#define bLSIG_Reserved 0x10 +#define bLSIG_Length 0x1fffe +#define bLSIG_Parity 0x20 +#define bCCKRxPhase 0x4 +#define bLSSIReadAddress 0x3f000000 +#define bLSSIReadEdge 0x80000000 +#define bLSSIReadBackData 0xfff +#define bLSSIReadOKFlag 0x1000 +#define bCCKSampleRate 0x8 + +#define bRegulator0Standby 0x1 +#define bRegulatorPLLStandby 0x2 +#define bRegulator1Standby 0x4 +#define bPLLPowerUp 0x8 +#define bDPLLPowerUp 0x10 +#define bDA10PowerUp 0x20 +#define bAD7PowerUp 0x200 +#define bDA6PowerUp 0x2000 +#define bXtalPowerUp 0x4000 +#define b40MDClkPowerUP 0x8000 +#define bDA6DebugMode 0x20000 +#define bDA6Swing 0x380000 +#define bADClkPhase 0x4000000 +#define b80MClkDelay 0x18000000 +#define bAFEWatchDogEnable 0x20000000 +#define bXtalCap 0x0f000000 +#define bXtalCap01 0xc0000000 +#define bXtalCap23 0x3 +#define bXtalCap92x 0x0f000000 +#define bIntDifClkEnable 0x400 +#define bExtSigClkEnable 0x800 +#define bBandgapMbiasPowerUp 0x10000 +#define bAD11SHGain 0xc0000 +#define bAD11InputRange 0x700000 +#define bAD11OPCurrent 0x3800000 +#define bIPathLoopback 0x4000000 +#define bQPathLoopback 0x8000000 +#define bAFELoopback 0x10000000 +#define bDA10Swing 0x7e0 +#define bDA10Reverse 0x800 +#define bDAClkSource 0x1000 +#define bAD7InputRange 0x6000 +#define bAD7Gain 0x38000 +#define bAD7OutputCMMode 0x40000 +#define bAD7InputCMMode 0x380000 +#define bAD7Current 0xc00000 +#define bRegulatorAdjust 0x7000000 +#define bAD11PowerUpAtTx 0x1 +#define bDA10PSAtTx 0x10 +#define bAD11PowerUpAtRx 0x100 +#define bDA10PSAtRx 0x1000 + +#define bCCKRxAGCFormat 0x200 + +#define bPSDFFTSamplepPoint 0xc000 +#define bPSDAverageNum 0x3000 +#define bIQPathControl 0xc00 +#define bPSDFreq 0x3ff +#define bPSDAntennaPath 0x30 +#define bPSDIQSwitch 0x40 +#define bPSDRxTrigger 0x400000 +#define bPSDTxTrigger 0x80000000 +#define bPSDSineToneScale 0x7f000000 +#define bPSDReport 0xffff + +#define bOFDMTxSC 0x30000000 +#define bCCKTxOn 0x1 +#define bOFDMTxOn 0x2 +#define bDebugPage 0xfff +#define bDebugItem 0xff +#define bAntL 0x10 +#define bAntNonHT 0x100 +#define bAntHT1 0x1000 +#define bAntHT2 0x10000 +#define bAntHT1S1 0x100000 +#define bAntNonHTS1 0x1000000 + +#define bCCKBBMode 0x3 +#define bCCKTxPowerSaving 0x80 +#define bCCKRxPowerSaving 0x40 +#define bCCKSideBand 0x10 +#define bCCKScramble 0x8 +#define bCCKAntDiversity 0x8000 +#define bCCKCarrierRecovery 0x4000 +#define bCCKTxRate 0x3000 +#define bCCKDCCancel 0x0800 +#define bCCKISICancel 0x0400 +#define bCCKMatchFilter 0x0200 +#define bCCKEqualizer 0x0100 +#define bCCKPreambleDetect 0x800000 +#define bCCKFastFalseCCA 0x400000 +#define bCCKChEstStart 0x300000 +#define bCCKCCACount 0x080000 +#define bCCKcs_lim 0x070000 +#define bCCKBistMode 0x80000000 +#define bCCKCCAMask 0x40000000 +#define bCCKTxDACPhase 0x4 +#define bCCKRxADCPhase 0x20000000 +#define bCCKr_cp_mode0 0x0100 +#define bCCKTxDCOffset 0xf0 +#define bCCKRxDCOffset 0xf +#define bCCKCCAMode 0xc000 +#define bCCKFalseCS_lim 0x3f00 +#define bCCKCS_ratio 0xc00000 +#define bCCKCorgBit_sel 0x300000 +#define bCCKPD_lim 0x0f0000 +#define bCCKNewCCA 0x80000000 +#define bCCKRxHPofIG 0x8000 +#define bCCKRxIG 0x7f00 +#define bCCKLNAPolarity 0x800000 +#define bCCKRx1stGain 0x7f0000 +#define bCCKRFExtend 0x20000000 +#define bCCKRxAGCSatLevel 0x1f000000 +#define bCCKRxAGCSatCount 0xe0 +#define bCCKRxRFSettle 0x1f +#define bCCKFixedRxAGC 0x8000 +#define bCCKAntennaPolarity 0x2000 +#define bCCKTxFilterType 0x0c00 +#define bCCKRxAGCReportType 0x0300 +#define bCCKRxDAGCEn 0x80000000 +#define bCCKRxDAGCPeriod 0x20000000 +#define bCCKRxDAGCSatLevel 0x1f000000 +#define bCCKTimingRecovery 0x800000 +#define bCCKTxC0 0x3f0000 +#define bCCKTxC1 0x3f000000 +#define bCCKTxC2 0x3f +#define bCCKTxC3 0x3f00 +#define bCCKTxC4 0x3f0000 +#define bCCKTxC5 0x3f000000 +#define bCCKTxC6 0x3f +#define bCCKTxC7 0x3f00 +#define bCCKDebugPort 0xff0000 +#define bCCKDACDebug 0x0f000000 +#define bCCKFalseAlarmEnable 0x8000 +#define bCCKFalseAlarmRead 0x4000 +#define bCCKTRSSI 0x7f +#define bCCKRxAGCReport 0xfe +#define bCCKRxReport_AntSel 0x80000000 +#define bCCKRxReport_MFOff 0x40000000 +#define bCCKRxRxReport_SQLoss 0x20000000 +#define bCCKRxReport_Pktloss 0x10000000 +#define bCCKRxReport_Lockedbit 0x08000000 +#define bCCKRxReport_RateError 0x04000000 +#define bCCKRxReport_RxRate 0x03000000 +#define bCCKRxFACounterLower 0xff +#define bCCKRxFACounterUpper 0xff000000 +#define bCCKRxHPAGCStart 0xe000 +#define bCCKRxHPAGCFinal 0x1c00 + +#define bCCKRxFalseAlarmEnable 0x8000 +#define bCCKFACounterFreeze 0x4000 + +#define bCCKTxPathSel 0x10000000 +#define bCCKDefaultRxPath 0xc000000 +#define bCCKOptionRxPath 0x3000000 + +#define bNumOfSTF 0x3 +#define bShift_L 0xc0 +#define bGI_TH 0xc +#define bRxPathA 0x1 +#define bRxPathB 0x2 +#define bRxPathC 0x4 +#define bRxPathD 0x8 +#define bTxPathA 0x1 +#define bTxPathB 0x2 +#define bTxPathC 0x4 +#define bTxPathD 0x8 +#define bTRSSIFreq 0x200 +#define bADCBackoff 0x3000 +#define bDFIRBackoff 0xc000 +#define bTRSSILatchPhase 0x10000 +#define bRxIDCOffset 0xff +#define bRxQDCOffset 0xff00 +#define bRxDFIRMode 0x1800000 +#define bRxDCNFType 0xe000000 +#define bRXIQImb_A 0x3ff +#define bRXIQImb_B 0xfc00 +#define bRXIQImb_C 0x3f0000 +#define bRXIQImb_D 0xffc00000 +#define bDC_dc_Notch 0x60000 +#define bRxNBINotch 0x1f000000 +#define bPD_TH 0xf +#define bPD_TH_Opt2 0xc000 +#define bPWED_TH 0x700 +#define bIfMF_Win_L 0x800 +#define bPD_Option 0x1000 +#define bMF_Win_L 0xe000 +#define bBW_Search_L 0x30000 +#define bwin_enh_L 0xc0000 +#define bBW_TH 0x700000 +#define bED_TH2 0x3800000 +#define bBW_option 0x4000000 +#define bRatio_TH 0x18000000 +#define bWindow_L 0xe0000000 +#define bSBD_Option 0x1 +#define bFrame_TH 0x1c +#define bFS_Option 0x60 +#define bDC_Slope_check 0x80 +#define bFGuard_Counter_DC_L 0xe00 +#define bFrame_Weight_Short 0x7000 +#define bSub_Tune 0xe00000 +#define bFrame_DC_Length 0xe000000 +#define bSBD_start_offset 0x30000000 +#define bFrame_TH_2 0x7 +#define bFrame_GI2_TH 0x38 +#define bGI2_Sync_en 0x40 +#define bSarch_Short_Early 0x300 +#define bSarch_Short_Late 0xc00 +#define bSarch_GI2_Late 0x70000 +#define bCFOAntSum 0x1 +#define bCFOAcc 0x2 +#define bCFOStartOffset 0xc +#define bCFOLookBack 0x70 +#define bCFOSumWeight 0x80 +#define bDAGCEnable 0x10000 +#define bTXIQImb_A 0x3ff +#define bTXIQImb_B 0xfc00 +#define bTXIQImb_C 0x3f0000 +#define bTXIQImb_D 0xffc00000 +#define bTxIDCOffset 0xff +#define bTxQDCOffset 0xff00 +#define bTxDFIRMode 0x10000 +#define bTxPesudoNoiseOn 0x4000000 +#define bTxPesudoNoise_A 0xff +#define bTxPesudoNoise_B 0xff00 +#define bTxPesudoNoise_C 0xff0000 +#define bTxPesudoNoise_D 0xff000000 +#define bCCADropOption 0x20000 +#define bCCADropThres 0xfff00000 +#define bEDCCA_H 0xf +#define bEDCCA_L 0xf0 +#define bLambda_ED 0x300 +#define bRxInitialGain 0x7f +#define bRxAntDivEn 0x80 +#define bRxAGCAddressForLNA 0x7f00 +#define bRxHighPowerFlow 0x8000 +#define bRxAGCFreezeThres 0xc0000 +#define bRxFreezeStep_AGC1 0x300000 +#define bRxFreezeStep_AGC2 0xc00000 +#define bRxFreezeStep_AGC3 0x3000000 +#define bRxFreezeStep_AGC0 0xc000000 +#define bRxRssi_Cmp_En 0x10000000 +#define bRxQuickAGCEn 0x20000000 +#define bRxAGCFreezeThresMode 0x40000000 +#define bRxOverFlowCheckType 0x80000000 +#define bRxAGCShift 0x7f +#define bTRSW_Tri_Only 0x80 +#define bPowerThres 0x300 +#define bRxAGCEn 0x1 +#define bRxAGCTogetherEn 0x2 +#define bRxAGCMin 0x4 +#define bRxHP_Ini 0x7 +#define bRxHP_TRLNA 0x70 +#define bRxHP_RSSI 0x700 +#define bRxHP_BBP1 0x7000 +#define bRxHP_BBP2 0x70000 +#define bRxHP_BBP3 0x700000 +#define bRSSI_H 0x7f0000 +#define bRSSI_Gen 0x7f000000 +#define bRxSettle_TRSW 0x7 +#define bRxSettle_LNA 0x38 +#define bRxSettle_RSSI 0x1c0 +#define bRxSettle_BBP 0xe00 +#define bRxSettle_RxHP 0x7000 +#define bRxSettle_AntSW_RSSI 0x38000 +#define bRxSettle_AntSW 0xc0000 +#define bRxProcessTime_DAGC 0x300000 +#define bRxSettle_HSSI 0x400000 +#define bRxProcessTime_BBPPW 0x800000 +#define bRxAntennaPowerShift 0x3000000 +#define bRSSITableSelect 0xc000000 +#define bRxHP_Final 0x7000000 +#define bRxHTSettle_BBP 0x7 +#define bRxHTSettle_HSSI 0x8 +#define bRxHTSettle_RxHP 0x70 +#define bRxHTSettle_BBPPW 0x80 +#define bRxHTSettle_Idle 0x300 +#define bRxHTSettle_Reserved 0x1c00 +#define bRxHTRxHPEn 0x8000 +#define bRxHTAGCFreezeThres 0x30000 +#define bRxHTAGCTogetherEn 0x40000 +#define bRxHTAGCMin 0x80000 +#define bRxHTAGCEn 0x100000 +#define bRxHTDAGCEn 0x200000 +#define bRxHTRxHP_BBP 0x1c00000 +#define bRxHTRxHP_Final 0xe0000000 +#define bRxPWRatioTH 0x3 +#define bRxPWRatioEn 0x4 +#define bRxMFHold 0x3800 +#define bRxPD_Delay_TH1 0x38 +#define bRxPD_Delay_TH2 0x1c0 +#define bRxPD_DC_COUNT_MAX 0x600 +#define bRxPD_Delay_TH 0x8000 +#define bRxProcess_Delay 0xf0000 +#define bRxSearchrange_GI2_Early 0x700000 +#define bRxFrame_Guard_Counter_L 0x3800000 +#define bRxSGI_Guard_L 0xc000000 +#define bRxSGI_Search_L 0x30000000 +#define bRxSGI_TH 0xc0000000 +#define bDFSCnt0 0xff +#define bDFSCnt1 0xff00 +#define bDFSFlag 0xf0000 + +#define bMFWeightSum 0x300000 +#define bMinIdxTH 0x7f000000 + +#define bDAFormat 0x40000 + +#define bTxChEmuEnable 0x01000000 + +#define bTRSWIsolation_A 0x7f +#define bTRSWIsolation_B 0x7f00 +#define bTRSWIsolation_C 0x7f0000 +#define bTRSWIsolation_D 0x7f000000 + +#define bExtLNAGain 0x7c00 + +#define bSTBCEn 0x4 +#define bAntennaMapping 0x10 +#define bNss 0x20 +#define bCFOAntSumD 0x200 +#define bPHYCounterReset 0x8000000 +#define bCFOReportGet 0x4000000 +#define bOFDMContinueTx 0x10000000 +#define bOFDMSingleCarrier 0x20000000 +#define bOFDMSingleTone 0x40000000 +#define bHTDetect 0x100 +#define bCFOEn 0x10000 +#define bCFOValue 0xfff00000 +#define bSigTone_Re 0x3f +#define bSigTone_Im 0x7f00 +#define bCounter_CCA 0xffff +#define bCounter_ParityFail 0xffff0000 +#define bCounter_RateIllegal 0xffff +#define bCounter_CRC8Fail 0xffff0000 +#define bCounter_MCSNoSupport 0xffff +#define bCounter_FastSync 0xffff +#define bShortCFO 0xfff +#define bShortCFOTLength 12 +#define bShortCFOFLength 11 +#define bLongCFO 0x7ff +#define bLongCFOTLength 11 +#define bLongCFOFLength 11 +#define bTailCFO 0x1fff +#define bTailCFOTLength 13 +#define bTailCFOFLength 12 + +#define bmax_en_pwdB 0xffff +#define bCC_power_dB 0xffff0000 +#define bnoise_pwdB 0xffff +#define bPowerMeasTLength 10 +#define bPowerMeasFLength 3 +#define bRx_HT_BW 0x1 +#define bRxSC 0x6 +#define bRx_HT 0x8 + +#define bNB_intf_det_on 0x1 +#define bIntf_win_len_cfg 0x30 +#define bNB_Intf_TH_cfg 0x1c0 + +#define bRFGain 0x3f +#define bTableSel 0x40 +#define bTRSW 0x80 + +#define bRxSNR_A 0xff +#define bRxSNR_B 0xff00 +#define bRxSNR_C 0xff0000 +#define bRxSNR_D 0xff000000 +#define bSNREVMTLength 8 +#define bSNREVMFLength 1 + +#define bCSI1st 0xff +#define bCSI2nd 0xff00 +#define bRxEVM1st 0xff0000 +#define bRxEVM2nd 0xff000000 + +#define bSIGEVM 0xff +#define bPWDB 0xff00 +#define bSGIEN 0x10000 + +#define bSFactorQAM1 0xf +#define bSFactorQAM2 0xf0 +#define bSFactorQAM3 0xf00 +#define bSFactorQAM4 0xf000 +#define bSFactorQAM5 0xf0000 +#define bSFactorQAM6 0xf0000 +#define bSFactorQAM7 0xf00000 +#define bSFactorQAM8 0xf000000 +#define bSFactorQAM9 0xf0000000 +#define bCSIScheme 0x100000 + +#define bNoiseLvlTopSet 0x3 +#define bChSmooth 0x4 +#define bChSmoothCfg1 0x38 +#define bChSmoothCfg2 0x1c0 +#define bChSmoothCfg3 0xe00 +#define bChSmoothCfg4 0x7000 +#define bMRCMode 0x800000 +#define bTHEVMCfg 0x7000000 + +#define bLoopFitType 0x1 +#define bUpdCFO 0x40 +#define bUpdCFOOffData 0x80 +#define bAdvUpdCFO 0x100 +#define bAdvTimeCtrl 0x800 +#define bUpdClko 0x1000 +#define bFC 0x6000 +#define bTrackingMode 0x8000 +#define bPhCmpEnable 0x10000 +#define bUpdClkoLTF 0x20000 +#define bComChCFO 0x40000 +#define bCSIEstiMode 0x80000 +#define bAdvUpdEqz 0x100000 +#define bUChCfg 0x7000000 +#define bUpdEqz 0x8000000 + +#define bTxAGCRate18_06 0x7f7f7f7f +#define bTxAGCRate54_24 0x7f7f7f7f +#define bTxAGCRateMCS32 0x7f +#define bTxAGCRateCCK 0x7f00 +#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f +#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f +#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f +#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f + + +#define bRxPesudoNoiseOn 0x20000000 +#define bRxPesudoNoise_A 0xff +#define bRxPesudoNoise_B 0xff00 +#define bRxPesudoNoise_C 0xff0000 +#define bRxPesudoNoise_D 0xff000000 +#define bPesudoNoiseState_A 0xffff +#define bPesudoNoiseState_B 0xffff0000 +#define bPesudoNoiseState_C 0xffff +#define bPesudoNoiseState_D 0xffff0000 + +#define bZebra1_HSSIEnable 0x8 +#define bZebra1_TRxControl 0xc00 +#define bZebra1_TRxGainSetting 0x07f +#define bZebra1_RxCorner 0xc00 +#define bZebra1_TxChargePump 0x38 +#define bZebra1_RxChargePump 0x7 +#define bZebra1_ChannelNum 0xf80 +#define bZebra1_TxLPFBW 0x400 +#define bZebra1_RxLPFBW 0x600 + +#define bRTL8256RegModeCtrl1 0x100 +#define bRTL8256RegModeCtrl0 0x40 +#define bRTL8256_TxLPFBW 0x18 +#define bRTL8256_RxLPFBW 0x600 + +#define bRTL8258_TxLPFBW 0xc +#define bRTL8258_RxLPFBW 0xc00 +#define bRTL8258_RSSILPFBW 0xc0 + +#define bByte0 0x1 +#define bByte1 0x2 +#define bByte2 0x4 +#define bByte3 0x8 +#define bWord0 0x3 +#define bWord1 0xc +#define bDWord 0xf + +#define bMaskByte0 0xff +#define bMaskByte1 0xff00 +#define bMaskByte2 0xff0000 +#define bMaskByte3 0xff000000 +#define bMaskHWord 0xffff0000 +#define bMaskLWord 0x0000ffff +#define bMaskDWord 0xffffffff + +#define bMask12Bits 0xfff + +#define bEnable 0x1 +#define bDisable 0x0 + +#define LeftAntenna 0x0 +#define RightAntenna 0x1 + +#define tCheckTxStatus 500 +#define tUpdateRxCounter 100 + +#define rateCCK 0 +#define rateOFDM 1 +#define rateHT 2 + +#define bPMAC_End 0x1ff +#define bFPGAPHY0_End 0x8ff +#define bFPGAPHY1_End 0x9ff +#define bCCKPHY0_End 0xaff +#define bOFDMPHY0_End 0xcff +#define bOFDMPHY1_End 0xdff + + +#define bPMACControl 0x0 +#define bWMACControl 0x1 +#define bWNICControl 0x2 + +#define PathA 0x0 +#define PathB 0x1 +#define PathC 0x2 +#define PathD 0x3 + +#define rRTL8256RxMixerPole 0xb +#define bZebraRxMixerPole 0x6 +#define rRTL8256TxBBOPBias 0x9 +#define bRTL8256TxBBOPBias 0x400 +#define rRTL8256TxBBBW 19 +#define bRTL8256TxBBBW 0x18 + +#endif diff --git a/drivers/staging/rtl8192e/rtl8192e/r819xE_phyreg.h b/drivers/staging/rtl8192e/rtl8192e/r819xE_phyreg.h new file mode 100644 index 000000000000..d5de279f6644 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/r819xE_phyreg.h @@ -0,0 +1,915 @@ +#ifndef _R819XU_PHYREG_H +#define _R819XU_PHYREG_H + + +#define RF_DATA 0x1d4 // FW will write RF data in the register. + +//Register //duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF +//page 1 +#define rPMAC_Reset 0x100 +#define rPMAC_TxStart 0x104 +#define rPMAC_TxLegacySIG 0x108 +#define rPMAC_TxHTSIG1 0x10c +#define rPMAC_TxHTSIG2 0x110 +#define rPMAC_PHYDebug 0x114 +#define rPMAC_TxPacketNum 0x118 +#define rPMAC_TxIdle 0x11c +#define rPMAC_TxMACHeader0 0x120 +#define rPMAC_TxMACHeader1 0x124 +#define rPMAC_TxMACHeader2 0x128 +#define rPMAC_TxMACHeader3 0x12c +#define rPMAC_TxMACHeader4 0x130 +#define rPMAC_TxMACHeader5 0x134 +#define rPMAC_TxDataType 0x138 +#define rPMAC_TxRandomSeed 0x13c +#define rPMAC_CCKPLCPPreamble 0x140 +#define rPMAC_CCKPLCPHeader 0x144 +#define rPMAC_CCKCRC16 0x148 +#define rPMAC_OFDMRxCRC32OK 0x170 +#define rPMAC_OFDMRxCRC32Er 0x174 +#define rPMAC_OFDMRxParityEr 0x178 +#define rPMAC_OFDMRxCRC8Er 0x17c +#define rPMAC_CCKCRxRC16Er 0x180 +#define rPMAC_CCKCRxRC32Er 0x184 +#define rPMAC_CCKCRxRC32OK 0x188 +#define rPMAC_TxStatus 0x18c + +//90P +#define MCS_TXAGC 0x340 // MCS AGC +#define CCK_TXAGC 0x348 // CCK AGC + +#define MacBlkCtrl 0x403 // Mac block on/off control register + +//page8 +#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC +#define rFPGA0_TxInfo 0x804 +#define rFPGA0_PSDFunction 0x808 +#define rFPGA0_TxGainStage 0x80c +#define rFPGA0_RFTiming1 0x810 +#define rFPGA0_RFTiming2 0x814 +//#define rFPGA0_XC_RFTiming 0x818 +//#define rFPGA0_XD_RFTiming 0x81c +#define rFPGA0_XA_HSSIParameter1 0x820 +#define rFPGA0_XA_HSSIParameter2 0x824 +#define rFPGA0_XB_HSSIParameter1 0x828 +#define rFPGA0_XB_HSSIParameter2 0x82c +#define rFPGA0_XC_HSSIParameter1 0x830 +#define rFPGA0_XC_HSSIParameter2 0x834 +#define rFPGA0_XD_HSSIParameter1 0x838 +#define rFPGA0_XD_HSSIParameter2 0x83c +#define rFPGA0_XA_LSSIParameter 0x840 +#define rFPGA0_XB_LSSIParameter 0x844 +#define rFPGA0_XC_LSSIParameter 0x848 +#define rFPGA0_XD_LSSIParameter 0x84c +#define rFPGA0_RFWakeUpParameter 0x850 +#define rFPGA0_RFSleepUpParameter 0x854 +#define rFPGA0_XAB_SwitchControl 0x858 +#define rFPGA0_XCD_SwitchControl 0x85c +#define rFPGA0_XA_RFInterfaceOE 0x860 +#define rFPGA0_XB_RFInterfaceOE 0x864 +#define rFPGA0_XC_RFInterfaceOE 0x868 +#define rFPGA0_XD_RFInterfaceOE 0x86c +#define rFPGA0_XAB_RFInterfaceSW 0x870 +#define rFPGA0_XCD_RFInterfaceSW 0x874 +#define rFPGA0_XAB_RFParameter 0x878 +#define rFPGA0_XCD_RFParameter 0x87c +#define rFPGA0_AnalogParameter1 0x880 +#define rFPGA0_AnalogParameter2 0x884 +#define rFPGA0_AnalogParameter3 0x888 +#define rFPGA0_AnalogParameter4 0x88c +#define rFPGA0_XA_LSSIReadBack 0x8a0 +#define rFPGA0_XB_LSSIReadBack 0x8a4 +#define rFPGA0_XC_LSSIReadBack 0x8a8 +#define rFPGA0_XD_LSSIReadBack 0x8ac +#define rFPGA0_PSDReport 0x8b4 +#define rFPGA0_XAB_RFInterfaceRB 0x8e0 +#define rFPGA0_XCD_RFInterfaceRB 0x8e4 + +/* Page 9 - RF mode & OFDM TxSC */ +#define rFPGA1_RFMOD 0x900 +#define rFPGA1_TxBlock 0x904 +#define rFPGA1_DebugSelect 0x908 +#define rFPGA1_TxInfo 0x90c + +/* Page a */ +#define rCCK0_System 0xa00 +#define rCCK0_AFESetting 0xa04 +#define rCCK0_CCA 0xa08 +/* AGC default value, saturation level */ +#define rCCK0_RxAGC1 0xa0c +/* AGC & DAGC */ +#define rCCK0_RxAGC2 0xa10 +#define rCCK0_RxHP 0xa14 +/* Timing recovery & channel estimation threshold */ +#define rCCK0_DSPParameter1 0xa18 +/* SQ threshold */ +#define rCCK0_DSPParameter2 0xa1c +#define rCCK0_TxFilter1 0xa20 +#define rCCK0_TxFilter2 0xa24 +/* Debug port and TX filter 3 */ +#define rCCK0_DebugPort 0xa28 +#define rCCK0_FalseAlarmReport 0xa2c +#define rCCK0_TRSSIReport 0xa50 +#define rCCK0_RxReport 0xa54 +#define rCCK0_FACounterLower 0xa5c +#define rCCK0_FACounterUpper 0xa58 + +/* Page c */ +#define rOFDM0_LSTF 0xc00 +#define rOFDM0_TRxPathEnable 0xc04 +#define rOFDM0_TRMuxPar 0xc08 +#define rOFDM0_TRSWIsolation 0xc0c +/* RxIQ DC offset, Rx digital filter, DC notch filter */ +#define rOFDM0_XARxAFE 0xc10 +/* RxIQ imblance matrix */ +#define rOFDM0_XARxIQImbalance 0xc14 +#define rOFDM0_XBRxAFE 0xc18 +#define rOFDM0_XBRxIQImbalance 0xc1c +#define rOFDM0_XCRxAFE 0xc20 +#define rOFDM0_XCRxIQImbalance 0xc24 +#define rOFDM0_XDRxAFE 0xc28 +#define rOFDM0_XDRxIQImbalance 0xc2c +/* PD, BW & SBD */ +#define rOFDM0_RxDetector1 0xc30 +/* SBD */ +#define rOFDM0_RxDetector2 0xc34 +/* Frame Sync */ +#define rOFDM0_RxDetector3 0xc38 +/* PD, SBD, Frame Sync & Short-GI */ +#define rOFDM0_RxDetector4 0xc3c +/* Rx Sync Path */ +#define rOFDM0_RxDSP 0xc40 +/* CFO & DAGC */ +#define rOFDM0_CFOandDAGC 0xc44 +/* CCA Drop threshold */ +#define rOFDM0_CCADropThreshold 0xc48 +/* Energy CCA */ +#define rOFDM0_ECCAThreshold 0xc4c +#define rOFDM0_XAAGCCore1 0xc50 +#define rOFDM0_XAAGCCore2 0xc54 +#define rOFDM0_XBAGCCore1 0xc58 +#define rOFDM0_XBAGCCore2 0xc5c +#define rOFDM0_XCAGCCore1 0xc60 +#define rOFDM0_XCAGCCore2 0xc64 +#define rOFDM0_XDAGCCore1 0xc68 +#define rOFDM0_XDAGCCore2 0xc6c +#define rOFDM0_AGCParameter1 0xc70 +#define rOFDM0_AGCParameter2 0xc74 +#define rOFDM0_AGCRSSITable 0xc78 +#define rOFDM0_HTSTFAGC 0xc7c +#define rOFDM0_XATxIQImbalance 0xc80 +#define rOFDM0_XATxAFE 0xc84 +#define rOFDM0_XBTxIQImbalance 0xc88 +#define rOFDM0_XBTxAFE 0xc8c +#define rOFDM0_XCTxIQImbalance 0xc90 +#define rOFDM0_XCTxAFE 0xc94 +#define rOFDM0_XDTxIQImbalance 0xc98 +#define rOFDM0_XDTxAFE 0xc9c +#define rOFDM0_RxHPParameter 0xce0 +#define rOFDM0_TxPseudoNoiseWgt 0xce4 +#define rOFDM0_FrameSync 0xcf0 +#define rOFDM0_DFSReport 0xcf4 +#define rOFDM0_TxCoeff1 0xca4 +#define rOFDM0_TxCoeff2 0xca8 +#define rOFDM0_TxCoeff3 0xcac +#define rOFDM0_TxCoeff4 0xcb0 +#define rOFDM0_TxCoeff5 0xcb4 +#define rOFDM0_TxCoeff6 0xcb8 + + +/* Page d */ +#define rOFDM1_LSTF 0xd00 +#define rOFDM1_TRxPathEnable 0xd04 +#define rOFDM1_CFO 0xd08 +#define rOFDM1_CSI1 0xd10 +#define rOFDM1_SBD 0xd14 +#define rOFDM1_CSI2 0xd18 +#define rOFDM1_CFOTracking 0xd2c +#define rOFDM1_TRxMesaure1 0xd34 +#define rOFDM1_IntfDet 0xd3c +#define rOFDM1_PseudoNoiseStateAB 0xd50 +#define rOFDM1_PseudoNoiseStateCD 0xd54 +#define rOFDM1_RxPseudoNoiseWgt 0xd58 +/* cca, parity fail */ +#define rOFDM_PHYCounter1 0xda0 +/* rate illegal, crc8 fail */ +#define rOFDM_PHYCounter2 0xda4 +/* MCS not supported */ +#define rOFDM_PHYCounter3 0xda8 +#define rOFDM_ShortCFOAB 0xdac +#define rOFDM_ShortCFOCD 0xdb0 +#define rOFDM_LongCFOAB 0xdb4 +#define rOFDM_LongCFOCD 0xdb8 +#define rOFDM_TailCFOAB 0xdbc +#define rOFDM_TailCFOCD 0xdc0 +#define rOFDM_PWMeasure1 0xdc4 +#define rOFDM_PWMeasure2 0xdc8 +#define rOFDM_BWReport 0xdcc +#define rOFDM_AGCReport 0xdd0 +#define rOFDM_RxSNR 0xdd4 +#define rOFDM_RxEVMCSI 0xdd8 +#define rOFDM_SIGReport 0xddc + +/* Page e */ +#define rTxAGC_Rate18_06 0xe00 +#define rTxAGC_Rate54_24 0xe04 +#define rTxAGC_CCK_Mcs32 0xe08 +#define rTxAGC_Mcs03_Mcs00 0xe10 +#define rTxAGC_Mcs07_Mcs04 0xe14 +#define rTxAGC_Mcs11_Mcs08 0xe18 +#define rTxAGC_Mcs15_Mcs12 0xe1c + + +/* RF Zebra 1 */ +#define rZebra1_HSSIEnable 0x0 +#define rZebra1_TRxEnable1 0x1 +#define rZebra1_TRxEnable2 0x2 +#define rZebra1_AGC 0x4 +#define rZebra1_ChargePump 0x5 +#define rZebra1_Channel 0x7 +#define rZebra1_TxGain 0x8 +#define rZebra1_TxLPF 0x9 +#define rZebra1_RxLPF 0xb +#define rZebra1_RxHPFCorner 0xc + +/* Zebra 4 */ +#define rGlobalCtrl 0 +#define rRTL8256_TxLPF 19 +#define rRTL8256_RxLPF 11 + +/* RTL8258 */ +#define rRTL8258_TxLPF 0x11 +#define rRTL8258_RxLPF 0x13 +#define rRTL8258_RSSILPF 0xa + +/* Bit Mask */ +/* Page 1 */ +#define bBBResetB 0x100 +#define bGlobalResetB 0x200 +#define bOFDMTxStart 0x4 +#define bCCKTxStart 0x8 +#define bCRC32Debug 0x100 +#define bPMACLoopback 0x10 +#define bTxLSIG 0xffffff +#define bOFDMTxRate 0xf +#define bOFDMTxReserved 0x10 +#define bOFDMTxLength 0x1ffe0 +#define bOFDMTxParity 0x20000 +#define bTxHTSIG1 0xffffff +#define bTxHTMCSRate 0x7f +#define bTxHTBW 0x80 +#define bTxHTLength 0xffff00 +#define bTxHTSIG2 0xffffff +#define bTxHTSmoothing 0x1 +#define bTxHTSounding 0x2 +#define bTxHTReserved 0x4 +#define bTxHTAggreation 0x8 +#define bTxHTSTBC 0x30 +#define bTxHTAdvanceCoding 0x40 +#define bTxHTShortGI 0x80 +#define bTxHTNumberHT_LTF 0x300 +#define bTxHTCRC8 0x3fc00 +#define bCounterReset 0x10000 +#define bNumOfOFDMTx 0xffff +#define bNumOfCCKTx 0xffff0000 +#define bTxIdleInterval 0xffff +#define bOFDMService 0xffff0000 +#define bTxMACHeader 0xffffffff +#define bTxDataInit 0xff +#define bTxHTMode 0x100 +#define bTxDataType 0x30000 +#define bTxRandomSeed 0xffffffff +#define bCCKTxPreamble 0x1 +#define bCCKTxSFD 0xffff0000 +#define bCCKTxSIG 0xff +#define bCCKTxService 0xff00 +#define bCCKLengthExt 0x8000 +#define bCCKTxLength 0xffff0000 +#define bCCKTxCRC16 0xffff +#define bCCKTxStatus 0x1 +#define bOFDMTxStatus 0x2 + +/* Page 8 */ +#define bRFMOD 0x1 +#define bJapanMode 0x2 +#define bCCKTxSC 0x30 +#define bCCKEn 0x1000000 +#define bOFDMEn 0x2000000 +#define bOFDMRxADCPhase 0x10000 +#define bOFDMTxDACPhase 0x40000 +#define bXATxAGC 0x3f +#define bXBTxAGC 0xf00 +#define bXCTxAGC 0xf000 +#define bXDTxAGC 0xf0000 +#define bPAStart 0xf0000000 +#define bTRStart 0x00f00000 +#define bRFStart 0x0000f000 +#define bBBStart 0x000000f0 +#define bBBCCKStart 0x0000000f +/* Reg)x814 */ +#define bPAEnd 0xf +#define bTREnd 0x0f000000 +#define bRFEnd 0x000f0000 +/* T2R */ +#define bCCAMask 0x000000f0 +#define bR2RCCAMask 0x00000f00 +#define bHSSI_R2TDelay 0xf8000000 +#define bHSSI_T2RDelay 0xf80000 +/* Channel gain at continue TX. */ +#define bContTxHSSI 0x400 +#define bIGFromCCK 0x200 +#define bAGCAddress 0x3f +#define bRxHPTx 0x7000 +#define bRxHPT2R 0x38000 +#define bRxHPCCKIni 0xc0000 +#define bAGCTxCode 0xc00000 +#define bAGCRxCode 0x300000 +#define b3WireDataLength 0x800 +#define b3WireAddressLength 0x400 +#define b3WireRFPowerDown 0x1 +/*#define bHWSISelect 0x8 */ +#define b5GPAPEPolarity 0x40000000 +#define b2GPAPEPolarity 0x80000000 +#define bRFSW_TxDefaultAnt 0x3 +#define bRFSW_TxOptionAnt 0x30 +#define bRFSW_RxDefaultAnt 0x300 +#define bRFSW_RxOptionAnt 0x3000 +#define bRFSI_3WireData 0x1 +#define bRFSI_3WireClock 0x2 +#define bRFSI_3WireLoad 0x4 +#define bRFSI_3WireRW 0x8 +/* 3-wire total control */ +#define bRFSI_3Wire 0xf +#define bRFSI_RFENV 0x10 +#define bRFSI_TRSW 0x20 +#define bRFSI_TRSWB 0x40 +#define bRFSI_ANTSW 0x100 +#define bRFSI_ANTSWB 0x200 +#define bRFSI_PAPE 0x400 +#define bRFSI_PAPE5G 0x800 +#define bBandSelect 0x1 +#define bHTSIG2_GI 0x80 +#define bHTSIG2_Smoothing 0x01 +#define bHTSIG2_Sounding 0x02 +#define bHTSIG2_Aggreaton 0x08 +#define bHTSIG2_STBC 0x30 +#define bHTSIG2_AdvCoding 0x40 +#define bHTSIG2_NumOfHTLTF 0x300 +#define bHTSIG2_CRC8 0x3fc +#define bHTSIG1_MCS 0x7f +#define bHTSIG1_BandWidth 0x80 +#define bHTSIG1_HTLength 0xffff +#define bLSIG_Rate 0xf +#define bLSIG_Reserved 0x10 +#define bLSIG_Length 0x1fffe +#define bLSIG_Parity 0x20 +#define bCCKRxPhase 0x4 +/* LSSI "read" address */ +#define bLSSIReadAddress 0x3f000000 +/* LSSI "read" edge signal */ +#define bLSSIReadEdge 0x80000000 +#define bLSSIReadBackData 0xfff +#define bLSSIReadOKFlag 0x1000 +/* 0: 44 MHz, 1: 88MHz */ +#define bCCKSampleRate 0x8 + +#define bRegulator0Standby 0x1 +#define bRegulatorPLLStandby 0x2 +#define bRegulator1Standby 0x4 +#define bPLLPowerUp 0x8 +#define bDPLLPowerUp 0x10 +#define bDA10PowerUp 0x20 +#define bAD7PowerUp 0x200 +#define bDA6PowerUp 0x2000 +#define bXtalPowerUp 0x4000 +#define b40MDClkPowerUP 0x8000 +#define bDA6DebugMode 0x20000 +#define bDA6Swing 0x380000 +#define bADClkPhase 0x4000000 +#define b80MClkDelay 0x18000000 +#define bAFEWatchDogEnable 0x20000000 +#define bXtalCap 0x0f000000 +#define bXtalCap01 0xc0000000 +#define bXtalCap23 0x3 +#define bXtalCap92x 0x0f000000 +#define bIntDifClkEnable 0x400 +#define bExtSigClkEnable 0x800 +#define bBandgapMbiasPowerUp 0x10000 +#define bAD11SHGain 0xc0000 +#define bAD11InputRange 0x700000 +#define bAD11OPCurrent 0x3800000 +#define bIPathLoopback 0x4000000 +#define bQPathLoopback 0x8000000 +#define bAFELoopback 0x10000000 +#define bDA10Swing 0x7e0 +#define bDA10Reverse 0x800 +#define bDAClkSource 0x1000 +#define bAD7InputRange 0x6000 +#define bAD7Gain 0x38000 +#define bAD7OutputCMMode 0x40000 +#define bAD7InputCMMode 0x380000 +#define bAD7Current 0xc00000 +#define bRegulatorAdjust 0x7000000 +#define bAD11PowerUpAtTx 0x1 +#define bDA10PSAtTx 0x10 +#define bAD11PowerUpAtRx 0x100 +#define bDA10PSAtRx 0x1000 + +#define bCCKRxAGCFormat 0x200 + +#define bPSDFFTSamplepPoint 0xc000 +#define bPSDAverageNum 0x3000 +#define bIQPathControl 0xc00 +#define bPSDFreq 0x3ff +#define bPSDAntennaPath 0x30 +#define bPSDIQSwitch 0x40 +#define bPSDRxTrigger 0x400000 +#define bPSDTxTrigger 0x80000000 +#define bPSDSineToneScale 0x7f000000 +#define bPSDReport 0xffff + +/* Page 8 */ +#define bOFDMTxSC 0x30000000 +#define bCCKTxOn 0x1 +#define bOFDMTxOn 0x2 +/* Reset debug page and also HWord, LWord */ +#define bDebugPage 0xfff +/* Reset debug page and LWord */ +#define bDebugItem 0xff +#define bAntL 0x10 +#define bAntNonHT 0x100 +#define bAntHT1 0x1000 +#define bAntHT2 0x10000 +#define bAntHT1S1 0x100000 +#define bAntNonHTS1 0x1000000 + +/* Page a */ +#define bCCKBBMode 0x3 +#define bCCKTxPowerSaving 0x80 +#define bCCKRxPowerSaving 0x40 +#define bCCKSideBand 0x10 +#define bCCKScramble 0x8 +#define bCCKAntDiversity 0x8000 +#define bCCKCarrierRecovery 0x4000 +#define bCCKTxRate 0x3000 +#define bCCKDCCancel 0x0800 +#define bCCKISICancel 0x0400 +#define bCCKMatchFilter 0x0200 +#define bCCKEqualizer 0x0100 +#define bCCKPreambleDetect 0x800000 +#define bCCKFastFalseCCA 0x400000 +#define bCCKChEstStart 0x300000 +#define bCCKCCACount 0x080000 +#define bCCKcs_lim 0x070000 +#define bCCKBistMode 0x80000000 +#define bCCKCCAMask 0x40000000 +#define bCCKTxDACPhase 0x4 +/* r_rx_clk */ +#define bCCKRxADCPhase 0x20000000 +#define bCCKr_cp_mode0 0x0100 +#define bCCKTxDCOffset 0xf0 +#define bCCKRxDCOffset 0xf +#define bCCKCCAMode 0xc000 +#define bCCKFalseCS_lim 0x3f00 +#define bCCKCS_ratio 0xc00000 +#define bCCKCorgBit_sel 0x300000 +#define bCCKPD_lim 0x0f0000 +#define bCCKNewCCA 0x80000000 +#define bCCKRxHPofIG 0x8000 +#define bCCKRxIG 0x7f00 +#define bCCKLNAPolarity 0x800000 +#define bCCKRx1stGain 0x7f0000 +/* CCK Rx Initial gain polarity */ +#define bCCKRFExtend 0x20000000 +#define bCCKRxAGCSatLevel 0x1f000000 +#define bCCKRxAGCSatCount 0xe0 +/* AGCSAmp_dly */ +#define bCCKRxRFSettle 0x1f +#define bCCKFixedRxAGC 0x8000 +/*#define bCCKRxAGCFormat 0x4000 remove to HSSI register 0x824 */ +#define bCCKAntennaPolarity 0x2000 +#define bCCKTxFilterType 0x0c00 +#define bCCKRxAGCReportType 0x0300 +#define bCCKRxDAGCEn 0x80000000 +#define bCCKRxDAGCPeriod 0x20000000 +#define bCCKRxDAGCSatLevel 0x1f000000 +#define bCCKTimingRecovery 0x800000 +#define bCCKTxC0 0x3f0000 +#define bCCKTxC1 0x3f000000 +#define bCCKTxC2 0x3f +#define bCCKTxC3 0x3f00 +#define bCCKTxC4 0x3f0000 +#define bCCKTxC5 0x3f000000 +#define bCCKTxC6 0x3f +#define bCCKTxC7 0x3f00 +#define bCCKDebugPort 0xff0000 +#define bCCKDACDebug 0x0f000000 +#define bCCKFalseAlarmEnable 0x8000 +#define bCCKFalseAlarmRead 0x4000 +#define bCCKTRSSI 0x7f +#define bCCKRxAGCReport 0xfe +#define bCCKRxReport_AntSel 0x80000000 +#define bCCKRxReport_MFOff 0x40000000 +#define bCCKRxRxReport_SQLoss 0x20000000 +#define bCCKRxReport_Pktloss 0x10000000 +#define bCCKRxReport_Lockedbit 0x08000000 +#define bCCKRxReport_RateError 0x04000000 +#define bCCKRxReport_RxRate 0x03000000 +#define bCCKRxFACounterLower 0xff +#define bCCKRxFACounterUpper 0xff000000 +#define bCCKRxHPAGCStart 0xe000 +#define bCCKRxHPAGCFinal 0x1c00 + +#define bCCKRxFalseAlarmEnable 0x8000 +#define bCCKFACounterFreeze 0x4000 + +#define bCCKTxPathSel 0x10000000 +#define bCCKDefaultRxPath 0xc000000 +#define bCCKOptionRxPath 0x3000000 + +/* Page c */ +#define bNumOfSTF 0x3 +#define bShift_L 0xc0 +#define bGI_TH 0xc +#define bRxPathA 0x1 +#define bRxPathB 0x2 +#define bRxPathC 0x4 +#define bRxPathD 0x8 +#define bTxPathA 0x1 +#define bTxPathB 0x2 +#define bTxPathC 0x4 +#define bTxPathD 0x8 +#define bTRSSIFreq 0x200 +#define bADCBackoff 0x3000 +#define bDFIRBackoff 0xc000 +#define bTRSSILatchPhase 0x10000 +#define bRxIDCOffset 0xff +#define bRxQDCOffset 0xff00 +#define bRxDFIRMode 0x1800000 +#define bRxDCNFType 0xe000000 +#define bRXIQImb_A 0x3ff +#define bRXIQImb_B 0xfc00 +#define bRXIQImb_C 0x3f0000 +#define bRXIQImb_D 0xffc00000 +#define bDC_dc_Notch 0x60000 +#define bRxNBINotch 0x1f000000 +#define bPD_TH 0xf +#define bPD_TH_Opt2 0xc000 +#define bPWED_TH 0x700 +#define bIfMF_Win_L 0x800 +#define bPD_Option 0x1000 +#define bMF_Win_L 0xe000 +#define bBW_Search_L 0x30000 +#define bwin_enh_L 0xc0000 +#define bBW_TH 0x700000 +#define bED_TH2 0x3800000 +#define bBW_option 0x4000000 +#define bRatio_TH 0x18000000 +#define bWindow_L 0xe0000000 +#define bSBD_Option 0x1 +#define bFrame_TH 0x1c +#define bFS_Option 0x60 +#define bDC_Slope_check 0x80 +#define bFGuard_Counter_DC_L 0xe00 +#define bFrame_Weight_Short 0x7000 +#define bSub_Tune 0xe00000 +#define bFrame_DC_Length 0xe000000 +#define bSBD_start_offset 0x30000000 +#define bFrame_TH_2 0x7 +#define bFrame_GI2_TH 0x38 +#define bGI2_Sync_en 0x40 +#define bSarch_Short_Early 0x300 +#define bSarch_Short_Late 0xc00 +#define bSarch_GI2_Late 0x70000 +#define bCFOAntSum 0x1 +#define bCFOAcc 0x2 +#define bCFOStartOffset 0xc +#define bCFOLookBack 0x70 +#define bCFOSumWeight 0x80 +#define bDAGCEnable 0x10000 +#define bTXIQImb_A 0x3ff +#define bTXIQImb_B 0xfc00 +#define bTXIQImb_C 0x3f0000 +#define bTXIQImb_D 0xffc00000 +#define bTxIDCOffset 0xff +#define bTxQDCOffset 0xff00 +#define bTxDFIRMode 0x10000 +#define bTxPesudoNoiseOn 0x4000000 +#define bTxPesudoNoise_A 0xff +#define bTxPesudoNoise_B 0xff00 +#define bTxPesudoNoise_C 0xff0000 +#define bTxPesudoNoise_D 0xff000000 +#define bCCADropOption 0x20000 +#define bCCADropThres 0xfff00000 +#define bEDCCA_H 0xf +#define bEDCCA_L 0xf0 +#define bLambda_ED 0x300 +#define bRxInitialGain 0x7f +#define bRxAntDivEn 0x80 +#define bRxAGCAddressForLNA 0x7f00 +#define bRxHighPowerFlow 0x8000 +#define bRxAGCFreezeThres 0xc0000 +#define bRxFreezeStep_AGC1 0x300000 +#define bRxFreezeStep_AGC2 0xc00000 +#define bRxFreezeStep_AGC3 0x3000000 +#define bRxFreezeStep_AGC0 0xc000000 +#define bRxRssi_Cmp_En 0x10000000 +#define bRxQuickAGCEn 0x20000000 +#define bRxAGCFreezeThresMode 0x40000000 +#define bRxOverFlowCheckType 0x80000000 +#define bRxAGCShift 0x7f +#define bTRSW_Tri_Only 0x80 +#define bPowerThres 0x300 +#define bRxAGCEn 0x1 +#define bRxAGCTogetherEn 0x2 +#define bRxAGCMin 0x4 +#define bRxHP_Ini 0x7 +#define bRxHP_TRLNA 0x70 +#define bRxHP_RSSI 0x700 +#define bRxHP_BBP1 0x7000 +#define bRxHP_BBP2 0x70000 +#define bRxHP_BBP3 0x700000 +/* The threshold for high power */ +#define bRSSI_H 0x7f0000 +/* The threshold for ant diversity */ +#define bRSSI_Gen 0x7f000000 +#define bRxSettle_TRSW 0x7 +#define bRxSettle_LNA 0x38 +#define bRxSettle_RSSI 0x1c0 +#define bRxSettle_BBP 0xe00 +#define bRxSettle_RxHP 0x7000 +#define bRxSettle_AntSW_RSSI 0x38000 +#define bRxSettle_AntSW 0xc0000 +#define bRxProcessTime_DAGC 0x300000 +#define bRxSettle_HSSI 0x400000 +#define bRxProcessTime_BBPPW 0x800000 +#define bRxAntennaPowerShift 0x3000000 +#define bRSSITableSelect 0xc000000 +#define bRxHP_Final 0x7000000 +#define bRxHTSettle_BBP 0x7 +#define bRxHTSettle_HSSI 0x8 +#define bRxHTSettle_RxHP 0x70 +#define bRxHTSettle_BBPPW 0x80 +#define bRxHTSettle_Idle 0x300 +#define bRxHTSettle_Reserved 0x1c00 +#define bRxHTRxHPEn 0x8000 +#define bRxHTAGCFreezeThres 0x30000 +#define bRxHTAGCTogetherEn 0x40000 +#define bRxHTAGCMin 0x80000 +#define bRxHTAGCEn 0x100000 +#define bRxHTDAGCEn 0x200000 +#define bRxHTRxHP_BBP 0x1c00000 +#define bRxHTRxHP_Final 0xe0000000 +#define bRxPWRatioTH 0x3 +#define bRxPWRatioEn 0x4 +#define bRxMFHold 0x3800 +#define bRxPD_Delay_TH1 0x38 +#define bRxPD_Delay_TH2 0x1c0 +#define bRxPD_DC_COUNT_MAX 0x600 +/*#define bRxMF_Hold 0x3800*/ +#define bRxPD_Delay_TH 0x8000 +#define bRxProcess_Delay 0xf0000 +#define bRxSearchrange_GI2_Early 0x700000 +#define bRxFrame_Guard_Counter_L 0x3800000 +#define bRxSGI_Guard_L 0xc000000 +#define bRxSGI_Search_L 0x30000000 +#define bRxSGI_TH 0xc0000000 +#define bDFSCnt0 0xff +#define bDFSCnt1 0xff00 +#define bDFSFlag 0xf0000 + +#define bMFWeightSum 0x300000 +#define bMinIdxTH 0x7f000000 + +#define bDAFormat 0x40000 + +#define bTxChEmuEnable 0x01000000 + +#define bTRSWIsolation_A 0x7f +#define bTRSWIsolation_B 0x7f00 +#define bTRSWIsolation_C 0x7f0000 +#define bTRSWIsolation_D 0x7f000000 + +#define bExtLNAGain 0x7c00 + +/* Page d */ +#define bSTBCEn 0x4 +#define bAntennaMapping 0x10 +#define bNss 0x20 +#define bCFOAntSumD 0x200 +#define bPHYCounterReset 0x8000000 +#define bCFOReportGet 0x4000000 +#define bOFDMContinueTx 0x10000000 +#define bOFDMSingleCarrier 0x20000000 +#define bOFDMSingleTone 0x40000000 +/*#define bRxPath1 0x01 +#define bRxPath2 0x02 +#define bRxPath3 0x04 +#define bRxPath4 0x08 +#define bTxPath1 0x10 +#define bTxPath2 0x20*/ +#define bHTDetect 0x100 +#define bCFOEn 0x10000 +#define bCFOValue 0xfff00000 +#define bSigTone_Re 0x3f +#define bSigTone_Im 0x7f00 +#define bCounter_CCA 0xffff +#define bCounter_ParityFail 0xffff0000 +#define bCounter_RateIllegal 0xffff +#define bCounter_CRC8Fail 0xffff0000 +#define bCounter_MCSNoSupport 0xffff +#define bCounter_FastSync 0xffff +#define bShortCFO 0xfff +/* total */ +#define bShortCFOTLength 12 +/* fraction */ +#define bShortCFOFLength 11 +#define bLongCFO 0x7ff +#define bLongCFOTLength 11 +#define bLongCFOFLength 11 +#define bTailCFO 0x1fff +#define bTailCFOTLength 13 +#define bTailCFOFLength 12 + +#define bmax_en_pwdB 0xffff +#define bCC_power_dB 0xffff0000 +#define bnoise_pwdB 0xffff +#define bPowerMeasTLength 10 +#define bPowerMeasFLength 3 +#define bRx_HT_BW 0x1 +#define bRxSC 0x6 +#define bRx_HT 0x8 + +#define bNB_intf_det_on 0x1 +#define bIntf_win_len_cfg 0x30 +#define bNB_Intf_TH_cfg 0x1c0 + +#define bRFGain 0x3f +#define bTableSel 0x40 +#define bTRSW 0x80 + +#define bRxSNR_A 0xff +#define bRxSNR_B 0xff00 +#define bRxSNR_C 0xff0000 +#define bRxSNR_D 0xff000000 +#define bSNREVMTLength 8 +#define bSNREVMFLength 1 + +#define bCSI1st 0xff +#define bCSI2nd 0xff00 +#define bRxEVM1st 0xff0000 +#define bRxEVM2nd 0xff000000 + +#define bSIGEVM 0xff +#define bPWDB 0xff00 +#define bSGIEN 0x10000 + +#define bSFactorQAM1 0xf +#define bSFactorQAM2 0xf0 +#define bSFactorQAM3 0xf00 +#define bSFactorQAM4 0xf000 +#define bSFactorQAM5 0xf0000 +#define bSFactorQAM6 0xf0000 +#define bSFactorQAM7 0xf00000 +#define bSFactorQAM8 0xf000000 +#define bSFactorQAM9 0xf0000000 +#define bCSIScheme 0x100000 + +#define bNoiseLvlTopSet 0x3 +#define bChSmooth 0x4 +#define bChSmoothCfg1 0x38 +#define bChSmoothCfg2 0x1c0 +#define bChSmoothCfg3 0xe00 +#define bChSmoothCfg4 0x7000 +#define bMRCMode 0x800000 +#define bTHEVMCfg 0x7000000 + +#define bLoopFitType 0x1 +#define bUpdCFO 0x40 +#define bUpdCFOOffData 0x80 +#define bAdvUpdCFO 0x100 +#define bAdvTimeCtrl 0x800 +#define bUpdClko 0x1000 +#define bFC 0x6000 +#define bTrackingMode 0x8000 +#define bPhCmpEnable 0x10000 +#define bUpdClkoLTF 0x20000 +#define bComChCFO 0x40000 +#define bCSIEstiMode 0x80000 +#define bAdvUpdEqz 0x100000 +#define bUChCfg 0x7000000 +#define bUpdEqz 0x8000000 + +/* Page e */ +#define bTxAGCRate18_06 0x7f7f7f7f +#define bTxAGCRate54_24 0x7f7f7f7f +#define bTxAGCRateMCS32 0x7f +#define bTxAGCRateCCK 0x7f00 +#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f +#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f +#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f +#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f + + +/* Rx Pseduo noise */ +#define bRxPesudoNoiseOn 0x20000000 +#define bRxPesudoNoise_A 0xff +#define bRxPesudoNoise_B 0xff00 +#define bRxPesudoNoise_C 0xff0000 +#define bRxPesudoNoise_D 0xff000000 +#define bPesudoNoiseState_A 0xffff +#define bPesudoNoiseState_B 0xffff0000 +#define bPesudoNoiseState_C 0xffff +#define bPesudoNoiseState_D 0xffff0000 + +/* RF Zebra 1 */ +#define bZebra1_HSSIEnable 0x8 +#define bZebra1_TRxControl 0xc00 +#define bZebra1_TRxGainSetting 0x07f +#define bZebra1_RxCorner 0xc00 +#define bZebra1_TxChargePump 0x38 +#define bZebra1_RxChargePump 0x7 +#define bZebra1_ChannelNum 0xf80 +#define bZebra1_TxLPFBW 0x400 +#define bZebra1_RxLPFBW 0x600 + +/* Zebra4 */ +#define bRTL8256RegModeCtrl1 0x100 +#define bRTL8256RegModeCtrl0 0x40 +#define bRTL8256_TxLPFBW 0x18 +#define bRTL8256_RxLPFBW 0x600 + +//RTL8258 +#define bRTL8258_TxLPFBW 0xc +#define bRTL8258_RxLPFBW 0xc00 +#define bRTL8258_RSSILPFBW 0xc0 + +/* byte endable for sb_write */ +#define bByte0 0x1 +#define bByte1 0x2 +#define bByte2 0x4 +#define bByte3 0x8 +#define bWord0 0x3 +#define bWord1 0xc +#define bDWord 0xf + +/* for PutRegsetting & GetRegSetting BitMask */ +#define bMaskByte0 0xff +#define bMaskByte1 0xff00 +#define bMaskByte2 0xff0000 +#define bMaskByte3 0xff000000 +#define bMaskHWord 0xffff0000 +#define bMaskLWord 0x0000ffff +#define bMaskDWord 0xffffffff + +/* for PutRFRegsetting & GetRFRegSetting BitMask */ +#define bMask12Bits 0xfff + +#define bEnable 0x1 +#define bDisable 0x0 + +#define LeftAntenna 0x0 +#define RightAntenna 0x1 + +/* 500 ms */ +#define tCheckTxStatus 500 +/* 100 ms */ +#define tUpdateRxCounter 100 + +#define rateCCK 0 +#define rateOFDM 1 +#define rateHT 2 + +/* define Register-End */ +#define bPMAC_End 0x1ff +#define bFPGAPHY0_End 0x8ff +#define bFPGAPHY1_End 0x9ff +#define bCCKPHY0_End 0xaff +#define bOFDMPHY0_End 0xcff +#define bOFDMPHY1_End 0xdff + +/*#define max debug item in each debug page +#define bMaxItem_FPGA_PHY0 0x9 +#define bMaxItem_FPGA_PHY1 0x3 +#define bMaxItem_PHY_11B 0x16 +#define bMaxItem_OFDM_PHY0 0x29 +#define bMaxItem_OFDM_PHY1 0x0 */ + +#define bPMACControl 0x0 +#define bWMACControl 0x1 +#define bWNICControl 0x2 + +#define PathA 0x0 +#define PathB 0x1 +#define PathC 0x2 +#define PathD 0x3 + +#define rRTL8256RxMixerPole 0xb +#define bZebraRxMixerPole 0x6 +#define rRTL8256TxBBOPBias 0x9 +#define bRTL8256TxBBOPBias 0x400 +#define rRTL8256TxBBBW 19 +#define bRTL8256TxBBBW 0x18 + + +#endif /* __INC_HAL8190PCIPHYREG_H */ diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_cam.c b/drivers/staging/rtl8192e/rtl8192e/rtl_cam.c new file mode 100644 index 000000000000..baf3b6342e44 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_cam.c @@ -0,0 +1,304 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * Based on the r8180 driver, which is: + * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ +#include "rtl_core.h" +#include "r8192E_phy.h" +#include "r8192E_phyreg.h" +#include "r8190P_rtl8256.h" /* RTL8225 Radio frontend */ +#include "r8192E_cmdpkt.h" + +extern int hwwep; +void CamResetAllEntry(struct net_device *dev) +{ + u32 ulcommand = 0; + + ulcommand |= BIT31|BIT30; + write_nic_dword(dev, RWCAM, ulcommand); +} + +void write_cam(struct net_device *dev, u8 addr, u32 data) +{ + write_nic_dword(dev, WCAMI, data); + write_nic_dword(dev, RWCAM, BIT31|BIT16|(addr&0xff)); +} + +u32 read_cam(struct net_device *dev, u8 addr) +{ + write_nic_dword(dev, RWCAM, 0x80000000|(addr&0xff)); + return read_nic_dword(dev, 0xa8); +} + +void EnableHWSecurityConfig8192(struct net_device *dev) +{ + u8 SECR_value = 0x0; + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + SECR_value = SCR_TxEncEnable | SCR_RxDecEnable; + if (((KEY_TYPE_WEP40 == ieee->pairwise_key_type) || + (KEY_TYPE_WEP104 == ieee->pairwise_key_type)) && + (priv->rtllib->auth_mode != 2)) { + SECR_value |= SCR_RxUseDK; + SECR_value |= SCR_TxUseDK; + } else if ((ieee->iw_mode == IW_MODE_ADHOC) && + (ieee->pairwise_key_type & (KEY_TYPE_CCMP | + KEY_TYPE_TKIP))) { + SECR_value |= SCR_RxUseDK; + SECR_value |= SCR_TxUseDK; + } + + + ieee->hwsec_active = 1; + if ((ieee->pHTInfo->IOTAction&HT_IOT_ACT_PURE_N_MODE) || !hwwep) { + ieee->hwsec_active = 0; + SECR_value &= ~SCR_RxDecEnable; + } + + RT_TRACE(COMP_SEC, "%s:, hwsec:%d, pairwise_key:%d, SECR_value:%x\n", + __func__, ieee->hwsec_active, ieee->pairwise_key_type, + SECR_value); + write_nic_byte(dev, SECR, SECR_value); +} + +void set_swcam(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, + u8 *MacAddr, u8 DefaultKey, u32 *KeyContent, u8 is_mesh) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + RT_TRACE(COMP_DBG, "===========>%s():EntryNo is %d,KeyIndex is " + "%d,KeyType is %d,is_mesh is %d\n", __func__, EntryNo, + KeyIndex, KeyType, is_mesh); + if (!is_mesh) { + ieee->swcamtable[EntryNo].bused = true; + ieee->swcamtable[EntryNo].key_index = KeyIndex; + ieee->swcamtable[EntryNo].key_type = KeyType; + memcpy(ieee->swcamtable[EntryNo].macaddr, MacAddr, 6); + ieee->swcamtable[EntryNo].useDK = DefaultKey; + memcpy(ieee->swcamtable[EntryNo].key_buf, (u8 *)KeyContent, 16); + } +} + +void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, + u8 *MacAddr, u8 DefaultKey, u32 *KeyContent) +{ + u32 TargetCommand = 0; + u32 TargetContent = 0; + u16 usConfig = 0; + u8 i; + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + enum rt_rf_power_state rtState; + rtState = priv->rtllib->eRFPowerState; + if (priv->rtllib->PowerSaveControl.bInactivePs) { + if (rtState == eRfOff) { + if (priv->rtllib->RfOffReason > RF_CHANGE_BY_IPS) { + RT_TRACE(COMP_ERR, "%s(): RF is OFF.\n", + __func__); + return ; + } else { + down(&priv->rtllib->ips_sem); + IPSLeave(dev); + up(&priv->rtllib->ips_sem); + } + } + } + priv->rtllib->is_set_key = true; + if (EntryNo >= TOTAL_CAM_ENTRY) + RT_TRACE(COMP_ERR, "cam entry exceeds in setKey()\n"); + + RT_TRACE(COMP_SEC, "====>to setKey(), dev:%p, EntryNo:%d, KeyIndex:%d," + "KeyType:%d, MacAddr %pM\n", dev, EntryNo, KeyIndex, + KeyType, MacAddr); + + if (DefaultKey) + usConfig |= BIT15 | (KeyType<<2); + else + usConfig |= BIT15 | (KeyType<<2) | KeyIndex; + + + for (i = 0; i < CAM_CONTENT_COUNT; i++) { + TargetCommand = i + CAM_CONTENT_COUNT * EntryNo; + TargetCommand |= BIT31|BIT16; + + if (i == 0) { + TargetContent = (u32)(*(MacAddr+0)) << 16 | + (u32)(*(MacAddr+1)) << 24 | + (u32)usConfig; + + write_nic_dword(dev, WCAMI, TargetContent); + write_nic_dword(dev, RWCAM, TargetCommand); + } else if (i == 1) { + TargetContent = (u32)(*(MacAddr+2)) | + (u32)(*(MacAddr+3)) << 8 | + (u32)(*(MacAddr+4)) << 16 | + (u32)(*(MacAddr+5)) << 24; + write_nic_dword(dev, WCAMI, TargetContent); + write_nic_dword(dev, RWCAM, TargetCommand); + } else { + if (KeyContent != NULL) { + write_nic_dword(dev, WCAMI, + (u32)(*(KeyContent+i-2))); + write_nic_dword(dev, RWCAM, TargetCommand); + udelay(100); + } + } + } + RT_TRACE(COMP_SEC, "=========>after set key, usconfig:%x\n", usConfig); +} + +void CAM_read_entry(struct net_device *dev, u32 iIndex) +{ + u32 target_command = 0; + u32 target_content = 0; + u8 entry_i = 0; + u32 ulStatus; + s32 i = 100; + for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) { + target_command = entry_i+CAM_CONTENT_COUNT*iIndex; + target_command = target_command | BIT31; + + while ((i--) >= 0) { + ulStatus = read_nic_dword(dev, RWCAM); + if (ulStatus & BIT31) + continue; + else + break; + } + write_nic_dword(dev, RWCAM, target_command); + RT_TRACE(COMP_SEC, "CAM_read_entry(): WRITE A0: %x\n", + target_command); + target_content = read_nic_dword(dev, RCAMO); + RT_TRACE(COMP_SEC, "CAM_read_entry(): WRITE A8: %x\n", + target_content); + } + printk(KERN_INFO "\n"); +} + +void CamRestoreAllEntry(struct net_device *dev) +{ + u8 EntryId = 0; + struct r8192_priv *priv = rtllib_priv(dev); + u8 *MacAddr = priv->rtllib->current_network.bssid; + + static u8 CAM_CONST_ADDR[4][6] = { + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} + }; + static u8 CAM_CONST_BROAD[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + }; + + RT_TRACE(COMP_SEC, "CamRestoreAllEntry:\n"); + + + if ((priv->rtllib->pairwise_key_type == KEY_TYPE_WEP40) || + (priv->rtllib->pairwise_key_type == KEY_TYPE_WEP104)) { + + for (EntryId = 0; EntryId < 4; EntryId++) { + MacAddr = CAM_CONST_ADDR[EntryId]; + if (priv->rtllib->swcamtable[EntryId].bused) { + setKey(dev, EntryId , EntryId, + priv->rtllib->pairwise_key_type, MacAddr, + 0, (u32 *)(&priv->rtllib->swcamtable + [EntryId].key_buf[0])); + } + } + + } else if (priv->rtllib->pairwise_key_type == KEY_TYPE_TKIP) { + if (priv->rtllib->iw_mode == IW_MODE_ADHOC) { + setKey(dev, 4, 0, priv->rtllib->pairwise_key_type, + (u8 *)dev->dev_addr, 0, + (u32 *)(&priv->rtllib->swcamtable[4].key_buf[0])); + } else { + setKey(dev, 4, 0, priv->rtllib->pairwise_key_type, + MacAddr, 0, + (u32 *)(&priv->rtllib->swcamtable[4].key_buf[0])); + } + + } else if (priv->rtllib->pairwise_key_type == KEY_TYPE_CCMP) { + if (priv->rtllib->iw_mode == IW_MODE_ADHOC) { + setKey(dev, 4, 0, + priv->rtllib->pairwise_key_type, + (u8 *)dev->dev_addr, 0, + (u32 *)(&priv->rtllib->swcamtable[4]. + key_buf[0])); + } else { + setKey(dev, 4, 0, + priv->rtllib->pairwise_key_type, MacAddr, + 0, (u32 *)(&priv->rtllib->swcamtable[4]. + key_buf[0])); + } + } + + if (priv->rtllib->group_key_type == KEY_TYPE_TKIP) { + MacAddr = CAM_CONST_BROAD; + for (EntryId = 1; EntryId < 4; EntryId++) { + if (priv->rtllib->swcamtable[EntryId].bused) { + setKey(dev, EntryId, EntryId, + priv->rtllib->group_key_type, + MacAddr, 0, + (u32 *)(&priv->rtllib->swcamtable[EntryId].key_buf[0]) + ); + } + } + if (priv->rtllib->iw_mode == IW_MODE_ADHOC) { + if (priv->rtllib->swcamtable[0].bused) { + setKey(dev, 0, 0, + priv->rtllib->group_key_type, + CAM_CONST_ADDR[0], 0, + (u32 *)(&priv->rtllib->swcamtable[0].key_buf[0]) + ); + } else { + RT_TRACE(COMP_ERR, "===>%s():ERR!! ADHOC TKIP " + ",but 0 entry is have no data\n", + __func__); + return; + } + } + } else if (priv->rtllib->group_key_type == KEY_TYPE_CCMP) { + MacAddr = CAM_CONST_BROAD; + for (EntryId = 1; EntryId < 4; EntryId++) { + if (priv->rtllib->swcamtable[EntryId].bused) { + setKey(dev, EntryId , EntryId, + priv->rtllib->group_key_type, + MacAddr, 0, + (u32 *)(&priv->rtllib->swcamtable[EntryId].key_buf[0])); + } + } + + if (priv->rtllib->iw_mode == IW_MODE_ADHOC) { + if (priv->rtllib->swcamtable[0].bused) { + setKey(dev, 0 , 0, + priv->rtllib->group_key_type, + CAM_CONST_ADDR[0], 0, + (u32 *)(&priv->rtllib->swcamtable[0].key_buf[0])); + } else { + RT_TRACE(COMP_ERR, "===>%s():ERR!! ADHOC CCMP ," + "but 0 entry is have no data\n", + __func__); + return; + } + } + } +} diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_cam.h b/drivers/staging/rtl8192e/rtl8192e/rtl_cam.h new file mode 100644 index 000000000000..fa607f98b172 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_cam.h @@ -0,0 +1,46 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * Based on the r8180 driver, which is: + * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ +#ifndef _RTL_CAM_H +#define _RTL_CAM_H + +#include <linux/types.h> +struct net_device; + +void CamResetAllEntry(struct net_device *dev); +void EnableHWSecurityConfig8192(struct net_device *dev); +void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, + u8 *MacAddr, u8 DefaultKey, u32 *KeyContent); +void set_swcam(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, + u8 *MacAddr, u8 DefaultKey, u32 *KeyContent, u8 is_mesh); +void CamPrintDbgReg(struct net_device *dev); + +u32 read_cam(struct net_device *dev, u8 addr); +void write_cam(struct net_device *dev, u8 addr, u32 data); + +void CamRestoreAllEntry(struct net_device *dev); + +void CAM_read_entry(struct net_device *dev, u32 iIndex); + +#endif diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_core.c b/drivers/staging/rtl8192e/rtl8192e/rtl_core.c new file mode 100644 index 000000000000..351504fb775c --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_core.c @@ -0,0 +1,3136 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * Based on the r8180 driver, which is: + * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ +#undef RX_DONT_PASS_UL +#undef DEBUG_EPROM +#undef DEBUG_RX_VERBOSE +#undef DUMMY_RX +#undef DEBUG_ZERO_RX +#undef DEBUG_RX_SKB +#undef DEBUG_TX_FRAG +#undef DEBUG_RX_FRAG +#undef DEBUG_TX_FILLDESC +#undef DEBUG_TX +#undef DEBUG_IRQ +#undef DEBUG_RX +#undef DEBUG_RXALLOC +#undef DEBUG_REGISTERS +#undef DEBUG_RING +#undef DEBUG_IRQ_TASKLET +#undef DEBUG_TX_ALLOC +#undef DEBUG_TX_DESC + +#include <linux/uaccess.h> +#include <linux/pci.h> +#include <linux/vmalloc.h> +#include "rtl_core.h" +#include "r8192E_phy.h" +#include "r8192E_phyreg.h" +#include "r8190P_rtl8256.h" +#include "r8192E_cmdpkt.h" + +#include "rtl_wx.h" +#include "rtl_dm.h" + +#include "rtl_pm.h" + +int hwwep = 1; +static int channels = 0x3fff; +static char *ifname = "wlan%d"; + + +static struct rtl819x_ops rtl819xp_ops = { + .nic_type = NIC_8192E, + .get_eeprom_size = rtl8192_get_eeprom_size, + .init_adapter_variable = rtl8192_InitializeVariables, + .initialize_adapter = rtl8192_adapter_start, + .link_change = rtl8192_link_change, + .tx_fill_descriptor = rtl8192_tx_fill_desc, + .tx_fill_cmd_descriptor = rtl8192_tx_fill_cmd_desc, + .rx_query_status_descriptor = rtl8192_rx_query_status_desc, + .rx_command_packet_handler = NULL, + .stop_adapter = rtl8192_halt_adapter, + .update_ratr_table = rtl8192_update_ratr_table, + .irq_enable = rtl8192_EnableInterrupt, + .irq_disable = rtl8192_DisableInterrupt, + .irq_clear = rtl8192_ClearInterrupt, + .rx_enable = rtl8192_enable_rx, + .tx_enable = rtl8192_enable_tx, + .interrupt_recognized = rtl8192_interrupt_recognized, + .TxCheckStuckHandler = rtl8192_HalTxCheckStuck, + .RxCheckStuckHandler = rtl8192_HalRxCheckStuck, +}; + +static struct pci_device_id rtl8192_pci_id_tbl[] __devinitdata = { + {RTL_PCI_DEVICE(0x10ec, 0x8192, rtl819xp_ops)}, + {RTL_PCI_DEVICE(0x07aa, 0x0044, rtl819xp_ops)}, + {RTL_PCI_DEVICE(0x07aa, 0x0047, rtl819xp_ops)}, + {} +}; + +MODULE_DEVICE_TABLE(pci, rtl8192_pci_id_tbl); + +static int __devinit rtl8192_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *id); +static void __devexit rtl8192_pci_disconnect(struct pci_dev *pdev); + +static struct pci_driver rtl8192_pci_driver = { + .name = DRV_NAME, /* Driver name */ + .id_table = rtl8192_pci_id_tbl, /* PCI_ID table */ + .probe = rtl8192_pci_probe, /* probe fn */ + .remove = __devexit_p(rtl8192_pci_disconnect), /* remove fn */ + .suspend = rtl8192E_suspend, /* PM suspend fn */ + .resume = rtl8192E_resume, /* PM resume fn */ +}; + +/**************************************************************************** + -----------------------------IO STUFF------------------------- +*****************************************************************************/ +static bool PlatformIOCheckPageLegalAndGetRegMask(u32 u4bPage, u8 *pu1bPageMask) +{ + bool bReturn = false; + + *pu1bPageMask = 0xfe; + + switch (u4bPage) { + case 1: case 2: case 3: case 4: + case 8: case 9: case 10: case 12: case 13: + bReturn = true; + *pu1bPageMask = 0xf0; + break; + + default: + bReturn = false; + break; + } + + return bReturn; +} + +void write_nic_io_byte(struct net_device *dev, int x, u8 y) +{ + u32 u4bPage = (x >> 8); + u8 u1PageMask = 0; + bool bIsLegalPage = false; + + if (u4bPage == 0) { + outb(y&0xff, dev->base_addr + x); + + } else { + bIsLegalPage = PlatformIOCheckPageLegalAndGetRegMask(u4bPage, + &u1PageMask); + if (bIsLegalPage) { + u8 u1bPsr = read_nic_io_byte(dev, PSR); + + write_nic_io_byte(dev, PSR, ((u1bPsr & u1PageMask) | + (u8)u4bPage)); + write_nic_io_byte(dev, (x & 0xff), y); + write_nic_io_byte(dev, PSR, (u1bPsr & u1PageMask)); + } + } +} + +void write_nic_io_word(struct net_device *dev, int x, u16 y) +{ + u32 u4bPage = (x >> 8); + u8 u1PageMask = 0; + bool bIsLegalPage = false; + + if (u4bPage == 0) { + outw(y, dev->base_addr + x); + } else { + bIsLegalPage = PlatformIOCheckPageLegalAndGetRegMask(u4bPage, + &u1PageMask); + if (bIsLegalPage) { + u8 u1bPsr = read_nic_io_byte(dev, PSR); + + write_nic_io_byte(dev, PSR, ((u1bPsr & u1PageMask) | + (u8)u4bPage)); + write_nic_io_word(dev, (x & 0xff), y); + write_nic_io_byte(dev, PSR, (u1bPsr & u1PageMask)); + + } + } +} + +void write_nic_io_dword(struct net_device *dev, int x, u32 y) +{ + u32 u4bPage = (x >> 8); + u8 u1PageMask = 0; + bool bIsLegalPage = false; + + if (u4bPage == 0) { + outl(y, dev->base_addr + x); + } else { + bIsLegalPage = PlatformIOCheckPageLegalAndGetRegMask(u4bPage, + &u1PageMask); + if (bIsLegalPage) { + u8 u1bPsr = read_nic_io_byte(dev, PSR); + + write_nic_io_byte(dev, PSR, ((u1bPsr & u1PageMask) | + (u8)u4bPage)); + write_nic_io_dword(dev, (x & 0xff), y); + write_nic_io_byte(dev, PSR, (u1bPsr & u1PageMask)); + } + } +} + +u8 read_nic_io_byte(struct net_device *dev, int x) +{ + u32 u4bPage = (x >> 8); + u8 u1PageMask = 0; + bool bIsLegalPage = false; + u8 Data = 0; + + if (u4bPage == 0) { + return 0xff&inb(dev->base_addr + x); + } else { + bIsLegalPage = PlatformIOCheckPageLegalAndGetRegMask(u4bPage, + &u1PageMask); + if (bIsLegalPage) { + u8 u1bPsr = read_nic_io_byte(dev, PSR); + + write_nic_io_byte(dev, PSR, ((u1bPsr & u1PageMask) | + (u8)u4bPage)); + Data = read_nic_io_byte(dev, (x & 0xff)); + write_nic_io_byte(dev, PSR, (u1bPsr & u1PageMask)); + } + } + + return Data; +} + +u16 read_nic_io_word(struct net_device *dev, int x) +{ + u32 u4bPage = (x >> 8); + u8 u1PageMask = 0; + bool bIsLegalPage = false; + u16 Data = 0; + + if (u4bPage == 0) { + return inw(dev->base_addr + x); + } else { + bIsLegalPage = PlatformIOCheckPageLegalAndGetRegMask(u4bPage, + &u1PageMask); + if (bIsLegalPage) { + u8 u1bPsr = read_nic_io_byte(dev, PSR); + + write_nic_io_byte(dev, PSR, ((u1bPsr & u1PageMask) | + (u8)u4bPage)); + Data = read_nic_io_word(dev, (x & 0xff)); + write_nic_io_byte(dev, PSR, (u1bPsr & u1PageMask)); + + } + } + + return Data; +} + +u32 read_nic_io_dword(struct net_device *dev, int x) +{ + u32 u4bPage = (x >> 8); + u8 u1PageMask = 0; + bool bIsLegalPage = false; + u32 Data = 0; + + if (u4bPage == 0) { + return inl(dev->base_addr + x); + } else { + bIsLegalPage = PlatformIOCheckPageLegalAndGetRegMask(u4bPage, + &u1PageMask); + if (bIsLegalPage) { + u8 u1bPsr = read_nic_io_byte(dev, PSR); + + write_nic_io_byte(dev, PSR, ((u1bPsr & u1PageMask) | + (u8)u4bPage)); + Data = read_nic_io_dword(dev, (x & 0xff)); + write_nic_io_byte(dev, PSR, (u1bPsr & u1PageMask)); + + } + } + + return Data; +} + +u8 read_nic_byte(struct net_device *dev, int x) +{ + return 0xff & readb((u8 __iomem *)dev->mem_start + x); +} + +u32 read_nic_dword(struct net_device *dev, int x) +{ + return readl((u8 __iomem *)dev->mem_start + x); +} + +u16 read_nic_word(struct net_device *dev, int x) +{ + return readw((u8 __iomem *)dev->mem_start + x); +} + +void write_nic_byte(struct net_device *dev, int x, u8 y) +{ + writeb(y, (u8 __iomem *)dev->mem_start + x); + + udelay(20); +} + +void write_nic_dword(struct net_device *dev, int x, u32 y) +{ + writel(y, (u8 __iomem *)dev->mem_start + x); + + udelay(20); +} + +void write_nic_word(struct net_device *dev, int x, u16 y) +{ + writew(y, (u8 __iomem *)dev->mem_start + x); + + udelay(20); +} + +/**************************************************************************** + -----------------------------GENERAL FUNCTION------------------------- +*****************************************************************************/ +bool MgntActSet_RF_State(struct net_device *dev, + enum rt_rf_power_state StateToSet, + RT_RF_CHANGE_SOURCE ChangeSource, + bool ProtectOrNot) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + bool bActionAllowed = false; + bool bConnectBySSID = false; + enum rt_rf_power_state rtState; + u16 RFWaitCounter = 0; + unsigned long flag; + RT_TRACE((COMP_PS | COMP_RF), "===>MgntActSet_RF_State(): " + "StateToSet(%d)\n", StateToSet); + + ProtectOrNot = false; + + + if (!ProtectOrNot) { + while (true) { + spin_lock_irqsave(&priv->rf_ps_lock, flag); + if (priv->RFChangeInProgress) { + spin_unlock_irqrestore(&priv->rf_ps_lock, flag); + RT_TRACE((COMP_PS | COMP_RF), + "MgntActSet_RF_State(): RF Change in " + "progress! Wait to set..StateToSet" + "(%d).\n", StateToSet); + + while (priv->RFChangeInProgress) { + RFWaitCounter++; + RT_TRACE((COMP_PS | COMP_RF), + "MgntActSet_RF_State(): Wait 1" + " ms (%d times)...\n", + RFWaitCounter); + mdelay(1); + + if (RFWaitCounter > 100) { + RT_TRACE(COMP_ERR, "MgntActSet_" + "RF_State(): Wait too " + "logn to set RF\n"); + return false; + } + } + } else { + priv->RFChangeInProgress = true; + spin_unlock_irqrestore(&priv->rf_ps_lock, flag); + break; + } + } + } + + rtState = priv->rtllib->eRFPowerState; + + switch (StateToSet) { + case eRfOn: + priv->rtllib->RfOffReason &= (~ChangeSource); + + if ((ChangeSource == RF_CHANGE_BY_HW) && + (priv->bHwRadioOff == true)) + priv->bHwRadioOff = false; + + if (!priv->rtllib->RfOffReason) { + priv->rtllib->RfOffReason = 0; + bActionAllowed = true; + + + if (rtState == eRfOff && + ChangeSource >= RF_CHANGE_BY_HW) + bConnectBySSID = true; + } else { + RT_TRACE((COMP_PS | COMP_RF), "MgntActSet_RF_State - " + "eRfon reject pMgntInfo->RfOffReason= 0x%x," + " ChangeSource=0x%X\n", + priv->rtllib->RfOffReason, ChangeSource); + } + + break; + + case eRfOff: + + if ((priv->rtllib->iw_mode == IW_MODE_INFRA) || + (priv->rtllib->iw_mode == IW_MODE_ADHOC)) { + if ((priv->rtllib->RfOffReason > RF_CHANGE_BY_IPS) || + (ChangeSource > RF_CHANGE_BY_IPS)) { + if (ieee->state == RTLLIB_LINKED) + priv->blinked_ingpio = true; + else + priv->blinked_ingpio = false; + rtllib_MgntDisconnect(priv->rtllib, + disas_lv_ss); + } + } + if ((ChangeSource == RF_CHANGE_BY_HW) && + (priv->bHwRadioOff == false)) + priv->bHwRadioOff = true; + priv->rtllib->RfOffReason |= ChangeSource; + bActionAllowed = true; + break; + + case eRfSleep: + priv->rtllib->RfOffReason |= ChangeSource; + bActionAllowed = true; + break; + + default: + break; + } + + if (bActionAllowed) { + RT_TRACE((COMP_PS | COMP_RF), "MgntActSet_RF_State(): Action is" + " allowed.... StateToSet(%d), RfOffReason(%#X)\n", + StateToSet, priv->rtllib->RfOffReason); + PHY_SetRFPowerState(dev, StateToSet); + if (StateToSet == eRfOn) { + + if (bConnectBySSID && (priv->blinked_ingpio == true)) { + queue_delayed_work_rsl(ieee->wq, + &ieee->associate_procedure_wq, 0); + priv->blinked_ingpio = false; + } + } + } else { + RT_TRACE((COMP_PS | COMP_RF), "MgntActSet_RF_State(): " + "Action is rejected.... StateToSet(%d), ChangeSource" + "(%#X), RfOffReason(%#X)\n", StateToSet, ChangeSource, + priv->rtllib->RfOffReason); + } + + if (!ProtectOrNot) { + spin_lock_irqsave(&priv->rf_ps_lock, flag); + priv->RFChangeInProgress = false; + spin_unlock_irqrestore(&priv->rf_ps_lock, flag); + } + + RT_TRACE((COMP_PS | COMP_RF), "<===MgntActSet_RF_State()\n"); + return bActionAllowed; +} + + +static short rtl8192_get_nic_desc_num(struct net_device *dev, int prio) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtl8192_tx_ring *ring = &priv->tx_ring[prio]; + + /* For now, we reserved two free descriptor as a safety boundary + * between the tail and the head + */ + if ((prio == MGNT_QUEUE) && (skb_queue_len(&ring->queue) > 10)) + RT_TRACE(COMP_DBG, "-----[%d]---------ring->idx=%d " + "queue_len=%d---------\n", prio, ring->idx, + skb_queue_len(&ring->queue)); + return skb_queue_len(&ring->queue); +} + +static short rtl8192_check_nic_enough_desc(struct net_device *dev, int prio) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtl8192_tx_ring *ring = &priv->tx_ring[prio]; + + if (ring->entries - skb_queue_len(&ring->queue) >= 2) + return 1; + return 0; +} + +void rtl8192_tx_timeout(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + schedule_work(&priv->reset_wq); + printk(KERN_INFO "TXTIMEOUT"); +} + +void rtl8192_irq_enable(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + priv->irq_enabled = 1; + + priv->ops->irq_enable(dev); +} + +void rtl8192_irq_disable(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + + priv->ops->irq_disable(dev); + + priv->irq_enabled = 0; +} + +void rtl8192_set_chan(struct net_device *dev, short ch) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + + RT_TRACE(COMP_CH, "=====>%s()====ch:%d\n", __func__, ch); + if (priv->chan_forced) + return; + + priv->chan = ch; + + if (priv->rf_set_chan) + priv->rf_set_chan(dev, priv->chan); +} + +void rtl8192_update_cap(struct net_device *dev, u16 cap) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_network *net = &priv->rtllib->current_network; + bool ShortPreamble; + + if (cap & WLAN_CAPABILITY_SHORT_PREAMBLE) { + if (priv->dot11CurrentPreambleMode != PREAMBLE_SHORT) { + ShortPreamble = true; + priv->dot11CurrentPreambleMode = PREAMBLE_SHORT; + RT_TRACE(COMP_DBG, "%s(): WLAN_CAPABILITY_SHORT_" + "PREAMBLE\n", __func__); + priv->rtllib->SetHwRegHandler(dev, HW_VAR_ACK_PREAMBLE, + (unsigned char *)&ShortPreamble); + } + } else { + if (priv->dot11CurrentPreambleMode != PREAMBLE_LONG) { + ShortPreamble = false; + priv->dot11CurrentPreambleMode = PREAMBLE_LONG; + RT_TRACE(COMP_DBG, "%s(): WLAN_CAPABILITY_LONG_" + "PREAMBLE\n", __func__); + priv->rtllib->SetHwRegHandler(dev, HW_VAR_ACK_PREAMBLE, + (unsigned char *)&ShortPreamble); + } + } + + if (net->mode & (IEEE_G|IEEE_N_24G)) { + u8 slot_time_val; + u8 CurSlotTime = priv->slot_time; + + if ((cap & WLAN_CAPABILITY_SHORT_SLOT_TIME) && + (!priv->rtllib->pHTInfo->bCurrentRT2RTLongSlotTime)) { + if (CurSlotTime != SHORT_SLOT_TIME) { + slot_time_val = SHORT_SLOT_TIME; + priv->rtllib->SetHwRegHandler(dev, + HW_VAR_SLOT_TIME, &slot_time_val); + } + } else { + if (CurSlotTime != NON_SHORT_SLOT_TIME) { + slot_time_val = NON_SHORT_SLOT_TIME; + priv->rtllib->SetHwRegHandler(dev, + HW_VAR_SLOT_TIME, &slot_time_val); + } + } + } +} + +static struct rtllib_qos_parameters def_qos_parameters = { + {3, 3, 3, 3}, + {7, 7, 7, 7}, + {2, 2, 2, 2}, + {0, 0, 0, 0}, + {0, 0, 0, 0} +}; + +static void rtl8192_update_beacon(void *data) +{ + struct r8192_priv *priv = container_of_work_rsl(data, struct r8192_priv, + update_beacon_wq.work); + struct net_device *dev = priv->rtllib->dev; + struct rtllib_device *ieee = priv->rtllib; + struct rtllib_network *net = &ieee->current_network; + + if (ieee->pHTInfo->bCurrentHTSupport) + HTUpdateSelfAndPeerSetting(ieee, net); + ieee->pHTInfo->bCurrentRT2RTLongSlotTime = + net->bssht.bdRT2RTLongSlotTime; + ieee->pHTInfo->RT2RT_HT_Mode = net->bssht.RT2RT_HT_Mode; + rtl8192_update_cap(dev, net->capability); +} + +int WDCAPARA_ADD[] = {EDCAPARA_BE, EDCAPARA_BK, EDCAPARA_VI, EDCAPARA_VO}; + +static void rtl8192_qos_activate(void *data) +{ + struct r8192_priv *priv = container_of_work_rsl(data, struct r8192_priv, + qos_activate); + struct net_device *dev = priv->rtllib->dev; + int i; + + mutex_lock(&priv->mutex); + if (priv->rtllib->state != RTLLIB_LINKED) + goto success; + RT_TRACE(COMP_QOS, "qos active process with associate response " + "received\n"); + + for (i = 0; i < QOS_QUEUE_NUM; i++) { + priv->rtllib->SetHwRegHandler(dev, HW_VAR_AC_PARAM, (u8 *)(&i)); + } + +success: + mutex_unlock(&priv->mutex); +} + +static int rtl8192_qos_handle_probe_response(struct r8192_priv *priv, + int active_network, + struct rtllib_network *network) +{ + int ret = 0; + u32 size = sizeof(struct rtllib_qos_parameters); + + if (priv->rtllib->state != RTLLIB_LINKED) + return ret; + + if ((priv->rtllib->iw_mode != IW_MODE_INFRA)) + return ret; + + if (network->flags & NETWORK_HAS_QOS_MASK) { + if (active_network && + (network->flags & NETWORK_HAS_QOS_PARAMETERS)) + network->qos_data.active = network->qos_data.supported; + + if ((network->qos_data.active == 1) && (active_network == 1) && + (network->flags & NETWORK_HAS_QOS_PARAMETERS) && + (network->qos_data.old_param_count != + network->qos_data.param_count)) { + network->qos_data.old_param_count = + network->qos_data.param_count; + priv->rtllib->wmm_acm = network->qos_data.wmm_acm; + queue_work_rsl(priv->priv_wq, &priv->qos_activate); + RT_TRACE(COMP_QOS, "QoS parameters change call " + "qos_activate\n"); + } + } else { + memcpy(&priv->rtllib->current_network.qos_data.parameters, + &def_qos_parameters, size); + + if ((network->qos_data.active == 1) && (active_network == 1)) { + queue_work_rsl(priv->priv_wq, &priv->qos_activate); + RT_TRACE(COMP_QOS, "QoS was disabled call qos_" + "activate\n"); + } + network->qos_data.active = 0; + network->qos_data.supported = 0; + } + + return 0; +} + +static int rtl8192_handle_beacon(struct net_device *dev, + struct rtllib_beacon *beacon, + struct rtllib_network *network) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + rtl8192_qos_handle_probe_response(priv, 1, network); + + queue_delayed_work_rsl(priv->priv_wq, &priv->update_beacon_wq, 0); + return 0; + +} + +static int rtl8192_qos_association_resp(struct r8192_priv *priv, + struct rtllib_network *network) +{ + int ret = 0; + unsigned long flags; + u32 size = sizeof(struct rtllib_qos_parameters); + int set_qos_param = 0; + + if ((priv == NULL) || (network == NULL)) + return ret; + + if (priv->rtllib->state != RTLLIB_LINKED) + return ret; + + if ((priv->rtllib->iw_mode != IW_MODE_INFRA)) + return ret; + + spin_lock_irqsave(&priv->rtllib->lock, flags); + if (network->flags & NETWORK_HAS_QOS_PARAMETERS) { + memcpy(&priv->rtllib->current_network.qos_data.parameters, + &network->qos_data.parameters, + sizeof(struct rtllib_qos_parameters)); + priv->rtllib->current_network.qos_data.active = 1; + priv->rtllib->wmm_acm = network->qos_data.wmm_acm; + set_qos_param = 1; + priv->rtllib->current_network.qos_data.old_param_count = + priv->rtllib->current_network.qos_data.param_count; + priv->rtllib->current_network.qos_data.param_count = + network->qos_data.param_count; + } else { + memcpy(&priv->rtllib->current_network.qos_data.parameters, + &def_qos_parameters, size); + priv->rtllib->current_network.qos_data.active = 0; + priv->rtllib->current_network.qos_data.supported = 0; + set_qos_param = 1; + } + + spin_unlock_irqrestore(&priv->rtllib->lock, flags); + + RT_TRACE(COMP_QOS, "%s: network->flags = %d,%d\n", __func__, + network->flags, priv->rtllib->current_network.qos_data.active); + if (set_qos_param == 1) { + dm_init_edca_turbo(priv->rtllib->dev); + queue_work_rsl(priv->priv_wq, &priv->qos_activate); + } + return ret; +} + +static int rtl8192_handle_assoc_response(struct net_device *dev, + struct rtllib_assoc_response_frame *resp, + struct rtllib_network *network) +{ + struct r8192_priv *priv = rtllib_priv(dev); + rtl8192_qos_association_resp(priv, network); + return 0; +} + +static void rtl8192_prepare_beacon(struct r8192_priv *priv) +{ + struct net_device *dev = priv->rtllib->dev; + struct sk_buff *pskb = NULL, *pnewskb = NULL; + struct cb_desc *tcb_desc = NULL; + struct rtl8192_tx_ring *ring = NULL; + struct tx_desc *pdesc = NULL; + + ring = &priv->tx_ring[BEACON_QUEUE]; + pskb = __skb_dequeue(&ring->queue); + if (pskb) + kfree_skb(pskb); + + pnewskb = rtllib_get_beacon(priv->rtllib); + if (!pnewskb) + return; + + tcb_desc = (struct cb_desc *)(pnewskb->cb + 8); + tcb_desc->queue_index = BEACON_QUEUE; + tcb_desc->data_rate = 2; + tcb_desc->RATRIndex = 7; + tcb_desc->bTxDisableRateFallBack = 1; + tcb_desc->bTxUseDriverAssingedRate = 1; + skb_push(pnewskb, priv->rtllib->tx_headroom); + + pdesc = &ring->desc[0]; + priv->ops->tx_fill_descriptor(dev, pdesc, tcb_desc, pnewskb); + __skb_queue_tail(&ring->queue, pnewskb); + pdesc->OWN = 1; + + return; +} + +static void rtl8192_stop_beacon(struct net_device *dev) +{ +} + +void rtl8192_config_rate(struct net_device *dev, u16 *rate_config) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_network *net; + u8 i = 0, basic_rate = 0; + net = &priv->rtllib->current_network; + + for (i = 0; i < net->rates_len; i++) { + basic_rate = net->rates[i] & 0x7f; + switch (basic_rate) { + case MGN_1M: + *rate_config |= RRSR_1M; + break; + case MGN_2M: + *rate_config |= RRSR_2M; + break; + case MGN_5_5M: + *rate_config |= RRSR_5_5M; + break; + case MGN_11M: + *rate_config |= RRSR_11M; + break; + case MGN_6M: + *rate_config |= RRSR_6M; + break; + case MGN_9M: + *rate_config |= RRSR_9M; + break; + case MGN_12M: + *rate_config |= RRSR_12M; + break; + case MGN_18M: + *rate_config |= RRSR_18M; + break; + case MGN_24M: + *rate_config |= RRSR_24M; + break; + case MGN_36M: + *rate_config |= RRSR_36M; + break; + case MGN_48M: + *rate_config |= RRSR_48M; + break; + case MGN_54M: + *rate_config |= RRSR_54M; + break; + } + } + + for (i = 0; i < net->rates_ex_len; i++) { + basic_rate = net->rates_ex[i] & 0x7f; + switch (basic_rate) { + case MGN_1M: + *rate_config |= RRSR_1M; + break; + case MGN_2M: + *rate_config |= RRSR_2M; + break; + case MGN_5_5M: + *rate_config |= RRSR_5_5M; + break; + case MGN_11M: + *rate_config |= RRSR_11M; + break; + case MGN_6M: + *rate_config |= RRSR_6M; + break; + case MGN_9M: + *rate_config |= RRSR_9M; + break; + case MGN_12M: + *rate_config |= RRSR_12M; + break; + case MGN_18M: + *rate_config |= RRSR_18M; + break; + case MGN_24M: + *rate_config |= RRSR_24M; + break; + case MGN_36M: + *rate_config |= RRSR_36M; + break; + case MGN_48M: + *rate_config |= RRSR_48M; + break; + case MGN_54M: + *rate_config |= RRSR_54M; + break; + } + } +} + +static void rtl8192_refresh_supportrate(struct r8192_priv *priv) +{ + struct rtllib_device *ieee = priv->rtllib; + if (ieee->mode == WIRELESS_MODE_N_24G || + ieee->mode == WIRELESS_MODE_N_5G) { + memcpy(ieee->Regdot11HTOperationalRateSet, + ieee->RegHTSuppRateSet, 16); + memcpy(ieee->Regdot11TxHTOperationalRateSet, + ieee->RegHTSuppRateSet, 16); + + } else { + memset(ieee->Regdot11HTOperationalRateSet, 0, 16); + } + return; +} + +static u8 rtl8192_getSupportedWireleeMode(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u8 ret = 0; + + switch (priv->rf_chip) { + case RF_8225: + case RF_8256: + case RF_6052: + case RF_PSEUDO_11N: + ret = (WIRELESS_MODE_N_24G|WIRELESS_MODE_G | WIRELESS_MODE_B); + break; + case RF_8258: + ret = (WIRELESS_MODE_A | WIRELESS_MODE_N_5G); + break; + default: + ret = WIRELESS_MODE_B; + break; + } + return ret; +} + +void rtl8192_SetWirelessMode(struct net_device *dev, u8 wireless_mode) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u8 bSupportMode = rtl8192_getSupportedWireleeMode(dev); + + if ((wireless_mode == WIRELESS_MODE_AUTO) || + ((wireless_mode & bSupportMode) == 0)) { + if (bSupportMode & WIRELESS_MODE_N_24G) { + wireless_mode = WIRELESS_MODE_N_24G; + } else if (bSupportMode & WIRELESS_MODE_N_5G) { + wireless_mode = WIRELESS_MODE_N_5G; + } else if ((bSupportMode & WIRELESS_MODE_A)) { + wireless_mode = WIRELESS_MODE_A; + } else if ((bSupportMode & WIRELESS_MODE_G)) { + wireless_mode = WIRELESS_MODE_G; + } else if ((bSupportMode & WIRELESS_MODE_B)) { + wireless_mode = WIRELESS_MODE_B; + } else { + RT_TRACE(COMP_ERR, "%s(), No valid wireless mode " + "supported (%x)!!!\n", __func__, bSupportMode); + wireless_mode = WIRELESS_MODE_B; + } + } + + if ((wireless_mode & (WIRELESS_MODE_B | WIRELESS_MODE_G)) == + (WIRELESS_MODE_G | WIRELESS_MODE_B)) + wireless_mode = WIRELESS_MODE_G; + + priv->rtllib->mode = wireless_mode; + + ActUpdateChannelAccessSetting(dev, wireless_mode, + &priv->ChannelAccessSetting); + + if ((wireless_mode == WIRELESS_MODE_N_24G) || + (wireless_mode == WIRELESS_MODE_N_5G)) { + priv->rtllib->pHTInfo->bEnableHT = 1; + RT_TRACE(COMP_DBG, "%s(), wireless_mode:%x, bEnableHT = 1\n", + __func__, wireless_mode); + } else { + priv->rtllib->pHTInfo->bEnableHT = 0; + RT_TRACE(COMP_DBG, "%s(), wireless_mode:%x, bEnableHT = 0\n", + __func__, wireless_mode); + } + + RT_TRACE(COMP_INIT, "Current Wireless Mode is %x\n", wireless_mode); + rtl8192_refresh_supportrate(priv); +} + +static int _rtl8192_sta_up(struct net_device *dev, bool is_silent_reset) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *) + (&(priv->rtllib->PowerSaveControl)); + bool init_status = true; + priv->bDriverIsGoingToUnload = false; + priv->bdisable_nic = false; + + priv->up = 1; + priv->rtllib->ieee_up = 1; + + priv->up_first_time = 0; + RT_TRACE(COMP_INIT, "Bringing up iface"); + priv->bfirst_init = true; + init_status = priv->ops->initialize_adapter(dev); + if (init_status != true) { + RT_TRACE(COMP_ERR, "ERR!!! %s(): initialization is failed!\n", + __func__); + priv->bfirst_init = false; + return -1; + } + + RT_TRACE(COMP_INIT, "start adapter finished\n"); + RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); + priv->bfirst_init = false; + + if (priv->polling_timer_on == 0) + check_rfctrl_gpio_timer((unsigned long)dev); + + if (priv->rtllib->state != RTLLIB_LINKED) + rtllib_softmac_start_protocol(priv->rtllib, 0); + rtllib_reset_queue(priv->rtllib); + watch_dog_timer_callback((unsigned long) dev); + + if (!netif_queue_stopped(dev)) + netif_start_queue(dev); + else + netif_wake_queue(dev); + + return 0; +} + +static int rtl8192_sta_down(struct net_device *dev, bool shutdownrf) +{ + struct r8192_priv *priv = rtllib_priv(dev); + unsigned long flags = 0; + u8 RFInProgressTimeOut = 0; + + if (priv->up == 0) + return -1; + + if (priv->rtllib->rtllib_ips_leave != NULL) + priv->rtllib->rtllib_ips_leave(dev); + + if (priv->rtllib->state == RTLLIB_LINKED) + LeisurePSLeave(dev); + + priv->bDriverIsGoingToUnload = true; + priv->up = 0; + priv->rtllib->ieee_up = 0; + priv->bfirst_after_down = 1; + RT_TRACE(COMP_DOWN, "==========>%s()\n", __func__); + if (!netif_queue_stopped(dev)) + netif_stop_queue(dev); + + priv->rtllib->wpa_ie_len = 0; + kfree(priv->rtllib->wpa_ie); + priv->rtllib->wpa_ie = NULL; + CamResetAllEntry(dev); + memset(priv->rtllib->swcamtable, 0, sizeof(struct sw_cam_table) * 32); + rtl8192_irq_disable(dev); + + del_timer_sync(&priv->watch_dog_timer); + rtl8192_cancel_deferred_work(priv); + cancel_delayed_work(&priv->rtllib->hw_wakeup_wq); + + rtllib_softmac_stop_protocol(priv->rtllib, 0, true); + spin_lock_irqsave(&priv->rf_ps_lock, flags); + while (priv->RFChangeInProgress) { + spin_unlock_irqrestore(&priv->rf_ps_lock, flags); + if (RFInProgressTimeOut > 100) { + spin_lock_irqsave(&priv->rf_ps_lock, flags); + break; + } + RT_TRACE(COMP_DBG, "===>%s():RF is in progress, need to wait " + "until rf chang is done.\n", __func__); + mdelay(1); + RFInProgressTimeOut++; + spin_lock_irqsave(&priv->rf_ps_lock, flags); + } + priv->RFChangeInProgress = true; + spin_unlock_irqrestore(&priv->rf_ps_lock, flags); + priv->ops->stop_adapter(dev, false); + spin_lock_irqsave(&priv->rf_ps_lock, flags); + priv->RFChangeInProgress = false; + spin_unlock_irqrestore(&priv->rf_ps_lock, flags); + udelay(100); + memset(&priv->rtllib->current_network, 0, + offsetof(struct rtllib_network, list)); + RT_TRACE(COMP_DOWN, "<==========%s()\n", __func__); + + return 0; +} + +static void rtl8192_init_priv_handler(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + priv->rtllib->softmac_hard_start_xmit = rtl8192_hard_start_xmit; + priv->rtllib->set_chan = rtl8192_set_chan; + priv->rtllib->link_change = priv->ops->link_change; + priv->rtllib->softmac_data_hard_start_xmit = rtl8192_hard_data_xmit; + priv->rtllib->data_hard_stop = rtl8192_data_hard_stop; + priv->rtllib->data_hard_resume = rtl8192_data_hard_resume; + priv->rtllib->check_nic_enough_desc = rtl8192_check_nic_enough_desc; + priv->rtllib->get_nic_desc_num = rtl8192_get_nic_desc_num; + priv->rtllib->handle_assoc_response = rtl8192_handle_assoc_response; + priv->rtllib->handle_beacon = rtl8192_handle_beacon; + priv->rtllib->SetWirelessMode = rtl8192_SetWirelessMode; + priv->rtllib->LeisurePSLeave = LeisurePSLeave; + priv->rtllib->SetBWModeHandler = rtl8192_SetBWMode; + priv->rf_set_chan = rtl8192_phy_SwChnl; + + priv->rtllib->start_send_beacons = rtl8192e_start_beacon; + priv->rtllib->stop_send_beacons = rtl8192_stop_beacon; + + priv->rtllib->sta_wake_up = rtl8192_hw_wakeup; + priv->rtllib->enter_sleep_state = rtl8192_hw_to_sleep; + priv->rtllib->ps_is_queue_empty = rtl8192_is_tx_queue_empty; + + priv->rtllib->GetNmodeSupportBySecCfg = rtl8192_GetNmodeSupportBySecCfg; + priv->rtllib->GetHalfNmodeSupportByAPsHandler = + rtl8192_GetHalfNmodeSupportByAPs; + + priv->rtllib->SetHwRegHandler = rtl8192e_SetHwReg; + priv->rtllib->AllowAllDestAddrHandler = rtl8192_AllowAllDestAddr; + priv->rtllib->SetFwCmdHandler = NULL; + priv->rtllib->InitialGainHandler = InitialGain819xPci; + priv->rtllib->rtllib_ips_leave_wq = rtllib_ips_leave_wq; + priv->rtllib->rtllib_ips_leave = rtllib_ips_leave; + + priv->rtllib->LedControlHandler = NULL; + priv->rtllib->UpdateBeaconInterruptHandler = NULL; + + priv->rtllib->ScanOperationBackupHandler = PHY_ScanOperationBackup8192; + + priv->rtllib->rtllib_rfkill_poll = NULL; +} + +static void rtl8192_init_priv_constant(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *) + &(priv->rtllib->PowerSaveControl); + + pPSC->RegMaxLPSAwakeIntvl = 5; + + priv->RegPciASPM = 2; + + priv->RegDevicePciASPMSetting = 0x03; + + priv->RegHostPciASPMSetting = 0x02; + + priv->RegHwSwRfOffD3 = 2; + + priv->RegSupportPciASPM = 2; +} + + +static void rtl8192_init_priv_variable(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u8 i; + + priv->AcmMethod = eAcmWay2_SW; + priv->dot11CurrentPreambleMode = PREAMBLE_AUTO; + priv->rtllib->hwscan_sem_up = 1; + priv->rtllib->status = 0; + priv->H2CTxCmdSeq = 0; + priv->bDisableFrameBursting = 0; + priv->bDMInitialGainEnable = 1; + priv->polling_timer_on = 0; + priv->up_first_time = 1; + priv->blinked_ingpio = false; + priv->bDriverIsGoingToUnload = false; + priv->being_init_adapter = false; + priv->initialized_at_probe = false; + priv->sw_radio_on = true; + priv->bdisable_nic = false; + priv->bfirst_init = false; + priv->txringcount = 64; + priv->rxbuffersize = 9100; + priv->rxringcount = MAX_RX_COUNT; + priv->irq_enabled = 0; + priv->chan = 1; + priv->RegWirelessMode = WIRELESS_MODE_AUTO; + priv->RegChannelPlan = 0xf; + priv->nrxAMPDU_size = 0; + priv->nrxAMPDU_aggr_num = 0; + priv->last_rxdesc_tsf_high = 0; + priv->last_rxdesc_tsf_low = 0; + priv->rtllib->mode = WIRELESS_MODE_AUTO; + priv->rtllib->iw_mode = IW_MODE_INFRA; + priv->rtllib->bNetPromiscuousMode = false; + priv->rtllib->IntelPromiscuousModeInfo.bPromiscuousOn = false; + priv->rtllib->IntelPromiscuousModeInfo.bFilterSourceStationFrame = + false; + priv->rtllib->ieee_up = 0; + priv->retry_rts = DEFAULT_RETRY_RTS; + priv->retry_data = DEFAULT_RETRY_DATA; + priv->rtllib->rts = DEFAULT_RTS_THRESHOLD; + priv->rtllib->rate = 110; + priv->rtllib->short_slot = 1; + priv->promisc = (dev->flags & IFF_PROMISC) ? 1 : 0; + priv->bcck_in_ch14 = false; + priv->bfsync_processing = false; + priv->CCKPresentAttentuation = 0; + priv->rfa_txpowertrackingindex = 0; + priv->rfc_txpowertrackingindex = 0; + priv->CckPwEnl = 6; + priv->ScanDelay = 50; + priv->ResetProgress = RESET_TYPE_NORESET; + priv->bForcedSilentReset = 0; + priv->bDisableNormalResetCheck = false; + priv->force_reset = false; + memset(priv->rtllib->swcamtable, 0, sizeof(struct sw_cam_table) * 32); + + memset(&priv->InterruptLog, 0, sizeof(struct log_int_8190)); + priv->RxCounter = 0; + priv->rtllib->wx_set_enc = 0; + priv->bHwRadioOff = false; + priv->RegRfOff = 0; + priv->isRFOff = false; + priv->bInPowerSaveMode = false; + priv->rtllib->RfOffReason = 0; + priv->RFChangeInProgress = false; + priv->bHwRfOffAction = 0; + priv->SetRFPowerStateInProgress = false; + priv->rtllib->PowerSaveControl.bInactivePs = true; + priv->rtllib->PowerSaveControl.bIPSModeBackup = false; + priv->rtllib->PowerSaveControl.bLeisurePs = true; + priv->rtllib->PowerSaveControl.bFwCtrlLPS = false; + priv->rtllib->LPSDelayCnt = 0; + priv->rtllib->sta_sleep = LPS_IS_WAKE; + priv->rtllib->eRFPowerState = eRfOn; + + priv->txpower_checkcnt = 0; + priv->thermal_readback_index = 0; + priv->txpower_tracking_callback_cnt = 0; + priv->ccktxpower_adjustcnt_ch14 = 0; + priv->ccktxpower_adjustcnt_not_ch14 = 0; + + priv->rtllib->current_network.beacon_interval = DEFAULT_BEACONINTERVAL; + priv->rtllib->iw_mode = IW_MODE_INFRA; + priv->rtllib->active_scan = 1; + priv->rtllib->be_scan_inprogress = false; + priv->rtllib->modulation = RTLLIB_CCK_MODULATION | + RTLLIB_OFDM_MODULATION; + priv->rtllib->host_encrypt = 1; + priv->rtllib->host_decrypt = 1; + + priv->rtllib->dot11PowerSaveMode = eActive; + priv->rtllib->fts = DEFAULT_FRAG_THRESHOLD; + priv->rtllib->MaxMssDensity = 0; + priv->rtllib->MinSpaceCfg = 0; + + priv->card_type = PCI; + + priv->AcmControl = 0; + priv->pFirmware = vzalloc(sizeof(struct rt_firmware)); + if (!priv->pFirmware) + printk(KERN_ERR "rtl8193e: Unable to allocate space " + "for firmware\n"); + + skb_queue_head_init(&priv->rx_queue); + skb_queue_head_init(&priv->skb_queue); + + for (i = 0; i < MAX_QUEUE_SIZE; i++) + skb_queue_head_init(&priv->rtllib->skb_waitQ[i]); + for (i = 0; i < MAX_QUEUE_SIZE; i++) + skb_queue_head_init(&priv->rtllib->skb_aggQ[i]); +} + +static void rtl8192_init_priv_lock(struct r8192_priv *priv) +{ + spin_lock_init(&priv->fw_scan_lock); + spin_lock_init(&priv->tx_lock); + spin_lock_init(&priv->irq_lock); + spin_lock_init(&priv->irq_th_lock); + spin_lock_init(&priv->rf_ps_lock); + spin_lock_init(&priv->ps_lock); + spin_lock_init(&priv->rf_lock); + spin_lock_init(&priv->rt_h2c_lock); + sema_init(&priv->wx_sem, 1); + sema_init(&priv->rf_sem, 1); + mutex_init(&priv->mutex); +} + +static void rtl8192_init_priv_task(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + priv->priv_wq = create_workqueue(DRV_NAME); + INIT_WORK_RSL(&priv->reset_wq, (void *)rtl8192_restart, dev); + INIT_WORK_RSL(&priv->rtllib->ips_leave_wq, (void *)IPSLeave_wq, dev); + INIT_DELAYED_WORK_RSL(&priv->watch_dog_wq, + (void *)rtl819x_watchdog_wqcallback, dev); + INIT_DELAYED_WORK_RSL(&priv->txpower_tracking_wq, + (void *)dm_txpower_trackingcallback, dev); + INIT_DELAYED_WORK_RSL(&priv->rfpath_check_wq, + (void *)dm_rf_pathcheck_workitemcallback, dev); + INIT_DELAYED_WORK_RSL(&priv->update_beacon_wq, + (void *)rtl8192_update_beacon, dev); + INIT_WORK_RSL(&priv->qos_activate, (void *)rtl8192_qos_activate, dev); + INIT_DELAYED_WORK_RSL(&priv->rtllib->hw_wakeup_wq, + (void *) rtl8192_hw_wakeup_wq, dev); + INIT_DELAYED_WORK_RSL(&priv->rtllib->hw_sleep_wq, + (void *) rtl8192_hw_sleep_wq, dev); + tasklet_init(&priv->irq_rx_tasklet, + (void(*)(unsigned long))rtl8192_irq_rx_tasklet, + (unsigned long)priv); + tasklet_init(&priv->irq_tx_tasklet, + (void(*)(unsigned long))rtl8192_irq_tx_tasklet, + (unsigned long)priv); + tasklet_init(&priv->irq_prepare_beacon_tasklet, + (void(*)(unsigned long))rtl8192_prepare_beacon, + (unsigned long)priv); +} + +static short rtl8192_get_channel_map(struct net_device *dev) +{ + int i; + + struct r8192_priv *priv = rtllib_priv(dev); + if ((priv->rf_chip != RF_8225) && (priv->rf_chip != RF_8256) + && (priv->rf_chip != RF_6052)) { + RT_TRACE(COMP_ERR, "%s: unknown rf chip, can't set channel " + "map\n", __func__); + return -1; + } + + if (priv->ChannelPlan >= COUNTRY_CODE_MAX) { + printk(KERN_INFO "rtl819x_init:Error channel plan! Set to " + "default.\n"); + priv->ChannelPlan = COUNTRY_CODE_FCC; + } + RT_TRACE(COMP_INIT, "Channel plan is %d\n", priv->ChannelPlan); + Dot11d_Init(priv->rtllib); + Dot11d_Channelmap(priv->ChannelPlan, priv->rtllib); + for (i = 1; i <= 11; i++) + (priv->rtllib->active_channel_map)[i] = 1; + (priv->rtllib->active_channel_map)[12] = 2; + (priv->rtllib->active_channel_map)[13] = 2; + + return 0; +} + +static short rtl8192_init(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + memset(&(priv->stats), 0, sizeof(struct rt_stats)); + + rtl8192_init_priv_handler(dev); + rtl8192_init_priv_constant(dev); + rtl8192_init_priv_variable(dev); + rtl8192_init_priv_lock(priv); + rtl8192_init_priv_task(dev); + priv->ops->get_eeprom_size(dev); + priv->ops->init_adapter_variable(dev); + rtl8192_get_channel_map(dev); + + init_hal_dm(dev); + + init_timer(&priv->watch_dog_timer); + setup_timer(&priv->watch_dog_timer, + watch_dog_timer_callback, + (unsigned long) dev); + + init_timer(&priv->gpio_polling_timer); + setup_timer(&priv->gpio_polling_timer, + check_rfctrl_gpio_timer, + (unsigned long)dev); + + rtl8192_irq_disable(dev); + if (request_irq(dev->irq, (void *)rtl8192_interrupt_rsl, IRQF_SHARED, + dev->name, dev)) { + printk(KERN_ERR "Error allocating IRQ %d", dev->irq); + return -1; + } else { + priv->irq = dev->irq; + RT_TRACE(COMP_INIT, "IRQ %d\n", dev->irq); + } + + if (rtl8192_pci_initdescring(dev) != 0) { + printk(KERN_ERR "Endopoints initialization failed"); + free_irq(dev->irq, dev); + return -1; + } + + return 0; +} + +/*************************************************************************** + -------------------------------WATCHDOG STUFF--------------------------- +***************************************************************************/ +short rtl8192_is_tx_queue_empty(struct net_device *dev) +{ + int i = 0; + struct r8192_priv *priv = rtllib_priv(dev); + for (i = 0; i <= MGNT_QUEUE; i++) { + if ((i == TXCMD_QUEUE) || (i == HCCA_QUEUE)) + continue; + if (skb_queue_len(&(&priv->tx_ring[i])->queue) > 0) { + printk(KERN_INFO "===>tx queue is not empty:%d, %d\n", + i, skb_queue_len(&(&priv->tx_ring[i])->queue)); + return 0; + } + } + return 1; +} + +static enum reset_type rtl819x_TxCheckStuck(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u8 QueueID; + u8 ResetThreshold = NIC_SEND_HANG_THRESHOLD_POWERSAVE; + bool bCheckFwTxCnt = false; + struct rtl8192_tx_ring *ring = NULL; + struct sk_buff *skb = NULL; + struct cb_desc *tcb_desc = NULL; + unsigned long flags = 0; + + switch (priv->rtllib->ps) { + case RTLLIB_PS_DISABLED: + ResetThreshold = NIC_SEND_HANG_THRESHOLD_NORMAL; + break; + case (RTLLIB_PS_MBCAST|RTLLIB_PS_UNICAST): + ResetThreshold = NIC_SEND_HANG_THRESHOLD_POWERSAVE; + break; + default: + ResetThreshold = NIC_SEND_HANG_THRESHOLD_POWERSAVE; + break; + } + spin_lock_irqsave(&priv->irq_th_lock, flags); + for (QueueID = 0; QueueID < MAX_TX_QUEUE; QueueID++) { + if (QueueID == TXCMD_QUEUE) + continue; + + if (QueueID == BEACON_QUEUE) + continue; + + ring = &priv->tx_ring[QueueID]; + + if (skb_queue_len(&ring->queue) == 0) { + continue; + } else { + skb = (&ring->queue)->next; + tcb_desc = (struct cb_desc *)(skb->cb + + MAX_DEV_ADDR_SIZE); + tcb_desc->nStuckCount++; + bCheckFwTxCnt = true; + if (tcb_desc->nStuckCount > 1) + printk(KERN_INFO "%s: QueueID=%d tcb_desc->n" + "StuckCount=%d\n", __func__, QueueID, + tcb_desc->nStuckCount); + } + } + spin_unlock_irqrestore(&priv->irq_th_lock, flags); + + if (bCheckFwTxCnt) { + if (priv->ops->TxCheckStuckHandler(dev)) { + RT_TRACE(COMP_RESET, "TxCheckStuck(): Fw indicates no" + " Tx condition!\n"); + return RESET_TYPE_SILENT; + } + } + + return RESET_TYPE_NORESET; +} + +static enum reset_type rtl819x_RxCheckStuck(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + if (priv->ops->RxCheckStuckHandler(dev)) { + RT_TRACE(COMP_RESET, "RxStuck Condition\n"); + return RESET_TYPE_SILENT; + } + + return RESET_TYPE_NORESET; +} + +static enum reset_type rtl819x_ifcheck_resetornot(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + enum reset_type TxResetType = RESET_TYPE_NORESET; + enum reset_type RxResetType = RESET_TYPE_NORESET; + enum rt_rf_power_state rfState; + + rfState = priv->rtllib->eRFPowerState; + + if (rfState == eRfOn) + TxResetType = rtl819x_TxCheckStuck(dev); + + if (rfState == eRfOn && + (priv->rtllib->iw_mode == IW_MODE_INFRA) && + (priv->rtllib->state == RTLLIB_LINKED)) + RxResetType = rtl819x_RxCheckStuck(dev); + + if (TxResetType == RESET_TYPE_NORMAL || + RxResetType == RESET_TYPE_NORMAL) { + printk(KERN_INFO "%s(): TxResetType is %d, RxResetType is %d\n", + __func__, TxResetType, RxResetType); + return RESET_TYPE_NORMAL; + } else if (TxResetType == RESET_TYPE_SILENT || + RxResetType == RESET_TYPE_SILENT) { + printk(KERN_INFO "%s(): TxResetType is %d, RxResetType is %d\n", + __func__, TxResetType, RxResetType); + return RESET_TYPE_SILENT; + } else { + return RESET_TYPE_NORESET; + } + +} + +static void rtl819x_silentreset_mesh_bk(struct net_device *dev, u8 IsPortal) +{ +} + +static void rtl819x_ifsilentreset(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u8 reset_times = 0; + int reset_status = 0; + struct rtllib_device *ieee = priv->rtllib; + unsigned long flag; + + u8 IsPortal = 0; + + + if (priv->ResetProgress == RESET_TYPE_NORESET) { + + RT_TRACE(COMP_RESET, "=========>Reset progress!!\n"); + + priv->ResetProgress = RESET_TYPE_SILENT; + + spin_lock_irqsave(&priv->rf_ps_lock, flag); + if (priv->RFChangeInProgress) { + spin_unlock_irqrestore(&priv->rf_ps_lock, flag); + goto END; + } + priv->RFChangeInProgress = true; + priv->bResetInProgress = true; + spin_unlock_irqrestore(&priv->rf_ps_lock, flag); + +RESET_START: + + down(&priv->wx_sem); + + if (priv->rtllib->state == RTLLIB_LINKED) + LeisurePSLeave(dev); + + if (IS_NIC_DOWN(priv)) { + RT_TRACE(COMP_ERR, "%s():the driver is not up! " + "return\n", __func__); + up(&priv->wx_sem); + return ; + } + priv->up = 0; + + RT_TRACE(COMP_RESET, "%s():======>start to down the driver\n", + __func__); + mdelay(1000); + RT_TRACE(COMP_RESET, "%s():111111111111111111111111======>start" + " to down the driver\n", __func__); + + if (!netif_queue_stopped(dev)) + netif_stop_queue(dev); + + rtl8192_irq_disable(dev); + del_timer_sync(&priv->watch_dog_timer); + rtl8192_cancel_deferred_work(priv); + deinit_hal_dm(dev); + rtllib_stop_scan_syncro(ieee); + + if (ieee->state == RTLLIB_LINKED) { + SEM_DOWN_IEEE_WX(&ieee->wx_sem); + printk(KERN_INFO "ieee->state is RTLLIB_LINKED\n"); + rtllib_stop_send_beacons(priv->rtllib); + del_timer_sync(&ieee->associate_timer); + cancel_delayed_work(&ieee->associate_retry_wq); + rtllib_stop_scan(ieee); + netif_carrier_off(dev); + SEM_UP_IEEE_WX(&ieee->wx_sem); + } else { + printk(KERN_INFO "ieee->state is NOT LINKED\n"); + rtllib_softmac_stop_protocol(priv->rtllib, 0 , true); + } + + dm_backup_dynamic_mechanism_state(dev); + + up(&priv->wx_sem); + RT_TRACE(COMP_RESET, "%s():<==========down process is " + "finished\n", __func__); + + RT_TRACE(COMP_RESET, "%s():<===========up process start\n", + __func__); + reset_status = _rtl8192_up(dev, true); + + RT_TRACE(COMP_RESET, "%s():<===========up process is " + "finished\n", __func__); + if (reset_status == -1) { + if (reset_times < 3) { + reset_times++; + goto RESET_START; + } else { + RT_TRACE(COMP_ERR, " ERR!!! %s(): Reset " + "Failed!!\n", __func__); + } + } + + ieee->is_silent_reset = 1; + + spin_lock_irqsave(&priv->rf_ps_lock, flag); + priv->RFChangeInProgress = false; + spin_unlock_irqrestore(&priv->rf_ps_lock, flag); + + EnableHWSecurityConfig8192(dev); + + if (ieee->state == RTLLIB_LINKED && ieee->iw_mode == + IW_MODE_INFRA) { + ieee->set_chan(ieee->dev, + ieee->current_network.channel); + + queue_work_rsl(ieee->wq, &ieee->associate_complete_wq); + + } else if (ieee->state == RTLLIB_LINKED && ieee->iw_mode == + IW_MODE_ADHOC) { + ieee->set_chan(ieee->dev, + ieee->current_network.channel); + ieee->link_change(ieee->dev); + + notify_wx_assoc_event(ieee); + + rtllib_start_send_beacons(ieee); + + if (ieee->data_hard_resume) + ieee->data_hard_resume(ieee->dev); + netif_carrier_on(ieee->dev); + } else if (ieee->iw_mode == IW_MODE_MESH) { + rtl819x_silentreset_mesh_bk(dev, IsPortal); + } + + CamRestoreAllEntry(dev); + dm_restore_dynamic_mechanism_state(dev); +END: + priv->ResetProgress = RESET_TYPE_NORESET; + priv->reset_count++; + + priv->bForcedSilentReset = false; + priv->bResetInProgress = false; + + write_nic_byte(dev, UFWP, 1); + RT_TRACE(COMP_RESET, "Reset finished!! ====>[%d]\n", + priv->reset_count); + } +} + +static void rtl819x_update_rxcounts(struct r8192_priv *priv, u32 *TotalRxBcnNum, + u32 *TotalRxDataNum) +{ + u16 SlotIndex; + u8 i; + + *TotalRxBcnNum = 0; + *TotalRxDataNum = 0; + + SlotIndex = (priv->rtllib->LinkDetectInfo.SlotIndex++) % + (priv->rtllib->LinkDetectInfo.SlotNum); + priv->rtllib->LinkDetectInfo.RxBcnNum[SlotIndex] = + priv->rtllib->LinkDetectInfo.NumRecvBcnInPeriod; + priv->rtllib->LinkDetectInfo.RxDataNum[SlotIndex] = + priv->rtllib->LinkDetectInfo.NumRecvDataInPeriod; + for (i = 0; i < priv->rtllib->LinkDetectInfo.SlotNum; i++) { + *TotalRxBcnNum += priv->rtllib->LinkDetectInfo.RxBcnNum[i]; + *TotalRxDataNum += priv->rtllib->LinkDetectInfo.RxDataNum[i]; + } +} + + +void rtl819x_watchdog_wqcallback(void *data) +{ + struct r8192_priv *priv = container_of_dwork_rsl(data, + struct r8192_priv, watch_dog_wq); + struct net_device *dev = priv->rtllib->dev; + struct rtllib_device *ieee = priv->rtllib; + enum reset_type ResetType = RESET_TYPE_NORESET; + static u8 check_reset_cnt; + unsigned long flags; + struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *) + (&(priv->rtllib->PowerSaveControl)); + bool bBusyTraffic = false; + bool bHigherBusyTraffic = false; + bool bHigherBusyRxTraffic = false; + bool bEnterPS = false; + + if (IS_NIC_DOWN(priv) || (priv->bHwRadioOff == true)) + return; + + if (priv->rtllib->state >= RTLLIB_LINKED) { + if (priv->rtllib->CntAfterLink < 2) + priv->rtllib->CntAfterLink++; + } else { + priv->rtllib->CntAfterLink = 0; + } + + hal_dm_watchdog(dev); + + if (rtllib_act_scanning(priv->rtllib, false) == false) { + if ((ieee->iw_mode == IW_MODE_INFRA) && (ieee->state == + RTLLIB_NOLINK) && + (ieee->eRFPowerState == eRfOn) && !ieee->is_set_key && + (!ieee->proto_stoppping) && !ieee->wx_set_enc) { + if ((ieee->PowerSaveControl.ReturnPoint == + IPS_CALLBACK_NONE) && + (!ieee->bNetPromiscuousMode)) { + RT_TRACE(COMP_PS, "====================>haha: " + "IPSEnter()\n"); + IPSEnter(dev); + } + } + } + if ((ieee->state == RTLLIB_LINKED) && (ieee->iw_mode == + IW_MODE_INFRA) && (!ieee->bNetPromiscuousMode)) { + if (ieee->LinkDetectInfo.NumRxOkInPeriod > 100 || + ieee->LinkDetectInfo.NumTxOkInPeriod > 100) + bBusyTraffic = true; + + + if (ieee->LinkDetectInfo.NumRxOkInPeriod > 4000 || + ieee->LinkDetectInfo.NumTxOkInPeriod > 4000) { + bHigherBusyTraffic = true; + if (ieee->LinkDetectInfo.NumRxOkInPeriod > 5000) + bHigherBusyRxTraffic = true; + else + bHigherBusyRxTraffic = false; + } + + if (((ieee->LinkDetectInfo.NumRxUnicastOkInPeriod + + ieee->LinkDetectInfo.NumTxOkInPeriod) > 8) || + (ieee->LinkDetectInfo.NumRxUnicastOkInPeriod > 2)) + bEnterPS = false; + else + bEnterPS = true; + + if (ieee->current_network.beacon_interval < 95) + bEnterPS = false; + + if (bEnterPS) + LeisurePSEnter(dev); + else + LeisurePSLeave(dev); + + } else { + RT_TRACE(COMP_LPS, "====>no link LPS leave\n"); + LeisurePSLeave(dev); + } + + ieee->LinkDetectInfo.NumRxOkInPeriod = 0; + ieee->LinkDetectInfo.NumTxOkInPeriod = 0; + ieee->LinkDetectInfo.NumRxUnicastOkInPeriod = 0; + ieee->LinkDetectInfo.bBusyTraffic = bBusyTraffic; + + ieee->LinkDetectInfo.bHigherBusyTraffic = bHigherBusyTraffic; + ieee->LinkDetectInfo.bHigherBusyRxTraffic = bHigherBusyRxTraffic; + + if (ieee->state == RTLLIB_LINKED && ieee->iw_mode == IW_MODE_INFRA) { + u32 TotalRxBcnNum = 0; + u32 TotalRxDataNum = 0; + + rtl819x_update_rxcounts(priv, &TotalRxBcnNum, &TotalRxDataNum); + + if ((TotalRxBcnNum+TotalRxDataNum) == 0) + priv->check_roaming_cnt++; + else + priv->check_roaming_cnt = 0; + + + if (priv->check_roaming_cnt > 0) { + if (ieee->eRFPowerState == eRfOff) + RT_TRACE(COMP_ERR, "========>%s()\n", __func__); + + printk(KERN_INFO "===>%s(): AP is power off, chan:%d," + " connect another one\n", __func__, priv->chan); + + ieee->state = RTLLIB_ASSOCIATING; + + RemovePeerTS(priv->rtllib, + priv->rtllib->current_network.bssid); + ieee->is_roaming = true; + ieee->is_set_key = false; + ieee->link_change(dev); + if (ieee->LedControlHandler) + ieee->LedControlHandler(ieee->dev, + LED_CTL_START_TO_LINK); + + notify_wx_assoc_event(ieee); + + if (!(ieee->rtllib_ap_sec_type(ieee) & + (SEC_ALG_CCMP|SEC_ALG_TKIP))) + queue_delayed_work_rsl(ieee->wq, + &ieee->associate_procedure_wq, 0); + + priv->check_roaming_cnt = 0; + } + ieee->LinkDetectInfo.NumRecvBcnInPeriod = 0; + ieee->LinkDetectInfo.NumRecvDataInPeriod = 0; + + } + + spin_lock_irqsave(&priv->tx_lock, flags); + if ((check_reset_cnt++ >= 3) && (!ieee->is_roaming) && + (!priv->RFChangeInProgress) && (!pPSC->bSwRfProcessing)) { + ResetType = rtl819x_ifcheck_resetornot(dev); + check_reset_cnt = 3; + } + spin_unlock_irqrestore(&priv->tx_lock, flags); + + if (!priv->bDisableNormalResetCheck && ResetType == RESET_TYPE_NORMAL) { + priv->ResetProgress = RESET_TYPE_NORMAL; + RT_TRACE(COMP_RESET, "%s(): NOMAL RESET\n", __func__); + return; + } + + if (((priv->force_reset) || (!priv->bDisableNormalResetCheck && + ResetType == RESET_TYPE_SILENT))) + rtl819x_ifsilentreset(dev); + priv->force_reset = false; + priv->bForcedSilentReset = false; + priv->bResetInProgress = false; + RT_TRACE(COMP_TRACE, " <==RtUsbCheckForHangWorkItemCallback()\n"); +} + +void watch_dog_timer_callback(unsigned long data) +{ + struct r8192_priv *priv = rtllib_priv((struct net_device *)data); + queue_delayed_work_rsl(priv->priv_wq, &priv->watch_dog_wq, 0); + mod_timer(&priv->watch_dog_timer, jiffies + + MSECS(RTLLIB_WATCH_DOG_TIME)); +} + +/**************************************************************************** + ---------------------------- NIC TX/RX STUFF--------------------------- +*****************************************************************************/ +void rtl8192_rx_enable(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + priv->ops->rx_enable(dev); +} + +void rtl8192_tx_enable(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + + priv->ops->tx_enable(dev); + + rtllib_reset_queue(priv->rtllib); +} + + +static void rtl8192_free_rx_ring(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + int i, rx_queue_idx; + + for (rx_queue_idx = 0; rx_queue_idx < MAX_RX_QUEUE; + rx_queue_idx++) { + for (i = 0; i < priv->rxringcount; i++) { + struct sk_buff *skb = priv->rx_buf[rx_queue_idx][i]; + if (!skb) + continue; + + pci_unmap_single(priv->pdev, + *((dma_addr_t *)skb->cb), + priv->rxbuffersize, PCI_DMA_FROMDEVICE); + kfree_skb(skb); + } + + pci_free_consistent(priv->pdev, + sizeof(*priv->rx_ring[rx_queue_idx]) * + priv->rxringcount, + priv->rx_ring[rx_queue_idx], + priv->rx_ring_dma[rx_queue_idx]); + priv->rx_ring[rx_queue_idx] = NULL; + } +} + +static void rtl8192_free_tx_ring(struct net_device *dev, unsigned int prio) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtl8192_tx_ring *ring = &priv->tx_ring[prio]; + + while (skb_queue_len(&ring->queue)) { + struct tx_desc *entry = &ring->desc[ring->idx]; + struct sk_buff *skb = __skb_dequeue(&ring->queue); + + pci_unmap_single(priv->pdev, le32_to_cpu(entry->TxBuffAddr), + skb->len, PCI_DMA_TODEVICE); + kfree_skb(skb); + ring->idx = (ring->idx + 1) % ring->entries; + } + + pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries, + ring->desc, ring->dma); + ring->desc = NULL; +} + +void rtl8192_data_hard_stop(struct net_device *dev) +{ +} + + +void rtl8192_data_hard_resume(struct net_device *dev) +{ +} + +void rtl8192_hard_data_xmit(struct sk_buff *skb, struct net_device *dev, + int rate) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + int ret; + struct cb_desc *tcb_desc = (struct cb_desc *)(skb->cb + + MAX_DEV_ADDR_SIZE); + u8 queue_index = tcb_desc->queue_index; + + if ((priv->rtllib->eRFPowerState == eRfOff) || IS_NIC_DOWN(priv) || + priv->bResetInProgress) { + kfree_skb(skb); + return; + } + + assert(queue_index != TXCMD_QUEUE); + + + memcpy((unsigned char *)(skb->cb), &dev, sizeof(dev)); + skb_push(skb, priv->rtllib->tx_headroom); + ret = rtl8192_tx(dev, skb); + if (ret != 0) { + kfree_skb(skb); + }; + + if (queue_index != MGNT_QUEUE) { + priv->rtllib->stats.tx_bytes += (skb->len - + priv->rtllib->tx_headroom); + priv->rtllib->stats.tx_packets++; + } + + + return; +} + +int rtl8192_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + int ret; + struct cb_desc *tcb_desc = (struct cb_desc *)(skb->cb + + MAX_DEV_ADDR_SIZE); + u8 queue_index = tcb_desc->queue_index; + + if (queue_index != TXCMD_QUEUE) { + if ((priv->rtllib->eRFPowerState == eRfOff) || + IS_NIC_DOWN(priv) || priv->bResetInProgress) { + kfree_skb(skb); + return 0; + } + } + + memcpy((unsigned char *)(skb->cb), &dev, sizeof(dev)); + if (queue_index == TXCMD_QUEUE) { + rtl8192_tx_cmd(dev, skb); + ret = 0; + return ret; + } else { + tcb_desc->RATRIndex = 7; + tcb_desc->bTxDisableRateFallBack = 1; + tcb_desc->bTxUseDriverAssingedRate = 1; + tcb_desc->bTxEnableFwCalcDur = 1; + skb_push(skb, priv->rtllib->tx_headroom); + ret = rtl8192_tx(dev, skb); + if (ret != 0) { + kfree_skb(skb); + }; + } + + + + return ret; + +} + +static void rtl8192_tx_isr(struct net_device *dev, int prio) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + + struct rtl8192_tx_ring *ring = &priv->tx_ring[prio]; + + while (skb_queue_len(&ring->queue)) { + struct tx_desc *entry = &ring->desc[ring->idx]; + struct sk_buff *skb; + + if (prio != BEACON_QUEUE) { + if (entry->OWN) + return; + ring->idx = (ring->idx + 1) % ring->entries; + } + + skb = __skb_dequeue(&ring->queue); + pci_unmap_single(priv->pdev, le32_to_cpu(entry->TxBuffAddr), + skb->len, PCI_DMA_TODEVICE); + + kfree_skb(skb); + } + if (prio != BEACON_QUEUE) + tasklet_schedule(&priv->irq_tx_tasklet); +} + +void rtl8192_tx_cmd(struct net_device *dev, struct sk_buff *skb) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtl8192_tx_ring *ring; + struct tx_desc_cmd *entry; + unsigned int idx; + struct cb_desc *tcb_desc; + unsigned long flags; + + spin_lock_irqsave(&priv->irq_th_lock, flags); + ring = &priv->tx_ring[TXCMD_QUEUE]; + + idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries; + entry = (struct tx_desc_cmd *) &ring->desc[idx]; + + tcb_desc = (struct cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); + + priv->ops->tx_fill_cmd_descriptor(dev, entry, tcb_desc, skb); + + __skb_queue_tail(&ring->queue, skb); + spin_unlock_irqrestore(&priv->irq_th_lock, flags); + + return; +} + +short rtl8192_tx(struct net_device *dev, struct sk_buff *skb) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtl8192_tx_ring *ring; + unsigned long flags; + struct cb_desc *tcb_desc = (struct cb_desc *)(skb->cb + + MAX_DEV_ADDR_SIZE); + struct tx_desc *pdesc = NULL; + struct rtllib_hdr_1addr *header = NULL; + u16 fc = 0, type = 0, stype = 0; + bool multi_addr = false, broad_addr = false, uni_addr = false; + u8 *pda_addr = NULL; + int idx; + u32 fwinfo_size = 0; + + if (priv->bdisable_nic) { + RT_TRACE(COMP_ERR, "%s: ERR!! Nic is disabled! Can't tx packet" + " len=%d qidx=%d!!!\n", __func__, skb->len, + tcb_desc->queue_index); + return skb->len; + } + + priv->rtllib->bAwakePktSent = true; + + fwinfo_size = sizeof(struct tx_fwinfo_8190pci); + + header = (struct rtllib_hdr_1addr *)(((u8 *)skb->data) + fwinfo_size); + fc = header->frame_ctl; + type = WLAN_FC_GET_TYPE(fc); + stype = WLAN_FC_GET_STYPE(fc); + pda_addr = header->addr1; + + if (is_multicast_ether_addr(pda_addr)) + multi_addr = true; + else if (is_broadcast_ether_addr(pda_addr)) + broad_addr = true; + else + uni_addr = true; + + if (uni_addr) + priv->stats.txbytesunicast += skb->len - fwinfo_size; + else if (multi_addr) + priv->stats.txbytesmulticast += skb->len - fwinfo_size; + else + priv->stats.txbytesbroadcast += skb->len - fwinfo_size; + + spin_lock_irqsave(&priv->irq_th_lock, flags); + ring = &priv->tx_ring[tcb_desc->queue_index]; + if (tcb_desc->queue_index != BEACON_QUEUE) + idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries; + else + idx = 0; + + pdesc = &ring->desc[idx]; + if ((pdesc->OWN == 1) && (tcb_desc->queue_index != BEACON_QUEUE)) { + RT_TRACE(COMP_ERR, "No more TX desc@%d, ring->idx = %d, idx = " + "%d, skblen = 0x%x queuelen=%d", + tcb_desc->queue_index, ring->idx, idx, skb->len, + skb_queue_len(&ring->queue)); + spin_unlock_irqrestore(&priv->irq_th_lock, flags); + return skb->len; + } + + if (type == RTLLIB_FTYPE_DATA) { + if (priv->rtllib->LedControlHandler) + priv->rtllib->LedControlHandler(dev, LED_CTL_TX); + } + priv->ops->tx_fill_descriptor(dev, pdesc, tcb_desc, skb); + __skb_queue_tail(&ring->queue, skb); + pdesc->OWN = 1; + spin_unlock_irqrestore(&priv->irq_th_lock, flags); + dev->trans_start = jiffies; + + write_nic_word(dev, TPPoll, 0x01 << tcb_desc->queue_index); + return 0; +} + +static short rtl8192_alloc_rx_desc_ring(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rx_desc *entry = NULL; + int i, rx_queue_idx; + + for (rx_queue_idx = 0; rx_queue_idx < MAX_RX_QUEUE; rx_queue_idx++) { + priv->rx_ring[rx_queue_idx] = pci_alloc_consistent(priv->pdev, + sizeof(*priv->rx_ring[rx_queue_idx]) * + priv->rxringcount, + &priv->rx_ring_dma[rx_queue_idx]); + + if (!priv->rx_ring[rx_queue_idx] || + (unsigned long)priv->rx_ring[rx_queue_idx] & 0xFF) { + RT_TRACE(COMP_ERR, "Cannot allocate RX ring\n"); + return -ENOMEM; + } + + memset(priv->rx_ring[rx_queue_idx], 0, + sizeof(*priv->rx_ring[rx_queue_idx]) * + priv->rxringcount); + priv->rx_idx[rx_queue_idx] = 0; + + for (i = 0; i < priv->rxringcount; i++) { + struct sk_buff *skb = dev_alloc_skb(priv->rxbuffersize); + dma_addr_t *mapping; + entry = &priv->rx_ring[rx_queue_idx][i]; + if (!skb) + return 0; + skb->dev = dev; + priv->rx_buf[rx_queue_idx][i] = skb; + mapping = (dma_addr_t *)skb->cb; + *mapping = pci_map_single(priv->pdev, + skb_tail_pointer_rsl(skb), + priv->rxbuffersize, + PCI_DMA_FROMDEVICE); + + entry->BufferAddress = cpu_to_le32(*mapping); + + entry->Length = priv->rxbuffersize; + entry->OWN = 1; + } + + if(entry) + entry->EOR = 1; + } + return 0; +} + +static int rtl8192_alloc_tx_desc_ring(struct net_device *dev, + unsigned int prio, unsigned int entries) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + struct tx_desc *ring; + dma_addr_t dma; + int i; + + ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma); + if (!ring || (unsigned long)ring & 0xFF) { + RT_TRACE(COMP_ERR, "Cannot allocate TX ring (prio = %d)\n", + prio); + return -ENOMEM; + } + + memset(ring, 0, sizeof(*ring)*entries); + priv->tx_ring[prio].desc = ring; + priv->tx_ring[prio].dma = dma; + priv->tx_ring[prio].idx = 0; + priv->tx_ring[prio].entries = entries; + skb_queue_head_init(&priv->tx_ring[prio].queue); + + for (i = 0; i < entries; i++) + ring[i].NextDescAddress = + cpu_to_le32((u32)dma + ((i + 1) % entries) * + sizeof(*ring)); + + return 0; +} + + +short rtl8192_pci_initdescring(struct net_device *dev) +{ + u32 ret; + int i; + struct r8192_priv *priv = rtllib_priv(dev); + + ret = rtl8192_alloc_rx_desc_ring(dev); + if (ret) + return ret; + + for (i = 0; i < MAX_TX_QUEUE_COUNT; i++) { + ret = rtl8192_alloc_tx_desc_ring(dev, i, priv->txringcount); + if (ret) + goto err_free_rings; + } + + return 0; + +err_free_rings: + rtl8192_free_rx_ring(dev); + for (i = 0; i < MAX_TX_QUEUE_COUNT; i++) + if (priv->tx_ring[i].desc) + rtl8192_free_tx_ring(dev, i); + return 1; +} + +void rtl8192_pci_resetdescring(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + int i, rx_queue_idx; + unsigned long flags = 0; + + for (rx_queue_idx = 0; rx_queue_idx < MAX_RX_QUEUE; rx_queue_idx++) { + if (priv->rx_ring[rx_queue_idx]) { + struct rx_desc *entry = NULL; + for (i = 0; i < priv->rxringcount; i++) { + entry = &priv->rx_ring[rx_queue_idx][i]; + entry->OWN = 1; + } + priv->rx_idx[rx_queue_idx] = 0; + } + } + + spin_lock_irqsave(&priv->irq_th_lock, flags); + for (i = 0; i < MAX_TX_QUEUE_COUNT; i++) { + if (priv->tx_ring[i].desc) { + struct rtl8192_tx_ring *ring = &priv->tx_ring[i]; + + while (skb_queue_len(&ring->queue)) { + struct tx_desc *entry = &ring->desc[ring->idx]; + struct sk_buff *skb = + __skb_dequeue(&ring->queue); + + pci_unmap_single(priv->pdev, + le32_to_cpu(entry->TxBuffAddr), + skb->len, PCI_DMA_TODEVICE); + kfree_skb(skb); + ring->idx = (ring->idx + 1) % ring->entries; + } + ring->idx = 0; + } + } + spin_unlock_irqrestore(&priv->irq_th_lock, flags); +} + +void rtl819x_UpdateRxPktTimeStamp(struct net_device *dev, + struct rtllib_rx_stats *stats) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + + if (stats->bIsAMPDU && !stats->bFirstMPDU) + stats->mac_time = priv->LastRxDescTSF; + else + priv->LastRxDescTSF = stats->mac_time; +} + +long rtl819x_translate_todbm(struct r8192_priv *priv, u8 signal_strength_index) +{ + long signal_power; + + signal_power = (long)((signal_strength_index + 1) >> 1); + signal_power -= 95; + + return signal_power; +} + + +void +rtl819x_update_rxsignalstatistics8190pci( + struct r8192_priv *priv, + struct rtllib_rx_stats *pprevious_stats + ) +{ + int weighting = 0; + + + if (priv->stats.recv_signal_power == 0) + priv->stats.recv_signal_power = + pprevious_stats->RecvSignalPower; + + if (pprevious_stats->RecvSignalPower > priv->stats.recv_signal_power) + weighting = 5; + else if (pprevious_stats->RecvSignalPower < + priv->stats.recv_signal_power) + weighting = (-5); + priv->stats.recv_signal_power = (priv->stats.recv_signal_power * 5 + + pprevious_stats->RecvSignalPower + + weighting) / 6; +} + +void rtl819x_process_cck_rxpathsel(struct r8192_priv *priv, + struct rtllib_rx_stats *pprevious_stats) +{ +} + + +u8 rtl819x_query_rxpwrpercentage(char antpower) +{ + if ((antpower <= -100) || (antpower >= 20)) + return 0; + else if (antpower >= 0) + return 100; + else + return 100 + antpower; + +} /* QueryRxPwrPercentage */ + +u8 +rtl819x_evm_dbtopercentage( + char value + ) +{ + char ret_val; + + ret_val = value; + + if (ret_val >= 0) + ret_val = 0; + if (ret_val <= -33) + ret_val = -33; + ret_val = 0 - ret_val; + ret_val *= 3; + if (ret_val == 99) + ret_val = 100; + return ret_val; +} + +void +rtl8192_record_rxdesc_forlateruse( + struct rtllib_rx_stats *psrc_stats, + struct rtllib_rx_stats *ptarget_stats +) +{ + ptarget_stats->bIsAMPDU = psrc_stats->bIsAMPDU; + ptarget_stats->bFirstMPDU = psrc_stats->bFirstMPDU; +} + + + +static void rtl8192_rx_normal(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + struct rtllib_hdr_1addr *rtllib_hdr = NULL; + bool unicast_packet = false; + bool bLedBlinking = true; + u16 fc = 0, type = 0; + u32 skb_len = 0; + int rx_queue_idx = RX_MPDU_QUEUE; + + struct rtllib_rx_stats stats = { + .signal = 0, + .noise = -98, + .rate = 0, + .freq = RTLLIB_24GHZ_BAND, + }; + unsigned int count = priv->rxringcount; + + stats.nic_type = NIC_8192E; + + while (count--) { + struct rx_desc *pdesc = &priv->rx_ring[rx_queue_idx] + [priv->rx_idx[rx_queue_idx]]; + struct sk_buff *skb = priv->rx_buf[rx_queue_idx] + [priv->rx_idx[rx_queue_idx]]; + + if (pdesc->OWN) { + return; + } else { + struct sk_buff *new_skb; + + if (!priv->ops->rx_query_status_descriptor(dev, &stats, + pdesc, skb)) + goto done; + new_skb = dev_alloc_skb(priv->rxbuffersize); + /* if allocation of new skb failed - drop current packet + * and reuse skb */ + if (unlikely(!new_skb)) + goto done; + + pci_unmap_single(priv->pdev, + *((dma_addr_t *)skb->cb), + priv->rxbuffersize, + PCI_DMA_FROMDEVICE); + + skb_put(skb, pdesc->Length); + skb_reserve(skb, stats.RxDrvInfoSize + + stats.RxBufShift); + skb_trim(skb, skb->len - 4/*sCrcLng*/); + rtllib_hdr = (struct rtllib_hdr_1addr *)skb->data; + if (!is_broadcast_ether_addr(rtllib_hdr->addr1) && + !is_multicast_ether_addr(rtllib_hdr->addr1)) { + /* unicast packet */ + unicast_packet = true; + } + fc = le16_to_cpu(rtllib_hdr->frame_ctl); + type = WLAN_FC_GET_TYPE(fc); + if (type == RTLLIB_FTYPE_MGMT) + bLedBlinking = false; + + if (bLedBlinking) + if (priv->rtllib->LedControlHandler) + priv->rtllib->LedControlHandler(dev, + LED_CTL_RX); + + if (stats.bCRC) { + if (type != RTLLIB_FTYPE_MGMT) + priv->stats.rxdatacrcerr++; + else + priv->stats.rxmgmtcrcerr++; + } + + skb_len = skb->len; + + if (!rtllib_rx(priv->rtllib, skb, &stats)) { + dev_kfree_skb_any(skb); + } else { + priv->stats.rxok++; + if (unicast_packet) + priv->stats.rxbytesunicast += skb_len; + } + + skb = new_skb; + skb->dev = dev; + + priv->rx_buf[rx_queue_idx][priv->rx_idx[rx_queue_idx]] = + skb; + *((dma_addr_t *) skb->cb) = pci_map_single(priv->pdev, + skb_tail_pointer_rsl(skb), + priv->rxbuffersize, + PCI_DMA_FROMDEVICE); + + } +done: + pdesc->BufferAddress = cpu_to_le32(*((dma_addr_t *)skb->cb)); + pdesc->OWN = 1; + pdesc->Length = priv->rxbuffersize; + if (priv->rx_idx[rx_queue_idx] == priv->rxringcount-1) + pdesc->EOR = 1; + priv->rx_idx[rx_queue_idx] = (priv->rx_idx[rx_queue_idx] + 1) % + priv->rxringcount; + } + +} + +static void rtl8192_rx_cmd(struct net_device *dev) +{ +} + + +static void rtl8192_tx_resume(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + struct sk_buff *skb; + int queue_index; + + for (queue_index = BK_QUEUE; + queue_index < MAX_QUEUE_SIZE; queue_index++) { + while ((!skb_queue_empty(&ieee->skb_waitQ[queue_index])) && + (priv->rtllib->check_nic_enough_desc(dev, queue_index) > 0)) { + skb = skb_dequeue(&ieee->skb_waitQ[queue_index]); + ieee->softmac_data_hard_start_xmit(skb, dev, 0); + } + } +} + +void rtl8192_irq_tx_tasklet(struct r8192_priv *priv) +{ + rtl8192_tx_resume(priv->rtllib->dev); +} + +void rtl8192_irq_rx_tasklet(struct r8192_priv *priv) +{ + rtl8192_rx_normal(priv->rtllib->dev); + + if (MAX_RX_QUEUE > 1) + rtl8192_rx_cmd(priv->rtllib->dev); + + write_nic_dword(priv->rtllib->dev, INTA_MASK, + read_nic_dword(priv->rtllib->dev, INTA_MASK) | IMR_RDU); +} + +/**************************************************************************** + ---------------------------- NIC START/CLOSE STUFF--------------------------- +*****************************************************************************/ +void rtl8192_cancel_deferred_work(struct r8192_priv *priv) +{ + cancel_delayed_work(&priv->watch_dog_wq); + cancel_delayed_work(&priv->update_beacon_wq); + cancel_delayed_work(&priv->rtllib->hw_sleep_wq); + cancel_work_sync(&priv->reset_wq); + cancel_work_sync(&priv->qos_activate); +} + +int _rtl8192_up(struct net_device *dev, bool is_silent_reset) +{ + if (_rtl8192_sta_up(dev, is_silent_reset) == -1) + return -1; + return 0; +} + + +static int rtl8192_open(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + int ret; + + down(&priv->wx_sem); + ret = rtl8192_up(dev); + up(&priv->wx_sem); + return ret; + +} + + +int rtl8192_up(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + if (priv->up == 1) + return -1; + return _rtl8192_up(dev, false); +} + + +static int rtl8192_close(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + int ret; + + if ((rtllib_act_scanning(priv->rtllib, false)) && + !(priv->rtllib->softmac_features & IEEE_SOFTMAC_SCAN)) { + rtllib_stop_scan(priv->rtllib); + } + + down(&priv->wx_sem); + + ret = rtl8192_down(dev, true); + + up(&priv->wx_sem); + + return ret; + +} + +int rtl8192_down(struct net_device *dev, bool shutdownrf) +{ + if (rtl8192_sta_down(dev, shutdownrf) == -1) + return -1; + + return 0; +} + +void rtl8192_commit(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + if (priv->up == 0) + return; + rtllib_softmac_stop_protocol(priv->rtllib, 0 , true); + rtl8192_irq_disable(dev); + priv->ops->stop_adapter(dev, true); + _rtl8192_up(dev, false); +} + +void rtl8192_restart(void *data) +{ + struct r8192_priv *priv = container_of_work_rsl(data, struct r8192_priv, + reset_wq); + struct net_device *dev = priv->rtllib->dev; + + down(&priv->wx_sem); + + rtl8192_commit(dev); + + up(&priv->wx_sem); +} + +static void r8192_set_multicast(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + short promisc; + + promisc = (dev->flags & IFF_PROMISC) ? 1 : 0; + priv->promisc = promisc; + +} + + +static int r8192_set_mac_adr(struct net_device *dev, void *mac) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct sockaddr *addr = mac; + + down(&priv->wx_sem); + + memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); + + schedule_work(&priv->reset_wq); + up(&priv->wx_sem); + + return 0; +} + +/* based on ipw2200 driver */ +static int rtl8192_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + struct iwreq *wrq = (struct iwreq *)rq; + int ret = -1; + struct rtllib_device *ieee = priv->rtllib; + u32 key[4]; + u8 broadcast_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u8 zero_addr[6] = {0}; + struct iw_point *p = &wrq->u.data; + struct ieee_param *ipw = NULL; + + down(&priv->wx_sem); + + switch (cmd) { + case RTL_IOCTL_WPA_SUPPLICANT: + if (p->length < sizeof(struct ieee_param) || !p->pointer) { + ret = -EINVAL; + goto out; + } + + ipw = kmalloc(p->length, GFP_KERNEL); + if (ipw == NULL) { + ret = -ENOMEM; + goto out; + } + if (copy_from_user(ipw, p->pointer, p->length)) { + kfree(ipw); + ret = -EFAULT; + goto out; + } + + if (ipw->cmd == IEEE_CMD_SET_ENCRYPTION) { + if (ipw->u.crypt.set_tx) { + if (strcmp(ipw->u.crypt.alg, "CCMP") == 0) + ieee->pairwise_key_type = KEY_TYPE_CCMP; + else if (strcmp(ipw->u.crypt.alg, "TKIP") == 0) + ieee->pairwise_key_type = KEY_TYPE_TKIP; + else if (strcmp(ipw->u.crypt.alg, "WEP") == 0) { + if (ipw->u.crypt.key_len == 13) + ieee->pairwise_key_type = + KEY_TYPE_WEP104; + else if (ipw->u.crypt.key_len == 5) + ieee->pairwise_key_type = + KEY_TYPE_WEP40; + } else { + ieee->pairwise_key_type = KEY_TYPE_NA; + } + + if (ieee->pairwise_key_type) { + if (memcmp(ieee->ap_mac_addr, zero_addr, + 6) == 0) + ieee->iw_mode = IW_MODE_ADHOC; + memcpy((u8 *)key, ipw->u.crypt.key, 16); + EnableHWSecurityConfig8192(dev); + set_swcam(dev, 4, ipw->u.crypt.idx, + ieee->pairwise_key_type, + (u8 *)ieee->ap_mac_addr, + 0, key, 0); + setKey(dev, 4, ipw->u.crypt.idx, + ieee->pairwise_key_type, + (u8 *)ieee->ap_mac_addr, 0, key); + if (ieee->iw_mode == IW_MODE_ADHOC) { + set_swcam(dev, ipw->u.crypt.idx, + ipw->u.crypt.idx, + ieee->pairwise_key_type, + (u8 *)ieee->ap_mac_addr, + 0, key, 0); + setKey(dev, ipw->u.crypt.idx, + ipw->u.crypt.idx, + ieee->pairwise_key_type, + (u8 *)ieee->ap_mac_addr, + 0, key); + } + } + if ((ieee->pairwise_key_type == KEY_TYPE_CCMP) + && ieee->pHTInfo->bCurrentHTSupport) { + write_nic_byte(dev, 0x173, 1); + } + + } else { + memcpy((u8 *)key, ipw->u.crypt.key, 16); + if (strcmp(ipw->u.crypt.alg, "CCMP") == 0) + ieee->group_key_type = KEY_TYPE_CCMP; + else if (strcmp(ipw->u.crypt.alg, "TKIP") == 0) + ieee->group_key_type = KEY_TYPE_TKIP; + else if (strcmp(ipw->u.crypt.alg, "WEP") == 0) { + if (ipw->u.crypt.key_len == 13) + ieee->group_key_type = + KEY_TYPE_WEP104; + else if (ipw->u.crypt.key_len == 5) + ieee->group_key_type = + KEY_TYPE_WEP40; + } else + ieee->group_key_type = KEY_TYPE_NA; + + if (ieee->group_key_type) { + set_swcam(dev, ipw->u.crypt.idx, + ipw->u.crypt.idx, + ieee->group_key_type, + broadcast_addr, 0, key, 0); + setKey(dev, ipw->u.crypt.idx, + ipw->u.crypt.idx, + ieee->group_key_type, + broadcast_addr, 0, key); + } + } + } + + ret = rtllib_wpa_supplicant_ioctl(priv->rtllib, &wrq->u.data, + 0); + kfree(ipw); + break; + default: + ret = -EOPNOTSUPP; + break; + } + +out: + up(&priv->wx_sem); + + return ret; +} + + +irqreturn_type rtl8192_interrupt(int irq, void *netdev, struct pt_regs *regs) +{ + struct net_device *dev = (struct net_device *) netdev; + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + unsigned long flags; + u32 inta; + u32 intb; + intb = 0; + + if (priv->irq_enabled == 0) + goto done; + + spin_lock_irqsave(&priv->irq_th_lock, flags); + + priv->ops->interrupt_recognized(dev, &inta, &intb); + priv->stats.shints++; + + if (!inta) { + spin_unlock_irqrestore(&priv->irq_th_lock, flags); + goto done; + } + + if (inta == 0xffff) { + spin_unlock_irqrestore(&priv->irq_th_lock, flags); + goto done; + } + + priv->stats.ints++; + + if (!netif_running(dev)) { + spin_unlock_irqrestore(&priv->irq_th_lock, flags); + goto done; + } + + if (inta & IMR_TBDOK) { + RT_TRACE(COMP_INTR, "beacon ok interrupt!\n"); + priv->stats.txbeaconokint++; + } + + if (inta & IMR_TBDER) { + RT_TRACE(COMP_INTR, "beacon ok interrupt!\n"); + priv->stats.txbeaconerr++; + } + + if (inta & IMR_BDOK) + RT_TRACE(COMP_INTR, "beacon interrupt!\n"); + + if (inta & IMR_MGNTDOK) { + RT_TRACE(COMP_INTR, "Manage ok interrupt!\n"); + priv->stats.txmanageokint++; + rtl8192_tx_isr(dev, MGNT_QUEUE); + spin_unlock_irqrestore(&priv->irq_th_lock, flags); + if (priv->rtllib->ack_tx_to_ieee) { + if (rtl8192_is_tx_queue_empty(dev)) { + priv->rtllib->ack_tx_to_ieee = 0; + rtllib_ps_tx_ack(priv->rtllib, 1); + } + } + spin_lock_irqsave(&priv->irq_th_lock, flags); + } + + if (inta & IMR_COMDOK) { + priv->stats.txcmdpktokint++; + rtl8192_tx_isr(dev, TXCMD_QUEUE); + } + + if (inta & IMR_HIGHDOK) + rtl8192_tx_isr(dev, HIGH_QUEUE); + + if (inta & IMR_ROK) { + priv->stats.rxint++; + priv->InterruptLog.nIMR_ROK++; + tasklet_schedule(&priv->irq_rx_tasklet); + } + + if (inta & IMR_BcnInt) { + RT_TRACE(COMP_INTR, "prepare beacon for interrupt!\n"); + tasklet_schedule(&priv->irq_prepare_beacon_tasklet); + } + + if (inta & IMR_RDU) { + RT_TRACE(COMP_INTR, "rx descriptor unavailable!\n"); + priv->stats.rxrdu++; + write_nic_dword(dev, INTA_MASK, + read_nic_dword(dev, INTA_MASK) & ~IMR_RDU); + tasklet_schedule(&priv->irq_rx_tasklet); + } + + if (inta & IMR_RXFOVW) { + RT_TRACE(COMP_INTR, "rx overflow !\n"); + priv->stats.rxoverflow++; + tasklet_schedule(&priv->irq_rx_tasklet); + } + + if (inta & IMR_TXFOVW) + priv->stats.txoverflow++; + + if (inta & IMR_BKDOK) { + RT_TRACE(COMP_INTR, "BK Tx OK interrupt!\n"); + priv->stats.txbkokint++; + priv->rtllib->LinkDetectInfo.NumTxOkInPeriod++; + rtl8192_tx_isr(dev, BK_QUEUE); + } + + if (inta & IMR_BEDOK) { + RT_TRACE(COMP_INTR, "BE TX OK interrupt!\n"); + priv->stats.txbeokint++; + priv->rtllib->LinkDetectInfo.NumTxOkInPeriod++; + rtl8192_tx_isr(dev, BE_QUEUE); + } + + if (inta & IMR_VIDOK) { + RT_TRACE(COMP_INTR, "VI TX OK interrupt!\n"); + priv->stats.txviokint++; + priv->rtllib->LinkDetectInfo.NumTxOkInPeriod++; + rtl8192_tx_isr(dev, VI_QUEUE); + } + + if (inta & IMR_VODOK) { + priv->stats.txvookint++; + RT_TRACE(COMP_INTR, "Vo TX OK interrupt!\n"); + priv->rtllib->LinkDetectInfo.NumTxOkInPeriod++; + rtl8192_tx_isr(dev, VO_QUEUE); + } + + spin_unlock_irqrestore(&priv->irq_th_lock, flags); + +done: + + return IRQ_HANDLED; +} + + + +/**************************************************************************** + ---------------------------- PCI_STUFF--------------------------- +*****************************************************************************/ +static const struct net_device_ops rtl8192_netdev_ops = { + .ndo_open = rtl8192_open, + .ndo_stop = rtl8192_close, + .ndo_tx_timeout = rtl8192_tx_timeout, + .ndo_do_ioctl = rtl8192_ioctl, + .ndo_set_rx_mode = r8192_set_multicast, + .ndo_set_mac_address = r8192_set_mac_adr, + .ndo_validate_addr = eth_validate_addr, + .ndo_change_mtu = eth_change_mtu, + .ndo_start_xmit = rtllib_xmit, +}; + +static int __devinit rtl8192_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + unsigned long ioaddr = 0; + struct net_device *dev = NULL; + struct r8192_priv *priv = NULL; + struct rtl819x_ops *ops = (struct rtl819x_ops *)(id->driver_data); + unsigned long pmem_start, pmem_len, pmem_flags; + int err = -ENOMEM; + bool bdma64 = false; + u8 revision_id; + + RT_TRACE(COMP_INIT, "Configuring chip resources"); + + if (pci_enable_device(pdev)) { + RT_TRACE(COMP_ERR, "Failed to enable PCI device"); + return -EIO; + } + + pci_set_master(pdev); + + if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { + if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { + printk(KERN_INFO "Unable to obtain 32bit DMA for consistent allocations\n"); + goto err_pci_disable; + } + } + dev = alloc_rtllib(sizeof(struct r8192_priv)); + if (!dev) + goto err_pci_disable; + + err = -ENODEV; + if (bdma64) + dev->features |= NETIF_F_HIGHDMA; + + pci_set_drvdata(pdev, dev); + SET_NETDEV_DEV(dev, &pdev->dev); + priv = rtllib_priv(dev); + priv->rtllib = (struct rtllib_device *)netdev_priv_rsl(dev); + priv->pdev = pdev; + priv->rtllib->pdev = pdev; + if ((pdev->subsystem_vendor == PCI_VENDOR_ID_DLINK) && + (pdev->subsystem_device == 0x3304)) + priv->rtllib->bSupportRemoteWakeUp = 1; + else + priv->rtllib->bSupportRemoteWakeUp = 0; + + pmem_start = pci_resource_start(pdev, 1); + pmem_len = pci_resource_len(pdev, 1); + pmem_flags = pci_resource_flags(pdev, 1); + + if (!(pmem_flags & IORESOURCE_MEM)) { + RT_TRACE(COMP_ERR, "region #1 not a MMIO resource, aborting"); + goto err_rel_rtllib; + } + + printk(KERN_INFO "Memory mapped space start: 0x%08lx\n", pmem_start); + if (!request_mem_region(pmem_start, pmem_len, DRV_NAME)) { + RT_TRACE(COMP_ERR, "request_mem_region failed!"); + goto err_rel_rtllib; + } + + + ioaddr = (unsigned long)ioremap_nocache(pmem_start, pmem_len); + if (ioaddr == (unsigned long)NULL) { + RT_TRACE(COMP_ERR, "ioremap failed!"); + goto err_rel_mem; + } + + dev->mem_start = ioaddr; + dev->mem_end = ioaddr + pci_resource_len(pdev, 0); + + pci_read_config_byte(pdev, 0x08, &revision_id); + /* If the revisionid is 0x10, the device uses rtl8192se. */ + if (pdev->device == 0x8192 && revision_id == 0x10) + goto err_rel_mem; + + priv->ops = ops; + + if (rtl8192_pci_findadapter(pdev, dev) == false) + goto err_rel_mem; + + dev->irq = pdev->irq; + priv->irq = 0; + + dev->netdev_ops = &rtl8192_netdev_ops; + + dev->wireless_handlers = (struct iw_handler_def *) + &r8192_wx_handlers_def; + dev->ethtool_ops = &rtl819x_ethtool_ops; + + dev->type = ARPHRD_ETHER; + dev->watchdog_timeo = HZ * 3; + + if (dev_alloc_name(dev, ifname) < 0) { + RT_TRACE(COMP_INIT, "Oops: devname already taken! Trying " + "wlan%%d...\n"); + dev_alloc_name(dev, ifname); + } + + RT_TRACE(COMP_INIT, "Driver probe completed1\n"); + if (rtl8192_init(dev) != 0) { + RT_TRACE(COMP_ERR, "Initialization failed"); + goto err_free_irq; + } + + netif_carrier_off(dev); + netif_stop_queue(dev); + + register_netdev(dev); + RT_TRACE(COMP_INIT, "dev name: %s\n", dev->name); + + rtl8192_proc_init_one(dev); + + if (priv->polling_timer_on == 0) + check_rfctrl_gpio_timer((unsigned long)dev); + + RT_TRACE(COMP_INIT, "Driver probe completed\n"); + return 0; + +err_free_irq: + free_irq(dev->irq, dev); + priv->irq = 0; +err_rel_mem: + release_mem_region(pmem_start, pmem_len); +err_rel_rtllib: + free_rtllib(dev); + + DMESG("wlan driver load failed\n"); + pci_set_drvdata(pdev, NULL); +err_pci_disable: + pci_disable_device(pdev); + return err; +} + +static void __devexit rtl8192_pci_disconnect(struct pci_dev *pdev) +{ + struct net_device *dev = pci_get_drvdata(pdev); + struct r8192_priv *priv ; + u32 i; + + if (dev) { + unregister_netdev(dev); + + priv = rtllib_priv(dev); + + del_timer_sync(&priv->gpio_polling_timer); + cancel_delayed_work(&priv->gpio_change_rf_wq); + priv->polling_timer_on = 0; + rtl8192_proc_remove_one(dev); + rtl8192_down(dev, true); + deinit_hal_dm(dev); + if (priv->pFirmware) { + vfree(priv->pFirmware); + priv->pFirmware = NULL; + } + destroy_workqueue(priv->priv_wq); + rtl8192_free_rx_ring(dev); + for (i = 0; i < MAX_TX_QUEUE_COUNT; i++) + rtl8192_free_tx_ring(dev, i); + + if (priv->irq) { + printk(KERN_INFO "Freeing irq %d\n", dev->irq); + free_irq(dev->irq, dev); + priv->irq = 0; + } + free_rtllib(dev); + + kfree(priv->scan_cmd); + + if (dev->mem_start != 0) { + iounmap((void __iomem *)dev->mem_start); + release_mem_region(pci_resource_start(pdev, 1), + pci_resource_len(pdev, 1)); + } + } else { + priv = rtllib_priv(dev); + } + + pci_disable_device(pdev); + RT_TRACE(COMP_DOWN, "wlan driver removed\n"); +} + +bool NicIFEnableNIC(struct net_device *dev) +{ + bool init_status = true; + struct r8192_priv *priv = rtllib_priv(dev); + struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *) + (&(priv->rtllib->PowerSaveControl)); + + if (IS_NIC_DOWN(priv)) { + RT_TRACE(COMP_ERR, "ERR!!! %s(): Driver is already down!\n", + __func__); + priv->bdisable_nic = false; + return RT_STATUS_FAILURE; + } + + RT_TRACE(COMP_PS, "===========>%s()\n", __func__); + priv->bfirst_init = true; + init_status = priv->ops->initialize_adapter(dev); + if (init_status != true) { + RT_TRACE(COMP_ERR, "ERR!!! %s(): initialization is failed!\n", + __func__); + priv->bdisable_nic = false; + return -1; + } + RT_TRACE(COMP_INIT, "start adapter finished\n"); + RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); + priv->bfirst_init = false; + + rtl8192_irq_enable(dev); + priv->bdisable_nic = false; + RT_TRACE(COMP_PS, "<===========%s()\n", __func__); + return init_status; +} +bool NicIFDisableNIC(struct net_device *dev) +{ + bool status = true; + struct r8192_priv *priv = rtllib_priv(dev); + u8 tmp_state = 0; + RT_TRACE(COMP_PS, "=========>%s()\n", __func__); + priv->bdisable_nic = true; + tmp_state = priv->rtllib->state; + rtllib_softmac_stop_protocol(priv->rtllib, 0, false); + priv->rtllib->state = tmp_state; + rtl8192_cancel_deferred_work(priv); + rtl8192_irq_disable(dev); + + priv->ops->stop_adapter(dev, false); + RT_TRACE(COMP_PS, "<=========%s()\n", __func__); + + return status; +} + +static int __init rtl8192_pci_module_init(void) +{ + printk(KERN_INFO "\nLinux kernel driver for RTL8192E WLAN cards\n"); + printk(KERN_INFO "Copyright (c) 2007-2008, Realsil Wlan Driver\n"); + + rtl8192_proc_module_init(); + if (0 != pci_register_driver(&rtl8192_pci_driver)) { + DMESG("No device found"); + /*pci_unregister_driver (&rtl8192_pci_driver);*/ + return -ENODEV; + } + return 0; +} + +static void __exit rtl8192_pci_module_exit(void) +{ + pci_unregister_driver(&rtl8192_pci_driver); + + RT_TRACE(COMP_DOWN, "Exiting"); + rtl8192_proc_module_remove(); +} + +void check_rfctrl_gpio_timer(unsigned long data) +{ + struct r8192_priv *priv = rtllib_priv((struct net_device *)data); + + priv->polling_timer_on = 1; + + queue_delayed_work_rsl(priv->priv_wq, &priv->gpio_change_rf_wq, 0); + + mod_timer(&priv->gpio_polling_timer, jiffies + + MSECS(RTLLIB_WATCH_DOG_TIME)); +} + +/*************************************************************************** + ------------------- module init / exit stubs ---------------- +****************************************************************************/ +module_init(rtl8192_pci_module_init); +module_exit(rtl8192_pci_module_exit); + +MODULE_DESCRIPTION("Linux driver for Realtek RTL819x WiFi cards"); +MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); +MODULE_VERSION(DRV_VERSION); +MODULE_LICENSE("GPL"); + +module_param(ifname, charp, S_IRUGO|S_IWUSR); +module_param(hwwep, int, S_IRUGO|S_IWUSR); +module_param(channels, int, S_IRUGO|S_IWUSR); + +MODULE_PARM_DESC(ifname, " Net interface name, wlan%d=default"); +MODULE_PARM_DESC(hwwep, " Try to use hardware WEP support(default use hw. set 0 to use software security)"); +MODULE_PARM_DESC(channels, " Channel bitmask for specific locales. NYI"); diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_core.h b/drivers/staging/rtl8192e/rtl8192e/rtl_core.h new file mode 100644 index 000000000000..93478df42b7d --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_core.h @@ -0,0 +1,1096 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * Based on the r8180 driver, which is: + * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ + +#ifndef _RTL_CORE_H +#define _RTL_CORE_H + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/ioport.h> +#include <linux/sched.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/slab.h> +#include <linux/netdevice.h> +#include <linux/pci.h> +#include <linux/etherdevice.h> +#include <linux/delay.h> +#include <linux/rtnetlink.h> +#include <linux/wireless.h> +#include <linux/timer.h> +#include <linux/proc_fs.h> +#include <linux/if_arp.h> +#include <linux/random.h> +#include <linux/version.h> +#include <linux/io.h> + +/* Need this defined before including local include files */ +#define DRV_NAME "rtl819xE" + +#include "../rtllib.h" + +#include "../dot11d.h" + +#include "r8192E_firmware.h" +#include "r8192E_hw.h" + +#include "r8190P_def.h" +#include "r8192E_dev.h" + +#include "rtl_eeprom.h" +#include "rtl_ps.h" +#include "rtl_pci.h" +#include "rtl_cam.h" + +#define DRV_COPYRIGHT \ + "Copyright(c) 2008 - 2010 Realsil Semiconductor Corporation" +#define DRV_AUTHOR "<wlanfae@realtek.com>" +#define DRV_VERSION "0014.0401.2010" + +#define IS_HARDWARE_TYPE_819xP(_priv) \ + ((((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8190P) || \ + (((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8192E)) +#define IS_HARDWARE_TYPE_8192SE(_priv) \ + (((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8192SE) +#define IS_HARDWARE_TYPE_8192CE(_priv) \ + (((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8192CE) +#define IS_HARDWARE_TYPE_8192CU(_priv) \ + (((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8192CU) +#define IS_HARDWARE_TYPE_8192DE(_priv) \ + (((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8192DE) +#define IS_HARDWARE_TYPE_8192DU(_priv) \ + (((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8192DU) + +#define RTL_PCI_DEVICE(vend, dev, cfg) \ + .vendor = (vend), .device = (dev), \ + .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID , \ + .driver_data = (kernel_ulong_t)&(cfg) + +#define irqreturn_type irqreturn_t + +#define rtl8192_interrupt(x, y, z) rtl8192_interrupt_rsl(x, y) + +#define RTL_MAX_SCAN_SIZE 128 + +#define RTL_RATE_MAX 30 + +#define TOTAL_CAM_ENTRY 32 +#define CAM_CONTENT_COUNT 8 + +#ifndef BIT +#define BIT(_i) (1<<(_i)) +#endif + +#define IS_NIC_DOWN(priv) (!(priv)->up) + +#define IS_ADAPTER_SENDS_BEACON(dev) 0 + +#define IS_UNDER_11N_AES_MODE(_rtllib) \ + ((_rtllib->pHTInfo->bCurrentHTSupport == true) && \ + (_rtllib->pairwise_key_type == KEY_TYPE_CCMP)) + +#define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI 0x1000 +#define HAL_HW_PCI_REVISION_ID_8190PCI 0x00 +#define HAL_MEMORY_MAPPED_IO_RANGE_8192PCIE 0x4000 +#define HAL_HW_PCI_REVISION_ID_8192PCIE 0x01 +#define HAL_MEMORY_MAPPED_IO_RANGE_8192SE 0x4000 +#define HAL_HW_PCI_REVISION_ID_8192SE 0x10 +#define HAL_HW_PCI_REVISION_ID_8192CE 0x1 +#define HAL_MEMORY_MAPPED_IO_RANGE_8192CE 0x4000 +#define HAL_HW_PCI_REVISION_ID_8192DE 0x0 +#define HAL_MEMORY_MAPPED_IO_RANGE_8192DE 0x4000 + +#define HAL_HW_PCI_8180_DEVICE_ID 0x8180 +#define HAL_HW_PCI_8185_DEVICE_ID 0x8185 +#define HAL_HW_PCI_8188_DEVICE_ID 0x8188 +#define HAL_HW_PCI_8198_DEVICE_ID 0x8198 +#define HAL_HW_PCI_8190_DEVICE_ID 0x8190 +#define HAL_HW_PCI_8192_DEVICE_ID 0x8192 +#define HAL_HW_PCI_8192SE_DEVICE_ID 0x8192 +#define HAL_HW_PCI_8174_DEVICE_ID 0x8174 +#define HAL_HW_PCI_8173_DEVICE_ID 0x8173 +#define HAL_HW_PCI_8172_DEVICE_ID 0x8172 +#define HAL_HW_PCI_8171_DEVICE_ID 0x8171 +#define HAL_HW_PCI_0045_DEVICE_ID 0x0045 +#define HAL_HW_PCI_0046_DEVICE_ID 0x0046 +#define HAL_HW_PCI_0044_DEVICE_ID 0x0044 +#define HAL_HW_PCI_0047_DEVICE_ID 0x0047 +#define HAL_HW_PCI_700F_DEVICE_ID 0x700F +#define HAL_HW_PCI_701F_DEVICE_ID 0x701F +#define HAL_HW_PCI_DLINK_DEVICE_ID 0x3304 +#define HAL_HW_PCI_8192CET_DEVICE_ID 0x8191 +#define HAL_HW_PCI_8192CE_DEVICE_ID 0x8178 +#define HAL_HW_PCI_8191CE_DEVICE_ID 0x8177 +#define HAL_HW_PCI_8188CE_DEVICE_ID 0x8176 +#define HAL_HW_PCI_8192CU_DEVICE_ID 0x8191 +#define HAL_HW_PCI_8192DE_DEVICE_ID 0x092D +#define HAL_HW_PCI_8192DU_DEVICE_ID 0x092D + +#define RTL819X_DEFAULT_RF_TYPE RF_1T2R + +#define RTLLIB_WATCH_DOG_TIME 2000 + +#define MAX_DEV_ADDR_SIZE 8 /*support till 64 bit bus width OS*/ +#define MAX_FIRMWARE_INFORMATION_SIZE 32 +#define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE) +#define ENCRYPTION_MAX_OVERHEAD 128 +#define MAX_FRAGMENT_COUNT 8 +#define MAX_TRANSMIT_BUFFER_SIZE \ + (1600 + (MAX_802_11_HEADER_LENGTH + ENCRYPTION_MAX_OVERHEAD) * \ + MAX_FRAGMENT_COUNT) + +#define scrclng 4 + +#define DEFAULT_FRAG_THRESHOLD 2342U +#define MIN_FRAG_THRESHOLD 256U +#define DEFAULT_BEACONINTERVAL 0x64U + +#define DEFAULT_SSID "" +#define DEFAULT_RETRY_RTS 7 +#define DEFAULT_RETRY_DATA 7 +#define PRISM_HDR_SIZE 64 + +#define PHY_RSSI_SLID_WIN_MAX 100 + +#define RTL_IOCTL_WPA_SUPPLICANT (SIOCIWFIRSTPRIV + 30) + +#define TxBBGainTableLength 37 +#define CCKTxBBGainTableLength 23 + +#define CHANNEL_PLAN_LEN 10 +#define sCrcLng 4 + +#define NIC_SEND_HANG_THRESHOLD_NORMAL 4 +#define NIC_SEND_HANG_THRESHOLD_POWERSAVE 8 + +#define MAX_TX_QUEUE 9 + +#define MAX_RX_QUEUE 1 + +#define MAX_RX_COUNT 64 +#define MAX_TX_QUEUE_COUNT 9 + +enum RTL819x_PHY_PARAM { + RTL819X_PHY_MACPHY_REG = 0, + RTL819X_PHY_MACPHY_REG_PG = 1, + RTL8188C_PHY_MACREG = 2, + RTL8192C_PHY_MACREG = 3, + RTL819X_PHY_REG = 4, + RTL819X_PHY_REG_1T2R = 5, + RTL819X_PHY_REG_to1T1R = 6, + RTL819X_PHY_REG_to1T2R = 7, + RTL819X_PHY_REG_to2T2R = 8, + RTL819X_PHY_REG_PG = 9, + RTL819X_AGC_TAB = 10, + RTL819X_PHY_RADIO_A = 11, + RTL819X_PHY_RADIO_A_1T = 12, + RTL819X_PHY_RADIO_A_2T = 13, + RTL819X_PHY_RADIO_B = 14, + RTL819X_PHY_RADIO_B_GM = 15, + RTL819X_PHY_RADIO_C = 16, + RTL819X_PHY_RADIO_D = 17, + RTL819X_EEPROM_MAP = 18, + RTL819X_EFUSE_MAP = 19, +}; + +enum nic_t { + NIC_UNKNOWN = 0, + NIC_8192E = 1, + NIC_8190P = 2, + NIC_8192SE = 4, + NIC_8192CE = 5, + NIC_8192CU = 6, + NIC_8192DE = 7, + NIC_8192DU = 8, +}; + +enum rt_eeprom_type { + EEPROM_93C46, + EEPROM_93C56, + EEPROM_BOOT_EFUSE, +}; + +enum dcmg_txcmd_op { + TXCMD_TXRA_HISTORY_CTRL = 0xFF900000, + TXCMD_RESET_TX_PKT_BUFF = 0xFF900001, + TXCMD_RESET_RX_PKT_BUFF = 0xFF900002, + TXCMD_SET_TX_DURATION = 0xFF900003, + TXCMD_SET_RX_RSSI = 0xFF900004, + TXCMD_SET_TX_PWR_TRACKING = 0xFF900005, + TXCMD_XXXX_CTRL, +}; + +enum rt_rf_type_819xu { + RF_TYPE_MIN = 0, + RF_8225, + RF_8256, + RF_8258, + RF_6052 = 4, + RF_PSEUDO_11N = 5, +}; + +enum rf_step { + RF_STEP_INIT = 0, + RF_STEP_NORMAL, + RF_STEP_MAX +}; + +enum rt_status { + RT_STATUS_SUCCESS, + RT_STATUS_FAILURE, + RT_STATUS_PENDING, + RT_STATUS_RESOURCE +}; + +enum rt_customer_id { + RT_CID_DEFAULT = 0, + RT_CID_8187_ALPHA0 = 1, + RT_CID_8187_SERCOMM_PS = 2, + RT_CID_8187_HW_LED = 3, + RT_CID_8187_NETGEAR = 4, + RT_CID_WHQL = 5, + RT_CID_819x_CAMEO = 6, + RT_CID_819x_RUNTOP = 7, + RT_CID_819x_Senao = 8, + RT_CID_TOSHIBA = 9, + RT_CID_819x_Netcore = 10, + RT_CID_Nettronix = 11, + RT_CID_DLINK = 12, + RT_CID_PRONET = 13, + RT_CID_COREGA = 14, + RT_CID_819x_ALPHA = 15, + RT_CID_819x_Sitecom = 16, + RT_CID_CCX = 17, + RT_CID_819x_Lenovo = 18, + RT_CID_819x_QMI = 19, + RT_CID_819x_Edimax_Belkin = 20, + RT_CID_819x_Sercomm_Belkin = 21, + RT_CID_819x_CAMEO1 = 22, + RT_CID_819x_MSI = 23, + RT_CID_819x_Acer = 24, + RT_CID_819x_HP = 27, + RT_CID_819x_CLEVO = 28, + RT_CID_819x_Arcadyan_Belkin = 29, + RT_CID_819x_SAMSUNG = 30, + RT_CID_819x_WNC_COREGA = 31, +}; + +enum reset_type { + RESET_TYPE_NORESET = 0x00, + RESET_TYPE_NORMAL = 0x01, + RESET_TYPE_SILENT = 0x02 +}; + +enum ic_inferiority_8192s { + IC_INFERIORITY_A = 0, + IC_INFERIORITY_B = 1, +}; + +enum pci_bridge_vendor { + PCI_BRIDGE_VENDOR_INTEL = 0x0, + PCI_BRIDGE_VENDOR_ATI, + PCI_BRIDGE_VENDOR_AMD, + PCI_BRIDGE_VENDOR_SIS , + PCI_BRIDGE_VENDOR_UNKNOWN, + PCI_BRIDGE_VENDOR_MAX , +}; + +struct buffer { + struct buffer *next; + u32 *buf; + dma_addr_t dma; + +}; + +struct rtl_reg_debug { + unsigned int cmd; + struct { + unsigned char type; + unsigned char addr; + unsigned char page; + unsigned char length; + } head; + unsigned char buf[0xff]; +}; + +struct rt_tx_rahis { + u32 cck[4]; + u32 ofdm[8]; + u32 ht_mcs[4][16]; +}; + +struct rt_smooth_data_4rf { + char elements[4][100]; + u32 index; + u32 TotalNum; + u32 TotalVal[4]; +}; + +struct rt_stats { + unsigned long txrdu; + unsigned long rxrdu; + unsigned long rxok; + unsigned long rxframgment; + unsigned long rxcmdpkt[8]; + unsigned long rxurberr; + unsigned long rxstaterr; + unsigned long rxdatacrcerr; + unsigned long rxmgmtcrcerr; + unsigned long rxcrcerrmin; + unsigned long rxcrcerrmid; + unsigned long rxcrcerrmax; + unsigned long received_rate_histogram[4][32]; + unsigned long received_preamble_GI[2][32]; + unsigned long rx_AMPDUsize_histogram[5]; + unsigned long rx_AMPDUnum_histogram[5]; + unsigned long numpacket_matchbssid; + unsigned long numpacket_toself; + unsigned long num_process_phyinfo; + unsigned long numqry_phystatus; + unsigned long numqry_phystatusCCK; + unsigned long numqry_phystatusHT; + unsigned long received_bwtype[5]; + unsigned long txnperr; + unsigned long txnpdrop; + unsigned long txresumed; + unsigned long rxoverflow; + unsigned long rxint; + unsigned long txnpokint; + unsigned long ints; + unsigned long shints; + unsigned long txoverflow; + unsigned long txlpokint; + unsigned long txlpdrop; + unsigned long txlperr; + unsigned long txbeokint; + unsigned long txbedrop; + unsigned long txbeerr; + unsigned long txbkokint; + unsigned long txbkdrop; + unsigned long txbkerr; + unsigned long txviokint; + unsigned long txvidrop; + unsigned long txvierr; + unsigned long txvookint; + unsigned long txvodrop; + unsigned long txvoerr; + unsigned long txbeaconokint; + unsigned long txbeacondrop; + unsigned long txbeaconerr; + unsigned long txmanageokint; + unsigned long txmanagedrop; + unsigned long txmanageerr; + unsigned long txcmdpktokint; + unsigned long txdatapkt; + unsigned long txfeedback; + unsigned long txfeedbackok; + unsigned long txoktotal; + unsigned long txokbytestotal; + unsigned long txokinperiod; + unsigned long txmulticast; + unsigned long txbytesmulticast; + unsigned long txbroadcast; + unsigned long txbytesbroadcast; + unsigned long txunicast; + unsigned long txbytesunicast; + unsigned long rxbytesunicast; + unsigned long txfeedbackfail; + unsigned long txerrtotal; + unsigned long txerrbytestotal; + unsigned long txerrmulticast; + unsigned long txerrbroadcast; + unsigned long txerrunicast; + unsigned long txretrycount; + unsigned long txfeedbackretry; + u8 last_packet_rate; + unsigned long slide_signal_strength[100]; + unsigned long slide_evm[100]; + unsigned long slide_rssi_total; + unsigned long slide_evm_total; + long signal_strength; + long signal_quality; + long last_signal_strength_inpercent; + long recv_signal_power; + u8 rx_rssi_percentage[4]; + u8 rx_evm_percentage[2]; + long rxSNRdB[4]; + struct rt_tx_rahis txrate; + u32 Slide_Beacon_pwdb[100]; + u32 Slide_Beacon_Total; + struct rt_smooth_data_4rf cck_adc_pwdb; + u32 CurrentShowTxate; +}; + +struct channel_access_setting { + u16 SIFS_Timer; + u16 DIFS_Timer; + u16 SlotTimeTimer; + u16 EIFS_Timer; + u16 CWminIndex; + u16 CWmaxIndex; +}; + +enum two_port_status { + TWO_PORT_STATUS__DEFAULT_ONLY, + TWO_PORT_STATUS__EXTENSION_ONLY, + TWO_PORT_STATUS__EXTENSION_FOLLOW_DEFAULT, + TWO_PORT_STATUS__DEFAULT_G_EXTENSION_N20, + TWO_PORT_STATUS__ADHOC, + TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE +}; + +struct txbbgain_struct { + long txbb_iq_amplifygain; + u32 txbbgain_value; +}; + +struct ccktxbbgain { + u8 ccktxbb_valuearray[8]; +}; + +struct init_gain { + u8 xaagccore1; + u8 xbagccore1; + u8 xcagccore1; + u8 xdagccore1; + u8 cca; + +}; + +struct tx_ring { + u32 *desc; + u8 nStuckCount; + struct tx_ring *next; +} __packed; + +struct rtl8192_tx_ring { + struct tx_desc *desc; + dma_addr_t dma; + unsigned int idx; + unsigned int entries; + struct sk_buff_head queue; +}; + + + +struct rtl819x_ops { + enum nic_t nic_type; + void (*get_eeprom_size)(struct net_device *dev); + void (*init_adapter_variable)(struct net_device *dev); + void (*init_before_adapter_start)(struct net_device *dev); + bool (*initialize_adapter)(struct net_device *dev); + void (*link_change)(struct net_device *dev); + void (*tx_fill_descriptor)(struct net_device *dev, + struct tx_desc *tx_desc, + struct cb_desc *cb_desc, + struct sk_buff *skb); + void (*tx_fill_cmd_descriptor)(struct net_device *dev, + struct tx_desc_cmd *entry, + struct cb_desc *cb_desc, + struct sk_buff *skb); + bool (*rx_query_status_descriptor)(struct net_device *dev, + struct rtllib_rx_stats *stats, + struct rx_desc *pdesc, + struct sk_buff *skb); + bool (*rx_command_packet_handler)(struct net_device *dev, + struct sk_buff *skb, + struct rx_desc *pdesc); + void (*stop_adapter)(struct net_device *dev, bool reset); + void (*update_ratr_table)(struct net_device *dev); + void (*irq_enable)(struct net_device *dev); + void (*irq_disable)(struct net_device *dev); + void (*irq_clear)(struct net_device *dev); + void (*rx_enable)(struct net_device *dev); + void (*tx_enable)(struct net_device *dev); + void (*interrupt_recognized)(struct net_device *dev, + u32 *p_inta, u32 *p_intb); + bool (*TxCheckStuckHandler)(struct net_device *dev); + bool (*RxCheckStuckHandler)(struct net_device *dev); +}; + +struct r8192_priv { + struct pci_dev *pdev; + struct pci_dev *bridge_pdev; + + bool bfirst_init; + bool bfirst_after_down; + bool initialized_at_probe; + bool being_init_adapter; + bool bDriverIsGoingToUnload; + + int irq; + short irq_enabled; + + short up; + short up_first_time; + struct delayed_work update_beacon_wq; + struct delayed_work watch_dog_wq; + struct delayed_work txpower_tracking_wq; + struct delayed_work rfpath_check_wq; + struct delayed_work gpio_change_rf_wq; + struct delayed_work initialgain_operate_wq; + struct delayed_work check_hw_scan_wq; + struct delayed_work hw_scan_simu_wq; + struct delayed_work start_hw_scan_wq; + + struct workqueue_struct *priv_wq; + + struct channel_access_setting ChannelAccessSetting; + + struct mp_adapter NdisAdapter; + + struct rtl819x_ops *ops; + struct rtllib_device *rtllib; + + struct work_struct reset_wq; + + struct log_int_8190 InterruptLog; + + enum rt_customer_id CustomerID; + + + enum rt_rf_type_819xu rf_chip; + enum ic_inferiority_8192s IC_Class; + enum ht_channel_width CurrentChannelBW; + struct bb_reg_definition PHYRegDef[4]; + struct rate_adaptive rate_adaptive; + + struct ccktxbbgain cck_txbbgain_table[CCKTxBBGainTableLength]; + struct ccktxbbgain cck_txbbgain_ch14_table[CCKTxBBGainTableLength]; + + struct txbbgain_struct txbbgain_table[TxBBGainTableLength]; + + enum acm_method AcmMethod; + + struct rt_firmware *pFirmware; + enum rtl819x_loopback LoopbackMode; + enum firmware_source firmware_source; + + struct timer_list watch_dog_timer; + struct timer_list fsync_timer; + struct timer_list gpio_polling_timer; + + spinlock_t fw_scan_lock; + spinlock_t irq_lock; + spinlock_t irq_th_lock; + spinlock_t tx_lock; + spinlock_t rf_ps_lock; + spinlock_t rw_lock; + spinlock_t rt_h2c_lock; + spinlock_t rf_lock; + spinlock_t ps_lock; + + struct sk_buff_head rx_queue; + struct sk_buff_head skb_queue; + + struct tasklet_struct irq_rx_tasklet; + struct tasklet_struct irq_tx_tasklet; + struct tasklet_struct irq_prepare_beacon_tasklet; + + struct semaphore wx_sem; + struct semaphore rf_sem; + struct mutex mutex; + + struct rt_stats stats; + struct iw_statistics wstats; + struct proc_dir_entry *dir_dev; + + short (*rf_set_sens)(struct net_device *dev, short sens); + u8 (*rf_set_chan)(struct net_device *dev, u8 ch); + void (*rf_close)(struct net_device *dev); + void (*rf_init)(struct net_device *dev); + + struct rx_desc *rx_ring[MAX_RX_QUEUE]; + struct sk_buff *rx_buf[MAX_RX_QUEUE][MAX_RX_COUNT]; + dma_addr_t rx_ring_dma[MAX_RX_QUEUE]; + unsigned int rx_idx[MAX_RX_QUEUE]; + int rxringcount; + u16 rxbuffersize; + + u64 LastRxDescTSF; + + u16 EarlyRxThreshold; + u32 ReceiveConfig; + u8 AcmControl; + u8 RFProgType; + u8 retry_data; + u8 retry_rts; + u16 rts; + + struct rtl8192_tx_ring tx_ring[MAX_TX_QUEUE_COUNT]; + int txringcount; + int txbuffsize; + int txfwbuffersize; + atomic_t tx_pending[0x10]; + + u16 ShortRetryLimit; + u16 LongRetryLimit; + u32 TransmitConfig; + u8 RegCWinMin; + u8 keepAliveLevel; + + bool sw_radio_on; + bool bHwRadioOff; + bool pwrdown; + bool blinked_ingpio; + u8 polling_timer_on; + + /**********************************************************/ + + enum card_type { + PCI, MINIPCI, + CARDBUS, USB + } card_type; + + struct work_struct qos_activate; + + u8 bIbssCoordinator; + + short promisc; + short crcmon; + + int txbeaconcount; + + short chan; + short sens; + short max_sens; + u32 rx_prevlen; + + u8 ScanDelay; + bool ps_force; + + u32 irq_mask[2]; + + u8 Rf_Mode; + enum nic_t card_8192; + u8 card_8192_version; + + short enable_gpio0; + + u8 rf_type; + u8 IC_Cut; + char nick[IW_ESSID_MAX_SIZE + 1]; + + u8 RegBcnCtrlVal; + bool bHwAntDiv; + + bool bTKIPinNmodeFromReg; + bool bWEPinNmodeFromReg; + + bool bLedOpenDrain; + + u8 check_roaming_cnt; + + bool bIgnoreSilentReset; + u32 SilentResetRxSoltNum; + u32 SilentResetRxSlotIndex; + u32 SilentResetRxStuckEvent[MAX_SILENT_RESET_RX_SLOT_NUM]; + + void *scan_cmd; + u8 hwscan_bw_40; + + u16 nrxAMPDU_size; + u8 nrxAMPDU_aggr_num; + + u32 last_rxdesc_tsf_high; + u32 last_rxdesc_tsf_low; + + u16 basic_rate; + u8 short_preamble; + u8 dot11CurrentPreambleMode; + u8 slot_time; + u16 SifsTime; + + u8 RegWirelessMode; + + u8 firmware_version; + u16 FirmwareSubVersion; + u16 rf_pathmap; + bool AutoloadFailFlag; + + u8 RegPciASPM; + u8 RegAMDPciASPM; + u8 RegHwSwRfOffD3; + u8 RegSupportPciASPM; + bool bSupportASPM; + + u32 RfRegChnlVal[2]; + + u8 ShowRateMode; + u8 RATRTableBitmap; + + u8 EfuseMap[2][HWSET_MAX_SIZE_92S]; + u16 EfuseUsedBytes; + u8 EfuseUsedPercentage; + + short epromtype; + u16 eeprom_vid; + u16 eeprom_did; + u16 eeprom_svid; + u16 eeprom_smid; + u8 eeprom_CustomerID; + u16 eeprom_ChannelPlan; + u8 eeprom_version; + + u8 EEPROMRegulatory; + u8 EEPROMPwrGroup[2][3]; + u8 EEPROMOptional; + + u8 EEPROMTxPowerLevelCCK[14]; + u8 EEPROMTxPowerLevelOFDM24G[14]; + u8 EEPROMTxPowerLevelOFDM5G[24]; + u8 EEPROMRfACCKChnl1TxPwLevel[3]; + u8 EEPROMRfAOfdmChnlTxPwLevel[3]; + u8 EEPROMRfCCCKChnl1TxPwLevel[3]; + u8 EEPROMRfCOfdmChnlTxPwLevel[3]; + u16 EEPROMTxPowerDiff; + u16 EEPROMAntPwDiff; + u8 EEPROMThermalMeter; + u8 EEPROMPwDiff; + u8 EEPROMCrystalCap; + + u8 EEPROMBluetoothCoexist; + u8 EEPROMBluetoothType; + u8 EEPROMBluetoothAntNum; + u8 EEPROMBluetoothAntIsolation; + u8 EEPROMBluetoothRadioShared; + + + u8 EEPROMSupportWoWLAN; + u8 EEPROMBoardType; + u8 EEPROM_Def_Ver; + u8 EEPROMHT2T_TxPwr[6]; + u8 EEPROMTSSI_A; + u8 EEPROMTSSI_B; + u8 EEPROMTxPowerLevelCCK_V1[3]; + u8 EEPROMLegacyHTTxPowerDiff; + + u8 BluetoothCoexist; + + u8 CrystalCap; + u8 ThermalMeter[2]; + + u16 FwCmdIOMap; + u32 FwCmdIOParam; + + u8 SwChnlInProgress; + u8 SwChnlStage; + u8 SwChnlStep; + u8 SetBWModeInProgress; + + u8 nCur40MhzPrimeSC; + + u32 RfReg0Value[4]; + u8 NumTotalRFPath; + bool brfpath_rxenable[4]; + + bool bTXPowerDataReadFromEEPORM; + + u16 RegChannelPlan; + u16 ChannelPlan; + bool bChnlPlanFromHW; + + bool RegRfOff; + bool isRFOff; + bool bInPowerSaveMode; + u8 bHwRfOffAction; + + bool aspm_clkreq_enable; + u32 pci_bridge_vendor; + u8 RegHostPciASPMSetting; + u8 RegDevicePciASPMSetting; + + bool RFChangeInProgress; + bool SetRFPowerStateInProgress; + bool bdisable_nic; + + u8 pwrGroupCnt; + + u8 ThermalValue_LCK; + u8 ThermalValue_IQK; + bool bRfPiEnable; + + u32 APKoutput[2][2]; + bool bAPKdone; + + long RegE94; + long RegE9C; + long RegEB4; + long RegEBC; + + u32 RegC04; + u32 Reg874; + u32 RegC08; + u32 ADDA_backup[16]; + u32 IQK_MAC_backup[3]; + + bool SetFwCmdInProgress; + u8 CurrentFwCmdIO; + + u8 rssi_level; + + bool bInformFWDriverControlDM; + u8 PwrGroupHT20[2][14]; + u8 PwrGroupHT40[2][14]; + + u8 ThermalValue; + long EntryMinUndecoratedSmoothedPWDB; + long EntryMaxUndecoratedSmoothedPWDB; + u8 DynamicTxHighPowerLvl; + u8 LastDTPLvl; + u32 CurrentRATR0; + struct false_alarm_stats FalseAlmCnt; + + u8 DMFlag; + u8 DM_Type; + + u8 CckPwEnl; + u16 TSSI_13dBm; + u32 Pwr_Track; + u8 CCKPresentAttentuation_20Mdefault; + u8 CCKPresentAttentuation_40Mdefault; + char CCKPresentAttentuation_difference; + char CCKPresentAttentuation; + u8 bCckHighPower; + long undecorated_smoothed_pwdb; + long undecorated_smoothed_cck_adc_pwdb[4]; + + u32 MCSTxPowerLevelOriginalOffset[6]; + u32 CCKTxPowerLevelOriginalOffset; + u8 TxPowerLevelCCK[14]; + u8 TxPowerLevelCCK_A[14]; + u8 TxPowerLevelCCK_C[14]; + u8 TxPowerLevelOFDM24G[14]; + u8 TxPowerLevelOFDM5G[14]; + u8 TxPowerLevelOFDM24G_A[14]; + u8 TxPowerLevelOFDM24G_C[14]; + u8 LegacyHTTxPowerDiff; + u8 TxPowerDiff; + s8 RF_C_TxPwDiff; + s8 RF_B_TxPwDiff; + u8 RfTxPwrLevelCck[2][14]; + u8 RfTxPwrLevelOfdm1T[2][14]; + u8 RfTxPwrLevelOfdm2T[2][14]; + u8 AntennaTxPwDiff[3]; + u8 TxPwrHt20Diff[2][14]; + u8 TxPwrLegacyHtDiff[2][14]; + u8 TxPwrSafetyFlag; + u8 HT2T_TxPwr_A[14]; + u8 HT2T_TxPwr_B[14]; + u8 CurrentCckTxPwrIdx; + u8 CurrentOfdm24GTxPwrIdx; + + bool bdynamic_txpower; + bool bDynamicTxHighPower; + bool bDynamicTxLowPower; + bool bLastDTPFlag_High; + bool bLastDTPFlag_Low; + + bool bstore_last_dtpflag; + bool bstart_txctrl_bydtp; + + u8 rfa_txpowertrackingindex; + u8 rfa_txpowertrackingindex_real; + u8 rfa_txpowertracking_default; + u8 rfc_txpowertrackingindex; + u8 rfc_txpowertrackingindex_real; + u8 rfc_txpowertracking_default; + bool btxpower_tracking; + bool bcck_in_ch14; + + u8 TxPowerTrackControl; + u8 txpower_count; + bool btxpower_trackingInit; + + u8 OFDM_index[2]; + u8 CCK_index; + + u8 Record_CCK_20Mindex; + u8 Record_CCK_40Mindex; + + struct init_gain initgain_backup; + u8 DefaultInitialGain[4]; + bool bis_any_nonbepkts; + bool bcurrent_turbo_EDCA; + bool bis_cur_rdlstate; + + bool bCCKinCH14; + + u8 MidHighPwrTHR_L1; + u8 MidHighPwrTHR_L2; + + bool bfsync_processing; + u32 rate_record; + u32 rateCountDiffRecord; + u32 ContiuneDiffCount; + bool bswitch_fsync; + u8 framesync; + u32 framesyncC34; + u8 framesyncMonitor; + + bool bDMInitialGainEnable; + bool MutualAuthenticationFail; + + bool bDisableFrameBursting; + + u32 reset_count; + bool bpbc_pressed; + + u32 txpower_checkcnt; + u32 txpower_tracking_callback_cnt; + u8 thermal_read_val[40]; + u8 thermal_readback_index; + u32 ccktxpower_adjustcnt_not_ch14; + u32 ccktxpower_adjustcnt_ch14; + + enum reset_type ResetProgress; + bool bForcedSilentReset; + bool bDisableNormalResetCheck; + u16 TxCounter; + u16 RxCounter; + int IrpPendingCount; + bool bResetInProgress; + bool force_reset; + bool force_lps; + u8 InitialGainOperateType; + + bool chan_forced; + bool bSingleCarrier; + bool RegBoard; + bool bCckContTx; + bool bOfdmContTx; + bool bStartContTx; + u8 RegPaModel; + u8 btMpCckTxPower; + u8 btMpOfdmTxPower; + + u32 MptActType; + u32 MptIoOffset; + u32 MptIoValue; + u32 MptRfPath; + + u32 MptBandWidth; + u32 MptRateIndex; + u8 MptChannelToSw; + u32 MptRCR; + + u8 PwrDomainProtect; + u8 H2CTxCmdSeq; + + +}; + +extern const struct ethtool_ops rtl819x_ethtool_ops; + +void rtl8192_tx_cmd(struct net_device *dev, struct sk_buff *skb); +short rtl8192_tx(struct net_device *dev, struct sk_buff *skb); + +u8 read_nic_io_byte(struct net_device *dev, int x); +u32 read_nic_io_dword(struct net_device *dev, int x); +u16 read_nic_io_word(struct net_device *dev, int x) ; +void write_nic_io_byte(struct net_device *dev, int x, u8 y); +void write_nic_io_word(struct net_device *dev, int x, u16 y); +void write_nic_io_dword(struct net_device *dev, int x, u32 y); + +u8 read_nic_byte(struct net_device *dev, int x); +u32 read_nic_dword(struct net_device *dev, int x); +u16 read_nic_word(struct net_device *dev, int x) ; +void write_nic_byte(struct net_device *dev, int x, u8 y); +void write_nic_word(struct net_device *dev, int x, u16 y); +void write_nic_dword(struct net_device *dev, int x, u32 y); + +void force_pci_posting(struct net_device *dev); + +void rtl8192_rx_enable(struct net_device *); +void rtl8192_tx_enable(struct net_device *); + +int rtl8192_hard_start_xmit(struct sk_buff *skb, struct net_device *dev); +void rtl8192_hard_data_xmit(struct sk_buff *skb, struct net_device *dev, + int rate); +void rtl8192_data_hard_stop(struct net_device *dev); +void rtl8192_data_hard_resume(struct net_device *dev); +void rtl8192_restart(void *data); +void rtl819x_watchdog_wqcallback(void *data); +void rtl8192_hw_sleep_wq(void *data); +void watch_dog_timer_callback(unsigned long data); +void rtl8192_irq_rx_tasklet(struct r8192_priv *priv); +void rtl8192_irq_tx_tasklet(struct r8192_priv *priv); +int rtl8192_down(struct net_device *dev, bool shutdownrf); +int rtl8192_up(struct net_device *dev); +void rtl8192_commit(struct net_device *dev); +void rtl8192_set_chan(struct net_device *dev, short ch); + +void check_rfctrl_gpio_timer(unsigned long data); + +void rtl8192_hw_wakeup_wq(void *data); +irqreturn_type rtl8192_interrupt(int irq, void *netdev, struct pt_regs *regs); + +short rtl8192_pci_initdescring(struct net_device *dev); + +void rtl8192_cancel_deferred_work(struct r8192_priv *priv); + +int _rtl8192_up(struct net_device *dev, bool is_silent_reset); + +short rtl8192_is_tx_queue_empty(struct net_device *dev); +void rtl8192_irq_disable(struct net_device *dev); + +void rtl8192_tx_timeout(struct net_device *dev); +void rtl8192_pci_resetdescring(struct net_device *dev); +void rtl8192_SetWirelessMode(struct net_device *dev, u8 wireless_mode); +void rtl8192_irq_enable(struct net_device *dev); +void rtl8192_config_rate(struct net_device *dev, u16 *rate_config); +void rtl8192_update_cap(struct net_device *dev, u16 cap); +void rtl8192_irq_disable(struct net_device *dev); + +void rtl819x_UpdateRxPktTimeStamp(struct net_device *dev, + struct rtllib_rx_stats *stats); +long rtl819x_translate_todbm(struct r8192_priv *priv, u8 signal_strength_index); +void rtl819x_update_rxsignalstatistics8190pci(struct r8192_priv *priv, + struct rtllib_rx_stats *pprevious_stats); +u8 rtl819x_evm_dbtopercentage(char value); +void rtl819x_process_cck_rxpathsel(struct r8192_priv *priv, + struct rtllib_rx_stats *pprevious_stats); +u8 rtl819x_query_rxpwrpercentage(char antpower); +void rtl8192_record_rxdesc_forlateruse(struct rtllib_rx_stats *psrc_stats, + struct rtllib_rx_stats *ptarget_stats); +bool NicIFEnableNIC(struct net_device *dev); +bool NicIFDisableNIC(struct net_device *dev); + +bool MgntActSet_RF_State(struct net_device *dev, + enum rt_rf_power_state StateToSet, + RT_RF_CHANGE_SOURCE ChangeSource, + bool ProtectOrNot); +void ActUpdateChannelAccessSetting(struct net_device *dev, + enum wireless_mode WirelessMode, + struct channel_access_setting *ChnlAccessSetting); + +/* proc stuff from rtl_debug.c */ +void rtl8192_proc_init_one(struct net_device *dev); +void rtl8192_proc_remove_one(struct net_device *dev); +void rtl8192_proc_module_init(void); +void rtl8192_proc_module_remove(void); + +#endif diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_crypto.h b/drivers/staging/rtl8192e/rtl8192e/rtl_crypto.h new file mode 100644 index 000000000000..ee57c0f4fa69 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_crypto.h @@ -0,0 +1,382 @@ +/* + * Scatterlist Cryptographic API. + * + * Copyright (c) 2002 James Morris <jmorris@intercode.com.au> + * Copyright (c) 2002 David S. Miller (davem@redhat.com) + * + * Portions derived from Cryptoapi, by Alexander Kjeldaas <astor@fast.no> + * and Nettle, by Niels Mé°ˆler. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ +#ifndef _LINUX_CRYPTO_H +#define _LINUX_CRYPTO_H + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/list.h> +#include <linux/string.h> +#include <asm/page.h> +#include <linux/errno.h> + +#define crypto_register_alg crypto_register_alg_rsl +#define crypto_unregister_alg crypto_unregister_alg_rsl +#define crypto_alloc_tfm crypto_alloc_tfm_rsl +#define crypto_free_tfm crypto_free_tfm_rsl +#define crypto_alg_available crypto_alg_available_rsl + +/* + * Algorithm masks and types. + */ +#define CRYPTO_ALG_TYPE_MASK 0x000000ff +#define CRYPTO_ALG_TYPE_CIPHER 0x00000001 +#define CRYPTO_ALG_TYPE_DIGEST 0x00000002 +#define CRYPTO_ALG_TYPE_COMPRESS 0x00000004 + +/* + * Transform masks and values (for crt_flags). + */ +#define CRYPTO_TFM_MODE_MASK 0x000000ff +#define CRYPTO_TFM_REQ_MASK 0x000fff00 +#define CRYPTO_TFM_RES_MASK 0xfff00000 + +#define CRYPTO_TFM_MODE_ECB 0x00000001 +#define CRYPTO_TFM_MODE_CBC 0x00000002 +#define CRYPTO_TFM_MODE_CFB 0x00000004 +#define CRYPTO_TFM_MODE_CTR 0x00000008 + +#define CRYPTO_TFM_REQ_WEAK_KEY 0x00000100 +#define CRYPTO_TFM_RES_WEAK_KEY 0x00100000 +#define CRYPTO_TFM_RES_BAD_KEY_LEN 0x00200000 +#define CRYPTO_TFM_RES_BAD_KEY_SCHED 0x00400000 +#define CRYPTO_TFM_RES_BAD_BLOCK_LEN 0x00800000 +#define CRYPTO_TFM_RES_BAD_FLAGS 0x01000000 + +/* + * Miscellaneous stuff. + */ +#define CRYPTO_UNSPEC 0 +#define CRYPTO_MAX_ALG_NAME 64 + +struct scatterlist; + +/* + * Algorithms: modular crypto algorithm implementations, managed + * via crypto_register_alg() and crypto_unregister_alg(). + */ +struct cipher_alg { + unsigned int cia_min_keysize; + unsigned int cia_max_keysize; + int (*cia_setkey)(void *ctx, const u8 *key, + unsigned int keylen, u32 *flags); + void (*cia_encrypt)(void *ctx, u8 *dst, const u8 *src); + void (*cia_decrypt)(void *ctx, u8 *dst, const u8 *src); +}; + +struct digest_alg { + unsigned int dia_digestsize; + void (*dia_init)(void *ctx); + void (*dia_update)(void *ctx, const u8 *data, unsigned int len); + void (*dia_final)(void *ctx, u8 *out); + int (*dia_setkey)(void *ctx, const u8 *key, + unsigned int keylen, u32 *flags); +}; + +struct compress_alg { + int (*coa_init)(void *ctx); + void (*coa_exit)(void *ctx); + int (*coa_compress)(void *ctx, const u8 *src, unsigned int slen, + u8 *dst, unsigned int *dlen); + int (*coa_decompress)(void *ctx, const u8 *src, unsigned int slen, + u8 *dst, unsigned int *dlen); +}; + +#define cra_cipher cra_u.cipher +#define cra_digest cra_u.digest +#define cra_compress cra_u.compress + +struct crypto_alg { + struct list_head cra_list; + u32 cra_flags; + unsigned int cra_blocksize; + unsigned int cra_ctxsize; + const char cra_name[CRYPTO_MAX_ALG_NAME]; + + union { + struct cipher_alg cipher; + struct digest_alg digest; + struct compress_alg compress; + } cra_u; + + struct module *cra_module; +}; + +/* + * Algorithm registration interface. + */ +int crypto_register_alg(struct crypto_alg *alg); +int crypto_unregister_alg(struct crypto_alg *alg); + +/* + * Algorithm query interface. + */ +int crypto_alg_available(const char *name, u32 flags); + +/* + * Transforms: user-instantiated objects which encapsulate algorithms + * and core processing logic. Managed via crypto_alloc_tfm() and + * crypto_free_tfm(), as well as the various helpers below. + */ +struct crypto_tfm; + +struct cipher_tfm { + void *cit_iv; + unsigned int cit_ivsize; + u32 cit_mode; + int (*cit_setkey)(struct crypto_tfm *tfm, + const u8 *key, unsigned int keylen); + int (*cit_encrypt)(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes); + int (*cit_encrypt_iv)(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes, u8 *iv); + int (*cit_decrypt)(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes); + int (*cit_decrypt_iv)(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes, u8 *iv); + void (*cit_xor_block)(u8 *dst, const u8 *src); +}; + +struct digest_tfm { + void (*dit_init)(struct crypto_tfm *tfm); + void (*dit_update)(struct crypto_tfm *tfm, + struct scatterlist *sg, unsigned int nsg); + void (*dit_final)(struct crypto_tfm *tfm, u8 *out); + void (*dit_digest)(struct crypto_tfm *tfm, struct scatterlist *sg, + unsigned int nsg, u8 *out); + int (*dit_setkey)(struct crypto_tfm *tfm, + const u8 *key, unsigned int keylen); +}; + +struct compress_tfm { + int (*cot_compress)(struct crypto_tfm *tfm, + const u8 *src, unsigned int slen, + u8 *dst, unsigned int *dlen); + int (*cot_decompress)(struct crypto_tfm *tfm, + const u8 *src, unsigned int slen, + u8 *dst, unsigned int *dlen); +}; + +#define crt_cipher crt_u.cipher +#define crt_digest crt_u.digest +#define crt_compress crt_u.compress + +struct crypto_tfm { + + u32 crt_flags; + + union { + struct cipher_tfm cipher; + struct digest_tfm digest; + struct compress_tfm compress; + } crt_u; + + struct crypto_alg *__crt_alg; +}; + +/* + * Transform user interface. + */ + +/* + * crypto_alloc_tfm() will first attempt to locate an already loaded algorithm. + * If that fails and the kernel supports dynamically loadable modules, it + * will then attempt to load a module of the same name or alias. A refcount + * is grabbed on the algorithm which is then associated with the new transform. + * + * crypto_free_tfm() frees up the transform and any associated resources, + * then drops the refcount on the associated algorithm. + */ +struct crypto_tfm *crypto_alloc_tfm(const char *alg_name, u32 tfm_flags); +void crypto_free_tfm(struct crypto_tfm *tfm); + +/* + * Transform helpers which query the underlying algorithm. + */ +static inline const char *crypto_tfm_alg_name(struct crypto_tfm *tfm) +{ + return tfm->__crt_alg->cra_name; +} + +static inline const char *crypto_tfm_alg_modname(struct crypto_tfm *tfm) +{ + struct crypto_alg *alg = tfm->__crt_alg; + + if (alg->cra_module) + return alg->cra_module->name; + else + return NULL; +} + +static inline u32 crypto_tfm_alg_type(struct crypto_tfm *tfm) +{ + return tfm->__crt_alg->cra_flags & CRYPTO_ALG_TYPE_MASK; +} + +static inline unsigned int crypto_tfm_alg_min_keysize(struct crypto_tfm *tfm) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + return tfm->__crt_alg->cra_cipher.cia_min_keysize; +} + +static inline unsigned int crypto_tfm_alg_max_keysize(struct crypto_tfm *tfm) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + return tfm->__crt_alg->cra_cipher.cia_max_keysize; +} + +static inline unsigned int crypto_tfm_alg_ivsize(struct crypto_tfm *tfm) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + return tfm->crt_cipher.cit_ivsize; +} + +static inline unsigned int crypto_tfm_alg_blocksize(struct crypto_tfm *tfm) +{ + return tfm->__crt_alg->cra_blocksize; +} + +static inline unsigned int crypto_tfm_alg_digestsize(struct crypto_tfm *tfm) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST); + return tfm->__crt_alg->cra_digest.dia_digestsize; +} + +/* + * API wrappers. + */ +static inline void crypto_digest_init(struct crypto_tfm *tfm) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST); + tfm->crt_digest.dit_init(tfm); +} + +static inline void crypto_digest_update(struct crypto_tfm *tfm, + struct scatterlist *sg, + unsigned int nsg) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST); + tfm->crt_digest.dit_update(tfm, sg, nsg); +} + +static inline void crypto_digest_final(struct crypto_tfm *tfm, u8 *out) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST); + tfm->crt_digest.dit_final(tfm, out); +} + +static inline void crypto_digest_digest(struct crypto_tfm *tfm, + struct scatterlist *sg, + unsigned int nsg, u8 *out) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST); + tfm->crt_digest.dit_digest(tfm, sg, nsg, out); +} + +static inline int crypto_digest_setkey(struct crypto_tfm *tfm, + const u8 *key, unsigned int keylen) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST); + if (tfm->crt_digest.dit_setkey == NULL) + return -ENOSYS; + return tfm->crt_digest.dit_setkey(tfm, key, keylen); +} + +static inline int crypto_cipher_setkey(struct crypto_tfm *tfm, + const u8 *key, unsigned int keylen) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + return tfm->crt_cipher.cit_setkey(tfm, key, keylen); +} + +static inline int crypto_cipher_encrypt(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + return tfm->crt_cipher.cit_encrypt(tfm, dst, src, nbytes); +} + +static inline int crypto_cipher_encrypt_iv(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes, u8 *iv) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + BUG_ON(tfm->crt_cipher.cit_mode == CRYPTO_TFM_MODE_ECB); + return tfm->crt_cipher.cit_encrypt_iv(tfm, dst, src, nbytes, iv); +} + +static inline int crypto_cipher_decrypt(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + return tfm->crt_cipher.cit_decrypt(tfm, dst, src, nbytes); +} + +static inline int crypto_cipher_decrypt_iv(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes, u8 *iv) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + BUG_ON(tfm->crt_cipher.cit_mode == CRYPTO_TFM_MODE_ECB); + return tfm->crt_cipher.cit_decrypt_iv(tfm, dst, src, nbytes, iv); +} + +static inline void crypto_cipher_set_iv(struct crypto_tfm *tfm, + const u8 *src, unsigned int len) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + memcpy(tfm->crt_cipher.cit_iv, src, len); +} + +static inline void crypto_cipher_get_iv(struct crypto_tfm *tfm, + u8 *dst, unsigned int len) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + memcpy(dst, tfm->crt_cipher.cit_iv, len); +} + +static inline int crypto_comp_compress(struct crypto_tfm *tfm, + const u8 *src, unsigned int slen, + u8 *dst, unsigned int *dlen) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_COMPRESS); + return tfm->crt_compress.cot_compress(tfm, src, slen, dst, dlen); +} + +static inline int crypto_comp_decompress(struct crypto_tfm *tfm, + const u8 *src, unsigned int slen, + u8 *dst, unsigned int *dlen) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_COMPRESS); + return tfm->crt_compress.cot_decompress(tfm, src, slen, dst, dlen); +} + +#endif /* _LINUX_CRYPTO_H */ diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_debug.c b/drivers/staging/rtl8192e/rtl8192e/rtl_debug.c new file mode 100644 index 000000000000..c19b14cd6f77 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_debug.c @@ -0,0 +1,1029 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * Based on the r8180 driver, which is: + * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ +#include "rtl_core.h" +#include "r8192E_phy.h" +#include "r8192E_phyreg.h" +#include "r8190P_rtl8256.h" /* RTL8225 Radio frontend */ +#include "r8192E_cmdpkt.h" + +/**************************************************************************** + -----------------------------PROCFS STUFF------------------------- +*****************************************************************************/ +/*This part is related to PROC, which will record some statistics. */ +static struct proc_dir_entry *rtl8192_proc; + +static int proc_get_stats_ap(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + struct rtllib_network *target; + int len = 0; + + list_for_each_entry(target, &ieee->network_list, list) { + + len += snprintf(page + len, count - len, + "%s ", target->ssid); + + if (target->wpa_ie_len > 0 || target->rsn_ie_len > 0) + len += snprintf(page + len, count - len, + "WPA\n"); + else + len += snprintf(page + len, count - len, + "non_WPA\n"); + + } + + *eof = 1; + return len; +} + +static int proc_get_registers_0(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + + int len = 0; + int i, n, page0; + + int max = 0xff; + page0 = 0x000; + + len += snprintf(page + len, count - len, + "\n####################page %x##################\n ", + (page0>>8)); + len += snprintf(page + len, count - len, + "\nD: OF > 00 01 02 03 04 05 06 07 08 09 0A 0B " + "0C 0D 0E 0F"); + for (n = 0; n <= max;) { + len += snprintf(page + len, count - len, "\nD: %2x > ", n); + for (i = 0; i < 16 && n <= max; n++, i++) + len += snprintf(page + len, count - len, + "%2.2x ", read_nic_byte(dev, + (page0 | n))); + } + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; + +} +static int proc_get_registers_1(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + + int len = 0; + int i, n, page0; + + int max = 0xff; + page0 = 0x100; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n ", + (page0>>8)); + len += snprintf(page + len, count - len, + "\nD: OF > 00 01 02 03 04 05 06 07 08 09 0A 0B " + "0C 0D 0E 0F"); + for (n = 0; n <= max;) { + len += snprintf(page + len, count - len, + "\nD: %2x > ", n); + for (i = 0; i < 16 && n <= max; i++, n++) + len += snprintf(page + len, count - len, + "%2.2x ", read_nic_byte(dev, + (page0 | n))); + } + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; + +} +static int proc_get_registers_2(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + + int len = 0; + int i, n, page0; + + int max = 0xff; + page0 = 0x200; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n ", + (page0 >> 8)); + len += snprintf(page + len, count - len, + "\nD: OF > 00 01 02 03 04 05 06 07 08 09 0A 0B 0C " + "0D 0E 0F"); + for (n = 0; n <= max;) { + len += snprintf(page + len, count - len, + "\nD: %2x > ", n); + for (i = 0; i < 16 && n <= max; i++, n++) + len += snprintf(page + len, count - len, + "%2.2x ", read_nic_byte(dev, + (page0 | n))); + } + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; + +} +static int proc_get_registers_3(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + + int len = 0; + int i, n, page0; + + int max = 0xff; + page0 = 0x300; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n ", + (page0>>8)); + len += snprintf(page + len, count - len, + "\nD: OF > 00 01 02 03 04 05 06 07 08 09 0A 0B " + "0C 0D 0E 0F"); + for (n = 0; n <= max;) { + len += snprintf(page + len, count - len, + "\nD: %2x > ", n); + for (i = 0; i < 16 && n <= max; i++, n++) + len += snprintf(page + len, count - len, + "%2.2x ", read_nic_byte(dev, + (page0 | n))); + } + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; + +} +static int proc_get_registers_4(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + + int len = 0; + int i, n, page0; + + int max = 0xff; + page0 = 0x400; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n ", + (page0>>8)); + len += snprintf(page + len, count - len, + "\nD: OF > 00 01 02 03 04 05 06 07 08 09 0A 0B " + "0C 0D 0E 0F"); + for (n = 0; n <= max;) { + len += snprintf(page + len, count - len, + "\nD: %2x > ", n); + for (i = 0; i < 16 && n <= max; i++, n++) + len += snprintf(page + len, count - len, + "%2.2x ", read_nic_byte(dev, + (page0 | n))); + } + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; + +} +static int proc_get_registers_5(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + + int len = 0; + int i, n, page0; + + int max = 0xff; + page0 = 0x500; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n ", + (page0 >> 8)); + len += snprintf(page + len, count - len, + "\nD: OF > 00 01 02 03 04 05 06 07 08 09 0A 0B " + "0C 0D 0E 0F"); + for (n = 0; n <= max;) { + len += snprintf(page + len, count - len, + "\nD: %2x > ", n); + for (i = 0; i < 16 && n <= max; i++, n++) + len += snprintf(page + len, count - len, + "%2.2x ", read_nic_byte(dev, + (page0 | n))); + } + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; + +} +static int proc_get_registers_6(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + + int len = 0; + int i, n, page0; + + int max = 0xff; + page0 = 0x600; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n ", + (page0>>8)); + len += snprintf(page + len, count - len, + "\nD: OF > 00 01 02 03 04 05 06 07 08 09 0A 0B " + "0C 0D 0E 0F"); + for (n = 0; n <= max;) { + len += snprintf(page + len, count - len, + "\nD: %2x > ", n); + for (i = 0; i < 16 && n <= max; i++, n++) + len += snprintf(page + len, count - len, + "%2.2x ", read_nic_byte(dev, + (page0 | n))); + } + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; + +} +static int proc_get_registers_7(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + + int len = 0; + int i, n, page0; + + int max = 0xff; + page0 = 0x700; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n ", + (page0 >> 8)); + len += snprintf(page + len, count - len, + "\nD: OF > 00 01 02 03 04 05 06 07 08 09 0A 0B 0C " + "0D 0E 0F"); + for (n = 0; n <= max;) { + len += snprintf(page + len, count - len, + "\nD: %2x > ", n); + for (i = 0; i < 16 && n <= max; i++, n++) + len += snprintf(page + len, count - len, + "%2.2x ", read_nic_byte(dev, + (page0 | n))); + } + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; + +} +static int proc_get_registers_8(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + + int len = 0; + int i, n, page0; + + int max = 0xff; + page0 = 0x800; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n", + (page0 >> 8)); + for (n = 0; n <= max;) { + len += snprintf(page + len, count - len, "\nD: %2x > ", n); + for (i = 0; i < 4 && n <= max; n += 4, i++) + len += snprintf(page + len, count - len, + "%8.8x ", rtl8192_QueryBBReg(dev, + (page0 | n), bMaskDWord)); + } + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; + +} +static int proc_get_registers_9(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + + int len = 0; + int i, n, page0; + + int max = 0xff; + page0 = 0x900; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n", + (page0>>8)); + for (n = 0; n <= max;) { + len += snprintf(page + len, count - len, "\nD: %2x > ", n); + for (i = 0; i < 4 && n <= max; n += 4, i++) + len += snprintf(page + len, count - len, + "%8.8x ", rtl8192_QueryBBReg(dev, + (page0 | n), bMaskDWord)); + } + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; +} +static int proc_get_registers_a(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + + int len = 0; + int i, n, page0; + + int max = 0xff; + page0 = 0xa00; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n", + (page0>>8)); + for (n = 0; n <= max;) { + len += snprintf(page + len, count - len, "\nD: %2x > ", n); + for (i = 0; i < 4 && n <= max; n += 4, i++) + len += snprintf(page + len, count - len, + "%8.8x ", rtl8192_QueryBBReg(dev, + (page0 | n), bMaskDWord)); + } + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; +} +static int proc_get_registers_b(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + + int len = 0; + int i, n, page0; + + int max = 0xff; + page0 = 0xb00; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n", + (page0 >> 8)); + for (n = 0; n <= max;) { + len += snprintf(page + len, count - len, "\nD: %2x > ", n); + for (i = 0; i < 4 && n <= max; n += 4, i++) + len += snprintf(page + len, count - len, + "%8.8x ", rtl8192_QueryBBReg(dev, + (page0 | n), bMaskDWord)); + } + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; +} +static int proc_get_registers_c(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + + int len = 0; + int i, n, page0; + + int max = 0xff; + page0 = 0xc00; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n", + (page0>>8)); + for (n = 0; n <= max;) { + len += snprintf(page + len, count - len, "\nD: %2x > ", n); + for (i = 0; i < 4 && n <= max; n += 4, i++) + len += snprintf(page + len, count - len, + "%8.8x ", rtl8192_QueryBBReg(dev, + (page0 | n), bMaskDWord)); + } + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; +} +static int proc_get_registers_d(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + + int len = 0; + int i, n, page0; + + int max = 0xff; + page0 = 0xd00; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n", + (page0>>8)); + for (n = 0; n <= max;) { + len += snprintf(page + len, count - len, "\nD: %2x > ", n); + for (i = 0; i < 4 && n <= max; n += 4, i++) + len += snprintf(page + len, count - len, + "%8.8x ", rtl8192_QueryBBReg(dev, + (page0 | n), bMaskDWord)); + } + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; +} +static int proc_get_registers_e(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + + int len = 0; + int i, n, page0; + + int max = 0xff; + page0 = 0xe00; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n", + (page0>>8)); + for (n = 0; n <= max;) { + len += snprintf(page + len, count - len, "\nD: %2x > ", n); + for (i = 0; i < 4 && n <= max; n += 4, i++) + len += snprintf(page + len, count - len, + "%8.8x ", rtl8192_QueryBBReg(dev, + (page0 | n), bMaskDWord)); + } + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; +} + +static int proc_get_reg_rf_a(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + + int len = 0; + int i, n; + + int max = 0xff; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n#################### RF-A ##################\n "); + for (n = 0; n <= max;) { + len += snprintf(page + len, count - len, "\nD: %2x > ", n); + for (i = 0; i < 4 && n <= max; n += 4, i++) + len += snprintf(page + len, count - len, + "%8.8x ", rtl8192_phy_QueryRFReg(dev, + (enum rf90_radio_path)RF90_PATH_A, n, + bMaskDWord)); + } + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; +} + +static int proc_get_reg_rf_b(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + + int len = 0; + int i, n; + + int max = 0xff; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n#################### RF-B ##################\n "); + for (n = 0; n <= max;) { + len += snprintf(page + len, count - len, "\nD: %2x > ", n); + for (i = 0; i < 4 && n <= max; n += 4, i++) + len += snprintf(page + len, count - len, + "%8.8x ", rtl8192_phy_QueryRFReg(dev, + (enum rf90_radio_path)RF90_PATH_B, n, + bMaskDWord)); + } + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; +} + +static int proc_get_reg_rf_c(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + + int len = 0; + int i, n; + + int max = 0xff; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n#################### RF-C ##################\n"); + for (n = 0; n <= max;) { + len += snprintf(page + len, count - len, "\nD: %2x > ", n); + for (i = 0; i < 4 && n <= max; n += 4, i++) + len += snprintf(page + len, count - len, + "%8.8x ", rtl8192_phy_QueryRFReg(dev, + (enum rf90_radio_path)RF90_PATH_C, n, + bMaskDWord)); + } + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; +} + +static int proc_get_reg_rf_d(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + + int len = 0; + int i, n; + + int max = 0xff; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n#################### RF-D ##################\n "); + for (n = 0; n <= max;) { + len += snprintf(page + len, count - len, "\nD: %2x > ", n); + for (i = 0; i < 4 && n <= max; n += 4, i++) + len += snprintf(page + len, count - len, + "%8.8x ", rtl8192_phy_QueryRFReg(dev, + (enum rf90_radio_path)RF90_PATH_D, n, + bMaskDWord)); + } + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; +} + +static int proc_get_cam_register_1(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + u32 target_command = 0; + u32 target_content = 0; + u8 entry_i = 0; + u32 ulStatus; + int len = 0; + int i = 100, j = 0; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n#################### SECURITY CAM (0-10) ######" + "############\n "); + for (j = 0; j < 11; j++) { + len += snprintf(page + len, count - len, "\nD: %2x > ", j); + for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) { + target_command = entry_i+CAM_CONTENT_COUNT*j; + target_command = target_command | BIT31; + + while ((i--) >= 0) { + ulStatus = read_nic_dword(dev, RWCAM); + if (ulStatus & BIT31) + continue; + else + break; + } + write_nic_dword(dev, RWCAM, target_command); + target_content = read_nic_dword(dev, RCAMO); + len += snprintf(page + len, count - len, "%8.8x ", + target_content); + } + } + + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; +} + +static int proc_get_cam_register_2(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + u32 target_command = 0; + u32 target_content = 0; + u8 entry_i = 0; + u32 ulStatus; + int len = 0; + int i = 100, j = 0; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n#################### SECURITY CAM (11-21) " + "##################\n "); + for (j = 11; j < 22; j++) { + len += snprintf(page + len, count - len, "\nD: %2x > ", j); + for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) { + target_command = entry_i + CAM_CONTENT_COUNT * j; + target_command = target_command | BIT31; + + while ((i--) >= 0) { + ulStatus = read_nic_dword(dev, RWCAM); + if (ulStatus & BIT31) + continue; + else + break; + } + write_nic_dword(dev, RWCAM, target_command); + target_content = read_nic_dword(dev, RCAMO); + len += snprintf(page + len, count - len, "%8.8x ", + target_content); + } + } + + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; +} + +static int proc_get_cam_register_3(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + u32 target_command = 0; + u32 target_content = 0; + u8 entry_i = 0; + u32 ulStatus; + int len = 0; + int i = 100, j = 0; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n#################### SECURITY CAM (22-31) ######" + "############\n "); + for (j = 22; j < TOTAL_CAM_ENTRY; j++) { + len += snprintf(page + len, count - len, "\nD: %2x > ", j); + for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) { + target_command = entry_i + CAM_CONTENT_COUNT * j; + target_command = target_command | BIT31; + + while ((i--) >= 0) { + ulStatus = read_nic_dword(dev, RWCAM); + if (ulStatus & BIT31) + continue; + else + break; + } + write_nic_dword(dev, RWCAM, target_command); + target_content = read_nic_dword(dev, RCAMO); + len += snprintf(page + len, count - len, "%8.8x ", + target_content); + } + } + + len += snprintf(page + len, count - len, "\n"); + *eof = 1; + return len; +} +static int proc_get_stats_tx(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + + int len = 0; + + len += snprintf(page + len, count - len, + "TX VI priority ok int: %lu\n" + "TX VO priority ok int: %lu\n" + "TX BE priority ok int: %lu\n" + "TX BK priority ok int: %lu\n" + "TX MANAGE priority ok int: %lu\n" + "TX BEACON priority ok int: %lu\n" + "TX BEACON priority error int: %lu\n" + "TX CMDPKT priority ok int: %lu\n" + "TX queue stopped?: %d\n" + "TX fifo overflow: %lu\n" + "TX total data packets %lu\n" + "TX total data bytes :%lu\n", + priv->stats.txviokint, + priv->stats.txvookint, + priv->stats.txbeokint, + priv->stats.txbkokint, + priv->stats.txmanageokint, + priv->stats.txbeaconokint, + priv->stats.txbeaconerr, + priv->stats.txcmdpktokint, + netif_queue_stopped(dev), + priv->stats.txoverflow, + priv->rtllib->stats.tx_packets, + priv->rtllib->stats.tx_bytes + + + ); + + *eof = 1; + return len; +} + + + +static int proc_get_stats_rx(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + + int len = 0; + + len += snprintf(page + len, count - len, + "RX packets: %lu\n" + "RX data crc err: %lu\n" + "RX mgmt crc err: %lu\n" + "RX desc err: %lu\n" + "RX rx overflow error: %lu\n", + priv->stats.rxint, + priv->stats.rxdatacrcerr, + priv->stats.rxmgmtcrcerr, + priv->stats.rxrdu, + priv->stats.rxoverflow); + + *eof = 1; + return len; +} + +void rtl8192_proc_module_init(void) +{ + RT_TRACE(COMP_INIT, "Initializing proc filesystem"); + rtl8192_proc = create_proc_entry(DRV_NAME, S_IFDIR, init_net.proc_net); +} + + +void rtl8192_proc_module_remove(void) +{ + remove_proc_entry(DRV_NAME, init_net.proc_net); +} + + +void rtl8192_proc_remove_one(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + + printk(KERN_INFO "dev name %s\n", dev->name); + + if (priv->dir_dev) { + remove_proc_entry("stats-tx", priv->dir_dev); + remove_proc_entry("stats-rx", priv->dir_dev); + remove_proc_entry("stats-ap", priv->dir_dev); + remove_proc_entry("registers-0", priv->dir_dev); + remove_proc_entry("registers-1", priv->dir_dev); + remove_proc_entry("registers-2", priv->dir_dev); + remove_proc_entry("registers-3", priv->dir_dev); + remove_proc_entry("registers-4", priv->dir_dev); + remove_proc_entry("registers-5", priv->dir_dev); + remove_proc_entry("registers-6", priv->dir_dev); + remove_proc_entry("registers-7", priv->dir_dev); + remove_proc_entry("registers-8", priv->dir_dev); + remove_proc_entry("registers-9", priv->dir_dev); + remove_proc_entry("registers-a", priv->dir_dev); + remove_proc_entry("registers-b", priv->dir_dev); + remove_proc_entry("registers-c", priv->dir_dev); + remove_proc_entry("registers-d", priv->dir_dev); + remove_proc_entry("registers-e", priv->dir_dev); + remove_proc_entry("RF-A", priv->dir_dev); + remove_proc_entry("RF-B", priv->dir_dev); + remove_proc_entry("RF-C", priv->dir_dev); + remove_proc_entry("RF-D", priv->dir_dev); + remove_proc_entry("SEC-CAM-1", priv->dir_dev); + remove_proc_entry("SEC-CAM-2", priv->dir_dev); + remove_proc_entry("SEC-CAM-3", priv->dir_dev); + remove_proc_entry("wlan0", rtl8192_proc); + priv->dir_dev = NULL; + } +} + + +void rtl8192_proc_init_one(struct net_device *dev) +{ + struct proc_dir_entry *e; + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + + priv->dir_dev = create_proc_entry(dev->name, + S_IFDIR | S_IRUGO | S_IXUGO, + rtl8192_proc); + if (!priv->dir_dev) { + RT_TRACE(COMP_ERR, "Unable to initialize /proc/net/rtl8192" + "/%s\n", dev->name); + return; + } + e = create_proc_read_entry("stats-rx", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_stats_rx, dev); + + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/stats-rx\n", + dev->name); + + e = create_proc_read_entry("stats-tx", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_stats_tx, dev); + + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/stats-tx\n", + dev->name); + + e = create_proc_read_entry("stats-ap", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_stats_ap, dev); + + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/stats-ap\n", + dev->name); + + e = create_proc_read_entry("registers-0", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_0, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-0\n", + dev->name); + e = create_proc_read_entry("registers-1", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_1, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-1\n", + dev->name); + e = create_proc_read_entry("registers-2", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_2, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-2\n", + dev->name); + e = create_proc_read_entry("registers-3", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_3, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-3\n", + dev->name); + e = create_proc_read_entry("registers-4", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_4, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-4\n", + dev->name); + e = create_proc_read_entry("registers-5", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_5, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-5\n", + dev->name); + e = create_proc_read_entry("registers-6", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_6, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-6\n", + dev->name); + e = create_proc_read_entry("registers-7", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_7, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-7\n", + dev->name); + e = create_proc_read_entry("registers-8", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_8, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-8\n", + dev->name); + e = create_proc_read_entry("registers-9", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_9, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-9\n", + dev->name); + e = create_proc_read_entry("registers-a", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_a, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-a\n", + dev->name); + e = create_proc_read_entry("registers-b", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_b, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-b\n", + dev->name); + e = create_proc_read_entry("registers-c", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_c, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-c\n", + dev->name); + e = create_proc_read_entry("registers-d", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_d, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-d\n", + dev->name); + e = create_proc_read_entry("registers-e", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_e, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-e\n", + dev->name); + e = create_proc_read_entry("RF-A", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_reg_rf_a, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/RF-A\n", + dev->name); + e = create_proc_read_entry("RF-B", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_reg_rf_b, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/RF-B\n", + dev->name); + e = create_proc_read_entry("RF-C", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_reg_rf_c, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/RF-C\n", + dev->name); + e = create_proc_read_entry("RF-D", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_reg_rf_d, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/RF-D\n", + dev->name); + e = create_proc_read_entry("SEC-CAM-1", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_cam_register_1, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/SEC-CAM-1\n", + dev->name); + e = create_proc_read_entry("SEC-CAM-2", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_cam_register_2, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/SEC-CAM-2\n", + dev->name); + e = create_proc_read_entry("SEC-CAM-3", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_cam_register_3, dev); + if (!e) + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/SEC-CAM-3\n", + dev->name); +} diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c b/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c new file mode 100644 index 000000000000..a7fa9aad6f2d --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c @@ -0,0 +1,2995 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ +#include "rtl_core.h" +#include "rtl_dm.h" +#include "r8192E_hw.h" +#include "r8192E_phy.h" +#include "r8192E_phyreg.h" +#include "r8190P_rtl8256.h" +#include "r8192E_cmdpkt.h" + +/*---------------------------Define Local Constant---------------------------*/ +static u32 edca_setting_DL[HT_IOT_PEER_MAX] = { + 0x5e4322, + 0x5e4322, + 0x5ea44f, + 0x5e4322, + 0x604322, + 0xa44f, + 0x5e4322, + 0x5e4332 +}; + +static u32 edca_setting_DL_GMode[HT_IOT_PEER_MAX] = { + 0x5e4322, + 0x5e4322, + 0x5e4322, + 0x5e4322, + 0x604322, + 0xa44f, + 0x5e4322, + 0x5e4322 +}; + +static u32 edca_setting_UL[HT_IOT_PEER_MAX] = { + 0x5e4322, + 0xa44f, + 0x5ea44f, + 0x5e4322, + 0x604322, + 0x5e4322, + 0x5e4322, + 0x5e4332 +}; + +#define RTK_UL_EDCA 0xa44f +#define RTK_DL_EDCA 0x5e4322 +/*---------------------------Define Local Constant---------------------------*/ + + +/*------------------------Define global variable-----------------------------*/ +struct dig_t dm_digtable; +u8 dm_shadow[16][256] = { + {0} +}; + +struct drx_path_sel DM_RxPathSelTable; +/*------------------------Define global variable-----------------------------*/ + + +/*------------------------Define local variable------------------------------*/ +/*------------------------Define local variable------------------------------*/ + + + +/*---------------------Define local function prototype-----------------------*/ +static void dm_check_rate_adaptive(struct net_device *dev); + +static void dm_init_bandwidth_autoswitch(struct net_device *dev); +static void dm_bandwidth_autoswitch(struct net_device *dev); + + +static void dm_check_txpower_tracking(struct net_device *dev); + + + + + +static void dm_bb_initialgain_restore(struct net_device *dev); + + +static void dm_bb_initialgain_backup(struct net_device *dev); + +static void dm_dig_init(struct net_device *dev); +static void dm_ctrl_initgain_byrssi(struct net_device *dev); +static void dm_ctrl_initgain_byrssi_highpwr(struct net_device *dev); +static void dm_ctrl_initgain_byrssi_by_driverrssi(struct net_device *dev); +static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(struct net_device *dev); +static void dm_initial_gain(struct net_device *dev); +static void dm_pd_th(struct net_device *dev); +static void dm_cs_ratio(struct net_device *dev); + +static void dm_init_ctstoself(struct net_device *dev); +static void dm_Init_WA_Broadcom_IOT(struct net_device *dev); + +static void dm_check_edca_turbo(struct net_device *dev); + +static void dm_check_pbc_gpio(struct net_device *dev); + + +static void dm_check_rx_path_selection(struct net_device *dev); +static void dm_init_rxpath_selection(struct net_device *dev); +static void dm_rxpath_sel_byrssi(struct net_device *dev); + + +static void dm_init_fsync(struct net_device *dev); +static void dm_deInit_fsync(struct net_device *dev); + +static void dm_check_txrateandretrycount(struct net_device *dev); +static void dm_check_ac_dc_power(struct net_device *dev); + +/*---------------------Define local function prototype-----------------------*/ + +static void dm_init_dynamic_txpower(struct net_device *dev); +static void dm_dynamic_txpower(struct net_device *dev); + + +static void dm_send_rssi_tofw(struct net_device *dev); +static void dm_ctstoself(struct net_device *dev); +/*---------------------------Define function prototype------------------------*/ + +void init_hal_dm(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + priv->DM_Type = DM_Type_ByDriver; + + priv->undecorated_smoothed_pwdb = -1; + + dm_init_dynamic_txpower(dev); + + init_rate_adaptive(dev); + + dm_dig_init(dev); + dm_init_edca_turbo(dev); + dm_init_bandwidth_autoswitch(dev); + dm_init_fsync(dev); + dm_init_rxpath_selection(dev); + dm_init_ctstoself(dev); + if (IS_HARDWARE_TYPE_8192SE(dev)) + dm_Init_WA_Broadcom_IOT(dev); + + INIT_DELAYED_WORK_RSL(&priv->gpio_change_rf_wq, (void *)dm_CheckRfCtrlGPIO, dev); +} + +void deinit_hal_dm(struct net_device *dev) +{ + + dm_deInit_fsync(dev); + +} + +void hal_dm_watchdog(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + if (priv->being_init_adapter) + return; + + dm_check_ac_dc_power(dev); + + dm_check_pbc_gpio(dev); + dm_check_txrateandretrycount(dev); + dm_check_edca_turbo(dev); + + dm_check_rate_adaptive(dev); + dm_dynamic_txpower(dev); + dm_check_txpower_tracking(dev); + + dm_ctrl_initgain_byrssi(dev); + dm_bandwidth_autoswitch(dev); + + dm_check_rx_path_selection(dev); + dm_check_fsync(dev); + + dm_send_rssi_tofw(dev); + dm_ctstoself(dev); +} + +static void dm_check_ac_dc_power(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + static char *ac_dc_check_script_path = "/etc/acpi/wireless-rtl-ac-dc-power.sh"; + char *argv[] = {ac_dc_check_script_path, DRV_NAME, NULL}; + static char *envp[] = {"HOME=/", + "TERM=linux", + "PATH=/usr/bin:/bin", + NULL}; + + if (priv->ResetProgress == RESET_TYPE_SILENT) { + RT_TRACE((COMP_INIT | COMP_POWER | COMP_RF), + "GPIOChangeRFWorkItemCallBack(): Silent Reseting!!!!!!!\n"); + return; + } + + if (priv->rtllib->state != RTLLIB_LINKED) + return; + call_usermodehelper(ac_dc_check_script_path, argv, envp, 1); + + return; +}; + + +void init_rate_adaptive(struct net_device *dev) +{ + + struct r8192_priv *priv = rtllib_priv(dev); + struct rate_adaptive *pra = (struct rate_adaptive *)&priv->rate_adaptive; + + pra->ratr_state = DM_RATR_STA_MAX; + pra->high2low_rssi_thresh_for_ra = RateAdaptiveTH_High; + pra->low2high_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M+5; + pra->low2high_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M+5; + + pra->high_rssi_thresh_for_ra = RateAdaptiveTH_High+5; + pra->low_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M; + pra->low_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M; + + if (priv->CustomerID == RT_CID_819x_Netcore) + pra->ping_rssi_enable = 1; + else + pra->ping_rssi_enable = 0; + pra->ping_rssi_thresh_for_ra = 15; + + + if (priv->rf_type == RF_2T4R) { + pra->upper_rssi_threshold_ratr = 0x8f0f0000; + pra->middle_rssi_threshold_ratr = 0x8f0ff000; + pra->low_rssi_threshold_ratr = 0x8f0ff001; + pra->low_rssi_threshold_ratr_40M = 0x8f0ff005; + pra->low_rssi_threshold_ratr_20M = 0x8f0ff001; + pra->ping_rssi_ratr = 0x0000000d; + } else if (priv->rf_type == RF_1T2R) { + pra->upper_rssi_threshold_ratr = 0x000fc000; + pra->middle_rssi_threshold_ratr = 0x000ff000; + pra->low_rssi_threshold_ratr = 0x000ff001; + pra->low_rssi_threshold_ratr_40M = 0x000ff005; + pra->low_rssi_threshold_ratr_20M = 0x000ff001; + pra->ping_rssi_ratr = 0x0000000d; + } + +} + + +static void dm_check_rate_adaptive(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rt_hi_throughput *pHTInfo = priv->rtllib->pHTInfo; + struct rate_adaptive *pra = (struct rate_adaptive *)&priv->rate_adaptive; + u32 currentRATR, targetRATR = 0; + u32 LowRSSIThreshForRA = 0, HighRSSIThreshForRA = 0; + bool bshort_gi_enabled = false; + static u8 ping_rssi_state; + + if (IS_NIC_DOWN(priv)) { + RT_TRACE(COMP_RATE, "<---- dm_check_rate_adaptive(): driver is going to unload\n"); + return; + } + + if (pra->rate_adaptive_disabled) + return; + + if (!(priv->rtllib->mode == WIRELESS_MODE_N_24G || + priv->rtllib->mode == WIRELESS_MODE_N_5G)) + return; + + if (priv->rtllib->state == RTLLIB_LINKED) { + + bshort_gi_enabled = (pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI40MHz) || + (!pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI20MHz); + + + pra->upper_rssi_threshold_ratr = + (pra->upper_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled) ? BIT31 : 0); + + pra->middle_rssi_threshold_ratr = + (pra->middle_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled) ? BIT31 : 0); + + if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { + pra->low_rssi_threshold_ratr = + (pra->low_rssi_threshold_ratr_40M & (~BIT31)) | ((bshort_gi_enabled) ? BIT31 : 0); + } else { + pra->low_rssi_threshold_ratr = + (pra->low_rssi_threshold_ratr_20M & (~BIT31)) | ((bshort_gi_enabled) ? BIT31 : 0); + } + pra->ping_rssi_ratr = + (pra->ping_rssi_ratr & (~BIT31)) | ((bshort_gi_enabled) ? BIT31 : 0); + + if (pra->ratr_state == DM_RATR_STA_HIGH) { + HighRSSIThreshForRA = pra->high2low_rssi_thresh_for_ra; + LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ? + (pra->low_rssi_thresh_for_ra40M) : (pra->low_rssi_thresh_for_ra20M); + } else if (pra->ratr_state == DM_RATR_STA_LOW) { + HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra; + LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ? + (pra->low2high_rssi_thresh_for_ra40M) : (pra->low2high_rssi_thresh_for_ra20M); + } else { + HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra; + LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ? + (pra->low_rssi_thresh_for_ra40M) : (pra->low_rssi_thresh_for_ra20M); + } + + if (priv->undecorated_smoothed_pwdb >= (long)HighRSSIThreshForRA) { + pra->ratr_state = DM_RATR_STA_HIGH; + targetRATR = pra->upper_rssi_threshold_ratr; + } else if (priv->undecorated_smoothed_pwdb >= (long)LowRSSIThreshForRA) { + pra->ratr_state = DM_RATR_STA_MIDDLE; + targetRATR = pra->middle_rssi_threshold_ratr; + } else { + pra->ratr_state = DM_RATR_STA_LOW; + targetRATR = pra->low_rssi_threshold_ratr; + } + + if (pra->ping_rssi_enable) { + if (priv->undecorated_smoothed_pwdb < (long)(pra->ping_rssi_thresh_for_ra+5)) { + if ((priv->undecorated_smoothed_pwdb < (long)pra->ping_rssi_thresh_for_ra) || + ping_rssi_state) { + pra->ratr_state = DM_RATR_STA_LOW; + targetRATR = pra->ping_rssi_ratr; + ping_rssi_state = 1; + } + } else { + ping_rssi_state = 0; + } + } + + if (priv->rtllib->GetHalfNmodeSupportByAPsHandler(dev)) + targetRATR &= 0xf00fffff; + + currentRATR = read_nic_dword(dev, RATR0); + if (targetRATR != currentRATR) { + u32 ratr_value; + ratr_value = targetRATR; + RT_TRACE(COMP_RATE, + "currentRATR = %x, targetRATR = %x\n", + currentRATR, targetRATR); + if (priv->rf_type == RF_1T2R) + ratr_value &= ~(RATE_ALL_OFDM_2SS); + write_nic_dword(dev, RATR0, ratr_value); + write_nic_byte(dev, UFWP, 1); + + pra->last_ratr = targetRATR; + } + + } else { + pra->ratr_state = DM_RATR_STA_MAX; + } +} + +static void dm_init_bandwidth_autoswitch(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + priv->rtllib->bandwidth_auto_switch.threshold_20Mhzto40Mhz = BW_AUTO_SWITCH_LOW_HIGH; + priv->rtllib->bandwidth_auto_switch.threshold_40Mhzto20Mhz = BW_AUTO_SWITCH_HIGH_LOW; + priv->rtllib->bandwidth_auto_switch.bforced_tx20Mhz = false; + priv->rtllib->bandwidth_auto_switch.bautoswitch_enable = false; +} + +static void dm_bandwidth_autoswitch(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 || + !priv->rtllib->bandwidth_auto_switch.bautoswitch_enable) { + return; + } else { + if (priv->rtllib->bandwidth_auto_switch.bforced_tx20Mhz == false) { + if (priv->undecorated_smoothed_pwdb <= + priv->rtllib->bandwidth_auto_switch.threshold_40Mhzto20Mhz) + priv->rtllib->bandwidth_auto_switch.bforced_tx20Mhz = true; + } else { + if (priv->undecorated_smoothed_pwdb >= + priv->rtllib->bandwidth_auto_switch.threshold_20Mhzto40Mhz) + priv->rtllib->bandwidth_auto_switch.bforced_tx20Mhz = false; + + } + } +} + +static u32 OFDMSwingTable[OFDM_Table_Length] = { + 0x7f8001fe, + 0x71c001c7, + 0x65400195, + 0x5a400169, + 0x50800142, + 0x47c0011f, + 0x40000100, + 0x390000e4, + 0x32c000cb, + 0x2d4000b5, + 0x288000a2, + 0x24000090, + 0x20000080, + 0x1c800072, + 0x19800066, + 0x26c0005b, + 0x24400051, + 0x12000048, + 0x10000040 +}; + +static u8 CCKSwingTable_Ch1_Ch13[CCK_Table_length][8] = { + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01} +}; + +static u8 CCKSwingTable_Ch14[CCK_Table_length][8] = { + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00} +}; + +#define Pw_Track_Flag 0x11d +#define Tssi_Mea_Value 0x13c +#define Tssi_Report_Value1 0x134 +#define Tssi_Report_Value2 0x13e +#define FW_Busy_Flag 0x13f + +static void dm_TXPowerTrackingCallback_TSSI(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + bool bHighpowerstate, viviflag = false; + struct dcmd_txcmd tx_cmd; + u8 powerlevelOFDM24G; + int i = 0, j = 0, k = 0; + u8 RF_Type, tmp_report[5] = {0, 0, 0, 0, 0}; + u32 Value; + u8 Pwr_Flag; + u16 Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver = 0; + u32 delta = 0; + + RT_TRACE(COMP_POWER_TRACKING, "%s()\n", __func__); + write_nic_byte(dev, Pw_Track_Flag, 0); + write_nic_byte(dev, FW_Busy_Flag, 0); + priv->rtllib->bdynamic_txpower_enable = false; + bHighpowerstate = priv->bDynamicTxHighPower; + + powerlevelOFDM24G = (u8)(priv->Pwr_Track>>24); + RF_Type = priv->rf_type; + Value = (RF_Type<<8) | powerlevelOFDM24G; + + RT_TRACE(COMP_POWER_TRACKING, "powerlevelOFDM24G = %x\n", + powerlevelOFDM24G); + + + for (j = 0; j <= 30; j++) { + + tx_cmd.Op = TXCMD_SET_TX_PWR_TRACKING; + tx_cmd.Length = 4; + tx_cmd.Value = Value; + cmpk_message_handle_tx(dev, (u8 *)&tx_cmd, + DESC_PACKET_TYPE_INIT, + sizeof(struct dcmd_txcmd)); + mdelay(1); + for (i = 0; i <= 30; i++) { + Pwr_Flag = read_nic_byte(dev, Pw_Track_Flag); + + if (Pwr_Flag == 0) { + mdelay(1); + + if (priv->bResetInProgress) { + RT_TRACE(COMP_POWER_TRACKING, + "we are in slient reset progress, so return\n"); + write_nic_byte(dev, Pw_Track_Flag, 0); + write_nic_byte(dev, FW_Busy_Flag, 0); + return; + } + if ((priv->rtllib->eRFPowerState != eRfOn)) { + RT_TRACE(COMP_POWER_TRACKING, + "we are in power save, so return\n"); + write_nic_byte(dev, Pw_Track_Flag, 0); + write_nic_byte(dev, FW_Busy_Flag, 0); + return; + } + + continue; + } + + Avg_TSSI_Meas = read_nic_word(dev, Tssi_Mea_Value); + + if (Avg_TSSI_Meas == 0) { + write_nic_byte(dev, Pw_Track_Flag, 0); + write_nic_byte(dev, FW_Busy_Flag, 0); + return; + } + + for (k = 0; k < 5; k++) { + if (k != 4) + tmp_report[k] = read_nic_byte(dev, + Tssi_Report_Value1+k); + else + tmp_report[k] = read_nic_byte(dev, + Tssi_Report_Value2); + + RT_TRACE(COMP_POWER_TRACKING, + "TSSI_report_value = %d\n", + tmp_report[k]); + + if (tmp_report[k] <= 20) { + viviflag = true; + break; + } + } + + if (viviflag == true) { + write_nic_byte(dev, Pw_Track_Flag, 0); + viviflag = false; + RT_TRACE(COMP_POWER_TRACKING, "we filted this data\n"); + for (k = 0; k < 5; k++) + tmp_report[k] = 0; + break; + } + + for (k = 0; k < 5; k++) + Avg_TSSI_Meas_from_driver += tmp_report[k]; + + Avg_TSSI_Meas_from_driver = Avg_TSSI_Meas_from_driver*100/5; + RT_TRACE(COMP_POWER_TRACKING, + "Avg_TSSI_Meas_from_driver = %d\n", + Avg_TSSI_Meas_from_driver); + TSSI_13dBm = priv->TSSI_13dBm; + RT_TRACE(COMP_POWER_TRACKING, "TSSI_13dBm = %d\n", TSSI_13dBm); + + if (Avg_TSSI_Meas_from_driver > TSSI_13dBm) + delta = Avg_TSSI_Meas_from_driver - TSSI_13dBm; + else + delta = TSSI_13dBm - Avg_TSSI_Meas_from_driver; + + if (delta <= E_FOR_TX_POWER_TRACK) { + priv->rtllib->bdynamic_txpower_enable = true; + write_nic_byte(dev, Pw_Track_Flag, 0); + write_nic_byte(dev, FW_Busy_Flag, 0); + RT_TRACE(COMP_POWER_TRACKING, + "tx power track is done\n"); + RT_TRACE(COMP_POWER_TRACKING, + "priv->rfa_txpowertrackingindex = %d\n", + priv->rfa_txpowertrackingindex); + RT_TRACE(COMP_POWER_TRACKING, + "priv->rfa_txpowertrackingindex_real = %d\n", + priv->rfa_txpowertrackingindex_real); + RT_TRACE(COMP_POWER_TRACKING, + "priv->CCKPresentAttentuation_difference = %d\n", + priv->CCKPresentAttentuation_difference); + RT_TRACE(COMP_POWER_TRACKING, + "priv->CCKPresentAttentuation = %d\n", + priv->CCKPresentAttentuation); + return; + } else { + if (Avg_TSSI_Meas_from_driver < TSSI_13dBm - E_FOR_TX_POWER_TRACK) { + if (RF_Type == RF_2T4R) { + + if ((priv->rfa_txpowertrackingindex > 0) && + (priv->rfc_txpowertrackingindex > 0)) { + priv->rfa_txpowertrackingindex--; + if (priv->rfa_txpowertrackingindex_real > 4) { + priv->rfa_txpowertrackingindex_real--; + rtl8192_setBBreg(dev, + rOFDM0_XATxIQImbalance, + bMaskDWord, + priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value); + } + + priv->rfc_txpowertrackingindex--; + if (priv->rfc_txpowertrackingindex_real > 4) { + priv->rfc_txpowertrackingindex_real--; + rtl8192_setBBreg(dev, + rOFDM0_XCTxIQImbalance, + bMaskDWord, + priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value); + } + } else { + rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, + bMaskDWord, + priv->txbbgain_table[4].txbbgain_value); + rtl8192_setBBreg(dev, + rOFDM0_XCTxIQImbalance, + bMaskDWord, priv->txbbgain_table[4].txbbgain_value); + } + } else { + if (priv->rfa_txpowertrackingindex > 0) { + priv->rfa_txpowertrackingindex--; + if (priv->rfa_txpowertrackingindex_real > 4) { + priv->rfa_txpowertrackingindex_real--; + rtl8192_setBBreg(dev, + rOFDM0_XATxIQImbalance, + bMaskDWord, + priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value); + } + } else + rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, + bMaskDWord, priv->txbbgain_table[4].txbbgain_value); + + } + } else { + if (RF_Type == RF_2T4R) { + if ((priv->rfa_txpowertrackingindex < + TxBBGainTableLength - 1) && + (priv->rfc_txpowertrackingindex < + TxBBGainTableLength - 1)) { + priv->rfa_txpowertrackingindex++; + priv->rfa_txpowertrackingindex_real++; + rtl8192_setBBreg(dev, + rOFDM0_XATxIQImbalance, + bMaskDWord, + priv->txbbgain_table + [priv->rfa_txpowertrackingindex_real].txbbgain_value); + priv->rfc_txpowertrackingindex++; + priv->rfc_txpowertrackingindex_real++; + rtl8192_setBBreg(dev, + rOFDM0_XCTxIQImbalance, + bMaskDWord, + priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value); + } else { + rtl8192_setBBreg(dev, + rOFDM0_XATxIQImbalance, + bMaskDWord, + priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value); + rtl8192_setBBreg(dev, + rOFDM0_XCTxIQImbalance, + bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value); + } + } else { + if (priv->rfa_txpowertrackingindex < (TxBBGainTableLength - 1)) { + priv->rfa_txpowertrackingindex++; + priv->rfa_txpowertrackingindex_real++; + rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, + bMaskDWord, + priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value); + } else + rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, + bMaskDWord, + priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value); + } + } + if (RF_Type == RF_2T4R) { + priv->CCKPresentAttentuation_difference + = priv->rfa_txpowertrackingindex - priv->rfa_txpowertracking_default; + } else { + priv->CCKPresentAttentuation_difference + = priv->rfa_txpowertrackingindex_real - priv->rfa_txpowertracking_default; + } + + if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) + priv->CCKPresentAttentuation = + priv->CCKPresentAttentuation_20Mdefault + + priv->CCKPresentAttentuation_difference; + else + priv->CCKPresentAttentuation = + priv->CCKPresentAttentuation_40Mdefault + + priv->CCKPresentAttentuation_difference; + + if (priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1)) + priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1; + if (priv->CCKPresentAttentuation < 0) + priv->CCKPresentAttentuation = 0; + + if (priv->CCKPresentAttentuation > -1 && + priv->CCKPresentAttentuation < CCKTxBBGainTableLength) { + if (priv->rtllib->current_network.channel == 14 && + !priv->bcck_in_ch14) { + priv->bcck_in_ch14 = true; + dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + } else if (priv->rtllib->current_network.channel != 14 && priv->bcck_in_ch14) { + priv->bcck_in_ch14 = false; + dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + } else + dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + } + RT_TRACE(COMP_POWER_TRACKING, + "priv->rfa_txpowertrackingindex = %d\n", + priv->rfa_txpowertrackingindex); + RT_TRACE(COMP_POWER_TRACKING, + "priv->rfa_txpowertrackingindex_real = %d\n", + priv->rfa_txpowertrackingindex_real); + RT_TRACE(COMP_POWER_TRACKING, + "priv->CCKPresentAttentuation_difference = %d\n", + priv->CCKPresentAttentuation_difference); + RT_TRACE(COMP_POWER_TRACKING, + "priv->CCKPresentAttentuation = %d\n", + priv->CCKPresentAttentuation); + + if (priv->CCKPresentAttentuation_difference <= -12 || priv->CCKPresentAttentuation_difference >= 24) { + priv->rtllib->bdynamic_txpower_enable = true; + write_nic_byte(dev, Pw_Track_Flag, 0); + write_nic_byte(dev, FW_Busy_Flag, 0); + RT_TRACE(COMP_POWER_TRACKING, "tx power track--->limited\n"); + return; + } + } + write_nic_byte(dev, Pw_Track_Flag, 0); + Avg_TSSI_Meas_from_driver = 0; + for (k = 0; k < 5; k++) + tmp_report[k] = 0; + break; + } + write_nic_byte(dev, FW_Busy_Flag, 0); + } + priv->rtllib->bdynamic_txpower_enable = true; + write_nic_byte(dev, Pw_Track_Flag, 0); +} + +static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device *dev) +{ +#define ThermalMeterVal 9 + struct r8192_priv *priv = rtllib_priv(dev); + u32 tmpRegA, TempCCk; + u8 tmpOFDMindex, tmpCCKindex, tmpCCK20Mindex, tmpCCK40Mindex, tmpval; + int i = 0, CCKSwingNeedUpdate = 0; + + if (!priv->btxpower_trackingInit) { + tmpRegA = rtl8192_QueryBBReg(dev, rOFDM0_XATxIQImbalance, bMaskDWord); + for (i = 0; i < OFDM_Table_Length; i++) { + if (tmpRegA == OFDMSwingTable[i]) { + priv->OFDM_index[0] = (u8)i; + RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, OFDM_index = 0x%x\n", + rOFDM0_XATxIQImbalance, tmpRegA, priv->OFDM_index[0]); + } + } + + TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2); + for (i = 0; i < CCK_Table_length; i++) { + if (TempCCk == (u32)CCKSwingTable_Ch1_Ch13[i][0]) { + priv->CCK_index = (u8) i; + RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x" + " = 0x%x, CCK_index = 0x%x\n", + rCCK0_TxFilter1, TempCCk, + priv->CCK_index); + break; + } + } + priv->btxpower_trackingInit = true; + return; + } + + tmpRegA = rtl8192_phy_QueryRFReg(dev, RF90_PATH_A, 0x12, 0x078); + RT_TRACE(COMP_POWER_TRACKING, "Readback ThermalMeterA = %d\n", tmpRegA); + if (tmpRegA < 3 || tmpRegA > 13) + return; + if (tmpRegA >= 12) + tmpRegA = 12; + RT_TRACE(COMP_POWER_TRACKING, "Valid ThermalMeterA = %d\n", tmpRegA); + priv->ThermalMeter[0] = ThermalMeterVal; + priv->ThermalMeter[1] = ThermalMeterVal; + + if (priv->ThermalMeter[0] >= (u8)tmpRegA) { + tmpOFDMindex = tmpCCK20Mindex = 6+(priv->ThermalMeter[0] - + (u8)tmpRegA); + tmpCCK40Mindex = tmpCCK20Mindex - 6; + if (tmpOFDMindex >= OFDM_Table_Length) + tmpOFDMindex = OFDM_Table_Length-1; + if (tmpCCK20Mindex >= CCK_Table_length) + tmpCCK20Mindex = CCK_Table_length-1; + if (tmpCCK40Mindex >= CCK_Table_length) + tmpCCK40Mindex = CCK_Table_length-1; + } else { + tmpval = ((u8)tmpRegA - priv->ThermalMeter[0]); + if (tmpval >= 6) + tmpOFDMindex = tmpCCK20Mindex = 0; + else + tmpOFDMindex = tmpCCK20Mindex = 6 - tmpval; + tmpCCK40Mindex = 0; + } + if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + tmpCCKindex = tmpCCK40Mindex; + else + tmpCCKindex = tmpCCK20Mindex; + + priv->Record_CCK_20Mindex = tmpCCK20Mindex; + priv->Record_CCK_40Mindex = tmpCCK40Mindex; + RT_TRACE(COMP_POWER_TRACKING, "Record_CCK_20Mindex / Record_CCK_40" + "Mindex = %d / %d.\n", + priv->Record_CCK_20Mindex, priv->Record_CCK_40Mindex); + + if (priv->rtllib->current_network.channel == 14 && + !priv->bcck_in_ch14) { + priv->bcck_in_ch14 = true; + CCKSwingNeedUpdate = 1; + } else if (priv->rtllib->current_network.channel != 14 && + priv->bcck_in_ch14) { + priv->bcck_in_ch14 = false; + CCKSwingNeedUpdate = 1; + } + + if (priv->CCK_index != tmpCCKindex) { + priv->CCK_index = tmpCCKindex; + CCKSwingNeedUpdate = 1; + } + + if (CCKSwingNeedUpdate) + dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + if (priv->OFDM_index[0] != tmpOFDMindex) { + priv->OFDM_index[0] = tmpOFDMindex; + rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, + OFDMSwingTable[priv->OFDM_index[0]]); + RT_TRACE(COMP_POWER_TRACKING, "Update OFDMSwing[%d] = 0x%x\n", + priv->OFDM_index[0], + OFDMSwingTable[priv->OFDM_index[0]]); + } + priv->txpower_count = 0; +} + +void dm_txpower_trackingcallback(void *data) +{ + struct r8192_priv *priv = container_of_dwork_rsl(data, + struct r8192_priv, txpower_tracking_wq); + struct net_device *dev = priv->rtllib->dev; + + if (priv->IC_Cut >= IC_VersionCut_D) + dm_TXPowerTrackingCallback_TSSI(dev); + else + dm_TXPowerTrackingCallback_ThermalMeter(dev); +} + +static void dm_InitializeTXPowerTracking_TSSI(struct net_device *dev) +{ + + struct r8192_priv *priv = rtllib_priv(dev); + + priv->txbbgain_table[0].txbb_iq_amplifygain = 12; + priv->txbbgain_table[0].txbbgain_value = 0x7f8001fe; + priv->txbbgain_table[1].txbb_iq_amplifygain = 11; + priv->txbbgain_table[1].txbbgain_value = 0x788001e2; + priv->txbbgain_table[2].txbb_iq_amplifygain = 10; + priv->txbbgain_table[2].txbbgain_value = 0x71c001c7; + priv->txbbgain_table[3].txbb_iq_amplifygain = 9; + priv->txbbgain_table[3].txbbgain_value = 0x6b8001ae; + priv->txbbgain_table[4].txbb_iq_amplifygain = 8; + priv->txbbgain_table[4].txbbgain_value = 0x65400195; + priv->txbbgain_table[5].txbb_iq_amplifygain = 7; + priv->txbbgain_table[5].txbbgain_value = 0x5fc0017f; + priv->txbbgain_table[6].txbb_iq_amplifygain = 6; + priv->txbbgain_table[6].txbbgain_value = 0x5a400169; + priv->txbbgain_table[7].txbb_iq_amplifygain = 5; + priv->txbbgain_table[7].txbbgain_value = 0x55400155; + priv->txbbgain_table[8].txbb_iq_amplifygain = 4; + priv->txbbgain_table[8].txbbgain_value = 0x50800142; + priv->txbbgain_table[9].txbb_iq_amplifygain = 3; + priv->txbbgain_table[9].txbbgain_value = 0x4c000130; + priv->txbbgain_table[10].txbb_iq_amplifygain = 2; + priv->txbbgain_table[10].txbbgain_value = 0x47c0011f; + priv->txbbgain_table[11].txbb_iq_amplifygain = 1; + priv->txbbgain_table[11].txbbgain_value = 0x43c0010f; + priv->txbbgain_table[12].txbb_iq_amplifygain = 0; + priv->txbbgain_table[12].txbbgain_value = 0x40000100; + priv->txbbgain_table[13].txbb_iq_amplifygain = -1; + priv->txbbgain_table[13].txbbgain_value = 0x3c8000f2; + priv->txbbgain_table[14].txbb_iq_amplifygain = -2; + priv->txbbgain_table[14].txbbgain_value = 0x390000e4; + priv->txbbgain_table[15].txbb_iq_amplifygain = -3; + priv->txbbgain_table[15].txbbgain_value = 0x35c000d7; + priv->txbbgain_table[16].txbb_iq_amplifygain = -4; + priv->txbbgain_table[16].txbbgain_value = 0x32c000cb; + priv->txbbgain_table[17].txbb_iq_amplifygain = -5; + priv->txbbgain_table[17].txbbgain_value = 0x300000c0; + priv->txbbgain_table[18].txbb_iq_amplifygain = -6; + priv->txbbgain_table[18].txbbgain_value = 0x2d4000b5; + priv->txbbgain_table[19].txbb_iq_amplifygain = -7; + priv->txbbgain_table[19].txbbgain_value = 0x2ac000ab; + priv->txbbgain_table[20].txbb_iq_amplifygain = -8; + priv->txbbgain_table[20].txbbgain_value = 0x288000a2; + priv->txbbgain_table[21].txbb_iq_amplifygain = -9; + priv->txbbgain_table[21].txbbgain_value = 0x26000098; + priv->txbbgain_table[22].txbb_iq_amplifygain = -10; + priv->txbbgain_table[22].txbbgain_value = 0x24000090; + priv->txbbgain_table[23].txbb_iq_amplifygain = -11; + priv->txbbgain_table[23].txbbgain_value = 0x22000088; + priv->txbbgain_table[24].txbb_iq_amplifygain = -12; + priv->txbbgain_table[24].txbbgain_value = 0x20000080; + priv->txbbgain_table[25].txbb_iq_amplifygain = -13; + priv->txbbgain_table[25].txbbgain_value = 0x1a00006c; + priv->txbbgain_table[26].txbb_iq_amplifygain = -14; + priv->txbbgain_table[26].txbbgain_value = 0x1c800072; + priv->txbbgain_table[27].txbb_iq_amplifygain = -15; + priv->txbbgain_table[27].txbbgain_value = 0x18000060; + priv->txbbgain_table[28].txbb_iq_amplifygain = -16; + priv->txbbgain_table[28].txbbgain_value = 0x19800066; + priv->txbbgain_table[29].txbb_iq_amplifygain = -17; + priv->txbbgain_table[29].txbbgain_value = 0x15800056; + priv->txbbgain_table[30].txbb_iq_amplifygain = -18; + priv->txbbgain_table[30].txbbgain_value = 0x26c0005b; + priv->txbbgain_table[31].txbb_iq_amplifygain = -19; + priv->txbbgain_table[31].txbbgain_value = 0x14400051; + priv->txbbgain_table[32].txbb_iq_amplifygain = -20; + priv->txbbgain_table[32].txbbgain_value = 0x24400051; + priv->txbbgain_table[33].txbb_iq_amplifygain = -21; + priv->txbbgain_table[33].txbbgain_value = 0x1300004c; + priv->txbbgain_table[34].txbb_iq_amplifygain = -22; + priv->txbbgain_table[34].txbbgain_value = 0x12000048; + priv->txbbgain_table[35].txbb_iq_amplifygain = -23; + priv->txbbgain_table[35].txbbgain_value = 0x11000044; + priv->txbbgain_table[36].txbb_iq_amplifygain = -24; + priv->txbbgain_table[36].txbbgain_value = 0x10000040; + + priv->cck_txbbgain_table[0].ccktxbb_valuearray[0] = 0x36; + priv->cck_txbbgain_table[0].ccktxbb_valuearray[1] = 0x35; + priv->cck_txbbgain_table[0].ccktxbb_valuearray[2] = 0x2e; + priv->cck_txbbgain_table[0].ccktxbb_valuearray[3] = 0x25; + priv->cck_txbbgain_table[0].ccktxbb_valuearray[4] = 0x1c; + priv->cck_txbbgain_table[0].ccktxbb_valuearray[5] = 0x12; + priv->cck_txbbgain_table[0].ccktxbb_valuearray[6] = 0x09; + priv->cck_txbbgain_table[0].ccktxbb_valuearray[7] = 0x04; + + priv->cck_txbbgain_table[1].ccktxbb_valuearray[0] = 0x33; + priv->cck_txbbgain_table[1].ccktxbb_valuearray[1] = 0x32; + priv->cck_txbbgain_table[1].ccktxbb_valuearray[2] = 0x2b; + priv->cck_txbbgain_table[1].ccktxbb_valuearray[3] = 0x23; + priv->cck_txbbgain_table[1].ccktxbb_valuearray[4] = 0x1a; + priv->cck_txbbgain_table[1].ccktxbb_valuearray[5] = 0x11; + priv->cck_txbbgain_table[1].ccktxbb_valuearray[6] = 0x08; + priv->cck_txbbgain_table[1].ccktxbb_valuearray[7] = 0x04; + + priv->cck_txbbgain_table[2].ccktxbb_valuearray[0] = 0x30; + priv->cck_txbbgain_table[2].ccktxbb_valuearray[1] = 0x2f; + priv->cck_txbbgain_table[2].ccktxbb_valuearray[2] = 0x29; + priv->cck_txbbgain_table[2].ccktxbb_valuearray[3] = 0x21; + priv->cck_txbbgain_table[2].ccktxbb_valuearray[4] = 0x19; + priv->cck_txbbgain_table[2].ccktxbb_valuearray[5] = 0x10; + priv->cck_txbbgain_table[2].ccktxbb_valuearray[6] = 0x08; + priv->cck_txbbgain_table[2].ccktxbb_valuearray[7] = 0x03; + + priv->cck_txbbgain_table[3].ccktxbb_valuearray[0] = 0x2d; + priv->cck_txbbgain_table[3].ccktxbb_valuearray[1] = 0x2d; + priv->cck_txbbgain_table[3].ccktxbb_valuearray[2] = 0x27; + priv->cck_txbbgain_table[3].ccktxbb_valuearray[3] = 0x1f; + priv->cck_txbbgain_table[3].ccktxbb_valuearray[4] = 0x18; + priv->cck_txbbgain_table[3].ccktxbb_valuearray[5] = 0x0f; + priv->cck_txbbgain_table[3].ccktxbb_valuearray[6] = 0x08; + priv->cck_txbbgain_table[3].ccktxbb_valuearray[7] = 0x03; + + priv->cck_txbbgain_table[4].ccktxbb_valuearray[0] = 0x2b; + priv->cck_txbbgain_table[4].ccktxbb_valuearray[1] = 0x2a; + priv->cck_txbbgain_table[4].ccktxbb_valuearray[2] = 0x25; + priv->cck_txbbgain_table[4].ccktxbb_valuearray[3] = 0x1e; + priv->cck_txbbgain_table[4].ccktxbb_valuearray[4] = 0x16; + priv->cck_txbbgain_table[4].ccktxbb_valuearray[5] = 0x0e; + priv->cck_txbbgain_table[4].ccktxbb_valuearray[6] = 0x07; + priv->cck_txbbgain_table[4].ccktxbb_valuearray[7] = 0x03; + + priv->cck_txbbgain_table[5].ccktxbb_valuearray[0] = 0x28; + priv->cck_txbbgain_table[5].ccktxbb_valuearray[1] = 0x28; + priv->cck_txbbgain_table[5].ccktxbb_valuearray[2] = 0x22; + priv->cck_txbbgain_table[5].ccktxbb_valuearray[3] = 0x1c; + priv->cck_txbbgain_table[5].ccktxbb_valuearray[4] = 0x15; + priv->cck_txbbgain_table[5].ccktxbb_valuearray[5] = 0x0d; + priv->cck_txbbgain_table[5].ccktxbb_valuearray[6] = 0x07; + priv->cck_txbbgain_table[5].ccktxbb_valuearray[7] = 0x03; + + priv->cck_txbbgain_table[6].ccktxbb_valuearray[0] = 0x26; + priv->cck_txbbgain_table[6].ccktxbb_valuearray[1] = 0x25; + priv->cck_txbbgain_table[6].ccktxbb_valuearray[2] = 0x21; + priv->cck_txbbgain_table[6].ccktxbb_valuearray[3] = 0x1b; + priv->cck_txbbgain_table[6].ccktxbb_valuearray[4] = 0x14; + priv->cck_txbbgain_table[6].ccktxbb_valuearray[5] = 0x0d; + priv->cck_txbbgain_table[6].ccktxbb_valuearray[6] = 0x06; + priv->cck_txbbgain_table[6].ccktxbb_valuearray[7] = 0x03; + + priv->cck_txbbgain_table[7].ccktxbb_valuearray[0] = 0x24; + priv->cck_txbbgain_table[7].ccktxbb_valuearray[1] = 0x23; + priv->cck_txbbgain_table[7].ccktxbb_valuearray[2] = 0x1f; + priv->cck_txbbgain_table[7].ccktxbb_valuearray[3] = 0x19; + priv->cck_txbbgain_table[7].ccktxbb_valuearray[4] = 0x13; + priv->cck_txbbgain_table[7].ccktxbb_valuearray[5] = 0x0c; + priv->cck_txbbgain_table[7].ccktxbb_valuearray[6] = 0x06; + priv->cck_txbbgain_table[7].ccktxbb_valuearray[7] = 0x03; + + priv->cck_txbbgain_table[8].ccktxbb_valuearray[0] = 0x22; + priv->cck_txbbgain_table[8].ccktxbb_valuearray[1] = 0x21; + priv->cck_txbbgain_table[8].ccktxbb_valuearray[2] = 0x1d; + priv->cck_txbbgain_table[8].ccktxbb_valuearray[3] = 0x18; + priv->cck_txbbgain_table[8].ccktxbb_valuearray[4] = 0x11; + priv->cck_txbbgain_table[8].ccktxbb_valuearray[5] = 0x0b; + priv->cck_txbbgain_table[8].ccktxbb_valuearray[6] = 0x06; + priv->cck_txbbgain_table[8].ccktxbb_valuearray[7] = 0x02; + + priv->cck_txbbgain_table[9].ccktxbb_valuearray[0] = 0x20; + priv->cck_txbbgain_table[9].ccktxbb_valuearray[1] = 0x20; + priv->cck_txbbgain_table[9].ccktxbb_valuearray[2] = 0x1b; + priv->cck_txbbgain_table[9].ccktxbb_valuearray[3] = 0x16; + priv->cck_txbbgain_table[9].ccktxbb_valuearray[4] = 0x11; + priv->cck_txbbgain_table[9].ccktxbb_valuearray[5] = 0x08; + priv->cck_txbbgain_table[9].ccktxbb_valuearray[6] = 0x05; + priv->cck_txbbgain_table[9].ccktxbb_valuearray[7] = 0x02; + + priv->cck_txbbgain_table[10].ccktxbb_valuearray[0] = 0x1f; + priv->cck_txbbgain_table[10].ccktxbb_valuearray[1] = 0x1e; + priv->cck_txbbgain_table[10].ccktxbb_valuearray[2] = 0x1a; + priv->cck_txbbgain_table[10].ccktxbb_valuearray[3] = 0x15; + priv->cck_txbbgain_table[10].ccktxbb_valuearray[4] = 0x10; + priv->cck_txbbgain_table[10].ccktxbb_valuearray[5] = 0x0a; + priv->cck_txbbgain_table[10].ccktxbb_valuearray[6] = 0x05; + priv->cck_txbbgain_table[10].ccktxbb_valuearray[7] = 0x02; + + priv->cck_txbbgain_table[11].ccktxbb_valuearray[0] = 0x1d; + priv->cck_txbbgain_table[11].ccktxbb_valuearray[1] = 0x1c; + priv->cck_txbbgain_table[11].ccktxbb_valuearray[2] = 0x18; + priv->cck_txbbgain_table[11].ccktxbb_valuearray[3] = 0x14; + priv->cck_txbbgain_table[11].ccktxbb_valuearray[4] = 0x0f; + priv->cck_txbbgain_table[11].ccktxbb_valuearray[5] = 0x0a; + priv->cck_txbbgain_table[11].ccktxbb_valuearray[6] = 0x05; + priv->cck_txbbgain_table[11].ccktxbb_valuearray[7] = 0x02; + + priv->cck_txbbgain_table[12].ccktxbb_valuearray[0] = 0x1b; + priv->cck_txbbgain_table[12].ccktxbb_valuearray[1] = 0x1a; + priv->cck_txbbgain_table[12].ccktxbb_valuearray[2] = 0x17; + priv->cck_txbbgain_table[12].ccktxbb_valuearray[3] = 0x13; + priv->cck_txbbgain_table[12].ccktxbb_valuearray[4] = 0x0e; + priv->cck_txbbgain_table[12].ccktxbb_valuearray[5] = 0x09; + priv->cck_txbbgain_table[12].ccktxbb_valuearray[6] = 0x04; + priv->cck_txbbgain_table[12].ccktxbb_valuearray[7] = 0x02; + + priv->cck_txbbgain_table[13].ccktxbb_valuearray[0] = 0x1a; + priv->cck_txbbgain_table[13].ccktxbb_valuearray[1] = 0x19; + priv->cck_txbbgain_table[13].ccktxbb_valuearray[2] = 0x16; + priv->cck_txbbgain_table[13].ccktxbb_valuearray[3] = 0x12; + priv->cck_txbbgain_table[13].ccktxbb_valuearray[4] = 0x0d; + priv->cck_txbbgain_table[13].ccktxbb_valuearray[5] = 0x09; + priv->cck_txbbgain_table[13].ccktxbb_valuearray[6] = 0x04; + priv->cck_txbbgain_table[13].ccktxbb_valuearray[7] = 0x02; + + priv->cck_txbbgain_table[14].ccktxbb_valuearray[0] = 0x18; + priv->cck_txbbgain_table[14].ccktxbb_valuearray[1] = 0x17; + priv->cck_txbbgain_table[14].ccktxbb_valuearray[2] = 0x15; + priv->cck_txbbgain_table[14].ccktxbb_valuearray[3] = 0x11; + priv->cck_txbbgain_table[14].ccktxbb_valuearray[4] = 0x0c; + priv->cck_txbbgain_table[14].ccktxbb_valuearray[5] = 0x08; + priv->cck_txbbgain_table[14].ccktxbb_valuearray[6] = 0x04; + priv->cck_txbbgain_table[14].ccktxbb_valuearray[7] = 0x02; + + priv->cck_txbbgain_table[15].ccktxbb_valuearray[0] = 0x17; + priv->cck_txbbgain_table[15].ccktxbb_valuearray[1] = 0x16; + priv->cck_txbbgain_table[15].ccktxbb_valuearray[2] = 0x13; + priv->cck_txbbgain_table[15].ccktxbb_valuearray[3] = 0x10; + priv->cck_txbbgain_table[15].ccktxbb_valuearray[4] = 0x0c; + priv->cck_txbbgain_table[15].ccktxbb_valuearray[5] = 0x08; + priv->cck_txbbgain_table[15].ccktxbb_valuearray[6] = 0x04; + priv->cck_txbbgain_table[15].ccktxbb_valuearray[7] = 0x02; + + priv->cck_txbbgain_table[16].ccktxbb_valuearray[0] = 0x16; + priv->cck_txbbgain_table[16].ccktxbb_valuearray[1] = 0x15; + priv->cck_txbbgain_table[16].ccktxbb_valuearray[2] = 0x12; + priv->cck_txbbgain_table[16].ccktxbb_valuearray[3] = 0x0f; + priv->cck_txbbgain_table[16].ccktxbb_valuearray[4] = 0x0b; + priv->cck_txbbgain_table[16].ccktxbb_valuearray[5] = 0x07; + priv->cck_txbbgain_table[16].ccktxbb_valuearray[6] = 0x04; + priv->cck_txbbgain_table[16].ccktxbb_valuearray[7] = 0x01; + + priv->cck_txbbgain_table[17].ccktxbb_valuearray[0] = 0x14; + priv->cck_txbbgain_table[17].ccktxbb_valuearray[1] = 0x14; + priv->cck_txbbgain_table[17].ccktxbb_valuearray[2] = 0x11; + priv->cck_txbbgain_table[17].ccktxbb_valuearray[3] = 0x0e; + priv->cck_txbbgain_table[17].ccktxbb_valuearray[4] = 0x0b; + priv->cck_txbbgain_table[17].ccktxbb_valuearray[5] = 0x07; + priv->cck_txbbgain_table[17].ccktxbb_valuearray[6] = 0x03; + priv->cck_txbbgain_table[17].ccktxbb_valuearray[7] = 0x02; + + priv->cck_txbbgain_table[18].ccktxbb_valuearray[0] = 0x13; + priv->cck_txbbgain_table[18].ccktxbb_valuearray[1] = 0x13; + priv->cck_txbbgain_table[18].ccktxbb_valuearray[2] = 0x10; + priv->cck_txbbgain_table[18].ccktxbb_valuearray[3] = 0x0d; + priv->cck_txbbgain_table[18].ccktxbb_valuearray[4] = 0x0a; + priv->cck_txbbgain_table[18].ccktxbb_valuearray[5] = 0x06; + priv->cck_txbbgain_table[18].ccktxbb_valuearray[6] = 0x03; + priv->cck_txbbgain_table[18].ccktxbb_valuearray[7] = 0x01; + + priv->cck_txbbgain_table[19].ccktxbb_valuearray[0] = 0x12; + priv->cck_txbbgain_table[19].ccktxbb_valuearray[1] = 0x12; + priv->cck_txbbgain_table[19].ccktxbb_valuearray[2] = 0x0f; + priv->cck_txbbgain_table[19].ccktxbb_valuearray[3] = 0x0c; + priv->cck_txbbgain_table[19].ccktxbb_valuearray[4] = 0x09; + priv->cck_txbbgain_table[19].ccktxbb_valuearray[5] = 0x06; + priv->cck_txbbgain_table[19].ccktxbb_valuearray[6] = 0x03; + priv->cck_txbbgain_table[19].ccktxbb_valuearray[7] = 0x01; + + priv->cck_txbbgain_table[20].ccktxbb_valuearray[0] = 0x11; + priv->cck_txbbgain_table[20].ccktxbb_valuearray[1] = 0x11; + priv->cck_txbbgain_table[20].ccktxbb_valuearray[2] = 0x0f; + priv->cck_txbbgain_table[20].ccktxbb_valuearray[3] = 0x0c; + priv->cck_txbbgain_table[20].ccktxbb_valuearray[4] = 0x09; + priv->cck_txbbgain_table[20].ccktxbb_valuearray[5] = 0x06; + priv->cck_txbbgain_table[20].ccktxbb_valuearray[6] = 0x03; + priv->cck_txbbgain_table[20].ccktxbb_valuearray[7] = 0x01; + + priv->cck_txbbgain_table[21].ccktxbb_valuearray[0] = 0x10; + priv->cck_txbbgain_table[21].ccktxbb_valuearray[1] = 0x10; + priv->cck_txbbgain_table[21].ccktxbb_valuearray[2] = 0x0e; + priv->cck_txbbgain_table[21].ccktxbb_valuearray[3] = 0x0b; + priv->cck_txbbgain_table[21].ccktxbb_valuearray[4] = 0x08; + priv->cck_txbbgain_table[21].ccktxbb_valuearray[5] = 0x05; + priv->cck_txbbgain_table[21].ccktxbb_valuearray[6] = 0x03; + priv->cck_txbbgain_table[21].ccktxbb_valuearray[7] = 0x01; + + priv->cck_txbbgain_table[22].ccktxbb_valuearray[0] = 0x0f; + priv->cck_txbbgain_table[22].ccktxbb_valuearray[1] = 0x0f; + priv->cck_txbbgain_table[22].ccktxbb_valuearray[2] = 0x0d; + priv->cck_txbbgain_table[22].ccktxbb_valuearray[3] = 0x0b; + priv->cck_txbbgain_table[22].ccktxbb_valuearray[4] = 0x08; + priv->cck_txbbgain_table[22].ccktxbb_valuearray[5] = 0x05; + priv->cck_txbbgain_table[22].ccktxbb_valuearray[6] = 0x03; + priv->cck_txbbgain_table[22].ccktxbb_valuearray[7] = 0x01; + + priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[0] = 0x36; + priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[1] = 0x35; + priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[2] = 0x2e; + priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[3] = 0x1b; + priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[0] = 0x33; + priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[1] = 0x32; + priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[2] = 0x2b; + priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[3] = 0x19; + priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[0] = 0x30; + priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[1] = 0x2f; + priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[2] = 0x29; + priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[3] = 0x18; + priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[0] = 0x2d; + priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[1] = 0x2d; + priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[2] = 0x27; + priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[3] = 0x17; + priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[0] = 0x2b; + priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[1] = 0x2a; + priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[2] = 0x25; + priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[3] = 0x15; + priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[0] = 0x28; + priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[1] = 0x28; + priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[2] = 0x22; + priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[3] = 0x14; + priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[0] = 0x26; + priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[1] = 0x25; + priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[2] = 0x21; + priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[3] = 0x13; + priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[0] = 0x24; + priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[1] = 0x23; + priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[2] = 0x1f; + priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[3] = 0x12; + priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[0] = 0x22; + priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[1] = 0x21; + priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[2] = 0x1d; + priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[3] = 0x11; + priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[0] = 0x20; + priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[1] = 0x20; + priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[2] = 0x1b; + priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[3] = 0x10; + priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[0] = 0x1f; + priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[1] = 0x1e; + priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[2] = 0x1a; + priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[3] = 0x0f; + priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[0] = 0x1d; + priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[1] = 0x1c; + priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[2] = 0x18; + priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[3] = 0x0e; + priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[0] = 0x1b; + priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[1] = 0x1a; + priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[2] = 0x17; + priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[3] = 0x0e; + priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[0] = 0x1a; + priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[1] = 0x19; + priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[2] = 0x16; + priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[3] = 0x0d; + priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[0] = 0x18; + priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[1] = 0x17; + priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[2] = 0x15; + priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[3] = 0x0c; + priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[0] = 0x17; + priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[1] = 0x16; + priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[2] = 0x13; + priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[3] = 0x0b; + priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[0] = 0x16; + priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[1] = 0x15; + priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[2] = 0x12; + priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[3] = 0x0b; + priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[0] = 0x14; + priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[1] = 0x14; + priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[2] = 0x11; + priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[3] = 0x0a; + priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[0] = 0x13; + priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[1] = 0x13; + priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[2] = 0x10; + priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[3] = 0x0a; + priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[0] = 0x12; + priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[1] = 0x12; + priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[2] = 0x0f; + priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[3] = 0x09; + priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[0] = 0x11; + priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[1] = 0x11; + priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[2] = 0x0f; + priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[3] = 0x09; + priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[0] = 0x10; + priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[1] = 0x10; + priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[2] = 0x0e; + priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[3] = 0x08; + priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[0] = 0x0f; + priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[1] = 0x0f; + priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[2] = 0x0d; + priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[3] = 0x08; + priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[7] = 0x00; + + priv->btxpower_tracking = true; + priv->txpower_count = 0; + priv->btxpower_trackingInit = false; + +} + +static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + + if (priv->rtllib->FwRWRF) + priv->btxpower_tracking = true; + else + priv->btxpower_tracking = false; + priv->txpower_count = 0; + priv->btxpower_trackingInit = false; + RT_TRACE(COMP_POWER_TRACKING, "pMgntInfo->bTXPowerTracking = %d\n", + priv->btxpower_tracking); +} + +void dm_initialize_txpower_tracking(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + if (priv->IC_Cut >= IC_VersionCut_D) + dm_InitializeTXPowerTracking_TSSI(dev); + else + dm_InitializeTXPowerTracking_ThermalMeter(dev); +} + +static void dm_CheckTXPowerTracking_TSSI(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + static u32 tx_power_track_counter; + RT_TRACE(COMP_POWER_TRACKING, "%s()\n", __func__); + if (read_nic_byte(dev, 0x11e) == 1) + return; + if (!priv->btxpower_tracking) + return; + tx_power_track_counter++; + + + if (tx_power_track_counter >= 180) { + queue_delayed_work_rsl(priv->priv_wq, &priv->txpower_tracking_wq, 0); + tx_power_track_counter = 0; + } + +} +static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + static u8 TM_Trigger; + u8 TxPowerCheckCnt = 0; + + if (IS_HARDWARE_TYPE_8192SE(dev)) + TxPowerCheckCnt = 5; + else + TxPowerCheckCnt = 2; + if (!priv->btxpower_tracking) { + return; + } else { + if (priv->txpower_count <= TxPowerCheckCnt) { + priv->txpower_count++; + return; + } + } + + if (!TM_Trigger) { + { + rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d); + rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f); + rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d); + rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f); + } + TM_Trigger = 1; + return; + } else { + printk(KERN_INFO "===============>Schedule TxPowerTrackingWorkItem\n"); + + queue_delayed_work_rsl(priv->priv_wq, &priv->txpower_tracking_wq, 0); + TM_Trigger = 0; + } + + } + +static void dm_check_txpower_tracking(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + if (priv->IC_Cut >= IC_VersionCut_D) + dm_CheckTXPowerTracking_TSSI(dev); + else + dm_CheckTXPowerTracking_ThermalMeter(dev); +} + +static void dm_CCKTxPowerAdjust_TSSI(struct net_device *dev, bool bInCH14) +{ + u32 TempVal; + struct r8192_priv *priv = rtllib_priv(dev); + TempVal = 0; + if (!bInCH14) { + TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[0] + + (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[1]<<8)) ; + + rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); + TempVal = 0; + TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[2] + + (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[3]<<8) + + (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[4]<<16)+ + (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[5]<<24)); + rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); + TempVal = 0; + TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[6] + + (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[7]<<8)) ; + + rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); + } else { + TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[0] + + (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[1]<<8)) ; + + rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); + TempVal = 0; + TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[2] + + (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[3]<<8) + + (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[4]<<16)+ + (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[5]<<24)); + rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); + TempVal = 0; + TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[6] + + (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[7]<<8)) ; + + rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); + } + + +} + +static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH14) +{ + u32 TempVal; + struct r8192_priv *priv = rtllib_priv(dev); + + TempVal = 0; + if (!bInCH14) { + TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] + + (CCKSwingTable_Ch1_Ch13[priv->CCK_index][1]<<8) ; + rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); + RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n", + rCCK0_TxFilter1, TempVal); + TempVal = 0; + TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][2] + + (CCKSwingTable_Ch1_Ch13[priv->CCK_index][3]<<8) + + (CCKSwingTable_Ch1_Ch13[priv->CCK_index][4]<<16)+ + (CCKSwingTable_Ch1_Ch13[priv->CCK_index][5]<<24); + rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); + RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n", + rCCK0_TxFilter2, TempVal); + TempVal = 0; + TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] + + (CCKSwingTable_Ch1_Ch13[priv->CCK_index][7]<<8) ; + + rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); + RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n", + rCCK0_DebugPort, TempVal); + } else { + TempVal = CCKSwingTable_Ch14[priv->CCK_index][0] + + (CCKSwingTable_Ch14[priv->CCK_index][1]<<8) ; + + rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); + RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n", + rCCK0_TxFilter1, TempVal); + TempVal = 0; + TempVal = CCKSwingTable_Ch14[priv->CCK_index][2] + + (CCKSwingTable_Ch14[priv->CCK_index][3]<<8) + + (CCKSwingTable_Ch14[priv->CCK_index][4]<<16)+ + (CCKSwingTable_Ch14[priv->CCK_index][5]<<24); + rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); + RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n", + rCCK0_TxFilter2, TempVal); + TempVal = 0; + TempVal = CCKSwingTable_Ch14[priv->CCK_index][6] + + (CCKSwingTable_Ch14[priv->CCK_index][7]<<8) ; + + rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); + RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n", + rCCK0_DebugPort, TempVal); + } + } + +void dm_cck_txpower_adjust(struct net_device *dev, bool binch14) +{ + struct r8192_priv *priv = rtllib_priv(dev); + if (priv->IC_Cut >= IC_VersionCut_D) + dm_CCKTxPowerAdjust_TSSI(dev, binch14); + else + dm_CCKTxPowerAdjust_ThermalMeter(dev, binch14); +} + +static void dm_txpower_reset_recovery(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + RT_TRACE(COMP_POWER_TRACKING, "Start Reset Recovery ==>\n"); + rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, + priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value); + RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc80 is %08x\n", + priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value); + RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFA_txPowerTrackingIndex is %x\n", + priv->rfa_txpowertrackingindex); + RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF A I/Q Amplify Gain is %ld\n", + priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbb_iq_amplifygain); + RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: CCK Attenuation is %d dB\n", + priv->CCKPresentAttentuation); + dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + + rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, + priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value); + RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x\n", + priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value); + RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x\n", + priv->rfc_txpowertrackingindex); + RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF C I/Q Amplify Gain is %ld\n", + priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbb_iq_amplifygain); + +} + +void dm_restore_dynamic_mechanism_state(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u32 reg_ratr = priv->rate_adaptive.last_ratr; + u32 ratr_value; + + if (IS_NIC_DOWN(priv)) { + RT_TRACE(COMP_RATE, "<---- dm_restore_dynamic_mechanism_state(): driver is going to unload\n"); + return; + } + + if (priv->rate_adaptive.rate_adaptive_disabled) + return; + if (!(priv->rtllib->mode == WIRELESS_MODE_N_24G || + priv->rtllib->mode == WIRELESS_MODE_N_5G)) + return; + ratr_value = reg_ratr; + if (priv->rf_type == RF_1T2R) + ratr_value &= ~(RATE_ALL_OFDM_2SS); + write_nic_dword(dev, RATR0, ratr_value); + write_nic_byte(dev, UFWP, 1); + if (priv->btxpower_trackingInit && priv->btxpower_tracking) + dm_txpower_reset_recovery(dev); + + dm_bb_initialgain_restore(dev); + +} + +static void dm_bb_initialgain_restore(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u32 bit_mask = 0x7f; + + if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI) + return; + + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); + rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1); + rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1); + rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, (u32)priv->initgain_backup.xcagccore1); + rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1); + bit_mask = bMaskByte2; + rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, (u32)priv->initgain_backup.cca); + + RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x\n", priv->initgain_backup.xaagccore1); + RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc58 is %x\n", priv->initgain_backup.xbagccore1); + RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc60 is %x\n", priv->initgain_backup.xcagccore1); + RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc68 is %x\n", priv->initgain_backup.xdagccore1); + RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n", priv->initgain_backup.cca); + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); + +} + + +void dm_backup_dynamic_mechanism_state(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + priv->bswitch_fsync = false; + priv->bfsync_processing = false; + dm_bb_initialgain_backup(dev); + +} + + +static void dm_bb_initialgain_backup(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u32 bit_mask = bMaskByte0; + + if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI) + return; + + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); + priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask); + priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask); + priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bit_mask); + priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bit_mask); + bit_mask = bMaskByte2; + priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bit_mask); + + RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc50 is %x\n", priv->initgain_backup.xaagccore1); + RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc58 is %x\n", priv->initgain_backup.xbagccore1); + RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc60 is %x\n", priv->initgain_backup.xcagccore1); + RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc68 is %x\n", priv->initgain_backup.xdagccore1); + RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xa0a is %x\n", priv->initgain_backup.cca); + +} + +void dm_change_dynamic_initgain_thresh(struct net_device *dev, + u32 dm_type, u32 dm_value) +{ + if (dm_type == DIG_TYPE_THRESH_HIGH) { + dm_digtable.rssi_high_thresh = dm_value; + } else if (dm_type == DIG_TYPE_THRESH_LOW) { + dm_digtable.rssi_low_thresh = dm_value; + } else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH) { + dm_digtable.rssi_high_power_highthresh = dm_value; + } else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH) { + dm_digtable.rssi_high_power_highthresh = dm_value; + } else if (dm_type == DIG_TYPE_ENABLE) { + dm_digtable.dig_state = DM_STA_DIG_MAX; + dm_digtable.dig_enable_flag = true; + } else if (dm_type == DIG_TYPE_DISABLE) { + dm_digtable.dig_state = DM_STA_DIG_MAX; + dm_digtable.dig_enable_flag = false; + } else if (dm_type == DIG_TYPE_DBG_MODE) { + if (dm_value >= DM_DBG_MAX) + dm_value = DM_DBG_OFF; + dm_digtable.dbg_mode = (u8)dm_value; + } else if (dm_type == DIG_TYPE_RSSI) { + if (dm_value > 100) + dm_value = 30; + dm_digtable.rssi_val = (long)dm_value; + } else if (dm_type == DIG_TYPE_ALGORITHM) { + if (dm_value >= DIG_ALGO_MAX) + dm_value = DIG_ALGO_BY_FALSE_ALARM; + if (dm_digtable.dig_algorithm != (u8)dm_value) + dm_digtable.dig_algorithm_switch = 1; + dm_digtable.dig_algorithm = (u8)dm_value; + } else if (dm_type == DIG_TYPE_BACKOFF) { + if (dm_value > 30) + dm_value = 30; + dm_digtable.backoff_val = (u8)dm_value; + } else if (dm_type == DIG_TYPE_RX_GAIN_MIN) { + if (dm_value == 0) + dm_value = 0x1; + dm_digtable.rx_gain_range_min = (u8)dm_value; + } else if (dm_type == DIG_TYPE_RX_GAIN_MAX) { + if (dm_value > 0x50) + dm_value = 0x50; + dm_digtable.rx_gain_range_max = (u8)dm_value; + } +} + +static void dm_dig_init(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + dm_digtable.dig_enable_flag = true; + dm_digtable.Backoff_Enable_Flag = true; + + dm_digtable.dig_algorithm = DIG_ALGO_BY_RSSI; + + dm_digtable.Dig_TwoPort_Algorithm = DIG_TWO_PORT_ALGO_RSSI; + dm_digtable.Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_MAX; + dm_digtable.dbg_mode = DM_DBG_OFF; + dm_digtable.dig_algorithm_switch = 0; + + dm_digtable.dig_state = DM_STA_DIG_MAX; + dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX; + dm_digtable.CurSTAConnectState = dm_digtable.PreSTAConnectState = DIG_STA_DISCONNECT; + dm_digtable.CurAPConnectState = dm_digtable.PreAPConnectState = DIG_AP_DISCONNECT; + dm_digtable.initialgain_lowerbound_state = false; + + dm_digtable.rssi_low_thresh = DM_DIG_THRESH_LOW; + dm_digtable.rssi_high_thresh = DM_DIG_THRESH_HIGH; + + dm_digtable.FALowThresh = DM_FALSEALARM_THRESH_LOW; + dm_digtable.FAHighThresh = DM_FALSEALARM_THRESH_HIGH; + + dm_digtable.rssi_high_power_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW; + dm_digtable.rssi_high_power_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH; + + dm_digtable.rssi_val = 50; + dm_digtable.backoff_val = DM_DIG_BACKOFF; + dm_digtable.rx_gain_range_max = DM_DIG_MAX; + if (priv->CustomerID == RT_CID_819x_Netcore) + dm_digtable.rx_gain_range_min = DM_DIG_MIN_Netcore; + else + dm_digtable.rx_gain_range_min = DM_DIG_MIN; + + dm_digtable.BackoffVal_range_max = DM_DIG_BACKOFF_MAX; + dm_digtable.BackoffVal_range_min = DM_DIG_BACKOFF_MIN; +} + +static void dm_ctrl_initgain_byrssi(struct net_device *dev) +{ + + if (dm_digtable.dig_enable_flag == false) + return; + + if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) + dm_ctrl_initgain_byrssi_by_fwfalse_alarm(dev); + else if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI) + dm_ctrl_initgain_byrssi_by_driverrssi(dev); + else + return; +} + +/*----------------------------------------------------------------------------- + * Function: dm_CtrlInitGainBeforeConnectByRssiAndFalseAlarm() + * + * Overview: Driver monitor RSSI and False Alarm to change initial gain. + Only change initial gain during link in progress. + * + * Input: IN PADAPTER pAdapter + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 03/04/2009 hpfan Create Version 0. + * + *---------------------------------------------------------------------------*/ + +static void dm_ctrl_initgain_byrssi_by_driverrssi( + struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u8 i; + static u8 fw_dig; + + if (dm_digtable.dig_enable_flag == false) + return; + + if (dm_digtable.dig_algorithm_switch) + fw_dig = 0; + if (fw_dig <= 3) { + for (i = 0; i < 3; i++) + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); + fw_dig++; + dm_digtable.dig_state = DM_STA_DIG_OFF; + } + + if (priv->rtllib->state == RTLLIB_LINKED) + dm_digtable.CurSTAConnectState = DIG_STA_CONNECT; + else + dm_digtable.CurSTAConnectState = DIG_STA_DISCONNECT; + + + if (dm_digtable.dbg_mode == DM_DBG_OFF) + dm_digtable.rssi_val = priv->undecorated_smoothed_pwdb; + dm_initial_gain(dev); + dm_pd_th(dev); + dm_cs_ratio(dev); + if (dm_digtable.dig_algorithm_switch) + dm_digtable.dig_algorithm_switch = 0; + dm_digtable.PreSTAConnectState = dm_digtable.CurSTAConnectState; + +} + +static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm( + struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + static u32 reset_cnt; + u8 i; + + if (dm_digtable.dig_enable_flag == false) + return; + + if (dm_digtable.dig_algorithm_switch) { + dm_digtable.dig_state = DM_STA_DIG_MAX; + for (i = 0; i < 3; i++) + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); + dm_digtable.dig_algorithm_switch = 0; + } + + if (priv->rtllib->state != RTLLIB_LINKED) + return; + + if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_low_thresh) && + (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_thresh)) + return; + if ((priv->undecorated_smoothed_pwdb <= dm_digtable.rssi_low_thresh)) { + if (dm_digtable.dig_state == DM_STA_DIG_OFF && + (priv->reset_count == reset_cnt)) + return; + else + reset_cnt = priv->reset_count; + + dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX; + dm_digtable.dig_state = DM_STA_DIG_OFF; + + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); + + write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17); + write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17); + write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x17); + write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x17); + + if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00); + else + write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); + + write_nic_byte(dev, 0xa0a, 0x08); + + return; + } + + if ((priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh)) { + u8 reset_flag = 0; + + if (dm_digtable.dig_state == DM_STA_DIG_ON && + (priv->reset_count == reset_cnt)) { + dm_ctrl_initgain_byrssi_highpwr(dev); + return; + } else { + if (priv->reset_count != reset_cnt) + reset_flag = 1; + + reset_cnt = priv->reset_count; + } + + dm_digtable.dig_state = DM_STA_DIG_ON; + + if (reset_flag == 1) { + write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c); + write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c); + write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x2c); + write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x2c); + } else { + write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20); + write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20); + write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x20); + write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x20); + } + + if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20); + else + write_nic_byte(dev, rOFDM0_RxDetector1, 0x44); + + write_nic_byte(dev, 0xa0a, 0xcd); + + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); + } + dm_ctrl_initgain_byrssi_highpwr(dev); +} + + +static void dm_ctrl_initgain_byrssi_highpwr(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + static u32 reset_cnt_highpwr; + + if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_high_power_lowthresh) && + (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_highthresh)) + return; + + if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_power_highthresh) { + if (dm_digtable.dig_highpwr_state == DM_STA_DIG_ON && + (priv->reset_count == reset_cnt_highpwr)) + return; + else + dm_digtable.dig_highpwr_state = DM_STA_DIG_ON; + + if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10); + else + write_nic_byte(dev, rOFDM0_RxDetector1, 0x43); + } else { + if (dm_digtable.dig_highpwr_state == DM_STA_DIG_OFF && + (priv->reset_count == reset_cnt_highpwr)) + return; + else + dm_digtable.dig_highpwr_state = DM_STA_DIG_OFF; + + if (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_lowthresh && + priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) { + if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20); + else + write_nic_byte(dev, rOFDM0_RxDetector1, 0x44); + } + } + reset_cnt_highpwr = priv->reset_count; +} + +static void dm_initial_gain(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u8 initial_gain = 0; + static u8 initialized, force_write; + static u32 reset_cnt; + + if (dm_digtable.dig_algorithm_switch) { + initialized = 0; + reset_cnt = 0; + } + + if (rtllib_act_scanning(priv->rtllib, true) == true) { + force_write = 1; + return; + } + + if (dm_digtable.PreSTAConnectState == dm_digtable.CurSTAConnectState) { + if (dm_digtable.CurSTAConnectState == DIG_STA_CONNECT) { + if ((dm_digtable.rssi_val+10-dm_digtable.backoff_val) > dm_digtable.rx_gain_range_max) + dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_max; + else if ((dm_digtable.rssi_val+10-dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min) + dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_min; + else + dm_digtable.cur_ig_value = dm_digtable.rssi_val+10-dm_digtable.backoff_val; + } else { + if (dm_digtable.cur_ig_value == 0) + dm_digtable.cur_ig_value = priv->DefaultInitialGain[0]; + else + dm_digtable.cur_ig_value = dm_digtable.pre_ig_value; + } + } else { + dm_digtable.cur_ig_value = priv->DefaultInitialGain[0]; + dm_digtable.pre_ig_value = 0; + } + + if (priv->reset_count != reset_cnt) { + force_write = 1; + reset_cnt = priv->reset_count; + } + + if (dm_digtable.pre_ig_value != read_nic_byte(dev, rOFDM0_XAAGCCore1)) + force_write = 1; + + if ((dm_digtable.pre_ig_value != dm_digtable.cur_ig_value) + || !initialized || force_write) { + initial_gain = (u8)dm_digtable.cur_ig_value; + write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); + write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); + write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); + write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); + dm_digtable.pre_ig_value = dm_digtable.cur_ig_value; + initialized = 1; + force_write = 0; + } +} + +static void dm_pd_th(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + static u8 initialized, force_write; + static u32 reset_cnt; + + if (dm_digtable.dig_algorithm_switch) { + initialized = 0; + reset_cnt = 0; + } + + if (dm_digtable.PreSTAConnectState == dm_digtable.CurSTAConnectState) { + if (dm_digtable.CurSTAConnectState == DIG_STA_CONNECT) { + if (dm_digtable.rssi_val >= dm_digtable.rssi_high_power_highthresh) + dm_digtable.curpd_thstate = DIG_PD_AT_HIGH_POWER; + else if ((dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh)) + dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER; + else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) && + (dm_digtable.rssi_val < dm_digtable.rssi_high_power_lowthresh)) + dm_digtable.curpd_thstate = DIG_PD_AT_NORMAL_POWER; + else + dm_digtable.curpd_thstate = dm_digtable.prepd_thstate; + } else { + dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER; + } + } else { + dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER; + } + + if (priv->reset_count != reset_cnt) { + force_write = 1; + reset_cnt = priv->reset_count; + } + + if ((dm_digtable.prepd_thstate != dm_digtable.curpd_thstate) || + (initialized <= 3) || force_write) { + if (dm_digtable.curpd_thstate == DIG_PD_AT_LOW_POWER) { + if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00); + else + write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); + } else if (dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER) { + if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20); + else + write_nic_byte(dev, rOFDM0_RxDetector1, 0x44); + } else if (dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER) { + if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10); + else + write_nic_byte(dev, rOFDM0_RxDetector1, 0x43); + } + dm_digtable.prepd_thstate = dm_digtable.curpd_thstate; + if (initialized <= 3) + initialized++; + force_write = 0; + } +} + +static void dm_cs_ratio(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + static u8 initialized, force_write; + static u32 reset_cnt; + + if (dm_digtable.dig_algorithm_switch) { + initialized = 0; + reset_cnt = 0; + } + + if (dm_digtable.PreSTAConnectState == dm_digtable.CurSTAConnectState) { + if (dm_digtable.CurSTAConnectState == DIG_STA_CONNECT) { + if ((dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh)) + dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER; + else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh)) + dm_digtable.curcs_ratio_state = DIG_CS_RATIO_HIGHER; + else + dm_digtable.curcs_ratio_state = dm_digtable.precs_ratio_state; + } else { + dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER; + } + } else { + dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER; + } + + if (priv->reset_count != reset_cnt) { + force_write = 1; + reset_cnt = priv->reset_count; + } + + + if ((dm_digtable.precs_ratio_state != dm_digtable.curcs_ratio_state) || + !initialized || force_write) { + if (dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER) + write_nic_byte(dev, 0xa0a, 0x08); + else if (dm_digtable.curcs_ratio_state == DIG_CS_RATIO_HIGHER) + write_nic_byte(dev, 0xa0a, 0xcd); + dm_digtable.precs_ratio_state = dm_digtable.curcs_ratio_state; + initialized = 1; + force_write = 0; + } +} + +void dm_init_edca_turbo(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + priv->bcurrent_turbo_EDCA = false; + priv->rtllib->bis_any_nonbepkts = false; + priv->bis_cur_rdlstate = false; +} + +static void dm_check_edca_turbo(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rt_hi_throughput *pHTInfo = priv->rtllib->pHTInfo; + + static unsigned long lastTxOkCnt; + static unsigned long lastRxOkCnt; + unsigned long curTxOkCnt = 0; + unsigned long curRxOkCnt = 0; + + if (priv->rtllib->iw_mode == IW_MODE_ADHOC) + goto dm_CheckEdcaTurbo_EXIT; + if (priv->rtllib->state != RTLLIB_LINKED) + goto dm_CheckEdcaTurbo_EXIT; + if (priv->rtllib->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO) + goto dm_CheckEdcaTurbo_EXIT; + + { + u8 *peername[11] = { + "unknown", "realtek_90", "realtek_92se", "broadcom", + "ralink", "atheros", "cisco", "marvell", "92u_softap", + "self_softap" + }; + static int wb_tmp; + if (wb_tmp == 0) { + printk(KERN_INFO "%s():iot peer is %s, bssid:" + " %pM\n", __func__, + peername[pHTInfo->IOTPeer], + priv->rtllib->current_network.bssid); + wb_tmp = 1; + } + } + if (!priv->rtllib->bis_any_nonbepkts) { + curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt; + curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt; + if (pHTInfo->IOTAction & HT_IOT_ACT_EDCA_BIAS_ON_RX) { + if (curTxOkCnt > 4*curRxOkCnt) { + if (priv->bis_cur_rdlstate || + !priv->bcurrent_turbo_EDCA) { + write_nic_dword(dev, EDCAPARA_BE, + edca_setting_UL[pHTInfo->IOTPeer]); + priv->bis_cur_rdlstate = false; + } + } else { + if (!priv->bis_cur_rdlstate || + !priv->bcurrent_turbo_EDCA) { + if (priv->rtllib->mode == WIRELESS_MODE_G) + write_nic_dword(dev, EDCAPARA_BE, + edca_setting_DL_GMode[pHTInfo->IOTPeer]); + else + write_nic_dword(dev, EDCAPARA_BE, + edca_setting_DL[pHTInfo->IOTPeer]); + priv->bis_cur_rdlstate = true; + } + } + priv->bcurrent_turbo_EDCA = true; + } else { + if (curRxOkCnt > 4*curTxOkCnt) { + if (!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) { + if (priv->rtllib->mode == WIRELESS_MODE_G) + write_nic_dword(dev, EDCAPARA_BE, + edca_setting_DL_GMode[pHTInfo->IOTPeer]); + else + write_nic_dword(dev, EDCAPARA_BE, + edca_setting_DL[pHTInfo->IOTPeer]); + priv->bis_cur_rdlstate = true; + } + } else { + if (priv->bis_cur_rdlstate || + !priv->bcurrent_turbo_EDCA) { + write_nic_dword(dev, EDCAPARA_BE, + edca_setting_UL[pHTInfo->IOTPeer]); + priv->bis_cur_rdlstate = false; + } + + } + + priv->bcurrent_turbo_EDCA = true; + } + } else { + if (priv->bcurrent_turbo_EDCA) { + u8 tmp = AC0_BE; + priv->rtllib->SetHwRegHandler(dev, HW_VAR_AC_PARAM, (u8 *)(&tmp)); + priv->bcurrent_turbo_EDCA = false; + } + } + + +dm_CheckEdcaTurbo_EXIT: + priv->rtllib->bis_any_nonbepkts = false; + lastTxOkCnt = priv->stats.txbytesunicast; + lastRxOkCnt = priv->stats.rxbytesunicast; +} + +static void dm_init_ctstoself(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv((struct net_device *)dev); + + priv->rtllib->bCTSToSelfEnable = true; + priv->rtllib->CTSToSelfTH = CTSToSelfTHVal; +} + +static void dm_ctstoself(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv((struct net_device *)dev); + struct rt_hi_throughput *pHTInfo = priv->rtllib->pHTInfo; + static unsigned long lastTxOkCnt; + static unsigned long lastRxOkCnt; + unsigned long curTxOkCnt = 0; + unsigned long curRxOkCnt = 0; + + if (priv->rtllib->bCTSToSelfEnable != true) { + pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF; + return; + } + if (pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM) { + curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt; + curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt; + if (curRxOkCnt > 4*curTxOkCnt) + pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF; + else + pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF; + + lastTxOkCnt = priv->stats.txbytesunicast; + lastRxOkCnt = priv->stats.rxbytesunicast; + } +} + + +static void dm_Init_WA_Broadcom_IOT(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv((struct net_device *)dev); + struct rt_hi_throughput *pHTInfo = priv->rtllib->pHTInfo; + + pHTInfo->bWAIotBroadcom = false; + pHTInfo->WAIotTH = WAIotTHVal; +} + +static void dm_check_pbc_gpio(struct net_device *dev) +{ +} + +void dm_CheckRfCtrlGPIO(void *data) +{ + struct r8192_priv *priv = container_of_dwork_rsl(data, + struct r8192_priv, gpio_change_rf_wq); + struct net_device *dev = priv->rtllib->dev; + u8 tmp1byte; + enum rt_rf_power_state eRfPowerStateToSet; + bool bActuallySet = false; + char *argv[3]; + static char *RadioPowerPath = "/etc/acpi/events/RadioPower.sh"; + static char *envp[] = {"HOME=/", "TERM=linux", "PATH=/usr/bin:/bin", NULL}; + + bActuallySet = false; + + if ((priv->up_first_time == 1) || (priv->being_init_adapter)) + return; + + if (priv->bfirst_after_down) { + priv->bfirst_after_down = 1; + return; + } + + tmp1byte = read_nic_byte(dev, GPI); + + eRfPowerStateToSet = (tmp1byte&BIT1) ? eRfOn : eRfOff; + + if ((priv->bHwRadioOff == true) && (eRfPowerStateToSet == eRfOn)) { + RT_TRACE(COMP_RF, "gpiochangeRF - HW Radio ON\n"); + printk(KERN_INFO "gpiochangeRF - HW Radio ON\n"); + priv->bHwRadioOff = false; + bActuallySet = true; + } else if ((priv->bHwRadioOff == false) && (eRfPowerStateToSet == eRfOff)) { + RT_TRACE(COMP_RF, "gpiochangeRF - HW Radio OFF\n"); + printk(KERN_INFO "gpiochangeRF - HW Radio OFF\n"); + priv->bHwRadioOff = true; + bActuallySet = true; + } + + if (bActuallySet) { + mdelay(1000); + priv->bHwRfOffAction = 1; + MgntActSet_RF_State(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW, true); + if (priv->bHwRadioOff == true) + argv[1] = "RFOFF"; + else + argv[1] = "RFON"; + + argv[0] = RadioPowerPath; + argv[2] = NULL; + call_usermodehelper(RadioPowerPath, argv, envp, 1); + } +} + +void dm_rf_pathcheck_workitemcallback(void *data) +{ + struct r8192_priv *priv = container_of_dwork_rsl(data, + struct r8192_priv, + rfpath_check_wq); + struct net_device *dev = priv->rtllib->dev; + u8 rfpath = 0, i; + + rfpath = read_nic_byte(dev, 0xc04); + + for (i = 0; i < RF90_PATH_MAX; i++) { + if (rfpath & (0x01<<i)) + priv->brfpath_rxenable[i] = 1; + else + priv->brfpath_rxenable[i] = 0; + } + if (!DM_RxPathSelTable.Enable) + return; + + dm_rxpath_sel_byrssi(dev); +} + +static void dm_init_rxpath_selection(struct net_device *dev) +{ + u8 i; + struct r8192_priv *priv = rtllib_priv(dev); + + DM_RxPathSelTable.Enable = 1; + DM_RxPathSelTable.SS_TH_low = RxPathSelection_SS_TH_low; + DM_RxPathSelTable.diff_TH = RxPathSelection_diff_TH; + if (priv->CustomerID == RT_CID_819x_Netcore) + DM_RxPathSelTable.cck_method = CCK_Rx_Version_2; + else + DM_RxPathSelTable.cck_method = CCK_Rx_Version_1; + DM_RxPathSelTable.DbgMode = DM_DBG_OFF; + DM_RxPathSelTable.disabledRF = 0; + for (i = 0; i < 4; i++) { + DM_RxPathSelTable.rf_rssi[i] = 50; + DM_RxPathSelTable.cck_pwdb_sta[i] = -64; + DM_RxPathSelTable.rf_enable_rssi_th[i] = 100; + } +} + +#define PWDB_IN_RANGE ((cur_cck_pwdb < tmp_cck_max_pwdb) && \ + (cur_cck_pwdb > tmp_cck_sec_pwdb)) + +static void dm_rxpath_sel_byrssi(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u8 i, max_rssi_index = 0, min_rssi_index = 0; + u8 sec_rssi_index = 0, rf_num = 0; + u8 tmp_max_rssi = 0, tmp_min_rssi = 0, tmp_sec_rssi = 0; + u8 cck_default_Rx = 0x2; + u8 cck_optional_Rx = 0x3; + long tmp_cck_max_pwdb = 0, tmp_cck_min_pwdb = 0, tmp_cck_sec_pwdb = 0; + u8 cck_rx_ver2_max_index = 0, cck_rx_ver2_min_index = 0; + u8 cck_rx_ver2_sec_index = 0; + u8 cur_rf_rssi; + long cur_cck_pwdb; + static u8 disabled_rf_cnt, cck_Rx_Path_initialized; + u8 update_cck_rx_path; + + if (priv->rf_type != RF_2T4R) + return; + + if (!cck_Rx_Path_initialized) { + DM_RxPathSelTable.cck_Rx_path = (read_nic_byte(dev, 0xa07)&0xf); + cck_Rx_Path_initialized = 1; + } + + DM_RxPathSelTable.disabledRF = 0xf; + DM_RxPathSelTable.disabledRF &= ~(read_nic_byte(dev, 0xc04)); + + if (priv->rtllib->mode == WIRELESS_MODE_B) + DM_RxPathSelTable.cck_method = CCK_Rx_Version_2; + + for (i = 0; i < RF90_PATH_MAX; i++) { + if (!DM_RxPathSelTable.DbgMode) + DM_RxPathSelTable.rf_rssi[i] = priv->stats.rx_rssi_percentage[i]; + + if (priv->brfpath_rxenable[i]) { + rf_num++; + cur_rf_rssi = DM_RxPathSelTable.rf_rssi[i]; + + if (rf_num == 1) { + max_rssi_index = min_rssi_index = sec_rssi_index = i; + tmp_max_rssi = tmp_min_rssi = tmp_sec_rssi = cur_rf_rssi; + } else if (rf_num == 2) { + if (cur_rf_rssi >= tmp_max_rssi) { + tmp_max_rssi = cur_rf_rssi; + max_rssi_index = i; + } else { + tmp_sec_rssi = tmp_min_rssi = cur_rf_rssi; + sec_rssi_index = min_rssi_index = i; + } + } else { + if (cur_rf_rssi > tmp_max_rssi) { + tmp_sec_rssi = tmp_max_rssi; + sec_rssi_index = max_rssi_index; + tmp_max_rssi = cur_rf_rssi; + max_rssi_index = i; + } else if (cur_rf_rssi == tmp_max_rssi) { + tmp_sec_rssi = cur_rf_rssi; + sec_rssi_index = i; + } else if ((cur_rf_rssi < tmp_max_rssi) && + (cur_rf_rssi > tmp_sec_rssi)) { + tmp_sec_rssi = cur_rf_rssi; + sec_rssi_index = i; + } else if (cur_rf_rssi == tmp_sec_rssi) { + if (tmp_sec_rssi == tmp_min_rssi) { + tmp_sec_rssi = cur_rf_rssi; + sec_rssi_index = i; + } + } else if ((cur_rf_rssi < tmp_sec_rssi) && + (cur_rf_rssi > tmp_min_rssi)) { + ; + } else if (cur_rf_rssi == tmp_min_rssi) { + if (tmp_sec_rssi == tmp_min_rssi) { + tmp_min_rssi = cur_rf_rssi; + min_rssi_index = i; + } + } else if (cur_rf_rssi < tmp_min_rssi) { + tmp_min_rssi = cur_rf_rssi; + min_rssi_index = i; + } + } + } + } + + rf_num = 0; + if (DM_RxPathSelTable.cck_method == CCK_Rx_Version_2) { + for (i = 0; i < RF90_PATH_MAX; i++) { + if (priv->brfpath_rxenable[i]) { + rf_num++; + cur_cck_pwdb = + DM_RxPathSelTable.cck_pwdb_sta[i]; + + if (rf_num == 1) { + cck_rx_ver2_max_index = i; + cck_rx_ver2_min_index = i; + cck_rx_ver2_sec_index = i; + tmp_cck_max_pwdb = cur_cck_pwdb; + tmp_cck_min_pwdb = cur_cck_pwdb; + tmp_cck_sec_pwdb = cur_cck_pwdb; + } else if (rf_num == 2) { + if (cur_cck_pwdb >= tmp_cck_max_pwdb) { + tmp_cck_max_pwdb = cur_cck_pwdb; + cck_rx_ver2_max_index = i; + } else { + tmp_cck_sec_pwdb = cur_cck_pwdb; + tmp_cck_min_pwdb = cur_cck_pwdb; + cck_rx_ver2_sec_index = i; + cck_rx_ver2_min_index = i; + } + } else { + if (cur_cck_pwdb > tmp_cck_max_pwdb) { + tmp_cck_sec_pwdb = + tmp_cck_max_pwdb; + cck_rx_ver2_sec_index = + cck_rx_ver2_max_index; + tmp_cck_max_pwdb = cur_cck_pwdb; + cck_rx_ver2_max_index = i; + } else if (cur_cck_pwdb == + tmp_cck_max_pwdb) { + tmp_cck_sec_pwdb = cur_cck_pwdb; + cck_rx_ver2_sec_index = i; + } else if (PWDB_IN_RANGE) { + tmp_cck_sec_pwdb = cur_cck_pwdb; + cck_rx_ver2_sec_index = i; + } else if (cur_cck_pwdb == + tmp_cck_sec_pwdb) { + if (tmp_cck_sec_pwdb == + tmp_cck_min_pwdb) { + tmp_cck_sec_pwdb = + cur_cck_pwdb; + cck_rx_ver2_sec_index = + i; + } + } else if ((cur_cck_pwdb < tmp_cck_sec_pwdb) && + (cur_cck_pwdb > tmp_cck_min_pwdb)) { + ; + } else if (cur_cck_pwdb == tmp_cck_min_pwdb) { + if (tmp_cck_sec_pwdb == tmp_cck_min_pwdb) { + tmp_cck_min_pwdb = cur_cck_pwdb; + cck_rx_ver2_min_index = i; + } + } else if (cur_cck_pwdb < tmp_cck_min_pwdb) { + tmp_cck_min_pwdb = cur_cck_pwdb; + cck_rx_ver2_min_index = i; + } + } + + } + } + } + + update_cck_rx_path = 0; + if (DM_RxPathSelTable.cck_method == CCK_Rx_Version_2) { + cck_default_Rx = cck_rx_ver2_max_index; + cck_optional_Rx = cck_rx_ver2_sec_index; + if (tmp_cck_max_pwdb != -64) + update_cck_rx_path = 1; + } + + if (tmp_min_rssi < DM_RxPathSelTable.SS_TH_low && disabled_rf_cnt < 2) { + if ((tmp_max_rssi - tmp_min_rssi) >= + DM_RxPathSelTable.diff_TH) { + DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] = + tmp_max_rssi+5; + rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, + 0x1<<min_rssi_index, 0x0); + rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, + 0x1<<min_rssi_index, 0x0); + disabled_rf_cnt++; + } + if (DM_RxPathSelTable.cck_method == CCK_Rx_Version_1) { + cck_default_Rx = max_rssi_index; + cck_optional_Rx = sec_rssi_index; + if (tmp_max_rssi) + update_cck_rx_path = 1; + } + } + + if (update_cck_rx_path) { + DM_RxPathSelTable.cck_Rx_path = (cck_default_Rx<<2) | + (cck_optional_Rx); + rtl8192_setBBreg(dev, rCCK0_AFESetting, 0x0f000000, + DM_RxPathSelTable.cck_Rx_path); + } + + if (DM_RxPathSelTable.disabledRF) { + for (i = 0; i < 4; i++) { + if ((DM_RxPathSelTable.disabledRF>>i) & 0x1) { + if (tmp_max_rssi >= + DM_RxPathSelTable.rf_enable_rssi_th[i]) { + rtl8192_setBBreg(dev, + rOFDM0_TRxPathEnable, 0x1 << i, + 0x1); + rtl8192_setBBreg(dev, + rOFDM1_TRxPathEnable, + 0x1 << i, 0x1); + DM_RxPathSelTable.rf_enable_rssi_th[i] + = 100; + disabled_rf_cnt--; + } + } + } + } +} + +static void dm_check_rx_path_selection(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + queue_delayed_work_rsl(priv->priv_wq, &priv->rfpath_check_wq, 0); +} + + +static void dm_init_fsync(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + priv->rtllib->fsync_time_interval = 500; + priv->rtllib->fsync_rate_bitmap = 0x0f000800; + priv->rtllib->fsync_rssi_threshold = 30; + priv->rtllib->bfsync_enable = false; + priv->rtllib->fsync_multiple_timeinterval = 3; + priv->rtllib->fsync_firstdiff_ratethreshold = 100; + priv->rtllib->fsync_seconddiff_ratethreshold = 200; + priv->rtllib->fsync_state = Default_Fsync; + priv->framesyncMonitor = 1; + + init_timer(&priv->fsync_timer); + setup_timer(&priv->fsync_timer, dm_fsync_timer_callback, + (unsigned long) dev); +} + + +static void dm_deInit_fsync(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + del_timer_sync(&priv->fsync_timer); +} + +void dm_fsync_timer_callback(unsigned long data) +{ + struct net_device *dev = (struct net_device *)data; + struct r8192_priv *priv = rtllib_priv((struct net_device *)data); + u32 rate_index, rate_count = 0, rate_count_diff = 0; + bool bSwitchFromCountDiff = false; + bool bDoubleTimeInterval = false; + + if (priv->rtllib->state == RTLLIB_LINKED && + priv->rtllib->bfsync_enable && + (priv->rtllib->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC)) { + u32 rate_bitmap; + for (rate_index = 0; rate_index <= 27; rate_index++) { + rate_bitmap = 1 << rate_index; + if (priv->rtllib->fsync_rate_bitmap & rate_bitmap) + rate_count += + priv->stats.received_rate_histogram[1] + [rate_index]; + } + + if (rate_count < priv->rate_record) + rate_count_diff = 0xffffffff - rate_count + + priv->rate_record; + else + rate_count_diff = rate_count - priv->rate_record; + if (rate_count_diff < priv->rateCountDiffRecord) { + + u32 DiffNum = priv->rateCountDiffRecord - + rate_count_diff; + if (DiffNum >= + priv->rtllib->fsync_seconddiff_ratethreshold) + priv->ContiuneDiffCount++; + else + priv->ContiuneDiffCount = 0; + + if (priv->ContiuneDiffCount >= 2) { + bSwitchFromCountDiff = true; + priv->ContiuneDiffCount = 0; + } + } else { + priv->ContiuneDiffCount = 0; + } + + if (rate_count_diff <= + priv->rtllib->fsync_firstdiff_ratethreshold) { + bSwitchFromCountDiff = true; + priv->ContiuneDiffCount = 0; + } + priv->rate_record = rate_count; + priv->rateCountDiffRecord = rate_count_diff; + RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rate" + "Countdiff %d bSwitchFsync %d\n", priv->rate_record, + rate_count, rate_count_diff, priv->bswitch_fsync); + if (priv->undecorated_smoothed_pwdb > + priv->rtllib->fsync_rssi_threshold && + bSwitchFromCountDiff) { + bDoubleTimeInterval = true; + priv->bswitch_fsync = !priv->bswitch_fsync; + if (priv->bswitch_fsync) { + write_nic_byte(dev, 0xC36, 0x1c); + write_nic_byte(dev, 0xC3e, 0x90); + } else { + write_nic_byte(dev, 0xC36, 0x5c); + write_nic_byte(dev, 0xC3e, 0x96); + } + } else if (priv->undecorated_smoothed_pwdb <= + priv->rtllib->fsync_rssi_threshold) { + if (priv->bswitch_fsync) { + priv->bswitch_fsync = false; + write_nic_byte(dev, 0xC36, 0x5c); + write_nic_byte(dev, 0xC3e, 0x96); + } + } + if (bDoubleTimeInterval) { + if (timer_pending(&priv->fsync_timer)) + del_timer_sync(&priv->fsync_timer); + priv->fsync_timer.expires = jiffies + + MSECS(priv->rtllib->fsync_time_interval * + priv->rtllib->fsync_multiple_timeinterval); + add_timer(&priv->fsync_timer); + } else { + if (timer_pending(&priv->fsync_timer)) + del_timer_sync(&priv->fsync_timer); + priv->fsync_timer.expires = jiffies + + MSECS(priv->rtllib->fsync_time_interval); + add_timer(&priv->fsync_timer); + } + } else { + if (priv->bswitch_fsync) { + priv->bswitch_fsync = false; + write_nic_byte(dev, 0xC36, 0x5c); + write_nic_byte(dev, 0xC3e, 0x96); + } + priv->ContiuneDiffCount = 0; + write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd); + } + RT_TRACE(COMP_HALDM, "ContiuneDiffCount %d\n", priv->ContiuneDiffCount); + RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d " + "bSwitchFsync %d\n", priv->rate_record, rate_count, + rate_count_diff, priv->bswitch_fsync); +} + +static void dm_StartHWFsync(struct net_device *dev) +{ + u8 rf_timing = 0x77; + struct r8192_priv *priv = rtllib_priv(dev); + RT_TRACE(COMP_HALDM, "%s\n", __func__); + write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cf); + priv->rtllib->SetHwRegHandler(dev, HW_VAR_RF_TIMING, + (u8 *)(&rf_timing)); + write_nic_byte(dev, 0xc3b, 0x41); +} + +static void dm_EndHWFsync(struct net_device *dev) +{ + u8 rf_timing = 0xaa; + struct r8192_priv *priv = rtllib_priv(dev); + RT_TRACE(COMP_HALDM, "%s\n", __func__); + write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd); + priv->rtllib->SetHwRegHandler(dev, HW_VAR_RF_TIMING, (u8 *) + (&rf_timing)); + write_nic_byte(dev, 0xc3b, 0x49); +} + +static void dm_EndSWFsync(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + RT_TRACE(COMP_HALDM, "%s\n", __func__); + del_timer_sync(&(priv->fsync_timer)); + + if (priv->bswitch_fsync) { + priv->bswitch_fsync = false; + + write_nic_byte(dev, 0xC36, 0x5c); + + write_nic_byte(dev, 0xC3e, 0x96); + } + + priv->ContiuneDiffCount = 0; + write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd); +} + +static void dm_StartSWFsync(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u32 rateIndex; + u32 rateBitmap; + + RT_TRACE(COMP_HALDM, "%s\n", __func__); + priv->rate_record = 0; + priv->ContiuneDiffCount = 0; + priv->rateCountDiffRecord = 0; + priv->bswitch_fsync = false; + + if (priv->rtllib->mode == WIRELESS_MODE_N_24G) { + priv->rtllib->fsync_firstdiff_ratethreshold = 600; + priv->rtllib->fsync_seconddiff_ratethreshold = 0xffff; + } else { + priv->rtllib->fsync_firstdiff_ratethreshold = 200; + priv->rtllib->fsync_seconddiff_ratethreshold = 200; + } + for (rateIndex = 0; rateIndex <= 27; rateIndex++) { + rateBitmap = 1 << rateIndex; + if (priv->rtllib->fsync_rate_bitmap & rateBitmap) + priv->rate_record += + priv->stats.received_rate_histogram[1] + [rateIndex]; + } + if (timer_pending(&priv->fsync_timer)) + del_timer_sync(&priv->fsync_timer); + priv->fsync_timer.expires = jiffies + + MSECS(priv->rtllib->fsync_time_interval); + add_timer(&priv->fsync_timer); + + write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cd); + +} + +void dm_check_fsync(struct net_device *dev) +{ +#define RegC38_Default 0 +#define RegC38_NonFsync_Other_AP 1 +#define RegC38_Fsync_AP_BCM 2 + struct r8192_priv *priv = rtllib_priv(dev); + static u8 reg_c38_State = RegC38_Default; + static u32 reset_cnt; + + RT_TRACE(COMP_HALDM, "RSSI %d TimeInterval %d MultipleTimeInterval " + "%d\n", priv->rtllib->fsync_rssi_threshold, + priv->rtllib->fsync_time_interval, + priv->rtllib->fsync_multiple_timeinterval); + RT_TRACE(COMP_HALDM, "RateBitmap 0x%x FirstDiffRateThreshold %d Second" + "DiffRateThreshold %d\n", priv->rtllib->fsync_rate_bitmap, + priv->rtllib->fsync_firstdiff_ratethreshold, + priv->rtllib->fsync_seconddiff_ratethreshold); + + if (priv->rtllib->state == RTLLIB_LINKED && + priv->rtllib->pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM) { + if (priv->rtllib->bfsync_enable == 0) { + switch (priv->rtllib->fsync_state) { + case Default_Fsync: + dm_StartHWFsync(dev); + priv->rtllib->fsync_state = HW_Fsync; + break; + case SW_Fsync: + dm_EndSWFsync(dev); + dm_StartHWFsync(dev); + priv->rtllib->fsync_state = HW_Fsync; + break; + case HW_Fsync: + default: + break; + } + } else { + switch (priv->rtllib->fsync_state) { + case Default_Fsync: + dm_StartSWFsync(dev); + priv->rtllib->fsync_state = SW_Fsync; + break; + case HW_Fsync: + dm_EndHWFsync(dev); + dm_StartSWFsync(dev); + priv->rtllib->fsync_state = SW_Fsync; + break; + case SW_Fsync: + default: + break; + + } + } + if (priv->framesyncMonitor) { + if (reg_c38_State != RegC38_Fsync_AP_BCM) { + write_nic_byte(dev, rOFDM0_RxDetector3, 0x95); + + reg_c38_State = RegC38_Fsync_AP_BCM; + } + } + } else { + switch (priv->rtllib->fsync_state) { + case HW_Fsync: + dm_EndHWFsync(dev); + priv->rtllib->fsync_state = Default_Fsync; + break; + case SW_Fsync: + dm_EndSWFsync(dev); + priv->rtllib->fsync_state = Default_Fsync; + break; + case Default_Fsync: + default: + break; + } + + if (priv->framesyncMonitor) { + if (priv->rtllib->state == RTLLIB_LINKED) { + if (priv->undecorated_smoothed_pwdb <= + RegC38_TH) { + if (reg_c38_State != + RegC38_NonFsync_Other_AP) { + write_nic_byte(dev, + rOFDM0_RxDetector3, + 0x90); + + reg_c38_State = + RegC38_NonFsync_Other_AP; + } + } else if (priv->undecorated_smoothed_pwdb >= + (RegC38_TH+5)) { + if (reg_c38_State) { + write_nic_byte(dev, + rOFDM0_RxDetector3, + priv->framesync); + reg_c38_State = RegC38_Default; + } + } + } else { + if (reg_c38_State) { + write_nic_byte(dev, rOFDM0_RxDetector3, + priv->framesync); + reg_c38_State = RegC38_Default; + } + } + } + } + if (priv->framesyncMonitor) { + if (priv->reset_count != reset_cnt) { + write_nic_byte(dev, rOFDM0_RxDetector3, + priv->framesync); + reg_c38_State = RegC38_Default; + reset_cnt = priv->reset_count; + } + } else { + if (reg_c38_State) { + write_nic_byte(dev, rOFDM0_RxDetector3, + priv->framesync); + reg_c38_State = RegC38_Default; + } + } +} + +void dm_shadow_init(struct net_device *dev) +{ + u8 page; + u16 offset; + + for (page = 0; page < 5; page++) + for (offset = 0; offset < 256; offset++) + dm_shadow[page][offset] = read_nic_byte(dev, + offset+page * 256); + + for (page = 8; page < 11; page++) + for (offset = 0; offset < 256; offset++) + dm_shadow[page][offset] = read_nic_byte(dev, + offset+page * 256); + + for (page = 12; page < 15; page++) + for (offset = 0; offset < 256; offset++) + dm_shadow[page][offset] = read_nic_byte(dev, + offset+page*256); + +} + +/*---------------------------Define function prototype------------------------*/ +static void dm_init_dynamic_txpower(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + priv->rtllib->bdynamic_txpower_enable = true; + priv->bLastDTPFlag_High = false; + priv->bLastDTPFlag_Low = false; + priv->bDynamicTxHighPower = false; + priv->bDynamicTxLowPower = false; +} + +static void dm_dynamic_txpower(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + unsigned int txhipower_threshhold = 0; + unsigned int txlowpower_threshold = 0; + if (priv->rtllib->bdynamic_txpower_enable != true) { + priv->bDynamicTxHighPower = false; + priv->bDynamicTxLowPower = false; + return; + } + if ((priv->rtllib->pHTInfo->IOTPeer == HT_IOT_PEER_ATHEROS) && + (priv->rtllib->mode == IEEE_G)) { + txhipower_threshhold = TX_POWER_ATHEROAP_THRESH_HIGH; + txlowpower_threshold = TX_POWER_ATHEROAP_THRESH_LOW; + } else { + txhipower_threshhold = TX_POWER_NEAR_FIELD_THRESH_HIGH; + txlowpower_threshold = TX_POWER_NEAR_FIELD_THRESH_LOW; + } + + RT_TRACE(COMP_TXAGC, "priv->undecorated_smoothed_pwdb = %ld\n", + priv->undecorated_smoothed_pwdb); + + if (priv->rtllib->state == RTLLIB_LINKED) { + if (priv->undecorated_smoothed_pwdb >= txhipower_threshhold) { + priv->bDynamicTxHighPower = true; + priv->bDynamicTxLowPower = false; + } else { + if (priv->undecorated_smoothed_pwdb < + txlowpower_threshold && + priv->bDynamicTxHighPower == true) + priv->bDynamicTxHighPower = false; + if (priv->undecorated_smoothed_pwdb < 35) + priv->bDynamicTxLowPower = true; + else if (priv->undecorated_smoothed_pwdb >= 40) + priv->bDynamicTxLowPower = false; + } + } else { + priv->bDynamicTxHighPower = false; + priv->bDynamicTxLowPower = false; + } + + if ((priv->bDynamicTxHighPower != priv->bLastDTPFlag_High) || + (priv->bDynamicTxLowPower != priv->bLastDTPFlag_Low)) { + RT_TRACE(COMP_TXAGC, "SetTxPowerLevel8190() channel = %d\n", + priv->rtllib->current_network.channel); + + rtl8192_phy_setTxPower(dev, + priv->rtllib->current_network.channel); + } + priv->bLastDTPFlag_High = priv->bDynamicTxHighPower; + priv->bLastDTPFlag_Low = priv->bDynamicTxLowPower; + +} + +static void dm_check_txrateandretrycount(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + + ieee->softmac_stats.CurrentShowTxate = read_nic_byte(dev, + Current_Tx_Rate_Reg); + + ieee->softmac_stats.last_packet_rate = read_nic_byte(dev, + Initial_Tx_Rate_Reg); + + ieee->softmac_stats.txretrycount = read_nic_dword(dev, + Tx_Retry_Count_Reg); +} + +static void dm_send_rssi_tofw(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + write_nic_byte(dev, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb); +} diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_dm.h b/drivers/staging/rtl8192e/rtl8192e/rtl_dm.h new file mode 100644 index 000000000000..ab44a9a6927c --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_dm.h @@ -0,0 +1,324 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ +#ifndef __R8192UDM_H__ +#define __R8192UDM_H__ + + +/*--------------------------Define Parameters-------------------------------*/ +#define OFDM_Table_Length 19 +#define CCK_Table_length 12 + +#define DM_DIG_THRESH_HIGH 40 +#define DM_DIG_THRESH_LOW 35 + +#define DM_FALSEALARM_THRESH_LOW 40 +#define DM_FALSEALARM_THRESH_HIGH 1000 + +#define DM_DIG_HIGH_PWR_THRESH_HIGH 75 +#define DM_DIG_HIGH_PWR_THRESH_LOW 70 + +#define BW_AUTO_SWITCH_HIGH_LOW 25 +#define BW_AUTO_SWITCH_LOW_HIGH 30 + +#define DM_check_fsync_time_interval 500 + + +#define DM_DIG_BACKOFF 12 +#define DM_DIG_MAX 0x36 +#define DM_DIG_MIN 0x1c +#define DM_DIG_MIN_Netcore 0x12 + +#define DM_DIG_BACKOFF_MAX 12 +#define DM_DIG_BACKOFF_MIN -4 + +#define RxPathSelection_SS_TH_low 30 +#define RxPathSelection_diff_TH 18 + +#define RateAdaptiveTH_High 50 +#define RateAdaptiveTH_Low_20M 30 +#define RateAdaptiveTH_Low_40M 10 +#define VeryLowRSSI 15 + +#define CTSToSelfTHVal 35 + +#define WAIotTHVal 25 + +#define E_FOR_TX_POWER_TRACK 300 +#define TX_POWER_NEAR_FIELD_THRESH_HIGH 68 +#define TX_POWER_NEAR_FIELD_THRESH_LOW 62 +#define TX_POWER_ATHEROAP_THRESH_HIGH 78 +#define TX_POWER_ATHEROAP_THRESH_LOW 72 + +#define Current_Tx_Rate_Reg 0x1e0 +#define Initial_Tx_Rate_Reg 0x1e1 +#define Tx_Retry_Count_Reg 0x1ac +#define RegC38_TH 20 + +#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 +#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 + +#define TxHighPwrLevel_Normal 0 +#define TxHighPwrLevel_Level1 1 +#define TxHighPwrLevel_Level2 2 + +#define DM_Type_ByFW 0 +#define DM_Type_ByDriver 1 + +/*--------------------------Define Parameters-------------------------------*/ + + +/*------------------------------Define structure----------------------------*/ +struct dig_t { + u8 dig_enable_flag; + u8 dig_algorithm; + u8 Dig_TwoPort_Algorithm; + u8 Dig_Ext_Port_Stage; + u8 dbg_mode; + u8 dig_algorithm_switch; + + long rssi_low_thresh; + long rssi_high_thresh; + + u32 FALowThresh; + u32 FAHighThresh; + + long rssi_high_power_lowthresh; + long rssi_high_power_highthresh; + + u8 dig_state; + u8 dig_highpwr_state; + u8 CurSTAConnectState; + u8 PreSTAConnectState; + u8 CurAPConnectState; + u8 PreAPConnectState; + + u8 curpd_thstate; + u8 prepd_thstate; + u8 curcs_ratio_state; + u8 precs_ratio_state; + + u32 pre_ig_value; + u32 cur_ig_value; + + u8 Backoff_Enable_Flag; + u8 backoff_val; + char BackoffVal_range_max; + char BackoffVal_range_min; + u8 rx_gain_range_max; + u8 rx_gain_range_min; + bool initialgain_lowerbound_state; + + long rssi_val; +}; + +enum dm_dig_sta { + DM_STA_DIG_OFF = 0, + DM_STA_DIG_ON, + DM_STA_DIG_MAX +}; + + +enum dm_ratr_sta { + DM_RATR_STA_HIGH = 0, + DM_RATR_STA_MIDDLE = 1, + DM_RATR_STA_LOW = 2, + DM_RATR_STA_MAX +}; + +enum dm_dig_op_sta { + DIG_TYPE_THRESH_HIGH = 0, + DIG_TYPE_THRESH_LOW = 1, + DIG_TYPE_THRESH_HIGHPWR_HIGH = 2, + DIG_TYPE_THRESH_HIGHPWR_LOW = 3, + DIG_TYPE_DBG_MODE = 4, + DIG_TYPE_RSSI = 5, + DIG_TYPE_ALGORITHM = 6, + DIG_TYPE_BACKOFF = 7, + DIG_TYPE_PWDB_FACTOR = 8, + DIG_TYPE_RX_GAIN_MIN = 9, + DIG_TYPE_RX_GAIN_MAX = 10, + DIG_TYPE_ENABLE = 20, + DIG_TYPE_DISABLE = 30, + DIG_OP_TYPE_MAX +}; + +enum dm_dig_alg { + DIG_ALGO_BY_FALSE_ALARM = 0, + DIG_ALGO_BY_RSSI = 1, + DIG_ALGO_BEFORE_CONNECT_BY_RSSI_AND_ALARM = 2, + DIG_ALGO_BY_TOW_PORT = 3, + DIG_ALGO_MAX +}; + +enum dm_dig_two_port_alg { + DIG_TWO_PORT_ALGO_RSSI = 0, + DIG_TWO_PORT_ALGO_FALSE_ALARM = 1, +}; + + +enum dm_dig_ext_port_alg { + DIG_EXT_PORT_STAGE_0 = 0, + DIG_EXT_PORT_STAGE_1 = 1, + DIG_EXT_PORT_STAGE_2 = 2, + DIG_EXT_PORT_STAGE_3 = 3, + DIG_EXT_PORT_STAGE_MAX = 4, +}; + +enum dm_dig_dbg { + DIG_DBG_OFF = 0, + DIG_DBG_ON = 1, + DIG_DBG_MAX +}; + +enum dm_dig_connect { + DIG_STA_DISCONNECT = 0, + DIG_STA_CONNECT = 1, + DIG_STA_BEFORE_CONNECT = 2, + DIG_AP_DISCONNECT = 3, + DIG_AP_CONNECT = 4, + DIG_AP_ADD_STATION = 5, + DIG_CONNECT_MAX +}; + +enum dm_dig_pd_th { + DIG_PD_AT_LOW_POWER = 0, + DIG_PD_AT_NORMAL_POWER = 1, + DIG_PD_AT_HIGH_POWER = 2, + DIG_PD_MAX +}; + +enum dm_dig_cs_ratio { + DIG_CS_RATIO_LOWER = 0, + DIG_CS_RATIO_HIGHER = 1, + DIG_CS_MAX +}; + +struct drx_path_sel { + u8 Enable; + u8 DbgMode; + u8 cck_method; + u8 cck_Rx_path; + + u8 SS_TH_low; + u8 diff_TH; + u8 disabledRF; + u8 reserved; + + u8 rf_rssi[4]; + u8 rf_enable_rssi_th[4]; + long cck_pwdb_sta[4]; +}; + +enum dm_cck_rx_path_method { + CCK_Rx_Version_1 = 0, + CCK_Rx_Version_2 = 1, + CCK_Rx_Version_MAX +}; + + +enum dm_dbg { + DM_DBG_OFF = 0, + DM_DBG_ON = 1, + DM_DBG_MAX +}; + +struct dcmd_txcmd { + u32 Op; + u32 Length; + u32 Value; +}; +/*------------------------------Define structure----------------------------*/ + + +/*------------------------Export global variable----------------------------*/ +extern struct dig_t dm_digtable; +extern u8 dm_shadow[16][256]; +extern struct drx_path_sel DM_RxPathSelTable; + +extern u8 test_flag; +/*------------------------Export global variable----------------------------*/ + + +/*------------------------Export Marco Definition---------------------------*/ +#define DM_APInitGainChangeNotify(Event) \ + { \ + dm_digtable.CurAPConnectState = Event; \ + } +/*------------------------Export Marco Definition---------------------------*/ + + +/*--------------------------Exported Function prototype---------------------*/ +/*--------------------------Exported Function prototype---------------------*/ +extern void init_hal_dm(struct net_device *dev); +extern void deinit_hal_dm(struct net_device *dev); + +extern void hal_dm_watchdog(struct net_device *dev); + + +extern void init_rate_adaptive(struct net_device *dev); +extern void dm_txpower_trackingcallback(void *data); + +extern void dm_cck_txpower_adjust(struct net_device *dev, bool binch14); + +extern void dm_restore_dynamic_mechanism_state(struct net_device *dev); +extern void dm_backup_dynamic_mechanism_state(struct net_device *dev); +extern void dm_change_dynamic_initgain_thresh(struct net_device *dev, + u32 dm_type, + u32 dm_value); +extern void DM_ChangeFsyncSetting(struct net_device *dev, + s32 DM_Type, + s32 DM_Value); +extern void dm_force_tx_fw_info(struct net_device *dev, + u32 force_type, + u32 force_value); +extern void dm_init_edca_turbo(struct net_device *dev); +extern void dm_rf_operation_test_callback(unsigned long data); +extern void dm_rf_pathcheck_workitemcallback(void *data); +extern void dm_fsync_timer_callback(unsigned long data); +extern void dm_check_fsync(struct net_device *dev); +extern void dm_shadow_init(struct net_device *dev); +extern void dm_initialize_txpower_tracking(struct net_device *dev); +extern void dm_CheckRfCtrlGPIO(void *data); +extern void dm_InitRateAdaptiveMask(struct net_device *dev); +extern void init_hal_dm(struct net_device *dev); +extern void deinit_hal_dm(struct net_device *dev); +extern void hal_dm_watchdog(struct net_device *dev); +extern void init_rate_adaptive(struct net_device *dev); +extern void dm_txpower_trackingcallback(void *data); +extern void dm_restore_dynamic_mechanism_state(struct net_device *dev); +extern void dm_backup_dynamic_mechanism_state(struct net_device *dev); +extern void dm_change_dynamic_initgain_thresh(struct net_device *dev, + u32 dm_type, + u32 dm_value); +extern void DM_ChangeFsyncSetting(struct net_device *dev, + s32 DM_Type, + s32 DM_Value); +extern void dm_force_tx_fw_info(struct net_device *dev, + u32 force_type, + u32 force_value); +extern void dm_init_edca_turbo(struct net_device *dev); +extern void dm_rf_operation_test_callback(unsigned long data); +extern void dm_rf_pathcheck_workitemcallback(void *data); +extern void dm_fsync_timer_callback(unsigned long data); +extern void dm_check_fsync(struct net_device *dev); +extern void dm_shadow_init(struct net_device *dev); +extern void dm_initialize_txpower_tracking(struct net_device *dev); +extern void dm_CheckRfCtrlGPIO(void *data); + +#endif /*__R8192UDM_H__ */ diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_eeprom.c b/drivers/staging/rtl8192e/rtl8192e/rtl_eeprom.c new file mode 100644 index 000000000000..c1ccff4a8321 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_eeprom.c @@ -0,0 +1,139 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * Based on the r8180 driver, which is: + * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ +#include "rtl_core.h" +#include "rtl_eeprom.h" + +static void eprom_cs(struct net_device *dev, short bit) +{ + if (bit) + write_nic_byte(dev, EPROM_CMD, + (1 << EPROM_CS_SHIFT) | + read_nic_byte(dev, EPROM_CMD)); + else + write_nic_byte(dev, EPROM_CMD, read_nic_byte(dev, EPROM_CMD) + & ~(1<<EPROM_CS_SHIFT)); + + udelay(EPROM_DELAY); +} + + +static void eprom_ck_cycle(struct net_device *dev) +{ + write_nic_byte(dev, EPROM_CMD, + (1<<EPROM_CK_SHIFT) | read_nic_byte(dev, EPROM_CMD)); + udelay(EPROM_DELAY); + write_nic_byte(dev, EPROM_CMD, + read_nic_byte(dev, EPROM_CMD) & ~(1<<EPROM_CK_SHIFT)); + udelay(EPROM_DELAY); +} + + +static void eprom_w(struct net_device *dev, short bit) +{ + if (bit) + write_nic_byte(dev, EPROM_CMD, (1<<EPROM_W_SHIFT) | + read_nic_byte(dev, EPROM_CMD)); + else + write_nic_byte(dev, EPROM_CMD, read_nic_byte(dev, EPROM_CMD) + & ~(1<<EPROM_W_SHIFT)); + + udelay(EPROM_DELAY); +} + + +static short eprom_r(struct net_device *dev) +{ + short bit; + + bit = (read_nic_byte(dev, EPROM_CMD) & (1<<EPROM_R_SHIFT)); + udelay(EPROM_DELAY); + + if (bit) + return 1; + return 0; +} + +static void eprom_send_bits_string(struct net_device *dev, short b[], int len) +{ + int i; + + for (i = 0; i < len; i++) { + eprom_w(dev, b[i]); + eprom_ck_cycle(dev); + } +} + +u32 eprom_read(struct net_device *dev, u32 addr) +{ + struct r8192_priv *priv = rtllib_priv(dev); + short read_cmd[] = {1, 1, 0}; + short addr_str[8]; + int i; + int addr_len; + u32 ret; + + ret = 0; + write_nic_byte(dev, EPROM_CMD, + (EPROM_CMD_PROGRAM << EPROM_CMD_OPERATING_MODE_SHIFT)); + udelay(EPROM_DELAY); + + if (priv->epromtype == EEPROM_93C56) { + addr_str[7] = addr & 1; + addr_str[6] = addr & (1<<1); + addr_str[5] = addr & (1<<2); + addr_str[4] = addr & (1<<3); + addr_str[3] = addr & (1<<4); + addr_str[2] = addr & (1<<5); + addr_str[1] = addr & (1<<6); + addr_str[0] = addr & (1<<7); + addr_len = 8; + } else { + addr_str[5] = addr & 1; + addr_str[4] = addr & (1<<1); + addr_str[3] = addr & (1<<2); + addr_str[2] = addr & (1<<3); + addr_str[1] = addr & (1<<4); + addr_str[0] = addr & (1<<5); + addr_len = 6; + } + eprom_cs(dev, 1); + eprom_ck_cycle(dev); + eprom_send_bits_string(dev, read_cmd, 3); + eprom_send_bits_string(dev, addr_str, addr_len); + + eprom_w(dev, 0); + + for (i = 0; i < 16; i++) { + eprom_ck_cycle(dev); + ret |= (eprom_r(dev)<<(15-i)); + } + + eprom_cs(dev, 0); + eprom_ck_cycle(dev); + + write_nic_byte(dev, EPROM_CMD, + (EPROM_CMD_NORMAL<<EPROM_CMD_OPERATING_MODE_SHIFT)); + return ret; +} diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_eeprom.h b/drivers/staging/rtl8192e/rtl8192e/rtl_eeprom.h new file mode 100644 index 000000000000..9452e1683a72 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_eeprom.h @@ -0,0 +1,29 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * Based on the r8180 driver, which is: + * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ + + +#define EPROM_DELAY 10 + +u32 eprom_read(struct net_device *dev, u32 addr); diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_ethtool.c b/drivers/staging/rtl8192e/rtl8192e/rtl_ethtool.c new file mode 100644 index 000000000000..36452fb7cef8 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_ethtool.c @@ -0,0 +1,53 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * Based on the r8180 driver, which is: + * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> + ***************************************************************************** + */ +#include <linux/netdevice.h> +#include <linux/ethtool.h> +#include <linux/delay.h> + +#include "rtl_core.h" + +static void rtl819x_ethtool_get_drvinfo(struct net_device *dev, + struct ethtool_drvinfo *info) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + strcpy(info->driver, DRV_NAME); + strcpy(info->version, DRV_VERSION); + strcpy(info->bus_info, pci_name(priv->pdev)); +} + +static u32 rtl819x_ethtool_get_link(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + return ((priv->rtllib->state == RTLLIB_LINKED) || + (priv->rtllib->state == RTLLIB_LINKED_SCANNING)); +} + +const struct ethtool_ops rtl819x_ethtool_ops = { + .get_drvinfo = rtl819x_ethtool_get_drvinfo, + .get_link = rtl819x_ethtool_get_link, +}; diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_pci.c b/drivers/staging/rtl8192e/rtl8192e/rtl_pci.c new file mode 100644 index 000000000000..ddadcc3e4e7c --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_pci.c @@ -0,0 +1,97 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * Based on the r8180 driver, which is: + * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> + *****************************************************************************/ +#include "rtl_pci.h" +#include "rtl_core.h" + +static void rtl8192_parse_pci_configuration(struct pci_dev *pdev, + struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + + u8 tmp; + int pos; + u8 LinkCtrlReg; + + pos = pci_find_capability(priv->pdev, PCI_CAP_ID_EXP); + pci_read_config_byte(priv->pdev, pos + PCI_EXP_LNKCTL, &LinkCtrlReg); + priv->NdisAdapter.LinkCtrlReg = LinkCtrlReg; + + RT_TRACE(COMP_INIT, "Link Control Register =%x\n", + priv->NdisAdapter.LinkCtrlReg); + + pci_read_config_byte(pdev, 0x98, &tmp); + tmp |= BIT4; + pci_write_config_byte(pdev, 0x98, tmp); + + tmp = 0x17; + pci_write_config_byte(pdev, 0x70f, tmp); +} + +bool rtl8192_pci_findadapter(struct pci_dev *pdev, struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + u16 VenderID; + u16 DeviceID; + u8 RevisionID; + u16 IrqLine; + + VenderID = pdev->vendor; + DeviceID = pdev->device; + RevisionID = pdev->revision; + pci_read_config_word(pdev, 0x3C, &IrqLine); + + priv->card_8192 = priv->ops->nic_type; + + if (DeviceID == 0x8172) { + switch (RevisionID) { + case HAL_HW_PCI_REVISION_ID_8192PCIE: + printk(KERN_INFO "Adapter(8192 PCI-E) is found - " + "DeviceID=%x\n", DeviceID); + priv->card_8192 = NIC_8192E; + break; + case HAL_HW_PCI_REVISION_ID_8192SE: + printk(KERN_INFO "Adapter(8192SE) is found - " + "DeviceID=%x\n", DeviceID); + priv->card_8192 = NIC_8192SE; + break; + default: + printk(KERN_INFO "UNKNOWN nic type(%4x:%4x)\n", + pdev->vendor, pdev->device); + priv->card_8192 = NIC_UNKNOWN; + return false; + } + } + + if (priv->ops->nic_type != priv->card_8192) { + printk(KERN_INFO "Detect info(%x) and hardware info(%x) not match!\n", + priv->ops->nic_type, priv->card_8192); + printk(KERN_INFO "Please select proper driver before install!!!!\n"); + return false; + } + + rtl8192_parse_pci_configuration(pdev, dev); + + return true; +} diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_pci.h b/drivers/staging/rtl8192e/rtl8192e/rtl_pci.h new file mode 100644 index 000000000000..28c7da677a80 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_pci.h @@ -0,0 +1,103 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * Based on the r8180 driver, which is: + * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> + ******************************************************************************/ +#ifndef _RTL_PCI_H +#define _RTL_PCI_H + +#include <linux/types.h> +#include <linux/pci.h> + +static inline void NdisRawWritePortUlong(u32 port, u32 val) +{ + outl(val, port); +} + +static inline void NdisRawWritePortUchar(u32 port, u8 val) +{ + outb(val, port); +} + +static inline void NdisRawReadPortUchar(u32 port, u8 *pval) +{ + *pval = inb(port); +} + +static inline void NdisRawReadPortUshort(u32 port, u16 *pval) +{ + *pval = inw(port); +} + +static inline void NdisRawReadPortUlong(u32 port, u32 *pval) +{ + *pval = inl(port); +} + +struct mp_adapter { + u8 LinkCtrlReg; + + u8 BusNumber; + u8 DevNumber; + u8 FuncNumber; + + u8 PciBridgeBusNum; + u8 PciBridgeDevNum; + u8 PciBridgeFuncNum; + u8 PciBridgeVendor; + u16 PciBridgeVendorId; + u16 PciBridgeDeviceId; + u8 PciBridgePCIeHdrOffset; + u8 PciBridgeLinkCtrlReg; +}; + +struct rt_pci_capab_header { + unsigned char CapabilityID; + unsigned char Next; +}; + +#define PCI_MAX_BRIDGE_NUMBER 255 +#define PCI_MAX_DEVICES 32 +#define PCI_MAX_FUNCTION 8 + +#define PCI_CONF_ADDRESS 0x0CF8 +#define PCI_CONF_DATA 0x0CFC + +#define PCI_CLASS_BRIDGE_DEV 0x06 +#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04 + +#define U1DONTCARE 0xFF +#define U2DONTCARE 0xFFFF +#define U4DONTCARE 0xFFFFFFFF + +#define INTEL_VENDOR_ID 0x8086 +#define SIS_VENDOR_ID 0x1039 +#define ATI_VENDOR_ID 0x1002 +#define ATI_DEVICE_ID 0x7914 +#define AMD_VENDOR_ID 0x1022 + +#define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10 + +struct net_device; +bool rtl8192_pci_findadapter(struct pci_dev *pdev, struct net_device *dev); + +#endif diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_pm.c b/drivers/staging/rtl8192e/rtl8192e/rtl_pm.c new file mode 100644 index 000000000000..8e1a5d55dce8 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_pm.c @@ -0,0 +1,134 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ + +#include "rtl_core.h" +#include "r8192E_hw.h" +#include "r8190P_rtl8256.h" +#include "rtl_pm.h" + +int rtl8192E_save_state(struct pci_dev *dev, pm_message_t state) +{ + printk(KERN_NOTICE "r8192E save state call (state %u).\n", state.event); + return -EAGAIN; +} + + +int rtl8192E_suspend(struct pci_dev *pdev, pm_message_t state) +{ + struct net_device *dev = pci_get_drvdata(pdev); + struct r8192_priv *priv = rtllib_priv(dev); + u32 ulRegRead; + + printk(KERN_INFO "============> r8192E suspend call.\n"); + del_timer_sync(&priv->gpio_polling_timer); + cancel_delayed_work(&priv->gpio_change_rf_wq); + priv->polling_timer_on = 0; + + if (!netif_running(dev)) { + printk(KERN_INFO "RTL819XE:UI is open out of suspend " + "function\n"); + goto out_pci_suspend; + } + + if (dev->netdev_ops->ndo_stop) + dev->netdev_ops->ndo_stop(dev); + netif_device_detach(dev); + + if (!priv->rtllib->bSupportRemoteWakeUp) { + MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_INIT, true); + ulRegRead = read_nic_dword(dev, CPU_GEN); + ulRegRead |= CPU_GEN_SYSTEM_RESET; + write_nic_dword(dev, CPU_GEN, ulRegRead); + } else { + write_nic_dword(dev, WFCRC0, 0xffffffff); + write_nic_dword(dev, WFCRC1, 0xffffffff); + write_nic_dword(dev, WFCRC2, 0xffffffff); + write_nic_byte(dev, PMR, 0x5); + write_nic_byte(dev, MacBlkCtrl, 0xa); + } +out_pci_suspend: + printk("r8192E support WOL call??????????????????????\n"); + if (priv->rtllib->bSupportRemoteWakeUp) + RT_TRACE(COMP_POWER, "r8192E support WOL call!!!!!!!" + "!!!!!!!!!!!.\n"); + pci_save_state(pdev); + pci_disable_device(pdev); + pci_enable_wake(pdev, pci_choose_state(pdev, state), + priv->rtllib->bSupportRemoteWakeUp ? 1 : 0); + pci_set_power_state(pdev, pci_choose_state(pdev, state)); + + mdelay(20); + + return 0; +} + +int rtl8192E_resume(struct pci_dev *pdev) +{ + struct net_device *dev = pci_get_drvdata(pdev); + struct r8192_priv *priv = rtllib_priv(dev); + int err; + u32 val; + + printk(KERN_INFO "================>r8192E resume call.\n"); + + pci_set_power_state(pdev, PCI_D0); + + err = pci_enable_device(pdev); + if (err) { + printk(KERN_ERR "%s: pci_enable_device failed on resume\n", + dev->name); + return err; + } + pci_restore_state(pdev); + + pci_read_config_dword(pdev, 0x40, &val); + if ((val & 0x0000ff00) != 0) + pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); + + pci_enable_wake(pdev, PCI_D0, 0); + + if (priv->polling_timer_on == 0) + check_rfctrl_gpio_timer((unsigned long)dev); + + if (!netif_running(dev)) { + printk(KERN_INFO "RTL819XE:UI is open out of resume " + "function\n"); + goto out; + } + + netif_device_attach(dev); + if (dev->netdev_ops->ndo_open) + dev->netdev_ops->ndo_open(dev); + + if (!priv->rtllib->bSupportRemoteWakeUp) + MgntActSet_RF_State(dev, eRfOn, RF_CHANGE_BY_INIT, true); + +out: + RT_TRACE(COMP_POWER, "<================r8192E resume call.\n"); + return 0; +} + + +int rtl8192E_enable_wake(struct pci_dev *dev, pm_message_t state, int enable) +{ + printk(KERN_NOTICE "r8192E enable wake call (state %u, enable %d).\n", + state.event, enable); + return -EAGAIN; +} + diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_pm.h b/drivers/staging/rtl8192e/rtl8192e/rtl_pm.h new file mode 100644 index 000000000000..e5299fc3b34a --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_pm.h @@ -0,0 +1,31 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ + +#ifndef R8192E_PM_H +#define R8192E_PM_H + +#include <linux/types.h> +#include <linux/pci.h> + +int rtl8192E_save_state(struct pci_dev *dev, pm_message_t state); +int rtl8192E_suspend(struct pci_dev *dev, pm_message_t state); +int rtl8192E_resume(struct pci_dev *dev); +int rtl8192E_enable_wake(struct pci_dev *dev, pm_message_t state, int enable); + +#endif diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_ps.c b/drivers/staging/rtl8192e/rtl8192e/rtl_ps.c new file mode 100644 index 000000000000..c9a7c563b682 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_ps.c @@ -0,0 +1,310 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * Based on the r8180 driver, which is: + * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> + *****************************************************************************/ +#include "rtl_ps.h" +#include "rtl_core.h" +#include "r8192E_phy.h" +#include "r8192E_phyreg.h" +#include "r8190P_rtl8256.h" /* RTL8225 Radio frontend */ +#include "r8192E_cmdpkt.h" + +static void rtl8192_hw_sleep_down(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + unsigned long flags = 0; + spin_lock_irqsave(&priv->rf_ps_lock, flags); + if (priv->RFChangeInProgress) { + spin_unlock_irqrestore(&priv->rf_ps_lock, flags); + RT_TRACE(COMP_DBG, "rtl8192_hw_sleep_down(): RF Change in " + "progress!\n"); + return; + } + spin_unlock_irqrestore(&priv->rf_ps_lock, flags); + RT_TRACE(COMP_DBG, "%s()============>come to sleep down\n", __func__); + + MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS, false); +} + +void rtl8192_hw_sleep_wq(void *data) +{ + struct rtllib_device *ieee = container_of_dwork_rsl(data, + struct rtllib_device, hw_sleep_wq); + struct net_device *dev = ieee->dev; + rtl8192_hw_sleep_down(dev); +} + +void rtl8192_hw_wakeup(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + unsigned long flags = 0; + spin_lock_irqsave(&priv->rf_ps_lock, flags); + if (priv->RFChangeInProgress) { + spin_unlock_irqrestore(&priv->rf_ps_lock, flags); + RT_TRACE(COMP_DBG, "rtl8192_hw_wakeup(): RF Change in " + "progress!\n"); + queue_delayed_work_rsl(priv->rtllib->wq, + &priv->rtllib->hw_wakeup_wq, MSECS(10)); + return; + } + spin_unlock_irqrestore(&priv->rf_ps_lock, flags); + RT_TRACE(COMP_PS, "%s()============>come to wake up\n", __func__); + MgntActSet_RF_State(dev, eRfOn, RF_CHANGE_BY_PS, false); +} + +void rtl8192_hw_wakeup_wq(void *data) +{ + struct rtllib_device *ieee = container_of_dwork_rsl(data, + struct rtllib_device, hw_wakeup_wq); + struct net_device *dev = ieee->dev; + rtl8192_hw_wakeup(dev); + +} + +#define MIN_SLEEP_TIME 50 +#define MAX_SLEEP_TIME 10000 +void rtl8192_hw_to_sleep(struct net_device *dev, u64 time) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + u32 tmp; + unsigned long flags; + + spin_lock_irqsave(&priv->ps_lock, flags); + + time -= MSECS(8+16+7); + + if ((time - jiffies) <= MSECS(MIN_SLEEP_TIME)) { + spin_unlock_irqrestore(&priv->ps_lock, flags); + printk(KERN_INFO "too short to sleep::%lld < %ld\n", + time - jiffies, MSECS(MIN_SLEEP_TIME)); + return; + } + + if ((time - jiffies) > MSECS(MAX_SLEEP_TIME)) { + printk(KERN_INFO "========>too long to sleep:%lld > %ld\n", + time - jiffies, MSECS(MAX_SLEEP_TIME)); + spin_unlock_irqrestore(&priv->ps_lock, flags); + return; + } + tmp = time - jiffies; + queue_delayed_work_rsl(priv->rtllib->wq, + &priv->rtllib->hw_wakeup_wq, tmp); + queue_delayed_work_rsl(priv->rtllib->wq, + (void *)&priv->rtllib->hw_sleep_wq, 0); + spin_unlock_irqrestore(&priv->ps_lock, flags); +} + +static void InactivePsWorkItemCallback(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *) + &(priv->rtllib->PowerSaveControl); + + RT_TRACE(COMP_PS, "InactivePsWorkItemCallback() --------->\n"); + pPSC->bSwRfProcessing = true; + + RT_TRACE(COMP_PS, "InactivePsWorkItemCallback(): Set RF to %s.\n", + pPSC->eInactivePowerState == eRfOff ? "OFF" : "ON"); + MgntActSet_RF_State(dev, pPSC->eInactivePowerState, RF_CHANGE_BY_IPS, + false); + + pPSC->bSwRfProcessing = false; + RT_TRACE(COMP_PS, "InactivePsWorkItemCallback() <---------\n"); +} + +void IPSEnter(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *) + &(priv->rtllib->PowerSaveControl); + enum rt_rf_power_state rtState; + + if (pPSC->bInactivePs) { + rtState = priv->rtllib->eRFPowerState; + if (rtState == eRfOn && !pPSC->bSwRfProcessing && + (priv->rtllib->state != RTLLIB_LINKED) && + (priv->rtllib->iw_mode != IW_MODE_MASTER)) { + RT_TRACE(COMP_PS, "IPSEnter(): Turn off RF.\n"); + pPSC->eInactivePowerState = eRfOff; + priv->isRFOff = true; + priv->bInPowerSaveMode = true; + InactivePsWorkItemCallback(dev); + } + } +} + +void IPSLeave(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *) + &(priv->rtllib->PowerSaveControl); + enum rt_rf_power_state rtState; + + if (pPSC->bInactivePs) { + rtState = priv->rtllib->eRFPowerState; + if (rtState != eRfOn && !pPSC->bSwRfProcessing && + priv->rtllib->RfOffReason <= RF_CHANGE_BY_IPS) { + RT_TRACE(COMP_PS, "IPSLeave(): Turn on RF.\n"); + pPSC->eInactivePowerState = eRfOn; + priv->bInPowerSaveMode = false; + InactivePsWorkItemCallback(dev); + } + } +} + +void IPSLeave_wq(void *data) +{ + struct rtllib_device *ieee = container_of_work_rsl(data, + struct rtllib_device, ips_leave_wq); + struct net_device *dev = ieee->dev; + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + down(&priv->rtllib->ips_sem); + IPSLeave(dev); + up(&priv->rtllib->ips_sem); +} + +void rtllib_ips_leave_wq(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + enum rt_rf_power_state rtState; + rtState = priv->rtllib->eRFPowerState; + + if (priv->rtllib->PowerSaveControl.bInactivePs) { + if (rtState == eRfOff) { + if (priv->rtllib->RfOffReason > RF_CHANGE_BY_IPS) { + RT_TRACE(COMP_ERR, "%s(): RF is OFF.\n", + __func__); + return; + } else { + printk(KERN_INFO "=========>%s(): IPSLeave\n", + __func__); + queue_work_rsl(priv->rtllib->wq, + &priv->rtllib->ips_leave_wq); + } + } + } +} + +void rtllib_ips_leave(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + down(&priv->rtllib->ips_sem); + IPSLeave(dev); + up(&priv->rtllib->ips_sem); +} + +static bool MgntActSet_802_11_PowerSaveMode(struct net_device *dev, + u8 rtPsMode) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + if (priv->rtllib->iw_mode == IW_MODE_ADHOC) + return false; + + RT_TRACE(COMP_LPS, "%s(): set ieee->ps = %x\n", __func__, rtPsMode); + if (!priv->ps_force) + priv->rtllib->ps = rtPsMode; + if (priv->rtllib->sta_sleep != LPS_IS_WAKE && + rtPsMode == RTLLIB_PS_DISABLED) { + unsigned long flags; + + rtl8192_hw_wakeup(dev); + priv->rtllib->sta_sleep = LPS_IS_WAKE; + + spin_lock_irqsave(&(priv->rtllib->mgmt_tx_lock), flags); + RT_TRACE(COMP_DBG, "LPS leave: notify AP we are awaked" + " ++++++++++ SendNullFunctionData\n"); + rtllib_sta_ps_send_null_frame(priv->rtllib, 0); + spin_unlock_irqrestore(&(priv->rtllib->mgmt_tx_lock), flags); + } + + return true; +} + +void LeisurePSEnter(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *) + &(priv->rtllib->PowerSaveControl); + + RT_TRACE(COMP_PS, "LeisurePSEnter()...\n"); + RT_TRACE(COMP_PS, "pPSC->bLeisurePs = %d, ieee->ps = %d,pPSC->LpsIdle" + "Count is %d,RT_CHECK_FOR_HANG_PERIOD is %d\n", + pPSC->bLeisurePs, priv->rtllib->ps, pPSC->LpsIdleCount, + RT_CHECK_FOR_HANG_PERIOD); + + if (!((priv->rtllib->iw_mode == IW_MODE_INFRA) && + (priv->rtllib->state == RTLLIB_LINKED)) + || (priv->rtllib->iw_mode == IW_MODE_ADHOC) || + (priv->rtllib->iw_mode == IW_MODE_MASTER)) + return; + + if (pPSC->bLeisurePs) { + if (pPSC->LpsIdleCount >= RT_CHECK_FOR_HANG_PERIOD) { + + if (priv->rtllib->ps == RTLLIB_PS_DISABLED) { + + RT_TRACE(COMP_LPS, "LeisurePSEnter(): Enter " + "802.11 power save mode...\n"); + + if (!pPSC->bFwCtrlLPS) { + if (priv->rtllib->SetFwCmdHandler) + priv->rtllib->SetFwCmdHandler( + dev, FW_CMD_LPS_ENTER); + } + MgntActSet_802_11_PowerSaveMode(dev, + RTLLIB_PS_MBCAST | + RTLLIB_PS_UNICAST); + } + } else + pPSC->LpsIdleCount++; + } +} + +void LeisurePSLeave(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *) + &(priv->rtllib->PowerSaveControl); + + + RT_TRACE(COMP_PS, "LeisurePSLeave()...\n"); + RT_TRACE(COMP_PS, "pPSC->bLeisurePs = %d, ieee->ps = %d\n", + pPSC->bLeisurePs, priv->rtllib->ps); + + if (pPSC->bLeisurePs) { + if (priv->rtllib->ps != RTLLIB_PS_DISABLED) { + RT_TRACE(COMP_LPS, "LeisurePSLeave(): Busy Traffic , " + "Leave 802.11 power save..\n"); + MgntActSet_802_11_PowerSaveMode(dev, + RTLLIB_PS_DISABLED); + + if (!pPSC->bFwCtrlLPS) { + if (priv->rtllib->SetFwCmdHandler) + priv->rtllib->SetFwCmdHandler(dev, + FW_CMD_LPS_LEAVE); + } + } + } +} diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_ps.h b/drivers/staging/rtl8192e/rtl8192e/rtl_ps.h new file mode 100644 index 000000000000..df79d6c4ca03 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_ps.h @@ -0,0 +1,47 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * Based on the r8180 driver, which is: + * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> + ******************************************************************************/ +#ifndef _RTL_PS_H +#define _RTL_PS_H + +#include <linux/types.h> + +struct net_device; + +#define RT_CHECK_FOR_HANG_PERIOD 2 +#define INIT_DEFAULT_CHAN 1 + +void rtl8192_hw_wakeup(struct net_device *dev); +void rtl8192_hw_to_sleep(struct net_device *dev, u64 time); +void rtllib_ips_leave_wq(struct net_device *dev); +void rtllib_ips_leave(struct net_device *dev); +void IPSLeave_wq(void *data); + +void IPSEnter(struct net_device *dev); +void IPSLeave(struct net_device *dev); + +void LeisurePSEnter(struct net_device *dev); +void LeisurePSLeave(struct net_device *dev); + +#endif diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_wx.c b/drivers/staging/rtl8192e/rtl8192e/rtl_wx.c new file mode 100644 index 000000000000..44fffe2f3d07 --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_wx.c @@ -0,0 +1,1332 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ + +#include <linux/string.h> +#include "rtl_core.h" + +#define RATE_COUNT 12 +static u32 rtl8192_rates[] = { + 1000000, 2000000, 5500000, 11000000, 6000000, 9000000, 12000000, + 18000000, 24000000, 36000000, 48000000, 54000000 +}; + +#ifndef ENETDOWN +#define ENETDOWN 1 +#endif + +static int r8192_wx_get_freq(struct net_device *dev, + struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + return rtllib_wx_get_freq(priv->rtllib, a, wrqu, b); +} + + +static int r8192_wx_get_mode(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + return rtllib_wx_get_mode(priv->rtllib, a, wrqu, b); +} + +static int r8192_wx_get_rate(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + return rtllib_wx_get_rate(priv->rtllib, info, wrqu, extra); +} + + + +static int r8192_wx_set_rate(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret; + struct r8192_priv *priv = rtllib_priv(dev); + + if (priv->bHwRadioOff == true) + return 0; + + down(&priv->wx_sem); + + ret = rtllib_wx_set_rate(priv->rtllib, info, wrqu, extra); + + up(&priv->wx_sem); + + return ret; +} + + +static int r8192_wx_set_rts(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret; + struct r8192_priv *priv = rtllib_priv(dev); + + if (priv->bHwRadioOff == true) + return 0; + + down(&priv->wx_sem); + + ret = rtllib_wx_set_rts(priv->rtllib, info, wrqu, extra); + + up(&priv->wx_sem); + + return ret; +} + +static int r8192_wx_get_rts(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + return rtllib_wx_get_rts(priv->rtllib, info, wrqu, extra); +} + +static int r8192_wx_set_power(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret; + struct r8192_priv *priv = rtllib_priv(dev); + + if (priv->bHwRadioOff == true) { + RT_TRACE(COMP_ERR, "%s():Hw is Radio Off, we can't set " + "Power,return\n", __func__); + return 0; + } + down(&priv->wx_sem); + + ret = rtllib_wx_set_power(priv->rtllib, info, wrqu, extra); + + up(&priv->wx_sem); + + return ret; +} + +static int r8192_wx_get_power(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + return rtllib_wx_get_power(priv->rtllib, info, wrqu, extra); +} + +static int r8192_wx_set_rawtx(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + int ret; + + if (priv->bHwRadioOff == true) + return 0; + + down(&priv->wx_sem); + + ret = rtllib_wx_set_rawtx(priv->rtllib, info, wrqu, extra); + + up(&priv->wx_sem); + + return ret; + +} + +static int r8192_wx_force_reset(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + down(&priv->wx_sem); + + RT_TRACE(COMP_DBG, "%s(): force reset ! extra is %d\n", + __func__, *extra); + priv->force_reset = *extra; + up(&priv->wx_sem); + return 0; + +} + +static int r8192_wx_force_mic_error(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + + down(&priv->wx_sem); + + RT_TRACE(COMP_DBG, "%s(): force mic error !\n", __func__); + ieee->force_mic_error = true; + up(&priv->wx_sem); + return 0; + +} + +#define MAX_ADHOC_PEER_NUM 64 +struct adhoc_peer_entry { + unsigned char MacAddr[ETH_ALEN]; + unsigned char WirelessMode; + unsigned char bCurTxBW40MHz; +}; +struct adhoc_peers_info { + struct adhoc_peer_entry Entry[MAX_ADHOC_PEER_NUM]; + unsigned char num; +}; + +static int r8192_wx_get_adhoc_peers(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + return 0; +} + + +static int r8191se_wx_get_firm_version(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *wrqu, char *extra) +{ + return 0; +} + +static int r8192_wx_adapter_power_status(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *) + (&(priv->rtllib->PowerSaveControl)); + struct rtllib_device *ieee = priv->rtllib; + + down(&priv->wx_sem); + + RT_TRACE(COMP_POWER, "%s(): %s\n", __func__, (*extra == 6) ? + "DC power" : "AC power"); + if (*extra || priv->force_lps) { + priv->ps_force = false; + pPSC->bLeisurePs = true; + } else { + if (priv->rtllib->state == RTLLIB_LINKED) + LeisurePSLeave(dev); + + priv->ps_force = true; + pPSC->bLeisurePs = false; + ieee->ps = *extra; + } + + up(&priv->wx_sem); + + return 0; +} + +static int r8192se_wx_set_radio(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + down(&priv->wx_sem); + + printk(KERN_INFO "%s(): set radio ! extra is %d\n", __func__, *extra); + if ((*extra != 0) && (*extra != 1)) { + RT_TRACE(COMP_ERR, "%s(): set radio an err value,must 0(radio " + "off) or 1(radio on)\n", __func__); + up(&priv->wx_sem); + return -1; + } + priv->sw_radio_on = *extra; + up(&priv->wx_sem); + return 0; + +} + +static int r8192se_wx_set_lps_awake_interval(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *) + (&(priv->rtllib->PowerSaveControl)); + + down(&priv->wx_sem); + + printk(KERN_INFO "%s(): set lps awake interval ! extra is %d\n", + __func__, *extra); + + pPSC->RegMaxLPSAwakeIntvl = *extra; + up(&priv->wx_sem); + return 0; +} + +static int r8192se_wx_set_force_lps(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + down(&priv->wx_sem); + + printk(KERN_INFO "%s(): force LPS ! extra is %d (1 is open 0 is " + "close)\n", __func__, *extra); + priv->force_lps = *extra; + up(&priv->wx_sem); + return 0; + +} + +static int r8192_wx_set_debugflag(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u8 c = *extra; + + if (priv->bHwRadioOff == true) + return 0; + + printk(KERN_INFO "=====>%s(), *extra:%x, debugflag:%x\n", __func__, + *extra, rt_global_debug_component); + if (c > 0) + rt_global_debug_component |= (1<<c); + else + rt_global_debug_component &= BIT31; + return 0; +} + +static int r8192_wx_set_mode(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = netdev_priv_rsl(dev); + + enum rt_rf_power_state rtState; + int ret; + + if (priv->bHwRadioOff == true) + return 0; + rtState = priv->rtllib->eRFPowerState; + down(&priv->wx_sem); + if (wrqu->mode == IW_MODE_ADHOC || wrqu->mode == IW_MODE_MONITOR || + ieee->bNetPromiscuousMode) { + if (priv->rtllib->PowerSaveControl.bInactivePs) { + if (rtState == eRfOff) { + if (priv->rtllib->RfOffReason > + RF_CHANGE_BY_IPS) { + RT_TRACE(COMP_ERR, "%s(): RF is OFF.\n", + __func__); + up(&priv->wx_sem); + return -1; + } else { + printk(KERN_INFO "=========>%s(): " + "IPSLeave\n", __func__); + down(&priv->rtllib->ips_sem); + IPSLeave(dev); + up(&priv->rtllib->ips_sem); + } + } + } + } + ret = rtllib_wx_set_mode(priv->rtllib, a, wrqu, b); + + up(&priv->wx_sem); + return ret; +} + +struct iw_range_with_scan_capa { + /* Informative stuff (to choose between different interface) */ + __u32 throughput; /* To give an idea... */ + /* In theory this value should be the maximum benchmarked + * TCP/IP throughput, because with most of these devices the + * bit rate is meaningless (overhead an co) to estimate how + * fast the connection will go and pick the fastest one. + * I suggest people to play with Netperf or any benchmark... + */ + + /* NWID (or domain id) */ + __u32 min_nwid; /* Minimal NWID we are able to set */ + __u32 max_nwid; /* Maximal NWID we are able to set */ + + /* Old Frequency (backward compat - moved lower ) */ + __u16 old_num_channels; + __u8 old_num_frequency; + + /* Scan capabilities */ + __u8 scan_capa; +}; + +static int rtl8192_wx_get_range(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct iw_range *range = (struct iw_range *)extra; + struct r8192_priv *priv = rtllib_priv(dev); + u16 val; + int i; + + wrqu->data.length = sizeof(*range); + memset(range, 0, sizeof(*range)); + + /* ~130 Mb/s real (802.11n) */ + range->throughput = 130 * 1000 * 1000; + + if (priv->rf_set_sens != NULL) { + /* signal level threshold range */ + range->sensitivity = priv->max_sens; + } + + range->max_qual.qual = 100; + range->max_qual.level = 0; + range->max_qual.noise = 0; + range->max_qual.updated = 7; /* Updated all three */ + + range->avg_qual.qual = 70; /* > 8% missed beacons is 'bad' */ + range->avg_qual.level = 0; + range->avg_qual.noise = 0; + range->avg_qual.updated = 7; /* Updated all three */ + + range->num_bitrates = min(RATE_COUNT, IW_MAX_BITRATES); + + for (i = 0; i < range->num_bitrates; i++) + range->bitrate[i] = rtl8192_rates[i]; + + range->max_rts = DEFAULT_RTS_THRESHOLD; + range->min_frag = MIN_FRAG_THRESHOLD; + range->max_frag = MAX_FRAG_THRESHOLD; + + range->min_pmp = 0; + range->max_pmp = 5000000; + range->min_pmt = 0; + range->max_pmt = 65535*1000; + range->pmp_flags = IW_POWER_PERIOD; + range->pmt_flags = IW_POWER_TIMEOUT; + range->pm_capa = IW_POWER_PERIOD | IW_POWER_TIMEOUT | IW_POWER_ALL_R; + range->we_version_compiled = WIRELESS_EXT; + range->we_version_source = 18; + + for (i = 0, val = 0; i < 14; i++) { + if ((priv->rtllib->active_channel_map)[i+1]) { + range->freq[val].i = i + 1; + range->freq[val].m = rtllib_wlan_frequencies[i] * + 100000; + range->freq[val].e = 1; + val++; + } + + if (val == IW_MAX_FREQUENCIES) + break; + } + range->num_frequency = val; + range->num_channels = val; + range->enc_capa = IW_ENC_CAPA_WPA|IW_ENC_CAPA_WPA2| + IW_ENC_CAPA_CIPHER_TKIP|IW_ENC_CAPA_CIPHER_CCMP; + range->scan_capa = IW_SCAN_CAPA_ESSID | IW_SCAN_CAPA_TYPE; + + /* Event capability (kernel + driver) */ + + return 0; +} + +static int r8192_wx_set_scan(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + enum rt_rf_power_state rtState; + int ret; + + if (!(ieee->softmac_features & IEEE_SOFTMAC_SCAN)) { + if ((ieee->state >= RTLLIB_ASSOCIATING) && + (ieee->state <= RTLLIB_ASSOCIATING_AUTHENTICATED)) + return 0; + if ((priv->rtllib->state == RTLLIB_LINKED) && + (priv->rtllib->CntAfterLink < 2)) + return 0; + } + + if (priv->bHwRadioOff == true) { + printk(KERN_INFO "================>%s(): hwradio off\n", + __func__); + return 0; + } + rtState = priv->rtllib->eRFPowerState; + if (!priv->up) + return -ENETDOWN; + if (priv->rtllib->LinkDetectInfo.bBusyTraffic == true) + return -EAGAIN; + + if (wrqu->data.flags & IW_SCAN_THIS_ESSID) { + struct iw_scan_req *req = (struct iw_scan_req *)b; + if (req->essid_len) { + ieee->current_network.ssid_len = req->essid_len; + memcpy(ieee->current_network.ssid, req->essid, + req->essid_len); + } + } + + down(&priv->wx_sem); + + priv->rtllib->FirstIe_InScan = true; + + if (priv->rtllib->state != RTLLIB_LINKED) { + if (priv->rtllib->PowerSaveControl.bInactivePs) { + if (rtState == eRfOff) { + if (priv->rtllib->RfOffReason > + RF_CHANGE_BY_IPS) { + RT_TRACE(COMP_ERR, "%s(): RF is " + "OFF.\n", __func__); + up(&priv->wx_sem); + return -1; + } else { + RT_TRACE(COMP_PS, "=========>%s(): " + "IPSLeave\n", __func__); + down(&priv->rtllib->ips_sem); + IPSLeave(dev); + up(&priv->rtllib->ips_sem); + } + } + } + rtllib_stop_scan(priv->rtllib); + if (priv->rtllib->LedControlHandler) + priv->rtllib->LedControlHandler(dev, + LED_CTL_SITE_SURVEY); + + if (priv->rtllib->eRFPowerState != eRfOff) { + priv->rtllib->actscanning = true; + + if (ieee->ScanOperationBackupHandler) + ieee->ScanOperationBackupHandler(ieee->dev, + SCAN_OPT_BACKUP); + + rtllib_start_scan_syncro(priv->rtllib, 0); + + if (ieee->ScanOperationBackupHandler) + ieee->ScanOperationBackupHandler(ieee->dev, + SCAN_OPT_RESTORE); + } + ret = 0; + } else { + priv->rtllib->actscanning = true; + ret = rtllib_wx_set_scan(priv->rtllib, a, wrqu, b); + } + + up(&priv->wx_sem); + return ret; +} + + +static int r8192_wx_get_scan(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + + int ret; + struct r8192_priv *priv = rtllib_priv(dev); + + if (!priv->up) + return -ENETDOWN; + + if (priv->bHwRadioOff == true) + return 0; + + + down(&priv->wx_sem); + + ret = rtllib_wx_get_scan(priv->rtllib, a, wrqu, b); + + up(&priv->wx_sem); + + return ret; +} + +static int r8192_wx_set_essid(struct net_device *dev, + struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + struct r8192_priv *priv = rtllib_priv(dev); + int ret; + + if ((rtllib_act_scanning(priv->rtllib, false)) && + !(priv->rtllib->softmac_features & IEEE_SOFTMAC_SCAN)) { + ; /* TODO - get rid of if */ + } + if (priv->bHwRadioOff == true) { + printk(KERN_INFO "=========>%s():hw radio off,or Rf state is " + "eRfOff, return\n", __func__); + return 0; + } + down(&priv->wx_sem); + ret = rtllib_wx_set_essid(priv->rtllib, a, wrqu, b); + + up(&priv->wx_sem); + + return ret; +} + +static int r8192_wx_get_essid(struct net_device *dev, + struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + int ret; + struct r8192_priv *priv = rtllib_priv(dev); + + down(&priv->wx_sem); + + ret = rtllib_wx_get_essid(priv->rtllib, a, wrqu, b); + + up(&priv->wx_sem); + + return ret; +} + +static int r8192_wx_set_nick(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + if (wrqu->data.length > IW_ESSID_MAX_SIZE) + return -E2BIG; + down(&priv->wx_sem); + wrqu->data.length = min((size_t) wrqu->data.length, sizeof(priv->nick)); + memset(priv->nick, 0, sizeof(priv->nick)); + memcpy(priv->nick, extra, wrqu->data.length); + up(&priv->wx_sem); + return 0; + +} + +static int r8192_wx_get_nick(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + down(&priv->wx_sem); + wrqu->data.length = strlen(priv->nick); + memcpy(extra, priv->nick, wrqu->data.length); + wrqu->data.flags = 1; /* active */ + up(&priv->wx_sem); + return 0; +} + +static int r8192_wx_set_freq(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + int ret; + struct r8192_priv *priv = rtllib_priv(dev); + + if (priv->bHwRadioOff == true) + return 0; + + down(&priv->wx_sem); + + ret = rtllib_wx_set_freq(priv->rtllib, a, wrqu, b); + + up(&priv->wx_sem); + return ret; +} + +static int r8192_wx_get_name(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + return rtllib_wx_get_name(priv->rtllib, info, wrqu, extra); +} + + +static int r8192_wx_set_frag(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + if (priv->bHwRadioOff == true) + return 0; + + if (wrqu->frag.disabled) + priv->rtllib->fts = DEFAULT_FRAG_THRESHOLD; + else { + if (wrqu->frag.value < MIN_FRAG_THRESHOLD || + wrqu->frag.value > MAX_FRAG_THRESHOLD) + return -EINVAL; + + priv->rtllib->fts = wrqu->frag.value & ~0x1; + } + + return 0; +} + + +static int r8192_wx_get_frag(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + wrqu->frag.value = priv->rtllib->fts; + wrqu->frag.fixed = 0; /* no auto select */ + wrqu->frag.disabled = (wrqu->frag.value == DEFAULT_FRAG_THRESHOLD); + + return 0; +} + + +static int r8192_wx_set_wap(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *awrq, + char *extra) +{ + int ret; + struct r8192_priv *priv = rtllib_priv(dev); + + if ((rtllib_act_scanning(priv->rtllib, false)) && + !(priv->rtllib->softmac_features & IEEE_SOFTMAC_SCAN)) { + ; /* TODO - get rid of if */ + } + + if (priv->bHwRadioOff == true) + return 0; + + down(&priv->wx_sem); + + ret = rtllib_wx_set_wap(priv->rtllib, info, awrq, extra); + + up(&priv->wx_sem); + + return ret; + +} + + +static int r8192_wx_get_wap(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + return rtllib_wx_get_wap(priv->rtllib, info, wrqu, extra); +} + + +static int r8192_wx_get_enc(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *key) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + return rtllib_wx_get_encode(priv->rtllib, info, wrqu, key); +} + +static int r8192_wx_set_enc(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *key) +{ + struct r8192_priv *priv = rtllib_priv(dev); + int ret; + + struct rtllib_device *ieee = priv->rtllib; + u32 hwkey[4] = {0, 0, 0, 0}; + u8 mask = 0xff; + u32 key_idx = 0; + u8 zero_addr[4][6] = {{0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} }; + int i; + + if ((rtllib_act_scanning(priv->rtllib, false)) && + !(priv->rtllib->softmac_features & IEEE_SOFTMAC_SCAN)) + ; /* TODO - get rid of if */ + if (priv->bHwRadioOff == true) + return 0; + + if (!priv->up) + return -ENETDOWN; + + priv->rtllib->wx_set_enc = 1; + down(&priv->rtllib->ips_sem); + IPSLeave(dev); + up(&priv->rtllib->ips_sem); + down(&priv->wx_sem); + + RT_TRACE(COMP_SEC, "Setting SW wep key"); + ret = rtllib_wx_set_encode(priv->rtllib, info, wrqu, key); + up(&priv->wx_sem); + + + if (wrqu->encoding.flags & IW_ENCODE_DISABLED) { + ieee->pairwise_key_type = ieee->group_key_type = KEY_TYPE_NA; + CamResetAllEntry(dev); + memset(priv->rtllib->swcamtable, 0, + sizeof(struct sw_cam_table) * 32); + goto end_hw_sec; + } + if (wrqu->encoding.length != 0) { + + for (i = 0; i < 4; i++) { + hwkey[i] |= key[4*i+0]&mask; + if (i == 1 && (4 * i + 1) == wrqu->encoding.length) + mask = 0x00; + if (i == 3 && (4 * i + 1) == wrqu->encoding.length) + mask = 0x00; + hwkey[i] |= (key[4 * i + 1] & mask) << 8; + hwkey[i] |= (key[4 * i + 2] & mask) << 16; + hwkey[i] |= (key[4 * i + 3] & mask) << 24; + } + + #define CONF_WEP40 0x4 + #define CONF_WEP104 0x14 + + switch (wrqu->encoding.flags & IW_ENCODE_INDEX) { + case 0: + key_idx = ieee->tx_keyidx; + break; + case 1: + key_idx = 0; + break; + case 2: + key_idx = 1; + break; + case 3: + key_idx = 2; + break; + case 4: + key_idx = 3; + break; + default: + break; + } + if (wrqu->encoding.length == 0x5) { + ieee->pairwise_key_type = KEY_TYPE_WEP40; + EnableHWSecurityConfig8192(dev); + } + + else if (wrqu->encoding.length == 0xd) { + ieee->pairwise_key_type = KEY_TYPE_WEP104; + EnableHWSecurityConfig8192(dev); + setKey(dev, key_idx, key_idx, KEY_TYPE_WEP104, + zero_addr[key_idx], 0, hwkey); + set_swcam(dev, key_idx, key_idx, KEY_TYPE_WEP104, + zero_addr[key_idx], 0, hwkey, 0); + } else { + printk(KERN_INFO "wrong type in WEP, not WEP40 and WEP104\n"); + } + } + +end_hw_sec: + priv->rtllib->wx_set_enc = 0; + return ret; +} + +static int r8192_wx_set_scan_type(struct net_device *dev, + struct iw_request_info *aa, + union iwreq_data *wrqu, char *p) +{ + struct r8192_priv *priv = rtllib_priv(dev); + int *parms = (int *)p; + int mode = parms[0]; + + if (priv->bHwRadioOff == true) + return 0; + + priv->rtllib->active_scan = mode; + + return 1; +} + + + +#define R8192_MAX_RETRY 255 +static int r8192_wx_set_retry(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + int err = 0; + + if (priv->bHwRadioOff == true) + return 0; + + down(&priv->wx_sem); + + if (wrqu->retry.flags & IW_RETRY_LIFETIME || + wrqu->retry.disabled) { + err = -EINVAL; + goto exit; + } + if (!(wrqu->retry.flags & IW_RETRY_LIMIT)) { + err = -EINVAL; + goto exit; + } + + if (wrqu->retry.value > R8192_MAX_RETRY) { + err = -EINVAL; + goto exit; + } + if (wrqu->retry.flags & IW_RETRY_MAX) { + priv->retry_rts = wrqu->retry.value; + DMESG("Setting retry for RTS/CTS data to %d", + wrqu->retry.value); + + } else { + priv->retry_data = wrqu->retry.value; + DMESG("Setting retry for non RTS/CTS data to %d", + wrqu->retry.value); + } + + + rtl8192_commit(dev); +exit: + up(&priv->wx_sem); + + return err; +} + +static int r8192_wx_get_retry(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + + wrqu->retry.disabled = 0; /* can't be disabled */ + + if ((wrqu->retry.flags & IW_RETRY_TYPE) == + IW_RETRY_LIFETIME) + return -EINVAL; + + if (wrqu->retry.flags & IW_RETRY_MAX) { + wrqu->retry.flags = IW_RETRY_LIMIT & IW_RETRY_MAX; + wrqu->retry.value = priv->retry_rts; + } else { + wrqu->retry.flags = IW_RETRY_LIMIT & IW_RETRY_MIN; + wrqu->retry.value = priv->retry_data; + } + return 0; +} + +static int r8192_wx_get_sens(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + if (priv->rf_set_sens == NULL) + return -1; /* we have not this support for this radio */ + wrqu->sens.value = priv->sens; + return 0; +} + + +static int r8192_wx_set_sens(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + struct r8192_priv *priv = rtllib_priv(dev); + + short err = 0; + + if (priv->bHwRadioOff == true) + return 0; + + down(&priv->wx_sem); + if (priv->rf_set_sens == NULL) { + err = -1; /* we have not this support for this radio */ + goto exit; + } + if (priv->rf_set_sens(dev, wrqu->sens.value) == 0) + priv->sens = wrqu->sens.value; + else + err = -EINVAL; + +exit: + up(&priv->wx_sem); + + return err; +} + +static int r8192_wx_set_enc_ext(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + + if (priv->bHwRadioOff == true) + return 0; + + down(&priv->wx_sem); + + priv->rtllib->wx_set_enc = 1; + down(&priv->rtllib->ips_sem); + IPSLeave(dev); + up(&priv->rtllib->ips_sem); + + ret = rtllib_wx_set_encode_ext(ieee, info, wrqu, extra); + { + u8 broadcast_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u8 zero[6] = {0}; + u32 key[4] = {0}; + struct iw_encode_ext *ext = (struct iw_encode_ext *)extra; + struct iw_point *encoding = &wrqu->encoding; + u8 idx = 0, alg = 0, group = 0; + if ((encoding->flags & IW_ENCODE_DISABLED) || + ext->alg == IW_ENCODE_ALG_NONE) { + ieee->pairwise_key_type = ieee->group_key_type + = KEY_TYPE_NA; + CamResetAllEntry(dev); + memset(priv->rtllib->swcamtable, 0, + sizeof(struct sw_cam_table) * 32); + goto end_hw_sec; + } + alg = (ext->alg == IW_ENCODE_ALG_CCMP) ? KEY_TYPE_CCMP : + ext->alg; + idx = encoding->flags & IW_ENCODE_INDEX; + if (idx) + idx--; + group = ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY; + + if ((!group) || (IW_MODE_ADHOC == ieee->iw_mode) || + (alg == KEY_TYPE_WEP40)) { + if ((ext->key_len == 13) && (alg == KEY_TYPE_WEP40)) + alg = KEY_TYPE_WEP104; + ieee->pairwise_key_type = alg; + EnableHWSecurityConfig8192(dev); + } + memcpy((u8 *)key, ext->key, 16); + + if ((alg & KEY_TYPE_WEP40) && (ieee->auth_mode != 2)) { + if (ext->key_len == 13) + ieee->pairwise_key_type = alg = KEY_TYPE_WEP104; + setKey(dev, idx, idx, alg, zero, 0, key); + set_swcam(dev, idx, idx, alg, zero, 0, key, 0); + } else if (group) { + ieee->group_key_type = alg; + setKey(dev, idx, idx, alg, broadcast_addr, 0, key); + set_swcam(dev, idx, idx, alg, broadcast_addr, 0, + key, 0); + } else { + if ((ieee->pairwise_key_type == KEY_TYPE_CCMP) && + ieee->pHTInfo->bCurrentHTSupport) + write_nic_byte(dev, 0x173, 1); + setKey(dev, 4, idx, alg, (u8 *)ieee->ap_mac_addr, + 0, key); + set_swcam(dev, 4, idx, alg, (u8 *)ieee->ap_mac_addr, + 0, key, 0); + } + + + } + +end_hw_sec: + priv->rtllib->wx_set_enc = 0; + up(&priv->wx_sem); + return ret; + +} +static int r8192_wx_set_auth(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *data, char *extra) +{ + int ret = 0; + + struct r8192_priv *priv = rtllib_priv(dev); + + if (priv->bHwRadioOff == true) + return 0; + + down(&priv->wx_sem); + ret = rtllib_wx_set_auth(priv->rtllib, info, &(data->param), extra); + up(&priv->wx_sem); + return ret; +} + +static int r8192_wx_set_mlme(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + + struct r8192_priv *priv = rtllib_priv(dev); + + if (priv->bHwRadioOff == true) + return 0; + + down(&priv->wx_sem); + ret = rtllib_wx_set_mlme(priv->rtllib, info, wrqu, extra); + up(&priv->wx_sem); + return ret; +} + +static int r8192_wx_set_gen_ie(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *data, char *extra) +{ + int ret = 0; + + struct r8192_priv *priv = rtllib_priv(dev); + + if (priv->bHwRadioOff == true) + return 0; + + down(&priv->wx_sem); + ret = rtllib_wx_set_gen_ie(priv->rtllib, extra, data->data.length); + up(&priv->wx_sem); + return ret; +} + +static int r8192_wx_get_gen_ie(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *data, char *extra) +{ + int ret = 0; + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + + if (ieee->wpa_ie_len == 0 || ieee->wpa_ie == NULL) { + data->data.length = 0; + return 0; + } + + if (data->data.length < ieee->wpa_ie_len) + return -E2BIG; + + data->data.length = ieee->wpa_ie_len; + memcpy(extra, ieee->wpa_ie, ieee->wpa_ie_len); + return ret; +} + +#define OID_RT_INTEL_PROMISCUOUS_MODE 0xFF0101F6 + +static int r8192_wx_set_PromiscuousMode(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + + u32 *info_buf = (u32 *)(wrqu->data.pointer); + + u32 oid = info_buf[0]; + u32 bPromiscuousOn = info_buf[1]; + u32 bFilterSourceStationFrame = info_buf[2]; + + if (OID_RT_INTEL_PROMISCUOUS_MODE == oid) { + ieee->IntelPromiscuousModeInfo.bPromiscuousOn = + (bPromiscuousOn) ? (true) : (false); + ieee->IntelPromiscuousModeInfo.bFilterSourceStationFrame = + (bFilterSourceStationFrame) ? (true) : (false); + (bPromiscuousOn) ? + (rtllib_EnableIntelPromiscuousMode(dev, false)) : + (rtllib_DisableIntelPromiscuousMode(dev, false)); + + printk(KERN_INFO "=======>%s(), on = %d, filter src sta = %d\n", + __func__, bPromiscuousOn, bFilterSourceStationFrame); + } else { + return -1; + } + + return 0; +} + + +static int r8192_wx_get_PromiscuousMode(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + + down(&priv->wx_sem); + + snprintf(extra, 45, "PromiscuousMode:%d, FilterSrcSTAFrame:%d", + ieee->IntelPromiscuousModeInfo.bPromiscuousOn, + ieee->IntelPromiscuousModeInfo.bFilterSourceStationFrame); + wrqu->data.length = strlen(extra) + 1; + + up(&priv->wx_sem); + + return 0; +} + + +#define IW_IOCTL(x) [(x)-SIOCSIWCOMMIT] +static iw_handler r8192_wx_handlers[] = { + IW_IOCTL(SIOCGIWNAME) = r8192_wx_get_name, + IW_IOCTL(SIOCSIWFREQ) = r8192_wx_set_freq, + IW_IOCTL(SIOCGIWFREQ) = r8192_wx_get_freq, + IW_IOCTL(SIOCSIWMODE) = r8192_wx_set_mode, + IW_IOCTL(SIOCGIWMODE) = r8192_wx_get_mode, + IW_IOCTL(SIOCSIWSENS) = r8192_wx_set_sens, + IW_IOCTL(SIOCGIWSENS) = r8192_wx_get_sens, + IW_IOCTL(SIOCGIWRANGE) = rtl8192_wx_get_range, + IW_IOCTL(SIOCSIWAP) = r8192_wx_set_wap, + IW_IOCTL(SIOCGIWAP) = r8192_wx_get_wap, + IW_IOCTL(SIOCSIWSCAN) = r8192_wx_set_scan, + IW_IOCTL(SIOCGIWSCAN) = r8192_wx_get_scan, + IW_IOCTL(SIOCSIWESSID) = r8192_wx_set_essid, + IW_IOCTL(SIOCGIWESSID) = r8192_wx_get_essid, + IW_IOCTL(SIOCSIWNICKN) = r8192_wx_set_nick, + IW_IOCTL(SIOCGIWNICKN) = r8192_wx_get_nick, + IW_IOCTL(SIOCSIWRATE) = r8192_wx_set_rate, + IW_IOCTL(SIOCGIWRATE) = r8192_wx_get_rate, + IW_IOCTL(SIOCSIWRTS) = r8192_wx_set_rts, + IW_IOCTL(SIOCGIWRTS) = r8192_wx_get_rts, + IW_IOCTL(SIOCSIWFRAG) = r8192_wx_set_frag, + IW_IOCTL(SIOCGIWFRAG) = r8192_wx_get_frag, + IW_IOCTL(SIOCSIWRETRY) = r8192_wx_set_retry, + IW_IOCTL(SIOCGIWRETRY) = r8192_wx_get_retry, + IW_IOCTL(SIOCSIWENCODE) = r8192_wx_set_enc, + IW_IOCTL(SIOCGIWENCODE) = r8192_wx_get_enc, + IW_IOCTL(SIOCSIWPOWER) = r8192_wx_set_power, + IW_IOCTL(SIOCGIWPOWER) = r8192_wx_get_power, + IW_IOCTL(SIOCSIWGENIE) = r8192_wx_set_gen_ie, + IW_IOCTL(SIOCGIWGENIE) = r8192_wx_get_gen_ie, + IW_IOCTL(SIOCSIWMLME) = r8192_wx_set_mlme, + IW_IOCTL(SIOCSIWAUTH) = r8192_wx_set_auth, + IW_IOCTL(SIOCSIWENCODEEXT) = r8192_wx_set_enc_ext, +}; + +/* + * the following rule need to be follwing, + * Odd : get (world access), + * even : set (root access) + * */ +static const struct iw_priv_args r8192_private_args[] = { + { + SIOCIWFIRSTPRIV + 0x0, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "set_debugflag" + }, { + SIOCIWFIRSTPRIV + 0x1, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "activescan" + }, { + SIOCIWFIRSTPRIV + 0x2, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "rawtx" + }, { + SIOCIWFIRSTPRIV + 0x3, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "forcereset" + }, { + SIOCIWFIRSTPRIV + 0x4, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "force_mic_error" + }, { + SIOCIWFIRSTPRIV + 0x5, + IW_PRIV_TYPE_NONE, IW_PRIV_TYPE_INT|IW_PRIV_SIZE_FIXED|1, + "firm_ver" + }, { + SIOCIWFIRSTPRIV + 0x6, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED|1, IW_PRIV_TYPE_NONE, + "set_power" + }, { + SIOCIWFIRSTPRIV + 0x9, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED|1, IW_PRIV_TYPE_NONE, + "radio" + }, { + SIOCIWFIRSTPRIV + 0xa, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED|1, IW_PRIV_TYPE_NONE, + "lps_interv" + }, { + SIOCIWFIRSTPRIV + 0xb, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED|1, IW_PRIV_TYPE_NONE, + "lps_force" + }, { + SIOCIWFIRSTPRIV + 0xc, + 0, IW_PRIV_TYPE_CHAR|2047, "adhoc_peer_list" + }, { + SIOCIWFIRSTPRIV + 0x16, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 3, 0, "setpromisc" + }, { + SIOCIWFIRSTPRIV + 0x17, + 0, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | 45, "getpromisc" + } + +}; + +static iw_handler r8192_private_handler[] = { + (iw_handler)r8192_wx_set_debugflag, /*SIOCIWSECONDPRIV*/ + (iw_handler)r8192_wx_set_scan_type, + (iw_handler)r8192_wx_set_rawtx, + (iw_handler)r8192_wx_force_reset, + (iw_handler)r8192_wx_force_mic_error, + (iw_handler)r8191se_wx_get_firm_version, + (iw_handler)r8192_wx_adapter_power_status, + (iw_handler)NULL, + (iw_handler)NULL, + (iw_handler)r8192se_wx_set_radio, + (iw_handler)r8192se_wx_set_lps_awake_interval, + (iw_handler)r8192se_wx_set_force_lps, + (iw_handler)r8192_wx_get_adhoc_peers, + (iw_handler)NULL, + (iw_handler)NULL, + (iw_handler)NULL, + (iw_handler)NULL, + (iw_handler)NULL, + (iw_handler)NULL, + (iw_handler)NULL, + (iw_handler)NULL, + (iw_handler)NULL, + (iw_handler)r8192_wx_set_PromiscuousMode, + (iw_handler)r8192_wx_get_PromiscuousMode, +}; + +static struct iw_statistics *r8192_get_wireless_stats(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + struct iw_statistics *wstats = &priv->wstats; + int tmp_level = 0; + int tmp_qual = 0; + int tmp_noise = 0; + if (ieee->state < RTLLIB_LINKED) { + wstats->qual.qual = 10; + wstats->qual.level = 0; + wstats->qual.noise = -100; + wstats->qual.updated = IW_QUAL_ALL_UPDATED | IW_QUAL_DBM; + return wstats; + } + + tmp_level = (&ieee->current_network)->stats.rssi; + tmp_qual = (&ieee->current_network)->stats.signal; + tmp_noise = (&ieee->current_network)->stats.noise; + + wstats->qual.level = tmp_level; + wstats->qual.qual = tmp_qual; + wstats->qual.noise = tmp_noise; + wstats->qual.updated = IW_QUAL_ALL_UPDATED | IW_QUAL_DBM; + return wstats; +} + +struct iw_handler_def r8192_wx_handlers_def = { + .standard = r8192_wx_handlers, + .num_standard = sizeof(r8192_wx_handlers) / sizeof(iw_handler), + .private = r8192_private_handler, + .num_private = sizeof(r8192_private_handler) / sizeof(iw_handler), + .num_private_args = sizeof(r8192_private_args) / + sizeof(struct iw_priv_args), + .get_wireless_stats = r8192_get_wireless_stats, + .private_args = (struct iw_priv_args *)r8192_private_args, +}; diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_wx.h b/drivers/staging/rtl8192e/rtl8192e/rtl_wx.h new file mode 100644 index 000000000000..6a51a25ec87d --- /dev/null +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_wx.h @@ -0,0 +1,31 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ + +#ifndef R819x_WX_H +#define R819x_WX_H + +struct net_device; +struct iw_handler_def; +struct iw_statistics; + +extern struct iw_handler_def r8192_wx_handlers_def; +struct iw_statistics *r8192_get_wireless_stats(struct net_device *dev); +u16 rtl8192_11n_user_show_rates(struct net_device *dev); + +#endif |