diff options
Diffstat (limited to 'drivers/staging/rtl8723bs/include')
| -rw-r--r-- | drivers/staging/rtl8723bs/include/HalVerDef.h | 10 | ||||
| -rw-r--r-- | drivers/staging/rtl8723bs/include/drv_types.h | 4 | ||||
| -rw-r--r-- | drivers/staging/rtl8723bs/include/hal_btcoex.h | 1 | ||||
| -rw-r--r-- | drivers/staging/rtl8723bs/include/hal_com.h | 9 | ||||
| -rw-r--r-- | drivers/staging/rtl8723bs/include/hal_com_reg.h | 295 | ||||
| -rw-r--r-- | drivers/staging/rtl8723bs/include/hal_intf.h | 2 | ||||
| -rw-r--r-- | drivers/staging/rtl8723bs/include/ieee80211.h | 3 | ||||
| -rw-r--r-- | drivers/staging/rtl8723bs/include/rtw_cmd.h | 5 | ||||
| -rw-r--r-- | drivers/staging/rtl8723bs/include/rtw_ioctl.h | 72 | ||||
| -rw-r--r-- | drivers/staging/rtl8723bs/include/rtw_mlme.h | 8 | ||||
| -rw-r--r-- | drivers/staging/rtl8723bs/include/rtw_mlme_ext.h | 1 | ||||
| -rw-r--r-- | drivers/staging/rtl8723bs/include/rtw_odm.h | 28 | ||||
| -rw-r--r-- | drivers/staging/rtl8723bs/include/rtw_recv.h | 11 | ||||
| -rw-r--r-- | drivers/staging/rtl8723bs/include/xmit_osdep.h | 4 |
14 files changed, 10 insertions, 443 deletions
diff --git a/drivers/staging/rtl8723bs/include/HalVerDef.h b/drivers/staging/rtl8723bs/include/HalVerDef.h index 8f654a49fb9d..d0ce21ccc1cc 100644 --- a/drivers/staging/rtl8723bs/include/HalVerDef.h +++ b/drivers/staging/rtl8723bs/include/HalVerDef.h @@ -9,16 +9,7 @@ /* hal_ic_type_e */ enum hal_ic_type_e { /* tag_HAL_IC_Type_Definition */ - CHIP_8192S = 0, - CHIP_8188C = 1, - CHIP_8192C = 2, - CHIP_8192D = 3, - CHIP_8723A = 4, - CHIP_8188E = 5, - CHIP_8812 = 6, - CHIP_8821 = 7, CHIP_8723B = 8, - CHIP_8192E = 9, }; /* hal_chip_type_e */ @@ -58,7 +49,6 @@ struct hal_version { /* tag_HAL_VERSION */ u8 ROMVer; }; -/* VERSION_8192C VersionID; */ /* hal_version VersionID; */ /* Get element */ diff --git a/drivers/staging/rtl8723bs/include/drv_types.h b/drivers/staging/rtl8723bs/include/drv_types.h index 0ce08c2a0755..82159e1c7f9b 100644 --- a/drivers/staging/rtl8723bs/include/drv_types.h +++ b/drivers/staging/rtl8723bs/include/drv_types.h @@ -42,7 +42,6 @@ #include <rtw_mlme.h> #include <mlme_osdep.h> #include <rtw_io.h> -#include <rtw_ioctl.h> #include <rtw_ioctl_set.h> #include <osdep_intf.h> #include <rtw_eeprom.h> @@ -51,7 +50,6 @@ #include <rtw_mlme_ext.h> #include <rtw_ap.h> #include <rtw_version.h> -#include <rtw_odm.h> #include "ioctl_cfg80211.h" @@ -494,8 +492,6 @@ static inline u8 *myid(struct eeprom_priv *peepriv) #include <rtw_btcoex.h> -int rtw_change_ifname(struct adapter *padapter, const char *ifname); - extern char *rtw_initmac; extern int rtw_mc2u_disable; extern int rtw_ht_enable; diff --git a/drivers/staging/rtl8723bs/include/hal_btcoex.h b/drivers/staging/rtl8723bs/include/hal_btcoex.h index 78599d3521bf..fb167642da01 100644 --- a/drivers/staging/rtl8723bs/include/hal_btcoex.h +++ b/drivers/staging/rtl8723bs/include/hal_btcoex.h @@ -45,7 +45,6 @@ void hal_btcoex_HaltNotify(struct adapter *padapter); void hal_btcoex_Handler(struct adapter *padapter); s32 hal_btcoex_IsBTCoexCtrlAMPDUSize(struct adapter *padapter); -void hal_btcoex_SetManualControl(struct adapter *padapter, u8 bmanual); bool hal_btcoex_IsBtControlLps(struct adapter *padapter); bool hal_btcoex_IsLpsOn(struct adapter *padapter); u8 hal_btcoex_RpwmVal(struct adapter *); diff --git a/drivers/staging/rtl8723bs/include/hal_com.h b/drivers/staging/rtl8723bs/include/hal_com.h index 7be0ea20bca4..6356b8c2ef81 100644 --- a/drivers/staging/rtl8723bs/include/hal_com.h +++ b/drivers/staging/rtl8723bs/include/hal_com.h @@ -147,17 +147,8 @@ u8 GetHalDefVar(struct adapter *adapter, enum hal_def_variable variable, bool eqNByte(u8 *str1, u8 *str2, u32 num); -bool IsHexDigit(char chTmp); - u32 MapCharToHexDigit(char chTmp); -bool GetHexValueFromString(char *szStr, u32 *pu4bVal, u32 *pu4bMove); - -bool GetFractionValueFromString(char *szStr, u8 *pInteger, u8 *pFraction, - u32 *pu4bMove); - -bool IsCommentString(char *szStr); - bool ParseQualifiedString(char *In, u32 *Start, char *Out, char LeftQualifier, char RightQualifier); diff --git a/drivers/staging/rtl8723bs/include/hal_com_reg.h b/drivers/staging/rtl8723bs/include/hal_com_reg.h index 8213dcf48b34..d8d03752dc2e 100644 --- a/drivers/staging/rtl8723bs/include/hal_com_reg.h +++ b/drivers/staging/rtl8723bs/include/hal_com_reg.h @@ -72,13 +72,9 @@ #define REG_MULTI_FUNC_CTRL 0x0068 /* RTL8723 WIFI/BT/GPS Multi-Function control source. */ #define REG_GSSR 0x006c #define REG_AFE_XTAL_CTRL_EXT 0x0078 /* RTL8188E */ -#define REG_XCK_OUT_CTRL 0x007c /* RTL8188E */ #define REG_MCUFWDL 0x0080 -#define REG_WOL_EVENT 0x0081 /* RTL8188E */ #define REG_MCUTSTCFG 0x0084 #define REG_FDHM0 0x0088 -#define REG_HOST_SUSP_CNT 0x00BC /* RTL8192C Host suspend counter on FPGA platform */ -#define REG_SYSTEM_ON_CTRL 0x00CC /* For 8723AE Reset after S3 */ #define REG_EFUSE_ACCESS 0x00CF /* Efuse access protection for RTL8723 */ #define REG_BIST_SCAN 0x00D0 #define REG_BIST_RPT 0x00D4 @@ -117,7 +113,6 @@ #define REG_FWIMR 0x0130 #define REG_FWISR 0x0134 #define REG_FTIMR 0x0138 -#define REG_FTISR 0x013C /* RTL8192C */ #define REG_PKTBUF_DBG_CTRL 0x0140 #define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2) #define REG_PKTBUF_DBG_DATA_L 0x0144 @@ -132,11 +127,9 @@ #define REG_MBIST_START 0x0174 #define REG_MBIST_DONE 0x0178 #define REG_MBIST_FAIL 0x017C -#define REG_32K_CTRL 0x0194 /* RTL8188E */ #define REG_C2HEVT_MSG_NORMAL 0x01A0 #define REG_C2HEVT_CLEAR 0x01AF #define REG_MCUTST_1 0x01c0 -#define REG_MCUTST_WOWLAN 0x01C7 /* Defined after 8188E series. */ #define REG_FMETHR 0x01C8 #define REG_HMETFR 0x01CC #define REG_HMEBOX_0 0x01D0 @@ -526,44 +519,6 @@ #define MAX_MSS_DENSITY_1T 0x0A /* */ -/* 8192C Cmd9346CR bits (Offset 0xA, 16bit) */ -/* */ -#define CmdEEPROM_En BIT5 /* EEPROM enable when set 1 */ -#define CmdEERPOMSEL BIT4 /* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */ -#define Cmd9346CR_9356SEL BIT4 - -/* */ -/* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) */ -/* */ -#define GPIOSEL_GPIO 0 -#define GPIOSEL_ENBT BIT5 - -/* */ -/* 8192C GPIO PIN Control Register (offset 0x44, 4 byte) */ -/* */ -#define GPIO_IN REG_GPIO_PIN_CTRL /* GPIO pins input value */ -#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) /* GPIO pins output value */ -#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) /* GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. */ -#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) - -/* */ -/* 8811A GPIO PIN Control Register (offset 0x60, 4 byte) */ -/* */ -#define GPIO_IN_8811A REG_GPIO_PIN_CTRL_2 /* GPIO pins input value */ -#define GPIO_OUT_8811A (REG_GPIO_PIN_CTRL_2+1) /* GPIO pins output value */ -#define GPIO_IO_SEL_8811A (REG_GPIO_PIN_CTRL_2+2) /* GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. */ -#define GPIO_MOD_8811A (REG_GPIO_PIN_CTRL_2+3) - -/* */ -/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */ -/* */ -#define HSIMR_GPIO12_0_INT_EN BIT0 -#define HSIMR_SPS_OCP_INT_EN BIT5 -#define HSIMR_RON_INT_EN BIT6 -#define HSIMR_PDN_INT_EN BIT7 -#define HSIMR_GPIO9_INT_EN BIT25 - -/* */ /* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */ /* */ #define HSISR_GPIO12_0_INT BIT0 @@ -573,22 +528,6 @@ #define HSISR_GPIO9_INT BIT25 /* */ -/* 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) */ -/* */ -/* -Network Type -00: No link -01: Link in ad hoc network -10: Link in infrastructure network -11: AP mode -Default: 00b. -*/ -#define MSR_NOLINK 0x00 -#define MSR_ADHOC 0x01 -#define MSR_INFRA 0x02 -#define MSR_AP 0x03 - -/* */ /* USB INTR CONTENT */ /* */ #define USB_C2H_CMDID_OFFSET 0 @@ -787,206 +726,6 @@ Default: 00b. #define IMR_WLANOFF BIT0 /* */ -/* 8723E series PCIE Host IMR/ISR bit */ -/* */ -/* IMR DW0 Bit 0-31 */ -#define PHIMR_TIMEOUT2 BIT31 -#define PHIMR_TIMEOUT1 BIT30 -#define PHIMR_PSTIMEOUT BIT29 -#define PHIMR_GTINT4 BIT28 -#define PHIMR_GTINT3 BIT27 -#define PHIMR_TXBCNERR BIT26 -#define PHIMR_TXBCNOK BIT25 -#define PHIMR_TSF_BIT32_TOGGLE BIT24 -#define PHIMR_BCNDMAINT3 BIT23 -#define PHIMR_BCNDMAINT2 BIT22 -#define PHIMR_BCNDMAINT1 BIT21 -#define PHIMR_BCNDMAINT0 BIT20 -#define PHIMR_BCNDOK3 BIT19 -#define PHIMR_BCNDOK2 BIT18 -#define PHIMR_BCNDOK1 BIT17 -#define PHIMR_BCNDOK0 BIT16 -#define PHIMR_HSISR_IND_ON BIT15 -#define PHIMR_BCNDMAINT_E BIT14 -#define PHIMR_ATIMEND_E BIT13 -#define PHIMR_ATIM_CTW_END BIT12 -#define PHIMR_HISRE_IND BIT11 /* RO. HISRE Indicator (HISRE & HIMRE is true, this bit is set to 1) */ -#define PHIMR_C2HCMD BIT10 -#define PHIMR_CPWM2 BIT9 -#define PHIMR_CPWM BIT8 -#define PHIMR_HIGHDOK BIT7 /* High Queue DMA OK Interrupt */ -#define PHIMR_MGNTDOK BIT6 /* Management Queue DMA OK Interrupt */ -#define PHIMR_BKDOK BIT5 /* AC_BK DMA OK Interrupt */ -#define PHIMR_BEDOK BIT4 /* AC_BE DMA OK Interrupt */ -#define PHIMR_VIDOK BIT3 /* AC_VI DMA OK Interrupt */ -#define PHIMR_VODOK BIT2 /* AC_VO DMA Interrupt */ -#define PHIMR_RDU BIT1 /* Receive Descriptor Unavailable */ -#define PHIMR_ROK BIT0 /* Receive DMA OK Interrupt */ - -/* PCIE Host Interrupt Status Extension bit */ -#define PHIMR_BCNDMAINT7 BIT23 -#define PHIMR_BCNDMAINT6 BIT22 -#define PHIMR_BCNDMAINT5 BIT21 -#define PHIMR_BCNDMAINT4 BIT20 -#define PHIMR_BCNDOK7 BIT19 -#define PHIMR_BCNDOK6 BIT18 -#define PHIMR_BCNDOK5 BIT17 -#define PHIMR_BCNDOK4 BIT16 -/* bit12 15: RSVD */ -#define PHIMR_TXERR BIT11 -#define PHIMR_RXERR BIT10 -#define PHIMR_TXFOVW BIT9 -#define PHIMR_RXFOVW BIT8 -/* bit2-7: RSVD */ -#define PHIMR_OCPINT BIT1 -/* bit0: RSVD */ - -#define UHIMR_TIMEOUT2 BIT31 -#define UHIMR_TIMEOUT1 BIT30 -#define UHIMR_PSTIMEOUT BIT29 -#define UHIMR_GTINT4 BIT28 -#define UHIMR_GTINT3 BIT27 -#define UHIMR_TXBCNERR BIT26 -#define UHIMR_TXBCNOK BIT25 -#define UHIMR_TSF_BIT32_TOGGLE BIT24 -#define UHIMR_BCNDMAINT3 BIT23 -#define UHIMR_BCNDMAINT2 BIT22 -#define UHIMR_BCNDMAINT1 BIT21 -#define UHIMR_BCNDMAINT0 BIT20 -#define UHIMR_BCNDOK3 BIT19 -#define UHIMR_BCNDOK2 BIT18 -#define UHIMR_BCNDOK1 BIT17 -#define UHIMR_BCNDOK0 BIT16 -#define UHIMR_HSISR_IND BIT15 -#define UHIMR_BCNDMAINT_E BIT14 -/* RSVD BIT13 */ -#define UHIMR_CTW_END BIT12 -/* RSVD BIT11 */ -#define UHIMR_C2HCMD BIT10 -#define UHIMR_CPWM2 BIT9 -#define UHIMR_CPWM BIT8 -#define UHIMR_HIGHDOK BIT7 /* High Queue DMA OK Interrupt */ -#define UHIMR_MGNTDOK BIT6 /* Management Queue DMA OK Interrupt */ -#define UHIMR_BKDOK BIT5 /* AC_BK DMA OK Interrupt */ -#define UHIMR_BEDOK BIT4 /* AC_BE DMA OK Interrupt */ -#define UHIMR_VIDOK BIT3 /* AC_VI DMA OK Interrupt */ -#define UHIMR_VODOK BIT2 /* AC_VO DMA Interrupt */ -#define UHIMR_RDU BIT1 /* Receive Descriptor Unavailable */ -#define UHIMR_ROK BIT0 /* Receive DMA OK Interrupt */ - -/* USB Host Interrupt Status Extension bit */ -#define UHIMR_BCNDMAINT7 BIT23 -#define UHIMR_BCNDMAINT6 BIT22 -#define UHIMR_BCNDMAINT5 BIT21 -#define UHIMR_BCNDMAINT4 BIT20 -#define UHIMR_BCNDOK7 BIT19 -#define UHIMR_BCNDOK6 BIT18 -#define UHIMR_BCNDOK5 BIT17 -#define UHIMR_BCNDOK4 BIT16 -/* bit14-15: RSVD */ -#define UHIMR_ATIMEND_E BIT13 -#define UHIMR_ATIMEND BIT12 -#define UHIMR_TXERR BIT11 -#define UHIMR_RXERR BIT10 -#define UHIMR_TXFOVW BIT9 -#define UHIMR_RXFOVW BIT8 -/* bit2-7: RSVD */ -#define UHIMR_OCPINT BIT1 -/* bit0: RSVD */ - - -#define HAL_NIC_UNPLUG_ISR 0xFFFFFFFF /* The value when the NIC is unplugged for PCI. */ -#define HAL_NIC_UNPLUG_PCI_ISR 0xEAEAEAEA /* The value when the NIC is unplugged for PCI in PCI interrupt (page 3). */ - -/* */ -/* 8188 IMR/ISR bits */ -/* */ -#define IMR_DISABLED_88E 0x0 -/* IMR DW0(0x0060-0063) Bit 0-31 */ -#define IMR_TXCCK_88E BIT30 /* TXRPT interrupt when CCX bit of the packet is set */ -#define IMR_PSTIMEOUT_88E BIT29 /* Power Save Time Out Interrupt */ -#define IMR_GTINT4_88E BIT28 /* When GTIMER4 expires, this bit is set to 1 */ -#define IMR_GTINT3_88E BIT27 /* When GTIMER3 expires, this bit is set to 1 */ -#define IMR_TBDER_88E BIT26 /* Transmit Beacon0 Error */ -#define IMR_TBDOK_88E BIT25 /* Transmit Beacon0 OK */ -#define IMR_TSF_BIT32_TOGGLE_88E BIT24 /* TSF Timer BIT32 toggle indication interrupt */ -#define IMR_BCNDMAINT0_88E BIT20 /* Beacon DMA Interrupt 0 */ -#define IMR_BCNDERR0_88E BIT16 /* Beacon Queue DMA Error 0 */ -#define IMR_HSISR_IND_ON_INT_88E BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ -#define IMR_BCNDMAINT_E_88E BIT14 /* Beacon DMA Interrupt Extension for Win7 */ -#define IMR_ATIMEND_88E BIT12 /* CTWidnow End or ATIM Window End */ -#define IMR_HISR1_IND_INT_88E BIT11 /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */ -#define IMR_C2HCMD_88E BIT10 /* CPU to Host Command INT Status, Write 1 clear */ -#define IMR_CPWM2_88E BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_CPWM_88E BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_HIGHDOK_88E BIT7 /* High Queue DMA OK */ -#define IMR_MGNTDOK_88E BIT6 /* Management Queue DMA OK */ -#define IMR_BKDOK_88E BIT5 /* AC_BK DMA OK */ -#define IMR_BEDOK_88E BIT4 /* AC_BE DMA OK */ -#define IMR_VIDOK_88E BIT3 /* AC_VI DMA OK */ -#define IMR_VODOK_88E BIT2 /* AC_VO DMA OK */ -#define IMR_RDU_88E BIT1 /* Rx Descriptor Unavailable */ -#define IMR_ROK_88E BIT0 /* Receive DMA OK */ - -/* IMR DW1(0x00B4-00B7) Bit 0-31 */ -#define IMR_BCNDMAINT7_88E BIT27 /* Beacon DMA Interrupt 7 */ -#define IMR_BCNDMAINT6_88E BIT26 /* Beacon DMA Interrupt 6 */ -#define IMR_BCNDMAINT5_88E BIT25 /* Beacon DMA Interrupt 5 */ -#define IMR_BCNDMAINT4_88E BIT24 /* Beacon DMA Interrupt 4 */ -#define IMR_BCNDMAINT3_88E BIT23 /* Beacon DMA Interrupt 3 */ -#define IMR_BCNDMAINT2_88E BIT22 /* Beacon DMA Interrupt 2 */ -#define IMR_BCNDMAINT1_88E BIT21 /* Beacon DMA Interrupt 1 */ -#define IMR_BCNDOK7_88E BIT20 /* Beacon Queue DMA OK Interrupt 7 */ -#define IMR_BCNDOK6_88E BIT19 /* Beacon Queue DMA OK Interrupt 6 */ -#define IMR_BCNDOK5_88E BIT18 /* Beacon Queue DMA OK Interrupt 5 */ -#define IMR_BCNDOK4_88E BIT17 /* Beacon Queue DMA OK Interrupt 4 */ -#define IMR_BCNDOK3_88E BIT16 /* Beacon Queue DMA OK Interrupt 3 */ -#define IMR_BCNDOK2_88E BIT15 /* Beacon Queue DMA OK Interrupt 2 */ -#define IMR_BCNDOK1_88E BIT14 /* Beacon Queue DMA OK Interrupt 1 */ -#define IMR_ATIMEND_E_88E BIT13 /* ATIM Window End Extension for Win7 */ -#define IMR_TXERR_88E BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ -#define IMR_RXERR_88E BIT10 /* Rx Error Flag INT Status, Write 1 clear */ -#define IMR_TXFOVW_88E BIT9 /* Transmit FIFO Overflow */ -#define IMR_RXFOVW_88E BIT8 /* Receive FIFO Overflow */ - -/*=================================================================== -===================================================================== -Here the register defines are for 92C. When the define is as same with 92C, -we will use the 92C's define for the consistency -So the following defines for 92C is not entire!!!!!! -===================================================================== -=====================================================================*/ -/* -Based on Datasheet V33---090401 -Register Summary -Current IOREG MAP -0x0000h ~ 0x00FFh System Configuration (256 Bytes) -0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) -0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) -0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) -0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) -0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) -0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) -0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) -0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) -*/ - /* */ - /* 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) */ - /* */ -/* Note: */ -/* The bits of stopping AC(VO/VI/BE/BK) queue in datasheet RTL8192S/RTL8192C are wrong, */ -/* the correct arrangement is VO - Bit0, VI - Bit1, BE - Bit2, and BK - Bit3. */ -/* 8723 and 88E may be not correct either in the earlier version. Confirmed with DD Tim. */ -/* By Bruce, 2011-09-22. */ -#define StopBecon BIT6 -#define StopHigh BIT5 -#define StopMgt BIT4 -#define StopBK BIT3 -#define StopBE BIT2 -#define StopVI BIT1 -#define StopVO BIT0 - -/* */ /* 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits) */ /* */ #define RCR_APPFCS BIT31 /* WMAC append FCS after pauload */ @@ -1557,10 +1296,6 @@ Current IOREG MAP #define SDIO_HIMR_ATIMEND_E_MSK BIT26 #define SDIO_HIMR_CTWEND_MSK BIT27 -/* RTL8188E SDIO Specific */ -#define SDIO_HIMR_MCU_ERR_MSK BIT28 -#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT29 - /* SDIO Host Interrupt Service Routine */ #define SDIO_HISR_RX_REQUEST BIT0 #define SDIO_HISR_AVAL BIT1 @@ -1583,10 +1318,6 @@ Current IOREG MAP #define SDIO_HISR_ATIMEND_E BIT26 #define SDIO_HISR_CTWEND BIT27 -/* RTL8188E SDIO Specific */ -#define SDIO_HISR_MCU_ERR BIT28 -#define SDIO_HISR_TSF_BIT32_TOGGLE BIT29 - #define MASK_SDIO_HISR_CLEAR (SDIO_HISR_TXERR |\ SDIO_HISR_RXERR |\ SDIO_HISR_TXFOVW |\ @@ -1651,39 +1382,13 @@ Current IOREG MAP #define GPS_HWPDN_SL BIT21 /* GPS HW PDn polarity control */ #define GPS_FUNC_EN BIT22 /* GPS function enable */ -/* 3 REG_LIFECTRL_CTRL */ -#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 -#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 -#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 -#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 - -#define HAL92C_MSDU_LIFE_TIME_UNIT 128 /* in us, said by Tim. */ - -/* 2 8192D PartNo. */ -#define PARTNO_92D_NIC (BIT7|BIT6) -#define PARTNO_92D_NIC_REMARK (BIT5|BIT4) -#define PARTNO_SINGLE_BAND_VS BIT3 -#define PARTNO_SINGLE_BAND_VS_REMARK BIT1 -#define PARTNO_CONCURRENT_BAND_VC (BIT3|BIT2) -#define PARTNO_CONCURRENT_BAND_VC_REMARK (BIT1|BIT0) - /* */ /* General definitions */ /* */ -#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E 176 -#define LAST_ENTRY_OF_TX_PKT_BUFFER_8812 255 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8723B 255 -#define LAST_ENTRY_OF_TX_PKT_BUFFER_8192C 255 -#define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC 127 #define POLLING_LLT_THRESHOLD 20 #define POLLING_READY_TIMEOUT_COUNT 1000 - -/* GPIO BIT */ -#define HAL_8192C_HW_GPIO_WPS_BIT BIT2 -#define HAL_8192EU_HW_GPIO_WPS_BIT BIT7 -#define HAL_8188E_HW_GPIO_WPS_BIT BIT7 - #endif /* __HAL_COMMON_H__ */ diff --git a/drivers/staging/rtl8723bs/include/hal_intf.h b/drivers/staging/rtl8723bs/include/hal_intf.h index 45bebbadb7ca..5cffab2d06ff 100644 --- a/drivers/staging/rtl8723bs/include/hal_intf.h +++ b/drivers/staging/rtl8723bs/include/hal_intf.h @@ -353,8 +353,6 @@ bool rtw_hal_c2h_valid(struct adapter *adapter, u8 *buf); s32 rtw_hal_c2h_handler(struct adapter *adapter, u8 *c2h_evt); c2h_id_filter rtw_hal_c2h_id_filter_ccx(struct adapter *adapter); -s32 rtw_hal_is_disable_sw_channel_plan(struct adapter *padapter); - s32 rtw_hal_macid_sleep(struct adapter *padapter, u32 macid); s32 rtw_hal_macid_wakeup(struct adapter *padapter, u32 macid); diff --git a/drivers/staging/rtl8723bs/include/ieee80211.h b/drivers/staging/rtl8723bs/include/ieee80211.h index c11d7e2d2347..9041d8dc5fb1 100644 --- a/drivers/staging/rtl8723bs/include/ieee80211.h +++ b/drivers/staging/rtl8723bs/include/ieee80211.h @@ -204,7 +204,7 @@ struct ieee_param { struct ieee_param_ex { u32 cmd; u8 sta_addr[ETH_ALEN]; - u8 data[0]; + u8 data[]; }; struct sta_data { @@ -746,7 +746,6 @@ int rtw_parse_wpa2_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwi void rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, u8 *wpa_ie, u16 *wpa_len); -u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen); u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen); u8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id, u8 *buf_attr, u32 *len_attr); u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id, u8 *buf_content, uint *len_content); diff --git a/drivers/staging/rtl8723bs/include/rtw_cmd.h b/drivers/staging/rtl8723bs/include/rtw_cmd.h index 28d2d2732374..fe1b03101203 100644 --- a/drivers/staging/rtl8723bs/include/rtw_cmd.h +++ b/drivers/staging/rtl8723bs/include/rtw_cmd.h @@ -94,7 +94,7 @@ struct c2h_evt_hdr { u8 id:4; u8 plen:4; u8 seq; - u8 payload[0]; + u8 payload[]; }; struct c2h_evt_hdr_88xx { @@ -591,7 +591,6 @@ extern u8 rtw_clearstakey_cmd(struct adapter *padapter, struct sta_info *sta, u8 extern u8 rtw_joinbss_cmd(struct adapter *padapter, struct wlan_network *pnetwork); u8 rtw_disassoc_cmd(struct adapter *padapter, u32 deauth_timeout_ms, bool enqueue); extern u8 rtw_setopmode_cmd(struct adapter *padapter, enum ndis_802_11_network_infrastructure networktype, bool enqueue); -extern u8 rtw_setdatarate_cmd(struct adapter *padapter, u8 *rateset); extern u8 rtw_setrfintfs_cmd(struct adapter *padapter, u8 mode); extern u8 rtw_gettssi_cmd(struct adapter *padapter, u8 offset, u8 *pval); @@ -613,8 +612,6 @@ extern u8 rtw_ps_cmd(struct adapter *padapter); u8 rtw_chk_hi_queue_cmd(struct adapter *padapter); -extern u8 rtw_set_chplan_cmd(struct adapter *padapter, u8 chplan, u8 enqueue, u8 swconfig); - extern u8 rtw_c2h_packet_wk_cmd(struct adapter *padapter, u8 *pbuf, u16 length); extern u8 rtw_c2h_wk_cmd(struct adapter *padapter, u8 *c2h_evt); diff --git a/drivers/staging/rtl8723bs/include/rtw_ioctl.h b/drivers/staging/rtl8723bs/include/rtw_ioctl.h deleted file mode 100644 index 7179591cb01d..000000000000 --- a/drivers/staging/rtl8723bs/include/rtw_ioctl.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - ******************************************************************************/ -#ifndef _RTW_IOCTL_H_ -#define _RTW_IOCTL_H_ - -/* 00 - Success */ -/* 11 - Error */ -#define STATUS_SUCCESS (0x00000000L) -#define STATUS_PENDING (0x00000103L) - -#define STATUS_UNSUCCESSFUL (0xC0000001L) -#define STATUS_INSUFFICIENT_RESOURCES (0xC000009AL) -#define STATUS_NOT_SUPPORTED (0xC00000BBL) - -#define NDIS_STATUS_SUCCESS ((uint)STATUS_SUCCESS) -#define NDIS_STATUS_PENDING ((uint)STATUS_PENDING) -#define NDIS_STATUS_NOT_RECOGNIZED ((uint)0x00010001L) -#define NDIS_STATUS_NOT_COPIED ((uint)0x00010002L) -#define NDIS_STATUS_NOT_ACCEPTED ((uint)0x00010003L) -#define NDIS_STATUS_CALL_ACTIVE ((uint)0x00010007L) - -#define NDIS_STATUS_FAILURE ((uint)STATUS_UNSUCCESSFUL) -#define NDIS_STATUS_RESOURCES ((uint)STATUS_INSUFFICIENT_RESOURCES) -#define NDIS_STATUS_CLOSING ((uint)0xC0010002L) -#define NDIS_STATUS_BAD_VERSION ((uint)0xC0010004L) -#define NDIS_STATUS_BAD_CHARACTERISTICS ((uint)0xC0010005L) -#define NDIS_STATUS_ADAPTER_NOT_FOUND ((uint)0xC0010006L) -#define NDIS_STATUS_OPEN_FAILED ((uint)0xC0010007L) -#define NDIS_STATUS_DEVICE_FAILED ((uint)0xC0010008L) -#define NDIS_STATUS_MULTICAST_FULL ((uint)0xC0010009L) -#define NDIS_STATUS_MULTICAST_EXISTS ((uint)0xC001000AL) -#define NDIS_STATUS_MULTICAST_NOT_FOUND ((uint)0xC001000BL) -#define NDIS_STATUS_REQUEST_ABORTED ((uint)0xC001000CL) -#define NDIS_STATUS_RESET_IN_PROGRESS ((uint)0xC001000DL) -#define NDIS_STATUS_CLOSING_INDICATING ((uint)0xC001000EL) -#define NDIS_STATUS_NOT_SUPPORTED ((uint)STATUS_NOT_SUPPORTED) -#define NDIS_STATUS_INVALID_PACKET ((uint)0xC001000FL) -#define NDIS_STATUS_OPEN_LIST_FULL ((uint)0xC0010010L) -#define NDIS_STATUS_ADAPTER_NOT_READY ((uint)0xC0010011L) -#define NDIS_STATUS_ADAPTER_NOT_OPEN ((uint)0xC0010012L) -#define NDIS_STATUS_NOT_INDICATING ((uint)0xC0010013L) -#define NDIS_STATUS_INVALID_LENGTH ((uint)0xC0010014L) -#define NDIS_STATUS_INVALID_DATA ((uint)0xC0010015L) -#define NDIS_STATUS_BUFFER_TOO_SHORT ((uint)0xC0010016L) -#define NDIS_STATUS_INVALID_OID ((uint)0xC0010017L) -#define NDIS_STATUS_ADAPTER_REMOVED ((uint)0xC0010018L) -#define NDIS_STATUS_UNSUPPORTED_MEDIA ((uint)0xC0010019L) -#define NDIS_STATUS_GROUP_ADDRESS_IN_USE ((uint)0xC001001AL) -#define NDIS_STATUS_FILE_NOT_FOUND ((uint)0xC001001BL) -#define NDIS_STATUS_ERROR_READING_FILE ((uint)0xC001001CL) -#define NDIS_STATUS_ALREADY_MAPPED ((uint)0xC001001DL) -#define NDIS_STATUS_RESOURCE_CONFLICT ((uint)0xC001001EL) -#define NDIS_STATUS_NO_CABLE ((uint)0xC001001FL) - -#define NDIS_STATUS_INVALID_SAP ((uint)0xC0010020L) -#define NDIS_STATUS_SAP_IN_USE ((uint)0xC0010021L) -#define NDIS_STATUS_INVALID_ADDRESS ((uint)0xC0010022L) -#define NDIS_STATUS_VC_NOT_ACTIVATED ((uint)0xC0010023L) -#define NDIS_STATUS_DEST_OUT_OF_ORDER ((uint)0xC0010024L) /* cause 27 */ -#define NDIS_STATUS_VC_NOT_AVAILABLE ((uint)0xC0010025L) /* cause 35, 45 */ -#define NDIS_STATUS_CELLRATE_NOT_AVAILABLE ((uint)0xC0010026L) /* cause 37 */ -#define NDIS_STATUS_INCOMPATABLE_QOS ((uint)0xC0010027L) /* cause 49 */ -#define NDIS_STATUS_AAL_PARAMS_UNSUPPORTED ((uint)0xC0010028L) /* cause 93 */ -#define NDIS_STATUS_NO_ROUTE_TO_DESTINATION ((uint)0xC0010029L) /* cause 3 */ - -extern struct iw_handler_def rtw_handlers_def; - -#endif /* #ifndef __INC_CEINFO_ */ diff --git a/drivers/staging/rtl8723bs/include/rtw_mlme.h b/drivers/staging/rtl8723bs/include/rtw_mlme.h index c94fa7d8d5a9..1b343b434f4d 100644 --- a/drivers/staging/rtl8723bs/include/rtw_mlme.h +++ b/drivers/staging/rtl8723bs/include/rtw_mlme.h @@ -102,13 +102,17 @@ there are several "locks" in mlme_priv, since mlme_priv is a shared resource between many threads, like ISR/Call-Back functions, the OID handlers, and even timer functions. - Each struct __queue has its own locks, already. -Other items are protected by mlme_priv.lock. +Other items in mlme_priv are protected by mlme_priv.lock, while items in +xmit_priv are protected by xmit_priv.lock. To avoid possible dead lock, any thread trying to modifiying mlme_priv SHALL not lock up more than one locks at a time! +The only exception is that queue functions which take the __queue.lock +may be called with the xmit_priv.lock held. In this case the order +MUST always be first lock xmit_priv.lock and then call any queue functions +which take __queue.lock. */ diff --git a/drivers/staging/rtl8723bs/include/rtw_mlme_ext.h b/drivers/staging/rtl8723bs/include/rtw_mlme_ext.h index 89b389d4c44b..65e138a5238f 100644 --- a/drivers/staging/rtl8723bs/include/rtw_mlme_ext.h +++ b/drivers/staging/rtl8723bs/include/rtw_mlme_ext.h @@ -662,7 +662,6 @@ extern void adaptive_early_32k(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint extern u8 traffic_status_watchdog(struct adapter *padapter, u8 from_timer); int rtw_chk_start_clnt_join(struct adapter *padapter, u8 *ch, u8 *bw, u8 *offset); -int rtw_get_ch_setting_union(struct adapter *adapter, u8 *ch, u8 *bw, u8 *offset); struct cmd_hdl { uint parmsize; diff --git a/drivers/staging/rtl8723bs/include/rtw_odm.h b/drivers/staging/rtl8723bs/include/rtw_odm.h deleted file mode 100644 index 94fc68a5c424..000000000000 --- a/drivers/staging/rtl8723bs/include/rtw_odm.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/****************************************************************************** - * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. - * - ******************************************************************************/ -#ifndef __RTW_ODM_H__ -#define __RTW_ODM_H__ - -#include <drv_types.h> - -/* -* This file provides utilities/wrappers for rtw driver to use ODM -*/ - -void rtw_odm_dbg_comp_msg(struct adapter *adapter); -void rtw_odm_dbg_comp_set(struct adapter *adapter, u64 comps); -void rtw_odm_dbg_level_msg(void *sel, struct adapter *adapter); -void rtw_odm_dbg_level_set(struct adapter *adapter, u32 level); - -void rtw_odm_ability_msg(void *sel, struct adapter *adapter); -void rtw_odm_ability_set(struct adapter *adapter, u32 ability); - -void rtw_odm_adaptivity_parm_msg(void *sel, struct adapter *adapter); -void rtw_odm_adaptivity_parm_set(struct adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff, - s8 IGI_Base, bool ForceEDCCA, u8 AdapEn_RSSI, u8 IGI_LowerBound); -void rtw_odm_get_perpkt_rssi(void *sel, struct adapter *adapter); -#endif /* __RTW_ODM_H__ */ diff --git a/drivers/staging/rtl8723bs/include/rtw_recv.h b/drivers/staging/rtl8723bs/include/rtw_recv.h index a88b7c088a86..44f67103503a 100644 --- a/drivers/staging/rtl8723bs/include/rtw_recv.h +++ b/drivers/staging/rtl8723bs/include/rtw_recv.h @@ -385,17 +385,6 @@ static inline u8 *get_rxmem(union recv_frame *precvframe) return precvframe->u.hdr.rx_head; } -static inline u8 *get_recvframe_data(union recv_frame *precvframe) -{ - - /* alwasy return rx_data */ - if (precvframe == NULL) - return NULL; - - return precvframe->u.hdr.rx_data; - -} - static inline u8 *recvframe_pull(union recv_frame *precvframe, signed int sz) { /* rx_data += sz; move rx_data sz bytes hereafter */ diff --git a/drivers/staging/rtl8723bs/include/xmit_osdep.h b/drivers/staging/rtl8723bs/include/xmit_osdep.h index e781cd5dfd01..8704dced593a 100644 --- a/drivers/staging/rtl8723bs/include/xmit_osdep.h +++ b/drivers/staging/rtl8723bs/include/xmit_osdep.h @@ -25,8 +25,8 @@ struct sta_xmit_priv; struct xmit_frame; struct xmit_buf; -extern int _rtw_xmit_entry(struct sk_buff *pkt, struct net_device *pnetdev); -extern int rtw_xmit_entry(struct sk_buff *pkt, struct net_device *pnetdev); +extern void _rtw_xmit_entry(struct sk_buff *pkt, struct net_device *pnetdev); +extern netdev_tx_t rtw_xmit_entry(struct sk_buff *pkt, struct net_device *pnetdev); void rtw_os_xmit_schedule(struct adapter *padapter); |