diff options
Diffstat (limited to 'drivers/staging/sm750fb/ddk750_mode.c')
| -rw-r--r-- | drivers/staging/sm750fb/ddk750_mode.c | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/drivers/staging/sm750fb/ddk750_mode.c b/drivers/staging/sm750fb/ddk750_mode.c index 4a4b1de97a87..1df7d57dea6d 100644 --- a/drivers/staging/sm750fb/ddk750_mode.c +++ b/drivers/staging/sm750fb/ddk750_mode.c @@ -25,9 +25,9 @@ static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam, * Note that normal SM750/SM718 only use those two register for * auto-centering mode. */ - POKE32(CRT_AUTO_CENTERING_TL, 0); + poke32(CRT_AUTO_CENTERING_TL, 0); - POKE32(CRT_AUTO_CENTERING_BR, + poke32(CRT_AUTO_CENTERING_BR, (((y - 1) << CRT_AUTO_CENTERING_BR_BOTTOM_SHIFT) & CRT_AUTO_CENTERING_BR_BOTTOM_MASK) | ((x - 1) & CRT_AUTO_CENTERING_BR_RIGHT_MASK)); @@ -66,7 +66,7 @@ static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam, /* Set bit 14 of display controller */ dispControl |= DISPLAY_CTRL_CLOCK_PHASE; - POKE32(CRT_DISPLAY_CTRL, dispControl); + poke32(CRT_DISPLAY_CTRL, dispControl); return dispControl; } @@ -83,29 +83,29 @@ static int programModeRegisters(mode_parameter_t *pModeParam, if (pll->clockType == SECONDARY_PLL) { /* programe secondary pixel clock */ - POKE32(CRT_PLL_CTRL, sm750_format_pll_reg(pll)); - POKE32(CRT_HORIZONTAL_TOTAL, + poke32(CRT_PLL_CTRL, sm750_format_pll_reg(pll)); + poke32(CRT_HORIZONTAL_TOTAL, (((pModeParam->horizontal_total - 1) << CRT_HORIZONTAL_TOTAL_TOTAL_SHIFT) & CRT_HORIZONTAL_TOTAL_TOTAL_MASK) | ((pModeParam->horizontal_display_end - 1) & CRT_HORIZONTAL_TOTAL_DISPLAY_END_MASK)); - POKE32(CRT_HORIZONTAL_SYNC, + poke32(CRT_HORIZONTAL_SYNC, ((pModeParam->horizontal_sync_width << CRT_HORIZONTAL_SYNC_WIDTH_SHIFT) & CRT_HORIZONTAL_SYNC_WIDTH_MASK) | ((pModeParam->horizontal_sync_start - 1) & CRT_HORIZONTAL_SYNC_START_MASK)); - POKE32(CRT_VERTICAL_TOTAL, + poke32(CRT_VERTICAL_TOTAL, (((pModeParam->vertical_total - 1) << CRT_VERTICAL_TOTAL_TOTAL_SHIFT) & CRT_VERTICAL_TOTAL_TOTAL_MASK) | ((pModeParam->vertical_display_end - 1) & CRT_VERTICAL_TOTAL_DISPLAY_END_MASK)); - POKE32(CRT_VERTICAL_SYNC, + poke32(CRT_VERTICAL_SYNC, ((pModeParam->vertical_sync_height << CRT_VERTICAL_SYNC_HEIGHT_SHIFT) & CRT_VERTICAL_SYNC_HEIGHT_MASK) | @@ -122,41 +122,41 @@ static int programModeRegisters(mode_parameter_t *pModeParam, if (sm750_get_chip_type() == SM750LE) { displayControlAdjust_SM750LE(pModeParam, tmp); } else { - reg = PEEK32(CRT_DISPLAY_CTRL) & + reg = peek32(CRT_DISPLAY_CTRL) & ~(DISPLAY_CTRL_VSYNC_PHASE | DISPLAY_CTRL_HSYNC_PHASE | DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE); - POKE32(CRT_DISPLAY_CTRL, tmp | reg); + poke32(CRT_DISPLAY_CTRL, tmp | reg); } } else if (pll->clockType == PRIMARY_PLL) { unsigned int reserved; - POKE32(PANEL_PLL_CTRL, sm750_format_pll_reg(pll)); + poke32(PANEL_PLL_CTRL, sm750_format_pll_reg(pll)); reg = ((pModeParam->horizontal_total - 1) << PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT) & PANEL_HORIZONTAL_TOTAL_TOTAL_MASK; reg |= ((pModeParam->horizontal_display_end - 1) & PANEL_HORIZONTAL_TOTAL_DISPLAY_END_MASK); - POKE32(PANEL_HORIZONTAL_TOTAL, reg); + poke32(PANEL_HORIZONTAL_TOTAL, reg); - POKE32(PANEL_HORIZONTAL_SYNC, + poke32(PANEL_HORIZONTAL_SYNC, ((pModeParam->horizontal_sync_width << PANEL_HORIZONTAL_SYNC_WIDTH_SHIFT) & PANEL_HORIZONTAL_SYNC_WIDTH_MASK) | ((pModeParam->horizontal_sync_start - 1) & PANEL_HORIZONTAL_SYNC_START_MASK)); - POKE32(PANEL_VERTICAL_TOTAL, + poke32(PANEL_VERTICAL_TOTAL, (((pModeParam->vertical_total - 1) << PANEL_VERTICAL_TOTAL_TOTAL_SHIFT) & PANEL_VERTICAL_TOTAL_TOTAL_MASK) | ((pModeParam->vertical_display_end - 1) & PANEL_VERTICAL_TOTAL_DISPLAY_END_MASK)); - POKE32(PANEL_VERTICAL_SYNC, + poke32(PANEL_VERTICAL_SYNC, ((pModeParam->vertical_sync_height << PANEL_VERTICAL_SYNC_HEIGHT_SHIFT) & PANEL_VERTICAL_SYNC_HEIGHT_MASK) | @@ -174,7 +174,7 @@ static int programModeRegisters(mode_parameter_t *pModeParam, reserved = PANEL_DISPLAY_CTRL_RESERVED_MASK | PANEL_DISPLAY_CTRL_VSYNC; - reg = (PEEK32(PANEL_DISPLAY_CTRL) & ~reserved) & + reg = (peek32(PANEL_DISPLAY_CTRL) & ~reserved) & ~(DISPLAY_CTRL_CLOCK_PHASE | DISPLAY_CTRL_VSYNC_PHASE | DISPLAY_CTRL_HSYNC_PHASE | DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE); @@ -187,14 +187,14 @@ static int programModeRegisters(mode_parameter_t *pModeParam, * Note: This problem happens by design. The hardware will wait * for the next vertical sync to turn on/off the plane. */ - POKE32(PANEL_DISPLAY_CTRL, tmp | reg); + poke32(PANEL_DISPLAY_CTRL, tmp | reg); - while ((PEEK32(PANEL_DISPLAY_CTRL) & ~reserved) != + while ((peek32(PANEL_DISPLAY_CTRL) & ~reserved) != (tmp | reg)) { cnt++; if (cnt > 1000) break; - POKE32(PANEL_DISPLAY_CTRL, tmp | reg); + poke32(PANEL_DISPLAY_CTRL, tmp | reg); } } else { ret = -1; |