diff options
Diffstat (limited to 'drivers/staging/vme/bridges/vme_tsi148.c')
| -rw-r--r-- | drivers/staging/vme/bridges/vme_tsi148.c | 1010 |
1 files changed, 383 insertions, 627 deletions
diff --git a/drivers/staging/vme/bridges/vme_tsi148.c b/drivers/staging/vme/bridges/vme_tsi148.c index 89a7dccb934f..faf652edb70f 100644 --- a/drivers/staging/vme/bridges/vme_tsi148.c +++ b/drivers/staging/vme/bridges/vme_tsi148.c @@ -1,8 +1,8 @@ /* * Support for the Tundra TSI148 VME-PCI Bridge Chip * - * Author: Martyn Welch <martyn.welch@gefanuc.com> - * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc. + * Author: Martyn Welch <martyn.welch@ge.com> + * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc. * * Based on work by Tom Armistead and Ajit Prem * Copyright 2004 Motorola Inc. @@ -59,28 +59,14 @@ int tsi148_dma_list_add (struct vme_dma_list *, struct vme_dma_attr *, int tsi148_dma_list_exec(struct vme_dma_list *); int tsi148_dma_list_empty(struct vme_dma_list *); int tsi148_generate_irq(int, int); -int tsi148_slot_get(void); - -/* Modue parameter */ -int err_chk = 0; - -/* XXX These should all be in a per device structure */ -struct vme_bridge *tsi148_bridge; -wait_queue_head_t dma_queue[2]; -wait_queue_head_t iack_queue; -void (*lm_callback[4])(int); /* Called in interrupt handler, be careful! */ -void *crcsr_kernel; -dma_addr_t crcsr_bus; -struct vme_master_resource *flush_image; -struct mutex vme_rmw; /* Only one RMW cycle at a time */ -struct mutex vme_int; /* - * Only one VME interrupt can be - * generated at a time, provide locking - */ + +/* Module parameter */ +static int err_chk; +static int geoid; static char driver_name[] = "vme_tsi148"; -static struct pci_device_id tsi148_ids[] = { +static const struct pci_device_id tsi148_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) }, { }, }; @@ -109,16 +95,17 @@ static void reg_split(unsigned long long variable, unsigned int *high, /* * Wakes up DMA queue. */ -static u32 tsi148_DMA_irqhandler(int channel_mask) +static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge, + int channel_mask) { u32 serviced = 0; if (channel_mask & TSI148_LCSR_INTS_DMA0S) { - wake_up(&dma_queue[0]); + wake_up(&(bridge->dma_queue[0])); serviced |= TSI148_LCSR_INTC_DMA0C; } if (channel_mask & TSI148_LCSR_INTS_DMA1S) { - wake_up(&dma_queue[1]); + wake_up(&(bridge->dma_queue[1])); serviced |= TSI148_LCSR_INTC_DMA1C; } @@ -128,7 +115,7 @@ static u32 tsi148_DMA_irqhandler(int channel_mask) /* * Wake up location monitor queue */ -static u32 tsi148_LM_irqhandler(u32 stat) +static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat) { int i; u32 serviced = 0; @@ -136,7 +123,7 @@ static u32 tsi148_LM_irqhandler(u32 stat) for (i = 0; i < 4; i++) { if(stat & TSI148_LCSR_INTS_LMS[i]) { /* We only enable interrupts if the callback is set */ - lm_callback[i](i); + bridge->lm_callback[i](i); serviced |= TSI148_LCSR_INTC_LMC[i]; } } @@ -149,7 +136,7 @@ static u32 tsi148_LM_irqhandler(u32 stat) * * XXX This functionality is not exposed up though API. */ -static u32 tsi148_MB_irqhandler(u32 stat) +static u32 tsi148_MB_irqhandler(struct tsi148_driver *bridge, u32 stat) { int i; u32 val; @@ -157,8 +144,7 @@ static u32 tsi148_MB_irqhandler(u32 stat) for (i = 0; i < 4; i++) { if(stat & TSI148_LCSR_INTS_MBS[i]) { - val = ioread32be(tsi148_bridge->base + - TSI148_GCSR_MBOX[i]); + val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]); printk("VME Mailbox %d received: 0x%x\n", i, val); serviced |= TSI148_LCSR_INTC_MBC[i]; } @@ -170,22 +156,21 @@ static u32 tsi148_MB_irqhandler(u32 stat) /* * Display error & status message when PERR (PCI) exception interrupt occurs. */ -static u32 tsi148_PERR_irqhandler(void) +static u32 tsi148_PERR_irqhandler(struct tsi148_driver *bridge) { printk(KERN_ERR "PCI Exception at address: 0x%08x:%08x, attributes: %08x\n", - ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPAU), - ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPAL), - ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPAT) + ioread32be(bridge->base + TSI148_LCSR_EDPAU), + ioread32be(bridge->base + TSI148_LCSR_EDPAL), + ioread32be(bridge->base + TSI148_LCSR_EDPAT) ); printk(KERN_ERR "PCI-X attribute reg: %08x, PCI-X split completion reg: %08x\n", - ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPXA), - ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPXS) + ioread32be(bridge->base + TSI148_LCSR_EDPXA), + ioread32be(bridge->base + TSI148_LCSR_EDPXS) ); - iowrite32be(TSI148_LCSR_EDPAT_EDPCL, - tsi148_bridge->base + TSI148_LCSR_EDPAT); + iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT); return TSI148_LCSR_INTC_PERRC; } @@ -193,16 +178,19 @@ static u32 tsi148_PERR_irqhandler(void) /* * Save address and status when VME error interrupt occurs. */ -static u32 tsi148_VERR_irqhandler(void) +static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge) { unsigned int error_addr_high, error_addr_low; unsigned long long error_addr; u32 error_attrib; struct vme_bus_error *error; + struct tsi148_driver *bridge; + + bridge = tsi148_bridge->driver_priv; - error_addr_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_VEAU); - error_addr_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_VEAL); - error_attrib = ioread32be(tsi148_bridge->base + TSI148_LCSR_VEAT); + error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU); + error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL); + error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT); reg_join(error_addr_high, error_addr_low, &error_addr); @@ -226,8 +214,7 @@ static u32 tsi148_VERR_irqhandler(void) } /* Clear Status */ - iowrite32be(TSI148_LCSR_VEAT_VESCL, - tsi148_bridge->base + TSI148_LCSR_VEAT); + iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT); return TSI148_LCSR_INTC_VERRC; } @@ -235,9 +222,9 @@ static u32 tsi148_VERR_irqhandler(void) /* * Wake up IACK queue. */ -static u32 tsi148_IACK_irqhandler(void) +static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge) { - wake_up(&iack_queue); + wake_up(&(bridge->iack_queue)); return TSI148_LCSR_INTC_IACKC; } @@ -245,9 +232,13 @@ static u32 tsi148_IACK_irqhandler(void) /* * Calling VME bus interrupt callback if provided. */ -static u32 tsi148_VIRQ_irqhandler(u32 stat) +static u32 tsi148_VIRQ_irqhandler(struct vme_bridge *tsi148_bridge, + u32 stat) { int vec, i, serviced = 0; + struct tsi148_driver *bridge; + + bridge = tsi148_bridge->driver_priv; for (i = 7; i > 0; i--) { if (stat & (1 << i)) { @@ -257,8 +248,7 @@ static u32 tsi148_VIRQ_irqhandler(u32 stat) * 8-bit IACK cycles on the bus, read from offset * 3. */ - vec = ioread8(tsi148_bridge->base + - TSI148_LCSR_VIACK[i] + 3); + vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3); vme_irq_handler(tsi148_bridge, i, vec); @@ -273,13 +263,19 @@ static u32 tsi148_VIRQ_irqhandler(u32 stat) * Top level interrupt handler. Clears appropriate interrupt status bits and * then calls appropriate sub handler(s). */ -static irqreturn_t tsi148_irqhandler(int irq, void *dev_id) +static irqreturn_t tsi148_irqhandler(int irq, void *ptr) { u32 stat, enable, serviced = 0; + struct vme_bridge *tsi148_bridge; + struct tsi148_driver *bridge; + + tsi148_bridge = ptr; + + bridge = tsi148_bridge->driver_priv; /* Determine which interrupts are unmasked and set */ - enable = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO); - stat = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTS); + enable = ioread32be(bridge->base + TSI148_LCSR_INTEO); + stat = ioread32be(bridge->base + TSI148_LCSR_INTS); /* Only look at unmasked interrupts */ stat &= enable; @@ -291,61 +287,63 @@ static irqreturn_t tsi148_irqhandler(int irq, void *dev_id) /* Call subhandlers as appropriate */ /* DMA irqs */ if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S)) - serviced |= tsi148_DMA_irqhandler(stat); + serviced |= tsi148_DMA_irqhandler(bridge, stat); /* Location monitor irqs */ if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S)) - serviced |= tsi148_LM_irqhandler(stat); + serviced |= tsi148_LM_irqhandler(bridge, stat); /* Mail box irqs */ if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S | TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S)) - serviced |= tsi148_MB_irqhandler(stat); + serviced |= tsi148_MB_irqhandler(bridge, stat); /* PCI bus error */ if (stat & TSI148_LCSR_INTS_PERRS) - serviced |= tsi148_PERR_irqhandler(); + serviced |= tsi148_PERR_irqhandler(bridge); /* VME bus error */ if (stat & TSI148_LCSR_INTS_VERRS) - serviced |= tsi148_VERR_irqhandler(); + serviced |= tsi148_VERR_irqhandler(tsi148_bridge); /* IACK irq */ if (stat & TSI148_LCSR_INTS_IACKS) - serviced |= tsi148_IACK_irqhandler(); + serviced |= tsi148_IACK_irqhandler(bridge); /* VME bus irqs */ if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S | TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S | TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S | TSI148_LCSR_INTS_IRQ1S)) - serviced |= tsi148_VIRQ_irqhandler(stat); + serviced |= tsi148_VIRQ_irqhandler(tsi148_bridge, stat); /* Clear serviced interrupts */ - iowrite32be(serviced, tsi148_bridge->base + TSI148_LCSR_INTC); + iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC); return IRQ_HANDLED; } -static int tsi148_irq_init(struct vme_bridge *bridge) +static int tsi148_irq_init(struct vme_bridge *tsi148_bridge) { int result; unsigned int tmp; struct pci_dev *pdev; + struct tsi148_driver *bridge; + + pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev); - /* Need pdev */ - pdev = container_of(bridge->parent, struct pci_dev, dev); + bridge = tsi148_bridge->driver_priv; /* Initialise list for VME bus errors */ - INIT_LIST_HEAD(&(bridge->vme_errors)); + INIT_LIST_HEAD(&(tsi148_bridge->vme_errors)); - mutex_init(&(bridge->irq_mtx)); + mutex_init(&(tsi148_bridge->irq_mtx)); result = request_irq(pdev->irq, tsi148_irqhandler, IRQF_SHARED, - driver_name, pdev); + driver_name, tsi148_bridge); if (result) { dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n", pdev->irq); @@ -359,7 +357,7 @@ static int tsi148_irq_init(struct vme_bridge *bridge) TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO | TSI148_LCSR_INTEO_IACKEO; - /* XXX This leaves the following interrupts masked. + /* This leaves the following interrupts masked. * TSI148_LCSR_INTEO_VIEEO * TSI148_LCSR_INTEO_SYSFLEO * TSI148_LCSR_INTEO_ACFLEO @@ -392,14 +390,14 @@ static int tsi148_irq_init(struct vme_bridge *bridge) return 0; } -static void tsi148_irq_exit(struct pci_dev *pdev) +static void tsi148_irq_exit(struct tsi148_driver *bridge, struct pci_dev *pdev) { /* Turn off interrupts */ - iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTEO); - iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTEN); + iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO); + iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN); /* Clear all interrupts */ - iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_INTC); + iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC); /* Detach interrupt handler */ free_irq(pdev->irq, pdev); @@ -408,11 +406,11 @@ static void tsi148_irq_exit(struct pci_dev *pdev) /* * Check to see if an IACk has been received, return true (1) or false (0). */ -int tsi148_iack_received(void) +int tsi148_iack_received(struct tsi148_driver *bridge) { u32 tmp; - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VICR); + tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); if (tmp & TSI148_LCSR_VICR_IRQS) return 0; @@ -423,20 +421,24 @@ int tsi148_iack_received(void) /* * Configure VME interrupt */ -void tsi148_irq_set(int level, int state, int sync) +void tsi148_irq_set(struct vme_bridge *tsi148_bridge, int level, + int state, int sync) { struct pci_dev *pdev; u32 tmp; + struct tsi148_driver *bridge; + + bridge = tsi148_bridge->driver_priv; /* We need to do the ordering differently for enabling and disabling */ if (state == 0) { - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN); + tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1]; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEN); + iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO); + tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1]; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO); + iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); if (sync != 0) { pdev = container_of(tsi148_bridge->parent, @@ -445,13 +447,13 @@ void tsi148_irq_set(int level, int state, int sync) synchronize_irq(pdev->irq); } } else { - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO); + tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1]; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO); + iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN); + tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1]; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEN); + iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); } } @@ -459,28 +461,32 @@ void tsi148_irq_set(int level, int state, int sync) * Generate a VME bus interrupt at the requested level & vector. Wait for * interrupt to be acked. */ -int tsi148_irq_generate(int level, int statid) +int tsi148_irq_generate(struct vme_bridge *tsi148_bridge, int level, int statid) { u32 tmp; + struct tsi148_driver *bridge; + + bridge = tsi148_bridge->driver_priv; - mutex_lock(&(vme_int)); + mutex_lock(&(bridge->vme_int)); /* Read VICR register */ - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VICR); + tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); /* Set Status/ID */ tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) | (statid & TSI148_LCSR_VICR_STID_M); - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VICR); + iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR); /* Assert VMEbus IRQ */ tmp = tmp | TSI148_LCSR_VICR_IRQL[level]; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VICR); + iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR); /* XXX Consider implementing a timeout? */ - wait_event_interruptible(iack_queue, tsi148_iack_received()); + wait_event_interruptible(bridge->iack_queue, + tsi148_iack_received(bridge)); - mutex_unlock(&(vme_int)); + mutex_unlock(&(bridge->vme_int)); return 0; } @@ -488,8 +494,8 @@ int tsi148_irq_generate(int level, int statid) /* * Find the first error in this address range */ -static struct vme_bus_error *tsi148_find_error(vme_address_t aspace, - unsigned long long address, size_t count) +static struct vme_bus_error *tsi148_find_error(struct vme_bridge *tsi148_bridge, + vme_address_t aspace, unsigned long long address, size_t count) { struct list_head *err_pos; struct vme_bus_error *vme_err, *valid = NULL; @@ -520,8 +526,8 @@ static struct vme_bus_error *tsi148_find_error(vme_address_t aspace, /* * Clear errors in the provided address range. */ -static void tsi148_clear_errors(vme_address_t aspace, - unsigned long long address, size_t count) +static void tsi148_clear_errors(struct vme_bridge *tsi148_bridge, + vme_address_t aspace, unsigned long long address, size_t count) { struct list_head *err_pos, *temp; struct vme_bus_error *vme_err; @@ -561,16 +567,9 @@ int tsi148_slave_set(struct vme_slave_resource *image, int enabled, unsigned int vme_bound_low, vme_bound_high; unsigned int pci_offset_low, pci_offset_high; unsigned long long vme_bound, pci_offset; + struct tsi148_driver *bridge; -#if 0 - printk("Set slave image %d to:\n", image->number); - printk("\tEnabled: %s\n", (enabled == 1)? "yes" : "no"); - printk("\tVME Base:0x%llx\n", vme_base); - printk("\tWindow Size:0x%llx\n", size); - printk("\tPCI Base:0x%lx\n", (unsigned long)pci_base); - printk("\tAddress Space:0x%x\n", aspace); - printk("\tTransfer Cycle Properties:0x%x\n", cycle); -#endif + bridge = image->parent->driver_priv; i = image->number; @@ -627,49 +626,27 @@ int tsi148_slave_set(struct vme_slave_resource *image, int enabled, return -EINVAL; } -#if 0 - printk("\tVME Bound:0x%llx\n", vme_bound); - printk("\tPCI Offset:0x%llx\n", pci_offset); -#endif - /* Disable while we are mucking around */ - temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] + + temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITAT); temp_ctl &= ~TSI148_LCSR_ITAT_EN; - iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_IT[i] + + iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITAT); /* Setup mapping */ - iowrite32be(vme_base_high, tsi148_bridge->base + TSI148_LCSR_IT[i] + + iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITSAU); - iowrite32be(vme_base_low, tsi148_bridge->base + TSI148_LCSR_IT[i] + + iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITSAL); - iowrite32be(vme_bound_high, tsi148_bridge->base + TSI148_LCSR_IT[i] + + iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITEAU); - iowrite32be(vme_bound_low, tsi148_bridge->base + TSI148_LCSR_IT[i] + + iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITEAL); - iowrite32be(pci_offset_high, tsi148_bridge->base + TSI148_LCSR_IT[i] + + iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITOFU); - iowrite32be(pci_offset_low, tsi148_bridge->base + TSI148_LCSR_IT[i] + + iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITOFL); -/* XXX Prefetch stuff currently unsupported */ -#if 0 - - for (x = 0; x < 4; x++) { - if ((64 << x) >= vmeIn->prefetchSize) { - break; - } - } - if (x == 4) - x--; - temp_ctl |= (x << 16); - - if (vmeIn->prefetchThreshold) - if (vmeIn->prefetchThreshold) - temp_ctl |= 0x40000; -#endif - /* Setup 2eSST speeds */ temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M; switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { @@ -712,13 +689,13 @@ int tsi148_slave_set(struct vme_slave_resource *image, int enabled, temp_ctl |= TSI148_LCSR_ITAT_DATA; /* Write ctl reg without enable */ - iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_IT[i] + + iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITAT); if (enabled) temp_ctl |= TSI148_LCSR_ITAT_EN; - iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_IT[i] + + iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITAT); return 0; @@ -726,8 +703,6 @@ int tsi148_slave_set(struct vme_slave_resource *image, int enabled, /* * Get slave window configuration. - * - * XXX Prefetch currently unsupported. */ int tsi148_slave_get(struct vme_slave_resource *image, int *enabled, unsigned long long *vme_base, unsigned long long *size, @@ -738,25 +713,27 @@ int tsi148_slave_get(struct vme_slave_resource *image, int *enabled, unsigned int vme_bound_low, vme_bound_high; unsigned int pci_offset_low, pci_offset_high; unsigned long long vme_bound, pci_offset; + struct tsi148_driver *bridge; + bridge = image->parent->driver_priv; i = image->number; /* Read registers */ - ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] + + ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITAT); - vme_base_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] + + vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITSAU); - vme_base_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] + + vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITSAL); - vme_bound_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] + + vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITEAU); - vme_bound_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] + + vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITEAL); - pci_offset_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] + + pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITOFU); - pci_offset_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] + + pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITOFL); /* Convert 64-bit variables to 2x 32-bit variables */ @@ -833,6 +810,9 @@ static int tsi148_alloc_resource(struct vme_master_resource *image, unsigned long long existing_size; int retval = 0; struct pci_dev *pdev; + struct vme_bridge *tsi148_bridge; + + tsi148_bridge = image->parent; /* Find pci_dev container of dev */ if (tsi148_bridge->parent == NULL) { @@ -841,8 +821,8 @@ static int tsi148_alloc_resource(struct vme_master_resource *image, } pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev); - existing_size = (unsigned long long)(image->pci_resource.end - - image->pci_resource.start); + existing_size = (unsigned long long)(image->bus_resource.end - + image->bus_resource.start); /* If the existing size is OK, return */ if ((size != 0) && (existing_size == (size - 1))) @@ -851,10 +831,10 @@ static int tsi148_alloc_resource(struct vme_master_resource *image, if (existing_size != 0) { iounmap(image->kern_base); image->kern_base = NULL; - if (image->pci_resource.name != NULL) - kfree(image->pci_resource.name); - release_resource(&(image->pci_resource)); - memset(&(image->pci_resource), 0, sizeof(struct resource)); + if (image->bus_resource.name != NULL) + kfree(image->bus_resource.name); + release_resource(&(image->bus_resource)); + memset(&(image->bus_resource), 0, sizeof(struct resource)); } /* Exit here if size is zero */ @@ -862,9 +842,9 @@ static int tsi148_alloc_resource(struct vme_master_resource *image, return 0; } - if (image->pci_resource.name == NULL) { - image->pci_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL); - if (image->pci_resource.name == NULL) { + if (image->bus_resource.name == NULL) { + image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL); + if (image->bus_resource.name == NULL) { printk(KERN_ERR "Unable to allocate memory for resource" " name\n"); retval = -ENOMEM; @@ -872,26 +852,26 @@ static int tsi148_alloc_resource(struct vme_master_resource *image, } } - sprintf((char *)image->pci_resource.name, "%s.%d", tsi148_bridge->name, + sprintf((char *)image->bus_resource.name, "%s.%d", tsi148_bridge->name, image->number); - image->pci_resource.start = 0; - image->pci_resource.end = (unsigned long)size; - image->pci_resource.flags = IORESOURCE_MEM; + image->bus_resource.start = 0; + image->bus_resource.end = (unsigned long)size; + image->bus_resource.flags = IORESOURCE_MEM; retval = pci_bus_alloc_resource(pdev->bus, - &(image->pci_resource), size, size, PCIBIOS_MIN_MEM, + &(image->bus_resource), size, size, PCIBIOS_MIN_MEM, 0, NULL, NULL); if (retval) { printk(KERN_ERR "Failed to allocate mem resource for " "window %d size 0x%lx start 0x%lx\n", image->number, (unsigned long)size, - (unsigned long)image->pci_resource.start); + (unsigned long)image->bus_resource.start); goto err_resource; } image->kern_base = ioremap_nocache( - image->pci_resource.start, size); + image->bus_resource.start, size); if (image->kern_base == NULL) { printk(KERN_ERR "Failed to remap resource\n"); retval = -ENOMEM; @@ -903,10 +883,10 @@ static int tsi148_alloc_resource(struct vme_master_resource *image, iounmap(image->kern_base); image->kern_base = NULL; err_remap: - release_resource(&(image->pci_resource)); + release_resource(&(image->bus_resource)); err_resource: - kfree(image->pci_resource.name); - memset(&(image->pci_resource), 0, sizeof(struct resource)); + kfree(image->bus_resource.name); + memset(&(image->bus_resource), 0, sizeof(struct resource)); err_name: return retval; } @@ -918,9 +898,9 @@ static void tsi148_free_resource(struct vme_master_resource *image) { iounmap(image->kern_base); image->kern_base = NULL; - release_resource(&(image->pci_resource)); - kfree(image->pci_resource.name); - memset(&(image->pci_resource), 0, sizeof(struct resource)); + release_resource(&(image->bus_resource)); + kfree(image->bus_resource.name); + memset(&(image->bus_resource), 0, sizeof(struct resource)); } /* @@ -937,6 +917,9 @@ int tsi148_master_set( struct vme_master_resource *image, int enabled, unsigned int pci_bound_low, pci_bound_high; unsigned int vme_offset_low, vme_offset_high; unsigned long long pci_bound, vme_offset, pci_base; + struct tsi148_driver *bridge; + + bridge = image->parent->driver_priv; /* Verify input data */ if (vme_base & 0xFFFF) { @@ -970,7 +953,7 @@ int tsi148_master_set( struct vme_master_resource *image, int enabled, pci_bound = 0; vme_offset = 0; } else { - pci_base = (unsigned long long)image->pci_resource.start; + pci_base = (unsigned long long)image->bus_resource.start; /* * Bound address is a valid address for the window, adjust @@ -1007,26 +990,12 @@ int tsi148_master_set( struct vme_master_resource *image, int enabled, i = image->number; /* Disable while we are mucking around */ - temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] + + temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTAT); temp_ctl &= ~TSI148_LCSR_OTAT_EN; - iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_OT[i] + + iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTAT); -/* XXX Prefetch stuff currently unsupported */ -#if 0 - if (vmeOut->prefetchEnable) { - temp_ctl |= 0x40000; - for (x = 0; x < 4; x++) { - if ((2 << x) >= vmeOut->prefetchSize) - break; - } - if (x == 4) - x = 3; - temp_ctl |= (x << 16); - } -#endif - /* Setup 2eSST speeds */ temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M; switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { @@ -1126,33 +1095,27 @@ int tsi148_master_set( struct vme_master_resource *image, int enabled, temp_ctl |= TSI148_LCSR_OTAT_PGM; /* Setup mapping */ - iowrite32be(pci_base_high, tsi148_bridge->base + TSI148_LCSR_OT[i] + + iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTSAU); - iowrite32be(pci_base_low, tsi148_bridge->base + TSI148_LCSR_OT[i] + + iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTSAL); - iowrite32be(pci_bound_high, tsi148_bridge->base + TSI148_LCSR_OT[i] + + iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTEAU); - iowrite32be(pci_bound_low, tsi148_bridge->base + TSI148_LCSR_OT[i] + + iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTEAL); - iowrite32be(vme_offset_high, tsi148_bridge->base + TSI148_LCSR_OT[i] + + iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTOFU); - iowrite32be(vme_offset_low, tsi148_bridge->base + TSI148_LCSR_OT[i] + + iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTOFL); -/* XXX We need to deal with OTBS */ -#if 0 - iowrite32be(vmeOut->bcastSelect2esst, tsi148_bridge->base + - TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTBS); -#endif - /* Write ctl reg without enable */ - iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_OT[i] + + iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTAT); if (enabled) temp_ctl |= TSI148_LCSR_OTAT_EN; - iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_OT[i] + + iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTAT); spin_unlock(&(image->lock)); @@ -1183,23 +1146,26 @@ int __tsi148_master_get( struct vme_master_resource *image, int *enabled, unsigned int vme_offset_low, vme_offset_high; unsigned long long pci_base, pci_bound, vme_offset; + struct tsi148_driver *bridge; + + bridge = image->parent->driver_priv; i = image->number; - ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] + + ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTAT); - pci_base_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] + + pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTSAU); - pci_base_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] + + pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTSAL); - pci_bound_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] + + pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTEAU); - pci_bound_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] + + pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTEAL); - vme_offset_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] + + vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTOFU); - vme_offset_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] + + vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTOFL); /* Convert 64-bit variables to 2x 32-bit variables */ @@ -1305,6 +1271,9 @@ ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf, vme_cycle_t cycle; vme_width_t dwidth; struct vme_bus_error *vme_err = NULL; + struct vme_bridge *tsi148_bridge; + + tsi148_bridge = image->parent; spin_lock(&(image->lock)); @@ -1317,13 +1286,15 @@ ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf, __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle, &dwidth); - vme_err = tsi148_find_error(aspace, vme_base + offset, count); + vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset, + count); if(vme_err != NULL) { dev_err(image->parent->parent, "First VME read error detected " "an at address 0x%llx\n", vme_err->address); retval = vme_err->address - (vme_base + offset); /* Clear down save errors in this address range */ - tsi148_clear_errors(aspace, vme_base + offset, count); + tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset, + count); } skip_chk: @@ -1333,9 +1304,6 @@ skip_chk: } -/* XXX We need to change vme_master_resource->mtx to a spinlock so that read - * and write functions can be used in an interrupt context - */ ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf, size_t count, loff_t offset) { @@ -1346,6 +1314,12 @@ ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf, vme_width_t dwidth; struct vme_bus_error *vme_err = NULL; + struct vme_bridge *tsi148_bridge; + struct tsi148_driver *bridge; + + tsi148_bridge = image->parent; + + bridge = tsi148_bridge->driver_priv; spin_lock(&(image->lock)); @@ -1373,15 +1347,17 @@ ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf, __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle, &dwidth); - ioread16(flush_image->kern_base + 0x7F000); + ioread16(bridge->flush_image->kern_base + 0x7F000); - vme_err = tsi148_find_error(aspace, vme_base + offset, count); + vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset, + count); if(vme_err != NULL) { printk("First VME write error detected an at address 0x%llx\n", vme_err->address); retval = vme_err->address - (vme_base + offset); /* Clear down save errors in this address range */ - tsi148_clear_errors(aspace, vme_base + offset, count); + tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset, + count); } skip_chk: @@ -1403,48 +1379,50 @@ unsigned int tsi148_master_rmw(struct vme_master_resource *image, unsigned int pci_addr_high, pci_addr_low; u32 tmp, result; int i; + struct tsi148_driver *bridge; + bridge = image->parent->driver_priv; /* Find the PCI address that maps to the desired VME address */ i = image->number; /* Locking as we can only do one of these at a time */ - mutex_lock(&(vme_rmw)); + mutex_lock(&(bridge->vme_rmw)); /* Lock image */ spin_lock(&(image->lock)); - pci_addr_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] + + pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTSAU); - pci_addr_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] + + pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTSAL); reg_join(pci_addr_high, pci_addr_low, &pci_addr); reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low); /* Configure registers */ - iowrite32be(mask, tsi148_bridge->base + TSI148_LCSR_RMWEN); - iowrite32be(compare, tsi148_bridge->base + TSI148_LCSR_RMWC); - iowrite32be(swap, tsi148_bridge->base + TSI148_LCSR_RMWS); - iowrite32be(pci_addr_high, tsi148_bridge->base + TSI148_LCSR_RMWAU); - iowrite32be(pci_addr_low, tsi148_bridge->base + TSI148_LCSR_RMWAL); + iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN); + iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC); + iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS); + iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU); + iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL); /* Enable RMW */ - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL); + tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL); tmp |= TSI148_LCSR_VMCTRL_RMWEN; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VMCTRL); + iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL); /* Kick process off with a read to the required address. */ result = ioread32be(image->kern_base + offset); /* Disable RMW */ - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL); + tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL); tmp &= ~TSI148_LCSR_VMCTRL_RMWEN; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VMCTRL); + iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL); spin_unlock(&(image->lock)); - mutex_unlock(&(vme_rmw)); + mutex_unlock(&(bridge->vme_rmw)); return result; } @@ -1637,8 +1615,6 @@ static int tsi148_dma_set_vme_dest_attributes(u32 *attr, vme_address_t aspace, /* * Add a link list descriptor to the list - * - * XXX Need to handle 2eSST Broadcast select bits */ int tsi148_dma_list_add (struct vme_dma_list *list, struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count) @@ -1651,7 +1627,7 @@ int tsi148_dma_list_add (struct vme_dma_list *list, struct vme_dma_attr *src, dma_addr_t desc_ptr; int retval = 0; - /* XXX descriptor must be aligned on 64-bit boundaries */ + /* Descriptor must be aligned on 64-bit boundaries */ entry = (struct tsi148_dma_entry *)kmalloc( sizeof(struct tsi148_dma_entry), GFP_KERNEL); if (entry == NULL) { @@ -1788,11 +1764,14 @@ err_mem: /* * Check to see if the provided DMA channel is busy. */ -static int tsi148_dma_busy(int channel) +static int tsi148_dma_busy(struct vme_bridge *tsi148_bridge, int channel) { u32 tmp; + struct tsi148_driver *bridge; + + bridge = tsi148_bridge->driver_priv; - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] + + tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSTA); if (tmp & TSI148_LCSR_DSTA_BSY) @@ -1815,12 +1794,12 @@ int tsi148_dma_list_exec(struct vme_dma_list *list) dma_addr_t bus_addr; u32 bus_addr_high, bus_addr_low; u32 val, dctlreg = 0; -#if 0 - int x; -#endif + struct tsi148_driver *bridge; ctrlr = list->parent; + bridge = ctrlr->parent->driver_priv; + mutex_lock(&(ctrlr->mtx)); channel = ctrlr->number; @@ -1837,48 +1816,6 @@ int tsi148_dma_list_exec(struct vme_dma_list *list) } else { list_add(&(list->list), &(ctrlr->running)); } -#if 0 - /* XXX Still todo */ - for (x = 0; x < 8; x++) { /* vme block size */ - if ((32 << x) >= vmeDma->maxVmeBlockSize) { - break; - } - } - if (x == 8) - x = 7; - dctlreg |= (x << 12); - - for (x = 0; x < 8; x++) { /* pci block size */ - if ((32 << x) >= vmeDma->maxPciBlockSize) { - break; - } - } - if (x == 8) - x = 7; - dctlreg |= (x << 4); - - if (vmeDma->vmeBackOffTimer) { - for (x = 1; x < 8; x++) { /* vme timer */ - if ((1 << (x - 1)) >= vmeDma->vmeBackOffTimer) { - break; - } - } - if (x == 8) - x = 7; - dctlreg |= (x << 8); - } - - if (vmeDma->pciBackOffTimer) { - for (x = 1; x < 8; x++) { /* pci timer */ - if ((1 << (x - 1)) >= vmeDma->pciBackOffTimer) { - break; - } - } - if (x == 8) - x = 7; - dctlreg |= (x << 0); - } -#endif /* Get first bus address and write into registers */ entry = list_first_entry(&(list->entries), struct tsi148_dma_entry, @@ -1890,21 +1827,22 @@ int tsi148_dma_list_exec(struct vme_dma_list *list) reg_split(bus_addr, &bus_addr_high, &bus_addr_low); - iowrite32be(bus_addr_high, tsi148_bridge->base + + iowrite32be(bus_addr_high, bridge->base + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU); - iowrite32be(bus_addr_low, tsi148_bridge->base + + iowrite32be(bus_addr_low, bridge->base + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL); /* Start the operation */ - iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, tsi148_bridge->base + + iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL); - wait_event_interruptible(dma_queue[channel], tsi148_dma_busy(channel)); + wait_event_interruptible(bridge->dma_queue[channel], + tsi148_dma_busy(ctrlr->parent, channel)); /* * Read status register, this register is valid until we kick off a * new transfer. */ - val = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] + + val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSTA); if (val & TSI148_LCSR_DSTA_VBE) { @@ -1952,12 +1890,15 @@ int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base, { u32 lm_base_high, lm_base_low, lm_ctl = 0; int i; + struct tsi148_driver *bridge; + + bridge = lm->parent->driver_priv; mutex_lock(&(lm->mtx)); /* If we already have a callback attached, we can't move it! */ for (i = 0; i < lm->monitors; i++) { - if(lm_callback[i] != NULL) { + if (bridge->lm_callback[i] != NULL) { mutex_unlock(&(lm->mtx)); printk("Location monitor callback attached, can't " "reset\n"); @@ -1996,9 +1937,9 @@ int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base, reg_split(lm_base, &lm_base_high, &lm_base_low); - iowrite32be(lm_base_high, tsi148_bridge->base + TSI148_LCSR_LMBAU); - iowrite32be(lm_base_low, tsi148_bridge->base + TSI148_LCSR_LMBAL); - iowrite32be(lm_ctl, tsi148_bridge->base + TSI148_LCSR_LMAT); + iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU); + iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL); + iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT); mutex_unlock(&(lm->mtx)); @@ -2012,12 +1953,15 @@ int tsi148_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base, vme_address_t *aspace, vme_cycle_t *cycle) { u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0; + struct tsi148_driver *bridge; + + bridge = lm->parent->driver_priv; mutex_lock(&(lm->mtx)); - lm_base_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMBAU); - lm_base_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMBAL); - lm_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMAT); + lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU); + lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL); + lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); reg_join(lm_base_high, lm_base_low, lm_base); @@ -2060,11 +2004,14 @@ int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor, void (*callback)(int)) { u32 lm_ctl, tmp; + struct tsi148_driver *bridge; + + bridge = lm->parent->driver_priv; mutex_lock(&(lm->mtx)); /* Ensure that the location monitor is configured - need PGM or DATA */ - lm_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMAT); + lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) { mutex_unlock(&(lm->mtx)); printk("Location monitor not properly configured\n"); @@ -2072,28 +2019,28 @@ int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor, } /* Check that a callback isn't already attached */ - if (lm_callback[monitor] != NULL) { + if (bridge->lm_callback[monitor] != NULL) { mutex_unlock(&(lm->mtx)); printk("Existing callback attached\n"); return -EBUSY; } /* Attach callback */ - lm_callback[monitor] = callback; + bridge->lm_callback[monitor] = callback; /* Enable Location Monitor interrupt */ - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN); + tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); tmp |= TSI148_LCSR_INTEN_LMEN[monitor]; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEN); + iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO); + tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); tmp |= TSI148_LCSR_INTEO_LMEO[monitor]; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO); + iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); /* Ensure that global Location Monitor Enable set */ if ((lm_ctl & TSI148_LCSR_LMAT_EN) == 0) { lm_ctl |= TSI148_LCSR_LMAT_EN; - iowrite32be(lm_ctl, tsi148_bridge->base + TSI148_LCSR_LMAT); + iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT); } mutex_unlock(&(lm->mtx)); @@ -2107,30 +2054,33 @@ int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor, int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor) { u32 lm_en, tmp; + struct tsi148_driver *bridge; + + bridge = lm->parent->driver_priv; mutex_lock(&(lm->mtx)); /* Disable Location Monitor and ensure previous interrupts are clear */ - lm_en = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN); + lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN); lm_en &= ~TSI148_LCSR_INTEN_LMEN[monitor]; - iowrite32be(lm_en, tsi148_bridge->base + TSI148_LCSR_INTEN); + iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN); - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO); + tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); tmp &= ~TSI148_LCSR_INTEO_LMEO[monitor]; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO); + iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); iowrite32be(TSI148_LCSR_INTC_LMC[monitor], - tsi148_bridge->base + TSI148_LCSR_INTC); + bridge->base + TSI148_LCSR_INTC); /* Detach callback */ - lm_callback[monitor] = NULL; + bridge->lm_callback[monitor] = NULL; /* If all location monitors disabled, disable global Location Monitor */ if ((lm_en & (TSI148_LCSR_INTS_LM0S | TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM3S)) == 0) { - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMAT); + tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT); tmp &= ~TSI148_LCSR_LMAT_EN; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_LMAT); + iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT); } mutex_unlock(&(lm->mtx)); @@ -2141,12 +2091,19 @@ int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor) /* * Determine Geographical Addressing */ -int tsi148_slot_get(void) +int tsi148_slot_get(struct vme_bridge *tsi148_bridge) { u32 slot = 0; + struct tsi148_driver *bridge; + + bridge = tsi148_bridge->driver_priv; + + if (!geoid) { + slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT); + slot = slot & TSI148_LCSR_VSTAT_GA_M; + } else + slot = geoid; - slot = ioread32be(tsi148_bridge->base + TSI148_LCSR_VSTAT); - slot = slot & TSI148_LCSR_VSTAT_GA_M; return (int)slot; } @@ -2167,45 +2124,50 @@ static int __init tsi148_init(void) * boards registers, this means there is a fix length 508kB window which must * be mapped onto PCI memory. */ -static int tsi148_crcsr_init(struct pci_dev *pdev) +static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge, + struct pci_dev *pdev) { u32 cbar, crat, vstat; u32 crcsr_bus_high, crcsr_bus_low; int retval; + struct tsi148_driver *bridge; + + bridge = tsi148_bridge->driver_priv; /* Allocate mem for CR/CSR image */ - crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE, - &crcsr_bus); - if (crcsr_kernel == NULL) { + bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE, + &(bridge->crcsr_bus)); + if (bridge->crcsr_kernel == NULL) { dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR " "image\n"); return -ENOMEM; } - memset(crcsr_kernel, 0, VME_CRCSR_BUF_SIZE); + memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE); - reg_split(crcsr_bus, &crcsr_bus_high, &crcsr_bus_low); + reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low); - iowrite32be(crcsr_bus_high, tsi148_bridge->base + TSI148_LCSR_CROU); - iowrite32be(crcsr_bus_low, tsi148_bridge->base + TSI148_LCSR_CROL); + iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU); + iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL); /* Ensure that the CR/CSR is configured at the correct offset */ - cbar = ioread32be(tsi148_bridge->base + TSI148_CBAR); + cbar = ioread32be(bridge->base + TSI148_CBAR); cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3; - vstat = tsi148_slot_get(); + vstat = tsi148_slot_get(tsi148_bridge); if (cbar != vstat) { + cbar = vstat; dev_info(&pdev->dev, "Setting CR/CSR offset\n"); - iowrite32be(cbar<<3, tsi148_bridge->base + TSI148_CBAR); + iowrite32be(cbar<<3, bridge->base + TSI148_CBAR); } dev_info(&pdev->dev, "CR/CSR Offset: %d\n", cbar); - crat = ioread32be(tsi148_bridge->base + TSI148_LCSR_CRAT); + crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); if (crat & TSI148_LCSR_CRAT_EN) { dev_info(&pdev->dev, "Enabling CR/CSR space\n"); iowrite32be(crat | TSI148_LCSR_CRAT_EN, - tsi148_bridge->base + TSI148_LCSR_CRAT); + bridge->base + TSI148_LCSR_CRAT); } else dev_info(&pdev->dev, "CR/CSR already enabled\n"); @@ -2214,8 +2176,9 @@ static int tsi148_crcsr_init(struct pci_dev *pdev) * through VME writes. */ if(err_chk) { - retval = tsi148_master_set(flush_image, 1, (vstat * 0x80000), - 0x80000, VME_CRCSR, VME_SCT, VME_D16); + retval = tsi148_master_set(bridge->flush_image, 1, + (vstat * 0x80000), 0x80000, VME_CRCSR, VME_SCT, + VME_D16); if (retval) dev_err(&pdev->dev, "Configuring flush image failed\n"); } @@ -2224,20 +2187,25 @@ static int tsi148_crcsr_init(struct pci_dev *pdev) } -static void tsi148_crcsr_exit(struct pci_dev *pdev) +static void tsi148_crcsr_exit(struct vme_bridge *tsi148_bridge, + struct pci_dev *pdev) { u32 crat; + struct tsi148_driver *bridge; + + bridge = tsi148_bridge->driver_priv; /* Turn off CR/CSR space */ - crat = ioread32be(tsi148_bridge->base + TSI148_LCSR_CRAT); + crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); iowrite32be(crat & ~TSI148_LCSR_CRAT_EN, - tsi148_bridge->base + TSI148_LCSR_CRAT); + bridge->base + TSI148_LCSR_CRAT); /* Free image */ - iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_CROU); - iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_CROL); + iowrite32be(0, bridge->base + TSI148_LCSR_CROU); + iowrite32be(0, bridge->base + TSI148_LCSR_CROL); - pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, crcsr_kernel, crcsr_bus); + pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel, + bridge->crcsr_bus); } static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) @@ -2245,6 +2213,8 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) int retval, i, master_num; u32 data; struct list_head *pos = NULL; + struct vme_bridge *tsi148_bridge; + struct tsi148_driver *tsi148_device; struct vme_master_resource *master_image; struct vme_slave_resource *slave_image; struct vme_dma_resource *dma_ctrlr; @@ -2264,6 +2234,18 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) memset(tsi148_bridge, 0, sizeof(struct vme_bridge)); + tsi148_device = kmalloc(sizeof(struct tsi148_driver), GFP_KERNEL); + if (tsi148_device == NULL) { + dev_err(&pdev->dev, "Failed to allocate memory for device " + "structure\n"); + retval = -ENOMEM; + goto err_driver; + } + + memset(tsi148_device, 0, sizeof(struct tsi148_driver)); + + tsi148_bridge->driver_priv = tsi148_device; + /* Enable the device */ retval = pci_enable_device(pdev); if (retval) { @@ -2279,15 +2261,16 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) } /* map registers in BAR 0 */ - tsi148_bridge->base = ioremap_nocache(pci_resource_start(pdev, 0), 4096); - if (!tsi148_bridge->base) { + tsi148_device->base = ioremap_nocache(pci_resource_start(pdev, 0), + 4096); + if (!tsi148_device->base) { dev_err(&pdev->dev, "Unable to remap CRG region\n"); retval = -EIO; goto err_remap; } /* Check to see if the mapping worked out */ - data = ioread32(tsi148_bridge->base + TSI148_PCFS_ID) & 0x0000FFFF; + data = ioread32(tsi148_device->base + TSI148_PCFS_ID) & 0x0000FFFF; if (data != PCI_VENDOR_ID_TUNDRA) { dev_err(&pdev->dev, "CRG region check failed\n"); retval = -EIO; @@ -2295,12 +2278,11 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) } /* Initialize wait queues & mutual exclusion flags */ - /* XXX These need to be moved to the vme_bridge structure */ - init_waitqueue_head(&dma_queue[0]); - init_waitqueue_head(&dma_queue[1]); - init_waitqueue_head(&iack_queue); - mutex_init(&(vme_int)); - mutex_init(&(vme_rmw)); + init_waitqueue_head(&(tsi148_device->dma_queue[0])); + init_waitqueue_head(&(tsi148_device->dma_queue[1])); + init_waitqueue_head(&(tsi148_device->iack_queue)); + mutex_init(&(tsi148_device->vme_int)); + mutex_init(&(tsi148_device->vme_rmw)); tsi148_bridge->parent = &(pdev->dev); strcpy(tsi148_bridge->name, driver_name); @@ -2320,29 +2302,29 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) master_num = TSI148_MAX_MASTER; if(err_chk){ master_num--; - /* XXX */ - flush_image = (struct vme_master_resource *)kmalloc( - sizeof(struct vme_master_resource), GFP_KERNEL); - if (flush_image == NULL) { + + tsi148_device->flush_image = (struct vme_master_resource *) + kmalloc(sizeof(struct vme_master_resource), GFP_KERNEL); + if (tsi148_device->flush_image == NULL) { dev_err(&pdev->dev, "Failed to allocate memory for " "flush resource structure\n"); retval = -ENOMEM; goto err_master; } - flush_image->parent = tsi148_bridge; - spin_lock_init(&(flush_image->lock)); - flush_image->locked = 1; - flush_image->number = master_num; - flush_image->address_attr = VME_A16 | VME_A24 | VME_A32 | - VME_A64; - flush_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | - VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 | - VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER | - VME_PROG | VME_DATA; - flush_image->width_attr = VME_D16 | VME_D32; - memset(&(flush_image->pci_resource), 0, + tsi148_device->flush_image->parent = tsi148_bridge; + spin_lock_init(&(tsi148_device->flush_image->lock)); + tsi148_device->flush_image->locked = 1; + tsi148_device->flush_image->number = master_num; + tsi148_device->flush_image->address_attr = VME_A16 | VME_A24 | + VME_A32 | VME_A64; + tsi148_device->flush_image->cycle_attr = VME_SCT | VME_BLT | + VME_MBLT | VME_2eVME | VME_2eSST | VME_2eSSTB | + VME_2eSST160 | VME_2eSST267 | VME_2eSST320 | VME_SUPER | + VME_USER | VME_PROG | VME_DATA; + tsi148_device->flush_image->width_attr = VME_D16 | VME_D32; + memset(&(tsi148_device->flush_image->bus_resource), 0, sizeof(struct resource)); - flush_image->kern_base = NULL; + tsi148_device->flush_image->kern_base = NULL; } /* Add master windows to list */ @@ -2367,7 +2349,7 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER | VME_PROG | VME_DATA; master_image->width_attr = VME_D16 | VME_D32; - memset(&(master_image->pci_resource), 0, + memset(&(master_image->bus_resource), 0, sizeof(struct resource)); master_image->kern_base = NULL; list_add_tail(&(master_image->list), @@ -2415,6 +2397,10 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) mutex_init(&(dma_ctrlr->mtx)); dma_ctrlr->locked = 0; dma_ctrlr->number = i; + dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM | + VME_DMA_MEM_TO_VME | VME_DMA_VME_TO_VME | + VME_DMA_MEM_TO_MEM | VME_DMA_PATTERN_TO_VME | + VME_DMA_PATTERN_TO_MEM; INIT_LIST_HEAD(&(dma_ctrlr->pending)); INIT_LIST_HEAD(&(dma_ctrlr->running)); list_add_tail(&(dma_ctrlr->list), @@ -2455,40 +2441,42 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) tsi148_bridge->lm_detach = tsi148_lm_detach; tsi148_bridge->slot_get = tsi148_slot_get; - data = ioread32be(tsi148_bridge->base + TSI148_LCSR_VSTAT); + data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT); dev_info(&pdev->dev, "Board is%s the VME system controller\n", (data & TSI148_LCSR_VSTAT_SCONS)? "" : " not"); - dev_info(&pdev->dev, "VME geographical address is %d\n", - data & TSI148_LCSR_VSTAT_GA_M); + if (!geoid) + dev_info(&pdev->dev, "VME geographical address is %d\n", + data & TSI148_LCSR_VSTAT_GA_M); + else + dev_info(&pdev->dev, "VME geographical address is set to %d\n", + geoid); + dev_info(&pdev->dev, "VME Write and flush and error check is %s\n", err_chk ? "enabled" : "disabled"); - if(tsi148_crcsr_init(pdev)) { + if (tsi148_crcsr_init(tsi148_bridge, pdev)) dev_err(&pdev->dev, "CR/CSR configuration failed.\n"); goto err_crcsr; - } - - /* Need to save tsi148_bridge pointer locally in link list for use in - * tsi148_remove() - */ retval = vme_register_bridge(tsi148_bridge); if (retval != 0) { dev_err(&pdev->dev, "Chip Registration failed.\n"); goto err_reg; } + pci_set_drvdata(pdev, tsi148_bridge); + /* Clear VME bus "board fail", and "power-up reset" lines */ - data = ioread32be(tsi148_bridge->base + TSI148_LCSR_VSTAT); + data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT); data &= ~TSI148_LCSR_VSTAT_BRDFL; data |= TSI148_LCSR_VSTAT_CPURST; - iowrite32be(data, tsi148_bridge->base + TSI148_LCSR_VSTAT); + iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT); return 0; vme_unregister_bridge(tsi148_bridge); err_reg: - tsi148_crcsr_exit(pdev); + tsi148_crcsr_exit(tsi148_bridge, pdev); err_crcsr: err_lm: /* resources are stored in link list */ @@ -2519,15 +2507,17 @@ err_master: kfree(master_image); } - tsi148_irq_exit(pdev); + tsi148_irq_exit(tsi148_device, pdev); err_irq: err_test: - iounmap(tsi148_bridge->base); + iounmap(tsi148_device->base); err_remap: pci_release_regions(pdev); err_resource: pci_disable_device(pdev); err_enable: + kfree(tsi148_device); +err_driver: kfree(tsi148_bridge); err_struct: return retval; @@ -2541,56 +2531,58 @@ static void tsi148_remove(struct pci_dev *pdev) struct vme_slave_resource *slave_image; struct vme_dma_resource *dma_ctrlr; int i; + struct tsi148_driver *bridge; + struct vme_bridge *tsi148_bridge = pci_get_drvdata(pdev); - dev_dbg(&pdev->dev, "Driver is being unloaded.\n"); + bridge = tsi148_bridge->driver_priv; - /* XXX We need to find the pdev->dev in the list of vme_bridge->dev's */ + + dev_dbg(&pdev->dev, "Driver is being unloaded.\n"); /* * Shutdown all inbound and outbound windows. */ for (i = 0; i < 8; i++) { - iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_IT[i] + + iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITAT); - iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_OT[i] + + iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTAT); } /* * Shutdown Location monitor. */ - iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_LMAT); + iowrite32be(0, bridge->base + TSI148_LCSR_LMAT); /* * Shutdown CRG map. */ - iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_CSRAT); + iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT); /* * Clear error status. */ - iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_EDPAT); - iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_VEAT); - iowrite32be(0x07000700, tsi148_bridge->base + TSI148_LCSR_PSTAT); + iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT); + iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT); + iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT); /* * Remove VIRQ interrupt (if any) */ - if (ioread32be(tsi148_bridge->base + TSI148_LCSR_VICR) & 0x800) { - iowrite32be(0x8000, tsi148_bridge->base + TSI148_LCSR_VICR); - } + if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800) + iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR); /* * Map all Interrupts to PCI INTA */ - iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTM1); - iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTM2); + iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1); + iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2); - tsi148_irq_exit(pdev); + tsi148_irq_exit(bridge, pdev); vme_unregister_bridge(tsi148_bridge); - tsi148_crcsr_exit(pdev); + tsi148_crcsr_exit(tsi148_bridge, pdev); /* resources are stored in link list */ list_for_each(pos, &(tsi148_bridge->dma_resources)) { @@ -2608,19 +2600,22 @@ static void tsi148_remove(struct pci_dev *pdev) /* resources are stored in link list */ list_for_each(pos, &(tsi148_bridge->master_resources)) { - master_image = list_entry(pos, struct vme_master_resource, list); + master_image = list_entry(pos, struct vme_master_resource, + list); list_del(pos); kfree(master_image); } - tsi148_irq_exit(pdev); + tsi148_irq_exit(bridge, pdev); - iounmap(tsi148_bridge->base); + iounmap(bridge->base); pci_release_regions(pdev); pci_disable_device(pdev); + kfree(tsi148_bridge->driver_priv); + kfree(tsi148_bridge); } @@ -2634,250 +2629,11 @@ static void __exit tsi148_exit(void) MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes"); module_param(err_chk, bool, 0); +MODULE_PARM_DESC(geoid, "Override geographical addressing"); +module_param(geoid, int, 0); + MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge"); MODULE_LICENSE("GPL"); module_init(tsi148_init); module_exit(tsi148_exit); - -/*---------------------------------------------------------------------------- - * STAGING - *--------------------------------------------------------------------------*/ - -#if 0 -/* - * Direct Mode DMA transfer - * - * XXX Not looking at direct mode for now, we can always use link list mode - * with a single entry. - */ -int tsi148_dma_run(struct vme_dma_resource *resource, struct vme_dma_attr src, - struct vme_dma_attr dest, size_t count) -{ - u32 dctlreg = 0; - unsigned int tmp; - int val; - int channel, x; - struct vmeDmaPacket *cur_dma; - struct tsi148_dma_descriptor *dmaLL; - - /* direct mode */ - dctlreg = 0x800000; - - for (x = 0; x < 8; x++) { /* vme block size */ - if ((32 << x) >= vmeDma->maxVmeBlockSize) { - break; - } - } - if (x == 8) - x = 7; - dctlreg |= (x << 12); - - for (x = 0; x < 8; x++) { /* pci block size */ - if ((32 << x) >= vmeDma->maxPciBlockSize) { - break; - } - } - if (x == 8) - x = 7; - dctlreg |= (x << 4); - - if (vmeDma->vmeBackOffTimer) { - for (x = 1; x < 8; x++) { /* vme timer */ - if ((1 << (x - 1)) >= vmeDma->vmeBackOffTimer) { - break; - } - } - if (x == 8) - x = 7; - dctlreg |= (x << 8); - } - - if (vmeDma->pciBackOffTimer) { - for (x = 1; x < 8; x++) { /* pci timer */ - if ((1 << (x - 1)) >= vmeDma->pciBackOffTimer) { - break; - } - } - if (x == 8) - x = 7; - dctlreg |= (x << 0); - } - - /* Program registers for DMA transfer */ - iowrite32be(dmaLL->dsau, tsi148_bridge->base + - TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAU); - iowrite32be(dmaLL->dsal, tsi148_bridge->base + - TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAL); - iowrite32be(dmaLL->ddau, tsi148_bridge->base + - TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAU); - iowrite32be(dmaLL->ddal, tsi148_bridge->base + - TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAL); - iowrite32be(dmaLL->dsat, tsi148_bridge->base + - TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAT); - iowrite32be(dmaLL->ddat, tsi148_bridge->base + - TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAT); - iowrite32be(dmaLL->dcnt, tsi148_bridge->base + - TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCNT); - iowrite32be(dmaLL->ddbs, tsi148_bridge->base + - TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDBS); - - /* Start the operation */ - iowrite32be(dctlreg | 0x2000000, tsi148_bridge->base + - TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL); - - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] + - TSI148_LCSR_OFFSET_DSTA); - wait_event_interruptible(dma_queue[channel], (tmp & 0x1000000) == 0); - - /* - * Read status register, we should probably do this in some error - * handler rather than here so that we can be sure we haven't kicked off - * another DMA transfer. - */ - val = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] + - TSI148_LCSR_OFFSET_DSTA); - - vmeDma->vmeDmaStatus = 0; - if (val & 0x10000000) { - printk(KERN_ERR - "DMA Error in DMA_tempe_irqhandler DSTA=%08X\n", - val); - vmeDma->vmeDmaStatus = val; - - } - return (0); -} -#endif - -#if 0 - -/* Global VME controller information */ -struct pci_dev *vme_pci_dev; - -/* - * Set the VME bus arbiter with the requested attributes - */ -int tempe_set_arbiter(vmeArbiterCfg_t * vmeArb) -{ - int temp_ctl = 0; - int gto = 0; - - temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VCTRL); - temp_ctl &= 0xFFEFFF00; - - if (vmeArb->globalTimeoutTimer == 0xFFFFFFFF) { - gto = 8; - } else if (vmeArb->globalTimeoutTimer > 2048) { - return (-EINVAL); - } else if (vmeArb->globalTimeoutTimer == 0) { - gto = 0; - } else { - gto = 1; - while ((16 * (1 << (gto - 1))) < vmeArb->globalTimeoutTimer) { - gto += 1; - } - } - temp_ctl |= gto; - - if (vmeArb->arbiterMode != VME_PRIORITY_MODE) { - temp_ctl |= 1 << 6; - } - - if (vmeArb->arbiterTimeoutFlag) { - temp_ctl |= 1 << 7; - } - - if (vmeArb->noEarlyReleaseFlag) { - temp_ctl |= 1 << 20; - } - iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_VCTRL); - - return (0); -} - -/* - * Return the attributes of the VME bus arbiter. - */ -int tempe_get_arbiter(vmeArbiterCfg_t * vmeArb) -{ - int temp_ctl = 0; - int gto = 0; - - - temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VCTRL); - - gto = temp_ctl & 0xF; - if (gto != 0) { - vmeArb->globalTimeoutTimer = (16 * (1 << (gto - 1))); - } - - if (temp_ctl & (1 << 6)) { - vmeArb->arbiterMode = VME_R_ROBIN_MODE; - } else { - vmeArb->arbiterMode = VME_PRIORITY_MODE; - } - - if (temp_ctl & (1 << 7)) { - vmeArb->arbiterTimeoutFlag = 1; - } - - if (temp_ctl & (1 << 20)) { - vmeArb->noEarlyReleaseFlag = 1; - } - - return (0); -} - -/* - * Set the VME bus requestor with the requested attributes - */ -int tempe_set_requestor(vmeRequesterCfg_t * vmeReq) -{ - int temp_ctl = 0; - - temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL); - temp_ctl &= 0xFFFF0000; - - if (vmeReq->releaseMode == 1) { - temp_ctl |= (1 << 3); - } - - if (vmeReq->fairMode == 1) { - temp_ctl |= (1 << 2); - } - - temp_ctl |= (vmeReq->timeonTimeoutTimer & 7) << 8; - temp_ctl |= (vmeReq->timeoffTimeoutTimer & 7) << 12; - temp_ctl |= vmeReq->requestLevel; - - iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_VMCTRL); - return (0); -} - -/* - * Return the attributes of the VME bus requestor - */ -int tempe_get_requestor(vmeRequesterCfg_t * vmeReq) -{ - int temp_ctl = 0; - - temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL); - - if (temp_ctl & 0x18) { - vmeReq->releaseMode = 1; - } - - if (temp_ctl & (1 << 2)) { - vmeReq->fairMode = 1; - } - - vmeReq->requestLevel = temp_ctl & 3; - vmeReq->timeonTimeoutTimer = (temp_ctl >> 8) & 7; - vmeReq->timeoffTimeoutTimer = (temp_ctl >> 12) & 7; - - return (0); -} - - -#endif |