diff options
Diffstat (limited to 'drivers/staging/wilc1000/wlan.h')
| -rw-r--r-- | drivers/staging/wilc1000/wlan.h | 97 |
1 files changed, 94 insertions, 3 deletions
diff --git a/drivers/staging/wilc1000/wlan.h b/drivers/staging/wilc1000/wlan.h index 8c4634262adb..7689569cd82f 100644 --- a/drivers/staging/wilc1000/wlan.h +++ b/drivers/staging/wilc1000/wlan.h @@ -8,6 +8,7 @@ #define WILC_WLAN_H #include <linux/types.h> +#include <linux/bitfield.h> /******************************************** * @@ -65,6 +66,8 @@ #define WILC_INTR_CLEAR (WILC_INTR_REG_BASE + 0x30) #define WILC_INTR_STATUS (WILC_INTR_REG_BASE + 0x40) +#define WILC_RF_REVISION_ID 0x13f4 + #define WILC_VMM_TBL_SIZE 64 #define WILC_VMM_TX_TBL_BASE 0x150400 #define WILC_VMM_RX_TBL_BASE 0x150500 @@ -88,10 +91,53 @@ #define WILC_SPI_TX_MODE (WILC_SPI_REG_BASE + 0x20) #define WILC_SPI_PROTOCOL_CONFIG (WILC_SPI_REG_BASE + 0x24) #define WILC_SPI_INTR_CTL (WILC_SPI_REG_BASE + 0x2c) +#define WILC_SPI_INT_STATUS (WILC_SPI_REG_BASE + 0x40) +#define WILC_SPI_INT_CLEAR (WILC_SPI_REG_BASE + 0x44) + +#define WILC_SPI_WAKEUP_REG 0x1 +#define WILC_SPI_WAKEUP_BIT BIT(1) #define WILC_SPI_PROTOCOL_OFFSET (WILC_SPI_PROTOCOL_CONFIG - \ WILC_SPI_REG_BASE) +#define WILC_SPI_CLOCKLESS_ADDR_LIMIT 0x30 + +/* Functions IO enables bits */ +#define WILC_SDIO_CCCR_IO_EN_FUNC1 BIT(1) + +/* Function/Interrupt enables bits */ +#define WILC_SDIO_CCCR_IEN_MASTER BIT(0) +#define WILC_SDIO_CCCR_IEN_FUNC1 BIT(1) + +/* Abort CCCR register bits */ +#define WILC_SDIO_CCCR_ABORT_RESET BIT(3) + +/* Vendor specific CCCR registers */ +#define WILC_SDIO_WAKEUP_REG 0xf0 +#define WILC_SDIO_WAKEUP_BIT BIT(0) + +#define WILC_SDIO_CLK_STATUS_REG 0xf1 +#define WILC_SDIO_CLK_STATUS_BIT BIT(0) + +#define WILC_SDIO_INTERRUPT_DATA_SZ_REG 0xf2 /* Read size (2 bytes) */ + +#define WILC_SDIO_VMM_TBL_CTRL_REG 0xf6 +#define WILC_SDIO_IRQ_FLAG_REG 0xf7 +#define WILC_SDIO_IRQ_CLEAR_FLAG_REG 0xf8 + +#define WILC_SDIO_HOST_TO_FW_REG 0xfa +#define WILC_SDIO_HOST_TO_FW_BIT BIT(0) + +#define WILC_SDIO_FW_TO_HOST_REG 0xfc +#define WILC_SDIO_FW_TO_HOST_BIT BIT(0) + +/* Function 1 specific FBR register */ +#define WILC_SDIO_FBR_CSA_REG 0x10C /* CSA pointer (3 bytes) */ +#define WILC_SDIO_FBR_DATA_REG 0x10F + +#define WILC_SDIO_F1_DATA_REG 0x0 +#define WILC_SDIO_EXT_IRQ_FLAG_REG 0x4 + #define WILC_AHB_DATA_MEM_BASE 0x30000 #define WILC_AHB_SHARE_MEM_BASE 0xd0000 @@ -112,6 +158,32 @@ #define WILC_HAVE_DISABLE_WILC_UART BIT(7) #define WILC_HAVE_USE_IRQ_AS_HOST_WAKE BIT(8) +#define WILC_CORTUS_INTERRUPT_BASE 0x10A8 +#define WILC_CORTUS_INTERRUPT_1 (WILC_CORTUS_INTERRUPT_BASE + 0x4) +#define WILC_CORTUS_INTERRUPT_2 (WILC_CORTUS_INTERRUPT_BASE + 0x8) + +/* tx control register 1 to 4 for RX */ +#define WILC_REG_4_TO_1_RX 0x1e1c + +/* tx control register 1 to 4 for TX Bank_0 */ +#define WILC_REG_4_TO_1_TX_BANK0 0x1e9c + +#define WILC_CORTUS_RESET_MUX_SEL 0x1118 +#define WILC_CORTUS_BOOT_REGISTER 0xc0000 + +#define WILC_CORTUS_BOOT_FROM_IRAM 0x71 + +#define WILC_1000_BASE_ID 0x100000 + +#define WILC_1000_BASE_ID_2A 0x1002A0 +#define WILC_1000_BASE_ID_2A_REV1 (WILC_1000_BASE_ID_2A + 1) + +#define WILC_1000_BASE_ID_2B 0x1002B0 +#define WILC_1000_BASE_ID_2B_REV1 (WILC_1000_BASE_ID_2B + 1) +#define WILC_1000_BASE_ID_2B_REV2 (WILC_1000_BASE_ID_2B + 2) + +#define WILC_CHIP_REV_FIELD GENMASK(11, 0) + /******************************************** * * Wlan Defines @@ -134,7 +206,23 @@ #define WILC_TX_BUFF_SIZE (64 * 1024) #define MODALIAS "WILC_SPI" -#define GPIO_NUM 0x44 + +#define WILC_PKT_HDR_CONFIG_FIELD BIT(31) +#define WILC_PKT_HDR_OFFSET_FIELD GENMASK(30, 22) +#define WILC_PKT_HDR_TOTAL_LEN_FIELD GENMASK(21, 11) +#define WILC_PKT_HDR_LEN_FIELD GENMASK(10, 0) + +#define WILC_INTERRUPT_DATA_SIZE GENMASK(14, 0) + +#define WILC_VMM_BUFFER_SIZE GENMASK(9, 0) + +#define WILC_VMM_HDR_TYPE BIT(31) +#define WILC_VMM_HDR_MGMT_FIELD BIT(30) +#define WILC_VMM_HDR_PKT_SIZE GENMASK(29, 15) +#define WILC_VMM_HDR_BUFF_SIZE GENMASK(14, 0) + +#define WILC_VMM_ENTRY_COUNT GENMASK(8, 3) +#define WILC_VMM_ENTRY_AVAILABLE BIT(2) /*******************************************/ /* E0 and later Interrupt flags. */ /*******************************************/ @@ -150,14 +238,16 @@ /* 21: INT5 flag */ /*******************************************/ #define IRG_FLAGS_OFFSET 16 -#define IRQ_DMA_WD_CNT_MASK ((1ul << IRG_FLAGS_OFFSET) - 1) +#define IRQ_DMA_WD_CNT_MASK GENMASK(IRG_FLAGS_OFFSET - 1, 0) #define INT_0 BIT(IRG_FLAGS_OFFSET) #define INT_1 BIT(IRG_FLAGS_OFFSET + 1) #define INT_2 BIT(IRG_FLAGS_OFFSET + 2) #define INT_3 BIT(IRG_FLAGS_OFFSET + 3) #define INT_4 BIT(IRG_FLAGS_OFFSET + 4) #define INT_5 BIT(IRG_FLAGS_OFFSET + 5) -#define MAX_NUM_INT 6 +#define MAX_NUM_INT 5 +#define IRG_FLAGS_MASK GENMASK(IRG_FLAGS_OFFSET + MAX_NUM_INT, \ + IRG_FLAGS_OFFSET) /*******************************************/ /* E0 and later Interrupt flags. */ @@ -185,6 +275,7 @@ #define DATA_INT_EXT INT_0 #define ALL_INT_EXT DATA_INT_EXT #define NUM_INT_EXT 1 +#define UNHANDLED_IRQ_MASK GENMASK(MAX_NUM_INT - 1, NUM_INT_EXT) #define DATA_INT_CLR CLR_INT0 |