diff options
Diffstat (limited to 'drivers/thermal/ti-soc-thermal/dra752-thermal-data.c')
| -rw-r--r-- | drivers/thermal/ti-soc-thermal/dra752-thermal-data.c | 65 |
1 files changed, 0 insertions, 65 deletions
diff --git a/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c b/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c index 4167373327d9..33a3030aa3c0 100644 --- a/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c +++ b/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c @@ -41,24 +41,16 @@ dra752_core_temp_sensor_registers = { .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET, .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK, .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK, - .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK, .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK, - .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK, - .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK, .bgap_threshold = DRA752_BANDGAP_THRESHOLD_CORE_OFFSET, .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET, - .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK, .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK, .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK, - .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET, - .ctrl_dtemp_0 = DRA752_DTEMP_CORE_0_OFFSET, .ctrl_dtemp_1 = DRA752_DTEMP_CORE_1_OFFSET, .ctrl_dtemp_2 = DRA752_DTEMP_CORE_2_OFFSET, - .ctrl_dtemp_3 = DRA752_DTEMP_CORE_3_OFFSET, - .ctrl_dtemp_4 = DRA752_DTEMP_CORE_4_OFFSET, .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET, }; @@ -74,24 +66,16 @@ dra752_iva_temp_sensor_registers = { .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET, .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK, .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK, - .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK, .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK, - .mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK, - .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK, .bgap_threshold = DRA752_BANDGAP_THRESHOLD_IVA_OFFSET, .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET, - .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK, .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK, .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK, - .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET, - .ctrl_dtemp_0 = DRA752_DTEMP_IVA_0_OFFSET, .ctrl_dtemp_1 = DRA752_DTEMP_IVA_1_OFFSET, .ctrl_dtemp_2 = DRA752_DTEMP_IVA_2_OFFSET, - .ctrl_dtemp_3 = DRA752_DTEMP_IVA_3_OFFSET, - .ctrl_dtemp_4 = DRA752_DTEMP_IVA_4_OFFSET, .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET, }; @@ -107,24 +91,16 @@ dra752_mpu_temp_sensor_registers = { .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET, .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK, .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK, - .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK, .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK, - .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK, - .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK, .bgap_threshold = DRA752_BANDGAP_THRESHOLD_MPU_OFFSET, .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET, - .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK, .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK, .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK, - .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET, - .ctrl_dtemp_0 = DRA752_DTEMP_MPU_0_OFFSET, .ctrl_dtemp_1 = DRA752_DTEMP_MPU_1_OFFSET, .ctrl_dtemp_2 = DRA752_DTEMP_MPU_2_OFFSET, - .ctrl_dtemp_3 = DRA752_DTEMP_MPU_3_OFFSET, - .ctrl_dtemp_4 = DRA752_DTEMP_MPU_4_OFFSET, .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET, }; @@ -140,24 +116,16 @@ dra752_dspeve_temp_sensor_registers = { .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET, .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK, .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK, - .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK, .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK, - .mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK, - .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK, .bgap_threshold = DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET, .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET, - .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK, .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK, .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK, - .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET, - .ctrl_dtemp_0 = DRA752_DTEMP_DSPEVE_0_OFFSET, .ctrl_dtemp_1 = DRA752_DTEMP_DSPEVE_1_OFFSET, .ctrl_dtemp_2 = DRA752_DTEMP_DSPEVE_2_OFFSET, - .ctrl_dtemp_3 = DRA752_DTEMP_DSPEVE_3_OFFSET, - .ctrl_dtemp_4 = DRA752_DTEMP_DSPEVE_4_OFFSET, .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET, }; @@ -173,24 +141,16 @@ dra752_gpu_temp_sensor_registers = { .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET, .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK, .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK, - .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK, .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK, - .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK, - .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK, .bgap_threshold = DRA752_BANDGAP_THRESHOLD_GPU_OFFSET, .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET, - .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK, .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK, .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK, - .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET, - .ctrl_dtemp_0 = DRA752_DTEMP_GPU_0_OFFSET, .ctrl_dtemp_1 = DRA752_DTEMP_GPU_1_OFFSET, .ctrl_dtemp_2 = DRA752_DTEMP_GPU_2_OFFSET, - .ctrl_dtemp_3 = DRA752_DTEMP_GPU_3_OFFSET, - .ctrl_dtemp_4 = DRA752_DTEMP_GPU_4_OFFSET, .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET, }; @@ -200,11 +160,6 @@ static struct temp_sensor_data dra752_mpu_temp_sensor_data = { .t_cold = DRA752_MPU_T_COLD, .min_freq = DRA752_MPU_MIN_FREQ, .max_freq = DRA752_MPU_MAX_FREQ, - .max_temp = DRA752_MPU_MAX_TEMP, - .min_temp = DRA752_MPU_MIN_TEMP, - .hyst_val = DRA752_MPU_HYST_VAL, - .update_int1 = 1000, - .update_int2 = 2000, }; /* Thresholds and limits for DRA752 GPU temperature sensor */ @@ -213,11 +168,6 @@ static struct temp_sensor_data dra752_gpu_temp_sensor_data = { .t_cold = DRA752_GPU_T_COLD, .min_freq = DRA752_GPU_MIN_FREQ, .max_freq = DRA752_GPU_MAX_FREQ, - .max_temp = DRA752_GPU_MAX_TEMP, - .min_temp = DRA752_GPU_MIN_TEMP, - .hyst_val = DRA752_GPU_HYST_VAL, - .update_int1 = 1000, - .update_int2 = 2000, }; /* Thresholds and limits for DRA752 CORE temperature sensor */ @@ -226,11 +176,6 @@ static struct temp_sensor_data dra752_core_temp_sensor_data = { .t_cold = DRA752_CORE_T_COLD, .min_freq = DRA752_CORE_MIN_FREQ, .max_freq = DRA752_CORE_MAX_FREQ, - .max_temp = DRA752_CORE_MAX_TEMP, - .min_temp = DRA752_CORE_MIN_TEMP, - .hyst_val = DRA752_CORE_HYST_VAL, - .update_int1 = 1000, - .update_int2 = 2000, }; /* Thresholds and limits for DRA752 DSPEVE temperature sensor */ @@ -239,11 +184,6 @@ static struct temp_sensor_data dra752_dspeve_temp_sensor_data = { .t_cold = DRA752_DSPEVE_T_COLD, .min_freq = DRA752_DSPEVE_MIN_FREQ, .max_freq = DRA752_DSPEVE_MAX_FREQ, - .max_temp = DRA752_DSPEVE_MAX_TEMP, - .min_temp = DRA752_DSPEVE_MIN_TEMP, - .hyst_val = DRA752_DSPEVE_HYST_VAL, - .update_int1 = 1000, - .update_int2 = 2000, }; /* Thresholds and limits for DRA752 IVA temperature sensor */ @@ -252,11 +192,6 @@ static struct temp_sensor_data dra752_iva_temp_sensor_data = { .t_cold = DRA752_IVA_T_COLD, .min_freq = DRA752_IVA_MIN_FREQ, .max_freq = DRA752_IVA_MAX_FREQ, - .max_temp = DRA752_IVA_MAX_TEMP, - .min_temp = DRA752_IVA_MIN_TEMP, - .hyst_val = DRA752_IVA_HYST_VAL, - .update_int1 = 1000, - .update_int2 = 2000, }; /* |