diff options
Diffstat (limited to 'include/asm-mips/dec')
| -rw-r--r-- | include/asm-mips/dec/ecc.h | 3 | ||||
| -rw-r--r-- | include/asm-mips/dec/ioasic_addrs.h | 3 | ||||
| -rw-r--r-- | include/asm-mips/dec/kn01.h | 34 | ||||
| -rw-r--r-- | include/asm-mips/dec/kn02.h | 33 | ||||
| -rw-r--r-- | include/asm-mips/dec/kn02xa.h | 46 | ||||
| -rw-r--r-- | include/asm-mips/dec/kn03.h | 13 | ||||
| -rw-r--r-- | include/asm-mips/dec/kn05.h | 76 | ||||
| -rw-r--r-- | include/asm-mips/dec/prom.h | 30 | ||||
| -rw-r--r-- | include/asm-mips/dec/system.h | 18 | ||||
| -rw-r--r-- | include/asm-mips/dec/tc.h | 10 |
10 files changed, 143 insertions, 123 deletions
diff --git a/include/asm-mips/dec/ecc.h b/include/asm-mips/dec/ecc.h index 724908b0bf13..19495a490e72 100644 --- a/include/asm-mips/dec/ecc.h +++ b/include/asm-mips/dec/ecc.h @@ -49,7 +49,8 @@ struct pt_regs; extern void dec_ecc_be_init(void); extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup); -extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs); +extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, + struct pt_regs *regs); #endif #endif /* __ASM_MIPS_DEC_ECC_H */ diff --git a/include/asm-mips/dec/ioasic_addrs.h b/include/asm-mips/dec/ioasic_addrs.h index 5e18a7510592..4cbc1f8a1129 100644 --- a/include/asm-mips/dec/ioasic_addrs.h +++ b/include/asm-mips/dec/ioasic_addrs.h @@ -45,7 +45,8 @@ /* - * Offsets for I/O ASIC registers (relative to (system_base + IOASIC_IOCTL)). + * Offsets for I/O ASIC registers + * (relative to (dec_kn_slot_base + IOASIC_IOCTL)). */ /* all systems */ #define IO_REG_SCSI_DMA_P 0x00 /* SCSI DMA Pointer */ diff --git a/include/asm-mips/dec/kn01.h b/include/asm-mips/dec/kn01.h index 946943502f83..eb522aa1e226 100644 --- a/include/asm-mips/dec/kn01.h +++ b/include/asm-mips/dec/kn01.h @@ -8,14 +8,12 @@ * * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions * are by courtesy of Chris Fraser. - * Copyright (C) 2002, 2003 Maciej W. Rozycki + * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki */ #ifndef __ASM_MIPS_DEC_KN01_H #define __ASM_MIPS_DEC_KN01_H -#include <asm/addrspace.h> - -#define KN01_SLOT_BASE KSEG1ADDR(0x10000000) +#define KN01_SLOT_BASE 0x10000000 #define KN01_SLOT_SIZE 0x01000000 /* @@ -41,17 +39,9 @@ /* - * Some port addresses... - */ -#define KN01_LANCE_BASE (KN01_SLOT_BASE + KN01_LANCE) /* 0xB8000000 */ -#define KN01_DZ11_BASE (KN01_SLOT_BASE + KN01_DZ11) /* 0xBC000000 */ -#define KN01_RTC_BASE (KN01_SLOT_BASE + KN01_RTC) /* 0xBD000000 */ - - -/* * Frame buffer memory address. */ -#define KN01_VFB_MEM KSEG1ADDR(0x0fc00000) +#define KN01_VFB_MEM 0x0fc00000 /* * CPU interrupt bits. @@ -80,4 +70,22 @@ #define KN01_CSR_VRGTRB (1<<0) /* red DAC voltage over blue (r/o) */ #define KN01_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */ + +#ifndef __ASSEMBLY__ + +#include <linux/interrupt.h> +#include <linux/spinlock.h> +#include <linux/types.h> + +struct pt_regs; + +extern u16 cached_kn01_csr; +extern spinlock_t kn01_lock; + +extern void dec_kn01_be_init(void); +extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup); +extern irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id, + struct pt_regs *regs); +#endif + #endif /* __ASM_MIPS_DEC_KN01_H */ diff --git a/include/asm-mips/dec/kn02.h b/include/asm-mips/dec/kn02.h index f797f7045920..8319ad77b250 100644 --- a/include/asm-mips/dec/kn02.h +++ b/include/asm-mips/dec/kn02.h @@ -8,21 +8,12 @@ * * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions * are by courtesy of Chris Fraser. - * Copyright (C) 2002, 2003 Maciej W. Rozycki + * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki */ #ifndef __ASM_MIPS_DEC_KN02_H #define __ASM_MIPS_DEC_KN02_H -#ifndef __ASSEMBLY__ -#include <linux/spinlock.h> -#include <linux/types.h> -#endif - -#include <asm/addrspace.h> -#include <asm/dec/ecc.h> - - -#define KN02_SLOT_BASE KSEG1ADDR(0x1fc00000) +#define KN02_SLOT_BASE 0x1fc00000 #define KN02_SLOT_SIZE 0x00080000 /* @@ -39,22 +30,14 @@ /* - * Some port addresses... - */ -#define KN02_DZ11_BASE (KN02_SLOT_BASE + KN02_DZ11) /* DZ11 */ -#define KN02_RTC_BASE (KN02_SLOT_BASE + KN02_RTC) /* RTC */ -#define KN02_CSR_BASE (KN02_SLOT_BASE + KN02_CSR) /* CSR */ - - -/* * System Control & Status Register bits. */ #define KN02_CSR_RES_28 (0xf<<28) /* unused */ #define KN02_CSR_PSU (1<<27) /* power supply unit warning */ #define KN02_CSR_NVRAM (1<<26) /* ~NVRAM clear jumper */ #define KN02_CSR_REFEVEN (1<<25) /* mem refresh bank toggle */ -#define KN03_CSR_NRMOD (1<<24) /* ~NRMOD manufact. jumper */ -#define KN03_CSR_IOINTEN (0xff<<16) /* IRQ mask bits */ +#define KN02_CSR_NRMOD (1<<24) /* ~NRMOD manufact. jumper */ +#define KN02_CSR_IOINTEN (0xff<<16) /* IRQ mask bits */ #define KN02_CSR_DIAGCHK (1<<15) /* diagn/norml ECC reads */ #define KN02_CSR_DIAGGEN (1<<14) /* diagn/norml ECC writes */ #define KN02_CSR_CORRECT (1<<13) /* ECC correct/check */ @@ -63,8 +46,8 @@ #define KN02_CSR_BNK32M (1<<10) /* 32M/8M stride */ #define KN02_CSR_DIAGDN (1<<9) /* DIAGDN manufact. jumper */ #define KN02_CSR_BAUD38 (1<<8) /* DZ11 38/19kbps ext. rate */ -#define KN03_CSR_IOINT (0xff<<0) /* IRQ status bits (r/o) */ -#define KN03_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */ +#define KN02_CSR_IOINT (0xff<<0) /* IRQ status bits (r/o) */ +#define KN02_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */ /* @@ -98,6 +81,10 @@ #ifndef __ASSEMBLY__ + +#include <linux/spinlock.h> +#include <linux/types.h> + extern u32 cached_kn02_csr; extern spinlock_t kn02_lock; extern void init_kn02_irqs(int base); diff --git a/include/asm-mips/dec/kn02xa.h b/include/asm-mips/dec/kn02xa.h index 648c4dcbba1d..a25f3d7da7f7 100644 --- a/include/asm-mips/dec/kn02xa.h +++ b/include/asm-mips/dec/kn02xa.h @@ -9,7 +9,7 @@ * * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions * are by courtesy of Chris Fraser. - * Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki + * Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki * * These are addresses which have to be known early in the boot process. * For other addresses refer to tc.h, ioasic_addrs.h and friends. @@ -17,31 +17,23 @@ #ifndef __ASM_MIPS_DEC_KN02XA_H #define __ASM_MIPS_DEC_KN02XA_H -#include <asm/addrspace.h> #include <asm/dec/ioasic_addrs.h> -#define KN02XA_SLOT_BASE KSEG1ADDR(0x1c000000) - -/* - * Some port addresses... - */ -#define KN02XA_IOASIC_BASE (KN02XA_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */ -#define KN02XA_RTC_BASE (KN02XA_SLOT_BASE + IOASIC_TOY) /* RTC */ - +#define KN02XA_SLOT_BASE 0x1c000000 /* * Memory control ASIC registers. */ -#define KN02XA_MER KSEG1ADDR(0x0c400000) /* memory error register */ -#define KN02XA_MSR KSEG1ADDR(0x0c800000) /* memory size register */ +#define KN02XA_MER 0x0c400000 /* memory error register */ +#define KN02XA_MSR 0x0c800000 /* memory size register */ /* * CPU control ASIC registers. */ -#define KN02XA_MEM_CONF KSEG1ADDR(0x0e000000) /* write timeout config */ -#define KN02XA_EAR KSEG1ADDR(0x0e000004) /* error address register */ -#define KN02XA_BOOT0 KSEG1ADDR(0x0e000008) /* boot 0 register */ -#define KN02XA_MEM_INTR KSEG1ADDR(0x0e00000c) /* write err IRQ stat & ack */ +#define KN02XA_MEM_CONF 0x0e000000 /* write timeout config */ +#define KN02XA_EAR 0x0e000004 /* error address register */ +#define KN02XA_BOOT0 0x0e000008 /* boot 0 register */ +#define KN02XA_MEM_INTR 0x0e00000c /* write err IRQ stat & ack */ /* * Memory Error Register bits, common definitions. @@ -52,8 +44,13 @@ #define KN02XA_MER_PAGERR (1<<16) /* 2k page boundary error */ #define KN02XA_MER_TRANSERR (1<<15) /* transfer length error */ #define KN02XA_MER_PARDIS (1<<14) /* parity error disable */ -#define KN02XA_MER_RES_12 (0x3<<12) /* unused */ -#define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask */ +#define KN02XA_MER_SIZE (1<<13) /* r/o mirror of MSR_SIZE */ +#define KN02XA_MER_RES_12 (1<<12) /* unused */ +#define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask: */ +#define KN02XA_MER_BYTERR_3 (0x8<<8) /* byte lane #3 */ +#define KN02XA_MER_BYTERR_2 (0x4<<8) /* byte lane #2 */ +#define KN02XA_MER_BYTERR_1 (0x2<<8) /* byte lane #1 */ +#define KN02XA_MER_BYTERR_0 (0x1<<8) /* byte lane #0 */ #define KN02XA_MER_RES_0 (0xff<<0) /* unused */ /* @@ -72,4 +69,17 @@ #define KN02XA_EAR_ADDRESS (0x7ffffff<<2) /* address involved */ #define KN02XA_EAR_RES_0 (0x3<<0) /* unused */ + +#ifndef __ASSEMBLY__ + +#include <linux/interrupt.h> + +struct pt_regs; + +extern void dec_kn02xa_be_init(void); +extern int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup); +extern irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id, + struct pt_regs *regs); +#endif + #endif /* __ASM_MIPS_DEC_KN02XA_H */ diff --git a/include/asm-mips/dec/kn03.h b/include/asm-mips/dec/kn03.h index 676abd17c6a4..edede923ffb8 100644 --- a/include/asm-mips/dec/kn03.h +++ b/include/asm-mips/dec/kn03.h @@ -10,24 +10,15 @@ * * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions * are by courtesy of Chris Fraser. - * Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki + * Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki */ #ifndef __ASM_MIPS_DEC_KN03_H #define __ASM_MIPS_DEC_KN03_H -#include <asm/addrspace.h> #include <asm/dec/ecc.h> #include <asm/dec/ioasic_addrs.h> -#define KN03_SLOT_BASE KSEG1ADDR(0x1f800000) - -/* - * Some port addresses... - */ -#define KN03_IOASIC_BASE (KN03_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */ -#define KN03_RTC_BASE (KN03_SLOT_BASE + IOASIC_TOY) /* RTC */ -#define KN03_MCR_BASE (KN03_SLOT_BASE + IOASIC_MCR) /* MCR */ - +#define KN03_SLOT_BASE 0x1f800000 /* * CPU interrupt bits. diff --git a/include/asm-mips/dec/kn05.h b/include/asm-mips/dec/kn05.h index b120362b8f13..15fe8f881e60 100644 --- a/include/asm-mips/dec/kn05.h +++ b/include/asm-mips/dec/kn05.h @@ -1,10 +1,12 @@ /* * include/asm-mips/dec/kn05.h * - * DECstation 5000/260 (4max+ or KN05) and DECsystem 5900/260 + * DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min + * or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or + * KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC * definitions. * - * Copyright (C) 2002, 2003 Maciej W. Rozycki + * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -13,8 +15,8 @@ * * WARNING! All this information is pure guesswork based on the * ROM. It is provided here in hope it will give someone some - * food for thought. No documentation for the KN05 module has - * been located so far. + * food for thought. No documentation for the KN05 nor the KN04 + * module has been located so far. */ #ifndef __ASM_MIPS_DEC_KN05_H #define __ASM_MIPS_DEC_KN05_H @@ -24,48 +26,50 @@ /* * The oncard MB (Memory Buffer) ASIC provides an additional address * decoder. Certain address ranges within the "high" 16 slots are - * passed to the I/O ASIC's decoder like with the KN03. Others are - * handled locally. "Low" slots are always passed. + * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA. + * Others are handled locally. "Low" slots are always passed. */ -#define KN05_MB_ROM (16*IOASIC_SLOT_SIZE) /* KN05 card ROM */ -#define KN05_IOCTL (17*IOASIC_SLOT_SIZE) /* I/O ASIC */ -#define KN05_ESAR (18*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */ -#define KN05_LANCE (19*IOASIC_SLOT_SIZE) /* LANCE Ethernet */ -#define KN05_MB_INT (20*IOASIC_SLOT_SIZE) /* MB interrupt register */ -#define KN05_MB_EA (21*IOASIC_SLOT_SIZE) /* MB error address? */ -#define KN05_MB_EC (22*IOASIC_SLOT_SIZE) /* MB error ??? */ -#define KN05_MB_CSR (23*IOASIC_SLOT_SIZE) /* MB control & status */ -#define KN05_RES_24 (24*IOASIC_SLOT_SIZE) /* unused? */ -#define KN05_RES_25 (25*IOASIC_SLOT_SIZE) /* unused? */ -#define KN05_RES_26 (26*IOASIC_SLOT_SIZE) /* unused? */ -#define KN05_RES_27 (27*IOASIC_SLOT_SIZE) /* unused? */ -#define KN05_SCSI (28*IOASIC_SLOT_SIZE) /* ASC SCSI */ -#define KN05_RES_29 (29*IOASIC_SLOT_SIZE) /* unused? */ -#define KN05_RES_30 (30*IOASIC_SLOT_SIZE) /* unused? */ -#define KN05_RES_31 (31*IOASIC_SLOT_SIZE) /* unused? */ +#define KN4K_SLOT_BASE 0x1fc00000 + +#define KN4K_MB_ROM (0*IOASIC_SLOT_SIZE) /* KN05/KN04 card ROM */ +#define KN4K_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */ +#define KN4K_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */ +#define KN4K_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */ +#define KN4K_MB_INT (4*IOASIC_SLOT_SIZE) /* MB interrupt register */ +#define KN4K_MB_EA (5*IOASIC_SLOT_SIZE) /* MB error address? */ +#define KN4K_MB_EC (6*IOASIC_SLOT_SIZE) /* MB error ??? */ +#define KN4K_MB_CSR (7*IOASIC_SLOT_SIZE) /* MB control & status */ +#define KN4K_RES_08 (8*IOASIC_SLOT_SIZE) /* unused? */ +#define KN4K_RES_09 (9*IOASIC_SLOT_SIZE) /* unused? */ +#define KN4K_RES_10 (10*IOASIC_SLOT_SIZE) /* unused? */ +#define KN4K_RES_11 (11*IOASIC_SLOT_SIZE) /* unused? */ +#define KN4K_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */ +#define KN4K_RES_13 (13*IOASIC_SLOT_SIZE) /* unused? */ +#define KN4K_RES_14 (14*IOASIC_SLOT_SIZE) /* unused? */ +#define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ /* * Bits for the MB interrupt register. * The register appears read-only. */ -#define KN05_MB_INT_TC (1<<0) /* TURBOchannel? */ -#define KN05_MB_INT_RTC (1<<1) /* RTC? */ -#define KN05_MB_INT_MT (1<<3) /* ??? */ +#define KN4K_MB_INT_TC (1<<0) /* TURBOchannel? */ +#define KN4K_MB_INT_RTC (1<<1) /* RTC? */ +#define KN4K_MB_INT_MT (1<<3) /* ??? */ /* * Bits for the MB control & status register. * Set to 0x00bf8001 on my system by the ROM. */ -#define KN05_MB_CSR_PF (1<<0) /* PreFetching enable? */ -#define KN05_MB_CSR_F (1<<1) /* ??? */ -#define KN05_MB_CSR_ECC (0xff<<2) /* ??? */ -#define KN05_MB_CSR_OD (1<<10) /* ??? */ -#define KN05_MB_CSR_CP (1<<11) /* ??? */ -#define KN05_MB_CSR_UNC (1<<12) /* ??? */ -#define KN05_MB_CSR_IM (1<<13) /* ??? */ -#define KN05_MB_CSR_NC (1<<14) /* ??? */ -#define KN05_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ -#define KN05_MB_CSR_MSK (0x1f<<16) /* ??? */ -#define KN05_MB_CSR_FW (1<<21) /* ??? */ +#define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */ +#define KN4K_MB_CSR_F (1<<1) /* ??? */ +#define KN4K_MB_CSR_ECC (0xff<<2) /* ??? */ +#define KN4K_MB_CSR_OD (1<<10) /* ??? */ +#define KN4K_MB_CSR_CP (1<<11) /* ??? */ +#define KN4K_MB_CSR_UNC (1<<12) /* ??? */ +#define KN4K_MB_CSR_IM (1<<13) /* ??? */ +#define KN4K_MB_CSR_NC (1<<14) /* ??? */ +#define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ +#define KN4K_MB_CSR_MSK (0x1f<<16) /* ??? */ +#define KN4K_MB_CSR_FW (1<<21) /* ??? */ #endif /* __ASM_MIPS_DEC_KN05_H */ diff --git a/include/asm-mips/dec/prom.h b/include/asm-mips/dec/prom.h index a05d6d3395fe..1384dd0964b9 100644 --- a/include/asm-mips/dec/prom.h +++ b/include/asm-mips/dec/prom.h @@ -24,7 +24,7 @@ * PMAX/3MAX PROM entry points for DS2100/3100's and DS5000/2xx's. * Many of these will work for MIPSen as well! */ -#define VEC_RESET (u64 *)KSEG1ADDR(0x1fc00000) +#define VEC_RESET (u64 *)CKSEG1ADDR(0x1fc00000) /* Prom base address */ #define PMAX_PROM_ENTRY(x) (VEC_RESET + (x)) /* Prom jump table */ @@ -111,19 +111,21 @@ extern int (*__pmax_close)(int); * On MIPS64 we have to call PROM functions via a helper * dispatcher to accomodate ABI incompatibilities. */ -#define __DEC_PROM_O32 __attribute__((alias("call_o32"))) - -int _rex_bootinit(int (*)(void)) __DEC_PROM_O32; -int _rex_bootread(int (*)(void)) __DEC_PROM_O32; -int _rex_getbitmap(int (*)(memmap *), memmap *) __DEC_PROM_O32; -unsigned long *_rex_slot_address(unsigned long *(*)(int), int) __DEC_PROM_O32; -void *_rex_gettcinfo(void *(*)(void)) __DEC_PROM_O32; -int _rex_getsysid(int (*)(void)) __DEC_PROM_O32; -void _rex_clear_cache(void (*)(void)) __DEC_PROM_O32; - -int _prom_getchar(int (*)(void)) __DEC_PROM_O32; -char *_prom_getenv(char *(*)(char *), char *) __DEC_PROM_O32; -int _prom_printf(int (*)(char *, ...), char *, ...) __DEC_PROM_O32; +#define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \ + __asm__(#fun " = call_o32") + +int __DEC_PROM_O32(_rex_bootinit, (int (*)(void))); +int __DEC_PROM_O32(_rex_bootread, (int (*)(void))); +int __DEC_PROM_O32(_rex_getbitmap, (int (*)(memmap *), memmap *)); +unsigned long *__DEC_PROM_O32(_rex_slot_address, + (unsigned long *(*)(int), int)); +void *__DEC_PROM_O32(_rex_gettcinfo, (void *(*)(void))); +int __DEC_PROM_O32(_rex_getsysid, (int (*)(void))); +void __DEC_PROM_O32(_rex_clear_cache, (void (*)(void))); + +int __DEC_PROM_O32(_prom_getchar, (int (*)(void))); +char *__DEC_PROM_O32(_prom_getenv, (char *(*)(char *), char *)); +int __DEC_PROM_O32(_prom_printf, (int (*)(char *, ...), char *, ...)); #define rex_bootinit() _rex_bootinit(__rex_bootinit) diff --git a/include/asm-mips/dec/system.h b/include/asm-mips/dec/system.h new file mode 100644 index 000000000000..78af51fbc797 --- /dev/null +++ b/include/asm-mips/dec/system.h @@ -0,0 +1,18 @@ +/* + * include/asm-mips/dec/system.h + * + * Generic DECstation/DECsystem bits. + * + * Copyright (C) 2005 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#ifndef __ASM_DEC_SYSTEM_H +#define __ASM_DEC_SYSTEM_H + +extern unsigned long dec_kn_slot_base, dec_kn_slot_size; + +#endif /* __ASM_DEC_SYSTEM_H */ diff --git a/include/asm-mips/dec/tc.h b/include/asm-mips/dec/tc.h index d7bba43f863a..9cb51f24d42c 100644 --- a/include/asm-mips/dec/tc.h +++ b/include/asm-mips/dec/tc.h @@ -7,10 +7,8 @@ * * Copyright (c) 1998 Harald Koerfgen */ -#ifndef ASM_TC_H -#define ASM_TC_H - -extern unsigned long system_base; +#ifndef __ASM_DEC_TC_H +#define __ASM_DEC_TC_H /* * Search for a TURBOchannel Option Module @@ -36,8 +34,8 @@ extern unsigned long get_tc_base_addr(int); */ extern unsigned long get_tc_irq_nr(int); /* - * Return TURBOchannel clock frequency in hz + * Return TURBOchannel clock frequency in Hz */ extern unsigned long get_tc_speed(void); -#endif +#endif /* __ASM_DEC_TC_H */ |