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-rw-r--r--include/asm-mips/io.h100
1 files changed, 27 insertions, 73 deletions
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index 8c011aa61afa..6b17eb9d79a5 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -4,7 +4,7 @@
* for more details.
*
* Copyright (C) 1994, 1995 Waldorf GmbH
- * Copyright (C) 1994 - 2000 Ralf Baechle
+ * Copyright (C) 1994 - 2000, 06 Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
* Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
* Author: Maciej W. Rozycki <macro@mips.com>
@@ -40,56 +40,13 @@
* hardware. An example use would be for flash memory that's used for
* execute in place.
*/
-# define __raw_ioswabb(x) (x)
-# define __raw_ioswabw(x) (x)
-# define __raw_ioswabl(x) (x)
-# define __raw_ioswabq(x) (x)
-# define ____raw_ioswabq(x) (x)
+# define __raw_ioswabb(a,x) (x)
+# define __raw_ioswabw(a,x) (x)
+# define __raw_ioswabl(a,x) (x)
+# define __raw_ioswabq(a,x) (x)
+# define ____raw_ioswabq(a,x) (x)
-/*
- * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
- * less sane hardware forces software to fiddle with this...
- *
- * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
- * you can't have the numerical value of data and byte addresses within
- * multibyte quantities both preserved at the same time. Hence two
- * variations of functions: non-prefixed ones that preserve the value
- * and prefixed ones that preserve byte addresses. The latters are
- * typically used for moving raw data between a peripheral and memory (cf.
- * string I/O functions), hence the "__mem_" prefix.
- */
-#if defined(CONFIG_SWAP_IO_SPACE)
-
-# define ioswabb(x) (x)
-# define __mem_ioswabb(x) (x)
-# ifdef CONFIG_SGI_IP22
-/*
- * IP22 seems braindead enough to swap 16bits values in hardware, but
- * not 32bits. Go figure... Can't tell without documentation.
- */
-# define ioswabw(x) (x)
-# define __mem_ioswabw(x) le16_to_cpu(x)
-# else
-# define ioswabw(x) le16_to_cpu(x)
-# define __mem_ioswabw(x) (x)
-# endif
-# define ioswabl(x) le32_to_cpu(x)
-# define __mem_ioswabl(x) (x)
-# define ioswabq(x) le64_to_cpu(x)
-# define __mem_ioswabq(x) (x)
-
-#else
-
-# define ioswabb(x) (x)
-# define __mem_ioswabb(x) (x)
-# define ioswabw(x) (x)
-# define __mem_ioswabw(x) cpu_to_le16(x)
-# define ioswabl(x) (x)
-# define __mem_ioswabl(x) cpu_to_le32(x)
-# define ioswabq(x) (x)
-# define __mem_ioswabq(x) cpu_to_le32(x)
-
-#endif
+/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
#define IO_SPACE_LIMIT 0xffff
@@ -103,8 +60,20 @@
*/
extern const unsigned long mips_io_port_base;
-#define set_io_port_base(base) \
- do { * (unsigned long *) &mips_io_port_base = (base); } while (0)
+/*
+ * Gcc will generate code to load the value of mips_io_port_base after each
+ * function call which may be fairly wasteful in some cases. So we don't
+ * play quite by the book. We tell gcc mips_io_port_base is a long variable
+ * which solves the code generation issue. Now we need to violate the
+ * aliasing rules a little to make initialization possible and finally we
+ * will need the barrier() to fight side effects of the aliasing chat.
+ * This trickery will eventually collapse under gcc's optimizer. Oh well.
+ */
+static inline void set_io_port_base(unsigned long base)
+{
+ * (unsigned long *) &mips_io_port_base = base;
+ barrier();
+}
/*
* Thanks to James van Artsdalen for a better timing-fix than
@@ -334,7 +303,7 @@ static inline void pfx##write##bwlq(type val, \
\
__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
\
- __val = pfx##ioswab##bwlq(val); \
+ __val = pfx##ioswab##bwlq(__mem, val); \
\
if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
*__mem = __val; \
@@ -389,7 +358,7 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
BUG(); \
} \
\
- return pfx##ioswab##bwlq(__val); \
+ return pfx##ioswab##bwlq(__mem, __val); \
}
#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
@@ -399,10 +368,9 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \
volatile type *__addr; \
type __val; \
\
- port = __swizzle_addr_##bwlq(port); \
- __addr = (void *)(mips_io_port_base + port); \
+ __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
\
- __val = pfx##ioswab##bwlq(val); \
+ __val = pfx##ioswab##bwlq(__addr, val); \
\
/* Really, we want this to be atomic */ \
BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
@@ -416,15 +384,14 @@ static inline type pfx##in##bwlq##p(unsigned long port) \
volatile type *__addr; \
type __val; \
\
- port = __swizzle_addr_##bwlq(port); \
- __addr = (void *)(mips_io_port_base + port); \
+ __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
\
BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
\
__val = *__addr; \
slow; \
\
- return pfx##ioswab##bwlq(__val); \
+ return pfx##ioswab##bwlq(__addr, __val); \
}
#define __BUILD_MEMORY_PFX(bus, bwlq, type) \
@@ -589,24 +556,11 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
*/
#define __ISA_IO_base ((char *)(isa_slot_offset))
-#define isa_readb(a) readb(__ISA_IO_base + (a))
-#define isa_readw(a) readw(__ISA_IO_base + (a))
-#define isa_readl(a) readl(__ISA_IO_base + (a))
-#define isa_readq(a) readq(__ISA_IO_base + (a))
-#define isa_writeb(b,a) writeb(b,__ISA_IO_base + (a))
-#define isa_writew(w,a) writew(w,__ISA_IO_base + (a))
-#define isa_writel(l,a) writel(l,__ISA_IO_base + (a))
-#define isa_writeq(q,a) writeq(q,__ISA_IO_base + (a))
-#define isa_memset_io(a,b,c) memset_io(__ISA_IO_base + (a),(b),(c))
-#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),__ISA_IO_base + (b),(c))
-#define isa_memcpy_toio(a,b,c) memcpy_toio(__ISA_IO_base + (a),(b),(c))
-
/*
* We don't have csum_partial_copy_fromio() yet, so we cheat here and
* just copy it. The net code will then do the checksum later.
*/
#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
-#define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
/*
* check_signature - find BIOS signatures