diff options
Diffstat (limited to 'include/asm-sh')
| -rw-r--r-- | include/asm-sh/atomic.h | 3 | ||||
| -rw-r--r-- | include/asm-sh/bitops.h | 1 | ||||
| -rw-r--r-- | include/asm-sh/bus-sh.h | 1 | ||||
| -rw-r--r-- | include/asm-sh/cache.h | 2 | ||||
| -rw-r--r-- | include/asm-sh/clock.h | 61 | ||||
| -rw-r--r-- | include/asm-sh/cpu-sh3/dma.h | 31 | ||||
| -rw-r--r-- | include/asm-sh/cpu-sh4/dma.h | 52 | ||||
| -rw-r--r-- | include/asm-sh/cpu-sh4/freq.h | 2 | ||||
| -rw-r--r-- | include/asm-sh/dma-mapping.h | 25 | ||||
| -rw-r--r-- | include/asm-sh/dma.h | 14 | ||||
| -rw-r--r-- | include/asm-sh/freq.h | 11 | ||||
| -rw-r--r-- | include/asm-sh/futex.h | 49 | ||||
| -rw-r--r-- | include/asm-sh/io.h | 283 | ||||
| -rw-r--r-- | include/asm-sh/io_generic.h | 96 | ||||
| -rw-r--r-- | include/asm-sh/ioctl.h | 76 | ||||
| -rw-r--r-- | include/asm-sh/irq-sh7780.h | 349 | ||||
| -rw-r--r-- | include/asm-sh/irq.h | 143 | ||||
| -rw-r--r-- | include/asm-sh/kexec.h | 33 | ||||
| -rw-r--r-- | include/asm-sh/machvec.h | 66 | ||||
| -rw-r--r-- | include/asm-sh/mman.h | 1 | ||||
| -rw-r--r-- | include/asm-sh/mutex.h | 9 | ||||
| -rw-r--r-- | include/asm-sh/ptrace.h | 10 | ||||
| -rw-r--r-- | include/asm-sh/system.h | 10 | ||||
| -rw-r--r-- | include/asm-sh/thread_info.h | 2 | ||||
| -rw-r--r-- | include/asm-sh/timer.h | 42 |
25 files changed, 942 insertions, 430 deletions
diff --git a/include/asm-sh/atomic.h b/include/asm-sh/atomic.h index aabfd334462c..fb627de217f2 100644 --- a/include/asm-sh/atomic.h +++ b/include/asm-sh/atomic.h @@ -101,6 +101,8 @@ static inline int atomic_cmpxchg(atomic_t *v, int old, int new) return ret; } +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) + static inline int atomic_add_unless(atomic_t *v, int a, int u) { int ret; @@ -140,4 +142,5 @@ static __inline__ void atomic_set_mask(unsigned int mask, atomic_t *v) #define smp_mb__before_atomic_inc() barrier() #define smp_mb__after_atomic_inc() barrier() +#include <asm-generic/atomic.h> #endif /* __ASM_SH_ATOMIC_H */ diff --git a/include/asm-sh/bitops.h b/include/asm-sh/bitops.h index 5163d1ff2f1b..1c5260860045 100644 --- a/include/asm-sh/bitops.h +++ b/include/asm-sh/bitops.h @@ -470,6 +470,7 @@ found_middle: */ #define fls(x) generic_fls(x) +#define fls64(x) generic_fls64(x) #endif /* __KERNEL__ */ diff --git a/include/asm-sh/bus-sh.h b/include/asm-sh/bus-sh.h index 83c5d2fd057f..e42d63b65cb5 100644 --- a/include/asm-sh/bus-sh.h +++ b/include/asm-sh/bus-sh.h @@ -21,6 +21,7 @@ struct sh_dev { void *mapbase; unsigned int irq[6]; u64 *dma_mask; + u64 coherent_dma_mask; }; #define to_sh_dev(d) container_of((d), struct sh_dev, dev) diff --git a/include/asm-sh/cache.h b/include/asm-sh/cache.h index 9b4dd6d8212e..656fdfe9e8b4 100644 --- a/include/asm-sh/cache.h +++ b/include/asm-sh/cache.h @@ -22,8 +22,6 @@ #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) -#define L1_CACHE_SHIFT_MAX 5 /* largest L1 which this arch supports */ - struct cache_info { unsigned int ways; unsigned int sets; diff --git a/include/asm-sh/clock.h b/include/asm-sh/clock.h new file mode 100644 index 000000000000..fdfb75b30f0d --- /dev/null +++ b/include/asm-sh/clock.h @@ -0,0 +1,61 @@ +#ifndef __ASM_SH_CLOCK_H +#define __ASM_SH_CLOCK_H + +#include <linux/kref.h> +#include <linux/list.h> +#include <linux/seq_file.h> + +struct clk; + +struct clk_ops { + void (*init)(struct clk *clk); + void (*enable)(struct clk *clk); + void (*disable)(struct clk *clk); + void (*recalc)(struct clk *clk); + int (*set_rate)(struct clk *clk, unsigned long rate); +}; + +struct clk { + struct list_head node; + const char *name; + + struct module *owner; + + struct clk *parent; + struct clk_ops *ops; + + struct kref kref; + + unsigned long rate; + unsigned long flags; +}; + +#define CLK_ALWAYS_ENABLED (1 << 0) +#define CLK_RATE_PROPAGATES (1 << 1) + +/* Should be defined by processor-specific code */ +void arch_init_clk_ops(struct clk_ops **, int type); + +/* arch/sh/kernel/cpu/clock.c */ +int clk_init(void); + +int __clk_enable(struct clk *); +int clk_enable(struct clk *); + +void __clk_disable(struct clk *); +void clk_disable(struct clk *); + +int clk_set_rate(struct clk *, unsigned long rate); +unsigned long clk_get_rate(struct clk *); +void clk_recalc_rate(struct clk *); + +struct clk *clk_get(const char *id); +void clk_put(struct clk *); + +int clk_register(struct clk *); +void clk_unregister(struct clk *); + +int show_clocks(struct seq_file *m); + +#endif /* __ASM_SH_CLOCK_H */ + diff --git a/include/asm-sh/cpu-sh3/dma.h b/include/asm-sh/cpu-sh3/dma.h index b972e715f9ee..954801b46022 100644 --- a/include/asm-sh/cpu-sh3/dma.h +++ b/include/asm-sh/cpu-sh3/dma.h @@ -3,5 +3,34 @@ #define SH_DMAC_BASE 0xa4000020 -#endif /* __ASM_CPU_SH3_DMA_H */ +/* Definitions for the SuperH DMAC */ +#define TM_BURST 0x00000020 +#define TS_8 0x00000000 +#define TS_16 0x00000008 +#define TS_32 0x00000010 +#define TS_128 0x00000018 + +#define CHCR_TS_MASK 0x18 +#define CHCR_TS_SHIFT 3 + +#define DMAOR_INIT DMAOR_DME +/* + * The SuperH DMAC supports a number of transmit sizes, we list them here, + * with their respective values as they appear in the CHCR registers. + */ +enum { + XMIT_SZ_8BIT, + XMIT_SZ_16BIT, + XMIT_SZ_32BIT, + XMIT_SZ_128BIT, +}; + +static unsigned int ts_shift[] __attribute__ ((used)) = { + [XMIT_SZ_8BIT] = 0, + [XMIT_SZ_16BIT] = 1, + [XMIT_SZ_32BIT] = 2, + [XMIT_SZ_128BIT] = 4, +}; + +#endif /* __ASM_CPU_SH3_DMA_H */ diff --git a/include/asm-sh/cpu-sh4/dma.h b/include/asm-sh/cpu-sh4/dma.h index e2b91adf821a..0dfe61f14802 100644 --- a/include/asm-sh/cpu-sh4/dma.h +++ b/include/asm-sh/cpu-sh4/dma.h @@ -1,17 +1,49 @@ #ifndef __ASM_CPU_SH4_DMA_H #define __ASM_CPU_SH4_DMA_H +#ifdef CONFIG_CPU_SH4A +#define SH_DMAC_BASE 0xfc808020 +#else #define SH_DMAC_BASE 0xffa00000 +#endif -#define SAR ((unsigned long[]){SH_DMAC_BASE + 0x00, SH_DMAC_BASE + 0x10, \ - SH_DMAC_BASE + 0x20, SH_DMAC_BASE + 0x30}) -#define DAR ((unsigned long[]){SH_DMAC_BASE + 0x04, SH_DMAC_BASE + 0x14, \ - SH_DMAC_BASE + 0x24, SH_DMAC_BASE + 0x34}) -#define DMATCR ((unsigned long[]){SH_DMAC_BASE + 0x08, SH_DMAC_BASE + 0x18, \ - SH_DMAC_BASE + 0x28, SH_DMAC_BASE + 0x38}) -#define CHCR ((unsigned long[]){SH_DMAC_BASE + 0x0c, SH_DMAC_BASE + 0x1c, \ - SH_DMAC_BASE + 0x2c, SH_DMAC_BASE + 0x3c}) -#define DMAOR (SH_DMAC_BASE + 0x40) +/* Definitions for the SuperH DMAC */ +#define TM_BURST 0x0000080 +#define TS_8 0x00000010 +#define TS_16 0x00000020 +#define TS_32 0x00000030 +#define TS_64 0x00000000 -#endif /* __ASM_CPU_SH4_DMA_H */ +#define CHCR_TS_MASK 0x30 +#define CHCR_TS_SHIFT 4 + +#define DMAOR_COD 0x00000008 + +#define DMAOR_INIT ( 0x8000 | DMAOR_DME ) +/* + * The SuperH DMAC supports a number of transmit sizes, we list them here, + * with their respective values as they appear in the CHCR registers. + * + * Defaults to a 64-bit transfer size. + */ +enum { + XMIT_SZ_64BIT, + XMIT_SZ_8BIT, + XMIT_SZ_16BIT, + XMIT_SZ_32BIT, + XMIT_SZ_256BIT, +}; + +/* + * The DMA count is defined as the number of bytes to transfer. + */ +static unsigned int ts_shift[] __attribute__ ((used)) = { + [XMIT_SZ_64BIT] = 3, + [XMIT_SZ_8BIT] = 0, + [XMIT_SZ_16BIT] = 1, + [XMIT_SZ_32BIT] = 2, + [XMIT_SZ_256BIT] = 5, +}; + +#endif /* __ASM_CPU_SH4_DMA_H */ diff --git a/include/asm-sh/cpu-sh4/freq.h b/include/asm-sh/cpu-sh4/freq.h index 201d94fd214f..ef2b9b1ae41f 100644 --- a/include/asm-sh/cpu-sh4/freq.h +++ b/include/asm-sh/cpu-sh4/freq.h @@ -12,6 +12,8 @@ #if defined(CONFIG_CPU_SUBTYPE_SH73180) #define FRQCR 0xa4150000 +#elif defined(CONFIG_CPU_SUBTYPE_SH7780) +#define FRQCR 0xffc80000 #else #define FRQCR 0xffc00000 #endif diff --git a/include/asm-sh/dma-mapping.h b/include/asm-sh/dma-mapping.h index d3fa5c2b889d..48f1f42c5d14 100644 --- a/include/asm-sh/dma-mapping.h +++ b/include/asm-sh/dma-mapping.h @@ -4,6 +4,7 @@ #include <linux/config.h> #include <linux/mm.h> #include <asm/scatterlist.h> +#include <asm/cacheflush.h> #include <asm/io.h> extern struct bus_type pci_bus_type; @@ -141,24 +142,24 @@ static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg, } } -static inline void dma_sync_single_for_cpu(struct device *dev, - dma_addr_t dma_handle, size_t size, - enum dma_data_direction dir) +static void dma_sync_single_for_cpu(struct device *dev, + dma_addr_t dma_handle, size_t size, + enum dma_data_direction dir) __attribute__ ((alias("dma_sync_single"))); -static inline void dma_sync_single_for_device(struct device *dev, - dma_addr_t dma_handle, size_t size, - enum dma_data_direction dir) +static void dma_sync_single_for_device(struct device *dev, + dma_addr_t dma_handle, size_t size, + enum dma_data_direction dir) __attribute__ ((alias("dma_sync_single"))); -static inline void dma_sync_sg_for_cpu(struct device *dev, - struct scatterlist *sg, int nelems, - enum dma_data_direction dir) +static void dma_sync_sg_for_cpu(struct device *dev, + struct scatterlist *sg, int nelems, + enum dma_data_direction dir) __attribute__ ((alias("dma_sync_sg"))); -static inline void dma_sync_sg_for_device(struct device *dev, - struct scatterlist *sg, int nelems, - enum dma_data_direction dir) +static void dma_sync_sg_for_device(struct device *dev, + struct scatterlist *sg, int nelems, + enum dma_data_direction dir) __attribute__ ((alias("dma_sync_sg"))); static inline int dma_get_cache_alignment(void) diff --git a/include/asm-sh/dma.h b/include/asm-sh/dma.h index 8e9436093ca8..a118a0d43053 100644 --- a/include/asm-sh/dma.h +++ b/include/asm-sh/dma.h @@ -15,6 +15,7 @@ #include <linux/spinlock.h> #include <linux/wait.h> #include <linux/sysdev.h> +#include <linux/device.h> #include <asm/cpu/dma.h> #include <asm/semaphore.h> @@ -54,8 +55,8 @@ enum { * DMA channel capabilities / flags */ enum { - DMA_CONFIGURED = 0x00, DMA_TEI_CAPABLE = 0x01, + DMA_CONFIGURED = 0x02, }; extern spinlock_t dma_spin_lock; @@ -74,7 +75,8 @@ struct dma_ops { struct dma_channel { char dev_id[16]; - unsigned int chan; + unsigned int chan; /* Physical channel number */ + unsigned int vchan; /* Virtual channel number */ unsigned int mode; unsigned int count; @@ -91,6 +93,8 @@ struct dma_channel { }; struct dma_info { + struct platform_device *pdev; + const char *name; unsigned int nr_channels; unsigned long flags; @@ -130,7 +134,11 @@ extern void unregister_dmac(struct dma_info *info); #ifdef CONFIG_SYSFS /* arch/sh/drivers/dma/dma-sysfs.c */ -extern int dma_create_sysfs_files(struct dma_channel *); +extern int dma_create_sysfs_files(struct dma_channel *, struct dma_info *); +extern void dma_remove_sysfs_files(struct dma_channel *, struct dma_info *); +#else +#define dma_create_sysfs_file(channel, info) do { } while (0) +#define dma_remove_sysfs_file(channel, info) do { } while (0) #endif #ifdef CONFIG_PCI diff --git a/include/asm-sh/freq.h b/include/asm-sh/freq.h index 2c0fde46a0ed..39c0e091cf58 100644 --- a/include/asm-sh/freq.h +++ b/include/asm-sh/freq.h @@ -14,16 +14,5 @@ #include <asm/cpu/freq.h> -/* arch/sh/kernel/time.c */ -extern void get_current_frequency_divisors(unsigned int *ifc, unsigned int *pfc, unsigned int *bfc); - -extern unsigned int get_ifc_divisor(unsigned int value); -extern unsigned int get_ifc_divisor(unsigned int value); -extern unsigned int get_ifc_divisor(unsigned int value); - -extern unsigned int get_ifc_value(unsigned int divisor); -extern unsigned int get_pfc_value(unsigned int divisor); -extern unsigned int get_bfc_value(unsigned int divisor); - #endif /* __KERNEL__ */ #endif /* __ASM_SH_FREQ_H */ diff --git a/include/asm-sh/futex.h b/include/asm-sh/futex.h index 9feff4ce1424..6a332a9f099c 100644 --- a/include/asm-sh/futex.h +++ b/include/asm-sh/futex.h @@ -1,53 +1,6 @@ #ifndef _ASM_FUTEX_H #define _ASM_FUTEX_H -#ifdef __KERNEL__ +#include <asm-generic/futex.h> -#include <linux/futex.h> -#include <asm/errno.h> -#include <asm/uaccess.h> - -static inline int -futex_atomic_op_inuser (int encoded_op, int __user *uaddr) -{ - int op = (encoded_op >> 28) & 7; - int cmp = (encoded_op >> 24) & 15; - int oparg = (encoded_op << 8) >> 20; - int cmparg = (encoded_op << 20) >> 20; - int oldval = 0, ret; - if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) - oparg = 1 << oparg; - - if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int))) - return -EFAULT; - - inc_preempt_count(); - - switch (op) { - case FUTEX_OP_SET: - case FUTEX_OP_ADD: - case FUTEX_OP_OR: - case FUTEX_OP_ANDN: - case FUTEX_OP_XOR: - default: - ret = -ENOSYS; - } - - dec_preempt_count(); - - if (!ret) { - switch (cmp) { - case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break; - case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break; - case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break; - case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break; - case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break; - case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break; - default: ret = -ENOSYS; - } - } - return ret; -} - -#endif #endif diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h index 6bc343fee7a0..b0b2937b6f83 100644 --- a/include/asm-sh/io.h +++ b/include/asm-sh/io.h @@ -11,7 +11,7 @@ * For read{b,w,l} and write{b,w,l} there are also __raw versions, which * do not have a memory barrier after them. * - * In addition, we have + * In addition, we have * ctrl_in{b,w,l}/ctrl_out{b,w,l} for SuperH specific I/O. * which are processor specific. */ @@ -23,19 +23,27 @@ * inb by default expands to _inb, but the machine specific code may * define it to __inb if it chooses. */ - +#include <linux/config.h> #include <asm/cache.h> #include <asm/system.h> #include <asm/addrspace.h> #include <asm/machvec.h> -#include <linux/config.h> +#include <asm/pgtable.h> +#include <asm-generic/iomap.h> + +#ifdef __KERNEL__ /* * Depending on which platform we are running on, we need different * I/O functions. */ +#define __IO_PREFIX generic +#include <asm/io_generic.h> + +#define maybebadio(port) \ + printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \ + __FUNCTION__, __LINE__, (port), (u32)__builtin_return_address(0)) -#ifdef __KERNEL__ /* * Since boards are able to define their own set of I/O routines through * their respective machine vector, we always wrap through the mv. @@ -44,113 +52,120 @@ * a given routine, it will be wrapped to generic code at run-time. */ -# define __inb(p) sh_mv.mv_inb((p)) -# define __inw(p) sh_mv.mv_inw((p)) -# define __inl(p) sh_mv.mv_inl((p)) -# define __outb(x,p) sh_mv.mv_outb((x),(p)) -# define __outw(x,p) sh_mv.mv_outw((x),(p)) -# define __outl(x,p) sh_mv.mv_outl((x),(p)) - -# define __inb_p(p) sh_mv.mv_inb_p((p)) -# define __inw_p(p) sh_mv.mv_inw_p((p)) -# define __inl_p(p) sh_mv.mv_inl_p((p)) -# define __outb_p(x,p) sh_mv.mv_outb_p((x),(p)) -# define __outw_p(x,p) sh_mv.mv_outw_p((x),(p)) -# define __outl_p(x,p) sh_mv.mv_outl_p((x),(p)) - -# define __insb(p,b,c) sh_mv.mv_insb((p), (b), (c)) -# define __insw(p,b,c) sh_mv.mv_insw((p), (b), (c)) -# define __insl(p,b,c) sh_mv.mv_insl((p), (b), (c)) -# define __outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c)) -# define __outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c)) -# define __outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c)) - -# define __readb(a) sh_mv.mv_readb((a)) -# define __readw(a) sh_mv.mv_readw((a)) -# define __readl(a) sh_mv.mv_readl((a)) -# define __writeb(v,a) sh_mv.mv_writeb((v),(a)) -# define __writew(v,a) sh_mv.mv_writew((v),(a)) -# define __writel(v,a) sh_mv.mv_writel((v),(a)) - -# define __ioremap(a,s) sh_mv.mv_ioremap((a), (s)) -# define __iounmap(a) sh_mv.mv_iounmap((a)) - -# define __isa_port2addr(a) sh_mv.mv_isa_port2addr(a) - -# define inb __inb -# define inw __inw -# define inl __inl -# define outb __outb -# define outw __outw -# define outl __outl - -# define inb_p __inb_p -# define inw_p __inw_p -# define inl_p __inl_p -# define outb_p __outb_p -# define outw_p __outw_p -# define outl_p __outl_p - -# define insb __insb -# define insw __insw -# define insl __insl -# define outsb __outsb -# define outsw __outsw -# define outsl __outsl - -# define __raw_readb __readb -# define __raw_readw __readw -# define __raw_readl __readl -# define __raw_writeb __writeb -# define __raw_writew __writew -# define __raw_writel __writel +#define __inb(p) sh_mv.mv_inb((p)) +#define __inw(p) sh_mv.mv_inw((p)) +#define __inl(p) sh_mv.mv_inl((p)) +#define __outb(x,p) sh_mv.mv_outb((x),(p)) +#define __outw(x,p) sh_mv.mv_outw((x),(p)) +#define __outl(x,p) sh_mv.mv_outl((x),(p)) + +#define __inb_p(p) sh_mv.mv_inb_p((p)) +#define __inw_p(p) sh_mv.mv_inw_p((p)) +#define __inl_p(p) sh_mv.mv_inl_p((p)) +#define __outb_p(x,p) sh_mv.mv_outb_p((x),(p)) +#define __outw_p(x,p) sh_mv.mv_outw_p((x),(p)) +#define __outl_p(x,p) sh_mv.mv_outl_p((x),(p)) + +#define __insb(p,b,c) sh_mv.mv_insb((p), (b), (c)) +#define __insw(p,b,c) sh_mv.mv_insw((p), (b), (c)) +#define __insl(p,b,c) sh_mv.mv_insl((p), (b), (c)) +#define __outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c)) +#define __outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c)) +#define __outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c)) + +#define __readb(a) sh_mv.mv_readb((a)) +#define __readw(a) sh_mv.mv_readw((a)) +#define __readl(a) sh_mv.mv_readl((a)) +#define __writeb(v,a) sh_mv.mv_writeb((v),(a)) +#define __writew(v,a) sh_mv.mv_writew((v),(a)) +#define __writel(v,a) sh_mv.mv_writel((v),(a)) + +#define inb __inb +#define inw __inw +#define inl __inl +#define outb __outb +#define outw __outw +#define outl __outl + +#define inb_p __inb_p +#define inw_p __inw_p +#define inl_p __inl_p +#define outb_p __outb_p +#define outw_p __outw_p +#define outl_p __outl_p + +#define insb __insb +#define insw __insw +#define insl __insl +#define outsb __outsb +#define outsw __outsw +#define outsl __outsl + +#define __raw_readb(a) __readb((void __iomem *)(a)) +#define __raw_readw(a) __readw((void __iomem *)(a)) +#define __raw_readl(a) __readl((void __iomem *)(a)) +#define __raw_writeb(v, a) __writeb(v, (void __iomem *)(a)) +#define __raw_writew(v, a) __writew(v, (void __iomem *)(a)) +#define __raw_writel(v, a) __writel(v, (void __iomem *)(a)) /* * The platform header files may define some of these macros to use * the inlined versions where appropriate. These macros may also be * redefined by userlevel programs. */ -#ifdef __raw_readb -# define readb(a) ({ unsigned long r_ = __raw_readb((unsigned long)a); mb(); r_; }) +#ifdef __readb +# define readb(a) ({ unsigned long r_ = __raw_readb(a); mb(); r_; }) #endif #ifdef __raw_readw -# define readw(a) ({ unsigned long r_ = __raw_readw((unsigned long)a); mb(); r_; }) +# define readw(a) ({ unsigned long r_ = __raw_readw(a); mb(); r_; }) #endif #ifdef __raw_readl -# define readl(a) ({ unsigned long r_ = __raw_readl((unsigned long)a); mb(); r_; }) +# define readl(a) ({ unsigned long r_ = __raw_readl(a); mb(); r_; }) #endif #ifdef __raw_writeb -# define writeb(v,a) ({ __raw_writeb((v),(unsigned long)(a)); mb(); }) +# define writeb(v,a) ({ __raw_writeb((v),(a)); mb(); }) #endif #ifdef __raw_writew -# define writew(v,a) ({ __raw_writew((v),(unsigned long)(a)); mb(); }) +# define writew(v,a) ({ __raw_writew((v),(a)); mb(); }) #endif #ifdef __raw_writel -# define writel(v,a) ({ __raw_writel((v),(unsigned long)(a)); mb(); }) +# define writel(v,a) ({ __raw_writel((v),(a)); mb(); }) #endif #define readb_relaxed(a) readb(a) #define readw_relaxed(a) readw(a) #define readl_relaxed(a) readl(a) -#define mmiowb() +/* Simple MMIO */ +#define ioread8(a) readb(a) +#define ioread16(a) readw(a) +#define ioread16be(a) be16_to_cpu(__raw_readw((a))) +#define ioread32(a) readl(a) +#define ioread32be(a) be32_to_cpu(__raw_readl((a))) -/* - * If the platform has PC-like I/O, this function converts the offset into - * an address. - */ -static __inline__ unsigned long isa_port2addr(unsigned long offset) -{ - return __isa_port2addr(offset); -} +#define iowrite8(v,a) writeb((v),(a)) +#define iowrite16(v,a) writew((v),(a)) +#define iowrite16be(v,a) __raw_writew(cpu_to_be16((v)),(a)) +#define iowrite32(v,a) writel((v),(a)) +#define iowrite32be(v,a) __raw_writel(cpu_to_be32((v)),(a)) + +#define ioread8_rep(a,d,c) insb((a),(d),(c)) +#define ioread16_rep(a,d,c) insw((a),(d),(c)) +#define ioread32_rep(a,d,c) insl((a),(d),(c)) + +#define iowrite8_rep(a,s,c) outsb((a),(s),(c)) +#define iowrite16_rep(a,s,c) outsw((a),(s),(c)) +#define iowrite32_rep(a,s,c) outsl((a),(s),(c)) + +#define mmiowb() wmb() /* synco on SH-4A, otherwise a nop */ /* * This function provides a method for the generic case where a board-specific - * isa_port2addr simply needs to return the port + some arbitrary port base. + * ioport_map simply needs to return the port + some arbitrary port base. * * We use this at board setup time to implicitly set the port base, and - * as a result, we can use the generic isa_port2addr. + * as a result, we can use the generic ioport_map. */ static inline void __set_io_port_base(unsigned long pbase) { @@ -159,51 +174,52 @@ static inline void __set_io_port_base(unsigned long pbase) generic_io_base = pbase; } -#define isa_readb(a) readb(isa_port2addr(a)) -#define isa_readw(a) readw(isa_port2addr(a)) -#define isa_readl(a) readl(isa_port2addr(a)) -#define isa_writeb(b,a) writeb(b,isa_port2addr(a)) -#define isa_writew(w,a) writew(w,isa_port2addr(a)) -#define isa_writel(l,a) writel(l,isa_port2addr(a)) +#define isa_readb(a) readb(ioport_map(a, 1)) +#define isa_readw(a) readw(ioport_map(a, 2)) +#define isa_readl(a) readl(ioport_map(a, 4)) +#define isa_writeb(b,a) writeb(b,ioport_map(a, 1)) +#define isa_writew(w,a) writew(w,ioport_map(a, 2)) +#define isa_writel(l,a) writel(l,ioport_map(a, 4)) + #define isa_memset_io(a,b,c) \ - memset((void *)(isa_port2addr((unsigned long)a)),(b),(c)) + memset((void *)(ioport_map((unsigned long)(a), 1)),(b),(c)) #define isa_memcpy_fromio(a,b,c) \ - memcpy((a),(void *)(isa_port2addr((unsigned long)(b))),(c)) + memcpy((a),(void *)(ioport_map((unsigned long)(b), 1)),(c)) #define isa_memcpy_toio(a,b,c) \ - memcpy((void *)(isa_port2addr((unsigned long)(a))),(b),(c)) + memcpy((void *)(ioport_map((unsigned long)(a), 1)),(b),(c)) /* We really want to try and get these to memcpy etc */ -extern void memcpy_fromio(void *, unsigned long, unsigned long); -extern void memcpy_toio(unsigned long, const void *, unsigned long); -extern void memset_io(unsigned long, int, unsigned long); +extern void memcpy_fromio(void *, volatile void __iomem *, unsigned long); +extern void memcpy_toio(volatile void __iomem *, const void *, unsigned long); +extern void memset_io(volatile void __iomem *, int, unsigned long); /* SuperH on-chip I/O functions */ -static __inline__ unsigned char ctrl_inb(unsigned long addr) +static inline unsigned char ctrl_inb(unsigned long addr) { return *(volatile unsigned char*)addr; } -static __inline__ unsigned short ctrl_inw(unsigned long addr) +static inline unsigned short ctrl_inw(unsigned long addr) { return *(volatile unsigned short*)addr; } -static __inline__ unsigned int ctrl_inl(unsigned long addr) +static inline unsigned int ctrl_inl(unsigned long addr) { return *(volatile unsigned long*)addr; } -static __inline__ void ctrl_outb(unsigned char b, unsigned long addr) +static inline void ctrl_outb(unsigned char b, unsigned long addr) { *(volatile unsigned char*)addr = b; } -static __inline__ void ctrl_outw(unsigned short b, unsigned long addr) +static inline void ctrl_outw(unsigned short b, unsigned long addr) { *(volatile unsigned short*)addr = b; } -static __inline__ void ctrl_outl(unsigned int b, unsigned long addr) +static inline void ctrl_outl(unsigned int b, unsigned long addr) { *(volatile unsigned long*)addr = b; } @@ -214,12 +230,12 @@ static __inline__ void ctrl_outl(unsigned int b, unsigned long addr) * Change virtual addresses to physical addresses and vv. * These are trivial on the 1:1 Linux/SuperH mapping */ -static __inline__ unsigned long virt_to_phys(volatile void * address) +static inline unsigned long virt_to_phys(volatile void *address) { return PHYSADDR(address); } -static __inline__ void * phys_to_virt(unsigned long address) +static inline void *phys_to_virt(unsigned long address) { return (void *)P1SEGADDR(address); } @@ -234,27 +250,60 @@ static __inline__ void * phys_to_virt(unsigned long address) * differently. On the x86 architecture, we just read/write the * memory location directly. * - * On SH, we have the whole physical address space mapped at all times - * (as MIPS does), so "ioremap()" and "iounmap()" do not need to do - * anything. (This isn't true for all machines but we still handle - * these cases with wired TLB entries anyway ...) + * On SH, we traditionally have the whole physical address space mapped + * at all times (as MIPS does), so "ioremap()" and "iounmap()" do not + * need to do anything but place the address in the proper segment. This + * is true for P1 and P2 addresses, as well as some P3 ones. However, + * most of the P3 addresses and newer cores using extended addressing + * need to map through page tables, so the ioremap() implementation + * becomes a bit more complicated. See arch/sh/mm/ioremap.c for + * additional notes on this. * * We cheat a bit and always return uncachable areas until we've fixed - * the drivers to handle caching properly. + * the drivers to handle caching properly. */ -static __inline__ void * ioremap(unsigned long offset, unsigned long size) +#ifdef CONFIG_MMU +void __iomem *__ioremap(unsigned long offset, unsigned long size, + unsigned long flags); +void __iounmap(void __iomem *addr); +#else +#define __ioremap(offset, size, flags) ((void __iomem *)(offset)) +#define __iounmap(addr) do { } while (0) +#endif /* CONFIG_MMU */ + +static inline void __iomem * +__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags) { - return __ioremap(offset, size); + unsigned long last_addr = offset + size - 1; + + /* + * For P1 and P2 space this is trivial, as everything is already + * mapped. Uncached access for P1 addresses are done through P2. + * In the P3 case or for addresses outside of the 29-bit space, + * mapping must be done by the PMB or by using page tables. + */ + if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) { + if (unlikely(flags & _PAGE_CACHABLE)) + return (void __iomem *)P1SEGADDR(offset); + + return (void __iomem *)P2SEGADDR(offset); + } + + return __ioremap(offset, size, flags); } -static __inline__ void iounmap(void *addr) -{ - return __iounmap(addr); -} - -#define ioremap_nocache(off,size) ioremap(off,size) - -static __inline__ int check_signature(unsigned long io_addr, +#define ioremap(offset, size) \ + __ioremap_mode((offset), (size), 0) +#define ioremap_nocache(offset, size) \ + __ioremap_mode((offset), (size), 0) +#define ioremap_cache(offset, size) \ + __ioremap_mode((offset), (size), _PAGE_CACHABLE) +#define p3_ioremap(offset, size, flags) \ + __ioremap((offset), (size), (flags)) +#define iounmap(addr) \ + __iounmap((addr)) + +static inline int check_signature(char __iomem *io_addr, const unsigned char *signature, int length) { int retval = 0; diff --git a/include/asm-sh/io_generic.h b/include/asm-sh/io_generic.h index be14587342f7..92fc6070d7b3 100644 --- a/include/asm-sh/io_generic.h +++ b/include/asm-sh/io_generic.h @@ -1,51 +1,49 @@ /* - * include/asm-sh/io_generic.h - * - * Copyright 2000 Stuart Menefy (stuart.menefy@st.com) - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - * Generic IO functions + * Trivial I/O routine definitions, intentionally meant to be included + * multiple times. Ugly I/O routine concatenation helpers taken from + * alpha. Must be included _before_ io.h to avoid preprocessor-induced + * routine mismatch. */ - -#ifndef _ASM_SH_IO_GENERIC_H -#define _ASM_SH_IO_GENERIC_H - -extern unsigned long generic_io_base; - -extern unsigned char generic_inb(unsigned long port); -extern unsigned short generic_inw(unsigned long port); -extern unsigned int generic_inl(unsigned long port); - -extern void generic_outb(unsigned char value, unsigned long port); -extern void generic_outw(unsigned short value, unsigned long port); -extern void generic_outl(unsigned int value, unsigned long port); - -extern unsigned char generic_inb_p(unsigned long port); -extern unsigned short generic_inw_p(unsigned long port); -extern unsigned int generic_inl_p(unsigned long port); -extern void generic_outb_p(unsigned char value, unsigned long port); -extern void generic_outw_p(unsigned short value, unsigned long port); -extern void generic_outl_p(unsigned int value, unsigned long port); - -extern void generic_insb(unsigned long port, void *addr, unsigned long count); -extern void generic_insw(unsigned long port, void *addr, unsigned long count); -extern void generic_insl(unsigned long port, void *addr, unsigned long count); -extern void generic_outsb(unsigned long port, const void *addr, unsigned long count); -extern void generic_outsw(unsigned long port, const void *addr, unsigned long count); -extern void generic_outsl(unsigned long port, const void *addr, unsigned long count); - -extern unsigned char generic_readb(unsigned long addr); -extern unsigned short generic_readw(unsigned long addr); -extern unsigned int generic_readl(unsigned long addr); -extern void generic_writeb(unsigned char b, unsigned long addr); -extern void generic_writew(unsigned short b, unsigned long addr); -extern void generic_writel(unsigned int b, unsigned long addr); - -extern void *generic_ioremap(unsigned long offset, unsigned long size); -extern void generic_iounmap(void *addr); - -extern unsigned long generic_isa_port2addr(unsigned long offset); - -#endif /* _ASM_SH_IO_GENERIC_H */ +#define IO_CONCAT(a,b) _IO_CONCAT(a,b) +#define _IO_CONCAT(a,b) a ## _ ## b + +#ifndef __IO_PREFIX +#error "Don't include this header without a valid system prefix" +#endif + +u8 IO_CONCAT(__IO_PREFIX,inb)(unsigned long); +u16 IO_CONCAT(__IO_PREFIX,inw)(unsigned long); +u32 IO_CONCAT(__IO_PREFIX,inl)(unsigned long); + +void IO_CONCAT(__IO_PREFIX,outb)(u8, unsigned long); +void IO_CONCAT(__IO_PREFIX,outw)(u16, unsigned long); +void IO_CONCAT(__IO_PREFIX,outl)(u32, unsigned long); + +u8 IO_CONCAT(__IO_PREFIX,inb_p)(unsigned long); +u16 IO_CONCAT(__IO_PREFIX,inw_p)(unsigned long); +u32 IO_CONCAT(__IO_PREFIX,inl_p)(unsigned long); +void IO_CONCAT(__IO_PREFIX,outb_p)(u8, unsigned long); +void IO_CONCAT(__IO_PREFIX,outw_p)(u16, unsigned long); +void IO_CONCAT(__IO_PREFIX,outl_p)(u32, unsigned long); + +void IO_CONCAT(__IO_PREFIX,insb)(unsigned long, void *dst, unsigned long count); +void IO_CONCAT(__IO_PREFIX,insw)(unsigned long, void *dst, unsigned long count); +void IO_CONCAT(__IO_PREFIX,insl)(unsigned long, void *dst, unsigned long count); +void IO_CONCAT(__IO_PREFIX,outsb)(unsigned long, const void *src, unsigned long count); +void IO_CONCAT(__IO_PREFIX,outsw)(unsigned long, const void *src, unsigned long count); +void IO_CONCAT(__IO_PREFIX,outsl)(unsigned long, const void *src, unsigned long count); + +u8 IO_CONCAT(__IO_PREFIX,readb)(void __iomem *); +u16 IO_CONCAT(__IO_PREFIX,readw)(void __iomem *); +u32 IO_CONCAT(__IO_PREFIX,readl)(void __iomem *); +void IO_CONCAT(__IO_PREFIX,writeb)(u8, void __iomem *); +void IO_CONCAT(__IO_PREFIX,writew)(u16, void __iomem *); +void IO_CONCAT(__IO_PREFIX,writel)(u32, void __iomem *); + +void *IO_CONCAT(__IO_PREFIX,ioremap)(unsigned long offset, unsigned long size); +void IO_CONCAT(__IO_PREFIX,iounmap)(void *addr); + +void __iomem *IO_CONCAT(__IO_PREFIX,ioport_map)(unsigned long addr, unsigned int size); +void IO_CONCAT(__IO_PREFIX,ioport_unmap)(void __iomem *addr); + +#undef __IO_PREFIX diff --git a/include/asm-sh/ioctl.h b/include/asm-sh/ioctl.h index 524700e84acd..b279fe06dfe5 100644 --- a/include/asm-sh/ioctl.h +++ b/include/asm-sh/ioctl.h @@ -1,75 +1 @@ -/* $Id: ioctl.h,v 1.1.1.1 2001/10/15 20:45:09 mrbrown Exp $ - * - * linux/ioctl.h for Linux by H.H. Bergman. - */ - -#ifndef __ASM_SH_IOCTL_H -#define __ASM_SH_IOCTL_H - -/* ioctl command encoding: 32 bits total, command in lower 16 bits, - * size of the parameter structure in the lower 14 bits of the - * upper 16 bits. - * Encoding the size of the parameter structure in the ioctl request - * is useful for catching programs compiled with old versions - * and to avoid overwriting user space outside the user buffer area. - * The highest 2 bits are reserved for indicating the ``access mode''. - * NOTE: This limits the max parameter size to 16kB -1 ! - */ - -/* - * The following is for compatibility across the various Linux - * platforms. The i386 ioctl numbering scheme doesn't really enforce - * a type field. De facto, however, the top 8 bits of the lower 16 - * bits are indeed used as a type field, so we might just as well make - * this explicit here. Please be sure to use the decoding macros - * below from now on. - */ -#define _IOC_NRBITS 8 -#define _IOC_TYPEBITS 8 -#define _IOC_SIZEBITS 14 -#define _IOC_DIRBITS 2 - -#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1) -#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1) -#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1) -#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1) - -#define _IOC_NRSHIFT 0 -#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS) -#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS) -#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS) - -/* - * Direction bits. - */ -#define _IOC_NONE 0U -#define _IOC_WRITE 1U -#define _IOC_READ 2U - -#define _IOC(dir,type,nr,size) \ - (((dir) << _IOC_DIRSHIFT) | \ - ((type) << _IOC_TYPESHIFT) | \ - ((nr) << _IOC_NRSHIFT) | \ - ((size) << _IOC_SIZESHIFT)) - -/* used to create numbers */ -#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) -#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) -#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) -#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) - -/* used to decode ioctl numbers.. */ -#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) -#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK) -#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK) -#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK) - -/* ...and for the drivers/sound files... */ - -#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT) -#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT) -#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT) -#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT) -#define IOCSIZE_SHIFT (_IOC_SIZESHIFT) - -#endif /* __ASM_SH_IOCTL_H */ +#include <asm-generic/ioctl.h> diff --git a/include/asm-sh/irq-sh7780.h b/include/asm-sh/irq-sh7780.h new file mode 100644 index 000000000000..8c8ca1281084 --- /dev/null +++ b/include/asm-sh/irq-sh7780.h @@ -0,0 +1,349 @@ +#ifndef __ASM_SH_IRQ_SH7780_H +#define __ASM_SH_IRQ_SH7780_H + +/* + * linux/include/asm-sh/irq-sh7780.h + * + * Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp> + */ + +#ifdef CONFIG_IDE +# ifndef IRQ_CFCARD +# define IRQ_CFCARD 14 +# endif +# ifndef IRQ_PCMCIA +# define IRQ_PCMCIA 15 +# endif +#endif + +#define INTC_BASE 0xffd00000 +#define INTC_ICR0 (INTC_BASE+0x0) +#define INTC_ICR1 (INTC_BASE+0x1c) +#define INTC_INTPRI (INTC_BASE+0x10) +#define INTC_INTREQ (INTC_BASE+0x24) +#define INTC_INTMSK0 (INTC_BASE+0x44) +#define INTC_INTMSK1 (INTC_BASE+0x48) +#define INTC_INTMSK2 (INTC_BASE+0x40080) +#define INTC_INTMSKCLR0 (INTC_BASE+0x64) +#define INTC_INTMSKCLR1 (INTC_BASE+0x68) +#define INTC_INTMSKCLR2 (INTC_BASE+0x40084) +#define INTC_NMIFCR (INTC_BASE+0xc0) +#define INTC_USERIMASK (INTC_BASE+0x30000) + +#define INTC_INT2PRI0 (INTC_BASE+0x40000) +#define INTC_INT2PRI1 (INTC_BASE+0x40004) +#define INTC_INT2PRI2 (INTC_BASE+0x40008) +#define INTC_INT2PRI3 (INTC_BASE+0x4000c) +#define INTC_INT2PRI4 (INTC_BASE+0x40010) +#define INTC_INT2PRI5 (INTC_BASE+0x40014) +#define INTC_INT2PRI6 (INTC_BASE+0x40018) +#define INTC_INT2PRI7 (INTC_BASE+0x4001c) +#define INTC_INT2A0 (INTC_BASE+0x40030) +#define INTC_INT2A1 (INTC_BASE+0x40034) +#define INTC_INT2MSKR (INTC_BASE+0x40038) +#define INTC_INT2MSKCR (INTC_BASE+0x4003c) +#define INTC_INT2B0 (INTC_BASE+0x40040) +#define INTC_INT2B1 (INTC_BASE+0x40044) +#define INTC_INT2B2 (INTC_BASE+0x40048) +#define INTC_INT2B3 (INTC_BASE+0x4004c) +#define INTC_INT2B4 (INTC_BASE+0x40050) +#define INTC_INT2B5 (INTC_BASE+0x40054) +#define INTC_INT2B6 (INTC_BASE+0x40058) +#define INTC_INT2B7 (INTC_BASE+0x4005c) +#define INTC_INT2GPIC (INTC_BASE+0x40090) +/* + NOTE: + *_IRQ = (INTEVT2 - 0x200)/0x20 +*/ +/* IRQ 0-7 line external int*/ +#define IRQ0_IRQ 2 +#define IRQ0_IPR_ADDR INTC_INTPRI +#define IRQ0_IPR_POS 7 +#define IRQ0_PRIORITY 2 + +#define IRQ1_IRQ 4 +#define IRQ1_IPR_ADDR INTC_INTPRI +#define IRQ1_IPR_POS 6 +#define IRQ1_PRIORITY 2 + +#define IRQ2_IRQ 6 +#define IRQ2_IPR_ADDR INTC_INTPRI +#define IRQ2_IPR_POS 5 +#define IRQ2_PRIORITY 2 + +#define IRQ3_IRQ 8 +#define IRQ3_IPR_ADDR INTC_INTPRI +#define IRQ3_IPR_POS 4 +#define IRQ3_PRIORITY 2 + +#define IRQ4_IRQ 10 +#define IRQ4_IPR_ADDR INTC_INTPRI +#define IRQ4_IPR_POS 3 +#define IRQ4_PRIORITY 2 + +#define IRQ5_IRQ 12 +#define IRQ5_IPR_ADDR INTC_INTPRI +#define IRQ5_IPR_POS 2 +#define IRQ5_PRIORITY 2 + +#define IRQ6_IRQ 14 +#define IRQ6_IPR_ADDR INTC_INTPRI +#define IRQ6_IPR_POS 1 +#define IRQ6_PRIORITY 2 + +#define IRQ7_IRQ 0 +#define IRQ7_IPR_ADDR INTC_INTPRI +#define IRQ7_IPR_POS 0 +#define IRQ7_PRIORITY 2 + +/* TMU */ +/* ch0 */ +#define TMU_IRQ 28 +#define TMU_IPR_ADDR INTC_INT2PRI0 +#define TMU_IPR_POS 3 +#define TMU_PRIORITY 2 + +#define TIMER_IRQ 28 +#define TIMER_IPR_ADDR INTC_INT2PRI0 +#define TIMER_IPR_POS 3 +#define TIMER_PRIORITY 2 + +/* ch 1*/ +#define TMU_CH1_IRQ 29 +#define TMU_CH1_IPR_ADDR INTC_INT2PRI0 +#define TMU_CH1_IPR_POS 2 +#define TMU_CH1_PRIORITY 2 + +#define TIMER1_IRQ 29 +#define TIMER1_IPR_ADDR INTC_INT2PRI0 +#define TIMER1_IPR_POS 2 +#define TIMER1_PRIORITY 2 + +/* ch 2*/ +#define TMU_CH2_IRQ 30 +#define TMU_CH2_IPR_ADDR INTC_INT2PRI0 +#define TMU_CH2_IPR_POS 1 +#define TMU_CH2_PRIORITY 2 +/* ch 2 Input capture */ +#define TMU_CH2IC_IRQ 31 +#define TMU_CH2IC_IPR_ADDR INTC_INT2PRI0 +#define TMU_CH2IC_IPR_POS 0 +#define TMU_CH2IC_PRIORITY 2 +/* ch 3 */ +#define TMU_CH3_IRQ 96 +#define TMU_CH3_IPR_ADDR INTC_INT2PRI1 +#define TMU_CH3_IPR_POS 3 +#define TMU_CH3_PRIORITY 2 +/* ch 4 */ +#define TMU_CH4_IRQ 97 +#define TMU_CH4_IPR_ADDR INTC_INT2PRI1 +#define TMU_CH4_IPR_POS 2 +#define TMU_CH4_PRIORITY 2 +/* ch 5*/ +#define TMU_CH5_IRQ 98 +#define TMU_CH5_IPR_ADDR INTC_INT2PRI1 +#define TMU_CH5_IPR_POS 1 +#define TMU_CH5_PRIORITY 2 + +#define RTC_IRQ 22 +#define RTC_IPR_ADDR INTC_INT2PRI1 +#define RTC_IPR_POS 0 +#define RTC_PRIORITY TIMER_PRIORITY + +/* SCIF0 */ +#define SCIF0_ERI_IRQ 40 +#define SCIF0_RXI_IRQ 41 +#define SCIF0_BRI_IRQ 42 +#define SCIF0_TXI_IRQ 43 +#define SCIF0_IPR_ADDR INTC_INT2PRI2 +#define SCIF0_IPR_POS 3 +#define SCIF0_PRIORITY 3 + +/* SCIF1 */ +#define SCIF1_ERI_IRQ 76 +#define SCIF1_RXI_IRQ 77 +#define SCIF1_BRI_IRQ 78 +#define SCIF1_TXI_IRQ 79 +#define SCIF1_IPR_ADDR INTC_INT2PRI2 +#define SCIF1_IPR_POS 2 +#define SCIF1_PRIORITY 3 + +#define WDT_IRQ 27 +#define WDT_IPR_ADDR INTC_INT2PRI2 +#define WDT_IPR_POS 1 +#define WDT_PRIORITY 2 + +/* DMAC(0) */ +#define DMINT0_IRQ 34 +#define DMINT1_IRQ 35 +#define DMINT2_IRQ 36 +#define DMINT3_IRQ 37 +#define DMINT4_IRQ 44 +#define DMINT5_IRQ 45 +#define DMINT6_IRQ 46 +#define DMINT7_IRQ 47 +#define DMAE_IRQ 38 +#define DMA0_IPR_ADDR INTC_INT2PRI3 +#define DMA0_IPR_POS 2 +#define DMA0_PRIORITY 7 + +/* DMAC(1) */ +#define DMINT8_IRQ 92 +#define DMINT9_IRQ 93 +#define DMINT10_IRQ 94 +#define DMINT11_IRQ 95 +#define DMA1_IPR_ADDR INTC_INT2PRI3 +#define DMA1_IPR_POS 1 +#define DMA1_PRIORITY 7 + +#define DMTE0_IRQ DMINT0_IRQ +#define DMTE4_IRQ DMINT4_IRQ +#define DMA_IPR_ADDR DMA0_IPR_ADDR +#define DMA_IPR_POS DMA0_IPR_POS +#define DMA_PRIORITY DMA0_PRIORITY + +/* CMT */ +#define CMT_IRQ 56 +#define CMT_IPR_ADDR INTC_INT2PRI4 +#define CMT_IPR_POS 3 +#define CMT_PRIORITY 0 + +/* HAC */ +#define HAC_IRQ 60 +#define HAC_IPR_ADDR INTC_INT2PRI4 +#define HAC_IPR_POS 2 +#define CMT_PRIORITY 0 + +/* PCIC(0) */ +#define PCIC0_IRQ 64 +#define PCIC0_IPR_ADDR INTC_INT2PRI4 +#define PCIC0_IPR_POS 1 +#define PCIC0_PRIORITY 2 + +/* PCIC(1) */ +#define PCIC1_IRQ 65 +#define PCIC1_IPR_ADDR INTC_INT2PRI4 +#define PCIC1_IPR_POS 0 +#define PCIC1_PRIORITY 2 + +/* PCIC(2) */ +#define PCIC2_IRQ 66 +#define PCIC2_IPR_ADDR INTC_INT2PRI5 +#define PCIC2_IPR_POS 3 +#define PCIC2_PRIORITY 2 + +/* PCIC(3) */ +#define PCIC3_IRQ 67 +#define PCIC3_IPR_ADDR INTC_INT2PRI5 +#define PCIC3_IPR_POS 2 +#define PCIC3_PRIORITY 2 + +/* PCIC(4) */ +#define PCIC4_IRQ 68 +#define PCIC4_IPR_ADDR INTC_INT2PRI5 +#define PCIC4_IPR_POS 1 +#define PCIC4_PRIORITY 2 + +/* PCIC(5) */ +#define PCICERR_IRQ 69 +#define PCICPWD3_IRQ 70 +#define PCICPWD2_IRQ 71 +#define PCICPWD1_IRQ 72 +#define PCICPWD0_IRQ 73 +#define PCIC5_IPR_ADDR INTC_INT2PRI5 +#define PCIC5_IPR_POS 0 +#define PCIC5_PRIORITY 2 + +/* SIOF */ +#define SIOF_IRQ 80 +#define SIOF_IPR_ADDR INTC_INT2PRI6 +#define SIOF_IPR_POS 3 +#define SIOF_PRIORITY 3 + +/* HSPI */ +#define HSPI_IRQ 84 +#define HSPI_IPR_ADDR INTC_INT2PRI6 +#define HSPI_IPR_POS 2 +#define HSPI_PRIORITY 3 + +/* MMCIF */ +#define MMCIF_FSTAT_IRQ 88 +#define MMCIF_TRAN_IRQ 89 +#define MMCIF_ERR_IRQ 90 +#define MMCIF_FRDY_IRQ 91 +#define MMCIF_IPR_ADDR INTC_INT2PRI6 +#define MMCIF_IPR_POS 1 +#define HSPI_PRIORITY 3 + +/* SSI */ +#define SSI_IRQ 100 +#define SSI_IPR_ADDR INTC_INT2PRI6 +#define SSI_IPR_POS 0 +#define SSI_PRIORITY 3 + +/* FLCTL */ +#define FLCTL_FLSTE_IRQ 104 +#define FLCTL_FLTEND_IRQ 105 +#define FLCTL_FLTRQ0_IRQ 106 +#define FLCTL_FLTRQ1_IRQ 107 +#define FLCTL_IPR_ADDR INTC_INT2PRI7 +#define FLCTL_IPR_POS 3 +#define FLCTL_PRIORITY 3 + +/* GPIO */ +#define GPIO0_IRQ 108 +#define GPIO1_IRQ 109 +#define GPIO2_IRQ 110 +#define GPIO3_IRQ 111 +#define GPIO_IPR_ADDR INTC_INT2PRI7 +#define GPIO_IPR_POS 2 +#define GPIO_PRIORITY 3 + +/* ONCHIP_NR_IRQS */ +#define NR_IRQS 150 /* 111 + 16 */ + +/* In a generic kernel, NR_IRQS is an upper bound, and we should use + * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value. + */ +#define ACTUAL_NR_IRQS NR_IRQS + +extern void disable_irq(unsigned int); +extern void disable_irq_nosync(unsigned int); +extern void enable_irq(unsigned int); + +/* + * Simple Mask Register Support + */ +extern void make_maskreg_irq(unsigned int irq); +extern unsigned short *irq_mask_register; + +/* + * Function for "on chip support modules". + */ +extern void make_imask_irq(unsigned int irq); + +#define INTC_TMU0_MSK 0 +#define INTC_TMU3_MSK 1 +#define INTC_RTC_MSK 2 +#define INTC_SCIF0_MSK 3 +#define INTC_SCIF1_MSK 4 +#define INTC_WDT_MSK 5 +#define INTC_HUID_MSK 7 +#define INTC_DMAC0_MSK 8 +#define INTC_DMAC1_MSK 9 +#define INTC_CMT_MSK 12 +#define INTC_HAC_MSK 13 +#define INTC_PCIC0_MSK 14 +#define INTC_PCIC1_MSK 15 +#define INTC_PCIC2_MSK 16 +#define INTC_PCIC3_MSK 17 +#define INTC_PCIC4_MSK 18 +#define INTC_PCIC5_MSK 19 +#define INTC_SIOF_MSK 20 +#define INTC_HSPI_MSK 21 +#define INTC_MMCIF_MSK 22 +#define INTC_SSI_MSK 23 +#define INTC_FLCTL_MSK 24 +#define INTC_GPIO_MSK 25 + +#endif /* __ASM_SH_IRQ_SH7780_H */ diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h index 614a8c13b721..060ec3c27207 100644 --- a/include/asm-sh/irq.h +++ b/include/asm-sh/irq.h @@ -15,13 +15,20 @@ #include <asm/machvec.h> #include <asm/ptrace.h> /* for pt_regs */ -#if defined(CONFIG_SH_HP600) || \ +#if defined(CONFIG_SH_HP6XX) || \ defined(CONFIG_SH_RTS7751R2D) || \ defined(CONFIG_SH_HS7751RVOIP) || \ - defined(CONFIG_SH_SH03) + defined(CONFIG_SH_HS7751RVOIP) || \ + defined(CONFIG_SH_SH03) || \ + defined(CONFIG_SH_R7780RP) || \ + defined(CONFIG_SH_LANDISK) #include <asm/mach/ide.h> #endif +#ifndef CONFIG_CPU_SUBTYPE_SH7780 + +#define INTC_DMAC0_MSK 0 + #if defined(CONFIG_CPU_SH3) #define INTC_IPRA 0xfffffee2UL #define INTC_IPRB 0xfffffee4UL @@ -235,8 +242,9 @@ #define SCIF1_IPR_ADDR INTC_IPRB #define SCIF1_IPR_POS 1 #define SCIF1_PRIORITY 3 -#endif -#endif +#endif /* ST40STB1 */ + +#endif /* 775x / SH4-202 / ST40STB1 */ /* NR_IRQS is made from three components: * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules @@ -245,37 +253,35 @@ */ /* 1. ONCHIP_NR_IRQS */ -#ifdef CONFIG_SH_GENERIC +#if defined(CONFIG_CPU_SUBTYPE_SH7604) +# define ONCHIP_NR_IRQS 24 // Actually 21 +#elif defined(CONFIG_CPU_SUBTYPE_SH7707) +# define ONCHIP_NR_IRQS 64 +# define PINT_NR_IRQS 16 +#elif defined(CONFIG_CPU_SUBTYPE_SH7708) +# define ONCHIP_NR_IRQS 32 +#elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \ + defined(CONFIG_CPU_SUBTYPE_SH7705) +# define ONCHIP_NR_IRQS 64 // Actually 61 +# define PINT_NR_IRQS 16 +#elif defined(CONFIG_CPU_SUBTYPE_SH7750) +# define ONCHIP_NR_IRQS 48 // Actually 44 +#elif defined(CONFIG_CPU_SUBTYPE_SH7751) +# define ONCHIP_NR_IRQS 72 +#elif defined(CONFIG_CPU_SUBTYPE_SH7760) +# define ONCHIP_NR_IRQS 112 /* XXX */ +#elif defined(CONFIG_CPU_SUBTYPE_SH4_202) +# define ONCHIP_NR_IRQS 72 +#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) +# define ONCHIP_NR_IRQS 144 +#elif defined(CONFIG_CPU_SUBTYPE_SH7300) +# define ONCHIP_NR_IRQS 109 +#elif defined(CONFIG_SH_UNKNOWN) /* Most be last */ # define ONCHIP_NR_IRQS 144 -#else -# if defined(CONFIG_CPU_SUBTYPE_SH7604) -# define ONCHIP_NR_IRQS 24 // Actually 21 -# elif defined(CONFIG_CPU_SUBTYPE_SH7707) -# define ONCHIP_NR_IRQS 64 -# define PINT_NR_IRQS 16 -# elif defined(CONFIG_CPU_SUBTYPE_SH7708) -# define ONCHIP_NR_IRQS 32 -# elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \ - defined(CONFIG_CPU_SUBTYPE_SH7705) -# define ONCHIP_NR_IRQS 64 // Actually 61 -# define PINT_NR_IRQS 16 -# elif defined(CONFIG_CPU_SUBTYPE_SH7750) -# define ONCHIP_NR_IRQS 48 // Actually 44 -# elif defined(CONFIG_CPU_SUBTYPE_SH7751) -# define ONCHIP_NR_IRQS 72 -# elif defined(CONFIG_CPU_SUBTYPE_SH7760) -# define ONCHIP_NR_IRQS 110 -# elif defined(CONFIG_CPU_SUBTYPE_SH4_202) -# define ONCHIP_NR_IRQS 72 -# elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) -# define ONCHIP_NR_IRQS 144 -# elif defined(CONFIG_CPU_SUBTYPE_SH7300) -# define ONCHIP_NR_IRQS 109 -# endif #endif /* 2. PINT_NR_IRQS */ -#ifdef CONFIG_SH_GENERIC +#ifdef CONFIG_SH_UNKNOWN # define PINT_NR_IRQS 16 #else # ifndef PINT_NR_IRQS @@ -288,22 +294,22 @@ #endif /* 3. OFFCHIP_NR_IRQS */ -#ifdef CONFIG_SH_GENERIC +#if defined(CONFIG_HD64461) +# define OFFCHIP_NR_IRQS 18 +#elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */ +# define OFFCHIP_NR_IRQS 48 +#elif defined(CONFIG_HD64465) # define OFFCHIP_NR_IRQS 16 +#elif defined (CONFIG_SH_EC3104) +# define OFFCHIP_NR_IRQS 16 +#elif defined (CONFIG_SH_DREAMCAST) +# define OFFCHIP_NR_IRQS 96 +#elif defined (CONFIG_SH_TITAN) +# define OFFCHIP_NR_IRQS 4 +#elif defined(CONFIG_SH_UNKNOWN) +# define OFFCHIP_NR_IRQS 16 /* Must also be last */ #else -# if defined(CONFIG_HD64461) -# define OFFCHIP_NR_IRQS 18 -# elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */ -# define OFFCHIP_NR_IRQS 48 -# elif defined(CONFIG_HD64465) -# define OFFCHIP_NR_IRQS 16 -# elif defined (CONFIG_SH_EC3104) -# define OFFCHIP_NR_IRQS 16 -# elif defined (CONFIG_SH_DREAMCAST) -# define OFFCHIP_NR_IRQS 96 -# else -# define OFFCHIP_NR_IRQS 0 -# endif +# define OFFCHIP_NR_IRQS 0 #endif #if OFFCHIP_NR_IRQS > 0 @@ -313,16 +319,6 @@ /* NR_IRQS. 1+2+3 */ #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS) -/* In a generic kernel, NR_IRQS is an upper bound, and we should use - * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value. - */ -#ifdef CONFIG_SH_GENERIC -# define ACTUAL_NR_IRQS (sh_mv.mv_nr_irqs) -#else -# define ACTUAL_NR_IRQS NR_IRQS -#endif - - extern void disable_irq(unsigned int); extern void disable_irq_nosync(unsigned int); extern void enable_irq(unsigned int); @@ -542,9 +538,6 @@ extern int ipr_irq_demux(int irq); extern int ipr_irq_demux(int irq); #define __irq_demux(irq) ipr_irq_demux(irq) - -#else -#define __irq_demux(irq) irq #endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */ #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \ @@ -557,18 +550,35 @@ extern int ipr_irq_demux(int irq); #define INTC_ICR_IRLM (1<<7) #endif -#ifdef CONFIG_CPU_SUBTYPE_ST40STB1 +#else +#include <asm/irq-sh7780.h> +#endif +/* SH with INTC2-style interrupts */ +#ifdef CONFIG_CPU_HAS_INTC2_IRQ +#if defined(CONFIG_CPU_SUBTYPE_ST40STB1) +#define INTC2_BASE 0xfe080000 #define INTC2_FIRST_IRQ 64 -#define NR_INTC2_IRQS 25 - +#define INTC2_INTREQ_OFFSET 0x20 +#define INTC2_INTMSK_OFFSET 0x40 +#define INTC2_INTMSKCLR_OFFSET 0x60 +#define NR_INTC2_IRQS 25 +#elif defined(CONFIG_CPU_SUBTYPE_SH7760) #define INTC2_BASE 0xfe080000 -#define INTC2_INTC2MODE (INTC2_BASE+0x80) - -#define INTC2_INTPRI_OFFSET 0x00 +#define INTC2_FIRST_IRQ 48 /* INTEVT 0x800 */ #define INTC2_INTREQ_OFFSET 0x20 #define INTC2_INTMSK_OFFSET 0x40 #define INTC2_INTMSKCLR_OFFSET 0x60 +#define NR_INTC2_IRQS 64 +#elif defined(CONFIG_CPU_SUBTYPE_SH7780) +#define INTC2_BASE 0xffd40000 +#define INTC2_FIRST_IRQ 22 +#define INTC2_INTMSK_OFFSET (0x38) +#define INTC2_INTMSKCLR_OFFSET (0x3c) +#define NR_INTC2_IRQS 60 +#endif + +#define INTC2_INTPRI_OFFSET 0x00 void make_intc2_irq(unsigned int irq, unsigned int ipr_offset, unsigned int ipr_shift, @@ -577,13 +587,16 @@ void make_intc2_irq(unsigned int irq, void init_IRQ_intc2(void); void intc2_add_clear_irq(int irq, int (*fn)(int)); -#endif /* CONFIG_CPU_SUBTYPE_ST40STB1 */ +#endif static inline int generic_irq_demux(int irq) { return irq; } +#ifndef __irq_demux +#define __irq_demux(irq) (irq) +#endif #define irq_canonicalize(irq) (irq) #define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq)) diff --git a/include/asm-sh/kexec.h b/include/asm-sh/kexec.h new file mode 100644 index 000000000000..9dfe59f6fcb5 --- /dev/null +++ b/include/asm-sh/kexec.h @@ -0,0 +1,33 @@ +#ifndef _SH_KEXEC_H +#define _SH_KEXEC_H + +/* + * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return. + * I.e. Maximum page that is mapped directly into kernel memory, + * and kmap is not required. + * + * Someone correct me if FIXADDR_START - PAGEOFFSET is not the correct + * calculation for the amount of memory directly mappable into the + * kernel memory space. + */ + +/* Maximum physical address we can use pages from */ +#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL) +/* Maximum address we can reach in physical address mode */ +#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL) +/* Maximum address we can use for the control code buffer */ +#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE + +#define KEXEC_CONTROL_CODE_SIZE 4096 + +/* The native architecture */ +#define KEXEC_ARCH KEXEC_ARCH_SH + +#ifndef __ASSEMBLY__ + +extern void machine_shutdown(void); +extern void *crash_notes; + +#endif /* __ASSEMBLY__ */ + +#endif /* _SH_KEXEC_H */ diff --git a/include/asm-sh/machvec.h b/include/asm-sh/machvec.h index 3f18aa180516..550c50a7359e 100644 --- a/include/asm-sh/machvec.h +++ b/include/asm-sh/machvec.h @@ -18,44 +18,37 @@ #include <asm/machvec_init.h> struct device; -struct timeval; -struct sh_machine_vector -{ +struct sh_machine_vector { int mv_nr_irqs; - unsigned char (*mv_inb)(unsigned long); - unsigned short (*mv_inw)(unsigned long); - unsigned int (*mv_inl)(unsigned long); - void (*mv_outb)(unsigned char, unsigned long); - void (*mv_outw)(unsigned short, unsigned long); - void (*mv_outl)(unsigned int, unsigned long); - - unsigned char (*mv_inb_p)(unsigned long); - unsigned short (*mv_inw_p)(unsigned long); - unsigned int (*mv_inl_p)(unsigned long); - void (*mv_outb_p)(unsigned char, unsigned long); - void (*mv_outw_p)(unsigned short, unsigned long); - void (*mv_outl_p)(unsigned int, unsigned long); - - void (*mv_insb)(unsigned long port, void *addr, unsigned long count); - void (*mv_insw)(unsigned long port, void *addr, unsigned long count); - void (*mv_insl)(unsigned long port, void *addr, unsigned long count); - void (*mv_outsb)(unsigned long port, const void *addr, unsigned long count); - void (*mv_outsw)(unsigned long port, const void *addr, unsigned long count); - void (*mv_outsl)(unsigned long port, const void *addr, unsigned long count); - - unsigned char (*mv_readb)(unsigned long); - unsigned short (*mv_readw)(unsigned long); - unsigned int (*mv_readl)(unsigned long); - void (*mv_writeb)(unsigned char, unsigned long); - void (*mv_writew)(unsigned short, unsigned long); - void (*mv_writel)(unsigned int, unsigned long); - - void* (*mv_ioremap)(unsigned long offset, unsigned long size); - void (*mv_iounmap)(void *addr); - - unsigned long (*mv_isa_port2addr)(unsigned long offset); + u8 (*mv_inb)(unsigned long); + u16 (*mv_inw)(unsigned long); + u32 (*mv_inl)(unsigned long); + void (*mv_outb)(u8, unsigned long); + void (*mv_outw)(u16, unsigned long); + void (*mv_outl)(u32, unsigned long); + + u8 (*mv_inb_p)(unsigned long); + u16 (*mv_inw_p)(unsigned long); + u32 (*mv_inl_p)(unsigned long); + void (*mv_outb_p)(u8, unsigned long); + void (*mv_outw_p)(u16, unsigned long); + void (*mv_outl_p)(u32, unsigned long); + + void (*mv_insb)(unsigned long, void *dst, unsigned long count); + void (*mv_insw)(unsigned long, void *dst, unsigned long count); + void (*mv_insl)(unsigned long, void *dst, unsigned long count); + void (*mv_outsb)(unsigned long, const void *src, unsigned long count); + void (*mv_outsw)(unsigned long, const void *src, unsigned long count); + void (*mv_outsl)(unsigned long, const void *src, unsigned long count); + + u8 (*mv_readb)(void __iomem *); + u16 (*mv_readw)(void __iomem *); + u32 (*mv_readl)(void __iomem *); + void (*mv_writeb)(u8, void __iomem *); + void (*mv_writew)(u16, void __iomem *); + void (*mv_writel)(u32, void __iomem *); int (*mv_irq_demux)(int irq); @@ -66,6 +59,9 @@ struct sh_machine_vector void *(*mv_consistent_alloc)(struct device *, size_t, dma_addr_t *, gfp_t); int (*mv_consistent_free)(struct device *, size_t, void *, dma_addr_t); + + void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size); + void (*mv_ioport_unmap)(void __iomem *); }; extern struct sh_machine_vector sh_mv; diff --git a/include/asm-sh/mman.h b/include/asm-sh/mman.h index 3ebab5f79db7..693bd55a3710 100644 --- a/include/asm-sh/mman.h +++ b/include/asm-sh/mman.h @@ -35,6 +35,7 @@ #define MADV_SEQUENTIAL 0x2 /* read-ahead aggressively */ #define MADV_WILLNEED 0x3 /* pre-fault pages */ #define MADV_DONTNEED 0x4 /* discard these pages */ +#define MADV_REMOVE 0x5 /* remove these pages & resources */ /* compatibility flags */ #define MAP_ANON MAP_ANONYMOUS diff --git a/include/asm-sh/mutex.h b/include/asm-sh/mutex.h new file mode 100644 index 000000000000..458c1f7fbc18 --- /dev/null +++ b/include/asm-sh/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include <asm-generic/mutex-dec.h> diff --git a/include/asm-sh/ptrace.h b/include/asm-sh/ptrace.h index 0f75e16a7415..792fc35bd624 100644 --- a/include/asm-sh/ptrace.h +++ b/include/asm-sh/ptrace.h @@ -91,6 +91,16 @@ struct pt_dspregs { #define instruction_pointer(regs) ((regs)->pc) extern void show_regs(struct pt_regs *); +#ifdef CONFIG_SH_DSP +#define task_pt_regs(task) \ + ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \ + - sizeof(struct pt_dspregs) - sizeof(unsigned long)) - 1) +#else +#define task_pt_regs(task) \ + ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \ + - sizeof(unsigned long)) - 1) +#endif + static inline unsigned long profile_pc(struct pt_regs *regs) { unsigned long pc = instruction_pointer(regs); diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h index 28a3c2d8bcd7..bb0330499bdf 100644 --- a/include/asm-sh/system.h +++ b/include/asm-sh/system.h @@ -57,6 +57,16 @@ last = __last; \ } while (0) +/* + * On SMP systems, when the scheduler does migration-cost autodetection, + * it needs a way to flush as much of the CPU's caches as possible. + * + * TODO: fill this in! + */ +static inline void sched_cacheflush(void) +{ +} + #define nop() __asm__ __volatile__ ("nop") diff --git a/include/asm-sh/thread_info.h b/include/asm-sh/thread_info.h index 46080cefaff8..85f0c11b4319 100644 --- a/include/asm-sh/thread_info.h +++ b/include/asm-sh/thread_info.h @@ -60,8 +60,6 @@ static inline struct thread_info *current_thread_info(void) #define THREAD_SIZE (2*PAGE_SIZE) #define alloc_thread_info(ti) ((struct thread_info *) __get_free_pages(GFP_KERNEL,1)) #define free_thread_info(ti) free_pages((unsigned long) (ti), 1) -#define get_thread_info(ti) get_task_struct((ti)->task) -#define put_thread_info(ti) put_task_struct((ti)->task) #else /* !__ASSEMBLY__ */ diff --git a/include/asm-sh/timer.h b/include/asm-sh/timer.h new file mode 100644 index 000000000000..dd6579c0b04c --- /dev/null +++ b/include/asm-sh/timer.h @@ -0,0 +1,42 @@ +#ifndef __ASM_SH_TIMER_H +#define __ASM_SH_TIMER_H + +#include <linux/sysdev.h> +#include <asm/cpu/timer.h> + +struct sys_timer_ops { + int (*init)(void); + unsigned long (*get_offset)(void); + unsigned long (*get_frequency)(void); +}; + +struct sys_timer { + const char *name; + + struct sys_device dev; + struct sys_timer_ops *ops; +}; + +#define TICK_SIZE (tick_nsec / 1000) + +extern struct sys_timer tmu_timer; +extern struct sys_timer *sys_timer; + +static inline unsigned long get_timer_offset(void) +{ + return sys_timer->ops->get_offset(); +} + +static inline unsigned long get_timer_frequency(void) +{ + return sys_timer->ops->get_frequency(); +} + +/* arch/sh/kernel/timers/timer.c */ +struct sys_timer *get_sys_timer(void); + +/* arch/sh/kernel/time.c */ +void handle_timer_tick(struct pt_regs *); + +#endif /* __ASM_SH_TIMER_H */ + |